USX603112394 3112394_Electronic_Computing_Machine_Nov63 3112394 Electronic Computing Machine Nov63

3112394_Electronic_Computing_Machine_Nov63 3112394_Electronic_Computing_Machine_Nov63

User Manual: 3112394_Electronic_Computing_Machine_Nov63

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Nov. 26, 1963

3,112,394

P. B. CLOSE ETAL

ELECTRONIC COMPUTING MACHINE
Filed Dec. 15 1959

103 Sheets-Sheet 1

INVENTORS -P. B. CLOSE1._~_~ COULTER, L. R. 01 TMER, R. P. FAHRENBRUCK,
F. R.GOLDAMMER, L. J. I>IJUlJI'(ICK, E.V. GULDEN! T. P. HOLLORA~!
C. S. JENK INS, L. D. KILHEFFER..I K. Al KINKER, oJ. D. LVONSlN. D. MANOR,
R. P. MARVIN, W. L. MILLER, ~ L. OBRIAN, J. H. RANDA L,
E. M. GARNER, R. O. SATHER, R. L.YOST e. A. B. BRADEN, JR. BY
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Nov. 26, 1963

3,112,394

P.B.CLOSE ETAL
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Nov. 26, 1963

3,112,394

P. B. CLOSE ETAL

ELECTRONIC COMPUTING MACHINE
Filed Dec. 15, 1959

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Nov. 26, 1963

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3,112,394

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15. 1959

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F. R. GOLDAMMER, L. J. GOODRICK, E. V. GULDEN, T. to: HOLLORAN
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R.P. MARVINL . L. MILLER~ P. L. O'BRIAN\.. J. H. RANDALL,
BY
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Nov. 26, 1963

3,112,394

P. B. CLOSE ET AL

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Filed Dec. 15, 1959
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~
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Nov. 26, 1963

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3,112,394

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P. B. CLOSE ET AL

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Nov. 26, 1963

3,112,394

P. 8. CLOSE ETAL

ELECTRONIC COMPUTING MACHINE
1959

51

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F. R. GOLDAMMER, L. J. GOODRICK, E. v. GULDEN, T. r: HOLLORAN
C. S. JENKINS, L. D. KILHEFFER, ~. A. KINKE,,!, J. D. LYONS, N. b• MANOR,
R. P. MARVIN..l W. L. MILLER, P. L. 0 BRIAN, J. N. RANDALL.&.
BY
E. M. GARNEI1, R. O. SATHER, R. L. YOST 8 A. B. BRADEN,JI1.

Nov. 26, 1963

3,112,394

P. 8. CLOSE ET AL

ELECTRONIC COMPUTING MACHINE
Filed Dec. 15, 1959

lO~

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BY
c. S. JENKIPoIJ, L.D. KILHEFFER, K. A. KINKER, J. D. LYONS, N. 0. MANOR,
R.P. MARV.I'I, W. L, MILLER~ P. L. O'BRIAN, J. H. RANDAL,
E. N. GARNER, R.O.SATHER, R.L. YOST a A. B. BRADEN,JR.

THEIR ATTORNEYS

Nov. 26, 1963

3,112,394

P. B. CLOSE ETAL

ELECTRONIC COMPUTING MACHINE
103 Sheets-Sheet 53

1959

FIG.75

I NVENTORS- P. B. CLOSE , J. A. COULTER, L. R. DITMER, R. P. FAHRENBRUCi<,
F. R. GOLDAMMER, L. J. GOODRICK, E.V. GULDEN, T. P. HOLLORAN,
BY
C.S. JENKINS, L. D. KILHEFFER, 1<. A. KINKER, J. D. LYONS, N. D. MANOR,
R. P. MARVIN, W.L. MILLER, P. L. O'BRIAN, J. H. RANDALL,
E. M. GARNER, R.O. SATHER, R.L. YOST a A. B. BRADEN, JR.

Nov. 26, 1963

3,112,394

P. S. CLOSE ET AL

ELECTRONIC COMPUTING MACHINE

FIG.76

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INVENTORS-P. B. CLOSE, J. A. COULTER.t L. R. DITMERI.R, P. FAHRENBRU~CK'
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~
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Nov. 26, 1963

3,112,394

P. B. CLOSE ETAL

ELECTRONIC COMPUTING MACHINE
1959

lO~

I NVENTORS- P. B. OLOSE,J. A. OOULTER, L. R. DITMER, R. P. FAHRENBRUOK,
F. R. GOLDAMMER, L. J. GOODRIOK, E.V. aULDEN, T. P. HOLLORAN,
BY
O. S. JENKINS, L. D. KILHEFFER, K. A. KINKER, J. D. LYONS, N. D. MANOR,
R. P. MARVIN, W. L. MILL ER, P. L. O'BRIAN, J. H. RANDALL
E. M. GARNER, R. O. SATHER, R. L. YOST a A. B. BRADEN, JR.

Sheets-Sheet 55

Nov. 26, 1963

P. B. CLOSE ET AL

3,112,394

ELECTRONIC COMPUTING MACHINE
Filed Dec. 15, 1959

103 Sheets-Sheet 56

FIG.78

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C. S. JENKINS, L. D. KILHEFFER, K. A. KINKER I.. J. D. LYONS, N. b. MANOR,
R. P. MARVIN.! W. L. MILLER, Po L. O'BRIAN, J. H. P'lANDALl:.
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Nov. 26, 1963

3,112,394

P. B. CLOSE ET AL

ELECTRONIC COMPUTING MACHINE
Filed Dec. 15, 1959

103 Sheets-Sheet 57

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BY
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~
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Nov. 26, 1963

3,112,394

P. B. CLOSE ET AL

ELECTRONIC COMPUTING MACHINE
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Nov. 26, 1963

P. B. CLOSE ET AL

3,112,394

ELECTRONIC COMPUTING MACHINE
15. 1959

103 Sheets-Sheet 59

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R. P. MARVIN...! W. L. MILLER, P. .0 BRIAN, J. H. RANDALL,a.
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Filed Dec. 15. 1959

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BY
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R. P. MARVIN, W.L. MILLER, P. L. dBRIAN, J. H. RANDALL,
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P. 8. CLOSE ETAL

3,112,394

ELECTRONIC COMPUTING MACHINE
Filed Dec. 15. 1959

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C.S. JENKINS, L.D. KILHEFFER, K.A. KINKER. J. O. LYONS. N. D. MANOR,
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R. P. MARVIN, W. L. MILLER~ P. L. O'BRIAN. J. H. RANDALL1.
BY
E.M.GARNER, R.O. SATHE", R. L.YOST a A. B. BRADEN. JR.

103 Sheets-Sheet 69

Nov. 26, 1963

3,112,394

P. 8. CLOSE ETAL

ELECTRONIC COMPUTING MACHINE
Filed Dec. 15, 1959

103 Sheets-Sheet 70

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N. D. MANOR. R. P. MARVIN.
W. L. MILLER. P. L. O'BRIAN.
J. H. RANDALL. E. M. GARNER.
R. O. SATHER, R. L. YOST a
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E. M. GARNt.", R.O. SATHER, R. L. YOST a A. B. BRADEN, JR.

Nov. 26, 1963

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Filed Dec. 15. 1959

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R. P. MARVIN, W. L.MILLER, P. L. O'BRIAN, J. H. RANDALL.
E. M. GARNER, R. O. SATHER, R. L. YOST a A. B. BRADEN, JR.
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U0DRICK E. V. GULDEN, T. I': HOLLORAN~.
C. S. JENKINS, L D. KILHEFFER, k. A. KINKER] J. D. LYONS N. D. MANOR,
R. P. MARVIN, W. L.MILLER, P. L. 0' BRIANl . H. RANDAL,
L
BY
E. M. GARNER, R. O. SATHER, R. L. YOST a A. B. BRADEN, JR.

Nov. 26, 1963

APN

p.e.CLOSE ETAL
ELECTRONIC COMPUTING MACHINE

3,112,394
103 Sheets-Sheet 89
77

154

T53
DE2

DR
IN4

RLR

INVENTORS-P. B. CLOSE... J. A. COULTER, L. R. DITMEf!, R. P. FAHRENBRUCK,
F. R. GOLDAMMER L.J. "OODRICK E.V. GULDEN T. t': HOLLORAN
C. S. JENKINS, L. O. KILHEFFERLi(~. KINKER, J. D. LYONS, N. D. 'MANOR,
R. P. MARVIN ... W. L. MILLER..! P. . 0 BRIAN, u. H. RANDALL
BY
~~?<='i!!U.e;,.~~'4./
E. M. GARNE", R. O. SATHE", R. L. YOST a A. B. BRADEN, JR.

Nov. 26, 1963

3,112,394

P. B. CLOSE ETAL

ELECTRONIC COMPUTING MACHINE
103 Sheets-Sheet 90

Filed Dec. 15. 1959

FIG. 101
MOD

H3

TS2

PR2

H2

H4

~--------~~~--------------------------~

INVENTORS- P. B. CLOSE, J. A. COULTER, L. R. DITMER, R. P. FAHRENBRUCK,
F. R.GOLOAMMER,L.J.GOODRICK, E.V. GULDEN, T. P. HOLLORAN,
BY
O. S.JENKINS, L. D. KILHEFFER, K. A. KINKER, J. D. LYONS, N.D. MANOR,
R.P. MARVIN, W. L. MILLER, P. L.O'SRIAN, J.H. RANDALL,
E.M.GARNER, R.O.SATHER, R.L.YOST a A.B. BRADEN, JR.

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Nov. 26, 1963

3,112,394

P. 8. CLOSE ET AL

ELECTRONIC COMPUTING MACHINE

Filed Dec. 15. 1959

lKINS, L.a. KILHEFFER, K. A. KINKER, J. D.LYONS, N. D. MANOR,
R. P. MARVIN, W. L. MILLER, P. L. O'BRIAN, J. H. RANDALL,
E. M. GARNER, R. O. SATHER, R. L. YOST a A. B. BRADEN

Nov. 26, 1963

3,112,394

p, B. CLOSE ET AL

ELECTRONIC COMPUTING MACHINE
Filed Dec. 15, 1959

103 Sheets-Sheet 100

FIG. 107 B'

'------_-09+

'-----------".

sro

lNVENiORS-P. B. CLOSEJ. J. A. COULTE~} L. R. DITMER\ ,R. P. FAHRENBRUCK,
F. R.GOLOAMMER, L. J. "OO~ICK, E. v. GULDEN. T. P. nOLLORAN",
C. S. JENKINS, L. D. KI LHEFFER. K.~. KINKER} J. D. LYONS, N. I).MANOR,
R. P. MARVIN..!. W. L. MILLER..t F? L. 0 BRIAN, .... H. RANOALL.,
BY
~%:::~'e4,~~:tE. M. GARNEI'(, R. O. SATHEI'(, R. L.YOST E\ A. B. BRADEN, ",R.

Nov. 26, 1963

3,112,394

P. 8. CLOSE ET AL

ELECTRONIC COMPUTING MACHINE
Filed Dec. 15. 1959

FIG.107C

ECW-02

103 Sheets-Sheet 101

FIG.107E
SHF-04

MI

•+

MA

08M(4)

t

RLR

J
r
H2t..SA(1l

+ 0---------,

r

Ht~J=--H4-l

-RI

t

ARO

H5

Pt9
SA(2)

+

58(1 ) 1 - - - - - '

O+R

AM

t

5TO

FIG. 107 F
CMA-05

INVEN'roRS-P. B. CLDSE ....~_~ COULTER""L. R. DITMER, R P. FAHRENBRUCI<,
F. R.GOLDAMMERbL.J. GuulJrdC~... E. V. ~ULDEN, T. P. HOLLORA~1
I
C. S. JENKINS, L. • KILHEFFER ",. ~.KINKER~ J. o. LYONS N. D. MANOR,
R. P. MARVIN... W. L. MILLER...! P. l . 0 BRIAN, ". H. RANDALl ,
BY ~61':~C:;'::::OWl!lOo"1::=l!~~
E M. GARNE,.;, R. O. SATHE,.;, R. L. YOST a A. B. BRADEN, JR.

Nov. 26, 1963

3,112,394

P. B. CLOSE ETAL

ELECTRONIC COMPUTING MACHINE
Filed Oec. 15. 1959

FIG.I07G
MB-06

103 Sheets-Sheet 102

FIG.I07 J FIG. 107M
SUB-09

MOO-12

M~0J

MA

MA

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.
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-t~.

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FIG.107L

PR2

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.+ -t

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t
RAO
t
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t
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t

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ADD-OS

MUS-13

MI

t
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FIG.I07N

Q
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t
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t

S8t2)

~

DR--..J

OBN(2)'=+CPM

tot

I

STO~

STO

COULTE~1

FAHRENBRUCK.~/J
Vl'

INVENTORS-P. B. CLOSE.lL!.
L. R. DITMER. R. P.
F. R. GOLDAMMER L. J. IWUURICK, E. v. GULDEN T. 1? HOLLORAN,
C. S. JENKIN$, L. b. KILHEFFER." K. A. \<1 NKER. J. b. LYONS, N. D. MANOR,
R. P. MARVIN.&. W. L. MILLER, r: L. 0 BRIAN, J. H. RANDALL,
BY
E. M. GARNE". R. O. SATHER. R. L. YOST a A. B. BRADEN, ..R.

.
THEIR ATTORNEYS

~

Nov. 26, 1963

P.

3,112,394

e. CLOSE ETAL

ELECTRONIC COMPUTING MACHINE
Filed Dec. 15. 1959

FIG.I07P

103 Sheets-Sheet 103

FIG.I07Q

FIG.I07S
EPT-17

DIV-14

CFM-15

MI

MI

MI

MA

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t

t

•
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MtJ

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+

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5TO-5

+

e

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MI

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++

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10(1)

R05

IN4

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FIG.I07R

MA

-

AI=-----L0

AS

R5B

~

OB N (J)

++
5TO-4

COUL~,

=----,

t

5TO-5

INVENTORS-P. B.CLOSE, J. A.
L.R.DllMER, R. P. FAHRENBRUCK,
F. R. GOLDAMMER L. J. GOODRICK, E. v. GULDEN, T. P. HOLLORAN
C.S.JENKINS, L.B. KILHEFFER, K.~. KINKER, J. D. LYONS, N.D.MilNoR.
R. P. MARV!!t w. L. MILLER..!. P. L. 0 BRIAN, J. H. RANDAlL.
BY
E. M. GARNUI, R. O. SATHE", R. L. YOST a A. B. BRADEN, JR.

OBM(2)~

++

5TO-4

t

5TO-5

~~
•
~

THEIR ATTORNEYS

United States Patent Office

31 112,394.
Patented Nov. 26, 1963

1

2

3,112,394

whlcl: not only utilizes the data carried by the ledger card
media. and other bpnt media in addition to key-board
entry ,bta to perform all calculations invo.lvc.d in a computing op2mtion, but additionally, as an mCldent. to t?e
CO~'pl!tjng opera lion, UPti8tcs the ledger card data m bo,h
its rrintcd hum~m,readab!e ~lHd its magnetically·rc:::orded
m:~ch;ne-readable sections ~:id is thereby capable of producing a printed journal s:1cet and other output documen~s, if desired.
A further object of the present invention is to devise a
novel Jaw-cost compllter which is capable of suppressing
all insignificant digits while updating the ledger card data
in both its printed human-readable and magneticallyr~cordcd mac11inc-rcadable sections.
And another object of the present invention is to devise a new a;ld improved low-cost transistorized computer
which docs not require air conditioning and which utilizes
inexDcnsivc resistor logic ;;nd transistor flipflop control
circt;itry which perform multi;:"le functions and thus maint~in the cos~ of the conl~put(.r at a rnini[num.
The features of the present invention which are believed to be novel are set forth with particularity in appended clail11~. The organiza:ion and manner of operation of the invention, to:;clher with further objects and
advantages thereof. mil)" best he understood by reference
to the foliowing dcscription taken in connection with the
ilccompanying drawings, in the several figures of which
like reference characters identify like elements, and in
\vhich:
FIG. 1 is a perspective vicw of tile novel co~puter consirucled in accordance with the present invention;
r;IG. 2 is a plan view of the keyboard of the accounting macbinc portion of the computer;
FIGS. 3A and :'\ B, when joined together at the dashed
l;ncs, form a longitudinal cross-sectional view of the account'ng machine portion of the computer;
FIG. '-1- is a plan view, partly in section, of the mechanism utilized in acconlalj(~e with the present invention for
stopping the amount n:cks of the accounting machine portion;
FIG. 5A is a plan view showing the conductor pattern
disposed on the top surface of the printed-circuit board
utilizell for determining the stopped positions of the
amount racks;
FIG. 58 is a pbn vicw showing the conductor paticrn
disposed on (he bottom surface of the printed-circuit
board utilized [or determining the stopped positions of
[he amount r[,cks;
FIG. 5 B is a plan view showing the conductor pattern
disposed on the bottom surface of the printed-circuit
bom'd shown in FIG. SA.
FIG. 6 is an exploded vkw of one of the variol1s solenoid aCiuatcd mechanisms utilized for selectively stop-

ELECTRONIC COMPUTING lI1."
Three selective carriage-return keys "RETURN-1,"
"RETURN-2" and "RETURN-3" are located on the
right siJe of the typewriter keyboard to eITcct return of
th~ carriage to a prcdctennincd stop position, w;ih Cf
I'. ithout vertical sp:lcing of the platen.
The position at

3,112,394

10
which the carriage returns, dcpenus upon the length of
inserts proviJcd ia each of the c3rriage "stors," illustrated as reference numeral 73 in FIG. 3A. Depression
of each of the typ~wri,cr carriage RETURN keys, raises
a u~'ct~.Irn sto;l lever" to a given height so that -it ~ontact3
the d~sjrcd '~c~HTiage return insert" in the carri~1f:; stop,
to halt the (rare! of the nrriagc. Vertical sp3~in~ or
the n;atcn, um:cr centrol of the c~rria;.;:c RFTUR:-l keys,
is clTec!cd by papt:[ feeJ slides 18, 19-, and 20, each located at the side of a difrerent one of the RETUR:-l keys.
When one of slides 18 thru 20 is moved toward the
front of the mDchin~, it cO~lples the corresnonding RETURN kev with vertical space key "VERT" in a m~nner Stich that tkpre:·.sion of key "VERT" C;}USCS the platen
Ie be "raced vUtiC;1Uy in nr\Jitio!1 to b;;in,,! returned to a
predetermined position. However, lhcpJ1:'cr fe~d key
"VERT" ·may be used to vertically space the platen one
or more position~ [Dr each dC;Jression thcri.:of. Loc<\ted
dir'~'2tly below th·; ('~'rri~\gc return keys is a typewriter
tatJlllation key ''TAD'' w:lich, when depressed, C[lUSCS the
carria::;e to t:::bu13l'~ to a particular column as selected
by a corresrond:;~,! tYi'~''''riter stop. It ,is to be appreei:l.ted that :'.11 carri::"e ll'0tinn to hereinafter be c\(:.scribed
is der;endcnt lIpen th~ felet ,hilt the c8lTiage is closeu.
At the left of the 8mo,mt k~yboilrJ is a typewriter
ribbon control lever 21. With Jewr 21 in th·~ center or
nCf>1l13l position. the typewriter prints in black; when in
th~ lower position, the t~'pewrilcr prints in red unlil the
lever is manually restored to normal; ~md, when in the
upper llosltien, the type'Nriter prints in red until cOnltj)c~
tion of the next oper:lti,m of the accounting machine, at
'Nhich time the lever is automatically reslored to its central
t"'(lsitlon. Anothtr ribhon control lever, not ~,hown, is
located on the top of th~ n~achine under th~ pI Cltcl1.
\'/flcn tbjs lc"/er is in its fon:vanJ 'Po~;ition\ norn:z) 'Jlack
printing of amoul!ts is effected c:-:.cept during a subtract
opcra:ion in the:;; 1 totalizer and dnring a credit b:llnn('e
op;:ration which a;"e 8utomatically rrinted-out in red.
y'\::hen in its rCHr\I/~1t·,J positi'Jl1. typewriter ribtG~ control
k-,,-'.ci" 21 is rendered cflec1ive (0 control the nmount printing o;.'cration, the s;::rne .:lS on tYPc\-\Titer printing.
4.

A1120Unl

l:'cyboard of A ccolfflting Alachine

The amount KeyboarJ cO,lsist;; of tcn rows of Keys for
enlering aIDe-t'llt'; into th~ ;!;ccounting machine totalizers
i'Jld/or into the computer m(;mory. Each amoUilt row
consists of nirh: ~.cY'') nlllnbercd franl "1" thl"u 9," zeros
(lnd p1.1nClllntiul1 heing print2d auto111[tt-ioalJ):. ..A,ny del)r~sscJ ~,n~oullt key i:; restored to its original position
"I hen ~~no; her ~~~ljOlint key in the sanl':; ro\\/ is de'Pi'e~s~d!
and. all depressed amnunt keys are ;jmultancously restored Ur,(lfl ucpres'ion of the rel~ase key "R EL" which
is 10c2.ted immedbtcly to the right of the ""BALANCE-I"
key in the lower left corner of the keyboard. This rel'2~!'-;c key is Lltil:LCU to restore those keys dcprc:'sed in
CT!'O:'~ allu espcci~1.Hy those keys lof;atcd in the control
i:~c;tion on the I'cft side or the kcybo;Jrd, which are not
r~;c;lsed by [I.nothcr key jn thc sZ!tl1e roY'?,
)~ny depressed.
Cln1(;Unt l:c}, or keys, is automatically restored upon com'PietiDn of eJ.ch rnnchine Dperntion, excC:!it vi'hen "'repeat
entry" is called for, either by fl. stop contrcl or by depression ot repeat key "REP" which ,is located j;1.1mctliately
':0 tile 'ri:,h( of the numb:!" '"5" key in tI~e control kcybo~rd section. 'I hose keys lcc~led 011 the left side of
the kcyLo:lI'd, stIch as date keys l thn! 9 and I thru 3
l'c"rectiveiy loetted in the e;cventh D.nd twelfth rows, llt"e
st.1.yu{)\vn" keys \vhich i1re not rel;;:1s:cd during each 111achine open~ti0n but arc rcle:tsed onlY by depression of
another key in that particular row, or by deprc:;sioll of a
special release key '~REL:' losatcd above ti1C namber ~~3"
in the t',vcHlli row. A non-repe"t (bte key "~ON REP"
is located directly above the special re!ease key "REV'
;lnG, when dqo;-c;ssed, effects nen-printing of the year
d~tc \vhen dcnressed and is restored cnly by derression
of th'~ d:tte r~lease luoy.
10

H

Depression of tabllbting Ley "TAB," loc::ted in the
hnvcr right-hand COI"l:er or t£18 :..ilnount kc)/boilrd, C~}iJSeS
the C;]rri:1gc to be t:lbllialed ,., the !cft until the movement
thc-rcc,f i-; arrcsL',J by a scH:.h1c stop 0'n tbe c:lrriage.
5- I'lv:, "Ti\B" key provides a ('onvenient nl~rlns for tabulating: the c[)ri'i~g~ to a dC5';rcu coh; lnn;Q' position \vithout
the flc';:::-:::"';ity of llsing ;) ~'r.-Jo!or··b:lr"' orcr:ttion, but is
I101~n1ally not uSf~J as [l f;:,.rt uf a ro:;t(n:; :~>.:quenc·~.
A
carriagt;-opening key "C AI:';:' OrIeN" is located at the
10 extreme upper ri:iht-hand (erner of the keyboard and,
u!~cn derlrc,'~sioI1 th~rcof, scic ~lj·.. ciy inilj~!l,~s opening and
c1osin;; oper~ltions of til:; calTi:;g~ when the carri~ge is
Icc2tcd in "home" position. A sinzle depression of the
'carriag,':-opcning key ('~=:.u~cs the cRrri:J~~e to open If it is
15 closed, or to clo,c if it is open. The key doc,; not renuin
dl.)\vn \':h,;.;n jj.;'::'l'e:-;'~~d, ~l~t in~t(;ad is restored to its original rO~ilioll ans," each uepre:;sio".
A carriag(>return key "C!\R. RET' is located immedi~tely below tbe C.1ri"i2 tC opening key nncl, when de20 pressed, cfrccls return of the carriage to a given stop
r,'l~~il.iDn ~v;'h~ch is deternlillecl by :;c1ective plaCCillcnt of a
sl1;t2b!e carriage-return insclt in the pr.rticuhlr stop th:lt
cOiilrois the position to be ,elected if the carriage is
not open. The carriage-return key is "locked-out" while
25 t!lC Inachine is opcrJ.tlng H!1d. convers~ly, mnchine opcration is locked-out if the carria::;e-return key is derressed and held down.
A carriage-release key "CARR REt," locClt8d on the
ri~ht: side of tlJe keyboard directly above UPP':-f-IllotOf30 bar 23, functions in three diilerent way;;: if fully depressed
anu b~ld dovm while the 'cJrria:,c dr;vin; mc:ms is deen~rgizcd, the carriage is un;oc:~ed and tblls permiltcd to
be manu:lJ1y moved in either direction te :,ny desired position; when partially Gept<~ss['J. the c:\:Ti~:gc c~capcnl~nt
3.3 mechanism is relcrelc,,~.e key thus permits man40 t:21 or driven movement of the carriage to :l1ly desired
po:,ition without interruption by Ion-lard or rcverse-tabul;::ling stops. '!'he carriage-rc1ca~.c key is t~elf ,restoring
?nd functions only while ckpre,;:'cd, anJ wh::n ailowcll
to resume its initial position, etke,s cnpgemcnt of the
45 e<;capement mechanism to hold the carriage at that position.
Non-automatic key "NON-AUTO," located at the right
of upper-motor-bar 23, is a stay-down key w:iich, when
depressed, remRins down nntil reicascd by " non-automatic
[;0 rc!ca"c key "REL," located dir~ctly bc10w it. The nonalllom~ltic key disables the  of
the middle"motor-bar provide the ability to make multi;Jle
postings where the carria,oc must altern:ltely tabulate ;~nJ
rctuOll between two posting cohll1Jns or between t;1c reference column and the po,;ting column.
A tonch or hold d;;pression of lower-motor-bar 28 takes
precedence over and thus disables paper feed, carrj~ge
return and certain types of stop-controlied <::arriagc tabulation, regard;css of the position of the molor-b~]' con'rol
lever. This disabling ability permits the lovla-ll1otor-i'~:r

12

[;

10

15

20

25

30

:':;i

,10

,Hi

50

55

GO

65

70

75

to effect a "skip-tabubte" machine operation simply by a
touch or hold operation thereof. It also provides the
means for skipping columns in which no postings arc to
be ml:dc and to skip operatio!1s whicb are not required
on every posting run; it permits carriage tab alation when
a stop has established non-tabubtion control; and it take~
precedence over many functions of the stop, thus providing variable control over paper feed and carriage tabulation and return,
As previously stated, motor-bar control lever 29 c.fIects
the fUl:.ction of the middle-molor-bar only. When the
lcver is in its upper position as shown, the middle-motorbar fun::tions in a normal manner, whcreils, when in its
middle and lower positions, normal operation of only
the middle-motor-bar is modified.
The coutml portion of the accounting machine keyboard
is located to the left of the amount section and includes
the tlsunl totalizer selecting und control keys. For example, "ADD 1" and "SUET 1" keys rcspectively select
totalizer #: 1 L-J~ A9L
(FlG. 4) from computer controlled means at particular
times durin3 their movement in the setting direction, each
of the "mollnt racks is stopped and thus po;;itioned at
any digital position from "0" to '"9" and each is then
effective to control printing of the numerical digit correspondin~ to the digital po,ition of that particular amount
rack as previously de~cribed. "Vith ,the exception of th~
rightmost one of teeth 101, all of the teeth on rack extension 98 arc equally spaced by a distance of approximately five thirty-seconds of an incb. However, in order
to provide a suitab;c clearance of approximately twentyfivc thousandths of an inch between rack-stopping pin
133 ,'me! the ri",!llmost or "0" digit tooth during insertion of the pin, t]le spacing between the "0" digit tooth
,tIld the 8djacent "1" digit tooth is five thirty-seconds less
tw(,nty··uve thousDndths, or approximately .132 inch.
A laminaced ~:pring buffer mechanism (FIG. 3B) comprisin::; top, center, and bottom L-shaped leaves 142, 143,
and 144, respectively. is affixed to the upper surface of
cross-bar 82 by means of screws 145 threaded therein.
The lower end of each of the depending leg portions of
le"vcs 142 anu 143 has a vertical slot, not shown, centrally
formed therein to accommodate lever arm 136 of the
rack-stopping mech:mism together with rack eXlension 9'3,
to!h of which are slidably position<:d therein. The width
Gf the slot in le"ves H2 and j'13 is fcligJrlly larger t:l~m
L"1e grcalcA thickness of arrn 136 or ra~k ~)8. but i~ nlltch

5

10

15

20

25

30

35

40

45

50

55

GO

G5

70

3,112,394

21
AdJiliomUy, the buffer mechanism is so positioned that
c.lch end Ot rack-stopping pin 138 is in close proximity 10
the front surhcc of leaf 1-12. As a result, !eaves H2
and 143 provide a support for the backside of pin 13::
to absorb tile force of the blow exerted by the rack teeth
on pin 138 when the rack is suddenly stopped thereby.
However, it has been found that when the rack is traveling
at maximum velocity in the rearw::lrd setting direction
and is brought to a sudden stop by pin 138 being inserted
in front of one of teeth 101, the lower ends of !eaves
142 and 143 are delkcteJ to the right as viewed in
FIG. 3B. When the rack is suddenly brought to a standstill, the depending legs 'Of leaves 142 and 143, due to
the energy stored therein, attempt to resume their original
position. As a result, they tend to overshoot their mark
by deflecting to the left and thus attempt to drive the
rack in the opposite direction. To minimize this !I;l(iesirable effect, a screw 146 is slid ably mounted in aligned
holes formed in leaves 142 and 143 and is threaded in
leaf 144. A pressure setting spring 147 is interposed between the head of screw 146 and washer 148 positioned
against the front face of leaf 142. Thus, by sui!clhle
adjustment of screw 146, a suitable friction damping effect
is provided the rack-stopping mechanism anJ rebounding
of the racks is minimized.
As previollsly described, during a rack setting operation,
all non-stopped amount racks travel in unison and in
alignment with the other. Consequently, control means
have been provided whereby the computer not only (ktects the corresponding digital positions of ali stopped
racks, but, in addition, detects the point-by-point digital
position of all non-stopped racks. With refer~nce to FIG.
4, an eleventh or timing rack 149 is provided havi~lg a
constn;ction and mode of operation exactly the same as
the just-described amonnt and auxiliary racks 49 and 55,
respectively, with the exception that timing rack 149 is
not stoppel\ at any time by' a depressed key on the accounting machin(') keyboard and is not provided with a
solenoid-actuated rack-stopping mechanism. Actually, a
conventional amount and auxi'liary rack are used for this
pllrposeand the row of keys. located on the accounting
machine keyboard and which selectively stop that particular rack when depressed, along with the zero stops
"6 (FIG. 3A) associated therewith, have been removed.
Timing rack 149 is provided with an extension 150 ,11tached thereto by pin 99 and spring clip too, and is essentially of the same general construction as rack extensions
98 with the exception that rack extension 150 does not
have any tceth formed thereon.
With reference to FIG. 7, to::;ether with the partbl
plan view thereof in FIG. R, a fbt ;nd horizont,llly disposed, timing rack comb 151 is welded to the up;:Jcrmost
face of rack cxtension ISO ::mu hilS formed therein eight
rectangular shJped slots IS;! par~Jlel disposed ',vith respect to cne another with their long axes pc.rpcnd:cululy
disposed with respect to the direction of movement of
rack extension 150. An L-shaped br[;c1cet 156 i~ afllxcd
to the upper sl.:dnce of cross-bar 82 by me:ws of screws
157 threaded therein, and a cubic::.l block of insulating
material 153 is attGched to the lower frent face of the
depending leg of bracket 1% by me~ms of screws 151)
threaded in block 158. Block 158 hr,s embeddd there!"
a photocell 160 whose terminal~ are connected to output
terminals 16,1 and adapted to be energized by leads 162
connected to a suit8ble source of electrical energy, not
shown. A further L-shaped bracket 163 is attached to
mounting bar 81 by suitable means, not shown, and h:Js
mounted on the horizontal leg portion thereof, a light
source 164 which is energized by leads HiS connected to
a suitable source of electrical energy, not shown. A horizontally disposed flat plate 166 is fixedly secured to the
lower end of block 15S by suitable means, not shown, al}d
is positioned directly below and parallel with respect to
timing rack comb 151 intermediate light source 164 and
comb 151. Plate 166 has a single rectangular-shaped slot

22
167 formed therein disposed substanti~lly parailel with
respect to, anti of sufficient length so as to partially overInp the slots formcd in cow:' 151. It is evident, therefore,. tint as liming rack 150 is moved from left to right,
5 as viewed, the slots formed in comb 151 sequentially coincide with the slot formed in fixed plate 166, thus seqnentially exposing light source 164 to photocell 160.
For the accomplishment of the desired objectives in
accordance with the present invention, it is desirable that
10 the sequential alignment of slots 152 and 167, from the
rigiltmoc;t to the leftmost of slots 152, be synchronized
with the time 2.t which the non-stopped amount racks
simultaneollsly pass through digital positions number 'T'
thm "8." For example, at the beginning of a rack15 setting operation when all the amount racks are positioned in their number "0" digital positions, the relative
positions of slots 152 with respect to slot 167 are as
shown in FIG. 8.
Howevcr, when the non-stopped
amount racKs arc approaching their number "1" digital
20 positions, slot 167 is also approaching alignment with
the rightmost one of slots 152; when all non-st'Opped
amount racks arc approaching their number '·2" digital
positions, slot 167 is approaching alignment with the
second [rom the rightmost one of slots 152; and so on,
25 twtil ~JI non-stoppcd amount racks are approaching their
number "8" digital positions, at which time ~lot 167 is
approaching the eighth or leftmost one of slots 152.
However, as the just-described solenoid-actuated rackstopping mechanism is not capable of inserting rack30 stopping pin 133 (FIG. 6) in front of the desired one of
rack teeth 101 in a zero amount of time even after the
corresponding solenoid is energized, the computer, hence
the solenoid, must be "warned" or I~otified slightly in advance in order for the rCick-stopping mechanism to be
35 effective in slopping its related mck at the desired digital
po,;ition. For example, it has been empirically determined
that, with a r::;ck traveling at an average velocity of
approximately twenty inches per second, approximately
one-tenth of an inch is sufIicient anticipation for the rack40 stopping mechanism. Consequently, as the tooth pitch
of the amount racks is approximately equal to five thirtyseconds of an inch, slots 167 and 152 are in substantial
alignment approximately two-thirds of a digital position
ahead of the non-stopped amount racks. However, as the
4:) amount racks start with an initial velocity of "zero" and
are therefore traveling at a relatively low velocity when
passing tilWllgh digital positions number "1" and number
"2," and also as the spacing between the first and the
second on~s of rack tc~[h IG1 is approximately twenty50 five thousandths of an inch less than the pitch of the remainin& teeth, as previollsly mentioned, the distance betwecn tbe slots formed in comb 151, at the rightmost end
thereof, are mllch less than the distance between the slots
formed in the leflmost end thereof.
Ideally, the slot spacing should approximate the curve55
plot of rack velocity vs. time. However, due to various
loading conditions of the amount racks occurring during
the setting operation thereof, the exact spacing between
slots are empirically determined. Such an empirical de60 termination is as follows: a satisfactory distance between
slot 167 and the first one of slots 152, counting from right
to left and when in a "0" digit position, is .045 inch; a
satisfactory dist:mce between the second and the third
on;:;s of slots 152 is .162 inch; and the consecutive dis65 tances between the remaining adjacent ones of slots 152
are .164, .153, .157, .153 and .139 inch, respectively,
corresponding to slot distances 3-4, 4-5 5-6 6--7
and 7-8; a slot width of .030 inch ha; been' found
satisfactory.
70
"Vith reference to FIG. 3B, there is shown a mechanical type of memory device which is utilized bv the computer to temporarily store indications of the digital positions of each of the amount racks at the end of the previously-initiated rack-setting opcration. The device then
7G operates suitable output means in the form of a con-

3,112,394

23

24

ventional card or paper tape punching mechanism which
makes a permanent record of all of the sequentbl digital
positions at which the amount racks were stopped during
a programming or computing operation.
Such a memory device consists essentially of a horiZiontally disposed upper switch-basket, indicated generally
as 170, and a horizontally disposed lower switch basket
located directly below switch-basket 170 and indicated
generally as 171. Upper switch-basket 170 consists essentially of a substantially flat, rectangular-shaped and horizontally disposed board 172 composed of a suit::bk e~ec­
trically non-conductive material, such as fiberboard or the
like, and affixed to the underside of cross-bars 173 by
means of screws 174 threaded therein. Cross-bars 173,
in turn, are affixed to side plates 88 by means of scrC'NS
175 which are threaded in the ends of bars 173 as shown
more clearly in FIG. 4. Board 172 is provided with tcn
equally spaced and rectangular shaped slots 176, the long
axis of each slot being in axial alinement with the direction of movement of a different one of the amount racks.
A column of ten pairs of equally spaced and met~l!ic
spring-clips 177 are fixedly secured to an electricaHy nonconductive mounting block 178 and collectivcly form a
unitary assembly of the upper switch-basket. As shown
more clearly in FIG. 12, the lower end of each pair of
spring-clips 177 making-up a column is "snapped in" :md
held by the same one of the rectangular slots formed in
board 172. With reference back to FIG. 3B, crlch column of spring-clips is disposed directly above and oriented
parallel with respect to the direction of movement of a
corresponding amount rack, and the spriag-ciips within
the column arc spaced in a manner such that each pair
is positioned with respect to another pair to correspond
to a different one of the ten digital positions of that particular amount rack. Each of the spring-clips hilS connected thereto an electrical conductor forming a p.dcd
the end of
selected one of each of the uppcr ends of plungers 217
bracket 210. Consequently, it is see,1 t!nt the dcs:rcd
verticJlmovement of lower basket 171 is insured at all 15 and 218 respectively engage studs 215 and 2t 6. Contimes.
s~ql!ently, as a result of such engagement, predetermined
ones of plungers 217 in the left-hand row, and predeIn some instances, operation of th:! card or Flp~r 1:lpe
termined ones of plungers 218 in the right-hand row, are
punching mechanism is required only when the :l~count­
1::oth depressed and latched in their downwardly deflected
ing machine carriage is in ccrtnin colunlnar p~)sitions corresponding to the columnar format of the lediier cards or 20 positions, and, additionally, simultaneously release selectcd ones of previously depressed and latched plungcrs.
business forms in the carriage thereof. Consequently,
When solenoid L47 is de-energized, the switch basket is
operation of the punching mech8nism is additionally conspring-m.e:ed back to its initial st~lrting position. As a
trolled by means of a plurality of switches located at the
result of the basket return, the electrically non-conductive
back of the traveling carriage which are actuated by a
plurality of adjustable stops removably mounted Ol~ a rear 25 tip 228, carried on the lower end of each of the plungers,
engage and thus deflect downwJrdly the topmost ones of
form-bar located on the back of the carria.ce. Such a cara plurality of switch bladcs 229 which are arranged in
riage-position switch mechanism is of the s,:mle gener;:l
twenty rows with each row corresponding to a different
type as that shown and described in eopending application
one of plungers 217 and 218. When the uppermost one
Serial No. 567,411, filed February 23, 1956, by Edgar H.
Sonnanstine, Jr., and assigned to the same assignee ,lS the 30 of switch blades 229 is deflected downwardly, all of the
switch bJades in that particular column are electrically
instant application. Consequently, a detailed description
connected together until solenoid 227 is again energized to
thereof is not deemed necessary to be again given herein
move the switch basket upwardly, as viewed, as previously
in order to obtain a full understanding and a :,precialion
described.
of the present invention.
A substantially V-shaped arm 153 is pivotally mounted
Briefly, however, with reference to FIG. 17, the mecha- ::;5
on stud 154 and supports a roller on tbe upper end therenism includes a substantially C-shaped rear form-bar 212
of which is adapted to eng3gc a projection of plate :::14,
removably mounted on suitahle backets, not shown, which
as shown in dotted li!1es, to rock arm 153 counter-clockare secured to the lower re[lr framework of the c:lrrirrge,
wise, as viewed, and effect actuation of a switching mechathe rear form-bar being essentially of the same general
construction as the front form-bar which is similarly at- 40 nism, indicated generally as SC41, in a well known manner.
tached to the front of the carriage. Rear form-bar 212
\Vith reference to FIGS. 44B and 44D, cam actuated
is slidably supported between rollers 213 and extends subswitching mCide rods 219.
ing projections formed on the underneath side of base
The forward, i.e. upper, end of each of the plungers is 70 65 by means of screws 598 threaded therein. A mountslotted to snugly embrace a suitably slotted guide rou 220,
ing frame 599, in turn, is fixedly secured to the bottom
guide rods 219 and 220 being fixedly secured at their ends
side of plate 597 by means of screws 600 threaded therein
to top plate 221 and a bottom plate, not visible, which 3r~
nnd is adapted to have fixedly secured to the depending
slotted to receive guide rod 222 to form a shiftable fr:lme!e.g thereof, by suitable means not shown, a plurality of
work for supporting plungers 217 and 218. A sUbstantial- 75 switches SC42, SC43, and SC49.

'n

3,112,394

27
As diagrammatic:illy illustrated in F1G. 44G, and, as
ShO"lll by the timing chart of FlG. 87C, for rensons to
become more appnrent herein:,·fter each time main cam
shaft 533 of the mnchinc is rota led clockvvisc through an
arc oE 126 degrees from the starting position as shown
in FIG. 46B, cam 592 engages the movable nrm of switch
SC49 sHch thnt the normnUy-opencd contncts thereof nrc
closed thereby; when the main cam shaft is rotated 168
degrees clockwise from the starting position as sho·llln,
cam 592 additionally engages the movable arm of switch
SC48 such that the normally-opened contacts thereof are
closed and the normally-closed contacts thereof arc
opened thereby; when the main cam shaft is rotated 182
degrees, the movable arm of switch SC49 is released by
cam 592 and the normally-opened contacts thereof resume their initial opened condition; a 213 degree clo~k­
wise rotation of the main cam shaft causes cam 593 to
engage the movable arm of switch SC42 SHch that the
normally-opened contacts thereof are closed thereby; a
224 degree clockwise rotation of the m~ljn cam shaft
causes the movable arm of switch SC43 to be relcB.sed
by cam 592 such that the norm:llly-opened and the normally-closed contacts of switch SC48 are allmved to resume their initial mnditions; and, a 264 degree clockwise
rotation of the main c:lm shaft causes the movable "rm
of switch SC42 to be released by cam 593 such th;;t the
contacts thereof are allowed to resume their initial conditions.
As previously mentioned, due to the incorpomtion of
an overdraft control mechanism in the accounting machine portion of the present computer, true negative totals
are permitted to be selectively printed-out from any of
the tot:llizers therein, all of which is fully described in
the previously referred-to Patent 2,626.,749. ""\lith reference to the fc:gmentary view of FlO. 44f, which ess"ntiallycorresponds to FIG. 47 of the jllst referred-to patcnt,
the overdraft control mechanism includes an overdraft
cam shaft 601 extending tmnsverscly across the machine
beneath base 65 ~nd is jOLlrnaled in brackets 602, only
one of which is shown. which are secured to the underneath side of base 65 by means of screws 603 threaded
therein. Secured to overdraft shaft 601 is a spur gear
6114 which disconnectably engages a similar spur gear,
not shown, mounted on main cam shaft 588 (FIG. 44D).
As fully described in the just referred-to patent, the pitch
diameter of overdraft gear 6(}4 is twice that of the simi!:!r
gear mounted on the main cam shaft of the machine,
thereby causing ovcrdwft eam shaft 601 to be rotated at
one-half the speed of main cam shaft 588 when the latter
is rotated during a machine cycle.
In accordance with the present invention, a pair oJ leaf
switches, indicated generally as SC45 and SC47, are insulated from and fixedly secured to bracket 605 by me:ll1S
of screws 606 threaded therein, bracket 605 being fixedly
secured to bracket 602 by suitable means not shown.
Rotatably mounted on a stud 607 (FIGS. 44C and 44E)
afilxed at one end to bracket 605, are a pair of C3m follower arms 608 and 609 which are respectively spring
biased in a clockwise direction, as viewed in FIGS. 44C
and 44E, by means of springs 610 and 611. Fixedly secured to overdraft cam shaft 601 me a pair of cams 6~2
and 613 which are propcrly positioned on shaft 601 so
os to engage rollers 614 and 615 respectively carried by
cam follower arms 608 and 609. Respectively affixed to
the upper end of each of arms 608 and 609 is one of a
pair of insulating tips 616 and 611 which are adapted to
respectively engage leaf switches SC45 and SC47.
With additional refercnce to the timing chart of FIG.
87C, when main cam shaft 588 is rotated 30 degrees from
the initial starting position thereof, overdraft cam shaft
601 is engaged thereto and is thereafter rotated at onehalf the speed of the main cam sh~.. ft. Thereafter, each
time overdraft shaft 601 is rotated 10 degrees counterclockwise from its starting position as sl;own in Fi;.
44C, cam follower arm 608 is permitted to be rocked

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clockwise by spring 610 due to the decreased diameter
of cam 612 being presented to roller 614. ThLIS, when
arm {lOS is rocked clockwise, the normally-closed cont:lcts
of leaf switch SC-15 :lre opened thereby. E,:ch time overdnit Shelft 601 is rotated 165 degrees counter-clockwise
frem its initial starting position, an increased diameter
c[ cam 6U is prescnteJ to roller 614, and, consequently,
Cuil1 fonmver mm 608 is rocked counter-clockwise and
thereby closes the contacts of switch SC45.
With aJliitional reference to FIG. 4~E, each time overdr:lft Sh,lft 6(;1 is rotated 260 degrees counter-clockwise
from its starting position as shown, the maximum diamctcr of cam 613 is presented to roller 615, and, consequently, cam follower arm 609 is dcllected counter-clockwise sl!~h thllt the normally-opened contacts of leaf switch
,SCi7 are closed thereby. However, each time the overdraft shaft is rotated 290 degrees counter-clockwise from
its startiJlg position, the minimum diameter of cam 613
is prcsented to roller 615 to allow arm 609 to be rocked
clockwise by spring 611, which, in turn, allowcJ the contacts of switch SC47 to resume their undeflccted positions
as shown.
6. Paper Tape PUllch Portion of Computer

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It is to be apprecinted that substantially anyone of the
multitude of commercially available paper tape or card
recording mechanisms is quite easily adaptable to be
utilized by the present computer to provide a permanent
record of all of the sequential digital positions at which
the amount racks of the accounting machine portion
thereof were selectively stopped doing a programming
or computing operation. However, FIG. 44H discloses a
partially cro~s-scctional and fragmentary view of a preferred high speed paper tape recording mechanism so
utilized by the present computer, wbich mechanism is
fully described in copcnding application Serial No.
820,539, filed June 15, 1959, by Richard C. Simmerman
et n1. and assigned to thi.: present nssignee, FIG. 44H of
the present application being substantially identical to
FIG. 1 of the just-mentioned copen ding opplication.
It is to be notcd at the outset that the recording mechanism partially shown in FIG. 44H essentially relates to
that portion of the entire mechanism which is utilized,
together with a common feeding means, for punching a
single hole in the paper tape during each operation thereof. As it is dc:,ired to utilize a transversely oriented
column of eight holes, plL!s one sprocket hole, in a recorJing tape Ivith respect to the travel thereof, and in
accordance with the parlicular code associated with the
punching mechanism, it is to be appreciated that the
complete paper tape recording mechanism, in fact, includes a combination of nine substantially identical ones
of such punching mechanisms shown in FIG. 44H, plus
the single paper tape feeding means.
As shown, side frames 618, only one of which is shown,
form the main supporting structure for the recording
mechanism, side frames 618 being held in a fixed spacedapart rclation:;hip by means of a plurality of cross-bars
including a punch guide block 619, a punched lever
comb 621}, and a punch interposer guide block 621. A
rcct:.mgulf\rly-shaped punch Slipport block 622 is fixedly
secured to one of side-plates 618, by suitable means not
shown, and is provided with a single row of nine bores
formed therethrough, each bore being adapted to have
slid ably disposed therein a punch member 623. Each
of the punch members 623 is provided with a recess located midway its length, into which is disposed one end
of a p;
As shown in rrG. 1, the traveling p~pcr e3rriagc, for
23') threaded in th~ rail 240. i\. plat;cn 2~1 is jOUfn',ld 20 the beforc··de~cribcd accounting machine, consists of a
in tho uppennost ends of s!de-plHl~s 233 and 23.1~ and
framework Ivhieh includes a PJir of end hOllsings 26 t
i:, also journ.,led in hub 242 :clnd 243, which a~e respec\Vith reference to FIG. 17, the end housings 264, only
one cf which is shown, are S~.!flPcrt~.d in a sjxlced and
tively ",.clc:ed or o!herwbe rol drive ('10tor, as shown in the fragmenl;!ry view of ,10 a series of grooved b:dl-bc::ring rollers 274, which are
F!G. 31. The output shaft 148 of motor (CDl'vn exrotatably secured to the bhmvn, which, in turn, are mounted
on an auxiliary frame platc of the machine. The slide
513 is resiliently urged tcw"rd t;le front of the machine,
cr to the left, as vic\'.-ed, by means of a spring 514, but
is normally ret:lineu in its rearward position, against the
ur'gcncy of the spring 514, by means of a rod 515, secured
to the upper end of a lever 5!6. The lever 516 is pivotally mounted on a stud 517, which is secured to thc
auxiliary frame plate, and its lower end is pivotally connected to the forward end of a link 518. The rcar end
of the link 518 is pivotally connected to the upper end of
a follower arm 519, which is retatably mounted on a
~haft 526 and is provided with rolls 521 and 522, which
respectively cooperate with a pair of companion cam
pbtcs 523 ,and 524, secured to the main cam shaft 525
of th<;: uccounting machine.
Hence, during each cycle of operation of the accounting machine, the C¢ through 99. In addition to the one hundred normal addresses, there are two additioool addresses
t\abeJed "A" and "B." The words stored in addresses ¢¢
through 99 not only represent arithmetic data., but also
represent "instructions" which are utilized oy the computer to dictate the sequence of opemti'Ons therein. The
words previously stored in addresses ¢¢ through 99 of
the memory may be changed by instructions given by the
computer; however, the words located in addresses A and
B are used by the computer to store intermediate results
during arithmetic computations and cannot be changed
directly by instructions.
With reference to FIGS. 52a and 52b, there is schematically shown the ferrite core memory utilized by the
present computer. Such a memory comprises four thou-

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sand and eighty type N-400-080 ferrite cores at p'resent
manufactured byuhe assignee 'Of the instant applicati'On.
The ferrite cores of the memory are selectively ar,ranged
in a pattern of rectangularly-shaped configuration having one hundred two vertical columns and forty horizontal
rows thereof. The fi.st one hundred columns, as viewed
from left to right, respectively represent memory address
locations rprp through 99, whereas the two remaining rightmost columns respectively represent address locations A
and B. ,In each of the columns, from the topmost to the
bottommost core, the forty cores are arranged in a succession of ten groups, with each group containing four
cores. Each group of four cores is representative of a
decimal digit of a predetermined order, whereas all of
the groups of a particular column collectively represent
all of the orders of a word ten decimal digits in length.
Each of the ten successive decimal digits of the word located in any address is respectively identified as the "firstorder" digit through the "tenth-order" digit, where the
first order is the lowest or "penny" digit and the tenth
order is ,the highest order digit of the number or word.
The four cores used to store the first-order digit of a
word which is residing in an address in the memory
a,re located in the first row through the f.ourth row, counting from bottom to top. The four cores used to· store
the second-order digit of the word are located immediately above in the fifth through the eighth rows; in the
drawing, only the fifth and eighth rows are shown, rows
six and seven being omitted for the sake of simplicity.
The four cores used to store the third-order digit are
located immediately above in rows nine through twelve,
where rows nine and twelve are the only ones illustrated,
rows ten and eleven being omitted for the reasons just
mentioned. The location of each higher-order digit
progresses upward, as just described, so that the tenth
or highest-order digit is located at the top of the column in the last four rows shown; i.e., thirty-seven through
forty. Therefore, it is seen, the maximum storage in
each memory address is a ten-digit number which will
hereinafte·r be called a "word," the lowest-ordcr digit
thereof being located at the bottom of each address and
the highest-order digit thereof being located at the top
of each address.
As the instant computer utilizes the well-known "8421
binary-coded-decimal-digit" system of numerical representation, each of the four cores in a group making up a
particular Qrder decimal digit of the word is known as a
"binary-bi!." The binary-bits are consecutively labeled
(a), (b), (e), and (d), where bit (a) is the lowest-order
of representing a particular order numerical digit havin rows #1, #5, #9, and #37, and bit (d) is the highestorder bit represented by the magnetic state of the cores
located in rows #4, #8, #12 . . . and #40. As previously mentioned, each group of four cores ,is capable
of representating a particular order numerical digit havjng a value from "0" through "9." Fer example, to
represent a decimal digit having a value ef "0," all of
the fQur cores in a ,group are selectively set to binary
bit representations (0000); for a decimal digit having a
value of "1," the cores are set to (0001) binary bit representations; a decimal digit having a value of "2," the cores
are set to bit representations (0010); a "3" is represented
by (0011); "4" by (0100); "5" by (0101); "6" by
(0110); "7" by (0111); "8" by (1000); and finally, to
represent a decimal digit having a value of "9," the cores
are sequentially set to binary bit representations (1001).
To illustrate, supposing that the word 0000000695 is
stored in memory at address rp1>. In the leftmost vertical
column, the four lowermost cores, indicated by reference
nume·mls 885 through 888, are respectively conditioned to
collectively represent binary bits (0 10 1) indicative of the
first-order digit "5." In other words, cere 885, representative ef binary bit "a,"is set to binary" 1"; core 886,
representative of binary bit "b," is also set to binary '·0";
core 887, representative of binary bit "e," is set to' binary

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"1 "; and, fin "lIy. core 888, representative of bit "d," is
set to binary "0" representation. ColIectively, the magnetic state of cores 885 through 888 represents the penny
digit "5." The next group of four cores, located directly
above group 885 through 888, are set to binary bit representatiens (1001) and collectively represent the secondorder decimal digit "9." The next group of fOllr cores are
set to binary bit representations (01 10), collectively representing the third-order decima'l digit "6." All of the
remaining cores in address ¢cp are individually set to
binary "0" representations. Thus, with the non-significant
decimal digits removed, the word becomes "695."
In one mode of operation, when a column of cores is
to be "read out" to determine the word stored in that particular memory address, the cores are sequentially read,
one at a time, starting with the core at the bottom of tbe
address and concluding with a core at the tep of the address. For example, in address rprp, core 885 is read first
to produce the binary value of bit "a" of the first-order
digit; core 886 is read next to produce bit "b" of the firstorder digit; core 887 is read next to produce bit "e"; and
core 888 is next read to produce bit "d" of this digit.
The next four bits, representing the second-order digit,
are successively read out, and the remainder of the bits
for successive higher-order digits are thereafter sequentially read out in the same sequence, concluding with bit
"d" of the tenth-order decimal digit.
After a cere has been read out, it is generally desired to
restore the core to its original magnetic state as before
being read. That is, after each bit-representing core is
read out, if the core was originally set to represent a
binary "l," the core is returned to tbe "1" state following
reading thereof. Therefore, following the reading of
each bit, a predetermined unit of time is permitted to
lapse before the next bit is read out; it is during this time
lapse that the core, just read, is returned to the" 1" state
if it had previously been set to that state.
For the sake of simplicity of the following description, the vertical or column orientation of the memory
will hereinafter be termed the "Y" direction, and the
horizontal or row orientation wiII hereinafter be termed
the "X" direction.
Even though, in reality, eaoh of the memory cores
has five cenductors threaded therethreugh for purposes
to be more fully described hereinafter, only three of
these conductors are to be considered at this time in describing a mode of operation of the memery in terms
ef the electrical schematic diagram thereof shown in
FIG. 52. The first of the three just-mentioned conductors is a "sense winding" 871, which starts at terminal
872 at the lower left corner of the memory and is alternately threaded through each row of cores bounded by
address ¢if> through 99. As shown, sense winding 871
is successively "hreaded from left to right threugh all
of the cores of t,he first row, is threaded from right to
left through the cores of the second row, from left to
right through the third row, and alternately continues
on from row to row. Finally, sense winding 871 is
threaded from right to left through the topmost or fortieth row of cores, ,and terminates at terminal 873. All
of the cores in address  are threaded in the "Y" direction by common current-carrying conductor 878,
which is shown positioned to the left within the apertures thereof. Also, all of the cores located in the first
row bounded by address rprp and address "B" larethreaded
in the "X" direction by a common current-carrying conductor 879, which is shown centrally positioned within
the apertures thereof, address "B" being the rightmost
one of the memory addresses.
It will now be assumed that it is desired to read out
the contents of address ¢. Thus, in order to read bit
Ha" of the first-order decimal digit of the word stored
in address ¢, a half-amplitude or "half-select" current
impulse is delivered to' conductor 878, and, simultaneously therewith, a half-select current impulse is present

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in conductor 879. The two half-select impulses are in
such directions that the magnetomotive forces associated ~herewith are additive in the region of core 885,
with the resultant force being of sufficient magnitude to
rna,gnetically saturate the core in a direction indicative of
a binary "zero." Due to the fact that core 885 is the
only core in the entire memory that has received the
necessary magnetomotive force to cause a reversal of its
magnetic state, all of the remaining cores essentially remain magnetically undisturbed. It is known that whenever the state of magnetic remanence of anyone of the
memory cores is reversed, ,a voltage impulse is induced
thereby in sense winding 871. However, due to the fact
that in the present memory only one core at a tfme is
sensed, there is no ambiguity as to which core was responsible for the impulse induced in the sense winding.
11herefore, if core 885, whose magnetic state is indioative of bit "a" of the first-order digit of the number, is storing a binary "1," its magnetic state is reversed by the coincidental "X" and "Y" read impulses,
and, consequently, a voltage impulse appears between
terminals 872-873 of the sense winding 871, indicating
that core 885 was previously storing a binary "1." If
core 885 had previously been storing a binary "0," however, a voltage impulse does not appear across the output
terminals of the memory sense winding, thus indicating a
binary "0" storage.
After core 885 has been read, its magnetic state is
thereafter indicative of a binary "0," as previously mentioned. Thus, if the magnetic state of the core was indicative of 'a binary "0" before being read, there is no
need for "resetting" the core ufter it is read. However,
if the state of the core was indicative of a binary "1'1
before being read, it is often necessary to "reset" the
core to a binary "1" representation after it has been mad.
To do this, the directions of both of the current 1mpulses
applied through the "X" 'and "Y" conductors are effectively reversed simultaneously. This causes a corresponding reversal of the additive magnetomotive force
in the vicinity of the core, which reverses the magnetic
state thereof. Again, as only a half-select current impulse is applied to each of the "X" and "Y" conductors,
core 885 is the only core in the entire memory that is
magnetically affected thereby.
Now that core 885 has been read 'and afterwards reset to its initial state, core 886 is read next to determine
the binary value of the bit" b" of the first-order digit of
the word. Again, a half-select current impulse is applied in the "Y" direction to conductor 878, and, essentially, a half-select current impulse is simultaneously applied in the "X" direction to nhe conductor of the second
row corresponding to 879. As before, both half-select
currents are in such directions to effect storage of a binary "0" in core 886. If the state of core 8S6 was indicative of a "I" before being read, the current in each
of the "X" and "Y" conductors threaded therethrough
is reversed to reset core 886 to "1" after it is read. This
reading and writing sequence of operation is sequentially continued from core to core until all forty cores of
address <1> have been read and thereafter restored to
their respective magnetic states.
The just-described combined reading and writing cycle
of operation of eaoh core is hereinafter called a "readwrite" cycle. The time requir,ed to complete a readwrite bit cycle in the instant computer is approximately
40 microseconds. During the first 30 microseconds of
the read-write cycle, the core is set to a binary "0" representation; during the remaining 10 microseconds of
the cycle, the core is often reset toa binary "1" representation if it was originally in that state. However, if the
core was originally in a binary "0" state before being
read, there is no resetting operation necessary during the
last lO~microsecond interval. Therefore, to read out an
entire ten-digit word from an address in memory requires a total time of 40X 40, or 1,600, microseconds.

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Due to the fact that, in the present memory, it is not
desired to reverse the current flow in a conductor, an
additional conductor is individually threaded in the "X"
direction through each of the rows of cores. This is
i1!ustrated by conductor 880, shown threaded through
the cores of the first row and disposed parallel with respect to conductor 879, previously described. By the
same token, 'an additional conductor is also individually
threaded in the "Y" direction through the cores of each
of memory addresses rp through 9'9, and also addresses
"An and "B." This conductor is illustrated by conductor 881, shown threaded through the cores of address
rp1> and disposed parallel with respect to conductor 878,
previously described. Thus, two conductors are threaded
in the "X" direction and two conductors are threaded
in the "Y" direction through each of the cores of the
memory; each of the fOllr 'wires transmits current in only
one direction, as will be s,hown hereinafter. The fifth
wire through memory cores in addresses rprp through 99
is sense wire 871, heretofore described. A separate
sense winding 891, which originates at terminal 892 and
terminates at terminal 893, is alternately threaded, in
one dipcction and then the other, through the forty rows
of cores making up memory addresses "A" and "B" in
the same manner 'as memory sense winding 871.
Before attempting to give a more detailed description
of the memory, it is to be appreciated that each of the
rows of cores, from the first to the fortieth row, is connected in a same circuit configuration with respect to the
others. Likewise, each of the columns of cores, from
addresses  through 99 and including addresses "A"
and "B," is also of the same circuit configuration with
respeot to the others. Thus, a description and full comprehension of the mode of operation of address rprp with
respect to the first row of cores for producing bit "a" of
the first-order digit of the word stored in address "''''
should suffice for the remaining bits of that digit, and also
the remaining digits of that word. As the mode of operation of address 1>1> is exactly the same as that of the
remaining memory addresses, a further description of the
remaining addresses, again, would result only in unnecessary repetition. It is also to be appreciated that, in an
attempt to simplify the schematic representation of the
memory as shown in FIG. 52, addresses 1>1> through 9
are consecutively shown, reading from the extreme left
to the right; ,addresses 1", and 19 are shown next, with
addresses 11 through 18 being omitted, as indicated by
the vertical "break" in the drawing between addresses 1",
and 19; following in sequence are addresses 21>, 29, 3,
39, 4, 49, 5rp, 59, 6rp, 69, 7rp, 79, 8 89, and 9rp through
99, and finally addresses "A" and "B"; addresses 21-28,
31-38, 41-48, 51-58, 61-68, 71-78, and 81-88 are
omitted. Starting from the bottom of the drawing, the
first four rows are shown which make up the low-order
digit of the word stored in memory; rows #5 and #8 are
shown next, with rows #6 and #7 omitted as indicated
by the horizontal "break" in the drawing between rows
#5 and #6; following in sequence are rows #9, #12,
#13, #16, #17, #20, #21, #24, #25, #28, #29, #32,
#33, #36, and #37 ,through #40; rows #10-#11, #14#15, #18-#19, #22-#23, #26-#27, #30-#31, and
#34-#35 are omitted.
With particular attention directed to the first row of
cores, on emergence from the rightmost end of the first
row of cores, conductor 880 is connected to conductor
882, which passes below the first row and is connected at
its opposite end to line XDa, located at the bottom left
corner of the memory. The leftmost end of conductor
879 also is connected to line XDa, and its opposite end is
connected to the cathode of one of crystal diodes 876, its
anode being connected to line XG",; and, finally, the remaining left end of conductor 880, on emergence from
the leiltmost end of the first row of cores, is connected to
the cathode of one of crystal diodes 877, whose anode is
connected to line (XGrp)'.

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Whenever line XDa is activated, that line is effectively
connected to a source of potential of approximately -12
volts. Thus, if line XGtp is simultaneously activated
therewith, that line is effectively connected to terminal
843 of a temperature-compensated current regulator, of
the type previously described with respect to FIG. 51g,
so that a half-select drive current impulse flows from line
XGtp through diode 876 from right to left through conductor 879 and out at line XDa. However, if line
(XGtp)' is simultaneously activated instead of line XGtp,
line (XGtp Y is effectively connected to terminal 843 of
the current regulator, so that a half-select current impulse
from Hne (XGtpY flows through diode 877, thereafter
flows from left to right through the upper loop of conductor 880, and is returned to line XDa by way of conduct or 882. Consequently, it is seen that, when line XDa
is activated, the half-select drive impulse flows in one of
two directions through the cores of the first row, depending upon whether XGtp or (XGtp)' was simultaneously
activated with line XDa.
The electrical connections for rows #2 through #4,
respectively representing bits "b," "e," and "d" of the
first-order digits of the words stored in memory, are
exactly the same as for row #1, the anodes of the four
crystal diodes 877 each being connected to line (XGtp)'
and the anodes of the four crystal diodes 876 being connected to line XGtp. When line XDb is activated, the line
is effectively connected to a potential source of -12
volts, as was line XDa. Thus, when line XGtp is activated simultaneously with XDb, the half-select current
impulse flows from right to left through the cores of .the
second row; if (XG<1>)' is activated instead of XGtp, a
half-select current impulse flows from left to right through
the cores of the second row. By the same token, if XDe
and XGtp are simultaneously aotivated, a half-select current impulse flows from right to left through the third
row of cores; a simultaneous activation of XDe and
(XGtp)' effectively causes a reversal of current flow
through the third row of cores. Finally, XDd and XGtp,
or XDd and (XG<1> Y operate together to effectively send
a half-select impUlse from right to left or from left to
right, respectively, through the fourth row of cores in
the same manner as just described.
As just described, the first four of diodes 877 (i.e., the
ones respectively associated with rows #1 through #4)
have their anodes connected together and returned to
line (XGtp),. The second group of four diodes 877, associated with rows #5 through #8, of which only rows #5
and #8 are illustrated, all have their respective anodes
connected to line (XGIY. The anodes of the third group
of diodes are each connected to line (XG2)', the anodes
of the fourth group being connected ,to (XG3Y, and so
on up the column, with the anodes of the tenth group of
diodes 877 being connected to line (XG9) '. Also, as
shown, the left end of each of the conductors corresponding to 879 and 882 associated with rows #1, #5, #9,
#13 . . . #33, and #37, which rows successively correspond to bit "a" of each successive-order decimal digit of
the word stored in memory, are connected together and
returned to line XDa. Likewise, although not fully illustrated, the left end of each of the conductors corresponding to 879 and 882 but associated ,with rows #2, #6, # 10,
#14 . . . #34, and #38, which rows successively correspond to bit "b" of each successive-order decimal digit of
the word in memory, are connected together and returned
to line XDb. By the same token, although not fully illustrated, the left end of each of the conductors corresponding to 879 and 882 but associated with rows #3, #7, #11,
#15 . . . #35, and #39, which rows successively correspond to bit "e" of each successive-order decimal digit of
the word in memory, are conneoted together and returned
to line XDe. And finally, the left end of the conductors
corresponding to 879 and 882 but associated with rows
#4, #8, #12, #16 ..• #36, and #40, which rows successively correspond to bit "d" of each successive-order

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decimal digit of the word in memory, are connected together and returned to line XDd.
With respect to the vertically-disposed column of diodes
located to the right of address "B" and indicated as 876,
the ,first bottom group of four diodes thereof associated
with rows # 1 through # 4 each has its anode connected
to line XGtp; the second group of four diodes 876 located
directly above the first group have their anodes returned
to common line XGl; the anodes of the third group of
diodes 876 are connected to line XG2, and so on, with
the anodes of the last four diodes 876 at the top of the
column and associated with rows #37 through #40 being
connected to common line XG9.
Referring to the lowermost row of diodes 874 located
below row # 1, counting from left to right, the anodes of
the first ten of diodes 874 respectively associated with addresses "'41 through <1>9 are connected to line YG",. With
respect to the next group of diodes 874 located immediately to the right of the first group of diodes and respectively associated with addresses 11 through 19, of which
only addresses 11 'and 19 are illustrated and addresses 12
through 18 are omitted, their anodes are connected to line
YGl; the anodes of the third group of diodes 874 respectively associated with addresses 20 through 29 are connected to line YG2; and so on, with the anodes of the
last group of ten diodes 874, respectively associated with
addresses 941 through 99, being connected to line YG9.
With respect to the upper row of diodes 875, which are
located directly above row #40, the first group of ten
diodes which are respectively associated with addresses
41<1> through 99 have their anodes connected to line
(YG<1»' in the same manner as the lower row of diodes
874. The anodes of each successive group of ten diodes
875, counting from left to right, are respectively connected to lines (YGl)' through (YG9)'.
To complete the electrical connections to memory addresses <1>tp through 99, the upper ends of vertical conductors corresponding to 878 and 883, which are respectively associated with addresses tp<1>, 1<1>, 241, 341, ••• 8tp,
and 9<1>, are connected to line YDtp. The upper ends of
vertical conductors corresponding to 878 and 883, which
are respectively associated with addresses 01, 11, 21,
31, . . . 81, and 91, are connected to line YDI. Only
addresses <1>1 and 9'1 of this group are illustrated, the remaining addresses of this group being omitted for simplicity purposes. Likewise, the upper ends of vertical conductors 878 and 883, which are respectively associated
with addresses 412, 12, 22, 32, . . . 82, and 92, are connected to line YD2. This sequence of connections continues from lines YD3 through YD9, where YD9 is connected to vertical conductors corresponding to 878 and
883, which are respectively associated with addresses <1>9,
19, 29, 39, . . . 89, and 99.
To summarize: Selective energization of line YD",
essentially selects all addresess whose low-order digit is
a "0"; YDI essentially selects all addresses whose loworder digit is a "1"; YD2 essentially selects all addresses
whose low-order digit is a "3"; and so on from YD3
through YD9, where YD9 essentially selects all addresses
whose low-order digit is a "9." Forgetting about "primenotations" for the present, selective energization of line
YGtp essentially selects all ~ddresses whose high-order
digit is a "0"; YGl essentially selects all addresses whose
high-order digit is a "1 "; YG2 essentially selects all addresses whose high-order digit is a "2"; and so on from
YG3 to YG9, where selective energization of line YG9
essentially selects all addresses whose high-order digit is a
"9." Thus, suppose that it is desired to select a particular
address; say address 9",. To accomplish this, YD<1> is energized corresponding to the low-order digit "0" of the address, and, simultaneously therewith, YG9 is energized
corresponding to the high-order digit "9" of the address.
Thus, when YDtp and YG9 are simultaneously energized,
a binary "I" representative half-select current flows upwardly from line YG9 through all of the cores in address

3,112,394

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69
9 and out at line YD. To select address 99, YD9 and
YG9 are energized simultaneously.
As far as "prime notations" are concerned, it is to be
pointed out at this time that throughout the electrical
circuitry of the computer signal lines bearing a "prime"
notation-Le., (XG)' et al.-essentially
have diametrically opposite states or energization conditions to their respective "primeless" counterparts; i.e.,
XG, YG, et al. For example, lines (YG through 99 to "half-select" a particular address to a
binary "0" representation, whereas lines YG through
YG9 are effective to send a half-select impulse upwardly
through anyone of the same respective addresses to
"half-select" that particular address to a binary "1" representation. It is also to be appreciated at this point that,
when the state of a signal line bearing a "prime" notation
is de-energized or is FALSE, the "primeless" signal line
cOllnterpart is respectively "energized" or is TRUE, and
vice versa. In other wonds, when one is energized, the
other is de-energized; when one is TRUE, the other is
FALSE, etc.
In the "X" direction of the memory, line XDa selects
those ten rows corresponding to bit "a" of each order
decimal digit of the word; line XDb selects those ten rows
corresponding to bit "b"; line XDc selects the ten rows
corresponding to bit HC"; and, finally, line XDd selects
the ·final ten rows corresponding to bit "d" of each order
decimal digit of the word. Lines (XG through XG9 are
effective to send a half-select impUlse from right to left
through anyone of the same respective rows to "halfselect" that particular row to a binary "1" representation.
Thus, combining "X" and "Y" selection of the memory,
in order to store a binary "1" representation in a core, say
core 885 as Ian example, which is located at the junction of
row # 1 and address , lines YD, YG, XDa, and
XG are all simuitaneously energized. To store a binary
"0" representation therein, lines YDc/>, (YG¢)', XDa, and
(XG)' are all effectively energized simultaneously. To
store binary information in core 886·, line XDb is energized instead of line XDa. The manner of "X" and "Y"
selection of addresses "A" and "B" is exactly the same as
the manner of selection of memory addresses c/> through
99. Consequently, further detailed description thereof is
not deemed necessary.
Before proceeding further with the description of the
logical control circuitry of the compu teT, it is to be
pointed out that an attempt has been made to simplify
and thus alleviate the inherent complexity of the schematic representation in order to facilitate a full and complete understanding of the circuitry, both as to its organization and as to its mode of operation. For example,
throughout the drawings, all input lines are appropriately labeled and are positioned to the leftmost side of the
various building blocks previously described, and the various output lines thereof also are appropriately labeled
and are positioned to the rightmost side of the building
blocks. However, for illustrative purposes only, but a
selected few of the input and output lines are actually
shown connected. It is, of course, to be understod that,
in order to obtain a full and complete electrical circuit
diagram of the computer, it first is necessary to substitute
the appropriate type of building block circuitry (taken
from FIGS. 46 through 51) for each of the correspondingly-labeled building blocks which are logically illustrated throughout tbe drawings. Afterwards, all likelabeled lines (whether input lines, output lines, or otherwise) are to be connected together, thus forming a complete circuit diagram from the schematic representation
thereof.

17. X-Drivers

5

10

15

20

25

30

35

40

45

With reference to the lower right-hand section of FIG.
60, there are schematically illustrated four "X-drivers,"
which are utilized to selectively energize input lines XDa
through XDd, previously described in connection with
the core memory shown in FIG. 52. Each of the Xdrivers comprises a two-input logical AND of type "RI,"
an inverter amplifier of type "Il2," and an emitter follower amplifier of type "E3," each connected in cascade
with respect to the others. More specifically, the Xdriver for bit "a" includes logical AND 111}8, inverter
4237, and emitter follower 4251t; the X-driver for bit
"b" comprises logical AND 111}9, inverter 423·S, and
emitter follower 4251; the X-driver for bit "c" comprises
logical AND 1110, inverter 4239, and emitter follower
4252; and, finally, the X-driver for bit "d" comprises
logical AND 1111, inverter 4250, and emitter follower
4253.
During a read-write cycle of operation for reading a
word from an address in memory, line SMC goes TRUE
for 1600 microseconds to allow line XDW to effectively
"condition" the selected X-driver to effectively be turned
"ON" at, and for, the proper amount of time. At 40
microseconds intervals, lines BaM through BdM sequentially go TRUE for a period of 40 microseconds each, and
then respectively go FALSE. Consequently, at the beginning of the read-write cycle, output line XDa is energized, and a potential of approximately -12 volts appears thereon. Line XDa stays energized for a maximum period of 40 microseconds and then is de-energized.
Forty microseconds after line XDa was first energized,
output line XDb is energized for a maximum period of
40 microseconds, and then is de-energized. Forty microseconds after line XDb was first energized, line XDc is
energized for a maximum period of 40 microseconds.
Finally, 40 microseconds after line XDc was first energized, line XDd is energized for a maximum period of
40 microseconds, lines XDa through XDd of FIG. 60,
of course, being identical to lines XDa through XDd of
FIG. 52, as previously stated. Thus it is evident, as a
maximum total time of 160 microseconds is required to
read each digit out of memory, that a maximum of 1600
microseconds is required to read a ten-digit number out
of a particular address in memory.
18. Bit-Collnter

50

55

GO

G3

70

75

The bit-counter, logically shown in the upper portion
of FIG. 62, includes two type "F2" flipfiops 6lt41 and
61142, connected as a scale-of-four binary counter, and
is utilized to select the binary bit of the word to be read
out of an address in memory during a read-write cycle,
as illustrated in the block diagram of FIG. 45. When
the computer is first turned "ON," or when pushbutton
RSI (FIG. 76) is actuated, fiipflops 6041 and 6042 are
unconditionally ~et TRUE by reset line (RS)' going
FALSE. That is, the states of fiipfiops 6041 and 6042
are sllch that reference output lines BCa and BCb, respectively therefrom, arc TRUE, and prime output lines
(BCa)' and (BCb)' are both FALSE.
The bit-counter usually counts in a forward direction,
as will be shown later. However, there are times when
the bit-counter is required to effectively count in a reverse direction. When counting in a reverse direction,
the read-write word cycle begins by reading out the
high-order bit of the high-order digit; i.e., bit "d" of
digit #9. The signal which provides for this reverse
operation of the bit-counter comes from line DBD.
When line DBD is TRUE (line (DBD)' thus being
FALSE), the bit-counter counts in a reverse direction.
Conversely, when line DBD is FALSE (line (DBD)'
thus being TRUE), the bit-counter counts in a forward
direction.
If it be desired that the bit-counter is to count in a
forward direction, lines (DBD)', BCa, and BCb must

3,112,394

71
first be TRUE. Therefore, as all three inputs to logical
AND 1158 are simultaneously TRUE, lines Bd and BdM
are also TRUE, the remainder of output lines Ba through
Be and BaM through BdM being FALSE. When input
line Cye goes from TRUE to FALSE, the prime inputs
to both of fiipflops 6041 and 6042 go from TRUE to
FALSE. Consequently, both flipflops 6041 and 6042
change state, so that lines BCa and BCb go FALSE and
lines (BCa)' and (BCb)' go TRUE. As lines (DBD)',
(BCa)', and (BCb)' are now TRUE, all of the inputs
to logical AND 1152 are simultaneously TRUE, and thus
output line Ba is TRUE, with the remaining outputs Bb
through Bd being FALSE. When line CYYC goes from
FALSE back to TRUE, the state of both fiipflops remains
unchanged. However, when line CYC again goes from
TRUE to FALSE, the reference input to flipflop 6041
goes from TRUE to FALSE. At this time, lines BCa
and (BCb), are TRUE, and lines (BCa)' and BCb are
both FALSE. Thus, as inputs (DBD)', BCa, and
(BCb), of logical AND 1154 are simultaneously TRUE,
output line Bb is TRUE, and remaining outputs Ba, Be,
and Bd are FALSE. When line CYC goes from TRUE
to FALSE a third time, all input lines to logical AND
1156 are simultaneously TRUE, and output line Be is
likewise TRUE, with lines Ba, Bb, and Bd being FALSE.
Finally, when CYC goes from TRUE to FALSE a fourth
time, line Bd is TRUE, with lines Ba through Be being
false.
To summarize, only readout line Bd is initially set
TRUE when the computer is first turned "ON" or when
pushbutton RSI (FIG. 76) is actuated; the remaining
readouts, Ba through Be, are FALSE. At this time, for
each successive occurrence of a TRUE-to-FALSE reversal of line CYC, the bit-counter is incremented by a
count of one binary bit. Thus, with four such reversals
of line CYC, the bit-counter counts Ba, Bb, Be, and back
to Bd. When the bit-counter is to count backwards, line
DBD is rendered TRUE instead of line (DBD) '. Consequently, at this time, line Ba instead of line Bd is
TRUE; remaining lines Bb through Bd are FALSE.
Thereafter, for each 'successive occurrence of a TRUE-toFALSE reversal of line CYC, the counter is decremented
by a count of one bit. Thus, with four such reversals of
line CYC, the bit-counter counts Bd, Be, Bb, and back to
Ba. It is to be appreciated, of course, that lines BaM
through BdM are at all times of the same state as lines
Ba through Bd, respectively. It is also to be appreciated,
as before stated, that lines BaM through BdM of FIG. 62
are respectively identical to lines BaM through BdM of
FIG. 60 and anywhere else they may appear in the computer circuitry.
,19. X and Y Grounders
In the left portion of FIG. 66, there are diagrammatically shown two sets of ten X-grounders, one set of ten
represented by output lines XG¢ through XG9, and the
other represented by output lines (XG¢), through
(XG9)'. Each of the twenty X-grounders comprises a
serially-connected network of a two-input logical AND
of type "Rl," an inverter amplifier of type "Il2," and an
inverter amplifier of type "12." The emitter electrodes
of inverters 3268 through 3287 are connected together
and returned via line CRX to output terminal 843 of
temperatme-compensated current regulator 7001, which
has previously been shown and described in detail in connection with section (g) of FIG. 51.
The mode of operation of each of the X-grounders
is somewhat straightforward. When both inputs to any
one of logical AND's 1281 through 1300 are simultaneously TRUE, that particular AND circuit effectively
causes a constant-current operating potential of approximately -10 volts to be applied to its respective output
lead; i.e., one of leads XG¢ through XG9 or (XG through D9 are also utilized by the computer 10 TRUE state of line Wrp1, lines W<;/>cp and W¢2 through
W¢I), of course, being FALSE. However, both the
for various control purposes, in addition to memory digit
low-order section and the high-order section of the wordselection. In addition to the read-out lines following the
selecting register must first be set to zero via line (PW<;/»'
forward-reverse logic, there is an additional readout line
D9L, which is TRUE each time lines Da and Dd are
in order for line STI to be effective to preset the wordsimultaneously TRUE, regardless of whether the digit 15 selecting register to "01." The reason for this ,is that,
counter is operating in a forward or a reverse direction.
as shown, line ST1 is effective only in presetting the state
of flipflop 6051 and does not affect the states of the re21. Y-Drivers
maining flipflops of both sections of the word-selecting
register.
In the rightmost section of PIG. 65 there are shown
With reference to FIG. 64, the four fiipflops which are
ten V-drivers, whose output lines are respectively labeled 20
utilized to store the high-order decimal digit of the number
YD<;/> through YD9. Each driver includes a serially-constored in the word-selecting register are 6047 through
nected network comprising a two-input type "Rl" logical
6050. The state of flipflop 6047 represents the low-order
AND, a type "112" inverter, and a tyJXl "E3" emitter folbit "a," the state of flipflop 6048 represents the secondlower amplifier. As previously described, by sdective energization of line YD<;/>, all addresses whose low-order digit 25 order bit "b," the state of flipflop 6049 represents the thirdorder bit "e," and the state of flipflop 6050 represents the
identification is a "zero" arc effectively "selected"; i.e.,
fourth or high-order bit "d" of the decimal digit. Output
addresses cj>rp, 1<;/>, 2rp, . . . 8<;/>, and 9cj>,by selective enerlines Wla through WId and (W1a)' through (WId)' from
gization of line YDI all addresses ending in a "one" are
flipflops 6047 through 6050 are connected as inputs to a
effectively selected; i.e., 11, 21, 31, . . . 81, and 91; by
selective energization of line YD2, all addresses ending 30 decoder network comprising ten type "RI" logical ANDS
1226 through 1235, which are individually 'cascaded with
~n a "two" arc effectively selected; and so on, with line
a type "Dr' logical OR, a type "IS" inverter, and a type
YD9 effectively selecting all addresses ending in a "nine";
"Il5" inverter. As in the low-order section of the wordi.e., addresses rp9, 19, 29, . . . 89, and 99. Selective
selecting register, as previously mentioned, its high-order
energization of lines YDcj> through YD9 is effected by
logically ANDING line YDW with each of lines W¢¢ 35 section is also unconditionally preset to "zero" by line
(PWrp)', which presets the reference outputs of flipflops
through Wrp9 which originate at the decoder portion of
6047 through 6050 FALSE.
the low-order digit section of a "word-selecting" register
Included in the high-order section of the word-selecting
next to be descl'ibed.
register are ten readouts which decode the decimal digit
22. Word-Selecting Register
40 representation as represented by the states of flipflops
6047 through 6050, the readouts being by way of output
The word-selecting register is a two-digit register which
lines WIcj> through W19. For example, when the highis utilized to temporarily store a t\vo-decim81-digit numorder digit in the word-selecting register is a "0," only
ber representing the address location of the word in memline Wlcp is TRUE. Line Wll is TRUE only when the
ory from which reading is to take place. That is, the
word located in memory at the address corresponding to 45 high-order digit is a "1," and so on, so that line WI9 [s
TRUE only when the high-order digit is a "9." Then ten
the number stored a through Wcpd and (Wcpa)' through
during the next read-write cycle. Even though there are,
(W cj>d)' from flipflops 6051 and 6054 are connected as
in fact, only twenty readout lines Wrp¢ through Wl1) for
inputs to a decoder network comprising ten type "Rl"
the word-selecting register, in combination they effectively
logical ANDS 1261 through 1270, which are individually 65 function as one hundred readouts. In other words, one
cascaded with a type "Dl" logical OR, a type "IS" inverter,
of lines Wlrp through Wl1) is TRUE, indicative of the
and a type "115" inverter. Thus, when the low-order sechigh-order digit of addresses rp<;/> through 99. At the same
tion of the word-selecting re~ster is storing a count of
time, one of lines W¢cj> through Wcj>9 is TRUE, indicative
"zero," output lines Wrpa through Wrpd are FALSE, and
of the low-order digit of the address. As an illustrative
lines (Wrpa)' through (W¢d)' are TRUE. As all of the 70 example, address 96 is represented by lines W19 and Wcp6
input lines to logical AND 1261 are simultaneously TRUE,
simultaneously bcing TRUE; address 48 is represented by
output line W<;/><;/> is TRUE, indicative of the "zero" storage
lines W14 and W¢8 simultaneously being TRUE, and
in flipflops 6051 through 6054. In a like manner, cjt is
so on. Thus, a half-select current is allowed to flow in
seen that only one of output lines W <;/><;/> through W <;/>9 of
the "Y" direction only in the vertical string of cores lothe decoder is TRUE at any given instant, and a TRUE 75 cated in the address corresponding to the number stored

3,112,394

75
in the word-selecting register. The number in the wordselecting register remains therein during the entire time the
ten-digit word is being read out of memory. Other suitable means have been provided for selecting addresses
"A" and "B," as will later be seen.
The bit and digit counter combination determines which
row of cores is to receive a half-select current impulse
during a read-write cycle. That is, the output of the bit
counter determines which bit is to be read out-i.e., bit
"a," "b," "c," or "d," and the digit counter determines
which order digit is to be read out. For example, if the
bit counter is at "a" and the digit counter at "1," a halfselect current impulse is permitted to flow only through
the row of cores corresponding to the low-order bit of
the second-order digit. If the bit counter is at "d" and
,the digit counter at "9," a half-select current impul$e is
permitted to flow only through the row of cores corrcsponding to the high-order bit of the tenth-order digit,
and so on.
24. Synchronizing Clocks
Before going into a detailed description of a complete
read-write cycle of a word stored in a particular address
in memory, it is deemed desirable, at this point, to briefly
describe the various "clocks" which are utilized by the
oomputer for synchronization purposes, to insure the
proper sequence of data handling and transfer.
With reference to FIG. 84, a 50-kilocycle multi-vibrator 6125, substantially identical to the one heretofore
shown and described in connection with section (a) of
FIG. 50, has the reference output thereof connected
through AND gates 1778 and 1779 to both the reference
and the prime inputs of flip-flop 6127. As multivibrator
'6125 is essentially a 50 kc. square-wave generator, the
signal voltage appearing on the reference output lead MY
thereof is as shown by the topmost waveform in FIG.
87B. If at "TIME-I" the state of line MY is reversed
from TRUE to FALSE, the state of line MY reverses
from FALSE back to TRUE ten microseconds later at
'TIME-2." Ten microseconds later, at "TIME-3," the
state of line MY again reverses from TRUE to FALSE,
and so on. As heretofore mentioned, the state of line
(MY)' is effectively 180 degrees out of phase with the
state of line MY.
If it is assumed th8t directly preceding TIME-l the
states of lines MY and C31 are both TRUE, as shown, at
TIME-l the reference input to flip flop 6127 is reversed
from TRUE to FALSE. Consequently, flip flop 6127 is
triggered so that the state of line C31 is rendered FALSE
and the state of line C13 is rendered TRUE. At TIME-3,
when the state of line MY again is reversed from TRUE
to FALSE, the state of line C31 is rendered TRUE and
the state of line C13 is rendered FALSE. This sequence
of events is continually repeated during operation of the
computer.
At TIME-2, the state of line (MY)' is reversed from
TRUE to FALSE, and, consequently, flip flop 6128 is
triggered so that the state of line C42 is thereby rendered
FALSE and the state of line C24 is thereby rendered
TRUE. At TIME-4, when the state of line (MY)' again
reverses from TRUE to FALSE, the states of lines C42
and C24 are reversed. At TIME-t, when the state of line
C31 reverses from TRUE to FALSE, flip flop 6129 is triggered so that the state of line C41 is thereby rendered
FALSE, and, simultaneously therewith, the state of line
C41 is rendered TRUE. Thirty microseconds later, the
state of line C24 reverses from TRUE to FALSE. Therefore, at TIME-4, flip flop 6129 is reset to its initial state
so that immediately thereafter the state of line C41 i~
rendered TRUE and the state of line C14 is simultaneously rendered FALSE.
As shown, output lines C31, C13, C42, and C24 are
variously connected as inputs to flip flops 6129 through
6.132 to provide suitably phased clock pulses on output
hnes C41, C14, C43, C34, C23, and Cl2. It is to be

76

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20

noted that the highest-order numeral designation thereof
denotes the time at which the state of that particular line
is rendered TRUE and the lowest-order numeral designation denotes the time at which the state of that particular
line is rendered FALSE. For example, the state of line
C41 is rendered TRUE at each TIME-4 and FALSE at
each TIME-t, the state of line C23 is rendered TRUE at
each TIME-2 and FALSE at each TIME-3, and so on.
The 400-cycle multivibrator 6126 has a period of approximately 1.24 milliseconds. Consequently, due to the
synchronizing action with respect to the state of line C41,
as heretofore described in connection with section (b)
of FIG. 50, the state of line ICC is rendered TRUE and
the state of line (ICC)' is rendered FALSE at TIME-I'
approximately 1.24 milliseconds ·thereafter at TIME-I'
the state of line ICC is rendered FALSE a~d the state of
line (ICC)' is rendered TRUE. Again, approximately
1.24 milliseconds thereafter, at TIME-I, the state of line
!CC a.gain is rendered TRUE and the state of line (ICC)'
IS agam rendered FALSE. As this sequence of events is
~on(~nually repeated during operation of the computer, it
IS eVident that the output from the 400-cycle multivibrator
6126 is effectively synchronized with the output from the
50 kc. multivibrator 6125.

25
25. Detailed Read-Write Cycle

30

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50

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60

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~ith reference to FIG. 60, during a complete readwnte cycle of a WOJ;d stored in a particular address in
memory, line SMC is TRUE for a ,period of 1600 microse~onds, and line MYW is TRUE for a period of 1650
microseconds. Therefore, as all the inputs to logical
AND 1096 are simultaneously TRUE at TIME-3 line
YDW also goes TRUE at TIME-3 and stays TRUE for
a period of 20 microseconds until TIME-I' at TlME-t
line YDW goes FALSE and stays FALSE for 20 micro~
seconds until TIME-3; at TIME-3 line YDW again goes
TRUE, and so on. Thus, it is seen, at TIMES 1 and 3
]~ne YDW goes FALSE and TRUE, respectively, for pe:
nods of 20 microseconds each. This is done to permit
one of Y-driver output lines YD¢ through YD9 (FIG.
65) to be selectively energized for a period of 20 microseconds by selected ones of output lines W¢¢ through
W¢9 of the decoding portion of the low-order section of
the word-selecting register,as will more fully be described hereinafter.
As previously described in connection with FlG. 66,
selected pairs of Y-grounder output lines YGt/>--(YG¢)',
YGl-(YGl)' . . . YG9-(YG9)' are conditioned at
~redetermined times by a corresponding one of output
hnes WI through W19 of the decoding portion of the
high-order section of the word-selecting register (FIG.
64), a selected one of each pair being selectively energized by one of lines WR and (WRY. As shown in
FIG. 66, lines WR and (WR)' alternately effect energization of only one of the Y-grounder output lines.
That is, only one of the Y-grounder output lines is energized at any given time; when that particular Y-grounde.r o~tput lin~ is de-energized, another Y-grounder output
lme IS energIzed, and so on. This is clearly illustrated
in the timing chart of FIG. 87A, which is to be referred
to, from time to time, during the following detailed description of a complete read-write cycle.
It will be assumed that it is deskous to read a word
out of memory address , that the reading operation
is to begin with the lowermost core in address ¢¢, and
that all data read out is to be re-stored in address .
Thus, to begin the reading operation, lines (WR)' and
WI.. (FIG. 66) simultaneously go TRUE, thereby energlzmg Y-grounder output line (YG¢)' at TIME-I, as
shown in the just-mentioned timing chart of FlG. 87B.
Simultaneously therewith, lines XDW and BaM (FIG.
60) go TRUE,thereby energizing X-driver output line
XDa at TIME-I. Also simultaneously therewith, lines
DM and (WR)' (FIG. 66) are TRUE to energize Xgrounder output line (XG)' also at TIME-I. Conse-

3,112,394

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78

quently, as both the X-driver, XDa, and the X-grounder
(XG1»' (FIG. 52A) are simultaneously energized at
TIME-t, a current impulse of half-select magnitude (approximately 180 ma.) flows from left ,to right through
the bottom row of cores to "half-select" each of the cores
in the row toward a binary "zero" representation, as previously described, the binary value of the low-order bit
of the first-order digit of the word stored in memory address 1>1> being represented by the initial state or direction of magnetization of core 885, as before stated.
Twenty microseconds later, at TIME-3, line YDW
(FIG. 60) goes TRUE to effect energization of Y-driver
output line YD1> (FIG. 65). Thus, as the Y -driver output line YD and Y-grounder output line (YG1> toward a binary "zero" representation. As the magnetommotive forces produced by
the two half-select currents are additive in the region of
core 885 only. immediately following TIME-3 core 885
is the only oore in the entire memory that is magnetically
set to a binary "zero" representation at this time. If it
is assumed that core 885 previously was in a magnetic
remanent state representative of a binary "one," the
state of magnetization of the core is reversed immediately
following TIME-3. Consequently, with respect to terminal 872, a negative-going output pulse is induced in
memory sense winding 871 (FIG. 52) having a peak amplitude occurring approximately 3 microseconds after
TIME-3.
The negative-going output pulse induced in memory
sense winding 871 renders memory sense amplifier 4399
(FIG. 67 A) conductive during presence thereof, so that
the uppermost input to logical AND 1163 goes TRUE
during presence of the pulse from memory, as shown in
FIG. 87. Assuming that the signal on the lowermost input to AND 1163 from flipflop 6149 is also TRUE, both
of the common-load transistors making up AND 1163
(FIG. 48j) are rendered non-conductive, 'so that the signal applied to the reference input of flipflop 6055 goes
FALSE approximately 3 microseconds after TIME-3
and flipflop 6055 is triggered thereby, so that output line
MSA goes TRUE, indicating that a binary "one" had
previously been stored in core 885 (FIG. 52); output
line (MSA)', when TRUE, indicates that the core was
'previously storing a binary "zero."
At TIME-4, line (WR)' goes FALSE (FIG. 66) and
,une WR goes TRUE. Therefore, X and Y-grounder
lines (XG
and YG are energized. As core 885 (FIG. 52A) was
previously storing a binary "one," X and Y-driver output
lines XDa and YD remain energized, and, consequently,
a full-select current impulse flows through the core in
the opposite direction to "re-set" the core back to its initial binary "one" state immediately following TIME-4.
However, if the core had been initially storing a binary
"zero," instead of a binary "one," a voltage impulse
would not have been induced in the memory sense winding, and, consequently, output line MSA (FIG. 67 A) remains FALSE instead of going TRUE, thus indicative of
the binary "zero" storage in core 885. In that instance
when line MSA remains FALSE, line MXW (FIG. 60)
likewise remains FALSE, and, consequently, not all of the
inputs to logical AND 1098 are TRUE, as before. As a
result, line XDW goes FALSE and causes X-driver output line XDa to be de-energized. This is illustrated in
FIG. 87 by the dotted portion of the output signal representation of X-driver line XDa between TIME-4 and
TIME-1 for bit "a." X-driver line XDa now being deenergized at TIME-4, a binary "one" representing halfselect current flows through oore 885 in the "Y" direction only, and, consequently, the core is not "reset" to a

binary "one" state, but, instead, remains in its initial binary "zero" state.
It is to be noted that, during a read-write cycle, halfselect current is first applied in the "X" direction for
a period of 20 microseconds-Le., from TIME-1 to
TIME-3-before a coincidental half-select current is
applied in the "Y" direction through the core being "read."
One reason for operating the computer memory in this
manner is due to the physical placement of memory
sense winding 871 (FIG. 52). Due to the fact that the
sense winding is oriented parallel with respect to the
conductors threaded through the core in the "X" direction,
when a half-select current is first applied in the "X"
direction, a voltage impulse is induced in the sense winding even though the magnetic state of each core remains
unchanged. In fact, the amplitude of this voltage may
be from ten to fifteen times greater than the amplitUde
of the voltage induced in the sense winding due to a
"change-oi-state" of one of the cores. Consequently,
it is desirable to allow sufficient time ,to lapse after
application of a half-select current in the "X" direction
so that this unwanted voltage impulse is dissipated and
thus aUeviate any undesirable effects therefrom.
Another reason for this 20-microsecond delay is that
a half-select current through a core causes a noise impulse
to be induced in the sense winding especially if the previous half-select current through the core was in the
opposite direction. The amplitUde of this noise impulse
is, in most instances, approximately 7 millivolts per core
and requires from ten to fifteen microseconds to be
dissipated. As there are 100 cores in the "X" direction
per row, and, as the noise from all of the cores in each
row is additive, the total maximum ampU,tude of the
noise impulse is approximately 700 millivolts.
In an attempt to simplify the description and to insure
a complete understanding of the inherent complexity
of the mode of operation of the computer memory, it
has been assumed to this point that all of the cores making up memory addresses 1> through 99 and addresses
"A" and "B" are magnetized in the same direction to represent either a binary "one" or a binary "zero." However, in the actual operation of the computer memory,
this is not the case, the reasons for which are as follows:
As previously described with respect to FIG. 52,
memory sense winding 871 is sequentially threaded in
the same direction through every other one of the forty
rows of cores making up the entire memory. Thus, if
every core in the memory were magnetically set in the
same direction to represent, say, a binary "one," opposite
polarity output pulses are induced in the memory sense
winding during a read-write cycle, all of which pulses
individually represent a binary "one" storage in the respective core. For example, the cores making up the oddnumbered rows are responsible for output pulses of one
polarity indicative of a binary "one" storage, whereas
the cores making up the even-numbered rows are responsible for output pulses of an opposite polarity also
indicative of a binary "one" storage.
Also, as previously mentioned, it has been found that
a subsequently-applied half-select current impulse through
a core causes a noise impulse to be induced in the sense
winding if the previously-applied half-select current impulse through the core was in the opposite direction to the
subsequently-applied half-select current impulse; however, the subsequently-applied half-select current impU'lse
through the core causes a much smaller amplitude noise
impulse to be induced in the sense winding if the subsequently-applied half-select current impulse is in the
same direction as the previously-applied half-select current impulse.
Therefore, to alleviate the need for sensing amplifiers
which must be responsive to input impulses of opposite
polal'ity, and also, during reading of a particular core,
in order to subsequently apply a half-select current impulse therethrough in the "Y" direction, which is in the

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3,112,394

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same direction as the half-select current impulse previously applied in the "Y" direction therethrough during writing of a previously-read core, it has been found desirable
during the operation of the memory of the present computer for all of the cores making up the odd-numbered
rows to be magnetically set in one direction to represent
storage of a binary "one" and for all of the cores making
up the even-numbered rows to be magnetically set in
the opposite direction to represent storage of a binary
"one." Consequently, during a read-write cycle of operation, binary "one" signifying impulses of the same
polarity are induced in the memory sense winding, and
thus the sense amplifiers need only be responsive to
single polarity impulses; and, also, much smaller amplitude noise impulses are induced in the sense winding
during the reading operation.
With the foregoing in mind, the next portion of the
read-write cycle will be described and directed to bit
"b" of the low-order digit of the word stored in address
.p.p.
Now that core 885 (FIG. 52A) has been read and
then "reset" to represent its initial binary "one" storage,
line CYC (FIG. 61) goes from TRUE to FALSE at
the following TIME-l, measured with respect to bit "b."
As previously described in detail with respect to the bit
counter shown in FIG. 62, when line CYC goes FALSE
for the second time, line BaM goes FALSE, line BbM
goes TRUE, and lines BcM and BdM remain FALSE.
As line XOW (FIG. 60) also goes TRUE at TIME-l,
X-driver outputJine XOa is de-energized and output line
XOb is energized at TIME-l, as shown in FIG. 86. As
line YOW (FIG. 60) goes FALSE at each TIME-l, Ydriver output line YO.p (FIGS. 65 and 52A) is deenergized, and consequently, the half-select current in
the "Y" direction through the cores of address .p.p is
thereby not permitted to flow. However, as X-grounder
line XG", (FIG. 52B) remains energized during TIME-l,
and as X-driver Hne XOb is energized for the first ,time at
TIME-l, a haIf-select current flows from right to left
through core 886 to "half-select" the magnetic state of
core 886 indicative of a binary "zero." It is to be noted
that the half-select current in the "X" direction through
core 885 flowed from left to right, instead of right to
left, to magnetically "half-set" core 885 toward a binary
"zero" representation. Thus, it is seen, the half-select
read current flows in one direction through the cores in
the even-numbered rows and in the opposite direction
through the cores in the odd-numbered rows.
At TIME-2, flipflop 60'55 (FIG. 67A) is reset by line
C42 so that output line MSA is thereafter FALSE. At
TIME-3, line YOW (FIG. 60) goes TRUE to again effect
energization of line YO", (FIG. 65). Thus, as Y-driver
output line YO", and Y-grounder line YG.p (FIG. 52)
are both simultaneously energi7'cd at TIME-3, a current
impulse of half-select magnitude flows upwardly through
core 886 to cause "full-selection" of the magnetic state
of core 886 to a binary "zero" representation, If it is
assumed that the magnetic state of core 886 is indicative
of a binary "one," the state of magnetization of the core
is reversed immediately following TIME-3, and, consequently, a negative-going impulse is again induced in
memory sense winding 871 (FIG. 52) with respect to
terminal 873, approximately three microseconds after
TIME-3, as bef'Ore.
As before, the negative-going impulse induced in memory sense winding 871 causes the reference input to flipflop 6055 to go FALSE shortly after TIME-3, and, consequently, flipfi'Op 6055 is triggered so that line MSA is
TRUE, indicating that a binary "one" had previously
been stored in c'Ore 886. At TIME-4, line (WR)' goes
FALSE (FIG. 66) and line WR goes TRUE. Consequently, X and Y-grounder lines XG", and TG.p are both
de-energized, and, simultaneously therewith, lines (XG.p)'
and (YG",)' are energized. As core 886 was previously
storing a binary "one," X and Y-driver output lines XDb

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and YO", remain energized f'Or ten microseconds longer
to effect "resetting" of core 886 back to its initial binary
"one" state immediately following TIME-4.
The previously-described sequence of events is now
repeated with respect to cores 887 and 888 and also with
respect to the remaining ones of the forty cores making
up address ",,,,. In the illustrative example given, as evidenced by the presence and absence of memory sense amplifier pulses (FIG. 87A), the binary number stored in
cores 885 through 888, corresponding to low-order bit
"a" through the high-order bit "d," is "0111," thus indicating that the low-order digit of the word stored in address "' is a "seven."
To summarize: Alternate cores of each memory address are magnetically set in one direction t'O represent a
binary "one," whereas the remaining cores in the address
are magnetically set in the 'Opposite direction to represent
a binllfY "one." When the core representing bit a of the
low-order digit is read (i.e., core 885), a half-select
"read" current in the "X" direction flows to the right
through core 885 at the first TIME-l. At TIME-3, a
half-select read current in the "Y" direction flows downwardly through core 885 at the first TIME-3 to magnetically set core 885 toward binary "zero." If the core
was originally storing a binary "one," its magnetic state
is therefore reversed, and a negative-going voltage pulse
is induced in memory sense winding 871, which causes
the half-select currents in the "X" and "Y" directions
through core 885 to be reversed to magnetically reset
core 885 to binary "one" at TIME-4. At the second
TIME-I, a half-select current fI'Ows to the left in the "X"
direction through core 886. At the second TIME-3, a
half-select current flows upwardly through core 886 to
magnetically set core 886 to binary "zero." If core 886
was originally storing a binary "one," a second negativegoing potential impulse is induoed in the mem'Ory sense
winding to cause the half-select currents in the "X" and
"Y" directions through core 886 to be reversed to reset
core 886 to binary "one" at the second TIME-4. As
before stated, this sequence of events is sequentially repeated from the lowermost to the uppermost 'Of the c'Ores
making up address .p.p.
26. Sense-Amplifier Strobe
With reference to FIG. 67A, inverter 4393 is effectively connected in series with memory sense winding
871, and inverter 4395 is effectively connected in parallel
with respect to the memory sense winding. As shown,
inverter 4395 is rendered non-conductive from TIME-3
to TIME-4 by line C34, and inverter 4393 is rendered
conductive from TIME-3 to TIME-4 by line C43. Thus,
as inverter 4395 is non-conductive during the time each
'Of the memory cores is being read, the inverter exerts
essentially no effect on sense winding 871; however, as
inverter 4393 is conductive during the time each core is
being read, the lower end of sense winding 871-i.e.,
terminal 872-is effectively grounded thereby during that
time to complete the circuit therethrough. From TIME-4
to TIME-3, sense winding 871 is effectively 'Open-circuited by inverter 4393 and effectively short"Circuited by
inverter 4395, thus rendering sense winding 871 noneffective at all times except for the time interval during
which reading of a memory core is to take place.
As previously described with respect to FIG. 87 A, if
a binary "one" was previously stored in the core being
read, the output of a memory sense amplifier is TRUE
after a time lapse of approximately three microseconds
after TIME-3. Thus, to prevent undesirable noise impulses from entering the system, the output of sense
amplifier 4399 is sampled, or "strobed," for a period of
approximately three microseconds, starting approximately
three microseconds after each TIME-3. Strobing is effected by a three-microsecond one-shot flipflop 6147,
which is triggered at TIME-3 by line C31, so that the
prime output thereof goes FALSE at TIME-3 and re-

3,112,394

81
mains FALSE for a period of three microseconds, after
which time the prime output thereof returns to a TRUE
condition. The prime output of flipflop 6147 is connected to the reference input of a three-microsecond oneshot flipflop 6149, so that, after a time lapse of three
microseconds after TIME-3-i.e., when the prime output
of flipflop 6147 goes TRUE-the reference output of flipflop 6149 goes TRUE and stays TRUE for a period of
three microseconds, after which time the reference output
thereof goes FALSE. Therefore, the lowermost input
line to logical AND 1163 goes TRUE only after a time
lapse of three microseconds after TIME-3, and stays
TRUE for a period of only three microseconds.
As previously described, memory addresses "A" and
"B" (FIG. 52B) have a common sense winding 891 separate from the main memory sense winding 871. l'vlemory addresses "A" and "B" have a common pair of
V-grounder lines (ABG)' and ABG and separate Ydriver lines AAD and BBD (FIG. 60), which function in the same manner as the just-described Ygrounder and V-driver lines for memory addresses
¢¢ through 99. Thus, it is possible to read and write
in only one ,of memory addresses "A" or "B" at
any given time, the same as for memory addresses ¢¢
through 99. However, as addresses "A" and "B" have
a separate sense winding from addresses ¢¢ through 99,
a word from either of addresses ¢¢ through 99 may be
read out simultaneously with the word being read out
of address "A" or "B." Because of the common X-driver
and X-grounder lines, it is not possible to write separate
words in both a memory address and either of addresses
"A" or "B." However, the same word may be writlen
in both addresses. As shown in FIG. 67 A, the output
of "A" and "B" sense amplifier 4400 is strobed by singleshot flipflops 6148 and 6150 in exactly the same manner
as memory sense amplifier 4399, as was just described
in detail. 'The ~trobed signals from sense amplifier 4430
operates a transistor logical AND HM, which triggers
flipflop 6056 in response to a negative-going impulse from
"A" and "B" sense winding 891. As the complete readwrite cycle of operation of addresses "A" and "B" is, for
all practical purposes, exactly the same as the just-described read-write cycle for memory addresses ¢¢
through 99, a description thereof would only result in an
undue repetition, which is not deemed necessary for a
full understanding of the mode of operation thereof in
view of the just-described read-write cycle for memory
addresses ¢¢ through 99.
27. Format of Instruction Words Generally
In order to perform the functions of a "general purpose" type computer, the present computer is provided
with 'eighteen different types of general purpose "instructions" which it, in a sense, "obeys" ~n order to allow the
programmer to solve almost any type of mathematical
problem. For reasons to become more apparent hereinafter, the just-described magnetic core memory stores
both "instruction" words and data words, which appear
as one and the same as far as the computer memory is
concerned-i.e., a ten-digit binary-coded decimal number-and, to alleviate the necessity of providing "plus" or
"minus" indications to identify positive and negative
numbers, a negative number is stored in the computer
memory as its complement. For example, the minimum
negative number that is effectively stored is OOOODOOOOl,
whose complement is 9999999999; the maximum negative number that is effectively store is 1000000000, whose
complement is 9{)0{}OOO{}OO. Thus, the maximum positive
number stored is 8999999999. Both data and instruction words may essentially be stored in the computer
memory either by indexing the words in the accounting
machine keyboard portion of the computer, by totaling
or subtotaling selected totalizers of the accounting machine, by reading the words from the magnetic strip portion of the ledger cards, or by reading the words from

82
punched cards or paper tapes via conventional, commercially-available paper tape and card readers.
Programming the computer consists essentially of
writing two related programs, the first program of which
5 is written for the accounting machine portion of the computer, which programming consists of designing mec:hanical stops which are placed on the form-bar portion of the
accounting machine, in a manncr fuBy descl,ibed in the
before-referred-to Patent No. 2,626,749. In program10 ming the accounting machine, the programmer decidc3
at what carriage columnar position the program is to
start and the columnar position to which the carriage is
to be moved by subsequent machine cycles. The stops
on the form bar m, the sum of these
two amounts is to be stored in memory address 52, and
the next instruction word is stored in memory address 32.
As the code number for an ADD instruction is 08, the 15
instruction word appears as illustrated below:

j

In,trnclion Word Format

----------------Sect. 1

Sect. 2

Sect 3

- - - ---- - - ~

§

W

Sect. 4

Ee( t ..J

~

~

20

---- - - ' -

After the addition operation is completed, the computer, in a sense, "looks" in memory address 32 for the
next instruction. Also, following the addition, the words
in memory addresses 42 and 5¢ remain the same as before, even though each was involved in the addition
operation. However, regardless of the word originally
stored in memory address 52 before the addition, memory
address 52 now contains the sum word derived from the
addition. The reason for this is that a memory address
is automatically cleared prior to storage of another word
in that particular address. ConsequentJy, only the sum
word is stored in the sum address.
A characteristic of nine of the eighteen instructions is
the ability to effectively increment section 3 or decrement section 4 of any instruction word. That is, if one
operation is called for which is to be sequentially performed on several words that are stored in memory locations having sequential addresses, it is not necessary to
utilize a separate instruction for each operation performed, or to build an address-incrementing loop.
An example of an instruction in which address incrementing is utilized is the "enter-key board-words" instruction, abbreviated as EKW, having a code number designation "00," and interpreted by the computer as: "The
words subsequently indexed in the accounting machine
keyboard are to be sequentially stored in memory address
locations X through Y, where X and Yare specified in
section 2 and section 4, respectively, of the instruction
word." Thus, if several sequential entries are to be
indexed in the accounting machine keyboard, it is, of
course, obviolls that these successive entries must be
stored in adjacent memory address locations. If it were
necessary to utilize a separate instruction word for storage of each of the keyboard entries in a designated
memory address, ten instruction wOl'ds would then be
necessary to store ten entries in memory. However, with
an address incrementi ng instruction, all ten entries are
sequentially stored by the use of only one instruction
word. This incrementing feature not only simplifies programming, but also reduces the required number of instruction words necessary for completion of a given program. When utilizing an instruction with an addrcssincrementing format, the programmer specifies, in section
3 of the instruction word, the memory address of the first
word on which an operation is required, and specifies, in
section 4 of the instruction word, the memory address of
the last word on which an operation is required. The
only restriction is that the address specified in section 4
of the instruction word must be eql1al to, or greater than,
the address specified in ~e('tion 3. Thcrenficf, the Cl'nlpuler sequentially generates each of the address locations

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between those two 5pecified, even if the original instruction word is no longer stored in memory. However, after
the instruction has been executed, the original instruction
word may remain in memory unchanged, if desired.

28. Format of Enter-Keyboard-Words Instruction
Word (EKW-OO)
The EKW instruction is utilized when amounts are to
be entered, and thus stored, in the computer memory,
either by the words being indexed in the keyboard or by
a preselected totalizer within the accounting machine
being totalized. With only a single EKW instruction,
from one to one hundred different amounts may selectively be stored in sequentially-ascending memory addresses. Howc,vcr, in order to enter the amount indexed
in the accounting machine keyboard, a machine cycle,
of operation must first be initiated. The particular motor
bar of the machine to be depressed to initiate a cycle of
cperation thereof is specified in the instruction word by
the programmer. In this way, the programmer is assnred that the correct motor bar is automatically depressed for each amount entered. Hence, there is prevented the possibility of the accounting machine carriage
becoming out of synchronism with the program in the
computer due to the operator's depressing the wrong
motor bar. When the computer is "ready" to carry out
on EK'N instruction, the "enter-keyboard-words" lamp,
illustrated in FIG. 1 as EK, is illuminated. The operator
thereafter indexes the amount into the accounting machine keyboard and then depresses the "resume-programbar." Immediately thereafter, the computer automatically effects depression of thc particular motor bar specified in the instruction word. Consequently, a cycle of
operation of the accounting machine is thereby initiated,
and the amount just indexed in the keyboard thereof is
entered into the selected memory address.
In order for the programmer to prepare an instruction
word which instructs the computer to enter words into
memory, from either the accounting machine keyboard or
tbe totalizers therein, the two-digit decimal number for
each of tbe five sections of the instruction word must be
specified, the composite ten-digit decimal number thereafter representing the desired instruction word, as before
stated. l\S the code number designation for an EKW
command is "00," the two decimal digits in section 1 of
the instruction word are, likewise, "00." In section 2 of
the instruction word, the high-order decimal digit therein
designates the motor bar code, and the low-order decirnal digit therein designates the decimal point lamp code;
section 3 designates the memory address in which the first
word entered from the accounting machine is to be stored;
section 4 designates the memory address in which the last
word entered is to be stored; and section 5 designates the
memory address location of the next instruction word in
the program. Listed below, in chart form, are the various codes specified by section 2 of the instruction word
and to which the computer is responsive:
Section ~ of ihe Instruction Word

GO
High-Or(ler Digit. of Section 2
IIIol.or·Bur Cock

(;5

70

Ox TOllCh UPlx'r ::\Ic"ltor Bnr
lr Holel U [lpl'r 1\10tor Ihr
:.;x 'rou~'h T"> 1i (lrogram

with dednlal point uetwcell
columns 2 and 3

~f des.ired, the programmer may instruct the computer
to rIlummate a preselected one of the three decimal point
iar:1PS to give a visual indication on the accounting machine keyboard ns 10 tbe decimal point location for the
amount 10 be indexed, decimal point lamp P¢ being lo7.) cated on the kcybmml between amount rows 2 and 3,

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85

in the dcci;n~l point lamp code position in the instrucdecimal point lamp PI being located bctween amount
(:Ga wOTd. the preselected motor bar is automatically oprows 5 and 6, and decimal point lamp P2 being located
cn1eU by the computer as seem as the carriage is stopped,
between amount rows Sand 9.
EVe') [hough the resume-program-bar was not depressed.
When the decimal point is desired betwcen rows 5 and
The alltomatic-rcsume-prooam instruction, in effect, de6, the computer illur;:linates lamp Pi between these rows
pr,,~scs the resume-program-bar automatically, and the
even though the amount 0,465,85 is printed as 0,465.85,
word printed out has its decimal point in the normal poand, when a decimal point is dcsired bctween rows 8 and
sition. }'or cxample, suppose that a totalizer is to be sub9, the computer iJiuminat8s lamp P2 between thesc rows
totaled and the contents thereof slored in memory address
even though the amount 0.465,855,55 is printed as
10 62. Assuming that a middle rotor bar "touch" operation
0,465,855.55.
is ues;rcd, n'on~ with an automutic-resume-program operAs an example, suppose that three amounts are to he
alion, the instruction word appears as "00 23 62 62 48,"
slored in memory. The first amount is desired to be
the space between each pair of decimal digits indicating
stored in memory address 45, the second amount is dethe five sections of the instruction word. As soon as the
sired to be stored in memory address 46, and the third
amount is desired to be stored in memory address 47. 15 cDlTiage comes to rest on a stop, the middle motor bar
'17 is dcpr;:ssed, regardless of which direction the carriage
Consequcntly. the desir<:d address of the first word to be
was moving when the stop was engaged. Thus, the autoentered is placed in section 3 of the instruction worc1,
mat!c-resumc-program instruction eliminates the need for
and the desired address of the last word to be entered is
aulO!:latic stops for the carr;ag~. The numeral "6" in
placed in sec lion 4 thereof. It is also assumed that, when
the resuine-progrQm bar is depressed, it is desired that 20 the 1110lor bar code specifies that a motor bar is not to
be operated and is used only for an "enter-card-word"
the compuler automatically initiate depression of the
instruction (ECW), which is to be more fully described
middlc motor bar 27 for a "touch" operation (code 2x),
hereinafter. Since a machine cycle is required to enter
thereby effecting a cycle of operation of the accounting
the indexed amount from the keyboard into the computer
machine and tln:s enter the first amount into memory.
Further assumed is that the decimal point lamp located 2;j memory during an EKW instruction, the numeral "6"
placed in the motor bar code has no significance in this
between rOViS 5 and 6 is to be illuminated (code xl) and
instance.
the next instruction is located in memory address 2.
Therefore, the instruction word appears as shown below:
29. Format of Print-Out-Words Instruction Word
(POW-Ol)
Reet. 1

--c;-

Sect. 2

Beet. 3

-~~~ --~~--

Sect. 4

I Sect. 5

30

-:;--1--;-

If thc first amount to be indexed is 0.025,00 and enterkcyboard-\vords bmp PI is illuminated, amount key #2
of row 4 and amount key #5 of row 3 are manually depressed first. Thereafter, the resume-program-bar is manually depressed, and, consequently, the computer automatically effects depression of the middle motor bar 27
for a "touch" operation. The amount thereafter printed
,,-ppears as 0,025.00. If the printing of cents ".00" is not
desired, a particularly designed stop is placed on the form
bar to suppress printing thereof.
When a negative amount is to be entered into the computer memory, rever"e key "REV" is initially depressed.
This not only causes the amount to be printed with a
"diamond" symbol printed to the right thereof, but, in
addition. causes the complement of the number to be
stored in memory as a "credit balance." Negative
amounts previollsly stored in the totalizers of the accounting machine arc automatically stored in the computer
memory as complements thereof.
There are three ways to total or sub-total the amount
in the computer memory by means of the EKW instruction. If the carriage of the machine is stationary and the
non-select key "NON SELECT" is depressed, both the
desired totalizer and the particular type of 2" or ".;:6" causes the card to be positioned for posting in the middle area; and an "x3" or "x7" causes the
card to be positioned for posting in the lowermost area.
This permits the words on the card to be grouped for
simplicity of progrumming and mathematical op;:rations.
For exrunplc, a ledger card designed for payroll app!ication usually has two posting areas whereby relatively fixed
dnta, ,~ush as el]~p!oyce's dock number, number of depen,lenL. carnin£, r:'ic, dcdllctiom;, etc., ;']'e po, ted ill ::n
~,rca at th,'~ top of the cani, v.;h'.:reas C'lnployce's ~arningss

3,112,394

29
taxes, and deductions for each pay period are posted in
the arc a of the main body of th·;: Cc: t·,!. In audition to
being printed 0;1 t1lC face of the c:}rei, this inform:Jtion
is also mag!1ctically recorded on the m,,:;nctic strip cf the
ledg::'f c"rd.
For p~)T()n posting, for CXaJllp~e, an ".\"2" or H.r6" is
placed in the lO'N-order digit position of section 2 of the
instrnclion v/ord. I-I{)'v/evcr",!f it is dc:,;ired to chanr;c the
fixed data at the top of tl~~ card, a;1 "xl" or ".\5" is placed
in the lov-i-order d;git position of section 2 of the instruction word.
In apJ.yrol! appiicatio!1 in which the words magneticalIv recorded on t!"le IeclQcr c~rds are indicative of ::n employee's e:Jrn:ng record: the cards are s through 19, and so on for
tl:e third and fourth cards, until (he fhe words magnetically recorded on the iHth cJrd arc stored in the addresses
49 through 44, thus filling tlle entire string of addresses.
Even though tile contents of the fifth card fills the remaining string of addrcsses as specified in the instruction word,
the last card is ejected al~o becrl1lSc of the '"eject-card"
instruction code (x8) which app<:urs in thc low-order
digit position of section 2 of the instruction word. After
the fifth card is ejected, if the computer is operating in
:..J ill S~:­
tion 2 of the instruction word.

92
Afier GlC eatire recording op.:ralion on the ledger card
is completed and the card i" ejected, (he carriage remains
in home position, Wdl the paper guide open. However,
if ti1e next step in the p~'ogram n::ccss~taLl.;s t.he cnrriaee
5 'to be moved away from homeposilion, the paper guide is
first closed, either by an instruction involvillg a molor
bar, or by manual (kprcss;on of the carriage open· close
key.
lO

32. Format of SJ!lFT Instructioll Word (SllF-04)

The "shifl" ins!.ruction is utiJ;7.ed to effect the shifting
of a word stored in memory by a predetermined number
of decimal digi1s in either direction. Thereafter, the
shifted word is seleclively stored either in the same
1:, address or in another selecled address in memory. The
code for the SHF instruction-i.e., 04-is in section 1
of the instruction word; in section 2 of the instruclion
worJ is placed the "shift" lllld "direction" code; in section
3 is the address of the wore! to be shifted; in section 4 is
~O the address in w/:;ch the result is to be stored; and in section 5 is the address of the next instruction word. The
"shift" and "direction" code for an SHF instruction is
shown below, w;lcre "/2" sp~cifies the number of shifts
from zero to nine.
:.:;;
OQ-No shift.
2n-Shift left.
3.'l-Shift right and round.
41l-Shin right.
30 51l-Shift right w:thout preserving sign.

3;;

40

4.ii

50

55

GO

Gil

70

75

As lln examrlc, lln instruction word capabJe of initillting the copyin~ of a word from memory address 5", into
memory :.ddrt:ss 79, with the next insIruction word located in memory address RJ, is 04 00 50 79 81. Since a
"00" code is placed in section 2 of the il1'ltruc,jon word,
the word stored in addr~ss 5\\ i~ simply stored in address
79. After the instruction has been carried out, the same
word appears in bo;.h of :~ddresses 51' and 79. The above
inslruc~ion word prin'ed out appears as 4,005,079.81.
Thus, it is seC';"!, an instnlction 'Nord actually appears :.s
a data word when printed out, with both types of words
being stored in memory in exactly the same manner as
previously mentioneu. In fa,t, it will become more ob\ious hereinafter that an instruction word is capable of
being 2,rithmeti'.:ally modified in the same manner as a
data word.
In the previous portion of the description, each of the
instruction words h~{s been illustrated as consisting of five
distinct groups of numbers of two decimal digits each.
This was done in order to emphasize the separate functions of each of the five sections thereof. However,
hereinllfter, 111l instruction words will be designated in
exactly the same manner as they appear while stored in
memory.
In the above example, suppose that the word in addre:'s 5'D is 0000000]55 and is to be shifted three placcs
to the i~ft, which, in efIect, mUltiplies the word by one
thousand, "and the result is to be :'tored in address 79.
In this inst211ce, an instruction word capable of initiating
tllis particular sClllience of events is 0423507981. After
being shift~d three plae~s to the left, the word subsequently stored in addrc'~s 79 is GOOD 155000. However, suppose inst'cad that ihe word in adJres:; 5 is to be shifted
one plJce to the right, whkh, in eff8ct, multiplies the
won I by onc t~nth. In tbis instance, the instruction
word is 044150798 l. Aflcr being ,;hiflcd one place to
the right, the word sllb~equcntly stored in address 79 is,
in this inst:wce, O()00000015.
HI" ulacin" tbe code designation "31l" in section 2 of
the "in:;t[l!eti~n word, the \;:ord being oj"lerafed upon is
first shifled to the r1:.;ht "1l-1" times, and thereafter
the word OO()O()G0003 is added thereto to round off the
Jew-orJer di[:il [liereof. FollOlving the uddilion, the
word j,; shifted one mere di 'fit to Ihe rirht. Tn the previ'olls example, if ti1C wonf initially stored in uddrc5s

3,112,394

93

94

from nlE'!TIOry nre add~:d ~lijd tbe sun) stored in 2I~ y
5,/> (i.e .• 0000000155) is to be shifted right two placeq
specilkd address thereof. The two 1','0;-(\5 ~re aorkd i:1
and then round.:d, an instruction word capable of iaitiataccordance with the klWS of ~llgebra whereby the add,ti"n
ing this sequence of events i~ 0432507')3 1. The word in
of two positive words result:; in a positive sum; the ::.uuiaddress 79, after being shifted and rollnd,::d, is new
5 lion of two nC3"tive numbers results in a ne:;ativ,:; sum;
0000000002.
ami the addition of a posilive and a negative word result,
When a n-cgative word is ~;hifted to the right in responRe
in a diffC!ence between the two words. the dilI"rcnce
to a "3n" or a "4n" code in section 2 of the instruction
word having an algebraic sign of the operand having the
word, 9000000000 is adckd to tIle word each time it is
larger absolute value.
shifted, in order to preserve its sign. However, with
In section 1 of an ADD instruction word is the code
a ·'51l" code in section 1. of the instruction word, the 10
desi:;nation therefor, i.e., 08: in section 2 thereof is the
word is shifted to the rish! without it~ sign being prememory address of the "addend"; in section 3 thereof
served, and, wh~thcr the v,'ord is positive or neg::.tive,
is the memory address of the "augend"; in section 4 is the
a zero is effeclively fill;:d in as the tenth·order digit foladdress in memury of the sum; and in section 5is the
lowing each shift.
Jij memory address of the next instruction word to be car33. Format of CLEAR-llfEMORY-ADDRESSES
ried out.
Instfllction IYord (CMA-05)
Thus, if the addend data word :;tored in memory ndIn a CMA instruction, use is again made of the ability
dress 17 is to be added to the augend d"t:l w'ord store,l
of the computer to increment addresses. As a result.
in address 19, (he sum data word is to be stored in
any number of addresses are cleared with the use of 20 memory address 21, and the next instruction word is
only one instruction word; when an address is cleared,
located in memory address 22, :m instruction word caa word of all zeros is stored therein. For a CMA inpable of initiating this particubr sequen2C of events ic;
struction, the code therefor-i.e., 05-is in section 1 of
0817192122. Since negative wmds are stored in mcmL'ry
the instruction word; two zeros ['fe in section 2 thercof;
as complements thereof, the addition of a positive word
in section 3 is the memory address of the first word in the 25 and a negative word, or the addition of two negativc
string of addresses to be cleared; in section 4 is the adwords, results in the correct sum thereof. For eX:lmple,
dress of the last word in the string of addresses to be
if +222 is to be added to -111. the addition operation
cleared; and in section 5 is pl::!ced the address of the next
c:1 lTied Ollt within the computer is 9999999889 plus
instruction word to be acted upon.
OOOOOO()222 eqmls 0000000111. lf -- 222 is to be :Judd
As an example, 2,n instruction word capable of initiat- 30 to -111, the ::.ddition operation carried out within the
ing the clearing of memory addresses 1¢ through 2.
computer is 9999999889 plus 9999999778 equals
with the next instruction v'Iord being stored in memory
9999999667, which is the complement of -333.
address 9¢, is 0500102090.
37. FOllllat of SUBTRACT 1m/ruction IVai'll (SUIJ--09)
34. Format of MOToa DA R Instruction
35
Hiord (At IJ-06 )
Like the "add" instruction, the "subtract" im;crllclion
has a four-addrcss forrn~lt rind obtains ~h',; dUTct"cncc b.::The motor bar instructicYl effects the desired depres·
t\veen any t\VO \vords in accordanCe v\:iih the hlV/S of alsion of a preselected motor bar to initiate a preselected
gebra.
cycle of operation of the accounting machine portion of
Tn section 1 of a "suulract" instruction ",'ord is ,he
the computer. In section 1 of a mo['or bar instmction
word is the coJe nllmbtr "06"; in section 2 are the motor 40 code therefor, i.e., 0.9; in section 2 thereof is tbe memOl '.'
addre;;s of the "millllcml"; in section 3 is the memory :].d~
bar and decimal point codes, the same as previously
dress of the "subtrahend"; in section 4 is the 111<:;,,01 v
described with respect to the EKW instruction; zeros are
address of the "rcmai11d~r"; and in scctioa 5 is the rn''':rJ.;in both section 3 and section 4; and in section 5 is the
ory address of the ncxt instruction word.
address of the next instruction word. Tn a MB instrucSuppose that the word in address 19 is to be subtrac!sd
tion, :!n "x3" eode in section 2 of the instruction word ·10
from the wO;'d in ~ddre.'3 17, the rcm:d:lllcr sLOred in ;-,dhas no slgnifica;H.:e, as, in this instance, an "6x" code is
dress 21, (}r:d the next instruc~jon \Jv'oru stored in adJrc:~s
p!aced therein to effect ,:n "auto111atic·resume-program"
22. In this in~)tan(e, an iGstruction 'word capable of
operation.
iili,iating this parlieu!nr sequence of c\".~nts is 0917192 [22.
If a normal "dollar" d~cimnl point "nd a middle motor
bar "touch" op~ration is desired, wilh the next instruc·· 50 According to the bws of algebra, \\ hen a negative word
is subtr:lctrd from a positive word, th:: absolute valli':;;;
tion word being stored in ml!mory :iddress GG. an instrucof ,he two words are added, and th<~ si;n of their sum
tion word capable of initiating thi:; p,\rticular sequence
i~ posi(~ve. Thus. if the word 0000000222 is stored in
of events is 06200000(,6. Comc(jucntly. as soon as the
addre,os 17 and the complement of --4'14 is st0red in
carriage reaches a stop. either by tabulution, carriag~
return, or depression of th~ "non-select" key, the des- 5;3 addfcss J9, the computation carried Gut \'.'iihin (t;;::
computer i': 9999999556 subtracted from GJ0DOOO:'22 reignated molor bar is operated, and the computer prosults in a fC'lna:ndc!" of 0000000(:66 to bc ston:-o i;1 8dceedsonw3rd to carry alit the (]ictatcs of the next indress 21. If a positive \vord is suDt:':1ct!.:d from a ncp.astruction word.
tlve word, the remaindcr is a ne.s[,tivc word whose (lb35. Furmat of STOP ll1S1ructioll IVcrd (STP--07)
GO solute value is the Sllm of the abso;ut~ ,".dues of the
two operands. Thus, if the compl~mcnt of --222 is
When a "stop" instruction is given to the computer,
stored in address 17 and the wod oeoO(,IJ()-I44 is ,Icrcci
ail operations therein effectively come to a standstill,
ill address 19, the computation carried out is 0000000"1'1·[
and lamp HI. (FIG. 1) is iilllmina:ed. However, when
snhtracted from 9999999778 f-;ives a rcrnahldcr of
the rcsllme-program-bar is dcprcs:ccd, l,\mp HA is turned
off, and the computer proceeds to carry out the next G;3 9999999334 to be stored in address 21. 9999999334 bcirn::
the complement of -666; if the comp];:r:1ent of
instruction. The code for a "stop" operation-i.e., 07is stored in address 17 and the complemen~ of --444 is
is in section 1 of the instruction word; in sections 2, 3,
stored in ~ddres~; 19, the computation c:mi;;d is
and 4 thereof are z~ros; and 1;] section 5 is the address
9999999556 subtracted from 999999977S gi';(;.~ J rem;;inof the next instruction word.
If the next instruction word is located in memory 70 clef of 0000000222 to b~ stmcd in address 21; and, if
the Inst-tnentioned nlinucnd and subtrnh.2nd (ire ini..::raddress 5, an instruction word of this type is
ch:m::ccd, the computation c2rricd alit is 9,)9999977S sub0700000050.
tmcted from 99999995:,r, t'ives a rcm~linc!cr of 9999::199773
36. Format of ADD fllstrllctioll Word (ADD-08)
to be stored in rld,Jrcss 2 J, 9S'99999 ;'78 b~~n2 the con1plcIn carrying out an "ADD" instruction, tViO \.<'Ol ds bLeB 75 meat of - 222.

--7.22

3,112,30·1

95

Ol.~t or

96

tht! abov.;-d.::;cri0~J i'\.PN jn~~li Ui•..:Liurt, th~ tivc sun13,
resulttn2 froD1 the adJilion of the fivc p~drs of nUInbcrs,
'!'he "sun1" in~,truc~ion is another of the instructions
ure resp~cli\'cly ~~ored in nlCD1cry a.::idre:)~es 68 through
""hich takc (:dv;:titagc cf t!lC 8.ddrc~~-increnlentil1g ability
72, while th(; flrst word of each of the five pairs of words
of the COm~H!ter and is l;tiliz:~d to effect algebraic c:.ddition
I e~,p~ctivejy rCllwln in a corresponding 011e of menlory
of a phu"a 1ity of words located in a corresponding plu- [) .:udrC's"c~i Lj through 19.
nllity or scque:11i:11 ~ldJres~~es; thereafter, the total is stored
The AFN instruclion lll~y DC LitilizeJ, for example, in
in any preselected acldress in m~mory.
a p~yroll application where it is dCl.ircd to add an emIhG code number [or the SUM instruction-Le.,10--is
ployee's deductions, such as "Community Chest," "Union
i:1 ~ec(jon 1 of the instruction woru; the memory ,;dJreos 10 Du~s," "FICA," etc., to each of the respective weekly
in (0 which the totd is to be stored is in section 2 thereof;
;'lcuI11ulations thereof. All of such ndditions are automathe n,emory "ddn:ss of th", first word in the scri'c3 to be
tic~lly performed with only on~ instruction word, due
",J:lcd is in section 3; the memory address of the last
to the fact (hat the audrcsscs in section 3 and section 4
'.Yore! in the se~ks to be add"d is in section 4; ,md the
of the instrllctioa word are aut(,mutically modJicd by the
memory ~,Jdrcss of the next ins:rncdon word is in section 15 computer during the execution of the instruction. Also,
5 thcr~of.
as ~vHl be seen later, due ,to the bet that an instructioa
SUPpOSI:" that all of the \ovon.ls locntcd in addresses 81)
word is stored in a "rcgister" while the computer is exthlOliCh 84 ,",e to be added, the sum is to b~ stored in
ecuting tbe jnstru;:tion~ the ori2;inal inslruction \vord nOf-pondJ to the Il:~nl0r:l nddrcss of the
SUITt, is in scc~ion 4 of the instruction \vonl, and, following the addition, th:.; ;"d;Jrcss jn s~ction 4 is C:kcrcH1c:lted
hy "enc" to obt~:b the address of the second word of
the foJ:oviing p:lir of word", whkh address also correspo'lcb to the memory andress into which the ~um dc! ived
from the follmving addition is to be stored; ami in section 5 of the imlru~tion word is the address or the next
instruction word.
Suppose tint "five" pairs of viords are to be added,
the Erst word of tile fir,,! pair beillg stored in add res::;
15, the sccon~1 v:or,J of (he fir:;t pair being stored in address 72, ard the ,",ext instruction word being stored in
rtddrcss 88. /\.:1 i:~jstn!ction Vlord capC1.ble 0[- initiating
this par!ic:ular sequence of events is 1105157288.
Tn carrying out the APN instruction, the sequence of
events is as follows: The word stored in Inemorv addre,s
15 is added to the word stored in memory address 72,
and the 5111:1 resulting from [he addition is stored in
memory ~1ddrcss 72; thereafter, tb~ address specified in
section 3 of t11e instruc:io tl word is incremented by "one"
and thus becomes "address 16," instead of aduress 15,
and, simuJt:lTIcoHsly therc'lvith, the address specifkd in
section 4 of the instruction word is decremented by "one"
and thus beccn1es "alldrc:s 71" instead of address 72;
thereafter, (he word in ;lddress 16 is added to the \vord
in address 71, t:ud the sun1 resulting frf'm this second 2ddilion i:; stored in c.dd;-c:Js 71; thereafter, the Olddi'cSSCS
specified i:l section 3 Ute! ~~ction t, of the instruction word
are respectively incremented and decremented by "Oi1C,"
and, thcrc~lf(er, the word stored in address 17 is added
to the 'Nord stored in address 7 , and so on, until the
word stored in address 19 is added to the word stored in
adJresc; G8 and the sum resulti!lg from the last addition
i:; stored in address 68.
It is to be nolcu lliat, lipan compktion of the carrying

40. Format of J\1ULTfPLY-DOLLAR-DECIi'dAL Instruction Word (MDD-12)
25

30

3':;

40

.1;)

r50

o;}

(JO

(j,j

There are two multiply instructions which are utilized
by the present computer. The first multiply instruction,
"multiply-and-store-dollar-decimal" (MDD), is a "fixed
decimal point" multiplication. That is, tlYO words having
a maxirnllm of ten decimal digits each are multiplied tobether to obtain a proJuct thereof haying a maximum of
twenty decimal digits. After tbe rnultiplic:ltion, the prodlIct is shifted one decif'.1:.l1 position to the ri".ht and effectively, "five cent>" is th811 added thcre(u "ie!' mde'r to
round eff the low-oruer digit thereof. Thercafkr, the
product is shifted one Illorc dccirn3i position to the right,
anJ the ten low-order di2its of the p,oduct r,re stutcd
in the "product" address.
111e numerical code for MDD-i.e., "12"-is in sect:on
1 of the instruction worJ; the aduress of the m!lltipli~,\Dd
is in section 2 of the instruction \\ioru; in section 3 tlKfeof is the address of the multiplicT; in ~eclion 4 is the audr~ss of the product; 2nd in section 5 is the ndJrcss of the
next instruction word.
If it is desired for tbe vlOrd in address 41> to be nlultiplied by the word in addres:i 5, the product i, to be
storeu in address 95, a[!d the n,~xt instruction woru is
stored in address G. An instruction word c~p3.ble of
initiating this particular sequence of events is 1240509560.
According to tbe laws of aj"ebra, the al"cbr3ic si"n
of the product depends on the sign of the tv"o"·words ml~!­
tiplicd. That is, the algebraic; sign of tbe product of
two positive or two negative words is positive, while the
algebraic sign of the product of a positive word and a
negative word is negative. The J'v1DD instruction is a
special form of the "multiply-and-shift-producC' imtruction (MUS), to be described next, due to the fact that
it is possible to obtain essentially the same result with
either imtruction. However, upon compktioll of a MDD
instruction, both factors are retained in their original
addresses in memory. It is to be noted that in a MDD
instruction, the address in ~eelion 3 of the instruction
word should not also be [he address into which the product
is ,to be stored; otherwise the product is incorrect in this
instance.
41.

Format of MULTIPLY-AND-SHIFT Illstructioll
Word (MUS-H)

The second multipJy instruction, "multiply-and-shiftproduct," in contrast to the MDD instruelion, initiates
70 a variable-decimal-point type of multiplication. That is,
the two words are first multiplied togetber to obtain the
product thereof, which is stored in a twenty-digit register.
TIlereaftcr. while in the re,ni:;t::r, ,the pro(luctis shifted
either to the left or to th~ rigbt ;1 predelermineJ number
75 of decimal digit position:;. Af(c;;' being shifled, the ten

3,112,394

98

97
low-order digits of the shifted product are placed in the
product address in memory.
It is to be noted that the absolute values of the two
words, without regard to any decima,j point locations,
are mulliplied together to obtain the product. Thereafter,
thc product is shiil2d either to the left or to the right
by a maximum of nine decimal digit positions and t!u:n
"rounded" jf desired. As only the ten low-order digits
of 1:1e shifted product are stored in memory, :dl digits
above the ten low-order Digits are essentially ignored.
In section 1 of an in~inlction word for initiating a
MUS command is the code therefor, i.e., 13; in the highlow-order digital position of section 2 is the product
"number-of-shifts" code; in the high-order digital position of section 2 is the product "direction-of-shift" code;
in section 3 is the memory address of the mil1tip~icHTIl!;
in section 4 are the memory addresses of the multiplier
and the product; and in section 5 is the memory address
of the ne;.;,t instruction word.
Suppose th~t the word in address 78 (02222000ClO) is
to be multipHed by the word in address 89 (00COOOOO{)4),
the prodl;ct is to be shifted five places to the right, and
the next instruction word is stored in address 99. Thus,
an instruction word capable of efI.::cting the carrying out
of this particular command is 1345897899. Thc product,
berore being shifted in the direction of and by tbe Humber of places specified, is 00000000000888800000. After
being shifted fivc places to the right, the product stored
in address 89 is 0000OO88SS.
Again, according to the laws of algebra, th.: algebrD.ic
sign of the p;-oduct depends upon the sign of th<~ hvo
words being multiplied; the product of two positive or
two nc,edtive words is positive, while the product of a
positive WOH! and a nes;ative word is n·:gativ'e. It is to
be noted that the positive or negative product stored in
memory after the shifting operation is completed should
not exceed the capacity of the computer memory, Even
though the multiplicand may have essentially any value,
the absolute value of the multiplier, however, should not
be greater th,m 999999999. It is aLo to be noted that
the multiplier is effectively "lost" following a :MUS command. Therefore, to retain the multiplier, it is necess:uy
that a "shift" instruction precede the MUS instruction
in the program.

43. Formal of TAKE-ALTERNATE-INSTRUCTIONIF X;:;;Y Illstruction Word (CFM-15)
5

10

15

20

25

30

There are certain instances when it is desired for the
computer to carry out an alternate instruction if a certain
word in memory is equal to or greater than other particular words in memory. With the use of a CFM instruction, it is possible for the computer to algebraically compare the absolute magnitude of words located in two predetermined memory address;;s, and to use either the memory address specified in section 4 or the memory address
specified in section 5 of th~ instruction word for determining the next instruction word in the program, depending upon the result of the comparison.
In section 1 of the instruction word for effecting a CMF
operation is the numerical code therefor, Le., "15"; in section 2 thereof is the memory address of the first word
(x) to be compared; in section 3 is the memory address
of the second word (y) to be compared; in section 4 is
the memory address of the next instruction word if the
word in the memory address specified by section 2 is
equal to or greater than the memory address specified by
section 3; and in section 5 is the memory address of the
next instruction word if the word in the memory address
specified by section 2 is less than the word in the memory
add ress specified by section 3 of the instruction word,
Thus, if the first comparison word (x) is in address
46, the second comparison word (y) is in address 5""
the next regular instruction is in address lcp, and the
alternate instruction is in address 75. An instruction
word capable of initiating such a CFM operation is
11546507510.
44. Format of TAKE-ALTERNATE-INSTRUCTIONIF X".foY Instruction War;! (CFE-16)

35

The CFE instruction is somewhat similar to the justdescribed CFM instruction, with the exception that the
CFE instruction compares the two words only for
equality.
In section 1 of an instruction word capable of initiat40 ing a erE operation is the code "16"; in section 2 and
section 3 thereof are the memory acldresses of the two
words to be compared; in section 4 is the memory address
of the n~xt instruction word if the two words are of
unequal magnitude; and in section 5 of the instruction
45 word. is the memory address of the next instruction word
42. Format of DIVIDE Illstruction Word (DIV-14)
if the two words are of equal magnitude. Thus, if the
two words to be compared are locatcd in memory adThe "divide" instruction is utilized to effect the dividdresses cp5 and ¢6, the regular instruction word is loing of one word by another in order to obtain a quotient
thereof, with both the dividend and the divisor being
and the alternate instruction
cated in memory address
50 word is located in memory address 78. An instruction
treated as whole numbers during the division.
word capable of initiating this type of operation is
In section 1 of an instruction word for effecting a DIY
mathematical operation is the code therefor, i.e., 14; in
1605067810.
section 2 thereof is the memory address of the dividend;
45. Format of ENTER-PUNCHED-TAPE Instruction
in section 3 is the memory address of the divisior; the
Word (EPT-17)
memory address of the quotient is in section 4; and in 55
The
"enter-punched-bpe"
instruction utilizes the ability
section 5 is the memory address of the next instruction
of the computer to increment memory address designaword.
tions in an instruction word. Consequently, by the use
As an exam;)le, if the word in address 43 is to be diof but a single instruction word, any portion or even the
vided by the vwrd in address 57, the quotient is to be
stored in address ¢2, and the next instruction word is 60 entire capacity of the memory is selectively stored with information read from a punched tape. The particular
stored in address 88. An instruction word capable of
type of tape reader utilized by the present computer is a
efi'ecting tbe carrying out of this particular command is
wen-known commercially-available photoelectric type
1443570288. As before, the sign of the quotient is algesuch as that designated as Model 903 and at present manbraically determined by the algebraic signs of the two
operands; if the two operands are of the same algebraic 65 ufactured by Potter Instrument Company, Inc. As the
construction and mode of operation of such a tape reader
sign, the quotient is poshivc, and, if the two operands
are well known to those skilled in the art, a detailed deare of dissimilar algebraic signs, the quotient is negative.
scription th~reof is not deemed necessary for a full and
It is to be not.:d that, essentially, there is no limit to the
complete understanding of the present invention. Howmaximum value of the dividend (x). However, the highorder digit of the absolute value of the divisor (y) should 70 ever, a brief description of the format of the decimalcOlled digital information on the punched tape is given
be a "zcro," and the absolute value thereof is 999999999.
herein.
Also, in this instruction, the address of the dividend (x)
With reference to FIG, SSC, the paper tape llsed in
should not be the same as that in which the quotient is
conjunction with such a tape reader is effectively divided
to be stored; otherwise, the quotient is thereafter equal
75 into eight equally-spaced "channels," exclusive of "clock"
to 0010000000.

1""

3,112,394

99
ch:mnel (eLK), which are disposed paralicl with respect
to each other and with respect to the length of the tape.
A combination of perforations punched in predetermined
ones of the channel positions, and in a line perpendicular
to the length of the tape, collectively represent a particular decimal digit or symbol. For example, an absence
of a perforation in each of channels 1 through 4 represents the decimal digit "zero," assuming, of course, that
a perforation appears in the clock channel "CLK"; a
single perforation in channel 1 represents the decimal
digit "one"; a single perforation in channel 2 represents
the decimal digit "two"; a single perforation in channel 3
represents the decimal digit "four"; a perforation in channel 1 and channel 2 collectively represent the decimal
digit "three"; and so on, so that a perforation in channell and a perforation in channel 4 collectively represent
the decimal digit "nine." It is also to be noted that a
perforation in channel 6 and a perforation in channel 8
collectively represent an "end-of-frame" symbol (EOF),
and a perforation in channel 6 and a perforation in channel 7 collectively represent an "alternate-instruction"
symbol (AI).
In the operation of some of the various types of conventional paper tape punches, an odd number of holes,
exclusive of clock channel (CLK), is required to be
perforated in the tape to collectively represent a data
digit or a symbol digit. Thus, if a data digit or a symbol
digit is represented by an even number of holes, as shown,
a hole is additionally perforated in channel 5 in order
that an odd number of holes collectively represent that
particular digit; if the number of holes is already an odd
number, an additional hole is not perforated in channel
S. Thus, in the above tape, a hole is additionally perfor:lted in channel 5 whenever the holes perforated in
data channels 1 through 4 collectively represent either a
"zero," a "three," a Hfive," a Hsix," or a "nine. H Also,
a hole is additionally perforated in channel 5 whenever
the holes perforated in symbol channels 6 through 8 collectively represent either of the end-of-frame or alternateinstruction symbols.
Therefore, whenever a hole is perforated in channel 6,
as for symbols (EOF) and (AI), the digit is not considered as '\lata." Consequently, data punching errors
are cancelled simply by punching a perforation in channel 6 along with each incorrectly punched data digit, and
the computer is thereby instructed not to consider these
data digits. A perforation in both channel 6 and channel 7 effectively causes the computer to immediately stop
the tape when the tape reader "senses" the "alternateinstruction" symbol (AI) and to carry out the "alternate"
instruction specified in the instruction word. A perforation in both channel 6 and channel 8 causes the computer
to immediately stop the tape when the tape reader senses
the end-of-frame symbol (EOF) and to carry out the next
"regular" instruction specified in the instruction word. A
"frame" may comprise from one to one hundred words
ten decimal digits in length, with each word normally
punched one digit at a time, starting with the high-order
digit and ending with the low-order digit. However, each
word is thereafter sequentially read one digit at a time,
normally starting with the low-order digit and ending
with the high-order digit.
In an instruction word capable of initiating an "enterpunched-tape" operation, the code designation therefor
(i.e., "17") is in section 1 thereof; in section 2 is the
"direction code"; in section 3 is the memory address into
which is stored the first word read; in section 4 is the
memory address of the alternate instruction; and in section 5 is the memory address of the next regular instruction.
The "direction code" in section 2 of an EPT instruction word determines the direction in which the tape
is to be translated past the reading station. That is, a
"00" causes the tape to be translated in a forward direction to permit the reading of both data and symbol digits,

[;

10

13

20

23

30

3':;

,10

'.)

r;:)

G,j

C~)

OJ

70

j;;

too

whereas a "01" causes the tape to be tram:lated in a reverse direction to permit the reading of symbol digits
only. Thus, the operation of an EPT command not only
is dependent upon the "direction code" in sestion 2 of
the instruction word but, in addition, depends upon the
p8rticul<:r type of digits to be read from the tape; i.e., data
or symbol. Howe·"er, when an EPT instruction is first
initiated, the particular digit which is located directly over
the tape-reader head, as represented by a particular combination of perforations, as heretofore described, may
bG either a decimal digit from "0" through "9", an endof-frame symbol (EOF), or an alternate-instruction symbol (AI).
Thus, suppose that the number "00" is in section 2
of the instruction word and a combination of perforaHOllS representing a decimal digit is loc~ted directly over
the rc~,ding head at the beginning of the cycle of operation. In this instance, the tape is translated in a forward
direction past the reading station, and the first ten decimal
(li!;its read are stored in memory at the address specified
in section 3 of the instruction word; the address in section 3 being incremented each time a ten-digit word is
stored in memory. Data words are sequentially read
from the tape and stored in memory until an end-of-frame
symbol (EOF) is read, after which the tape is stopped
and thereafter remains in position for the next recorded
digit to be read therefrom. In the event the number of
digits in a given frame does not equal an integral number
of ten-digit words, "zeros" are effectively "filled in" in
tli(: remaining high-order digitJI positions of the data
word stored in the last one of the memory addrcsses used,
thus completing the word. Thereafter, the computer carries out the dictates of the next instruction word stored
in the memory address specified in section 5 of the instruclion word. It is to be noted that the particular number of words, thus stored, is not determined by the instruction word. The number of words stored in memory
in response to an "enter-punched-tape" instruction is determined solely by the number of words recorded on the
tape between end-of-frame symbols.
If, in the preceding example, an alternate-instruction
symbol digit (AI) wns positioned over the reading head
instead of a data digit, the tape is then indexed forward
by a distance of one digit, and the computer thereafter
carries out the dictates of the alternate instruction word
which is stored in memory at the address specified in.
section 4 of the instruction word. In the preceding example, an en,J-of-frame symbol (EOF) represents an
"illegal" instruction for the computer. Consequently, in
this instance, the computer ignores that particular instruction and does not stop the tape.
If 1m "cntcr-punehed-tape" command (EPT) is initiateu with the number "01" in section 2 of the instruction
word nnd with a data digit initially positioned over the
rearling head, the tape first starts to rewind-I. e., is translated in a reverse direction-and, consequently, the data
information recorded on the tape is not read; thus nO
dGta is stored in memory from the tape. The tape con~
tinues to rewind until an end-of-frame symbol (EOF}
has been read. ,\fhen the end-of-frame symbol is read,
the computer imm~cliately begins to carry out the dictates of the next instruction word stored in memory at
the address specified by section 5 of the instruction word.
Thereafter, the tape continues to rewind until an alternate-instruction symbol is read, at which time the tape
is automatically stopped.
Should en end-of-frilmc s)'mbol digit be positioned over
the reading head in the just-preceding example ins.(ead of
a data digit, the tape staTts to rewind, and the computer
immediately begins to carry out the dictates of the next instruction word which is stored in memory at the address
specified in section 5 of the EPT instruction word. When
rrn alternate··instruction symbol (AI) is thereafter first
read, the movement of the tape is automatically stopped.
However, if an alternate-instruction symbol has been po-

3,112,394

101
sitioned over the reading head, the tape starts to rewind
and is slopped only wh;:n the next altern3te-instruction
symbol is read subsequent to an end-of-frame symbol.
When the "end-of-frame" symbol is read, the computer
starts ,to carry out the dictates of the next instruction
word which is stored in memory at the address specified
in section 5 of the EPT instruction word, even though
the tape continues to rewind under the control of the
tape unit only, and is autom~ltic~lly stopped when the next
~ltemate-instruction symbol (AI) is sensed, all end-of- 10
frame symbols (EOF) ess~ntially being ignored. It is
to be noted that successive "enter-punched-tape" instructions should be separated by a minimum time lapse of
approximately 3.5 miHiscconds.
In the preceding example, in which the code number 1:")
"01" is in section 2 of the instruction register instead of
"00" and the tape is in the process of being rewound, if
a subsequent "enter-punched-tape" (EPT) command is
initiated before the rewinding operation is completed and
the code number "00" is subsequently in section 2 of the 20
instruction register, the computer essentially waits until
the winding operation is completed before attempting to
earry out the ne;.;;t succeeding "enter-punched-tape'" command.
46. Format Code Designations of Instruction Words 25
As just described, the code designations for the eighteen
instruction words are numbered from "00'" through "17."
As will be seen later, the computer is properly responsive
to anyone of the code designations "00" through "09"
even though the high-order digit thereof is anyone of the
even-numbered digits 0, 2, 4, 6, or S. Thus, for example, the code designation for an "add" instruction (i.e.,
"03") is effective in initiating the proper sequence of operations even though stored as "08," "23," "48," "6S," or
"88." Also, the computer is properly responsive to either
of the remaining code designations "10" through "IT'
even though the high-order digit thereof is anyone of the
odd-numbered digits 1, 3, 5, 7, or 9. For example, the
code designation for an "add-p::irs-of-numbers" instruction-i.e., "II "-is effective in initiating the proper sequence of operations even ,ulOugh stored as "11," "31,"
"51," '"71," or "91."
Following are three charts, respectively labeled I, II,
and IIr, which give an abbreviated listing and description
of the various instruction words and formats thereof as
previously described.

102
nHART II
Itl:"tructicm

})C.,;cril}tioll of tb:

11~~tructi~~1l

SIIF __________ _
C~u~

1\[

________ _

n ___________ _

srpp __________ _
A Il]) ____ ~. __ ..

SlJ B ____ .. ____ _

SF.\\ ~

30
---

~~-~--

~-~-~--~

CIIAHT HI
.~---

35

_~:~[~ ~~~PNa~~~~~,~I~ __ I·I_~r~ilJl:~l~'()inl~,()~t~,,~~~I~ __
O,r ________

"L~pp('r

"\-lot.Dr

.ro _____

B:lr

t;J)~wr

B:lr

2x ________

Touch."
To.1otor
°1(1)111."
Middle :\lotor

Tbr

I I3~

40 3x ________

l\,;~i-~:~l;~CIl.~fotor

l1Jr

~

"1[Dle!."
_______ La',vpr
~"[otor

Belr

4X~

ra._ .. ____ L?:Iii::.'>~otor

"c_ .. _____ "Ol~;'):or

TII,t,'.\'[',"Il

:2

~dlll

ns .)

~lniI

(\)lu~rlns

;

>I

lx ________

,15

-.----~---

ll.'r

Bar (E::'W

xL____

I

C~)lu:~

___ ~.

.£';3 ____ _

1 --

gl.ltd.

~ -----;;;:---;;I~;~:,~

I ~~~~I·---~~~~ --- - -~-I 01. ____
;11'1 T'c" ·n.l
1

.

1

:Elltt'r-Canl-\Von!s I,lnc-li'intl
CII.\Wr I

50

Ollt'r,~tion:ll

Cvdc

Enti~r l\':'"k;;."~ OarJ-!\1'\nu'\l I-~,">,u'~ ~ Pm~Tr:l::rl.
xL _______ Sl.op on Hr~t Linl.-,rLIhj"~\Lmu d l:('~
n 1'rOl:r~rn.
x~ ________ Stop on ~lt~on(l_ ~,ilH',-nnd ~\hnuc~l
Pro~~rcl-~l.
:r:3- _______ . StOT! on thIrd Lln:''lnd-\Lmu::1 l!i\-;ll:I,U
x>i ________ 1 St~)iJ OIl flrc-it Lin::n.IHLA.ut[)~lj :tie 1;\'''Ui1~l'
x13 ________ btoP on :-;e::ond Lin:,qn,[-'\ tlt:)T:':lti:' ~:,~\.';:u

170 ________ \

InstnwUon \Vonl Furmnt

55

x7 ________

.(8 ________

8t'JPOll. third Li1H',nnd-Auto"i~l1.i,': :\C~'.l1.'IWl'rOiS'·~:ll .

Ejf'vt

C~1ni--Auto111~1.~ic

~;(';;unlu ~~r(].:'L~~H.

I _ _ _~

05 00 ________

Xo

f~hjCt (Cupy).
LdL
ShFt T;i':i1L anLl :nOUIlrJ.

2fl

m~i:t

4n ___ . __
5n . ______

~hil't "i~ht.

an ______

Shift Ria;ht:1n{1
\Yhere 0 ft" is any nU-IL:b~r

70

Not Pr('~;crn\ Sic:n (SIIF Only).
0 to IJ :::,p<.':..·ily!Il~ tilt' lnl' -.b"r of

:;hir!~.

47. Instfl!cliol! Execuliol! Ti!lle

The following formulas give the first-orJ·cr Yi
i=O

(±Xi)
.=0

15

20

represents the sum of the digit values of the multiplier,
Xo being the lower-order digit of the multiplier, and
Xg being the high-order digit thereof. For example, if
the multiplier is equal to (12.45), then

f~Xi)
( .=0
is equal to (5+4-/-2+ 1 +0-/-0+0+0+0-/-0), or (12).
However, in the above example, if III was a "3," then
9

25

t= 112.90+ 8.08n+4.04:;,:sX i
i=O

(b) If the sign of X is negative and the sign of Y is posi-

tive, 12.12 milliseconds is to be added to the above time.
(c) If the sign of Y is negative and the sign of X is posi30
tive, 8.08 milliseconds is to be added to the above time.
(d) If the signs of X and Yare both negative, and m is

either a "2," a "4," or a "5," then
35

t= 112.90+8.08n+4.04tollxill
where IXr! represents a general digit of the number, regardless of whether the number appears in normal or
complemental form. However, when (m) is a "3," then

40

9

t= 120.98+8.08n+4.0{~SXi
;=0

The maximum time occurs when X is equal to
89,999,999.99, the sign of Y is negative, and a shift of
nine places to the right with "round-off" is desired. In
,15
this instance (tmax) is equal to .55 second. The minimum time occurs when (Ill) is a "2" or a "4," and (X)
and (II) are both equal to zero, the minimum time
being equal to 0.1 second.
GO (14-DIV) The time in milliseconds (I) required for a
DIV operation depends upon the algebraic sign of the
dividend and the divisor, and on the magnitude of the
quotient. When the signs of X and Yare both positive, t=48.28+t d; however, when the signs of X and
Yare both negative, or of opposite sign, 1=56.28-/-td,
55
where td in each instance is equal to

t=9.0S+ (Y -X)4.04
where X is the address in sec lion 3 of the instruction
word and Y is the address in section 4 thereof.
(ll-APN) The time (t) in milliseconds required for an 60
APN instruction depends upon the number of wordpairs to be added and is given by the formula

(lOOQu+ lOQ,+

i~Qi)8.08

where (Qj) is the individual digits of the quotient. For
example, if the quotient Q is 000.4351000, then Qo
through Q2 are equal to "0," Q3 is equal to "I," Q4 is
equal to "5," Q5 is equal to "3," Qa is equal to "'4,"
and Q7 is equal to "0." Consequcntly,

1=9.16+(11-1)7.40
where II is the number of pairs of words to be added.
65
(12-MDD) The time required for an MDD operation
1=0
is calculated from the following equations for an MUS
operation, except that, in an MDD operation, m is
in this instancc is equal to (1 +5-+--3+4), or (13). The
cqual to "3" and fl is equal to "2."
maximum time required for a DIV operation is ap(13-MUS) The time required for an MUS instruction 70
proximately six seconds.
depends on the "shift" and "direction" operational code
(15-CFM) The time required for a CFM operation dein section 2 of the in3truction word, the algebraic signs
pends only on the algebraic signs of the two words to
of the multiplier X and the multiplicand Y, and the
be compared. If X and Y have the same sign, t is
sum of the values of the digits of the multiplier. If
equal to 9.16 miliiseconds; however, if X and Y have
the high- and low-order digits in section 2 of the in- 75
opposite signs, t is equal to 5.12 mi lIiscconds.

(tQi)

3,112,394

lOG

105

(l6·--C':2'E) The time required ror a CFE op;:r"tion i~
7.4g millb.;cOilds,
(17-EPT) The time in milliseconds (I) r.::quir,~d (or an
EPf instruction depends upon the ham" of dala read
and is expre'i~ed by the forn-iU1a 1=) -r-1.(n:")lV, \,,"hc(e t"I
is the number of digiU~ per fraine.

valli

5

\Vhilc the computer is il~ the p;'oces:; o[ carryi:lg O:l(
th:.:; in3truc~ion sPCCiriClt by one of the j!1·;t-dc.:;(Tib~d i'1- 10
struction \vord'~, th~lt p:~;·t;c _lJU.f :nstrucl10a "'/onl h (:i~ ..~:­
tivcly s.iored in an ~instructi~n rcgi~~t~r.n \Vith rcL~~'e[1ce
to FJ GS. 45i\ 2nd 45 D, ti1(; in~truction fe~lst~r (!) is
{!ffectivcl~/ divlLi ..":d i:a~o f~v-.: :~cc·~;orj'~l 1 1;lro~lgh 5} whe:'c
scctio'Q 1 i~; capable of sturin.=; d-le tVI"O highcst·o[de~' digit \ Lj
and S2clio~1 5 i'; (,'(~~"Xtblc of :)tG~'i!1g the 1\-vo l{)\n;~;l-"-"jrd.>·
uigits of the ~\:n··digiL in:J~~:uc.:tio.:1 \\rord. C:H:h of lhc ~:'./";
s·.;ct:ons i~; c:r~.x:tivcly Jiviu~d into a hagb-on.:kr and a
d;~2:~t-re(~i'Jtcr.

(:;1(:11 oj' \,'"hich is

ud]jz(~d

to

s~or(~

a partic~tlar.7")nJ::r<- ckcin:a1 dir::it
of th:::" in~~~:-u:.:::tion \,:Dtd 20
~
in biu'try-ccde:l-dc.:inl·_ll fO:'EL For e>:arnpl;;~ J:~it-r ... gic;te~ (:~) effectively ~itorel the highe~·~t or tcnlh-ord~l' de"::i~
Ina! d1s;t cf the irlstruc~~on ~~vord~ djtii-rC'gf~~ter (is) c1Yc-..'lively stores t:le ni;-llh-or(h:;r decinlai dj~~t o~~ t~~ in~,t:·u..:­
tinn:) v~'ord; and ;)0 0;1, so th~-1t d~git-re:~jslcr (Iq» sLore3
the lo-~ve.st or fir~t-orj.::r dccir.1al di;jtL or t~1C i:j~trllctiDn

_01

word.
49, S<'i'1ion 1 of ill',!mctiol1 1\.::-"IS1(,1"

\\'lth

refcrc.\v..:~

to FiG. 55, section 1

o~ lh~

in ;truct;c:l

regi:-~ter i':) logicoJly illn'=tf:ttcu as ii:cilldin~ nve ~1~pl1ops,
6frSl ibt,fJu~h (i-f~;):j, \,. hO~j·e ~;la!t.:s of i.._nergiZt'l~io:l co!-

is likewise "zero," output lines (ISb)'

~1l1d

48, Illstruction Register Generally

low-order

of bit "boo

~b rel1Pin TRUE and FALS12, rec;r~clivcly. When
bit' c"is to oc rC<1u out of memory, only line Be from
Ih,.: bil couT1icr is TF..UE. As the binnry vDluc of bit
"e" i,i ~:L;o "zero," olllp:It lines (l~c)' and 13e remain U\1ck::l'.'c;J, \Vhen !he hirh "Ol'ckr bit "d" is to be read
nUl ~f memo;,y, only lin.; TId from the bit counter is
'i·RUi~,
j\s tllC binary value of bit "'d!' is no\v a Hone,"
when lin~ C41 goe'; TRtn:: at T!i,1E-4, all the inputs
to
AND %3 are TRUE. :md, consequently, line
u::cs TF:.UE at TIME-!. l\S the high-order
dil:lt of tbe code designation 13 ]lcxt to be fead in this
J1iI-rr j,;;i::r ex:;n:p!c, only line Dil from the digit counter
is TR UE at tilis put;cubr instance, Therefore, the rcfe;"fil::; ir;v't to flipn0p 6;)1)4 gG~S TRUE at Tf1\IE-4.
/q
~"~E-l, th~~ r8fcrC'nc~ input thereto goes FA.LSE,
~o ,h"t tb:: st~:' cs of ontput lines (ISd)' and 18d are
relc!"S{"!. That i.s, Er.e (ISd)' goes FALSE, and line Wei
g('~S TkIJE.
It is s~en, therefore, j'hat the st::.tcs of energization
d f,ipllops G%1 lhrol 1gh 6(!!M, collectively represent the
binary nan~her "lGOt\" ,vhich, in turn, represents the
tk.:;rn;)l digit ~'elght:' As th~ v[dl1e of bit Hal" of the
t~Dl;1-0rdcr digit is ~'O," the s::He of cnergiz~tioD of flipi;{)i'S repr c,:ents tbe "~ero" value of the tenth-order
oY the imtwction word,
Vlith n:ftlel;c'~ to FiG. 56, all of the output lines from
~,ec:'ion I of tiL! h':structio'l rc 6 ister [l.fC ·connected as inpli['3 to ~ln ''It)Stn;,.:'t:o:1-c:: d8 I-'::JdouC' h:iving n l11Ultiplicity
of out!)ui. r:n:_'s v;hirh (,11";3 :r'''']~cjiv~ly c~lergizcd by logil::il c~-lirbinn;-~:J:13 ("1' n~:; fi'.'c n;p;~or:s of section 1 of
t~t\~ ;n'~L1·tlct~on fes:i·,t(T ~lnd in~Cvidu;;ny correspond to
l

ao

lectively rcprc~('~~t, i-,1 bi~1:1i'~'-c:od~J d~cjn1lli f:J:rn., e,1.ch
or the p:-c~r!o:...t :y-Jc::,c~'jttd inslfllc:i{in coJc C;JH1!iCC;

a ~·',:\.:cLcd on~: or i~"!r,~truct~c:l \\'old~ Ei':\7'~l(tO) throu.::r!l
E ~~,'r{ ! '/). f r,T:.,)rin~:. for lh~ Inor.lcnt~ those output Jines
digit of each of the iil:;lfU,;.:tiori co~:e rHlnJtn:r~-; i:; Cij]ICf a :L} b=:;r!n~ :1 4'rJ':i:12~~ r:nt:1ti()r1, on1y one or the ren1aining
HOtle~' 0:' a "z::ro: o,":iy' c:~;; i1:~)t1GP (,~0~;.5) i.) nct.:~~j0:.l!'Y
O:tVl' ~i:lcS is T':'UE 8t :m}' given instance; tbe parto ~·t:Jl"C the hj~~l-oid~:-r digit oi~ the (n'~::-,. i ~o\,'/~\'\:;r, ;::.3
r(-~Jb,r En,,? ;.Ilat i~ "r~~'.tjE is d~pcndcnt upon~ and carthe lo\v-orJer d~~;it o!' t'h:J l"'l:'_:': m.::~/ b,~
r.: -T)'~!p~~s to. the p~rt;'~'ukr code nU111bcr stored in secuZ(.'~··J" thrfj:':~:1 ";"~inc," i''.JEl' Hit,HDp,,; (l~;;:};
f;>\~.)
~;;~}~'l ! of 1he in:-,irnciion IC~~:~tcr.
Th(;;r~ are, ho\vcvcr,
f'SC ne':c::",Jtj to J t.:Pi'C_),-;~1t ~h:· V~t~·_~,:: o:l: t:l:; I':J\,/··(H(:l~'i' (r~"lt ~j~) (:-r'(1~:·; c~:::~'pt::,i;1S, \vhich arc to be not~d hereinaftej·.
thereof.
Thps, in the prt:ceJ1!lg cx,Hnpic, an I,US" being stored
'\'J(il;~'

(Er~-r~l)

throd)t

C

I.

1'lil

(~~E)"r).

J\S

tl-:,,:;

iii:;h-or:k~~

1

,A:; IYi"cviou:-Jiv d~~~';:;ri~i(;d v/!th r~:·'rhxt to FrC:;. 67/;' ~:1(J
Btl, output liG~ 1\1:),\ fron1 the lj;CrHory ~;en:;c 8.r~lp!ir:.:r
nii!~1Dp uu5~) is cith'c?f "1 RlJE or F/\LSE Jer:..:nding u~-IC'il
1

\\,'hethcr a bil:'.l;::'/ 11.1 or a binary "!J" hau i:~~;t prc\riou.}]/
been fL:ad o~:t or n1ernory dEring a rC;ci.J-~\,\rfite ;::yc~c e,f
op;;(a~i0:i1.
If a ~-,in:=:ry ·'1 ~l bad just becn rC'~ld ont of
n~crnory, th~ sLate of 1in~ rdS!!.. [.8::3 froIl) F,!:.J ... :_:;~2 to
TRUE f!;)~)ro:.;ir~lfl.~c1~/ 3 ~11i('~-,~<;cconJs ancr TQ\IE-3, n:aJ
s:i..rvs 'Ti<.LJE li~tii tile n:,~~: T'~~,L-~--~, ,Ht \\iL;ch 1i(~c the
stat.; of ~i:1J il.~:}F\. rclnl-n~; F~"~.L:)E. If a bji.l~1ry HO'~ had
j~l::)t b~~ea n.:ad out of nlCi:lory, tbrJ SLa~c or lin~ l\'~Sj\
r~n-:~':~n~ u1:~:b~_ntcJ.: i,c .., ri\LSE.
'Tl1.US, ~..f~er pn:~:,'":;JinG sL~ction 1 of the instdJction
r.r::gistcr to "C'~/' by C;:..'£.11 eClu:lfions for the c:ghtccn readont lines
of tt,,: du:oJcr arc a,e follows:

55

],h,
'[",1,1.1

(,- ,'1' [ ,~

:\0,

f

t;O

th;rcof is an "c(~~lL" CC:l'~C~u';::[jt1y, ,1S bjllo:ry-bit Ha,"
loN-oi"G;~r ci,git of 1h,~ cod..:! d(':;i~n8tjorl ,is first 8:5
to b~ rca:l out c~ ,111Ctnory, E:'.c E;a is T~~_lJE, and, 8.S a
f) [V __ _
vyrO~'d is to IJC tfansf~rl'cd L:o:--n r:1C~)nory to lh~ instrucC F \1 ...... ~
en' ..... .
tion rcgi':1-::r, lin::: If,B is li~,:c',vii'~ TRUE, ~i3 vlill b:,; seen
.EI'11
1:~ter.
I-[ov~'-::vcr~ in tbi-~ ex~cnp;:;~ as the binary value
of bit "a" of the 10"Ii-oid::r di:;it of the code desig- 70
nation is "zero," line j>,lS/\. remains F/ILSE, "nd thereFor r,~u",;ons to be set forth herei'lafter, it is to be
fcr~ OLdput line: (Uti)' and IRa arc 'TRUE Oild Fi~j.LSE,
noted Ih.1t li:le }\Dl) is Tl{UE \vhencver either an "osn
re2{.lc,ctiv~ly,
\'\'hen bit ';l/' is 10 be r::;}d out of rn·enl0[' ;:m "09" is stored in seetio;} 1 of tbe instruction regisory, only thc line Eb ;rom t~e bit COl!nt:::r is TRUE,
whih; lines Ea, Be, U:l:_t Dd 2.re F ;\",LSE. 1\S the binary 75 ter, i.e" for either nn "nd,l" or a "subtract" command;
of the

3,112,394

107

108

however, line SUD is TRUE on]y for ;.l "cub tract" comsection of th2 \vonl-:·,c\:cting register previollsiy d·.:s~rIbcd
mand, i.e., "09." In addition, line MUS is TRUE when
with re,pect to FIG. 65, all of which may more clearly
either a "12" or a "13" is stored in section 1 of the
be seen by reference to the biockdi2~T"m shown in FIG.
instruction regi~ter, i.e., for either a "multiply-dollar45. TilliS. as jir;cs 17a through 17d of FiG. G4 and lines
decimal" or a "multiply-and-shift" instruction; ho>vcvcr, G lGa tllrough Iud of FIG. 65 ar;) each logically ANDED
line lVIDD is TRUE only for a "multiply-dolbr-lkcire::l"
\v;th line T12, \vhich odginatcs in FiG. 61, rJLcr the ·wordseiecting rC3istcr is preset to "00" by efl'c:cting a TRUEcommand, i.e., code "12." An additional readout is pro,a-FALSE reversal of the s~atc of line (?\V'p)', the highvided by line MOD, which is essentially a logical OR
and low-order digits stored in >ec!:on 2 of the instruction
of lines I"iUS and DIV and which signifies that either
a mUltiplication or a division operation is being carried 10 register are permitted to rc,pectivdy be simultaneously
out.
transferred directly into the high- and low-order digit positions of the word-selecting register by effecting selective
50. Section 2 of Instruction Register
energization of line 1'12, selective energization of line
With reference to FIG. 57, section 2 of the instruction
T12, therefore, effecting the transfer of the contents of
register includes eight flipflops, GOG6 through 6013, '?ihich 15 section 2 of the imtruction rcgist~r into the '.'lord-selecstore the seventh and eighth-order digits of the in"tlllctic;n
tion register.
word. As previously mentioned with resp~ct to til::t p;;rt
51. Sectioll 3 of Instme/ioll Regir!i'r
of the foregoing description relnting (J (he "lnsln,clio:i
Word Format," section 2 of lh,,; imtruct;c;n fegif,(er is
1\, previousiy m,~ntloned, s~ction 3 of the instruction
utilized to store theuddrcss cf either the first or t1,C sec:- 21)
rceister normally stores either a destination address or
ond operands, the destination nliJress, or a sp:::iill co dc,
the Ctddre,s of one of the opci':mds. \Vithreference to
depending upon the particular instruction. A c1t:cc;eer 1'or
t:1C ·lcft-In!nd portion of FIG. 58. section 3 of the instructhe high-order digit-register of ~ection 2 is provided wilh
tion register comprises eight flipilops, 6014 through (IOU,
seven readout lines H.p through H6 to respectively indicate a digit having a vaiue "zero" through "six" being S.l Hipllops 6014 through 6017 being a p:1ft of the high-ordcr
digit-register (IS) and llip!1ops 6:HS (hrough 6021 being
stored in the high-order digit-r;:gister; the decoder [or the
a part of the low-order digit-register (14) thereof, as illuslow-order digit-regjs~er is provided with readout lines Lp
trated in the block diagmm of FIG. 45. Tl:e tViC digitthrough L3, which respcctively indicate a digit having a
registers (14) and (IS) ·are interconn~ct~u in such a manvalue of "zero" through "three" being stored in (he low:30 ner tInt, when so combined, they function essentially as a
order digit-register.
binary-eodcd-decimal counter which is capablc of effecFor example, in an instruction calling for a particular
tivelycounting from 00 to 99 in units of "one."
motor bar operation of the accounting machine portion
To accomplish this, flipflops G!HS through 6I.l21 of digitof the computer, readout lines H¢ through H6 indicate
register (J4) me connected together to eolkctively funcwhich motor bar should be dcpress~d ancI wlnt type of
depression is desired-i.c., "tollch" or "holu"-in carrying 3J tion as a "powers-of-two" binary counter tbat increments
onc: unit each time the state of line IN4 changes from
out a "shift" instruction (SHF-04), and readout lines
TRUE to FALSE. After a count of "nine" (binary 1001)
H2 through H5 indicate the direclion and type of shift
is reached, digit-register (14) recycles back to "zero"
desired. The simplified logical equations for cuch of
(binary 0000) on the next change of state of l;ne IN4
readouts H¢ through H6 are as listed below. It is cO be
noted, however, as shown in the logical circL,it dia~,;'aJ;l  Lq,
indicated by a TRUE state of each of the amp!ified referthrough L3 are as given below:
ence outputs of flip flops (,018 and 6GZl. Thu o , it is
evident tha~~ vV~1en ref.:::r~ncc output 1!T;~3 1~:1 and l~!d are
both simultaneously TRUE, output line 149 from gute
G5 ]067 (FIG. 59) is likewise TRUE c~.ch tim~ the counter
reaches a COU;I! of "nine," line (I4~)', of course, being
It is to be noted that output lines 17a through 17d of
FALSE at that particular moment. As line (I49)' i3
the high-ordc-r digit-re!!bter of section 2 of the i'l~truction
FALSE only during" count of "nine," the state of the
register are respectively connected ~,s an input to onc of
prime input to flin:lop (;0/1) (F~G. :;~) is pf('v~n!cd from
flipflops 6!l47 through 6IlS(} of the high-oHkr te~tin of 70 being changed from TRUE to FALSE dilring the l'ext
the word-selecting register previOllsly d:scrib8u \'iith resucceeding TRUE-!o-FALS';~ change of state of line Ha.
spect to FIG. 64. It is also to be noted th,::t adput lii;e~
Ccnscquently, line~ Hi; and J4c remn 2 of the instruction
register (FJG. 57) is simultaneously preset to "00" by
line (PI¢)" which presets a FALSE state of output lines
17a through I7d, and 16a through 16d, also indicative of
"00"; section 3 (FIG. 58) is also simultaneously preset
to "00" by line (PI¢)', which presets the states of output
lines 15a through lSd, and 14a through 14d, FALSE,
indicative of "CO"; each of the digit-registers of sec,tion 4
(FIG. 58) is, however, simult::meously preset by binary
1111 by a TRUE-t::;-FALSE chang~ of state of line PI¢)',
which presets the states of output lines I3a through I3d
TR UE. indicative of bin:lry 1111, and presets the states of
output lines 12a through 12d TRUE, also indicative of
bin3ry 1111: and section 5 (FIG. 59) is simultaneously
preset to "GO" by line (PI4»', whi~h presets the stntcs of
output lines na through lId ~nd l¢a through I¢d, FALSE,
indica,uve of '"00."
From the foregoing, it is seen th~t s~lec!ive encrgization 'Of preset line (PI'IJ)' causes ea~h ~ec.tiGn of the
in;,trllction register '(0 be preset to "00," vlith the exception of section 4, eClch ~ection of whkh i, preset thcrehy
to bin:!ry 1111. In other words, the reference outputs
of all "he flipflops in sections 1, ~, 3, and 5 of the instruction register are preset FALSE, whcrca~. the refere;,c~
outputs of the flipflop> of s8ction 4 thcr~of are preset
TRUE by (PIp)' prior to the "loading" of a word from
memory into the instruction register. The reason for
thi, type of preset is that, due to the previously-described
decrementing vbility of section 4, it has been found
expedient, circuitwise, to fin'! prese't the reference output of each of the fiip!1ops of section 4 to a TRUE representa,tion and dlcn reverse the state of each particular
reference output whenever its correspDnding binary bit
from memory is "zero," contra to presetting the reference

3,112,394

112

111
outputs FALSE and Ib:n rC','crsh!J the state of each when
the corresponding bit from me~ory is a binary "one."
However, to avoid confusion, and for the purpose of
convenience in the following description, the above presetting technique of the instruction regisler by line (PI¢)'
will, nevertheless, be hereinafter referred to as presetting
the instruction register to "zero."
With reference to FIG. 58, the second preset line PRB
is a logical AND (1045) of lines SP and FG and is
utilized to preset section 4 of the instruction register to
"99" after the instruction register has previously been
preset by line (PI¢) '. The purpose for such a preset is
to be covered hereinafter.
As previously described with respect to the memory
sense amplifiers shown in FIG. 67 and the wave-form
chart of FIG. 86, each time a binary "one" is read out
of memory, the state of line MSA is changed from FALSE
to TRUE at a time approximately three microseconds
after TIME-3, and then its state returns to FALSE at
the next succeeding TfME-2. Thus. with reference to
FlG. 55, it is seen that from TIME-4 to the next SllCcceding TIlVIE-l during a "memory-to·in~truction-regis­
ter" word-cycle in which line MI is TRUE for approximately 1600 microseconds, line BaL is TRUE if the binary
bit "a" ju~t rcad out of memory is a "one," otherwise
line BaL remains FALSE; during the next succeeding
time interval of ten microseconds ,from TIME-4 Ito
TIME-t, line BbL is TRUE if the binary bit "bl> just
read out of memory is a "one," otherwise line BbL
remains FALSE; during the next succeeding time interval,
line BeL is TRUE if binary bit "e" just read out of
memory is a "one," otherwise line BeL remains FALSE;
and, during the next succeeding ten-microsecond time
interval from TIME-4 to TIME-I, line BdL is TRUE
if binary bit "d" just read out of memory is a "one,"
otherwise line BdL remains FALSE.
As shown in FIG. 59, lines BaL through BdL are each
individually ANDED with the low-order read-out line
D¢ of the previously-described digit counter (FIG. 63)
and then respectively connected to the reference inputs
of flipflops 6637-6034 of the low-order digit-register
(I¢) of section 5 of the instruction register; lines BaL
through BdL are also individually ANDED with the
second-order read-out line Dl of the digit-counter and
then respectively connected to the reference inputs of
flipflops 6033-6030 of the high-order digit-register (II)
of the fi fth section of the instruction register. Thus, if it
is assumed that the instruotion word stored in memory
address ¢1> is to be transferred into the instruction register, the state of flipflop 6037 is first "set" in a manner to
be indicative of the magnetic state of oore 885 (FIG.
52A), forty microseconds later the state of flipflop 6036
is "set" indicative of the magnetic state of core 886,
forty microseconds later flipflop 6035 is "set" indicative
of the sta,te of core 887, and so on, until the first eight
binary bits of the word in address ¢1> are effcc,tively stored
in section 5 of the instruction register, the first four bits,
of course, representing the low-order digit and the second
set of four bits representing the second-order digit of the
word in address ¢1>.
Input lines BaL through BdL are similarly ANDED
'with the remaining output lines D4 through D9 from the
digit counter to errect transfer of the corresponding digits
of the word in memory and subseqnent storage thereof in
sections 1 through 3 of the inSotruction register. For example, in section 3 (FIG. 58) are stored the fifth- and
sixth-order digits, in section 2 (FIG. 57) are stored the
sevenlh- and eighth-order digits, and in section 1 (FIG.
55) are stored the ninth- and tenth-order digits of the
word located in address ¢1>. As previously described,
the reference output from each of flipflops 6022 through
6029 (FIG. 58) of section 4 of the instruotion register is
initially preset TRUE just prior to a memory-to-instruc.
:tion-re,gister word ,j'xansfer. Thus, if the binary bit just

read ont of memory ie; a "zero," liEC (MSA)' remains
TRUE, and, consequently, output line S4L is rendered
TRUE from TIME-4 to TIME-t. Therefore, assuming
that low-order bit "a" of the third-order digit is a "zero,"
5 the prime input to flipflop 6026 go~s from TRUE to
FALSE at TIME-l approximately ,forty microseconds
after the state of flipflop 6030 (FIG. 59) is "set" indicative of bit "d" of the second-order digit of the word in
address 1>¢; a TRUE-to-FALSE reversal of the prime in10 put to flipflop 6026, of course, "se'ts" the state thereof so
that output line 12a is rendered FALSE, indicative of
binary "zero." The remaining bits of the third and
fourth order digits are sequentially stored in section 4
in the same manner as just described.
15

55. SUIIllnllry of Instructioll Register

In f,umm~;ry, the instn·clicn register is provi<.kd w,th a
bin:",ry "biC' scriaEz.er at the input of c:lch digi~-r~:'~~'1,:,t'2r
thereof and nlso is provided wjth ~ s::r:~\l~zcr on a JiDil20 by-digit b~,sis for se'111cnli:1Iy ~ck~lil1g each of :hc t;!n
digjt-·regist~rs t~)en::c;f~ st:trtin~ '\,v~th th~ l~J\.\'~-;t·o!'{},;r di2it-

25

30

35

40

rcg;stcr and cndi:r.g \vith th~ h:[',he,;;t-order digit-regis:cr
thncof. Comqucntly, hy mc:\ns of a "m'cr,10ry-to·jnstruction-r~2isler" transfer instruction, the word stored in
memory is trnnsfc:rn:d ir:['J the instruction rcgj~t~r, digit
by digit, starting with the low·order digit thereof, the
IOI'l-ord-.:r digit ccing ~torcd in digit-register (I¢) of section 5 and the high-order digit being stored in digit-register (19) of section 1 'Of the instructi'On register.
As previously dcscribed, and as mus(ra~ed in the block
diagram of FIGS. 45A 3nd 45D, the digit stored in a selectcd 'One of low-order digit-registers (Jq'J), (12), (14),
or (I6) is selectively stored in the low-order digit-register
(W1» of the word-selecting register, and, simultaneously therewith, the digit stored in a se:ecled one of highorder digit-registers (Il), (3), (IS), or (7) is selectively stored in the high-order digit-register (Wl) of the
'\vOId-selecting'r{)gister. Additionally, the low .. order digit
of section 2 of the instruction regis,ter is selectively stored
in an "R-counter," which is next to be described in detail.

56. R-Counter
With reference to FiG, 68, there is logically illustrated
45 a reverse-counting cotmter, herein3.fter termed "H.-counter," which includes four interconnected flipflops 6US7
through 6!l60. The F.-counter operates cs~entially in th~
3~.me mallncr as low-order digit-register (12) of section 4
of the instruction register, previously described in detail,
50 in that it is a single digit counter capabie of ClJunting in
a binary-coded-decimrl'l code in a rev~rse digital order.
For example, ,if the R-counter is initially at a count of
"nine," on each 'Occurrence of a TRUE·to-FALSE ch:mgc
of state 'Of line DR, the R-counter is effectivdy decre55 men(ed by one decimal digit until a count of "zero" is
reached. However, as no rccycling of the R-countcr is
provided, en the next subsequent change of state of line:

60

65

70

75

DR the R-countcr is returned to a count of binary 1111,
instead of binary 1001 as in digit-register (12). The two
presets provided for the R-collnter are pr~"et line PI{q),
which presets the counter to "zcro" by causing the states
of JlipJlops 6057 through 60GO to be such th;:t e"ch of the
referencc outputs thereof is FALSE (hereinafter known
as setting a ilipfiop "FALSE"), and preset lin:;) PRS, wh~ch
prese~s the counter to "eight" by "cUing 11ipflop 6060
TRUE and settinz flipflops 6(}57 th:-oll=~h 6C39 FALSE.
Any sin[;lc decimal digit, from "zero" 10 "nine," is sclectinly loaded into the H.-counter from two different
SOurCi;S. Fer example, the digit stored in the low-order
digit-register ([6) of section 2 of the instruction register
is transferred into the R-Collnter by means of selective
energization of line RLJ::'. However, prim to loading, all
four 1!ipflops 6:157 thmugh 6\)5G of the R-counter are first
preset FALSE by means of preset line PR,?, Thereafter,
the s:"te of each flijlfiop is selectively sct lly line RLR to

3,112,394

113

correspond to the statc of the: corresponding flil~n{)p in
digit-registcr (16) of the jpstruction register. Thus, if
digit-register (I6) were slar";', tbe numcral "six," so that
f1ipflops601l and 60]2 (FiG. 57) w"rc TRUE (fiipilo\lS
6010 and 60B being FALSE), v.'hen the state of line RLR
is rendered FALSE afcer being TRUE for o.t leGS! twenty
micrvseconds, both of flipl10ps (,'35il 2nd 6059 (FIG. 68)
are simultaneolisly set TRUE. There:ore, it is evident
that any digit from "zero" to) "nine" is selectively transf~rred from digit-register (16) to the R-counter.
After the R-counler h,b previously been preset to
"zero" by line PR¢>, any di:sit being read out of memory
is selectivdy stoTcd in th:; H.-counter by effecting sequential energization of line RU"i simu1:aneou,.ly with one of
output lines nil through Bd from the bit-counter (FIG.
62). Thlls, the bit-counter 'Oreratcs as a so-called "seri21izer" at the input of the R-counter to cfre:::t "elective setting cf tbe states of the fom f!;pflop~ th~rein to corresDond to the four binnry bit, being 5:?quenlially rez.d out
o'f mcrnorya1i(! corresponding: to the particlll:lr memory
digit to be stored in the R-cocmtcr.
The R-counter is used in variolls cf the instructions for
diffcrent purposes. For e,~amp!e, in a "shift" instruction, the R-CO!..1ntcr is first !o::-tded with the lo\.\'-e:·'~>i· di.~:it
stored in section 2 of the instruction n:'2'i:~tcr, '\'\'hic!J. digit
specifi~s the number of places the word in memory is to
be shifted. Afler thc entire word h~s been ~bifted one
diCit:::1 order, th~ R-co~mter i:l effectiv:ly decrem'cnted by
one c!ecimd digit by line DR ~nd t11,"'1 is essclltiC!!ly
"ch,:cked" to determine if (he R-counLr is :It a count of
"zero." In that way, the R-collnler is used to serve as ,m
indic~tion as to the rern:.linlng nurnbc-r of dj~ital crdcrs
the word is to be shi£t~J. In a divic,ion operation, suppo,e th:lt it is ncces;:ary to perform a series of subtraction
operations during ,vllich e:ght sI1ift OpeL:Ltlon~ ,cf bo~h
the quotient 8J~d the fi~.ln:lindcr is l\~GLdn:d. In this :r:~
stance, the R-counter is initially preset to a count of
·~eight" l:lnd thcrcafU;r dccrC!n~!1tcd by onc decin1.:-d di,~;t
after c3cb shifting oi,eratiGll is completed, until a count
of "zero" is reached. In other words, the R-countcr
counts dO\'/llwardiy .from "eight" and thus keeps a record
of the numb:::r of shifts remaining. h1 a "m:l1tiplv-anllshift" instruction, the R-counter is sequentially loaded
with each on~ of the digits of the TnUilir1icr word in
nlcmory. The }~-COljnter nlC~1 con~rols t~le number of
times that the multiplicand i~ added into an accumubting
rC::iistcr, and si;;nifics wilen the requited numbers of add itions have been performed. in a "multinly-:md-c.hift" or
a "multiply-dollar-decimal" instruction, the R-::ountcr is
utilized to record the number of times that the product
has been shifted, and, as a result, determines the number
of shifting operations re:naining to be compicted.
The R-counter is capable of providing three logic"llyderived readuut signals from output lines R¢, Ttl, and R3.
..tA..illong otber purposes, the states '01 r~acJo1Jt lines R¢ and
Rl arc respectively utilized ciEring a "shift" op·.cration 10
jndkrrte when the R-countcr js 3t :l count of Hz:cro" or
"one"; the state of readout line R'f> is utilized during both
multiply instructions to indk2.tc a "zero" count of tb~
H.-counter; and readout line RS is uliiized during all multiply and divide instructions, during wh;ch t;me the H.-counter is effectively recording tbe progress of the instruction
as it is being carried out.
57. F-Colll1ter

digit-register (I5), the F-counter is capable of counting
from "zero" to "Jiflcen" and then recycling to a count
of Hzero.'~
Prior to a mathematical computation, the F-counter is
{) generally preset to "zero" by means of a FALSE-to-TRUE
c:lUnge of state of preset lin~ PF¢>. Thereafter, on e~;ch
successive TRUE-to-FALSE change of state of line AF,
tbe F-countcr is incremented from a "zero" count and
advanced by one decimal diGit for each change of state
10 of line AF. It is to be noted, however, that selective
cncr;;iz:ttlon of line PI' presents the F-counter back to
"zero" regardless of the count held thercin. The F-counter
is provided with four readout lines, F, F8. F9, and Fl¢,
w~;ich rcspectively indb;te a COlmt of "zero," "eight,"
L:; "nine," and ~Iten" thereof.
58. Compare F-Collnter and Digit-Collllter

With reference to the upper right-hand portion of FIG.
12, the states of output lines Fa through Fel and (Fa),

20 through (Fd)' from tbe F-counter are logiCally compared with respect to the states of output lines Da through
Dd ¢> through 99, or addresses A or B,
01', as will be seen later, with a digit magnetically read
from a ledger card. However. prior to loading the "]"
digit-register, each of the flipflops therein is effectively
prc:set to "zero." Thereafter, the states of flipflops 6070,
6!}69, 6068, and 6i}67 are seqllenti31ly conditioned (0 respectively correspond to a difIerent one of the four bjn~ry
bits '!;hich are sequentially read from memory or the
ledger card in the following nunner: As iHustrated in
FIG. 71, output line .MSA from the memory sense amplifier flipflop 6055 (FIG. 67) for addresses ¢>¢> through 99,
output line ASA from the memory sense amplifier tlipJ10p
6056 for addresses A and B (FIG. 67), and output lir:e
CSA from the ledger card sense amplifier flipflop 6144
(FIG. 85), essentially arc each 10gicaJly AND ED, via
line JL, with each of output lines Ba through Bd from
the bit-counter (FIG. 62). Consequently, if bit "a" of
the digit is a binary "onc," the state of the reference output of flipflop 6070 is rendered TRUE; if bit "b" is a
binary "zero," the stale of the reference output of flipflop 6&61) remains FALSE, and so on.
Logically illustra1ed directly above flipflops 6\167
th~ough 6G70 are three additional readout lines J, J9,
and EOW, whose individual state of cnergizatlon is indicative of a particular number stored in the '']'' digitregister. For example, the state of output line Jop is
rendered TRUE whenever a binary OO()~} is stor~d in the
register; the state of output line J I} is rendered TRUE
wll:mever a bInary 1001 is stored therein; and a TRUE

3,112,394

115

116

state of output line EOW is indicative of a binary 1111
IO;lic:t11y ORED together and terminate in output line
being stored therein. Tn addition to the availability of
KS, Yihich, in turn, is logically connected as an input
a parallel type of read-out, the output of the "J" digitline to the "wri!e-control" circuitry (FIG. 60) in such
register is also effectively serialized, in that output lines
a manner th~t the digit stored in the "K" digit-register
Ja through Jd thereof are logically ANDED with the 5 is permitted to be selectively stored in any preselected
bit·counter output lines Ba through Ed via logical AND
nne of the memory addresses.
gates 1432 through 1435, line Ja being ANDED with line
62. Adder-Subtracter
TIa, line Jb being ANDED with line Bb, and so on. The
outputs of logical AND gates 1432 through H35 are logiBefore proceeding with a detailed description of the
cally ORED together and terminate at output line JS. 10
adder-subtracter portion of the computer logically illusOutput line JS, for example, is logically connected as an
trated in FIGS. 53 and 54, a brief description will first
input line to the "write-control" circuitry (FIG. 60), so
be given, setting forth the various salient operations
that the digit in the ''1'' digit-register is capable of being
which are sequentially executed in the performance of a
selectively stored in anyone of memory addresses q)(1)
15 simple addition and subtraction mathematical computathrough 99, or addresses A or B.
tion; sllch a description is deemed desirable in expedit60. Compare F-Colillter alld "j" Digit-Register
ing rnd assuring a clear understanding of the various
prin::iples involved in the construction and mode of opWith reference to FIG. 72, a compare circuit is illuscr~!lion of the adder-subtracter unit.
trated as comprising eight logical AND gates 1462 through
20
Preceding lln "add" instruction (ADD-OS), for ex1469, which are logically OR ED together and terminate
::lrnpie, both the addend and augend data words are first
at output lines IFJ and OFJ) '. The output lines from
slored in memory. To begin the "add" instruction, one
the "J" digit-register (FIG. 71) and the output lines from
of the data words is transferred to address-A, ,with the
the F-counter (FIG. 72) are logically connected to sesecond urt(a word remaining in one of memory addresses
lected ones of AND gates 1462 through 1469 in such a
25 ,orb (hrollnh 99. Thereafter, the low-order decimal digit
m;,nner that the value of the digit ~tored in the F-Collntcr
~i the w;rd in address-A is read out and stored in the
is effcctively compared with the value of the digit stoled
"J" digit-register via line ASA, as illustrated in the block
in the "J" digit-register. When the tl'lO digits ~re of undiagram of FIG. 45. Simultaneously therewith, the lowequal magnitude, the state of output line IF] is rendered
ord~r ckcimal di!,it of the word remaining in memory
TRUE. However, when the value of the two digits is of
equal magnitude, the state of output line (IFJ) , is ren- 30 is retid olltand ;tored in the "K" digit-register via line
l'vlSA. The output lines from (he '')'' and "K" digitdered TRUE, indicativc of equality.
Ie ~i~tcrs me connected as input lines to the adder-subtr;ctcr unit in a manner such that the two decimal digits
61, "K" Digit-Register
slored therein are effectively added together by the adderIn FIG. 70 there is logically illustrated a second digit- 35 subtracter unit, so that, if the slim is equal to "nine" or
register, hereinafter termed "K" digit-register, comprisless, a "sum" digit and a zero "carry" digit are derived
ing four electrically-interconnected flipl10ps 61:62 through
therein. However, if the sum is greater than "nine," a
6065, which are collectively capable of storage of any
"sum" digit ~jnd a "carry" one digit are derived.
number from binary 0000 through and incllld:ng binary
Following the addition of the two low-order digits,
1111. The "K" digit-register is preset to "zero" by effect- 40 (he sum digit is stored in the low-order digital position
ing selective energization of line PK1>. Thereafter, the
of address-A, and tbe carry digit is stored in a carry flipregister is selectively preset to binary 1001 by effecting a
flop. Next, the second-order digit of tbe word in
TRUE-to-FALSE change of state of line PK9.
address-A is stored in the "J" digit-register, and, simulLike the previously-described "J" digit-register, the
taneously therewith, the second-order digit of the word
"K" digit-register is capable of being loaded with any
remaining in memory is stored in the "K" digit-register.
digit previously stored in anyone of memory addresscs 46 Thereafter, both digits are, in a sense, simultaneously
¢1> through 99, or one of addresses A or B. However,
tnll';ferred to the adder-subtracter unit, wherein they
p;'ior to loading, the register is preset to "zero." There::re ::ldded tq;ether with the carry digit previously stored
after, the states of flipflops 6065, ,6064, 6063, and 61162
in the carry flipflop. If the sum of the two secondure sequentially conditioned in the following manner to 30 ord~r digits plus the oarry digit is greater than "nine,"
respectively correspond to a diiTerent one of the four
a sum digit is ubtained and stored in the second-order
binary bits which are sequentially read from memory:
digit:.ll position of address-A, and a carry "one" digit
Output line IVISA from the memory sense amplifier flipi:; obtainell alld stored in the carry flipflop. This seflop 6055 for addresses \&1> through 99 (FlO. (7) and
quence of open;!ions is repeated for each digital order
output line ASA from the memory sense amplifier flip- fjJ ';f tbe worus until each digit of one of the data words
fiop 6lY56 for addresses A and 13 (FrG. 67) are e~,ch esis added to th~ corresponding digit of the other data
s:':l~tially logically ANDED, via line KL. with ea~h of the
word. Foilowing the addition, the sum thereof is looutput lines Ba through Bd from the bit-counter (F1G.
cated in address-A. Consequently, the final step in the
(2). Consequcntly, if bit "0" of the digit just rend out
"add" instructlon is to store the sum data word in the
is a binary "one," the st~te of the reference output of 60 particular address in memory as previously specified.
flipflop 6055 is rendered TRUE by 'a change of state of
A "subtr"ct" instruction (SUB-69) is carried out
the flipflop; if bit "b" is a binary "zero," the st:::te of
in cs~:entially (h~ s;.!me manner, with the exception that
the reference output of flipflop 6frlS:J remains FALSE,
(lie dc,(J. word r~i11'lilling in memory is subtracted from
Ul1 d so on.
th'J drlta word in address-A, rather than being added
Logic, vihose
out for a "st1btr~cl" instruction is to transfer to addressTRUE sL,le is indicative of binary OGOO being stared in
1\ the minuend which is previously stored in one of memthe "K" digit·register. In addition to the av~lilrtbiljty
ory addrcssss 'pr/) through 99. As before, the first-order
of a parallel type of read-out, the output of the "K"
di:;it of the word in address-A is stored in the "J" digitdigit-register is also effectively serialized, in that output 70 r"gister, and, simuit,meously therewith, the first-order
lines Ka through Kd thereof r,re cHeh logically ANDED
digit of the data word rem~ining in memory is stored
with a corresponding one of bit-counter output lines Ba
ill the "K" digit-register. Thereafter, the digit in the
throurh Bd, via logical AND gates 131)3 thrmlgh 1396,
"f~" di~it-rcgic;ter is subtracted from the digit in the "J"
1inc }~(f being j\l',Jf)L:~) v/ith Enc Btl, li:-!e T~h \vilh Bh,
lF2it-n:gistcr, " difference digit is derived therefrom and
etc. The outputs of AND gcfcs 1393 !':rollgh 13% are 75 sturcd in the lOIN-order digital position of address··A, and

3,112,394

117

113

tIle' c,rry digit derived therefrom is stored in the co.rry
fli;:·fiGp, as before.
Du.::! to the het that ther,~ is no "borrowing" of digits
in the present tyre of computation, the carry digit is
~;ddcd to the next highcr~order digit stored in the "K"
digit~rcgister ralher than being subtr:!ctcd from the cor~
responding next higher~order digit in the "J" digit-register. In other words, any carry "one" digit effectively
increments the next succeeding digit in the "K" digitregister rather than decrementing the next sLlcceeding
digit in the "1" digit-register.
Tile just-described subtraction operation is sequentially repeated for each of the next successively higher-order
digits until the remainder derived from the subtraction
cper:l.tion is in address-A. As in the "add" instruction,
tIle final step in the "subtract" instruction is to copy t!1~
remainder data 'Nord into the particular address in memory, as previously specified.
From the foregoing, it is evident that the adder-subtracter unit is ,arable of adding two decimal digits and
a carry digit, either "zero" or Hone," and to obtain therefrom a d; one
decimal dicit, plus a carry digit of eilher "zero" Of "one,"
from a second decimal digit aGel of obtaining therefrom
a (It:cimal remainder digit and a new decimal carry digit.
Essentially, the adder-subtracter unit is an "adder" and
a "subtracter" combined into one cifcuit~sharing unit,
the adder ponion being selectively capable of individually performing 1he ne::cssary arithmetic computation whenc·'lcr an addition operation is required, and the sLlbtmcter
portion being selectively capab1e of individually performing the necessary aritln:letic ccmputation vt/hen ..;ver a sl.1btraction operation is required.
As previollsly DH;;1tio;.,;d, th~ add~r-sub(rncter unit is
cap~lble of sCfJlIcntia!!y rcrforn1ing an u<.:C!jtion cperation
with respect to tl.'O/O biIwry··codcd decimal di;:;its and a
decin1al carry dlgit of "O'! or "1" nlag~litudc. The n12g-

5

10

15

20

25

30

3:j

mldilj')n, of course, being: binary "0" plus binary "0"
equals binary "0"; binary "1" plus binary "0" equals binlii"y "I"; birwry "0" pius binary "11' equals binary "I"; and
bin'!fY "1" p:us binary "I" equals binary "0" plus a binary
"1" carry. Applying the just-mentioned rules for binary
audilion, binary OW 1 plus binary () i 00 equals binarv
lCUl, or "9." By .he same token. the decimal digit "5"
pius the decimal digit "5" equais binary 1010, However,
if decimal "! 0" (binary 10 10) is Sll btracted therefrom,
"5" p~us "5" ::lIsa equals bir:~~ry O(}')O plus a binary "1"
carry.
Listed belo'll, in "truth-table" form, are representations
of input bits "
1
iJ
1
1
1
;
tion operation being c3.rried out by the just-described
(J
I
II
1
1
1
1
-4 ______ _
()
()
j
[J
I' '
1
1
1
1
addGr-subtr2.cter arithmetic unit, suppose that the first--:f _______ ' 1
I)
()
1
1
o,
oreler digit of the addend word located in memory address
(I
(~
t
IJ ,
()
1
1
- (~------{)
I
()
,
j
(J
1
1
1,
(Kb) 'pc(5AS)'
FAL~E, as previously noted.
As none of AND gates
(29) /'I:=Keqe+ (Je)' Kc(qe)' SAS (Jc)' (Ke)' qcSAS
+JeKc(qc) '(5A5)' +Jc(Ke)' qc(SAS)'
911 through 914 have all of the inputs thereto simulta70
(30) t=Kdrc-'r-(Jd) 'K!!(rc)'SAS+Ud) '(Kd)'rcSAS
neous!y TRUE, the state of output line q is FALSE, in+JdKd(rc) '(SAS)'
dicative of binil[Y "0"; consequently, the sum of the "b"
bits plus the "a" bit crtrry is "0." However, as the states
By likewise comb;ning the lcgi~~l equations for "ANa"
of all of lines Jb, (Kb)', pc, and (SAS)' are TRUE, the
through "ANd" and "EAS" for both an addition operaAND gate I)l.i are simultaneously
tion (Equations 9 through 13) ami a sabtn,<;tion mathc- 75 sla;es of the i"puls
c

t~

c

~J

~-~-I
i il

~

=;-------1

~

~

+

+

,0

123
TRUE. As a result, the state of output line qc is TRUE,
indicative of a binary "1" carry resulting from addition of
the "b" bits pIllS the "a" bit carry.
The "e" bit in the "J" digit-register being a binary "1"
and the "c" bit in the "K" digil-re:;is,ter being a binary
"0," the state of line Ie is TRUE :md the state of line Kc
is FALSE. As none of AND g:ltes 920 through 923 have
all of the inputs thereto sinmitancously TRUE, the st:ltc
of output line r is FALSE; consequently, the sum of the
"e" bits plus the "b" bit carry is "0."
As the respective states of lines Je, (Ke)' {jC, ~md
(SAS)' arc each TRUE, all of the inputs to AND gate
926 are simultaneously TRUE. Consequently, the state
of output line re is TRUE, indicative of a binary "1"
carry resulting from addition of the "e" bits and the "b"
bit carry.
The high-order or "d" bit in the "j" digit-register being a binary "0" and the "d" bit in the "K" digit-register
being a binary "1," the state of line Jd is FALSE and the
state of line Kd is TRUE. With reference back to FIeL
54, as none of AND ~ates 934 through 937 have all of
the inputs thereto simu1t::meously TRUE, the state of 0:'1tput line s is FALSE, thus indicating that the sum of the
"d" bits plus the "e" bit carry is a binary "0."
Finally, as thc states of both of lines Kd and re are
TRUE, all of the inputs to AND g:lte 929 are simultaneously TRUE. As a result, the state of output line t h
TRUE, thus indicating a binary "I" carry resulting from
addition of the He!" bits pIllS the "('''bit cnrry.
Therefore, as the state of output line t is TRUE and
the state of each of output lines s, r, q, and ANa is FALSE,
the sum of the digit "7" (binary 0111) and the digit "9"
(binary 1001) is therefore indicated as being "16," or
binary 10000. The binary sum-i.e., lOOOO-j, converted ,to a bin::ry-coded-decimal form in the following
manner: As the state of the single input to Al-.JD gate
948 (FIG. 54) is TRUE, the state of output line EAS is
TRUE, thus indicative of a decimal "1" carry. Therefore. as the state of each of lines EAS and (q)' is TRUE,
the ~tate of output line ANb is likewise TRUE, thus indicating that the value of the "b" bit of the sum digit is a
binary "I." As the state of each of lines (q)', t, and
(SAS)' is TRUE, all the inputs to AND gate 942 are
TRUE, thus rendering output line ANe TRUE and thereby indicating that the value of the "e" bit of the sum
digit is a binary" 1." As none of AND gates 945 through
947 have all of the inputs thereto simultaneously TRUE,
the state of line ANd is FALSE and thereby indicat'~s
that the high-order bit '"d" of the sum digit is a binary
It is now evident that, upon completion of the jllst-

described addition operation of the two decimal digits
"7" and "9," the state of output line ANa is FALSE, the
state of output line ANb is TRUE, the state of output
Jine ANe is TRUE, and the state of output line ANd is
FALSE. Thus, the states of output lineS ANa throu:~h
ANd collectively represent the sum digit "6" (binary
0110). As the state of output line EAS is simultaneously
TRUE, as before stated, its state is indicative of the
decimal "1" carry digit.
Following the just-described addition operation of the
two first-order digits taken from the data words stored in
address  from the word in addrcss-A,
afte~ which the difference word is transferred from addrc:'s-A to a p2.rticlllar address in memory as specificd_
As the mode of o')eration of the adder-subtracter unit
in c_ ... __ .. .
1-D_ .... __ ._
I\L._ ... _. __

Fig. No.

Description

61

Gl
7:1
77

AM-n-· ____ ...... _..... ___ ... 'VC _______ ._

74

ARO-O-· _____ .- ___ ......... __ 8C ___ ...... _

74
85
62

BB-O-' _____ ._ ...... _..... _.. M ________ .. _

Bd-X-Y __ ... __ ...... __ ..... _. D ___ .. _.. __ .
BM-n-' __ ... ____ .......... _._ WC. __ .... __

CA(l)-O-·. ___ ... _.... ____ ....
CA(2)-0-· .. _... __ .. _____ .....
CR-O-' ____ ... __ .... ____ .....
CBS-O-' _._. _____ ... ___ .... __
CCR-X-Y ______ ... _........ _

WC._. ____ ..
WC. ____ ... .
WC. __ ..... .
M._. ___ .... .
D._ ........ _

CLC-O-' __ ._ .. _..... __ ._ .. __ .
CM-n-· __ ..... _.. _.......... _
CPA-O-·._ ........ ___ ··· .....
CPM-n-·_ .. _. __ .... _·_·· .... _

M._. __ ._ ... .
WC .. _..... _
SC_._._ .... .
SC_ ... ___ .. .

CYC-O·· - ._ .......... - ..... . I-D_ ... ____ .
D_ .... - .. D_ .. _._ .....
D2-X-Y._ .... _._ .. _. __ ...... _ D. __ .. __ ._.
D
....... ___ _
D3-X-Y--.- ............. -- .. .
D4-X-Y •.. - ....... --.-.-- .. -- D_ .. _._ ... ..
D
__ .. _____ ..
D5-X-Y-- ....... --.-.-- ..... .
D6-X-Y._ ..... -.... --.--.-- .. D._._._ .... _\
D7-X-Y_ ... ___ ._ .. _......... . D_ ......... _
D8-X-Y __ .- ..... -... -- ...... - D __ ...... _._
DU-X-y ___ ... _... __ ... · ..... . D ____ ._ .. __ _
DAD-O-' __ ......... _..... _._ SO. ________ _

gf.:-i.:-f.-_~~::::::::::::::::::

74

74
74
74

81
85

82
74

7-1
H
61

fi3

6a
03
6:!

63
63
63
63
63
63
75

Increment dlgit·connter.
Decrement (1i~it-coullter.
Increment li'-counh·r.
If the di~it just rcac] from thc paper tape is an alternate·lnstruction symbol, go to Stop-Y;
ot.herwIse, go to Stop-X.
COllY word of address·A Into memoflt at address specified by section·n 01 instruction
register.
Adafter, go to
Step-Yo Wbon ledger card is all the way into carriage prior to reversal, go to S(cp·X
if a clock pulse has not been picked uJl.
Close acconnting maelline carriage.
Clear memory address sl,"cified hy seetion-n of instnwtion register.
Complement word of address-A nnd store resu1t 1n address-A.
Complement word of memory address specified by section-n of instruction register and
store result in same address.
Increment bit-counter.
If digit-connter is at "0," go to Stop-Y; otherwise, go to Step-X.
If digit-counter is at 1'1/' go to Step-Y: otherwise, ~o to St<:p-X.
If di~it-('ount.er is at "2," to to Stcp-Y; otilCf\l,riflO, go to Step-X.
If digit-conuter is at '3," go to StOl}-Y; otherwise, go to Step-X.
If digit counter is at 114/' go to Step-Y: oth('rwi~e, go to Step-X.
If digit-counter is at "5,17 go to Step-Yj othcrwi~c, go to Step- X.
If di:nt·eonnter is at "6," go to 8(op-Y; otherWise, go to Step-X.
If (Hgit~counter is at 117/' go to Step-Y; otherwise, g-o to Sten-X.
If digit·countcr is at '18," to to Step-Y; othe-Twi:::e, go to Step-X.
If digit-counter is at "9," g-o to Stcp·-Y: otherwise, go to Step-X.
Add a constant to word in address-B and store sumln address-B.

3,112,394

127

DR-O-. ____

~~~~

__________

JI-D~Y_P~

128
SUBINSTRUCTIONS-Contlnued

____ I_-F-L ________ _

71

JM-n-* _______________________ M _________ _

60

K.p-X-Y _____________________ D __________ _
KEY-O-* ____________________ VTD ______ _
_______ _______ __________ l'vL ________ _
],.pX-Y ______ ____________ _____ j) - ______ ----

70
75
85

LI-X-Y ________________ ______ D _________ __

57

L2-X-Y _ _____________________ D _________ __

57

]~O-'

L3-X - Y ______________________ D _________ __
IJF A-O-* ___________________ __
LK-O-* _____________________ _
LL--O-* _____________________ __
MA-n-* _____________________ _

M ________ __
VTll ______ _
M _________ _
WC _______ __

~m:
m=2=::::: :::::: ::::::::
MB1(I)-O-* _________________

]1,1. ________ _

~

M _________ _
M _________ _

M 131 (3)- 0-' _________________ _ M _________ _

1\11l2(1)-0-' ________________ __ M ____ _
1\1B2(2)-0-' _______________ _ ]\,1. _______ __
MI-O-' ________ ._ ___ ._ _____ __ WC ________ _

57

57
85
75

85
75
81
81
81
81
81
81
76

MIC-O-* ____________________ VTD _____ __
MJ -n-' _________ ._ _______ _____ WC _______ __

71

MK-n-* ______________________ 1\1. _______ __

69

MOU(I)-O-* _________________ VTD ______ _
MOU(2)-0-* _________________ M _________ _
V'l' D ______ _
OIl M(2)-X-Y ________________ D _________ __
OBM(3)-0-* _________________ :\L ________ __
o Il:I1(4)-0-* _________________ :\1. _________ _
_________________ M _________ __

76

on 1'.,.1 (1)-0-* _ ________________
OB~{(5)-0-·

o B N (I )-X-Y _____ ____________
o BN
____________ ______
OBN(3)-0-' __ ___ ____________
o BN (4)-0-' ____ ______________

ll _________ __

76

76
76
76
76
76
76

77

M __________ _
1\1 __________ _
D __________ _

77

OITI-0-' __ ___________________ M __________ _

81

OII2-0-' _____________________ :\L _________ _

81

PC'J'-O-' _____________________ M __________ _

72

(~)-O-'

PF;j>-O-' ______ ________ _______
1'['11-0-' _____________________
1'J"'-O-* ______________________
1'.J1-0-' ____________
J'J5-0-' _ _____ ________ ________
]'R1>-O-' ______ _______________
J' K9-0-* ______ _______ ________
l' H",-O-* ______ _______________
1'R2-0-* _ ____________________
HP8--0-* _____________________
J'1'1'-O-* _____________________
J''fR-O-* __________________
1"1'8-0-' _ ___________ ________ _
l'W",-O-' ______ _______________
Il.;j>-X - Y _____ ________ ________ _
lU-X-Y ____ _________________ _
~_________

~__

M __________ _
1\1. _________ _
!lL ________ _
~L

________ __

M _________ __

1\1. _________ _
cd __________ _
1\-1. ____ -----1\1 __________ _

1\'1. ________ __

:\L ________ __

:\1. _________ _

;'IL _________ _
M __________ _

n __________ _
].J __________ _

77
77

72
55

71
71

n

70
70
68
68
68
76
7n

7G
f<4
68
68

Dt'c'l'OI1Hmt scction-4 or instruction register.
If tile nlgehraie sign of the dilTcreDf'c is positi'.·r, go to Str!)-Y; otherwi,", go to Step-X.
If the dkit iust read from paper tape. is an enel-of-frume symbol, go to Step-Y; otherwise,
~o 1,0 Step-X.
If "J" digit-register is nt ,j15", ~o to St.I~P- Y; otlwrwis<,. go to Step-X.
If F-('ollnter is at "9," r.;n to SteJ)-Y; othenvi::-c. go to Step-X.
H lLcnllnter is 3t "10/ go to Step-¥; othcnvlse, g-o to Stop-X.
Varbble timc-dday.
Go to next step in 8uhprngrmn whrncvcr dr{Jrcssion of a motor har \yill initiate a cycle of
oJl{~ration of the accounting mn.ehinc.
If high-order digit of scction-2 of instruction register is (10," go to Step-Y; otherwise ,go to
Step-X.
U high-order digit o[ seetion- 2 o[instruction register is "1," go to Step-Y; otherwise, 1'0 to
Sten-X.
I! high-order digit of soction-2 of instruction register is "2," go to Step-Y; otherwise ,to to
Step-X.
I! high-order digit ofseetion-2 o[instruc!ion register is "3,", go to Step -Y; otherwIse, go to
Step-X.
l[ high-order digit o[ section-2 o[instruction register is "4," go to Step--Y; otherwise, go to
Stop-X.
Uhigh-oJ'llcr [Jigit ofsection-2 of instruction register, is "5" go to Stcp-Y; otherwise, go t.o
St<'p-X.
If high-order digit of scction-2 of instruction register is "0," go to Step-Y; otherwise. ~o to
Step-X.
If memory addresses specified by sections 3 and 4 of instruction register are equal, go to
Step-Y; otherwise, go to Step-X.
If dif,!:its in F-countcr and (~igit-(,O!lntN nrc eflual, f!0 to Step-Y; othenvise, g-o to Stan-X.
I[ eligits in F-countcr and "J" digit-register are equai, gO to Stcp-Y; otherwise, go to StepJ

X.

Increment sociion-3 of instrnction rc~~ist('r.
'Tran~fl'r contents of particular ..::eclion of instrnction register into word-srlecting register
u.,O; indicatcri lTv the state of a corrl'spontiing- Oll~ of lines 'fI2 through TI5.
If oigit in "J" di~it-register is a u9," go to St(lP_Y; otherWise, go to Btep-X.
Variable time-(lclay.
Store in "J" digit-re!(ister tile datu hit ret)!1 from ledger card, which bit corresponds to
count in hlt-eonnter.
Store in "J P di~it-regist('r the data bit reud frOln memory, which bIt corresponds to count
in bit-counter.
Copy digit of "J" digit-register int<> mmnory a(ldn'ss at digital position Indicat.ed by
digit.countcr, the au.lress in Inclliory being speeirted hy section-ln of instrnction register.
If dit!it in "K" uis-iL-rc;;;i:;;;L<--'f is a 00/' go to Stt'p-Y; otherwise, go to Step-X.
Vari-lble timc-del:ty.
Place ledger card on next po~t.in~ lim'.
If lrw,'-oru('r digit in section-2 of instruction rL'l~i:;1er is f1 400," go to SU)P- Y; otlwr\"jsc, go
to r:;tep-X.
If low-aruer digit in section-2 of instrnction n'f~i::;ter is a HI," go to Stcp-Y,' oth('rw1~f', go
to Step-X.
If low'-arder digit in scction-2 of instrnction TC'?ister is n "2," {;'O to Step-\'"; oth(,T\vi~f', go
to Step--X.
II low-order digit in scction-2 o[ instruction re~;ister is " "3," go to Step-Y; atllerwise ~o
to St.ep--X.
Wait for next linefind impulse.
Vllfillhle time-delay.
Hl'eonl multiple linefind type infnrm~tion on Jc>(\0'['f card.
COpy word front nlCInory into addrc~,s-At and, ~imultaIJ('ously, copy the word dig"it by
digit into "J" digit-register, the address of the \'rord in tnemory bt'ing sprcif18d by
section-Il of the instrncti:1n register.
Dcprrss uPlwr lnotor bar for tOl1eh orwratinTI.
l)epress Uppf"t lllOtor bar for hold op('rlltion.
Depress mid. ill' motor bar for touch opl'rat.inn.
Depress mi,ldlc motor har for hold 0pl'raUoll.
ncpress lo\vor t11otor bar for touch operation.
J)(~I)f(.'SS lower nlotar bar for 1I01il oprration.
Copy instruction "lOrd froin IUt'mory int~) inst.r11ction r~f!j:.;trr. the rnmllory n(!drcss of
the instruction word being indicatetlliY the cont('llts of t.he 'ivord-s!~lecting r('gister.
Variable time-delay.
COllY tile wonl stared in the address in menwry,", specifted by scction-n of thc instmction rngistcr t digit by digit, into the aJ" digit-regist?r.
Copy tbe. digit of the wonl, a.s indicated hy the digit-connter, from mpmory address into
"K" digit-register, thc address in llWJllory being specified by section-n of the instruction registor.
Varia ble time-delay.
Ejcot the ledger card.
Variable tlrne-J to a 'rRUE stilte if the si!)l of the woru rrnd fr()]TI Inemory corresponds to
tho state of line OHM; otherwise, sC't linc. OEN to a FALSB state.
,\Vhen printing occur;.:, place :.1 cQmll13. between rows #5 and #6, and, if there is no significant
(li:;it in ro\VS #6 through #10, print a "zero" precedin~ the COIIlnw.
,YIICTI printing occnrs, plnet~ a comma hl'twrrH rmvs #8 and #9. If therc is no signific:lnt
(ligit in rows #9 or #10, print a "71~'ro" prr'e(',ciing: tl:1e comma.
"'\Vhen amount nLcks ore traveling in n. "sdt.in~" dirl'ctil)n, go to n('xt step in s!lbpro<;ram
each tim~ the timing rack ehangcs di.:;!;ital po~ition and alsu when printing liner C,)LlleS in.
Preset l?-co~lnter to 110."
Prrsct instrnction r(,f!i."tf~r tn "zrro."
PrC'set uJ" nigit-rcg-istpf to 1'0."
Prl_'St't ",I" digit-rc~t'3ter to 1'1."
Prpsrt ".Tn digit-re-gister to "5."
Prnsct "K" di~it-rcgist~r to "0,"
Pn\set .oK" (li):!it-register to "9."
Pre sot H.-connter to "0."
Preset R-counter to "2."
Preset TI-counter to "8."
Transi<1tp paper tape, in a fonvnrd direction.
'rTansl~'Lte paper tape in a reverse direction.
St.up pap:'r tapo.
Pri'~(',t, word-selecting rp:~i~t('r t r) '100."
If H-COnnL('r is HO," go to Step- Y; ot~wnYis[>, rn to Rtpp-X.
If H-counter is "1," go to Stl'p-Y; otherwit::C'. go to Step-X.

3,112,394

129
_ _ _ _ _ Oode

______
Type

ilflI~[~~~ ~~~~~~~ ~ ~~~~~~~~ ~

RA4-0-* ____________________ _
RA5-0-* ____________________ _
RA6-0-* ____________________ _
RA7-0-* ___________________ __
RAS-O-* ____________________ _
RAIl-O-' ___________________ __
RAD-n-' ____________________ _

130
_

D.----------1,L__________

Fig. No.

----~;I-I~;~.Q:~~:_;;~~~.:~:~Q-;tep-~;oth"rwise, ~~~~t~p:;-------8~)

F.n~;r~i'l,\~ nr~t-()r.h~r mek-stoppiL1',2: solenoid.
En('r~iw s!'cond-ordcr r:lck-stoppiug ~OlL'llOit1.
Jf:nrrgizc third-ord(1r rack-sLoppillfJ solenoilL
ErlC'f!:lze fourth-order T;)ek-stopping solenoid.

RO

~L__________
~l___________

M______ __ ___
M ___________

80
80
80
8ll

M______ _____

80

Energize seventll-ordcr raek-stoppong flolcnoid.

!\L__________

80

M___________

80
80

Encrgi:oC' eighth-order r8,('k-~torplng solf'noid.
Epl'r~~i?e ninth-order rack-stopping solenoid.
Ener~hc teuth-order rack-stopping solenoid.
Add tho word in the ad,lrr,s specified hy section-n 01 the imtruction re~lster to the word
In addres~-·A, and store snm in address-A.
Preset R-countcr to H2."
If nce~unting machine re:T~rsc key is depressed, go to Stcp·-Y; if nnt, go to Step-X.
I'~1cllnton-CO!Hl("r a dl~lt fron: word in memory address specifted by section-n 01 the

:r...L._________

77
fi8

RLR-O-* _ ___________________ M __________ _

68

VTD_ -- ----

RRS-O-* ____________________ ir~_~::::::
RSB-n-' _____________________ SC _______ _
SA(l)-O-* ___________________ _
SA(2)-0-* __________________ __
SAM-O-' __________________ __
S 13 (1)-0-* __________________ __
S B (2)-0-* ___________________ _
SEB-O-* ____________________ _

Description

1L__________

SC__________
Rb-O-* ____ _______ __ ____ ___ ___ M __________ _
REV-X-Y ___________________ D __________ _
RLM-n-* ____________________ M __________ _

~~t~-=-"*~~~::::::::::::::::::

I

SC _______ _
SO ________ VTD ___ _

SC __ _
SC _________ _
V'I'D ______ _

77
fiR

77
78
81

78
78
78
79
79
79
79
79

M _________ __
M __________ _
TDA-X-Y __________________ _ D __________ _

75
69

TDS-n-* _____________________ M __________ _

60

~1;1f.-=(;:."._~::: ::::::::::::::::

fifth-order rack-stopping solrnoid.
Energize sixth-order rack-stopping solenoid.

Enrr~lce

In;;tr:lctlOn re,!.nster, wInch dIgIt corresponds to connt in dF'It-countcr
I'resct the count of the R-countcr to correspond to low-order (Ugit olsectio~-2 olinstructlon
register.
Variable time-delay.
Upon depression ofrrsumc-p!'ogram-bar, go to next step in subprogram.
En('r~ize ra('k~release solenoid.
Subtract ·WOl',.1 in memory from word in nddress-A and store remainder in address-A
t,he adtire:::s in memory hl'dng specified by f;eciion-n of the instruction registe.r.
t
Shift word of ad'lrcss-A one 1)lacc to left a!ld ,tore result in address-A_
Bhift word of addn1 ....s-A O!lC plac.·c to rif~ht and store result in nddress-A
Varbhlc lime~dclav.
~
< .
Shift word of addr,·ss-il one pinee to left and store reslllt in ad,lress-B.
ShIft wore of addrr.ss-ll one place to right and f;torc result in atldress-B
Variahle time-df'lny.
.
Copy contelll~ of F-cciion-u of instruction r('~istcr into word-seleding r(>gi~tt·r.
Go to next step when the ontpu! of th,· paper tanc clock is rendered TRUE.
If ~~c character just read from the tape is a dot" digit, go 10 810p-Y; otheTly],e, go t,) Step-

Stoi'e the datajllst re.ad from tlle talle In memory address specified by contents ofscction-n
of instruction register.
•

66. Word-Cycle Subinstl'llctions
30 completion of the last read-write bit cycle, for control
purposes. Thus, the total time required for completion
Each of the previously-described word-cycles is herein
of a word-cycie operation is 1.68 milliseconds.
classified in one of three categories, depending upon the
During the first bit time period preceding the first readpat licular mode or sequence of operations initiated therewrite bit cycle, transfer to the word-selecting register
bJf- 1he first category comprises word-cycles (AM-n-*),
(B.M-n-*), and (MA-n-*), which are hereinafter re- 35 of the selected memory address previously stored in the
instruction register is effected by selectively en.ergizing
spectively designated "AM," "BM," and "MA" wordone
of lines Tl2 through TIS (FIGS_ 64 and 64) in the
cycles. As shown in the just-preceding chart, an "AM"
manner previously described with respect to the mode
word-cycle initiates the copying of t~1e word of address-A
of operation of instruction register. Also during the
into the memory address specified by a particular section
of the instruction register; a "BIVI" word-cycle initiates the 40 first bit time preceding the first read-write bit cycle, the
states of the particular signal lines that initiate the secopying of the word of address-B into the memory adlection of a particular one, or ones, of memory addresses
dress specified by a particular section of the instruction
"'''' through 99 and addresses "A" and "B" are selectively
register; and a "MA" word-cycle effects the copying into
rendered TRUE_ For example, as shown in FIG_ 60,
address-A of the word located in tile memory address specified by a particular section of the instruction register, 45 in order to initiate anyone of word-cycles "AM," "BM,"
"CJ\1," "1fA," "MJ," or "111," the state of a correspondthe word also being simultaneously copied digit by digit
ingly-labeled input line to logical OR 3116 is rendered
into the "J" digit-register_
TRUE and thereby renders the state of output line l'vlYW
The second category comprises word-cycles (CA-O-*),
TRUE also_ As previously described, the state of output
(CB-O-*), and (CM-n-*), which are hereinafter respectively designated "CA," "CB," and "CM" word-cycles. 50 line MYW is rendered TRUE for a period of 1680 microseconds to permit one of V-driver output lines YD",
Again, as shown in the just-preccding chart, a "CA"
through
YD9 (FIG_ 65) to be selectively energized for
word-cycle is capable of selectively initiating two distinct
twenty-microsecond periods by selected ones of output
modes of operation_ The first mode of operation seleclines W",

(FIG. 71) and PKop (FIG. 70) experience a TRUE-lo-FALSE reversal of state when line AD is rendered FALSE at the first TIME-4. Consequently, both the "1" and "K" digit-registers are respectively preset to "0" by lines Plop and PK at the first TIME-4 when line AD is rendered FALSE. With reference to FIG. 53, also at TIME-4 when line AD is rendered FALSE, the prime input to flipflop 6000 experiences a TRUE-to-FALSE reversal of state, so that line PCI is thereby rendered FALSE. Thus, in a sense, carry flipflop 6000 of the adder-subtracter unit is preset to "0." As shown in FIG. 79, when line DDF is rendered FALSE at the Hrst TIME-4, the state of flipflop 6105 is reversed, so that output line SHA is rendered TRUE thereby. When line SHA is rendered TRUE at the first TIME-4, digit-cycle lines MK (FIG. 69) and AJ (FIG. 71) are both rendered TRUE thereby also at the first 3,112,39·1 137 138 TIME-4. With reference to FIG. 60, when line SHA is rendered TRUE at the first TIME-4, line (SHA)' being simultaneously rend:n~d FALSE, output line ZA is rendered FALSE. As shown in FIG. 60, as line MK is rendered TRUE at TIME-4, output line MYW is also rendered TRUE for the first time at TIME-4. It is to be noted that, at the first TIME-l when line ZA was rendered TRUE, output line A'iVY is also rendered TRUE thereby. Consequently, due to the fact th::tt line AJ is rendered TRUE at TIME-4, output line A YW remains TRUE even though line ZA is rendered FALSE at TlME-4. When line CFF is rendered TRUE at the first TIME-4, all the inputs to logical AND 1094 are simultaneously TRUE. Consequently, at the second TIME-I, the state of flipflop 6038 is reversed, so that output l:n~ Si\IC is rendered TRUE thereby. Immediately thereafter, a sequence of four read-write cycles of operation are carried out in essentially the same manner as previously described with respect to that portion of the description entitled "Detailed Read-Write Cycle." During the first fOllr read-write cycles, the four binary bits of the first-order digit of the word stored in addressA is sequentially read out and simulVmeously stored bit by bit in the "J" digit-register (FIG. 71) via gate 1419 and line JL. Simultaneollsly therewith, the fIrst four binary bits of the first-order digit of the word stored in a selected one of memory addresses ¢r/> through 99 are sequentially read out and simultaneously stored bit by bit in the "K" digit-register (F!G. 7(}) via gate 1383 and line KL. As just seen, it is possible to simultaneously read from a selected one of memory addresses A or B and a selected one of memory addresses ¢.p through 99. However, as before mentioned, a different word cannot be simultaneously written in the two selected addresses. Since it is dcsired that the selccted word in one of memory addresses ¢¢ through 99 be preserved, the firsl-order digit just read from one of memory addresses cPr/> through 99 is simultaneously stored in the first-order digital positions of address-A and the selected one of addresses ¢ through 99. Consequently, with reference to FIG. 60, the information to gate IG38 from line ASA is essentially suppressed due to the fact that the state of line (RAD)' is FALSE durin3 the carrying-out of an "HAD" subcommand. This type of suppression is also necessary during the carrying-out of a "RSB" subccmma!1d, which is to be described hereinafter. During the last bit time of the fourth rend-write cycle, the bit-counter (FIG. 62) is at a count of "d," so that output lines BCa and BCb from flipflops 60£il and 61M2, respectively, are TRUE. Consequently, with reference to FIG. 61, at TIME-4 of the last bit time, the state of the prime input to flipflop 6039 is reversed from TRUE to FALSE, and, as a result, flipflop 6039 reverses state, so that output line CFF is rendered FALSE at nr,rE-4 of the fourth read-write cycle and line CYC is thereafter prevented from subsequently effecting advancement of the count of the bit-counter. When line CFF is rendered FALSE, line (CFF)' being rendered TRUE, the state of the prime input to flipflop 6038 (FIG. 6D) is reversed at TlME-l following completion of the four read-write cycles, and, as a result, the state of flipflop GQ38 is reversed, so that output line SMC is thereafter FAL '.:E. Also at TIME-4 when line (CFF)' is rendered TRUE, lines DDF and IW (FIG. 61) are rendered TRUE at the following TIME-3 and FALSE ten micr05ccor.ds later at T1ME-4. With reference to FIG. 79, when the output of gate 1691} is rendered FALSE at TIr,1E--1 by line DDF, the state of flipflop 6105 is reversed, so that output line SHA is rendered FALSE thercbv. When SHA is rendered FALSE at TIME-4, line ~:H( (fIG. 69) is thereby rendered FALSE, line AJ (FIG. 71) is thereby rendered FALSE, and line ZA (FIG. 60) is thereby rendered TRUE. With reference to FIG. tiO, it is to be noted that, when liJ1e MK is rendered FALSE, line lVIYW is rendered FALSE thereby, and, consequently, the "Y" drivers for memory addresses ¢¢ through 99 are prevented from being energized. However, even though line AJ was rendered FALSE at TIME-4, line ZA was simultaneously rendered TRUE. Therefore, line A YW remains TRUE, and, consequently, the "Y" driver for address-A is permitted to be selectively energized. With reference to FIG. 61. when the output of logical AND 1116 is rendered FALSE at TIME-4, the state of flipflop 6039 is reversed, so that output line CFF is rendered TRUE. Thus, at TIME-4 when line CFF is rendered TRUE, line CYC is likewise rendered TRUE and is rendered FALSE ten microseconds later at TIME1. When line CYC experiences a TRUE-to-FALSE reversal of state at TIME-I, the bit-counter (FIG. 62) is effectively advanced from a count of "d" to a count of "a." Also at TU,iIE-l, line S!>.'fC (FIG. 60) is rendered TRUE by a reversal of state of flipflop 6038. As is evident from the preceding portion of the description relating to the adder-subtracter portion of the computer (FIGS. 53 and 54), immediately following the simultaneous copying into the "J" and "K" digitregisters of bit "d" from each of the first-order digits of the word originally stored in one of memory addresses ¢¢ through 99 and the word stored in 'One of addresses A and B, the slim and carry digits are immediately available at the output of the adder-subtracter unit and ready for respective storage into address-A and carry flipflop 6(lOO (FIG. 53). - --'1-'- 140 cycles, subcommand "RAD" is essentially turned "ON" at TIME-I. During the first bit time of forty microseconds after subcommand "RAD" is "ON," the control circuitry for the memory is properly conditioned for simultaneous reading and writing with respect to address-A and a selected one of addresses ¢¢ through 99. Thereafter, a sequence of four read-write cycles is initiated, during which the first-order digit of the word in address-A is stored in the "I" digit-register, and, simultaneously therewith, the first-order digit of the word in a selected one of memory addresses ¢¢ through 99 is stored in the "K" digit-register. Following the fil'st sequence of four readwrite cycles, the sum and carry digits of the first--order digits of the two operands appear at the output of the adder-subtractor unit. Therefore, during the next bit time of forty microseconds following the first sequence of readwrite cycles, the control circuitry for the memory is properly conditioned preparatory to writing the low-order sum digit into the low-order digital position of address-A. Thereafter, a second sequence of four read-write cycles is initiated, during which time the sum digit is stored in the proper digital position of address-A. The above sequence of events is sequentially repeated for each of the remaining digits of the two operands until the sum of the two operands is derived "nd stored in address-A. After the addition operation is completc:d, line RAD remains TRUE for one more bit time of forty microseconds for other control purposes and then is renderel! FALSE. It is seen, therefore, that a "RAD" subcommand comprises twenty digit-cycles, each of which is five binary bits in length, plus one spare bit at the end of the subcommand for control purposes. Consequently, the tolal time required to complete a "RAD" subcommand is 101 binary bit times of forty microsecond~ each, or approximately .004 second. The mode of operation of each of subcommands "RSB" (Regular Subtract), "CPA" (Complement in "A"), "CPM" (Complement in Memory Addresses ¢¢ through 99), "DAD" (Add Constant to "B"), and "ARO" (Add Constant to "A") is essentially the same as for a "RAD" subcommand except for minor exceptions, and, conscquently, a detailed description thcreof is not deemed necess~ry for a full and complete understanding thereof. An "RSB" subcommand, for example, essentially differs only in that subtract line SAS of the adder-subtractor unit (FIGS, 53 and 54) is rendered TRUE by line RSB at the beginning of the "RSB" subcommand. '1' -'1-''1' ~~DF ~~ --'1;--1----'10'- F T T F KKF SUDCO:\Il\JA~D I_~~FF T T F --1-"- - ; - ; ; - - ; - ; ; - --1-"- T 'l' 'r :::~::::::: - :, - ~ -=-~:--= --~:-=,---:~: J_-~,: -_ ~.: - i~: CY~~_ F F - - F - --]-,,- TTl F F ---~,-- ,t' F. -;_~ - ~ -~~):~~I~~~}~= :~: ---- --- --- --- ------- --- --- ------ - - - - - ----L__________ T '1' 'r }' '1' F F T T F F F F - - - - - - - - ._--- - - - - - - - - - - - - - - - - - _ . -_._- - - - - - - - - - - - - - - - L__________ '1' '1' '1' F '1' F F '1' '1' F F F 1.' -2_-___-___-__-_-_ 1: --,-1'- --'1'-- - - , 1 ' - - - r ' - " - - T - - - - F - - ~-F- ~T- - - , 1 ' --~-, --1'~-- - -F-- -V-- ---- ---- ---- ---- ---- ---- ---- - - - - - - - - 3___________ 4 ___________ ~~ 'r T '1' F T '1' T F '1' 'l' F =-;-r ~--- T F .. - ~-- F --F - --- --- F F_I '1'-~'r F= '1,- _ _ '1'_ _ _ '1'_ _ _ _'1_'__ ~ _ _'_'__ ~_~_'1'__ I__ 2'.. ___ 1'_1__'1'_ _ _F_I __ ~_ --;r- _ '1' - - '1' -=-'1~__ ~~ --'1-,- --'1-'- --'1-'- L~ --'1-,- --;r- --~r- _ --;r-I--T-_-1--1-"- - - 1 - ' --'1'- -~ ,i---- ---,1'- --]-,,- - - 1 - ' - - - 1 - ' - --'1'--I--F- - p - --'1-'-1--'1-' ~F­ -- - - F - - - F - I - - F - - ----1'-- 3,112,394 142 141 '1'IMING CHART FOR FIRST-ORDI JJI!' SUA MK AJ MYW F F F F J<' SMC XDW T F F T F ]<' For·ty F IntNyal AYW F T F F T F T '1' F F }' F T F F T T T T '1' T F F T T 'l' 'l' T T T F 1st. 11if'roE:('('Olld ---F '[' let. Four Rend-Write Cycles __ __;_, ~I -+--;-,--1---:1'-1'-- - - :_____:._ _ I_(.:...l_60.:.../_'S_CC_.)~_ _ __ 1----·:---·- - - - - -----1----1----1 T '1' T T F F 2nd. Fortv T '1' T F F Interval F F T F F F 'l' 'l' T ------[----1--------1-------1--------1------------ J\!icr:oscrond T F 1----1------1------1------ F - - - - - - 1 - - - - ----1----1-----1----1------1 2nd. Your Read-Write Cyrles -4_-___-___-__-_-_1- - - F - - I - - T - - I - - F - - I - - - F - - I - - F - - : I - - F - - ' - - T - - I - - T - - I - - T - - I (leo J.£gce.) -----L _________ _ -------+----- -----1-----1-------1------ -----1----1-----1----------F T F F F Consequently, the difference between the two digits in the "J" and "K" digit-registers is obtained each time instead of the sum thereof, all of which is fully described previously with respect to that pmtion of the description relating to the adder-subtracter unit. In order to carry out a "CPA" subcommand, the word stored in address-A is complemented and ther~after stored in address-A. To accomplish this, each digit of the word in address-A is subtracted from "0," and the difference digit is stored in the proper digital position of address-A, with the carry digit being stored in the carry flipflop of the adder-subtracter unit, as previously described. To accomplish this, "0" is obtained by presetting the "1" digit-register to "0" at the beginning of the subcommand and, thereafter, leaving the "1" digit-register in the "preset to zero" condition during the entire subcommand. Consequently, during each sequence of four read-write cycles, the particular order digit of address-A is stored in the "K" digit-register. Thereafter, the digit is subtracted from "0" by tbe adder-subtracter unit, and, during the second sequence of four read-write cycles, tbe remainder digit is stored in tbe proper digital position of address-A. A "CPM" subcommand is carried out in a similar manner; however, in carryLng out a "DAD" subcommand, the word in address-B is selectively added to either of the constants 000000000 1 or OOOOOO{}005, and, therafter, the sum tbereof is stored in address-B. This is accomplisbed by first presetting the "K" digit-register to zero and immediately thereafter presetting tbe "J" digit-reigister to "I" or "5" at the beginning of the initiation of the subcommand, depending upon the pal1icular constant desired to be added to the word in address-B. After ,the first-order digit of the word in address-B is stored in the "K" digit-register, the sum digit derived from the contents .of the "1" and "K" digit-registers is stored in the fkst-order digital position of address-B. Thereafter, the "J" digit-register is preset to "0" and remains in the "preset to zero" condition during the remainder of the subcommand. An "ARO" subcommand selectively effects the addition of the word of address-A to the constant O(}OOO00005 and, thereafter, effects storage of the sum in address-A instead of address-B in substantially themme manner as a "DAD" command. Like the previously-described subcommands, a "SA" and a "SB" subcommand comprises twenty digit-cycles, each five bit times in length, plus one bit time at the end of the subcomman.d for control purposes. Thus, tbe length of a "SA" and a "SB" subcommand is 101 bit times F 30 35 40 45 50 55 60 65 70 75 T F F of forty microseconds each, or 4.04 milliseconds. In carrying out the dictates of a "SA" subcommand, each of the ten decimal digits of the word in address-A is effectively shifted, either to the next higher-ordc'r digital position or to the next lower-order digital position therein, which, in effect, respectively multiplies or divides the word in address-A by "ten." An "SB" subcommand effects the shifting of the word in address-B in a similar manner. Before desoribing in detnil the modes of operation effected by the "SA" and "SB" subcommands, a brief description of each will now be given in order to facilitate a full and complete understanding thereof. If it is assumed that the word in address-A is to be shifted one place to the left, the "K" digit-register is first preset to "0" at the beginning of the cycle of operation. Thereafter, the digit-counter is advanced from a count of "9" to a count of "0," and the '']'' digit-register is simultaneously preset to "0." After the "J" digit-register is preset to "0," the first-order digit of the word in address-A is transferred to the ''1'' digit-register, and the contents of tbe "K" digit-register-i.e., "{}"-is stored in the first-order digital position of address-A. Thereafter, the digit-counter is advanced from a count of "0" to a count of "1," and the "K" digit-regis,ter is again pr~set to "0," even though, in fact, the digit·register is already effectively storing a "0.". After the "K" digit-register is preset to "0," the second-order digit of the word in address-A is transferred to the "K" digit-register, and the first-order digit of the word, previously sto.red in the "]" digit-register, is stored in the second-order digital position of address-A. TIlereafter, the digit-counter is advanced from a count of "1" to a count of "2," and the "J" digit-register is again preset to "D." After the "j" digit-register is preset to "0," the third-order digit of tbe word in address-A is stored therein, and the second-order digit in the "K" digit-register is stored in the third-order digital position of address-A. Thereafter, the digit coup-ter is advanced from a count of "2" to a count Gf "3," and th~ "K" digit-register is again preset to "0." The just-stated sequence of events is repeated until each of the digits of the word in address-A is sequentially shifted to the next higher-order digital pmiti(>ll therein. In order to shift the word ill address-A one digital position to the right, instead of to the left, as just described, both the bit-counter and the digit-counter are each effectively operated in a reverse direction, and, as a result, reading und writing with respect to address-A are r,112,394 1<14 aim in reverse order. TImt is, btt '\1" of lk tent]l· ol'(1:;r digit of the word in address-A is the first to be read alit. and bit "a" of the first-order digit of the vlOrd in address-A is the last to be read out. Therefore, at the beginning of the operatbn, the "1(" cligit-regist~r is preset to "0," 2nd the digit-counter is decremented from a count of "0" to a count of "9." There.after, the "J" digit-register is preset to "0," niter which the tenth-order digit is stored in the "J" digit-register. After the tenth-ol:-der digit is transferred to ,the 'T' d;git-rcgister, the contents of the "K" digit-register-i.e., "O"-is stored in the tenth-ord~r digital position of address-A. Thereafter, the digitcounter is decremented from a cOllnt of "9" to a COllnt of "8," and the "K" digit-re~ister is preset to "0'," and so on, until the second-order digit of the word of address-A is shifted to the first-order digital position therein. It is to be noted that, in order to preserve the sign of a negative number whose complement is to be shifted a prescribed number 'Of places to the right, the "K" di,gitregister is initially preset to "9," and the numeral "9" i, stored in the tenth-order digital position of the word at the beginning of each shifting operation of the word. Otherwise, the sign is not pre~erved. As the word in addrcss-B is shifted eilher to the left or to the right via an "ASB" subcommand in e~senlial!y the same manner as just described with respect to address-A, u further description thereof is 110t deemed necessary for a full and complete understanding of the mode of op~ra­ tion the'reo-f. As will be seen later, in carrying out u "multiply-Jollardecimal" (MCC-12) or a "multiply-rmd-shift" (l\IUS13) instruction, the .ten-digit word s stored in addrcsses "A" and "B" are effectively combined to form a tVlcntydigtt word, whereby address-B contains the tcn lowerorder digits and address-A contains the ten higher-order di[,>1ts of the twenty-digit word. In order to shift such a twenty-digit word one place to the right, a "SA" subcommand is initiated, whereby the word in address-A is shifted to the right in the same manner as just described. However, at the conclusion of the "SA" subcommand, the original first-order digit of the word is address-A is stored in the "K" digit-register, and a "SB" subcommand is -thereafter initiated. In this instance, however, the "K" digit-register is not initially preset to "0" at the beginning of the "SB" subcommand. Consequently, when the word in address-B is shifted one place to the right, in the manner just described, the original first-order digit of the word in address-A, which is stored in the UK" digitregister, is sto'red in the tenth-order digital position of address-B. Thus, each of the twenty digits of the twentydigit word is effectively shifted to the next lower-order digital position of addresses "A" and "B." More specifically, a "SA" subcommand for shifting ,left is initiated and carried out in the following manner: With reference to FIG. 78, and with additional reference to the following timing chart, in initiating a "SA" subcommand, the reference input toO flipflop 610'1 is properly conditioned, so that, when line AN experiences a TRUE-to-FALSE reversal of state, indicating completion of the previollsly-initiated sequence of events to the extent that a "SA" subcommand is permitted to be initiated thereafter, output line SA is rendered TRUE by a reversal of state of flipflop 6101 at the first TIME-I. With reference to the lower left-hand corner of FIG. 62, the state of line GOO is rendered TRUE at TlME-l by line SA and remains TRUE as long as the state of line SA 'remains TRUE. With reference ~o the lower lefthand corner of FIG. 71, the states of lines JA and JJF are also rendered TRUE at TIME-I by line SA. As shown in FIG. 60, the state of line SOD is rendered TRUE at TIME-I due to the fact that the state of line JA is rendered TRUE at that time. Therefore, at the following TIME-3, all the inputs to logical AND 1113 (FIG. 61) are simultaneously TRUE, thus rendering line DDF TRUE at TIME-3. Ten microseconds later, 5 10 15 20 25 30 :15 ;0 45 50 55 60 G5 70 75 at TIME-4,the state of line DDF is rendered FALSE by line C34, and, consequently, the state of flipflop 6039 is reversed, so that the ~tate of output line CFF is rendered TRUE thereby. At TIME-4, when the state of line CFF is rendered TRUE, the state of line CYC is rendered TRUE and remains TRUE for ten microse{;onds, at which time line Cye is rendered FALSE. Thus, when line CYC experiences a TRUE-to-FALSE change of state, the bitcounter (FIG. 62) is incremented from a count of "d" to a count of "a," in the same manner as previously described. With reference to FIG. 79, when the state of line DDF is rendered FALSE at TIME-4, the state of flipflop 6105 is reversed, so that output line SHA is rendered TRUE thereby at TIME-4. As shown in FIG. 71, when line SHA is rendered TRUE, the state of line AJ is rendered TRUE thereby, and, simultaneously therewith, the state of line JA is rendered FALSE thereby. At TIME-3 when the state of line DDF is rendered TRUE, line AD (FIG. 61) is rendered TRUE for a period of tcn microseconds, after which time line AD is rendered FALSE. When line AD experknces a TRUEto-FALSE change of state 'at TIME-4, the digit-counter (FIG. 63) is advanced from a count of "9" to a count of "0," in the smne manner as previollsly described. At TIME-4 when the state of line AD is revc:rsed from TRUE to FALSE, the states of preset lines PJ¢ (FIG. 71) and PK¢ (FIG. 70) are both reversed thereby from a TRUE state to a FALSE state. Consequently. the "J" and "K" digit-registers are both preset to "0" at TIME-4, in the same manner as previously described. At the second TIl\.fE-l, the state of flipflop 6038 (FIG. 60) is rever;,cd, and output line SMC is rendered TRUE thereby 8l1d thus effects a r;:ad-write cycle, in substantially the same manner as previously described with respect to a "RAD" subcommand, to transfer the first-order bit of the first-order digit of the word in address-A, and subsequent storage of the bit in the "J" digit-register (FIG. 71), via selective energization of line JL, all in the manner previously desnibed. At the third TIME-I, the bit-counter is effectively advanced from a count of "a" to a count of "b," a second read-write cycle is initiated, and, consequently, the second-order bit of the first-order digit in address-A is stored in the "J" digit-register. At the fourth TIME-I, the bit-counter is again incremented, a third read-write cycle is initiated, and the third-order bit of the first-order digit of the word in address-A is stored in the "1" digitregister. Finally, at the fifth TIME-I, the bit-counter is incremented to a count of "d," a fourth read-write cycle is initiated, and, as a result, the fourth-order bit of the first··order digit of the word in address-A is s~ored in the "1" digit-register. At TIME-4 during the fourth read-write cycle, the state of flipflop 6039 (FIG. 61) is reversed, and line CFF is thereby rendered FALSE. Ten microseconds later at the following TIME-I, the state of flipflop 6038 (FIG. 60) is reversed, and line SMC is thereby rendered FALSE to prevent a read-write eycle from being initiated at that time. At the following T!ME-3, thirty microseconds after the stale of line CFF is rendered FALSE, the state of line DDF (FIG. 61) is rendered TRUE and remains TRUE until the following TIME-4, at which time line DDF is rendered FALSE. When line DDF is rendered FALSE at TIME-4, the state of flipflop 6105 (FIG. 79) is reversed, so that output line SHA is thereby rendered FALSE at TIME-4. Also at TIME4 when the state of line SHA is rendered FALSE, ~he state of flipflop 6101 is reversed, EO that output line SHB is thereby rendered TRUE at TIME-4. . With reference to FIG. 71, when the state of lme (SHB)' is rendered FALSE, the state of line AJ is thereby rendered FALSE. However, with reference to FIG. 69, when the state of line SHB is rendered TRUE, the state of line KA is thereby rendered TRUE, and,conse- 3,112,394 146 145 quently,the state of line SOO (FIG. 60) remains unchanged. Also at TIME--4 following the fourth readwrite cycle, the state of flipflop 6039 (FIG. 61) is reversed, so that the state of line CFF is thereby rendered TRUE. With reference to FIG. 60, ten microseconds after the state of line CFF is rendered TRUE, the state of flipflop 6038 is reversed, so that the state of line SMC is rendered TRUE at TIME-I. With reference to FIG. 61, ten microseconds after the state of line CFF is rendered TRUE, line CYC eJ.':periences a TRUE-to-FALSE reversal of state and thereby advances the bit-CO'Ilnter (FIG. 62) kom a count of "d" to a count of "a." Consequently, at TIME-I there is again initiated a sequence of four read-write cycles whereby the digit stored in the "K" digit-register-i.e., "O"-is stored in the first-order digital position of address-A. At TIME-4 foHowing the se.:ond sequence of four read-write cycles, the bit-counter being at a count of "d," the state of flipflop 6039 (FIG. 61) is reversed, so that the state of line CFF is thereby rendered FALSE. At the following TIME-I after the state of line CFF is rendered TRUE, the state of flipflop 6038 (FIG. 60) is reversed, so that the state of output line SMC is thereby rendered FALSE. As shown in FIG. 61, at the following TIME-3 after the state of line (CFF), ~s rendered TRUE, ~he state of line DDF is rendered TRUE for a period of ten microseconds and then is rendered FALSE at the following TIME--4. At TIME--4 when line DDF is rendered FALSE, the state of flipflop 6105 (FIG. 79) is reversed, so that the state of line SHA is thereby rendered TRUE. However, at this time the state of line SHB does not reverse, but, instead, remains TRUE. With reference to FIG. 61, at TIME-3 when the state of line DDF [s rendered TRUE, the state of line AD is rendered TRUE for a period of ten microseconds, after which period the state of line AD is rendered FALSE. When line AD experiences a TRUE-to-FALSE change of state at TIME-4, the digit-counter (FIG. 63) is incremented from a count of "0" to a count of '"I," in a manner previously described. At TIME--4 when the state o.f line (SHA)' is rendered FALSE, the states of lines KA and KKF (FIG. 69) are thereby rendered FALSE. However, at TIME-4 when the state of line SHA is rendered TRUE, the state of ldne AK is thereby rendered TRUE, and, consequently, the state of line SOO (FIG. 60) remains TRUE. With reference to FIG. 70, at TIME-4 when lines AD and KKF experience TRUE-to-FALSE changes of states, the state of line PK.p is reversed from TRUE to FALSE and effects the presetting of the "K" digit-register to "0." Also at time-4, the state of flipflop 6039 (FIG. 61) is reversed, so that the state of line CFF is thereby rendered TRUE. When the state of line CFF is rendered TRUE, the state of output line CYC is also rendered TRUE and remains TRUE for a period of ten microseconds, at which time ,the state of line CYC is rendered FALSE. When the state of line CYC experiences a TRUE-to-FALSE reversal of state at TIME-I, the bitcounter (FIG. 62) is 'advanced from a count of "d" to a count of "a." Also at TIME-I, the state of flipflop 6038 (FIG. 60) is reversed, so that the state of line SMC is ,thereby rendered TRUE. Consequently, at TIME-I, a third sequence of four read-write cycles is initiated, in the manner previously described, so that the four binary bits of the second-order digit of the word in address-A are read out and stored in the "K" digit-register (FIG. 70) via lines ASA and KL. At the following TIME-4 after the bit-counter has reached a count of "d," the state of flipflop 6039 (FIG. 61) is reversed, and the state of line CFF is thereby rendered FALSE. Ten microseconds later, the state of flipflop 6038 (FIG. 60) is reversed, and the state of line SMC is rendered FALSE at the following TIME-I to prevent a read-write cycle from being initiated during the following control period. With reference to FIG. 61, 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 at the following TIME-3, the state of line DDF is again rendered TRUE and remains TRUE for a period of ten microseconds, after which time the state of line DDF is rendered FALSE at the following TIME-4. With reference to FIG. 79, at TIME-4 when line DDF experiences a TRUE.to-FALSE reversal of state, the state of flipflop 6105 is reversed, so that the state of output line SHA is thereby rendered FALSE. Consequently, when line SHA experiences a TRUE-to-FALSE reversal of state, the state of flipflop 6106 is reversed, so that the state of output line SHB is also rendered FALSE at TIME-4. Consequently, the state of line AK (FIG. 69) is rendered FALSE at TIME-4 when the states of lines SHA and SHBare rendered FALSE. However, at the same time, the states of lines JA and JJF (FIG. 71) are rendered TRUE. Consequently, the state of line SOO (FIG. 60) remains TRUE. Also at TIME-4, when the state of line DDF is rendered FALSE, the state of flipflop 6039 (FIG. 61) is reversed, so that the state of output line CFF is thereby rendered TRUE. When the state of line CFF is rendered TRUE at TIME-4, the state of line CYC again is rendered TRUE and remains TRUE for a period of ten microseconds,after which period its state is rendered FALSE. Consequently, when line CYC experiences a TRUE·to-FALSE reversal of state at TIMEI, the bit-counter (FIG. 62) is advanced from a count of "d" to a count of "a." With reference to FIG. 60, the state of flipflop 6038 is reversed at TIME-I and thereby renders the state of line SMC TRUE. Thus, at TIME-I foHowing the fourth forty-microsecond control period, a fourth sequence of four read-write cycles is initiated, so that the first-order digit that was originally stored in address-A, but now is stored in the "I" digit·register, is stored in the second-order digital position of address-A. Consequently, it is seen that the digit originally stored in the first-order digital position of address-A is now shifted to the second-order digital position therein, and a "0" is stored in the first-order digital position of address-A. After completion of the fourth sequence of read-write cycles, the count of the bit-counter is advanced to "d." Therefore, at the following TIME-4, the state of flipflop 6039 (FIG. 61) is reversed, so that output line CFF is thereby rendered FALSE. At the following TIME-I after the state of line OFF is rendered FALSE, the state of flipflop 6038 (FIG. 60) is reversed, so that the state of output line SMC is thereby rendered FALSE to prevent further read-write cycles from being initiated during the following forty-microsecond control period. The state of line DDF (FIG. 61) is rendered TRUE from TIME-3 to TIME-4 during the following control period and effects advancement of the digit-counter (FIG. 63), via line AD, from a count of "I" to a count of "2." Thereafter, the "J" digit-register (FIG. 71) is preset to "0," and the third-order digit of the word in address-A is stored therein. The just-described sequence of events is sequentially repeated until each of the digits of the word stored in address-A has been shifted to the next higher-order digital position therein, hereinafter known as "shifting to the left." After ea:ch of the digits of the word in address-A has been shifted to the next higher-order di'gital position therein, the digit-counter is, at that time, at a count of "9," the bit-counter is at a count of "d," and the states of lines SHA and SHB are FALSE, thus indicating the end of the shift cycle. Therefore, at TIME-I of the following forty-microsecond control period, the state of flipflop 6040 (FIG. 61) is reversed, so that output line PC is thereby rendered TRUE. Consequently, the state of line AN is rendered TRUE at the following TIME-4 and remains TRUE for a period of ten microseconds, after which period line AN is rendered FALSE. When line AN experiences a TRUE-to-FALSE reversal of state, the state of flipflop 6101 (FIG. 78) is reversed, so that the state of line SA is thereby rendered FALSE, thus 3,112,394 147 148 completing the cycle of operation of the "SA" subcommand. PARTIAL TIME ; SA GOO JJF JA TIMI~Q instruction word is stored in the instruction register, the two decimal digits stored in section 1 thereof determine OHART FOR "SA" SUBCOMMAND SOO DDF OFF CYC SHA SIIB AJ AD PJ PK SMC KA KKF AK --- -------------------------------------1------L________ '1' T F F F F F '1' T T F F F F F F F ------------------------- -------------2_________ T T T T T F F F F F F F F F F F F }<' 40 pSec. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Control 3_________ T T T T T T F F F F F T T T F F F J<' Period 4_________ T T F F T F T '1' T T F F F }<' F - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ---1-------L________ T T F F T F T F T ]' T F F F '1' F F F - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - "AJ" Read-Write Diglt.Cycle - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - (160 pSCc.) 4_________ T T F F T F F F '1' F T F F F T F F F ----------------- -- ------ ------------ --1-----L________ T T 2_________ T T 3_________ T T F }<' F '1' F F F '1' j<- T F }<' F T F F F T F '1' F F F T T F F F T F F F F F F F F F F F F F F F F 40 "sec. Control Period --- -------------------------------- ---4_________ T T F F T F T '1' J;' '1' F F F F F T T F --------------------- ------ ------------1-----L________ T T F F T F T F F T F F F F T T T }<' - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - "KA" Read-Write Digit-Cycle - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - (160pSCc.) 4_________ T T F F '1' F .1" F F T F F F F T T T F L________ T T F F T F F F F T F F F F F '1' T F --------------------------------------- 2_________ T T F }<' T F F F F T F }<' F F F T T F 40 "sec. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Control 3_________ T T F F T T F F F T F T F T F T T F Period 4_________ T T F F T F T T T T F F F F F F F '1' -------------------- ---------- ------1--1------L________ T F T F F F T F F F T F T '1' T F F - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - "AK" Re,ad-Wrlte Digit-Cycle - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - (160 "sec.) 4_________ T T F F T F F F '1' T F F F F '1' }<' F T T - - - '1' ------------------------- -----------1------L________ ]' T T F F F F F T F F F F F F '1' T --------------------------------------- 2_________ T T F F T F F F T T F F F F F F F '1' 40 "sec. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Control 3_________ T T F F T T F F T T F F F F F F F '1' Period 4_________ T T T '1' T F T T F F F F F F F F F T T T '1' F T F F F F F F T F F F T T T T F I" F F F F F F T F F F ------------------ --------------------1-----L________ T 4_________ L _______ T F "JAn Read-Write Digit-Cycle (160 "sec.) I--;---;---;---;- --;- -F- --F- --F- F' - F - --F- --F- --F- F' -F-I-F- --F-:--F-1- - - - - - - ---I--'------I--I--------------------------~~ If, however, the word in address-A [s to be shifted to the right instead of to the left, a detailed description of the mode of operation of the subcommand capable of initiating the required sequence of events is obtained simply by modifying the previous "shifting left" description by substituting Bd for each occurrence of Ba, Be for each occurrence of Bb, Bb for each occurrence of Be, Ba for each occurrence of Bd, D9 for each occurrence of D, DB for each occurrence of Dl, Dl for each occurrence of D8, and D for each occurrence of D9. If the word in address-B is to be shifted instead of the word in address-A-i.e., via a "SB" subcommand-the preceding descriptions are to be modified by substituting SB for SA, IB for I A, BI for AI, KB for KA, and BK for AK. 69. In8tructions Generally As preY'iously described, there are eighteen basic instructions ,to which the computer is responsive. Five of these basic instructions concern the ledger card sensing equipment and -the accounting machine portion of the computer; one is concerned with the reading of punched paper tape; and twelve are concerned with arithmetic and control functions within the computer. The first step to be carried out in the cxeoution of each instruction is the reading-out from memory of the next instruction word in the program and storage of the instruction word in the 'instruction register. After the the particular type of instruction, or sequence of opera50 tions, to be executed next. For example, if the two-digit decimal number in section 1 of the instruction register is "00," an "enter-keyboard-words" instruction is ex)ecuted, whereby all data thereafter transferred between data-handling sections of the computer is in accordance 55 with a .particular sequence pattern dictated by this particular instruction. The execution of each instruction condudes by effecting the storage in the word-selecting register of the address in memory of the next regular instruction word, the 60 address in memory of the next regular iinstruction word being specified by the contents of section 5 of the present instruction word. After the address of the next instruction word is properly stored in the word-selecting register, the computer 65 may immediately carry out ilhe dictates of the next instpuction word read from memory, or may pause for a period of time before executing the next instruction. Whether or not the computer immediately proceeds to carry out ,the next instruction in ,the program depends 70 upon the partioular mode of operation pre-selected by the operator. If the computer is operating in an "automatic" mode, the next instruction in the program is immediately carried out upon completion of the preceding instruction. However, if the computer is operating in a "manual" 7;; mode, all computation stops upon compietition of the 3,112,394 149 execution of each instruction and is not resumed until either the manual or the automatic "mode-selection" push button is depressed. Upon depression of one of the mode-selection push buttons, the sequence of events is as follows: The next instruction word specified by the contents of the word-selection register is read out from memory and stored in the instruction register; the two decimal digits thus stored in section 1 of the instruction register are examined to determine the particular instruction to be carried out; and, thereafter, the computer proceeds to carry out the dictates of that particular instruction. As previously mentioned, for the purpose of convenience in describing in detail the inherently complex mode of operation which the computer executes in carrying out a particular instruction, each of the eighteen different instructions is considered a "subprogram" comprising a plurality of "sub instructions" which are sequentially given to the computer, the sequence of events initiated by the computer in carrying out each of the sub instructions being under the control of the control-counter. Again, as previously mentioned, each of the just-mentioned subinstructions is classified in one of six gcneral categories, labeled "word-cycles," "subcommands," "variable-time-delays," "decisions," "incrementing and decrementing," and "miscellaneous," of which the more complex ones of the various subinstructions have previously been described in detail, and all of which are each related to a specific portion of the computer control circuitry even though such specific portion does not always exist as a separate and distinct entity as such. 150 pared for equality to determine whether there are additional words to be entered into memory from the keyboard or totalizers of the accounting machine. If there is an additional entry to be made, section 3 of the instruction register is incremented, and the just-described se/) quence of events is again repeated. If, however, there are no additional entries to be made, the sequence of events initiated by the EKW instruction is thus terminated. Listed below in somewhat tabular form, and also graphi10 cally illustrated by the flow diagram of FIG. l07A, is a step-by-step description of the various previously described subinstructions to which the computer is sequentially responsive in executing an "EKW" instruction: 15 20 25 30 70. Detailed Description of EKW Instructions The first subprogram to be described in detail is concerned with the execution of an EKW instruction which effects the storage in memory of amounts entered into the accounting machine keyboard or taken from a preselected one or ones of the totalizers therein. An EKW instruction may be considered as comprising four distinct phases or groups of subinstructions, during the first phase of which all computation and data-handling activity within the computer ceases until an amount is indexed into the keyboard of the accounting machine portion thereof, or until the machine carriage is tabulated to the next stop; however, if an "automatic-resume-program" has previously been specified, all activity ceases only llntil the carriage reaches a stop. The second phase of the subprogram is concerned with initiating a cycle of operation of the accounting machine; consequently, the high-order digit in section 2 of the instruction register is examined to determine the required cycle of operation of the accounting machine to be initiated. Thereafter, the required machine cycle is automatically initiated by proper actuation of the required motor bar when the resume-program-bar is subsequently depressed by the operator. Upon completion of the machine cycle, the differentially-set positions of the amount racks collectively represent the amount to be stored in memory, as previously described. The third phase of the subprogram is, therefore, concerned with examining the printed circuit switch on the rear of the machine to determine the amount just entered into the keyboard, and subsequent storage of the amount in address-A. If reverse key REV (FIGS. 2 and 44A) has previously been depressed, indicative of a negative amount being entered into the accounting machine keyboard, the word initially stored in address-A is complemented before being subsequently stored in the selected address in memory. However, if reverse key REV is not depressed, the word initially stored in address-A is complemented before being subsequently stored in the selected address in memory. However, if reverse key REV is not depressed, the word initially stored in address-A is subsequently transferred to the selected address in memory. During the last phase of the subprogram, the contents of sections 3 and 4 of the instruction register are com- 35 40 45 Step Subinstructions Description L ____ :1.11-0--2 ______ _ Copy the instruction word from memory Into the instruction reglster, the address In memory of the next instruction word being indicated by tbe contents of the wordselecting reglster. If the number thus stored in section 1 of the instruction reglster is "00," carry out the subinstruction listed in Step-2 oC the following EKW subprogram: 2 ______ rFq.-0-3_. ___ _ Pro,ct the F-counter to "0"; thereafter go to Step-3. 3______ GO-iH ______ _ Go to Step-4 in the subprogram whenever depreSSion of a motor btlr will initiate a machlno cycle. 4- _____ L3-5-6 _______ _ If the low-order digi t in section 2 of the Instruction register is a "3," go to Step-6; otherwise., go to Step-5. 5 ______ RPB-{l-L ___ _ Upon depression of the resume-program-bar, go to Step·fl. 6______ IIq.-8-7- - ----. It the high-order digit in section 2 of the instruction register is a HO," go to Stcp-7; otherwise, go to Step-B. 7 ______ MBq.(I)-O--IL Depress the upper motor bar for a "touch" operation; thereafter, go to Step-IS. 8 ______ HJ-JQ--9 ______ _ If the high-order digit of section 2 of the instruction register is a "1," go to Stcp-9; otherwise, go to Step-IO. L ____ MBq.(2)-Q-18._ Depress the upper motor bar for a "hold" operation; tbereafter, go to Step-18. 10_____ TI2-12-1L ____ _ H the high-order digit of sectiou 2 of tbe instruction register is a 112," go to Stcp-ll; otherv,ise, go to Step-12. 11 _____ :MBI (J)-O-IL Depress the middle motor bar for a "touch" operation; thereafter, go to Step-18. 12_____ H3-14-13 _____ . H (he high-order digit of section 2 of the instruc· tion register is a "3," go to Step-13; otberwise, go to Step-l4. 13_____ MBl(2)-O-IL Depress the middle motor bar for a "hold" opcration; thereafter, go to Step-IS. 14-____ H4-Hl-15 _____ _ If the high-order digit of scction 2 of the. instruction register is a "4," go to Step--15; othen\isc, go to Step-16. 15_____ MB2(1)-O--IL Depress the lower motor bar for a" touch" operation; thereafter, go to Step-18. 16 _____ H5-Q-17 ______ _ Go to Step-17 if the high-order digit of section 2 o[ the instruction register is a "5. 17. ____ MB2(2)-Q-18_. Depress the lower motor bar for a" hold" o~r­ ation; thereafter, go to Step-18. 18 _____ Ll-20-l9 _____ _ Go to Step-19 if the low-order digit of sectIon 2 of the Instruction register is a "I"; otherwise, ~o to Step-20. 19 ___ ._ OIIl-O--ZZ ____ _ When printing occurs, place a comma between rows #5 and #tl; if there is no significant digit in rows #tl through #10, print a "0" prect>diug the comma; thercaftN, go to Step-22. 20 _____ L2-22-21 _____ _ If the low-order digit in section 2 of thc instruction regi~tcr ~s a 112/' go to Stcp-21; otherWise, gO to Step-ZZ. 21. ____ OII2-0-22 ____ _ When [}finting occurs, place a comma between #8 and #9; if tllere Is no significant digit in rows /Ill or #10, print a "0" preceding the comma; thereafter, gO to Step-22. 22 _____ PCT-O-23 ____ _ When the amount racks are tmveling in a "setting" direction, go to Step-23 Pilch time the timing rack changes d!gital po>ition and also upon engflgement of the printlng·liner. 23 _____ AF-0-24 ___ . __ _ Increment the F-cotmter; thereafter, go to Step-2-i. 24. ____ F9-22-25 _____ _ 00 to Step-25 il the F-countN is at a count of "9": otherwi>e, go to Step-22. 25_ ____ CA(Z)-O-2L __ Copy Into address-A the word collectiTely indicawd by the condit-ions of the rack readout switches; thereafter, gO to Stel>-26. 26 ___ ._ REV-28-2L __ Go to Step-27 if the "reverse" key Is depressed; otherwi,e. ~o to Step-28. 27 _____ CPA-O-28_. __ _ Complement the word stored In address-A; thereafter go to Step-28. 28_ ____ AM-3-29 _____ _ Copy the word of address-A Into the memory address specified by section 3 of tbe instruction register; thereafter, gO to Step-29. 29 ____ • I34-30-3L ___ _ Go to S tep-31 if the memory addresses specified by sections 3 and 4 of the Instruction register are equal; otherwise, gO to Step-30. 30_ ____ IN4-0-2 ______ _ Increment section 3 of the Instruction register; thereafter, go to Step-2. 31. ____ S'1'D-5-* _____ _ Copy the contents of section 5 of the Instruction register into tbe word-selecting register. H 50 55 60 65 70 75 3,112,394 151 152 Before proceeding with a detailed description of the mode of operation initiated by each of the eighteen basic instructions-i.e., "enter-keyboard-words" (EKW-OO) through "enter-punched-tape" (EPT-17)-it is to be noted that, in an effort to avoid in the following description an undue multiplicity of back-and-forth references with respect to the various figures of the drawings, the particular portions of the computer circuitry utilized in carrying out a particular instruction have essentially been taken from FIGS. 52A through 85 and re-assembled into a composite circuit diagram relating to that particular instruction. For example, certain significant particular portions of the computer circuitry utilized in executing an EKW instruction are combined and logically illustrated in FIGS. 89A and 89B as a composite circuit diagram. As previously described, the first subinstruction initiated and carried out in the execution of each instruction is a "MI" word-cycle, which effects the transfer to the instruction register of the word in memory previously stored at the address indicated by the contents of the word-selecting register. Also, as previously described, a "MI" word-cycle is initiated each time the state of line MI is rendered TRUE. As shown in FIG. 76, if the computer is operating in an "automatic" mode, as indicated by a TRUE state of line AUT, a "MI" word-cycle is automatically initiated by a reversal of state of flipflop 6092 when the state of line AN is rendered FALSE, line AN being rendered FALSE when the previously-initiated cycle of operation is completed. However, if the computer is operating in a "manual" mode, a "MI" word-cycle is initiated only by a depression of push-button MNI-MN2 (FIGS. 1 and 84), which also causes a reversal of state of flipflop 6092 (FIG. 76). After the next instruction word is transferred to the instruction register via the "MI" word-cycle, if the two decimal digits stored in section 1 thereof correspond to the code designation for an "enterkeyboard-words" instruction-i.e., "OO"-the state of line EKW is rendered TRUE in a manner previously described with respect to FIG. 56, and, consequently, an "enter-keyboard-words" instruction is thereafter executed in the following manner. It is, however, assumed that when the "enter-keyboardwords" instruction is first initiated: the able arm portion ( 497) of the accounting machine is in the non-deflected position shown in FIG. 38, and, consequently, the contacts of switch 496 are closed, thus indicating that motor bars 23, 27, and 28 are not disabled by able arm 497; that the carriage of the accounting machine is not tabulating over a carriage stop, as indicated by a closure of the contacts of switch 510 (FIGS. 43 and 82); that the accounting machine is in home position, ready for a cycle of operation thereof to be initiated, as indicated by a closure of the contacts of switch 528 (FIGS. 41 and 82); and that a paper-tape-punching operation is not to be initiated, as indicated by a closure of contacts SC41-3 (FIG. 82) of switch SC41 (FIG. 13). The just-mentioned assumptions having been satisfied, the state of line GO (FIG. 82) is rendered TRUE, thus indicating that a cycle of operation of the accounting machine is now permitted to be initiated. With reference now to FIG. 61, the state of line AN is reversed from TRUE to FALSE at TIM£....I, indicating completion of the previously-initiated "MI" wordcycle, as previously described. With reference now to FIG. 72, when line AN is thus rendered FALSE, the state of lines MIN and PF", are likewise reversed from TRUE .to FALSE. As previously described with reference to FIG. 72, when the state of line PF", is reversed from TRUE to FALSE, the F-counter is thereby preset to a count of "0." With reference to FIG. 89A, as a result of line MIN thus being rendered FALSE, the state of flipflop 6089 is reversed, so that line KEY is rendered TRUE thereby. As all of the inputs to logical AND 1743 are simultaneously TRUE when line KEY is thus rendered TRUE, the state of line EKL is thereby rendered TRUE and thus effects illumination of the enter-keyboard-words lamp EK (see also FIG. 2), indicating that the computer is ready for an amount to be indexed into the keyboard of the accounting machine portion thereof. Also, prior to line EKL being rendered TRUE, the state of one of lines L, Lt, or L2 is previously rendered TRUE. depending upon whether the low-order digit ,in section 2 of the instruction register (FIG. 57) is a "0," a "I," or a "2," respectively. Therefore, if the low-order digit is a "0," decimal-point lamp P", (see also FIG. 2), located between amount rows #2 and #3 on the accounting machine keyboard, is illuminated when line EKL is rendered TRUE; if the low-order digit is a "1," decimal-point lamp PI between amount rows #5 and #6 is iHuminated; and, if the low-order digit is a "2," decimal-point lamp P2 between amount rows #8 and #9 is illuminated. As will later be seen, a decimal-point and enter-keyboardwords lamps both remain illuminated until the resumeprogram-bar RPB (FIG. 2) is depressed. With reference to FIG. 38, when the resume-programbar push button is depressed, the common plunger of switches RPI and RP2 is actuated thereby. As shown in FIG. 84, when ,the resume-program-bar is depressed, the normally-opened switch contacts RP2 are closed, and normally-closed switch contacts RPI are opened thereby. Consequently, at the following TIME-I after the resumeprogram-bar is depressed, the state of flipflop 6138 is reversed, so that output line RP is thereby rendered TRUE. At TIME-l following the release of the resume-program-bar, the state of flipflop 6138 is again reversed, so that line RP is rendered FALSE thereby. As shown in FIG. 78, as a result of line RP experiencing a TRUE-to-FALSE reversal of state, the state of flipflop 6099 is reversed, and line RPB is rendered TRUE thereby. With reference back to FIG. 89A, at TIME-3 after line RPB is thus rendered TRUE, the reference input to flipflop 6118 reverses from TRUE to FALSE, and, consequently, the state of flipflop 6U8 is reversed and line WOA is thereby rendered TRUE. It is to be noted that, if the low-order digit in section 2 of the instruction register (FIG. 57) is a "3," as indicated by line L3 being TRUE, indicating an automatic-resume-program operation, neither of the decimal-point !lamps is illuminated, but, instead, the state of flipflop ()l18 is reversed at TIME--3 even though the resume-program-bar was not manually depressed. However, after the state of line WOA is rendered TRUE, upper motor bar solenoid MB is energized if the high-order digit in section 2 of the instruction register is either a "0" or a "l"(see also FIG. 38); middle motor bar solenoid MBI is energized if the high-order digit in section 2 is either a "2" or a "3"; and lower motor bar solenoid MB2 is energized if ,the highorder digit is either a "4" or a "5." It is to be appreciated, however, that the selected motor bar solenoid is energized when line WOA is rendered TRUE, regardless of whether the high-order digit in section 2 of the instruction register is anyone of the digits "0" through "5." After ,the selected one of the upper, middle, or lower motor bars is automatically actuated, a cycle of operation of the accounting machine is thus initiated thereby. With reference to FIG. 72, when a -machine cycle is initiated, the movable arm of switch 540 is deflected to the left, as viewed, so that line (NT)' is rendered TRUE thereby, line NT, of course, being rendered FALSE. However, if for some reason a machine cycle is not initiated when a selected one of the motor bars is energized, line NT remains TRUE. With reference now to FIG. 81, when the state of flipflop lt1l8 is reversed, so that line (WOA)' is rendered FALSE, the state of flipflop 6120 is reversed, so that line (RF)' is rendered FALSE thereby. Approximately 250 milliseconds later, however, the state of flipflop 6120 reverts back to its initial condition, so that line (RF)' is rendered TRUE thereby. Therefore, if it is assumed that a machine cycle 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 3,112,394 153 was not initiated when line WOA was initially rendered TRUE, as evidenced by line NT remaining TRUE, the state of flipflop 6118 is reversed at the following TIME-l by line AN after line (RF)' is rendered TRUE, thereby de-energizing the previously-energized motor bar solenoid. However, at the following TIME-3 after the motor bar is physically restored to its normal undeflected position, so that line GO is again rendered TRUE, the state of flipflop 6118 is again reversed, so that line WOA is again rendered TRUE, ,thereby re-energizing the preselected motor bar solenoid. If a machine cycle is still not initiated when line WOA is rendered TRUE for the second time, the above sequence of events is continually repeated until a machine cycle is finally initiated. As previously described with respect to FIGS. 7 and 51g, photocell 160 is utilized in conjunction with auxiliary timing rack 151 and light source 164 to provide an electrical impulse each time the auxiliary rack, and hence the amount racks, are translated from one digital position to another whHe traveling in a "setting" direction toward the rear of the machine. With additional reference to FIG. 72, each time a slot on timing rack 151 passes between light source 164 and photocell 160, the state of the prime input to flipflop 6071 is reversed from TRUE to FALSE; consequently, the state of flipflop 6071 is reversed, so that line PT is rendered TRUE and line (PT)' is simultaneously rendered FALSE. However, when the tooth portion of timing rack 151 passes between light source 164 and photocell 160, the state of flipflop 6071 is again reversed, so that line PT is thereby rendered FALSE and line (PT), is simultaneously rendered TRUE. As output lines PT and (PT)' of flipflop 6071 are logically connected as input lines to the reference and prime inputs, respectively, of flipflop 6072, the state of flipflop 6072. is reversed, so that output line PCT is rendered TRUE at times corresponding to each digital position of the timing rack, and is rendered FALSE during each period of time the timing rack is being translated from one digital position to another. With reference back to FIG. 89B, each time line PCT experiences a TRUE-to-FALSE reversal of state, line AF likewise experiences a TRUE-to-FALSE reversal of state. As a result, the F-counter (FIG. 72) is incremented by a count of "1" each time the timing rack is translated from one digital position to another. As shown in FIG. 89A, upper motor bar solenoid MB<,I>, if initially energized, is de-energized when the 'F-counter is advanced from a count of "0" to a count of "I" unless the highorder digit in section 2 of the instruction register is a "1"; middle motor bar solenoid MB1, if initially energized, is de-energized when the F-counter is advanced from a count of "0" to a count of "1" unless the highorder digit in section 2 of the instruction register i; a "3"; and lower motor bar solenoid MB2, if initially energized, is de-energized when the F-counter is advanced from a count of "0" to a count of "1" unless the highorder digit in section 2 of the instruction register is a "5." It is evident, therefore, that either a touch operation or a hold operation of a par,ticular motor bar is obtained simply by maintaining the corresponding motor bar solenoid energized for a predetermined period of time. However, wh~n line WOA is subsequently rendered FALSE, any prevIously-energized motor bar solenoid is de-energized thereby. When the F-counter reaches a count of "8," as indicated by line F8 being TRUE, order-hook solenoid OHl (see also FIG. 35) is energized jf the loworder digit in section 2 of the instruction register is a "1," whereas order-hook solenoid OH2 is energized jf tbe low-order digit in section 2 is a "2." As previously described with respect to FIG. 35, when order-hook solenoid OHl is energized, all order-hooks from the third to and including the eighth one are unlatched from their respective type sectors. However, when order-hook solenoid OID is energized, all order-hooks from the third to and including the eleventh one are unlatched from their re- 154 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 spective type sectors. Also, as previously described, the eighth and the eleventh ones of type sectors 67 (FIG. 34) respectively print the sixth and ninth order degits of the amount indexed in the accounting machine keyboard, with each digit being followed by a comma. When the timing rack leaves digital position #8, the state of F-counter line F8 (FIG. 89A) is rendered FALSE and thereby causes a reversal of state of flipflop 6089, which, in turn renders line KEY FALSE. Due to the fact that timing rack 151 is provided with only eight slots, as shown in FIG. 8, additional means are utilized to increment the F-counter from a count of "8" to a count of "9" when the timing rack has essentially reached digital position #9. As previously described with respect to FIGS. 3A and 41, when aligner bar 72 is brought into engagement with the notches formed on the lowermost end of arm 58 to precisely align all of the type sectors 67 in their differentially-set positions just prior to the printing operation, the contacts of switch 550 are closed as a result of clockwise rotational movement of follower arm 519. Consequently, with reference back to FIG. 72, when the timing ~ack is translated to its #9 digital position, so that the prmting-aligner bar is brought into engagement with the type sectors, a closure of the contacts of switch SS~ cau~es a subsequent reversal of state of flipflop 6071, whlch, m turn, causes the F-counter to be incremented from a count of "8" to a count of "9" in essentially the same manner as just described. With reference back to FIG. 89A when the F-counter is advanced from a count of "8," as'indicated by line F8 being rendered FALSE, any previously-energized orderhe ok solenoid is de-energized thereby. At TIME-l after the F-counter has been incremented to a count of "9," the ~tate of flipflop 6118 is again reversed, so that line WOA IS rendered FALSE thereby. When line WOA is thus rendered FALSE, any previously-energized motor bar solenoid is de-energized thereby. With reference now to FIG. 89B, also when line WOA is thus rendered FALSE the state of flipflop 6086 is reversed, so that line CA i~ rendered TRUE thereby. As a result of line CA ·thus being rendered TRUE, a "CA" word-cycle is initiated and thereafter executed, whereby the word collectively indicated by the conditions of the rack-readout switches is read out and stored in address-A in the following manner !he,-?,ord indicated by the rack-~eadout switches bein~ Id~ntIcal to the mount Just entered mto the accounting machme keyboard, as previously described with respect to FIGS. 3B, SA, and 5B. As diagrammatically illustrated in FIG. 67B, digitcounter output lines Dr/> through D9 are individually connected to a different one of conductors 119 disposed on printed circuit board 116. Thus, suppose that the firstorder amount rack is differentially set in digital position #5 corresponding to depression of amount key #5 in the low-order aI??unt row of the ~achine keyboard; i.e., the fir~~-~:der dIgIt of the amount mdexed. in the keyboard is Consequently, when a machme cycle is subsea 5. quently !nitiated, so that the first-order amount rack is stopped m the ,#5 digital position, Ih-le D<,I> is electrically connected to lme 120e by way of printed circuit conductors 118 and 119 due to the action of wiper blades 113-114, as previously described with respect to FIGS. 3A, SA, and SB. T~us it is evident that, when the digit~ounter (FIG. 63) IS at a count of "0," so that line D<,I> IS TRUE, and the bit-counter (FIG. 62) is simultaneously at a count of "a," so that line Ba is true, the state of output line RSS is TRUE, indicating that the low-order bit of the first-order digit is a binary "1." When the bitcounter advances to a count of "b," line RSS is rendered FALSE, thus indicating that bit "b" is a binary "0"· when the bit-counter advances to a count of "e," line is ;.e~dered TRUE, thus .indicating that bit "e" is a binary 1 ; and, when the bIt-counter advances to a count of "d," line RSS is rendered FALSE, thus indicating that bit "d" of the first-order digit is a binary "0." Therefore, RSS 3,112,394 156 155 as bits "a" and "e" of the digit each have a value of binary "I," and as bits "b" and "d" each have a value of binary "0," the differentially"set position of the first-order amount rack corresponds to binary OlOl-Le., decimal "5"which, in turn, corresponds to the assumed value of the first-order digit of the amount indexed in the accollnting machine keyboard. Therefore, it is evident that the bit and digit counters effectively operate together as a serializer which, in a sense, "scans" the differentiaLly-set positions of the ten amount racks, starting with the first-order amollnt rack and ending with the tenth-order amount rack, and essentially generates a train of impulses via line RSS, whith impulse train corresponds to the value of the amount entered into ,the accounting machine keyboard, the first impulse, or lack of an impulse, corresponding to the binary value of bit "a" of the first-order digit, and the last impulse, or lack of an impulse, corresponding to the binary value of bit "d" of the tenth-order digit of the amount. With reference back to FIG. 89B, lines RSS, CA, and EKW are each connected as an input to logical AND 1137. Consequently, as a result of line CA being rendered TRUE, a "CA(2)" word-cycle is executed, whereby the amount indexed in the accOllnting machine keyboard is sequentially stored in address-A via ,line MXW in essentially the same manner as previously described with respect to FIGS. 60, 52A, and 52B. After the word is stored in address-A, line AN is rendered FALSE, and, consequently, the state of flipflop 6080 is reversed, so that line CA is rendered FALSE, thus terminating the "CA" word-cycle operation. As previously described with respect to FIGS. 2 and 44A, when reverse key "REV" is manually depressed, indicating that the amount just indexed in the keyboard of the accounting machine is a negative number, the movable arm ofswiteh 572 is actuated thereby. With reference to FIG. 74, when the reverse key is depressed, the movable mm of switch 572 is deflected upwardly from the position shown, so that the state of line REV is rendered TRUE therebY, Therefore, as depression of the reverse key signifies that the algebraic sign of the word just stored in address-A is negative, and, as a negative word is stored in memory as its complement, the word just stored in address-A must be complemented before being stored in the selected address in memory. Thus, with reference to FIG. 89B, when line CA is thus rendered FALSE at the end of the previously-initiated "CA(2)" word-cycle, the state of flipflop 6083 is reversed, so that line CPA is rendered TRUE thereby. When liue CPA is thus rendered TRUE, a "CPA" subcommand is thereafter executed, whereby the word in address-A is complemental and its complement is stored back in address-A in exactly the same manner as previously described. When the previously-initiated "CPA" subcommand is terminated, so that line CPA is rendered FALSE, the state of flipflop 6077 is reversed, so that line AM is thereby rendered TRUE. When line AM is rendered TRUE, line TS3 is likewise rendered TRUE. Therefore, in response to lines AM and TS3 simultaneously being rendered TRUE, an "AM" word-cycle is ,thereafter executed, whereby the word stored in address-A is stored in the selected address in memory as specified by the contents of section 3 of the instmction register. It is to be noted that, had the reverse key not been depressed, the word in address-A is immediately stored in memory without being complemented when line CA is rendered FALSE. This is due to the fact that the state of flipflop 6U77 is reversed when line CA is rendered FALSE, because line (REV)' is TRUE, in this instance, indicative of non-depression of the reverse key. After the word in address-A is stored in the selected address ,in memory specified by section 3 of the instruction register, the state of flipflop 6077 i~ reversed when line AN is rendered FALSE, indicating thnt the previolls- 5 10 15 20 25 30 35 ,10 45 50 55 Iy-initiated "Al'vI" word-cycle is completed; consequently, the states of lines AM and TS3 are both rendered FALSE. As previously described with respect to FIG. 59, if the contents of sections 3 and 4 of the instruction register are of equal magnitUde, indicating that there are no other words to be indexed into the accounting machine keyboard, line 134 is rendered FALSE, and line (134)' is simultaneously rendered TRUE. However, if sections 3 and 4 are of unequal magnitude, indicating that there are additional words to be indexed into the keyboard, line 134 is rendered TRUE, and line (134)' is simultaneously rendered FALSE. Thus, with reference back to FIG. 89B, if there are no other words to be indexed into the keyboard, the state of flipflop 6107 is reversed when line AM is rendered FALSE and line STD is rendered TRUE thereby. When line STD is thus rendered TRUE, line TS5 is likewise rendered TRUE. In response to lines SID and TS5 being rendered TRUE, a "SID" subinstruction is executed, whereby the contents of seotion 5 of the instruction register is stored in the word-selecting register. However, if there are additional words to be indexed into the accounting machine keyboard, line IN4 is rendered FALSE when line AN is rendered FALSE, and, as a result, section 3 of the instruction register (FIG. 58) is incremented by a count of "1" in the same manner as previollsly described. If, before being incremented, the contents of section 3 of the instruction register is not equal to the contents of section 4 thereof, the state of flipflop 6(189 (FIG. 89A) is reversed when line AM is rendered FALSE at the end of the previously-initiated "Al\i" word-cylc1e. As a result, line KEY is again rendered TRUE, and the F-counter (FIG. 72) is again preset to "0" via line PF¢. Prior to a subsequently-initiated machine cycle when line GO is rendered TRUE, enter ..keyboard-words lamp EK is illuminated, thus providing a visual indication that another amount is to be indexed in the keyboard; thereafter, the just-described sequence of events is again repeated. It is ,to be noted that, even though line STD is rendered TRUE upon termination of the EKW subprogram, section 3 of the instruction register is incremented via line IN4 when line AM is rendered FALSE, regardless of the result of the comparison between ,the contents of sections 3 and 4 of the instruction register. It is also to be noted that, if it is desired that a plurality of words be stored in sequentially-numbered addresses in memory during the execution of a single EKW subprogram, the same motor bar, decimal-point lamp, and order-hook so!elloid are utiiized for each word entered. However, if a different motor bar, decimal-point lamp, or order-hook solenoid is desired to be utilized, a second EKW subprogram is initiated by a second EKW instruction word which specifies the desired combination thereof. 71. Detailed Description of POW Instructions 60 65 70 7G The next subprogram to be described in detail is concerned with the execution of a single POW instruction which effects the sequential printing-out of from one to one hundred words which were previously stored in sequentially numbered addresses in memory. Like the just-described EKW instruction, a POW instruction may also be considered as comprising four distinct phases or groups of subinstructions. During the first phase, the computer, in a sense, ascertains whether or not depression of a motor bar is capable of initiating a cycle of operation of the accounting machine. As previously described, prior to the machine cycle, each of the ten amount racks is physically located at "home" position, which position corresponds to a digital value of "0." Thus, the selected word in memory is read out and examined digit by digit, starting with the low-order digit thereof, to determine those digits of the word having a value of "0." Simultaneously therewith, 3,112,394 158 157 the rack-stopping solenoids corresponding to the digital positions of those digits of the word having a value of "0" are energized to prevent any movement of the associated amount racks when a machine cycle is subsequently initiated. Thereafter, the state of a particular sign memory flipflop is selectively conditioned to correspond to the algebraic sign of the word to be printed out. If the algebraic sign of the word to be printed out is negative, credit balance key CR. BAL. (FIG. 2) is effectively depressed via selective energization of credit balance solenoid CBS, as previously described with respect to FIG. 37 and also as shown in FIG. 81. When a machine cycle is subsequently initiated in order to carry out the fIrst half of a credit balance operation, the word read out from memory is subtracted from the contents of the "X" totalizer, which normally stores a word of all zeros. When the second machine cycle is subsequently initiated in order to carry out the fInal half of a credit balance operation, a total operation is taken with respect to the "X" totalizer, so that the complement of the word just read out from memory is printed in red, with a "CR" symbol to the right thereof. Due to the fact that the differentially-set positions of the ten amount racks are determined solely by the computer during the execution of a POW instruction, rather than by a totalizer or by depressed keys on the accounting machine keyboard, it is therefore necessary to automatically release the amount racks and all previously depressed amount keys when a total operation is called for during the execution of a POW instruction. Thus, in order to permit the automatic release of the amount racks and the keys prior to the initiation of a total-taking operation, rack release solenoid RRS (FIGS. 39 and 81) is selectively energized. During the second phase of the subprogram, the particular motor bar operation specified by the value of the low-order digit in section 2 of the instruction is executed in order to initiate the required machine cycle. The third phase of the POW instruction begins when the machine starts to cycle, so that the timing rack and all non-stopped amount racks simultaneously begin their travel in a "setting" direction toward the rear of the machine, those amount racks corresponding to the digital positions of the digits of the word having a value of "0" remaining in home position. Each time the timing rack is translated from a position indicative of one digital value to a position indicative of the next higher successively higher-order digital value after leaving home position, each of the digits of the word is essentially "examined" to determine whether its digital value corresponds to the digital value represented by the instantaneous position of the amount racks. If such correspondence exists, all corresponding digital-order rack-stopping solenoids are simultaneously energized and thereby arrest further movement of all corersponding amount racks. After all of the amount racks have been differentially positioned to correspond to the word just read out from memory, a normal printing operation takes place. During the final phase of a POW instruction, the contents of sections 3 and 4 of the instruction register are compared for equality to determine whether or not there are additional words to be printed out from memory. If there are additional words to be printed out, section 3 of the instruction register is incremented, and the entire sequence of events, just described, is again repeated. Otherwise, the instruction is concluded by effecting the copying into the word-selecting register the address of the next instruction word, which is located in section 5 of the instruction register. Listed below in somewhat tabular form, and also graphically illustrated by the flow diagram of FIG. 107B, is a step-by-step description of the various previously de- scribed subinstructions to which the computer is sequentially responsive in executing a "POW" instruction: 5 Step Sub Ins true· tlons Description L _____ MI-O-2 _______ Copy Into the instruction register the next Instruction word stored In memory at the address speclfled by the contents of the wordsdectlng register thereafter, II the number thus stored In section I of the In.tructlon 10 register Is "01," carry out the sublnstructlon l!.sted in Step-2 of the folloWIng POW subprogram. 2______ PF¢4-3 __ • ___ Preset the F -counter to "0"; thereafter, go to Step-3, 3______ GO-0-4 __ T____ Go to Step-! in the subprogram whenever depression of a motor bar wllllnltiste B machine 15 4______ AD-Q-o _______ cycle. Increment the diglt-eount~r; thpreafter, go to Step-fi. 5______ MJ-3-6 _______ Copy into the "J" digit-register the digit corresponding to the count In the digit counter of the word stored In memory at the address Indicated by section 3 01 the Instruction thereafter, go to Step-5. 20 6______ IFJ-27-7 ______ If re~!ster; the digtt In the F-counter Is eqUIII to the digit in the "J" dlglt·register, go to Step-7; other'."ise gO to Step-27. 7______ D-34-33 ______ If go the hlgh-{)tder digit In section 2 of the Instnle!ion register Is "0," go to Step-33; otherwise, go to Step-34. 33 _____ MB.p(l)-0-4L Depres. the upper motor bar for a touch operathereafter, go to Step-44. 34 _____ HI-36-3L ____ If tion; the high-order digit In section 2 olthe instruc00 tion re~lster Is a "I," gO to Step-3.5; otherwise, go to Step-36. 30 _____ MI34>(2)-o-4L Depress the upper motor bar for B hold operathereafter, go to Step-H. 36 _____ H2-38-3L_. __ If tion; the hlgh-{)rder digit In section 2 of the Instruc· tlon r'1l1ister Is a "2," go to Step-37; otherwise, go to tep-3B. 37. ____ MBl(I)-Q-4L Depress the middle motor bar for a touch opera· 05 tion; thereafter, go to Step- H. 38 _____ H3-40--39 ______ If the high order digit In section 2 of the instruction register Is a "3," go to Step-311; otherwise, go to Step-40, 39 _____ MB1(2)-0-44 __ Depress the middle motor bar for a hold operation; thereafter, gO to Step-H. 40 _____ II4-42-4L _____ If the high-order digit In section 2 of the Instruc70 tion register Is a "4," go to Step-4l; otherv.ise go to Step-42. 41. ____ MB2(1)-Q-4L Depress the lower motor bar for a touch opera. thereafter go to S te~4. 42 _____ H6-0-43 _______ If tlon; the hlgh-order digit In sec Ion 2 olthe instrnction regi~ter Is a "5," go to Step-43. 43 _____ MB2(2)-0-4L Depress the lower motor bar for a hold operation; thereafter, go to Step-44. 75 3,112,391 159 Step Sublnstructions 160 Description 44_ ____ Ll-4&-45 _____ _ If the low-order digit in section 2 of the imtruetion register isa 1'1," go to Sf.ep-45; othenvisc, go to Step-46. 45..___ OHl-0-48 ____ _ When printing occurs, place a comm~ between rows #5 and #6; if there is no significant divit in row. #f3 (,brougb #10, print a zero preccdill~ the comma; thereafter, go to Step-48. 46 _____ L2-48-47 _____ _ If the low-orrler dIgit III section 3 of the in,truction register is a H2,'~ go to Stcp-47; otherv;ise, gO to S tep-4S. 47_ ____ OH2-0-48 ____ _ When printing occurs, place a comma bctween rows #8 and #9; if there is no ,ignificant digit in rows #9, or #10, print a zero preceding the comma; thereatter, go to Step-4S. _____ PCT-0-49 ____ _ When the amount racks arc traveling in a "setting" direction, go to Step-49 each timo the timing rack ch!mges digital position, and also upon engagement of the printing-liner. 49 _____ AF-{)-SQ.. ____ _ Increment the F-connter; thereafter, go to Step-50_ 50 _____ F9-61-75 _____ _ II the F -counter is at a count of "9," go to Step-75; otherwise, go to Step-5t. 51. ____ AD(I)-{)-52 __ _ Increment the digit-counter; thereafter, go to Step-52. 52 _____ l\iJ-3-53 _____ _ Copy into tile ".T" diglt-regi,ter the digit corresponding to the count in tbe di~it counter of tbe word stored in memory at the address specified by section 3 of the instruction register; thereafter, go to Step-53. 53 _____ IFJ-74-54 _____ If the digit in the F-rountcr i, e~ual to the digit in the "J" dIgit-register, go to Step-54; otherwise, gO to to Step-74. 54 _____ D-5&-55 ______ I! the digit-counter is at a count of "0," go to Step-55; otherwise, go to Step-56. 55 _____ RA-{)-74 _____ Energize the first-order rack-stopping solenoid; go to Step-74. thereafter, 56 _____ DI-58-57 ______ If the digit-counter is at a count of "1," go to Step-57; otherwise, go to Ste]l-5H. 57 _____ RAI-0-74 _____ Energize the second-orucr rack-stopping solenoid; thereafter, go to Step-74. 58 _____ D2-50-59______ I! the digit-counter is at a count of "2," go to Step-59; otherv.;se, go to Step-50. 59 _____ RA2-0-74 _____ Energize the third-order rack-stopping solenoid; thereafter, gO to Step-74. 60 _____ D3-62-DL ____ If the digit-counter is at a count of "3," gO to Step-61; otherwise, go to Step-62. 61. ____ RA3-0-74 _____ Energize the fourth-order rac.k-stopping solenoid; thereafter, 62 _____ D4-64-63______ I! the digit-countergoIstoatStep-74. a count of "4," go to Stcp-63; otherwise, go to Step-64. 63 _____ RA4-0-74 _____ Energize the fifth-order rack-stopping solenoid; go to Step-H. 64 _____ D5-6&-5S______ It tbereafter, the digit-counter is at a COllnt of "5," go to S tep-6ii: othorwise, go to Step-uO. 65 _____ RA5-0-74 _____ Energize the sixth-order rack-stopping solenoid; thereafter, go to Step-74. 66 _____ D6-68-6L ____ I! the digit-counter Is at a count of "0," go to Step-67; otherwise, go to Step-fiS. 61- ____ RA6-0-74 _____ Energize the seventh-order rack stopping solenoid; thereafter, go to Step-74. 68 _____ D7-70-6L ____ It the digit-counter is at a count or "7," go to Step-59: otherwise, go to Step-70. 69 _____ RA 7..()-74 _____ EnergIze the cighth-order rack-stopping solenoid; thereafter, go to Step-74. 70.. ___ D8-72-7L ____ If the digit-counter is at a count of "8," go to Step-71; otherwise, go to 8tep-72. 71.- ___ RAB-O-74 _____ Energize the ninth-order rack-stopping solenoid; therearter, go to 8tep-74. 72 _____ D9-0-73_______ If the digit-counter is Ilt a count of "9," go to Step-73; otherwIse, go to Step-74. 73 _____ RA9-0-H _____ Energize the tenth-order rack-stopping solenoid; thereafter, go to Step-74. 74.. ___ DlhSl-4L ____ If the digit-counter is at a count of "9," go to Step-48; otherwise, go to Step-5l. 75 _____ CA(2)-{)..76 ____ Copy into address-A tbe word collecUyely indicated by the condition of the rack read- f) 1() 4~ 76 _____ RSB-3-77 _____ 71.- ___ OBN(1)-80-78_ 7L ___ RPB-O-7L ___ 79 _____ OBN(3)-O-L_ 80 _____ I34-81-83 ______ 81.. ___ IN4-(}-82 ______ 82 _____ OBM(3)-(}-2 __ 83 _____ STD-5-o ______ 15 20 2;) 30 :l:i ,j 0 45 riD st1'~t~~~'~;t\~ees~~~dr~~~~t~l~I~o~;I'W';)?' at the 5:) address specified by section 3 of tbe instruction register from the word In address-A and store the remainder in addrcss-A: thereafter, go to Step-77. If the state of line OBN is TRUE, go to Step78; otherwise, go to Step-SO. Upon depressIon of the resume-progr[lIl1 bar, GO go to Step-7g. Preset line OnN to a FALSE stat~; tbereafter, go to 8tep-2. If the addresses in memory specified by secUons 3 and 4 of the instruction register are equal, go to Step-S3; otllerwise, go to Step-8!. Increment section 3 of tbe instruction register; C.'5 thereafter, go to Step-82. Preset line OUM to a FALSE state; thereafter, go to Step-2. Copy the contents of section 5 of the instruction register into the word-selecting register. 70 Upon completion of the execution of the previously initiated "MI" word-cycle, during whioh time the next instruction word is read out from memory and stored in the instruction register, if the two-decimal-digit number stored in section 1 thereof corresponds to the code des- j5 ignation for a POW instruction-i.e" "01 "-the state of line POW is rendered TRUE in a manner previously described with respect to FIG, 56, and, consequently, a "print-out-words" instruction is thereafter executed in the following manner: With reference to FIGS. 90A through 90C, there is logically illustrated therein a composite circuit diagram of particular portions of the computer circuitry utilized in executing a POW instruction. As shown in FIG, 90A, at TIME--l after the initiation of a "MI" wordcycle, the states of f1ipflops 6095 and 6096 are simultaneously reversed, if not already in reversal states, so that lines (OBM)' and (OBN)' are respectively rendered TRUE thereby. As shown in FIG. 90B, the state of line HF¢ is rendered FALSE upon completion of the previously-initiated "MI" word-cycle when the state of line AN is rendered FALSE; consequently, the F-counter (FIG. 72) is preset to "0." It is assumed that, upon initiation of the POW instruction,able arm 497 (FIG. 38) of the accounting machine is in the non-deflected position, as shown, and, consequently, the contacts of switch 496 (FIGS_ 38 and 82) are closed, thus indicating that the motor bars are not disabled; that the carriage of the accounting machine is not tabulating over a carriage stop as indicated by a closure of the contacts of switch 516 (FIGS, 43 and 82); that the machine is in home position, so that the contacts of switch 528 (FIGS. 41 and 82) are closed; and that a papcr-tape-punching operation is not to be initiated as indicated by a closure of contacts SC41-3 (FIG_ 82) of switch SC41 (FIG. 13). The just-mentioned conditions having been satisfied, the state of line GO (FIG. 82) is rendered TRUE, indicating that a cycle of operation of the accounting machine is permited to be initiated. Thus, with reference back to FIG. 90A, all of the inputs to logical AND 1408 are simultaneously TRUE just prior to tbe completion of the previously-initiated "MI" word-cycle. Consequently, when line AN is rendered FALSE upon completion of the previously-initiated "Ml" word-cycle, the state of flipflop 6066 is reversed, so that line MJ is thereby rendered TRUE. With reference to FJG. 90B, line TS3 is rendered TRUE at the beginning of the instruction when line POW j,s rendered TRUE. Consequently, in response to lines 1'\1J and TS3 being rendered TRUE, a "1'\11" ,word-cycle is thereafter executed, whereby the word stored in memory at the address specified by the contents of section 3 of the instruction register is read out digit by digit, starting with the low-order digit thereof, and stored digit by digit in the "I" digit-register (FIG, 71). At TIME--3 after the initiation of a "MI" word-cycle, the state of flipflop 6118 (FIG. 90A) is reversed, so that line WOA is thereby rendered TRUE. After each of the digits of the word is read out from memory via a "MJ" word-cycle and sequentially stored in the "I" digit-register, the contents of the F-counter and the "I" digit-register are compared for equality in a manner previously described with respect to FIG. 72, However, due to the f.act that the F-counter is initially preset to "0," each digit stored in the "J" digit-register is essentially examined in order to determine whether its value is "0," If the digit stored in the "I" digit-register has a value of "0" when the "compare for equality" is made with respect to the contents of the IF-counter and the "I" digit-register, the state of line (IFJ)' is rendered TR UE; otherwise, the state of line (lFI) , remains FALSE. With reference now to FIG. 9OC, after the state of line WOA is rendered TRUE at the beginning of the "MJ" word-cycle, line EVG experiences 'a TRUE-toFALSE reversal of state each time the "J" digit-register is preset to "0" via a TRUE-to-FALSE reversal of state of line PI1> if the Ili,git presently stored in the "J" digitregister has a vallie of "0," as indicated by a TRUE state 3,112,394 161 162 of line (IFJ)'. Consequently, when the digit-counter is at a count of "1," as indicated by a TRUE state of line 01, the state of flipflop 6108 is reversed, ,so that line (RA¢)' is rendered FALSE if the value of the first-order digit of the word just read from memory is zero. When the digit-counter is subceql!;;;ntly incremented to a count of "2," line (RAl)' is rendered FALSE by a reversal of state of flipflop 6HI9 if the value of the second-order digit of the ,voru is also zero, and so on, until line (RAS)' is ['endered FALSE by a ,reversal of state of flipflop 6116 if the vulue of [he ninth-order digit of the word just read out from memory is zero. If the value of the tenth-order digit is zero, as indicated by a TRUE state of line (IF])', the state of flipfiop6117 is reversed, and line (RA9)' is rendered FALSE 'when line AN is rendered FALSE, indicating completion of the "MJ" word-cycle. It is seen, therefore, that the states of selected ones of lines (RA¢)' through (RA9)', corresponding to the digital positions of those digits of the word having a value of zero, are successively rendered FALSE by corresponding reversal of states of fiipfiops 6108 through 6117, respectively. Thus, after the digit-ceunter 're·aches a count of "9," as indicated by a FALSE state of line (D9) " the outputs from corresponding ones of logical ORS 3497 through 3506 are rendered FALSE "",hen line PCT is subsequently rendered FALSE. Consequently, tbose ones of rack-stopping solenoids RA¢L through RA9L corresponding to those digital positions of the digils of the 'word having a value of zero are simultaneously energized and thereafter prevent, in a manner previously described, any movement of the associated amount racks when a machine cycle is subsequently initiated. In other words, after the first "MJ" word-cycle is terminated, all amount racks corresponding to the digital positions of those digits of the word having a value of zero are locked ,in home position prior to the initiation of a machine cycle. As previously stated with respect to FIG. 3A, in initiating an addition or a ,~ubtraction q'cle of operation of the accounting machine, depression of the amount keys causes zero stop pawls 46 to be rocked counter-clockwise and thereby release amollDt racks 49 for rearward movement when a machine cycle is subsequently initiated. In a total-taking operation, however, no amount keys are depressed. Thus, additional means are utilized in a manner previously described with respect to FIGS. 39 and 40. whereby the zero stop pawls are rocked counterclockwise, and, additionally, all accidentally-depressed amount keys arc released at the beginning of the machine cycle. Consequently, with reference to FIG. 90B, rackrelease solenoid RRS is energized when the state of line WOA is rendered TRUE, and thereby allO'.vs the justmentioned additional means to function in the manner previously described. "Vi!h reference to pra. 90A, if the lligh-ordcr digit of the word just read out from memory and stored in the "J" digit-register is a "9," indic~ting the complement of a negative number, the state of line (19)' is rendcr~d FALSE. Thus, at TIME-3 during the last hit time period of the "MJ" word-cycle, when the st:lte of line EG is reversed from TRUE to FALSE, the st~tc of flip flop 6~95 remains unchanged, so that line (OBM)' remains TRUE. However, if the al[:ebraic sign of the word just read out from memory is positive, so thut line (J!:)' is TR UE, the state of line (OBM)' is rendered FALSE at TH',IE-3 by a change of stat.! of flipflop 61.1%. Consequently, line (OBM)', in the bter instc,nce, docs not remain TRUE for a time period sufficient to allmv credit balance solenoid CBS (FIG. 9GB) to be re,ponsive thereto. However, if the :2lgebraic Si;:'H of the word jmt read out from memory is negative, so that line (OE1\'!)', remains TRUE, credit balance solenoid CBS is energized for a time period sufficient for norm:!! operation thereof. As previously describcu with respect to FIG. 37, as a result of credit balance solenoid CBS being energized, the amount collectively indicated l~y the differcntiaily-set positions of the amount racks is subtracted, during the first machine cycle, from the "X" totalizer, which normally norcs a word of at! zeros. Durin;:; the second machine cv)c, a total operation is executed with respect to the "X" totalizer, so that the complement of the word just re~;d out from memory is rrinted in red, with n "CR" symbol disposed to the right thereof. As shown in FIG. 9GB, when line WOA is rendered TR.UE ~J tl];: beginning of t;lC "MY' word-cycle, upper motor bar solenoid l'IiB¢> is ener6ized if the high-order digit in section 2 of the instruction register is a "0" or a "1"; middle motor bar solenoid j\,fBl is ellc)rgized if the high-order digit in section 2 is either a "2" or a "3"; ;;nd lower motor bar solenoid MB2 is energized if the high-order digit is either a "4" or a "5". However, approximately 130 milliseconds after the preselected motor bar is automatically depressed via energization of the corresponding motor bar solenoid, all amount racKs not locked in home position are simultaneously translated in a settiug direction toward the rear of the machine. As previOllsly described with respect to FIG. 72 and with respect to the mode of operation of an EKW subprogram, the state of output line peT is rendered TRUE at each tr:mslational position of the timing rack corn:sponding to a digital value mJd is rendered FALSE during the time the timing rack is being translated from one position to a successively hi[:her-order digital value po,ition. Therefore, with reference b~c~ to FIG. 90A, when the timing and amount racks fir~t begin their translational movement toward the rear of the m~chine. the ~t:ltc of line (peT)' is reversed from TRUE to FALSE, and, as a result, the state of flipflop GOllS is reversed, EO th:\t line JHR is thereby rendered TRUE. At the following Tll'I'lE1, the state of flip-flop 6088 is again reversed, and line JHR is thereby rendered FALSE. As shown in FIG. 90B, e3ch til:1eline JHR experiences a TRUE-to-FALSE reversal of state, the state line AF likc'Nise exp::riences a TRUE-to-FALSE reversal of state. Thus, the F-countcr (FiG. 72) is incremented by a CGunt of ''1'' e[:c~ time the racks arc simultaneously translated from one position tLJ a successively higher-ordcr digital valued position. With reference to FIG. 9(}A, each (ime the st:)te of line JHR reverses from TRUE to FALSE, the stale of flipflop 6\)66 is reversed, so that line MJ is thereby rendered TRUE; consequently, a "1\'11" word-cycle is t!let"eby iniliated 'at the following Tl ME-l afkr each time line PCT is rendered TRUE while the racks are traveling in a setting direction. As just described, during the execution of a "MJ" wcrd-eycie, all of the di£;its of the word stored in memory at the address specified by the contents of section 3 of tbe ir,struction register are sequentially read out, stored in the ''1'' digit-register, and compared with the di'gitai COlmt of the F-counter. Thus, during t';e time the amount racks are being simultaneously translated from home position to their :;:; 1 digital posilions, the state of line JHR is reversed from Tl-~UE to FALSE, the F-counter is advan,:ed to a cOllnt of "J ," and simult:mcously ther~with, a "MJ" word-cycle is initiated. Consequently, each dieit of the word read out from memory is eff~ctively ex~mined to determine whether its value is "J." Thereafter, those ones of rack~toppinG solenoids RA¢L throuf:h RA9L (FIG. 4) correspending [0 the digital positions of those digits of the word haviag a value of "1" are sirrm1tr,neously energi:>:ed to arrcst movement of and thus differentially position the corre~pond;l1g amount racks at the :#: I digital valued pOoition, thereof in tbe same m~nner as just described. The above sequence of events is sequentially repe:lted Entil all of the ten amollnt racks are differentially set <1t those rligitd valued positions collectively representative of the word just read from memory. It is to be De (ed, ho'y,:v~r, th:Jt a "~,11"\'/0rd-cyc1e is also initi~t"d whm the F-coun!er rcaches a count of "9" enn though 5 10 15 20 25 30 35 ·10 45 50 55 60 65 70 75 3,112,394 163 ali amount rac:';s net previously stopped ue ;llltcmn(:calJy ~topp;::d ~t their high-order digital valued positions. HolYever, wiLh refcrer,cc 10 FIG. 90n, when the F-counter rea~hcs a count of "8," as h:dknted by a T~UE state of line Fll, order-hook solenoid OB 1 is energized if the low- 5 order digit in section 2 of the instruction register i3 a "1," \Vhere3s order-hook solenoid OH2 is energized if the loworder digit in section 2 is a "2." l\S previously described wilh respect to the EKW subprogram, when order-hook solenoid OR1 is energized, all order-hooks from the third 10 to and including the eighth ones are unlatched from their respective type sectors. However, when order-hook solenoid OHZ is energized, all order-hooks from the third to and including the eleventh ores are unlatched from their respective type sectors. As previously described with re- Iii spect to FIGS. 3A, 41, and 72, when printing aligner bars 72 engage the proper tooth of corresponding ones of the members 53 in order to precisely align each of the type sectors 67 prior to a printing operation, the contacts of switch 550 are closed, so that the slate of flipflops 6071 20 and 6;)72 are reversed, so that line (PCT)' is rendered FALSE thereby. As a result of line (PCT)' thus being rendered FALSE, the state of flipflop 6088 (FIG. 90A) is again reversed, so that line JHR is again rendered TRUE. Thus, 2:; at the following TU,1E-l when line JHR is rendered FALSE, line AF (FIG. 90B) experiences a TRUE-toFALSE reversal of state to eifect the advancement of the F-counter from a count of "8" to a count of "9." With reference to FIG. 90S, when the F-counter is in- 30 crementcd from a count of "8" to a count of "9," any previously-energized order-hook solenoid (OHI-OH2) is de-energized. With reference back to FIG. 90A, when line AN is rendered FALSE after the F-counter reaches a count of "9," the state of flipflop 6,118 is reversed,. so 3,; that line WOA is thereby rendered FALSE. With reference now to FIGS. 90B and 90C, as a result of line WOA thus being rendered FALSE, all previously-energized motor bar, rack-release, credit-balance, and rackstopping solenoids are de-energized and thus rendered ,,1}) ineffective. With reference to FIG. 90A, when the F-counter reaches a count of "9," as indicated by line F9 b~ing rendered TRUE, the state of flipflop 60S0 is reversed, and line CA is thereby rendered TRUE upon completion 4.3 of the following "MJ" word-cycle, as indicated by line MJ being rendered FALSE. In response to line CA thus being rendered TRUE, a "CA" word-cycle is thereafter executed, whereby the word collectively indicated by the differentially-set positions of the amount racks is read 50 out, in the manner previously described with respect to ,he EKW subprogram, and thereafter stored in address-A via line M),,'W (FIG. 90B). Upon completion of the previously-initiated "CA" word-cycle, as indicated by line CA being rendered FALSE, the state of !Iipfiop 611)0 i);"j (FIG. 90A) is reversed, so that line RSB is thereby rendered TRUE. In response to line RSB thus being rendered TRUE, a "RSB" subcommand is thereafter executed, whereby the word initially read out from the address in memory as specified by the contents of sec- GO tion 3 of the instruction register is subtracted digit by digit from the word just storecl in address-A. If cach digit of the word just read out from memory is equal in magnitude to the corresponding cligit of the word stored in address-A, line ZNO rcmains FALSE, and, as a re- Ii;) suIt, the stelte of flipflop 60':6 remains unchan,9cd, so that line (OBN)' remains TRUE. Hov/ever, if a digit of the word in address-A is not equal to the corresponding digit of the corresponding word in memory, indicating that the vv'Ord just printed out does not correspond to 70 the word just read out from memory, line ZNO experiences a TRUE-to-FALSE reversal of state, thereby causing the state of flipflop 60,96 to be reversed, so that line (ORN)' is thereby rendered FALSE, thus indicating that a printing error has occurred. When the state of 7ij 164 line (OBN)' is thus reversed from TRUE to FALSE, the state of flipflop 6107 is not revcrsed by logical AND 1716 to indicate completion of the "POW" subpro:;ram, as is normally the casco As previously described with respect to FlG. 59, if the contents of section 3 of the instruction register is equal to the contents of section 4 thereof, indic3ting that there are no other words to be rri:1~ed out from memory, the state of line (I34)' is rendered TRUE. Line (134)" however, is rendered FALSE if there <:re additional words to be pric:tcd out. Therefore, with reference bnek to FIG. 90A, if the word just printed out is cqual in magnitude to thc word just read out from memory, as indicated by a TRUE state of line (OBN)', and if there are no olher words 10 be printed out, as indicflted by a TRUE state of line (!34)', the st~te of flipflop 6107 is reversed by the output of logical AND 1716 when line AN experiences a TP..UEto-FALSE reversal of state upon completion of the previously-initiated "RSB" subcommand; consequently, line STD is thereby rendered TRUE, thus indicating the end of the POW subprogram. Vlhen line STD is thus rendered TRUE, line TS5 (FIG. 90B) is likewise rendered TRUE. Thus, as previously described with resrect to the EKW subprogram, in response to lines STD and TS5 being rendered TRUE, a "STD" subinstruction is thereafter executed, whereby the contents of section 5 of the instruction register is stored in the word-selecting register. However, if there are fldditional words to be printed out, line IN.~ (FIG. 90B) is rendered FALSE when line AN is rendered FALSE upon completion of the previously initiated "RSG" subcommand. Consequently, section 3 of the instruction register is incremenled, and thc same "PO\V" subprogram is ag~in subsequeGtJy executed in the same manner as jllst described. It is to be notec1, however, that, even thmlgh line STD is rendered TRUE, indicating the end of the "POW" subprogr<:m, ~ectiC'n 3 of the instruction register is, ncvertheiess, incrementcci via line IN4 regardJess of the result of the comparison b;:;tween the contents of sections 3 and 4 of the instruction register. It is also to be noted that, if a plurality of words stored in sequentially-numbered addresses in memory are to be sequentially printed out during the exeeu .. tion of a single "POW" subprogram, the same motor bar and order-hook solenoids are utilized for ench word printed out. However, if a different motor bar or order hook is desired to be utilized, a second "POW" instruction is to be initiated, which specifies the desired combination thereof. n. Detailed Description of ROC Instmction Before describing the mode of operation executed by the computer in carrying out a "record-on-card" stillprogram, a description will first be given with re,'!Ect ii) the particular ledger card \vhich is utilizcd in a novel manner by the present computer in accordance with the present invention. As previously described with respect to FIG. 8SA, the Iedf'er cQrds utilized by the present ccmp:ltcr are capable of havini; recorded thereon historical, current, and fixed ,hta in both machine-readabie and human-readable languages and, consequently, are readily adc\ptable to be utilized in the mechanization of record-keeping and accounting systems and proccdures. As illustrated in FIG. 8gA, e--O-IL ____ Prwtt,':, nw ,I ~;::., (1igit-Ttlgi::;kr to "0"; tlllTt'dh r, go to :::lWp-l1. 11 _____ MK-4-12 ______ Cory intn thu I ~ K" di~rif.-n'gi>ll'r tlll' digit" g------ indielltcd lIy 45 12 _____ n _____ 14 _____ 50 th~' C(H~l1t oj tlH' d~~it-\-,.,"ll:Htl'r, (;f llw \' (Ir:l "tDfl'(1 ill Illt'ItHirV :~! ,!w iL,ldn'.';s :;'l;(,l.'i!h'~l by llw cOlltl'nLc; uf-'-;('(':Lm -i (If Ilto in.~!'ruc'[ioil n'gi:;ter; thl'n':1f!,('/', ~1J tl) ~;:~'p~l.:1, E4-14-13 ______ If (he' digit E1t I!yti in t]H'" K,j digi~ rl'gistrf is :], j~O'", go 10 t;tel'~l:·~; ()thcr\"j"'l" g-o to St('n~l L digit~c'{)Ulltn i'-~ ('t'iWt of"O", go to :~tep-14; Othl'1" 1.,(', !~O RL(\jJ-fl. KEY-0-15 ____ \Yh,:ll tlw '2{Hl l'P~ c',wk . :;'.\';,1 . fl'ulcrt'(l D-O-H _______ If the 1 , 15 _____ [)9-HHS ______ 10 _____ ROS-O-17 _____ 17 _____ 11::-18-21 ______ li':\'L~r~, Sll t<) :::;10p~15, If 11"lt, d.igit-r'f1Tln~N is ;11 a f.':nml of 8lt'p-~~; oti!crwic;c, g-u to tJt('j':-l~L ~111 °tl", ?O to l'll tho It'rlg~'r (:ird; thno::aft,'r, ~" to 8/('1'-17. II tl'.e di~it ~t\)rl'd in the" K" digit. rr'gi 'f-:'l i-i a "0", ~~I) to Step~~:':; oql(\]"ll i~\', gn lil ;:;~vp-l:-;. 18 _____ SE:,-(}-IL ____ :nl'C'1jru 011' c::ynthronizing dnvk ~l~!l~1.1 itl[1 1rn:a1LI11 on nll~ lc'dgr'r card, ~lnd, cilJlUlt:'Ln(':~'u.'::y Ht'-c:1-l'1i ('ild-o[-\".llHl th' i'{,wi;h, n't' '1"11 55 :::t!)l'l'(l in ~;O 19 _____ f.l) nw rill "K" Co!) iwt Hl'JIl nw kd:'::i'J' ': !:d ILl' di[!it djgH-n'gL~t('r; 11lL']"I':~[jl'r, ::~lt'p-LlI, D -20-22-- ____ If tll~' I:i~ii·':' U'lt.Ct' i.~ a rOUitl oI 1'0", go to St[T-22; O~hlT\\ i:'t" go ~_;tt;p-:.!D, 20 _____ AD(2Hl-2L __ Dt'tI'\'W('llt tlw digit·counter; tlwJ'c:liter, ~o to Step-:!l. 21 _____ MK-4-1L ____ OliPY thp rligit in~o thr K" digit. rrr-i",tn as indicnied hy tll~' (1)UIlL of tilL' di~dt~(':)UIJt~'j', f1"}111 UI<-' 1\",lrd ~Ltm'd ill Jll~·li'.(H'Y a~ tlw :lIJ. drr:;~ :~il('('Hll·.l by !lll' l"ordnns l'f ~~'('tioIl 4 (If the im,t.rnc'Uon n'gi:;ll'T; tlwrcaft(·r, go to .j 60 22 _____ 134-2324 ______ If S' op-1~' l'he 8.fi~l·rf'·;~('s ill s{';ctions 3 :l1l(i4 0f n1(' imltruc.. rl'~i~ter nro G'lual, go t.o .st"l.J~~l; \l.'iS(', ro to Stcp-23. Dcercln('llt the C'OT'Ltrnts nf ::N"'i~'H 4. lion 65 23 _____ , DE2-0-9 ______ 24 _____ LK-o -25 ______ in,;troCllrm ()th,'f~ rq~h(t'r; t.lll'rf\~lrrl·r. Go to 8tep-:2S LlfLrT th(.' It'rJgr.'J' cnnlrl1c(('ly t'jcC'teu from ~he chine c(lrrin;:~p. 25 _____ STD-5-· ______ Copy the ('on:ent::; nf tion H'gistcr into thl~ itl,~truc~ fl'~istl'r. 70 With reference to FIG. 76, the st~te of flipflop 6692 is reversed upon completion of the previously-initiated subprogram, due to a TRUE-to-FALSE reversal of state of line AN. As previously described, when the state 75 of flipflop 6092 is reversed, so that line Ml is rendered 3,112,394 167 TrJ':J~:, a "i\lf' ','~'ord"cyc!c i:::; inHiatcd v,rbereby the \vord "tared in memory at the address specified by the con!;:;,,(s of !h-~ word·selecting register is read out and stored i.1 the i:::strllctiom register. Th'~reafler, if the two-decim«l-di,git number stored in section 1 of the instruction r;;[;i::;tcr corrc~pondo; to the code designation for a "ROC" instruction-i.e., "03"-I11e statc of line ROC (FIG. 56) is rendered TRUE. As a result, a "record-on-card" subp[ogr~~m is tbp[e~.ftcr cxecuted in the following manner: It is first assu!~ed that, upon initiation of the "ROC" mcprogram, a ledeer c:ll'd is positioned in (he accounting !1'~lchine carri~gc, the posting operation on the celrd is completed, and it is desired to magnetically record linefine! information in addition to the last line of posting on :11:: magnetic strip thereDf while the card is being ejected from the machine. With reference to FfG. 81, it is further assumed that the "blc arm of (he aCCOU;lling machine is in the non-dellectcd position, so th:1t the contacts of switch 496 arc closed, thus indicating that the motor bars are not disableu; that the carriag·~ of the machine is not tJbui&tlng over a carriage stop w that the contacts of s\vitch 510 are closed; th:!t the machine is in home position so that the contacts of switch 528 are closed; and that a PGPcr-tape-punching operation is not to be initiated, as indicated by a closure of switch contacts SC41-3_ The jus',-mentioned assumptions being satisfied, line GO is rendered TRUE, thus indicating that the accounting machine is ready for a cycle of operation thereof to be initiated. As it is aS3umed that the machine carriage is in home pc-silion, the contacts of switch 579 are closed, so that line He is rendered TRUE lhereby_ Also, as the carriage of the machine is now closed, the movable arm of switch 333 is in the position shown, so that the state of line CD)' is TRUE. In addition, when line ROC is initially rendered TRUE, lir;es REC and i are likewise rendered TRUE and remain TRUE for substantially the entire timc duraticn of the execution of the "ROC" subprogram. Consequently, when line i is initially rendered TRUE, the states of all of the inputs to logical AND 1767 are, for the first time, simultaneously TRUE, and, as a result, solenoid Yis energized thereby. As previously described with respect to FIG_ 38, whcn solenoid Y is energized, carriage throat shaft 453 is rotated counter-clockwis~ thereby to effect the tripping of the carriage throat clutch, not shown, which allows the carriage to be opened by the power shaft of the machine. During the carriage-opcning operation, the front feed chute is tilted forward to the position shown in FIG_ 18, so that compression rolls 296 are positioned in close proximity to the card-handling platen 241, with the ledger card disposed therebetween. In addition, after the carriage is opcned, the movable arm of the switch 333 (FIG_ 82) is deflected downwardly, as viewed, and thereby renders li:"!e D TRUE and line (D)' FALSE. When line (D), is thus rcndered FALSE, solenoid Y is de-energized thereby. As previously described, when the front feed chute is in the position shown in FIG. 18 and the compression rolls 2% are 2.dj3CC11t to, but not latched against, the cnrd-drive platen 241, the brushes 336 ar;d N are electrically connected together by the commut:ltor bar 342, as shmvn in FlG. 28B. However, when the paper guide motor is energized, the cam 301 (FIG. 19) is rotated counter-clockwise to the position shown, to complete the latching operation in a manner previously described. \Vllen the latching operation is completed, so that the ledger cnrd is secured between the compression rolls 296 and the platen 241, the commutator bar 342 will have been rotated clockwise to the position shown in FIG. 28/\. As a result, the brushes E and 339 are electrically connected together by the 'commutator bar 342_ As diagrammatically illustrated in FIG. 83, the brushes 336 and 339 function in essentially the same manner as the movable aEn of a ~ingle"pole double-throw s\1i·itch. 168 TIll'S, prior to tl:e btching operati')n, line E is substantially at 1;rollnd polential, and the polentl:d on line N is ~:llbstantially CCjual to the negative potentia! applied to brushes 336--339. Therefore, after carriage-opening ;" solenoid Y (FlG. 82) is de-energized by line (D)' being rendered FALSE and line D simultaneously being rendered J'RUE, paper-guide relay solenoid PGR (FIG. 83) is energized by gate 1777. Energization of relay solenoid PGR initiates the closure of normally-open contacts HI PGR-1, PGR-2, and PGR-5, and simultaneously initiates tb opening of normally-closed contacts PGR-3 aad PGR-4. As shown, an oDenine> of contacts PGR-3 and PGR-4 and a closure 'of cO~ltacts PGR-l and PGR-2 cz:use a reversal of subsequently-applied 1;;; ·current flow through the armature of paper guide motor PGfv!, which is of the permanent magnet type, and thereby cause a rcversnl of subsequent rotation thereof. A closure of contacts PCP'.-5, of course, causes arnlature current to flow lhrollgil paper-guide molor PGivL There~o fore, when the paper guide relay is energized, armature current is applied to the paper-guide motor, so that its armature is rotated in a dircction to effect the latching of the compression rolls 2% against the card-drive platen 241, as illustrateu in FIG. 19. After the latching operation is completed, so that the 25 commutator 340 is rotated by the paper-guide motor to (he po:;ilion shown in HG. 18A, Jin~ E (FIG. 83) is rendered l~~.L-\L.sE (llid 1hcn;by C~ltlS~S the papcr-r;t;ide motor to be: dc-energized by effecting a de-energization 30 cf paperguide relay PUR, and thus initiating the return of the relay CO!1tncts thereof to their normal conditions as shmvn. In addition, with reference to FIG. 17, a'fter the latching opemtion is completed, the radiant energy from the light source 373 is reflected from the ledger eard 35 back onto the sensitive areas of photocells PCB and PCC and thereby energize both. Consequently, with reference back to FIG. 83, when photocells PCB and pec me energized, lines 13 and C are respectively rendered TRUE thereby in the manner previou,ly described. tlf) When line E is rendered FALSE, due to the fact that the paper guide is now in a latched condition, lines (E)' and N are, of course, both rendered TRUE. As shown in FIG. 82, when line (E)' is rendered TRUE, energization of solenoid X is effected by gate 43 1769. As previously described with respect to FIGS. 16 and .17, energization of solenoid X allows subsequent rotatlOn of the square shaft 283 and tbereby -allows the lower compression rolls 288 to be disengaged from the platen 71. As also previously described with respect to [;J FIG. 19, when the square shaft 283 is rotated counterclockwise, as viewed, to cause the lower compression rolls to be disengaged from the accounting machine platen, the contacts of the switch 545 are operated thereby_ Therefore, with reference back to FIG. 82, after the [;.) lower compression roll disengagement operation is completed, the movable arm of switch 545 is deflected downvl8rdly, as vicv/cu. and thus causes the ~!ate of line G to thereafter be TRUE. Simultaneously therewith line (G)' is rendered FALSE and thereby causes sol~noid Cil X to be dc-energized_ When line G is thus rendered 1:RUE, card drive motor CDM is caused to be energ"iZed by gate 1770. As a result, the ledger card is driven toward the rear of the machine and back into the chute 291 by the platen 241, in the manner previously deG;:; scribed with respect to FIGS. 17 through 19_ As previollsly described with respect to that portion of the preceding description relating to the format of a "ROC" instruction word, the numeral "0" in the loworder digital position of section 2 thereof causes a " rec70 ord single linc fmd information" operation to subsequently be initiated; the numeral "1" in the low-order digital position of seclion 2 thereof causes a "record no lincfind information operation to subsequently be initiated; and the numeral "2" in the low-Ol"der digital por:l ~;iion of section 2 thereof causes a "record multiple line- 3,112,394 169 170 find information" opemtion to subsequently be initiated. A~ previously described with respect to FIG. 57, if the value of the digit stored in the iO'.v-ordcr digital position of section 2 of the instruction register is a "0," a "1," or a "2," the slate of one of Jines L¢ through L2 is respectively rendered TRUE. "'lith refercnce now to FIG. 85, if it is assumed that single linefind information i; desired to be recorded, as indicated by a TRUE state of line 1.1>, lines Ll and L2, of cou:-se, being FALSE, the reference input to flipflop 6140 is reversed frOl11 TKUE to FALSE when line G is rendered TRUE in the manner just described. Consequently, the state of llipflop 6140 is reversed, so that the upper end, as vie,ved, of the winding of linefind head 346 is rendered TRUE. Simultaneously therewith, the output of gate 18{)O is rendered TRUE, so thut the center tap of th~ winding of lhe linefind heud 346 is thereby rendered FALSE. As a result, current is caused to flow between the center tap and the upper end of the winding of linefind heGd 346 in such a direction as to magnetize the linefind channel portion of the magnetic strip of the ledgcr card in the opposite direction to the pre-magnetized direction. However, approximately ten to forly milliseconds later, the state of flipflop 6140 reverts back to its original condition, so that the lower end of the winding of linefind head 3~6 is nGW rcndered TRUE instead of its upper end, as before. Consequently, current is caused to flow between the cei1ter tap and the lower end of the linefind windin3 in sllch a direction as to magnetize the remaining portion of the linefind channel in the same direction as the pre-magnetized direction, thereby simultaneously ewsing all previou:;ly-rccorded line find information. It is now assumed that multiple line find information is desired to be recorded, so that line L2 is initially rendered TRUE instead of line L¢. Thus, when the state of J1ipflop 6140 is iniliaily reversed in the manner just dc;sc;-ibed, the slate of fiipflop 6141 is likewise reversed simultaneously therewith. Thus, again, the states of the upper end and ,center tap of the winding of linefind head 31.6 are rendered TRUE and FALSE, respectively, as before described. Consequently, the linefind channel is, aguin, first magnetized in the opposite pre-magnetized dircction by the first reversal of state of tlipflop 6140 and, thereafier, is magnetized in the same direction as the pren1ag,teti-:;:~J Ji~'c:.:.tion by a s~cond revc:5·~ ..il of st~He of flipl10p Ii 1 ,H) , as before dcscfib·cd. However, approximately sixty milliseconds after the state of flipflop 6141 is initially reversed, its state reverts back to its initial condition, so that the state of (he center tap of linefind head 346 is rendered TRUE thereby, thus essentially deenergizing the line-find head and thereby preventing further erasure of previously-recorcleu line find information, all of which is diagrammatically iilustrated in FIG. 88B. It is to be noted that, if it is desired for no line find information to be recorded in the linefind channel, as indicated by a TRUE state of line Ll, the linefind head is prcvcnted from being energized due to the fact that lhe state of line (Lit)' is t~us FALSE and thereby prevents tile output of logical AND 1798 from subs"~quently being rendered TRUE. With referen:e (0 FIG. 17, 'Nhen th~ ledGer card has been driven to the full extent into chute 291, the reversal spot located at the top margin of the ledger card, indicated as 376 in FIG. 88A, passes over the junction of the leg members 371 and 372. Consequently, the radiant energy from light source 373 is absorbed by the dark area thereof to the extent that photocdl PCB is thus deenergized. With reference to FIG. 83, when photocell PCB is de-energized, the state of line B is rendered FALSE thereby. When linc B is thus rendered FALSE, the state of flipflop 6122 is reversed, so that line P is rendered TRUE, line (P)', of course, being simultaneously rendered FALSE. \Vhen line (P)' is thus rendered FALSE, card-drive relay coil CDR is de-energized, and, as a result, relay contacts CDR-S are closed and th~reby render line (U)' TRUE. With reference to FIG. 82, also when coil CDR is de-energized, rel:J.y contacts CDR-l and CDR-2 are opened, whereas relay contacls CDR-3 and CDR-4 are closed, as shown, thus causing a reversal of subseql;[;ntly-applkd cnrrent through the is rendered TRUE; otherwi~;c, line (K1')' is rendered TRUE. If it is assumed that the diZ'; just stored in the "K" digit-rerrister h?,s a 172 v::duc other th~n zero; tl:e state of llh)floo G039 (r-;~G. 92D) is rcycr:;cd \vl,en linc Om"i is rc~[i?rcd FALSE. G 1O 1:, ~o 2:; 30 3" 40 .f.J I)U ;',} 00 (];; 70 7:; Consequently, line KE Y is thereby rendered TRUE, tndic,lling thcit the comjluter is ready to magneti:::aliy rccord the diGit now stored in the "K" di~it-registcr 011 ;he m,1£netic strip of the ledger oQrd. il.cluC!1 recording on th~ Lx!ger cnrd, however, does not begin until line S'\]l1'l (FIG. 92A) is rendered PALSE. When line S,\?vl is st:b~cquc"!1tIy rendered FA"LSE dL:C to a revers;)i of state of t1iptlop 61t:2 approximately 24:'\0 microseconds r,fter being rendered TRUE, the state of flipflop 60S9 (FIG. 92B) is ag"in reversed, so that line KEY is tbereby rendered FALSE. Wilh reference to FlG. 92C, when Iir;e KEY experiences a TRUE-to-FALSE reversal of state, the st~.tc of :1ipflop (;l(}~ is reversed, and lille SES is rendered TRUE ;md remain:; TRUE until all d'-\!a and clock information has bec;n ma~~netically recorded on the ledger c,ml. V,,'ith reference now to FlG. 85, ~,s lines SES and ROC remain TRUE during the entire recording op~ration, recordil1g current etTcctivcly flows through the winding of clock recording-reproducing hend 3'17 in one direction or in the opposite direction, depending upon whether the st:lte of line SAI'.'i is TRUE or FALSE. Tbus, it is evident, when line SES is rendered TRUE, an approximately 200-cycle-per-sccond square-wave signal is magneticnlIy recorded in the clock channel of the ledger cord while the card is being translated outwardly from the carriage at a linear speed of approxi:nately ten inches per second. As previously described with respect to FIG. 70, ,the output of the "K" digit-register is effectively ~crialized, in that the digit stored therein is effectively "read out" bit-by-bit and the state of line KS is sequentially conditioned either TRUE or FALSE for each bit, depending upon whether the bit just read out is either a "1" or a "0," respectively. Therefore, when line KEY (FIG. 61) is rendered FALSE, line CYC is reversed from TRUE to FALSE. As a result, the bit-counter (FIG. 62) is decremented from a binury count of "a" to a binary count of "d." With reference back to FIG. 70, if it is assumed that the digit previously stored in the "K" digit-rcgister is a "9"-i.e., binary IDOl-when the bit-counter is at a binary COlmt of "d," so that lir 20 25 30 :l.) clO 45 50 5;) GO (J5 70 75 3,112,394 176 175 the sequence of operation nevertheless remains substanFIG. 1·1.. After a time lapse of approximately tially unchanged. During the second phase of the sub1:::0 milli8cconos, the state of flipflop 6123 is again reprogram, after tbe ledger card ha3 reached ~he maximum versed, so that card-drive brake coil CDn is de-cnergizcd rearward position within the accounting machine carriage, thereoy. the card either is immediately ejected from the carriage Vlith reference back to F[G. 17, when the bottom edge or is placed in a proper position within the carriage ready ()f (he ledger card passes over the junction of arms 371for a position operation thereon. After the ledger card 372, pho:ocell PCB is de-energized due to the fact that is either ejeoted or placed on the next posting line, the the ra(FClnt energy from the light source 373 is thereafter third and last phase of the subprogram causes the carriage not rc!'!ccted by the ledger card onto the active area there0;'. As previously describcd, photocell PCB is connected ] I) to be closed and the preselected motor bar to be depressed for either a touch or a hold operation, in the circuit of pre-amplifier 4736 (FIG. 83) in such a Listed below in somewhat tabular form, and also graphmann'::r that the state of line (B)' is rendered TRUE when ically illustrated by the flow diagram of FIG, l07C, is a photocell PCB is de-energized. Thus, when line (8)' is step-by-step description of the various previously-described rendered TRUE. all of the inputs to gate 1775 are, for the first t!me, simultaneously TRUE, so tbat paper-guide 1;; subinstructions to which the computer is sequentially remolor PGM: is energized and is thereafter caused to rosponsive in executing an "EC\V" instruction. late in the o,posite direction, due to the fact that the paper-guide relay coil PGR W-[i '\\ hl'n a syncl1rc:ni'd;~~ clrwk imflipflop 6122 is again reversed, so that line CP), is renpuhe i..; In·lf;nl~tjCl111.r lde!u'd up frdrn ~h0, iI',lgc; c8.nl. ITi)\\e\'('r, y.h"n j [11' h"ig!-'i {',lrrl dered TRUE and thereby re-energizes card-drive relay i~ ,)[1 tlle W,-lY intl1 the r-arria;::'<; jH'-!i pri'ir to coil CDR. When coil CDR is energized, contacts CDR-S l\~V"L'nl, go /.0 Step 20 if ;J, dJl..~k impnlsn ll:t, not h~:,{'n piC'kf2d up. arc opened and thereby effect de-cnergization of paper- ~j;) 5 ______ CYC-O-fL _____ 11lrr~T!l(,l1t thr 1Jlt-c:oul1~cr; th{,l"cafkr, ~o to guide motor PGM. SU~;l-G. 6 ______ JL{l)·O-7 _____ Rtarl' in ttl\' ".P' dj~it-rl'l~j';t('r With reference to FIG. 82, when the state of line P is Tl'ml frnm the ledger C:11"d, ,.hid) tbus rendered FALSE, the state of line (EOC)' is thereby pr)ud ..; tl) thl' CJunt of tho hH~~\.}lliHpr; aftpr, 1(0 to Step-7. rend~red TRUE. Tberefor,::, with reference to FIG. 92C, 7 ______ Bd-4-8 ________ If the bit-counL!'r is at a ('lmnt of"J/' ~',O to 8teD-8; of,hc'r.\ i'J.p, r,-o to StcD-4. when line (EOC)' is thus rendered TRUE, indicating that ,10 8 ______ ng-lL-9_~ _____ , If lIlt': lli~~it-I:ollnt('f is at a PI')tlnt. of'IH/' g') 1.:1 t.11e Jedger card is completely ejected from the carriage, Step-9; olhcfXisc, go tu ~t('lJ-l1. 9 ______ C~'f-3 10 ______ C!e~1f the uddm·,s, in nl'~'UrJry ~pe~"iG.t'd fJ:--' "('L'the state of flipflop 60,}O is reversed upon occurrence of tinn-;j of th(' instrnction I"..'ghh'r; t,jl('r(,:lft~T, the next TRUE-to-FALSE reversal of state of line AN. gJ U) Sll"p-lO. 10 _____ OBN(?) 0-lL~ Pn'~('t j~!li~ OIL\J to ~l. rrHUR statv: t,hnn'~tf!L'r. \Vben the state of flipflop 6090 is thereby reversed, line to 8tqJ" 11. LK is rendered FALSE. As shown in FIG. 92A, when L10 11 _____ EO V'{-·14-1::L __ If W) the o',J" di2,it-rt'gist.t'l" !~ ;.;tfJring 15," go t.o 81(;p-12: n(.}ll'I"',\'i''',L', go to ~~cp-14. line LK is rendered FALSE, the state of flipflop 6107 is D9-13-17 ______ If t.ht, di;"dt-cl)u:1t('r i.e; at a count of"9," go to 12 reversed, so that line STD is rendered TRUE thereby. Stcp-17; otlIPn\"i;:e, i!·j t.o ~Hf.·p-l:t A 0(1) --0-12_ ~ _ Iucremn1t thE; digi~-(:{)<1U~f:r; tlll:n'l1ft,c'r, g.r) t.o 13 When line STD is thus rendered TRUE, line TS5 is likeStep-12" wise rendered TRUE. In response to lines STD and TSS 14 .. _. . .\D(1)-0-1.5 .. _ Increment the dig!t-:ounter; UH'n'"n'!T, to Step-15. thus heing rendered TRUE, a "STD" subinstruction is 00 15 _____ JI\'I-3-lfL _____ Copy th'~ uigil st~lr{'d in the ".I" digil-''("gi,t{,f thereafter executed, whereby the contents of section 5 of lncmoTY at the digit~_11 pr)~iti In indil":l',t"d by the connt. nfth,.' dlgit-:'{)tll1it ' f, ill;" ;Vi(lr'·7" jn 1he instruction register is stored in the word-selecting regmemor:.r being ~.~rled;l(~d lJY ;;I~'('~i"m :1 of nlE\ ister in the manner previously described. In addition, ill'.:t.nI{.Li IIi r: ... ~i~t0r; 1,h'_'Te,11tm, g:) t'l S~~lo-·)(L 16 _____ D~-4-17 _______ If the di,r~i-('llnnj('f h: at a cnunt IJfolH," go to when line STD is rendered TRUE, line (STD)" of course, S~,ep-li'; ()L1H~nd:i(" !~O to ~t,('p·4. being rendered F,..\LSE. line REC (FIG. 82) is rendered ;j,j 17 _____ 131-i8-HL _____ If tll~ !J1emfJl'Y a'ldre";,'·'e'~ ~J;)p['Hicd b;' ,,,{l"~ 3 a~ld 4 of the in-:.trLl(,;j'lIl I"L'gi ,tt'f n)",' FALSE, thus terminating the sequence of events initiated g.) to bd,;p-1D; o~hl'rxi~(', (!Q to ':;tp~)·-18" by the "ROC" instruction. 18 _____ I:--Joi·--o-4 _______ Incro:n2Ht ~C(;tiJ~l 3 of 01L' iw;:trlH~thfl f"Jli"d~.'r; sp~ct (0 (If 1 d ,)" j H ,0 73. Detailed Description of ECW Illstruction In execu!jng an "EeW" instruction, the control counter GO portion of the compu:er operates in conjunction with the card-handling portion thereof to effect the individual reproduction of Iincfind, clock, and data information, each being previously recorded magnetically in a different one of the three channels of the mngnetic strip portion of the G5 leltger crrrd in tbe manner just described. The subprogram for the execution of such an "ECW" instruction may be divided into three distinct phases. During the first phase of the subprogram, the data information, in the form of a sequence of words, is first read 70 from the magnetic strip and is thereafter stored in the designated memory 'address locations. If the ledger card does not have any information magnetically recorded thereon, such as, for example, a new ledger card, even though there is no information magnetically reproduced, 75 19 _____ Ll·"2~ <1," g'a to ~'l.ejl-30; oth',;'r\"'i'-;c, go to Step·-2H. If t.1l" low-orl!:..',r (iiC!:H in si'diol-2 0: j 11': in,c:t,rlldion rej!i;;ier i'{ a "'3," go to St<:;) -30; oUlUnYi~e, ~o to ~t.cp--:W. 29 .. _.. RPB-O-30 ..... Upon uC'1)fession of the re.sullle-I)rO~rmll b:Jr. go to Sj~'p-30. 3°_"'1 CLC-O-3L .. _ C!o-e tlJe accounl in~ tn:v:,ldui." ('-34-3L ____ If the high-order rJig!t in section 2 of the inKI-7 being closed, so that line GO is thereby rendered struction rr'gi:.::trr is a 110/' go to SteLl-33; TRUE; and that the carriage of the accounting machine otherwise. go to Rtep-34. 33 _____ MB (1)-1H5_ Depress the upper motor bar for a touch operais closed, so that the movable arm of switch 333 is in the the·reafter. go to St~D-45. M _____ IIl-3tl-35 ______ If tion the high-order digit in section 2 of the in- 10 position shown, so that line (D)' is TRUE. struction regi."trr is a "I, go to Step-35; Therefore, when line RED is initially rendered TRUE. ot/wr\1'i.-o. go to Step-3f). 35 _____ MB (2)-iH5_ Depros' the uppor motor bar for a hold operaline i likewise being rendered TRUE, all of the inputs to tion; thereafter. go to 8tep-45. gate 1767 are simultaneously TRUE. As a result, sole36 _____ H2-38-37 ______ If the high-order diqit in f'cction 2 of the in· strllction reghtor is a 112," go to S tcp- 37; noid Y is energized and thereafter causes the accounting otherwi,,". go to Stell-38. 37_____ Mlll (1)-0-45_ Depress the middle motor h~r for a touch 15 machine carriage to be opened in the manner previously operation; tlwreaftcr, go to Step-45. described with respect to FIG_ 38. If it is assumed that 38 _____ II3-40-39 ______ If the high-order digit in V), is TRUE, to FIG. 17. However, when the rcversal spot (indicated line 1M is also rendered TRUE when line TH is thus renas 376 in FIG. 8SA), located in the top margin of the dered TRUE. When line J:"~ is rendered TRUE. line ledger card, p1sses over the junction of the members 371 TS3 is lil;cwise rendered TRUE. Consequently, in responte to lines JM and TS) thus being rendered TRUE :l,j and 372 (FiG. 17), the radiant cnergy from the light source 373 is absorbed by the dark area thereof to the and the disit-collnter being at a COll!"!t of "0," a "Hvl" extent that the photoccll PC3 is thus de-energized. With digit·cycle is thereu fter executed, whereby the digit ju~,t reference to FIG. 83, when photocell PCB is de·energized, stored in the ".I" digit-register (i.e., "9") is stored in the the state of line B is f0!1dered FALSE thereby. When first·order digital position of the address in memory specified by the contents of section 3 of the instruction rcgist,cf. 30 line B is thlls recdered FALSE, the state of flipflop 6122 is reversed, so that line P is rendered TRUE, line (P)', of In the present example, as the first digit read from the course, being simultaneously rendered FALSE. ledger card and stored in r:12l110ry is not an encI-of-word When line (P)' is thus rendered FALSE, card-drive notation, and as there arc thereforc other di.r;itc; of the relay coil CDR is de-energized, and, as a result, relay word mR'gr:ctieally recorded on the card, the "J" digitregister is again preset to "0" by a TRUE-to-FALSE rc- 0,j contacts CDR-5 are closed and thereby render line (U)' TRUE. With reference to FIG. 82, also when coil CDR versal of state of line PJ at TI,\1E--3 "fter line JHR is is de-energized, relay contacts CDR-l and CDR-Z are again renderd TRUE. Thereaftor, the bit-counter is sucopened, whereas relay contacts CDR-3 and CDR-4 are cessively incremercted from a count of "d" through counts ·'a," Hb," and He" Lind back to a count of ·~d, I' during \vhich closed, as shown, thus causing a reversal of sUbsequentlytime the second digit magnetic,tlly read f;om the lcdgcr 40 f:ppiied current through the armature of motor CDM and a subsequent revers::!l of rotation thereof. However, when card is slored in the "J" digit-register via line JL in exactline (P), ,is rendered FALSE, card-drive motor CDM is ly the same manner as just described. Thereafter, the de-energized by the output of gate 1770 simultaneously be· digit-ccuntcr is advanced from a connt of "0" to a count ing rendered FALSE. With reference back to FIG. 83, of "1," and the digit thus stored in the "J" digit·register is thereafter stored in the second-order digitalposilion vf 4;) when line (P)' is thus rendered FALSE, the state of flipflop 6123 is reversed, so that card-drive brake solenoid the selected address in memory. CDB is enert',iz-::d. Consequently, when solenoid CDB is The above-described sequence of events is sequentially energized, th.: ledger card is brought to a slIdden standstill repeated until each of the digits of the first word is read in the manner previously described with respect to FIG. from the ledger card and thereafter stored in the selected address in memory. With reference to FIG. 91A, it is 50 14. However, approximately 120 milliseconds after solenoid CDS is energized, flipflop 6123 reverts back to its noted that line TH is rendered FALSE at each TlME-l initial state, so that solenoid CDI3 is thereby de-energized. by a reversal of state of flipflop 6061 after each "n.,'1" With reference to FIG. 82, when the state of flipflop read-write cycle is completed, as indicated by line (CFF)' 6122 (FIG. 83) is reversed, so that line P is rendered being rendered TRUE. Thus, when line TH is thereby rendered FALSE, the state of flipflop 61114 is reversed and 5::5 TRUE, line ECC is also rendered TRUE, thus indicating that the ledger card has been read. After the ledger card line SES thereby rendered TRUE, whenever either the has been read, the card is first reversed and thereafter digit-counter is at a count of "9," as indicated by line D9 ejected from the carriage, or is thereafter properly posibeing rendered TRUE, or an end-of-word notation is detioned in the carri:lge for a posting operation thereon, detected, as indicated by Hne EOW being rendered TRUE in the manner previously described with respect to FIG. 71. GO pending upon the value of the low-order digit in section 2 of the instruction register. For example, with reference If an end·of-word notation is not detected, the sta.te of to FIG. 91B, ;r it is assumed that the low-order digit in flipflop 6104 is again reversed, and line SES is thereby scdion 2 of the instruction register is an "8," indicating rendered FALSE at the following TIME--l after the digitcounter reaches a count of "9." As shown in FIG. 91B, that the ledger card is to be ejected, line (I6d)' is thereafter the digit-counter reaches a count of "9," line IN4 is G3 fore FALSE, and, as a result, the state of flipflop 6094 remains unchanged, so that line MOU, hence line RED, reversed from a TRUE state to a FALSE state when line both remain TRUE. Therefore, with reference to FIG. SES is rendered FALSE; as a result, section 3 of the in82, when line (U)' is rendered TRUE due to the cardstruction register is incremented by a count of "1" in the manner previously described. drive relay coil being de-energized, armature current is It is therefore evident that line SES ,is rendered TRUE 70 applied to card-drive motor CDM via gate 1771, so that after each word read from the ledger card is stored in the direction of rotation thereof is reversed, thus driving the selected address in memory. Consequently, when line the ledger card outwardly from the carriage. SES is subsequently rendered FALSE, it is necessary to When the reversal spot at the top margin of the ledger ascertain whether or not there is an additional word to be card leaves the junction of the leg members 371 and magnetically read from the ledger card and subsequently 75 372 (FIG. 17), photocell PCB is again energized, and line 3,112,394 183 B (FIG. 83) is again rendered TRUE. Also, when the trailing edge of the ledger card passes over the aperture of the paper guide 303 on its way outwardly from the carriage, photocell PCC is de-energized, and line C is thus rendered FALSE. Ho\vever, when the trailing edge of the ledger card passes over the junction of the leg members 371 and 372, photocell PCB is again de-energized, and line B 1S again rendered FALSE. Consequently, with reference to FIG. 83, as all of the inputs to logical AND 1775 are simultaneously TRUE after the ledger card is ejected from thc carri~ge onto the loading table, paper-guide motor PGM is thus energized and thereafter effects unlatch1ng of the compression rolls 296 from the card-drive platen 241 in the same manner as previously described with respect to FIG. 19. After the unlatching operation is completed, movable arm 336339 ,IE-i after line F9 is rendered TRUE. When line WOA is thus rendered FALSE, the state of flipflop 611)7 is rcversed, so that line STD is rendered TRUE. '.vith reference to FIG. 91B, when line STD ,is thus rendered TRUE, line TS5 is likc\vise rendered TRUE. Thereafter, in response to lines STD and TS5 being renvcred TRUE, a "STD"' i>ubinstruction is executed whereby the contents of section 5 of the instruction register is stored in the word-selecting register, thus terminating the scquencc of events initiated by the "ECW" instruction. It is to be noted that, if the numeral "6" had initially been stored in the high-order digital position of section 2 of the instruction register indicating "no motor bar operation," line WOA (FIG. 91A), after being initially rendered TRUE, remains TRUE for a period of approximately 250 milliseconds and is thereafter rendered FALSE bya reversal of state of flipflop 6H8 due to line AN subsequently being rendered FALSE after line (RF)' is rendcred TRUE by a reversal of state of flipflop 6120. Thus, when line WOA is rendered FALSE in this in~tance, line H6 being TRUE, the state of flipflop 6107 is reversed, as before, so that line STD is thereby relldercd TRUE. It will now be assumed that the ledger card, initially fed into the card-hancHing portion of the computer, is to be properly positioned in the accounting machine carriage on the next posting line ready for a posting operation thereon, rather than being ejected as just desc]1ibed. In this instance, the carriage of the machine is opened; the lower compression rolls are thereafter disengaged from the accoonting machine platen; and the ledger card is manually placed face down on the loading ,table and thereafter automatically driven into the accounting machine carriage in exactly the same manner as just described. Aftcr the data information is magnetically picked up from the magnetic strip portion of the ledger card Gnd stored in the selected address or addresses in memory, the direction of rotation of the card-drive motor is again reversed, as before, and the ledger card is thereafter driven outwardly from the accounting machine carriage in exactly the same manner a:; just described. Howcv..:r, as a line-finding operation is now 3,112,394 185 186 desired, so that the digit initially stored ,in the low-order digital position of section 2 of the instlUction register is either one of the digits "I" through "3" and "5" through "7," the state of flip flop 6094 (FIG. 91B) is reversed at TIME-l after line EOC is rendered TRUE, indicating that the ledger card is completely scanned, due to a TRUE-ta-FALSE reversal of state of the output of gate 1611. Consequently, the states of lines ;vl0U and RED are simultaneously rendered FALSE just after the initial forward direction of movement of the ledger card is reversed. With reference to FIG. 85, as the state of line (L)' is normally TRUE, the stnte of output line Q is likewise rendered TRUE by gates 1802 and Hill when line (RED)' is rendered TRUE. Consequently, with reference to FIG. 82, due to the fact that line Q is rendered TRUE simultaneously with line i being rendercd FALSE when line MOU is rendered FALSE, the card-drive motor CDM remains energized and continues to drive the ledger card outwardly from the accounting machine carriage. As previously described with respect to FIG. 17, when the reversal spot at the top of the ledger card leaves the junction of the arms 371 and 372, the photocell PCB is energized by the light source 373. 1\180, as previously described with respect to FIG. 83, line B is rendered TRUE when the photocell PCB is energized. \Vith reference to FIG. 85, when line 13 is thl1s rendered TRUE, the lowermost reference input to flipflop 61AG, as viewed, is thereby rendered FALSE, and line l\H4 is simultaneously rendered TRUE. When the lowermost reference input to flipflop 6146 is thus rendered FALSE, t'1e flipflop is thereafter propedy conditioned to be responsive via line (Rq,)', to a predetermined one of the negativcgoing Enefind impulses derived by linefind head 346 from the information previously stored in the linefind channel of the magnetic strip portion or the ledger card. Consequently, each time a negative-going Jinefind impulse is derived by pick-up head 346 as the ledger card is being driven outwardly from the accounting machine carriage, the impulse appears amplified and inverted at the output of transistor gate 1306. As a result, the state of output line LFA experiences a FALSE-to-TRUE-toFALSE reversal of state each time a linefir:d discontinuity is magnetically sensed by pick-up head 346. It is to be appreciated at this point that, when an "ECW" subprogram is fiTst initiated, the R-counter is preset to a count of "I;' "2," or "3," depending upon whether the ledger card is to be respectively positioned on the first, second, or third posting line. That is, if the low-order di,'Sit in section 2 of the instruction register is a "1" or a "5," the R-countcr is preset to a (';Ollnt of "1"; if the low-order digit in section 2 is a ''2'' or a "6," the R-counter is preset to a count of "2"; and if the loworder uigit is a "3" or a "7," the R-counler is preset to a count of "3," all of which is clearly illustrated in FIG. 68. As previously noted, a "0" in the low-order digital position of section 2 of the instruclion register initiates a "enter-new-card-with-manual-resume-program" cycle of operation. If it is assumed that the low-order digit in section 2 of the instruction register is a "7"-i.e., "stop on third linefind with automatic-resume-program"--the R-counter is pre~et to a count of "3," so that lines Ra and Rb (FIG. 68) are rendered TRUE, whcreas lines Rc and Rd remain FALSE. With reference to FIG. 91B, each time the state of line LFA reverses from TRUE to FALSE in response to a linefind discontinuity being detected, the state of line DR likewise reverses from TRUE to FALSE. Consequently, the R-counter is decremented each time a linefind discontinuitv is detected. Therefore, when the third !inefind discontinuity is detected, the R-counter is decremented from a count of "1" to a COllnt of "0," so that line Rq, (FIG. 68) is thereby rendered TRUE. \"lith ref. erence to FIG. 85, when the state of line (Rq,), is rendered FALSE, tile slate of flipflop 6146 is reversed, so that line (L)' is thereby rcr:clered FALSE. As a result, line Q likewise is rendered FALSE. With reference to FlG. 82, as a result of line Q thus being rendered FALSE, the card-drive motor CDl'vl is de-energized. Also, as shown in FIG. 83, 'when line (L)' is rendered FALSE, the state of flipflop 6123 is reversed, so that the earddrive brake solenoid COB is energized for a period of approximately 120 milli:;econds and thereby causes the ledger card to be brought ;0 a sudden standstill. At this point, the ledger card is properly positioned with respect to the next po"ting line and is held tightly pressed against the card-drive platen 241 (FIG. 19) by means of the compression rollers 296 in order to maintain propcr rcgi:itcr thereof. In addition, the carriage is now open, so that <.dditional forms may manually be inserted therein, if desired. With reference to FIG. 82, line EOC is likewise rendered FALSE when line (L)' is rendered FALSE. Due to the fact that line CLC is rendered TRUE as a result of an "automatic" resume-program operation being specified by the value of the loworder digit of section 2 of the instruction register, carriage-close solenoid Y is energized when line (EOC)' is thus rendered TRUE and thereafter causes the accounting machine carriage to be closed in the same manner as previously described. It is to be noted, however, that, if a manual resumcprogram is specified by the value of the low-order digit of section 2 of the instruction register, line CLC is reno dered TRUE upon subscqllcntdcpression of the resume· program bar, at which time line RPB is rendered TRUE. During the carriage-closing operation, the lower com· pression rolls 21lS (FIG. 17) are spring·urged into engagement with the accounting machine platen 71, with the lower edge of the ledgcr card firmly secured therebetween, and the movable arm of the switch 545 (FIG. 82) is deflected to the position shown, so that line (G)' is rendered TRUE and line G is rendered FALSE, thus causing solenoid Y to be dc-energized. When line (G)' is thus rendered TRUE, the ,paper-guide motor PGM is energized and thereafter effects unlatching of the compression rollers 296 (FIG. 19) from the card-handling platen 241. After the unlatching operation is completed, the paper guide 282 is spring-ur~cd to the position shown in FIG. 17, and the switch arm 33G-339 (FIG. 82) is effectively deflected downwardly to the position shown, so that line E is rendered TRUE and line N is rendered FALSE thereby, Also, after the unlatching operation is completed, the plungcr of switch 333 (FIG. 16) is released by the tail of memb'2r 329, so that the movable arm of switch 333 (see FIG. 82) is deflected to the position shown, so that jine (D)' is rendered TRUE and line D is rendered FALSE thereby. When line D is thus rendered FALSE, the state of flipflop 6124 (FIG. 83) is reversed, and, as a result, carriage-horne-unlock solenoid CHP is energized for a period of approximately 40 milliseconds and thereby allows the accounting machine carriage to thereafter be moved away from home position when a machinccyc1e is subsequently initiated. When line N is thus rendered FALSE, the state of flipflop 6122 is reversed, so that line (P)' is rendered TRUE and card-drive relay solenoid CDR is simultaneously energized thereby. As a result of solenoid CDR thus being cn.;rgized, rcby contacts CDR-5 are opened and thereby cause paper-guide motor POj'\,! to be de-energized, Simul· taneously therewith, relay contacts CDR-l and CDR-2 (FIG. 82) are closed, whereas relay contacts CDR-3 and CDR-4 are opened thereby. With reference to FIG. 91/\, at the following TIME-3 after line (D)' is rendered TRUE, the state of flipflop 6118 is reversed, so that line WOA is rendered TRUE thereby. As a result of line WOA thus being rendeTed TRUE, the particular motor bar depression indicated by the value of the high-order digit in section 2 of the instruction register is initiated 5 10 15 20 23 30 ;l,) 40 45 50 55 GO G5 70 75 3,112,394 188 187 in exactly the same manner as previously described in detail. After a machine cycle is initiated, the state of flipflop 6107 is reversed in the same manner as previously described, so that line STD is thereby rendered TRUE. :; As shown in FIG. 91 B, when line STD is thus rendered TRUE, Jine TS5 is likewise rendered TRUE. Consequently, in response to lines STD and TS5 being rendered TRUE, a "STD" subinstruction is thereafter executed whereby the contacts of section 5 of the instruction regis- 10 ter is stored in the word-selecting register, thus terminating the sequence of events initiated in accordance with an "ECW" subprogram. 74. Detailed Description of SHF Instl'llctioll Slep 3 ______ 4 ______ 5 ______ 0 ______ 7 ___ . __ 8 ______ 1;3 ~e~~~ci~s~:u~~~nv~~~fst~;, ~~~tJ~~:~-;~~~:r~:~~ ft~ !~~~i~r~j~ sign, and, thereafter, the word is stored in memory at the address specified by section 4 of the instruction register. Listed below in somewhat tabular form, and also graphically illustrated by the flow diagram of FIG. 107E, is a step-by-step description of the various previouslydescribed subinstrllctions to which the computer is sequentially responsive in executing a "SHF" instmction. ---_._---------- Step Suhinstructi0ns ,. ]){'s('riplioll - - - - - ----------- -----~----- COry th~ 11('xt in~;tru('tion ,,,'ord intn j11r inM f,f,r"tlPtlon n'gi;;tN, t118 Hdflr!~,~s in m(~nlOry (If the lwxt ir1'-tnwti(ln w()rd llCillg' illdir'utpd hv I1w C(111j(\llt~ ofthl' ,,~ord-~t'lecting rc~j~·t('r; nit;n'nftef! il1.l1f' ('(mt(,T1t.~~, thu'l ;'torrd in f(,Clion 1 oftlw in~trwtion r~'~i~I(Tk "O·j,~l CElrry out tho ~llhin~'(rll('ti('.n li~'jrd in fitcp 2 of the f(,11owing- ~~nF 8uhprop-rnm. i\r A -3-3 ______ _ CI/l1Y into nd(lfl<"~-A Ow \yoru :'torrd in ITlrmory ~ll tllt' rddrr)"'.s ~TNinNl lly ,rrd.inn .3 of tlll' in~'jrl1('!i(in n'ri'"~or, 1!TH1, "inw1t:n'E"on-ly nwn'wHl1, ('(\fiy jh(~ l,i"Orl'l d1rit 1·;: (';i'H 1Tlt.O tho oJ OJ digH-rl'gbtl~r: ~ hell',lL l t, ~,c l:...a ~ ll;.':3. 10 _____ 11. ____ :c:0 Description tir)r1S 9 _____ - In executing a "shift" instruction, one of five possibJe subprograms is carried out, depending upon the value of the high and low order digits stored in section 2 of the instruction register. For example, if the number stored in section 2 of the instruction register is "00," a simple copy operation is carried out, whereby the word stored in memory at the address specified by the contenls of section 3 of the instruction register is copied into the address in memory specified by the contents of section 4 of the instruction register; if the high-order digit stored in section 2 of the instruction register is a "2," the word stored in memory at the address specified by section 3 of the instruction register is shifted to the left by the number of digital positions specified by the value of the low-order digit stored in section 2 of the instruction register, and, thereafter, the result is stored in the address in memory specified by section 4 of the instrnction register; if the high-order digit stored in section 2 of the instruction register is a "3," the word stored in memory at the address specified by section 3 of the instruction register is shifted to the right by the number of digital positions specified by the vallie of the low-order digit in section 2 and is rounded off to the ne3rest halfcent, and, thereafter, the result is stored in memory at the address specified by section 4 of the instruction register; if the high-order digit in section 2 of the instruction register is a "4," the wonl stored in memory at the address specified by section 3 of the instruction register is shifted to the right by the number of digital positions specified by the value of the low-order digit in section 2 of the instruction register while preserving its alegbraic sign, and, thereafter, the word is stored in memory at the address specified by section 4 of the instruction register; and, if the high-order digit in scc~ion 2 of the instruction register is a "5," the word stored in memory at the address specified by section 3 of the instruction register is shifted to the right by the number of digital positions Subin;:;truc- 12 _____ l~L ____ 0B:'[(4)-O-L_ Prc'ct the state ofline on:-! to oorn,,])ond to the algebraic ~ig-n of the \yorrl just rt'ad from nH~mory; t,hercaftf'r, go to Step 4. . H,Lrt-O-3 ______ i PfG"ct the H-eOl1nler to a count, r~orr('sp(mdmg t.o tlle low-ord{lr J-if!it of ~(1:etiol1 2 of t,hp iUR ctruction rcgi::.!er; ttH~T('arrer, go to ~tl"P 5. R STD-I;-* <' 1h~:reaHcr, gO to Ekp 2. ._._ •• Copy the ('ontUlts of ~("ction fi of UlC' im:truc- Hon regi~tcr into the word-Hlrding H'd1ill'r. 45 Upon completion of the execution of the previously ini· tiated "M[" word cycle, during which time the next in· struction word stored in memory at the address indicated by the contents of the word·selecting register is read out and stored in the instruction register, if the contents of section I of the instruction register thereafter corresponds to the code designation for a "CMA" instruction (i,e., "05"), the state of line CMA is rendered TRUE in thc manner previously described with respect to FIG. 56, and, as a result, a "CMA" instruction is thef'<:after cxeclited in the following manner: At TIME-4 after the "MI" word· cycle is substantia!!y completed, line AN (HG. 61) is again rendered TRUE and ten microseconds later at TIME-l ,is again rendered FALSE. With reference back (0 FIG. 76, whcn line AN is rendered FALSE upon completion of the "1\11" word·cycle operation, the stale of flipflop 6092 is again reversed, and line !'vir is rendered FALSE thereby, thus terminating the "Ml" word·cycle operation. A, pre· viously mentioned with rcspect to FIG. 72, as long as both of Jines MI and AN are TRUE, line MIN is TRUE. Consequently, when line AN ,is thus rendered FALSE, line MIN is likewise rendered FALSE. Refercnce is now made to FIG. 94, wherein there is logically illustrated a composite circuit diagram of var50us portions of the computer circuitry utilized in 50 55 60 05 70 75 76. Detailed Description of iHB Instructions A "motor bar" instruction simply initiates selective depression of a predetermined one of motor bars 23, 27, or 28 (FIGS. 2 and 38) for either a "tonch" or a "hold" operation and thereafter immediately proceeds to the next instruction. As previollsly dcscribed, the par· ticular type of motor bar depression is determined by the value of the high·order digit of section 2 of the instruction register. For example, if the high·order digit of section 2 of the instrucHon register is a "0," upper motor bar 23 is actuated for a touch operation; jf the value of the high·order digit is a "I," upper motor bar 23 is actuated for a hold opcration; if the high· order digit is a "2," middle motor bar 27 is actuated for a touch operation; if the high·order digit is a "3," middle motor bar 27 is actuated for a hold operation; if the high·order digit is a "4," lower motor bar2S is ac. tuated for a to[lch operation; and, jf the high.order digit is a "5," lower motor bar 2& is actuated for a hold operation. Al~;o, as previously described, the value of the low·order di~it of section 2 of the instruction regis. ter determines the position of the decimal point when the word is subsequently printed out. For example, if the low·order digit is a "0," a normal decimal point is printed between the second ,end third order digits of the word printed out; if the low·order digit is a "J," a decimal point in the form of a "comma" is printed be· tween the fifth and sixth order digits of the word printed out; if the low·order digit is a "2," a comma is printed between the eighth and ninth order digits of the word printed out. Listed below in somewhat tabular form, and also graphically illustrated by the flow diagram of FIG. 107G, is a step·by.step description of the various previously described subinslructions to which the computer is sequen· t;alIy rc"ponsive in executing a "MB" instruction. 3,112,394 194 193 Step Subinstructlons DescripUon L _____ MI-Q-L _____ _ Copy the next instruction word from memory in to the instruction register, the address n1ernory of the ne:'l..t illstrn(~tion in 5 word lwing- indicated by the contt'llts of the word~ s('lceting rcgistt'r; thereafter, if the contc'nts of section 1 or the ins.truction reViflter i~ 00," ~o to Step 2 of the following" AlB" subrrogram. 2 ______ PF¢-O-L _____ Prrset the F-countrr to "0"; thereafter go to 3. 3 ______ GO-Q-4 _______ 00Step to Stp!} 4 '\vhrnrver (lcprcss;on of a motor bar is capable nf irdtint~n2; a cycle of operation of the m'('OtlntJnf! mnehine. 4______ H¢-6-L ______ If the high-order (Ii~it of section 2 of the in· SLnlction regi~tcr is a "0," go to Step 5; other"1'·1s[', go to Step 6. 5 ______ :'.iB¢(1)-Q-1L Depress the upper motor bar for a touch opera· It t1.on; therpnfter, go to Rtrp lG. 6 ______ Ml-8-L ______ If the high-ordC'·r dt~jt of Sf'ctlon 2 of the instw('t:on register is 1I1,n go to Step 7; otherwise, go to 8tep 8. 7 ______ MB¢(2)-Q-1fi_ Depress the upper motor bar for a hold operation; thereafter, go t.o Step IG. 8 ______ II2-1G-9 _______ II the high-order d i~it of sertion 2 of the instmction regist(~r is a "2/' go to Step 9; otherwise, go to Step 10. 9 ______ MB1(l)-O-lL Drprc-ss the middle motor hn.r for a touch operntion; thereafter, go to Step 1G. 10 _____ II3-12-1L ____ If the high-order digit of se('t.ion 2 of the instruction rc~!ish;r js a l '3," go to Step 11; othcn\'i~e, go to Step 12. lL ____ MB1(2)-Q-1L Depress t.hc mir digits, and, if there afe no highcr-onlrr sig-n[1krmt. digtts, print [L "0" prcreding the COIlUlla. Therenfter, go to St.ep 20. 20 _____ PCT-Q-2L __ _ V{hpTI the ~mOllnt rar}{s arc trn.vC'ling in a "setting" direction, go to Step 21 ench time the timing rack is translated to a different digital valued position and also when U:e print.ing alien(~r i.s ('ngageu. 2L ____ AF-Q-22 _____ _ Increment the F-(;Ollnter; thereafter, go to Stt'P 22. 22 _____ F9-20-23 _____ _ If the F-colJnter is at a count of "9," go to Step 2~'3; othc·nvlsP, go to 8tt;p 20; 23_ ____ STD-5-· _____ _ Copy the {"on tents or s('L'tion 5 of the instruction register into the word-selecting register. Upon completion of the execution of the previously initiated "MI" word-cycle, during which time the next instruction word is read out from the address in memory specified by the contents of the word-selecting register and thereafter stored in the instruction register, if the contents of section 1 of the instruotion register thereafter corresponds to the code designation for a "MB" ,instruction (Le" "06"), the state of line MB is rendered TRUE in .a manner previously described with respect to FIG. 56, and, as a result, a "motor bar" instruction is thereafter executed in the following manner; With reference to FIG. 95, there is logically illustrated therein a composite circuit diagram of particular portions of the computer circuitry utilized in executing a "MB" instruction. As shown therein, upon completion of the previously-initiated "MI" word-cycle, the state of flipflop 6089 is reversed when line MIN experiences a TRUE-to-FALSE reversal of state, and, as a result, the state of line KEY is rendered TRUE thereby. Also when line MIN is initially rendered TRUE, line PFet> experiences a TRUE-to-FALSE reversal of state, thus causing the F-counter (FIG. 72) to be preset to "zero." As previously described in detail, if it is assumed that 30 35 40 45 50 55 60 65 70 75 the accounting machine is in a condition such that actuation of a motor bar is capable of initiating a cycle of operation thereof, line GO is rendered TRUE, indicating that a cycle of operation of the accounting machine is permitted to be initiated at this time. It being assumed that line GO is TRUE, the state of flipflop 6118 is reversed at TlME-3 after line KEY is rendered TRUE and line WOA is thereby rendered TRUE. When line WOA is rendered TRUE, a selected one of motor bar solenoids MBcp, MBI, or MB2 is energized, depending upon the value of the high-order digit of section 2 of the instruction register. For example, if the high-order digit is either one of the digits "0" or "1," motor bar solenoid MBet> is energized; if the high-order digit is either one of the digits "2" or "3," motor bar solenoid MBI is energized, and, if the high-order digit is either one of the digits "4" or "5," motor bar solenoid MB2 is energized thereby. As a result of a selected one of the upper, middle, or lower motor bar solenoids being energized, a cycle of operation of the accounting machine is thus initiated thereby. With reference to FIG. 72, when the accounting machine begins to cycle, the movable arm of switch 540 is deflected to the left, as viewed, so that line (NT)' is thereby rendered TRUE. Thereafter, each time the accounting machine timing rack is translated from one digital valued position to a successively high-order digital valued position, the state of flipflop 6072 is reversed, so that line PCT experiences a TRUE-to-FALSE reversal of state in the same manner as previously described. Also as previously described, a TRUE-to-FALSE reversal of state of line PCT effectively increments the F-counter by a count of "1." With reference back to FIG. 95, after the F-counter reaches a count of "9," so that line F9 is rendered TRUE, the state of flipflop 6118 is reversed upon occurrence of the following TRUE-to-FALSE reversal of state of line AN, and, as a result, line WOA is rendered FALSE and thereby causes any previously-energized motor bar solenoid to be de-energized. When the F-counter first reaches a count of "8," so that line F8 is rendered TRUE, order-hook solenoid OHl is energized if the low-ordered digit in section 2 of the instruction register is a "1," whereas order-hook solenoid OH2 is energized if the low-order digit in section 2 is a "2." As previously described with respect to FIG. 35, when order-hook solenoid OHl is energized, all order-hooks from the third to and including the eighth one are unlatched from their respective type sectors. However, when order-hook solenoid OH2 is energized, all order-hooks from the third to and including the eleventh one are unlatched from their respective type sectors. Also as shown, upper motor bar solenoid MB is deenergized when the F-counter is advanced from a count of "0" to a count of "1," unless the high-order digit in seclion 2 of the instruction register is a "I"; middle motor bar solenoid MBI is de-energized when the Fcounter is advanced from a count of "0" to a count of "1," unless the high-order digit in section 2 of the instruction register is a "3"; and lower motor bar solenoid ME2 is dc-energized when the F-counter is advanced from a count of "0" to a count of "1," unless the high-order digit is a "5." It is evident, therefore, that either a touch or a hold operation of a particular motor bar is accomplished simply by maintaining the corresponding motor bar solenoid energized for a predetermined period of time. However, as previously stated, when line '\lOA is subsequently rendered FALSE, any previously-energized motor bar solenoid is de-energized thereby. After the F-counter reaches a count of "9," so that line F9 is rendered TRUE, the state of flipflop 6IG7 is reversed when line WOA is thus rendered FALSE and line STD is rendered TRUE thereby. When line STD is thus rendered TRUE, line TS5 is likewise rendereel TRUE. Consequently, a "STD" subinstruction ::,112,304 196 1£5 78. Detailed Description of ADD Instructions is thereafter executed whereby theconlents of section 5 of the instruction register is copied into the wordselecting register, thus terminating the sequence of events executed in accordance with a "MB" subprogram. In executing an "add" instruction, any two words stored in memory addresses ¢¢ through 99 are algebraically added togethn, and their sum is thereafter stored in any 5 predetermined memory address. 77. Detailed Description of STP Instructions Listed below in somewhat tabular form, and also The "stop" instruction is utilized simply to effect cessagraphically illustrated by the flow diagram of FIG. 1071, tion of al1 computation 2nd data-handling activity within is a step-by-step description of the various previouslythe computer until the rcsume-program-bar is manually described subinstructions to which the computer is sedepressed. W quentially responsive in executing an "ADD" instruction. Listed below in somewhat tabular form, and also graphically illustrated by the flow diagram of FIG. 107H, is a step-by-step description of the various previously deDescription Subil]struc~ Step tions scribed subinstructions to which the computer is sequen- - ----- ------------------tially responsive in executing a "STP" instruction. 15 L _____ 1\11-0-2 _____ _ Copy the noxt instruction word from momory --,--------;------------------ I ----.-0-1 L _____ l\!LO-. _____ _ Copy (he Step SuLInetructlOII8 I Ill'XL ~nstrll(·tin!l won] frol1l memory 20 into the in~trt;d;on rt':!:istl'r, Ill{' nd(1r('~,s in IIlE-'Hlm"y of tUl' H(''Xt itJ~,tn~{'t:on "',ron I h('in~ imi;eatt'd hy t.he 2 ____ _ into lhe instruction regielcr. the address in JI~('rnory of the next instruction word bl:'ing indicated by tho contents of the word-srlectin;; n~,.;ister; thereafter, if the contents of section 1 of t.he instruction re~ister is '08," go to Stt'P 2 o( the following sLlbpro~ram. CO],y into addrcss-A the word located in the uIlLlrl'SS in tflcmory ::;pedf'w\l by the contents of ~t.:'(·,tion 2 of tlw iUf:'trnction regist-Pf, and simuU""HlcOusiy eopy tlw ",;on], digit by digit, into the uJ" di~it-register; thereni(er, !!o to Step 3. Add to the word stored in address-A the word stored. in the tidrlrt:s~ in Illemory specif1ed by the contents of section 3 of the instruction register, and thereafter store the sum back in addreSS-A; thereafter, go to Step 4. Copy the word of aililregs-A into the address in memory specified by the contents of sec~ Uon 4 of the instruction register; tht'rcafter, go to Step 5. Copy the contents of ,;ection 5 of the ins.Lructio!! re~i;.;ter into the word~selectlng regIster. r()nt~ntsof ilIA -2-3 ______ _ lhe \voru-.ch'ct· ing rt'g"istf'r; tl}f'rl'Llft:~'r, if Ow COlltpllt~ nl ~;C«tiOll 1 of til(' in:-:Lrudion TI'g-istpr t~ --()-3 _____ _ 3 ______ rR4>-()-L ____ _ 4______ MA-3-5 ______ _ 5 ______ OBM(4)-0-fJ 6 ______ OBl\I(2)-7-S __ 7 ______ CPA-0-8 _____ _ tion~ 8 ______ 5 9 ______ Cll-O-9 AM-n-10 10 _____ 10 1L ____ De,cription I Clr~r n1; otlwrwi:"l', !IO to 8trp 22_ 22 _____ RAD-4-23 ____ Add to the word storcu in adurcss-A th~ word stOTl'U in memory at. the address :"perified by section 4 of j he in~t rw::t ion r('gistf'r; tlWrt.'ufl.er, go to Step ~3. 23 _____ DR-{)-2L ____ Dem'TIlent tho H-countcr; thereafter, go to Step 21. 2'- ____ SA(2)-{)-25 ____ Shift. the word of uddress-A one place to the rivht; thereafter, go to 8t:qJ 25. 25 _____ SB(2)-{)--2tL __ Shift the word of address-TI onr pJace to the righl; thrreaftPT, go to Stcp 20. 26 _____ AF-{)-2L _____ IIl-C'rern('nt 1be ~'-countcr; the-reuf:er, go to 8trl) '27. 27 _____ 1'1-17-28 _____ If the F-cnuntrr is at a, ('ount of HI0," go to Step ?R; otlwrv,:i:;c, go to Step 17. 28 _____ HLlt-{)-2L ___ Pre,,('t the R-('nun1cr to a count corresponding to thr low-of(ler digit of :"C'ction 2 of the instruct ion rc~i~ trr; thereafter, go to ~,t(,P 29. 29 _____ H¢-30-4L ____ H The R-COU1ll{"'Lr is at a (,Ol1nt of "0'1 go to Step 4]; ot.herwi~e. go to Rtt'p ~iO. 30 _____ H2-31-33 ______ HOw hip:h-ordfp 32. 32 _____ 1I4-{)-3fi_______ If Ihe hi~h-order digit of ,cction 2 of the instmeI inn l'l'gistrf i"- a i'~," go to St('1> 36. 33 _____ SA(1)-O-3L __ ShirL ,he word of adllrc,"-A one plaC(' to the left; l1H'r('aftrr, go to Step 34. 34 _____ SB(l)-{)-!O ____ Shift the word of aclrln'ss-B one pineo to the left; thereafter, go to Rtep 40. 35. ____ R1-3G-38 ______ If tllt' n_-cftunh'r is at a Cl1lUlt o( "1,'1 go to .c..rt'p 3~; ojhen\i~'t', go to Stt'P 3u. 30 _____ 8A{2~1-0-37 ____ .shift 011' ,o".'unL of adtlress-A on{' plarc to the ri>:hr; go to 81l:p 37. 37 _____ SB(3)-O-40 ____ Shift tlwtherl':1ft('r, word of nddro~~,-B on(' place to the 38 _____ Step 8ul,in::;trnc- I rj~ht; tlH'T{'arl('r, go to .Step 40. DAD-0-39 ____ A(1 is TRUE, line TS3 is likewise rendered TRUE when line MA is initially rendered TRUE. As a result of lines MA and TS3 being rendered TRUE, a first "fvfA" word-cycle is thereafter executed, whereby the multiplier word stored in the address in memory specified by the contents of section 3 of ,the instruction register is read out and stored in addrcssA. Simultaneously therewith, the multiplier word just read out from memory is copied digit by digit into the "J" digit.register. Upon completion of the "MA" wordcycle, the state of flipflop 6091 (FIG. 102B) is again reversed, so that line MA is rendered FALSE thereby. If, upon completion of the just-executed "MA" wordcycle, the algebraic sign of the multiplier word just read from memory is negative, so that the tenth-order digit thereof stored in the "J" digit-register is a "9," the stute of line OBM remains FALSE. Howeve,r, if the tmthorder digit stored in the "J" digit-register has a value other than "9," the state of flipflop 6095 is reversed upon completion of the "MA" word-cycle, and line OBl'I,1 is thereby rendered TRUE. Thus, it is evident, the state of line OBM is rendered TRUE if the algebraic sign of the multiplier word is positive and is rendered FALSE if the algebraic sign of the multiplier word is negative. If the algebraic sign of the multiplier word just read from memory is negative, so that line J9 is rendered TRUE, the state of flipflop 6083 is reversed upon completion od' the previously-initiated "MA" word-cycle, and line CPA is thereby rendered TRUE. As previollsly described, when line CPA is rendered TRUE, a "CPA" subcommand is ,thereafter executed, wher,eby the multiplier word stored ~n address-A is first read out and complemented, and, thereafter, the absolute negative value thereof is stored back in address-A. Upon completion of the "CPA" subcomm:11ld, the state of flipflop 6083 is ag,lin reversed, and line CPA is thereby rendered FALSE. It is to be noted that the state of flipflop 6081 is reversed and line CB thereby rendered TRUE, either upon completion of the first "MA" word-cycle if the algebraic sign of the multiplier word is positive, or upon completion of the SUbsequently-initiated "CPA" subcommand if the algebraic sign of the multiplier word is negative. In either 5 10 IJ 20 25 30 0.) -Jil 45 iJO ;:;5 60 65 70 75 event, in response to line CB thus being rendered TRUE, a "CD" word-cycle is thereafter executed, whereby a word of all zeros is stored in address-B. Upon completion of tbe "CIl" word-cycle, tlie state of flipflop 6081 is again reversed, so that line CB is thereby rendered FALSE. \Vith reference to FIG. l02A, in response to line cn thus being rendered FALSE, the st~te of flipflop {j077 is reversed, and line AM is rendered TRUE thereby. Line Ar>.'l being rendered TRUE likewise renders line TS3 TRUE. Conscquent!y, in reopome to lines All'! and TS3 bdr.g rendered TRUE, an "AM" word-cycle is thereafter cxecuted, whereby the absolute value of the multiplier word stored in address-A is read out and stored in memory at the address specified by the eontcnts of section 3 of the instruction register. Upon completion of the "AI\1" word-cycle, the state of flipflop 6077 is a::;ain reversed, so that line AM is rendered FALSE thereby. As shovm in FIG. 102B, line PRS is also rendered FALSE as a result of line AM thus being rendered FALSE. Line PRS thus being rendered FALSE causes the R-countcr to be preset to a count of "8." Also, \vhen line Ai'>'! is thus rendered FALSE, the stilte of flipflop 6091 is agnin reversed, so that lin~ l\'IA is rendered TRUE for the second time. However, as the R-countel' is GO'N at a count of "8," so that line R8 is TRUE, line TS4 (FIG. l02C) is likewise rendered TRUE \vhen line j,IA is rendered TRUE. In response to lines ttA and TS4 thus being rendered TRUE, a second "MA" wordcycle is there8fier exccuted, whereby the multiplicand word stored in memory at the address specified by the contents of section 4 of the instruction register is read out and ;;tored in address-A. Simultaneously therewith, the multiplicand word just read out from memory is copied digit by digit into the "I" digit-rcgiskr. Upon completion of the second "MA" word-cycle, the state of flipflop 6091 (FIG. 102B) is again reversed, so that line MA is rendered FALSE thereby. If, upon completion of the execution of the second "MA" wordcycle, the algehraic sign of the multiplicand word just read out from memory (as ind icated by a TRUE st<:tc of line J9 if negative and a TRUE st~"e of line (J9)' if posilive) corresponds to the algebraic sign of the multiplier word (as indicated by a TRUE state of line OEM if positive and a TRUE state of line (ORM)'), the state of flipflop 6096 is reversed, so that line OBN is rend~red TRUE, indicating that the algebraic sign of the prodtlct is positive. However, if such correspondence does not exist, the state of line OBN remains FALSE, indicating that the algebraic sign of the product of the two factors is negative. In addition, if the algebraic sign of the multiplicand is negative, so th~t line 19 is rendered TRUE, the state of flipflop 60S3 is reversed upon completion of the previously initiated "MA" word-cycle, and line CPA is thereby rendered TRUE. As previously described, when line CPA is rendered TRUE, a "CPA" subcommand is thereafter executed, whereby the word stored in address-A is read out and complemented, and, therc::fter, the absolute negative value thereof is stored back in addrcss-A. Upon completion of the "CPA" subcommand, the stale of flipflop 6(183 is again reversed, and line CPA is therehv rendered FALSE. It is again to be noted that the state of flipflop 6GSI is reversed and line CB thereby rendered TRUE, either upon completion of the second "lvfA" word-cycle if the algebraic sign of the multiplicand is positive, or upon completion of the "CPA" subcommand if the alegbraic sign of the multiplicand is negative. In either event, in response to line CB thus bein~ rendered TRUE, a "CD" word-cycle is thereafter eAecul~d, whereby a word of all zerm is stored in address-B. Upon completion of the just-initiated word-cycle "CB", the state of flipflop 6081 is ag?in reversed, so that line CB is thereby rendered FALSE. With reference to FIG. I02A, when line CB i3 thus rendered FALSE, the state of flipflop 6077 is revef~cJ, and line AM is rendered TRUE thereby for the second time. When line AM is 3,112,394 205 rendered TRUE, line TS4 (FIG. l02C) is likewise rendered TRUE. Consequently, in response to lines AM ,md TS4 being rendered TR VE, an "AM" word-cycle is thereafter executed, whereby the word in address-A is stored in memory at the address specified by the contents of section 4 of the instruction register. Upon completion of the "AM" word-cycle, the state of flipflop 6077 is again reversed, so that line Arvr is rendered FALSE thereby. The steps of the subprogram to this point have been concerned with determining the algebraic signs of the multiplicand and the multiplier, conditioning the state of line OBN to be indicative of the algebraic sign of the product of the two factors, complementing either or both of the factors if the algebraic sign of either or both is negative, and thereafter returning the absolute value of the two factors to their original addresses in memory. With reference now to PIG. l02A, after the absolute value of the multiplicand is stored in memory at the address specified by the contents of section 4 of the instructi'On register, via the previously-initiated "AM" wordcycle, the state of flipflop 6080 is reversed when line A~! is thus rendered FALSE for the second time, due to the fact that the R-counter is now at a count of "8," as indicated by a TRUE state of line R8. When the state of flipflop 6030 is reversed and line CA is rendered TRUE thereby. In response to line CA being rendered TRUE, a "CA" word-cycle is thereafter executed, whereby a word of all zeros is again stored in address-A. Thereafter, the state of flipflop 6080 is again reversed, and line CA is rendered FALSE. As a result of line CA thus being rendered FALSE, the state of flipflop 6066 is reversed, so that line MJ is rendered TRUE thereby. Substantially coincidentally therewith, line PR¢ (FIG. W2C) experiences a TRUE-to-FALSE reversal of state and therehy causes the R-counter to be preset to "0." When line MJ is thus rendered TRUE, line TS3 (FIG. 102A) is likewise rendered TRUE. ConsC"quently, in response to lines M1 and TS3 being rendered TRUE, a "MJ" word-cycle is thereafter executed, whereby the multiplier stored in memory at the address specified by section 3 of the instruction register is read out and the first-order digit thereof is stored in the R-counter. The reason that only the first-order multiplier digit is stored in the R-countcr via the previously initiated "MJ" word-cycle is that the F-counter was initially preset to zero, and thus line RLM is TRUE only during that time the count of the digit-counter is also equal to zero. Otherwise, line (IFD)', hence line RLM, remains FALSE. As previously described in detail, a digit is stored in the "J" digit-register from memory only when line RLM is TRUE. After the first-order digit of the multiplier is stored in the R-counter, the state of flipflop 6066 (FIG. 102A) is again reversed, so that line MJ is rendered FALSE thereby. If the first-order mulliplicr digit now stored in the R-counter has a value other than "0" as indicated by line (R¢ )'bcing TRUE, the s(:.:te of flipflop 6091 is reversed when line l\fJ is thus rendered FALSE, and, as a result, line RAD is rendered TRUE thereby. When line RAD is thus rendered TRUE, line TS-1 (FIG. 102C) is likewise rendered TRUE. Consequently, in response to lines RAD and TS4 thus being rendered TRUE, a first "RAD" subcommand is thereafter executed, whereby the multiplicand stored in memory at the address specified by the contents of section 4 of the instruction register is read out and added to the contents of address-A. Upon completion of the first "RAD" subcommand, line DR (FIG. I02C) experiences a TRUE-to-FALSE reversal of state, so that the R-counter is decremented by a count of "1." If, after being decremented, the R-counter is still at a count other than "0," Jines RAD and TS4 remain TRUE, so that a second "RAD" subcommand is thereafter executed, whereby the multiplicand is again read out from the address in memory specified by the contents of section 4 206 o 10 15 20 25 30 35 40 45 50 55 GO r: 6v 70 75 of the instruction register and is added to the partial product stored in address-A. After the second "RAD" subcomm~lfld is completed, the R-counter is again decremented by a count of "1," and, if, after being decremented for the second time, the R-counter is still at a count other than "0," a third "RAD" subcommand is thereafter executed, and so on. However, when the R-counter has been decremented to a count of "0," so that line R¢ is rendered TRUE thereby, indicating that the partial product with respect to the first-order digit of the multiplier word has been derived and stored in address-A, the state of flipflop 6097 (FIG. 102A) is again reversed, so that line RAD is rendered FALSE thereby. As a result of Hne RAD thus being rendered FALSE, the state of flipflop 6101 is reversed, so that line SA is thereby rendered TRUE. In response to line SA thus being rendered TRUE, a "SA" subcommand is thereafter executed, whereby the partial product now stored in address-A is shifted to the right by one digital position in the same manner as previously described in detail. Upon completion of the previouslyinitiated "SA" subcommand, the state of flipflop 6101 is again reversed, so that line SA is rendered FALSE thereby. When line SA is thus rendered FALSE, the state of flipflop 6103 is reversed, so that line SB is thereby rendered TRUE. In response to line "SB" being rendered TRUE, a "SB" subcommand is thereafter exeouted, whereby the word stored in address-B is shifted to the right by one digital position, with the original first-order digit of the word in address-A being stored in the tenthorder digital position of address-B. Upon completion of the just-initiated "SB" subcommand, the state of flipflop 6103 is again reversed, so that line SB is rendered FALSE thereby. With reference to FIG. 102C, just prior to the completion of the previously-initiated "SB" subcommand, line AF experiences a TRUE-to-FALSE reversal of stntc when line EG is rendered FALSE; consequently, the F-counter is incremented from a connt of "0" to a count of "1." Thus with reference to FIG. 102A, as the F-counter is at a count other than "10," so that line (Fl1»' rem8ins TRUE, the state of flip-flop 6C66 is again reversed upon completion of the just-initiated "SB" subcommand, so that lines MJ and TS3 are both rendered TRUE for the second time. With reference to FIG. 102C, it is again to be noted that, due to the fact that the F-counter is now at a count of "1," line (IFD)', hence line RLM, is rendered TRUE only during the time the digit-counter is also at a count of "1"; otherwise, line RLM remains FALSE. As a result of lines MJ and TS3 again being rendered TRUE, a second "MJ" digit-cycle is thereafter executed, whereby the second-order digit of the multiplier word is read out from the address specified by section 3 of the instruction register and is thereafter stored in the R-Collnter. Thereafter, a succession of "RAD" SUbCOfl1mands is executed, whereby the multiplicand is added to the partial product now stored in address-A by the number of times equal to the digital value of the second-order multiplier digit stored in the R-counter. Thereafter, the twenty-digit word stored in combined addresses A and B is shifted to the right by one digital position in the same manner as just described. The above-de~cribed sequence of events is sequentially repeated until the tenth-order digit of the multiplier is stored in the R-counter, the mUltiplicand is again added to the contents of address-A by the number of times dictated by the digital value of the tenth-order multiplier digit, and the twenty-digit product stored in combined addresses A and B is shifted to the right for the tenth time by one digital position. As t!lC ]'<'-C0unter is now at a count of "10," as indicated by line FlO being rendered TRUE, the multiplication portion of the "MUS" instruction is now completed. During the next phase of the "MUS" instruction, a 3,112,391 207 succession of "SA" and "SB" subcommands is executed, whereby the twenty-digit product is shifted either to the right or to the left by the number of digital positions hdicuteJ by (he contents of section 2 of the instl-uction register, p.ll in esscntially the same manner as previously described in detail with respect to that portion of the precediw; d·~scr,iption entitled "Description of SHF Instruction" and also with respect to that portion of the preceding description rel<1ting to the "SA" and "SI3" subcomm8nds. With reference to FIG. 102B, if the state of line (OEM)' was previously rendered TRUE, indicating that the algebraic sign of the multiplier is negative, the stale of flipflop 6084 is reversed upon completion of the last "SB" subcommand, during which time lines Flq, and Rq, are both rendered TRUE. Consequently, the state of line CPM is rendered TRUE in order to effect complementing of the multiplier stored in memory at the <1ddre'ls specifioo by section 3 of the instruction register. However, if the algebraic sign of the multiplier is positive, the state of line (OBM)' thus being FALSE, a subsequently-initiated "CPM" subcammand is prevented. As shown in FIG. l02C, the state of flipflop 6lJ79 is reversed and line BM thereby rendered TRUE upon completion of the last-initiated "SB" subcommand, if the state of line 0111\,1 is TRUE, indicating that the algebraic sign of the multiplier is positive; otherwise, the state of flipflop 6079 remains unchanged and line BM thereby remains FALSE until the Iast-initbted "CP!'.!" subcommand is complctccl. However, when line BM is finally rendered TRUE due (0 a reversal of state of flipflop 6079, line TS4 is likewise rendered TRUE. In response to lines BM and TS4 thus being rendered TRUE, a "BM" word-cycle is thereafter executed, whereby the word is address-B is read out and stored in memory at the address specified by the contents of section 4 of the instruction register. Upon completion of the "BM" wordcycle, the state of flipflop 6079 is again reversed, so that line BM is rendered FALSE thereby. With reference to FIG. l02B, when line BM is thus rendered FALSE, the state of line PR8 is reversed from TRUE to FALSE, thus causing the R-countcr to be preset to a count of "R," so that line R8 is rendered TRUE thereby. If the state of line (OBN)' was previously rendered TRUE, indicating that the algebraic sign of the product is negative, the state of flipflop 6084 is reversed when line 13M is thus rendered FALSE, and, as a result, line CPM is rendered TRUE thereby. When line CPM is thus rendered TRUE, line TS4 (FIG. 102C) is likewise rendered TRUE. Thus, ~n ,:g~~f,;es~l~~~~~~~~r i:nt~:~~:f~e~n:X~~~~:~~d\~~~;; the product stored in memory at the address specified by the contents of section 4 of the instruction register is complemented thereby. Upon completion of the justinitiated "CPM" subcommand, the state of flipflop 6084 (FIG. l02B) is again reversed, so that line CPM is rendered FALSE thereby. As shown, the state of flip-flop 6107 is reversed and line STD rendered TRUE upon completion of the justinitiated "BM" subcommand if the state of line OBN i:, TRUE, indicating that the algebraic sign of the product is positive; otherwise, the state of flipflop 6107 is not so reversed, and line STD is thereby rendered TRUE until the previously-initiated "CPM" subcommand is completed. However, when line STD is finally rendered TRUE, line TS5 is likewise rendered TRUE. In response to lines STD and TS5 thus being rendered TRUE, a "STD" subinstruction is thereafter executed, whereby the contents of section 5 of the instruction register is stored in the word-selecting register, thus terminating the sequence of events initiated in accordance with the "MUS" instruction. 208 cxccutln2 a "hID])" in~;truction, the cod~ nUffiber "32" is effectively utilizcJ during the "shift prod~ict" pha:,'~ of tbe subprogram i:1stcad of the number stored in section 2 of the instruction register, as in the pr(,;viously-dcscri8e·J "MUS" instruction. Tn addition, in executing a "NIDD" instructio:l, the address in memory of the multiplier is specified by the contents of section 2 of the instructiol1 register instead of section 4, a:, in the ex~cution of the previously-described "MUS" instruction. Listed below in somewhat tabuiar form, and al;:o 10 graphically illustrated by the flow diagram of FIG. 107M, is a step-by-step description of the various previously described subinstructions to which the computer is sequentially responsive in executing a "MDD" instruction: 15 Step I Sul)in'ilrllCtian~ ~o ~~= MH-L=I~~~:-i~;:~~-i~'truc~;::-:ghte~~-I: next , in..;truct.ion \Yord store(L in at tit:] Hl':1I1')T.\' (·,0nt.'~nt.~ of UI" ~,Yl)n!­ ~i'Juct.inl~ regi,"t~r; tiI2n~Jf[('f. if t.f!1! eunh'llts of ;Y'clionl of til,,' h'llrudi.on r\';:;i~t\:f i-.: "U," l1ddn'''" "l1',ecil1r,t}by the gO to Stf:jl ~ of the? f\)l!o',\'itl~ "!l:I~lro:.;ram. Pre'.;et Uw F-eountt.'r to "0"; tilf"re.lfter. ~!o Stpp 3. Pr!'-.:ut. UlC ;H~q) 4 H~coutltc'r Co":'!~~'tIH; nc;xt ".\'orJ from lrWIll'lry itlJo 4 ______ i\.lA-3-IL_____ A. antI, to tD no"; nvr~~'lft"r, 'p:O to ~inluH~lrH~ou-"lv :VlI]C0:;"5th'~ tl1(!n'\\-ith. co:n; word uigit byui~it. int.o th~ ".1" dj~~it-relii ... tH. till' ~l(ldrt";1 of th'_' ncd, wr)r,l ill iK'iJl'~ ~~Iedfii'(i bv t11D instru-\:t.ioll ;;0 of ~)tejj 5 ______ OB on Mf~) .. 7-8" 6 ... ___ .,,J 7" ____ Pre:;et tllp -:::t:tte of ~r(4)-O~~L- .1 fiPA-O-L .... en -O-fL ______ 8 ______ 9______ A:'If-n-lO___ ___ -iO RS-l1"l~ 1IJ. ____ _._ StCT t:!. C·Jj)Y tile next ,"onI fr0m 1 ~IA--2··13____ 14 _____ 17 J9-S~7 _________ A D{l)-O-IB_ _ _ 18 19 HL:lf-3-20 ____ 211 _____ D9-17-:2L _____ 2L ____ H~~22--2L----- HAD-I-2:J 05 23 _____ DH.-O-21_____ 24 _____ 8A(:2)"-0-:2.3 ____ 25_ ____ S 13 (~~J--o-2i':' ___ 70 83. Detailed Description of MDD Illstmctiol1s A "MDD" instruction is essentially a special case of the just-described "MUS" instruction. For example, in 75 27 _____ 28___ 2i:L ___ "~"; (hC"fC-lHer gD to A, and, simultnllcDn ';..'oni dif!it hy digit into the ",)" dir,it-f('g'l'itl'r, the. addre::;s of thQ m~xt ,vord in me 1TIory Leill~ specified hy nh~ contcnt~ of ..:;eC'tion 2 of thc' instrnction rc;;i.3ter; therl'~lf!cr. ~o to Stc,) 13. I'r",et t.he ,talc Df line OBN TRL'E if the algebraic sign of t1((', 'vort! ju~t rt',:1.11 frotH llH'mory ('orre~ponds to the ~tate of line o !L\ll; ot.berwi.-.:e, JH'C':-et tiw ~bk' nf liuc OfL',I FALSE; thereLl.H{~r, go to ~~~tep 14. If the digit. stored in tIle ".1" dil!it. rt".;i~t('j i<; tl "'Y'. go to Stop 7; oUit:!",.. i~:e. !:u tl) :::,ttC';) S, Cle~lr addres~,-.A; nH~rl;,tfter. go to St(';, 10. Pn'''l'L t1w H.-couuter to '~O"; t1H.'reJft.er 1 go to SloP!) 17_ lw.:rpnlpnt the (il~jt·coant,-~r; UWTc'.lft,t'f, ~o to Skp IS. H tb(~ rli~lt star,;-Il in th{; the d i~~lt ~torcd in UH' Step 19; otnt'nvls(', go to Sec"" m thc' ({-co,,!,t"r U1:' po.~;t~on is sW~(~iflul 11:.' \rhost' :}ddn'ss In nwm0ry ('nllt~·llt..:; of su::t:Dn ;) oj" th"~ ~I~I n",I,:~,_ tl'r; then·aJt'.:r\ t~:O to c;t!'l1 :':'J. If (he t1j~~t~torlnt'r is at a lnt Df~s·A pb',c I.,) t~1e ri!.!;ht; th~·n':l~t·~'r. ~o to<) Sbp . Shift the wor~l u',ld r<"8:3-:~ one tl) the, r .';.'.11t; thl.'r(,~LfV"r, ~o t,:) .':It,~p 2(L ____ t.o ('o"!'rp'.;noilil to ml~m()ry int,Q :~ddrl's ,~ly there ,·;H.h. to;JY tlw CAn)-O-l~l ____ PR¢.-O-17 _____ GO the H-c.QulJter tu l're.,\~,t l:_L~ ___ 13 .... 013;-;1(4)-O-jL 55 liIH~ OB~1 the algl~l)t':lk :-;ign of th:_' ~.vonl ju ~t fl·:ld. frollt lWml.')ry; nF"n'~liter. t~n to H!.t·,> 6, lftbe ~tatp of line OlL\f ir, TRLT E) go to Strp R; otlwrwi~~l.'l go to 8te;J 7, COrnl>lcl11Pllt the '11'01.'11 ;-;torcd in alldn',3:i-;\; thereaftt'r. go t() St.e.) 8. Ckelf fhidre,;;-;··B; UJen.'~tftt'r. go to i,!pp 9. C()~)y the word stored ill [ludrl'::::s-A int,o mrrnory at the acldr('::-~s ~qre("if1('d hy '1Pction II of 1hi~ i~l"trlH.'j,ion Tl';~i'itf;'r, "ft" IX'in·'; a ",')" if tlI;~ H-{'ol1nt,",r i, :IL n C,)ll11f, of dO", and iwinrz a "4" if t1w H-cnuntc" i" 3t a cou.nt of ";>,,"; t.lJ:'rcH.~t('r. t:0 to 8,tep IlJ. If th':.1 R-COllutr,lr i:.:. at ~L ,'oiml of "~", ~o to .stt~P n; ot.1j(~r~.'d.,p. ~Q /0 :,[('iI 11. 11- .... I'll'i-O-rL .. _ 45 50 UlD conkntf' Dr fi.-'gi ,ter; tht'n..",.llcf, go to 5. 2iJ. Ar'-O-:?7 _______ 1 I~"'·n;nll'nt the F-cm_:mtl'r; thl"'r{;J[tl~r,:;o tD f:~tl'[} J li'1¢-l7-2~_~ __ If2~;i) F·{~Ol~ntrr is at a {,[)U;lt .of "lO"t ;~0 t'J I Stt"P Z~; oth'~f':'i-O-il ______ STD is thus rendered FALSE, line PR¢ is likewise renPreset the R-counter to "0"; thereafter, go to Step 3_ 3______ MA-3-4 _______ 10 dered FALSE, so that the R-counter is thereby oaused to Copy th~ word from memory into address-A, be preset to "0." und, s~n:nltun~o~sly therewith, eopy the word dlglt by dlgltmto the "J" digit-register, With reference to FIG. 103A, as the R-counter is now the address of the word in mern ory h'ing ,at a count of "0," so that line R¢ is TRUE, line TS3 specified by the contents of sectlon 3 of the instruction register; thereafter, go to Step 4. 4______ OBM(4)-O-5 __ is rendered TRUE as a result of line MA being rendered Preset the state of line OBM to correspond to the algebraic sign of the word just rend from 15 TRUE. Consequently, a first "MA" word-cycle is therenlClnory; thereafter, go to St~p 5. 0 ______ OBM(2)-6-7 __ after executed, whereby the divisor stored in memory at If the state of line OBlIt is 'l'RUE, go to Step the address specified by the contents of section 3 of the 7; otherwise, go to Step 6. 6 ______ CPA-O-L ____ Complelpent the word stored in address-A; instruction register is read out and stored in address-A_ thereafter, go to Step 7. 7______ R-14-8 _______ Simultaneously therewith, the divisor is copied digit by If the R-counter is at a count of 140," go to Step 8; otherwise, go to Step 14. 8______ CB--{'-9 _______ 20 digit into the "J" digit-register. Upon completion of the 9 ______ AM-4-10 ______ Clear address- B; the.reafter, go to Rtep 9. "MA" word-cycle, the state of flipflop 6091 (FIG. 103B) Copy the word stored in address-A into n'emory at the address specified by the contents is again reversed, so that line MA is rendered FALSE of the section 4 of the instruction register' thereby_ If upon completion of the "MA" word-cycle register; thereafter, go to Step 10. ' In _____ PR8-0-1!. ____ Preset the n-counter to a count of "8"; therethe algebraic sign of the divisor just read from memory after, go to Step 11. 11. ____ MA-2-12 ______ Copy the word stored in memory at the ad- 25 is negative, so that the tenth-order digit thereof stored in dress specified by the contents of section 2 of the "J" digit-register is a "9," the state of line OBM retpe instruction register into address-A, and, mains FALSE. However, if the tenth-order digit of the sl~lnltaneo~sly therewith, COpy the word digit by dlglt into the "J" digit-register; divisor now stored in the "J" digit-register has a value thereafter, go to Step 12. l L ___ OBN(4)-0-13 __ Preset the state of line OBN TRUE if the other than "9," the state of flipflop 6095 is reversed on algebraic sign of tbe word just read from memory ('orresponds to the state of ]ine 30 completion of the "MA" word-cycle, and line OBM is thereby rendered TRUE. Thus, it is evident, the state of OBM; otherwise, preset the state of line OBN FALSE; tbereafter, go to Step 13. 13 _____ J9-14-G.. _____ _ line OBM is rendered TRUE if the algebraic sign of the Il the digit stored in the" J,e digit-register is a divisor is positive and is rendered FALSE if the algebraic "9," go to Step 6; otherwise, go to Step 14. 14_____ RSB-4-15 ____ _ Subtract the word stored in memory at the sign of the divisor is negative. address specified by the contents of section 4 of tbe instruction reg!,ter from the word 35 If the algebraic sign of the divisor just read from memstored in address-A; then'after, gO to Step 15. 15 _____ EAS-17-16 ____ ory is negative, so that line J9 is TRUE, the state of flipIf the Blge bralc sign of the differenee is pod live, go to Step 16; otherw!'e, go to Step 17. flop 60-8.3 is reversed upon completion of the previously16 _____ DAD-o-I4. ___ Add the constant 0000000001 to the word stored initiated "MA" word-cycle, and line CPA is thereby renin address-B; thereafter, go to Step 14. 11.. ___ RAD-4-18 ____ Add tbe word stored In memory at the address dered TRUE. In response to line CPA thus being renspecified by the contents of section 4 of the !nstmction register to the word stored in 40 dered TRUE, a "CPA" subcommand is thereafter exeaddress-A; thereafter, go to Step 18. cuted, whereby the divisor now stored in address-A is 18 _____ DR-o-19 ______ Decrement the H-connter; thereafter, go to read out and complemented, and its absolute negative Step 19. 19 _____ R-20-22.. ____ If the R-counter is at a count of "0 " go to value thereafter stored back in address-A, Upon comStep 22; otherWise, go to Step 20. ' 20 _____ SA(I)-o-ZL __ pletion of the "CPA" subcommand, the state of flipflop Shift the word stored in address-A one digital posiUon to the left; thereafter, go to "trp 21. 45 6083 is again reversed, and line CPA is thereby rendered 21. ____ SB(l)-O-lL __ Shift the word stored in address-B one digital FALSE, It is evident, therefore, that the state of flipflop position to the left; thereafter, go 10 81.<'p 14. 22 _____ BM-4-23.. ____ Copy the word of address-B into m(mory at 6681 is reversed and line CB thereby rendered TRUE, the address specified by the contents of scceither upon completion of the "MA" word-cycle, if the tlon 4 of the Instruction register; thereafter, go to Step 23. 23 _____ OBN (1)-24-25_ algebraic sign of the divisor is positive, or upon compleIf tho stato of line OBr\ is TUUE go to Step 50 tion of the "CPA" subcommand if the algebraic sign of 25; otherwise, go to Step 24. ' 24 _____ CPM-4-25.. __ Complement t.he word stored in memory at the the divisor is negative. In either event, as a result of line address speClfied by the contents of section 4 CB thus being rendered TRUE, a "CB" word-cycle is of the instruction register; thereafter, go to Step 25. thereafter executed, whereby a word of all zeros is stored 25_____ STD-5-* _____ _ Copy the contents of soet Ion 5 of the Imtruction in address-B. Upon completion of the "CB" word-cycle, register into the word-sdecting regbter. 55 the state of flipflop 608,1 is again reversed, so that line CB is thereby rendered FALSE, With reference to FIG. 103A, the state of flipflop 6077 ..l!pon :omr,letion of the execution of the previously is reversed as a result of line CB thus being rendered InItiated MI word-cycle, during which time the next FALSE, and line Al\'1 is rendered TRUE thereby. When 5nstruction word is read out from the particular address in I?emory specified by the contents of the word-selecting 60 line AM is rendered TRUE, line TS4 is likewise rendered TRUE. Consequently, in response to lines AM and TS4 :egIster .and thereafter stored in the instruction register, being rendered TRUE, an "AM" word-cycle is thereafter If the contents of section 1 of the instruction register executed, whereby the divisor now stored in address-A is thereafter corresponds to the code designation for.a "DIY" read out and stored in memory at the address specified instmction (i.e_ '~14"), the state of line DIY is rendered TRUE in the manner previously described with respect to 65 by the contents of section 4 of the instruction register. Upon completion of the "AM" word-cycle, the state of FIG. 56, and, as a result, a "DIY" instruction is thereafter executed in the following manner: flipflop 6677 is again reversed, so that line AM is rendered FALSE thereby, With reference to FIGS, 103A and 103B, there is illusWhen line AM is thus rendered FALSE, line PR8 trated therein a composite logic.al diagram of particular portions of the computer circuit utilized in executing a 70 (FIG. 103B) is likewise rendered FALSE and thereby causes the R-counter to be preset to a count of "8_" "DIY" instruction, With particular reference to FIG. 103B, at TIME-1 after line MI is rendered TRUE at the Also, the state of flipflop 6091 is again reversed as a rebeginning of the previously-initiated "MI" word-cycle, the sult of line AM thus being rendered FALSE, and line states of f1ipflops 6696 are reversed, so that lines OBM MA is again rendered TRUE thereby. As the R-counter and OBN are respectively rendered FALSE thereby. Upon 75 is now at a count of "8," s·o that line R8 is TRUE, line H 3,112,394 213 TSZ (FIG. 103A) is likewise rendered TRUE as a result of line MA being rendered TRUE. In response to lines MA and TSZ thus being rendered TRUE, a second "AM" word-cycle is thereafter executed, whereby the dividend stored in memory at the address specified by the contents of section 2 of the instruction register is read out and stored in address-A; simultaneously therewith, the dividend is copied digit by digit into the "J" digit-register. Upon completion of the second "MA" word-cycle, the state of flipflop 6091 (FIG. 103B) is again reversed, so that line MA is rendered FALSE thereby. If upon completion of the "MA" word-cycle the algebraic sign of the dividend, as indicated by the states of lines J9 and (J9)', corresponds to the algebraic sign of the divisor, as indicated by the states of lines OBM and (Omvl)', the state of flipflop 6096 is reversed, so that line OBN is rendered TRUE thereby. However, if the algebraic signs of the dividend and of the divisor are of opposite signs, the state of line OBN remains FALSE. Thus it is evident that the state of line OBN is rendered TRUE if the algebraic sign of the dividend corresponds to the algebraic sign of the divisor, and is rendered FALSE if the algebraic sign of the dividend does not correspond to the algebraic sign of the divisor. Also, if the algebraic sign of the dividend just read from memory is negative, so that line J9 is rendered TRUE, the state of flipflop 6083 is reversed upon completion of the previously-initiated "MA" wordcycle, and line CPA is thereby rendered TRUE. As previously described, when line CPA is rendered TRUE, a "CPA" subcommand is thereafter executed, whereby the word stored in address-A is read out and complemented, and its absolute value is thereafter stored back in address-A. Upon completion of the "CPA" subcommand t,he state of flipflop 6083 is again reversed, and line CPA is thereby rendered FALSE. It is evident, therefore, that the state of flipflop 6081 is reversed and line CB thereby rendered TRUE, either upon completion of the secondly-initiated "MA" word-cycle, if the algebraic sign of the dividend is positive, or upon completion of the previously-initiated "CPA" subcommand if the algebraic sign of the dividend is negative. In either event, when line CB is finally rendered TRUE, a "CB" word-cycle is thereafter executed, whereby a word of all zeros is stored in address-B. Upon completion of the "CB" word-cycle, the state of flipflop 6081 is again reversed, so that line CB is thereby rendered FALSE. With reference to FIG. 103A, the state of flipflop 6100 is reversed as a result of line CB thus being rendered FALSE, and, as a result, line RSB is thereby rendered TRUE. When line RSB is thus rendered TRUE, line TS4 is likewise rendered TRUE. Consequently, in response to lines RSB and TS4 thus being rendered TRUE, a "RSB" subcommand is thereby executed, whereby the divisor stored in memory at the address specified by the contents of section 4 of the instruction register is read out and subtracted from the contents of address-A. Upon completion of the "RSB" subcommand, the state of flipflop 6100 is again reversed, so that line RSB is thereby rendered FALSE. As previously described in detail with respect to that portion of the adder-su btractor circuitry shown in FIG. 54, decimal·carry output line EAS is rendered TRUE upon completion of the "RSB" subcommand if the algebraic sign of the remainder is negative; however, if the algebraic sign of the remainder is positive, line EAS is rendered FALSE. If it be assumed that the algebraic sign of the remainder now in address-A is positive, so that line (EAS), is TRUE, the state of flipflop 6085 (FIG. 103A) is reversed upon completion of the previously-initiated "RSB" subcommand, and line DAD is thereby rendered TRUE. When line DAD is thus rendered TRUE, a "DAD" sub. command is thereafter executed, whereby the constant 0000000001 is added to the word now stored in address-B which, in this instance, is a word of all zeros. Upon com~ 214 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 pletion of the "DAD" subcommand, the state of flipflop 6085 is again reversed, so that line DAD is rendered FALSE thereby. As a result of line DAD thus being rendered FALSE, the state of flipflop 6100 is again reversed, so that line RSB is rendered TRUE for the second time. Consequently, a second "RSB" subcommand is thereafter executed, whereby the divisor stored in memory at the address specified by the contents of section 4 of the instruction register is again subtracted from the contents of the address-A. Thereafter, the state of flipflop 6100 is again reversed, so that line RSB is rendered FALSE thereby. When line RSB is thus rendered FALSE, the state of flipflop 6085 is again reversed, so that line DAD is rendered TRUE for the second time, provided that the algebraic sign of the difference now in addrcss-A is still positive. However, if it be assumed that the algebraic sign of the difference is now negative, so that line (EAS)' is rendered FALSE, the state of flipflop 6085 is thereafter preVented from being reversed, and, consequently, line DAD remains FALSE. Therefore, as it has been assumed that the algebraic sign of the remainder is now negatiVe, so that line EAS is rendered TRUE, the state of flipflop 6097 is reversed upon completion of the previously-initiated "RSB" subcommand, and, as a result, line RAD is rendered TRUE thereby. It is evident, therefore, that the subtraction operation is continued until line EAS is rendered TRUE, indicating that the algebraic sign of the remainder is negative. Howevcr, when line RAD is thus rendered TRUE, line TS4 is likewise rendered TRUE. Consequently, a URAD" subcommand is thereafter executed, whereby the divisor stored in memory at the address specified by the contents of section 4 of the instruction register is added to the contents of address-A, which is thereafter storing a remainder whose algebraic sign is now positive; i.e., greater than "0." Just prior to completion of the "RAD" subcommand, the state of line DR (FIG. 103B) experiences a TRUE-to-F ALSE reversal of state and thereby causes the R-counter to be decremented from a count of "8" to a count of "7." Upon completion of the previouslyinitiated "RAD" subcommand, the state of flipflop 6097 (FIG. l03A) is again reversed, so that line RAD is thus rendered FALSE. As the R-counter is now at a count other than "0," so that line (Rot»' is rendered TRUE, the slate of flipflop 6101 is reversed when line RAD is thus rendered FALSE, and, consequently, line SA is rendered TRUE thereby. In response to line SA thus being rendered TRUE, a "SA" subcommand is thereafter executed, whereby the remainder stored in address-A is shifted to the left by one digital position. Thereafter, the state of fliptlop 6101 is again reversed, so that line SA is rendered FALSE thereby. When line SA is thus rendered FALSE, the state of flipflop 6103 is reversed and line SB rendered TRUE thereby. In response to line SB being rendered TRUE, a "SB" subcommand is thereafter executed, whereby the partial quotient stored in address-B is also shifted to the left by one digital position. Upon completion of the just-initiated "SB" subcommand, the state of flipflop 6103 is again reversed, and line SB is rendered FALSE thereby. As a result of line SB thus being rendered FALSE, the state of flipflop 6100 is again reversed, so that lines RSB and TS4 are again rendered TRUE. Consequently a "RSB" subcommand is thereafter executed, whereby the divisor stored in memory at the address specified by section 4 of the instruction register is subtracted from the shifted remainder now stored in address-A. Thereafter, a succession of "RSB" sub commands is executed until the remainder stored in address-A has been reduced to zero or .until. the algebraic sign thereof becomes negative, at whIch ttme the states of flipflops 6097 and 6100 are both reversed, so that lines RAD and RSB are thereby rendered TRUE and FALSE, respectively. In response to lines RAD and TS4 now being TRUE, a "RAD" subcommand is thereafter executed, whereby the divisor 3,112,394 215 stored in memory at the address specified by section 4 of the instruction register is added to the remainder stored in address-A. Thereafter, a "SA" subcommand followed by a "SB" subcommand is sequentially executed, whereby the words stored in addresses A and B are both shifted one digital position to the left. As shown in FIG. 103B, just prior to the completion of the "RAD" subcommand, the state of line DR experiences a TRUE-to-FALSE reversal of state and thereby causes the R-counter to be decremented from a count of "7" to a count of "6." The above-described sequence of subtraction operations is sequentially repeated until the R-counter is decremented from a count of "I" to a count of "0." Upon completion of the last-initiated "RAD" subcommand, after the R-counter reaches a count of zero, as indicated by line R.p being rendered TRUE, the state of flipflop 6079 is reversed, so that lines BM and TS4 are both rendered TRUE. In response to lines BM and TS4 thus being rendered TRUE, a "BM" word-cycle is thereafter executed, whereby the word stored in address-B is read out and stored in memory at the address specified by the contents of section 4 of the instruction register. Upon completion of the "BM" word-cycle, the state of flipflop 6079 is again reversed, so that line BM is rendered FALSE thereby. With reference to FIG. 103B, when line BM is reversed from TRUE to FALSE, the state of line PRS is likewise reversed from TRUE to FALSE, and, as a result, the R-counter is again preset to a count of "8," so that line RS is rendered TRUE thereby. If it is assumed that line (OBN)' was previously rendered TRUE, indicating that the algebraic sign of the quotient is negative, the state of flipflop 6084 is reversed upon completion of the previously-initiated "BM" word-cycle, and line CPM is rendered TRUE thereby. As line CPM is thus rendered TRUE, line TS4 (FIG. 103A) remains TRUE. Thus, in response to lines CPM and TS4 being TRUE, a "CPM" subcommand is thereafter executed, whereby the quotient now stored in memory at the address specified by the contents of section 4 of the instruction register is read out and complemented, and the complement thereof stored in the memory address specified by section 4 of the instruction register. Upon completion of the just-initiated "CPM" subcommand, the state of flipflop 6084 is again reversed, so that lines CPM and TS4 are both rendered FALSE thereby. As shown in FIG. 103B, if the state of line OBN is TRUE, indicating that the algebraic sign of the quotient is positive, the state of flipflop 6107 is reversed, and line SID is thereby rendered TRUE upon completion of the previously-initiated "BM" subcommand; otherwise, the state of flipflop 6107 is not so revel'sed until the previously initiated "CPM" subcommand is completed. However, when line STD is finally rendered TRUE, line TSS is likewise rendered TRUE. Consequently, a "STD" subinstruction is thereafter executed, whereby the contents of section 5 of the instruction register is stored in the word-selecting register, thus terminating the sequence of events initiated in response to a "DIY" instruction. 85. Detailed Description of CFM Instructiolls 216 register, the address of the next instruction word is that which is specified by section 5 of the instruction register. Listed below in somewhat tabular form, and also graphically illustrated by the flow diagram of FIG. [) 107Q, is a step-by-step description of the various previously-described subinstructions to which the computer is sequentially responsive in executing a "CFM" instruction: 10 Step Suhint the ,tuto of line OIlN T]{UE j[ the alge' braic si~n of the woru just read from memory corresponds t·o the state of line OHM; otherwise, preset tho st,;te of line OIlN FALSE; therearter, go to Step 6. If the state of line OliN is Til DE, go to Step 7; otherwise, 12:0 to Stpp 9. Suhtract the word stored in m~.lmory FIt the ndd~'css specified by the contents of ~cction 3 of thl~ instrnction rogister (nun the. \v()rd stored in address-A; thereaft('r, gO to Step 8. If tilt' a\gehruic Sign of the dUft'rence is positive, go to Step 10: otherwise, go to Step 11. If the sbte of line OIl:\1 is TUDE, go to Step 10; othenvise, go to Stpp 11. Co;>y the eontl'l1t3 of seetioll ,I of the instruction regist:..'r into tlH~ wonl-splf'(,tin~ register. Copy the contents of section 5 of the instruc:tion register into the word-selecting register. 40 45 50 53 60 During the execution of a "CFM" instruction, the values of the two words stored in memory at the addresses specified by the contents of sections 2 and 3 of the instruction register are compared with each other. G3 If the value of the word stored in memory at the address specified by section 2 of the instruction register is equal to or larger than the value of the word stored in memory at the addre'ss specified by section 3 of the instruction register, the address of the next instmction word is spec- 70 ified by section 4 of the instruction register. However, if the absolute value of the word stored in memory at the address specified by section 2 of the instruction register is less than the value of the word stored in memory at the addre's8 specified by section 3 of the instruction 75 Upon completion of the execution of the previously initiated "MI" word-cycle, during which time the next insruotion word is read out from the particular address in memory specified by the contents of the word-selecting register and thereafter stored in the instruction register, if the contents of section 1 of the instruction register thereafter corresponds to the code designation for a "CFM" instruction (i.e., "15"), the state of line CFM is rendered TRUE in the manner previously described with respect to FIG. 56, and, as a result, a "CFM" instruction is thereafter executed in the following manner: With reference to the composite logical diagram shown in FIG. 104, at TIME-l after line MI is rendered TRUE at the beginning of the previously-initiated "MI" wordcycle, the states of flipflops 6095 and 6096 are reversed, so that lines OBM and aEN are respectively rendered FALSE thereby. When line MIN is subsequently rendered FALSE upon completion of the previously-initiated "Ml" word-cycle, the state of flipflop 6091 is reversed, and line MA is thereby rendered TRUE. When line MA is thus rendered TRUE, line TS2 is likewise rendered TRUE. Consequently, a "MA" word-cycle is thereafter exeouted whereby the word stored in memory at the addres·s specified by section 2 of the instru,tion register is read out and stored in address-A; simultaneously therewith, the word being read out from memory is copied digit by digit into the "J" digit-register. Upon completion of the "MA" word-cycle, if the tenth-order digit of the word just read out from memory is a "9," indicating that the algebraic sign of the word is negative, the state of line OEM remains FALSE, indicative of the negative algebraic sign of the word just read from memory. However, if the algebraic sign of the word just read from memory is positive, so that line (19)' is TRUE, the state 3,112,394 217 218 of flipflop 6095 is reversed just prior to completion of ever, if line (PCI)' is rendered TRUE simultaneously the previously-initiated "MA" word-cycle, so that line with line STD, line TS4 is rendered TRUE in order OBM is rendered TRUE, indicating that the algebraic to effect the storage of the contents of section 4 of the sign of the word just read from memory is positive. instruction register into the word-selecting register. Upon completion of the previously-initiated "MA" 5 86. Detailed Description of CFE Instructions word-cycle, as indicated by line J'viA being rendered During the execution of a "CFE" instruction, the two FALSE, the state of flipflop 6066 is reversed, and lines words stored in memory at the addresses specified by the MI and TS3 are both rendered TRUE thereby. Consecontents of sections 2 and 3 of the instruction register quently a "MI" word-cycle is thereafter executed, whereby the word stored in memory at the address specified 10 are first compared for equality. Thereafter, if the values of the two words are of equal magnitude, the contents by section 3 of the instruction register is read out and of section 5 of the instruction register is thereafter stored copied digit by digit into the "I" digit-register. Again, into the word-selecting ,register; however, if the values if the tenth-order digit of the word just read from memof the two ,words are of unequal magnitudes, the contents ory and copied digit by digit into the "I" digit-register is a "9," indicating that the algebraic sign of the word is 15 of section 4 of the instruction register is stored into the word-selecting register. negative, the state of line J9 is rendered TRUE; otherListed below in somewhat tabular form, and also wise, line (11), is rendered TRUE. Therefore, if the graphically illustrated by the flow diagram of ,FIG. 107R, algebraic signs of the two words just read from memory is a step-by-step description of the various previously deare the same, the state of flipflop 6096 is reversed upon completion of the previously-initiated "MJ" word-cycle, 20 scribed subinstructions to which the computer is sequentially responsive in executing a "CFE" instruction: and, as a result, line OBN is rendered TRUE thereby. However, if the algebraic signs of the two words just read from memory are opposite, the state of line OBN SuhinstrucDescription tions remains FALSE. If it is assumed ,that the algebraic signs of the two words stored in memory at the addresses 25 i\U-D-L ____ _ Copy into tl1C' instruction fogister the nrxt in~ specified by sections 2 and 3 of the instruction register structioil ",;,-on1 stored in memory at the are of opposite signs, so that line (OBN)' is rendered address speeitlcd hy the contents of the ,\'Ord· re~:d::;ter; tllC'reafter, if ttl(' ('ontt'nts of se1ecting TRUE, the state of flipflop 6107 is reversed upon comsectiotl 1 of thn instrudioll reg'i::;.t(>l' is "Hi,'~ pletion of the previously-initiated "MJ" word-cycle, and, go to Step 2 in the (allowin!!: suh;)fogrnm. 2 _____ _ MA-3-3 ______ _ Cl)PY the 11C"\t \yord from Bl('lIlory into addn'~~~ as a result, line STD is rendered TRUE thereby. When 30 A~ and ~,illmlLuwously tlWI',''\,1, idl copy the line STD is thus rendered TRUE, line TS4 is rendered word (ligit 1)),' digit 11110 tJll'~ 'J" lligit-rrgi:"trr, tllr from the adder-subtracter is rendered FALSE if the remainder resulting from a subtraction operation is zero; otherwise, line ZN is rendered TRUE Therefore, if it is assumed that the value of the word stored in address-A and the value of the word stored in memory at the address specified by section 3 of the instruction register are of unequal magnitudes, so that line ZN is rendered TRUE upon completion of the "RSB" subcommand, the state of flipflop 6096 is reversed, and line OBN is rendered TRUE thereby. Also, when line RSB is thus rendered FALSE, the state of flipflop 6107 is reversed, so that line STD is rendered TRUE thereby. In response ,to lines STD and OBN simultaneously being TRUE, line TS4 is likewise rendered TRUE. Consequently, a "STD" subinstruction is thereafter executed, whereby the contents of section 4 of the instruction register is stored in the word-selecting register. However, if it is assumed that the values of the two words stored in memory at the addresses specified by sections 2 and 3 of the instruction register are of equal magnitudes, as indicated by line ZN being rendered FALSE, the state of line OBN rema,ins FALSE upon completion of the previously-initiated "RSB" subcommand. Consequently, when line STD is rendered TRUE simultaneously with line (OBN)', the state of line TS5 is likewise rendered TRUE. Consequently, a "STD" subinstruction is thereafter executed whereby the contents of section 5 of the instruction register is stored in the word-selecting register. 87. Detailed Description of EPT instructions By means of the execution of but a single "EPT" instruction, from one to one hundred words read from punched paper tape are stored in sequentiaUy-numbered addresses in memory. During the first phase of the "EPT' subprogram, the paper tape is caused to be translated in a forward direction, during which time data information is read therefrom ,if the value of the low-order digit of section 2 of the instruc,tion register is a "0"; bowever, if the low-order digit is a "1," the paper tape is caused to be translated in a reverse direction (i.e., rewound), during which time only symbol information is read therefrom. As ,previously described with respeot to FIG. 88C, the total number of words read from the paper tape, to be subsequently stored ,in sequentially-numbered addresses in memory,is determined by the number of ten-digit words punched in the paper tape between "end-of-frame" (EOF) or "alternate-instruction" (AI) symbols. That is, the words sequentially read from the tape are stored in sequentially numbered addresses in memory until either an HEOF" symbol or an "AI" symbol is detected. When an "EOF" symbol is detected, zeros are automatically stored in ,the remaining higher-order digital positions of the last address, and the computer thereafter proceeds to carry out the dictates of the next instruc60n word stored in memory at the address specified by the contents of section 5 of the instruction register. During the tapereading operation, the first digit read from the tape is stored in the first-order digital position of the address in memory specified by the contents of section 3 of the instruction register; the next digit read is stored in the second-order digital position thereof; and so on, until the address specified by the contents of section 3 of the instruction register ,is completely filled. Thereafter, section 3 of the instruction register is incremented by a count of "1," and the next ten digits read from the tape are stored in the next-higher-orderaddress in memory, the above-described sequence of events being sequentially repeated until an "EOF" symbol is detected. However, when an "alternate-instruction" (AI) symbol is detected, zeros are first stored in any remaining digital positions of the last operable address when tbe "AI" symbol is first detected, and, immediatelythcreafter, the computer proceeds to carry out the dictates of the next instruction word stored in memory at the address specified by the contents of section 4 of the instruction register. If, however, the digit stored in the low-order digital position of section 2 of the instruction register is a "1" instead 10 of a "0," the paper tape is caused to be translated in a reverse direction until an alternate-instruction symbol is detected, at which time the tape is brought to a standstill, and the computer immediately proceeds to carry out the dictates of the next instruction word stored 1n memory 15 at the address specified by the contents of section 5 of the instruction register. Listed below in somewhat tabular form, and also graphically illustrated by the flow diagram of FIG. 107S, is a step-by-step description of the various previously de20 scribed subinstructions to which the computer is sequentially responsive in executing a "EPT" instruction: Step Subinstructions Description 25 L ____ _ 1\1 I -0-2 _______ _ CntrY int.o thn im;frllction register the TIrxt 30 2 ______ L¢-4-3 _______ _ instructiun word SlOft'd in TIlemory at the "cldress speril",cI by the contents of the wordst'leding rl'gish',r; tllcfC'aftrf, if the conlpnts of section 1 of the instfuC'Holl rcgist('1' is oj 17," go to Step 2 in the fol1o\virlg subprogr:1.ITl. If tho lov,:-ordeT digit storNl in ~pdion 2 of the iu:>lruc1ion fl·gistcr is a "0," go to Stev 3; 3 ______ l'TFO-6 _____ _ 4- _____ LI~O-5 35 L ___ _ 0______ 7 ______ 40 8 ______ 9 ______ 10 _____ 4:3 Tnltl~jat(' the pap!'f t.ap{' in a fonvurd rlircctfon; UlL'rt.'ufter, go to Stl:'P 6. _______ _ If the low-order digit stored in section 2 of the PTn-O~6 _____ _ 00 the paper tave ill u reverse direction; tlll·n·dh.'r, go to Step (i. _____ _ Whon the output of the [laper tape clark is H'nden'd TRliE, go to Step 7. EOF~9-8 _____ _ I( the digit just read from the IJlmchcd pUllt'r tape is an end~of fralne synlbol, go to Stepl:S; othcrwtoe, go to S("p 9. PTB-o~18 ____ _ Stop the paper tape; thereafter, go to Step 18. TCL~O-lO ____ _ Wben the output of the paper tape clock is rendered TRUE, go to Step 10. A1~12~lL ____ _ 12 _____ L¢~5~13_. ____ _ 13 _____ TDA~G_1L __ _ 14_____ AD(I)-O~15 __ _ 16 _____ DD~G~lL 17 _____ 1::-14-0_0.. ____ _ 18 _____ D9~20_19.. ____ _ ___ _ 19..___ 013::\l(2)~ 20 _____ AlJ(I)~O~21. 21.____ ROS~3~18 22_____ STD~5-' Of> 23_____ in,c.;trnction register is a' ~ 1," go to StE'P 5. rr~ranslalc TCL~O-7 50 55 otlwr\\ L-K" go to St('-p 4. 22~23. __ ____ _ _____ _ STD~4~· _____ _ rr the digit just read from the paper tape is an alternate-instruction symbol, go to Step 11; otherwise, go to Step 12. Preset the state of line 013111 'fRUE; thereafter, go to Step 8. If tbe low-order digit of section 2 of tbe instruction fPgist('r is a uO," gO to Step 13; otberwise, go to Step 6. U the character just read from the paper tape is a data digit, go to Step 14; otherwise, go to Step 6. Incrument the digit-counter; thereafter, go to Step 15. Store the data digit jllilt read from the paper tapc into the nex thigber order digital position of tbe memory address speeified by the contents of section 3 of tbe instruction register; thereafter, go to Step 10. rr the digit-counter is at a count of "9," gO to Step 17; otherwise, go to Step 6. 1nerell'ent section 3 of the instruction register; thereaftrr, go to Step 6. If the digit-counter is at a count of "9," go to Step IY; otherwise, go to Step 20. If thc state of line OBIIl is 'l'HUE, go to Step 23; otherwise, go to Step 22. Increment the digit-counter; thercafter, go to Step 21. Store a zero in tbe memory address spe.cifled by the contents of section 3 of tbe instruction register, the digital position being indicated by the count of the digit-counter; thereafter, go to Step 18. Copy the contents of scction 5 of the instruction register into the word-seJecting register. Copy the contents of section 4 of the instruction r('gister into the word-selecting register. Upon completion of the execution of the previously initiated "MI" word-cycle, during which time the next in70 struction word is read out from the particular address in memory specified by the contents of the word-selecting register and stored in the instruction register, if the contents of section 1 of the instruction register thereafter corresponds to the code designation for an "EPT" instruction 75 (i.e., "17"), the state of line EPT is rendered TRUE in 3,112,394 221 the manner previously described with respect to FIG. 56, and, as an result, a "EPT" instruction is thereafter executed in the following manner. It is to be noted at the outset, howevcr, that the particular sequence of operations carried out during the execution of an "EPT" instruction is dependent, not only upon the contents of section 2 of the instruction register, but also upon the condition of the paper-tape reader when the "EPT" instruction is first initiated, as previously described with respect to that portion of the preceding description relating to the format of an "EPT" instruction word. For example, a different sequence of operations is executed when the "EPT" instruction is first initiated if the contents of section 2 of the instruction register is "00" and a data digit is positioned over the tape reading head; if the contents of section 2 is "00" and an "alternate-instruction" symbol digit is positioned over the reading head; if the contents of section 2 is "00" and an "end-of-frame" symbol digit is positioned over the reading head; if the contents of section 2 is "01" and an "end-of-frame" symbol digit is positioned over the reading head; or if lh~ tape unit is in a rewinding cycle of operation. Reference is now made to FIGS. 106A and 10GB, wherein there is illustrated a composite logical diagram of particular portions of the computer circuitry utilized in executing an "EPT" instruction, and additional reference is 'also made to FIG. 88C, wherein a fragmentary portion of the particular perforated tape utilized by a conventional paper-tape reader is diagrammatically illustrated. It is again to be noted that the particular paper-tapereading mechanism utilized by the present computer is a well-known photo-electric type, commercially available as Model No. 903, at present manufactured by Potter Instrument Company, Inc. The circuitry contained within the paper-tape reader is conventionally connected in such a way that lines Ta through Td are respectively rendered TRUE during a reading operation in response to a perforation located in a corresponding one of data channels # 1 through #4; line TDA is rendered TRUE in response to a lack of a perforation in channel #6, indicating the presence of a data digit over the reading head; line EOF is rendered TRUE in response to a perforation located in channel #8; line AI is rendered TRUE in response to a perforation located in channel #7; line TCL is rendered TRUE when a perforation is sensed in clock channel CLK; and line REW is rendered TRUE each time the tape unit is in a rewinding cycle of operation. At the first TIME-l after the "EPT" instruction is initiated, the state of flipflop 6061 is reversed, and line TH is thereby rendered TRUE; at the second TIME-I, the state of flipflop 6061 is again reversed, and line TH is thereby rendered FALSE; at the third TIME-l the state flipflop 6061 is aagin reversed, so that line TH is thereby rendered TRUE; and so on. Each time line TH is rendered TRUE, lines TSJ and JM are likewise rendered TRUE. Therefore, if it is now assumed that "00" is stored in section 2 of the instruction register and that one of the data digits "0" through "9" is positioned over the reading head when the "EPT" instruction is first initiated, the output of gate 1570 experiences a TRUE-to-FALSE reversal of state upon completion of the previously-initiated "MI" word-cycle when line MIN is thereafter rendered FALSE. As a result, the state of flipflop 6087 is reversed, so that line GC is rendered TRUE thereby. However, approximately forty microseconds later, at TIME-I, the state of flipflop 6087 is reversed by gate 1571, so that line GC is rendered FALSE thereby. Also, when line MIN is rendered FALSE upon completion of the previously-initiated "MI" word-cycle, the state of flipflop 6098 is reversed, so that line ROS is thereby rendered TRUE. After line ROS is rendered TRUE, the state of flipflop 6061 is reversed when line GC is rendered FALSE, and, as a result, line TH is rendered TRUE thereby and remains TRUE for a period of approximately two hundred microseconds, at which time the state of 222 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 flipflop 6061 is again reversed, so that line TH is thereby rendered FALSE. As shown in FIG. 61, the state of line AD is rendered FALSE at TIME-3 after line TH is rendered TRUE, and thereby causes the digit-counter to be incremented from a count of "9" to a count of "0." During the two hundred-microsecond interval during which time line TH is TRUE, line MXW (FIG. 60) is rendered TRUE each time the binary bit indicating output of the serializer is indicative of a binary "I" as evidenced by line TDS being rendered TRUE. Consequently, in response to lines TSJ and 1M both being rendered TRUE when TH is rendered TRUE, a "1M" digit-cycle is initiated, so that the data digit read from the tape is thereafter stored directly into memory at the first-order digital position of the address indicated by the contents of section 3 of the instruction register. Thereafter, the state of flipflop 6061 (FIG. l06A) is reversed and lines TH, TS3, and 1M are rendered FALSE thereby. It is to be noted that, even though line JM is thus rendered TRUE, any digit previously stored in the "J" digitregister is not stored in memory in the normal manner via the "1M" digit-cycle, due to the fact that the output of gate 1090 is rendered FALSE all during the execution of an "EPT" instruction. Consequently, line JM is rendered TRUE only to cause a digit cycle to be initiated, so that the digit read from the tape is directly stored in memory via gate 1092, which is controlled by the "EPT" instruction. It is also to be noted that, even though lines PTF and PTS are rendered TRUE and FALSE, respectively, when line ROS is rendered TRUE, thus releasing the tapebraking mechanism and thereby permitting the tape to thereafter be translated in a forward direction at constant velocity, sufficient time elapses before the tape actually begins to move, due to the inertia of the moving parts of the tape reader, to thus allow the data digit initially positioned over the reading head to be read and thereafter stored in the designated address in memory before being moved away from the reading head. However, when the tape is translated in a forward direction (0 the point where the second-order digit is positioned over the reading head, line (TCL)' from the clock channel output circuitry experiences a TRUE-ta-FALSE reversal of state. As a result, the state of flipflop 6087 is reversed due to a reversal of state of the output of gate 1569, and line GC is again rendered TRUE thereby. At TIME-l thereafter, the state of flipflop 6087 is again reversed, and line GC is rendered FALSE. When line GC is thus rendered FALSE, the state of flipflop 6061 is again reversed and line TH thereafter rendered TRUE for a secand two hundred-microsecond period, during which time the second-order digit read from the tape is stored in the seco?d-order digital position of the address in memory speCified by the contents of section 3 of the instruction register. As shown in FIG. 61, at TIME-J after line TH is re~dered. TRUE for the second time, the state of line ,~~ IS agam rendered FALSE and thereby causes the digit-counter to be incremented from a count of "0" to a count of "1." ~s long as line ROS remains TRUE, the above-descnbed seq~e.nce of events is sequentially repeated until the tenth digit read from the tape is stored in the tenthorder digital position of the address in memory specified by the contents of section 3 of the instruction register at which time the digit-counter is incremented to a count of "9" as indicated by line D9 being rendered TRUE. However, following the third bit-time period after line TH is rendered TRUE, the state of line IN4 is reversed from TRUE to FALSE. As a result, section 3 of the instruction register is incremented by a count of "I." Thereafter, t~e next group of ten digits read from the tape is stored m mem~ry at the address now specified by the contents of sectIOn 3 of the instruction register. A~ter an end-of-frame or an alternate-instruction symbol IS detected, the state of flipflop 6098 is reversed due to a reversal of state of a corresponding one of lines EOF 3,112,301 224 223 and AI. Consequently, line ROS is rendered FALSE and thereby prevents line MXW (FIG. 60) from thereafter being rendered TRUE. After line (ROS)' is thus rendered TRUE, the state of flipflop 6061 is continued to be reversed at each TIME-l and thereby causes line TH to be rendered TRUE for successive two hundred-microsecond periods until the digit-counter reaches a count of "9." However, in the event the digit-counter is already at a count of "9" when a symbol is detected, indicating that the address specified by the contents of section 3 of the instruction register is completely filled with significant digits, the state of flipflop 6061 is prevented by line (D9)' from being so reversed. Consequently, a zero is stored in each of the higher-order digital positions remaining unfilled in the last-designated address when a symbol is detected. When line ROS is thus renderedF ALSE, line PTF is rendered FALSE and line PTS is simultaneously rendered TRUE to thereby cause immediate energization of the forward tape-breaking mechanism, so that the paper tape is brought to a sudden standstill. Also atter line (ROS)' is rendered TRUE, the state of flipflop 6107 is reversed when line AN is subsequently rendered FALSE, indicating completion of the previously-initiated "JM" digitcycle. When line STD is thus rendered TRUE, one of lines TS4 or TS5 is simultaneously rendered TRUE, depending upon whether the symbol just detected is an alternate-instruction symbol or an end-of-frame symbol. If the character just detected is an alternate-instruction symbol, the state of flipflop 6095 is reversed, and line OBM is rendered TRUE. However, if the character just detected is an end-of-frame symbol, the state of line OBM remains FALSE. It is evident, therefore, that when line STD is rendered TRUE, line TS4 is likewise rendered TRUE if an alternate-instruction symbol is detected, whereas line TS5 is rendered TRUE if an end-of-frame symbol is detected. In response to lines STD and TS4 being rendered TRUE, a "SID" subinstruction is thereafter executed, whereby the contents of section 4 of the instruction register is stored in the word-selecting register, whereas, in response to lines SID and TSS being rendered TRUE, a "STD" subinstruction is thereafter executed, whereby the contents of section 5 of the instruction register is stored in the word-selecting register, thus terminating the sequence of events initiated in response to the "EPT" instruction. It is next assumed that the contents of section 2 of the instruction register is "00" and an alternate-instruction symbol is positioned over the reading head when the "EPT" instruction is first initiated. As before, ,the state of flipflop 6098 is reversed, so that line ROS is rendered TRUE upon completion of the previously-initialed "MI" word-cycle. As a result of line ROS thus being rendered TRUE, line PTF is rendered TRUE, whereas line PTS is rendered FALSE thereby. Consequently, the fonvard braking mechanism of the paper-tape reader is de-energized, so that ,the paper tape is thereafter translated in a forward direction at a constant velocity. However, as soon as the tape is transLated forward, so that the alternate-instruction symbol is no longer disposed over the reading head, line AI is rendered FALSE, and, as a result, the state flipflop 609'8 is again reversed, so that line ROS is rendered FALSE thereby. In ,addition, when line AI is thus rendered FALSE, the state of flipflop 6095 is also reversed, so that line OBM is rendered TRUE thereby. In response to line (ROSY initially being rendered FALSE, the state of flipflop 6107 is reversed, so that line SID is rendered TRUE thereby. Therefore, when line OBM is subsequently rendered TRUE as a result of the alternate-instruction symbol being moved away from the reading head, line TS4 is likewise rendered TRUE. In response to lines S'J1D and TS4 being rendered TRUE, a "STD" subinstruction is thereafter executed, whereby the contents of section 4 of the instruction register is stored in the word-selecting register. In addition, line 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 PTF is rendered FALSE and line PTS is rendered TRUE as a result of line ROS being rendered FALSE. Consequently, the forward braking mechanism is again energized in a manner such that the paper tape is brought to a sudden standstill. It is next assumed that, when the "EPT" instruction is first initiated, the contents of section 2 of the instruction register is "00" and ,an end-of-frame symbol is disposed over the reading head. As before, the state of flipflop @98 is reversed when line MIN is rendered FALSE upon completion of the previously-initiated "MI" word-cycle, so that line ROS is rendered TRUE thereby. As a result of line ROS thus being rendered TRUE, line PTP is likewise rendered TRUE, whereas line PTS is rendered FALSE. Consequently, the forward braking mechanism is de-energized, so that the tape is thereafter caused to be translated in a forward direction at a constant speed, during which time the data information read from the tape is stored in memory in the same manner as previously described. When an alternate-instruction symbol is subsequently detected, the states of both of flipflops 6095 and 6098 are reversed, so that line OBM is rendered TRUE and line ROB is rendered FALSE thereby. As a result of line ROS being rendered FALSE, line PTS is rendered TRUE, whereas line PTF is rendered FALSE. Consequently, the forward braking mechanism is energized, so that the tape is brought to a standstill. When line AN is subsequently rendered FALSE after line (ROS)' is rendered TRUE, the state of flipflop 6107 is reversed, so that line STD is rendered TRUE. As line OBM is also TRUE at this time, line TS4 is rendered TRUE when line SID is thus rendered TRUE. Thereafter, 'a "STD" subinstruction is executed, whereby the contents of section 4 of the instruction register is stored in the word-selecting register. it is to be noted that, if an end-of-frame symbol had been detected, instead of an alternate-instruction symbol, the state of flipflop 6098 is reversed, as before, and thereby causes the forward braking mechanism to be energized. However, a "STD" sub instruction is thereafter executed, whereby the contents of section 5 of the instruction register, instead of section 4, is stored in the word-selecting register. It is next assumed that, when the "EPT" instruction is first initiated, the contents of section 2 of the instruction register is "01" and 'a data digit is disposed over the reading head. Therefore, when line ROS is rendered TRUE upon completion of the previously-initialed "MI" word-cycle, as before, line PTR is rendered TRUE and line PTS is rendered FALSE. Consequently, the reverse tape braking mechanism is de-energized, so that the tape is thereafter translated in a reverse direction at a maximum constant speed. After the tape is being translated in a reverse direction, line GC is sequentially being rendered TRUE and FALSE by flipflop 6087, as before. However, due to the fact that the low-order digit of section 2 of the instruction register is now a "I", so that the state of line Lrp is FALSE, the state of line TH remains FALSE and thereby prevents 'any data read from the tape from being stored in memory at the address specified by section 3 of the instruction register. When an endof-fmme symbol is subsequently detected, the state of flip-flop 6098 is again reversed, and line ROS is rendered FALSE thereby. When line ROS is thus rendered FALSE, line PTR is likewise rendered FALSE, while line PTS remains FALSE and the tape continues to be rewound. Approximately forty microseconds after line (ROS)' is rendered TRUE, the state of flipflop 6107 is reversed, and lines STD and TS5 are both rendered TRUE thereby. Consequently, a "STD" subinstruction is thereafter executed, whereby the contents of section 5 of the instruction register is stored in the word-selecting register. As previously mentioned, line REW is rendered TRUE each time the tape is being tran&lated in a reverse direclion. Consequently, while the tape is being trnnslated 3,112,39·1 225 226 in a reverse direction and the computer is in the process of executing another instruction than "EPT," if an alternate-instruction symbol is subsequently detected, so that line AI is rendered TRUE, line PTS is rendered TRUE to effect immediate energization of the reverse braking mechanism and thereby cause the tape to be brought to a sudden standstill. . . . .. . When the "EPT" instructIOn IS firstlmtJated, If the contents of section 2 of the instruction register is "01" and an end-of-frame symbol is disposed over the reading head, line ROS is rendered TRUE, as before, upon completion of the previously-initiated "M.l" word.-cy~le. When line ROS is thus rendered TRUE, hne PTR IS likewise rendered TRUE, and, as a result, the reverse braking mechanism is de-energized, so th~t th.e paper tape is thereafter translated in a reverse dIrectIOn, as before. When an end-of-frame symbol is thereafter detected, the state of flipflop 6098 is again reversed, and l~nes ROS and PTR are both rendered FALSE. ApproxImately forty microseconds ·after line ROS is rendered FALSE, lines SID and TS5 are rendered TRUE by a reversal of state of flipflop 6107. As a result, the ,:ontents of sectio~ 5 of the instruction register is stored III the word-selecting register. The paper tape, however, continues t? be [ra.nslated in a reverse direction until an alternate-instructIOn symbol is detected, at which time line PTS is :endered TRUE. As previously described, as a result of hnes. PTS and PTR 'being rendered TRUE and FALSE, respectively, the reverse braking mechanism is energized and thereby causes the paper tape to be brought to a sudden standstill. It will next be assumed that, when the "EPT" instruction is first initiated the contents of section 2 of the instruction register i~ "01" and 'an alternate-instruction symbol is disposed over the reading head. As befo:e, line ROS is rendered TRUE by a reversal of ·state of flipflop 6&98 when line MIN is rendered FALSE upon completion of the previously-initiated. "MI" :",ord-cycle. When line ROS is rendered TRUE, hne PTR IS rendered TRUE and thereby causes de-energization of the reverse braking mechanism, 80 that the paper tape is thereafter translated in a reverse direction. When an end-of-frame symbol is subsequently detected, the state of flipflop 6098 is reversed, so that lines ROS ,and PTR are both rendered FALSE thereby. Approximately forty microseconds after line ROS is rend~red FALSE, the state of flipflop 6107 is reversed, so that hnes STD and TS5 are both rendered TRUE. Thereafter, a "STD" subinstmction is executed, whereby the contents of section 5 of the instruction register is stored in the word-selecting register. Upon subsequent detection of an alternate-instruction symbol, line PTS is rendered TRUE and thereby causes energization of the reverse braking mechanism, whereby the tape is brought to a sudden standstill. Finally, it is assumed that the paper tape mechanism is in a rewinding cycle of operation when the "EPT" instruc,tion is first initiated and "00" is stored in section 2 of the instruction register. As before, the state of flipflop 6098 is reversed and line ROS rendered TRUE when line MIN is subsequently rendered FALSE upon completion of the previously-initiated "MI" word-cycle. When an alternate-instruction symbol is thereafter detected, the states of flipflop 6098 and 6095 are both r~versed, so that lines ROS and OBM are rendered FALSE and TRUE, respectively. However, approximately forty microseconds after line ROS is rendered FALSE, the state of flipflop 6107 is reversed, so that lines STD and TS4 are both rendered TRUE thereby. Asa result, the contents of section 4 of the instruction register is thereafter stored in the wordselecting register. Also, when the alternate-instruction symbol is detected, line PTS is rendered TRUE and thereby causes the reverse braking mechanism to be energized and the tape to be brought to a sudden standstill. 88. Detailed Description of Paper Tape Punching Operatioll 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 There have previously be~a described in detail various modes of operations 'capable of being executed by the computer whereby words indexed into th~ accounti~g machine keyboard, or taken from the totalizers therem, are subsequently stored in selected addresses in memory via execution of an "EKW" instruction; whereby words stored in selected addresses in memory are subsequently printed out on recording media via execution of a "POW" instruction; whereby words stored in selected addresses in memory are magnetically recorded on a ledger card via execution of a "ROC" instruction; whereby words are magnetically read from a le,dger card and subsequently stored in selected addresses in memory via execution of an "ECW" instruction; and whereby words are read from punched paper tape and subsequently stored in selected addresses in memory via execution of an "EPT" instruction. There will now be described another mode of operation capable of being executed by the computer whereby wmds stored in selected addresses in memory, or either indexed into the keyboard or taken from the totalizers of the accounting machine, are subsequently recorded on punched paper tape. H is assumed that, prior to the initiation of a punching cycle of operation, the carriage of the accounting machine is stationary and is located in a columnar position such that plate 214 (FIG. 13), hence switch-operating studs 215 and 216, is positioned adjacent switch plungers 217 and 218, as illustrated by the dotted lines therein. It is further assumed that the 'paper-tape-punching mechanism (FIG. :44H) is properly loaded with a suitable supply of paper tape, and that switch ST43 (FIG. 86) has previously been closed by the operator, thus causing the direct-current power supply, which supplies the necessary unidirectional operating potential to the control circuitry of the paper-lape-punching mechanism. to be energized thereby in a well-known manner. Upon the machine carriage reaching the just-assumed position, the forward extension of plate 214 (FIG. 13) engages the roller portion of the arm 153 in a manner such the arm 153 is deflected counter-clockwise, as viewed, to the extent that switch SC41 is actuated thereby. When switch SC41 is (hus actuated, contacts SC41-1 and SC41-2 (FIG. 86) are closed, and contacts SC41-3 (FIG. 82) are opened thereby. It will now be assumed that a cycle of operation of the accounting machine has just be'en initiated in response to an enter-keyboard-words (EKW), print-outwords (POW), or motor bar (MB) instruction, so that the amount racks are subsequently differentially positioned indicJtive of the word read out from memory, or just entered in the keyboard, of taken from a totalizer of the accounting machine. With continued reference to FIG. 86 and also to the timing chart shown in FIG. 87C, ,after a cycle of opuation of thc accounting machine is initiated, so that the main CRm shaft 588 of the machine is rotated clockwise, as viewed in FIG. 44B, through an angular distance of approximately 126 degrees from the position shown, the contacts of switch SC49 are closed due to the engagement of the cam 592 with the actuator thereof. Closure of the contacts of switch SC49 completes the circuit throur;h solenoid L47 (FIG. 86) and thus effects energizatio-n thereof. "Vith reference to FIG. 13, as a result of solenoid L47 thus being energized, its orm3ture is caused to be rotated counter-clockwise, as vic'i'icd, thereby causing the stud 226 to deflect the lever 223 clockwise and thus shift the switch basket upwardly until selected ones of the plungers 217 and 218 are respectively engaged with predetermined ones of the studs 215 and 216. As a result of such engagement, predetermined ones of the plungers 218 in the rightmost row 3,112,394 227 228 and predetermined ones of the plungers 217 in the leftmost row are simultaneously depressed and latched in their downwardly-deflected positions, and, additionally, remaining ones of any previously-depressed and -latched plungers are caused to be released simultaneously therewith. After the main cam shaft of the machine is rot'ated through an angular distance of approximately 168 degrees, the movable arm of switch SC48 (FIG. 44B) is effectively deflected downwardly due to the engagement of the cam 592 with its actuator. When the movable arm of switch SC48 is deflected downwardly from the position shown in FIG. 86, solenoid L47 is de-energized, whereas solenoids L45 and L46 are both caused to be energized thereby. With reference back to FIG. 13, when solenoid L47 is thus de-energized, thc switch basket is spring-urged back to its initial starting position, as shown. As 'a result of the basket return, the electrically-non-conductive tip 22.8, carried on the lowermost end of each of the plungers 217 and 218, engages and thus deflects downwardly the topmost one of a corresponding stack of switch blades 229, which stacks are arranged in twenty rows, with each row corresponding to a different one of the plungers 217 and 218. It is appreciated, of course, that there are ten of the plungers 217 arranged in a leftmost row ·and there are ten of the plungers 218 arranged in a rightmost row. When the uppermost one of the switch blades 229 is deflected downwardly, all of the switch blades located in that pm·ticular stack are electrically connected together until the solenoid L47 is ·again energized and thereby again callses the switch basket to be moved upwardly in the same manner as previollsly described. With reference to FIG. 45D, there is illustrated therein a block diagram of the electrical circuitry which is utilized by the paper-~ape-punching mechanism and which is substantially identical with that shown and described in co-pending United States patent application Serial No. 634,260, filed by Richard C. Simmerman and :rvlelvin T. Roudebush on January 15, 1957, and assigned to the present assignee, now United States Patent No. 2,922,141, issued January 19, 1960. The tapepunch control circuitry, the rear form bar circuitry, and the rack read-out circuitry are herein shown and described in detail with respect to FIGS. 86, 13, and 3B, respectively. Due to the fact that a detailed description of the program selection, serializer, ·and punch magnet control circuitry is to be found in the just-mentioned copending application, a further detailed description thereof is not deemed necessary to again be given herein. Suffice it to say that the pattern of selective closure of the switches 229 (FIG. 13) causes a predetermined tapepunching program within the paper tape recorder to be selected in the same manner as described in the just-mentioned co-pending application. Just prior to de-energization of solenoid L47, the variOUS8molmt racks are assumed to be differentially positioned indicative of a word just read from memory, just entered from the accounting machine keyboard, or just taken from a selected one of (he totalizers of the machine, all in the same manner as previously described with respect to the "EKW," "POW," and "MB" instructions, so that the aligner bar 72 (FIG. 3A) is in engagement with the :aligner notches formed on the lower end of the member 58. Thus, with reference now to FIGS. 3B and 9, when the solenoids L45 and L46 are energized, the shaft 197 is rotated clockwise, as viewed in FIG. 3B, so that the switch basket 171 is lowered thereby to a position sufficient to cause engagement of the lowermost end of one of the spring clip members 18·" in each of the ten columns .thereof, as illustrated in FIG. 9, with a corresponding raised cam surJiace 205, which is formed on the topmost side of the rightmost end of each of the extensions of the: amount mcks. Consequently, due to such engagement of the spring clip mcm- bel'S 184 with the cams 205, corresponding ones of the members 184, one in each column, are latched in an upwardly-deflected ,position, all in the manner previously described. Thereafter, the latched clip members coIlectively represent the differentially-set digital valued positions of the amount racks. After the main cam shaft of the accounting machine is rotv.ted an angular distance of approximately 182 degrees, the actuator or the switch SC49 (FIG. 44B) is released from engagement with the cam 592. As a resuit of the release of the actuator of the switch SC49, the contacts thereof me thereby opened. With reference back to FIG. 86, when the contacts of switch SC49 are opened, as shown, solenoids L45 and L46 are de-energized thereby. As a result of solenoids L45 and L46 thus being de-energized, the lower switch basket 171 (FIG. 3B) is caused to be spring-urged upwardly, so that all latched ones of the c1ipmembers 184 are thereby brought into cnga.gement with, and thus short-circuit, corresponding ones of the spring-clip members 177, all in the same manner as previously described with respect to FiG. 12. When the main cam shaft of the accounting machine is rotated an angular distance of approximately 213 degrees, the cam 593 (FIG. 44G) engages the actuator of ~witch SC42, so that its normally-opened contacts are closed thereby. With reference to FIG. 86, due to the fact that relay solenoid K3 is normally energized, so that contacts K3-3 are closed thereby, relay solenoid Kl is caused to be ener.gizcd when the contacts of switch SC42 are thus closed. When relay solenoid K1 is energized, contacts Kl-l are opened and thereby cause a 300-ohm resistor to be connected in series with relay solenoid Kl, con~acts Kl-2 are closed, contacts Kl-3 are opened, contacts KI--4 are closed, contacts KI-5 are opened Gnd thereby cause relay solenoid K3 to be de-energized, contacts KI-6 are closed and thereby maintain relay solenoid Kl energized,and contacts Kl-7 (FIG. 82) are opened and thereby cause the state of line GO to be rendered FALSE, thus indicating that a punching cycle of operation is just initiated. At approximately 264 degrees of rotation of the main cam sh"ft, the actuator of switch SC42 (FIG. 44G) is reiensed by the cam 593, so that the contacts of switch scn are allowed to open as illustrated in FIG. 86. After relay solenoid K1 is energized, the accounting machine independently continues to complete its cycle of operation in the same manner as previously described. However, in response to relay solenoid Kl thus being energized, a cycle of operation of the punching mechanism is thereafter executed in the same manner as described in detail in the before-referred-to co-pending application Serial No. 634,260, whereby the amount collectively represented by the short-circuited conditions of the spring clip members 177 is caused to be recorded on the paper tape via the paper-tape-punching mechanism shown and described in detail with respect to FIG. 44H. If it is assumed that the word indexed into the accounting machine keyboard, as collectively represented by the short-circuited conditions of the spring clip members 177 (FIG. 3B), is a negative amount, as indicated by a depression of the reverse-entry key, the movable arm of switch SC46 (FIG. 44A) is actuated, so that its normally opened contacts are closed upon depression of the reverse entry key REV. Wi,th reference to FIG. 86, as the contacts of switch SC46 me thus closed prior to the closure of the contacts of switch SC42, relay solenoid K5 is energized simul~aneously 'with relay solenoid Kl when the contacts of switch SC42 are subsequently closed in the manner just described. When relay solenoid K5 is thus energized, contacts K5-1 are opened, whereas contacts K5-2 are closed and thereby maintain relay solenoid K5 energized even though COll- 5 10 15 20 25 30 35 ·10 45 50 55 60 65 70 75 3,112,394 230 .229 tacts SC42 are subsequently opened. In response to rclay solenoid K5 thus being energized, a symbol representing an opposite algebr,ai'~ sign to that which was program-selected is punched in the paper tape. However, if it is assumed that the word stored in memory to be subsequently read out and recorded on punched paper tape is the complement of a negative number, a different sequence of events from that just described is initiated. As previously described with respect to FIG. 37, a credit-balance cycle of operation is automatically initiated when solenoid CBS is selectively energized. Also, when credit balance key "CR. BAL." (FIG. 2) is depressed, a credit-balance operation is carried out when 'a cycle of operation of the 'accounting machine is subsequently initiated. As previously described with respect to FIGS. 44D and 44F, when a credit-balance cycle of operation is initiated and the main cam shaft thereafter rotaled an angular distance of approximately thirty degrees, the overdraft cam &haft 601 is coupled through the gear 604 to the main cam shaft 588 in such a manner that the overdraft cam shaft is thereafter rotated at exactly one half the speed of the main cam shaft. Thus, when a machine cycle is initiated and the overdraft cam shaft 601 thereafter is rotated an angular distance of approximately ten degrees, the normally-closed contacts of switch SC45 (FIG. 44C) are released by the cam 612 and are thus opened thereby. With reference to FIG. 86, when the contacts of switch SC45 are opened, relay solenoid Kl is prevented from being energized and thereby initiating a tape-recording operation during the first cycle of the credit-balance operation of the accounting machine. However, after the overdraft cam shaft is rotated through an angular distance of approximately 165 degrees, during which time the main cam shaft is rotated one complete revolution, the contacts of switch SC45 'are caused to be dosed by the cam ,612 ,and remain closed during the second cycle of the credit-balance operation of the accounting machine. Thus, relay solenoid Kl is allowed to be energized in the manner previously described only during the second cycle of operation of the accounting machine when a credit-balance operation is being carried out. After the overdraft c'am shaft 601 is rotated an angular distance of approximately 260 degrees, the normallyopened contacts of switch SC47 (FIG. 44E) are caused to be closed by the cam 613. With reference to FIG. 86, when the contacts of switch SC47 are closed, relay solenoid KS is thereafter permitted to be energized when contacts SC42 are subsequently closed and thereby cause energization of rel,ay solenoid Kl in the same manner as previously described. Energization of relay solenoid K5 causes contacts K5-2 to be closed and thereby maintain relay solenoid K5 energized, as before. After relay solenoid K5 is ener~gized, the cycle of operation subse.. quently carried out is exactly the same as just described with respect to the "reverse-entry" cycle of operation. After the overdraft shaft is rotated an angular distance of approximately 290 degrees, relay solenoid K5 remains energized even though the contacts of switch S047 are caused to be opened by the cam 613. 5 10 1.) 20 25 30 35 40 45 50 55 60 89. Operator Controls As previously mentioned with respect to FIG. 1, lo- 65 cated on the front of the right-hand portion of the computer oabinet is a control panel 15, having mounted thereon four push button controls, S¢1-S¢2, Sll-S12, SP1-SP2, and RSl, each of ,which, when depressed, 70 initiates ,a particular cycle of operation of the computer. That is, when either of the four just-mentioned push buttons is depressed, the particular cycle of operation associated with that particular push button is thereafter carried out, regardless of the particular portion of the 75 program the computer is currently in the process of executing. For example, when push button S¢1-S¢2 is depressed, the word-selecting register is preset to "00" via line PW.p. Immediately thereafter, the word stored in memory address "¢rfJ" is read out and stored in the instruction register, and the particular cycle of operation dictated by that particular instruction word is thereafter executed. When push button SU-S12 is depressed, the word-selecting register is preset to "01," via line PWl, and the particular cycle of operation dictated by the word stored in memory address ".pI" is immediately executed there::fter. However, when push button SP1-SP2 is depressed, the instruction register is preset to 0000009900. Immediately thereafter, the particular cycle of operation dictated by thc contents of the instruction register is executed; i.e., "Enter-keyboard-words into memory addresses ¢¢ through 99 with an upper motor bar 'touch' operation and a normal decimal-point lamp illumination." When reset push button RSI is depres!lCd, the states of substantially all of the control-counter flipflops are simultaneously so conditioned that the reference outputs thereof are thereafter rendered FALSE via line (RS)'. Thereafter, the computer remains in a standby or neutral condition until one of push buttons S¢l-S¢Z, S11-S12, or SPlSP2 is subsequently depressed. Also, as previously described, when the computer is first turned "ON," a neutral or standby condition is effected by line (RS) '. After the computer is in a neutral or standby condition, depression of one of push buttons S¢I-S¢2, Sll-S12, or SPl-SP2 is necessary in order to initiate a subsequent cycle of operation thereof. Located on the right side of the control panel 15 are two additional push buttons, ATI-AT2 and MN1MN2, which, when depressed, respectively condition the computer for a subsequent automatic or a manual mode of operation. For el'1 ultiply on'rUn1e rate by o v('rtime houTs. POw ____ Pr int out reguh'lr f'arnings md overtime eurnings. MDD ___ 1\'1 llltiply number or de1lendents by I a.oo. EKW ___ Pr int out gTO~~ parnir~gf1 ( ,;lIb-lolal" X" totalizer). ADD ____ AtId gross carnings to tolal g ro~s carnings to dtltO. SUB _____ Sll btraet tax: credit fronl g roos ___ earnings. Olo'l\L __ }), ~~ermin(' if Htljustl'd ~TOSS ,ofjual to ur greater (ban t'ro. SIIF _____ 00 py .00 for withholding " 1\1DD ___ SllE' _____ l\'1TS ____ 35 ADD ____ CFJ\L ___ SUB _____ 40 A])D ____ ADD ____ 1'OW ____ ADD ____ 45 MUS ____ POw ____ ADD ____ POw ____ 50 MB. _____ 1'OW____ 1'OW ____ ADD ____ 00 04 00 00 00 70 01 02 63 70 85 02 02 10 05 70 84 03 03 16 95 85 01 04 04 00 40 05 95 51 05 06 07 08 16 06 01 12 85 30 20 71 70 00 63 06 00 94 99 07 01 08 52 09 00 20 95 98 10 11 10 13 35 71 95 11 13 35 99 96 12 12 01 20 05 96 13 13 12 72 55 96 14 14 00 23 95 95 15 16 15 08 95 79 79 16 Og 95 96 96 17 17 15 96 62 19 18 18 01 00 62 96 20 19 12 96 56 96 20 20 21 01 13 00 35 95 57 97 95 21 22 22 08 83 95 99 23 23 15 99 58 24 25 24 09 58 83 95 25 25 08 95 83 83 26 26 as 96 95 96 27 27 01 20 96 96 28 t ax. ]\; ultiply aLljnsted gross by t ax rate. 00 py gro~s rarnings _________ M uHiply gro::s earnings 1y 1c.I.O.A. rato. Ad d F.I.O.A. deduction to 1'.I.O.A. to date. D.·'trrmine if new F.I.O.A. t 0 date is equal to or g reater tklll $120.00. Su btnwt F.I.O.A. to date f rom $120.00. A,III F.l.O.A. 11cduutian to 1<.I.O.A. to date. Ad 11 witbholdin.,; tax to 1~.1.C.A. (kdllctil:-,n. Pn'n! ant Federal tax drducI. ion. Ad d Federal tax to F(~lleral t ax t.o date. Mu ltillly gross earnings hy city tax rate. Pr int out dl,y tfiL ___________ Ad d city tax duclion (0 t )011(1 d('duc~ ions to date. Ad d crrdij, union d('durtion t o cf{~tlit union deduct ions 1o date. Ad d insurance deduction t 0 insurance deductions t o datc. Ad d annuity deduction 10 ( ~h{'st annuit y deductions to d a(c. Pri nt out nli~ccllaneou8 (]C'd uction. Ad d miscellaneous d"duct ion to nlit3crllaneolls ded uution" to date. Ad d anBuit,y dt'duetion to a nnuity deductions to d ate. Pri nt out fourtot.ls to date __ Ad d advance (aelor to c!Jeck II umlJer. nt out amount of net o;y (totnl ~j X" totalizer). TIt out elteck numbeL ____ TI1urize ,vords for proof tal. " ~;;:I ~,~ 38 08 75 88 88 39 39 08 76 89 89 35 40 08 77 90 90 41 41 08 78 91 91 42 42 01 20 98 98 43 43 08 ~8 92 92 44 44 08 78 82 82 45 45 46 01 08 20 93 79 61 82 93 46 47 06 20 00 00 48 48 49 01 10 10 85 93 70 93 84 50 47 49 3,112,394 233 Instruc-I tion word symhol 234 I Mcmcry Literal instruction Instrnction fJl1U uddrC':"s location dat~ ,vonls I ROC_. __ RCC'Ofds 'words on le(l~er curd. SHF_ .. __ . 81tHt dock num1cr two phces to the rkht. StH'_. __ _ Shift clock num ber eight places to tbe l('ft. CFE ___ _ Det('nninc if the £l.x('cDtion alert di;it is eqnal to' 7(,l'O. COllY ferty hours into teIll.~ GO 03 00 \70 9.,1) 01 I 95 P5 05 95 P5 53 51 0'( '12 52 01 28 [;3 1G 95 I ~2 m 54 5-1 Ol 00 CO j D;:; CJ I porary stof8.::e address. \"ithholding tax exelIlntion factor; Le., $13.00. . \Vithholulng iax ratc; Le., 5.1 00 00 00 fiG 00 00 00 00 13 18%. F.I.C.A. rate; i.e" 2.5C;~_ ' __ ' F.I.C ..A. rnaxinllllll; i.c.~ 57 58 on on 2fi 00 00 00 00 Oil I~O 00 fig 60 til 00 00, Oil 00 110 00 00 011 ! 40 ~120.00. City tax rntf'; LO. t 0.5% ______ Constaot of '10 hour.' .. ______ Check nrnnbcr advance factor; Lr., 1. CI}Ilstant .. 0" _______________ OvertiIne rartor; i.eo, IJ