3480_MI_A04 3480 MI A04

3480_MI_A04 3480_MI_A04

User Manual: 3480_MI_A04

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Collating List of Pages
This reference drawing contains the collating sequence.
page side. and EC levet of pages for IBM 3480 Magnetic

Tape Subsystem Maintenance Information Manllal (MI)
Volume A04, SY32-5055-13.
The part number of the divider tab list is 8673746.
This reference drawing is to be placed at the front of the
manual.
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Copyright IBM Corp. 1982. 1991

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MI

PAGE

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PUBLICATIONS REFERENCE DRAWING

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MACHINE TYPE/MODEL NO. 3480
~~~~~,

MACHINE NAME - Magnetic Tape Subsystem
"n·.........

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FORM NO.

E C NO. I DESCRIPTION/COMMENTS

SY32-5055-0

991552

--

VOL. A04 - Maintenance Information
REA 12-11655

336326

....

TNL SN32-0310
IEC 001122571 (REA 12-25744)
IEC 002122571 (REA 12-25494.
REA 12-25496)
----------- .----..

.

SY32-5055-1

336389

---_·_---_·_-------·1-

SY32-5055-2

........

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Second Edition
IEC 0011215156
IEC 0011225996
. - - - - - - - -..- ....-.. -...- ... -- ... .,.-..--.-----------.----.--

336390

-.......~~

Third Edition
lEe 0011225997
IEC 0011215157

1------------1-

SY32-5055-3

.........

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336391

----

Fourth Edition
REA 77-11223
IEC 0011215158
IEC 0011215159
IEC 0011225842
IEC 0011225843

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-·----·--------I·------l---------.. . -.-.-.. . --..----.----------.-.SY32-5055-4
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----- ....---.--... -.-.-.. -... - - . - - - - - - - - . - - -

TNL SN32-5036
--.------.-- ---.--

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SY32-5055-6

Sixth Edition
Seventh Edition
IEC 0011225844

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SY32-5055-10

A57721

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SY32-5055-11

A57723

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........
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Thirteenth Edition
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3480

SIN-

HI
Maintenance
Information
GLOSS
PLAN
INTRO
*START*
CART
PNEU
HSG
INST
INSP
INDEX

Vol AOI

3480
S/NMI
Maintenance
Information
PWR
SENSE
PANEL
MD
LOe
eARR-eU

Vol AOZ

Maintenance Library
Maintenance Infonnation
Logic Diagrams

3480
S/NMI
Maintenance
Information

3480

MI
Haintenance
Information

eARR-QB

Vol A03

3480
S/NMI
Maintenance
Information

SIN-

LGND
SPROe
SDISK
DIAG
OF
OPER

I

Vol A04

FSI
EAD

I

Vol AOS

Vols. A01 to AOS
Vols. C01 and 001

3480 Magnetic Tape Subsystem

SY32-7018-03

Preface
This manual contains maintenance information about the IBM
3480 Magnetic Tape Subsystem and is intended for customer
engineers responsible for servicing the 3480 tape subsystem.
This publication is designed to be used with the IBM
Maintenance Device (MOl. Therefore. CEs using this manual
should be familiar with that tool.

Related Publications

How to Order This Manual

IBM System/360 and System/370 I/O Interface Channel to
Control Unit Original Equipment Manufacturers' Information.
GA22-6974.

This manual or pages can be ordered from one of the following:
•

United States

IBM 3480 Magnetic Tape Subsystem Description, GA32-0042.

•

Europe/Middle East/Asia IE/ME/A)

How to Update the Maintenance
Information

•

Americas/Far East (A/FE)

Preface

PREF 1

Preface

PREF 1

Prerequisite Knowledge
It is assumed that you have a background in data processing
concepts and that you are familiar with the hexadecimal
numbering system. stored program concepts. and have a basic
understanding of tape subsystems and their relationship to a
processor I/O channel.

This manual is form number controlled. The 3480 manuals will
be updated by Technical Newsletters (TNLs). The TNL cover
letter will indicate the new EC level. The entire manual will be
updated by major revision. All updates are processed through
normal MLC control. The Publications Reference Drawing (PRO)
in the front of each volume contains the EC history.

Use the wiring Diagram/Logic Page Request form. Z 150-0 130.
Be sure to include the form number of the manual when ordering
the new manual or pages. Please write your telephone number
on the form in case there are any questions regarding your order.

United States
IBM Corporation
General Products Division
Dept.3Ot..
Tucson. Arizona 85744

E/ME/A
International Business Machines
S.A.E .• Division de Fabricacion
Dept. 9290
Valencia. Spain

A/FE
IBM Argentina SA
Dept. 020
H. Yrigoyen 2149
1640
Martinec. Pcia.
Buenos Aires
Republic of Argentina

3480 MI

EC336395

C> C""",ogh' IBM Corp. 1984

1985. 1986

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Tab List

Tab List

Volume A01

Volume A02

Volume A03

Volume A04

CARR-DR

LGND

Legend

GLOSS

Glossary

PWR

Power Maps

PLAN

Maintenance Plan

SENSE

Sense/Status

SPROC

Support Procedures

INTRO

3480 Introduction

PANEL

Panel

SDISK

Support Diskette Procedures

START

Start Maintenance

MD

Maintenance Device

DIAG

Support Diagnostic Descriptions

CART

Cartridge Analysis

LOC

Locations

OF

Data Fields and Registers

PNEU

Pneumatic Analysis

CARR-CU

Control Unit
Checks/ Adjustments/Removal/Replacement

OPER

Theory of Operation

MSG

Console Messages and EREP

INST

Installation/Removal

INSP

Safety Check Procedures

INDEX

Index

Drive Checks/ Adjustments/Removal/Replacement

TAB 1

Volume A05
FSI

Fault Symptom Index

EAD

Error Analysis Diagrams

3480 MI
«:

EC336395

CopVrlght IBM Corp. 19B4. 1985. 1986

Tab List

TAB 1

Notes

Notes

3480 MI

Notes

EC336395

'" Copyrlgl\.IBM Corp. 1984. 1985. 1986

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Contents

Contents

LGND 1

Graphic Symbols and lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Ke~
.......................................... 5
Connectors .... " .. , .... , ......... , .. ,.,." .. , ........... , .. , .. , . " . 5
Bus and Control lines , ... , ...... , ... ,.,., ... ,., ...... ,' ...... , .. " . . . . 5
IdentifYing Parts , ... ,., .. , ... , . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . " ... , .. . 10
Control Unit Location Area Definitions ,.,., .... , ... " . , .... , ..... " . , . " .... . 15
Tape Unit and Drive Location Area Definitions ., ..... " ..... " ... , .... ,., .... ,. 35
Error Analysis Diagram Logic Blocks , .. , ... ,.,.,., ...... , .... ,.,., ......... . 55
Logic Diagrams " . , . , .... , ... , ... , . . . . . . . . . . . . ,., . . . . . . . . . . . . . . . . . . . . . 60
Card Location Charts ... " ........ , ... , ....... , ........ , .... , ........ . 60
Card Plug lists ........ , ............ , . . . . . . . . . . . . . . . . . . . . . . . . . . . . , .. 60
Multiple Logic Diagrams for One Card , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Sample Logic Diagram ..... , ...... ,., . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , 65
Bundled Lines , . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . , ...... . 70
Logical/Physical Pins . . . . . . . . . . . . . . , .......... , . . . . . . . . . . . . . . . . . . . . . . . 70
Dot OR' s of Output lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... , ...... . 75
Field Wire Net lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Pin to Net list ..................................................... 80
Net to Pin list ..................................................... 80
Voltage Distribution list . , , .. , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

3480 MI

EC336395

 CopyrIght IBM Corp. 19B4, 1985

Contents

LGND 1

Legend
Graphic Symbols and Lines

Bus and Control Lines

Keys

Minor Bus Lines

Primary Key
Reverse number in a black square. Used in text and diagrams.

.

Legend

LGND 5

Legend

LGND 5

Bus and control lines that connect to a bus.

Write Data

~

B Read Bus
Device Data Bus

~

Secondary Key
Reverse letter in black circle. Used in text when keying to a test point symbol in a
diagram.

Connectors
Major Bus Line
On-Page Connectors

Bus and control lines that do not connect to a bus.

Connection between parts of the same diagram. Arrows point to remote connectors
and indicate flow direction of the line.

Control lines

Not Connected

Off-Page Connectors
Connection between diagrams on separate pages. Letter keys are used to identify
corresponding points.
Page
~
Number

'-=-'

Standard line break, used when a line break is needed.

Connected

--------~ss~-----

Entering Page

Leaving Page ~
--'-;~-1LY

Page
Number
Bus or cable with multiple control lines entering and exiting .

•

"

3480 MI

EC336395

~ Copyr'gh! IBM Corp. 1984. 1985

)

..

o

c

o

o

o

o

(J

o
Legend

Legend

(when no DO or 01)

2A-.

Identifying Parts

(ctd Connec..lor Pfn6

(VIew from end of cardl

Two different formats are used in the maintenance information
(MI) and logic diagrams to represent the unit that a part is
located.

Examples of the First Format:
lA-A1H4
1A-A 1D2-U06
1A-A 1E2-W22
lA-A2G2
2A-A1C2
Control Uni

J02-

U U

~

~[ord

002- ••• -B02
0 3 - ••• 03
Oq- ... 0<1
0 5 - ... ....- as
06-'" 06
0 7 - ... 07
0 8 - ••• 08
0'3- ... 0"1
10-'" 10
1 1 - " ' - 11
12-'" 12
013- ... -!l13

Cl3

lA-A2G2
--

D02- . • _B02
03- .
03
Oq
04- .
05
05- •
06
06- .
07
01- .
08
06- .
0"1
09- .
10
10- .
11
11-'
12- .
12
-!l13
•
D13- •

I..~

W-

U0 2

J I 3 - U _ GI3

-ffi-ffi-

P02-bj_M02

P02

P13-U-MI3

PI3-~_MI3

Logie Board Card Pin Position Identifiers
IA-AID2-U06

2'3- .
30- .
31- .
32-

wJ3--

TU-DO-..
TU-Dl-..
TU-DO/Dl-..

• _H13

1.

X22-D-X02

Logic Locallon Area Identifiers

10102

Z33-LJ-ZI3

-ctJ-

lA- TlAl ...

TU-DO/Dl-Al ...

CU-P2A4 ...

TU-DO/Dl-Pl-Pl ...

CU-PS-Ol ...

TU-DO/Dl-DK ...

CU-L/R-P2 ...

TU-Ol-DSP ...

CU-Al-TB3 ...

TU-PS-Ol ...

TU - DO-~tSG ...

TU-DO-Pl-WA2 ...

IgndlOc

N.3

Examples of the Second Format:

U02-kj-S02

U02

UI3-D-SI3

UI3-<>r.1""'513

or ("onnec: tor

Ignol0a

06
07
08
0'3
10
II
12

28- .

The next numbers are the functional
area within the tape unit. nolthe individual drives
within the tape unit.
Drive 0 - the remaining numbers pertain
to FRUs or parts in drive O.
Drive 1 - the remaining numbers pertain
to FRUs or parts in drive 1.
Drive 011 - the remaining numbers
pertain to FRUs or parts in both drive 0 and drive

Z22-D-Z02

T02

Frome

2S- .
26- .
27-

X 3 3 - U - XI3

~t;

2A·AIC2
-- u u

.t3oord

03
04
OS

Y33-LJ_\"I3

T(:Ipe Unit Logic Port Definitions

--GoOle

or
TU-...

-w02

J I 3 - r - GI3

Got@

~l

w22- •
23- •
2L.4- •

Y22-D-Y02

Boord

~Lord

(V,.'"

G02

J02

or connector

From.

Top cord CO"""_C.tor (TCC) pins
from 11"1_ top of the c.ard)

(02A-A1B2 cord only)
C02

Logic Par t Deflnili\)ns

t

Card (onn.Llor Pln5
(Vr.~ (rom end of cord

502

~

Igndl0b

lA-T1A 1
lA-T1A3Y
2A-A1Z2
lA-A2Y2
CU-P2A4
CU-PS-Ol-Jl-3
CU-UR-P2-2
CU-A 1-TB3-6
CU1APl-3
TU-OO-PA-Jl-012

TU-D1-PA-J1-D12
TU-001D1-A 1-Cl B 11
TU-001D1-Pl-3
TU-00/Ol-0K-P7-4
TU-DO-EL-J7-1
TU-D1-DSP-P1-011
TU-PS-Ol-P11-3
TU-PS1-J2-9
TU-OO-P 1-WA2-005
TU-Ol-Al-A2-B12

Nole: For descriptions. locations, and remove/replace
procedures for the location area identifiers, see the
following for:
•
•

Control unit - "Figure 1. Control Unit Location Area
Definitions"
Tape unit and tape drives - "Figure 2. Tape Unit and
Drives Location Area Definitions"

Part Locallon Idenllflers

U

t Logic
card and board pin U06 of the
IA-AID2 board position (this is the
pin connection between the logic
board and the logic card bottom card
connector (Bee) or other connector
in that position.

Logic Board Card Pin Position Identifiers
IA-AIE2-W22

Subsyslem Unilidenliliers
lA-... .
CU-... .
2A-... .
TU-... .

Control unit
Control unit
Tape unit
Tape unit

Tape Drive Unll Idenllflers
For subsystems unit with identifiers of TU or 2A only.

U

t W22
Logic card top card connector (Tee) pin
for the logic card in position
IA-AIE2 (the Tee is a card to card
connector located on the non-pin side
of the card and provides for card to
card connect ions or a single wide Tee
connects Tee card pins within a card.

LGND 10

CU-PS-Ol-Jl-3

(pin 3 of connector Jl)

CU-L/R-P2-2

(pin 2 of connector P2)

TU-DO/Dl-Al-ClBll

(pin Bll of position Cl)

TU-PS-Ol-Pll-3

(pin 3 of connector Pll)

TU-PSl-J2-9

(pin 9 of connector J2)

TU-DO-Pl-WA2-D05

(pin DOS of connector WA2)

TU-OO ....
TU-Ol ....
TU-OO/Dl
2A-OO/Ol

Legend
3480 MI

EC336396

© Copyrignl IBM Corp 1984. 1985; 1986. 1987

LGND 10

Legend
The following figures show how to locate parts In the 3480 documentation, uSing the identifying numbers that are shown in "Examples of
the Second Format" on LGND 10.
For the part location area that IS used in the logics, the figures show where they are located In the 3480 subsystem by referencing the
"Table of Contents" entry In the LOC and CARR sections of the Maintenance Information. The LOC and CARR sections "Table of
Contents" may not be the exact name or FRU number of the part referenced in the logiC, however the page referenced by the "Table 01
Contents" will relate to the part you are looking for.
These figures also show where a part can be found in the logiCS. For example, if the power is suspected to be a problem, you can look
for power parts (CBs, Power Supplies, and so forth) and find the logic pages that show these areas.

Control Unit location Area Definitions

LOGIC
LOCATION
AREA
IDENTIFIER

LOGIC
LOCATION
AREA
IDENTIFIER

DESCRIPTION

LOC I
TABLE OF CONTENTS
REFERENCE

LOGIC
PAGE

A2C2W22

Single wide TCC
AAOOI
OIA-A2 Top Card Cables
board position C2 CA002
row W, pin 22
WAOO5/006

FRUI70

A2Y2

Logic board
connector Y2 at
top of board

AAOOI

OlA-A2 Top Card Cables

FRU140

OlA-A2 Top Card Cables

FRUl40

CARR I
TABLE OF CONTENTS
REFERENCE

A2Z2

Logic board
connector Z2 at
bottom of board

AAOOI

DESCRI PTION

LOC 1
TABLE OF CONTENTS
REFERENCE

lAP I

Connectors
for gate fans

YFOO5

Fan Assemblies
I and 2

FRU165

Diskette
Drive

Diskette drive

WZOOl/OO2 Operator Set Up Panel

+24v
Service
Switch

Servi ce switch

ZT020

CU-AI Logic Gate
(Hinge Side)

FRUl62

Fans
(Gate)

Gate fans

YFOO5

Fan Assembly 1
Fan Assembly 2

FRUl50
FRU151

Al

Logi c board

AAOOO
AAIOO

OIA-AI Logic Board

FRUl39

L/R

Local/remote
power panel

YFOZO

Operator Set Up Panel

FRU084

AIA2

Logic board
pos it i on A2

AAOOO

OIA-AI Logic Board

FRUl39

-J I

Connector

YF020

Operator Set Up Panel

-J2

Connector

YF020

Operator Set Up Panel

AIY2

Logic board
connector Y2 at
top of board

AAOOO

OIA-AI Logic Board

FRUl39

Local
Power
Enable

Loca I power
enable

YF020

Operator Set Up Panel

AIZ2

Logic board
connector at
bottom of board

AAOOO

OIA-AI Logic Board

FRU139

MD
Connector

CU connector for
MD attachment

WXOOI

MD Connector

FRUl69

OP

Operator panel

Operator Set Up Panel

FRU142

AIYCDE

AIZFG

A2

Single wide TCC
AAOOI
board position P2
row y

OIA-AI Top Card
Connectors and Cables

FRUI8I

TCC row y
across board
positions C-E

AAOOO

OIA-AI Top Card
Connectors and Cables

FRUl93

TCC row Z
across board
positions F-G

AAOOO

Logi c board

OIA-AI Top Card
Connectors and Cables

FRUl87

AAOOI
AA200

OIA-A2 Logic Board

FRUI40

AAOOI

OlA-A2 Logic Board

A2A2

Log i c board
position A2

A2C2W

Single wide TCC
AAOOI
OlA-A2 Top Card Cables
board position C2 CAOO2
row \oj
WAOO5/006

3480 MI

EC336396

FRU140
FRUI70

LGND 15

Legend

LGND 15

CARR 1
TABLE OF CONTENTS
REFERENCE

LOGIC
PAGE

AIP2Y

Legend

FRU086

--

-JI/J2

Connector

WZlO6

-J2/P2

Connector

WZlO6

-J5

Connector

YFOl5
WZlO6

Operator Set Up Panel

FRUl42

-Power
Power on
Onindicator
Indicator

YFOl5

Operator Set Up Panel

FRUl42

-(Sub)
System
Power
Swi tch

(Sub) system
power switch

YFOl5

Operator Set Up Panel

FRUl42

-UEPO
Switch

UEPO switch

HOl5

Operator Set Up Panel

FRUl98

C

G

0

C

()

C

C

C

C

Legend

legend

Control Unit location Area Definitions (Continued)
LOGIC
LOCATION
AREA
IDENTIFIER
OSU

DESCRIPTION

LOGIC
PAGE

Operator
(controller)
setup panel

_"A"
Channel
Type
(Mode)
Sw itch

Channel type
(mode) switch

_"B"
Channel
Type
(Mode)
Switch

Channel type
(mode) swi tch

_"C"
Channel
Type
(Mode)
Switch

Channel type
(mode) switch

WZI02

WZ102

WZ104

LOGIC
LOCATION
AREA
IDENTIFIER

DESCRIPTION

LOGIC
PAGE

LOC 1
TABLE OF CONTENTS
REFERENCE

CARR 1
TABLE OF CONTENTS
REFERENCE

-CUO/CUl
Swi tch

CUO/CUl sw itch

YF010

Operator Set Up Panel

FRU197

LOC 1
TABLE OF CONTENTS
REFERENCE

CARR 1
TABLE OF CONTENTS
REFERENCE

Operator Set Up Panel

FRU141

-CU "A"
Address
Switch

Channel address
sw itch

WZ102

Operator Set Up Panel

FRU197

Operator Set Up Panel

FRU141

-CU "B"
Address
Switch

Channel address
sw itch

WZ102

Operator Set Up Panel

FRU197

-CU "c"
Address
Switch

Channel address
switch

wZl04

Operator Set Up Panel

FRU197

-CU "0"
Address
Switch

Channel address
switch

WZ104

Operator Set Up Panel

FRU197

-CU Error
Indicator

CU error indicator

YF010

Operator Set Up Panel

FRU141

-CU Onl ine
Switch

CU onl ine switch

YF010

Operator Set Up Panel

FRU141

Operator Set Up Panel

Operator Set Up Panel

FRU141

FRU141

-Channel A Channel disable
Disable
indicator
Indicator

YF010
(Sheet 1 )

Operator Set Up Panel

FRU141

-CU
Waiting
Indicator

CU wait indicator

YF010

Operator Set Up Panel

FRU141

-Channel A Channel
Enable/
enable/disable
Disable
switch
Swi tch

YF010
(Sheet 2)

Operator Set Up Panel

FRU141

Channel type
(mode) switch

WZ104

Operator Set Up Panel

FRU141

-Channel B Channel disable
Disable
indicator
Indicator

YFOIO
(Sheet 1 )

Operator Set Up Panel

FRU141

-"D"
Channel
Type
(Mode)
Switch

DC power on
indicator

YF010

Operator Set Up Panel

FRU141

-Channel B Channel
Enable/
enable/disable
Disable
switch
Switch

YF010
(Sheet 2)

Operator Set Up Panel

-DC Power
On
Indicator
- I ML!Power
On Reset
Swi tch

IML/power on
reset switch

YF010

Operator Set Up Panel

FRU141

-Channel C Channel disable
Disable
indicator
Indicator

YF010
(Sheet 1 )

Operator Set Up Panel

FRU141

-Jl/Pl

Connector

Operator Set Up Panel

FRU141

-Channel C Channel
Enable/
enable/disable
Disable
switch
Switch

YF010
(Sheet 2)

Operator Set Up Panel

FRU141

WZ106
YF010
(Sheets
1 and 2)

-J2/P2

Connector

Operator Set Up Panel

FRU141

-Channel D Channel disable
Disable
indicator
Indicator

YF010
(Sheet 1)

Operator Set Up Panel

WZ106
YF010
(Sheets
1 and 2)

-n/P3

Connector

YF010
(Sheet 2 )

Operator Set Up Panel

FRU141

-Channel D Channel
Enable/
enable/disable
Disable
switch
Switch

YF010
(Sheet 2 )

Operator Set Up Panel

-J4/p4

Connector

YF010
(Sheet 2 )

Operator Set Up Panel

FRU141

-J5/P5

Connector for
thermal jumper

YF010
(Sheet 2)

Operator Set Up Panel

FRU141

3480 MI

EC336395

~ CopyrIght IBM Corp. 1984, 1985

FRU141

FRU141

FRU141

legend

0
LGND 20

LGND 20

Legend

Legend

Control Unit Location Area Definitions (Continued)
LOGIC
LOCATION
AREA
IDENTIFIER

LOGIC
PAGE

LOC 1
TABLE OF CONTENTS
REFERENCE

CARR 1
TABLE OF CONTENTS
REFERENCE

Connector

WK006
WT003
WW010

CU-P2 Cable Connectors
(Dual Control Unit
Communication
Connectors)

FRU150

Power supply

YFOOI
YF003

CU-PSOI
(two different types)

FRUI44

DESCRIPTION

DESCRIPTION

LOGIC
PAGE

LOC 1
TABLE OF CONTENTS
REFERENCE

CARR 1
TABLE OF CONTENTS
REFERENCE

-Local
Power
Enable
Switch

Local power
enable switch

YF010

Operator Set Up Panel

FRUI41

-Offline
Indicator

Offline indicator

YF010

Operator Set Up Panel

FRU141

-CBI

Circuit breaker

YFOOI
YF003

CU-PSOI
(two different types)

FRU144

-Test/
Normal
Switch

Test/Normal
switch

YFOIO

Operator Set Up Panel

FRU141

-CB2

Circuit breaker

YFOOI
YF003

CU-PSOI
(two different types)

FRU144

CU-Pl Read/Write
Bus Connectors

FRU150

-CB3

Circuit breaker

YFOOI
YF003

CU-PSOI
(two different types)

FRU144

WT004
WTo06
WW020

CU-Pl Read/Write
Bus Connectors

FRU150

-Fl

Fuse

YFOOI
YF003

CU-PSOI
(two different types)

FRU144

WTOOI
WW010

CU-Pl Read/Write
Bus Connectors

FRU150

WW020

CU-PI Read/Write
Bus Connectors

FRUI50

PI
-AI

-A2
-Bl

Cable panel
Connector

Connector
Connector
Connector

WW010

CU-Pl Read/Write
Bus Connectors

FRUI50

-JI

Thermal connector

YF015

CU-Pl Read/Write
Bus Connectors

FRU150

CU-P2 Cable Connectors
(Dual Control Unit
Communication
Connectors)

FRU150

CU-P2 Cable Connectors
(Dual Control Unit
Communication
Connectors)

FRUI50

WTo08
WT010
WW020

CU-P2 Cable Connectors
(Dual Control Unit
Communication
Connectors)

FRUI50

WK005
WW010

CU-P2 Cable Connectors
(Dual Control Unit
Communication
Connectors)

FRUI50

CU-P2 Cable Connectors
(Dual Control Unit
Communication
Connectors)

FRUI50

-AI

-A2

-A3

-A4

3480 MI

-A5

PS-OI

-B2

P2

1)

LOGIC
LOCATION
AREA
IDENTIFIER

Cable panel

Connector

Connector

Connector

Connector

WW020

WKOOI
WK003
WK005
WW010

-Jl-J4B

Connectors

YFOOI
YF003

CU-PSOI
(two different types)

FRU144

-J9-Jl0

Connectors

YFOOI
YF003

CU-PSOI
(two different types)

FRU144

-J 11

Connector

YFOOI

CU-PSOI
(two different types)

FRU144

CU-PSOI
(two different types)

FRU144

-JI3-JI5
PS-02

Connectors

YF003

Power supply

YF002

CU-PS02

FRU145

-CBl

Circuit breaker

YF002

CU-PS02

FRU145

-CB2

Circuit breaker

YF002

CU-PS02

FRU145

-CB3

Circuit breaker

YF002

CU-PS02

FRU145

-Fl

Fuse

CU-PS02

FRU147

-F2

Fuse

YF002

CU-PS02

FRU148

-Jl-J20

Connectors

YF002

CU-PS02

FRU145

-Kl

Relay

YF002

CU-PS02

FRU145

Tl

Tai 19ate

AA002
ATIOO

I/O Tailgate Connector

FRU136, 137
233-238

T1AI

Tai Igate position
Al

AA002
IBOOI
IB002
IB003

I/O Tai 19ate Connector

FRUI36, 137
233-238

TIA3Y

Tag shoe card
connector y

IT003
WA004

I/O Tai Igate Connector

FRU137, 234, 236,
238

EC336395

Legend

LGND 25

LGND 25

CopYright IBM Corp. 1984. 1985

\

J

)

j

0

c

0

legend

0

0

0

0

--

c

Legend

lGND 30

Legend

lGND 30

Control Unit Location Area Definitions (Continued)
LOGIC
LOCATION
AREA
IDENTIFIER

LOC I
TABLE OF rONTENTS
RFFERENCE

CARR I
TABLE OF CONTENTS
REFERENCE

DESCRIPTION

LOGIC
PAGE

TlA3Z

Tag shoe card
connector z

ITOU3
WA005/006

1/0 Tai Igate Connector

FRUl70

TBI

Terminal block

ZTOIO

CU-Al Logic Gate
(hinge side)

FRUl60

TB2

Terminal block

ZTOII

CU-Al Logic Gate
(hinge side)

FRUl60

TB3

Terminal block

ZTOII

CU-Al Logic Gate
(hinge side)

FRUl60

Thermal
Switch
(Top of
gate)

Thermal switch

ZT020

Thermal Switch Assembly

FRU224

Thermal
Switch
(Bottom of
gate)

Thermal swi tch

YFOl5

Thermal Switch Assembly

FRUl43

3480 MI

EC336395

Legend

Legend

Tape Unit and Drive Location Area Definitions
LOGIC
LOCATION
AREA
IDENTIFIER

DESCRIPTION

LOGIC
PAGE

LOC 1
TABLE OF CONTENTS
REFERENCE

Logic board in
each drive in the
tape unit

AAOOO
AA100

02A-Al Logic Board Pin
and Card Side

FRU058

CBl

Circuit breaker
(primary power)

YF050
YF060

Tape Unit AC Power CB

FRU218

Compressor

Compressor

YF050
YF060

Major FRU Locations
50/60 Hz

FRU030

DC Switch

DC swi tch
(these are additional contacts
on the drive fan
and power switch)

SNOOl/002
(Sheet 2)

Tape Unit Locations

FRU104

Plug

SNOOl/002
(Sheet 2)

Al

-PI

OK

Deck assembly

Drive Locations
SNOOl/002
(Sheet 1)

Cartridge latched
sensor and LED

-Cartridge
Present
Sensor
and LED

Cartridge present
sensor and LED

-File Reel
Tach

File reel tachometer

SNOOI/002
(Sheet 2)

File Reel Motor

-FPSW

Deck assembly
file protect
switch

SNOOI/002
(Sheet 2)

File Protect Switch

Connector for
tension
transducer

PAOOO/OOI
(Sheet 2)

Tension Transducer

-Machine
Reel Tach
Phase A
Sensor
and LED

Machine reel
tachometer phase
A sensor and LED

SNOOI/002
(Sheet 1)

Machine Reel Tach
Sensor A

-Machine
Reel
Phase B
Sensor
and LED

Machine reel
tachometer phase
B sensor and LED

-PI

Connector for
tape path
sensor A

3480 MI

SNOOI/002
(Sheet 1)

SN001/00l
(Sheet 1)

SNOOl/002
(Sheet 1)

Cartridge Latch
Assembly

Cartridge Present
Sensor

Machine Reel Tach
Sensor B

Tape Path Sensor A

FRUOll

FRU010

FRU003
FRU009

FRU014

FRU225

FRU226

FRU006

DESCRIPTION

LOGIC
PAGE

LOC 1
TABLE OF CONTENTS
REFERENCE

CARR 1
TABLE OF CONTENTS
REFERENCE

-P2

Connector for
tape path
sensor B

SNOOl/002
(Sheet 1)

Tape Path Sensor B

FRU007

-P3

Connector for
cartridge present
sensor and f i Ie
protect swi tch

SNOOI/002
(Sheet 1
and 2)

Cartridge Present
Sensor and File
Protect Swi tch

FRU010

-p4

Connector for
cartridge latched sensor

SNOOl/002
(Sheet 1)

Cartridge Latch
Assembly

FRUOll

-P5

Connector for
machine reel tach
phase B sensor

SNOOI/002
(Sheet 1)

Machine Reel Tach
Sensor B

FRU226

-P6

Connector for
machine reel tach
phase A sensor

SNOOl/002
(Sheet 1)

Machine Reel Tach
Sensor A

FRU225

-P7

Connector for
fi Ie reel tach

SNOOl/002
(Sheet 2)

Fi Ie Reel Motor

FRU003

-Plenum
Press Sw

Plenum pressure
sensor swi tch

SNOOl/002
(Sheet 2)

Plenum Assembly and
Pressure Switch

FRuo40

-Tape Path
Sensor A
and LED

Tape path sensor
A and LED

SNOOl/002
(Sheet 1)

Tape Path Sensor A

FRUo06

-Tape Path
Sensor B
And LED

Tape path sensor
B and LEO

SNOOI/002
(Sheet 1)

Tape Path Sensor B

FRU007

-Tray
Solenoid

Cartridge latch
solenoid

YG010
YG 110

Latch Sensor

FRU002

Drive Fan
and Power
Sw itch

Orive fan and
power switch

YF020

Tape Unit Locations

FRU104

DSP

Message display

Operator Control and
Display

FRU021

Ready/Not Ready Switch

FRU109

FRU104

-Cartridge
Latched
Sensor
and LED

-J14

CARR 1
TABLE OF CONTENTS
REFERENCE

LOGIC
LOCATION
AREA
IDENTIFIER

-Jl

Connector

WOOOO
WOOOI

-J2

Connector

WOOOO
WOOOI

-J3

Connector

WOOOO
WOOOI

-J4

Connector

WOOOO
WOOOI

-Ready
Swi tch

Switch

WOOOO
WOOOI

EC336395

Legend

.

o1111'1Ol/"'''
:m::g;~~z

All

AO,

0(.,Il107/......
~x_oo

_

I'IPOO,

'(PI"'08/~

(
Il109/_
I
I'I'O/A7'>.

kR "DOAUS ['(TEND BIT 0

.... px_o, _ XII ADOAESS
E'TEND BIT ,

"'001

I
ClUBb.
I

~X'--OOO -

lIR lDAD
CSOO1
_xAACOO
- lIR AfAO ;ATE
_X _ _

,",,00,

,",00,
..,OIAGOO -

"'00'
"'00,

~ItRSOO -~soo

1't'2/1'~

I
C' l/12o.
I

lIR ~ITE ;Are
OI~TIC

IIODE

C10/1~

I
C09/_

0tE CK RESET

I

-

_DwARE REst:T
IIPOO1 WCOO4

ICSII~Clt04 -

CSOO1

fICC)

r:~

;08/82>I
D,l/Blob.

IF two ClOCk S2-S3

II

-s

:l~~~m~
:a%~m:&

"14/1'07(":&
""/1'09'"
"'611>'0161;
"'711'" (71
.. 'B/P12(PI
I

002/'" 3_

"1
S

I
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c.zz/", ~

S

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c:..J/CO••

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"0 CARO (TCCI

",l1F,..s

-

m

WOF DQTA

}.
~7.P

~IOle03/DI
~I' 1004/01

(I' .0-71 BAOO1

IWIlI'ENO
!!AOO'

-"OF

~~~~~~~~~

l'

21 80./ 02 1
131D05ID3
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&(51 DOb/D51
(61 807/0.
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671u,3(9BI

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1
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O""'ENT
VOL. TACE PINS • •
2 +1 .71/ 111. S1'
3
+,v DOl, J03. P03. U03
CND D08. .JOI. poe. U08
I> CND I0I01>. 1111" W2" 11129
7 CNO leoe-.
a •• W29
e ;ND Y06. "11 , Y2." Y29
I 9 eND 106· Z11. 12', 129
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ourJCCTcnS
IP2B"
D00511 A-Q, /1'28"

,•

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0
0

,

I
I

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3480 MI

EC336396

.1)2c"

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'3/Z121]I-o
.1123141:&

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51Z0Z_

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01002

+ DATA ClOC. ---------SIoIDDVCItOO
+ DHIVE ClUCK
SIoIODICItOO

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pRI-22DEC82 0733

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N(xTBLk DC

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IoIAITE DATA --------l&"'''DDATAOO

(0-9101002

~5~o-J5'/Z32 ••------~-----------

CONTROl. ~tT - A' 80RAD
.... ITE DATA Fl(lJ

USN ooolf>

.pv .... , .1

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--- + I'llx

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.... ITE DATA FL.OW

D

SHEET _47'6264 EC-llJ274
D
f

0
0
Z
000'

LOC-'_ P2
USN 00031>

I AlOCIPFUR .... SEB
fItQC,... SACt I
CIO ItSCAD
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1m

PAI-22DECe2 073l
SEC
N[XTBLK DE
..De

I(

St;A.IPlJl

D

II 00F
I1000'2

Legend

LGND 65

Legend

LGND 70

Legend
Logic Diagrams (Continued)

Bundled Lines
Bundled lines combine Ihe billines in a bus and represenl the
bus as a single line. The bit lines in the bundle are identified by
a 'short-hand' notation. The (P,O-7)
Indicates that a parity bit
and bits 0 through 7 are included In the REMOTE CU ADDRESS

D

D

following the 'short-hand' notation
BUS. An asterisk (")
(P,O-l) indicates that the bit lines are defined in the information
area
at the bottom of the logic diagram.

0

D

The PINS columns
in the information area define the pins for
each bundle on the diagram. Pins 10/J13 through 1B/P04
represent the pins contained in the REMOTE CU ADDRESS BUS
bundle
The parity bit Is on pin 10/J13 (low order zeros do
not appear on the diagram for logical pins
and
and the 7
bit is on pin 1B/P04.

D·

0

II)

'"

D
:;;~:

----: : : : : :::T-ED---------------------P'lo4>":::

...001
_'510000
... AEI'Ol[ CU SEND
... 001
+ AlEI'Ol( CU lie_EDGE

~~OO

~ 'CP.«>-71.,
...- - - - - - - - - - - - - - -

------------------uo.,..
, ------------------------U05l1'

- - ... RUUTE CU

CP.o-71,,",OO]

ADDRES~

illS - - -... R"'ADROO

EJ

P'lZlAZ

"-

- - - - - - - - - - - - - - - - - + AE"UTC

'~D

".<-,,~~

~

Logical/Physical Pins

tu DATA IlUS - - - - - t s .... UuSoo

""'001 ... LOCAL CO ....

~TE"

------tILCLI'ISTOO

]'11>05,••- - - - - - - - - - - - - - - - WKOO1 ... LOCAL CU CONNECTED

D.

Pins are identified by logical pin notation and pin number
J02 is the physical pin. The 34 is a logical pin notation and is
used for engineering purposes only. Low order zeros are not
used for logical pin notation. For example, logical pin 10 = 1, 20
= 2
and
and so on.

0

/

P'I lJ'1Il

IPSPORSOO - I>QWER ()OI RESET

~~C~O~O(
IIPOO,

fJ
CARD CICC!

II,

relate~

to

the PINS column •.

10
11
12
13
14
15
16

17
18

J13
G10
G12
G1]
M02
MO]
M04
P02
P04

bit
b t
b t
b t
b t
b I
5 b I
• 6 b I
• 7 b I

•
•
•
•
•
•
•

P
0
1
2
3
It

"'00' ... L~ CU SEND

]111>07.

,,",00,

]./.J02tI

",00] ...

+~

CU

I'E~

ILCLC:OOOOO
.LCLSNOOO

QCJ(N~EDcE

.... llE

~IC,",,-

ILCLAO09.

J

./80§
, .2M)

.,NOt.~I----------------

'I

-- . . aJ OFFLINE

DOTTED - ... Z-001-.-SS..
~~,JOFI'LOO

lON1H{)l ufljlT
Al thlAALJ


I",oe.

II

I

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I
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SEC

IPFOR"'.I(~eB
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5
"'0

0

'
000'

EC336396

': COpyrlghllS". Corp 1984. 1985. '986. '987

Legend

)

LGND 70

J

o

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c

Legend

Legend
Logic Diagrams (Continued)
Logic diagrams show the input and output pins of each card.

olD,

D,

To differentiate between a driver (source) and receiver (sink) for
non-directional (BI-Oll lines on the right side of a logic diagram:
1.

2.

01A-A2C2

All logic diagram page references, except those beginning
with "W" (WA001, WC0061. that are followed by an
asterisk (.) are other driver logic diagram pages for the
receiver.
All logic diagram page references, except those beginning
with a "W" that are not followed by an asterisk are the
receiver logic diagram pages from the driver.

In this diagram the logic represents a wire-to-wire path. not a
logical flow path. The only output from the four CA cards is to
~ic page BAOO 1
The drive logics are on CA pag~ iii. WC005/6
and the receiver card on BAOO 1 ..--

B.
B Ilf.

- LOCAL BUFFER SERVICE

Logic

I

CAOOI

our

The '- LOCAL BUFFER SERVICE
linp.s un logic d~ram
pages CAOO 1
CA 1
CA201
and CA301 iii appear
to be output lines exiting the logic page and going to another
page. However, instE!ad of being inputs to other logic pages, the
lines are all outPuts that are "Dot-OR' ed" together.

LGND 75

I

D
013- -LOCAL BUFFER SERVICE OUT-$SERVOLOO
CA10l*CA201*CA301*WC005

Dot OR's of Output Lines

II,

Not I
Shown
I In I

c

o

-------------------------~

B

$SERVOLOO
BAOOI

$SERVOLOO - LOCAL BUFFER SERVICE OUT
CAOOI CA10l CA201 CA301

I

01A-A202
013- -LOCAL BUFFER SERVICE OUT-$SERVOLOO
CA001*CA201*CA301*WC005
CA10l

--------------------------

01A-A2V5
Local
1 - - - - - - - - - 0 0 3 Port

01A-A1V3
Local
Port

WC005/6

WC005/6

01A-A1K2

- 003---------J04
BAOOI

01A-A2E2
013- -LOCAL BUFFER SERVICE OUT-$SERVOLOO
CA001*CA10l*CA301*WC005
CA201

$SERVOLOO

-------------------------~

II

01A-A2F2

- LOCAL BUFFER SERVICE OUT
WC005

---------1---------

013- -LOCAL BUFFER SERVICE OUT-$SERVOLOO
CA001*CA10l*CA201*WC005
CA301

Test Points
Some logic card outputs are test points and connect only as far
as indicated in the logics. These lines are represented by having
a "TP" or "T.P." in the line name.

3480 MI

EC336395

Legend

LGND 75

Legend

Legend

LGND 80

Field Wire Net Lists
The Field Wire Nets Lists, show the following for the 01 A-A 1
and 01A-A2 boards:

Pin to Net List
DATE -

Net to Pin List

01/26/82

-

FIELD WIRE NET LIST

~W~*W**WWWW*****************************N************* WNW._WWW._.

PART NO.
EC
NO.

Pin to Net List

0004741673
000991666A

WNW.WWWWWW • • •

II

Net to Pin List

3381383C 1183D0583Dl083E0483ElO84A0584AIO8480384B13B4C038'.D0284D0784D12-

Voltage Distribution List

Pin to Net List
To determine which net contains a specific pin:

g.

1.

Find the pin number in the PIN column

2.

The column to the right of the pin number is the NET
column
that lists the net the pin is included in.

84Ea~-

3.

EJ

EJ

indicates that the pin
A 'Y' to the left of the pin number
is a voltage pin. Such a pin will also be referenced in the
Voltage Distribution List.

Net to Pin List
To determine which pins are included in a net:

85A0685802851l078581285C0585C 1185D0485D038501285E0686A02861302V 86C0386E03CIBIOCICI3CIEI4C2A05C2B03-

Elv

Find the net number in the ENG. NET NO. column

2.

The two columns to the right of the net number, the FROM
and TO columns
contain a listing of the pins included in
the net. They also indicate the order in which the pins are
connected.

O.

Voltage Distribution List

PIN

NET

$CUBSEL 00
. ·:UBCKAOO
SCUBCKAOO
SIFBSTIOO
SCUAI3US
01
SCU8CKAOO
$CU8BUS
02
SSCL TCI~OO
SSNDAOROI
S!FI3SELOO
SSNDADROI
S!FITLEVIOI
SMPXREG2901
S!FINTREQ
$CU3BUS
02
SCUIlCKIlOO
SIF,IROATAOO
$1 F,IROATA04
SIFWROATA08
SIFASELOO
SCAPORSTM
$IFCLK800
IFOOOBAI0
IFOO08AIO
SCU81lUS
03
SSWITCHM4
SSCRSETAM
PAOOIAAB2
$SCLTCCOO
$SCLEDI04
SSCXROATA08
$SCXRDATA07
$SWITCH
SC

B3B14B3C14B3D0683Dl1B3E05B3EllB4A0684All84B04B4B1484C04B4D04B400984D1384E0685A07851l03851l0885B1485C0685C128500585D0985D1385EIOB6A03B6B03B6C05B6E05CIB

$CUllBUS
01
$SCPARSTM
$CUllCKBOO
$IFBRPIOO
SCUI3CKAOO
SCATRPORI1
$CUBCKBOO
SSCLTCWOO

A'.C09A4009A',E09A5E09A5009-

03
01
01
03
01

01. 775
00.125
00.12 S
01.809
00.125

K~Bl3-

K2801J2001J2006JZE02G2C02G5A1085ElQB SE I I-

K2B01J2001J2006nE02G2C02G5AIOBSEIOB5E11f) 5D 11-

03
01
03
03
01
03
aI
03
01

05.100
00.484
00.734
00.625
01.709
06.S00
02.775
00.12S
00.125

SIFBRPIOO

83DIIA3C12A4011A 5C 11-

A3C12A4D 11A 5C 11A5011-

01
03
03
01

00.875
01.750
01.875
00.125

SIF8SELOO

J2010JIDI2EIOI2E4C0404E04D4E13-

JIOI2EIDI2E'.C0404£0404E13B4B13-

03
01
03
01
03
01

01.6S0
02.650
04.684
00.484
01.275
01.775

~IFaIASilO

SS~WADR02

SCU8SELOO
SCU8C~IDOO

SIFITLEVI02
$MPXREG2902
S I FWEtWOO
SClJBBU5
03
SCUBGAPOO
SIFI~RDATAOI
SIFW~DATA05

$!FWRDATA07
$SCXRDATA04
SIFWRDATA02
$!FASELOO
IFOOOBAIO
SIFRASDATOI
$IFBIASOO
SSCLTCCOO
SIFW
S

- - --- -- - -- - - -- - - - - - - - - - -- - - - -- - -- - - - - -- - -- - - --- - - - - - - - --- -- -- - - - - - -- - - - --c~~--SIFBSTIOO

B3DIOA3E11A4010-

S!FCLKBOO

K4BIOG5All05AII05AOS-

Voltage Distribution List
DATE - 01/26/82
- FIELD WIRE NET LIST
w•••••••••• w_ ... * •••••••••••••• __ •••••••• _--_ ••••••••• WN._._ .... W
PART NO. 0004741673
EC
NO. 000991666A
(41)
w*w*****~**************M.***.***********.************* **-* •• *._**

Note: The VOLTAGE column
shows the different
voltages that are supplied to the boards. +08500
means +8.5 Vdc. and so on.

0

+10500

3480 MI

A3CIOA4C09A4D09A4EQ9A5E09-

------------------------------------------

The Voltage Distribution List. references the voltage levels and
the pins that are supplied by that specific voltage level. See the
"Voltage Tolerance Tables" in the PWR section for the specific
voltage level tolerance.

ill

FIELD WIRE NET LIST -

NODE NAME CR

NO

IlJVOLTAGE

III

-

(41)

I).

1.

01/26/82

_* ___ •••• ****_* •••••••••••••••••••••••••••••••••••••

EJ

PIN

DATE -

VOLTAGE DISTRIBUTION LIST
PIN
PLANE
X
G2D03
J2003
J3AOI
J3D03
J4AOI
J4003
J5AOI
JSD03
K4D03
K5D03
B2AI4
B3AI4
9'. A 14
r?B I I
D2B II
03 B I 1
0', B 11
05 B I I
E 2111 I
E 301 I
E4 B I I
E5BI I
F2811
F 3 B1 I
F 4 III 1
F5BII
J2AI4
J 281 I
J3AI4
J4AI4
K 58 II
G2D04

03
03
03
03
03
03
03
03
03
OJ
03
03
03
D3

03
03
03
01
03
03
03
03
03
03

03
03
03
03
03
03

+01.0000
+01.0000
+02.5000
+02.7500
+04.2S00
+04.5000
+06.0000
+06.2500
+04.S000
+06.2500
+02.3750
+04.1250
+05.87S0
+02.DaGa
+02.0000
+03.7500
+05.500e
+07.2500
+02.0000
+030 7500
+05.5000
+07.2S00
+02.0000
+03. 7500
+OS.SOOO
+07.2500
+02.3750
+02.0000
+04.1250
+05.8750

v
+04.2500

+05.5000
+05.1250
+05. SOOO
+05.1250
+05.5000

+05.1250
+05.5000
+06.1250
+06.1250
+00.7500
+00.7500
+00.7500
~Ol.5C~O

+02.12S0
+02.12S0
+02.1250
.02.1250
+02.7500
+02.7500
+02.7500
+02.7500
+1)3.3751)
+03.37S0
+03.3750
+03.37S0
+OS.12S0
+05.2S00
+05.1'

EC336395

Legend

CopyrighllBM Corp. 1984. 1985

)

}

LGND 80

o

o

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o

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Support Procedures • . . . • . • • • . . . . • • • • • • • • • • • • • . • . . . . • . • • • • . .• 2
Start •••••...•••.••••••.••..•.•.•.••••.•.......•••.•..• 2
Introduction to Support Procedures . • . • . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Support Maintenance Package •••..•.•.•.•••••..•••..•••••••.. 2
When to Use !he Support Maintenance Package . . • • • . . . • • . . • . . . . . . . • 2
Transition from the Product Maintenance Package to !he Support Maintenance
Package ••••••••••..•••••..••.•.•••..••••••• o' • • • • • • •• 2
Data That Can Be Available •.•.••••.••••••••.••••••••••••.••..• 2
Data Analysis ••••.•••••....••••••••.••••••.•••••••••••... 2
Rechecking Actions •••••••..•••••••••••••••••.•..•.•••••• ~ •. 4
General Problem Definition Diagnostics .••••••••.••...•••••••••••.• 4
End of Call Actions • . • . . • . . . . . • . . . . . . . . • • . . . . . . • . . • . . . . . . . . • 4
Failure Has Not Been Repaired ••••..••.•••••••••.•••••••.•••.• 4
Failure Has Been Repaired •.•••.•.•••••••••••••••.•••..•••.• 4
Isolation Procedures •••.••••....••••••..••••••••..•..•.•••. 100
Isolation Procedures A ••••••••.•••••..•••••••••••••.•••••• 100
Isolation Procedures B ••••.•••••••••••••••••.•••.••...•.•• 110
Isolation Procedures C ......•••.•••.•••••••••••••••••••.•. 120
Isolation Procedures 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Isolation Procedures E •.••••••...••••••••••••••••••••••••. 140

3480 MI ECA57723

o

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Contents

ORoe 1

Contents

SPRoe

..

IBM COI\lfIdential

C Copyright IBM Corp. 1112.1181

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1

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Contents
Support Procedures
SI,ul
InlroriuclllJn 10 Supporl ?rocp.tlur"!;
Supporl Mamtp.nancp. Package
Whp.n 10 U<:P. Ihe Support Malnlp.nan!:p. Packaqp.
Tran~lllon from Ihp. ProducI Mmnlpnancp. P:lckaqp to th" Support Mmnt"na,,' ...' Pack:1QP
Oat:! Th:lt C:ln Bp. Avml:!hl"
Oat:! AnaIV!lI~
Rp.checklnll Acllons
General Problp.m Definotlon DI:lllnostlc~
End of Call ActIons
Faolure Has Nol Been Repaorp.d
FaIlure Has Been Rppaired

:14110 MI
E'! "I'VI'uhl 111M I "'I'

l~Ul.1

1'.111",

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Contents

SPRoe 1

Contents

SPRoe 1

2
2
'}

1
'}
)

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4
4
4
4
4

Support Procedures

Support Procedures
Introduction to Support Procedures

Start

The information in Volumes A04 and A05 of this maintenance
information make up the support material for the 3480
Magnetic Tape Subsystem. Each of the tabs within these
volumes represents a section of information that aids the service
representative in problem determination and repair at the
support level.

Have you used the support maintenance
package recently?
If not, see "Introduction to Support Procedures" on the page.

I

The support service representative should already be thoroughly
familiar with the information in Volumes A04 and A05. In
addition, the product service representative can, with aid, use
this information in troubleshooting when the product
maintenance package fails to isolate a subsystem problem.

Verify that the product service representative followed all procedures and exchangall FRUs as identified by the product
maintenance package.

Support Maintenance Package

I

The support maintenance package supplies the service
representative with a support diskette and documentation that
can be used to isolate difficult subsystem problems. The
support diskette gives the service representative the ability to
select and run specific diagnostics or utilities. The support
documentation supplies maintenance information beyond the
scope of MAPs and procedures used by the product service
representative.

Collect the data that is available.
(See "Data That Can Be Available" on this
page. )

I
I

The support maintenance package is intended to be used when
the product maintenance package fails to repair a problem. The
support service representative can use it by itself if the MD is
not available or is not operable. However the support
maintenance package is entered, it contains both reference
material and action-oriented material. You should enter the
package at the block marked 'Start' on this page and follow the
steps as they continue to other pages.

Use any new data or observations and return to the product maintenance package
"START" section using the new information.

•

Power is missing or out of tolerance at the point of failure.

•

Connections between FRUS (cables, connectors, top card
connectors, or board wiring) have short circuits or open
circuits.

New data or observations used by the product maintenance package can cause the
product maintenance package to develop a
new FSC.

•

A FRU exchanged by the product service representative is
defective.

•

A design problem exists in the hardware, the microcode, or
the maintenance package.

•

No trouble was found .

•

Failures occur during installation or after EC rework .

Next Page

Some messages are abend codes. Look for other
IEAOOOI messages, or EREP for the failing address.
The IEAOOOI messages and EREP provide useful sense
data for troubleshooting (see the MSG section).
•

Console messages and EREP
Look for multiple records.
Are there earlier sense records for the failing address
with different sense data (it is possible that after the
original failing sense data, later sense data can indicate
the effect of the problem, not the cause)?
Do multiple FSCs relate to a common problem?

•

•

Are FSCs common or similar for the drives on the same
subsystem?

Fault symptom codes (FSCs) that are supplied by the
product maintenance package. See PLAN 1 for "3480
Maintenance Package Summary."
System console messages. See MSG 1 for "How to Use
OS/VS/MVS System Console Messages."

Check for possible common control unit problems.
•

For two control unit configuration
Was the MD connected to the correct control unit?

Drive message displays. See PANEL 1 for "Message
Display Messages."
EREP output. See MSG 1 for "Environmental Recording,
Editing, and Printing Program."
•

Were the FRUs exchanged in the correct control unit?
See the MSG section for "Error Path Isolation."

OL T messages. See IBM 3480 Online Tests (OL Ts),
099-3480.
Audio-visual indications of the subsystem or media.

•

I

Console messages

Data That Can Be Available

Use the support maintenance package to correct failures that
were not repaired using the product maintenance package. The
following kinds of failures may require use of the support
maintenance package.
The FRUs identified by the product maintenance package
were not exchanged, or procedures were not followed as
directed by the product maintenance package.

Some items to check in the data analysis are:

This Support Procedures section of the maintenance information
contains the information about how to proceed to gather
appropriate information, how to analyze that information, and
how to use the action-oriented Fault Symptom Index (FSII. EAD,
and DIAG sections.

When to Use the Support Maintenance Package

Analyze the data collected.
(See "Data Analysis" on this page.)

3480 MI

Transition From the Product Maintenance
Package to the Support Maintenance Package

Next level of support symptom file search.

Data Analysis

•

Is it consistent?

•

Does it indicate multiple problems?

•

Is the problem (or one of the problems) obvious?

•

Does the problem indicate system, programming, operator,
or other errors?

If the problem analysis indicates some obvious errors, correct
the obvious errors before you continue. If correcting the obvious
errors shows that wrong data was used in the initial attempt to
correct the problem, return to the product maintenance package
with the new data and start again.

Support Procedures

EC336395

~ Copyright IBM Corp. 1984. 1985

)

)

)

SPRoe 2

SPRoe 2

1

suppArocedures

o

o

o

o

Introduction to Support Procedures

Start
Hive you used the support matntenlnce
package recently?
If not, see "Introductton to Support Procedures" on the page.

1
Verffy thlt the product customer engfneer
fo 11 owed 111 procedures Ind exchanged
all FRUs as fdentfffed by the product
mafntenance package.

The information in Volumes A04 and A05 of this maintenance
information make up the support material for the 3480 Magnetic
Tape Subsystem. Each of the tabs within these volumes
represents a section of information that aids the customer
engineer in problem determination and repair at the support
level.
The support customer engineer should already be thoroughly
familiar with the information in Volumes A04 and A05. In
addition, the product customer engineer can, with aid, use this
information in troubleshooting when the product maintenance
package fails to isolate a subsystem problem.

Support Maintenance Package

Collect the data that fs available.
(See "Data That Can Be Avaflable" on thfs
page.)

1
Analyze the dati collected.
(See "Dati Analysis" on thfs plge.)

1
Use a".r new dltl or observltfons Ind return to the product IBtntenlnce pickage
"START" section ustng the new Information.

!
New data or observltions used by the product maintenlnce pickage cln cluse the
product maintenlnce pickage to develop a
new FSC.

The support maintenance package supplies the customer
engineer with a support diskette and documentation that can be
used to isolate difficult subsystem problems. The support
diskette gives the customer engineer the ability to select and run
specific diagnostics or utilities. The support documentation
supplies maintenance information beyond the scope of MAPs and
procedures used by the product customer engineer.

When

t~

Use the Support Maintenance Package

Use the support maintenance package to correct failures that
were not repaired using the product maintenance package. The
following kinds of failures may require use of the support
maintenance package.
•

The FRUs identified by the product maintenance package
were not exchanged, or procedures were not followed as
directed by the product maintenance package.

o

Transition From the Product Maintenance
Package to the Support Maintenance Package
The support maintenance package is intended to be used when
the product maintenance package fails to repair a problem. The
- support customer engineer can use it by itlRtlf if the MD Is not
available or is not operable. However the support maintenance
package is entered, it contains both reference material and
action-oriented material. You should enter the package at the
block marked 'Starr on this page and follow the steps as they
continue to other pages.

o

suP. Procedures

.OC2

Some items to check In the data analysis are:
•

Console messages
Some messages are abend codes. Look for other
IEAOOOI messages, or EREP for the failing address. The
IEAOOOI messages and EREP provide useful sense data
for troubleshooting (see the MSG section).

•

Console messages and EREP

Look for multiple records.
Are there earlier sense records for the failing address
with different lense data (it is possible that after the
original failing sense data, later sense data can indicate
the effect of the problem, not the cause)?

This Support Procedures section of the maintenance information
contains the information about how to proceed to gather
appropriate information, how to analyze that information, and
how to use the action-oriented fault symptom index (FSI), EAD,
and DIAG sections.

Do multiple FSCs relate to a common problem?
Are FSCs common or similar for the drives on the same
subsystem?
Check for possible common control unit problems.

Data That can Be Available
•

Fault symptom codes (FSCs) that are supplied by the product
maintenance package. See PLAN 1 for "3480 Maintenance
Package Summary. n

•

System console messages. See MSG 1 for "How to Use
OSNS/MVS System Console Messages."

•

Drive message displays. See PANEL 1 for "Message Display
Messages."

•

EREP oUlput See MSG 1 for "Environmental Recording.
Editing, and Printing Program."

•

OLT messages. See IBM 3480 Online Tests (OLTs),

•

Audio-visual indications of the subsystem or media.

•

Next level of support symptom file search.

•

For two control unit configuration
Was the MD connected to the correct control unit?
Were the FRUs exchanged in the correct control unit?
See the MSG section for "Error Path Isolation."

099-3480.

•

Power is missing or out of tolerance at the point offailure.

•

Connections between FRUs (cables, connectors, top card
connectors, or board wiring) have short circuits or open
circuits.

•

A FRU exchanged by the product customer engineer is
defective.

•
•

Does it indicate multiple problems?

•

A design problem exists in the hardware, the microcode, or
the maintenance package.

•

Is the problem (or one of the problems) obvious?

•

•

No trouble was found. •

Does the problem indicate system, programming, operator,
or other errors?

•

Failures occur during installation or after EC rework.

Data Analysis
Is it consistent?

If the problem analysis indicates some obvious errors, correct
the obvious errors before you continue. If correcting the obvious
errors shows that wrong data was used in the initial attempt to
correct the problem, return 10 the product maintenance package
with the new data and start again.

"

Next Plge

3480 MI EC A57723
o CopyrIfhllBM eorp. 1 . , 1 .

IBM C~dentlal

Support Procedures

SPROC 2

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Support Procedures
From

Page

Use the FSC developed by the product
maintenance package.
If you want to verify
this FSC, use the data gathered in the preceding step,s to develop a fault symptom
code (see 'Determinir.~ a Fault Symptom
Code" on START 300).
Use the fault symptom
code to find the error as listed in the
Fault Symptom Code Index (FSI) section.
Return here after you find the fault symptom code in the FSI and continue with other
verification actions first, before doing
any troubleshooting actions in the FSI
(see Note).

If you want to verify that the MD is connected to the correct control unit in a two
control unit configuration, or that the
FRUs were exchanged in the correct control
unit, see START 400 for "Error Path Isolation".

o

o

(;

o

o

Support Procedures

SPRoe 3

Support Procedures

SPRoe 3

ATTENTION
Take care in using the FSI. The FSI is designed on the
assumption that the identified error indicator is the
selected fault symptom code (FSCI. not just any error
code taken from the sense bytes. This means that if you
are to use the FSI for corrective action. the source of the
FSC must be the product maintenance package exit or the
result of following the "Determine a Fault Symptom Code"
(see START 300).
Any use of the FSI other than for FSCs developed as
stated above is for information purposes only. The 3480
develops many error codes in the sense data from the
same problem. Some codes define the original cause of
the problem. and other codes can be the result of
attempted error recovery actions. Because all codes are
not direct results of the original error. if you review an
error code not given by the product maintenance package
or not developed by following this FSC development
procedure. you could be troubleshooting the effect of the
problem. not its cause.
Note:
The SPRaC section procedures are used to
verify that you are in the correct functional area before
doing any more troubleshooting or corrective actions.
These actions are, for example, re-running the product
maintenance package if the newly developed FSC differs
from the original FSC, or verifying that the MD was
connected to the correct control unit during product
maintenance. If your are sure that the earlier actions
were correct and the existing information still points to
the same area, continue with the actions specified in the
FSI "Additional Action/Comments" column instead of
returning to the SPRaC block that sent you to this note.
However, after completing all the actions specified in the
FSI, you must return to SPRac 4 and follow "General
Problem Definition Diagnostics," and if necessary the
"End of Call Actions."

Next Page

3480 MI
t)

EC336395

Cupvrlght IBM CtHP 1984 19t15

Support Procedures
From

Page

Rechecking Actions

End of Call Actions

•

Failure Has Not Been Repaired

Use the information from the FSI to
recheck the actions that were taken by the
product CEo
(See "Rechecking Actions" on this page)
•

If the FSI explanation and your analysis
are different, some of the data may have
been interpreted incorrectly earl ier.
Return to the product maintenance package
using the new data.

•

Compare the FSI explanation of the problem being analyzed
with what is known from the data collection and analysis
done in the preceding steps. If the FSI explanation and your
analysis vary widely, some misinterpretation of data may
have occurred using the new data from the FSI. Return to
the product maintenance package using the new data from
the FSI.
Compare the FRU list from the FSI with the FRU list
developed by the product maintenance package. If the FRU
lists do not match or, the product service representative did
not exchange all the FRUs, exchange those FRUs that have
not been exchanged.
If the product maintenance package was not used, exchange
the FRUs identified by the FSI.

General Problem Definition Diagnostics
If the problem information is consistent
and the FRUs have been exchanged, check the
cables and boards identified by the FSI.

The following are some general diagnostics that can be used to
test the functional areas of the subsystem when there is not
enough data to fully define a problem.
•

Support Procedures

SPROC 4

Support Procedures

SPROC 4

If the failure has not been repaired, or is intermittent without a
repair by either the product maintenance package or the support
maintenance package, call your next level of support, then use
the "No Trouble Found Procedures" EAO. Have a record of
actions taken, FRUs exchanged, error codes observed, and any
data collected during the analysis of the failure available when
you call. If you leave the call, leave the record for follow-on
effort.

Failure Has Been Repaired
If the failure has been found, verify the repair by retesting using
the program or diagnostic test that originally failed. Rerun the
product maintenance package, 'Unit Test' option, to run the
functional verify program.
Record the actions taken during the call, FRUs exchanged, tests
completed, and short ideas on how the fix was found.

Basic control unit tests within the subsystem
See "Basic CU Tests" on OIAG 1

Perform the actions defined in the "Additional Actions/Comments" column in the FSI
for the FSC, before continuing any other
actions in this SPROC section.
Use the information referenced in the FSI (EADs, diagnostics or others) to analyze the probblem.
Sometimes, a diagnostic or an EAD
can lead you to a new error code.
Use the
new error code for the entry to the FSI for
more fault isolation. Return here after
all other defined actions have been done,
whether the problem was fixed or not.

•

See the "Oiagnostic Identification Table" on OIAG 3 for
EE40 and EEAO
•

If you want to select these diagnostics,
see "General Problem Definition Diagnostics", on this page.

Complete the call.
(See "End of Call Actions", on this page.)

3480 MI

Control unit commands: non-motion and motion including
write and read commands from the host system
See IBM 3480 Online Tests (OL Ts), 099-3480, for
OLT 3480A

•

There are additional diagnostics avai lable
to test major functional areas of the 3480
subsystem.
If you did not have enough data
to define the problem, you can run any, or
all of these programs to assist in defining

Basic drive tests within the subsystem

Subsystem pathing assignment tests from the host system
See IBM 3480 Online Tests (OL Ts), 099-3480, for
OLT 3480B

•

Subsystem write and read reliability tests with extended run
times from the host system
See IBM 3480 Online Tests (OL Ts), 099-3480, for
OLT 3480C

•

Tape interchange tests with forced error logging for sense
definition of temporary errors, from the host system
See IBM 3480 Online Tests (OL Ts), 099-3480, for
OLT 34800

EC336395

ID Copyright IBM Corp. 1984. 1985

}

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Supp.rocedures

,... "'}"'.. "g.

o

o

Use the Infannetlan from the FSI to
recheck the actions that were taken by the
praduct CEo
(See "Rechecking Actions" on this page)

If the FSI explanation Ind your lnalysis
Ire different, sa-e of the dltl may have
been Interpreted Incorrectly elrlier.
Return to the product .. intenance pickage
using the new dati.

!
If the proble. Infannetlan Is consistent
Ind the FRUs have been exchanged, check the
cables and boards identified by the FSI.

!
Perfann the actions defined In the "Additional Actions/COmments" column in the FSI
for the FSC, before continuing any ather
Ictlans In this SPROC section. Use the Information referenced In the FSI (EADs, dllgnastlcs or others) to Inllyze the prabbl... Saletimes, a diagnostic or an [AD
can lead you to a new error code. Use the
new error code for the entry to the FSI for
.ore fault Isolation. Return here after
111 ather defined actions have been dane,
Whether the problem ~s fixed or not.

!
There are additional diagnostics avaflable
to test major functfonal areas of the 3488
subsystem. If you did nat have enough data
to define the problem, you can run any, or
all of these programs to assist in defining
If you want to select these diagnostics,
see "General Problem Definition Diagnostics", on this page.

•

Compare the FSI explanation of the problem being analyzed
with what is known from the data collection and analysis
done In the preceding steps. If the FSI explanation and your
analysis vary widely, some misinterpretation of data may
have occurred using the new data from the FSI. Return to the
product maintenance package using the new data from the
FSI.
Compare "e FRU list from the FSI with the FRU list
developed by the product maintenance package. If the FRU
lists do not match or, the product customer engineer did not
exchange a" the FRUs, exchange those FRUs that have not
been exchanged.

• If the product maintenance package was not used, exchange
the FRUs identified by the FSI.

General Problem Definition DlagnosOes
The following are some general diagnostics that can be used to
test the functional areas of the subsystem when there is not
enough data to fu"y define a problem.
•

suP. Procedures

Failure Has Not Been Repaired
If the failure has not been repaired, or is intermittent without a
repair by either the product maintenance package or the support
maintenance package, call your next level of support, then use
the "No Trouble Found Procedures" EAO. Have a record of
actions taken, FRUs exchanged, error codes observed, and any
data collected during the analysis of the failure available when
you call. If you leave the ca", leave the record for follow-on
effort

Failure Has Been Repaired
If the failure has been found, verify the repair by retesting using
the program or diagnostic test that originally failed. Rerun the
product maintenance package, 'Unit Test' option, to run the
functional verify program.
Record the actions taken during the call, FRUs exchanged, tests
completed, and short Ideas on how the fix was found.

See "Basic CU Tests" on OIAG 1

Basic,drive tests within the subsystem
."

•

o

Basic control unit tests within the subsystem

•

o

End of can Actions

Rechecking Adlons
•

!

o

o

See the "Diagnostic Identification Table" on OIAG 3 for
EE40 and EEAO

Control unit commands: non-motion and motion Including
write and read commands from the host system

- see IBM 3480 Online Tests (OLTa), 099-3480, for OLT
~OA

•

Subsystem pathing assignment tests from the host system

•

See IBM 3480 Online Tests (OLTa), 099-3480, for OLT
3480B

Subsystem write and read reliability tests with extended run
times from the host system
-

See IBM 3480 Online Tests (OLTs), 099-3480, for OLT

3480C
•

Tape interchange tests with forced error logging for sense
delini~on of temporary ~rrors, from the host system

See IBM 3480 Online Tests (OLTs), 099-3480, for OLT

34800

!
Complete the call.
(See "End of Call Actions", an this page.)

IBM C,...clentlal

3480 MI EC A57723

o CopyrIght IBM Corp. 1812, 1. .

,
.;

Support Procedures

SPRoe 4

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Supp.rocedure A

o

o

Taking a CHK1 dump

o

o

I

CHK1 dumps are recorded on the functional microcode diskette
when errors are detected that are considered to be microcode
related.. CHK1 dumps are not recorded for errors deemed to be
hardware related because hardware controls may not be
functional. The support diskette dump procedures will always
Interrogate the CHK1 dump area to determine if any valid data
has been stored.

ENTER TODAYS DATE
IN FORM OF DDMHVY
EXAMPLE: S1JAN88

supportOcecture A

SP.C 100

support Procedure A

SPROC 100

I
2742. DO YOU
WANT TO UNLOAD THE
'CHKIDMP' FILE?

•

ENTER A NUMBER
FROM THE FOLLOWING
LIST:

I

(DUMPING)

I

I-SUBSYS DIAGNOSTICS
2-SUBSYS DSPLY/ALTER
3-SUPPORT UTILITIES
4-END -SUPPORT CALL

o

(YES)
ENTER.COf+ENTS:
(48 CHAR. MAX.)

*** MAIN MENU ***

o

I
I

A TAPE DRIVE MUST BE
RESERVED TO THE MD
FOR THIS FUNCTION

CLOSING CHKIDMP FILE

REQUEST THE CUSTOMER
TO VARY A DRIVE
OFFLINE

274S. SUBSYS DUMP ••
COMPLETE

(3)

** SUPPORT UTILITIES

I-CU TRACE/MATCH CTL
2-MICROPROCESSOR CTL
3-SUBSYSTEM DUMP

, OF DUMP FILES = xx

(3)
ENTER DRIVE ADDRESS
THAT WAS VARIED
OFFLINE

SELECT
1- CU DUMP
2- DRIVE DUMP

SELECT:
1- CU DUMP
2- DRIVE DUMP
(ENTER on ly)

.,

(1)

Note

A drive dump should NOT be taken
specific direction by
your next level of support.
~thout

27S2.S9 - ENT~R THE
CU SERIAL NUMBER
EG: SSSSSS

I

OPENING CHKIDMP FILE

** SUPPORT UTILITIES

l-CU TRACE/MATCH CTL
2-MICROPROCESSOR CTL
3·SUBSYSTEM DUMP

I

(ENTER on ly)
I-SUBSYS DIAGNOSTICS
2-SUBSYS DSPLY/ALTER
3-SUPPORT UTILITIES
4-END -SUPPORT CALL

3480 MI EC A57723

o CopyrIfIlt IBM Corp. 1182, 1_

IBM~ntlal

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supp_Procedure B

0

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I

Taking a Concurrent Dump
Concurrent control unit dumps are 'snapshots' of running control
units that are taken without Impact to the customer. These
dumps are usually taken to determine the status of the control
unit with respect to the host or the attached drives. For example,
does a particular Interface have access to a particular drive? Or,
what was the last operation performed with a particular drive?
This function is sometimes used if the problem can be recreated,
but requires that the dump be obtained as soon as possible
tbllowing an error. The depth of the trace tables is limited and
other activity can cause pertinent data to be overwritten.

*** MAIN MENU ***
ENTER A NUttIER
FROM THE FOLLOWING
LIST:

o

o

I

NO VALID DUMP FILE
ON IML DISK

2742. DO YOU
WANT TO UNLOAD THE
'CHKlDMP' FILE?

•
ENTER COt+ENTS:
(48 CHAR. MAX.)

CLOSING CHKIDHP FILE

A TAPE DRIVE MUST BE
RESERVED TO THE HD
FOR THIS FUNCTION

DO YOU WANT TO DUMP
THE CONTROL UNIT
DATA?

** SUPPORT UTILITIES

l-CU TRACE/MATCH CTL
2-MICROPROCESSOR CTL
3-SUBSYSTEM DUMP
ENTER DRIVE ADDRESS
THAT WAS VARIED
OFFLINE

supporAcedureB

SPG>C 110

I
** SUPPORT UTILITIES

l-CU TRACE/MATCH CTL
2-MICROPROCESSOR CTL
3=SUBSYSTEM DIJoP

I-SUBSYS DIAGNOSTICS
2-SUBSYS DSPLY/ALTER
3-SUPPORT UTILITIES
4-END -SUPPORT CALL

.

REQUEST THE CUSTOMER
TO VARY A DRIVE
OFFLINE

o

(ENTER on1y)

(NO)

Note: If a drive problem is suspected, use
a different drive for this function
to avoid polluting the dump data.

(3)

I

I

ENTER TODAYS DATE
IN FORM OF DDtfotVY
EXNotPLE: 81JAM88

I-SUBSYS DIAGNOSTICS
2-SUBSYS DSPLY/ALTER
3-SUPPORT UTILITIES
4=END -SUPPORT CALL
(3)

o

(YES)

I

I

(DIJoPING)

I

I

2749. SUBSYS DUMP ••
COMPLETE
, OF DUMP FILES • xx

SELECT
1- CU DUMP
2= DRIVE DUMP
(1)

Note

A drive dump should NOT be taken
specific direction by
your next level of support.

OPENING CHKIDHP FILE

~thout

2792.S9 - ENTER THE
CU SERIAL NUMBER
EG: SSSSSS

SELECT:
1- CU DUMP
2- DRIVE DUMP

I (ENTER on1y)

I

I

"
3480 MI EC A57723
CI COPJl'l.ht IBM Corp.

'111. ,.

IBM Cott~ntlal

s~pport Procedure B

SPRoe 110

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suppeProcedure C

0

o

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Taking a Non-Concurrent Dump
Non-concurrent control unit dumps are taken to preserve the
contents of control storage following errors that stop the control
unit clocks. The data is 'clocked' out of the control unit using the
Maintenance Device (MD) and as a result, is slighUy slower than
a concurrent dump.

o

o

I

o

o

suPporOocedure C

sPGle 120

support Procedure C

SPRoe 120

I

*** WARNING ***
VERIFY THAT THE CU
IS OFFLINE
(ENTER • START DIAG)

** SUPPORT UTILITIES

l-CU TRACE/MATCH CTl
2-HICROPROCESSOR CTl
3=SUBSYSTEM DUMP

•

(ENTER on ly)

*** MAIN MENU ***
ENTER A NlHIER
FROM THE FOLLOWING
LIST:

2792.99 - ENTER THE
CU SERIAL NUMBER
EG: 888888

I-SUBSYS DIAGNOSTICS
2-SUBSYS DSPLY/ALTER
3-SUPPORT UTILITIES
4-END -SUPPORT CALL

ENTER TODAYS DATE
IN FORM OF DDMHYY
EXAMPLE: 81JAN88

I-SUBSYS DIAGNOSTICS
2-SUBSYS DSPlY/AlTER
3-SUPPORT UTILITIES
4-END -SUPPORT CAll

(3)

** SUPPORT UTILITIES

ENTER COMNTS:
(49 CHAR. MAX.)

I-CU TRACE/MATCH CTl
2-HICROPROCESSOR CTl
3-SUBSYSTEM DUMP
(3)
SELECT
I- CU DIJoIP
2- DRIVE DUMP
(1)

Note

CONCURRENT DUMP
NOT AVAILABLE!

A drive dump should NOT be taken
~thout specific direction by
your next level of support.

I

I

(DUMPING)

I

2749. SUBSYS DUMP ••
COMPLETE
, OF DUMP FILES

= xx

i

DO YOU WISH TO FORCE
A NON-CONCURRENT
DUMP?

T(YES)

3480 MI EC A57723
CI CopyrIght IBM Corp. 1182, 1_

4444

SELECT:
1= CU DUMP
2= DRIVE DUMP

I (ENTER on ly)

IBMC~ntlal

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suppeProcedure D

0

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Setting Error Match Codes and Trace Conditions
*** MAIN MENU ***
ENTER A NUMBER
FROM THE FOllOWING
LIST:

I-SUBSYS DIAGNOSTICS
2-SUBSYS DSPlY/AlTER
3-SUPPORT UTILITIES
4-END -SUPPORT CAll
(3)
** SUPPORT UTILITIES
I·CU TRACE/MATCH CTl
2-HICROPROCESSOR CTl
3-SUBSYSTEM DUMP
(1)

** CU TRACE/MATCH
--READING:
ERROR MATCH CODE

suppoAcedure D

sPOle

130

I
I-ERROR MATCH CNTRl
2-TRACE CONDITIONS
3-UCODE CONTROL
4=HONITOR 6-RESET

•

(1)

**ENTER:
Note: The first error code that you ~sh to
ERROR MATCH VAlUE(S)
match is entered in the first group
xxxx xxxx xxxx
of xxxx's. The second error code in
the second group. and so on.
Note: If an exact match -nth the error code
is required. the ignore value should
be set to eaee.
ENTER:
An example of 'Ignore Hask' usage to
IGNORE MASK VAlUE(S)
establish a range of match values
xxxx xxxx xxxx
would be to set an error match of 1234.
If an ignore mask of eee7 is also set.
the match ~ll occur on all values
from 123e to 1237. Again. the first
group of xxxx's is for the first error
match code. the second for the second
-MATCH CODE (1)
error match code. and so on.
•• WANT TO lIMIT THIS
MATCH COfoPARE TO
A SINGLE DRIVE?

4-RESET MATCH CODE
5-FCODE HANG (7eel)
6=NOTIFY MO (STS 5B)
7=FORCE CHKl DUMP

.

SELECT FOR TRACE:
I-MODULE ACTIVITY
2=DRIVE ACTIVITY
3·CHANNEl ACTIVITY

Note: The follo-nng trace options will be set
according to the trace conditions
requested by the additional actions
section of the FSI or as directed by
your next level of support.

-DO YOU
I - ( l ) - - - - - - - f WANT TO TRACE

1-(2)
-(3)-

lEVEL 7 ACTIVITY?

r(YES/NO)-

(ENTER only)
I-ERROR HATCH CNTRl
2-TRACE OPTI ONS
3-UCODE CONTROL
4=MONITOR 6=RESET

L...----i

-DO YOU
WANT TO TRACE
A SINGLE DRIVE?

r-(NO)-

(ENTER only)

** SUPPORT UTILITIES

l-CU TRACE/MATCH CTl
2=HICROPROCESSOR CTl
3=SUBSYSTEM DUMP
(ENTER only)

SELECT MATCH ACTION
I-WRITE DGHElO lOG
2-WRITE DGOVlY lOG
3-STOP TRACE

I

I=ERROR HATCH CNTRl
2=TRACE OPTIONS
3=UCODE CONTROL
4=HONITOR 6=RESET
(2)

(NO)

** TRACE MATCH MENU
-- ENTER A NUMBER
FROM THE FOllOWING
LIST:

o

o

I-SUBSYS DIAGNOSTICS
2=SUBSYS DSPlY/ALTER
3-SUPPORT UTILITIES
4=END -SUPPORT CAll
Note: Option '4' will allow the error code
match to occur only once and then the
match code -nll be reset. This prevents
nultiple lmatch actions from occurring.
Option '7' will cause the selected error
code to b'e treated as a recoverable CHKl.
This all~ws the control unit
to log th,e data to the functional diskette
for 1ater retri eva1•
The prece·ding M screens will be
presented for each error natch code
entered. This will allow different match
actions f.or each error. if required.

3480 MI EC A57723
CI eop,ri,ht IBM Corp. 1", 1_

IBM Co nfJdenUal

support Procedure D

SPRoe 130

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SUP. Procedure E

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supporOxedure E

spO>e

140

Microcode Error Problem Determination
this procedure is used whenever an error in the MD microcode is suspected. The
procedure causes a unique label to be entered In the MD trace table (PELOG) and the
table Is then written to the MD diskette. After performing the procedure, the next lewl of
support should be contacted to determine the next course of action. The diskette may
need to be forwarded to engineering for further analysis of the trace table.

•

Note: The error code can only be generated when running the MD and may not relate to
any customer problems.

Procedure E
1. Press the RESET button on the MD.
2. When the MAIN MENU appears on the MD keyboard/display, remove the diskette
from the MD.
3. Call your next lewl of support for further Instructions.

3480 MI EC A57723
CI Coprrf,hllBM Corp. 1_. 1181

IBM COI)ftclential
-~

~.

support Procedure E

SPRoe 140

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Notes

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3480 MI EC A57723
c)

Copyright IBM Corp. 1982,1999

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Notes

SPROe 150

150

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Contents

o
Contents

Support Plan . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Support Diskette . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Subsystem Display and Alter Programs .................................. .
Support Utilities Programs ........................................... .
loading The Support Diskette ............ . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Support Diskette Procedures Description ................................... .
Subsystem Display / Alter ....•• ,', ..... ,', .• , ..•. " •..•.. , •... , •....
Display Subsystem Configuration ........ ,',.... . , . . . , , , . . . , ... , ..... , , . . . .
Subsystem Component Descriptions , .. " ' . . . . , .... " . . . . . . . . . . . . . . . . . . . .
Storage Display/Alter Diagram ........................................ .. .
Storage Display/Alter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Unit Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Unit Control Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Display Control Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Alter Control Storage ........................................... ..
Drive Control Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Display Control Storage .......................... . ................ .
Channel RAM Display Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel RAM Display ................................................ ..
Device Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel Adapter Tags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel Adapter Status .................... ......................... .
Channel Adapter Interrupt Register ..................................... .
Buffer Page O. 1. 2. and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Status Store Display Diagram .......................................... ..
Status Store Display ................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Device Assignments .....•..........................................
Device Status ........................................ ............ .
Device Assignment Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Program Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interface Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buffer a ........................................................ .
Buffer 1 ., ....... , ....... " ... ,., .. , ............... , ....... , .... .
HexAIl , .... , ..... , ... , ............ , ... , ................... , .... .
Register Display/Alter Diagram ............ , .... " ....................... .
Register Display/Alter ... " ... , ........ " ...................... " ..... .
Error Registers ..... , ............. ,...., .............. , ......... , ..
Reference Screen ., ... , ...... , ............. ,..................... ..
Reset Control Unit ,., . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Display Drive lSRs and XRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Unit Scan Rings Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Unit Scan Rings ............. , .................. , ......... , .... .
Registers .........•... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt ..... , ... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Busses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hex Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MD Reference Key ................•...•............................

3480 MI

o

EC336395

II Copyright IBM c ...p. 19B4, 1985

100

100
100
100
100
100
105

105
105
110
111
111
111
111
111
111
111
115
116
116
116
116
116
116
116
116
120
121
121
121
121
121
121
121
121
121
121
125
126
126
126
126
126
130
131
131
131
131
131
131

Support Utilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trace/Match Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microprocessor Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Subsystem Dump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trace/Match Control Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trace/~tch Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Match Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Match Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ignore Mask Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Select Match Action . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trace Options ..................., . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ucode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... .
Select Control Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microprocessor Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Display Maintenance Adapter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microprocessor Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Storage Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maintenance Adapter Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sub.;ystem Dump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SDISK 1

140

140
140
140
140
145
146
146
146
146
146
146
146
146
146
146
150
155
155
155
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131

Contents

SDISK 1

Support Plan
The support plan provides SRs with a support diskette and
documentation that can be used to isolate difficult or
intermittent subsystem problems.
The support diskette gives SRs the ability to select and run
specific diagnostics or utilities. The support documentation
provides maintenance information beyond the scope of MAPs
and procedures used by product SRs.

Support Utilities Programs

SDISK 100

Support Plan

SDISK 100

Press ENTER: The following screen displays:

The support utilities programs permit you to:

***

***

MAIN MENU
ENTER A NUMBER
FROM THE FOLLOWING
LIST:

Perform a microcode trace
•

Support Plan

Operate the microprocessor in the control unit
Dump data from the control unit and the drives.

Note: The MD displays in the following diagrams may not be
the same as the actual MD displays.

Support Diskette
The support diskette supplies the following facilities:
•

Subsystem diagnostics

•

Subsystem display and alter programs

•

Support utility programs.

The subsystem diagnostics are explained in the DIAG section of
the maintenance information. This SDISK section explains the
subsystem display and alter programs and the support utility
programs.
You can perform two classes of maintenance with the support
diskette:
•

Concurrent maintenance. This class of maintenance lets a
customer run jobs on all of the subsystem except on the
drive you are troubleshooting. Subsystem performance may
be slightly degraded.

Loading The Support Diskette
To load the support programs, insert the support diskette into
the maintenance device and press the IPL key. The MD then
performs an initial program load (lpL) to load the support
programs. When the initial program load (lpL) is complete, the
following screen displays:

3480 SUPPORT DSKT
DISKETTE PN= 4770121
DISKETTE EC= xxxxxxx
CUO= xxxxx CU1=xxxxx

This screen provides the part number and EC level of the
diskette and the serial numbers of the subsystem control units.
Press ENTER: The following screen displays:
*WARN I NG:~
YOU MAY DESTROY NEW
DISKETTES I F THEY ARE
INSERTED

Non-concurrent maintenance. The subsystem is not
available for customer use.

Subsystem Display and Alter Programs
The subsystem display and alter programs perform as a service
panel. They permit you to:
•

1=SUBSYS DIAGNOSTICS
2=SUBSYS DSPLY!ALTER
3=SUPPORT UTILITIES
4=END -SUPPORT CALL

You can select the major support programs from this screen.
Some support diagnostic routines are non-concurrent. If
possible, all other troubleshooting procedures should be
performed before taking the subsystem away from the
customer.
The diagnostics are defined in the Diagnostic Procedures (DIAG)
section of the MI. Support utilities and subsystem display/alter
selections are explained in this section. Registers displayed by
the support programs and diagnostic routines, which are useful
for isolating hardware failures, are explained in the Data Fields
(OF) section of the MI.

Support Diskette Procedures Description
This warning indicates that when a diskette is IPL'ed and being
used, you cannot remove this diskette and insert another
diskette and continue without IPLing the MD.

An overview flow chart is provided for the Main Menu
selection.
The flow for each procedure begins at the selection screen
that displays after the Main Menu selection has been
entered.

Press ENTER:

ALWAYS IPL THE MD
WHEN CHANGING 3480
MD DISKETTES

Blocks represent MD display output.

Display and alter various registers in the subsystem.
The PF key causes the current program to stop running and
returns to the 'MAIN MENU'.

•

Press ENTER: The following selection screen displays:

Display the subsystem configuration.
Display and alter various storages in the subsystem.

•

This is the Main Menu title screen. If you know the menu
selection, you can enter it via this screen. If you do not know
the selection,

Null (pressing the enter key only) causes the current
operation to stop and returns to the preceding menu, or to
what is defined on the MD screen.

3480 MI

EC336395

,., Copvnght IBM Corp 1984, 1985

All charts start at 'MAIN MENU' .
MD display information screens are included only if they
contain information needed to use the procedure.

This screen is a reminder to IPL the last diskette inserted into
the MD.

•

Pressing the PF key causes the current operation to stop
and returns to the 'MAIN MENU'.

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Subsystem Display/Alter

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Subsystem Display/ Alter

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SDISK 105

Display Subsystem Configuration
The following procedure is used to display the subsystem
configuration:

Theory Only -- The MD displays
in this diagram may not be the
same as actual MD displays.

1. Insert and IPL the support diskette.
2. Press ENTER until the main menu selection screen displays.

D

3. Enter a 2 (SUBSYS DSPLY/ALTER).

*** MAIN MENU ***
ENTER A NUMBER
FROM THE FOLLOWING
LI ST:

4. Enter a 1 (SUBS CONFIG. DSPLY) from the Display/Alter
menu screen.

3480 MODEL xxx
SN xxxxx
CUID x
DRIVE MODEL xxx
xCUS xCHAN x
NO

Subsystem Component Descriptions
Control Unit and drive description display

EJ

D:

UCODE PN xxxxxxx
UCDDE EC xxxxxxx-x
COMPOSITE LVL xX.xx

I-SUBSYS DIAGNOSTICS
2-SUBSYS DSPLY/ALTER
3-SUPPORT UTILITIES
4-END -SUPPORT CALL

3480 MODEL - Control Unit model number - Defined by
switches on the device adapter card (01A-Al02).
SN - Control Unit unit serial number.

II

CUID - Setting of the CUO/CU1 switch on the control unit
operator panel.
DRIVE MODEL - Drive model number - Defined by switches
on the device adapter card (0IA-Al02).

DISPLAY OPTIONS
I - PASSIJORDS
2 - PATH GROUPS
J - DRIVE ADDRESSES

3

CUS - Defines the number of control units in the subsystem.
CHAN - Defines the number of channel adapters and their
locations (A, B , C, D ).
Microcode description display

F.J:

2

Go to DIAG I to
run diagnostics

UCODE PN - Identifies the part number of the functional
microcode currently loaded in the control unit

Go to SDISK I

DISPLAY OF
IML DISK
DATA

Selection

**SUBSYS DSPLY/ALTER
I-SUBS CONFIG. DSPLY
2-STORAGE DSPLY/ALT
J=REGISTER DSP/ALT

UCODE EC - Identifies the EC level of the functional
microcode currently loaded in the control unit.
COMPOSITE LVL - Defines the linked composite or the
functional microcode currently loaded in the control unit.
Display options display

II:

PASSWORDS - Unique passwords assigned by the host
system for specified drives.

2

PATH GROUPS - Unique path IDs assigned by the host
system for specified channel adapters.

2

3

3
Go to SDISK

ENTER CU AND CHANNEL
ADAPTER ID.

(REF)
OA THRU OD
ADAPTER
lA THRU 10
ADAPTER

3480 MI EC A57724
'lIZ. lno

C) Copyri.III/8M Corp.

DRIVE ADDRESS NEEDED:
ENTER VALUE BETWEEN
o AND F.

DISPLAY DRIVE
LOGICAL AND
PHYSICAL
ADDRESSES

- CUO
A THRU 0
- CUI
A THRU D

Subsystem Dfsplay/ Alter

SDISK 105

Subsystem Display / Alter

Subsystem Display! Alter

SDISK 110

Subsystem Display! Alter

SDISK 110

Storage Display! Alter Diagram

Theory Only -- The MD displays
in this diagram may not be the
same as actual MD displays.

II
*** MAIN MENU ***
ENTER A NUMBER
FROM THE FOLLOWING
LIST:

**SUBSYS DSPLY/ALTER
l=SUBS CONFIG. DSPLY
2=STORAGE DSPLY/ALT
3=REGISTER DSP/ALT

SELECT OPTIONS:
l=DISPLAY
2=ALTER
3=CANCEL

(2)

(2 )

I

ENTER START ADDRESS
AS XXXXX

(1)

D
l=SUBSYS DIAGNOSTICS
2=SUBSYS DSPLY/ALTER
3=SUPPORT UTILITIES
4=END -SUPPORT CALL

(2)

SELECT:
l=CU TBLS 2=CU STG
3=CHNL RAM 4=STS STG
(5) 5=DR STG

(2)

--

(3)
(4) -

II

11

ENTER START ADDRESS
AS XXXXX

ALTER CONTROL STORE
STARTING ADR = XXXXX
xxxx xxxx xxxx xxx x

(1)

m
ENTER DRIVE ADDRESS
AS X

m

II

II

ENTER NAME OF TABLE
OR LOG YOU WISH TO
DISPLAY OR TO CANCEL.
ENTER (ONLY)

xxxxx
xxxxx
xxxxx
xxxxx

yyyy
yyyy
yyyy
yyyy

yyyy
yyyy
yyyy
yyyy

yyyy
yyyy
yyyy
yyyy

II

ENTER START ADDRESS
AS XXXX

xxxx
xxxx
xxxx
xxxx

yyyy
yyyy
yyyy
yyyy

yyyy
yyyy
yyyy
yyyy

yyyy
yyyy
yyyy
yyyy

Channel RAM Display
See page SDISK 1

m
xxxx
xxxx
xxx x
xxxx

yyyy
yyyy
yyyy
yyyy

3480 MI

yyyy
yyyy
yyyy
yyyy

yyyy
yyyy
yyyy
yyyy

Status Store Display
See page SDISK 1

EC336395

II Copyright IBM Carp. 1984. 1985

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Subsystem Display/Alter (Continued)

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Subsystem Display/Alter (Continued)

Storage Display/Alter

Control Unit Control Storage

The following procedure Is used to display or alter subsystem
storage, tables, and logs with the maintenance device:

4.

1.

Insert and IPL the support diskette.

The subsystem display/alter function allows you to display and
alter control storage for trouble analysis. This function is
particularly helpful when trying to isolate Intermittent problems
or problems that are difficult to define.

2.

Press ENTER until the main menu selection screen displays.

Display Control Storage

3.

Enter a 2 (SUBSYS DSPL Y/AL TER).

4.

Enter a 2 (STORAGE DSPLY/ALT) from the Display/Alter
menu screen.

1.

Enter a 2 (CU STG) when the selection screen

5.

SELECT one of the following:

2.

Enter a 1 (DISPLAY) when the select option screen
displays.

3.

Enter the address of the first storage location (START
Control storage
ADDRESS) that you want to display
in the following format:
displays

G

c·,;

SOISK 111

iii

When the ALTER CONTROL STORE screen
displays, use
the MD space key to move the cursor under the byte to be
altered. Input new data.
Note: Do not press the ENTER key until all data for the
screen has been entered.

To exit from alter mode, press the maintenance device RET
(Return) key. The SELECT OPTION screen displays.

To display control storage:

D displays.

II

Drive Control Storage
The subsystem display/alter function allows you to display drive
control storage for trouble analysis.

Display Control Storage

1 = CU TBLS - Control unit tables
2 = CU STG - Control unit storage
(Control Storage)
3 = CHNL RAM - Channel buffer
4 = STS STG - Status storage
5 = DR STG - Drive storage

II

Note: Display functions can be performed concurrently with
customer operations. Alter functions are non-concurrent and are
allowed only if the control unit microprocessor Is stopped. You
must vary all channel paths offline in the controlling computer
operating system and take the control unit offline before
performing any alter function.

11.

a.

The x's represent the address of the data.

b.

The y's represent the data beginning at the xxxx
address.

To exit from display mode, press the maintenance device RET
(Return) key. The SELECT OPTION screen displays.

Alter Control Storage

Control Unit Tables
To display control unit tables:

D displays.

1.

Enter a 1 (CU TBLS) when the selection screen

2.

Enter the acronym for the table you want to display
For
example, enter CST to display the Control Status Table. The
in the following format:
table displays

Warning: Altering control storage overlays subsystem
microcode. The subsystem must be offline before using the
ALTER function and an IML must be performed again before It Is
returned to the customer.

II.

To display control storage:

D displays.

1.

Enter a 5 (DR STG) when the selection screen

2.

Enter a drive address when screen

3.

Enter the address of the first storage location (START
Control storage
ADDRESS) that you want to display
In the following format:
displays

m

D displays.

m.

a.

The x's represent the address of the data.

b.

The y's represent the data beginning at the xxxx
address.

To exit from display mode, press the maintenance device RET
(Return) key. The SELECT OPTION screen displays.
Nole: You cannot alter drive control storage.

II

a.

The x's represent the address of the data.

b.

The y's represent the data beginning at the xxx x
address.

To alter control storage:

Note: Refer to the Data Fields (OF) registers section of the
MI for a description of the table r:lata.

1.

Enter a 2 (CU STG) when the selection screen

Press ENTER to display the next four address locations.

2.

Enter a 2 (ALTER) when the select option screen
displays.

To exit from a table display, press the maintenance device RET
(Return) key. The ENTER NAME OF TABLE
screen displays.

3.

Enter the address of the first storage location (START
ADDRESS) that you want to change

3.

II

3480 MI

EC336396

© CopyrlghllBM Corp. 1984. 1985. 1987
.$%$0

D displays.

II

IJ.

Subsystem Display/Alter (Continued)

SOISK 111

-

Subsystem Displayl Alter (Continued)

Subsystem Display/Alter (Continued)

SDISK 115

Subsystem Display/Alter (Continued)

SDISK 115

Channel RAM Display Diagram

Theory Only - The MD displays
in this diagram may not be the
same as actual MD displays.

*** HAIN MENU ***
ENTER A NUMBER
FROM THE FOLLOWING
lIST:

ENTER CHANNEL:
ADAPTER 10.

l*SUeSYS DIAGNOSTICS
2-SUBSYS DSPlY/AlTER
3-SUPPORT UTILITIES
4-END -SUPPORT CAll

DISPLAY OPTIONS:
3-BUFFER
a-NONE
I-DEVICE 4-All
Z-CHANNEl
(a)

(2)

**SUBSYS DIAGNOSTICS
I-sues CONFIG. DSPlY
2-STORAGE DSPlY/AlT
3-REGISiER DSP/AlT
DO YOU WANT TO
DISPLAY ANOTHER CHAN
ADAPTER?

(2)

u_.t::~

SELECT:
I-CU TBLS 2-CU STG
3-CHNl RAM 4-STS STG
S-OR STG

Return to
SELECT
screen

(3)

..•..•.•.

TT

DEVICE CONDITION
xx xx xx xx xx xx xx
xx xx xx xx xx xx xx
xx xx

_ _t~:~
Return to
ENTER
CHANNEL
screen

(3)

.

CHAN NEl ADAPTER DATA
xxx xxxxxxxxxxx
xx xxxxxxxxxxxx
xx xx

BUFFER PAGE I
xx xx xx xx xx xx xx
xx xx xx xx xx xx xx
xx xx

DEVICE STATUS
xx xx xx xx xx xx xx
xx xx xx xx xx xx xx
xx xx

.........

BUFFER PAGE a
xx xx xx xx xx xx xx
xx xx xx xx xx xx xx
xx xx

BUFFER PAGE Z
xx xx xx xx xx xx xx
xx xx xx xx xx xx xx
xx xx

DEVICE COMM.~ND
xx xx xx xx xx xx xx
xx xx xx xx xx xx xx
xx xx

BUFFER PAGE 3
xx xx xx xx xx xx xx
xx xx xx xx xx xx xx
xx xx

3480 MI EC A57724

"j

\

J

J

\

,J

,J"
;

"

:
,J

\

\.1

\

, \

\.J

~j

.(

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o o o

0··0··0

o o o 0 o o o o

Subsystem Display/Alter (Continued)

o

(J

c

o

o o

c o

(;

o o o

Subsystem Display/Alter (Continued)

0.0

SDISK 116

Channel RAM Display
The following procedure Is used to display channel buffer data:
1. Insert and IPL the support diskette.
2. Press ENTER until the main menu selection screen displays.
3. Enter a 2 (SUBSYS DSPLY/ALTER).
4. Enter a 2 (STORAGE DSPLY/ALT) from the Display/Alter
menu screen.
5. Enter a 3 (CHNL RAM).
6. Enter the channel adapter 10 (A, B, C, or D).
7. Select one of the following DISPLAY OPTIONS:
01 2 3 4 -

NONE
DEVICE
CHANNEL
BUFFER
ALL

Note: One entry is used for each device starting with device O.

3480 MI EC A57124
C Copyri,"IBM Corp. 111%.1110

Subsystem Display/Alter (Continued)

SDISK 116

-

Subsystem Display/Alter (Continued)

Subsystem Display/Alter (Continued)

SDISK 120

Status Store Display Diagram

Theory Only -- The MD displays
in this diagram may not be the
same as actual MD displays.

*** MAIN MENU ***
ENTER A NUMBER
FROM THE FOLLOWING
LIST:

DISPLAY OPTIONS
(ENTER)
O=NONE
3'ERRORS
1=DEVICE
4=BUFFG
2.:-ASSIGN

(~F)(I)
l=SUBSYS DIAGNOSTICS
2=SUBSYS DSPLY/ALTER
3=SUPPORT UTILITIES
4=END -SUPPORT CALL
(2)

**SUBSYS DSPLY/ALTER
l=SUBS CONFIG. DSPLY
2=STORAGE DSPLY/ALT
3=REGISTER DSP/ALT
(2)

SELECT:
l=CU TBLS 2=CU STG (4) 3=CHNL RAM 4=STS STG
5=DR STG

O=QUIT
l=DEVICE DATA
2=INTERFACE DATA
3=CHECKl DATA

I

D

II

DEVICE ASSIGNMENTS
xx xx xx xx xx xx xx
xx xx xx xx xx xx xx
xx xx

INTFC ASSIGNMENTS
CHAN ABC 0 SER
Ca
C1

c·

6=HEX
UfFlALL

t(

) (t)

II

(5)

1

I

ERROR CODES
xxxxxxxxxx

III

D
sa xx
S6 xx
sc xx
92 xx

xx
xx
xx
xx

xx
xx
xx
xx

xx
xx
xx
xx

xx
xx
xx
xx

xx
xx
xx
xx

ca

xx xx xx
C6 xx xx xx
CC xx xx xx
D2 xx xx xx

xx
xx
xx
xx

xx
xx
xx
xx

xx
xx
xx
xx

fJ

ae xx
e6 xx
ec xx
12 xx

xx xx xx xx xx
xx xx xx xx xx
xx xx x
xx x~ xx xx xx

ae Through FF

DEVICE STATUS
xx xx xx xx xx xx xx
xx xx xx xx xx xx xx
xx xx

9S xx xx xx xx xx xx
9E xx xx xx xx xx xx

08 xx xx xx xx xx xx

A4 xx xx xx xx xx xx
AA xx xx xx xx xx xx

DE xx xx xx xx xx xx
E4 xx xx xx xx xx xx
EA xx xx xx xx xx xx

Ba xx xx xx xx xx xx
B6 xx xx xx xx xx xx
BC xx xx xx xx

Fa xx xx xx xx xx xx
F6 xx xx xx xx xx xx
FC xx xx xx xx

J
Fa xx xx xx x
F6 xx xx xx xx xx

x~

EI
DEVICE ASSIGN MASK
xx xx xx xx xx xx xx
xx xx xx xx xx xx xx
xx xx

DEVICE PROGRAM FLAGS
xx xx xx xx xx xx xx
xx xx xx xx xx xx xx
xx xx

4=MESSAGE BUFFER 0
5=MESSAGE BUFFER 1
6=ALL SS IN HEX FORM

3480 MI
.1;.

Subsystem Display/Alter (Continued)

EC336396

Copyrighl18M Corp. 1984. 1985. 1987

l

, .1

SDISK 120

o

o

c

o

()

o

Subsystem Display/Alter (Continued)
Status Store Display
The Status Store selection is used to display the status of the
subsystem.
The following procedure is used to display status storage data:

.,.

Insert and IPL the support diskette .

2.

Press ENTER until the main menu selection screen displays.

3.

Enter a 2 (SUBSYS DSPLY/AL TER).

4.

Enter a 2 (STORAGE DSPLY/ALT) from the Display/Alter
menu screen.

5.
6.

0=
1 =
2 =
3 =
4 =

NONE
DEVICE
ASSIGN
ERRORS
BUFFO

Note:

Status Store is initialized to:

Device
Device
Device
Device

Assignment
Status
Assignment Mask
Program Flags

3480 MI

EC336396

C. COPYright ttlM Corp. 1984. 1985 1987

a

= X'DD'

o

o

Subsystem Display/Aller (Continued)

SDISK 121

Device Assignments

Device Assignment Mask

Interface Assignments

One device assignment entry for each device starting with device

One device assignment mask entry for each device starting with
device 0

An 'X' identifies which channel the control unit is uSing and
whether it is assigned the serial bus

00:
80
40
20
10
08
04
02
01

D:

= Control Unit 0,
= Control Unit 0,
= Control Unit O.
= Control Unit O.
= Control Unit 1.
= Control Unit 1.
= Control Unit 1,
= Control Unit 1,

Adapter
Adapter
Adapter
Adapter
Adapter
Adapter
Adapter
Adapter

A
B
C
D
A
B
C
D

80
40
20
10
08
04
02
01

= Control
Control
= Control
= Control
= Control
= Control
= Control
= Control

=

Unit 0,
Unit 0,
Unit 0,
Unit O.
Unit 1,
Unit 1.
Unit 1.
Unit 1.

Adapter
Adapter
Adapter
Adapter
Adapter
Adapter
Adapter
Adapter

A
B
C
D
A
B
C
D

Device Status

Device Program Flags

One device status entry for each device starting with device 0

One device program flag entry for each device starting with
device 0

Enter a 4 (STS STG).
Select one of the following DISPLAY OPTIONS:

o

D:

Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7

= Deferred unit check
= Not lile protect
= Buffer assigned to control unit 0
= Buffer assigned to control unit 1
= Buffer write
= Buffer full/backward
= Buffer empty
= Device ready

D.

Error Codes
This is the error code of the last recovered Check 1 error

0

Buffer 0
This display contains control unit to control unit messages.
Control unit 1 In write mode and control unit 0 in read mode

D.

Buffer 1

II:

80
40
30
20
10
08
04
02
01

= Local system reset
= Remote system reset
= CMP device deadlock state
= CUO CMP device interlock
= CU1 CMP device interlock
= All channel paths assigned
= Device at BOT
= Initial extended contingent connection
= Give busy for extended contingE!nt connection

This display contains control unit 10 control unit messages.
Control unit 0 in write mode and control unit 1 in read mode

Ill.

Hex All
This selection provides a dump of all Status Store information
(address 00 through FF)

II.

= X'DE'
= X'FF'
= X'DO'

Subsystem Displayl Alter (Continued)

SDISK 121

Subsystem Display/Alter (Continued)

SDISK125

Subsystem Display/Alter (Continued)

Register Display/ Alter Diagram

Theory Only -- The MD displays
in this diagram may not be the
same as actual MD displays.

MA IN MENU
ENTER A NUMBER FROM
THE FOLLOWING
LIST:
,~,~,~

••••

<.

YES

E1
I=SUBSYS DIAG~OSTICS
2=SUBS(S DSPLY/ALTER
3=SUPPORT UTILITIES
4=END -SUPPORT CALL

1

27100. **00 YOU
WANT TO DISPLAY
THE ERROR REG'S?

9718.02 THE HP IS
RUNN I NG! ! CAN I STOP
IT NOW?

(NO)

ENTER XR YOU WISH
TO READ OR WRITE
OR CHAN FOR CHAN REG
OR NULL TO QUIT

(REF)

USE XR NAMES SUCH AS
"PER" OR "BOSE".

00
01
02
03

xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx

.,~

SUBSYS DSPY/ALTER
1=5UBS CONFIG. DSPLY
2=STORAGE DSPLY/ALT
3=REG I STER !lSP/ALT

xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx

I
BDSEO=xx
BDSE1=xx
BDSE2=xx
BDSE3=xx

ENTER I BYTE OF DATA
TO WR I TE THE XR
OR PRESS ENTER ONLY
TO READ

Control unit
local storage regs
04 through OB

oc

D

-

SELECT:
1= CU XI{S 2= CU LSR
3= DR XRS 4= DR LSR
5= CU SCAN RINGS

J( I)

(5)

(2j

DO YOU WANT TO READ
THE REGS AGAIN?

(YES)

(3)

(4 )

g

(2 )
BCSEO=xx
BCSE1=xx
BCSE2=xx
BCSE3=xx

It}

ENTER DRIVE ADDRESS
AS X

(YES)

E1

I

CER=xx WSE=xx RSR=xx
RER=xx DSE=xx PER=xx
ERA=xx ERB=xx MTI=xx

1(3·

(5 )

xxxxxxxx xxxxxxxx
00 xxxxxxxx xxx xxx xx
OE xxxxxxxx xxxxxxxx
OF xxxxxxxx xxxxxxxx

DRIVE LSR PAGE yy
xxxx xxxx xxxx xxxx

==========1==========
Drive local storage
register poges OO-OF
=====:===~==:========

I

m
DRIVE XR CONTENTS:
X01=yy X02=yy X03=yy
X04=yy X05=yy X06=yy
X07=yy X08=yy X09=yy

I(NO)

J(3,4)

RESET CONTROL UNIT?

8 0

Return to
SELECT screen

====;::========

0

XIO=yy
X21=yy
X24=yy
X27=yy

XII =yy
X22=yy
X25=yy
X30=yy

X20=yy
X23=yy
X26=yy
X31=yy

(YES)

I

===============

I
Control unit

Return to
SELECT screen

Return to
SELECT screen

=============

Return to
SELECT screen
=:=============

scan rings
See page SDISK 1

3480 MI

Sub&ystem Display/Alter (Continued)

EC336396

~ Copyrignlll:lM Ca,p. 1984. 1985 1981

t)

iJ

SDISK 125

o

o

o

~ ••
ni~nl~"
""
.... h~"~+Q",
~~J~~"" •••
..........
,..., ...... ,

11l1i'Ar

I

•

••

~......

o

o

I,r
__ o.n.t.i.n.I_IA_ti_,\

o

o

o

o

Subsystem Display / Alter (Continued)

--

Register Display / Alter

Reference Screen

The register display/alter routine lets you display or alter
selected subsystem registers and to display the control unit scan
rings.

The reference screen
is obtained by pressing the MD
keyboard/display REF key. The screen is used for prompting
and to ensure that correctly formatted data is entered.

Note: When the alter external register function is
used, a subsystem reset is needed before the subsystem
can be returned to the customer.

Note: See the OF section of the MI for XR names,
pages, and addresses.

o
SDISK 126

EJ

Reset Control Unit
The following procedure is used to display control unit external
registers:

The control unit can be reset by answering yes to the question
displayed on this screen

II:

1.

Insert and IPL the support diskette.

2.

Press ENTER until the main menu selection screen displays.

YES - Resets the control unit and forces a return to the
SELECT screen.

3.

Enter a 2 (SUBSYS DSPL Y / ALTER).

NO - Forces a return to the SELECT screen.

4.

Enter a 3 (REGISTER DSP / ALT) from the Display/Alter
menu screen.

5.

Select one of the following
1

=

2

=

3
4

=

5

=

=

D:

CU XRS - Control Unit External
Registers
CU LSR - Control Unit Local Storage
Registers
DR XRS - Drive External Registers
DR LSR - Drive Local Storage
Registers
CU SCAN RINGS - Control Unit Scan
Register

Display Drive LSRs and XRs

0

0,

Before you can display drive XRs
or LSRs
the functional
microcode must be running and the drive must be available to
the MD (not assigned to a host processor!.
Notes:
1.

See the OF section for definitions of pertinent drive XR bits.

2.

Unless indicated in a specific diagnostic, the contents of the
external registers may be different from the original
diagnostic display.

The OF (Data Fields and Registers) section of the MI defines the
registers that are useful when troubleshooting subsystem
failures.

Error Registers
Error register definitions

0:

CER = Channel Error Register
RER = Read Error Register
ERA = Error Register A
WSE = Write Status Error
DSE = Device Status Error
ERB = Error Register B
RSR = Read Status Register
PER = Processor Error Register
MTI = Maintenance Tag In
BCSE = Buffer Channel Status Error Register
BOSE = Buffer Device Status Error Register
Register data fields are defined in the Data Fields (OF) register
section of the M I.

3480 MI
t;; Copyr:ght IBM Corp

EC336395
1984 1985

Subsystem Display / Alter (Continued)

SDISK 126

Subsystem Display / Alter (Continued)

Subsystem Display / Alter (Continued)

SDISK 130

Control Unit Scan Rings Diagram

Theory Only -- The MD displays
in this diagram may not be the
same as actual MD displays.

*** MAIN MENU ***
ENTER A NUMBER
FROM THE FOLLOWING
LIST:

l=REGISTERS
2=INTERRUPT 3=BUSES
4=ERROR
S=l TO 4
6=HEX

II

(REF)

(3)

(4)

PCR
PSR
PER
XRA

xx
xx
xx
p aa

ERA xx
ERB xx
XRAEO xxxxxxxx
XRAEI xxxxxxxx

L -(6)-

OPTION 1-4 DISPLAYS
DATA INDICATED.
OPTION S DISPLAYS
DATA FROM 1 TO 4

l=SUBSYS DIAGNOSTICS
2=SUBSYS DSPLY/ALTER
3=SUPPORT UTILITIES
4=END -SUPPORT CALL

IMR xx.
PDR xx.
JA xxxx ..
IT xxxx ..

(1)
(2 )

II
L...-_-/I NL xxxxxxx
SIL xxxxxxx
R-H-RQ xxx
LBM x EX x

CILV
JILV
PILV
NLEV

x.
x.
x
xx

(2)

**

A "." OR "?" AFTER
AN ENTRY MEANS
GOOD OR BAD PARITY
WAS DETECTED

SUBSYS DSPY/ALTER
l=SUBS CONFIG. DSPLY
2=STORAGE DSPLY/ALT
3=REGISTER DSP/ALT

L...-_ _ _--/ INS xxxx ..
REG xxxx ..
JBO xxxx ..
J-B-DL xxx

xx. xx.
xx. xx.
EX-Cs xx
CK1-A xx

I

(3 )

SELECT:
1= CU XRS 2= CU LSR
3= DR XRS 4 DR LSR
S= CU SCAN RINGS

(S)

WORD ENTRYS MAY HAVE
TWO "." OR "?"S,
ONE FOR EACH BYTE.

HEX DATA IS SHOWN ...
WITH BIT 0 LEFT
JUST! F I ED IN THE
FIRST BYTE.

3480 MI

EC336395

CI Copyright IBM Corp. 1984. 1985

r

~--------------i

ERAB xxxx x
HOLD xxxx x.
STA xx

FCKI
CK2
MCK2
XRE

x
x
x
x

I
---~

ERAB xxxx x
UU

L

~

Force CHK 1 Sync Latch
ERB register
ERA register

HOLD xxxx x
UU

L

~

Force CHK 1 Sync Latch (holding)
ERAH register
ERBH register
The Force CHK 1 Sync Latch (H) is
set when Force CHK 1 is set. It
is used to set ERAH and ERBH.

~-------------------ixxxxxxxxxxxxxxxxxxxx

L

xxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxx
xx

Subsystem Display / Alter (Continued)

SDISK 130

c

()

o

o

Subsystem Display / Alter (Continued)
Registers

The Control Unit Scan Ring routine allows you to display
registers. interrupts. buses and error information when a Check
1 error condition exists.

The following registers are displayed
option is salected:

1.

Insert and IPL the support diskette.

2. Press ENTE:R until the main menu selection screen displays.
3.

Enter a 2 (SUBSYS DSPLY/ALTER).

4.

Enter a 3 (REGISTER DSP/ALT) from the Display/Alter
menu screen.

5.
6.

IMR
PDR
JA
IT
PCR
PSR
PER
XRA

ERA
ERB
XRAE

Buses

El when the REGISTERS

INS

Interrupt Mask Register
Processor Diagnostic Register
~ Processor Address high and low
= Interval Timers A and B
; Processor Control Register
; Processor Status Register
; Processor Error Register
; External Register Address
p ; page
aa ; address
= Error Register A (Ck 1)
; Error Register B (Ck 1)
; External Register Address Extended
=

REG
JBO
J-B-DL
Ex-CS =
CK l-A =

1 ; REGISTERS
2 ; INTERRUPT
3; BUSES
4; ERROR

5; 1 T04
6; HEX
Note: Scan ring data will not be valid unless a Check
1 condition exists.

3480 MI

EC336395

t COPYright IBM Corp 1984 '985

Note: The Data Fields (DF) section of the MI defines
the registers that are useful when troubleshooting
subsystem failures.

INL
SIL
R-H-RQ
LBM
EX
CILV
JILV
PILE
NLEV

;
;
;
;
;
;
;
;
;

Interrupt Latches
Sample Interrupt Latches
Return. Hold. and Request Latches
Level Before Master Mask
Extended Operation
Current Interrupt Level
Pending Processor Interrupt Level
Previous Interrupt Level
New Interrupt Level

Instruction register and source high/low. xx xx
equals the location of the register (CS CS).
Fetch Register. xx xx equals the location of the
register (XR XR).
Processor Bus Out
Jump. Blowout. and Disable LSR
Extended Operations and Cycle Steal delayed latches
First bit on indicates that a Check 1 error latch is on.
Second bit on indicates that multiple error latches
are on.

The following error information is displayed
option is selected:
ERAB
HOLD

Interrupt
The following interrupt information is displayed
INTERRUPT option is selected:

EJ when the BUSES

A Hex display of the scan rings is provided
option is selected.

III when the HEX

MD Reference Key
Provides prompting and information
selections.

D about the option screen

Error

Enter a 5 (CU SCAN RINGS).
Select one of the following:

SDISK 131

Hex Display

The following bus information is displayed
option is selected:

=

o

o

Subsystem Displav / Alter (Continued)

Control Unit Scan Rings

The following procedure is used to display control unit scan
rings:

c

o

c

EJ when the

STA

=

FCK 1 ;
CK2 ;
MCK2 =
XRE =

III when the ERROR

Error Registers A and B
Holding registers for ERA and ERB (ERAH and ERBH).
Indicates the condition that caused the first check 1
error.
Scan only register; used to load CRR and ERR
registers.
Force Check 1 on
Check 2 on
Microprocessor Check 2
External Register Error

Subsystem Display / Alter (Continued)

SDISK 131

Notes

3480 MI

EC336395

CI Copyrigllt IBM Corp. 1984. 1985

~}

~)

Notes

SOISK 135

Notes

SOISK 135

o

o

o

o

o

o

o

Support Utilities
Microprocessor Control

Introduction

Note:
The microprocessor control functions may
cause errors at the host system.

The following support utilities are selected from a support
diskette utilities menu:
•

Trace/Match control

•

Microprocessor control

•

Subsystem dump.

Trace/Match Control
The CU Trace/Match Control program gives you the ability to
perform a microcode trace. It lets you stop or record specific
error conditions and microcode data fields. The utility provides
MI-defined data that aids you when isolating machine
malfunctions. Trace/match control will run in concurrent and
non-concurrent maintenance modes; however running this
option in concurrent mode may affect system operation.
Cautions that must be observed when running in concurrent
mode are noted in the Trace/Match Control Procedure Details.

The support diskette contains programs that provide service
representative panel-like functions. The following functions may
be selected to supply microprocessor control from the MD
keyboard! display:

•

Microprocessor reset

•

Microprocessor start

•

Microprocessor stop
Microprocessor instruction step
Address compare/stop
Force branch

•

Microcode control options affect subsystem performance. All
options except 1, 2 and 9 are reset when exiting from the utility.

3480 MI

EC336395

'(, Copvrlght IBM Corp ~984. 1985 1986

Set/reset ignore error

o

o

o

Support Utilities

SDISK 140

Support Utilities

SDISK 140

Subsystem Dump
The Subsystem Dump program dumps control unit or drive data
fields and registers from the subsystem onto the support
diskette dump area. The dumped data will be analyzed by your
next level of support.
Sources of data for the control unit dump are the IML diskette
and control store.
Selecting CU dump will cause the MD to automatically search
for dump files, posting information to the keyboard display.
All dump activity is attempted in the concurrent mode
(functional microcode running). If the functional microcode is
not running, the MD will default to the non-concurrent mode,
posting informational messages on the keyboard display.
The IML diskette dump file contains information relative to
microcode generated or recovered check 1 conditions. Generally
speaking, it is historical data.
Dump files taken from control unit storage are files representing
current conditions (at time of dump).

Set/reset check stop
•

Set/reset check 2 ~ check 1

•

Reset maintenance control register.

Support Utilities (Continued)

Support Utilities (Continued)

SDISK 145

Trace/Match Control Diagram
Nole: See the warnings and notes on the facing page to
review what effects this program has on the tape
subsystem and host system before using trace/match
control.

NOTE I: All selections
except I. 2. and 9 are
reset when exiting this
uti 1i ty
(1)

CODE (1)
.. WANT TO LIMIT THIS (YES)
MATCH COMPARE TO
A SINGLE DRIVE?

** ENTER
THE DRIVE ADDRESS:
(0 - F)

-I~ATCH

** ENTER:
ERROR MATCH VALUE(S)
xxxx xxxx xxxx

~

I

(NO)
(2)
ENTER:
IGNORE MASK VALUE(S)
xxxx xxxx xxxx

Theory Only -- The MD displays
in this diagram may not be the
same as actual MD displays.

*** MAIN MENU ***
ENTER A NUMBER
FROM THE FOLLOWING
LIST:

(3)
SELECT MATCH ACTION:
I=WRITE DGHELO LOG
2=WRITE DGOVLY LOG
3=STOP TRACE

-

4=RESET MATCH CODE
5=FCODE HANG (7001)
6=NOTIFY MD (STS 5B)
7=FORCE CHKl DUMP

CURRENT EMC =
-

xxxxxxxxxxxxxxxxxxxx

xxxxxxxxxxxxxxxxxxxx

xxxxxxxx

I=SUBSYS DIAGNOSTIC~I
2=SUBSYS DSPLY/ALTER
3=SUPPORT UTILITIES 1
4=END -SUPPORT CALL

-

** TRACE/MATCH MENU
-- ENTER A NUMBER

I

(RE F)-

FROM THE FOLLOWING
LIST:

SELECT FOR TRACE:
I=MODULE ACTIVITY
2=DR IVE ACT! VITY
3=CHANNEL ACTIVITY

(3)

** SUPPORT UTILITIES

I=ERROR MATCH CNTRL
2=TRACE OPTIONS
3=UCODE CONTROL
4=MONITOR 6=RESET

I=CU TRACE/MATCH CTL
2=MI CROPROCESSOR CTL
3=SUBSYSTEM DUMP

( 4)

-DO YOU
( 1 ) - WANT TO TRACE

(2)-

1(3)

(I) -

** ENTER
-

(4)

** CU TRACE/MATCH

--READING:
ERROR MATCH CODE

r---

THE DRIVE ADDRESS.
(0 - F)

(2)
(3)
L--

(I )

(YES/NO)-

LEVEL 7 ACTIVITY?

-DO YOU
WANT TO TRACE
A SINGLE DRIVE?

(YES)-

** MONITOR:

I

ERROR MATCH WAIT--->
PF = QUIT

r--

(5)

'---

SEE NOTE 1

SELECT CONTROL OPTN:
I=UCOD CKI HANG-7002
2=CKI RCVRY HNG-7005
3=NO RD. ~.HEAD

4=NO
5=NO
6=NO
7=NO

BUFFERED WRITES
LOAD BALANCING t - - ERROR RECOVERY
RECONNECT

2730. ** ENTER
8=FMT21 ON LOAD BAL.
( B ) - THE DRIVE ADDRESS:
9=FORCE LOGGING
(0 - F)
A=NO EARLY START
B=FORCE PATHING ...

I-

I
C=NO BLOCKID CHK-ING
D=NO BUFF/CHAN TMOUT
* END OF LIST *

3480 MI

Support Utilities (Continued)

EC A47957

'!::: Copyrognt IBM Corp.

1984 1985. 1987

:)

SDISK 145

o

0
Support Utilities (Continued)
Trace/Match Control
The Trace/Match Control Utility Program provides prompting for
setup data that is used to specify actions to be taken when
selected hardware or microprogram errors occur. The match
values can be specified for all drives connected to a control unit
or limited to a single drive.
After the match values and options have been specified, the MD
monitor function can be given control. Its purpose is to wait for a
signal from the subsystem that indicates that an error match has
occurred. The monitor wait function can be terminated by
pressing the PF key on the MD keyboard/display.
A Display Error Match Code command is periodically sent to the
functional microcode's diagnostic monitor to detect stops, hangs,
or Check 1 errors. If one of these conditions occur, an error
message is displayed on the MD keyboard/display.

o

o

o

o

Error Match Control

Trace Options

Error Match Value

Trace options are provided to permit tracing of the microcode
activity if microcode problems are suspected.

II

The error match v<'llue
is compared to the current microcode
error code (current EMe)

Ucode Control

Ignore Mask Value

Select Control Options

The Trace/Match Control Program ORs this ignore mask value
with the error code from the subsystem and the error match
value
As a result. any bit that is on in the ignore mask is
treated as a don't care bit because the OR operation sets the bit
on. If the ignore mask value is hexadecimal FFFF, a match is
found for any error code.

The Select Control Option screens permit selecting the following
options

D

D.

Error Match Value
Ignore Hask Value
ORed Value

Note: When a selection is entered on the trace/match menu,
select for trace, select match action, or select control
option screens, an asterisk (0) replaces the equal (-) sign
on the item line to indicate that the item has been
selected.

In the example, the two ORed values match because the OR
function forces the low order bytes to match. Of course, you can
set the ignore mask to any value necessary to select the group of
error codes you want.

1. Insert and IPL the support diskette.
2. Press ENTER until the main menu selection screen displays.
3. Enter a 3 (SUPPORT UTILITIES).
4. Enter a 1 (CU TRACE/MATCH CTL) from the support utilities
menu screen.

D8ee
eeFF
D8FF

Error Code Value

D8nn
eeFF
D8FF

Select Match Action
The Select Match Action screens
selections:

STOP TRACE: All tracing stops when a matching error code
is found.
RESET MATCH CODE: The matching "Error Match Code"
entry will be reset after a match is found.

6. Select one of the following from the trace/match menu
screen:

FCODE HANG: The microprocessor will hang at 7001 when
an error is matched. See note 1.

...
-

ERROR MATCH CNTRL
TRACE OPTIONS
UCODE CONTROL
MONITOR
RESET.

UCOD CK1 HANG-7002: Will not force a Check 1 error. If a
Check 1 error occurs, it will hang at 7002. See Note 1.

o

CK1 RCVRY HANG-700S: Forces a Check 1 error and will
hang at 700S befor~ error recovery starts. See Note 2.

o

NO RD. AHEAD: No read ahead operations will be done by
the control unit See. Note 3.

o

NO BUFFERED WRITES: All write commands are interpreted
as tape writes. See Note 3.

o

NO LOAD BALANCING: This control unit will not initiate a
Load Balance, but may receive Load Balance jobs from the
other control unit See Note 3.
NO ERROR RECOVERY: Error recovery operations will not
be activated if an error is detected. See Note 4.

o

NO RECONNECT: Use of the reconnect timer (ITO) is
inhibited. See Note 3.

o

FMT21 ON LOAD BAL: When the FMT21 bit is sent, the
buffered log will be off-loaded when a drive is load balanced
to the other control unit

e

SDISK 146

•

FORCE PATHING This funcllon forces the subsystem to use
this control unit's butler for the transfer of data to and from a
selected drive. The MD prompts the user for the drive
address. After the function is active, a flashing message
appears on the MD screen.

•

NO BLOCKID CHK-ING: Unit checks caused by invalid block
IDs detected during read operations are inhibited.
Warning: This option must never be used in concurrent
maintenance mode because data integrity of the subsystem
can be affected.

o

NO BUFF/CHAN TMOUT: Disables the eight second
buffer-channel no activity microcode timer.

Monitor
This function monitors error match conditions that were
previously defined in "Error Match Control."

Reset
This function CLEARS/RESETS all Trace Match functions that
were previously selected.
Notes:
1. When an error occurs, this option will hang the entire
subsystem (non-concurrent maintenance) and can hang the
host system waiting for a response from the subsystem.

o

FORCE LOGGING: Sense data is sent to the host when an
error occurs. (See MSG 1 for turn on/off instructions.)

2. An error will cause the subsystem to hang (non-concurrent
maintenance). However, the host system will receive a
disconnect and will continue its processing without this
subsystem.

o

NO EARLY START: Use of the early start timer (lTD) and
device selection over the serial interconnection is inhibited.
See Note 3.

3. This option can be used in concurrent maintenance mode,
but subsystem performance for drives not under test will be
affected.

WRITE DGOVLY LOG: The sense error history log data will
be stored when an error code is matched.

5. Press ENTER after the CU TRACE/MATCH READINGS screen
displays.

1
2
3
4
6

o

provide the following

WRITE DGHELO LOG: External registers will be stored when
an error code is matched.

Support Utilities (Continued)

Note: Select Control Options affect control unit operations;
therefore, all drives will also be affected.

o

II

0:

D:

An example of the way the ignore mask value works is:

When a match action, control option, or trace option is asked for,
more than one selection can be specified. The selection process
is ended by pressing the ENTER key.

The following procedure is used to run the trace/match control
utility:

o

NOTIFY MD: The microcode alerts the MD via a present
status order when the error code is matched.
FORCE CHK1 DUMP: When the error code is matched, a
CHKl dump will be written in the logging area of the IML
diskette.

4. In concurrent maintenance mode, errors normally recovered
by the subsystem will be logged by the host as permanent
errors. Subsystem performance will not be affected, but host
throughput will, because the host will be performing its own
error recovery actions more frequently for errors that are
normally handled by the subsystem.

Note: The Error Match codes are reset when the control unit is
IML'ed. Switching a control unit online in a dual control
unit subsystem will cause its options to be replaced with
the options of the online control unit

3480 MI EC A57723
"Copyright IBM Corp. 1982. 1989

IBM COflfldential

Support Utillt.ies (Continued)

SDISK 146

o

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o

o

o

o

o

o

o

o

o

o

o

c

()

o

o

Support Utilities (Continued)

Support Utilities (Continued)

Trace/Match Control

Error Match Control

Trace Options

The Trace/Match Control Utility Program provides prompting for
setup data that is used to specify actions to be taken when
selected hardware or microprogram errors occur. The match
values can be specified for all drives connected to a control unit
or limited to a single drive.

Error Match Value

Trace options are pro'/ided to permit tracing of the microcode
activity if microcode problems are suspected.

After the match values and options have been specified, the MD
monitor function can be given control. Its purpose is to wait for a
signal from the subsystem that indicates that an error match has
occurred. The monitor wait function can be terminated by
pressing the PF key on the MD keyboard/display.
A Display Error Match Code command is periodically sent to the
functional microcode's diagnostic monitor to detect stops, hangs,
or Check 1 errors. If one of these conditions occur, an error
message is displayed on the MD keyboard/display.
When a match action, control option, or trace option is asked for,
more than one selection can be specified. The selection process
is ended by pressing the ENTER key.
When a selection is entered on the trace/match
menu, select for trace, select match action, or select
control option screens, an asterisk (oJ replaces the equal
(=) sign on the item line to indicate that the item has
been selected.
Note:

The following procedure is used to run the trace/match control
utility:
1.

Insert and IPL the support diskette.

2.

Press ENTER until the main menu selection screen displays.

3.

Enter a 3 (SUPPORT UTILITIES).

4.

Enter a 1 (CU TRACE/MATCH CTL) from the support utilities
menu screen.

5.

Press ENTER after the CU TRACE/MATCH READINGS screen
displays.

6.

Select one of the following from the trace/match menu
screen:
1
2
3
4
6

= ERROR MATCH CNTRL
= TRACE OPTIONS
= UCODE CONTROL
= MONITOR
= RESET.

0

The error match value
is compared to the current microcode
error code (current EMC).

Ucode Control

Ignore Mask Value

Select Control Options

The Trace/Match Control Program ORs this ignore mask value
with the error code from the subsystem and the error match
As a result, any bit that is on in the ignore mask is
value
treated as a don't care bit because the OR operation sets the bit
on. If the ignore mask value is hexadecimal FFFF, a match is
found for any error code.

The Select Control Option screens permit selecting the following

SDISK 146

•

FORCE PATHING: This function forces the subsystem to use
this control unit's buffer for the transfer of data to and from a
selected drive. The MD prompts the user for the drive
address. After the function is active, a flashing message
appears on the MD screen.

•

NO BLOCKID CHK-ING: Unit checks caused by invalid block
IDs detected during read operations are inhibited.
This option must never be used in concurrent
maintenance mode because data integrity of the subsystem
can be affected.
Warning:

D

options

D.

Select Control Options affect control unit
operations; therefore, all drives will also be affected.

•

UCOD CK1 HANG-7002: Will not force a Check 1 error. If a
Check 1 error occurs, it will hang at 7002. See Note 1.

•

CK1 RCVRY HANG-700S: Forces a Check 1 error and will
hang at 7005 before error recovery starts. See Note 2.

•

•

NO RD. AHEAD: No read ahead operations will be done by
the control unit. See Note 3.

Monitor

•

NO BUFFERED WRITES: All write commands are interpreted
as tape writes. See Note 3.

•

NO LOAD BALANCING: This control unit will not initiate a
Load Balance, but may receive Load Balance jobs from the
other control unit. See Note 3.

An example of the way the ignore mask value works is:

Error Match Value
Ignore Mask Value
ORed Value

0800
DOFF
08FF

Error Code Value

D8nn
DOFF
D8FF

In the example, the two ORed values match because the OR
function forces the low order bytes to match. Of course, you can
set the ignore mask to any value necessary to select the group of
error codes you want.

Select Match Action
The Select Match Action screens
selections:

IJ:

Note:

II provide the following
•

NO ERROR RECOVERY: Error recovery operations will not
be activated if an error is detected. See Note 4.

•

NO RECONNECT: Use of the reconnect timer (ITO) is
inhibited. See Note 3.

•

FMT21 ON LOAD BAL: When the FMT21 bit is sent, the
buffered log will be off-loaded when a drive is load balanced
to the other control unit.

RESET MATCH CODE: The matching "Error Match Code."
See Note 1.

•

NOTIFY MD: The microcode alerts the MD via a present
status order when the error code is matched.

•

WRITE DGHELO LOG: External registers will be stored when
an error code is matched.
WRITE DGOVL Y LOG: The sense error history log data will
be stored when an error code is matched.
STOP TRACE: All tracing stops when a matching error code
is found.

FORCE CHK1 DUMP: When the error code is matched, a
CHK1 dump will be written in the logging area of the IML
diskette.

The Error Match codes are reset when the control
unit is IML 'ed. Switching a control unit online in a dual
control unit subsystem will cause its options to be
replaced with the options of the online control unit.
Note:

3480 MI
ECA57693
C Copy"gnt IBM Corp. 1984. 1985. 1987

o

o

NO BUFF/CHAN TMOUT: Disables the eight second
buffer-channel no activity microcode timer.

This function monitors error match conditions that were
previously defined in "Error Match ControL"

Reset
This function CLEARS/RESETS all Trace Match functions that
were previously selected.
Notes:

1.

When an error occurs, this option will hang the entire
subsystem (non-concurrent maintenance) and can hang the
host system waiting for a response from the subsystem.

2.

An error will cause the subsystem to hang (non-concurrent
maintenance). However, the host system will receive a
disconnect and will continue its processing without this
subsystem.

FORCE LOGGING: Sense data is sent to the host when an
error occurs. (See MSG 1 for turn on/off instructions.)

3.

NO EARLY START: Use of the early start timer (ITO) and
device selection over the serial interconnection is inhibited.
See Note 3.

This option can be used in concurrent maintenance mode,
but subsystem performance for drives not under test will be
affected.

4.

In concurrent maintenance mode, errors normally recovered
by the subsystem will be logged by the host as permanent
errors. Subsystem performance will not be affected, but host
throughput will, because the host will be performing its own
error recovery actions more frequently for errors that are
normally handled by the subsystem.

Support Utilities (Continued)
1988

-

~

SDISK 146

Support Utilities (Continued)
Microprocessor Control
•

This utility permits controlling:
-

•

Support Utilities (Continued)

SDISK 150

Support Utilities (Continued)

SDISK 150

Theory Only -- The MD displays
in this diagram may not be the
same as actual MD displays.

Maintenance Control Register (MCR)
Microprocessor commands
Control storage commands
Maintenance Adapter commands.

Host or channel errors may occur if the utility is run during
concurrent maintenance mode.

*** MAIN MENU ***
ENTER A NUMBER
FROM THE FOLLOWING
LIST:

MP = RUNNING
MCR=xx MSB=xx MTI=xx
ADR=xxxxx DREG=xxxx
(PF=QUIT)

->

Nole: See the warnings on the following page to review what
effects this program has on the tape subsystem and host system
before using microprocessor control.
The following procedure is used to run the microprocessor
control uti Iity:
1.

Insert and IPl the support diskette.

2.

Press ENTER until the main menu selection screen displays.

3.

Enter a 3 (SUPPORT UTILITIES).

4.

Enter a 2 (MICROPROCESSOR CTl) from the support utilities
menu screen.

5.

Select one of the following:
1 = MA REGS - Maintenance Adapter Registers
2 = MP CMOS - Microprocessor Commands
3 = MA CMOS - Maintenance Adapter Commands.

l=SUBSYS DIAGNOSTICS
2=SUBSYS DSPLY/ALTER
3=SUPPORT UTILITIES
4=END -SUPPORT CALL

(1)SELECT:
l=MA REGS 2=MP CMDS (2)
3=MA CMDS

(3)

(3)

** SUPPORT UTILITIES
l=CU TRACE/MATCH CTL
2=MICROPROCESSOR CTL
3=SUBSYSTEM DUMP

l=IGN ERR 2=CHK STOP
3=CK2=CKl 4=RST MCR
5=AD STOP 6=ADR SYNC
7=RESET MA

(2)

(5)

© COPY"~hl

EC336396

(6)

I
2A30**ENTER
THE CS ADDRESS
(xxxxx)

3480 MI

1=RESET 2=START
3=STOP
4=STEP
5=FRC BR 6=FRC INST
CS ADDRESS = (XKXXX)

2A30**ENTER
THE CS ADDRESS
(xxxxx)

IBM Corp. 1984. 1985 1987

i)

~)

o

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o

o

o

o

Support Utiiities (Continued)
The following procedures describe the flow and MD display
screen content for each selectable path of the microprocessor
control utility. Each path starts at the utility's selection screen.

Enter a 1: The following screen displays current MA register
status:

•

•

MTI (Maintenance Tag In)
Bit 0:

MP = RUNNING
MCR=xx MSB=xx MTI=xx
ADR=xxxx
DREG~xxx
(PF=QU IT)
--->

Bit 1:

2=MP CMDS
•

Bit
Bit
Bit
Bit
Bit
Bit

---> MP

RUNNING = Microprocessor is executing instructions
STOPPED = Microprocessor is stopped

Selections:

Note: This display flashes and register content is
updated if the microprocessor is running and no
error bits are on in the maintenance status byte
(MSB) register (bits 4, 5, or 7).

1 = Product Maintenance Adapter Registers
2 = Microprocessor Commands
3 = Maintenance Adapter Commands

•

MCR (Maintenance Control Register)
Bit
Bit
Bit
Bit
Bit

0:
1:
2:
3:
4:

2:
3:
4:
5:
6:
7:

MA Request/MA response - Indicates that another
byte of information is available to the MP. or that
the MA is ready to receive another byte. Also
used to acknowledge "MP Status Out" or "Data"
received from the MP.
Data transfer - Active during data transfer to and
from the MP.
MD enabled - MD is on-line and enabled.
FRU 1 - Microprocessor card
FRU 2 - External register user card
FRU 3 - Maintenance adapter card
FRU 4 - Maintenance device
Check 1 error recovery - Code currently executing
is the result of a Check 1 error.

•

ADR: Control program instruction address

•

DREG: Control program data register

o

o

Support. Utilities (Continued)

Display Maintenance Adapter Registers

SELECT:
l=MA REGS
3=MA CMDS

o

SDISK 155

Microprocessor Commands

SELECT:
l=MA REGS
3=MA CMDS

2=MP CMDS

Enter a 2: The following screen displays microprocessor
command controls:
Warning: The following selections should be used in
non-concurrent maintenance mode only.

l=RESET
2=START
3=STOP
4=STEP
5=FRC BR 6=FRC INST
CS ADDRESS = (xxxx)

Ignore errors
Address compare stop
Check Stop
Check 2 = Check 1
Address compare sync

RESET: Resets the MP and forces a level 0 interrupt.
•

MSB (Maintenance Status Byte)
Bit 0:
Bit 1:
Bit 2:
Bit 3:

Bit 4:
Bit 5:
Bit 6:

Bit 7:

3480 MI
C)

EC336395

Copyright IBM Corp. 1984. 1985

Spare
Status modifier - Always inactive
Extended Op in progress - MP executing in
extended Op.
Address compare equal - Match between the
address entered from the MD and the control
storage address.
Check 1/Processor error - Hard error that affects
the integrity of the control unit.
MP stopped - MP has been stopped by a Check 1
condition or by a Stop MP command from the MD.
Instruction executed - MP read an instruction from
control storage during the last microprocessor
cycle.
Error, MTI data stored - Error data is stored in the
MTI register and is available to the MD.

•

START: Starts the MP at the next logical instruction.

•

STOP: Stops the MP. Must be done before force branch,
force instruction, step, control storage, reset, or MA
commands can be used.

•

STEP: Allows MP to run in a single instruction mode.

•

FRC BR (Force Branch): Transfers control to the address
loaded in the MA data register.

•

FRC INST (Force Instruction): Puts the instruction loaded in
the data register on the data bus. MP may be stepped to
execute the instruction.

•

CS ADDRESS: Displays the control storage address that
was current at the time the menu displayed.

Support Utilities (Continued)

SDISK 155

Support Utilities (Continued)

Support Utilities (Continued)

SOISK 160

Support Utilities (Continued)

SOISK 160

RST MCR: Reset Maintenance Control Register

Maintenance Adapter Commands

Resets all MCR bits

SELECT :
l=MA REGS
3=MA CMOS

2=MP CMOS

AD STOP: Address Stop
Causes the microprocessor to stop when the address
compare equal latch comes on
Turns MCR bit 1 on

Enter a 3: The following screen displays MA command
controls:

•

ADR SYNC: Address Synchronize
Turns MSB bit 3 on when the address compare equal
latch comes on when the address selected is executed.
Causes a sync pulse to be generated on the .+ Address
Compare Signal' line (MA003, 01A A 1E2 Z1 2) when
the address selected is executed.
Microprocessor does not stop.

Warning: The following selections should be used in
non-concurrent maintenance mode only (except ADR SYNC and
RESET MA).

•

RESET MA: Reset Maintenance Adapter
Resets the ignore error, check 2 equals check 1, and
check stop bits in the maintenance control register
(MCR)

l=IGN ERR 2=CHK STOP
3=CK2=CKI 4=RST MCR
5=AO STOP 6=AOR SYNC
7=RESET MA

Resets the maintenance tag in (MTI) register
Resets the force-branch function

•

IGN ERR: Ignore error

Resets the maintenance adapter level 0 interrupt
request

Prevents the microprocessor from stopping when a hard
(Check 1) error is detected
Turns MCR bit 0 on
•

CHK STOP: Check stop
Prevents the microprocessor from restarting after a
Check 1 error
Turns MCR bit 2 on

•

CHK2~CHK 1:

Check 2 ~ Check 1

Allows a Check 2 error to be handled as a Check 1 error
Turns MCR bit 3 on

3480 MI

EC336395

't Copyr'gh! IBM Corp. 1984. 1985

i)

{l

{)

f}

~)

~)

o

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Support Utilities

c

o

Support Utilities

SDISK 165

Support Utilities

SDISK 165

Subsystem Dump
Dump files may be created for the control unit, the drive or from
the CHK1 DMP file on the IML diskette. This interactive utility will
assembly the data from the selected area and move it to the MD
support diskette. Dump functions are available in the concurrent
(microcode operational and running) or non-concurrent modes
(microcode stopped or hung). The CHK1DMP file from the IML
diskette is only available in the concurrent mode. The MD will
automatically try the concurrent mode first as this mode is faster
and then default to thE:! non-concurrent mode.
If a file (CHK1DMP) exists on the IML diskette, the MD will
request an offline drive to perform the dump process. This is
required for the microcode to allocate interrupts for maintenance
purposes.
Multiple dump files may be taken and stored on the MD diskette.
An error message will display if the dump area is full. The user
may then choose to overwrite (destroy) existing dump files. The
MD creates a dump header file which defines the actual location
of the dump data on the diskette.
The following procedure is used to run the subsystem dump
utility:
1.

Insert and IPL the support diskette.

2.

Press ENTER until the main menu selection screen displays.

3.

Enter a 3 (SUPPORT UTILITIES).

4.

Enter a 3 (SUBSYSTEM DUMP) from the support utilities
menu.

5.

Theory Only -- The MD displays
in this diagram may not be the
same as actual MD displays.

SELECT DUMP TYPE:
CU DUMP
2= DRIVE DUMP

~1=

(1)

*** MAIN MENU ***
ENTER A NUMBER
FROM THE FOLLOWING
LIST:

l=SUBSYS DIAGNOSTICS
2=SUBSYS DSPLY/ALTER
3=SUPPORT UTILITIES
4=END -SUPPORT CALL
(3)

** SUPPORT UTILITIES
l=CU TRACE/MATCH CTL
2=MICROPROCESSOR CTL
3=SUBSYSTEM DUMP
(3)

(2)

2702.09 -- ENTER THE
CU SERIAL NUMBER
EG: 000000

2702.09 -- ENTER THE
CU SERIAL NUMBER
EG: 000000

ENTER TO DAYS DATE
IN FORM OF DDMMMYY.
EXAMPLE: 01JAN88

2702.09 -- ENTER THE
DR SERIAL NUMBER
EG: 000000

ENTER CURRENT TIME
IN FORM OF HHMM.
EXAMPLE: 2130

Select the type of dump needed.
1 = Control unit storage dump
2 = Drive storage dump

6.

FOllow instructions provided by the MD.

ENTER COMMENTS:
(40 CHAR. MAX.)

2740. SUBSYS DUMP ••
COMPLETE .••
#

3480 MI

EC A47957

'C COPYrIght IBM Corp.
Q.

1984. 1985 1987

OF DUMP FILES = xx

Notes

3480 MI
(

EC336396

Notes

SDISK 170

Notes

SDISK 170

CopynQhllbM Corp 1984, 1985, 1!:t87

,)

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,

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)

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,

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conte.

o

o

Subsystem Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Drive Command Exerciser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MD/MA Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic CU Test . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . .
Support Di agnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
How the Support Diagnostics Are Organized . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnostic Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnostic Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnostic Identification Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E010 - CU Functions Test ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
EE10 - Processor Basic Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EE30 - Data Buffer Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EE.w - Control Unit to Drive Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EE50 - Data Path Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EE60 - Channel Adapter Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EE90 - Status Store Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEAO - Tape Movement Tests . . . . . . . . • . . . . • . . . . . . . . . . . . . . . . . .
Diagnostic Identification Code Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3

How to Us. the Support Diagnostics . . . . . . • . . . . . . . . . . . . . . . . . . . . . . ..
Support Diagnostic Flow . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . .
Control of the Support Diagnostics .. . . . . . . . . . . • . . . . . . . . . . . . . . . . . ..
Running Support Di agnostics . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . .
Single-Control Unit Subsystem . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . .
Dual-Control Unit Subsystem . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . .
Getting the Diagnostics Running . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Controlling the Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Information Supplied by the Support Diagnostics . . . . . . . . . . . . . . . . . . . . . . .
Status Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Error Screens . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Common Stop Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Meaning . . . . . . . . . . . . . • . • . . . . . . . . . . . . . . . . . . . . . . . .
How to Use the Information Supplied by the Support Diagnostics . . . . . . . . . . . . .
Verify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
How to Use the Diagnostic Test Options . . . . . . . . . . . • . . . . . . . . . . . . . . . .
Some Examples of Using the Diagnostic Test Options . . . . . . . . . . . . . . . . . .
How to End Use of the Diagnostics . . . . . . . . . . . • • . . . . . . . . . . . . . . . . . ..

4
5
5
5
5
5
5
5
6
6
6
6
8
6
8
7
7
7

Maintenance Device/Maintenance Adapter Diagnostic . . . . . . . . . . . . . . . . . . .
Selection Screen . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . .
Open Test . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . .
Put Test . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Get Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Status Out Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

20
20
20
20
20
20

Basic Control Unit Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
FRUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Basic CU Test Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Processor Function Test - Routine EE12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Error Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
FRUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Interrupt Level Test - Routine EE13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Error Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
FRUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Processor External Register Test - Routine EE14 . . . . . . . . . . . . . . . . . . . . . . . 65
Error Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
FRUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Cartridge Automation Facility Wrap Test - Routine EE15

. . . . . . . . . . . . . . . . . . 70

Data Buffer Data Path Test - Routine EE32 . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Buffer Data Path Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Buffer Check Character Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Buffer Memory Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FRUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

100
100
100
100
100
100

Data Buffer Controls Test - Routine EE33 . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
'Suppress Out' and 'Data Stop' (Read Forward) Test . . . . . . . . . . . . . . . . . . .. 110

3480 MI EC A57723
I:)

Copyright IBM Corp. 1982,1999

o

o

'Suppress Out' and 'Data Stop' (Read Backward) Test . . . . . . . . . . . . . . . . . .
Read Overrun Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Overrun Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Separation Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 Mb/s Buffer Adapter Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Improved Data Recording Capability Tests
.... . . . . . . . . . . . . . . . . . . . ..
Error Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FRUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

110
110
110
110
110
110
110
110

Control Unit to Drive Bus Out Driver Wrap Telst - Routine EE42 . . . . . . . . . . . . .
Error Displays . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . "
FRUs . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . ..

150
150
150

Control Unit to Drive Bus and Tag Test - Routtine EE43 . . . . . . . . . . . . . . . . . .
Diagnostic Aid . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . ..
Error Displays . . . . . . . . . . . . . . . . . • . • . . . . . . . . . . . . . . . . . . . . . . .
FRUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . .

160
160
160
160

Control Unit to Drive Serial Test - Routine EE;44 . . . . . . . • . . . . . . . . . . . . . . 170
Error Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 170
FRUs . . . . . . . • • . . . . . . . . . . . . • • . ••••. . . . . . . . . . . . . • . . . . . .. 170
Short Loop Write to Read Pattern Test - Routllne EE52 . . . . . . . . . . . . . . . . . . .
Pattern Control . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . ..
Error Displays . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . ..
FRUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test 4 . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . .

o

o

200
200
200
200
202
208
214

Short Loop Write to Read Timing Test - Routl n. EE53 . . . . . . . . . . . . . . . . . . . 218
Error Displays . . . . . . . . . . . . . . . . . • . . . . . . • . . . . . . . . . . . . . . . . . . 218
FRUs . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . 218
Long Loop Write to Read Test - Routine EE54i . . . . . . . . . . . . . . . . . . . . . . . . 220
Error Displays . . . . . . . . . . . . . . . . . • • . • . . . . . . . . . . . . . . . . . . . . . . 220
FRUs . . . . . . . . . . . . . . . . . . . . . . • • • . . . . . . . . . . . . . . . . . . . . . . . . 220
Channel Interface Wrap Test - Routine EE82
Setup Procedure for the Channel Wrap Test
Error Displays . . . . . . . . . . . . . . . . . .
FRUs . . . . . . . . . . . . . . . . . . . . . . . •

300
300
300
300

Channel Adapter Function Test - Routine EEM . . . . . . . . . . . . . . . . . . . . . . .
Error Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FRUs . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . .
Error Analysis . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . .

320
320
320
320

External Register Bus Addressing and Data Jattern Test - Routine EE85 . . . . . .
Test 1 . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . .
Test 2 . . . . . . . . . . . . . . . . . . . . . • • . . . . . . . . . . . . . . . . . . . . . . . . .
Test 3 . . . . . . . . . • . . . . . . . . . . . • • . . • . . . . . . . . . . . . . . . . . . . . . .
Test 3 External Register Test Sequence
.........................
Test 4 . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . .
Test 4 External Register Test Sequence
.........................
Test 5 . . . . . . . . . . . . . . . . . . . . . • • • . . . . . . . . . . . . . . . . . . . . . . . .
Test 5 Address Test Sequence for Addres ses That Are Not Valid . . . . . . . . . .
Error Displays . . . . . . . . . . • . . . . . . • • . . . . . . . . . . . . . . . . . . . . . . . .
FRUs . . . . . . . . . . . . . . . . . . . . . . . • • • • . . . . . . . . . . . . . . . . . . . . . .
External Register Table (XRT) . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . .
Test 1 and 2 Error Displays . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . .
Test 3,4, and 5 Error Displays . . . . . . . • • . • • . . . . . . . . . . . . . . . . . . . . .

400
400
400
400
400
400
400
400
402
410
412

Status Store Write/Read RAM Storage Test. Routine EE92 . . . . . . . . . . . . . . .
Pattern Entry Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Displays . . . . . . . . . . . . . . . . . . • . • • . . . . . . . . . . . . . . . . . . . . .
FRUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

450
450
450
450

o

Contents

.IAG 1

Basic Tape Motion Test· Routine EEA2 . . . . . . . . . . . . . . . . . . . . . . . . . . .
i::~sseie"cti~~ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
...........................................
Error Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FRUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

500
500
500
500
500
500

Write/Read Exerciser - Routine EEA3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
~~r': ~~Iy' ~i~ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "
...........................................

510
510
510
510
510

Wrlt./Read Exerciser. Routine EEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . .
Error Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FRUs . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

550
550
550
550
550

eoo
eoo

Scope Loop Utility - Routine EEFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • .
Test Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800
Scope Loop Sync Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
~rlve Patch Load UtIlity. Routine EEF1

est Selection

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 820
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820

Drive Command Exerciser
...................................
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Run Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
~rror Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
r~or Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Drive Command Exerciser Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
~rlv. c;;'mmand Exerciser Details

.............................. .
romp ng Screens . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . •
Load Display (LDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write to Tape (WRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Locate Block (LOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modeset (MDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

720
720
720
720
720
721
722
725
725
725
725
725

400

.wo
.wo

Status Store Order Test - Routine EE93 . . . • . . . • • . . . . . . . . . . . . . . . . . . . 460
Error Displays . . . . . . . . . . . . . . . . • . • • . • • . . . . . . . . . . . . . . . . . . . . 460
FRUs . . . . . . . • . . . . . . . . . . . . . • . . • . • • . . . . . . . . . . . . . . . . . . . . . 460

IBM ConftdenUal-11 May 89

Contents

DIAG 1

fl

•
,

f)

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()

t)

()

()

'()

()

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c

c

c

o

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Contents
Subsystem Diagnostics
Drive Command Exerciser
MD/MA Diagnostic
Basic CU Test
Support Diagnostics
How the Support Diagnostics Are Organized
Diagnostic Sections
Diagnostic Routines
Diagnostic Identification Code
E010 - CU Functions Test
EE10 - Processor Basic Tes:s
EE30 - Data Buffer Tests
EE40 - Control Unit to Drive Test
EESO - Data Path Tests
EE60 - Channel Adapter Test
EE90 - Status Store Tests
EEAO - Tape Movement Tests
Diagnostic Identification Code Table
How to Use the Support Diagnostics
Support Diagnostic Flow .
Control of the Support Diagnostics
Running Support Diagnostics .
Single-Control Unit Subsystem
Dual-Control Unit Subsystem
Getting the Diagnostics Running
Controlling the Diagnostics
Information Supplied by the Support Diagnostics
Status Screen
Error Screens
Common Stop Addresses
Aadress Meaning
How to Use the Information Supplied by the Support Diagnostics
Verify
........ .
How to Use the Diagnostic Test Options
Some Examples of Using the Diagnostic Test Options
How to End Use of the Diagnostics . . . . . . .
Maintenance Device/Maintenance Adapter Diagnostic
Selection Screen
Open Test
Put Test
Get Test .
Status Out Test
Basic Control Unit Test
FRUs
Basic CU Test Messages

Contents
2

2
2
2
2
2
2
2
2
2
2
2
2

2
2
2
2
3
4

Data Buffer Data Path Test - Routine EE32
Data Buffer Data Path Test
Data Buffer Check Character Test
Data Buffer Memory Test
Error Displays
FRUs

100
100
100
100
100
100

Data Buffer Controls Test - Routine EE33
'Suppress Out' and 'Data Stop' (Read Forward) Test
'Suppress Out' and 'Data Stop' (Read Backward) Test
Read Overrun Test
Write Overrun Test
Separation Test
4.S Mbis Buffer Adapter Test
Error Displays
FRUs

110
110
110
110
110
110
110
110
110

Control Unit to Drive Bus Out Driver Wrap Test - Routine EE42
Error Displays
FRUs

150

150
150

DIAG 1

Test 3
Test 3 External Register Test Sequence
Test 4
Test 4 External Register Test Sequence
Test S
Test S Address Test Sequence for Addresses That Are Not Valid
Error Displays
FRUs
External Register Table (XRT)
Test 1 and 2 Error Displays
Test 3,4, and 5 Error Displays

400
400
400
400
400
400
400
400
402
410
412

Status Store Write/Read RAM Storage Test - Routine EE92
Pattern Entry Display
Error Displays
FRUs

4S0
450
4S0
4S0

Status Store Order Test - Routine EE93
Error Displays
FRUs

46C
460
460

Basic Tape Motion Test - Routine EEA2
Tests
Test Selection
Error Displays
FRUs . . . . .
Error Analysis

SOC
SOC
SOC
SOO
SOO

WritefRead Exerciser - Routine EEA3
Test Selection
Error Displays
FRUs .
Error Ana!ysis

S10
510
510
510

S

5
S
S

5
5
5
6
6
6
6
6
6
6
7
7

7

20
20
20
20

20
20
30
30

30

Processor Function Test - Routine EE12
Error Dispiays
FRUs .

50
50

Interrupt Level Test- Routine EE13
Error Displays
FRUs

55
55
55

Processor External Register Test - Routine EE14
Error Display
FRUs

65
65

3480 MI EC A57721

c

(J

50

65

Control Unit to Drive Bus and Tag Test - Routine EE43
Diagnostic Aid
Error Displays
FRUs .

160

Control Unit to Drive Serial Test - Routine EE44
Error Displays
FRUs

170
170
170

160
160

160

Short Loop Write to Read Pattern Test - Routine EE52
Pattern Control
Error Displays
FRUs
Test 2
Test 3
Test 4

200
200
200
200

Short Loop Write to Read Timing Test - Routine EE53
Error Displays
FRUs

218
218
218

Long Loop Write to Read Test - Routine EES4
Error Displays
. .... ,
FRUs ..
Channel Interface Wrap Test - Routine EE62
Setup Procedure for the Channel Wrap Test
Error Displays
FRUs
.................. .
Channel Adapter Function Test - Routine EE64
Error Displays
FRUs .'
Error Analysis
External Register Bus Addressing and Data Pallern Test - Routine EE85
Test 1
Test 2

202
208
214

220

220
220

300
300
300

300
320

320

sao
5~0

WritelRead Exerciser - Routine EEA4
Test Selection
Error Dispiays
FRUs
Error Analysis

S50
550
550

Scope Loop Utility - Routine EEFO
Test Selection
Scope Loop Sync Address ...

600
600

Drive Patch Load Utility - Routine EEF1
Test Selection

620

550
S50

600

620

Drive Command Exerciser
Commands
Run Mode Options
Error Display
Error Messages
Drive Command Exerciser Diagram

720
721

Drive Command Exerciser Details
Prompting Screens
Load Display (LDD)
Write to Tape (WRT)
Locate Block (LOC)
Modeset (MDS)

722
725
725
725
725
725

720
720
720
720

320

320
400

400
400

Contents

DIAG 1

Subsystem Diagnostics
The subsystem diagnostics exercise the subsystem. Four sets of
diagnostic exercisers are available:
Drive command exerciser
MDiMA diagnostic
Basic CU Test

Subsystem Diagnostics
Basic CU Test
The basic control unit test verifies:
•

The correct function of the maintenance adapter connections
to the processor and control store

•

The control unit's ability to execute the microcode and forces
the executing of the ROS control store checkout.

Support diagnostics.
You can be directed to run particular subsystem diagnostics by
some other part of this Maintenance Information, for example,
from the EAD section or the FSI section. Or you can select
diagnostics from what is known about the problem.

You can use this diagnostic to verify correct subsystem operation
after the maintenance adapter, processor, or control store cards
have been replaced. See" Basic Control Unit Test" on DIAG 1
for detailed information.

Drive Command Exerciser

Support Diagnostics

The drive command exerciser is a group of programs on the
support diskette that permits you to enter and perform chains of
tape drive commands. The drive command exerciser operates in
concurrent mai ntenance mode.

The support diagnostics are microprograms that can operate the
different parts of the subsystem independently of the subsystem
command operation. That is, the diagnostics:

Diagnostic routines and diagnostic sections are identified by an
identification code of EE plus a hexadecimal number. An E010 is
also assigned that runs a basic set of diagnostics that can be run
without disturbing a dual control unit subsystem.

Diagnostic Sections
Diagnostic sections consist of a group of diagnostic routines that
run in sequence. The sequences test particular areas of the
subsystem, such as the control unit data flow, the control unit to
magnetic tape drive interconnections. or the control unit buffer.
The diagnostic sections are useful when a general area is
suspected. but the specific function that may be failing within that
area is not known.

DIAG 2

E010 runs control unit and tape unit data path diagnostic routines
in the following order: EE12, EE13, EE14, EE32, EE33, EE52,
EE53, EE64, EE85, EE92, and EE93,
When E010 runs, the diagnostic routines included in E010 use
their built in defaults. Parameter entries such as channel and
drive addresses and pattern numbers are neither required nor
allowed.
To rerun E010, use option 1 (RESTART DIAG,) on the DIAG.11
screen.
Note:

You must take both control units offline (thus making the
complete subsystem unavailable to the customer) to run
any support diagnostiC routines that are not included in
E010, except for channel wrap diagnostic routine EE62
(see instructions for setup).

Diagnostic Routines

•
The chains of commands can be used to isolate drive motion
problems or failures caused by a particular sequence of
commands. You can use either of two sequences of commands
that have already been selected, or you can make your own
sequence. The commanas are entered from the maintenance
device keyboard/display.
See "Drive Command Exerciser' on DIAG 1 to find detailed
information about how to use the drive command exerciser.

MD/MA Diagnostic
The maintenance device/maintenance adapter diagnostic tests
the part of the maintenance adapter card that connects to the MD
and tests the communication path between the MD and the
maintenance adapter card. You can use this diagnostic when:
•

The MD does not seem to communicate with the control unit.

•

The maintenance adapter card has been replaced.

See" Maintenance Device/Maintenance Adapter Diagnostic" on
DIAG 1 for detailed information about the MD/MA diagnostic.

Consist of microcode
Replace the functional microcode

•

Diagnostic routines are the actual sets of microcode instructions
that perform tests on the parts of the subsystem. Some, but not
all. diagnostic routines can be called by diagnostic sections.

Diagnostic Identification Code

Test the parts of the subsystem.

Because they replace the functional microcode, the support
diagnostics cannot be used for concurrent maintenance in a
single-controi-unit subsystem. In a dual control unit subsystem,
those support diagnostics that test only the internal control unit
can be run on one control unit whi Ie the other control unit
continues to operate with the host processor. Subsystem
diagnostics that test the interconnections between control units
or that test the interconnections between the control unit and the
tape units cannot be used for concurrent maintenance on a dual
control unit subsystem. You can use the support diagnostics
when:
•

The error analYSIS diagram or FSI section calls for the
diagnostic

•

The product maintenance package does not fix a problem

•

You finish installation
Unless indicated in a specific diagnostic. the contents of
external registers may differ from the original diagnostic
display.

How the Support Diagnostics Are Organized
The support diagnostics test many parts of the subsystem.
Because you may not need to test everything in the subsystem,
the support diagnostics are divided into sections and routines.
The sections and routines can be selected to test only those parts
of the subsystem that are suspected of failing.

The tabie on DIAG 3 lists the identification code. the page on
which detailed explanations of the diagnostic sections and
routines begin, and the purpose of each diagnostic section or
routine. Also listed are the approximate run times. failure 10
examples for each routine, and prerequisite diagnostics. In
addition the table shows whether H~e routine or section can be
run in one control unit of a dual ccntrol unit subsystem while the
other controi unit operates with ine host processor (Type 1) or
whether the complete subsystem must be offline to run the
diagnostic (Type 2). Note that even Type 1 sections and routines
require you to taKe the subsystem oilline to run support
diagnostics in a single-control-unit subsystem. Use this table to
select the Identification code you want to use if you were not sent
to a particular diagnostic by another part of the maintenance
package.

E010 - CU Functions Test
This identification code causes the diagnostic control program to
run the diagnostic routines that test the internal circuits of the
control units. It does not test the tape units themselves and does
not test those circuits that can interfere with operations of a dual
control unit subsystem. This identification code can be used on
one control unit of a dual control unit subsystem while the other
control unit operates with the host processor.

EE10 - Processor Basic Tests
For control options, see the individual routines listed under this
diagnostic section on DIAG 3.

EE30 - Data Buffer Tests
For control options. see the individual routines listed under this
diagnostic section on DIAG 3.

EE40 - Control Unit to Drive Test
For control options, see the individual routines listed under this
diagnostic section on DIAG 3.

EE50 - Data Path Tests
For control options, see the individual routines listed under this
diagnostic section on DIAG 3.

EE60 - Channel Adapter Test
For control options, see the individual routines listed under this
diagnostic section on DIAG 3.

EE90 - Status Store Tests
For control options, see the individual routines listed under this
diagnostic section on DIAG 3.

EEAO - Tape Movement Tests
For control options, see the individual routines listed under this
diagnostic section on DIAG 3.

3480 MI EC A57721

Subsystem Diagnostics

DIAG 2

SUbsystOO iagnostics

o

The subsystem di agnostics exercise the subsystem. Four sets of
diagnostic exercisers are available:

o

o

o

Diagnostic routines and diagnostic sections are identified by an
identification code of EE plus a hexadecimal number. An E010 is
also assigned that runs a basic set of diagnostics that can be run
without disturbing a dual control unit subsystem.

Basic CU Test

•

Drive command exerciser

•

MD/MA diagnostic

•

•
•

Basic CU Test
Support diagnostics.

The correct function of the maintenance adapter connections
to the processor and control store

•

The control unit's ability to execute the microcode and forces
the executing of the ROS control store checkout

You can be directed to run particular subsystem diagnostics by
some other part of this Maintenance Information, for example,
from the EAD section or the FSI section. Or you can select
diagnostics from what is known about the problem.

Drive Command Exerciser
The drive command exerciser is a group of programs on the
support eli skette that permits you to enter and perform chains of
tape drive commands. The drive command exerciser operates in
concurrent maintenance mode.
The chains of commands can be used to isolate drive motion
problems or failures caused by a particular sequence of
commands. You can use either of two sequences of commands
that have already been selected, or you can make your own
sequence. The commands are entered from the maintenance
device keyboard/display.
See "Drive Command Exerciser" on DIAG 1 to find detailed
information about how to use the drive command exerciser.

MD/MA Diagnostic
The maintenance device/maintenance adapter diagnostic tests
the part of the maintenance adapter card that connects to the MD
and tests the communication path between the MD and the
maintenance adapter card. You can use this diagnostic when:

The basic control unit test verifies:

You can use this diagnostic to verify correct subsystem operation
after the maintenance adapter, processor, or control store cards
have been replaced. See "Basic Control Unit Test" on DIAG 1
for detailed information.

Support Diagnostics

Consist of microcode
Replace the functional microcode

•

Test the parts of the subsystem.

Because they replace the functional microcode, the support
diagnostics cannot be used for concurrent maintenance in a
single-control-unit subsystem. In a dual control unit subsystem,
those support diagnostics that test only the internal control unit
can be run on one control unit while the other control unit
continues to operate with the host processor. Subsystem
diagnostics that test the interconnections between control units
or that test the interconnections between the control unit and the
tape units cannot be used for concurrent maintenance on a dual
control unit subsystem. You can use the support diagnostics
when:
The error analysis diagram or FSI section calls for the
diagnostic

• The MD does not seem to communicate with the control unit.

•

The product maintenance package does not fix a problem

•

•
•

You finish installation
Unless indicated in a specific diagnostic, the contents of
external registers may differ from the original diagnostic .display.

See "Maintenance Device/Maintenance Adapter Diagnostic" on
DIAG 1 for detailed information about the MD/MA diagnostic.

Diagnostic sections consist of a group of diagnostic routines that
run in sequence. The sequences test particular areas of the
subsystem, such as the control unit data flow, the control unit to
magnetic tape drive interconnections, or the control unit buffer.
The diagnostic sections are useful when a general area is
suspected, but the specific function that may be failing within that
area is not known.

SUbSYSO Diagnostics

E010 runs control unit and tape unit data path diagnostic routines
in the following order: EE12, EE13, EE14, EE32, EE33, EE52,
EE53, EE64, EE85, EE92, and EE93.
When E010 runs, the diagnostic routines included in E010 use
their built in defaults. Parameter entries such as channel and
drive addresses and pattern numbers are neither required nor
allowed.
To rerun E010, use option 1 (RESTART DIAG.) on the DIAG.11
screen.
Note: You must take both control units offline (thus making the
complete subsystem unavailable to the customer) to run
any support diagnostic routines that are not included in
E010, except for channel wrap diagnostic routine EE62
(see instructions for setup).

EE10 - Processor Basic Tests
Diagnostic Routines
Diagnostic routines are the actual sets of microcode instructions
that perform tests on the parts of the" subsystem. Some, but not
all, diagnostic routines can be called by diagnostic sections.

•

The maintenance adapter card has been replaced.

Diagnostic Sections

o

Note: Loop until error is the only available option for this
section.

The support diagnostics are microprograms that can operate the
different parts of the subsystem independently of the subsystem
command operation. That is, the diagnostics:
•
•

o

Note: loop until error, and loop and bypass error are the only
available options for this routine.

Diagnostic Identification Code
The table on DIAG 3 lists the identification code, the page on
which detailed explanations of the diagnostic sections and
routines begin, and the purpose of each diagnostic section or
routine. Also listed are the approximate run times, failure 10
examples for each routine, and prerequisite diagnostics. In
addition the table shows whether the routine or section can be
run in one control unit of a dual control unit subsystem while the
other control unit operates with the host processor (Type 1) or
whether the complete subsystem must be offline to run the
diagnostic (Type 2). Note that even Type 1 sections and routines
require you to take the subsystem offline to run support
diagnostics in a single-control-unit subsystem. Use this table to
select the identification code you want to use if you were not sent
to a particular diagnostic by another part of the maintenance
package.

How the Support Diagnostics Are Organized

E010 - CU Functions Test
The support diagnostics test many parts of the subsystem.
Because you may hot need to test everything in the SUbsystem,
the support diagnostics are divided into sections and routines.
The sections and routines can be selected to test only those parts
of the ~ubsystem that are suspected of failing.

This identification code causes the diagnostic control program to
run the diagnostic routines that test the internal circuits of the
control units. It does not test the tape units themselves and does
not test those circuits that can interfere with operations of a dual
control unit subsystem. This identification code can be used on
one control unit of a dual control unit subsystem while the other
control unit operates with the host processor.

For control options, see the individual routines listed under this
diagnostic section on DIAG 3.

EE30 - Data Buffer and Buffer Adapter Tests
For control options, see the individual routines listed under this
diagnostic section on DIAG 3. The Improved Data Recording
Capability tests run automatically if the Improved Data Recording
Capability feature is installed.

EE40 - Control Unit to Drive Test
For control options, see the individual routines listed under this
diagnostic section on DIAG 3.

EE50 - Data Path Tests
For control options, see the individual routines listed under this
diagnostic section on DIAG 3.

EE60 - Channel Adapter Test
For control options, see the individual routines listed under this
diagnostic section on DIAG 3.

EE90 - Status Store Tests
For control options, see the individual routines listed under this
diagnostic section on DIAG 3.

EEAO - Tape Movement Tests
For control options, see the individual routines listed under this
diagnostic section on DIAG 3.

3480 MI EC A57723
"Copyri,ht IBM Corp. 1982,1988

IBM Con ,fidential

Subsystem Diagnostics

DIAG 2

o

()

()

{)

o

{)

o

o

o

()

o

o

o

sUbsv8m Diagnostics QntinUed)
Diagnostic Identification Code Table
Type

10

Code"
(MDlMA)

Page
DIAG

(See Note)

DIAG
30

EE10

EE12

DIAG

Load and Run
nmes
(ApproJdmate)

Failure 10
Example

Prerequisite
DI agnostics ....

Maintenance Device/Maintenance
Adapter Diagnostic. (MDlMA)

10 seconds

MD10xx

None

1

Basic control unit test. CU functions
test, diagnostic sectton. Runs
diagnostic routines EE12, EE13,
EE14, EE32, EE33. EE52. EE53, EE64,
EE85, EE92, and EE93.

5 minutes

CB10xx

None

1

Processor basic tests, diagnostic
section. Runs routines EE12, EE13,
EE14, and EE85.

1 minute and 5
seconds

1

Processor function test.

18 seconds

HC20xx

BCU

1

Interrupt level test.

18 seconds

HC30xx

BCU, EE12

1

Processor external register test.

18 seconds

HC40xx

BCU, EE12, EE13

1

CAF wrap test

45 seconds

KL4021

EE14

(See Note)

EE72

DIAG
DIAG

EE92

DIAG
70

EE30

Data buffer tests, diagnostic section.
Runs routines EE32 and EE33.

42 seconds

36 seconds

1

Status store wrtIrd RAM storage
test.

18 seconds

SS20xx

BCU, EE10

1

Status store order test.

18 seconds

SS30xx

BCU, EE10, EE92

2

Tape movement tests, diagnostic
section. Runs routInes EEA2, EEA3,
and EEA4.

7 mInutes and 30
seconds

2

BasIc tape motion test.

18 seconds

TM20xx

BCU, EE40, EE10

DIAG
510

2

Write/Read Exerciser.

3 minutes and 47
seconds

TM30xx

BCU, EE40, EE10,
EEA2

DIAG

2

Write/Read Exerciser.

4 minutes and 30
seconds

TM60xx

BCU, EE40, EE10,
EEA2

DIAG

DIAG
100

1

Data buffer data path test.

1 minute 30
seconds

BU20xx

BCU, EE10

EE33

DIAG
110

1

Data buffer controls.

40 seconds

BU30xx

BCU, EE10, EE32

EE40

DIAG

EEA2

Control Unit to drive tests,
diagnostic section. Runs routines
EE42, EE43, and EE44.

2 minutes
(16 drives)

EEA3

EEFO

DIAG
600

2

Scope loop utility.

Continuous

(EEF1)

DIAG
620

Not
Applicable

DrI ve Patch Load Utility.

Not
Applicable

Control Unit to drive bus out and
driver wrap test.

18 seconds

DI20xx

BCU

EE43

DIAG
160

2

Control Unit to drive bus and tag
test.

19 seconds

DI30xx

BCU, EE42

EE44

DIAG
170

2

Control Unit to drive serial test.

1 minute and 23
seconds (16
drives)

DI40xx

BCU, EE42, EE43

2

Data path tests, diagnostic section.
Runs routines EE52, EE53, and EE54.

54 seconds

1

Short loop write to read pattern test.

18 seconds

LW20xx

BCU, EE10, EE30

EE53

DIAG
218

1

Short loop write to read timing test.

18 seconds

LWJOxx

BCU, EE10, EE30,
EE52

EE54

DIAG
220

2

Long loop write to read test.

18 seconds

LW40xx

BCU, EE10, EE30,
EE52, EE53, EE40
BCU, EE10, EE30

The host processor channel cables must be disconnected before running this diagnostic.

•

Type 1 Di agnostics

•

Type 2 Diagnostics
-

The complete subsystem must be taken offline and made unavailable for customer use. Due to drive interface
interaction, run diagnostics from only one MD at a time.

Type 3 Di agnostics
The host processor channel cables must be disconnected before running this diagnostic.
Diagnostics can run in one control unit while the other control unit operates with the host processor.

•

10 codes within parenthesis cannot be used for diagnostic selection .

•• The prerequisite diagnostics for a routine must be run, in the correct order, and error free.

3

Channel interface wrap test.

45 seconds

CI20xx

BCU, EE10, EE30,
EE64

1

Channel Adapter function test.

51 seconds

CI40xx

BCU, EE10, EE30

300

EE70

The subsystem must be taken offline and made unavailable for customer use.

Dual Control Unit Subsystems

•

Channel Adapter test, diagnostic
section. Runs routine EE64.

DIAG
320

None.

Type 3 Di agnostics
-

EE10, BCU, EE30,
EE40

DIAG
200

DIAG

None.

Diagnostics can run in one control unit while the other control unit operates with the host processor.

EE52

EE60

None.

Type 1 and 2 Di agnostics
-

•

2

EE64

550

BCU

DIAG
150

EE62

EEA4

Note: Single Control Unit Subsystems

EE42

EESO

BCU, EE40, EE10

500

•
2

BCU, EE10

460

BCU, EE10

EE32

BCU, EE12, EE13,
EE14

Status store tests, diagnostic
section. Runs routines EE92 and
EE93.

EEAO

1

XBSOxx

1

DIAG

EE93

Reserved.

EE20

Prerequisite
Diagnostics ....

19 seconds

450

65
EE15

Failure 10
Example

External register bus addressing
and data pattern test.

EE90

55
EE14

Load and Run
nmes
(ApproJdmate)

1

50
EE13

Purpose

_lAG 3

Reserved.
DIAG

400

BCU

OSUbSystem DiagrGtics (Continued)

Type
Page

EE85

1

20
(BCU)

Purpose

ID
Code"

o

Reserved.

IBM Confider tlal-18 May 89

3480 MI EC A57723
g Copyright IBM Corp. 1982,1999

"--¥¥

Subsystem Diagnostics (Continued)

DIAG 3

o

o

()

()

o

()

o

o

o

o

o

c

c

c

c

o

10

Diagnostic Identification Code Table
Code·

I
I

(MD!MA)

I

Tlpe

~ ote
e~)

Page
DIAG
20

1

I

I

Purpose

I
Maintenance
I Device/Maintenance
Adaoter
Diagnostic. IMD/MAI EE12.
EE13. EE14, EE32. EE33. EE52.
EE53. EE64, EE85. EE92, and
I
EE93. See "E010 - CU
Functions Test."
Processor basic tests,
diagnostic section. Runs
routines EE12, EE13. EE14. and
I EE85.
Processor function test.

I Times
Load and Run
I

(ApDroximate)
2 minutes

1

II
EE12
Ei:13
EE14
EE20
EE30

I

EE32
EE33
I

EE40

I
I

I

I
I
I

DIAG
50
DIAG
55
I
DIAG I
65
I

!

I

EE50
EE52

I DIAG
100
DIAG
, 110

I

EE60

DIAG
150
DIAG
160
I DIAG
! 170
I
I

I

I

EE93

2
2

2

I

I

DIAG
300
DIAG
320

i
I

I

DIAG
400

I
I

I
I
I

3
1

Ii': IBM Corp "982. '986

BCU, EE12, EE13

I

42 seconds

BU30xx

I

BCU, EE10, EE32

Control Unit to drive tests,
diagnostic section. Runs
routines EE42. EE43, and EE44.
Control Unit to drive bus out
and driver wrap test.
Control Unit to drive bus and
tag test.
Control Unit to drive serial test.

2 minutes
(16 drives)

I

BCU

18 seconds
19 seconds

I

Channel interface wrap test.

I
I
I

DI20xx

i

DI30xx

I

1 minute and
23 seconds
(16 drives)
I 54 seconds

I DI40xx

I

I

I

!

I

f

18 seconds

I

18 seconds

!

Channel Adapter function test.

•

I

I
I

!

I

LW20xx

i

Purpose

2

Write/Read Exerciser.

2

Write/Read Exerciser.

2

Scope loop utility.

Aoolicable
I Not

Drive Patch Load Utility.

Load and Run
Times
{ADDroximate)
3 minutes and
47 seconds
4 minutes and
30 seconds
Continuous
Not
Aoolicable

Failure 10
Example

Prerequisite
Diagnostics ••

TM30xx
TM60xx

BCU, EE40,
EE10, EEA2
BCU, EE40,
EE10, EEA2
None.

None.

None.

The subsystem must be taken offline and made unavailable for customer use.

Type 3 Diagnostics
-

The host processor channel cables must be disconnected before running this diagnostic.

Dual Control Unit Subsystems
•

Type 1 Diagnostics
Diagnostics can run in one control unit while the other control unit operates with the host processor.

•

I

Type 2 Diagnostics
-

BCU
•

BCU. EE42

The complete subsystem must be taken offline and made unavailable for customer use. Due to drive interface
interaction, run diagnostics from only one MD at a time.

Type 3 Diagnostics
-

BCU, EE42, EE43

The host processor channel cables must be disconnected before running this diagnostic.
Diagnostics can run in one control unit while the other control unit operates with the host processor.

II

EE10, BCU,
EE30, EE40

ID codes within parenthesis cannot be used for diagnostic selection.

BCU, EE10, EE30

The prerequisite diagnostics for a routine must be run, in the correct order, and error free.

t

LW30xx

18 seconds

LW40xx

45 seconds

CI20xx

51 seconds

CI40xx

I

I
I

I
I
I

~ ote
e~)

Type 1 and 2 Diagnostics
-

BCU, EE10

I

I
I
I

BCU, EE10.
I
I
EE30, EE52
BCU, EE10. EE30, I
EE52. EE53. EE40
BCU, EE10, EE30

I

! Reserved.

1

I

3480 MI EC A57721

HC40xx

•

24 seconds

i

1

2

DIAG
I 500

I
I

BCU, EE12

Tlpe

Note: Single Control Unit Subsystems

BCU

Data buffer controls test.

I

I
i

I

I

External register bus
addressing and data pattern
test.
Status store tests, diagnostic
section. Runs routines EE92
and EE93.
Status store wrt/rd RAM
stora·oe test.
Status store order test.

I

i

I

I BCU, EE10

Data path tests, diagnostic
section. Runs routines EE52,
EE53. and EE54.
Short loop write to read pattern
I test.
! Snort loop write to read timing
i test.
Long loop write to read test.

I
I

I BCU
HC30xx

I
I

DIAG
510
DIAG
550
DIAG
600
DIAG
620

(EEF1)

18 seconds

I

EEA3

EEFO

I HC20xx

18 seconds

Page

EEA4

BCU

18 seconds

I
I

Code·

DIAG 3

I

BCU, EE10.
EE30, EE64
BCU, EE10. EE30

I Reserved.

!

~ C:Jpyr

i
!!
I

I

Prerequisite.
Diagnostics ••

BU20xx

Channel Adapter test,
Runs

1

I EEAO

EEA2

I

I

34 seconds

I

1
DIAG
450
DIAG
460

I

I

I

I

I
I

!

10

Example

1 minute and 5 I
I
seconds

I

section.
I diagnostic
routine EE64.

I

II

I

I

I

I

DIAG I 1
200
DIAG I 1
218
I
DIAG I 2
220
!

I

EE92

I

I

!

EE90

1

I
I

I
I

Interrupt level test.

1

2

I

I
I
I

Processor external register
test.
I Reserved.
! Data buffer tests, diagnostic
section. Runs routines EE32
and EE33.
Data buffer data path test.

2

I

I

,I
!

EE62

EE70
EE72
EE85

I

I

I
EE64

I

!

EE54
I

I

I

I

EE53

I

1
1

I

I EE43
EE44

1

I

I

I
EE42

1

I Faiiure

I

I
I
EE10

o

Subsystem Diagnostics (Continued)

Subsystem Diagnostics (Continued)

ID

c

2

Tape movement tests,
diagnostic section. Runs
routines EEA2. EEA3, and
I EEA4.
Basic tape motion test.

I
19 seconds

XB50xx

I
36 seconds

I

I 18 seconds
I

I

18 seconds

I

7 minutes and

I

30 seconds

I

18 seconds

I

I

i

I
I
I
I

BCU. EE10

I

SS20xx
SS30xx

I TM20xx
II

BCU, EE12
EE13. EE14

EE10
I BCU,
BCU. EE10, EE92
BCU, EE40, EE10

I
BCU, EE40, EE10

J
Subsystem Diagnostics (Continued)

DIAG 3

How to Use the Support Diagnostics

How to Use the Support Diagnostics

Theory Only -- The MD displays
in this diagram may not be the
same as actual MD displays.

*** MAIN MENU ***
ENTER A NUMBER
FROM THE FOLLOWING
LIST:

fJ

ENTER YOUR
DIAG SEL/ERROR CODE:
EG: D085

D

DO YOU WANT TO LOOP
THE DIAGNOSTICS?
(see DIAG 1 for
'Basic CU Test')

See DIAG 1 for
"Drive Command
Exerc i ser.

See DIAG 1 for
"Maintenance

Device/Maintenance
Adapter Diagnostic."

LI

0D

I=SUBSYS DIAGNOSTICS
2=SUBSYS DSPLY/ALTER
3=SUPPORT UTILITIES
4=END -SUPPORT CALL

r-------,
If a port open

THIS DIAGNOSTIC
**REQUIRES**THAT
BOTH CONTROL UNITS
ARE OFFLINE

-0I

SELECT :
1= MA REG
3= MA CMDS

I

[

I--------Ierror occurs
I
when selecting,
Irun MD/MA Diag.1
L Use
_ _EAD
_ _El03.
___ J

DIAG=(EE52)~ENTER~

DRIVE

----

2= MP CMDS
**ARE BOTH CONTROL
UNITS OFFLINE

II

]

---2 or 3

r Pr~s~i~g-the-PF ke~ 1

D

SUPPORT DIAG CNTRL
SECT I ON: EExx
#zz 1 - - - - - . ;
ROUTINE: EEyy
STS=
/RTN=

2 or 3

l

----,

r - - - -

See SDISK 1 for
I "Subsy'stem"Display/ I
Alter or Support
~t~l~t~e:.~ ____

l

J. -

-

-

-

10

J

U

.------------~I

1=
2=
3=
4=

3480 MI

4

0)

0)

3

8

DO YOU WANT TO RUN
ANOTHER DIAGNOSTIC?

No

for

"Mainten~nce

l

Adapter

Commands
as_needed.
_
_____
_ _ _ .....J

O=STEP, I=ERROR LOOP
2=LOOP RTN, 3=ADSYNC
4=LOOP SCT, 5=ADSTOP
6=IGNORE ERR, 7=RUN

I

ENTER

ENTER

-----,

Commands , or

----1---I

3

DO YOU WANT TO
BYPASS THIS
DIAGNOSTIC?

11M i cropr8cessor

(0
3, 4, or

[J

See SDISK

2

3 or 4

m

--->MP = STOPPED
MCR=OO MSB=84 MTI=20
ADR=????
DREG=????

r-----

r------------,
If a port error occurs
Iwhen selecting the
diagnostics, run MD/MA
1--------1 to ver i fy that port
open is the problem.
IXR problems can appear
be_MD
to_MA
problems
L to
__
__
__
_ _ _ .....J

J

r-------,

DlAG. II **SELECT:
1= RESTART DIAG.
2= TEST OPTN
3= MP CTRL, 4=EXIT

SELECTED DIAG.
BASIC CU TESTS
DR CMD EXERCISER
MD/MA DIAG.

Yes

at any time takes
you from this screenl
tot he DlAG. 1 1
:c~e=n~ ______
MACHINE FAILURES MAY
CAUSE CURRENT ERROR
DATA TO BE INVALID.
SEE DIAG 1 "VERIFY".

I Error information
- - - - screens. These are
I explained with the I
detai led explanation
~
Lo~ =a=h_rou~i:e~ _

J

DIAG 4

8=DISABLE MD SIGNAL

m

Yes

No

4

0)

I

o

PF

EC336395

How to Use the Support Diagnostics

© Copynght IBM Corp. 1984, 1985

7' ).

'\

~)

r)

DIAG 4

o

c

c

ni~nnoc:'ti,...c: l~on'tinll,::.rI\
.J-IO\I\I
-_ ...'to
- 11c:,::.
--- 'th,::.
.... - ~lInnor't
--,...,..._ ... ---::J'._-"'-,-_ ....... _--,

Support Diagnostic Flow

Note: Once the diagnostic microcode has been loaded, you
must perform an IMl on that control unit before normal
operation can be started again.

The flowchart on DIAG 4 shows the order of proceeding
through the support diagnostics. It does not show all the menus
because many of the menus are self-explanatory. The flowchart
is keyed to the text on this and the next two pages. The test
explains what the screenS mean and gives some suggestions
about how to interpret them.

In the following discussions, the reference keys refer to the
flowchart on DIAG 4.

To use the support diagnostics, you must know:

Note:

•

Running Support Diagnostics

When you are through running the diagnostics:

How the diagnostic programs are controlled.

Put the Normal/Test switch in the Normal position.

How to run the diagnostics for single-control-unit
subsystems and for dual-control-unit subsystems.

Put the channel Enable/Disable switch in the Enable
position.

What information the diagnostics will supply to you, and
how to use it.

Follow the instructions in "How to End Use of the
Diagnostics," located on DIAG 7, before putting the CU
Offline/CU Online switch in the CU Online position.

HO'.!\!

•

How to verify error data that may not be valid.
What options you have for controlling the diagnostics.
How to end use of the diagnostics.

Control of the Support Diagnostics
The diagnostic control program in the MD controls the running
of the support diagnostics. To permit you to control the way
the MD runs the diagnostics, the MD presents screenS on the
keyboard/display and reacts to your entries from the keyboard.
After you have made your selections, the diagnostic control
program selects the diagnostic routines and controls the order in
which they run. You can control which routines are run and the
order in which they run by entering:
•
•
•

A diagnostic section identification code
A diagnostic routine identification code
An error code
A fault symptom code (FSC).

•

The drive display
The operator's console printout
EREP
OlT.

You can get the fault symptom code from the MD
keyboard/ display.
If you enter an error code or a fault symptom code (FSC), the
diagnostic control program selects diagnostic routines
appropriate for that error code.
When the routine has been selected, the MD replaces the
functional microcode in the control unit with the diagnostic
routine microcode. Because the diagnostic routine microcode
replaces the functional microcode, you cannot perform
COncurrent maintenance using the support diagnostics.

3480
@

EC336395

CopyrIght IBM Corp. 19B4. 1985. 1986

......

lie.,. +ho
~ •• nn,.. .. +
"
"" .. I . " , ....,yl-'t""'.

ni~,..n,...,~+:"..,...
"""U~"V";;'''''''';;'

Set the CU Offline/CU Online switch to CU Offline.

2.

Now you are ready to run the support diagnostics.

Dual-Control-Unit Subsystem
Use this procedure when you run any support diagnostic other
than those included in the basic control unit tests (EO 10) on a
dual-control-unit subsystem.
1.

2.

Set the CU Offline/CU Online switch to CU Offline on both
control units.
On the control unit with the MD not attached, set the
Normal/Test switch to Test and press the IMl switch.
(This causes the control unit to stop and avoids interference
with the drives while the diagnostics run from the other
control unit.)

3.

On the control unit with the MD attached, set the
Normal/Test switch to Normal.

4.

Now you are ready to run the support diagnostics.

DIAG

-"

Connect the MD to the control unit that is to be tested, and
begin uSing the support diskette as explained in the SDISK
section of this maintenance information. Select the option of
using diagnostics by selecting option 1 from the main menu

STEP

Permits stepping through a diagnostic
section by stopping at the end of each
diagnostic routine. Each time the
ENTER key on the MD keyboard/display
is pressed, the next diagnostic routine
runs. You can also use this option with
the loop routine option to stop the
routine after each run.

ERROR LOOP

Causes the diagnostic routine to run to
the point of error and then restart the
test. The routine loops until the PF key
on the MD keyboard/display is pressed.

II-

When the diagnostic is in the process of loading from the
diskette and storing into control storage, problems can interfere
with the communications between the control unit and the MD,
causing 'Fast load' to stop. The control program then displays
a screen asking' PMA FORCE lOAD IT'.
A Yes response causes a 'Slow load' of the diagnostics

D.

Error loop causes the routine to loop if
no errors are detected.

You may run 'Basic CU Test', see E010 on DIAG 3.
LOOP RTN

loop routine. Causes the last routine
run to restart and loop until the MD
keyboard/display PF key is pressed. If
an error is detected, the loop ends and
an error screen is displayed unless
IGNORE ERR has also been selected.

ADSYNC

Address sync. Permits entering an
address for oscilloscope synchronizCltion.

LOOP SCT

loop section. Permits looping a section
of one or more diagnostic routines.
looping continues until an error is
detected or the PF key on the MD
keyboard/display is pressed.

ADSTOP

Address stop. Causes the microprogram
in progress to stop when the storage
address you have entered is reached.

IGNORE ERR

Ignore error. Disables the check 1 error
stop. If this option is used at the same
time as the loop routine option, the
routine restarts when an error occurs.

The diagnostics supply two controls at the start of the
diagnostics and several control options when the diagnostic
finishes the first pass.
Controls at the Start of the Diagnostics

1.

,.1,

au.:;;;",/

Result

Single-Control-Unit Subsystem
Use this procedure when you run the diagnostics on a
single-control-unit subsystem or when you run the basic control
unit tests (EO 10) on a dual-control-unit subsystem.

, 1'" .... +: ............

\ '"'VI I LII

Option

Controlling the Diagnostics

You can get the error code from:
•

to

0

0

Getting the Diagnostics Running

A No response causes a return to
•

0

0

0

When you start running the Basic CU tests, the diagnostic
control program lets you select whether to loop the diagnostics
1]. If you choose to loop the diagnostics, the diagnostics loop
until an error occurs.
When you choose to run selected diagnostics, the diagnostic
control program lets you specify the diagnostics to be run. You
enter your selection on a diagnostic selection menu
You can
enter the identification code for a diagnostic section or a
diagnostic routine, or you can enter an error code or a fault
symptom code. Following the selection of certain diagnostic
sections or diagnostic routines, you can select the drive,
channel, and test pattern that you want to use

fl.

EI D.

Controls at the End of the First Pass
When the diagnostic stops, either because of an error or
because it ran without errors, you can select from a number of
options. The first menu
permits you to select changes in the
way the diagnostic is running or to look at certain information.
If you want to change the control options for the diagnostic
(selection 2), you can get the drive, channel. and pattern

III

EI D,

1m

selection menu
and you get the test options menu
The selections from the test options menu cause the
following results.

m.

The last routine (of a section), will be Jhe first routine run when
an option, drive address, channel address, or test pattern is
changed.

DISABLE MD SIGNAL Ends diagnostic to MD signalling. This
option can be used with the ADSYNC
and LOOP RTN options to increase the
oscilloscope triggering rate.
RUN

This option starts the diagnostic
operating under the conditions that you
have established with your other option
selections. This option must be entered
as the last option selected. The last
routine (of a section), will be the first
routine run when an option, drive
address, channel address, or test pattern
is changed.

How to Use the Support Diagnostics (Continued)

DIAG 5

How to Use the Support Diagnostics (Continued)

How to Use the Support Diagnostics (Continued)

GOOD

Information Supplied by the Support
Diagnostics

Diagnostic complete with no errors

Address Meaning

OAT A(XX} Expected data, actual data is shown in the
/RTN field

y011

The support diagnostics supply three kinds of information:
•
•
•

A status screen
Error screens
Common stop addresses

PGMFLAG

Program flag

MTIERR

Maintenance-tags-in error (see note 1)

LOOPREQ

Error loop request

CHECK1

Check 1 error, not stopped (see note 1)

The branch operation did not work. The
microprocessor has failed. See the FSI section for
'"Error Code E 100."

For example, if you were running EE32 and the diagnostic
stopped with ERROR displayed as the status on the status
display:
1.

Press the ENTER key to display the first error screen.

y012

A test failed in this routine.

2.

Assume the first six characters on the first error screen are
BU2021.

y013

A get pointer error occurred. Indicates a
microprogram error.

3.

Look in the chart in the description of EE32 and find
BU2021.

4.

The chart explains that a buffer channel status error
occurred and that the FSI section for error code 05nn
should be used.

Status Screen
When a diagnostic routine is running or ends, with or without an
error, the status screen
(see DIAG 4) displays. If the routine
did not have an error and more than one routine is to run, the
screen displays only momentarily, then it is replaced with the
loading screen from the next routine. If an error occurred or no
more screens are to run, the diagnostic stops with the status
screen displayed. The status screen displays:

II

•

/RET

=

Return code

40

Good return

03

Error

y014

The routine ended successfully (Normal end).

y015

Reserved.

y016

A command that was not valid was received from the
MD. Rerun the routine. If the routine runs
successfully, ignore the error. If the routine fails
repeatedly, see FSI section for '"Error Code E 100."

Press ENTER for message from the diagnostic
•
•

•

•

SECTION = The name of the diagnostic section
ROUTINE = The name of the diagnostic routine
# = Control options

Note 1:
If STS = DATA(XX}, /RTN = actual byte received.
If STS = CK 1STOP or CHECK 1, /RTN = maintenance
status byte (MSB) (see note 2).
If STS = MTIERR, /RTN = maintenance tags in (MTI)
(see note 2).
If STS = PGMFLAG, /RTN =
80 = Loop routine (diagnostic)
40 = Loop on error
20 = Ignore error.

ZZ

No options

EL

Error loop

LR

Loop routine

IE

Ignore errors

EI

Error loop and ignore errors

LI

Loop routine and ignore errors

AD

Address sync

Error Screens

EA

Error loop and address sync

LA

Loop routine and address sync

AI

Address sync and ignore errors

In addition to the status screen, each diagnostic can supply you
with error screens
(see DIAG 4). The error screens follow
the status screen only if an error occurred. The error screens are
made for the particular diagnostic, so they are explained in the
description of each diagnostic.

EX

Error loop and address sync and ignore errors

LX

Loop routine and address sync and ignore errors.

STS

=

Note 2:
See '"Error Screens" if no screens are available.
See EAD 1 for E 100 or Fnnn.

RUNNING

Diagnostics running

STOPPED

Diagnostics stopped

CK1 STOP

Check 1 error, stopped

LOOPING

Diagnostic looping

ERROR

Error has occurred (see note 1)

y017

The MD connection is broken.

y018

The maintenance adapter card detected an error
during microprocessor to MD communications.

When an error occurs while running the diagnostics, the
diagnostic stops with the status screen displayed. When the
status is ERROR, use the information from the error screens as
follows:

m

MACHINE FAILURES MAY
CAUSE CURRENT ERROR
DATA TO BE INVALID.
SEE DIAG 1 "VERIFY".
This message is referred to by routines EE 12, EE 13, EE 14, and
EE85. The message tells you to make sure that the data
displayed by the error displays is correct.
Either XR address bus or XR data bus errors can occur that can
cause the data that is read by the microprocessor to be invalid.
The microprocessor then displays this invalid data as the data on
the error screen. To make sure that you know that you have the
correct data, you must verify the error screen display.

Press the enter key to advance to the first error screen.

2.

Write down the information from the error screen.

3.

Press ENTER to advance to any following error screens and
write down the information from those screens.

1.

Write down the error display data as explained under "How
to Use the Information Supplied by the Diagnostics."

4.

Look at the first six characters from the first error screen.
These constitute a failure 10 code.

2.

5.

Look up the failure 10 code in the chart that is part of the
description of the routine in this section of the maintenance
information. The chart tells you what failure occurred and
sends you to the error analysis diagram (EAD) that guides
you in troubleshooting that error. The other information
recorded from the error screens is used to analyze the error
using the EAD.

Display the control unit scan rings. Note that the XRA
register information is formatted differently on the scan ring
display than it is on the diagnostic display. See SDISK 1 for
'"Control Unit Scan Rings." and OF 1 for "XRA Register."

3.

Write down the data in ERA, ERB, and the XRA registers.
Also write down the value of the XR error bit (PSR bit 0).

4.

Compare the data from the scan rings with the data from
the error display.

5.

If the data is different, use the data from the scan rings.

6.

If the data from the error display is valid, you do not need to
verify the data again while diagnosing the failure.

When a diagnostic routine completes its run, it branches to a
stop address. The stop addresses supply diagnostic test result
indications.

m

Some error screens can send you to the following reference
screen.

1.

Common Stop Addresses

To obtain the stop address at which a diagnostic routine has
stopped, you must select 3 from the DIAG. 11 screen
(see
DIAG 4) and display the MA REGS. The address shown on the
MP = STOPPED screen
is the stop address.

Verify

How to Use the Information Supplied by the
Support Diagnostics

EJ

Status of diagnostics

DIAG 6

6.

When the failure has been repaired, load functional
microcode into the control unit, insert the product diskette
into the MD, and select the Unit Test option to verify that
the subsystem operates correctly.

The following stop addresses are common to all diagnostic
routines except EEA4 (where Y ~ 6), and EEFO (where Y ~. 0).
The y represents the second hexadecimal digit following the EE
in the name of the diagnostic routine as shown on the status
screen
(see DIAG 4).

II

3480 MI

How to Use the Support Diagnostics (Continued)

EC336395

~ Copyrtgh. IBM Corp. 1984. 1985

()

{)

r)

DIAG 6

o

o

o

o

o

o

How to Use the Support Diagnostics (Continued)
How to Use the Diagnostic Test Options
The test options for the support diagnostics are very versatile,
but you must understand some features of the programs to use
the options most effectively. The control program in the MO
interacts with the diagnostic programs to control the way the
options function. The options perform somewhat differently for
running a diagnostic section than they do for running a
diagnostic routine.
In running a diagnostic section or running from an error code
entry, the MO selects a group of routines to be run. The MO
then gives you the opportunity to select step mode or to loop
the section. Selecting either of these options at this time
(before the routines have started running) affects all of the
routines. Selections made after the routines are running can
affect a single routine or all the routines.
In running a diagnostic routine, you cannot select run options
until after the first pass of the routine. Any option selected
applies only to the one routine because only one routine is
running.

Some Examples of Using the Diagnostic Test
Options
The following discussion does not give all the possible
combinations for use of test options. It illustrates two ways in
which the options can be used so that you can see how to
devise other uses for them.

DIAG 7

How to Use the Support Diagnostics (Continued)

When the section starts, routine 1 runs and stops. When you
press the ENTER key, routine 2 runs and stops. Presuming that
we have no errors on the first pass, routines 3 and 4 run in the
same way as routines 1 and 2. When you press ENTER after
routine 4 stops, routine 1 starts again as shown by loop

How to End Use of the Diagnostics

Enter

When you are through running diagnostics, go to OIAG. 11 either
by pressing the PF key on the MO keyboard/display or by
pressing the ENTER key if you are stopped with GOOD displayed
(see OIAG 41. Selection 4 on the
on the status screen
OIAG. 11 screen 11.1 (see OIAG 4) takes you to the support
(see OIAG 41. You can then choose to
diskette main menu
use some other facility from the support diskette or you can end
the call (selection 4 on the main menu).

m.

II
II

Now, on the second pass, let us say that an error occurs in
routine 2, so routine 2 stops with the error indication. You can
modify the run options at this time by using selection 2 from the
OIAG. 11 screen (11.1 on OIAG 41.
Let us say that you select ERROR LOOP. The routine enters loop
After you analyze the
failure, you can get to the OIAG. 11 screen again by pressing PF.
Let us say that you select RUN with no other options. This
selection clears step mode and loop routine from the flags in
routine 2. Now, routines 3 and 4 continue in step mode and we
return to loop
where routine 1 runs in step mode. However,
routine 2 does not stop to permit you to press enter before
routine 3 starts. (Remember, you cleared step mode in routine
2.)

III, and you can analyze the failure.

III

To end the call:
Routine 2

III

1.

m

Routine

3

Using Loop Routine
Each routine contains indicators called flags that the MO sets
and tests to determine what control options are effective for
each run of a routine. If step mode or loop section options are
selected at the beginning of the run, the MO sets the
corresponding flags on in each routine in the section. During the
run, other options can be selected that affect single routines in
the section. Selecting run with no other options selected clears
all the options for that routine.

o

o

See the figure on this page again. This time let us say that we
selected a diagnostic section and will loop the section but not in
step mode. When the section begins, routine 1 runs, followed
by routines 2, 3, and 4, then loop
starts the operation
again. Let us say that on one of the passes an error occurs in
routine 4. The diagnostics stop in routine 4 and you select
LOOP RTN as a test option. This selection starts us in loop
Let us say that you cannot get a failure while running in the
LOOP RTN options, so you press the PF key to get to the
OIAG. 11 screen to select another option. To return to loop
you must select LOOP SeT for the test option. (Remember, if
you just select RUN, you clear all the control options for that
routine.)

m

m.

Routine

4

ILl
2.

If you have repaired the failure:
a.

Remove the support diskette from the MD.

b.

IML the functional microcode into the control unit.

c.

Insert the product diskette into the MD.

d.

Select the unit test option to verify that the subsystem
operates correctly.

e.

Return the eu Offline/eU Online switch to the eu
Online position.

f.

Return the subsystem to the customer.

If you have not repaired the failure, follow the defer call
procedure or other procedure to continue with the analysis
of the failure.

m,

Using Step Mode. Loop Routine. and Error Loop
Refer to the figure on this page. Let us assume that we selected
a diagnostic section and answered yes to the questions "Do you
want to loop the section?" and "Do you want to run in step
mode?"

3480 MI

EC336395

C CopyrighllBM Corp. 1984. 1985

How to Use the Support Diagnostics (Continued)

DIAG 7

Maintenance Device / Maintenance Adapter Diagnostic
This diagnostic tests the communication path between the
maintenance device and the maintenance adapter card in the
control unit. The diagnostic tests the cables and the part of the
maintenance adapter card that communicates with and responds
to the MD.

FAilURE ID
MD1020

When the maintenance device/maintenance adapter diagnostic
is selected (selection 4 on the subsystem diagnostics screen), all
tests are automatically run. When the diagnostic stops, one of
the following screens will be displayed:
•

Test complete screen

•

Tag active screen (failure 10; MD1020)

•

Function error screen (failure 10 ; MD2025).

Pressing Enter from any of these screens takes you to a
selection screen.

** SELECT: I.RESTART
2.PUT TEST 3.GET TST
4.0PEN TEST
5.STATUS OUT TEST
This screen permits you to select the tests you want to run.
Selection 1 restarts the complete maintenance
device/maintenance adapter diagnostic. The other selections
run the tests identified. PF 1 stops the tests and returns you to
the main menu.

Open Test
This test shifts a data byte of hexadecimal 5A from the
maintenance device through the maintenance adapter shift
register.

DESCRIPTION
MD display lines 2-4 indicate that one
or more inbound signal lines are active
(zero volts).
This error message wi 11 vary depending on
the state of each signal line named.

ADDITIONAL ACTIONS

FRU115

These signal lines may be held active
(zero volts) by the microcode in the CU,
To eliminate this as the cause of the
problem, do a power on reset (POR) to
the control unit by removing the IMl
diskette, and pressing the IMl switch.
The test may be restarted by pressing
enter on the MD keyboard and responding
"YES" to the "RETRY" message.

FRU169

The program detected that an internal MD
failure has occurred.

Replace the MD.

MD1025

The Port function indicated by the 'xxxx'
field has fai led. The order of testing is:
OPEN, PUT, GET, and STAT.

1.

The error Status Byte (aa) definition is:
48 = Timed out waiting for the
function to complete. (Caused
by a missing signal.)
81 = If the 'xxxx' field = OPEN, this
status byte means the serial data
path has fai led.
If the 'xxxx' field = PUT, GET,
or STAT, this sense byte means an
error condition occurred. (Caused
by an unexpected active Signal.)

FRUS

An active level (zero volts) on
'status in' will force 'read' active.
'Status in' is controlled by the MD.
Test this line at the maintenance
adapter card if 'read' is active.

MD1035

Selection Screen

DIAG 20

MD / MA Diagnostic

FRU117
FRU135

MD

Execute the MD diagnostic tests.
See the "IBM Maintenance Device
Maintenance Information."

FRU 115

2.

See EAD 1 for El03 errors.

FRU134

3.

See OPER 1, "Maintenance Device
to 3480 Maintenance Adapter
Communication Path," for the signal
lines used during the OPEN, PUT,
GET, AND STAT tests. Use this
information to find the fai ling
line, and use the status byte (aa)
to show what type of fai lure
occurred on that line.

FRU135

FRU 117

FRU169

ERROR DISPLAYS
MD1020 ** ERROR
MD 'WRITE'
ACTIVE
MD 'READ'
ACTIVE
MD 'STS OUT' ACTIVE

MD1035 ...... ERROR
THE MD IS FAiliNG

MD2025 ** ERROR
PORT 'xxxx' FAilED ..
STAT= aa
(ENTER = lOOP)
xxxx = OPEN
PUT

GET

STAT
aa = Status Byte

Put Test
This Test sends a hexadecimal 55 (Load Data Reg 1) command
to the maintenance adapter with a data byte of hexadecimal 5A.

Get Test
This test sends a hexadecimal 5E (Unload The MTI Reg)
command to the maintenance adapter and receives a data byte
of hexadecimal 20.

Status Out Test
This test sends a data byte with bad parity to the maintenance
adapter and checks that the maintenance adapter signals that
the byte is wrong.

3480 MI

EC336395

e Copynght IBM Corp. 19B4, 1985, 1986

,

t

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MD / MA Diagnostic

DIAG 20

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Basic Control Unit Test
The purpose of the basic control unit test is to assure that the
maintenance adapter, processor, and control storage functional
areas operate correctly.
This test consists of two major sections. The first section uses
the maintenance adapter to MD interconnection to test:
•

The MA data and address registers

•

The control unit controi storage data bus

•

All control storage address bus

•

The control unit microprocessor's ability to execute the
resident IML microcode.

The IML microcode will detect errors in the microprocessor,
external registers, and control storage areas.
The second section of the test loads and executes all the basic
support micro-diagnostics that are defined in EO 10 - CU
Functions Test (see DIAG 11.

c

c

o
Basic Control Unit Test

FRUS

o
DIAG 30

Basic CU Test Messages

See CARR-CU or CARR-DR, pages 1-1, 1-2, 1-3, and 1-4 for
the na~es and locations of the FRUs.

****

TESTING THE MA REGS
*** MAIN MENU ***
ENTER A NUMBER
FROM THE FOLLOWING
LIST:

TEST DATA=xx
xx

I

55

I=SUBSYS DIAGNOSTICS
2=SUBSYS DSPLY/ALTER
3=SUPPORT UTILITIES
*END OF LI ST*

1=
2=
3=
4=

B2
C4

1

SHECTED DIAG.
BAS IC CU TESTS
DR CMD EXERCISER
MD/MA DIAG.

I

27100 ** DO YOU
WANT TO LOOP THE
DIAGNOSTICS

Test data is:
00
FE
AA

****

TESTING CONTROL
STORAGE
PATTERN=xxxx
xxx x

Test data pattern is:
0000
FEFE
AAAA

5555
B2B2
C4C4

****

If 'no' is the answer, the CU Basic and EO 10 linked tests run
one pass.
If 'yes' is the answer, the CU Basic and E010 tests will run on
the first pass, and on the second and succeeding passes only
EO 10 will run.
If no failures are detected, the following message is displayed
after the diagnostics have completed: 'BASIC CU DIAG RAN
ERROR FREE'.

3480 MI

EC336395

RUNN ING THE IML
DIAGNOSTICS

** CU BASIC TEST
RAN ERROR FREE

Basic Control Unit Test

DIAG 30

Basic Control Unit Test (Continued)

Basic Control Unit Test (Continued)

1.

FOLLOW STEPS 1 AND 2 BEFORE TAKING ANY OTHER ACTIONS:
C81023

MD display 1 i ne 1 can also show:

FRUS

ADDITIONAL ACT IONS

DESCRIPTION

FAILURE ID

CB1023 **DATA COMPARE.

Data is written to and read back from four maintenance
adapter card registers (rrrrr).

2.

DIAG 32

ERROR DISPLAYS

If the value of ERA or ERB is other than 00, see the FSI
section for error code E 100.
If PSR bit o = 1, see the EAD 1 for error code Fnnn.
1.

2.

Remove the IML diskette from the control un it, then
press the IML swi tch to cause a power on reset.

FRU 115
FRU169
FRU139

Respond YES to the RETRY message on the MD display
to restart the test.

If the EXPECTED data equals the ACTUAL data, the parity
bit (which is not shown) is causing the error.

CB1023 **DATA PARITY
ERROR .. (rrrrr)
EXPECTED DATA = (xx)
ACTUAL DATA
= (xx)
rrrrr = DREGI
DREG2
AREGI
AREG2

CBI025

See the FSI section for error code El00.

MD display line 1 can a I so show:
CB1025 **ADDR PARITY
CB1025 **DATA PARITY
CB1025 **CS DATA BUS

FRU134
FRU135
FRU 115
FRU 117
FRU139

CB1025 *'\ADDRESS BUS
ERROR ..
EXPECTED = (xxxx)
ACTUAL
= (xxxx)

FRU 117
FRU 115
FRU139

CB1026

.1.-.1..

MP FAILURE

FRU 117
FRU 115
FRU139

CB1027

.\...1..

MP FAILURE

Data is written to and read back from control store, and
the EXPECTED and ACTUAL values are displayed if an error
occurs.
If the EXPECTED data equals the ACTUAL data, the pa r i t Y
bit (which is not shown) is causing the error.
CB1026

CB1027

CB1028

The extended operation bit in the maintenance status byte
(MSB) register did not reset after a 'Stepmp' operation.

The instruction executed bit in the maintenance status
byte (MSB) register did not activate after a Force
Instruct i on and 'Stepmp' command operation.

MD display 1 i ne 2 can also show:

ERROR .. **ADDR PARITY

A reset is issued to the MP fo 11 owed by two 'Step'
commands. This results in a hardware forced branch to
address 0000 and the execution of the first PROM
instruction.

1.

Remove the IML diskette, then press the IML swi tch to
cause a power-on reset.

2.

Select and run the "Basic CU Test" option again.

3.

Check the top card connectors on the logic card FRUs
1 is ted for this error.

1.

Remove the IML diskette, then press the IML switch to
cause a power-on reset.

2.

Select and run the "Basic CU Test" option again.

3.

Check the top card connectors on the logic card FRUs
1 is ted for this error.

Go to the PWR section, "MAP 0100--Power Start, "
point A, and fo 11 ow the power MAPs.

entry

Run diagnostic 'E010' .
Check the top card connectors on the logic card FRUs
1 is ted for this error.

FRU 117
FRU 115
FRU139

., ...

MP RESET
CB1028
ERROR .. h\ I NVAL I D ADR
EXPECTED = (xxxx)
ACTUAL
= (xxxx)

If the EXPECTED data equals the ACTUAL data, the parity
bit (which is not shown) is causing the error.

3480 MI

EC336395

~ Copvnght IBM Coo-p. 1984. 1985

Basic Control Unit Test (Continued)

DIAG 32

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Basic Control Unit Test (Continued)
ADDITIONAL ACTIONS
1.

FOLLOW STEPS 1 AND 2 BEFORE TAKING ANY OTHER ACTIONS:
2.
CB1036

o

Basic Control Unit Test (Continued)

DESCRIPTION

FAILURE 10

o

This error is generated by the PROM diagnostic program
that tests CU Control Storage.

FRUS

ERROR DISPLAYS

FRU135
FRU134
FRU115
FRU117
FRU139

CB1036 ** CS FAILURE
ERA=aa) ERB=bb) #CKI
DATA ADDRESS= (xxxx)
DATA PATTERN= (xxxx)

o
DIAG 34

If the value of ERA or ERB is other than 00, see the FSI
section for error code El00.
If PSR bit 0 = 1, see the EAD 1 for error code Fnnn.
Run diagnostic E010.

MD display 1 ine 2 wi 11 contain a I#CK1" if a check 1
condition occurred.
Register data is defined in the maintenance information
OF section.
CB1037

This error is generated by the PROM diagnostic program
while testing basic CU functions.
MD display 1 ine 2 wi 11 contain a "#CK1"
condition occurred.

Run diagnostic E010.

FRU 117
FRU115
FRU121
FRU085 1
FRUl14
FRU120
FRU116
FRUl19
FRU188
FRU139

if a check 1

Register data is defined in the maintenance information
OF section.

CB1038

This error is generated by the PROM diagnostic program
while testing basic CU functions.
MD display 1 ine 2 wi 11 contain a I#CK1" if a check 1
condition occurred.

See EAD 1 for error code Fnnn.
XR errors can cause ERA and ERB errors.
to check the ERA and ERB registers.

Use routine EE85

Run diagnostic E010.

Register data is defined in the maintenance information
OF section.

CB1041

An error occurred while trying to read error data from
the control unit.

1.

2.

Remove the IML diskette from the control unit, then
press the IML switch to cause a power on reset.
Respond YES to the RETRY message on the MD display to
restart the test.

FRU121
FRUl18
FRU 117
FRUl15
FRUl14
FRU120
FRU119
FRUl16
FRU134
FRU135
FRU157
FRU158
FRU159
FRU139
FRUl15
FRU117
FRU169
FRU139

CB1037 ** MP FAILURE
ERA=aa) ERB=bb) #CK1
XRA=xx) MTI=tt>
PSR=pp PCR=cc PER=ee

CB1038 ** XR FAILURE
ERA=aa) ERB=bb) #CKI
XRA=xx) MT I=tt)
PSR=pp PCR=cc PER=ee

CB1041 MA CONNECTION
ERROR ..
-RESET THE CU.
(ENTER = RETRY)

See DIAG 1 for "Maintenance Device/Maintenance Adapter
Diagnostic. II
CB1045

The PROM diagnostic failed to complete successfully, and
the error code is i nval id.

1 This FRU is EC sensitive.

3480 MI

EC336395

Cl Copyright IBM Corp. 1984. 1985

1.

Remove the IML diskette from the control unit, then
press the IML switch to cause a power on reset.

2.

Press the enter key on the MD.

3.

Select and run the "Basic CU Tests" option again.

FRU 115
FRUl17
FRU169
FRU139

CB1045 **INVALID IML
ERROR CODE = (xxxx)

See CARR-DR 4.

Basic Control Unit Test (Continued)

DIAG 34

Processor Function Test - Routine EE 12
Prerequisite diagnostics must run without failure before
this diagnostic is run. See DIAG 3, "PREREQUISITE
DIAGNOSTICS ...

Routine EE12
FAILURE ID
HC2021

Failure occurred when testing branch
conditions for active and reset conditions.

This routine provides a general check of the microprocessor data
flow, including:

HC2022

Failure occurred during local storage
paging or addressing operations.

•

Branching

HC2023

•

Local storage access and storage capabilities

Local storage register failed when
tested with AA, 55, and 01 patterns.

•

Paths to external registers

HC2024

•

Control storage access and storage capabilities.

Routine Start Address: 2010

If no error occurs, the routine loops as if "LOOP
ROUTINE" is set. When an error is detected, the routine saves
the error information and displays the error on the MD. After
the error is displayed, the routine continues to loop on that error.
However, if a different error occurs, that new error is displayed
on the MD, and the routine will loop on the new error.

ADDITIONAL ACTIONS

DESCRIPTION
I.

Remove the IML diskette, then press the
IML switch to cause a power-on-reset.
Run routine EEI2 again.

2.

If the value of ERA or ERB is other
than 0, see the FSI section for error
code EIOO. Also see action number 4
of this Additional Actions column.

External register immediate operation
fa i led.

3.

If PSR bit 0 - I, see EAD I for error
code Fnnn.

HC2025

Failure occurred during a register to
register operation.

4.

HC2026

Local storage
fa i led.

If a diagnostic failure occurs and no
errors are detected by the hardware,
see the FSI section for error code
EIOO and perform the procedures for
the microprocessor and control
storage.

Error Loop:

HC2027

~egister

immediate operation

Failure occurred during a processor to
control storage operation.

5.

FRUS
FRUI21
FRUI18
FRUI17
FRUI15
FRUI14
FRUI20
FRUI19
FRU116
FRU134
FRU135
FRUI57
FRU158
FRU159
FRU139

DIAG 50

ERROR DISPLAYS

nnnnnn
ERA ACT = xx,EXP= yy
ERB ACT - xX,EXP- yy
PSR ACT - xX,EXP- yy

PER ACT = xX,EXP- yy
MTI ACT - xX,EXP- yy
XRA ACT = xX,EXP= yy
MDI- md,WR= dw,RD-dr

MACHINE FAILURES MAY
CAUSE CURRENT ERROR
DATA TO BE INVALID.
SEE DIAG 1 "VERIFY".

XR errors (PSR bit 0 - I) can cause
ERA and ERB errors. Use diagnostic
EE85 to check the ERA and ERB
registers.

This screen is explained
on DIAG 6.

Error Displays
When an error is detected by the diagnostic program, the
maintenance device displays error information on its
keyboard/display. The first screen displays automatically. You
can see the second and following screens by pressing the
ENTER key on the keyboard/display.

nnnnnn = Failure 10
xx = The actual contents
of the external
register
yy
The expected contents
of the external
register
md = Contents of the
maintenance data
in register
dw
Data wr i tten
dr = Data read

-

The format of the display's first line is the same for all detected
errors. The remaining three lines contain additional information
about the failure.

-

External registers are defined in the OF (Data Fields) section of
this maintenance information.

FRUS
See CARR-CU or CARR-DR, pages 1-1, 1-2, 1-3, and 1-4 for
the names and locations of the FRUs.

3480 MI
It Copyright

Routine EE 12

EC336395

IBM Corp. 1984. 1985

n

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{)

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DIAG 50

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Interrupt Level Test - Routine EE 13
Prerequisite diagnostics must run without failure before
this diagnostic is run. See DIAG 3, "PREREQUISITE
DIAGNOSTICS."

Routine EE 13
FAILURE ID

DESCRIPTION

ADDITIONAL ACT IONS

HC3021

Fai lure occurred when testing if interrupts can be
suspended.

This routine tests the microprocessor interrupt handling for
interrupt levels 0 through 7.

HC3022

Invalid subroutine return code.

Routine Start Address: 3010

HOO23

The interrupt mask register ( I MR) has bits that won't
change. They are fixed in either an ON or an OFF
position.

HC3024

Whi Ie using the interrupt mask register ( I MR) an XR
error is detected.

HC3025

The local store page was not saved correctly or a PSW
swap occurred to the wrong interrupt I eve 1.

3.

If PSR bit o = 1 , see EAD 1
for error code Fnnn.

HC3026

An XR error occurred wh i Ie exercising the processor
external registers.

4.

If a diagnostic fai lure
occurs and no errors are
detected by the hardware,
see the FSI section for
error code El00 and perform the procedures for
the microprocessor and
control storage.

Error Loop: If no error occurs, the routine loops as if "LOOP
ROUTINE" is set. When an error is detected, the routine saves
the error information and displays the error on the MD. After
the error is displayed, the routine continues to loop on that error.
However, if a different error occurs, that new error is displayed
on the MD, and the routine will loop on the new error.

Error Displays
HC3027

The interrupts occurred in the wrong sequence.
current and/or previous values are wrong.

HC3028

Extend bits for external register addressing were not
saved and set/reset correctly.

HC3029

The format of the display's first line is the same for all detected
errors. The remaining three lines contain additional information
about the failure.

Extend bits for external register addressing were not
saved and set/reset correctly.

HC302A

The local store page was not saved correctly or a PSW
swap occurred to the wrong interrupt leve 1.

External registers are defined in the OF (Data Fields) section of
this maintenance information.

HC302B

An XR error occurred wh i Ie exercising the processor
external registers.

HC302C

The interrupts occurred in the wrong sequence.
current and/or previous values are wrong.

HC302D

Extend bits for external register addressing were not
saved and set/reset correctly.

HC302E

The condition code is not set correctly in the PSW.

HC302F

The local store page was not saved correctly or a PSW
swap occurred to the wrong interrupt leve 1.

See CARR-CU or CARR-DR, pages 1-1, 1-2, 1-3, and 1-4 for
the names and locations of the FRUs.

3480 MI

EC336395

~ COPYright IBM Corp. 1984. 1985

The PSR

Remove the IML diskette,
then press the IML switch to
cause a power-on-reset.
Run routine EE13 again.

2.

The PSR

When an error is detected by the diagnostic program, the
maintenance device displays error information on its
keyboard/display. The first screen displays automatically. You
can see the second and following screens by pressing the
ENTER key on the keyboard/display.

FRUS

1.

5.

If the value of ERA or ERB
is other than 0, see the FSI
section for error code El00.
Also see step 4 of this
Additional Actions column.

XR errors (PSR bit 0 = 1)
can cause ERA and ERB errors.
Use routine EE85 to check
the ERA and ERB registers.

o

c
FRUS
FRU121
FRU118
FRU117
FRU 115
FRU114
FRU120
FRU 119
FRU 116
FRU134
FRU135
FRU157
FRU158
FRU159
FRU139

DIAG 55

ERROR DISPLAYS

nnnnnn
ERA ACT = xx,EXP= yy
ERB ACT = xX,EXP= yy
PSR ACT = xX,EXP= yy

PER ACT = xX,EXP= yy
MTI ACT = xx,EXP= yy
XRA ACT = xX,EXP= yy
MDI= md,WR= dW,RD=dr

MACHINE FAILURES MAY
CAUSE CURRENT ERROR
DATA TO BE INVALID.
SEE DIAG 1 "VERIFY".
This screen is explained
on DIAG 6.

nnnnnn = Fai lure 10
xx = The actual contents
of the external
register
yy = The expected contents
of the external
register
md = Contents of the
maintenance data
in register
dw = Data wr i tten
dr = Data read

Routine EE 13

DIAG 55

Interrupt Level Test - Routine EE 13 (Continued)
ADDITIONAL ACTIONS

DESCRIPTION

FAILURE 10
HC3030

Extend bits for external register addressing were not
saved and set/reset correctly.

HC3031

The interrupts occurred in the wrong sequence.
current and/or previous values are wrong.

HC3032

The interval timer fa i led during interrupt handling.

HC3033

The interval timer fa i led during interrupt hand ling.

HC3034

The interval timer fa i led during interrupt handling.

HC3035

1.

Remove the IML diskette,
then press the IML switch to
cause a power-on-reset.

The PSR
Run routine EE13 again.
2.

If the value of ERA or ERB
is other than 0, see the FSI
section for error code El00.
Also see step 4 of this
Additional Actions column.

An XR error occurred while exercising the processor
external registers.

3.

If PSR bit 0 = I, see EAD 1
for error code Fnnn.

HC3036

Check 1 error occurred during the interrupt test.

4.

HC3037

Check 1 error occurred during the interrupt test.

HC3038

An XR error occurred while exercising the processor
external registers.

If a diagnostic failure
occurs and no errors are
detected by the hardware,
see the FSI section for
error code El00 and perform the procedures for
the microprocessor and
control storage.

5.

XR errors (PSR bit 0 = 1)
can cause ERA and ERB errors.
Use routine EE85 to check
the ERA and ERB registers.

3480 MI

FRUS
FRU121
FRU118
FRU117
FRU115
FRU114
FRU120
FRU119
FRU116
FRU134
FRU135
FRU157
FRU158
FRU159
FRU139

Routine EE 13 (Continued)

DIAG 60

Routine EE 13 (Continued)

DIAG 60

ERROR DISPLAYS
See the "Error Displays"
column on DIAG 55.

EC336395

C> Copyright IBM Corp. 1984, 1985

{)

{)

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3480 MI EC A57723
CJ Copyright IBM Corp. 1882,1888

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IBM Conftdentlal-13 May 89

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NOTES

NOTES

DIAG 66

()

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Processor External Register Test - Routine EE 14
Prerequisite diagnostics must run without failure before
this diagnostic is run. See DIAG 3, "PREREQUISITE
DIAGNOSTICS ...

This routine provides a check of the microprocessor external
registers function and error handling.
Routine Start Address: 4010
Error Loop: If no error occurs, the routine loops as if "LOOP
ROUTINE" is set. When an error is detected, the routine saves
the error information and displays the error on the MD. After
the error is displayed, the routine continues to loop on that error.
However, if a different error occurs, that new error is displayed
on the MD, and the routine will loop on the new error.

Error Displays
When an error is detected by the diagnostic program, the
maintenance device displays error information on its
keyboard/display. The first screen displays automatically. You
can see the second and following screens by pressing the
ENTER key on the keyboard/display.
The format of the display's first line is the same for all detected
errors. The remaining three lines contain additional information
about the failure.
External registers are defined in the OF (Data Fields) section of
this maintenance information.

FRUS
See CARR-CU or CARR-DR, pages 1-1, 1-2, 1-3, and 1-4 for
the names and locations of the FRUs.

3480 MI
.r Copyrlyflt IBM Corp

EC336395
1984

19H~

FAILURE ID

Routine EE 14
ADDITIONAL ACTIONS

DESCRIPTION

HC4021

Jump address high register fa i led.

HC4022

Force jump operation fa i led.

1.

Remove the IML diskette, then press the
IML switch to cause a power-on-reset.
Run routine EEi4 again.

HC4023

Jump address low register fa i led.

HC4024

Interval timer registers A and/or B fa i led.

HC4025

Interval timer A and/or B timings wrong.

HC4026

Processor control register (PCR) fa i led.

HC4027

Interrupt mask register ( IMR) fa i led.

HC4028

Processor diagnostic register (PDR) fa i led.

HC4029

Local storage page register (LSP) fa i led.

HC402A

ERA or ERB is incorrect, or the ERA or ERB
could not be reset, or the PSW error
indication is incorrect. See step 1 under
the Additional Actions column of this chart.

Hc402B

Level 1 interrupt problem.

2.

If the value of ERA or ERB is other
than 0, see the FSI section for error
code El00. Also see action number 4
of this Additional Actions column.

3.

If PSR bit 0 = 1 , see EAD 1 for error
code Fnnn.

4.

If a diagnostic fai lure occurs and no
errors are detected by the hardware,
see the FSI section for error code
El00 and perform the procedures for
the microprocessor and control
storage.

5.

XR errors (PSR bit o = 1) can cause
ERA and ERB errors. Use diagnostic
EE85 to check the ERA and ERB
registers.

FRUS
FRU121
FRU 118
FRU 117
FRU 115
FRU 114
FRU120
FRU 119
FRU 116
FRU134
FRU135
FRU157
FRU158
FRU159
FRU139

DIAG 65

ERROR DISPLAYS

nnnnnn
ERA ACT = xX,EXP= yy
ERB ACT = xX,EXP= yy
PSR ACT = xX,EXP= yy

PER ACT = xX,EXP= yy
MTI ACT = xX,EXP= yy
XRA ACT = xX,EXP= yy
MDI= md,WR= dw,RD=dr

MACHINE FAILURES MAY
CAUSE CURRENT ERROR
DATA TO BE INVALID.
SEE DIAG 1 "VERIFY".
This screen is explained
on DIAG 6.

nnnnnn = Failure ID
xx = The i!!Ictual contents
of the external
register
yy = The expected contents
of the external
register
md = Contents of the
maintenance data
in register
dw = Data written
dr = Data read

Routine EE 14

DIAG 65

Data Buffer Data Path Test - Routine EE32
Prerequisite diagnostics must run without failure before
this diagnostic is run. See DIAG 3, "PREREQUISITE
DIAGNOSTICS."
This routine contains three modules that test the data buffer
operation. The modules test the data paths into and out of the
buffer, the buffer CRC character generation, and the ability to
address all locations in the buffer.

Routine Start Address:

Routine EE32

DIAG 100

Routine EE32

DIAG 100

Data Buffer Check Character Test
This module tests the CRC character generation. A record is
written and the CRC character is stored. The same record is
then read and the calculated CRC character is compared with the
stored CRC character.

Data Buffer Memory Test

2010

Error Loop: If no error occurs, the routine loops as if "LOOP
ROUTINE" is set. When an error is detected, the routine saves
the error information and displays the error on the MD. After
the error is displayed, the routine continues to loop on that error.
However, if a different error occurs, that new error is displayed
on the MD, and the routine will loop on the new error.

Data Buffer Data Path Test
This module consists of four tests that check each of the four
data paths into the data buffer.
•

Test 1 uses the channel adapter write data path to write
data into the buffer and the drive read data path to read
data from the buffer.

•

Test 2 uses the drive write data path to write data into the
buffer and the channel adapter read data path to read data
from the buffer.

•

Test 3 writes 256 bytes of ripple data using the channel
adapter write data path and reads the data back using the
drive read data path.

•

Test 4 writes 256 bytes of ripple data using the drive write
data path and reads the data back using the channel adapter
read data path.

This module tests the addressability of the data buffer by writing
into and reading out of every buffer location. It also tests the
segment looping function of the data buffer.

Error Displays
When an error is detected by the diagnostic program, the
maintenance device displays error information on its
keyboard/display. The first screen displays automatically. You
can see the second and following screens by pressing the
ENTER key on the keyboard/display.
The format of the display's first line is the same for all detected
errors. The remaining three lines contain additional information
about the failure.
External registers are defined in the OF (Data Fields) section of
this maintenance information.

FRUS
See CARR-CU or CARR-DR, pages 1-1,1-2,1-3, and 1-4 for
the names and locations of the FRUs.

A 256 byte data pattern of each hexadecimal character from
hexadecimal 00 to hexadecimal FF is written into one data
buffer data path and read through another data path. The
expected data (written) is then compared to the actual data
(read).

3480 MI

EC336395

~ CopYright IBM Corp. 1984. 1985

:)

II

\

)

Data

suI

o

Data Path TeSPR-OUtine'EE32 (PontinUed)

o

o

o

o

Routine EE3RontinUed)

102

Routine EE32 (Continued)

DIAG 102

Data Buffer Data Path Test
'FOLLOW STEPS I AND 2 REFORE TAKING OTltER AClJOIIS:

BUZ9Z1

AOUIT I OffAL ACIIOlIS

FllltS

l. If ERA or ERR is not ee go 1.11 1$1 lor err code flBO
2. If PSR bit e - I, see fAO 1 for error cude Fnnn.
See the rSI secti on fur error codr 1l5nn.

FRU114
FRU128
*FRU1l2
*FRU1l3

OE SCR I PTl ON

rAILURE 10

A buffer channel status error occurred during a
write operation through the channel wri te data
path.

cod~

See the FSI section for error

A buffer device status error occurred on the last
pass during a read operation through the drive
read data path.

See the FSI section for error code

BU2924

Data read froll the buffer did not equal the data
written into the buffer.

If any errors are set, ignore the data cOllpare error and
troubleshoot the errors set by the hardw<'lre.
See the FSI section for error code USnn.

RU2BZ5

The BOSE status ~It a (device pointer stop) was
not active after a read operation through the
drive read data path.

See the rSI section for error code 1J6nn.

Channel - pointer· Stop was not on after an
MP read.

See the FSI section for error code nSlln.

RU2927

A buffer devi ce status error occurred during a
write operation through the drive write data
path.

See the FSI section for error code 1J611n.

8U2928

A buffer channel status error occurred during a
write opera t i on through the channel wri te da ta
path.

See the FSI section fur error code OSnn.

A buffer channel status error occurred on the
last pass during a read operation through the
channel read data path.

See the F51 section for error

Data read from the buffer did not equal the data
written into the buffer.

If any errors are set, ignore the data compare error and
troubleshoot the errors set by thc hardw~re.
See the FSI secti on lor error code IlSnn.

DU2e23

RU2926

RU2929

RU282A

nU202B

'Service in' did not become active or 'data in'
is active lin a channel Olleration.

NOTE: Vou will see the following error displays
only if the Oata COI.paction Feature is installed.

ERD=rb
PER-pp. XI!A=aa
MlJ-_, MOl =md
PSR~x)C,

U6nn.
O~nn.

nnnnnn Failure 10

...
ra
rb
xx
pp
aa

l1li

md

•
a

cod~

b
c
d
e
f

IlSnn.

See the rSI sectinn for c,·,·or r.od(! 1i5nn.

'Oata in' did not become active or 'serv;ce in'
is active on a channel operation.

RU2920

Channel 1 stop bit was not
channel operation.

nU?A2E

'Microprocessor write coml,lete' did 110t become
lIct he on a dianne 1 write opera t i on.

RU2n2F

~ctiye

after a

Outler chaMel status error occurred rlilri ng a
channel wri te operation.

No errors were set
Contents of error register A
Contents of error' register B
Contents of the processor status register
Contents of the processor error register
Contents of the extcrnal address register
Contents of the IInter. s of toe CeMP Diagnostic 0 Register

Conten s of the CCMP Diagnostic I Register
Cor ten s of the CeMP Feature Level He:;ister

i See the FSI

:I

..

!aeSE-abcde
i BDSE=fghij

! BwRP=cc

of ERA reg
- Contents
Contents of ERB reg

ra
rb =
p~ =
xx

-

section for error code DSnn.

I

II

I

: r:nnnnn
I

Bi ts 0-3 of PER reg
Contents of PSR ~eg

I

lEX?
:.\.:r

BeSE
klmno
abcde

BOSE
pqrst
fghi j

I

I

I

DA7A EXP/,.;;'7= aaaa
(DATA READ
• bbbb
; 9UF:~R ADR = ecce

I

I

II
I
I

II

-

I

i

,

!

i

I

C:MP Status Regi ster
CC"'IP Mode Register

Contents of XRA reg
aa
md
Contents of ~DI ~eg
11ITI= Contents of MTI reg

i

I

the
the
the
the

.

.

CTXE
EE
BB, CMOO = FF
CC, CMOI
GG
DO, CMFL = HH

!

I

Tne expected ccntert is 07.

of
of
of
of

. AA,

CMS
C1+I •
CHM
CTEO:.:

rmnnr.n
Fail ure 10
IERA=ra.ERB::Irb
: ".., = no e!"'l"'or set
! PSR=xx, P~R=pp. XRA=aa:
!MT:=I1ITI. MD[=md

I content is 0009.

I

s
s
s
s

: nnnnnn

The buffer devi ce remainder reg is ter does not
I • 05 after the last read of six bytes.

I

en
en
en
en

I

I,

I The BCSS content doe net·

or.'y if the

See the FSI section for error code D6nn.

BU4047

BU4049

Con
Cor.
Con
Con

AA

I

BU4046

d~sp1ay

4.5 Mt/s buffer adapter card is ins:a 1 1ed.

~--------~------------------------------------,-----------------------------------------~*FRUI12

I

see this error

!

= Faiiun~ ID
No errors we~e set
Buffer ::hannel status and error reg;ster

i

! nnnnnn

f

I

II

!

!~ATA EXP/wR7= aaaa !

iDAiA

READ
= Obt:b '
: 6!.iFF!K ADR = ccc: 1
: RE~ = gg, EX? = hh

i

DATA EXP/IIRT= aaaa
GAiA READ
= bbbo

I
I

,BUFfER AOR • ecce I
••
EXP - ff I

I B:SS

D

I

..,::

a

b
, c
cc
I d
! e

i

E

b; ts 0-3
= BeSE channel error group a
= seSE cnanne1 error group 1
= Conte"ts of t~e buffer wrap ref;; ster
• BCSE cr.a"~e 1 error group 2
= SeSE cnarnel e""or group 3
Buffer ~e'y1ce sta!.l.Os and error reg~ster
bi tS 0-3

I

Ii

I

aaaa
Expected 'Wri te da!a bbbb = Da-=.a t~at was read
cc!:c = Buffer address of t~e data in e"ror
ee = Conte:'lts of trte buf;er channe1 intermediate
storage aodress reg~ste!"
ff = EX;l!·:tec conte~ts of the buf'fel'" channel i ntermediate storage address regis~er

I hh

R.ema i nder reg; s ter expec ted count

I

re;~ster

a
1
2
3
s-:.atus and e"'!"'or

bits 0-3

• Expected SeSE channel error g-oup 0
m • Expected BeSE channel error group!

!nnnnnn

I
I,

i

BCP

i EX? kkl1

'ACT; ijj

I:~ . A~tual

nnnnnn

BuP
oCPP
mmnn

buffer channel pointer high
Actual bLlffer channei pointer low
ikk = Expected ~uffer channel pointer high value
11 • Expected Duffer channel poi nter low va I ue
lI""nn a Act~al buffer device pointer contents
loopp = Expected buffer device pointer contents
,JJ

g
BOSE device e"ror group
h = BOSE dev'ce error group
BOSE dev' ce er"or group
j • BOSE device er"or group
k :: Expected buffer cha:"'i~el

n • Expected
o = Expected
P
Expected
Q • Expectec

SeSE channel error group 2
BeSE Channel error group 3
buffer device status and f!"'ror
BOSE device error group 0
r = Expec!ed BDSE device err~r grOU;l 1
s
Expected BDSE device error group 2
t • Expected B~SC: dev i ce error group 3
E

a

i

• These FRUs are EC sensitive. FRU112 may not be present. See CARR-CU 7.

3480 MI EC A57721
(' copyrognt IBM Corp. 1982. 1988

()

{)

{)

()

f)

\..

{)

o

Data Bar Controls TesPRoutine EE33 (AntinUed)

o

o

o

o

o

Routine E .(Continued)

Separation Test
Nota: See the error displays on DIAG 112.

DESCRIPTION

FAILURE ID

FOLLOW STEPS 1 AND 2 8EFORE TAKING OTItER ACTIONS:

ADDITIONAL ACTIONS

FRUS

1. If ERA or ER8 Is not 88 go to FSI for err code E188

FRU114
FRU128
*FRU112
*FRU113

2. If PSR bit 8 • 1. see EAD 1 for error code Fnnn.

8U4843

'Service In' or 'data In' did not beCOMe active
In 783 _I croseconds.

See the FSI section for error code DSnn.

8114844

The channe I read .ore than 128 bytes. whl ch I ndicates the channel Is overrunning the drive.

See the FSI section for error code OSnn.

8114845

An XR error or check 1 was detected.

See steps 1 and 2 at the top of this chart.

8114846

The content of the 8DSE does not • the expected
content. The expected content Is 78888. The
content of the 8CSR does not • the expected
content. The expected content is 98888.

See the FSI secti on for error code D6nn.

8114847

The buffer device re.alnder register does not
• 85 after the last read of six bytes.

See the FSI section for error code D6nn.

8114848

The buffer device pointer expected content is
8888. The buffer channel pointer expected
content is 8999.

See the FSI section for error code D6nn.

8114849

The BCSS content doe not· the expected content.
The expected content Is 87.

See the FSI section for error code DSnn.

* These FRUs are EC sensitive. FRU112 may not be present See CARR-CU 7.

3480 MI EC A57723
CI Copyright IBM Corp. 1982, 1999

¥

ADDITIONAL ACTIONS

FRUS

FOLLOW STEPS 1 AND 2 BEFORE TAKING OTHER ACTIONS:

1. If ERA or ERB Is not 88 go to FSI for err code E188
2. If PSR bit 8 • 1. see EAD 1 for error code Fnnn.

BU484A

A channel control reset falled during an external
register reset test.

See steps 1 and 2 at the top of this chart.

FRU114
FRU129
*FRU112
*FRU113

BU484B

A check 4 reset failed during an external
register reset test.

See steps 1 and 2 at the top of this chart.

BU484C

A check 5 reset failed during an external
register reset test.

See steps 1 and 2 at the top of this chart.

BU494D

A hardware reset falled during an external
register reset test

See steps 1 and 2 at the top of this chart.

8U484E

A buffer register that can be reset by a POR
reset only is found In a reset state and no
POR reset was Issued.

See steps 1 and 2 at the top of this chart.

IU484F

The 388NS clock ring error Indicator (CTEO Reg
bit 2) Is not turned on when forced.

See steps 1 and 2 at the top of this chart.

BU48S9

The any error bit Indicator (eMS Reg Bit 7)
is not turned on by one of the other errors.

See steps 1 and 2 at the top of this chart •

BU48S1

The feature level parity error indicator (CTEO
Reg bit 6) is not turned on when forced.

See steps 1 and 2 at the top of this chart

BU48S2

The channel overrun error I ndi ca tor (CTEO Reg
Bit 9) is not working correctly.

See steps 1 and 2 at the top of this chart

BU48S3

The transferr co_plete/overrun error indicator
(eMS Reg Bit 3) is not working correctly.

See steps 1 and 2 at the top of this chart

1114854

The check 5 reset does not work correctly during
a channel operation.

See steps 1 and 2 at the top of this chart

BU4855

Service in or data in Is not working correctly
during a channel operation.

See steps 1 and 2 at the top of this chart

BU4856

The be toggle error indicator (CTEO Reg Bit 4)
Is not on when forced.

See steps 1 and 2 at the top of this chart

IU4857

Either the C3PO data parity error or the Be
channel parity error Indicators (Co.p Error 1
Reg Bits 8 or 3) are not on when forced.

See steps 1 and 2 at the top of thl s chart

1114958

Either the BC data parity error or the channel
data ~arity error indicators (CTEO Reg Bits 3
and 5 are not on when forced.

See steps 1 and 2 at the top of this chart

FAILURE ID

DESCR IPTI ON

ERROR DISPLAY
See error
display on
DIAG 112

IBM Conftdentlal-13 May 89

Routine EE33 (Continued)

ERROR DISPLAY
See error
display on
DIAS 112

DIAG 120

o

o

o

{)

{}

()

i)

()

o

o

o

o

o

o

o

o

o

o

Data Buffer Controls Test - Routine EE33 (Continued)

o

o

Routine EE33 (Continued)

DIAG 122

Routine EE33 (Continued)

DIAG 122

Buffer Adapter Tests

I

OESCRIPT!ON

FAI LURE 10

FRUS

ADDITIONAL ACTIONS

! :CLeOi. S7EPS I AND 2 BEFORE TAKING OTHER ACTIONS:

1. If E;;A or ERB is not 00 go to FSI for e"r code E100
2. If PSR bi t 0 = I, see EAD I for error code Fnnn.

ERROR DISPLAYS

II FRUl14

Note: Vou will see this er~or display only if the
4.5 Mb/s buffer adapter ca"d is installed.

F~U120

~--------~-------------------------------------TI------------------------------------------41*FRUII2

BU404A

A Channel control reset failed Curing an external! See steos 1 and 2 at the top of thi s chart.

reset test.

reg~s~er

SU4046

A c.oeck 4 re$et failed during an exte"nal

reg; ster reset test.
I
I

I

BU404C

cheCk 5 "eset fa i 1ed duri ng an ex:erna 1
register reset test.
A.

I
I See
I

steps

and 2 at the top of tni s chart.

I See steps

1 and 2 at the top of th i s cca rt.

'*FRU1l3

CMS - AA, CTXE - EE
Cr-t1 = B6, CMOO • FF
CHM - CC, CMOl
GG
CTEO= DD, CMFL = HH

I
'!I

II~------~--------------------------------------~--------------------------------------------~
BU404D
A haraware "eset failed during an external
I See steps I and 2 at the top of this chart.

AA

Contents
Contents
Contents
Contents

BB
CC
DO

of
of
of
of

the
the
the
the

CCMP Status Reg; ster
CCMP Mode Reg; ster
Channel Mode Regi ster
C2PQ Ecror 0 Regi ster

EE
FF
GG

HH

Contents
Contents
Contents
Contents

of
of
of
of

the
the
the
the

C2PO
CCMP
CCMP
CCMP

XR Error Register
Diagnostic 0 Register
Diagnostic 1 Register
Feature Level Register

'II

I
II
I

reg; ster reset test
BU404E

BU404F
BU4050
BU4051
BU4052

.

A buffer re. i ster that can be reset by a POR
reset or.1y is found in a reset state and no
POR reset was issued.

I' See steps

and 2 at the top of thi s Chart.

See steps 1 and 2 at the top of th; s chart.

The any e"rQr bit inaicator (CMS Reg Bit 7)
is nOt tu!'"~eo on by one of the other errors.

See steos

fea~ure

level ;iari:y err-or indicator (CTEO
5) is not turned on when forced.

Reg

b~!

The

cha~1ne~ cve!'"run error incieator (CTEO Reg
0) is nct working correet1y.

B~+:'

i

I

t~p

SU4054

The c!"!e~~ 5 reset oces
e ::-,anne 1 cpera: ; on.

See steps 1 and 2 at tne top of thi s enar!

!8DGl

BU4055

Service ~n or da~a in is not working correctly
during a channel coera~io".

See steps

and 2 at the top of thi s chart

BU4056

The bC

!o~gle err'J!" indicator (CTEO Reg Bit 4)
; s net or wnen forced.

See steps

and 2 at t!'1e top of thi s chart

'BuF~::r:

cc

,
BC?

BU4058

See steos

Either :~e Be data parity er-""cr or ~he channel
data parity e!"'ror indicators (CTEO Reg Bit~ 3
and 5) are not on wnen forced.

See steps

ERA
ERB
PER
PSR

I

reg
reg

reg
reg

::\:::c

ADR

= c:

! !1nnnrln

::~. :ne!" the :3?O dat5 pa""~ ty e,:,,!"'cr or- the Be
:hanl1el ;Jar~ ty error incicators (Comp Error
Reg 8~:s 0 or 3) a:"'! not on when forced.

of
of
of
of

Exoe::tec wr~ e data bbb = :ata !hat was read
Su"fer addr~ s of the da a in err:)r
Contents of ne Sl)Gl reg s~er

aaaa

8U4057

Contents
Contents
Bi ts 0-3
Conte,ts

and 2 at tr.e top of thi s chart
:DA7'; EXP/wR-;'= aaaa
! CA ~ A READ
:,bob

work correctly during

ra
rb
op'
xx •

EXP.'wRT= aaaa
: OA.TA READ
cbbb
i 8UFF~R ADR
ecce

See steps 1 and 2 at the top of thi s chart

rHJt

iBDSE=fghij

IBWRP'cc

iCA7A

of thi s cha"t

The t"~r.sferr compl ete/overrun e!""!"or indicat.or
(eMS Reg Bit 3) is not wo,.i(~ng cor"ect1y.

. BU4053

!BCSE-abcde

I

aa • Contents of XRA reg
md = Contents of MOl reg
"'" • Contents of MTJ reg

and 2 at tne top of th; s chart.

See steps I and 2 at the
See steps

t

I

Innnnnn
nnnnnn • Fa; 1ure 10
! ERA=ra, E::(8=rb
: ** z no error set
PS~=xx, PER=po ,XRA=aa:
IMTI=mm,MDI=mc

I·

The 300NS clock ring error indicator (CTEO Reg
b" 2) j S ~ct turned on when forced.

\ The

!

and 2

a~

tne top of this

c~art

~EXF ki<:il
t; j j

! ACT

and 2 at the top of thi s chart

nnnnnn

Fa~)ure

TD

oJ?
CCi'P
mm~"

Ac:ual bu~fer criannei pointer h~gh
Actual buffer c~armel pointer" low
Expected :uffer cr,anoel pcin~er high value
:xpected buffer channel pointer low val ue
rrrnnn = Actual bl..iffer device pointer contents
oopp = Expected buf'er device pointer contents

!nnnnnn

I BeSE
IEXP klmno
jACT abc::e

BOSE
pqrst
fghij

nnnnnn = Fail ure ID
* = No errors we~e se~
a = Buffer channel s~attJs and error reg; ster
bits 0-3
BCSE channel error group 0
c = SCSE channel error group I
c: = Contents of t~e buffer wrap reg; ster
c SCSE channel error group 2
~CSE channel error group 3
f = Buffer device s~atus and errOr register
bits 0-3
9
BOSE devi ce error grJUp 0
h SeSE devi ce error group 1
i : BeSE device error group 2
80SE dev i ce error group 3
k = £x;Jec~ed buffer charlnel status and e~ror
register bits 0-3
Expected BCSe: enannel e~ror group 0
, m = Expected BeSE channel error group 1
n Expected SeSE c!'",annel error group 2
o Expected BCSE c~anne i error group 3
p ~ Expected buffer device s~atus and !rror
q
Expected BDSE devi ce error group 0
r = Expected BOSE device error group 1
Expected BOSE device er"or group 2
Expected BOSE device error group 3

• These FRUs are EC sensitive. FRU112 may not be present. See CARR-CU 7

3480 MI EC A57721

Data Buffer Controls Test - Routine EE33 (Continued)

Routine EE33 (Continued)

DIAG 124

Routine EE33 (Continued)

DIAG 124

Buffer Adapter Tests

FOLLOW

S~EPS

FRUS

ADDliIONAL ACTIONS

OESCR! PTION

FAI LURE 10

1 AND 2 BEFORE TAKING OTHER ACTIONS:

1. If ERA or .ERB is not 00 go to rSI for err code 000
2. If PSR bit 0 = 1. see EAD I for error code Fnnn.

ERROR

I "RU:14

D!SPLA~S

Note: You wiil set! this error disolay onlY if the
4.5 Mbis buffer aaacter card is insta1 ~ed.

i FRU120
I

L-________~--------------------------------------_,--------------------------------------------_:·FRUl12

I"FRUI13

BU4059

Reserved

BU4C5A

The write data parity error indicator
(CTXE Bi t 1) is not on when forced.

See steps 1 and 2 at the top of thi s chart.

BU405B

Eitner the read data parity error or the xr output parity error indicators (CTXE Bits 2 & 3)
are not on when forced.

See steps 1 and 2 at the top of thi s chart.

• M, CTXE • EE
cBS, CMOO = FF
CHM = CC, CMDl • GG
CTEO- DO, CMFL • HH

C~S

~--------~--------------------------------------~---------------------------------------------i'

e1+!

AA

Contents
Contents
Contents
Contents

SS

c:

DO

of
of
of
of

the
the
the
the

C:MP Status Reg'i ster
CCMP Mode Regi ster
Channe 1 ~ode Reg is ter
CZPO Error 0 Regi ste r

!

nnnnnn

PS,=xx, DeR·PP. XRA=aa'
MTl=m.,MDI=md

I

.

cf XRA reg
of MOl reg
= Conte!'lts of MTl reg

aa =

C~nte!'!ts

Ccnte~ts

rm1

:~ATA
,DAT~,

GG
HH

nnnnnn = Fa ~ 1ure I D
= no error set

..

ra
Contents
ro
Contents
pp = 8i :s 0-3
xx
Conteots

of
of
of
of

Oi,:=

aaaa
c::o
cj

.
SCSE
,EXP klmno
)C abcde
nnnnnn :

r:nrnr,n
BCP
E~? kk ~ 1
, A~T i ;jj

j

Fa~~ure

BOSE
pqrst
fghij

:D

e!"'''"crs we!"! set
Buffe!" :narmel s:atus and error register
~c

b
BCSE char.ne 1 eeror ~r~up 0
C = BCSE ,"annel eccor group 1
cc ::. Contents of tne buffer wrap
BeSe: c~ar'lnel en'or g!"oup 2

eccc

tlOtl!::

= Data

t!'"lat was read

~r. e~ror

Buffer adc,:",ess of tt"!e :1a:3
Cont~!'lts

B~RP=cc

: nnnnnn

aaaa

:'x:Jec:'e~ wr~:e da~a

BcSE=f~hi

I

PSR reg

bDob

3UFoER ADR
SDGI = dd

I

PER reg

EX?'"",= aaaa
READ
~b~D
ecce

DAH EXP
04:- A i\E:.';D

CCMP Feature Level Reg; ster

ERA reg
ERS reg

a =

I

C2PO XR Error Regi ste
CCMP Diagnostic 0 Reg ster
CCMP Diagnostic 1 Reg ster

'SCSE =aocde

i ••

ERA=ca,ERS=c~

m~

Contents of the
Contents of the
Content 5 of the
Contents of the

EE
FF

of the BDG: reg's':.e':'"

Failure:O

nnnnnn
6:JP
ccpp

mmr.n

ii

Act .. al buffer channel pointer high
Actual buffe~ cnannel pointer ~ow
kk
Expec~ed buffer channel pointer high va'ue
11
EX;Jected buffer channel pointer low value
ImInn :; Ac~ual buffer device point.e ~Gntents
00:;;1 .a tltoected buf~er device :lo;nter c.:m!en:'s
jj

r

reg~s!.er

e ::. 3CSE channel e!"'!"'or group 3
f
Buffer- device s~atL:S and e:"ror regis~er
~; ts 0-3
9 ;: BDSE ::Jev ; ce erro~ group 0
h
B:)SE device error group 1
i = BOSE cevice er:"or group 2
j
SeSE device error group 3
k
Expected buffer :,anne1 sta~us and error
reg~s~er bits 0-3
Expec~ed seSE ehanne i er~or group 0
m = expected SCSE channel error group I
Expec~ed SCSE Channe 1 ecror grouc 2
n
expec:ed SCSE c"anne 1 error group 3
0
p
Expected buffer device status and error
q
Expec:ed SDSE devi ce error group 0
r = Expec:ed SeSE dev; ce error group 1
Expected BOSE device ereor group 2
• Expee:ed 60SE device ecror group 3

• These FRUs are EC sensitive, FRU112 may not be' present. See CARR-CU 7

3480 MI EC A57721
r. COPY"DhlIBM Corp, 19112, 1988

{)

fl

()

{)

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Data BU. Controls Test Ooutine EE33 (C8inUed)

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Note: See the error displays on DIAG 112.

FAILURE JD

DESCRIPTION

ADDITIONAL ACTIN:S

rRUS

FOLLOW STEPS 1 AND 2 BEFORE TAKING OTHER ACT J ONS:

1- If ER4 or ERB is not ~a 9" tn rSI for
error code E18e
2. If PSR bit 8 • 1. see lAD I r fir error corle
code Fnnn.

BU49S9

The comp xr error (CTXE Bi t B) is not on when
forced.

See steps 1 and 2 at

hi s

eh~rt.

BU49SA

The write data parity error indicator (CTXE
Bit 1) is not on when forced.

See steps 1 and 2 at the top of this

ch~rt.

BU49SB

Either the read data parity error or the xr
output parity error indicators (CTXE Bits 2 l 3)
are not on when forced.

See steps 1 and 2 at the top of this chart.

BU495C

CHS Register bit 9 (Co.p busy) cannot be reset.

See FSJ section for error code DAn".

BU495D

An errol' was detected in the data in or service
in tag lines during a read or write operation in
Improved Data Recording Capability .ode.

See rSI section for error code OAnn.

BU495E

An ending sequence error was detected during a
channel write or a channel read operation.

See FSI secti on for error code OSnn.

BU4BSF

The actual channel byte count does not equal the
expected channel byte count.

See rSI section for error code JlSnn.

BU4868

The channel byte count registers In each .odule
do not co.pare.

See FSJ sretlon for error code [JAnn.

BU4961

The I.proved Data Recording Capability record
trallor does not equal the calculated value.

See FSI section for error code DAnn.

BU4B62

The da ta read does not equal the da ta writ ten In
Improved Data Recording Capability mode.

See FSI section for error code 06nn.

BU4963

An error was detected in the service in or data
in tag lines.

See FSI secti on for error code DAnn.

BU4964

A data co.pare error was detected in the RAM
diagnostic tests.

See FSI section for error code DAnn.

BU4965

The any error bit (CMS bit 7) was on after
running the RAM diagnostic tests.

See FSI section for error code DAnn.

BU4966

Cannot force the encode does not equal decode
error (Co.p Error G bit 7).

See rSI sect I on for error code DAnn.

BU4667

Cannot force the initialization error (Co.p
error G bit 6).

See FSI section for error code OAnn.

BU4968

The any error bi t (CHS 81 t 7) was not turned on
by another Improved Oata Recording Capability
error.

See FSI section for error code DAnn.

BU4669

Cannot force the channel adapter Interface
overflow error (Comp error 1 bit 7).

See FSI section for error r.ode DAnn.

BU496A

Cannot force the channel byte count overflow
error (Comp error 1 bit 6).

See FSI section for error code OAnn.

BU496B

Cannot force a ca or be .aster transfer error
(Comp error 1 bits 1 or 4).

See FSI section for error code DAnn.

B1I406C

Cannot force a ere error (Cu.p error 8 bits 1
through 5).

See rSI section for error code OAnn.

BU486D

A check 5 reset did not work properly during a
channel operation.

See FSI section for error .. ode DAnn.

th~

tOil of

t

rlWl14

FRUIZ6
*FRU1l2
*FRUIl3

ERROR 01 srlH
Sec ~rror
display on
DIAG 112

-

~:-

3480 MI EC A57723
o Copyrl,h1IBM Corp ..1982.1881

IBM Confidentia'-18 May 89
..

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Routine EE33 !ntinUed)

olAf 124

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Routine EE42

Control Unit to Drive Bus Out Driver Wrap Test - Routine EE42
Prerequisite diagnostics must run without failure before
this diagnostic is run. See DIAG 3, "PREREQUISITE
DIAGNOSTICS ...
This routine tests the control unit/drive interconnection as
follows:
1.

2.

3.

Activates 'select out' to degate all 'bus in' lines from the
drives attached to the control unit and tests the 'bus in'
lines to make sure that none are active, If any 'bus in' lines
are active, the routine issues a clamp command to each
drive, one at a time, to isolate the drive with the active 'bus
in'lines.

Routine Start Address:

See CARR-CU or CARR-DR, pages 1-1, 1-2, 1-3, and 1-4 for
the names and locations of the FRUs.

FAILURE 10

DESCRIPTION

012021

When 'select out' was presented to the
drive, bits were sti 11 active on the device
data bus 'bus in'
A clamp command was
sent to all drives, but the active bit
condition was not removed from the bus.

ADDITIONAL ACTIONS
See the FSI

section for error code 8005.

See EAD I, "Drive Interconnections."

FRUS

ERROR DISPLAYS

FRU085 1
FRU199
FRU248
FRU 118

012021
BUS IN = vv INTF x
SEL OUT ACTIVE AND
ALL DRIVES 'CLAMPED'

vv
x

012022

The active device data bus 'bus in' bits
were removed from the bus following a clamp
command to the drive that was causing the
active bits.

See the FSI

section for error code 8005.

See EAD I, "Drive Interconnections."

FRu085 1
FRU199
FRU248
FRU 118

012022
(DR a) ON INTF x
HAS BUS IN BITS vv
ACTIVE WITH SEL OUT

a
x

vv
012023

Addressing: If a drive address is entered, only that drive is
tested. If no drive address is entered, the routine tests all drives
in the subsystem. The following screen is used to enter a drive
address.

During the "electronic wrap" of the control
unit/drive BI-DI bus, the data returned to
the device interrupt register (DIR) did not
equal the data sent to the device control
bus (DCB) register.

See the FSI section for error code 800A.
See EAD 1, "Drive Interconnections."

FRU085 1
FRU 118
FRU134
FRU115

x

yy
DI2024

A parity error was detected in the device
status/error (DSE) register.

See the FSI

section for error code 8Bnn.

See EAD I, "Drive Interconnections."

FRU085 1
FRU118
FRU 116
FRU134

x

vv

Error Displays
When an error is detected by the diagnostic program, the
maintenance device displays error information on its
keyboard/display. The first screen displays automatically. You
can see the second and following screens by pressing the
ENTER key on the keyboard/display.
External registers are defined in the OF (Data Fields) section of
this maintenance information.

3480 MI

EC336395

yy
DI2025

Whi Ie trying to determine if the subsystem
is configured with a dual or single control
unit, a status store time-out occurred.

1 This FRU is EC sensitive.

See the FSI section for error code 5360.

FRU121
FRU122
FRU133
FRU152
FRU195
FRU196
FRU134

address
drives 0 through 7,
drives 8 through F
of 'bus in' active bits

L for
H for
Value
Value

drives 0 through 7,
drives 8 through F
of 'bus out' bits
of 'bus in' bits

012024
PARITY ERROR OCCURRED
ON INTF x DATA = vv
'OSE' REG = yy

Valid Parameters:
Drive address (O-F, or OO-OFl.
Enter FF to run all drives.

Drive
L for
H for
Value

012023
BUS IN DID NOT EQUAL
BUS OUT ON INTF x
BUS 0 =vv BUS I =yyy

vv
DIAG=(EE42)-ENTER:
DRIVE
(xx)

@Copyr,ght IBM Corp. 19B4. 19B5

Value of 'bus in' active bits
L for drives 0 through 7,
H for drives 8 through F

2010

Error Loop: If no error occurs, the routine loops as if "LOOP
ROUTINE" is set. When an error is detected, the routine saves
the error information and displays the error on the MD. After
the error is displayed, the routine continues to loop on that error.
However, if a different error occurs, that new error is displayed
on the MD, and the routine will loop on the new error.

xx

DIAG 150

FRUS

Tests the tag-in lines to make sure that none are active. If
any tag-in lines are active, the routine issues a clamp
command to each drive, one at a time, to isolate the drive
with the active tag-in lines.
Ripples 'bus out' through all possible bit patterns. The data
is then read through the control unit device interrupt register
and compared.

o

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L for
H for
Value
Value

drives 0 through 7,
drives 8 through F
of 'bus out'/'bus in'
in the DSE register

012025
TIMEOUT OCCURRED
WHILE TRYING TO READ
STATUS STORE

See CARR-DR 4.

Routine EE42

DIAG 150

Control Unit to Drive Bus Out Driver Wrap Test - Routine EE42 (Continued)
FAILURE 10

DESCRIPTION

012026

Active tag lines were found after sett i ng
the device tag register (OTR) to zero. A
clamp command was sent to all drives on the
serial interconnection, but the active bit
condition was not cleared from the OTR
register.

ADDITIONAL ACTiONS
See the FSI section for error code 800A.
See EAO I, "0 rive Interconnections. "

FRUS
FRU085 1
FRU118
FRU134
FRU 115

,

,

See the FSI section for error code 7502.
See EAD 1,"Drive Interconnections. "

FRU085 1
FRU 118

a

The active 'address in' tag was removed
from the device data bus fol lowing a
clamp command to the drive.

See the FSI section for error code 8009.
See EAD I, "Drive Interconnections."

FRU085 1
FRU199
FRU248
FRU 118

a

The active 'status in' tag was removed from
the device data bus fol lowing a
clamp command to the drive.

See the FSI section for error code 8c07.
See EAD 1, "Drive Interconnections."

FRU085 1
FRU 118
FRU 116
FRU134

a

The active 'clock B in' tag was removed
from the device data bus following a
clamp command to the drive.

See the FSI section for error code 840C.
See EAD I, "Drive Interconnections."

FRU085 1
FRU 118
FRU199
FRU248

a

3480 MI

DIAG 152

L for drives 0 through 7,
H for drives 8 through F
Drive address
DI202A
(DR a) ON INTF x
CLOCKB IN TAG IS
ACTIVE

x

1 This FRU is EC sensitive.

L for drives 0 through 7,
H for drives 8 through F
Drive address
DI2029
(DR a) ON INTF x
STATUS IN TAG IS
ACT I VE

x

DI202A

L for drives 0 through 7,
H for drives 8 through F
Drive address
DI2028
(DR a) ON INTF x
ADDRESS IN TAG IS
ACT I VE

x

DI2029

Value of bits in the device
tag register
L for drives 0 through 7,
H for drives 8 through F
012027
(DR a) ON I NTF x
GAP IN TAG IS
ACTIVE

x

DI2028

Routine EE42 (Continued)

DI2026
DTR = vv
INTF =x
WITH ALL DRIVES
'CLAMPED'

x

The active gap in bit was removed from
the device data bus following a clamp
command to the drive.

DIAG 152

ERROR DISPLAYS

vv

012027

Routine EE42 (Continued)

L for drives 0 through 7,

H for drives 8 through F
Drive address

See CARR-DR 4.

EC336395

'" CopYright IBM Corp. , 9B4. '985

.~

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Control
Unit
to- Drive- Bus and Tao Test - Routine EE43
- - - _. -

-

-

-

-

--

-

This routine checks all tags to and from the drives during initial
selection to ensure correct response.
Following selection, 17 bytes of data are transferred to the drive
display with the message ' ........ • .... "'. (This test does not
remove the message on the drive display.) The routine then
de-selects the drive and checks all tags to and from the drive
during an ending sequence to ensure correct response.
All bits on the BI-OI and tag buses, except device tag register
(OTR) bit 4 ('gap in', 'gap out') are tested.

Routine Start Address:

Routine EE43

~

Prerequisite diagnostics must run without failure before
this diagnostic is run. See DIAG 3, "PREREQUISITE
DIAGNOSTICS. "

DIAG 160

Error Displays
When an error is detected by the diagnostic program, the
maintenance device displays error information on its
keyboard/display. The first screen displays automatically. You
can see the second and following screens by pressing the
ENTER key on the keyboard/display.
External registers are defined in the OF (Data Fields) section of
this maintenance information.

FRUS
See CARR-CU or CARR-DR, pages 1-1, 1-2, 1-3, and 1-4 for
the names and locations of the FRUs.

3010

Error Loop: If no error occurs, the routine loops as if "'LOOP
ROUTINE" is set. When an error is detected, the routine saves
the error information and displays the error on the MD. After
the error is displayed, the routine continues to loop on that error.
However, if a different error occurs, that new error is displayed
on the MO, and the routine will loop on the new error.
Addressing: If a drive address is entered, only that drive is
tested. If no drive address is entered, the routine tests all drives
in the subsystem. The following screen is used to enter a drive
address.

FAILURE ID
DI3021

DESCRIPTION

ADDITIONAL ACTIONS

,

The, drive did not return an address
in response to the control unit,
after
the control unit sent an
,
address out' tag along with the
drive address on the device data
bus 'bus out'.

See the FSI section for error code 8007.
See EAD 1, "Drive Interconnections. "

FRUS

ERROR DISPLAYS

FRU08s 1
FRUOS9
FRU049
FRUl08
FRU107
FRU10S

DI3021
(DR a) ADDRESS IN
WAS NOT RETURNED
DURING SELECTION
a

DI3022

DIAG=(EE43)-ENTER:
DRIVE
(xx)

,

The one s complement address sent from
the drive
, on the device data bus
'bus in on did not match the expected
address.
The expected address was
generated from the address sent to the
drive on the device data bus 'bus out'.

See the FSI section for error code 800c.
See EAD 1, "Drive Interconnections. "

FRU08S 1
FRU 118

Valid Parameters:

xx

Drive address (O-F, or ~O-OF).
Enter FF to run all drives.

Diagnostic Aid

DI3023

,

,

The device data bus address in from
the drive did not drop when the
control unit dropped device data
bus 'address out.'

See the FSI section for error code 8009.
See EAD 1 , "Drive Interconnections. "

Drive address
DI3022
(DR a) ADDR ON BUS
IN IS NOT CORRECT
BUS IN=vv EXPECT=xx

a
vv

xx

o

FRU08s 1
FRU199
FRU248
FRU118

Drive address
Address , on device data bus
'bus in
Expected address device data
bus I bus out'

DI3023
(DR a) ADDR IN STILL
ACTIVE AFTER ADDR
OUT WAS REMOVED

The following sequence should be used when isolating difficult
control unit to drive interconnection problems.
a
1.

Let the default run the routine on all drives.

2.

Check the drive displays and record the address of any drive
that does not display the message ' ................ '.

3.

Select the routine again and enter the drive address that did
not have the correct display. The routine will identify which
lines are not responding correctly.

1 This FRU is EC sensitive.

Drive address

See CARR-DR 4.

Note:
A valid address table is generated by selecting
all drives on the subsystem and checking for 'address
in'. If any drive in the subsystem does not respond, the
drive will not be in the valid address table and it will not
be tested when the "'running all drives" default is used.

3480 MI

EC336395

~ COPYright IBM Corp 1984.1985

Routine EE43

DIAG 160

Control Unit to Drive Bus and Tag Test - Routine EE43 (Continued)
DESCRIPTION

ADDITIONAL ACTIONS

The one s complement address sent from
,
the drive on device data bus 'bus in
remained on the bus after, the drive ,
dropped device data bus address in

See the FSI section for error code 8009.

FAILURE ID
DI3024

,

See EAD I, "Drive Interconnections."

The drive did not return status when
the control unit set device data bus
'command out'.

See the FSI section for error code 8E05.
See EAD I, "Drive Interconnections."

FRU085 1
FRUI99
FRU248
FRUI18

The drive returned 'unit check' in the
status byte at in i t i a I selection time.

See the FSI section for error code 8E06.
See EAD I, "Drive Interconnections."

013027

,

The drive did not return clock B in
when , the control unit set device data
bus clock A out'.

See the FSI section for error code 840A.
See EAD I, "Drive Interconnections. "

FRU085 1
FRUI18
FRUI16
FRUI34

DI3025
(DR a) STATUS IN DID
NOT BECOME ACTIVE
WITH COMMAND OUT
Drive address

FRU085 '
FRUI18
FRU116
FRU134

013026
(DR a) UNIT CHECK
WAS ACTIVE DURING
INITIAL SELECTION
Drive address

FRU085 '
FRU118
FRU199
FRU248

013027
(DR a) CLOCKB IN WAS
NOT RETURNED FOR
CLOCKA OUT
a

013028

'Clock B in' did not drop after the
control unit dropped device data bus
'clock A out'.

See the FSI section for error code 8300.
See EAD I, "Drive Interconnections. "

Drive address

FRU085 1
FRUI18
FRUI99
FRU248

013028
(DR a) CLOCKB IN WAS
STILL ACTIVE AFTER
CLOCKA OUT DROPPED
a

013029

,

'Clock B in did not set during the
data transfer of the control byte
(byte 0) to the drive.

See the FSI section for error code 840A.
See EAD I, "Drive Interconnections."

Drive address

FRU085 '
FRUI18
FRUI99
FRU248

013029
(DR a) CLOCKB DIDN'T
RESPOND AS EXPECTED
FOR CONTROL BYTE XFR
a

1 This FRU is EC sensitive.

3480 MI

EC336395

Cl Copyright IBM Corp. 1984. 1985

~)

DIAG 162

Drive address
,
Address on 'bus In
Expected address on 'bus out'

a

,

Routine EE43 (Continued)

DI3024
(DR a) AFTER ADDR IN
BECAME INACTIVE,
BUS IN=vv EXPECT=xx

a
013026

DIAG 162

ERROR DISPLAYS

a
vv
xx
DI3025

Routine EE43 (Continued)

Drive address

See CARR-DR 4.

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Control Unit to Drive Bus and Tag Test - Routine EE43 (Continued)

DI302A

'Clock B in' did not set during the
transfer of 16 bytes of display
information to the drive on the
device data bus.

See the FSI section for error code 8300.
See EAD 1, "Drive Interconnections. "

FRU08S 1
FRU 118
FRU199
FRU248

The drive hardware detected
an error.
,
Device data bus 'bus in contains
fai lure information from the drive.

See the FSI section for error code 89nn.
See EAD 1, "Drive Interconnections."

FRU08S 1
FRU199
FRU248
FRU118
FRU 116
FRU134
a

See the FSI section for error code 8C03.

The drive
did not set device data
,
bus status in' during the
de-selection sequence.

See EAD 1, "Drive Interconnections. "

FRU08s 1
FRU118
FRU116
FRU134

DI302D

The drive did not set clock B in
during the ending sequence on the
device data bus.

,

See the FSI section for error code 840A.
See EAD 1, "Drive Interconnections. "

FRU08s 1
FRU 118
FRU199
FRU248

DI302E

'Clock B in did not drop during the
ending sequence on the device data
bus.

See the FSI section for error code 840c.
See EAD 1, "Drive Interconnections. "

FRU08s 1
FRU 118
FRU199
FRU248

3480 MI

EC336395

C Copyright IBM Corp .... 984. 1986

Routine EE43 (Continued)

DIAG 164

Drive address

Drive address
,
Failure data on 'bus in

Drive address

Drive address
DI302E
(DR a) CLOCKB DID
NOT FALL DURING THE
ENDING SEQUENCE

a
1 This FRU is EC sensitive.

DIAG 164

DI302D
(DR a) CLOCKB DID
NOT BECOME ACTIVE
DURING ENDING SEQ.
a

,

Routine EE43 {Continued}

DI302C
(DR a) STATUS IN DID
NOT BECOME ACTIVE
DURING ENDING SEQ.
a

,

o

DI302B
(DR a) DR HARDWARE
DETECTED CHECK 1
BUS IN = xx

xx

DI302C

o

DI302A
(DR a) CLOCKB DIDN'T
RESPOND AS EXPECTED
FOR THE 16 BYTE XFR
a

DI302B

o

ERROR DISPLAYS

ADDITIONAL ACTIONS

DESCRIPTION

FAILURE 10

o

Drive address

See CARR-DR 4.

Control Unit to Drive Bus and Tag Test - Routine EE43 (Continued)
FAILURE 10
DI302F

DESCRIPTION
I
Device data bus I status in did not
drop during the ending sequence.

ADDITIONAL ACTIONS
See the FSI section for error code 8C07.
See EAD 1,"Drive Interconnect ions. II

FRUS

The drive microcode detected
an error.
Device data bus Ibus in I contains
fai lure information from the drive.

See the FSI section for error code 8Fnn.
See EAD 1, "0 rive Interconnections. II

FRU085 1
FRU 118
FRU 116
FRU134

IUnit check l was active in the ending
status from the drive.

See the FSI section for error code 8C01.

FRU085 1
FRU 118
FRU 116
FRU134
FRU199
FRU248

013033

FRU085 1
FRU 118
FRU 116
FRU134

When defaulting to all available
drives, the table bui ld module did
not find any drive avai lable.
(No drive returned laddress in l
during the selection sequence.)

1 This FRU is EC sensitive.

3480 MI

DIAG 166

Drive address
013032
ADDRESS DEFAULT NOT
SUCCESSFUL, RESTART
WITH VALID DR ADDR

The user entered a drive address that
is not a valid drive address for this
subsystem.

A timeout occurred while reading
status store to determine if this
is a dual, or single control unit
subsystem.

Drive address
Error information from
the drive
013031
(DR a) UNIT CHECK
WAS ACTIVE DURING
ENDING SEQUENCE

DI3033
ADDRESS ENTERED WAS
NOT VALID. ADDRESSES
, ,
MUST BE 'DO' - xx
xx

013034

Drive address
0130230
(DR a) DRIVE MICRO
CODE DETECTED ERROR
BUS IN = xx

a
013032

Routine EE43 (Continued)

DI302F
(DR a) STATUS IN DID
NOT FALL DURING THE
ENDING SEQUENCE

a
xx
013031

DIAG 166

ERROR DISPLAYS

a
013030

Routine EE43 (Continued)

See the FSI section for error code 5360.

FRU121
FRU 122
FRU133
FRU152
FRU195
FRU196
FRU134

0-7 for a single control unit
subsystem, or O-F for a dual
control unit subsystem
DI3034
TIMEOUT OCCURRED
WHILE TRYING TO READ
STATUS STORE

See CARR-DR 4.

EC336395

~ Copynghl IBM COI"p. 19B4, 1985

:}

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Control Unit to Drive Serial Test - Routine EE44
Prerequisite diagnostics must run without failure before
this diagnostic is run. See DIAG 3. "PREREQUISITE
DIAGNOSTICS ...

This routine tests the serial interconnection as follows:
1. The drive is selected to ensure that it can communicate with
the control unit.
2. The serial interconnection is used to issue a Clamp
command to the drive. CLAMP is displayed on the drive
message display.
3. The microcode attempts to re-select the drive using the
BI-OI parallel interconnection. If the preceding Clamp
command was recognized, the drive will not be available.
4. The serial interconnection is again used to issue an Unclamp
command.
5. The drive is again selected using the BI-DI parallel
interconnection. This time the drive should be available.
UNCLAMP is displayed on the drive message display.
6. At the end of the routine, the drive display is returned to its
normal unloaded display,·
•
Routine Start Address:

4010

See CARR-CU or CARR-DR, pages 1-1, 1-2, 1-3, and 1-4 for
the names and locations of the FRUs.
FAILURE 10
014021

DESCRIPTION
Selection of the drive was not successful.

ADDITIONAL ACTIONS
l.

2.

Run the control unit to drive bus and
tag test routine, EE43.
See the FSI section for error code
8E06.

FRUS
FRU085 1
FRUl18
FRUl16
FRU134

014022

014023

Following a Clamp command sent over the
serial interface to the drive, the next selection sequence was successful. This indicates that the Serial Clamp command
did not operate correctly.

See the FSI section for error code 8803.

FRU085 1
FRUl18

The selection sequence fol lowing the Unclamp
command was unsuccessful, indicating that
the Unclamp command did not operate
correctly.

See the FSI section for error code 8803.

FRU085 1
FRUl18

This could be a drive problem rather than
a serial interconnection problem if the
preceding Clamp command operated correctly.
014024

If a drive address is entered, only that drive will
be tested. If no drive address is entered, the routine will run
against all drives in the subsystem. The following screen is used
to enter a drive address.
014025

When defaulting to all drives, the table
build module did not find any drives available. (No drive returned 'address in' during selection.)

See the FSI section for error code 8807.

The user entered a drive address that is
not a valid drive address for this subsystem.

Run diagnostic EE40 on all drive
addresses to determine the pattern of the
failure.

014025
ADDRESS ENTERED WAS
NOT VALID. ADDRESSES
, ,
MUST BE '00' - xx
xx = 07 for a single control
unit subsystem or OF for
a dual control unit subsystem

014026

Error Displays

DIAG.07

A timeout occurred whi Ie reading status
store to determine if this is a dual- or
single-control-unit subsystem.

See the FSI section for error code 5360.

This screen is displayed several times
(about every 8 seconds during normal diagnostic execution). If the total execution
time is more than the normal run time (see
"Diagnostic Identification Code Table" run
times) see El03 in the FSI section.

None.

1 This FRU is EC sensitive.
3480 MI

EC336395

• Copynght IBM Corp 1984. 1985

014023
(DR a) SELECTION WAS
NOT SUCCESSFUL AFTER
'UNCLAMPING' THE DR.

014024
ADDRESS DEFAULT NOT
SUCCESSFUL, RESTART
WITH VALID DR ADDR

Valid Parameters:

External registers are defined in the OF (Data Fields) section of
this maintenance information.

014022
(DR a) SELECTION WAS
SUCCESSFUL AFTER
'CLAMPING' THE DR.

a = drive address

Run Drive Command exercises (see DIAG 1).

When an error is detected by the diagnostic program, the
maintenance device displays error information on its
keyboard/display. The first screen displays automatically. You
can see the second and following screens by pressing the
ENTER key on the keyboard/display.

014021
(DR a) INITIAL
SELECTION WAS NOT
SUCCESSFUL

a = drive address

Addressing:

Drive address (O-F, or OO-FF).
Enter FF to run all drives.

ERROR DISPLAYS

a = drive address

If no error occurs, the routine loops as if "LOOP
ROUTINE" is set. When an error is detected, the routine saves
the error information and displays the error on the MD. After
th~ error is displayed, the routine continues to loop on that error.
However, if a different error occurs, that new error is displayed
on the MD, and the routine will loop on the new error.

xx

DIAG 170

Routine EE44

FRUS

Error Loop:

DIAG=(EE44)-ENTER:
DRIVE
(xx)

o

o

FRU121
FRU122
FRU133
FRU152
FRU195
FRU196
FRU134

014026
TIMEOUT OCCURRED
WHILE TRYING TO READ
STATUS STORE

FRUll7
FRUl15
FRU121
FRU122

DIAG.07
WAITING FOR DIAG
COMPLETION

See CARR-DR 4.

Routine EE44

DIAG 170

Short Loop Write to Pattern Test - Routine EE52
Prerequisite diagnostics must run without failure before this
diagnostic is run. See DIAG 3, "PREREQUISITE DIAGNOSTICS."
This routine tests the short loop write, in the control unit. from
the write data flow to the read data flow. Microcode generated
patterns test the data path and the response from the read
detection circuits.

Test 1 performs initialization to set up the data path and
registers for tests 2, 3, and 4.

•

Test 2 operates in read forward mode USing the short loop
write to read controls.

•

Test 3 operates in read backward mode using the short loop
write to read controls.

•

Nole: When running the loop write to read diagnostic
routine normally, do not enter any test numbers or data
patterns.
Anyone of the valid data patterns listed below can be specified
for Tests 2, 3, and 4. Valid patterns are:
00 (see Note 1), 02, 04, 06, 08, OA, OC, OE, 10 through 1F, 20
through 26, 28, 2A, 2C, 2E, 30, 32, 34, 36, 38, 3A, 3C, 3E, 40,
42,44,46,48, 4A, 4C,4E, 50, 52,54, 56, 58, 5A,5C, 5E.

Routine EE52

DIAG 200

When an error is detected by the diagnostic program, the
maintenance device displays error information on its
keyboard/display. The first screen displays automatically. You
can see the second and following screens by pressing the ENTER
key on the keyboard/display.
The format of the display's first line Is the same for all detected
errors. The remaining three lines contain additional information
about the failure.
External registers are defined in the Data Fields (OF) section of
this maintenance information.

Pattern Entry Display

DIAG=(EE52)-ENTER:
PATTERN

Test 1 Error Display

tti i

LW2021
PARM ENTERED= xxxx,
IS NOT VALID. EX:
0202, 0302, OR 0402

Test 4 operates in write mode using the short loop write to
read controls.
tlil

DIAG 200

Error Displays

Pattern Control

The routine consists of four tests:
•

Routine EE52

Test data

Tests 2. 3. and 4 execute as follows:
•

The data pattern is stored in the buffer with the buffer control
set for Loop Write to Read.

•

Write and read data flow controls are set.

•

An IBG is written and followed by a microcode generated
pattern.

•

The read data flow is tested for the correct response.

•

Hardware error registers SCSE. WSE, RER. and RSR are
tested for error indications.

This sequence of operations is followed for each generated
pattern. If an error or unexpected condition is detected. an error
message displays on the maintenance device keyboard/display.

A pattern can be specified by entering a test number (02, 03, or
04) at position tt and a valid pattern number from the list above at
postion ii. For example, an entry of 023A would run test 2 with
data pattern 3A.
Notes:
1.

Data pattern 00 has special significance. When a test
number and data pattern number 00 are entered, all valid
data patterns are run for the test specified. The test a/so
runs if the BYPASS ERROR option is in effect. If errors are
detected, the error data is saved and the Failing Patterns
screens list all the failing patterns.

nnnnnn Failure 10
xxx x Parameter entered

FRUS
See CARR-CU or CARR-DR, pages 1-1, 1-2, 1-3, and '·4 ior the
names and locations of the FRUs.

Valid parameters for EE50:
If diagnostic section EE50 is specified, the valid drive address
parameters are O-F, or OO-OF.

Routine Start Address: 2010
Error Loop: If no error occurs. the routine loops as if "LOOP
ROUTINE" is set. When an error is detected. the routine saves
the error information and displays the error on the MD. After the
error is desplayed, the routine continues to loop on that error.
However, if a different error occurs. that new error is displayed
on the MD. and the routine will loop on the new error.

3480

ECA57693

,~ CoP¥"ght tBM Corp. 1984, 1985. 1988

~)

o o o o o o c o o o o c o o

0

o o c o o

(;

o o o o o o o o o o o o o

Short Loop Write To Read Pattern Test - Routine EE52 (Continued)

Routine EE52 (Continued)

DIAG 202

Routine EE52 (Continued)

DIAG 202

Test 2

OEseRI PTI ON

FAI LURE 10

ADDITIONAL ACTIONS

LWZOZl

The routine or pattern number is
not valid.

See -Pattern Control- on DrAG zoo to
verify that the routines and patterns
were entered correctly.

LWZOZZ

An external register error occurred.

If PSR bit 0 • I, see EAD I for error
code Fnnn.

LWZOZ3

A check I error occurred.

3480 MI EC AS7724
C Copyr,g",'6N Corp 'IISZ. ItIIO

See the FSI section for error code EIOG.

ERROR DISPLAYS

FRUS

FRUI14
FRUIZO
FRUll7
FRUll5
FRUI18
FRUIZl
FRUll9
FRU1l6
FRUIZZ
FRU1l7
FRU1l5
FRU1l4
FRU1l8
FRUIZl
FRU1l9
Fi Copyright IBM Corp. 19B4. 19B5

FRUI12 may not be present.

Bits expected from channel adapter RAM
Bits received from channel adapter RAM

Bits expected on bus lines
Bits received on bus lines

See CARR-CU 7.

Routine EE64 (Continued)

DIAG 330

Channel Adapter Function Test - Routine EE64 (Continued)
FAILURE 10
CI4036

DESCRIPTION
The microcode did not determine that a channel adapter
is present. The channel adapter is not tested.

. Routine EE64 (Continued)
FRUS

ADDITIONAL ACTIONS
Ensure that the channel adapter card is plugged. If it is
plugged, this is an error. If it is not plugged, ignore
this message. When running the Basic CU Test or E010,
this message is not displayed unless an error occurs.

DIAG 332

ERROR DISPLAYS

FRU133
FRU152
FRU195
FRU196
FRU121

CI4036
THE FOLLOWING ADAPS
WERE NOT TESTED
00

See the FSI section for error code 53AO.
Bits 0-3 correspond to channels A-D respectively.
If the bit is on, the channel was not tested.
Bits 4-7 are not used.
CI4037

The microcode sent a channel adapter order and status store
did not indicate that it was completed (CRR bit 7).

Remove the IML diskette, then press the IML switch to
cause a power-on-reset. Run routine EE64 again.
See the FSI section for error code 5311.

FRU133
FRU152
FRU195
FRU196
FRU121
FRU250
FRU251

CI4037
CHANNEL ADAPTER
DID NOT COMPLETE
LAST ORDER
ca
cc
cd
co

CI4038

The device address was bypassed during a select attempt.

See EAD I, "Status Store/Channel Adapter."

FRU133
FRU152
FRU195
FRU196

kk
mm
CI4039

The channel adapter did not respond with 'service in' to a
read type channel command.

See EAD I, "Status Store/Channel Adapter."

FRU 133
FRU152
FRU195
FRU196
FRU256

kk
mm

EC336395

CA=ca
CHNL CMD=cc
TGO=jj
TGI=kk
TGI EXPECTED=mm

The failing channel adapter
The failing channel command
Current 'tag out' data. See "Error
Displays" on DIAG 320 for bit meanings.
Actual 'tag in' data. See "Error
Displays" on DIAG 320 for bit meanings.
Expected 'tag in' data
CI4039
SERVICE-IN NOT
DETECTED DURING
DATA TRANSFER

ca
cc
jj

3480 MI

The failing channel adapter
The failing channel command
Channel adapter data
Channel adapter order
CI4038
RECEIVED SELECT-IN
DURING INITIAL
SELECT I ON

ca
cc
jj

CHNL CMD=cc
CA ADDR=ca
CA CMD=co
CA DATA=cd

CA=ca
CHNL CMD=cc
TGO=jj
TGI=kk
TGI EXPECTED=mm

The failing channel adapter
The fai l!ng read,type channel"command
Current tag out data. See Error
Displays" on DIAG 320 for bit meanings.
Actual 'tag in' data. See "Error
Displays" on DIAG 320 for bit meanings.
Expected 'tag in' data

Routine EE64 (Continued)

C Capyright IBM Carp, 1914, 1985

o

~)

DIAG 332

o

o

o

o

o

o

o

o

Channei Adapter Function Test - Routine EE64 (Continued;

CI403A

The channel adapter did not respond with
write type channel command.

Routine EE64 (Continued;
ADDITIONAL ACTIONS

DESCRIPTION

FAILURE 10

I

•
•
I
servIce
In
to a

See EAD I, "Status Store/Channel Adapter."

FRUS
FRUI33
FRUI52
FRUI95
FRUI96

mm
See EAD I, "Status Store/Channel Adapter."

FRUI33
FRUI52
FRUI95
FRUI96

mm
An unexpected channel command retry was requested by the
channel adapter microcode.

See the FSI section for error code 38CO.

FRUI33
FRUI52
FRUI95
FRUI96

mm

,. CopVllUhllRM Corp

EC336395
1984

19S~

CA=ca
CHNL CMD=cc
TGO=jj
BUSO=bo BUSI=bi
BUSI EXPECTED =mm

Actual status on 'bus in'
'Bus out' data
The failing channel adapter
The failing channel command
Current 'tag out' data. See "Error
Displays" on DIAG 320 for bit meanings.
Expected status on 'bus in'
CI403C
UNEXP CCR ON LAST
CHANNEL COMMAND
MARK-IN IS ACTIVE

bi
bo
ca
cc
jj

3480 MI

The fai ling channel adapter
The fai ling write type channel command
Current 'tag out' data. 'See "Error
Displays" on DIAG 320 for bit meanings.
Actual 'tag in' data. See "Error
Displays" on DIAG 320 for bit meanings.
Expected 'tag in' data

CI4038
CHAN STATUS ON BUS
IN DOES NOT MATCH
EXPECTED BUS IN
bi
bo
ca
cc
jj

CI403C

DIAG 334

CA=ca
CHNL CMD=cc
TGO=jj
TGI=kk
TG I EXPECTED=mm

CI403A
SERVICE-IN NOT
DETECTED DURING
DATA TRANSFER

kk

The received 'status in' ('bus in') did not match the
expected 'status in'

o

ERROR DISPLAYS

ca
cc
jj

CI403B

o

CA=ca
CHNL CMD=cc
TGO=jj
BUSO=bo BUSI=bi
BUSI EXPECTED =mm

Actual status on 'bus in'
'Bus out' data
The fai ling channel adapter
The fai ling channel command
Current 'tag out' data. See "Error
Displays" on DIAG 320 for bit meanings.
Expected status on 'bus in'

Routine EE64 (Continued)

DIAG 334

Channel Adapter Function Test - Routine EE64 (Continued)
DESCRIPTION

FAILURE 10
CI403D

The microcode forced a busy condition and the received
status did not match the expected status.

Routine EE64 (Continued)
ADDITIONAL ACTIONS

See EAD 1, "Status Store/Channel Adapter."

ERROR DISPLAYS

FRUS
FRU133
FRU152
FRU195
FRU196

CI403D
FORCED BUSY STATUS
NOT AS EXPECTED

bi
bo
ca
cc
jj
mm
CI403E

A channel adapter generated interrupt did not match the
expected interrupt.

See EAD 1, "Status Store/Channel Adapter."

FRU133
FRU152
FRU195
FRU196

ca
cc
ei
The channel adapter did not respond with an expected
interrupt.

See EAD 1, "Status Store/Channel Adapter."

FRU133
FRU152
FRU195
FRU196

ca
cc
ei
CI4040

A PUT type channel command did not generate an interrupt
at the expected end of data.

See EAD 1, "Status Store/Channel Adapter."

FRU133
FRU152
FRU195
FRU196

ca
cc
ei

3480 MI

EC336395

C> Copyright IBM Corp. 1984. 1985

J

CA=ca
CHNL CMD=cc
TGO=jj
INTRPT=ai
EXP INTRPT=ei

Actual interrupt received. See "Error
Displays" on DIAG 320 for interrupt
descriptions.
The fa iIi ng channe I adapter
The fai I ing channel command
Expected interrupt
CI4040
PUT INTERRUPT NOT
DETECTED ON LAST
DATA BYTE

ai

CA=ca
CHNL CMD=cc
TGO=jj
INTRPT=ai
EXP INTRPT=ei

Actual interrupt received. See "Error
Displays" on DIAG 320 for interrupt
descriptions.
The fai I ing channel adapter
The fai I ing channel command
Expected interrupt
CI403F
FREE DEV INTERRUPT
DID NOT OCCUR

ai

CA=ca
CHNL CMD=cc
TGO=jj
BUSO=bo BUSI=bi
BUSI EXPECTED =mm

Actual status on 'bus in'
'Bus out' data
The fai I ing channel adapter
The fai l:ng chan~el command "
Current tag out data. See Error
Displays" on DIAG 320 for bit meanings.
Expected status on 'bus in'
CI403E
INTERRUPT RECEIVED
NOT EXPECTED DURING
INITIAL SELECTION

ai

CI403F

DIAG 336

CA=ca
CHNL CMD=cc
TGO=jj
INTRPT=ai
EXP INTRPT=ei

Actual interrupt received. See "Error
Displays" on DIAG 320 for interrupt
descriptions.
The fai I ing channel adapter
The fai ling channel command
Expected interrupt

Routine EE64 (Continued)

DIAG 336

o

o

o

o

o

o

o

Channel Adapter Function Test - Routine EE64 (Continued;

CI4041

The channel adapter responded with an unexpected interrupt.

See EAD 1, "Status Store/Channel Adapter."

FRUS
FRU133
FRU152
FRU195
FRU196

CI4041
INTERRUPT RECEIVED
WAS NOT AS EXPECTED

ca
cc
ei
A 'unit check' was detected during initial selection.

See EAD 1, "Status Store/Channel Adapter."

FRU133
FRU152
FRU195
FRU196

The BCSE register did not indicate complete on a Write CRC
operation from the channel buffer.

See the FSI section for error code A140.

FRU133
FRU152
FRU195
FRU196
FRU114
FRU120
FRU112 1
FRU113 1
FRU256

a

The BCSE register did not indicate channel pointer stop
after reading all the data from the data buffer.

See the FSI section for error code A131.

FRU133
FRU152
FRU195
FRU196
FRU114
FRU120
FRU112 1
FRU 113 1
FRU256

b
c
d
e
ca
cc
1 This FRU is EC sensitive.

3480 MI

EC336395

'" Copyright IBM Corp. 1984. 1985

FRU112 may not be present.

CA=ca
CHNL CMD=cc
TGO=jj
INTRPT=ai
EXP INTRPT=ei

CA=ca
CHNL CMD=cc
BYTE CNT=by
BCSE=abcde

Buffer channel status and error register
bits 0-3
Channel error group 0
Channel error group 1
Channel error group 2
Channel error group 3
The fail ing channel adapter
The fai ling channel command
CI4044
BCSE CHNL PNTR STOP
NOT DETECTED

a

CA=ca
CHNL CMD=cc
TGO=jj
INTRPT=ai
EXP INTRPT=ei

Actual interrupt received
The failing channel adapter
The fai ling channel command
Expected interrupt
CI4043
BCSE MP WRITE COMP
NOT DETECTED
FOLLOWING WRITE CRC

b
c
d
e
ca
cc
CI4044

DiAG 338

Actual interrupt received. See "Error
Displays" on DIAG 320 for interrupt
descriptions.
The fai ling channel adapter
The fai ling write type channel command
Expected interrupt
CI4042
UNEXPECTED UNIT
CHECK DURING INITIAL
SELECTION

ai
ca
cc
ei
CI4043

o

ERROR DISPLAYS

ai

CI4042

c

Routine EE64 (Continued)
ADDITIONAL ACTIONS

DESCRIPTION

FAILURE ID

o

CA=ca
CHNL CMD=cc
BYTE CNT=by
BCSE=abcde

Buffer channel status and error register
bits 0-3
Channel error group 0
Channel error group 1
Channel error group 2
Channel error group 3
The failing channel adapter
The failing channel command

See CARR-CU 7.

Routine EE64 (Continued)

DIAG 338

Channel Adapter Function Test - Routine EE64 (Continued)

CI~O~5

ADDITIONAL ACTIONS

DESCRIPTION

FAILURE 10

Routine EE64 (Continued)

Any buffer error was detected in the BCSE register.

See the FSI section for error code A170.

FRUS

ERROR DISPLAYS

FRU133
FRU152
FRU195
FRU196

CI~O~5

BUFFER ERROR
DETECTED FOLLOWING
READ OR WRITE CMD.

FRUll~

FRU120
FRUl12 1
FRUl13 1
FRU256

a
b

c
d

e
ca
cc

by
CI~O~6

CI~0~7

Programming error. Command data taken from a control
table was not a Read command.

Call your next level of support.

Programming error. Byte count taken from a control table
was greater than 32.

Call your next level of support.

The service representative (SR) entered an invalid channel
adapter address. The address received by the microcode is
shown in the ADDRESS RCVD field. This could be an MD
communication error.

The status store did not acknowledge an order from the
channel adapter card.

Buffer channel status and error register bits 0-3
Channel error group 0
Channel error group 1
Channel error group 2
Channel error group 3
The failing channel adapter
The fai ling channel command
01 for Write command or 02 for Read command

READ CMD DOES NOT
XLATE TO EITHER
FORWARD OR BACKWARD

CI~0~7

ILLEGAL BYTE COUNT
FOR PUT COMMAND
CNT=bc

Ensure that the Maintenance device (MD) is working
correctly.

The MD
FRU169

INVALID CA ADDRESS
VALID = ABC 0 F
ADDRESS RCVD = xx

See REF screen or Error Displays.

Remove the IML diskette, then press the IML switch to
cause a power-on-reset. Run routine EE6~ again.

Byte count
CI~0~8

xx
CI~0~9

CA=ca
CHNL CMD=cc
BYTE CNT=by
BCSE=abcde

CI~0~6

bc
CI~0~8

DIAG 340

Data received by the microcode

FRU121
CI~0~9

CHANNEL ADAPTER
DID NOT ACKNOWLEDGE
LAST ORDER

See the FSI section for error code 5310.

CA ADDR=ca
CA CMD= co
CA DATA=cd
ca
cd
co
1 This FRU is EC sensitive.

3480 MI

EC336395

~ Copyright IBM Ccwp. 19B4. 1986

FRUl12 may not be present.

The fai ling channel adapter
Channel adapter order
Channel adapter data

See CARR-CU 7.

Routine EE64 (Continued)

DIAG 340

o

o

o

o

o

o

o

Channei Adapter Function Test - Routine EE64 {Continued;
FAILURE ID
CI404A

DESCRIPTION
The microcode sent a channel adapter order and status store
did not indicate that it was completed (CRR bit 7).

ADDITIONAL ACTIONS

FRUS

Remove the IML diskette, then press the IML switch to
cause a power-on-reset. Run rout i ne EE64 again.

FRU133
FRU152
FRU195
FRU196
FRU121
FRU250
FRU251

Unexpected errors have occurred which are either check 1,
check 2, or internal channel adapter errors.

See DIAG 320, "Error Analysis. "

The microcode detected a read back miss compare after
writing channel adapter RAM addresses.

See the FSI section for error code 3302.
See DIAG 320, "Error Analysis. "

CI404A
CHANNEL ADAPTER
DID NOT COMPLETE
LAST ORDER

The received tag-in did not match the expected tag-in
during the data transfer of wr i te data to the buffer, or
read data from the buffer.

Compare the received tag-in to the expected tag-in to
determine the failing tag.

FRUI33
FRU152
FRU195
FRU196
FRU121
FRU250
FRU251

The received interrupting channel adapter address does not
match the current channel adapter.

Run routine EE64 once for each channel.
See the FSI section for error code 5350.
See DIAG 320, "Error Analysis. "

CI404F

3480 MI
«)

The microcode detected a read back miss compare after
writing channel adapter data to the data buffer.

EC336395

CopYright IBM Corp. 19B4. 19B5

See the FSI section for error code 3302.
See DIAG 320, "Error Analysis. "

CA ADDR=ca
CA CMD=co
CA DATA=cd

The failing channel adapter
Channel adapter data
Channel adapter order

CI404c
READ DATA MISCOMPARE
DATA IS:
EXP=ee
RCVD=ff

FRU133
FRU152
FRU195
FRU196
FRU114
FRU120
FRU126
FRU250
FRU251
FRU256

Expected channel adapter RAM data
Received channel adapter RAM data
CI404D
CHANNEL IN TAGS ARE
WRONG.

ca
to
aa
bb

CI404E

DIAG 342

CI4048
A "CU" OR "CA" ERROR
CONDITION WAS
DETECTED

ee
ff
·c1404D

o

ERROR DISPLAYS

ca
cd
co

CI404C

o

Routine EE64 {Continued;

See the FSI section for error code 5311.

CI4048

o

Failing channel adapter address
Last tag-out, Service Out or Data Out
Tags-in received. See "Error Displays" on
DIAG 320 for bit meanin~s.
Tags-in expected. See Error Displays " on
DIAG 320 for bit meanings.

FRU133
FRUI52
FRU195
FRUI96

CI404E
WRONG CA ADDRESS
CAUSED INTERRUPT

FRU133
FRU152
FRU195
FRU196
FRU121
FRU250
FRU251

CI404F
READ DATA MISCOMPARE
DATA IS:
EXP=ee
RCVD=ff
ee
ff

CA ADDR=ca
TAGS OUT=to
TAGS IN=aa
EXP TAGS IN=bb

Expected buffer data
Received buffer data

Routine EE64 (Continued)

DIAG 342

Channel Adapter Function Test - Routine EE64 (Continued)

CI4050

CI4051

CI4052

ADDITIONAL ACTIONS

DESCRIPTION

FAILURE 10

The BCSE register did not indicate stop after the
microcode raised 'command out' through the channel
adapter.

'Service in' or 'data in
end of read data.

Routine EE64 (Continued)

, was detected after the expected

See the FSI section for error code A131.
See DIAG 320, "Error Analysis."

See the FSI section for error code A131.
See DIAG 320, "Error Analysis."

FRUl33
FRU152
FRU195
FRU196

CI4050
BCSE CHNL STOP NOT
DETECTED FOLLOWING
A WRITE COMMAND

CI4051
TOO MANY SERVICE-IN
OR DATA-IN ON READ
COMMAND

Call your next level of support.

Programming error.

CI4052
PROGRAMMING ERROR

See DIAG 320, "Error Analysis."

CI4053

ERROR DISPLAYS

FRUS
FRUl14
FRUI20
FRUl12 1
FRUl13 1
FRUI33
FRUI52
FRU195
FRU196
FRU256

DIAG 344

The channel adapter did not acknowledge a channel adapter
reset. The channel adapter is not tested.

Ensure that the channel adapter card is plugged. If it is
plugged, this is an error. If it is not plugged, ignore
this message. When running the Basic CU Test or E010,
this message is not displayed unless an error occurs.
See CARR-CU 1189 for the correct DLR switch sett i ngs.

FRU133
FRUI52
FRUI95
FRUI96
FRU121

See the FSI section for error code 53AO.

CI4053
THE FOLLOWING ADAPS
WERE NOT TESTED:
00
DLR= YY
Bits 0-3 correspond to channels A-D respectively.
If the bit is on, the channel was not tested.
Bits 4-7 are not used.

See DIAG 320, "Error Analysis."

yy = Contents of the DLR external register
CI4054

The BCSE register did not indicate complete on a Write CRC
operation from the channel buffer.

See the FSI section for error code A140.
See DIAG 320, "Error Analysis."

CI4055

The BCSE register did not indicate channel pointer stop
after reading all the data from the data buffer.

See the FSI section for error code A131.
See DIAG 320, "Error Analysis."

1 This FRU is EC sensitive.

3480MI

EC336395

~ CopyrighllBM Carp. 1984, 1986

FRUl12 may not be present.

FRU133
FRU152
FRU195
FRU196
FRUl14
FRU120
FRUl12 1
FRUl13 1
FRU256
FRU133
FRU152
FRU195
FRU196
FRUl14
FRU120
FRUl12 1
FRUl13 1
FRU256

CI4054
MP WRITE COMP NOT
DETECTED FOLLOWING
A WRITE CRC

CI4055
CHNL PNTR STOP NOT
DETECTED FOLLOWING
A READ COMMAND

See CARR-CU 7.

Routine EE64 (Continued)

DIAG 344

o

o

o

c

o

c

o

Channel Adapter Function Test - Routine EE64 (Continued)
FAILURE 10
CI4056

DESCRIPTION

See the FSI section for error code A170.
See DIAG 320, "Error Analysis."

CI4057

The microcode detected and unexpected level 6 interrupt.
Channel Adapter Addresses from the CCC external register:
80 = channel adapter A
40 = channel adapter B
20 = channel adapter C
10 = channel adapter 0

CI4058

At this time the processor should be in the correct level
indicated by the expected data.

Compare the contents of the CCC register with the CRR
register, they should be the same. If not, a channel
adapter has failed and either no interrupt is set or
multiple interrupts are set.
See DIAG 320, "Error Analysis."

FRUS

See DIAG 320, "Error Analysis."

FRU133
FRU152
FRU195
FRU196
FRU 114
FRU120
FRU112 1
FRU113 1
FRU256

CI4056
BUFFER ERROR
DETECTED FOLLOWING
READ OR WRITE CMD.

FRU133
FRU152
FRU195
FRU196
FRU121
FRU250
FRU251

CI4057
HOT LEVEL 6 INTRPT.
FOLLOWING A RESET
CCC=aa
CRR=bb

FRU117
FRU133
FRU152
FRU195
FRU196

CI405A

CI405B

Channel adapter internal diagnostics did not complete.
Correct completion is indicated by the ending status being
set, along with a level 6 interrupt.

See DIAG 320, "Error Analysis."

Channel adapter internal diagnostics detected an error
during execution.

See DIAG 320, "Error Analysis."

Unexpected errors have occurred, either check 1, check 2,
or internal channel adapter errors.

See DIAG 320, "Error Analysis."

1 This FRU is EC sensitive.

3480 MI
It Copyr.ghllBM

EC336395
Corp. 1984, 1985

FRU112 may not be present.

FRU133
FRU152
FRU195
FRU196

Contents of the channel card control register
Contents of the channel request register
CI4058
PSR IS NOT CORRECT
INTERRUPT TEST
EXP=aa
ACT=bb

aa
bb
CI4059

DIAG 346

ERROR DISPLAYS

aa
bb
Compare the actual contents of the PSR register to the
expected contents, they should be the same.

o

o

Routine EE64 (Continued)
ADDITIONAL ACTIONS

Any buffer error was detected in the BCSE register.

o

Expected contents of the PSR external register
Actual contents of the PSR external register
CI4059
LEVEL 6 INTERRUPT
DID NOT OCCUR

CI405B
CHANNEL ADAPTER
DIAGNOSTICS FAILED

CI405B
A "cu" or "CA" ERROR
CONDITION WAS
DETECTED

See CARR-CU 7.

Routine EE64 (Continued)

DIAG 346

Channel Adapter Function Test - Routine EE64 (Continued)
DESCRIPTION

FAILURE 10
CI405C

The internal channel adapter parameter data should be
'FF I . An error may have been detected before the parameter
was set.

Routine EE64 (Continued)
ADDITIONAL ACTIONS

FRUS

ERROR DISPLAYS

See DIAG 320, "Error Analysis."

CI405C
CACI DATA ERROR
FIRST LVL 6 INTRPT.
EXP=ee
ACT=ff
ee
ff

CI405D

The internal channel adapter diagnostic has forced a level
6 interrupt, however, it is not detected by the control
unit microcode.

See DIAG 320, "Error Analysis."

CI405E

The internal channel adapter diagnostic forced an error,
however, when the CER was checked it did not have the
correct channel error set.

See DIAG 320, "Error Analysis."

Data expected
Data received
CI405D
MID TEST CA INTRPT.
DID NOT OCCUR.

FRU133
FRU152
FRUI95
FRU196
FRU250
FRU251

CI405E
EXPECTED CER ERROR
DID NOT OCCUR.
EXP=ee
ACT=ff
ee
ff

Data expected
Data received

CI405F

The channel adapter address-switch test detected a parity
error while reading the channel adapter address switch
(the thumbwheel switch).

See DIAG 320, "Error Analysis. "
The cables associated with this failure are in cable
See FSI I for
~roups 23A, 23B, 23C, and 230.
Cable Group Table."

FRU197
FRU133
FRUI52
FRUI95
FRUI96

CI405F
CHANNEL ADAPTER ADDR
THUMB WHEEL SWITCH
PARITY ERROR.

CI4060

The channel adapter address-switch test detected an
undefined mode whi Ie reading the channel adapter address
switch (the thumbwheel switch).

See DIAG 320, "Error Analysis."
The cables associated with this failure are in cable
See FSI I for
~roups 23A, 23B, 23C, and 230.
Cable Group Table."

FRU197
FRUI33
FRUI52
FRUI95
FRU196

CI4060
CHANNEL ADAPTER ADDR
THUMB WHEEL SWITCH
INVALID MODE.

The channel adapters in this machine are down level and
are not supported by this level support disk.

You should install ECA 025 or use the level of the
support disk that you received with your machine.
EC A29128 is the last level that supports the down level
channel adapters.

FRUI33
FRU152
FRU195
FRU196
FRU121

CI4061

3480 MI

EC336396

DIAG 348

CI4061
DOWN LEVEL CHANNEL
ADAPTER IS NOT
SUPPORTED.
INSTALL EtA 025.

Routine EE64 (Continued)

• Capwrigtn IBM Carp. 1884. 1815. 18U

~)

DIAG 348

o

o

Externa.egister Bus AdQssing and Dataqattern Test - RAne EE85.·
Prerequisite diagnostics must run without failure before this
diagnostic is run. See DIAG 3, "PREREQUISITE DIAGNOSTICS."

Test 3 External Register Test Sequence

This routine consists of five tests.

START

Routine Start Address: 5010

Test 1
•

•

Tests the external register address extend bits (bits 6 and 7)
and the path from the process control register as it Is used
for external register addressing.
Tests external address error detection.

Error Loop: If no error occurs, the routine loops as if "LOOP
ROUTINE" is set When an error is detected, the routine saves
the error information and displays the error on the MD. After the
error is displayed, the routine continues to loop on that error.
However, if a different error occurs, that new error is displayed
on the MD, and the routine will loop on the new error.

Test 2
•
•

Ensures that an external register error causes a level 0
interrupt
Tests the path from the processor control register as it is
used for external register addressing.

Error Loop: If no error occurs, the routine loops as if "LOOP
ROUTINE" is set When an error is detected, the routine saves
the error information and displays the error on the MD. After the
error is displayed, the routine continues to loop on that error.
However, if a different error occurs, that new error is displayed
on the MD, and the routine will loop on the new error.

Ro
REG

NAME

WRT
REG

RO
REG

REG WRT
NAME REG

x

RCR

X

X

BDe

REG

x

RD
REG

x

eee

x

MOO

X

Rile

x

x

BOSE X

CDR

X

nePL x

x

BDR

X

X

CMR

X

nllPIl

x

x

BOSS

X

X

ITe

x

ROPL

X

X

BOPH

X

X

DeB

x

ReSIl

x

BCPC

X

eER

x

ReSl x

x
x

WSE

X

CRR

X

BIISII

X

X

RSR

X

DlR

X

ROSL X

X

RER

X

DSH

X

RWRP

X

X

RRC

X

DSL

X

Bee

x

RPR

X

DIR

X

BCSE

X

X

OSE

X

RCR

X

MOl

X

BCSS

X

•

Tests that external register errors can be set when bad
parity data is written to writable registers

•

Does not test processor external registers.

Error Loop - XR Register Write: Loop on the same XR
address writing 00.

(1) CCC

(17) BCSH

(2) CCA

(18) BCSL

(3) CDR

(19) BWRP

(4) ITC

(20) BCC

(5) OCB

(21) BCSE

(6) DTR

(22) BCR

(7) DSC

(23) BCSS

(8) DSR

(24) BDC

X

(9) MOO

(25) BOSE

X

* BHR

X

(10) WCR

(26) BDR

(11)RCR

(27) BOSS

NOTE: If the I_proved Data Recording
Capability or the ~.S Mh/s feature
is Installed, the featllre registers
are tested in place of the
registers Ilrer.eded hy an *.

FEATURE REGS
REG

EE85

DI• . 400 .

•

Ensures that external register address errors are set when
addresses that are not valid are written to or read from the
external register bus.

Error Loop - XR Write: Loop on the same XR address writing
00 and inhibit parity.

Test 4 External Register Test Sequence

X

END

Rtine

Error Loop - XR Read: Loop on the same XR address reading.

X

X

o
Test 5

Test 4

* BDG9
* BDAT

(12) ROC

Test 5 Address Test Sequence For Addresses
That Are Not Valid
•

Write and Read Addresses:
A04 through AOF
A 13 through A 17
B08 through BOF
COO through COF
C14 through C17
013 and 014 (Valid if the 4.5 Mb/s or Improved Data
Recording Capability features are installed).

•

Write Only Addresses:
A07
A10 through A12
B01
B03 through B06
B10
813
C12
C19
019

(28) BCPC

(13) BCPH

*(29) BOAT

NAME

WRT
REG

RO
REG

(14) BCPL

*(30) BDGO

CHRS

X

X

(15) BDPH

*(31) BDG1

014

X

X

(16) BDPL

*(32) BMR

CIII

X

X

CHDT X

X

CHS

Test 3
•

REG WRT
NAME REG

o

•

Read Only Addresses:
A18
818

DOD

X

Tests that writable external registers can be written to and
that readable external registers can be read. The data
written is ripple data 00 through FF. After each write, the
data is read and the read data is compared to the written
data.

Error Displays
When an error is detected by the diagnostic program, the
maintenance device displays error information on its
keyboard/display. The first screen displays automatically. You
can see the second and following screens by pressing the ENTER
key on the keyboard/display.

Error Loop - XR Register Write: Loop on the same XR
address writing the same data.

The format of the display's first line is the same for all detected
errors. The remaining three lines contain additional information
about the failure.

Error Loop - XR Register Read: Loop on the same XR
address reading the same data.

External registers are defined in the OF (Data Fields) section of
this maintenance information.

FRUS
See CARR-CU or CARR-DR, pages 1-1, 1-2, 1-3, and 1-4 for the
names and locations of the FRUs.

3480 MI EC A57723
c) Copyright IBM Corp.

1882.1889

IBM Comfidential

Routine EE85

DIAG 400

o

o

o

o

o

{)

{)

,'}

o

o

o

o

o

o

o

o

o

o

o

External Register Bus Addressing and Data Pattern Test - Routine EE85

Routine EE85

Prerequisite diagnostics must run without failure before this
diagnostic is run. See DIAG 3, "PREREQUISITE DIAGNOSTICS."

Test 3 External Register Test Sequence

This routine consists of five tests.

START

iREG

Routine Start Address: 5010

INAME
ICCC

Test 1
•

•

MOO

Tests the external register address extend bits (bits 6 and 7)
and the path from the process control register as it is used
for external register addressing.

CDR

Tests external address error detection.

ITC

Error Loop: If no error occurs. the routine loops as if "LOOP
ROUTINE" is set. When an error is detected, the routine saves
the error information and displays the error on the MD. After the
error is displayed, the routine continues to loop on that error.
However, if a different error occurs, that new error is displayed
on the MD, and the routine wiil loop on the new error.

CMR

IOCB

ICER

DLR
IOSH

Test 2

,OSL
!OIR

Ensures that an external register error causes a level 0
interrupt
•

I

iI DSE

I

!

II

I

WRT I' RO
REG I REG

I x Ii x
Ix I I
X
I
Ix I
Ix I
Ix
I
I

i REG !
i NAME ,I

ix
Ix
Ix

ix
.

:1'

x

x

I

RO
REu

i

[REG

I

x

Ix
I

!
I

Isoc
!

X

Ix

;

iBDSE

X

I

BCPL

X

!x

II

I

i BOR

X

BOPHI

x

Ix

i

iBOSS I x

i

IROC
I

1

i

: BDPH I

Ism! x i x
!BOSH [x I x
IBDSLI x I X
! BWRP!

scc

x I

: BCSE i

x

1x
Ix
I, x

If no error occurs, the routine loops as if "LOOP
ROUTINE" is set. When an error is detected, the routine saves
the error information and displays the error on the MD. After the
error is displayed. the routine continues to loop on that error.
However, if a different error occurs, that new error is displayed
on the MD, and the routine will loop on the new error,

•

Does not test processor external registers.

Error Loop - XR Register Write: Loop on the same XR
address writing 00.

iWSE i x
!RSR i x

(19) BWRP

(4) ITC

(20) BCC

(5) DCB

(21) BCSE

lRER

(6) DTR

(22) BCR

(7) DSC

(23) BCSS

(8) DSR

(24) BDC

(9) MDO

(25) BDSE

(10) WCR

(26) BDR

(11) RCR

(27) BDSS

(12) RDC

(28) BCPC

! .: BOGel

!---+--+--1
i 3~R i x ' SOAT I'
1 \.
I

I

x ,! x
X

4.5 MB/S REGS

I

NOTE: If the 4.5 Mb/s channel feature is

i

installed, the 4.5 Mb/s registers
~EG WRT RD i
C" . RC" I
a!'"e tested in place of tne registers NAME I R""U
i .. ".l I
preceded by an *.
'----'---.,---,
CMRS!X
CMM

Ensures that external register address errors are set when
addresses that are not valid are written to or read from the
external register bus.

Error Loop - XR Write:

Loop on the same XR address writing

00 and inhibit parity.

Test 4 External Register Test Sequence
(18) BCSL

IX
Ix

•

Error Loop - XR Read: Loop on the same XR address reading.

(3) CDR

·1, X
BC?C,

iRPR

LOOP:

Tests that external register errors can be set when bad
parity data is written to writable registers

(2) CCA

x

Tests the path from the processor control register as it is
used for exterr.al register addressing.

Error

•

(17) BCSH

!RRC

Ix

RO
REG

DIAG.400

Test 5

(1) CCC

I

t

WRT
REG

i x

IRCR

I

I

iNAME

I

1

\oIRT
REG

I

I

Test 4

o

(13) BCPH

(29) BDAT

(14) BCPL

(30) BDGO

(15) SDPH

(31) BDG1

(16) BDPL

(32) SMR

Test 5 Address Test Sequence For Addresses
That Are Not Valid
•

Write and Read Addresses:
A04
A 13
B08
COO

through AOF
through A 17
through BOF
through COF
C1~ through C17
D13 and D14 (Valid if the 4.5 Mb/s feature is installed).

•

Write Only Addresses:
A07
A10 through A12
B01
B03 through B06
B10
B13
C12
C19
D19

•

Read Only Addresses:

x!

A18
B18
DOD

Ix

Test 3
•

Tests that writable external registers can be written to and
that readable external registers can be read. The data
written is ripple data 00 through FF. After each write, the
data is read and the read data is compared to the written
data.

Errol Loop - XR Register Write:

I

eMS

I, x

x

Error Displays
When an error is detected by the diagnostic program, the
maintenance device displays error information on its
keyboard/display. The first screen displays automatically. You
can see the second and following screens by pressing the ENTER
key on the keyboard/display.

Loop on the same XR

address writing the same data.

Error Loop - XR Register Read: Loop on the same XR
address reading the same data.

CMOT I X

The format of the display's first line is the same for all detected
errors. The remaining three lines contain additional information
about the failure.
External registers are defined in the OF (Data Fields) section of
this maintenance information.

FRUS
See CARR-CU or CARR-DR, pages 1-1, 1-2, 1-3, and 1-4 for the
names and locations of the FRUs.

3480 MI EC A57721

Routine EE85

DIAG 400

External Register Bus Addressing and Data Pattern Test - Routine EE85 (Continued)

Routine EE85 (Continued)

DIAG 402

Routine EE85 (Continued)

DIAG 402

External Register Table (XRT)
Word 0
Note: The bits in the following table are contained in the first byte of word 0
of the XRT.
Bit
Bit 0

Label
HIT2A

Bit 1

Area

Description I Detail

XR
A Bus
Flags

Two or more external registers failed while testing the registers on bus A.

HIT1A

XR
A Bus
Flags

One external register failed while testing the registers on bus A.

Bit 2

WRAF

XR
A Bus
Flags

A failure was detected while writing a register on bus A.

Bit 3

RDAF

XR
A Bus
Flaas

A failure was detected while reading a register on bus A.

Bit 4

HIT2B

XR
B Bus
Flags

Two or more external registers failed while testing the registers on bus B.

Bit 5

HIT1B

XR
B Bus
Flags

One external register failed while testing the registers on bus B.

Bit 6

WRBF

XR
B Bus
Flaas

A failure was detected while writing a register on bus B.

Bit 7

RDBF

XR
B Bus
Flags

A failure was detected while reading a register on bus B.

3480 MI

EC336395

e Copyright IBM Corp. '984. '985

,)

o

o

o

o

o

o

o

o

External Register Bus Addressing and Data Pattern Test - Routine EE85 (Continued)

o
Routine EE85 (Continued)

o
DIAG 410

Tests 1 and 2 Error Displays
.--------~----------------.-------------------------------------r_-------------------------------------,-------r---------------------------------------------------------,

FAILURE ID
XB5021

DESCRIPTION
XR error is on after the hardware, check I, and user reset at
the start of the first test in routine EE85.

XB5022

The XRA did not match the data compare table during the test
of all possible combinations of data into the XRA.

XB5023

An XR error occurred while using procedure registers during
the testing of XRA.

XB5024

An error occurred while using the diagnostic mode to force an
error while writing to the JAH register (data equal 00), and
using extend bits for addressing external registers A or B.
An XR error is expected along with specific data in XRA.

XB5025

An XR or check 2 error is on unexpectedly during test of XRA
following a user test.

XB5026

1. An XR error is forced causing a level 0 interrupt. These
results are expected: XR error, check 2, and user write error.
2. An XR interrupt occurred; however, the XR error or check 2
are not set.
3. An XR error is forced with interrupts disabled, with XR
errors and check 2 in the processor error register (PER).
4. Current or preceding interrupt levels are not correct.

XB5027

1. A level 0 interrupt occurred; however, the current and
preceding interrupt levels do not match. Current = 0 and
previous = 7.
2. After returning from level 0, the PSR is not correct.

XB5028

1. Processor problems.
2. A level 0 interrupt occurred and the XRA did not have the
correct value in it.
3. The return from a level 0 interrupt did not occur or the
level 0 interrupt occurred too soon.
4. The JAH register did not activate 'users active' when an
error was forced on the data bus. (Address is correct.)
5. XR error interrupt did not occur.
6. Check reset is activated and check 2 and/or XR error did
not reset.
1. The preceding interrupt level changed when the reset is
given and XR error is not reset in the PER.

XB5029

To help in problem isolation, also run
diagnostics EEI0, EE30, EE40, EE50, EE60
EE90, and EEAO.
1.
2.

3.
4.

5.

6.

7.
8.

9.

10.
11.

Both read and write operations are performed while forcing an
addressing error on the XR address. The following failures can
occur:
• XR error or chec~ 2 did not occur
12.
• PER XR errors were not set or reset correctly
• IMR responded to an address with bad parity.
13.
While testing to assure that A and B bus does not affect the
processor bus, an XR or check 1 error occurred.

XB502A
XB502B

3480

ADDITIONAL ACTIONS

Remove the IML diskette, then press the
IML switch to cause a power-on-reset.
Run routine EE85 again.
If the value of ERA or ERB is other
than 0, see the FSI section for error
code EI00. Also see action number 4
of this Additional Actions column.
If PSR bit 0 = I, see EAO 1 for error
code Fnnn.
If a diagnostic failure occurs and no
errors are detected by the hardware,
see the FSI section for error code
EI00 and perform the procedures for
the microprocessor and control
storage.
XR errors (PSR bit 0 = 1) can cause
ERA and ERB errors. Use diagnostic
EEI0 to check the ERA and ERB
registers.
If ERA and ERB are not 0, record the
contents (if the screen is displayed)
of ERA and ERB and see the FSI section
for error code EI00.
If PSR bit 0 = I, record the contents
of PSR, PER, XRA, MTI, and MOl.
See EAD 1 for error code Fnnn.
If BCSE channel error groups 0-3
indicate any errors, record the contents
of BCSE. See the FSI section for error
code D5nn.
If BOSE channel error groups 0-3
indicate any errors, record the contents
of BOSE. See the FSI section for error
code 06nn.
If DSE bits 0, I, or 2 = I, record the
contents of DCB, OCR, DSE, DIR, and OTR.
See the FSI section for error code 04nn.
See EAO I, "Drive Interconnections."
If any RER bits = I, or if RSR bits 5,
6, or 7 = I, record the contents of RCR,
RRC, RER, RSR, and ROC. See the FSI
section for error code D8nn.
If WSE bits 4, 5, or 6 = I, record the
contents of WCR and WSE. See the FSI
section for error code 07nn.
If CER bits 0, I, or 2 = I, record the
contents of CER and AER. See the FSE
section for error code 55nn.

FRUS
FRUI2I
FRU1l8
FRU1l7
FRU1l5
FRU1l4
FRUI20
FRU1l9
FRU1l6
FRU134
FRU135
FRU157
FRUI58
FRU159
FRU139

ERROR DISPLAYS
nnnnnn
ERA = ra, ERB = rb
PSR = rr, PER = pp
MTI = mm, MOl = md
HOT BITS XR BUS = aa
XRA EXP = ex, ACT=ac

nnnnnn
**
ra
rb
rr
pp
mm
md
aa
ac
ex

(This screen is
explained on 01
MACHINE FAILURES MAY
CAUSE CURRENT ERROR
DATA TO BE INVALID.
SEE DIAG 1 "VERIFY".

Failure 10
No errors were set
Contents of error register A
Contents of error register B
Contents of the processor status register
Contents of the processor error register
Contents of the maintenance tag in register.
Contents of the users active register
Result of ANDing data from registers on the XR bus.
Actual data in external register address register
Expected data in external register address register.

nnnnnn
PSR = rr, PER = pp
MTI = mm, OSE = ds
RER = re, RSR = rs

BCSE=bc, BOSE = bd
WSE = ww, CER = ce
A CAE = aa,B CAE~ bb
C CAE = cC,D CAE= dd
~.

nnnnnn
**
rr
pp
mm
ds
re
rs
bc
bd
ww
ce
aa
bb
cc
dd

Failure 10
No errors were set
Contents of the processor status register
Contents of the processor error register
Contents of the maintenance tag in register.
Contents of the device status/error register.
Contents of the read error register
Contents of the read status register
Contents of the buffer channel status and error register
Contents of the buffer device status and error register
Contents of the write status/error register
Contents of the channel error register
Channel adapter A errors if CER bit 4 = 1
Channel adapter B errors if eER bit 5 = 1
Channel adapter C errors if CER bit 6 = 1
Channel adapter 0 errors if CER bit 7 = 1

An XR address parity error was forced, but the MIl did not
contain MTI FRU I, indicating that the error was not detected.

EC336396

C. Cop\,nyhllBM Corp

1984. lttu~l l'kit! I~JUI

Routine EE85 (Continued)

DIAG 410

External Register Bus Addressing and Data Pattern Test - Routine EE85 (Continued)

Routine EE85 (Continued)

DIAG 412

Tests 3, 4, and 5 Error Displays

FAILURE ID

DESCRIPTION

ADDITIONAL ACTIONS

FRUS
FRUl2l
FRU118
FRU117
FRU115
FRU114
FRU120
FRU1l9
FRU116
FRU134
FRU135
FRU157
FRU158
FRU159
FRU139

XB502C

An error occurred while testing register zzzz.

XB502D

An error occurred while testing register zzzz.

To help in problem isolation, also run
diagnostics EE10, EE30, EE40, EE50, EE60
EE90, and EEAO.

XB502E

A failure occurred while using an invalid address.

1.

An error is expected; see PSR, PER, and XRA registers.
If the actual and expected values are the same for those
registers, the error is indicated.
----------~-------------------------------------------------------

Remove the IML diskette, then press the
IML switch to cause a power-on-reset.
Run routine EE85 again.

2.

If the value of ERA or ERB is other
than 0, see the FSI section for error
code E100. Also see action number 4
of this Additional Actions column.

3.

If PSR bit 0
code Fnnn.

4.

If a diagnostic failure occurs and no
errors are detected by the hardware,
see the FSI section for error code
E100 and perform the procedures for
the microprocessor and control
storage.

5.

XR errors (PSR bit 0 = 1) can cause
ERA and ERB errors. Use diagnostic
EE85 to check the ERA and ERB
registers.

=

ERROR DISPLAYS

nnnnnn
REG = zzzz
XRT = ff
WR=yy.
RD

=

aa

~TI

ERA " ra,
PSR = xx,
PER = pp,
XRA = za,

ERB
EXP
EXP
EXP

=
=
=

xy
py
zy

MTI
MOl

EXP
EXP

=
=

ty
dy

I, see EAD 1 for error
=
=

ti,
di ,

MACHINE FAILURES MAY
CAUSE CURRENT ERROR
DATA TO BE INVALID.
SEE DIAG 1 "VERIFY".
(This screen is
explained on DIAG 6.)
nnnnnn Failure 10
zzzz
Mnemonic of the failing external register
ff
External register table at first error (program flags)
yy
Data written to the register
aa
Data read from the register
ra
Contents of error register A
** = No errors were set
rb
Contents of error register B
xx
Actual contents of the processor stdtus register
xy
Expected contents of the processor status register
pp
Actual contents of the processor error register
py
Expected contents of the processor error register
za
Actual contents of the external register address
register
zy
Expected contents of the externdl register address
register
ti
Actual contents of the maintenance tag in register
ty
Expected contents of the maintenance tdg in register
di
Actual contents of the users active register
dy
Expected contents of the users active register

---------------------------------------------------------------

3480

EC336396

Routine EE85 (Continued)

,~, COPY"Ql1t Ill'" Corp. 1984, 1985, 1986. 1987

,

~ )'
..

.'.

tl

'-j
l". .

DIAG 412

o

c

c

o

o

Status Store Write/Read RAM Storage Test - Routine EE92
Prerequisite diagnostics must run without failure before this
diagnostic Is run. See DIAG 3, "PREREQUISITE DIAGNOSTICS."
This routine writes each of the sixteen offset bytes in the sixteen
status store pages. The routine tests the status store RAM as
follows:
1.

It issues a command to write a status store page with a data

pattern and increments the (l!bet in the page until all sixteen
offset bytes have been written.
2.

3.

It issues a command to read the page of storage that was
just written. The read data and write data is then compared.
When all sixteen pages have been written, the data pattern is
changed and steps 1 and 2 are repeated.

o

o

o

o

o

Routine EE92

DIAG 450

Routine EE92

DIAG 450

Error Displays
When an error is detected by the diagnostic program, the
maintenance device displays error information on Its
keyboard/display. The first screen displays automatically. You
can see the second and following screens by pressing the ENTER
key on the keyboard/display,
The format of the display's first line Is the same for all detected
errors. The remaining three lines contain additional Information
about the failure.
External registers are defined in the OF (Data Fields) section of
this maintenance information.

FRUS

Note: The default data patterns are Hex AA, 55, FF, and 00.

Routine Start Address: 2010

See CARR-CU or CARR-DR, pages 1-1, 1-2, 1-3, and 1-4 for the
names and locations of the FRUs.

Error Loop: If no error occurs, the routine loops as if "LOOP
ROUTINE" is set. When an error is detected, the routine saves
the error information and displays the error on the MD. After the
error is displayed, the routine continues to loop on that error.
However, if a different error occurs, that new error is displayed
on the MD, and the routine will loop on the new error.

Pattern Entry Display
The data pattern written into status store can be altered by
entering the pattern when the following screen displays.

DIAG=(EE92)-ENTER:
PATTERN
ttii

ttll

Test data

Press the MD ENTER key to run the default data patterns.
or
Enter a pattern. Two bytes can be entered; the first byte (tt) must
be FF to alert the routine that the default patterns are not being
used. The second byte (ii) is the data pattern that will be written.
Valid patterns are FFoo-FFFF.

3480
EC336396
© COPYlIght 10M Corp. 1984, 1985.

1986, 1987

Status Store Write/Read RAM Storage Test - Routine EE92 (Continued)
FAILURE ID

DESCRI PTION

ADDITIONAL ACTIONS
1.

FOLLOW STEPS 1 AND 2 BEFORE TAKING ANY OTHER ACTIONS:
2.
SS2021

Routine EE92 (Continued)

A timeout occurred while trying to write in status store.

DIAG 452

ERROR DISPLAYS

FRUS

If the value of ERA or ERB is other than 00, see
the FSI section for error code E100.
If PSR bit 0 = 1, see EAD 1 for error code Fnnn.
See the FSI section for error code 53B2.

No hardware errors were detected for this error.

FRU121
FRU122
FRU133
FRU152
FRU195
FRU196
FRU134

SS2021
SS TIMEOUT OCCURRED
DURING THE WRITE FOR
PAGE x OFFSET y
x = Status store page
y = Offset of the storage location

SS2022

A timeout occurred while trying to read a location in
status store.

See the FSI section for error code 53BO.

No hardware errors were detected for this error.

SS2023

The data read from the status store RAM did not match the
data written.

See the FSI section for error code 53B3.

No hardware errors were detected for this error.

FRU121
FRU122
FRU133
FRU152
FRU195
FRU196
FRU134

SS2022
SS TIMEOUT OCCURRED
DURING THE READ FOR
PAGE x OFFSET y
x = Status store page
y = Offset of the storage location

FRU121
FRU122
FRU133
FRU152
FRU195
FRU196
FRU134

SS2023
DATA NOT AS EXPECTED
PAGE x OFFSET Y
WRITE = zz READ = ww
x = Status store page
y = Offset of the storage location

SS2024

The status store write/read was completed successfully;
however, a hardware error was detected.

See the FSI section for error code 5900.

The registers that were checked for errors are displayed.

If ERA and ERB are not 0, record the contents
of ERA and ERB and see the FSI section for error
code ElOO.
If PSR bit 0 = I, record the contents of PSR, PER,
XRA, MTI, and MOl. See EAD 1 for error code Fnnn.
If CER bits 0, I, 2, or 3 = I, record the
contents of CER. See the FSI section for error
code 55nn.

3480

FRU121
FRU122
FRU134

SS2024
ERROR: CER=cc PSR=rr
PER=pp ERA=ra ERB=rb
XRA=xx MTI=mm MDI=md
cc
rr
pp
ra
rb
xx
mm
md

EC336396

()

= Contents
= Contents
= Contents
= Contents
= Contents
= Contents
= Contents
= Contents

of
of
of
of
of
of
of
of

channel error register
the processor status re~ister
the processor error register
error register A
error register B
the external register address register
the maintenance 'tag in' register
the users active register

Routine EE92 (Continued)

~ CopYright tBM Corp. 1984, 1985. 1986. 1987

~.)

zz = Write data
ww = Read data

()

o

~)

DIAG 452

o

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o

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o

o

Status Store WriteiRead RAM Storage Test - Routine EE92 (Continued)
DESCRIPTION

FAILURE ID

ADDITIONAL ACTIONS
1.

FOLLOW STEPS 1 AND 2 BEFORE TAKING ANY OTHER ACTIONS:
2.
S$2025

Routine EE92 (Continued)
FRUS

The data read from status store RAM did not match the
data written.

See the FSI section for error code 53B3.

A hardware error was detected and the contents of the
registers that were checked are displayed.

If ERA and ERB are not 0, record the contents
of ERA and ERB and see the FSI section for error
code El00.

FRU121
FRU122
FRU133
FRU152
FRU195
FRU196
FRU134

If CER bits 0, 1, 2, or 3 = 1, record the
contents of CER. See the FSI section for error
code 55nn.

A timeout occurred whi Ie trying to write in status store.
A hardware error was detected and the contents of the
registers that were checked are displayed on an
additional error screen.

If ERA and ERB are not 0, record the contents
of ERA and ERB and see the FSI section for error
code El00.
If PSR bit 0 = 1, record the contents of PSR, PER,
XRA, MTI, and MDI. See EAD 1 for error code Fnnn.

SS2025
DATA NOT AS EXPECTED
PAGE x OFFSET Y
WRITE = zz READ = ww
x
y
zz
cc
rr
pp
ra
rb
xx
mm
md

FRU121
FRU122
FRU133
FRU152
FRU195
FRU196
FRU134

See the FSI section for error code 53B2.

x
y
cc
rr
pp
ra
rb
xx

A hardware error was detected and the contents of the
registers checked are displayed on an additional error
screen.

If ERA and ERB are not 0, record the contents
of ERA and ERB and see the FSI section for error
code El00.
If PSR bit 0 = 1, record the contents of PSR, PER,
XRA, MTI, and MDI. See EAD 1 for error code Fnnn.
If CER bits 0, 1, 2, or 3 = 1, record the
contents of CER. See the FSI section for error
code 55nn.
See the FSI section for error code 53BO.

FRU121
FRU122
FRU133
FRU152
FRU195
FRU196
FRU134

mm
md

3480 MI
« Copyr,gh'

EC336395

IBM Corp. 1984. 1985

HARDWARE REGISTERS
ERROR: CER=cc PSR=rr
PER=pp ERA=ra ERB=rb
XRA=xx MTI=mm MDI=md

Status store page
Offset of the storage location
Contents of the channel error register
Contents of the processor status register
Contents of the processor error register
Contents of error register A
Contents of error register B
Contents of the external register address
register
Contents of the maintenance 'tag in' register
Contents of the user's active register
SS2027
SS TIMEOUT OCCURRED
DURING THE READ FOR
PAGE x OFFSET Y

x
y
cc
rr
pp
ra
rb
xx

HARDWARE REGISTERS
ERROR: CER=cc PSR=rr
PER=pp ERA=ra ERB=rb
XRA~xx MTI=mm MDI=md

Status store page
Offset of the storage location
Write data
Read data
Contents of the channel error register
Contents of the processor status register
Contents of the processor error register
Contents of error register A
Contents of error register B
Contents of the external register address register
Contents of the maintenance 'tag in' register
Contents of the user's active register
SS2026
SS TIMEOUT OCCURRED
DURING THE WRITE FOR
PAGE x OFFSET Y

mm
md
A timeout occurred whi Ie trying to read from status store.

DIAG 454

ERROR DISPLAYS

ww

If CER bits 0, 1, 2, or 3 = 1, record the
contents of CER. See the FSI section for error
code 55nn.

SS2027

o

I f the va I ue of ERA or ERB is other than 00, see
the FSI section for error code El00.
If PSR bit 0 = 1, see EAD 1 for error code Fnnn.

If PSR bit 0 = 1, record the contents of PSR, PER,
XRA, MTI, and MDI. See EAD 1 for error code Fnnn.

SS2026

o

HARDWARE REGISTERS
ERROR: CER=cc PSR=rr
PER=pp ERA=ra ERB=rb
XRA=xx MTI=mm MDI=md

Status store page
Offset of the storage location
Contents of the channel error register
Contents of the processor'status register
Contents of the processor error register
Contents of error register A
Contents of error register B
Contents of the external register address
register
Contents of the maintenance 'tag in' register
Contents of the user's active register

Routine EE92 (eontinued)

DIAG 454

Routine EE93

Status Store Order Test - Routine EE93
Prerequisite diagnostics must run without failure before
this diagnostic is run. See DIAG 3, "PREREQUISITE
DIAGNOSTICS."
This routine tests to see if the subsystem is in a dual control unit
configuration. If it is, the routine issues a Reset Dual Control
Unit Connection before starting the orders test. The orders test
consists of the following:

FOLLOW STEPS 1 AND 2 BEFORE
TAKING ANY OTHER ACTIONS:

Note: Dual control unit order '4A' (Set Dual Controller
Connect) is not issued by this routine.
Routine Stert Address:

A timeout occurred whi Ie trying to determine
the type of subsystem being tested; single
or dual control unit.

See the FSI section for error code 5360.

SS3022

A timeout occurred whi Ie trying to get
status store to disconnect from the second
control unit before running the status store
orders test.

See the FSI section for error code 5360.

SS3023

A timeout occurred whi Ie trying to issue a
status store order for a single control
unit status store.

See the FSI section for error code 5310.

SS3024

A timeout occurred whi Ie trying to issue a
status store order for a dual control unit
status store.

FRU121
FRU117

SS3022
SS TIMEOUT OCCURRED
WHILE DISCONNECTING
THE 2ND CONTROL UNIT

FRU121
FRU117

SS3023
A TIMEOUT OCCURRED
FOR STATUS STORE
ORDER = xx

See the FSI section for error code 5310.

FRU121
FRU117

SS3025

The channel request register bit 5 was not
reset as expected when issuing the Reset
Message Buffer order.

See the FSI section for error code 5311.

FRU121
FRU 117

No hardware errors were detected for this
error.

FRUS

No hardware errors were detected for this
error.

SS3026

SS3027

The response returned from status store when
issuing the acknowledge message indicated
that the control units are still connected.
No hardware errors were detected for this
error.

See the FSI section for error code 5341.

See the FSI section for error code 5342.

FRU121
FRU 117

FRUI21
FRU 117

Status store order
that was issued
SS3024
A TIMEOUT OCCURRED
FOR STATUS STORE
ORDER = xx

xx

External registers are defined in the OF (Data Fields) section of
this maintenance information.

3480 MI

SS3021
SS TIMEOUT OCCURRED
WHILE TRYING TO READ
FEATURE INFORMATION

No hardware errors were detected for this
error.

The response returned from status store when
issuing a Read Message Buffer order
indicates that the Reset Message Buffer
order was not successful.

See CARR-CU or CARR-DR, pages 1-1,1-2,1-3, and 1-4 for
the names and locations of the FRUs.

FRU121
FRU117

xx

Error Displays

The format of the display's first line is the same for all detected
errors. The remaining three lines contain additional information
about the failure.

ERROR DISPLAYS

No hardware errors were detected for this
error.

Error Loop:

When an error is detected by the diagnostic program, the
maintenance device displays error information on its
keyboard/display. The first screen displays automatically. You
can see the second and following screens by pressing the
ENTER key on the keyboard/display.

FRUS

If the value of ERA or ERB is other than 00, see the FSI
section for error code El00.
If PSR bit 0 = 1 , see EAD 1 for error code Fnnn.

SS3021

3010

If no error occurs, the routine loops as if "LOOP
ROUTINE" is set. When an error is detected, the routine saves
the error information and displays the error on the MD. After
the error is displayed, the routine continues to loop on that error.
However, if a different error occurs, that new error is displayed
on the MD, and the routine will loop on the new error.

1.

2.

1. The routine issues status store orders that are valid for a
single control unit and tests a correct response from status
store.
2. The routine tests to see if this is a dual control unit
configuration, and if it is, the routine issues status store
orders that are valid for a dual control unit and checks the
response from status store.

ADDITIONAL ACT! ONS

DESCRIPTION

FAILURE 10

Status store order
that was issued
SS3025
THE RECEIVED BIT(5)
NOT RESET FOR ORDER
RESET READ MSG BUFF

SS3026
RESPONSE TO ACCESS
READ MSG BUFF SHOWS
RESET READ NOT GOOD

SS3027
THE ACKNOWLEDGE MSG.
RESPONSE I NO I CATES
CU'S ARE CONNECT~D

Routine EE93

EC336395

~ Copyrighl18M Ccwp. 1984, 1985

f)

DIAG 460

DIAG 460

o

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o

o

o

o

Status Store Order Test - Routine EE93 (Continued)
FAILURE ID

Routine EE93 (Continued)
ADDITIONAL ACTIONS

DESCRIPTION
I.
FOLLOW STEPS I AND 2 BEFORE TAKING ANY OTHER ACTIONS:
2.

SS3028

The status store order completed successfully, but a
hardware error was detected.

FRUS

If the value of ERA or ERB is other than 00, see the FSI
section for error code El00.
If PSR bit 0 = I, see the EAD 1 for error code Fnnn.
If ERA and ERB are not 0, record the contents
of ERA and ERB and see the FSI section for error
code EIOO.

FRU121
FRU117

If eER bits 0, 1, 2, or 3 = 1, record the contents of
CER. See the FSI section for error code 55nn.

SS3028
ERROR: CER=cc PSR=rr
PER=pp ERA=ra ERB=rb
XRA=xx MTI=mm MDI=md
cc
rr
pp
ra
rb
xx

See the FSI section for error code 5310.

mm
md
A timeout occurred whi Ie trying to issue a status store
order for a single control unit status store.

If ERA and ERB are not 0, record the contents
of ERA and ERB and see the FSI section for error
code El00.

A hardware error was detected and the contents of the
registers checked are displayed on an additional error
screen.

If PSR bit 0 = I, record the contents of PSR, PER,
XRA, MTI, and MDI. See EAD 1 for error code Fnnn.

If eER bits 0, " 2, or 3 = " record the contents of
CER. See the FSI section for error code 55nn.
See the FSI section for error code 5310.

FRU121
FRU 117
FRUI22
FRUI18
FRUI15
FRUI14
FRUI20
FRU 119
FRUI16
FRUI34
FRUI35
FRUI57
FRUI58
FRU159
FRUI39

A timeout occurred whi Ie trying to issue a status store
order for a dual control unit status store.

If ERA and ERB are not 0, record the contents
of ERA and ERB and see the FSI section for error
code EIOO.

A hardware error was detected and the contents of the
registers checked are displayed on an additional error
screen.

If PSR bit 0 = I, record the contents of PSR, PER,
XRA, MTI, and MDI. See EAD 1 for error code Fnnn.
If CER bits 0, "

CER.

2, or 3 = " record the contents of

See the FSI section for error code 55nn.

See the FSI section for error code 5310.

yy
cc
rr
pp
ra
rb
xx

FRU121
FRU 117

3480 MI

EC336395

IBM C",p. 1984 1985

of
of
of
of
of
of

the channel error register
the processor status register
the processor error register
error register A
error register B
the external register address

of the maintenance 'tag in' register
of the user's active register

yy
cc
rr
pp
ra
rb
xx

HARDWARE REGISTERS
ERROR: CER=cc PSR=rr
PER=pp ERA=ra ERB=rb
XRA=xx MTI=mm MDI=md

Status store order issued
Contents of the channel error register
Contents of the processor status register
Contents of the processor error register
Contents of error register A
Contents of error register B
Contents of the external register address
register
Contents of the maintenance 'tag in' register
Contents of the user's active register

SS302A
TIMEOUT OCCURRED FOR
DUAL STATUS STORE
ORDER = yy

mm
md

« Copyr'ght

Contents
Contents
Contents
Contents
Contents
Contents
register
Contents
Contents

SS3029
A TIMEOUT OCCURRED
FOR STATUS STORE
ORDER = yy

mm
md
SS302A

DIAG 462

ERROR DISPLAYS

If PSR bit 0 = I, record the contents of PSR, PER,
XRA, MTI, and MDI. See EAD I for error code Fnnn.

SS3029

o

o

o

HARDWARE REGISTERS
ERROR: CER=cc PSR=rr
PER=pp ERA=ra ERB=rb
XRA=xx MTI=mm MDI=md

Status store order issued
Contents of the channel error register
Contents of the processor status register
Contents of the processor error register
Contents of error register A
Contents of error register B
Contents of the external register address
register
Contents of the maintenance 'tag in' register
Contents of the user's active register

Routine EE93 (Continued)

DIAG 462

Basic Tape Motion Test - Routine EEA2
Prerequisite diagnostics must run without failure before
this diagnostic is run. See DIAG 3, "PREREQUISITE
DIAGNOSTICS ...
This routine contains two tests that exercise a single drive. The
serial and parallel drive interconnections are used to verify
correct operation of the Test I/O and Read Forward commands.
There is no data transfer when the Read Forward command is
tested.
Routine Start Address:

2010

Error Loop: If no error occurs, the routine loops as if "LOOP
ROUTINE" is set. When an error is detected, the routine saves
the error information and displays the error on the MD. After
the error is displayed, the routine continues to loop on that error.
However, if a different error occurs, that new error is displayed
on the MD, and the routine will loop on the new error.

Routine EEA2
4.

Enter the pattern. Valid parameters are 0200, or 0000.
Entering 0200 causes tests 1 and 2 to loop until you press
the PF key. Entering 0000 causes tests 1 and 2 to run one
time.

Error Displays
When an error is detected by the diagnostic program, the
maintenance device displays error information on its
keyboard/display. The first screen displays automatically. You
can see the second and following screens by pressing the
ENTER key on the keyboard/display.

Bit 2

This bit indicates the drive just changed from not
ready to ready. This is usually a normal condition. If
this is one of the error bits, see the FSI section for
error code 33E8.

Bit 3

This bit indicates that the drive has moved a
predetermined amount of tape and is notifying the
control unit. This is usually a normal condition. This
bit is not checked by routine EEA2.

Bit 4

The format of the display's first line is the same for all detected
errors. The remaining three lines contain additional information
about the failure.
External registers are defined in the DF (Data Fields) section of
this maintenance information.

Bit 5

Tests
FRUS
See CARR-CU or CARR-DR, pages 1-1,1-2,1-3, and 1-4 for
the names and locations of the FRUs.

This test initializes the routine and checks for active level 3
through level 6 interrupts.

Error Analysis

Test 2
This test checks to ensure that the correct drive address has
been entered. Once the address has been verified as correct, a
Sense command is issued to test correct execution of the
command. Finally, Serial Test I/O and Serial Read commands
are issued to test drive repositioning and drive interrupt
operations.

Analyze errors for routine EEA2 as follows:
1.

2.
3.

Test Selection

From the first error information screen record the key
number, the drive address, and the serial and parallel
commands.
Read the error message on the first error information screen
and perform any action indicated.
Take the actual drive status (tttt) and the expected drive
status (ssss) and convert them to binary. Example:

8621

The following screen displays after routine number EEA2 has
been entered to invoke the tape motion diagnostic routine.

tt i i

(xx)

Bit 0

Drive address
Test data

Bit 1

To run the tests:
1.
2.

Insert a scratch tape that is not file protected.
Enter the drive address (valid parameters are O-F, or

OO-OFI.
3.

Use the ENTER key to move the cursor under PATTERN
(ttii).

3480 MI
e

=

This bit indicates that a serial command was issued
since the last parallel command. This bit will only be
on in the next status received by the control unit. If
this is one of the error bits, see the FSI section for
error code 9602.
This bit indicates that the drive is repositioning after a
previous serial or parallel command. Repositioning
can be indicated over either the serial or the parallel
interconnections, and should always indicate the
real-time operation of the drive, so both indicators
should always indicate the same condition. If this is
one of the error bits, see the FSI section for error
code 8804.

Bit 12

This bit indicates that the drive tape volume is file
protected. If this is one of the error bits, see the FSI
section for error code CK07.

Bit 13

This bit indicates that the drive is positioned at or
following the logical end of tape. If this is one of the
error bits, replace FRU085*.
See EAD 1, "Drive Interconnections" for failure
isolation.

Bit 14

This bit indicates the drive set drive unit check and
sense data is present in the drive. Normally, the
sense data is valid and is displayed in a later error
information screen. Analyze this bit last.

This bit indicates that the drive is positioned at the
physical end of tape. If this is one of the error bits,
replace FRU085 *.
See EAD 1, "Drive Interconnections" for failure
isolation.

Bit 15

*

Reserved

This FRU is EC sensitive.

Bit 7

This bit indicates that the tape installed in the drive
has been manually unloaded using the Rewind/Unload
switch. If this is one of the error bits, see the FSI
section for error code 8202.

Bit 8

This bit indicates that the drive address is one with an
address in the range 8-F. If this is one of the error
bits, see the FSI section for error code 86CO.

Bit 9

This bit indicates that the drive has completed a tape
volume mount and is ready. If the drive is not really
ready, you must make it ready. If this is one of the
error bits, see the FSI section for error code 33E8.

Bit 10

This bit indicates that the drive has received patches
from the control unit. Normally during this
diagnostic, this bit is not active; however, if the
functional microcode has previously sent patches and
the drive has not been powered off or a reset has not
been issued, this bit may be on. This bit is not
checked.

Routine EEA2

EC336395

Copyright IBM Corp. 198<4, 1985, 1986

:)

~)

~)

.. )

~J

See CARR-DR 4.

See EAD 1, "Drive Interconnections" for failure
isolation.

1000 0110 0010 0001

The bits are numbered 0-15, left to right. Compare the actual
to expected drive status, and analyze bits that do not match.

DIAG=(EEA2)-ENTER:
DRIVE
PATTERN

xx
ttii

Bit 6

This bit indicates that the drive is positioned at the
beginning of tape. See EAD 1, "Drive
Interconnections" for failure isolation.

This bit indicates that the drive just completed a
connected command. If this is one of the error bits,
replace FRU085*.
See EAD 1, "Drive Interconnections" for failure
isolation.

Test 1

Bit 11

This bit indicates that the drive just completed a
disconnected command. If this is one of the error
bits, replace FRU085*.
See EAD 1, "Drive Interconnections" for failure
isolation.

DIAG 500

J

~)

~)
i..",

~}

DIAG 500
~
:~

j

c

o

o

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o

o

Error Analysis (Continued'.
Analyze the errors for routine EEA2 as follows:
1.

Record all information on the error screens.

2.

If ERA and ERB are not 0, record the contents (if the screen
is displayed) of ERA and ERB. See the FSI section for error
code E 100 and the following FRU list:

5.

FRU Name
114
120
112
113
111
119
118
116
134
117

FRU Name
117
115
114
118
121
119
116
120
122
134
135

Microprocessor card
Maintenance adapter card
Buffer control card
Drive-adapter card
Status store basic card
Read clock and format card
Write data card
Buffer adapter card
Status store communication card
Control store card
Control storage array card

If BOSE channel error groups 0-3 indicate any errors, record
the contents of BOSE. See the FSI section for error code
D6nn and the following FRU list:

6.

o

o

o

o

Routine EEA2

Diag 501

Routine EEA2

Diag 501

Notes:
1.

EC sensitive FRU, see CARR-DR 4.

2.

EC sensitive FRU, see CARR-CU 7.

Buffer control card
Buffer adapter card
Buffer storage card (See note 2)
Buffer storage card (See note 2)
Read ECC/CORR card
Read clock and format card
Drive-adapter card
Write data card
Control store card
Microprosessor card

If DSE bits 0, 1, or 2 = 1, record the contents of DCB,
OCR, DSE, DIR, and DTR. See the FSI section for error
code D4nn and the following FRU list:
FRU Name

3.

If PSR bit 0 = 1 , record the contents (if the screen is
displayed) of PSR, PER, XRA, MTI. and MOl. See EAD 1 for
error code Fnnn and the following FRU list:

118
116
134
085

FRU Name
118
117
115
114
121
119
116
120
122
4.

Drive-adapter card
Microprocessor card
Maintenance adapter card
Buffer control card
Status store basic card
Read clock and format card
Write data card
Buffer adapter card
Status store communication card

7.

064
062
085
132
131
130
123
124
125
119
111

FRU Name

3480

Buffer control card
Buffer adapter card
Buffer storage card (See note 2)
Buffer storage card (See note 2)
Channel adapter card (channel A)
Bus shoe card (channel A)
Channel adapter card (channel BI
Bus shoe card (channel CI
Channel adapter card (channel C)
Bus shoe card (channel CI
Channel adapter card (channel D)
Bus shoe card (channel D)
Read clock and format card
Drive-adapter card
Write data card
Power/PaR card
Control store card
Status store basic card
Status store communication card

EC336395

(, Copynght IBM Corp 1984, 1985, 1986

If any RER bits = 1, or if RSR bits 5, 6, 7 = 1, record the
contents of RCR, RRC, RER, RSR, and ROC. See the FSI
section for error code D8nn and the following FRU list:
FRU Name

If BCSE channel error groups 0-3 indicate any errors, record
the contents of BCSE. See the FSI section for error code
D5nn and the following FRU list:

114
120
112
113
133
136
152
233
195
235
196
237
119
118
116
126
134
121
122

Drive-adapter card
Write data card
Control store card
Drive control card (See note 1I

8.

Write power card
Read preamplifier card (See note 1I
Drive control card (See note 1)
Read detect card 3
Read detect card 2
Read detect card 1
Read skew buffer card 1
Read skew buffer card 2
Read skew buffer card 3
Read clock and format card
Read ECC/CORR card

If WSE bits 4, 5, or 6 = 1, record the contents of WCR and
WSE. See the FSI section for error code D7nn and the
following FRU list:
FRU Name
116
120
114
117
118
139

9.

Write data card
Buffer adapter card
Buffer control card
Microprocessor card
Drive-adapter card
Logic board A 1

Record the contents of drive sense. See the last display
screen under Error Displays for this routine for an
explanation of the drive sense bytes.

Routine EEA2 (Continued)

Basic Tape Motion Test - Routine EEA2 (Continued)

DIAG 502

ERROR DISPLAYS FOR ROUTINE EEA2
ERROR MESSAGES:
MAKE THE DRIVE READY

£~D=SER-x,PARALL-.~Y

--*Error messages--*

Data is not Valid
nnnnnn Fai lure 10
xxxx
Sequence code for the error.
Sequence codes are:
0000 Initialization and active interrupt test.
0002 Issue an initial sense to assure that
drive is in a known state.
0003 Assure that there are no pending drive
alerts for the drive being tested.
0005 The drive is at end of tape (EOT). A
rewind is issued to the drive.
0006 Issue a serial read forward command.
0008 During Key 0006 the drive is not
repositioning, which indicates that the
drive is accelerating towards 95 percent
velocity in preparation for setting 'gap
in'. Repeatedly issue a serial Test I/O
command unti I the drive sets repositioning. Repositioning occurs when the drive
reaches the 'gap in' point.
0009 During Key 0006 the drive is not repositioning. Key 0008 is completed with
repOSitioning set. Assure that the drive
does not set an alert.
0010 During Key 0006 the drive is not repositioning. Key 0008 is completed with
repositioning set. Key 0009 is completed
successfully. The drive should set an
alert, which indicates that it is back in
read forward stop lock.
0011 During Key 0006 the drive is not repositioning, which indicates that the drive
is not at read forward stoplock but is
moving towards read forward stop lock.
The drive should set an alert when it
reaches read forward stop lock.
0012 During Key 0006 the drive is not repositioning. Key 0011 either received an
alert or timed out.
Invoke a serial Test
I/O command and check for errors.
0013 During Key 0006 the drive is not repositioning. Key 0011 either received an
alert or timed out. Key 12 did not find
any errors.
Issue a serial Read Forward
command, and if repositioning is not on,
go to Key 0006.
0014 Key 10 has completed successfully. Perform
paral leI test I/O and check the drive status.
xx
Orive address
x
Last serial command issued
yy
Last parallel command issued

3480 MI

RCR
RER
ROC
WCR

Load the drive with a write
enabled tape.
OR STS FILE PROT = The drive should be set to write
enable (not fi Ie protect).

nnnnnn
KEY = xxxx,DR = xx

r

- - - - - - - - - - - - - - - - - - - - - - - - - -

"-

- - -

No error
Contents
Contents
Contents
Contents
Contents
register
wc Contents
ws Contents
- - - - rc
cr
re
rs
rd

DRSTS=tttt,EXP=ssss
ERA=ra, ERB=rb
PSR=rr,PER=pp,XRA=aa
MTI=mm,MDI=md,
*
tttt
ssss
ra
rb
rr
pp
aa
mm
md

No error is stored
Actual drive status
Expected drive status
Contents of error register A
Contents of error register B
Contents of the processor status register
Contents of the processor error register
Contents of the external register address
register
Contents of the maintenance tag in
register
Contents of the user s active register

a
b
C

d
e
f
g
h
j
cb
dc
ds
di
dt

b2
b4b5

abcde
fghij,OCB= cb
dc, OSE
ds
di
OTR = dt

No error is set
Buffer channel status and error
register bits 0-3
BCSE channel error group 0
BCSE channel error group 1
BCSE channel error group 2
BCSE channel error group 3
Buffer device status and error
register bits 0-3
BOSE device error group 0
BOSE device error group 1
BOSE device error group 2
BOSE device error group 3
Contents of the device control bus register
Contents of the device control register
Contents of the device status/error register
Contents of the device interrupt register
Contents of the device tag register

b6b7

21
2223

WSE

ws

read
read
read
read
read

control register
residual count register
error register
status register
diagnostic control

of the wr i te control register
of the wr i te status/error register
- - - - - - - - - - - - - - - - -

-

Contents of the drive error recovery byte
(see sense byte 8).
The contents of the drive features byte
(see sense byte 19).
Flags modifier to b4b5 (see sense byte 18).
The first error the drive detected. B4
contains the drive command associated with
this error, an EE to indicate a bus out
parity error whi Ie loading a command, or
an FF to indicate that the error occurred
when the drive was not performing a
command. B5 contains the drive error code
identifying this error (see sense bytes
20 and 21).
The last error the drive detected. B6
contains the drive command associated with
this error, an EE to indicate a bus out
parity error whi Ie loading a command, or
an FF to indicate that the error occurred
when the drive was not performing a
command. B7 contains the drive error code
identifying this error (see sense bytes
22 and 23).
Logical drive address and physical drive
address (contents of the thumbwheel switches).
See sense byte 30.
The drive EC level (contains the last four
digits of the drive ROS module EC level).

-----------------------~

Routine EEA2 (Continued)

EC336395

~ COPYright IBM Corp_ 19B4, 1985

,)

set
the
the
the
the
the

cr
rs

The following sense data is described in the
SENSE section (see formats 19 and 20).

b1

.

is
of
of
of
of
of

RRC
RSR

ORSNS- S8=bO,SI9=bl
s18= b2, S2021= b4b5
S2223= b6b7
S30= 21,
EC= 2223

bO

BCSE=
BDSE=
OCR
OIR =

re,
re,
rd,
wc,

~--)

:)

"

"

)-

t)

DIAG 502

c

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Notes

3480

EC336396

c

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(;
Notes

DIAG 503

Notes

DIAG 503

Routine EEA2 (Continued)

Basic Tape Motion Test - Routine EEA2 (Continued)
FAILURE ID

ADD I TI ONAL ACTIONS

DESCRIPTION
1.

FOLLOW STEPS I AND 2 BEFORE TAKING ANY OTHER ACTIONS:
2.

See "Error Analysis" on DIAG 500.

LVL 4 INTRPT ACTIVE
Level 4 interrupt is active following a reset.

See "Error Analysis" on DIAG 500.

LVL 5 I NTRPT ACTI VE
Level 5 interrupt is active following a reset.

See "Error Analysis" on DIAG 500.

TM2024

During execution of a drive diagnose command, an error occurred.

See "Error Analysis" on DIAG 500.

TM2025

DR ADDR NOT VALID
The drive address is not valid.

See "Test Selection" on DIAG 500.

TM2022

TM2023

Valid addresses are 0 through F.

ERROR DISPLAY
See the "Error Displays"
on DIAG 502.

If the value of ERA or ERB is other than 00, see the FSI
section for error code E100.
If PSR bit 0 = I, see EAD 1 for error code Fnnn.

LVL 3 INTRPT ACTIVE
Level 3 interrupt is active following a reset.

TM2021

FRUS

DIAG 504

FRU 119
FRU 117

See the FSI section for error code 1103.
FRU120
FRUI17

See the FSI section for error code 1104.
FRU120
FRU 117

See the FSI section for error code 1105.

See EAD I, "Drive Interconnections. "

Re-enter the drive address from the test selection option screen.
SNS CMD TIMED OUT
Sense time out. A Sense command issued to the drive did not
complete.

See "Error Analysis " on DIAG 500.

TIO CMD TIMED OUT
Test I/O time out. A Test I/O command issued to the drive did not
complete.

See "Error Analysis " on DIAG 500.

TM2028

SERIAL TIME OUT 8803
Serial time out. A serial command has been issued but the control
unit did not complete the operation.

See "Error Analysis" on DIAG 500.
See the FSI section for error code 8803.
See EAD I, "Dr i ve Interconnections. "

FRU085 1
FRU 118

TM2029

DR REPO ERROR 8804
Whi Ie preparing to issue a serial command, repositioning response
was active. The error could be caused by the drive being tested,
or another drive, or by an invalid response from the control un it.

See "Error Analysis" on DIAG 500.
See the FSI section for error code 8804.
See EAD I, "Drive Interconnections."

FRU085 1
FRU 118

TM202A

DR ALERT ON
Drive alert error. A Sense command has just completed successfully,
which should have reset any alert present. However, a drive alert
was detected.

See "Error Analysis" on DIAG 500.

FRU085 1

TM2026

TM2027

See EAD I, "Drive Interconnections. "

See EAD I, "Drive Interconnections. "

1.

2.
3.

Perform a Rewind/Unload operation on the drive.
Press POR on the drive.
Rerun routine EEA2.

See EAD I, "Drive Interconnections. "
TM202B

REW TO - NO ALERT
Rewind timed aut. Ending alert was not received from the drive.

I This FRU is EC sensitive.

3480

,)

FRU085 1

See EAD I, "Drive Interconnections. "

See CARR-DR 4.

Routine EEA2 (Continued)

EC336396

c,:, COf'l'''~''' II,,,. Corp

See "Error Analysis" on DIAG 500.

1984 1l1li5 II/llti 19117

il

DIAG 504

o

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Ci

Basic Tape Motion Test - Routine EEA2 (Continued;

Routine EEA2 (Continued)

DESCRIPTION

FAILURE 10

ADDITIONAL ACTIONS
1.

FOLLOW STEPS 1 AND 2 BEFORE TAKING ANY OTHER ACTIONS:
2.

FRUS

See "Error Analysis " on DIAG 500.

TM202D

INVALID PATTERN RECD
An i nva lid pattern was entered. Va lid patterns are 0200 and 0000.

See "Test Selection " on DIAG 500, and enter 0000 to run
the test once or 0200 to loop the test continuously.

TM202E

REW SELECT TIMED OUT
Rewi nd command time out. A Rewi nd command issued to the drive did
not complete.

See "Error Analysis " on DIAG 500.
See the FSI section for er r·or codes 89nn and 8Fnn.

FRU085 1
FRUI99
FRU248
FRU 118
FRU 116
FRUI34

TM202F

RDF DR SIB STOPPED
Serial Read Forward command is issued. The drive should be at read
stoplock and repositioning should be off. Repositioning is s till on.

See "Error Analysis " on DIAG 500.

FRU085 1

TM2030

SER RD, NO SEL, NOREPO
The following sequence occurred:
1. A serial Read Forward command was issued wi th the drive at read
forward stop lock.
2. Repositioning was not set after sufficient time for the drive
to have reached 95 percent ve loc i ty.

See "Error Analysis " on DIAG 500.

FRu085 1

TM2031

REW CMD NOT ACCEPTED
The internal status for a Rewi nd command was not correct, which
indicates that the drive did not accept the cOlllmand.

See "E r r-or Analysis " on DIAG 500.

TM2032

An external register error occurred during the operation.

See "Error Analysis " on DIAG 500.

...--

DIAG 506

ERROR DISPLAY

FRu085 1

See EAD I, "Drive Interconnections. "

See qeps 1 and 2 at the top of this char t
TM2033

o

See the "Error Displays "
on DIAG 502.

If the value of ERA or ERB is other than 00, see the FSI
section for error code EIOO.
If PSR bit 0 = 1, see EAD I for error code Fnnn.

REW ALEkT TOO SOON
The following sequence occurred:
1. A serial Read Forward command was issued wi th the drive at read
forward stop lock.
2. Repositioning was checked to ensure it was set, which indicates
that the drive was going back to read stop lock.
3. A drive alert was detected too soon.

TM202C

o

.

See "Error Analysis " on DIAG 500.

A control unit Check I error occurred.

See steps 1 and 2 at the top of this chart.
See "Error Analysis " on DIAG 500.

TM2034

Either the BeSE or BOSE register contains an error.
is not checked for incorrect bits.

TM2035

Errors are set in the write, read, or drive error registers.

See "Error Analysis " on DIAG 500.

TM2036

The BCSE or BOSE registers did not contain the correct status.

See "Error Analysis " on DIAG 500.

I This FRU is EC sensitive.

3480 MI

EC336395

Buffer status

See CARR-DR 4.

Routine EEA2 (Continued)

DIAG 506

Basic Tape Motion Test - Routine EEA2 (Continued)

Routine EEA2 (Continued)
ADDITIONAL ACTIONS

DESCRIPTION

FAILURE 10

1.

FOLLOW STEPS I AND 2 BEFORE TAKING ANY OTHER ACTIONS:
TH2037

2.

The WSE register did not contain the correct status.

See "Error Analysis" on DIAG 500.

A drive Check 1 error occurred during the last 1/0 operation.

See "Error Analysis" on DIAG 500.
See the DCB for nn bits and see the FSI section for error
code 8Fnn.

TH2039

The drive status is incorrect excluding drive unit check.

See "Error Analysis " on DIAG 500.

TH203A

The drive sense contains an error that is unrecoverable.

See "Error Analysis " on DIAG 500.

TH203B

NO ALERT READ
A Serial Read command was issued to the drive and no alert
occurred after repositioning.

See "Error Analysis " on DIAG 500.

DIAGNOSE CHD TIHED OUT
A diagnose command issued to the drive did not complete.

See "Error Analysis " on DIAG 500.

TH203D

After an error r as part of an error recovery routine, the control
unit issued a Serial Reset A' command followed by a 'Set Diagnose',
which causes a midtape load. During this recovery routine, an
error occurred.

See "Error Analysis " on DIAG 500.

TH203E

After an error r as part of an error recovery routine, the control
unit issued a Serial Reset A' command followed by a 'Set Diagnose',
which causes a midtape load. When the routine had not completed
after three minutes, a timeout occurred.

See "Error Analysis" on DIAG 500.

TH203F

The DLR external register and drive sense do not agree.
Hodel (All and B22) or (A22 and Bll).

See CARR-CU 1189 for correct DLR external register switch
setting.

TH203C

1 This FRU is EC sensitive.

3480 MI
e

ERROR DISPLAY
See the "Error Displays "
on DIAG 502.

If the value of ERA or ERB is other than 00, see the FSI
section for error code EIOO.
If PSR bit 0 = I , see EAD 1 for error code Fnnn.

See the FSI section for error code D7nn.

TH2038

FRUS

FRU116
FRU118
FRU120
FRU114
FRU139
FRu085 1
FRU118
FRU116
FRU134
FRU199
FRU248

FRU085 1

See EAD 1 , "Drive Interconnections. "

See EAD 1, "Drive Interconnections. "

FRU118

See CARR-DR 4.

Routine EEA2 (Continued)

EC336395

CopyrIght IBM Corp. 1984. 1985. 1986

il

DIAG 508

DIAG 508

o

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DESCRIPTION

TM2040

A timeout error occurred
during a TIO command to
the drive.

TM2041

A drive status error
occurred wh i Ie sending
code to the drive.

ADDITIONAL ACTIONS
1. This program has minimum diagnostic capability

during the drive patching procedure.

o

o
Routine EEA2

Basic Tape Motion Test-Routine EEA2 (Continued)
FAILURE 10

o

FRUs

o
DIAG-509

ERROR DISPLAYS
See the "Error Displays "
on DIAG 502.

2. This error occurs when a cartridge loader is
installed and a cartridge is present in the
drive to be tested.

3. This error can be bypassed by loading the
functional code into the control unit and
sett i ng the control unit on-line. Press unload
switch of the drive to be tested, reload
diagnostic EE54 and run it. To avoid
channel interference set all the channel
enable/disable switches to disable.
4. If this error persists, run "Start Repair " on
the product diskette.

TM2042

The correct level of code
patches is not found on
the IML diskette.

TM2043

The correct level of code
patches is not found on
the IML diskette.

TM2044

Unable to read the IML
diskette due to an error.

1. Make sure the diskette in the diskette reader

is the correct level.
2. This error occurs when a cartridge loader is
installed and a cartridge is present in the
drive to be tested.
3. This error can be bypassed by loading the
functional code into the control unit and
sett i ng the control unit on-I i ne. Press unload
switch of the drive to be tested, reload
diagnostic EE54 and run it. To avoid
channel interference set a II the channel
enable/disable switches to disable.
Ensure that the control unit successfully
loads code from the diskette.
4. If this error persists, run "Start Repair " on
the product diskette.

3480 MI

EC336395

Routine EEA2

DIAG-509

Write / Read Exerciser - Routine EEA3
Note:
If the diagnostic is not permitted to complete
normally, (for example, if the program function or enter
key is used to stop the diagnostic) you must wait until
the drive motion has stopped before restarting the
diagnostic or an error will occur.

Prerequisite diagnostics must run without failure before
this diagnostic is run. See DIAG 3, "PREREQUISITE
DIAGNOSTICS ...
This routine verifies that the write. read backward, and read
operations of the drive operate correctly. Routine EEA3 tests
are performed at the beginning-of-tape (BOT).

FRUS

This test checks the drive's data flow and buffer with the
following sequence of operations:

See CARR-CU or CARR-DR, pages 1-1,1-2,1-3, and 1-4 for
the names and locations of the FRUs.

1.
2.
3.

Error Analysis

4.
5.

Checks for interrupts that are on all of the time.
Ensures that a single drive address is entered.
Sends a sense command to reset any unit checks or sense
data.
Sends a rewind command to start the test at BOT.
Writes and reads 16 blocks of varying length data.

Routine Start Address:

3010

Error Loop:

If no error occurs, the routine loops as if "LOOP
ROUTINE" is set. When an error is detected, the routine saves
the error information and displays the error on the MD. After
the error is displayed, the routine continues to loop on that error.
However, if a different error occurs, that new error is displayed
on the MD, and the routine will loop on the new error.

T est Selection
The following screen displays after routine number EEA3 has
been entered to start the tape motion diagnostic routine.

DIAG={EEA3)-ENTER:
DRIVE
(xx)

Valid parameters:

xx

Drive address (O-F, or OO-OF).

To run the tests:
1.
2.

Insert a write enabled scratch cartridge in the drive and
make it ready.
Enter the drive address.

Error Displays
When an error is detected by the diagnostic program, the
maintenance device displays error information on its
keyboard/display. The first screen displays automatically. You
can see the second and following screens by pressing the
ENTER key on the keyboard/display.
The format of the display's first line is the same for all detected
errors. The remaining three lines contain additional information
about the failure.

Bit 6

Bit 7

Bit 8

Analyze the errors for routine EEA3 as follows:
1.
2.
3.

From the first error information screen record the key
number, the drive address, and the drive status.
Read the error message on the first error information screen
and perform any action indicated.
Take the actual drive status (tttt) and the expected drive
status (ssss) and convert them to binary. Example:

8621

=

Bit 10

1000 0110 0010 0001

The bits are numbered 0-15, left to right. Compare the
actual to expected drive status, and analyze bits that do not
match.
This bit indicates that a Serial command was
Bit 0
issued since the last parallel command. This bit
will only be on in the next status received by the
control unit. If this is one of the error bits, see
FSI section for error code 9602.
This bit indicates that the drive is repositioning
Bit 1
after a previous Serial or Parallel command.
Repositioning can be indicated over either the
serial or the parallel interconnections and should
always indicate the real-time operation of the
drive, so both indicators should always indicate
the same condition. If this is one of the error
bits, see FSI section for error code 8804.
This bit indicates the drive just changed from Not
Bit 2
Ready to Ready. This is usually a normal
condition. If this is one of the error bits, see FSI
section for error code 33E8.
This bit indicates that the drive has moved a
Bit 3
predetermined amount of tape and is notifying
the control unit. This is usually a normal
-condition. This bit is not checked by routine
EEA3.
Bit 4
This bit indicates that the drive just completed a
Disconnected command. If this is one of the
error bits, replace FRU085 *.

Bit 5

Bit 9

Bit 11

Bit 12

Bit 13

Bit 14

Bit 15

Routine EEA3

DIAG 510

Routine EEA3

DIAG 510

This bit indicates the drive set drive unit check
and sense data is present in the drive. Normally,
the sense data is valid and is displayed in a later
error information screen. Analyze this bit last.
See EAD 1, "Drive Interconnections" for failure
isolation.
This bit indicates that the tape loaded in the drive
has been manually unloaded using the
Rewind/Unload switch. If this is one of the error
bits, see FSI section for error code 8202.
This bit indicates that the drive address is one
with an address in the range of 8 F. If this is
one of the error bits, see FSI section for error
code 86CO.
This bit indicates that the drive has completed a
tape volume mount and is ready. If this is one of
the error bits, see FSI section for error code
33E8.
This bit indicates that the drive has received
patches from the control unit. Normally during
this diagnostic, this bit is not active: however, if
the functional microcode has previously sent
patches and the drive has not been powered off
or reset has not been issued, this bit may be on.
This bit is not checked.
This bit indicates the drive is positioned at the
beginning of tape. See EAD 1, "Drive
Interconnections" for failure isolation.
This bit indicates that the drive tape volume is file
protected. If this is one of the error bits, see FSI
section for error code CK07.
This bit indicates that the drive is positioned at or
following the logical end of tape. If this is one of
the error bits, replace FRU085*.
See EAD 1, "Drive Interconnections" for failure
isolation.
This bit indicates that the drive is positioned at
the physical end of tape. If this is one of the
error bits, replace FRU085 *.
See EAD 1, "Drive Interconnections" for failure
isolation.
Reserved

See EAD 1, "Drive Interconnections" for failure
isolation.
This bit indicates that the drive just completed a
Connected command. If this is one of the error
bits, replace FRU085*.
See EAD 1, "Drive Interconnections" for failure
isolation.

External registers are defined in the DF (Data Fields) section of
this maintenance information.

3480

EC336395

., Copv"ghlIBM co

Copyright ISM Corp. 1984. 1985. 1986 ,} ~) ~) if \ ,J ~) t " ) ,) t ~J ~j DIAG 528 . l j o o () o o o o o Write / Read EXerciser - Routine EEA3 (Continued) Routine EEA3 (Continued; DESCRIPTION FAILURE 10 ADDITIONAL ACTIONS 1. FOLLOW STEPS 1 AND 2 BEFORE TAKING ANY OTHER ACTIONS: TM3061 TM3062 TM3063 TM3064 o 2. A pattern sequence table error occurred during a read back check operation. 'Gap in' and 'generate gap out' (RSR register) were on, causing a level 3 interrupt to occur. FRUS If the value of ERA or ERB is other than 00, see the FSI section for error code El00. If PSR bit 0 = I, see EAD 1 for error code Fnnn. See "Error Analysis" on DIAG 510. See the FSI section for error code 7074. See "Error Analysis" on DIAG 510. See the FSI section for error code 7081. o DIAG 530 ERROR DISPLAYS See the "Error Displays" on DIAG 512. FRU062 1 FRU064 FRUl16 FRUl18 FRU130 FRU131 FRU132 FRU123 FRU124 FRU125 FRUl19 FRUl12 2 FRUl13 2 FRUl18 FRUl19 FRU176 FRUl16 A device buffer overrun condition occurred once while writing the same record. See "Error Analysis" on DIAG 510. See the FSI section for error code 7081. FRUl14 FRU120 FRUl17 A device buffer overrun condition occurred while reading a record operation. See "Error Analysis" on DIAG 510. See the FSI section for error code 7173. FRUl14 FRU120 ---------+-----------------------------------------------------------------~-------------------------------------------------------+------~ 1 TM3065 TM3066 'Density separator' was not detected before 45 sets of samples were taken. See "Error Analysis" on DIAG 510. A pattern sequence table error occurred during a read back check operation. The read data flow detected a tapemark (TM) that was not expected. See "Error Analysis" on DIAG 510. 1 This FRU is EC sensitive. See CARR-DR 4. 2 This FRU is EC sensitive. FRUl12 may not be present. 3480 MI EC336395 Copyright FRU085 1 FRU 118 FRUl16 FRU134 FRU199 FRU248 - See "Error Analysis" on DIAG 550. See the FSI section for error code 70E6. This FRU is EC sensitive. FRUl16 FRU 118 FRU120 FRU 114 FRU139 FRU085 1 See the FSI section for error code 70E4. TM6042 ERROR DISPLAYS See the "Error Displays " on DIAG 552. If the value of ERA or ERB is other than 00, see the FSI section for error code EIOO. If PSR bit 0 = 1 , see EAD 1 for error code Fnnn. TM6035 DIAG 558 FRU120 FRU 114 FRU 114 FRU120 FRU112 2 FRU 113 2 FRUlll FRU 116 FRU085 1 FRU062 1 FRU064 FRU 116 FRU 118 FRUl14 FRU120 See CARR-DR 4. FRU112 may not be present. See CARR-CU 7. EC336395 Routine EEA4 (Continued) IBM Corp. 1984. 1985 .J :) :} ~J \. \. 1 DIAG 558 '" I'" o o o o o o o o Vvrite i Read Exerciser - Routine EEA4 (Continuedj Routine EEA4 (Continued; DESCRIPTION FAILURE 10 ADDITIONAL ACT IONS 2. TM60~~ FRUS A wr i te data f low errol was detected wh i Ie writing this , record. Error bits were 011 in the WSE register, or 'end wr i te did not set in the maximum allowable time. See "Error Analysis " on DIAG 550. A wr i te sequence error occurred. Ca 11 your next level of support. o DIAG 560 ERROR DISPLAYS See the "Error Displays " on DIAG 552. If the value of ERA or ERB is other than 00, see the FSI section for error code El00. If PSR bit o .. 1, see EAD 1 for er ror code Fnnn. 1. FOLLOW STEPS I AND 2 BEFORE TAKING ANY OiHER ACTIONS: TM60~3 o See the FSI section for error code 70E5. This is a microcode program error. rM60~5 Call your next level of support. A wr i te sequence error occurred. This is a microcode program error. TM60~6 A , time out occurred waiting for the gap out'. , status in , response See "Error Analysis " on DIAG 550. to FRu085 1 FRUl18 See the FSI section for error code 70E3. TM60~7 See "Error Analysis " on DIAG 550. A drive check I occurred. See the FSI section for error code 89nn. FRU085 1 FRU199 FRU2~8 FRUl18 FRUl16 FRU13~ TM6048 A time out occurred waiting for the device data bus to become active. , status in , line See "Error Analy .. is " on DIAG 550. See the FSI .. ection for error code 8C03. TM60~9 The hardware detected a device adapter error. See "Error Analysis " on DIAG 550. See the FSI sect ion for error code 8Bnn. TM60~A Drive sense data contains an error, and whi Ie ending the tag sequence to the drive, device data bus 'status in' did not drop. See "Error Analyc,is " on DIAG 550. See the FSI .. ec:t ion for error code 8C07. FRU085 1 FRUl18 FRUI16 FRU13~ FRU085 1 FRUl18 FRU116 FRU13~ FRU085 1 FRU118 FRUl16 FRU13~ 1 This FRU is EC sensitive. 3480 MI EC336395 See CARR-DR ~. Routine EEA4 (Continued) DIAG 560 Write/Read Exerciser - Routine EEA4 (Continued) Routine EEA4 (Continued) ADDITIONAL ACTIONS DESCRIPTION FAILURE 10 I. FOLLOW STEPS I AND 2 BEFORE TAKING ANY OTHER ACTIONS: 2. If the value of ERA or ERB is other than 00, see the FSI section for error code El00. If PSR bit 0 = I, see EAD I for error code Fnnn. A pattern sequence table error occurred during the read back check. The read data flow detected an IBG that was not expected. See "Error Analysis" on DIAG 550. TM604c This is a microcode program error. Call your next level of support. TM604D IBG was not detected after device data bus TM604e I gap •In I . See the FSI section for error code 7061. See "Error Analysis" on DIAG 550. See the FSI section for error code 7093. TM604E A device buffer overrun occurred once whi Ie writing the same record. See "Error Analysis" on DIAG 550. See the FSI section for error code 7181. TM604F 256 ERGs were read without detecting a Block or TM. See "Error Analysis" on DIAG 550. See the FSI section for error code 7702. This FRU is EC sensitive. 2 This FRU is EC sensitive. 3480 MI EC336395 e Copyright IBM Corp. 1984. 1985 FRUS DIAG 562 ERROR DISPLAYS See the "Error Displays" on DIAG 552. FRU062 1 FRU064 FRUIl6 FRUI18 FRU130 FRUI31 FRUI32 FRUI23 FRUI24 FRUI25 FRUI19 FRUI12 2 FRU 113 2 FRu064 FRU062 1 FRU085 1 FRUI30 FRU116 FRU216 FRU059 FRU 117 FRUI31 FRU132 FRUI18 FRUI19 FRU063 1 FRU058 FRUOl3 FRUI14 FRUI20 FRUI17 FRU062 1 FRU064 FRUI16 FRUI18 FRUI30 FRUI31 FRUI32 FRUI23 FRUI24 FRUI25 FRU 119 FRUI122 FRUI13 2 See CARR-DR 4. FRUI12 may not be present. See CARR-CU 7. Routine EEA4 (Continued) DIAG 562 o o o o o o o o WriieiRead Exerciser - Rouiine EEA4 (Coniinuedj FAILURE !D Routine EEA4 (Continued) DESCRIPTION ADDITIONAL ACTIONS I. FOLLOW STEPS I AND 2 BEFORE TAKING ANY OTHER ACTIONS: 2. TM6050 A read error occurred on the last record. A timeout occurred waiting for the device data bus response to 'gap out'. See "Error Analysis" on DIAG 550. , status in , FRUS See "Error Analysis" on DIAG 550. o DIAG 564 ERROR DISPLAYS See the "Error Displays" on DIAG 552. If the value of ERA or ERB is other than 00, see the FSI section for error code EIOO. If PSR bit 0 = I, see EAD I for error code Fnnn. See the FSI section for error code 76nn. TM6051 o FRU0621 FRU064 FRU 116 FRU 118 FRUI30 FRUI31 FRUI32 FRUI23 FRUI24 FRUI25 FRU 119 FRUI20 FRUI14 FRU III FRu085 1 FRU 118 See the FSI section for error code 7701. TM6052 During a read back check, a level 3 interrupt occurred that was caused by 'end sync'. See "Error Analysis" on DIAG 550. See the FSI section for error code 7503. TM6053 A read back check error occurred on the last record. See "Error Analysis" on DIAG 550. See the FSI section for error code 74nn. I This FRU is EC sensitive. 3480 EC336396 FRu064 FRU062 1 FRu085 1 FRUI30 FRU 116 FRU216 FRU059 FRUI17 FRUI31 FRU 132 FRU 118 FRU 119 FRU063 1 FRU058 FRUOl3 FRU064 FRU062 1 FRU 116 FRU 118 FRUI30 FRUI31 FRUI32 FRUI23 FRUI24 FRUI25 FRU 119 FRU III FRU 114 FRUI20 FRU264 FRU265 See CARR-DR 4. Routine EEA4 (Continued) DIAG 564 Write/Read Exerciser - Routine EEA4 (Continued) FAILURE 10 Routine EEA4 (Continued) ADDITIONAL ACTIONS DESCRIPTION 1. 2. See "Error Analysis" on OIAG 550. The value of bits 0 and I of the RRC register do not match the value of bits 6 and 7 (word 1) of the LOT table. See the FSI section for error code 7501. TI'I6055 A timeout occurred whi Ie waiting for the device data bus 'status response to 'gap out'. .In , See "Error Analysis " on DIAG 550. ERROR DISPLAYS See the "Error Displays" on DIAG 552. If the value of ERA or ERB is other than 00, see the FSI section for error code El00. If PSR bit 0 = I, see EAD 1 for error code Fnnn. FOLLOW STEPS 1 AND 2 BEFORE TAKING ANY OTHER ACTIONS: TI'I6054 FRUS DIAG 566 FRu064 FRU062 1 FRU085 1 FRU130 FRU 116 FRU216 FRU059 FRU 117 FRU131 FRUI32 FRU 118 FRU119 FRU063 1 FRU058 FRU013 FRU085 1 FRU118 See the FSI section, error code 7502. TM6056 Device data bus 'gap out' did not occur for the last block of data read. See "Error Analysis " on DIAG 550. FRu085 1 FRU 118 See the FSI section, error code 7502. TM6057 After a Read 10 operation, an error was indicated in the BOSE register. See "Error Analysis " on DIAG 550. See the FSI section, error code 70CI. TI'I6058 A block 10 format error occurred. Bits 0 and 8-11 of the four-byte block 10 are always zero. The block just read from the tape contains a block 10 with at least one of these bits on. This FRU is EC sensitive. 2 This FRU is EC sensitive. 3480 See "Error Analysis" on DIAG 550. • See the FSI section for error code 70c4. FRU 114 FRUI20 FRUI12 2 FRU 113 2 FRU 111 FRU 116 FRU062 1 FRU064 FRU 116 FRU 118 FRU130 FRU 13 1 FRU132 FRUI23 FRU124 FRUI25 FRU 119 FRU112 2 FRU 113 2 See CARR-DR 4. FRU112 may not be present. See CARR-CU 7. EC336396 Routine EEA4 (Continued) :) DIAG 566 o o (; o o o o WriteiRead Exerciser - Routine EEA4 (Continued; Routine EEA4 (Continuedj ADDITIONAL ACTI ONS DESCRIPTION FAILURE 10 1. FOLLOW STEPS 1 AND 2 BEFORE TAKING ANY OTHER ACTIONS: 2. See "Error Analysis" on DIAG 550. A block 10 error occurred on a Read Backward operation. The block just read from the tape does not have the expected block 10 sequence number. See "Error Analysis" on DIAG 550. TM605B The expected buffer CRC data did not compare to the actual data read from the buffer. This could be the wrong block read. No hardware errors were detected. See "Error Analysis " on DIAG 550. TM605C The expected buffer CRC data did not compare to the actual data read from the buffer. This could be the wrong block read. No hardware errors were detected. See "Error Analysis" on DIAG 550. TM605D A level 0 interrupt occurred that was caused by an external register error. See "Error Analysis " on DIAG 550. TM605A FRUS See the FSI section for error code 70C2. See the FSI section for error code 70C3. o DIAG 568 ERROR DISPLAYS See the "Error Displays " on DIAG 552. If the value of ERA or ERB is other than 00, see the FSI section for error code El00. If PSR bit 0 = I, see EAD 1 for error code Fnnn. A block 10 error occurred on a Read Forward operation. The block just read from the tape does not have the expected block 10 sequence number. TM6059 o FRU062 1 FRU064 FRUl16 FRU118 FRU130 FRU131 FRU132 FRU123 FRU124 FRU125 FRUl19 FRUl12 2 FRUl13 2 FRU062 1 FRu064 FRUl16 FRU118 FRU130 FRU131 FRU132 FRU123 FRU124 FRU125 FRUl19 FRUl12 2 FRUl13 2 See steps I and 2 at the top of this chart. See the FSI section for error code 7061. TM605E TM605F A level 0 interrupt occurred that was not caused by an external register error or 'collision detect' . See "Error Analysis " on DIAG 550. A level 0 interrupt occurred that was caused by 'collision detect'. See "Error Analysis" on DIAG 550. See the FSI section for error code 1100. FRUl19 FRUl17 FRUl19 FRUl17 See the FSI section for error code 1100. This FRU is EC sensitive. 2 This FRU is EC sensitive. 3480 MI EC336395 It Copyr'ght IBM Corp. 1984. 1985 See CARR-DR 4. FRUl12 may not be present. See CARR-CU 7. Routine EEA4 (Continued) DIAG 568 Write/Read Exerciser - Routine EEA4 (Continued) Routine EEA4 (Continued) ADDITIONAL ACTIONS DESCRIPTION FAILURE 10 1. FOLLOW STEPS 1 AND 2 BEFORE TAKING ANY OTHER ACTIONS: TM6060 TM6061 TM6062 2. If the value of ERA or ERB is other than 00, see the FSI section for error code El00. If PSR bit 0 = 1, see EAD 1 for error code Fnnn. A time out occurred waiting for 'beg sync' during a read back check operation. See "Error Analysis" on DIAG 550. See the FSI section for error code 7071. See "Error Analysis" on DIAG 550. A write data flow error was detected whi Ie writing this record. FRU bits were on in WSE register, or 'end write' did not set in the maximum allowable time (50 microseconds). See the FSI section for error code 7076. The BOSE register detected an buffer error while writing this record. See "Error Analysis" on DIAG 550. See the FSI section for error code 7077. , FRUS FRU062 1 FRU064 FRU 116 FRU118 FRU130 FRU131 FRU132 FRU123 FRU124 FRU125 FRU119 FRU 1122 FRU 113 2 FRU085 1 FRU062 1 FRU064 FRUl16 FRUl18 FRUl14 FRU120 FRU 114 FRU120 FRUl12 2 FRU 113 2 FRUlll FRUl16 'Device xfer complete (BOSE register) was not on, at the end of a Buffer to WDF Transfer operation. See "Error Analysis " on DIAG 550. See the FSI section for error code 7078. FRU120 FRUl14 TM6064 A pattern sequence table error occurred during a read back check operation. See "Error Analysis " on DIAG 550. FRU062 1 FRU064 FRUl16 FRUl18 FRU130 FRU131 FRU132 FRU123 FRU124 FRU125 FRUl19 FRUl12 2 FRU 113 2 'Gap in' and 'generate gap out' (RSR register) were on, causing a level 3 interrupt to occur. See "Error Analysis" on DIAG 550. TM6065 See the FSI section for error code 7081. This FRU is EC sensitive. 2 This FRU is EC sensitive. 3480 MI C Copyright IBM FRUl18 FRUl19 FRU176 FRUl16 See CARR-DR 4. FRU112 may not be present. See CARR-CU 7. EC336395 corp. ERROR DISPLAYS See the "Error Displays" on DIAG 552. TM6063 See the FSI section for error code 7074. DIAG 570 Routine EEA4 (Continued) 1984, 1986 :J DIAG 570 \.. j o o o o o o o o WriteiRead Exerciser - Routine EEA4 (Continued; Routine EEA4 (Continued) DESCRIPTION FAILURE ID ADDITIONAL ACTIONS 1. FOLLOW STEPS 1 AND 2 BEFORE TAKING ANY OTHER ACTIONS: 2. If the value of ERA or ERB is other than 00, see the FSI section for error code El00. If PSR bit 0 = I, see EAD 1 for error code Fnnn. See the FSI section for error code 7081. FRUl14 FRU120 FRUl17 TM6067 A device buffer overrun condition occurred while reading a record operation. See "Error Analysis" on DIAG 550. See the FSI section for error code 7173. FRUl14 FRU120 TM6068 'Density separator' was not detected before 45 sets of samples were taken. See "Error Analysis" on DIAG 550. FRU062 1 FRU064 FRUl16 FRUl18 FRU130 FRU131 FRU132 FRU123 FRU124 FRU125 FRUl19 FRUl12 2 FRUl13 2 A pattern sequence table error occurred during a read back check operation. The read data flow detected a tapemark (TM) that was not expected. See "Error Analysis" on DIAG 550. A tapemark (TM) was read during read back check that did not meet the minimum length specifications. See "Error Analysis" on DIAG 550. TM606A See the FSI section for error code 7161. See the FSI section for error code 7041. See the FSI section for error code 7042. This FRU is EC sensitive. 2 This FRU is EC sensitive. 3480 MI EC336395 Copyr'ght IBM Corp. '984. ,985 o DIAG 572 ERROR DISPLAYS See the "Error Displays" on DIAG 552. See "Error Analysis" on DIAG 550. TM6069 (t FRUS A device buffer overrun condition occurred once whi Ie writing the same record. TM6066 o FRU062 1 FRU064 FRUl16 FRUl18 FRU130 FRU131 FRU132 FRU123 FRU124 FRU125 FRUl19 FRUl12 2 FRU 113 2 FRU062 1 FRU064 FRUl16 FRUl18 FRU130 FRU 131 FRU132 FRU123 FRU124 FRU125 FRUl19 FRU112 2 FRU113 2 See CARR-DR 4. FRUl12 may not be present. See CARR-CU 7. Routine EEA4 (Continued) DIAG 572 Write/Read Exerciser - Routine EEA4 (Continued) Routine EEA4 (Continued) DESCRIPTION FAILURE 10 ADDITIONAL ACTIONS 1. FOLLOW STEPS 1 AND 2 BEFORE TAKING ANY OTHER ACTIONS: TM606B 2. The write control register eWCR) did not set at the correct time. See "Error Analysis" on DIAG 550. TM606C This is a microcode program error. Call your next level of support. TM606D The read back check started incorrectly. I t came up when reading the IBG. and did not find the block before the first IBG. See "Error Analysis" on DIAG 550. See the FSI section for error code 7051. See the FSI section for error code DOnn. See the FSI section for error code D8nn. TM606F The read back check started incorrectly and timed out waiting for the IBG preceding the first block written. See "Error Analysis" on DIAG 550. The IBG read during the read back check was too short. See "Error Analysis" on DIAG 550. See the FSI section for error code 7052. See the FSI section for error code 7151. This FRU is EC sensitive. 2 This FRU is EC sensitive. 3480 MI ERROR DISPLAYS See the "Error Displays " on DIAG 552. If the value of ERA or ERB is other than 00. see the FSI section for error code El00. If PSR bit 0 = 1. see EAD 1 for error code Fnnn. See the FSI section for error code 7192. TM606E FRUS DIAG 574 FRU064 FRU116 FRU063 1 FRU118 FRU062 1 FRU064 FRU116 FRUl18 FRU130 FRU131 FRU132 FRU123 FRU124 FRU125 FRU119 FRU112 2 FRU 113 2 FRU062 1 FRU064 FRU116 FRU118 FRU130 FRU131 FRU132 FRU123 FRU124 FRU125 FRU119 FRUl12 2 FRU 113 2 FRU062 1 FRU064 FRU116 FRUl18 FRU130 FRU131 FRU132 FRU123 FRU124 FRU125 FRUl19 FRU112 2 FRU 113 2 See CARR-DR 4. FRUl12 may not be present. See CARR-CU 7. EC336395 Routine EEA4 (Continued) ~ Copyright IBM Corp. 1984. 1986 {) f} \ DIAG 574 :1 o o o o o o o o Write / Read Exerciser - Routine EEA4 (Continued) Routine EEA4 (Continued) ADDITIONAL ACT IONS DESCR I PTI ON FAILURE ID 1. FOLLOW STEPS 1 AND 2 BEFORE TAKING ANY OTHER ACTIONS: 2. TM6070 The IBG read during the read back check was too long. A read back check occurred waiting for the IBG. See "Error Analysis" on DIAG 550. See "Error Analysis" on DIAG 550. See the FSI section for error code 7159. TM6072 VOID was detected during a read operation. A valid block l TH, or ERG was not detected within 67 milliseconds after 'gap in . See "Error Analysis" on DIAG 550. See the FSI section for error code 7153. This FRU is EC sensitive. 2 This FRU is EC sensitive. 3480 MI EC336395 C CopyrighllBM Corp. 1984. 1985 FRUS o DIAG 576 ERROR DISPLAYS See the "Error Displays " on DIAG 552. If the value of ERA or ERB is other than 00, see the FSI section for error code El00. If PSR bit 0 = I, see EAD 1 for error code Fnnn. See the FSI section for error code 7152. TM6071 o FRU062 1 FRU064 FRU116 FRU118 FRU130 FRU131 FRU132 FRU123 FRU124 FRU125 FRU119 FRU112 2 FRU113 2 FRU064 FRU062 1 FRU085 1 FRU130 FRU116 FRU216 FRU059 FRU 117 FRU131 FRU132 FRU 118 FRU119 FRU063 1 FRU058 FRU013 FRU064 FRU062 1 FRU085 1 FRU130 FRUl16 FRU216 FRU059 FRU117 FRU131 FRU132 FRUl18 FRU119 FRU063 1 FRU058 FRU013 See CARR-DR 4. FRUl12 may not be present. See CARR-CU 7. Routine EEA4 (Continued) DIAG 576 Write/Read Exerciser - Routine EEA4 (Continued) FAILURE 10 Routine EEA4 (Continued) DESCRIPTION ADDITIONAL ACTIONS 1. FOLLOW STEPS 1 AND 2 BEFORE TAKING ANY OTHER ACTIONS: 2. TM6073 A data transfer timeout was detected during a read operation. valid IBG was read within 67 mi II iseconds after 'beg sync' No If the value of ERA or ERB is other than 00, see the FSI section for error code El00. If PSR bit 0 ; 1, see EAD 1 for error code Fnnn. See "Error Analysis" on DIAG 550. See the FSI section for error code 7154. TM6074 A data transfer timeout was detected during a RBC operation. valid IBG was read within 67 mi II iseconds after 'beg sync'. No See "Error Analysis" on DIAG 550. See the FSI section for error code 7155. TM6075 A read back check of a tapemark determined that the tapemark's length was too long. This FRU is EC sensitive. 2 This FRU is EC sensitive. 3480 MI 01> EC336395 Copyr'ght IBM Corp. 19B4. 19B5 FRUS See "Error Analysis" on DIAG 550. See the FSI section for error code 7156. DIAG 578 ERROR DISPLAYS See the "Error Displays" on DIAG 552. FRU062 1 FRU064 FRU 116 FRUl18 FRU130 FRU131 FRU132 FRU123 FRU124 FRU125 FRU 119 FRUl12 2 FRUl13 2 FRU062 1 FRU064 FRUI16 FRUl18 FRU130 FRU131 FRU132 FRU123 FRU124 FRU125 FRUl19 FRU 1122 FRUl13 2 FRU062 1 FRU064 FRUl16 FRUl18 FRU130 FRU131 FRU132 FRU123 FRU124 FRU125 FRU 119 FRUl12 2 FRU 113 2 See CARR-DR 4. FRUl12 may not be present. See CARR-CU 7. Routine EEA4 (Continued) DIAG 578 o o o o o o o o Routine EEA4 (Continued) Write/Read Exerciser - Routine EEA4 (Continued) ADDITIONAL ACTIONS DESCRIPTION FAILURE 10 1. FOLLOW STEPS 1 AND 2 BEFORE TAKING ANY OTHER ACTIONS: TM6076 TM6077 o 2. FRUS See "Error Analysis" on DIAG 550. A Write Erase Gap operation was not ended by a buffer interrupt. See "Error Analysis" on DIAG 550. See the FSI section error code 7154. DIAG 580 ERROR DISPLAYS See the "Error Displays" on DIAG 552. If the value of ERA or ERB is other than 00, see the FSI section for error code El00. If PSR bit a = I, see EAD 1 for error code Fnnn. No beginning of block or tapemark was detected in the maximum allowed time during a read operation. o FRu062 1 FRU064 FRU116 FRU118 FRU 130 FRU131 FRUI32 FRUI23 FRU124 FRUI25 FRUI19 FRUI12 2 FRU113 2 FRUI14 FRUI20 See the FSI section for error code 715A. TM6078 A write data flow error occurred. See "Error Analysis " on DIAG 550. TM6079 A valid density pattern was not read after five retries. See "Error Analysis " on DIAG 550. See the FSI section for error code 7141. ,write TM607A A timeout occurred waiting for density separator. TM607B A timeout occurred waiting for the density separator. end' when writing a write See "Error Analysis " on DIAG 550. See the FSI section for error code 7144. FRUI16 See "Error Analysis " on DIAG 550. FRU062 1 FRUo64 FRU 116 FRU118 FRU130 FRUI31 FRUI32 FRU123 FRUI24 FRU125 FRU119 FRU 1122 FRU 113 2 See the FSI section for error code 7142. This FRU is EC sensitive. 2 This FRU is EC sensitive. 3480 EC336396 FRU062 1 FRU064 FRU 116 FRUI18 FRUI30 FRUI31 FRUI32 FRUI23 FRUI24 FRU125 FRUI19 FRUI12 2 FRU113 2 FRU264 FRU265 See CARR-DR 4. FRUI12 may not be present. See CARR-CU 7. Routine EEA4 (Continued) DIAG 580 Write/Read Exerciser - Routine EEA4 (Continued) FAI LURE 10 Routine EEA4 (Continued) DESCRIPTION ADDITIONAL ACT IONS FOLLOW STEPS I AND 2 BEFORE TAKING ANY OTHER ACTIONS: 1. 2. TM607C See "Error Analysis " on DIAG 550. See the FSI section for error code 7143. This is a microcode program error. TM607E A timeout occurred waiting for I gap in FRu062 1 FRU064 FRU 116 FRU 118 FRUI30 FRUI31 FRUI32 FRUI23 FRUI24 FRUI25 FRU 119 FRU 1122 FRUI13 2 Ca I I your next level of support. I from the drive. See "Error Analysis " on DIAG 550. See the FSI section for error code 960 I. TM607F A time out occurred waiting for the drive to be selected on a read or write command. See "Error Analysis " on DIAG 550. See the FSI section for error code 8005. See the FSI section for error code 8007. See the FSI section for error code 8009. FRU085 1 FRU 118 FRU 117 FRUI34 FRU liS FRU085 1 FRUI99 FRU248 FRU 118 FRU059 FRU049 FRUI08 FRU107 FRUI05 TM6080 This is a microcode program error. Ca 1 I your next level of support. TM6081 This is a microcode program error. Ca II your next leve I of support. TM6082 This is a microcode program error. Ca I I your next level of support. TM6083 A Set Diagnose command was sent to the drive and it did not complete correctly. See "Error Analysis " on DIAG 550. FRu085 1 FRUI99 TM6084 A Set Diagnose command, sent to the drive, did not complete. See "Error Analysis " on DIAG 550. FRU08s 1 FRUI99 FRU248 FRU 118 FRU059 FRU049 FRUI08 FRUI07 FRUI05 See the FSI section for error code 8005. See the FSI section for error code a007. See the FSI section for error code 8009. This FRU is EC sensitive. 2 This FRU is EC sensitive. 3480 EC336396 See CARR-DR ERROR DISPLAYS See the "Error Displays " on DIAG 552. If the value of ERA or ERB is other than 00, see the FSI section for error code EIOO. If PSR bit 0 = I, see EAD I for error code Fnnn. A timeout occurred wh i Ie waiting for the IBG after the density separator. TM607D FRUS DIAG 582 4. FRUI12 may not be present. See CARR-CU 7. Routine EEA4 (Continued) DIAG 582 o o o o o o o o Write/Read Exerciser - Routine EEA4 (Continued; Routine EEA4 (Continued) DESCRIPTION FAilURE 10 ADDITIONAL ACTIONS 1. FOllOW STEPS I AND 2 BEFORE TAKING ANY OTHER ACTIONS: 2. TM6085 TM6086 I This FRU is EC sensitive. 3480 MI EC336395 ~ CopyrIght IBM Corp. 19B4, 1985, 1986 FRUS If the value of ERA or ERB is other than 00, see the FSI section for error code EIOO. If PSR bit 0 = I, see EAD I for error code Fnnn. Test EEA4 has completed, and there are one or more errors in the counters. The counters are displayed on the screen with the following first line: BlKS CORR EEA3 EEA4. (See ERROR DISPLAYS on DIAG 552.> The DlR external register and drive sense do not agree. Model (All and B22) or (A22 and BII). o I. See "Error Counts" on DIAG 550. 2. a. b. c. d. 3. Clean the read/write head. FRUOI3. 4. Use the product diskette and run the "unit test" option, looking for a high number of temporary errors. Test another drive using the same cartridge. Test the the same 2 drives using another cartridge. Test both drives using both cartridges. Run the test using the other CU (if present). See CARR-DR I-I, for See CARR-CU 1189 for correct DlR external register switch sett ing. o DIAG 584 ERROR DISPLAYS See the "Error Displays" on DIAG 552. DR FRU062I FRU064 FRU063 1 FRU085 1 FRU216 FRU059 FRUOl3 CU FRUI32 FRUI31 FRU 130 FRUI25 FRUI24 FRUI23 FRUI19 FRUIII FRUI99 FRU248 FRU264 FRU265 FRUI18 See CARR-DR 4. Routine EEA4 (Continued) DIAG 584 Write / Read Exerciser-Routine EEA4 (Continued) FAILURE 10 DESCRIPTION TM4087 A timeout error occurred during a TIO command to the drive. TM4088 A drive status error occurred wh i Ie sending code to the drive. ADDITIONAL ACTIONS 1. This program has minimum diagnostic capability during the drive patching procedure. FRUs Routine EEA4 DIAG-586 Routine EEA4 DIAG-586 ERROR DISPLAYS See the "Error Displays " on DIAG 552. 2. This error occurs when a cartridge loader is insta lIed and a cartridge is present in the drive to be tested. 3. This error can be bypassed by loading the functional code into the control unit and sett i ng the control unit on-line. Press unload switch of the drive to be tested. reload diagnostic EE54 and run it. To avoid channel interference set a II the channel enable/disable switches to disable. 4. If this error persists. run "Start Repair " on the product diskette. TM4089 The correct level of code patches is not found on the IML di skette. TM408A The correct level of code patches is not found on the IML diskette. TM408B Unable to read the IML diskette due to an error. 1. Make sure the diskette in the diskette reader is the correct level. 2. This error occurs when a cartridge loader is installed and a cartridge is present in the drive to be tested. 3. This error can be bypassed by loading the functional code into the control unit and setting the control unit on-line. Press unload swi tch of the drive to be tested. reload diagnostic EE54 and run it. To avoid channel interference set a II the channel enable/disable switches to disable. Ensure that the control unit successfully loads code from the diskette. 4. If this error persists. run "Start Repair " on the product diskette. 3480 MI e EC336395 Copyright IBM Corp. 19B4. 1985. 1986 :) " } } Scope a p Utility - RoutOEEFO o This routine permits the service representative (SR) to select and loop a register in any of the eight control or adapter cards. Addresses, data, clock lines, and so on, can also be scoped in the external register area of the control unit using this scoping utility. Use the "XR Bus and Control Clocks" timing chart (see EAD 1) as a guide when using this scope procedure. Error Loop: All errors are ignored when this routine is running. This chart shows which diagnostic is used to to!'t the external registers. III AGUOSTl C EEl2 EEl3 EEl~ Test Selection The following screen displays after routine EEFO has been selected. EE85 DIAG=(EEFa)-ENTER: PATTERN TTl I TT II Address for register selection Data field (enter 00) Four characters must be entered for the data pattern to be valid. Valid IT patterns are listed under ENTRY ADDRESS in the table below. If an odd-numbered address is selected, the parity bit is inhibited and the data field will be the default listed in the Address and Register Selection chart in Figure 1. Parity errors can be forced by selecting the odd number address for the register being tested. ENTRY REGISTER PARITY DEFAULT FUNCTIONAL ADDRESS TESTED INHIBIT DATA AREA 21 22 23 24 25 26 27 28 29 2A 2B 2C 20 2E 2F 3a CCC CCC WCR \tICR RCR RCR DCB DCB ,.,100 ~1DO Bf'IR BHR LSP LSP BCSL BCSL Yes No Yes No Yes No Yes No Yes No Yes No Yes No Yes fio aa FF sa FF aa FF as FF aa FF as FF" aa FF ae FF Status Store Status Store Write Control Write Cont r(! 1 Read Data Read Data Drive-Adapter Drive-Adapter Maintenance Adapter f'laintenance Adapter Buffer Adapter Buffer Adapter f-li c roproce ssor f4icroprocessor Buffer Control Buffer Control Figure 1. Address and Register Selection Chart CARD LOCATION alA-AlG2 SlA-AIG2 81A-AIP2 FJIA-AIP2 alA-AlS2 alA-AlS2 alA-AlQ2 alA-AlQ2 alA-AlE2 alA-AlE2 81A-AIK2 SlA-AIK2 SlA-AID2 91A-A1D2 91A-A1l2 alA-AlL2 o o o IlEGISTER lOCATI ON FUNCTlON!.l AREA ERA ERB IHR ITA I1B JAH JAl PRR" LSP pCR PER PDR I'SR XRA OIA-AID2 Processor HOI MTI HOD HTO I'RR" OIA-AIE2 11nlntenar,';r CCA CCC CDR pRR" CER CHR CRR OlA-AIG2 Status Store BCC BCR BCPC BCpll BCPL SCSE BCSI1 BCSL BCSS PRR" BOC BOR BDPH BOPL BOSE BOSH BOSl BOSS BWRP 91A-AIL2 Buffer B069 BOAT CIIH"" CHH** BOGI BMR CHOT.... CHS"* BIA-AIK2 BufferAdapter OCB OCR OLR OIR OTR DSE PRR* llSC OSH OSL OSR 91A-AIQ2 OriveAdapter RCR ROC RER PRR* RPR RRe RSR 91A-AlS2 Read Data WCR WSE pRR* 61A-AIP2 Wri te Oat' o o o Routine EEFO 011600 Scope Loop Sync Address The scope loop routine consists of the following sync address. SYNC ADDRESS ae3A e93C ee3D ee3E ee4S 9a42 DESCRIPTION Set the PCR extend bits on Write the specified external register Read the specified external register Read, 'OR' the data and write it back Set the extend bits off Set user reset into the PRR register Figure 3. Scope Loop Sync Addresses ~ ITC -- * lhis register is used to send a check reset to .,"" or all functional areas. When the register is written the 'check reset' line is activated, at. rI if bit 3 is inactive, all functional areas whos 0 assi gned hi tis active perforM a ched reset. ** lhese Buf fer Adapter regi sters wi 11 be tested; OJ Id.1f;e of the unmarked Buffer Adapter registers if tht ",."I.r,.l unit has the 4.5 Hhls channel adapter or the Extended n~ta Recording Format feature. Figure 2. Diagnostic and External Register :h;'lrt 3480 MI EC A57723 tr) CopyriplrtlBM Corp. 1982,1989 IBM Con fidential Routine EEFO OIAG 600 o o o () o {) {) () n o o o o o o o o Scope Loop Utiliiy - Rouiine EEfO Routine EEFO This routille pel mlts the service representative (SR) to setect and loop a regis tor in any of the eight control or adapter cards. Addresses, data, clock lines, alld so on, can also be scoped in the extelnal register area of the control unit using thIs scoping utility. Use the "xn Bus and Control Clocks" liming chart (seo EAD 1) as a gUldo when l,,::ing this scope procedure. Error Loop: All errors are ignored when this Inut,ne is running. Test Selection rhis chart shows which diagnostic is lIsed to test the externat registers. r------- -.------- ,.------,,.-------, DIAGNOSTIC --------- EEl2 EE 13 EEl4 The following screen dIsplays after routille I::EI-O has been selected. L IAG=(EEFO>-ENTER: PATTERN TTl I LSP PCR PER PDR PSR XRA DIA-AID2 Processor ENTRY REGISTER PARITY DEFAULf FUNCTIONAL ADDRESS TESTED INHIBIf DATA AREA -----_. 21 CCC Yes 00 Status Store 22 CCC No FF Status Store 23 WCR Yes 00 Write Control 24 WCR No FF Write Control 25 RCR Yes Read Data 00 26 RCR No FF Read Data 27 DCB Yes 00 Drive-Adapter 28 DCB Dri ve--Adapter No FF 29 MOO Yes Maintenance Adapter 00 2A MDO No FF Maintenance Adapter 2B BMR Yes Buffer Adapter 00 2C BMR Buffer Adapter No FF 2D LSP Yes Microprocessor 00 2E LSP No FF Microprocessor 2F BCSL Yes Buffer Control 00 30 BCSl Buffer Control No FF ---- o DIAG 600 Scope Loop Sync Address Tho scope loop routine consists of the following sync addruss. ,.---------------------------, SYNC ADDRESS DESCRIPTION - - - _._-----------------_._--- MDI MTI MDO MTO PRR* 01A-AIE2 003A 003C 003D 003E 0040 0042 Set the PCR extend bits on Write the spec1fied external register Read the spec1fied external reg1ster Read, 'OR' the data and write 1t back Set the extend b1ts off Set user reset 1nto the PRR register Maintendnce Figure 3. Scope Loop Sync Addr ..... ---_._- - - - - - - OIA-AIG2 Status Store OlA-AIL2 Buffer - _ .. _----- Parity errors can be forced by selecting the odd number addross for the register being tested. Figure 1. ERA ERB IMR ITA ITB JAH JAl PRR* CCA CER CCC CMR CDR CRR PRR* Four characters must be entered for the data patte I n to be valid. Valid TT patterns aro listed under ENTRY ADDRESS in the table below. If an odd-numbered addross is selected, the parity bit is inhibited and the data froid will be the default listed in the Address and Register Selection chart in Figure 1. ---_. LOCATION - - - - - - - - - . t - - - - -...- - - - - - _._----_.- Address for register selection Data field (enter 00) ----- ._----- ._---- REGISTER FUNCTIONAL AREA - - - - - - - - _._----- ._---_.__. - lE85 ----------- . TT II o CARD LDCAfION BCC BCR BCPC BCPII BCPl BCSE BCSII BCSt. BCSS PRR"* BOC BDR BOPII BOPl BDSE BOSIl BDSl BOSS BWRP BDGO BOGI BOAT BMf~ ._---_._----- 0IA--AIG2 0IA-AIG2 0IA-AIP2 0IA-AIP2 0IA-AIS2 01A-AIS2 01A--AIQ2 01A--AIQ2 01A-AIE2 0IA-AIE2 01A-AIK2 01A-AIK2 0IA-AID2 0IA-AID2 01A-All2 01A-All2 --- --- 01A-AIK2 ----- -- - -- OlA-AIQ2 DriveAddpter RCR RPf~ fmC RRC RER RSR PRR* OIA-AIS2 Redd Data WCR OIA-AIP2 Write Ddtd DCB OCR DLR OIR DTR DSE PRRA DSC OSf! OSt. DSR ITC - - - --------- ---- Address and Reglsler Selection Chari WSE Pf~R* '-------_. "* This register is used to send a check reset to any or all functjonal aredS. When the register is written the 'check reset' line is dctivated, and if bit 3 is inactive, al I functional areas whose assigned bit is active perform a check reset. Figure 2. 3480 EC336396 Diagnostic and Exlernal Reglsler Chari Routine EEFO DIAG 600 Scope Loop Utility - Routine EEFO (Continued) Routine EEFO Scope Loop Sync Address (Continued) Set the sync address by performing the following: The notes on this page refer to to the diagram on DIAG 615. The scope loop sync address provides a positive going sync pulse, when the microprocessor fetches an instruction from the selected address. The negative going part of this pulse should be used to sync the oscilloscope when scoping the XR timings for a specific part of the EEFO routine. The first Subsystem Clock SO time (after the negative transition of the sync pulse) starts that part of the XA timing sequence (see DIAG 610). 1. 2. 3. 4. 5. 6. 7. 8. Notes: This scope loop routine contains the following sync addresses. See DIAG 610 for the following reference key locations. SYNC ADDRESS eeJ8 D eOJA fJ OOJC EJ 0040 II 0042 B 0044 B Figure 1. 3480 Start routine EEFO running (see "Test Selection" on DIAG 600). Press the PF key on the MD. Enter a 2 (alter parameters). The screen displays, WANT TO ALTER TEST PARM? Press Yes. Enter sync address (xxxx). See Figure 1 on this page. On next display enter a 7 (run). IS THIS CORRECT? Press Yes. Attach the scope lead (on this control unit) to 01A-A1E2Z12. 2. SUPPORT DIAG CNTRL SECTION: EExx Izz ROUTIN: EEyy STS/RTNa Turns on both XR page selection XR address extend bits. Sets PCR bits 6 and 7 to one (equals XR page 0). They may already be on. Reads the XR selected in "Test Selection". During address selection the XR address bus contains the address of the selected XR. During read time, the XR data bus contains the data specified in the 'Data Used" (see Figure 1 on DIAG 6(0) in "Test Selection" that was written into the selected XR during sync address 0040. The following chart indicates which bits are active for anyone of the eight registers that can be selected with routine EEFO. I EXTEND XR ADDRESS BITS BUS BITS o1 XR REGISTER CCC WCR RCR DCB MDO BMR LSP BCSL Figure 2. Io To read the XR selected by the XR address and XR extended bits 0 and 1 at S18-S21 time. However, the XR data read from the selected XR is actually latched. 3. To aI/ microprocessors cards with XR registers. If active during 'XR addressed clock' time, a check 2 and 'XR error latched' are set. 4. The microprocessor card samples 'XR error ungated' during S9-S1O time for XR write, and S20-S21 time for XR read. 5. When the MP instruction decodes as an XR write, data is put on the XR data bus and write gate is turned on. 01234P I 1 234567 FUNCTIONAL AREA CARD LOCATION o0 000000 o C:l 0 0 0 C:l 000101 110000 100 1 1 1 101 1 1 0 111111 001010 Status Store Wri te Data Flow Read Clock/Format Dri ve-Adapter Mai nt. Adapter Buffer Adapter Mi croprocessor Buffer Adapter 0IA-AIG2 C:lIA-AIP2 01A-AIS2 01A-AIQ2 01A-AIE2 01A-AIK2 0IA-AID2 01A-AIL2 C:l 1 o1 o1 10 1 1 11 11 BA001, OF001, 01001, MP003, RG001, SS001, MA001, The logic pages used are: BA001, 01001, MA001, RG001, SS001. in the microprocessor card at S18-S19 time. Turns off both XR page selection XR address extend bits. Sets PCR bi ts 6 and 7 to zero (equals XR page A). Writes the XR that was selected in the "Test Selection". Duri n9 address selection, the XR address bus contains the address of the selected XR. During write time the XR data bus contains the data specified in the "Data Used" in "Test Selection" . See Figure 1 on DIAG 600. The logic card that contains the XR that is selected turns on its line to the MA card. Each line name identifies the card that it came from. For example, selecting the eGG register's XR turns on '-SS addressed' line to the MA card. The MA card checks the lines from all cards to ensure that only one XR is selected at a time. It also checks that one line is on during all XR operations. The logic pages used are: and MA002. If the following screen is displayed after setting up the scope loop and sync address, you can ignore it because the loop routine is still running. DESCRIPTION Sets the XR page to the page selected by the service representative. PCR bits 6 and 7, and XR XR extend bits 0 and I, respectively, are set to the XR page of the selected XR. See Figure 2 on this page. 1. DIAG 605 0038 - PGR bits 6,7 = 1,1 003A - PGR bits 6,7 0,0 003G - PGR bits 6,7 = XR page of selected XR (see Figure 2 on this page) 0040 - From EEFO's, data used in the write data test selection parameter 0042 - SR selected XR read data that was written in address sync word 0040 cycle The bidirectional XR data bus can have write data on it from SO-S14 time, but the selected XR writes at S5-S7 'XR load' time. The XR data bus can have read data on it at S18-S21 time, however, it is set into the microprocessor card's read data register (ROR) at S18-S19 time. Extend Bit and XR Register Chart . Reads, then writes the XR selected during "Test Selection". During address selection, the XR address bus contains the address of the selected XR. During read time, the XR data bus contains the data specified in the 'Data Used' (see Figure 1 on DIAG 6(0) "Test Selection" that was written into the selected XR during sync address 0040. During write time, the XR data bus contains the data that was read during the read part of this sync address. 6. Used by the MA to validate its 'one and only one' check. 7. To write the XR selected by the XR address and XR extend bits 0 and 1 at SO-S13 time. The XR write data is set on the XR data bus at SO-S13 time, but the selected XR sets at S5-S7 'XR load' time. The logiC pages used are: BA001, OF001, 0/001, MA001, RG001, SS001. 8. To all XR cards on logics pages BA001, OF001, 01001, MA001, RG001, SS001 and to BA003 from BA002 as '-XR load clock '. Scope loop Sync Addre.. Descriptions EC336396 ,0 Copynght IBM Corp. Routine EEFO 1984. 1965. 1966. 1967 #). 4 DIAG 605 o o o o o o o o Scope Loop Utility - Routine EEFO (Continued) o Routine EEFO o DIAG 610 M~croprocessor Clock (T Clock) ~IT7ITO/ 4 Tl ~1~T2 ~IIT3/'- T4 -./T5/T6IT7ITOI4 Tl ~1~T2 ~IT31'- T4 -./T5IT6IT7ITO Subsystem Clock (S Clock) - - - - - - - - - - -....~ 0 1 21314151617181911011111211314115161711811920210 1 21314151617181911011111211314115161711811920210 1 (5ync for addresses ~ 38, 3A, 3e, 40, 42, 44) , [EFO Sync Word Pu 1se --------+~ - - I I , (sync minus) ~------------------------------------------------------------------~ r----------, SYNC ADDRE5S (see DIAG 605 for 1 reference keys) ~----------+----------55-57 1 0038 -X~ Extend D L __________ BIts 0-1 -1. - - - - - -1- - - - - - - - - - - -C~n-b~ in-eithe~ ;t~t~ - - - - - - - - - - - - - - - 4- - - Both extend bits must be on here ---------.... ~ _____ - 1__ - - _ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .J. ______________________________________________ ~__________ r----------T----------S5-S7 1 003A L __________ ~ -~~t;x6:~d _______________________--1.[ = = = = _________ _ ~a~ ~e=i~ ~i~h~r=s~a~e= = = = .J.l__________..J1·4--- Both extend bits must be off --------+~ r----------T----------S5-57 003C -XR Extend Bits 0-1 II L __________ ~ Extend bits are set for the XR page of the XR register selected by the SR _________ _ r----------T----------S5-57 0040 -XR Extend Bits 0-1 II L __________ ~ Extend bits are set for the XR page of the XR register selected by the 5R _________ _ r----------T----------55-S7 0042 -XR Extend Bits 0-1 o L __________ ~ Extend bits are set for the XR page of the XR register selected by the SR _________ _ r----------T----------55-57 0044 -XR Extend Bits 0-1 m L __________ 3480 MI ~ EC336395 ~ CopYTight IBM Corp_ 1984, 1985 Extend bits are set for the XR page of the XR register selected by the 5R _________ _ Routine EEFO DIAG 610 Scope Loop Utility - Routine EEFO (Continued) Microprocessor Clock (T Clock) Subsystem Clock (5 Clock) Routine EEFO ~IT7ITOI. ~ 0 1 Tl ~ I~T2 ~IT31'_ T4 2131415161718191101111121131411516171181192021 G -'IT5IT6IT7ITOI. Tl ~ I~T2 ~IT31'_ T4 -'IT5IT6IT7ITO 1 21314151617181911011111211314115161711811920210 1 DIAG 615 Notes are on DIAG 605. -514-515 I This clock pulse cause the XR address busL-, Ito set from the CS address bus (even pty). , ___ I = = = = = = = = = = = = = = = = = = = = = ~~~·~_M~u~s~t~~b~e~-v_-a_-_l-·_I-d~~b_y~~-'~_I_A_d_d_re_s_s -XR Address Bus (p, 0-4) I __o_f__t_h_e__ XR________________________ f Read f Wr i te ~~r -_-_-_-_-_-_-_-_-_-~-_-_= (i f not a 1ready on) l___________________________~r_-_-_-_-_-_-_-_-_-_-_-_- -MP (User) XR Addressed -_ -_ lL._M_u_s_t b_e_v_a_l_i_d __h_e_r_eone __ XR selected. . for __ test of only See Note 1 . . + Read or wr i te wi 11 not __+.1..-____________ • set if address bus par i ty ~ Resets if the next MP errors are detected instruction is for a XR on a different card l Resets if the address bus bitsl change. I '--__---'r- -518-521 See Note 2. -XR Read Gate When read gate is active, the selected XR register contents are placed on the XR data bus. -XR Error Ungated See Note 3. Becomes active during a read when ~I,----------, the MA card detects odd parity on the XR address bus, or more than one XR is addressed. l Becomes active during a write when the MA card detects odd parity on the XR bus, or more than one XR is addressed. Also, it comes on if the XR user card detects a data bus parity error during the write. I I ,-------,r- -520-521 -XR Error Ungated Sample Clock (internal - cannot be scoped) Sample XR selection error Sample XR selection error -----------------------------U-s-e-d--o-n-l-y--w-h-e-n--re-a-d--g-a-t-e---is-o-n-.---.--'I r------------------------,~r._--U-s-e-d--o-n-l-y--w-h-e-n--w-r-i-t-e--g-a-te---is--o-n-.---- rt- Wrong parity during a write causes 'XR error ungated' from the XR user card to become active. Wrong parity is detected during read by the MP card, but no external error line is avai lable. The error --. ,..~-(-R-e-a-d-)-----(-W-r i t e) See Not e 5. code describes the error. Data from the XR set on the data bus. -XR Data Bus (p, 0-7) See Note 4. 1 t= -XR Addressed Clock Used only on a read cycle. --.~I--~ '--______...01 +-- See Note 6. Used on 1y on a wr i te cyc Ie. -50-513 L-Becomes active if an instruction specifies -XR Write Gate I See Note 7. that an XR is to be written. See Note 8. -59-510 -XR Load 3480 MI '--_____...II+_ Used when write gate is not on. (this line is a free-running clock.) '--____...II+_ When write gate is on, data is sent from the XR data bus to the selected XR. Routine EEFO EC336395 It CopYflght IBM Corp. 1984, 1985 f) \ DIAG 615 o o o Drive Patch Load Utility - Routine EEF 1 o o o o o o o Routine EEF 1 DIAG 620 Routinp. fEF 1 DIAG 620 This routine is used to automatically read microcode from the IML diskette and then send it to the drive. Error Loop does not apply to this routine. Test Selection This routine cannot be selected directly from the maintenance device (MOl. When any routine is loaded that requires drive microcode patches from the IML diskette. this routine is automatically loaded. VIIIO MI " I °'1''1'''01" 111M I .".' "111'1 I'HI', . £1££. 1'111' • Drive Command Exerciser Drive Command Exerciser The drive command exerciser is a group of programs, on the support diskette, which permits you to test a suspect drive for failures. The support diskette is loaded on a maintenance device (MD), which is connected to a control unit. The drive command exerciser issues commands to the suspect drive in a concurrent maintenance mode. The exerciser can be used to isolate drive motion problems or failures caused by a specific command sequence. You must select one channel adapter and one drive to run the commands on. The maintenance device (MD) will display the channel adapters you are allowed to select from. Only those channel adapters that the control unit microcode is able to communicate with, will be displayed. If you select a channel adapter that is not on the MD display, an error is caused. You can run a predefined group of commands to the drive by selecting routine 1 or 2, or you can run a group of commands of your own selection, up to a maximum of eight commands. Note: Routine 2 cannot be looped because the last command of that routine is a Rewind Unload. Any group of commands that contains a Rewind Unload (RUN) command should not be looped, because it can cause errors. Any motion command issued to a drive after a Rewind Unload (RUN) command will cause an error. A command is entered by keying in the command acronym and pressing the ENTER key. When all the commands in the chain are entered, a null entry (the ENTER key is pressed again) signals the program that all the command entries have been made. A run mode option selection screen is then displayed. Once a command chain is entered and the run mode is selected, the MD sends the commands to the control unit. Each command is executed in turn. Status from the control unit is sent to the MD and is analyzed by the exerciser microprogram. Depending on the status returned from the control unit, one of the following actions are taken: • • • If the command sent receives a good beginning and ending status from the device, the next command is issued. If the status returned is a channel command retry, the same command is reissued. Commands Commands are entered as acronyms by way of the maintenance device keyboard/display. If additional data such as record number, data length, and number of blocks is required, the exerciser microprogram will request the information. The following commands are supported by the drive command exerciser: • • • • • • • • • • • • • • • • • • • • • • • • BSB - Backspace block BSF - Backspace file DSE - Data security erase ERG - Erase gap FSB - Forward space block FSF - Forward space file LDD - Load display LOC - Locate block MDS - Mode set NOP - No operation RBI - Read block 10 RBK - Read backward RBL - Read buffered log RDF - Read forward REW - Rewind RUN - Rewind unload SID - Sense path/group 10 SIO - Sense I/O SNS - Sense TIO - Test I/O WRT - Write to tape with synchronize buffer command WTM - Write tape mark RES - Reserve device REL - Release device Execution run mode options are: • Once: The command or command chain executes once. • Continuous Loop: The loop continues until an MD function key is pressed, or an error is detected. If an error is detected, the loop ends and an error message is displayed on the M 0 keyboard/display. The error message is followed by 32 bytes of sense information. Note: The loop option should not be selected if you are using the Rewind Unload (RUN) command. If loop is used with a group of commands containing Rewind Unload, an error will occur. • III Copyright IBM Loop 255 Times: The command or command chain loops 255 times, or until an error is detected. If an error is detected, the loop ends and an error message is displayed Error Display If an error is detected while the drive command exerciser is executing, the following error screen is displayed. The first and second lines are used to display an error message that describes the error. The last line is used to indicate the command that was executing when the error occurred. (Error Message) ON THE COMMAND: (Command) NO ROOM IN BRT TO CREATE REC DEVICE IS NOT ONLINE BUFFER DATA NOT CORRECT DEFERRED UNIT CHECK CHANNEL TRANSFER ACTIVE SNS ERROR MATCH CODE MATC Error Messages The following error messages are displayed on lines 1 and 2 of the MD keyboard/display when an error is detected while the drive command exerciser is executing. LOOK AT SENSE FOR PROBLEM INCORRECT NUMBER OF DATA BYTES SNT DEVICE IS IN USE CANNOT RELEASE, NOT RESERVED INVALID DIAGNOSTIC OP-CODE INVALID CHANNEL OP-CODE CANNOT SCHEDULE OPERATION SENSE HAS ERROR DATA TIMEOUT ALLOC BUFF SW ERR OUR. WRTCARR WCA ORDER ERR OUR. WRTCACC WCA ORDER ERR OUR. DIAGINT WCA ORDER TIMEOUT DURING PMA RESP. ERROR PROCESSING RBSSSS ORDER ERR OUR. DIAG MODEWCA ORDER UNIT CK END STAT FROM DV ERR DURING SWB SSS ORDER ERR DURING RBE SSS ORDER ERR OUR. RDCADC RCA ORDER ERR OUR. WTCADS WCA ORDER DIDNT SEE IBG OUR LWR CMND BCSE NOT COMP OR FRU ACTIVE BOSE FRUS ACTIVE ATTEMPTING TO RD INVAL CS RD BUFF POINTERS FOR TM SET OF DIAG MODE FAILED ERR OUR DEV SEL SEQUENCE ERR OUR DEV CMND SEQUENCE RESET OF DIAG MODE FAILED DO RBP CMND B4 DEL REC TIMEOUT ENDING LWR OP FOUND DEVICE XFER ACTIVE Drive Command Exerciser 19B4. 19B5 f) BUFFER IS IN USE XR ERROR EC336395 corp. CHANNEL COMMAND RETRY NO BUFFER RECORDS PRESENT NEED RES TO EXECUTE COMMAND Run Mode Options THE TAPE IS FILE PROTECTED DEVICE IS NOT READY Status and error data sent to the MD keyboard/display contains the same information as would normally be sent to the host system. INVALID DATA WITH COMMAND For write data commands that execute in tape write immediate mode (SYN - Synchronize buffer), block size (1 K increments to 32K) and block count (1 to 256) must be defined. If the status returned is a unit check, the program gets sense data from the control unit and displays an error message followed by the sense data. 3480 MI on the MD keyboard/display. The error message is followed by 32 bytes of sense information. DIAG 720 ~) DIAG 720 o o The drive command exerciser is a group of programs, on the support diskette, which permits you to test a suspect drive for failures. The support diskette is loaded on a maintenance device (MD), which is connected to a control unit The drive command exerciser issues commands to the suspect drive in a concurrent maintenance mode. The exerciser can be used to isolate drive motion problems or failures caused by a specific command sequence. You must select one channel adapter and one drive to run the commands on. The maintenance device (MD) will display the channel adapters you are allowed to select from. Only those channel adapters that the control unit microcode is able to communicate with, will be displayed. If you select a channel adapter that is not on the MD display, an error is caused. You can run a predefined group of commands to the drive by selecting routine 1 or 2, or you can run a group of commands of your own selection, up to a maximum of eight commands. Note: Routine 2 cannot be.looped because the last command of that routine is a Rewind Unload. Any group of commands that contains a Rewind Unload (RUN) command should not be looped, because it can cause errors. Any motion command issued to a drive after a Rewind Unload (RUN) command will cause an error. A command is entered by keying in the command acronym and pressing the ENTER key. When all the commands in the chain are entered, a null entry (the ENTER key is pressed again) signals the program that all the command entries have been made. A run mode option selection screen is then displayed. Once a command chain is entered and the run mode is selected, the MD sends the commands to the control unit Each command is executed in turn. Status from the control unit is sent to the MD and is analyzed by the exerciser microprogram. Depending on the status returned from the control unit, one of the following actions are taken: • • • If the command sent receives a good beginning and ending slatus from the device, the next command is issued. If the status returned is a channel command retry, the same command is reissued. If the status returned is a unit check, the program gets sense data from the control unit and displays an error message followed by the sense data. o o o o o Drive Comm! Exerciser ERR DURING RBE SSS ORDER Commands Error Display Commands are entered as acronyms by way of the maintenance device keyboard/display. If additional data such as record number, data length, and number of blocks is required, the exerciser microprogram will request the information. If an error is detected while the drive command exerciser is executing, the following error screen is displayed. ERR OUR. WTCADS WCA ORDER The first and second lines are used to display an error message that describes the error. The last line is used to indicate the command that was executing when the error occurred. BCSE NOT COMP OR FRU ACTIVE ERR DUR. RDCADC RCA ORDER The following commands are supported by the drive command exerciser: • • • • • • • • • • • • • • • • • • • • • • • • BSB - Backspace block BSF - Backspace file DSE - Data security erase ERG - Erase gap FSB - Forward space block FSF - Forward space file LDD - Load display LOC - Locate block '\ MDS - Mode set NOP - No operation RBI - Read block 10 RBK - Read backward RB L - Read buffered log RDF - Read forward REW - Rewi nd RUN - Rewind unload SID - Sense path/group 10 SIO - Sense I/O SNS - Sense TIO - Test I/O WRT - Write to tape with synchronize buffer command WTM - Write tapemark RES - Reserve device REL - Release device DIDNT SEE IBG OUR LWR CMND BOSE FRUS ACTIVE ATTEtJlPTING TO RD INVAL CS (Error Hessage) ON THE C!H4ANO: (Conmand) RD BUFF POINTERS FOR TM SET OF DIAG MODE FAILED ERR OUR DEV SEL SEQUENCE ERR OUR DEVCMND SEQUENCE RESET OF DIAG MODE FAILED Error Messages DO RBP CMND B4 DEL REC TIMEOUT ENDING LWR OP The following error messages are displayed on lines 1 and 2 of the MD keyboard/display when an error is detected while the drive command exerciser is executing. LOOK AT SENSE FOR PROBLEM INCORRECT NUMBER OF DATA BYTES SNT DEVICE IS IN USE INVALID DATA WITH COMMAND CANNOT RELEASE, NOT RESERVED NEED RES TO EXECUTE COMMAND INVALID DIAGNOSTIC OP-CODE INVAUD CHANNEL OP-CODE For write data commands that execute in tape write immediate mode (SYN - Synchronize buffer), block size (1K increments to 32K) and block count (1 to 256) must be defined. CANNOT SCHEDULE OPERATION SENSE HAS ERROR DATA TIMEOUT ALLOC BUFF SW ERR OUR. WRTCARR WCA ORDER Run Mode Options Execution run mode options are: ERR OUR. WRTCACC WCA ORDER .. ERR OUR. DlAGINT WCA ORDER • Once: The command or command chain executes once. TIMEOUT DURING PMA RESP. • Continuous Loop: The loop continues until an MD function key is pressed, or an error is detected. If an error is detected, the loop ends and an error message is displayed on the MD keyboard/display. The error message is followed by 32 bytes of sense information. FOUND DEVICE XFER ACTIVE Note: The control unit error light can blink on and off under certain normal operating conditions. Real errors will be reported on the error display. Note: The loop option should not be selected if you are using the Rewind Unload (RUN) command. If loop is used with a group of commands containing Rewind Unload, an error will occur. • Loop 255 Times: The command or command chain loops 255 tirnes, or until an error is detected. If an error is detected, the loop ends and an error message is displayed on the MD keyboard/display. The error message is followed by 32 bytes of sense information. THE TAPE IS FILE PROTECTED DEVICE IS NOT READY CHANNEL COMMAND RETRY NO BUFFER RECORDS PRESENT BUFFER IS IN USE NO ROOM IN BRT TO CREATE REC DEVICE IS NOT ONLINE BUFFER DATA NOT CORRECT XR ERROR DEFERRED UNIT CHECK Status and error data sent to the MD keyboard/display contains the same information as would normally be sent to the host system. CHANNEL TRANSFER ACTIVE SNS ERROR MATCH CODE MATC ERROR PROCESSING RBSSSS ORDER ERR OUR. DIAG MODEWCA ORDER UNIT CK END STAT FROM DV ERR DURING SWB SSS ORDER 3480 MI EC A57723 f') Copyright IBM Corp. 1982. 1989 IBM Con fidential Drive Command Exerciser DIAG 720 t) o o () o () u () o o o o o o o o o o Drive Command Exerciser (Continued) Drive Command Exerciser (Continued) o o DIAG 721 Drive Command Exerciser Diagram *** MAIN MENU *** ENTER A NUMBER FROM THE FOLLOWING LI ST: l-SUBSYS DIAGNOSTICS 2-SUBSYS DSPLYIALTER 3-SUPPORT UTILITIES * END OF LI ST * YOU CAN USE PREDEFINED COMMANDS OR YOU CAN USE YOUR OWN LIST. (YES) DO YOU WANT PREDEFINED COMMANDS? (1) 1= 2= 3= 4= MSG7 INSERT TAPE IN DRIVE x AND MAKE IT READY SELECTED DIAG. BASIC CU TESTS DR CMD EXERCISER MDIMA DIAG. I(3) (NO) ENTER COMMAND ONLY. SEE REF TEXT FOR ABBREVIATIONS. (3 ) THIS PROGRAM LETS YOU SELECT A CHANNEL AND A DRIVE AND CHAIN COMMANDS (REF) - 1= ROUTINE 1 2= ROUTINE 2 3= MANUAL ENTRY # 2 DOES NOT LOOP (ll =========~========= Up to eight commands T (2) can be entered, one at a time. Press ENTER ONLY THE FOLLOWING CHANNEL ADAPTERS ARE ACTIVE. CHOOSE ONE! ABC 0 ENTER LOGICAL ADDRESS OF THE DRIVE TO BE TESTED (O-F) SELECT MODE 1= ONCE; 2= UNTIL ERROR 3= LOOP 255 RELEASE DRIVE REWIND UNLOAD WRITE TAPEMARK NO OPERATION LDD= RBL= WRT= RDF= LOAD DISPLAY READ BUFFER LOG WRITE TO TAPE READ FORWARD RBI= SNS= SID= SIO= READ BLOCK 10 READ SENSE SENSE 10 SENSE 10 RBK= LOC= MDS= TIO= READ BACKWARD LOCATE BLOCK MODESET TEST 10 I EC A47957 C Copyright IBM Corp. 1984. 1985. 1986. I (REF)- 1= 2= NO 3= RUN ONCE THROUGH LOOP FOREVER IF ERROR OCCURS LOOP 225 TIMES PRESS ENTER TO START PRESS ANY FUNCTION KEY TO STOP. 1= 2= 3= 4= (3) I I FSF= BSF= ERG= DSE= (4) I See Note 1. See Note 2. I REPEAT THE SAME CHANGE OPTIONS NEW COMMANDS END PROGRAM (\) (I' BEFORE YOU CONTINUE ENSURE THAT THE CUSTOMER HAS VARIED DRIVE X OFFLINE. OF RUN. LOOP OCCURS TIMES FSF,WRT (511x),WTM, BSF,LOC,LOC,BSF,LDD, RUN I REL= RUN= WTM= NOP= ========== ========== REMOVE THE TAPE FROM THE DRIVE YOU WANT TO USE BEFORE YOU CONTINUE BSFlLOC~RDF(10X), RBK lOx ,FSF. 2=REW,WTM,DSE,REW ... BSB=BACK SPACE BLOCK FSB= FWD SPACE BLOCK RES= RESERVE DRIVE REw= REWIND (REF) 1=REW,WRT(16x),WTM, ========= ~ Return to MAIN MENU ========= FWD SPACE FILE BKWD SPACE FILE ERASE GAP DATA SEC ERASE Note 1: The actual number of blocks written to tape using the write command is twice as many as entered on the MD keyboard. Note 2. Read commands will read multiple blocks from the drive. The next read command will purge the buffer and read the following block from the drive. ======L===== Return to the ENTER COMMAND ONLY screen Drive Command Exerciser (Continued) 3480 MI 1987 DIAG 721 Drive Command Exerciser Details The Drive Command Exerciser programs are written on the support diskette. Once the support diskette has been placed in the maintenance device and the control program has been loaded, the MD display screen indicates the control unit serial number and the EC level and part number of the support diskette. Drive Command Exerciser Details Press ENTER: The following screen displays. ONLY THE FOLLOWING CHANNEL ADAPTERS ARE ACTIVE. CHOOSE ONE! ABC D Press ENTER: The following screen displays. *** MAIN MENU *** ENTER A NUMBER FROM THE FOLLOWING LIST. • • • A YES response to "Do you want predefined commands?" causes the following screen to display: Press ENTER: The following screen displays. SELECT MODE 1= ONCE; 2= UNTIL ERROR 3= LOOP 255 1 = ROUTINEl 2 = ROUTINE2 3 = MANUAL ENTRY # 2 DOES NOT lOOP The channel adapter that is to be tested is selected from this display. • ONCE - The commands run one time. REW, WRT(16x), WTM, BSF, LOC, RDF(10x), RBK(10x) and FSF commands. Enter an At 8, C, or 0: The following screen displays. CONTINUOUS LOOP - The loop continues until an MD lunction key is pressed, or an error occurs. "an error is detected, the loop ends and an error message is displayed on the MD keyboard/display. The error message is followed by 32 bytes of sense information. Press ENTER: The following screen displays. ENTER UNIT ADDRESS OF THE DRIVE TO BE TESTED. (O-F) I=SUBSYS DIAGNOSTICS 2=SUBSYS DSPLY/ALTER 3=SUPPORT UTILITIES * END OF LIST * • Enter a 1: The following screen displays. And the contents 01 routine 2: REW, WTM, DSE, REW, FSF, WRT(511x). WTM BSF, LOC, LOC, BSF, LDD, and RUN commands. • A NO response to "Do you want predefined commands?" causes the following screen to display: Enter the drive address: The following screen displays. 1= 2= 3= 4= SELECTED DIAG. BASIC CU TESTS DR CMD EXERCISER MDjMA DIAG. LOOP 255 TIMES - The command or command chain loops 255 times. If an error is detected, the loop ends and an error message is displayed. The error screen is followed by another screen that contains 32 bytes of sense information. If one of the routines is selected, each command executes in the sequence noted above. This entry identifies the tape drive that will be tested. Note: In a dual control unit configuration the MD can be attached to either control unit; therefore, any drive can be tested. Note: The loop option should not be selected if you are using the Rewind Unload (RUN) command. If loop is used with a group 01 commands containing Rewind Unload, an error will occur. Select the run mode and press ENTER: The following screen displays. ENTER COMMAND ONLY. SEE REF TEXT FOR ABBREVIATIONS. BEFORE YOU CONTINUE ENSURE THAT THE CUSTOMER HAS VARIED DRIVE X OFFLINE. PRESS ENTER TO START PRESS ANY FUNCTION KEY TO STOP. Enter a 3: The following information screen displays. • THIS PROGRAM LETS YOU SELECT A CHANNEL AND A DRIVE AND CHAIN COMMANDS. X = Current drive being tested. Press ENTER: The following screen displays. MSG7 INSERT TAPE IN DRIVE X AND MAKE IT READY • Commands can be entered from this screen only. • Up to eight commands can be entered, one at a time. • If the command abbreviations are not known, pressing the REF key will cause prompting screens to display. See the Drive Command Exerciser Diagram for the content 01 the screens (DIAG 721). Press ENTER: The following screen displays. REMOVE THE TAPE FROM THE DRIVE YOU WANT TO USE BEFORE YOU CONTINUE • Remove the cartridge completely from the drive. 3480 1= 2= 3= 4= REPEAT THE SAME CHANGE OPTIONS NEW COMMANDS END PROGRAM Pressing RET causes the 'ENTER COMMAND ONLY' screen to return. Alter the drive is ready, press ENTER. The lollowing screen displays. • • Press ENTER: The following screen displays. Pressing REF causes the next prompting screen to display. This entry prepares the drive you want to use so the MD can exercise it. DO YOU WANT PREDEFINED COMMANDS? OF RUN LOOP OCCURS TIMES Pressing the REF key causes a prompting screen to display that defines the selections. If you press the ref key while the above display Is active, you will be shown the contents 01 routine 1: Any adapter not shown is either not working correctly or not present. DIAG 722 • See the Drive Command Exerciser Diagram (DIAG 721) for the paths taken for each selection. • If routine 2 is being used, you cannot change options. "you select option 2 it will default to option 1. Press ENTER after each command abbreviation Is keyed In. Note: II the LOD, WRT, LOC, or MDS commands are entered, additional prompting screens will display. See Prompting Screens on DIAG 725 for the content of the screens. Drive Command Exerciser Details EC336396 ~) ~) ') \ ... DIAG 722 o o o o o o Device Command Exerciser Details (Continued) o Device Command Exerciser Details (Continued) Write To Tape (WRT) Prompting Screens o o o DIAG 725 Modeset (MDS) Load Display (LDD) ENTER HEX NUMBER 01 TO IF FOR BLOCKSIZE. THESE ARE MULTIPLES OF 1024 BYTES. DO YOU WANT TO USE THE DEFAULT MESSAGE AND CONTROL? (NO) I l(YES) The bits used to enter one byte of data for a modeset instruction are defined as follows: ====== ======= Return to the ENTER COMMAND ONLY 5 creen • ENTER ONE HEX BYTE FOR CONTROL OF THE DISPLAY. ENTER ONE HEX BYTE OF DATA FOR MODESET INSTRUCTION. ENTER IN HEX THE NUMBER OF BLOCKS TO WRITE FROM 0001 TO FFFF. • Bits 0 and 1 - Tape Format - =====-= - 00 01 10 11 - Write 18 track format Reserved Reserved Reserved Locate Block (LOC) • ! ENTER UP TO SIXTEEN CHARACTERS TO BE DISPLAYED ON THE DRIVE. ENTER LOCATE ADDRESS AS 01000005. ERROR OCCURS IF PAST THE WRITTEN AREA. • Bits 0,1, and 2 - • - Permit drive message to overlay message No overlay unless tape is removed No overlay until drive is ready Display both messages until cartridge is removed, then display 9 - 16 until the drive is ready. 0 - Execute supervisor commands 1 - Inhibit supervisor commands • Bits 4. 5, and 6 - Reserved • Bit 7 - Inhibit Control Unit Error Recovery. - 0 - Automatic error recovery takes place 1 - Temporary read and write errors reported as permanent errors. Bit 3 - • 000 001 010 111 0 - Buffered write 1 - Tape write mode Bit 3 - Inhibit Supervisor Commands - The bits used to control the load display option are defined as follows: • Bit 2 - Write Mode 0 - Display message specified by bit 5 1 - Display both messages Bit 4 1 - Flash message specified by bit 5 • Bit 5 - • 0 - Display bytes 1 through 8 1 - Display bytes 9 through 16 Bits 6 and 7. - 3480 MI Reserved ECA57693 © Copyright IBM Corp. 1984. 1985. 1986. 1981. 1988 Device Command Exerciser Details (Continued) DIAG 725 Notes Notes 3480 MI Notes EC336395 DIAG 755 DIAG 755 II> Copyright IBM Corp. 1984, 1985 ~) ~) 3 £ J l #) \. ~) :) :J (1 ~ ~1 content. o o Data Fields . . . . . . . . . . . . . . . . . . . . . Functional Areas ......................................... . External Register Address Cross-Reference Table . . . . . . . . . . . . . . . . . . . . . . External Register Addressing .. , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Externals Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cross Reference Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Buffer Control Card (01A-A 1L2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , Buffer Adapter Card (01 A-A 1 K2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Drive Adapter Card (01A-A102) ............................... Maintenance Adapter Card (01A-A1 E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . Microprocessor Card (01 A-A 102) .............................. Read Data Flow and Read Control Card (01A-A1S2) . . . . . . . . . . . . . . . . . . . Status Store Card (01 A-A 1G2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Data Flow Card (01A-A1P2) .............................. XRA Value to Register Name Cross Reference Table . . . . . . . . . . . . . . . . . . 5 5 5 5 5 5 10 10 10 10 12 External Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BCPH Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BCPL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BCSE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "BCSS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BOSE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BDGO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BDG1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BDPH Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BDPL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BWRP Register ........................................... CAE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CAS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CCA Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CCC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CER Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 'CHM Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 'CMDT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -CMM Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 'CMRP Register . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . 'CMRS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 'CMS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CRR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DCB Register .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . OCR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DLR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DTR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ERA Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ERB Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MOl Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MOO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSB Register ............................................ MTI Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MTO Register ............................................ PCR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PER Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PRR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PSR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RCR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ROC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15 15 15 15 20 20 25 25 30 30 30 33 35 35 35 35 36 36 36 36 37 37 3480 Mf EC A57723 If: CopyrighllBM Corp. 1982,1989 3 3 o o o o o content40F 1 75 RER Register RPR Register RRC Register RSR Register WCR Register WSE Register XRA Register . .. _ . . . . . . . . . . . . . . . . . . . . . . . 80 80 82 82 85 85 Buffer Adapter Internal Register Bit Definitions . . . . . . . . _ . . . . . . _ . . . . . . . . 'Channel Byte Count Registers . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . - - . . 'CMDO Register . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . . . . . . . . 'CMD1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 'CMFL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . 'Configuration Registers . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . . . • Diagnostic Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • Error Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 88 88 88 88 88 88 88 Control Storage Tables and Logs CSTTable . . . . . . . . . . . . . . . . . . . CUTTable . . . . . . . . . . . . . . . . . . . OGHELO Log . . . . . . . . . . . . . . . . . DOT Table . _ ................ LOT Table . . . . . . . . . . . . . . . . . . . PGM Table . . . . . . . . . . . . . . . . . . PGTTable . . . . . . . . . . . . . . . . . . . SNERRH Table . . . . . . . . . . . . . . . . 90 90 . . . . . . . . ...........................' 105 117 120 125 130 140 145 Drive Status Bits 0·15 . . . . . . . . . . . . . 150 Drive External Registers . . . . . . . . . . . 155 Note: Registers marked with a • mayor mi y not be present depending upon the EC level and installed features. 40 40 40 45 45 45 50 50 55 55 55 60 60 60 62 65 65 65 70 70 70 IBM Cc nfid~ntial Contents OF 1 (J () () () o {) {l {) f) () o o o o o o o Contents Data Fields F;.mctlo~a: A~eas Externa: "egister Address Cross-Reference Table External Register Addressing Externals Registers Cross Reference Tables Bu~fer Control Card (0, A-A 1 L2) Buffer ,t..dapter Card (C1A-A1K2) Drive Adapter Card (01 A-A 1Q2\ Maintenance Adapter Card (01A-AIE2) Microprocessor Card (01 A-A 102) Read Data Flow and Read Control Card (01 A-A 1S2) Status Store Card (01 A-A 1G2) Wr;te Data F!ow Card (01 A-A 1P2) XRA Value to Regis:er Name Cross Reference Table External Register Bit Definitions BCPH Register BCPL Register BCSE Register BCSS Register BOSE Register BDGO Register BDG1 Register BDPH Regis:er BOPL Register BWRP Register CAE Register CAS Register CCA Register Register CER Reg:ster 'CHM Reg;ster 'CMDT Register 'CMM Register 'CMRP Register 'CMRS Regis:er 'CMS Register eRR Register DCB Register DCR Register DIR Register DLR Register DSE Register DTR Register ERA Register ERB Register MCR Register MOl Register MOO Register MSB Register MTI Register MiO Register PCR Register PER Register PRR Register PSR Register RCR Register RDC Reg!ster ecc 3430 MI EC A57721 3 3 3 3 5 5 5 5 5 5 10 10 10 10 12 15 15 15 15 20. 20 25 25 30 30 30 33 RER Register RPR Register RRC Register RSR Register WCR Register WSE Register XRA Register 75 80 80 82 82 4.5 Mb/s Buffer Adapter Internal Register Bit Definitions 'CTEO Register 'CTXE Register 'CMFL Register 'CMDO Register 'CMD1 Register 88 88 68 o o o Contents OF 1 Contents OF 1 85 85 88 88 88 Control Storage Tables and Logs CST Table . CUT Table DGHELO Log DOT Table LDT Table PGM Table PGT Table SNERRH Table 90 90 105 Drive Status Bits 0-15 150 Drive External Registers • These registers are EC sensitive and mayor may net be present. 155 117 120 125 130 140 145 35 35 35 35 36 36 36 36 37 37 40 40 40 45 45 45 50 50 55 55 55 60 60 60 62 65 65 65 70 70 70 Data Fields Data Fields Functional Areas The microprocessor communicates data that can be used for problem analysis via external registers. These one byte wide registers are distributed throughout the control unit and are attached to the processor by the External Register Interface. The registers may be read only, write only, or read/write. Functional areas serviced by the registers are the following: • Buffer area and control • Drive adapter interface XR PAGE: XR page select address. The XR page defines groups of external registers that have the same address. That is, two external registers may have the address hexadecimal 02, but they are defined as different locations by the XR page. The pages are controlled by the XR address extend bits 0 and 1, shown on logic page MPOO 1, as follows: XR Address Extend Bits 1 Maintenance adapter o Microprocessor 0 0 1 1 • Read data flow • Status store • Write data flow Examples of Address Bus/XRA Translation 0 1 0 1 Page A B Note: The location of bit definitions for individual registers can be found in the table of contents. Storage fields that are loaded by the microcode with subsystem error and status information are also defined. External Register Address Cross-Reference Tables • REGISTER NAME: Formal name of the register. • REGISTER MNEM/TVPE: MNEM - Mnemonic name of the register. TYPE - Type of register. R = Read W = Write R/W = Read and Write XR Page=D XR Address Bus = Hex 00 o --L o 1 1 1 The external register address value as it appears on the Maintenance Device (MD) display. Addresses for the XR registers are generated from the XR address bus and the XR address extend bits 0 and 1. The extend bits become bits 0 and 1 of the XRA register. Bits 0, 1, 2, 3, 4, and P of the XR address bus become XRA register address bits 2,3,4,5,6, and 7. XR register address bits 2, 3, 4, 5, 6, and 7 are used to address multiple XR registers and the extend bits control which register (page) will be selected. The XR address extend bits do not have any parity bits associated with them. The parity of the XR address bus is even. XR Address Extend Bits 0 1 XR Address Bus Bits E o XR Address E!us Bits XR Address Extend Bits 2 234 567 1 0 0 0 1 0 1 T XR o 0 .1. _ _' - - _ o12 3 4 P o0 0 0 0 I Extend Address Bits XR Address Bus Bits 01Add 0 to maintain even parity for address bus bits 0-4 o 0 0 0 0 0 I The actual register address in the buffer page. Both hexadecimal and decimal values are provided. External Register Addressing The external register cross-reference tables contain the following information: XRA value = E2 XRA Value Bits EXAMPLE 1 1 1 XRA VALUE: XR to XR Page/Address Bus Examples EXAMPLE 1 XR Page/Address Bus to XRA C 0 ADDRESS: • DF 3 I c o XRA value EXAMPLE 2 EXAMPLE 2 XR Page=B XRA value = Al XRA Value Bits XR Address Bus = Hex 13 XR Address Extend Bits XR Address Bus Bits A 0 1 2 3 4 5 6 7 0 0 o 1 1 0 1 o 0 0 --L .1. 0 o o 1 1 0 1 2 3 4 P 1 0 0 1 1 '1Add 0 eve" parity for address bus bits 0-4 o 1 to m,'"t,'" T 1 0 0 1 1 1 I 7 T I XR Extend Address Bits XR Address Bus Bits 0 1 1 0 0 2 3 4 P 0 0 0 0 XRA value o o 0 1 0 X 1T XR page C XR address bus XR address Hex 10 (16 decimal) 0 1 234 p T XRA Register Extend Bits 0 1 3480 MI Address Bits 2 3 4 567 EC336395 Data Fields • CapyrightlBM Corp. 1984. 19B5 :J :J DF 3 o External.gisters o o o o Cross Reference Tables MNEM Note: Not all the registers are defined in this section. Only those registers that are useful for troubleshooling are defined. Buffer Control Card (01A-A1L2) Register MNEM Type Register Name XR Page BCPH RfW Buffer Channel Pointer High BCPL RIW Buffer Channel Pointer Low BOPH RIW BOPL RIW Register Type o o Qternal Registers"F 5 Register Name XR Page Addr Hex Addr Dee XRA Value CMM RIW Mode 0 16 22 ED CHM R/W Channel Mode 0 17 23 EE Drive Adapter Card (01A-A1Q2) Addr Hex Addr Dee 0 00 0 CO 0 01 1 C3 MNEM Type Register Name XR Page Addr Hex Addr Dec XRA Value Buffer Device Pointer High 0 02 02 C5 OLR R Device Level Register A 10 16 21 Buffer Device POinter Low 0 03 3 C6 OSH R Control Unit Serial High A 11 17 22 C9 OSL R Control Unit Serial Low A 12 18 24 R Device Interrupt Register B 10 16 61 XRA Value Register BCSH RIW Buffer Channel Stop High BCSL RIW . Buffer Channel Stop Low 0 05 5 CA OIR BOSH RIW Buffer Device Stop High 0 00 6 CC ITC RIW Interval Timer C 9 11 17 62 RfW Device Control Register B 12 18 64 B 13 19 67 0 04 4 BOSL RIW Buffer Device StOp Low 0 07 7 CF OCR BWRP RIW Buffer Wrap 0 08 8 01 OSE R Device Status/Error BCC RfW Buffer Channel Command 0 09 9 D2 OCB RIW Device Control Bus B 14 20 68 OTR RIW Device Tag Register B 15 21 6B OSC RIW Device Secondary Clock B 16 22 60 RfW Device Secondary Register B 17 23 6E BCSE RIW Buffer Channel StatuS/Error 0 OA 10 D4 BCR RIW Buffer Channel Remainder 0 OB 11 07 BCSS RIW Buffer Channel SARS 0 DC 12 D8 BCPC W Buffer Channel Pad Counter 0 00 13 DB BOC RIW Buffer Device Command 0 OE 14 DO BOSE RIW Buffer Device Status/Error 0 OF 15 DE BOR RfW Buffer Device Remainder 0 10 16 E1 BOSS RfW Buffer Device SARS 0 11 17 E2 Buffer Adapter Card (01A-A1K2) MNEM Register Type Register Name XR Page Adell" Hex Addr Dec XRA Value BOAT RIW Buffer Data (Pseudo Name) 0 12 18 E4 BOGO RfW Buffer Diagnostic 0 0 15 21 EB BOG1 RfW Buffer Diagnostic 1 0 16 22 ED BMR RfW Buffer Mode Register 0 17 23 EE - OSR Maintenance Adapter Card (01 A-A1 E2) MNEM Type Register Name XR Page Addr Hex Addr Dec XRA Value MTI RIW Maintenance Tag In C 10 16 A1 MTO RIW Maintenance Tag Out C 11 17 A2 Register MOl R Maintenance Data In C 12 18 A4 MOO RfW Maintenance Data Out MSB R Maintenance Status Byte . . . . C 13 19 A7 Note: • These registers are not directly addressable, but can be displayed by using the Support Diskette. Buffer Adapter Card (01A-A1K2) witll 4.5 Mbls Channel or Improved Data Recording Capability Replaces the above table when installed. Register MNEM Type Register Name XR Page Addr Hex Addr Dec XRA Value CMOT RfW DiagnostiC Data 0 12 18 E4 CMRS RfW Register Select 0 13 19 CMRP RfW Register Page 0 14 20 CMS R Status 0 15 21 3480 MI EC A57723 trl Copyright IBM . -- E7 E8 EB External Registers IBM Con ,fldentlal r",p 1982,1989 "3 ... . zz DF5 n. , n " (1 " o () () () o () o o o o o o o o External Registers External Registers Note: Not all the registers are defined in this section. Only those registers that are useful for troubleshooting are defined. Buffer Control Card (01 A-A 1L2) ! BCPH BCPl BDPH BDPl BCSH BCSl BOSH BOSl BWRP BCC BCSE I I BCR BCSS BCPC BDC BOSE BDR Register Type RiW R/W I R/W p..!W R/W R/W I R/W i I R/W i I I I R/W R/W R/W R/W R/W I W R/W I RiW I I I I BOSS I XR Page Register Name Buffe. Channel Pointer High Buffer ! Buffer Buffer I Buffer I I I Buffer Buffer Buffer Buffer Channel Pointer low Device Pointer High Device POinter low Channel Stop High Channel Stop low Device Stop High Device Stop low Wrap I Buffer Channel Command Buffer Channel Status/Error I Buffer Channel Remainder I i R/W i R/W I Buffer Buffer Buffer Buffer OF 5 Drive Adapter Card (01 A-A 1 Q2) Cross Reference Tables MNEM o o Channel SARS Channel Pad Counter Device Command Device Status/Error Buffer Device Remainder Buffer Device SARS I 0 0 I 0 0 0 0 0 I Addr Hex I I 00 I 01 I 02 I 03 I 04 L 05 I 06 07 08 I 09 I I OA I OB I I OC I 00 i OE i OF I 10 I 11 I J I i I 0 0 0 0 I 0 0 I 0 I 0 0 0 0 I i I XRA Value! CO i 02 3 4 5 6 7 8 I 9 I 10 11 I i ! Addr Dec 0 1 I C3 C5 II C6 C9 CA J CC CF 01 I I I i i I 07 I 12 13 14 08 DB DO I 15 DE E1 I I II E2 I 16 17 I I l Register Type R R R R R/W R/W R R/W R/W R/W R/W I I I I I ! Register Name Device level Register Control Unit Serial High Control Unit Serial low Device Interrupt Register Interval Timer C Device Control Register Device Status/Error Device Control Bus Device Tag Register Device Secondary Clock Device Secondary Register I I ! XR Page A A A B 8 B 8 B 8 B 8 I Addr Hex 10 11 12 10 11 12 13 14 15 16 17 Addr Dec 16 17 18 16 17 18 19 I I 20 21 I 22 I 23 XRA Value I 21 i 22 24 61 62 64 67 68 68 60 6E I I I 02 04 I MNEM DlR DSH I DSl DIR ITC OCR DSE DC8 OTR OSC OSR Maintenance Adapter Card (01 A-A1 E2) I I i i I I MNEM MTI MTO MOl MOO MSB Note: I I I i ! I Register Type R/W R/W R R/W R I Register Name I Maintenance Tag In I ! Maintenance Tag Out I I Maintenance Data In ! i I Maintenance Data Out I Maintenance Status Byte I : I l XR Page C C C C ~. I I! I Addr Hex I 10 I 11 I I I 12 I 13 Addr Dec I 16 I 17 ! 18 I 19 i I I I I I . . I I i XRA Value A1 A2 A4 A7 . ! I I i I • These registers are not directly addressable. but can be displayed by using the Support Diskette. Buffer Adapter Card (01 A-A1 K2) Register Type R/W R/W R!W R/W MNEM BOAT BOGO BDG1 BMR XR Page Register Name Buffer Data (Pseudo Name) Buffer Diagnostic 0 Buffer Diagnostic 1 Buffer Mode Register Addr Hex 12 0 0 I Addr Dec 18 21 15 0 0 16 17 22 ED 23 EE Addr Dec XRA Value I 4.5 Mbls Buffer Adapter Card (01A-A1K2) Replaces the above table when installed. MNEM CMOT Register Type I Register Name I XR Page I I R/W I R/W R I Status 0 CMM I I I ! R/W I Mode 0 CHM ! R/W I Channel Mode· 0 CMRS CMRP CMS I I R/W ! Addr I Hex I I Diagnostic Data 0 I 12 18 E4 Register Select 0 19 E7 Register Page 0 I I 13 14 i I 15 20 21 16 22 I 17 I I 23 E8 I I I ! E8 I ED I EE I External Registers 3480 MI EC A57721 ¥ OF5 External Registers (Continued) External Registers (Continued) OF 10 Cross-Reference Tables (Continued) Microprocessor Card (0 1A-A 1D2) Register TYDe W Reaister Name Interval Timer B R Error Reoister A ITA R R/W Error Reoister B Interval Timer A XRA R PER MNEM ITB ERA ERB Read Data Flow and Read Control Card (01A-A 1S2) XR Page AlB C Addr Hex 18 ess Dec XRA Value Register TYDe Reaister Name XR Paae Addr Hex 30/70 BO MNEM RCR RSR 18 4 4 R/W R Read Control Reaister Read Status Reoister B B 02 03 ess Dec XRA Value 2 45 3 4 46 49 0 18 4 FO RER R Read Error Reaister B 04 19 5 33/73 RRC R Read Residual Count B 05 5 4A External Reaister Address A/B C/O 19 5 B3/F3 RPR R Read Pattern Register B 06 6 4C R Processor Error Register A/B/C/O 1A 6 35/75/ B5/F5 ROC R/W Read Oiaanostic Control B 07 7 4F JAL W Jump Address Low A/B/C/O 1A 6 35/75/ B5/F5 PSR R Processor Status Register A/B/C/O 1B 7 A/B/C/O 1B 7 Reoister Name XR Paae Addr Hex ess Dec XRA Value 36/76/ B6~1F6 JAH W Jump Address High POR R/W Processor Diagnostic Register A/B/C/O 1C 8 39/79/ B9/F9 PCR R/W Processor Control Register A/B/C/O 10 9 3A/7A/ BA/FA IMR R/W Interrupt Mask Register A/B/C/O 1E 0 3C/7C/ BC/FC MNEM 3F/7F/ BF/FF CCA 3~~(6/ B6 F6 LSP R/W Local Storage Page A/B/C/O 1F 1 Status Store Card (01A-A 1G2) Register TYDe R/W Channel Card Control A 00 Channel Card Address A 01 0 1 00 CDR R/W R/W Channel Data Reoister A 02 2 05 CER CMR R W Channel Error Reoister Channel Modifier Register A 03 A 03 3 3 06 06 CRR R Channel Request Register A 07 7 OF CAE R Channel Adapter Error CAS R Channel Adapter Status CCC 03 These registers are not directly addressable, but can be displayed JIY using the Support Diskette. Write Data Flow Card (01A-A 1P2) 3480 MI MNEM WCR Register TYDe R/W Register Name XR Page Addr Hex ess Dec Write Control Reoister B 00 0 40 WSE R Write Status/Error B 01 1 43 EC336395 External Registers (Continued) • Copyright IBM Carp. 1984. 19B5 :1 '.r XRA Value "1, 1... OF 10 o Cross-Reference Tables (Continued) XRA Value to Register Name Cross-Reference Table XRA Value Register Name 00 Channel Card Control 03 Channel Card Address 05 Channel Data Register 06 (R) Channel Error Register 06 (W) Channel Modifier Register OF Channel Req~st Register 21 Device Level Register 22 Control Unit Serial High 24 Control Unit Serial Low 30 Interval Timer B 33 Interval Timer A 35 Processor Error Log 35 Jump Address Low 36 (R) Process.or Status Register 36 (W) Jump Address High 39 3A 3C Processor Diagnostic Register Processor Control Register Interrupt Mask Register 3F Local Storage Page 40 Write Control Register 43 Write Status/Error 45 Read Control Register 46 Read Status Register 49 Read Error Register 4A Read Residual Count 4C Read Pattern Register 4F Read Diagnostic Control 61 Device Interrupt Register 62 Interval Timer C 64 Device Control Regi ster 67 Device Status/Error 68 Device Control Bus 6B Device Tag Register 60 Device Secondary Clock 3480 MI EC A57723 "Copyri,hlIBM Corp. 1882.1889 0 o 0 XRA Value o o XRA Value Register Name External Reaers (Continued) .F 12 Register Name 6E Device Secondary Register DB Buffer Channel Pad Counter 70 Interval Timer B DO Buffer Device Command 73 Interval Timer A DE Buffer Device Status/Error 75 Processor Error Register E1 Buffer Device Remainder 75 Jump Address Low E2 Buffer Device SARS 76 (R) Processor Status Register FO Error Regi ster B 76 (W) Jump Address High F3 External Register Address 79 Processor Diagnostic Register F5 (R) Processor Error Register 7A Processor Control Register F5 (W) Jump Address Low 7C Interrupt Mask Register F6 (R) Processor Status Register 7F Local Storage Page F6 (W) Jump Address High A1 Maintenance Tag In FA Processor Control Register A2 Maintenance Tag Out FC Interrupt Mask Register A4 Maintenance Data In FF Local Storage Page A7 Maintenance Data Out BO Error Register A B3 External Register Address B5(R) Processor Error Register Buffer Adapter Registers XRA Value Register Name B5 (W) Jump Address Low B6 (R) Processor Status Register B6(W) Jump Address High BA Processor Control Register BC Interrupt Mask Register BF Local Storage Page CO Buffer Channel Pointer High C3 Buffer Channel Pointer Low C5 Buffer Device Pointer High C6 Buffer Device Pointer Low XRA Value C9 Buffer Channel Stop High E4 Diagnostic Data CA Buffer Channel Stop Low E7 Register Select CC Buffer Device Stop High E8 Register Page CF Buffer Device Stop Low EB Status 01 Buffer Wrap ED Mode 02 Buffer Channel Command EE Channel Mode 04 Buffer Channel Status/Error 07 Buffer Channel Remainder 08 Buffer Channel SARS IBM Con :ndentlal E4 Buffer Data Not Real EB Buffer Diagnostic 0 ED Buffer Diagnostic 1 EE Buffer Mode Register Buffer Adapter Registers with the 4.5 Mbls Channel or Improved Data Recording Capability Register Name -. Note: These registers replace the buffer adapter registers when the Improved Data Recording Capability 4.5 Mb/s buffer adapter card is installed. External Registers (Continued) DF12 o o f) () r) ~ () o f) , ' o o o o o o o o Externai Registers (Continued) External Registers (Continued) Cross-Reference Tables (Continued) XRA Value XRA Value to Register Name Cross-Reference Table XRA Value Channel Card Control 03 Channel Card Address C5 Channel Data Register 06 (R) i Channel Error Register 06 (W) Channel Modifier Register OF Channel Request Register Device Secondary Register DB Buffer Channel Pad Counter 70 Interva! Timer B DO Buffer Device Command 73 Interval Timer A DE Buffer Device Status/Error 75 Processor Err::Jr Register El 75 Jump Address Low E2 76 (Rl Processor Status Register FO 76 (W) Jump Address Hign F3 External Register Address 79 Processor Diagnostic Reg!ster F5 rR) Processor Error Register Pr()CeS5Cr Control Register F5 (IN) Jump Address Low 21 Device Level Register 7C In:errupt Mask Register F6 (Ri 22 Control Unit Serial High 7F Local Storage Page Fa (Wi Jump Address High 24 Control Unit Serial Low Al ~Iaintenance FA Processor Con:roi Register 30 Interval Timer B A2 Maintenal"ce Tag Out FC Interrupt Mask Register 33 Interval Timer A A4 Ma!ntenance Data In FF 35 Processo~ i 35 Jump Address Low i 36 (R) Processor Status Register 36 (W) A.7 ~'1a!ntenance 3F BO E~ror 53 Processor Control Register Write Control Register 43 Write Status/Error 45 Read Control Register 46 Read Status Register 49 Read Error Register 4A Read Residual Count 4C Read Pattern Register 4F Read Diagnostic Control 61 Device Interrupt Register 62 Interval Timer C 64 Device Control Register 67 Device Status/Error 68 Device Control Bus 6B Device Tag Register Device Secondary Clock 3480 MI EC A57721 " Copyr'gnt IBM CQrp. 1982. 1988 Buffer Device Remainder i Buffer Device SARS Error Register B I Processor Status Register I I Local Storage Page Buffer Adapter Registers Register .A. i External Register Adcress XRA Value B5 (R) Processor Error Register BS(IN) Jump Address Low B6 (RJ Pr::Jcessor Status P,egister B6 ('11/) Jump Address High BA Processor COl"trol Register BC Interrupt BF Local Storage Page CO Buffer Channel Pointer High C3 Buffer Channei Pointer Low CS Buffer Device Pointer High XRA Value C6 Buffer Device Pointer Low E4 Interrupt Mask Register Local Storage Page DF12 Data Out Processor Diagnostic Register , 40 60 I Tag In Jump Address High 39 3C Error Log i o Register Name 6E 7A 3A XRA Value Register Name Register Name 00 o Mas~ Register Name E4 Buffer Data Not Real EB Buffer Diagnostic 0 ED i Buiter Diagnostic 1 EE i Buffer Mode Register Register 4.5 Mbls Buffer Adapter Registers Register Name Diagnostic Data i C9 Buffer Channel Stop High E7 CA Buffer Channel Stop Low E8 Register Page CC Buffer Device Stop High EB Status CF Buffer Device Stop Low ED Mode 01 Buffer Wrap EE Channel Mode 02 Buffer Channel Command 04 Buffer Channel Status/Error 07 Buffer Channel Remainder 08 BufferChannelSARS Note: i i Register Select These registers replace the buffer adapter registers when the 4.5 Mb/s buffer adapter card is installed. I II --1 External Registers (Continued) DF12 External Register Bit Definitions BCPH Register • • Type = Read/Write Card = 01A-A lL2 XRA Value = CO The Buffer Channel Pointer High (BCPH) register provides the high order half of the address used for channel storage cycles. It is incremented at the end of each channel storage cycle, except the last channel storage cycle, at the completion of Store CRC and Loop Write to Read operations. It is initialized before starting a Buffer Channel Side operation. The BCPH register is reset by Power-On-Reset (PaR). External Register Bit Definitions BCSE Register Type = Read/Write Card = 01 A-A 1K2 XRA Value = D4 • The Buffer Channel Status and Error (BCSE) register is used to indicate channel status and error conditions. Note: All cards referenced by this table are on the 01A gate. To display the BCSE register, see "Register Display/Alter" on SDISK 1. Bits Bits Bits Bits Bits BCPl Register • • • Type = Read/Write Card = 01A-A lL2 XRA Value = C3 The Buffer Channel Pointer Low (BCPL) register provides the low order half of the address used for channel storage cycles. It is incremented at the end of each channel storage cycle, except the last channel storage cycle, at the completion of Store CRC and Loop Write to Read operation. It is initialized before starting a Buffer Channel Side operation. The BCPL register is reset by paR. OF 15 Bit 0-3 4-7 4-7 4-7 4-7 have the (BCSEO) (BCSE 1) (BCSE2) (BCSE3) same meaning for all four channel groups. Channel Error Group 0 = Channel Error Group 1 = Channel Error Group 2 = Channel Error Group 3 = Description I Detail label 0 Channel Pointer Equals Stop A status condition set during a channel store cycle when buffer control detects that the last byte in the buffer has transferred for this channel data transfer operation. 1 Channel Stop A status condition set after a Channel Stop condition is received from the buffer adapter card during channel read or write operations. Set after a Device Read End condition is received from the read data flow during a Loop to Read operation. 2 Microprocessor Write Complete A status condition set after the data in the channel RAM containing the two CRC bytes has been stored. 3 Sample Channel Errors (This is a status condition.) When set, enables the Channel Error Group pointer so that following each read of the BCSE register, the contents of the BCSE register are updated to the next error group. The first read of the BCSE register shows the errors for Error Group 0, the second read for Error Group 1, the third read for Error Group 2, and the fourth read for Error Group 3. The operation then is repeated. 4-7 Channel Errors Bits 4 through 7 represent errors in each of the four error groups and change meaning for each group. Bits 4-7 of the BCSE register comes from Bits 0-3 of the CEGO, CEG' CEG2, and CEG3 register respectively. Error groups are identified by the Channel Error Group Pointer. Channel Error Group 0 (CEGO): Bit 4 = Any channel error Bit 5 = Channel overrun Bit 6 = Channel Adapter to Buffer Adapter Parity Error Bit 7 = Buffer Control to Channel Adapter Parity Error Channel Error Group 1 (CEG1): Bit 4 = Buffer Control - FRU 114 (A 1L2). FRU 120 (A 1K2) Bit 5 = Buffer Adapter - FRU 120 (A 1K2). FRU 114 (A 1L2) Bit 6 = Buffer Memory - FRU112 (A1M2); FRU 113 (A 1N2) Bit 7 = Host/Channel Adapter Channel Error Group 2 (CEG2): Bit 4 = Channel Buffer Memory Address Parity Error Bit 5 = Buffer Memory Address Pointer Parity Error Bit 6 = Channel Buffer Memory Data Correctable Error Bit 7 = Channel Buffer Memory Data Uncorrectable Error Channel Error Group 3 (CEG3): Bit 4 = Buffer Adapter to Buffer Control Channel Data Bus Parity Error Bit 5 = Buffer Control Channel RAM Data Parity Error Bit 6 = Channel CRC Error Bit 7 = Not used 3480 MI External Register Bit Definitions EC336395 OF 15 '" Copynght IBM Corp. 1984. 1985. 1986 ~) t-- "1 :) ;) ~) , ,I ~ o o o o o o o External Register Bit Definitions (Continued) BOSE Register • • • • • • The Buffer Channel SARS (BCSS) register provides the addressing for the intermediate channel storage, for any data transfers between the channel storage and the buffer channel side interfaces (host processor). It is incremented each time a byte of data is read from, or written into the channel storage via one of the buffer channel side interfaces. The BCSS register is reset with a hardware or channel control reset. o External Register Bit Definitions (Continued) BCSS Register Type = Read/Write Card = 01 A-A 1L2 XRA Value = 08 o o OF 20 Type " Read/Write Card - 01A-A1K2 XRA Value = DE The Buffer Device Status and Error (BOSE) register shows drive status and error conditions. Note: All cards referenced by this table are on the 01A gate. To display the BOSE register, see "Register Display/Alter" on SDISK 1. Bits Bits Bits Bits Bits Bit 0-3 4-7 4-7 4-7 4-7 have the same meaning for all four device groups. (BDSEO) = Device Error Group 0 (BOSE 1) = Device Error Group 1 (BDSE2) = Device Error Group 2 (BDSE3) = Device Error Group 3 Description I Detail Label '0 0 Device Pointer Equals Stop 1 Device 2 Device Data Transfer Complete A status condition set after the CRC bytes have been processed through the Device CRC Checker during a write operation. Is also set after the data in the device RAM, containing the two CRC bytes, has been stored during a Read and Store CRC operation. 3 Sample Device Errors J (This is a status condition.) When set, enables the Device Error Group pointer, so that following each read of the BOSE register, the contents of the BOSE register are updated to the next error group. The first read of the BOSE register shows the errors for Error Group 0, the second read for Error Group 1, the third read for Error Group 2, and the third read for Error Group 3. The operatipn then is repeated. Device Errors Bits 4 through 7 represent errors in each of the four error groups and change meaning for each group. Bits 4-7 of the BOSE register comes from Bits 0-3 of the CEGO, CEG 1, CEG2, and CEG3 register respectively. Error groups are identified by the Device Error Group Pointer. 4-7 Re~d End A status condition set during a device store cycle when buffer control detects that the last data byte has been transferred for this device data transfer. A status condition set after a Device Read End is received from the Read Data Flow. ' Device Error Group 0 (DEGO): Bit 4 = Any device error Bit 5 = Device Data OJerrun Bit 6 = Read Data Flow to Buffer Adapter Parity Error Bit 7 = Buffer Control to Buffer Adapter Device Data Bus Parity Error Device Error Group 1 (DEG1): Bit 4 = Buffer Control - FRU 114 (A 1L21. 0.... Bit 5 = Buffer Adapter - FRU 120 (A 1K2~. vBit 6 = Buffer Memory - FRU 112 (A 1M21i ~ Bit 7 = Read Data Flow Device Error Group 2 (DEG2): Bit 4 = Device Buffer Memory Address Parity Error Bit 5 = Device Buffer Memory Address Pointer Parity Error Bit 6 = Device Buffer Memory Data Correctable Error Bit 7 = Device Buffer Memory Data Uncorr.ectable Error Device Error Group 3 (DEG3): Bit 4 = Buffer Adapter to Buffer C,ontrol Data Bus,Par!ty Error Bit 5 = Buffer Control Device RAM Data Parity Errqr Bit 6 = Device CRC Error' Bit 7 = Not used 3480 MI EC336395 co Copyngh.IBM Corp, 1984, 1985, 1986 External Register Bit Definitions (Continued) OF 20 External Register Bit Definitions (Continued) External Register Bit Definitions (Continued) BDGO Register BOG 1 Register • • • • • • Type = Read/Write Card = 01A-A1K2 XRA Value = EB Label 0 Shift Gate Select 0 1 Shift Gate Select 1 Shift Gate Select 2 2 Type = Read/Write Card = 01A-A1K2 XRA Value = ED The Buffer Diagnostic 1 (BOG 1 I register is used with diagnostic mode. Buffer Diagnostic 0 (BDGOI register is used for diagnostic purposes. Bit Oe.criDtion I Detail Used to select one of eight scan paths on the BC card when the Shift Gate Enable bit equals a one, or one of two paths on the BA card when the Shift Gate Enable bit equal zero. See Bit O. Bit Label Oe.criDtion I Detail 0 Scan Out Data (Read OnlY) Used to sample the Scan Out Data from the BC card. 0 Scan In Data (Write Only) Used for diagnostic scans of the BC card. 1 Service In (Read Only) Samples the Service In tag. A value of one indicates that the Service In tag is active. 1 Scan Clock A (Write Only) When set to a one, permits 'LSSD scan A clock' line to scan data for the BC card. 2 Data In (Read Only) When set to a one, indicates that the Data In tag is active. 2 Scan Clock B (Write Only) When set to a zero, permits 'LSSD scan B clock' line to scan data for the BC card. See Bit O. 3 Shift Gate Enable Used to start a scan operation on the BC card when the bit is set to a one. 4 Enable Correctable Error Status When set to a one, enables the correctable error status to be put into the BCSE register. 5 6 Read End When set to a one issues a Read End Tao in diaonostic mode. Device Side Diaanostic When set to a one, causes a drive operation in diagnostic mode. 3 Write End (Read Only) When set to a one, indicates that the Write Data Flow End tag is active. 7 Channel Side Diagnostic When set to a one, causes a channel operation in diagnostic mode. 3 Disable ECC (Write Only) When set to a one, disables buffer storage error correction. 4 5 6 7 Service Out When set to a one causes a Service Out taa in diaanostic mode to be sent. Data Out When set to a one, causes a Data Out tag in diagnostic mode to be sent. Stop Out When set to a one, causes a Stop Out tag in diagnostic mode to be sent. Suppress Out When set to a one, causes a Suppress Out tag in diagnostic mode to be sent. 3480 MI • Capvright IBM o External Register Bit Definitions (Continued) EC336395 carp. 1914. 19BII {) o OF 25 o t) () OF 25 o o o o o o External Register Bit Definitions (Continued) BDPH Register The Buffer Device Pointer High (BDPH) register provides the high order half of the address used for drive channel storage cycles. It is incremented at the end of each drive storage cycle, except the last drive storage cycle, at the completion of a Read Data Flow operation. It is initialized before startin\l a Buffer Device Side operation. The BDPH register is reset by Power-on-Reset (POR). Label DescriPtion / Detail 0 Select Channel Adapter A Specifies which of the channel adapters is to be selected. 1 Select Channel Adapter B See Bit O. 2 Select Channel Adapter C See Bit O. 3 Select Channel Adapter D See Bit O. 4 Device Address 8 Specifies which device address is to be used or a displacement into apage of RAM. 5 6 7 Device Address 4 See Bit 4 Device Address 2 See Bit 4. Device Address 1 See Bit 4. 3480 MI EC336395 o External Register Bit Definitions (Continued) • • c '0 Copyngh. IBM Corp. 1984, 1985 o o OF 30 BDPL Register Type- Read/Write Card 01A-A lL2 XRA Value " C5 Bit o Type = Read/Write Card = 01A-A lL2 XRA Value = C6 The Buffer Device Pointer Low (BDPL) register provides the low order half of the address used for drive channel storage cycles. It is incremented at the end of each drive storage cycle, except the last drive storage cycle, at the completion of a Read Data Flow operation. It is initialized before starting a Buffer Device Side operation. The BCPL register is reset by a Power-on-Reset. BWRP Register • • • Type = Read/Write Card = 01A-A lL2 XRA Value = Dl Bits 0-3 of the Buffer Wrap (BWRP) register control the setting of fixed 16, 32, 64, or 128K byte storage segments for Buffer ~hannel Side operations. Bits 4-7 control the setting of fixed 16, 32, 64, or 128K byte storage segments for Buffer Device Side operations. This register is reset by a Power-On-Reset. Bit Label Description / Detail 0 Channel 128 K-byte Segment Buffer Channel Side Operation 1 Channel 64 K-byte Segment Buffer Channel Side Operation 2 Channel 32 K-byte Segment Buffer Channel Side Operation 3 Channel 16 K-byte SeQment Buffer Channel Side Operation 4 Device 128 K-byte Segment Buffer Device Side Operation 5 Device 64 K-byte Segment Buffer Device Side Operation 6 Device 32 K-bvte Segment Buffer Device Side Operation 7 Device 16 K-byte Segment Buffer Device Side Operation External Register Bit Definitions (Continued) OF 30 External Register Bit Definitions (Continued) External Register Bit Definitions (Continued) OF 33 External Register Bit Definitions (Continued) OF 33 CAE Register The Channel Adapter Error (CAE) register is not a channel external register in the sense that it cannot be read directly. To get the data from the adapter error register you must transfer the data to an external register that can be read directly. For the procedures. do the following steps (see "Register DisplayI Alter" on SDISK 1). To read the CAE: 1. Set the channel card control (CCC) register to hexadecimal: 85 45 25 15 for for for for channel channel channel channel adapter adapter adapter adapter A B C 0 2. Set the channel card address (CCA) register to hexadecimal 03 to write the CAE into the channel adapter RAM. 3. Set the channel card address register to hexadecimal C3 to write the CAE into the channel data register (CDR). 4. Read the channel data register to get the contents of the CAE. Bit 0 1 2 3 4 5 6 7 Definition Multi-tag error Channel adapter RAM write parity error Channel adapter RAM read parity error Buffer-data-in parity error Channel adapter to status store data parity error Channel adapter to status store response parity error Status store to channel adapter data parity error Status store to channel adapter response parity error Note: There is one CAE register in each channel adapter. When an error occurs on channel adapter A. bit 4 of the CER register is set. Channel adapter B errors sets bit 5. and so on (see "CER Register" on OF 35). 3480 MI EC336395 • Cclpyr9ltl8M Corp. 1984. 1985 ') t o o o o o o Externai Register Bit Definitions (Continued; CER Register The Channel Adapter Status (CAS) is a read only register. It is displayed by channel orders using the MD support diskette (see "Channel RAM Display" on SDISK 1). The CAS register is located on the channel adapter card for the channel adapter that is selected. • • • label 0 CA Offline Notes: DescriPtion / Detail Bit 0 is active when the Power-On-Reset (POR) signal to the respective channel adapter shoe card is active. It means that the shoe card drivers are not on. 1. Any active channel error register bit sets a Check 2 error. 2. All cards referenced by this table are on the 01A gate. Bit DescriPtion / Detail label Status Store Basic Card Parity Error Basic register parity check (internally checked). Status store basic (SSB) card - FRU 121 (A1G2) 1 Offline Switch Bit 1 is active when the Enable/Disable switch for the respective channel adapter on the ooerators oanel is in the disabled oosition. 2-4 Channel Mode Switches The Channel Mode Switch bits are set to the value of the three high order bits of the low order hex digit of the address switches (bits 4-6) on the operators panel. The bits are used by the microcode to control the operation mode of control unit buffer during data transfer mode. 1 Status Store Communication Card Parity Error Status store communication parity check (data from status store communication register to status store communication card checked)' Status store communication (SCC) card FRU122 (A1F2) 2 5 Address Switch Parity Bad Bit 5 is active when even parity is detected on the control unit address switches (high order hex digit and low order bit of the low order hex digit (bits 0-3, 7). SSC Card to SSB Card Transfer Error Remote control unit control transfer error (status store communication card to status store basic card). 3 6 Collision Detected Bit 6 is set if both control units in a two control unit subsystem have activated the collision detection hardware circuits. When Collision Detected is on, the 'adapters failure' to status store. This causes the failing channel adapter's bit to be set in the Channel Error Register (CER). Check 2 error and a level 6 interruot then become active. XR Data Bus Pari tv Error XR data parity error. XR data from the microprocessor card had bad parity. Microorocessor - FRU 117 (A 102) 4 Channel Adapter A Detected Error Register parity check transfer error. Data from the channel adapter register to the status store card (A 1G2) had bad parity. Channel Adapter A - FRU 133 (A2C2) 5 Channel Adapter B Detected Error Register parity check transfer error. Data from the channel adapter register to the status store card (A 1G2) had bad parity. Channel Adaoter B - FRU 152 (A2D2) 6 Channel Adapter C Detected Error Register parity check transfer error. Data from the channel adapter register to the status store card (A1G2) had bad Darity. Channel Adaoter C - FRU195 (A2E2) 7 Channel Adapter 0 Detected Error Register parity check transfer error. Data from the channel adapter register to the status store card (A 1G2) had bad parity. Channel Adapter 0 - FRU 196 (A2F2) Reserved CCA Register • • • OF 35 Type = Read Card = 01A-A 1G2 XRA Value = 06 0 7 o The Channel Error Register (CER) contains pointers to errors detected by the status store or channel adapter areas. The Channel Adapter Status (CAS) register has the following bit definitions. Bit o External Register Bit Definitions (Continued) CAS. Register 01 A-A2C2 for channel adapter A 01A-A2D2 for channel adapter B 01A-A2E2 for channel adapter C 01A-A2F2 for channel adapter 0 o o Type = Read/Write Card = 01A-A 1G2 XRA Value = 03 Note: After the failing channel has been identified by the CER register bits 4-7. see "CAE Register" on OF 33 for more details. The Channel Card Address Register (CCA) is used to present orders to the status store or channel adapter areas. CCC Register • • • Type = Read/Write Card = 01A-A 1G2 XRA Value = 00 The Channel Card Control (CCC) register is used by the microcode to control the selection of the channel adapters and specify the address that is to be used. It is also used with the CCA register. Bit 0 selects channel adapter A Bit 1 selects channel adapter B Bit 2 selects channel adapter C Bit 3 selects channel adapter 0 ' Bit'S 4-7 specify the channel adapter RAM page. 3480 MI e Copyright IBM Corp. EC336395 1984. 19B5 External Register Bit Definitions (Continued) OF 35 External Register Bit Definitions (Continued) External Register Bit Definitions (Continued) CMM Register CHM Register • Type = Read/Write • Card = 01A-A1K2 • XRA Value = EE The CHM register is used to set the channel r.node. Only microcode can change the contents of this XR through an XR write operation. This register is reset by a hardware reset. Type = Read/Write Card = 01A-A1K2 XRA Value = ED • • • The CMM register is used to set the operation mode for the 4.5 Mb/s Buffer 'Adapter Card. I Bit Label Bytes in Flight 0 Bytes in Flight Description/Deta i I Channel Timer 0 Channel Timer 1 3 See Bit 3 These two bits determine the maximum amount of time the buffer adapter waits for an out tag before setting a channel overrun error. If the timer is disabled, a channel overrun error cannot be set. Channel Time Timer 0-1 Selected Disabled 16 us 64 us I, 256 us ThiS bit determines the group of channel adapters (local or remote) through which a channel data transier takes place. Bit On = Remote 6it Off = Local 4 Channel Group ~ Channel Mode 1 See bit 7 Cl1annei Mode 2 Channei Mode 3 See bit 7 These three bits determine the channel data transfer rate and mode. Channel Mode 0-2 000 001 010 011 100 101 110 111 Channel Mode 1.5 Mbls Interlock (Service in first) 1.5 Mb/S Interlock (Data in firs!; 1.5 Mbis Streaming 2.0 Mb/s Streaming 3.0 Mb/s Streaming Reserved 4.5 Mbis Streaming Reserved CMDT Register • • • 2 5 Force 300 ns Clock Ring Error 6 Force Toggle Feature Parity Error Pseudo Buffer End 7 The CMDT register is used for diagnostic data transfers between the microprocessor and the buffer adapter. or buffer contro!ler. The CMDT is reset to X' 00' by a channel control reset. i Description/Detail Can be written or read for diagnostic purposes 1 ! Can be written or read for diagnostic purposes Bits 2 and 3 set the diagnostic mode 00 = No Diagnostics 01 = Reserved 10 = Buffer Channel Diagnostics 11 = Buffer Device Diagnostics This bit is set for the Maintain Separation command, When this bit is set it causes the 300 ns clock ring to go out of synchronization causing the 300 ns clock ring error to be set. When this bit is set the feature switch parity is defined as even and forces a feature switch parity error, When this bit is off the feature switch parity is defined as odd. This bit is set after receiving a buffer control interrupt at the end of a data transfer. CMRP Register • • • Type = Read/Write Card = 01A-A1K2 XRA Value = E8 The CMRP register is the microcode interface for reading and writing the 4.5 Mbis channel adapter internal registers, These registers are addressable by the page and register number in the CMRS register, The CMRP register holds the data of the register addressed t:y the CM RS register, 4.5 Mbls Buffer Adapter Register Pages # Regs CMRS Bits Page 0 1 2 3 4 5 6 7 Type = Read/Write Card = 01 A-A 1K2 XRA Value = E4 Label Reserved Reserved Diagnostic Mode a Diagnostic Mode 1 , Maintain Separation 4 -. 7 1 15 31 63 127 00 01 10 6 i a See Bit 1 These two bits determine the maximum number of outstanding in tag requests that are permitted. Bits 0-1 In Tag Bits Count 00 01 10 11 2 3 OF 36 # 1-3 i 000 001 010 011 Per Page 0 Type NA a NA 4 100 101 a 2 R NA NA R:W 110 111 a a NA NA 0 Description Reserved Reserved C2PO Error and Feature Level Registers Reserved Reserved Buffer Adapter Diagnostic Registers Reserved Reserved - , I The at:ove figure lists the buffer adapter register pages with their respective page addresses (CMRS XR bits 1-3). The desired register address within the page must be specified by writing CMRS XR, bits 4-7. External Register Bit Definitions (Continued) 3480 MI EC A57721 {) o r) OF 36 o o o o Externaegister Bit DefiAns (Continued) CHM Register CMM Register • Type - ReadIWrite • Card - 01 A-A 1K2 (with 4.5 Mb/s Channel or Improved Data Recording Capability features) • XRA Value - EE The CHM register is used to set the channel mode. Only microcode can change the contents of this XR through an XR write operation. This register is reset by a hardware reset. • Type - ReadIWrite • Card - 01A-A1K2 (with the 4.5 Mb/s Channel or Improved Data Recording Capability features) • XRA Value - ED The CMM register is used to set the operation mode for the Buffer Adapter Card. Bit 0 1 2 3 Label Bytes in Flight 0 Bytes in Flight Channel Timer 0 Channel Timer 1 4 Channel Group 5 6 7 Channel Mode 1 Channel Mode 2 Channel Mode 3 00 15 01 31 10 63 11 127 See Bit3 These two bits determine the maximum amount of time the buffer adapter waits for an Out tag before seHing a channel overrun error. If the timer is disabled, a channel overrun error cannot be set. Channel Time Timer 0-1 Selected 2 3 Diagnostic Mode 0 Diagnostic Mode 1 4 Maintain separation Force 300 ns Oock Ring Error S 7 When set to 1, this bit specifies that the RAM selected for the Comp Ram Diagnostic Is to be written. When set to 0, the selected RAM Is read. Bits 2 and 3 set the diagnostic mode 00 - No Diagnostics 01 = Buffer RAM Dia~ostic 10 = Buffer Channel 'agnostlcs 11 - Buffer Device Diagnostics This bit Is set for the Maintain Separation command. When this bit Is set it causes the 300 ns clock ring to go out of synchronization causing the 300 ns clock ring error to be set. When this bit Is set the feature SWitch parity is defined as even and forces a feature switch parity error. When this bit IS'off the feature switch parity Is defined as odd. This bit Is set after receiving a buffer control interrupt at the end of a data transfer. • Type - ReadIWrite • Card - 01A-A1K2 (with 4.5 Mb/s Channel or Improved Data Recording Capability features) • XRA Value - E8 The CMRP register is the microcode interface for reading and writing the channel adapter internal registers. These registers are addressable by the page and register number in the CMRS register. The CMRP register holds the data of the register addressed by the CMRS register. Buffer Adapter Register Pages Channel Mode t:5Mb/s Interlock (Service in first) 1.5 Mb/s Interlock (Data in first) 1.5 Mb/s Streaming 2.0 Mb/s Streaming 3.0 Mb/s Streaming -3.7 Mb/s Streaming 4.5 Mbls Streaming Reserved Page # 0 -_. Type - ReadIWrite Card - 01 A-A 1K2 (with the Improved Data Recording Capability feature) XRA Value - E4 The CMDT register is used for diagnostic data transfers between the microprocessor and the buffer adapter, or buffer controller. The CMDT is reset to X '00' by a channel control reset. 3480 MI EC A57723 Des<=MplonlDetaii This bit turns on Improved Data Recording Capability Format. CMRP Register CMDT Register rJ Copyright IBM Corp_ 1982.1989 Force Toggle Feature Parity Error Pseudo Buffer End 6 00 Disabled 01 16 us 10 64 us 11 256 us This bit determines theJroup of channel adapters (local or remote) through which a chann data transfer takes place. Bit On - Remote Bit Off - Local See bit 7 See bit 7 These three bits determine the channel data transfer rate and mode. 000 001 010 011 100 101 110 111 1 Improved Data Recording Capability Ram Write/Read 0 See Bit 1 These two bits determine the maximum number of outstanding in t~g requests that are permiHed. Bits 0-1 In Tag Bits Count Channel Mode 0-2 • • • Label Bit Description/Detail eF 36 1 2 3 4 5 6 7 CMRS Bits 1-3 000 001 010 011 100 101 110 111 # Regs Per Page 16 0 3 8 0 2 4 4 Type R NA R NA NA RIW NA NA Description Comp 0 through Comp 3 Channel Byte Count Registers Reserved C3PO Error and Feature Level Registers Comp 0 through Comp 3 Error Registers Reserved Buffer Adapter Diagnostic Registers Comp 0 through Comp 3 Diagnostic Registers Comp 0 through Comp 3 Configuration Registers The ~bove fiQure lists the buffer ad~J'l'e .. register pages with their respective page addresses (CMRS XR bits 1-3). The desired register ;tddress within the page must be specifipd by writing CMRS XR, bits 4-7. IBM Con lfidential External Register Bit Definitions (Continued) OF 36 o o o () o () () o o o External.gisters (Contin.d) o o CMRS Register • • • The CMRS register is the microcode interface for selecting and accessing registers on the 4.5 Mb/s or Improved Data Recording Capability buffer adapter card. These registers are organized into eight pages, and each page can contain up to 16 registers. Deserl ptloniDetaii Label o External Reg.rs (Continued) • • • time. Bit Label Deseri ption/Detail Set when the Comps are busy initializing their respective Encoders and Decoders. Also set when Improved Data Recording Capability is on during a channel read or write. See bit 3. 1 Channel End Set when the end data is detected during a channel read or a channel write. CMRP page address 2 These bits select the CMRP register page to be accessed by either an XR read or write to the CMRP XR. There is a total of 8 CMRP register pages with a varying number of registers in each. 2 Buffer Control End Set when the buffer transfers the last byte of data to the buffer control. 4 CMRP register address 0 See bit 7. 3 Xfer Complete/Overrun Set when stop out or end indications and out tags corresponding to all generated in tags have been received. 5 CMRP register address 1 See bit 7. 4 6 CMRP register address 2 See bit 7. ChannelOp Complete Set when a channel operation is complete. Not set for a zero byte transfer. 7 CMRP register address 3 These bits select the CMRP register to be accessed within a selected CMRP register page. 5 4.5 Mb/s or Improved Data Recording Capability installed This bit is set to 1 when the 4.5 Mb/s channel or Improved Data Recording Capability adapter card is installed. 6 Improved Data Recording Capability allowed Improved Data Recording Capability is allowed when this bit is set to 1. In a dual control unit subsystem both control units must have the Improved Data Recording Capability feature installed before Improved Data Recording Capability can be allowed. 7 Any Error Set by any of the error bits on CMRP register page 2. Setting this bit causes the CMRP register address to increment after each XR read of the CMRP XR. 1 CMRP page address 0 See bit 3. 2 CMRP page address 1 3 CopyrigtrtlBM Corp. 1982.1989 37 The CMS register is used to post status information and is synchronized to the MP interface so that it may be read by microcode at any Comp Busy Auto increment CMRP regi ster address 3480 MI EC A57723 • Type'" Read Card - 01 a-A1 K2 (with 4.5 Mb/s Channel or Improved Data Recording Capability features) XRA Value - EB 0 0 ... It') o CMS Register Type - ReadlWrite Card - 01A-A1K2 (with 4.5 Mb/s Channel or Improved Data Recording Capability features) XRA Value - E7 Bit o o IBM Cor.1fidential External Registers (Continued) DF37 o () {} () f) i) () o o o o o o o o o External Registers (Continued) External Registers (Continued) Type = Read/Write • • Card = 01A-A1K2 XRA Value = E7 The CMRS register is the microcode interface for selecting and accessing registers on the 4.5 Mb/s buffer adapter card. These registers are organized into eight pages, and each page can contain up to 16 registers. Bit 3 4 Label Setting this bit causes the CMRP register address to increment after each XR read of the CMRP XR. CMRP page address 0 See bit 3. CMRP page address 1 See bit 3. CMRP page address 2 These bits select the CMRP register page to be accessed by either an XR read or write to the CMRP XR. There is a total of 8 CMRP register pages with a varying number of registers in each. • XRA Value 0 1 I 2 See bit 7. 6 CMRP register address 2 See bit 7. 7 CMRP register address 3 These bits select the CMRP register to be accessed within a selected CMRP register page. ! = 01A-A1K2 = EB Always read as '0'. Channel End Set when the end data is detected during a channel read or a channel write. Buffer Control End Set when the buffer transfers the last byte of data to the buffer control. I 4 I, ChannelOp II I I I, Xfer Complete/Overrun Complete 4.5 Mb/s installed I Set when the buffer has received stop out or end indications and has received out tags to correspond with all generated tags. I I! I I I 6 I 6 I I I I I Set when a channel operation is complete. Not set for a zero byte transfer. This bit is set when the 4.5 Mb/s channel adapter card is installed. This bit is controlled by sWitch pOSftion 3 on the 4.5 Mb/s buffer adapter card and should be set to '0'. Reserved I 7 i Reserved I I 5 I I I II I Desc ription/ Deta iI Label I, I I 1 3 See bit 7. CMRP register address 1 3480 MI EC A57721 Type Card Bit r------r----------------------~--------------------------------------------------------__j 5 = Read • • The CMS register is used to post status information and is synchronized to the MP interface so that it may be read by microcode at any time. Description/Detail Auto increment CMRP register address CMRP register address 0 OF 37 CMS Register CMRS Register • o o Reserved i Any Error I Set by any of the error bits on CMRP register page 2. External Registers (Continued) OF 37 External Register Bit Definitions (Continued) External Register Bit Definitions (Continued) CRR Register OCR Register • • • • • • Type = Read Card = 01A-A lG2 XRA Value = OF The Channel Request Register (CRR) is used by status store to present status information about the channel adapter, status store, or message handling between the control units in a dual control unit subsystem. Type = Read/Write Card = 01A-A 1Q2 XRA Value = 64 The Device Control Register (OCR) is used by the microcode to select and control the correct device lines. Bit Bit DescriDtion / Detail Label 0 1 2 3 When set to a zero, bit 0 gates the lines between the drive-adapter card and the drive (see Note), drivers and receivers. When set to a one, the (see Note) lines are gated to the drivers and receivers. The oCB and oTR registers are controlled by this bit. This bit is used also with bits 2 and 4. 1 Interrupt/ Secondary Select Hi/Lo When set to a zero, permits the microcode to sense interrupts that are present (see Note). When set to a one, the interrupts (see Note) are sensed. The olR register is controlled by this bit. See Bit 3. See Bit 3. These bits indicate that their respective channel adapter has met one of the following conditions: . . The adapter is at the end of initial selection and status has been accepted by the channel. When used as a secondary, and this bit is set to a zero, the serial data and clock are sent from the oSR and OSC register to the drives on the (see Note) interface. When set to a one, it is sent selected control unit (see Note). The oSR and OSC registers are controlled bv this bit. 2 Enable Bus The adapter has received a Halt I/O, Selective Reset, or System Reset from the channel. Indicates that the other control unit has acknowledged receipt of a message. This bit is reset when the microcode sends a Write Messaoe Buffer order. When set to a one, permits the oCB register or write data flow, access to the device control bus. When set to a zero, the bus drivers are unconditionally disabled. The control unit that is enabled is controlled bv OCR reaister bit O. 3 ITO Enable When set to a one, permits the OSC register, linked with the oSR register, to be used as an internal timer. It also degates the serial command and clock lines to the devices. When set to zero the OSC and oSR reoisters ooerate as a serial interconnection. 4 Enable Write When set to a one, with bit 2 also set to a one, permits the data from the write data flow, access to the drive control bus. When set to a zero, the write data flow does not have access to the drive control bus. OCR register bit 0 controls the control unit that is enabled. 5 S ITC Time Out When ITC eouals zero. This bit will reset when a non- zero is set into the ITC. ITO/Serial Command Complete Set when the ITO or oSC contents equal zero. This occurs a the time of the timeout or after the secondary command has been sent to the drive. The bit resets when a non-zero value is set into the ITO register or a new secondary command is loaded into the oSR reQister. Reset Repos Sets the 'repositioning in latch'. 4 Acknowledge 5 Received Indicates that this control unit has received a message from the other control unit. This bit is reset when the microcode sends a Write Messaoe Buffer order. S SS Order Ack Indicates that the status store or the channel adapter has processed the order in the CCA reaister (AO 1l- It is reset when reoister AO 1 is written into. 7 SS Response Indicates that the status store or channel adapter has successfully processed the order that is in CCA reaister AO 1. This bit is valid onlv if bit S of this reoister is on. Type = Read/Write Card = 01A-A lQ2 XRA Value = 68 7 Note: The Device Control Bus (DCB) register is used to transfer information from the control unit microcode to the drive through 'bus out' using the Device Data Bus (DDB). It is also used to transfer information to the control unit microcode from the drive through 'bus in' using the DDB. 3480 MI • Copyright IBM ~) corp. Descriotion / Detail Select Hi/Lo DCB Register • • • Label 0 See Bit 3. Channel Adapter A Reouest Channel Adapter B Reauest Channel Adapter C Reauest Channel Adapter o Request OF 40 Single Control Unit Subsystem Local = Control Unit 0 - Addr 0-7 EC336395 Local = Control Unit 0 - Addr 0-7 Remote = Control Unit 0 - Addr 8-F Local = Control Unit 1- Addr 8-F Remote = Control Unit 1- Addr 0-7 External Register Bit Definitions (Continued) 1984. 1985 {) Dual Control Unit Subsystem ~) OF 40 o o o o o o o o o o o o e o o 0 000 o 0 (Continued) External Register Bit Definitions (Continued) DIR Register • • • The Device Interrupt Register (DIR) is used to present interrupts from any drive to the microcode. An interrupting device causes its corresponding bit and the P bit to be set in the DIR register. The hardware sets an error if only the P bit is on. Description 0 Interrupt from drive 0 1 Interrupt from drive 1 2 Interrupt from drive 2 3 Interrupt from drive 3 4 Interrupt from drive 4 5 Interrupt from drive 5 6 Interrupt from drive 6 7 Interrupt from drive 7 DLR Register • • • o o OF 45 DSE Register Type - Read Card - 01A-Al02 XRA Value - 61 Bit e o o _oe Type - Read Card - 01A-Al02 XRA Value - 21 The Device Level Register (DLR) contains miscellaneous information. • • • Type - Read Card - 01A-Al02 XRA Value - 67 The Device Status/Error (DSE) register shows device status and error conditions. Note: All cards rererenced by this table are on the 01A gate. Bit Label Description/Detail 0 Drive Adapter-Card Parity Error Bit 0 indicates that bad parity was detected by the drive adapter-card (Al02) on the device data bus (DDB). It is also used to permit interrupts from the drives to be signalled ir the drive bus parity bit is on and no other drives bus lines are on. 1 Write Data Parity Error card Bit 1 indicates that bad parity was detected on the MUX data path when the data was gated from the write data flow to the drive control bus. FRU116 (A1 P2) 2 Drive Adapter-Card Parity Error Bit 2 indicates that the device adapter-card had bad internal parity or there was an interrupt error. fRU11S (A 102) 3 Reserved 4 Repositioning Repositioning is used as a response to any serial sequence command that causes tape motion. It indicates that the drive is either repositioning or it is not at the command stoplock position. 5 Repositioning Same as bit 4. 6 Reserved 7 Reserved ., See the CARR section for the switch position assignments for the Drive Adapter Card (FRUl18). 3480 MI EC A57124 C Copyri,ht IBM Corp ,18Z, ,no External Register Bit Definitions (Continued) OF 45 External Register Bit Definitions (Continued) DTR Register ERA Register and ERAH (Holding) • • • ERA XR only Type = Read/Write Card = 01A-A1Q2 XRA Value = 6B • • • The Device Tag Register (DTR) is used by the microcode to transfer control tags to and from the drive. Label 0 Select Out Select Out is used to start the Initial Sequence to the drive and requires no response from the drive. Select Out must stay active during the complete connected part of the operation. 1 Address Out Address Out is used to signal all the drives to decode the address that is on the bus. When the drive recognizes its address, its responds by placing its complement address on the bus and raisingAddress In. 2 Command Out Command Out is a response to Address In during Initial sequence and indicates to the selected drive that the command on the bus is valid. Command Out stays active until Status In is received. 3 Clock A Out Clock A Out is used during data transfer sequences and it is the odd parity of the nine data bits being transferred. During sense or control transfer sequences, Clock Out A is used as a response to Clock B In/Out. Clock A Out indicates to the selected drive that the control unit has accepted or provided the information on the bus that was requested bv the drive generated Clock B In/Out line. 4 Gap In/Out Type = Read Card = 01A-A 1 D2 XRA Value = BO The ERAH is not a XR register, but it can be displayed using "CU Scan Rings - Error" (see SDISK DescriPtion / Detail Bit 1). Error register A (ERA) and error register B (ERB) are used to indicate check 1 error conditions. Normally, the processor is stopped before it reads the error registers, However, they can be read out using the support diskette Alter/Display program "CU Scan Rings" (see SDISK 1). The registers are also used to verify that the check 1 error detection circuits are working correctly. ERAH is the holding register for the ERA register. If the check 1 error recovers on the retry operation, the ERAH or ERBH registers indicates the cause of the recovered check 1 error. If any bit is on in the ERA or ERB register, it means that the check 1 condition is a solid error and the ERA or ERB register(s) have meanings that are useful for troubleshooting. Notes: Gap In and Gap Out share a common bi-directionalline. The microcode raises 'Gap Out' by writing in to the DTR register. The DTR register monitors the Gap In/Out line and raises Gap In for read operations. 1. The ERA register does not include Check 1 errors that are caused by Forced Microcode Check 1 (PCR register, bit 5) errors. 2. All cards referenced by this table are on the 01A gate. 3. MD displays can indicate ERA and ERB as a single hex character field named 'ERAB'. 4, MD displays can indicate ERAH and ERBH as a single hex character field named 'HOLD'. 5 Address In Address In is used as a response to Address Out to indicate to the control unit that the address of the selected drive is valid. Address In is also used to indicate any error or unusual condition that is detected durina a data transfer seauence. 6 Status In Status In is used to indicate that the status information on the bus is valid. Status In is the response to Command Out during a Initial Sequence or a control unit ending seauence. 0 CS Data Parity Funnel Error 7 Clock Bin Clock B In/Out is a bi-directional line between the control unit and all attached drives. Its function is the same as Clock A Out. 1 Reg Source Funnel Error This bit is set when the register source indicates an invalid source (valid sources are CS, LSR, JUMP, and XR registers). The error is inhibited until Initial Diagnostic Complete (PCR register bit 4) so that the microcode can initialize local storage. This is an internal error of the microprocessor card. 2 Microprocessor, Internal Data, or Clock Error This bit is set when an error is detected by one of the three check latches in the microprocessor . Bit 3 4 3480 MI OF 50 External Register Bit Definitions (Continued) EC336395 Label Current Interrupt Parity Error Processor Interrupt Level Parity Error DescriPtion / Detail This bit is set when bad pa,ity is detected in the micro- processor card (A 102) on a word fetched from the control storage data bus or when the control storage source reaister indicates an invalid source. 1. Control Storage Data Parity Error - Data transferred from the CS Data Bus to the Microprocessor or Data Bus. 2. Local Storage or External Register Data Parity Error - Data transferred from LS or XR Bus In to Microprocessor Data Bus In. 3. Registers internal to the microprocessor card have bad parity (even) or an invalid clock state (system clocks) was detected. This bit indicates that bad parity was detected in the 'current interrupt level' latches in the microprocessor card. This bit indicates that bad parity was detected on the 'processor interrupt level' bus during an interrupt swap, in the microprocessor card. 5 LSR Address Parity Error This bit indicates that bad parity was detected on the 'LSR selects and address' bus in the microprocessor card. 6 XR Address Parity Error This bit indicates that bad parity was detected on the 'XR select and processor XR address' bus in the microprocessor card. 7 Processor Bus Out Parity Error This bit indicates that bad parity was detected on 'processor bus out' during a register write operation. The error was detected in the microorocessor card. OF 50 External Register Bit Definitions (Continued) • Capyright IBM Corp. 1984, 1985 :) !) , • J o o o o o o o External Register Bit Definitions (Continued) Externai Register Bit Definitions (Continued) ERB Register and ERBH (Holding) MOl Register ERB XR only • • • • • • o o Type; Read Card;01A-A1D2 XRA Value; FO o OF 55 Type; Read Card; 01A-A1E2 XRA Value; A4 The Maintenance Data In (MOl) register has two functions: The ERBH is not a XR register, but it can be displayed using "CU Scan Rings - Error" (see SDISK 1). Error register B (ERB) and error register A (ERA) are used to indicate check 1 error conditions. Normally, the processor is stopped before it reads the error registers. However, they can be read out using the support diskette Alter/Display program "CU Scan Rings" (see SDISK 1). The registers are also used to verify that the check 1 error detection circuits are working correctly. ERBH is the holding register for the ERB register. If the check 1 error recovers on the retry operation, the ERBH or ERAH registers indicates the cause of the recovered check 1 error. If any bit is on in the ERB or ERA register, it means that the check 1 condition is a solid error and the ERB or ERA register(s) have meanings that are useful for troubleshooting. 1. When Maintenance Tag Out (MTO) register bit 2 (Read XR Active) and Maintenance Tag In (MTI) register bit 4 (XR Address Error) both equal 1, this register defines the logic card that contains the external register at the time of an external register error. 2. When MTO bit 2 or MTI bit 4 does not equal 1, this register contains commands or data transferred between the functional microcode and the maintenance device; however, this data does not provide valid pointers to external register logic cards. Diagnostic routines only display the MOl register when the register can define the logic card that contains the external register that was addressed at the time of the external register error. Use the following procedure to read the contents of the MOl register. Notes: 1. 1. The ERA register does not include Check 1 errors that are caused by Forced Microcode Check 1 (PCR register, bit 5) errors. 2. All cards referenced by this table are on the 01 A gate. 3. MD displays can indicate ERA and ERB as a single hex character field named ·ERAS'. Display the MTI register to verify that bit 4 equals 1. If Bit 4 does not equal 1, no further troubleshooting information can be read, even if the bit is turned on. Display the MTO register to verify that bit 2 equals 1. If bit 2 does not equal 1, write hexadecimal 20 into the register to turn on bit 2. Display the contents of the MOl register to determine the logic card that contains the external register that was addressed at the time of the external register error. 4. MD displays can indicate ERAH and ERBH as a single hex character field named 'HOLD'. To display the MOl register, see "Register Display/Alter" on SDISK 1. 2. 3. Bit 0 4 Label XR Address Compare Error MP Register Error Uncorrectable CS Read Error CS Address Parity Error CS Refresh Error 5 Selection Check 6 Key Bit Check 7 CS Write Data Parity Error 1 2 3 Descriotion / Detail Set when the Processor XR Address bus bits 0-4 do not match the XR Address bus bits 0-4 (internal in the microorocessor card). Bad parity is detected in the IMR or PDR registers (internal in the microprocessor card). The control storage error correction hardware detected an uncorrectable data word on a control storaoe fetch ooeration (error was detected bv the CS card). This bit indicates that bad parity was detected on the control storage address bus (error was detected by the CS card). This bit indicates that one of the three refresh error is in error (error was detected by the CS card). This bit indicates that Multiple Card Selects was active (error was detected by the CS card!. The Key Bit Check bit indicates an error was detected from the control storage address bus parity bit (error was detected by the CS card). This bit indicates that the data being written had bad parity (error was detected by the CS card). MCR Register Note: Bit 0 All cards referenced by this table are on the 01 A gate. Label Buffer Adapter 1 Status Store 2 Device Adapter 3 Read Data Flow 4 Microprocessor 5 Write Data Flow 6 Maintenance AdaPter Reserved 7 Descriotion / Detail One of the following external registers was addressed during an external register error: BCPH. BCPL. BDPH, BDPL.BCSH, BCSL. BDSH,BDSL, BWRP. BCC. BCSE. BCR. BCSS. BCPC. BDC. BDSE. BDR. BDSS. BDAT. BDGO. BDG1. BMR, or BDAT. FRU 114 (A lL2) FRU120 (A1K2) One of the following external registers was addressed during an external register error: CCC CCA, CDR. CER, CMR, or CCR. FRU121 (A1G2) One of the following external registers was addressed during an external register error: DSH DSL, DIR. DLR. ITC. DCR. DSE. DCB, DTR. DSC, or DSR. FRU 118 (A lQ2) One of the following external registers was addressed during an external register error: RCR RSR.RER. RRC, RPR,or RDC. FRU 119 (A 1S2) One of the following external registers was addressed during an external register error: ITB, ERA. ERB. ITA. XRA. PER. JAL. PSR. JAH. PDR. PCR. IMR. or LSP. FRUl17 (A1D2) One of the following external registers was addressed during an external register error: WSE or WCR. FRU 116 (A 1P2) One of the following external registers was addressed during an external register error: MTI. MTO MDI or MDO. FRU115 (A1E2) The Maintenance Control Register (MCR) is not a readable register. The following description is for information only. The four bits of the MCR register are set by individual MO commands. All bits are reset with a Reset MCR command. The MCR is controlled by the "Microprocessor Control Utility," see SDISK 1. Bit 0 1 2 3 4 5 3480 MI DescriPtion lonore Errors Address Compare StoP Check Stop Check 2 ; Check 1 Address Compare Sync Prooram Flao External Register Bit Definitions (Continued) EC336395 ~ Copyright IBM Corp. 19B4. 19B5 "d g OF 55 External Register Bit Definitions (Continued) MOO Register External Register Bit Definitions (Continued) OF 60 MTI Register = • Type = ReadiWrite • Type • 8ard = 01A-A1E2 XRA Value = A7 • Card = 01A-A1E2 Read/Write XRA Value = A1 The Maintenance Data Out (MDO) register is L;sed to transfer information between the microcode and the maintenance device. The Maintenance Tag In (MTI) register controls the operation of the maintenance adapter (MA) and provides status and error conditions for the adapter and the subsystem. MSB Register To display the MTI register, see" Register Displayl Alter" on SDISK 1, Note: = Read = 01A-A1E2 • • Type Card • To display the MSB register, see 'Microprocessor Control" on SDISK 1. Bit o o Label A status condition that indicates to the microprocessor that another byte of information is ready to be taken by the microprocessor, or that another byte of information can be received by the maintenance adapter. This bit also acknowledges microprocessor Status Out. Data Transfer or M D Connection Busy Bit 1 indicates a status condition that is active during all data transfers to and from the microprocessor or indicates that the MD byte transfer is in process. 2 Maintenance Device Enabled A statL;s condition that indicates that the maintenance device is on-line and enabled, 3 XR Address Bus Parity Error Spare This bit will always be off. 2 Extended Op in Progress This bit indicates that the microprocessor is exec"':!ing an Extenced Op instruction (an ir,struction that requires more tr,an one control storage fetch, 3 Address Compare Equa: This bit indioates a match betweer, the compare a::idress set by the Maintenance Device microcode and the co;,trol storage adcress that is referenced by the microprocessor. 4 Check i Hardware Error Tt"1,is bit indicates a hard error in the microprocessor or otrer hardware circuits cf this control unit. 5 MP Stopped This bit is on if the microprocessor is stopped, TI-]e microDrocessor may be stopped with a StoP MP commarrd from the Maintenance Device. a Check 1 error condition, or t,y processor control, 6 Instruction Executed ThiS bit indicates to tt",e microprocessor microcode that the rr,ic:'otJrocessor read an ir.structicn from the control storage ~or executi8n during the last microprocessor CYCle. ThiS bit is :.;sed during a Force MP Instruction sequ~nce to confirm the execGtion of the instruction before resetting force m9de, Error - MTI Status Stored Description/Detail Desc ription/Dt!ta i I Status MOdifier 7 Label Mainter"1ance ,A,dapter Request/Response The Maintenance Status Byte (MS6) register contains the Maintenance Adapter and Microprocessor status. Bit Ail cards referenced by this table are on the 01A gate. 4 ! j XR Adaressed , Line Error 5 MA Internal Card Error 6 M D Parity Error Either none or more than one XR addressed lines are active during an XR read or write cycle, Exterr,al Register cards - FRUl17 (A1D2!: FRUl15 (A1E2): FRU121 (A1G2): FRU120 (A1K2i: FRU114 (A1L2): FP,Ui16 (AiP2): FRU118 (A1Q2): FP,U119 (,A,1S2) I I 7 ChecK 1 The maintenance acapter card iA1E2) has detected bad parity on tne XR address bL;s from the microprocessor card, FRU117 (,~ 1D2) The maintenance adapter card (A1E2) detected an error internal to the card. This can be caused ty the MA card, bad clock lines to the MA card from the control store (CS) card (A1C2), or voltages to either card, FRU115 (A1E2): FFW134 (A1C2) The maintena.'"lce adapter card detected bad parity on serial data in !ir,e from the mair,tenance device. FRU = Maintenance Device Indicates that a Check 1 occurred that has not been reset by a cheok or hardware reset. This bit indicates that error cata is stored in the MTI register. 3480 MI EC A57721 External Register Bit Definitions (Continued) ~) :1 f ) " .f~ ,} OF 60 f l , I o o o o o External Register Bit Definitions (Continued) o o o o o External Register Bit Definitions (Continued) OF 62 External Register Bit Definitions (Continued) OF 62 MTO Register • • • Type = Read/Write Card = 01A-A 1E2 XRA Value = A2 The Maintenance Tag Out (MTO) register is used by the microcode to control the operation of the maintenance adapter and report status and other information about the subsystem. To display the MTO register, see "Register Display/Alter" on SDISK 1. Bit 0 1 label DescriDtion / Detail Not Used Wait Light This bit is used by the microcode to indicate the amount of subsystem activity. Wait light blinks - Normal subsystem activity Wait light on continuous - No drive activity Wait light never on - subsystem in a loop or wait light circuitry oroblem (this is not a normal condition) 2 RD X/R Active This bit aates the XR active latch to the MP. 3 Data Ready This bit indicates that the data in the MOO register is ready to be transferred to the MD. For information onlv. Disolaying the MTO reaister will change the values of bits 3-6. 4 MD Status Out This bit indicates that the microcode needs the attention of the MD. For information only. DisDlayinQ the MTO register will chanQe the values of bits 3-6. 5 Data Demand This bit indicates that the microcode wants to send data to or receive data from the MA. For information onlv. Disolavina the MTO reaister will chanae the values of bits 3-6. 6 Command/Data Received This bit indicates to the MA that the MP has successfully received the command or data byte. For information only. Displaying the MTO register will change the values of bits 3-6. 7 Reserved 3480 MI EC336395 III Copyr91t IBM Corp. 1984. 1985 External Register Bit Definitions (Continued) External Register Bit Definitions (Continued) PCR Register PER Register • • • • • • Type = Read/Write Card = 01A-A 102 XRA Value = BA The microcode uses the Processor Control Register (PCR) to cause events or conditions to occur within the subsystem. Bit 0 Description / Detail Label Force Interrupt Forces an interrupt at levels 0 through 6, whichever is enabled. This directs the microcode to handle interrupts with more priority if they are not masked off. Interrupt priorities, high to low: Level Level Level Level Level Level Reset 0 - Microprocessor of subsystem maintenance adapter 1 - Microprocessor (Timer) 2 and 3 - Read control 4 and 5 - Buffer control 6 - Status store 7 - All others by the hardware automatically and will always read as a zero. 1 Return From Interrupt Causes a PSW swap from the current level to the highest remaining level that has an interrupt pending. Reset by the hardware automatically and will always read as a zero. 2 Diagnostic Mode When set, activates the 'diagnostic mode' line. Enables data with incorrect parity to be written to an external register. Prevents the MA from alerting the channel interface to disconnect during a check 1 condition. When set, activates the hardware reset line. Causes all functional areas except the micro processor to initialize to a power-on condition. It is also forced active while power-on reset is active. Remains set for at least ten processor cycles. 3 Hardware Reset 4 Initial Diagnostic Complete Forced Microcode Check 1 This bit is set by the microcode after the initial power-on diagnostics have successfully completed. Remains set until next power on sequence. Enables Reg Funnel Parity checker after all LSR locations have been initialized to good parity. 6 XR Address Extend 0 See Bit 7. 7 XR Address Extend 1 These two bits extend the XR addressing to 128 Read/Write registers. See 'External Register Addressing' on OF 3. 5 Activates the 'check l' line when the microcode detects a non-recoverable error condition. Type = Read Card = 01A-A 102 XRA Value = F5 The Processor Error Register (PER) contains status and error condition indicators. Note: Bit EC336395 All cards referenced by this table are on the 01 A gate. 0 Label MP Check 2 1 ITA/B = 0 Active if the ITA/ITB counter equals zero. When active, a level 1 (timer) interrupt is aenerated. Timer ITA/B is used by the microcode to time the different operations. 2 Collision Detect Bit 2 on, indicates a problem in the dual control unit communication area. When one control unit attempts to communicate with the other control unit and does not receive a response, the control unit expecting the response causes bit 2 of the PER register in the control unit that did not respond to be set on. A microcode forced check 1 error is caused in the control unit that has PER reoister bit 2 on. DescriPtion / Detail Set when a parity error is detected in the ITA/ITB timer registers (card A 102). Reset by a check reset to the microprocessor if the error no longer exists. 3 On-line Indicates the state of the online switch (one eauals online). 4 XR Read Parity Error Set if a read parity error is detected by the microprocessor card (A 102) during an XR read operation. Reset by a Check Reset to the MA/MP. When active, causes XR Error and Check 2 to be set. 5 XR User Read Error XR User Write Error Set if the 'XR error un gated' line is active during an XR read operation. Reset by Check Reset to the MA/MP. Set if the 'XR error ungated' line is active during an XR write operation. Reset by Check Reset to the MA/MP. Indicates the state of the Test/Normal switch. (1) for normal mode; (0) for test mode. See PANEL 1 for "Control Unit Switches and Indicators" for the function of the switch. 6 7 Normal Mode PRR Register The Processor Reset Register (PRR) is used to send a check reset to any or all functional areas. Each functional area is assigned a particular bit in the register. When the register is written, the check reset line is activated and, if bit 3 is not active, all functional areas whose bit is active performs a check reset. This register is a virtual register (no hardware) and does not store what was written. It is always reset after the write is complete. Bit 3480 MI OF 65 Label 0 Drive-adapter 1 Maintenance adaPter/processor 2 Status store/channel adapter 3 Must be a zero for check reset 4 Buffer (drive side) 5 Buffer (channel side) 6 Write data flow 7 Read data flow DescriDtion / Detail External Register Bit Definitions (Continued) • Co!I¥right IBM Corp. 1984. 1985 ( " . OF 65 . , \ j o o o o o o o PROCESSOR STATUS REGISTER ROC Register • • • • • • The Processor Status Register (PSR) contains status indlcalors pertinent to error conditions. Descrlptlon/Delall BII Label 0 XR Error This bit continuously samples the condition of the 'XR error latched' line and is set whenever any of the tnree XR Error bits (PER register bits 4, 5 or 6) are set. Once set. the bit remains set until a check reset Is issued to the MA/MP functional area. 4 Check 2 This bit continuously samples the status of the 'Check 2 error' line. When a Check 2 condition exists, this bit. will be active, See "External Registers Data Flow/Error Detection" in the OPER section for more Information. READ CONTROL REGISTER • Type = Read/Write • • Card = 01A-A1S2 XRA Value = 45 The Read Control Register (RCR) is used by the microcode to control the operation of the read data flow and condition it to do the needed read fu.nction. BII Label Read Gate This bit is used by the read detection circuits to gate the VFC from the write clock onto the read data. It becomes active when Gap In is sensed and reset at the end of the device operation, 1 Read LWR This bit conditions the read detection circuits to perform a Loop-Write-to-Read LWR operation. It is used on a short LWR operation. 2 Read Condition This bit is used to activate the read data flow. It becomes active at the time the read data flow should start detecting beginning sync and is reset at the end of the operation. 3 Inhibit External Pointers This bit, when active, inhibits the ECC from processing any pOinters other than ECC pointers. 4 Read/Write This bit specifies the type of operation; one equals read and zero equals write. Bit 4 is set before the rise of read gate and must not change until the end of the operation, S Fwd/Bkwd This bit is active lor the same duration for read or write operations. ltis on for a forward direction and off for a backward direction, 6 Gap Out Enable This bit permits 'Gap Out' to be set under the control of the Command Complete microprocessor, 'Gap Out' is set with a fixed delay after 'End Sync' Is sensed, or after BOB (without sensing the ending sync), ERG. or TM when IBG is sensed, 7 Density Enable EC336396 " Cooy"go, ItlM Corp 1984 1985 1986 1987 o OF 70 Type = Read/Write Card = 01A-A1S2 XRA Value :; 4F The Read Diagnostic Control (ROC) register controls the diagnostic status and functions of the read logiC. BII Label Descrlpllon/Detail 0 (See Note) Select Tone This bit, when a one, permits the microprocessor to read the tone zones in the Read Pattern Register (RPR). Zones A through F will appear In bit positions 0 through 5 respectively. 1 (See Note) Select Amp Sense This bit, when a one, permits the microprocessor to read the amp sense zones in the Read Pattern Register (RPR). Zones A through F will appear In bit positions 0 through 5 respectively, 2 Disable ECC This bit, when a one, disables the error correction from being performed. This permits the data record to be read into the buffer uncorrected, 3 Check Character Read This bit, when a one, causes all the characters read from the tape (including tha four ECC check characters) to be sent to the buffer during data frames. 4 Disable Dead Track Threshold This bit, when a one, disables dead-tracking that Is due to persistent pointers. S Enable BOB Processing This bit is set by the microcode when the read head is still In the IBG to enable the hardware part of BOB processing. 6 Inhibit Dropping Pointers This bit, when a one, will not let the ECC drop the pointers, 7 ECC Diagnostic This bit, when a one, passes ECC diagnostic information instead of data. Description/Detail 0 3480 o Exteinal Register Bit Cefinitions (Continued) Extemal Registei Bit Definitions (Continued) Type = Read Card = 01A-A1D2 XRA Value = 36, 76, B6, and F6 o Note: When the state of bits 0 or 1 changes, the RPR must be reset before liS new value can be used. This bit permits the display of the density pattern being read, See bits 0-3 of the "RPR" on OF 80. External Register Bit Definitions (Continued) DF 70 External Register Bit Definitions (Continued) External Register Bit Definitions (Continued) OF 75 READ ERROR REGISTER Type = Read Card = OIA-AIS2 XRA Value = 49 • • • The microcode uses the Read Error Register (RERI to get the FRU Information detected by the read data flow. All cards referenced by this table are on the OIA gate. Bit Bit 0 Label Description/Detail FRUO 2. 3. Skew Buller Hardware Error (card A2K2) - The error Is determined by the demodulator module on the ECC card (A I R2). RER bit 5 is also activated. The 'gate read cycle' lines from this card (A2K2) are not equal to the 'gate read cycle' lines from the other two Skew Buller Hardware Error cards (A2L2 and A2M2). RER bit 7 is also activated. The 'ROC equals zero' lines from this card (A2K2) are not equal to the 'ROC equals zero' lines from the other two Skew Buller Hardware Error cards (A2L2 and A2M2). AER bit 7 is also activated. Descrlptlon/Delall 3 Acceleration Check This can be a normal condition. For some write conditions, the drive can have limited instantaneous speed variations (ISV), and when the speed is more than the limits, write errors can occur. The ISV can cause changes in the write data density. Based on a pre-determined limit of 15 V, the acceleration check is turned on and the microcode repeats the write before a write error occurs. If this bit is on and write errors are occurring, troubleshoot the write errors. If this bit frequentiy occurs without any other write error conditions, it can be an indication of wear of the tape media, mechanical tape path parts or the read/write head. 4 CRC Hardware Failure This bit indicates that the CRC checker on the ECC card has failed and activates a Check 2 condition. FRU111 (A 1A2); FAU119 (A 152) 5 FRU5 This bit indicates that one of the following conditions has occurred: Skew Buller Zones A and B: This bit indicales that one of the following conditions has occurred: 1. Label FRUs for condition I: FRUl23 (A2K2); FRUIll (AlR2); FRUn9 (AI 52) FRUs for conditions 2 and 3: FRU123 (A2K2); FRU119 (A1S2) 1 FRUI 1. 2. 3. 4. 5. Skew Buller Zones C and 0: This bit indicates that one of the following conditions has occurred: 1. 2. 3. Skew Buller Hardware Error (card A2L2) - The error is determined by the demodulator module on the ECC card (A lR2). RER bit 5 is also activated. The 'gate read cycle' lines Irom this card (A2L2) are not equal to the 'gate read cycle' lines from the other two Skew Buller Hardware Error cards (A2K2 and A2M2). RER bit 7 is also activated. The 'ROC equals zero' lines from this card (A2L2) are not equal to the 'ROC equals zero' lines from the other two Skew Buller Hardware Error cards (A2K2 and A2M2). REA bit 7 is also activated. Skew Buller Hardware Errors I, 2 and 3 as determined by the demodulator module on the ECC card (A I A2). ARP registers parity error during a sample period. Correction registers parity error during a sample period. Decode parity error during a sample period. Incorrect parity on the corrected data bus during the residual byte. Possible FRUs. Condition I: FRUl23 (A2K2); FRU124 (A2L2); FRU125 (A2M2) Conditions 2-5: FRU111 (AI R2); FRU119 (A 152) 6 FRU6 This bit indicates that one 01 the following conditions has occurred: 1. 2. FRUs for condition I: FRUI24 (A2L2); FRUlll (A1R2); FRU119 (AIS2) FRUs for conditions 2 and 3: FRU124 (A2L2); FRU119 (A1S2) The data buller did not respond correctly following the 'read data ready' signal. The read clock and format did not respond correctly following the 'read data ready'signal. This bit also sets RER bit 7. Possible FRUs. FRUl20 (A1K2); FRU119 (A1S2) 7 2 FRU2 FRU7 This bit indicates that one of the following conditions has occurred: Skew Bufler Zones E and F: This bit indicates that one of the following conditions has occurred: 1. 2. 3. 1. Skew Buller Hardware Error (card A2M2) - The error is determined by the demodulator module on the ECC card (AlR2). AEA bit 5 is also activated. The 'gate read cycle' lines from this card (A2M2) are not equal to the 'gate read cycle' lines from the other two Skew Buller Hardware Error cards (A2K2 and A2L2). RER bit 7 is also activated. The 'ROC equals zero' hnes from this card (A2M2) are not equal to the 'ROC equals zero' lines from the other two Skew Buller Hardware Error cards (A2K2 and A2M2). AEA bit 7 is also activated. 2. 3. 4. 5. 6. FAUs for condition 1: FRU125 (A2M2); FAUll1 (A1A2); FAU119 (AI 52) FAUs for conditions 2 and 3: FRUl25 (A2M2); FAU119 (A1S2) Skew Buller Hardware Errors I, 2 and 3 as determined by the 'gate read cycle' and 'ROC equals zero' Signals. Also sets the respective skew buller hardware error bits (RER bits 0, 1 and 2). The clock module on Al S2 is not cycling correclly. The module 18 and module 8 counters are not in sequence. (Write/Read data flow counters are used to control data transfer.) The read clock and FMT card detected bad parity on the corrected data bus during the residual byte. RER bit 3 will be set if this error occurs. The data buller did not respond correctly following the 'read data ready' signal. This condition also sets RERbit 6. The read clock and FMT did not respond correctly following the 'read data ready' signal. This condition also sets RER bit 6. Possible FRUs. Condition 1: FRUs are indicated by bits 0-2. FRUl23 (A2K2); FRU124 (A2L2); FRU125 (A2M2) Conditions 2 and 3: FRUI19 (A1S2) Condition 4: FRU111 (A1R2); FRUl19 (A1S2) Conditions 5 and 6: FRU120 (A1K2); FRU119 (A1S2) 3480 EC336396 <: CopyroQ"' ,HM Corp , .... 19115 External Register Bit Definitions (Continued) '98e. Iilll ~) OF 75 o c o o o o Ci External Register Bit Definitions (Continued) RPR Register Description / Detail label IBG/IDla External Register Bit Definitions (Continued) o OF 80 Type = Read Card = 01A-A 1 S2 XRA Value = 4A The Read Pattern Register (RPR) is a selectable register for patteil1, tones, or amp sense. It is selected by the Read Diagnostic Control (ROC) register. In Normal mode, it is used by the micrvcode to determine the type of information being detected by the read logic. See the ROC register for more information. 0 o RRC Register Type ~ Read Card .c 01A-A 152 XRA Value .c 4C Bit o The meaning of bits 0, 1, 2, and 3 depends on the setting of the Density Enable bit (RCR register bit 71. When Density Enable IS not on, these bits indicate when an IBG, TM, ERG, or SPR pattern is being sensed. A TM indication will cause an interrupt level 2. This interrupt level is active when the RPR register bit 1 IS set and RCR register bit 7 is not set. The Read Residual Count (RRC) register stores the residual byte count that is read from the tape. The count is equal to the number of pad bytes that were written and are in a number range of 0 to 13. The microprocessor uses the count to determine the location and number of pad bytes in the buffer so that the count is not sent to the channel. Bit 0 label Bits 0 and 1 form the encoded modulo 4 count of the block 10. See Bit O. 1 Block lOB 2 Reserved 3 Reserved 4-7 DescriPtion / Detail Block IDA Contains the encoded residual byte count read from the drive. When Density Enable is on and a density pattern is being detected, bits 0, 1,2, and 3 are an indication of the actual density belOQ read. 1 TM/SIDl See Bit O. 2 ERG/SID2 See Bit O. 3 SPR/SID3 See Bit O. 4 BOB This bit indicates that a data block is being sensed by the read logic. It will be active when one or less zones are active and a no data condition does not eXists. This bit causes a interrupt level 2. This level will be active when the RPR register bit 4 is present. 5 VOID This bit indicates that a no data condition is beinQ sensed. 6 NOA This bit indicates that none of the other defined patterns exist. 7 Reserved Note: See "RCR Register" bit 7 and "ROC Register" bits 0 and 1 for more details. 3480 MI '.tl Copynyhl IBM Corp EC336395 1984. 19A5 External Register Bit Definitions (Continued) OF 80 External Register Bit Definitions (Continued) • • • Type = Read/Write Card = 01A-A 1S2 XRA Value = 46 The Read Status Register (RSR) contains the status of the read or write operation as it progresses. It also contains the status of the error correction attempts. Bit Label DF 82 WCR Register RSR Register • • External Register Bit Definitions (Continued) Descriotion / Detail 0 Beginning Sync This bit indicates that the beginning sync pattern was recognized by the read data flow card. When this bit is active interrupt level 3 is sionaled. 1 Ending Sync This bit indicates that the ending sync pattern was recognized by the read data card. When this bit is active. interruot level 3 is sionaled. 2 Gap Out Timing This bit is active when the IBG and TM or ERG or BOB are active in the Read Pattern Register (RPR). If bit 6 of the Read Control Register (RCR) is also active. interrupt level 3 is signaled. which causes 'gap out' to be sent to the drive. The drive must receive 'oao out' within a soecified time in order to control the oao size. Type = Read/Write Card = 01A-A 1P2 XRA Value = 40 The Write Control Register (WCR) controls the operation of the write data flow and conditions the appropriate write function. Bit label 0 Block IDA Bits 0 and 1 form the modulo 4 count of the 2 bit 10. They are set to the starting 10 (before Gap In) for the first record. On following write operations. the microcode must set the 10 somewhere in the IBG before the record which they are to be used. They should not chanoe aoain until the next IBG. Descriotion / Detail 1 Block lOB See Bit O. 2 LWR This bit conditions the write looic to execute a Looo-Write- to-Read operation. 3 DIAG This bit conditions the modulation encoder to handle the diagnostic data supplied to the write data flow functional area. 4 Reserved 3 Gap In This bit is set when 'gap in' is sent by the drive during tape repositioning. It indicates that the end of the last record read or written was sensed at the read/write head. 5 Write Data Flow Op Enable When this bit equals a one. bits 6 and 7 have the meaning indicated. 4 Data Corrected This bit is set when ECC corrections to the record just read are made. Bits 5-7 of this register indicate whether the corrections were successful. 6 Write Mode A Bits 5. 6. and 7 cause the Write Data Flow to write the following command information: 5 Data Check This bit indicates that the ECC could not correct this data block and it must be repositioned for a retrv. A check 2 interruot is sionaled when this occurs. 6 Multitrack Indicator This bit indicates that more ECC pointers were detected then the operating threshold oermits. A check 2 interruot is sionaled when this occurs durino write ooerations. 7 CRC Check This bit indicates that a data check was detected. A check 2 interrupt is signaled when this occurs. BIT 5 6 7 1 1 1 1 0 0 1 1 0 1 0 1 COMMAND Wr i te Data Wr i te TM Wr i te ERG Wr i te Density These bits must be valid before the write head is one third of the way through the preceding IBG. when writing a record. They cannot change again until Device Data Transfer Complete (Bit 0 of the BDS register) is detected. This indicates that a full record has been transferred to the drive. To continue writing to this drive. these bits must be valid before the write head is two thirds of the way through the IBG. 7 3480 MI EC336395 Write Mode Bits See Bit 6. External Register Bit Definitions (Continued) DF 82 • Copyright IBM Corp. 1984, 1985 f) o o o o o o Externa! Register Bit Definitions (Continued) Type ~ Read Card = 01A-A lP2 XRA Value = 43 DescriPtion / Detail 0 Write Operation This bit is active when 'gap in' is received from the drive. It is reset during a write operation if bit 5 of the Write Control register (WCR) does not become active during the IBG mark. When this bit is not active, there is no writing of data. Also, this bit is not affected bv anv resets to the write circuits. 1 End Write This bit indicates that the last byte of the postamble has been written. The IBG mark must be still written. 2 Reserved 3 Reserved 4 Error 2 5 Error 3 This bit indicates a write data flow error. 6 7 Error 4 This bit indicates a multiDlexed data Daritv error. 3480 MI EC336395 o OF 85 Type = Read Card = 01A-A1D2 XRA Value = F3 The External Register Address (XRA) register saves the value of the external register address during execution cycles of instructions that address XR registers, When an XR error is detected, this register is latched and it contains the address of the XR register being addressed. The XRA register is reset by MP Reset or Power-On-Reset (POR). Note: Bit All cards referenced by this table are on the 01 A gate, label Descriotion / Detail 0 XR Address Extend Bit 0 Set from processor control register bit 6. See Bit 1. 1 XR Address Extend Bit 1 Set from processor control register bit 7. Bits 0 and 1 indicate which XR page to access. XR Page Bit 0 Bit 1 0 0 A 0 1 B 1 0 C 1 1 D 2 XR Address Bus Bit 0 Bit 7 of current instruction. See Bit 6. 3 XR Address Bus Bit 1 Bit 8 of current instruction. See Bit 6. 4 XR Address Bus Bit 2 Bit 9 of current instruction. See Bit 6. 5 XR Address Bus Bit 3 Bit 10 of current instruction. See Bit 6. 6 XR Address Bus Bit 4 Bit 11 of current instruction. Bits 2 through 6 are set from CS Data Bus Hi/lo bits 7 throuah 11 for instructions that address XR reaisters. 7 XR Address Bus Parity Set for even parity for XR (external register) bus address bits 0 through 4. This bit is generated by the microprocessor card (A 1D2) for even parity on the XR Address Bus (bits 0-4, and Pl. This bit indicates a write control error. Reserved ~ Copyroght IBM Corp 1984. 1985 o External Register Bit Definitions (Continued) • The Write Status/Error (WSE) register contains the status of the write circuits and the write operation currently in progress. label o XRA Register WSE Register Bit o External Register Bit Definitions (Continued) OF 85 4.5 Megabyte Buffer Adapter Internal Registers 4.5 Megabyte Buffer Adapter Internal Registers DF88 The following is a list of internal 4.5 Mb/s buffer adapter registers. These registers can only be accessed by putting the page and register numbers into the CMRS register and reading or writing the CMRP register. See MI pages OF 36 and OF 37. Page 2 Registers Type = Read Only This page contains three registers used to report errors detected by the C2PO, and one register that displays the feature level. e CTEe 1 2 CTXE CHFL Check 5 C2PO Error e Check 5 C2PO XR Error Feature Level Register None CTEa Regi ster CTXE Regi s ter CMFL Register Bit Name/Description Bit Name/Description Bit Name/Description e o o 1 2 3 4 5 6 7 Channel Overrun Error 100 ns Clock Ring Error 390 ns Clock Ring Error BC Control Parity Error BC Toggle Error Channel Data Parity Error Feature Level Parity Error Reserved 1 2 3 4 5 6 7 Reserved XR Write Data Parity Error XR Read Data Pari ty Error XR Output Parity Error Resel'ved Reserved Reserved Reserved 1 2 3 4 5 6 7 4.5 Ilbls Buffer Adapter Card Installed EC Level 0 EC Levell Reserved Tailgate A Installed Tailgate B Installed Tailgate C Installed Tailgate D Installed Page 5 Registers Type = Read/Write This page contains two registers that provide the microcode interface for the diagnostic operations on the buffer adapter card. REG I~NEHONIC e 0100 1 CI101 ct-IOO Register CI~Dl Bit Narne/Description Bit Shift Gate Select 0 Shift Gate Select 1 Shift Gate Select 2 Shift Gate Enable Gate BC Disable ECC Reserved Reserved 0 1 2 0 1 2 3 4 5 6 7 3 4 5 6 7 NAt1E RESET Diagnostic Register 0 Diagnostic Register 1 Channel Contl'ol Channel Control Register Name/Description [Scan Out Data (Read)] [Service In (Read)] [Data In (Read)] [\oII'ite End (Read)] Service Out Data Out Stop Out Suppress out [Scan [Scan [Scan [Read In Data (Write)] A Clock (Write)] B Clock (\oIrite)] End (\oIr it e)] 4.5 Megabyte Buffer Adapter Internal Registers 3480 MI EC A57721 () Copyright IBM Corp_ 1982, 1988 I) ,) ,') ,f) DF 88 o Internal _der Adapter Retters o o o Note: All of the internal buffer adapter registers are present if the buffer adapter card supports the Improved Data Recording Capability feature. Only the CETO, CTXE, CMFl., CMDO, and CMD1 registers are present if the 4.5 Mb/s without the Improved Data Recording Capability feature is present. None of the registers are present if the Improved Data Recording Capability or the 4.5 Mb/s channel features are not installed. These are internal registers and cannot be accessed directly. These registers can only be accessed by putting the page and numbers into the CMRS register and reading or writing the CMRP register. See MI page DF 36 and 37 for more information. regi~ter o o CTEO Register CTXE Register CMFL Register 4: Channel Toggle Error Reserved Tailgate A Installed S Channel Data Parity Error Reserved Tailgate B Installed 6 Feature Level Parity Error Reserved Tailgate C Installed 7 CRC Error Reserved Tailgate 0 Installed Type - Read Only Type - Read Only This page contains four sets of channel byte count registers from COMPO-3. The four channel byte count registers in each COMP count the total number of bytes transferred to or from the channel. Channel byte count 0 is the most significant byte of the count field. The registers can be reset by Channel control. This Improved Data Recording Capability page consists of four sets of two error registers found in COMPO-3. Each COMP has two error registers, COMP Error 0 and COMP Error 1. The bit organization is the same for each COMP register. REG MNEMONIC NAME RESET CPOEO COMPO Error 0 CheckS CPOEI COMPO Error 1 CheckS REG MNEMONIC NAME 0 0 CPOBO COMPO Channel Byte Count 0 I I CPOBI COMPO Channel Byte Count I 2 CPIEO COMPO Error 0 .' Check5 CPOB2 COMPO Channel Byte Count 2 3 CPIEI COMPO Error 1 Check 5 COMPO Channel Byte Count 3 4 CP2EO COMPO Error 0 Check5 CaMPI Channel Byte Count 0 S CP2El COMPO Error 1 Check 5 CPOB3 3 CPIBO 4 S CP1Bl COMPI Channel Byte Count 1 6 CP3EO COMPO Error 0 Check 5 6 CP1B2 CaMPI Channel Byte Count 2 7 CP3El COMPO Error I Check 5 CPIB3 CaMPI Channel Byte Count 3 7 8 CP2BO COMP2 Channel Byte Count 0 9 CP2Bl COMP2 Channel Byte Count 1 Bit A CP2B2 COMP2 Channel Byte Count 2 0 B CP2B3 COMP2 Channel Byte Count 3 C CP3BO COMP3 Channel Byte Count 0 0 CP3BI COMP3 Channel Byte Count 1 E CP3B2 COMP3 Channel Byte Count 2 F CP3B3 .F 88 Page 3 Registers Page 0 Registers 2 Internal Buffer .apter Registers COMP3 Channel Byte Count 3 Page 2 Registers COMPO-3 Error 0 COMPO-3 Error 1 NamelDescription Name/Description Upper CRC Error 0 (UCRCO) Channel Adapter Data Parity Error 1 UpperCRC Error I (UCRCI) Channel Adapter Master Transfer Error 2 Lower CRC Error 0 (LCRCO) C3PO to Channel Adapter Interface Error 3 Lower CRC Error 1 (LCRC1) Buffer Control Channel Interface Error 4 Lower CRC Error 2 (LCRC2) Buffer Control Master Transfer Error 5 Lower CRC Error 3 (LCRC3) C3PO tOO ns Clock Ring Error 6 In itialization Error Channel Byte Count Overflow 7 Encode Not Equal to Decode C3PO to Channel Adapter Overflow Error Type - Read Only This page contains three registers used to report errors detected by the C3PO or display the buffer adapter feature level. Bit 0 MNEMONIC NAME RESET CTEO C3PO EllOrO CheckS CTXE C3PO XR Error CheckS CMFL Buffer Adapter feature level None CTEO Register CTXE Register CMFL Register NamelDescription Name/Description NamelDescription Chan nel Overrun Error Comp XR Error Improved Data Recording Capability installed I 100 ns Clock Ring Error XR Write Data Parity Error Comp EC Level 0 2 300 ns Clock Ring Error XR Read Data Parity Error Comp EC Levell 3 Comp Control Parity Error XR Output Parity Error Improved Data Recording Capability allowed - 3480 MI EC A57723 o Copyright IBM Corp. 1982.1989 - IBM Cor.fidential Internal Buffer Adapter Registers OF 88 o o o () o o o () o o o Internal_Her Adapter R.sters (Continu. o o o Internal BU. Adapter Registe.continUed) Page 5 Registers Page 7 Registers Type = ReadlWrite Type - ReadlWrite This page contains two registers that provide the microcode interface for the diagnostic opN<'Ilions on the buffer adapter card. This page consists of four registers in COMPO-3 that are used to establish operation the COMP configuration registers is the same for each COMPo REG 0 MNEMONIC NAME RESET CMDO Diagnostic Register 0 Channel Control CMDI 1 Diagnostic Regisler I Channel Conlrol ... CMD1 Register Bit Name/Description Name/Description 0 Shift Gate Seled 0 Scan Out Data (Read) or Scan In Data (Write) 1 Shift Gate Select 1 Service In (Read) or Scan A Clock (Write) 2 Shill Gate Select 2 Data In (Read) or Scan B Clock (Write) 3 Shill Gate Enable WrHe End (Read) or Read End (Write) 4 Gate BC Service Out 5 Disabl", ECC Data Out 6 Reserved Stop Out 7 Reserved Suppress out MNEMONIC NAME RESET CPOC COMPO Configuration POR at power on time. The organization of ... ... CMDO Register REG 0 parameter~ I CPIC COMPI Configuration POR 2 CP2C COMP2 Configuration POR 3 CP3C COMP3 Configuration POR CMPO-3 Configuration Registers BH Name/Description 0 COMP Online/Offline (I 1 COMP 100 2 COMP 10 1 3 COMP 102 4 COMP Counl 0 5 COMPCount 1 6 1 or 2 Statistics RAMs (1 7 Global CRC = online) = Stat. RAM 2) Page 6 Registers == Type - ReadlWrite This page contains four registers in COMPO-3 that are used to select internal diagnostic functions. The organization of these COMP Diagnostic Registers is the same for each COMPo REG MNEMONIC NAME RESET 0 CPOD COMPO Diagnostic Channel Control Channel Control I CP1D COMPI Diagnostic 2 CP2D COMP2 Diagnostic Channel Control 3 CP3D COMP3 Diagnostic Channel Control CMPO-3 Diagnostic Registers Bit Name/Description 0 RAM Select 0 1 RAM Select 1 2 RAM Select 2 3 Disable Encoder and Decoder 4 Force Bad Parity 5 Force Busy 6 Force Encode Statistic RAM In itializalion Error 7 Force Decode Statistic RAM Initialization Error 3480 MI EC A57723 '!"l Copyright IBM Corp. 1982,1989 IBM Cor. rirt~ntial Internal Buffer Adapter Registers (Continued) OF 88-1 () o o () {) t) o o o o 3480 MI EC A57723 Cl Copyright IBM Corp. 1882, 1988 o o o o IBM ConfldeR'tlal-13 May 89 o o NOTES .8-2 NOTES DF 88 - 2 () {} o () o () {) {) {) o o o o o o o Control Storage Tables and Logs o o Control Storage Tables and Logs o OF 90 CST Table The Command Status Table (CST) contains information about the command currontly executln!l with a dnvtl. Thtl fltllds In thtl CST ilre set by microcode. ThiS table IS acctlsstld by thtl drive address USIl1\l Ihtl support diskette Subsystem Dlsplay/Alttlr prO\lral11. Bits Field B-12 CMD Detail Function Indicates which 5-bit channel command code is to be executed. The 5-blt channel command codes accepted by the control unit are: SENSE COMMANDS: Ward 0 '00' Bits Field 0-3 ADSTAT Detail Function Provides 1I1ltmi stillus and Interrupt condition indications yenerllted by the ehannel ddilpter. 0 1 2 3 5 6 7 8 9 A BC D E F 47 DRIVE PrOVides the drive address for which commilnd WilS received. '08' '10' '18' '20' '28' iI CCW aceepted End of command challl Interface disconnect Selltctlve reset Data path not avmlallie Invalid buffer conditions CCR Interrupt - CCR stacked, refused. or channltl did not chmn from thlt devlee end after a CCR. Sullsyslem error Command sequence Invalid Reserved different IIroup Command reject Bus out panty error Deferred unit check DeVice not ready DeVice hie protected - Modesets other than 3480 Read block 10 Sense Sense I/O device Sense path group 10 Read buffered log READ I WRITE COMMANDS: '80' '88' '90' '98' 'AO' 'A8' '80' '88' - No operation locate block Synchronize buffer Write Read Read backward Test I/O Data security erase CONTROL COMMANDS: chilnnel 'CO' 'C8' 'DO' '08' 'EO' 'E8' 'FO' 'F8' - Rewind Rewind unload Erase gap Write tape mark Forward space block Backspace block Forward space file Backspace file MISCELLANEOUS COMMANDS: '40' '48' '50' '58' '60' '68' '70' '78' 13 14-15 3480 MI EC336395 SPVRINH - Control access Set path group 10 Suspend multipath reconnection Read data buffer 3480 mode set load display Assign Unassian Indicates that supervisor ooerations are inhibited. Reserved Control Storage Tables and Logs OF 90 Control Storage Tables and Logs (Continued) Bits Field 0-3 CHANNEL 4 RECCU Function Control Storage Tables and logs (Continued) Detail Identifies which of this control unit's channel adapters received the command. Receiving CU's bit indicates which control unit received the command. 5 PENDING Command Pending bit indicates that a command is in progress for a drive. 6 FIRST 1st pass complete bit indicates that the first part of a given command is complete. 7 RETRY Command Retry bit indicates that the channel command retry status for the addressed drive has been accepted. B RECERR Record-In Error bit indicates that the read command has a permanent error. but must transfer any available read data to the channel before performing a unit check on the command. 9 NODATA Indicates that a read operation had to be performed (because no data was in the buffer for this drivel when a read command was sent from the channel. 1 0 0 0 = Channel adapter o 1 0 0 = Channel adapter o 0 1 0 = Channel adapter o 0 0 1 = Channel adapter Bit. A B C D 10 11 Field WRTMODE NOTIFY = Control unit 1 o - Buffer write mode 1 - Tape write mode Indicates that Continue Command execution is to be notified by scan when a drive operation has o = Control unit 0 1 Detail Function Write Mode bit indicates whether the drive is operating in tape write or buffer write mode. OF 95 been marked complete. 12-15 CCPARM The Continue Command execution parameter is used by Continue Command execution when it has been notified by SCan that a device operation has been marked complete. DEVICE PREPARATION CODES: Read ahead stopped Buffer write operation complete o 0 1 0 - Repositioning complete o 1 0 0 - Spare code o 1 0 1 - Spare code o 1 1 0 - Spare code o0 0 1 o0 1 1 - BUFFER MANAGEMENT CODES: Buffer deallocation pending 1 0 0 0 - Device sending in progress 1 0 0 1 - Spare code 1 0 1 0 - Spare code 1 0 1 1 - Spare code o1 1 1- SPECIAL EXECUTION CODES: 1 1 0 0 - Sector location complete 1 1 0 1 - Selective reset buffer write complete 1 1 1 0 - Repositioning because of off-line sequence 1 1 1 1 - Spare code 3480 MI EC336395 Control Storage Tables and logs (Continued) • Capwright IBM Carp. 1984. 1985. 1988 :) OF 95 o o o o o o o Control Storage Tables and Logs (Continued) o o Control Storage Tables and Logs (Continued) o OF 100 CST Table (Continued) Word 2 Bits Function LOCDIR Indicates the search dirtlction by the microprocessor for the Locate Block command. 1 CHANGE Indicates whether a change in search direction for the Locate Block command has occurred. Also indicates if the read direction has been changed to determine when to set the Inhibit ERPS in the Logical Device Table (LOT) and the Suppress Read Ahead bit 4 in the CST. 2 NERP Permanent Inhibit CU ERPS bit indicates that the Inhibit ERPS bit in the Logical Device Table (LOT) for this device should not be reset at the end of the command chain. 3 INTDIS Indicates that a interface disconnect has been detected and the channel adapter has not responded with device freed. This bit is set by OCSSPMOS and reset by OCSMDFOS when the device freed has occurred. 4 SUPRDA Suppress Read Ahead bit is set whenever a write type command has been received or whenever the read commands that have been received have changed direction twice. When set, this bit causes read ahead operations to be inhibited until a tape mark has been read or written, or that a Locate Block, Rewind Unload Device operation has been initiated. 5 CONCONN Contingent Connection bit indicates that the drive is connected to the channel that issued the command (which has unit checked) until the next SIO has been accePted bv the control unit. 6 DISCON Indicates that an interface disconnect has been detected by the channel adapter and has been acknowledaed bv the microcode. 3480 MI ntial Control Storage Tables and Logs (Continued) DF 120 o o o f) o f) t {) o o () o o o o o o o Control Storage Tables and Logs (Continued) o o Control Storage Tables and Logs (Continued) o OF 125 LOT Table The Logical Device Table (LOT) contains current information about each drive which is not directly related to a particular buffer segment. Word 1 Word 0 Field Bits Function Bits Function Field 0-7 DEVFLT Contains the fault count for this drive since the last reset of 'Fault Count', 0 INHWROP Inhibits this control unit from startIng a Write operation from the buffer to this drive, 8 INHAUSP Inhibits this control unit from Issuing a forward or backward 'Auto Space' command to this drive. 1 IBGTOUT Indicates that during Gap Out proceSSing an IBG Time Out occurred on the last IBG, 9 INHRDAH Inhibits performing read ahead operations. 2 ENDSYC 10 INHREC Inhibits usina the Reconnect Timer (ITC). Indicates the 'Ending Sync' was detected dUring the read of the last record, 11 INHSERST Inhibits using the serial interconnection to start this drive. 3 STRBC Indicates that writing has started but the read-to-write head timer did not time out, 12 INHERP Inhibits performing internal ERPS. 4 WR1REC Indicates that the first record of a Write operation is readv to be written. 13 MDDEV Indicates that this drive is reserved to the MD. ERPDEV Indicates that this drive is reserved to the ERP. 5 RD1REC 14 Indicates that writing has started but the first record has not been 'read back checked', 15 CALLERP Indicates to call the ERP after Gap Out processing, even if the record was read with no errors. 6-7 TWOBITID Is the modulo 4 count used to identify a Write ooeratlon with its 'read back check'. 8 BUFPIN 9 PCUDA Indicates that this drive's buffer is pinned to this control unit, Permits the control unit's deallocation of this drive, 10 TPMARK Indicates that the last record was a tape mark. 11 SYNCMODE Indicates that this drive is in Synchronous Data Transfer mode (blocksize is more than 64K). 12 RDAHOP Indicates that the current Read operation is not scheduled (Read Ahead). 13 TINHWROP 14 DISERP Indicates that a Read Data Buffer operation is in progress and Write operations are not to be scheduled, Indicates to disable the ERP flag for errors during channel data transfers. 3480 MI ( C"PYllqht !BM Corp EC336395 1~lR4 19A~) Control Storage Tables and Logs (Continued) OF 125 Control Storage Tables and Logs (Continued) Control Storage Tables and Logs (Continued) OF 130 LOT Table (Continued) Word 9 Word 2 Bits Function Contains the hi h order channel block ID. Word 3 Function Field Function 0 SCNALGOR Indicates that Scan is needed to compute the reconnect time for this device. 1 SCNALGOE Indicates that Scan is needed to compute the earlv start time for this device. 2 SCNREC Indicates that when the ITC times out, Scan should call Reconnect for this device. 3 SCNFOREC Indicates that Reconnect should be called in despite the ITC timer. 4-15 SCNRSVD Reserved Field Function Contains the counter for the number of erase gaps (lBGOUTS) that occurred during a write operation. Contains the low order channel block ID. Word 4 Word 10 Function Contains the hi h order device block ID. Word 5 Function Contains the low order device block ID. Bits 0-7 IBGTOCNT B GLOC Indicates that this is the first Gap-In after a Disconnected Locate operation. 9 NOBID Indicates that not to check Bids for correct during So ace ODS. 10 DBSDEV Indicates that this device is assigned to the MP by buffer management for buffer deallocation ourooses. 11 ALLNOREP 12-15 FIROVRN Word 6 Bits Field 0-15 BLCKSIZ Function Contains the block size/ 16 of the largest block in this file. Contains the number of Device- Buffer Overruns that have occurred while writing a record from the buffer to taoe. Word 11 Word 7 Function Bits Field 0-15 BSTPTR Contains the local transfer count. Function Contains the buffer status table PTR under normal conditions. Word 12 WordS Function Contains the remote transfer count. Bits Field 0-15 ERPBST 3480 MI C Copyr'ghl IBM Function Contains the buffer status table PTR under ERP conditions. EC336395 c"'p. Control Storage Tables and Logs (Continued) 1984. 1985 r) ~) OF 130 o o o o o o o Control Storage Tables and Logs (Continued) o o Control Storage Tables and Logs (Continued) o OF i35 PGM Table The Path Group Map (PGM) consists of seven data words for each entry. (Each drive has a separate seven-word entry.) The table is accessed by the drive address. Word 3 Word 0 Bits Field 0-7 MAP Function The first byte is the path group mask that has a bit set for each channel adapter interface that is a member of the path. Detail Bits 0-3 represent control unit 0 channel adapters A through D Bits 4-7 represent control unit 1 channel adapters A through D Bit format: 1000=A 0100=8 0010=C 0001=D 8-13 Not used. 14 ALLASND Indicates that all 8 channel paths have drives assigned. This allows the control unit to differentiate between the All Assigned and None Assigned conditions of the channel assignment in status store. 15 PSWDREC Indicates that a valid password has been set by a control access command. Field Function 0-7 8-15 PASSWRD4 Contains the password (if any) set by the control access command. 8-15 PASSWRD5 Contains the password (if any) set by the control access command. Passwords are generated by the host system. Word 4 Bits Field 0-7 PASSWRD6 Contains the password (if any) set by the control access command. 8-15 PASSWRD7 Contains the password (if any) set by the control access command. Function Detail Bits Field 0-7 PASSWRD8 Contains the password (if any) set by the control access command. 8-15 PASSWRD9 Contains the password (if any) set by the control access command. Detail Passwords are generated by the host system. Function Detail Passwords are generated by the host system. Not used. PASSWRD1 Contains the password (if any) set by the control access command. Passwords are generated by the host system. Word 2 Bits Field 0-7 PASSWRD2 Contains the password (if any) set by the control access command. 8-15 PASSWRD3 Contains the password (if any) set by the control access command. 3480 MI Detail Field Word 5 Word 1 Bits Function Bits 0-7 Function EC336395 II Copyright IBM Corp. 1984. 1985 Detail Passwords are generated by the host system. Word 6 Bits Field 0-7 PASSWRDA Contains the password (if any) set by the control access command. Function Detail 8-15 PASSWRD8 Contains the password (if any) set by the control access command. Passwords are generated by the host system. Control Storage Tables and Logs (Continued) OF 135 Control Storage Tables and Logs (Continued) Control Storage Tables and Logs (Continued) OF 140 PGT Table The Path Group ID Table (PGT) contains the path group identification of each channel adapter interface for both control units. It also contains the Path Group Management byte that includes information about the path mode of the interface (single or multipath). There is one PGT for each channel. Bytes 13 and 14 Bits The Path Group ID Table is affected by Set Path Group ID commands addressed to drives connected to both local and remote control units in a two control unit subsystem. This ensures that both control units will contain the same path group ID information after the execution of any Set Path Group ID commands. There is an entry In this table for each control unit and adapter combination. (Up to eight entries In a maximum, dual control unit, eight channel subsystem.) The table is accessed by specifying the control unit number and channel adapter. Field Function 0 CADIS Indicates that this channel adapter is disabled. 1 PRODIS Indicates that this channel adapter Is processing a channel adapter disable sequence. 2 Reserved 3 Reserved 4-7 Reserved B PROSYS 9-15 Reserved Detail Disable sequence is Initiated by moving the Disable switch to Disable or the Off-line/On-line switch to Off-line. Byte 0 Bits 0 Field SYSERR 1-2 Reserved 3 IDREC Function Detail A system reset is being processed within the control unit. The reset may have been caused by the channel or control unit. The ID Received bit is set if a path group ID has been received for the channel interface since the last Power-On or system reset. PST Table 4 PATHMOD Set for channel interfaces in multipath mode. Reset for interfaces in single path mode. o = Single path 5-7 GROUP o 0 0 = Path group 0 o 0 1 = Path group 1 o 1 0 = Path group 2 o 1 1 = Path group 3 3480 Identifies a path group 10 that has been received by the control unit over this channel. These three bits are a shorthand identifier of the 11 byte Path Sweep GROUP 10. Indicates that the system reset for this channel is in progress. 10 0 10 1 1 10 111 The Pattern Sequence Table (PST) contains 16 entries which indicates the sequence of written and read back check patterns duriny a Device Data Transfer operation. = Path group 4 = Path group 5 = Path group 6 = Path group 7 Control Storage Tables and Logs (Continued) EC33&39& !:. COPY"~"lltlM Corp. 1984 1~.5 '~.b '!lII7 {) o Cl #) \. OF 140 o o o o o o o o Control Storage Tables and Logs (Continued) o Control Storage Tables and Logs (Continued) o OF 145 SNERRH Table The Sense I:::rror History Table (SNERRt1) contains the sense bUlldlH call entry parameters and Ihe lirslfour words of drive sense that result from a drive unit check. The table is updated each lime the sense builder IS called. 1\ is 256 words long and wraps when filled so that the last 20 to 40 errors are saved. Word 0 Word 1 Word vvvv lxyy zz-- Device side POSTPERM vvvv 2xyy zz-- Device side POST 0000 2xyy zz-- Device side POSTERA 0000 3KOO zz-- Device side RECOVER 0000 4xOO zz-- Device side PERM 0000 5xOO zz-- BUFLOG vvvv 6xyy zz-- Device side SNSTRACE 0000 7KOO 00-- Device side SNSRESET vvvv 8xyy zz-- CHECK1 trace entry vvvv 9KYY zz-- Channel side POSTPERM 0000 Axyy zz-- Channel side POSTERA 0000 BxOO 00-- Channel side RECOVER 0000 CKOO zz-- Channel side PERM vvvv DOyy zz-- CUERR vvvv EKYY zz-- Channel side SNSTRACE 0000 FKOO 00-- Channel side SNSRESET 2 Word 3 Description ABCD SNERRH can be displayed by using the "Storage Display/Alter - Control Unit Tables" function, see SDISK 1. When SNERRH IS entered, Ihe lalesl error record is shown In the top line of the MD display. Since SNERRH is a wrap log, the next entry on the MD display will be the oldest entry in Ihe log. II you scroll the display forward or backward to see additional entries, record the microcode table address so you know when you have returned to the latest entry. • ABCD indicates that a control unit or channel error has occurred and Is four words long (see Figure 1). • EFAB indicates that a drive error has occurred and is live words long (see Figure 3). ABCD Word Bils a 0-15 A four-character constant ('EFAB') to Identify each entry. 1 0-7 8-15 Indicates the drive ERP code. Indicates drive address. 2 0-7 Device lIag 1. The device flag is associated with the first error that was detected for the current command. 8-15 Device lIag 2. The device lIag is associated with the last error that was detected. 0-7 Device Command Code 1. Indicates that the command was active or last issued at the time of the first error that is defined In Word 3 bits 8 through 15. ABCD ABCD ABCD 3 ABCD Word 0 1 2 3 Bits 0-15 0-15 Definition Log Request Code Indicates the drive address Contains sense byte 9 - (Control unit flag byte) 0-7 8-15 Microcode error recovery action code Reserved ABCD POST POSTERA POSTPERM RECOVER SNSRESET SNSTRACE These are microcode operations and will be used to report errors to your next level of support. 3480 EC336396 0-7 Device Command Code 2. Indicates that the command was active or last issued at the time of the second or last error that is defined in Word 4 bits 8 through 15. 8-15 Device error code 2. This code is associated with the second or last error detected. ABCD Flgur. 1. Control Unit or Channel Error. Table BUFLOG CHECK 1 CUERR PERM 4 ABCD ABCD SENSE BUILDER REQUEST LABELS Present buffered log (format 21). Counter overflow or unload. Check 1 recovery started at this time. Control unit error not attributable to a particular drive. Recovery unsuccessful, present unit check with the data now In the sense table. Enter and error code and ERA code into Ihe sense table. Enter and ERA code only into the sense table. Single invocation yielding both POST and PERM. Recovery successful, clear the sense table. Unequivocal clear (RESET) the sense tables. Entry only in SNERRH, not in sense tables. Device error code 1. This code is associated with the first error detected for the current command. ABCD Microcode error code - (Control unit sense bytes 10 and 11) 0-3 4-7 8-15 8-15 ABCD A four-character constant ('ABCD') to identify each entry. D811nlllon Flgur. 3. Drlv. Errors ABCD ABCD ABCD ABCD Figure 2. Control Unit or Channel Error. Warda vvvv Bits 0-15 of WORD 1 (see Figure 1). K Bits 4-7 of WORD 2 (see Figure 1). yy Bits 8-15 of WORD 2 (see Figure 1). zz Bits 0-7 of WORD 3 (see Figure 1). Control Storage Tables and Logs (Continued) OF 145 Drive Status Bits 0-15 Drive Status Bits 0-15 OF 150 When Status In is active, the information on the bus from the drive is status bits 0-7 or 8-15 for the selected drive. The status bits are sent to the control unit for the following conditions. • At the end of any Initial Sequence During the Ending Sequence, of a Transfer Sequence A status bit that is the result of a control unit initiated operation is sent only to that control unit. Status that is not associated with a control unit operation is sent to both control units. Bit DescriDtion I Detail Label Bit Label Description I Detail 0 Prep Move Executed This bit is set when a Serial command execution begins. If the command cannot be completed, a Unit Check (UC) is set. The bit is reset after status is sent by the Parallel command. If the Parallel is a motion command, it must be the same command as the Serial command or UC is set, and no motion occurs. 6 Unit Check Bit 6 is set when the drive has detected an error condition that it can not recover from by itself. If a command was in process, it is sent with Device End. If no command was in process, UC will be in the initial status of the next command. The bit is reset after status is sent. 1 Repositioning This bit is set at the end of a motion command as the drive begins the repositioning operation. It stays set until the drive enters Stoplock. If a new command is received and the drive is at the wrong Stoplock position to execute the command, this bit is set and is in the initial status for that command. This bit is reset when the correct Stoplock is reached, or at Gap In time if the command stays connected and the command is in the opposite direction to the last command. 7 Manual Rewind/Unload Bit 7 is set when tape tension is up, the Ready/Not Ready switch is in the inactive position and the rewind/unload switch is pressed. 8 Address High This bit is active during status presentation when the drive address switch is set to hexadecimal address 8-F. It is reset after status is presented. 9 Ready This bit is set after a Load-Op operation when tension is set, the machine reel has rotated at least one revolution, and BOT status is detected (except a mid-tape-Ioad). It is reset by a Rewind-Unload operation or any drive error condition that causes a loss of tension or requires the motor stopping. Bit 1 is also set when the drive Ready switch activated if it had been inactive during the load operation. 10 Patched This bit is set after a successful Patch load to a drive. It stays on until a power down condition, power on reset, or a Reset command. 11 Load Point This bit is set when the drive motion is backward and the BOT is sensed. Drive motion is stopped and no backwards commands are accepted until BOT is reset with the next forward operation. 2 3 Not-Ready-To-Ready New Sector Bit 2 is set when the drive goes into Stop lock after establishing tension and a radius during a load operation. If the drive Ready switch is active, or when placed in the active position, a CU Alert is sent to the control unit. Moving the Online/Offline switch to the online position on a loaded and ready drive will also set this bit. This bit is reset after status is sent during normal interface sequences by the first control unit to select the drive. Bit 3 is set when a Write command is in progress and a new sector number is detected from the drive table, as the command is executing. It is reset the next time status is sent to the control unit. The drive may find a new sector number after the control unit ends a Write operation. The ending status will not show the sector status but the initial status for the next command will. 4 5 3480 MI Device End for Disconnected Command This bit is set at the end of any disconnected command. A control unit Alert is sent on the interface that issued the command. UC may be active when this status is set. Bit 4 is reset after status is sent during normal interface operations. Enables Reg Funnel Parity checker after all LSR locations have been initialized to good parity before this bit is set. Microcode can change active conditions. Device End Bit 5 is set when the drive has completed any connected command. It is reset after status is sent during the ending sequence. 12 File Protected Cartridge This bit is set when a cartridge is loaded if the tape is file protected. It stays active until the current cartridge is unloaded and reset durino an unload operation. 13 Tape Indicate (EOT) or Logical End of Tape This bit is set when the drive motion is forward and EOT is sensed. Drive motion is not stopped and the EOT status stays active until a backward operation moves the tape backward and passes EOT. 14 Physical End of Tape (PEOT) This bit is set when the microcode senses the physical end of tape. Tape motion is stopped and UC is set. 15 Reserved Drive Status Bits 0-15 EC336395 Gil Copyright IBM Corp. 19B4. 19B5 o If a data error is received while moving the tape forward from BOT, and a backward command is executed for ERP, BOT will not be detected. {) OF 150 o o "'_: .. _ 1:_._ . _. . o o o o o 1 D,..,._:,..+,.. .. r LlIIVC LA"CIIIOI J'C~:"""CI" o o o Drivp Extprnal Registers OF 155 Drive External Registers OF 155 The following registers are drive external registers that can be accessed using the support diskette, "Register Display/Alter" option (see SDISK 1). Note: Bit positions marked 'x' may be on or off. Only the important drive external registers and bits are defined. BIT 5 6 7 x x x x x x x x Cartridge Present Sensor x 0 I XOI x x High Addr Bit x X02 x x Off line Switch x x Over Temp Sw x x LED Open Message Display Error Error Timer Error I Tape Path SNSR-A Tape Path SNSR-B Cartridge Latched Sensor Module Parity Error Counter Parity Error Module Parity Error X03 X07 x08 X09 Air Loss Switch x File Protect Sensor Loader Extract Sensor Rdy/Not Rdy Switch x Xl0 Serial Command Error x XII Analog Cnvrter Error File Motor Error 2 4 REGISTER x Machine Motor Error 3 Rewind Sw itch x x 1/9 2/A X25 0/8 X26 ( 8) X27 3480 MI x Drive 10 (4) (2) x x x Gap CNT Parity Error x Timer Parity Error Intf B Error x x x x Power Amp Error Tension Loss x x x Tag/Bus Parity Error x x 6/E 7/F Drive Address 4/C 3/B x (1) x x x Intf A Error x X20 x Timer Error 2 R/Unload Sw itch 5/0 (4) x x x 24v dc Fai lure Logical Address (2 ) ( 1) I NTFC A INTFC B Selected Selected EC336395 ~ Copyr.gh.IBM Corp. 19B4. 1985. 1986 .¥2. At. Notes Notes OF 160 3480 MI EC A57721 Notes OF 160 ,$.) , ~.) iI o o o o o o o o Contents 5 Control Unit Control Unit Functional Area Dlduram 10 10 Data Movement Data Hanrlilng Functional Areas Channel Arlapter Channel Interface Channel Adapter /Status Store Communlcatlor)s Channel Adapter/Buffer Communications Data Buffer Buffer Control Card Buffer Adapter C<1rd Buffer Storage Cards Write Read Read Clock/Detect Cards Read Skew Cards . Read ECC/CORR Card Read Clock and Format Card Drive-Adapter . . . . . . . . Control Functional Areas .. Control Status Store Status Store/Channel Adapter Communications Maintenance Adapter Maintenance Adapter Registers MD Serializer /Deserializer . ...... . Error Checking . . . . . . . . . . . . . Power. . . . . . . . . . . . . . . . . ...... . Voltage Regulator . . . . . . . . . ............. . Power-On-Reset/UV Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 15 15 15 15 20 20 20 20 20 25 25 25 25 25 25 30 30 30 30 30 30 30 30 30 30 30 Tape Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tape Unit Diagram .. ' Logical Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Drive Control Card . . . . . . . . . . . . . . . . . . Write Card . . . . . . . . . . . . . . . . . . . . . . . . Read Preamplifier Card . . . . . . . . . . . . . . . Power Amplifier Board . . . . . . . . . . . . . . . . . . . . . Message Display Power . . . . . . . . . . . . . . . . . . . . . . . . . Pneumatic Supply Drive . . . . . . . . . . . . . . . . . . . Tape Threading-Loading Sensor Test . . . . . . . . . . . . . . . . . . . . . . . ILS Test ..................... . Thread-Load . . . . . . . . . . . . . . Tape Unloading . . . . . . . . . U~oad . . . . . . . . . . . 35 35 40 40 40 40 40 40 40 45 50 55 55 55 55 55 55 Subsystem Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initial Microprogram Load (lML) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel Initiated Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 60 60 60 External Registers Data Flow / Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Moving Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Registers Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XR Detected Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CHK 1 Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CHK 2 Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 65 65 65 65 70 70 70 (, Cppvrl~lht IBM Corp . ; Contents Introduction 3480 MI o EC336395 1984, 1985, 198f) Maintenance Device to 3480 Maintenance Adapter Communication Path MD To;From MA Communl(;atlon Path Signal Lines MD To MA Communlc,IIlon Path Error Checktng Panty Error DeteCtion Communication Path SI!lnal Sequence Error Detection MD Internal Adapter Error Detection MD TO MA COlTllTlUnlcatlon Path OpenltiOflS 80 80 80 80 80 80 81 Tape Record Format ... Tape Format Tape Data Record Format 85 85 85 Read Data Flow Read Operation Buffered Read Read Operation Write Operation Buffered Write Mode Tape Write Immediate Mode Read Back Checking 90 90 90 96 100 100 100 106 Loop Write to Read Data Flow Short Loop Write to Read Long Loop Write to Read 110 110 Drive Data Flow Read Write Read/Write Operations Diagram Motion Control Diagram Motion Control Message Display .. Motor Control Parallel/Serial Interconnector Parallel Interconnector Serial Interconnector 120 Subsystem Configurations , .. , . . . . . . . . . , . . . . . . . . . . " . Single Control Unit Configuration Single Control Unit Command Sequence Single Control Untt Configuration Diagram ,. Dual Control Unit Configuration Load Balancing In A Dual Control Unit Subsystem Status Store To Status Store Interconnection Channel Adapter To Status Store Interconnection Channel Adapter To Buffer (Local/Remote) Interconnection Dual Control Unit Command Sequence Dual Control Updating Status Store 'RAM' ... Writing A Message Into Address 80 and 83 Updating The RAM Status Byte Control Unit To Control Unit Communication Send Message Operation .. . ...... . Receive Message Operation .. . . . . . . . . . . . . . . , . , , .. , , , .. . Status Store to Status Store Interconnections Diagram 135 Channel Commands Input/Output Instructions ... Channel Command Summary Channel Command Descriptions Assign (X'BT) Backspace Block (X'2T) Backspace File (X'2F') .. Control Access (X'E3') Data Security Erase (X'97') 110 120 120 120 125 130 130 130 130 130 130 o OPER 1 Erase Gap (X'lT) Forward Space Block (X'37') Forward Space File (X'3F') Load Display (X'9F') Locate Block (X'4F') Mode Set (X'DB') No Operation (NOP) (X'03') Read Backward (X'OC) Read Block ID (X'22') Read Buffer (X'12') .. Read Buffered Log (X'24') Read Forward (X'02') Rewind (X'OT) Rewind Unload (X'OF') Sense (X'04') Sense I/O (X'E4') Sense Path Group ID (X'34') Set Path Group ID (X'AF') Suspend Multipath Reconnection (X'5B') Synchronize (X'43') Test I/O (X'OO') Unassign (X'CT) Write (X'Ol') Write Tape Mark (X'IF') 165 165 165 165 165 165 165 170 170 170 175 175 175 175 175 175 175 175 175 180 180 180 180 lBO Control Unit to Drive Operation ..................................... . Initial Selection . . . . . . .. . . . . . . . . ............. . Alert Sequence ........ , . , , ........... . Ending Sequence (Control Unit Initiated) Write Operation . . . . . . . . . . . Serial Interconnection Sequence 185 185 185 186 187 188 CONTINUED ON OPER 2. 135 135 135 140 140 140 140 140 141 142 142 142 145 145 145 145 150 150 155 160 160 160 160 160 165 Contents OPER 1 Contents (Continued) Contents (Continued) 110 Interface ........•.................................•.......•........••.•.••... Channel To Control Unit Interfaco Bus Out Bus In Opor.ltlonalOut Address Out HoldOut Select Out C('Inlln.Huf Oul Service Qui Data Out Suppress Oul Select In Operalional In Address In Stalus In Service In Meter In Data In Request In Disconnect In M.trk In Mark Out Control Unit To Drive Interconnection ................ . Select out .. . ............................... . Address Out .. Address In Command Out Status In ... Repositioning In Gap InlOut Clock A Oul . Clock B InlOut Microprocessor 10 Channel Adapler Operation ..•••••..•..••••..•.........••..••..••... MP 10 SS Communication SS 10 CA Communication ......................................................... . MP to SS to CA Communication .................................................... . MP 10 SS Operation (Sel CDTI Bil 0 On) ........................................... . SS 10 CA Operation (Sel con Bil 0 On) ........................................... . MP 10 SS Operalion (Write CTO inlo RAM) ......................................... . SS 10 CA Operation (Wrile CTO inlo RAM) ......................................... . MP 10 SS Operation (Read RAM CTO Location) ..................................... . SS 10 MP Operation (Read RAM CTa Localion) . . . . .. . ...... . MP Exlernal Regisler Read (Read Dala into COR) . . . .. . ............ . MP 10 SS 10 CA Dala Flow ..... . .... XRA Decode ..... . Channel Card Control Register ....... . Channel Card Address Register ................ . Channel Data Regisler ............. . 190 190 190 190 190 190 190 190 190 190 190 190 190 190 190 190 190 190 190 190 245 200 200 200 205 205 205 205 210 210 210 210 215 215 215 215 215 Aulomallc Cartridge Loader (Fe. lure) •••••••••••••••••••••••••••••••••••••••.•••••.•• 240 EC A47957 Real Time Stall.lleal Analysis and Reporting Sy.tem ........•••.•.•......•....••....•.•. 190 220 ar K2 - Cerd 1 I I ~ " .. cd I I I I I I I I , I __________0.2~-~~ _~ ~ Buffer Controls L2 - Co r d : I 1 I __________O..!~-~!.. _ ~ Dc to Reed Ske ... 1 K2 - Cerd 1 POR H4 - Cord 01A-A2 1 -----.! Reod ControL 52 - Cerd LJ Reed ECC R2-Cord 1 1 1 Reed Skew 2 L2 - Cero 1 1 R .. ed Skew 3 M2-Cerd : 1 1 1 1 I I 1 1 1 1 ~---------------+---------------1 I 1 1 I ~ !, : I I i l 1 l __________0.2~-~!.. _l __________O..2~-~~_~ • • • This is 0 fecture on the 348C MOdel A11 end stc~ce~d on the 3 4 80 Model A22. • • •• Tn;s FRU is EC Sensitive. See CARR-CU 4. 3480 MI EC A57721 C Copyrogh' IBM Co,p 'ge2. V ReouLetor T2 - Ce-rd OiA-A1 r---------------+---------------~ R.. ed 1 I Chonne L Adopter F2 - Cc r d D.. I 1 1 1 1 1 I R/W De t o l l ~~~~-=~~.I I 1 1 1 I I 1 r---------------1 I~-----:!I : : I 1 1 IWrit .. Do:e : I I ~ I 1 I I I 1 1 I I I i: i i I i 1 -.J -Drives 8-F prIOsIOnt onLy on duoL control unit sub-system II I I I -----..! Chonr.e L eeep te r cords B.C.D ere instoLled onLy if tke AdditionaL CkenneL 1nterfoce feeture 1. 2. 3 is instoLl .. d 0' A-A i ~---------------~ ---+-----------....., To 0 tl-e r •• control unit Control Store B2 - Cerd Control Unit '~8S rl 'J " ~) OPER10 o o o o o o o Control Unit (Continued) DUring read operations the control unit pre-reads data from the drive into the data buffer. When the host requests the data from the subsystem. the control unit responds immediately and transfers the data to the host at channel speed. Channel Adapter Orders: The microprogram gives the channel adapter an order by writing an address into the channel adapter address register and then writing the order into the channel adapter order register. The control unit functional areas can be separated into two categories: data handling and control. Data Handling Functional Areas The data handling functional areas provide the data paths to transfer data between the host system and the drives for read and write operations. The bold lines in the diagram identify the read and write data paths. The data handling areas include: Data handling functional areas provide the data paths to transfer data between the host system and the drives for read and write operations. The data handling area formats data to be sent to the drives. This area also processes data received from the drives to put it in a form that can be accepted by the host system.· Error checking is also performed by the data handling functional areas. In addition to orders from the microprocessor sent to the status store, there is a small set of orders from the channel adapter to the status store. Channel Adapter Data Buffer Channel Adapter • Write • Read Drive Adapter The channel adapter connects the control unit to a System/370 channel interface. The channel adapter monitors all channel sequences. either independently or along with the microprocessor, through the status store card. The control functional areas control the movement of data and information within the subsystem and between the subsystem and host system. The control areas include: There can be up to four channel adapters, A through 0, installed in a control unit. The adapters are the same, and each adapter is on one logic card. • Control • Status Store • Maintenance Adapter Channel Adapter RAM: The channel RAM keeps track of various control unit conditions, about which the channel adapter needs information to make decisions quickly. The RAM also monitors the status for each drive attached to the control unit that is transferred to the channel. Data Movement The microprocessor, within the control functional area, controls data movement between the tape subsystem and host system, and the data flow within the subsystem. The data buffer area contains user-programmed information. Components of the control unit operate asynchronously to process data in and out of the data buffer, schedule I/O operations with the host system, and controls drive operations and data flow. When a buffered write operation occurs, data is transferred at channel data speed to the buffer. The controller signals the host channel that the data has been written on tape; although, in reality, the data is still in the buffer. When the control unit's workload permits scheduling work for the drive that the data was intended for, the data is transferred to the drive and written on tape. The channel adapter RAM can be thought of as being divided into two halves, a low half and a high half. The low half of the RAM is used as a buffer for control data to or from the channel. The high half of the RAM is divided into four pages. Page 0 is for storing drive conditions. Page 1 is for the channel status for each drive. Page 2 is used for the last channel command given to each drive. Page 3 is for special use. There is a channel adapter 'RAM' in each channel adapter. Malfunction Reset: Malfunction reset is microprogram controlled. If the microprogram determines that a specific channel adapter is causing nonrecoverable errors, the bit corresponding to the channel adapter is set in the channel modifier register on the status store card. This causes the 'malfunction reset' line to that channel adapter to become active. When this occurs, the channel adapter card logically disconnects from all interfaces and is reset. As long as the 'malfunction reset' line is active, the channel adapter is not active. Channel Interface The channel adapter recognizes the following channel sequences or conditions: • • • • • Initial Selection Polling Sequence Ending Sequence Interface Disconnect Selective/System Reset Buffer Data Send/Receive Control Information Data Send/Receive Go Online Go Offline Check Reset o o Control Unit (Continued) The diagram on the preceding page shows the functional areas of the 3480 control unit. This tOPIC explains the purpose of the functional areas. A brief description of the control unit power components is also included. • o OPER ." 11; Channel Adapter to Status Store Communication The status store/channel adapter bus has two uses. First, it is the communication path between the microprogram and the channel adapter. Second, the status store supplies information to the channel adapter to determine initial status to be sent to the channel. Microprogram-to-channel adapter communication is done by external registers. The contents of these registers are gated to the status store/channel adapter bus. Gating is controlled by status store. The status store/channel adapter bus consists of nine bidirectional data bus lines, five response lines, and 10 control lines. All active status store/channel adapter communication lines are minus. Channel Adapter to Data Buffer Communication The channel adapter/buffer bus is the path for transferring customer data. There are two buses: one for the buffer, and one for the remote buffer. The microprogram controls which communication bus the channel adapter card uses at a given time. The microprogram assigns a buffer in the status store, and the channel adapter makes the correct connection to send/receive data. The bi-directional data bus has nine data lines (eight lines for data and one for parity) and seven control lines. All active line levels except the "data OK to parity check" line are minus. The channel interface is the standard System/370 interface. The tag and bus cables connect to shoe card connectors at the bottom of the control unit. All active line levels between the channel adapter and the shoe cards are minus. PAGE 0 DRIVE CONDITION CHANNEL CONTROL PAGE 1 DRIVE STATUS DATA BUFFER PAGE 2 DRIVE COMMAND PAGE 3 SPECIAL USE LOW HIGH PAGE size = 16 bytes RAM size = 128 bytes 3480 MI EC336395 ~ Copvnght IBM Corp. 1984. 1985. 1986 Control Unit (Continued) OPER 15 Control Unit (Continued) Control Unit (Continued) OPER 20 Data Buffer Buffer Control Card Buffer Adapter Card Write The data buffer contai ns a buffer control card, a buffer adapter card. and one or two buffer storage cards. The data buffer is temporary storage for data being transferred between the control unit and the channel. The buffer permits data transfer between the channel and the control unit at channel speed without the mechanical speed restrictions of the drives. The buffer control card contains external registers that monitor and record subsystem conditions and status. It also includes the channel buffer FRU and device buffer FRU registers. The buffer control card controls the data buffer, decodes commands and generates controls to the buffer address, buffer lines, and storage cards. When an error is detected, error registers are collected and read by the microprocessor over the external register bus. These registers become part of an error code that points to a possible FRU. All clock and reset signals needed by the buffer are received on this card and sent to Ii-,e other buffer cards. The buffer adapter card contains: The write functional area contains the write data flow card'that processes and controls the data that is to be recorded on tape. The microprocessor specifies the operation sequence, controls command execution in the drive, and checks the operation sequence. The data buffer stores the data until it is processed. The drive starts by responding with 'gap in' as a synchronizing start point. The processed data and one clock timing are sent to the device adapter, and the device adapter sends the data to the drive. The buffer has data input and output buses. A write operation consists of sending data from the channel to the buffer, followed by sending data from the buffer to the write data flow path. A read operation consists of sending data from the read data flow path to the buffer, followed by sending data from the buffer to the channel. The microprocessor can read and write the buffer at the same time. Buffer Data Write/Read: Data is written into the buffer from the read data flow path or channel through a CRC generator. Then it is moved to an input/output register and becomes two bytes wide. Next the data is sent through two single byte multiplexors to a random access memory (RAM). Data is sent from the RAM to storage through the multiplexers in 2-byte blocks of 16 bytes. Data read from the buffer by the write data flow or channel follows a similar data path. Blocks of 16 bytes are sent from memory to the RAM through the multiplexors. From there it is sent to the two input/output registers through the multiplexers. The data is then sent through a CRC checker one byte at a time to either the write data flow or the channel. The data transfer is started when the microprocessor sets a Read or Write command in either the buffer channel or device command registers. When the transfer is complete, the buffer sets the status in the buffer channel or device status registers, and sends an interrupt to the microprocessor, which then reads the status. Error Checking: All bus, CRC, and parity errors are monitored by two error assembly circuits that set bits in the two buffer error registers. These registers are used to build an error code that can be read by the microprocessor. Parity checking is done on the external register data bus and errors are reported by way of the 'XR error' and 'XR active' lines. A hardware error causes a Check 2 error to occur. • Synchronization registers that communicate with the channel adapter and the read/write data bus. CRC generators and checkers to check for storage bit failures. Device and channel pOinters. Device and channel stop registers. • The buffer adapter card has been redesigned for the 4.5 Mb!s channel data rate. and replaces the old card when the 4.5 Mb/s channel data rate feature is installed. The buffer adapter card compares the current and stop addresses of the devices and channei and sends the result to the buffer control card. Parity is checked for all data going in and out of storage. the read and write data paths. and the channel adapter. Error Checking: Two error assembly circuits monitor all bus, CRC, and parity errors and set bits in two buffer error registers. These registers are used to build an error code that can be read by the microprocessor that points to a possible FRU. Parity checking is aone on the XR data bus and errors are reported through the 'XR error' and 'XR active' lines. A hardware error is a Check 2 error. Initial processing is done in byte parallel form. ECC and CRC bytes are generated and combined with the data into a formatted sequence. A bit pattern of all ones is generated for preamble, postamble, and sync/resync symbols, and is inserted into the data format. The combined data is serialized longitudinally by encoded byte and diagonally by bit. Nine 'write data' lines, one 'write data parity' line, and one 'clock' line are sent to the selected drive through the drive adapter. Control lines and clock lines to the data flow section come from the control section of the write data flow card. Control lines and clock lines are used to control switching, modes of operation, and generation of special marks. Errors are detected and returned to the write data flow card for error reporting and sampling, Buffer Storage Cards The buffer storage is EC sensitive and contains either one or two logic cards. Single card buffers have sizes of 512K bytes, 1024K bytes, or 2048K bytes of storage in an 18 by 256K bits or 1024K bits matrix. Write and read operations are done in 16 byte blocks. In the two card buffer storage, each card contains 256K bytes of storage in an 18 by 128K bit matrix. Write and read operations are done in 16 byte blocks. Error Checking: Error checking is supplied by two signals leaving the buffer adapter card. Address parity is generated on the buffer adapter card and is then checked externally. The 'address valid' signal indicates that the address selected is valid and is assigned to the card. Control Unit (Continued) 3480 MI EC A57721 1: Copy"~"1 OPER 20 IBIIA Corp. 1982. '988 ~), -, :} Control.t (Continued) 0 o o o o fa Control u.continUed) Data Buffer Buffer Control Card Buffer Adapter Card Write The data buffer contains a buffer control card, a buffer adapter card, and one or two buffer storage cards. The data buffer is temporary storage for data being transferred between the control unit and the channel. The buffer permits data transfer between the channel and the control unit at channel speed without the mechanical speed restrictions of the drives. The buffer control card contains external registers that monitor and record subsystem conditions and status. It also includes the channel buffer FRU and device buffer FRU registers. The buffer control card controls the data buffer, decodes commands and generates controls to the buffer address, buffer lines, and storage cards. When an error is detected, error registers are collected and read by the microprocessor over the external register bus. These registers become part of an error code that points to a possible FRU. All clock and reset signals needed by the buffer are received on this card and sent to the other buffer cards. The Buffer Adapter card is EC and Feature sensitive and can contain: The write functional area contains the write data flow card that processes and controls the data that is to be recorded on tape. The microprocessor specifies the operation sequence, controls command execution in the drive, and checks the operation sequence. The data buffer stores the data until it is processed. The drive starts by responding with 'gap in' as a synchronizing start point. The processed data and one clock timing are sent to the device adapter, and the device adapter sends the data to the drive. The buffer has data input and output buses. A write operation consists of sending data from the channel to the buffer, followed by sending data from the buffer to the write data flow path. A read operation consists of sending data from the read data flow path to the buffer, followed by sending data from the buffer to the channel. The microprocessor can read and write the buffer at the same ti me. Buffer Data Write/Read: Data is written into the buffer from the read data flow path or channel through a CRC generator. Then it is moved to an input/output register and becomes two bytes wide. Next the data is sent through two single byte multiplexors to a random access memory (RAM). Data is sent from the RAM to storage through the multiplexers in 2-byte blocks of 16 bytes. Data read from the buffer by the write data flow or channel follows a similar data path. Blocks of 16 bytes are sent from memory to the RAM through the multiplexors. From there it is sent to the two input/output registers through the multiplexers. The data is then sent through a CRC checker one byte at a time to either the write data flow or the channel. The data transfer is started when the microprocessor sets a Read or Write command in either the buffer channel or device command registers. When the transfer is complete, the buffer sets the status in the buffer channel or device status registers, and sends an interrupt to the microprocessor, which then reads the status. Error Checking: All bus, CRC, and parity errors are monitored by two error assembly circuits that set bits in the two buffer error registers. These registers are used to build an error code that can be read by the microprocessor. Parity checking is done on the external register data bus and errors are reported by way of the 'XR error' and 'XR active' lines. A hardware error causes a Check 2 error to occur. • Synchronization registers that communicate with the channel adapter and the read/write data bus. • CRC generators and checkers to check for storage bit failures. • Device and channel pointers. • Device and channel stop registers. • 4.5 Mbls channel feature • Improved Data Recording Capability feature The buffer adapter card compares the current and stop addresses of the devices and channel and sends the result to the buffer control card. Parity is checked for all data going in and out of storage, the read and write data paths, and the channel adapter. Error Checking: Two error assembly circuits monitor all bus, CRC, and parity errors and set bits in two buffer error registers. These registers are used to build an error code that can be read by the microprocessor that points to a possible FRU. Parity checking is done on the XR data bus and errors are reported through the 'XR error' and 'XR active' lines. A hardware error is a Check 2 error. Initial processing is done in byte parallel form. ECC and CRC bytes are generated and combined with the data into a formatted sequence. A bit pattern of all ones is generated for preamble, postamble, and sync/resync symbols, and is inserted into the data format. The combined data is serialized longitudinally by encoded byte and diagonally by bit. Nine 'write data' lines, one 'write data parity' line, and one 'clock' line are sent to the selected drive through the drive adapter. Control lines and clock lines to the data flow section come from the control section of the write data flow card. Control lines and clock lines are used to control switching, modes of operation, and generation of special marks. Errors are detected and returned to the write data now card for error reporting and sampling. Buffer Storage Cards The buffer storage is EC sensitive and contains either one or two logic cards. Single card buffers have sizes of 512K bytes, 1024K bytes, or 2048K bytes ofstorage in an 18 by 256K bits or 1024K bits matrix. Write and read operations are done in 16 byte blocks. In the two card buffer storage, each card contains 256K bytes of storage in an 18 by 128K bit matrix. Write and read operations are done in 16 byte blocks. Error Checking: Error checking is supplied by two signals leaving the buffer adapter card. Address parity is generated on the buffer adapter card and is then checked externally. The 'address valid' signal indicates that the address selected is valid and is assigned to the card. 3480 MI EC A57723 o Copyright IBM CDrp. 1982.1989 IBM Cornfldential Control Unit (Continued) OPER 20 o () o {) o () {) {) o () o o o o o o o Read Read ECC/CORR Card The read area of the control unit consists of: The read ECC/CORR card receives its control and timing from the read clock/format card. Data and detection pointers are received from the read deskew cards. The output-corrected data is sent to the data buffer. The read ECC/CORR card: One or three Read Detect Cards (EC sensitive) • Three read deskew cards • A read ECC correction card • A read clock and format card. The read area receives the read data from the drive, detects the encoded data, and detects the sync pattern. When the read area detects a sync pattern, the data is deserialized to byte format. deskewed, and the pointers are stored. The deskewed data is demodulated and placed in an ECC buffer. Then the data is transferred to the data buffer. Read Clock/Detect Cards The read data is sent from the drive to the read/clock detect cards. These cards detect the data and conditions, and recover the timing and signaling information read from six tracks of the tape. o Control Unit (Continued) Control Unit (Continued) • o • Demodulates the data • Generates error syndromes, error patterns, and pointers • Performs error correction • Conducts CRC checking. The syndrome generator receives 18 demodulated read data bytes one at a time, and generates four syndromes per data frame. Two syndromes are vertical syndrome bytes, and two are diagonal syndrome bytes. The pointer system receives pointers to erroneous tracks from the read detection, deskew, demodulation, and error pattern generators. The pointer values are stored in registers, and sent to the error pattern generators in the correct format. The ECC/CORR card also signals the skew buffer to dead track any tracks with continuous errors. The error pattern generation system consists of two error pattern generators, one generator for each group of nine tracks. The generation system uses syndromes from the syndrome generator and the pointers from the pointer system to generate error patterns. The correction system deserializes the error patterns from the error pattern generators. The corrected data byte is then stored in the correction register, and sent to the data buffer and clock and format card. A 16-bit Cyclic Redundancy Check (CRC) character is generated by the write data flow card when the data record is written on tape. The check characters are generated for all data bytes and resynchronization data patterns. During a read operation, the same CRC character should be generated. After reading the check character, the CRC register should equal zero. If the CRC register does not equal zero, a read error is indicated. o OPER 25 Drive-Adapter The drive-adapter supplies the communication link between the control unit and its attached drives. With a two control unit subsystem configuration, dual control unit communication compatibility provides a second communication path for up to eight additional drives for each control unit. Therefore, any control unit can communicate with up to 16 drives in the maximum configuration. See the write-up on Dual Control Unit subsystems in this section. The drive-adapter card is controlled by the microprocessor. The microprocessor writes in external registers on the drive-adapter card to set up the communication paths. Read Clock and Format Card The read clock and format card supplies clock timings and control for the read data flow, and communicates with the microprocessor. The read clock and format card controls when the deskew will read out, and identifies synchronization and resynchronization bytes. This card also supplies the control lines and clock timings for the read ECC card. Read Skew Cards The read data is sent from the read/clock detect cards to the read deskew cards. The read deskew cards are used to deserialize and deskew data from the tape. Each card has six separate data paths; however, the three cards (18 data tracks) must communicate with each other to deskew the data. 3480 MI 'f; COPY"'1ht ECA57693 IBM Corp 1984. 1985. 1986. 1987. 1988 Control Unit (Continued) OPER 25 Control Unit (Continued) Control Unit (Continued) OPER 30 Control Functional Areas Status Store/Channel Adapter Communications Maintenance Adapter Registers Power The control functional areas control the movement of data within the subsystem and between the subsystem and host system. In addition, these areas provide for communication between functional areas and between control units in a dual control unit subsystem configuration. The control areas also provide for error logging and status information transfer to the host system. Status store communicates with the channel adapters by polling. Status store polls each channel adapter (A-D) in sequence. The following registers are contained in the maintenance adapter card logic: The status store/channel adapter bus has two uses. First, it is the path by which the microcode communicates with the channel adapter. Second, it supplies information to the channel adapter that determines the initial status to be sent to the channel. • Maintenance control The power area of the control unit contains an ac power supply and a dc power supply. The ac power supply provides power for the dc power supply, fans, and ac power for the tape units. The dc power supply supplies power to the control unit. Tape unit dc power is developed in each tape unit dc power supply. • Maintenance status byte • Maintenance data out • Maintenance data in • Maintenance tag out. Control The microprocessor card in the control functional area contains a microprocessor, local storage register, and associated logic for control and communications with the other areas of the control unit. This card also contains all processor external registers, the external interrupt hardware, and most of the prccessor error detection and reporting logic. The processor controls and keeps track of control unit operations through external registers via the external register bus. Control storage consists of tables accessible by the microprogram and the microprocessor. Control storage also contains the initial microprogram load (IML) data after it has been loaded. Any time the microprocessor needs the microprogram to perform a function, it communicates with control storage to obtain the instructions. Control storage uses additional storage contained on the array card Status Store The status store functional area provides a common area in the control unit to store status information. Status information is used by the microprocessor and channel adapter areas for allocation of common resources. The status store area also provides a communication path between the microprocessor and channel adapter. The status store communication card contains the logic that provides a communication path between two control units when two control units are connected as a single subsystem. All machines are shipped with the status store card. The status store communication card is a feature on the 3480 Model A 11 and standard on the 3480 Model A22. A status store card and status store communication card are required for a dual control unit configuration. The status store card contains the microprocessor bus, the channel adapter bus, the controlling logic, and the status store storage. 3480 MI Maintenance Adapter The maintenance adapter provides a way for the maintenance device (MD) to monitor and change the control unit's status. The maintenance adapter card enables the MD to read or write data stored in control storage and to control the microprocessor. The maintenance adapter card performs the basic communication function on the MD bus, and provides a bus for command and data transfer between the MD microprogram and external registers. The mai ntenance adapter card processes these Check 1 error conditions: • Stopping the microprocessor • Disconnecting the channels from the subsystem • Starting the microprocessor under specific conditions. Voltage Regulator The voltage regulator card controls the voltages needed for the storage cards in the control unit. Power-on-ResetIUV Detector The registers are for temporary storage of control and status information, and data used by the maintenance device for trouble analysis. MD Serializer/Deserializer The MD serializer/deserializer is a shift register on the maintenance adapter card that converts serial data from the maintenance device to a parallel format for command decoding or for the microprocessor. When data and commands are to be sent to the MD, the data is converted from parallel to serial data The power-an-reset (POR) card contains the POR circuits and the under voltage (UV) circuits. In addition to resetting the control unit circuits during a power-on, the POR and UV pulses are used to supply POR to the channels. A POR during a power down clamps the channel interface off before the loss of power. During a power up sequence, the channel interface is held off for approximately 800 ms to permit the voltages to stabilize. Error Checking The maintenance adapter card receives and decodes commands from an MD to: • Perform the microprocessor control function • Read and write control storage • Detect and trap error conditions • Send and receive commands and data to and from the MD microprogram for maintenance purposes. The maintenance adapter monitors Check 1 errors. A Check 1 error is a hard microprocessor error in which the integrity of the subsystem is suspect. A Check 2 error is a hardware-detected error. Any of the control unit cards may recognize parity errors or other errors. These errors activate the Check 2 error line to the maintenance adapter and microprocessor. The microprocessor searches for Check 2 errors during normal operation. Control Unit (Continued) ECA57693 o CopynghllBM Corp ~} Microprogram-to-channel adapter communication is done through external registers. The content of these registers is gated to the status store/channel adapter bus. Gating is controlled by status store. OPER 30 1984. 1985. 1988. 1987 {} ~) :J ~J ~,. '.J :} tl ~) ~ l '\ J o o o o o o o o o o OPER 35 Tape Unit Tape Unit Tape Unit Diagram These are high level drawings showing theory only. For detai led point-to-point wiring see the machine logics. ~ r------ This FRU is EC sensitive. See CARR-DR 4. TAPE UNIT WITHOUT EC 333293 (See CARR-DR 4) DRIVE 0 02A--A I D2* MicroProcessor I I I I Dp·" i ce Cont rol Bus to a nd from Cont rol Unit • 1 t Local I I IRemote 1 1 02A-AIB2* Adapter , I 4 ~ I I Read Bus to Cont rol Unit I -- '--- 1 1 Local I I Power Ampl ifier Board t Dev ice Cant rol Bus to a nd from Cant rol Unit 1 • 1 Local I I IRemote 02A-AIB2'\ Drive Control I 1 02A-A I J4'\ Wr i te Local Read Bus to Cant ro I Un i t I I 02A-AIG2* Wr i te Power IRemote p+, I 1 • I I t 1 DRIVE I I 02A-AID2* MicroProcessor 1 1 Local t IRemote 02A-AIB2* Adapter 1 , 1 1 II I I 1 Writ e Data and comm ands to and 1 from next drive 1 , I 4 ~ 02A-AIK4* Wr i te - I 1 3480 MI (¢ ==. COPVflUh1 IBM COfP EC336395 1984. 198~. 1986 1 Local 1 IRemote Message Display Board OUI-A I J2* Read Preamp I if i er I - 02A-AIH2* Read Preamp I if i e r Mechanical Position Sensors 1..J=I::!"·d/",;" Head I • I -- Message Display Board Power Amp I i f i er Board , t Mechanical Position Sensors Pneumatic Supply t -- Optional Feature 1 I I I 1 I t+ Local 1 IRemote I 02A-A IB2" Drive Control + .1 4 I I I I. I I IRemote 02A-AIG2* Wr i te Power 1 1 1 ITransport Assembly 02A-AIJ4* Wr i te Local 1 Power Amp I if i er Board t I I -- 02A-AIH2* Read Preamp I if i er Load er Cont rol Card I 1 Writ e Data and comm ands to and 1 from next drive 1 Read/Wr i te Head I L___________________________________ J 02A-AIH2* Read Buffer ITransport Assembly I DRIVE I ITransport Assembly 1 Read Dat! from the next drive r 02A-AIC2* Digital Servo t p+, I Pneumatic Supply Loader Control Card Power Amplifier Board .1 4 Read/Wr i te Head 1 1 - -. 1 1 u lop t i ona I Feat r e -1-. Message Display Board Mechanical Position Sensors I 02A-AIH2* I-- 02A-AIJ2* Read PreRead Buffer I-- amp I if i er IRemote Message Display Board ITransport Assembly 02A-AIK4* Wr i te 1 DRIVE 0 r 02A-AIC2" Dig ita I Servo TAPE UNIT WITH EC 333293 (See CARR-DR 4) r ----r------------------------------------------------------------,- ------l K Mechanical Position Sensors I 1 1 Read/Write Head 1 1 1 I Read Data from L___________________________________ J the next drive Tape Unit OPER 35 Tape Unit (Continued) * This FRU is EC sensitive. Tape Unit (Continued) OPER 40 Drive Control Card- Write Card- Message Display The drive control card controls all functions within the drive. Write data and commands are received by the adapter section and are passed, under control of the microprocessor section, to the digital servo section and the write card. Read data is read from the tape by the read head and sent to the read preamplifier card, under control of the digital servo section, as directed by the microprocessor section. All motion control is controlled by the digital servo section, power amplifier card, and the microprocessor card. The write card contains the 18 write drivers, the head connector, parity checking circuits, and error checking circuits that check for an open head or head cable, shorted write drivers, and various other write problems. The message display provides a means for the host system and the tape subsystem to communicate with the operator. The message display is a logic board with eight LEOs and two bar LEOs that displays messages that are sent from the processor through the digital servo card. See CARR-DR 4. Logical Components Each tape unit contains two drives and two groups of logical components that control tape movement and data transfer within the tape unit. Each drive and its associated logical and mechanical components operates independently; however, the power and pneumatic supplies are shared by both drives. The diagram on the preceding page shows the components needed to load, move, and unload tape, and to write on and read from tape. This topic explains the purpose of these components along with a description of the tape unit power supply and pneumatic supply is also included in this topic. The drive's mechanical components, sensors, and tape movement operations are also described. Processor CardThe processor card controls all functions within the drive. Write data and commands are received by the adapter card and are passed, under control of the processor, to the digital servo card and write card. Read data is read from the tape by the read head and sent to the read card, under control of the digital servo card, as directed by the processor. All motion controls are controlled by the digital card, power amplifier card, and the processor. Digital Servo CardBecause the drive is a microprocessor based system operating in a real time mode, and because of the tight control that is needed to maintain proper tape tension and tape velocity, high speed control processing is required. The digital servo card is designed to relieve the processor of simple housekeeping work, which increases its availability to perform processing tasks. The digital servo card serves as a buffer and the interconnections between the processor and the rest of the drive. It also gathers information from the various drive sensors, mechanical switches, and error lines from other cards and presents them to the processor. Adapter CardThe drives can be logically attached to one or two control units. The adapter card contains two buses and the controls that permit communications between the drives and one or both control units. In a dual control unit configuration, only one control unit at a time is permitted to communicate with a specific drive. The other control unit cannot access the drive until the first control unit has finished using the drive. 3480 MI Microprocessor The microprocessor section of the drive control card contains the microprocessor, storage for the local storage register, and associated logic for control and interconnections to the control unit. Some external registers (XRsl. the external interrupt hardware, and most of the microprocessor error detection and reporting logic are located in this part of the card. The microprocessor performs microcode to control and monitor control unit activity through the external registers which are accessed by way of the external register interconnections. Digital Servo Power The read card amplifies the 18 read signals generated at the read/write head. The read preamplifier card sends the read data to the control unit by way of read bus local or remote. The bus is selected by the control unit. Power Amplifier Board The power amplifier board accepts digital current inputs from the processor through the digital servo section of the digital servo card, converts them to analog. signals and applies necessary gain and phase shifting to drive the reel motors. The power amplifier board uses the input from the tension transducer to keep correct tension on the tape. The power amplifier board also controls power on, power off, and power on reset. The tape unit ac power is provided by the control unit ac supply. AC power is cabled from the control unit to the first tape unit then cabled from that tape unit to the next tape unit, and so on. The dc power for the tape unit is developed in each tape units dc power supply. The dc power supply furnishes the power for both drives in that tape unit. Loader Control Card The automatic cartridge loader - loader control card has its own microprocessor and storage. The storage is loaded from the control unit IML diskette using the "Patching Path" each time the drive patches are loaded. This code is used by the loader control card to control the functions within the automatic cartridge loader. The loader control card uses the information from sensors, mechanical switches, and cards in the drive to control the loading and unloading of the tape cartridge. The digital servo section of the drive control card serves as a buffer and provides the connections to and from the microprocessor and the rest of the drive. The digital section of the card gathers information from the sensors, mechanical switches, and error lines from other cards in the drive and presents them to the drive microprocessor. Because the drive is a microprocessor based operating system in a real time mode and because correct control is needed to maintain the correct tape tension and tape velocity, high speed control processing is needed. The digital servo section is designed to relieve the microprocessor of having to do certain simple housekeeping routines. Adapter The adapter section of the drive control card contains two buses and the controls that permit communication between the drive and one or both of the control units. A drive can attach to one or two control units. In the two control unit environment, only one control unit is permitted to communicate with a specific drive at anyone time. The other control unit cannot access the drive until the first control unit has finished its operation. EC336395 Tape Unit (Continued) o Copyright IBM Corp. 19B4. 19B5. 19B6 {) Read Preamplifier Card- 1') l OPER 40 o o o o o o o o Tape Unit (Continued) o Tape Unit (Continued) o OPER 45 Pneumatic Supply The tape unit contains one pneumatic supply that is shared by both drives. The pressure side of the pneumatic supply consists of a pump, regulator, and an output filter. The vacuum side of the supply uses the same pump and an inlet filter. D ReadlWrite Head Air under regulated pressure is distributed to ihe drive components through a plenum which acts as a buffer to ensure a constant supply to the components. A pressure sensor attached to the plenum monitors the air pressure and causes a Check 46 to occur if pressure is reduced because of a leak in a hose or a loss of air from the supply. D. Air is supplied to the following bearing surfaces in the tape path to reduce friction and tape wear. • Right Guide Bearing • Left Guide Bearing • Decoupler • Tension Transducer IJ II ~~--- Vacuum (supply hose shown) (supply hose shown) III II. Plenum D. Air is also supplied to the tape lifter solenoid The solenoid is energized whenever tape is not moving. When the solenoid is energized, air blows through a slot in the read write head and pushes the tape away from the head. If the solenoid fails to operate when tape motion is stopped, intermittent read write errors can occur. To Decoupler Note: A solenoid failure does not a/ways cause an error check condition. The vacuum side of the pneumatic supply applies vacuum to the and to the decoupler The tape cleaner tape cleaner removes particulate matter from the tape before it passes over the read write head. The vacuum applied to the decoupler pulls the tape into the decoupler. The decoupler provides a cushion that prevents the tape from stretching during start and stop operations. No error checking is directly associated with the vacuum side of the pneumatic supply. However, vacuum failures can cause intermittent read write errors. D To Transducer Ill. Air Supply ~:-- _ _ _ Output Filter EJ Air Supply to Plenum To Right Guide Bearing Regulator Inlet Filter 3480 MI EC336396 Tape Unit (Continued) OPER 45 Tape Unit (Continued) Tape Unit (Continued) OPER 50 Drive The drive contains the read/write head to lead and write data, and the mechal1lcal components, sensors, and motors to thread tape and move tape forward and backward. The processor controls all mechanical operations in the drive. The processor uses the digital servo and power amplifier to change digital signals used by the control logic to analog signals used by the drive motors. Drive sensors feed back information to the digital servo to indicate motion errors and tape position 50 that the digital servo can modify the speed, velocity, or direction of tape motion. The following sensors monitor the drive: • Cartridge Present Sensor - indicates that the tape cartridge has been inserted into the drive. • Cartridge Latched Sensor - indicates that the cartridge is latched in place. • Tape Path Sensor A - indicdtes Ihatthe tape leader block is at the file reel. • Tape Path Sensor 8 - indicates that the tape leader block is at the machine reel. • Machine Reel Tach Sensor A - senses the position of the machine reel. II is used in conjunction with Tach 1 sensor 8 to generate the 'tach l' pulse. • Machine Reel Tach Sensor 8 - senses the position of the machine reel. II is used in conjunction wilh Tach 1 sensor A. • Tension Transducer - senses tape tension. lis output is used by the microprocessor to control the reel motor power amplifiers. • File Reel Tachometer (Tach 2) - monitors the speed and direction of the file reel motor. Loaded Tape Path Threader Aim File Reel Tach 2 Cartridge Present Sensor Machine Reel Tach 1 Sensor A EC336396 Tension Transducer Tach 1 Sensor B Tape Unit (Continued) C Cop~ngnllUM "';urp 1964. lY85. 1~H6 lYtlr ~) Tape Path Sensor A ---\_1_'__/_1_-1- Read/Write Head 3480 MI Tape Pdth Sensor B ~) OPER 50 o o o o o o o o Tape Unit (Continued) Tape Unit (Continued) Tape Threading-Loading Thread-Load Tape Unloading rape threading-loading is an automatic microprogram controlled operation that begins after a tape cartridge has been inserted and latched in the drive. The operation consists of: The thread-load operation begins by driving the thread motor in a forward direction in a pulsed mode. Pulsed mode provides velocity control lor the threading mechanism. Backward bias is applied to the file reel motor to maintain tension on the tape during threading. The tape unloading-rewinding operation starts when the Unload switch is pressed, and the Ready/Not Ready switch In the Not Ready position. Tape is rewound onto the file reel at high speed until BOT Is detected. • Sensor Test - Tests sensors and associated detection circuitry. • ILS Test - Tests lor interlayer slip_ • Thread-Load - Threading, loading, and positioning the tape at BOT. Sensor Test The sensor test is a diagnostic routine that tests the threading path sensors and the tension error detection circuits. The test is limited to sensors that are in a "light" (not covered) state at the time the cartridge is inserted. In addition, the test sets appropriate lIags if a midtape load Is required or if a cleaner cartridge has been inserted. o To thread tape, the carrier pin is extracted from the file reel by At the same time that the threading the threader mechanism mechanism starts to move, the machine reel Is positioned (nulled) to permit proper entry of the tape carrier pin. The carrier pin, leader block, and tape are then pulled around the periphery of the tape path by the threader mechanism Finally, the carrier pin and leader block are housed In the machine reel Proper engagement of the carrier pin In the machine reel is ensured by a sensor at the machine reel home position. D. II. II. When the threading operation is complete, the threader motor is stopped and the tape is moved forward, under microprogram control, to BOT. A Stoplock condition Is activated at BOT and a 'not-ready to ready' alert is presented if the Ready/Not Ready switch is In the Ready position. Unload The unload (last wrap detect) sequence starts with the tape under tension, at BOT, and with 'rewind unload status' signal active. Stoplock and tension control are deactivated, and the tape Is moved at low speed (less than one meter/second (3.28 feet/second)) to the last wrap null point. The last wrap null point Is where the machine reel Is positioned for the exit of the leader block and carrier pin. o OPE-R 55 The machine reel is nulled to ensure proper exit of the leader block and carrier pin and a small backward bias Is applied to the file reel motor to remove any slack In the tape. The thread motor Is driven backward In pulsed mode. Increased bias is also applied to the IIle reel motor to maintain tape tension. When the leader block is sensed at the cartridge home position, power Is dropped from the file reel and threader motors, and the cartridge tray solenoid is energized. When the cartridge tray solenoid energizes, the tray cover is raised, which permits the cartridge to be removed from the drive. Nole: The cartridge latch should be closed when the tape drive is not being used. (A cartridge need nol be in the drive.) When the tape drive is needed, open the cartridge latch by pressing the Unload switch. When the tape reaches the last wrap null point, the leader block is withdrawn from the machine reel sufficiently to change the state of tape path sensor 'B'. ILS Test This test is performed to determine il an ILS condition exists in the cartridge belore the processing of data. If this condition is detected,the control unit is instructed to issue a "Locate" command to a sector near EDT, lollowed by a "Rewind" command. This operation reestablishes correct tape tension on the reel. • A start/reposition/stop loop starts. • The acceleration rate lor the start is 150 meters/sec (492.13 feet/sec). • At 100% velocity, velocity deviation is checked at each 0132 tach-2's. • If at any 01 the 32 tests made, the velocity is greater than 3.5% of nominal, an ILS condition exists. • The above sequence is repeated ten times. • An alert is issued to the control unit signaling load complete. • " an ILS condition was detected, 'ttnit check' and the appropriate ERP code will be sent to the control unit. ,I I l 3480 MI EC336396 --------i\p l'----B--\P Tape Unit (Continued) ----------. __ OPER 55 .-.- ...... .. Subsystem Initialization Subsystem Initialization This tOpiC describes the power sequencing, initial microprogram load (IML), and channel selection operations. Initial Microprogram Load (IML) Channel Initial Selection Power Sequencing After every power-on-reset. or when the IML button is pushed on an offline control unit. the control unit will IML itself from the IML diskette. The IML diskette is kept in the IML device at all times, When the host system needs to access a drive, it starts a selection sequence on the data channel. The timing chart at right shows when the channel Interface lines are activated and deactivated during an initial selection sequence. Power sequencing for the tape subsystem is activated from the control unit. When power is applied, internal diagnostic tests check voltages. After the voltages have been checked, a general reset of the control unit and drive logic is performed, Finally, a basic function test of the control unit and drive logic is performed. Errors detected during the power on sequence are reported to the control unit. When all tests have been made and the results have been reported to the control unit, the control unit IMLs itself from the IML diskette. The control unit has a permanent microprogram that detects and reads the IML diskette information into the control storage area of the control unit logic. A read operation is performed from the diskette device and the data is sent to control storage. ff the diskette device cannot read the IML diskette, or read errors occur, the Control Unit Error Ughtturns on. Since the control unit is offline to the IML, no information is sent to the host system. When the host system attempts to vary the IML failed 3480 subsystem online, a host system message 'No Paths Available' occurs. Errors that occur during the IML are saved in an area in the microcode. After the MD is connected (with the product diskette) the microcode checks this error field and creates an FSC that is used to troubleshoot the IML failure. If no read errors occur, the control unit performs diagnostic tests to ensure that the microprogram has loaded without any errors and is executing correctly, If errors occur during the diagnostic tests, the 3480 and host system operates the same as with an IML failure with one exception. The difference is the FSC identified when the MD is connected points to the failing area found by the diagnostic instead of an IML failure. Initial selection begins by activating the 'operational out', 'hold out', and 'address out' lines. An address byte that contains the address of the control unit and drive is placed on the 'bus out' Interface line. The 'select out' line is activated and sent to all the units on that data channel, and then is sent to the next control unit. Each control unit, in sequence, compares the address with its own, The control unit with the correct address traps the selection and answers by activating the 'operational in' and 'address in' lines, and by placing its address on the 'bus in' line. The data channel checks the address returned and, if correct, places a command byte on the 'bus out' line and activates the 'command out' line. The microprocessor in the control unit, after checking the device status, activates the 'status in' line and places status (normally zero) on the 'bus in' line. The data channel activates the 'service out' line to indicate that it has received the status byte, OPER 60 Channel Interface Lines OperationalOut---4 Hold Out ----4 t--+-+"') (r-------~ Select Out ---~ l - h H ' Address Out - - - 4 ~*'~ Operational In ----i.----I........~ Address In ---~ l---,rlHt--"" Command Out ---+ _--It--~T---i-""", Status In ----~ l---!-..-+---I--J-I--! Addr ---~I t-t-+-t-~--4~~""'~..u=--.;..- Status Zero At this point, the microprocessor is ready to start decoding commands and processing data. If the IML and diagnostics complete successfully, the control unit wait light is on and the control unit error light is off. Pressing the control unit Online/Offline switch to online, causes the IML device to run again and load any necessary control unit or drive microcode patches. The control unit offline light then goes off, and the host system completes its vary online procedure. In a dual control unit configuration, each control unit is Independent of the other control unit. Each control unit must be separately IML'ed. Any IML or IML diagnostic errors that occur are reported only in the failing control unit. 3480 MI EC336396 'C: COPYright IBM Corp. 19&4. 11185. 1986. Subsystem Initialization OPER 60 1987 o I l \ j o o o o o o External Registers Data Flow / Error Detection The external registers (XRs) are used by the microprocessor that has a 16 bit (one word) instruction to communicate, through the channel adapter to the channel, and through the device adapter to the drive. The XRs are used to control various operations in the functionai areas and also for error retention. The XRs are eight bits, plus parity, in size and are used in read-only, write-only, or read/write operations. All XR errors are reported to either the maintenance adapter (MA) or the microprocessor (MP) card. There are seven functional areas in the control unit that use the XRs. The buffer adapter and the buffer control card are in the same functional area. External Register Addressing Moving Data There is a five bit address in all microprocessor XR instructions permitting up to 32 XRs to be addressed (hexadecimal 0-1 F). Data is moved using three data buses: 2. XR Data Bus A Addresses are .extended' by using processor control register (PCR) bits 6 and 7 (extend bits 0 and 1). 128 addresses can be selected by addressing one of four register pages. Each page contains 32 addresses. The 'extend' bits are not part of the address bus and are not parity checked, but are sent to each functional area from the MP card. Status Store PCR Register Bits 6 and 7 • Buffer 'Extend Bits 0 and I' • Microprocessor • Write Data Flow • Device Interconnections • Read Data Flow 0 0 1 1 0 1 0 1 Figure 1. Maintenance adapter The XRs are addressed by using an XR address bus (a six bit bus) which uses bits 0-4 and a P bit for even parity together with two 'extend' bits (0-1). Extend bits 0 and 1 are in fact the PCR register bits 6 and 7. See Figure 1. These bits are sent to each functional area from the MP card. They are not parity checked. o Hex. Adr. o External Registers Data Flo"-,, I Error Detection • • o Clocking for the XRs is provided by the C5 card. There are 22 sub cycles (50-521!, each sub cycle is 23.1667 ns. 00) Note: There is an XR timing chart on EAD 8 and a drawing on EAD 2696 that may help in understanding the following sequence. B C 0 External Register Operation Pare B Page C Page 0 01) b. The latched XR addressed lines are read through the MDI register when the read XR addressed bits latch (MTO bit 2) is on. c. The MA card also uses the 'XR addressed clock' line to set the MP error latch (MTI bit 3) and MA error latch (MTI bit 5) if the XR address bus has bad parity. d. If 'XR error ungated' line is active, the processor sets the XR error functional area read error latch (PER bit 5). 'XR error ungated' line must not be active during S20-521 time to avoid an error. ( 10) 3. If the instruction specified that an XR was to be written, 'XR write gate' line is activated at SO-S 13 time and the processor places the write data on all three XR data buses. The functional area's gate the 'XR data bus' lines on their internal buses. 4. If the XR address bus and the XR address extend bits have addressed a write XR (XR write gate is on), the functional area register activates its XR addressed line (MP). An 'XR addressed' line is not generated if the XR address bus has bad parity. 5. The MA card checks the XR addressed line for only one line being active. An 'XR error ungated' line is activated if the addressed area detects that the write data had bad parity. An 'error ungated' line is activated if the MA card detects bad parity on the XR address bus, or if more than one XR addressed line is active. The following sequence addresses, reads, and writes into a selected external register. ( 11) 1. Registers The address is placed on the XR address bus by the MP card. 02 I a. The bus contains bits 0-4, P with even parity. b. The 'extend' bits (0-1) are also sent to each functional area to select the page that the addressed register is on. c. Each functional area decodes the data on the XR address bus, together with the 'extend' bits, to determine if one of its registers is being addressed. d. An 'XR addressed' line is activated when an XR in a functional area is selected. 1E 1F Figure 2. If an XR read is occurring, 'XR addressed clock' line is generated and 'XR error ungated' line is sampled at 520-521 time. The MA card uses 'XR addressed clock' line to set the XR functional area error latch (MTI bit 4) and to latch the functional area (MP) 'XR addressed' lines if only one functional area is not detected. A Page Selection Pat A 00 01 Page Page Page Page a. XR MP Bus The XR MP bus is internal to the MP card. Each data bus is eight bits plus a parity bit for odd parity. The XR Data Bus A moves data between the MA, DI, S5, and the MP card. The XR Data Bus B moves data between the MP, BA, DF, and the RC cards. Register Addressing The XR address is common to all cards containing XRs, except the buffer control card. The buffer control card receives only the P-bit from the XR address bus. XR address bits 0-4 are received from the buffer adapter card through a top card connector. OPER If the instruction specified that an XR was to be read, an XR gate is generated permitting the addressed area to gate the data on the XR data bus. XR Data Bus B • o 'XR addressed' is not generated if the XR address bus has bad parity. e. The XR addressed lines go to the MA card where they are checked for only one active line . ._ - - - - - - _ . _ - - - - - - - - 3480 MI EC336395 'll Copyroght IBM Corp. 19B4. 1985 External Registers Data Flow / Error Detection OPER 65 External Registers Data Flow / Error Detection (Continued) At 55-57 time the 'XR load' line is activated by the control store card. The XRA register is loaded with XR address extend bits 0 and 1, and the five bits plus parity of the XR address bus. If an XR was read during the first half of the cycle and the data latched in the scan path had bad parity, the XR read parity latch (PER bit 4) is set. The XR functional area write error latch (PER bit 6) is set if XR write is occurring and 'XR error ungated' line is active at 59-5 10 time. The three XR errors indicated by PER bits 4, 5, and 6 causes the 'XR error latched' line to be active. XR error latched being active causes the 'check 2' line to be active and also activates the 'MP external interrupt 0' line and stops the XRA register from being updated. The XRA register contains the address of the register that was used when the error occurred. External Registers Data Flow/Error Detect. (Cont.) OPER 70 External Registers Data Flow / Error Detect. (Cont.) OPER 70 CHK 2 Errors MTI Bit 3 is set: If the MP XR was found to have a parity error. MTI Bit 4 is set: If no XR or more than one XR addressed line is active. MTI Bit 5 is set: If the XR address bus has bad parity. PER Bit 4 is S8t: Check 2 is used by the functional area's to indicate to the microcode that some error has occurred internal to their area. If a read data parity error is detected by the MP card during an XR read (sets P5R bit 0). XR Detected Errors PER Bit 5 is S8t: CHK 1 Errors If the functional area containing the XR that was addressed detects bad parity on a read (sets P5R bit 0). ERB Bit 0 is set: If there is an XR address compare error. An address on XR address bus does not equal the address that the instruction called for. PER Bit 6 is S8t: If the functional area containing the XR that was addressed detects bad parity during an XR write. ERB Bit 1 is set: If the MP card (registers IMR or PORI has bad parity. ERA Bit 6 is set: If MP internal XR address bus has bad parity. 3480 MI EC336395 .. Copyright IBM Corp. 1984. 19B5 a o ~) o ") \. ~) o o Fytprn~1 Rpni~tpr~ --------- ---0;1-- ---- n~t~ o o o Flnw IFrrnr nptpr.tinn lr.nntinliPtil XR Data and Address I=v+ornal Ro,..i~+or~ na+a I=ln\AI Il=rrnr no+o,.+inn ............. .., . . . . . . . . . . "" • • I _ • • "". _ ................. v .• - _ . , . . . , •• ,... . . . . . . . o o ~ OPER 7" .- OIA-Al Logic Board (FRU 139) r------------------------------------------------------------------------------------------------l 01A-A1C2 Control Store Card 'bF - DETAIL A CC 01A-A1K2 Address Bits (0-4) to B C _ - XR Wr i te/Read - - - - - - - _ . -XR - XR Read Gate - - - - - - - -... + - - - XR Data Bus Bits (0-7,P) bi di--. TCC I BA002, 003 01A-A1L2 BC003 L - - . o r - - - - - - - - , - - - - - XR Load --,1--.1--------,1 . .- - -....- - - - - - - - - - - - - - - XR Data Bus A (BIOI) - - - - - - - - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _+. I I I ..---+-----------.. .,...- - XR Data Bus B (B I 0 I) - XR Address Bus (p, 0-4) ..---....-----------++- -+ ---+ ~ (FRUll71 - .! MPOOI r- 01A-A1Q2 Drive Adapter Card ~ ~ f-+ ~ XR Ext Add (0-1) - - x~ 1::: --"""T"""'TI ... 1....+ ~ - --. '-- r- r- 10...+ ---+ - WD XR Addressed _ (FRU121) (FRUl14) 55001 BCOOI ---+ - DV XR Addressed L...------------++ll--+ - MP XR Addressed (FRU 119) r--- ---+ - BA XR Addressed 01A-A1L2 Buffer Control Card (FRUl15) r--I---- RCOOI rml 01A-A1G2 Status Store Basic Card 01A-A1P2 Write Data Card A BAOOI (p) I ----+ (FRU120) DIOOI 01A-A1S2 Read Clock And Format Card 01A-A1E2 Maintenance Adapter Card See Deta i 1 --. (FRU118) L,-------, lo..r-----' ..,.... 01A-A1K2 Buffer Adapter Card I I I (FRUl16) I---- MADOI DFOOI ~ - RC XR Addressed --11----' -+------------11-----' -t------------t-------------+----1f-J -t------------t-------------+---~f-I - XR Addressed Clock L •• ~I________________________·~~__- ~~TE;~~:r~~~~c~O -.---------------------------_~I----------------'I L-..... 55 Addressed - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---J. ________________________________________________________________________________________________ ~ Point-to-point wiring on a board is shown on the Control Unit and/or Drive net wire lists. 3480 MI EC336395 ~ Copynght IBM Corp. 19B4. 1985 External Registers Data Flow / Error Detection OPER 75 Maintenance Device to 3480 Maintenance Adapter Communication Path The maintenance device (MD) is the primary tool for servicing the 3480 subsystem. It executes maintenance analysis programs contained on a diskette and has a communication path to the 3480 subsystems maintenance adapter (MA) card. This communication path is used to send commands to the MA from the MD where they are recognized as control or data transfer functions. The direction of the data movement is determined by the type of function specified by the MA (read/write) and by the type of function specified by the MD program (get/put!. The communication path signal lines used for control of data byte movement differs for MD 'get' or MD 'put' type functions. Command and data bytes are sent serially by bit from the MD to the MA. Data and status bytes are received by the MD on a separate serial data line. The purpose of this description is to give information to explain the function of each signal line and its use for specific operations. The signal lines are named from the Product Maintenance Adapter Perspective (such as, Serial Data In). The signal levels used are +5 V dc to 0 V dc with +5 V dc being the inactive level. Read Shift This line is activated by the MA in response to 'status in' and is used to request data bytes during an MD 'put' operation. It is a signal to the MD to start sending shift pulses. It must go inactive at the center (+ edge) of the 9th shift pulse. This line goes active then inactive for each byte that is sent by the MD. 9600 bits per second (bps) pulses ( 104 microseconds) are placed on this line by the MD in response to the 'read' or 'write' signals from the MA. These pulses control the movement of SERDES register bits to and from the MD and the MA. Shift pulses also appear during the 'diagnostic wrap' part of an MD port 'open' operation. See Figure 1. Statu s Read Seria I Sh ift Seria I Wr i te Statu s Enabl e . In ~ Data In ~ Data Out ..Out . .. - MD MD SERDES MA MA SERDES MA Status In The MA card also checks the parity of the data it receives from the MD. If an even number of bits are detected, the MA ends the operation by activating 'status out' and 'write' at the end of the 9th bit period. This error condition is also indicated by a bit in the MA cards MTI register, and the 'status out' sequence sets error bits in the MD for detection by its program. Write Sh i ft Gate ,---J Communication Path Signal Sequence Error Detection The MD checks for the correct signal during 'get' and 'put' operations. If 'read' is the expected signal, and 'write' appears without 'status out', an error is reported by the MD program. MD Internal Adapter Error Detection The MD checks for the correct internal interrupt sequence during all port operations and errors are reported by the MD program. This line is used together with the 'write' line to end an MD 'put' operation if the MA detects bad parity on an incoming data or command byte. 'Write' and 'status out' may be activated when there is no other activity and the MD will send shift pulses to move a single byte of status information from the MA to the MD. This asynchronous operation occurs following all commands that are executed by the 3480 microcode. See Figure 5 on the following page . ... Figure 1. 3480 MI This line is used to send serial data bits from the MA SERDES register to the MD SERDES register. It changes on the trailing (+) edge of the shift pulse and it is valid for the MD to sample it on the leading (-) edge. The bit order is 0-7, then the 'P' bit is last. Since the MD samples for bit 0 on the leading edge (-) of the first shift pulse, the data in the MA SERDES must be valid before the 'write' line is activated. Status Out - This line is activated at the start of an operation by the MD to signal the MA to respond with 'read' and to receive a command. It is also activated when all data bytes have been sent or received by the MD to signal the end of the operation. The command byte sent for the second 'status in' sequence is 'end-of-message' (EOM) (X'40'). This line is deactivated when the 'read' signal goes inactive. Data received by the MD in a 'get' operation from the MA is tested for an odd number of bits (vertical redundancy). If an even number of bits are detected, the operation is ended with a 'status in' command sequence and an error condition sent to the MD program. This line is activated by the MA to send data to the MD when a 'write' type command is received in an MD 'get' operation. It is a signal to the MD to start sending shift pulses. It must go inactive at the center (+) edge of the 9th shift pulse. This line goes active then inactive for each byte that is received by the MD. It is also used in combination with 'status out' to end an MD 'put' operation in progress or asynchronously to send a status byte from the MA to the MD. ~ ~ Parity Error Detection Serial Data Out This line is used to send serial data bits from the MD serializer/deserializer (SERDES) register to the MA SERDES register. It changes on the leading H edge of the 'shift' pulse and it is valid for the MA to sample it on the trailing (+) edge. The bit order is 0-7, then the 'P' bit is last. See Figure 1. OPER 80 MD to MA Communication Path Error Checking Serial Data In MD to / from MA Communication Path Signal Lines MD MD to MA Communication Path Serial Data In Enable This line is activated by the MD during an MD port 'open' operation. It is monitored by the MA card indicating that the MD is connected. It must be active during all communication path operations. Shifting Bits Through SERDES EC336395 MD to MA Communication Path • Copyright IBM Corp. 1984. 1985 l J f\ V OPER 80 o o o o o o o c o o o o o o o o c o o o o o o o o o o o o o o o o o Maintenance Device to 3480 Maintenance Adapter Communication Path (Continued) MD to MA Communication Path Operations • Open with Diagnostic External Wrap • Put from the MD to the MA 2. • Get from the MA to the MD. 1. Open: This function is executed in the MD and it resets the MD hardware adapter, activates the 'enable' line, and tests the data path between the MD and the MA. This test is accomplished by shifting a data byte (X'SA') from the MD SERDES through the 'serial data in' path to the MA SERDES, and returns the data to the MD SERDES through the 'serial data out' path. This test requires 18 shift pulses. See Figure 2. Put: In this function both command and data bytes are sent across the 'serial data In' path using the 'read' and 'status . In' lines for control. The MA command byte is sent first followed by the data bytes. The EOM command byte is sent to end the operation. Command bytes are indicated with the 'status in' signal line. The MD Initiates the operation by activating the 'status In' line and the MA responds by activating 'read'. When the active 'read' signal line Is detected by the MD, It starts sending 'shift' pulses that moves data or command bytes. There Is a form of 'put' function with no data transfer that Is used to send a command byte only for control type functions that have no data associated with them. See Figure 3. MD to MA Communication Path (Continued) 3. Get: In this function, the command bytes are sent to the MA by way of the 'serial data In' path, but the data bytes are controlled by the 'write' signal line and are received by the MD on the 'serial data out' path. You will notice that this operation is similar to the 'put' function except the 'write' line is used to move data and It is active before 'status In' and 'read' becomes active to send the EOM command at the end of the data transfer part of the operation. See Figure 4. Nota: See the Maintenance DevlcelMalntenance Adapfer Diagnostic on DIAG 1. This diagnostic permits you to repetitively execute (loop) any of the above operal/on•. Enable Communication Path Enable - Status In 9 Bit Period Shift Pulses MA Sample Time Bits Data In OPER 81 e 1 2 3 MD Sample Time 4. 5 6 7 pel 2 3 4 S 6 'SA' 7 IL-_ _ _ _ _ _~ - Read - Write ,34S9 Status Byte to MD - Status Out ~L-_ _ _ _ _ _~ - Shift -,Gn1r- - , 7 n Pr--- P U Figure 4. U U U 9th Shift Pulse Status Out Sequence Data Out 'SA ' - - - - - - - - - - - - - - - - - - - , Figure 1. MD 'Open' Operation - Status In - Read , _-- I ..... --, COllll1and 1'--_- ___~r_ --'1 , . . ____E_DM _ _---Jr_ _ _--'IlL--_Da_ta_to_34_S9_ _ - Shift Pulse ~ Figure 2. 'Put' Opera lion 'rom MD to MA - Status In ' _-- __---'r .... - Write --,IL-_ Data from 34S9 _ - Shift Figure 3. 3480 MI 'Get' OperaUon 'rom the MA to MD EC336396 e COPyroght tBM Corp. 1984. 1985. 1986. 1987 - aggs ¥4¥± MD to MA Communication Path (Continued) OPER 81 Tape Record Format Tape Record Format OPER 85 Tape Format This diagram represents the general format of the tape. Tape Formats ~----,-----~------~----.-------III-----'------'-----~-------.------r---~ L -__ ~ laG ______ Preamble ____ ~ ~ Record ____ ~ Postamble III ____ 13G _______ ~ ______ Record ____ I Postamble ______ ~ ~ ~ ____ ~ __ There are three 3480/3490 tape formals and two tape lengths: ~ • 3480 Format This format is used when the data compaction and auto-blocking facility is not present is disabled, or when the length of the compacted logical block exceeds the m;tximum buffered compacted block limit if an 18 track format is desired. Tape Data Record Format This diagram represents the general format of data records on tape. 3480 format is only supported on CST. r-~------~--~----r---------~----~--------~-----IIII----------------~--~---.------'---~ BG Preamble 71 data frames 71 data frames Resync 71 or fewer data frames Sync I Sync ~~------~--~--~--------~----~--------~-----IIII--------------~----~--~----~--~ Tape Media Dimensions • 3480 XF Format This format is used when the data compaction and auto-blocking facility is enabled and the length of the compacted logical block does not exceed the maximum buHered compacted block limit if an 18 track format is desired. 3480 XF format is only supported on CST. • 3480-2 XF Format The 3490 models capable of writing 3480-2 XF format sUPPol1 two tape lengths. Cartridge System Tape (CST) and Cal1ridge System Tape - 2 (CST -2). Other models of 3480/3490 support CST only. This format is the only 36 track format anc is used whether data compaction is enabled or disabled. 3480-2 XF format is sUPPol1ed on either CST or CST-2 Table 1. Tape Media Dimensions 1 Characteristic 3480 modeis A 11 and A22 control units, 3490 models 03 i and 0::2 subsyterns. and 3490 models A01 and A02 control units provide the following capabilities: CST CST·2 Unit 12.65 (0.498) 12.57 (0.495) mm (in) Tape Length 165 332 m • 3480 XF Format Read/Write Capability if the Oata Compaction and Auto-Blocking Facility is installed. Reel Circumference 280-307 310-314 mm • CST handling capability. Tape Width • 3480 Format Read/Write Capability. 3490 model D41 and D42 subsytems, and 3490 models A 10 and A2G control units provide the following capabilities: IBM Enhanced Capacity Cartridge System Tapes should not be mounted in a 3480 subsystem. Only the 3490E has the design updates needed to support the use of the enhanced capacity cartridge. • 3480-2 XF Format Read/Write Capability. Tape that exceeds the length of IBM Cartridge System Tape could cause damage to either the tape or the drive, if processed to its Physical-End-Of-Tape. When an enhanced capacity cartridge is mounted in a 3480 Magnetic Tape Subsystem, the subsystem will return an ERA code to the operating system, indicating a tape length incompatibility. If this occurs, the job will not run and should be rerun with the cartridge mounted in a 3490E Magnetic Tape Subsystem. See MSG section for a discussion of ERA codes. 3480 MI • 3480 and 3480 XF Format Read-Only Capability. • CST and CST-2 handling capability. EC C13783 Tape Record Format OPER 85 o Cupyrillhl 10M Curp. 1984, ID91 ~) (1 o {) () \) ~) ~ ) ) ~) ~) ) Read D8FIOW o This topic describes the major data flow paths within the subsystem that are used to transfer data during read and write operations and that control tape motion. In addition, data flow for the loop write to read diagnostic routine is also described. Read Operation The diagram on the OPER 95 page shows the read data flow path within the 3480 tape subsystem. Buffered Read A buffered read operation moves the data twice - first from the drive to the control unit data buffer, and then from the data buffer to the channel. The move from the drive to the buffer is performed at the drive data rate. If multiple read commands have been sent to the same drive, the control unit might cause the drive to read the next data block in the file before the channel asks for it Therefore, the requested data block might already be in the data buffer. If it is, the control unit sends it to the channel at channel speed as soon as the Read command is received, without requiring data transfer from the drive, including the drive start up time. Channel end and device end are sent as ending status and the operation is comp/ete when all the requested data in the buffer has been sent to the channel, or the channel has stopped requesti ng data. If the data block is not in the buffer, the control unit responds with a channel command retry. The channel command retry causes the channel to disconnect from the subsystem and to become available for other host system work. o o o o o DataFlow ~R90 Read Data Flow OPER 90 • As the data block is read from the tape, it is loaded into the data buffer. At the same time, the control unit signals the channel by sending a device end. The channel responds to the device end by sending the original Read command. When the control unit receives the Read command, it starts sending the data block, one byte at a time, from the data buffer to the channel. The drive might still be sending data to the buffer at this time. When all the data has been transferred by the control unit from the buffer, or the buffer and the drive, or the channel stops requesting data bytes from the buffer, the control unit sends device end and channel end to end the operation. The channel might not have requested all of the data bytes in the buffer. In this case, the remaining bytes are discarded. If any nonrecoverable errors occur during any part of the operation, unit check is sent with device end; the host system program requests sense data, and the control unit sends the drive sense bytes to the channel. If the end-of-tape (EDT) is detected during the read operation, a unit check is sent with ending status. If the BOT area is detected during a read backward operation, a unit check is sent with ending status. Improved Data Recording Capability is not supported during a Read Backward operation. The control unit then selects and starts the addressed drive. As soon as the drive is up to speed, the control unit checks for read data from the drive. If a tape mark is found, the operation ends with unit exception, channel end, and device end. If no tape mark is found, the control unit checks the inter block gap, synchronization, and preamble characters for correct patterns and timing. 3480 MI EC A57723 C Copyright IBM Corp. 1982.1988 IBM Confidential o o {) () o I} {) {) () () o o o o o o Read Data Flow o o o Read Dala Flow 11,ls hlPIC dt!scr Ib"s tile malor datd IltlW paths wrthrn tht) that are USt!tlto translllI data durin!l r!lad ant! wllh, "Pl)"ltl()n~; and th,]t control tape motion. In addition, data flow for lilt! loop Wlltu to I cad diagnostiC rOlllino IS also descllbed. sIJl)~;y"h"n Read Operation Tlw he,iVY lilies III IIw dlaU',11Il on the followlilY pallO show tho re,ld d,lta 1I0w path wllIlin the ;14filJ talle subsystem. Buffered Read A bulleled lead operation movus lilt) data twicu first from tho (1live to the control unit data buffor, and then fromthu data buffel to tile channel. The move from the drive to the buller is performed at the drive data ratu. If multiple read commands have been sont to the sarne drive, tho control unit might cause the drive to read the next data block III the file before the channel asks for it. Therefore, the requested data block might already be in the data buffer. If It is, the control unit sends it to the channel at channel speed as soon as the Read command is received, without requiring data transfer from the drive, includlll(lthe drive startup lime. Channel end and device end are sent as ending status and the operation is complote when all the requested data In the buffor has been sent to the channel, or the channel has stop pod requesting data. If tho data block is not in the buller. tho control unit responds with a channel command retry. The channel command retry causes the channel to disconnect from the subsystem and to become available for other host system work. o OPER 90 As the d.Jta IJlnck IS I tldd II 0111 Iht! t EC336395 Copyr.gh.IBM Corp 1984, 1985 o Drive Data Fiow (Continued; The Stoplock (position-hold) mode is used when the tape is in a stopped position and under tension. When in Stoplock mode, the tape lifter solenoid is energized to prevent the tape from sticking tCl the head. The drive can independently reposition the tape from one location to the preceding Stoplock location, under direction from the control unit. Thus, the drive can independently revert to the preceding data block position for fast error recovery. Once loaded, the drive maintains one of three Stop lock positions, in anticipation of the next command. • Read Forward Stoplock, ready for a read forward • Read Backward Stoplock, ready for a read backward • Write Stoplock, ready for a write. Stop lock positions are achieved automatically by the drive, and are based on the command just executed. At the end of a particular command where no similar command is immediately following, the drive always assumes that some time in the future the next command to be executed will be the same as the last one. The drive repositions the tape to the Stoplock position that accommodates the next (similar) command. The exception to this is a Backspace Block command. After a Backspace Block command, the drive assumes a Read Forward Stop lock in anticipation of a subsequent Read command. o o OPER 130 Message Display Parallel/Serial Interconnector The digital servo also communicates with the message display by way of the 'XR repowered data' bus that also connects to the power amplifier, additional display control signals, and switch signals from the operator panel. Commands are sent to the device on the Device Control Bus (DCB). For a dual control unit subsystem, cables DCB local and remote are used. For a single control unit subsystem, only the DCB local cable should be connected. The adapter card has two separate parallel paths (local/remote) and a single serial path. (The serial buses are connected together on the adapter card.) Motor Control The digital servo card functions as a buffer and the bus between the microprocessor and the other areas of the device. Like the adapter card, the processor communicates with the digital servo external registers using the XR data and address buses. The digital servo sends the data and control signals to the power amplifier board. The power amplifier converts this digital information to motor current. The digital servo then collects information in its external registers from the motor tachometers and tape sensors. This information is used by the processor to control the speed of the drive motors. Parallellnterconnector Commands received on one of the parallel interconnection are controlled by the device microprogram once the 'command out' tag becomes active. (Adapter hardware logic processes the device selection.) The command is controlled by the processor, which communicates with the adapter using the external registers on the adapter and the XR data and address buses. Seriallnterconnector The serial interconnection permits limited communication to the device while the parallel interconnection is busy or has failed. Only non-data transmission commands are sent over the serial interconnection. The adapter card synchronizes and gates the serial clock and data to the digital servo card, where it is decoded. The data path runs from the DCB cable, through the adapter, to the digital servo. Once decoded, the motion commands are controlled by device microprogram just as if they had come on the parallel interconnection; hardware-only commands are executed independent of microprogram. Drive Data Flow (Continued) OPER 130 Notes 3480 MI Notes EC336395 N;otes • eap,right IBM Carp. 1984. 1985 () {) OPER 131 OPER 131 ,\ " j o o o o o o o o . . . +8"" r'","VII ....... f:Igul .. ·a+: ....... '" s U..,SYS"OWIII "IVII" The 3480 tape subsystem can be configured as either a single or dual control unit subsystem. In a single control unit subsystem, the control unit sends data to and receives data from its attached drives. In a dual (two) control unit configuration, either control unit can transfer data to or receive data from its own drives or the drives attached to the other control unit. This topic describes the operation of both configurations. Subsystem Configurations 8. 9. When the interrupt is detected by the microprogram, it examines the Channel Response Register (CRR) in status store to identify the reason for the interrupt and to find out which channel adapter bit is set. A single control unit configuration consists of one control unit with up to eight attached drives. The control unit receives commands and data from the host system and transfers data and subsystem status by way of the channel and its channel adapter. The diagram at right shows the data paths between the host channel, control unit and drives. 55 Status Store adapter, which in turn, resets 'control unit busy' in the channel adapter and permits the processing of a new command. 11. The microprogram initiates the command, sets up the buffer, starts the selected drive, and controls the data flow to or from the drive. Rem Remote , , Host Channel Host Channel Chan Adapter A Chan Adapter B Chan Adapter C Chan Adapter SS SS SS SS Loc Rem Loc Rem I I I I I I I The host issues a channel command to the subsystem. 2. The channel adapter waits to be polled by status store. 3. The channel adapter requests a device assignment and the device status byte from status store. 4. Status store tests the device assignment byte, and if not assigned elsewhere, sets the channel adapter bit and responds with the device status bit. 5. The channel adapter uses the device status bit to generate initial status. 6. The channel adapter passes the initial status to the host. 7. The channel adapter stores the command, device condition byte, and interrupt request code, sets control unit busy, and activates a level 6 interrupt. Rem 0 Loc Rem I I Status Store Microprocessor Buffer 1. Loc I I Single Control Unit Command Sequence An example of a typical single control unit command sequence is: OPER 135 , Host Channel an ending status byte in the channel adapter RAM and directs the adapter to present the status to the host system. interrupts the microprogram after the ending status has been transferred and requests that the device be freed in status store. Lec Local , Host Channel 12. When the operation is complete, the microprogram stores 13. If command chaining is not indicated, the channel adapter o Single Control Unit Configuration Diagram The microprogram interrogates the channel RAM to find the reasons for the interrupt and the command byte. 10. The microprogram resets the interrupt to free the channel Single Control Unit Configuration o Loc Rem Data Flow Device Adapter Loc Rem Adapter Drive 0 Loc Drive 7 Rem ------------- ------------- 3480 MI EC336395 ~ Copyright IBM Corp. 19B4. 19B5 Subsystem Configurations OPER 135 Subsystem Configurations (Continued) Dual Control Unit Configuration The dual control unit configuration interconnects two control units. This dual control unit configuration permits operations in the subsystem to be balanced between the control units for most efficient use of subsystem resources. This mode of subsystem operation is transparent to the host system, because subsystem operations are automatically handled by the subsystem hardware and microprogram. Note: If when using a dual control unit subsystem one of the control units is not able to detects a response from the other control units, it indicates this in the other control unit by setting PER register bit 2 (collision detect), in that control unit. See PER bit 2 in the MI OF section. In a dual control unit configuration the following four communication paths are used: II. • Status store to status store • Channel adapter to status store • • D. II. Channel adapter to remote buffer II. Subsystem Configurations (Continued) Status Store to Status Store Interconnection II The status store to status store communication path is used to give the two control units the ability to synchronize their individual operations and to provide a communications path between the two microprocessors using a 'master/slave' mode of operation. When either control unit is in the 'slave' status, status store does not execute orders. Part of the status store communication path between control units is the 'RAM' address bus, RAM data bus, and 'memory write' signal. When a memory write operation is performed the RAM address bus contains the address of the status store RAM; the RAM data bus contains the data being written to the RAM, and the memory write signal is used to gate the data into the RAM. When either control unit is written into, the 'RAM' in the other control unit is also written into with the same data. Figure 1 on the following page shows the data paths between the host channel, control unit, and drives. SS Status Store Loc Local Rem Remote Both control units monitor their workloads and periodically balance their work by reassigning drives from the more active control unit to the less active control unit. Reassignment may occur at any time during the host processing of a drives tape. D EJ The channel adapter to status store interconnection supplies the communication path for data and status information between the channel adapters and status store. All channel adapters in a control unit share the same local and remote buses to the buffer. Only one is permitted use of the bus at anyone time. The status store communicates with the channel adapters by polling each adapter in turn; channel adapter A, channel adapter B, and so on. The interconnection contains the following lines: II • Service Out (Remote/Local) - this is the channel service out tag. • Data Out (Remote/Local) - this is the channel data out tag. • Service In (Remote/Local) - this is the control unit service in tag. The communication path contains the following lines: • • A nine bit bi-directional data bus used to transfer orders and data between the status store and the channel adapter. A five bit bi-directional response used to transfer an address or response data to the channel adapter, or response data to the status store. • Two system clocks (C 1 and C2 • Local Control Unit Master -;- indicates this control unit is the current master control unit. • Two condition bits that define the current PLA condition. • An adapter select line to each adapter. • Remote Control Unit Master -;- indicates that the other control unit is the current master. • An adapter reset line to each adapter. Data In (Remote/Local) - this is the control unit data in tag. • Stop (Remote/Local) - this is the channel adapter signal used to inform the buffer that the data transfer has ended. • Data Valid (Remote/Local) - this line is used as a gate for data that is sent to the channel for parity checking. • Buffer Data Bus (Remote/Local) - this a 9-bit bi-directional data bus used to send and receive data from the buffer. • Suppress Out (Remote/Local) - this is the channel suppress out tag. l. • Local Control Unit Connected ~ the local control unit is enabled for a dual control unit mode of operation. • An adapter interrupt line from each adapter to the status store. • Remote Control Unit Connected -;- the remote control unit is enabled for a dual control unit mode of operation. • An adapter failure line from each adapter to the status store. Note: Local and remote control unit connected lines become inactive when the corresponding control unit is offline. Load Balancing in a Dual Control Unit Subsystem At varying times each drive attached to the subsystem is assigned to one of the two control units. All commands to a drive are executed by the assigned control unit and all buffered data to the drive is stored in that assigned control unit. Channel Adapter to Buffer (Local/Remote) Interconnection Channel Adapter to Status Store Interconnection The remainder of the status store to status store communication path control signals are: Channel adapter to local buffer OPER 140 • Local Control Unit Send ~ indicates that the microcode has assembled a message in the message buffer. Note: This signal is named 'received' at the receiving control unit. • Local Control Unit Acknowledge -;- this line is used to acknowledge the receiving of a message. This causes a reset of the 'send' signal at the other control unit. The pattern of channel attachment usage of each drive is also monitored. If the channel attachment in one control unit receives most of the host commands for some drives, the load balancing algorithms of the subsystem attempts to use the buffer in that control unit for those drives. When a drive is aSSigned to a control unit for use by the service representative, la drive is assigned to the control unit by plugging in the MOl reassignment of the drive is not permitted un~ the service representative releases the drive or unplugs the MD from the control unit. 3480.MI • CapojriIht 11M EC338395 c:.,. '114. Subsystem Configurations (Continued) '11' o ,') OPER 140 o o o o o o o o Subsystem Configurations (Continued) Dual Control Unit Command Sequence Subsystem Configurations (Continued) 11. The microprogram determines which control unit the drive is assigned to. Host Channel The host system issues a channel command to the subsystem. 2. The channel adapter waits to be polled by status store. 3. The channel adapter requests a device assignment and the device status byte from status store. 4. Status store requests Master status before it can begin order execution. 5. When Master status is granted, status store tests the device assignment, and if not assigned elsewhere, sets the channel adapter bit and responds with the device status byte from status store RAM. 6. 7. The channel adapter uses the device status byte to generate initial status and transfers this to the host system. The channel adapter stores the command, device condition byte, and interrupt request code in the channel adapter RAM, sets 'control unit busy', and through the channel adapter activates a request interrupt to the status store. Status store activates an interrupt level 6 to the microprogram, Local: Perform the command action as required - set up the buffer, start the drive. Remote: Send the command to the other control unit via status store. Wait for the remote control unit to finish the command. The remote control unit sends the ending status in a message when the command is complete. Local Status Store When the interrupt is detected by the microprogram, it examines the Channel Response Register (CRR) in status store to identify the reason for the interrupt and to find which channel adapter bits are set. 9. The microprogram reads the channel adapter RAM to find the interrupt reason and the command byte. 10. The microprogram resets the interrupt to free the channel adapter. The channel adapter resets the 'control unit busy' condition. Microprocessor Buffer Loc Rem Data Flow Drive Adapter Loc Adapter Drive 0 Loc Drive 7 Rem --------------- ---- - -Read Loc Preamp Rem Read Detect Loc Rem Figure 1, 3480 MI (I EC336395 CUJlVflntn IBM Cnrl) 1984. 1985 Remote Remote Local B I ~ I Status store • I Rd/Wrt Data Flow (Device Control Bus) J 11 • I L Read Data Flow (Read Data Bus) • Loc I I Buffer Rem Data Flow • I Loc Drive Adapter Rem L I J Status Store Microprocessor I • II Rem 8. Control Unit I Channel Adapter D 12. When the command has completed, the microprogram stores the ending status byte in the channel adapter RAM and directs the adapter to present the status to the host system. 13. If command chaining is not indicated, the channel adapter requests that the device be freed by passing a status store order on a polling operation. OPER 141 I Control Unit 0 Channel Adapter Status Store o Host Channel I An example of a typical dual control unit command sequence is: 1. o r Adapter Loc Drive 8 --------------- Drive F • Rem -Read - -Loc Preamp Rem L Read Detect Loc Rem Dual Control Unit Configuration Subsystem Configurations (Continued) OPER 141 Subsystem Configurations (Continued) Dual Control Updating Status Store 'RAM' At installation time the customer assigns the control units as and 1. During a normal dual control operation, control unit assumes control of the 'master/slave' logic. a a At every status store condition 3 cycle, control unit a deactivates the 'local master' line for one cycle to permit control unit 1 to reach the master condition if it needs to. The importance of being in the master condition is that the status store in each control unit can not execute any orders while in the 'slave' condition. If control unit 1 is in the 'slave' condition, a request for 'master' condition is generated by activating its 'local master' line. OPER 142 Subsystem Configurations (Continued) Part of the status store communication path between control units is the RAM address bus, RAM data bus, and a memory write signal line. When a memory write operation is performed, the RAM address bus contains the address of the status store RAM; the RAM data bus contains the data being written to the RAM, and the memory write signal is used to gate the data into the RAM. When either control unit is written into, the RAM in the other control unit is written into with the same data. The timing chart shows an example of a message being written into address 80 and 83, and the updating of the RAM status. Note: This is to remind you that each control units status store lines going to the other control unit are labeled local, and are labeled remote coming from the other control unit. The timing chart is shown at the control unit side. See OPER 1, Subsystem Configurations, "Status Store to Status Store Communication Path Diagram." Writing a Message into Address 80 and 83 Updating the RAM Status Byte Control unit 1 requests an initial microcode load (lML) from control unit 0 by writing a message into address 80 and 83. The first part of the timing chart shows that control unit 1 must activate its 'local master' line, assemble the data and address to be written, then activates its 'memory write' Elline to gate the information into address 80 and 83 of both RAMs. The second half of the timing chart shows control unit 1 updating the device status byte in address 1 B of the RAMs. Control unit 1 activates its 'local master' line, assembles the data and the address to be written into, then activates its 'memory write' line to gate the information into address 1B 1]. Because this is not a message, control unit 1 does not activate its 'send' line. D EJ 0 When both addresses have been written into, control unit 1 activates its 'send' line to indicate to control unit that a message has been written. No other action takes place until control unit 0 acknowledges the 'remote send' line. D a Note: The 'send' line is only active when a message has been sent to the RAMs. Updating the device status byte needs no 'send' line. a WRITING A MESSAGE INTO LOCATION II III 80 AND 83 UPDATING RAM STATUS BYTE Control Unit 0 (Loc Master) ll----' Control Unit l.Jr (Rem Master) I LI III ~--------------------------------~ Loc Send Ell Rem Send III I II I Loc Ack Rem Ack ~~____________________~B~n~__________________________ Memory Write Address Bit P ~. ~. ~_______ I__~n~____~n~___nJtr_l____~~ r---1L--I ___________________________________ __________________________ ~I ~n~ Bit _______ 111"1 ~ ______________________________________________________________________ ______ ____________ _________________________________________________________________________ _______________ _________________ ____________________________ Bit 0 &n~ ~n~ ~~ ~n~ Bit 2 Bit ---------------------------------------------------------------------------~~----______________________________________________ -----'n. . __---