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CONTROL DATA
CORPORATION
CONTROL DATA®
8092
Te IeProgrammer
PROGRAMMING REFERENCE
MANUAL
CONTROL DATA
CORPORATION
CONTROL DATA®
8092
TeleProgrammer
PROGRAMMING REFERENCE
MANUAL
Pub No. 368 107 01
RECORD OF REVISIONS
Rev.
Date
Notes
Reprint with revision.
Revised to reflect ECOs 1163, 1198,
1268, 1291, 1334, TITI, T354, 1401,
A
8/24/64
Chanqe 1 5/21/65
Change 2
1402. 1403. 1411, 1431, 1470, 1505,
and 1585.
(Revision packet)
Revised to reflect ECO DP2193.
(Revision packet)
8/25/66
5/15/67
Renrint (includes chrlnae 1 rlnd 2)
C
1967. CONTROL DATA CORPORATION
Print.d in the United States of America
CONTENTS
CHAPTER ONE-PROGRAMMING
General Characteristics
The Central Processor
Basic Concepts in Programming the TeleProgrammer
Instruction Word Format
8092 Instruction Repertoire
Description and Examples of Instructions
Load Instructions
LDN Load A (No Address Mode)
LDM Load A (Memory)
LD I
Load A {Indirect}
LCM Load Complement to A (Memory)
LC I
Load Complement to A (Indirect)
TTA Tag Register Contents to A
BER - Contents of BER Register to A
Store Instructions
STM - Store A (Memory)
ST I
Store A {Indirect}
ATT - A to Tag Register
ABR - A to B~ffer Entrance Register
ABX - A to Buffer Exit Register
Jump Instructions
ZJP
Jump, if Contents of A = 0
NZP Jump, if Contents of A :f 0
PJP
Jump, if Contents of A ~ 0
NJP
Jump ,if Contents of A < 0
UJP
Unconditional Jump
Shift Instructions
SHA Shift A Left One Bit
Arithmetic Instructions
AD N - Add (No Address)
ADM - Add (Memory Address)
AD I
Add (Indirect Address)
SBN - Subtract (No Address)
SBM - Subtract (Memory Address)
SB I
Subtract {Indirect Address}
RAM - Replace Add (Memory Address)
RAO - Replace Add One (Memory Address)
Logical Instructions
LP N - Logical Product (No Address)
LPM Logical Product (Memory Address)
LP I
Logical Product {Indirect Address}
LSN Logical Sum (No Address)
LSM Logical Sum (Memory Address)
LS I
Logi~al Sum {Indirect Address}
iv
1-1
1-2
1-3
1-6
1-9
1...,10
1-10
1-10
1-10
1-11
1-12
1-12
1-13
1-14
1-15
1-15
1-15
1-16
1-16
1-18
1-20
1-20
1-20
1-21
1-22
1-22
1-23
1-23
1-24
1-24
1-24
1-25
1-26
1-2.6
1-27
1-27
1-28
1-29
1-29
1-30
1-31
1-31
1-32
1-33
Input/O utput
INN
OUT IB I
IBO INA OTN -
Instructions
Input Normal
Output Normal
Initiate Buffer Input
Initiate Buffer Output
Input to A
Outout No Address
1-34
1-34
1-35
1-37
1-38
1-39
1-39
Control Instructions
External Function
EXF CIL
C lear Interrupt Lockout
CBC
Clear Buffer Controls
ERR
Error Stop
HLT
Halt
1-40
1-40
1-42
1-42
1-43
1-43
CHAPTER TWO = OPERATION
TeleProgrammer Operator's Console
Switches
Displays
Status Indicators
Starting the 8092 TeleProgrammer
Loading A Program or Data
Entering Data From the TeleProgrammer Console
Examining the Storage Contents
2-1
2-2
2-4
2-5
2-7
2-7
2-7
2-8
CHAPTER THREE
A BRIEF LOGICAL DESCRIPTION OF THE TELEPROGRAMMER
Input/Output Section
Program Step
Arithmetic Section
Storage Section
Control Section
3-1
3-2
3-3
3-5
3-7
GLOSSARY
APPENDIX
Appendix A - TOSAS - A TeleProgrammer Assembler
Appendix B - Programming Examples
Appendix C - Mathematical Tables
Change 1
v
A-1
B-1
C-1
8092 TeleProgrammer
VI
CHAPTER ONE
PROGRAMMING
GENERAL CHARACTERISTICS
The CONTROL
DATA~:<
8092 TeleProgrammer
IS
a highly flexible and
versatile stored program processor specially designed as a high speed
buffer memory system for use in a variety of data communication applications.
Among the more important features are the following:
stored program
parallel mode of operation
8-bit word length
2048 words of core storage - 4096 (optional)
1 Direct I/O Channel (8 bits)
1 Buffer I/O Channel (8 bits)
versatile instruction repertoire of 42 instructions
3 Auxiliary Tag registers of 4 bits each
indirect and direct addressing and modification
interrupts
12 bit external function address codes
7 internal program registers
physical size: height, 68 inches; width, 34 inches;
depth, 30 inches
storage reference cycle time of 4 microseconds
The ability to use the OSAS . or OSAS-A assembler
for those who have a 160 or 160-A computer.
~:<
Registered Trademark of Control Data Corporation
1-1
THE CENTRAL PROCESSOR
The TeleProgrammer is a parallel, single address electronic data
processor.
Operations are controlled by an internally stored program
located in sequential addresses.
seconds.
The storage cycle time is 4 mlcro-
The basic memory may be expanded from 2048 words to
4096 words.
Each internal core word contains 8 bits.
Instructions
are executed in one to four storage cycle times; with times varying
from 4 to 16 microseconds.
The average instruction time is approxi-
mately 10 microseconds.
The Block Diagram indicates the principal functional divisions
ARITHMETIC
t
-
CORE
STORAGE
I
CONTROL
i
1- 2
INPUT/OUTPUT
BASIC CONCEPTS IN PROGRAMMING THE TELEPROGRAMMER
The TeIeProgrammer has some Unique features for programming.
of these center around the word length of 8 bits.
addresses fur 4096
highest address
IS
words,
212 - 1).
12
Most
In order to carry
bits are required
(2 12
=
4096, where
To provide for 12 bits, the TeleProgram-
mer makes use of three 4-bit Tag registers (Tag registers 1, 2, and 3).
The carryover from 8 bits to 4 additional bits, in the Tag register,
causes a split in the second octal digit from the left.
This is indicated
below:
4-bit Tag reg.
3
8-bit word length
2
1
3
3
Split octal digit
In this manual, the 8,.;; bit word length will be represented as two full
octal digits and one quartic digit (the leftmost 2 bits).
The Tag registers
will be generally represented as shown above, with one full octal digit
(on the left) and a single bit (0 or 1) on the right.
( c:J
D)
The jagged
ends of the registers indicate the split octal digit.
1-3
Change 1
In addition, this manual will refer to numbers of "three octal digits" being
contained in the 8-bit word length.
Actually, this is physically impossible,
since three octal digits occupy 9 bits and there are only 8 bits in the
TeleProgrammer word.
However, what
IS
meant here, is that the
leftmost bit of the three digit octal number
IS
to be discarded.
For
example, show the octal number, 277, in a TeleProgrammer word.
Octal 277
=
a
10 111 111
In
binary
discard)
1
quartic digit
2 octal digits
This convention of representing the contents of the 8-bit words will be used
many times in this manual.
Looking at the above 9-bit configuration,
one can see that to discard the leftmost bit, it must be zero.
that the highest quartic digit of the word is 3.
This means
This, in turn, indicates
the maximum "octal" of three digits which can be expressed
In
the 8.. bit
word length; --it is 377.
IS
equivalent
to 256 registers.
The octal range 000 through 377
Since each Tag register holds 4 bits, there are 16
possible configurations for the 4 bits (0000 through 1111). Thus, 16 times
256
= 4096 total registers available.
1-4
WORD FORMAT
People who work with computers are generally acquainted with the term,
"octal".
It is the number base associated with three bits --which
turn, provides eight possible number states (zero through seven).
In
Since
the 8092 TeleProgrammer has an 8-bit word length and partitioning by
three bits over the complete word is inefficient; the number base of four
with partitioning by two bits is used for the
~
two bits of the word.
The number base of four, is referred to, in this manual, as QUARTIC.
Keep in mind, that only the
~
in Quartic.
bits are expressed by two octal digits.
The lower
upper QUAR TIC digit
Bits
00
01
10
'lii
IS
SIX
two bits of the word length is expressed
The
represented by bits, as shown below:
The Upper QUAR TIC Digit
o
1
2
3
The CONTROL DATA 8092 TeleProgrammer word contains 8 binary
digits.
These are shown below with the least significant bit (b o ) on the
right.
I
8 bits
b 4 b 3 1b 2
I b 7 I b 6 Ib 5 I I
Single Word
Binary Format
I
Ib 1 I bO I
Any binary digit above can be represented by any combinations of ones
or zeros. Although the 8092 operates in binary, it is more efficient to
consider the word format as containing 2 octal and 1 Quartic digits, as
shown below:
~I
8 bits
1-Z3
Single Word Format With
Two 0 ctals and 0 ne Quartic
Quartic Digit
(0,1,2, or '3)
1-5
c\
~
Octal Digit
(0 thru 7)
Octal Digit
(0 thru 7)
INSTRUCTION WORD FORMAT
The TeleProgrammer operates on a two word instructional set.
Most
instructions are contained in a set of two sequential storage locations.
The first word contains the Function Code, in the lower 2 octal digits,
and the Tag register designator, T, in the upper quartic digit.
The
second word of the instructional set holds: an operand of 2 octals and 1
quartic, or a partial address of 2 octals and 1 quartic.
Three modes
of operation are possible in the 8092; NO ADDRESS MODE, MEMORY
ADDRESS MODE, and INDIRECT ADDRESS MODE.
Tag register
Designator
~
shown below:
Examples are
Function Code ~
(2 octals)
I
NO ADDRESS MODE
Where T = 0, since there is no
Auxiliary Tag register used in
this mode.
The operand must
contain 3 digits in the octal range
of 000 thru 377.
T
F
2 Octal Digits
MEMORY ADDRESS MODE
Where T can equal 0, 1, 2, or 3.
The lower 8 bits of the operand
address appear in the second word
and the upper 4 bits of the operand
address appear in the Auxiliary Tag
register designated by T. If T=O,
the address of the operand is fully
contained in the second word of the
instructional set.
1-6
T
F
I
INDIRECT ADDRESS MODE
Where T can equal 0, 1, 2, or 3.
{
At one of the first 256 core locations,
T
F
given in the second word, is the
lower 8 bits of the operand address.
....-'------------------t\
The upper 4 bits of this operand
lOne of First 256 Core Addresse~
address· will be found in the Auxiliary
(Octal rang of th
dd
~
"
"d"
d b T
e
ese a resses
T ag reglster
10 lcate
y
.
is: 000 thru 377
I
Examples of the Three Operational Modes
Example 1.
NO ADDRESS MODE
Put the octal number, 277, into
the A register.
Octal
IFunction
Code
Tag
Solution:
{
Since no Auxiliary Tag register is
involved, T = o. The octal code
for "LOAD A" in this mode is 20;
thus F = 20. The octal operand,
277, is placed in the second set. as
2 octals (77), and 1 quartic (2).
I
0
I
2
!
!
2
7
I
0
7
Operand of 3 digits
(2 octals and 1 quartic)
Example 2.
Load the contents of octal address,
3771, into the A register.
MEMORY ADDRESS MODE
Solution:
The Tag, 2, indicates Auxiliary
Tag register 2 holds the upper
2 quartic digits of the address
whose l()wer 8 bits are given in
the second instruction word. Note,
octal 3771 is contained in the
designated Tag register and the
second word of the instruction
set.
I
I
~
Octal
".r-T..:...::a::i!g:....--rF:.....::u::.:n=c~ti:.:;o.:.:n:....:C=o-=d:.=:je
I
2
i
2
!
\
3
!
1~~3
~ Full
7
12 Bit Address
I
1
I
4
Note:
The quartic and 1 bit fit
together to form octal, 7, the
second digit of the address.
1-7
1
Tag reg. 2
Example 3.
Load the operand whose complete
address is in address 0126 and
Tag reg. 1.
INDIRECT ADDRESS MODE
Solution:
{
Octal 126 is the address given
in the second word. At this
address, 0126 ,the lower 8 bits
of the location of the operand are
placed. The upper 4 bits of the
operand location are placed in
Auxiliary Tag register, 1, indicated by the Tag designator of
the first word. Continuing this
example, assume address 0126
and Tag register 1 contain the
quantities shown below, show
what finally is loaded into A.
Tag
I 1
I
I
Octal
Function Code
2
i
2
I
digits
1 quartic digit
Assume Tag register 1
1
contai7
Assume address, 0126. conta~
Octal
. }~~
Address
___
Formed
Assume address 2546
contains: --;
r--O~-r~7'-ii~6:-1~L-------------~th~ls
IS
loaded
into A
~
o :
7
8 bits
1-8
!
6
~I
THE 8092 TELEPROGRAMMER
INSTRUCTION REPERTOIRE
Cycle
Rei. Octal Time
Code Code
Functions
*
...
Functions
A RITHMETICS :
LOADS:
Load A (No. )
Load A (Mem. )
Load A (Ind. )
Load Comp. (Mem. }
Load Comp. Und. )
Tag Reg. to A
Clear A
BER to A
LDN
LDM
LDI
LCM
LCI
TTA
CLA
BER
20
21
22
25
26
03
03***
06
Add (No. Adr.)
Add (Mem.)
Add (Ind.)
Subtract ( No. )
Subtract (Mem.)
Subtract Hnd.)
Replace Add (Mem. )
Replace Add 1
2
3
4
3
4
1
1
1
STORES:
Store A (Mem. )
Store A (Ind. )
A to ·Tag Reg.
A to BER
A to BXR
JUMPS:
Cycle
Rei. Octal Time
.,.
Code Code
STM
STI
ATT
ABR
ABX
41
42
02
04
05
3
4
1
1/2
1/2
2
3
4
2
3
4
4
4
Log.
Log.
Log.
Log.
Log.
Log.
LPN
Prod. (No. )
Prod. (Mem. ) LPM
LPI
Prod. (Ind. )
Sum (No. )
LSN
Sum (Mem. )
LSM
Sum (Ind. )
LSI
10
2
3
4
2
3
4
11
12
14
15
16
IN-OUT:
ZJP
NZP
PJP
NJP
UJP
DON
60
61
62
63
64
02***
2
2
2
2
2
1
Input Normal
Output Normal
Input Buffer
Output Buffer
Input to A
Output No. Adr.
INN
OUT
IBI
IBO
INA
OTN
12
13
10
11
16
14
EXF
CIL
CBC
ERR
HLT
15
13
01
00
11
..........
.,..,.
......
.,..,.
1/2
1/2
2
2
QQ~TROL.fi;
Sl:IIFIS;
A Left 1 bit
30
31
32
34
35
36
51
55
LOGICALS:
****
H A = 0
H A f 0
H A ~ 0
H A < 0
Unconditional
Do Nothing
ADN
ADM
ADI
SBN
SBM
SBI
RA.M
RAO
SHA 01
1
Ext. Function
Clear Interrupt
Clear Buffer
Error Stop
Halt
* Cycle Times; each cycle = 4 microseconds.
** 3 + 2 (X = 1) + terminate time. Where X = No.
*** -No tag should be referenced.
**** Jump cycle time is 1 cycle, if jump is not made.
1-9
of words.
Change 1
3
1
1
-
1
DESCRIPTION AND EXAMPLES OF INSTRUCTIONS
LO AD Instructions
Seven LOAD instruction are available.
LDN
LDM
LDI
LCM
LCI
TTA
BER
These are:
LOAD A (No Address Mode)
LOAD A (Memory Address Mode)
LOAD A (Indirect Address Mode)
LOAD Complement to A (Memory Address Mode)
LO AD Complement to A (Indirect Address Mode)
Tag Register Contents to A .
Contents of B ER Register to A
LDN - (20) - LOAD A (No Address) 2 Cycles
Load the A register' with the contents of the second word of the instructional
set.
Octal numbers 000 through 377 can be entered into A by this instruction.
Example:
{i
I
Put the octal number, 177, into A
T
LDN
0
2
1
i
y7
8 bit
A register
0
~
i
7
LDM - (21) - LOAD A (Memory) 3 Cycles
Load the A register with the. contents of the memory address whose lower
eight bits are given in the second instruction word and whose upper four bits
are contained in the designated Auxiliary Tag register.
Example: Assume memory address 3573 (in octal) contains the octal
quantity, 033. Load this into. A •
1-10
o
A register
3
3
Memory Address =l...-...;0:::...---L_...::3'---'----'3~__'
LDI -
(22) - LOAD A {Indirect} 4 Cycles
Load A with the contents of the address whose lower 8 bits are contained in
one of the first 256 (decimal) addresses, and whose upper 4 bits are contained
In
a designated Auxiliary Tag register.
The location in the core (one
of the first 256 decimal addresses) is given in the second instruction word.
The Auxiliary Tag register is indicated in the first word.
Example: Assume octal address, 3646, contains the octal number, 277.
Load this number to A, using the indirect mode via octal address 0216.
LDI
2
2 bit
~uartic
2
10
Address 0 2· 1 6 contains
Tag
register
2
Address 3 6 4 6
A register
7
'----=2:..-...J---:._"'--_7=-----' --~~I'----=2=----11_7"'----'-1_7"----'
1-11
LCM -
(25) - Load Complement to A (Memory) 3 Cycles
Load the A register with the complement of the contents of the memory
address whose lower 8 bits are given in the second instruction word and
whose upper 4 bits are contained in the designated Auxiliary Tag register.
Example: Assume memory address 2077 (in octal) contains the octal
quantity, 125.
Load the complement of this quantity into A.
2
complement
207 7
Memory Address
r
__r-:-~~:-~r-I-_______
Of
1
2
.5
J ~25
is 252
(Note:
quartic complements are "three's complement".
Thus, the complement of the quartic digit, 1, above is 2; whereas, the complements of the
octal digits 2 and 5 are respectively 5 and 2.)
LCI -
(26) - Load Complement to A (Indirect) 4 Cycles
Load A with the complement of the contents of the address whose lower
8 bits are contained in one of the first 256 (decimal) addresses and whose
upper 4 bits are contained in the designated Auxiliary Tag register.
The
location in the core (one of the first 256 decimal addresses) is given in the
second instruction word.
The Auxiliary Tag register is indicated in the first
word.
1-12
Example: Assume octal address 3467 contains the octal number, 053. Load
the complement of this number into A, using the indirect mode and via octal
location 0023.
ister
2
!
4
3
7
Address 0 0 2 3
~f o_...i._r6_~~_~
L
__
~§
6 7
complement
L-O~-'-""":5~...L--=3!...-rl--_O_f ~
.....
)3
324
Note: The 1 bit of Tag register 3 and the quartic digit at address 023, form
the bits, 100, which gives the octal digit, 4. Also note the complement of the
quartic digit, 0, at address 3467 is equal to 3; whereas the complements of the
octal digits 5 and 3 are respectively equal to 2 and 4
TTA -
(03) - Tag Register
eo
A
1 Cycle
Load the contents of the designated Auxiliary Tag register into the A register.
Pack zero's in upper 4 bits.
Example:
Load contents of Tag register, 2, into A.
o
TTA
3
" Three bits
Note:
The four bits of the Tag register are: 0110.
00 000 110 = 006.
When packed to the right
of A, they give the following:
CLA -
(03) - Clear A
1 Cycle
This instruction is the same as the preceding instruction (TTA) except that the
TAG is not referenced. The A register is therefore cleared (all zeros).
1-13
Change 1
BER -
(06) - Buffer Entrance Register to A
1 Cycle
Load the A register with the lower 8 bits of the Buffer Entrance register.
Example:
Load Buffer Entrance register into A
BER Code
b! (;
o
Upper quartic digit
'-
"'1<=-----8
bits---~~I
~1~-1-0--rl--11--~1-0~0~~1-1-0-'1
Buffer Entrance Register (10 bits)
(Shown in bi~fONnat)
Note:
0 n this instruction, the lower 8 bits (1 quartic and 2 octals) are trans-
ferred into the A register.
The upper 2 bits (1 quartic digit) are not transferred.
On the reverse transfer (A to BER), the right 2 bits of Tag register 3 are
sent to the upper 2 bit locations of B ER •
ABR instruction.
Change 1
1-14
This is explained in detail in the
S TO R E Instructions
Five S TO R E instructions are available; these are:
STM
STI
ATT
ABR
ABX
STM -
STORE A (Memory Address Mode)
STORE A (Indirect Address Mode)
A to Tag Register
A to Buffer Entrance Register
A to Buffer Exit Register
(41) - STORE A
(Memory Mode) 3 Cycles
Store the contents of the A register into the location
whose address is eqUlva-
lent to the combined contents of the designated Tag register and the second
word of the instruction set.
Example:
Assume A
at octal address, 2356.
contains the octal number, 155.
Address 2 3 5 6
STI -
(42) - STORE A
1
Store this number
5
(Indirect Mode) 4 Cycles
Store the contents of the A register into the location whose address is equivalent to the combined contents of the designated Tag register and the contents
of one of the first 256 decimal cOre registers.
The exact location of one of
these 256 registers is given, through its address, in the second instruction
word.
1-15
Example: Assume the A register contains the octal number, 037. Storethis
number in octal address, J 777, by using octal location 0102, and the indirect
mode.
l'!'~I}
_
C
I
::C
____
-----------------
~a~reg. 1
J~
Address 1 02 contains
1
1 1
3
o
Address 3 7 7 7
ATT -
(02) - A to Tag. Register 1 Cycle
Transfer the lower 4 bits of the A register into the designated Auxiliary Tag
register.
Example: Assume the A register contains the octal number, 073. Store the A
register at Auxiliary Tag register, 3.
ATT
! 0 I 2
o ! 7 ! 3
3
Tag reg. 3
Three Bits
101
}
Last 4 bits
ILj-*-~:_~J.-Jl+oo:---------::.J0ll
One bit
DON -
(02) - Do Nothing
1 Cycle
This ins'tl"Uction is the same as the preceding instruction (A TT ), except that the
tag is not referenced. This instruction has no operation. Control goes to the
next instruction set.
ABR -
(04) - A to Buffer Entrance Register
1 Cycle, 2 Cycles if jump is
made.
Transfer the contents of A to the lower 8 .bit positions of the Buffer Entrance
register. The rightmost 2 bits of Tag register 3 become the 9th and 10th bits
Change 1
1-16
of the ~uffer Entrance Register (B ER); the upper two bits of Tag register 3
are referenced for bits 11 and 12 of BER.
If the buffer is busy, a jump
occurs to the combined address contained in the second word of the instruction
set and the designated Tag register.
If the buffer is not busy, control goes
to the next instructional set.
Example:
Assume one wants to effectively enter a starting octal address of
Shown are the program steps involved.
2534 into the Buffer Entrance register.
To effectively enter a starting address, ·2534 into BER
Tag
I
0
ILoad A Coda
0 I
2
I
0
Tar
I
i
5
0
-
IStore A Codel
·0
2
I
i
I
8 bit
A register
o
Load octal
number,S,
into A
5
. A register
Store A at
T~ reg .. 3
Q_
i 01
Tag reg. 3
4 bits
I
Tag
I 0
1
ILoad A Codel
i
2
!
3
0
I
4
Load octal
number, 134
into A
8 bit
IA to B ER Code
o
If Buffer is busy,
jump goes to address
4
35 7 5
bits----~
1-17
Buffer
Entrance reg.
Shown in 10 bits
Since BER is a 10-bitregister, there is not room for the full 12-bit address.
The upper 2 bits (1 quartic) are obtained by referencing the left 2 bits of Tag
register 3. In the above example ,the left 2 bits of Tag register 3 and the leftmost bit of BE R give the octal digit, 2.
A B X - {05} - A to Buffer Exit Register 1 cycle, 2 cycles if jump
IS
made.
Transfer the contents of Ato the lower 8 bits of the Buffer Exit register (BXR).
The right quartic digit (2 bits) of Tag register 3 fills the 2 upper bits of BXR.
The instruction is used to store the terminating address for buffer transfers.
The
left quartic digit of Tag register 3 is referenced by the TeleProgrammer to determine the highest order 2 bits of the address.
F or a Buffer Input instruction,
enter the LWA + 1, and for a Buffer Output instruction, enter the LWA + 2.
H the buffer is busy a jump occurs to the combined address contained in the designated Tag register of the first word and the contents of the second word of the
instruction set.
H not busy, control continues to the next instruction set in sequence.
NOTE: The above concept may be clearer, if it is remembered that 12 bits,
rather than 8 bits, are required to cQver the whole possible address range of
4096 registers. As a consequence, it must be possible to perform buffer operations covering the complete address ra.nge.
To accomplish this, the BER or
BXR (of 10 bits) uses the 8 bits of the instruction operand, 2 bits from TAG
register 3 (the lowest order 2 bits).
By referencing the highest order 2 bits of
Tag register 3, _ the full 12 bits are available.
The use of a
words.
The
highest order
during buffer
Change 1
10 bit BER and ·8XR allows a maximum buffer operation of 20008
first word address and last word address must be identical in the
2 bits.
The highest order 2 bits of Tag 3 must not be altered
operations.
1-18
Example: S how a program which places octal address, 3520 into BXR;
if the buffer is busy, wait until it is not busy.
Location of
Instruction
Instructions
Explanation of Action which Occurs
3420
3421
020}
007
Load A with the octal
number, 007.
3422
302
S tore lower 4 bits of
A at Tag register, 3.
3423
3424
020}
120
Bits, 0111, go
to Tag reg. 3
Load A with the octal
number, 120.
A goes to bits 1 thru 8 of BXR, right
quartic 1.3) of Tag reg. 3 goes to bits
9 and 10 of BXR." ... Left quartic digit
of Tag reg. 3 is referenced for upper
2 bits of address.
reg. 3 (in bits)
If buffer is busy, jump
goes to combined
address of designated
Tag. reg. and contents
of second word.
In this
example, jump goes to
3425.
Upper quartic is
referenced for
leftmost part of
address. . This
combined with
leftmost bit of
BXR gives octal
digit, 3.
1-19
reg.
BXR (10
JUMP INSTRUCTION
Five JUMP instructions are available, they are:
ZJP
NZP
PJP
NJP
UJP
JUMP, if contents of A=O
JUMP, if contents of Ai'O
JUMP, if contents of ~~ 0 (positive)
JUMP, if contents of A < 0 (negative)
Unconditional JUMP
ZJP -
(60) - Zero JUMP
2 Cycles if jump is made; otherwise, 1.
If the contents of A equals zero, jump to the combined address contained
the designated Tag register and the second word of the instruction set.
the contents of A are not zero, continue
In
In
If
sequence with next set of
instructions.
Example:
Test A for zero, and Jump
otherwise continue.
to
octal address, 6254, if A
ZJP
0
6
:
If A = 0
Jump to
1
Address
~
If A i' 0,
continue in sequence
NZP -
(61) - Not Zero JUMP
5
2
:
2 Cycles if jump
:l
)
: 74
I}:
zero;
ZJP
~::ruction
I
; } Next
I
IS
IS
Instruction
Set
made; otherwise, 1.
If contents of A are not zero, jump to the combined address contained in the
designated Tag register and the second word of the instruction set.
If the
contents of A are zero, continue in sequence with the next set of instructions.
1-20
Example:
Test A, and if not zero, Jump to octal address, 0222.
continue in sequence.
see
If A
If A
~r-...:iL0--'---6--'---1-----'1} N ZP
f= 0, jump to
address
=
If zero,
Instruction
0 2 :::2=-2_---------l:--=2--'--=2--'---=2-----11
--C
I}
0, con~t~in~u::e:::--------~
=====================1
in sequenc e
Set
Next
Instruction
Set
Note:
Since the complete jump address can be expressed in 8 bits, no Tag
register is required.
Thus, the Tag designation = 0, in the first instruction
word.
PJP -
(62) - Positive JUMP
2 Cycles if jump is made;' 'otherwis~, 1.
If the contents of A are positive (equal or greater than zero), jump to the
combined address contained in the designated Tag register and the second
word of the instruction set.
sequence. (If leftmost bit
If the contents of A are not positive, continue
0, contents of A are positive.)
Example:
Test A, and if positive, jump to octal address 4715.
continue in sequence.'
6
If A is positive
jump to octal
address
In
Otherwise,
2
47 15
I}
If A is not positive,
_ _ _~~
continue in sequence/"
.------.-----.-----.1
with next set of
~----'----........----'
instructions
1-21
Next
Instruction
Set
NJP -
(63) - Negative JUMP
2 Cycles if jump is made; otherwise, 1.
If the contents of A are negative, jump to the combined address contained in
the designated Tag register and the second word of the instruction set.
If
the contents of A are not negative, continue in sequence with the next set of
instructions.
Example:
Test A, and if negative, jump to octal address, 0012.
negative, continue in sequence.
If A is negative jump to
address 0012
0
6
3
I}
I}
~
_______--------~C=OZ~~C~~1~~~~~2~~1
If A is not negative,
continue in sequence----_ _
»
:=================1
Since significant portion of the address can be contained
In
If not
NJP
Instruction
Set
Next
Instruction
Set
B bits, no Tag
register is required and thus Tag designation of first instruction word is zero.
UJP -
(64) - Unconditional JUMP
2 Cycles
Jump to the combined address contained in the designated Tag register and
the second word of the instruction set.
Example:
Jump to address, 1323.
r
Jump to address 1
Change 1
3 2 3 4-----~
1-22
SHIFT INSTRUCTION
One shift instruction is available:
SHA = SHIFT A LEFT ONE BIT
SHA -
(01) - Shift A Left 1
1 Cycle
Shift the contents of A left--end around--l bit position.
left end of the A register
Bits coming off the
enter the lowest bit position on the right end of the
register.
Example:
Assume A contains the octal number 023.
of A by 2, using the shift instruction.
Multiply the contents
A register
Tag
Q
Shift Code
a I 1
Tag register
designation IS
zero on shifts
Q
2
1 J
0
4
6
I before
I after
shift
shift
Note: One shift instruction is required to shift A one place (1 bit) to the left.
Each left shift is equivalent to one multiplication by 2.
To shift 5 bits left, it
is necessary to give 5 shift instructions, or loop through the single shift
instruction 5 times.
1-23
ARITHMETIC INSTRUCTIONS
There are eight Arithmetic instructions:
two replace adds.
three adds, three subtracts, and
These are:
AD 0 (No Address)
ADD (Memory Address)
ADD (Indirect Address)
ADN
ADM
ADI
SBM
SBM
SBI
SUBTRACT (No Address)
SUBTRACT (Memory Address)
SUBTRACT (Indirect Address)
RAM
RAO
R.EPLACE ADD (Memory Address)
REPLACE ADD ONE (Memory Address)
ADN -
(30) - ADD (No Address) 2 Cycles
Add to the A register the 8 bit number given in the second word of the
struction set.
In-
The sum is left in A.
Example: Assume A contains the octal number, 122.
211, to A.
Add the octal number,
Initial Contents
of A
122
Tag
Instruction
Set
{
'
0
Add Code
3!
0
~I-=2~~~1~~1~~r-
/-
....
2
3
Add
1
3
Final Contents
of A
3
ADM -
3
(31)- ADD (Memory Address) 3 Cycles
.. Add to A the contents of the combined address given
register and the second word of the instruction set.
1-24
In
the designated Tag
Example:
Assume A contains the octal, 011.
Add the contents of address
(Assume contents of address 1523 are 111.)
1523 to A.
Add Code
1
3
~I
1 5 2 3
1
0
Initial A
! 1 :
1
1
1
1
,.
C;;
2
1
2
2
1
Final Contents of A
(32) - ADD (Indirect Address) 4 Cycles
ADI -
Add to A the contents of the combined address contained
In
the designated
Tag register and one of the first 256 decimal locations indicated in the second
word of the instruction set.
Example:
Assume A contains octal number, 110. Assume octal address,
4413 contains 302. Add the contents of address 4413 to A, by using the
indirect mode and octal address, 0222.
I
{
.
Tag reg.
I
4
r-I
Tag
1
Add Code
3!
2
Initial A Contents
1
1
; 0
I
-2-..----2-,----::-2---,~
!
3
0
o
o
1 II-
1
1
2
3 (see note)
3
Final A
1
1
"'--
~----
Address
4 4 1 3
3
2
Note:
The addition of 1 and 3 in the rightmost quartic digits overflows the
register and the carryover (1) is added to the rightmost digit.
1-25
SBN -
(34) - SUBTRACT (No Address) 2 Cycles
Subtract from the A register, the number contained in the second word of
the instruction set.
Example:
Instruction
Set
SBM -
The difference is left in A register.
Assume A contains 003.
f
.I
Tag
0
Subtract 001.
0
Subt l Codel
3 1 4 I
Q
0
1
~o
~tract
0
Initial
0
0
0
Final A
(35) - SUBTRACT (Memory Address) 3 Cycles
Subtract from the contents of A, the contents of the combined address contained in the designated Tag register and the second word of the instruction
set.
Example:
tains 233.
Assume A contains the octal, 113. Assume address, 7622 conSubtract the contents of address 7622 from A.
Subt. Code
3
5
1
2
reg. 2
1
3
3
subtract
)
Address
Initial A
i
1 1
3
7 6 2 2
=
2
2
Final
3
3
1-26
7
A
SBI -
(36) - SUBTRACT {Indirect Address} 4 Cycles
Subtract from the contents of A, the contents of the combined address contained
in the designated Tag register and the location of one of the first 256 decimal
registers, indicated by the second word of the instruction set.
Example: Assume A contains the octal, 333. Assume address 3502 contains
the octal number, 123. Reduce A by the contents of address 3502, using
indirect mode and octal address, 0002.
J
5!
Instruction
Set
0
3
2
Address 0002
=
1
!
~_1 ~
__
1
Initial A
! 3 !
2
3
3
2
s~aclL-~2~~F~i~n~al~A~-0~--
__2__' -__3__
Address 3 5 02
RAM -
(51) - REPLACE ADD (Memory Addtess) 4 Cycles
Add the contents of the A register to the contents of the memory' address
formed by the contents of the designated Tag register and the second word of
the instruction set.
The sum thus formeQ, remains in A, and replaces the
initial contents of the memory address.
1-27
Example: Assume A contains the octal number, 200. Assume address 1000
contains the octal number, 233. Increase the contents of address 1000 by the
contents of A.
}
Ttre
I ~ I
0
1~.
i
Initial A
! 0 i
3
\
0
3
0
Address
Memory
1 0 0 0
Initial Contents
2
3
3
Address
Memory
1 00 0
Final Contents
0
3
4
~
RAO -
Ad(
Set
o
g•
Instruction
2
2
(55) - REPLACE ADD ONE
4 Cycles
Add 1 to the contents of the memory address indicated by the combined contents of the designated Tag register and the second word of the instruction
set.
This sum is performed in A and remains in A at the end of the instruction.
Example:
Add 1 to the contents of memory address, 0200.
Instruction
.Set
Tag
0
f
I
2
I Add
: 5
1 Code
! 5 I
/
~
3
goes to
A
0
A reg.
1
1
i
3
(
Add 1
3
Address 0200 =
(Initial contents)
3
1
Address 0200 =
(Final contents)
3
1
4
1-28
1
Final A
4
LOGICAL INSTRUCTIONS
There are six Logical instructions:
three are Logical sums.
three of which are Logical products;
These are:
LPN
LPM
LPI
LOGICAL PRODUCT (No Address)
LOGICAL PRODUCT (Memory Address)
LOGICAL PRODUCT (Indirect Address)
LSN
LSM
LSI
LOGICAL SUM (No Address)
LOGICAL SUM (Memory Address)
LOGICAL SUM (Indirect Address)
Logical Product is defined as a "bit by bit" multiply which observes the
following rules:
1
0
0
1
times o
times o
times 1
times 1
0
0
0
1
Logical Sum is a "bit by bit" sum without "carries" which observe the
following rules:
LPN
1 + 0
0+1
1
1
0+0
1 + 1
0
0
(10) - LOGICAL PRODUCT (No Address) 2 Cycles
Form in A the Logical Product of the contents of A and the contents of the
second word of the instruction set.
1-29
Change 1
Example:
Test A for "even".
I Tag
Instruction
Set
Zero
Jump
l
LPM -
{
ILog.Pr.Code
.
0
ill
0
I
0
0
1
{I
If even, Jump to octal address, 0100.
Initial A
I
where d
The Logical Product,
using 001, will give a
zero in A, if A is
initially even.
ZJP
6
octal digit
=
! a
0
~____.-____~____~
I 1
0
a
0
where X
X
If A = 0, jump to
address, 0100.
Final A
0
:
;
0, if initial A
1, if initial A
X
IS ~.
IS
odd.
(11) - LOGICAL PRODUCT (Memory Address) 3 Cycles
Form in A, the Logical Product of the contents of A and the contents of the
memory location whose address is the combined contents of the designated
Tag register, and the second word of the instruction set.
The initial contents
of the memory location remains unchanged.
Example: Assume A contains the octal, 222. Assume memory address,
5211, contains 033.
Form the Logical Product in A.
Tag Log.Pr.Code
3
1
1
2
Log. Product
o
Final A
o
Memory Address 5 2 1 1
1-30
3
3
LPI -
(12) - LOGICAL PRODUCT (Indirect Address) 4 Cycles
Form in A the Logical Product of the contents of A and the contents of the
memory location whose address
IS
the combined contents of the designated
Tag register and the contents of one of the first 256 decimal locations.
The
address of this decimal location is given in the second word of the instruction
set.
The initial contents of the memory location remain unchanged.
Example:
Use the indirect mode to form the Logical Product of A and
memory location 3700. Use octal location, 0030 in the process. Assume
initial contents of A and location 3700 are respectively: 133 and 012.
Tag
2
{
Address
A
Log.Pr.Code
I
0030
1
2
3
o
3
Logical
Product
3
700
=
~~0~~~1--~~2~~~
2
fFiaiI -A
LSN -
(14) - LOGICAL SUM (No Address) 2 Cycles
Form in A the Logical Sum of the contents of A and the second word of the
instruction set.
1-31
Example:
Assume A contains octal number, 002.
Tag
{
I a
Ii Log.Sum
Code
1
! 4 I
o
Initial A
LL09~
Add
Note:
The bit-by-bit Logical Add
of the above example is:
002 = 00 000 010
001 = 00 000 001
Logical Sum = 00 000 all
003
LSM -
Set A to 003.
a I a i
a
2
1 (see note)
)
0
a
a
3
Final A
(15) - LOGICAL SUM (Memory Address) 3 Cycles
Form in A the Logical Sum of the contents of A and the contents of the
memory location whose combined address is given in the designated Tag
register and the second word of the instruction set.
Example: Assume A contains octal number, 111. Form in A the Logical
Sum of the contents of A and the contents of memory location, 6112. Assume
this location contains 333.
Sum Code
1
5
/
1
3
Initial A
1
3
!
Note:
6 1 12
3
3S
1
3 (see note)
{
Log. Sum
Memory
Address
!
2
Final A
2
:
!
2
The Logical Sum performed above, is shown below In bit form.
111,
333,
Logical Sum
01 001 001
11 all all
10 010 010
1-32
222
LSI -
(16) - LOGICAL SUM (Indirect Address) 4 Cycles
Form in A the Logical Sum of the contents of A and the contents of the
memory location whose address is the combined contents of the designated
Tag register and one of the first 256 (decimal) locations.
The location of
one of these 256 locations is given in the second word of the instruction set.
Example: Assume A contains 010. Assume memory location, 1510, contains
301. Using the indirect mode, and location 0300, form in A the Logical Sum
of the contents of A and the contents of address 1510.
ILog.8um
COd~
1
6
I
:
I
!
0
0
I
o
Initial A
! 1 !
0
3
0
1
------~~----------
\
0300
3
Memory
Location
1 5 1 0
1
3
1-33
Fir:fU A
ill
INPUT-OUTPUT INSTRUCTIONS
There are six instructions directly related to input-output functions.
These
are:
INN
OUT IBI
IBO
INA
OTN -
INPUT NORMAL
OUTPUT NORMAL
INITIATE BUFFER INPUT
INITIATE BUFFER OUTPUT
INPUT TO A
OUTPUT NO ADDRESS
(72) - INPUT NORMAL
INN -
(see p. 9 for timing)
Input a number of words to memory starting at the memory address contained
in the designated Tag register and the second word of the instruction.
The
ending address plus 1, is contained in a third word immediately following the
second word.
Thus, this instruction set is composed of three words.
(The
Tag register designation indicated in the first word is automatically assigned
as the Tag register designation for the ending address plus 1, in the third
word. )
Example:
Input 80 words to memory starting at octal address, 6577.
I
1
6
7
7
I
Instruction
~ -iL....--=3--'--O:l--'--7:..--..11 ~S
et
Ending Address Plus 1
Starting Address
Difference =
120 in octal = 80 decimal
6717
6577
120
Input
Memory Locations
;
!
16577
6600
6601
I
6716
1-34
OUT -
(73) - OUTPUT NORMAL
Output a number of words from memory starting at the memory address contained
in the designated Tag register and the second word of the instruction set.
The ending address plus 1, is contained in a third word immediately following.
Thus, this instruction set is composed of three words.
(The Tag register
designation, indicated in the first word is automatically assigned as the Tag
register designation for the ending address plus 1, in the third word.)
Example: Output 300 (decimal) words from memory, starting at octal
address, 1200.
Tag reg. 3
~-----t
-4
3
Tag IOutput Code
3
7
3
2
0
0
3
7
7
First 127 (decimal) words
puted from octal addresses
Ending Address Plus 1
Starting Address
Number of Words
(see note)
Tag ILoad
o ! 2
o !
Tag
3
Tag reg. 3
IA
i
0
to
0
ACOd~'
0 I
!
!
3
I
TaS r,}
I
2
.
Load A with 003.
Change Tag register, 3, by storing
A at Tag register 3. Tag register 3
now contains 0011 (in bits).
Tag IOutput Code
~I
4-4
0
0
0
----?
2
5
5
6
are outshown:
1377
1200
177 = 127 10
J
!
1
!
J
I
Next 173 (decimal) words are outputed
from octal addresses shown:
Ending Address Plus 1 = 1655
Starting Address
= 1400
Number of Words
255
173 10
127 + 173
1-35
=
total 300 words
NOTE:
The "ending address plus 1" of 1377 above, resulted in a "gap"--that is, no
output came from this register.
The reason is that quartic address, 1377,
falls at a "boundary address" as far as the addressing logic of the TeleProgrammer is concerned.
"Boundary addresses" are those, which when
incremented by 1, cause a change to occur in anyone of the 4 leftmost
address bits.
above) .
This in turn, requires a change in the Tag register (as
There are 16 such "boundary addresses" in the whole 4096 regis-
This condition is not serious due to the following alternatives:
ters.
(a)
If output follows input or vice versa such "gaps" would
have existed in the identical places anyway, and thus are
of no consequence.
(b)
If one wishes, he can fill the gap location by loading one
word into A and storing at the gap address.
(c)
By effective memory allocation, boundary addresses can
often be entirely avoided.
(d)
Buffered operations do not have this situation.
The previous example was given to indicate that a change
changes any
~
In
address which
of the 4 leftmost bits of the 12-bit address, requires a corre-
sponding change in the contents of the Tag register.
It should be apparent,
that the maximum transfer without changing the Tag register is 256 (decimal
words.
1-36
IBI - (70) - INITIATE BUFFER INPUT
1 cycle, 2 cycles if jump is made.
Before using this instruction, the starting address of the buffer transfer is
sent to BER, and the ending address plus 1 is sent to BXR (see these
instructions) .
If the buffer channel is not
This instruction initiates the input buffer cycle.
busy, control goes to the next instruction following the second word of the
instruction set.
If the buffer channel is busy, a jump occurs to the memory
location whose combined address is contained
In
the designated Tag register
and the second word of the instruction set.
Example:
Initiate buffer input, and if busy wait until not busy. Assume the
instruction is given at the location whose octal address is, 1203.
at address, 1203
at next address, 1204
If Buffer
IS
busy,jump goes to
1 2 0 3 (waiting)
If Buffer
IS
not busy, control goes to _ _ _ _ _ _.....
})
'-----'----'---......&1
Next Instruction Set
~======:============~I.
in Sequence
1-37
Change 1
IBO -
(71) - INITIATE BUFFER OUTPUT 1 cycle, 2 cycles if jump is made.
Before using this instruction, the starting address of the buffer transfer must
be sent to BER, and the ending address plus 1 must be sent to BXR (see
these instructions).
This instruction initiates the output buffer cycle.
If the buffer channel is busy,
a jump occurs to the combined memory address given in the designated Tag
register and the second word of the instruction set.
If the buffer channel is
not busy, control goes to the next sequential instruction following the instruction
set.
Example:
Initiate buffer output and if busy jump to octal address 0010.
T
Instruction
Set
{
ag
~
@:U ·
II B u.f 0 u t C
0
d
e
Tag reg. not required here,
since jump is to octal address,
0010 "f b ff
. b
I
U
ens
usy.
Next set of instructions in
sequence if buffer is not
busy. Control goes here
after buffer output is started.
Change 1
1-38
INA -
(76) - INPUT TO A
This instruction inputs one word from a previously selected input device to
the A register.
Example: Assume a previous instruction (see EXF) has selected the paper
tape reader for input. Input one frame (one word) to A.
Tag IINA Code
!
o
7
i
Note:
This is a single word
instruction, and the Tag register
designation IS always zero.
6
OTN - (74) - OUTPUT NO ADDRESS
This instruction outputs one word.
This word
IS
the second word of the
instruction set.
Example: Assume a previous instruction has selected the Printer.
the number 0102.
Instruction
Set
{
I
Tag
0
IOutput Code
7
i 4
Note: The Tag register
designation is always zero
in this instruction.
I
LL-.I---=.0_,,--=-2---'
CONTROL INSTRUCTIONS
Five Control 'instructions are available:
EXF
CIL
CBC
ERR
HLT
Output
EXTERNAL FUNCTION
CLEAR INTERRUPT LOCKOUT
CLEAR BUFFER CONTROLS
ERROR STOP
HALT
1-39
EXF -
(75) - EXTERNAL FUNCTION
This instruction is used to select an external input or output device to communicate with the TeleProgrammer.
The select function is accomplished by
'~ending out on the output lines a 12-bit llfunction code".
Each external
device is capable of recognizing and interpreting only its own unique code.
Thus, the programmer by selecting different external function codes can use
this same instruction to select all external devices.
The 12-bit function code is contained in the second and third words of the
three words which make up this instruction set.
The format of the three
words are best described by the following:'
,
Instruction
Set
Tag
I 0
IEXF Code
;
7
0
a
I
where
a b
5
The upper 6 bits
of the function code.
b
The lower 6 bits
of the function code.
c d
0
c
a
d
b
I I
·c
d
I I
The 12-bit Function Code
Note:
If the external device cannot be selected the TeleProgrammer halts.
1-40
Change 1
Example: Request the status of the typewriter (ready or not ready) , if busy,
wait; request typewriter input; and input to A.
I
(0010)
Tag
(0011 )
(0014)
7!
5
o
4
2
Request status of the typewriter.
{
{
I
I
Tag
0
is 42
Tag
0
Ilnp'ut to A
7
! 6
!
40
I
I 0
(0016)
I 0
(0017)
0
~
2
(0020)
0
2
0
Tag
{ Tag
I
(5
Input status response to A
INon Zero Jump
! 6 ! 1
(0015)
(0021)
~Theoctal function code for this
:=:0=====4~=====O===~
(0012)
(0013)
IEXF Code
0
1
0
If A = 0, typewriter is ready,
continue. If A f 0, it is not
ready, jump back to address
0010 (wait). (see note)
IEXF Code
!
7
I
5
Request typewriter to input a
~aracter to A.
The octal
~ code for th,g 's:
IlnEut to A
I
7
!
b
Input the character to A
Note:
In the jump back to address 0010 above, no Tag register is required
since the octal address is one whose significant bits can be expressed in
8 bits.
1-41
CIL -
(13) - CLEAR INTERRUPT LOCKOUT
NOTE
A do nothing (02) instruction should be
used at interrupt locations 10, 20, 30
and 40 when such interrupt levels 'are
used; then use the 013 or 113 instruction.
This instruction clears the interrupt lockout flip flop (F F).
This instruction
must be programmed at the end of every routine which is initiated by the
interrupt.
This instruction returns control to the main program.
Example: Assume an interrupt has occurred and a routine entered. At the
end of this routine show the instruction required to clear the Interrupt Lockout
and return control to the Main Program.
Tag
1
CSC -
ICIL
:
Note:
In this instruction, the Tag
designation becomes a part of the
function code itself. It c an only be
o or 1. Thus, to return to main
program after clearing interrupt
lockout, the Tag designation must
be- 1. If zero, control continues in
sequence.
Code
3
!
1
CLEAR SUFFER CONTROLS
(07) -
This instruction has the effect of sending a zero to buffer control and thus
putting that device in a "ready state".
If this instruction is used during a
buffer operation, it will stop the buffer.
Example:
I
Tag
0
Change 2
C lear buffer control.
lesc
i
0
Code
!
7
A Tag register designation
ignored in this single word
instruction.
1-42
IS
Two S TO P S are available; these are:
ERR
HLT
ERROR STOP
HALT STOP
=
=
ERR - (000) - ERROR STOP
This is an illegal instruction -- as such, it can be used as an Error Stop.
Example:
Use the Error Stop instruction.
o
o
o
Error Stop
HLT - (77) - PROGRAM STOP
This instruction is used to bring the program to a halt.
Example:
Tag
0
I
Use the S TO P instruction.
I
7
I
7
Program Stop
1-43
CHAPTER TWO
OPERATION
P
TAG ~EGISTER
---,- --I- •-I- ••
-I- --I- •-I
II
o
CLEARP
TAG REGISTER SELECT
1 I
:
2
:
3
1
I- - -I
RUN,ERR,SEL,
-- + -- .. - A
I
a
I
'10
, 8
,
REGISTER
7
I
6
, 5
7
I
.6
I 5
I
A
CLEA9
't-- - ...
C 10'
--+---+-I
I
aXR
I 3
'
2
,
I
I 0
2
,
I
I 0
REGISTER
,
3
I
AL..·~....;:·;.........
I.~....;:-:-.;:::;.....&I...:::-:-_-=---=.:....I
REGISTER
17;6:5:4:3:2:1 :01
CLE~zl-
~'I'
NON- LOCK
LOCK
RUN
~ RUN
SWEEP MASTER STEP
CLEAR
Figure 2-1
4
, 4
Z
IN ,OUTIIaA,OBA
~z(jIP~EN~~;MANUAL
INTERRUPT
, 9
8092 Operatorls Panel
TeleProgrammer OPERATORl s CONSOLE
The 8092 TeleProgrammer Operatorls Panel consists of several displays
and switches necessary for the operation of the TeleProgrammer.
The
panel (see figure 2-1) contains six display windows, six switches, and
a lock switch.
Four of the display windows can display in binary the
contents of nine 8092 registers.
Buttons beneath these displays clear
and enter data into the P, A, Z, and Tag registers (the only registers
into which data may be entered or cleared).
A fifth window contains
information as to which Tag register has been selected.
The sixth
window contains the operating lights which indicate the status of operation
2-1
of the TeleProgrammer.
ing and mode switches.
At the bottom of the panel are located all the operatThe operation of these switches is explained below:
SWITCHES
Manual Interrupt
-Momentary depression causes the TeleProgrammer to enter an interrupt routine
to determine the nature of the interrupt.
BFR.Z
- This 3-position switch chooses the register that is to be displayed in the a-bit
Z
register display.
-Y.P.. -
Displays the last word processed
during the last buffer ope ration (B FR register)
Center - Shows the current contents of the
Z register (Z register).
Down - Not assigned.
BER. P. BXR
- This 3-position switch chooses the register to be displayed in the 12-bit P register
display .
.Y..e.. - Displays the lowest-order 10 bits of
the address of the last word transferred
out, or the next word to be transferred in
on the buffer channel (BE R) register.
Tag 3 must be referenced for the highestorder 2 bits of the address.
Change 1
2-2
Center - Displays the address of the
current instruction (P register).
Down - Displays the lowest-order 10 bits
of the LWA + 1 of the buffer area (BXR)
register.
Tag 3 must be referenced for
the highest-order 2 bits of the address.
ENTER/SWEEP
-Sweep is used to display the contents of
core storage locations.
Enter is used
for entering information into core storage
from the console.
LOAD/MASTER CLgAR
- LOAD position allows speciallyprepared
paper tapes to be read into storage by the
paper tape reader.
Master CLEAR performs a TeleProgrammer clear which:
a.
Clears the registers
b.
Clears the control flip-flops
c.
Clears all waiting interrupts and
~emoves interrupt lockout.
Note:
The master clear does not alter
core storage.
RUN/STEP
.Y.!L -
In RUN position, a program
1S
executed at high speed starting at the location specified by the P register.
2-3
Change 1
Center - C enter position stops the computer
program.
If the switch is in RUN and an
ERR or HL T instruction is executed, the
switch must be returned to neutral and
then placed in RUN to continue computation.
Down - In STEP position, one storage
cycle of an instruction
IS
executed each
time the switch is set; a program may be
executed one instruction at a time for debugging.
NON-RUN LOCK
RUN LOCK
In the Lock position all other switches are
disabled and the TeleProgrammer is locked
In
the RUN position.
In the non-lock position, the console switches
are enabled and the TeleProgrammer programs can be operated and modified from
the console.
DISPLAYS
Z REGISTER
- This display known as the Z register
group displays the Z and B FR registers
In
accordance with the setting of the B FR ,
Z switch.
A Register
-Displays the current contents of the A
register.
2-4
P Resister
- This display known
WI
the P regis&.r
gr"up di.plays the BER. p. and BXR
registers in accordance with the setting
of the B ER. P, BXR switch.
TAG REGISTER
- This display indicates the Tag register
currently being referenced by an inatruclion.
The contents of any Tag register m oIllY be
displayed by depressing one 01 the buMons
directly below the .elect indioa6Drs.
Oe-
pressing one 01 the .eIect bulk»n. alao
enabl. . the Tag regi ..... to be manually
set or cleared.
STATUS INDICATORS
RUN
-Indicates &hai the Tei.P!"OfIjJr..,m.r i. in
RUN stalus.
This does not necessarily
indicate that instructions are being executed.
ERR
-Indicate. that a timing fault haa occurred.
SEL
-Displayed each tim.
8ft
EXF ilUltruction
is ex.:utad; remain. until ••I.tion i.
completed.
A con...... display of BEL
with no apparent il!l)ut./ output _Doa usually
indie" the TeleProgrammer has Mhmp'-:<
Instructions
Tagl Codes
Cycles
Action Performed
I
LON
01
}
2
Load A with 1
I
ATT
}
1
Bits, 001, go to Tag reg. I
EXF
}
3
S elect the TTU, starting with the
first TTU.
I INA
}
2
Input the character from the selected
TTU to the A register.
I
}
}
3
Store character in A at desired
memory location
4
Add 1 to memory location where
characters are stored.
4
Add 1 to TTU select address.
This also tests last TTU address.
2
Subtract one more than number of
lines being serviced.
2
If not last servicing, jump back to
servIce next TTU.
I
04
20
I
I
STM
00
I
I
RAO
65
}
SBN
32
}
}
0475
0476
o I
o I
0 I
0477
0500
1 I NJP
o I 63
0501
Continue
I
Note:
The above instructions contain mnemonic function codes in
order to indicate the type of instruction being performed. Before
program execution, these must be replaced by their equivalent
numeric codes.
B-2
Example 2
Assuring Transmission Validity
Several techniques have evolved to assure message content validity.
One such technique is a form of the Fire code which is described
the following problem.
In
By this method, specific words of the data to
be transmitted are added into eight "Check Sum" (S) words.
After
computing each of the eight sum words, at both origin and destination
locations, comparisons of the corresponding sums indicate message
validity.
This technique provides the advantage of being able to use all
bits of a message character as jnformation bits.
a parity bit is not mandatory.
Thus the presence of
However, the presence of a parity bit·
does not affect or degrade the method.
Assume a block of 240 words of 1 character per word is to be transmitted.
This block is preceded by an 8 word header, and followed by
8 Check Sum words. Using a Fire code, the data in the header and
information portions are to be checked through comparisons of the accumulated sums in the 8 C-heck Sum (S) wopds.
The accumulated sums
of the sum words are determined by the following algorithm:
8 1
W. + W. + W + ---------- + Wn
1
J
k
S2
W i +1 + Wj + 1 + Wk +1 +
+ Wn +1
S3
Wi +2 + Wj + 2 + Wk+2 +
+ Wn +2
8 8
Wi+ 7 + Wj + 7 + Wk +7
------ +
Wn + 7
where i ,j ,k, --- n are the computer addresses
contb,ining the data words which are to be transmitted.
W = data words, thus W· = data word at address J
J
81' S2' --- 88 =·Check 8um words
B-3
In order to implement this method, a matrix of 32 words is used.
Each
of the 32 words contains 8 bits which indicate the computer addresses of
the words which are to be added in the first Check Sum word, S 1.
Thus the bit locations within the matrix indicate: i, j, k, ---n addresses
of the preceding algorithm.
The technique is indicated by the flow chart and diagram of TeleProgrammel" areas below:
Data
Block
1
1000 - -
8ave previous contents of 81' 8 2 ---8 8
Zeroize: 81,8 2 ---8 8
Address, A o ' (see sketch) Zeroize B,
8
Header
Words
M
(B = bit counter)
1
iE-----------(2
Octal
Addresses
240
Data
Words
j
1367- 1370--
I
8 8um
Words
1377Ao _ _
Wt + 8 1 - 8 1
Al
WtH + 8 2 --8 2
A2
where:
Al = 0334
A32
=
0373
A 32 - -
(0374)
(0375)
(0376)
(0377)
B-4
Temp
M
B
1M .
B·It
atrlx
32 Words
j
THE PROGRAM
Location
2000
2001
2002
I
0 1 LON
o 1 02
1
1 I ATT
Action Performed
Cycles
TI Code
}
1
}
1
3
Preset Tag register 1 to 0010 ,
(in bits)
I
2003
2004
2005
2006
2007
2010
2011
2012
2013
'2014
2015
2016
1 I LOM
3 170
o STM
3 24
21 RAO
0104
2\ RAO
01 06
°ISBN
3 34
21 NZP
0 03
1
}
2017
2020
2021
2022
0 1 LON
0100
11 STM
31 70
2023
2024
2025
2026
2027
2030
}
}
}
4
S ave the contents of the· check sum
words by storing initial contents at
following .addresses:
Sl-+ 0324
4
S2
}
2
}
2
}
2
}
3
21 RAO
01 22
2, NZP
o 17
1
}
4
}
2
OISTM
3 77
1
}
3
I
I
3
~0325
Sa -+0333
This loop presets each of the eight
check stirn words to zero.
.
Set Bit Counier, B, to zero.
(B is loc~ted at octal address ,377 • )
B-5
THE PROGRAM
Location
T
Code
Cycles
Action Performed
2031
2032
2033
2034
0
3
0
3
LON
33
STM
76
}
2
}
3
Store first address minus 1 of Bit
Matrix at M; where M is at address
0376.
2035
2036
0
3
RAO
76
}
4
M +
2037
2040
2041
2042
0
3
2
1
S8N
74
ZJP
12
}
}
2
Test address at M, and jump if
last Matrix Word has been serviced.
2043
2044
0
3
LOI
76
}
4
Load next Matrix Word into A
2045
0
SHA
}
1
Shift Matrix Word left 1
2046
2047
0
3
STM
75
}
3
Store shifted Matrix Word at temporary register (at address 0375) .
2050
2051
0
0
LPN
001
}
2
Look at what previously had been
the leftmost bit of Matrix Word.
2052
2053
2
0
NZP
66
}
2
If bit -I 0, jump; otherwise, continue.
2054
2055
0
3
RAO
77
}
4
8 + 1 - - 8 (Increase bit count
by 1.)
2056
2057
0
0
LPN
07
}
2
Look at last three bit positions of
count at B.
l~M
2
8-6
THE PROGRAM
I
Location
TI Code
2060
2061
21 ZJP
0135
Cycles
}
Action Performed
2
If next Matrix Word is required,
Jump. Otherwise, continue.
3
Return the current Matrix Word to
A and jump back to look at next
bit.
I
LDM
75
UJP
45
}
}
2066
2067
2070
2071
01 LDM
31 77
o STM
3 1 74
1
}
}
2072
2073
2074
2075
1 1 LDI
3 I 74
11 RAD
3 1 70
} "
2076
2077
2100
2101
01 RAO
3 I 74
2 RAO
o I 75
}
}
2062
2063
2064
2065
01
3
21
°1
2
I
I
}
3
Bit Count ..... t, where t is at address
0374.
3
3
Wt + Sl---j. S 1
4
Update parameters In above equation.
.
3
I
I
2102
2103
21 NZP
0172
}
2
Loop back to lac ation , 2072, if not
zero.
}
4
Store into last. Check Sum Word at
address 0777.
}
4
I
I
2104
2105
2106
2107
1
3
1
3
2110
2111
o I 54
21 UJP
}
2
Loop back for next iteration.
2112
OIHLT
}
1
Stop
I LDI
174
I RAD
177
.
B-7·
APPENPIX C - MATHEMATICAL
T~BLES
TABLE OF POWERS OF TWO
o
2
4
8
1
2
3
1.0
0.5
0.25
0.125
16
32
64
128
4
5
6
7
0.062
0.031
0.015
0.007
256
512
1 024
2 048
8
9
10
11
5
25
625
812 5
0.003 906 25
OD01 953 125
0.000 976 562 5
0.000 488 281 25
4
8
16
32
096
192
384
768
12
13
14
15
0.000
0.000
0.000
QOOO
244
122
06.1
030
140
070
035
517
625
312 5
156 25
578 125
65
131
262
524
536
072
144
288
16
17
18
19
0.000
0.000
0.000
0.000
015
007
003
001
258
629
814
907
789
394
697
348
062
531
265
632
5
25
625
812 5
1
2
4
8
048
097
194
388
576
152
304
608
20
21
22
23
0.000
0.000
0.000
0.000
000
000
000
000
953
476
238
119
674
837
418
209
316
158
579
289
406
203
101
550
25
125
562 5
781 25
16
33
67
134
777
554
108
217
216
432
864
728
24
25
26
27
0.000 000 059 604
0.000 000 029 802
0.000 000 014 901
~OOO 000 007 450
644
322
161
580
775
387
193
596
390
695
847
923
625
312 5
656 25
828 125
268
536
073
2 147
435
870
741
483
456
912
824
648
28
29
30
31
0.000
0.000
0.000
0.000
000
000
000
000
003
001
000
000
725
862
931
465
290
645
322
661
298
149
574
287
461
230
615
307
914
957
478
739
062
031
515
257
5
25
625
812 5
4
8
17
34
294
589
179
359
967
934
869
738
296
592
184
368
32
33
34
35
0.000
0.000
0.000
0.000
000
000
000
000
000
000
000
000
232
116
058
029
830
415
207
103
643
321
660
830
653
826
913
456
869
934
467
733
628
814
407
703
906
453
226
613
25
125
562 5
281 25
68
137
274
549
719
438
877
755
476
953
906
813
736
472
944
888
36
37
38
39
0.000
0.000
0.000
0.000
000
000
000
000
000
000
000
000
014
007
003
001
551
275
637
818
915
957
978
989
228
614
807
403
366
183
091
545
851
425
712
856
806
903
951
475
640
320
660
830
C-l
625
312 5
156 25
078 125
OCTAL-DECIMAL INTEGER CONVERSION TABLE
.0.0.0.0
to
.0777
(.octal)
.0.0.0.0
to
.0511
(Decimal)
.octal
Decimal
100.0.0 - 4.096
2.0.0.0.0 - 8192
3.0.0.0.0 - 12288
4.0.0.0.0 - 16384
50000 - 2.048.0
6.0.0.0.0 - 24576
7.0.0.0.0 - 28672
.0.0.0.0
.0.010
.0.02.0
.0.03.0
.0.04.0
.0.05.0
.0.06.0
.0.07.0
.0100
.0110
.0120
.013.0
0140
.0512
to
to
1.023
(Decimal)
1777
(.octal)
1
2
3
.0.001
.0.0.09
.0.017
.00.02
.0.010
.0.018
.0.0.03
.0.011
.0.019
.0.0.04
0.012
.0.0.05
.0.013
.0.02.0
.0021
.0.024 . .0.025
.0032 .0.033
.0.026
.0.034
.0.028
0.036
.0.04.0
.0.048
.0.041
.0.049
.0.057
.0.042
.0.05.0
.0.058
.0.027
.0.035
.0.043
.0051
.0029
.0037
.0.045
.0.065
.0.066
.0.074
.0.082
.0.09.0
.0.098
.01.06
.0114
.0122
0.067
.0.075
.0.083
.0.091
.0.099
.01.07
.0131
.0139
.0056
.0.064
.0.072
.0.08.0
.0.088
0096
.0.073
.0.081
.0.089
0097
.015.0
.01.04
.01.05
.016.0
.0112
.0113
.017.0
.012.0
.0121
.0.059
.0115
.om
4
.0.044
.0.052
.0.06.0
5
.0053
.0.061
.0.068
.0.076
.0.069
.0.077
.0.084
.0.085
.0.092
.01.0.0
.0.093
.0101
.01.09
.0108
.0116
.0124
.0117
.0125
0132
.014.0
.0148
0156
.0164
.0172
0133
.0141
.0149
.0157
.0165
.0173
.018.0
.0188
.0181
.0189
.02.0.0
.0128
.0129
.013.0
.0136
.0144
.0152
.0160
.0168
.0137
.0145
.0153
.0161
.0169
.0138
.0146
.0154
.0162
.017.0
.026.0
.027.0
.0176
.0184
.0177
.0185
.0178
.0186
.0171
.0179
.0187
.03.0.0
.031.0
.032.0
.033.0
.034.0.
.0192
.02.0.0
.02.08
.0216
.0224
.0232
.0193
.02.01
.02.09
.0217
.0225
.0233
.0241
.0194
.0195
.0196
.0197
.02.02
.0210
.0218
.0226
.0234
.02.03
.0211
.0219
.0227
.02.04
.02.05
.0240
.0248
.0147
.0155
.0163
.0249
.0242
.025.0
.0235
.0243
.0251
0212
.022.0
0
1
2
3
4
5
6
7
.0257
.0265
.0273
.026.0
.0268
.0275
.0276
.0284
.0261
.0269
.0277
.0285
.0293
.03.01
.03.09
.0317
.0262
.027.0
.0289
.0297
.03.05
.0313
.0258
.0266
.0274
.0282
.029.0
.0298
.03.06
.0314
.0259
.0267
.044.0
.045.0
.046.0
.047.0
.0256
.0264
.0272
.028.0
.0288
.0296
.03.04
.0312
.0263
.0271
.0279
.0287
.0295
.03.03
.0311
.0319
.05.0.0
.0320
.054.0
.055.0
.0118
.0119
.056.0
.0126
.0127
.057.0
.0321
.0329
.0337
.0345
.0353
.0361
.0369
.0377
.0322
.033.0
.0338
.0346
.0354
.0362
.037.0
.0378
.0326
.0334
.0342
.01.03
DIll
.0328
.0336
.0344
.0352
.036.0
.0368
.0376
.0325
.0333
.0.095
051.0
052.0
.0530
0134
.0142
.015.0
.0158
0166
0135
.0143
.0151
0159
.0167
060.0
.0384
.0385
.0610
0392
.04.0.0
.04.08
.0416
.0393
.04.01
.04.09
.0386
.0394
.04.02
.041.0
.0418
7
6
.021.0
.022.0
.023.0
.024.0
.025.0
.035.0
.036.0
.037.0
10.0.0
0
.0.00.0
.0.008
.0.016
.0213
.0228
.0236
.0221
.0229
.0237
.0244
.0252
.0245
.0253
.0.0.06
.0.014
.0.022
.0.0.07
.0.015
.0.03.0
.0.038
.0023
.0.031
.0.039
.0.046
.0.054
.0.062
.0.047
.0.055
.0.063
.0.07.0
.0.078
.0.086
.0.094
.01.02
.011.0
.0.071
.0.079
.0.087
.040.0
.0410
.042.0
.043.0
.062.0
.063.0
.064.0
.0174
.0182
.019.0
.om
.065.0
.0183
.0191
.066.0
.067.0
.0424
.0432
.044.0
.0198
.02.06
.0214
.0199
.07.0.0
.0448
.02.07
.071.0
.0215
.0223
.0231
.0239
.072.0
.0247
.0255
.076.0
.077.0
.0456
.0464
.0472
.048.0
.0488
.0496
14.0.0
141.0
.0222
.023.0
.0238
.0246
.0254
.073.0
.074.0
.075.0
0
1
2
3
4
5
.0512
.0513
.0514
.0515
102.0
103.0
1.04.0
105.0
.052.0
.0528
.0536
.0544
.0552
.0522
.053.0
.0538
.0546
1.06.0
.056.0
.0521
.0529
.0537
.0545
.0553
.0561
.0568
.0569
.0517
.0525
.0533
.0541
.0549
.0557
.0565
.0573
.0518
.0526
.0534
.0542
.055.0
.0558
.0566
.0574
.0519
.0527
.0535
.0543
.0551
.0559
.0567
1.07.0
.0523
.0531
.0539
.0547
.0555
.0563
.0571
.0516
.0524
.0532
.054.0
.0548
.0556
.0564
.0572
.0575
liDO
.0576
.0584
.0577
.0585
.0593
.058.0
.0588
.0581
.0589
.0582
.0596
.0597
.06.04
.0612
.062.0
.0628
.0636
.06.05
.0613
.0621
.0598
.06.06
.0614
.0622
.063.0
.0583
.0591
.0599
15.0.0
151.0
152.0
153.0
154.0
155.0
156.0
157.0
.0644
.0652
.0645
.0653
.066.0
0668
0676
.0661
0669
.0677
.0684
.0685
0692
.0693
.0654
0662
067.0
.0678
.0686
.0694
10.0.0
1010
1110
112.0
.0592
113.0
114.0
115.0
116.0
117.0
.06.0.0
.06.08
.0616
.0624
.0632
.06.09
.0617
.0625
.0633
.06.01
.0554
.0562
.057.0
.0578
.0586
.06.02
.061.0
.0618
.0626
.0579
.0587
.0595
.06.03
.0611
.0619
.0627
.0634
.0635
.0643
.0594
6
.0629
.0637
.0638
.0615
.0623
.0631
.0639
12.0.0
.064.0
.0641
121.0
1220
1230
1240
125.0
1260
.0648
0656
0664
.068.0
0688
.0649
0657
0665
0673
0681
.0689
.0642
.065.0
0658
0666
0674
0682
.069.0
.0651
0659
0667
.0675
0683
.0691
127.0
.0696
.0697
.0698
.0699
.07.0.0
.07.01
.07.02
.0695
.07.03
13.0.0
131.0
132.0
133.0
134.0
135.0
136.0
137.0
.07.04
.0712
.072.0
.0728
.0736
.0744
.0752
.076.0
.07.05
.0713
.0721
.0729
.0737
.0745
.0753
.0761
.07.06
.0714
.0722
.073.0
.0738
.0746
.0754
.0762
.07.07
.0715
.0723
.0731
.0739
.0747
.0755
.0763
.07.08
.0716
.0724
07.09
.0717
.0725
.0733
.0741
.0749
.0757
.0765
.071.0
.0718
.0726
.0734
.0742
.075.0
.0758
.0766
.0711
.0719
.0727
.0735
.0743
.0751
.0759
.0767
.0672
0732
.0740
.0748
0756
.0764
.0646
.06.07
C-2
.0647
.0655
.0663
.0671
.0679
0687
.0283
.0291
.0299
.03.07
.0315
.0324
.0331
.0339
.0332
.034.0
0347
0348
.0355
.0356
.0363
.0364
.0371
.0379
.0372
.0387
.0395
.04.03
.0411
.0426
.0434
.0442
.0419
.0427
.0435
.0443
.0449
.0457
.0465
.0473
.0481
.0489
.045.0
.0451
.0458
.0466
.0474
.0482
.049.0
.0459
.0467
.0475
.0483
.0497
.05.05
.0498
.05.06
.0417
.0425
.0433
.0441
.0491
.0499
.05.07
0
1
2
3
143.0
144.0
145.0
146.0
.0816
.0824
.077.0
.0778
.0786
.0794
.08.02
.081.0
.0818
.0826
.0771
.0779
.0787
.0795
147.0
.0769
.0777
.0785
.0793
.08.01
.08.09
.0817
.0825
.0832
.0833
.0834
.084.0
.0848
.0856
.0841
.0864
.0872
.088.0
.0888
.0865
.0873
.0881
.0889
.0842
.085.0
.0858
.0866
.0874
.0882
.089.0
16.0.0
.0896
.0897
.0898
161.0
1620
1630
1640
.0904
0912
0920
.0928
0936
09.05
0913
0921
.0929
0937
.0944
.0952
.096.0
.0968
.0976
.0984
.0992
10.0.0
142.0
165.0
166.0
167.0
17.0.0
1710
172.0
173.0
174.0
175.0
176.0
177.0
.0292
.03.0.0
.03.08
.0316
.0323
.0768
.0776
.0784
.0792
.08.0.0
.08.08
7
.059.0
.05.04
.0281
.08.03
.0811
.0819
.0827
.0835
.0843
.0350
.0358
.0366
.0374
.0382
.0389
.0397
.039.0
.0398
.04.06
.0414
.0422
.0391
.0399
.04.07
.0415
.0423
.043.0
.0438
.0446
.0431
.0439
.0447
.0476
.0484
.0453
.0461
.0469
.0477
.0485
.0454
.0462
.047.0
.0478
.0486
.0463
.0471
.0479
.0487
.0492
.05.0.0
.05.08
.0493
.05.01
.05.09
.0494
.05.02
.051.0
.0495
.05.03
.0511
.038.0
.0388
.0396
.04.04
.0412
.042.0
.0428
.0436
.0444
.0452
.046.0
.0468
4
.0772
.078.0
.0788
.0796
.08.04
.0812
.082.0
.0828
.04.05
.0413
.0421
.0429
.0437
.0445
5
.0773
.0781
.0789
.0797
.08.05
.0813
.0821
.0829
.0891
.0892
.0885
.0893
.0906
.0914
0922
093.0
0938
.0899
0907
0915
0923
.0931
0939
.09.0.0
.0908
0916
0924
.0932
094.0
.09.01
.0909
0917
0925
.0933
0941
.0945
.0953
.0946
.0954
.0947
.0955
.0948
.0956
.0949
.0957
10.08
.0961
.0969
.0977
.0985
.0993
1.0.01
10.09
1.016
1017
.0962
.097.0
.0978
.0986
.0994
10.02
1.010
1.018
.0963
.0971
.0979
.0987
.0995
1.0.03
1.011
1.019
.0964
.0972
.098.0
.0988
.0996
1.0.04
1.012
1.02.0
.0965
.0973
.0981
.0989
.0997
1.0.05
1.013
1.021
.0859
.0867
.0875
.0327
.0335
.0343
.0351
.0359
.0357
.0365
.0373
.0381
.0883
.0851
.0294
.03.02
.031.0
.0318
0341
0349
.0836
.0844
.0852
.086.0
.0868
.0876
.0884
.0849
.0857
.0278
.0286
0837
.0845
.0853
.0861
.0869
.0877
.0367
.0375
.0383
.0455
6
7
.0774
.0782
.079.0
.0798
.08.06
.0814
.0822
.083.0
.0775
.0783
.0791
.0799
.08.07
.0815
.0823
.0831
.0838
.0846
.0854
.0839
.0862
.087.0
.0878
.0886
.0894
.09.02
0910
.0918
0926
.0934
.0942
.095.0
.0958
.0966
.0974
.0982
.0990
.0998
1.0.06
1014
1022
.0847
.0855
.0863
.0871
.0879
.0887
.0895
.09.03
0911
.0919
0927
.0935
.0943
.0951
.0959
.0967
.0975
.0983
.0991
.0999
10.07
1.015
1023
OCTAL-DECIMAL INTEGER CONVERSION TABLE
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
2000
20)0
2020
2030
2040
2050
2060
2070
1024
1032
1040
1048
1056
1064
1072
1080
1025
1033
1041
1049
1057
1065
1073
1081
1026
1034
1042
1050
1058
1066
1074
1082
1027
1035
1043
1051
1059
1067
1075
1083
1028
1036
1044
1052
1060
1068
1076
1094
1029
1037
1045
1053
1061
1069
1077
1085
1030
1038
1046
1054
1062
1070
1078
1086
1031
1039
1047
1055
1063
1071
1079
1087
2400
2410
2420
2430
2440
2450
2460
2470
1280
1288
1296
1304
1312
1320
1328
1336
1281
1289
1297
1305
1313
1321
1329
1337
1282
1290
1298
1306
1314
1322
1330
1338
1283
1291
1299
1307
1315
1323
1331
1339
1284
1292
1300
1308
1316
1324
1332
1340
1285
1293
1301
1309
1317
1325
1333
1341
1286
1294
1302
1310
1318
1326
1334
1342
1287
1295
1303
1311
1319
1327
1335
1343
2100
2100
2120
2130
2140
2150
2160
2170
1088
1096
1104
1112
1120
1128
1136
1144
1089
1097
1105
1113
1121
1129
1137
1145
1090
1098
1106
1114
1122
1130
1138
1146
1091
1099
1107
1115
1123
1131
1139
1147
1092
1100
1108
1116
1124
1132
1140
1148
1093
1101
1109
1117
1125
1133
1141
1149
1094
1102
1110
1118
1126
1134
1142
1150
1095
1103
1111
1119
1127
1135
1143
1151
2500
2510
2520
2530
2540
2550
2560
2570
1344
1352
1360
1368
1376
1384
1392
1400
1345
1353
1361
1369
1377
1385
1393
1401
1346
1354
1362
1370
1378
1386
1394
1402
1347
1355
1363
1371
1379
1387
1395
1403
1348
1356
1364
1372
1380
1388
1396
1404
1349
1357
1385
1373
1381
1389
1397
1405
1350
1358
1366
1374
1382
1390
1398
1406
1351
1359
1367
1375
1383
1391
1399
1407
2200
2210
2220
2230
2240
2250
2260
2270
1152
1160
1168
1176
1184
1192
1200
1208
1153
1161
1169
1177
1185
1193
1201
1209
1154
1162
1170
1178
1186
1194
1202
1210
1155
1163
1171
1179
1187
1195
1203
1211
1156
1164
'1172
1180
1188
1196
1204
1212
1157
1165
1173
1181
1189
1197
1205
1213
1158
1166
1174
1182
1190
1198
1206
1214
1159
1167
1175
1183
1191
1199
1207
1215
2600
2610
2620
2630
2640
2650
2660
2670
1408
1416
1424
1432
1440
1448
1456
1464
1409
1417
1425
1433
1441
1449
1457
1465
1410
1418
1426
1434
1442
1450
1458
1466
1411
1419
1427
1435
1443
1451
1459
1467
1412
1420
1428
1436
1444
1452
1460
1468
1413
1421
1429
1437
1445
1453
1461
1469
1414
1422
1430
1438
1446
1454
1462
1470
1415
;423
1431
1439
1447
1455
1463
1471
2300
2310
2320
2330
2340
2350
2360
2370
1216
1224
1232
1240
1248
1256
1264
1272
1217
1225
1233
1241
1249
1257
1265
1273
1218
1226
1234
1242
1250
1258
1266
1274
1219
1227
1235
1243
1251
1259
1267
1275
1220
1228
1236
1244
1252
1260
1268
1276
1221
1229
1237
1245
1253
1261
1269
1277
1222
1230
1238
1246
1254
1262
1270
1278
1223
1231
1239
1247
1255
1263
1271
1279
2700
2710
2720
2730
2740
2750
2760
2770
1472
1480
1488
1496
1504
1512
1520
1528
1473
1481
1489
1497
1505
1513
1521
1529
1474
1482
1490
1498
1506
1514
1522
1530
1475
1483
1491
1499
1507
1515
1523
1531
1476
1484
1492
1500
1508
1516
1524
1532
1477
1485
1493
1501
1519
1517
1525
1533
1478
1486
1494
1502
1510
1518
1526
1534
1479
1487
1495
1503
1511
1519
1527
1535
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
3000
3010
3020
3030
3040
3050
3060
3070
1536
1544
1552
1560
1568
1576
1584
1592
1537
1545
1553
1561
1569
1577
1585
1593
1538
1546
1554
1562
1570
1578
1586
1594
1539
1547
1555
1563
1571
1579
1587
1595
1540
1548
1556
1564
1572
1580
1588
1596
1541
1549
1557
1565
1573
1581
1589
1597
1542
1550
1558
1566
1574
1582
1590
1598
1543
1551
1559
1567
1575
1583
1591
1599
3400
3410
3420
3430
3440
3450
3460
3470
1792
1800
1808
1816
1824
1832
1840
1848
1793
1801
1809
1817
1825
1833
1841
i849
1794
1802
1810
1818
1826
1834
1842
1850
1795
1803
1811
1819
1827
1835
1843
1851
1796
1804
1812
1820
1828
1836
1844
1852
1797
1805
1813
1821
1829
1837
1845
1853
1798
1806
1814
1822
1830
1838
1946
1854
1799
1807
1815
1823
1831
1839
1847
1855
3100
3110
3120
3130
3140
3150
:i160
3170
1600
1608
1616
1624
1632
1640
1648
1656
1601
1609
1617
1625
1633
1641
1649
1657
1602
1610
1618
1626
1634
1642
1650
1658
1603
1611
1619
1627
1635
1643
1651
1659
1604
1612
1620
1628
1636
1644
1652
1660
1605
1613
1621
1629
1637
1645
1653
1661
1606
1614
1622
1630
1638
1646
1654
1662
1607
1615
1623
1631
1639
1647
1655
1663
3500
3510
3520
3530
3540
3550
3560
3570
1856
1864
1872
1880
1888
1896
1904
1912
1857
1865
1873
1881
1889
1897
1905
1913
1858
1866
1874
1882
1890
1898
1906
1914
1859
1867
1875
1883
1891
1899
1907
1915
1860
1868
1876
1884
1892
1900
1908
1916
1861
1869
1877
1885
1893
1901
1909
1917
1862
1870
1878
1886
1894
1902
1910
1918
1863
1871
1879
1887
1895
1903
1911
1919
3200
3210
3220
3230
3240
3250
3260
3270
1664
1672
1680
1688
1696
1704
1712
1720
1665
1673
1681
1689
1697
1705
1713
1721
1666
1674
1682
1690
1698
1706
1714
1722
1667
1675
1683
1691
1699
1707
1715
1723
1668
1676
1684
1692
1700
1708
1716
1724
1669
1677
1685
1693
1701
1709
1717
1725
1670
1678
1686
1694
1702
1710
1718
1726
1671
1679
1687
1695
1703
1711
1719
1727
3600
3610
3620
3630
3640
3650
3660
3670
1920
1928
1936
1944
1952
1960
1968
1976
1921
1929
1937
1945
1953
1961
1969
1977
1922
1930
1938
1946
1954
1962
1970
1978
1923
1931
1939
1947
1955
1963
1971
1979
1924
1932
1940
1948
1956
1964
1972
1980
1925
1933
1941
1949
1957
1965
1973
1981
1926
1934
1942
1950
1958
1966
1974
1982
1927
1935
1943
1951
1959
1967
1975
1983
3300
3310
3320
3330
3340
3350
3360
3370
1728
1736
1744
1752
1760
1768
1776
1784
1729
1737
1745
1753
1761
1769
1777
1785
1730 1731
1738 1739
1746 1747
1754 1755
1762 1763
1770 .1771
1778 1779
1786 1787
1732
1740
1748
1756
1764
1772
1780
1788
1733
1741
1749
1757
1765
1773
1781
1789
1734
1742
1750
1758
1766
1774
1782
1790
1735
1743
1751
1759
1767
1775
1783
1791
3700
3710
3720
3730
3740
3750
3760
3770
1984
1992
2000
2008
2016
2024
2032
2040
1985
1993
2001
2009
2017
2025
2033
2041
1986
1994
2002
2010
2018
2026
2034
2042
1987
1995
2003
2011
2019
2027
2035
2043
1988
1996
2004
2012
2020
2028
2036
2044
1989
1997
2005
2013
2021
2029
2037
2045
1990
1998
2006
2014
2022
2030
2038
2046
1991
1999
2007
2015
2023
2031
2039
2047
2000
to
2777
10ctaii
1024
to
1535
IDecimal1
Octal Decimal
10000 - 4096
20000 - 8192
30000 - 12288
40000 - 16384
50000 - 20480
60000 - 24576
70000 - 28672
7
3000
to
3777
10ctaii
1536
to
2047
10ecimaii
..
C-3
OCTAL-DECIMAL INTEGER CONVERSION TABLE
0
4000
2048
10
10
4777
10clal)
2559
10ecimal)
Oclal Decimal
10000 - 4096
20000- 8192
30000 - 12288
40000 - 16384
50000 - 20480
60000 - 24576
70000 - 28672
2560
10
10
5777
10clal)
3071
(Oecimal)
2
3
4
5
6
7
0
1
2
3
4
5
6
7
4000
4010
4020
4030
4040
4050
4060
4070
2048
2056
2064
2072
2080
2088
2096
2104
2049
2057
2065
2073
2081
2089
2097
2105
2050
2058
2066
2074
2082
2090
2098
2106
2051
2059
2067
2075
2083
2091
2099
2107
2052
2060
2068
2076
2084
2092
2100
2108
2053
2061
2069
2077
2085
2093
2101
2109
2054
2062
2070
2078
2086
2094
2102
2110
2055
2063
2071
2079
2087
2095
2103
2111
4400
4410
4420
4430
4440
4450
4460
4470
2304
2312
2320
2328
2336
2344
2352
2360
2305
2313
2321
2329
2337
2345
2353
2361
2306
2314
2322
2330
2338
2346
2354
2362
2307
2315
2323
2331
2339
2347
2355
2363
2308
2316
2324
2332
2340
2348
2356
2364
2309
2317
2325
2333
2341
2349
2357
2365
2310
2318
2326
2334
2342
2350
2358
2366
2311
2319
2327
2335
2343
2351
2359
2367
4100
4110
4120
4130
4140
4150
4160
4170
2112
2120
2128
2136
2144
2152
2160
2168
2113
2121
2129
2137
2145
2153
2161
2169
2114 2115
2122 2123
2130 ·2131
2138 2139
2146 2147
2154 2155
2162 2163
2170 2171
2116
2124
2132
2140
2148
2156
2164
2172
2117
2125
2133
2141
2149
2157
2165
2173
2118
2126
2134
2142
2150
2158
2166
2174
2119
2127
2135
2143
2151
2159
2167
2175
4500
4510
4520
4530
4540
4550
4560
4570
2368
2376
2384
2392
2400
2408
2416
2424
2369
2377
2385
2393
2401
2409
2417
2425
2370
2378
2386
2394
2402
2410
2418
2426
2371
2379
2387
2395
2403
2411
2419
2427
2372
2380
2388
2396
2404
2412
2420
2428
2373
2381
2389
2397
2405
2413
2421
2429
2374
2382
2390
2398
2406
2414
2422
2430
2375
2383
2391
2399
2407
2415
2423
2431
4200
4210
4220
4230
4240
4250
4260
4270
2176
2184
2192
22M
2208
2216
2224
2232
2177
2185
2193
2201
2209
2217
2225
2233
2178
2186
2194
2202
2210
2218
2226
2234
2179
2187
2195
2203
2211
2219
2227
2235
2180
2188
2196
2204
2212
2220
2228
2236
2181
2189
2197
2205
2213
2221
2229
2237
2182
2190
2198
2206
2214
2222
2230
2238
2183
2191
2199
2207
2215
2223
2231
2239
4600
4610
4620
4630
4640
4650
4660
4670
2432
2440
2448
2456
2464
2472
2480
2488
2433
2441
2449
2457
2465
2473
2481
2489
2434
2442
2450
2458
2466
2474
2482
2490
2435
2443
2451
2459
2467
2475
2483
2491
2436
2444
2452
2460
2468
2476
2484
2492
2437
2445
2453
2461
2469
2477
2485
2493
2438
2446
2454
2462
2470
2478
2486
2494
2439
2447
2455
2463
2471
2479
2487
2495
4300
4310
4320
4330
4340
4350
4360
4370
2240
2248
2256
2264
2272
2280
2288
2296
2241
2249
2257
2265
2273
2281
2289
2297
2242
2250
2258
2266
2274
2282
2290
2298
2243
2251
2259
2267
2275
2283
2291
2299
2244
2252
2260
2268
2276
2284
2292
2300
2245
2253
2261
2269
2277
2285
2293
2301
2246
2254
2262
2270
2278
2286
2294
2302
2247
2255
2263
2271
2279
2287
2295
2303
4700
4710
4720
4730
4740
4750
4760
4770
2496
2504
2512
2520
2528
2536
2544
2552
2497
2505
2513
2521
2529
2537
2545
2553
2498
2506
2514
2522
2530
2538
2546
2554
2499
2507
2515
2523
2531
2539
2547
2555
2500
2508
2516
2524
2532
2540
2548
2556
2501
2509
2517
2525
2533
2541
2549
2557
2502
2510
2518
2526
2534
2542
2550
2558
2503
2511
2519
2527
2535
2543
2551
2559
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
2823
2831
2839
2847
2855
2863
2871
2879
0
5000
1
5000
5010
5020
5030
5040
5050
5060
5070
2560
2568
2576
2584
2592
2600
2608
2616
2561
2569
2577
2585
2593
2601
2609
2617
2562
2570
2578
2586
2594
2602
2610
2618
2563
2571
2579
2587
2595
2603
2611
2619
2564
2572
2580
2588
2596
2604
2612
2620
2565
2573
2581
2589
2597
2605
2613
2621
2566
2574
2582
2590
2598
2606
2614
2622
2567
2575
2583
2591
2599
2607
2615
2623
5400
5410
5420
5430
5440
5450
5460
5470
2816
2824
2832
2840
2848
2856
2864
2872
2817
2825
2833
2841
2849
2857
2865
2873
2818
2826
2834
2842
2850
2858
2866
2874
2819
2827
2835
2843
2851
2859
2867
2875
2820
2828
2836
2844
2852
2860
2868
2876
2821
2829
2837
2845
2853
2861
2869
2877
2822
2830
2838
2846
2854
2862
2870
2878
5100
5110
5i20
. 5130
. 5140
5150
5160
5170
2624
2632
2640
2648
2656
2664
2672
2680
2625
2633
2641
2649
2657
2665
2673
2681
2626
2634
2642
2650
2658
2666
2674
2682
2627
2635
2643
2651
2659
2667
2675
2683
2628
2636
21i44
2652
2660
2668
2676
2684
2629
2637
2645
2653
2661
2669
2677
2685
2630
2638
2646
2654
2662
2670
2678
2686
2631
2639
2647
2655
2663
2671
2679
2687
5500
5510
5520
5530
5540
5550
5560
5570
2880
2888
2896
2904
2912
2920
2928
2936
2881
2889
2897
2905
2913
2921
2929
2937
2882
2890
2898
2906
2914
2922
2930
2938
2883
2891
2899
2907
2915
2923
2931
2939
2884
2892
2900
2908
2916
2924
2932
2940
2885
2893
2901
2909
2917
2925
2933
2941
2886 2887
2894 2895
2902 2903
2910 2911
2918 2919
2926 2927
2934 2935
2942 . 2943
5200
5210
5220
5230
5240
5250
5260
5270
2688
2696
2704
2712
2720
2728
2736
2744
2689
2697
2705
2713
2721
2729
2737
2745
2690
2698
2706
2714
2722
2730
2738
2746
2691
2699
2707
2715
2723
2731
2739
2747
2692
2700
2708
2716
2724
2732
2740
2748
2693
2701
2709
2717
2725
2733
2741
2749
2694
2702
2710
2718
2726
2734
2742
2750
2695
2703
2711
2719
2727
2735
2743
2751
5600
5610
5620
5630
5640
5650
5660
5670
2944
2952
2960
2968
2976
2984
2992
3000
2945
2953
2961
2969
2977
2985
2993
3001
2946
2954
2962
2970
2978
2986
2994
3002
2947
2955
2963
2971
2979
2987
2995
3003
2948
2956
2964
2972
2980
2988
2996
3004
2949
2957
2965
2973
2981
2989
2997
3005
2950
2958
2966
2974
2982
2990
2998
3006
2951
2959
2967
2975
2983
2991
2999
3007
5300
5310
5320
5330
5340
5350
5360
5370
2752
2760
2768
2776
2784
2792
2800
2808
2753
2761
2769
2777
2785
2793
2801
2809
2754
2762 .
2770·
2778
2786
2794
2802
2810
2755
2763
2771
2779
2787
2795
2803
2811
2756
2764
2772
2780
2788
2796
2804
2812
2757
2765
2773
2781
2789
2797
2805
2813
2758
2766
2774
2782
2790
2798
2806
2814
2759
2767
2775
2783
2791
2799
2807
2815
5700
5710
5720
5730
5740
5750
5760
5770
3008
3016
3024
3032
3040
3048
3056
3064
3009
3017
3025
3033
3041
3049
3057
3065
3010
3018
3026
3034
3042
3050
3058
3066
3011
3019
3027
3035
3043
3051
3059
3067
3012
3020
3028
3036
3044
3052
3060
3068
3013
3021
3029
3037
3045
3053
3061
3069
3014
3022
3030
3038
3046
3054
3062
3070
3015
3023
3031
3039
3047
3055
3063
3071
C-4
--
OCTAL-DECIMAL INTEGER CONVERSION TABLE
0
,
2
3
4
6000
6010
6020
6030
6040
6050
6060
6070
3072
3080
3088
3096
3104
3112
3120
3128
3073
3081
3089
3097
3105
3113
3121
3129
3074
3082
3090
3098
3106
3114
3122
3130
3075
3083
3091
3099
3107
3115
3123
3131
3076
3084
3092
3100
3108
3i16
3124
3132
3077
3085
3093
3101
3109
3117
3125
3133
3078
3086
3094
3102
3110
3118
3126
3134
3079
3087
3095
3103
3111
3119
3127
3135
6100
6110
6120
6130
6140
6150
6160
6170
3136
3144
3152
3160
3168
3176
3184
3192
3137
3145
3153
3161
3169
3177
3185
3193
3138
3146
3154
3162
3170
3178
3186
3194
3139
3147
3155
3163
3171
3179
3187
3195
3140
3148
3156
3164
3172
3180
3188
3196
3141
3149
3157
3165
3173
3181
3189
3197
3142
3150
3158
3166
3174
3182
3190
3198
6200
6210
6220
6230
6240
6250
6260
6270
3200
3208
3216
3224
3232
3240
3248
3256
3201
3209
3217
3225
3233
3241
3249
3257
3202
3210
3218
3226
3234
3242
3250
3258
3203 3204
3211 3212
3219 3220
3227 , 3228
3235 3236
3243 3244
3251 3252
3259 3260
3205
3213
3221
3229
3237
3245
3253
3261
6300
6310
6320
6330
6340
6350
6360
6370
3264
3272
3280
3288
3296
3304
3312
3320
3265
3273
3281
3289
3297
3305
3313
3321
3266
3274
3282
3290
3298
3306
3314
3322
3267
3275
3283
3291
3299
3307
3315
3323
3268
3276
3284
3292
3300
3308
3316
3324
0
,
2
3
7000
7010
7020
7030
7040
7050
7060
7070
3584
3592
3600
3608
3616
3624
3632
3640
3585
3593
3601
3609
3617
3625
3633
3641
3586
3594
3602
3610
3618
3626
3634
3642
7100
7110
7120
7130
7140
7150
7160
7170
3648
3656
3664
3672
3680
3688
3696
3704
3649
3657
3665
3673
3681
3689
3697
3705
7200
7210
7220
7230
7240
7250
7260
7270
3712
3720
3728
3736
3744
3752
3760
3768
7300
7310
7320
7330
7340
7350
7360
7370
3776
3784
3792
3800
3808
3816
3824
3832
0
,
2
3
6400
6410
6420
6430
6440
6450
6460
6470
3328
3336
3344
3352
3360
3368
3376
3384
3329
3337
3345
3353
3361
3369
3377
3385
3330
3338
3346
3354
3362
3370
3378
3386
3331
3339
3347
3355
3363
3371
3379
3387
3143
3151
3159
3167
3175
3183
3191
3199
6500
6510
6520
6530
6540
6550
6560
6570
3392
3400
3408
3416
3424
3432
3440
3448
3393
3401
3409
3417
3425
3433
3441
3449
3206
3214
3222
3230
3238
3246
3254
3262
3207
3215
3223
3231
3239
3247
3255
3263
6600
6610
6620
6630
6640
6650
6660
6670
3456
3464
3472
3480
3488
3496
3504
3512
3269
3277
3285
3293
3301
3309
3317
3325
3270
3278
3286
3294
3302
3310
3318
3326
3271
3279
3287
3295
3303
3311
3319
3327
6700
6710
6720
6730
6740
6750
6760
6770
4
5
6
7
3587
3595
3603
3611
3619
3627
3635
3643
3588
3496
3604
3612
3620
3628
3636
3644
3589
3497
3605
3613
3621
3629
3637
3645
3590
3598
3606
3614
3622
3630
3638
3646
3591
3599
3607
3615
3623
3631
3639
3647
3650
3658
3666
3674
3682
3690
3698
3706
3651
3659
3667
3675
3683
3691
3699
3707
3652
3660
3668
3676
3684
3692
3700
3708
3653
3661
3669
3677
3685
3693
3701
3709
3654
3662
3670
3678
3686
3694
3702
3710
3713
3721
3729
3737
3745
3753
3761
3769
3714
3722
3730
3738
3746
3754
3762
3770
3715
3723
3731
3739
3747
3755
3763
3771
3716
3724
3732
3740
3748
3756
3764
3772
3717
3725
3733
3741
3749
3757
3765
3773
3777
3785
3793
3801
3809
3817
3825
3833
3778
3786
3794
3802
3810
3818
3826
3834
3779
3787
3795
3803
3811
3819
3827
3835
3780
3788
3796
3804
3812
3820
3828
3836
3781
3789
3797
3805
3813
3821
3829
3837
5
6
7
4
5
6
7
3332
3340
3348
3356
3364
3372
3380
3388
3333
3341
3349
3357
3365
3373
3381
3389
3334
3342
3350
3358
3366
3374
3382
3390
3335
3343
3351
3359
3367
3375
3383
3391
3394 3395
3402 3403
3410 3411
3418 3419
3426 3427
3434 3435
3442 3443
3450 3451
3396
3404
3412
3420
3428
3436
3444
3452
3397
3405
3413
3421
3429
3437
3445
3453
3398
3406
3414
3422
3430
3438
3446
3454
3399
3407
3415
3423
3431
3439
3447
3455
3457
3465
3473
3481
3489
3497
3505
3513
3458
3466
3474
3482
3490
3498
3506
3514
3459
3467
3475
3483
3491
3499
3507
3515
3460
3468
3476
3484
3492
3500
3508
3516
3461
3469
3477
3485
3493
3501
3509
3517
3462
3470
3478
3486
3494
3502
3510
3518
3463
3471
3479
3487
3495
3503
3511
3519
3520
3528
3536
3544
3552
3560
3568
3576
3521
3529
3537
3545
3553
3561
3569
3577
3522
3530
3538
3546
3554
3562
3570
3578
3523
3531
3539
3547
3555
3563
3571
3579
3524
3532
3540
3548
3556
3564
3572
3580
3525
3533
3541
3549
3557
3565
3573
3581
3526
3534
3542
3550
3558
3566
3574
3582
3527
3535
3543
3551
3559
3567
3575
3583
0
,
2
3
4
5
6
7400
7410
7420
7430
7440
7450
7460
7470
3840
3848
3856
3864
3872
38&0
3888
3896
3841
3849
3857
3865
3873
3881
3889
3897
3842
3850
3858
3866
3874
3882
3890
3898
3843
3851
3859
3867
3875
3883
3891
3899
3844
3852
3860
3868
3876
3884
3892
3900
3845
3853
3861
3869
3877
3885
3893
3901
3846
3854
3862
3870
3878
3886
3894
3902
3847
3855
3863
3871
3879
3887
3895
3903
3655
3663
3671
3679
3687
3695
3703
3711
7500
7510
7520
7530
7540
7550
7560
7570
3904
3912
3920
3928
3936
3944
3952
3960
3905
3913
3921
3929
3937
3945
3953
3961
3906
3914
3922
3930
3938
3946
3954
3962
3907
3915
3923
3931
3939
3947
3955
3963
3908
3916
3924
3932
3940
3948
3956
3964
3909
3917
3925
3933
3941
3949
3957
3965
3910
3918
3926
3934
3942
3950
3958
3966
3911
3919
3927
3935
3943
3951
3959
3967
3718
3726
3734
3742
3750
3758
3766
3774
3719
3727
3735
3743
3751
3759
3767
3775
7600
7610
7620
7630
7640
7650
7660
7670
3968
3976
3984
3992
4000
4008
4016
4024
3969
3977
3985
3993
4001
4009
4017
4025
3970
3978
3986
3994
4002
4010
4018
4026
3971
3979
3987
3995
4003
4011
4019
4027
3972
3980
3988
3996
4004
4012
4020
4028
3973
3981
3989
3997
4005
4013
4021
4029
3974
3982
3990
3998
4006
4014
4022
4030
3975
3983
3991
3999
4007
4015
4023
4031
3782
3790
3798
3806
3814
3822
3830
3838
3783
3791
3799
3807
3815
3823
3831
3839
7700
7710
7720
7730
7740
7750
7760
7770
4032
4040
4048
4056
4064
4072
4080
4088
4033
4041
4049
4057
4065
4073
4081
4089
4034
4042
4050
4058
4066
4074
4082
4090
4035
4043
4051
4059
4067
4075
4083
4091
4036
4044
4052
4060
4068
4076
4084
4092
4037
4045
4053
4061
4069
4077
4085
4093
4038
4046
4054
4062
4070
4078
4086
4094
4039
4047
4055
4063
4071
4079
4087
4095
c-s
6000
to
6777
10ctal)
3072
to
3583
10ecimal)
Octal Oecimal
10000 - 4096
20000 - 8192
30000 - 12288
40000 - 16384
50000 - 20480
60000 - 24576
70000 - 28672
7
7000
to
7777
10ctal)
3584
to
4095
10ecimal)
OCTAL-DECIMAL FRACTION CONVERSION TABLE
OCTAL
DEC.
OCTAL
.000
.001
.002
.003
.004
.005
.006
.007
.000000
.001953
.003906
.005859
.007812
.009765
.011718
.013671
.100
.101
.102
.103
.104
.105
.106
.107
.010
.011
.012
.013
.014
.015
.016
.017
.015625
.017578
.019531
.021484
.023437
.025390
.027343
.029296
.020
.021
.022
.023
.024
.025
.026
.027
DEC.
OCTAL
DEC.
OCTAL
DEC.
.125000
.126953
.128906
.130859
.132812
.134765
.136718
.138671
.200
.201
.202
.203
.204
.205
.206
.207
.250000
.251953
.253906
.255859
.257812
.259765
.261718
.263671
.300
.301
.302
.303
.304
.305
.306
.307
.375000
.376953
.378906
.380859
.382812
.384765
.386718
.388671
.110
.111
.112
.113
.114
.115
.116
.117
.140625
.142578
.144531
.146484
.148437
.150390
.152343
.154296
.210
.211
.212
.213
.214
.215
.216
.217
.265625
.267578
.269531
.271484
.273437
.275390
.277343
.279296
.310
.311
.312
.313
.314
.315
.316
.317
.390625
.392578
.394531
.396484
.398437
.400390
.402343
.404296
.031250
.033203
.035156
.037109
.039062
.041015
.042968
.044921
.120
.121
.122
.123
.124
.125
.126
.127
.156250
.158203
.160156
.162109
.164062
.166015
.167968
.169921
.220
.221
.222
.223
.224
.225
.226
.227
.281250
.283203
.285156
.287109
.289062
.291015
.292968
.294921
.320
.321
.322
.323
.324
.325
.326
.327
.406250
.408203
.410156
.412109
.414062
.416015
.417968
.419921
.030
.031
.032
.033
.034
.035
.036
.037
.046875
.048828
.050781
.052734
.054687
.056640
.058593
.060546
.130
.131
.132
.133
.134
.135
.136
.137
.171875
.173828
.175781
.177734
.179687
.181640
.183593
.185546
.230
.231
.232
.233
.234
.235
.236
.237
.296875
.298828
.300781
.302734
.304687
.306640
.308593
.310546
.330
.331
.332
.333
.334
.335
.336
.337
.421875
.423828
.425781
.427734
.429687
.431640
.433593
.435546
.040
.041
.042
.043
.044
.045
.046
.047
.062500
.064453
.066406
.068359
.070312
.072265
.074218
.076171
.140
.141
.142
.143
.144
.145
.146
.147
.187500
.189453
.191406
.193359
.195312
.197265
.199218
.201171
.240
.241
.242
.243
.244
.245
.246
.247
.312500
.314453
.316406
.318359
.320312
.322265
.324218
.326171
.340
.341
.342
.343
.344
.345
.346
.347
.437500
.439453
.441406
.443359
.445312
.447265
.449218
.451171
.050
.051
.052
.053
.054
.055
.056
.057
.078125
.080078
.082031
.083984
.085937
.087890
.089843
.091796
.150
.151
.152
.153
.154
.155
.156
.157
.203125
.205078
.207031
.208984
.210937
.212890
.214843
.216796
.250
.251
.252
.253
.254
.255
.256
.257
.328125
.330078
.332031
.333984
.335937
.337890
.339843
.341796
.350
.351
.352
.353
.354
.355
.356
.357
.453125
.455078
.457031
.458984
.460937
.462890
.464843
.466796
.060
.061
.062
.063
.064
.065
.066
.067
.093750
.095703
.097656
.099609
.101562
.103515
.105468
.107421
.160
.161
.162
.163
.164
.165
.166
.167
.218750
.220703
.222656
.224609
.226562
.228515
.230468
.232421
.260
.261
.262
.263
.264
.265
.266
.267
.343750
.345703
.347656
.349609
.351562
.353515
.355468
.357421
.360
.361
.362
.363
.364
.365
.366
.367
.468750
.470703
.472656
.474609
.476562
.478515
.480468
.482421
.070
.071
.072
.073
.074
.075
.076
.077
.109375
.111328
.113281
.115234
.117187
.119140
.121093
.123046
.170
.171
.172
.173
.174
.175
.176
.177
.234375
.231)328
.238281
.240234
.242187
.244140
.246093
.248046
.270
.271
.272
.273
.274
.275
.276
.277
.359375
.361328
.363281
.365234
.367187
.369140
.371093
.373046
.370
.371
.372
.373
.374
.375
.376
.377
.484375
.486328
.488281
.490234
.492187
.494140
.496093
.498046
C-6
OCTAL-DECIMAL FRACTION CONVERSION TABLE
OCTAL
DEC.
OCTAL
DEC.
OCTAL
DEC.
OCTAL
DEC.
.000000
.000001
.000002
.000003
.000004
.000005
.000006
.000007
.000000
.000003
.000007
.000011
.000015
.000019
.000022
.000026
.000100
.000101
.000102
.000103
.000104
.. 000105
.000106
.000107
.000244
.000247
.000251
.000255
.000259
.000263
.000267
.000270
.000200
.000201
.000202
.000203
.000204
.000205
.000206
.000207
.000488
.000492
.000495
.000499
.000503
.000507
.000511
.000514
.000300
.000301
.000302
.000303
.000304
.000305
.000306
.000307
.000732
.000736
.000740
.000743
.000747
.000751
.000755
.000759
.000010
.000011
.000012
.000013
.000014
.000015
.000016
.000017
.000030
.000034
.000038
.000041
.000045
.000049
.000053
.000057
.000110
.000111
.000112
.000113
.000114
.000115
.000116
.000117
.000274
.000278
.000282
.000286
.000289
.000293
.000297
.000301
.000210
.000211
.000212
.000213
.000214
.000215
.000216
.000217
.000518
.000522
.000526
.000530
.000534
.000537
.000541
.000545
.000310
.000311
.000312
.000313
.000314
.000315
.000316
.000317
.000762
.000766
.000770
.000774
.000778
.000782
.000785
.000789
.000020
.000021
.000022
.000023
.000024
.000025
.000026
.000027
.000061
.000064
.000068
.000072
.000076
.000080
.000083
.000087
.000120
.000121
.000122
.000123
.000124
.000125
.000126
.000127
.000305
.000308
.000312
.000316
.000320
.000324
.000328
.000331
.000220
.000221
.000222
.000223
.000224
.000225
.000226
.000227
.000549
.000553
.000556
.000560
.000564
.000568
.000572
.000576
.000320
.000321
.000322
.000323
.000324
.000325
.000326
.000327
.000793
.000797
.000801
.. 000805
.000808
.000812
.000816
.000820
.000030
.000031
.000032
.000033
.000034
.000035
.000036
.000037
.000091
.000095
.000099
.000102
.000106
.000110
.000114
.000118
.000130
.000131
.000132
.000133
.000134
.000135
.000136
.000137
.000335
.000339
.000343
.000347
.000350
.000354
.000358
.000362
.000230
.000231
.000232
.000233
.000234
.000235
.000236
.000237
.000579
.000583
.000587
.000591
.000595
.000598
.000602
.000606
.000330
.000331
.000332
.000333
.000334
.000335
.000336
.000337
.000823
.000827
.000831
.000835
.000839
.000843
.000846
.000850
.000040
.000041
.000042
.000043
.000044
.000045
.000046
.000047
.000122
.000125
.000129
.000133
.000137
.000141
.000144
.000148
.000140
.000141
.000142
.000143
.000144
.000145
.000146
.000147
.000366
.000370
.000373
.000377
.000381
.000385
.000389
.000392
.000240
.000241
.000242
.000243
.000244
.000245
.000246
.000247
.000610
.000614
.000617
.000621
.000625
.000629
.000633
.000637
.000340
.000341
.000342
.000343
.000344
.000345
.000346
.000347
.000854
.000858
.000862
.000865
.000869
.000873
.000877
.000881
.000050
.000051
.000052
.000053
.000054
.000055
.000056
.000057
.000152
.000156
.000160
.000164
.000167
.000171
.000175
.000179
.000150
.000151 •
.000152
.000153
.000154
.000155
.000156
.000157
.000396
.000400
.000404
.000408
.000411
.000415
.000419
.000423
.000250
.000251
.000252
.000253
.000254
.000255
.000256
.000257
.000640
.000644
.000648
.000652
.000656
.000659
.000663
.000667
.000350
.000351
.000352
.000353
.000354
.000355
.000356
.000357
.000885
.000888
.000892
.000896
.000900
.000904
.000907
.000911
.000060
.000061
.000062
.000063
.000064
.000065
.000066
.000067
.000183
.000186
.000190
.000194
.000198
.000202
.000205
.000209
.000160
.000161
.000162
.000163
.000164
.000165
.000166
.000167
.000427
.000431
.000434
.000438
.000442
.000446
.000450
.000453
.000260
.000261
.000262
.000263
.000264
.000265
.000266
.000267
.000671
.000675
.000679
.000682
.000686
.000690
.000694
.000698
.000360
.000361
.000362
.000363
.000364
.000365
.000366
.000367
.000915
.000919
.000923
.000926
.000930
.000934
.000938
.000942
.000070
.000071
.000072
.000073
.000074
.000075
.000076
.000077
.000213
.000217
.000221
.000225
.000228
.000232
.000236
.000240
.000170
.000171
.000172
.000173
.000174
.000175
.000176
.000177
.000457
.000461
.000465
.000469
.000473
.000476
.000480
.000484
.000270
.000271
.000272
.000.273
.0002"74
.000275
.000276
.000277
.000701
.000705
.000709
.000713
.000717
.000720
.000724
.000728
.000370
.000371
.000372
.000373
.000374
.000375
.000376
.000377
.000946
.000949
.000953
.000957
.000961
.000965
.000968
.000972
C-7
OCTAL-DECIMAL FRACTION CONVERSION TABLE
OCTAL
DEC.
OCTAL
DEC.
OCTAL
DEC.
OCTAL
DEC.
.000400
.000401
.000402
.000403
.000404
.000405
.000406
.000407
.000976
.000980
.000984
.000988
.000991
.000995
.000999
.001003
.000500
.000501
.000502
.000503
.000504
.000505
.000506
.000507
.001220
.001224
.001228
.001232
.001235
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C-8
GLOSSARY
GLOSSARY OF TeleProgramming TERMS
The following glossary gives the meaning of terms that are used
relatively specialized sense in this manual.
In
a
ADDER
In general, a device used to add two quantities.
Specifically, the borrow structure in the subject
computer.
ADDRESS
The number designating a storage location; also
the storage location itself.
NO ADDRESS MODE
The TeleProgrammer permits the performance of arithmetic and logical operations by an
a-bit constant associated with the instruction and
using the memory location immediately following
the instruction as an. a-bit operand.
MEMORY ADDRESS MODE A mode of addressing wherein an
a-bit operand in any storage location is addressed
by the memory location (immediately following the
instruction). and the contents of the Tag register .
as referenced by T.
INDIRECT ADDRESS MODE Instructions employing indirect
addressing use the memory location immediately
following the instruction to refer to one of the
first 256 storage locations. The contents of
this location are used along with the contents of
the Tag register to form the address of the operand.
BIT
BORROW
BUFFER
Binary digit; may be either
"1"
or
"0".
In a subtractive counter or accumulator, a signal
indicating that in stage n, a "1" was subtracted
. from a "0".
Noun: A device in which data are stored temporarily in the' course of transmission from one
point to another. Verb: -To store data temporarily.
jl
Change 1
BUFFERED
INPUT/OUTPUT
A term indicating that the computer may carry
on high speed computation at the same time it is
exchanging data with a peripheral device. In
the TeleProgrammer, this term must be distinguished from normal I/O, during which the
computer cannot engage in computation.
CARRY
In an additive counter or accumulator, a signal
indicating that in stage n, a "1" was added to a
"1".
CHANNEL
A transmission path that connects the computer
to a given external equipment.
CLEAR
A command that removes a quantity from a
register by placing every stage in the "0"
state.
COMMAND
A signal that performs a unit operation, such as
transmitting contents of one register to another,
shifting a register, setting a flip-flop.
COMPLEMENT
Noun: See One's Complement to Two's Complement.
Verb: A command which produces the
one's complement of a given quantity.
CONTENT
The quantity or word held in a register or
storage location.
CORE
A small ferromagnetic toroid used as the bistable
device for storing a bit in a memory plane.
COUNTER
A register with provisions for increasing or
decreasing its content by 1 upon receiving the
appropriate command.
END-AROUND
BORROW
A borrow that is generated in the highest order
of an accumulator or counter, and is sent directly
to the lowest order stage.
ENTER
To manually place in a register a quantity that
is not from storage. In the TeleProgrammer,
quantities may be entered in only the Tag A, P,
and Z registers.
FUNCTION CODE
The lower 2 octal digits of the first word in the
instruction set.
Change 1
-2
INPUT
DISCONNECT
During an input instruction, a signal sent to the
computer by the external device to indicate that
the device has completed all available transmissions to the computer.
INPUT REQUEST
A request, by the computer, for information
from an external device. Occurs during input
instruction only. (See Resume.)
INTERRUPT
A signal (or class thereof) which, when received
and recognized by the computer, forces the computer to forestall its current operation and jump
to a subroutine, the starting address of which is
determined by the class of the interrupt. A
subroutine may have any number of options. It
may merely stop the computer, it may determine
the nature of the interrupt in order to take
corrective measures, or it may retur1\ the computer to another phase of the main program.
JUMP
An instruction that jumps from one sequence of
instructions to a second, and makes no preparation for returning to the first sequence.
LOAD
To place a quantity from storage in the A register.
LOCKOUT
Any function (usually of machine logic) that
inhibits an action which would normally occur
were the lockout not imposed.
LOGICAL
PRODUCT
In Boolean algebra, the AND function of several
terms.
The product is 11111 only when all the
terms are "1 11 ; otherwise it is 110". Sometimes
referred to as the result of "bit-by-bit" multiplication.
LOGICAL SUM
In Boolean algebra, the OR function of several
terms.
The sum is "1" when any or all of the
terms are 11111; it is 1'0" only when all are "0".
MASK
In the information of the logical products of two
quantities, one of them may be used as a mask
for the other.
The mask determines what part
of the other quantity is to be considered. Wherever the mask is "0", that part of the other
quantity is cleared, but wherever the mask IS a
111", the other quantity is left unaltered.
MASTER CLEAR
(MC)
A general command produced by placing the
Load/ C lear switch in the down (C LEAR)
position. An MC clears all of the crucial
registers and control FFs to prepare for a new
mode of operation.
MODULUS
An integer which describes certain arithmetic
characteristics of registers, especially counters
and accumulators, within a digital computer.
The
modulus of a device is defined by rn for an open
ended device and rn-l for a closed (end- around)
device, where r is the base of the number
system used and n is the number of digit positions (stages) in the device.
Generally, devices
with modulus rn use two's complement arithmetic
procedures, and devices with modulus rn-l use
one's complement procedures.
ONE'S
COMPLEMENT
With reference to a binary number, that number
which results from subtracting each bit of the
given number from the bit "1". A negative
number is expressed by the one's complement
of the corresponding positive number.
OPERAND
The quantity sl1ecified by the 8 _bits of
the second word of the instruction set.
This
quantity is operated upon in the execution of the
instruction.
OPERATION CODE
Th~
OVERFLOW
The condition in which the capacity of a register
is exceeded.
PARTIAL ADD
An addition without carries. Accomplished by
toggling each bit of the' augend where the corresponding bit of addend is a "1".
PROGRAM
A' precise sequence of instructions that accomplishes a computer routine; a plan for the solution
of a problem.
Change 1
low&r 2 octill digits of the first word in the
instruction set also called Function Code and
identified by the letter, F. After the code is
translated, it conditions the computer for execution of the specified instruction.
QUARTIC
A number system with a base of four.
These
numbers are normally partitioned into groups of
two for ease of reading.
READ
To place a quantity from a storage location into
a register. The quantity in storage remains
unchanged.
READY
The input/output control signal sent by either the
computer or an external equipment to alert the
device that is to receive a transmission. The
ready signal indicates that the word or character
has been transmitted .
RELATIVE
ADDRESSING
. A mode of addressing wherein the address of
the operand is determined by adding (or subtracting) the contents of the execution address portion
of the instruction word to (or from) the instruction
address.
REPLACE
In the title of an instruction, the result of the
execution of the instruction is stored in the location from which the initial operand was obtained.
RESUME
The output control signal sent by an external
equipment to indicate that it is prepared to receive
another word or character. The resume· signal
is thus a request for data.
(See Input Request.)
ROUTINE
The sequence of operations which the computer
performs under the direction of a program.
SHIFT
To move the bits of a quantity right or left.
SIGN BIT
The bit in the highest-order stage of the register
(in registers where a quantity is treated as
signed by use of one's complement notation).
If the bit is "1", the quantity is negative;. if the
bit is "0", the quantity is positive.'
SIGN EXTENSION
The duplication of the .sign bit an the highest-order
stages of a register.
5
STATUS
1) The condition of an external device, as
reflected in the response given to a status request
interrogation by the computer.
2) The condition of the computer as shown by
the Status Mode indicator on the console. May
variously indicate what it is presently doing, why
it stopped, or what it will do when it next starts.
TRANSMISSION
FORCED
A transmission where both set and clear inputs,
only one of which will be a "1", are simultaneously gated into a F F which has not been
cleared previously.
TRANS LA TIO N
An indication of the content of a group of bit
registers. A complete translation gives the
exact content, while a partial translation indicates
only that the content is within certain limits.
TWO's
COMPLEMENT
That number which results from subtracting each
bit of a number from "0". The two's complement may be formed by complementing each bit
of the given number and then adding one to the
result, performing the required carries.
WORD
A unit of information which has been coded for
use in the computer as a series of bits. The
normal word length is 8 bits.
WRITE
To enter a quantity into a storage location.
6
COMMENT SHEET
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