400083 01_1660_Maintenance_Jul78 01 1660 Maintenance Jul78
400083-01_1660_Maintenance_Jul78 400083-01_1660_Maintenance_Jul78
User Manual: 400083-01_1660_Maintenance_Jul78
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XEROX
Diablo Systems Incorporated
A Xerox Company
HyTerm Communications Terminal
Model1660 '
Maintenance Manual
400083-01 Rev. 8
July, 1978
® Copyright 1978
Diablo Systems, Inc, (A Xerox Company)
Hayward, California 94545
"Diablo," "HyType," and "Xerox" are registered trademarks of Xerox Corporation.
"HyTerm" is a trademark of Diablo Systems, Inc.
PREFACE
This manual contains only Theory of Operation (Section 2) and Maintenance (Section 3)
information, and schematics and logic drawings (Section 4). Refer to the Product
Description manual, no. 400082, for operation instructions, specifications, functional
description, interface information and installation instructions.
This is a preliminary edition. Comments and suggestions on this manual and its use are
welcome. Please complete the pre-addressed comment card bound in the back of this
manual. Your cooperations is appreciated.
Diablo Systems, Inc., reserves the right to make improvements to products without
incurring any obligation to incorporate such improvements in units previously sold.
iii
WARRANTY
The Diablo HyTerm Communications Terminal Model 1641 is warranted against defects in
materials and workmanship for 90 days from the date of shipment. Any questions with
respect to the warranty should be directed to your Diablo sales represenative. All
requests for repairs should be directed to the Diablo repair depot in your area. This will
assure you of the fastest possible service.
iv
TABLE OF CONTENTS
SECTION 1 -- INTRODUCTION
1.1
GENERAL DESCRIPTION •
1-1
1.2
SCOPE •
1-1
1.3
RELATED DOCUMENTS
1-1
SECTION 2 - THEORY OF OPERATION
2.1
INTRODUCTION •
2-1
2.2
PROCESSOR (HPR03) BOARD •
2-3
2.2.1
General Operation
2-3
2.2.2
8080A Microprocessing Unit (MPU)
2.2.3
Clock Generator
2.2.4
Bus Driver/System Controller
2.2.5
Memory.
2-11
2.2.6
Input/Output.
2-14
2.2.7
Miscellaneous Circuitry
2-20
2.3
2.4
.
.
2-5
2-8
.
XMEM (EXTRA MEMORY) BOARD.
2-9
2-20
.
2.3.1
Application
2.3.2
Basic XMEM Board
2-21
2.3.3
XMEM Configurations •
2-21
2.3.4
Addressing
2-21
2.3.5
Additional Applications
2-22
MATRIX INTERFACE BOARD
2-21
.
2-22
2.4.1
I/O Ports 5 and 6 .
2-22
2.4.2
Carriage Position Data
2-24
2.4.3
Carriage Direction Commands
v
.
2-25
2.5
PROCESSOR (PRINTER)
2.5.1
2.6
2-26
Chip Task Assignment •
2-26
CARRIAGE SERVO BOARD
2-29
2.6.1
Digital Sinew ave Generator
2.6.2
Servo Position Transducer
·
2-31
2.6.3
Servo Feedback Amplifier
·
2-31
2.6.4
Servo Feedback Demodulator/Amplifier
2.6.5
Carriage Position Tachometer
2.6.6
Carriage Velocity Command
2-30
.
.
2.7 CARRIAGE POWER AMPLIFIER BOARD
2.8
2.9
2.11
2-35
2-37
2-41
2.7.1
Carriage Power Amplifier Circuit
2-41
2.7.2
Power Monitor Circuit.
2-43
2.7.3
Paper Feed Drive C ircui t
·
MATRIX HAMMER DRIVER BOARD
2-44
2-47
2.8.1
Hammer Driver Circuit
2-47
2.8.2
Hammer Coil Protection Circuit
2-47
2.8.3
Surge Suppression .
2-47
2.8.4
Current Limiting •
2-47
2.8.5
Power Loss Protection.
2-47
POWER SUPPL Y .
2.9.1
2.10
2-33
Detailed Description
2-49
.
KEYBOARD (CORTRON UP/DOWN STROKE)
2-49
2-55
2.10.1
Keyswitch Description.
2-55
2.10.2
Circuit Description
2-55
2.10.3
External Electronics
2-56
KEYBOARD (MICROSWITCH UP/DOWN STROKE)
2-58
2.11.1
General Description
2-58
2.11.2
Internal Logic Description •
2-58
vi
2.11.3
2.12
External Electronics
2-59
CONTROL PANEL
2-61
2.12.1
Operation Mode
2-63
2.12.2
Switches.
2-63
2.12.3
Reading Registers.
2-63
2.12.4
Indicators and Audible Alarm
2-63
SECTION 3 - MAINTENANCE
3.1
3.2
3.3
INTRODUCTION •
3-1
3.1.1
General Rules
3-1
3.1.2
Top Cover Removal/Replacement
3-2
3.1.3
Tools
3-3
PREVENTIVE MAINTENANCE
.
3-3
3.2.1
Supplies.
3-3
3.2.2
Cleaning and Inspection
3-4
3.2.3
Lubrication
.
3-4
MODULE REMOVAL AND REPLACEMENT
.
3-9
3.3.1
Printed Circuit Boards.
3-9
3.3.2
Power Supply.
3-11
3.3.3
Control Panel
3-15
3.3.4
Keyboard
3-16
3.3.5
Printer
.
3-18
3.3.6
Print Head
3-19
3.3.7
Paper Carrier Subassembly.
3-21
3.3.8
Paper Feed Motor.
3-23
3.3.9
Carriage Subassem bly .
3-25
3.3.10
Carriage Drive System.
3-28
3.3.11
Mother Board.
3-33
vii
3.4
3.5
ADJUSTMENTS
.
3-34
3.4.1
Printer Quality Testing
3-34
3.4.2 .
Printer Adjustments
3-36
3.4.3
Control Panel Alarm Volume Adjustment.
3-48
3.4.4
Power Supply Adjustment
3.4.5
Cover-Open Switch Adjustment.
3-50
3.4.6
Paper-Out Switch Adjustment
.
3-50
.
3-48
COMPONENT IDENTIFICATION
3-51
3.5.1
Reference Designator System
3-51
3.5.2
Coordinate System
3-51
3.5.3
Pin Numbering
3-53
SECTION 4 - SCHEMATICS AND REFERENCE INFORMATION
4.1
INTRODUCTION
4-1
4.2
FUNCTIONAL LOGIC.
4-1
4.3
SIGNAL NOMENCLATURE.
4-2
4.4
LOGIC SYMBOLOGY •
4-2
4.5
INTEGRA TED CIRCUITS
4.6
ASCII CODE CHART •
4.7
SCHEMATICS AND LOGIC DRAWINGS
.
4-2
4-62
viii
.
4-62
LIST OF ILLUSTRATIONS
FIGURE
PAGE
1-1
Model 1660 Hyterm Communications Terminal
1-0
2-1
Model 1660 Hyterm System Block Diagram
2-0
2-2
Block Diagram, HPR03 Board
2-2
2-3
Typical Instruction Cycle (Output Instruction).
2-6
2-4
MPU Instruction Format
2-7
2-5
MPU Status and Resultant Control Signals
2-9
2-6
Memory Map.
2-12
2-7
Memory Timing
2-13
2-8
MXI Board Block Diagram •
2-23
2-9
Track Crossing Detection Logic.
2-24
2-10
Track Crossing Detection Waveforms
2-25
2-11
Processor Simplified Block Diagram .
2-26
2-12
Carriage Servo Block Diagram •
2-29
2-13
Digital Sinewave Generator
2-29
2-14
Digital Sinewave Generator Waveforms •
2-30
2-15
Servo Postion Transducer
•
2-31
2-16
Servo Feedback Amplifier •
2-31
2-17
Servo Feedback Amplifier Waveforms
2-32
2-18
Servo Feedback Demodulator/Amplifier •
2-33
2-19
Servo Feedback Demodulator/Amplifier Waveforms
2-33
2-20
Waveform Analysis
2-34
2-21
Carriage Position Tachometer
2-22
Carriage Position Tachometer Waveforms
2-36
2-23
Carriage Position FET Input Waveforms .
2-36
2-24
Carriage Velocity Command Circuits
2-38
.
.
ix
2-35
2-25
Ribbon Motion Sensor •
2-38
2-26a
Carriage Power Amplifier Simplified Diagram
2-40
2-26b
Carriage Power Amplifier
2-27
Simplified Feedback Circuit
2-42
2-28
Power Monitor Circuit.
2-43
2-29
Paper Feed Drive C ircui t
2-30
Paper Drive Waveforms
2-45
2-31
Typical Stepping Motor Rotation
2-45
2-32
Typical Hammer Driver and Common Protection Circuits
2-46
2-33
Power Supply Block Diagram
2-48
2-34
Simplified Input Rectifier/Filter/Doubler Section
(115 VAC Input Strapping)
2-49
Simplified Input Rectifier/Filter/Doubler Section
(230 VAC Input Strapping)
2-50
2-36
Simplified Transistor Chopper (Half-Wave)
2-50
2-37
Power Supply Waveforms
2-51
2-38
Control Module Block Diagram .
2-52
2-39
Control Module Timing Diagram
2-52
2-40
Key Position Layout
2-56
2-41
Keyboard Timing Diagram •
2-60
2-42
Block Diagram, Control Panel
3-0
Hyterm with Top Cover Removed
3-0
3-1
Carrier System Lubrication Points
3-5
3-2
Carriage System Lubrication Points •
3-6
3-3
Platen System Lubrication Points
3-7
3-4
Circui t Board Locations
3-8
3-5
Power Supply Mounting
3-10
3-6
Power Supply Connections •
3-11
.
2-40
.
2-44
·
2-35
·
·
x
2-62
3-7
Control Panel Connections •
3-14
3-8
Carrier System Removal - A
3-20
3-9
Carrier System Removal - B
3-20
3-10
Carrier System Removal- C
3-20
3-11
Carrier System Replacement
3-22
3-12
Paper Feed Motor Removal/Replacement
3-22
3-13
Carriage Drive Pulley Removal.
3-24
3-14
Ribbon Drive Cable Replacement
3-26
3-15
Carriage Drive Cable Tension Spring.
3-28
3-16
Carriage Drive Cable Routing
3-17
Right Hand Carriage Drive Cable Installation.
3-30
3-18
Carriage Drive Cable Tension Spring Assembly
3-30
3-19
Mother Board Connections •
3-32
3-20
Dot Matrix Character Edge Variation
3-35
3-21
Carrier Assembly Adjustment Points.
3-36
3-22
Paper Feed Adjustment Points
.
3-37
3-23
Platen Drive Adjustment Points.
3-38
3-24
Front Guide Bearing Adjustment Points
3-25
Platen-to-Print Head Adjustment Tool Installation.
3-40
3-26
Platen-to-Print Head Adjustment Points •
3-41
3-27
Variable Adjust Platen Knob's End Play Adjustment
3-42
3-28
Carriage Drive Cable Adjustment
3-43
3-29
Ribbon Drive Cable Adjustment.
3-43
3-30
Ribbon Drive Gear Adjustment •
3-44
3-31
Paper Clamp Adjustment
3-45
3-32
Bottom Feed Paper Chute Adjustment
3-46
3-33
Control Panel Alarm Volume Adjustment.
3-48
3-34
Paper-Out Switch Adjustment
3-51
.
xi
3-29
.
3-39
3-35
Circuit Board Component Location and Pin Numbering.
3-36
Sem iconductor Lead Identification
3-37
Control Panel Assignment Table
3-56·
3-38
Keyboard Cable
3-57
3-39
EIA Cable Pin Identification
3-58
4-1
Examples of Functional Logic
4-1
4-2
ASCII Code Chart.
4-63
4-3
Logic Drawing Notation
4-64
.
3-52
3-54
LIST OF TABLES
2-1
I/O Ports
2-15
2-2
Voltage/Current Levels
2-53
2-3
Cortron Key Position Numbers and Position Codes.
2-57
2-4
Micro Switch Key Position Numbers and Position Codes
2-60
2-5
I/O Interface Connections •
2-61
3-1
Major Asse.mblies and Modules .
3-9
3-2
Reference Designators.
3-53
3-3
Keyboard Signal Names
3-55
4-1
Integrated Circuits
4-3
4-2
Schematic and Logic Drawing Index .
4-62
xii
Figure 1-1. Model 1660 HyTerm Communications Terminal
1-0
Section 1
INTRODUCTION
1.1
GENERAL DESCRIPTION
The Diablo Model 1660 HyTerm Communications Terminal (see Figure 1-1) combines the
field-proven Series 2300 Matrix Printer with 1) an integral power supply, 2) additional
microprocessor control and Read-Only Memory/Random Access Memory (ROM/RAM), and
3) an Electronic Industries Association RS-232-C interface, to produce a fully-contained
data communications terminal that is similar in size and mobility to the ordinary widecarriage office typewriter. In the local mode of operation, the Model 1660 HyTerm will
serve as a desktop document writer for correspondence and other secretarial functions.
When used as a data communications terminal, the Model 1660 HyTerm transmits and
receives asynchronous serial data over a communications link from a distant computer or
data terminal. In this remote mode of operation, the Model 1660 HyTerm may also be
used as a computer console or similar I/O device for data entry and data editing. In
addition, the Model 1660 HyTerm is ideally suited for computer applications where a hardcopy printout is required on multi-copy forms.
The Model 1660 HyTerm utilizes a 9-wire print head and serial impact to construct
characters in a 7 x 9 dot matrix. The matrix printer is capable of printing characters at a
maximum speed of 200 characters per second (cps). The microprocessor control and
ROM/RAM memory facilitate such features as motion accumulation, high speed horizontal
and vertical tabbing, automatic reverse line printing, and complete local and remote
control of all printer functions.
SCOPE
1.2
This manual provides information on theory of operation, maintenance, and module
replacement.
It also includes data covering the electronic components used and
explanations of the logic symbology and drawing conventions used. It does not include
operating instructions, installation procedures, or information on the functional operation
of the HyTerm; these are all contained in the Product Description manual listed in the
related documents.
RELATED DOCUMENTS
1.3
(1)
HYTERM COMMUNICATIONS TERMINAL MODEL 1660, PRODUCT DESCRIPTION. Diablo Systems, Inc. Publication No. 400082-01.
(2)
SERIES 2300 MATRIX PRINTER PARTS CATALOG.
Publication No. 82414-01.
(3)
INTERFACE BETWEEN DATA TERMINAL EQUIPMENT AND DATA COMMUNICATION EQUIPMENT EMPLOYING SERIAL BINARY DATA INTEREIA Standard RS-232-C, August, 1969.
Engineering Dept.,
CHANGE.
Electronic Industries Assn., 201 Eye St. N. W., Washington, D.C. 20006.
(4)
AMERICAN STANDARD CODE FOR INFORMATION INTERCHANGE. USAS
X3.4-1977. American National Standards Institute, 1430 Broadway, New York,
N. Y. 10018.
1-1
Diablo Systems, Inc.
(5)
DATA SET 103A INTERFACE SPECIFICATION. February, 1967, Engineering
Director, Data Communications, American Telephone and Telegraph Co.
Publication 41101.
(6)
DATA SET 202C and 202D INTERFACE SPECIFICATION. May, 1964,
Engineering Director, Data Communications, American Telephone and Telegraph Co., Publication 41202.
(7)
Data Set 212A Interface Specification. October, 1976.
Special Services, American Telephone and Telegraph Co.
(8)
C.C.I.T.T. GREEN BOOK, VOL. VIII, DATA TRANSMISSION, 1973. The
International Telephone and Telegraph Consultative Committee, International
Telecommunication Union, Geneva, Switzerland.
1-2
Director, Data and
COVER
OPEN
SWITCH
~I
HAMMER DATA 1-9
EIA
INTERFACE
t'J
POWER-oN
~
HAMMER
HAMMER
~
PRINT
HEAD
DRIVER
PCB
( H)
CTRl I
CTRl
IOATA
-
CONTROL
READ
WRITE
CONTROL
PANel
~
~
TERMINAL
MICROPROCESSOR
HPR03
STROBE
FUNCTION
SELECT
K
I
Q
INSTRUCTIONS
DATA)
PRINTER
INTERFACE
MXI
MICROPROCESSOR
"
~\I
~I
PROCES SOR
SYS ClK
KEYBOARD
DATA
FUNCTIONS
STATUS & CTRl
CARRIAGE
PoS.
:
I
I
I
L __ ~I ___
1
STATOR
0
:p
CARRIAGE
PDS
fEEDBACK
I
I
II
SERVO OISA
DATA
SERVO
tCI
I
ERROR
ROTOR
CARRIAGE
DRIVE
MOTOR
PAPER FEED CTRl
CA"'AGER
POWER
I
XMEM
CARRIAGE
SERVO
IBI
iilltB,
I
~
CARRIAGE
CONTROL
IAI
lEI
DATA
PAPER
OUT
SWITCH
l
AMP
I
RIBBON
MOTION
SENSOR
J
CARRIAGE
HOME
SENSOR
PAPE'R FEEO
DRIVE
MOTOR
tol
083-001
Figure 2-1. Model 1660 HyTerm System Block Diagram
Section 2
THEORY OF OPERATION
2.1
INTRODUCTION (Figure 2-1)
The 1660 employs two separate, asynchronous, processing systems. One, called the
"printer microprocessor," is an integral part of all HyType printers. The other, called the
"terminal microprocessor," provides the additional functions that transform a matrix
printer into a 1660 communications terminal.
The terminal microprocessor, located on the HPR03 board, controls the overall terminal
functions of sending and receiving data over the EIA interface, receiving data from the
keyboard, and monitoring the control panel. It also communicates with the printer microprocessor, contained on the PROCESSOR board. This second microprocessor system
initiates movement of the printer carriage and paper feed drive motor, and it monitors
feedback from the carriage position circuit to effect proper execution of these motion
commands. It also issues hammer-fire instructions to the hammer driver board, it
provides printer status information to the terminal microprocessor, and it performs other
"housekeeping" functions.
The XMEM board is not part of all 1660 terminals. It is used during engineering
development, in early production models, and for options when requirements exceed the
memory available on the HPR03 board.
The MATRIX INTERFACE board is located logically between the two microprocessors. It
provides temporary storage for data and status information, and synchronizes the transfer
of data from the terminal microprocessor to the printer microprocessor, and the transfer
of status information back. It also contains some control logic for the servo feedback
system.
The CARRIAGE SERVO board receives the carriage motion commands from the printer
microprocessor in digital form and converts these to analog signals represenatitive of the
distance and direction to be moved. These servo "error" signals are passed on to the
carriage power amplifiers, which drive their respective servo motors. Feedback signals,
derived from the carriage rotary transducers, are amplified and passed on to the MATRIX
INTERFACE board. Here they are available to the printer microprocessor, which uses
them to regulate the error signals.
The HAMMER DRIVER board provides nine identical driver circuits for driving each of the
nine print head hammers and a hammer protection circuit.
The CARRIAGE POWER AMPLIFIER drives the carriage servo motor and the paper feed
step motor. It also monitors the input voltages and develops the POWER ON signal to
initiate the Restore operation.
2-1
-RD
-WR
"DAf
~ PANEL
CTRL
+017
PORT 3
ADDR ,
ADDR I
+HOLD
I···........··,
llllllllll!l!
+ADDR •
..
.,;,;,;,;,;,;,;r
-)(INTR
8--1
_ _ A.
IJ21
,"\."\."\."\."\.W
L
RAM
I
I ..
P" __
~
I
II
-
•
r."\."
T/n
L1
+ADtR 15
!I~I ~"TlnN
~
PORT
2
........ R
PORT4DMA
1:}
PORT7
PRTRt MOTHER
BOARD
IPII
+DA'
~ u:~;~'
to.:)
I
to.:)
-BUS EN
IHI
t
+DA7
if
....,
INPUT
LEVEl
CONVERTER
DATA
,:" [
-MEMR
-MEMW
-READ
- -WRITE
+HLDA
~ RS-232
IJII
FUNCTION
r-I
+KYSTB
1Lr:;-)
OUTPUT
LEVEL
INTR
Figure 2-2. Block Diagram, HPR03 Board
2.2
PROCESSOR (HPR03) BOARD, PART NO. 23924-XX (Figure 2-2)
The HPR03 board contains the terminal microprocessor system. This includes the 8080A
Microprocessing Unit (MPU), Memory, several Input/Output (I/O) ports, the Universal
Synchronous/Asynchronous Receiver/Transmitter (USART) and its associated RS-232
interface components, and all control electronics.
NOTE
Throughout this manual, two terms will be used extensively:
terminal microprocessor refers mainly to the entire HPR03
circuit board, whereas MPU refers to the 8080A integrated
circuit.
2.2.1
General Operation
The terminal microprocessor is actually a miniature computer. It receives its instructions
from Read Only Memory (ROM), either locally or located on the XMEM board. These
instructions are arranged to form a "microprogram." As it executes this microprogram,
the MPU receives data from the various input ports and stores it in memory, or reads data
out of memory and sends it to the various output ports. Between input and output
instructions, the MPU may perform other operations on the data, make logical decisions
concerning the data, or "jump" to a different portion of its program.
2.2.1.1
Input/Output
Data can enter or leave the HPR03 board via any of four channels. First, in the case of
the keyboard, data enters the board over the "keyboard data bus" and is held in Port 2
until the MPU is ready for it. Then the MPU "reads" the data from Port 2, and the data is
transferred to the MPU over the bidirectional data bus.
Second, data may enter (or leave) over the EIA interface, and be held temporarily in the
USART (Port 0). The data is transferred between the MPU and the USART over the
bidirectional data bus.
Third, data may enter or leave the board over the 8-bit bidirectional data bus through the
J2 connector (normally used for the control paneI). In this case, an "I/O port" or its
equivalent must be located on another board cable-connected to the HPR03 board via J2.
This port is addressed as Port 3.
Fourth, data may enter or leave the board over the 8-bit bidirectional data bus through
the mother board connector (PI). Again, an I/O port of some type must be located on
another circuit board plugged into the printer mother board. The port must be addressed
as Port 4, 5, or 6.
In this fourth case, the data transfer can be either between the MPU and the external
port, or it can be directly between the memory and the external port, bypassing the MPU.
If direct memory access is used, the external port or device must provide the necessary
signals to delay, or "hold," the MPU while the data transfer is taking place.
Note that the MPU can also address Port 1 for either input or output. This port, however,
is contained fully on the HPR03 board, and does not transfer data onto or off the board.
It is used for local control of the baud rate and interrupt enable/disable, and to monitor
interrupt status.
2-3
When the XMEM board is supplied, it is addressed in the same manner as HPR03 internal
memory via address lines on the mother board. Data is also transferred via the mother
board.
2.2.1.2
Interrupts
The normal microprogram instruction sequence can be interrupted when necessary to
enable the transfer of data to or from an I/O device, or for other purposes. Generally,
when an interrupt occurs, the MPU completes the instruction it is presently performing,
and then jumps to its interrupt servicing routine, which begins at memory location 0056 •
10
This routine first determines what type of interrupt is occurring, and then performs
the steps necessary to service the interrupt.
If two or more interrupts occur
simultaneously, the interrupt service routine in the microprogram determines which will
be serviced first.
There are five types of interrupts, all of which can be individually enabled or disabled by
the microprogram. The first four types can be independently enabled or disabled on the
HPR03 board, whereas the last type (external) must be disabled on the circuit board on
which it is initiated (some external circuit board). The five types of interrupts are as
follows:
(1)
USART receive:
the USART has received a character from the data link
and is waiting to transfer it to the MPU.
(2)
USART send:
the USART has shifted a character out to the data link
and is ready to accept a new character from the MPU
for transm ission.
(3)
Keyboard:
a data character has been received from the keyboard
(or parallel data interface) accompanied by a strobe,
and is waiting to be read by the MPU.
(4)
Real-Time Clock:
the Real-Time Clock has timed out, denoting that 10 ms
has elapsed since it was activated.
(5)
External:
an interrupt can be generated by logic on a different
circuit board and applied to the HPR03 board via the
- XINTR input.
2.2.1.3
Memory
Either random-access memory (RAM), read-only memory (ROM), or erasable read-only
memory (EROM) ICs (or all three) may be used. Maximum capacity of the HPR03 board is
4K bytes of ROM, 1K of EROM, and 512 bytes of RAM. Additional memory on the XMEM
board can be utilized by placing the necessary address on the memory address bus; data is
transferred over the bidirectional data bus.
2.2.1.4
Real-Time Clock
A 10-ms one-shot is used as a real-time clock, to allow the MPU to pole various I/O ports
(eg, the control panel) at regular intervals.
2-4
2.2.1.5
Special Voltage Supplies
The HPR03 board also contains local voltage regulators to convert the ± 15V from the
main power supply to ± 12V and -5V needed by the EIA interface, some of the memory ICs,
the MPU, and some external circuits and devices.
2.2.2
8080A Microprocessing Unit (MPU)
The 8080A is an 8-bit microprocessor contained in a single 40-pin integrated circuit (IC)
package. It has an 8-bit wide bidirectional data bus used for both input and output. It has
a 16-bit address bus, capable of addressing up to 65,536 memory locations. The MPU's
instructions are located in memory, from where they are fetched and executed
sequentially. There are over 100 separate instructions possible, although many are
similar, the difference being only in the various MPU internal registers specified.
2.2.2.1
Architecture
To understand the operation of the terminal microprocessor, it is only necessary to know
that the MPU contains an instruction register, a program counter, a memory address
register, a stack pointer, and other registers and logic elements. The instruction register
contains the 8-bit instruction op code. The program counter contains the 16-bit memory
address of the next instruction to be fetched. The memory address register is made up of
two 8-bit registers, referred to as the Hand L register pair. It is used to address memory
for memory read and memory write instructions. Other internal MPU registers can also
be used to address memory. The stack pointer is generally used to "remember" the
address of the next sequential main program instruction while an interrupt subroutine is
being executed. Still other elements internal to the MPU perform the arithmetic and
logic operations and control the input and output over the data bus.
This is admittedly a very brief description of the MPU architecture, but this background
should be sufficient to allow understanding of the material to follow. Further information
on the MPU can be found in the integrated circuit information presented in the
Schematics/ Reference section of this manual.
2.2.2.2
Timing
Timing is controlled by two 12V (nominal) non-overlapping clocks,
are provided at a frequency of 2 MHz by a Clock Generator IC.
2.2.2.3
~1
and
~2.
These clocks
Basic Processor Operation
MPU operation is divided into time periods called "cycles" and "states." There are two
types of cycles: instruction cycles and machine cycles. The material that follows is
summarized in the timing chart in Figure 2-3.
2-5
A.
Without WAIT State
I
f-...
4t---------
INSTRUCTION
M2
T2
Ml
TZ
TI
T4
T3
TI
.. I....
CYCLEn
M3
T2
TI
T3
T3
INSTRUCTION
CYCLE n+l
Ml
T1
T2
11
12
+ A 15- 0 -+------J
+ 0 7- 0
....1.....---.-..1
+SYNC
+0 BIN -+--_-+----J
-WA
STATUS
INFORMATION
B.
*
+----1
CD
8
With WAIT State
INSTRUC
INSTRUCTION CYCLE n - - - - - - - - - - -...........f-- CYCLE r
T1
T2
Tl
T4
T3
T2
I
M3
M2
Ml
TW
TW
Tl
T3
TW
T2
T3
Ml
Tl
T2
Jl f'L-1""'--If'L- ~ ~""- """---~ ~ ""- ""--~ ""'-- ~ ~
J2 L--J'-\ ~ LJ-\ LJ-\LJ-\ ~ ~ ~ ~ LJ-\ ~ ~ ~ LJ-\U
+ A15-0 ~
+07-0
~
+SYNC
~
,
'- ---- -
BYTF
\UNKNOWNI
BYTE
ONF
I
--'
- ---FLOA TlNG
-
-,
TWO
\
-
--~~
-
--
I
-- -
X'
--
I
1/0
!lFVICF
X
NUMBFR
X
ACCUMUlA fOR
+ OBIN
+READY fWAIT
*
-
-
\
'"-
-WR
STATUS
INFORMATION
X
\
/(j)
X0
X®
*Numbers in circles refer to types of machine cycles.
Figure 2-3. Typical Instruction Cycle (Output Instruction)
2-6
J
rti
2.2.2.3.1
Instruction Cycle. An instruction cycle includes both the fetching of the
instruction from memory and the execution of the instruction. Each instruction may
contain one, two, or three 8-bit bytes. Multiple byte instructions must be stored in
successive memory locations. Figure 2-4 illustrates the three instruction formats. The
actual bit configuration of the op code is not important to the understanding of the
terminal processor operation.
One Byte Instructions
I
D7
I
D6
I
D5
D4
D3
D2
D1
DO
OP CODE
Two Byte Instructions
D7
D6
D5
D4
D3
D2
D1
DO
OP CODE
D7
D6
D5
D4
D3
D2
D1
DO
DATA or
ADDRESS
Three Byte Instructions
D7
D6
D5
D4
D3
D2
D1
DO
OP CODE
D7
D6
D5
D4
D3
D2
D1
DO
DATA or
D7
D6
D5
D4
D3
D2
D1
DO
ADDRESS
Figure 2-4. MPU Instruction Format
2.2.2.3.2
Machine Cycle. A machine cycle is required each time an I/O array or the
memory is accessed. Each instruction cycle can contain from one to five machine cycles.
There are ten different types of machine cycles possible, as follows:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
Instruction Fetch
Memory Read
Memory Write
Stack Read
Stack Write
Input
Output
Interrupt Acknowledge
Halt Acknowledge
Interrupt Acknowledge While in Halt
2.2.2.3.3
States. A state is defined as the time interval (500 ns) from leading edge to
leading edge of the ~1 clock. There are 6 possible states, numbered T1 through T5 and TW
(representing "wait"). All machine cycles include T1, T2, and T3. When the jumper wire is
installed between pins 24 (WAIT) and 23 (RDY) of the 8080A, TW follows T2. This is to
slow down the MPU so that slower memory les may be used. T4 and T5 are omitted
during execution of instructions not requiring them.
2-7
2.2.2.3.3.1 Tl. During state Tl either a memory address or an I/O port number is placed
onto the memory address bus. Also, the MPU places eight bits of status information on
the data bus which identify the type of machine cycle being performed. Following the
rising edge of ~2 the SYNC signal is produced by the MPU, which identifies the beginning
of a machine cycle. See Figure 2-3.
2.2.2.3.3.2 T2. During state 2 the MPU monitors its RDY input. If it is high, the MPU
goes on to state 3; if it is low, the MPU goes on to the Wait state.
During machine cycles that bring data into the MPU (Instruction Fetch, Memory Read,
Stack Read, Input, and Interrupt Acknowledge), the Data Bus In signal, DBIN, is developed
at ~2 during T2. DBIN remains high through TW and into T3. This signal develops -READ
and -MEMR at the proper time to provide the input data needed by the MPU. (This is
covered more fully in 2.2.4.)
2.2.2.3.3.3 TW.
The wait state provides the MPU delay required for proper memory
access. No internal processing occurs during this state. The MPU monitors its RDY input,
and if it is low, it remains in the Wait state; if it is high, the MPU goes on to state 3. If
the RDY input is connected to the WAIT output, the MPU goes on to T3 after one state
time (500 ns) in TW.
During machine cycles in which the MPU outputs data (Memory Write, Stack Write,
Output), it develops the WR (Write) signal during TW or T3 and holds it low until after the
end of T3. This signal is used by other logic on the HPR03 board or another board to
strobe the output data to memory or to the selected output port.
2.2.2.3.3.4 T3.
During state T3 the data or instruction byte is actually transferred
between the MPU and memory or an I/O port. The source and destination of the byte is
determined by the type of machine cycle being performed. For example, during an
instruction fetch cycle, the source of the data (instruction byte) is the memory location
addressed during state 1; the destination is the MPU. During an Output machine cycle,
the source is the MPU and the destination is the I/O port selected (addressed) in state 1.
2.2.2.3.3.5 T4 and T5. These two states are used only when required for manipulation of
data within the MPU.
2.2.2.3.4
Hold. When the +HOLD signal goes high, it causes the MPU to stop operation
at the end of the instruction currently being executed. This is used during direct memory
access; when DMA is not used, the +HOLD line is held low by a jumper wire to GND.
2.2.3
Clock Generator (8224)
The clock generator is contained in a single integrated circuit that provides several
functions. First, it provides the two non-overlapping 12V signals, ~1 and ~2, required by
the MPU. The frequency of these signals (2 MHz) is controlled by an external quartz
crystal. A TTL equivalent of the ~2 signal, +T~2, is also developed for use in timing other
functions.
Second, the 8224 converts the MPU's SYNC signal into the Status Strobe signal, STSTB.
This signal is used to load the status information, put out by the MPU at the beginning of
each machine cycle, into the Bus Driver/System Controller IC. This is covered more fully
in 2.2.4.
2-8
Third, at power-on, the clock generator IC develops +CLR, which is used to reset and
initialize the entire HPR03 board.
The 8224 has other capabilities not utilized by the terminal microprocessor.
2.2.4
Bus Driver/System Controller (8228)
This module is another single IC that performs three basic functions: bidirectional bus
control, system logic control, and initial interrupt request processing.
TYPE OF MACHINE CYCLE
I
CD ®
® ®
@
@
Do
INTA
0
0
0
0
0
0
0,
WO
1
1
0
0
1
02
03
04
STACK
0
0
0
1
0
0
0
0
0
0
0
0
0
OUT
0
0
0
1
1
0
0
0
0
0
1
Os
M,
1
INP
0
0
0
0
0
0
06
07
1
MEMR
1
1
0
0
HLTA
0
0
0
0
0
1
(j)
CV ®
@
1
0
1
1
1
0
0
1
0
0
0
0
1
1
0
0
1
0
1
0
0
0
0
0
1
0
0
-
INTA
(NONE)
INTA
I/OW
I/O R
MEMW
MEMR
MEMW
MEMR
MEMR
~
-
Figure 2-5. MPU Status and Resultant Control Signals
2-9
CONTROL
SIGNALS
2.2.4.1
Bus Control
The 8228 provides a buffer between the MPU and the memory and I/O ports. Controlling
the two 8-bit data buses on the HPR03 board involves not only switching the data on and
off in the proper direction at the right time, but also in providing the required voltage and
current levels. Since the MPU is an MOS device, it requires a voltage of at least +3.3
volts for a "logic 1" or "true" indication on its data inputs. The 8228 provides a minimum
of +3.6 volts on the 8080 Data Bus, which is substantially higher than can be guaranteed by
standard TTL devices. For output data, the MPU can provide only 1.9 rnA of current
drive. With many I/O ports and the memory connected to the bidirectional data bUS, this
value could easily be exceeded, so the 8228 is used to provide over 10 rnA to satisfy this
requirement. The buses can be "turned off" (forced into the high-impedance state) when
direct memory access is used. See 2.2.4.4. The direction of data flow on the buses is
controlled internally by the same signals that furnish the system control function
performed by this IC.
2.2.4.2
System Logic Control
At the beginning of each machine cycle, the MPU issues "status" information on the 8080
data bus that indicates the type of cycle about to be performed. At the same time, the
clock generator module develops STSTB, which loads this status information into a status
latch inside the 8228. This status latch output is decoded, along with DBIN, WR, and
HLDA (Hold Acknowledge) from the MPU, into the system control signals MEMR
(Memory Read), MEMW (Memory Write), READ (I/O READ), and WRITE (I/O WRITE).
(These decoded signals also provide the internal control of the bus driver.) Note that
these signals are not levels, but that they are gated by DBIN or WR from the MPU at the
proper time. The status information provided by the MPU, and the system control signals
developed for each of the ten types of machine cycles are shown in Figure 2-5.
2.2.4.3
Interrupt Handling
The 8228 is capable of handling interrupts in either of two different ways. Only one of
these methods is used in this terminal, in which the Interrupt Acknowledge pin (23) is
connected to +12V through a resistor. ,Connected this way, when the MPU is interrupted
(by an input from the keyboard or USART, for example), it performs an INTERRUPT
ACKNOWLEDGE machine cycle, and the 8228 automatically forces an RST 7 (Restart 7)
instruction into the MPU. This instruction causes the MPU to fetch its next instruction
from memory location 56 , which begins the routine needed to service the interrupt.
10
2.2.4.4
Direct Memory Access
The BUS ENable input (pin 22) must be low for normal operation. When direct memory
access is used, the DMA circuitry on another board drives this signal high, forcing all 8228
outputs into their high-impedance state. This allows the bidirectional data bus and the
MEMR and MEMW signals to be controlled by the DMA logic. If the DMA feature is not
used, -BUS EN is held low by a jumper wire to GND.
2-10
2.2.5
Memory
Maximum memory capacity of the HPR03 board is 4K ROM, 512 bytes of RAM, and 1K of
EROM. ROM memory consists or one or two 2K x 8-bit mask-programmed ROM ICs
containing the terminal microprogram. RAM memory consists of two 256 x 4-bit ICs for
each 256 bytes. The EROM portion can be either a 512 x 8-bit or 1K x 8-bit EROM IC.
The EROM would normally contain keyboard position encoding data or similar data for
terminals built in small quantities-too small to justify masked-ROM changes. When the
XMEM board is supplied, the terminal microprogram can be stored there. See paragraph
2.3.
2.2.5.1
Addressing
The memory map in Figure 2-6 shows the relationship of the various memory elements to
their addresses.
The memory les on the HPR03 board are addressed by the lower-order bits of the memory
address bus. The higher-order bits A9, A10, All, A14, and A15 are used to select, through
a decoder, whether RAM, ROM, or EROM will be addressed. In the case of RAM, the
state of the A8 line determines which pair of les will be addressed. For ROM, the All
line selects which of the two possible les will be used. (Note that All goes to both ROM
les; the internal programming of the les is such that one of the ICs will be activated when
All is low and the other when All is high.)
Since the memory address bus is available on the HPR03 board outputs, external memory
can assume any memory address, so the terminal designer must assure that only one
memory location exists for each address. For example, during program development, the
microprogram can be contained in external memory beginning at location 0000. In this
case, the HPR03 board cannot have ROMs installed. After the microprogram is
perfected, it can be "burned" into masked ROMs, which can be installed on the HPR03
board, and the external memory board can be eliminated.
The memory address bus being available on the HPR03 board's plug also enables the entire
memory to be addressed from and external source, as is the case when the DMA function
is utilized.
2.2.5.2
Reading
All memory les are three-state devices. This means that the outputs remain in the highimpedance, or "off" state, at all times when the Ie is not selected. (This allows the
memory address bus to be used for addressing I/O devices; the address lines can assume
any configuration, but there will be no input to or output from memory without the proper
system control signals.) The MEMR signal is connected to the "output disable" input of
the RAMs (pin 9). This maintains the RAM outputs in their high-impedance state at all
times other than during a memory read. MEMR is also one of the inputs to the memory
type decoder. This allows ROM and EROM to be selected only during a read operation.
2-11
XMEM
HPR03
0000
0000
EROMl
ROMl
2K
lK
03FF
0400
EROM2
07FF
07FF
OBOO
0800
lK
EROM3.
ROM2
2K
lK
OBFF
OCOO
EROM4
OFFF
1000
lK
OFFF
EROM5
4000
KYBD
512 - - - - -41FF
-or
ROM
1K
43FF
ROM3
13FF
1400
EROM6
1800
ROM4
NOT
1K
17FF
EROM7
USED
lK
1K
lBFF
1COO
EROMe
lK
1FFF
8000 RAMl 80FF 512
8100 RAM2 81FF
512 8200 RAM3 82FF
8300 RAM4 83FF
8400 RAM5
RAM6
1K
RAM 7
RAM8 87FF
FFFF
NOTES:
1.
2.
First 4K can be either ROMS on HPR03 or EROMS on XMEM.
Second 4K can be either ROMs or EROMs on XMEM.
Figure 2-6. Memory Map
2-12
2.2.5.3
Writing
When memory write is performed, the RAM output remains disabled (MEMR is high), and
MEMW being low allows information on the bidirectional data bus to be written into the
addressed RAM location. Note that each pair of RAMs operates in parallel, one Ie
servicing the low-order four bits of the bidirectional bus, and the other taking care of the
high-order four bi ts.
2.2.5.4
Timing
Typical idealized timing waveforms are shown in Figure 2-7. Specific timing requirements
for each of the memory Ie types can be found in the Ie information in the schematic/reference section. In all cases, the timing shown in Figure 2-7 is within the timing
constraints of the individual les.
+AO-A 15
(ADDRESS)
-------
+DBIN
\
\
-MEM R
DATA
AVAILABLE
111111/ '1/////II////I!J
--..
+AO-A 15
(ADDRESS)
500ns
--
I
DATA OUT
B. WRITE
-WR
-MEM W
A. READ
\
Figure 2-7. Memory Timing
2-13
2.2.5.5
Direct Memory Access
When the DMA function is utilized, it conforms to the following general sequence:
(1)
DMA circuitry on another board raises the +HOLD line to the MPU.
(2)
The MPU finishes the instruction it is presently performing, and then raises
its HLDA (Hold Acknowledge) line. It then suspends operations, and holds all
data and address lines in their high-impedance state.
(3)
The DMA circuitry receives the hold acknowledgement and drives -BUSEN
low. This forces the 8228 to place all of its outputs, both data and control
signals, into their high-impedance state.
(4)
The external DMA circuitry then places the desired address on the memory
address bus, and drives either -MEMR or -MEMW low. The data is then
transferred over the bidirectional data bus.
When the DMA circuitry is finished, it raises -BUSEN and lowers +HOLD, and
the MPU resumes processing at its next sequential instruction.
(5)
2.2.6
Input/Output
The terminal microprocessor can address up to eight I/O ports. These ports, or "devices,"
such as keyboard, control panel, etc., are addressed over the Memory Address Bus, and
data is transferred to and from the MPU over the bidirectional data bus. An I/O channel
or device is first addressed by the MPU, which then develops the -READ or -WRITE signal
to transfer the data. On output, for example, the MPU first addresses a particular output
device, then places the output data on the bidirectional data bus, and finally develops
- WRITE. Although the data is available to all "devices" on the bus, only the one that had
been addressed can accept the data. Input is similar: only the addressed device places
data onto the bus. All other devices are "observers."
The five low-order bits of the memory address bus are used for I/O device selection. Bits
2, 3, and 4 are applied to a decoder, the outputs of which (-PORT" through -PORT 6) are
used to select one of the seven possible ports. Each port can comprise up to four 8-bit
bytes, and bits 0 and 1 are used to select one of the four bytes.
Three of the seven possible I/O ports are located on the HPR03 board. The rest of the
ports mayor may not be used in a particular terminal or printer. The possible ports and
their typical functions are as shown in Table 2-1.
2.2.6.1
USART (Port 0)
The type 8251 USART (Universal Synchronous/Asynchronous Receiver/Transmitter) Ie
accepts an 8-bit byte of data from the MPU in parallel format and converts it to a serial
stream of data for transmission over the communications link. Similarly, it receives data
characters from the link in serial format and converts them into parallel data bytes for
the MPU. During transmission, the USART adds start, stop, and parity bits. During
reception, it strips these bits and also checks parity, if desired. It also checks for data
framing errors and overrun errors, and can monitor modem status. It has other
capabilities that are not generally used (synchronous transmit/receive, character lengths
down to 5 bits, etc.).
2-14
Table 2-1. I/O Ports
Port
No.
Function
0
USART
1
Baud Rate, Interrupt
Enable/Disable & Status
2
Keyboard
3
Control Panel
4
DMA
2.2.6.1.1
Addressing. The CS (Chip Select) input is driven low whenever the MPU
addresses Port O. No information can be transferred between the USART and the MPU
until the USART is selected.
The USART also has a C/D input, which is connected to the +ADDR f) line of the Memory
Address Bus. When this line is high, control information is transferred; when it is low,
data is transferred. The USART does not utilize the +ADDR 1 line.
2.2.6.1.2
Timing. Refer to the baud rate counter discussion in 2.2.6.2.1.2.
2.2.6.1.3
Information Transfer. Two inputs, RD and WR, determine the direction of
information transfer. When RD is low, the USART places data or status information
(determined by the C/D input) on the bidirectional data bus for input to the MPU. When
WR is low, data or control information from the MPU is taken off the data bus and loaded
into the USART. The RD and WR inputs are controlled by -READ and -WRITE,
respectively, from the 8228 bus driver/system controller.
Note that all information transfer between the MPU and the USART is over the
bidirectional data bUS, through a bidirectional, 3-state buffer within the USART.
Information transfer between the USART and the data link is over individual lines for Send
Data, Receive Data, and each of the modem status and control lines, through a voltage
level converter, to (or from) the modem. (Refer to the integrated circuit data in the
Schematics/Reference section for information on the level converter les.)
2.2.6.1.3.1 Read Data. When the USART receives a character from the data link, it
raises its RXRDY (Receiver Ready) line, which goes to the interrupt logic. If USART
interrupts are enabled, +INTR is developed and sent to the MPU. In servicing this
interrupt, the MPU performs a sequence of instructions, one or which is an input from
Port o. With CS low, RD low, and C/D lOW, the USART puts an 8-bit byte of data onto
the bidirectional data bus, from where it is accepted by the MPU. The USART, having
presented the data byte to the bUS, resets its RXRDY line, until the next character is
received and the entire sequence repeats.
As the data is received from the data link, the USART strips off the start and stop bits,
checks the parity bit (if parity checking is enabled-see 2.2.6.1.3.4), and checks for
framing errors (lack of a stop bit at the proper time). If an error is detected, a bit is set
in the internal Status Register. The USART also checks to see that the previous character
has been accepted by the MPU-if RXRDY is still high (has not been reset by the MPU
having read the previous character), the overrun status bit is set.
2-15
2.2.6.1.3.2 Write Data. When the MPU wishes to send data to the USART, it addresses
Port 0, places the data character on the bidirectional data bus, and develops -WRITE.
This combination (CS, WR, and C/D all low) loads the character into the USART, which
then adds the start, stop, and parity bits, and immediately begins to shift the character
out, one bit at a time through the level converter IC to the data link.
There are two status bits pertaining to data transmission: TXE (Transmitter Empty) and
TXRDY (Transmitter Ready). Both of these become reset when a character is loaded into
the USART from the MPU. If a relatively long time has passed since the previous
character was loaded, TXRDY sets again almost immediately. This allows a second
character to be loaded, even though the first has not been fully shifted out. TXRDYagain
resets as the second character is loaded, but this time it remains reset until the first
character is completely shifted out. Then it sets again, allowing another character to be
loaded. When all data characters have been fully transmitted, TXE again sets.
2.2.6.1.3.3 Read Status. When the MPU wishes to know the status of the USART, it
performs an input from Port 0 with +ADDR "high. This occurs after any interrupt, since
the MPU needs to know if it is the USART that is interrupting, and before every data
output to the USART, because the MPU must check to see that the USART is able to
accept the data character.
When Port 0 is addressed, the -PORT" signal enables the USART by driving its CS input
low, and +ADDR 0 drives the USART's C/D input high, which directs the USART to
transfer control/status information.
-READ again directs the USART to output
information onto the bidirectional data bus, but because the C/D input is high, the USART
outputs status information instead of data.
2.2.6.1.3.4 Write Control. A control write is used to program the USART for parity
checking, byte length, number of stop bits, etc. When the MPU outputs control
information for the USART, it addresses Port 0 while holding +ADDR "high. However,
complete control of the USART requires more than 8 bits of information. The USART is
designed to accept two different control bytes, a "Command" byte and a "Mode" byte. It
accepts the Mode byte only as the first control instruction following a reset. All
subsequent "control writes" are accepted as Command bytes. Each of the individual bits
in the Command and Mode bytes is defined in the IC data for the 8251 in the
Schematics/Reference section of this manual.
2.2.6.2
I/O Port IC (8255)
The other two I/O ports on the HPR03 board, Ports 1 and 2, utilize an 8255 Programmable
Interface IC. This type of IC may also be used for ports located on the other circuit
boards. This is a 40-pin IC having eight pins connected to the bidirectional data bus and
three more sets of eight pins each that can interface to various "peripheral" devices. The
balance of the pins are used for power supply connections and control signals.
2-16
The 8255 contains three 8-bit registers called A, B, and C, each of which can be used for
either input or output. The C register can even be split into two 4-bit registers, each
individually programmable for input or output, or for control and status signals.
There are three possible modes of operation, selected by a control word issued by the
MPU. This control word is a part of the firmware microprogram stored in ROM, so it can
be different for each 8255, and it can even change at different points in the execution of
the program. (This control word can also be used to alter individual bits in Register C,
while leaving the other seven bi~s unchanged.) The three possible modes are as follows:
Mode 0:
Simple input or output for each register
Two 8-bit and two 4-bit registers
Outputs are latched
Inputs are not latched
Mode 1:
Strobed input or output for Registers A and B
Register C used as control/status for the other two registers
Inputs and outputs all latched
Mode 2:
Strobed bidirectional bus (not used in HPR03)
Each 8255 IC has the following connections to the terminal microprocessor:
Dt) -D7:
The bidirectional data bus, over which all data transfer occurs between
the MPU and the 8255.
CS:
Chip Select Input. One of the decoded "port" signals is used to select
only one 8255 at a time. Only -PORT 1 and -PORT 2 select 8255s on
the HPR03 board. The other port signals may select 8255s on other
circuit boards.
AO&A1:
ADDRESS f) and ADDRESS 1 Inputs. The two low-order lines of the
Memory Address Bus (ADDR f) and ADDR 1) are used to select. which of
the three registers is to be used, or to specify that a control word is
being sent out by the MPU.
ADDR 1
ADDR f)
(AI)
(Af)
o
o
1
1
1
1
o
o
Register A
Register B
Register C
Control Word
RD:
Read Input. When low, specifies a read (into the MPU) is
occurring. This is considered "input."
WR:
Write Input. When low, specifies a write (from the MPU) is
occurring. This is considered "output."
Further details of the 8255 IC's operation can be found in the Schematics/Reference
section.
2-17
2.2.6.2.1
Port 1. Port 1 is enabled by the -PORT 1 signal. It is generally operated in
Mode O. The control word from the MPU programs the port for input through Register A
and output through Registers Band C.
2.2.6.2.1.1 Status Inputs.
MPU of the following:
Bit
Bit
Bit
Bit
Bit
Bit
2
3
4
5
6
7
The six bits of Register A that are used provide status to the
EIA option 3
EIA option 2
Carrier Detect
Clear to Stand
Keyboard Interrupt
Real-Time Clock Interrupt
2.2.6.2.1.2 Baud Rate Counter. This counter produces a square wave at 1, 16, or 64
times the baud rate frequency. The USART clock frequency requirements vary according
to the USART programming (the "mode" instruction) and the desired baud rate. The mode
instruction determines whether this clock must be 1, 16, or 64 times the baud rate. (64 is
generally used for baud rates below 1200.) A factor is loaded into Register B of the 8255
by the MPU, and the counter, driven by Tt2, is counted up until it overflows. When this
happens, the same factor is reloaded and the counting resumes. The overflow also toggles
a D-type flip-flop, which further divides the count by 2 and makes the output
sym metrical.
The USART clock can also be supplied by an external source via board pin 4, when the
correct jumper wire is installed. Furthermore, during synchronous data transmission/reception, the USART's receive clock is provided by the modem. In this case, a jumper on
the HPR03 board must be changed to separate the transmit and receive clocks. .
2.2.6.2.1.3 Interrupt Enable/Disable. Each of the four types of interrupts that can be
generated on the HPR03 board can be individually enabled or disabled. A "1" loaded into
the C Register enables, while a "0" disables, as follows:
Bit 4
Bi t 5
Bit 6
Bit 7
USART receive
USART send
Keyboard
Real-Time Clock
2.2.6.2.2
Port 2. Port 2 is selected by the -PORT 2 signal, and is generally operated in
Mode 1. The control word from the MPU programs the port for input through Registers A
and B. The Register C bits are used mostly for control/status in Mode 1, but two bits,
PC6 and PC7, are still available for I/O, and in this port they are used for output.
2-18
2.2.S.2.2.1 Keyboard (Parallel) Input. This data, in the form of 8-bit parallel bytes on
the -DATAI' through -DATA7 lines, is continually applied to the Register A inputs. As
long as the Register A strobe input, which is PC4 (pin 13) in the Mode 1 configuration, is
low, this data is loaded into Register A. -KYSTB is normally high, so after it drops low
and then goes high again, the KEYBOARD INTERRUPT flip-flop sets on the trailing
(positive going) edge. As soon as this flop-flop sets, it latches the data into Register A; at
this point the eight parallel inputs may be removed or changed without altering the data in
the register.
When the KEYBOARD INTERRUPT flip-flop sets, it also presents an interrupt to the MPU
(provided keyboard interrupts have been previously enabled). When the MPU recognizes
the interrupt, part of its interrupt service routine is an instruction to read from Register
A, to input the data to the MPU. Following this, it also performs a pair of "bit set/reset"
instructions: the first to put a "low" on PCS to clear the KEYBOARD INTERRUPT flipflop; the second to put a "high" back on PCS to enable the flip-flop to be set again by the
next -KYSTB. The MPU also reads the function key status from Register B as part of this
interrupt service routine.
Note that +BUSY is driven high when the KEYBOARD INTERRUPT flip-fl,op sets, and
remains high until after the flip-flop is cleared and reenabled. This signal can be used by
an 8-bit parallel input device as a ready/not ready indicator; when +BUSY is high, it
indicates that -KYSTB signals will not be accepted. The 8-bit parallel input device should
present -KYSTB only when +BUSY is low.
2.2.S.2.2.2 Function Key Status. The keyboard function key signals, as well as the status
of the three options, are continually applied to Register B. In Mode 1, the Register B
strobe is received on PC2 (pin 1S). The +SYNC signal from the MPU thus latches the
status of the function keys and jum per options into Register B.
These signals do not produce an interrupt. Instead, their status is read from Register B by
the MPU each time it services an interrupt caused by -KYSTB.
2.2.S.2.2.3 Real-Time Clock One-Shot. The Real-Time Clock one-shot is controlled by
the individual bit set/reset feature of the 8255. Bit 7 in the C Register (PC7, pin 10) is
controlled by the MPU: when it goes high, the one-shot fires; when it goes low, the oneshot is enabled to fire again. PC7, when high, must first go low, then return to high to
start the 10 ms timer.
2.2.S.3
Off-Board I/O
Input from or output to logic circuits external to the HPR03 board can be accomplished in
either of two ways: programmed I/O or direct memory access. Programmed I/O can
occur either through the mother board connector (PI) or the control panel connector (J2).
DMA transfer can occur only through the mother board.
2-19
2.2.6.3.1
Programmed I/O. This is accomplished in the same manner used for onboard
I/O. An I/O port, #3 through #6, is addressed, and -READ or -WRITE is developed. If
necessary, +ADDR ., and +ADDR 1 may be used to further define the address (as when an
8255 IC is used). All data is transferred between the MPU and the off-board port over the
bidirectional data bus.
Port 3 must be accessed through the control panel connector. (-READ and -WRITE are
passed through the drivers, and become -RD and -WR.) Ports 4,5, and 6 must be accessed
through the mother board. Port 4 is generally reserved for DMA, and Ports 5 and 6 are
generally used for the printer.
2.2.6.3.2
Direct Memory Access. Data can be transferred directly between memory
and an external device following the procedure outlined in 2.2.5.5. In this case, data is
transferred directly between memory and the external device over the bidirectional data
bus; the MPU stops in a "Hold" condition while the transfer takes place.
2.2.7
Miscellaneous Circuitry
2.2.7.1
3-Terminal Voltage Regulators
There are three 3-terminal voltage regulator ICs, shown on sheet 1 of the HPR03 logic
drawing, that provide the source of -5V, -12V, and +12V. These voltages are derived from
the ± 15V provided by the power supply, which also provides +5V.
2.2.7.2
Level Converters
The input and output voltage level converters provide the interface between "the TTL
inputs and outputs of the USART and the 12V (nominal) requirements of RS-232-C.
2.2.7.3
Options
There are four options on the HPR03 board that provide variations in operation. These
are covered in detail in the Product Description.
2.3
XMEM (EXTRA MEMORY) BOARD, PART NO. 23926-XX.
When the 4K bytes of ROM, 1K of EROM, and 512 bytes of RAM on the HPRO board are
adequate for the programming application, the XMEM board is not supplied. When
additional memory is required, the XMEM board is installed in slot F, directly behind the
HPRO board; no connections other than plugging into the mother board are required. The
XMEM1 board can contain up to 1.5K bytes of RAM, 4K of ROM, 8K of EROM, or a
combination of memory types.
2-20
2.3.1
Applications
During program development, programs are stored on EROMs so they can be debugged,
erased, and rewritten. When the program has been tested and validated, it is burned into
the masked ROMs, which are installed on the HPRO board.
EROMs on the XMEM board are used to store development programs. Because of the time
involved in manufacturing masked ROMs, early production terminals are often shipped
with programs on EROMs on the XMEM board instead of on masked ROMs on the HPRO
board. Also, when a program is larger than 4K bytes, additional memory chips, either
ROMs or EROMs, are installed on the XMEM board to store part of the program. ROMs
and EROMs on the XMEM board are addressed in the same manner as ROMs and EROMs
located on the HPRO board. For applications requiring more than 512 bytes of working
read/write memory, up to 1.5K bytes of RAM can be installed on the XMEM board.
2.3.2
Basic XMEM Board
The basic XMEM board (dwg. no. 23926-XX) contains an address buffer, address decoders,
and voltage regulators. IC memory chips of the required type and number are .added to
suit a specific application.
2.3.3
XMEM Configurations
The XMEM can have the following numbers of memory chips installed:
12 Type 2111A-4, 256 x 4-bit RAMs
2 Type 8316A, 2K x 8bit masked ROMs
8 Type 8708, 1K x 8bit EROMs
While it is possible to have all these memories installed (physically) on the same XMEM
board, is is logically impractical, because both ROMs and EROMs use the same addresses,
and two EROMs must be eliminated for each ROM installed. There is no address
interference between RAMs and ROMs or EROMs, so a full complement of RAMs can be
installed regardless of the number of ROMs and/or EROMs installed.
2.3.4
Addressing
Figure 2-6 shows the memory addressing scheme used by the MPU to access the entire
memory, both on the HPRO board and on the XMEM board. Note that HPRO ROMs #1
and #2, and XMEM ROMs #3 and #4 use the same address areas as the EROMs on the
XMEM board, so the EROMs can not be used when the masked ROMs are installed. This is
done intentionally, so that a program can be written electrically into EROMs, tested and
corrected as often as necessary, and when approved, the program can be used to generate
masked ROMs without need for address modification. When masked ROMs are in
production, the EROMs can be eliminated, and, if the program is less than 4K, the two
ROMs containing the program can be installed on the HPRO board. If there is no need for
the additional RAM storage, the XMEM board can be eliminated. If the program is larger
than 4K, two additional ROMs can be installed on the XMEM board, along with as many
RAMs as are required.
2-21
ROMs and EROMs can be mixed, as long as there is no direct address conflict. For
example it would be possible to use EROMs 5, 6, 7, and 8 with HPRO ROMs 1 and 2, but
these EROMs could not be used with XMEM ROMs 3 and 4. Since RAMs use an entirely
different address area, their use is independent of ROM/EROM configuration.
Additional Applications
2.3.5
o
EROMs can be used in terminals produced in quantities too small to justify
the expense of preparing masked ROMs.
o
A mixture of ROMs and EROMs can be used in applications requiring special
programs.
o
RAMs can provide additional working memory.
2.4
MATRIX INTERFACE BOARD, PART NO. 25930-XX
The MATRIX INTERFACE (MXI) board contains I/O Ports 5 and 6, which transfer data,
control signals, and Status information between the terminal processor and the printer
processor. Also contained on the MXI board is the logic for receiving and temporary
storage of carriage position feedback signals from the CARRIAGE SERVO board enroute
to the printer processor. Carriage directional commands are also produced on the MXI
board from the data received from the printer processor. These signals are applied to the
servo motor driver FETs on the CARRIAGE SERVO board. A block diagram of the MXI
board is shown in Figure 2-8.
2.4.1
I/O Ports 5 and 6
I/O ports 5 and 6 are used to synchronize the tranfer of information between the two
processors. When the terminal processor performs an output instruction to Port 5 or 6,
the output information is stored on the MXI board where it is available to the printer
microprocessor. The printer microprocessor periodically "reads" the MXI board to see if
there is any information that it should process. Similarly, as the printer microprocessor
goes though its steps of controlling the printer operations, it provides status information
to the MXI board. This status information is monitored by the terminal microprocessor
prior to each output com mand.
2.4.1.1
Transferring Information to the Printer Processor.
The prerequisites to actual transfer of data include the +POWER ON and -SELECT
PRINTER signals. The +POWER ON signal energizes the 8212 ICs and is inverted to
provide a -POWER ON signal. Both +POWER ON and -POWER ON are outputs to the
printer processor. The -SELECT PRINTER signal will enable the transfer of information
between the two processors.
*WRITE TO PORT 6: When -WRITE and -PORT 6 signals develop, the control information
on the data bus is transferred to the printer microprocessor via the Port 6 latches. This
data is output directly onto control lines to the printer and includes the following control
signals: -DOUBLE LINE FEED, +AUTO LINE FEED, +TEST, -SET TOF ZERO, and
+RESTORE (INT 0).
2-22
*WRITE TO PORT 5: A Write to Port 5 instruction will only be performed by the terminal
processor if the +READY output line from the MXI board is high. This +READY signal is
developed on the MXI board when the printer processor provides a -DATA ACK to the MXI
board. The -DATA ACK indicates that the printer has received and processed the
previous information and it is now able to receive more data. -DATA ACK enters the MXI
board and resets the Data Strobe FF (C49) which in turn raises the +READY signal. The
- WRITE and -PORT 5 signals load the data on the terminal data bus (DA0 -DA 7) into the
Port 5 latch on the MXI board and raise the +DATA STROBE signal to inform the printer
processor that data is available. This data is then clocked into the printer processor via
the printer data bus (D1 - D8). The Data Strobe FF is reset when the -DATAACK line
becomes active (low) from the printer processor.
Transferring Information from the Printer Processor
2.4.1.2
Only status information is received by the terminal processor from the printer when a
Read from Port 5 instruction is output to the MXI board from the terminal processor. A
+SYSTEM CLOCK signal allows status information from the printer processor to be loaded
into the Port 5 latch (D54) at a time that will not cause an error in the system. The
-SELECT PRINTER signal must also be present to enable the transfer of data between the
two processors. When -READ and -PORT 5 signals are issused from the terminal
processor, the data latched at D54 is transferred to the terminal processor via the bidirectional data bus (DA0 - DA 7). This status information is "read" by the terminal
processor prior to each command.
+ CAR REV
+
FROM PRINTER
PROCESSOR
~~
DIR
{
+
CAR UN MOOE
+
CAR EVEN
FROM CARRIAGE {
SERVO BOARD
+ CAR POS B
+
CAR POS A
FROM PRINTER
PROCESSOR
+
CLOCK A
-
PORT 6
____________________
TRACK
CROSSING
DETECTION
LOGIC
:v
+
~+~C~A~R~F~W~D_
CAR POS INT 1
}
TO CARRIAGE
SERVO BOARD
TO PRINTER
PROCESSOR
,.
A
II.
PORT
II.
TO PRINTER
PROCESSOR
FROM TERMINAL
PROCESSOR
(HPR03)
-
- L
SELECT
PRINTER
~
-_R-"-EA...;.;;;D_ _---I~
-
.-------,
+ DATA
F IF
PORT 5
STROBE
STROBE
+
pk____________-t:
READY
TO PRINTER
PROCESSOR
READY
-
FROM PRINTER
PROCESSOR
FROM TERMINAL
PROCESSOR
(HPR03)
{
1
DATA ACK
I
F/F
~
II.
fll1jljIljIljljljljIIljI~j~jI~~~j~j~jlj~lj~jI~jII~j~j~j~j~j~jljI~j~j~j~jjjjjjj~jjjjIjIjjjjIjjjIjjjjjjjjjjjj;:gU;;81fj~j~j~~Ij;
+ SYSTEM
CLOCK
I
TO TERMINAL
PROCESSOR (HPR03)
.
PORT
PORT
5
5
(STATUS)
,
fL..----.....l
..
(COMMANDS)
~
U~j;gI;Bgj!l!~~:
TO PRINTER
PROCESSOR
..
rL.------------J
~----------------~----------------~
083-002
Figure 2-8. MXI Board Block Diagram
2-23
2.4.2 Carriage Position Data
The'matrix printer prints characters using a dot matrix where the horizontal distance
between sucessive dot positions is 1/100 inch (.254 mm). The purpose of this circuitry is
to generate a 4 ps pulse when, and only when, the carriage has moved the print head 1/100
inch in either direction (left o~ right) from the position represented by the preceding
pulse. This circuit is called the Track Crossing Detection Logic.
The printer's carriage servo motor includes a shaft position transducer that transforms a
two-phase sinewave input into a composite output. The instantaneous value of the output
is compared with the input and used to produce three square waves called +CAR POS A,
+CAR POS B, and +CAR POS EVEN. The high and low status of these square waves
changes with respect to actual carriage travel, so that (depending on the direction of
carriage movement) two of them (EVEN and A or B) will be opposite polarity when the
third (A or B) changes polarity. This event occurs once for each 1/100 inch of carriage
movement and is called a track crossing point. The circuit output is a 4 us pulse called
+CAR POS INT 1, and is supplied to the printer microprocessor as an interrupt signal,
telling the microprocessor to interrupt its normal program and update carriage position
data.
+5
+ CLOCK
A
C39
9
X>-'------+---f49
+CAR pos INT I
+CAR
pos
B
+CAR
P~S
A
+ CAR
EVEN
14
r-------------....:...:..t
013-003
Figure 2-9. Track Crossing Detection Logic
2-24
+CLOCK A (C37-9)
+ CAR
POS A (C37-7)
+ CAR
EVEN (CI3-13)
+ CAR
pos
B (C37-4)
~----------~---I
~I
~I
l
-=--~
_ _ ___
~
:
: .+I
C61-3
L___
I
I
C13-11
C13-6
I
,
-------~~~I~~----
C37-IO
-----;L~
C37-14
C61-8
I
C25-IO (+CAR
pos
I
--JIlL..-__
INT_I)________
CARRIAGE MOVEMENT RIGHT--.
----------~~'~~----
------;L!---I
I
______________---'r-l~___
CARRIAGE MOVEMENT
ll.E!.
~
083-004
Figure 2-10. Track Crossing Detection Waveforms
Referring to Figures 2-9 and 2-10, device C37 is a series of D-type flip-flops with their
Clear input tied to +5 volts. In this situation the C37 Q outputs will follow the D input
with positive clock input excursions. As shown by the waveforms in Figure 2-10,
generation of the +CAR POS INT 1 signal for carriage movement to the right begins with
a high to low transition of +CAR POS A, followed some time later (not clock related) by
+CAR EVEN going low to high. With the preconditions met, and again some time later,
+CAR POS B will go low. Then, with the next positive clock transition, the output of XOR
gate C61-13 will go high, NAND gate C13-11 will go lOW, and NAND gate C13-6 will go
high. C13-6 = high is supplied to C37-12 where, with the next positive clock transition,
C37-10 goes high. This high drives the output of XOR gate C61-8 low, and is supplied to
C37-13. C37-13 =high drives C37-14 low with the next positive clock transition to drive
the output of C61-8 high again to end the pulse. Inverter C2 5-1 0 inverts the output of
C61-8 to produce the 4 ps positive pulse on +CAR POS INT 1 that is sent to the printer
microprocessor.
For carriage movement to the left, Figure 2-10 shows +CAR EVEN first going low,
followed by +CAR POS B going high. Then when +CAR POS A goes high, the signals
proceed through the logic as outlined above to produce the 4 ps output pulse.
2.4.3
Carriage Direction Commands
The PROCESSOR board provides a directional signal (± DIR) to the MXI board where it is
gated with the +CAR LIN MODE signal from the CARRAIGE SERVO board to produce the
+CAR FWD and +CAR REV carriage direction signals for the CARRIAGE SERVO board.
The +CAR LIN MODE signal is active (high) only when the carriage is in detent (or
stopped). This high +CAR LIN MODE signal causes both the +CAR FWD and +CAR REV
output signals to become inactive (low). When the +CAR LIN MODE signal goes inactive
(low), the polarity of the ± DIR signal will determine which of the two carriage direction
signals will be active. A +DIR produces an active (high) +CAR FWD signal and an inactive
(low) +CAR REV signal while a -DIR signal produces an inactive (low) +CAR FWD signal
and an active (high) +CAR REV signal.
2-25
2.5
PROCESSOR (PRINTER) BOARD, PART NO. 24620-XX
The matrix printer's microprocessor consists mainly of six MOS-LSI chips: two Parallel
Data Control (PDC) chips, two Read Only Memory (ROM) chips, one Random Access
Memory (RAM) chip, and one Central Processor Unit (CPU) chip. Auxiliary devices such
as a clock generator and addressable latch modules, a voltage regulator, a power-on delay
circuit, and several control switches complete the PROCESSOR board circuits.
Figure 2-11 presents the PROCESSOR board circuits in simplified block diagram form. Its
use along with the full schematic diagram in Section 4 and the following paragraphs should
aid the reader in understanding the operation of the microprocessor.
.
Pow.r 0"
Dato
..
Prillt.r
Cootrol
-
Poper F••• Control
Illt.rfac. Cootrol
Data Ack
--.
Strobe
SwiUfI••
( OptIOD)
-
PDC-I
C!54
-...
Cor Tro_ Cr ......
---
-..
--
R.stor.
Power On
~
....
Data Bu.
CPU
A69
•
•
I
r•
r-+
RAM
••
a"
...
.
C24
•
....... -Fir.
-
Switches (Cootrol)
Car
Veloclt,
PDC-2
ROM(S)
A24139
A54
Addre ••
-
--.
_..
'.
Control lin ••
~t
..
..
s.rvo Control
ADDR
LATCH
E40
Figure 2-11. Processor Simplified Block Diagram
2.5.1
Chip Task Assignment
2.5.1.1
The PDC (Parallel Data Controller)
A PDC is a flexible parallel input/output device for interfacing the microprocessor to
external circuits. It provides two independent, bidirectional 8-bit input/output channels,
each of which may operate in a variety of parallel data transfer modes. The CPU is able
to designate these 16 lines to operate as either inputs or outputs in blocks of 4.
PDC-1 C54 has 8 data inputs (pins 10-17) and a data strobe input all working as one
channel. Latched +DATA signals are presented to these 8 inputs, along with the +DATA
STROBE on pin 8, all from the MXI board. The transition of the data strobe causes the
ASCII data to be sent into the PDC data buffer. The PDC will then produce a high signal
at pin 9 to indicate that the PDC buffer is full. This signal is inverted to -DATA
ACK=low and is sent to the MXI board to delay the output of the ACKNOWLEDGE signal
to the controller until the CPU has taken the data from the PDC buffer. When this
internal transfer of data has been completed, the PDC will drive its pin 9 low to produce
-DATA ACK= high to the MXI board to permit the output of the ACKNOWLEDGE signal
to the controller. This is ref erred to as the handshake mode of operation.
2-26
The second channel operates in the clocked I/O mode. The input lines (pins 30-37) are
divided so that pins 34-37 are inputs and pins 30-33 are outputs, with pin 1 the input clock
or strobe.
Pins 34-37 receive inputs from the option selection switches or the MXI board (pin 35
only). These inputs are read during a power on sequence or when a +DATA STROBE =high
is received from the MXI board.
Pins 2 and 30-33 are outputs to Addressable Latch E40. Pins 30-32 address 1 of 8 latches
in E40. Pin 33 inputs the data to be set into the addressed latch. Pin 2 controls the mode
of operation of E40. When pin 2 is high, the output from pin 33 will be set into the
addressed latch, and all other outputs will remain unchanged. When pin 2 is low, pins 3033 have no effect on the outputs of E40. All 8 lines from E40 will output data previously
set into the latch.
Pins 18-25 connect to the bidirectional data bus to transfer data to and from the CPU.
PDC pins 3-6 and 42 are processor activity control lines used by the several chips to
communicate with each other. Pins 40 and 41 are clock signal inputs.
PDC-2 C24 operates in the static output mode. It functions as two groups of 8 latched
outputs fed from the data bus. One group (pins 10-17) is designated as Hammer Data.
Outputs on these lines control individual print wire firing through the HAMMER DRIVER
board. The other group (pins 30-37) is designated Velocity Data. Outputs on these lines
are commands used to generate carriage servo drive through the CARRIAGE SERVO board
and are latched and remain static until changed by insertion of new command information.
New command information occurs when the processor detects a need for a change in
carriage velocity following a track crossing. Referring to the previous discussion, the MXI
board generates the +CAR POS INT 1 pulse for each increment of carriage movement.
Processor logic, in looking ahead at the stored data, may detect that the carriage has
reached a tab position or the end of the print line. In this instance, the processor will
begin to issue new carriage velocity commands to change the carriage velocity to meet
the changing situation. In addition, three command line inputs (pins 1, 2, and 8) carry
+TEST, +LINE FEED, and +SET TOF ZERO command signals from the MXI board
instructing the processor to execute the indicated function.
2.5.1.2
The RAM (Random Access Memory)
RAM A54 is a device consisting of 2048 bits of read-write memory in a 256 x 8-bit
configuration. It is used in the microprocessor as the general working register, the
vertical and horizontal tab table, and as the processor's data buffer.
2.5.1.3
The ROM (Read Only Memory)
ROMs A24 and A39 are devices each consisting of 16,384 bits of read only memory in a
2048 x 8-bit configuration. They are used in the microprocessor for the storage of all
microprocessor program instructions, including various constants such as the velocity
table used for servo control, and the print font.
2-27
2.5.1.4
The CPU (Central Processor Unit)
CPU A69 is a device which contains all of the logic necessary to receive and decode 8-bit
instruction words, and to perform all the required arithmetic and logic operations.
Through a 14 line parallel (multiplexed) address bus, the CPU addresses 32,768 bits or 4096
bytes (8-bits/byte) of read only memory (ROM), and with the same 14 line bus also
addresses 2048 bits or 256 bytes of random access memory (RAM). The CPU functions as
an 8-bit parallel data processor, and in conjunction" with the RAM, the ROMs, and the two
PDCs forms the microprocessor for the matrix printer.
2.5.1.5
The Clock Generator Circuit
Clock module E8, along with 3.58 MHz crystal D8, make up the printer's basic clock
generator. The clock output frequency is 256 kHz on pins 1, 4, and 10. Pins 1 and 10 are
designated CLK A, and pin 4 is designated CLK B. The output at pin 10 includes a driver
which makes this output TTL compatible. Inverter D18-2 inverts the CLK A signal for use
in the MXI board circuits.
2.5.1.6
The 12 Volt Regulator Circuit
Module E66 and its associated components form a circuit which lowers the -15 volt input
to -12 volts, and regulates the output for use in the microprocessor circuits.
2.5.1.7
Summary
In overview, the matrix printer's microprocessor controls machine operation by receiving,
storing and executing commands. As each command is executed, the processor s.ignals its
status to the terminal microprocessor through the MXI board, to keep the terminal microOnly in the RESTORE activity does the printer
processor constantly updated.
microprocessor program digress. The microprocessor will, by itself, initiate a RESTORE
sequence under the following conditions:
o When instructed to backspace (BS) past the left margin.
o When instructed to print (CR or S1) past column 132.
o When instructed to tab (HT or VT) with a value greater than 127 •.
o When the carriage fails to move when commanded.
NOTE
If the carriage still does not move during the restore sequence,
the microprocessor will issue the +SERVO DISABLE signal to
prevent circuit damage.
o When POWER ON goes low during machine operation.
-The RESTORE sequence can also be commanded by the terminal microprocessor.
2-28
2.6
CARRIAGE SERVO BOARD, PART NO. 24625-XX
Refer to the CARRIAGE SERVO board schematic diagram. Figure 2-12 is a simplified
block diagram of the circuits on the CARRIAGE SERVO board.
As described earlier, the Track Crossing Detection Logic circuit on the MXI board makes
use of a series of three squarewaves on the PROCESSOR board to update its carriage
position file. The development of these squarewaves in sync with actual carriage
movement is one of the two major functions of the CARRIAGE SERVO board. The second
major function of this board is to provide an error signal to the CARRIAGE POWER
AMPLIFIER board for use in developing carriage servo drive signals.
VELOCITY
D-A
------i
CONVERTER
DATA
LINEAR
MODE
SER~
SHAFy------
TRACK
CROSSING
REFERENCE
Figure 2-12. Carriage Servo Block Diagram
REF
+15V
OUT.
,...................-.........-._----.....---+---- CAR I
~~
....--~....---
Figure 2-13. Digital Sinewave Generator
2-29
CAR2S4
NOTE:
2.6.1
All waveforms pictured in this section were taken with the oscilloscope
synchronized to the A output of shift register G21-15 during carriage
forward movement at 200 cps while printing the test line.
The Digital Sinew ave Generator
Figure 2-13 is a partial schematic diagram showing the Digital Sinewave Generator.
Figure 2-14a shows the waveforms generated by this circuit. The two modules G15 and
G21 are 4-bit parallel access shift registers which are driven by a clock circuit with an
output of about 5 MHz, connected to form a divide-by-16 circuit. The outputs of G15 and
G21 are squarewaves as shown in Figure 2-14, where the output G21-15=high is followed
one clock cycle later by G21-14=high and so forth. When G15-12 goes high, feedback
through G15-11 and through NAND gate G9-6 drives the output G21-15 low. This
condition then cascades through the registers again until G15-12 goes low, when G15-1I
will drive G2I-15 high to start the cycle again. These squarewave outputs are connected
through inverters, pull-up resistors, and load resistors to two output lines. The inverters
act as switches, allowing current to flow through the associated load resistor whenever
the inverter output is low. Seven of the inverter outputs are selected for summation to
form each of the two signals CAR 1 and CAR 3. The values of the several load resistors
plus a capacitor from each of the output lines to their common return line produces the
two-phased sinusoidal waveforms shown in Figure 2-14b. These signals are fed to the
stator windings on the carriage servo's position transducer.
A"
G21-15
II
G21-14
"8 11
G21-13
"C II
G21-12
"0"
G15-15
"E"
G15-14
"F"
G15-13
"Gil
J8A-4
CAR. I
J8A-7
CAR. 3
G15-12 "HI!
(a)
(b)
Figure 2-14. Digital Sinew ave Generator Waveforms
2-30
2.6.2
Servo Position Transducer
The Servo Position Transducer consists of rotor and stator members made up as flat disks
with windings laminated on adjacent surfaces. The rotor is mounted on the free end of the
carriage servo motor shaft, with the stator mounted over it and fastened to the motor
casing. Output signals from the rotor are picked up by means of an axially mounted rotary
transformer as CAR 5 and CAR 6 signals.
As shown in Figure 2-15, the stator has an eight segment winding, with alternate segments
connected together to form two groups of four segments each. The four segments of one
group are displaced laterally from the other group by a distance equal to one-half a
winding width. This displacement is equal to a 90° phase difference. The rotor has one
sym metrical winding.
The two sinusoidal waveforms shown in Figure 2-15 are introduced into the transducer's
stator windings, and are coupled electromagnetically to the transducer's rotor winding.
Since all windings in the device are nearly 1:1, the only transformation of the inputs is
that the summed output is phase modulated by rotor movement. The phase modulated
output is supplied back to a 3-stage amplifier and demodulator circuit on the CARRIAGE
SERVO board.
STATOR
It _ - _ _
ElIAII5£MrO) RIll
a.-TYI
ROTOR
Figure 2-15. Servo Position Transducer
2.6.3
Servo Feedback Amplifier
AS
ROTARY
TRANSFORMER
][
(ON TRANSDUCER)
~52~A7
Ik
S
~:
~::61~
A'"
D4
Ik
Figure 2-16. Servo Feedback Amplifier
2-31
Figure 2-16 is a partial schematic diagram showing the Servo Feedback Amplifier. Figure
2-17 shows waveforms taken in this circuit. Waveform A is the phase-modulated servo
transducer output, as seen at the input to the first video amplifier B5-1/-14. Amplifier B5
has an adjusted gain of :: 20. It amplifies and partially filters the input (B). The second
video amplifier D5, also with a gain of 20, further filters the signal and generates a 10
volt p-p output waveform (C) which displays some squaring effect of saturation limiting.
This output is applied to a high speed squaring comparator module E5. E5 is overdriven,
and produces a squarewave output.
A
B
I sf VIDEO AMPL. INPUT
I st VIDEO AMPL. OUTPUT
85 - 1/14 (85-1 INVERTED)
85 -7/8 (85 -7 INVERTED)
c
2 nd VIDEO AMPL. OUTPUT
05-7/8(05-7 INVERTED)
Figure 2-17. Servo Feedback Amplifier Waveforms
2-32
2.6.4
Servo Feedback Demodulator/Amplifier
Figure 2-1S is a partial schematic diagram showing the Servo Feedback Demodulator/
Amplifier circuit. Figure 2-19 shows waveforms taken in this circuit.
The squarewave output of comparator E5 is inverted and applied to Exclusive OR gate
D1S-S as the squared and inverted phase-modulated signal from the carriage servo
transducer. This output of D1S-S is applied to Exclusive OR gates DlS-3 and D1S-11 along
with reference squarewaves from the sinewave generator. Refer to Figure 2-19. Observe
the two inputs to either D1S-3 or D1S-11, along with its output, on a multichannel
oscilloscope which is synchronized to the sinewave generator while slowly moving the
carriage by hand. The squarewave input from gate Dl8-S (B) will appear to move with
respect to the input on pin 1 or 12 from the sinewave generator (A). Then, the output (C)
from either D1S-3 or D1S-11 will be a squarewave whose relative high-low status will vary
as the high-low states of the two inputs vary with respect to each other. Figure 2-20
illustrates the development of the output waveform (C) from the two squarewave inputs
(A and B), and further shows the sawtooth waveshape developed in the integrating circuits
for input to amplifiers A1S-l0 and C1S-12. The output of A1S-l0 is then supplied to
amplifier AlS-12. These three amplifiers produce the waveshapes called CAR POS SIG
#1, CAR POS SIG #2, and CAR POS SIG #3.
rlt-.........--+---.---=-:---..---CAR. POS· I
~--+--CAR.POS·2
}:!--.......--+~-HF~-4--__----+----If--+--CAR.POS·3
' -TO
-"
CAR.POS
TACH
Figure 2-18. Servo Feedback Demodulator/Amplifier
CAR.
pos· I
A
CAR. POS
#
2
B
CAR. POS#3
C
Figure 2-19. Servo Feedback Demodulator/Amplifier Waveforms
2-33
MOTION
I:i: -.~
UlTI.TI..TI.TI.
~
~
AV. 2.I5V
trJDrJrIDrlO[
AV.3.7I5V
AV.5.0V
ILJL.JL.Jl...
~
~
~
~~
~
~
AV. 1.25V
~
ILJL.JL.Jl...
~
rrn:::rr:rJ.IlT
OEMOO
~
~
~
REF
OE-"LATOR
INTEIIRATOR
~
ILJL.JL.Jl...
ILJL.JL.Jl...
~
~
~
Figure 2-20. Waveform Analysis
2-34
-+I5V
-
OV
2.6.5
Carriage Position Tachometer
Figure 2-21 is a partial schematic diagram showing the Carriage Position Tachometer and
associated circuits. Figure 2-22 shows waveforms taken in these circuits.
The design of the transducer on the carriage servo motor is such that each complete cycle
of the sawtooth waveform input to these circuits represents 2/100 inch (.508 mm) of
carriage travel, or two "track crossing" points. Thus, while these inputs do not vary in
amplitude, they do vary in frequency. This variation (or modulation) follows actual
carriage speed, with the waveshape itself tracking carriage position.
Refer to Figure 2-22. Modules E39 and F39 are high speed comparators. Their inputs are
the triangular CAR POS SIG waveforms A, Band C. Their actual outputs are squarewaves. The duration of these squarewaves follows the frequency of the sawtooth inputs.
They pass through inverters, whose outputs are waveforms E and F from comparators F39
and E39 respectively, and are sent to the MXI board as CAR POS A and CAR POS B. The
CAR POS SIG #3 is also sent through inverting amplifier C18-10, comparator F39-7, and
inverter E27-8 to develop the CAR EVEN signal also supplied to the MXI board.
The CAR POS A and B squarewaves are also channeled through a series of inverters and
NAND gates to supply waveforms F, G, H, and I. These signals are used to control the
feedback FETs C39-7, -10, -2 and -15 respectively.
The three CAR POS SIG triangular waveforms, plus CAR POS SIG #3 inverted are supplied
to the control FETs through differentiating networks. Figure 2-23 shows the waveforms
taken at the capacitor-resistor junction in each network. The control pulse to each FET
will turn the FET on to pass either the positive or the negative part of the differentiated
signal, depending on the direction of carriage movement. Since carriage velocity is seen
here as frequency, the higher or lower the velocity, the higher or lower the level of the
differentiated squarewave. The voltage levels of the outputs of the FETs are applied one
at a time to the input (pin 1) of amplifier A39-12 representing carriage velocity. A39-12
inverts the input and presents it to the carriage velocity summation junction (pin 7) of
~ervo Summation Amplifier A39-10 as negative feedback.
_1
I~~~~~~~~~~~~~~~~~~~~~~~~~~~~~o~~.~m#1
...-v,..
~~
~
__-+~~~~~~~~~~-+-+-~--.-~~~~~-------o9--=--r...+-----"--~--+-__+-~--+-~--~~--_{)!53
Figure 2-21. Carriage Position Tachometer
2-35
CAR. POS A
A
B
C
o
E
F
CAR.
P~S
G
CAR.
P~S
CAR.
P~S
3
CAR.
P~S
3
H
I
Figure 2-22. Carriage Position
Tachometer Waveforms
Figure 2-23. Carriage Position
FET Input Waveforms
2-36
I
2
2.6.6
Carriage Velocity Command
As discussed earlier, the printer microprocessor looks ahead in its buffer, determines the
carriage direction and velocity requirements for the upcoming print situation, and adjusts
its commands to the CARRIAGE SERVO board accordingly. The velocity command
arrives on the CARRIAGE SERVO board in digital form, and is converted to an analog
form which is then used to develop a velocity command voltage level. This voltage level
is then adjusted in polarity to set the direction of carriage movement, and applied to a
summing junction where it is summed with a negative feedback voltage. The resultant is
amplified and sent to the CARRIAGE POWER AMPLIFIER board as CAR SERVO ERROR,
a signal whose level and polarity is used to generate the carriage servo motor drive to
propel the carriage in the right direction at the right velocity.
2.6.6.2
The D-A Converter
Module H39, a D-A Converter, converts the binary input from the printer microprocessor
to a current. The amplitude of this current represents the carriage speed command. The
circuit's operating parameters are set by the value of the resistor in the +5V supply line to
pin 14 such that when all digital inputs are high, the output current at pin 4 will be 99.696
of the reference current (approximately 1 rnA) on pin 14. When all digital input signals
are low, the output on pin 4 will be 0 rnA. G39-10 is a current-to-voltage converter, with
its instantaneous output voltage level stored in capacitor G34 for reference between
updating inputs from the microprocessor.
2.6.6.3
Carriage Direction Switches
The output of the D-A Converter circuit at G39-10 is applied to the FWD control FET at
B39-14, and to inverting amplifier G39-12. The inverted output from G39-12 is then
applied to the REV control FET at B39-3. The outputs of both FETs are then tied to the
carriage velocity summation junction (pin 7) of Servo Summation Amplifier A39-10.
2.6.6.4
Carriage Linear Mode
An input from the printer microprocessor, +CAR LIN MODE, is used to control FET B39-7.
Whenever the carriage is stopped, this signal is issued by the printer microprocessor to
turn on the FET and apply the CAR POS SIG #2 signal directly to the summation junction.
This signal serves to electrically detent the carriage servo motor to lock the carriage in
position.
2.6.6.5
Servo Summation Amplifier
The Servo Summation Amplifier A39-10 has four inputs; speed signal forward, speed signal
reverse, carriage linear mode signal, and tachometer negative feedback signal. The first
three control carriage movement. The feedback stabilizes the servo system, and causes
the carriage to accelerate (or decelerate) and move at the command speed without
variation due to changes in mechanical load. The output, CAR SERVO ERROR, is limited
to approximately 5.6 volts peak, and is negative for forward and positive for reverse
carriage movement.
2-37
CAR. POI SI6 tit 2
CAR. LINEAR MODE DO
U--------::.t .;!!O-............-~'-----~~~~~!!!......2!~~2..--!.W
SUIIIIED FEED UCK
CAR. FWD 37 U---------------~ ~~~.+=:Mf
CAR. REV 18
+I5VF
16 CAR. SERVO ERROR
VELDCITY • DATA 12
VELOCITY I DATA ID
VELOCITY 2 DATA 14
VELOCITY 3 DlTA 10
YElDCITY 4 DlTA ..
WLDCITY S DaTA 7
VILDCITY • DATA •
VELOCITY 7 DlTA II
Figure 2-24. Carriage Velocity Command Circuits
~N
MOTION
~
SENSOR
·r·-_-_-~~~-~~,~~q~~~I-~~~<21~~~~~L~E~D~~~--------~-------.'~2'
I ...... illMT.latI/OMI :r~
LED RET
__ ~_~~~_1:"" ••• :'
~~ £
-
- ----~
.~
CARRIAGE
SERVO
BOARD
9ENSORDAIVE
FROM
CARRIAGE
POSITION
TACHOMETER
RIBBON MOTION SENSOR
DRIVE 210---------------------...
RETlI'tN22
~
......
n.
51-INHIBIT (RIBBON JAM)
I ••
:!O
+RES~~~W~:!~:~ ~::::::::::::~~~E~I.~.-'~--~-------------------J---------------------------+-+~
(NOT USED) 17
(NOT USED) 26
'>t"------------------------------------------------------------------------.J
083-052
Figure 2-25. Ribbon Motion Sensor
2-38
2.6.6.6
Ribbon Motion Sensor (RMS) [See Figure 2-25]
The Ribbon Motion Sensor (RMS) circuit consists of a light sensitive phototransistor and a
Light Emitting Diode (LED). This circuit works in conjunction with an idler wheel located
inside all matrix ribbon cartridges. This idler wheel has reflective spokes and is driven by
the physical motion of the ribbon moving through the ribbon cartridge. When the ribbon
cartridge is installed correctly, an access hole in the cartridge is aligned directly over the
RMS circuit to allow light from the LED to be reflected back from the idler wheel's
reflective spokes to the light-sensitive transistor. The phototransistor ~onverts these
"light flashes" to electrical pulses and routes these pulses to the CARRIAGE SERVO board
via the RMS DRIVE input at pin 21. On the CARRIAGE SERVO board, these ribbon
motion pulses travel through comparator E39-7 and its associated circuitry to appear on
pin 14 of counter modules B29 and C24. The CAR POS A pulse train from the Carriage
Position Tachometer circuit is applied to input pin 5 of counter C24 whose output on pin
12 is connected to input pin 5 of counter B29. The output of these two counter modules on
B29-12 is a pulse for every 256 -CAR POS A pulses at C24-5. (256 -CAR POS A pulses are
the equivalent of 25 characters spaces of carriage movement.) The RMS pulses at pin 14
of the counter modules are Clear signals that reset both counters to zero. This action of
continuously resetting the counters keeps the B29-12 output high.
Should the ribbon fail to move for any reason, the RMS pulses used as Clear signals to the
counter modules are not produced. Any subsequent carriage movement soon accumulates
the 256 counts needed to present a negative-going pulse at the output of B29-12. This
negative-going pulse sets the G9/D23 latch output D23-6 low and causes the -INHIBIT
signal at E18-3 to become active (low). The -INHIBIT = low signal is loaded into the Port
5 Status latch on the MXI board and read by the terminal microprocessor.
When an active (high) +RESTORE (INT 0) signal from the MXI board is applied to AND
gate E18-6, the G9/D23 latch is reset and the -INHIBIT signal becomes high (inactive)
again.
2-39
1
S2
048
R
I
i
1
} FEED BACK
S4
F41
T
-15V
Figure 2-26a. Carriage Power Amplifier Simplified Diagram
__-.
.,.
CM.
MOTOR
DRIVE
Figure 2-26b. Carriage Power Amplifier
2-40
2.7
CARRIAGE POWER AMPLIFIER BOARD, PART NO. 40525-XX
This assembly includes the Carriage Servo Power Amplifier, the Paper Feed Drivers, and
the Power Monitor circuit. It is located in Slot D, and has a finned heat sink attached to
it, to help cool the several drive transistors.
NOTE
Do NOT stand the terminal on its rear heat sink panels. The
finned heat sinks are mounted on plug-in circuit boards which
can be easily damaged by this practice.
2.7.1
Carriage Power Amplifier Circuit
This circuit supplies and controls current flow to the carriage servo drive motor. The
circuit is designed as an H bridge, allowing all current to flow through the motor from
supply to supply instead of through circuit ground. This feature helps to avoid circuit
noise problems. Figure 2-26a illustrates the circuit in simplified form, where certain
transistors (final drivers) in the actual circuit are represented as switches. It may be seen
that closing switches S2 and S3 will cause electrons to flow through the motor left to
right.
Refer to Figure 2-26b. Assume a CAR SERVO ERROR signal input of +1 volt for a
commanded motor current of 1 ampere. The output from operational amplifier B55-6 will
be low, and this will place a low potential on the base of transistor G58 to disable the
Pulse Fwd circuits, and on the emitter of transistor G73, to turn G73 off. G73 being off
turns transistor E70 off, which turns transistor E65 on to turn on the Pulse Rev switching
transistor F6 3.
The error signal is also supplied to amplifier A50-6. The A50-6 output will be negative
with a positive input, which will turn transistor D45 off and transistor E44 on to turn on
Drive Rev switching transistor D48.
2-41
Referring again to Figure 2-25, transistor D48 is shown as switch S2, while transistor F63
is shown as switch S3. Turning these two transistors on establishes a current path from
the +15 volt supply through D48, resistor C53 (R), the drive motor, and through F63 to the
-15 volt supply.
Figure 2-27 is a simplified schematic diagram of the feedback circuit. This circuit
includes the .1 ohm resistor C53 (R) located in one of the lines to the servo motor, across
which is connected a precision balanced 10K resistor network and difference amplifier
B62-10. The value of resistor C53 is such that its voltage drop to current ratio is 1 to 10.
(.1 volt drop equals 1.0 ampere of motor current.) Difference amplifier B62-10 presents
this voltage to the servo error input terminal 2 of amplifier B55-6. The two signals are
summed at a ratio of 10 input to 1 feedback. As current through the drive motor
approaches the commanded level, the output of B55-6 will diminish. When motor current
matches command current, the Pulse Rev switching transistor F63 will be turned off. This
removes motor current, which removes feedback voltage, and F63 is turned back on again.
The circuit will oscillate in this manner to maintain motor current at the commanded
level.
Should the Power Monitor circuit detect an input voltage error, it will generate a -CAR
SERVO DISABLE signal. This signal will turn transistor E77 on which results in turning
Pulse Fwd and Pulse Rev transistors F47 and F63 off to disable carriage servo movement.
10K
10K
ERROR
FWD/REV.
>-...-~
PULSE
AMPLIFIERS
OTHER
CKTS
Figure 2-27. Simplified Feedback Circuit
2-42
~IN>-----------------------------------------~
- ..
+lIV
+IIIS
+IIIS
I0Il
2IC
--IllS
JIIIIIER FEED
DISAIJU
Figure 2-28. Power Monitor Circuit
2.7.2
Power Monitor Circuit
The purpose of this circuit is to inhibit all printer functions any time one or more of the
three supply voltages of +5, +15, or -15 volts drops below a level where printer
malfunction or component damage could occur as a result of the low voltage.
The circuit operates as follows. As power is applied, transistors B12 and B13 are off.
Three divider networks begin to sample the +5, +15, and -15 volt levels being supplied:
zener diode B5 and resistor All sample the +5 volt input; zener diode A7 and resistor A9
sample the +15 volt input; and zener diode B7 and resistor B6 sample the -15 volt input.
As these voltages approach their appropriate values, diodes A12, A8, B8 and B9 (operating
as an AND gate) are reverse biased, and transistors B12 and B13 turn on. Up to this time
transistor B16 has been on and B22 off. When transistors B12 and B13 turn on, capacitor
A22 begins to charge through resistor A24 and the emitter/base junction of B16, and
transistor B22 is biased off. With transistor B22 off, transistors A30, B23, C36, and C34,
are all biased on, and their outputs are all clamped low. This condition disables all printer
functions as outlined. This condition will continue until capacitor A22 has charged
sufficiently to turn transistor B22 on.
At the end of the delay (approximately 25 ms), transistor B22 is turned on discharging
capacitor A22 and turning transistor B16 off. It will also turn off transistors A30, B23,
C36 and C34, allowing all their outputs to go high. This removes the circuit disable
clamps, starts the program counter in the printer microprocessor, and initiates a Restore
sequence.
Any subsequent interruption in, or depreciation of, any of the three input voltages
monitored, will disable the printer by action of this circuit. Complete restoration of
power recycles this circuit, putting the printer back in operation with a Restore sequence.
2-43
2.7.3
Paper Feed Drive Circuit
Figure 2-29 is a partial schematic diagram of the Paper Feed Drive circuit. Figure 2-30
shows waveforms taken in the circuit. The circuit consists of two identical channels A
and B, each feeding a field winding in the paper feed stepping motor. As shown in Figure
2-30, the signals in channel A lead the signals in channel B by 90u • This relationship
produces clockwise rotation of the stepping motor shaft (as viewed from its shaft end) for
upward paper movement only. Since the A and B channels are identical, only channel B
will be discussed here.
MPER FEED DISABLE
'>---41~~...--~
88
14
___
RETURN
eM
14
n
PiU'ER FEED DRIVE
a
>----~~~~~;1V~.IS~..-,.IIr---remainder of this seetion contains
component location/identification infOrmation that will be useful in troubleshooting.
MOTE
Preventive Maintenanee, when performed aeeording to the
proeedures listed here, will not -&ffeet the Diablo 1IIU'I'8IIly.
However, any module replacement or adjustment ImsueeessfuIly
attempted that results in dam~ to the equipment will render
the warranty mil and void. All time and material required to
restore the tenninal to workiJJg order will be biDed at the
prevailing rates.
3.1.1
General Rules
There are a few general rules that should always be observed:
(1)
Never remove or install any circuit boards, or conneet or disconneet any plugs, while
power is OIL
(2)
Applying power to the tenninal initiates a printer Restore sequenee, whiell ineludes
carriage movement. Make sure the carriage is free to move to the left before
applying power.
(3)
Whenever the access cover is removed, be careful not to brush against the cove~
open switcb: operating this switch could allow the carriage to move suddenly, which
could cause an injW'Y. When operating the terminal with the aecess cover removed
(and the cover-open switch in the noverride" position), keep fingers" hair, etc., away
from the printer.
(4)
Never remove the top cover without first disconnecting the power cord from the
wall outlet.
(5)
The print head does not need cleaning 1Blder normal operating conditions. Only
unusually severe operating conditions will make print head cleaning necessary, in
which case the problem should be referred to your Diablo Service Represenative.
3-1
(6)
Do not use alcohol to clean the paper feed rollers, or any other rubber parts.
Alcohol dries out the rubber and hardens it, eventually resulting in paper feed
problems. Use "Fedron Platen Cleaner" or its equivalent.
WARNING
Fedron Platen Cleaner and similar products are flammable,
and have a very low flash point.
(7)
Take care not to touch plastic parts with platen cleaner. These products are usually
harmful to plastics. Use alcohol to clean plastic parts.
(8)
When tipping the HyTerm up to gain access to its underside, first position the power
cord and EIA cable to the sides so they will not be in the way. Make sure the
surface behind the HyTerm is flat and free of any foreign objects. Then tip the
HyTerm up approximately 70° so that it balances on the rear edge of its bottom
cover. Do not allow the table surface or any objects to apply pressure to the finned
heat sinks on the rear; since these heat sinks are mounted on the power amplifier
boards, any pressure could damage these circuit boards or the mother board and its
connectors. Also, while the HyTerm is tilted up in this manner, hold onto it with one
hand to prevent it from falling.
3.1.2
Top Cover Removal/Replacement
Removal of the top cover and its accessories is a prerequisite to most HyTerm
maintenance procedures.
REMOVAL
Refer to Figure 3-0.
(1) Turn the power off and unplug the cord from the ac outlet.
(2) Remove the top cover accessories: the access cover and the plastic platen
skirts over the ends of the platen shaft (see Figure 3-0).
(3) Remove the platen: grasp the platen knobs in both hands, press down on the
platen latches with your thumbs, and lift the platen straight up.
(4) Release the top cover by pulling forward on the two latches inside the cover at
both sides, just in front of the platen. Lift the top cover straight up and free
from the printer.
REPLACEMENT
(1) Remove the platen from the printer.
(2) Install the top cover and accessories by reversing the Removal procedure above.
3-2
3.1.3 Tools
A basic hand tool assortment, including regular and Phillips screwdrivers, small open-end
wrenches, pliers, and Allen setscrew wrenches is needed for any maintenance. Tools such
as screw starters, offset screwdrivers, etc., are not essential, but will make some jobs
much easier. In addition, the following tools are needed for driving and removing the
special screws used in the terminal and for performing printer adjustments.
Diablo Part No.
Description
R
(1) T15 TORX Screwdriver
or T15 Driver Bit
(2) T15 TORX Key Wrench
(3) Circuit Board Extender
(4) 3M Connector Extractor Tool
(5) Molex Connector Extractor Tool
(6) Molex Connector Pin Extractor Tool
(7) Platen Adjustment Tool
(8) Tensiometer, Electromatic Equipment
Co. Model DXX-lKD or equivalent,
calibrated for Diablo cable.
70826-03
70826-01
70826-05
40539-01
70832
24853
13197
24708
For detailed troubleshooting and repair of circuit boards, the usual oscilloscope, soldering
iron, etc., are needed, plus the following special tools:
Description
Diablo Part No.
(1) Transducer Cable Extender
(2) Carriage Motor Cable Extender
(3) 48V Return Cable Extender
3.2
40666
40667
24789
PREVENTIVE MAINTENANCE
3.2.1 Supplies
The following supplies and lubricants are necessary for proper preventive maintenance.
The part numbers listed below are Diablo part numbers.
1.
2.
3.
4.
5.
6.
7.
8.
Fedron Platen Cleaner, or equivalent.
No. 99000-01 Alcohol Pads (91% Isopropyl alcohol), or equivalent.
Lint-free Wipes.
Clean, low pressure compressed air.
No. 70825-01 2-oz tube of Multipurpose grease.
No. 70364 Polyoil (light white grease).
No 70243 Light Oil (Shell Turbo 27).
Loctite
CAUTIONS:
*
*
*
TORX
R
Do not use alcohol on any rubber parts.
Do not use platen cleaners on plastic parts.
Platen cleaners are flammable, and have a very low flash point.
is a registered trademark of Camcar Screw & Mfg.
3-3
3.2.2
Cleaning and Inspection
It is difficult to state specific rules concerning the frequency of preventive maintenance
inspections, because of differences in the hours of usage and environmental considerations
from one machine to another. It is recommended, therefore, that the following preventive
maintenance procedure be performed at least every 500 hours of printing time, or every
six months, whichever occurs first:
(1)
Remove power from the terminal. Remove the top cover (see 3.1.2). Reinstall the
platen once the top cover has been removed from the HyTerm.
(2)
Thoroughly inspect the printer for signs of wear and loose or broken hardware.
Check carriage cable for signs of wear, and cable pulleys for loose bearings. Check
platen for looseness or wobble. Check platen drive gears for looseness. Check the
carriage for looseness, wobble, or accumulation of foreign material on the rails,
which might cause uneven movement of the carriage.
(3)
Remove the platen and the paper cradle and inspect them and the plastic paper
clamp for signs of wear.
(4)
Clean the printer thoroughly, using alcohol-saturated cleaning pads and wipes.
Remove accumulations of paper residue, ink, dust, etc., with special attention to
carriage rails and pulley grooves.
(5)
Clean the paper bail tires and paper feed rollers with a good platen cleaner which is
non-injurious to rubber products, such as "Fedron" Platen Cleaner. Do not use
alcohol to clean these items.
*(6)
Clean the rest of the terminal as required -- remove all dust and foreign material.
*(7)
Inspect the entire machine for loose hardware and frayed wires or cables.
*(8)
Check to be certain that the fan is operating.
*(9)
Check all power supply voltages (see 3.4.3).
Items above marked with an asterisk (*) should be checked on every machine visit, not
only at the P.M. inspection.
3.2.3
Lubrication
Lubricate the various parts of the cleaned and inspected printer according to the following
schedule. DO NOT exceed this schedule. Too much lubricant is often worse than none at
all! (To be done every six months or if printer has not been used for more than a week.)
3-4
®----
Figure 3-1. Carrier System Lubrication Points
3.2.3.1
Carrier System
Refer to Figure 3-1. Lightly grease all the points indicated in this procedure with Diablo
no. 70825-01 grease.
1.
Paper Feed Roller Shaft Pins @
.
2.
Platen Position Lever Detent Plate (inside surface)
3.
Platen Position Slide Plates (carrier frame)
with the lever moved limit to
limit. Also grease all points of the contact with pivots, eccentrics, guides, etc.
4.
Platen Position Torque Shaft Ends, Bearing Surfaces, and Spring Loops
5.
Paper Release Lever Tab Ramp and Shaft Piviots
6.
7.
Paper Bail Pivots @ .
©,
®.
®.
Paper Release Torque Shaft Pivots and Arm Slots ® .
3-5
@.
Figure 3-2. Carriage System Lubrication Points
3.2.3.2
Carriage System
Refer to Figure 3-2. While this system is to be lubricated at normal 6 month or 500 hour
intervals, it may need additional attention if the printer has not been used for some time.
1.
2.
3.
4.
5.
6.
7.
Carriage Rails @ - Clean the rails with alcohol wipes.
Carriage Rear Bearings
Place 4 - 5 drops of No. 70243 oil on the rail
beside each bearing. Move the carriage back and forth manually to spread the
oil and saturate the felt washers inside each bearing.
Carriage Front Bearings
Swab the top and bottom rail surfaces with No.
70243 oil. Leave a thin film only - no droplets.
Ribbon Cartridge Latches
Apply one small drop on No. 70243 oil to each
latch pivot, and moisten the latch return spring ends.
Ribbon Drive Capstan
Apply one drop of No. 70243 oil to the capstan
drive blade and hUb. Work the blade up and down manually a few times to
spread oil to the blade shaft in the hUb.
Ribbon Drive Clutches
Apply one very small drop of No. 70243 oil to each
clutch pulley shaft end. Wipe all gears with the oil. *Oil the clutch springs by
spreading oil lightly across their surfaces.
Ribbon Drive Pulley @ - Apply one drop of No. 70243 oil to the upper end of
the pulley shaft.
®-
©©®-
®-
3-6
Figure 3-3. Platen System Lubrication Points
3.2.3.3
Platen System
Refer to Figure 3-3.
1.
Paper Feed Idler Gear (A)- Inspect the large felt washer behind this gear. If it
is becoming white in co'fof, saturate it with 70364 Polyoil.
2.
Platen Latches (Bl - Lightly grease the contact area between these arms and
the carrier side ~mes with No. 70825-01 grease.
3.
Platen Hubs (2) - Apply one drop of No. 70243 oil to the shaft between the
knob end and dF(ve gear hub.
NOTE
This procedure is applicable to optional pin feed platens. The
pin cam area of these platens is self-lubricating, and does not
require additional lubrication for the life of the unit.
3-7
(D). CAR PWR AMP
HAMMER DRIVER (H)
C) CAR SERVO
(B) PROCESSOR
XMEM (F)
CIRCUIT BOARD CLAMP
Figure 3-4. Circuit Board Locations
3-8
3.3 MODULE REMOVAL AND REPLACEMENT
Always make certain that the power cord is unplugged from the ac outlet before
attempting to replace any components or modules.
All modules have been assigned "assembly numbers" according to the system adopted by
the American National Standards Institute (ANSI) in their standard no. Y32.I6: "Reference
Designations for Electrical and Electronics Parts and Equipments." Table 3-1 lists all
major assemblies, and the smaller assemblies that are normally considered replaceable as
modules, along with their reference designations. These designations are used in the
remainder of this section and in the schematics and wiring diagrams to identify the
various assemblies.
Table ,3-1. Major Assemblies and Modules
Description
Assembly No.
(Reference Designators)
Ma trix Printer
Matrix Interface (MXI) Board
Processor Board
Carriage Servo Board
Carriage Power Amplifier Board
HPR03 Board
XMEM Board
Hammer Driver Board
Mother Board
Power Supply
Keyboard
Control Panel
Al
AlAI
A1A2
A1A3
A1A4
A1A5
A1A6
AlAS
A1A9
A2
A3
A4
3.3.1 Printed Circuit Boards
CAUTION
Never remove or install circuit boards or connectors while
power is applied to the HyTerm.
(1)
Turn the power off and unplug the cord from the ac outlet.
(2)
Remove the paper or forms from the printer. Remove the forms tractor if
applicable (see 1660 Product Description, paragraph 2.4.3).
(3)
Remove the top cover and accessories from the printer (see 3.1.2).
(4)
Remove the screw in the center of the circuit board clamp (see Figure 3-4) and
remove the clamp.
(5)
Locate the circuit board to be removed (see Figure 3-4).
(6)
Grasp the circuit board firmly at the two upper corners and pull it straight up,
taking care not to stress any existing cable connections.
(7)
Disconnect all remaining cables from the circuit board.
REPLACEMENT
(1)
(2)
Check all jumper positions and switch settings on the circuit board. Verify that the
board is configured correctly.
If the HPR03 board is being installed, first attach the keyboard cable to the P2
connector on the circuit board.
3-9
·
LD
I
M
Q)
~
::s
bD
......
~
3-10
(3)
(4)
Holding the board with the component side toward the front of the printer (toward
the platen), insert the circuit board into the guides and slide it all the way down
until it contacts the connector on the motherboard.
Using firm, equal pressure on both upper corners of the board, push it down so that it
is fully seated into the socket.
NOTE
If excessive resistance is encountered, check to make sure the
proper board is being installed in the socket: all boards are
keyed so they will not fit in the wrong socket (refer to Figure
3-4).
(5)
Replace the platen, insert a sheet of paper, and apply power to the HyTerm. Test
the HyTerm at this time.
(6)
After determining that the terminal is operating properly, remove power and install
the circuit board clamp. Remove the platen and install the top cover and
accessories (see 3.1.2).
3.3.2
Power Supply
REMOVAL
(1) Turn the power off and unplug the power cord from the ac outlet.
(2)
(3)
(4)
Move the HyTerm to a location where both the top and bottom are accessible when
the HyTerm is tilted back (preferably a work bench).
Remove the top cover following the procedure in 3.1.2. Remove the paper cradle
(see Figure 3-5).
Tilt the HyTerm up so it is resting on the rear edge of the bottom cover, and remove
the screen-like bottom pan. Loosen the three rear screws and remove the three
forward and two side screws; then slide the bottom pan off the HyTerm. Lay the
HyTerm back on its feet.
CAUTION
When tipping the HyTerm up, be certain to use a flat surface,
with no foreign objects in the way. Any small object could
cause pressure to be applied to the rear heat sinks, which are
mounted on the power amplifier boards. Excess pressure on
these boards could damage the boards and/ or the mother
board.
(5)
Look down into the platen area of the printer and locate the power supply, which is
covered by an aluminum screen. Remove the four mounting screws from the top of
the power supply (see Figure 3-5). The supply will drop slightly and rest on the work
surface.
(6)
Tilt the HyTerm up slightly and reach underneath to hold the power supply with your
hand (to prevent it from falling). Then tilt the HyTerm all the way up so that it
rests on the rear edge of the bottom cover.
(7)
Slide the power supply out of the printer enough to access the terminal strip at the
right side of the power supply. Disconnect the wiring from the terminal strip. Set
the power supply aside and set the HyTerm down on its feet.
3-11
TBI
POWER
SUPPLY
+5V
GND
GND
+15V
~
I
......
-15V
to..:)
+48V
+ 48V
AC
{BLACK
FAN
WHITE
TO
TI7
TI6 Tl5
TI4 Tl3
Ti2
Til
RTN
013 -006
Figure 3-6. Power Supply Connections
REPLACEMENT
(1)
Tilt the HyTerm up on the rear edge of the bottom cover and connect the wires to
the power supply terminal strip as shown in Figure 3-6. Observe the caution about
tilting the HyTerm noted in step (4) above.
(2)
Swing the power supply into position inside the printer casting. Make sure all wires
and cables are routed correctly and securely.
(3)
Holding the power supply in position, insert the mounting screws through the cover
screen and the printer casting and start them into the threads in the power supply
frame. Start all four mounting screws.
(4)
Set the HyTerm back down on its feet.
screws securely.
(5)
Locate the power connections (+48V, +15V, -15V and +5V ) at the right side of the
mother board between the card cage and the rear right side of the bottom cover (see
Figure 3-25).
(6)
Plug the HyTerm into an ac outlet and turn the POWER switch on. Verify
that the HyTerm does a restore (carriage moves to left).
(7)
Using a voltmeter, measure the voltages between ground and each of the four power
connections on the motherboard. The voltages should read as follows when under
load conditions:
Tighten all four power supply mounting
+5V = +4.75 to +5.25 volts
+15V = +15 to +16 volts
-15V = -15 to -16 volts
+48V = +48.5 to +50.5 volts
If voltages do not read within the ranges above, see 3.4.3.
(8)
Temporarily install the platen and a sheet of paper and test the HyTerm for proper
operation by running a Self-Test routine and by entering data from the keyboard. If
operation is satisfactory, turn the POWER switch off and unplug the power cord.
(9)
Tilt the HyTerm up again and install the screenlike bottom pan by sliding it under
the three rear screws and then installing the remaining five screws. Tighten all
eight bottom pan mounting screws.
(10) Set the HyTerm down on its feet and install the paper cradle.
(11)
Replace the top cover and accessories (see 3.1.2).
(12)
Insert paper, apply power, and test the HyTerm thoroughly.
3-13
CONNECT WHITE WIRE
OF POWER CORD HERE.
CONNECT TO HPR03
BOARD "'2 CONNECTOR.
rn ~
CONNECT BLACK
WIRE OF POWER
CORD HERE.
CONNECT WHITE AC WIRE FROM
POWER SUPPLY T9 HERE.
(
I
({
~t
~ ~:::=:::F!!!!I
o
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!~~'
!!!!!!!!!!!!!.
~
I
I-'
e
~
N/O (NORMALLY OPEN)
CONNECT WHITE WIRE
FROM MOTHERBOARD
T8 HERE.
CONNECT BLACK WIRE
FROM POWER, SUPPLY
T8 HERE.
COM (COMMON) CONNECT
BLACK WIRE FROM MOTHERBOARD T3 HERE.
083-007
Figure 3-7. Control Panel Connections
3.3.3
Control Panel
REMOVAL
(1) Set the power switch to off and unplug the power cord from the ac outlet.
(2) Remove the top cover and accessories (see 3.1.2).
(3)
(4)
(5)
(6)
Remove the keyboard mask by lifting up on the forward corners of the mask until it
"pops" loose, then lift the mask from the keyboard.
Remove the four control panel mounting screws (two screws on each side of the
pane!).
Remove the HPR03 board from slot (E) of the mother board (see Figure 3-4);
disconnect the control panel cable at the J2 connector.
Disconnect the remaining wiring on the rear of the control panel and lift the control
panel off the HyTerm.
REPLACEMENT
(1)
Connect the control panel wiring on the rear of the panel referring to Figure 3-7.
(2)
Connect the control panel cable to the J2 connector on the HPR03 board and install
the HPR03 board into slot (E) of the mother board (see Figure 3-4).
(3)
Set the control panel in place and install the four mounting screws and tighten
securely.
(4)
Install the keyboard mask by setting it in place and applying pressure on the forward
corners of the mask un til its "pops" securely into place.
Install the top cover and accessories (see 3.1.2).
Apply power and test the HyTerm.
(5)
(6)
3-15
3.3.4
Keyboard
REMOVAL
(1)
Turn the power off and unplug the power cord from the ac outlet.
(2)
Remove the top cover and accessories (see 3.1.2).
(3)
Remove the keyboard mask by lifting up on the forward corners of the mask until it
"pops" loose, then lift the mask from the keyboard.
Remove the four keyboard mounting screws (two on each side).
(4)
(5)
(6)
Disconnect the keyboard cable connector which is visible through an access hole cut
in the left side of the control panel.
Remove the keyboard by first sliding it to the right then lifting up on the left
forward corner and swinging the left side out first, then the right. Set the keyboard
aside where it will not be damaged.
REPLACEMENT
(1)
Set the right side of the keyboard into place and then swing the left side into place.
(2)
Connect the keyboard cable to the keyboard connector.
(3)
Center the keyboard on its mounting brackets and install the four mounting screws.
Tighten the mounting screws down securely.
(4)
Install the keyboard mask by setting it in place and applying pressure on the forward
corners of the mask until its "pops" into place.
(5)
Install the top cover and accessories (see 3.1.2).
(6)
Apply power and test the HyTerm.
Keyswitch Removal/Replacement
3.3.4.1
Once the keyboard has been removed from the HyTerm, individual keyswitches can be
replaced if necessary. The required tools for keyswitch replacement are a low-wattage
soldering iron, a solder removal tool, 60/40 rosin-core solder, and a long needle-nose
pliers.
CAUTION
When removing the key tops from the "Press-t
Z
~
o
«
o
...J
8
L",,~O
Figure 3-16. Carriage Drive Cable Routing
3-29
HEMOSTAT
CLAMP
CAPSTAN
Figure 3-17. Right-Hand Carriage Drive Cable Installation
LEAF SPRING
MOUNTING
SCREW PARTS
CABLE END
o
CABLE
RING
HUB
LOCKWASHER
083-055
Figure 3-18. Carriage Drive Cable Tension Spring Assembly
3-30
(8)
Refer to Figure 3-17. From the capstan, arrange the cable back to the right around
the right side pulley CW (bottom rear to front top ), and to the left and CW (front to
back) around the carriage drive pulley, with the cable in the drive pulley's upper
groove. It will be necessary to allow the capstan to rotate slightly.
(9)
Protect the carriage drive pulley with heavy paper, and grasp it with a hemostat
clamp as shown in Figure 3-17. Hook the hemostat clamp's lower finger ring over
the main frame servo motor shield as shown, where the motor's magnetism will help
to hold it in position. Rotate the capstan CCW to keep a slight tension on the cable,
and to locate the notch on the capstan's inside rim (closest to the motor) as near the
top as possible.
(10) Place the ball end of the second cable between the capstan and the main frame at
the lowest point of the capstan (the ball will not fit between the capstan and the
main frame at any other point). Pull the cable up until the ball can be inserted into
the notch on the capstan's inside rim and insert the ball into the notch. Run the
cable directly over to the left side pulley. There should be no more than 1/4 turn of
this cable on the capstan.
(11) Arrange the cable around the left side pulley CCW (bottom rear to top front), and
back to the right. Carefully route the cable CCW (front to back and back to left)
around the carriage pulley in the lower slot of the pulley. Stretch the cable to the
left, and thread its free end out through the cable hole in the left side frame.
(12) Assemble the hardware items on the free end of the cable, as it protrudes beyond
the side of the frame, in the order shown in Figure 3-18. Put the locknut on finger
tight only, and avoid twisting the cable.
(13) Refer to Figure 3-18. Mount the leaf spring onto the side frame with the screw, flat
washer, and lockwasher. Use a TORX T15 screwdriver to tighten the screw down
slightly and apply a light spring tension on the cables.
(14) Insert the small end of the TORX screwdriver down through the hub of the carriage
drive pulley; this prevents the pulley from flipping over and releasing the drive
cables. Carefully release the hemostat clamp. Holding the TORX screwdriver
handle upright, gently rotate the drive capstan CW to move the carriage pulley left,
to a position just to the right of the carriage servo motor, where the pulley hub is
accessible up through the bottom alongside the motor. Install the hemostat clamp
(with heavy paper protector for the pulley) as shown in Figure 3-13b, and remove the
TORX screwdriver.
(15) Place the spacer [removed in step (4) above] on top of the carriage drive pulley with
the shoulder extending down into the center of the pulley. Position the carriage
subassembly over the clamped carriage drive pulley, and insert the shoulder screw
through the pulley and spacer, and into the mounting hole on the carriage. Using a
TORX T15 screwdriver, tighten down the shoulder screw and remove the hemostat
clamp.
(16)
Perform the printer adjustments described in section 3.4.1.
(17) Reinstall the printer into the bottom cover (see 3.3.5 ).
(18) Replace the top cover and accessories (see 3.1.2 ).
(19) Apply power and test the HyTerm carriage movement while printing.
3-31
T6
T5
T4
T7
T8
T9
TOP VIEW
""
""
I
IS)
Diablo Sy,Itlm$
:", .,~C:=-=_!~J
013-00'
Figure 3-19. Mother Board Connections
Mother
3.3.11
Bo~rd
REMOVAL
(1)
Turn the power off and unplug the power cord from the ac outlet.
(2)
Remove the top cover and accessories (see 3.1.2).
(3)
Remove the printer from the bottom cover (see 3.3.5).
(4)
Using a nut driver, remove the circuit board clamp; disconnect and remove all the
circui t boards.
(5)
Stand the printer up on the front of its main frame, with the bottom facing front
(toward you).
(6)
Disconnect the Molex plug from the mother board located at the left side frame (the
right side as you view it).
(7)
Using a TORX T15 screwdriver, remove the two rear shock mounts from the printer.
(8)
Using a TORX T15 screwdriver, remove the two mother board mounting bracket
screws from the right-side frame and three from the left-side frame. Remove the
remaining six mounting screws from the bottom center of the mother board.
(9)
Carefully flip the mother board over to expose the circuit board sockets and wire
connections. Disconnect all the wire connections from the mother board and cut the
necessary tie wraps to free the mother board.
REPLACEMENT
(1)
Refer to Figure 3-19. Connect all wire and cable connections to the mother board
and replace the necessary tie wraps.
(2)
Set the mother board in place and check that all wires and cables clear the mother
board and frame, and are arranged properly to reach their respective connections.
(3)
Using a
screws,
bracket
bracket
(4)
Using a TORX T15 screwdriver, install the two rear printer shock mounts.
(5)
Connect the Molex connector at the left-side frame to its mate on the mother
board.
(6)
Place the printer back down on its feet and install and connect all the circuit boards
and their wire and cable connections.
(7)
Reinstall the printer into the bottom cover (see 3.3.5).
(8)
Replace the top cover and accessories (see 3.1.2).
(9)
Apply power and test the HyTerm.
TORX T15 screwdriver, install the six bottom center mother board mounting
then the three left-side frame and the two right-side frame mounting
screws (a cable clamp is installed on one of the left-side frame mounting
screws). Tighten down all the mounting screws.
3-33
3.4
ADJUSTMENTS
The HyTerm seldom requires readjustment due to ordinary wear, and no adjustments
should be attempted unless a malfunction indicates a specific need. But readjustment is
routinely required whenever any of the following components or subassemblies are
changed, or where adjustments are distributed to facilitate other maintenance:
(1)
(2)
(3)
(4)
(5)
Print Head
Paper Carrier Subassembly
Paper Feed Motor
Carriage Subassembly
Carriage Drive System
(6)
(7)
(8)
(9)
(10)
Ribbon Drive System
Paper Clamp
Bottom Feed Paper Chute (option)
Cover-Open Switch
Paper-Out Switch
Only the control panel's Alarm Volume adjustment can be performed at will, without
affecting operation or other adjustments.
3.4.1
Printer Quality Testing
3.4.1.1
Print Registration
1.
Column Registration:
The maximum deviation between identical characters in the same column is .010 inch (.254mm)
when printing in one direction; .020 inch
(.508mm) when printing bidirectional.
2.
Line Registration:
The maximum deviation between identical characters in the same line is .010 inch (.254mm).
[ Does not apply to first character of a line.]
NOTE
Test methods for the above are totally related to the proper
alignment and handling of the paper or form used.
3.4.1.2
Print Quality Test
The print quality test below is a method of testing the printer for possible misalignment.
But print quality is not attributed to printer alignment alone. Paper thickness, number of
copies, the condition of the ribbon, and the position of the Platen Adjust Lever all affect
print quality as does the condition to the print head, the straightness of the carriage rails,
and the roundness of the platen. Therefore, proper assessment of print quality requires
that print samples for evaluation be obtained under standardized conditions. Tests should
be made using a new ribbon cartridge on a good grade of bond paper with the Platen
Adjust Lever in the second (from the front) detent position.
1.
Prepare the printer as described above. (Install a new ribbon cartridge
and one sheet of bond paper; set the Platen Adjust Lever to the second
detent from the front.)
2.
Power up and print a few lines of random characters to allow the ribbon
cartridge to stablize.
3.
Print a full (132 character) line across the page that includ~s several of
the following characters: upper-case E, F, T, Z, and lower-case g, j, p, q,
and the underscore.
3-34
4.
Observe the print sample for clear character recognition and uniform
character intensity across the entire print line. Observe the characters
for uniform dot density (or character fill) and edge definition (see Figure
3-20) within a maximum dot edge variation of .003 inch (.076 mm).
The following conditions are indicators of possible printer misalignment:
*
*
*
*
*
Characters are too light or too dark.
Characters with flat tops (E, F, T, and Z) are faded or lighter along the top
edges.
Characters extending below the print line (g, j, q, and the underscore) are faded
or lighter along the bottom edge.
Characters are light or spotty at one end of the print line when compared to the
other end.
Characters are light or spotty over the entire length of the print line.
: - .OO3"MAX.
L('076mm)
~r-~-i-~-i-~~-:;:r:;;;;===~t==
@oooooo
0000000
o
00
000
.OO3"MAX. (.076mm)
Figure 3-20. Dot Matrix Character Edge Variation
3-35
3.4.2
Printer Adjustments
Because some adjustments affect others, the printer adjustments should be performed in
the sequence outlined in this section.
3.4.2.1
Carrier Assembly
1.
Carrier Assembly Bias Shaft @: Check for axial movement of .001 inch (.025 mm)
± .0005 inch (.0127 mm). Adjust the position of the collar on the left end of the
shaft as required to achieve this dimension.
2.
Platen Position Torque Shaft
Check that the set screws in the eccentric
collars
at each end of this shaft are aligned vertically with each other when the
Platen Adjust Lever (D) is fully forward (in first detent), and that the shaft end play
is .001 inch (.025 mm) ± .0005 inch (.0127 mm). Adjust one or both eccentric end
collars as required to achieve this dimension. Failure of eccentric collars to align as
described indicates that the torque shaft is possibly twisted, in which case the
proper lateral alignment of the platen will be impossible.
3.
Move the Platen Adjust Lever @ back and forth. A positive detenting force must
be felt for each position. Adjust the detent plate
as required to achieve an even
de tenting action. The carrier assembly must move equally at both ends within .002
inch (.051 mm) in increments of .005 inch (.127 mm) ± .002 inch (.051 mm) between
detent positions.
©
® :
®
Figure 3-21. Carrier Assembly Adjustment Points
3-36
Figure 3-22. Paper Feed Adjustment Points
Paper Feed Assembly
3.4.2.2
Refer to Figure 3-22 for Paper Feed adjustment points.
With the Paper Release Lever @ fully forward, the Paper Feed Rollers @ must clear the
Platen
by .08 inch (2.03 mm) minimum. The paper feed system may be adjusted as
follows to achieve this and other goals:
®
1.
Insert four sheets of standard forms paper (.012 inch or .305 mm) and move the
paper release lever
fully rearward.
2.
Ensure that the torque ~ft arm tabs
roller support arm slots \SJ .
3.
Ensure that the paper release actuator @ is touching the ramp on the paper release
lever
Loosen the actuator's set screw and adjust the actuator to achieve this
condition, then retighten the set screw.
4.
Remove the four sheets of paper, and insert one strip of paper 1 inch (25.4 mm)
wide, or a .004 inch (.102 mm) shim, between the front paper feed rollers and the
platen. Check that both platen and rollers rotate when the strip, or shim, is pulled
free. Repeat for all rollers, front and rear. If no rotation occurs, the torque shaft
arm Tabs B have been pushed down too low.
®
® are touching the lower edge of the feed
®.
3-37
Figure 3-23. Platen Drive Adjustment Points
Platen Drive Assembly
3.4.2.3
Refer to Figure 3-23 for Platen Drive Assembly adjustments points.
must have between
With the paper feed motor drive gear @ locked, platen drive gear
.0005 inch (.0127 mm) minimum to .002 inch (.051 mm) maximum play, including idler
gear
1.
Loosen the paper feed motor mounting screws @ , and remove the platen.
®
©.
2.
3.
4.
®
©
©
Locate the idler gear
and turn the eccentric
counterclockwise ONLY until a
and motor gear @. (Clockwise
minimum backlash is obtained between gear
rotation of this eccentric will make proper installation of the platen impossible.)
for no binding effect for a full 3600 of rotation.
Check the idler gear
Install the platen. Rotate the paper feed motor mounting plate around mounti~
screw @ to achieve th~ear play dimenisions described above between gear~
and
Tighten screws ® .
©
©.
3-38
1
.0006" t..OOO4"
(.015mmi: .OIOm.)
Figure 3-24. Front Guide Bearing Adjustment Points
3.4.2.4
Carriage Front Guide Bearing Assembly
Refer to Figure 3-24 for Carriage Front Guide Bearing adjustment points.
Under normal operating conditions and preventive maintenance activity, the carriage
sliding bearings should not require corrective maintenance. All carriage assemblies
including replacement units have their front bearings carefully adjusted at the factory,
and should not require further post-installation adjustment in the field. Malfunction in
this area, however, can effect carriage movement and print quality. If the carriage
assembly is replaced for any reason, the front bearing should be checked for proper
clearance and, if necessary, adjusted as follows:
1.
Make sure the upper bearing stud @ is firmly tightened.
2.
3.
4.
Adjust the lower bearing eccentric (B) as required to achieve a clearan~of .0006
inch (.015 mm) ± .0AQ4 inch (.010 min) between the lower bearing block \S) and the
printer's front rail ® .
Test the bearing clearance at several points along the front rail to ensure that the
rail has not become worn.
Tighten eccentric @and lubricate the rails (see 3.2.3.2.).
3-39
3.4.2.5
Platen-To-Print Head Adjustment
The Platen-to-Print Head adjustment is essential for optimum print quality. A special
Platen-to-Print Head Adjustment Tool (Diablo No. 24708) must be used along with the
following procedure:
1.
Remove the print head from the carriage assembly (see 3.3.6).
2.
Install the Platen-to-Print Head tool onto the carriage assembly as shown in Figure
3-25. The tool is correctly aligned for use when its two mounting thumbscrews
have been threaded in smoothly, completely, and are finger tight.
Figure 3-25. Platen-To-Print Head Adjustment Tool Installation
3-40
Refer to Figure 3-26 for Platen-to-Print Head adjustment points.
3.
Loosen the front eccentric lockbolt A on each side of the printer, and orient the
eccentrics as shown.
4.
Loosen the two rear eccentric clamp screws on each side of the printer with a
TORX T15 screwdriver, then loosen the rear eccentric clamp bolt B on each side
of the printer.
5.
Slide the carriage from end to end, stopping at several points to rotate the platen
while checking the tool-to-platen clearances. Check for an average of .010 inch
(.254 mm) ± .001 inch (.025 mm) clearance between the platen surface and the tool
face 'A'.
Adjust both rear eccentrics as required to achieve this goal. Tighten the two clamp
screws on each side of the printer and recheck the clearance to ensure nothing has
moved out of adjustment. Tighten the eccentric lockbolts B on each side of the
printer.
Slide the carriage from end to end, stopping at several points to rotate the platen
while checking the tool-to-platen clearances. Check for an average of .010 inch
(.254 mm) ± .001 inch (.025 mm) clearance between the platen surface and the tool
face 'B'. Adjust both front eccentrics as required to achieve this goal. Hold each
adjusted eccentric with a 7/16" wrench while tightening its lockbolt. Recheck the
clearances to ensure nothing has moved out of adjustment.
6.
7.
8.
Remove the tool and reinstall the print head (see 3.3.6).
, . . - - - - MANIFOLD
LEVER
FORWARD
TO 2ND
DETENT
( .Z54_:.t.OZ5",.)
-~""'-.OIO·1:.00I-
_ - - CLAMP SCREWS
(TORX #15)
TOOL
' - - - - REAR ECCENTRIC
(BOTH SID£S)
( 7/16- WRENCH)
IDLER GEAR
MAY BE
REMOVED
' - - - - FRONT ECCENTRIC
(BOTH SIDES)
( 7/16· WRENCH )
Figure 3-26. Platen-To-Print Head Adjustment Points
3-41
3.4.2.6
Variable Adjust Platen Knob's End Play Adjustment
The variable adjust (right hand) platen knob's end play must not exceed .002 inch
(.051mm) maximum.
Refer to Figure 3-27 for the variable adjust platen knob's end play adjustment.
1.
Loosen the set screws in the platen release gear hub
achieve the desired clearance.
2.
Retighten the set screws in the platen release gear hub •
@
and adjust the hub to
.002"
MAXIMUM
(.O!ilmm)
Figure 3-27. Variable Adjust Platen Knob's End Play Adjustment
3-42
3.937
( 10 CM)
1-4--
]
.130 (.33CM)
DEFLECTION
AT 16.5 j; 2.2LB
LOAD (7.4 kO ± 1.0kg)
1.968
(5CM)
Figure 3-28. Carriage Drive Cable Adjustment
3.4.2.7
Carriage Drive Cable Adjustment
Refer to Figure 3-28 for Carriage Drive Cable adjustments.
With the carriage positioned against the right-hand stop, check the cable tension midway
along the exposed cable for a force of 16.5 lbs ± 2.2 Ibs (7.4 kg ± 1.0 kg) necessary to
distort the cable as shown.
NOTE
If the Tensionmeter listed under tools at the front of this
section is not used, the dimensions between force points shown
must be carefully followed.
1.
Adjust cable tension by tightening or loosening cable tension nut B while holding
the square cable shank A from turning.
2.
After adjusting the nut B ,move the carriage back and forth several times to
redistribute cable tension, and recheck. Use Loctite on nut B after adjustment
has been completed.
083-010
Figure 3-29. Ribbon Drive Cable Adjustment
3.4.2.8
Ribbon Drive Cable Adjustment
Refer to Figure 3-29 for Ribbon Drive Cable adjustment.
The Ribbon Drive Cable tension must be adjusted to provide adequate drive while not
unduly impeding carriage motion or straining the cable. To adjust the cable, start with a
properly lubricated carriage, then install a ribbon cartridge and proceed as follows:
1.
Move the carriage back and forth slowly at least 6 inches (15.24 cm) each way from
machine centerline while tightening the cable locknut A on the right end of cable
B
2.
Tighten slowly until the ribbon drive is observed to rotate without slipping during a
full carriage motion. Then add 1/2 to 3/4 turn (180° to 270°) to locknut A.
3-43
Figure 3-30. Ribbon Drive Gear Adjustment
3.4.2.9
Ribbon Drive Gear Adjustment
Refer to Figure 3-30 for Ribbon Drive Gear adjustments.
The Ribbon Drive system~cludes two opposing spring clutch gears (
driving a ribbon capstain ®, and being driven from a cable pulley gear
backlasfiis adjusted as follows:
1.
2.
@
Y.
e )
and
The s~em
Hold clutch gear
stationary.
Rotate the eccentric mounting screw (j;) of cable pulley gear @ clockwise
ONLY to achieve a .003 i~ (.08 mm) Y.002 inch (.05 mm) backlash between
pulley @and clutch gear
0
Move the carriage from ~ to side and check for a full 360 of clockwise
rotation of ribbon capstan
without evidence of binding or slippage.
8 .
3.
t(1)
®
3-44
3.4.2.10
Paper Clamp Adjustment
Refer to Figure 3-31 for Paper Clamp adjustments.
The Paper Clamp extends the full length of the pIa ten, and is held in place by the two rear
carriage rail clamp's rear hold-down screws. The Paper Clamp assembly will seldom
require adjustment, except when the rear carriage rail has been removed and replaced. To
adjust, proceed as follows:
1.
Loosen the two rear mountin~crews
each end of the carriage rail
2.
Push the paper clamp assem*
go and retighten the screws
®.
® from the rear carriage rail clamps at
© back toward the platen @ as far as it will
0J .
Figure 3-31. Paper Clamp Adjustment
3-45
"..-I
I
\
/
,/
~
........
"\
\
\
083-050
083-051
b.
a.
Figure 3-32. Bottom Feed Paper Chute Adjustment
3-46
Bottom Feed Paper Chute Adjustment
3.4.2.11
Refer to Figure 3-32 for Bottom Feed Paper Chute adjustments.
The Bottom Feed Paper Chute is an optional feature, not found on all HyTerms. Its use
requires that a forms tractor be used along with the standard friction-feed platen. To
properly adjust the paper chute, proceed as follows:
1.
Make sure the following adjustments are correct before adjusting the bottom feed
paper chute:
(a) Platen-To-Print Head (see 3.4.2.5).
(b)
2.
Paper-Feed Assembly (see 3.4.2.2).
Remove the Paper Clamp @, and replace its rail clamp mounting screws (Vfinger
tight. Loosen all other screws except those holding the paper chute's bottom flanges
@.
3.
Move the paper release and platen adjust levers fully forward.
4.
Adjust the paper chute
down as low as possible, tighten the four forward facing
screws @. See Figure 3-32a.
5.
6.
Remove screws
Install paper clamp @, adjust paper clamp and paper chute back toward the platen
See Figure 3-32a.
as far as possible. Tighten screws
7.
Adjust the dimples of the paper out bail @ to touch the front paper chute cruat both
ends. Tighten set screws located in hubs at each end of paper out bail
See
Figure 3-32b.
8.
Adju~micro switch
to just res~ .025 - .040 inch ~ore dimples of paper out
bail @ touch front paper chute ®. Tighten screws \.!). See Figure 3-32b. Bail
minimum movement should be .100 inch at tangent of dimples. If not, form switch
arm and readjust the switch per step 7. Note: Bail must move freely.
®
0.
0.
®.
®
3-47
3.4.3
Control Panel Alarm Volume Adjustment
Refer to Figure 3-33 for the Control Panel Volume Adjustment.
There is a potentiometer on the control panel that can be adjusted to change the Alarm
buzzer volume. To adjust, proceed as follows:
1.
Remove access cover to expose the switch portion tof the control panel.
2.
Using a small blade screwdriver, adjust the Alarm buzzer volume control potentiometer until the desired volume is obtained. To test the alarm after each
adjustment, depress the RESET keyswitch on the keyboard and then attempt to
print a character (Cover-Open error will occur).
-
EVEN ONONON
-
-
I[~~I~II
ODD
ON ETX ON ON
11!!!1Ir11l11 0
I IAUTO CR LINE
PARITY
REV CHAN
-
EOT CR
ETX
TEST.
liE
OT
-
@
~
o~
FI
5 AMP
00
115V
SB
o
083-011
Figure 3-33. Control Panel Alarm Volume Adjustment
3.4.4
Power Supply Adjustment
Adjustment of the power supply should not normally be required unless power supply
components have been replaced. Proper adjustment of the power supply requires use of a
variable load, so these adjustments should not be attempted in the field. It is
recommended that power supply adjustment problems be referred to the nearest Diablo
service depot. The following information is provided for Diablo service depot personnel.
NOTE
For locations of the various potentiometers mentioned in the
following procedures, refer to the assembly drawing following
schematic no. 400062-XX in the schematics/reference section.
All output readings should be taken with a digital voltmeter.
3-48
3.4.4.1
Overvoltage Protection
Disconnect the power supply outputs from the terminal and connect a dummy load to the
+5V output which draws approximately 1 amp. While monitoring the +5V output, adjust
pot R22 clockwise and note the maximum voltage obtainable (after which the overvol tage
circuit takes over and causes the output to drop). This should be between +5.5V and +6.3V,
preferable around +6.0V. Adjust pot R23 on the control module (the small circuit board
attached to the power supply's main circuit board) clockwise to trigger the overvoltage
circuit at a highter point, or counterclockwise for a lower point.
NOTE
If the put put reaches +6.3V before triggering the OVP circuit,
the SCR "crowbar" circuit may trigger, requiring removal of
input power before the power supply can restart. If this
occurs, turn off power, turn pots R23.on the control module
and R22 both counterclockwise slightly, restore power, and
continue the test as described.
3.4.4.2
Current Limit
This adjustment should be made with the input voltage at a nominal valu~-not at either of
its extremes. This is, the input voltage should be as close to 115V (or 230V) as possible.
This adjustment also requires that the outputs be loaded so that the power supply delivers
about 320 watts of total power.
CAUTION
Maintain this power level for no longer than 30 seconds while
making this adjustment.
Adjust pot R19 until the output begins to drop off at the 320 watts total power point.
3.4.4.3
Output Voltage
With the power supply connected to the terminal, adjust pot R22 to obtain +5.0V +1 V, at
Mother Board connector T15 (refer to Figure 3-19). Check the +15V, -15V and +48V
readings at Mother Board connectors T15, TIl, and T18, respectively. If these readings
are not within,::, 5%, some problem exists and must be corrected before proper adjustment
can be made.
NOTE
The power supply must be connected to the terminal for this
adjustment. Accurate adjustment cannot be make without a
proper connected to the +5 output.
3-49
3.4.5
Cover-Open Switch Adjustment
Before attempting an adjustment, be sure that the top cover fits the bottom cover
properly, and that the access cover fits the top cover properly, and is tight. Adjust and/or
from the access cover clamp springs (replace if necessary) to tighten the access cover. If
switch adjustment is still necessary, proceed as follows:
For a minor adjustment, form the small protrusion on the bracket inside the bottom center
of the access cover. If further adjustment is necessary, it may be necessary to shift the
entire bracket up or down slightly. Check the adjustment by making sure the switch
operates each time the access cover is opened or closed.
Paper-Out Switch Adjustment
3.4.6
This switch is functional only when a forms tractor or pin-feed platen is used. When a
friction-feed platen is used (without forms tractor), the switch is held in its nonoperated
(paper in) position by the paper release lever's being in its rearward position. When the
paper release lever is moved to its forward position, the switch operating mechanism is
unlocked and allowed to sense the paper-~out condition.
Before starting this adjustment, make sure that the Platen-T-Y
VCC-14, GND-7
Loading:
Inputs
Outputs
7404
1 UnIt Loads
10 Unit Loads
74LS04
.2 UnIt Loads
5 Unit Loads
4-7
7405
1 UnIt Load
10 Unit Loads
TTL Quad 2-1 nput AND Gate
TTL Quad 2-lnput AND Gate, Low Power Schottky
Part No.1 0119
Part No. 10210
Logic
Symbol
~
~
![y-
Type 7408
Type 74LS08
Truth Table
A
B
Y
L
L
L
H
L
L
L
H
L
:D--v
A~11 Y
H
H
H
e 13
VCC14, GND-7
Loading:
Inputs
Outputs
1 Unit Load (.2 for 74LS08)
10 Unit Loads (5 for 74lSOS)
TTL Hex Inverter Buffer/Driver
Type 7416
Part No. 10390
These driv~!s have high-voltage (up to 15V) open-collector outputs for interfacing with high-level circuits or for
driving high current loads.
Logic Symbol
Alternate Symbol
A
Loading:
Inputs
Outputs
1 Unit Load
25 Unit Loads
4-8
-{>--v
TTL Dual 4-lnput NAND Gate
Part No.1 0 125
Type 7420
Log ic Sy mbol
Truth Table
A
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
A
8
C
D
VCC-14, GND·7. Pins 3& 11 not used.
Alternate Symbol
A
B
y
C
o
Loading:
Inputs
Outputs
B C D Y
L L L H
L L H H
L
L
H
H
H
H
L
L
L
L
H
H
H
H
H
H
L
L
L
H
L
H
H L
H H
L L
L H
H L
H H
L L
L H
H L
H H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
1 Unit Load
10 Unit Loads
TTL Quad 2-lnput NAND High-Voltage Interface Gate
Part No.1 0120
Type 7426
These gates have high-voltage (up to 15V) opencollector outputs for interfacing with high-level
circu its.
Logic Symbol
AI ternate Symbol
:=D-v
A~12
II y
B 13
VCC·14, GND-7
Loading:
Inputs
Outputs
1 Unit Load
10 Unit Loads
4-9
Truth Table
A
L
H
L
H
B
y
L
L
H
H
H
H
H
L
TTL Quad 2-Input OR Gate
TTL Quad 2-lnput OR Gate, Low Power Schottky
Type 7432
Type 74LS32
Part No. 10302
Part No. 13082
Logi c Sy mbo I
Alternate Symbol
9
I~
::[J-y
Truth Table
A
L
L
H
H
B
L
H
L
H
y
L
H
H
H
VCC-14, GND-7
Loading:
Inputs
Outputs
1 Unit Load (.25 for 74 LS32)
10 Unit Loads (5 for 74LS32)
Part No. 42408-01
TTL 4-Wide AND-OR-INVERT Gate
Logic Sy mbol
A
Y
B
C
o
VCC-14, GND-7
Loading:
Inputs
.25 U nit Load
Outputs
5 Unit Loads
4-10
= AB+CDE+FGH+IJ
Type 74LS54
Type 7474
Type 74LS74
Part No. 10139
Part No. 13085
TTL Dual 0 Flip-flop
TTL Dual 0 Flip-Flop, Low Power Schottky
The 7474 contains two Ootype edge-triggered
flip-flops with direct preset and clear inputs. A low
level on the preset or clear input will set or reset the
flip-flop, respectively, regardless of other input condi-
tions. When both the preset and clear are high, the
logic level on D is transferred to a on the positivegoing edge of the clock.
Logic Symbol
Timing Waveforms
4
2
P
Q
D
5
ClK
ClK
Q~
6
C Q
0
1
10
P Q 9
Truth Table
ClK
C 0
8
13
VCC-14, GNO-7
Preset input
Data input
Clock input
Clear input
Data outputs
P
o
CLK
C
o,a
Function
Preset
Clear
Clear
Set
Reset
Set Up
Inputs
0
Outputs
P
C
0,0
Inputs
Clear
H
L
L
H
H
H
Outputs
Unit Loads
7474
74LS74
.5
2
.25
1
1
.5
.75
2
5
10
4-11
a
Clock
0
Q
X
X
X
X
X
H
L
H
L
H*
H
H
L
H
L
No Change
••
L
X
H
L
X
*This configuration is nonstable; that is, it will not
persist when preset and clear inputs return to their
inactive (high level).
Loading:
CLK
Preset
L
H
L
H
H
H
TTL Dual J--K Flip-Flop with
Preset and Clear
Part No. 10138
Type 7476
Logic Symbol
Truth Table
INPUTS
7
2
p
4
Q
9
15
ClK
16
J
Q
12
c
CLR
H
L
L
H
H
H
H
Q
K
H
10
H
H
H
CLK
J
K
Q Q
X
X
X
X
X
X
X
X
X
H
L
H
H
H
L
H
L
H
L
L
L
QO QO
H L
L H
TOGGLE
H
H
C
3
8
VCC -
5
GND
8
-
11
PR
L
H
L
ClK
Q 14
K
p
OUTPUTS
(083 - 038)
Type 7486
Part No. 10303
TTL Quad 2-lnput Exclusive OR Gate
Logic Symbol
1
1A~1Y
1B~
~B 3Y
3A 10
38
Truth Table
2A~2Y
28~
1~11. 4Y
4A 13
,48
VCC-14, GND-7
Loading:
Inputs
Outputs
1 Unit Load
10 Unit Loads
4-12
INPUTS
A
L
L
H
H
B
L
H
L
H
OUTPUT
Y
L
H
H
L
TTL Dual Retriggerable One-Shot
TTL Dual Retriggerable One-Shot
Part No. 10145
Part No. 42313-01
Either of the one-shots in this package
can be triggered by a positive-going or
a negative-going input, providing the
other input is already in the proper state.
At least one of the inputs must be removed and re-applied in order to retrig-ger-l1l"e--ae-vlce-~------A-Tow-orrlfie-C-fnpllL--terminates the output pulse immediately.
The length of the output pulse is dependent upon external timing components.
Type 74123
Type 74LS123
Alternate Symbols
Q
A
Logic Symbol
B
Q
Q
Q
c
C
(C) (RIC)
14
15
A
2
Q 13
B
-4
C Q
3
Truth Table
(c) (RIC)
7
9
A
10
Q
CLEAR
5
L
X
X
B
C Q
H
H
12
X
H
X
L
L
11
Loading:
INPUTS
A
74123
Clear
2 Unit Loads
Other Inputs 1 Unit Load
Outputs
10 Unit Loads
4-13
B
X
X
L
H
H
74LS123
.25 Unit Load
.25 Unit Load
5 Unit Loads
OUTPUTS
Q
Q
L
L
L
H
H
H
BCD/Decimal Decoder/Driver,
Low Power Schottky
Type 74LS145
Part No. 10172-29
This BCD-to-decimal decoder/driver
consists of eight inverters and ten 4input NAND gates. The inverters are
connected in pairs to make BCD input
data available for decoding by the NAND
gates. Full decoding of BCD input logic
ensures that all outputs remain off for
all invalid (10-15) binary input conditions.
Logic
15
14
13
12
A
B
e
0
S~mbol
0
1
2
3
4
5
6
7
8
9
11
vee -16
GND - 8
(083-035)
4-14
TTL Dual 2:4 Decoder
TTL Dual 2: 4 Decoder, Low Power Schottky
Part No. 10194
Part No. 13090
Type 74155
Type 74LS155
Truth Table
Logic Symbol
Outputs
Inputs
1C
A
1Y3
1Y2
lY1
1YO
B
2Y3
1G
13
3
2C
2G
2Y2
2Y1
2YO
VCC-16, GND-8
Select
A
B
X
L
L
H
H
X
X
L
L
H
H
X
X
L
H
L
H
X
X
L
H
L
H
X
Loading:
Inputs
Outputs
1 Unit Load (.25 for 74LS155)
10 Unit Loads (5 for 74LS155)
4-15
Gate
1G
Data
1C
1YO
1Y1
1Y2
1Y3
H
L
L
L
L
X
X
H
H
H
H
L
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
2G
2C
2YO
2Y1
2Y2
2Y3
H
L
L
L
L
X
X
L
L
L
L
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H.
L
H
H
H
H
H
H
L
H
TTL 4-Bit Synchronous Binary Counter
TTL 4-Bit Synchronous Binary Counter, Low Power Schottky
All
fl i p-flops
s i mu Itaneously, so
in this chip are clocked
all output changes occur
Type 74161
Type 74lS161
Part No. 10335
Part No. 13091
simultaneously. A low on the Clear input overrides
other inputs, and drives all outputs low.
Timing Waveforms
Logic Symbol
CLEAR~
----tu
LOAD
{:==: ===
r-
DATA
INPUTS
4
-l
:-
-l
:=
8
I
CLOCK-~
ENABLE
c
:,~I------~~__~r---
P -----::-'.
ENAB{LE :
===:
8
VCC-16, GND-8
-H
CARRY _ _
Loading'
Unit Loads
Inputs
LOAD
CLK, EN-T
Other
Outputs
1
.5
.5
.25
2
1
10
-
L _ __ _ _ _ _ _ _ _ _
~---:--:___-....JnL-----------
I
CLEAR -l.
1.
2.
3.
4.
r - : - - I
-
===U,-'---:-----:----:..._________
4 __
74lS161
!
2---::
~:
_
_
_ ;L--~:-=--=--=-~__---,
au TP U T S
74161
- .
:12
:13
14
I J-.-L PRESET
15
c:
0
COUNT
•
I-
5
INPUTS
H
L
X
f
t
t
t
t
EN-P
EN-T
X
X·
X
X·
X
X
X
X
l
H
l
H
L
l
H
H
-
Clear outputs to zero
Preset to binary twelve
Count to thirteen. fourteen, fifteen. zero. one, and two.
Inhibit
Truth Table
ClK
INHIBIT
LOAD
C
A.B,C,o
OUTPUTS
X
X·
X
X
X
l
X
X
X
L
H
DATA
H
H
H
H
H
H
H
H
X
X
X
X
No Change
No Change
All lOW
Preset to
A,S,C,D.
input data
No 'Change
No Change
No Change
Count Up
• Avoid changes to inputs while ClK is low.
4-16
Type 74175
Part No. 10337
TTL Quad D Flip-Flop
with Clear
This positive-edge-triggered flip-flop
utilizes TTL circuitry to implement
D-type flip-flop logic, with a direct
clear input and complementary outputs from each flip-flop.
Data at the D inputs meeting the
set-up time requirements is transferred to the Q outputs on the positive going edge of the clock pulse.
Clock triggering occurs at a particular voltage level and is not directly
related to the transition time of
the positive-going pulse. When the
clock unput is at either the high or
low level, the D input signal has no
effect at the output.
Logic Symbol
Alternate Symbol
r------,
4
-
10 10
>CLK
C 10
~
5
202Q
4~
-~CLK
C2Q
4~
2
3D 30
u- ~>CLK
C 30
4~
13
9
1
L.
4
2
1Q
10
3
1Q
7
5
2Q
20
6
2Q
10
12
3D
3Q
11
3Q
13
9
15
4040
CLK
14
C4Q
v
_ _ _ _ -I
4Q
40
eLK
e
2
3
7
6
10
11
15
4Q 14
11
vee - 16
GNO -
(083-034)
8
4-17
Synchronous Up/Down Counter
with Dual Clock
Type 74193
Part No. 10154
Logic Symbol
This device is a synchronous
up/down 4-bit binary counter.
Synchronous operation is provided by having all flip-flops
clocked simultaneously, so
that the outputs change together when so instructed by
steering logic.
11
()
LOAD
QA
Q8
QC
9
QD
0
5
CU
CAR ....,
4
CD
8RW ....,
15
A
1
8
10
C
The outputs of the four master-sla ve flip-flops are triggered by a low-to-high transition of either count (clock)
input. The direction of counting is determined by which
count input is pulsed, while
the other count is held high.
3
2
6
7
r"\
12
r"\
13
C
All four counters are fully
program mabIe; ie, each output may be preset to either
level by entering the desired
data at the inputs while the
load input is low. The output
will change independently of
the count pulses.
14
VCC - 16
GND -
8
(083-032)
A clear input, when taken to
a high level, forces all outputs
to the low level, independent
of the count and load inputs.
The clear, count, and load inputs are buffered to lower the
drive requirements of clock
drivers, etc., required for long
words.
4-18
TTL 4-Bit Parallel-Access Shift Register
Part No. 10191
Type 74195
Data can be loaded into this register either serially
or in parallel. When Parallel Enable (PE) is low,
parallel data is loaded into the flip-flops on every
positive-going clock. When PE is high, data is shifted
from the J and K inputs to flip-flop 0, and from 0 to
1, 1 to 2, and 2 to 3, at each positive-going clock
transition. A Iowan the Clear (C) input overrides all
other controls.
Logic Symbol
9
PE
2
4
~
6
7
10
J
K
piJ
QiJ
PI
QI
P2
02
P3
03
elK
I~
14
13
03
C
VCC-16, GND-8
Truth Table
C
PE
Inputs
CLK
J
L
H
H
H
H
H
H
X
X
L
H
H
H
H
H
H
L
X
OOn
•
•••
•
L
K
Po-P3
X
X
X
X
X
X
abcd
L
L
H
H
L
H
L
H
X
X
X
X
X
X
00
01
L
a
OOn
L
OOn
OOn
H
L
b
01n
OOn
OOn
OOn
OOn
-
High
Low
Irrelevant
State of 00 before positive transition of CLK
Loading:
Inputs
Outputs
1 Unit Load
10 Unit Loads
4-19
Outputs
02
L
c
02n
01n
01n
01n
01n
03
03
L
d
03n
02n
02n
02n
02n
H
d
03n
02n
02n
02n
02n
-
Clear
Parallel Load
No Change
} Shift
TTL 8-bit Addressable Latch
TTL 8-bit Addressable Latch, Low Power Schottky
Part No. 10339
Part No. 13094
This is a multifunctional device capable of storing
single line data in eight addressable latches, and being
a one-of-eight decoder and demultiplexer with
high-active outputs. It incorporates a low-active
common clear for resetting all latches, as we" as a
low-active enable.
remain in their previous state and are unaffected by
the data or address inputs. When operating as an
addressable latch, changing more than one bit of the
address could impose a transient wrong address.
Therefore, this should only be done while E is HIGH.
_ Type 74259
Type 74LS259
In the one-of-eight decoding or demultiplexing
mode, the addressed output wi" follow the state of
the 0 input, with all other outputs in the LOW state.
There are two modes of operation, shown in the
Function Table. In the addressable latch mode, when
E is LOW, data on the data line (D) is written into the
addressed latch. The addressed latch will follow the
data input, with all nonaddressed latches remaining in
their previous states. When E is HIGH all latches
When E is HIGH and C is LOW a" outputs are
LOW and unaffected by the address and data inputs.
Logic Diagram
Logic Symbol
ONLY ONE LATCH SHOWN FOR CLARITY
A2
- - - - t ;'::>-411....a
>-----....---+--
......
~---_r_
A1
A2
A f/) - - - - 4 :oc:>-tI....-a '>----11-+--+-......
D ----'[--....
E
~----TlT-~~~
A1
A0
o
E
c
C
\
TO OTHER LATCHES
VCC-16, G ND-8
Function Table
Inputs
Outputs
C
E
0
L
L
L
H
H
H
L
L
H
L
L
H
L
H
X
L
H
X
Loading:
Unit Loads
742,59 74LSZ59.
Inputs
I
I
Outputs
E
Other
1.5
1
6
.25
.25
5
4-20
Addressed
Latch
Others
L
H
L
L
H
No Change
L
L
L
No Change
No Change
No Change
Mode
} Demultiplexer
Clear
} Addressable
Latch
Part No.1 0197
Part No. 13096
TTL Hex Bus Driver, Three-State
TTL Hex Bus Driver, Three-State, Low Power Schottky
Logic Symbol
-I
12
I 3
1
4
5
6
7
9
12
I
11
I
I
14
I
13
I
t5 I
1_ _ VCC-16, GND-8
Loading:
Unit Loads
74367
74LS367
Inputs (Gate enabled)
Outputs
1
.25
20
10
4-21
Type 74367
Type 74LS367
MOS 8-bit Microprocessing Unit
Part No. 42338
This is a single chip 8-bit parallel microprocessor
wh i ch forms a microcomputer system when
interfaced with any type or speed of standard
semiconductor memory up to 64K 8-bit words and an
I/O device. The MPU inputs and outputs data over an
8-bit bi-directional three-state data bus (D(}DJ). It
addresses memory and I/O devices over a 16-bit
three-state memory address bus (A(}A 15). It is driven
by two 12-volt non-overlapping clocks, ~1 and ~2.
There are four input signals, INT (Interrupt), ROY
(Ready), HOLD, and RST (Reset). Output signals
include INTE (Interrupt Enable), OBI N (Data Bus
In), WR (Write), SYNC, WAIT, and HLDA (Hold
Ackn owl edge) .
The 8OS0A uses its internal stack pointer to access
external memory, allowing it to handle mUltiple-level
priority interrupts. This also allows adequate
subroutine nesting ..
Type 80S0A
Logic Symbol
+5V
vec
O~
01
The 8080A contains a register array made up of
six 1&bit registers: a Program Counter, a Stack
Pointer, and four register "pairs," each made up of
two 8-bit registers. One of these is the Temporary
Register, called W/l, which is used for the internal
execution of instructions. The other three are
working registers, called B/C, O/F, and H/L. The six
general purpose registers can be used as either single
8-bit registers or 16-bit register pairs; W/Z is not
program addressable.
02
03
04
05
06
07
+12V
28
VOO
A~
A1
A2
A3
A4
A5
AS
A7
A8
A9
22
The 8080A also contains an Arithmetic and Logic
Unit (ALU), containing an 8-bit accumulator (ACC),
an 8-bit temporary accumulator (ACT), an 8-bit
temporary register (TMP), and a 5-bit flag register. All
arithmetic and logic instructions are performed in th is
section.
15
The third major part of the 8080A contains the
Instruction Register, Instruction Decoder, and all
ti ming and control logic. The last major portion is the
Data Bus Buffer, a 3-state bi-directional 8-bit latch
that serves to isolate the the MPU's internal data bus
from the external bus.
11
12
RST
SYNC
HOLD
GND
The instruction set consists of over 100 different
instructions, which provide conditional and
u ncon d i tional branching, decimal and binary
arithmetic, and logical, register-to-register, stack
control, memory reference, and I/O instructions. Up
to 256 input ports and 256 output ports can be
addressed. Instructions may be either one, two, or
three 8-bit bytes in length. Memory can be referenced
four ways: direct, register, register indirect, and
immediate. Non memory-reference instructions can
be executed in 2 microseconds when a 2 MHz clock is
used. The sequential program execution can be
interrupted by driving the INT input high.
HLDA 24
WAIT
vee
11
-5V
Loading:
Outputs
4-22
1.2 Unit Loads
Mnemonic
Of\CfiptiGn
Iry
MOV rl, r2
MOV M,I
MOVr,M
MOlle rt9,s!!r 10 register
fIIo.,e /tgister 10 memory
Mo~ memory to register
HilI
Move immedllte register
Move immediate memory
Increment register
Decrement register
Increment memory
Decrement memory
Add regiuer to A
Add register to A with tlrry
Subtract regiuer f,am A
Subtrlct regl!'!1 from A
with borrow
And register With A
Exclu'i~ Or legister with A
Or register with A
Compile regitt" with A
Add memory to A
Add memory to A WIth carry
Subtract memory from A
Subtract memory from A
with borrow
~nd memory with A
Elclusi~ Or memory with A
0, memory with A
Compile memory with A
Add immediate !o A
Add immed,a" to A with
tlrfy
Subtract i,.,..med,lte f,am A
Subtract immediate from A
wim borrow
And immedilte with A
Excl""lIe Or immed,ate with
A
Or imm~dilte with A
Compare immedl.te with A
Rotl" A left
ROllte A right
Rotate A left through tlrry
Rotlte A light through
tlrry
JUl'lP uncondltlonll
Jump on tiny
Jump on no ~rry
Jump on lero
Jump on no rero
Jump on positive
Jump on minus
Jump on pa"ty e\lfn
Jump on PI"ty odd
C.II unconditional
C.II on Cllly
C.II on no tarry
Cetl on lflO
Call on no lero
C.II on poslt've
Cp.II on monus
e.1! on """ty e~n
C,II on PI"ty odd
Return
hftUfn on tftrry
Return on 00 carry
o
o
o
o
o
o
o
o
o
o
HlT
MVI I
MVIM
lNR I
OCR I
INR M
OCR M
ADO r
ADC r
SUB r
S8B r
ANAr
XRA r
ORAr
eMPr
ADD M
AOC M
SU8 M
S88 M
ANA M
XRA M
ORA M
CMPM
ADI
ACI
SUI
S81
ANI
XRI
ORI
CPI
RlC
RRC
RAl
RAR
JMP
JC
JNC
JZ
JNZ
JP
JM
JPE
JPO
CAll
!;.C
CNC
CZ
CNZ
CP
CM
CPE
CPO
RET
RC
RNC
o
1
o
1
0
0
0
0
0
0
o
o
o
o
1
D
1
D
D
1
1
0
o
0
1
1
0
0
o o
o o
o
o
o
o
o
s
DOS
IDS
D 0
1 0
D D
1
0
D 0
o
o
1
1
1
RZ
RNZ
RP
RM
RPE
RPO
RST
IN
OUT
lXI 8
o
o
o
1
0
10
0
5
5
1
1
o
o
o
o
S
S
S
1
S
S
S
S
S
S
S
S
S
lXI H
S
S
S
S
lXI SP
PUSH B
S
S
S
S
S
S
10
10
4
lXI
S
o o
o
o
o
o
PUSH H
o
o
POP B
PUSH PSW
POP D
1
o
o
o
o
1
0
0
0
0
1
0
0
0
0
POP PSW
o
o
o
o
o
l'
1
1
o
o
o
o
o
1
1
o
o
o
0
1
0
0
1
1
STA
LOA
XCHG
XTHl
SPHl
PCHl
DAD 8
o
o
1
0
0
DAD 0
DAD H
DAD SP
0
0
0
0
1
0
0
0
0
0
0
o
0
0
0
0
1
1
1
0
0
0
1
0
o
o
o
o
o
o
o
0
0
1
0
0
1
0
0
10
10
0
17
11/17
11/17
11/17
11/17
11117
0
0
o
1
0
STAX B
STAX D
lOA X 1:1
LOAX D
INX B
INX D
INX H
INX SP
OCX 8
OCX 0
DCX H
DCXSP
CMA
STC
CMC
10
10
10
10
10
10
10
o
o
o
o
o
o
1
o
o
o
o
o
0
0
DAA
11/17
11/17
0
SHlD
lHlO
EI
01
11117
10
5/11
5111
0
1
0
0
HOP
Register
I ODD or SSS
A
111
I
I
B
000
I
I
C
001
I
I
D
010
I
I
E
011
I
1
H
100
I
I
L
101
I
I
Mem
110
2) Two possible cycle times (11/17 or 5/11) indicate instruction cycles dependent on
condition flags.
3) After a Restart instruction, the next instruction is fetched from memory at the
address eight times AAA.
4-23
D:J
~
0
o
C 0
1
0
0
1
1
0
n
A
1
A
1
1
0
1
1
o 1
o o o
0
0
0
0
o
o
o
0
o
10
0
0
o
10
o
0
o
o
o
11
o
o
11
o
o
11
o
o
11
o
o
0
o
1
o
\
o
o
1
1
0
0
1
1
o
o
o
o
o
o
0
0
0
0
0
0
o 0
o 0
o 0
o 0
o
o
o
o
o
o
o
o
o
o
o
0
0
0
0
0
o
0
o
10
0
o
10
o
0
o
10
0
0
0
o
o
o
0
1
0
0
0
0
0
0
1
1 0
o 0 0
1 0 I!
010
1
1
0
o
o
o
o
o
0
1
1
0
0
1
1
0
0
0
C
o
010
1 1 0
o
o
o
o
o
o
o
o
o
0
o
0
001
0
o
o
0
0
0
o
o
1
1
1
0
0
0
0
0
1
1
0
0
1
0
1
o
10
7
7
7
5
7
5
5
5
0
1
1
13
13
4
18
5
5
10
10
10
1
o
o
o
o
o
o
0
0
0
0
1
1
10
10
o
o o
o 1
1
o
1
1
o
o
1
1
0
0
0
0
0
o
1
1
o
o
o
0
0
o
o
Cycle,
000
A
o
o
Do
0
010
o
,
Cloeld2!
D,
5/11
5/11
5/11
5/11
5111
5/11
11
10
10
10
0"
E 0"
Pop regluer plir H & L off
,tick
Pop A and FIlgs
off st.ck
Store A dKect
lold A direct
Excha,. 0 & E, H & l
Registers
hchlngt top of st.ck, H & l
H & l to st.ck pointer
H & l 10 progrlm counter
Add B & C te H & l
Add 0 & E to H & l
Add H & l to H & l
Add stick pointer to H & l
StOle A induect
Store A indirect
lold A indirect
lOld A indrrect
Increment 8 & C registers
Increment 0 & E registers
Increment H & l IIlJlsters
Increment stick pointer
Oecrrment 8 & C
Decr~ment 0 & E
Decrement H & l
Oecrement Slick oointer
Complement A
Set carry
Complement Clrry
DeCimal Idlust A
Store H & l direct
Loed H & l duect
En.blt Interrupts
DISIIble interrupt
No-operation
Notes:
)
04
o o ,
o o 0
Push A Ind Flags
on stick
Pop register pau B & C
Pop register pair 0 &
POP H
0
1
1
Return on lero
Return on no zero
Return on positive
Return on minus'
Return on parity even
Return on plrity odd
Reslln(3)
Input
Output
lo.d immediate register
Plir B & C
lold immedilte rt!!ist"
Pair 0 & E
Load i",mediue register
Pair H & l
lOid immediate stick pointer
Push register P,ir 8 & C on
st.ck
Push register PIli 0 & E on
stack
Push register P,ir H & l on
Il& Os
stICk
o
o
o
o
Iry
stICk
o
o
0
Dneription
SIKk
o
o
1
0
D
PUSH D
o
0
o
o
Mnemonic
Cycles
S
S
S
0
1
1
Instruction Code (t )
Clock(2)
Imtluctlon Code (I)
04 03 ~ 0 1 Do
Os Os
o
o
o
o '1
o o
o o
o o
o
1
Type 8080A (Continued)
Part No. 42338
MOS 8-bit Microprocessing Unit
1
1
1
1
o
5
5
5
5
4
4
4
4
16
16
4
4
4
M2
OPCODE
MNEMON~C
T1
T212l
T3
T5
T4
MOVr1.r2
o
1
0
0
o
S
S
S
MOVr.M
o
1
0
0
o
1
1
0
MOVM.r
o
1
1
1
o
S
S S
(SSS)-TMP
(HL) ________~~~~Pr
PCOUT
STATUS
PC
PC +1
INST~TMP/IR
(TMP)-OOD
(SSS)~TMP
T212l
Tl
X[3J
.......•....
....
'
'.',
HLOUT
STATUS[6]
.'.
-:.
DATA-.ODO
HL OUT
STATUS[7J
(TMP)-~DATA
SPHL
1
1
1
1
1 0
0
1
MVI r. data
o
0
0
0
o
1
1
0
X
MVI M. data
o
0
1
1
o
1
1
0
X
LXI rp. data
o
0
R P
o
0
0
1
X
PC
LOA addr
o
0
1
1
1
0
1 0
X
PC-PC+l
STA addr
o
0
1
1
o
0
1 0
X
PC=PC+l
LHLD addr
o
0
1 0
1
0
1
0
X
PC
SHLD addr
o
0
1
0
o
0
1 0
x
LOAX rp[4J
o
0
A P
1
0
1 0
x
STAX rpl4]
o
0
A P
o
0
1 0
x
XCHG
1
1
1
0
1
0
1
ADOr
1
000
o
S S S
(SSS)-TMP
(A)-ACT
ADDM
1
0
o
1
(A)-ACT
(HU
1
BUS
...;:;:;::
:::::'.'
'.... '.'<::.'.
T3
B2 -f.DDDD
PC OUT
STATUS[6J
B2--.· MP
.... .... ::::
~
,
PC+l
PC + 1
PC OUT
STATUS[6]
DATA-.A
rp OUT
STATUS[6]
'::~{}:f::
(AI --.DA·
rpOUT
STATUS17]
BUS
::::::: •.......
::::::::.
mE)
'.~
0
0
1
0
(ACT)+(TMP)-A
;.:
.',
ADI data
1
1
0
0
o
1
1
0
ADCr
1
0
0
0
1
S S
S
HLOUT
STATUS[6]
(A)-ACT
PC OUT
STATUS(6)
PC = PC + 1
(SSS)~TMP
[9]
(ACT)+(TMP)+CY-A
,•.r....................
(A)-ACT
rA-~TMP
ADCM
1
000
1
1
1
0
(A)-ACT
HLOUT
STATUS[6J
ACI data
1
1
0
0
1
1
1
0
(A)~ACT
PC OUT
STATUS(6J
PC
SUB r
1
0
0
1
o
S
S
S
(SSS)~TMP
19J
(ACT)-(TMP)-A
PC + 1
B2-f.'
(A)-ACT
SUB M
1
0
0
1
o
1
1
0
(A)-ACT
HLOUT
STATUS[6J
SUI data
1
1
0
1
o
1
1
0
(A)-ACT
PC OUT
STATUSI6J
PC
SBB r
1
0
0
1
1
S S
S
(SSS)-TMP
(A)-ACT
191
(ACT)-(TMP)-CY-A
SBB M
1
0
0
1
1
1
1
0
(A)-ACT
HL OUT
STATUS[6J
SBI data
1
1
0
1
1
1
1
0
(A)·ACT
INR r
o
0
0
0
o
1
0
0
'.'"',,
PC OUT
STATUS[6J
00110100
DCA,
o
0
0 0
0
1 0
1
OCR M
o
0
1
1
o
1
0
1
INX 'P
o
0
R P
o
0
1
1
B:2-~'
PC + 1
i.',
ON
~~:::;:;;;~::;;~:;:;:;::
OATA-'"
PC = PC + 1
........-..
ALU-ODO
(TMP) + 1-ALU
INA M
OATA-~'
'.'
x
HLOUT
STATUS(6)
.,--
(OOO)-TMP
(TMP)+l-ALU
(AP) + 1
::::::::::::~ ~;;~;~~~~~~;;~;~~~~;;;;
ALU-ODO
:.:.: :-:: ::~
:-:
X
_. ...--,
,
DATA-.TMP
(TMP)+l-.ALU
HLOUT
STATUS(6)
'.".'
DATA-.TMP
(TMP)-l-.ALU
RP
-OCXrp
o
0
R P
1
0
1
(AP) - 1
1
RP
--+---~---~~---+------~------
DAD rplB)
o
0
R P
1
0
0
1
OAA
o
0
1
0
o
1
1
1
ANA,
1
0
1
0
o
S S S
o
1
ANAM
1
0
1 0
1
0
x
(ril-ACT
(L)-TMP
(ACT)+(TMPI-ALU
(9)
(ACT) +(TMPI-A
DAA~A. F LAGS[10J '.'
(SSS)-TMP
(A)-ACT
PC OUT
STATUS
PC = PC + 1 INST-TMP/IA
(A)-ACT
4-24
:-:
:.:
HLOUT
STATUS(6)
ALu--+L,CY
.--------------------------,----~~---~~-~----- ~-----~~ ..------"-~---:
J----------.-----~~~-------r_~
T3
T1
fTMP)
HLOUT
I---S~~~lJS~7J
PCOUT
STATUS[6J
PC
~
PC + 1
B3
PC
=
B3-
-
---~----------
M5
-~-----,--
T1
T3
T2[2J
T1
T3
T4
B3~
PC
=
PC + 1
B3
{{{ :}~{{{{:
..........
.rh
~W
~W
!--W
T5
::=:::::::=:::=:=:=:=::
......•.................
...................
.DATA BUS
PC + 1
PC" PC + 1
PCOUT
STATUS[6J
-~----
"~-
PC = PC + 1
I
I
~
M4
M3
WZ OUT
STATUS[6J
DATA
WZOUT
STATUS[7J
(A)-
WZ OUT
STATUS[6J
WZOUT
STATUS[7J
~~~~-
.............
.. .... .. .. .. .. ........
...........
DATA BUS
DATA-~~~
:::=:::::=:=:::::::::::
WZ OUT
STATUS[6J
WZ = WZ + 1
DATA BUS
(U
}~:}~:f~{:~
A
WZ = WZ + 1
.......................
.......................
............
........... .
WZOUT
STATUS17J
..:.. :-:.:.:-:.:.:.:.:. :.:..:..:.:.:.::.:.:.:.:.:.:.:.:.:.:
............. .......... . :.........................................
........."...........
:.:.:
..:.:.:.:.:.: .. :.:.: .:.:.:.:.:.:.:.:.:.:. ...............:....:...::.:.. :.. :.:.: .. :....:.:.:.:.:...:.:.:.
~{:~:~:~:}~:~:~:
...........
... ....... .
...........
...........
.......................
...........
............
~:~:~:~:~: ~:~......
:~:~:~: ~:~:~:~:. }~:~:~:~:~:~:~{:
...........
........... ~:~:~:~:
..........
. ........ .
[9J
(ACT)+(TMP)+CY~·A
(ACT)+(TMP)+CY-A
.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:
..................
..
:::=:::=;::::::::::::::
.:.:.:.:.:.:.:.:.:.:.:.
~~~~:t{{t~~ ~:}~{{{:~ :}t{(~{ ~f?): :~~rfrr~~ ~~~tt~
(ACTHTMP)--A
r[9J
..
......................... ......................
............
. ......... . .....................
:.:.:.:
..:.:.:.:.:.:.:.: :::::::::::=:::::::::
. ..........
.
.:.:.:.:.:.:.;.:.:.:.:.:.:.:.:.:.:.:
..................
[9J
.......
......................
.........................
:::::::::::::::::::::::
:::::::=:::::::::::::
.............................................
.. ........ ..........
..............
...
...
.
.
.
.
.
.
.
..
...........
...........
.............
............
........................ ·•·.·
... 01·.·.·.·.·.·.·.
..............................................
............ ..........
............
......... ...
...........
..........
........................
............ .......... .
:.:.:.:.:.:.:.:.:.:.:
.. : .:.:.:.:.:.:.:.:.:.:.
:::::::::::::::::::::: ~:~:~{:~:~:~:~{:~:~:~{:~:~:
[9J
......................
......... ..
...................
............ .......... ...........
(ACT)+(TMP)-A
...........
...........
............ ..................
[9J
..........
........ .
............
......... ..
..................................
:::::::::;::::::::::::: ::::::::::::::::::::: :::::::::::::;::::::::
:.:.:.:.:.:.:.:.:.:.:.: .:.:.:.:.:.:..:.:.:.:. :.:.:.:.:.:-:.:.:.:.:.
........... .......... ............ .......... .......... .
::::::::::::::::::::=: ::::::::::::::::::::: ::::::::::::::::::::::: ::::::::::::::::::::: :::::::::::::::::::::;
( ACT)-(TMP)~-A
:::::::::::::::::::::: ::::::::::::::::::::: :::::::::::::::::::::::.::::::::::::::::::::: :.:.:.:.:.:.:.:.:.:.:.
.........................
............
......... .
::::::::::::::::::::::
...........
.............
...........
...........
HlOUT
STATUS[7J
::=:::::::::=:::=::::
..................... :=:=:=:=:::=:=:=:=:=::::::=:=:=:=:=:=:=::;=::
ALU
-DATA BUS
............
.......... .
............
:..:.:.................
..............
............
:~:}~{{}. ............. ............
. .........
......... .
:::.::.:.:......::::.. :::.:::.:::.::.:.:.:
• ..•..
::::::::::::::::::::: :::::::::::::::::::::::::::::::::=:::::::::::
.:.:.:.:.:.:.:.:.:.:. :.:.:.:.:.:.:.:.:.:.:.:...:.:.:.:.:.:.:.:.:.:.
.....................
..........
..........
..........
. ........ .
..........
..........
..........
..........
::::::::::::::::::::
...........
ALU
HLOUT
STATUSl7J
_ DATA BUS
.............
......... ...
.............
.........
:.:.:.:.:.:.:.:.:.:.:.:
::::::::::::::~::::::::
:.:.:...:...:......:....
.............
........... .
:.:.:.:.:.:.:.:.:.:.:.:
.:.:.:.:.:.:.:.:.:.:.:.
:.:.:.:.:.:::.:.:.:.: ::.:.:.:::::-:::::.:.:::::::::::::::::::::::: ::.:::::::::::::::::=:
:::::::::::::::::::::.:::::::::::::::::::::::::::::::::::::::::::::".:::::::::::::::::::::
..........
. ......... ..
...........
........... ...... ...........
.....................
............ :=:::::=:::: :::::::=:::::::::::::::
....................
:.:.:.:.:.:.:.:.:.:.
..:.:::.':::::::,:::.::,::::,::,,::::,,:,:,:::,::,:
:::::::=:=:::::=:::= :::::::::::: ............
:::::::::::::::::::::::
............
...........
[9J
(Acn+(TMP)~A
4-25
MNEMONIC
M111]
OP CODE
M2
T3
T1
T4
0
o
1
1
0
1 0
1 0
1
S S
XRA M
1
0
1
0
1
1
XRI data
1
1
1
0
1
1
ORA,
1
0
1
1
o
S S S
(A)-ACT
(SSS)-TMP
ORA M
1 .0
1
1
o
1
1
0
(A)-ACT
HLOUT
STATUS(S]
ORI data
1
1
1
1
o
1
1
0
(A)-ACT
PCOUT
STATUS(SJ
CMP,
1
0
1
1
1
S
S
S
(A)-ACT
(SSS)-TMP
ANI data
1
XRA,
1
1
peOUT
STATUS
~
T2(2)
T1
T5
T3
PC + 1
(A)-ACT
PC OUT
STATUS(SJ
PC
S
(A)-ACT
(SSS)-TMP
19J
(ACT)+ (TPM)-A
1
0
(A)-ACT
HLOUT
STATuslSJ
1
0
(A)-ACT
PC OUT
STATuslSJ
PC~PC+l
(9J
(ACT)+(TMP)-A
PC
PC + 1 INST-TMP/IR
:.
~
DATA
PC - PC + 1
1
0
1
1
1
1
1
0
(A)-ACT
HLOUT
STATUslSJ
CPI data
1
1
1
1
1
1
1
0
(A)-ACT
PC OUT
STATUS[SJ
PC
RLC
000 0
o
1
1
1
(A)-ALU
ROTATE
[9J
ALU-A.CY
ARC
000 0
1
1
1
1
(A)-ALU
ROTATE
[9]
ALlJ-A,CY
RAL
000 1
o
1
1
1
(A), CY-ALU
ROTATE
[9)
ALlJ-A.CY
RAR
000 1
1
1
1
1
(A), CY-ALU
ROTATE
[9J
ALlJ-A,CY
CMA
001
0
1
1
1
1
(A)-A
CMC
o
0
1
1
1
1
1
1
CY-CY
STC
o
0
1
1
o
1
1
1
l-CY
JMP add,
1
1
0
0
o
0
1
1
J cond add,[17J
1
1
C
C
COl
0
CALL addr
1
1
0
0
1
1
0
1
SP = sp - 1
~~2~Js[SJ
C cond add,[17J
1
1
C
C
C
1
0
0
JUDGE CONDITION
I F TRUE. SP = SP - 1
RET
1
1
0
0
1
0
0
1
R cond add,[llJ
1
1
C
C
COO
0
INST-TMP/IR
JUDGE CONDITION[14J
RST n
1
1
N
N
NIl
1
-+w
.:.
'~•••~•••~•••~~
-f-'
B2·
r-'
DATA - _TMP
=
PC + 1
.:....
x
t=:::
=
B2-_'
DATA
CMPM
SP
_1 MP
(9J
.:
::: n
::~ ~:.:.:.: ~~ ~:~
JUDGE
CONDITION
.•.•.
I:;:;::········· ,'.
SP - 1
INST-TMPIIR
PC OUT
STATUS[SJ
PC
PCOUT
STATUS[SJ
PC
~
B2
-f-'
:.:
.•.•.•.
PC + 1
B2-f-Z
PC + 1
B2 -f-Z
PC = PC + 1
B2
PC OUT
ST ATUS[S]
PC = PC + 1
B2-'f-Z
SP OUT
STATUS[15J
SP = SP + 1
DATA-f-Z
SP OUT
STATUS[lS)
SP = SP - 1
(PCH) -f-DATA BUS
( H U - - - - - - t1
... PC
f-z
PCHL
1
1
1
0
1
0
0
1
PUSH,p
1
1
R
P
o
1
0
1
SP = SP - 1
~2~JS[lSJ
SP = SP - 1
(,h)-f-DATA BUS
PUSH PSW
1
1
1
1
o
1
0
1
SP = SP - 1
SP OUT
STATUS[lSJ
SP = SP - 1
(A)
POPrp
1
1
R
P
000
1
x
SP OUT
STATUS[15)
SP = SP + 1
DATA-f-'l
POP PSW
1
1
1
1
000
1
x
:::'.•....•......•
SP OUT
STATUS[15)
SP = SP + 1
DATA-f-FLAGS
XTHL
1
1
1
0
o
0
1
1
x
:.:
SP OUT
STATUS[15J
SP = SP + 1
DATA- ~Z
IN port
1
1
0
1
1
0
1
1
x
PC OUT
STATUS[SJ
PC = PC + 1
B2-f-Z. W
OUT port
1
1 0
1
o
0
1
1
x
PC OUT
5TATUsI6J
PC-PC+l
B2-f-Z. W
EI
1
1
1
1
0
1
1
1
INST-TMPIIR
:.:.:-:.:.:.:.:.:•.•.•.•~..
1
.'.
.',
:;.....
:.;
SET INTE F/F
.. .•. ...:::::::: :.:
.•.•.
.....
:.......
......
•.•.
'
01
1
HLT
o
1
1
1
1
1
1
o
0
o
1
1
RES·ET INTE F/F
1
.'. :.:
'.'
:~;
x
1 0
::: .":::::
:~:.:.::::::
NOP
o
000
o
000
PC OUT
STATUS
PC - PC + 1 INST-TMPIIR
4-26
x
::::
::: :::
:.' .•...
.•.•.
PC OUT
STATUS
::::: ..,
f-DATA BUS
;.:.:
.'. '.'.
,'.
:::.:::.;.:.
"'::: ;~~r~:: ~:~:~:~:~:::~:;:.::.
HALT MODEI:!>J
:::•...••..•',,'.::.:....~..:.....:.::.:.::.:~:~:;:~:~:;: ~'.'
.......•:.:
,
:.:;:N~~~:;:;:~:
,'.'
:.:~:.:.
:.:.:.:
'.'
':.:.:.:
M5
M4
M3
~--------"-.----------------,---------~~---------,---------.,---------~-------------~-
T212l
Tl
11
T3
[9J
(ACT)+(TMP)--A
19J
(ACT) +(TMP)-A
T3
T1
T2[2]
T4
T3
T5
(ACT)+(TMPI--A
[9J
...............
. . . . .. .......... ........... ...........
}~{:~
:~: ~ :~: ~: ~: :~ :~:}~:, .~:~:~:~
:~: ~:~ ~:~: ~:~:~:~: ~: ~:~: ~:~ :: ~:~:~:}~: ~:~: ~:~: ~:~:~: ~: ~:~ :~: ~:~: ~:~:~
-"---------+-""---" -
[9[
~:.~ :.~ :.'~',: ~ :,~',:~ ~ :.~ ',: ~ :.~ ~ :.~ :,~ :.~ :.' ~ :.' ~:.},~ :.~ :.~:.~ :.~ :.' ~
:.'
(ACT)+ITMP) -A
(ACT) - ITMP) FLAGS
[9
[9J
T2[2l
Tl
,
-----+-----'---i (ACT) -(TMP)
..... ' .... ,.... ',..', ........ ' .., ..
~:,' ~ :.~ :,~ :.~ :.~ :.~:.~ :.' ~ :.~ :.~ ',: ~ :.~
:=:=;=:::=:::=:::=:=:=:=:::=:=:=:=:
I PC
PC OUT
STATUS[6J
FLAGS
c
PC + 1
B3 - f-W
SP OUT
STATUS[16]
(PCH)---- f-DATA BUS
SP : SP - 1
SP OUT
STATUS[16J
(PCL)-
PC + 1
B3
SPOUT
STATUS[16]
(PCH)~
SP OUT
STATUS[16]
(PCL)--1
SP: SP - 1
f-W[13]
PCOUT
STATUS[6J
PC
SP OUT
STATUS[15]
SP~SP+l
DATA_W
SP OUT
STATUS[15J
SP
DATA
SPOUT
STATUS[16]
(TMP
c
SP + 1
~
OONNNOOO)(PCL!
-z
_GATA
_DATA BUS
DATA BUS
........ .......
DATA BUS
.....
FLAGS
t
I
BUS
f-DATA BUS
:,'.
:,'
DATA
f-rh
SP OUT
STATUS[15J
SP
SP + 1
DATA
f-A
=
SPOUT
STATUS[15J
DATA- f-W
WZOUT
STATUS(18)
DATA
::::::::::::::::::::
............
.. :..:..:.. :..:.:.:.: .. :.:
SPOUT
STATUS[16]
(H)----- -DATA BUS
~A
:=:=:::=:=:=:=:::=:::::=
SPOUT
STATUS[16]
.......................................................
=:::=:=;=:=:=:=:::::=::::=:::=::;::::::=:=:=:
(A)- ~~TA BUS
:::::::::::::::::::::;:: ::::::::::::::::::::::::::::::::::: :.:.:.:.:.:..:.:.:.:.:. :.:.:.:..:.:...:.:................ :...:...:.. :.:
:.:.:.:.:.: . :.:.:.:. :.: . :.:.:.:.:.:.:.:. :. :-:.:.:.:.:.:.:.: :::::::;:::::::::::::: ::::::::=:::::::::::::::::::::::::::::::::::
...........................
~
..
SP = SP + 1
WZOUT
STATUS!18]
~:,'~,:~.:~.:~.: ~',:~.: ~ ~,: ~.: ~ :,' ~',:~ ~.:~',:~,:~.: ~.:~,:~ :,~.: ~ ~'.:~.;~.:~.: ~.:~,:~:.~'.:~',:~,:~',: ~,:~',:~,: ~,: ~',:~.:~',:~,:~',: ~.,: ~,{,:~,:~,:~:,~-.:~:,'~ ::::;::::::::;::::::
............................. ........
.. .. ....
.. ..
.:.:.:.:.:.:.:..:.:.:.:. :.:.:... :.:.:.:.:.:.:.: :.:.:..:..:.. :.;.:..:.:.:.................................................................
..
::=:::::::::::::::::::: ::::::::::::::::::::: :::::::::::::::::::::: ::::::::::::::::::::::: :::::;::::;:: ::::::::::::::::::::
'.:
SP OUT
STATUS[15J
...:
(WZ) + 1 - PC
WZOUT
STATUS[ll1
(WZ) + 1 - PC
WZOUT
STATUS[l1,12]
(WZ) + 1 - PC
(WZ) + 1 - PC
SPOUT
STATUS[16]
SP OUT
STATUS[16J
:.:.:.:~
WZ OUT
STATUS[11,12J
...........
:.:-:.:.:.:.:-:.:-:-:
:::::::::::::::::::::
4-27
(L)- -
DATA BUS
WZOUT
ST ATUS[11,12]
(WZ) + 1 - PC
WZOUT
STATUS[ll]
(WZ) + 1 -PC
NOTES FOR CHART ON PRECEDING PAGES
1. The first memory cycle (M 1) is always an
instruction fetch; the first (or only) byte, containing
the op code, is fetched duri ng this cycle.
2. If the READY input from memory is not high
during T2 of each memory cycle, the processor will
enter a wait state (TW) until READY is sampled as
high.
13. If the condition was not met, sub-cycles M4 and
M5 are skipped; the processor instead proceeds
immediately to the instruction fetch (M 1) of the next
instruction cycle.
14. If the condition was not met, sub-cycles M2 and
M3 are skipped; the processor instead proceeds
immediately to the instructi on fetch (M 1) of the next
instructi on cycle.
3. States T 4 and T5 are present, as requi red, for
operations which are completely internal to the CPU.
The contents of the internal bus during T 4 and T5 are
available at the data bus; this is designed for testing
purposes on Iy. An
X" denotes that the state is
present, but is only used for such internal operations
as instruction decoding.
15. Stack read sub-cycle.
16. Stack write sub-cycle.
II
4.
rp
5.
NZ
Z
NC
C
PO
PE
P
M
Only register pai rs rp == B (registers B and C) or
= 0 (registers 0 and E) may be specified.
These states are skipped.
6. Memory read sub-cycles; an instruction or data
word wi II be read.
7.
Memory write sub-cycle.
not zero (Z = 0)
zero (Z == 1)
no carry (CY == 0)
carry (CY = 1)
parity odd (P = 0)
parity even (P = 1)
plus (S = 0)
minus (S == 1)
000
001
010
011
100
101
110
111
18. 1/0 sub-cycle: the 1/0 port's 8-bit select code is
duplicated on address lines 0-7 (A - ) and 8-15
O7
(A8- 15 l.
8. The READY signal is not required during the
second and third sub-cycles (M2 and M3). The HOLD
signal is accepted during M2 and M3. The SYNC
signal is not generated during M2 and M3. During the
execution of DAD, M2 and M3 are required for an
internal register-pair add; memory is not referenced.
19. Output sub-cycle.
20. The processor will remain idle in the halt state
until an interrupt, a reset or a hold is accepted. When
a hold request is accepted, the CPU enters the hold
mode; after the hold mode is terminated, the
processor returns to the halt state. After a reset is
accepted, the processor_ begins execution at memory
location zero. After an interrupt is accepted, the
processor executes the instruction forced onto the
data bus (usually a restart instruction).
9. The results of these arithmetic, logical or rotate
instructions are not moved into the accumulator (A)
until state T2 of the next instruction cycle. That is, A
is loaded while the next instruction is being fetched;
this overlapping of operations allows for faster
processing.
10. If the value of the least significant 4-bits of the
accumulator is greater than 9 £!: if the auxiliary carry
bit is set, 6 is added to the accumulator. If the value
of the most significant 4-bits of the accumu lator is
now greater than 9, ~ if the carry bit is set, 6 is
added to the most significant 4-bits of the
accumulator.
11. This represents the first sub-cycle
instruction fetch) of the next instruction cycle.
cce
17. CONDITION
SSS or DOD
Value
rp
Value
A
111
000
001
010
B
0
00
01
10
11
B
C
0
E
(the
H
L
12. If the condition was met, the contents of the
register pair WZ are output on the address lines
(A - 15 ) instead of the contents of the program
O
counter (PC).
4-28
all
100
101
H
SP
Part No. 42335-XX
Part No. 42403-XX
TTL 3-line to 8- Line Decoder
Type 8205
Type 25LS 138
Logic Symbol
1 A¢
o¢
01
A1
02
03
04
05
06
07
A2
E1
E2
E3
VCC-16, GND-8
Truth Table
AO
A1
A2
L
L
L
L
L
L
L
H
H
H
L
H
L
L
L
H
H
H
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
Loading:
Inputs
Outputs
H
H
H
H
X
X
X
X
X
X
X
Inputs
E1
Outputs
E2
E3
0
1
2
3
4
5
6
7
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
L
L
L
L
H
H
H
H
H
H
L
H
H
H
H
H
8205
.16 Unit Load
6 Unit Loads
H
H
H
H
H
H
H
H
25LS138
.25 Unit Load
5 Unit Loads
4-29
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
TTL 8-bit I/O Port, Schottky
Part No. 42337
Type 8212
Th is device contains an 8-bit latch with three-state
output buffers and logic to allow independent control
of input and output. It also has an internal Service
Request flip-flop for generating interrupts for the
MPU.
Logic Diagram
Logic Symbol
011
001
4
012
013
OS!
OS2
014
015
!\olD
016
017
018
OS1
OS2
001
012
002
013
003
014
INT
MD
STB
Oil
005
006
C
007
14
008
VCC-24, GND-12
Function Table
Mode
Input
Output
MO
L
L
L
L
L
L
H
H
H
Inputs
DS1=L
OS2=H
STB
No
No
No
Yes
Yes
Yes
No
Yes
Yes
011-8
X
L
H
H
L
H
H
L
H
X
H
L
X
X
X
X
H
L
Outputs
001-8
Internal
Latches
Hi-Z
Hi-Z
Hi-Z
Previous H/L
H
L
Previous H/L
H
L
No Change
Load L
Load H
No Change
Load H
Load L
Read
Load H
Load L
Interrupt Generation
Loading:
Inputs
Inputs
C, OS2, D 11-8, STB
MO
DS1
.16 Unit Load
.46 Unit Load
.62 Unit Load
Outputs
9 Unit Loads
OSl=L
OS2=H
No
No
No
Yes
4-30
C
STB
L
H
H
L
L
X
•
X
5-R
ff
Output
INT
H
No Change
H
L
X
L
L
TTL Clock Generator/Driver, Schottky
Part No. 10215
Type 8224
Clock Generator
The device provides the 12 volt, non-overlapping
clocks required by the 8080 MPU. The frequency of
the output signals is determined by an external
crystal (crystal frequency = 9 times clock frequency).
It also provides power-up Reset and Status Strobe
functions.
The clock generator provides the 12 volt 01 and
~2 signals needed by the 8080, plus a ~2 TTL signal
for related logic.
Status Strobe
Logic Sy mbol
The SYNC signal from the 8080 is used to
generate STSTB (low active) at the earl iest possible
moment that the 8080 status data is stable on the
MPU data bus (at the beginning of each 8080
machine cycle). This STSTB signal is used by the
8228 System Controller IC. STSTB is also developed
when RST is produced.
+ 12V
9
VOD
OSC 12
Reset
A pulse is developed automatically at turn-on
when power reaches a minimum predetermined value.
A level is produced when the RST-IN input is driven
low.
2 5 SYNC
RSTIN
ROY I N
STSTB
RST
Ready
The ROY input to the 8080 must meet certain
critical timing requirements. An asynchronous signal
can be applied to the 8224 on the ROY-IN input, and
the ROY output of the 8224 will be synchronized
properly with the 8080.
RDY
VCC-16, GND-8
Loading:
Inputs
Outputs
ROY, RST,STSTB
~2,OSC
.16 Unit Load
1.5 Unit Loads
9 Unit loads
4-31
TIL Bus Driver/System Controller, Schottky
Part No. 42331
Type 8228
This is a combination bi-directional 8-bit bus
driver and system controller for use with the 8080
MPU.
Logic Symbol
Status Word Chart
TYPE OF MACHINE CYCLE
!
+sv
28
vee
15
17 O¢
01
12
02
10
03
6
04
19
OS
13
DB¢ 16
DB1
11
DB2
9
DB 3
DB4
DB S
Db
DB 6
07
OB7
OBIN
INTA
WR
MEM R
HLOA
I/O R
BUS EN MEM W
I/O W
STSTB GNO
1
(0
@
G)
'4)
7)
(8)
(9)
Qg
DO
01
INTA
0
0
0
0
0
0
0
1
0
1
WO
1
1
1
0
1
o'
1
1
1
02
STACK
0
0
0
0
1
1
0
0
0
0
0
03
04
HlTA
0
0
0
0
0
0
0
0
1
1
OUT
0
0
0
0
0
0
1
0
0
0
Os
M,
1
0
0
0
0
0
0
1
0
1
06
INP
0
0
0
0
0
1
0
0
0
0
07
MEMR
1
1
0
1
0
0
0
0
1
0
(5)' /6)
I
-
INTA
(NONE)
INTA
I/OW
I/O R
MEMW
r-
CONTROL
SIGNALS
MEMR
MEMW
MEMR
MEM~
System Controller
Bus Driver
When driving into the 8080 MPU, this device
provides a minimum of +3.6 volts, well above the
+3.3 volts required by the 8080. On 8080 output,
this· device provides 10 rna of drive current, as
opposed to the 8080' s 1.9 rna. The di rection of data
flow on the bus is controlled by the System
Controller portion of this IC. The BUS EN input
turns the bus driver on and off; when BUS EN is high,
the bus outputs are in the three-state high-impedance
condition.
At the beginning of each 8080 machine cycle, the
status information from the 8080 is loaded into a
6-bit latch inside the 8228. The STSTB signal from
the 8224 IC strobes this latch. The outputs of this
latch are then gated by the DBIN, WR, and HLDA
outputs from the 8080 to produce the system control
outputs MEM R, MEM W, I/O R, I/O W, and INTA.
Interrupt Acknowledge (lNTA) is normally used to
gate instruction data from the peripheral circuitry
onto the data bus after the MPU has been
,interrupted. A special feature of this IC allows an
RST7 (Restart 7) instruction to be gated into the
MPU automatically whenever the MPU is interrupted.
This is accomplished by connecting the INTA output
to +12 volts through a 1K resistor.
4-32
Type 8228
Timing Waveforms
T2
01
02 _ _ _
..J
v
-STATUS STROBE
8080 DATA
v
BUS ________~)(~______~><~
_____________________________________
DBIN __________________~/
-I NTA I -lOR
t -
\~---------------------__JI
M EM R - - - - - - - - - - -......\~______________
SYSTEM BUS DURING READ
8080 BUS DURING READ
~-= ==- ==-
=-==-= ====><
><== ~ -= -= =-=-= ==== =-= =
>--------.------
--------------<=::)<
HLDA
/
I
- INTA t -IOR,-MEMR -------------..\
DURING HLDA
~.-------------',
"---~/
WR
\
lOW OR MEM W
8080 BUS DURING WRITE
=
/
:= = -= == ==== =-= -= ___ X"-_____________________
SYSTEM BUS DURING WRITE - - - - - -
..J
- - -
-
<:'-_______..JX~___________________
\~_____~/
SYSTEM BUS ENABLE
SYSTEM BUS OUTPUTS - - - - - -
-
- - -
-
- -
- - <, _____,,> - - - -
Loading:
Inputs
02,06
STSTB
Others
.46 Unit Load
.31 Unit Load
.16 Unit Load
Outputs
00-07
Others
1.25 Unit Loads
9 Unit Loads
4-33
-
- - - - - -
- -
-
MOS Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
The USART is used to interface the serial data
channel of a terminal or communications device to
the parallel data channel of a computer or terminal.
The transmitter section converts parallel data into
serial words with start bits, stop bits, and (if desired)
parity bits. The receiver section converts serial data
into parallel words, while stripping off the start bits
and stop bits, checking word length, and, if desired,
checking parity. Both the receiver and transmitter are
Part No. 42336
Type 8251
double buffered. Parallel words can contain up to
eight bits. Serial word length can be 5, 6, 7, or 8 bits.
Parity can be even or odd, or parity checking and
generation can be inhibited. The number of stop bits
can be either one or two (or 1-1/2 when word length
= 5 bits). Transmitting and receiving can occur
simultaneously (full-duplex). Transmit and Receive
Clocks must be supplied at 1, 16, or 64 times the
desired baud rate.
Logic Symbol
Block Diagram
+5V
26
vee
21
TRANSMIT
BUFFER
O~
29
01
1
02
TkO
(P-S)
03
04
TxRDY
TRANSMIT
CONTROL
6
05
7
06
8
TxE
_TxC
OSR
OTR
RxO
RTS
Rxe
RxO
RO
WR
c/o
TxD
TxE
Tx ROY
RxROY
DSR
eTS
cs
/
INTERNAL
DATA BUS
OT R
RTS
SYNOET
GNO
4
Loading:
Outputs
R.RDY
/
1 Unit Load
4-34
R.C
CONTROL
_SYNDET
MOS Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
This is a three-state, bidirectional, 8-bit buffer
used to interface the 8251 to the MPU system data
bus. Data, control words, command words, and status
information are transferred through this buffer.
CTS (Clear to Send). A low on this input enables
the 8251 to transmit serial data if the TxN bit in the
command byte is set to a 1.
ReadIWrite Control Logic
DTR (Data Terminal Ready) and RTS (Request to
Send). These two outputs can be set low by
programming the appropriate bits in the command
instruction word. They are normally used for modem
control.
Control inputs from the MPU system are received
and stored here Control/command bits stored here
influence subsequent 8251 operation.
RST (Reset). A high on this input forces the 8251
into an "idle" cOr:'dition, where it remains until a
Mode instruction is received.
Trans·mit Buffer
This buffer accepts parallel data from the Data Bus
Buffer, converts it to a serial bit stream, inserts the
appropriate characters or bits, and outputs a
composite serial stream of data on the TxD pin. It
consists essentially of two buffers, ~ transmit buffer
and a holding register.
ClK (Clock). This input is normally driven by the
02 (TTL) output of the 8224 Clock Generator, to
provide timing for internal operations. This clock
must be greater than 30 times the RxC and TxC
frequency for synchronous operation and 4.5 times
for asynchronous operation.
Transmit Control
WR (Write). A low on this input signals the8251
that the MPU is writing (outputting) to the 8251.
This section controls the Transmit Buffer and
provides the signals necessary to synchronize
transmission with the MPU.
RD (Read). A low on this input signals the 8251
that the MPU is reading (inputting) from the 8251.
TxRDY (Transmit Ready). This output goes high
to inform the MPU that the transmit holding register
is ready to accept the next character, The MPU can
also check this condition by performing a status read
operation. This output goes low (at least
momentarily) when a character is received from the
MPU, and returns high when the character is
transferred from the holding register to the transmit
buffer.
C/O (Control/Data). This input, along with the
WR and RD inputs, informs the 8251 whether the
word on the data bus is a data, control, or status
word.
L
H
H
WR
RD
Function
X
X
L
Data
Status
Control
H
L
H
Type 8251
(Continued)
DSR (Data Set Ready). This input is normally
used to test modem conditions such as Data Set
Ready. Its condition is tested by the MPU performing
a status read operation.
Data Bus Buffer
C/O
Part No. 42336
TxE (Transmitter Empty). This output goes high
when the transmitter has no more characters to
transmit. It goes low when a character is received
from the MPU.
CS (Chip Select). A low on this input enables the
8251. A high disables all reading and writing and
drives all outputs into the high-impedance state.
TxC (Transmit Clock). The signal applied to this
input controls the rate of data transmission. In
synchronous transmission, the baud rate is the same
. as the TxC rate. In asynchronous transmission, the
TxC rate can be 1, 16, or 64 times the baud rate,
determined by the Mode instruction. The serial data
is shifted out of the 8251 on the falling edge of TxC.
Modem Control
These inputs and outputs can be used to interface
to the mode m, or they can be used for other
functions as desi red.
4-35
MOS Universal Synchronous/Asynchronous Recei~er/Transmitter (USART)
Receive Buffer
SYNOET (SYNC Detect). This pin is used in
synchronous mode only, and it can be used as either
an input or an output, programmable through the
Control word. When used as an output, it goes high to
indicate that the 8251 has received a SYNC character.
If the 8251 is programmed to use double SYNC
characters, then SYNOET goes high in the middle of
the last bit of the second SYNC character. The
cond it ion of this output is also available to the MPU
via a status read operation, which automatica!ly resets
the SYNOET condition.
This buffer accepts serial data from the RxO
input, converts it to parallel format, checks for bits or
characters accord ing to the establ ished mode and
control words, and provides this data to the MPU.
Receive Control
. This section controls the Receive Buffer and
provides the signals for synchronizing it with the
MPU.
SYNOET may be used as an input if the check for
synchronization is made by external logic. In this
case, when SYNOET is driven high, the 8251 begins
assembling serial input data into characters on the
fallin~ edge of the next RxC.
RxRDY (Receiver Ready). This output goes high
to inform the MPU that the 8251 has a character
ready to be input to the MPU. This condition can also
be checked via a status read operation. The output is
driven low when the character is received by the MPU
(when RD is driven low).
Mode Instruction
RxC (Receiver Clock). The signal applied to this
input controls the rate of data reception. In
synchronous mode, the RxC rate must be the same as
the baud rate. In asynchronous mode, the RxC rate
can be 1, 16, or 64 times the baud rate,' as determined
by the Mode instruction. The data on the RxO input
is sampled and shifted into the 8251 on the rising
edge of RxC.
D7
D6
D5
D4
I S2 I Sl I EP I PEN I
D3
D2
D1
DO
L2 ILl I B2 I B 1
I
Type 8251
(Continued)
Part No. 42336
The first "control" (C/O high) write after a Reset
loads ,the Mode instruction into the 8251. Any
subsequent control writes load Command
instructions. The Mode instruction format is as
follows:
I
I:
Baud Rate Factor
L
H
L
H
~~L__~~L-+___
H+-H~
Sync
Mode
1x
16x 64x
Character Length
L -_ _ _ _ _ _ _ _ _ _ _ _
1.-_ _ _ _ _ _ _ _ _ _ _ _
L
L
H
L
L
H
H
H
5
6
7
8
H
~
Parity enabled
L
=
Parity disabled
H
L
=
=
Even parity
Odd parity
H = SYNDET is an Input
L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ L = SYNDET is an Output
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ H = Single SYNC character
L = Dquble SYNC character
Synchronous
4-36
No, of bits
II
I
Number of Stop Bits
L
H
L
H
L
L
H
H
Not
Used
1
1%
2
Asynchronous
Part No. 42336
MOS Uf\iversal Synchronous/Asynchronous Receiver/Transmitter (USART)
Command Instruction
Type 8251
(Continued)
After the mode instruction has been loaded,
subsequent control writes load the Command
instruction, as follows:
07
06
05
I SYN I RST I
H = Enable Search
for SYNC
L = Normal
RTS
I
04
ERR
03
02
01
00
I BRK I RxE I OTR I TxN I
L
J
H = Enable Transmit
L = Disable Transmit
High forces OTR
output low
H = Reset 8251
H = Enable Receive
L = Oisable Receive
High forces RTS
output low
H forces TxO low
L = Normal
High resets error
flags PE, FE, OE
Status Read
When a Read operation is performed with the C/O
input high, status is provided to the MPU on the
parallel data bus as follows:
D7
06
I
SYN
DET .
Framing Error.
Stop bit not
detected at end
of character
(Async only).
05
FE
D4
OE
D3
PE
I I
D2
TxE
!
D1
DO
!
!
I
Same definitions
as output pins
Parity Error.
Received character had
incorrect parity
bit.
Overrun Error.
A second character was received
before the first
was read by the
MPU. First char·
acter is lost.
4-37
Part No. 42407-01
Universal Communication Interface
Type 8255
Logic Symbol
VCC
...1l..
PC4
~
RST
2.0 RO
3~WR
~ PA~
2.
PA1
~
PA2
...!...
PA3
"':Q..
PA4
~
PAS
~
PAS
_37
PA7
PC¢
~
PC7
~
PC1 ~
PC3 !2.
PC5.!3..
PC6 ~
BIDIRECTIONAL DATA BUS
A
16
~
OATA
!
PCZ
RD ---.a~
19
WR
-PB1
~
PB2
~
PB3
~
PB4
~
PBS
~
PBS
~
PB7
'""
I
READ
WRITE
--H-__
A 1 - - - - - - . . - I CONTROL
AS
LOGIC
01
~
02
~
04
~
05
~
06
~
07
~
RESET
--~
GR~UP
CONTROL
I
cs - - - " ' , - ( " 1
29
27
PIN NAMES
GNO
07 - DO
DATA BUS (BIDIRECTIONAL)
RESET
RESET INPUT
CS
CHIP SELECT INPUT
RD
READ INPUT
WR
WRITE INPUT
AO,Al
REGISTER ADDRESS
PA7-PAO
A REGISTER (BITS)
PB7-PBO
B REGISTER (BITS)
PC7-PCO
C REGISTER (BITS)
VCC
15 VOLTS
GND
o VOLTS
4-38
/,A _ _
""
1: "
~
GROUP
B
A
...)
1/0
1'..--------,.,,,"1 B RE~~~TER I~".r-T"~--,",/ PB7-PB.8
r
Universal Communication Interface
Part No. 42407-01
The 8255 is a general purpose, programmable interface
designed for use with 8080 microprocessor systems to
provide communication between the 8080 and a variety of
peripheral devices. An eight-bit bidirectional data bus
buffer interfaces the 8080 system bus with the 8255
internal data bus. Three eight-bit registers - called A, B,
and C - can be connected directly to the peripheral device.
The three registers can be configured by system software or
firmware to suit the input/output requirements of a specific
peripheral device. The C register can be split into two
four-bit registers, and can also be used for control and
status signals in applications requiring them. The'
microprocessor can read from or write to any of the three
registers via the data bus buffer.
The operating modes are as follows:
Mode 0 - Basic Input/Output. The A and 8 registers can
be separately defined as input or output. The C register
can be split into two four-bit registers, one input and the
other output, or it can be used for all input or all
output. Sixteen different register ~nfigurations are
available. No strobes or handshaking are involved.
Mode 1 - Strobed Input/Output. The A and 8 registers
can be individually programmed for input or output. Six
bits of the C register are used as control and status bits
for the A and 8 registers; the remaining two bits of the C
register can be programmed as either input or output.
Communication between the microprocessor and the
interface is maintained over the eight bidirectional data bus
lines, four control lines, and two address lines. The
microprocessor selects the 8255 operating mode by sending
a Control Word over the data bus lines. The Control Word is
also used to define registers as being input, output,
bidirectional, or control. Only the A register can be
bidirectional, and only the C register can be used for
control. Individual bits of the C register can be set or reset
by a Control Word.
There are three operating modes. Registers are controlled in two groups of 12 bits each. Control Group A
controls the eight bits of the A register and the four
high-order bits of the C register (C7 - C4); Control
Group 8 contlols the eight bits of the B register and the
low-order half (C3 - CO) of the C register. Since the
structure of the Control Word permits separate programming of the two groups, the 8255 can operate In two
modes simultaneously. Operating mode is set during system
initialization, and can be changed during program execution
by sending a new Control Word over the data lines.
Type 8255 (Continued)
Mode 2 - Strobed Bidirectional Input/Output. The A
register can be used for two-way communication with a
peripheral device. Five bits of the C register are used for
control and status fot" the A register; the remaining three
bits of the C register can be used for input, output, or.
control, depending on the mode of the 8 register. When
the B register is in Mode 0, the C register bits could be
input or output. In mode 1, the three bits of the C
register would be used for control' and status of the
8 register.
In Mode 1 or Mode 2, when the C register is used for
control and status, the peripheral device is permitted to
interrupt the 8080. The 8080 program can enable/disable
interrupts by setting/resetting individual C register bits.
Loading:
When a register is programmed for output, up to eight
output buffers, selected randomly from the 8 and C
registers, can furnish 1 mA at 1.5 volts to drive Darlington
type or similar circuits. Other outputs can drive 1 unit load.
4-39
Part No. 42191-33
Keyboard Encoder
A non-programmed MOS/LSI Scanner,
in a 28-lead dual-in-line package.
Used in Cortron Up/Dn stroke keyboard. Supply Voltages:
Vss = 5V at 40 rna.
Vdd = OV at 50 rna (for TTL outputs).
Vgg =-12V at 40 rna.
The device has 12 TTL/DTL outputs
which are capable of sinking 1.6 rna.
These outputs are:
Pin
19. SR out
12. 01
13. 00
Pin
14. Strobe
18. Flag (SRIN)
and B1 through B7
Each of these outputs has the following
specifications:
Logic "1" (high)
Logic "0" (low)
= 2.4V min. at 100 /la
= 0.4V max. at 1.6 rna
The device has 7 standard TTL/DTL compatible
outputs, each capable of sinking 3.2 rna. These
outputs are A1 through A7.
Each of these outputs has the following
specifications:
Logic "1" (high)
Logic "0" (low)
= 2.4V min. at 200 /la
= 0.4V max. at 3.2 rna
This device has 6 logic inputs
Pin
17. Function
10. Data in (FF)
11. Clock in
Pin
20. Bypass shift logic
15. Latch Inh
16. NKR/2KRO
Type MM5873
Logic Symbol
9
A1
8
A2
7
A3
6
A4
5
A5
A6
4
3
A7
27
81
26
25
82
83
84
24
23
85
22
21
86
87
10
11
FF
~
16
elK IN
II
NKR/2KR
~ FN
'"
~ 8Sl
-
,1
12
13
,3
ST8
~
SRIN
SRO
19
18
Voo - 1 (GRN)
VGG -
2 (-12V)
Vss - 28 (+5V)
083-048
Each input has the following specification:
= Vss -2V min.
= Vss +0.3V max.
Yin (Logic 0) = Vss -4.0V max.
= Vgg min.
Yin (Logic 1)
A pull-up resistor is provided for each input on the device.
4-40
Keyboard Encoder
Type SD25010-K
Part No. xxx xxx
An LSI programmable circuit in a dual-in-line
package. Used in the MICROSWITCH
keyboard in the Model 1660.
Logic Symbol
POWER SUPPLY
+5 VDC at lAmp, Max.
OUTPUT SPECIFICATIONS
Data Bits DO-D7 and Strobe.
1. Logic '1' (high)
X15
X14
Oil
X13
X12
02
X11
= 2.4V min. at 40 Ila
2. Logic '0' (low) = 0.4V max. at 1.6 rna
XO-X15 will handle a full matrix of Hall
effect logic scan switches.
01
03
X10
04
05
X9
06
X8
X7
(NOT USED)
X6
07
(NOT USED)
27
28
29
30
31
32
33
34
35
36
X5
X4
YO-Y7 will handle a full matrix of Hall
effect logic scan switches.
X3
STB
37
X2
INPUT SPECIFICATIONS
X1
X¢
Strobe Reset and System Reset (POR)
inputs.
High level voltage =2.0V
Low level voltage = 0.8V
High level current =0.25 rna source
Low level current = 1.6 rna source
Y¢
Y1
Y2
Y3
Y4
Clock Input - External Drive Option.
High level input voltage = Vdd -1.0V
Low level input voltage = 0.8V
Y5
Y6
Y7
STR
SYSR
40
OSC
Vee - 1
Vss -
4-41
21
083-047
Microprocessor
Type CPU11806
Part No. 13144
The PPS-8 Central Processor Unit,
is a complete 8-bit parallel processor
on a single MOS chip. The Central
Processor Uni t (C P U) uses f ourphase dynamic logic for operation.
The CPU contains:
(a) Logic necessary to receive and
decode the instructions
(b) 8-bit parallel adder-accumulator for
arithmetic and logical operations
(c) 14-bit P-Register for sequencing
through the ROM program
(d) 16-bit L-Register for subroutine
linkage, RAM operand addressing,
and ROM indirect addressing
(e) Three 8-bit registers, (X, Y and Z)
for RAM operand addressing
(f) 5-bit stack pointer S for addressing
a dedicated RAM area
(g) Logic for processing a priority
interrupt structure
(h) Direct memory access (DMA) mode
(i) Multiplexed receivers and drivers for
interfacing with the 14-bit multiplexed
address bus and the 8-bi t bi-directional
data/instruction bus.
The CPU, through time multiplexing,
utilizes an 8-bi t bi-directional bus to
transfer instrctions from ROM to CPU
(and I/O) during 04, and to transfer data
between the CPU, RAMs and I/O devices
during 02.
Logic Symbol
20 1101
A/B1
21
1/02
A/B2
22 1/03
A/B3
23 1/04
A/B4
24 1105
A/B5
25 1106
A/BS
26 1/07
A/B7
27 1/08
A/B8
A/B9
A/B10
A/B11
4
2
ClK A
A/B12
ClKS
A/B13
11
10
9
8
7
S
3
17
18
19
15
14
A/B14
34
28
29
30
PO
SPO
INT 0
ACKO
INT 1
DMRA
35
33
37
INT2
WIIO
31
RIH
VDD -16
VSS -- 41
(083-042)
FUNCTIONAL DESCRIPTION
Instructions for the PP-8 CPU are either one, two, or three bytes in length,
and require from one to three clock cycles for execution. The CPU decodes
instructions, senses interrupt and D MA requests, and controls data transfer,
arithmetic, logical, and indexing operation.
The adder, with the 8-bit accumulator register (A), and associated logic circuits
forms the Arithmetic and Logical Unit (ALU). The A register is the primary
working register in the CPU and the central data interchange for most data
operations. The adder is an 8-bit parallel binary adder with an internally
connected carry flipflop (C), used for precision arithmetic operation, packed
BCD (decimal) arithmetic, and hexadecimal data manipulation. Accumulator
circular shifting right and left with carry linkage is also available.
4-42
Microprocessor (continued)
Part No. 13144
Type CPU 11806
P-REGISTER (14-BITS)
Y-REGISTER (8-BITS)
The P-Register contains the address
of the instruction currently being executed, and automatically increments
(least significant 7-bits) to fetch the
next byte from instruction memory
(ROM). It may be altereQ during the
execution of Branch, Return or Skip
instructions.
The Y-Register is used as an alternate
lower RAM address register and as a
"loop counter" or it may be used as a
general purpose program m ing register.
S-REGISTER (5-BITS)
The 5-bit up-down counter S-Register
is used as an address pointer to a 32
byte "stack" in RAM. This stack pointer
is automatically incremented each time
a byte is "pushed" into the stack and
decremented each time a byte is "popped"
from the stack.
L-REGISTER (I6-BITS)
The L-Register saves the return address
after a subroutine call or an interrupt.
It is also used as an address register
for indirect ROM operands, as an alternate RAM address register, or as a general purpose programming register.
W-REGISTER (8-BITS)
The W- Register serves pri marily as an
internal buffer register. Additionally,
it is used in conjunction with the LAL
and PSHL instructions.
Z-REGISTER (8-BITS)
This register holds the 7 most significant
bits of the 14-bit RAM operand address
or may be used as a general purpose
programming register.
POWER-ON RESET (PO)
The Power-On input signal is used to
initialize the CPU to a known starting
address and state during a power-on
sequence. The Power-On (PO) signal
is generated external to the CPU. The
CPU receives this signal, initializes
the internal logic states, and at the same
time generates a Synchronized PowerOn output (SPO) signal which is used
to initialize other circuits of the PPS-S.
X-REGISTER (8-BITS)
The X-Register holds the 7 least significant bits of the 14-bit RAM operand
address. The most significant bit (8th
bi t) is used as an upper RA M address
control bit.
Logic 1
Logic 0
r
- the Z-Register contents are output for
the most significant
7 bits of the RAM
address.
- logic zero is output
for the most significant 7 bits of the
RAM address.
I CLOCK CYCLE
I
,~-SYSTEM {A
CLOCK
ii
ADDRESS BUS
114 LINES)
This register may be loaded, stored,
and automatically incremented or decremented under program control.
DATA BUS
(II LINES)
READ INHIBIT
(I LINE)
WRITE CillO
I/O ENABLE
(. LINE)
4-43
PPS-8
BUS
1/0
WRITE
CMD
t= WRITE
ENABLE
O=SELECT
0=WRi"TE
RAM
TIMING
BASIC
Microprocessor (continued)
Part No. 13144
PPS-8 INSTRUCTIONS SET LIST
Skip/Branch Group
B
BDI
NOP
SKC
Data Transfer Group
L
LN
LD
LNXL
LDXL
LNCX
LDCX
LNXY
S
SN
SO
SNXL
SDXL
SNCX
SDCX
SNXY
X
XN
XD
XNXL
XDXL
XNCX
XDC~
XNXY
Type CPU 11806
Load A
Load A. I ncrement Address
Load A. Decrement Address
Load A. Increment Address, Exchange L
Load A, Decrement Address. Exchange L
Load A, Increment Be Compare Address, Exchange
Load A. Decrement Be Compare Address, Exchange
Load A, I ncrement Address, Exchange Y
Store A
Store A. Increment Address
Store A, Decrement Address
Store A, Increment Address. Exchange L
Store A. Decrement Address. Exchange L
Store A. Increment Be Compare Address, Exchange
Store A, Decrement Be Compare Address. Exchange
Store A, Increment Address, Exchange Y
EXChange
Exchange. 'Increment Address
Exchange. Decrement Address
Exchange, Increment Address, Exchange l
Exchange. Decrement Address, Exchange l
Exchange. Increment & Compare Address. Exchange
Exchange, Decrement Be Compare Address. Exchange
Exchange. Increment Address, Exchange Y
Stack Group
Branch
Branch, Dis!lble Interrupts
No Operation
Skip if Carry
Register Group
L
L
L
L
l
l
LX
LY
LZ
LAI
LXI
LVI
LZI
LAL
LXl
LVL
LZL
LXA
LVA
LZA
LLA
XV
XL
XAX
XAV
XAZ
XAL
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
X
V
Z
A Immediate
X Immediate
V Immediate
Z Immediate
A through link
X through link
V through link
Z through link
~oad X from 1>.
Load Y from A
Load Zfrom A
Load L from A
Exchange Y
Exchange L
Exchange A and X
Exchange A and V
Exchange A and Z
Exchange A and L
Subroutine Group
PSHA
PSHX
PSHY
PSHZ
PSHl
POPA
POPX
POPY
POPZ
POPl
Push A
Push X
Push Y
Push Z
Push L
Pop A
Pop X
PopY
PopZ
Pop L
Bl
RT
RSK
RTI
SKNC
SKZ
SKNZ
SKP
SKN
SKE
BBT
BBF
BC
BNC
BZ
BNZ
BP
BN
BNE
Arithmetic Group
A
AC
ASK
ACSK
AISK
INCA
DC
DCC
Add
Add with Carry
Add. Skip on Carry
Add with Carry, Skip on Carry
Add Immediate, Skip on Carry
Increment A
Decimal Correct (1)
Decimal Correct (2)
Branch and Link
Return
Return Be Skip
Return, Enable Interrupts
Skip if No Carry
Skip if Zero
Skip if Non-Zero
Skip if Positive
Skip if Negative
Skif if Equal
Branch if Bit (n) True
Branch if Bit (n) False
Branch if Carry
Branch if No Carry
Branch if Zero
Branch if Non-Zero
Branch if Positive
Branch if Negative
Branch if Not Equal
Input/Output Group
Logical Group
AN
ANI
OR
EOR
COM
Logical
Logical
Logical
Logical
104
IN
OUT
RIS
AND
AND Immediate
OR
Exclusive OR
Bit Manipulation Group
Compl~ment
Increment/Decrement Group
INCX
DECX
INXY
DEXY
INCY
DcCY
Digit I/O (C, D)
Input (C. D)
Output (C,D)
Read Interrupt Status
SC
RC
RAR
RAL
MDR
MDl
SB
Increment X
Decremen, X
'ncremen-:: X, Exchange Y
Decrement X, EXChange Y
'ncrement Y
Decrement Y
RS
4-44
Set Carry
Reset Carry
ROiate ARight
Rotate A Left
Move Digit Right
Move Digit Left
Set Bit (n)
Reset Bit (n)
Part No. 10353
Dual line Driver
This line driver is commonly used to interface data
terminal equipment to data communication equip-
Type 75150P
ment utilizing the E IA Standard RS-232-C. Input is
TTL/DTL compatible, and output is ±12V.
Logic Symbol
Truth Table
+12V
r
1A 2
j~ --,
-
I
17
I
I
I
A
L
X
H
H
L
H
1Y
STB 11
2A 31
:6 2Y
0--
L
OUTPUT
Y
INPUTS
STB
l5--~..J
L
OV
H
+5V
Irrelevant
-x
+12
+12
-12
-12V
Alternate Symbols
+12V
+12V
__ ts_
r
8
21
1
I
1
~
I
L
1,5- ~_I
4
vcc+
STB
1A
1Y
7
2A
2Y
6
GND
VCC-
-12V
5
-12V
Loading:
Inputs
Strobe
1 Unit Load
2 Unit Loads
4-45
Quadruple line Receiver
Part No. 10354
Type 75154
put will remain either low (OV) or high (+5V) as
determined by the previous input. For fail-safe operation, the threshold terminal is left floating. This reduces the hysteresis loop, causing the negative-going
threshold to be above OV. The positive-going threshold is unchanged. In this mode, if the input voltage
goes to OV or is open-circuited, the output goes high
(+5V) regardless of the previous input condition.
vee can be either +5V or +12V. Pin 9 should not be
connected externally.
This receiver satisfies the requirements of the
interface between data communication equipment
and data terminal equipment as defined by EIA Standard RS-232-C. Input is from +25V to -25V, and output is either OV or +5V. For normal operation, the
threshold control terminal is connected to VCC1.
This provides a wide hysteresis loop which is the difference between the positive-going and negative-going
threshold levels. In this mode of operation, if the
input voltage goes to zero (or open-circuit), the out-
Alternate Symbol
Logic Sym bol
VCC1 VCC2
I
1A
..I~5J~ L6
3
I
4:
:13
1Y
2T
3T
4T
2Y
1A
2A
1T--2A
2T---
j
3A
111
3A
~-3Y
4A
GND
3T
4T
A
y
4Y
4A
input
output
threshold
control
+5V
+12V
T
14:
I
I
t_~_1
VCCl
VCC2
Truth Table
(each receiver)
Waveforms
4
INPUT
A
OUTPUT
-12
+12
H (+5)
r---i
3
(0)
'r
~,
Y
L
I
'I
"
2
I
O~~~~T~~~
o-
-25
.T"
FAIL-SAFE •
OPERATIONJ
"
,
-
I,
-
-f,
"
"
,
1-
-4
Loading:
Ol,Jtputs
1Y
2Y
3Y
4Y
10 Unit Loads
4-46
-3
-2
-I
o
2
~,;:::
3
4
25
Voltage Comparator
Part No. 10188
This comparator can be used with
power supplies providing two output
voltages, up to + 15 volts. It can be
used with single-output supplies up
to +5 volts.
Type LM311
Logic Sym bol
- IN
3
~-OUT
+ IN
2
v+ ,
PIN 8
PIN 4
GND, PIN 1
v- ,
(083 -041)
Dual AND-Gate Peripheral Driver
Type 75451
Part No. 10181
Logic Sy mbol
1
1A~1Y
, 8 2
Truth Table
6
2A~2Y
28 7
vee-8,
GND-4
Loading:
Input
Output
1 Unit Load
300 ma
4-47
A
B
y
L
L
H
H
L
H
L
H
L
L
L
H
High-Speed Dual Comparator
Part No. 10168
Type LM319
This device can operate on voltage supplies up to
±15V, but can also operate off of a single +5V
supply, depending upon the application. Note the
non-standard voltage comections.
Logic Sy mbol
+1 N 1
Alternate Symbol
12
-IN f
OUT 1
GNDf
+IN 2 9
-IN2
7
10
OUT 2
GND 2
V+, pin 11
V-, pin 6
Type LM320H-5
Type LM320H-12
Part No. 42155-05
Part No. 42155-12
J. Terminal Negative Voltage Regulator, 5 Volt
3-Terminal Negative Voltage Regulator, 12 Volt
providing current limiting and thermal overload
protecti on.
This series of negative regulators provides precision
regulation of output currents up to .5A, while also
Logic Symbol
Pinout
(Bott"OmView)
OUT
IN
3
2
OUT
GND
GND
Maximum Voltages
I
I
IN
OUT
-05
-7 to-25
-4.8 to -5.2
4-48
-12
-14 to-35
-11.6 to -12.4
IN
Part No. 10284-03
3-Terminal Positive Voltage Regulator, 12 Volt
Type LM340T-12
This series of positive regulators provides precision
regulation of output currents up to 1A, while providing
current limiting and thermal overload protection.
Connection Diagram
Logic Symbol
INVOUT
GND\ r
1'-'\
O
GND
Input
1--_ _--'1
OUT (2)
1--_ _--'1
GN 0 (3)
p
I- n ....,1..oIo-_..J------II IN (1)
= +14.4 to +27.5V
Output.= +11.4 to +12.6V
3- Terminal Positive Voltage Regulator, 12-Volt
Part No. 42154-05
Part No. 42154-12
This series of positive regulators provides precision
regulation of output currents up to .5A. while also
providing current limiting and thermal overload
protection.
3-Terminal Positive Voltage Regulator, 5 Volt
Pinout
(Top View)
Logic Symbol
IN '
~
1.'
2
Type LM341P-5
Type LM341 P-12
0
OUT
] ~
GND
-lZ
Input (1)
Output (2)
+14.8 to +27V
+11.4 to +12.6V
4-49
-5
+7 to +17V
+4.75 to +S.ZSV
2
3
Part No. 10124
Differential Video Amplifier
Type LM733C
Th is d ifferential- i nput/d ifferent ial-output
amplifier provides selectable gains of 10, 100, and
400.
Logic Symbol
Gain Selection
Gain
Connection
10
100
400
None
G1A to G1B
G2A to G2B
G2A G1A
t:" >7
14
IN 1
8
OUT 1
OUT 2
"
~4
IN 2 '
G2B G1B
V+,10
. V-, 5
(No connection to pins 2, 6,9, and 13)
Dual Op Amp, General Purpose
Dual Op Amp, Selected
Part No. 10165
Part No. 13072
Type 72747
Type 72747
Logic Symbol
J
C
13+
+IN
-IN
2
t
+
12
"
-/,4
6
OUT
7
~
to
-/~
~
I,...-
5
3 Nt
N2
VCC4, No Connection -11
Part No. 10166
Op Amp, General Purpose
This single op amp is housed in an 8-pin DIP.
logic Symbol
VCC+
Pin 1 = Offset null/Comp
Pin 5 = Offset null (N2)
Pin 8 = Comp
+IN
3
-IN
2
~7
+
V
4
VCC4-50
6
OUT
Type 72748
Voltage Regulator, -12V
Part No. 13142
Logic Symbol
2
IN
Type M C7 912CB
Pin Out
@
OUT
GND
VIN
Vo
= -14.5
= -11.5
TO -30V
TO -12.5V
(083-039)
4-51
Part No. 13143
Clock Generator
Type 13143
The Clock Generator circuit generates
the "An and "B" clock waveforms required
by circuits in the PPS. The Clock
Generator has an internal oscillator which
is stabilized by connecting a 3.579545 MHz
color TV quartz crystal to the appropriate
inputs. Primary clock A output is a square
wave. Clock B output is a pulse output
occurring during each phase of clock A,
with unique timing features required by the
circuits within the PPS system. Clock A
is also available, through a TTL output, for
synchronizing equipment external to PPS.
The input straps provide a countdown of the
oscillator frequency equal to the number
associated with the strap; ie, S12 divides by
12, E14 divides by 14, and S18 divides by 18.
Thus, with a crystal frequency of approximately 3.58 MHz and input S14 terminated to
VDD , the clock A output frequency is 256 kHz,
(3.58 MHz -:- 14 =256 kHz).
Logic Symbol
Bottom View
r---,
I XTAL I
J
L
2
10
ClKS 4
ATTL
CLKA 1
518514512
7 8 9
VOO -
PIN 6
FREQUENCY
VS5 -
PIN 5 (GND)
SELECT STRAPS - PINS 7,8,9
(083-036)
4-52
NPN Transistor Array
Part No. 42191-32
This device consists of five
general-purpose silicon NPN
transistors on a common monolithic substrate. Two of the
transistors are internally
connected to form a differentially-connected pair.
Type CA3086
Logic Symbol
~
~
4
2
4(
~
12
''\
13
(083-040)
Quad Field Effect Transistor (FET)
This
FETs.
Ie
contains four
Part No. 10190
Type 8041
independent p-channel
Logic Symbol
3
,,
6
2
4-53
14
Parallel Data Controller
Part No. 13159
The Parallel Data Controller (PDC), is
a flexible parallel input/output device
for interfacing the PPS-S system to
external devices or for interfacing between
multiple PPS systems. The device provides
two independent, bi-directional input/
output channels, each of which operates in
a variety of parallel data transfer modes.
Each channel consists of ten TTL-compatible lines; eight data lines and two
control lines (DAI through DAB, CAl
and CA2; DBl through DBS, CBl and CB2).
Each channel has its own data buffer
(eight bits) and function register (eight
bits); the two channels share a common
device status register (5 bits) and an
interrupt status register (4 bits.)
The function (mode) of each channel
is program mabIe and is selected by
control data loaded into the associated
function register under CPU program
control. Direct addressing for up to 15
PDCs is possible by the use of four chip
select address straps (ASl through AS4)
that can be user-terminated to create
each device address. Address 0000 is
reserved for the "all call" command, Read
Interrupt Status (RIS).
Type 10453
Logic
DATA
CHANNEL A
8
CA2
9 CAl
10
DAl
11
DA2
DA3
DA4
DA5
DA6
DA7
DA8
25
INSTRUCTIONI
DATA BUS
24
23
22
21
20
19
18
29
28
27
26
4
VDD- 38
VSS- 39
4-54
S~mbol
CB2
CB1
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
2
31
30
32
33
37
34
36
35
DATA
CHANNEL
1/01
I/D2
I/D3
I/D4
1105
1106
I/D7
liDS
AS1
AS2.
AS3
AS4
ACK1
SPO
DMA
ACK¢ 3
INT2 5
(083 - 044
Type 1408L-6
Digital-to-Analog Converter
Part No. 13060
This eight-bit multiplying D-to-A converter
provides a current output which is the product of a
digital word (applied to the A l-A8 inputs) and an
analog reference voltage (applied to the VR + and VRinputs). Digital
inputs are TTL and CMOS
compatible. Output voltage swing is +0.5V to -0.6V
with the Range Control (pin 1) grounded; leaving
pin 1 open enables the negative voltage swi ng to reach
-5V when maximum power supply voltages are
applied. Frequency compensation capacitors are
connected to pin 16. Note the non-standard VCC and
GND connections.
Logic Symbol
MSB
5
6
7
8
Alternate Symbol
12
A2
A3
A4
A5
OUT
4
4
15
A6
A7
LSB 12 A8
NOTE:
2
VCC-13, GND-2
VCC
VEE
+5V
-5V to -15V (cu trent source)
VRVR+
-15V (max.)
+5V (max.)
Loading:
Inputs (digital)
Output
1 Unit Load
2.0 rna.
4-55
Resistor Network, 1K x 15
Resistor Network. 1K x 13
Part No. 10239-01
Pinout
Pinout
16
15
14
13
12
11
10
9
2
3
4
5
6
7
8
Resistor Network. Quad 10K x 2
14
13
12
1t
10
9
8
2
3
4
5
6
7
Resistor Network. 15K X 13
Part No. 13044
2
7
3
8 ------...,
9
Part No.1314 0
Pinout
Pinout
1-....--
Part No. 10761
14
13
12
tt
10
9
8
,
2
3
4
5
6
7
5
6
14 ___~. . J
10
12
13
(Pins 4 and 11. no connection)
4-56
2048-Bit (256 x 8-Bit) RAM
Type 10809
Part No. 13158
The Random Access Memory (RAM)
is a 2048 bit RAM organized in
256 x 8-bit configuration. It is
designed for compatibility with
the PPS-8 system, and the A and
B system clocks. It is a dynamic
memory with automatic refresh logic
and a 1.8 IlS access time. It is intended
to be used as a read/write data storage
device for the PPS-8 system.
Logic
8
A/B1
A/B2
S~mbol
1/01
A/B3
A/B4
1103
A/B5
1/04
A/B6
1105
1102
A/B7
1106
A/B8
1/07
1108
16
17
18
23
AS1
AS2
AS3
AS4
ASS
AS6
AS7
SC1
SC2
SC3
SC4
SC5
SC6
SC7
RIH
WIIO
ClK A
ClK
VOO- 25
Vss-14
4-57
B
083-045
MOS 256 x 4-Bit Static RAM, 3-State
Type 2111 A-4
Part No. 42334-11
This is the 450 ns member of a family of
random-access memories avail able in several speed
ranges_ The Output Disable pin (9), when high, drives
the Input/Output pins to their high-impedance state_
Logic Symbol
+5V
4 Art>
3 A1
A6
A7
00
eEl
eE2
R/W
Timing Waveforms
(All times are minimum unless noted)
Write Cycle
Read Cycle
450 ns
400 ns
ADDRESS
CHIP
CHIP
ENABLES
f CE 2)
ENABLES
OUTPUT
DISABLE
OUTPUT
DISABLE
~CE
DATA OUT
VALID
DATA I/O
DATA
DATA IN
STABLE
I/O
l
READ/
WRITE
Loading:
Outputs
1.25 Unit Loads
4-58
20
n.
250 ns
512 x 8-Bit Programmable Read Only Memory, Three-State
Part No. 10406
These devices are Programmable Read-Only
memories which are normally programmed by the
vendor. No truth table appears here because each
program requires a separate table. Note that the part
number above is the Diablo number for the
unprogrammed pROMs: a new number is assigned
when the pROM is programmed. Part numbers for
programmed pROMs appear on the schematic. Access
time is typically 35 ns (60 ns maximum).
In the LATCHED READ mode, outputs are held
in their previous state (1, 0, or Hi-Z) as long as Strobe
is low, regardless of the state of address or chip
enable. A positive Strobe transition causes data from
the applied address to reach the outputs if the chip is
ena bled, and causes outputs to go to the H i-Z state if
the chi p is disabled.
Type 82S115
A negative Strobe transition causes outputs to be
locked into their last Read Data condition if the chip
was enabled, or causes outputs to be locked into the
Hi-Z condition if the chip was disabled.
There are two modes of operation. In the
TRANSPAR ENT READ mode, stored data is
addressed by applying a binary code to the address
inputs while holding Strobe high. In this mode the bit
drivers are controlled solely by CE 1 and CE2 lines.
Waveforms
(Times shown are maximum unless noted)
(Times shown are in nanoseconds)
Logic Symbol
A0
A1
A2
A3
A4
A5
A6
A7
A8
FE1
FE2
01
7
ST,!~!~
,
+3.0
,_____________________________
ov
, - - - - --- ------------------+3.0V
USV
a
02
03 9
04
05
06
07
08
~---------------------------OV
CE
-----+3.0V
CHIP ENABLE
'------ov
CE 2
STR
CE1
CE2
Latched Read
,-------------- .....
, - - - - - - - - - - - - ~ 3.0V
1.5V
VCC-24, GND-12
_------+3.0V
CHIP ENABLE
CE
ArJ-A8
FE1, FE2
STR
CE1, CE2
01-08
Address Inputs
Programming Inputs
Strobe Input
Chip Enable Inputs
Data Outputs
STROBE
ov
""OH
90
Loading:
Inputs
Outputs
2
.1 Unit Load
6 Unit Loads
4-59
MOS 2K x 8 Masked ROM
Type 8316
This is a Read-Only Memory that is programmed
during manufacture. No part number is given because
each program requires a separate part number. Part
numbers are given on the schematics. Outputs are
3-state, controlled by three programmable chip-select
inputs. Any combination of high- or low-active chip
select inputs can be defined, and the desired chip
select code is programmed into the chip during manufacture. Maximum access time is 1.5 J,.LS. Only a single
power supply voltage (+5V) is required.
Logic Symbol
A'
AI
01
02
A2
A3
A4
05
A5
A6
07
A7
08
A8
A9
AIO
CSt
CS2
CS3
VCC-24, GND-12
Waveforms ,
(All times shown are maximum)
ADDRESS
500 ns
500 ns
PROGRAMMABLE
CHIP SELECTS
5S TIME
,
1.5 ps
VO H
DATA OUTPUT
OUTPUT VALID
VOL
Loading:
Outputs
1.1 Unit Loads
4-60
MOS 1024 x 8-Bit Electrically-Alterable ROM
Part No. 42329
This Read-Only Memory is programmed at the
Diablo factory. It has a transparent quartz lid which
allows exposure to ultraviolet light to erase the bit
pattern. It is electrically compatible with the type
8308 ROM. Access time is 450 ns. Outputs are
3-state, controlled by the Chip Select (eS) input.
Type 8708
Logic Symbol
+5V
+12V
24
8
vee
A~
A1
A2
A3
VBB = +5V
= +5V
VDD = +12V
VSS = GND
A4
vce
A5
A6
A7
08
AS
A9
PRGM
CSjWE
VSS
12
-5V
Waveforms
(All times shown are maximum)
ADDRESS
120ns
120ns
CS/WE
ACCESS TIME
450n5
VOH - - - - - - - - - - - DATA OUTPUT
1,..-----------, -
OUTPUT HIGH IMPEDANCE
V-OL - - - - - - - - - - - - - - - - - - - - - - Loading:
Outputs
1 Un it Load
4-61
OUTPUT VALID
-
-
- -
-
-
OUTPUT HIGH
IMPEDANCE
1'-------------' - - - - - - --
4.6
ASCII CODE CHART
The ASCII code chart is reproduced in Figure 4-2.
4.7
SCHEMATICS AND LOGIC DRAWINGS
Figure 4-3 explains the meaning of the various notations contained on the logic drawings
and schematics. For more information on component locations, connector pin numbers,
cables, etc., see Section 3.S.
Table 4-2 lists the schematics and logic drawings provided in the remaining pages of this
manual.
Table 4-2. Schematic and Logic Drawing Index
Description
Drawing No.
23924:-99
23926-XX
24930-01
24620-XX
2462S-XX
4052S-XX
2460S-XX
2493S-01
4000S6-01
400089-01
400097-01
400062-XX
400094-01
400285-01
24500-XX
HPR03 Board (Terminal Processor)
XMEM1 Board
MXI Board (Matrix Interface)
PROCESSOR Board (Printer)
CAR SERVO Board
CAR PWR AMP Board
HAMMER DRIVER Board
Motherboard
Con trol Panel
Interconnection Diagram
Power Distribution
Power Supply (115/230 Vac)
Keyboard (Cortron)
Keyboard (Micro Switch)
Interconnection Diagram, Printer Cables
4-62
o
o
o
o
0 0 0
0
NUL DLE
0 0 1
1
SOH DCI
0 1i0
2
STX DC2
u
0 1I1
3
ETX DC3
:ii:
o 1 0 0
o 1I 0 11
4
5
6
SP
I
I
I· •
I· .1
()
:1.
:::.:'~
1:·: F;.: .I:)
:::::;
1.·.·
• ••
EDT DC4
·:1:. i ..:l
'1.· ·.1
•
ENQ NAK
:.:.:.
I
------+---+-I----+-!~-~---+---+-
o
1: 1 0
I
ACK SYN i •••
I
;:.:••'
~O~I~--+---+----I~--+----+T-..
1 1 1 7 BEL
1 0 0 0 8 BS
1 0 I 0 1 9 HT
1 0 1,I 0 10 LF
I
I
ETB!
.
CAN
.
I
Ii
!
I
i
!
EM
j'
I
i...
·1.'·
••• !
•
...
.1.
!...
I ••:.
!
.:::
-..i i~
i ·•• .:
r:·
i.....
1.:.1
I":..
::::a
li··1
...... I..'. .
........
i i.. )
,.
--t ... : .... ~.:-. I I
, .. ',
1 :;-: .:.:.:.
I
I·····
••• +-~--.-.=--
I
~~---t--+---+---I~--+-----t----+---+------+ii:
.::::
i _:._:.:.;--+--_1"_._._ I I I
•••: . .
I
r·
•...··1·!
•
~~~I--+i~~-+---+---+---+ - - + - - -
I
:
I
II
i
i
i
·1··:·
:•••..:
("I"
...
Ii i....)
I
I
!
T! . .(
:.1..
~.:J
~-~--~-~--~~~
I
SUB
.:.!I.:.'!
ESC
..:.'.
I
I
••••
.:.:..
•••••
••
·1.1
•• :••
I..
•••
I·::
.:::
.....
,].
I
.1 ••
~~~-+---+---I~--+----+-----+-'- --t-----+-----~_=____il----___
1 I 0 i 1 I 1 11
I
!
I
VT
1 1 I 0 0 12 FF FS
I
T
.'
I
.1
!.::::
,.....
I...
i
I
:
~~i~+--r~--~r-~--4---~--4-----·+---~-~--~
1 1 I 0 ,1 13
i
1 1 I 1 0 14
1
··1 Pi ....:.
so RS
i····.!!·· '. ·:·'1
-1--=-----1.---.-.·--+----+---+-1--.
CR GS
.•.•
1
::::
I
•••:.
j.....j i
I·. '.
'
-+-_ _.....
1 11 1 1 15
51
us
I
../
i ·7
:::)
DEL
All characters in these two columns an SP(Space) are
non-printing. Del(Delete) does not print in the remote
mode,but prints logical NOT symbol~) when entered on
keyboard in local mode. (Logical NOT is also printed
in place of characters received with parity or framing
error.
Figure 4-2. ASCII Code Chart
4-63
*THS
COOfONATE OF SIGNAL OUTPUT ON
LOGIC DRAWING (St£ET 4)
ABSENCE OF COf\tECTOR SYt.eOL INJICATES
SIGNAL SOURCE IS THS BOARD
* COORDINATES a:a:SIGNAL If'FUTS ON
OTl£R St£ETS
COtIECTOR DENTFIER wt£N
BOARD HAS MORE THAN
ON: CONECTOR
THS DRAWING
* COOAOINA
TE MARKINGS
FOR LOCATING SIGNALS
REFERENCED ON ANOTl-ER
~T
+ IIIIlICATES ACTIVE HGH
SPECIAL NOTES
CBERAL NOTES
-
IlENTlCAL COMPONENTS
MOUNTED AT SEVERAL
LOCATIONS ON
THS BOARD
DRAWING NO. (SAME
AS CIRCUIT BOARD
ASSY NOJ
TOTAL NO. OF SHEETS FOR THIS
CIRCUT BOARD ONCLlDES ASSY
DRAWING & RELATED DRAWINGS!
Figure 4-3· Logic Drawing Notation
REVISION HISTORY - #23924-XX HPR03 Board
Rev.
A ECO#
7648
As released.
B
7690
Change resistor F24 from 1K to 8.2K; add resistor F25 from
-OPTION D to +5V.
C
7759
Correct error on bill of material (diode A28 omitted); add "on"
indication to 81-S4 on sheet 3 of schematic; correct note 5 on
sheet 1 of schematic -specified "B7," should be "B11." No
changes to board.
D
7771
Replace 74L8221 at A26 with 74L8123. Change resistor (832)
and capacitor (A29), and remove diode (A28). Provides more
stable real-time clock.
E
7816
Allow use of plastic ICs, no schematic changes.
13
15
16
17
11
12
7
8
5
6
4
23924-99
P1
SH1-D7
- WRIT E
WRITE
~;
. .--~-~~~=-------------------------------------------------~~-------------------------------------------------------------------------------1~----------------------------------------~~~~39
-
READ
L
- READ
SH1-D7 ~~
. .----~~~--------------------------------------------------------_t~~----~------------------------------------------------------------------------------i-~--------------------------------------------~~=-~37
+ RST
9
....... 8
- RST
_
SHI-87 - .~~~~~~---------------------------------------------------------t~--.--------------------------------------------------------~ruu/-~-------------------.~~+----------------------------------------------------~_~SH4-E16
.
r -____________________________________. -_________________7_4_L_S~_4
__________________1_~_+------______________________________~+~K~Y~B~D=_~I~N~T~R~_~-~SH4-C'6
K
4
P2
, 826
, lK
CI-S____.....
2 0 P
0 ff
12~~+~K~Y~S~T~B------~------------------------------------------_+~r_t_+_------~~----------~3i>CLK
+ 5V
!R1
126
+ 5V
+5V
i'16
•
J
f - - - - - - -- -- - - - - - - - - - - - - - - - - - - - - - ~
I
•
•
•
? c , "~
~:
:L_~_
~ >
.....!..!
~
5
pe4
vee
RS r
~~~ ~
RO
PC3
16~---~D~A~TA~I~---~----~_+~--r_+_;__r-t_t~r_t_+_;__r-------~3,PAI
1
&
5
PC5~
>
>'
» ' lK.
H
WR
13 14 15 ,- 2 :5 4 1 '0 9-' 8-';' 6" 5 - ~
13 }-_-~D~AT.:..::A~0~_ _+ _ - -........
12_+_+++_+__+__+_+_+_+_+_+_t_t_------...:..;4 PA¢J
:
174LS7~ 2~cr-
~
PC6~1...:..1------'-<'()~'0 4 74LS32
74Ls1l4
+5V
~
rio
INTFC
I
ill
j
iL ~·~"cu""
Sus
18~---~D~A~TA~2~---~-----------*~--~+-4_~~_+~~t_+_;__r-------~2,PA2
H
20~---~O~A~T~A~3~----~------------~~r_+_;__r_r_t~~t_+_;__r--------------~1,AA3
2
PC 7 1_'1c;:0'------------------------------------"-1
B
1
-
H
~
Q
~
pAm
19~----~O~A~T~A-4~----~--------------~~+_;__r_r_t~r_t_+_i__r---------------4~O,P~4
OS
4LS~1_'4'------------------_+~~+_----------------------------------'--+'--R~T~C~L~K'--~IN~T'--R__~~~SH4-B'6
-,~
:3
:- - - 852 - - i
'i'...74LS367
15~----~O~A~T~A~6~----~--------------------~~~_+~~t_+_i__r--------------~3~8,PA&
G
~I.........
2.
+ SV
MODE,
14.
7~----~F~K~Y~1------_+------------------------~+_~~-t_t-f--------------~1~8 PB~
(IS):
8~----~F~K~Y~2~----~~--------------------------+-~_t_+~--r_------------~'~9,PB1
>rn.! F23 >E74:
•
10~----~F~K~Y~3~----------------------------------~~_+_+~--r_------------~2~O,PB2
O¢
5~----~F~K~Y-4~--------------------------------------~_+~--t_~--------------~Z~' PB3
01
6 ~----~F~K~Y~5~----------------------------__----------~;_~_+--------------~2~Z~PB4
.... ---F27 ---1
4
E
54""",""
r-;-<.r
~53
/'I..
I
ill
•
__
'"'
825S
0
23
52 __
V ONI
:7
- OPTlON B
24
PBS
51 __
:8
- OPTION A
25
PB7
~ ~ __ ~~NJ
D
OPTION
'""ONI
~
,
:6
-
- OPTION C
~
2
:5
~ ONI
J2
11
G
-WR
3
-----r~~~---:~-------------------------------------4 ~
..:.••__~~~~~------4-------------------------~r-+-;--+-1~r-+---------------~'PCZ
+ SYNC
16
SHI-87 ~~
F
- RD
I
15
:~i
I "'-...
•
14~----~D~A-T~A~7------~----------------------~~t-;_-I-'_f--~t_~----------------3_17 P~7
.
J
P2
~6-----------------------++~----------------------~+~B~U~S~Y~9
8.2K
8.2K
8.21(
067:
8.2K
~
8.2K
34
)070
8.2K
069
0&8
8.2K
8.2K
(1):
~
~~~_T:l~3---------------------------------C~L~R--~ 1
L-
GND
'----~"""T_."..7- - - '
I
I(
L------------------------------------------------------r-+~r_+_~_t~--t_--------~~----------------------________________________________________-__O~P~T~I~0~N~~D__~~~SH4-GI6
c
SH1-E7
~_. .-~+~D~A~0~--------------------------------------------------------____- J
:. + DAI
+ DA2
...
SH1-E7 ~.....--~~~--------------------------------------------------------------------------------------------------~
SH1-E7
SH1-E7
SH1-E7
SH1-E7
•
SH1-07
SH1-07
.
I
:. .-+~~D~A~3~---------------------------------------------------~
~-~;~~+~~DA~4~------------------------------------------------------------------------------------------~
:--tSCHEMATiC DIAGRAM
~ ?~~~!~~!~~
~.~~+~~DA~5~---------------------------------------------------------------------------------------------~
.
~
~.~--+~~D~A6~--------------------------------------------------------------------------------------------~
.
~~~~+~~D~A~7--------------------------------------------------------------------------------------------------~
PW
"'''a'''
23924-99
DC" CTL ~i,j!·lo.n
17
c
TtiRU
4
Incorporated
ASSY, HP R03
H'( iE~M
15
13
12
11
10
9
8
7
6
..
5
J2
+ADDRI
+ADDR
®
L
(i1 14
+~
..1..2S
II
~.-~~~~
______________________________
~.-
__________
~
__________________________________________________________________
CS
~~~12~
,
+SV
-I--~~~~------------------------------------_r+_------------_t----~------------~~--------------------__~----------------------------j_---2~0~~K
.
+t
---?
----.§..
26
VCC
,,~
"I
K
IK
~CTS
PC0 ~
LOAD
PCI ~
~~CLK
PC2 ~
ENP
15
CARP'PC3 ~ B2~~ENT
MODE¢
-4
CNTR 13
31
I
It
r.;:;-
IV.g...
2Y
75154 3Yt-'I~1- - - - ,
4Y.!2--
E.--
+12V
--~-fBlS
7515iZ1P i
10
P8~ 18
I
I
I
21
I
/\
5 B E26 Q.S~
9
...J.g, D P Q~
~ B30
PSI 19
1=---------=S=-iIC
Q.C ~
LOAD
2
D FF
PS2 20
~-------'3'=i~74LS161~~~
4~CLK
A37
D"3____I;.;.I~C~K
'i -21
PB3
f=-----"""l
C
~O ENP CAR L"I5~__.......!.13~,~t':::"..!)I.:y-!:12'-4_...!1\4
~ ~~fll
:2 ~~
}--~~~~~--------~:2A
75154 3'( ~
GHD
~~~~~~~--------------
4'( F-
39
5
~IL~R
C
-B12
)(
-
Dill 34
270iZl
28
01 33
01
32
02 ~-------------+--4--~~------------------------------------------------------r_--------_11
02
31
03 ~-------------+--_4--~+_~--------------.--------------------------------------r_--------~2,03
30
04 ~------------~--~~_+_4~._---------------------------------------------+_-------~S04
2 P"2
3 P"I
4
P"1i
i.,f"
+DATA TERMINAL READY
RTS
I
I
I
-
I
,-; __ 1
I
I
I
I
I
I
~
8__
75ISi2l"P1
31
23
3
r
I
+12V
SYNDETr!§.
16
j
+ REQUEST TO SEND
I
I
17
I
I
I
I
21
1'0
TXO~I~9--------------~--<7
I
L
4
I
1
I
H
I
I
I
II
J
I
I
17
I
1"0
2
I
I
-12V
:~
Ji!Q
I P"3
~--+-~-1
~
~I
E5
OPTION I
L15--~-J
TxC
r)i.!!
""7
+
I
I
'I;Ti3--
1 ~~
JI
I
16
J
-XMIT DATA
:
5
G
J5--~-J
-12V
05 ~-------------+--_4--~+__r_4~._----------------------------------------------r_--------~605
29
28
06 ~---------
-~-~r_~+_~-+_4~._------------------------_i-----7~06
27
07 ~------------+_-+_~_+~-~+_~~---------------~------------+_-----~807
8251
8255
F
SH1 - B7
SH1 - H7
SH 1 - D7
SH1 - D7
---.
..--.
----
+ RST
35 RST
PC4
-PORT I
6
CS
PCS 12
5
RO
PC6 II
WR
PC7 10
-READ
-WRITE
36
13
13
RO
10
WR
~RST
F
RxRDY~
TxRDY~
GNO
~7
E
E
SH3 - L3
SH1 - E7
D
SH1 - E7
SH1 - E7
SH1 - E7
SH1 - E7
SH1 - E7
SH1 - D7
SH1 - D7
c
SH3-)<3
SH3 - 63
•
-..
..-..-..
--...
.-
.-...
-..
-..
-
RST
1
1
+DAI
D
+DA2
+DA3
+DA4
+DA5
+DA6
+DA7
+ KYBD INTR
......!...
2
~
B22~
5
B22~
13
+RTCLK INTR
PI
®
"-
+DA0 '
-
XINTR
12
B27
..,....6
74lS54 ,..,
I..,
7
13
AE 32
+5V
,
.
-t
SCHEMATIC OIA;,;;G.;,;RAM;..;;..;_ _ _ _
~~:~~--
~
IK
___________________________________________________________________________________________________________- - - -____________~------~3~D3
4
TITL,(
PW ASSY J HPR03
74L5~4
MOOUCT NO
23924-99
c
1\
+INTR ..
)..!-!.-----------.:.....:..;.:....;..;..:-._~
. . SH 1-17
I
THR
4
!
II
......._
23926-XX
14
15
16
17
t
13
~
+~~A~a
. -_________________________________~-------------------------------~----------------------------------__________+~A~7___~~SH2-J16,SH3-DI7
r--------------------jf-.-----------------+.--------------------------.-:+~A:..::6~_I~
. . SHl-KI6,SH3-D17
r---------------------------jH-~--------------------+_I~--------------------------------_+~A::.:5~_~
~SH2- K16, SH3 - 017
+
A4
r-------------------------------_t1_~~----------------------------4_~~------------------------------------------~~~--~~~SH2-KI6,SH3-D17
K
,------------------------++-iH-~-----------------------+++_I~-------------------------------------+~A::.:3~_~
=SH2 - K16, SH3 - 017
r-------------------------+++-l-+-.----------------------If-+++-i-+-------------------------~+--.:..:A:..::2~_~~SH2 - K16, SH3 - 017
35~+--A-D-D-R~~--------~
23926-XX
~-D2
L
NOTES: UNLESS OTHERWISE SPECIFIED,
1. ALL RESISTANCES SPECIFIED IN OHMS •
2. ALL RESISTOFtS ARE 1/4 WATT.
5
± %.
3. ALL CAPACITANCE
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REVISION HISTORY -#23926-XX XMEMI Board
Rev.
A ECO#
7646
As released.
B
7852
Add dash numbers for 1641, 1660. No schematic changes.
C
7933
PWA MEMI bill of materials and ROM changes.
D
7953
PWA MEMI establish -98, -99. Change bill of material
include -98 - authorize 04 etch for custom ROM.
E
A4092
to
Authorized Purchasing to buy other than plastic packaged Ie's
if there was a shortage.
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MATRIX INTERFACE
C4,C38,C64,03,037,D73
24930-01
REV. A
083-020
REVISION HISTORY - #24930-01 MATRIX INTERFACE
REV. A Eeo#
A1902
As released.
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24620-12.-13
REV. H
083 -021
REVISION HISTORY -# 24620-12, -13 PROCESSOR Board
REV.
ECO#
ETCH
CONFIGURA TION
A
A1429
01
Standard -01 configuration bill of material, assembly, and
schematic as released.
B
A1464
01
Documentation change only.
C
A1539
01
Eliminate PROM PCB, add ROM's. to this assembly
(A24=13206-01/A39=13206-12)
D
A1828
01
Add ROM descriptions
(13206-01 = A52GOPA 13206-12 = A52GIPB)
E
A1902
01
Change drawing to -XX, add -11 (systems) configuration.
F
A3106
01
Documentation change only
G
A3127
02
Add -02, -05, and -12 configurations. Allow use of -02 etch.
Remove switch A74 and ground terminal B70. Add -12V (Vss) to
ROM pins 12 and 40. Add connector J17 in upper left hand
corner for additional ROM PCB interconnect. Include ROMs
with bi-directional printing program.
H
A3610
02
Add -13 configuration. Allow program change to accept multiple
font option.
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+511
14",~gll)"""'.
f: ~6
4
10 I
~~'
"OpF".K
·Y..
~~.
rr.T
I
.1
GND :
-+SVF
AI....
IK
9101f1'
...r--'
+15VS
DEMODULATOR
WIDE BAND VIDEO AMPLIFIERS
20.
+i:30
12K
Z Ele } : S : - - - - - - - - - - - - - {
•
51 -INHIBIT (RIBBON JAM)
[57
7.5 K
(NOT USEID 11Q~--------------------------------------------------------------------------------------------------------------------------~
(NOT USED) 26 V
CAR SERVO
24625-02
REV. 0
083-022
REVISION HISTORy-it 24625-02 CARRIAGE SERVO Board
REV. ECO#
ETCH
CONFIGURA TION
A
A1738
03
Release -02 configuration, and allow use of -03 etch. Include
Ribbon Motion Sensor circuits.
B
A1871
03
Add low offset Op-Amp (selected 747C) at A39 to reduce speed
variation in reverse carriage motion.
C
A1870
03
Change transistor FlO from type 2N5322L to type 2N5322.
D
A1891
03
Documentation changes only.
873
tOt
CARRfA6E POWER AMFf..IF1ER
874
100
871
I·I
B!5O
56~
847
5E~ ~~----------------------------------------------------------------------------------------~~~--r-1r.::----~
5.11<
ERROR
846
i~
851
F72
+150
101<
G72
E63
G71
854
5111<
A62
II<
853
100
C75
~-'-+--~~~--------------r---------~------~>-
21<
r------------.,
A63
:
.0047
~~~-, 10K.:
13
CARRIAGE
ORNE MOTOR
-150
E77
-150
E76
875
~--._--+_--~~~~Mr~------------------------~~
~ 8~--------------------------------------------------------------------------------1
F47
POWER MONtroR CKT
+155
r
82
.1
+511
A26
21<
85
5V
All
II<
AI2
-'44
+155
B44
IK
A9
II<
+511
86
+155
470
B9
88
L-__________________________________________________________________________________________________________
--------------------------------------~18
+PW
SERVO ENABLE
87
1111
~-------------------------------------------------------------------------------------------------------------------------------------------i16 +POWEft ON
+~ A 4~----------------------------------------------------------------_1--~_r----~~~·
Cit
G37
IW'ER FEED DRIVE A
.1A2W
-15110
~--@----"·~~~---1
...E-3-7---o0 -150
+15VO
~
~
Fu..
5011
~ -~~-_~...~
.........--+!
...=-~-oO+I50
.In2W
PAPER FEED #1
"5- 3t#'
+1632 0 +15115
UuF
3IjVTANT
~------------_.~~--O+!511
ANALOG GNO
0-
:)--....:IIo:r;;--;----o -15 liS
4}-----------.......:::;:.:...::=:.:..-----------'-----------....;..;:..--..,
G26
I
PAPER FEED DISABLE
DRIVElt RETURN
G24
I
+PFB 10~------------------------------------------------------------------------------+-,_--~~_tH
IMPER FEED DRIVE B
E20
-150
PAPER FEED #2
CAR PWR AMP 40525-07
REV. A
083,-on
REVISION HISTORY -#40525-07 CARRIAGE POWER AMPLIFIER Board
REV. ECO#
ETCH
CONFIGURATION
N
A1260
05
As released for use in the Series 2300 Matrix Printer.
P
A1260A
05
Documentation error
Q
A1565
05
Documentation error.
A
A3128
06
-05 to -06 configuration. Allow use of -07 etch. PCB relayout
only. Change component locator codes as follows:
C57 to A44
C54 to B46
C55 to B47
C56 to B44
C54 to A45
DS6 to A47
A
A3278
07
-os
to -07 configuration, -06 to -08 configuration. Reduce
sensitivity to power supply variations. Remove D74. Replace
D73 with a jumper. Change zener diodes A7 and B7 to 11 volt
devices. Change resistor values:· D75 to S.IK and B33 to 30K.
.,,
.~ 47n
....--
'~
~
..
104
r-.l
~M
"l:
tOA
*
'0
AI'
4roo.
+ 48
V (FUSED)
~
~
~t:..
• levI
G.
GZ2
31.
101<
_
I
_. G21
'zn:
.
0
-I!!VD
-H_ERI2 DATA
-HAMMERI 3 DATA
- H_ER ... 4 DATA
H_MER ... 5DATA
- HIMIIER... 6 DATA
HA_R# 7DATA
_ER#8DATA
.2I!lA
510&
31
~
*I~I
el&6
4
_ A3':c.
CU
CZT
~
j"' .:.~
* !
?
Ftl
~
C38
~
16'
~
~
*
~
COO
HI
=~DIIIVI
Mil.
•
~
F48
.40
470...
-.SO
,.
0"
P'
0"
2 TV
~
-"5
""
ro"-o....
':M
.'5f
"65
470A
... ".
~
~
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.
C13
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~
_~)
?
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U
.,9
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lOk
G2
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•
..
0
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:;
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:;,~
C~
CAl!
!I
J2'
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~:.
05
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i'·
:-r ±~"
+I,\I'S
53.0.
AI'''
680A. FI
+~)~.
~OV
~H
I,F
~
._;}
+POWER ON
470.0.
ilI2
2 F34
A2T
470A
.\31,
I
127
AI~
50 ...
820.0.
[51
"
C'O
UD
+I!JVO +I&VO
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!1
8 n4
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.OOA
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D
,
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A
014........ ____ /
I
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4?OA+~~
~ HAMNER COIL *' I
~
/
032
@
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H~COll*2
~~
47
la
C45
18
19 HAMMER DOll
*
3
2
8"9 ' _ , ~
"'"
9
10 HAIAIER COll_ 4
II
870
CTI
'4
/
C70
51 HAMMER COIl# 5
~
HAMMER CClL#6
~
HAMMER COL# 7
~
I
100A
~
410A
~
~
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)
la
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~
,
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1.0.
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C",
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ca
835
C401
21
2 HAMMER COIUl'e
Def
'52
SI(
C£!'o
C12
,
r;'.::,
.M
A
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4
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GNO
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+15VD
GX0
::
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(YYY"\
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27J11f
HAMMER DRIVER
I~F,50V
-
117
I
~mL
12211'
14
15
C 19
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13
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9
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o +t5YD
142 154 i72
I
I
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TlO ~
48VRET
24605-03
REV. C
083-024
REVISION HISTORY -# 24605-03 HAMMER DRIVER Board
REV. ECO#
ETCH
CONFIGURATION
A
A1426
02
-02 configuration bill of material. Assembly, and schematic as
released.
B
A1532
02
Documentation change only.
C
A1575
02
Parts standardization.
Change transistor types: TIP32 to
TIP32A, 2N3644 to PN3644.
D
A1817
02
Change types but not values of capacitors for automatic
insertion.
A
A1896
04
-02 to -03 configuration. Allow use of -04 etch. New layout only,
no circuit changes.
B
A1975
04
Document change only.
C
A3539
04
Hardware change only. See Parts Catalog.
9
+OA II
• T2
SPARE
GNO
11
9
121--2+-,0'-!A:.....!...1- - - - _ _ _ 1
1I1---.:!+~0!..!A~2_ _ _ _---1
131--.;L..O+0'-!A"--'<.3--------.
8
t OA 4
10
tOA5
14
+OA6
16
tOA 7
~~-----~W~HB~T~M(R~IB~B~O~N~J~A~M~)----------------------------------------------------~rs5~1--------~46~~
15.~-----~t~CA=R~~~~A~---------------------------------------------------------_453
8
II
14
16
44
23
21
25
>-
l
«
37
39
CD
52 1-__--"SY~STE~M!....C~L~O~C~K_ ___1 54
>(/)
18
«
(,)
0~
5I-
~
rt)
0
o0:
4~U
0I
0=
IF
t5V
::t=1
X
.......
o
41
51
- SELECT PRINTER
---o
H
W
FOE
READ
- WRITE
23
24
II--
0
J2
26
o-....L--r---~:
~~
~!
+I5VS
I5VS
~
55~
(,)
~
W
~
~
29
30
31
32
33
34
T8./
h-<"
- COVER OPEN
I~ (-
-1
T9
~"
I~ ~
L_-.l
"='
- PAPER OUT
28
+0 7
+06
t05
t04
+03
to 2
191-----cV!:'E~LO~C=IT~Y~47_:D:_:A=iTA:'__--------------------___I19
71---V.:..E=.!L~0~C~IT...!Y~5~D~A~~~-----------__I7
91---V!..E~L~OC~ITC.!Y-26~O~/IJ.~A~------------___I9
~
32
33
34
1I1-__V~EL~OC~ITY~.!.7..!D::::A~:rA=___ _ _ _ _ _ _ _ _ _ _ ____I1i
501----..!+~SE~R'-!.V~0...!DI~SA=B:!:L!:.E___________________I20
50
:
~~
43
49
45
~
18
:!
tOATA
-DATA
-BELL
-BUSY
STROBE
ACKNOWLEDGE
(TIME OUT)
RESET
:~~~RE:ET
{
~~~~
~
(REF)
(CHECK):4
-DOUBLE LWE FEED
+CAR POS INT I
+AUTO LINE FEED
=~~ ;~~D
l
2811-_....!!;IN~T-=2_
37
52
43
51
45
(j;
:~:
ZERO
!~T
17
+PCMR ON
-PaNER ON
(REF)
;:
~
41
0
I
W
I
IL
+ 5V o-----l5
L
RIB~~~S~~TlON
U
S
i~--::.J:::/:::::.
~
(,)
1'"/!
CAR POS SlG# I
CAR POS SIG# 2
CAR POS SIG# 3
~~: ~
"'I.NT/ ..'/_.
~f""
P2 ...JI--=-'''-'-=--------I.!....2
~~~ ~~~E
I,
I
L
5
SENSOR RET
SENSOR DRIVE
~~ SPARE
L--
35
38
19
22
37
CJ)
«
...-- 43
CD
0-
L - 46
-15VOo--_-~ 21
~ 23
W
~ 26
~ 45
~
~~:=
5
c[
~~
:
2
81----I--....;S:o:E;;,:,R:.:;V.:::.0-=DI;:::S:;.;A.;::B;:LE~~8
Ii
.!:
~
21
C
IS
J.
CAR. SERVO ERROR
20
...
.....
48
24~----~H~A~M~MER~~2~D«~~A~--------------------~ ~
55
T7
'----.!!"
r--
T4
~~>----=
~DT6
..
T5
VEL
32~>-+
47~>--48
PAPER FEEO# I
PAPER FEED#2
W"
51~_-....."
DRIVER RET
~~~
54 f---
55~
56~
D
B
22
20
- HAMMER 3 DATA
- HAMMER 4 DATA
24
16
44
45R
JI4
461-____-'-'HA;..;;M.:c.:ME=R'-C.:...O:.:cIL=--#"-'-I------------<~
25
23
21
- HAMMER 5 ORA
- HAM MER 6 Om-A
- HAMMER 7 DATA
39
41
42
27
28
13
- HANMER 8 DATA
26
- HAMMER 9 DATA
8
47'1---.!==~:"":::::=--------------117
~
+5V
1--!
33
+15VS
2.lSR
:
:: : ~:i==:l=~~~~~---tIO----:~~
:
i
:,
-15VO
+15VD
:
'"
~
31
35
~
Tl2
I
Til
-15V ----~~ -----------_J
T2
r
.--
FUSE
I~R
4!R
:~ R
24
52
~
~
...--
5
22
6
3
9
501-_~-'-H::.:A;:.:;M:.::M=ER:.:..:::C:.::Oc:.:IL::.;:#::..!:6--------_+_---I4
0::
~
~Z
Z
8
a
~ ~~R
~ ~
321-_~--!.HA=M:::M::E!!.R-=C:.=0;:::IL=.:#~7------_+_--I12
10
~
«~
21R
22
~
I-
13 Z
HAMMER COIL# 8
23
20 Q.
8 . - - 54
13R
. - - 55
14
~ 17
~Q'\___..J1!5r_-----'-H;;.;A""WMER=:.:..:::C.;:;0.;.::IL:.:;#:....:::.9----------t___j 23 ~
TI8-'!,Y
,-----112
-.3
~
8'7
:
I
20
HAMMER COIL#5
0:
2
r--
0-...
po-- ..
":'
+15V - - < f - + 15V
•
HAMMER COIL-#'4
a:~
:= ~
TI5
+5V --<~ +5V
.
.-- I
16
HAMMER COIL#'3
II
:~
,-- I
L-
HAMMER COIL#2
19
18 R
Cf)>-
L 34
r--------------- -<~ ~
TI4
--«
S
33S;
34
36
~
44
13
+PFA
26,~~~H~AM~~ME~IRLLI~O~A~~AL---------------------f40~------~4~3r__
~56
~
~
-12V o---~ 54
~
~
~!
:Sr-+---
22
«
~
~
41--1----<
>~
~
46,~--~+~P~F~B------------------------------------------------_4------------_410
...-- 4
CAR MOTOR
~)>---~--.
~~:
27
~ 28
lr--r-
+ PW SERVO ENABLE
(NOT USED)
7)~1----
~ 38
~ 40
~
r--- I
lSI-18
~ 41
~ 42
32
KEf
'V~
>Cf)
31
1"
L--
-15VS
+15VD
(/)
•
:~~~~~~:::::~~:::::::::::::::::::::r::::::::~:
.I •• T/ ..../ T E L . .
TR I
47
-~
-15VS 0------1 !5 3
~3
JI4
42~W
23
241--W
5
6
L--
+15VS
411-_4--'-~
(,)
... t: r-r
- - - -1
48
49
2
CAR I
I--yt:~- -j)~-+-----------------------~~.!L-
REF
(GBB7 7AMP ONLY)
MOTHER BOARD
24935-01
REV. B
083 -025
REVISION HISTORY -#24935-01 MOTHER BOARD
REV.
A ECO#
A1902
As released
B
A3535
Change Key Position from 20-22 to 4-6. Remove 90° form
from 10 terminals.
.
PIM)OUCT
16
17
11
12
13
15
9
10
7
8
5
6
4
Il1O.
400056-01
L
NOTES: UNLESS OTHERWISE
+ sv
19
Y4
+5V
20~----~~--~~--------
C1
+
C4
*Z2
1SV
K
17 18
~
;,0.1
1ZV
R13
150
~~::::CR13
+5V
14
POWER
GND
I ___
~
L
-:;,;-
;Sb
I
1
9,10 I ,.., D "
:
J
-
1
1
17
:
.
:~
,,
11112 •
1
C"'" 1 5
is.
:-
-:
-:
:
:£t.
H
,'
15,16,,...
~
'
A ,.... ,1
~
___ ':.'J
,
,
~
- 12-
2- 1
11 10 9
U2
•
.•
- 7-•6- S-
8
~
4
.•
SW,
4
O~
01
ON
SW 2
3
PA1
02
I/O INTFC
ON
03
SW 3
2
PAZ
04
ON
SW4
1
OS
SW 6
39
34
-- -...
33
-- ..-- -...
-- ---- --...
-.. .-
32
31
30
29
PA3
06
~ON
.
--- -...-
26
VCC
PA~
07
PAil
28
--
27
I
1
.6
PBi&
18
ON
7416
SW 7
38
,
PB1
PA6
PBZ
1 S,16
EON
;SE.
- .
l£
:
~
SW 8
37
~,
-
,
:•
",12 :,..,
E
Pi:l3
.7
ON
SW 9
14
c ,....
15
,~
-=-~
15.1~
-
ON
SW 10
15
ON
SW 11
16
SW 12
17
I~~'
14
+
15
+
ADOR 1
8
-
PORT 3
@
~
23
24
1~
74 LS jf4
5J"1
25
10
13
13 U4 ~12
12
5 U4 ",,6
11
3 U4 ..... 4
7416
RST
PC6
7416
RO
36" WA
PC7
10
1 U4 ":)2
7416
R8...
LED 2
1S'O·
+
DA 1
+
DA
+
DA 3
+
DA 4
+
DA
5
+
DA
6
+
DA
7
R7
LED 3
CRS
I~
R6
LED 4
1S0
t1.
2
3
REFERENCE SCHEMATIC PACKAGE FOR
SPECIFIC ASSIGNMENTS OF LEOS
AND SWITCHES.
2
J
6.
7
8
6
H
5
10
12
G
SPARES:
tt.
3~4
...
~~4
1~
~i1l4
R3
~
1S0
LED 7
CR2
!t-
RZ
CII10
LED 8
1S0
~
9~e
R4
150
LE06
CII!
F
~~4
15'0
CR4
~
~~4
R...5
LEO'S
E
~
~"4
R10
A
LEO 9
CR12
CR11
1S0
~
R11
D
1S0
LE010
~
R12
...
1S0~
LED11
EA-
DA ¢
1S'O"
CR6
OS1
+
8UllER
A_
8255
6
I~
1.
9 US ~8
7416
PC3
CR7
~
11 U5
+
1S·0
CR8
.,..12
13 US
7"16
PC5
9
WR
PB7
PCl
L. ___ ...J
ADOR ¢
0)
",,6
5 US
7416
PC1
PC4
ON
RD
11
CLR
22
3~ "
l/'1"16
7416
,
'" ()."
K
R9
LED 1
2
7416
P B6
-
1
c
,
:~
I
PB4
PC~
PBS
,
13,14: ...... 8"'" 1 3
I
1~
1
:E,
,
21
'U1
:
D
PA7
1
'
9.10: ' " 0 "
20
~
9 U4 ~8
V"7"16
----~
-:.=
19
7"16
12
F
10
11 U4
,
B().:3
+ SV TO PIN 14 OF 14-PIN IC, GND TO PIN 7;
+SV TO PIN 16 OF 16-PIN Ie, GND TO PIN 8.
ALL LIGHT EMITTING DIODES ARE MV5753
OR EQUIVALENT. EXCEPT CR 13 WHICH IS A
5082-4955 OR EQUIVALENT.
+5V
CR9
PAS
14
13,14
4.
13
ON
17
ALL CAPACITANCE SPECIFIED IN MICROFARADS.
5.
40
: -
3.
•I
1K
_______ JI
SW 5
9 10:,.., 0 "
11,12
•
>
---,
t
ON
;Sb
G
!
.•
- --------- -- - -
±
OHMS.
5 '%,.
+SV
,
13,14.,..." B ().13
r-- -------------•
~
~ ~
~
•I • ~
L
SPECIFIED~
1. ALL RESISTANCES SPECIFIED IN
2. ALL RESISTORS ARE
WATT,
A1
CR1
CS
1N4454
E~
R1
+1
:!5
C5
AAA
1
2.~
1K
c
122
3SV
=
~
......
GiNO
SCHEMATIC DIAGRAM
PE
~7
Di.ablo Systemalncorporated
~----------------~.
CONTROL PANEL ASSY,
13
"OOOCT
00400056-01
17
+
12V
H TERM
•
-
I
17
~IIO.
400089-01
I
!
I
16
1
15
!J
14
13
I
12
I
!
11
10
1
1 •
9
I
7
I
I
6
~
5
.
I
I
1
3
rae. . .
III
2
400089-01
1
I
r~ID2 f-
L
L
-
rCONTROL PANEL ASSY
A4
K
PW ASSY
HPR03
A4WI PI
rCLR
t OAI
I
2
-
-
4
5
6
7
J
JI
8
9
10
"
14
15
16
17
H
WR
18
19
20
"
5
I
6
7
J2
P2
8
9
10
II
12
10
II
...
12
13
14
+ 12V
t ADORI
t ADDR I
PORT :3
15
16
GND
GND
17
13
14
15
16
17
18
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I
19
20 20
19
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2
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8
9
NOT USED
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5
6
7
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12
13
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DATA
DATA
DATA
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12
13
14
7
6
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2
4
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16
17
18
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3
4
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6
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7
8
9
10
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12
12
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NOTES:
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-12 V
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ONLY POWER LEADS ARE SHOWN IN THESE
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DRAWINGS FURNISHED BY LH, RESEARCH INC.
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Hayward. ca;1omia IM54S
CORTRON UP/ON STROKE KEYBOARD
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8
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84 83 82 B1
NOTE:
MATRIX
61
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OUTPUT 81. r/J
[24
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SENSE
ADDRESS
TEST
CORE
Fz
---
1
82 53 84 85 86 87
rw
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3
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r
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TEST
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/57 33]49/60
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OUTPUT 87.'
83.r/J
[78
179
B
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f94
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> LEFTOUTPUT
81·1
83· ,
f95
f92
DRIVE
ADDRESS
SCHEMATIC DIAGRAM
•
7
...
01
06
1N995
07
D
+5V
TP1
1
vee
~~~~~~--~----------r_~-r~~_r~~----1-0_;X15
- D~
2
D; ....2_7_ _ _ _----4
~~--------------------~13
1.
ALL RESISTANCES SPECIFIED IN OHMS.
2.
ALL RESISTORS ARE 1;4WATT,
3.
ALL CAPACITANCE SPECIFIED IN MICROFARADS.
,
D1
28
13
D2 29
14
D3
15
....--+-~t-+-...+---e-+------------i X10
,--~
c
30
13
31
11
32
9
~-10--------------------0-4~19
3
&
+ 5V TO
+ 5 V TO
±50;0.
PIN 14 OF 14-PIN I C, GND TO PIN 7;
PIN 16 OF 16-PIN I C, GND TO PIN B.
DIODES 6 AND 7 ARE INSTALLED ON
KEYBOARD BY THE MANUFACTURER FOR
DIAGNOSTIC CODE CHECKS OF STATIONS
48 AND 61.
SECRETARY SHIFT STATIONS 33, 49 AND 60
ARE LOCATED HERE.
~-8--------------------0-5~17
c
74 LSf.f4
17
D6
18
~
• - 03
12
16
D5
6
-02
4.
~------------------~--~20
D 4 1---------------1
'--+-~-r-41~--e-~----r---------~X9
- 01
~-------------------~'8
~r-~~~~--~+--4--;---------~X12
'--+-....-+-~...-.t--....;--4I...-+----------t X11
4
~----------------------~16
~~~~~~----4---_+----r_~_r~~_r--------1-2_;X13
MPRoe
o
NOTES: UNLESS OTHERWISE SPECIFIED,
~-2--------------------0-6~1S
33
X7
19
+5V
le1
20
'--r-~~~~-~+--e--;-------;X5
22
D7 36
X4
23
3
37
5
5 T B t------------;
4
+
- 07 14
-
KYSTB
,.....
12
B
o
®
26
~
C9
.:, B
Q)
(\J
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o
o
v
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____________~94Y'
L..-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-:8
:-t
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L-_ _ _ _ _ _ _ _ _ _ _~~7~YZ
L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~6,Y3
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~5 Y4
4;,Y5
L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
L -________________________________________~3,Y.
~
______________________________________________
+ BUSY
9 ~(--R-E-A-O-Y)~-------t
A
8
- POR
2~Y7
SCHEMATIC DIAGRAM
38
UOILESS OTHERWISE SPECIfIED
DIWE"'SIOOIS .RE '" INCHES
TOlERANCES "RE
XX •
ANGULAR •
~------------------~STR
11
XXl< ,
JO.~_ _ _ _ _ _3_9~ SYSR
r---------------a
Diablo Systems Incorporated
Hayward. California 94545
A
40
C5
~---~~------~osc
~..---.-v\lrv--
-
GND
21
z%
DRAWINGS FURNISH ED BY MICRO SWITCH ,FREEPORT, ILL.,FOR MAINTENANCE PURPOSES ONLY.
61SHOF GFiAFHICS/ACCUFRESS
SC"lE
470PF
400285-01
J8
8
7
BRN
YEL
RED
2
8
4
WHT
GRN
GRAY
CARRIAGE
MOTOR
8
TRANSDUCER
PAPER FEED
MOTOR
PRINTER CABLES
24500-XX
REV. M
Diablo Systems Incorporated
Xt:I(UX
545 Oakmead Parkway
Sunnyvale, California 94086
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