mitra
compagnie internationale
pour I'informatique
15
-
Reference manual
Contents
Genera I
Introduction
MITRA 15 main features
Models MITRA 15/20, MITRA 15/30
MITRA 15 opera ti ng system
Applications
GENERAL LAYOUT
Core memory
Processing units
Micro-programmed ROM (or micro-processor)
Registers
Logical and arithmetical operator
Indi cators
Communication with the environment
Interrupts, suspensions, traps
Mode and protection
STRUCTURE OF A PROGRAM
Definition of modularity
Definition of a section
Section and segment bases
Consequences of modularity on MITRA 15 programs
Constituents of a program
Section calls
System's management concepts
1 -1
1 -1
1 -1
1 -3
1 -8
1 -11
2-1
2 -1
2 -1
2-2
2-4
2-4
2-5
2-6
2-6
2-9
3-1
3-1
3-1
3-1
3-2
3-5
3-7
3-10
4-1
ASSEMBLY LANGUAGE
Source line forma t
Ba si c c ha ra cter set
Symbols
Constants
Expressions
4-4
ADDRESSING MODES
Symbolic representation of the instruction
Addressing mode representation
5-1
5-1
5-2
PSE UDO-IN STR UCTION S
Source text segmentation
Assembly pseudo-instructions
Page pseudo-i nstructi on
6-1
6-1
4-2
4-2
4-2
4-3
6-6
6-14
@)compagnie internationale pour I'informatique 1973
4057 U/EN
203 pages
4057
Contents
IN STR UCTION S
General
Sy mbolic notations
Load and store instructions
LBL
SBL
LBR
SBR
LBX
LDA
STA
LDE
STE
LOX
STX
LOR
STR
LEA
SPA
STS
OLD
DST
7-1
7-1
7-2
7-6
7-8
7-9
7-10
7-10
7-12
7-13
7-14
7-15
7-16
7-17
7-18
7-19
7-20
7-21
7-22
7-23
7-24
7-25
Fixed-point arithmeti c
ADD
ADM
SUB
MUL
DIV
7-25
7-26.
7-27
7-28
7-29
7··30
Logi ca I opera ti ons
lOR
EaR
AND
CMP
7-31
7-31
7-32
7-33
7-34
Register incrementation and decrementation
ICX
DCX
ICL
DCL
7-35
7-35
7-36
7-37
7-37
Shift operations
SHR
SLLS
SRCS
SAD
SLCD
SLCS
SAS
SRLS
SRCD
SHC
SLLD
SRLD
PTY
NLZ
7-38
7-40
7-41
7-42
7-43
7-44
7-45
7-46
7-47
7-48
7-49
7-51
7-52
7-53
7-54
4057
Contents
Inter-regi ster opera ti ons
SRG
XAE
XAX
XEX
XAA
CCE
ACE
CCA
AEE
CNX
AlE
AAE
lNE
CNA
CMX
7-55
7-56
7-57
7-57
7-58
7-58
7-59
7-59
7-60
7-60
7-61
7-61
7-62
7-62
7-63
7-63
Floating-point arithmetic
FAD
FSU
FMU
FDV
7-64
7-66
7-67
7-68
7-69
Byte stri ng processi ng
MVS
CPS
TRS
7-70
7-70
7-71
7-72
Branch instructions
BRU
BRX
BCT
BOT
BCF
BOF
BAZ
BAN
BE
BZ
Bl
BlZ
BNE
BNZ
BGE
BPZ
7-73
7-74
7-75
7-76
7-77
7-78
7-79
7-80
7-81
7-82
7-83
7-84
7-85
7-86
7-87
7-88
7-89
System communi cation instructions
ClS
RTS
CSV
RSV
DIT
DITR
7-90
7-90
7-93
7-94
7-96
7-97
7-100
Control instructions
TES
STM
ClM
7 -101
7-102
7-103
7-103
4057
Contents
RD
WD
LDP
INPUT/OUTPUT CONTROL SYSTEM
Input/output system organization
Input/output interface
Tra nsfers
f.:
Operationa I labels
Handler uti lization
LIST OF PSEUDO-INSTRUCTIONS
7-104
7-104
7-105
8-1
8-1
8-1
8-6
8 -11
8-14
A-1
LIST OF INSTRUCTIONS
B-1
ADDRESSING MODES
C-1
ASSEMBLER OPERATION
D-1
The informations contained in this manual can be modified without warning.
mitra
15
1.
General
1-1. INTRODUCTION
MITRA 15 is a real time computer relying on a modular design and advanced micro-programmed structure
for an efficient approach to numerOU5 application fields, such as process control, scientific computation,
remote-processing or transaction management.
The system includes up to four processing units specialized through read-only micro-programmed memories
(ROM) and arranged around a planar structure core memory. According to their micro-programs, these units
become CPU's, lOP's or special-purpose units. Each processing unit is provided with a "MIN I BUS" for
connecting a comprehensive range of periphera I units.
MITRA 15 is available in two fully compatible models which only differ by their processing capacity and
the range of connectable peripheral units. Thus, each user can select the model and configuration best
suited to its specific requirements.
1-2. MITRA 15 MAIN FEATURES
1-2.1 • Core memory
MITRA 15's memory is a lithium-ferrite core random access memory organized in 16-bit words with 2 additional bits, 1 for parity and 1 for protection. The very short 800 nanoseconds word read/write cycle provides an outsta ndi ng tra nsfer ra te of 2.5 Mbytes per second (m ill ions of bytes/second) •
Memory contents are adressable on a byte basis and alterable on a byte, half-word or word basis.
The memory is made up of 4 096-word blocks (i.e. 8 192 bytes) up to a maximum of eight. Its capacity can
thus be extended from 4096 words to 32 768 words per 4 096-word increments.
•
Dynamic memory protection
This feature provides full protection to any memory area against unwanted attemps to alter its contents.
The protection its assigned on a dynamic basis (LDP instruction).
A I-bit protection "lock" is associated with every memory word. Besides, an indicator of the program
status acts as a "key" : when this indicator is set to I, the program is able to gain access to all memory
locations; otherwise the program can only gain access to unprotected areas.
•
Parity
Full parity ckeck is provided both in the memory an during I/O operations.
1-2.2. Processing units
The functions available in a conventional computer are shared between a wired module, indentical for all
processing units, the so-called "micro-processor", and the contents of a ready-only control memory which
"specializes" the micro-processor to provide the functions of a CPU, lOP or special-purpose unit.
A processing unit comprises a fast register block, five program indicators, a micro-programmed read-only
memory, an operator and an interrupt/suspension system.
1-1
4057 U
•
Fast register memory
This memory is implemented in MSI bipolar integrated circuit registers which are organized in eight 16-bit
program-adressable register blocks. The capacity of each processing unit can be extended from two to eight
8-register blocks per 2-block modules. Access time: 60 nanoseconds per word.
In the CPU, the first block (block 0) is assigned to the program context, the remaining blocks being available for peripheral transfers.
In an lOP, all block are available for peripheral transfers.
P
Program counter
L
Loca I base
G
Genera I base
A
Accumulator
E
Extended A reg.
X
Index
Program context
Block 0 of CPU
•
Program indicators
C
Carry or operation test
a
Overflow or opera ti on test
MS
Mode: master/slave
MA
Interrupt Mask
PR
M em ory prote cti on
For detailed description of indicators see chapter II.
•
Instructions
MITRA 15 has a set of 86 instructions including:
- 40 memory reference instructions,
- 29 register instructions,
- 12 shift instructions,
-
5 special instructions.
All instructions have a fixed format:
3
5
IMode I
Function
4
4
8
Displacement
or
/Mode
1-2
'Function
8
Displacement
4057 U
They operate on bytes (half-words), words, double-words or unlimited length byte strings.
Addressing modes:
- immediate addressing for operands which can be coded in one byte;
- direct, indirect and indexed addressing with respect to the local base;
- direct, indirect and indexed addressing with respect to the general base.
•
Micro-programmed read-only memory
This non-destructive read out permanent memory is pre-recorded. Each 16-bit word contains one microinstruction. The memory is implemented in MSI bipolar IC 's and its access time is 60 nanoseconds. Its
capacity is 512 or 1024 words per processing unit.
Three different versions are avai lable for the following functions:
MCl
executes the basic instruction code and the coupling functions for peripherals which are connectable to CPU's Minibus only.
MC2
executes the complementary code (optional instructions) and the coupling functions for peripherals
which are connectable to the Minibus of either the CPU or an lOP.
MC3
executes the coupling for peripherals which are connectable to an lOP's Minibus.
•
Interrupts (IT)
32 priority interrupt levels are available which can be armed, masked or triggered by program. They provide
up to 112 discrete external interrupts by grouping.
When an interrupt is triggered, the program context is automatically swapped in 30 ps.
For a special high speed interrupt level, this swapping is effected in 5 ps only, by register block switching.
•
Suspensions
MITRA 15 also offers 32 suspension levels organized on a priority basis for micro-program coupling of
periphera Is requiring urgent or frequent transfers.
The maximum response time is 300
•
J.,IS.
Minibus
Each processing unit is provided with a Minibus for device controllers connection. This Minibus is implemented as a printed circuit located in the chassis wiring and provides non-specialized plug-in locations for all
controller cards.
1-3. MODELS MITRA 15/20, MITRA 15/30
MITRA 15/20
•
MITRA 15/20 CPU comprising, as standard:
- 512-word micro-programmed ROM (MCl),
-
64 fast access registers,
- Basi c code providing for 77 instructions,
- Priority interrupt system.
1-3
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•
Core memory
4K to 32K 16-bit words per 4K increments.
•
Performance
- Addressing mode: direct, indirect, indexed, relative, immediate, local and general.
- 1 index, 2 bases.
- 77 instructions, including 33 memory reference instructions.
- Load, store or add word in 2.1 ).Is.
•
Main options
- Up to 3 direct memory accesses (DMA)
- Additional micro-programmed ROM (MC2)
- Up to 32 priority interrupt levels per 1 or 4 levels modules.
- Wired MULjDIV (7 and 8 ).Is).
- Floating point operator (OVF).
- Power fa i I ure protection.
•
Software
- MITRAS 1 Assembler;MITRAS 2 Extended Assembler; LP 15; BASIC; FORTRAN IV.
- li nka ge edi tor.
- 2 Monitors: Basic Monitor MOB and Real-Time Monitor MTR.
- Libraries.
•
Basic peripherals (Range I)
- Console typewriter (with paper tape reader/punch),
- 300 char ./sec. paper tape reader,
- 60 char./sec. paper tape punch,
- Logging slow printer (15 char./sec.),
- 2 to 128 16-bit digital input lines for logical levels, or filtered, or relayed,
- 2 to 64 16-bit digital output lines for logical levels or relayed,
- Counter inputs; real-time clock,
- Ana log inputs.
1-4
4057 U
CORE MEMORY
4K
4K
4K
4K
4K
4K
4K
4K
words
words
words
words
words
words
words
words
Logging
Real time clock
digital inputs
digital outputs
analog inputs
counter inputs
interrupts
MITRA 15/20 general layout
1-5
4057 U
MITRA 15/30
•
MITRA 15/30 CPU comprising, as standard:
- 1024-word mi cro-programmed ROM,
- 32 fast access registers,
- Extended operation code for 86 instructions,
- Priority interrupt system,
- Wired MUL/DIV,
- Power failure protection.
•
Core memory
4K to 32K 16-bit words per 4K increment
•
Performance
- Addressing modes: direct, indirect, indexed, relative, immediate, local and general.
- 1 index, 2 bases
- 86 instructions, including 40 memory reference instructions
- Load, read, write or add word in 2.1 ps
- M UL/DIV in 7 and 8 ps, respectively.
•
Main options
- Up to 3 direct memory accesses (DMA)
- Up to 3 input/output processors (lOP)
- Extension to 128 fast access registers per processing unit (64-level modules)
- 32 priority interrupt levels per 1 or 4 level modules
- Floating-point operator (OVF)
Ii
Software
- MITRAS i Assembler; MITRAS 2 Extended Assembler; Macro-generator; LP 15; BASIC; FORTRAN IV;
Librarian; File management system.
- :3 Monitors: Basic Monitor MOB; Real-Time Monitor MTR; Disk Real-Time Monitor MTRD.
•
Peri phera Is
• Range I (Model 20)
• Range II :
- One head per track fixed-disks; average access time 10 ms, transfer rate 150 kbyte/sec, capacity 100 to
1600 kbytes.
- Movable head disk-pack units; average access time 60 or 90 mSi transfer rate 100 or 150 kbyte/sec;
capncity 2.5 to 5 Mbytes or 6.2 to 24.8 Mbytes.
- Card reader: 200 or 600 cpm.
- Card punch: 20 or 40 cpm.
1-6
4057 U
CORE MEMORY
1K
or
4K
4 K words
words
4K
4K
4K
4K
words
words
words
words
4K
4K
words words
Cartridge disk
I nterface for
10000and IRIS
series peripherals
Card reader
Logging
Card punch
Card reader
High-speed printer
Line printer
Real-time clock
digital inputs
digital outputs
Tape handlers
analog inputs
Synchronous ••• --data links ....:.II.~
..".-jI"'"
..
, ,
Asynchronous ••••• "
data links •• 11.......
interrupts
"'~
--""
.., ......••••
Disk packs
MITRA 15/30 genera I layout
1-7
4057 U
- Line printers: 132 columns; 200, 400 or 600 Ipm.
- Communication controller for 1 synchronous data link, full duplex, 1200/4800 bauds
- Communication controller for 2 asynchronous data links, full duplex, 50 to 1200 bauds.
• Range III :
- OCTET interface for connecting all CillO 000 or IRIS Series peripherals: (card readers, printers, tape
handlers, etc ••• ).
1-4. MITRA 15 OPERATING SYSTEM
Depending on the availability of a fast access disk unit, the software is offered in two different versions:
the resident system and the disk system.
•
The resident system provides:
- 2 Monitors: the Basic Monitor MOB and the Real-time Monitor MTR
- Assemblers: MITRAS and LP 15; Compilers: BASIC and FORTRAN and a Macro-generator.
•
The disk system provides:
- The real-time Monitor MTRD
- The resldent system processors, a librarian and a linkage module.
In addition, the software includes:
- Debugging commands avai lable as extension of each monitor.
- A comprehensive library of "real-time" mathematical programs, and a file management system.
- MITRA 15 Simulators available for use on CillO 070, IRIS 50, IRIS 80, IBM 360, etc.
M!TRAS 1 Assembler
Translates the symbolic MITRAS language generates in one single pass a relocatable binary object-listing
a nd a list of error dia gnosti cs.
i
Both source and relocatable binary programs are normally on paper tape; memory requirement: 4K words.
M!TRAS 2 Extended Assembler
Translates the symbolic MITRAS language; has a larger set of pseudo-instructions than MITRAS I. Memory
requirement: 8K words.
LINKAGE EDITOR
Operates in two passes for converting binary relocatable programs generated during various assembly or
compilation runs, into a relocatable memory image format which can be loaded for execution by the Basic
Monitor.
The linkage editor also provides a memory map of the relative location of the various modules and a listing
of the common sub-routines which are called. Memory requirement: 4K words.
1-8
4057 U
BASIC MON ITOR MOB
Perform computer control and handles user's communications with the system and the basic processors. Its
main functions are
- trap processing,
- internal interrupt control,
- program loading,
- i nput/ output control,
- program execution control.
Memory requirement: 4K words.
REAL-TIME MON IT OR MTR
Handles simultaneously interrupt-dependent batched jobs in core. Controls and supervises all privi leged
operations, such as I/O handling or memory protection, and provides operator communication. Memory
requirement: 8K words.
4 Kwords
OPERA TlNG
SYSTEM
resident
system
Basic Monitor
MOB
disk
system
PROGRAM
GENERATION
resi dent
system
disk
system
LIBRARY
MITRAS I
linkage editor
loader-editor
8 Kwords
12 Kwords
16 Kwords
Real-time
Monitor MTR
Simulation
control command
ana Iyzer
interpreter
disk real-time
Monitor MTRD
linkage
module
MITRAS 2
lP 15
FORTRAN IV Assembler
linkage editor
FORTRAN IV
Macrogenerator
BASIC
MITRAS 2
linkage editor
BASIC
lP 15
librarian
lP 15
Mathematical programs real-time
programs communication programs
file management system packages
Structure of MITRA 15 standard software
1-9
4057 U
DISK REAL-TIME MONITOR MTRD
This disk-oriented version of the MTR Monitor has additional capabilities for overlay control and user's
libraries management, as well as for automatic linking of batched programs (com pi Ie-link, .Ioad-and-go);
requires 8K words memory and a fast access disk unit.
LOADER - LINKAGE EDITOR
Operates in one pass for loading binary relocatable programs for immediate execution.
This processor can only accept binary programs generated by MITRAS I. Memory requirement: 4K words.
LP 15
This assembler type language has a syntax which is closely related to that of sophisticated languages such
as ALGOL, but with the feature of direct access to MITRA 15's registers.
The binary object programs thus generated have an efficiency which is practically equivalent to that of
assembled programs. Memory requirement: 12K words without a disk unit.
BASIC
This conversational compiler provides for time-shared operation and alphanumerical data processing.
Memory requirement: 8K words.
FORTRAN IV
This compiler generates in one single pass a relocatable binary object-program in the format required by
the linkage editor. May call sub-routines written in another language and translated in relocatable binary
format; compatible with C II 10020, IRIS 45 and IRIS 50. Memory requirement: 16K words or 12K words
with a disk unit.
AMAP EXTENSION (DEBUGGING AIDS)
An AMAP extension available with every monitor as a debugging aid and provides instruction execution
records, halt on address, memory dumps and contents alteration, through special monitor commands.
LINKAGE MODULE
Provides for automatic linking of batched programs in the deffered processing area with concurrent realtime programs.
This processor is controlled by the disk real-time monitor MTRD; requires 12K memory words and a fast
access disk unit.
MACRO-GENERATOR
Translation program using user-defined procedures. It provides in one pass a program in assembly or compilation language. Memory requirement: 16K words.
LI BRARIAN
Provides for handling the system library constitutive files through commands such as: insert, replace, copy,
load, dump on external medium ••• Memory requirement: 8K words and a fast access disk unit.
1 -10
4057 U
UTI LlTY PROGRAMS
These programs are available for:
- Updating and correcting source programs on sequential access media (paper tape, magnetic tape, etc.).
- Handling and updating library programs on sequential access media. Memory requirement: 4K words.
MITRA 1 5 S IMULA TOR S
These simulation programs are available for CillO 070, IRIS 50, IRIS 80, IBM 360, etc. computers and
include:
- a MITRA 15 interpreter,
- MITRAS Assembler and Linkage editor,
- a system genera tor,
- LP 15 Compiler.
They perform assembly, linkage edition and debugging functions on programs intended for later exploitation
on any MITRA 15 configuration.
1-5. APPLICATIONS
LA BORA TOR IES
Spectrometry
Gazeous chromatography
Crista IIography
MEDECINE
Chemical analysis
EIectrocardi ography
ENGINEERING
Components testing
Seismography
Ranging
INDUSTRY
Monitoring
Automation
Process control
Chemicals
Oil and derivates
Steel industry
Mechani ca I engineering, aerospace, etc.
REMOTE PROCESSING
Front-end computers
Sa te II i te sta ti ons
Front ends
Deconcentrated companies
Public Administrations
Universities
SCIENTIFIC COMPUTATION
Time-shari ng
Data centers
Education
Desi gn offi ce
Private companies
TRAN SACTION PROCESSIN G
Data collection
File management
Insurance companies
Banks
Public services •••
1-11
mitra
15
2.
General layout
MITRA 15 is built around a planar structure core memory the capacity of which can be extended modularly
by 4K 16-bit words blocks. This core memory has four access ports for connecting up to four processing units
or direct memory access controllers.
Each processing unit includes a micro-programmed read-only memory (ROM); a specific micro-program prerecorded in this memory specializes the associated processing unit for performing the functions of :
- a central processing unit (CPU),
- an input/output processor (lOP), or
- a special-purpose unit for a particular process.
Each processing unit controls a so-called MINIBUS which is a peripheral bus designed for direct connection
of peripheral controllers.
11-1 • CORE MEMORY
The core memory is basically organized in 18-bit words each comprising 16 data bits, 1 parity bit and 1
memory protection bit.
Read/write operations are executed in two separate half-cycles. A read cycle includes a destructive readout ha If-cycle followed by a rewrite ha If-cycle. A write cycle includes a clear ha If-cycle followed by a
write half-cycle.
Memory access time is 400 ns (1/2 cycle) and a full read/write cycle lasts 800 ns.
Though memory transfers are performed on a word basis, micro-commands allow the programmer to operate
on bytes, i.e. on half-words. Thus, all MITRA 15 addresses point to byte locations, even-numbered
addresses corresponding to word locations.
The memory is built up with 4096-word modules, i.e. 8192 bytes. MITRA 15 is designed for a maximum of
eigh modules corresponding to a maximum capacity of 32 768 words (or 65 536 bytes).
The control logic supplies the timing signals required for operating the memory proper (half-cycles timing
control), and the transfer signals for data exchanges with the processing units; in addition it deals with the
four accesses relative priorities.
11-2. PROCESSING UNITS
The operation of a MITRA 15 processing unit, and more specifically of the CPU, may be described at two
fully distinct levels:
• A first level corresponding to what may be termed "user-level" and the knowledge of which is sufficient
for programming an application on MITRA 15.
it includes the following features:
- the standard instruction set detailed in chapter VII;
- six general registers of block 0;
- the five program i ndi cators;
- the interrupt system.
11-1
4057~U~'
•
______________________________________________________________________
A second level corresponding to what may be termed "micro-processor" level
This micro-processor includes the following features:
- a set of about forty hardware-implemented basic micro-instructions;
- a read-only memory implemented on module boards and which contains the sub-routine set, (also called
"micro-programs") defining MITRA 15's standard instructions set and peripheral coupling functions;
- operational registers;
- micro-processor sta tus i ndi ca tors;
- a so-called "suspension system" corresponding, for the second level, to the interrupt system of the first
level.
The following sections describe the various components of a processing unit, viz:
- micro-programmed ROM
- Sand M memory transfer registers
- fast-access register blocks
- status indi cators
- interrupt and suspension systems.
11-3. MICRO-PROGRAMMED ROM (OR MICRO-PROCESSOR)
This non-destructive ROM is pre-recorded in factory and implemented in integrated circuits (access time:
60 ns per word) .
Each memory word is 16 bits long and contains one micro-instruction.
The control ROM of a processing unit contains either 512 words (Mel), or 1024 words (MCl + MC2).
Any micro-instruction is executed in 300 ns.
The address of the currently executed micro-instruction is contained in a 10-bit register called T-register.
A micro-instruction has the following format:
o
2
M
6
OP
7
9
CC
10
15
AD
Each micro-instruction has a dual purpose:
1) It controls a number of functions, viz. :
- memory control (2 bits: M-field)
- basic operation code (generally 5 bits: OP-field)
- complementary operation code (3 bits: CC-field) defining for instance a general register address
2) It defines the address of the next micro-instruction (through a 6-bit modifier: AD-field), by updating
T-re;Jister contents.
In fact, micro-instructions are not stored sequentially.
No indexing adder is associated with T-register, since its contents is not incremented by one unit from a
m i cro-i nstructi on to the nex t, as ina seq uentia I a ddressi ng sc heme.
11-2
4057 U
CPU's and lOP's are differenciated by the kind and contents of their respective control memories.
In the CPU, MCl control memory (512 words) executes the basic operation code and the coupling functions
for peripherals which are connectable to its Minibus only (Range I).
MC2 control memory provides for executing the complementary operation code (optional instructions) and
the coupling functions for peripherals which are connectable either to the Minibus of the CPU, or to the
Minibus of an lOP (Range II).
The CPU's control memory then includes 1024 words (MCl + MC2).
MC3 control memory executes the coupling functions for peripherals which are connectable to the Minibus
of an lOP only (Range III).
CORE MEMORY
1K
or
4K
words
4K
4K
4K
4K
words
words
words
4K
4K
words
4K
words
words
J
I
I
words
I
t
I
S
J
I
I
U
I
M
~
I
MEMORY BUS
-
address
read/write
PR
r----l
T 1-1I
I
I
I
Operator
I
I~~ micro-processor
I
I
Register
memory
-
interrupt~ 0LG
-
suspensions
I
r-I
L _____ J
ROM
I
MS
command
execution
MINIBUS
--
commands
read
write
i nterrupts
- ----suspensions
Processing unit layout
11-3
4057 U
11-4. REGISTERS
11-4.1 . Memory transfer registers
S-register is a 15-bit address register, though actual addresses are 16 bits long. The rightmost bit of an
address, which specifies the desired byte within the addressed word, is in fact ignored by the memory logic.
M-register is an 18-bit data register receiving the transferred memory words. Two of these bits are reserved
for parity and protection tests; the 16 other bits are used for date exchanges with U-register.
11-4.2. Fast-access registers
A standard MITRA 15 processing unit includes eight register blocks each comprising eight 16-bit integrated
circuit registers numbered 0 through 7. Eight optiona I blocks are avai lable on 15/30 model.
These registers have different assignments in the CPU and in an lOP.
In the CPU, the first block (block 0) is reserved for program execution; its first six registers have the following functions:
A
Accumulator,
E
Accumulator extension,
P
Program counter,
X
Index register,
L
Local base register,
G
General base register,
the last two registers, V and W ared used by micro-programs.
The other blocks are normally assigned to peripheral transfers through the suspension system (channel memories) .
In an lOP, all register blocks are available for peripheral transfers.
Each register has a unique address form 0 to 63 (or 127). In the micro-programs, a general register address
is generated from:
- the contents of the corresponding field of the micro-instruction format (3 bits).
- the contents of J-register.
:t will be seen in section 11-8. that a high-speed interrupt causes an automatic switching of the register
block. In the new block, the registers have then the same assignment as in block 0, but for other programs.
! 1-5. lOG ICAl AN D ARITHMETICAL OPERATOR
The logical and arithmetical operator includes a universal register, or U-register, and a dual-input operator ~ The 16-bit U-register cannot be directly accessed by the instructions, but constitutes an accumulation
register for the micro-processor. In this respect it can contain one operand of a micro-instruction and/or
store the result. Both operands of a micro-instruction may also be provided by :
- a general register (operand 2)
- M-register in connection with the core memory (operand 1)
- the I/O interface (operand 2)
- the control memory (operand 2)
11-4
4057 U
- the stack (operand 2)
- the indicators (operand 2)
The results of the operation are stored in the following devices:
- U-register (universa I)
- M-register {data}
for core memory transfers
- S-regi ster {a ddress}
- a general register
- the indicators
11-6. IN DICATORS
MITRA 15's central processor includes nine indicators:
•
Four i ndi ca tors reserved for micro-processor use :
B-indicator
assigned to U-register overflows
Tz-indicator
for a zero micro-instruction result
To-indicator
for the sign of a micro-instruction result
Ao-indicator
address of the processed byte.
•
C
Five program-accessible indicators
= Carry
-; his indi cator has two different meanings according to the last instruction by which it is set.
• Carry/borrow {arithmeti c type instruction}
- When a positive number is added {negative number subtracted}, if the result is obtained without becoming
zero, C is reset (C = O).
- When a positive number is added {negative number subtracted}, if the result is obtained after becoming
zero, C is set (C = 1).
- When a negative number is added {positive number subtracted}, if the result is obtained without becoming
zero, C is set (C = 1).
- When a negative number is added (positive number subtracted), if the result is obtained after becoming
zero, C is reset {C = O}.
• For other instructions using C-indicator, the status C-indicator, the status C = 1 after execution denotes
a zero value in a register or, in the case of a comparison, equality of two values.
o = Overflow
This indicator also has two different meanings according to the last instruction executed.
• For arithmetic type instructions, O-indicator is used for overflow. More precisely, when both operands
have the same sign, if the result is of the opposite sign, 0 is set (0 = 1). Otherwise, 0 is reset (0 = O).
• For other instructions using O-indicator, the status 0 = 1 after execution denotes a negative value in a
register (leftmost bit set) or, in the case of a comparison, that A-register value is less than the addressed
word value.
11-5
4057 U
MS
= Master/Slave
mode
For programs executed in Master mode, this indicator is set to 1, otherwise the program is executed in normal or "slave" mode.
See chapter VII "Instructions" for detailed description of the above three indicators for every instruction.
MA = Interrupt mask indicator
This indicator is set to 1 for masked interrupts, otherwise MA
= O.
PR = Memory protection "key"
When PR
= 1,
the program is able to gain access to any memory location.
When PR = 0, the program is only allowed to gain access to unprotected memory areas ("protection lock"
cleared) .
These five indicators are incl\Jded in the context of a specific program.
11-7. COMM UN ICA TlON WITH THE ENVIRONMENT
The processing unit is coupled to the peripheral controllers via a so-called MINIBUS which is accessible
through mi cro-instructions. The interface includes:
- for data: 16 output bit lines and 16 input bit lines;
- three functi on bi t lines;
- for addresses: 6 bit lines or 10 bit lines in particular cases;
- a sync line;
- a reset line.
The peripheral Minibus, on which the peripheral controllers are connected, includes 16 unidirectional data
lines, both for input and output, an address and peripheral control bus, as well as interrupt and suspension
lines.
11-8. INTERRUPTS - SUSPENSIONS - TRAPS
11-8.1 • Interrupts
ihe interrupt system operates when
- a fl interrupt si gna I occurs;
- a special micro-instruction, located by definition at specific "interrupt point", occurs;
- interrupts are unmasked;
- tf·,0 priority level of the current program is lower than that of the incoming interrupt.
There are 32 interrupt levels (IT levels). Each of these levels has an associated memory address containing
the context pointer of a program specifically assigned to this level. These 32 context pointers are stored in
a table pointed to by the contents of memory address 10.
WheOl an interrup,t condHio.n occ..lIrs :
- the condition is stored in a flip-flop (one per signal),
- its IT-level is hardware-coded and compared with that of the task currently processed (register 8),
11-6
4057 U
- if the interrupt is accepted, its specific IT-level (0 through 32) is stored in the hardware of the microprocessor when the interrupt test mi cro-j nstructi on is executed,
- then, the micro-program performs the following operations:
• Storage of the interrupted task context at an address depending on its rank (the latter being stored in
register 8) •
• Loading of the interrupting task context from an address depending on its rank.
Call of the first instruction of the interrupting task. (See "Communication with the micro-processor"
page 11-8).
When the task is over or must wait for the occurence of a specific event, it releases the processing unit
through an interrupt de-activation and context swapping instruction OIT which:
- acknowledges the interrupt ca lIing for the task,
- stores the task's context, and
- calls for the next task waiting at the same IT-level, or, if there is no such task, for a task waiting at the
next lower IT-level.
If no task is waiting, the computer executes a wait loop until an external event occurs at the lowest level.
The total number of interrupt levels is 32, 4 internal and 28 external. Besides, up to 4 interrupts may be
on a same level, providing a total number of multiplexed external interrupts equel to 112 (28 x 4).
As a rule, standard periphera I controllers use one interrupt level each.
Internal interrupt levels are assigned to the following tasks:
- operator's console interrupt request,
- power turn on,
- power shut down,
- program (level 0).
High-speed interrupt
Optionally, one external IT-level may be of the "high-speed" type, i.e. may call fora task the context
of which is stored in a register block other than block 0, which contains the interrupted task context.
Consequently, the task switching only requires that the indicators be transferred in block 0; it lasts about
2 }JS.
When this "high-speed task" is acknowledged, the control is returned to the interrupted task (the context
of which is still in block 0) through a special OITR instruction by-passing the usual context swapping in
block O.
11-8.2. Suspensions
The suspension system is able to interrupt the current micro-program at the end of every micro-instruction,
and to launch a special micro-program. The suspension request is either issued by a peripheral or internal
to the micro-processor (processi ng uni t) .
On occurence of a suspension, the micro-processor's status, i.e. the contents of U-, J-, T-registers and
of 8, Tz, To, Ao indicators are transferred in a stack. The suspension micro-program is then executed.
At the end of the suspension program, the initial contents of U-, J-, T- •.• registers are restored from the
values previously saved in the stack.
11-7
4057 U
REGISTERS
VM
PM
AI
PA
II
ES
MS
MA
C,O
i = IT rank
SRD(k}
PG
..
PR
••
Mode violation
Memory protection violation
Non-existing address
Parity error
Non-implemented instruction
I/O error
Mode indicator (Master/Slave)
Interrupt mask
Program indicators
Double-word specifying the
assi gnment of Supervi sor 's k-secti on
Trap in a program or I/O
Access to protected areos
I
•
CORE MEMORY
o
78
15
PRTS (PRT Supervisor)
~
SRD(k)
~
SRD(o)
4k
associated deactivation words
-----~
--------
group IT no
Communication with the micro-processor
11-8
IT group
4057 U
The stack has a capacity of four suspensions, i.e. the number of suspension levels is four. The number of
suspension signals is 32, or 8 per level, assigned as follows:
- 5 i nterna I suspensi ons :
traps (1)
interrupts (2)
control panel (1)
power failure (1)
- 27 external suspensions associated with peripherals.
/1-8.3. Traps
The origin of a trap is an abnormal condition detected at the end of a micro-instruction.
The trap processing micro-program:
- protects bytes 4 to 9 of the memory which contain L- and P-register values and the indicators status of
the context of the instruction which initiated the trap;
- signals the cause of the trap by setting a bit in memory word 2;
- performs a ca II to supervisor section
o.
The following abnormal conditions initiate a standard trap:
- non-existing memory address: the user has specified an address exceeding the available memory.
- memory protection violation: the user attempts to write in a protected memory area with a zero PR-key.
- parity fault in core memory read-out signals.
Other traps may be initiated by the following causes:
- operating mode violation: attempt to use privi ledged instructions in a slave mode program.
- invalid instruction: incorrect OP-code specified.
- "watch-dog" timer runout.
In all these situations:
- the current instruction is
~borted,
- the micro-processor's stack is not triggered,
- a special micro-program generates a supervisor call.
The operations performed by the standard monitors in response to a trap condition are described in the
corresponding utilization manuals. The trap status word is described in "Communication with the microprocessor" diagram page 11-8.
11-9. MO DE AN D PROTECTION
11-9.1 . Operating modes
- Normal or "slave" mode.
In this mode, priviledged instructions cannot be executed and any attempt to execute such an instruction
causes a "mode violation" trap. MS indicator is reset (MS = 0).
11-9
4057 U
- Privi ledged or "master" mode.
In this mode all instructions, whether priviledged or not, are executable. MS indicator is set (MS = 1).
The various supervisor modules are examples of programs which must be executed in master mode. (See
CSV and RSV instructions).
It should be noted that addressing modes are different in master and slave modes (see Chapter V "Addressing
modes") to provi de absolute addressing capabi lity in master mode.
11-9.2. Memory protection system
The protection system becomes operative whenever PM key-switch is turned on the control panel.
The operation is as follows:
- a l-bit protection "lock" is associated with each memory word and may be set by a LDP instruction
(Loa D Protection).
- the program status includes a PR-indicator which acts as a "key".
If key value is 1 (override key), the program may gain access to all memory locatiom.
If key value is 0, the program may only gain access to memory locations whose lock value is O •
•
PR-key loading
The PR indicator is loaded with the program context.
It is preserved before being forced to 1 during any supervisor call SVC and restored to its previous value
when the supervi sor returns the control to the ca II i ng program.
•
Protection violation
If a "zero key" program attemps an access to any location having a 1 lock value, the protection system
operates and initiates a "protection violation" trap.
Memory protection and operating mode are independent.
11-10
mitra
15
3.
Structure of a program
111-1. DEFINITION OF MODULARITY
In programming art, as in other techniques, the modularity consists in breaking down a system in to smaller
elements with standard interfaces.
Since the introduction of the "sub-program" concept, modularity is an acomplished fact in programmation.
As a main program may also be considered as a module, we rather call them "sections". The following
advantages are due to modularity:
- easier system specification,
- easier software writing, by sharing the work between a number of programmers,
- identical sections may be used in different system without rewriting,
- easier debugging and assistance on software products.
111-2. DEFINITION OF A SECTION
A section mainly comprises an instruction sequence called a program segment. The purpose of these instructions is to process data which are either assigned to the section, or shared between a number of sections.
Data which pertain to a section in proper make up a "local data segment" (LOS).
Data which are common to several sections make up a "common data section" (CDS).
Accordingly a section is either the common data section CDS, or a local data segment (LOS) plus an executable program segment (Loca I Program Segment = LPS).
The CDS is accessible from any point in the program.
More particularly, the CDS may be accessed from a LOS in general addressing mode (direct, indirect or
indexed indirect).
Symbols and labels defined in the CDS are applicable to the whole program.
A LOS is accessed from the associated LPS in local addressing mode (direct, indirect or indexed indirect).
Symbols and labels defined in a LOS are applicable to the section only. Nevertheless, they may be referenced in the CDS. A program segment is exclusively made up of unalterable items (instructions), and this
improves relocatabi lity and simplifies writing of re-entrant sub-routines.
111-3. SECTION AND SEGMENT BASES
• Genera I base G
General base G is uniquely assigned to the program; it constitutes an implicit base to which every address
referenced by this program is related. Accordingly, the micro-processor automatically adds this base value
to all addresses specified in the instructions •
• Loco I base L
Local base L is the implicit base value for all local data contained in a local data segment (LOS).
111-1
4057 U
• Program base P
Program base P is assigned to a loca I program segment (LPS).
Initially, base P is the starting address of the section and from there on acts as a program counter for the
currently executed section (see Chapter 111-2.).
The actual values of L- and P-bases may be unknown at the time a program is written. At linkage edition
time, they are automatically generated in relative value with respect to the general base of the program
and stored in the associated PRT.
111-4. CONSEQ UENCES OF MODULARITY ON MITRA 15 PROGRAMS
From the hardware viewpoint, modularity implies the existence of special instructions for section calls and
returns.
From the software viewpoint, program modularity is a fundamental concept of the assembly language which
includes so-called "segmentation" pseudo-instructions:
CDS
Common Data Section
LDS
Loca I Data Segment
LPS
Local Program Segment
FIN
End of segment or section (LDS, LPS or CDS)
I DS
Indirect Data Segment.
We shall call "program module" the result of an assembly or compilation processing. When a module is
written in assembly language it is rather ca lied "assembly module". Every assembly module must conclude
with an END pseudo-instruction. A program may be built up from modules of various origins (differing by
their source language, author, creation date, etc.).
The linkage editor interconnects the various modules into a complete executable program.
Remark:
To facilatate the programming, particularly in the case of re-entrant sub-routines, the assembler recognizes
so-called "dummy data segments" which are images of later-defined data or of data belonging to another
LDS (or CDS) than the LDS in which the dummy area is defined.
These dummy segments are treated as formal parameters, in particular for defining relative displacements
with respect to the beginning of the segment (description of dynamic data blocks, index values, etc.) but
generate no object code.
Example 1 : Typical organization of a program
COMMON
TWa
C1
CDS
RES
DATA
FIN
LOCAL
LDS
RES
DATA
FIN
C2
16
1
2
&FO
common
data
section
local
data
section
Section 1
SPROG
DEB
111-2
LPS
LDA
AND
RTS
FIN
LOCAL
=3
C2
DEB
program
section
4057 U
Example 1 : Typical organization of a program (continued)
LOCP
LDS
RES
DATA,l
DATA,l
DATA
RES
FIN
U
V
TAB
ATAB
PRINC
INIT
LPS
LDA
ADD
STA
CLS
CSV
FIN
END
2
28
31
ATAB
1024
local
data
section
Secti on 2
LOCP
U
= C1
TAB
SPROG
M:EXIT
INIT
PRINC
program
section
End of file code (%EOD on card and paper tape).
Example 2 : Other possible special organizations
PROG
CDS
FIN
LPS1
LPS
FIN
END
PROG
LPS1
This LPS having no associated LDS cannot use
the local addressing mode; it must use the
genera I addressing mode
CDS
. .
FIN
LDS
LDS1
FIN
LPS
LPS1
LDS1
FIN
LPS2
LPS
LDS1
FIN
END
LPS1
These two LPS are both associated with the
same LDS. The local symbols are deleted at
the beginning of the next LDS. Nevertheless,
there are two distinct sections (two items in
the PRT).
The local base L being initially the same for
both sections, no mutual calls are allowed
(through C LS pseudo-instructions).
.
" 1-3
4057 U
Example 2 : Other possible special organizations (continued)
CDS
FIN
LDS1
LDS
This LPS having no associated LPS, it is only
accessible through indirect addressing via an
item of the CDS.
FIN
LDS2
LDS
FIN
LPS2
LPS
FIN
END
This LPS cannot refer to the LDS called LDS2,
since loca I symbols are deleted after every
occurence of an LDS pseudo-instruction.
LPS2
Example 3 :
First module
PROG CDS
RES
C1
DATA
RES
C2
C3
DATA
C4
RES
DATA
C5
FIN
16
2
4
D1
2
C2
Second module
PROG CDS
DUM
RES
16
C1
DATA 2
C2
RES
4
C3
DATA D1
C4
RES
2
DATA C2
C5
FIN
Third module
PROG CDS
RES
C1
DATA
C2
RES
C3
DATA
RES
C4
C5
DATA
FIN
DUM
16
2
4
D1
2
C2
Remarks
These CDS reflet each others.
The dummy CDS DUM do not
generate any ob ject code.
They use to satisfy the general
addressing modes and the references. Also they enable each
program to have in clear the
elements it uses.
--------------------- -------------------- -------------------- ---------------------------LDS1
D1
LPS1
DE B1
lDS
RES
DATA
FIN
LDS
LDA
ClS
ClS
CSV
FIN
END
2
C1
LDS1
D1
lPS2
lPS3
M:EXIT
DEB1
lPSl
--------------------- -------------------- -------------------- ---------------------------
" 1-4
4057 U
Example 3 :
. First module
Second module
LDS2
LOS
RES
02
DATA
RES
03
DATA
04
DATA
FIN
LPS2 LPS
DEB2 LOA
LOX
STA
RTS
FIN
END
LDS2
2
4
02
5
C2
C4
Remarks
Third module
03
04
LOS
RES
DATA
RES
DATA
DATA
FIN
DUM
2
4
5
C2
C4
LDS2
02
=2
Ch,x
The two program segments
LPS2 and LPS3 are linked to
the same data segment LDS2.
They are separely assembly,
but one of the two references
a dummy segment DUM whi ch
also uses to satisfy the local
addressing modes and allows
the programmer to have in
clear the elements he uses.
The DUM segment do not
generate any object code.
DEB2
LPS3 LPS
DEB3 LOA
LOX
STA
RTS
FIN
END
LDS2
04
=0
C4
DEB3
--------------------- -------------------- ------------------- ---------------------------After these three modules be linked, a executable IMT of the following forme will be obtain.
CDS
PROG
LOS
LDSl
LPS
LPSl
LOS
LDS2
LPS
LPS2
LPS
LPS3
~
Running
section
111-5. CONSTITUENTS OF A PROGRAM
•
Task Working Block (TWB)
The first sixteen words of the CDS are called the "Task Working Block" or TWB.
This 16-word area is reserved to the Monitor which may store therein the return address to the calling task,
as well as the caller's local data base (L) and the program indicators.
The Monitor may maintain in the TWB a pointer to the system's common data area (ZC).
All programs which require Monitor Calls must reserve 16 words at the beginning of their respective CDS.
This feature allows for monitor sections re-entry, the latters operating in the calling program.
111-5
4057 U
•
Program Relocation Table (PRT)
The sections are assigned through a section relocation double-word (SRD), which contains the initial values
of Land P with respect to G :
o
15
1= L - G
Section relocation double-word (SRD)
p = P- G
The PRT is made up of all the SRD of the program sections.
This PRT is stored in the locations immediately preceding G-address, thus the SRD of section no. n has an
address given by :
G - 4n
This table is built at linkage edition time.
Note:
The Monitor's PRT is pointed to by the contents of a fixed address as that of the micro-processor (address 12).
The PRT is the communication area between the different sections of a same program or between a program
and the Monitor (for the Monitor's PRT).
Context
I
I
Level
Indi cators
X
Pointer
E
A
G
I
L
P
\
IN
...................
pN
Ii
PRT (2 N words)
.·.0 ..............
pi
11
...............
, ..
pI
G'
TWB
\
(
Where Ii
= Li
- G and pi
= Pi
Initia I
secti on
- G
Structure of a program
111-6
!
CDS
J
Sections 1 throug h N
CTX
4057 U
Remark:
The CDS, which is accessible from any section of a program, constitutes an implicit communication area
between the sections.
•
De-activation word table or DeVice Table (DVT)
This 32-word table precedes in core memory the Context Pointer Table (CPT) which is also 32-word long.
A DVT word has the following format:
o
2
Trigger_-----J
Ena b Ie _---------4
3
14
15
-----------~~---------IT no. in the group
group no.
Arm
Bits 3 to 15 are also called "interrupt configuration".
The interrupt system and the DVT are described in Chapter II.
•
Context (CTX)
The context is the communication area between a priority level and an associated program. It groups seven
words:
Word 1
Status indicators
Word 2
Initial X va lue
Word 3
In itia I E value
Word 4
Initial A value
Word 5
Initia I G value
Word 6
Initia I L va lue
Word 7
Initial P value
The context is used for initializing and restarting a task, and for protecting its status when the corresponding level is activated or de-activated.
When activated, a task level defines in the context table (CTX) the specifi c pointer fo the associated
context. P-, l-, G-, A-, E- and X-registers, as well as the status indicators are loaded from the context
area and program execution begins at address P.
Conversely, when a level is interrupted by a higher priority level, or when it is acknowledged, the current
contents of P-, L-, G-, A-, E- and X-registers and of the status indicators are stored in the context area.
For further details, see DIT instruction description (Chapter VII).
111-6. SECTION CAllS
There are two kinds of sections:
-sections pertaining to a given program, accessible through a CALL SECTION (CLS).
- sections available to all programs: supervisor section or common library section, accessible through a
CALL SUPERVISOR (CSV).
111-7
4057 U
•
Program section call (CLS instruction)
During the execution of a CLS instruction, the processor:
- stores the contents of P (program address) and L (local data base) in the first two words of the called
section's loca I area (after subtracting G-base). These elements are required for "returning" to the task
and therefore must be saved.
- Loads P- and L-registers with the starting address and the loca I data segment address, respectively, of
the called section which may then be executed.
During the execution of a RTS (ReTurn Section), the processor:
- Restores in P- and L-registers the values which had been saved at the beginning of the called section's
loca I segment.
Note
When several sections of a program are separately assembled, if one contains a call to another, it is not
necessary to declare that the calling section is external to the module. This declaration is implicit and the
linkage editor performs the necessary checks.
The transfer diagram is given in the description of CLS instruction (Chapter VII "Instructions").
•
Supervisor ca II (CSV instruction)
The supervisor sections and the sections constitued by common sub-programs make up the "resident operati ng system" .
Hereafter, we shall call "system section" a section of the operating system.
A "system section" :
a) remains at the calling program's priority level;
b) processes both the calling task's data and its own local data;
c) is automatically executed in master mode.
Moreover, since a task is identified by its G-base value it is logical to associate the call with this base
rather than L-base.
In the CALL SUPERVISOR, i.e. in a system section, G has the same function as L in the CALL SECTION.
Paragraph (c) above, which is associated with class 0 addressing modes (see chapter V), implies paragraph
(b) since a system section may:
- access its own data in LD, LI and LlX addressing modes, it being understood that these data have absolute
oddresses and, therefore, system sections are resident with an implicit zero local base. (In this respect,
the operating system is a single program).
- access the calling task data in GD and GIX addressing modes, since the general base G remains that of
the caPing task.
When executing a RETURN SUPERVISOR instruction (RSV), the processor restores in L- and P-registers the
values which had been previously saved in the calling program's TWB.
The mode of the calling program is automatically re-established by RSV instruction.
The communication diagram of a supervisor call is given in the description of CSV instruction (Chapter VII).
111-8
4057 U
Example of re-entrant section programmation
M:MOVE module of MOB Monitor for moving a byte string .
• Main program
PRINC
CDS
RES
FIN
16
LDS1
CH1
CH2
LOS
TEXT
RE S, 1
FIN
"ABC DEFG HIJK L"
12
LPS1
DEB
LPS
LEA
XAX
LEA
LDE
CSV
FIN
END
LDS1
CH2
CH1
=12
M:MOVE
DEB
LPS1
~
TWB
I
Pa,amet." loading
• M:MOVE re-entrant module
FICTIV
TO
11
T2
T3
14
T5
T6
T7
N3
N2
N1
NO
CDS
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
FIN
SUPER
LOS
FIN
M:MOVE
LPS
SPA
BRU
RSV
R:MOVE
C
XEX
DST
DCX
BCF
LBR
SBR
BRU
DUM
4
1
1
1
1
1
1
1
1
1
1
1
1
SUPER
#NO
Dummy TW B. Genera tes no ob ject code.
Used for proper generation of instruction displacements
in the LPS.
Since a CSV does not alter G-base value, M:MOVE
will operate in the main program's TWB.
Entry point of the module for the CSV.
$+2
#TO
Entry point of the module for a branch instruction
=1
o
@#11,X
@#TO,X
C
111-9
4057 U
o
#T1
LDA
BRU
FIN
END
@
#
NO
111-7. SYSTEM'S MANAGEMENT CONCEPTS
•
Functions of the Supervisor
- Task management: connection at interrupt levels, queuing and "distribution" functions.
- Input/Output management: initialization on user's call, checking of interrupt-initiated transfers
termination, etc •••
- Resource management: reservation and release on user's call.
- Event management.
- Delay management.
- Etc .••
Operation and re-entrance of Supervisor ca lis
S.I
Supervisor
ITi
..
~-
S·I
Return
Return
- - - - - + - -.....1....-------------71DIT
ITi . . __
-- - - - .......---------------_.........
_ _ _ _ _ Supervisor's processing at task's level
The Supervisor operates at the level of the calling task and this provides supervisor context protection at
this level.
B,esides, for full re-entrance capability, variable data operated upon by the Supervisor must be stored in
an area specified by the calling task: this is the purpose of the TWB described in paragraph 111-5.
•
Data area management
• System common data area
In order that a relative address may always be positive with respect to any G-base value, this area is located in the upper portion of the memory.
It comprises a group of fixed-length blocks which are dynamically assigned on user's request.
To have the program relocatable with respect to this area, it is the address ZC of the whole common area
which the Supervisor stores in G + 6, in relative value with respect to G, the address of the actually
as .. igned block being provided in a register (preferably X) as a relative value with respect to ZC. This
Cl~C;'ess is assigned by the Loader.
111-10
4057 U
The task will address this block in GIX mode with:
- D = 6,
-(G+6)=ZC,
- (X) = Block address with respect to ZC.
To progress in the block, the task increments or decrements X-register.
This procedure has an obvious advantage:
When a program is dynamically relocated, e.g. after a swapping, the only action of the system is to
update (G + 6) contents with the new ZC relative address to provide the connection with its data, without
any attention from the user.
Thus, the main purpose of this area is :
- to provide communication between separate programs,
- to allow for dynamic relocatability of the programs.
•
Program common data area
Every program includes a common data section (CDS) accessible in general addressing mode. This addressing mode. This addressing being a Iways relative to G-base, the actua I location of the program may be
unknown to the user without any influence on the programmation •
•
Local data areas
Since every program section may have a local data area, the corresponding base must be updated at the
beginning of the section (when a called section is entered) or upon return to the calling section.
This updating is automatic and requires no attention from the programmer who needs only state the name
of the section to be executed.
The linkage editor builds a relative location table in which every section is defined by the relative
addresses of its entry point and local data segment.
Some programs may require a direct access to more than 256 bytes in a data segment; this is provided for
by instructions for incrementing and decrementing L-base, where by the direct access area is shifted. The
Assembler is made aware of such shifting by a BASE pseudo-instruction.
111-11
mitra 15
4.
Assembly language
The Assembler isa language translation processor which converts a source program, written in "symbolic
assembly language", into an object program.
The programmer is assisted in its task by the following convenient features:
- assembly "pseudo-instructions" for generating data of various kinds,
- possibi lity of sharing the job between severa I programmers (program divided into segments and sections),
- possibility of easily writing re-entrant sub-routines owing to full separation of data and work areas.
The source program is processed in a single assembly pass during which:
- every source line is read,
- symbols are entered into tables,
- relative addresses are assigned at the beginning of declared segments,
- pseudo-i nstructi ons a re executed,
- the "relocatable binary" (RB) object text is edited along with a directory of satisfied references, the
object listing and a list of errors which have been detected at this level,
- "forward" or downstream references, which cannot be solved by the Assembler, are actually processed
by the Linkage Editor.
MITRAS 1 Assembler requires the following minimum hardware resources:
- 4 K-words of core memory (including I/O processing), and
- a console typewriter (Teletype ASR33).
MITRAS 2 Extended Assembler requires an additional 4 K-word memory module.
Remarks:
1 • Hereafter the features which are available with. MITRAS 2 only are distinctly pointed out by a vertical
dotted line in the margin.
Pseudo-instructions which are not accepted by MITRAS I are underlined.
2. MITRAS 1 Assembler requires about 4800 bytes (without label table) thus leaving, under MOB basic
monitor, about 1000 bytes of table space, i.e. 100 common labels.
Source language instructions are of two kinds:
- Machine code instructions, which are each converted into a single machine word specifying an instruction executable by MITRA 15's internal logic. In the following they will be called "instructions".
- Assembly instructions which are command statements controlling the assembler either for assembly procedure, or for data or text generation. In the following they wi II be ca lied "pseudo-instructions".
IV-l
4057
U~
____________________________________________________________________
IV-1. SOURCE LINE FORMAT
IV-1 .1 . Instruction or pseudo-instruction line
An instruction or pseudo-instruction line has a maximum of four fields:
.. a label field:
Always beginning at column 1 and containing a 1 to 6-character symbol beginning with an alpha character
and ending with a blank column.
- a command field:
Beginning at the first non blank column after the label field (or at the first non blank column after column
1 when the label field is unused) and ending with a blank column. This field must contain a command
statement both for an instruction and a pseudo-instruction.
- an argument field:
Beginning at the first non blank column after the command field and ending with a blank column, except
if the first non blank column contains a special character "*" in which case this field is ignored as such.
The argument field cannot extend beyond column 57 with MITRAS I and column 72 with MITRAS 2.
- a comment field:
Beginning at the first column after the special character
"if".
IV-l .2. Comment lines
A comment line is a line the first non blank character of which is a special character ,.*,.
ignored by the Assembler but appear in the object listing.
These lines are
IV-l .3. Blank lines
Blank lines are accepted and treated as empty comment lines.
IV -2. BASIC CHARACTER SET
The Assembler accepts all the following characters:
- a Iphabeti c characters: letters A through Z and
..
11.11
.. numeric charact ers : digits 0 through 9 •
... special characters: blank
+- *
/ . , ( ) ,.
=
#
$ % &
@
etc.
Furthermore it accepts all characters recognized by the peripherals. These characters make up a subset of
EBCDIC.
No check is performed on the characters which are included in a comment field or a byte string.
IV-3. SYMBOLS
A s"mbol is an identifiable group of up to 6 alphanumerical characters, the first of which is alphabetical.
No olanK or special characters are allowed.
A svmbol is defined when it appears in the label field of a source line.
In ai i cases, a symbol identifies the source line to which it belongs.
IV-2
4057 U
It may also identify the memory address of the code generated by the source line. In such a situation, a
numerical value is assigned to the symbol and is equal to the most significant byte memory address.
IY-3.1. Pseudo-instructions prohibiting assignment of a value to the label
Those are:
GOTO, BASE, BND, DEF, REF, FIN, END, PAGE
A symbol may appear in the label field, but no value is assigned to it.
Its only purpose is to mark the corresponding line in the argument field of a GOTO pseudo-instruction.
IY-3.2. Commands for assigning an address value to the label
- Assignment commands:
the EQU pseudo-instruction provides for assigning a numerical value to the symbol in a label field.
- Generation commands:
Machine instructions
Generation of pseudo-instructions:
RES, DATA, GEN, TEXT, DO •
• Segmentation pseudo-instructions:
CDS, LOS, IDS, LPS, BASE.
Any symbol appearing in the label field of such a command is entered into the assembly symbol table and
an address value is assigned to it.
The address value is always relative to the beginning of the segment which contains the symbol in a label
field.
An address value specified in operand field of DATA and GEN pseudo-instructions will be relocated, at
linkage edition time, by the value of L or P base of the segment in which it has been defined, so as to
become relative to the genera I base G of the program.
In resident programs declared in Master Mode, the loader will generally relocate the address values by the
general base G, since, in that case, local mode indirect addresses must be absolute.
However, in a LOS, it is possible to force a label expression to remain relative to the base, even for a
program executable in Master Mode.
For this, the label expression must be preceded by the special character
"#" .
This procedure is allowed in a CDS, though it is basically ineffective.
IY .... 4. CONSTANTS
Data may be directly entered in assembly language as alphanumerical constants. Three types of constants
are permitted in statements:
IY-4.1. Decimal integer constants
A decimal integer constant is represented by a decimal integral numbtr'Of 5 digits or less, with or without
a sign:
Example:
+ 75
75
-75
IY-3
4057_U~
___________________________________________________________________
The maximum absolute value for an unsigned number is 2 16
-
1 = 65,535.
The constant generated by the Assembler is in pure binary form (in two's complement for negative va lues)
and occupies the area specified in the g'e~eration pseudo-instruction.
IV-4.2. Hexadecimal constants
A hexadecimal constant is represented by an integral hexadecimal number of 4 digits or less, preceded by
the special character "&".
Exo:~~ple:
&lA
&E3FF
iV -4.3. Character string constants
A character string constant is a sequence of alphabetical, numerical or special characters in quotation
marks. The internal representation of normalized characters is "EBC~IC".
A translation module included in all stand~rd monitors' provides for automatic translation ASCII·EBCDIC and
EBCDIC-ASCII, should they be required; this translation is performed by the input-output system.
Example:
"C HARACTER STRJN G"
A quotation mark is represented in the string by two consecutive quotation marks.
Example:
"NEXT""CHARACTER" represents: NEXT"CHARACTER
I'.
IV-5. EXPRESSIONS
An (:"':pression is made up of one or several symbols or constants combined through arithmetic
oP,e;a:to~~
,\r\ expression is represented by a single value which is computed by the Assembler or by the lin'k,age '"
Editor according to the rules specified in section IV-3.2.
,(
,-
An expression is said to be computable when its value may be determ i ned at the fi rst en counter; therefore,
•
it must contain no forward or exter~al references. ,"
t.
!
b"
. ~'
IV-5.1. 0eerators
I,.'
'f
I
The Assembler accepts the following operators:
"Minds" unary operator (example:
-3)
S:Jbtraction operator (example: A-3)
+
Addition operator
WI· .::" the unary minus operator is followed by a constant, the Assembler generates the latter in pure binary
two': c:)mplement form.
:\,-5,'1.
TWO
Expression evaluation
kinds of expressions are to be consiClered
- label expression:
/",:'
A s',(mbol identifying a specific m!mory loca'tion whose addres!;'s !?'evalue of the label.
::'.lc(l
CC)'.:"
IV-4
(1 symbol may be reduced to •
+er va lue.
.'
special tharacter $ in whiA case it specifies the current location
4057 U
- Predefined symbol:
A predefined symbol specifies no memory location; its value is absolute and defined by EQU pseudo-instructions preceding its utilization.
- (Forward) reference
A forward reference is a symbol which has not yet been defined. It may be defined later on either by a
label, or through an EQU or REF pseudo-instruction.
- Conventional representations:
Elements of assembly language syntax are represented by their denominator contained between square
brackets (e.g. : :: = - < va lue>/ < va lue>
In this case, "ab" may be indentical with "-value" or "value".
Example 2 :
:: = /
In this case, "value" may be identical with "term" or "value" followed by "sign" followed by "term". This
is equivalent to the statement that "value" is a sequence of "term" separated by a "sign".
MITRAS I Version
: : = < constant> / :: = /
< Label expression>
:: = < label >/< label> < term>
:: = < reference>/<-reference>< sign>
< Sign> :: = + /
:: =< term>/-/
Predefined expressions are always computable by the Assembler. Some expressions may be-computable at
linkage edition time only.
M ITRAS 2 Version
< Constant> :: = < integral decimal constant>/< integral hexadecimal constant>
< Term> :: = < constant>/< predefi ned sym bol>
< Displacement> :: = < label >-
< Va I ue > :: = /< displacement>/ +/< term>
< Label expression> :: = < labe!>/ :: =< reference>/
< Predefined expression> :: = /-/< label expression>
: same structure as for "predefined expression", but any label may be replaced by an address
reference.
IV-5
4057 U
Predefined expressions are always computable by the Assembler. Some expressions may be computable at
linkage edition time only.
Remark:
A label may be reduced to the special character $ {current value of the location counter} but only as the
fi rst term of an expressi on.
Example of such label expressions:
$ +2
valid
2 +$
invalid
mitra
15
5.
Addressing modes
V-1. SYMBOLIC REPRESENTATION OF THE INSTRUCTIONS
V-1 .1 • Representation conventions
Hereafter the followi ng representation conventi ons wi II be used:
One of the terms between braces may be specified and excludes all others (possible terms are
stacked vertica IIy).
-
[]
The term between square brackets may be omitted being either optional or implicit.
The expression bounded by the end separator immediately preceding the ellipsis mark and the
associated begin separator may be repeated.
Examples:
[,0]
One term out of A, Band C must be specified, 0 is optional.
One term out of A, Band C must be specified, but A may be omitted when selected.
~ ~
[,B] ... , C ~ ...
The expression between braces may be repeated; in the first possible term, B element is optional but may
be repeated.
V-1 .2. Instruction representation
All instructions are represented in accordance with the following format:
[label]
OP
o
[,x]
o
o
,x
1
V-1
4057 U
Wherein:
OP
Operation code
D
Displacement
=
Immediate addressing (parameter) operand va lue = displacement
@
Indirect addressing
#
Relative addressing with respect to genera I base (C DS)
,X
Indexing
Remark
For instructions or pse'udo-instructions whose name has four characters, the first three only are used for
operati on code recognition purpose.
V-2. ADDRESSIN G MODE REPRESENTATION
V-2.1. Addressing class
MITRA 15 addressing capabi lities are adapted according to the various instruction operation codes.
Addressing functions may be classified into three main groups corresponding to three instruction classes:
•
Class 0 instructions
These instructions control the following operations
- register load and store operations
- fixed-or floating-point arithmetic operations
- logical operations
- byte string operations
- comparaison
•
Class 2 instructions
These are conditional or unconditional branch instructions.
•
Class 1 instructions
'" shift operations
- index operations
- base operations
- section or supervisor calls
- input/output operations
- register operations
- interrupt and interrupt masking operations
These three groups make up a very comprehensive instruction set which will be discussed later on after a
brief description of addressing forms pertaining to each type.
V-2
4057 U
The following conventions are used in the dicussion :
- L
Loca I base
- G
General base
- G'
Genera I base in slave mode or zero in master mode
- X
Index register
- P
Program base
- D
Displacement
- ()
Contents of
•
Class 0 addressing
Assembly
language
Mode
Direct, Local
DL
Indirect, Local
IL
Indirect, Loca I, Indexed
ILX
Addressing
function
IDENT
Byte, word or double-word
located in the first 256 bytes
of the loca I segment.
Y=(L)+D
@ IDENT
Byte, word or double-word
located anywhere and pointed
at through the loca I segment.
Y=G '+((L)+D)
@ IDENT,X
Element of a byte, word or
double-word array located
anywhere and pointed at
through the loca I segment.
Y=G '+((L)+D)+(X)
Byte, word or double-word
located in the first 256 bytes
of the common segment.
Y=(G)+D
Element of an array pointed
at through the common
segment.
Y=( G) +(( G) +D)+(X)
A l-byte operand is specified
in the instruction. This byte
may be extended on the left
by 8 leading zeroes, if
required.
(Y) = D
Y = (P)
Direct, General
DG
#
Indirect, General, Indexed
IGX
_ @#IDENT,X
Parameter or immediate
P
Addressed data
IDENT
=OPERAND
V-3
4057 U
Example of class 0 addressing
Common segment
loca I segment
(l) _ __
(G) _ __
SCAl
CSCAl
INFO 1
INFO 6
ATAB
CTAB
ACTAB
I(
POINT
APOINT
APOINT
INFO 2
- f---
I--
X)
ACTAB
ATAB
(X)
INFO 5
INFO 3
INFO 5
I
r~·OA
I OlO
Instruction
Operand
Instruction
#CSCAl
INFO 6
lOA
SCAl
INFO 1
@#CTAB, X
INFO 5
lOA
@POINT
INFO 2
lBR
@TAB, X
INFO 3
Instruction
lOA
V-4
Operand
=
INFO 4
Operand
INFO 4
4057 U
•
Class 1 addressing
This class includes:
- either instructions without actual operand, i.e. register contents swapping, section end, etc .••
- or instructions whose operand is generally known (possibly through an unknown modifier) at programmation
time: shift, increment, index, etc.
The following modes are permitted:
Assembly
Language
Mode
Operand
Addres~ing
functi on
Parameter or immediate
p
==PARAM·
Operand defined by displacement va lue
(Y)==D
Y==(P)
Parameter, Indexed
PX
==PARAM,X
Operand defined by value plus X-register
contents.
(Y)==D+(X)
Y==(P)
Direct, Local
DL
IDENT
Operand located in the first 256 bytes of
the local segment.
Y==(L)+D
Remark 1 :
To simplify program writing, a number of symbolic instruction codes recognized by the Assembler specify
both the operation code and the displacement.
For example SRG, which is a register instruction, is specified through its displacement:
SRG
== 02
exchange A and E
SRG
== 04
A and X
SRG
== 06
E and X
SRG
==IC
-A--A
etc.
In actual practice, for the Assembler,
XAE
is equiva lent to SRG == 02
XAX
SRG == 04
XEX
SRG == 06
CNA
SRG == 1 C
etc.
In addition, MITRAS 2.Assembler recognizes 14 shift instruction mnemonics which specialize the two operation codes SHR and SHC.
V-5
4057 U
Examples:
SHR = &23
equiva lent to
SRCS = 3
(shift, ri g ht, circular, single)
SHR = &E8
equiva lent to
SRCD = 8
(shift, ri g ht, circular, double)
SHC = &OB
equivalent to
SLLD = 11
(shift, left, logical, double)
SHC = &4E
equiva lent to
SRLD=14
(shift, ri g ht, logical, double)
Remark 2 :
Instructions CLS and CSV may be used in two different ways:
a} The operand is a LPS name; the Assembler generates a blank word and the Linkage Editor determi.,es,
one the one hand, if the instruction to be generated is a CLS or a C5V according to the section type
(monitor or user section) and, on the other hand, the corresponding section number.
This is the normal case wherein the user is not concerned with the section number.
b} The operand is not a LPS name. These instructions are treated as any class 1 instruction, the three
addressing modes being availa~le.
Example for a program module
PROG
Ll
P1
L2
P2
L3
P3
L4
N UMSEC
P4
DEB
l..--..
CDS
RES
FIN
16
LDS
FIN
LPS
RTS
FIN
Ll
LDS
FIN
LPS
RTS
FIN
LDS
FIN
LPS
RTS
FIN
LDS
RES
DATA
FIN
LPS
CLS
CLS
LDX
CLS
CLS
CSV
FIN
END
P1
L2
P2
L3
P3
3
3
L4
Sl
=2
=1
= 2, X
N UM5EC
M:EXIT
DEB
P4
Ca II Sl
Ca II 52
~
---
~
Call S3
Ca II 53
Call monitor
Note: CLS NUMSEC is not available with MITRAS 1.
V-6
These uti lizations require the knowledge
of the section number in the program's PRT
4057 U
•
Class 2 addressing
Normally, instructions pointed at by a branch instruction belong to the same section as the branch instruction. However program section length is unlimited.
Four addressing modes are permitted:
Assembly
language
Mode
Addressing
functi on
Branch i nstructi on
Relative downstream
(plus) RP
LABEL
Any instruction within 512 bytes downstream
Y={P)+2D
Relative upstream
(minus) RM
LABEL
Any instruction within 512 bytes upstream
Y={P)-2D
Indirect, Local
IL
@LABEL
Any instruction pointed at through the
loca I segment.
Y=G '+({L)+D)
Indirect, General
IG
@#LABEL
Any instruction pointed at through the
common segment.
Y=G '+({G)+D)
In addition, an indexed unconditional branch instruction is also available. For indirect branch instructions,
the index is used for pre-indexation (more convenient for "Branch table" processing), contrary to data
indexation which is a post-indexation (more convenient for accessing element of an array).
Examples:
Program section
c:::
BRU
B2
BAZ
B1
@BL
BE
B3
BOT
B4
BRX
@#BC
@ TB
B5
~
Common
Local
BL
DATA
DATA
B3
.~
B4
TB
(X)
B5
~
;
V-7
4057 U
V-2.2. Permitted expressions
• ClassO
Predefined or reference expression
• Class 1
P
va lue
PX
value
DL
predefined or reference expression
• Class 2
RP
reference expressi on
RM
label expression
DL
predefined or reference expression
DG
predefined or reference expression
mitra
15
6.
Pseudo-instructions
VI-1. SOURCE TEXT SEGMENTATION
VI-1.1. General
The source text is translated by the Assembler into an object module in "relocatable binary" format (RB).
The Assembler can only satisfy the reterences to symbols of the assembled source text.
The Assembled modules are converted by the Linkage Editor into a complete program represented by a
"relocatable memory image" (RMI). All external references (section names) between program modules are
then sa ti sfi ed .
The RMI is loaded into core by the Loader starting from a general base address G which is only defined at
loading time.
VI-1 .2. Source text
The source text is the assembly unit. It comprises one or several segments and must be terminated by an
END pseudo-i nstructi on.
Source
Module
MITRAS
1 or 2
MITRAS
I or II
Linkage
editor
RB module
copied in the
library
RMI
program
VI-i
4057 U
VI-l .3. Common data section
If the assembly module is to include an actual or dummy common data section (COS), the latter must always
be declared before any other segment of the assembly module.
VI-l .4. Sections
Every section must include an executable local program segment (LPS) which defines the section. A local
data segment (LOS) is normally associated with aLPS.
When such a LOS is actua IIy defined in the same module as the LPS, it must precede the latter in the source
text. Several LPS may be associated with a single LOS and the number of sections is equal to the number of
LPS.
VI-l.5. Identifier scopes
Identifiers may be classified into internal labels defined within the assembly module, and external labels
declared through OEF and REF pseudo-instructions.
•
Internal labels
• Labe Is defi ned in the COS
These labels are defined for the whole assembly module and may be referenced from any segment. However,
they connot be redefined as local labels without causing a "double definition" error.
• Labels defined in a LOS
These labels are defined until the appearance of another LOS pseudo-instruction.
They may be referenced from the C OS, from the LOS itself and from any LPS following the LOS in which the
label is defined, up to a new LOS.
• Labels defined in aLPS
They may be referenced from LPS itself, from the COS or from the associated LOS (which normally precedes
the LPS).
•
Externa I labels
A label is said to be "external" when it has a meaning outside the assembly module in which it has been
defned (where it appears in label field).
Thus, being known at linkage edition time, it provides a convenient link to other modules without resorting
toa COS {actual or dummy} or toa Call Section.
A label is external when declared through a OEF pseudo-instruction which must appear in the segment in
whi ch the label has been defined.
The external label may be referenced in another module provided that it is declared in the latter module
through a REF pseudo-instruction. The REF pseudo-instruction must appear in the segment where the external
label is used.
The "external" status does not modify the notions of "common" or "local" labels, for the Assembler.
When a label belonging to the COS is to be declared in a REF pseudo-instruction, it must be preceded by
a u#" special character.
VI··2
4057 U
Example:
REF #LAB1, #LAB2, #LAB3
Do not confuse external labels and segment names. The latters, though known outside the assembly module
at linkage edition time, are only accessible through Call Section or Call Supervisor.
Example:
PROG
ETlQO
LDSl
ETlQl
LPSl
z
LDS2
CDS
DEF
RES
DATA
FIN
LDS
RES
DEF
REF
DATA
DATA
FIN
LPS
REF
LDA
FIN
END
LDS'
REF
REF
X
ETlQ2
ETlQ3
DATA
DATA
DATA
FIN
LPS2
y
LPS
LDA
STA
LDA
FIN
ETIQO
16
1
8
ETlQl
ETlQ3
2
ETlQ3
LDS1
ETlQ2
ETIQ2
Z
ETlQl
#ETIQO
ETlQl
o
4
LDS2
#ETlQO
X
ETIQ1
X
Remark:
It is important to remember that, for local external labels, the displacement is generated relative to the
LDS of the section containing the corresponding DEF but used relative to the LDS of the section containing
the corresponding REF.
VI-l .6. Location counter
The location counter contents is a byte address with a maximum value of 2 16
-
1 = 65535.
The location counter is symbolically represented by the special character "$".
This counter is reset to zero at every segment declaration, so that a II references ca Iculated at assembly
time are always relative to the starting address of the declared segment.
VI-3
4057 U
YI-l .7. Segmentation pseudo-instructions
These pseudo-instructions define the assembly module structure in terms of sections and segments.
They are:
- Common data section: CDS
- Loco I data segment: LDS
- Indirect data segment: IDS
- Executable local program segment: LPS
~
End of segment: FIN
- End of module: END
Every segment opened by a segmentation pseudo-instruction must conclude with a FIN pseudo-instruction •
•
CDS/FIN pseudo-instruction
This pseudo-instruction identifies the common data section CDS.
Format:
Label
Command
Argument
< Name>
CDS
[DUM]
[< label>]
FIN
·
Result:
- The location counter is reset.
- All labels may be referenced form the module declared sections.
- If DUM option is specified, no code is generated and the section is dummy •
•
LDS/FIN pseudo-instruction
This pseudo-instruction identifies a local data segment LDS.
Format:
Label
[]
Command
LDS
···
·
FIN
Argument
[DUM]
Result:
- The location counter is reset.
- "Nome" defined in label field is an implicit external definition.
- If )UM option is specified, no code is generated and the segment is dummy.
VI-4
4057 U
•
I DS/F IN pseudo-i nstructi on
This pseudo-instruction identifies an indirect access data segment within a LOS or CDS. This segment is
such that any label located between the IDS pseudo-instruction and the associated FIN pseudo-instruction
is defined in relative value within the declared indirect segment.
Format:
i
Command
Argument
IDS
[DUM]
[
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File Type : PDF
File Type Extension : pdf
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PDF Version : 1.6
Linearized : No
Create Date : 2016:02:22 17:21:37Z
Creator : Compagnie Internationale pour l'Informatique, 1973
Keywords : 4057, U/EN
Modify Date : 2016:06:29 20:26:33-07:00
XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19
Creator Tool : Compagnie Internationale pour l'Informatique, 1973
Metadata Date : 2016:06:29 20:26:33-07:00
Producer : Adobe Acrobat 9.0 Paper Capture Plug-in
Format : application/pdf
Title : Mitra 15. Reference manual
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Instance ID : uuid:fa3e5d8b-b870-ee4a-b03d-b7e26516575c
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