420305239 001A_SCMP_Applications_Handbook Feb77 001A SCMP Applications Handbook

User Manual: 420305239-001A_SCMP_Applications_Handbook-Feb77

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SC/MP
Microprocessor
Applications
Handbook

~

National Semiconductor

Publication Number 420305239-001 A

SC/MP Applications Handbook
PREFACE
In conjunction with other support documents (listed below), this Applications Guide provides the user with
sufficient information to build, checkout, and utilize a wide variety of SC/MP-based systems. The information
is organized in capsule form; thus, the designer can, with minimum effort, expand, modify, or customize a given
application. The applications (chapter 2) are organized by class - Analog-to-Digital/Digital-to-Analog Systems,
K.eyboard/Display Systems, Multiprocessor Systems, and so on. Chapter I and the appendixes provide general
design data as regards the instruction set, addressing modes, input/output capabilities, interrupt structures, and
other applications-related features.
To complete your SC/MP support library, the following documents are presently available:
•

Data Sheet, ISP-8A/500D Single-Chip 8-bit MicroProcessor (SC/MP) - publication number
420305227-001. Provides electrical characteristics and functional overview of SC/MP chip.

•

SC/MP Technical Description - publication. number 4200079. Comprises comprehensive
descriptions of functional details, general interfacing characterisitcs, supporting hardware,
and systems information.

•

SC/MP Assembly Language Programming Manual- order number ISP-8S/994Y.Contains
comprehensive overview of the SC/MP Microprocessor as it relates to assembly language
programming and detailed descriptions of the assembly language, sundry source statements, programming techniques, and assembly input/output formats.

The information in this handbook is believed to be reliable; nevertheless, the National Semiconductor
Corporation does not assume responsibility for inaccuracies and the material presented is subject to change
without notice. Furthermore, such information does not convey to the user of semiconductor devices described
any license under the patent rights of the National Semiconductor Corporation or others.

February 1977 R

©National Semiconductor Corporation
2900 Semiconductor Drive
Santa Clara, California 95051

CONTENTS
Page

Chapter
PREFACE
1

SC/MP AS A GENERAL PURPOSE APPLICATIONS MICROPROCESSOR
INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
APPLICATIONS (lVERVIEW OF SC/MP . . . . . . . . . . . . . . . . . . . .
SC/MP Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sense Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Input/Output. . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-Bit Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12-Bit Address Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . .
Putting the Basics of SC/MP to Use. . . . . . . . . . . . . . . . .
SC/MP Hardware. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Accumulator Register. . . . . . . . .. . . . . . . . . . . . . . . . . .
Pointer Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extension Register. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SC/MP Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADDRESSING CAPABILITIES AND INSTRUCTION SET OF SC/MP.
Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PC-Relative Addressing. . . . . . . . . . . . . . . . . . . . . . . . .
Immediate Addressing. . . . . . . . . . . . . . . . . . . . . . . . .
Indexed Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . .
Auto-Indexed Addressing. . . . . . . . . . . . . . . . . . . . . . .
Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IMPLEMENTING A MINIMUM (LOW-COST) SC/MP SYSTEM. . . . . .
EXPANDING THE SECURITY-ENTRY SYSTEM. . . . . . . . . . . . . . .
BUFFERING AND INTERFACE CHARACTERISTICS OF SC/MP . . .

2

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1-1
1-1
1-1
1-1
1-2
1-2
1-2
1-2
1-2
1-2
1-3
1-3
1-3
1-6
1-6
1-8
1-11
1-11
1-11
1-11
1-11
1-11
1-12
1-16
1-16
1-19

TTL/MOS Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buffering SC/MP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TRI-ST ATE Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-19
1-19
1-21

CONCEPTS AND PRINCIPLES OF SC/MP INTERFACING
GENERAL CONCEPTS OF A/D AND D/A CONVERTERS.
SINGLE-INPUT ANALOG-TO-DIGITAL CONVERTER. . .
General Description. . . . . . . . . . . . . . . . . . . .
System Operation . . . . . . . . . . . . . . . . . . . . .
System Adjustments. . . . . . . . . . . . . . . . . . .
Software Considerations. . . . . . . . . . . . . . . . .

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2CI-0
2CI-0
2C 1-0
2C 1-0
2CI-2
2CI-2

CONTENTS (Continued)
Page
ANALOG-TP-DIGITAL CONVERSION USING MULTIPLE CONVERTERS. . . . . . . . . . . . . . . ..
General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
System Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

2CI-3
2CI-3
2C 1-3

System Adjustments. . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Considerations. . . . . . . . . . . . . . . . . . . . . . . . .
ANALOG-TO-DIGITAL CONVERTER USING MULTIPLEXED UNITS.
General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . .

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2CI-5
2CI-5
2CI-7
2C 1-7

System Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . ..
System Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

2C 1-7
2CI-7

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Software Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2CI-9
CONCEPTS FOR A LOW-COST SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2CI-I0
General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2C 1-1 0
System Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2CI-1O
INTERFACING A KEYBOARD TO SC/MP. . .
USING SC/MP AS A KEYBOARD SCANNER.
General Description. . . . . . . . . . .
System Operation. . . . . . . . . . . .
Software Considerations. . . . . . . .
USING SC/MP WITH A KEYBOARD (20-KEY)

........
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.... ....
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... .....
ENCODER

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2C2-1
2C2-1
2C2-1
2C2-1
2C2-3
2C2-7

General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
System Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Software Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

2C2-7
2C2-7
2C2-7

USING SC/MP WITH THE MM5740 (90-KEY) ENCODER . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
System Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN INTERRUPT-DRIVEN KEYBOARD/DISPLAY SYSTEM ... , . . . . . . . . . . . . . . . . . . . . . . . .

2C2-13
2C2-13
2C2-13
2C2-13
2C2-15

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2C2-15
System Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MODIFY Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XECUTE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

2C2-17
2C2-17
2C2-17
2C2-17

ABORT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2C2-17
Software Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2C2-18
System Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2C2-18
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2C2-37
2C2-37
2C2-37
2C2-37

MULTIPROCESSOR SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2C3-1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2C3-1
2C3-1
2C3-1

INTERFACING SC/MP WITH A BURROUGHS SELF-SCAN DISPLAY . . . . . . . . . . . . . . . . . . .
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iii

. CONTENTS (Continued)
Page

Chapter
INTERFACING A SCjMP SYSTEM WITH A CASSETTE RECORDER . . . . . . . . . . . . . . . . . . . . . •
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operator Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Software Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2C4·1
2C4-1
2C4-2
2C4-2
2C4-5

INTERFACING SCjMP WITH A SEIKO PRINTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2C4-13
General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....... 2C4-13
System Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2C4-16
Software Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2C4·17

•

APPENDIX A.
APPENDIX B.
APPENDIX C.
APPENDIX D.
APPENDIX E.

CLOCK CONSIDERATIONS FOR SCjMP . . . . . . . . . . . .
ADDRESS ASSIGNMENTS AND DECODING METHODS.
SCjMP INTERRUPT SYSTEM. . . . . . . . . . . . . . . . . . . .
MATH ROUTINES. . . . . .. . .. . . . . . . . • . . .. . . . . .
IMPLEMENTING PROGRAM DELAYS FOR SCjMP. . . . .

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A-I
B-1
C-l
0.1
E-l

LIST OF TABLES
Table
1-1
1-2
1-3
1-4
2C2-1
2C4-1

Title

Page

Description of SCjMP Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-10
SCjMP Instruction Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-12
Instruction Execution Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-13
Symbols and Notations Used to Express Instruction Execution. . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-14
Alphanumeric Characters and Corresponding Hex-Input Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2C2-37
Cassette Recorders Used for Accuracy and Reliability Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2C4-1

LIST OF ILLUSTRATIONS
Figure
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
1-9
1-10
2Cl-1
2CI-2
2CI-3
2CI-4
2Cl-5
2Cl-6
2Cl-7
2CI-8

Tide
Basic Functions of SCjMP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU Architecture and Pinouts of SCjMP .......................................... .
40-Pin SC/MP Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCjMP Timiflg (Based on I-MHz Crystal) and Processing Sequences . . . . . . . . . . . . . . . . . . . . . . . .
SCjMP Program Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Minimum Security System Using SC/MP and PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Expanded Security System Using SC/MP, PROM, a 4-by-l0 Decoder, and Miscellaneous Components ..

.
.
.
.
.
One Method of Buffering Data, Address, and Control Lines of SCjMP ...................... .
TRI-STATE Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
One Method of TRI-ST ATE Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Principles of Analog-to-Digital/Digital-to-Analog Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-Converter Analog-to-Digital System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Timing Summary for Single-Converter System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flowchart and Program Listing for Single-Converter System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiple-Converter Analog-to-Digital System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flowchart and Program Listing for Multiple-Converter System . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog-to-Digital Converter System Using Multiplexed Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flowchart and Program Listing for Analog-to·Digital Converter System with Multiplexed Inputs ......

iv

Page
1-1
1-4
1-8
1-9
1-15
1-17
1-18
1-20
1-21
1-22
2CI-O
2C I-I
2CI-I
2Cl-2
2CI-4
2CI-5
2CI-8
2CI-9

LIST OF ILLUSTRATIONS (Continued)
.poapre
'2CI-9
2CI-IO
2C2-1
2C2-2
'2C2-3
2C2-4
~C2-S
J~'

~C2-6

:2C2-7
2C2-8
2C2-9
2C2-IO
2C2-11
t·
:2<:2-12
·2C2-13
2C2-14
2C2-15
.2C2-16
2C2-17
2C3-1
2C3-2
2C3-3
2C4-1
2C4-2
2C4-3

Title

Page

Low-Cost Converter System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2C 1-12
Flowchart and Program Listing for Low-Cost Converter System . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Cl-13
Using SC/MP as a Keyboard Scanner. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2C2-2'
Flowchart for SC/MP Interfaced with a 6x8 Keyboard Matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2C2-3
Program Listing for SC/MP Interfaced with a 6x8 Keyboard Matrix . . . . . . . . . . . . . . . . . . . . . . . .. 2C2-4
Using SC/MP with a Keyboard (20-Key) Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2C2-8
Using Sense B of SC/MP to Input Keycode Data-Flowchart and Program Listing. . . . . . . . . . . . . . .. 2C2-9
Using Keyboard as Interrupt Device (via Sense A)-Flowchart and Program Listing . . . . . . . . . . . . . . . 2C2-11
Interfacing SC/MP with the MM5740 (90-Key) Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2C2-14
Interrupt-Driven Keyboard/Display System-Block Diagram and Memory Map . . . . . . . . . . . . . . . . . . 2C2-16
Flow Diagram for Interrupt Service Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2C2-22
Flow Diagrams for READ, MODIFY, XECUTE, and ABORT Subroutines . . . . . . . . . . . . . . . . . . . . . 2C2-23
Flow Diagrams for G4HEX and G2HEX Subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2C2-24
Flow Diagrams for SCAN/MUXDIS and DONE Subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2C2-25
Program Listing for Interrupt-Driven Keyboard/Display System . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2C2-26
Interrupt-Driven Keyboard/Display System-Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 2C2-36
SC/MP Interfaced with Burroughs Self-Scan Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2C2-38
Flowchart for Control and Moving-Message Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2C2-39
Program Listing for Control and Moving-Message Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2C2-40

2C4-6
2C4-7
2C4-8
2C4-9
2C4-10

Using SC/MP in a Multiprocessing System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2C3-2
Flowchart for Multiprocessing System and Program Listing for KITBUG . . . . . . . . . . . . . . . . . . . . .. 2C3-3
Program Listing for Burroughs Self-Scan Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2C3-12
Cassette Recorder Interfaced with SC/MP System-Block Diagram and Message Format. . . . . . . . . . .. 2C4-1
Decoding and Memory-Interface Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2C4-3
Cassette-to-SC/MP Interface Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2C4-4
SC/MP-to-Cassette Interface-Write and Read Flowcharts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2C4-5
SC/MP-to-Cassette Interface-Program Listing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2C4-6
SC/MP Interfaced with Seiko Digital Printer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2C4-14
Column/Character Relationships and Timing for One Print Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . 2C4-15
Memory Allocations for Printer Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2C4-16
Summary and Detailed Flowchart for SC/MP-to-Printer Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 2C4-18
Program Listing for SC/MP-to-Printer Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2C4-19

A-I
A-2
A-3
A-4
B-1
B-2
8-3
B-4
8-5
Col
C-2
C-3

Connecting Capacitor or Crystal to SC/MP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator Frequency versus Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using External Clock for SC/MP Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. •
Alternate Methods of Generating External Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Using External Logic and Spare Address Lines to Select RAM/PROM Memory or Input/Output Peripherals
Using 2-by-4 Decoder to Select Memory and Input/Output Peripherals . . . . . . . . . . . . . . . . . . . . . . .
Using Address Bits 12-15 and 4-by-16 Decoder to Select anyone of 16 Input/Output Peripherals . . . . .
Using Read/Write Strobes to Implement Address Decodes . . . . . . . . . . . . . . . . .' . . . . . . . . . . . . . . .
Using 6-Bit Bus Comparators to Select Peripherals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SC/MP Interrupt/Instruction Fetch Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using SC/MP and a Priority Encoder to Implement a Multilevel Interrupt System . . . . . . . . . . . . . . . .
Flowchart and Program Listing for Multilevel Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2C4-4
2C4-5

v

A-I
A-I
A-2
A-3
B-1
B-4
B-S
B-7
B-8
C-I
C-2
C-4

Chapter 1
SC/MP AS A GENERAL PURPOSE APPLICATIONS MICROPROCESSOR

INTRODUCTION

APPLICATIONS OVERVIEW OF SC/MP

This document defines the internal architecture, the pinouts,
and the interfacing techniques of the SC/MP microprocessor
from an applications point-of-view; it is also addressed to
the concepts, principles, hook-up detail, and general implementation procedures that relate to the many applications
for which SC/MP is suitable. It is assumed that the user of
this document is somewhat familiar with SC/MP hardware
and software. If additional information is required in either
of these areas, the following support documents are available:

SC/MP is a single-chip 8-bit microprocessor with a I6-bit
addressing capability that provides the user with a simple,
cost-effective, and general-purpose tool for implementing a
wide range of applications. The basic functions of SC/MP
are shown in figure 1-1. The following sections are addressed
to the purpose and use of these basic functions as they relate
to the broad spectrum of SC/MP applications.
SC/MP Timing

• Data Sheet, ISP-8A/500D Single-Chip 8-bit Microprocessor (SC/MP) - publication number
420305227-001. Provides electrical characteristics
and functional overview of SC/MP chip.
• SC/MP Technical Description - publication number 4200079. Comprises comprehensive descriptions of functional details, general interfacing
characteristics, supporting hardware, and systems
information.
• SC/MP Assembly Language Programming Manualorder number ISP-8S/994Y. Contains comprehensive overview of the SC/MP Microprocessor as it
relates to assembly language programming and detailed descriptions of the assembly language, sundry
source statements, programming techniques, and
assembly input/output formats.

For applications where timing is not particularly critical,
only a capacitor is required for the clock - all other timing
circuits are an integral part of the chip. If the application
requires precision clock control, the capacitor can be replaced with a crystal - shown connected by broken lines in
figure I-I. In either case, no external timing circuits (clock
drivers, phase splitters, buffers, and so forth) are required.
Refer to appendix A for information on using a capacitor
or a crystal, and for external clock considerations.
Sense Lines
SC/MP uses two sense lines (Sense A and Sense B) as its
"eyes" to see what is happening external to the processor;
the sense inputs shown in figure 1-1 are an integral part of
the chip. Under program control, either or both sense lines

r--ll~-..,
I CRYSTAL I

I CAP~~ITOR I
I

I

1-_ _' "

_ _ _ SENSEA
SENSE
INPUTS

_ _ _ SENSEB

s

SERIAL
INPUT

8·BITDATA

C'-

MEMORY

M
p

SERIAL
OUTPUT

EXTERNAL
CONTROL
FLAGS

INPUT/OUTPUT ANO MEMORY
CONTROL (NAOS, NWDS, NRDS
AND OTHERSI

ADORESS

_1-------1

NS10524

Figure 1-1. Basic Functions of SC/MP

1-1

can be examined and a decision based on the logic state of
one or both inputs can be made.

Refer to the SC/MP Technical Description for details of
DMA operation.)

The Sense A line serves a dual function in that it is used as
the interrupt input; when Sense A is used as an interrupt,
SC/MP can monitor asynchronous events while running
other programs. (Refer to appendix C for implementation
detail of SC/MP interrupts.) In certain applications, the
Sense A line can also be used for polling.

12-Bit Address Bus
SC/MP provides 12 dedicated address lines (AD 00 through
AD 11) that are internally latched - an applications feature
that can save much external logic. As previously indicated,
the 4 most significant address bits (AD 12 through AD 15)
are time-multiplexed on the 8-bit data bus; thus, a SC/MP
system can be expanded easily to 65,536 bytes of memory.

Serial Input/Output

Power Requirements

The serial interface capability of SC/MP is provided by a
single 8-bit register (the Extension Register) and a "ninthbit" output latch for the least significant digit of the word.
The serial input/output capability is especially useful for
Teletype@ applications, since the Teletype data are in 8-bit
format - a parity bit plus a 7-bit code. The serial interface
is also cost-effective in inexpensive analog-to-digital systems,
X-V plotters, display systems, data-acquisition systems, and
a host of other applications where inputs are generated in
serial order and the output device can be driven serially.

For direct interface with TTL and MOS devices, both +5volt and -7-volt sources are required. From an applications
viewpoint, it is advantageous to use low-power TTL and
MOS devices, since the SC/MP interface can be implemented
without buffering.
Putting the Basics of SC/MP to Use
Before looking at the internal architecture of SC/MP, let us
first see how an applications concept can be developed by
using nothing more than the basic features just described
and some simple software. Consider a "fire alarm system"
with a fire-sensing device connected to the Sense A/interrupt
line. The interrupt capability of the Sense A line is enabled
by software and, or. each instruction fetch to memory, the
interrupt input is interrogated. As long as there is no fire,
the interrupt status does not change and SC/MP stays in the
main program. If a fire occurs, the interrupt input becomes
active (high), and on the next instruction fetch, SC/MP is
directed to another program; this program is written by the
user and is called an interrupt service routine_ The interrupt
service routine can be written to serve any or all of several
functions - turning on the fire alarms, playback of prerecorded evacuation procedures and perhaps opening emergency exits, turning on the sprinkler system, calling the fire
department, and so on. All of these functions can be performed by software control of flags 0,1, and 2. For instance,
the alarm system and playback of evacuation procedures
might be activated simply by setting flag 0 from a logic '0'
to a logic '1'. A series of pulses on flag 1 might be used to
open one or more emergency exits and to turn on the
sprinkler systems. Flag 2 might be used to activate an automatic phone dialer - a coded pulse train could indicate the
number to be dialed. The phone systems could also be activated and the dial-up code transmitted via the serial input/
output port of SC/MP. Except for memory and external
interface circuits, all hardware required to implement the
fire control system is resident in the SC/MP chip; thus, optimal cost-effectiveness is obtained.

Control Flags
Discrete control of events that occur external to the microprocessor are provided by three control flags (0, 1, and 2);
these TTL-compatible outputs are built into· the SC/MP
chip. Under software ~ontrol, each flag output can produce
pulses or fixed voltage levels; thus, lamps, motors, relays,
and other similar devices can be serviced as required by the
application. Since any combination of the flags can be set
with a simple series of instructions, there is a significant savings in external decoding logic.
8-Bit Data Bus
The 8-bit data bus provides a means of bidirectional data
transfer between the Accumulator, which is internal to
SC/MP, and standard memory components or peripheral devices, which are external to SC/MP. Valid input data are expected to be on the bus at negative read-strobe (NRDS)
time, whereas output data are valid on the bus at negative
~te-strobe (NWDS) time. The four most significant address
bits (AD 12, AD 13, AD 14, and AD 15) and four input/
output status signals (RFLG, IFLG, DFLG, and HFLG) are
multiplexed on the data bus and appear at negative addressstrobe (NADS) time; if the application requires, the address
and status signals can be externally latched. (Note: In applications that use Direct Memory Access (DMA), data
transfers between memory and a peripheral can be made
without entering the data port of SC/MP; that is, SC/MP
does not actively participate in the actual transfer of data.
® Registered trademark of the Teletype Corporation.

1-2

designated Pointer Register - say, PI. Now, when an 'LD I'
Instruction is executed, SC/MP is instructed to load 8-bits
of data from the external device whose address is specified
by the contents of PI. Another pointer - P3, for example could be loaded with the memory location in which the
data are to be stored, that is, an 'ST 3' Instruction. When
this instruction is executed, the foregoing data are transferred from the Accumulator to the memory location specified by P3.

SC/MP Hardware
In the preceding section, SC/MP is defined in basic terms
with little emphasis on the internal architecture of SC/MP.
To view SC/MP from a general-purpose applications perspective, a study of the CPU architecture and a description
of the pinouts are in order. Figure 1-2 shows the functional
subdivisions and identifies each input/output pin of the SCI
MP chip. In subsequent sections, all functions and pinouts
that are related directly to applications are described in
terms of both hardware and software.

From a programming point-of-view, certain conventions
regarding pointer register assignments are beneficial; some
typical assignments are as follows:

Accumulator Register
Almost any data movement within the SC/MP system involves the 8-bit Accumulator; thus, the Accumulator is used
in every type of application. In terms of interface and software control, functions of the Accumulator can be summarized as follows.

~

pointer Register I - - - - - - - - - ROM Pointer
Pointer Register 2 - - - - - - - - - RAM Pointer
Pointer Register 3 - - - - - - - - - Subroutine Pointer

As previously indicated, the low-order or the high-order byte
of any Pointer Register can be exchanged with the Accumulator; also, the 16-bit content of the Program Counter (PC)
can be exchanged with any of the other Pointer Registers.
Not only are these exchanges useful in implementing the
addressing schemes of SC/MP, the 16-bit exchange is particularly useful in executing subroutine calls. For example,
using the foregoing convention, Pointer Register 3 is loaded
with the memory location that just precedes the subroutine
address; that is, if the subroutine address is X'FEI5, then,
Pointer Register 3 is set to X'FEI4. The content ofP3 now
is exchanged with the Program Counter, and since the PC
is incremented before the instruction fetch, the instruction
at address X'FE15 is executed. During subroutine nesting,
it is important to save the contents of P3 because they are
the only return link to the basic program. This is easily
accomplished via the Accumulator and two store instructions - one for the low-order byte and one for the highorder byte. The following examples assume that SUBR is
the label on the first instruction of the subroutine.

• Data transfers to and from memory are made via
the Accumulator.
• Under software control, the low-order or high-order
data byte of any Pointer Register can be exchanged
directly with the contents ofthe Accumulator; data
can also be exchanged between the Extension Register and the Accumulator.
• Data can be copied from the Status Register to the
Accumulator and vice versa.
• Results of all operations performed by the Arithmetic Logic Unit are left in the Accumulator.
Pointer Registers
Except for Pointer Register 0 (PO), which is dedicated for
use as the Program Counter (PC), the remaining three Pointer
Registers (PI, n, and P3) are available for addressing memory and other peripheral devices. In a given application, a
Pointer Register might be used as follows: 16 bits (2 bytes)
of address data are transferred via the Accumulator to a

1-3

I

BUS
ACCESS

BREO

(5

ENIN

<3 "

ENOUT< •

"
",

WRITE DATA
STROBE

I

NRST

It.
INPUT /OUTPUT
CONTROL

4-MSB
MULTIPLEXED
ADDRESS

"-

READ DATA
STROBE

NRDS ( 2
CONT (

..........

ENABLE OUTPUT

ADDRESS READY
STROBE

NADS (39
NWDS (

ENABLE INPUT

WAIT

NHOLD( •

DATA
INPUTI
OUTPUT

~

BUS
REOUEST

J

I

J

.....

I

PROGRAM COUNTER
(POINTER REGISTER 110)

l
i

k•••

--'I

POINTER REGISTER 111

....J
I

POINTER REGISTER 112

L

ii:

OSCILLATOR
AND
TIMING
GENERATOR

(37

X2 (3B

>----v..
(.0 >-----v

o•

.

J

I

~.

<

r--~~~II:S
INSTRUCTION
DECODE AND CONTROL

•••••••

4-BITS
INPUTIOUTPUT
STATUS

(13

~

- CONTROL
OUTPUTS

22}-

t

J

~

·i .}) . i/ .. i ...·.I.:..I'
NS10525

Figure 1-2. CPU Architecture and Pinouts of SC/MP

SUBROUTINE JUMP
SUBR 1
FE14
C414
33
C4FE
37
3F
SUBROUTINE RETURN
3F

LDI
XPAL
LDI
XPAH
XPPC

SUBR-1
L(SUBR 1)
P3
H(SUBR 1)
P3
P3

;LOAD LOWER SUBROUTINE ADDRESS
;TRANSFER LOWER TO P3L
;LOAD UPPER SUBROUTINE ADDRESS
;TRANSFER UPPER TO P3H
;EXCHANGE PC AND P3

XPPC

P3

;RETURN FROM SUBROUTINE EXCHANGE

If multilevel subroutines are used, the current contents of the Pointer Register should be saved on the top of the stack and
should be restored upon return from the subroutine.
C414
33
CEFF
C4FE
37
CEFF
3F
C6FF

LDI
XPAL
ST
LDI
XPAH
ST
XPPC
LD

L(SUBR 1)
P3
@-1(P2)
H(SUBR 1)
P3
@-1(P2)
P3
@1(P2)

37
C601
33

XPAH
LD
XPAL

P3
@1(P2)
P3

;LOAD LOWER SUBROUTINE ADDRESS
;TRANSFER TO P3
;SAVE P3L ON STACK
;LOAD UPPER SUBROUTINE ADDRESS
;TRANSFER TO P3H
;SAVE P3H ON STACK
;JUMP TO SUBROUTINE
;RETURN FROM SUBROUTINE, LOAD
;P3H F ROM STACK
;TRANSFER TO P3H
;LOAD P3L FROM STACK
;TRANSFER P3L FOR RETURN TO
;CALLING SUBROUTINE

contents of the Pointer Register are exchanged with the
To implement multilevel (nested) subroutines, a memory
"stack" is required. In accordance with the foregoing assignments, Pointer Register 2 can be used as the stack pointer
in RAM. The address loaded into P2 points to the top of
the stack; this address is a location in read/write memory_
contents of the Program Counter. As a result, the next instruction to be executed will be at the location addressed
by the expression. The Pointer Register will contain the address of the XPPC Instruction, allowing a subroutine return
to the instruction that follows.

A subroutine call can also be implemented via the Jump to
Subroutine Instruction (JS). The SC/MP assembler treats
this pseudo instruction the same as any other assemblylanguage statement except that, in this case, one or more
machine-language instructions are generated. Following is
an example:
JUMP TO SUBROUTINE (JS)

Operation

Operands

Format:

JS

ptr, expression

Memory:

7 bytes

Generated Code:

LDI
XPAH
LDI
XPAL
XPPC

If P3 is used as a subroutine pointer and its contents are not
disturbed, the subroutine can be called repeatedly without
reloading P3. The following setup shows how this can be
accomplished.

H(expression)
ptr
L(expression)-1
ptr
ptr

SIN:

•
•

When a Jump to Subroutine is invoked, the code generated
results in the setting of the specified Pointer Register (ptr)
to the value, expression-I. In calculating this value, the
memory page structure of SC/MP must be considered-refer
to SC/MP Assembly Language Programming Manual. The

•
3F
90FD

1-5

•

•
•

•
•

XPPC
JMP

P3
SIN

;SUBROUTINE RETURN
;FOR REENTRY

Extension Register

(XAE). Also a serial input/output can be implemented via
the Extension Register and the Serial Input/Output Instruction (SIO). Technically, the Extension Register can be
thought of as a 9-bit register; the additional bit in the output
latch is useful for implementing 'starts' and 'stops' while still
maintaining 8 bits of data in the register. A simple sequence
of instructions to initialize the output latch is shown below.

Basically, the 8-bit Extension Register is a backup for the
Accumulator as the Accumulator can be loaded from the
Extension Register with a Load AC from Extension Instruction (LDE) or the contents of the two registers can be exchanged with an Exchange AC and Extension Instruction

INITIALIZE:

o

LI
XAE

;LOAD ACCUMULATOR WITH ALL ZEROES
;TRANSFER CONTENTS OF ACCUMULATOR TO
;E-REGISTER
;SET OUTPUT LATCH TO ZERO

SIO

In the first Load Immediate Instruction (LI), the Accumulator is loaded with all zeroes; the second Exchange AC and
Extension Instruction (XAE) fills the 8-bit Extension Register with zeroes. Now, a Serial Input/Output Instruction
(SIO) is executed; this right-shifts the Extension Register
one position and brings the data at the serial input (SIN)
port into the most significant bit position, while shifting a
'0' into the output latch. (Note: The Extension Register
also can be used for addressing - refer to "Addressing
Capabilities and Instruction Set of SC/MP," located later in

2
3

PFLG:

LDI
CAS
LDI

4

CAS

this section, for additional information about addressing.)
Status Register
Conditional responses of SC/MP are based on the logic '0'
or logic '1' states of the 8 bits in this register. As shown in
figure 1-2, bits 0,1, and 2, respectively, are dedicated to control flags 0, I, and 2. One or more of the control flags are
set by loading a bit pattern into the Accumulator and then
copying the contents of the Accumulator to the Status Register; refer to series of instructions that follows.

01

;SET LSB OF ACCUMULATOR TO '1'
;SET FLAG 0 to '1'
;SET CONTENTS OF ACCUMULATOR
;EQUAL TO 0
;RESET FLAG 0 FROM LOGIC '1' TO
;LOGIC '0'

00

•

•
•
21
22

SFLG:

LDI

;SET BIT POSITIONS '0' AND '1' OF
;ACCUMULATOR TO LOGIC '1'
;SET FLAGS 0 AND 1 SIMULTANEOUSL Y

03

CAS

From the preceding instructions, it is readily seen that flags
0, 1, and 2 are software-controlled to produce a series of
pulses or a DC level at the output pins in whatever timing
sequence the application requires. The state of the flags can

be tested by copying the contents of the Status Register to
the Accumulator and by using a masking or bit-testing
operation - similar to the Sense A/Sense B program that
follows.

1-6

1
2
3

CSA
ANI
JNZ

12
13

CSA
ANI
JNZ

•
•
•
11

;COpy CONTENTS OF STATUS REGISTER INTO ACCUMULATOR
;MASK TO TEST SENSE A (81T 4)
;JUMP TO SASET IF SENSE A = 1
;CONTINUE PROGRAM IF SENSE A = 0

010
SASET

;COPY CONTENTS OF STATUS REGISTER INTO ACCUMULATOR
;MASK TO TEST SENSE 8 (81T 5)
;JUMP TO S8SET I F SENSE 8 = 1
;CONTINUE PROGRAM IF SENSE 8 = 0

020
S8SET

•
•

•

21
22
23

CSA
ANI
JNZ

;COPY CONTENTS OF STATUS REGISTER INTO ACCUMULATOR
;MASK TO TEST SENSE A AND SENSE 8 (8ITS 4 AND 5)
;JUMP TO ORSET IF SENSE A OR SENSE 8 IS EQUAL TO '1'
;CONTINUE PROGRAM IF 80TH SENSE A AND SENSE 8
;EQUALS '0'

030
ORSET

As shown in the foregoing code, the operational sequence
for testing each sense input is the same - the only difference
being that for Sense A the mask coincides with bit 4 and
that for Sense B it coincides with bit 5. When the two sense
lines are tested simultaneously (lines 21, 22, and 23), the
program does not immediately identify which sense line is
high but simply jumps to a location (ORSET) if either Sense
A or Sense B is set. This method of testing might be useful
in a polling system where time is critical and it takes too
long to check discretely each sense line every time the program circulates through the polling loop. By simultaneously
checking both inputs and by jumping to an,appropriate subroutine, software can be used to discriminate between Sense
A and Sense B - if, in fact, one of the sense inputs is high.

the interrupt system can be enabled, first, by setting bit 3
of the Accumulator to a logic '1' and, then, by executing a
copy AC to Status Instruction (CAS). In either case, with
bit 3 of the status register set to a logic 'I', the Sense A line
becomes an interrupt input - refer to appendix C for implementation detail of the interrupts. The interrupt system
can be disabled in either of two ways: (1) a Disable Interrupts Instruction (DINT) can be used to set bit 3 of the
Status Register to a logic '0', or (2) the interrupt system
can be disabled, first, by setting bit 3 of the Accumulator
to '0' and, then, by executing a Copy AC to Status Instruction (CAS). With bit 3 of the Status Register as a logic '0',
the Sense A input is now returned to the sense mode and its
function is once again identical to that of Sense B.

Many applications require an interrupt input, and the Sense
A line can be used for this purpose. The SC/MP interrupt
system is enabled simply by using an Enable Interrupt Instruction (lEN) to set bit 3 in the Status Register; alternately,

In some applications it may be desired t~ enable (or disable)
the interrupt line and to set (or pulse) one or more flags
with the same series of instructions. This can be done
as follows:

2
3

•
•
•9
10
11
12

CSA
ORI
(

009

;ENABLE INTERRUPT (lEN) AND SET FLAG
;COPY STATUS TO ACCUMULATOR
;ENA8LE INTERRUPT AND SET FLAG 0

' ...

CSA
ANI
CAS

OF6

;DISABLE INTERRUPT (DINT) AND RESET FLAG
;COPY STATUS TO ACCUMULATOR
;DISA8LE INTERRUPT AND RESET FLAG 0
;COPY ACCUMULATOR TO STATUS

'-7

Bits 4 and 5 of the Status Register correspond, respectively,
to the Sense A and Sense B inputs. If the Sense A line is
high, a logic '1' is read into bit 4 of the Status Register,
whereas if the Sense B line is high, status bit 5 is set to a
logic '1'. The following series of instructions show one way

to test the Sense A/Sense B status. The code in lines 1, 2,
and 3 tests the status of Sense A (in the sense mode) and
the code in lines 11, 12, and 13 tests the status of the Sense
B input; the code in lines 21, 22, and 23 shows how both
sense lines can be tested simultaneously .

....-~

Bits 6 and 7 of the Status Register provide arithmetic control; these control functions can be summarized as follows:
Bit 6 -

Overflow (OY); this bit is set if an arithmetic overflow occurs during an add instruction (ADD, ADI, or ADE)
or during a complement-and-add instruction (CAD, CAl, or CAE). Overflow is not affected by the decimaladd instructions (DAD, DAI, or DAE).

Bit 7 -

Carry/Link (CY /L); this bit is set if a carry from the most significant bit occurs during an add, a complementand-add, or a decimal-add instruction. The bit is also included in the Shift Right with Link (SRL) and the
Rotate Right with Link (RRL) Instructions. CY /L is input as a carry into the bit 0 position of the add,
complement-and-add, and decimal-add instructions.

SC/MP Pinouts

As shown in figure 1-3, SC/MP is housed in a 40-pin, dualin-line package. Two of the pins are used for input power
and two are used for timing; the remaining 36 pins are used
for control, addressing, and data input/output functions. In
a usual application, the 8 input/output pins (DB 00 through
DB 07) are connected to a common data bus and the 12 address pins (AD 00 through AD 11) are connecled to a common address bus. In conjunction with bus access and other
appropriate control signals, three functions are implemented:
(1) 8-bit data are input to SC/MP, (2) 8-bit data are output
from SC/MP, and (3) address and status information are
output from SC/MP. Timing detail and a description of each
pinout are described in other documents; however, as an
applications convenience, these functions are summarized,
respectively, in figure 1-4 and table 1-1.

NWDS

VGG

NRDS

NADS

ENIN

X2

ENOUT

X1

BREa

AD 11

NHOLD

AD10

NRST

CONT
DB 07
DB De
DB 06
DB 04
DB 03
DB 02

S
C
/

M

P

ADOS
AD 08
AD 07
AD De
ADOS
AD 04
AD 03
AD 02

DB 01

AD 01

DB DO

AD DO
SIN

SENSE B

$OUT

FLAG 0

FLAG 2

VII

FLAG 1

NS70526

Figure 1-3. 40-Pin SC/MP Chip

1-8

(~

I;
BREO

2OO'I1K

v.

-::----,L---------------------------fVJ----------------------------!-'OOm_ -I

,...----------------.."".J---------------------------

ITypicel)
NRST

ENOUT

"""'\.

rlm~.I-'"

NRDS/
NWDS

300._ --+----..rHl1~
II
~:~

al

~~

,~.-------~/J__t_____r

NADS ~/
NHOLD

I.

!

I

---------x.....~;.;.--'I-200-.----------'"

I

1

I

~ ,--4----1 r - -- - 1~r_---

\

Il~.

r"

V

~--300._

ENOUT

~

~I

NADS

_ _J.

:

______

~.~,

~I
~----------~:~/'

I

~(~

---!'::::~\~"i!:
,~.~
-~
--.

NOTES;
1. ENOUTnalwayl
low whill SCIMP il
ICtUilly utina bul,
that ii, ENIN input
MCI
BREO
.
. hi
__ • output

NRDS
OR
NWDS

2. When SC/MP il not
utina bul (BREa
output or EN IN
input lowJ, ENOUT
il held in .... ItI..

I

BREO

-.J'
--\~1,~::::::~,;~;:.:_;:::::::=+I:,~3OO;;;.'...:.:~::r_----------------'I

,~

HIGH FOR DURATION OF INPUTIOUTPUT CYCLE

I

ENOUT

_ ___'____________________..... I
1

Ityp;call

1 I

N~'______~~r,---------------------

NADS

250,,",~
I

I

I

SO.,", --' l-

I

AQOO-A011 _ _

-,

ADDRESS VALID

..

....

,~--~,~--------~I---------------I
I
I

250,,",-:----:
50.--1 t":''::.:;'-1 I~----~--~A~D~DR~E~SS~6-----~DATA
I

_

DBOO-DBOl

VALID I

STATUS VALID

___________

I

~~---~~

\i '

NRDS

INWDS IS ACTIVE HIGH
DURING INPUT CYCLE)

~5O....

I

I

Itypicall I

I

1---1500'1_

I

I
I

I

.1

I I

~ ~

!II
I

·1

4OO'IteC

I

.......-- 1200 '11K ----...

IJl l aIl R~ElI al lemW·.; lI f.~ m~ lI . J.lI ~: lI .~ lI...:~ lI...:'~· :-·X~-: ~i_\~: : ~: ~7~ :~ ~ ·_·" ~" _" ~':~:~ :~ ~·~ ~R~· ~DU~ :~:~m:~:~ ~.:;~ ':':~.~ ~;~ ~ ~:~:~:~ :~ ':~·U~·T~C~Y~C~LE~ ~ ~;,~L~~~:;~:i
I
ENOUT

NADS

I

---{

I

,~________________________________________ J

-----~-----'~---....--==:~~:!. .'>--~'~I:~j;~_~_·~_'_'-------------------------------

:r---r!

~:::::,~i~1--~1--------~~~5O ....
ADOD-AD11

DIICJO.DB07

NWDS
INRDS IS ACTIVE HIGH
DURING OUTPUT CYCLE)

1---750.,",

, I'

750._ ---l

Figure 1-4. SC/MP Timing (Based on I·MHz Crystal) and Processing Sequences

'·9

• ENIN input.

Table 1·1. Description of SC/MP Pinouts

lID

Basic
Function
Timing

Xl

III
X2

m

-

Vss

m

Power

VGG

Sense A

1m

Sense B

m

Flag 0

ID
Flag 1

HI

External
sensing and
softwarecontrolled
interrupt

External
control of
peripherals

m

....
D

ENIN

Bus-Access,
DMA,and
Multiprocessor
Control

ENOUT

-

CONT

-

NRST

Connect capacitor between these pins
for applications where timing is not
critical; use crystal where timing is
critical. (Refer to Appendix A for
component characterization and the
use of an external clock.!

Basic
Function

Design Considerations

Negative
Reset

When this input is set low, in-process operations are aborted.

NHOLD

Wait

In conjunction with CONT, the NHOLD
input can be used to implement single
cycle/single-instruction control of SC/MP
- refer to figure 1-4e for extended input/
output timing.

SIN

Serial Input/
Output

When the SIO instruction is executed,
the MSB of the input data is shifted into
the MSB of the extension register, and the
LSB is shifted from the E-Register to an
output latch, that is, the contents of the
register can be changed without affecting
ihe state of the output latch.

NADS

Negative
Address
Strobe

When low, indicates valid address and
status outputs are present on the system
buses. The NADS leading edge of the
strobe can be used to externally
latch input/output status and the four
MSB of the 16-bit address; refer to figures 1-4c, 1-4d, and 1-4e for I/O timing
of NADS.

NRDS

Negative
Read Strobe

A Tri-State output that, when low,
indicates SC/MP is ready to accept data
from the 8-bit input/output bus; as
shown in figure 1-4c, data are input on
the trailing edge of this strobe.

Negative
Write Strobe

A Tri·State output that, when low, indicates output data from SC/MP is valid
on 8-bit input/output bus; refer to figure
1-4d for output timing.

....

VSS = +5V (±5%)
VGG = -7V (±5%)

Flag 2

BREa

..

Design Considerations

Start/Stop

These TTL-level inputs are connected
directly to bit positions 4 and 5 of the
status register. Both bits can be copied
from the status register to the accumulator but neither bit can be written into
from the accumulator, that is, they are
"read only" inputs. With the interrupt
armed (bit 3 of status register set high),
the Sense A pin becomes the interrupt
input - see figure 1-4g for processing
sequence of interrupt request and
Appendix C for implementation detail
of the interrupt system.

m

SOUT

ID

m

Each flag output is TTL-compatible and
can drive a 1.6-milliampere load. The
flags are software-controlled and can be
set or pulsed in a single or multiple
sequence.

In simple stand-alone applications,
BREa can be connected to VGG through
a 6.8 kilohm resistor, ENOUT can be ignored, and ENIN can be connected to
VSS so that the SC/MP microprocessor
has access to system buses whenever the
BREa pin is high. In systems that require
bus-sharing, the common bus-request
line is continually tested by each microprocessor; when the request line is low,
system buses can be accessed, and if
BREa and ENIN are set high, bus access
is granted.
Permits suspension of operations without loss of internal status. Can be used
with 'HALT' flag to implement a programmed halt; also, can be used with
NHOLD (Wait) signal to implement
singl-e-cycle/single-instruction control
of microprocessor.

R

-......
NWDS

DB 00-07 Input/Output
data

AD 0011

ED

.··m

"Refer to SC/MP data sheet for minimum/maximum values.

1-10

Latched
Address

At NADS time, I/O status and 4-MSB of
16-bit address are output from SC/MP;
at NRDS time, data are input to SC/MP
and, at NWDS time, data are output
from SC/MP. Each pin is bidirectional
and Tri-State.
At NADS time, the 12-bit latched
address is valid and, as shown in figures
1-4c and 1-4d, a read or write function
then is implemented .

ADDRESSING CAP ABILITIES AND INSTRUCTION
SET OF SC/MP

ploying larger memories, the high-order
bits must be set to the starting address of
the desired 4K block of memory. For example, when the 4 high-order bits are
0001 2 , memory locations 1000 16 IFFF 16 are addressed; when 0010 2 ,
memory locations 2000 16 - 2FFF 16
are addressed; and so forth.

Addressing
During execution, instructions and data defined in a program
are stored into and loaded from specific memory locations,
the Accumulator, or selected registers. Because SC/MP memory (read/write and read-only), and peripherals are on a
common data bus, any instruction used to address memory
may be used to address the peripherals. The formats of the
instruction groups that reference memory are shown below.

opcode

I'

I ptr

.0
disp

A PC-relative address is formed by adding the displacement
value specified in the operand field of the instruction to the
current contents of the Program Counter. The displacement
is an 8-bit twos-complement number, so the range of the
PC-relative addressing format is -127 10 to +127 10 locations
from the current contents of the Program Counter.

Memorv
Reference
Instructions

disp

7 . . . . 32 11.0

PC-Relative Addressing

1

Memory
Incrementl
Decrement
Instructions
and Transfer
Instructions

Immediate AddreSSing
Immediate addressing uses the value in the second byte of a
double-byte instruction as the operand for the operation to
be performed. For example, compare a Load Instruction
(LD) to a Load Immediate Instruction (LDI). The Load
Instruction uses the contents of the second byte of the
instruction in computing the effective address of the data
to be loaded. The Load Immediate Instruction uses the contents of the second byte as the data to be loaded.

Memory-reference instructions use the PC-relative, indexed,
or auto-indexed methods of addressing memory. The
memory-increment/decrement instructions and the transfer
instructions use the PC-relative or indexed methods of addressing. The various methods of addressing memory and
peripherals are shown below.
Type of
Addressing

m

PC-relative
Indexed
Immediate t
Auto-indexed

0
0
1
1

Operand Formats
ptr
disp

0
1, 2,or 3
0
1, 2,or 3

Indexed Addressing
Indexed addressing enables the programmer to address any
location in memory through the use of the Pointer Register
and the displacement value of an instruction. When indexed
addressing is specified in an instruction, the contents of the
designated Pointer Register are added to the displacement
to form the effective address. The contents of the Pointer
Register are not modified by indexed addressing.

-128* to +127
-128* to +127
-128* to +127
-128* to +127

.. For PC-relative, indexed, and audo-indexed memoryreference instructions, another feature of the addressing
architecture is that the contents of the Extension Register are substituted for the displacement if the instruction displacement equals -12S (X'SO).
t Immediate addressing is an addressing format specific to
immediate instructions.

Auto-Indexed Addressing
Audo-indexed addressing provides the same capabilities as
indexed addressing along with the ability to increment or
decrement the contents of the designated Pointer Register
by the value of the displacement. If the displacement is less
than zero, the contents of the Pointer Register is decremented by the displacement before the contents of the effective address are fetched or stored. If the displacement is
equal to or greater than zero, the contents of the Pointer
Register are used as the effective address, and the contents
of the Pointer Register are incremented by the displacement
after the contents of the effective address are fetched or
stored.

NOTE
All arithmetic operations associated with
address format affect only the 12 loworder address bits; no carry is provided to
the 4 high-order bits. For systems employing memories of 4K or less, the high-order
bits can be ignored, as they are set to 0000
following initialization. For systems em-

1·11

(Instruction Set

bit operation code that specifies an operation that SC/MP
can execute without further reference to memory. A doublebyte instruction consists of an 8-bit operation code and an
8-bit data or displacement field. When the second byte
represents a data field, the data are processed by SC/MP
during execution of the instruction, thereby eliminating the
need for further memory references. When the second byte
represents a displacement value, it is used to calculate a
memory address that will be accessed (written into or read
from) during execution of the instruction.

The SC/MP instruction set provides the general-purpose
user of microprocessors a powerful programming capability
along with above-average flexibility and speed. The instruction set consists of 46 instructions, which comprise 8 general categories. A listing of the complete instruction set is
provided in table 1-2; typical instruction execution times
are given in table 1-3, and notations and symbols used as
shorthand expressions of instruction capability are defined
In table 1-4.

Figure 1-5 provides a flowchart that illustrates the execution
sequence for the various classes of SC/MP instructions.

:The instruction set includes both single-byte and doublebyte instructions. A single-byte instruction consists of an 8-

Table 1-2. SC/MP Instruction Summary
Mnemonic

Description

Object Format

Operation

76543210 76543210
disp
1 1000 mptr
disp
1 100 1 mptr
disp
11010 mptr
11011 mptr
disp
disp
11100 mptr
disp
11 101 mptr
disp
11110 mptr
disp
1 1 1 1 1 mptr

(AC)<-(EA)
(EA)<-(AC)
(AC)<-(AC)
(EA)
(AC)<-(AC) v (EA)
(AC)<-(AC) v (EA)
(AC)<-(AC)10 + (EA)lO + (CY/L);(CY/L)
(AC)<-(AC) + (EA) + (CY/L);(CY/L),(OV)
(AC)<-(AC) + -(EA) + (CY/L);(CY/Ll.(OV)

Micro·
Cyc

22K

r
K

NAOS

VGG

P

-V

DB 00

DBOl

DB 02

0803

DB 04
0805

DB 06

...
~

DB 01

.....

+V

v----..........I'.I
. v -----1231

'137 14"
1139 17
'13A 11
,13B 19
113C C4"
,13E 'I
,13F C4,1
,141 '7
1142 116
1143 042U
1145 98F8
,147 C4FF
'149 IFFF
'148 '6
'14C 0421
,14E 98E7
liS, C4H
'152 ,7
1153 19
1154 C4FF
1156 'FFFF
1158 116
'159 0421
,15B 9CF7
'ISO 16
'lSE 041'
116' 9800
1162 CllA
1164 61
,165 9C,4
'167 C4,2
,169 9H2
,16B C4,4
,160 ,7
'16E C4,5
1171 'I
'171 C4FF
,173 ,FFF
1175 12
1176 C4H
I17B n
'179 9CF5
,17B 9'BA
'170 H

....

TH[S PROGRAM CONVERTS THE SC/MP M[N[MUM
SYSTEM TO AN ElECTRON[C COMB [NATION lOCK.
OATA [S SET ON THE SER[Al ENTRY LINE
AND [S ENTERED BY PULSING THE SB [NPUT.
; FI [S 'ENTER DATA' lAMP
; Fl [S 'ACCEP!' lAMP
; F2 [S ,'REJECT' lAMP
; SER[Al OUT CONNECTS TO SA
; SB [S DATA BIT STROBE
lD[
; CLEAR ACCUMULATOR
ENT:
; CLEAR STATUS REG[STER
CAS
; CLEAR E REG[STER
XAE
S[O
; CLEAR SER[Al OUT lATCH
lD[
,B,
; SET ACCUMULATOR MSB = 1
; SET E REG[STER MS8 = 1
XAE
; SET ACCUMULATOR = 1
lD[
TED:
'I
; TURN ON 'ENTER DATA' LIGHT
CAS
TST] :
; lOAD STATUS [NTO ACC
CSA
AN[
; TEST FOR S8 = 1
'21
TST] :
; GO BACK [F S8 NOT = 1
JZ
; SET UP .6 SECOND DELAY
lD[
IFF
DlY
; EXECUTE .6 SECOND DELAY
IFF
; lOAD STATUS [NTO ACC
CSA
AN[
; 80UNCE TEST
'21
; [F NOT STIll 1 START OVER
JZ
ENT
lD[
; [F SB STlll-l CONTINUE
D
; TURN OFF 'ENTER OATA' lAMP
CAS
S[O
; ENTER 8IT [NTO SER[Al [NPUT
lD[
; SET UP .6 SECOND DELAY
TST2:
'FF
,FF
DLY
; EXECUTE .6 SECOND DELAY
CSA
; WAIT FOR SB TO DROP
AN[
; [S S8 STIll H[GH?
121
; GO 8ACK [F SWITCH H[GH
JNZ
TST2
TST3:
CSA
; lOOK FOR STOP BIT = 1
AN[
; '·!ASK STOP 8IT
C1D
; [F STOP BIT NOT 1 00 AGA[N
JZ
TED
TST4:
; lOAD CORRECT BIT PATTERN
lD
CODE
; XOR RECE[VED BIT PATTERN
XRE
JNZ
REJECT ; [F RESULT = , TAKE NEXT [NST
; SET CODE FOR ACCEPT lAMP
ACCEPT: LOt
,2
; GO TO DELAY ROUTINE
JMP
DELAY
; SET CODE FOR REJECT lAMP
REJECT: lD[
14
; TURN ON APPROPR[ATE lAMP
DELAY:
CAS
lD[
; SET UP 5 BIT COUNT
; TRANSFER COUNT TO E. REG
lOOP:
XAE
lD[
; SET UP .6 SECOND DELAY
IFF
; EXECUTE .6 SECOND DELAY
DlY
JF1'
; PRESET CARRY
CCl
; SUBTRACT 1 FROM COUNT
lD[
IFF
; COUNT [S [N E REG
ADE
; NO-CONTINUE 3 SECOND DELAY
JNZ
lOOP
; YES-START OVER !!!!
JMP
ENT
CODE:
.BYTE
; CORRECT WORD
.END

'S

.

Figure 1-6. Minimum Security System Using SC/MP and PROM

NS10529

22K
MM74C04N

d

DATA

SET

XI

~C.

-V_

):2

FLAG 1

SENSE A
V_

..

ENnn
UATA

.::::::I

SIN

SENSEB
ADOO

AD,,)l
AD02
AD 03
AD 04

....
I

CD

AD 05

J ..

NWDS

~ SOUl
74

-V---'"

REPEAT
CIRCUITS
CO"'NECTEO
TO PIN 3
FOR EACH
PINOUT

••

V"

ENIN

S

~

I

AC
SOURCE

REST
(READY
DATAl

I

ENOUT
BREQ

r

.?22K

.?22K

S.M

NRST

CONT
NADS

P

VGG

DBOO

AOOS

DBOI

~ ADO'

DB02

1\0 OR

DB 03

AD 1')9

DB 04

AO ,0

OB05

AD 11

OB06

NROS

DB07

NOTES:
1. Transistor Array ILM 3046N)
or equivalent.

-v

-v --..--l1sl
+v----(23J

•

+V

tVS10530

Figure 1-7. Expanded Security System Using SC/MP, PROM, a 4-by-l 0 Decoder, and Miscellaneous Components

BUFFERING AND INTERFACE CHARACTERISTICS
OF SC/MP

Buffering SC/MP
As indicated in the preceding paragraph, SC/MP can generally interface with MOS and low-power TTL circuits without the use of buffers. In applications where the SC/MP
drives more than one TTL load, buffering is required. One
method of buffering SC/MP outputs is shown in figure 1-8.
To minimize component count and to conserve power,
low-power Schottky TRI-STATE® octal buffers are used;
in addition to data-, address-, and control-line buffering,
the high-order address bits (AD 12-AD 15) are latched to
support large memories and/or a full complement of input/
output peripherals. Each buffered output line can drive 10
or more TTL loads - approximately 16 milliamperes.
To determine if buffered or direct-to-chip connections
are required for a particular application, the user must
consider carefully such system parameters as overall loading, sink-current capabilities of SC/MP, duty cycle, peak
power, and so on. Refer to the SC/MP Data Sheet for
parametric specifications.

In any application, buffering and interfacing capabilities of
SC/MP are important design considerations; the following
sections are addressed to these parameters.

TTL/MOS Interfaces
From an overall interface point-of-view, the current and
voltage characteristics of SC/MP are summarized as follows.
• Except for BREQ (pin 5) and Xl/X2 (pins 37/38),
all input pins typically present a 1.4-milliampere
TTL load to any driving device.
• Except for BREQ, all output pins can drive a 1.6milliampere TTL load.
• With VSS = +5Vand VGG = -7V, SC/MPisvoltagecompatible with TTL devices; thus, it can interface
directly with TTL logic. Direct interface with
5-volt MOS logic also can be implemented.

The power-up and initialization circuit shown in figure 1-8
is designed to accommodate any 'clock' technique (appendix A) that is used with SC/MP. An RC network can be
used for the NRST input but does not provide timing that
is as precise and probably not as reliable as would be provided by the Schmitt Trigger. (Note: If a manual reset is
desired, a switch can be connected from the input of the
Schmitt trigger to ground.)

NOTE
Refer to SC/MP Data Sheet for minimum/
maximum input/output specifications.
To minimize buffering requirements, it is advantageous to
use MOS, or Low-Power TTL devices for direct interface
with SC/MP. Usually, the low-power devices present much
less than a 1.6-milliampere load and their propagation delay
times compare favorably with the timing parameters of
SC/MP_

® Registered trademark of the National Semiconductor
Corporation

1·19

-

-v

BREQ

l.6...
......

..

DBO-DB7

NOTE 3

NOTE 2

L

'"

r"~

No
4

LATCHED HIGH·ORDER
ADDRESS BITS

AU 11.

.. AD14
AD 13
.. AD12

NAD1S
LATCHED INVERTED
HIGH.ORDER ADDRESS BITS .. lI'tA
4
NAD13
.. NAD 12

NOTE 2

.....
- .....

+5V

~

5.1K
NRsT

-a

~

S
C
/

~~f;:,
~O,TE[

lK

~

4275

1

~"oo-

2
2!lf

+~r

-=-

M
P

..

ADO·AD7

NOTE 2

BUFFERED DATA BUS
NOTES:
1. QUAD 2·lnput NAND 5c:hmitt Triggar (DM74Lsl32) or
Equivalent
2. Tri·state Octal Buffer (OM 81Ls95/DM 81Ls97) or
Equivalent
3. HEX/Quad D Flip·Flops with Clear 10M 74Ls175)
4. HEX Inverter 10M 74L04) or Equivalent
5. Refer to sC/MP Data Sheet for Unbuffared Drive
Capability of Each OUTPUT LINE
6. The data buffers are alway. enabled to output data,
except at NRDs time.

'"

BUFFERED
LOW·ORDER ADDRESS BUS

'"

807
801
805
804
803
802
BD 1
800

AD"
AD 10
AD.
ADa
AD7
ADI
AD5
AD4
AD3

IWZ
AD 1
ADO
NOTE 2

AD8·AD11

BUFFERED FLAGS AND SERIAL OUTPUT

FLGO
.. FLGl
.. IFLG2

LSOUT
FLAG 0/1/2
ANDsOUT

-""+5V
4.1K

NWDS
NRDS
NADS

.,..

NOTE 2
BUFFERED CONTROL STROBES

NWIlS
.. NRIlS
... NAIlS

NS10531

Figure 1-8. One Method of Buffering Data, Address. and Control Lines of SC/MP

TRI-STATE Considerations
In figures 1-2 and 14, the 12-bit latched address port
(AD OO-AD 11), the 8-bit input/output port (DB OO-DB 07),
and the read (NRDS)/Write (NWDS) strobes have three
separate output states - a TTL logic '0', a TTL logic '1',
and a high-impedance (HI-Z) (TRI-STATE) output. The '0'
and '1' states are self-explanatory; an examination of figure
1-9 will show why the third (HI-Z) state is required. As
shown, the 8-bit input/output bus is bidirectional; that is,
during a read cycle, the internal receivers of SC/MP are connected to the bus and, during a write cycle, the SC/MP

r

drivers are connected to the bus. If the TRI-STATE device
(shown shaded in figure 1-9) is removed, the TTL outputs
of SC/MP and of the TTL device are connected directly to
the bus and both will attempt to drive it. Generally, the
drive capability of the TTL device is the greater of the two;
thus, it will prevail and system control by SC/MP is lost.
With the TRI-STATE device connected, the TTL device is
effectively disconnected from the bus; however, at read
strobe (NRDS) time, the output of the buffer is enabled
and the drivers of SC/MP are disabled. Accordingly, the
SC/MP receivers read whatever is put on the bus by the buffer.

READ CYCLE - SC/MP
DRIVERS TRI-STATED
WRITE CYCLE SC/MP
DRIVERS ACTIVE

,

~

;,.

....

,

8·BIT INPUT/OUTPUT BUS
..

111
T~~~:'

S

C,

1

M

P

TO OTHER
DEVICES

1

TRI-STATE OUTPUTOUTPU T ENABLED WHEN
NRDS I S LOW; OUTPUT
DISABL ED (TRI-STATE)
WHEN NRDS IS HIGH

[

TTL
DEVICE

-

NRDS

'f--

I
I,

TO OTHER
DEVICES

NS10532

Figure 1-9. TRl-STATE Bus Interface

1-21

Figure 1-10 shows a method of implementing TRI-ST ATE
control. With both TRI-ST ATE ENABLE lines high, both
the memory and peripheral devices are effectively disconnected from the data bus; that is, the output drivers of each
device are in the high-impedance mode. At read strobe time,
one of the devices is selected; if address bit (AD 08) is low
(inverted high), the TRI-STATE ENABLE line of ROMI
PROM is driven low and this memory device is selected as

the bus driver. Conversely, if AD 08 is high, the other select
line is enabled and the peripheral is selected to drive the bus.
Since each device is selected by a discrete address, the processor has absolute control over each "receiver" or "transmitter" connected to the bus. (Note: The basic addressdecoding scheme shown in figure 1-10 can be expanded to
serve small-memory systems (up to 4K) that require multiple
read/write peripherals; refer to appendix B for further detail.)

8·BIT INPUT/OUTP. DATA BUS

• •

~

II-

~

II-

TRI-STATE
ENABLES

..

ACTIVE

ROM/PROM

\

LOW

PERIPHERAL

""-

...

S

C
/
M

P

LOW ORDER ADDRESS BITS
(ADOO - AD 07)

~AD~-C>-~

l.CL.
-

AD 08----..

HIGH ORDER ADDRESS 81TS (AD 08 - AD 11)

NRDS

~

RDS

V

NS10533

Figure 1-10. One Method of TRI-STATE Control

1-22

Chapter 2
CONCEPTS AND PRINCIPLES OF SC/MP INTERFACING
In the preceding section of this manual, SC/MP is defmed
in terms of general-purpose applications-timing, loading,
peripheral interfacing, software manipulation, and so on. In
this section, these SC/MP parameters are brought together
to explain how to hook-up, how to implement, and how to
control a variety of functional SC/MP-based applications.
For current convenience and future add-on flexibility,
the applications are organized by class.

alphanumerically for statistical studies in applications
where time is plotted against some other variable. In
subsequent sections, some typical analog-to-digital conversion schemes are described. Refer to chapter 1 of this
manual for timing information, pinout descriptions, and
interfacing detail of the SC/MP chip.

GENERAL CONCEPTS OF AID AND D/A CONVERTERS

General Description

Generalized concepts of how a SC/MP-based system can be
used in a general-purpose analog-to-digital converter are
shown in figure 2C 1 -1. The analog source can be any
device capable of producing a current or a low-voltage
output over a predetermined range. Under program control
and system timing parameters, the analog source is sampled
by the Analog-to-Digital Converter and the resulting output
is a digital word with 8-bit resolution. The digital word is
stored in RAM where, under program direction, it can serve
a number of functions. For example, the converted data
can be compared to a previously stored reference value;
thus, in a quality-control configuration, for example, a
pass or a reject decision can be made. As another example,
the difference between the input data and the stored
reference can be treated as an error signal, and when
reconverted to its analog equivalent (shown with broken-line
blocks and lines), it can be used in applications that require
coordinate control. The output data also can be listed

The SC/MP-controlled analog-to-digital converter shown in
figure 2Cl-2 is well-suited to applications such as simple
machine control, single-parameter testing, data acquisition,
and other single-input functions. Requiring few components, minimum memory, and "a simple program, the
single-input analog-to-digital converter is easy and inexpensive to implement. Operating principles of analog-to-digital
converters and logic circuits used in this application are welldefined in textbooks and industrial manuals; thus, the following descriptions are aimed primarily at the functional
interfaces, user-supplied system parameters, and control
and supervision of the software.

r
I

•

SOURCE TIMING
AND CONTROL

-,
~

L - - - ...J

System Operation
Other than supply voltages, the single-input converter
system requires a start pulse, clock pulses, an output-enable
gate, and, of course, an analog input. Providing that a valid

of)
)

ANALOG·TO·DIGITAL
CONVERTER

ANALOG VOLTAGE
OR CURRENT SOURCE

..L

SINGLE-INPUT ANALOG-TO~DIGITAL CONVERTER

a

SC/MPWITH
RAM,AND ROM
OR PROM MEMORIES

,

1

r----,
~

DIGITAL·TO·ANALOG
CONVERTER

J.-- - - - - - -

L ___ --1

-

ALPHA·NUMERIC
OUTPUT

USER DATA

-.J

NS10534

Figure 2Cl-1. Principles of Analog-to-Digital/Digital-to-Analog Conversion
2C1-0

A~LOO __________________________________________________,

INPUT

AD10

NWOS

AD11

AD 10

AD"
NOTE 4
NOTES:

--V'

1. Thi. cont"',8tian repnunts only on. of me""
to build end inhlrf8CI e .ingl. e"'I~lo-dititei con·
.y.t.m. If
compon.nts end inltrflCillll
melhoch .,. ulld, .Iectripl 'plCificlition. daould be
equive''"t to those lliown.

NADS

'''hi'

01"',

Z. H•• conve,.er IDM 74041. or equivel.nt.
3. 3-input politi".nd ....

aREa

~DM

74111 or equiv.llnl.

4. D.... D flip-flop IDM 74741, or eqviv.lenl.

i'.

CLOCK

S. If NWDS goe' hi... lineclinl before e n.... clock
I,enltlion i. completed. pul..·.trelChin.I.-=h .imi·
I., to thIt shown by the __ ned circuits Cln be ulld
to ....nd NWDS; in ..... CIII, remov. thl jumper_
If .... pulre-stretchlr i. not required, hlnlwire ttII
jum"'" connection .nd omit III of .... 1CfHMd
circuits.
8. "SCIMP chip i. nol buff.red, low-power de,ice'
are required - IN Filur.1-8 for bu ••.,1d SCIMP
chip.

IUSERSUPPLIEDI

NS10535

Figure 2Cl-2. Single-Converter Analog-to-Digital System
circuit similar to that
the unused flip-flop in
this purpose. In figure
has been arbitrarily
address could be used.

start-converter pulse is present (logic I at pin 6), the
conversion starts on the trailing edge (high-to-Iow transition)
of the first clock pulse and continues for 40 clock cycles.
When the conversion is completed, an 8-bit digital word is
"loaded into an output latch and an end-of-conversion
(EOC) logic level is generated. The binary output (DBO
through DB7) is TRI-STATE to permit the use of common
bus lines. When a valid address is received, an output-enable
, signal is generated; at this time, the digital output enters
: the accumulator of SC/MP and subsequently is stored in a
designated memory location. Valid data are held in the
output latch from the end of one conversion to the end of
the next; thus, data transfers to memory can be implemented asynchronously.

CONVERSION
STARTS

CONVERSION
ENOS

j---40CLOCKCYCLES----j

AIO CLOCK

'-'+05V
--- V

n ri n n n r''''I n h n r
J UUUUU UUUU

Ji
--I

+5V
STRT CONY ~

~

+5V

ov

I

the trailing edge of • "slow" dock, the system is
inoperative. NWDS can "extended tshown screenedl
by the pulse-stretching latch noted in fig. 2Cl·2

~.~~-NW-OS--E-X~T-EN-O-E-O----------------

~

L
_

+5V
OUTPUT
ENABLE

NWDS controls this width_ If, .. shown by 1he do1-

~ ted line, the "start conv" pulse is terminated before

I

OV

ENO-OF
CONVERSION
(EOCI

Timing for one conversion cycle is summarized in figure
'2Cl-3. As shown, the conversion begins on the trailing
'edge of the clock pulse; thus, the 'start converter' gate
must be at least as wide and preferably somewhat wider
than one clock cycle. Referring to figure 2Cl-3, it is seen
that the width of the 'start' gate (STRT CONV) is determined by the write strobe (NWDS) of SC/MP. If the analogto-digital clock is slower than NWDS, a pulse-stretching

noted in iigure 2C 1-2 is required;
the DM7474 package is available for
2C 1 - 2, a starting address of X'0800
chosen-any other nonconflicting

~

EOC GATE'" 40 x l/f~LOCK
I

DATA·ENABLED TRANSITION
UNOER PROGRAM CONTROL

OV
1,0 .SEC DELAY BETWEEN OUTPUT ENABLE

ANO OATA-VALID CONOITION OF DATA PORT
+5V

'II-STAll
OV

I

r ---1r-

,~

___

1

I

+----l

~
NS70536

Figure 2Cl-3. Timing Summary for Single-Converter System

2C1-1

When the conversion cycle starts, the analog input is
admitted at pin 12 of the converter chip and the end-ofconversion (EOC) gate is set low. During the next 40 clock
cycles, the input is sampled continuously and, via a process
of successive approximation, the analog signal is converted
into an 8-bit digital word. At the end of the fortieth clock
cycle, the conversion is complete and two things happenthe EOC gate is set high and the digital word is loaded into
an output latch on the converter chip.

are provided to optimize conversion accuracy. Variable
resistor RI is the zero adjustment, and for a 10-volt scale,
it is set for a transition from '11111111' to '11111110' to
occur at 19.53 millivolts (that is, one-half of the least
significant bit value). If the voltage difference between
pins 5 and 15 is more than 10 volts, then the half-bit
zero-adjustment value is obtained by dividing 528 (the
number of half-bit values) into the difference voltage. For
instance, if the voltage between pins 5 and IS is 10.24
volts, RI is adjusted for 20 millivolts at the transition
point-'ll 111111' to '11111110'. Resistor R2 is the
full-scale adjustment, and for a 10-volt scale, it is set for the
transition from '00000001' to '00000000' to occur at 58.6
millivolts (that is, one and one-half times the least significant bit value). Again, if the difference voltage is 10.24
volts, R2 is adjusted for 60 millivolts at the transition
point-'OOOOOOOI' to '00000000'.

When the output is enabled (Output Enable set high), the
latched data (DBO through DB7) are available at pins 13,
14, 16, 17, and 1 through 4, respectively. In likeness to
the STRT CONV gate, the Output Enable gate is generated
via an arbitrary address-in this case, 0400 16 • The Output
Enable gate is synchronized by the address strobe (NADS)
from SC/MP, and the gate remains active high until the bus
request line (BREQ) is released (goes low) by the microprocessor. The output control functions are under software
control and, as shown in figure 2CI-2, are implemented by
a flip-flop.

Software Considerations
The flowchart and program listing in figure 2C I -4 shows
how the single-input analog-to-digital converter system
(figure 2CI-2) can be software-controlled to provide the
functions described under system operation. Referring to
figures 2CI-2 and 2CI-4, the software-hardware interface
can be summarized as follows.

System Adjustments
With supply voltages as shown, the analog-to-digital converter in figure 2C 1-2 is designed to operate over an input
range of ro volts (±5 volts). Two adjustments (RI and R2)

1

(

START

)

TITLE

SCMP. SINGLE A/D CONVERTER PROGRAM

2

0003

•

3

0002

P2=2

4

0000

CONV0=0

t

PROGRAM

PUT STARTING ADDRESS (X'OIIGO) IN

5

P3=3

NOP

0000

08

6

0001

C400

LDI

X·00

7

0003

32

XPAL

P2

8

0004

C408

LDI

X'08

9

0006

36

XPAH

P2

10

0007

CA00

ST

CDrN0(P2) ;START CONVERTER 0

0009

08

tlOP

;IF REQUIRED DELAY INTRODUCEU TO

12

000A

03

tlOP

; COMPLETE THE CONVERSION

13

0008

03

NOP

14

000C

08

15

0000

C404

16

000F

36

17

0010,· C402

LDI

x'02

;LD P3 WITH MEM ADDRS FOR

13

0012

37

XPAH

P3

;CONVERTED DIGITAL OUTPUT

19

0013

C400

LDI

X'00

LOAD CONVERTED OUT,
PUT INTO ACCUMULATOR

20

0015

33

XPAL

P3

AND STORE IN MEMORY

21

0016

C200

LD

CONV0(P2) ;REAO IN CONVERTED OUTPUT

ST

(P3)

POINTER P2 AND
BEGIN CONVERSION

WAIT FOR 40 CLOCK
PERIODS 14OI'SEC FOR
1 MHz CLOCKI,
- NOTEIF CLOCK IS SLOWER

THAN 1 MHz A LONGER
DELAY IS REQUIRED.THAT
IS-DELAY· 4O.X l/fclock

•
•
•

SET BASE CONVERTER
ADDRESS IX·04OO1
IN POINTER P2 TO
SELECT OUTPUT

11

START:

; LOAD P2 WITH ADRS OF CONVERTER

NOP
ACCEPT:

LDI

X'04

XPAH

P2

; LD P2 III TH BASE CONV ADRS

LOAD POINTER P3

WITH ADDRESS
X·0200 TO STORE
CONVERTED OUTPUT

LOCATION X·02OO,

t

22

0018

C80~

STORE:

; ST~RE CONVERTED OUTPUT
; IN LOCATION 200

EXIT

NS10537

Figure 2Cl-4. Flowchart and Program Listing for Single-Converter System
2C1-2

At the start of the program, P2 is loaded with the starting
address, X'0800 (lines 6 through 9), a STore Instruction is
executed, and the 12-line address port of SC/MP is latched
at X'0800 for the remainder of the input/output cycle. Accordingly, ADIO goes low, ADII goes high, and, at write
strobe (NWDS) time, the conversion starts. Since there are
seven instructions executed prior to the Load Instruction,
the NOPS are not required unless the converter clock rate is
slowed down. If the clock rate is considerably less than 1.0
megahertz, more delay may be required - refer to appendix
E for delay calculations.

Once the analog-to-digital conversion is completed (after 40
clock cycles), the digital data are accepted by SC/MP and
are stored in a specified memory location. As indicated by
lines 15 through 20 of the program, P2 is loaded with the
address for "data acceptance" - in this case, X'0400 - and
P3 is loaded with the "memory-destination" address
(X'0200). When the LD Instruction (line 21) is executed,
the 8-bit digital output of the converter is read into the Accumulator, and when the next instruction (STore, line 22)
is executed, the data are stored in memory location X'0200.
Observe that when the X'0400 address is valid, the output
data are gated into the Accumulator via the address strobe
(NADS) rather than the read strobe (NRDS); the NADS signal provides adequate time for the transfer of data, whereas
the NRDS signal may not.

ANALOG-TO-DIGITAL CONVERSION USING
MULTWLECONVERTERS
General Description
The SC/MP-based multiple analog-to-digital converter shown
in figure 2CI-5 is simply an extension of the principles and
concepts used in the single configuration (figure 2CI-2).
The multiple system is adaptable to almost any application
where analog-to-digital conversion is required - complex
control systems, multiple-parameter testing, precision measurements, environmental studies, and many others. Among
other advantages, the multiple-converter system is easy and
relatively inexpensive to implement.

System Operation
Other than supply voltages, the multiple system requires
start/select signals for each converter, a user-supplied clock
source, output buffers, and appropriate control and decoding logic.

2C1-3

NOTE

In figure 2C 1-5, it is assumed that each
analog Signal source is located some distance from the other; thus, the analog-todigital conversion is performed at the
origin rather than at the destination. This
is done because a digital signal can be transmitted over a reasonable distance with
little or no degradation, whereas an analog
signal may require additional circuits for
equivalent accuracy and stability. If the
signal sources are in close proximity and
sampling time is not a critical factor, the
inputs can be multiplexed as shown in
figure 2CI-7.

Some of the multiple-converter circuits are functionally
equivalent to those of the single converter; thus, they are
described by reference only.
The eight analog-to-digital converters shown in figure 2C 1-5
can be started and the associated output selected in any
sequential order - this being determined by the users program and being implemented by the two BCD-to-decimal
decoders. The 'start' and 'select' decoders operate as follows.
A starting address of X'0800 has been arbitrarily selected;
any other nonconflicting address can be used. The chosen
address is recognized when address bit II (ADII) is high
and address bit 10 (ADIO) is low. When the write data
strobe (NWDS) goes active-low, the decoder input logic (G I,
G2A, and G2B) is enabled and address bits 0, I, and 2 are
decoded to produce anyone of eight start signals. The start
decoding truth table is shown as an inset to the upper BCDto-decimal decoder block of figure 2C 1-5.

The 'select' decoder uses an arbitrary address of X'0400
and is synchronized by the address strobe (NADS) from
SC/MP. With address bit 10 (ADIO) high and address bit II
(AD II) low, a logic 'I' appears at pin 2 of the flip-flop. At
NADS time, a high also appears at pin 3 of the flip-flop;
accordingly, the 0 output (pin 6) is driven low. Likewise,
the 'D' input (pin 12) of the decoder is low and address bits
0, 1, and 2 are decoded to produce anyone of eight 'select'
signals. The converter-select signal remains valid until the
bus request line is released by the microprocessor (BREQ
goes low) - at which time, the decoding logic is disabled
(0 goes high).

INPUT

ENOOF
t'!nNV =0

OBO
START
TAUTHTABLE

START
A B C GI IoZ CONY

OBI

I

OB2

X X X X H NOSTRTI

":"

X X X L

X NOSTRT

X X

X L

X NOSTRT

L

L

L

H L

STRTO

H L

L

H L

STRTI

OB3
OB4
OB5

L H L

H L STRT2

DBa

H H L

H L

STRT3

DB 7

H H L

STRT4

L

L

H L

----f!!I

AI

H H L STRTS

L H H H L

STRT&

GZ • GZA ANO GZB
X • DON'T CARE

..

AD 10---------------,

~

~

AD"

BOB 0
BOB I
SELECT
TRUTH TABLE

BREO----------------------------------~

BOBZ

~ ~~

BOB 3

SELE

ADZ

~

IA B C o
IL

AD,

~

L

L

L SELO

H L

L

L SELl

L

H L

H H L
L

ADD

~

CON'

L

L

SELZ

IUffER #1 THRU
IUffER #7
..
(SEE #0 AIOVE . .
fOR PINOUT DETAIL)

SEL3
SELS

H H L

SELa

H H H L SEL7

BOB 4
BOBS
BOB &

H L SEl4
H L

H L
L

L

CONVERTER #1 THRU
CONVERTER #7
(SEE #0 AlOVE
fOR PINOUT DETAIL)

BOB 7
1. This configumion ,."..m only OM of mMy ways to build and in...•
. . . . muh:iple-input _Iog-to-cligit.l c:onveI'W'. If 01her components and
intwtKing medlodl an YIMI. electro IPICificatiOM should bllllui••
....t to III... shawn tnd/or dacribed.

2. 81LS98 HtxCon.,. (OM 1404), or equid"'t
3. 3-lnput POIitive AND 01.. CDM 7"0, or.equiv.a.nt
4. If optiOllllI buffers, (OM 81LS.t ......., ... invtrten thn.mea
the ·output ......• lint (pin 7) of ... OM 5357' C*1 be .Iimi......
In this CIII, the output ..... line of uch converter is tied to +5 voili.
The TRI-STATE Clplbility of the syS1llm is now MfV8d by the buffen.
rMhIr then the conwwtIIn.
5. The buffer i, recommended if multiple loeds . . driven; if loading it
mini....' (not more 1Mn 1.& milliim.... '. output buffering is not
required.
6. It SCIMP chip is not buffered. low-power devices are required-_
figure ,-. for buffered SC/MP chip_

Figure 2el-S. Multiple-Converter Analog-to-Digital System

NS70538

In a multiple-converter system, timing for one conversion
cycle is identical to that shown in figure 2CI-3; however,
'there are noteworthy differences in the start and select func'tions. The eight converters in figure 2CI-5 can be started in
any random order and, after an appropriate delay (40 x
clock period), the outputs can be selected at random. For
instance, it may be desirable to start the converters in 2-6-174-3-8-5 order and to enable the outputs in 7-2-54-1-3-8-6
order, or in some other sequence that suits a particular application. Output levels (DBO through DB7) of each converter
are TTL-compatible and, as previously indicated, the data
lines are TRI-STATE to permit common bus lines. If the
output lines must drive multiple loads, a TRI-STATE buffer
such as the DM81LS95 (shown as a broken-line block in
ftgUre 2Cl-5), is required.

program (figure 2Cl-6) stores to the address of the first
converter (X'0800). When the program is executed by
SC/MP, address bits 0, 1, and 2 (figure 2Cl-5) are modified
by lines 11 through 17 of the program and are decoded by
the 74LS138 chip; in this case, the converters are started in
a 1-through-8 sequence. Any other starting sequence can be
obtained by rearrangement of the store instructions. The
last Store Instruction is followed by four NOP Instructions,
each consuming 10 microseconds; thus, a delay of 40 microseconds is introduced. Assuming a 1.0-megahertz clock, no
delay is required for this program; the NOP instructions are
included only to indicate how a 'short' delay can be implemented. If a 100-kilohertz clock is used, the conversion time
is 400 microseconds (that is, 40 x l/fclock). In this case,
a delay of not less than 104 microseconds is required assuming the converter outputs are loaded and stored in the
"starting" sequence. If the load/store operations are performed in random o;der, the worst case delay is 292
microseconds - refer to appendix E for program delays of
this magnitude.

System Adjustments
The zero (Rl) and full-scale (R2) adjustments for each converter in figure 2Cl-5 are identical to those described for
the single digital-to-analog system (figure 2Cl-2).
Software Considerations

After the analog-to-digital conversions are complete and
select address X'040N - where N =0 through 7 - is valid,
the digital outputs of converters 1 through 8 are loaded
into the Accumulator and are transferred to the memory
location pointed to by P3. In likeness to the single-converter
system, the output data are gated into the Accumulator via
the address strobe (NADS); the slow access time of the converter peripherals does not permit the use of the read strobe
(NRDS). As previously indicated, the program can be
arranged to allow sampling of the converter outputs in any
random order.

The flowchart and the program listing in figure 2Cl-6 shows
how the multiple analog-to-digital converter system (figure
2Cl-5) can be software-controlled to provide the functions
described under system operation. Software, concepts are
identical to those shown and described for the singleconverter system except that eight converters must be serviced rather than just one converter.
An address of X'080N - where N =0 through 7 - is selected
to start the conversion; line 10 of the multiple-converter

(

START
PROGRAM

)

+
SET STARTING ADDRESS
(X'GBODIIN POINTER P2
FOR EACH OF EIGHT CON·
VERTERS; START CONVERTERI IN PROGRAM·
ORDERED SEQUENCE

,

,

LOAD POINTER REG·
ISTER P2 WITH BASE
ADDRESS (X'CMOOI TO
SELECT CONVERTER
OUTPUTS; LOAD
POINTER P3 WITH
INITIAL MEMORY
STORAGE ADDRESS
(X'OZOIII

,

,

WAIT FOR 40 CLOCK
PERIODS (40 "SEC FOR
1.0 MHz CLOCKI.
-NOTEIF CLOCK IS SLOWER
THAN 1.0 MHz. A
LONGER DELAY IS
REQUIRED. THAT IS.
DELAY· 40. 11F.

LOAD ACCUMULATOR
WITH DIGITAL OUTPUT
OF CONVERTER NO. I;
STORE CONTENTS OF
ACCUMULATOR IN AD·
DRESS SPECIFIED BY
POINTER P3 AND IN·
CREMENT P3 (BY 11 TO
NEXT MEMORY
LOCATION

I

I
Figure 2CI-6. Flowchart and Program Listing for Multiple-Converter System

2C1-5

I
REPEAT LOAD-ANDSTORE OPERAnONS
UNTIL CONVERTER
OUTPUTS #1 THROUGH
#I ARE RESIDENT IN
MEMORY LOCATIONS
X'OZOII THROUGH
x'Om RESPECTIVELY

E!.T

1.
2
3
4
5
6
7
8
9
1.0
1.1.
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
210
21.
22
23
24
25
26
27
28
29
310
31.
32
33
34
35
36
37
38
39

4121
41.
42
43
44
45
46
47
48
49
513
51.
52
53
54

TITLE
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108
108
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F'-'
it..

P3
STAF.:T:

=
=

NOP
LOI
XPAL
LOI
~-::PAH

ST
ST
ST
ST
ST
ST
ST
ST
NOP
NOP
NOP
NOP
ACCEPT: LDI
XPAH
LDI

SCt'1P,

"'t1ULTIPLE A.····D CONVERTER PRGt1"

2
3:

.- BASE ST ADRS -:> PTR2

€1
F'2
c·
0,;;'

P2
7
CONV0o!------.

ADn

•

ADID

I.

I. THIS CONFIGURATION REPRESENTS ONLY ONE OF MANY WAYSTO BUILD
AND INTERFACE AN ANALOG·TO·DIGITAL CONVERTER WITH MULTIPLEXED
INPUTS. IF OTHER COMPONENTS AND INTERFACING METHODS ARE USED.
ELECTRICAL SPECIFICATIONS SHOULD BE EOUIVALENT TO THOSE SHDWN
AND/OR DESCRIBED.

~I
+5V

·toOlE~

Z. HEX CONVERTER 10M 14041, DR EQUIVALENT.
3. 3·INPUT POSITIVE AND GATE IDM14nl, DR EQUIVALENT.

5.IK

• ~~I.~

NADS

•

I I

.; ICLOCK

~I~ __

4. IF OUTPUT LOADING EXCEEDS THE DRIVE CAPABILITIES OF THE CONVERTER,
THE OUTPUT LINES CAN BE BUFFERED AS SHOWN IN FIGURE ZCI·5. WIRING
CHANGES CAN IE SUMMARIZED AS FOLLOWS: BREAK THE 'OUTPUT ENABLE'
LINE IPIN 11 TO THE CONVERTER AND TIE PIN 1 to +5V FOR CONTINUOUS
ENAILE. CONNECT THE ii OUTPUT IPIN &1 OF THE FLlP.FLOP TO SELECT
LINES il, /ll. OF THE 11LS95 IUFFER IFIGURE ZCI·51; CONNECT DATA LINES
ASSHOWN.
5. IF NWOS GOES HIGH IINACTIVEIBEFORE A CLOCK CYCLE IS COMPLETED,
A PULSE·STRETCHING LATCH SIMILAR TO THAT SHOWN IY THE SCREENED
CIRCUITS IN FIGURE ZCU CAN BE USED TO EXTEND NWOS.
6. IF SCIMP CHIP IS NOT BUFFERED, LOW.pOWER DEVICES ARE REQUIRED-SEE
FIGURE I·' FOR BUFFERED SCIMP CHIP.

-=-______--,

L._ _ _ _

I I

IRED

END OF
CONVEnSION

010

...~do

+5V

-5V

~
SOD"

5 .. __~ __ ..

OBI

.~b--DBZ

AD 0

DB3

AOI

084

ADZ

•

~ NOTE 4

DIS
OBI

NROS

lUtol.!tE~--"'----...

OB1

ANALOG INPUT #1 --~.
__---------------------~

ANALOGINPUT#Z--~.__----------------------~
ANALOGINPUT#3--~.__-----------------------~

--------------------------J

ANALOGINPUT#4--~.
__

ANALOGINPUT#5--~.__---------------------------------------~
ANALOGINPUT#&--~.__----------------------------------------~
ANALOGINPUT#1---~.
__- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -_ _ _ _ _ _ _-J

ANALOGINPUT#I---~.__------------------------------------------~

--J

CLOCKIUSERSUWLIEOI~.
__- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

Figure 2Cl-7. Analog-to-Digital Converter System Using Multiplexed Inputs

NS10540

~ftware

Considerations

!Figure 2C 1-8 shows the flowchart and the program listing
~t are applicable to the multiplexed-input system of figure 2CI-7. The basic concepts are the same as those of the
single- and multiple-converter systems - that is, start the
~onverter, accept the 8-bit digital data, and store the output
rmemory.
It'he program is set up to start the converters in a l-to-8
j.equence (hexadecimal address X'OO through X'07); this is
~ arbitrary choice and can be altered to select anyone of
be converters by changing the 8 low-order bits of P2. Since
~ere is a one-to-one correspondence between the selected

(

converter and the memory storage location, converter
X'0800 is stored in memory location X'0200, converter
X'0801 in location X'0201, and so on for the remaining six
converters. The memory addresses likewise should be altered
by appropriate changes in the 8 low-order bits of P3. After
each conversion, the program checks to see if all eight analogto-digital operations are completed; as shown by the flowchart, this is done by inclusively DRing the Accumulator
with a constant - in this case, '7'. If the OR-result is not
equal to '0', the program loops back and continues with the
next conversion. If the OR-result is '0' , the eighth conversion
is completed and, as written, the program will exit to an
appropriate users routine.

t
START
)
PROGRAM

I

TO SELECT CONVERTER OUTPUT,
LOAD SELECT AODRESS X'04 IN
EIGHT MSB OF Pl-THE EIGHT
LSB OF Pl ARE UNAFFECTED
SINCE THEY KEEP TRACK OF ANA·
LOG SIGNALS 1·THRU-8 IX'OO
THROUGH X'071

t
. CLEAR POINTER REGISTERS pz. P3

LOOP---~

LOAD EIGHT MSB OF P3 WITH
BASE MEMORY ADDRESS
(X'OZI - THE EIGHT LSB ARE SET
TO X'OO THROUGH X'07. DEPENDING UPON WHICH ANALOG SIGNAL
IS SELECTED.

TO SELECT MULTIPLEXER INPUTS ANO
TO START A-TG-D CONVERTERS. SET
lASE STARTING ADDRESS IX'OIOOI
IN POINTER REGISTER Pl.

TO SELECT NEXT CONVERTER, TRANSFER CONTENTS OF EXTENSION TO
ACCUMULATOR AND INCREMENT BY 1.
EXCHANGE CONTENTS OF A·AND-E REGISTERS; TRANSFER E·TO-A SO THAT
10TH REGISTERS CONTAIN THE SAME
NUMBER.

OUTPUT OF DESIGNATED CONVERTER (PlI TRANSFERRED TO
ACCUMULATOR AND STORED IN
THE MEMORY LOCATION POINTEDTOBY P3.

LOAD SELECTOR LATCH OF MULTIPLEXER WITH ADDRESS POINTED-TO
BY Pl; START CONVERSION

TITLE

SCMP.

3
4

0001.
1;.1002
0001

P1.
P2
P3

5
6
7
8
9

=
=
=

08
C400
12
C400

START:

NOP
LDI
XPAL
LDI

2

0000
0001
0003
0004
10 0006
1.1. '21007

~::PAH
LD
ST
L.DI

36

C21313
CA130
C404
36

~~AE

F'2

(P2)
(P2)
4
P2
2

; LOAD ANALOG SWITCH ADRS LATCH
; START CONVERSION

; CONVERSION COMPLETE IN 40 MIC
;ACCEPT CONVERTER OUTPUT
; STORE CONVERTER OUTPUT

(P2)
(P3:)

P3:

4~~1

LDE

E4e7
98eA
40
F4131

'-y-:>
,:;..
LDE
ADI

€Ii

~~IT

;CHECK IF ALL ANALOG
; SIGNALS CONVERTED

1

;ADRS FOR NEXT ANALOG SIGNAL

7

.

P·-:·
..;:.

E)·aT:

; USER RETURN ROUTINE

eeee
ee29
ee02

END
LOOP
P3

eee7

P1
START

e~~1e3:

eee1
13l3e1

*
*

NS10541

Figure 2Cl-8 (Concluded)

CONCEPTS FOR A LOW-COST SYSTEM

System Operation

General Description

As shown, the 8-bit data word (DBO through DB7) enters
two flip-flops that serve as input latches. When a valid address is received - hexadecimal address X'0400 has been
arbitrarily chosen - the 'data input disable' lines (pins 9
and 10) are driven low. At write strobe (NWDS) time with
both disable lines low, outputs D, C, B, and A of one latch
are set to agree with the logic states of the 4 least significant
bits (DBO, 1,2, and 3, respectively), and the other latch'is
set to agree with the logic states of the 4 most significant
bits. Thus, the 8-bit word is latched and is applied to the
DAI200 for the digital-to-analog conversion process. The
digital-to-analog converter uses a series of current-weighted
switches, an ultrastable resistor network, a precision voltage
reference, and three high-gain operational amplifiers to produce the analog-voltage equivalent of the 8-bit digital input.

The 4-chip system shown in figure 2CI-9 illustrates a very
simple technique for converting a digital input to an analog
output and also demonstrates how this analog signal can be
used to generate the digital equivalent of some unknown
voltage. Converter systems. of this type can be usefully employed in such applications as security/alarm systems, errorcontrol loops, digital plotters, and any other application
where these techniques are applicable. The connection
scheme shown in figure 2CI-9 requires a dedicated microprocessor during the conversion cycle and the scheme is
limited to a single 8-bit output. However, this low-cost
system requires little external hardware, no bus connections, and only a few control signals. The system is further
enhanced by the fact that Sense B, the serial input/output
capability, and flags 0, I, and 2 are not used, so conceivably these resources of SC/MP can be put to use in other
applications.

The input currents are summed and compared to a precision
reference voltage; in the system shown, the +IO-volt reference (pin 14) is supplied externally - although the internal

2C1-10

reference can be used for most purposes. The difference voltage that results from comparing the weighted input currents
(pin 19) of the digital word. It is readily seen that if the
digital input consists of all ones (FF), the analog output is
10 volts; whereas, if the input word consists of all zeroes,
the analog output is 0 volt. Suppose the input bit pattern
is 10000000 (80); since this number is halfway between 00
and FF, the analog output is very close to 5 volts. This
analog output can be buffered and used as an error-control
signal or for any other purpose that the application requires.
The system shown in figure 2CI-9 can also be used to
produce an 8-bit word that is the digital equivalent of an
unknown voltage. Such an unknown voltage - within the
conversion range - is shown connected to pin 3 of the voltage comparator (LM311); pin 2 of the comparator is connected to the output of the digital-to-analog converter. Using
successive approximation techniques, the inputs at pins 2
and 3 are compared and, under software direction, appropriate adjustment is made to the input word (DBO through
DB7) after each approximation. With some assumptions,
the operation can be summarized as follows. Since the inherent resolving power of the system is 8 bits, there are 256
digital increments from one end of the conversion range to

2C1-11

the other; that is, if 0 volt is represented by a bit pattern of
all zeroes, the to-volt limit is represented by a bit pattern
of all ones. Assuming an unknown value of 7 volts, the input word for the first approximation is set to the halfway
point - in hexadecimal format X'80. Since the unknown
voltage is higher than the analog-voltage equivalent of the
first input approximation, the Sense-A line of SC/MP is
driven high. The software differentiates between these two
conditions (Sense A = '0' and Sense A = '}') in such a way
that if the line is high, the input word is set halfway between
X'80 and X'FF. If the sense line is low, the input word is
set halfway between X'OO and X'80. In the current example,
the input word is set to X'CO and a second approximation
is performed. Assuming a digital-to-analog relationship that
is nearly linear, the output at pin 19 (approximately 7.5
volts) is now higher than the unknown and the Sense-A line
is driven low. A third approximation is made between X'CO
X'80, that is, at X' AO. Similar input adjustments based on
the high or the low state of sense A are contained until eight
approximations are completed; at this time, an 8-bit word
that is very near the analog equivalent of the unknown voltage will appear in the Accumulator of SC/MP. This word
can be stored away and used later to plot the unknown
voltage or for any other purpose the application requires.

AO 10

OATAIN
DISABLE

ADll
NWDS

l?" -

DBa
OBI

q;
I
II

OUTPUT

~~~~~~

n

ANALOG-VOL
.. EQUIVALENT
OF DIG INPUT

~ ..~~
Vee 16

:~~~.:

6

+5V
HIGHQR LOW
INPUT TO
SENSE A LINE

+5V

DB2
DB3

221

-

•

~

•

.. +15V

O.Olpl

~
N

DB4
DB5
DB6
DB7
1.0pl

ANALOG INPUT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -____________________________________________________________J
~TO+l0VOR

'lOY TO -lOY)

NOTES:
1. This configuration represents only one of many ways to imple·
ment low-c:ost D·to-A/A-fO·D converter systam. If other com·
ponents and interfacing methods Ire used. electrical specifications
should be equivalent to those shown and/or described.
2. Hlx converter (DM7404). or equivalent.
3. If SC/MP chip is not buffered. low-powe, devices are required-see
ligur. 1·8 lor bulfered SC/MP chip.

NS10542

Figure 2CI-9. Low-Cost Converter System

The software can easily be expanded to utilize the analog
data for whatever purpose the application requires.

Software Considerations. The flowchart and program listing shown in figure 2C1-1O shows one method of implementing software control of the low-cost D-A/A-D system.

START
)
PROGRAM

LOAD FIRST APPROXIMATION
(MASK = X'SO) IN
ACCUMULATOR

YES (DONE)

MASK =
X'01

NO
STORE FIRST MASK
AT LOCATION
'MASK'

SENSE B =
1

YES - (APPROXIMATION
TO HIGH)

NO

STORE APPROXIMATION IN LOCATION
'TEMP' IN MEMORY

PUT APPROXIMATION
INTO D/A LATCHES
IN COMPLEMENT
FORM

GENERATE NEW
MASK BY RIGHTSHIFTING ONE BIT
POSITION

RECOMPLEMENT
APPROXIMATION;
STORE PRESENT
APPROX IN E-REG

STORE NEW MASK
IN LOCATION 'MASK';
EXCLUSIVEL Y - OR
WITH E-REG TO GET
NEW APPROXIMATION

RESET MASK BIT
POSITION IN APPROXIMATION TO ZERO;
LOAD RESULTANT
APPROX IN E-REG

EXIT

TITLE

1

SCMP.

/SINGLE AID CONVERSION USING D/A'

2
]:

12I€1I21::I.

4

e';:1e;;:~

Pi
P2

5

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P3
t1ASI<

121(1(11

TEt'1P

6
7

e
9 121121121121 0:::

=

=
=
=
=

1
2

NOP
Figure 2CI-I0. Flowchart and Program listing for Low-Cost Converter System

2C1-13

10

(1(1(1:1 C40~)
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:1:? I;:K104 C4~)O
:1J: 0(u:;:16 1:3:
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:15 ~j~3~-::19 ...,-::."::1
:"
:1.6 (1~)t)A (:40:;::
:17 (1(n)C J:t.~

CON'·,·'

:1..:::

(U)I~1[:o

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NE::·::T

1';

(1~~~::1F

CE:t)~)

L..[:OI

(1

::·::PAL

P::;::

LOI

(1

>::PAL.

p-::'
...:.

U)l

~:

::~.- (1:1
.' APPRm~ Cor'lPLETE
.; STATUS TO ACU
.' CHECK· SENSE B
.; SENSE E: HIGH
,; I'tASK TO ACU
.' SHIFT F.:IGHT NASI<
.' STOF.:E NE~n APPRO:'::
.i SET NE::'::T Lm,J OP[:'ER
.; BIT IN E>·::T F.:EG
NASK TO ACU
F.:ESET BIT TO (1
.; APpF.:O>~ TO
REG
.' Jr-tP TO SHIFT r-tASK
.; AN[) SET NE>n BIT
.' E~ :+:
0[103:

00~~1:1

NO ERROR LINES
SOURCE CHECKSUM=4F0F

NS70543

Figure lel-IO (Concluded)

2C1·14

INTERFACING A KEYBOARD TO SC!MP

puts the keycode in the SC/MP Extension Register, and
returns to the calling program.

SC/MP applications that require a keyboard interface usually
use one of two methods to generate keycodes. In one
method, SC/MP is used as a keyboard scanner, whereas in
the other method, SC/MP is interfaced with a keyboard encoder. For either type of interface, programs can be developed for continuous keyboard scan or for using the keyboard as an interrupt device.

System Operation
A fixed address (X'0900) is assigned to the "keyboard peripheral" and when a load (LD) instruction is executed, the
TRI-ST ATE buffers are simultaneously activated. Thus, if
any key (SO through S47) is pressed, one Of the bits (DBO
through DB7) on the data bus appears as a logic' 1'.

When SC/MP is interfaced with an appropriate keyboard
and is supported with the proper software, any application
that can be controlled by alphanumeric inputs is feasible lawn-sprinkler control, home and business lighting, vending
machines, combination locks, kitchen appliances, games,
and so on. Some basic principles of keyboard interfacing
are shown in the following illustrations and are described in
the supporting text.

The program "LOOP" checks for the "nonzero" condition
and provides a deb ounce time of 5 milliseconds. After debounce, the value of the key is determined by updating a
counter in RAM. The counter is incremented by "8" for
each row scanned and by "I" for each column scanned. For
example, assume that S9 (row 2/column 2 of figure 2C2-1)
is pressed. The first row is scanned by the software, and
finding no key pressed, the row counter (row select) is incremented by 8 and the second row is scanned. In this row,
one of the bits in the data word is a logic '1'; accordingly,
the column counter is now incremented by 1 and comparisons are made to determine which switch is pressed - for
this example, it is the second switch (S9) in the column. It
can readily be seen that a different binary code (keycode)
is produced for each switch in the matrix. The keycode is
saved in temporary memory, and the keyboard is tested for
key release by executing a Load Instruction to the keyboard.
This activates all the buffers, and, upon key release, the
keycode is transferred from temporary memory to the Extension Register. The designated pointer then is exchanged
with the Program Counter to return to the calling program.

USING SC/MP AS A KEYBOARD SCANNER
General Description
The keyboard matrix shown in figure 2C2-1 consists of six
rows with eight keys in each row. Functional relationships
between the keyboard and SC/MP can be summarized as
follows. The entire key matrix is scanned by testing input
data to the microprocessor for a value other than zero; this
condition occurs if any key is depressed. After key detect,
a software deb ounce is performed. Then, the program determines the row and the column corresponding to the key,
computes the correct binary code, tests for key release,

2C2-1

TAl ST i\ TE OCT AL
BUFFER OM 81LS96

NRDS

from

SC/MP

----.----------------------------------1

DBO~

OBI

DB2
DATA

t.
SC/MP

DB3
DB..
DBS

------TRI STATE OCTAL
BUFFER 10M 81lS%1

DB6
DB7

ADO
AD 1
AD2
AD3
AD.
ADDRESS

ADS

from

SC/MP

AD6
AD7
ADS
AD9
AD 10

AD 11

AD 11

AD 10
AD 9
AD 8 - -.....01111.
AD 7 - -......jll,.

NOTES:

1. This configuration represents only one of many nys to
build and interface a keyboard scanner. If oth.,. componen11
and interfacing methods are used. electrical specifications
should be the composite equivalent of those shown.
2. Unused pins that can be left unterminated are not shown.

AD 6

Vco, "61--- +SV

NSI0644

Figure 2C2-1. Using SC/MP as A Keyboard Scanner

2C2-2

Software Considerations
The flowchart in figure 2C2-2 and the program listing in
figure 2C2-3 show how SC/MP can be utilized by software
to perform a keyboard scanning function.

NS10545

Figure 2C2-2. Flowchart for SC/MP Interfaced with A 6x8 Keyboard Matrix

2C2-3

.,

'r I T l...E :::'C:HNt·H;;:..·
; ~::;I.. ,,·'j··IF'

fle'IS fI:;

sc.····t··IP ..'

KE'T'E:OAF.:O SCHNNEF.:.

H

lS A 6 BY 8 MATRIX.

,·'f·

....

I",

:.:.'

; TYPICAL MAIN PROGRHM

j 1·'(

::.. :l

; THIS SECTION OF CODE SETS UP THE RAM POINTER
;HND THE POINTER FOR THE SCAN ROUTINE .
.'! '::,

.1./
'! '.. ~

lj (~i;::i :;;::

LL'I
::C! U'::>'(I:::: I ..:·::l-Ij.::.
(I (: ! CI'::i ~:: 1':.

:::: :::.

;::::~:

(,1,):;'1::.:•..:: ....

:':;'-"1

I) U':::: ::!

C:.4·1:::U::1

;,: : ~:i

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:::: ~ .. '

;;::1:::; (:jUOC ..~:F

L. 0:: F.: Ar'1 :;.
~~

H r:: F.:At·1 :;.

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;~:

U) I
::·::PfiL
U> I
::l F ,~;. 0 ::=::
:~~ '1
()(:(>; C:fV::C:

HD I

8:? 1:)1;"':::::::: UJ..

.:·:;HE

?? 1::1f1,?E:

LOOP1 :

L..[:O

::::T

I:~u:~:n

9~::::EU

.J~2:

:::::~~

~::'!Cf?C::

9UFF

..T1"'1F'

::::1::;: 003E
::::? (10::!:F
:::: ::: ~:~ r) .:~. :1..
:::9 1,>,04:;;:0

>::AE::

9k,

O(:~.:.1·4

:i.e:
9UC16
(1 ::t.
HHr:r:::
Ol

; INCR SWITCH BY 8

::::

; ROW DRIVER INTO ACCUM

9::1.

1)1j4~:i

9UF'?

:::12 121 (14 .? Ci: :i:F
9 ::::: 121 I) 4 :::~ i;:~:1..
94 f:11~j4A :::::FW:;,
9 o:::i ~.~ 1:::1 ,:+ C C:::;: J: F
:~16

004E

~K1

97 ~":IC14F ~~CF6
9S 1~~n5:t C~;;:O:1

:3 ')

~:1 (1 ~:i :::::

:~:::

.1.~j~J

1~~n':i4

C:~~O;;,::

H:1:1..
l(j:?
J.(13:

1~1 (1 '::i

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(1(1~i?

C~;::l1::::

~~1()59

~~l

0'·."E F.:

L..OOPi
F.:ELEAS

ILD

S~'J ITCH 0:: ;;:: ::0

::·::AE
F.:ELEH::::: :

JNP
LD
DL.'T'
LD
LCo

::'::F'AL
LD
::-:;PHH
L[)

c:"
....1

ALLK'T'S(J:)
PELEfiS
TENPL o::;;~::o

9121B3:

; COMPARE NEW WITH OLD
; IF 0. KEY RELEASED

TEt1PH 0:: 2::0
J:
S~'H

TCH 0:: 2)

~'~AE

lJ:'~i
1~1fj5B

.' READ KE'T' MATR I X
; SAVE CO[)E
.' DEBOUNCE 5 MS

.:i-

H.14 (10:iA :3:F
:H:1E:

; IF = 0. KEY DECODED
; SAVE CODE IN E REG
; INCR SWITCH VALUE
; RECALL FOR NEXT SHFT

SHIFT
ALLK',.'S 0:: J;)

At'~E

JNZ

.' F.:OJ..J [)F.: I VEF.: TO E REG.
; READ ROW INTO ACCUM
; IF NOT 0. VALID KEY

:;~·JITCH(2)

U:':=: 1::JO::::::) :11:::
:::;:4

;COMPHRE NEW WITH OLD
; IF = 0. INVALID KEY

Jt'lP SCAN

1~)7'

10::::

Figure lCl-3 (Continued)
2C2-6

; F.:ESTORE PTR 3:
.' GET KEYCODE
; SAVE CODE IN E REG
; RETURN TO CALLING
; pr;;:OGRAt'l

:1..0::~

:t::I.. ~;~

.; OHTH HF.:EH

ttl
:1..J.;?
1:1 :~::

l1C

0800

SAVE = 0

.1..:1.?
:i.:l.:::::
:1.:l '::~

CI~:~O::i..

·fl::.t'lPL _...

j-

of:)i:::1 2:

lEI"'if'H ..-

;;~~

122
1:·:'::'
124

0003

SWITCH

0004

KLYMD

128

8900

PERIPH -

:.L?':::'
:i.;~:::t

=
=

3

4

X~0900

t:::::,::,
END

J.3::1.

1·::Ii ... L.~::'/:::;·

O~:~:3:F

LOOP

0~32i

(jlj;::;:f)

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€100[) :+:

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TE.t'lPL

~1001.

0(1~10

Nel ERPOP LINES

SOURCE CHECK5UM=5578
+**DISC SECTORS USED:+::+::+:
F I R::;-r INPUT ::::ECTOF.: HE::·::
f~' I t··lfl!.... INPUT :;::ECTCIF.: HE::<:

--

-

~)292
~~1:;::~~6

Figure lCl-3 (Concluded)

2C2-6

NS10546

USING SC/MP WITH A KEYBOARD (20-KEY) ENCODER
General Description
The keyboard matrix and the 20-key encoder shown in
figure 2C2-4 can be used with SC/MP to provide continuous
keyboard scanning or the keyboard can be used as an interrupt device. For continuous scanning, the 'Sense 8' input to
SC/MP is tested for a 'logic 1', and if this condition is detected, the 5-bit key code is stored in RAM and the program
halts. In a real-life system, the code could be saved in the
Extension Register and control could be transferred to a
user routine that processes the keycode data.
When the keyboard is used as an interrupt device, SC/MP
executes a 'main' program until a 'logic l' (keycode input
available) is detected at the 'Sense A' input. The program
then jumps to an interrupt service routine, which inputs the
code, saves it in the Extension Register, and returns control
to the interrupted program.
System Operation
In figure 2C2-1 where SC/MP is used as a keyboard scanner,
the binary code for each key is computed by the program.
As shown in figure 2C2-4, the TRI-STATE CMOS encoder
(MM74C923) provides all of the key-encoding logic, and, in
addition, it provides switch debouncing and a 2-key rollover
function. The 2-key rollover guarantees that the Data Available Signal at pin 13 goes from a logic 'l' (upon valid key
entry) to a logic '0' - even though a second key is depressed
before the first I-to-O transition is completed. A logic '1'
for the second key will then appear at pin 13 after some
predetermined deb ounce interval. Operation of the key encoder system is very simple and straightforward. When
closure of a key contact is detected, the encoder deb ounces

2C2-7

the key and loads the appropriate binary code into five
TRI-STATE output latches; the presence of this output
data is indicated by driving the Data Available Signal high.
As shown, the Data Available Pin is connected to the Sense
8 input of SC/MP or, if the keyboard is interrupt-driven, to
Sense A. In either case, SC/MP responds by outputting the
assigned keyboard address, and at read-strobe (NRDS) time,
pin 14 (the Output Enable Signal) of the encoder is driven
low. Subsequently, the latched keycode data are read into
the Accumulator.
Software Considerations
Minimum software support for the keyboard encoder shown
in figure 2C2-4 includes a scan (or interrupt service) routine
for inputting data to SC/MP. In more-sophisticated software
systems, the program, in addition to the basic scan function,
may include recognition code for any combination of hexl
command keys and also some sort of debug code to ensure
valid processing of the ·input data. Some software examples
are given in figures 2C2-5 and 2C2~6; a summary of these
programs follows.
Figure 2C2-5
This program uses the Sense 8 input for keyboard interrogation and uses the Extension Register to index the keys;
the keycode data are stored in memory with no processing
involved.
Figure 2C2-6
This program uses Sense A as a keyboard interrupt; the
interrupt service routine gets the keycode, saves it in the
Extension Register, and then returns to the main program.

FRDMAD·
DRESS PORT
OFSC!MP

AD 0

ADll

ADI

AD 10

ADa

AD 9

AD9

AD a

AD 10

AD

AD 11

AD 0

+5V

NOTES:
1. This configuration represents just OMI of
m..,y way. to build and interflc. I key-

board encoder. If other components
end interfleing methods are used. aleetrical .pecificetions should be the
composite equivalent of those shown.
2. Quod 2·input OR _
(OM 74L321. o.

equiv.lent.
3. Unused pin. thlt can be left unt.mi-

nated are not shown.

l-----------__

J----}•••••r-.--

TO SENSE B OR. IF
INTERRUPT·DRIVEN.
TO SENSEA

~:;I ~~ ~~~

PORT

DB3
DB4

NSI0547

Figure 2C2-4. Using SC/MP with A Keyboard (20.Key) Encoder

2C2-8

-Low eo,t Dnelopment System

I",SeIM'.

1.
\.

TITLE

SCAN~

" 20 KE'T' KYBO SCAN "

2
3
4
.1 THIS PROGRAM IS USED WITH THE 74C923 20 KEY
; KEYBOARD ENCODER.
THE PORTION OF THE PROGRAM
; LABELED MAIN IS USED AS A MEANS TO GET TO
; THE KEYBOARD SCAN ROUT I NE.
; SENSE B IS CONNECTED TO THE DATA VALID
; SIGNAL OF THE 74C923.
;20 KEY CODES ARE STORED IN MEMORY.
; THE ROUTINE THEN EXITS TO USER PROGRAM.

5
6
7
8
9

1.0
1.1.
1.2
1.3
1.4
15
16
1.7
'18
1.9
20
21
22
23
24
25
26

0000
0001.
0002
0004
0005
0007
0008
000A
000C
0000

08
04
C400
32
C403
36
C41.4
CA00
05
C402

NOP
DINT
LDI
XPAL
lDI
XPAH
lOI
ST
lEN
lDI

L(RAM)
2

H(RAM)
;PTR 2

2

)("1.4

= OATA

BUFFER

; STORE COUNT
;ENABLE INTERRUPT

(2)

2

Figure 2C2-S. Using Sense B of SC/MP to Input Keycode Data - Flowchart and Program Listing

2C2-9

27
28
29
3'21
3:1.
3:2
3:3
34
35
36
37
38
39
40
41.
42
43
44
45
46
47
48
49
50
51.
52
53
54
55
56
57
58
59
60
61.
62
63
64
65
66
67
68
69
70

000F
001.0
0'211.2
001.3
0'211.5

1Zt1.
C401.
31.
C409
3:5

ENTRY:

XAE
LDI
XPAL
LDI
XPAH

; SET E REGISTER
L(KYBD)
1.
H(KYB[»
1.

=2

; PO INTER 1. = KEYBOARD A[)DRESS

; THE NEXT SECTION OF CODE STARTING WITH
; THE LABEL " SCAN" AND END I NG l..t I TH THE
; INSTRUCTION JNZ RELEASE IS THE ACTUAL
.: TEST I NG FOR KEYBOAR["J I NPUT AND .:::EY RELEASE.

001.6
001.7
001.9
001.B
001.D
001.F
0'2121.
0023
0024
0026

06
D42'3
9C02
90F9
C1.00
D41.F
CA01.
06
[)42121
9CFB

SCAN:

CSA
ANI
JNZ
JMP
INPUT: LD
ANI
ST
RELEAS: CSA
ANI

121028
002A
002C
002D
002E
0030

C201.
CA80
'212
40
F401.
'211.

MAIN:

; MASK TO TEST SENSE B INPUT
; SENSE B = 1..' VALID KEY
; SENSE B = €I, CONTINUE
; GET KEYBOARD
; BLANK HI 3
; SAVE KEYCODE

X"20
RELEAS

;MASK TO TEST SENSE B
; IF ACCUM = 1., LOOP UNTIL
iKEY RELEASED
; GET KEYCODE
; SAVE KEYCODE IN DATA BUFF.

.JNZ

1.(2)
-1.28(2)

LD
ST
CCL
LDE
ADI
XAE

1.

DLD
JNZ

0031. BA00
0033 9CE1.

ENTRY
KYBD
RELEAS

X"2121
INPUT
SCAN
(1.)
X"1.F
1.(2)

;E REGISTER UPDATED FOR USE
;AS INDEX ON DATA BUFFER
.: DECREMENT COUNT

(2)
SCAN

EXIT:

0901.
0300

; AFTER 20 KEYS TAKEN CONTINUE
; USER PROGRAM

KYBD = X"0901.
RAM = X"0300

0000
001.0
0901.
0023

END

*

EXIT
MAIN
SCAN

0035
0028
001.6

*
*

NO ERROR LINES
SOURCE CHECKSUt'1=81.EB

INPUT
RAM

001.D
0300

NS10548

Figure 2C2-S (Concluded)

2C2-10

DISABLE INTER·
RUPT.INITIALIZE
INTERS. THEN EN
ABLE INTERRUPTS

ENTER
USERS
PROGRAM

SAVE CODE IN
EXTENSION
REGISTER

WAIT FOR
KEY RELEASE

ENABLE
INTERRUPTS
READ
KEYBOARD

TITLE

1

2
3
4
5

SCAN1~

,. SCI"MP TO 20 KEY KE'T'BOARD"

;THIS PROGRAM USES SENSE A AS AN INTERRUPT TO
; SCI"MP.. AND WORKS WITH THE 74C923 KEYBOARD ENCODER.
; THE KEY CODE IS NOT PROCESSED
; DEPRESSION OF ANY KEY CAUSES AN INTERRUPT
; THE PROCESSOR THEN GETS THE KEY CODE.

6
7
8
9

10
.; INITIALIZE AND WAIT FOR INTERRUPT

11

12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

0000
0001
0002
0004
0'2105
00'217
0008
000A
000B
000D
000E

08
04
C410
33
C400
37
C401
31
C409
35
05

NOP

OINT
LDI
XPAL
LOI
XPAH
LOI
XPAL
LOI
XPAH
lEN

;DISABLE INTERRUPT
L(KEYSAV)-1
3

H(KEYSAV)
; PTR :1 = INTERRUPT SERVICE

3

L(KYBO)
1

H(KYBD)
1.

;PTR 1. = KEYBOARD ADDRESS
;ENABLE INTERRUPT

Figure 2C2-6. Using Keyboard as Interrupt Device (via Sense A) - Flowchart and Program Usting

2C2-11

; THE NEXT INSTRUCTION SIMULATES A
.; USERS MA I N PROGRAM.
IN TH I S CASE THE
;PROGRAM IS WASTING TIME WAITNG FOR
;AN INTERRUPT FROM THE KEYBOARD.

27
28

29
30
31
32
33
34 000F 90FE

']MP

LOOP:

;AWAITING INTERRUPT

LOOP

35

36
; THE FOLLOWING CODE IS THE INTERRUPT
; SERVICE.
THIS ROUTINE GETS THE KEYCODE.
;SAVES IT IN THE E REGISTER AND RETURNS
; TO THE MA I N PROGRAM.

37

38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

0011
0013
0015
0016
0017
0019

C100
D41F
01
06
D410
9CFB

KEYSAV: LD
ANI
XAE
RELEAS: CSA
ANI
']NZ

(1)
X'" iF

; GET KEYCODE
; BLANK HI 3
; SAVE CODE IN E REG

X'" 10
RELEAS

.; MASK TO TEST SENSE A
; J..JA I T FOR KEY RELEASE

;AT THIS POINT THE USER SHOULD SAVE
; THE KEYCODE IN TEMP STORAGE. OR
; CONTINUE TO PROCESS THE CODE IN
;THE INTERRUPT ROUTINE

001B C702

LD

@2(3)

001D 05
001E 3F

lEN
XPPC

3

001F 90F0

']MP

KEYSAV

0901
0000

SCA~1 SC~MP

KEYSAV
RELEAS

KYBD

; MODIFY P3 TO SKIP LOOP
.; AND CONT I HUE MA I N PROG.
;ENABLE INTERRUPT
; RETURN TO MA I N PROG.
; WITH KEYCODE IN E REG.

= X"'0901

END
TO 2a KEY KEYBOARD

0011
0016

KYBD

0901

LOOP

000F

.NO ERROR LINES
SOURCE CHECKSUM=8D75
NS70549

Figure 2C2-6 (Concluded)
2C2-12

USING SC/MP WITH THE MMS740
(90-KEY) ENCODER
General Description
Figure 2C2-7 shows one way in which SC/MP might be
interfaced to a relatively large key matrix. This particular
scheme uses a 90-key encoder with supporting circuit peripherals, a unified bus comparator for address assignment,
and a TRI-STATE octal output buffer. The encoder is capable of providing a 9-bit output code; however, in figure
2C2-7, only 8 bits are used - DBO through DB6 for keycode
information and DB7 for parity. The encoder also provides
internal switch debouncing and a 2-key (or N·key) rollover
function.
System Operation
Clock requirements for the encoder are supplied by an
LM555 oneshot; this circuit provides a suitable operating
frequency. The shift, shift lock, and special-character con·
trol functions are implemented, respectively, by switches

2C2·13

SI, S2, and S3; a shift·lock indicator is provided also. The
encoder is operated in the pulse data strobe mode; hence,
when valid data are entered by the keyboard, the valid-data
'flag' (pins 13/14) is latched for timing compatibility with
the Sense A (interrupt mode) or the Sense B (scan mode)
inputs. For either operating mode, SC/MP responds by out·
putting the assigned keyboard address, and at read·strobe
(NRDS) time, the output of the TRI·STATE buffer is en·
abled. Accordingly, the keycode data (BOO through BD7) is
read into SC/MP.
Software Considerations
Software requirements for the MM5740 system could be
similar to those shown in figure 2C2-5 (scan mode) and
figure 2C2-6 (interrupt mode). In some applications, the
keycode data can be in..terpreted by more than one program.
For instance, one program might implement a quality con·
trol function, another could use the same data for display
purposes, while a third program could use the data for sta·
tistical analysis.

NOTES:
1. This configuration represellts only one of
many ways 10 bUild and interface a keyboard
encoder, If other components and interfacing

methods are used, electrical specifications
should be the composite equivalent
of those shown.

2. Timer (lM5551. or equivalent.
3.

I!!l
(32]

•
•

au AD

2·lnput OR Gate 10M 74321. or

equivalent.

-'2V

4. Triple 3·lnl)ut NAND Gate 10M 74101.
Qrequlvalerll.
5. HEX Converter 10M 7404), or equivillent.
6. If SC/MP chip IS not buttered. low· power
devices are required-see figure ,·8 for

+5V

buffered SC/MP chip.

10..,1

+5V

BOO ......
BD'~

BD 2 .......
8D3 --rODATA
PORT
SC/MP

804......

BD 5 ......

..•
~

~

~Y6y,

I I I I

29

B.~
OS

DB7~:

13

,

G1

Y7~8D6
VB

16

__

BD 7 ......

+5V

5'

'so"

~ '50"
AD11
AD 10

AD 9
AD •

33K

NOTE

AD

,

2
AD 0

2oop'

+5V

~~p -=~.::========================================------------------------------------------------------------~~

NRDS FROM

INITIALIZE -

Figure 2C2-7. Interfacting SC/MP with the MMS740 (90-Key) Encoder

NS10550

AN INTERRUPT-DRIVEN
KEYBOARD/DISPLAY SYSTEM
General Description
The preceding applications (figures 2C2-1, 2C2-4, and
2C2-7) show how SC/MP can be used to input and process
data from a keyboard. This application shows how SC/MP
can be used to develop a functional keyboard/display system that is interrupt-driven; a block diagram of the system
is shown in figure 2C2-8. Besides SC/MP, the system hardware consists of a 20-key matrix (16 hexadecimal and
4 command keys), a 20-key encoder, a 6-digit/7-segment
LED display that is software multiplexed, and appropriate
memory, decode, and buffer/driver devices. System software consists of a monitor program that allows user to
read or modify (write into) a memory location, to execute
a program starting at any address, and to abort the interrupt service at any time. Four main subroutines are callable

from the keyboard: SCAN, MUXDIS, G4HEX,andG2HEX.
The SCAN subroutine gets valid keycode data from the
20-key matrix; also, this subroutine automatically calls the
MUXDIS subroutine, which services the LED display. The
G4HEX and G2HEX subroutines also call up SCAN and
get, respectively, four hexadecimal characters and two
hexadecimal characters from the keyboard. The hexadecimal characters are stored in a temporary table (six consecutive memory locations) and then are packed in three
contiguous memory locations with the following assignments: HIGH ADDRESS, LOW ADDRESS, and DATA.
Memory assignments for the entire keyboard/display system are shown in the memory map of figure 2C2-8. The
foregoing monitor program is resident in the 512-by-8
PROM; an additional 30 words of RAM also are required
for this program. Memory services for the keyboard and display peripherals are as shown.

2C2-15

FROM ADDRESS
PORT OF SCIMP

l_

AD3
AD'
ADO
AD'
ADS
; ;;;;AD.
AD.

I
..

FROM DATA PORT
Of SCMP

ADa
AD.
AD'
AD ,.
AD 11

081
D• •

..

082

..
•
..

DB3
DB4
DB5

•
•

oB6
DB7

~

~:b1E tc~~~BE (NWDSI

•

READ STROBE INROS)
FROM SC/MP

I

II

MEMORY MAP
X'FeF

X'FIF

x',a

X'FII
X'FIA
X'EF.
X'EID
X'ElI

X'EM

x'Im

IxlT
IMTIt • •IIPT

~

...r:-a

G)

X1)'7

"014

.,,,.,.,,-41------

' - - - - - - - - t•• ~~~:: A

NS10557

Figure 2C2-8, Interrupt-Driven Keyboard/Display System-Block Diagram and Memory Map

System Operation

MODIFY Mode

Anyone of the 20 keys can be pressed to initiate an interrupt, and when this condition occurs, the six LED indicators
display a OOdOOO as an 'interrupt-recognition' code.

1.

Depress and release MODIFY key.

2.

Enter address by 'press-and-release' of any four hexadecimal keys; enter data in selected address by 'pressand-release' of any two hex keys. Before new data is
entered, display will show hexadecimal address and
'old' data; after modification, display will show same
address and 'new' data.

3.

After address is entered, it can be incremented and display updated by successively pressing MODIFY key.

NOTE
Although the depression of any key causes
an interrupt, the interrupt will automatically abort if the key is not a legitimate
command - thus, the operator may not
see the initial message OOdOOO.
Once the interrupt is accepted, the keyboard/display system
can be utilized in anyone of three modes - READ, MODIFY, and EXECUTE; a fourth mode (ABORT) is used to
return control to the interrupted program. The first key
entered must be a legitimate READ, MODIFY, or EXECUTE
command; if the key entry is invalid, or if a valid command
is followed by an illegal sequence of keys, the interrupt service is exited just as though the' ABORT' key were pressed.

NOTE
If, after entry of each modify command,
user fails to enter 2-key hexadecimal data,
interrupt service is terminated and control
is returned to interrupted program.

4.

Operating procedures and a summary of results for each
command key are given below.

To transfer from modify mode to read mode, simple
'press-and-release' READ key after completion of any
legitimate modify command.

XECUTEMode
READ Mode
1.

Depress and release READ key.

2.

Enter address by 'press-and-release' of any four hexadecimal keys; display will show 4-digit hexadecimal
address and 2-digit hexadecimal data in that address.
After address is entered, it can be incremented and display updated by successively pressing READ key.

3.

Depress and release XECUTE key.

2.

Press and release four hexadecimal keys to specify
point-of-entry address and to transfer control to user's
program.
NOTE
Entry errors for first three keys can be
nullified by pressing ABORT and then repeating operating sequence for XECUTE.
Once fourth key is entered and address is in
error, system may require reinitialization.

To modify a memory location while in read mode, proceed as follows:
Press MODIFY key and then whichever two hexadecimal keys are required for data modification.
Before new data are entered, display will show hexadecimal address and 'old' data; after modification,
display will show same address and 'new' data.

4.

1.

Return to interrupted program by 'press-and-release' of
ABORT key.

ABORT Mode
1.

Depress and release ABORT key.

2.

Interrupt service is exited and control is transferred to
interrupted program.

2C2-17

Software Considerations
The following entry and subroutine-calling codes (or their
functional eqUivalents) must be implemented in the users
program if the keyboard/display is used for anything other
than a passive monitor.
1.
2.
3.
4_
5.

Entry Code to INTERRUPT SERVICE Routine
Calling Code for MUXDIS Subroutine
Calling Code for Keyboard SCAN Routine
Calling Code for G4HEX Routine
Calling Code for G2HEX Routine

Purpose:

Coding schemes to satisfy each of the preceding requirements are described in the listings that follow_ Figures
2C2-9 through 2C2-12 that follow the listings provide a
software flowchart for each subroutine and other relevant
code; figure 2C2-13 provides a complete printout of the
monitor program.
System Schematics
Pin-to-pin wiring of the keyboard/display system is shown
schematically in figure 2C2-14.

Calling Interrupt Service Routine via Pointer 3.

Conditions: Following Code must appear somewhere in users program.
Code:

•
•
•

LDI
XPAL
LDI
XPAH

;1

USERS PROGRAM

X'FF

3
X'D

3

lEN

•

•

;CONTINUE USERS PROGRAM
;WHEN ANY KEY IS DEPRESSED, USERS PROGRAM IS
;INTERRUPTED AND KEYBOARD MONITOR PROGRAM IS
;EXECUTED

•

Purpose:

;GET LOW-ORDER BYTE OF INTERRUPT ADDRESS
;PUT IN POINTER REGISTER 3
;GET HIGH-ORDER BYTE OF INTERRUPT ADDRESS
;PUT IN POINTER REGISTER 3
;POINTER 3 NOW LOADED WITH '1-LESS' THAN THE ADDRESS OF
;THE INTERRUPT SERVICE ROUTINE
;ENABLE INTERRUPT

Call MUXDIS Subroutine.

Conditions: Locations X'D8a through X'D85 must be preloaded with the information to be displayed the hex digit in
X'D8a and least Significant digit in X'D85; Pointer 2 must be equal to X'D8a. This subroutine saves the contents
of calling Pointer I upon entry and restores this pointer upon exit.
Code:

•
•

;1

USERS PROGRAM

•

RETURN:

DINT
LDI
XPAL
LDI
XPAH

X'55
1
X'F

XPPC

1

<-------->
lEN

•
•

•

;DISABLE INTERRUPT
;GET LOW-ORDER BYTE OF MUXDIS SUBROUTINE ADDRESS
;PUT LOW-ORDER BYTE IN POINTER 1
;GET HIGH-ORDER BYTE OF MUXDIS SUBROUTINE ADDRESS
;PUT HIGH-ORDER BYTE IN POINTER 1
;POINTER 1 NOW LOADED WITH '1-LESS' THAN THE ADDRESS
;OF THE MUXDIX SUBROUTINE
;CALL MUXDIS SUBROUTINE
;INSTRUCTION TO BE EXECUTED UPON RETURN FROM MUXDIS
;ENABLE INTERRUPT SO MONITOR PROGRAM CAN BE EXECUTED
;UPON ENTRY FROM KEYBOARD

;1

CONTINUE USERS PROGRAM

2C2·18

Purpose:

Calling Keyboard SCAN Subroutine via Pointer 3.

Conditions: Pointer 2 must be loaded with X'D80. If Pointer 2 is already being used as the RAM pointer, the following code
is required to implement the subroutine call.
Code:

DINT
LDI
XPAH

H(USER RAM BASE)
2

XAE
LDI
XPAL

L(USER RAM BASE)
2

ST
LDE
ST

P2SAV(2)

LDI

X'29

XPAL

3

ST
LDI
XPAH

P2SAV+2(2)
X'F
3

ST

P2SAV+3(2)

LDI
XPAL
LDI
XPAH
XPPC

X'SO
2
X'D
2
3

P2SAV+1(2)

<

>

LDI
XPAH
LDI
XPAL
LDE
ST
LD
XPAH
LD
XPAL
LD
XAE
LD
XPAH
LDE
XPAL

H(USER RAM BASE)
2
L(USER RAM BASE)
2

•

ESAV(2)
P2SAV+3(2)
3
P2SAV+2(2)
3
P2SAV+1(2)
P2SAV(2)
2
2

;DISABLE INTERRUPT
;GET HIGH-BASE RAM ADDRESS IN ACCUMULATOR
;PUT HIGH-BASE RAM ADDRESS IN POINTER 2 AND 'OLD'
;P2-HIGH IN ACCUMULATOR
;TEMPORARI LY SAVE 'OLD' P2-HIGH IN EXTENSION
;GET LOW-BASE RAM ADDRESS IN ACCUMULATOR
;PUT LOW-BASE RAM ADDRESS IN POINTER 2 AND 'OLD'
;P2-LOW IN ACCUMULATOR
;SAVE 'OLD' P2-LOW IN P2SAV
;PUT 'OLD' P2·HIGH IN ACCUMULATOR
;SAVE 'OLD' P2-HIGH IN P2SAV+1 WHERE 'P2SAV' AND
;'P2SAV+1' ARE RESERVED RAM LOCATIONS WITHIN
;BASE-VALUE DISPLACEMENT RANGE OF USER RAM
;LOAD ACCUMULATOR WITH '1-LESS' THAN LOW-ORDER
;ADDRESS OF SCAN ROUTINE
;PUT LOW-ORDER ADDRESS OF SCAN IN POINTER 3 AND
;OLD' P3-LOW IN ACCUMULATOR
;SAVE 'OLD' P3-LOW IN P2SAV+2(2)
;GET HIGH-ORDER ADDRESS OF SCAN ROUTINE
;PUT HIGH-ORDER ADDRESS OF SCAN IN POINTER 3 AND
;'OLD' P3-HIGH IN ACCUMULATOR
;SAVE 'OLD' P3-HIGH IN P2SAV+3 WHERE 'P2SAV+2' AND
;'P2SAV+3' ARE RESERVED RAM LOCATIONS WITHIN
;BASE-VALUE DISPLACEMENT RANGE OF USERS RAM
;GET LOW-ORDER RAM-BASE ADDRESS FOR SCAN
;PUT LOW-ORDER ADDRESS IN POINTER 2
;GET HIGH-ORDER RAM-BASE ADDRESS FOR SCAN
;PUT HIGH-ORDER ADDRESS IN POINTER 2
;CALL SCAN ROUTINE
;RETURN FROM SCAN WITH KEYCODE IN EXTENSION REGISTER
;GET HIGH-BASE RAM ADDRESS IN ACCUMULATOR
;RESTORE HIGH-BASE RAM
;GET LOW-BASE RAM ADDRESS IN ACCUMULATOR
;RESTORE LOW-BASE RAM
;GET KEYCODE IN ACCUMULATOR
;SAVE KEYCODE IN USERS RAM
;GET 'OLD' HIGH-ORDER CONTENT OF POINTER 3
;RESTORE 'OLD' P3-HIGH
;GET 'OLD' LOW-ORDER CONTENT OF POINTER 3
;RESTORE 'OLD' P3-LOW
;GET 'OLD' LOW-ORDER CONTENT OF P2
;TEMPORARI L Y SAVE 'OLD' P2-LOW IN EXTENSION
;GET 'OLD' HIGH-ORDER CONTENT OF P2
;RESTORE 'OLD' HIGH-ORDER CONTENT OF POINTER 2
;GET 'OLD' P2-LOW FROM EXTENSION
;RESTORE 'OLD' LOW-ORDER CONTENT OF POINTER 2
;CONTENTS OF P2 IS NOW THE SAME AS IT WAS BEFORE
;CALLING SCAN ROUTINE
;CONTINUE USERS PROGRAM

•

•
2C2-19

Purpose:

How to save and restore pointers when calling
G4HEX Subroutine via Pointer 1.

Conditions: Pointer 3 must contain SCAN address and
Pointer 2 must point to X'D80 (RAM base for
code that follows). Locations SAV3LO/
SAV3HI must be preloaded by the user for
program return in case of an entry error from
keyboard. Pointer 2 is the RAM pointer for
the users program; thus, a few RAM locations
within displacement range of the base-value
of the users fixed RAM must be reservedsee illustration.

+127 BYTE
} DISP

USERS
FIXED
RAM
-127 BYTE
} DISP

USERS
CHANGING
RAM

Code:

•
•
•

DINT
LDI
XPAH
XAE
LDI
XPAL

ST
LDE
ST
LDI
XPAL
ST
LDI
XPAH
ST

LDI
XPAL
ST
LDI

; { USERS PROGRAM
;DISABLE INTERRUPT
H(USERS RAM BASE) ;GET HIGH-BASE RAM ADDRESS IN ACCUMULATOR
;PUT HIGH-BASE RAM ADDRESS IN POINTER 2 AND 'OLD'
2
;P2-HIGH IN ACCUMULATOR
;TEMPORARILY SAVE 'OLD' P2-HIGH IN EXTENSION
L(USERS RAM BASE) ;GET LOW-BASE RAM ADDRESS IN ACCUMULATOR
;PUT LOW-BASE RAM ADDRESS IN POINTER 2 AND 'OLD'
2
;P2-LOW IN ACCUMULATOR. POINTER 21S NOW EQUAL
;TO USERS RAM BASE.
;SAVE 'OLD' VALUE OF P2-LOW
P2SAVL(2)
;PUT 'OLD' VALUE OF P2-HIGH IN ACCUMULATOR
P2SAVH(2)
;SAVE 'OLD' VALUE OF P2-HIGH
;LOAD ACCUMULATOR WITH '1-LESS' THAN LOW-ORDER
X'29
;ADDRESS OF SCAN ROUTINE
;PUT LOW-ORDER ADDRESS OF SCAN IN POINTER 3 AND
3
;'OLD' P3-LOW IN ACCUMULATOR
P3SAVL(2)
;SAVE 'OLD' P3-LOW IN P3SAVL(2)
;GET HIGH-ORDER ADDRESS OF SCAN ROUTINE
X'F
;PUT HIGH-ORDER ADDRESS OF SCAN IN POINTER 3 AND
3
;OLD' P3-HIGH IN ACCUMULATOR
P3SAVH(2)
;SAVE 'OLD' P3-HIGH IN P3SAVL(2) WHERE 'P3SAVL(2)'
;AND 'P3SAVH(2)' ARE RESERVED RAM LOCATIONS WITHIN
;BASE-VALUE DISPLACEMENT RANGE OF USERS RAM
X'S2
;LOAD ACCUMULATOR WITH '1-LESS' THAN LOW-ORDER
;ADDRESS OF G4HEX SUBROUTINE
;PUT LOW-ORDER ADDRESS OF G4HEX IN POINTER 1 AND
;'OLD' P1-LOW IN ACCUMULATOR
P1SAVL(2)
;SAVE 'OLD' P1-LOW
X'F
;GET HIGH-ORDER ADDRESS OF G4HEX SUBROUTINE

2C2-20

XPAH

CALL:

ST
LDI
XPAL
LDI
XPAH

P1SAVH(2)
X'80
2
X'D
2

LDI
ST

L(CALL)
X'F8(2)

XPPC
DINT
LDI
XPAH
LDI
XPAL
LD
XPAL
LD
XPAH
LD
XPAL
LD
XPAH
LD
XAE
LD
XPAH
LDE
XPAL

lEN

•

H(USER RAM BASE)
2
L(USER RAM BASE)
2
P3SAVL(2)
3
P3SAVH
3
P1SAVL(2)
1
P1SAVH(2)
1
P2SAVL(2)
P2SAVH(2)
2
2

;PUT HIGH-ORDER ADDRESS OF G4HEX IN POINTER 1
;AND 'OLD' P1-HIGH IN ACCUMULATOR
;SAVE 'OLD' P1-HIGH
;GET LOW-ORDER RAM BASE FOR G4HEX CODE
;PUT LOW-ORDER BYTE IN POINTER 2
;GET HIGH-ORDER RAM BASE FOR G4HEX CODE
;PUT HIGH-ORDER BYTE IN POINTER 2. POINTER 2
;NOW CONTAINS BASE RAM ADDRESS.
;GET LOW-ORDER CALLING ADDRESS FOR G4HEX
;LOCATIONS X'DF8/X'DF9 ARE ESCAPE ROUTES IN CASE
;OF ERROR AND MUST BE LOADED WITH THE ADDRESS OF
;USERS PROGRAM WHERE THE CALL TO G4HEX OCCURS.
;CALL G4HEX SUBROUTINE
;DISABLE INTERRUPT
;RETURN FROM G4HEX

;POINTER 2 NOW EQUAL TO BASE ADDRESS OF USERS RAM
;GET 'OLD' LOW-ORDER CONTENT OF POINTER 3
;RESTORE 'OLD' P3-LOW
;GET 'OLD' HIGH-ORDER CONTENT OF POINTER 3
;RESTORE 'OLD' P3-HIGH
;GET 'OLD' LOW-ORDER CONTENT OF P1
;RESTORE 'OLD' P1-LOW
;GET 'OLD' HIGH-ORDER CONTENT OF P1
;RESTORE 'OLD' HIGH-ORDER CONTENT OF POINTER 1
;GET 'OLD' LOW-ORDER CONTENT OF P2
;TEMPORARI LY SAVE 'OLD' P2-LOW IN EXTENSION
;GET 'OLD' HIGH-ORDER CONTENT OF P2
;RESTORE 'OLD' HIGH-ORDER CONTENT OF POINTER 2
;GET 'OLD' P2-LOW FROM EXTENSION
;RESTORE 'OLD' LOW-ORDER CONTENT OF POINTER 2
;CONTENTS OF P2 IS NOW THE SAME AS IT WAS BEFORE
;CALLING G4HEX ROUTINE
;ENABLE INTERRUPT
;CONTINUE USERS PROGRAM

•
•

Return Status: Upon return to users program, the G4HEX Subroutine has loaded and packed 4-hex characters as indicated
below.

2C2-21

Purpose:

How to save and restore pOinters when calling G2HEX Subroutine.

Conditions: Setup and control of pointers 1,2, and 3 and the escape locations are similar to their functional counterparts in
parts in the preceding G4HEX subroutine.
Code:

Same as G4 HEX code.

Return Status: Upon return to users program, the G2HEX subroutine has loaded and packed 2-hex characters as indicated
below.

o

MODE STATUS:
X'OO No Command Received
X'01 'Mod' PreViously Received
X'02 'Rd' Previously Received

ENTER INTERRUPT
SERVICE

YES

YES

ENTER READ
SUBROUTINE

NS70552

Figure 2C2-9. Flow Diagram for Interrupt Service Routine

2C2-22

,...-------=

YES

I MOOE STATUS

--------,
MODE STATUS = I

.
IL ________
x'o2

_________
JI
X·O,

YES

YES

INCREMENT ADDR;
UPDATE ADDR
DISPLAY TABLE

YES

SET MODE STATUS
WORD' X·O,

SET MODE STATUS
WORD=- X'02

INCREMENT ADDR
AND UPDATE
DISPLAY

NS70585

Figure 2C2-10. Flow Diagrams for READ, MODIFY, XECUTE, and ABORT Subroutines

2C2-23

YES

YES

NS10553

Figure 2C2-11. Flow Diagrams for G4HEX and G2HEX Subroutines

2C2-24

iiiiiiiiDD

.I.)~I£ ilDilmU

ENTER
SCAN/MUXDIS
SUBROUTINES

SETUP PI TO CALL
MUXDIS ROUTINE

MODIFY P3 FOR
AUTO·INDEXING;
SAVE 'OLD' P3

GET 4·BIT KEYCODE
BY AUTO·INDEXING
P2.

NO

YES
SHIFT CODE 4·PLACES
LEFT FOR MEM PACK;
SAVE IN E·REG

REPLACE LOOP
COUNT IN Pl·LOW

GET NEXT 4·BIT
CODE AND 'OR' WITH
CONTENTS OF E·REG

GET KEYCODE
AND SAVE IN
LOCATION 'E SAVE'

STORE PACKED CODE
AUTO·INDEXED
WITH P3

NO

YES

RESTORE Pl, P2, & P3;
RETURN TO CALLING
ROUTlNE·READ, MOD·
IFY, OR XECUTE

PUT KEYCODE IN
E·REG; RETURN TO
CALLING PROGRAM

NS70554

Figure 2C2-12. Flow Diagrams for SCAN/MUXDIS and DONE Subroutines

2C2·25

TITLE

1.

KYDISI,

~

KYBD & DISPLY

~

2
3
4
5
6
7
8

;THIS ROUTINE IS AN INTERRUPT SERVICE.
WHEN ANY KEY
; IS PRESSED, THE PRESENT PROGRAM IS INTERRUPTED
; AND THE KEYBOARD & DISPLAY ARE SERVICED UNTIL AN
; ILLEGAL ENTRY IS MADE OR THE ABORT KEY IS PRESSED.
;A STATUS REGISTER IN RAM INDICATES WHETHER
; READ OR MODIFY MODES CHOSEN

9

1.0
1.1.
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
20
21.

;USERS MAIN PROGRAM MUST LOAD POINTER 3
;WITH X~0DFF OR X~0E5C AND ENSURE THAT
; INTERRUPTS ARE ENABLED WHEN KEYBOARD
; CONTROL I S DES I RED.

22

23
24
25
26
27
28
29
30
31.
32

; COMMANDS
; MODIFY
; XECUTE
; READ
; ABORT
0E00

44

45
46
47
48
49
50
51.
52
53
54

X~1.0
X~1.1.
X~1.2

X~1.3

=X~0E00

;LOCATIONS ~SAVE~ THRU ~SAVS~ ARE USED
;TO SAVE THE STATUS OF THE INTERRUPTED
; PROGRAM.

33

34
35
36
37
38
39
40
41.
42
43

=
=
=
=

0DFF
0DFE
0DFD
0DFC
0DFB
0DFA
0DF9
0DF8
0DF7
0D80
FFFF
0000

SAVA:
= · -1.
SAVE:
= · -1.
SAV1.LO:
= · -1.
SAV1.HI:
= · -1.
SAV2LO:
= · -1.
SAV2HI:
= · -1.
SAV3LO:
= · -1.
SAV3HI:
= · -1.
SAYS:
= · -1.
RAM
= WD80
KYBD
= -1.
LEOS
= WD00
; THE NEXT GROUP OF EQUATE STATEMENTS
; DEFINE TEMPORARY WORKING RAM USED

Figure 2C2-13. Program Listing for Intemapt-Driven Keyboard/Display System

2C2-26

55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109

; WITH POINTER 2

0000
0006
0007
0008
0009
000A
000B
000C
0000
000E
000F
0010
0011
0012
0013
0014
0E00

TABLE
STATUS
HAD DR
LADDR
DATA1
LTEMP2
HTEMP2
SA Vi
SAV2
INDX
ESAV
L03
HI3
CNT
SAVL1
SAVL2

=0
= 6
=7
=
=
=
=
=
=
=
=
=
=
=
=
=

8
9

X~A

X/B
X~C

X~D

X"'E
X~F

W10

X"'11
X~12

X,013
W14

= WE00

0E00
0E02
0E03
0E05
0E06
0E08
0E0A
0E0B
0E0D
0E0F
0E10
0E12
0E14
0E15
0E17
0E19
0E1A

C8FF
40
caFB
06
C8F1
C455
31
C8F2
C40F
35
C8EC
C480
32
C8E6
C40D
36
C8E0

INTRPT: ST
LDE
ST
CSA
ST
LDI
XPAL
ST
LDI
XPAH
ST
LDI
XPAL
ST
LDI
XPAH
ST

0E1C
0E1E
0E1F
0E21
0E23
0E24
0E26
0E28
0E2A
0E2C

C429
33
C8DA
C40F
37
C8D4
C400
CA00
CA01
CA04

LDI
XPAL
ST
LDI
XPAH
ST
LDI
ST
ST
ST

SAVA

; SAVE ACCUM

SAVE

; SAVE E REG I STER
; GET STATUS
; SAVE STATUS REGISTER

SAYS
L::(2)
TAE:LE+3:(2 :>
::< "'[)
TABLE+2(2)
1
CMLOOP
IZt
STATUS(2)
SA'v'lLO
1
SA'v'lHI
1
SA'v'2LO
SA'v'2HI
2
SA'v'3:LO
3
SAV3HI
3
SAVS
SAVE
SA'v'A
]:

JMP

INTFi:PT

L(G4HEX)-1.
1
H(G4HEX)
1.
1.
LADDR(2)
1
HADDFi:(2)
1.
L< I NTRPT)-1.
3:
H( INTF.:PT)

C482
3:1
C41ZtF
3:5
~3E65 3D
1Z1E66 C21Zt8
1Z1E68 31
1Z1E69 C21Zt;.IZtE6B 35
IZtE6C C4FF
IZtE6E 33:
1Z1E6F C4~)E
IZtE71 37
1Z1E72 C5FF
IZtE74 1Zt5
IZtE75 3:[)

XECUTE: LDI
XPAL
LDI
XPAH
XPPC
LD
XPAL
LD

>~PPC

1

IZtE76 3:F
IZtE77 4121
IZtE78 E413:

CMLOOP: XPPC
LDE
XRI

3:

LDI
>~PAL

LDI
XPAH
LD
lEN

.; DISPLAY "IZtIZtD01Zt1Zt-; ZERO STATUS BITS

; PTf': 1 RESTORED

2

~

-'"

1]1-1(1)

.; PTR 2 RESTORED

; PTR 3: RESTORED
.; GET OLD STATUS
.; STATUS REG RESTORED
.; GET OLD E REGISTER
.;E REG RESTORED
; GET OLD ACCUM
; ENABLE INTERRUPTS
; RETURN TO I NTERFi:UPTED
; PROGRAM

; GET 4 [>IGIT HEX ADDR.
; GET LO 8 AD[)R
.; GET HI 8 ADDR

; RESTORE INTERRUPT POINTER
; DECREt1ENT PC PFi:IOR TO FETCH
; ENABLE I NTEFi:RUPT
; E>~ECUTE USERS PROGRAM
.; CALL SCAN
.; GET CODE
.; MASK TO TEST

::<'"13
Figure lC2-13 (Continued)

2C2-28

ABORT KEY

1.65
1.66
1.67
1.68
1.69
1.70
1.71.
1.72
1.73
1.74
1.75
1.76
1.77
1.78
1.79
1.80
1.81.
1.82
1.83
1.84
1.85
1.86
1.87
1.88
1.89
1.90
1.91.
1.92
1.93:
1.94
1.95
196
1.97
198
1.99
200
201.
202
203
204
205
206
207
2138

209
2113

211
21.2
213

21.4
215
21.6
21.7
218
21.9

0E7A
0E7C
eE7D
eE7F
0E81
0E82
0E84
0E86
0E87
0E89
0EE:E:

.;

~~ECUTE
~'~"·1.2

F:EAD

T7

JMP

E~{IT

.JZ
LDE

98(:1.
40
E41.0
98€1(:
40
E41.1.
98D9
40
E41.2
986E:
90E:0

.; GET STATUS E:IT
; IF 1., THIS KMODE
;PREYIOUSLY ENTERED
; IF 121, MODIFY ENTERED
.; FOR FIF:ST TIME
; READ WAS ENTERED
;SET MODE STATUS IF
;THIS IS 1.ST ENTRY

H(G4HE~<:)

; GET 4 HEX CHARACTERS

H(G2HE~<)

1
1.
LADDF:O::2)
1
HADDF:(2)
1.
DATA1.(2)
(1.)
G2DAT1

; UPDATED ADDRESS RESTORED
;GET PACKED DIGITS
; LOCATION MODIFIED

;THIS SECTION OF CODE UPDATES THE ADDRESS POINTER
; AND THE DISPLAY TAE:LE UPON SUCCESSIVE COMMAND
.; KE'T' ENTR I ES
Figure 2C2-13 (Continued)

2C2-29

220
221.
222
223
224
225
226
227
228
229
230
231.
232
233
234
235
236
237
238
239
240
241.
242
243
244
245
246
247
248
249
250
251.
252
253
254
255
256
257
258
259
260
261.
262
263
264
265
266
267
268
269
278
271.
272
273
274

LINK:
JMP
UPDATE: CCL
LD
ADI
ST
CSA
ANI
J2
LD
CCL
ADI
ST
PUTC:
LD
ANI
ST
LD
SR
SR
SR
SR
ST
LD
ANI
ST

CMLOOP

0EBD
0EBF
0EC0
0EC2
0EC4
0EC6
0EC7
0EC9
0ECB
0ECD
0ECE
0ED0
0ED2
0ED4
0ED6
0ED8
0EDA
0EDB
0EDC
0EDD
0EDE
0EE0
0EE2
0EE4

90B7
02
C208
F401.
CA08
06
0480
9807
C207
02
F401.
CA07
C208
D40F
CA03
C208
1.C
1.C
1.C
1.C
CA02
C207
D40F
CA01.

0EE6
0EE8
0EE9
0EEA
0EEB
0EEC

C207
1.C
1.C
1.C
1.C
CAe0

LD
SR
SR
SR
SR
ST

HADDR(2)

0EEE
0EF0
0EF2
0EF4

C206
0402
98B6
901.0

LD
ANI
J2
JMP

STATUS(2)

LADDR(2)
1.
LADDR(2)

; INCREMENT LO ADDRESS

W80

; MASK TO TEST

CARRY~LINK

PUTC
HADDR(2)
1.
HADDR(2)
LADDR(2)
X'F
TABLE+3(2)
LADDR(2)

TABLE+2(2)
HADDR(2)
X'F
TABLE+1.(2)

TABLE(2)

; INCREMENT HI ADDRESS
; BLANK UPPER 4
; CHANGE ADDR DISPLAY LSD

; CHANGE ADDR DISPLAY 2ND LSD
;3RD LSD ADDR INTO
; 0 I SPLAY TABLE

; MSD ADDR INTO
; 0 I SPLAY TABLE

2

DATA
G2DATA

;GET 2 HEX DATA & DISPLAY

LD
ANI
JN2

STATUS(2)

; GET PROGRAM STATUS WORD

0EFC C206
0EFE 0401.
0F00 9806

LD
ANI
J2

STATUS(2)
1.
READ1.

8F82
8F04
0F06
0F08
0F8A

LDI
ST
JMP
LDI
ST

STATUS(2)
G2DATA

0EF6 C206
0EF8 0402
0EFA 9CC3

C482
CA06
980B
C482
CA86

READ:

READ1.:

2

UPDATE

;IF 1. THIS KMODE
;PREVIOUSLY ENTERED
;MASK TO TEST MODIFY
; IF 0. READ ENTERED FOR FIRST
; TIME

2

; MODIFY WAS ENTERED

2

STATUS(2)
Fipre lCl-13 (Continued)

2C2-30

; SET MODE STATUS WORD

275
276
277
278
279
280
281.
282
283
284
285
286
287
288
289
290
291.
292
293
294
295
296

0F0C
0F0E
0F0F
0F1.1.
0F1.2
0F1.3
0F1.5
0F1.6
0F1.8
0F1.9
0F1.B
0F1.C
0F1.D
0F1.E
0F1.F
0F20
0F21.
0F23
0F24
0F26
0F28

C482
31.
C40F
35
3D
C208
31.
C207
35
C1.00
01.
40
1.C
1.C
1.C
1.C
CA04
40
D40F
CA05
9093

LDI
XPAL
LDI
XPAH
XPPC
G2DATA: LD
XPAL
LD
XPAH
G2DAT1.: LD
XAE
LDE
SR
SR
SR
SR
ST
LDE
ANI
ST
JMP

L(G4HEX)-1.
1.
H(G4HEX)
1.
1.
LADDR(2)
1.
HADDR(2)
1.
(1.)

TABLE+4(2)
X'F
TABLE+5(2)
LINK

;GET 4 HEX DIGIT ADDRESS
;PTR 1. = ADDR TO BE READ
; GET DATA
; SAVE DATA IN E REG
;GET PACKED DATA

; MSD IN LO 4
;MSD DATA INTO TABLE
; GET DATA
; BLAN~ UPPER 4
; LSD DATA INTO TABLE

297

298
299
300
301.
302
303
304
305
306
307
308
309
31.0
31.1.
31.2
31.3
31.4
31.5
31.6
31.7
31.8
31.9
320
321.
322
323
324
325
326
327
328
329

; NEXT SECTION OF CODE IS THE KEYBOARD SCAN AND JUMP TO
; THE MULTIPLEXED DISPLAY ROUTINE
0F2A
0F2C
0F2D
0F2F
0F31.
0F32
0F34
0F35
0F37
0F39
0F3A
0F3C
0F3E
0F40
0F42
0F43
0F45
0F47
0F48
0F4A
0F4C
0F4D
0F4F
0F50
0F52

C455
31.
CA0A
C40F
35
CA0B
06
D41.0
9C03
3D
90F8
C2FF
D41.F
CA0F
06
D41.0
9803
3D
90F8
C20A
31.
C20B
35
C20F
01.

SCAN:

LDI
XPAL
ST
LDI
XPAH
ST
LOOK:
CSA
ANI
JNZ
XPPC
JMP
INPUT: LD
ANI
ST
RELEAS: CSA
ANI
JZ
XPPC
JMP
RETURN: LD
XPAL
LD
XPAH
LD
XAE

L
*
+
,

-

.

!

30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F

a
1
2
3
4
5
6
7
8
9
;

<
=

>
?

if it is valid, the software converts the 7-bit ASCII input
code to a 6-bit ASCII output code. After this conversion is
made, the clear bit and display-blanking bit are set to the
proper condition and are ORed with the character. The
character word now is written into the DM74199 latch.
Subsequently, the Data Present line is pulsed and the Write
Flag is tested to see if the display is ready to accept new
data. Figures 2C2-16 and 2C2-1'I, respectively, show the
flowchart and the program listing for the Control and
Message-Moving Program that is used to print a message
that is greater than 32 words long.

+5V

DBa
DB1

-7V~

DB2
DB3

5

DB4

~
M

DB5
DB&
DB7

P

NOTES,
1. 2-lnput NAND GatelDM74l001

or equivalent.
2. Unused pins not shown.

• ..

1331 AD OB

DB 03 L!!I

..

.. •

AD 09

~

...
...

00 AD10
!iii AD 11

...
HBCIIEFGHI
.. ".'.
"'~····i

.:... . . . . . I....I
189~ la.·
!

DBa
DB 1
DB2
DB 3

=1---r--

DB2

~.

DB 1

T1!!J

~

15 014
14 003

D01~

012 11

DB4

DB 5

A1~ AD 01 TAD01--t..!.1A1

D13~DB&

DB.
DB5

I

'1

u

a,

( '.) =. ?yO'"
..··n

DBO~D01

A3~ AD 03 --rAD03~A3

D14~ DB7

1221-- DB 7

,.

Figure 2C2-1S. SC/MP Interfaced with Burroughs Self·Scan Display

'!.II

rn,

u

T- ...

H .... • ......

.

Z

U 'v UJ i\ :i:J
~!E- $"+_1 #

123456
NS70557

•

- '1' .".....-.. . . .,. . . .
ii..:··-·
qJ

DB&
+5V ..............

Jf-l'a-frfT
npn'R
.. t .._-ht.. h.!1
q+.~ .•.
' •• "

002

1

(;: <::::> []

~

~

r---I

SEND
WRITE PULSE

NS10658

Figure 2C2-16. Flowchart for Control and Moving-Message Program

.',:::.-.
32 CHAF.:ACTEF.5.

4
~

'-'
7

RAM LOCATIONS USED.

l':Ii-OO

-OF01.
UI"'I::j:?

HFU:.:::
1,:iF04

•.. ).-:,

:?7
?:~:

ADl+:L::::S OF l'lESSAGE HIGH
ADDRLSS OF MESSAGE LOW
NE~r ADDRESS OF MESSAGE HIGH
HEXl ADDRESS OF MESSAGE LOW
CHAR PER LINE COUNTER

~J

.'

:i.

.i

I-i i 1'11,,'

2

.i

j:

.i

!::.I 1::.Ij.·.1 '-i.

1-1 1"11'' '
1._. I,,) I..! I'" I

"I·

.i

i:::I'.:":.ii:.:I

1··IC·j·,..

O;:;~KI

.i

l·}i

U ':~~

'<;':'II'!

~)FOO

.i

::;:At'lE AS ~:::1F0~3
SAt'lE AS (1F0:1
SAt'lE AS (1F~32
::::A t'lE AS ~3F~~G
SAt'lE AS (1F~34
AN:oF.:ESS OF DISPLA'T'.
::::TfiF.:T OF F.:At1.

, :'

'j.),:!

1~1

.i

S rAF.:"I· I NG ADDF.:ESS.

1,)UiJ~~1

""1:::,,'1

(,.10..1.,:,1:1.

L...:::,

U~~IU,:.:~

(1~:.Ii:J.':.:

r

MESSAG[ IS A~CII SIRING IN MEMORY.
Lt-.I[,' 1.)['" j'lt:: .:::.'c. 1':'1 ("F:: I :::: A E::'T'TE OF ALL (1.

; ADDRESS OF MESSAGE.

PfKiE
4';:1

4:t
"1-2 O(:)I,:.IU U:::::
4._. 1;:)(,)Ui C40F
4,'1- 0(10:::: .... ,
4,,; (01),,:1.

C:'~·i,:JU

~1·1::::

]:.;

l~' I;~I 1(1 (.

HOP
1....[:0 I

:''';F'AH
L[}l

HO::PAt'l)

.i

::

PUT F.:At·l ADDRESS IN P3.-

:'':F··Hj·-j

1.

()CIO:)

4 9 (~ "II) E::
c-':O 0,,,,0::1[:,
!"i.l OOUF
~:;:?

I:::I'~~J

I...

!::::()J..

i...

r!J::::;

J.

C';,': OO':! ..,'

C40~J

1...01

1.... 0::

~34

I'jC·1..4 ... "J..

>':P~~II....

:1.

5~5

OI?I:t~:;

L..[:OI

(j

C40(J

I:::;DF:)
.i

CLEAF.: D I SPLA'T'.

Figure 2C2-17. Program Listing for Control and Moving-Message Program

2C2-40

~tS Oell? C::::"UU
5 '? f:.1 U J. ~::~! C 1.+ ;::~ '-.::1
5:::: OO::i. !::: Ci:::(::14

:::;T
:::::T

C:OI...It·,11 (::::::0

6U U(':!.J..L: C=:·!:::t:t.

U)

':::::1

::::T
>::1"1"11....

L:::::T 0:: 3:)
L H'·IF" (: 3: : 0

!:~i()1.J:·

C1::: 0:,::

f: ;::: Ij ,;,:1 ::-::1. .,:: ,: :
6 '? ~~:! (:1 ;? ;~:: C: :::~: I;:) 1;:)

C'1- !:<,"":::::,·I

(1)

; 5ET LINE COUNT,

1...1) I

.; SET P2 TO ADDF.:ESS.
H::::T 0:: ::!:::HTI·'·IF (J:::O

I....[)

::;::1

,._:[:0,;:;:

;PUT ADDRESS IN TEMP.

r'h:tH.
.; HIGH ADDF.:E55 IN P2 .

~::ao

OI:);~::L::

·::'1 00::\>
7';;? r:::!cl;~:::F
?:? r::'I··I·.:·~:=:

(~i(2

Jt·,i~::

:-

L.C'

:::::ELF
HIt'iF' (3:::0

(,

;··::F'!:::II···j

.::.:.

"'I:~!:~;:

1....[:,
>':PH!....
.Jr'IF"

I.::::::;'() ..:,

c:

1....1)

:.:.•::::

.; GET NE>::r ~~OF.:[).
; CHECK I F DONE.
.; F.:ESTOF.:E PO INTER

UN:
.. ::.,:::
1..... :,:la~;::

>:F"HL..
L[:O

HTt'·iP(:i:)

~.:;li:·.lL.E

.Tt'iF'

F'F.:N·r

1.[:0

::::::? ':'lj:'C:I::: '.::,·jTF

::::c·

1;1 'J"? E·

:::: F ::::: (:1

f: ~:"

(t C! ,':1. :~::

~::!

::::'? 00 :1-.:..1::::: ::.:: 1::'1;::) ·'l (;
:~:9 0()4::::
:)0 I:::! 0 '.1-:::,'
91. 1:::1'::'1,1.[:

: : : [) ::::1

; SA',lE LHlE COUNT.

I

:::;:T

C()I.Jt·JT 0:: ~i: ::-

I
i)L..',"

OFF

L.l)
.J:;:"

(2)

L..[)

; DO t1 SHOF.:T DELA'T'.

~'.1:=:O

.; CHECK I F DONE,
.; BUt'lP F.:At'l PO I

ILl>

r::I::::I:).i:

>:;F:'AL..
ILl)
..It'lF'

i"IC:O~:

::::q:.Ii:>f:1

HTI"'·IF' 0:: 3:::0

I.:.I.··L

r" r:··1- r~: ~~1

q '::"

i~~ C!;::~

? -::.; .., f"

HI)

.; NE::n ADDF.:ESS .
.; BUt'lP HI CiH.

F'r.::IrH

:-::AE
U:'L
!.~·~:::1 ~::

tHEF~ .

.He

:) C: C E:
.. :,:;c::

.::, ,:::'

; SAVE IN P2 Lm~,
.; F.:ESTOF.:E HIGH.

I:

i.lr.u·
er:::I r·n

.; SA',lE CHAR
.; GET CHAR
.; CLEAI<: L I r·w:.
;CHECK IF LESS THAN 020.
.; NO :> ~7.11.F.
; LESS THAN 0iF F.:ETUF.:N.

U i J .. f-

eel...
nn'::? F4O::.. U
:1.1,;.1:::: (:"::',,,:,c,' :·:!'-+I~.C
.~ j'::':::' ~~~r~~~5E: A 0
J I::·I"!

f""1,::I.

r1 ("1 ~.; .-:::

r> 1.+ ..;: F.

11:'<:;
:1.06

C~C<~;[

[;;C:::.:;:)

:1

r~nl:::("t

:1..0,' CjIJf::::
:1.0:=:: .;:)1,,'6:2:

fif' .i

~:lC~)

..I!-.

PPlnr

LI:>f::
I·:·!r·~ I
()f,: I

O::.F

::::T
C::::::H

(J.. ::-

0,,::
[:'C:~:ll.

(IF:
1...

C:3~~1~)

:1!:::1'~1

~306~:'

11t::1

~~11:1C':::

07
[.:-,-:I-E

1.1:1

C10~:::::::

(I,'

CL.EAF.: L. INK.
CHECK IF :> ~)5F.
'T;ES f':ETUF.:tl
CHAk I:::; ","ALID.
.; ::::TFdF' OFF HIGH BITS,
.; SET CL.EAF.: RND DISPLR'T' BITS,
: SEN[) ~'KlF.:D.
.: SE T ~'~F.: I TE C'T'CLE FLAG 0,
.: NOI'~ SET FLt1Ci ~:::1.
.: NOl,~ F.:E:::;ET FLAG.
.: DO IT.

I

1'-1::::

i-1t·j

.;
.;
.;
;

I

I..:H':::
Figure 2C2-17 (Continued)

2C2-41

·1.E:

C::::A
ANI

:U. 3:
:1.:1.4

~:K169

(16

OC-~6A

[)4;;::~)

:1..:1. ~~

!~11~~6C

:::reF!:::

. m::

:1'1£

~:J(:16E

E:E,04

['ILD

~::121~1

[:OOW'IIT

cuur·n'.::.::;:>

J:::::

l:t·? ~:;n70 :::::::::CI:,
:1..:1..:=: :;::u:::q;::: ;c,,;:;[:,:,:
1:1.::'

.; GET STATUS.
,; CHEC¥: I F SENSE B I S SET.
.: ~~AIT IF SET.
.: E:UI'1F' COUNTER

NHI
PI'<: I Nl

.J r'IF'

t';:::I.:·
,1 :~':,
E,t,~[:o

:1 ::??

•
DOl,IA I T

rH~1~i6

COUNT
HST

(;'1(1(14

GTt!='

r:.:.l~::1~:::1~j

HH1P

L:;T
MCIF.'E
PF.'INT

1:::1I)(1J,

LTi'jF'

1';'1(103:

(1(140

t'jfJ,J

(i~,;,13::~:

Ff.::NT'
::::ELF

~:i~:E:6

j'll1SC:i
ON
F.: Ar'l

(K14 [:0

STAF~T

A["~?

s

0069
0002
13F213

0(G:?
0F(1(1

013(10 ""

NO EF.:F.'OF.' L r: t4E5

SOURCE

rHECK~UM=3~~5

NS70559

Figure 2C2-17 (Concluded)

2C2-42

MULTIPROCESSOR SYSTEM
General Description
Figure 2C3-1 shows how two microprocessors -SC/MP #1
and SC/MP #2 - can be interconnected to perform different tasks on a time- and memory-share basis. SC/MP #1 is
the basic SC/MP kit (l SP-8K/200) with a TTY input/output
interface, whereas SC/MP #2 is used to drive a Burroughs
self-scan display - see figure 2C~-1~. The control program
for each microprocessor is stored in a separate ROM; the
256 bytes of RAM are shared. The basic functions of SC/MP
#1 are defined in the SC/MP Kit Users Manual; however,
with more RAM and with the latching and buffering techniques shown in figure 1-8, the kit capabilities can be
expanded to provide a complete keyboard/display system.
System Operation
When power is applied to the multiprocessor system, NRST
of SC/MP #2 is driven high via the RC network and the
processor initializes at address X'OOO 1; for the time being,
SC/MP #1 is held off by the low input from flag I of
SC/MP #2. Each processor uses the Sense A input for
program direction; that is, if Sense A is low for SC/MP #2,
it branches to the Burroughs self-scan routine. After this

2C3-1

decision is implemented by setting P3 to the proper address, the SC/MP #2 software sets flag I high (NRST #1
now is driven high); this causes SC/MP #1 to initialize at
address X'OOOI. Since the Sense A input of SC/MP #1 is
tied high, it branches to the KITBUG Routine.
With both processors initialized and directed to their
respective programs, bus requests are made and ENIN is
tested for bus access. If EN IN is low, the processor requesting access must wait until its ENIN lines goes high. If the
ENIN line is high and no bus request is issued, the "bus
available" signal is passed to the next processor - in this
case, SC/MP #2 - via the ENOUT line. (Refer to figure 1-4f
for functional detail of bus-access control.)
Software Considerations
Figure 2C3-2 shows the system flowchart and the program
listing for KITBUG; a detailed flowchart for KITBUG is
shown in the SC/MP Kit Users Manual. The program listing
for the self-scan routine is shown in figure 2C3-3; except
for address assignments, this listing is similar to that shown
in figure 2C2-17. The flowchart for the multiprocessor "selfscan" program is functionally equivalent to that shown in
figure 2C2-16. There are no timing constraints; the system
is self-clocking and self-synchronizing.

AD 10
AD"
AD 10

-'2V
OBO
DB'
DB'
DBl
DB.
DB'
DBG

'-1-

't-'

DB 7

IIIIIII

"V

O.CD-(REFER TO
FIGURE 2C2
FOR FUNCTIONAL
DETAIL AND
CHARACTER SETI

2

NOTES

1. HI. inwerter IDM 74L041
orequivllent.
2. 3·lnput NAND 1IIh1
IDM 74L 101 or equivillftt.

NS10560

Figure 2C3-1. Using SC/MP in a Multiprocessing System

1
2
3
4

5
6
7
8

· TITLE

KITBUG,

=

0001
0002
0003

P1
P2
P3

=

=

1
2
3

FFFF

EXOFF

=

-1

9

~

MULTI PROCESSOS 3 17 76

~

MULTIPROCESSOR FLOWCHART

; FIXED STACK ASSIGNMENTS

10
11

12
13
14
15
16
17
18
19
20
21

0FFF
0000
0FFE
FFFF
0FFD
FFFE
0FFB
FFFC
0FF9
FFFA
0FF7
FFF8

22

23
24
25
26
0FF6
27
28
29
30
31
0000
32 0000 08

=

SR

· -STACK

· =. -1.

=

EX

· -STACK

· =. -1.

AC
PT2
PT1

=
· =.-2
=
· =.-2

· -STACI<
· -STACK

=

· -STACK

=
=

· -STACK

· =.-2

PC
P2ADR

· -1

· =0
NOP
START:

33

34
35
36
37
38
39
40
41
42

· =0FFF
STACK:

0001
0002
0004
0006
0007
0009
000A

06
0410
9C22
33
C404
37
3F

CSA
ANI
JNZ
XPAL
LDI
XPAH
XPPC

· PAGE
· LOCAL

43

44
45
46
47
48
49
50 000B C0F2
51 000D 01

;
;
;
;
;

010
ENTER
P3
004
P3
P3

READ STATUS
CHECK FOR SENSE A.
SET IRESET DISPLAY/KITBUG.
ZERO P3 LOW.
SET ADDRESS OF ROM2.

; GO TO DI SPLAY.

~DEBUG

ENTRY AND

EXIT~

ON A SOFTWARE HALT, HARDWARE USES THE FOLLOWING WORDS
TO SAVE THE ENVIROMENT.
DEBUG EXIT - RESTORE ENVIROMENT AND GO.
EXIT:

LO
XAE

STACK+EX

RESTORE E REG

Figure 2C3-2. Flowchart for Multiprocessor System and Program Listing for KITBUG

2C3-3

52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
1.00
1.01.
1.02
1.03

000E
0010
0011
0013
001.4
001.6
0017
001.9
001.A
001C
001D
001F
0020
0022
0024
0025
0027

C0EA
35
C0E8
31
C0E6
36
C0E4
32
C0DC
37
C0DA
33
C7FF
C0DC
07
C0D7
3F

LD
XPAH
LD
XPAL
LD
XPAH
LD
XPAL
LD
XPAH
LD
XPAL
LD
LD
CAS
LD
XPPC

STACK+PT1
P1
STACK+PT1+1
P1
STACK+PT2
P2
STACK+PT2+1.
P2
STACK+PC
P3
STACK+PC+1
P3
@lEXOFF(P3)
STACK+SR

RESTORE P1

RESTORE P2

PUT DESIRED PC IN P3

ADD EXIT OFFSET TO PC
RESTORE SR

STACK+AC
P3

DEBUG ENTRY POINT
0028
002A
002B
002D
002E
0030
0031
0033
0034
0036
0037
0039
003A
003:C
003D
003F
0040

C8D4
06
C8D3:
01
C8CF
36
C8C9
32
C8C7
35
C8C1
31.
C8BF
37
C8B9
33
C8B7

ENTER:

STACK+AC

ST
CSA
ST
XAE
ST
XPAH
ST
XPAL
ST
XPAH
ST
XPAL
ST
XPAH
ST
XPAL
ST

STACK+SR
SAVE EXTENSION REGISTER
STACK+EX
P2
STACK+PT2
P2
STACK+PT2+1.
P1
STACK+PT1
P1
STACK+PT1+1.
P3
STACK+PC
P3
STACK+PC+1

. PAGE
. LOCAL

POINTER

STACK

'MAIN COMMAND LOOP'

THIS CODE INITIALIZES POINTER REGISTERS AND
PROMPTS FOR AND GETS THE NEXT COMMAND.
ON EXIT. E HOLDS THE COMMAND CHARACTER
0042
0044
0045
0047
0048
004A
004B

C4F6
32
C40F
36
C401.
37
C4C3

CMDLP:

LDI
XPAL
LDI
XPAH
LDI
XPAH
LDI

L(P2ADR)
P2
H(P2ADR)
P2
H(PUTC)
P3
L(PUTC)-1
Figure 2C3-2 (Continued)

PRINT CR-LF

1.04
1.05
1.06
1.07
1.08
1.09
1.1.0
1.1.1.
1.1.2
1.1.3
1.1.4
1.1.5
1.1.6
1.1.7
1.1.8
1.1.9
1.20
1.21.
1.22
1.23
1.24
1.25
1.26
1.27
1.28
1.29
1.38
1.31.
1.32
1.33
1.34
1.35
1.36
1.37
1.38
1.39
1.48
1.41.
1.42
1.43
1.44
1.45

1.46
1.47
1.48
1.49
1.50
1.51.
1.52

0040
004E
0050
0051.
0053
0054
0056
0057
0059
005A

33
C40D
3F
C40A
3F
C42D
3F
C484
33
3F

XPAL
LDI
XPPC
LDI
XPPC
LDI
XPPC
LDI
XPAL
XPPC

P3
'liD
P3
0A
P3

· PAGE
· LOCAL

"GO"

PRINT CR
PRINT LF

"-"

P3
L(GECO)-1.
P3
P3

; P3 HIGH OK.
GET COMMAND CHAR.

;

RESTORE MACHINE STATE AND TRANSFER CONTROL
TO SPECIFIED ADDRESS.
G ADDRESS
0058
085C
885E
0068
8861.
8063
0065

48
E447
9C87
3F
E48D
98A6
9064

GO:

LDE
XRI
JNZ
XPPC
XRI
J2
JMP

"G"
$SKIP
P3
'liD
EXIT
ERROR

;

CALL GECO

$SKIP:
· PAGE
· LOCAL
;

8867
8868
806A
086C
006D
886F
0071.
0073
8875
0877
0079
0078
0070
807F
0080
8882
0084
0086
0087
8089
008A

48
E454
9809
40
E440
9C5A
C480
9002
C401.
CEFF
C400
37C4
DE33
3F
E400
9C47
C601.
35
C601.
31.
C401.

"TYPE"

TYPE OR MODIFY MEMORY.

TYPE:
MOD:

$2:
$1.:

LDE
XRI
J2
LDE
XRI
JN2
LDI
JMP
LDI
ST
JS

XRI
.JN2

$4:

LD
XPAH
LD
XPAL
LDI

CHECK FOR TYPE COMMAND. IF
NOT "T", SKIP COMMAND.

"T"

$2

"M"
$SKIP

o

$1.
1.
@-1.(P2)
P3,GHEX

00
ERROR
@1.(P2)
P1.
@1.(P2)
P1.
H(PUTC)
Figure 2C3-2 (Continued)

2C3-5

SAVE FLAG FOR TYPE OR MODIFY
GET ADDRESS

CHECK TERMINATOR
PUT STARTING ADDRESS IN STAC

PRINT CR-LF

153 008C 37
154 0080 C4C3
155 008F 33
156 0090 C40D
157 0092 3F
158 0093 C40A
159 0095 3F
160 0096 35
161 0097 01
162 0098 40
163 0099 35
164
165 009A C442
166 009C 33
167 0090 40
168 009E 3F
169 009F 31
170 00A0 01
171 00A1 40
172 00A2 31
173 00A3 40
174 00A4 3F
175 00A5 C501
176 00A7 3F
177
178 00A8 C200
179 00AA 9CDE
180
181 00AC C484
182 00AE 33
18300AF,3F
184 0080 E40D
185 00B2 9806
186 0084 E415
187 0086 988A
188 0088 C400
008A 37C4
008C DA33
008E 3F
189 008F E40D
190 00C1 9C08
191 00C3 C601
192 00C5 C601
193 00C7 C9FF
194 00C9 908F
195
196
197
198
199
200
201
202 80CB C401

XPAH
LDI
XPAL
LDI
XPPC
LDI
XPPC
XPAH
XAE
LDE
XPAH

P3
L(PUTC)-1
P3
00
P3
0A
P3
P1

LDI
XPAL
LDE
XPPC
XPAL
XAE
LDE
XPAL
LOE
XPPC
LO
XPPC

L(PHEX2)-1
P3

PRINT CR
PRINT LF
PRINT HIGH BYTE
READ AND RESTORE BYTE FROM P

P1
; P3 HIGH OK.

LO

JNZ

CALL PHEX2
PRINT LOW BYTE

P3
P1
P1
P3
@1(P1)
P3

CALL PHEX1
PRINT 2-DIGIT HEX FOLLOWED B
8LANK (PHEX1)
CHECK TYPE OR MODIFY FLAG

(P2)
$4

iP3 HIGIH IS STILL OK.

LDI
XPAL
XPPC
XRI

JZ
XRI
LOOP1:

JZ
JS

XRI

JNZ
LD
LD
ST
JMP

L(GECO)-1
P3
P3
00
$4
015
CMDLP
P3.GHEX2

i

i

GO TO GECO.
0D XOR 018 (CAN)

0D
ERROR
@1(P2)
@1(P2)
-1(P1)
$4

$SKIP:
. PAGE
. LOCAL
i
i

~ERROR

PROCESSING~

PRINT CARRAIGE RETURN • LINE FEED AND LOOP
TO THE TOP OF THE COMMAND LOOP.

ERROR:

LDI

H(PUTC)
Figure 2C3-2 (Continued)

2C3-6

; PRINT LINE FEED

203
204
205
206
207
208
209
21.0
21.1.
21.2
21.3
21.4
21.5
21.6
21.7
21.8
21.9
220
221.
222
223
224
225
226
227
228
229
23121
231.
232
233
234
235
236
237
238
239
24121
241.
242
243
244
245
246
247
248
249
250
251.
252
253
254
255

00CO
00CE
0000
0001.
0003
0004
0006
01307
0009

P3
L(PUTC)-1.
P3
0A
P3

XPAH
LOI
XPAL
LOI
XPPC
LOI
XPPC
LOI
JMP

37
C4C3
33
C40A
3F
C43F
3F
C400
9008

P3

o

LOOP1.

. PAGE
. LOCAL

"HEX NUMBER INPUT"

GHEX GETS A 1.6-BIT VALUE AND PUSHES IT TO THE STACK
GHEX2 ASSUMES THE FIRST CHAR IS IN THE E REGISTER.
ONLY THE LAST 4 INPUT DIGITS ARE SAVED.
RETURNS VALUE I N TOP 2 WORDS OF STACK AND

TE~:M I NATOR

·1 N THE AC AND EX REG I STERS.

0008
0000
e0DF
e0E1.
00E3
e0E5
00E6
00E8
00EA
00EB
0eED
00EF
00F1.
00F2
00F4
0eF6
eeF8
0eF9
0eFA
00FC
00FE
00FF
01.01.
01.03
01.05
01.06
01.138
01.09
e1.0A
01.08
01.00
01.0E
01.1.0

C401.
901212
C4ee
CAFB
C484

GHEX2:
GHEX:
$6:

:n

CEFD
C401.
37
CEFF
C2FF
9C01.
3F
C400
CAe3
CAe2
413
03
FC3A
940F
133
FCF6
941.9
C601.
37
C601.
33
40
3F
913D2
1213
FC0D
94F1

LDI
.JMP
LDI
ST
LDI
XPAL
ST
LDI
XPAH
ST
LD
JNZ
~I

DLY
DLD
JZ
LDE
ANI
ST
XAE
SR
XAE
CSA
ORI
XOR
CAS
JMP
CSA
ANI
CAS
ANI
JZ
XPPC
JMP
JS

255
23
SET OUTPUT BIT TO LOGIC 0 FL
FOR START BIT. (NOTE INVER

1
9

-1(P2)
1.38

i

INITIALIZE BIT COUNT
AT 0FF5
DELAY 1. BIT TI ME

8

-1(P2)
$EXIT

DECREMENT BIT COUNT.
PREPARE NEXT BIT

1

-2(P2)

i

AT 0FF4
SHIF DATA RIGHT 1. BIT
SET UP OUTPUT BIT

1.

-2(P2)
PUT BIT TO TT'T'
$1.
SET STOP BIT
0FE
020
$2
P3
PUTC
P3,CMDLP

CHECK FOR KEYBOARD INPUT SEN
ATTEMPTED INPUT (NOTE THAT
INPUT IS NOT INVERTED)
RETURN

Figure 2C3-2 (Continued)

2C3-1.0

e1F6 37C4
e1F8 4133
e1FA 3F
414
13131313
AC
ERROR
EXOFF
GHEX2
MOD
P2AOR
PHEX1
PT2
STACK
$1
$1
$2
$3
$4
$5
$6
$LOOP
$SKIP

. END
FFFE
eeCB
FFFF
e0DB
e06C ...
eFF6
0130
FFFC
eFFF
131377
13101
13166
e11C
ee8A
121122
13178
0198
eeCB

CMOLP
EX
GECO
GO
Pi
P3
PHEX2
PUTC
START
$1
$2
$2
$3
$4
$5
$EXIT
$F::ET

NO ERF::OR LINES
SOURCE CHECKSUM=E86E
FIRST INPUT SECTOR HEX FINAL INPUT SECTOR HEX -

131342
FFFF
13185
e05B *
131301
1313133
13143
e1C4
131301 ...
00F2
1312175
121189
121168
121119
e15D
e1E9
01133

ENTER
EXIT
GHEX
LOOP1
P2
PC
PT1
SR
T'T'PE
$1
$2
$2
$3

$4
$6
:.f;LOOP
:.f;SKIP

131328
eeeB
eeDF
131386
130132
FFF8
FFFA
13131313
131367
13147
131130
e1F4
e1A6
13173
eeE1
13eF8
131367

*

132913
02A0
NS10561

Figure 2C3-2 (Concluded)

2C3-11

. TITLE

~

2

DISP, 'MOVING MESSAGE FOR MULTI '

MESSAGE MUST BE > 32 CHARACTERS.

3
4

5
6

7
8

RAM LOCATIONS USED.

9
~0
~~

0F00

~2
~3
~4

0F0~

0F02
0F03
0F04

~5
~6
~7
~8
~9

20

0000

2~

088~

22

8002
0003
0004
0800
0F00

23
24
25
26
27
28

HST
LST
HTMP
LTMP
COUNT
ADR
RAM

0400

ADDRESS OF MESSAGE HIGH
ADDRESS OF MESSAGE LOW
NEXT ADDRESS OF MESSAGE HIGH
NEXT ADDRESS OF MESSAGE LOW
CHAR PER LINE COUNTER

=
=
=

2
3
4
0800
0F09

; SAME AS 0F00
; SAME AS 8F8~
; SAME AS 0F02
; SAME AS 0F03
; SAME AS 0F04
; ADDRESS OF DISPLAY.
; START OF RAM.

=

0400

; STARTING ADDRESS.

=
=
=

=

0
~

29

30
MESSAGE IS ASCII STRING IN MEMORY.
END OF MESSAGE IS A BYTE OF ALL 0.

3~

32
33
34

. PAGE
35
36
37
38
39
40
41.
42
43
44
45
46
47
48
49
5121
51.
52
53
54
55
56
57
58

START:
0400 138
040~ C42e
13493 137
0404 C49F
9406 37
0407 C4ee
0409 33
04eA C4e4
040C CBe9
040E C477
041.0 CB01.
941.2 C408
12141.4 35
12141.5 C40e
041.7 31.
041.8 C400
e41.A Cgee
041.C C429
e41.E CBe4
0420 C301.
0422 CB03

Nap
LOI
CAS
LOI
XPAH
LDI
XPAL
LOI
ST
LDI
ST
LOI
XPAH
LDI
XPAL
LDI
ST
LDI
ST

S:
LD
ST

929
H(RAM)
3
URAM)
3
H(MMSG)
HST(3)
UMMSG)
LSTG)
H(ADR)
1.
UAOR)
1.
9
(1.)
32
COUNT(3)
LSTG)
LTMPG)

; SET F1., TURN ON SC/MP 1..
; SEND FLAG.
; PUT RAM ADDRESS IN P3.

;SET STARTING ADDRESS IF MESSA
; SAVE I N RAM.
; PUT ADDRESS OF DISPLAY IN P1..

; CLEAR DI SPLAY.
; SET LINE COUNT.
; PUT ADDRESS IN TEMP.

Figure 2C3-3. Program Listing for Burroughs Self-Scan Routine

2C3-12

59
60
61.
62
63
64
65
66
67
68
69
7e
71.
72
73
74
75
76
77
78
79
8e
81.
82
83
84
85
86
87
88
89
ge
91.
92
93
94
95
96
97
98
99
1.13e
1.1211
1132
1.e3
104
1e5
106
1e7
1.08
1.e9
1.1.13
1.1.1.
112
11.3
114
1.15
1.1.6
11.7

0424 32
0425 C3:00
0427 CB02

XPAL
LD
ST

2
HST(3:)
HTMP(3:)

.; SET P2 TO ADDRESS.

XPAH

2

.; HIGH ADDRESS IN P2.

LD
JNZ
LD
XPAH
LD
XPAL
JMP

@1.(2)
SELF
HTMP(3:)
2
LTMP(3)
2
MORE

.; GET NEXT loJORD.
; CHECK IF DONE.
; Fi:ESTORE POINTER.

XPAL
LD
.JMP

2
HTMP(3)
PRNT

; SAVE IN P2 LOW.
.; F~ESTORE HIGH .

LDI
ST
LDI
DLY

32

; SAVE LINE COUNT.

COUNT(3)
€IFF
e8e

.; DO A SHORT DELA',.'.

LO
JZ
ILO
JNZ
XPAL
ILO
JMP

(2)
S
LTMP(3)
ON
2
HTMP(3)
PRINT

PRNT:
0429 3:6
PRINT:
042A
e42C
042E
e43e
e431.
e433
e434

C6e1.
9C22
C3:e2
36
C3e3
32
geeD
ON:

e436 32
e437 C3e2
e439 geEE
NEW:
e43B
e43D
e43F
e441.

C42e
CBe4
C4FF
8F8e

e443
e445
e447
e449
e44B
e44C
e44E

C2ee
9809
ABe3
9CEB
32
ABe2
geOA

e45e
13451.
e452
e453
0455
0457

1211.
4e
1212
F4EIZI
941212
9001

l1459
l145A
e45C
045E
e45F
13461
0463
0465
e466
13468
0469
e468

-~
""~-

F4C0
94CC
4e
D43F
DC81Z1
C91Z1l1
136
Dce1
07
[>4FE
137

046C
1Z146D
1346F
0471
0473
e475

06
D420
9CF8
881214
98(:6
9083

MORE:

; CHECK IF DONE.
; BUMP RAM POINTER.
; NEXT ADDRESS.
BUMP HIGH.

i

SELF:
~'::AE

LDE
CCL
A[n
.JP
.Jto1P

IZIEIZI
GT1.F
PF.:INT

.; SAVE CHAR.
.; GET CHAR.
.; CLEAR LINK .
; CHECK IF LESS THAN 1Z12l1.
; NO > IZI1.F.
; LESS THAN IZI1F RETUF.:N.

GT1.F:
CCL
ADI
.JP
LDE
ANI
ORI
ST
CSA
ORI
CAS
ANI
CAS

~1CIZI

PRINT
1Z13F
~)81Z1

(1.)

; SET loJF.: ITE C'r'CLE FLAG 0.
; NCiloJ SET FLAG 121.
; NCiloJ RESET FLAG.
.; DO IT.

1
0FE

DOl-JAIT:
CSA
ANI
.JNZ
DLD
.JZ
.Jto1P

.; CLEAR LINK.
.; CHEcr: IF )- 1Z15F.
.; 'T'ES RETURN.
; CHAR IS VALID.
.; STF.:IP OFF HIGH BITS.
.; SET CLEAR AND DISPLAY 8ITS.
.; SEND "KlFi:D.

020
DOWAIT
COUNT(3)
NEloJ
PF.:INT

Mt1SG:
Figure 2C3-3 (Continued)

2C3-13

.; GET STATUS.
.; CHECK IF SENSE 8 IS SET.
; "JAIT IF SET.
.; 8UMP COUt-HEFi:.

118 9477
9479
0478
947D
947F
0481
9483
0485
9487
9489
0488
9480
048F
0491
13493
0495
0497
0499
0498
13490
119 049E
04A0
04A2
04A4
04A6
04A8
04AA
e4AC
04AE
13480
9482
9484
9486
9488
948A
e48C
94BE
94C0
04C2
94C4
129 04C6
94C8
94CA
94CC
04CE
0400
94D2
121404
94D6
121408
12t4DA
04DC
04DE
04E9
12t4E2
e4E4
12t4E6
12t4E8
94EA

2929
2929
2020
2020
2020
4055
4C54
4920
5052
4F43
4553
534F
5220
4F50
4552
4154
494F
4E20
4F46
20
5457
4F20
5343
2F40
5053
2C20
4F4E
4520
5255
4E4E
494E
4720
4849
5442
5547
2054
4845
204F
5448
4552
2052
554E
4E49
4E47
2941
2942
5552
524F
5547
4853
212153
454C
4629
5343
414E
212144
4953
512t4C
4159

NULTI PROCESSOR OPERATION OF

· ASCII

~

· ASCII

. . TWO SCrMPS, ONE RUNNING KIT8UG THE OTHER . .

· ASCI I

....

RUNNING A BURROUGHS SELF SCAN DISPLAY .

Figure 2C3-3 (Continued)

2C3-14

e4EC
e4EE
e4Fe
1.21. e4F1.
1.22
1.23
1.24

DISP

ADR
GT1.F
LST
MORE
PRINT
S

2E2e
21212121
2121
1210

BYTE

1211211210

END

121

MOVING MESSAGE FOR MULTI

0a00
121459
9991.
9443
942A
9429

COUNT
HST
LTMP
NEW
PRNT
SELF

1211304
130130
13121133
e43B
13429
0450

DOWAIT
HTMP
MMSG
ON
RAM
START

046C
13121132
121477
13436
eFee
134130 ,..

NO ERROR LINES
SOURCE CHECKSUM=D1.36
NS70562

Figure 2C3·3 (Concluded)

2C3-15

INTERFACING A SC/MP SYSTEM
WITH A CASSETTE RECORDER

corder was used to record and playback and, in all cases,
the results were error-free. The transmission rate of 330 baud
(40 bytes/second) is sufficient for most applications; the
clocking scheme permits the storage of 17 2K-byte programs
(including interprogram gaps) to be recorded on each 15minute side of the cassette tape.

General Description
Figure 2C4-1 shows how a casette tape recorder can be interfaced with a SC/MP-based system to provide approximately
40K 8-bit bytes of data on each side of a 30-minute tape.
As an alternative to using paper tape, PROMs, or more complex and expensive media, the cassette interface can be used
to store and transport program libraries; also, systems of
similar design could be used for small-business inventories
and many other applications.

Table 2C4-1. Cassette Recorders Used for Accuracy and
Reliability Tests

Off-the-shelf integrated circuits were used to implement the
system shown in figure 2C4-1. A recorder in the cost range
of 50 dollars will provide satisfactory performance; however,
a higher priced ($80 to $100) recorder should provide better
consistency and greater reliability. The recorders listed in
table 2C4-1 were used to verify the accuracy and reliability
of this application. Using the four recorders, a 10K-byte
program was loaded 10 times in succession and then two
playbacks were made from each recorder. A different re-

Make

Model

Panasonic
Panasonic
Sony
Sony

R0309AS
R0423S
TC-40
TC-55

Approximate Cost
$ 40
$ 70
$100
$155

*Specifying the ideal recorder for a particular application is difficult: it is reccommended that the output waveform
(WF-A, figure 2C4-3) be used as a
guide to selection.

DIGITAL INPUT
-END OF TRANSMISSION
('ISSllTE

HfC{)RDfH

M[1\10HY PE:RIPHERAL

DeCODE R
AOORESS
NRDS

t---ot

-+..--t...

SENSE B

NWDS .....
NOTE

SC/MP SYSTEM INCLUDES

HEX KEYBOARD AND/OR
TTY. INTERFACE CIRCUITS. DISPLAY. AND MINIMUM DEBUG ROUTINES

OATA

18200-82FFI

~_I_~

I

•::t.

•

GENERATED BY

16-BITS EACH-USER ENTERS

Ij

L~{: : ;J: ~:': : ~:@(@,: : : ~ <~'r~.w.-<~: :~: :~ : : : :~: :': : :': : : : : :m: : :~ s~;,: :~: : : ~: : :~ ~.: :~: :~:,~ :s: : : :~: ~: : :~: : : : :<: m: ; :t.,~ v,: (@:"*'"': :";,:;", ~.J
Figure 2C4-1. Cassette Recorder Interfaced with SC/MP System- Block Diagram
and Message Format

2C4-1

NS10563

Operator Control
An input/output program residing in PROM provides all
timing and control functions required to send and receive
information between the CPU and the recorder. The send
operation can be summarized as follows. Using a keyboard
or a tape reader, the operator loads RAM locations X'S203
(high-order byte) and X'S204 (low-order byte) with a 4digit hexadecimal address that corresponds to the starting
address of the program -see MESSAGE FORMAT in figure
2C4-1. Next, RAM locations X'S20C (high-order byte) and
X'S20D (low-order byte) are loaded with the POINT OF
ENTRY ADDRESS. This entry point may be the starting
address of any program to which the operator wants to
transfer control upon completion of loading (playback
mode)_ Finally, the high and low order bytes for LENGTH
OF PROGRAM are loaded into RAM locations X'820A and
X'S20B, respectively. To initiate the output cycle, the operator turns on the recorder and transfers control to address
X'SOC7 - the beginning of the data write routines. After
the TAPE LEADER (12S bytes of zeros) is run through,
the Search (LED) Indicator lights and stays on until the
data transmission is complete; at this time, the Search Indicator is turned off, the End-of-Transmission Indicator is
turned on, and the program halts at location X'SI42.
NOTE: If the recorder is inadvertently stopped before the
output cycle is completed, the tape must be rewound and
the cycle restarted.

In the receive (playback) mode, the operator transfers control via the keyboard to X'SOOO - the starting address of
the bootstrap loader routine. The bootstrap loader conditions SC/MP and then addresses the receive routine. Now,
when the cassette is turned on and the operator selects the
playback mode, the Search Indicator is turned on until the
IDENTIFICATION WORD (figure 2C4-I) is recognized;
then, the indicator is turned off. NOTE: For normal operation, the Search Indicator should be "on" from 3 to 5
seconds; if it is on for a Longer period because of defective
tape, dirty heads, or another maLfunction, the operator
should abort the operation and restart it at X'8000. If the
checksum is good, the Search Indicator is turned on again
when the transmission-of-data is completed.
When in the playback mode, the volume control of recorder
should be adjusted until the "monitor output" is just below
the clipping level when measured with an oscilloscope. Using
the Search Indicator on-off time of approximately S seconds
as a limit switch, the adjustment can be optimized by a
trial-and-error method.
System Operation
Transmission of data from SC/MP to the cassette recorder
is accomplished by using a scheme that is self-synchronizing

2C4-2

on a bit-time basis; that is, data are referenced to a "timeframe" rather than a leading or trailing pulse edge; thus,
there is no cumulative error buildup in the system. The
"approximate" 4-millisecond time frame (duration between
clock pulses) is established by the send routine. A logic '0'
is represented by the absence of a pulse at the midpoint of
the time frame; a logic '1' is represented by the presence of
a pulse. The clock and bit (data) pulses are generated by the
address decoder circuits shown in figure 2C4-2. To generate
either a clock or a bit (logic '1 ') pulse, a unique address is
presented to the system address bus during the execution of
a STore Instruction by SC/MP. The clock or bit pulse is
then transmitted to the cassette recorder via the interface
circuits shown in figure 2C4-3. A negative-going pulse is
produced to begin the time frame. If the data bit is a '1',
the decoder is addressed at the midpoint (between clock
pulses) of the time frame and a second negative-going pulse
is generated. If the data bit is a '0', the decoder is not addressed and no pulse appears between the clock pulses of
the time-frame.
To record, the data write routines generate a long leader of
zeros plus the identification word (X' AS) shown in figure
2C4-I; these data are presented to the interface circuits in
figure 2C4-3. The leader allows the tape-drive motor and
AGC loop to stabilize; the leader also serves as an interprogram gap that facilitates multiple-program recording on a
single side of the cassette tape. As shown by the idealized
waveforms in figure 2C4-3, TTL inputs from the address
decoder are changed to signals that are suitable for recording on the tape. User data are transmitted following the
identification word.
In the playback mode of operation, the recorder output
(WF-A, figure 2C4-3) is translated to a TTL signal (WF-B)
that drives the Sense B input (WF-C) of SC/MP. The processor tests the Sense B line (output of "send" latch) for a
logic '0', which occurs at the first clock pulse of the time
frame. The latch is reset by SC/MP and, after a predetermined delay (approximately one-half time frame), Sense B
is again tested. If a negative-going pulse is found at the "center" of the time frame, the data bit is recognized as a logic
'1' and the latch is reset. If there is no zero-transition between the first and last pulses of the time frame, the bit is
recognized as a logic '0'. As previously indicated, this technique - referencing the data bit to a time interval rather
than to the leading or trailing edge of a pulse - prevents
cumulative error buildup in the system. Tape format is such
that upon completion ofloading a program from the cassette,
the program may be executl!d or control can be transferred
to another existing program; for instance, a debug program.
As previously indicated, the user can transfer program control by simply loading the POINT OF ENTRY ADDRESS
(figure 2C4-I) with the proper starting location.

NOTE
SC/MP SYSTEM IN·

AD12

CLUDES HEX KEYBOARD AND/OR TTY.

A013

INTERFACE CIRCUITS,
DISPLAY. AND MIN·

AD14

IMUM DEBUG
ROUTINES,

A015

NWDSI

AOOO-AD 11

PORT

£

POR;I.

I,

DBD-DB7

••

NRDS~I------------

DBO
DB'

DO,

D'.

082

DB.

D'3

r-'~m"'1

LvLf"Hls l"oc"
I

D03

DB2
DB3

DB.

DO.
DB3

DBS
A4

......

--..l

A4

D02

2ms

I--

I
I

"1"~

DATA (0 or 11
TO INVERTER
IFIG.2C5·3)

I-- DATA
TIME

DB6
NOTES:

DBS

DB'

+SV

1. Unused pins not shown

A'

2.2·jnpul: OR II"- IDM 1432)

DB6
DB7

D'2

DB7

DO,
DBO

D,.

+5V~22IV,.,.

AD05

ADOS

A& 111-- AD 06

AD 06

AD07

AD 01

or equivalent
3. EDT'" end of transmission

NS10564

Figure 2C4-2. Decoding and Memory-Interface Circuits

DIGITAL I NPUT FROM

~~~~~~:, ~d~,~C~;lM

----------------------------------------------------------------------------------------------------________________________________________,

BELOW

CASSETTE
RECOROER

MON
OUTPUT

II.)

(')
~

~

MIC
INPUT

I ..

,

CLOCK

so
--r

PULSE

--=LJ- It _J

TYPICAL INPUT
DECODER

'0-

111M

L OGIC 0

Lp·ULSE "" LOG IC

CLOCK~------------

U

LEGEND :
FOR A 1MHz CRYSTAL .
Tl
2,., SEC
T2 / T3 / T4 / T 5

- O.4 V

150/-J SEC

NOTES
1 He/( Inverter (OM 7404 ) or equivalent
2 . Unused pillS not shown

O.2V

ov

NS10565

Figure 2C4-3. Cassette-to-SC/MP

Interfa~e

Circuits

Software Considerations
The "data write" and "data receive" routines are stored in
ROM. A "minimum control" routine is also stored in ROM;
this routine directs communications between the operator
and a "hex" keyboard, and controls the LED indicators
shown in figure 2C4-2. Send and receive flowcharts and a
complete program listing for the cassette-to-SC/MP interface
are shown in figures 2C44 and 2C4-5, respectively.

To transfer control to RAM or to modify locations in RAM,
an input/output interface capability is required by the operator. Such a capability is provided by the SC/MP Low Cost
Development System or by the SC/MP minimum debug kit
with a "hex" keyboard/display and the necessary interface
circuits. NOTE: Refer to figures 2C2-8 and 2C2-14 for
guidelines to design a keyboard-entry/display interface.}

li:IDm:~~~r@~~~~~j~::> DATA WRITE~~:~~::M::j~

i:~

it
.~~
§;I':~

*~

~

~

il':ll

[:ill

m
~

~]

~1i:

lli~
~'*:

ji

·w-:
'.

m

W
~

I
NS10566

Figure 2C4-4. SC/MP-to-Cassette Interface-Write and Read Flowcharts

2C4-5

TITLE
4

...

....1

is
7

::::;;~~)(1

F.: FIt'l

;:::::(11;)

F'EF.:IPH

=
=

000:::

TAPEIO.

~,::"'82k10
~.::

P:::~:

.-

J:

:3

~::t('I02

F'2

:H~

000:1.

F':t

=
=

2

:11.
:1.2

:1.4

OO~jl;:1

15

(HJ~:H

:1.6
:t.?
:1:::::

0002
~KI((.:::

~;;TtiF":TL

E:ITCNT
TEt'lP1.
TEt'lP2
TEt'lPJ:
TEt'lP4

(1~:~I;J?

.::!..\!::.

(1121121::::
Ok1('19

(10 (:t I=i

~'J[)CNTU

f1(1~?1E:

~'JDCNTL.

(1(1~~IC

.JUt'lF'U
JUNPL.

~100D

'-:11::'
~....'

.:
1;'1~)00

32

cr-fT!...
C1< :;:; U1"1
:;:;'THR1U

0005
;2:1.

;27

CNTU

0004
(~I;)~)f':;

24

3: ~1"3

SC~MP

;

RAM
PE~:

ROUTINES/

ADDF~ESS FOR POINTER
I PHE~:AL ADDRESS FO~: POINT

POINTER #3
POINTER #2
POINTE~: #1.

1.

; TEMPORARY DATA IN RAM

13

.-,,'.',

,,0 :::

/

~J(1(11.

t::.1f1~:::12
~:::10f1J:

00[14

=

0

.-

~t

=
=
=
=
=
=
=
=
=

2

PEF.: I PHEF.:AL

EOTON
EOTOFF
SF.:CHON
::;;RCHOF
FLAG

=
=
=
=
=

INSIDE COUNTER FOR LEADER
OUTSIDE COUNTER FOR LEADER
CHECK SUM COUNTER
STARTING ADDRESS (UPPER)
STARTING ADDRESS (LOWER)
BIT COUNTER
TEMPORARY STORAGE LOCATIONS
"
"
"
"
"
"
"
"
"
WORD COUNT (UPPER)
WORD COUNT (LOWER)
TRANSFER ADDRESS (UPPER)
TRANSFER ADDRESS (LOWER)

3:

4
5

E.
'(it

:::
9

1.0
1.1.
1.2

1.2
OF.:DE~:

CODES
END OF TAPE LED ON POINTER
END OF TAPE LED OFF POINTER
SEARCH LED ON POINTER
SEARCH LED OFF POINTER
READ . .··WR I TE FLAG

~J

1.

.-,

,::.

3:
4

Figure 2C4-5. SC/MP-to-Cassette Interface-Program Listing

2C4-6

. PAGE /BOOTSTRAP LOADER'
3:8

3:9
BOOTSTRAP LOADER ROUTINE.
RECEIVES PROGRAM FROM TAPE.
ALL NECCESSARY INFORMATION FOR LOADING IS ON TAPE.

4~)

41.
42
43:

THIS PROGRAM MAY BE REASSEMBLED TO ADDRESS X'0000 TO
FUNCTION AS A POWER-ON LOADER.

44

45

'ff.i

47
48
49

SEARCH LED ON WHEN PROGRAM STARTS
~EARCH LED OFF WHEN IDENTIFIER CHARACTER RECEIVED
EN[:O OF TAPE (EOT) LED ON WHEN RECEPTION COMPLETE
SEAF.:CH LED ON IF CHECKsur'lS COMPAF.:E

5~)

51.
,_la::,

C"'-'

CONTROL IS THEN TRANSFERED TO USER PROGRAM

5:3:

54
55
56 ::::(l(H)
57 ::3(1(1:1

~X::

[:OOT :

C4(1~J

c::;.=< 8~~104 C4::::2
6(1 8(H)6 3:6
61. ::::(1(1'( C4(n)
62 8~X19 CA~)2

6::

::::~:H)E:

C4(1(1

64 ::::(1(1[:' '7-' C"
65 8~X1E CA:::::3:
66 80:1(1 :::?
67 ::::~):11. (:E:(12
::::[1j_"('

0:1.

7~t

::::(11.::::: C4::=:F

72

::::(HH

::::t

7:3: ::::(l:1E: (:4:;::(1

74
75

::::~;:1[:'

'(':3

8~)2;2

35

::::O:1.E .]:[:0
?6 ::::(l1,F 4~:1
7"7 8(12t1 E4A::;
9:::~j2

'('9

::::(124

90FS

80

:::::(1;;-~6

CE:~).3:

::::(12:::: C46D
82 S(12A :::::1
::::3: ::::~)2E: (:4::::(1
::::4 80:<:[:0 :'5
::::5 8~:12E 3:D

:31.

P;;-,

LDI
ST
L.DI

(1

LOC I [:. :

CKsur'l (P2::O
LO::PEPIPH)

:"::PAL

F'J:

LDI

H0:: PEl': I PH)

:"':F-'f1f-l

Pl:

ST
LOI

69 :::::(11.':; C4(n;:1

LO::F.:AM)
P2
H0:: F.:A~l)

::':;PAH

:::;r

6:::: ::::(lj3 C:E:(l:1
7~::"1

r·KlP
LDI
j·::PAL
L[)I

SF.:CHor~ 0:: P3:)
EOTOFF 0:: P3:)

(1

LO::GETE:IT)--1.
P:1

L01
i::F.: I

P1

GO TO GETBIT FOR INPUT

.JZ
JI"1P

::;;ETPNT
LOCID
SPCHOF0:: PJ:)
L 0:: PEe'·. . )-1

CHECK FOR PROPER ID CHARACTE
IF 10 RECEIVED. TAKE REST OF
PFi:OGF~AM.
ELSE GET NEXT BIT
TURN OFF SEARCH LED
PLACE ADDRESS OF BYTE RECEIV
IN F·1.

SETPNT: ST
U) I

F':1

P:1

LDI

H(~:EC'·"')

i::PAH
::':;PPC

P1.
P:1
P3:

87 :3(13:(1 .3:[:0
88 8(13:1. ::7
89 ::::~):3:2 3:()

>(F'PC

P1.

'90

::::~:E::

CA(lD

91.

::::~)::5

3:D

TUFi:N ON SEARCH LED
TURN OFF END OF TAPE LED
CLEAR ACCUMULATOR
CLEAR E REGISTER
PLACE ADDRESS OF GET BIT
IN P1.

>::F'AL..

::::HE
LC' I

_i:3:

86

FOR RELOCATION TO X'0000
INITIALIZE RAM POINTER
IN P2

GET STARTING ADDRESS (LOWER)
AN[:' PLACE IN P3
GET STARTING ADDRESS (UPPER)

:'(PAH

p-:;.

:,::PPC

P1.
JUMPL(P2)
P1.

ST
::'::F'PC
ST
::·WPC
ST

JUI'lPU 0:: P2::O
P1.
I.oJDCNTL 0:: P2)
F'1.
~'JDCNTU 0:: F'2::O

:'::F'PC
ST
ADD
ST
ILD
.JNZ
ILD
JNZ
>·':PPC
>,::CIF.:
JZ
L(:OI
::<:F'AL
LDI
;:·WAH
ST
Hf1L T

Pi
@1.O::P3:)
CKSUI'l 0:: P2 ::0
CYSUt'l 0:: P2 )
~'JDCNTL 0:: P2::O
BOOTIN
~,mct-HU 0:: P2::O
BOOTIN
Pi
CKSUt'l 0:: P2::O

L[:oI
;:<:PAL
l..DI
;'-=:F'tiH
::::T
:=':T

L 0:: PEl': I PH::O
PJ:
HO::PEF.:IPH)
P3:
EOTONO::P3:)
SF.:CHON(Pl.)
JUt'lPL 0:: P2)
P3:
JUt'lF'U 0:: P2::O
P3
I!'-i 0:: P::'~)
P3:

GET WOF.:D COUNT (LOWER)
GET WORD COUNT (UPPER)

97
98
99
il313
i131.
i132
i133
1.(14

8~)47

8(149

H)5 8(14B
1.(16
1.(17
i13::::
i139
1.1.(1
ii:1
ii2
i:1:3:
i1.4
1.1.5
1.16
1.1.7

8(14D
:;::(14E
8~)5(1

8~)52
8~)54

::::~355

BOOTIN

-::. ..,.
::::k)5'( ...;.,

::::f::158 CB(1(1
::::(:15A ~)(1
:=:~7.15B

C4~~1(1

8(15[)

~

E::·::ECPF.:

...::.

ii:~: ::::05E C4::::::=:
1.1.9 8(1';(1 ::~':O
1.2(1 :~:~:)6i CE:(1I)
1.21. :=:~Jt:.'::: CBI,);?
1.~:;;~ :=:06~i e;;::OD
1.23: :=:~::16?
1.24 ::::~~16::::: C20C
1.25 ::::06 A _.. f
:126 :=!I) ...~~E: C7FT

1.;;;?

:12::::
1.;29
1.:3:tl
1.:::1.
1.32
1.3:3:
1.3:4
1.','5
1.:3:6
1.3:7
1.38
i3:9
i413
i4:1
i42
i43:
i44
i45
i46

::::(1~::D

L.D

;";PAL·
LD
;:':;F'AH
LL'
;'-:;PF'C

:::F

E~<:ECF'F.:

L 0:: PEl': I PH)
P:(
H(PEF.:IF'H)
p-::'
-,.
EOTON 0:: P3:::O

RECEIVE ROUTINE.
t'iCCUt'lUL:.ATOR.

::::06E C4::::F
:=:1~170 31.
8(171. CA(17
:=:~Z17:3: C48(1
::::"Z17~:~

-.'C"
,,:;.,_1

::::~)76

CR06
C41;:18
CA(15
C40(1

LDI
;:-=:PAL
ST
LDI
;:'::PAH
ST
LDI
ST
LDI

~):1

~':;AE

::::07::::
::::07A
8(17C
:=::(17E
807F
8(180
80:=::2

3:[:'
BA(i5

9802

LOOP:

>'::F'PC
DLD
.JZ

GO TO RECEIVE
STOF.:E AND INCREMENT POINTER
ADD CHARACTER TO CHECKSUM
INCREMENT LOWEF.: WOF.:D COUNTER
CHECK FOF.: ZERO
INCREMENT UPPER WORD COUNTER
CHECK FOF.: END OF TRANSt1 I SS I 0
GET CHECKSUM FROM TAPE
Cot1PAF.:E TO CALCULATED VALUE
EXECUTE LOADED PROGRAt1

TUF.:N ON EOT LED TO INDICATE
CHECKSUI'l ERF.:OF.: AND HALT

TURN ON END OF TAPE LED
TUF.:N ON SEARCH LED
LOAD TF.:ANSFER ADDF.:ESS

DECF.:EMENT POINTER FOR FETCH
EXECUTE

RECEIVES ONE 8-BIT CHAF.:ACTEF.: INTO

LO::CiETBIT)-i
Pi
TEt'lP2 0:: P2)
HO::GETBIT)
Pi
TEt'lPi 0:: P2)

PLACE ADDRESS OF GETBIT
IN Pi
SAVE CURF.:Er·n CONTENTS OF Pi

:::

SET BIT COUNT

BITCr-H(P2)

P1.
BITCNT(P2)
F.:ETF.:N2

Figure 2C4-S (Continued)

2C4-8

CLEAR ACCIJMULATOR
CLEAF.: E REGISTEF.:
GO TO GETBIT
DECREMENT BIT COUNT
CHECK FOR ZERO

147
148
149
15(1
151
152
153:
154
:155
156
157
158
159
160
161
162
163:
164
165
166
167
168
l~q

170
171
172
173
174
175
1:?6
1.7?

8(184

9~3F9

8086 C2(17

F:ETF:N2

8£188 ::1
E:~:1:=:9 C;206
8~3::=:B

3:5

:3(18C 4(1
:::~3:=:D

3:[:'

::=:(18E 9(l[:OE

;

:=:~39(1

C40~~1

::::~3:"'~=,

..:'..::.

.Jt'1P
L[)
::::'2~1

FESET
TEt'1F'4 I. P2::O
F'3:
TEt'1PJ: 0:: P2::O

P:::

Pl
GETBIT

PAGE -DATA WF.:ITE
195
196
197
lq:=:
199
2(1(1

SHIFT E REGISTEF.:
COPY STATUS TO ACCUMULATOF.:
MASK
IF ZEF.:O, BIT F.:ECEIVED
CHECK AGAIN
CLEAF: ACCUMULATO,": FOF~ DELA'T'
DELAY 1 MS (1/4 BIT TIME)
RESET LATCH
I NIT ACCUt1ULATOI<: FOR DELAo.,'
DELAo.,' PAST to1 I DDLE OF WI NDmJ
COF'o.,' STATUS TO ACCUi"tULATOR
NASK
IF ZERO., THEN BIT IS A "1"

(1

.JZ
Jt'lF'
LDE

F.:ETUF.:N

ROUTINES~

SEND 4 SEem·jDS OF "(1" (ABOUT 10(1(1) TO ALLOW FOR
TAPE TO SETTLE ON PLAY BACK AND ACT AS LEADER
OUTPUT OPEF.:ATION OF LED INDICATORS:

Figure 2C4-S (Continued)

2C4-9

IN P3

SAVE ORIGINAL CONTENTS OF P3

CLOCK
Cf:5A

:1.7:::: :;::(jf1F 9::::0,,:

:1.:'::;:

PLACE PEl<: I PHEI<:AL ADDR

;:'::"2i:r

[:"-l ;::: (1

179 :':;:1)[;:1. ::::<004
1:30 ::::OEC 40
1.:'::1 ::::OE:4 i)I.:::::::0

RESTORE Pl TO ORIGINAL
CONTENTS

2f12
2(13:

SEARCH LED ON WHEN LEADER COMPLETE
SEARCH LED OFF WHEN TRANSMISSION COMPLETE
END OF TAPE LED ON WHEN TRANSMISSION COMPLETE

2~:14

205
2(16
2(17 ::::(1C7 C4(1)
2(18 8(1(:9 ::;;::
2~)9 :3(1CA (:4::::2
21(1 ::::~K:C 3:6
211 ::::(1(:D (:400
212 :='::(1CF :l::3:
212: ::::ODO C4:::::3:

2:14 ::K1[:r2

:::7

215 ::::(10:::
2:16 :::::(1D5
2:17 ::::(1[:06
2:1:::: :='::0 [):::
~1.9 ::::ODI'i
;;:;20 :::~)[:,C
;22:1. :::Oi)F

C400

ItHT'

LDI
;'';PAH
LI) I
eeL.

Cot'lP :

.)2
Ft=I~)E:

Cfi[:o
51

CF'I~')E:

C40U
F,':Uf:'
1.:f::llaH

2;~:2

:'.::OFO CEO::'

;::~;;;~.:::

:::::OE;? C:B(ll

;;::;~:4

:::01::4

C4~):::

22';7 ::::OEFI 1.::1"100
2;;:'::: ::::OEI:: CBIj·:t

22::::'

:::~"FE

0:: UPPEF.: >
PLACE PEF.: I PHERAL ADDRESS
IN P3

P]:
CLEAR ACCUMULATOR
CLEAR CARRY~LINK FLAG
FORM 1/S COMP OF LOWER COUNT

(1

t'JDCNTL0:: P2)
~'J[:oCt'HL 0:: P2::O

LDI
I.~:HI)

::: r
:::; r
:::,r
::::r·K'U)k·

CLEAR ACCUMULATOR
FORt·t 1'" S COf'tP OF UPPER COUNT

j..JDCNTU 0:: P2)
~'JDCNTU 0:: P2)
:3F.:CHOF 0:: F'J::EOTUFFO::PJ::-

TURN OFF SEARCH LED
TUF.:N OFF END OF TAPE LED
SET OUTER COUNTER

1...1:) I

;;,;;,:;i :::;:OF6 (:1"10:1.
226 :::OE:::: 14:::0

PLACE RAM POINTER IN P2
0:: Lm.JER)

L 0:: RAt'l:O
P2
HO::F.:AM)
P2
L O::PEF.: I PH)
PJ:
HO::F'ERIPH)

I.::: t·n :1. .

;::.tn:::.

::::1

cr'ITL0:: P2)

L [0 I

;,<. ::::(1

:::' r

CNTU 0:: F'2: ..
Fl..HCi0:: P::::: .:0

::::""1"
L!) I
[:'L'r'

C4~'1~:1

22:0 ::::or: 0 :::1"0,"2::.:l. :::a:1F.~: [:f:IOO
.::.~,.•,:: :.::OF4 9CF6
;~ ..L;: ::::(1FI:~ BfKl1
2:3:4 ::::OF:::: 9'+EE
;23:5 :X1FA C[:~~12

[:OL.I)

:lNZ
[:'L.D

JP
~;T

SET INNER COUNTER
PULSE ~'JF.: I TE FLAG
CLEAR ACCUMULATOR
DELAY 1 BIT TIME
DECREMENT INNER COUNTER
CHECK FOR ZERO
DECREMENT OUTER COUNTER
CHECK FOR LESS THEN ZERO
TURN ON SEARC~ LED

(:1

4
CNTUO::P2)
CNT2
CNTLO::P2)
ern:1
SRCHONO::P3:)

2J:?
BLOCK TRANSFER ROUTINE.
24~J

24:1
:24:2
243:
244
245

246
247
24::::

SENDS BLOCK OF DATA TO CASETTE

THE FOLL.OWING ADDRESSES MUST BE LOADED BY USER BEFORE
EXECUTING THE WRITE PROGRAM:
;,.,; .. ' ::::2(13:
;'·';·::::2~)4

>';"'82(1A
;<"'82(1B

:,.,: .'

::::2~JC

;,.,: ..' 82(1[>

UF'PEF.:
Lm·JEF.:
UPF'EF.:
LOj..JEF.:
UPPER
LOl.oJEF.:

:::: BITS OF PF.:OGRAM A[>[>F.:ESS
E: BITS OF PF.:OGF.:AM ADDRESS

::::

BITS OF PF.:OGRAM LENGTH

8 BITS OF PF.:OGRAM LENGTH
8 BITS OF TRANSFEF.: A[:ODRESS

.-.c·

0:: ENTRY

PO I NT )

BITS OF TRANSFER A[:ODI':ESS

249
25(1
251 80FC C40(1
252 ::::(1FE CA(12
253: :::::1.~3(1 C4::::j_
254 ::::1.(12 3:5
255 :=::1((~: (:444

BLOCK:

L[:oI
ST
L[:'I
>;F'fiH
L.[:II

~:1

CKSUf't 0:: P2)
H 0:: ~'JF.: I TE ::0

Pi
L(~.JF.:ITE)-:1

Figure 2C4-S (Continued)

2C4-10

CLEAR ACCUMULATOR
INITIALIZE CHECKSUM COUNTER
PLACE ADDRESS OF WRITE IN P~

256
257
25:::
259
260
261.
262
263
264
265
266
267
268
269
2713
27:1

::::1(15
C:1J)6
::::1.(1:::
E:1.(19
:::1.(lB
810e
81eE
81eF
811:1
8:1:12
8:1:14
8:1:15
E:::11.7
8:1:18

J::l
:~:[:,

:";F'HL
U:"l
,··';f:'f:'C

C204

LD

1.:At:l~

::0
C203:
3:D
C20[)
3:D
C2(lC
::D

1... 1>
:,":F'F'C

C2~)B

[..[:0

::[:0

>':F'F'C

1...1""
>T'PC

LC'
:'-o:PPC

C:;::0A

L l>

8:1.:tA ]:[:0

::::1:1E: C204

:\PF'C

CiETE:'T'T:

272 :=::1:1.D ;:::1.
27:' :::::t:tE c~:'o:::

I.

274 ::::t;;: 0 ~, ~-:,
275 :::::1.:21. C!::;Ol

;;::76
277
;;;;:7::::
279
2::;:(1
2::::1.

:.1.

:::::l.:;:?

CH~.)4

r,

>':F"fIH
I. [:.

,cf'IF
LT'!

::::l:??: 0.1.
:::::1:;:4 (444
::::::1.;~:I;

L C'
>·:F'AI....

•

F~:IL.

, .. T

.::

::::L:::::3 (",+::::;:1..

I

LCd
.'"':Pf:IH

2::::~:':~

:='::1.21:.': ::.~:;
:::::l;;::C CfIO::::-

:c:r

2::::::::'

:~::l.':::E

L[",[

40

2:::::4 ::::12F F:20:?

tiL'i::-

2::::~

'::;T

:=::l~~::1

CA(I.::::

::::1..J:~1

r·'.l

..:~I..tnf"'L.. I .. ~..• ~~:.!
P.l.
..J!...Ir'1f"u':P;:':-

GET TRANSFER ADDRESS

P1
[,.I[:OCtHL (P,;:::o
Pt.
~,j[:OCt·j fU 0: P2::F.l
::;'mVfL 0:: F'2::F:1
':,If'iF: TU 0:: F'2:.o
1"'.1..
I.~.L '" "-'.1.'
L."'~F.I.

GET LENGTH

i

AAf)[:

2E:9 ::::1..:':7 geE2
29f1 ::::1::9 AAOH
;291. :::::1 :em 9 CT' E
29;: ::::1]:[:0 C2~3d:
293: ::::::1.::r ]:[:0
;;:~94 :::::140 CBOJ:
295 :='::14:;:: CBOO
296 8144 ~:10

fE."-1.

::C'1.

.:.: i t li;,:'1 L '.Y'::: .:H<~'lkl·iE.'

F':l.
::: rHI?T 1..1 0:: P2.:-

UPDti TE CHECf:::SUt'l

Cf·.:·:·:Ut'l 0:: F'2.:Cf::::::ut'i(f"d:..o

i':F'PI....
II...r.:,

F"l

JNZ
:r L.I'

(~El'E:"I"'r

TrC
L.D
;"';PPC'

::::T
::;T

PLACE CURRENT ADDRESS IN P:1

CiEr CHARACTER THROUGH
POINTER AND SAVE IN E REG.
CiET ADDRESS OF WRITE AND
SAVE CURRENT CONTENTS OF P:1

LJ>F

2::::6 :='::13::': 40
:~::::::7 :,,::1..:::4::[:0
2::::::::

LOAD ACCUMULATOR WITH ID
WRITE ID ON TAPE
GET STARTING ADDRESS
I.ojF.: I TE ONTO 1 APE

P1.

PLACE CHARACTER IN ACC.
:;END CHAF.:ACTER
INCREMENT WORD COUNTER
CHECK FOr;:: ZEF.:O

.,.1[.' C: t·n L. (. P:;: .:,'~L.. CNTU '.:

f·'d:::-

SEND CHECKSUM TO TAPE
f":1
::::Pt::HOF (. F'J. ::EcnUNo:.f":3:)

TURN OFF SEARCH LED
TURN ON END OF TAPE LED
HALT WHEN FINISHED

HtiL..T

297
298
299
3:130
3:131.
302
303
3:134
3135
3136
3:137
308
3:139
3::1(1

WRITES 1. 8-8IT CHARACTER ON TAPE

DATA WRITE RUUTINE.

:31.45
81.46
8148
81.4A
8:14B
8:14[)
8:14F
8:15:1
8:153

~H

C4(1::::
CA(15
4(1
D41;::1:1
9C(1::::
C40(1
C:E:~~14

8F(14

~,jR

I H:. :

t'lASK :

SEt·jD(l :

:'::T BIT
I<:ETUI<:N

FLACi (. PJ:::O
~)

9:3(1;;::
9C1E0
3:[l
90D:=::

.Jr'lP
F.:ETF.:N:1 : ;:":PF'C

:=:(10~)

EN[)

BOOT

:::::(1FC ·t,

BOOT

::':~C1::"B

CK:::;Ut"1

~:1~~1~:::12

::::"jE::::

ct·n~':

:=:~:::1EC

(lIj~JO

::::~jDJ:

'::11:')01
:::::::fCKi

COt'lP
E:'·::ECF'F.:
GETB'T'f
.JUt'IPU
t'l A::::; f'::
P.2
PAI"l

:'3~jE:?

PETf"rU

C10~)7

1:: L.. 0::::: 1<
Cf·.:::,H
eN"!:).
c:tnu
EOTOt·j
CiFTC.t r
.JUt'IF'L
L.OOP
P:l.
F'f,RI PH
PE:::'FT
F.:ETPt·C·
:3ETf"NT
:::;PCHOF
STi=lRfl...1
TEt'1F'J:

(1(1(18

~'l[:OCt·jT'-'

.JZ
.Jto1p

~'~RITE FLAG
TO I'1IDDLE OF WINDOW
~'~I<: I TE FLAG
ACC. FOR DELA'T'
TO END OF WINDOW

PULSE
[)ELA'T'
PULSE
CLEAI<:
DELA'y'

.2

:310
[)L.D

BA(l~i

SHIFT
(1
FLAGO

I I I I •

~T~

DBO
OBI

~

~,~

DB2
DB3

I I 1•

t2 3)O
T(

DB4

~TE3)O

DBS

I I •

.. I

t2T,:>o

DB 7

NOTES:

1. Hex inverter (OM 7404) or equivalent

_,Iow'_

+10V

"(241

2. TTL/MOS H•• invert8f 10M 7812) or equiva ..... t

3. 2-lnput AND Gate (OM 7408I"or equiv8$ent.
4. I. SCIMP chip is not
_ _ . . requi....t- figure 1-8 for
_
SCIMP chip.

TO SENSE A
elF SC/MP

.0015,<'
4.7
':"

':"

+5V

NS10568

Figure 2C4-6. SC/MP Interfaced with Seiko Digital Printer

~

COLUMNS

---..------To

TI

T2
T3

T4

TC
T6
TI

TR

10

Tq

11

TIO

T"

----1n I____________________________________________________________________________

n L-----

I

PRINT
(NOTE COMMAND
21

I

I

I
MOTOR STOP

~GNAL

I

1

I
r
---.;.I-------------------------------.J
~
I

IJ

I....-....~I-

MOTOR DRIVE
SIG (NOTE 21

I

(NOTE 11

BLANK POSITIONS OF
EACH PRINT WHEEL

~

B

I \.

~

TYPE II
IGREATER THAN ~
50 mSEC (Note 41

10 TO 80 mSEC

I

~L--~====~00lli~====~------~
NOTE 3

TIMING SIGNAL

:

(NOTE 21
SELECTPULSE'O'
_________

SELECT PUI.SE 'I'
(NOTE 21

~lln. --------------------------------------------------------_______~__
•

•

.. I

TO
BLANK__
POSITION
A_L_L_P_R_IN_T
W_H_E_E_L_S_R_E_T_U_R__
N

II--~~I
LESS THAN
I.
_
1.5mSEC

------------~I

~I---~-------------------------------------------------------------------------II

~~~~~irULSE'2' _________________4JIr--l..------------------------------------------------________________________
COLOR CHANGE
PULSE (NOTE 21

PLATEN
PRINT

PAPER
FEED

0"
~MAIN

90"

180"

360"

270"

SHAFT

....t - - - - - - - -

TYPE I

=APPROXIMATEL Y 400 mSEC TYPE II =APPROXIMATEL Y 430 mSEC

~I

- - - - - - - -.......

(VARIES·ACCORDING TO PRINTING SPEEDI
NOTES;
1. Printed 'Red' in columns 04 through 016 to represent negative result.

2. These signals are generated by SC/MP.
3. Time period between TN and TN+l "" 13 to 25 mSEC.
4. For a 'Type I' timing cycle, implement 8 3D-millisecond dalay between last trailing edge of

'Aeturn' signal and leading edge of 'Print' comm.,d; for a 'Type II' timing signal, implement a
50·millisecond delay between le.ding edge of 'Motor Stop' signal and leading edge of
'Print' command.
5. For further detail on Model 310 OIGITAL PRINTER, refer to specification sheets and
other documents of manufacturer IShinshu Seiki Co., Ltd. of Japan); for further detail
on devices OM 8693 and OM 8694, refer to specification sheets of National Semi·
conductor Corp.

Figure

2C4~7.

Column/Character Relationships and Timing for One Print Cycle

2C4-15

NS10569

System Operation
The SC/MP-to-printer interface is implemented via a specialpurpose chip set that includes interface logic #1 (DS 8693),
interface logic #2 (DS 8694), and two transistor arrays (DS
8692). The DS 8693 device contains the interface logic for
the color solenoid driver, the motor driver, and seven of the
column/character select solenoid drivers; the DS 8694 chip
contains the interface logic for eight column/character solenoid drivers plus the clock oscillator and timing-signal
buffer. Each transistor array contains eight common-emitter
output circuits - each circuit features active pull down and
each can sink up to 350 milliamperes of current. Address
decoding for the printer interface is performed by a BCD-todecimal decoder (DM 74LS138). Hexadecimal address
X'0200 is assigned to access the printer; address assignments
for interface control are as follows:
Hex
Address

Function

0200

Printer Interface

0201

Clock IN 1

Used to load DS 8693 with
print information for columns D 10 through D 16

0202

Clock IN2

Used to load DS 8694 with
print information for columns D I through D9

0203

Common Clock

Used to clear DS 8693 and
DS 8694

0204

Print

Used to issue PRINT COMMAND

Remarks

ROM

The printer program continuously monitors a data buffer
that is maintained in RAM (figure 2C4-8). This buffer is
filled by any appropriate input device (keyboard, tape, or
other), and when filled, the program is executed to print a
line consisting of 16 characters. As shown in figure 2C4-7,
the 16 columns (each column corresponding to a print
wheel) are divided into two column words - COLWORD 1
representing the characters to be printed for columns D1
through D9 (D3 is blank) and COLWORD 2 representing
characters for the remaining columns (D10 through D16).
The character codes for each column and the constants
used to select a particular column are stored in ROM. When
the characters stored in the data buffer for a particular
column agree with those in the character code list, the print
wheel for that column is mechanically latched; thus, at the
end of the timing cycle (To - - - - Til), all 16 print wheels
are locked in position and the line is printed. The following
example shows the interrelationships between the columns,
the characters, the timing pulses, and COLWORDS 1 and 2.

RAM·

·REMAINING RAM LOCATIONS
ARE UNUSEO.

NS70570

Figure 2C4-8. Memory Allocations for Printer Program

2C4-16

drive signals also are reset until the arrival of the next print
command.

(NOTE: The TTL to MOS inverters in the interface devices
require that the column drivers be driven with a logic '0' for
selection; that is, the print wheels lock into position at a
particular timing pulse if the COL WORD bit co"esponding
to that position is a logic '0 '.)

Software Considerations
The flowcharts (figure 2C4-9) and program listing (figure
2C4-1O) shows how the SC/MP-to-printer interface can
be software-controlled to provide the foregoing printing
capabilities.

After the line of data is printed, all print wheels are unlatched and return to the blank (B) position; the motor

COLUMNS

~

016

CHARACTER

~

9

1
1
1
1

015 014 013

012

011

010

09

8

7

6

5

4

3

2

1

1
1

1
1
1

1

08

07

06

o

05

04

6

6

1
1

1
1
1

1
1
0
1
1
1
1
1

1
1
0
1
1
1
1
1

03

02

01

•

M

TIMING SIGNAL
To
T,
T2
T3
T4
T5
Ts
T7
Ts
Tg
T,o
T"

~
~
~
~
~
~

..........

1
1

1
1

1

1

1
1

~

~

~

0
1

1
0
1
1
1

0
1
1
1

1
0
1
1
1

1
1
1
1
0
1
1
1
1
1

1

0
1
1
1
1
1
1

1
0

0
1

1

1
1

1
1
1
1
1

1
1
1
1

2C4-17

1
0
1
1
1

1
1

0
1
1
1
1
1
1
1
1
1

0
1
1
1

1
1
0
1

1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
0

SETUP Pl AS TEMP
STORAGE PTRX'Ol10; LOAD P2U
WITH X1)QAND
CLEAR CLOCK eTR

..

GENERATE COLUMN
WORDS 1 AND 2 FOR
NEXT PRINT CYCLE
BY COMPARING
CHARACTERS IN
DATA BUFFER WITH
CHARACTERS IN
CODE LIST FOR 01
THROUGH 016

SEND COLUMN WORDS
1 AND 2 TO INTERFACE
CHIPS (OS 8693 AND
OS 86941; INCREMENT
RINTER CLOCK COUNTE

~

B' ,

NO

SETUP P2L WITH AD·
DRESSES OF COLUMN
WORD CONSTANTS AND
GENERATE NEW COL
WORD 1

EXIT

TO SETUP P2L fOR
COLUMN WOAD CON·
STANT, ADD X'OF
TO VALUE OF CON·
STANT

EXIT

NS10571

Figure 2C4-9. Summary and Detailed Flowchart for SC!MP-to-Printer Interface

2C4-18

1.
2
3
4
5
6
7
8
9
1.121
1.1.
1.2
13
14
1.5
1.6
17
18
1.9
2121
21
22
23

24
25
26
27
28
29
3121
31.
32
33
34
35
36
37
38
39
4121
41.
42
43
44
45
46
47
48
49
5121
51.
52
53
54

SCMP,

=
=
=
=
=
=
=
=
=
=
=
=
=

1.
2
3
1.
2
3
4
12121210
1.
2
4
5
6

NOP
LOI
XPAL
LOI
XPAH
ST
LOI
XPAH
LOI
XPAH
LOI
XPAL
LOI
ST

L(SEIKO)
P3
H(SEII~PAL

P3
TEMP1(P1)
0F
TEMP2(P1)
-9
GENCOL2
TEMP2(P1)
0F0
P2
-1(P2)
COLloJR1(P1)
COLWR1(P1)
TEMP2(P1)
SCNCHK
TEMP2(P1)

WO~:D

CONST.

ADRS.

; COL WORD CONST TO ACU

73:

74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
1013
1131
102
103
1134
1135
106
107
108
109

0059 D105
005B C905
005D 90CE
005F
0060
13062
01364
1211366
0068
aa6A
006C
e06E
0e6F
13071
131373
01375
01377
0079
e07B
007C
007E
007F
131381
13083
131385

33
C901
[)40F
C9a2
F4F7
94aF
C1a2
F4Fe
32
C2FF
D105
C905
C1e2
90C4
C102
132
F4F0
C2FF
0106
C9a6
90EE

ST
ANI
ST
ADI
JP
LD
ADI
XPAL
LD
AND
ST
COL2RET:LD
JMP
GENCOL2:LD
CCL
ADI
XPAL
LD
AND
ST
JMP

131387
0088
008A
0a8C
0a8E
0a8F
0091
0092
0094

136
D410
9CFB
C400
33
C402
37
C105
CB02

FNSHSCN:CSA
ANI
JNZ
LDI
XPAL
LDI
XPAH
LD
ST

'3: .....

_tf..

COMPR2:

aF0
P2
-1(P2)
COLloJR2(P1)
COL~JR2 (P1 )
COL2RET
010
FNSHSCN
L(SEIKO)
P3
H(SEIKO)
P3
COLWR1(P1)
CLK2(P3)
Figure lC4-10 (Continued)

2C4-20

.; SAVE DATA BFR ADRS
.; MASK UPPER BITS
; SAVE COLMN COUNT
.; COL COUNT>8
.; GET COL COUNT
; ADD ADRS FOR COLWR[) CONST
;COLWRD CONST TO ACU
; GENERATE COLWRD1
; SAVE NEW COLWRD1
; LO COLMN COUNT
; GO TO SCAN COMPL T CHK RTN.
; GET COL COUNT
; ADD ADRS FOR COLWRD CONST
;COLWRD CONST TO ACU
; GENERATE COLWRD2
; SAVE NEW COLWRD2
;XFR SENSEA TO ACU
; CHECK IF SENSE A PRESENT
; LOOP BACK TO FINISH SCAN
.i GET SEIKO ADRS.

; GET COLWRD1
) XFR COLWRD1 TO PRINTER

110
11.1.
1.1.2
113
1.14
115
1.16
11.7
118
11.9
1.20
1.21
1.22
123
124
12S
1.26
127
1.28

0096
0098
ee9A
0e9C
ee9E
e0A0
00A2
e0A3
e0AS
00A6
00A8
0eAA

00ce
00Cl
130(:2
eeC3
eeC4
0eC5
00C6
eeC7
129 0eC8
eeC9
00eA
0eCB
1.30
131.
132
133 1210013
e001
e002
0003
e004
01305
131306
131307
1.34 0008
13009
000A
121008
13S
136
137
138 e0E0
0eE1.
00E2
00E3
e0E4
00ES
00E6

C106
C801.
Age4
E4eo
98138
C400
37
C41S
33

93FF
C4FF
C803

DONE:

LO
ST
ILO
XRI
JZ
LOI
XPAH
LOI
XPAL
JMP
LOI
ST

COLWR2(Pl)
CLK1. "6", -'7"

Figure 2C4-10 (Continued)

2C4-21

eeE7
139 eeE8
aeE9
aeEA
lZIaEB
1.4121
1.41.
1.42
1.43 eeFIZI
elZlF1.
elZlF2
1Z10F3
0aF4
lZIeF5
IZI1Z1F6
IZI1Z1F7
1.44 elZlF8
aeF9
aaFA
1Z10FB
aaFC
alZlFO
IZIIZ1FE
alZlFF
1.45
1.46

CLK1.
CLKCTR
COL2"~E

COU.JR2
CONST
DONE
GENCOL
P3
RETCOM
TEMP1.

37

3:S
3:9
2E
20

· BYTE

eeFe

· =aFa

FE
FD
FB
F7
EF
DF
BF
7F
FE

CONST:

,"s . . , . . 9-', ....... , -,_ . .

· BYTE

0FE,IZIFD,aFB,IZIF7,IZIEF,IZIDF,IZIBF,1ZI7F

· BYTE

IZIFE. eFD .. IZIFB. IZIF7. eEF .. IZIDF, eBF. 1Z17F

· END

PRNT

F[)

FB
F7
EF
OF
BF
7F
lZIaa1.

IZIIZ1IZ11.
a0e4
lZIa75
eee6
elZlFe
€leAS
aa79
aae3
ee20
aae1.

*'

CLK2
COL1.
COL4
COMPR1.
CONTPR
EXIT
P1.
PRINT
SCNCHK
TEMP2

1Z11Z102
aaca
€IeEe
ae54
13131.6
eaAC
aae1.
aee4
elZl30
aaa2

*'
*'
*'

*'

CLK3:
COL2
COLWR1.
COMPR2
CONTSC
FNSHSC
P2
PRNT
SEIKO
TEST

NO ERROR LINES
SOURCE CHECK5UM=4E54

alZl03
aaoe
eea5
lZIe5F
ee34
1312187
aee2
eee1.
a2ae
ae40

*'

NS10572

Figure 2C4-10 (Concluded)

2C4-22

APPENDIX A
CLOCK CONSIDERATIONS FOR SC/MP
GENERAL

voltage that is equal to or greater than 25 volts is recommended. Lead length from the body of SC/MP to the body
of the capacitor should not exceed 1.25 inches. When a
capacitor is used, the frequency varies according to the
capacitance as shown in figure A-2.

The on-chip oscillator and timing generator of SC/MP can
be controlled by anyone of the following three methods:
• CAPACITOR - if timing is not a critical
parameter
• CRYSTAL - if more precise timing is required
• EXTERNAL DRIVE - if application requires that
SC/MP be synchronized with system clock

CRYSTAL TIMING
When a crystal is used, the on-chip oscillator of SC/MP
operates at the resonant frequency of the crystal. Pin connections and lead lengths for a crystal are identical to those
for a capacitor; however, as shown in figure A-I, a capacitor
may be required to suppress crystal harmonics. The crystal
should be hermetically sealed (HC type can) and should
meet the following electrical specifications.

CAPACITOR TIMING
As shown in figure A-I, the capacitor is connected between
Xl (pin 37) and X2 (pin 38) of the SC/MP chip. A nonpolarized ceramic or silver mica capacitor with a working

BODY OF
CAPACITOR

-HNOTE:
CAPACITOR Cl MAY BE
REQUIRED TO SUPPRESS
CRYSTAL HARMONICS

WHERE
(~ .. 1.25 INCHESI
IS THE DISTANCE
FROM THE BODY
OF SC/MP TO
THE BODY OF
CAPACITOR
OR CRYSTAL

OR
CRYSTAL

-fl~

Vss

.
Xl
I

Fi&ure A-I. Connecting Capacitor or Crystal to SC/MP

Cl
~
SOOpf , -

.....L

SENSE A

s

9
M
P

SENSE B

1400

FLAG 0
1200
FLAG 1
1000

iL

.,s.
w
Z
c(
t-

FLAG 2
SOUT

800

U

SIN
600
NADS

U
c(

...
c(

400

VGG

u

200

O~~~~-~-~-~-~~0.0

0.2

0.4

0.6

0.8

1.0

1.2

NORMALIZED FREQUENCY (flf@ SOD pFI

1.4

NS10574

NS10573

Figure A-l. Oscillator Frequency versus Capacitance

A-'

• Resonant frequency - - - - - - - - - - - - - - ~ 900 kHz
~l MHz
• Series resistance at resonance - - - - - - -~ 600-ohms
• Load capacitance at resonance - - - - - -20-to-30 pf

USING AN EXTERNAL CLOCK
SC/MP can be synchronized with an external clock simply
by connecting appropriate drive circuits to the XI/X2
inputs. A recommended method of implementing the
external-clock circuit is shown in figure A-3a; the true and
complemented "idealized" waveforms are shown in figure
A-3b. Alternate methods of generating the XI/X2 input
signals are shown in figure A-4.

Suitable crystals can be obtained from several manufacturers; four such manufacturers are listed below.
•
•
•
•

X-Iron Electronics, Hayward, California
M-Iron Industries, Yankton, South Dakota
Crystek Crystal Co., Ft. Myers, Florida
JAN Crystals, Ft. Myers, Florida

36011
±5%
EXTERNAL
CLOCK

lK
±5%

s

36011
±5%

~

M
p
NOTE:
Any 74H-series flip-flop
connected in a divide-bytwo configuration can be
used in this timing
application_

t,

NADS

LOGIC 1

VGG

90%

WF1.
LOGIC 0
NOTE: Waveforms WF-l and WF-2
are interchangeable at the
Xl/X2 pins of SC/MP; each
waveform should be an approximate 50% duty cycle_

tr
LOGIC 1

WF2.
LOGIC 0

- l l too

LEGEND: lItoo ;;" 0 to 20 !]sec
t _ ; ; . 4!]sec
r
.;; 25 !]sec
t
;;'4!]sec
f - . ; ; 25!]sec

NS70575

Figure A-3_ Using External Clock for SC/MP Timing

A-2

FROM SYSTEM
CLOCK

360H
±5%

TO PIN 37
OF SC/MP
+5V

360 H
±5%

+5V

TO PIN 38
OF SC/MP

VSS

FLAG 0

Xl

FLAG 2

X2

FLAG 1

SENSE A

NWDS

SOUT

ENIN

SIN
2·INPUT EXCLUSIVE
OR GATE
(OM 74S86)

SENSE B

m

=).. "
FROM SYSTEM
CLOCK

S

AD 00

360H
±5%
360 H
±5%

TO PIN 37
OF SC/MP

AD01
AD 02

+5V
AD 03
TO PIN 38
OF SC/MP

AD 04
AD Of
AD 06

FROM
CLOCK
360H
±5%

TO PIN 37
OF SC/MP

ENOUT
BREQ
NHOLD

~

NRST
CONT

M
P

NADS

NRDS

DB 00
DB 01

ADO:'

DB02

ADOR

DB 03

AD 09

DB 04

AD 10

DB 05

AD 11

DB06

VGG

DB 07

+5V
NOTE:

360H
±5%
TO PIN 38
OF SC/MP

For these circuits, the system clock input should
be a 50% duty cycle.

NS70576

Figure A4. Alternate Methods of Generating External Clock Signals

A·3

APPENDIX B
ADDRESS ASSIGNMENTS AND DECODING METHODS

INTRODUCTION

Nondecoded Peripheral Addressing

The addresses for memory and peripheral devices can be
assigned and decoded in a number of different ways; some
address assignments and decoding methods are shown and
described in the sections that follow.

As previously indicated, 16 address lines (AD 00 through
AD 15) are available; 12 of these lines (AD 00 through
AD 11) are internally latched on the SCjMP chip; whereas
the other 4 lines (AD 12 through AD 15) are output (at

NOTES
NWDS

VGG

NRDS

NADS

EN IN

X2
Xl

1. To elimiNlte buffering of add,..
Ii.... low power or low-power
Schottky TTL pteI .... UIed.

2. eSl. CS2 end SEL Ire 1tCtiv.-low
signlls. Refer to truth table below.
The tri-ltate output diuble 1001

signal must be low to enable output.
DEVICE SELECT

AD 11

BREa

AD 10

NRST
CONT
DB 07
DB os

05
04

03
0802

S
C
/
M
P

01

TRUTH TABLE

ADDRESS BITS
10
11
09

DEVICE
SELECTED

ADOS
AD 08
AD07

ADOS
AD 05

0

0

0

PROM

1

0

0

RAM

X

1

X

X

X

1

READ

DEVICE

:;;~:~E

X· DON'T CARE

AD 04
AD OJ

1\002

ADOl

00

ADOD
SIN

SOUT
FLAG 2

V,,

FLAG 1

NS70577

Figure 8-1. Using External Logic and Spare Address Unes to Select RAM/pROM Memory
or Input/Output Peripherals
8-1

When power is applied and SC/MP is initialized, all the
address bits are low (set to '0') and PROM is selected;
thus, program execution begins at PROM address X'OOOI.
Observe that with AD 09 set to '0', RAM is not selected
because CS2 is high and neither the read nor the write devices can be selected because both SEL signals are high.
For an application example, suppose the PROM program
requires access to RAM, to the read device, and to the
write device; the folloWing series of instructions shows
one way to implement the read and write functions.

NADS time) on the 8-bit input/output bus. Most applications do not require all 16 address lines for memory.
For example, consider the system shown in figure 8-1 consisting of 512-by-8 words of PROM, 256-by-8 words of
RAM, a read device, and a write device. Nine address lines
(AD OO-AD 08) are required to discretely identify each of
the 512 bytes of PROM and only 8 lines (AD OO-AD 07)
are required for RAM; thus, the 3 remaining address bits
(AD 09/ AD 10/ AD 11) are free and can be used for device
selection. The 'device select truth table' shows how this
can be done.
READ FROM RAM:

•
•
•

LDI

02

XPAH
LDI
XPAL
LD

2
05
2
(2)

;WHEN TRANSFERRED TO HIGH POINTER BY
;NEXT INSTRUCTION, TURNS ON BIT 9 TO
;SELECT RAM
;SET BIT 9 OF POINTER 2
;LOAD RAM ADDRESS 5 INTO ACCUMULATOR
;PUT RAM ADDRESS IN LOW POINTER 2
;LOAD DATA FROM RAM ADDRESS SPECIFIED IN
;POINTER 2

•
•

•

WRITE INTO RAM:

•
•
•

DATA:

LDI

02

XPAH
LDI

2
X'10

XPAL
LD
ST

2
DATA
(2)

.BYTE

X'1F

•
•
•
READ FROM "READ DEVICE":
•
•
•
LDI

04

XPAH
LD

1
(1 )

•
•
•

;WHEN TRANSFERRED TO HIGH POINTER BY
;NEXT INSTRUCTION, TURNS ON BIT 9 TO
;SELECT RAM
;SET BIT 9 OF POINTER 2
;LOAD RAM ADDRESS (DECIMAL 16) INTO
;ACCUMULATOR
;PUT RAM ADDRESS IN LOW POINTER 2
;LOAD DATA TO BE STORED
;STORE DATA IN RAM ADDRESS SPECIFIED BY
;POINTER 2
;DATA TO BE STORED

;WHEN TRANSFERRED TO HIGH POINTER BY NEXT
;INSTRUCTION, TURNS ON BIT 10 TO SELECT
;"READ DEVICE"
;SET BIT 10 OF POINTER 1
;READ DATA FROM DEVICE (NOTE: LOW POINTER 1
;IS NOT REQUIRED FOR THIS OPERATION)

8-2

WRITE INTO "WRITE DEVICE":

•
•
•

LDI

DATA:

XPAH
LD
ST
.BYTE

08

DATA
(1)

X'AA

;WHEN TRANSFERRED TO HIGH POINTER BY NEXT
;INSTRUCTION, TURNS ON BIT 11 TO SELECT
;''WRITE DEVICE"
;SET BIT 11 OF POINTER 1
;LOAD DATA TO BE WRITTEN
;WRITE DATA
;DATA TO BE WRITTEN

•
•
•
READ AND/OR WRITE:
LDI

OC

XPAH
LD
ST

(1)
(1)

1

;WHEN TRANSFERRED TO HIGH POINTER BY
;NEXT INSTRUCTION, TURNS ON BITS 10 & 11
;TO SELECT READ AND WRITE DEVICE
;SET BITS 10 & 11 OF PTR 1
;READ DATA FROM READ DEVICE
;WRITE DATA THAT WAS PREVIOUSLY READ

important consideration. If the access time is greater than
the strobe width, bipolar memories can be used or the
RAM/PROM devices can be selected as shown in figure
B-l-via the external logic and the latched address lines.

Observe that the read and write peripherals must be strobed
by NRDS or NWDS; otherwise, the selected peripheral
would input or output data as soon as the address is valid,
and, at the same time, SC/MP would output address and
status information. By strobing the chip selects, reading or
writing of data is delayed until the "address" and "status"
outputs from SC/MP are completed. Strobes are not required in the address logic of the RAM or PROM since the
on-chip output-enable (OD) signal provides this function.

In figures B-1 and B-2, three latched address lines are
always available since memory is arbitrarily restricted to
512 bytes. Some applications require 4K of memory (or
more) and, in this case, there are no spare address lines for
device selection; figure B-3 shows how address bits 12-15
can be used to implement a system of this type. The 4 address bits (AD 12-AD 15) are output on the data bus at
"address/status time," and the leading edge of the address
strobe (NADS) latches these bits into the DM85L51 chip.
The binary address code then is inputted to the 4-by-16
decoder, which selects 1 of 16 peripheral input/output devices in accordance with the decoding select logic. In figure
B-3, the 16 peripherals can be any combination of read,
write, and read/write devices whose input/output characteristics are compatible with SC/MP. Observe that the decoder is strobed; thus, access time of all peripherals
must be less than the strobe widths-refer to figure 1-4 for
timing parameters.

Decoded Addressing of Peripherals
In many applications, the addressing requirements of the
system exceed those shown in figure B-1. For these systems, discrete selection logic is expensive, cumbersome,
and complicates the software; thus, some form of address
decoding is preferred. Figure B-2 shows one way of implementing a simple decoding scheme. Here, address bits 10
and 11 are decoded by one half of the 74LS155 to yield
four output select signals; address bit 9 is used to select
RAM or PROM. In figure B-2, all chip selects are strobed
via the decoder; thus, access time of the memory chip is an

8-3

NWOS

VGG

NRDS

NADS

ENIN

X2

ENOUT

Xl

BREO

ADll

NHOLD

AD10

NRST
CONT
DB 07
OBoe
DB 06
DB 04
DB 03
DB 02

S

NOTES:
1. To .limin... bufforing andlor
minimize loading. low power on
low·_r Schottky TTL glltos
are used.
2. If strobe widths are not wide enough
for accau time relative to chip select,
UIO RAMIPROM ..Ioct circuits shown

in Figure B·l.
3. CS1, CS2, SEL A, SELS, and SEL C
a" active-low signals; refer to truth
table below. The tri-ltate output disable
(001 signal must be low to enabl. output.

ADOS
ADOS

C

DECOOING SELECT
TRUTH TABLE

AD 07

/

SELECT
A B
X X
L L
L H
H L
H H
X X

AD 06
AD 05

M
P

AD 04
AD 03

INPUTS
STROBE
Gl
H
L
L
L
L
X

OUTPUTS
DATA
Cl
X
H
H
H
H
L

1Y0

1Yl

H

H
H

H
H
H
H

H
H
H

1Y2 1Y3
H
H
H
H
H

X

~

DON'T CARE

AD 01

0800

ADDRESS MAP

AD 00
SIN

SENSE B

lOUT

FLAG 0

FLAGZ

VII

FLAG 1

ADll
0
0
1
0
1

AD 10
0
0
0
1
1

ADOS
0
1
X
X
X

DEVICE SELECTED
PROM
RAM
PERIPHERAL A
PERIPHERAL B
PERIPHERAL C

X • DON'T CARE

f'[HIPH[H/\L

~\

ADC»-AD 07
SEL A ....~------,

R[IJ..D Pl Rlf)HlH/\..L

B

SELB ....~--.,

H

AD 02

DB 01

Hl~[)

H
H
H
H

NOTE2----------------+-----~

SELC~~-----------------------_i

NS70578

Figure B-2. Using 2-by4 Decoder to Select Memory and Input/Output Peripherals

NOTES,

1. To eliminate buffering andlor minimize loading,
low power or low-power Schonky devices are

"ted.
NWDS

VGG

NRDII

NADS

ENIN

X2

ENOUT

XI

BREa

AD 11

NHOLD

AD 10

S
C

NRST
CONT
DB 07

/

DBOB

0806

M
P

DB 04
DB 03

0802

2. The addrns bus is connected to memory peripherals as required; for example if peripheral
=1 is. 4K PROM, all 12 latched address lines
are used - if peripheral .... 2 is a 512-word RAM,
only 9 address lines are used, and so on.
3. SEL 1 through SEL 16 are active-low signals; ref.r
to truth table below:
DECODING SELECT
TRUTH TABLE
INPUTS
Gl G2 A B C
L L
L ILL
L L L L L
L L L L H
L ILL L H
L L L H L
L L L H L
L L L H H
L L L H H
L L H L L
L L H L L
L L H L H
L •L H L H
L iL H H L
L L H H L
L L H H H
L L H H H
L H X X X
H L X X X
H H X X X

ADOB
ADOS
AD 07
AD 06
ADOS
AD 04
AD 03
AD 02

DBOI

ADOI

DB 00

AD 00

SENSE A

SIN

SENSE B

SOUT

FLAG 0

FLAG 2

VII

FLAG 1

0

0

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X

1
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

1
H

I.
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

2
H
H

to
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

3 4
H H
H H
H H
t; H
H ..
H H
H H
H H
H H
H H
H H
H H
H H
H H
H H
H H
H H
H H
H H

OUTPUTS
7 8 9
H H H H
H H H H
H H H H
H H H H
H H H H
H H H H
I. H H H
H L H H
H
H H
H H H IH H H H
H H H H
H H H H
H H H H
H H H H
H H H H
H H H H
H H H H
H H H H

5 6

10 '1 12 13 14 15

H
H
H
H
H

H
H
H
H
H
H
H
H
H
H

I.
H
H
H
H
H
H
H
H
H
H
H
H
H

"

L
H
H
H
H
H
H
H
H

H
H
H
H
H
H
H
H
H
H
H

L
H
H
H
H
H
H
H

H
H
H
H
H
H
H
H
H
H
H
H

H
H
H
H
H
H
H
H
H
H
H
H
H

H
H
H
H
H
H

L

..

tf
H
H
H
H

H
H
H
H
H
H
H
H
H
H
H
H
H
H

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

tf

"

..

H
H
H

tf

H
H

~. . . . . . . . . . . . . .rNDTE2

II LINE TO lb LINl
DECODER OM 74LS1'J41

::PtiL

E::::PAH

C(1E~)

L..[:O

(1Fl? (17
C"-'
,-''::' f1F1:~: CODF
53: 0F1A (1~i
54 ~)Fl.E: ::E:F
55

,: RESTOF.:E P1

P:i

; F.:ESTOF.:E p2

P;;~H

p;;::

PCL

,: F.:E::::TOF.:E RETUF.:N ADDR

PJ:
PCH
P3:
STflTUS

,: RESTOF.:E STATUS REG.

tiCU

,: F.:E5TOF.:E ACU

CA:;
L[:O

lEN
~'::PPC

P3:

r::-.-

._It.

PAGE

~INTERRUPT

ROUTINE~

57
58
59
6(1
61

.. INTERRUPT ROUTINE,
READS PRIORITY ENCODER TO DETERMINE
; INTERRUPT NEEDING SERVICE AND BRANCHES THERE.

62 (1F1C C:;::DB

I NTF.:PT:

63: OF1E (16
64 (1F:1F G::::[)6
65 (1F~~1 3::~:
66 0F:;~:;:~ (::::[:18
67 OF24 3:7

68

~)F25

c:::::[)7

69 OF2? ::a
70 &.3F2:::: C::=:[)3:
71 OF;;;: A 35
" .::, OF2B c::::cr
..,-,
-:..-,
" ..::. (1F;2D ..::..::.
74 OF;;::E C:::CB
75 OF3:~~1 3:6
76 OF3:1 C::::'::C:7
77 OF?:: ~):1
78 OF 3:4 (::::=(:2
79 0F:3:6 C40(1
80 ~)F3:::: 3:2
81 (1F39 C43:0
82 OF3:B 3:6
83 OF3:C C2(1(1
84 OF?E 3:";
~.-.

~

:::'T
CSA
5T

FICU

::-:;PfiI._

P~~:

ST
::,::PAH
ST
;:':;PAL
ST
;:,::PAH
ST
;:

25
.-.-,

REGISTERS A AND E (AND P1 IF USED) ARE NOT SAVED .
PEGISTER F'2 IS USED AS THE STACk POINTER .
PEGISTEP P3 15 THE SU8POUTINE CALL.ING PEGISTER.

.::..
.::..::.

.-,.-,

ALL OF THESE POUTINES MAY BE REPEATED WITHOUT
PELOADING P3 AFTEP THE FIRST CALL.
3:4

- - TABLE D-l. DOUBLE ADD (DADD), DOUBLE NEGATE (DNEG), AND DOUBLE SUBTRACT (DSUB) - 3:5

PAGE

~DADD..

=

~~1

DNEG,

DSUB~

10 ~~1 (1

36
- .. -:r

DADD: DOUBLE ADD
(OP]. . OP4)

~·I·

3:::::

=

(OP1 . 0P2)

+

(OP]"OP4)

39

4(1
41
42
4],
44
45
46
47
48
49

1 (n]13 0::::
HH31 (12
1 (n]2 C2~~11
1(n]4 F2(C
1(U~16 CA03:
10(1:?, C2(10
11313A F202
1 (n]C CA02
l(l13E C6~~12
113113 ]'F

[lADD

NOP
CC:L
LD
AD[:'
ST
L[:'
ADD
ST
LD
::·::PPC

1(2)

ADD LOW ORDER BYTE
(CARRY MAY BE SET)
SA',lE F.:ESUL T
ADD HIGH ORDER BYTES + CARRY

3:(2)
3:(2)
~~1(2)

2(2)
2(;;~)

FIX STACk POINTER

1]12(2)

3:

0-2

.•Tt, IF'
5:1
1:".-.
"-'.::::.

Cot·4EC,·

C'"'"':'

,-,,,:;.

[:'OUBLE t·jEGAl E (~::.'~:; C CII'"IF'lEI'1EtH)
(OP1.0P2) = - (OPi.OF2)

54
coco
,_f._'

56 1(11:::: 0::::
co...,
,• .1 I"

:1(114 (1::::

58 1(115

C4~)(1

59 1'3:1.7

FA~)1.

6~~1

61
62

63:
64

65

seL
LOI
CA[:,

SET CARRY IN
(1

1(:2)
:1(2)

:=:T

1(119 CAOl
1~31B (:40(1
1.01D FA~X1
1(11F CA~~1I~1
1(12:1 3:F
:1(122 9f1EF

L[:' I
CA[:'
ST
:'·':PPC
Jt"1 F'

NEGATE LOW BYTE

SET CARRY

COI'iPLH1EtH HIGH B'T'TE AND
ADD CAF.:P'T' I t·4

(1(2)
~].::;;::

&

::-

3:
[) t·4 E I~i

66
67
6::::

DSUB:

DOUBLE SUBTRACT
(OP3.0P4)
(OP3.0P4) -

=

6S'
70
71 11,)24 ~~1::::
'70"-:'
, 0<..
1(125 (C

73:

H~126

[:.sUB:

74 1(12:::: FAf11
... 1::.

CAD
ST
L[:'
CA[:'

H)2C C2(1;;::
FA~~1~~1

7::::

lf1"7;:~71

CA~];:::

~:;T

79

H~C2

C6~)2

L[:'
:'
<:NORI'IAL RETUI<:N>

STACK USAGE:
REL EN T1<: 'T'

USE

RETURN

TEI'IF'
COUNT
FC:EM(H)
FC:EI1( L)
DI VI SOl': ( H)
DIVISOR(L)

REt1AINDER

----------- ----------- -----------5
-4
-]

-2
-1
(F'2)-:>

0

DIVISOFC:

0-5

1'::'7
-' ,
19:3
199
2(U::'1
2(11 lOA::::
2(12 1(lA9
2~::'13: lf1AB
204 1(lAD
2f15 l(lAE
212:16 1(lE:~::'1
2f17 H::'182

:1

2
f1::::

DI'·. .

C2t;:)~)

9C(13:
3F
9(lF::::
CA~?19

l·[)l

Ct"1FC

2 a.] E:

1~::'184

C2~::'u)

2[19
2H)
211
212
213
;;::14
215
216
217
21::::
219
220
;;::2:1
222
223:
;;-:24
225
2;;::6

1[186

~)1

40
1~)B:::: 94(1;;-:
H::'18A 9fu::'f?
l~::'lBC f1;;::
H'IBD 7(1
108E ~::'11
HmF AAFC
':1~X:1 9'3F4

$:SET:

HX::: 4(1

$:SETUP

1~)87

NOF'
L[:'
JNZ
::'::PF'C
Jr'lP
LDI
ST
L[)
'::::AE
ILD
JI"iP

DIVIDEND(Hj QUOTIENT(H) QUOTIENT(H)
DIVIDEND(L) QUOTIENT(L) QUOTIENT(L)

0(2)

CHECK FOR ZERO DIVISOR
EF.: F.: OF.:

RETUF.:t,~

COUNT

9

DIV
-4(2)
1::.1(2)
NORMALIZE THE DIVISOR
+4

$SETUP
SHIFT LEFT 1 BIT

= COUNT

-4(2)
:$-5ET

COUNT

-1(2)
1(2)

SA'·... E [) I VI SOF.:

1f1C6 C201
1f1C::;: CAFD

LL'E
ST
L["
::::T

-3:(2)

1~::'lCA

l_[)

2(2)

COpy DIVIDEND TO
INITIAL REMAINDER

HXA CAFF

C2~::'12

1f1CC CAFE
:1. (lCE C4~::'K1
1(lD(1 CA~::'l(l
227 1(lD2 CA~::'l:1.
22E: 112:1D4 CAf12
229
2:?-0 1(lD6 03:
23:1 1 12:1[) 7 C2FE
;.?32 10[)9 FA(l(l
23::?- 1f1[)B ~:H
23A 10[)C C2FD
235 10L'E FAFF
23:6 112:1E12:1 CAFE:
23:7 1(lE2 (16
23::3 1 12:1E 3: E4:3(1
23:9 10E5 941E
240 10E7 BAFC
241 10E9 9:329
242 1~::'lEB (12
24:?- 1(lE(: C2~)2
244 1(lEE F202
245 10F0 CA02
246 H)F2 C201
247 10F4 F201
24:3 10F6 CA01
249 10F:::: 02
250 10F9 C2FF
251 1(lF8 1F

::::T
LDI
ST
:::'T
ST
$LOOP

SC:L
L[)
CAL'
::::F.: I
JP
DL[)
JZ
eeL
LD
ADD
ST
L[:'
ADD
5T
CCL
LD
F.: F.: L

INITIALIZE LOW BYTE OF DIVIS
AND RESULT TO ZERO

fi I.:;;::)

1(2)
;~(

+ :1

2)

SUBTF.:ACT :
REMAINDER-DIVISOR

-·2(;;::)
~~1 (2::'

-:3:(2:.1

-1(2)
SAVE TEMPORARILY
CHEO::: CAF.:F.:'T':

-5(2)
~1:3(1

JUMP IF RESULT >= 0
COUNT = COUNT - 1
CHECK IF DONE

:*' D'.... (j F.:
-4(2)
~DONE

I'm
DOUBLE LEFT SHIFT:
ADD QUOTIENT TO ITSELF

2(2)
2(2)

1(2)
1',:2)
1.(2)

SHIFT DIVISOR RIGHT 1 BIT

-1.(2)

0-6

'-,C"'-'
'::",_1.::.

10FC CAFF
2~: i.~jFE {2'0'~5'
254 11.f1f1 lF
255 lHH. CAf1tl
256 :1:10:::: 9~~1[:o:1

257
258

:1:1~)5 C;:?FE:
259 :1:1(17 CAFD
260 :1:1~)9 ~):1
26:1 :1:10A CAFE
262 :1:1f1C AAf1;;::
26? :1:1~)E 9CC6
264 :1:1:1~~1 F1A~~11
265 :1:1:12 9~X:;;-,
266
267 :1:114 C2FE
26B :1:1:16 CA~~n~1
269 :1:1 :1:::: C7~~12
270 :1:1:1ti 3:F
27:1 :1:1:18 ::;'0::::8

ST

--1 (2)

CO

ao::2,

pr::L.
~;T

..H'W
$:[:0 ',/GF.:

$[:,Ot·JE

LE:'
ST
::::TENSIO

~)

F'F.: C;-:::O
PF.:+1 (2)
PR+;;::O::;;::)
PR+]:(;2)
PF.:+4 0:: 2)
PF.:+SO::;;:: )
1'11'.:2)
t'l:1 +:1 0::;;::)
t'1:1 +;;:: (2)
6
cour·n(2)
1'12+2(2)
~3F

NE::-::T[:'
l'E:(2)

DIGIT COUNT
;

=6

LOA[) l'1UL T I PL I EF.:
USE Lmo.lEST E:CD [:'IGIT
IF ZEF.:O THEN GO TO NEXT DIGI
ADD 1'1UL T I PL I CAND TO PF.:ODUCT

t'11+5(2)
PR+5(2)
PF.:+5( 2)
1'1:1+4(2)
PR+4(2)
PF.:+4 (2::0
1'1:1 +:3: (2::0
PF.:+:3:( 2)
PF.:+:3: 0:: 2)
111+2(2)
PF.:+2(2)
PF.:+2(;;::)
t11+1(2)
PI<:+1(2)
PR+l(2)
t11(2)
PR(2)
PR(2)
113(2)
$Ll
COUNT(2)
$OUT

0·8

DECF.:Et'1ENT t1UL TIPLIER
AND ADD AGAIN iF NOT ZERO
DECF.:EI1ENT DIGIT COUNT
I~UIT IF DONE

357
3:58
]:59

::6(1
::61
3:62

:?,6::
3:64
365
3:66
3:67
3:6:=:

369
370
3:71
372
373
374
375

376
377
37:::
379

380
3:81
382
383
384
385
386
387

388
389
39~)

::::~91

3:92
393
394
3:95

3:96
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411

1174 C4~)4
:1.176 CAF6
117:::: (12
1.179 C2(1~::
:U.7E: F2((J:
117[:' CA~jJ
11?F C2(1:::~
11:=.:::1 F2(12
1:1.::::3: CA~)2
:1.1::::5 C2(11
1187 F2~31
1189 CA01
11::::B C2(1(1
118D F2~}(1
118F CA(1(1
1191 C2FF
1193: F2FF
1195 CAFF
1197 C2FE
1199 F2FE
119B CAFE
119D BAF6
119F 9CD7
llAl C2FD
llA3 D401
llA5 980A
11A7 C207'
l1A9 lC
llAA lC
l1AB lC
llAC lC
llA[:' CA~)7
llAF 908E
1181 C2~)6
11K? CA(17
1185 C2(15
1187 CA06
l1B9 C207
1188 9[182
118[:' C2(14
118F CA01
llCl C2F7
llC3 CA02
llC5 C2F8
llC7 CA03
llC9 C2F9
llC8 CA04
llCD C2FA
llCF CA05
llDl C2FB
1103 CA06
llD5 C2FC
llD7 CAe7
llD9 3F
11DA C411

:tL:2 :

L[d
::::T
eeL

4
TEI'IPr:'2;.

LD

1'11+5(~:·

A[:,[;.
5T
LD
ADD
5T
LO

1'1:1 +'=.:; 0:: 2
1'11+·::;" ~:
l'U+4 ;2
"1:1+4 .;::
1'11+4 2
.-,
1'11+3: .::.
..
1'11+:3. ~:)
1'1i + 3: ;;:~ ::1'11+2 .2)
1'11+2(2)
1'11+2(2)

A[:'D

sT
L(:o
A[:0[:0
ST
L[:o
AO[:'
sT
LD
A[:0 [:'
sT
L'LL'
JNZ
LD
ANI
"-T7
'-

$L3::

tOUT:

LD
SF!:
SR
sR
SF.:
ST
.JI'1P
LD
sT
LD
ST
LD
Jt'1P
LD
ST
LD
ST
LD
ST
LD
ST
U)
ST
LD
ST
LD
ST
XPPC
LDI

SHIFT l'lUL T I PL I C:At-m LEFT
4 BITS (1 DIGIT)

111+1(;;:~)

I'll +1 O::~:)
I'll +1 (;;:~::o
1'11(2)
I'll 0::;;-:::0
1'11(;;: )
TEI'1P(2)
$L2
COUt-H 0:: 2)
1
$L]:
112+2(2)

OTHERloJISE SHIFT LOloJ loJOF.:D F.:IG

1·'12+2(2)
;f:LOOP
1'12+1(2)
112+2(2)
"12(2)
1'12+1(2)
112+2(2)
$LOOP
4(2)

COP'y' SIGN TO OUTPUT

GET NE:>::T NULTIPLIER [:'IGIT
IF COUNT IS EVEN THEN USE NE

1(;;-~)

PR(2)
2(2)
PR+l(2)
3:(2)
PR+2(2)
4(2)
PR+3(2)
5(2)
PR+4(2)
6(2)
PR+5(2)
7(2)
3
H(BCDMPY)

0-9

;

RETURN
JUMP TO BCDt1PY

4i;;-,
4i3:
4i4
4i5
4i6
417

iiDC
i"1DD
110F
:l.:l.E(1

;:
·.:NOF.:I'lAL F.:ETUF.:t·J>

STACK USAGE.
REL ENTF.:'T'
(1
1.
2
3:
4
5

00C1i
1!;1005

$OP1
$OP2

OP1(SIGt'J)
OP1(i::O
OP1(2:.'
OP1(3:)
OP2 (:::; I GN)
OP20::1)

6

OF'2(2)

7

OP2(J:)

OP1(SIGN)
OP1(!)
OP1(2)
OP1 (3:)
F.:ESUL T(SIGN)
F.:ESUL TO:: 1 )
F.:ESUL TO:: 2)
RESUL T(J:)
F I F.:ST OPEF.:AND
SECOND OPEF.:At~D

=
5

8CDSU8:
llE2
llE4
llE6
liE8
llEA
llEC
1.1.EE
llF0
llF2

C201
9C08

LD
.JNZ
L[)
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LD

C2~32

9CI!;14
C203
9827
C200
E401
01

..1""
.:;..

$8SU8:

LD
XF.: I

$OP1(2)
$8SU8
$OP1+1(2)
$8SU8
$OP1+2(2)
$OUT
:t:OP1-l 0:: 2)
1211

>~AE

D-10

.' CHECK FOF.: ZERO OP1.
" NOT ZEF.:O.
. CHECK FOR ZEF.:O OP1.
.' NOT ZEF~O.
.' CHECK FOR ZERO OP1.
.' OPl IS 2EF.:O RETURN.
CHANGE SIGN OF SUBTRAHEND
THEN DO ADDITION

462
463
464
465
466
467
468
469
470
471
472
473
474
475
476

llF3
llF5
llF7
llF8
llFA
llFB
llFO
llFE
1200
1202
1204
1206
12£18
1.20A
1.20C

91103
C20l1
01
C204

477

1.2~)E

CA~)5

47::: 1.21.0
479 1.21.1.
48~~1 1.21.:3:
481. 1.21.5
482 1.21.7
483
484
4::::5
486 1.21.::::
487 1.21.A
4E:8 1.21.C
489
490
491.
492
49:3:
494
495
496 1.21.E
497 1.2:1F
498 1.22:1
499 1.22:3:
50(1 1225
5~)1 1227
5~)2 1;;-:29
5(13 1.228
504 1.22D
5"~15 1.22F
5£16 :l2:3:1.
5"~17 1.23::3:
5"~18
5&'~19
51.~~1

51.:1
5L2
51.::
514
51.5
":~t6

JMF'
LD
:X:AE

$CHK
$OF'1-1(2)

$CHK:

L[)

$OF'2-1(2)

6~)

9C21
1212
C20:::;
EA07
CA07
C202
EA06
CA06
C2€11.
EA€15

SAt'lE

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D4:=:~~1

9(:02
C7&.32
J:F

$OUT
$O'·lFL

XRE
JNZ
CCL
LO
DAD
ST
LD
DA[:,
ST
LD
DAD
ST
C:::'A
ANI
JNZ
L[:o
::-:;PF'C

Cot'lF'ARE SIGNS

;f:[:o I FF

OIFFEF~ENT

$OF'1+2(2)
$OF'2+2(2)
$·OP2+20::2)
i:OF':1.+1'.: 2)
;f:OF'2+10:: 2)
;f:OF';;::+1 (2 : 0
$OF':1(2::O
$OP2(2::O
$OP2(2::O

1'-'
=. THEF.:E AN EN[:' CARF.:'T'?

£18~)

'T'ES -- OVEF.:FLO~·l
I tK:F.:HIENT F'3 B'T' 2 FOF.: NOF.:t'lAL
F.:ETUF.:N

:t·OVFL
I]I;'~

( 3~

-

JUt'lF'
SIGNS
SAt'lE SIGNS ADD MAGNITUDES

)

3:

OP2Z
(:401.
CA(14

LDI
ST
.Jt1P

9~)[:oF

i
$:OF'2-1. (2::0
:;At'lE

• SET OF'2 SIGN NEG .

..

L[:'E

98~~12

r-'

(:4(1:1.
CA(14

LDI
ST
L[:'

$;~:

C2J.~15

.ne

9C(1:::::
(:2(16
9C(14

L[:O

C2~17

9::::E7
C6~:::15

m:::

.JNZ
L[:'
JZ
L[:O
L[:oI
::<:F'f=tH
LX'I
::CI'IF'::O
J.

::=+7D
1.2::::: ::1
12:3:9 ~);;-:
L~:J:A 3·[:,
1;;:::3:E: C6FE:
:12:3:[:0 (12
1.2:3:E c;;::~)=:
12*) EA~:::17
1.2~:5

BCDADD:

;:f:OF':1 +;2'.:;;':::0
:$OF';::+,~: 0:: ;;;:::0

0·11

S l(lr·~ FLAG IS IN SIGN.
CHEU:::
IF OF'2 IS ZEF.:O.
.'
• t·40 .

.'

UF'2 I:::; ZEF.:O.
SET F'2 TO F'OINT TO 0F'2
COI'lPLEI'lEt'~T OP2

F.:E:=:'TOF.:E F'2
Al.o[.o j'IAGNI fU["ES

~51.7 LeA 2 Cfi~3-;'
51.:=: 1244 1::2(1:;::
519 1246 Efi06
52~Z1 124:::: Cfn) 6
521 124A C2f:11
522 124(: EA(15
523: 124E CAOS
S2:4 125f) ~36
c::"-'C'
._I.:::. .. j25:1 [:'4::::(1
526 1.253: 9C1~3
5;;:~7 1255 C605
.:::..._1 ( (:412
528 1'-'<=:""
..::,
'- ~-' 1259 3:5
53:~:::1 125A (:47[:0
5:a 125C 31
C'''''':''-'
._1"'::.'::' :1;;":5[:0 (12
53::: :125E 3:[:0
53:4 125F C6FE:
53:5 1261 C401
53:6 1263: 9~3(12
53:7 1265 C4~:::1~:1
538 1267 E2~:::14
539 :1269 CA~34
540 126B C205
541 126D 9CA6
542 126F C206
543: 1271 9CA2
544 127:: C207
545 1275 9C9E
546 :1277 C4(1~:::1
547 1279 CA(14
548 127B 9~398
549
55121
551

:":T
L[:O
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:

:* OF' ;~: -+- :,:
l·OP!-+-:)

;~:: :0
;.~:

t·OF'2~·1 ' _.
.-

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$C'P2+::l.O: .::: ..
:H)P:1.':2:"

[:oA[:o
:;T

:tOF'2':'2)

ST

,
,
,

l·OP20::~-:)

IS THEF.:E AN END CAF.:F.:Y?

CSA

ANI
.Jt·C

~I

LD
LDI
:"':F'AH
Lf"'I
:: 13
1.

2

DIVISOR(S)
DIVISOR(1)
DIVISOR(2)

0-13

P3:(L:.o SA"","E
(II-'OT I EtH ( :=; I Gt~)
OUOTIENT(1)
QUOTIENT(2)
OUOTIENT(l)
DIVISOR(SIGN)
DIVISOR(l)
DIVI50R(2)

...,.

617
618
619

DI'y'I501<:(J:)
D I 'y' I [lEND (5)
[) I V I [:'EN[:' 0:: 1 )
[:0 I './ IDEND (2)
D I V I [:'Et·m (J:)

~.

(P2, E::

4

5

620
621

6

7

D I V I 501<: (J:)
DI'y'IDEND(5)
D I V I DEt.,j[) 0:: 1)
[:, I V I [)END ( 2)
D I V I DEND (J: ::0

(J.UOTIENT(5)
QUOTIEtH(1)
QUOTIENT(2)
I)UOT lENT ( 3)

~.-,.-.

0'::'::'

626

FFF:3
FFF9
FFFA
FFF[I

627

f10~31

628

fnX15

$TH1F'
$CtH
$PJ:
$0
$D1
$D2

~~18

BC[:'[:O I '...':

623:

624
625

-:=:

=
=
=
=

-7
-6
-3:
1

(~UOTIEtH

t::'
._'

D I V I :=.OF.:
DIVIDEND (QUOTIENT UPON PETU

$[d. (2)

CHECK FOP ZEPO DIVI50P

629
63:~~1

12A6

:l(::1
$[:'1+;;::(;2)
:lC:1

CAFA

t·mp
LE'
.Jt·c
lE'
.JNZ
lE'
JNZ
;:-::F'fiH
ST

3:~:

::·:;PAL

...::.

CAFE:
C401
CAF9

ST

:t-F'3.+:1 (;;::)

L[:oI

1

ST
LT.'

:!:Ct·n (2)
(1( 2)

>:;OP

4(2)

ST

--4(~2)

LD

iD1 0:: 2)

63:1 12A7

C2~31

632 12A9

9C)~lB

63:3: 12AE:

C2~~12

634 :12AD 9CI:'::17
63:5 12AF
636 12E:1
637 12EG
12E:4
12E:E.
641:'::1 12E:7
641 12B9
642 12BA
643: 12BC
644 12BE
645 12C(1
646 :12C2
647 12C4
64::::: 12C6
649 12[:::::
65"~1

1:;~C:A

651 :12CC
652 12CE
653: :1.2D~:::1
654 :12D:1
655 12D3:
656 12['5
657 :12[:07
65:::: :12[:09
659 12DE:
66~)

661
662
664

665
666
66':::::
669
670

671

C21:'::C
9C(13:
JF
9(lF~3

3:7

:lei:

C2~3(1

E;2(14
CAFC
C2(11
D4F(1
9(::1F

$SET:

CAF:::::
(12
(:2(C

:*,SL1 :

F2~~C

EF.:POP SA'·... E PJ:
~.p3·'.:

2)

~3FO

lSETUP
4

ST
eCl
L[:'
AD[:'

.; GET S l(:.t·~.
; CHECK I F THE SAI·lE.
; SA ...·'E S IClt·l.
t·WF.:I·IAL_ I ZE THE [:, I '.... I SOP
CHECK FOP ZEPO HIGH DIGIT
tmT 2EPO - t·WPI·lAl I ZAT ION

$['1 +;;,0::';::"
$ [d + :::: '.: 2.'
:$:[:o'J.. +20::;;-::.'

SHIFT ~IVISOR lEFT 1 81T
0:: [:'m'lE 4 T I t'IES •.'

:'1:[.01.+:].. (;~-::'
:H):l +:1 '. ::c: :::¥ rft +1. '.' ,~: '.'

L['
A[:'l'

CA~:::l;;-~

ST

C20:1.
l.:2E'F· F--201
:1;;::E:1. Ct="i~~l:1
1:2E3: E:AF:::::
1.2E':i 9CES'
~12E7 AAF:9
:12E9 90DE:
12EE: C4(1('1
12EE. CAF[:'
12EF CAFE
12F:l CAFF
12F::: Cti~::10

L[:o

:$.[.oJ ,.:,' .'

::::T

::H' J. (' :: "
l [.01. 0:: ::: "

:f·::;ETI..IP

COUtH = :1

lTEI'iP(;;-,,

F;2~)2

1;;-~[:O[:o

PETUF.:t·l

E: C:[:O [:, I '. •'

JtE

:;T

CA(l::
C2(:":I2

$:[.01+1(2)

titl I
lDI

CA~)4

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[:'LD
JNZ
IL['
Tt·W
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~j;: T E t·1F' .. ;~:.'
$·SLJ.
:lUH' .:::'
J::::;E-r

:;r

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';T
:::;T

:l1~'+j' ;,:'
:$0+';, ': .:: ':0

::=. r

0"';;:: : -

COUNT :::: COUNT + 1
I)UClT I Et·n :::: 0

0-14

4(2)
;fSUB

672 1.;2F5 CA(14
673: :1;;::F7 9(n~12
674

5T
Jt'lP

675

:("j:

INCREMENT QUOTIENT - ILD MAY BE USED SINCE THERE
WILL NEVER BE A CARRY FROM 1 OIGIT TO THE NEXT
I Le.'
:$:0+:;:: '.:;;:::::0
I t~('F.:EI'IEt-n C!.UOT I Et·n 0:: E:C[:'::O
LOI
H(BC~SUB::O
CALL BCDSUB
XPAH
3
TO DO SUBTRACTION
LOI
L(BCD5UB)-i
(DIVIDEND-DIVISOR)
;:-:;F'fIH
L. [:, I
;:'::F'AI...

:3:F

>::pp(:

677 :12F9 AAFF
678 12FB C411
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