60207900B_1700_Programming_Training_Feb70 60207900B 1700 Programming Training Feb70
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1
)
PROGRAMMING
TRAINING
MANUAL
INSTRUCTION INDEX
INSTRUCTIONS (by class)
Hex
Code
Mnemonic
Section
Number
Hex
Code
Mnemonic
AXXX
BXXX
CXXX
DXXX
EXXX
FXXX
JMP
MUI
DVI
STQ
RTJ
STA
SPA
ADD
SUB
AND
EOR
LDA
RAO
LDQ
ADQ
5.1. 2.4
5.1.2.2
5.1. 2. 2
5.1. 2.1
5.1.2.4
5.1. 2.1
5.1. 2.1
5.1. 2. 2
5.1. 2. 2
5.1. 2. 3
5.1. 2. 3
5.1. 2.1
5.1.2.5
5.1. 2.1
5.1. 2.2
Skip
010X
011X
012X
013X
014X
015X
016X
017X
018X
019X
01AX
01BX
01CX
01DX
01EX
01FX
SAZ
SAN
SAP
SAM
SQZ
SQN
SQP
SQM
SWS
SWN
SOY
SNO
SPE
SNP
SPF
SNF
PSEUDO OPS (by mnemonic)
Page
Section
Mnemonic
Number
Number
.,...-r'
,.--,
"'--"'"
Shifts**
Storage
1XXX
2XXX
3XXX
4XXX
5XXX
6XXX
7 XXX
8XXX
9XXX
Section
Number
5.2.1
5.2.1
5.2.1
5.2.1
5.2.1
5.2.1
5.2.1
5.2.1
5.2.2
5.2.2
5.2.3
5.2.3
5.2.4
5.2.4
5.2.4
5.2.4
QRS
LRS
ARS
QLS
ALS
LLS
OF2X
OF6X
OF4X
oFAX
OFCX
OFEX
5.3
5.3
5.3
5.3
5.3
5.3
Interregister
0808*
081X
0818*
082X
0828*
083X
0838*
084X
0848*
085X
0858*
086X
0868*
087X
0878*
08A8*
08BX
08D8*
08E8*
08FX
08F8*
TRM
TRQ
TRB
TRA
AAM
AAQ
AAB
CLR
TCM
TCQ
TCB
TCA
EAM
EAQ
EAB
LAM
LAQ
LAB
CAM
CAQ
CAB
5.4
5.4
5.4
5.4
5.4
5.4
5.4
5.4
5.4
5.4
5.4
5.4
5.4
5.4
5.4
5.4
5.4
5.4
5.4
5.4
5.4
Register Reference
OOXX
02XX
03XX
04XX
05XX
06XX
07XX
09XX
OAXX
OBXX
OCXX
ODXX
OEXX
SLS
INP
OUT
EIN
lIN
SPB
CPB
INA
ENA
NOP
ENQ
INQ
EXI
5.5.5
5.5.4
5.5.4
5.5.3
5.5.3
5.5.2
5.5.2
5.5.1
5.5.1
5.5.5
5.5.1
5.5.1
5.5.3
*Right most Hex number will include destination register.
**Third Hex number will include uppermost bit of shift count (bit 4).
ADC
ADC*
ALF
BSS
BZS
COM
DAT
DEC
ElF
EJT
EMC
END
ENT
EQU
EXT
EXT*
IFA
IFC
LOC
LST
MAC
MON
NAM
NLS
NUM
OPT
ORG
ORG*
SPC
VFD
6.7
6.8
6.9
6.12
6.12
6.13
6.13
6.10
6.15
6.20
6.16
6.2
6.3
6.5
6.3
6.6
6.15
6.18
6.17
6.19
6.16
6.22
6.1
6.19
6.6
6.21
6.14
6.14
6.19
6.11
6-9
6-10
6-11
6-15
6-15
6-16
6-16
6~13
6-21
6-27
6-23
6-4
6-4
6-7
6-4
6-6
6-21
6-25
6-24
6-27
6-23
6-29
6-3
6-27
6-9
6-28
6-19
6-19
6-27
6-13
-_.-
)
l
'-./
.J
1700 PROGRAMMING TRAINING MANUAL
TIDRD EDITION
I
'-_ .J
FOR TRAINING PURPOSES ONLY
This manual was compiled and written by
instructional personnel of
CONTROL DATA INSTITUTE FOR ADVANCED
TECHNOLOGY
CONTROL DATA CORPORATION
,,~-
.......
/
Publication Number 60207900B
February, 1970
The original draft of this manual was compiled and
written by the Southern Region Training Staff. Technical revisions which have been incorporated in this
printing were submitted by the Southern, Southeastern
and Eastern Region Training Staffs.
Physical composition was accomplished by the Graphic
Services Department within Control Data Educational
Institutes. Since this department has continuation responsibilities for the originals of this manual, additional corrections, revisions, or suggestions should
be submitted to the Manager of Graphic Services for
processing.
\.
Copyright 1970, Control Data Corporation
Printed in the United States of America
TABLE OF CONTENTS
PART I
1700 BASIC SYSTEM DESCRIPTION
1700 ARITHMETIC
ASSEMBLY SOURCE FORMAT
BASIC 1700 INSTRUCTION FAMILIARIZATION
1700 MACHINE INSTRUCTIONS
PSEUDO OPS
INTRODUCTION TO MACHINE LANGUAGE I/O
r
SYSTEM REQUESTS
,)
.,
MSOS USE
\'
...~
('--
'J
',-,
\
I
PART II
CONFIGURING A SYSTEM
ADVANCED CODING TECHNIQUES
PERIPHERAL PROGRAMMING - I (NON-INTERRUPT MODE)
PERIPHERAL PROGRAMMING - II (INTERRUPT MODE)
LIBEDT EXAMPLES
APPENDIXES
INDEX
~I
..
INDEX TO FIGURES
Page
Description
1
2
3
4
5
6
7
8
9
r'~
,
L..../
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
1700 Computer System Characteristics
1700 Interrupt Trap Area .
Basic System Description •
Typical Configuration •
Console.
Numbers
1700 Integer Numbers .
Range of Numbers Used in the 1700.
Floating Point Example.
Processing the Assembly Language Program
Sample Assembly Listing .
Address Modes for Storage Reference Class Instructions
Data, Program and Common Counters.
Side and Top Views of 850 Disk Pack .
Flow of Requests •
Macro Calls for Requests Available to Background Programs .
Control Statements Available Under the Job Processor •
Control Statements Available to the Breakpoint Package.
Control Statements Available to the System Recovery Package.
1700 Computer System Block Diagram.
1700 Hardware Configuration .
1700 (1704 or 1774) Communications System Configuration.
Mass Memory Core Maps •
Object Tape
Flow of Program Through Execution
Error Examples for Incorrect Addressing in Mass Memory
Programs •
Maps of Mass Memory Modules and Core Subroutines
1700 Core Map (Externals)
Disk.
Sector Format on Disk •
Data Buffer for Disk.
Interim Drum Interface Codes
1731 Functions.
1700 Interrupt Hardware and Software Functions
Interrupt Flow.
v
1-1
1-4
1-7
1-10
1-11
2-1
2-4
2-5
2-9
3-1
3-7
5-2
6-12
7-12
8-4
8-6
9-2
9-19
9-25
10...,7
· 10-10
• 10-12
11-2
11-5
• 11-11
·
•
·
•
•
•
•
•
11-22
11-45
11-51
12-37
12-38
12-39
12-49
12-59
13-2
• 13-10
INDEX TO PROBLEMS*
L
I~
C·,.:,'-
PROBLEM
PAGE
Addressing
5-14
MOVE
5-28
SUM
5-28
CHNG
5-28
SUB
5-35
SORT
5-37
CLRPB
5-40
CONVRT
5-43
VALUE
6-16
INI
6-19
CKASSM
8-59
Runanywhere
11-23
REENTRANT
11-31
THREAD
11-38
MMPGM
11-47
*Note that solutions to problems appear in Appendix G.
r "\
\.~
...
~.
~.
vii
PART I
.'
II
CHAPTER I
1700 BASIC SYSTEM DESCRIPTION
CHAPTER I - 1700 Basic System Description
~."
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('
TOPIC
PAGE
Introduction
1-1
1.1
Memory
1-1
1.2
Protect System
1-2
1.3
Interrupt System
1-3
1.4
Input/ Output
1-6
1.5
Basic System Description
1-6
1.5.1
Registers
1-6
1.6
Typical Configuration
1-10
1.7
Console Description
1-12
1.1
INTRODUCTION
C...}
The CONTROL DATA® 1704 Computer is a stored program, digital computer. Physically
small, it is designed for high computation and input/output (I/O) s pee d. The program protection features of the 1704 Computer and high reliability under a wide range of environmental
conditions make it suitable for real-time, on-line, or control applications.
The interface of the 1700 Computer System is capable of accepting a greatvariety of peripheral
devices. Refer to Figure 1 for system characteristics.
Figure 1. 1700 Computer System Characteristics
Stored program, digital computer
Completely solid - state, 6000-type logic
Parallel modes of operation
IS- bit storage word
16 data bits
1 parity bit
1 program protect bit
Reliability (calculated):
Approximately S,OOO h 0 u r s
mean time between failures for
the 1704 Computer
Environment:
40° F to 1200 F
Relative humidity 0% to SO%
Cooling: Forced Air
16-bit instruction word
System Interrupt
Two 16-bit index registers
Multilevel indirect addressing
Magnetic core storage (options available):
4096 IS-bit w 0 r d s, expandable to
32,76S words
Input/ Output (options available):
Transmission of 16-bit words or S-bit
characters
Console includes: Register contents displayed in binary; operating switches
and indicators
Flexible repertoire of instructions:
Arithmetic operations
Logical and masking 0 per ations
Interregister transfers
Base 16 (hexadecimal) number system
Binary arithmetic:
Modulus 2 - 1 (one's complement)
Intercomputer communications:
1700 to 1700
Satellite operations
1.1 MEMORY
The basic 1700 Computer System provides high- speed, random-access mag net i c core
storage for 4,096 IS-bit w 0 r d s. The storage capacity may be expanded from 4K by 4K
increments to 32K as a maximum. With the addition of special hardware, memory may
be doubled from 32K to 64K.
® Registered trademark of Control Data Corporation
1-1
1.1
storage c y c I e time is 1. 1 microseconds. This is defined as the shortest possible time
between successive Read/Write operations in storage.
A storage word may be a 16-bit instruction, a 16-bit 0 per and or a 16-bit addres s. A
parity bit and a program protect bit are a p pen de d to each 16-bit storage word; thus a
storage word is 18 bits long. Format:
17
16
15
t
tparity Bit
Program Protect Bit
Bit
o
l16-Bit Data or Instruction Word
Bit 16 is the parity bit. It takes on a value so that the total number of 1 bits is odd (total
number of bits includes the program protect bit). For example, if all 16 data bits are 1 's
and the program protect bit is 0, the parity bit is a 1.
Bit 17 is the program protect bit. If it is a one, the word is protected and can only be
modified or changed by a protected instruction.
1.2 PROTECT SYSTEM
The program protect system in the 1700 makes it possible to protect a program in the
computer from any other non-protected program also in the computer. The combination
of the high internal memory speed and the program protect s y s t e m makes possible the
use of the 1700 for background and foreground work. Foreground programs are protected
and are generally multi-level (level 2 to 15) process programs. The foreground job is
protected in core and runs at higher priority than background jobs which are assemblies,
compilations, programs being debugged, etc. The background programs use the time
available and are run in unprotected core. The protect system is enabled by setting the
program protect switch on the programmer's panel. Any attempt to violate in any manner
the protected portion of core from an unprotected instruction will cause a program protect violation which sets an in t err up t on line 0 and also the program protect indicator
which is visible as one of the fault lines on the programmer's panel. There are four program protect violations. They are:
1. An attempt is made by a non-protected instruction to write into a storage location
containing a protected instruction or operand. It is legal to read from a protected
area.
2. An a t t em p t is made to write into a protected storage location by way of the external storage access when a non-protected instruction was the ultimate source of
the attempt.
3. An attempt is made to execute a protected instruction following the execution of a
non-protected instruction.
.1-2
1.2
.' '"
~
u
4. An attempt is made to execute interregister class instructions with bit 0 a one (M
register is the destiriation); instructions EIN, IIN, EXI, SPB, or CPB. Later examination of these instructions will show how these are used to change the state of
interrupts or the protected core area itself.
1.3 INTERRUPT SYSTEM
The basic computer (1704) provides two interrupt lines. Line 0 provides entry for interrupts generated as a result of a storage parity error, a program protect fault, or power
failure. There are instructions available for the processing program to check for parity
error or protect fault, and power failure can be assumed if one of the other two conditions
does not exist. In the case of power failure, approximately 8 milliseconds of programming time are available; then the computer generates a mas t e r clear before the power
actually goes down. Special hardware is a v a i I a b I e' which can generate an automatic
restart after the power comes back up.
Line Iprovides for interrupts from the low-speed peripherals controlled by Equipment #1,
the slow channel synchronizer. Any of the four stations (TTY, Card Reader, Paper Tape
Reader, Paper Tape Punch) on the slow channel synchronizer sends its interrupt to line 1.
The 1705 provides expansion from two interrupt lines to 16 interrupt lines, to pro v ide
for additional equipment.
o
Interrupts are controlled by an interrupt mask register (M Register, 16 bits) which either
allows selected interrupts in or blocks them out. Each line corresponds to its bit in the
M Register. If the bit is a 0, any interrupt on that line is blocked out and must wait; if
the bit is a 1, the interrupt is allowed in. The mask in the M register is set and changed
under pro g ram control. Priority is established by the mask in the M register, not by
the line position. In the case of concurrent interrupts on more than one line at the same
priority, the lowest numbered line is recognized first.
There is a fixed group of core 10 cat ion s assigned to the interrupt system, locations
$100-$13F, called the Interrupt Trap area. Four core locations are ~eserved for each
line, beginning at $100 for line 0; each 4-'word block is called the "trap" for that line.
n
1-3
1.3
.... '''- ...
Figure 2. 1700
13F
13E
13D
t----------4
Interrupt Trap Area
1
LINE 15 TRAP
13C
....
r"
".
107
106
105
104
103
102
101
100
1
1
LINE 1 TRAP
I
LINE 0 TRAP
I
Contents of Trap:
word
word
word
word
3 - address of interrupt processor
2 - priority level for line
1- R TJ to interrupt handler
0 - overflow and P
If the interrupt system is enabled and an in t err up t occurs on a line that has a corresponding 1 in the M register, the hardware does the following:
1. disables the interrupt system (locks out all interrupts),
2. saves the contents of the Pre g i s t e r (the address of the next instruction which
would have been executed in the interrupted program) in the first word of the trap
for that line,
3. saves the state of the
same word,
0
v e r flow indicator (1 if set, 0 if not set) in bit 15 of that
4. transfers control to the second word in the trap.
The above is all that the hardware does in handling an interrupt; anything else must be
done by the software. Under most systems, the second word of the trap for each line is
initialized by the software to contain a jump out of the t rap to a routine (or routines) to
save the registers of the interrupted program and handle the interrupt. The third and
fourth words of each trap can be used by the so f twa r e to contain anything desired; the
standard operating system uses these words to hold the priority level of the line and the
address of the processing program for the line, respectively. The interrupt processing
routine may exit interrupt state (back to the interrupted program) through word 0 of the
corresponding trap.
Example:
Assume line 1 has high priority, line 3 has lower priority. Line 0 always has highest
priority. Any other running program has lower priority than either line 0, 1, or 3.
1-4
1.3
u
Make a table containing M register masks to be used while the routine servicing each
line is running:
bit ----.
o
15
MASKM
o 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1
mask for main program
MASK3
o 0 0 0 0 0 000 0 0 000 1 1
mask for line 3
MASK1
o 0 000 0 0 0 0 0 0 0 000 1
mask for line 1
MASKO
o 000 0 0 0 0 0 0 0 000 0 0
mask for line 0
Note that MASKM will allow all pertinent lines to interrupt; MASK3 will allow line 1 or
line 0 to interrupt; MASK1 will allow only line 0 to interrupt; MASKO will not allow any
line to interrupt.
The processing programs would be set up as follows:
Main Program
Set M register to MASKM
Enable interrupt system
Enl
Interrupt Processor for Line 3
Store A, Q, I, M registers
Set M register to MASK3
Enable interrupt system
Inhitt interrupts
Restore registers
Exit interrupt state 03
Interrupt Processor for Line 1
Store A, Q, I, M registers
Set M register to MASK!
Enable interrupt system
Inhibi3 interrupts
Restore registers
[)
\ ....
Exit interrupt state 01
,
1-5
1.3
Interrupt Processor for Line 0
Store A, ~Q' I, M registers {
Exit interrupt state 00
J
could just leave interrupts locked
out during execution as shown here
rat her than set new mask (mask
would be MASKO if set and interrupts enabled)
\, _____
i
Chapter 4 of the Computer Reference Manual contains more details abo u t the Interrupt
System.
1.4 INPUT/OUTPUT
Included with the 1704 is a slow channel synchronizer. This channel handles any or all
of the slow speed devices normally affixed to a 1704. These are the 1713 Teletype, the
1729 Card Reader, the 1721 Paper Tape Reader, and the 1723 Paper Tape Punch. * Figure 2 shows a data pack extending from these slow speed devices through the slow channel
synchronizer to both the A and Q registers. T ran s fer of information to these devices
then is one word at a time (unbuffered) with the Q register containing address information
and the A register containing data. The addition of a 1705 to the 1704 extends the A/Q
unbuffered channel to eight more equipments. The 1705 also provides the addition of a
direct access bus (DAC) to core. This provides buffered transfer of data directly to or
from memory, bypassing the registers in the computer and, in fact, bypassingthe normal
compute channel of the computer. This direct access allows high speed transfer of data
from peripheral devices like discs, drums, mag tapes, or high speed industrial equipment like multiplexers, etc.
1.5 BASIC SYSTEM DESCRIPTION
Figure 2 ill us t rat e s the basic structure of the 1704 and also extension to peripherals
through the addition of a 1705. The basic 1704 is supplied with 4K (4096 words) of core
storage. Core can be expanded in 4K increments to a maximum of 32K (or to 64K with
the addition of special hardware).
1. 5. 1 Registers
There are four registers that the programmer can get to directly from instructions. These registers are the A, Q, I, and M registers.
The A Register is the principal arithmetic register. It contains 16 bits (labeled
bit-O up to bit-15) of which bit-15 is the sign bit for arithmetic operations. The
A register is also the register used to interface data d uri n g input/output operations to peripheral equipment.
*Also the variations of these (1711, 1713,11722, 1724).
1-6
"
.. _-"",'
1.5.1
Figure 3.
\
I
...--------......, DACDirect
Core
Access
Line 0 Interrupt
Storage
4 K Basic
Parity & Program Protect
Expand
To 32K
1704
U
Basic System Description
1705
,
14
Z
F
(8 Bits)
L...
(18 Bits)
S
(15 Bits)
t
f
X
(16 Bits)
---.
,
- - - -...1705
P
(15 Bits)
..-.
14
Inter
rupt
I~V
Line~
..---
Y
(16 Bits)
~
16 Interrupt Lines
+1
..
M
-.
(16 Bits)
II
, 1'~
.~ 1 t
~
~_____JAddend
Q
Augend·l
Gates
Gates
A
(16 Bits)
(16 Bits)
~
-+--l
e
Adder
(16 Bits)
LogicaL...
Difference
~
C,)
:s
1-i
Shif~--..
C,)
I JP.ft
oS~~--r-~~~~~
~ogical
• ..
Shifter
Product
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C,)
or-!
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1705
~
r.iI
00
0
E-t
--
~--------------!t-----+__
I A/Q Channel - I/O
(Part of 1704)
I
I
I
I
I
11711- TTY
11729 - CR
~
"Rig-ht
-"'-1
-=- -
'-Slow channeiSynchronizer
Equip #1
S
Shift
~---~
H
rn
-+--l
Note:
1
1721- PTRf
I 1723-PTP
1-7
The I register is memory
location $FF.
1.5.1
The Q Register is a multi-use register.
Its uses include:
a. Auxiliary arithmetic register.
b. Retains part of the result of arithmetic operations such as multiply or divide.
c. Retains the most significant portion of the dividend during divide operations.
d. The Q Register is also used as the primary index register for address modification.
e. The Q Register supplies the addressing for per ip her a 1 equipments during
unbuffered input/output operations.
The I Register is the second index register available.
00FF 16 ·
It is actually core location
The M Register or Mask Register controls interrupts. A one bit in any position
of the mask register will enable an interrupt from the corresponding line number
while a zero in any bit position of the mask register blocks the interrupt from the
corresponding line number. The mask register is effective in controlling interrupts only when the interrupt system is enabled.
Other registers of interest to the programmer are:
P Register: This 15-bit register functions as the program address counter. It
holds the address of each instruction, and after executing the instruction at address
P, P is advanced to the address of the next instruction. The amount by which P
is advanced is determined by the type of instruction being executed.
X Register: The X register is an exchange register containing 16 bits. This
register holds data going to or from memory. It also holds one of the parameters
in most arithmetic operations.
Y Register: The Y register is an address register containing 16 bits. It is in this
register that storage addresses are formed and held for transfer during a storage
reference.
The A, Q, M,
mer's panel.
X~
Y and P Registers can be displayed and entered on the program-
Shifter: The shifter is used by multiply, divide, and shift ins t r u c t ion s. It is
capable of shifting the output of the adder left and right one binary position or
giving a direct transfer path to the arithmetic registers.'
Adder: A I6-bit adder is used toperform all arithmetic and address calculations.
Inputs to the adder are shown through the gates. The adder is a one's complement:
subtractive adder which is more fully described in the next chapter.
F Register: This 8-bit register is used by the control section of the 1704 for decoding instructions.
1-8
'-,
......... '
1.5.1
Z Register: This register communicates between the actual core storage and the
computer through the X register. Notice this is an IS-bit register; the lower 16
bits are data or instructions from core, the 17th bit or bit #16 is the par it Y bit
and the high order bit or bit #17 is the pro g ram protect bit. Core storage is
described more fully in the next section.
S Register: This 15-bit register w h i chis fed from the Y reg is t e r is used to
directly address core storage. Since core storage has a maximum of 32K locations, the S register need only be 15 bits.
The Z register and the S register are connected directly to ext ern a I equipment
through the 1705. This d ire c t access channel allows insertion or extraction of
core data directly to peripherals without program intervention.
Refer to Reference 1, Appendix A, for a more de t a i led description of the registers.
o
1-9
.
I-'
r-'
~
~
~
I-d
(5
>
~
(":)
0
Z
~
~
0
c::::
!J:j
>
~
1721 PTR
~
CR
1704 CPU
32K
Disk
'I
....
o
1711 TTY
I
Analog
Gear
.J
(
)
0
Z
~
o
CONTROL DATA
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Hi Temp
Temp Warn OV
PP
Par
~OOOOO
10 (500
~
F2
SK
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
LP
XR
A
0
0
0
0
1
1
1
1
L
A
Q
0
0
0
0
Q
Skip
MIAfQIM
K
Interregister
Shift
(')
6
Fl
Register ReferencL
q
i
o
I:j
00
6
1I
510 0 0 0 006 0 0 0 a 0 a 6 a a 8
r lind
F
Ind Sto
OFF
r-:::l
~
1-1
I
EMERGENCY
1700
Storage Reference
ot-"
(D
ear
Program
Protect
Register Select
Q
Enter
00
..
Test
Mode
Sweep
Sel
Skip
Sel
stop
00
Master
Clear
Run
0 0
Step
.
1-1
1.7
1.7 CONSOLE DESCRIPTION
SWITCHES
Master Clear
This is a three-position key/lever switch. A Mas t e r Clear is
executed whenever it is momentarily operated either up or down.
A Master Clear returns the computer and peripheral device'S to
initial conditions by clearing all registers and peripheral equipment logic.
Run/Step
This is a three-position key/lever switch. When the s wit chis
momentarily placed in the RUNposition, the computer begins program execution, starting with the instruction whose address is in
the P register. The computer is stopped by momentarily placing
the switch in the STEP position.
If the switch is repeatedly placed in the STEP position, the computer steps t h r 0 ugh the program, stopping after each storage
reference. The significance of the storage reference just made
is indicated by the Instruction Sequence indicators (INSTRUC TION,
INDIRECT ADDRESS, etc.).
Enter/Sweep
This is a three-position key/lever switch maintained in all positions. The center position is off. Enter is used to enter memory;
sweep is used to examine the contents of memory.
Enter
The ENTER position selects the Enter mode. In this mode, each
Step operation of the R UN/ STE P switch stores the contents of the
X register at the location specified by P + 1 and then advances the
P register by one. The first step after a Master Clear or clear
P stores the contents of the X register at the location specified
by P.
To store a few instructions in unprotected storage, pro c e e d as
follows:
1) Power is on but computer is stopped.
2) Operate Master Clear switch.
3) Press P REGISTER SELECT switch and CLEAR pushbutton,
in that order. Set desired address for instruction in P by use
of indicator pushbuttons.
4) Set ENTER/SWEEP switch to ENTER.
5) Press X REGISTER SELECT switch.
1-12
1.7
o
6) Press CLEAR pushbutton, then enter word to be stored by use
of indicator pushbuttons.
7) Move RUN/STEP switch to STEP one time (carefully).
To store additional words in successive storage locations, repeat
steps 6 and 7 until finished. To change to a new seq u e n c e of
addresses, start at step 2 for the first one, then repeat steps 6
and 7 for each successive word.
A lighted indicator pushbutton indicates a "1", a dark one a "0".
Sweep
The SWEEP position selects the Sweep mode. In this mode, each
operation of the RUN/STEP switch displays in the X register the
contents of the storage location whose address is P + 1. The P
register is advanced by one after each Step operation. The first
step after a Master Clear or clear P displays the location specified by P. Instructions are not executed.
Selective Stop
This is a three-position key/lever switch. The computer stops
when it executes a Selective Stop instruction if this switch is in
either the up or down po sit ion. The up position is maintained;
the down position is momentary.
Selective Skip
This is a three-position key/lever s wit c h. Two Selective Skip
instructions (SWS and SWN) are conditioned by this switch. This
switch is off in the center position; the up position is maintained;
the down position is momentary.
Program Protect/
Test Mode
This is a three-position key/lever switch maintained in all positions. The center position is off.
Program Protect
The PROGRAM PROTECT position selects program protection.
Test Mode
The TEST MODE position s e I e c t s Test mode.
the customer engineers for maintenance.
Emergency Off
This is used by
Pressing this switch shuts off power for the entire system.
1-13
1.7
,-.........
,.
Register Select
The M, P, Y, X, A, and Q registers are available for display and
manual entry of values via switch/indicators. A six-pushbutton
switch/indicator, REGISTER SELECT, selects the register for
display and entry.
Push the button for the desired register, and the contents of that
re gis te r will light up in the 16-bit console binary register. A
button lighted indicates a 1 bit; unlighted, a 0 bit.
If it is des ire d to change the contents of the register, push the
C LEAR button (not Master Clear switch) to clear out that register.
Then set the new con ten t s in the register by pushing the button
(it will light up when pushed) for each bit that should be a 1 bit in
the register.
INDICATORS
Program Protect
The PROGRAM PROTECT bit indicator displays the state of the
program protect bit of the last storage location referenced by the
computer.
Faults
There are five fault indicators.
is present.
Instruction Sequence
Indicators
When lighted, the fault condition
•
HI TEMP
The temperature inside the co mp ute r has exceeded safe operating limits.
•
TEMP WARN
The ambient air temperature is approaching
the maximum safe operating limit.
•
OVERF LOW
•
PROGRAM PROTECT A violation of the program protect
system has been detected.
•
STORAGE PARITY A parity error has been detected in an
operand or instruction read from storage.
An arithmetic register overflow has occurred.
When an instruction is being stepped, this group of four indicators
des c rib e the meaning of the storage reference just completed.
The data of the storage reference (read or write) is in the X register. The four indicators and the i r meaning when lighted are:
•
INSTRUCTION: The contents of the X register is an instruction.
1-14.
)
~i
1.7
I" .• ~ ... \
U
• INDIREC T ADDRESS: The contents of the X register is the
result of indirect addressing. The indirect address may also
be another indirect address, hence, this indicator may remain lighted for several consecutive storage references.
•
STORAGE INDEX: The contents of the X register is the value
of the Storage Index register.
• OPERAND: The contents of the X register is the value of the
operand either written into or read from storage.
If more than one Instruction Sequence indicator is 1 i g h ted, the
computer is running. If only one indicator is lighted, the computer is not running or is in a rather unlikely program loop which
does not use operands, the storage index, or indirect addressing.
o
1-15
o
CHAPTER II
1700 ARITHMETIC
o
CHAPTER II - 1700 Arithmetic
U
o
TOPIC
PAGE
2.1
HEX-DEC Conversions
2-1
2.2
Range of Numbers
2-4
2.3
Adder:
2-6
2.4
Overflow
2-7
2.5
Floating Point Numbers
2-7
2.6
Exercises
2-10
2.1
o
()
Numbers
Figure 6.
Hexadecimal
Binary
Decimal
Octal
0
0
0
0
1
1
1
1
2
2
10
2
3
3
11
3
4
4
100
4
5
5
101
5
6
6
110
6
7
7
111
7
8
10
1000
8
9
11
1001
9
·10
12
1010
A
11
13
1011
B
12
14
1100
C
13
15
1101
D
14
16
1110
E
15
17
1111
F
16
20
10000
10
2.1 HEX-DEC CONVERSIONS
Since the 1700 is a 16-bit machine, it is convenient to group the 16 binary bits into 4
hexadecimal digits. This allow s for quicker and easier manipulation of the arithmetic
and easier identification of program dumps. The relationship of the 4 binary bits to each
hexadecimal digit and the decimal equivalent is shown below:
15
[
14
13
12
11
10
I
H3
9
7
8
6
5
HI
16 Bit 1700 Machine Word
2-1
3
2
1
I
I
H2
4
0
I
HO
2.1
",,--'.
The Range of Binary Bits in Each HEX Position Is:
I
G'
Binary
HEX
Decimal
Binary
HEX
Decimal
0000
0001
0010
0011
0100
0101
0110
0111
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7·
1000
1001
1010
1011
1100
1101
1110
1111
8
8
9
9
10
11
12
13
14
15
A
B
C
D
E
F
This table must be memorized.
The arithmetic operations that are essentially basic involve binary to HEX, HEX to binary, hexadecimal to decimal, decimal to hexadec imal conversion, taking the one's
complement of a hexadecimal number, and adding and subtracting hexadecimal numbers.
Each hexadecimal digit represents by its position in the n u m be r a certain power of the
base 16. The least significant digit is a multiple of 16 0 which is 1; the second least
significant digit represents a multiple of 161 which is 16; the third least significant digit
represents a multiple of 16 2 which is 256; and the most significant hex a dec i m a I digit
represents a multiple of 16 3 which is 4096. It is necessary then only to do these multiplications followed by a final addition of the four multiples in 0 r d e r to convert a hexadecimal number to the decimal equivalent.
Example: Convert 13ED16 to Decimal.
D
E
3
1
x
x
x
x
16 0
161
16 2
16 3
=
=
=
=
13
14
3
1
x
1 = 13
x
16 = 224
x 256 = 768
x 4096 =.4096
Sum
510110
There are many methods of converting a decimal number to hexadecimal. The simplest
method involves successive divisions of the decimal number by 16. Each remainder becomes in turn the least significant hexadecimal digit of the converted answer, while each
quotient becomes the next decimal number to be divided. D i vis ion s continue until the
quotient becomes zero.
Example: Convert 1476 10. to HEX.
92 - Continue division
16 11476
.144
36
~
4 - First remainder is HO=4
2-2
I
2.1
5 - Continue division
16
192
80
12 - Second rema:inder is H1=C
o-
Divis ion stops
1615
o
5 - Third rema:inder is H2=5
ANSWER - 1476 10 = 5C4 16
Addition of hexadecimal numbers is straightforward. Notice that 16 is carried fronl the
least significant position to the most. The subtract:ing, of course, is the opposite of addition with 16 be:ing borrowed from the most significant position.
Example: Add the HEX numbers 13CE and 2AA 7.
13CE
+ 2AA7
3E 75
It "
E (14) + 7 = 21 - Carry
C (12) + A(10) +1 = 23 3
+ A(10) +1 = 14 = 31
+2
16-Excess 5
Carry 16-Excess 7
No Carry-Excess E
No Carry-Excess 3
As we'll encounter shortly, negative numbers in the 1700 are carried :in one's complement
form. The subtraction in each position of a dig it from the largest possible digit in the
base used yields the one's complement of the number.
Example: Find the One's Complement of the HEX Number 347E.
Subtract
FFFF
347E
CB 81 - is One's Complement of 347E.
The same result can be obtained by convert:ing both numbers to binary.
HEX
BINARY
FFFF =
347E =
CB81=
1111 1111 1111 1111
0011 0100 0111 1110~~~-------------------------------~
1100 1011 1000 0001--is One's Complement of - - - '
Notice that the one's complement of a binary number has all ones :in the b:inary n u m be r
changed to zeroes, and all zeroes changed to ones, which s u g g est s another method of
obtain:ing the one's complement of a number.
2-3
2.2
!
Figure 7. 1700 Integer Numbers
"
Example:
D -------------~
------------~
t
SIGN BIT
~
3 B716 =1010 0 0 0 0 1 1 1 0 1 1 0 1 1 11
3
B
7
Negative Numbers Stored in One's Complement Form:
F
3
F
c
F
F
B
4
7
8
1111 1 1 1 1000 100 10001
1
SIGN BIT
'2-4
--"
"....---~/
I
2.2
c
2. 2 RANGE OF NUMBERS
Figure 8 illustrates the range of n u m be r s used in the 1700. The total number of bits
available is 16 and for arithmetic operations bit #15 will be a zero for positive numbers,
and a one for negative numbers. For positive numbers, bits 0-14 are in true form. However, for negative numbers bits 0-14 are in one's complement form. Notice there are
two O's, a positive zero and a negative zero •
. - Positive Numbers-Bit 15 is a 0 - Number is in true form.
+32,767
+32,766
t
Positive
Numbers
+
C)
0111 1111 1111 1111
0111 1111 1111 1110
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
+1
+0
0000 0000 0000 0001
0000 0000 0000 0000
-0
-1
1111 1111 1111 1111
1111 1111 1111 1110
•
t
-32,766
•
•
•
•
1000
-32,767
1000 0000 0000 0000
•
Negative
Numbers
•
•
•
•
•
•
•
•
• • •
0000 0000 0001
~Negative Numbers-Bit 15 is a 1 - Number is in One's
Complement Form.
Note: Each Negative Number is Represented as the One's Complement of its
Corresponding Positive Number.
Figure 8. Range of Numbers Used in the 1700 /
2-5
2.3
2.3 ADDER
A straightforward add e r would pose problems in the 1700 in that negative zero in many
cases would be produced as are s u 1t instead of a positive zero. Consider the addition:
4321
+BCDE
FFFF - Straightforward addition of the positive number 4321 and a negative number of the same size, BCDE, yields a correct result of zero, but negative zero instead of positive zero.
Since the skip tests do not r e c a gn i z e negative zero, the adder in the 1700, which is a
16-bit one's complement subtractive adder, eliminates minus zero in all but one case. It
functions by taking the one's com p 1 e men t of the addend and subtracting this from the
augend. The same addition as in the above is accomplished:
Add
4321
4321
4321
4321
+ BCDE----.One's Complement--.4321-.Now Subtract
Same Result - - - - I.~. 0000
But +0
The one case where a minus zero is produced is the case where minus zero is added to
minus zero.
Add
Subtract
FFFF
FFFF
+ FFFF - - - - - I..
~O 000
FFFF
(-0) + (-0)
=
(-0)
Negative zero can be con v e r ted to positive zero by simply adding positive zero to it.
Add
Subtract
FFFF
FFFF
+OOOO--------~~·FFFF
0000
(-0) + (+0)
=
(+0)
For subtraction, the subtrahend is not complemented, but is subtracted directly from the
minuend. The only case producing negative zero is (-0) - (+0) = (-0).
Subtract Directly
FFFF
0000
FFFF
Page 3-20 of Reference 1, Appendix A, expounds further on conditions causing negative
zero.
2-6
2.4
....,
,.,
u
2.4 OVERFLOW
Overflow in the 1700 is e sse n t i all y a condition wherein the result of some arithmetic
operation is too large to fit into its designated register. Overflow can be caused by add
type operations, by a subtract type operation and by divide. In a one's complement computer like the 1700, overflow, when it occurs, sets the overflow indicator which remains
on until tested. Refer to Figure 8. Notice that overflow will not occur when a positive
number is added to a negative number since the result will always lie within the range of
numbers. Adding two positive numbers together or adding two negative numbers together,
or the equivalent operation (subtracting a neg a t i v e number from a positive number or
subtracting a positive number from a negative number), can cause a result which is too
large to be contained in the A or Q Register. Recovery can be made from add type overflow operations and, in fact, overflow is often a useful tool for accumulating single precision numbers into double precision numbers.
Example: Add 1 to the Largest Possible Number
7FFF
000l--+-Complement
Then Subtract
--t-l••
Subtract Borrow
C)
7FFF--Note: If the adder must borrow from
beyond the most significant
FFFE
8001
position, it subtracts 1 from
1
the result.
8000 ~Answer is now (-7FFF) which is wrong.
The computer logic will set the overflow indicator when both signs are initially the same
and a borrow occurs.
Recovery ca,.n be made, however, by accumulating the overflow in a second cell and
masking out bit-15 of the first, since bits 0 through 14 remain correct.
Remember that any add type instruction can cause overflow.
RAO, AAQ, etc.
This includes ADD, SUB,
Divide overflow will be described in more detail in the storage reference class of instructions for the DVI instruction itself.
2.5 FLOATING POINT NUMBERS
Floating point numbers will be of interest to scientific pro g ram mer s, and since the
Fortran compiler provides for them, their format will be discussed here. The range is
.591 x 10- 39 through 1. 694 x 10 39 •
Floating point numbers require two words of core and inc 1 u de: one bit, sign of coefficient; 8 bits, biased exponent; 23 bits, normalized coefficient.
2-7
2.5
Word 1
---------------~
7
Word 2
~---------------0\
0\/15
----}----i--------]
[[
/15 .14
6
r
......
_ _ _ _ _ _ _ _ _ 1_ _ _ _ _ _ - - - - -
--------------------~/
I\
Coef¥Cient
23 Bits
Sign of Coefficient
1 Bit
A number, for example 25., would be packed as follows:
1. convert decimal number to hexadecimal
25·10 = 19·'16
2. convert hexadecimal number to binary
19. 16 = 0001 1001. 2
3. normalize the binary number (move the binary point to the left of the first one bit)
0001 1001. 2 = )1001 2 x 2 5,
coefficient
exponent
(power of 2)
4. bias the exponent. In the 1700, all exponents (positive or negative) are biased by
8016 (80 is added to the exponent)
25 = 5 + 80 = 8516
5. pack the number in the two words:
'
!
10\100001011 1100100! 00000000000000001
f
ex'lonent
85
V
\
I
Coefficient
Left Justified
sign of coefficient
= 42E4000016
A ,negative number would be packed as though it was positive, then both words
would be complemented.
- 19 16 =
1110111101010011011111111111111111111
= BDIBFFFF16
To unpack numbers (i. e., from a HEX dump) the reverse procedure is followed.
2-8
l'
"
.....
",
CHAPTER III
ASSEMBLY SOURCE FORMAT
(j
2.5
Figure 9.
Floating Point Example
EXAMPLE: PACK 375 10
375 10
= 17716
16/375
/23 r 7
LLr7
17716
= 0001
0111 0111 2
.1011 1011 1000
o
or
=
X
1
29
1Q]1000 100D 101110111 100000000000000J
~
4
4
D
DC
EXPONENT:
0
0
0
9
+80
---89 16
10001001 2
- 375 10 WOULD BE STORED AS
F
F
F
F
F
F
F
F
-44
DOC
000
--- ----------------- ----'--B
B
2
2
3
F
F
F 16
~ [Q111011Q[01000 10~O 1111111111111}]
2-9
2.6
2.6 EXERCISES
1. Group these 16 bit 1700 binary numbers into hexadecimal, convert the an s w e r s to
decimal, then add the three together.
a.
0010 1101 1010 1110
b.
1000 1111 1100 0111
c. 1111 1111 1100 0000
2.
Convert these decimal numbers to HEX, and represent each in binary as they would
appear as a 16-bit 1700 word.
a. 4095
3.
b.
-17
c.
255
How would a signed number, either positive or negative, that occupied only an 8-bit
field be expanded to occupy a 16-bit field?
2-10
CHAPTER III - Assembly Source Format
/..-
-'\
"-.)
o
TOPIC
PAGE
3.1
Program Flow
3-1
3.2
1700 Assembly Language Source Format
3-2
3.2.1
Location Field
3-2
3.2.2
Opcode Field
3-3
3.2.3
Address Field
3-3
3.2.4
Comment Field
3-5
3.3
Assembly Listing
3-5
3.1
U
3.1 PROGRAM FLOW
Two phases are involved in processing the assembly language program. The first phase
involves reading of the source program (the program prepared by the programmer) into
the computer un de r control of the assembler program. The assembler program reads
and decodes the instructions 0 u t put tin g a listing with the object program. The object
program, which can be output on either paper tape, mag tape, or disk is in a formatted
form suitable for loading back into the computer un de r control of the relocating linking
loader program. This re-entry of the object program into the computer through the loader
is Phase Two. After loading, relocating and linking this program appropriately to other
programs, the pro g ram can now be executed. Two large standard software packages,
then, are involved in the assembly process; the assembler itself and the relocating linking
loader. Figure 10 illustrates this diagrammatically.
Phase 1 - Assembly of Source Program
Source Program
1700 Computer
Obj ect Program
(J
~-.
rv\Ju
Assembler
Program
Paper Tape
...
or
MagTape
Paper Tape
Disk
--
g
1700 Computer
- - -....~
Figure 10.
Relocating
Linking Loader
- - - - - - - - I I...
~ Results
Processing the Assembly Language Program
()
3-1
Q
Listing on typewriter
or printer
Phase 2 - Loading and Running of Object Program
Object Program
0J\J
3.2
3.2 1700 ASSEMBLY LANGUAGE SOURCE FORMAT
Regardless of the standard assembler being used (utility assembler or macro assembler)
the source format is prepared the same. This source format consists of four fields, the
lo cat ion field, the opcode field, the address field and the comment field as illustrated
below:
I
Location
Opcode
Address
Comments
The total width of all four fields combined is 72 columns. Each field, however, can be of
any length and the statements are said to be free-field. To signal the end of these fields,
either a blank or a tab is used. The blank is technically used as the field terminator for
card input source with con sec uti v e blanks ignored and the first non-blank character
signifying the beginning of the next field. For paper tape input source the tab u I a r key
depression is normally the field terminator since the source can be typed using tab fields
to arrange the source type in an orderly fashion. Blanks, however, can be used for paper
tape input source as field terminators also. Consecutive tabs will indicate the absence of
a field. The carriage return key depression will signify the end of a statement for paper
tape input source. The end of the card itself for card input source is the statement terminator.
3.2. 1 Location Field
The location field is used for placing symbols which will de fin e positions in the
program. The s e symbols have a maximum length of· six characters (more than
six will not be processed by the assembler) and the first character must be alphabetic.
Example:
Location
Opcode
Address
Comments
A123
1A23
------i~~ Legal
TAGTOMB
-----;~.
-----t..~ illegal - must begin with
alphabetic
Legal - only TAGTOM is
processed.
The same symbol cannot be used twice in the same program, as this would constitute a doubly defined symbol, an error condition. Upon finding a symbol in the
location field, the assembler p I ace s this symbol with its location in its internal
symbol dictionary. Further references to this symbol then will yield its location.
An asterisk in the first column of the location field indicates that all subsequent
information in that statement is to be treated as a remark.
3-2
3.2.1
u
Example:
Location
Opcode
Address
Comments
* THESE LINES WILL BE PROCESSED AS A REMARK AND
*
APPEAR ONLY ON THE LISTING.
THEY DO NOT GENERATE
* ANY MACHINE CODE.
START
Symbols appearing in the location field corresponding to certain pseudo instructions are meaningless. These will be discussed under the section dealing with the
pseudo instructions. A n u mer i c entry into the location field is allowed for one
pseudo instruction only, the NAM pseudo instruction.
3.2.2
Opcode Field
In this field, machine instruction m n e m 0 n i c s or pseudo instructions or macro
names (if the macro assembler is used) are placed. The machine mnemonics will
be decoded by the assembler with the appropriate machine codes generated. The
pseudo instruction will produce act ion by the assembler and may not, for some
pseudo instructions, generate any specific machine instructions. Macro names
will be discussed in Chapter VII.
o
Example:
Location
Opcode
Address
NAM
I
NAM is a pseudoinstruction
1
START
]
I
I
j
Comments
i
-LDA
LDA is a machine
mnemonic
J
I
~
3.2. 3 Address Field
The operands used in the address field are:
Symbolic
Numeric
Asterisk
Special Characters (A, Q, M, 0, I, B)
Combination of above special characters joined by arithmetic
operators (address expression)
Null (absence of operand)
Symbols used in the address field either alone or in an expression, must be legally
defined. Besides appearing in the location field, symbols can be defined as being
names in the address field of certain pseudo instructions.
3-3
3.2.3
Numeric operands in the address field can be either decimal or hexadecimal. To (
distinguish between the two, a $ sign would precede the hexadecimal number (1234 '-...../
is a decimal, $1234 would be hexadecimal). The range of decimal numbers must
be.± 32,767. The range for hexadecimal numbers is.±. 7FFF. Expressions are
formed by the combination of either symbolic or numeric operands with addition,
sub t r act ion, multiplication or division operators (+, -, *, /). Nesting is not
allowed. The expression is scanned left to right with divisions and multiplications
done first and a second scan left to right for addition or subtraction. An expression e val u ate d as a constant in the address field may be used only with the =X
form of constant, not =N.
Example:
Location
I
TAG1
I
TAG2
Opcode
I
I
Address
Comments
I
I
I
I
TAG1+6*$1C/4
LDA
I
If TAG1 is at location 103 16 , the expression is evaluated:
1st) 6 x 28 = 168
2nd) 168 i 4 = 42 = $2A
3rd) 0103 + 2A = 012D, then the contents of cor e location 012D16 is loaded into
the A register at run time.
The asterisk can be used in the address field to also specify the current location
of the program counter w hen the instruction is assembled. If the instruction is
two words long, the as t e r is k specifies the first word of the instruction. Even
though the asterisk is also used in the address field as a multiplication sign, the
logical use of the asterisk for both processes will not conflict.
Example:
Location
Opcode
I
I
TAG
I
LJ?A
I
I
I
I
TAG1
Address
Comments
I
*-2
I
I
I
I
I
LDA
**2
Will load A with contents
of the core location 2 before TAG.
The first * refers to the
1 0 cat ion of TAG 1, the
second * is for multiplication.
The special symbols Q, I andB are used with the storage reference instructions
to refer to index registers. Q refers to Q register index modification, I refers
to the contents of location FF to be used as an index register, and B would specify
both the Q register and location FF to be add e d to the base~ address to form the
effective address.
3-4
3.2.3
Example:
Opcode
Location
Address
I
I
LDA
TAG, I
I
I
I
I
I
I
I
I
I
LDA
TAG,Q
I
I
TAG,B
I
I
LDA
I
I
Comments
The contents of core location FF are added to
TAG to produce the effective address.
Sam e as abo v e, but Q
register is used.
Both Q and I are adde d.
I
I
The address fie 1d for any of the interregister instructions requires either A, Q
or M registers as a destination.
Example:
Opcode
Location
Address
I
I
A,Q
AAQ
I
I
I
TRA
A,Q,M
I
I
I
c·
Add A to Q and put results in A and Q
I
I
Comments
I
Transfer A to A, Q and
M registers
For the interregister instructions, A, Q and M, refer to the registers A, Q and M.
3.2.4 Comment Field
This field is used for remarks that are printed as part of the list output. Entries
in this field do not produce any machine code.
If it is desired to put a comment on an instruction which does not have an address
field (i. e. , SLS) it is advisable to put a 0 in the address field, before the comment
begins, to eliminate an assembly error message.
i. e. ,
~.
SLS
SLS
0
COMMENT
COMMENT
incorrect
correct
3 ASSEMBLY LISTING
The assembly list consists of 18 columns of descriptive information related to the source
statement, followed by a maximum of 80 columns listing the source statement.
3-5
Column
Contents
1-4
line number; truncated to 4 deoimal
digits
5
space
6
relocation designator for location
P program relocation
D data relocation
7-10
location in hexadecimal
11
space
12-15
machine word iIi hexadecimal
16-17
relocation designator for word
P
-P
C
-C
D
-D
X
blank
program relocation
negative program relocation
common relocation
negative common relocation
data relocation
negative data relocation
external
absolute
,....
'----........
',-..... ,
SYMBOL TABLE
18
space
19-98
input source statement
A table containing the location symbols, 10 cat ion s, and relocation
values is printed at the end of pass 3 if the L option is selected. Format of the symbol table:
Column
Contents
1-6
9-12
13
symbol name
location
relocation of location
15-20
23-26
27
symbol name
location
relocation of location
29-34
37-40
41
symbol name
location
relocation of location
The columns not specified above contain spaces.
(\,
3-6
3.3
Figure 11. Sample Assembly Listing
Line Number
Location (relative to beginning of program)
Contents of Location (hexadecimal code
of instruction)
0001
0002
0003
0004
0005
0006
0007
0008
POOOO 0000
START
POOOi C400
POO02 OOOG P
POO03 GOFF
POO04 1400
POO05 8000 P
POO06 0010
X
NAM
ENT
0
LDA +
SOURCE
START
0
STAJMP+
I
(START)
$10
START
NUM
END
\
X
v
I
+Input Source Statements
I
OOFF' ,START
OOOOP X
LNumber of errors
would appear here
0006P
Symbol Table - - - - - '
Appendix D contains error messages.
3-7
(J
II
CHAPTER IV
BASIC 1700 INSTRUCTION FAMILIARIZATION
o
CHAPTER IV - Basic 1700 Instruction Familiarization
0
o
TOPIC
PAGE
4.1
LDA, STA, ADD Assuming Data Available
4-1
4.2
LDA, STA, ADD Using Preset Data
4-1
4.3
LDA, STA, ADD Using Preset Data to
lllustrate Looping
4-2
4.4
STQ and MUI Instructions
4-2
4.5
LDQ and DVI Instructions
4-3
4.6
JMP and RTJ to lllustrate a Subroutine
4-3
c)
4.1
4.1 LDA, STA, ADD ASSUMING DATA AVAILABLE
The Load A (LDA) instruction replaces the contents of the A Register with the contents of
the referenced m e m 0 r y location. The contents of the memory location is not changed.
The Store A (STA) instruction replaces the contents of a referenced memory location with
the contents of the A Register. The contents of the A Register is not changed.
The Add to A (ADD) instruction forms a 16-bit sum of the contents of the A Register and
the contents of the referenced memory location and p I ace s this sum in the A Register.
The contents of the memory location is not changed.
Problem: Replace the contents of location SAVE with the sum of the contents
of locations SAVE and DATA, assuming that both locations contain legal data.
Location
Opcode
Address
LDA
DATA
ADD
SAVE
STA
SAVE
4.2 LDA, STA, ADD USING PRESET DATA
The NUM instruction c rea t e s a table of constants listed in the addres s field behind the
instruction. If a Label is given, it is assigned to the first value.
The BSS pseudo instruction reserves a segment of core to be used for any purpose.
data contained is unknown at load time.
The
The BZS pseudo instruction reserves a segment of core to be used for any purpose and
fills this area of core with all zeroes.
Problem: Add zero to the contents' of location TAG and store the res u I t in
location TAG2. Locations TAG and TAG2 should then be equal.
Location
Opcode
Address
TAG
NUM
$423
BZS
TAGl(l)
BSS
TAG2(1)
LDA
TAG
ADD
TAGI
STA
TAG2
BEGIN
4-1
4.3
4.3 LDA, STA, ADD USING PRESET DATA TO ILLUSTRATE LOOPING
The Skip if A is Zero (SAZ) instruction checks the contents of the A register. If A is all
zeros, the program skips to a prestated location up to 16 locations forward, (never backward). If not, program control goes to P + 1 (the next location).
The Skip if A is Positive (SAP) instruction checks the uppermost bit of the A register. If
this bit is "0" (positive), program execution will skip to the specified location up to 16
locations forward, (never backward). If not, the program will continue at P + 1.
The Skip if A is Minus (SAM) operates identically to the SAP instruction except that the
uppermost bit of the A Register is checked for a "1", indicating a negative quantity.
Problem: Add 21 16 to each of the quantities in a r ray TAG1 and then store
these new numbers at array TAG2.
Index Register I will be used for con t roll in g the loop. It starts at 4 and progresses
through 3, 2, 1, 0, then the loop ends when it turns negative.
Solution:
Location
Ope ode
Address
TAG1
NUM
NUM
BSS
NUM
NUM
NUM
$4152,$0431,$0210
$12F3, $F201
TAG2(5)
$21
$0001
$0004
LDA
STA
LDA
ADD
STA
LDA
SUB
STA
SAZ
JMP
SLS
END
SAVE
$FF
TAG3
TAG1, I
TAG2, I
$FF
ONE
$FF
DONE-*-l
LOOP
0
TAG3
ONE
SAVE
BEGIN
LOOP
DONE
Comments
t'?""-
4~FF
for loop control
1st no. ----- A
(A)+(TAG1 +(FF» ---. A
(A)
~ TAG2+(FF)
Subtracts 1 from A
Skip to DONE if (A) = 0
Stop Instruction
4.4 STQ AND MUI INSTRUCTIONS
The S tor e Q (STQ) instruction replaces the contents of the referenced memory location
with the contents of the Q Register. The contents of Q are unchanged.
4-2
"-
4.4
U
The Multiply (MUI) instruction forms a 32-bit pro d u c t of the contents of A (multiplier)
and the contents of the referenced memory location (multiplicand) and places the product
in the QA Registers. The contents of the memory location is not changed.
Problem: Multiply the contents of MEMbythe quantity 2016 which is currently
in A. Store the results of A in memory location A and the results
of Q at memory location Q.
Location
Opcode
Address
MUI
STA
STQ
MEM
Comments
A
Q
4.5 LDQ AND DVI INSTRUCTIONS
The Load Q (LDQ) instruction places the contents of the referenced memory location into
the Q register. Contents of memory are unchanged.
The Divide Integer (DVI) instruction divides the 32-bit QA Register by the contents of the
referenced memory location. The contents of memory are not changed. Q will contain
the remainder and A the quotient.
Problem: Divide 4528
o
16
by the contents of location SAVE
Solution:
Location
Opcode
Address
SAVE
TAG1
TAG2
NUM
NUM
NUM
LDQ
LDA
DVI
$0025
$4528
$0000
TAG2
TAG1
SAVE
Divisor
Dividend
Clear Q
Get dividend
Answer is in A
4.6 JMP AND RTJ TO ILLUSTRATE A SUBROUTINE
The Jump (JMP) instruction causes a program sequence to terminate and initiates a new
sequence at a specified location.
The Return Jump (RTJ) instruction is a jump enabling the progralll to begin execution in
a new location and, by storing a return address, return to the next ins t r u c t ion in the
program sequence.
Problem: During the main pro g ram sequence, skip to a routine to clear a
storage area, and ret urn to the location which the program left.
4-3
4.6
Location
Opcode
Address
LDA
STQ
RTJ
NAME
SAVE
CLEAR
I
I
CLEAR
I
SLS
0
LDA
STA
I
Comments
Lea ves P+2 in CLEAR.
Program Control given
to LDA TAGY.
0
TAGY
TAG2
Return address placed
here.
Clear location(s)
(CLEAR)
Will return control to the
SLS instruction.
I
JMP
I
I
TAGY
TAG2
I
NUM
BSS
0
TAG2(1)
4-4
\,-j
CHAPTER V
1700 MACHINE INSTRUCTIONS
o
/-
r-----
I
1,,--.. /
('
~.
--
CHAPTER V - 1700 Machine Instructions
f'-
~)
TOPIC
• 5.1
5.1.1
0
C~.\I
5.1.1. 1
5.1.1.2
5. 1. 1. 3
5.1.1.4
5. 1. 1. 5
5.1.1.6
5. 1. 1.7
5. 1. 1. 8
5. 1. 1. 9
5.1.1.10
5.1.1.11
5.1.2
5.1.2.1
5.1.2.2
5. 1. 2. 3
5.1.2.4
5.1.2.5
5.1.3
• 5.2
5.2.1
5.2.2
5.2.3
5.2.4
o 5.3
5.3.1
o 5.4
e 5.5
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
• 5.6
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
5.6.6
Introduction
Storage Reference Class
Addressing for Storage Reference Class
Instructions
Constant Mode
Absolute: One Word
Absolute: One Word Indirect
Absolute: Two Word
Absolute: Two Word Indirect
Relative: One Word
Relative: One Word Indirect
Relative: Two Word
Relative: Two Word Indirect
Review of Addressing Modes
Indexing
Instructions in the Storage Reference Class
LDA, LDQ, STA, STQ, and SPA Instructions
ADD, ADQ, SUB, MUI and DVI Instructions
AND and EOR Instructions
JMP and R T J Instructions
RAO Instructions
Execution Times
Skip Class Instructions
A and Q Skip Tests
Skip Switch Tests
Overflow Skip Tests
Parity and Program Protect Indicator Tests
Shift Class Instructions
Timing for Shift Class Instructions
Interregister Class Instructions
Register Reference Class Instructions
Instructions ENA, INA, ENQ and INQ
Instructions SPB and CPB
Instructions EIN and IIN
Instructions INP and OUT
Instructions SLS and NOP
Exercises
Exercises on Constant Mode of Addressing
Exercises on Absolute Mode of Addressing
Exercises on Relative Mode of Addressing
Exercises on Indexing
Exercises on Shift and Skip Instructions
Review Exercises
PAGE
5-1
5-1
5-3
5-3
5-7
5-8
5-8
5-9
5-10
5-12
5-12
5-13
5-13
5-13
5-18
5-18
5-19
5-20
5-22
5-2!t
5-25
5-27
5-27
5-28
5-28
5-29
5-32
5-33
5-35
5-41
5-41
5-42
5-43
5-44
5-44
5-49
5-49
5-49
5-50
5-50
5-51
5-52
....- .",.'
.j
L)
5.1
INTRODUCTION
There are five classes of instructions in the 1700.
They are:
Shift Class Instructions
Skip Class Instructions
storage Reference Class
Register Reference Class Instructions
Interregister Class Instruction
Only the storage reference cIa s s uses core for operands. Instructions in all classes other
than storage reference class are one word instructions and take 1. 1 microseconds to execute
with the exception of the shift clas!3 instructions whose execution time depends on the number
of bits shifted, and INP and OUT instructions. Refer to Appendix B for instruction execution
times, or to section 5. 1. 3.
5.1 STORAGE REFERENCE CLASS
C)
Of the five classes of instructions in the 1700, only this group uses core for operands.
This means, then, that the instructions in this group are the only ones that are addressable. Because of the limitation of 16 bits in an instruction word to implement the ability
to reach any core location from any other core location, two-word instructions are used.
One-word instructions are available for addressing either absolute core blocks or within
a fixed range of core locations from the instruction. The format for these instructions is:
Address Mode
15
first word:
,
12 1~11----1-:--9--~~
'J I
Fir
lind , q
Ii
, Instr¥ction
Relative
Address Flag
Indirect Address Flag
(ind. )
7
,
G
~
o
I
,
D¥1ta
I Index Register Flag
Q
~--Index
second word:
Register Flag
M
~
is not zero for one-word instructions.
fl is zero, and M contains the operand (or operand address) for two-word instructions.'
The instructions are defined by the F field and will be discussed 1 ate r. The rest of the
format word deals with various ways of addressing the instruction; this will be discussed
first.
5-1
5.1
Figure 12. Address Modes for Storage Reference Class Instructions"
/'
..,
\,,,,,,,..-
ADDRESS MODE
15
12
J
first word:
11
10
Instructi(3'n
Relative
Address Flag
Indirect Address Flag
(ind)
9
Jt
8
o
7
t
L..._ _ _ _ _ _
Delta
I Index Register Flag
Q Index Register Flag
6.
6.
I: 0 for one-word instructions
= 0 for
two-word instructions
M
second word:
Assembly Language
,
Name
Desi~tor
Opcode
Terminator
Constant
,
Address
Field
Operand
Address
P+1
=N
=X
=A
One-Word Absolute
One-Word Abs. Ind.
(
Two- Word Absolute
+
Two-Word Abs. Ind.
+
One- Word Relative
*
One-Word ReI. Ind.
*
)
M
(
)
P+ 6.
(
)
(P+6.)
P+1+M
Two- Word Relative
Two- Word ReI. Ind.
(M)
(
)
(P+1+M)
CC45
C800
0044
CCOO
0044
LDA* (BUFADR) Loc BUFADR contains addr of operand; operand
in BUF--'A; BUF ADR is wit hi n 127 10 locs of
LDA instr.
LDA BUF
Contents of loc BUF --.A; BUF is any distance
from the LDA instr.
LDA (BUFADR)
Loc BUF ADR contains addr of operand; operand
--.A; BUF ADR is any distance from the LDA
instr.
*If the buffer is 4516 locations in the positive direction from this instruction
5-2
5.1.1
L.
5. 1. 1 Addressing for Storage Reference Class Instructions
Figure 12 illustrates the various ways of addressing storage reference class instructions. The combination of the r, ind, and b. bits determines the mode of
addressing used. Because of the limitation of 16 bits in an instruction word, some
modes of addressing require two words to reach all parts of core. A brief glance
at this chart shows a direct correspondence between two-word instructions and the
bit content of b.. When ~ (bits 0-7) in the instruction word is all 0' s, two consecutive core words are used as a single instruction. Also, there are only three
main t y pes of addressing: constant, absolute and relative. Within the absolute
and relative types are one and two-word va r i e tie s and also one and two-word
indirect types. Listed also in this table are the proper assembly language designators necessary to tell the assembler the exact mode of addressing desired. Indirect addressing is specified by parentheses enclosing the address field contents.
This table ignores man i p u I a t ion s with the index register since index register
modification is common to all modes of addressing. This fig u regives only the
base address for each mode. The base address must be found before index register
modification 0 c cur s even when indirect addressing is specified. In each of the
indirect addressing modes notice that the base address is specified as the contents
(the use of parentheses around the address specifies the contents of) of its corresponding non- indirect mode. This means that for indirect addressing a fur the r
search is made into the addressed core location to find the base address.
C~~~~
5. 1. 1. 1 Constant Mode
This mode of addressing is used where an operand is lmown to the programmer,
that is, he is using a constant. This mode of addressing utilizes two words.
The first word of the instruction is specifically the instruction itself, the mode of
addressing for this example is constant, and the unused bits in this word will be
set to zero. This arrangement is illustrated below:
15
I
---------------:.~
F
Bit ....~I------------------ 0
0
0
q
I
0
0
0
0
0
0
0
01
LInd=O
L-il =00
R=O
t
The upper four bits signify the actual instruction. This field is called the F field.
The next four bits, that,is, bits 8, 9, 10 and 11, are used to signify the mode of
addressing for the instruction. Also, bits 8 and 9 will signify indexing, where
bit 8 signifies index register I which is core location FF, and bit 9 will indicate
indexing with the Q register. For the constant mode of addressing bit 10, which
is called the indirect bit, is a zero and bit 11, which is called the relative bit, is
also a zero. For our example here, we will assume no indexing used, therefore
bits 8 and 9 will be o. The lower eight bits, that is bits 0-7, are called the il
field, and for constant mode of addressing all these bits are O's.
5-3
-5. 1.1.1
The combination of the ~ field, the indirect bit and the relative bit are indicators ,'--to the machine of the mode of addressing used. Note for constant mode the field '-__,/
is all 0' s, the indirect bit is a 0 and the reI a t i v e bit is a 0, signifying cons tant
mode of addressing.
Numeric constants. This form is for numbers.
Example:
LDA
=N$407F
This con stan t mode instruction written in assembly language will generate two
machine words of code:
at P
P+1
COOO
407F
The operand itself is placed in the second word, so the base address is P+l, the
second word of the instruction.
The =N in the address field signifies to the assembler the constant as numeric (a
number). The number can be either decimal or hexadecimal (in which case it is
preceded by the dollar sign). The res u 1 t of the above example is to load into A
the number 407F16.
Example:
LDA
=N256
..... _ /
The decimal number 256 would be converted and the following code generated:
at P
P+l
COOO
0100
Illegal example:
LDA
=N$100+$27
An error message would result because address arithmetic (+) is not allowed with
the =N form of constant addressing.
Address constants.
numbers.
This form is for 15-bit addresses and address arithmetic on
Example:
LDA
=XTAG
The =X in the address field signifies that TAG is a symbol. The assembler substitutes the value in its symbol d ire c tor y for the symbol and puts this value in
P+l. If, for example, TAG is a location symbol at address 100 in the program,
the following code is generated.
if"
5-4
5.1.1.1
r--- .
I
at P
P+1
\..J'
COOO
0100
An expression can also be used:
LDA
=XTAG+10
This will put the address of TAG+10 in the code:
at P
P+1
COOO
010A
The =X form of add res s cons tants is the correct way to allow numeric address
arithmetic:
ADD
=X$34F2-022+$lA
will generate code to add to the contents of the A register 34F6 16 •
1)000
at P
P+1
COOO ..... 34F6
Even though the result of the expression in the address field is a constant, the =X
form must be used rather than =N because an expression is not allowed with =N.
LDA
=X$100+$27 would be legal and would generate:
at P
P+1
COOO
0127
In address expressions only a 15-bit constant will be produced so note that
LDA
=X-TAG
will generate
at P
P+1
COOO
7EFF
(not FEFF)
also, with numbers:
LDA
=X-11
will generate
at P
P+1
COOO
7FF4
This feature of the assembler can well be utilized in sophisticated coding.
ASCII constants. This form is for alphabetic and numeric characters.
Example:
LDA
=AXY
5-5
5.1.1.1
The =A means that the alphanumerics following (only 2 allowed) are to be converted
to their ASCII 8-bit code. (See Appendix E.) The first alphanumeric (X in this
case) ASCII code is placed in the high order 8 bits of P+1, and the second ASCII
equivalent is placed in the lower 8 bits. The code will be:
at P
P+1
',-_,
COOO
5859
A blank is a character in the ASCII form:
LDA
=A
X
will generate the code:
at P
P+1
COOO
2058
ASCII will be discussed in detail when 110 is discussed.
Examples:
COOO
1000
LDA
=N$1000
Get 100016 into A register
COOO
00C8
LDA
=N200
Get 20010 into A register
COOO
0500
LDA
=XDATA
Get address of DATA P0500
into A register
COOO
0505
LDA
=XDATA+5
Get address of DATA+5 into A
register
COOO
LDA
=X-$100
Get 15-bit negative of 10016
into A register
LDA
=AX
Get ASCII cons tant X into A
register
r- --,
7EFF
COOO
5820
5-6
5.1.1.2
l...;
5.1.1.2 Absolute: One Word
As was mentioned before, there are both one-word and two-word instructions for
the Storage Reference Class. Let's examine the absolute mode of addressing in
its one-word form. The format for this mode of addressing is:
15------------------------~~
I
I 0 IQ
~
~0
F
Instructiot
Relative bit
=
Bit
~4~-----------------------------
1'- I
I
!:!l
0
I
fl is a non- zero
O~
Indirect bit is 0
The F field remains the same as in constant mode, that is, it signifies the type of
instruction within this class used. The relative bit and the indirect bit are also
O's for this class. However, ~ is non-zero (See Figure 12). It may have been
noticed now that this one-word type instruction has !:!l non- zero w her e the constant mode example had ~ as zero and was a two-word type. The actual value in
~ will be the absolute address. Notice the size of fl. It is only eight bits which
means that the range of n u m be r s in hexadecimal is from 01 to FF. In d~cimal
this gives a range from 1 to 255. This is the limitation on this mode of addressing.
Its advantage is its one-word length. To imp I e men t this absolute region from
core location 01 to FF, all operating systems for the 1700 deJine this area as being
the Communications Region. In this region are placed all system masks and all
references to other points in the system allowing quick access through this region
with this mode of addressing.
Example:
START
LDASTA-
$21
$EC
The contents of location 2116 in the absolute communications region is moved to
core location EC16. The minus sign as an opcode terminator signals the assembler to form a one-word instruction with the -!:!l field set to the address. The
example above generates two one-word instructions:
C021
60EC
Example:
=NO
$FF
LDA
STA-
f',
I
This e x amp I e clears index register I. Since I is core location $FF which is in
the communications region, all references to I will use a b sol ute one-word addressing.
.___.J
5-7
5. 1. 1. 2
The base address, for one-word absolute mode of addressing cannot be 0 since a
delta of 0 results in a two-word instruction at run time.
Example:
$4F-$50+1
LDA-
This results in base address of 0 which is an assembly error.
must be 01 to FF at run time.
The base address
5.1.1.3 Absolute: One Word Indirect
This mode of addressing is the indirect version of the a b sol ute one-word. Its
format, then, will be the same as for one-word a b sol ute; however, bit 10 (the
indirect bit) is set. Its base address, then, is not ~ but the contents of ~ and
further, if the high order bit of the contents of ~ is a 1 then the indirect search
will continue. This mode of addressing is extensively used where locations in the
communications region contain addresses of other programs. The reference to
these other programs is made by the use of the one-word absolute indirect mode
of addressing through the communications region.
Example:
Assume location E6 in the communications region always contains the
address of a desired routine. The routine can then be en t ere d by:
($E6)
JMP-
5. 1. 1.4 Absolute: Two Word
Since it is necessary to be able to absolutely address any core location from any
other core location, it takes a second word for the absolute mode of addressing to
specify the absolute address. The format for a b sol ute two-word mode of addressing is:
I( Iv lIB
P
P+l
Flo
IIIQ II
10
M
0
0
0
0
0
0
0
I
\.-Address Placed
in P+l
~----------------------------------------~
r==O
ind == 1
!::J. == 0016
Again, F will specify the particular instruction, ~ will be 0, the relative bit (bit
11) is 0, and the indirect bit (bit 10) is set. The second w 0 r d of the instruction
will contain the actual absolute address. Since the limit for allowable core in the
1700 is 32,767, only 15 of the 16 bits in the second word are u til i zed for this
absolute address. For absolute two-word bit #15 of the sec ond word will be o.
"'____,
5.1.1.4
Example:
COUNT
START
o
o
LDA+
COUNT
The + opcode terminator signals the ass em b 1 e r that the base address must be
placed in P+1. The base address, then, is (P+1). Notice (Figure 12) that this is
really the indirect case for constant mode.
The address COUNT is placed in the second word. If the assembler's program
counter for COUNT is at 0033, then at 0034 the assembler would generate:
C400
D033
START
STA+
$7F32-41
The address is calculated as 7F32 16 -29 16 or 7F09 and this address is placed in
the second word of the instruction:
6400
7F09
At START location
Example:
Cj
Add 1000 10 to the contents of core location 1000.
LDA+
$1000
ADD
=NI000
STA+
$1000
5.1.1.5 Absolute: Two Word Indirect
With indirect addressing the base address does not contain the operand itself, but
rather this base address contains the address of the operand. Notice from Figure 12 that two-word absolute is actually a case of constant mode indirect. Instead
of base address being P+1 as in constant mod e, the search is made into P+ 1 for
the base add res s. The indirect bit which is set for two-word absolute mode is
actually a case of constant mode indirect. Indirect addressing, however, can be
multi-level; that is the search may continue from address to address to find the
final base address. The continuation of this indirect search i~ accomplished each
time bit 15, the high order bit, of the base address is a 1 and the indirect bit (bit
10) is set. Using this high order bit of the address as an indirect flag is possible
since only the low order 15 bits of this address can contain another address. Since
the indirect bit is already set for the two-word absolute mode of addressing, the
use of parentheses in the address field for this mode of addressmg will cause bit
15 of the second word to be set. This forms two-word absolute indirect mode of
addressing.
Example:
TAG
START
Assume TAG contains 0400
LDA+
(TAG)
5-9
5.1.1.5
If TAG is at the absolute location 0301, this code is generated:
C400
8301
302
303
The high order bit of 303 is set. The contents of 303 is examined at run time and
since the high order bit is set, the search for a base address continues. The contents of 301 is brought out, and if the high order bit is a 1, the search would continue; in this case, however, the high order bit is a 0, so 400 is the base address.
The effect of this instruction, then, is to load A with the contents of 0400.
Example:
Assume the following values in core:
Core
Value
500
501
C400
400F
4010
3407
8501
COlO
If the contents of core location 500 were executed as the first word of a two-word
instruction, the computer would be in an endless loop searching for an address.
The instruction at core location 500 is:
($4010)
LDA+
Since this is two-word absolute indirect, the sea r c h continues to core location
4010 for an address. Bit 15 is set in core location 4010, so the search continues
to 501, then back to 4010, etc. This condition is catastrophic, of course, but it
illustrates the fact that the search for an address will continue until bit 15 is a 0;
then this cell contains the base address.
5.1.1.6 Relative: One Word
.~ There are two types of relocation associated with programs. One is called program reI 0 cat ion which means that the assembler begins the assembly with its
program counter equal to zero so that this program, when it is loaded into core
by the relocating linking loader, can be relocated anywhere. This program relocation is strictly a function of the assembler and the loader. This ability allows
the program to be loaded anywhere into the core and run. Once loaded, the ability
to take the same program and move it from one area of core to another and the
program still run, is not a function of the loader. This type of relocation is lmown
as dynamic relocation or "run anywhere". In process control programs, generally
many pro g ram s are put on a mass storage device with a common area of core
allotted for running these programs at any time. To allow pro per allocation of
this core area the programs on the mass storage device should be run anywhere
so they can fit into space available in the common area rather than in a particular
5-10
5. 1. 1.6
('
area of the common core. Achievement of run anywhere programs is the result
of the use of the relative mode of addressing in the 1700. For the one-word relative mode of addressing /:::,. will contain a signed increment that when added to P
will yield the base address. The base address is made relative to P or where the
program instruction presently is so that if the whole program is moved, the same
reI a t i v e distance is maintained between instructions I data and the base address
found in exactly the same manner, since P is variable. The format for the oneword relative commands is:
U
F
11 0 Q I
I
Contains signed 8-bit
increment
The limitation for this one-word relative mod e of addressing is the size of /:::,..
Since I::l is 8 bits and s igne d, the range from P is +7F to 80 (-7F), or ±127 10 •
Example:
LOOP
I • I!
Ii'"
--
JMP*
J
{
I
(J j
/
J
I
()
,1
i
LOOP
If the JMP instruction !s -12710 locations back or less, the one-word relative form
can be used (and is pre fer red). Assume the program counter is at 010016 for
LOOP and at 014316 for; the JMP instruction, then the JMP instruction decodes at:
Note: !J. is BC which is -4316 in 8 bits.
18BC
The * opcode terminator is used to sign if y to the assembler one-word relative
mode of addressing.
Example:
Consider the same bas i c structure but coded absolutely, then relatively. Assume the distance from LOOP to LAST is less than 127 10 •
a)
LOOP
LAST
b)
/"-"',
...... -.... ...
\,.
LOOP
JMP*
LOOP
LOOP
LAST
'\
JMP+
For a) above, the routine could not be moved to another core location once loaded
because with two-word absolute used with the JMP instruction, the absolute address placed in the second cell would cause a jump back to the original location
of LOOP. But in case b), the incremental difference placed in /:::,. for JMP* LOOP,
and since the distance between LOOP and LAST will not change if the whole routine
is moved, the program will jump to the new location of LOOP. b), then, is "run
anywhere" where a) is not.
,
,
5-11
f
5. 1. 1.7
5. 1. 1. 7 Relative: One Word Indirect
This mod e of addressing is an extension of the one-word relative to the indirect
mode; the relative bit is set, the indirect bit is set, and b. is non-zero (see Figure 12). With the base add res s found as in one-word relative (P+ b.) a further
search is made in this address location for the base address. The indirect bit is
set and the search will continue if the high order bit in the contents of P+ l:l contains a one.
Example:
Contains an addressAssume 0600.
ADDR
(ADDR)
JMP*
For this example ADDR must be within 12710 of the JMP instruction and ADDR
contains the address, 0600, to which control will pass. This r 0 u tin e jumps to
location 600 and continues program execution from there.
5.1.1. 8 Relative: Two Word
Two-word relative mode of addressing is used when the difference bet wee n the
instruction and the address is greater than the limitations imposed by one-word
relative, that is greater than :!:12710. Two words are necessary and in the second
word of the instruction is placed the difference between that word and the address.
The base address is then P+1+M where M is the contents of P+1.
.
Example:
LOOP
==)------------l~
.
Assume PC-0100
More than 12710
LOOP -----t~•.. Assume PC-0400
JMP
Two word relative mode of addressing is used here since the difference between
the JMP instruction and LOOP is greater than -7F. The above JMP LOOP would
decode as:
400401-
1800
FCFE
Notice that the difference between P+1 and LOOP is placed in P+1.
5-12
5. 1. 1. 9
5. 1. 1. 9 Relative: Two Word Indirect
This mode of addressing is the extension of the two-word relative to the indirect
mode; the relative bit is set, the indirect bit is set and ~ =00 since this is a twoword instruction. With the base address found as in two-word relative, a further
search is made in this address location for the base address. The base address
is then (P+l+M). The search will continue if the high order bit of the contents of
P+l +M contains a one since the indirect bit is set.
Example:
Contains an addressAssume 0600.
AD DR
JMP
(ADDR)
ADDR can be any distance from the JMP instruction and ADDR contains the address, 0600, to which control will pass.
5. 1. 1. 10 Review of Addressing Modes
o
A cross check back through Reference 1, Appendix A, page 3-4 will show that the
Computer Reference Manual describes the s tor age reference class as having 7
modes of add res sin g. A count from Figure 12 here shows 9 distinct modes of
addressing. Although a seeming conflict exists, there is really none. From the
viewpoint of basic machine language, there are only 7 modes since two-word
absolute indirect to the basic machine is nothing more than an extension of twoword absolute in the in d ire c t mode and both relative modes can be grouped together as one. When considering the manner in which the pro g ram mer must
specify the different modes to the assembler, there are 9 different combinations
as described. Some of the terminology also differs between this training manual
which essentially follows the terminology of the assembler manuals and the terminology used in the computer reference manual. The basic difference in terminology is:
S tor age Mode is the same as Two-Word Absolute
Absolute Mod e is the same as One-Word Absolute
Indirect is the same as One-Word Absolute Indirect
Relative Mode is the same as One-Word Relative
16- Bit Relative is the same as Two-Word Relative.
5.1.1.11 Indexing
Two index reg i s t e r s are available, the Q register and the I register which is
actually core location FF. The contents of these registers can be used to modify
the base address to form an effective address. This indexing, or address modification is a c com pi ish e d simply by adding the contents of the specified index
5-13
5.1.1.11
register (either Q or I or both) to the base address. If indirect add res sing is
s p e c if i ed, the search is made to find the final base address before indexing is
done. This simplified flow chart illustrates this:
Get
Base
Address
\~ ../
Get Contents
of Base Address
Yes
Add Q
to Base
Address
Add I to
Yes
)----tptBase Address
This is
J---.r---I. Effective
Address
The use of in d ex in g is wide- spread principally for forming repetitive loops for
the type of work that would otherwise require an inordinate amount of repetitive
programming.
Example:
Suppose the problem is to add together a series of numbers located in consecutive
memory locations 1000 thru 1002 and then store the result into a location called
TEMP. This routine would accomplish the additions:
TEMP
START
0
LDA+
ADD+
ADD+
STA*
0
$1000
$1001
$1002
TEMP
Reserve Temporary Location
If the series of numbers to be added was much longer, however, the length of the
program, due to the number of ADD instructions, would be prohibitive. The same
problem, with the numbers to be added in core 1000 thru 2000, ignoring overflow,
and with the instructions covered so far would be solved with an in de xed loop:
TEMP
START
LOOP
DONE
0
LDQ
LDA+
ADD+
ADQ
SQZ
JMP*
STA*
0
=X$2000-$1000
$1000
$1000,Q
=N-1
DONE~*-l
LOOP
TEMP
Reserve temporary loc.
Difference in Q
Decrease Q by i
Finished?
No
Yes
(
'I
"
5-14
5.1.1.11
Here, Q is set up as the index register used. The, Q in the address field signifies
Q register indexing, and the assembler will set bit 9 in this instruction word. Q
contains initially the difference between the lower and upper core locations of the
numbers to be added. For each pass through the loop, Q is decreased by 1 allowing
the next lower core location contents to be added in turn. The sequence of addition
is: (1000) from the LDA instruction, (2000) from B.A. * of 1000 +Q which is
initially 1000, (lFFF) from B. A. of 1000 +Q which is now 1 less or OFFF,
(lFFE)---, till (1001). When Q is decreased to 0, the SQZ instruction skips out
of the loop.
If Q were not available at this point in the program, I could be used:
TEMP
START
LOOP
~-~
,-.. ,
('--..-.-)
0
LDA
STALDA+
ADD+
STA*
LDAADD
STASAZ
LDA*
JMP*
0
=X$2000-$1000
$FF
$1000
$1000,1
TEMP
I
=N-1
I
ENDIT-*-1
TEMP
LOOP
Temporary storage
Index Register I
Can use either I or $FF
Result is in TEMP
ENDIT
The , I in the address field signifies to the assembler that I register indexing is to
be used and bit 8 in the machine language word is set.
I cannot be manipulated as easily as Q. TEMP is used to store the partial results
of the adds when the A register is used to manipulate the contents of the index
register I.
The ,B in the address field signifies to the assembler that both Q and I indexing
are to be used.
The use of Q as an in d e x register does not increase the execution time, but use
of I indexing takes 1.1 microseconds longer.
*Base address
5-15
5.1.1.11
.""
Addressing Problem
Given are contents of the index registers and some core I 0 cat ion s.
Contents of any locations not shown is zero. What will the A register
contain after each instruction is executed?
(1000)
(0240)
(1234)
(0260)
(1254)
(1111)
(1)=0020
(Q)=0120
=
=
=
=
=
=
.. ,~,
l,-" ,
0120
1234
02E:q
1111
2311
9000
(A)=
a.
b.
c.
d.
LDA+
LDA+
LDA+
LDA+
$240 .
($240)
($240), I
($1111),B
...........--,.
5-16
/~---\
\
(')
,---'
~
*
*
•*
•
...
*
-:]
~j
REFER~NCE
RIQI
F
DELTA
(P)=**** **** **** ****
~~~~
~""
~
*MNE**OPERATION*
JMP EFAr+P
MUI (EFA)X(A)r+QA
.. 3
DVI (QA)/(EFA),.A.REM,.Q
.. 4 STQ (Q),.EFA
... 5 RTJ P+lv~"EFA,EFA+lr+P
* 6 STA (A),.EFA
... 7 SPA (A)"EFA,PARITYr+A
ADD tA}+(EFl)'+-A
* 8 SUB
(A)-(EFA)r+A
* 9
... A AND (A)I\(EFA)r+A
* 8 EOR (A)""t-< EF A) r+A
.. C LOA (EFA)r+A
* 0 RAO (EFA)+!,.EFA
... E LDQ (EFA),.Q
... F
ADQ
(EFA)+(Q),.Q
.
++++ ++++,.,.
""""~"""""r+~~~~ ++"r+""""~"""
* 1
* 2
...
;
~
STORAGE
... 101
I
J-l
/--
'"
'0" =00
'"
+
0
4
4
4
8
8
C
C
'+0
"
+1
+2
+3
+
#'
...
...
...
M
(P+l)=**** **** **** ****
"MODE*
*SAO
*OP**ADR*
~
p+l
CONSTANT*
~OO ABSOLUTE
=00 STORAGE
DEL.TA
STORAGE INDTRECT
INDIRECT
=00 LONG RELATIvE
_00 RELATIVE
M
-+
=~O
(M)
+
~OO
(DELTA)
-=00 LONG REL14-TlvE INDtRFCT
RELATIVE INnIRECT
oEFA*
SA
~OO
SA+(I)
BA+(Q)
BA+(Q)+(I)
..
*
....
....
...
P+l+M
P+DELTA
(P·.l +M)
=
..
(P+DELTA)*
oC$
~
-(
)
(
)
*..-
..
*
*...
..-
...
..
·
·
·
01
J-l
J-l
J-l
J-l
5.1.2
5.1.2 Instructions in the Storage Reference Class
The instructions for the storage reference class are:
F
F
1
2
3
4
5
6
7
8
JMP
MUI
DVI
STQ
RTJ
STA
SPA
ADD
Jump
Multiply
Divide Integer
Store Q
Return Jump
Store A
Store A, Parity
to A
Add to A
A
B
SUB
AND
EOR
C
D
LDA
RAO
E
F
LDQ
ADQ
9
Subtract from A
AND with A
Exclusive OR
with A
Load A
Replace Add 1
in Storage
Load Q
Add to Q
Any of the nine addressing modes, plus indexing, can be used on all of these instructions.
5. 1. 2. 1 LDA, LDQ, STA, STQ, AND SPA Instructions
These instructions are the basic load and store instructions. For the load instructions, either LDA or LDQ, the contents of the effective address specified is loaded
into the registers, either A or Q, as per the specific instruction and the contents
of the storage I 0 cat ion are not altered. The STA and STQ registers store the
contents of the register into the effective address, replacing what was in this core
address with the information that was in the register. For the store instructions
STA and STQ, the original contents of the A or Q registers are not changed. The
SPA instruction is the same as the STA instruction with the exception that aft e r
the information from A is stored into the core address specified, A is cleared and
the parity of the original contents of A is returned to bit 0 of A. This parity bit
is the value that would be necessary to make the total number of bits of the original
contents of A plus this bit, odd. This par it Y bit is not necessarily the same as
the parity bit that will appear in core for this data word since core might contain
a program protect bit. In fact, this bit is the exclusive OR of the core parity bit
and program protect bit.
Any method of addressing may be used with these instructions.
Example:
Location
Opcode
Address
LDA
TAG
Comments
Contents of A is replaced by the contents of core location labeled TAG.
tents of TAG is not changed.
5-18
The con-
5.1.2.1
Location
Opcode
Address
SPA
TAG1
Comments
The contents of A (assume F2F7) is stored into the cor e location labeled TAG1.
Then A is cleared and the parity of the original contents of A is returned to A, bit
position O. The parity returned is 1.
5. 1.2. 2 ADD, ADQ, SUB, MUI and DVI Instructions
These instructions are the p rim a r y arithmetic instructions for the 1700. Data
from core can be add e d to the A register with the ADD instruction, or to the Q
reg i s t e r with the ADQ instruction. Data from core can be subtracted from the
A register with the SUB instruction. Notice there is no instruction for direct subtraction from Q. These a r it h met i c operations can cause overflow (refer to
Chapter II, Section 4).
Example:
Location
·'
C
Opcode
Address
LDQ
ADQ
TAG
=N-6
Comment
Using Constant mode of addressing for the ADQ produced an effective subtraction
from Q. Q is loaded with the contents of core location TAG and the number -6 is
added to Q.
"
j
The MUI instruction will multiply an operand in core by the contents of the A register. Both of these operands are 16 bits long, producing a double length, 32 bit
pro d u c t in the Q and A registers. The Q register contains the m?st significant
portion of the product and the sign of th~ product and the A register contains the
least significant portion of the product. The MUI instruction cannot cause overflow. The MUI instruction destroys the original contents of Q.
Example:
Location
Opcode
Address
Comment
LDA
MUI
=N$FF31
=N$31
-$CE to A register
Multiply by 31
Result is (Q register)=FFFF
(A register)=D891
The result in the double length register then is -276E 16 •
Negative zero can be produced by the MUI instruction:
c.
(+0) X
(- N) x
(-0) x
(+N) x
(- N)
= (-0)
(+0) = (-0)
(+N) = (-0)
(-0) = (-0)
5-19
5.1.2.2
Division of integers is a c com pi ish e d with the DVI instruction. It divides the
double length QA register by the contents of a core location. The Q register must
contain the most significant portion and the sign of the dividend and A must contain
the least significant portion of the dividend. The signed quotient will be placed in
the A register and the signed rem a in de r will be placed in the Q register after
division occurs. The DVI instruction can cause overflow, if the quotient is larger
than 7 FFF in absolute value.
Example:
Location
Opcode
Address
Comment
LDQ
LDA
DVI
=N$FFFF
=N$FFFO
=N$FFFA
=N in address field indicates CONSTANT MODE
OF ADDRESSING used.
The number following =N
is the operand.
This example divides -15 by -5. Notice that Q had to be set to extend the sign to
32 bits. Result is 0003 in A and 0000 in Q•.
5.1.2.3 AND and EOR Instructions
These instructions perform logical manipulation of data from the specified core
location with the contents of the Are g is t e r. The AND instruction performs a
logical product operation; its bit by bit truth table is:
-A
1
1
0
0
-B
A/\B
1
0
0
0
1
0
1
0
Example:
Operand 1--
Bit
15
0
1111 0010 1001 0111
Operand 2 --
0011 1111 1100 0000
Logical Product
0011 0010 1000 0000
The AND instruction is used to extract a certain field of bits. In the e x amp I e
above, a field from bit 6 through 13 is extracted from operand 1. Operand 2 contains ones in these bit positions and O's in the remaining bit positions to block out
the unwanted bits. Operand 2 is referred to as a mask.
5-20
i-------
5.1.2.3
Example:
Examine bits 4 thru 7 of core location TAG for all zeroes.
Location
Opcode
Address
Comment
LDA
AND
SAZ
JMP
TAG
=N$OOFO
YES-*-1
NO
Load (TAG) in A register
AND with A Mask
Test for zeroes
YES
The EOR logical instruction performs an ex c 1 u s i ve OR bit by bit.
rules for an exclusive OR are:
A
1
1
0
0
B
1
0
1
0
The logical
A-¥B
0
1
1
0
-
A 0 is produced as a result of a match between the two bits and a 1 is produced as
a result of a mismatch. This instruction is frequently used to test for a particular
bit pattern.
Example:
Test for 10110 in bit positions 3 thru 7 of contents of core 10 cat ion
DATA.
Location
Opcode
Address
Comments
LDA
AND
EOR
SAZ
DATA
=N$00F8
=N$OOBO
YES-*-1
Mask out all except 3-7.
Test for bits 10110
YES
If the exact bit pattern 10110 was present in bit positions 3 through 7, all the bits
in both operands would match, and a positive zero will be in the A register and the
program will skip to YE S.
An instruction that performs an inclusive OR is not specifically available in the
storage reference class. The truth table for the inclusive OR is:
A
1
1
B
1
AVB
1
o
1
o
o
1
1
o
o
A 1 is produced if a 1 appears in either or both operands. Notice that the inclusive OR logical function can be obtained by the combination of the logical product
and exclusive OR functions.
5-21
5.1.2.3
Example:
Form the inclusive OR bit-by-bit of the contents of core location AA
and BB.
Location
Opcode
Address
Comment
TEMP
0
LDA
AND
STA
LDA
EOR
ADD
0
AA
BB
TEMP
AA
BB
TEMP
Logical Product AA & BB
Store Temporarily
Exclusive OR AA & BB
Combine them. Inclusive
OR is now in A.
5.1.2.4 JMP and RTJ Instructions
These instructions alter the path of program flow. JMP is an unconditional program branch to the effective address. The RTJ, besides branching control to
another core location, also provides the link by which control can be returned to
the instruction following the R T J instruction. This allows program flow from a
main program to a closed subroutine and back again to the main program. This
is illustrated below:
Main
Program
Address
,""'-- P
Main Program
__---A'---_~
I
Effective
RTJ Address
=0025 16
\
Subroutine
I
P+1
I
~00f5
1
A
\
Computer
stores P+ 1 or
P+2 here
,2
I
1st Instruction
of
Subroutine
~P+2
I
I
5
I
!3
•
Next to Last
Instruction
of Subroutine
6
4
Indirect
JMP Address
=0025 16
I
5-22
5.1.2.4
The subroutine is structured with its first location left open to allow the address
(P+l or P+2) to be placed by the RTJ instruction. Program control is then given
to the second cell of the subroutine. By using a jump indirect through the first cell
as the last instruction in the subroutine, program control will be given to the next
executable instruction following the RT J in the main program. This flow is independent of the location of the R T J instruction.
Example:
Comment
Location
Opcode
Address
LOOP
LDA
TEN
JMP
LOOP
Simply jumps back to location LOOP
BACK
RTJ
BACKI
Sets BACK+2 into BACKI
since mode of addressing
is 2 word.
BACKl
0
0
Address BACK+2 is placed
here.
JMP
(BACKl)
Will jump not to location
B A C K 1, but to location
whose address is inBACKl
which is BACK+2.
0
To specify indirect mode of addressing the address is placed in parentheses as in
the above example. This means that the specified address (in this case, BACKl)
itself contains the address that is desired. More will be said on addressing later.
5. 1.2. 5 RAO Instructions
This RAO instruction is used to inqrease the contents of the effective address by
1. This instruction is very useful as a counter where a memory location is initialized or preset and the RAO instruction increases the count in this memory cell
each time a desired condition occurs (number of times through a loop, etc.).
(~
..
\ .....~..,'
I
...
5-23
i
5.1.2.5
Example:
Location
Opcode
Address
COUNT
o
o
LOOP
LDA
TEST,Q
SAZ
2
JMP
LOOP
COUNT
LOOP
RAO
JMP
Comment
Skips to RAO COUNT if A
is zero,
In this example the contents of core location COUNT is increased by 1 each time
the A register is found to be zero. This RAO (Replace and Add One) instruction
can only add one to the contents of the designated core location and does not change
the contents of any of the registers. This instruction can cause overflow and, as
such, is very useful for loop control.
Example:
Location
Loop through a given portion of a program 12 times then jump to core
location NEXT. It is necessary to preset a COUNT cell such that increasing it by 1 will not cause overflow until it has been increased 12
times. The largest po sit i v e number minus 11 then is preset into
COUNT.
Opcode
Address
Comment
SOY
LDA
STA
0
Turn off overflow if set
=X$7FFF-l1
COUNT
LOOP
RAO
SOY
COUNT
JMP
COUNT
NEXT-*-1
LOOP
o
o
NEXT
Overflow will occur the 12th time the RAO instruction is performed.
5-24
5.1.3
5. 1. 3 Execution Times
EXECUTION TIlVIE
(microseconds) *
INSTRUCTION
LDA
STA
LDQ
STQ
ADD
SUB
ADQ
AND
EOR
RAO
MUI
JMP
RTJ
DVI
SPA
o
Load A
Store A
Load Q
Store Q
Add A
Subtract
Add Q
AND with A
Exclusive OR with A
Replace Add One in Storage
Multiply Integer
Jump
Return Jump
Divide Integer
Store A, Parity to A
Timings are for one-word instructions.
two-word instruction.
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
3.3
7.0
1.1
2.2
9.0
2.2
An additional cycle must be added for a
Note the speed of the integer multiply and divide instructions.
sidered very fast for the computer hardware.
*Add 1. 1 microsecond
if Storage Index Register is used.
Add 1. 1 microsecond for each level of Indirect Addressing.
r--.,
/
\..-..
\
-,:)
5-25
These are con-
c.n
I----l
SKIPS
*
*
F=O
Fl=l
*
(P)=* * * *
****
I
t\:)
0")
SKIP COUNT
~~~~r~~~~~~~~~~~~~~~~~~~
*
+
*
*
~
ARITHMETIC TESTS
t
*
**** ****
*
*
c.n
F2
*
*TEST*
~
MACHINE STATE TESTS
*
*TEST*
*
*
0
SAZ
(A)=ZERO
8
SWS
SKIP SWITCH ON
*
*
1
SAN
(A)rfZERO
9
SWN
SKIP SWITCH OFF
*
*
2
SAP
(A)=POSITIVE
A
SOY
OVERFLOW
*
*
3
SAM
(A)=NEGATIVE
B
SNO
NOT OVERFLOW
*
*
4
SQZ
(Q)=ZERO
C
SPE
PARITY ERROR
*
*
5
SQN
(Q)rfZERO
D
SNP
NOT PARITY ERROR
*
*
6
SQP
(Q) =POSITIVE
E
SPF
PROTECT FAULT
*
*
7
SQM
(Q)=NEGATIVE
F
SNF
NOT PROTECT FAULT
*
*
--)'
*
i
-)
-(
""
5.2
5.2 SKIP CLASS INSTRUCTIONS
--/.
These instructions are used to make conditional tests and skip forward depending on
whether the instruction meets the actual condition being tested. The format for these instructions appears below:
15
12
l
o0
0 0
v
F
11
'I,
8
7
I
o0
0 1
v
Instruction
F1
"
5
6
I
\
v
I
4
I
Sub- Instruction
F2
0
3
I
"
l
Skip 'tount
Notice the skip count is only four bits which allow s a skip count of only 15. The skip
count is not signed so the instructions will only allow a skip in the forward d ire c t ion.
If the skip condition is met, program control proceeds to P + 1 + skip_ count.
If the skip
condition is not met, program control continues from P+1.
5.2.1 A and Q Skip Tests
The following types of con d it ion a 1 tests are available on the A and Q register:
.,.--;..,~
F2'
0
1
2
3
4
5
6
7
0000
0001
0010
0011
0100
0101
0110
0111
SAZ
SAN
SAP
SAM
SQZ
SQN
SQP
SQM
A=+O
Arf+O
A= +
A= Q=+O
Qrf+O
Q= +
Q=-
Example:
Location
Opcode
Address
Comments
START
LDA
ARS
SAZ
ARS
SAZ
=N$0080
4
1
4
TAGl-*-l
Loads 0080 into A
TAG
1 is the Skip Count
will not skip to TAG
will skip to TAG1
TAG1
The TAG1-*-1 address is a form peculiar only to the utility assembler. With this
form the assembler is being d ire c ted to form a skip count to TAG1, which has
some program counter value. This counter value, minus the current location of
5-27
"'-
5.2.1
tithe SAZ instructions (which is some program counter value less than TAG1), minus
one more, forms the skip count. The -1 is used to compensate for the +1 in the
skip formula P+1+skip count. When using the macro assembler, the address need
only be TAG! as the macro assembler will automatically calculate the skip count.
For all cases the distance skipped (to TAG1 in this example) must be no greater
than 16 lo cat ion s forward from the location of the skip command. The macro
assembler will also accept the -*-1 form.
5.2. 2 Skip Switch Tests
The SWS and SWN instructions test the condition of the skip switch located on the
programmer t s panel. This switch can be used to alter pro g ram flow from the
panel.
Example: .
Opcode
Address
TAG
SWS
GO-*-l
GO
TAG1
SWN
G01-*-1
Location
Comments
START
G01
The code bet wee n TAG and GO will be skipped at run time if the skip switch on
the programmer's panel is set. It would be executed if the switch were not set.
The code between TAG! and G01 will be skip p e d if the skip switch on the programmer's panel is not set. It will not be skipped if the switch is set.
5.2.3 Overflow Skip Tests
The SOV (F2=A) and SNO (F2=B) instructions test the state of the overflow indicator. Ref e r to Chapter II, Section 4, for a dis c u s s ion of those arithmetic
operations causing overflow. The overflow indicator is cleared up o~ execution
of these instructions.
5-28
\.......
5.2.3
j
Example:
Location
Opcode
Address
START
LDA
ADD
SNO
OPl
OP2
TAG-*-l
ADD
SOV
JMP
OP3
ERROR-*-l
OK
Comments
CORR
TAG
ERROR
OPl
OP2
OP3
OK
CJ
In the above e x amp 1 e, two numbers are added and if no overflow occurred, the
instructions between CORR and TAG will be skipped and a third n u m b e r will be
added. The overflow in die a tor is again checked and if overflow had occurred,
the routine would skip to ERROR. The overflow indicator once set, remains set
until tested with either an SOV or SNO instruction.
5.2.4 Parity and Program Protect Indicator Tests
The SPE (F2=C) and SNP (F2=D) instructions will test for a storage parity error
and the SPF (F2=E) and SNF (F2=F) instructions will test for pro g ram protect
fault errors.
Example:
Location
Ope ode
Address
START
SPE
SPF
JMP
JMP
JMP
PAR-*-l
PROT-*-l
ERROR
PARITY
PROTEK
PAR
PROT
Comments
If either a parity error or a program protect fault occurs, an interrupt is generated
on line o. Since both interrupts can 0 c cur on the same line, the interrupt pro- cessor for this line must distinguish between the two. This example illustrates
how this might be done with program control going to the location named PARITY
5-29
5.2.4
if a par it Y error is found, and program control jumping to core location named
PROTEKli the protection fault caused the interrupt. Ifneither interrupt was found
by this process, program control would jump to some error routine to service what
is apparently a ghost interrupt. The parity and protect indicators (both the interrupt signal and the programmer's panel fault indicators) will clear when these instructions are executed.
Problem:
MOVE
LP1
Problem:
SUM
LOOP
DONE
Problem:
CHNG
LP2
ADDRI
ADDR
The following routine will move how many numbers? From what core
locations to what core locations?
0
LDQ
LDA+
STA+
ADQ
SQM
JMP*
JMP*
0
=N$1000
$1000,Q
$3000, Q
=N-1
1
LPI
(MOVE)
The follow in g routine sums how many numbers?
locations? Where does it store the answer?
LDQ
LDA
ADD+
ADQ
SQM
JMP*
STA+
From what core
=X$2000-$1000
=N$
$1000, Q
=N-l
DONE-*-l
LOOP
$3000
The following routine moves how man y numbers? From which core
locations to where?
0
0
LDA
=N$1000
ADDR1
STA*
LDA
=N$4000
STA*
ADDR
LDA+
(ADDR1)
LDQ+
(ADDR)
STA+
(ADDR)
STQ+
(ADDR1)
ADDR1
RAO*
LDA*
AD DR
SUB
=Nl
STA*
ADDR
SUB
=N$3000
SAM
3
JMP*
LP2
0
0
0
0
(CHNG)
JMP*
5-30
~
('\
I
n
()
,
01
I
~
~
--_/
\-
"--- -
*
*
*
*
*
*
*
*
*
*
*
*
SHIFTS
rrSHIFT A
SHIFT
F=O
(P) =*
** *
LEFTr,+rSHIFT Q
Fl=F
+++
* * ** * **
~~~~rttr~~r~~r~r~~~~~~~~+H
* ** **
~~t~
RIGHT SHIFTS
t
DELAY
4
ARS
(A) RIGHT
8
Nap 1.1+SHIFT COUNT(.l)
(Q) LEFT
2
QRS
(Q) RIGHT
*
(QA)LEFT
6
LRS
(QA) RIGHT
*
*
*
+
LEFT SHIFTS
C
ALS
(A) LEFT
A
QLS
E
LLS
t
SHIFT COUNT
*
*
*
*
*
*
*
*
01
t..:>
t+;:..
5.3
5.3 SHIFT CLASS INSTRUCTIONS
These instructions are used to shift the data bit by bit either in the A register or the Q
register singly or together. The data can be shifted either left or right bit by bit. For
these instructions the format appears below:
15
I
12
11
F=O
8
1111
0 0 0 0
F1=F
7
I
6
I
5
I
4
I
\
l=shlltleft __________________________
O=shift right
3
0
I
V
1
I
C/
Shift Count
~
1 =shift A -------------------------'
l=shift Q - - - - -_ _ _ _ _ _ _ _
--1
Notice the shift count is five bits allowing a shift either way a maximum of 31 positions.
The upper bit of the shift count will a p pea r in the hex code as part of the second digit.
For example, a OF51 is an ARS %,(linstruction, not ARS 1.
Left shifts are end around: the high order hit of the register is shifted around and into
the low order bit of that register for single register shifts. For a double register shift,
(Long Shift), the Q register is considered the most significant register and the A register
the least significant register and on left shift s the high order bit of Q is shifted around
into the low order bit of A. High bit of A is shifted left into the low order hit of Q.
Right shifts are end off with sign extension. Bits shifted off the right end are lost, and
the sign bit of the register is extended from the left., For long right shifts, the low bit
(Bit 0) of Q is shifted into the high bit (Bit 15) of A arid the sign (Bit 15) of Q is extended
from the left.
.
The mnemonics for the instructions in this class are:
ARS
QRS
LRS
ALS
QLS
LLS
A Right· Shift
Q Right Shift
Long Right Shift (QA)
A Left Shift
Q Left Shift
Long Left Shift (QA)
5-32
5.3
u
Example:
Location
Opcode
Comments
Address
I
I
ALS
8
If the A register contained F302, execution of this instruction would
shift the A register left 8 bits leaving 02F3. The high order bits of A
moved end around intoI the low order bits of A.
I
I
I
LRS
8
If Q=8000 and A=AOFO, execution of this instruction extends the sign
of Q to the right and the lower 8 bits of A would shift end off and be
lost. Result is FF80 I in Q, and OOAO ?-n A.
5.3. 1
I
I
Illegal
LLS
40
J
I
Legal
QRS
I
I
0
I
I
I
J
Maximum number of shifts
allowed is 31,
Is effectively a no operation
Timing for Shift Class Instructions
The time for shift class instruction execution is:
o
I
For long shifts (QA together) 1. 1 + • 2 x shift count
For single register shifts (Q or A) 1. 1 + • 1 x shift count
(--'1,
l .•....,'
5-33
INTERREGISTER
*
F=O
(P)=* * * *
*
*
Fl=8
PR AQM AQM
*
****
**
ADDER CONTROLS ~
*
*
*
*
*
*
*
*
01
•
~
~
I +++
***
*
"+ ~~ DESTINATION REGISTERS
*
'"
~~RIGIN REGISTERS
*
'"
~OPERAND
*
TWO
*
*
*
SUM
TRANSFER COMPLIMENT
40
CLR
Or--A,Q,M
80
SET
-O~A,Q,M
30
AAQ
(A)+(Q)~A, Q, M
AO
TRA
(A)~A,Q,M
60
TCA
(A) NOT r--A , Q, M
28
AAM
(A)+(M)
*
90
TRQ
(Q)~A,Q,M
50
TCQ
(Q)NOT ~A, Q, M
38
AAB
B+(A) ~A, Q, M
*
*
*
*
*
*
*
*
88
TRM
(M)r--A, Q, M
48
TCM (M)NdT~A,Q,M
98
TRB
B~A,Q,M
58
TCB B NOT~A,Q,M
*
/l
***
+~"'OPERAND ONE
TRANSFER
LOGICAL AND
EXCLUSIVE OR
~A,
*
Q, M
*
*
*
*
*
*
COMPLIMENT LOGICAL AND
70
EAQ
(A).3o'-(Q) ~A, Q, M
BO
LAQ
(A)/\(Q)~A,Q,M
FO
CAQ
«A) /\ (Q»NOT~A, Q, M
68
EAM
(A)~(M)~A,
A8
LAM (A)/\(M)~A,Q,M
E8
CAM
«A)/\ (M»NOT~A, Q, M
78
EAB
B-'7"(A) ~A, Q, M
B8
LAB
F8
CAB
(B/\ (A) )NOT~A, Q, M
Q, M
B/\ (A)r*'A, Q, M
*
*
*
B=INCLUSIVE OR OF (M}AND(Q).
(~)
.
01
.
c:...:>
LX
*
*
*
("1
,
I-'
5.4
l''--
5.4 INTERREGISTER CLASS INSTRUCTIONS
./
This class of instructions performs arithmetic or logical manipulation with the contents
of A, Q or M or any combination of the three. The format for this class of instruction is:
Operand 1
Adder Control Lines ...41------.
I
15
12
11
8
7
L
P
Fl=8
F=O
~
+
Logical Product --------'
6
X
R
1
Exclusive OR - - - - - - - - - - '
~and2
+
5
4
3
Origin
Registers
2
1
o
Destination
Registers
Since the adder can operate on only two 0 per and s and there are three possible origin
registers, these three origin registers are considered as two operands, operand 1 and
operand 2. Operand 1 includes bit 5 or the Are g i s t e r bit and it can have two forms:
Operand 1
A (Bits)
o
FFFF
Contents of A
1
If this bit 5 is a· 0, then all l' s are used as an operand and if bit 5 is a 1, then the contents
of A is an operand.
Operand 2 is the combination of bits 3 and 4 or the combination of the Q and M register
bits:
Q (Bit
0
0
1
1
4)
M (Bit 3)
0
1
0
1
Operand 2
FFFF
(M)
(Q)
Inclusive OR of Q & M
If neither of these registers is specified, then all l' s are used as the operand. If anyone
but not the other is specified, then the contents of that specified register is used. If both
Q and M are specified, then the inclusive OR of Q and M is used as Operand 2. The bit
by bit truth table for the inclusive OR is:
A
B
AVB
1
1
1
1
o
o
o
1
1
1
o
o
Here a bit in either position yields a bit in the result.
5-35
5.4
/
Either A, Q or M,or any combination of these can be specified as the destination registers. These are listed in any order and s epa rat e d by commas in the address field.
Since M is the interrupt mask register, the interregister instruction with M as a destination register must itself be protected if the protect switch on the programmer's panel
is on. Otherwise, a protect fault will occur.
Formation of the operation itself comes fro m bits 6 and 7 of the instruction word.
operations possible are:
XR (Bit 6)
LP (Bit 7)
1
1
1
1
Operation
Arithmetic Sum
Exclusive OR
Logical Product
Complement Logical Product
0
0
0
The
0
Refer back to Section 5.1.2. 3 of this chapter for the truth tab I e s of the logical product
and the exclusive OR. All the possible combinations of different instructions in this class
using these two operands number 22. The mnemonics assigned with the instructions in
this class are:
SET
CLR
TRA
TRM
TRQ
TRB
TCA
TCM
TCQ
TCB
AAM
AAQ
AAB
EAM
EAQ
EAB
LAM
LAQ
LAB
CAM
CAQ
CAB
Set to l's
Clear to "0"
Transfer A
Transfer M
Transfer Q
Transfer Q V M
Transfer Complement A
Transfer Complement M
Transfer Complement Q
Transfer Complement Q V M
Transfer Arithmetic Sum A, M
Transfer Arithmetic Sum A, Q
Transfer Arithmetic Sum A, QV M
Transfer Exclusive OR A, M
Transfer Exclusive OR A, Q
Transfer Exclusive OR A, Q V M
Transfer Logical Product A, M
Transfer Logical Product A, Q
Transfer Logical Product A, Q VM
Transfer Complement Logical Product A, M
Transfer Complement Logical Product A, Q
Transfer Complement Logical Product A, Q V M
5-36
-
,
\ ....... - .. ~,
5.4
Examples:
LDA
CLR
CLR
AAQ
TCA
TRA
SET
AAQ
=NO
Clears A
So does this
Clears A, Q and M
Adds A to Q, puts result in A
Puts complement of A into Q
Transfers A to Q and M
Set M to all l's
Only affects overflow indicator-adds A and Q, puts result nowhere
A
A,Q,M
A
Q
Q,M
M
o
Problem:
The following is an example of how a subroutine can pick up parameters from the calling
r 0 uti n e. How does the subroutine pick up the parameters? Does it pick up the actual
argument or the address of the argument?
Calling Program:
C-")
-'
$500
1
=XX
LDA
STA
LDA
STA
LDA
STA
ARG3
RTJ
SUB
o (l~.,)
o
$502
ARGI
0'
$503
ARG2
0
ARGI
=XY
ARG2
=xz
{'p\
r';!r
Address of Z
X
NUM
f
10
X data
$701
Y
NUM
12
Y data
$702
Z
NUM
6
Z data
ARG3
0
$700
Addresses of parameters fall directly beneath the call to the subroutine.
'
.
Address of Y
O'Y"
$504
f
"~ •..
Address of X
/
5-37
5.4
Subroutine:
('
"
SUB
'---'
0
0
STA*
SAVEA+l
STQ*
SAVEQ+l
LDA-
$FF
STA*
SAVEI+l
LDA*
SUB
EOR
=N$8000
STA*
SUB
LDA*
(SUB)
STA*
SUBAGI \'::,
RAO*
SUB
LDA*
(SUB)
STA*
SUBAG2 ' :-'J
RAO*
SUB
LDA*
(SUB)
STA*
SUBAG3
(-"
~
SUB
'LDA*
INA
I
AND
=N$7FFF.
STA*
SUB
LDA
=NO
STA-
$FF
SAVEQ
LDQ
=NO
SAVE A
LDA
=NO
JMP*
(SUB)
SUBAGI
BSS
SUBAGl(l)
SUBAG2
BSS
SUBAG2(1)
SUBAG3
BSS
SUBAG3(1)
SAVEl
t
f
('
5-38
5.4
~
.~
U
Problem:
How many numbers does the following r
locations?
SORT
BEGIN
TEMP
0
CHECK
EXIT
0
uti n e sort?
CLR
A
STA-
$FF
ENQ
1
LDA+
$500, Q
SUB+
$500, I
SAP
CHECK-*-l
LDA+
$500, Q
STA*
TEMP+l
LDA+
$500,1
STA+
$500, Q
LDA
=NO
STA+
$500,1
INQ
1
TRQ
A
EOR
=N$lO
SAZ
1
JMP*
BEGIN
LDA-
$FF
INA
1
STA-
$FF
EOR
=N$F
SAZ
EXIT-*-l
ENQ
1
ADQ-
$FF
JMP*
BEGIN
SLS
,..-,~
I
In what order?
I
\ . ___ .i
5-39
From what core
.
C1
~
REGISTER REFERENCE
*
F70
Fl
DELTA
*
(P)= * * * * * * * * * * * * * * * *
*
* ,....r--~~~~r--~~~r--r-- r--~~•• t+ "~~ ~ ~r+~~r-* t ARITHMETIC
t INTERRUPT
t PROTECT
~
/)
!
*
I/O
A
ENA _ +-DELTA
A
t4
EIN* ENABLE
•7
CPB
CLEAR
2
INP
*
*
*
*
C
ENQ ' +-DELTA
Q
5
lIN
6
SPB
SET
3
OUT
9
INA
+-DELTA+(A) ~A
E
EXI*EXIT
0
SLS
SELECTIVE STOP
D
INQ
+-DE LT A+(Q)r-"Q
B
NOP
INHIBIT
('\
"
r-A
*
*
*
(A)~I/O
*
+
*ONE INSTRUCTION DELAY
*
0
*
*
*
* t
I
*
I/O
*
*
*
*
(-,
5.5
G
"r ...•
5.5 REGISTER REFERENCE CLASS INSTRUCTIONS
All the instructions in the class are one-word. The F field is always a zero and the Fl
field will signify the particular instruction within this class. The format for the Register
Reference Class of instructions is:
Fl
+
Instruction
Code ---.J
The instructions within this class are:
Fl
0
1
2
3
4
5
6
7
8
9
o
A
B
C
D
E
F
SLS
INP
OUT
EIN
lIN
SPB
CPB
INA
ENA
NOP
ENQ
INQ
EXI
Selective Stop
SKIPS
Input to A
Output from A
Enable Interrupt
Inhibit Interrupt
Set Program Protect
Clear Program Protect
INTERREGISTER
Increase A
Enter A
No operation
Enter Q
Increase Q
Exit Interrupt State
SHIFTS
The 11 field is available in this class of instructions.
5.5. 1
Instructions ENA, INA, ENQ and INQ
These four instructions are used to e it her enter into or increase the A register
or the Q register by the value in fl. This val u e is signed allowing numbers of
the magnitude plus or minus 127.
Example:
LDA
ENA
SUB
INA
=N22
22
=N$1
-1
,f)
\.. .. /
5-41
Loads A with 1616
So does this
Decreases A by 1
So does this
5.5.1
Where applicable, these instructions should be used in place of storage reference
class with con s tan t mode as these take only one word and 1. 1 microseconds to
execute.
The value in the address field is p I ace d into D. by the assembler.
machine instruction equivalent is OA16.
\
'--.
The ENA 22
5. 5. 2 Instructions SPB and CPB
These. instructions are used to either set or clear the protect bit (Bit 17) in memory. For these instructions f:j, is not used. The address of the core lo cat ion
which will have its protect bit either set or cleared must be in the Q register. If
the program protect switch on the programmer panel is on, then these instructions
must be protected. Otherwise, a program protect fault (interrupt on line 0, protectfault indicator on panel) will occur and these instructions become no operations.
Example:
Clear the protect bits in core from 1000 to 2000.
TEMP
START
LOOP
0
LDQ
CPB
INQ
STQ*
ADQ
SQZ
LDQ*
JMP*
0
=N$1000
Address is in Q
1
TEMP
=N-$2000
DONE-*-l
TEMP
LOOP
DONE
Finished?
No
('
I.
.........
.,,;'
Yes
This particular routine is further simplified with the use of interregister c las s
instructions.
Problem:
The CLRPB subroutine clears protect bits on what core area?
Calling Program
LWA
FWA
RTJ
NUM
NUM
CLRPB
$4000
$2000
\
". ../
5-42
5.5.2
G
Subroutine
CLRPB
LOOP
DONE
TEMPQ
TEMPA
5.5.3
o
0
STQ*
STA*
LDA
SUB*
RAO*
LDQ*
SOY
CPB
INQ
AAQ
SOY
JMP*
RAO*
LDQ
LDA
JMP*
0
TEMPQ+l
TEMPA+l
=X$7FFF
(CLRPB)
CLRPB
(CLRPB)
0
//
/
/
/
1
0
DONE-*-l
LOOP
CLRPB
=NO
=NO
(CLRPB)
Instructions EIN and IIN
These instructions are used to either en a b 1 e the interrupt system or inhibit the
interrupt -s y s t em. If the program protect switch on the programmer's panel is
on, these instructions must be protected. Othe rw is e, a protect violation will
occur. The interrupt system is inhibited immediately upon execution of the IIN
in s t r u c t ion. However, for the EIN instruction one free instruction is allowed
before the interrupt system becomes enabled.
Example:
MAIN
RTJ
SUB
SUB
o
o
Interrupt System inhibited
IIN
EIN
JMP*
(SUB)
This instruction is free.
This subroutine will operate on any level without interference from any other level
since the whole subroutine functions with the in t err up t system off. Control is
returned to the main program -before the interrupt system is activated through
use of the one free instruction following the EIN.
n
'--_.-
5-43
5.5.3
For example, if an internal interrupt occurred on line 0, P and the overflow indicator of1 the inte$rrupted progra m wlOdUld havbe been saved in word 0 of thle trap for
l ine 0 (ocation 100). Control wou have een transferred to word 1 ( 0 cat ion
$101). If word 1 contained a jump tothe Internal Interrupt Processor, that routine
would be executed. It would determine the cause of interrupt (program pro t e c t
violation or parity error) by using the appropriate instructions (skips). Then the
routine could exit back to the interrupted program. It would do that by:
,--....
lo-
00
EXI
The delta in the EXI instruction should be the lower 8 bits of the word 0 trap location for the appropriate line. In this case, the 00 means the trap for line 0, at
address $100.
$104
jump to proc.
a
$100
•
...
v
>
P
."
line 0
exit through here
The EXI instruction (Exit Interrupt State) is use d to exit from an interrupt subroutine. It restores the overflow indicator to its previous state, resets P of the
interrupted program, and enables the interrupt system.
5.5.4 Instructions INP and OUT
The INP and OUT instructions are used for all input and output operations on the
1700. They are used to input or output data to or from the A register. They output function codes to the peripheral equipment from the A register, and they input
s tat us conditions of the equipment to the A register. The Q register is used to
address the desired equipment. A brief introduction to I/O using these instructions
is contained in Chapter 7.
5.5.5
Instructions SLS and Nap
The SLS or selective stop ins t r u c t ion is dependent upon the positioning of the
selective stop switch on the programmer's panel. If the selective stop switch is
up, then the program will stop on this instruction. If the selective stop switch is
not up, then this instruction is the sam e as a Nap or No Operation Instruction,
where the computer simply steps past this instruction without performing any operation. If the computer stops, program execution will continue by momentarily
setting the RUN-STEP switch on the programmer's panel to the RUN pos ition.
('
"
5-44
•••
0
5.5.5
Example:
START
=N$1000
LDA
NOP
NOP
Put in for future expansion
"
Program stops i~ stop
switch is up
Continues when run switch
is hit or if stop switch
is not up.
SLS
Problem:
The following is a conversion routine which converts a positive or negative hexadecimal number in the A register to the ASCII codes for the decimal number. It
consists of a CONVRT subroutine and a main program CONTST which was used to
check it out.
Study the program carefully, see how the conversion is done and how the parameters are passed.
o
This should be considered a final examination over the 1700 instructions and their
use.
5-45
5.5.5
0001
0002 POOOO
POOOI
POO02
0003 POO03
0004 POO06
0005 POOOC
POOOO
0006 POOOE
POOOF
POOIO
POOll
POOl2
POOl3
POO14
POOlS
POOl6
POO17
0007
0008 POO18
0002 POO19
0010 POOIA
0011 POOIB
0012 POOIC
0013 POOlO
0014 POOlE
0015 POOlF
0016 P0020
0017 P0021
0018 P0022
0019 P0023
0020 P0024
0021 P0025
P0026
0022 P0027
0023 P0028
0024 P0029
0025 P002A
0026 P002B
0027 P002C
0028 P0020
P002E
0029 P002F
0030 P0030
0031 P0031
0032 P0032
0033 P0033
0034 P0034
0035 P0035
0036 P0036
0037 P0037
0038 P0038
0039 P0039
0040 P003A
0041 P003B
0001
0001
0001
0003
0006
002B
0020
0030
0031
0032
0033
0034
0035
0036
0037
0038
0039
0000
48E6
EOFF
48E5
0842
40FF
0122
0001
0864
EAEA
48E8
E8EA
48El
EOOO
0020
480F
480F
480F
480F
0842
0106
3000
OOOA
EAOE
4905
OOFF
l8F8
40FF
OC05
CADO
OFC8
OOFE
8ACO
69C9
DOFF
OOFe:
BUF
BUFI
SIGN
NAM
BSS
CONVRT
SAVEQ(}}.SAVEI(l).SAVEA(l)
BSS
BSS
NUM
BUF(3)
BUFl(6)
$28.$20
ENT
0
STg*
LOOSTO*
CLR
STOSAP
INO
TCA
LDO*
STQ*
LOO*
STO*
LOQ
CONVRT
0
SAVEO
I
SAVEl
TAB
CONVRT
POS
LOOP
OUT
BACK
STQ*
STQ*
STQ*
STQ*
CLR
SAZ
OVI
LOQ*
STQ*
RAOJMP*
STQENQ
LOA*
ALS
INQ
ADD*
STA*
RAOINQ
0
I
POS
1
A
SIGN.O
BUFI+5
TAB+O
BUFI
-:N$20
BUFI+l
BUFl+2
BUFI+3
BUFl+4
0
OUT
=NIO
TAB.Q
BUFl.1
I
LOOP
I
5
BUFl.Q
8
-I
BUFl.Q
BUF.I
I
-I
('
\".
5-46
5.5.5
C~
0042
0043
0044
0045
0046
0047
P003C
P003D
P003E
P003F
P0040
P0041
P0042
0048 P0043
0049
I
SUFI
LOOP
0171
18F7
EBCI
DONE
C8CI
60FF
COOO
0003 P
ICD4
OOFF SAVEQ
0006P SIGN
002AP OUT
SQM
JMP*
LDQ*
LDA*
STALOA
DONE
BACK
SAVEQ
SAVEl
I
=XBUF
JMP*
END
(CONVRT)
OOOOP SAVEl
OOOCP TAB
0033P BACK
OOOIP SAVEA
OOOEP CONVRT
0035P DONE
0002P BUF
OOISP POS
003EP
0003P
0021P
PP
*
CONTST
CONVPT
2885
2BC8
TTY
Output
MI
*p
J
*ASSEM
OPTIONS LX
J
*P.
J
*L,5
J
*x"
+1427 2 ....
~f--- Answer
J
5-47
5.5.5
r- -,
\,-~,
QOOI
0002
0003
0004 POOOO 0000
CONTST
0005 POOOI COOO
POO02 37CO
0006 POO03 5400 X
POO04 7FFF X
0007 POOOS 6800
POO06 0007
0008 POO07 54F4
WRITE
0009 poooa OC01
0010 POO09 OOOF P
0011 POOOA 0000
0012 POOOB 18FC
0013 POOOC 0003
0014 POOOO 0000
00}5 POOOE 14EA
00}7
18FF
0018
0018 POOl} 54F4
QQIB PQ012 OAgO
0019
EXIT
NAM
ENT
EXT
0
LOA
CONTST
CONTST
CONVRT
0
=N$37CO
RTJ
CONVRT
STA
WRITE+6
RTJNUM
AOC
NUM
NUM
NUM
ADC
JMPP
NUM
EXIT
($F4)
$OCOI
COMPL
0
$18FC
3
0
($EA)
EXIT
$18FF
END
CONTST
Writes an
,,---"
I
............
I
CONVRT
OOFF CONTST
0004X
OOOOP WRITE
5-48
0007PCOMPL
OOOFP EXIT
0011P
-~.
5.6
5.6 EXERCISES
...
\
LJ
5.6.1 Exercises - Constant Mode of Addressing
1. What is in the A and Q registers when location NEXT is reached?
a)
LDA
ALS
LDQ
LRS
EOR
=N$1FOC
3
=N277
12
=N$0106
LDA
LDA
MUI
=N$7FFF
=N6
=N6
LDQ
LDA
AND
LLS
AND
=AAB
=AXY
=ACD
16
=AWZ
NEXT
b)
NEXT
c)
---.. \
"
-.---../
See Appendix E for
ASCII conversions.
NEXT
)
5.6.2 Exercises - Absolute Mode of Addressing
1. Write code to increase the contents of Index Register I by 1016.
2. If C017 is in core 10 cat io n 3F, and 4016 is in core location 4017, where would
program control be given for:
a)
b)
c)
JMPJMPJMP+
($3F)
$3F
($3F)
3. What is wrong with these:
a)
b)
c)
"'
LDALDA+
LDA+
0
$7F3-$700
(TEST)
........,,-
5-49
5.6.3
5.6. 3 Exercises - Relative Mode of Addressing
1. Will these instructions address b a c k war d or forward, and how many locations
from P?
b)
1831
1800
c)
EFFF
18FE
a)
2. What modes of address are these assembly language instructions?
a)
b)
c)
d)
e)
f)
g)
h)
LDA
TASK
JMPRAO+
STA*
($44)
*+3
AND
=X$4111-4111
STQ
LDA
LDA-
=XTWIX
10
(HIND)
(DRUM)
3. Why is relative addressing never used to address into the communications region?
5.6.4 Exercises - Indexing
1. What is wrong with these:
a)
b)
c)
LDA
MUI
ALS
AB, Q, I
A,Q
6,Q
2. What number is in A when NEXT is reached:
Core Location
Contents
002200230024-
0000
8024
0023
5-50
5.6.4
a)
I
"-/
LDQ
LDA-
=N$-l
($23), Q
LDQ
LDA-
=N$24
($22), Q
LDQ
LDA
=N$l
$23,Q
NEXT
b)
NEXT
c)
NEXT
3. What is wrong with this program:
START
LOOP
NAM
LDA
STALDA+
SUB+
LDQADQ
SQZ
JMP*
=N$10
r
$2000
$2000, I
r
=N-1
DONE-*-l
LOOP
DONE
C··
'I
,/
5.6.5 Shift and Skip Instructions
1. What will these machine language instructions do:
a)
b)
c)
d)
OFFO
01A3
OF52
OF88
2. What will be in the Q and A Registers when this program jumps to OVER.
Location
Opcode
Address
Comments
START
LDA
LDQ
LLS
QRS
ALS
SQM
ARS
SAM
ALS
QRS
JMP
=N$738F
=N$OlCA
3
14
5
GO-*-l
2
GQ-*-l
2
3
OVER
Loads 738F in A
Loads 01CA in Q
GO
5-51
5.6.6
5.6. 6 Review Exercises
1. Switch the contents of Location 1000 into Location 1001, and vice versa:
TEMP
0
0
LDA+
STA*
LDA+
STA+
LDA*
STA+
$1000
TEMP
$1001
$1000
TEMP
$1001
Several points of note:
1.
The problem descriptions seldom, if ever, specify core locations in decimal;
they're assumed to be hexadecimal since rarely is a core location referenced
decimally. Therefore, 1000 and 1001 in the problem mean 1000 hex and 1001
hex.
2.
The TEMP location is necessary for switching to hold the one operand while
the other is being s wit c he d. This form TEMP 0 0 can be used to simply
define a core location; one cell is reserved and zero's placed therein.
3.
The one-word reI a t i v e mode of addressing is used for locations within the
range of .±.127 to save one core location and one cycle time, and also to allow
the program to be run anywhere.
4.
Two-word absolute mode of addressing is used for the core locations 1000 &
1001. This is because this program could be fin all y loaded any number of
core locations away from 1000 and 1001; therefore, a two-word instruction
is needed. But why use absolute mode instead of relative? For programming
"run anywhere" programs there are two basic rules:
a) Everything that will move with the program is to be coded using relative
mode;
b) Everything that remains fixed in core is to be coded using absolute mode.
Since the statement of the problem states the two fix e d core locations to be
switched regardless of where the program doing the switching is to be loaded,
references to 1000 and 1001 should be made using absolute mode.
5-52
5.6.6
2. Transfer the contents of core locations 1000 through 1FFF to 3000 through 3FFF.
Cj
START
LOOP
LDQ
LDA+
STA+
1NQ
SQM
JMP*
=X$lFFF-$1000
$1000,Q
$3000,Q
-1
DONE-*-l
LOOP
DONE
3. Do a reverse transfer of problem 2, i. e., place contents of 1000 in 3FFF, 1001
in 3FFE, etc.
START
LOOP
LDQ
CLR
STALDA+
STA+
RAO1NQ
SQM
JMP*
=X$lFFF-$1000
A
I
$1000,1
$3000,Q
I
-1
DONE-*-l
LOOP
DONE
o
For this problem, two in de x registers are needed, one indexing up (I), and one
indexing down (Q).
4. Do Example 2 without Index Registers:
AREAl
AREA2
COUNT
LOOP
C)
NAM
ADC
ADC
NUM
LDA
STA*
LDA
STA*
LDA
STA*
LDA*
STA*
RAO*
RAO*
RAO*
SOY
JMP*
EXAMP
0
0
0
NUM sets the number 0
=X$7FFF-$lFFF+$1000
COUNT
=N$1000
First Address in AREAl
AREAl
First Address in AREA2
=N$3000
AREA2
(AREAl)
Indirect Addressing
(AREA2)
AREAl
AREA2
COUNT
DONE-*-l
LOOP
DONE
5-53
5.6.6
Several points to note:
1.
The number prestored in location COUNT is the d iffe r en c e between the
largest po s s i bI e positive number 7FFF and the difference between the beginning and end of the core blocks. Ifwe increase this count by one each time
through the loop, we will en c 0 u nt e r an overflow condition when the count
changes from 7FFF to 8000. We can then loop through and exit from the loop
using this preset count.
2.
AREAl and AREA2 are preset 'by using the ADC pseudo-op to O. Formerly
the form AREAl 0 0 was used to perform the same function. The assembler,
when encountering a zero in the opcode field, treats it as an ADC pseudo-op
so both forms are equivalent.
3.
This method of solving the problem is absolutely dependent on the use of indirect addressing since the addresses must be contained and manipulated in
core cells.
~'
....... -..
:5-54
u
CHAPTER VI
PSEUDO OPS
o
.. ,,",
CHAPTER VI - Pseudo Ops
~
lj
PAGE
TOPIC
C)
6.0
Introduction
6-1
6.1
NAM
6-1
6.2
END
6-2
6.3
ENT, EXT
6-2
6.4
EXT*
6-4
6.5
EQU
6-4
6.6
NUM
6-5
6.7
ADC
6-6
6.8
ADC*
6-6
6.9
ALF A IQC-J1
6.10
DEC
6.11
VFD
6.12
BSS, BZS
6-10
6.13
DAT, COM
6-11
6.14
ORG, ORG*
6-14
6.15
IFA, ElF
6-15
6.16
MAC, EMC
6-16
6.17
LOC
6-18
6.18
IFC
6-18
6.19
NLS, LST, SPC
6-19
6.20
EJT -~A-66 6.TC:eT ov f,l~T oIVIT)
6-19
6.21
OPT
6-19
6.22
MON
6-20
6.23
Exercises on Pseudo Ops, Utility Assembler
6-21
6.24
Exercises on Pseudo Ops, Macro Assembler
6-22
-
l-oC.ft/~~ r/~tl)/
IVj--r ..f-C-~p;cltl~7--
6-7
6-8
VA-All/It) f; !(<#'( el VlfIII1Tt;-.,
t
(f?I--C/{ Mi::~71(,-//!4/1)
6-9
c
6.0
~-
'\
6. 0 INTRODUCTION
The 1700 has 3 assemblers:
•
Basic assembler, which operates as a stand-alone system in a 4-K computer
•
Utility assembler, which operates under the utility system and r e qui res an 8-K
computer
•
Macro assembler, which 0 per ate s under the mass storage operating system and
requires a 12-K computer
The standard pseudo ops covered in this c hap t e r are available under all 3 assemblers,
with the exception of some additional pseudo ops available only under the macro assembIer. These are noted where they are described.
In addition to the mnemonics for the machine instructions which we have covered, there
are certain instructions that are only recognized by the assembler. They are used by the
ass em b Ie r itself to control the assembly, control the data, reserve storage, convert
data, signify beginning and end of assembly and control the output listing. These instructions are called pseudo instructions or pseudo ops.
6.1 NAM
o
The first instruction on any source pro g ram must be the pseudo instruction NAM. Its
use is to signal the assembler when to begin ass em b I y and how to set up its program
counter for this assembly. Its form is:
Location
Opcode
Address
NAM
Name
Comments
If the location field is blank, the assembler will begin assembly with its counter at zero
and signal to the loader in the object program that this program is program relocatable.
This provides the ability to have the sou r c e program assemble without regard to where
the program will finally be loaded and run in core. If a hexadecimal number appears in
the I 0 cat ion field, the assembler sets its program counter to that value and assembles
the program absolutely. When a program of this type becomes loaded, it is loa de d beginning at this absolute address specification. In the address field of the NAM pseudo op
will be the program name which is reproduced on the output listing.
6-1
6.1
Example:
NAM
SORT
This program is assembled program relocatable and can be loa de d anywhere into core.
The name SORT will appear on the output listing.
$100
NAM
INTERRUPT
This program is assembled absolutely, beginning at 100 hex, and will be loaded into core
at 100 hex only.
6.2 END
The last instruction in the pro g ram must be an END pseudo instruction. It marks the
physical end of the program. The address field may con t a i n an entry point to the program. This is called a named t ran s fer address, and it is the entry point where it is
desired for execution to begin after the object program is loaded.
Example:
NAM
ENT
SORT
START
END
START
START
6.3 ENT, EXT
Two pseudo instructions are used to pro v ide communication between programs. They
are the ENT (entry point) pseudo ins t r u c t ion, and the EXT (external point) pseudo instruction. Those 10 cat ion s internal to a program that are needed in another program
are declared as entry points to the i mIne d i ate program. The other program .can then
refer to these entry points in its immediate program by declaring them as external. The
names must match identically. Since communication between these two pro g ram s can
not be made at assembly time (since both programs can be assembled at different locations
at different times), the relocating linking loader must provide the cor r e c t location addresses when these two programs are finally loa d e d together. To accomplish this, the
loader builds loader symbol tables (Figure 13) where it places ref ere n c e s to all entry
points and ex t ern a I points. These tables locate exactly for the loader where the entry
point addresses are and where the external point references are that need patching with
6-2
6.3
their corresponding entry point addresses. When it finds a mat chin names between an
entry point and an external point, it does the patching.
Example:
Program 1 is w r itt e n and it needs to ext r act data from program 8 which has not
yet been written. The writers of both pro g ram s agree to a 10 word area with the
name of CLARK. Since program 1 needs to refer to CLARK in pro g ram 8, it declares CLARK as an external. This external declaration allow s the assembler the
use of this symbol which is not otherwise defined in program 1.
NAM
EXT
PROGI
CLARK
LDA+
CLARK
Program 8, when it is finally written, will declare C LARK as an entry point.
NAM
ENT
PROG8
CLARK
BSS
CLARK(10)
o
When both of these pro g ram s are finally loaded together in core, the loader will
link the address of CLARK at program 8 to its correct reference in program 1.
The EXT described above is called an absolute external. It means ref ere n c e s made
from the program to the external are ass em b 1 e d in absolute form (even if a relative
mode is used in the ins truction).
More than one symbol can be defined with each ENT and EXT instruction, sin c e their
general form is:
EXT
ENT
nl'n2'---nl,n2'---
n - name
-6-3
6.4
6.4 EXT*
Another form of external is available under the macro assembler: the relative external.
It causes the loader (at load time, when linking is done) to patch in the relative distance
from the referencing instruction to the location of the external, rather than the absolute
core location. This allows the use of relative references.
E~T*
Example:
TAG
I
I
5800
7FFFX
RTJ
I
TAG
t
A two-word relative mode must be used in referencing these externals.
6.5 EQU
It is common to use symbols in place of constants or !mown address 1 0 c a ti on s.
The
EQU pseudo instruction provides a means of declaring to the asselnbler the equivalence
of a symbol with a number or expression. The form of EQU is:
Location
Opcode
Address
Comments
EQU
ONE (1), TWO(2), THREE(3)
The symbol with its equivalent n u m be r is placed in the assembler's symbol directory
and all references to that symbol will yield its e qui val e n t number. It is important to
note that the EQU does not generate any code; it simply tells the assembler another value
for symbols found in the program. For example, it uses a 2 wherever it s~es the name
TWO.
Example:
r---
\"-----
Count the number of times the exact bit configuration 1110 appears in bit
positions 4 to 7 of core locations 1000 to 10CE.
COUNT
START
LOOP
OVER
DONE
NAM
0
EQU
EQU
LDQ
LDA+
AND
EOR
SAN
RAO*
INQ
SQM
JMP*
FIND
0
MASKl($OOFO), MASK2($00EO), FmST($1000)
LAST($10CE)
=XLAST-FmST
FIRST,Q
And out all but bits 4 thru 7.
=NMASKl
Look for exact match.
=NMASK2
OVER-*-l
Was match not exact?
No, match was exact.
COUNT
-1
Yes, no match.
DONE-*-l
Finished?
LOOP
No.
Yes.
r---'
.........
6-4
'
6.5
By using the EQU, the same general problem with different parameters could be solved
with this program simply by chan gin g the EQU card. Assume the problem looked for
10110 2 in bit positions 8 through 12 of core location 3020 through 3F21. Simply pull out
the EQU card and insert one:
EQU
EQU
MASK2($lFOO), MASK2($1600), FIRST($3020)
LAST($3F21)
The EQU instruction is e s p e cia 11 y useful for referencing the mask tables in low core.
(See Appendix I.) These masks are available for foreground or background programs to
use, rather than defining additional core locations in a program to contain masks. The
EQU's to be used would be as follows:
EQU
EQU
LPMASK($2), NZERO($12), ZERO($22)
ONEBIT($23), ZROBIT($33)
These are the same EQU's used by the system and they make it easier to rem e m be r
which mask is being used. For example:
LDA-
c
LPMASK+2
This can be used instead of:
LDAThe same code is generated:
$4
C004
It is easier to remember that LPMASK+2 is a mask location containing two one bits on the
right end than to remember what location $4 contains. NZER0+4 would contain 4 zero
bits on the right. Location ZERO always contains a 0 word. . ONEBIT+5 would contain a
one bit in bit position 5; ZROBIT+8 would contain a zero bit in bit position 8.
6.6 NUM
In order to insert known con s tan t s into the assembly, the pseudo op NUM is used. Its
form is:
Location
Opcode
s
NUM
Address
Comments
s means a symbol
16-bit constants are inserted, in line, one constant to a word. If a symbol is specified
in the location field, it is assigned the storage .address of the first constant.
6-5
6.6
Example:
HERE
NAM
NUM
EXAM
$7312,21,-21,-$216
Since this is a program relocatable assembly (blank in location field of NAM card), HERE
is at program counter POOOO and the following constants are inserted:
POOOOPOOOlP0002P0003-
7312
0015
FFEA
FDE9
Expressions are not allowed.
NUM
$7312-41
Ulegal
6.7 ADC
To insert in line a table of addresses, the ADC pseudo instruction ~s used. It functions
identically to the NUM pseudo instruction except expressions may be used and the result
is evaluated for only 15 bits since an address value cannot exceed 15 bits in length. Bit
15 will be set if the expression is enclosed in parentheses (indicating an indirect reference). Its form is:
s
'--_."
ADC
Example:
Opcode
Address
NAM
EQU
EQU
EXAM
TEN(10)
MASK($F302)
HAT
ADC
TEN
TEN is. OOOA (See EQU)
STILL
ADC
(HAT)
Will set Bit 15
Location
Comments
Assume the program counter for HAT is at POI02 and for STILL, POIFF; then:
POI02
OOOA
POIFF
8102
,~---,
6.8 ADC*
Under the macro ass em b Ie r there is a second form of the ADC pseudo op, the ADC*
pseudo op. This form functions identically to the ADC pseudo op in the utility assembler.
However, all address expressions e v al u a te d are then placed in relative form. Examples of both forms are on the following page.
6-6
6.8
HERE
NAM
BSS
ADC
EXAM1
TAG(10) ,TAGl(lO)
TAG ,TAG1
HERE which is at P0014 has the absolute address of TAG (POOOO), and HERE+1 (P0015)
has the absolute address of TAG1 (POOOA).
HERE
NAM
BSS
ADC*
EXAM2
TAG(10) , TAG1(10)
TAG, TAG1
HERE, at P0014, has the relative address of TAG (FFEB, or twenty decimal locations
back) and HERE+1 (P0015) has the relative address of TAG1 (FFF5).
6.9 ALF
ASCII characters are stored in consecutive locations, two 8-bit characters for each core
location, by the ALF pseudo instruction. The ALF pseudo instruction is used to pack a
core area with a message which can be used for subsequent output to ASCII devices like
the teletype. A symbol, if used in the location field, will refer to the fi r s t word of the
block. The format for the ALF pseudo instruction is:
C~)
s
ALF
n, <2n characters>
HERE
NAM
ALF
EXAM
3,ABACAD
Example:
Three words are packed with the ASCII equivalents of ABACAD:
POOOO
P0001
P0002
4142
4143
4144
Table of ASCII equivalents is found in Appendix E.
A blank is stored into unused locations.
Example:
produces:
/'
r·-.....",
HERE
ALF
POOOO
POO01
POO02
POO03
POO04
POO05
4142
4143
4144
2020
2020
2020
6,ABACAD
\~-.......,.-
6-7
6.9
The ALF pseudo op in the utility system only allowed specification for its message by the
use of an unsigned integer for the number of core locations to be reserved. In the macro
assembler a second form for this pseudo op is available:
ALF
n, ~essag;>n
n may be a non-integer character which signals the end of the message. n is a delimiter
and appears before the comma and after the message.
This form is an advantage where the programmer does not desire to count the number of
words in his message and will find no conflict between his message and the terminating
character used.
For either form the pseudo op ALF will pack two ASCII characters per word. The address
of the first location of the message in core will be assigned to the symbol in the location
field, if specified.
Example:
GO
NAM
EXAMP
ALF
Z,DATAZ
Two words· are reserved, starting at location GO for the ASCII equivalent of DATA.
6.10 DEC
A DEC pseudo op is available under the macro assembler. Suppose the following problem
needed to be solved:
y = 1. 63 x 10 3 x 2 + 21246 x 10-2 x + 81 x 26
• 0074 x 10 6
.11 x 10 3
Insertion of the constants in this problem would be facilitated by having the assembler do
the binary or decimal conversions. The DEC pseudo op allows insertion of constants with
decimal or binary scaling factors. Its form is:
s
DEC
k is a constant - IDdBb
Example:
HERE
NAM
EXAMP
DEC
163D1,74D2,21246D-2,81B6,11Dl
This example shows the cons tants from the equation inserted. The decimal numbers are
converted men tall y to integers. HERE is the s y m b 01 i c address of the first of these
decimal constants which are inserted one per core cell. The size, then, of the converted
decimal constants must lie within the range of ±32, 767.
6-8
\ .......
6.11
c
6.11 VFn
The VFD pseudo op is available under the macro assembler. It is frequently desirable
to pack data into memory locations. The VFD (variable field definition) pseudo instruction assigns data to consecutive locations in the instruction sequence without regard for
computer words. Data is stored in bit strings rather than word units. Its format is:
s
m will specify the mode.
N
A
X
VFD
m1n1/v1,m2n2/v2,···,mnnn/vn
Three modes are possible:
numeric constant
ASCII character code
expression
n will specify the number of bits and v is the value. n may be 16 bits or less for either
N mode or X mode; however, for A mode n must be some mul tiple of 8 since ASCII
character conversion is meaningless for a non-multiple of 8 bits. Numeric constants
must be within the range of +32,767.
Example using numeric constants:
o
TAG
NAM
VFD
LDA
EXAMP
N4/$F,N8/6,N8/-6,N2/16
The ass e m b ly of the bit strings begins with the high order bit of the first core cell (in
this example the core cell labeled TAG). TAG gets packed with 1111 which is the binary
equivalent of hexadecimal F. The next 8 bits of TAG get packed with the binary equivalent
of 6 which is 0000 0110. The next 8 bits (which will now be thelowerfourbits of TAG) and
the upper four bits of TAG+1 get packed with -6 or 11111001. The next two higher order
bits get packed with as much of the number 16 as is possible, that is, with the low order
two bits (00). The remaining bits of TAG+1 set to zeros. TAG and TAG+1 will thenlook
like this:
TAG
TAG+1
F06F9000-
1111 0000 0110 1111
1001 0000 0000 0000
If the n u m be r of bits specified is not sufficient for the value then the high order bits of
the value are truncated (chopped off), as many as are necessary. If the number of bits is
larger than the value, then the sign of the value is extended.
Example using expressions:
NAM
EQU
TOP
VFD
EXAMP
TAG($4FF1), HAT(20)
X8/T AG+2, X8/HA T
6-9
6.11
The pre v i 0 us example shows the use of expressions where the expression is evaluated
absolutely (since neither TAG nor HAT is relocatable). If fewer than 16 bits are specified, the absolute expression by itself is evaluated (using 16 bits) and is truncated. The
previous example is decoded by the assembler.
TOP
F314
When the expression is evaluated relatively, the n must be 15 and the expression must
be positioned so that it will be stored right justified at bit position 0 of the computer word.
Example using ASCII character mode:
NAM
TAP
VFD
EXAMP
A24/ABC, N8/$3F
The above ex amp 1 e illustrates three ASCII characters, A, B and C; these will be converted using 8 bits for each, followed by the numeric constant 3F hex in the lower 8 bits
of TAP+l. The above example is decoded by the assembler.
TAP
TAP+l
4142
433F
6.12 BSS, BZS
Blocks of data storage can be all 0 cat e d within the program using either the BSS or the
BZS pseudo instructions. The block is given a name and a size according to the following
format:
BSS
n is name of block
s is size
These pseudo ins t r u c t ion s reserve areas. The BZS area is zeroed out at load time
while the BSS block is not changed at load time; therefore, anything may be initially set
in a BSS block at run time.
Example:
NAM
BSS
EXAM
AA(10), BB(20)
LDA
The symbol AA will be assigned the address of the first 10 c a ti on of the block of 10 and
the symbol BB will be assigned the address of the first location of the block of 20 locations reserved. When this program is loaded, anything can be initially contained in these
first 30 locations. Had a BZS been used instead of the BSS, these first 30 locations would
have been zeroed at load time.
('
' - . r'
6-10
6.13
,.....'"
~
6.13 DAT, COM
Two other pseudo ops are used to res e r v e areas for use that are outside the bounds of
the main program. These areas are reserved by the DAT and COM pseudo ops. Refer
to Figure 13. Notice that the common storage area (reserved by the COM pseudo instruction) is the area that is used by the loader. This area cannot be preset with data and
is used only at run time when the loader becomes destroyed. The data area (reserved by
the DAT pseudo instruction) is assigned an area with the programs themselves; in fact,
the data block will precede the pro g ram that declares it. The data area can be preset.
The loader will make common and data area assignments just once and will use its common counter and data counter at this assigned value for the rest of the programs loaded.
It is necessary, then, for the first sub pro g ram s of a run declaring common or data
storage to declare the largest amount necessary. The format for the COM and DAT
pseudo instructions is the same as for the BSS and BZS and is:
DAT
COM
n l (sl),n 2 (s2)'·· .nm(Sm)
n l (Sl)' n 2 (S2)' • • • nm (s m)
NAM
BSS
DAT
COM
EXAM
AA(30)
CAT(40) ,RAN(20)
CCC (40) ,AB(10)
Example:
o
The BSS will reserve 30 locations within the program while the DAT will reserve a total
of 60 core locations, reserved outside of the program area. In fact, this data area will
immediately precede the main pro g ram area in core. The common area, 50 words in
this example, is reserved at the high end of core where the loader resides at load time.
This common area cannot be preset with data and 'can only be used at run time, when the
loader is no longer needed.
6-11
6.13
,,1'.... - . . ,
Loader
High
Core
.....t---50 Words
Common Counter
I
Loader Symbol Tables
More Programs
1
Program
~
Program Counter
~
60 Words
~Data Counter
Data
Executive Monitor
Resident
013F
•
Interrupt
Area
0100
~
OOFF
~
0000
~
c:
Communication
Area
Figure 13. Data, Program and Common Counters.
Figure 13 ill us t rat e s the three counters: data, program and common counter. There
are three types of reI 0 cat ion po s sib 1 e when loading programs, each type using its
appropriate counter. References to addresses will be relocated using the data counter if
the address is in the data area, the program counter if the address is in the main program
area and the common counter if the address is in the common area.
c
6-12
6.13
C/
Example:
NAM
DAT
COM
BSS
LDA+
STA+
STA+
EXAMP
AA(10)
BB(10)
CC(10)
AA+3
BB+7
CC+4
The listing for the above looks like:
001.
002.
003.
004.
005.
006.
0
007~
POOOO
POOOA
POOOB
POOOC
POOOD
POOOE
POOOF
OOOOD
OOOOC
OOOA
C400
0003D
6400
0007C
6400
0004P
NAM
DAT
COM
BSS
LDA+
EXAMP
AA(10)
BB(10)
CC(10)
AA+3
STA+
BB+7
STA+
CC+4
The first column is the line number. The second column is the core location in hex.
The P preceding it indicates that the value of the pro g ram counter will be added to the
number at load time, yielding the actual core location.
Hex word followed by relocation symbol: P for program counter, D for data counter, and
C for common counter.
Although there is only one common area and one data area assigned per core load, references to data in these areas can be made by all programs in core. The relative position
with respect to the data or common counter for the data desired must be kn own by each
program but the same names need not be used by diffe_rent pro g ram s to reference the
same data.
Example:
Program 1 is the first program loaded.
common area.
NAM
DAT
It must declare the largest data or
PROG1
AX(lOO) ,BX(50) ,CX(100)
6-13
6.13
When the program is loaded, a data area of 250 locations is assigned and the data counter
is set at the beginning of this area.
Suppose PROG6, which is the sixth program loaded, is interested only in the data which
PROG1 lmows as the 26th to 30th locations in BX.
NAM
DAT
PROG6
DUMMY(125), MINE(5)
LDA
MINE
DUMMY is not used by program 6. It only allows a skip past the AX and first 25 locations
of BX corresponding to program 1. Ref ere n c e to MINE in program 6 will yield the
same data as reference to BX+25 in program 1.
6.14 ORG, ORG*
Presetting the data area is accomplished by the use of the ORG pseudo
ORG
OPe
Its form is:
a
This pseudo op c han g e s the value of the assembler's counter to agree with a. All instructions or data following the ORG instruction are assembled into consecutive locations
until either an 0 the r ORG instruction is encOlmtered or an ORG* is encountered. When
an ORG* is en c 0 u n t ere d, the assembler's program counter is set to the value that it
would have been,if the very first ORG ins t r u c t ion had not occurred. The address expression (a) may be either positive program relocatable, positive data reI 0 cat a b I e or
absolute. Notice common reI 0 cat a b I e address expressions are not allowed since the
common area cannot be preset.
Example:
NAM
DAT
LDA
.......... .1
EXAMP
AX(20) ,BX(40)
Assume P. C. =P0030
ORG
AX+10
ORG
BZS
ORG*
LDA
AX
10
C,
6-14
6.14
G
In this example the program counter starts off at 0000 and pro c e e d s in sequence until
the first ORG instruction is assembled. Since the address expression refers to the data
area, the assembler's pro g ram counter will now be at DOOOA, indicating that the code
beneath this first ORG pseudo i:n.struction will be inserted beginning in the 10th data area
location. When the second ORG instruction is encountered, the code under it (BZS10) is
assembled into the beginning of the data area. When the ORG* instruction is encountered,
the program counter is set to P0031; this is the next location following the last location
assembled before the first ORG instruction. Any symbols used in the address expression
of the ORG pseudo op must have been previously defined in the program.
The following example can be used to illustrate presetting values in A and B in the DATA
block:
A= OOOOD
X:: OOOOC
C= 0007D
OOOOP
000lP
0002P
OOOOD
DAT
COM
DAT
0
LDASTA+
ORG
NUM
0004P
ORG*
RAO-
START
A(5) ,B(2)
X
C(50)
0
$FF
X
A
~~
A
0
t
6. 15 IF A, ElF
B
$FF
The macro assembler contains a conditional assembly instruction. With the p s e u do op
IFA, it is possible to specify portions of a program to be e i the r assembled or excluded
during assembly time. Its format is:
s
IFA
(This pseudo op can be used within a macro skeleton.) e may be an ex pre s s ion and c
specifies one of four conditions:
EQ
NE
GT
LT
e1=e 2
e1~e2
e1>e2
e1<;e2
The termination of the coding en com pas sed within the ran g e of an IFA pseudo op is
accomplished with the pseudo op ElF. Since nesting is allowed, a match between an IFA
and ElF pseudo op range is made by correspondence between the first two characters of
the symbols in the location field of the IF A and the address field of an ElF.
6-15
6.15
Example:
TOTS
NAM
EQU
EXAMP
AB(10) ,AC (20) ,AD(30)
IFA
LDA
STA
ElF
AB+AC, EQ, AD
TAG
TAG1
TOTS
The LDA TAG and the STA TAG1 instructions will be assembled in this example since
equality exists. Changing the EQU card, however, or changing the condition from EQ to
NE would have excluded these two lines of code from the assembly.
Problem:
VALUE PROBLEM (COMMON)
Starting in the 11th location of COMMON are 10 words. Bits 13-8 of each of the 10 words
are to be compared with bits 5-0 of a location called VALUE which is ext ern a I to this
program. Do not destroy the original contents of VALUE. Count how many complete
matches are found in the bit strings compared and store the answer in the 7th word of the
data block. For example, if bits 5-0 of VALUE con t a in 101100 and bits 13-8 of Xl
con tain 101100, one match has been found. Any other bit configuration would be a nomatch. Write a complete program to solve this problem.
x·1
Value
XXXXXX
[ -----------]
[ -~
XXXXXX
-----------
6.16 MAC, EMC
The macro assembler gets its name from the macro capability incorporated therein. An
often used set of instructions may be grouped tog e the r to form a macro. Macros then
need be defined once and the rea f t e r the whole macro structure will be incorporated in
line in the assembly generated coding whenever the macro name is called. Each macro
has a name which is first define d by the use of the MAC pseudo op and thereafter the
name can be placed in the opcode field as if it were an instruction or pseudo instruction
and the assembler will substitute, starting at that location, the whole structure that was
previously defined by that name. The macro must first be defined. The form is:
s
MAC
6-16
(-',
'-..."
6.16
I
r
'
\J
s is the name of the macro. The p's are symbols of one or two characters that will define variables wi thin the macro structure. Parameters are enclosed in apostrophes as
shown within the macro. The keypunch code for apostrophe is 8-5. The macro structure
itself is defined to be finished when the EMC pseudo op appears in the opcode field. EMC
is always the last instruction in a macro definition.
Example:
HELP
NAM
MAC
LDA
STA
ADD
STA.
EMC
EXAMP
XA,XB
'XA'
'XA'+l
'XA'-l
'XB'
HELP is the name of the macro and XA and XB signify variables within the macro. All
the code between the MAC and EMC is the mac r 0 structure. Anything in this structure
can be made variable. In this assembly only positions of the address field were varied.
Macros canbe of anylength and they can also be nested. A macro must be defined before
it is called by name. Calling the macro in the above example would look like this:
SAZ
HELP
OVER-* .... l
TAG,TAG1
OVER
The macro is called by placing its name in the opcode field. The assembler will search
the symbol d ire c tor y for a macro with the name of HELP, and if found, the complete
macro structure is placed in line at this point. When calling a macro, the variables must
be specified. For this example TAG will be inserted for each XAreference and TAG1 will
be inserted for each XB reference. Effectively, then, the assembler will place in line
the following:
LDA
STA
ADD
STA
TAG
TAG+1
TAG-1
TAG1
A macro could be defined as "an instruction which' stands for' a number of other instructions. "
6-17
6.17
6.17 LaC
Since' the code for a macro is ins e r ted in line wherever it is "called," if there are any
symbols in the location field of the macro, it could be called only once, since the symbol
would tbe doubly defined if the macro were called again. This problem can be eliminated
by defining the symbols local to the macro.
Symbols that are local to the macro being defined are listed in the LaC pseudo OPe This
pseudo op i m m e d i ate I y follows the MAC pseudo op and it allows use of one- or twoc h a r act e r symbols local to the macro so that the same symbols can also appear in the
main program. Its form is:
LaC
Example:
TOPP
'AB'
'G1'
'G2'
NAM
MAC
LaC
LDA
EaR
STA
JMP
EMC
EXAMP
AD,AB
G1,G2
'AD'
=N$0171
'AD'+l
'AD'+2
Symbols passed as parameters may not be defined as local.
6.18 IFC
A conditional assembly pseudo op is available for use within the macro skeleton. It is
the IFC pseudo OPe It operates the same as the IFA covered previously; however, it has
only two conditions, the NE and EQ. Its form is:
s
IFC
Each a must be a string of from one to six characters, or a formal parameter specified
in the MAC statement. The c h a r act e r strings should not contain commas, blanks or
apostrophies. Two character strings are equal when they contain the same characters in
the same po sit ion and are of the same length. Characters in excess of 6 are ignored.
Termination of the range of the IFC is made when an ElF is encountered with the first
two characters of the symbol in its address field matching the first two characters in the
location field of the IFC.
6-18
6.18
Example:
TOTAL
IT
NAM
MAC
LD'XA'
STA
IFC
ADD
STA
ElF
EMC
EXAMP
XA,XB,XC,XD
=N$4000
'XB'
'XC'EQ'XD'
'XB'+2
'XB'
IT
If parameter XC and XD are equal when this macro is call e d then the ADD and STA instructions will be inc 0 r p 0 rat e d in line with the rest of the macro structure. If parameters XC and XD are not equal when the mac r 0 is called, these ins t r u c t ion s will
not be inserted in line as part of this macro structure during assembly.
o
TOTAL
Q, TAG, TEN, NINE
LDQ
STA
=N$4000
TAG
The generated code is:
Since TEN and NINE do not match character for character, the IFC condition is not met
and the ADD followed by the STA instructions are not assembled.
Problem:
Write a macro for an IN! instruction. Add a test routine to check it out.
The IN! macro should increase the I Register by any constant exactly the same way the
INA increases the A Register or the INQ increases the Q Register. In other words, no
other registers should be destroyed when the macro is called.·
6.19 NLS, LST, SPC
Three pseudo instructions are used for control of the listing. They are NLS, which prevents normal output list until a LST instruction is encountered or until the end of a
program. Spacing paper on the printer is a c com p 1 ish e d by the SPC pseudo OPe The
n urn b e r of lines to space is specified as an absolute address expression in the address
field.
6-19
6.19
Example:
NAM
LDA
EXAMP
SPC
12
12 lines are spaced
NLS
Lis ting is stopped
LST
Lis ting is enabled
6.20 EJT
In addition to the NLS, LST, and SPC listing control pseudo instructions, the macro
assembler also has an EJT pseudo
printing of the lis t output.
OPe
This ins t r u c t ion causes page ejection during
6.21 OPT
Three standard options determine the type of output from the assembler. All three are
automatically selected if no OPT statement is encountered be for e the first NAM. OPT
is the only pseudo instruction that may precede the NAM pseudo OPe No code is generated
by this pseudo instruction.
OPT must begin in card column 2.
Normal execution of ass em b I y produces list output on the standard list device, punch
output on standardpunch device and load and go output on the mass storage device. These
are 0 p t ion s L, P and X. Two other options are available. The Mop t ion will enable
Ii sting of macro skeletons and an A option will cause abandonment of the assembly and
will return control to the operating system. To exercise these 0 p t ion s or to eliminate
any of the three standard options, the OPT pseudo instruction is used. When the OPT
pseudo instruction is encountered by the ass e m bl e r it will type OPTIONS on the teletypewriter and allow the operator to manually reset the options desired. He can choose
any or all of these five options.
Option
Meaning
L
List output on standard list unit
P
Punch binary output on standard punch unit
X
Load and go; executable output loaded on a mass storage
device
M
List macro skeletons
A
Abandon assembly
6-20
c
6.21
/"' .... _..,
\~
Relocatable binary output is s e I e c ted by the P option.
1700 Operating System Reference Manual.
The format is described in the
If the X option is selected, relocatable binary output is placed on the mass storage unit
for subsequent loading and execution as described in the 1700 Operating System Reference
Manual.
The L option results in assembly listing.
6.22 MON
Mter the last subprogram has been assembled, control can be returned to the operating
system by use of the MON pseudo OPe It may be used only after the END statement.
MON must begin in card column 2.
Example:
cc
2
OPT
NAM
f
END
NAM
o
1
END
PGM
n . . . .1------ Name of main entry point in main
SUB
program
. . .1----- No name
on subroutine end card
MON
cc
2
6.23 EXERCISES ON PSEUDO OPS - UTILITY ASSEMBLER
1. What are the errors in this program?
Location
LED
TAG
TAG11
START
Opcode
Address
NAM
EQU
NUM
BSS
EXT
LDA+
STA+
EXAMP
720
-72, $FFFF, 72
25
LAD, TAG
TAG
LAD
END
START
6-21
Comments
6.2.3
2. Why will the ORG LIST produce an error?
COM
LIST (30)
ORG
LIST
COM
LIST(30)
3. In this example:
LDA
LIST
this assembler will decode the LDA LIST as:
C400
OOOOC
Why?
4. What is the problem?
(~
BSS
LIST (10)
LDA
SAZ
LIST+3
6.24 EXERCISES ON PSEUDO OPS - MACRO ASSEMBLER
1. What code is produced:
a)
VFD
NI2/-17 ,N5/$7F2 ,N15/47
b)
VFD
A8/A,A8/B
c)
DEC
16DIB4
d)
ADC*
*-1
6-22
6.24
('
-",
~j
2. What instructions are assembled:
G01
T02
H03
EQU
IFA
LDA
IFA
ADD
I?A
ADD
ElF
ElF
ElF
AA(10), BB(20), CC(30)
10, GT, BB-15
=N$1000
CC-AA, EQ, BB
=N$1000
40, NE, BB*2
=N$2000
HO
TO
GO
3. If this macro definition:
PRINT
TAG
o
TAG1
MAC
ALF
IFC
ALF
ElF
EMC
XA,XB,XC
Z,ERROR'XB'Z
'XA', EQ, LU
Z, LOGICAL UNIT'XC'Z
PRINT
LU, 6, 8
is called by
what assembly language is produced when this macro is called?
4. What discrepancy is in this program?
FALL
MAC
'TE'
NUM
LDA
EMC
LOC
FALL
LDA
TE
$7FF3
'TE'
TE
CJ
6-23
c'
CHAPTER VII
INTRODUCTION TO MACHINE LANGUAGE I/O
l~
"
I~ .... "I
I
\,....
,~
-
"
,,"
CHAPTER VII
C~
0
Introduction to Machine Language
Ilo
TOPIC
PAGE
7.0
Introduction
7-1
7.1
Unbuffered
7.1.1
Use of Registers in
7.1.1.1
Q Register
7-2
7.1.1.2
A- Register
7-2
7.1.2
Functions, Status and Data
7-2
7.1.3
Summary, Unbuffered
7.1.4
Low-speed Package
7-3
7.1.5
Reply or Rej ect
7-4
7.1.6
Functions
7-5
7.1.6.1
Paper Tape Reader Example
7-5
7.1.7
Status
7-9
7.1.8
Interrupts
7.2
Buffered
7.2.1
Disk Functions
7-12
7.2.1.1
Director Function
7-13
7.2.1.2
Load Address Function
7-14
7.2.1.3
Write Function
7-15
7.2.1.4
Read Function
7-17
7.2.1.5
Compare Function
7-17
7.2.2
Disk Status
7-17
7.2.2.1
Director Status
7-17
7.2.2.2
Address Register Status
7-18
7.2.3
Summary, Buffered
Ilo
7-18
Ilo
7-1
I/o
Ilo
7-1
7-3
7-10
Ilo, Disk Example
7-11
'.-'
7.0
7. 0 INTRODUCTION
The 1700 is composed of a 1704 and various peripherals. The 1704 contains the registers and the logic necessary for bringing data into the computer, performing operations
upon the data and sending the data out of the computer for fu tu r e reference and/or display.
ARITHMETIC
CONTROL
INPUT
......
:- -
~~~~-
--- - - MEMORY
-- -
-
OUTPUT
-+-....:::;...;:~=--=~-.
1704
The per i p her a 1 s are composed of devices capable of sending and/or receiving data.
Such devices are the tel e t y p e, paper tape reader and paper tape punch. Many other
peripherals are available and discussed in Chapters 12 and 14.
The peripherals and the 1704 cannot com m u n i cat e directly; therefore, an interpreter
is required. The interpreter is referred to as a controller. The program tells the controller the operation to be performed and the controller directs the per i p her a 1 in the
performance of the operation.
7.1 UNBUFFERED I/O
7.1.1 Use of Registers in I/O
Conlmunications among the 1704 and the peripherals is a c com pI ish e d via one
input/ output (I/O) .channel attached to each controller. The I/O channel works in
conjunction with the 1704's A register and Q register. It is, consequently, called
the A/ Q channel.
~ 4----r-A/-Q---~_
7-1
_I
7.1.1.1
7. 1.1. 1 Q Register
..............
The Q reg i s t e r designates the equipment to be referenced and directs the op-,
erations to be performed. The Q reg i s t e r will be in the following format when
performing an 110 operation via the AIQ channel.
15
QI~
11 10
'{\
7
6
0
W
______~_____E____~~__S_'______________D~I
_______
The Wfield, bits 15-11, will always be zero except when referencing a 1706;
this will be discussed later.
The E portion, bits 10-7, designates the e qui pm e n t number being referenced.
The equipment number will correspond directly with a hardware switch located on
each controller. The n u m be r will vary from a hexadecimal 0 to a hexadecimal
F.
The S po r t ion distinguishes among peripherals attached to the same controller.
The bits composing the station code will vary with controllers.
The D portion is the director bit or bits which designates the type of information
being transferred: data, status or function. The n u m be r of bits used to compose the D po r t ion also varies a c cor din g to the controller being referenced.
~,------- "
7. 1. 1. 2 A Register
The A register sends and receives all communications between the 1704 and
the peripherals; that is, the data, functions, or status.
7. 1. 2 Functions, Status, and Data
The 1704 is capable of sending or receiving data, sending a function, or receIVIng
status. The D portion of Q and the II 0 ins t r u c t ion executed denote which of
the three operations is to be performed. All inputloutput operations via the A/Q
channel are performed with two instructions.
INP
OUT
The INP instruction brings inf 0 rm a ti 0 n into the A register: data or s ta tu s.
The OUT instruction sends in f or mat ion from the A register: data or function.
Bit 0 of Q is usually the D portion, designating the type of in for mat ion being
transferred. (Note: the exceptions are discussed in Chapte r ,14.) When bit 0
of Q is a 0, the transfer of data is designated. The direction of the data flow is
in d i cat e d by the 110 instruction. The INP brings data into A. The OUT sends
data from A. When bit 0 of Q is a 1, the transfer of status or the transfer of a
function is requested. INP requests status while an OUT sends a function.
7-2
7.1.2
INP
OUT
<
<
D=Odata
D = 1 status
D= 0 data
D = 1 function
7. 1. 3 Summary, Unbuffered Ilo
In review, all input/output operations performed by the 1704 will take p I ace via
the A/Q channel. The Q register indicates the peripheral being referenced and
the type of information being transferred. The information to be transferred will
be brought into or sent from the A register, depending upon the instruction executed: INP or OUT. Three types of information may be transferred: data,
function, or status.
7.1.4 Low-speed Package
o
The grouping of the teletype, paper tape reader and paper tape punch is referred
to as the low-speed package. The low-speed package is always equipment number
1. The various peripherals attached are referenced specifically with the S portion of the Q register, bits 4-6.
Peripheral
"S"tation
Teletypewri ter
Paper tape reader
Paper tape punch
1
2
4
The format of Q for each of the low-speed peripherals is as follows:
...
15
Q1 0
0
0
0
11
0
I
10
0
\
0
0
v
Equip.
1
7
1
5
0
6
I
0
4
1
3
0
2
0
1
0
0
DI
3
0
2
0
1
0
0
DI
I'---y----/
Station
1
TELETYPEWRITER $0090/$0091
15
Q 10
14
0
13
0
12
0
11
0
I
10
0
9
0
\
,-\
~
",-,,--~
8
0
V
Equip.
1
..
6
7
1 I 0
1\
5
1
v
Station
2
PAPER TAPE READER $00AO/$00A1
7-3
4
0
1
7.1.4
-',
~
Q
15
0
1
14
0
13
0
12
0
11
0
I
10
0
9
0
\
8
0
V
Equip.
1
7
1
I
1\
6
1
5
0
4
0
V
3
0
2
0
1
0
0
DI
"'---
.
I
Station
4
PAPER TAPE PUNCH $00CO/$00C1
The programmer must load the Q register with the cor r e c t equipment, station
and director setting prior to executing the desired I/o instruction.
The coding necessary
as follows:
~o
reference each of the low-speed peripherals for data is
LDQ
NOP
INP
=N$0090
TTY FOR DATA
-1
DATA IN A
LDQ
LDA
NOP
OUT
=N$0090
DATA
TTY FOR DATA
DATA IN A
-1
SEND DATA TO TTY
LDQ
NOP
INP
=N$OOAO
PTRDATA
-1
DATA IN A
LDQ
LDA
NOP
OUT
=N$OOCO
DATA
PTPDATA
DATA IN A
-1
DATA TO PTP
~'.-
- ...........
C,
7.1.5 Reply or Reject
Control will be returned to the program after the execution of an I/o instruction
at one of t h r e e locations: P+1, P+ ~, P+1+ il. Control will be returned to P+1
when the controller a c c e p t s the command, NORMAL REPLY. Control will be
returned to P+1 + ~ when the controller rejects the command, EXTERNAL REJECT.
If the con trolle r fails to reply or reject within 6 microseconds, an INTERNAL
REJECT is generated and con t r 0 I continues at P+ il. The NOP instruction is
inserted within the above coding to allow for an INTERNAL REJECT.
("
\,
7-4
7.1.5
INSTRUCTION
ADDRESS
RESPONSE
r
~I
NOP
INP
Continue
INTERNAL REJECT - - - - - i... 2000
EXTERNAL REJECT
.. (P) 2001
NORMAL REPLY
.. 2002
P+ b.
P+1+ "b.
P+1
INTERNAL REJECT
EXTERNAL REJECT
NORMAL REPLY
-1
2001 +(-1)=2009
2001 +1 +(-1)=2001.
2001+1=2002
7. 1. 6 Functions
I/O programming for the 1700 peripherals requires the programmer to c onne c t
with the desired peripheral by set tin g the Q register and issuing a function.
LDQ
LDA
NOP
OUT
=N$OOAl
FUNC
PTR FOR FUNC OR STATUS
FUNCTION IN A
-1
SEND FUNCTION TO PTR
A function is a command or a group of commands sent to the controller. The
function sent will vary according to the equipment. The paper tape reader allows
the pro g ram mer to clear the con t roll e r, clear interrupts, select interrupt
on data and/or alarm, start motion and stop motion. Each function corresponds to a bit in the A register. The func ti on is requested if a 1 appears in
the corresponding bit.
o
A
15
0
I
7
0
0
0
0
0
0
0
01
6
1
5
1
t
2
4
3
1 ~~ 1
1
1
0
11
STOP MOTIOJ
START MOTION
INTERRUPT ON ALARM
DATA INTERRUPT REQUEST
CLR INTERRUPTS
CLR CONTROLLER
1
r1
The above functions may be sent together, with the ex c e p ti on of the clear controller and clear interrupt; these must be sent separately.
7. 1. 6. 1 Paper Tape Reader Example
The programmer may clear the controller to clear all logic and interrupts previously selected by loading Q with $00A1, by setting bit 0 of the A register and by
issuing an OUT instruction.
7-5
7.1.6.1
LDQ
ENA
OUT
=N$00A1
1
-1
PTR FUNC OR STATUS
CLR CONTROLLER
FUNC TO PTR
The programmer may then start the motor on the paper tape reader. The start
motor command causes the reader to begin moving paper tape and start reading.
LDQ
ENA
OUT
=N$00A1
$20
-1
PTR FUNC OR STATUS
START MOTION
FUNC TO PTR
The' next step is to bring the data into the A register by set tin g the director bit
of Q to 0 and issuing an INP instruction.
LDQ
NOP
INP
=N$OOAO
PTR FOR DATA
-1
DATA INTO A
The program will continue to loop on the INP instruction until data has been read
into the holding register of the paper tape reader. Once data is available it will
be brought into the lower 8 bits of the A register. Note: the number of bits
composing a data word will vary among the peripherals. The first frame will be
in A and may be shifted to the upper 8 bits. Input will then be r e que s ted again
for the lower 8 bits.
ALS
NOP
INP
8
FIRST FRAME UPPER 8 BITS A
-1
NEXT FRAME BROUGHT TO A
The entire 16-bit word is now in the Are g i s t e r and s h 0 u I d be s tor e d in the
buffer area. Once the word is stored the program con tin u e s to bring data into
the A register. A check should be made to determine when all requested words
have been read from the reader.
7-6
7.1.6.1
r,.-·····
U
START
DATA
COMP
WDCK
0
NAM
LDQ
ENA
OUT
ENA
OUT
INQ
NOP
INP
ALS
NOP
INP
STA*
LDA
SAP
RAO*
JMP*
SLS
NUM
END
PTR
=N$OOAI
1
-1
$20
-1
-1
PTR FOR FUNC/STATUS
CLR CONTROLLER
FUNC TO PTR
START MOTOR
FUNC TO PTR
PTR FOR DATA
-1
8
FRAME IN A
DATA UPPER 8 BITS
-1
BUF
WDCK
COMP
WDCK
DATA
0
FFFO
START
16-BIT WORD IN A
SA VE IN MEMORY
WORD CHECK IN A
WHEN POSITIVE COMPLETE
CONTINUE READING
STOP WHEN COMPLETE
CHECK FOR 16 WORDS
The programmer may check for leader on the paper tape as has been done in the
example on the next page.
()
7-7
7.1.6.1
1721 PTR - AUG '6S
USDA
C-':.
-'
*Clear controller from console; cannot start motion and clear con t roll e r in same
function.
01.
NAM
BOOTSTRAP
02.
ENT
START
LDQ
=N$A1
PTR DIR FUNC
04. POO02 OA20
ENA
$20
START l\1:0TION*
05. POO03 03FE
OUT
-1
06. POO04 ODFE
INQ
-1
SET TO READ
07. POO05 OBOO
NOP
INP
-1
INPUT LEADER
09. POO07 0113
SAN
3
10. POOOS lSFD
JMP*
LOAD1
11. POO09 OBOO
NOP
03. POOOO EOOO
POOOI 00A1
START
OS. POO06 02FE
LOAD1
12. POOOA 02FE
LOAD2
C
INP
-1
INPUT FRAME
13. POOOB OFCS
ALS
S
SIDFT TO PACK
14. POOOC OBOO
NOP
15. POOOD 02FE
INP
-1
INPUT NEXT FRAME
16. POOOE 6C04
STA*
(ADDRES)
STORE WORD
17. POOOF 0103
SAZ
EXIT-*-l
EXIT ON ZERO WORD
IS. P0010 DS02
RAO*
ADDRES
UPDATE ADDRESS
19. P0011 lSFS
JMP*
LOAD 2
GO GET NEXT WORD
20. POO12 0014P
ADDRES
ADC
*+2
LOAD AT POO14
21. POO13 0000
EXIT
NUM
$0
ZERO FOR SLS
END
START
22.
I
EXIT
OOFF
0013P
/
..
BOO!ST
.,.;
START
1725
OOOOP LOAD1
0006P LOAD2
Where
'
BOOTSTRAP
loaded
0012P
Set Stop switch up and program will stop
after reading paper tape. Run and loaded
PG M will execute.
7-S
! .• ,
OOOAP ADDRES
r~
o
7.1.7
7.1.7 Status
The paper tape reader has been pro g ram me d "r'ithout the uFle of interrupts for
each of the above examples. Status may be taken on the paper tape reader at any
time to monitor the progress of the operation or to ass u r e the program that the
operation was com pIe ted correctly. Status is taken by setting the Q register
and issuing an INP instruction.
LDQ
NOP
INP
=N$OOAI
PTR FUNC/STATUS
-1
STATUS TOA
The status is now in the A register. The status conditions exist if a 1 is present
in the corresponding bit position.
15
A
C)
11
~~~~
10
9
t
8
i
7
6
5
I I
4
~
3
2
1
0
I I I
POWER ON+
PAPER MOTION FAILURE
EXISTENCE CODE
PROTECTED
LOST DATA
ALARM
11
DATA
INTERRUPT
BUSY
READY
Ready (bit 0): Power is on and paper tape has been loaded into the reader. The
preparations have been made lmown to the logic by pressing the READY switch on
the paper tape reader console. The reader beconles not ready if a paper motion
failure occurs or if the power is turned off.
Busy (bit 1): The paper tape reader is busy if a start motion command has been
issued and no stop motion command has followed. Motion stops on a stop motion
command, a paper motion failure, or if the power is turned off.
Interrupt (bit 2): An interrupt condition exists. Other status bits must be examined to determine the condition causing this interrupt.
Data (bit 3): The data hold reg is t e r in the paper tape reader contains an 8-bit
frame of data which is ready for transfer to the computer. Start motion must be
set to receive this status. The s tat us· drops when the data hold reg is t e r is
emptied by transfer to the computer.
()
7-9
7.1.7
Alarm (bit 5): At least one of the following con d i t ion s exis ts in the paper tape
reader: (1) paper motion failure (bit A9), (2) lost data (bit 6), or (3) power off
(bit A10 is 0).
(~=
Lost data (bit 6): When in interrupt on data mode, paper motion continues after
the data hold register is full. If the data is not t ran s fer red to the computer
be for e the next frame appears, a los t data status occurs to show a f ram e has
been passed. The time between frames is 2.857 milliseconds. The status drops
when a clear controller command is sent. Lost data stops tape motion.
Protected (bit 7): The PROGRAM PR OT E C T switch is on. This switch on the
paper tape reader works in conjunction with the PROGRAM PROTECT switch on
the computer. If the switch on the computer is off and the PROGRAM PROTECT
switch of the peripheral device is on, no action is taken but the status bit is set to
indicate the switch is on. If the switch on the computer is set, all rules of program pro t e c t ion apply. The paper tape reader in this condition only accepts
protected instructions.
Existence code (bit 8): The paper tape rea d e r is at t a c h e d.
the reader is missing from the particular computer system.
If the bit is a 1,
Paper motion failure (bit 9): No change in the feed hole circuit has occurred for
40 milliseconds while trying to read. The paper motion failure causes the reader
to become not ready; it can only be made ready by pushing the READY switch or
by a clear controller command. It is con sid ere d an illegal operation to send
any other function code or a read command to the reader until the READY switch
has been pressed or a clear controller has been issued.
Power on (bit 10):
Power to the rea d e r is on.
If this bit is a 0, power is off.
7.1.8 Interrupts
The paper tape reader may be programmed with interrupts by s imp I y selecting
the desired interrupts and exiting to the operating system or continuing execution
of instructions within the progra~. When a selected interrupt is generated, control will be returned to the program.
LDQ
ENA
OUT
ENA
OUT
Exit
=N$00A1
1
-1
$34
-1
PTR FUNC/STATUS
CLR CONTROLLER
FUNC TO PTR
START MOTOR, ALARM, DATA
FUNC TOA
When the interrupt returns control to the program, status must be taken to determine w hi c h of the two in t err u p t s was generated, data or alarm. If the data
interrupt was generated, the programmer b r in g s the data into A and saves it.
Once the data is saved, a check should be made to determine if all data has been
7-10
(".
7.1.8
transferred. If the operation was not complete, the pro g ram mer should reselect interrupts and exit, waiting for the next interrupt.
7.2 BUFFERED I/O EXAMPLE
The A/Q channel prohibits the execution of other instructions while data is being transferred. The reason is obvious: the Q register and A register, which are used for I/O,
are also the arithmetic registers. A direct storage access (DSA) channel may be connected to the 1704. The DSA transfers data di re c tly to memory, bypassing the A and
Q registers. Therefore, apr 0 g ram may be executing while data is being transferred.
The direct storage of data is ref err e d to as BUFFERING. The A/Q channel is used to
send functions and receive status, but the data is transferred via the DSA. The disk is
an example of a buffered device.
1704
A/Q
DSA
7-11
1
7.2
SIDE VIEW:
850 DISK PACK
(6 DISKS)
\._.-
,1.-__________ _ DISK SURFACE 0
DISK SURFACE 1
------i-----..s..c-- - - - - -
-
- -
DISK SURFACE 9
TOP VIEW:
DISK SURFACE
r----~
CYLINDER 00...1
SECTOR 14
CYLINDER 99£ SECTOR 15
SECTOR 0
SECTOR 1
DIRECTION OF
ROTATION
853 contains 100 cylinders; 854 contains 200 cylinders.
Figure 14. Side and Top Views of 850 Disk Pack
7. 2. 1 Disk Functions
The program s e 1 e c t s the disk by setting the Q register with the e qui pm e n t
number and the desired director bits. Throughout this discussion the disk shall
be considered equipment number 8.
7-12
.
7.2.1
15
Q
I0
14
13
12
11
o
o
o
o
I
10
1
9
0
8
0
7
0
I
\ . . . __---..V _---J'
6
5
4
3
o
o
o
o
o
1
2
D
EQUIP 8
The setting of the director bits will define the operation and the information to be
sent from or received in the A register.
A
(A) depends upon D field of Q
I
Q
C)
DISK FUNCTION CODES
Value Set in Q
(Bits 02-00)
001
010
011
100
101
110
111
Output from A
Input to A
Director function
Load address
Write
Read
Compare
Checkword check
Write address
Director status
Address register status
'i/)
\ ....... 1
7-13
D
I
7.2.1.1
7.2.1.1 Director Function
D = 001 , OUT
LDQ
LDA*
NOP
OUT
FUNC
DISK FOR FUNC
FUNC IN A
-1
FUNC TO CONTROLLER
=N$0401
A
UNIT SELECT
RELEASE
ALARM INTERRUPT
END OF OPERATION INTERRUPT
READY & NOT BUSY INTERRUPT
CLEAR INTERRUPT
The clear interrupt fun c t ion will clear all selected in t err u p t s, allowing the
pro g ram mer to select the in t err up t s hde desires. Threedinlterrupts may be
selected: next ready and not busy status, en of operation, an a arm. The next
ready and not busy in t err u p t occurs when the 1738 becomes not busy but still
holds its ready status.
The end of 0 per a t ion interrupt allows the controller to inform the 1700 when
it has completed an 0 per at ion such as a data transfer. The alarm interrupt
will notify the 1700 that an alarm condition has arisen. There are eight possible
alarm conditions: not ready, checkword error, lost data, seek error, add res s
error, defective track, storage parity error, and protect fault.
The release function allows an unprotected pro g ram to use the disk even though
the protect switch on the disk is still set. A protected pro g ram must issue the
release function. The next time a protected program accesses the disk, the disk
will become protected and must again be released before it will become accessible
to an unprotected program.
The unit select and unit select code will al way s be zero unl e s s two disks are
connected to the con t roll e r. Bit 8 is the unit select bit. It informs the controller that the pro g ram will select unit 0 or unit 1. Bit 9 indicates which unit
bit 8 wishes to select. If 9 bit is a 0, unit 0 is s e 1 e c ted; if it is a 1, unit 1 is
selected. The controller ignores bit 9 unless bit 8 is set.
7-14
C
c
7.2.1.2
7. 2. 1. 2 Load Address Ftmction
D = 010 , OUT
Once the functions have been sent to the controller, the program notifies the controller of the beginning add res s on the disk to be used by the program. The Q
register is loa de d with the D portion set to 010 and the disk add res s (sector
record address) is placed in the A register (Figure 14).
LDQ
LDA
=N$0402
=XDISKAD
DISK FOR DISK ADDR
ADDR IN A
-1
ADDR TO THE DISK
Nap
OUT
The controller will position the Read/Write heads on the requested address. The'
heads will be moved directly to the address forward or backward, depending on the
cu rr en t location of the Read/Write heads. The address held in the A register
will be in the following format.
15
8
7
4
AIL ___________________c_Y_L_I_ND
___E_R
____________- L_________
H_E_A_D______
3
0
~_______SE_C___T_O_R___~I
The disk has been functioned and g i v e n the desired disk address. The next step
will be to initiate one of three operations.
WRITE
READ
COMPARE
D = 011
D = 100
D = 101
7. 2.1. 3 Write Ftmction
D = 011 , OUT
The write function code reques ts the con t roll e r to prepare to read data from
memory and write it on the disk.
LDQ
LDA
OUT
=N$0403
=XMEMADR
-1
DISK TO WRITE
MEMORY ADDR IN A
WRITE OPERATION INITIATED
The controller expects to find the first word address minus 1 (FWA-1) of the buffer area in the Are g is t e r when the write function is received. The controller
goes into memory via the DSA to the FWA-1, at which location the controller extracts the last word add res s plus 1 (LWA+1). The controller keeps the LWA+1
and upda te s the FWA-1 tmtil the two are equal; at this point the write operation
is complete. The controller updates the address each time a 16-bit data word is
transferred from memory.
7-15
7.
2.1~
3
DATA BUFFER FOR DISK
,----.- - - - I
I
I
LWA + 1
I
I
FWA---
DATA
LWA-'~------------------~,
FWA - 1 MUST CONTAIN LWA + 1 OF BUFFER
Prior to issuing the write operation, the interrupts must be selected, the sector
record add re s s must be sent to the controller and the LWA+1 of the buffer area
must be at the FWA-1.
LDQ
LDA*
NOP
OUT
LDQ
LDA
NOP
OUT
LDA
STA
LDQ
LDA
NOP
OUT
=N$0401
FUNC
DISK FOR FUNC
SELECTED INT IN A
-1
INT SELECTED
DISK FOR DISK ADDR
ADDR IN A
=N$0402
=XDISKAD
=XLWAP1
FWAMI
=N$0403
=XFWAM1
HEADS POSITIONED
LWA+1 IN A
LWA+1 AT FWA-1
DISK TO WRITE
FWA-1 IN A
-1
OPERATION INITIATED
-1
The 1704 continues executing ins tructions while the disk t ran s fer s data. When
the data has all been transferred or an alarm condition has arisen, the 1704 will
be notified.
7-16
7.2.1.4
o
7. 2.1.4 Read Function
D = 100 ; OUT
The read function code follows the same programming pro c e d u r e as the write
function, the differences being the D setting of Q and the fact that the disk reads
data into memory rather than writing data on the disk.
7. 2. 1. 5 Compare Function
D = 101 ; OUT
The compare function code follow s the same pro g ram min g procedure as the
read and write function codes. The compare function causes the con t roll e r
to read data from the computer's memory and compare it with the data stored on
the disk. If at any time during the compare, one word does not compare, the no
compare status bit will be set. This fun c t ion provides an extra c he c k on the
validity of the data transferred.
The checkword check (D=110) and write address (D=lll) functions are used by the
customer engineers.
7.2.2 Disk Status
o
7. 2. 2. 1 Director Status
D = 001 , INP
Status may be t a ken to m 0 nit 0 r the operation of the disk. Once the disk generates an interrupt, status must be taken to determine which interrupt was generated. This is a c com p lis he d by loading the Q register with the D portion set
to 001 and by issuing an INP instruction.
LDQ
NOP
INP
15
=N$0401
DISK FOR STATUS
-1
STATUS IN A
14
A
PRODUCT FAULT
STORAGE PARITY ERROR
DEFECTIVE TRACK
ADDRESS ERROR
SEEK ERROR
LOST DATA
CHECKWORD ERROR
PROTECTED
NO COMPARE
7-17
READY
BUSY
INTERRUPT
ON CYLINDER
END OF OPERATION
ALARM
7.2.2.1
The ready status in d i cat e s that the unit is available. The busy bit indicates
that the controller and/or the drive unit is presently involved in the performance
of an operation. This bit is set with the acceptance of a load address, write,
read, compare, checkword check, or write address function. At the completion
of the function which set the busy status, the status will be cleared and the disk
will become not busy. Once the disk is not busy, a new function may be issued.
The interrupt bit a c k now 1 e d g e s that an interrupt has occurred. Further examination of A will determine which of the three selected in t err u p t s was generated: bit 4 (EOP) and bit 5 (ALARM).
If neither bit 4 nor bit 5 is set, the pro g ram mer should check bits 0 and 1 for
ready and not busy. If the alarm bit is set, the pro g ram mer mus t determine
which of the eight alarm conditions caused the interrupt.
The on cylinder status bit 3 is set when the Read/Write heads have reached the
sector record address initially sent to the controller via the A/Q channel.
7. 2. 2. 2 Address Register Status
D = 010 ; INP
The programmer may request the disk to return the current position of the Read/
Write heads at any time by selecting the disk as above but issuing an INP instruction.
LDQ
NOP
INP
=N$0402
DISK FOR DISK ADDR
-1
CURRENT ADDR IN A
The address will be in the same format used to send the address to the controller.
7. 2. 3 Summary, Buffered 1/0
The DSA provides the 1704 with a means of storing data directly in memory; this
permits the execution of instructions while transferring data. The program sends
the function word, the sector record address, and stores the LWA+1 of the buffer
area at the FWA-1 prior to initiating an operation. The operation is indicated by
the D portion of Q, with the A register containing the FWA-1 of the buffe-r area.
The con t roll e r interrupts the 1704 when a selected interrupt condition arises.
The program takes status to determine which of the selected interrupts was generated.
7-18
('
_/
CHAPTER VIII
SYSTEM REQUESTS
o
II
CHAPTER VIII - System Requests
G
TOPIC
•
C)
(1
'-../'
PAGE
8.1
Operating Systems
8-1
8.1.1
utility
8-1
8.1.2
MSOS
8-1
8.2
Request Processing
8-1
8.2.1
Summary of Request Processing
8-3
8.3
Requests
8-4
8.3.1
Exit Request
8-7
8.3.2
Read/Write Reques ts
8-8
8.3.2.1
Format of the Read/write Request
8-9
8.3.2.2
Request Code
8-10
8.3.2.2.1
Format of Records
8-10
8. 3.2. 2. 1. 1
Teletype
8-11
8.3.2.2.1.2
Paper Tape Reader and Paper Tape Punch
8-11
8. 3. 2. 2. 1. 3
Mass Storage Addressing
8-15
8.3.2.3
X Bit
8-15
8.3.2.4
Request Priority
8-16
8. 3.2. 5
Completion Priority
8-16
8. 3. 2. 6
Completion Address
8-16
8.3.2.7
Thread Word
8-19
8.3.2.8
Error Code
8-19
8.3.2.9
Mode
8-19
8.3.2.10
A Field
8-19
8.3.2.11
Logical Unit
8-19
8.3.2.12
Number of Words
8-24
8.3.2.13
Starting Address of Buffer
8-24
8.3.2.14
Setting Up RW Requests in Background
8-28·
8.3.2.14.1
Looping on the Thread Word
8-28
CHAPTER VIII - System Requests (Cont)
TOPIC
•
•
•
". ..
PAGE
8.3.2.14.2
Looping on a Flag
8-28
8.3.2.14.3
Scheduling Out of the Completion Routine
8-29
8.3.2.15
Examples of Programs Using Ilo Requests
8-30
8.3.3
Schedule Reques t
8-36
8.3.3.1
Format of Schedule Request
8-36
8.3.3.2
Request Code
8-37
8.3.3.3
X Bit
8-37
8.3.3.4
Priority
8-37
8.3.3. 5
Address
8-37
8. 3. 3. 6
Example of Schedule Request
8-38
8.3.4
Timer Request
8...;40
8.3.4.1
The Format for the Timer Request
8-40
8.3.4.2
Request Code
8-41
8.3.4.3
X Bit
8-41
8. 3.4.4
Units
8-41
8.3.4.5
Priority
8-41
8.3.4.6
Address
8-41
8.3.4.7 .
Q Parameter
8-41
8.3.4.8
Example of Timer Reques t
8-42
8.3.5
Status Request
8-42
8.3.5.1
Format of the Status Request
8-42
8.3.5.2
Request Code
8-43
8.3.5.3
X Bit
8-43
8.3.5.4
A Field
8-43
8.3.5.5
Logical Unit
8-43
8.3.5.6
Address of Parameter List
8-43
8.3.5.7
Reply to Status Reques t
8-44
8.3.5.7.1
Hardware Status
8-45
~
\,•...
/
(-~
\
('
\.,.
/' ..
Chapter VIII - System Requests (Cont)
,.
~)
TOPIC
•
0
•
•
•
PAGE
8. 3. 5.7. 2
Word 8 of PDT
8-45
8. 3. 5.7.3
Current Buffer Address
8-47
8. 3. 5. 8
Example of Status Reques t
8-47
8.3.6
GTFILE Request
8-47
8. 3. 6.1
Format of GTFILE Reques t
8-48
8. 3. 6. 2
Request Code
8-49
8. 3.6. 3
X Bit
8-49
8.3.6.4
Request Priority
8-49
8. 3. 6. 5
Completion Priority
8-49
8. 3.6. 6
Completion Address
8-49
8.3.6.7
Mode
8-49
8. 3.6. 8
A Field
8-49
8. 3. 6. 9
Logical Unit
8-49
8.3.6.10
Word Addresses: wI, w2
8-50
8.3.6.11
Starting Core Addres s
8-50
8.3.6.12
File Name Address
8-50
8.3.6.13
Example of a GTFILE Request
8-51
8.3.7
Loader Request
8-54
8. 3.7. 1
Format of the Loader Request
8-55
8.3.8
Core Reques t
8-55
8. 3. 8. 1
Format of Core Reques t
8-56
8.3.8.2
Example of Core Request
8-56
8.3.9
INDIR Request
8-59
8. 3.9. 1
Format of the INDIR Request
8-59
8. 3. 9. 2
Example of the INDIR Request
8-59
8.4
Problem
8-60
c)
8.1
8.1 OPERATING SYSTEMS
The 1700 computer system has two commonly used operating systems: the utility system
and the mass storage operating system (MSOS). MSOS is a disk or drum oriented system and all 0 cat e s the resources of the computer according to a priority system. The
utility system is a much smaller system. It provides for assembly, loading, and execution of programs in a batch mode.
8. 1.1 utility
The 1700 utility system provides the 1700 computer with a means of loading and
executing programs in configurations smaller than the minimum required for the
1700 operating system. The utility system requires 8K of core but no disk or
drum. I/O is by way of the paper tape rea d e r and paper tape punch, and lis ting
and operator control is t h r 0 ugh the teletype. * Ex e cut ion of jobs through the
utility system can make use of the standard drivers provided by utility. The
standard drivers provided are for the teletype, paper tape input, and paper tape
output. It is possible, then, to operate these devices in one's own pro g ram by
simply using a standard calling sequence.
8.1.2 MSOS
o
Under MSOS core is divided into two areas: foreground and background. The
foreground is for s y s tern and process programs. System programs are those
programs that make up the operating system, such as the job processor and
drivers. Pro c e s s programs are those application programs that are most important to the particular installation. For example, if the system is controlling a
chemical plant operation, those programs monitoring the chemical pro c e s s are
the pro c e s s programs. The pro c e s s programs and system programs usually
have the highest priority and have access to the resources of the computer first.
Foreground is protected; this means the on-line process programs cannot be destroyed by programs in the background and they cannot be inadvertently brought
into execution by background programs. However, b a c kg r 0 u n d programs may
make use of protected routines such as I/O drivers.
Backgr ound programs are run in a batch mode (serially) and run at the lowest
priorities in the system. Programs in the background are called jobs. Assembling, compiling, and loading are examples of such jobs.
8. 2 REQUEST PROCESSING
Three basic functions of the 0 per at in g system are to: (1) allocate core space to those
pro g ram s that want to use it, (2) communicate with the outside world, i. e., supervise
I/O operations, and (3) allocate CPU time between the various programs. When a program wants one of these functions done, a request is made to the operating system.
o
*There are other options available.
8-1
8.2
Are que s t takes the form of a transfer of control to the module of the operating system
that processes requests (the request entry processor, entry point name MONI) followed
by words containing the necessary parameters for the particular request.
,r---.,
(
,
'----/
The entry ad d res s for MONI is always located in core location F4 so every request is
initiated by an indirect return jump through F4. The return jump will provide the linkage necessary. The parameter string length is different for different requests:
54F4
RTJ
($F4)
TO MONI
Reques t code
and other parameters
=1
In the first parameter word, bit positions 9 through 14 will be the request code. This is
for all requests.
MON! saves the registers of the requesting program in a special core area called volatile
storage and gives control to a request processor denoted by the request code in the parameter list. This processor must return control to the request exit processor which returns control to the requesting program.
The 1700 ope ra ting system provides the user with up to 30 monitor requests; 20 are
reserved for the operating system. However, they may be replaced by user-written processors when the system is initiated. The other 10 requests may be added at initialization
by including in the resident load the necessary programs with the required entry points.
The number of possible request processors can be extended from 30 to 63 by reassembly.
C
Each request processor is a separate submodule and has a coded entry point with one of
the following names:
T1
.:\,---.---~-
reserved for system use
T20
T21
:
~r--_ _ _ _ available to users
T3J
The numerical part of each name is the request code. It corresponds to the value of an
index to a table of request processor addresses contained in MONI.
MONI has these entry points as externals providing linkage with each appropriate request
processor.
Since the numeric part of the entry point name for each request processor must correspond to its request code, a request code of 5 will provide entry through MON! to module
T5.
c~
8-2
8.2
G
User
Requests
..
...
Request
Entry
Processor
...
I
T1
I
Request Submodules
c;J
I
I
I
::
~
Users can asselnble an added request processor, as sign a request code to it, and affix
the entry point with T followed by the number for the request code and incorporate it as
part of the sys tem.
8. 2.1 Summary of Request Processing
Note that all requests begin with the return jump toMONIand that MONIdetermines which
type of request it is by examining the request code in the first word of the parameter
string. Each type of r e que s t has a request processor to which MONI g i v e s control,
depending on the request code. When control is given to the request processor, several
functions take place before control is returned to the requesting program.
o
It is important for the programmer to understand that a request only initiates action desired of the operating system. It does not do anything. In most cases, a request causes
the des ire d action only to be put on a queue; control is returned i m me d i ate 1y to the
requestor at the next instruction beneath the parameter string.
For example, it is desired to write a message on logical unit 4:
REQ
RET
~
RTJ- ($F4)
(Parameters for a
write request on
logical unit 4)
~
Control is passed to MONI. MONI passes control to the Read/Write request processor
which puts the request on a queue of other messages waiting to be printed on logical unit
4. Control then passes to the request exit routine which returns control to the requestor
at RET. The message has not yet been written but it will be done in due time.
o
8-3
8.2.1
RTJ- ($F4)
~
/
~;propriat~
request
TO MONI - - processor;
t
eques
"'Reque~s~ processor
gets on a
exits
queue
~
~
Back
to
program
TOREQXT
Figure 15. Flow of Requests
8. 3 REQUESTS
The following requests are included in the standard operating system:
READ *
WRITE *
FREAD*
FWRITE*
SCHEDULE
TIMER
Available to both foreground and
background programs.
EXIT *
CORE
LOADER
GTFILE
STATUS*
SPACE
RELEASE
Available only to background programs.
Request processor modules for these
requests must have the same residency
as the job processor.
)
Available only to foreground programs.
INDIR is an indirect version of any of the listed requests.
The job processor can make any request.
*These requests are included in the utility system.
8-4
R
8.3
c)
System macro calls are available to generate the code for the requests under the macro
ass em b 1 e r, which runs under MSOS. Codes for the requests under the utility system
must be coded by the programmer.
In this chapter those requests that are available to b a c kg r 0 u n d programs will be discussed. Those requests available only to for e g r 0 un d programs will be discussed in
Chapter 11.
Any of the allowable requests for background programs will be accepted by the operating
system and put on the desired queue. They will not be rejected.
o
o
8-5
8.3
RC
NUM
5
OAOO
(r-., ,
'-_/
EXIT
FWRITE
Q,
c, s, n, m, rp, cp, a,x*
6
OCXX---
]
.~
Po ....
§~
C,,)
'0
~
Q)
~
0
0014
0014
0014
0014
0015
0015
0015
0016
0017
,0017
0017
0017
0017
0017
om8
0018
0018
0019
0020
0021
0022
0022
0022
0023
NAM
CARD TO PRINT
*
*TIDS PROGRAM USES SYSTEM REQUESTS TO READ AND WRITE
*
POOOO 0028
ENT
EXT
BSS
BUF
::::;:::r:
*
~_--ISTART
P0028
P0029
P002A
P002B
P002C
P002D
P002E
START, PRINT
IOERR ......-- error subroutine
BUF(40) _
data buffer
RD
54F4
0801
0031 P
0000
100C
0028
0000 P
,
ADDR
T'
'or' f' ,t bitF:~t"'d
11
4 0, A
Buffer
CP = 1
RP= 0
ASCII mode
40 words
Read is initiated
EXIT Macro
EXIT
P002F 54F4
Jump to dispatcher (EXIT Request)
P0030 OAOO
No work to do until Read completed
Read completed *
P0031 0162 'COMPRD
SQP
SCHPRT
Q15 = 0 if no Read error
P0032 5400 X
RTJ
Q15 = 1 if error
IOERR
P0033 7FFF X.---_~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
SCHDLE
PRINT,O,Q
Schedule Macro
.---_---lSCHPRT
Xbit= 0
P0034 [54F4
Schedule PRINT at
P0035 1200
priority 0 before exit
RP= 0
P0036 0039 P from completion routine
EXIT
P0037 154F4
Jump to dispatcher at end of completion
P003810AOO
Dispatcher will now go execute PRINT at priority 0
,-----1
t
~--~*~-------~-------~-~-------------~-----
, , tt
1 11
1
PRINT
FWRIT~on~:t COMr PR • BU F. 3 5' A 0 1t'
bi::r:atted Write Macro
54F4
OC01
LUN COMPL
Indirect bit for LUN
0042 P
CP= 1
ADDR
0000
Buffer
RP = 0
18FC
Write is initiated
ASCII mode
0023
35 words (on TTY)
0000 P
EXIT Macro
EXIT
54F4
Jump to dispatcher
L;O.:,:A:. :O. .:,O__..L7N:..,:o_w;,;..o:.:r:..,:k:...t:.:o:.....d.:.:o:.....::un.:.:t:..:il::......:..:W:..,:r...:,it:..:e:.....c:.:o:.,:m:::;p!:,;l:.,:e.:.;te:..;d=----_____________________________
*
0162
SQP
FIN!
NO 10 ERR
COMPPR
5400 X
RTJ
IOERR
,-----1
P0039
P003A
P003B
P003C
P003D
P003E
P003F
P0040
P0041
P0042
P0043
P0044 0033 X
r---------------------~---------------------EXIT Macro
EXIT
FIN!,
P0045 154F4
P0046 .OAOO
I
[
~---~----=E~N=D--~S=T~A=R=T~----------------
Entry points
OOFF START
0034P COMPPR
I
SCHPRT
0001
0002
0003
0004
Read Macro
POOOO 18FF
CARD
IOERR
OOFF
2210
2257
0028P PRINT
0042P' FIN!
IOERR
}
IOERR
0039P BUF
0045P IOERR
NAM
ENT
IOERR
IOERR
o
o
NUM
E;ND
$18FF
where pgms loaded
OOOOP
(J
8-31
OOOOP COMPRD
0044X
II0
4---
0031P
subroutine
Hang instruction used for
checkout
8.3.2.15
Reads and writes initiate r/ o. Control returns to next ins truction in program before r/o
is done. Job I/O is done at priority O. Program should not loop waiting for r/o to be
done.
·. - -·. .'"
l
.,'
Completion add res s is entered when r/o is done, at priority 1. It should be short and
exit to dispatcher. Check Q for r/o errors.
This JOB does not check Q after Request, to see if Request accepted (Q15 = 0).
not have to but system programs must.
Jobs do
--------------------------
------------------------~
TTY Printout
*p
J
*ASSEM
J
*p
J
*L,8
J
*
X"
.___No MAP
Ar
THIS PROGRAM WORKS ON THE 1700 COMPUTER SYSTEM UNDER MSOS 2.0 Formatted Write (
J
'-.......
For program checkout, hang instruction could also be used to see if com pIe t ion r
entered.
0019
0020
0021
0021
0021
0022
0023
P0042 0172
*
COMPPR
P0043 54F4
P0044 OAOO
P0045 18FF
HANG
SQM
EXIT
HANG
NUM
END
$18FF
START
8-32
0
uti n e
8. 3. 2. 15
(j
EXAMPLE READ/WRITE PROGRAM
JOB
0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
OOEA
0000
START
54F4
0201
0009 P
0000
100C
0028
001F P
POOOO
POOOI
POO02
POO03
POO04
POO05
POO06
POO07
NAM
ENT
EXT
EQU
0
RTJNUM
ADC
NUM
CARD TO PRINT
ST ART, PRINT
IOERR
ADISP($EA)
0
($F4)
$0201
COMPRD ~
0, $100C
Initiate FREAD
READ, CP = 1 RP = 0
Completion Address
THREAD, LUN CR = 12, ASCII
NUM
ADC
40
BUF
ONE CARD TO READ
FWA BUFFER AREA
Control returns beneath parameter string after Read is initiated. If program has
nothing to do, it should exit until completion routine is entered. Unprotected program
can exit to dispatcher.
0012
JMP-
P0008 14EA
(ADISP)
When Read is finished control will go to completion address COMPRD.
routine should check bit 15 of Q for 110 errors and exit to dispatcher.
o
0013
0014
0015
0016
0017
0018
0019
P0009
POOOA
POOOB
POOOC
0162
COMPRD
5400 X
7FFFX
54F4
SCHPRT
I
POOOD 11200
POOOE 0011 P
POOOF 54F4
P0010 OAOO
I
I
SQP
RTJ
SCHPRT
IOERR
RTJNUM
ADC
RTJNUM
($F4)
$1200
PRINT
($F4)
$AOO
Completion
Schedule PRINT at priority 0
before exit, to drop priority
back to O.
EXIT REQUEST
Dispatcher will pass control to Print after read completion routine exit.
0020
0021
0022
0023
0024
P0011
P0012
P0013
P0014
P0015
P0016
P0017
54F4
PRINT
0401
001A P
0000
1009
0023
001F P
RTJNUM
ADC
NUM
($F4)
PRINT, CP = 1 RP= 0
$0401
COMPLETION ADDRESS
COMPPR
0,$1009,35
35 words on TTY
ADC
BUF
Control returns l).ere after print is initiated.
patcher.
0025
0026
P0018 54F4
P0019 OAOO
I
I
RTJNUM
FWA BUFFER
Exit Request is same as jump to dis-
($F4)
$AOO
After print is done, control goes to COMPPR at priority 1. Here exit from program.
0027
0028
0029
0030
0031
0032
P001A 0162
COMPPR
P001B 5400 X
P001C OOOB X
P001D 54F4
FINI
POOlE 10AOO
P001F 0028
BUF
I
SQP
RTJ
FINI
IOERR
RTJNUM
BSS
END
($F4)
$OAOO
BUF(40)
START
8-33
EXIT WHEN THRU
8.3.2.15
TTY Printout. Read/Write Program
Not using system macros.
Coding requests as in example will produce much faster assembly time than when using
macros.
*p
J
*ASSEM
J
*p
J
*L,8
J
*X, N
~The E message noted unpatched externals (IOERR). The * @typed by operator
~
~H,fS
J
said to ignore them.
PROGRAM WORKS ON THE 1700 COMPUTER SYSTEM UNDER MSOS 2.0
~
output from WRITE
Unformatted Write did not do line feed as there are no line feed/ CR in unformatted Write.
Formatted Write should be used on print devices such as TTY and LP.
Unformatted Write on printer does not work correctly. The printer buffer is filled but
the line is not printed until the next output line is sent to the printer.
8-34
c
8. 3. 2. 15
C)
Read formatted ASCII data records from paper tape into BUF area and type it out.
Assume the BUF area is larger than the formatted record. Con tin u e until the
reader runs out of tape, giving an error.
FLAG
BEGIN
START
READIT
o
MORE
READY
NAM
ENT
BSS
ADC
0
CLR
STA*
RTJNUM
ADC
NUM
ADC
LDA*
SAN
JMP*
LDQ
SQP
RTJNUM
CLR
STA*
RTJNUM
ADC
NUM
ADC
LDA*
SAN
JMP*
JMP*
RAO*
STQ
RTJNUM
BEGIN
BUF(30), STAT(1)
Flag for swi tching
0
0
A
Clear flag
FLAG
Format read L U2 is paper tape
($F4)
reader
where to go when fin$800
ished
READY
0,$1002,30
BUF
Hang until flag set by compleFLAG
tion routine
1
*-2
STAT
MORE-*-1
Exit request on input error($F4)
end
job
$AOO
Clear flag
A
Hang
until flag set by compleFLAG
tion
routine.
Type out format
($F4)
$COO
READY
0,$1004,30
BUF
FLAG
1
*-2
START
Completion routine sets flag
FLAG
Exit back to program
STAT
($F4)
$AOO
8-35
8.3.3
8. 3.3 Schedule Request - Request Code 9
The schedule request is available only under MSOS.
Programs occur in the 1700 run at 16 different priorities, 15 (high) to 0 (low). A
program can schedule a section of coding to be executed at a certain priority level.
The address of the scheduled coding can be either in the s c h e d u I in g program,
external to it, or in the system.
If the desired priority of the scheduled program is higher than the running priority
. of the scheduling program, a pseudo interrupt occurs and the scheduled program
is executed immediately. In this way a schedule reques t can be con sid ere d a
jump that also changes the running priority. Control Will return to the "interrupted" program when the scheduled program exits.
If the desired priority of the scheduled program is not higher, it is threaded onto
a queue of programs waiting to be executed, in order of priority. In this way one
program may schedule another to be executed at a different priority after the
scheduling program exits.
Background programs can be scheduled to run at levels 0 and 1 only.
A parame ter may be pas sed in the reques tor f s Q reg i s t e r to the program being
scheduled.
8. 3. 3. 1 Format of Schedule Request
RTJ-
REQ
15
0
rc
x
rp
p
c
14
0
($F4)
8
7
x
0
0
c
Completion Address
9
0
1
0
0
1
0
4
0
0
3
p
request code, 6 bits: 9
relative/indirect indicator, 1 bit: 0 or 1
this field is ignored by the scheduler
priority, 4 bits: 0-15
address of program scheduled
The macro call is:
REQ
SCHDLE
c,p,x
REQ will be on the 54F4, which will be g en era ted by the macro. REQ+ 1 is the
first word of the parameter stringlO-
8-36
_0
8. 3. 3. 1
\
An example of a coded call would be:
RTJ-
($F4)
NUM
$1201
ADC
PGM
(schedules PGM at priority 1)
8.3.3.2 Request Code
This field is always 9 for schedule requests.
8. 3. 3. 3 X Bit
The x bit is used in conjunction with the c parameter.
relates to this parameter.
It will be discussed as it
8.3.3.4 Priority
The p field is the priority at which the programmer desires to run the scheduled
program. The priority may be greater than, e qua I to or less than the program
that schedules it. However, in the background it is always 0 or 1.
o
8. 3. 3. 5 Address
The c field contains the address of the program being scheduled. The x parameter de t e r min e s the forms the c may take as it did for the c parameter of the
read/write reques ts.
x
o or blank
c
The meaning of c
c
c is the address.
i. e., SCHDLE
PGM, -, PGM is assembled as an absolute address (program relocatable).
~O
c
~blank
c is relative.
c is a positive increment added to the address
of the first word of the parameter list to locate
the address.
i. e., SCHDLE
PGM-*+1, -, X
In this example PGM is the address.
(c)
c is an index to the system directory.
set bit 15. x has no meaning.
l)
8-37
The ( )
8.,3.3. 5
Note that there is no indirect form and that the option (c) cannot be used in the
background because programs in the system 1 i bra r y may not be scheduled from
the background; see Chapter 11.
C~'
8.3.3.6 Example of Schedule Request
The following example program writes one message from pro g ram SCHEDULE
and then schedules TWO (the entry point in pro g ram NEXT) to run at priority 1
and write another message.
c
.,
8-38
8. 3.3. 6
0
0001
0002
0003
0004
0005
0005
0005
0005
0005
0005
C)
0006
0006
0006
0007
0007
0007
0007
0008
0008
0008
0009
POOOO
POOOI
POO02
POO03
POO04
POO05
POO06
4558
414D
504C
4520
4E4F
2031
2E20
POO07
POO08
POO09
POOOA
POOOB
POOOC
POOOD
54F4
OC01
0010 P
0000
1004
0006
0000 P
0004
0004
0004
0004
0004
0004
XA
FWRITE
4, XB, MA, 6, A, 0, 1, A
EXIT
XB
SCHDLE
TWO,l
P0010 54F4
P0011 1201
P0012 7FFF X
EXIT
POO13 54F4
POO14 OAOO
END
OOFF
POOOO
POOOI
POO02
POOQ3
POO04
POO05
POO06
4558
414D
504C
4520
4E4F
2E20
3220
POO07
POO08
P0009
POOOA
POOOB
POOOC
POOOD
54F4
OC01
0010 P
0000
1004
0007
0000 P
XA
0007P
XC
OOOOP
MA
MB
NAM
ENT
ALF
TWO
FWRITE
0005
1 ENTRY POINT TABLETWO
XA
2E2F
()
SCHEDULE
XA
TWO
*, EXAMPLE NO 1. *
POOOE 54F4
POOOF OAOO
I
0001
0002
0003
MA
NAM
ENT
EXT
ALF
XB
NEXT
TWO
*, EXAMPLE NO. 2*
4, XC, MB, 7 ,A, 0, 1
EXIT
2F44
J
*X
EXAMPLE NO 1.
EXAMPLE NO. 2
8-39
0010P
TWO
0012X
8.3.4
'\
C
8.3.4 TIMER Request - Request Code 8
--'
The timer reques t is available only under MSOS.
Ahardware timing device such as the 1573 timer is required for the timer request
to work since there is no real time clock in the cpu.
The timer request is a scheduled request where the program is scheduled after a
predetermined time delay. The delay allowed will be from 1/60 second to 32, 767
minutes.
Parameters c, p, and x are specified as for the SCHDLE request. However, instead
of a parameter a time delay is specified in Q when the request is made. The delay
is specified in multiples of the basic unit of the timing device. The timer passes
the current contents of the core clock (E8) to the scheduled program in Q.
Timer requests are stacked in the s c he d u I e request stack but are not threaded
with them. Ins tead, they are threaded together on the basis of time until activation. When the delay for a timer request has expired, a SCHDLE request is made
by the system and the request is rethreaded into the SCHDLE thread.
The timer request is normally made by protected programs but it can be made by
jobs at levels 0 or 1.
The timer was different under MSOS 1. O.
8. 3.4. 1 Format for the ITIMER Request
RTJ15
0
14
rc
8
($F4)
9
8
x
c
7
u
0-3
4
3
p
0
0-15
Q
rc
x
u
p
c
Q
request code, 6 bits: 8
relative/indirect indicator, 1 bit: 0 or 1
type of units desired, 4 bits: 0 to 3
priority, 4 bits: 0-15
address of program to be scheduled
number of units desired: 1-32,767
must also be in Q register
The macro form for this reques t is:
TIMER
c, p, x, Q, u
("
"'-'
8-40
'
8.3.4.1
o
An example of a coded call woold be:
LDQ
RTJNUM
ADC
NUM
=N$0005
($F4)
$1024
PGM
5
(schedule PGM in 5 seconds to run at priority 4)
8.3.4.2 Request Code
Request code is 8.
8. 3. 4. 3 X Bit
The x bit is used in conjlUlction with the c parameter.
relates to this parameter.
It will be discussed as it
8. 3.4.4 Units
The type of lUli ts reques ted is s p e c if i e d bas ed on the bas i c unit of the timing
device.
u
0
1
2
3
0
basic units: 60/sec on 1573
1/10 second
seconds
minutes
The units field is used in conjunction with the Q parameter to calculate the desired
time delay and it controls the precision required in the timing.
8. 3.4. 5 Priority
This is the priority at which the scheduled program is to run. It follows the same
rules as in a schedule request.
8. 3.4. 6 Address
The c field contains the address of the program being scheduled and it follows the
same rules as for a schedule request.
8. 3.4.7 Q parameter
The Q parameter is the n u m be r of the type of units desired; it must be in the Q
regis ter and the Q word of the reques t.
()
8-41
8.3.4.7
For example, a timer request for 5 seconds could be either u=2 and Q=5, or u=l
and Q=50. If u=2, the request will be on the seconds thread and will be scheduled
in at leas t 5, but less than 6, seconds. If u=l, the r e que s t will be on the 1/10
second thread and will be s c h e d u led in at least 5 seconds, but less than 5 1/10
seconds. This is how the desired timing precision can be achieved.
8. 3.4. 8 Example of\ TIMER Request
Assume the basic unit of the system is 1/60 second. Schedule the program PGM
using an absolute call, after 20 minutes has elapsed, to run at priority 6.
ENQ
TIMER
20
PGM, 6, , 20, 3
8.3.5 STATUS Request - Request Code 3
This request is available to unprotected programs only. Foreground programs do
not use the status request to obtain status.
The status of a particular read/write request is obtained with the status request.
The status of the request is returned in the A, Q, and I registers.
The status request can be used to determine whether an I/O operation is complete,
to examine the type of hardware to which the logical unit is assigned, to check the
dynamic status on the hardware, or to find out how far along the 1/ a is by checking
the current buffer address.
8.3.5.1 Format of the STATUS Request
RTJ15
0
15
0
14
0
rc
0
0
12
0
($F4)
0
o
9
0
1
111 A 10
1
I
8
x
7
0
0
0
0
0
0
9
LUN
ap
address of parameter list
rc
x
request code, 6 bits: 3
relative/indirect indicator, 1 bit: 0 or 1
Q logical unit, 10 bits; modified by a, same as for read/write requests
a logical unit address indicator, 2 bits; same as for read/write requests
Settings are:
a = blank = 00: Q is the logical unit number
a= R
= 01: Q is a signed 'increment (±lFF)
a=I
= 10: Q is a core address (0< Q~3FF)
ap address of parameter list of request
8-42
0
0
0
0
C
8.3.5.1
o
The macro call is:
STATUS
Q,
ap, a, x
An example of a coded call would be:
RTJNUM
NUM
ADC
($F4)
$0600
0004
REQ+l
(Obtain status of a request on logical tulit 4; request address is REQ+l)
8.3.5.2 Request Code
The reques t code is 3.
8. 3. 5. 3 X Bit
The x bit is used in conjunction with the ap parameter and will be discussed as it
relates to that parameter.
8. 3. 5.4 A Field
The a bits modify the logical unit field in the same way as in the I/O request.
o
8. 3. 5. 5 Logical Unit
The logical unit is the same 10 gi cal unit upon which the I/O request was made
(the one we wish to have the status of). The logical unit may be specified directly,
indirectly or relatively, in the same way the logical unit was specified in the I/O
request.
8. 3. 5. 6 Address of Parameter List
The ap field is the address of the parameter list for the request for which status
is desired. It can be specified directly, indirectly or relatively, in conjunction
wi th the x bit.
x
ap
Meaning of ap
==0 or blank
ap
ap is the address of the firs t word of the parameter list of the I/O request.
i. e., STATUS -, REQ+l, -,REQ+1 is the parameter address.
~o
~blank
()
ap
ap is relative.
ap is a positive increment added to the address
of the first word of the status requestparameter
list to obtain the address of the first word of an
input/output reques t parameter lis t.
8-43
8. 3. 5. 6
x
ap
Meaning of ap
i. e., STATUS -, REQ+l-*+2, -, X
REQ+l is the parameter address.
=0
=blank
(ap)
ap is indirect
ap is the address of a I 0 cat ion containing the
add res s of the first word of an input/output
parameter list.
i. e., STATUS -, (REQADR), -,REQADR contains the address of REQ+l
~o
(ap)
;iblank
ap is double relative.
ap is a positive increment added to the address
of the first word of the status request parameter
list to obtain the address of a location containing
another positive increment. The second increment is added to the address of the first word of
the status reques t parameter lis t to obtain the
address of the first word of an input/output request parameter list. Because of wraparound
in adding, both increments may refer to locations ahead of or behind the status reques t.
i. e., STATUS -, (REQREL-*+2), -, X
REQREL contains a number to be added to the
firs t word of the status parameter list to form
the distance to REQ+l (s+l+contents of REQREL).
Although the parameter! address is not needed in the utility system, it is supplied
to be compatible with 1700 MSOS. If it is omitted, only device status will be returned.
8. 3. 5. 7 Reply to STATUS
Requ~st
Following execution of the status request, the A, Q, and I registers con t a i n the
status. The content of these registers is as follows:
A: hardware status of device
Q: word 8 of Physical Device Table for device
I: last core address of data transmission
8-44
('
8.3.5.7.1
8. 3. 5.7.1 Hardware Status
o
Hardware Status Reply
A
The hardware reply 1S dynamic unless the device is connected to a buffered data
channel and the channel is busy. If it is-not busy, the hardware reply is the status
obtained at the completion of the last request for that device. For an explanation
of hardware replies refer to the hardware specifications.
This status is the hardware reply bits on the device itself.
8.3. 5.7.2 Word 8 of PDT
See appendix D of the MSOS Reference Manual for contents of this word.
15
Q
I
14
13
11
10
4
S
E
T
Word 8
3
1
o
R
EREQST
Reques t Status
Bits
o
P - 0=1
1=1
R
2=1
[
3=1
T --4-10
Device not available to unprotected programs
Device may be read from unprotected pro g ram s
Device may be written by unprotected pro g ram s
Equipment table includes words 18-33 for message
buffering
Equipment type constant (T), see T table
S
Equipment Class, see Stable
E
un
i
Device failure
Operation is in progress
Operation is complete
14 = 1
15 = 1
= 0
STABLE
EQUIPMENT CLASS CODES
Word 8, EREQST Bits 11-13
o
1
2
3
4
5
6
7
Class not defined
Magnetic tape device
Mass storage device
Card device
Paper tape device
Printer device
Teletype device
Reserved for future use
8-45
8.3.5.7.2
T TABLE
(-.~:
STANDARD EQUIPMENT TYPE CODES
Word 8, EREQST Bits 4-10
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
1711/1713 Teletypewriter
1721/1722 Paper Tape Reader
1723/1724 Paper Tape Punch
1
J
43 ]
44
45-99
100-127
Unassigned
1738/853 Disk Unit
1751 Drum Unit
1729 Card Reader
1738/854 Disk Unit
601 Magnetic Tape Unit
Software Buffering Device
1742 Line Printer
1728/430 Card Reader/Punch
Software Core Allocator
210 CRT Display Station
1558 Latching Relay Output
1553 External Register Output
311B/312B Data Set Terminal
322/323 Teletype Terminal
Unassigned
166 Line Printer
1612 Line Printer
415 Card Punch
405 Card Reader
608 Magnetic Tape Unit
609 Magnetic Tape Unit
1713 Teletype Keyboard
1713 TTY Paper Tape Punch
1713 TTY Paper Tape Reader
Unassigned
1797 Buffered I/O Interface
Software Dummy Alternate
1584 Selectric I/O Typer
1582 Flexowriter I/O Typer
1716 Coupling Data Channel
1718 Satellite Coupler
Unassigned
8000 Series Magnetic Tape Unit
C
Unassigned
1530 A/D Converter 30/40 PPS
1534 A/D Converter 200 PPS .
1538 A/D Converter High Speed
Unassigned
Reserved for future standard equipment
Open for user assignment
8-46
C
B. 3. 5. 7. 2
The word B status can be used to determine several things about the device. The
E field can be used to see if any reques t is active on the device and w h e the r a
hardware error is present; this requires operator intervention. T can be used to
find out what kind of equipment the device is. For example, a program could see
if the standard output device is a teletypewriter or a line printer and then output
either 70-character lines or 136-character lines. The P and R fields can be used
to determine the availability to jobs.
B. 3. 5.7.3 Current Buffer Address
address
I
The add res s of the las t word that was stored in the buffer or written from the
buffer is in the I register. In this way a job can determine how much of its buffer
has been filled during operation.
B. 3. 5. B Example of Status Reques t
0015
0015
0015
0015
o
0015
0015
0022
0022
0022
0022
AA
FWRITE
$FC,XA, (AD DR) , (LENGTH), A, 0,1, I
XA
EXIT
SQP
OK-*-l
STATUS
$FC, AA+1, I
POOBF 54F4
P0090
P0091
P0092
P0093
P0094
P0095
OC01
00A1 P
0000
1BFC
B053 P
B052 P
OUT
P009C 54F4
P009D 0600
P009E BOFC
OK
~
EXIT
The above example takes status on the request from the completion routine if an
error indication is present.
More examples of status requests are in the CKASSM routine, section B. 3.10.
B. 3. 6 GTFILE Request - Request Code 13
This request is available only to background programs and only under MSOS.
A permanent file that has been placed in the program library* can be ace e sse d
during execution by the GTFILE request. A file is brought into core as it appears
on the mass storage device; GTFILE does not load a program. If apr 0 g ram is
()
-----------------
*A file is placed in the program library by a LIBEDT operation.
B-47
8.3.6
placed in the program library as a file, it must be in its a b sol ute binary form.
Data files cannot be c han g e d and written back on the library during execution. .
GTFILE only reads the file into core.
C,"
8. 3. 6.1 Format of GTFILE Request
RTJ-
15
0
11~
0
rc
1
1
($F4)
~
0
I! I
7
rn
4
I
0
3
CD
c
completion address
thread
v
1 ~ 1 :1
$C2
£
w1
s
starting core address
w2
f
filename address
rc
x
rp
cp
c
thread
v
m
a
request code, 6 bits: 13
relative indicator
request priority (for MSOS), 4 bits: 0
completion priority, 4 bits: 1
completion address
for system: 0
error bits, 3 bits
mode, 1 bit: 0 *
logical unit modifier, 2 bits: 2 *
Q logical unit address of MS device, 9 bits: $C2
w1 first word desired in file
s starting core address for buffer
w2 last word desired in file
f filename address
c
*
The macro call is:
GTFILE c, f, s, w1, w2, x, rp, cp
*Set by assembler if macro call used.
l
':..-
8-48
8.3.6.1
o
An example of a coded call would be:
FILNAM
ALF
1
RTJNUM
ADC
NUM
NUM
NUM
ADC
NUM
ADC
*, FILE *
FILE NAME
($F4)
$lA01
GOT
COMPL
o
$08C2
o
BUF
BINARY, LIBUNIT
WHOLE FILE WANTED
BUFFER
o
(FILNAM)
ADDR OF FILE NAME
(The file FILE is requested to be stored in BUF. GOT is the completion address. )
8.3.6.2 Request Code
Request code is 13.
8. 3. 6. 3 X Bi t
o
The x bit is used in conjunction with the f parameter.
relates to that parameter.
It will be discussed as it
8.3.6.4 Request Priority
The reques t priority is always 0 in the background for jobs. It will be used as the
request priority for the mass storage driver when it reads in the file.
8.3. 6. 5 Completion Priority
The completion priority is always 1 in the background.
8. 3. 6. 6 Completion Address
c is for the completion add res s and takes the same form as for the read/write
request.
8. 3. 6. 7 Mode
The mode field mus t be set to 0 (binary).
8. 3. 6. 8 A Field
The a bit, logical unit modifier, must be set to 2 (indirect).
8. 3. 6. 9 Logical Unit
The address of the library logical unit, $C2, must be set in this field.
8-49
8.3.6.10
8.3.6.10 Word Addresses: wI, w2
wI and w2 are the beginning and ending word addresses (mass storage) within the
file if word addressing is used and the disk word driver is present in the system.
If only a portion of a file is wanted, the wI, w2 specifies the words wanted. Th~y
are specified directly. If the complete file is wanted, wI and w2 s h 0 u I d be left
blank.
GTFILE -, -, -, 10,45, -, GTFILE
, , '"
,
In the first example words 10 to 45 would be brought in.
In the second, the com-
plete file would be brought in.
8. 3. 6. 11 Starting Core Address
s is the starting address of the block into which the file or a portion of the file is
to be transferred. x determines the type of addressing mode stakes.
x
s
Meaning of s
s
s is the starting address; x has no meaning.
e. g., GTFILE -, -, BUF, -, -, -, -, -
=0
=blank
(s)
s is indirect.
s is the core location which contains the starting
address of the block.
c
e. g., GTFILE -, -, (BUFADR), -, -, -, -, In this case BU FADR con t a ins the address of
the block.
~o
~blank
(s)
s is relative.
s is a positive increment added to the first word
of the parameter list to form the s tar tin g address of the block.
e. g., GTFILE -, -, (BUF-*+5), -, -, X, -, BUF is the buffer.
8. 3. 6. 12 File Name Address
The f parameter in d i cat e s the address of the firs t word of a three-word block
that contains the ASCII name of the file. It takes two forms, f and (f).
f is a positive increment to be added to the first word of the parameter list when
it stands alone.
8-50
c
8.3.6.12
()
For example:
GTFILE -, NAME-*+7 , -, -, -, -, -, In this case NAME would contain the first two characters of the ASCII name and
the relative distance to NAME would be assembled into the macro.
(f) indicates f is the add res s of the three word block containing the ASCII name.
For example:
GTFILE
-, (NAME), -, -, -, -, -,-
In this case the address of NAME is assembled into the macro.
The system searches the program library for the file with the s p e c if i e d name.
It is supposed to be necessary to specify two add i t ion a I words at the end of the
reques t in which the s y s t e m will return the actual sector add res s of the file.
This does not work, however, so we omit it.
8. 3. 6. 13 Example of a GTFILE Request
o
The following example uses a GTFILE request to obtain a file named SYSINI from
the program lib r a r y and store it into a buffer, beginning at $6000 (absolute address).
It happens that in this example the GTFILE request is to obtain a file that is an
a b sol ute program and is to transfer control to it; but the GTFILE could simply
have been used to input data to a buffer.
The example shows how the GTFILE works and how it is assembled.
c)
8-51
8.3.6.13
EXAMPLE USING GTFILE REQUEST FOR SYSTEM INITIALIZER
0001
0002
0003
0004
0005
0006
0007
0007
0007
0007
0007
0007
0008
0008
0008
0009
0009
0009
0010
0011
0011
0011
0011
0011
0011
0012
0012
0012
0013
0014
0015
0015
0015
0016
'5359
5349
4E49
5349
2049
4E20
6000
POO06 0000
POOOO
POO01
POO02
POO03
POO04
POO05
POO07
POO08
POO09
POOOA
POOOB
POOOC
POOOD
POOOE
POOOF
54F4
1A01
0014 P
0000
08C2
0000
6000
0000
8000 P
FILNAM
NAM
ENT
ALF
GETSI
SI
*, SYSINI*
BUF
ALF
*, SI
SIADDR
SI
GETFIL
EQU
SIADDR($6000)
File to go at $6000
0
0
GTFILE GOT, (FILNAM), SIADDR, , ,0, o~
I
~
IN*
Name of FILE in program library
MSG Buffer for TTY
4
\
Completion address
after SYSINI i~ brought
lnto core
\
Address
where
file name
is
~
Core
address
where
file is
to go
CP=l
RP
= 0
X bit = 0 (not blank)
Disk address
left blank;
program librarywill be
searched
EXIT (wait for completion)
C
P0010 54F4
P0011 OAOO
(unnecessary)
EXIT
POO12 54F4
POO13 OAOO
POO14 017B
POO15
POO16
POO17
POO18
P0019
P001A
P001B
54F4
OC01
001E P
0000
18FC
0003
0003 P
P001C
P001D
POOlE
POOIF
54F4
OAOO
0171
ICED
GOT
SIIN
SQM
IIrf t1
NOGOOD
E
FWIUTE
(std
)FC, WRr , B f
com!~~
COMPL
device)
ADDR
bit = 0 (not blank)
c~n~i:ect bit referring to $FC
MSG
RP
BUF
ASCII
3 words
=0
EXIT
Wait until Write is done
WROTE
NOGOOD
SQM
JMP*
EXIT
NOGOOD
(GETFIL+6) •
END
SI
Jump to beginning addres s of
SYSINI which is $6000
P0020 54F4
P0021 OAOO
8-52
C~'
8.3.6.13
o
This program may be rea sse m b 1 e d for any system. Change the EQU for the desired
high core address where the system initializer is to be pIa c e d. The system initializer
should be stored in the program library under the file name SYSINIo It can then be called
into core by typing on the TTY
*8I
8Y8INI was made a file so it could be stored in high core.
o
C)
8-53
8.3.7
8. 3.7 LOADER Request - Request Code 7
This request may be made only by background programs.
The loader request enables the pro g ram to load programs during execution. A
program is loaded beg inn in g at the first word of unassigned, unprotected core.
When loading, the loader res ide s in the upper part of unprotected core, wiping
out COMMON if it was being used.
The par am e t e r s for the loader request are in the A and Q registers. These
parameters pre s c rib e what type of load is to take place and from which logical
unit.
15
o
3
A
t
Qu
o
15
tna
Q
t
type of loading operation; discussion follows
Qu
logical unit number of the input unit if a relocatable binary program is being
loaded
tna
entry point, core address of the first of three sequential locations containing
the entry point name
t
Qu
Function
tna
0
Load relocatable binary programs
from any unit
input device
ignored
1
Load from program library
on library unit
library unit
ignored
2
Load program from library
unit and execute immediately
library unit
location of
program name
3
Produce memory map
ignored
ignored
4
Look up entry point name
ignored
location of
entry point
name
5
Same as t = 1 but no memory map
printed
6
Search directory of core-resident
entry points
ignored
ignored
7
Initialize data base
ignored
ignored
8-54
C
c
8.3.7
G
When the load is com pie ted without an error, the A register contains the last
transfer address given, as in normal loading. If an error terminated loading, A
contains zero and the Q register contains the storage address of the input block
processed by the loader at the time the error occurred.
8. 3.7. 1 Format of the LOADER Request
RTJ-
o
o
($F4)
1
1
9
8
1
o ------------------------------~-
~I
The macro call would be:
LOADER
An example of a coded request would be:
RTJ-
($F4)
NUM
$OEOO
See the core request for a program example using the loader request.
o
8. 3. 8 CORE Request -
R~quest
Code 11
The core request can be made only by background programs.
The core request can expand or contract available unprotected core. For example, if during execution the high locations of one's program are no longer needed,
one could release these locations by a core request so that another program could
be loaded into this area.
The core request has two forms, depending on the contents of the A and Q registers. If A and Q are zero, the core request asks for the cur r en t boundaries of
unassigned unprotected core. When the request has been processed, the Q register contains the lower boundary-l and the A register contains the upper
boundary+1. (The contents of A and Q are actually obtained from core locations
$ED and $EC.) With this information the program can set new b 0 un dar i e s to
available unprotected core.
When A and Q are non-zero and a core request is made, the new boundaries are
set according to the contents of A and Q. A contains the new upper boundary and
Q the lower. Both boundaries mus t be within un pro t e c ted core and A mus t be
larger than Q.
The core request is supposed to return the actual lower and upper bounds of unprotected core, but since it currently returns the lower-l and upper+l (from $ED
and $EC) we program it to allow for that.
C)
8-55
8.3.8.1
8. 3. 8. 1 Format of Core Request
r-'\
(
($F4)
RTJ-
o
rc
1
o
1
9
8
1
0
0
0
0
0
.
........... -
0
0
0
~I
The macro call would be:
CORE
The coded call would be:
($F4)
$1600
RTJNUM
8. 3. 8. 2 Example of Core Request
The following example program, LOADERC, makes a core request to obtain
bounds. It then drops the lower bound by 22 16 • Then it makes a loader request
to load a relocatable binary program tape from logical unit 2. The program on
the tape will begin to overlay the BSS block in LOADERC at address P0011.
LOADERC receives the entry point address inA from the loader (from the end tna
card of the loaded program) and stores it in the second word of the jump ins truction, where it can jump to the loaded program.
C'
0001
0002
0003
0004
0005
0005
0005
0006
0007
0007
0007
0008
0009
0010
0010
0010
0011
0012
0013
0014
0014
0014
0015
0016
0017
0002
POOOO 0846
XX
POO01 54F4
POO02 1600
POO03 ODDD
POO04
POO05
POO06
POO07
POO08
54F4
1600
COOO
0002
OFC4
POO09
POOOA
POOOB
POOOC
POOOD
POOOE
54F4
OEOO
6802
1400
0000 P
OBOO
NAM
EXT
EQU
CLR
CORE
LOADERC
ENTRY
TAPEU(2)
A,Q
Get core limits
INQ
CORE
LDA
-$22
Set lower limit
=XTAPEU
4
ALS
LOADER
XA
STA*
JMP+
Unpatched external
Set up LUN
Call loader
Save entry point address
Jump to it
XA+1
**
Nap
EXIT
POOOF 54F4
P0010 OAOO
ENT
P0011 0022
END
XX
BSS
XX
8-56
PT($22)
C'
"
8.3.8.2
C)
The system r e c 0 v e r y package was used to dump some of the program area beginning at POOOD in LOADERC. It shows that the new buffer of the loaded program
exactly overlayed the BSS in LOADERC; then the write request, beginning at
P0009 in the new program, wrote out the confirming message.
Use of the system to execute this job is covered in Chapter 9, but the example is
included here so that it can be studied for later reference (since it a p pi i e s to
the core and loader requests).
o
()
8-57
·
·
·
00
C/.:)
00
t\j
RE DUMP
Buffer PT began here at 2F3F but is now overlayed
by message buffer. CORE wiped out PT buffer and
set new lower limit at 2F3F.
New program F was
loaded at 2F3F.
F
2F3B
RE DUMP 2F4B
[ 2F5B
j
i
2F3F
2F48
0000
1804
OBOO
1004
54F4
AF47
OAOO
2F3F
"
(
414E
54F4
ANOTHER EXAMPLE
4F54
OAOO
4845
0179
A
5220
54F4
4558
OD01
414D
0009
Write request at
entry point of F
504C
0000
4520
1004
"
0008
FFF3
..
54F4
7FEB
OC01
54F4
2F51
OAOO
Buffer address in F
TTY PRINTOUT
00
I
*p
c..n
J
00
*L,8
J
*SR
J
*x
E
*
~
L, 02 FAILED 02
ACTION
CU
ANOTHER EXAMPLE
ANOTHER EXAMPLE
J
J
Unpatched external ENTRY which was not needed so
ignored.
Load F from paper tape reader. There is no *T on
the end of the tape, hence the message and CU.
Output from Program F
RE
*2F3B
ERR
RE
*D2F3B,2F5B
RE Dump Request
RE
rJ
(l
f~
~
l,
8.3.9
o
8.3.9 INDm Request - No Request Code
This request can be used by foreground or background programs under MSOS only.
It is not a separate request but is an indirect version of any other request.
Any request can be used again without repeating the r e que s t by using the INDIR
request.
8.3.9.1 Format of the INDIR Request
RTJ-
($F4)
ap
Only in the INDIR request should bit 15 of the first word of the parameter list be
set to 1. This tells the s y s t em that the w 0 r d under the RT J- ($F4) is not a
parameter but is the address of the parameter list to be requested.
The macro form is:
INDIR
(p)
p is the address of the parameter list; it must be in parentheses.
o
To code the call:
RTJADC
($F4)
(REQ+1)
(if the desired request parameters begin at REQ+1)
8. 3. 9. 2 Example of the INDIR Request
An example of the INDIR reques t would be one in which the r e que s t parameters
could be stored in a buffer and an indirect request could cause them to be executed.
The following example stores the buffer address for MESSAGE in the s field of a
reques t at REQBUF (the number of words in n) and then executes the r e que stat
REQBUF.
Note that by using the INDIR request, control returns beneath it after the request
is initiated. If a jump had been made to REQBUF-1 (if a RTJ- ($F4) were there),
can t r a I would return under the parameter string at REQBUF. This may not be
the desired action.
o
8-59
8.3.9.2
BUF
~
ALF
~
LDA
STA*
ENA
STA*
INDIR
REQBUF
N
S
*,MESSAGE *
=XBUF
S
4
N
(REQBUF)
~
NUM
ADC
NUM
$OCOl
COMPL
NUM
$1004
NUM
NUM
o
o
FWRITE
o
ASCII, TTY
~
More e x amp 1 e s of the INDIR reques t appear in the routine CKASSM in the next
section, 8.4.
8.4 PROBLEM
The following program is a routine which can be used to check out the macro assembler.
Study it car e fu 11 y to see what it does.
After studying the program as it is written, figure out what would happen if the two SQP
instructions at P0007 and POOOD were SQN instead.
Comprehension of the CKASSM routine should be considered a "final examination" on requests. Any points which are not thoroughly clear to the reader should be restudied
carefully in the appropriate sections. A very good knowledge of these r e que s t s is required before the student goes on to study Part II of the training manual.
8-60
()
0
C)
0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013
0014
0014
0014
0015
0015
0015
0016
0016
0016
0017
0018
0019
0019
0019
0020
0020
0020
0021
0022
0023
0023
0023
0023
84758702
NAM CKASSM
DEcK 10
JUNI: 4. 19t>M
M4'~M'O~
VERIFICATION TEST FOR A007 MACRO ASSEMBLER
*
'dO
spEC ID REFER TO 84800300
PROGRAMMING SYSTEMS. AID SYSTEMS DIVISION. CDC
*
'I}
AssEMBLE USING 1700 MACRO ASSEMBLER
THIS PROGRAM IS A VERIFICATION FOR THE
*
MACRO ASSEMBLER
*
THIS IS ONE OF A SERIES OF TESTS THAT USES
*
INDIRE.Ct SyStEM REQUEStS ON VARIOUS
**
COMBINATIONS OF (F)READ/(F)WRITE REQUESTS.
ENT CKASSM
CKASSM NOP
INDIR (F1+U
'dO
POOOO OBOO
POOOI 54F4
POO02 SOCS P
INDIR (W1+1)
POOO3 S4F4
POO04 80BC P
INI
POO05
POOO6
POO07
POOO8
54F4
80B8 P
0161
18FC
POO09 s4F4
POOOA 80AF P
POOOB
POOOC
POOOD
poooE
54F4
80AB p
0161
18FC
pOOOF
P0010
pooll
POO12
0023 poo13
0023 POO14
pOOlS
0024
0024 pool6
0024 POO17
0025 poOla
POOl9
poOIA
P001B
poolC
POOID
poolE
POOIF
P0020
P0021
P0022
P0023
P0024
P0025
P0026
P0027
P0028
P0029
po02A
P002B
54F4
OCOO
0000
0000
OaFC
0019
004A P
INDIR (T1 +1)
SQP 1
JMP* INt
INOIR (R1+1)
IN2
INDIR ( '2+ 11
SQP 1
JMP'l} IN2
FWRITE $FC •• BUF,25,B, •• I
EXIT
54F4
OAOO
4E45
5854
2040
4553
5341
4745
2053
484F
554C
4420
494E
4449
4341
5445
2056
4552
4946
4943
4154
494F
MSG
ALF
25.NEXT MESSAGE SHOULD INDICATE VERIF ICAl ION
P002C
P002D
P002E
P002F
P0030
8-61
4E2-0
2020
2020
2020
2020
8.4
0026 P0031
P0032
P0033
POO34
P0035
POO36
P0037
po03A
POO39
poo3A
P0038
P003C
P003D
P003E
P003F
POO4O
4041
4352
4F20
4153
5345
4042
4C45
5220
4F4E
2031
3730
3020
4F48
2020
2020
2020
2020
2020
2020
2020
2020
2020
2020
2020
2020
P0041
POO42
P0043
P0044
P0045
P0046
P0047
POO48
P0049
0027 P004A 0060
0028
0028 POUAA 54F4
0028 POOAB 0600
0028 POoAC 0005
0028 POOAO OOAF
0029
0029 POOAE 54F4
0029 POOAF 0800
0029 POOBO 0000
POOS1 0000
0029 POOB2 08C2
0029 POOS3 0019
POOB4 004A
0030 POOBS 0000
POOB6 0001
0031
0031 POOB7 54F4
0031 POOA8 0600
0031 POOB9 0005
0031 POOBA OORC
0032
0032 POOBS 54F4
0032 POOBC OCOO
0032 POOAO 0000
POOBE 0000
0032 pOOBF 08C2
0032 POOCO 0019
POoCI 0031
0033 POOC2 0000
POOC3 0001
ON 1700 OK
25.MACRO ASSEMBLER
------------------- -
MSGI
ALF
T2
AZS BOF(96)
STATUS 5,R1+1
(~:~~
C
P
Rl
FREAD $C2.,BUF.25.B •• ,I
P
NOM
0.1
,1
STAIOS
WI
FWRITE $C2"MSG1.2S,B."I
S.Wl+1
P
P
NUM
0.1
C
8-62
8.4
o
0034
-Ulf~POOC4
0014 POOCS
0034 POOC6
POOC7
0034 POOC8
0014 POOC9
POOCA
0035
Fl
54F4
OCOO
0000
0000
18FC
0019
0018 P
END
CKASSM
J
*p
J
C)
*ASSEM
OPTIONS LX
J
*p
J
*L,5
J
*X,N
NEXT MESSAGE SHOULD INDICATE VERIFICATION
MACRO ASSEMBLER ON 1700 OK
J
o
8-63
r
"-
'
o
--CHAPTE-R IX
MSOS USE
o
o
c
c
c)
CHAPTER IX - MSOS Use
TOPIC
o
C)
PAGE
9.1
Job Processor
9-1
9.1.1
Assembling a Program
9-2
9.1.2
Loading and Executing a Program
9-6
9.1.3
Other Job Processor Control Statements
9-7
9.2
Debugging
9-13
9.2.1
Assembler Errors
9-13
9.2.2
Device Failure
9-15
9.2.3
Loading Errors
9-17
9.2.4
Logic Errors
9-17
9.2.4. 1
Breakpoint Package
9-18
9.2.4.2
System Recovery Package
9-24
c
o
9.1
9. 1 JOB PROCESSOR
The job processor is that part of the operating system which monitors the background.
It is a system program, and it allows jobs to run in the background when the system does
not need the CPU or the background core area. Under the control of the job processor
are the program library and such jobs as assembling, loading, compiling and executing.
The job processor resides in the system lib r a r y on the mass storage device until it is
called into execution by a manual interrupt and an * followed by any control statement and
a carriage return (CR).
For example: The operator depresses the MI key and types *P.
MI
®
J
The system will t y p e the MI and J. (In this chapter all messages typed by the operator
will be circled.) MI indicates that the manual interrupt has been accepted.
The J will be printed when the job processor has come into core and is ready for a control
statement. The job processor types its messages on the standard comments device which,
in most cases, is the teletypewriter.
o
Each control s tat em e n t to the job processor must begin with an asterisk and must be
terminated with a carriage return. The job processor will type a J when it has finished
doing what it was instructed to do and is ready to a c c e p t another control statement. It
will also light the BREAK light on the teletype, and the operator must depress the BREAK
RE LEASE key to turn off the light (and start the motor), then type his statement. If this
light was not lighted, the system is not waiting for his input.
If the operator realizes that he has t y p e d the statement incorrectly before he types the
car ria g e return, he can" erase" it by typing a rub out, line feed, carriage return and
then proceed.
JOX, hhhh indicates an error in a control statement to the job processor or a processing
error in the background program. A sum mar y of the error messages appears in Appendix D.
The following control statements are available for the operator to use to instruct the job
processor in running a job. A brief description of their mea n ing is here and they are
described in detail in the MSOS reference manual.
C)
9-1
9.1
Figure 17. Control Statements Available Under the Job Processor
Control Statement
Meaning
*p
Brings in the loa d e r, initializes for an independent loading operation.
* K, Iu, Pu, Lu
Alters standard logical units. Where I is input,
P is punch and L is the list device.
*L,u
Loads a program from logical unit u.
*X,m
Executes the program that was loaded. If m is
blank, the memory map will be printed.
*
Note error and overlay
J
@)
J
®
J
o
1 ENTRY POINT TABLE***COM 7FCD
***DAT 24EO
START
2559
QQ
BP
2587
9-19
9.2.4.1
At this point the programmer can enter anyone of the available breakpoint statements.
The programmer may want to break his programs into portions and execute them
s epa rat ely. An Saaaa, aaaa, •••• CR sets a stop or breakpoint at the addresses
,aaaa, so that during execution when the program reaches this point the program
will halt and control will return to the keyboard. The breakpoint program will at
that time print the message BP, aaaa indicating that the breakpoint at the address
aaaa has been reached and the breakpoint program expects another control statement.
For example, in the program EXAMPL listed as illustration 1 under Section 9. 1. 1
perhaps the programmer would like to execute his program thru the EXIT on card
5, pro g ram location 12. He would probably take the TTY listing which has the
address of the first location of his program (24EO). He would then add the program relocatable address of the instruction where he wants the breakpoint to the
first location. He would set the breakpoint one instruction after the last instruction that he wants executed. For example:
Comments Device
Notes
J
®
J
0L,8)
EXAMPL
J
24EO
®
J
24E 0 machine addres s of program
+ 12 instruction in program
24F2 actual address
@
J
o
1
ENTRY POINT TABLEGO
24E9
BP
0 S24 F2)
BP
0D24EO, 24F2)
24EO 4558 414D 504C 4520 5052 494E 5420 4F55 5420 54F4
24EA OCOI 24F2 0000 18FC 0009 24EO 54F4 OAOO 54F3
BP
0J24E9)
EXAMPLE PRINT OUT
BP, 24F2
9-20
9.2.4.1
u
The *S24F2 sets a breakpoint at 24F2. The D24EO, 24F2 dump s that core area.
The J24E9 jump s to location 24E9 (P0009) and executes the write. The program
stops at 24F2 before executing the SE T A, Q instruction.
One can set a maximum of 15 breakpoints with one *Saaaa(CR). However, many
more than that can actually be set at anyone time. A breakpoint at a location is
actually a RTJ to the breakpoint package inserted in place of the actual code. The
actual code is kept by the breakpoint pac k age to be executed and to be returned
when the breakpoint is removed. Therefore, s eve r a 1 considerations should be
made when setting a breakpoint. A breakpoint should not be set at a non-executable
instruction such as a data word because the program would never get to that word
to ex e cut e the R TJ, and therefore would not stop at that breakpoint. Also, the
breakpoint should not be set at the second word of a two-word instruction because
when that instruction is put into execution the R T J would then be interpreted as an
address rather than executed as a jump to the breakpoint package. The breakpoint
should not be placed at a location that will be modified or changed during execution.
For example, a breakpoint should not be set at an instruction whose address is to
be modified or the first word of a subroutine whose en tr y is via a RTJ for then
again the R T J to the breakpoint package would be modified or destroyed and the
result would be unpredictable.
o
A breakpoint should never be set on anR TJ instruction because the actual instruction is executed in the breakpoint program itself. H enc e, the actual program's
RTJ would take the wrong address with it.
If a breakpoint is to be cleared, the * Taaaa, aaaa(CR) statement is used. If all the
breakpoints that have been set are to be cleared, the *T(CR) statement is used but
none of the addresses are speCified.
The contents of the registers are printed out with the *P(CR) statement.
BP
® REG.
A=18FD
Q=18CD
1=0814
M=9000
P=54FF
BP
One can enter each of the registers except M by indicating the register and typing
the hexadecimal number that is to be entered.
BP
~AFOFO)
BP
01FFFF)
BP
~Q1234)
BP
® REG.
o
A=FOFO
Q=1234
BP
9-21
1=FFFF
M=9000
P=54FF
9.2.4.1
The contents of core can be dumped by the *Daaaa, aaaa statement. The first aaaa
s p e c if i e s the first location the programmer wants to print and the second aaaa
specifies the last.
C~'
BP
*S24F2
BP
~D24EO, 24F2)
24EO
24EA
4558 414D 504C 4520 5052
OCOI 24F2 0000 18FC 0009
494E
24EO
5420 4F55
54F4 OAOO
5420 54F4
54F3
BP
The output from the *P(CR) statement is on the standard list device. In this example the list devic~ has been made the same as the comments device with an *K
statement. This example is a dump of the program listed as Illustration 1. Note
that the last location printed out (54F3) has been set as a breakpoint.
If only one location is wanted, specify the single address.
BP
~D24EO)
24EO
BP
4558
If one wants to enter a 1 0 cat ion in core an *Eaaaa, hhhh, hhhh, •••• (CR) is used.
The aaaa specifies the first address to be entered and the following hexadecimal
numbers to be placed in each sequential location.
BP
~E2557 , FFFF ,0000, FFFF)
BP
~D2557 , 2550
2557
BP
FFFF
0000
FFFF
~EAAXx)
BOl, *EAAXX
BP
*E2557, AAAA, BBBB, CCCC
BP
~D2557 , 255~
2557
AAAA
BBBB
BP
9-22
Note the error message
CCCC
c
9.2.4.1
o
If a location is to be skipped, i. e., not en t ere d with data, skip that location by
typ ing two commas in a row. This indicates that the location is to be left unaffected. If a location is to be filled with zeros, the zeros must be specified.
When a programmer would like to begin execution of a sequence of programming
out of the normal sequence, he may use'the jump s tat e men t, *Jaaaa(CR) to the
instruction to be executed. Execution begins immediately after the *Jaaaa statement. The aaaa is the address of the first instruction to be executed.
J
~K, L4)
J
®
J
~L,~
EXAMPL
24EO
J
®
J
@
J
o
o
1 ENTRY POINT TABLEGO
24E9
BP
~S24FD
BP
~D24EO, 24F2)
24EO
24EA
BP
4558 414D
OC01 24F2
504C 4520 5052
0000 18FC 0009
494E
24EO
5420 4F55
54F4 OAOO
5420 54F4
54F3
~J24E9)
EXAMPLE PRINT OUT
BP,24F2
The *J24E9 caused the jump to P0009 to execute the write.
The return jump *Raaaa is used when an iterative loop is b e in g checked out and
the programmer would like a stop at each execution of the loop.
The con ten ts of words on the mass s tor age device may be dumped using the
*Ms1, w1, s2, w2, nCR where:
()
sl
w1
s2
w2
n
is
is
is
is
is
the
the
the
the
the
beginning sector number
beginning word to be dumped of that sector
last sector to be dumped
last word of that sector to be dumped
logical unit of the disk
',--./
9-23
9.2.4.1
There are several combinations that one can use. If, while working in the background, the scratch unit is wanted, the n may be omitted and the scratch unit is
assumed. If complete sectors are wanted, the word specification can be omitted
and the complete sector will print, If one wanted to examine a file that has been
stored on sector 24 of the disk, he could do the following:
*M24(CR)
The programmer may begin in the mid dIe of a sector and dump the rest of the
sector by specifying the first sector and first word but omitting the second sector
and word.
If the first complete sector of scratch is wanted, type
*M(CR)
Examples of the *M statement are under the system recovery section as the system
recovery's *M works exactly the same as the breakpoint's.
If at any time the program is to be terminated, a MI and an * Z (CR) will do so. An
example of *z being used to terminate a job is in the first program in the system
recovery section.
If an error is made while using the breakpoint package, the breakpoint pac k age
will p r in t a message beginning with a B. The possible error statements are as
follows:
B01, statement
Statement or parameters are unintelligible for the breakpoint program.
B02,hhhh
hhhh16 cannot be processed by b rea kpoint program because it is protected.
B03,hhhh
Breakpoint lim it exceeded •. hhhh16 is
the last breakpoint processed.
B04
Previous *E statement requested entries
in protected core. Entries are not proc e sse d; breakpoint program waits for
new statement.
9. 2.4. 2 System Recovery Package
The system recovery package is called in with an *SR(CR) before the program is
executed just as the breakpoint was. However, the system recovery package does
not function and does not accept con t r 0 I statements until after the program has
finished normally or aborts. A RE message indicates that Recovery is in and is
ready to receive a statement.
9-24
c
9.2.4.2
Figure 19. Control Statements Available to the System Recovery Package
Control Statements
Brief Description
*Daaaa1' aaaa2(CR)
Dump locations of core beginning with hexadecimal address aaaal and ending with hexadecimal
addres s aaaa 2 •
*Ms1, wI, s2, w2, n(CR)
Dump mass storage unitnfrom sector and word
sl, wI to sector and word s2, w2.
*T(CR)
Terminate the system recovery package and return to the job processor.
*n(CR)
Change the list device for dumping contents of
core or mass storage.
The statements for dumping core and mass storage are the same as for the breakpoint. The output is on the standard list device.
An *T(CR) terminates the system recovery package.
J
®
J
EL,8)
EXAMPL
o
J
o@
24EO
:======-
Note that breakpoint and recovery flags may be
set
J
@
1 ENTRY POINT TABLEGO
24E9
BP
~J24E9)
EXAMPLE PRINT OUT
BP, 24F2
EE24ED, 18F~
The operator presses the manual interrupt
MI
...
'4_------- but ton on the typewriter here if he desires to
terminate job execution and enter the Recovery
RE
package
ED
~D24EO,24F0
24EO
24EA
RE
4558 414D
OC01 24F2
5048
0000
4520 5052
18FB 0009
494E
24EO
5420 4F55
54F4 OAOO
5420 54F4
54F3
The *D above dumps core from 24EO through 24F2, after the program has executed.
o
9-25
9.2.4.2
(~
BP
1'--..,-
<§E9)
EXAMPLE PRINT OUT
RE
®
RE
QM,15,,12)
ERR
Note: ERROR Occurred because word 1 is larger than word 2.
RE
0 M,15)
SECTOR NUMBER
5800
0015
0400
001F
OFOA
0029
0033
OBOO
0000
OD03
1401
012,1
0000
0302
0000
18DF
0000
1803
0844
18F5
0000
OBOO
E80D
C8EO
0000
18FO
OBOO
1CF2
0000
5806
02FE
0000
0000
OD04
A30B
0181
0000
03FB
B80B
0039
0000
5803
0104
0019
0000
0163
0009
FFFE
414C
2E20
0008
0000
18FE
0000
0161
18F3
6810
OAOO
OOOA
FFFA
4045
0000
0000
08FC
OOOA
18FD
1CF8
0131
18E8
0001
OOOB
FFFC
5354
24E3
18FC
0001
0031
68F7
90A4
18F8
0131
0002
OOOC
FFFB
'204E
68D5
001E
255E
0000
18DC
OIA7
CC99
18E6
0003
OOOD
FFFA
4F2E
0842
7FEA
54F4
OBOO
OBOO
0138
9897
18F8
0004
OOOE
FFF9
2049
481D
54F4
OAOO
0000
CCAB
CCA1
01A6
5448
0005
OOOF
FFFF
5320
OC17
OAOO
54F4
2560
68A8
689E
012A
4520
0006
0010
5443
4154
5825
54F4
OD01
68B3
68A8
C800
CC95
534D
0007
0000
4520
204C
54F4
OD01
0008
OC09
D8A8
FF9E
6893
414C
0001
404F
OODO
0000
0000
4144
0000
0000
0000
FFFF
0000
0000
0000
6804
0000
5000
0000
4804
0000
0000
0000
1800
0000
0000
0000
0003
0000
0000
0000
FFFF
0000
0000
0000
FFFF
0000
0000
0000
0002
0000
0000
0000
0000
0000
0000
0000
0000
0000
1400
2020
0000
2020
0000
FFFF FFFF FFFF FFFF
Note:
** implies that the 0000 or FFFF continues for the rest of the sector.
**
RE
0D2137)
2137
C80D
RE
~D24EO, 255~
24EO
24EA
24F4
24FE
2508
2512
251C
2526
2530
253A
2544
254E
2558
0001
0008
0000
534D
4F43
OD01
0008
0000
5805
ODFE
681A
C893
4045
RE
~M,124,25,124)
SECTOR NUMBER
0814
0124
SECTOR NUMBER
0001
5803
5800
OOOB
0015
0000
001F
2020
**
SECTOR NUMBER
0001
0000
2020
OOOB
C
0000
**
RE
®
J
(-"
.......
9-26
_.
9.2.4.2
In the previous example the *4 reassigns output to lun4, the TTY. The *M, 15 implies sector
of s c rat c h from W 0 r d 15 on. *D2137 dumps 1 0 cat ion 2137.
*D24EO, 2558 dumps those locations, inclusive. *M, 124,25,124 dump s several
consecutive sectors.
°
o
o
9-27
PART II
I\'......
(
,-.
'"
"
CHAPTER X
CONFIGURING A SYSTEM
CHAPTER X - Configuring a System
r
.-.
Vi
I~
L.J
TOPIC
PAGE
10.1
Central Processor
10-1
10.1.1
Low Speed I/O Package
10-1
10.2
1705 Interrupt Data Channel
10-2
10.3
Buffered Controllers
10-2
10.4
1706 Buffered Data Channel
10-3
10.5
Unbuffered Controllers
10-3
10.6
160-A Peripherals
10-5
10.7
1500 Equipment
10-5
10.8
Priorities for DSA Bus
10-5
10.9
Summary, Configuring Equipment
10-6
10.10
Related Manuals
10-6
c
10.1
u
CONFIGURING A SYSTEM
The content of this chapter will be devoted to the 1700 and its peripherals as a total system.
It is designed to assist the presales analyst in configuring a system by considering the interrelationship of the various pieces of hardware. Each has its own characteristics which must
relate to and interface with the total hardware configuration.
Figure 20 is a diagram of m 0 s t of the s tan dar d hardware and it should be consulted as a
reference from the text in this chapter. Figure 21 also contains the hardware and it includes
the new hardware.
10.1 CENTRAL PROCESSOR
The basic 1704 computer consists of the centralprocessor, arithmetic unit, 4K memory
and A/Q channel access to the low-speed I/O package via the slow-channel synchronizer,
equipment number 1.
Memory modules maybe added in 4K (1708) increments to a maximum of 32K. The 1709
(8K mod u I e) is available only on a used basis. A new hardware addition has recently
been made to the product line to allow an increase of memory size to 65K.
Two interrupt lines are included: line 0 for internal interrupts and line 1 for the slowchannel synchronizer.
10.1.1 Low Speed I/O Package
o
The low-speed package consists of:
•
teletypewriter
1711 - keyboard entry and printer only, 100 characters per second
1712*- keyboard & printer, 100 cps, with offline mechanical paper tape
reader and punch
1713 - keyboard, printer, on-line mechanical paper tape reader and punch,
100 cps
•
paper tape reader
1721 - 400 cps reader, electronic
1722 - same reader, with added take-up and supply reels
• paper tape punch
1723 - 120 cps punch
1724 - same punch, with added take-up and supply reels
•
card reader
1729*- 100 card-per-minute reader, replaced by 1729-2 which connects to 1705
*Only available used on an as-available basis.
10-1
10.1.1
These are the stan dar d peripherals connected to line 1; other peripherals must
normally be connected through a 1705. Some exis ting con fig u rat ion s do have
s p e cia 1 peripherals other than those above on line 1, but this is on a QSE basis
and each case must be considered individually.
C.'..
10.2 1705 INTERRUPT DATA CHANNEL
Any system which will require more than the two basic interrupts or the peripherals in
the low-speed r/o package will need a 1705. The addition of the 1705 will add the following capabilities to the system:
a) addition of 14 more interrupt lines for external equipment
b) addition of up to eight controllers to the A/Q channel
c) addition of direct memory access for up to eight buffered controllers
See note A, Figure 20, for additional explanation of line connections.
Input/ Output for the additional eight controllers would be unbuffered if they are connected
to the A/Q channel only. I/O will be buffered if they are connected to the A/Q channel
and the DSA bus and are either capable of doing direct memory acces s on their own or
are connected through a 1706 or 1716.
10.3 BUFFERED CONTROLLERS
Three controllers are capable of performing data transfers directly between computer
memory and the attached peripheral device:
1738 disk controller - controls one or two 853 (1. 5-million-word) or 854 (3. O-millionword) disks,
1751 drum controller - controls drum; size from 65K to 524K words,
1748 master communications terminal controller - controls up to 64 rem 0 t e communications sets (through 8136's) or up to four 302 communications expansion modules.
The buffered controllers are connected to the A/Q channel (for transfer of control information) and the DSA bus (for transfer of data). Any program which is running and using
the CPU continues to run while the controller is handling the data transfer, s inc e the
A and Q registers are not used during the data transfer.
Direct memory transfer is done on a cycle- stealing bas is; that is, the controller steals
a me m 0 r y cycle every time it wishes to transfer a word (through the Z register). In
order to calculate how much each buffered controller will slow down the CPU (and, therefore, a running program), a percentage could be figured based on the transfer rate of
the peripheral. For example, the 1738 is capable of transferring one word every 12.8 ).Is
so it will steal approximately every 12th cycle and can therefore slow down a program
by up to 9% when the disk is run n in g. The program would only be slowed down if the
CPU and the 1738 both wanted to access memory at the same time.
10-2
c
10.4
o
10.4 1706 BUFFERED DATA CHANNEL
The 1706 allows direct memory access for unbuffered controllers. It is for any of the
controllers thatare not capable of doing buffered data transfers. (That is, any except the
1738, 1751 and 1748.) The 1706 is connected between the 1705 (DSA and A/Q channels)
and the peripheral controller.
Only three 1706's are allowed in any system; this is a software limitation rather than a
hardware limitation. The 1716 is exactly like a 1706 except it is accessible by two
c ompu te r s. See note C of Figure 20. The 1706 may control up to eight controllers.
However, when deciding which peripherals should go on the 1706, it is very important to
note that it is logically busy the entire time it is handling a buffer t ran s fer for a peripheral. During that time it cannot be accessed to do any operation or take status on;
any other peripheral connected to it. Therefore, the timing on the peripherals must be I
considered so that data will not be lost on one while the 1706 is working on another.
o
As a rule, a 1706 would not be purchased to handle relatively slow peripherals (i. e. , the
1742 line printer or 430 card reader/punch). These peripherals can very effectively be
operated in interrupt mode as they will interrupt the CPU infrequently to perform their
I/O. The 1706 would more effectively be used and needed to handle fast peripherals
(such as magnetic tapes or the 405 card reader). For example, a 1732/608 magnetic
tape can transfer one f ram e of data every 32 )lS. Since MSOS can lock out interrupts
for up to 50 }.lS at one time, data could be lost on the tapes if they were not conriected to
a 1706.
Software for controllers operated in the buffered mode through the 1706 should be considered on an individual basis in the light of new software releases.
10.5 UNBUFFERED CONTROLLERS
The standard controllers which could be operated in the unbuffered mode t h r 0 ugh the
1705 to the A/Q channel are as follows. Most are shown in Figure 20. The newer ones
are in Figure 21.
•
1726/405 Card Reader - 1200 cpm reader. 405 can also be connected through 1750
via a 177 controller. Shown on Figure 21.
o
1728/430 Card Reader/Punch - 500 cards per minute read; 100 cards per minute
punch, (column punch). Reader canbe purchased separately as a 1729-2, 330-cpm.
Punch can be purchased separately as a 420A, 100 cpm.
• 1729-2 Card Reader - this is the replacement for the 1729 and it reads 330 cpm.
Not shown on Figures.
• 1731/601 Magnetic Tapes - this is the 1x8 controller for 601 magnetic tapes (200,
556 bpi). They do not have assembly/disassembly mode. They have been updated
by the newer 1732/608-609 tapes, and are now available only on a used basis./
o
10-3
10.5
• 1732/608-609 Magnetic Tapes - the new controller, featuring assembly/disassembly
option, which replaces the 1731. One controller can handle up to eight tape units;
608's or 609's or a combination of both.
C~'
608's - 7 track; bcd or binary; 200, 556, 800 bpi; read forward and reverse
609's - 9 track; binary only; 800 bpi only; read forward and reverse
Software from the 1731/601 is completely upward compatible with 1732 hardware.
The 1732 is a more expensive controller than the 1731, but the added f eat u res
would be desirable for the more sophisticated user:
assembly/disassembly mode*
800 bpi
forward and reverse read
9-track tape
• 1735/915 Page Reader - optical character recognition equipment, 370 characters
per second. Software operates as a compiler under utility System; no standard
driver is as yet available under MSOS, but it is planned to be added.
• 1736-1 OCR Document Reader Controller - controls one 935-1 or 935-2 document
reader. Software not yet available; will probably run under utility first.
• 1740/501-505 Line Printers - 501, 1000-lpm printer or 505, 500-lpm; 136 characters. Software not yet available for 505.
• 1742 Line Printer (with controller included) - this is the Holley 300-lpm with control, 136 columns.
• 1744 Digigraphics Controller - controls one 274 dig i g rap h i c light-pen console.
Shown on Figure 21. Software is QSS.
• 17 45-1 Inquiry/Retrieval Controller - controls 211 Display/Entry and 218 Output
stations.
• 1746-1 Single Station Entry/Display - controls CRT display and keyboard.
• 1747 Data Set Controller - controls 301-B data sets. Software runs under Utility
System. Standard software is available for 6000 import/export.
• 1749 Communications Terminal Controller - con t r 0 1 s remote communications
equipment, up to 16 lines per controller. Standard software is available only in
the unbuffe red mode on the 1749; software is not available to connect the 1749
through the 1706 in a buffered mode. The 1748 is used for buffered operations."
Standard software is available now or will be shortly on most of the peripherals above
(except as noted) to run under MSOS in the unbuffered mode.
*Also, new software for the 1732 utilizing assembly mode will mean the tapes only have
to be accessed half as often.
10-4
C
o
10.6
10.6 160-A PERIPHERALS
Several 160-A peripherals are connected to the 1700 on existing configurations through
a 160-A adapter, and the 1750:
a)
b)
c)
d)
405 card reader (through 177 controller)
166 line printer and control
415 card punch (through 170 controller)
165-2 Calcomp plotter and control
These equipments are not listed as standard available products as they are only available
used on an as-available basis.
10.7 1500 EQUIPMENT
The 1500 series of analog equipment for pro c e s s control is all connected to the 1700
through different interfaces. A large, detailed chart of 1500 equipment is a v a i I a b I e
through ADSD in La Jolla. Much of the series is shown in the Figure 20 chart and its
primary interfaces are:
a) 1750 DCB Termiriator - this is the prime in t e rfa c e and it allows A/Q channel
access to the 1500 series via the 1705. It is required if any 1500 equipment is to
be connected to the computer.
o
b) 1797 Buffered I/O Interface - this provides access to the DSA bus for buffered 1500
equipment. It is functionally equivalent to the 1706 for standard peripherals. It
is connected to the DSA and the 1750 and it controls up to three 1571' s.
c) 1571 Chaining Buffer Channel - this is the priority buffer channel which assigns
priorities to the equipment on the 1797. It is required if a 1797 is pre sen t. A
high priority pie c e of equipment can steal the channel away from a low priority
equipment.
See notes E-J of Figure 20.
One piece of 1500 equipment will be mentioned here as it is nearly 'always needed in all
configurations: 1573 Line Synchronized Timing Option.
This is the clock con n e c ted to the 1750 which generates timed interrupts to the CPU
(60/sec). Any process system which requires a clock for timed programs will need a
1573 since there is no realtime clock in the computer itself. Many standard s y s t ems
need a clock, especially to m on i t or I/O which can get hung up (for example, the 1706
can hang up in a buffer operation if the peripheral malfunctions or drops Ready). Several controllers are capable of generating the necessary timed interrupt, but if one of
these is not present in the system, the 1573 can be used.
10.8 PRIORITIES FOR DSA BUS
o
Since all memory accesses, even buffered, must go through the Z register, priorities
must be assigned to all the interfaces which may use the DSA bus. The 1797 takes
10-5
10.8
highest priority in direct memory access, the 1706 takes second priority, the standard
buffered equipments (1738, 1751, 1748) take third priority. The running program takes
lowest priority for accessing memory. On Figure 20, see Q), ®, and ®.
(--
10.9 SUMMARY, CONFIGURING EQUIPMENT
The chart in Figure 20 can be utilized very effectively to configure a system. Note that
low- speed 110 package is connected to the CPU through the Low- Speed 110 Synchronizer.
Each of the standard buffered equipments (1738, 1751 and 1748) has line connections
leading to the CPU via the A/Q channel line and the DSA line. The unbuffered equipments
connect to either the A/Q line or, through a 1706, to the DSA line and A/Q line (to add
buffer capability).
The 1750 connects to the 1705 (for A/Q access). The 1797 has lines to the 1750 and DSA,
and the 1571 leads directly to the 1797. Note that all 1500 peripherals connect either to
the 1571, 1797 or 1750. The 160-A peripherals connect through the 1750.
10. 10 RELATED MANUALS
Additional information on systems configuration will be found in:
Systems Manual
Communications Peripheral Equipment Manuals
ADSD General Information Manual
Pricing Manual
c
c
10-6
o
o
Software Limitation
It
c
COMPUTER
i
14K-WORD CORf. MEMORY)
I.T) COMMOS
SYNCHRONIZER
A
srmV.GE INCREMENT
(4K·WO!tD CORE MEMORY OPTION)
~
A/Q CHANNEL. MAXIMUM 8 DEVICES - 200 FEET
Like
AI Q chan
E-
EVENT
COUNTER
INPUTS
{
~
.....
F-
~~
CD
sr,.oARD
LCGIC-LEVEL
SIGNALS
EXTERNAL
INTERRUPT
.
N
0
INPUTS
{
CD
PROTECTED,
NONPROTECTED
CONTACT CLOSURE
SlGNALS
Like 1706
I-L
-.::J
0
0
(')
0
K-
G--H-
S
I-L
0
I
-.::J
"0
L-
~
M-
CD
~
U1
~
(f.l
M-
CD
S
1563
~=~~~i
td
......
ANALOG
0
Q
~
54 INPUT/OUTPUT
TElZTYPEWRITERS
tJ
.....
~
aq
~
~
S
HIGH-SPEED, { .
HIGH-LEVEL
ANALOG
_I
INPUTS
UTeHING
I
REI..A.Y
IO-BIT REOOWTION
srANDAHD
LOGIC LEVEL
1 T05 MA
4 T020 MA
1564A - IS64H DIGITAL INPUT
SIGNAL CONDITIONiNG
SlGNALQ
l(lTOSOMA
DIGITAL
INPUTS
PROTECTED.
{ NONPROTECTED
CONTACT CLOSURE
SIGNALS
1564J - lS64R DIGITAL INPUT
SlGNAL CONDInONING
NOTE: @ ALL INTERFACE MODULES SHCM'N ON THE BDCB C-\N ALs:J BE
CONNECTED TO TH E DC1;I
TO 1750
ANALOG
SIGNALS
OUTPUTS
}
10.10
Figure 20 (cont)
Figure 20 is an overall view of a CONTROL DATA® 1700 Computer System; it shows how
different subsystems are used and the methods by which they can be connected. A few basic
facts about the CDC®1700 Computer System are pointed out below. Each statement corresponds to letters on the block diagram.
A
Up to eight input/output (I/O) controllers can be connected directly to the A/Q channel and
up to eight I/O controllers can be connected directly to the direct storage access (DSA)
bus. However, this does not mean that 16 I/O controllers can be directly connected;
only eight can be connected because each controller that is connected to the-DSA bus must
also be connected to the A/Q channel.
B
Only three CDC 1706 Buffered Data Channels and/or the buffered 1716 Coupling Data
Channels can be used in a system complex; this is an addressing restriction, not a hardware restriction.
C
Each Model 1706 or 1716 provides up to eight data channels to which I/O subsystems can
be connected. Either the 1706 or the 1716 permits the attached subsystems to operate
via the direct storage access (DSA) bus.
D
The "OR" box indicates that the attached I/O subsystem can either operate through the
1716 or connect directly to the A/ Q channel. Operation via the 1706 is in the buffered
mode; operation via the A/Q channel is in the unbuffered mode.
E
The CDC Model 1750 DCB Terminator is required whenever a CDC 1500 Series subsystem is used with the CONTROL DATA 1700 Computer. The 1750 provides a data and
control bus (DCB) which is functionally equivalent to the A/Q channel.
F
The DCB provides the capability of attaching up to 15 CDC 1500 Series I/O subsystems,
all of which operate through the A/Q channel via the Model 1750.
G
The CDC 1797 Buffered I/O Interface is required when the attached CDC 1500 Series subsystems must operate through the DSA bus; it provides up to eight priority buffer channels to which the CDC 1500 Series equipment can be connected.
H
The CDC 1571 Chaining Buffer Channel connects to one of the eight priority buffer channels of the Model 1797. Up to three 1571's can be connected to one 1797. Each 1571
uses one priority buffer channel.
c
NOTE
If a 1797 is included in a system, the Model 1571 is also required
to connect existing CDC 1500 Series I/O subsystems.
I
Each 1571 provides a buffered data and control bus (BDCB) to which up to 15 CDC 1500
Series I/O subsystems can be connected.
All devices that are s how n connected to the BDCB can be connected to the DCB (refer to F,
above); this means that the 1797/1571 is only required by system definition.
c~
10-8
10.10
C)
Figure 20 (cont)
J
Subsystems connected to the BDCB normally operate through the Model 1797 and the DSA
bus. However, by program control, they can operate through the Model 1750 and the
A/Q channel.
K
The 1587 A Mas t e r Control Panel, 1587B Digiswitch Panel, 1587C Pushbutton Panel,
1587E Rotary Switch Panel and 1587F Ke yb 0 a rd Panel connect to the 1564A through
1564H Digital Input Signal Conditioning and operate through the 1544 Digital Input Interface with the 1545 Digital Input Sync Unit.
L
The 1587G Annunciator Panel receives its information directly from a 1553 Ext ern a 1
Register Output Interface.
o
10-9
.o
I-'
I-'
o
1700 HARDWARE CONFIGURATION
1704 CO'lPUTER
with 4,096 16-blt
word. of core atorage
Interrupt D,ta Channell 4K Storage Increment
1705
t':fj
......
1708
SL'BSYSTEMS
~
..,
I..~D
trJLTl.SYSIU1 H::'::-:S
Not lupportelf by standard
.~!tv.:, .... ~S3
0:'\1y_
~---------------------------,
co
.
the following products have
direct storage access for
data transfer:
l\:)
I-'
1706
1716
1738
I-'
-::]
0
0
::r:
..,
I-'
0
I
I-'
0
~
H
Up to 3 1706 ' , IMy attach to the
\748
1751
..,
~
M-
lir;o Systeo
Buffered Data Channel
0..
~
..,
.a:"..o:~ot:'
Multiplexer
Controller
170~
Dr ... Interfoee
and Storage
1706
~
a
......
te
1716
1748
1751
1797
~
CO
(j
0
CoupUng Oata
Ch.nnel
A/D
Int~rlace
750 • DeB
~
Ter.dnator
Dhk Storage
Drive Cont1"ollet"
1738 - IX2
W
OCR Document
Reader Controller
1736-1 IXI
MagnetiC Tape
Controllpf
Card Re .. dcr-runC'h
Controller
1728 - lXl
1731 • IX8
t!' 1:'~: Sot:! ••• q'.1!~t:1' UP TO 300 BPS
3316
COiJMJN I CATION S
MULTI PLEXER
CONTROLLER
3000
1748
COMMUN ICATIONS
MULT I pLEXER
CONTROLLER
1700
0
a......
8529 B
DATA SET
CONTROLLER
~
.,
8090
8092
~
c-i......
0
::I
1706
BUFFERED
DATA
CHANNEL
40,800 BPS
I
(
Supplied By ColllTlOn Carrier
)
:
_________________ J
3275 C
DATA SET
CONTROLLER
3000
1747
DATA SET
CONTROLLER
1700
6673
DATA SET
CONTROLLER
6000
6674
DATA SET
CONTROLLER
6000
*Indlcates CDC terminal deylces using compatible data sets may be used,
Use of other than CDC dey I ces. must be coord I nated with csa Product Management.
{~
()
("-,
)
10.10
o
The following is a systems bulletin describing buffered and non-buffered operations:
BUFFERED/NON-BUFFERED OPERATIONS
The purpose of this Data Sheet is to define the terms "Buffered and Non-Buffered" operations
in terms of hardware. Hopefully, this will eliminate any misconceptions in actual hardware
operations relative to the terms. It should be made clear that all I/O devices used with the
1700 Computer are buffered in regard to the handling of data. Each output device or subsystem has a buffer into which the computer can load data. This is a temporary storage media
that holds the data while the output de vic e goes through its slow-speed operation using that
data. During this time, the computer is free to continue on with its program. Each input device or subsystem contains a buffer media into which it loads data until the running program
can accept it as input and during which time the input device is obtaining the next set of data
for entry into the buffer.
Non-Buffered Operations
o
The term "Non-Buffered" operation is synonomous with "Direct" operation, and means that an
I/O operation is in progress and data is being transferred during the execution of an I/O instruction via the computer's A/Q Channel. Therefore, data is either being input to the A-Register or output from the A-register. The Q-register, in each case, holds an address specifying the e quip men t or device from which the data is coming or to which the data is going.
Out put data goes to a buffer for temporary storage until the device can use it and input data
comes from a buffer where it has been waiting. This is the Non-Buffered or Direct I/O
Operation.
Buffered Operations
The term "Buffered" operation means that the program has initiated an I/O operation for the
Direct Storage Access (DSA) bus and is then free to continue its program while the actual data
transfer is completed. The run n in g program is not interrupted until the entire record has
been either read or written. Typically, a buffered operation is carried out as follows:
o
1)
Normally initiated by the computer program executing a "Non- Buffered" input or output
instruction to a device connected to both the A/Q channel and D SA bus. This Non- Buffered
output would be the instruction telling the device or subsystem to start operating in the
"Buffered" mode.
2)
Information supplied to the device during this Non- Buffered operation would be a "Pointer
Word" that would point to a set of control words located in memory.
3)
These control words may represent the Starting and Ending memory addre sses (Record
length) plus any other information required by the device. They may also represent the
starting and ending addresses used by the I/O device.
4)
Once the Non-Buffered op era t io n is completed, the program is free to continue its
function.
5)
When the specified device wants data or has data available, it requests a memory cycle.
10-13
10.10
6)
On the next available memory cycle, the data word is transferred to or fetched from the
memory. Therefore, the program is delayed for one memory cycle each time a data
word is t ran s fer red in or out of memory. This is commonly referred to as cycle
stealing.
7)
After each data transfer, the device or subsystem increments the current address and
compares it with the Ending address. steps 5, 6 and 7 are repeated until the current
address and Ending address match (held in the 1571 or its equivalent).
8)
When the entire record has been transferred, the Buffered operation stops and the program can be interrupted.
Direct Storage Access (DSA)
Direct Storage Access is com m 0 n 1y referred to as Direct Memory Access or may just be
called a memory channel. The 1700 Computer DSA contains a Data Register, Memory Address Register and control logic which enables at t a c h e d devices or subsystems to request
memory cycles and receive access to the memory on a priority basis. The DSA bus always
have a higher priority than the a r it h met i c unit. With no Memory request from DSA, the
arithmetic units requests will continue to be granted for consecutive memory cycles. However, a Memory request from the DSA has first priority so that when received, the next memory cycle is granted for DSA use. Once the DSA has control of the memory, it would use as
many memory c y c Ie s as necessary to satisfy all requests from the devices on the DSA bus.
For e x amp 1 e, if six devices were attached to the DSA bus and all requested memory at the
same time, the program would be effectively stall e d for six memory cycles (6.6 ,Us) while
these six requests were serviced.
Summary
In summary, a Non-Buffered operation passes data in and out of the A-register via the A/Q
channel while the B u f fer e d operation passes data in and out of the memory on the D ire c t
storage Access Bus.
('
"----
10-14
CHAPTER XI
ADVANCED CODING TECHNIQUES
o
III
o
c
c
CHAPTER XI - Advanced Coding Techniques
C)
0
o
11.0
11.1
11.1.1
11.1.2
11.1.3
11.1.4
11.2
11.2.1
11.2.2
11.2.3
11.3
11.3.1
11.3.2
11.4
11.4.1
11.4.1.1
11.4.1.2
11.4.2
11.4.3
11.4.3.1
11.4.3.2
11.4.3.3
11.4.4
11.4.5
11.4.5.1
11.4.5.2
11.5
11.5.1
11.5.2
11.5.3
11.5.4
11.5.5
11.5.6
11.5.7
11.6
TOPIC
PAGE
Introduction
Source, Object and Absolutized Programs
Source Program
Obj ect Program
Abs olutized Program
Form of Programs in MSOS Libraries
Run Anywhere Coding
Writing Programs for Run Anywhere Coding
Buffer Addresses
X Bit in System Requests
Reentrant Coding
Methods of Reentrants
Reentrant Problem, A VG
MSOS Requests Made by System Programs
Schedule
Priorities (Schedule)
Rejects (Schedule)
TIMER Request
I/O Requests
Priorities (I/O)
Rej ects (I/O)
System Request Problem, THREAD
EXIT Requests
SPACE and RELEASE
SPACE Request
RELEASE Request
Coding Mass Memory Programs
Modules in Library
Allocatable Core
Scheduling the Mass Memory Program
Form of Mass Memory Programs
Externals to Mass Memory Programs
Space
Mass Memory Problem, MMPGM
External References and Linkage, Summary
11-1
11-4
11-4
11-4
11-10
11-12
11-12
11-12
11-17
11-19
11-24
11-26
11-31
11-32
11-32
11-34
11-34
11-34
11-35
11-35
11-37
11-38
11-38
11-38
11-39
11-40
11-42
11-42
11-43
11-44
11-44
11-46
11-46
11-47
11-49
11.0
Q
11. 0 INTRODUC TION
Advanced coding techniques for the 1700 will be the special considerations needed for
understanding and writing programs that are part of the system. There are two separate libraries of programs: the Program Library and the System Library.
The programs in the Program Library are relocatable binary programs which are run
in the background as jobs. This would include such programs as the library subroutines
needed by the jobs. They are loa d e d into the unprotected background area of core by
the loader, for execution, after being called in from the teletypewriter. Jobs could' also
be loaded from the card reader or paper tape reader for execution.
The programs in the System Library are absolute programs which are part of the system;
they are run in the foreground in a large area of protected core called allocatable core.
This would include user process programs. The Operating System contains a directory
of all the system programs (all the mass memory pro g ram s and maybe a few core
resident programs). This is like a list of all the programs, by mod u I e name, and it
con t a ins the addresses of where they are. The system uses the directory to find the
programs when it is desired to bring them into core to execute them.
o
Protected core is normally synonymous with the foreground, and unprotected core with
the background. In the background only one program (and its subroutines) would be in
execution at one time at the lowest priority. In the foreground many programs could be
in various states of execution at different priorities. The lower priority ones might have
been suspended (temporarily stopped) while the highest priority one is executed. The
unfinished programs wait in core to finish execution. If the system needs more allocatable core because it is full, it will" swap out" the entire background area to the Swap
area on mass memory, protect the background area, and use it for foreground programs.
When en 0 ugh foreground programs are completed in order to release the background
area, that core is unprotected again and the job swapped back in to continue.
Note that some of the system programs are core resident. The reason all of them are
not core, resident is that they will not all fit in core at once. Therefore, the ones which
are not nee d e d all the time reside on mass me m 0 r y in the System Library and are
called into allocatable core as they are needed.
In order to understand what all these programs look like and how they execute, as well
as how they call each other in to core, it will be necessary to study the different kinds
of programs.
Emphasis in this chapter will be on system programs as background programs will run
with any of the coding techniques previously covered.
11-1
11.0
Protected
Scratch
- -Loader
----Background:
Unprotected
programs)
Allocatable
Core
programs)
+-®
Foreground:
Protected
Core Resident
Process
Programs
Core Resident
Operating
System
Figure 23. ,Mass Memory and Corel\1aps
11-2
c
11.0
(
\
'-.)
An introduction to the priority structure of the running programs under MSOS will also
be helpful as an introduction to this chapter. There are 16 program priorities from 15
(high) to 0 (low). An idle loop runs at priority -1 when the system has nothing else to
do. These priorities pertain to core res ide n t and mass memory resident programs.
When apr 0 g ram is running at its priority, it can be suspended by any higher priority
program which the system allows to run. The suspended program waits in core to resume execution when the priority structure works back down to it.
The priority structure can only be changed by interrupts (hardware) or scheduling (software). The mask in the M register allows hardware, which has a higher priority than
the running program, to interrupt. When an interrupt occurs, the Common Interrupt
Handle r saves all the registers of the interrupted program on the Interrupt Stack (so
that the program can later be resumed) and transfers control to the program which will
service the interrupt on the line.
A schedule request allows a program to change the priority level. If the request is for
a higher level program, a pseudo interrupt will occur immediately (the suspended program goes on the Interrupt Stack) and the hi g her level program is executed. Control
will later return to the suspended program. If the schedule request is for an equal or
lower level priority, the request parameters go on the Scheduler Stack and are threaded
in it by priority to be picked up later when the priority structure works down to that level.
o
All programs exit to the MSOS Dispatcher. It is the Dispatcher that must cause the next
lowest priority program to be executed. It does this by looking at the Interrupt Stack
and Scheduler Stack and finding the highest priority waiting program.
Interrupts
from
Hardware
Scheduled
Programs
All Programs
exit to:
~
DISPATCHER
~
Choos es next
program from
Interrupt
Stack'
Scheduler
Stack
11-3
11.1
11.1 SOURCE, OBJECT AND ABSOLUTIZED PROGRAMS
11.1. 1 Source Program
The source program is the program written in ass em b 1 y language code by the
programmer. It most likely would be punched on cards or on paper tape. Here
is an example of'a source program listing:
0001
0002
START
0003 POOOO 0000
0004 POOOI C400
pOOO2 0006 P
0005 POO03 60FF
0006 POOO4 1400
POOOS 8000 P
X
0007 POO06 0010
0008
I
OOFF
START
NAM
ENT
SOURCE
START
0
0
LOA+
X
STAJMP+
I
NUM
END
510
START
OOOOP X
(START)
0006P
The source program is read into the computer by the assembler. The computer
does not execute the pro g ram at this time. The ass em b 1 e r translates the
mnemonics into binary 0 b j e c t code. The source program is listed at this time
(on the teletypewriter or the line printer) and the 0 b j e c t program is punched on
paper tape (or on the disk, drum or magnetic tape).
11. 1.2 Object Program
It is important to lmow that the object program is not executed either. It must be
loaded by a "relocating" loader back into the computer before it can be executed.
It is not important at this point to be able to interpret the codes in the object program. One must just understand that the codes represent the des ire d program
and that the loader will interpret the codes when it loads the object program and
will make an executable program out of these codes. On the following page is an
example of how the previous source program would look in object form.
11-4
c
11.1.2
c
Figure 24. Object Tape
EISE~s
NAM block
R
C
ms!ltt
E
00
00
00
00
04
00
00
06
60
FF
14
00
80
00
00
'0
CI
•• ••
•• •
•• ••
•
··.. ••
·..
....... .
·· ..... .•
... ...
S
T
A
R
T
1\
• • •••
•••••••••
••••••
••
••
••• •••
•• • ••
•
• • ••••
,
S
T
A
R
T
RBD block
}
}
ENT block
XFR block
Note that each block on the paper tape is preceded by the one's complement of the
word count in that block and followed by a checksum word on that block.
11-5
11.1.2
Figure 24.
Object Tape (Cont)
f
,,""" "-
,,-,,/'
I
--.. NAM BLOCK
001010000 010110000
0
0
0
0
0
0
0
0
'0
0
0
7
a
S
R
u
C
E
RBD BLOCK
0100 0000 0101 0000
0001 0000 0000 0001
0
0
0
0
0
0
0
0
4
0
C
0
0
0
0
6
0000 0000 0001 1000
6
0
F
F
1
4
0
0
, 8
0
0
0
0
0
1
0
0
0
0
0
ENT BLOCK
100010000 010110000
T
s
A
R
T
0
0
0
0
XFR BLOCK
110010000 01011
s
A
T
T
R
11-6
1 word = 2 frames on paper tape
11.1.2
C)
The following is some of the information about the blocks the assembler makes in
the binary object program for the loa d e r. This was extracted from the Loader
Chapter of the MSOS Reference Manual, and it may be consulted for more detail.
Relocatable Binary Input
The loader recognizes r e 1 0 cat a b 1 e binary blocks by the type indicator field in
bits 13-15 of the first word of the block. The following block types are defined:
Type
Indicator
Description
NAM
RBD
BZS
ENT
EXT
XFR
001
010
011
100
101
110
Name block
Command sequence block
Zero storage block
Entry point block
External name block
Transfer address block
If the loader is unable to recognize the indicator, it does not process the block.
NAM Block
The NAM block contains a word count for common storage and data storage, the
program length, and the name of the program.
1
C)
I
0000
0101
0010
J 0000
Number of words in common storage block
Number of words in data storage block
program length
character 2
character 1
Program
character 4
character 3
} Name
character 6
character 5
RBD Block
An RBD block contains a portion of the actual command sequence data of the program. Words 2-59 contain the r e lo cat ion bytes and words for the command
sequence input. Each relocation byte is a 4- bit indicator that identifies a word
of the command sequence input as an absolute 15-bit address or as a 15-bit address
relative to some relocation base. The relocation base for a word is determined
by the particular combination of bit settings within the relocation byte.
Relocation bytes in RBD blocks:
0000
0001
0101
0010
0110
0011
0111
Abs olute (no relocation)
Positive program relocation
Negative program relocation
Positive common storage relocation
Negative common storage relocation
Positive data storage relocation
Negative data storage relocation
11-7
11.1.2
0100
RO
0000
R1
0101
R2
0000
R3
R6
R7
RIO
R11
WO
WI
W2
W3
R4
R5
W4
W5
W6
W7
R8
R9
---
--
R40
R43
R42
R41
W40
W41
W42
W43
R44
not used
R45
W44
W45
Core Image of RBD Block
Wn
Rn
WO
RO
nth word of input block, (n=1-45)
Relocation byte of nth word
Origin addres s of input block
Relocation byte for WO
There is one relocation byte for every word in the command sequence input, and
a maximum of 45 words in an RBD block. The first word is the address at which
the loa d e r begins storing command sequence data. The relocation byte for the
first word address (storage address) of an RBD block may be 0000, 0001, or 0011.
Zero is the leading bit for all but the last relocation byte; one is the leading bit for
the last relocation byte.
In processing an RBD b I 0 c k, the loader picks up the 15 bits which represent the
first word address of the command seq u e n c e data in the block. It adjusts this
address for relocation according to the setting of the bits representing its relocation byte. The resulting absolute address is the first word address in core to
receive the command sequence data (stored in consecutive locations). Each word
is relocated according to its relocation byte.
11-8
(~
\
11.1.2
ENT Block
1000
name 1
I
;
0000
character 1
3
0101
I
character 2
-4
5
6
0000
El
name 2
E2
-
-
-
-
name 13
E13
name 14
E14
not used
not used
o
Core Image of ENT Block
Namen = Six-character name of nth entry in block
En
= Entry point address of nth name
XFR Block
The XFR block contains a t ran sf e r address (in words 2-4), which is six ASCII
characters in length, including trailing spaces. The transfer address must be an
entry point in the program being loaded or in another program loaded during the
same load operation.
1100
I
0101
0000
Character 1
3
5
I
0000
Character 2
4
6
Core Image of XFR Block
The XFR block must be the last in a relocatable binary program. If an XFR block
is out of order, a loader error message is issued and the load is terminated. The
11-9
11.1.2
loader records the transfer address in the XFR block. If two or more relocatable
binary programs are loaded with one operation, the loader saves the last transfer address for the start of execution.
l.,
It is obvious by looking at the code that it could not be executed exactly as it ap-
pears. Normally the programmer n eve r has to know what the object tape looks
like. He would only have to know the format if he wanted to examine parts of the
tape. For example, if he stored a number of object programs on one tape, he may
wish to be able to search the tape for a particular program. He could do that by
writing a program to look at the NAM blocks until it found the right one.
11. 1. 3 Absolutized Program
The programmer is, however, very much concerned with how the program looks
after it is loaded into core for execution. The different addressing modes he used
when he wrote the source pro g ram will determine what the final core image of
that pro g ram looks like. An absolutized program is an exact copy of this core
image, which can be executed. The loader loads and absolutizes the object program at a certain adqress, which is wherever it happens to load it. It also links
the program to any externals and loads and links any library subroutines required.
A utility routine could be used to punch a tape with this core image on it; hence,
the term "absolute tape". Here is an example of an absolutized image of the previous object program, (if the program was loaded at $1000).
($1000)
($1001)
($1002)
($1003)
($1004)
($1005)
($1006)
0000
C400
1006
60FF
1400
9000
0010
0
LDA+
0
X
STAJMP+
I
NUM
Op Code
(START)
$10
Notice that the contents of location $1002 is $1006 to indicate where X is and that
$1005 contains $9000 to indicate the jump through location $1000. The 0006P and
8000P in the source code were relocated by the loader when the object program was loaded. No matter where the program was loaded, the correct addresses
would be filled in at that time.
11-10
C
11.1.3
Figure 25.
o
Flow of Program Through Execution
ASSEMBL Y TIME
Assembler
P option
object tape
(written out by assembler)
Source
Deck
(read into computer
by assembler)
(listed by assembler)
L option
unprotected core
~
o
G
V
object form on
disk scratch
X option
EXECUTION TIME
Loader
Object tape
(generated by program)
C~)
Absolutized
Program
unprotected core
11-11
(loaded into computer
by loader)
11.1.4
11. 1.4 Form of Programs in MSOS Libraries
The reason it is so important for the analyst to understand the distinction between
what the object program generated by the assembler and the absolutized program
after loading look like is because user and system pro g ram s are stored in the
libraries on mass storage in th e s e two different forms. User background programs in the program library are stored in relocatable binary object form. They
will be loaded by the loader into core whenever they are executed, so they will be
absolutized and linked each time they are loaded and' run.
System programs (including user pro c e s s programs) in the system library are
stored in absolutized form and will be read into core (without any changes) whenever they are needed for execution. This is because it must be possible to bring
the real time process programs into memory very fast; the relative time it would
take to load them in with the loader every time they are needed would be too great.
A much better solution would be to write the source program in such a fashion that
the absolutized program could be run any w her e in core and would still execute
properly. The absolutizing of the system process programs is done during system
initialization (by the loader portion of the system initializer) when the programs
are stored on the system library.
11.2 RUN ANYWHERE CODING
11.2. 1 Writing Programs for Run Anywhere Coding
The method devised for writing programs so they can be stored in absolute form
and still run anywhere in core is called Run Anywhere Coding. It is important to
know that this is done at the source level.
Source
Object
~
------------. ~
assemble
Runanywhere or
not Runanywhere
------. D
Absolute
load
anywhere
Runanywhere or
not Runanywhere
Runanywhere or
not Runanywhere
The object program can be loaded anywhere and absolutized and will run correctly
at that time because the loader has reI 0 cat e d any addresses which were in the
program. However, if an absolute image of this program is later run somewhere
else in core, it will run cor r e c t I y if it was coded run anywhere in the original
source form. Here is an example of the same program coded both ways; (assume
it was loaded and absolutized at $1000).
11-12
11.2.1
,.... .. ,
~
,
U
Not Runanywhere
Source
START
X
Absolute
0
0
LDA+
X
STAJMP+
r
NUM
$10
($1000)
($1001)
($1002)
($1003)
($1004)
($1005)
($1006)
(START)
=0
=C
=1
=6
=1
=9
=0
0
4
0
0
4
0
0
0 0
o0
o6
F F.
0 0
0 0
1 0
Runanywhere
Source
o
Absolute
START
0
0
X
X
LDA*
STAJMP*
NUM
($1000) = 0 0 0 0
($1001) = C 8 0 3
($1002) = 6 0 F F
($1003) = 1 CFC
($1004) = 0 010
r
(START)
$10
Notice that the addresses of X and START in the first example were relocated by
the loader to show that X is at $1006 and START at $1000. The program will run
at $1000, but if, for example, it is moved to $2000 without the object being reloaded,
it will not run correctly because it will think X is at $1006 (when actually it moved
to $2006) and then it will jump through $1000 (when actually the entry point START
moved to $2000) •
However, in the second example all addressing in the program is relative. The
LDA * loads from X which is 3 10 cat ion s forward and the JMP* jumps through
STAR T which is 3 locations b a c k war d. Yet the STA- r must be left as it was
because the r register is absolute core location $FF, and it will always be there.
The program is runanywhere because it can be kept in absolute form and can be
later run anywhere in core with correct results.
One might at this point wonder why not code all programs in run anywhere form.
The primary reason is that it is more difficult ~o learn to do run anywhere coding
since there are more chances for the programmer to make errors which will not
produce any error me s sag e s. In general, w hen writing a program to be run
anywhere, all ref ere n c e s to addresses that move with the program should be
relative, and all addresses w h i c h are absolute core locations must be absolute.
o
11-13
11.2.1
COMMON
--"
C
14
... ,.,.,
references to common
absolute
references to subroutine
of program relative
references within ~
program relative
~
SUBROUTINE
~
~ PROGRAM
CORE RESIDENT
PART OF
SYSTEM
SCAN
NAM
ENT
EXT*
EXT
COM
0
RA
SCAN
ALARM
LOWPGM
X(10)
0
LDA+
x+o
1
f
STALDA+
$10C
1
\
RTJ+
ALARM
RTJ
•
references to low core
absolute
relative external
absolute external
reference common absolute
reference $FF absolute
$FF
T
I-
LOWPGM
f
reference interrupt trap
absolute
reference subroutine
relative
reference program. in
system resident absolute
END
Without worrying about the externals at this point, note that all references within
the program area must be relative. A good way to tell if there are any which are
not relative is to look at the source listing and see if any of the codes on the left
are followed by a P, i. e., in the program SOURCE example, change:
,
POOOI C400
P0002 0006,
f
LDA+
X
LDA *
X
f '\
to
POOOI C803
j '\
11-14
11.2.1
Change all loads, stores, jumps, etc., in the program to relative.
Look at the VALUE problem from chapter 6 and observe the addressing used in
the program. COUNT is addressed in two-word relative mode, because the DATA
block most likely moves with the pro g ram and may be further away than 12710
locations. LPMASK+6 is addressed with one-word absolute mode because it is a
fixed low core address. MASK in the program is addressed in one-word relative
mode because it moves with the pro g ram. Yet X in the common block must be
addressed in two-word absolute mode because common is fixed and is in high core.
The LDA VALUE is in two-word relative mode. This implies VALUE is relative
to the TEST subroutine and the assembler requires two-word addressing for any
relative externals.
o
11-15
11.2.1
/'
VALUE PROBLEM
('-- ..
NAM
TEST
COM
DUMMY(10), X(lO)
DAT
DUM (6) , COUNT(1)
EQU
LPMASK($2)
ENT
START
EXT*
VALUE
MASK
BZS
MASK(l)
START
0
0
CLR
Q
STQ
COUNT
LDA
VALUE
AND-
LPMASK+6
ALS
8
STA*
MASK
ENQ
9
LDA+
X,.Q
AND
=N$3FOO
EOR*
MASK
SAN
t
RAO
COUNT
SQZ
EXIT-*-l
INQ
-1
JMP*
SEARCH
JMP*
(START)
SEARCH
EXIT
END
11-16
('~
........ " ..
'
11.2.2
U
11.2.2 Buffer Addresses
Buffe r addresses used for indirect addressing (to load or store) in the program
must be absolutized each time they are used. If the buffer is in low core system
resident, it can be absolutely addressed:
I
I
BUFADR
EXT
ADC
I
BUF
BUF
I
I
I
STA*
(BUFADR)
I
I
The address assembled into BUFADR will be the absolute address of the buffer.
Since the buffer will never move, even though the program moves, the addressing
will still be correct.
However, if the buffer moves with the program, the ADC would not work because.
it would contain the address of where the buffer was when the program was absolutized. In the following example RE LA TIVE the buffer BUF is in the program at
P0007. BUF ABS must always contain the address of where the buffer really is.
If we used:
o
BUFABS
ADC
BUF
BUFABSwouldassemble as 0007P which, if the program was absolutizedat $1000,
would contain $1007. Whenever the program moved, the buffer would not be at
$1007 any more. Neither would the example at P006C work correctly for the same
reason.
Study the code beginning at POOOO and see that BUF ABS is calculated each time it
is used. The RTJ* will cause the current address of the BD ins t r u c t ion to be
stored in BD. (R TJ stores P+1 in jump add res s, then RNI at P+2.) Then the
LDA calculates the distance from BUF to BD. ADD the contents of BD (the current
address of BD) and store it in BUF ABS to calculate the buffer address!
11-17
11.2.2
CORRECT
~
000 I
..... _. ___ ... __ ._.____ ... ___________NA M. _R.~J~~_l! VE
·---·-0002---0003
POOOO._.5801
RTJ*
*+1
. -- ... _.
. . . . . ---------_...... _. __._...-_._--0004 POOOI 0000
SO
NUM
P0002
COOO - -_._.._ .' __ -.__•______ -.---.LDA .- ----- .-----.-.--=
XBUF-BD
~.-,, 7 _ ..•. _ 0005
.
.
.....
.
-__ . .
.. -. -... - '-' ...•. -..•.- -.-
*
r?~
1-,
I
~--.....
.
.
.
P0003 0006
0006 P0004 88FC
ADD*
a
SD
( ' ~"--OO 0 7-'-PO 005 '-'6 86 G-' -----···--··---·-------S TA*·--··-·------- B UF' A8'S
?
_0 0 0.8 _______ .... _._._. . _. _______~ __. _______ ._..____
*
0009
__.________._._.__
('lOOI0 P0006 0000
SLS
'... In·----·
1'1
--"PO
ob1·--··0·064----·-·BU-~----------ljz S----------- B·UF ('1'00) .
oo
0012 POOGB 0001
BUFABS
BSS
BUFABS(l)
11.___ . .. . ... ---- ... - ..' ..--. --"--" -. - --. - ----- .. ----.- ------ - ------ - -- .--------- ---.- _ .. - ........... -- - -. r
0013
0014
11-00'1'S--pcftf({c-C'o-6b . - - - - - LDA
=XB"uF'--P006 D 0007 P
*
INCORRECT
*
1J---'b(fi'6-~P'()'O 6-E--6
1~
g-FC-------------------S·TA*---------·B·U F' A-a g-'- -- .
_
._____________________________________________________________________
0017
END
The b u f fer address will be correct whether the buffer is forward from the LDA
=XBUF-BD or behind it, because of the 15-bit arithmetic used. With BUF in its
current location the calculation would be
0007
-0001
0006
+0001
0007
C
....
assembled
If the buffer were at 7FFE relatively, the calculation would be
7FFE
-0001
7FFD
+0001
7FFE
assembled
A very nice way to clean up even the correct code above would be:
BUF
BUFABS
RTJ*
BZS
0
BUFABS
BPF(lOO)
0
1
('
\
11-18
11.2.2
C)
The RTJ jumps over the buffer, taking the buffer address with it.
BUFABS, then continues execution following BUF ABS.
It stores it in
Look at the peripheral program BOOTSTRAP for the paper tape reader in chapter
8. Location P0012 is used to contain the buffe r address of where the data is to
read into. Since this address is program relocatable (contains 0014P), the program is not run anywhere be c au s e when it is loaded and absolutized P0012 will
contain the absolute buffer address at that time. If the program and buffer were
moved, ADDRES would then contain the wrong buffer address.
More coverage of the externals for run anywhere programs will be mentioned in
a later section, 11.6. How the externals are written depends primarily on where
they and the referencing program are in the system.
11.2. 3 X Bit in System Requests
In run anywhere programs, the X bit must be used in s y s t e m requests; and ad-
dresses used in the requests must follow the same rules for add res s e s in the
program which move relative to the program or are external in low core.
The following example is for the X bit being set in a schedule request:
o
($F4)
,(
N7 19, N111, N8/8 ---+ ~_9--.J1L---1.L..-1_0--,-18_-1
HE LP+ 1
•.
dis tance
RTJVFD
ADC*
Since this is a request made from a run any w her e program, the address being
scheduled, which is HE LP, must be relative if HE LP is relative to this request.
(HE LP could be in the scheduling program or external to it.)
When the X bit is used as above to indicate relative addresses, the relative distance must be from the first word of the parameter string (not from the RTJ or
the ADC). That is why the relative address constant (ADC* HELP+1) is coded as
HE LP+1 instead of HE LP. The dis tan ce established from the ADC to HE LP+ 1
would be the same dis tan c e as from the VFD to HE LP , which is the distance
required by the operating system.
POOOO
POOOI
POO02
POO03
POO04
POO05
POO06
POO07
POO08
POO09
54F4
1308
00-07
RTJVFD
ADC*
7
7
HELP
(---')
'-,-/
11-1-ff
($F4)
N7 19, N111, N8/8
HE LP+l
11.2.3
Of course, if HELP were a core resident program, it would have to be scheduled
absolutely from a run anywhere program. It can be scheduled this way tV'en if it
is in the sys tern directory.
54F4
1208
7FFFX
RTJNUM
ADC
($F4)
$1208
HELP
EXT
HELP
r
When the X bit is set to indicate relative, all addresses in that request must follow suit. In an I/O request, for example, the completion address and huffer
address must be relative. Again, they must be relative to the first word of the
parameter string.
REQ
RTJNUM
ADC*
NUM
NUM
NUM
ADC*
COMPL
1
BUF
~
($F4)
$OD56
COMPL+1
0
$18FC
10
BUF+5
FWRITE, RP=5, CP=6
ASCII, STD PRINT DEV
Note that COMPL+1 is used to add 1 to the distance between the ADC* and COMPL
(to make it relative to REQ). BUF+5 is used to add 5 to the distance between the
ADC* and BUF. The number of words does not have to be relative even though
the X bit is set.
If it is desired to use relative addressing to locate the number of words, it would
be done as follows:
REQ
RTJNUM
ADC*
NUM
NUM
ADC*
ADC*
$18FC
(N+4)
BUF+5
NUM
10
($F4)
$OD56
COMPL+1
o
COMPL
BUF
N
"11-20
C"~
11.2.3
All other requests which can utilize the X bit for relative addressing must follow
the same pattern.
The ADC* in the above examples will only calculate the correct distance for addresses forward from the ADC*. Since the r e 1at i v e address must be a 15-bit
positive increment which is added to P and must work whether the distance is forward or backward, the following method is often used:
ADC
COMPL-*+l
ADC
BUF-*+5
or
The regular ADC form used here has an expression in the address field which will
always calculate the correct distance. The desired address minus the current P
counter makes a 15-bit relative distance from P and the adjustment of +1 or +5 in
the example is for a completion or buffer address.
Figure 26 shows incorrect examples of relative addressing. See MMPGM in the
mass memory coding section 11.5.7 for more examples. Relative addressing is
detailed in Chapter 8 of this manual. Also, the MSOS Reference Manual contains
details of using the X bit in all system requests.
o
C)
11-21
11.2.3
Figure 26. Error Examples for Incorrect Addressing in
Mass Memory Programs
! NOTE:
0013
0013
0013
0013
0013
0013
FWRITE
POO02
POO03
POO04
POO05
POO06
POO07
0013
0013
POO02
POO03
POO04
POO05
POO06
POO07
POO08
$FC, WROTE, MSGBUF, 10, A, 5,6, 1,1
54F4
OD56 4
• - - - - X bit set
0012 P
0000
But address still program relocatable
18FC
OOOA
. . - - Buffer was at P0018 in early example
~
0013
0013
0013
0013
Buffer is at P0018
Completion address is at P0012
FWRITE
$FC, WROTE-*+ 1, (MSGBUF), 10, A, 5, 6, I, X
54F4·
OD56 4
.. - - - - X bit set
dist. to WROTE
OOOF .----Rel.
..
0000
18FC
OOOA
bit on buffer address
8018 P ...---Indirect
..
NOTE. Buffer is at P0003
. Completion address is at P001D
WRITE
0016
0016
0016
0016
FWRITE
c
$FC, *-WROTE-5, *+MSGBUF-5, 10, A, 5,6, I, X
POOOD 54F4
POOOE OD56
~ - - - - - - Wrong reI. dist. to compl.
POOOF 7FEC 4
P0010 0000
0016 P0011 18FC
0016 P0012 OOOA
********RL*********
4 - - - - - - Illegal relocation to buffer
~~
0016
0016
0016
0016
0016
0016
WRITE
POOOD
POOOE
POOOF
P0010
P0011
POO12
POO13
FWRITE
$FC, *-WROTE-5, *-MSGBUF-5, 10, A, 5, 6, I, X
54F4
OD56
-4 - - - - - - Wrong reI. dist. to compI. (appears backward)
7FEC .
0000
18FC
OOOA
~
- - - - - - Backward reI. dist. to buffer (appears forward)
OOOB 4
c
11-22
11.2.3
()
Problem: Write a runanywhere program.
Given: skeleton of a program which computes an average of 10 pos itive numbers.
AVG
LOOP
TEST
o
AV
NAM
AVERAGE
ENT
AVG
BZS
OVFL(1)
0
0
ENQ
9
ENA
0
SOY
0
ADD*
X,Q
SNO
TEST-*-1
RAO*
OVFL
AND
=N$7FFF
SQZ
AV-*-1
INQ
-1
JMP*
LOOP
LDQ*
OVFL
ALS
1
LRS
1
DVI
=N10
JMP*
(AVG)
END
AVG
11-23
11.2.3
a.
Write a main program, with a buff e r with data in it, to call A VG as a subroutine. Set up the proper lin k age between the main program and its subroutine. The main program should punch the answer (the average of the data)
on binary paper tape. * Be sure the pro g ram s work before going further.
b.
The programs should be coded in runanywhere form and should not des t roy
themselves.
c.
To check out the runanywhere features of the programs add a move subroutine
to move the main program and A VG to a higher core area after they have run
once and given one answer. Then control should be transferred to the entry
point of the m a in program at its new add res s to run it again and see if it
gives the same answer.
C~·
This will simulate a runanywhere mass memory module being executed in a
different core area, and it can be checked out in the b a c kg r 0 u n d with the
protect switch set.
If CONVRT is used, it should not be moved in the move and should be addressed
absolutely. This is because it is not runanywhere. Using CONVRT would
s i m u 1 ate a mass memory module calling a core resident subroutine which
remains at a fixed location even though the module runs in different locations.
11.3 REENTRANT CODING
I'~
It is necessary in a real time process en vir 0 n men t for many of the programs to be
reentrant. This is because the process programs run at different priority levels and
may have common subroutines. A reentrant program is one that can be entered at more
than one priority level. The program may begin its computations but be stopped (perhaps as a result of a hardware in t err u p t at a higher level). Then it may be entered
again at a hi g her level (perhaps by being called by the higher level interrupting program). It mus t do a computation for the hi g her level calling program. Then it mus t
resume the original com put a t ion later without losing any continuity or results. An
example of a situation in which a subroutine PGM must be reentrant is as shown on the
following page.
l._"
*The main program could instead call the CONVRT conversion subroutine to convertthe
hexadecimal answer to ASCII codes, then write it in ASCII on the teletype.
11-24
c
11.3
o
(Priority 4)
(Priority 6)
Program A
Program B
CD
r- -
o f
r
PGM
RTJ+
: @r
I
I
RTJ+
r - -.
CDI
---.
: °1
I
Exit
I
I
I
PGM
CD
Exit
I
I
I
I
I
I
I
J
+-:-( _________
L _ _ - .PGM
CD hardware
o
°1
I
I
-1
CD:
I
interrupt"
I
I
@~
I
I
L __ _ _ _ _ _ _ _ _ @EXit __ -lI
\ CD
1. Program A runs at Priority 4 and
2. calls PGM (at same priority).
3. PGM is running when
4. an interrupt occurs.
5. Pro g ram B begins to run at priority 6 (higher) as a result of the interrupt, and
6. it, too, calls PGM.
7. PGM must run a calculation for program Band
8. return to program B.
9. Program B must complete and exit. At that time
10. the priority drops back down to 4, and PGM resumes its computation for program
A where the interrupt 0 c cur red. It must correctly complete its run for A and
11. return to program A. A then can
12. complete and exit. PGM must be reentrant so it can make correct computations
and exits for A and B.
11-25
11.3.1
11.3.1 Methods of Reentrants
There are a n urn be r of d iff ere n t methods which are used to make programs
reentrant. ]700 MSOS provides for reentrant programs by con t a in i n g a core
area called Volatile Storage which any pro t e c ted program may use. Volatile
storage is actually a BSS block in the pro g ram VOLA and its size is set up at
system initialization time. A program can establish its reentrancy by requesting
a temporary area of volatile storage for each run in which to store its temporary
results during ex e cut ion. No locations in the program are a can be used for
temporary results because they would be destroyed if the program was reentered
before it completed execution. The ref 0 r e, all data would be either in volatile
storage or in the registers. (P, A, Q and I would be saved in the interrupt stack if
an interrupt occurred. )
The follow in g program can be used as an example and it will be recoded to be
reentrant. The addresses of two parameters which are to be add e d together by
the subroutine are passed in A and Q. The answer is to be passed back in A.
ADD2
NAM
ENT
0
STA*
STQ*
LDA*
ADD*
JMP*
f
BSS
END
ADD2
ADD2
0
TEMP
TEMP+1
(TEMP)
(TEMP+l)
(ADD2)
STORE ADDRESSES OF
PARAMETERS.
PICK UP PARAM 1
ADD PARAM 2
RETURN WITH ANSWER
IN A
TEMP(2)
The program as it is written above would not be reentrant because its return address andparameter addresses would be lost if the program was reentered before
it was finished.
11-26
(~
'-. .. '
11.3.1
r'.
(-)
The following is the program coded in reentrant form.
1.
2.
3.
4.
5.
6.
7.
NAM
ENT
EQU
0
IIN·
RTJ-:NUM
EIN
LDA*
STALDALDQADDSTALDQIIN
STQ*
RTJEIN
JMP*
END
ADD2
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
EXIT
C)
ADD2
ADD2
A VOLA($BB), A VOLR($BA), ZERO($22)
0
ENTRY POINT
LOCK OUT INTERRUPTS
(AVOLA)
GO GET SOME VOLA TILE
4
4 WORDS WANTED
ADD2
3,1
(ZERO), Q
1,1
(ZERO), Q
1,1
3,1
PICK UP RETURN ADDRESS
SA VE IT IN VOLA TILE
GET PARAM 2 IN A
GET PARAM 1 ADDRESS IN Q
ADD PARAM 1 TO PARAM 2
PASS ANS. BACK IN A
PICK UP RETURN ADDRESS
ADD2
(AVOLR)
STORE RETURN ADDRESS
GIVE BACK VOLA TILE
ENABLE INTERRUPTS
EXIT
(ADD2)
M
Z
t-3
~
~
M
~
.......
t-3
4-word volatile storage block
3
Return
2
I
1
A
(I) + 0
Q
:=}
calling program's registers
I
Subroutine ADD2's I register contains volatile address.
A separate 4-word block of volatile storage will be assigned each time the program
is reentered. Since its I register is always saved when an interrupt occurs, the
value of I in each run will locate the specific block being used in that run.
S u c c e s s i v e blocks allocated will always be to higher priorities and, naturally,
release will be in reverse order.
11-27
11.3.1
$1008
$1004
$1000
r1
rl
r1
turn
Volatile assigned on 3rd en try;
i.e., at priority 6, I register
contains $1008
mrn
Volatile assigned on 2nd en try;
i.e., at.priority 5, I register
contains $1004
turn
Volatile assigned on 1st en try;
i. e., at priority 4, Ire g is t e r
contains $1000
Lines 1 through 7 in the e x amp I e ADD2 program could be the same in any reentrant program consisting of getting volatile storage for that run and saving the
return add res s. Lines 12 through 17 could be the same also, con sis tin g of
ret urn in g the volatile and exiting. Lines 8 through 11 comprise the program
itself. Note that in this case no TEMP's were needed because the par a met e r
addresses in the calling program's A and Q registers are con t a in e d in volatile
locations 1 and 0 and they can be used to access the parameters. The following
is a line-by-line description of the reentrant coding for the ADD2 program.
r'"
1..........
1.
The entry point is entered by a RTJ from the calling program.
2.
The subroutine must lock out interrupts because the return address which the
RTJ stored in the entry point must not be lost. Since the RTJ instruction
s tor e s its return address in the jump address and does an RNI at jump address+1 (line 2, the IIN) an interrupt cannot occur and wipe out the ret urn
add res s in ADD2 before the IIN. The IIN must also be in effect before the
R TJ to VOLA because VOLA is not r e en t ran t and expects interrupts to be
locked out before it is entered.
3,4 Jump to VOLA (through locore location $BB). Pass a parameter to VOLA
requesting four words of volatile storage. A different block will be assigned
each tim e this subroutine is entered, and the address of the block comes to
the calling pro g ram (ADD2) in I. ADD2 must never destroy its I register
because it contains the address of the volatile b I 0 c k. VOLA also saves the
calling program's Q, A and I registers in the first three words of the block.
All the registers inADD2 (including I) will always be safe from an interrupting
and r e e n te ring program because ADD2's registers would be saved on the
interrupt stack.
\'
\--
11-28
.
11• .3.1
5.
En a b I e interrupts as soon as possible because it is illegal to lock them out
for more than 50}.ls (including the time in VOLA).
6.
One free instruction is allowed after the E1N before an interrupt can occur; so
the return address is rescued from the entry point -- it will be safe in A. At
any time after this point an in t err up t can occur and the Interrupt Handler
will save the registers.
7.
Store the return address in volatile so that the A register can be used in the
program.
8.
Q still has the address of parameter 2 in it from the calling program so itcan
be used to get the parameter into A.
9.
The address of parameter 1 was passed in A and VOLA put it in the 2nd word.
It can be loaded into Q.
10.
Parameter 1 is then add e d into A using the address in Q. Note in 8 and 10
that the addresses are put in Q. One way of addressing the parameters which
would not work is:
LDAADD-
(1+1)
(1+0)
It looks like it would work because the addresses are in 1+1 and 1+0 but this
would be assembled as $100 and $FF which of co u r s e is not where the addresses are. An assembly error would probably occur at the 1+1. Another
method which would not work is:
o
LDAADD-
($3), I
($22), I
Location $3 has a 1 in it to which will be added the contents of $FF (giving 1+1)
and the add would be from 0+ the con ten t s of $FF (giving 1+0). This would
get the par a met e r address in A. Then the ADD would add in the second
parameter address.
11.
The answer is stored in volatile+1 because that is where VOLR will restore
the A register from. Any parameters to be returned in registers must be put
in the first three words of volatile.
12.
The return address must be picked up out of volatile because volatile is going
to be returned and it would be lost.
13.
Interrupts are locked out for exiting.
14.
The return address is stored in ADD2 because the
replace ADD2' s Q.
o
11-29
0
rig ina I Q is going to
11.3~1
15.
Vol a til e is returned. VOLR restores the original registers from the first
three words of volatile! That is why the an s we r was put there, to get it in
the original A. Also, since volatile is now gone, the return address had to
be res cued; and it c 0 u 1 d not be left in Q (to exit through Q) because ADD2' s
Q is gone.
16.
Enable interrupts.
17 •
Free instruction to exit.
Incorrect example:
line 10
ADDLDQ-
RTJEIN
..------+. JMP*
(ZERO), Q
3,1
(AVOLR)
ANSWER IN A.
RETURN ADDR INQ
RETURN VOLATILE
(ZERO), Q
Q now has the original Q in it, not the return address; also the answer in A
was clobbered and has the original A in it.
If any other t e m po r a r y locations were needed by the reentrant program, they
would be requested in vol at i 1 e and would be addressed the same way. For example, if it was desired to move the par a met e r addresses to volatile +5 and 6
(like TEMP's in non-reentrant program), the NUM in line 4 would be 6 and lines
8 through 12 would be replaced with:
LDASTALDQ+
STQLDQLDALDQADDSTA-
1,1
4,1
0,1
5,1
4,1
(ZERO), Q
5,1
(ZERO), Q
1,1
11-30
PICK UP PARAM 1 ADDRESS
MOVE TO TEMP (1+4)
PICK UP PARAM 2 ADDRESS
MOVE TO TEMP+1(I+5)
GET PARAM 1 ADDRESS IN Q
GET PARAM 1
GET PARAM 2 ADDRESS IN Q
ADD PARAM 2 TO PARAM 1
STORE ANSWER TO PASS IN A
~'
....... ..
,
,"
11.3.1
5
address of
parameter 2
4
address of
parameter 1
3
return
2
I
1
A
(I) + 0
Q
0
This example coding (immediately above) is used simply to ill u s t rat e how the
program can a c c e s s volatile for its temporary results. Of course, it would be
inefficient to code the present example this way because the move and reloading
are not necessary. Study all the addressing carefully.
11.3.2 Reentrant Problem, AVG
o
Following is the AVG program which computes an average. Rewrite the program
as a non-destructive and reentrant subroutine. Assume that the calling program
passes the number of words in A and the first word address in Q to the subroutine.
The subroutine s h 0 u 1d pass the average back in A and the remainder in Q. Remember that interrupts may not be in hi bit ed more than 50 J1S at anyone time.
AVG
LOOP
TEST
AV
NAM
ENT
BZS
0
ENQ
ENA
SOY
ADD*
SNO
RAO*
AND
SQZ
INQ
JMP*
LDQ*
ALS
LRS
DVI
JMP*
END
AVERAGE
AVG
OVFL(l)
0
9
0
0
X,Q
TEST-*-l
OVFL
=N$7FFF
AV-*-l
-1
LOOP
OVFL
1
1
=N10
(AVG)
AVG
o
11-31
11.4
11.4 MSOS REQUESTS MADE BY SYSTEM PROGRAMS
Remember that all requests to MSOS simply put a des ire d action (such as a Write or
Schedule) on a list (queue) and that the action mayor may not be performed (depending
on the rules) before control returns to the requestor.
There are special con sid era t ion s system programs (either core resident or mass
memory resident) must make when making requests to the operating system. This is
in addition to the considerations and rules jobs must follow.
First, all pro t e c ted programs must check a request after it is made to see if it was
accepted. When control is returned to the requestor beneath the parameter string, Q
will be positive if the request was accepted, negative if the request was rejected. For
example:
f
CKQ
REQOK
. RTJNUM
ADC
SQP
JMP*
($F4)
$1206
PGM
REQOK-*-l
REQREJ
schedule request
f
In the above example when control is ret urn e d at CKQ, a skip is made to REQOK if,
indeed, the request was accepted. Otherwise, (Q negative) a jump is made to REQREJ
because the r e que s t is rejected. If a request is rejected, the program might either
rep eat the request at REQREJ, change the priority, or print an error message. Remember that when a job made a request, the system would continually repeat the request
until it was accepted, then return control to the program beneath the parameter string.
However, all protected programs should check every request in the above fashion since
there will be no other indication if a request is rejected.
c
Even though a bit of Q is used to in d i cat e acceptance or rejection of a request by the
system, if the program were passing a parameter in Q, the full 16-bit original Q is still
passed intact. Only the upper bit has been changed when contI-ol comes back to the requestor.
11.4.1 Schedule
A schedule request made by a s y s tern program would be coded the same as one
made by a job except the requestor should check to see that it is accepted. Examples would be:
)
RTJNUM
ADC
SQP
JMP*
OK
($F4)
$1205
WRITE
OK-*-l
REJ
f
WRITE is in the scheduling program. It will be executed at priority 5.
11-32
c
f
0
EXT
f
RTJNUM
ADC
SQP
JMP*
OK
11.4.1
MIPRO
($F4)
$1204
MIPRO
OK-*-1
REJ
f
MIPRO is external to the scheduling program and will be run at priority 4.
core resident and not in the system directory.
It is
y.
EXT
l
RTJNUM
ADC
SQP
JMP*
OK
o
MIPRO
($F4)
$1204
(MIPRO)
OK-*-1
REJ
)
Here MIPRO is in the system directory and will run at 4. The MIPRO program
could be either core resident or mass memory resident. The scheduling program
does not have to know where MIPRO is as the system will find it.
There is an important consideration to make when deciding whether to schedule a
program with the regular external form or whether to schedule it with the system
directory for m (having the program in the system directory). If it is undecided
whether the scheduled program will be core resident or mass memory resident,
use the system d ire c tor y form as it will work in either case. The same logic
would apply to a core resident program which may later be a mass memory program. Using the system directory form simply causes the system to have four
more words of core (for the directory entry) and take a few microseconds longer
to schedule but this can save miles of recoding.
11-33
11.4.1.1
11.4. 1. 1 Priorities (Schedule)
The system program will be concerned with the priorities of the scheduled programs. The software p rio r it i e s run from 15 (highest) to 0 (lowest). The C P
(completion priority) fie 1 d in'the request is the desired priority for the address
scheduled. This Ineans that scheduling is actually like jumping to an address and
changing the running priority concurrently.
If the priority in the schedule request is lower than or equal to the current running
priority of the program making the request, the scheduled program will run after
the current program is finished and the p rio r it y works down to it. It waits by
priority in the scheduler stack with other scheduled programs. This is the way to
set up things to be done after the current program exits.
If the scheduled priority is higher than the running priority, a p s e u d 0 interrupt
occurs immediately and the scheduled program is executed. Then control returns
back to the requestor.
Pro c e s s programs usually run at priorities of 4, 5 and 6. Jobs run at 0 and 1.
Other priorities are us u a 11 y for the operating system and hardware interrupts.
11.4. 1.2 Rejects (Schedule)
A scheduled request for a core resident system program which is not in the system directory would be r e j e c ted if there is no room in the scheduler stack (the
queue for waiting scheduled programs) for the request parameters. If the request
is for apr 0 g ram which is in the system directory and that program is already
threaded on some thread, a reject would occur. This implies that the program
has been scheduled (perhaps by some 0 the r program) and not yet finished.. Parameters for schedule requests for system directory programs are not transferred
to the scheduler stack so a reject would not occur as a result of the s c h e d u 1e r
stack being full.
At this poi n t it could be noted that relatively minor modifications to the system
would be required to allow for a que u e of requestors waiting to rerun a desired
system directory program (for example, a mass memory program which is already
in core). It would even be possible to allow that mass memory program to be reentered by a higher priority interrupting program (in which case it would have to
be reentrant).
11. 4. 2 TIMER Request
Since TIMER requests are simply delayed scheduler calls, they may be made by
system programs with the same considerations as required for scheduler calls.
11-34
C
11.4.1.1
(j
11.4.3 I/O Requests
The I/O requests (READ, WRITE, FREAD, F W R I T E) must consider priorities
when these requests are in protected programs
They must also check to see if
the requests were accepted. The actual operation of what the requests do is the
same as for jobs.
o
The following is an FWRITE example:
RTJNUM
ADC
NUM
NUM
NUM
ADC
SQP
JMP*
T
OK
WROTE
BUF
~
BSS
($F4)
$OC76
WROTE
FWRITE, RP=7, C P=6
COMPLETION
o
$18FC
35
BUF
OK-*-l
REJ
ASCII MODE, STD. PRINT DEVICE
35 WORDS
BUFFER ADDRESS
T
l
BUF(35)
END
o
11.4.3.1 Priorities (I/O)
The request priority (RP=7 in example) has a b sol ute 1y nothing to do with the
running priority of the program. It is the priority of this request with respect to
other requests for a logical unit number. In other w 0 r d s if there are RP=6 and
RP=10 r e que s t s waiting to be written on the printer, the RP=7 requests will be
threaded in between the 10 and the 6. Each logical unit has a queue of requests
waiting for it and the driver will handle them sequentially by priority. When the
write actually gets done is a function of the driver (program) priority and its relationship with the priority of the running program. For example, if the teletype
driver runs at priority 10 and the program runs at p rio r i t Y 6, the driver will
periodically interrupt the program to do the actual write operation.
The completion priority in the requests (CP=6 in example) is related to the running
priority of the program. It is like a schedule request for the completion address
after the I/O is finished. In the example, if the running priority is 4, a pseudo
interrupt will occur and the priority will be changed to 6 when the I/O is finished
and the completion routine entered.
o
11-35
11.4.3.1
From the time the request is in it i ate d until the time the I/O is completed, the
thread word in the request will be non- zero. Here is an example of apr 0 g ram
which runs at priority 4, initiates a request, and loops waiting for the request to
be finished.
THREAD
LOOP
RTJNUM
NUM
NUM
NUM
NUM
ADC
SQP
JMP*
LDA*
SAZ
JMP*
($F4)
$OCEO
0
0
$0804
35
BUF
LOOP-*-l
REQREJ
THREAD
COMPL-*-l
*-2
FWRITE, RP=14
NO COMPLETION
THREAD
ASCII, OUT ON TTY
REQUEST ACCEPTED
THREAD ZERO YET?
SKIP OUT; I/O DONE
COMPL
Many programs have been coded this way; and this should not be done. Looping
like this at any p rio r it y is going to slow down a s y s t e m by locking out lower
priorities. For example, if many process programs were coded this way, they
could almost completely lock out job processing (which runs at 0 and 1). It would
be much better to cod e the write with a completion address and jump to the dispatcher to wait for the completion routine to be entered.
C
It is important to control the priorities in a program which makes a number of I/O
requests. Com pIe t ion routines should be very short and should be at a higher
priority than the rest of the program to cause a software interrupt in the program
when I/O is complete. Completion priority could be lower than running priority
if it is simply desired to check for errors at the end of the pro g ram or if it is
desired for the programs handling the data to run lower.
If a program is to run at priority 4 and all its I/O completion is to run at priority
5, it would be necessary for each completion routine to schedule the priority back
down to the program priority before initiating the next request.
c
11-36
11.4.3.1
0
EXT
EQU
T
REQOK
COMPRD
SCHPRT
0
PRINT
REJ, IOERR
ADISP($EA)
RTJNUM
ADC
NUM
NUM
NUM
ADC
SQP
JMP+
JMP-
($F4)
$0875
COMPRD
0
$1005
40
BUF
REQOK
REJ
(ADISP)
SQP
RTJ
RTJ
NUM
ADC
JMPRTJNUM
ADC
NUM
ADC
SCHPRT
IOERR
($F4)
$1204
PRINT
(ADISP)
($F4)
$OC05
COMPPR
0,$1004,35
BUF
FREAD, CP=5
COMPLETION
ASCII, LUN 5=CR
40-WORD BUFFER
PRIORITY HERE IS 5
SCHEDULE, DOWN TO 4
PRINT IN SAME PGM
PRINT NOW AT PRIORITY 4
FWRITE, CP=5
LUN 4 (TTY), 35 WORDS
1
11.4.3.2 Rejects (I/O)
An I/O request could be r e j e c ted if the request is already threaded (like if the
program tried to start up that write again before it was finished) or if the system
tries to schedule the driver and finds the scheduler stack full. (In that case the
driver's priority would be lower than the running priority of the program and that
is not normal. )
11-37
11.4.3.3
11.4. 3. 3 System Request Problem, THREAD
The following example program .runs at priority 12 and makes a Write request for
the teletypewriter (logical unit 4) at priority 14. Since it has no completion address, it does not jump to the dispatcher to wait for the Write to be finished as
control would not return to the pro g ram. Instead, it waits for the Write to be
finished by looping on the thread word at LOOP. (The thread word was filled when
the request was made and becomes z e r 0 again only when the driver has finished
this request.) The driver runs at priority 10.
THREAD
LOOP
RTJNUM
NUM
NUM
NUM
NUM
ADC
SQP
JMP*
LDA*
SAZ
JMP*
($F4)
$OCEO
0
0
$1004
35
BUF
LOOP-*-l
REQREJ
THREAD
COMPL-*-l
*-2
FWRITE ,~RP=14
NO COMPLETION
THREAD
ASCII, OUT ON TTY
COMPL
When will the write actually be done?
c
11. 4. 4 EXIT Requests
All pro g ram s exit to the dispatcher. This is so the dispatcher can pick up the
highest priority program waiting to be executed next, whether it is a previously
interrupted program or a scheduled pro g ram. This is how the priority drops.
The EXIT request made by an unprotected program generates a jump to the dispatcher. A protected pro g ram may not use the EXIT request; it must code the
jump to the dispatcher:
f
EQU
1
JMPEND
ADISP($EA)
(ADISP)
11.4.5 SPACE and RELEASE
There are two requests which only protected programs are allowed to make: Space
and Release. These requests are used to get, and later release, core in the protected area called allocatable core. Any unprotected program may a c c e s s this
~'
-....,
11-38
·"
U
11.4.5
\
area and may use the space for anything it desires -- to contain data or programs.
The allocatable cor e area is divided into priority blocks (so that some core will
always be available at the highest p r io r it ie s). The sizes of the blocks at each
priority are set up by the systems analysts at system initialization time.
11.4.5.1 SPACE Request
Here is the format of the SPACE request:
RTJ15
I
($F4)
9 8
o
4
I I
RC=10
COMPL
THREAD = 0
Q
N WORDS
RP
1
CP
The Macro form for the SPACE request would be:
SPACE n, compl, rp, cp, X
RC is request code 10. Bit 8 is X bit.
o
RP is priority of the block in which space is des ired.
C P is the priority of the completion address.
COMPL is the completion add res s of where control will go after the space has
been gotten.
THREAD is the thread word, zero •
..s. is
the Q register par am e t e r passed back to the completion routine.
contain:
Q will
address - of the space gotten, or
$8000 - if no space will ever be available at this p rio r it y; this means
that even if the background were swapped out there would still
not be enough core to fill the request.
N WORDS is the number of words of space requested.
The address of the space would also be in core immediately preceding the space
block which was acquired.
o
11-39
11.4.5.1
r-------,
I
FWA
c'
I
I
I
FWA
BLOCK
A swap would occur if necessary to get core under the following conditions:
Request priority is greater than 3
Completion priority is greater than 2
Core is not already swapped
No unprotected I/O is going on
The minimum time between swaps is passed
c
Otherwise, the request for space waits on a queue.
The space request would only be rejected if it was already threaded.
involved in a previous operation.)
(i. e., still
11. 4. 5. 2 RE LEASE Request
After the program which requested the space is finished using it, it must release
the space. This is done with aRE LEA S E request. The format of the release
request is as follows:
RTJ-
15
($F4)
9 8
RC = 12
[I
FWA
The Macro call for RE LEASE is:
RE LEAS fwa, t, x
RC is request code 12; bit 8 is X bit.
11-40
1 0
o
o
11.4.5.2
~
bit, bit 0, should be 0 if it is desired for con t r 0 I to return to the program
(releasor) after the release is made. The It' bit is set to 1 if control should go to
the dis pat c her instead. The release request is the only one which allows this
choice of whether to come back to the program beneath the parameter string (as
all other requests do) or to go to the dispatcher if this was the last thing to do. The
It' bit will be used in coding mass memory programs.
FWA is the address of the core to be released. It must be the correct address of
the block or else no release will occur and there will be no error message. This
is to provide flexibility so that a program which was coded to run on mass memory
(in a later sec t ion) could be changed to be core resident without any changes or
reassembly of the program. When it became core resident and tried to release
its core, the core simpJy wouldn't be released.
The release request causes the space to be immediately given to any other space
requestor waiting on the space que u e before control returns to the releasor (or
dispatcher) •
An example of a space and release request could be:
f
1.
C)
2.
3.
COMPL
4.
5.
GOTSP
6.
7.
8.
9.
o
REL
RTJNUM
ADC
NUM
NUM
NUM
SQM
JMPSQP
JMP*
STQ*
r
RTJNUM
NUM
($F4)
$1445
COMPL
0
0
$1000
REJ
(ADISP)
GOTSP-*-l
NOSPAC
REL+2
($F4)
$1800
0
END
11-41
RP=4, CP=5
COMPLETION ADDRESS
ADDRESS COMES BACK HERE
$1000 WORDS WANTED
REQUEST REJECTED
WAIT FOR SPACE
GOT SOME SPACE
NO SPACE GOTTEN
ADDR. OF SPACE IN RELEASE
GO RELEASE SPACE
ADDRESS OF SPACE
11.4.5.2
1. Space request, priority 4 block, completion priority 5
2. Q is checked to see if request was not accepted.
3. Completion address is entered when sbPace ids gotten or if there is no space.
Q would be negative if no space was 0 taine •
4. If space was obtained, Q contains the address of the block. Here it is stored
in the release request. The address could also have been obtained later from
word 3 of the space parameter list.
5. Continue in program, using space.
6. Release the space; program is finished using it.
7. It' bit is not set, so control returns to the program after the release.
8. The address of the block is here; it was placed here after the space was obtained.
9. Continue in program.
C~,
Note that the above program is not runanywhere so it must be a core resident systemprogram. The completion address in the space request is not relative.
11.5 CODING MASS MEMORY PROGRAMS
All programs that are to be part of the System Library resident on mass memory must
conform to special rules. All of the rules are logical when the inter-relationship of the
program and the system is considered. The most important general consideration is to
be sure the program gets to do everything it set out to do before it disappears.
11. 5. 1 Modules in Library
The programs are stored on mass memory in a b sol uti zed form. (The System
Initializer put them there.) E a c h program - or a set of a program and its subroutines together - is called a module and has a name unique to the module. The
name must not appear as an entry point anywhere in the system. The name of
the 'module must be in the system directory. Here is an example of two modules
on mass memory:
MIPRO
Module
MIPRO
Program
{
(MIPRO is not an entry
point. )
'----------'
~
SCAN!
Program
SCAN
Module
SCAN2
Subroutine
SCAN3
Subroutine
c
11-42
11.5.1
MIPRO is the program which handles manual interrupts to the process; the module
is made up of the single program. SCAN is a module made up of a user process
program SCAN1 and its subroutines SCAN2 and SCAN3. These three programs go
together and will always be together as a g r 0 u p when the module is brought into
core for execution.
It is possible for a mass memory module to contain a DATA block within it, accessible only to the programs in that module. Any number of modules may contain
s epa rat e DATA blocks, but there may be only one in each module. Here is an
example of the SCAN module if it contained a DATA block:
SCAN3
SCAN2
SCAN1
DATA
The programs in any module may use system COMMON, which is in highest core.
11.5.2 Allocatable Core
o
The area of core that the mass memory programs run in is called all 0 cat a b 1 e
core. It is divided into priority blocks and the highest core area is available to
the larges t priority programs. A program to be run will be put in the smallest
space it will fit in which is available to that priority. Note that this means a program may run at different places in allocatable core at different times. There is
no dynamic relocation of the programs in allocatable core so as core spaces are
released, they are saved for subsequent programs to be run in.
Time 2
MIPRO
area of allocatable core
available to priority 4+
Time 1
o
MIPRO
In the above example MIPRO may run in different places depending on the space
available.
11-43
11.5.2
/-"
The systems analysts decide what priority area the program will run in (at system
initialization time); so a program calling a mass memory program has no control
over this.
(_,
11.5.3 Scheduling the Mass Memory Program
When it is desired to bring a mass memory program into core for execution, the
calling program schedules it in. An example would be:
MIPRO
EXT
r
SCHDLE
(MIPRO), 4,0
The system program MIPRO is scheduled in, to be executed at priority 4. As in
all requests for system programs, MIPRO must be named external and must be in
parentheses in the SCHDLE request.
The name MIPRO is the name of the mod u I e in the system directory. This request causes the system to obtain space in allocatable core to put the program in
(by a SPACE request), then to read it in (by a mass memory READ request), then
transfer control to it at its first core location.
The calling program does not have to worry about all this; it s imply knows that
scheduling it causes the program to come in to core and begin ex e cut ion. The
schedule request would be rejected if the program has already been scheduled (by
another caller) and is still in the process of being brought into core. It could not
be rejected from the scheduler s t a c k being full because the parameters are not
transferred to the stack.
C
11.5.4 Form of Mass Memory Programs
All mass memory programs have to be runanywhere, as has already been covered.
This is because they are stored on the s y s t e m library in absolute form and are
run at different places in allocatable core, not where they were absolutized.
Mass memory programs· do not normally have to be reentrant because a program
is usually brought into core each time it is called to be run. Minor modifications
to the system would be r e qui re d to allow mass memory program which is in
core to be r e en t ere d by a higher priority interrupting program; in that case it
would have to be reentrant.
a
c
11-44
11.5.4
o
Figure 27. Maps of Mass Memory Modules and Core Subroutines
Priority 4
o
SCAN3 subroutine needed by both
SCAN and ALARMS modules
One copy in each module.
SCAN4
...
~--+---- SCAN4
~--------------~
subroutine also needed by both
SCAN and ALARMS modules. It is core
resident and reentrant.
o
11-45
-'
C
11.5.5
-'
11.5.5 Externals to Mass Memory Programs
Externals in mass memory programs which reference locations w h i c h are core
resident must be absolute. Externals which reference addresses in other mass
memory programs (in the same module) must be relative. There must not be any
externals which reference addresses in any other mod u I e. This is because one
module does not know when another module is in core (or where it is) unless special
links are pro v ide d to handle it. This means that any subroutine which several
modules need would be either core resident or there would be a separate copy in
each mod u I e that needs it. Another solution would be to put the subroutine in a
separate module by itself and let routines needing it schedule it.
11.5.6 Space
Mass memory programs may reI e a s e their own space. This is a good feature
because it means that a program can schedule a mass memory program and then
can forget about it after the schedule request has been accepted and exit knowing
that the scheduled program will be executed at its priority. The mas s memory
program could pick up the address of where· it is, as its first instruction (i. e.),
and store it in the release request which would be the last instruction in the program.
1.
2.
SCNMSG
NAM
NUM
STA*
SCNMSG
$C8FE
REL+2
RTJNUM
NUM
END
($F4)
$1801
0
f.
REL
3.
LDA* *-1
RELEASE REQ., TBIT SET
ADDRESS TO BE RELEASED
core during execution:
FWA
FWA
C8FE
68xx
Space gotten in SPACE
request
54F4
1801
FWA
11-46
c
u
o
11.5.6
1.
Note that SCNMSG is not declared as an entry point since it is also the name
of the module.
2.
Remember that the first word preceding Space in allocatable core obtained by
a SPACE request contains the address of where that block of space is. The
NUM $C8FE is to fake out the assembler and cause it to make a code as the
first word of the program which will be a LDA* *-1. A LDA* *-1 instruction
would not have been assembled properly because it attempts to reference outside of the program area relatively. Also remember that the first word of a
mass memory module is executed so the NUM will not be treated as data. So,
the $C8FE gets the address of the space occupied by the program into A.
3.
Note that in the release request the 't' bit (bit 0 in the fir s t word of the parameter string) is set to indicate to the system not to return to the program
which made the release request after releasing the space. This bit would be
necessary for a mass memory program reI e a sin g its own core. It makes
sense because if control was returned to the program, there isn't any program
after the end. Or, even if there was some more program (such as a jump to
the dispatcher), it may not be executed. Rem e m be r that when a release
request is made, the space is allocated to any waiting r e que s t s before the
return to the requestor. Therefore, the space may have been given away and
may in fact contain another program or data; a return to the releasing program
would cause a mess because it may not be there any more.
If the mass memory module contains several subroutines, the NUM $C 8FE
would be the first instruction in the mod u I e and the RE LEASE would be the
last request made in the module.
Mass memory programs should com pIe t e their I/O and their calls to any
subroutines before ex it i n g. This is because when they release their space
and exit, any data b u f fer s or completion addresses in the program may be
lost as soon as the release request is made.
11.5.7 Mass Memory Problem, MMPG1V[
The following example program contains one err 0 r which could cause incorrect
results. It is very subtle and difficult to locate.
Assume that the assembly-language coding is runanywhere and correct. Look for
an error which can occur during execution. The program runs at priority 4. The
driver runs at priority 10. The completion routine runs at priority 6.
o
11-47
11.5.7
*
OOFA
ADISP
*
*
POOOO C8FE
MMPGM
P0003
P0004
P0005
P0006
P0007
P0008
P0009
POOOA
POOOB
POOOC
MSGBUF
*
4D4l
5353
204D
454D
4F52
5920
4558
4l4D
504C
4520
*
WRITE
POOOD
POOOE
POOOF
POOIO
POOll
P0012'
P0013
P0014
P0015
P0016
P0017
P0018
P0019
54F4
OD56
OOOF
0000
l8FC
OOOA
7FF4
0162
5800
7FFF
5400
7FFF
l4FA
NAM
ENT
EXT *
EXT
EXT
MMPGM
MMPGM
REQREJ, IOERR
CORSUB
SYSPGM
EQU
ADISP($FA)
NUM
STA*
JMP*
$C8FE
REL+2
WRITE
ALF
*, MASS MEMORY EXAMPLE*
MASS MEM PGM EXAMPLE
MM EXTS IN SAME MODULE RELATIVE
CORE RES SUB EXT ABSOLUTE
SYS DIR PGMS MUST BE EXTERNAL
FIRST INSTR OF MM PGM EXECUTABLE
PICK UP CORE ADDRESS OF MMPGM
FWRITE
$FC, WROTE-*+l, MSGBUF-*+5, 10, A, 5,6, I, X
SQP
RTJ
REQOK
REQREJ
PROT PGMS MUST CHECK REQ ACC
GO HANDLE REJ;REL ADDRESSING
RTJ+
CORSUB
ABS ADDRESSING TO CORE RES PGM
JMP-
SCHDLE
(ADISP)
(SySPGM), 4, 0
NO MORE TO DO
SCH SYS Dm PGM, CORE OR MM
SQP
RTJ
REL
IOERR
CHECK Q FOR 10 ERRORS
GO ANALYZE ERRORS
RELEAS
0, T, 0
o WILL BE REPLACED. W/ ADDRESS
END
MMPGM
c
X
X
X
X
REQOK
POOIA 54F4
POOIB 12(14
POOIC FFFF X
POOID 0162
POOlE 5800 X
POOIF 7FFF
*
WRaTE
*
REL
P0020 54F4
P002l 1801
P0022 0000
DO NOT RETURN TO PGM AFTER REL
*
I
REQOK
IOERR
OOFF
0017P
OOlFX
MMPGM
WROTE
REQREJ
OOOOP ADISP
OOIDP REL
0016X
OOFA
0020P
11... 48
MSGBUF
SYSPGM
0003P
OOlCX
WRITE
CORSUB
OOODP
0018X
11.5.7
The following is a description of the concepts presented in MMPGM. Note that an
entry point MMPGM is declared; therefore, the name of the module must be something other than MMPGM. There are two relative externals, REQREJ and IOERR,
which must be subroutines in this same module. There is one absolute external,
CORSUB, which must be a core resident subroutine.
POOOO -
picks up the address of the cor e block MMPGM is 10 cat e d in, then
stores it in the release request.
POOOD -
initiates an FWRITE from MSGBUF. RP=5 and CP=6. The X bit is
set so WROTE-*+l and MSGBUF"'*+5 calculate the correct distances
from POQOE to the completion address WROTE and the buffer MSGBUF
and places them in-POOOFanci-P0013~
OOOE
+OOOF
001D
o
WROTE
OOOE
+7FF4
8002
1
0003
MSGBUF
P0014 -
checks to see if the request was accepted.
P0017 -
jumps to execute CORSUB at running priority 4.
P0019 -
schedules a program in the system directory, SYSPGM, to be executed
at priority 4 aft e r completion of MMPGM. Note that SYSPGM must
be named external and that the ( ) causes bit 15 to be set in P001B. The
program should have checked Q to see if the r e que s t was accepted.
I
P001C -
the pro g ram has now run out of things to do, so it goes to the dispatcher to await the write completion.
P001D -
after the write, the completion routine (running at priority 6) checks
for errors.
P0020 -
the completion routine then releases cor e. The T bit is set so that
after core is released, control will go to the dis pat c her instead of
returning to the program.
11.6 EXTERNAL REFERENCES AND LINKAGE, SUMMARY
It is desirable at this point to review the rules regarding externals among the various
types of system programs.
o
Core resident programs can make references to other core resident programs e it her
relatively or a b sol ute I y. Since there is a choice, it is probably best to use absolute
mode. Then if this program is ever made mass memory res ide nt, its references to
low core programs will be correct.
11-49
11.6
Core resident programs would not make any references to mass memory programs by
way of externals. They would schedule the mass memory programs (which would be in
the system directory).
Mass memory programs are grouped together in modules. A module may be composed
of a single program or several pro g ram s. Externals which reference core resident
programs must be a b sol ute. Externals which reference other programs in the same
module must be relative. Mass memory programs may not reference any programs in
another module by externals (they can schedule them in).
A mod u 1 e has a name unique to it which is not an entry point anywhere in the system.
This is the name in the system directory. Cor e resident programs can also be in the
directory but only a few us u all yare. Any program which may at some later date be
changed from cor e resident to mass memory resident (or vice versa) should be in the
directory so that it can be scheduled by the system directory schedule r e que s t form.
c
c
11-50
11.6
'-"
C
Figure 28. 1700 Core Map
"
I
system common
Common
Loader
Unprotected
Subprogram B
Subprogram A
Program Library
Data Block
Job Processor
1----------
o
Request Processor
--------System and Process
Programs
- do not have to be
run anywhere
(* L) ----------- -
- run anywhere
;---------- Communications
Region
-
- mass memory externals
relative
0000~'--- _ _ _ _ _ _ _ _ _ _
- cannot reference any
locations in a mass
memory module by
externals
--1
- locore externals abs olute
- cannot reference any locations in
other mas s memory modules by
way of externals
o
Each" group" of mass memory programs loaded and linked together by one *YM control
statement is called a mass memory module and has a name unique to the module.
11-51
c
(j
CHAPTER XII
o
PERIPHERAL PROGRAMMING - I
c
('
\ ......
CHAPTER XII - Peripheral Programming I
Cj
0
12.1
12.1.1
12.1.2
12.1.3
12.2
12.2.1
12.2.2
12.2.3
12.3
12.3.1
12.3.2
12.3.3
12.4
12.4.1
12.4.2
12.4.3
12.5
12.5.1
12.5.2
12.5.3
12.6
12.6.1
12.6.2
12.6.3
12.6.4
12.7
12.7.1
12.7.1.1
12.7.1.2
12.7.1.3
12.7.1.4
12.7.1.5
12.7.1.6
12.7.2
12.7.2.1
12.7.2.2
12.7.3
12.7.3.1
12.7.4
TOPIC
PAGE
1721 Paper Tape Reader
PTR Functions
PTR Status
PTR Example Program
1723 Paper Tape Punch
PTP Functions
PTP Status
PTP Example Program
1711 Teletypewriter
TTY Functions
TTY Status
TTY Example Program
1713 Teletypewriter
1713 Functions
1713 Status
1713 Example Program
1726/405 Card Reader
CR Functions
CR Status
CR Example Program
1742 Line Printer
LP Functions
LP Status
Programming the Printer
Example, 1742 Line Printer
1738/853 Disk
Disk Functions
Director Bits 001 - Director Functions
Director Bits 010 - Sector Record Address
Director Bits 011 - WRITE
Director Bits 100 - READ
Director Bits 101 - COMPARE
Other Director Functions
Disk Status
Director Status
Address Register Status
Disk Sample Programs
Addresses Tag Program
Problem
12-1
12-1
12-3
12-5
12-6
12-6
12-7
12-9
12-11
12-11
12-12
12-15
12-17
12-18
12-19
12-20
12-23
12-23
12-25
12-28
12-29
12-29
12-31
12-31
12-32
12-36
12-40
12-40
12-41
12-41
12-42
12-42
12-42
12-42
12-42
12-43
12-44
12-47
12-48
12.8
12.8.1
12.8.2
12.8.2.1
12.8.2.2
12.8.3
12.8.4
12.9
12.9.1
12.9.2
12.9.2.1
12.9.2.2
12.9.3
12.9.3.1
12.9.3.2
12.9.4
12.9.4.1
12.9.4.2
12.10
12.11
12.11.1
12.11.2
12.11.3
12.11.4
12.11.5
1751 Drum Controller
Drum Functions
Drum Status
Director Status I
Director Status II
Programming the Drum
Drum Example Program
1731/601 Magnetic Tape
D = 00 MT Data
M T Functions
D = 01 Control Function
D = 10 Unit Select Function
MT Status
D = 01 Status I
D = 10 status II
MT Example Programs
MT Example 1
MT Example 2 - With Error Checks
1732/608-609 Magnetic Tape
1706 Buffer Data Channel
1706 Functions
Programming the Peripheral Through the 1706
1706 Status
Summary of 1706
1706 Example Program
12-48
12-50
12-52
12-52
12-53
12-53
12-55
12-57
·12-57
12-60
12-60
12-61
12-61
12-61
12-62
12-62
12-62
12-63
12-66
12-66
12-67
12-68
12-69
12-70
12-71
C~-~
('
'-.. ..
'
12.1
12.1 1721 PAPER TAPE READER
The paper tape reader transcribes data to the lower 8 bits of the A Register at a rate
of 350 !eight-bit characters per second. The time between frames is 2. 857 milliseconds.
These times qualify the 1721 to be grouped with the low speed package; equipment number 1, station number 2.
The Q Register will be in the following format when referencing the paper tape reader •
Q
..
15 14 13 12 11 10
9
8
6
5
4
3
2
1
I?}~t~tj~j~l{r{~l~}}j~~
7
0
0
1\ 0
1
0
0
o
0\
0
J~
,
Equipment 1
Station 2
o
~
Director
O-+- Data
I-+- Status/Function
The Q Register will contain either $OOAO or $OOAl.
LDQ
LDQ
=N$OOAO
=N$OOAI
DATA
FUNCTION/STATUS
12.1.1 PTR Functions
The D portion dictates the. operation to be performed in conjunction with the INP
and OUT instructions.
D = 1 FUNCTION (OUT)
The programmer may issue the functions together with the exception of the clear
controller and clear interrupt functions which must be issued separately.
A
1
0
TI
r
11'T'"T""T""T""')){T'"T"'T"'T"T'"tWm~fWm"""""""'ffW~(mW~mm?~mtm-:-:-:-;-:-(?m-:-:-:-:-:-)~(~~j~f{~jf~\-:-:-:7':'""n{(~~ffj:-:-:-:-:-:~{fj~~{~
+Clear Controller
Clear Interrupts
LDQ
ENA
OUT
=N$00A1
PTR for FUNC
CLR INT, CLR CONT
3
-1
12-1
12.1.1
The remaining functions may be issued jointly.
43210
A
Stop Motion
t
l
1
bata Interrupt Request
Select Interrupt on Alarm
Start Motion
Data Interrupt Bit 2 allows the programmer to instruct the 1721 to interrupt the 1700 when the
holding register on the 1721 contains a frame of data ready for transfer.
Alarm InterruptBit 4 permits the paper tape reader to interrupt the computer if one of the following
conditions arise:
a) Paper Motion failure
b) Lost data
c) Power off
Start Motion Bit 5 starts the pap e r tape reader moving tape through the read .station. Paper
will continue to be moved through the read station until the motion is stopped or
the reader runs out of paper.
Stop Motion Bit 6 stops the movement of the paper through the read station. The brakes on the
1721 assure stopping before reaching the next frame.
LDQ
LDA
NOP
OUT
=N$00A1
=NFUNC
PTR for FUNC
PLACE FUNCTION IN A
-1
INITIATE DESmED OPERATIONS
The logic has been set up, the ref 0 r e, the programmer needs only to bring the
data into the computer.
D
=
0
DATA
LDQ
NOP
INF
=N$OOAO
PTRFORDATA
-1
DA TA IN LOW 8 BITS OF A
12-2
o
12.1.2
12.1.2 PTR status
The programmer may monitor the operations of the paper tape reader by taking
status.
D = 1
STATUS (INP)
LDQ
=N$00A1
PTR FOR STATUS
-1
STATUS IN A
Nap
INP
The status bits are in the A Register.
15
A
11 10
987
6
I I I
poweron+W'
Paper Motion Failure ~
Existence Code
Protected
Lost Data ----,-------'
Alarm - - - - - - - - - '
o
5
4
3
2
1
0
I I I I
11
+I Ready
•
Busy
Interrupt
Data
Ready (Bit 0): Power is on and paper tape has been loaded into the reader.,
The preparations have been made known to the logic by pressing the READY switch
on the paper tape reader console. The reader becomes Not Ready if a paper motion
failure occurs or if the power is turned off.
Busy (BJtJ): The paper tape reader i~_ Busy if a Start Motion command has
been iss u e d and no Stop Motion command has followed. Motion stops on a Stop
Motion command, a paper motion failure, or if the power is turned off.
Interrupt (Bit 2): An interrupt condition exists. Other s tat us bits must be examined to determine the condition causing this interrupt.
Data (Bit 3): The Data Hold register in the paper tape rea de r contains an 8-bit
frame of data which is ready for transfer to the computer. Start Motion must be
set to receive this status. The status drops when the Data Hold register is emptied -by transfer to the computer.
Alarm (Bit 5): At least one of the follow in g conditions exists in the paper tape
reader: (1) paper motion failure (bit A9), (2) lost data (bitA6), or (3) power off
(bit A10 is '0').
o
Lost Data (Bit 6): When in interrupt on Data mode, paper motion continues after
the Data Hold register is full. If .the data is not transferred to the computer before
the next frame appears, a lost data status occurs to show aframe has been passed.
The time between frames is 2.857 milliseconds. The status drops when a clear
controller command is sent. Lost data stops tape motion.
12-3
12.1.2
Protected (Bit 7): The PROGRAM PROTEC T s wit chis on. This switch on the
paper tape reader works in conjunction with the PROGRAM PROTECT switch on
the computer. If the switch on the computer is off and the PROGRAM PROTECT
switch of the peripheral device is on, no ~ction is taken but the status bit is set to
indicate the switch is on. If the switch on the computer is set, all rules of program protection apply. The paper tape reader in this condition only accepts protected instructions.
Existence Code (Bit 8): The paper tape reader is attached. If the bit is a '1', the
reader is missing from the particular computer system.
Paper Motion Failure (Bit 9): No change in the feed hole circuit has occurred
for 40 milliseconds while trying to read. The paper motion fa i I u r e causes the
reader to become Not Ready; it can only be made ready by pus h in g the READY
switch or by a Clear Controller command. It is considered an illegal operation to
send any other function code to the rea d e r or a read command until the READY
switch has been pressed or a Clear Controller has been issued.
Power __9n (Bit 10): :power to the reader is on.
If this bit is a '0', power is off.
c
12-4
12.1.3
12.1.3
o
Example
The following is a test program for the 1721 paper tape reader. It inputs data,
beginning with the first nonzero frame, until a zero word is encountered, atwhich
time data input stops. The data is stored in the consecutive locations beginning
after the end of the program.
The controller should be cleared from the console before the program begins, as
the clear controller function cannot be sent with the start motion function at line 4.
The stop switch should be set so the program will stop after reading the tape.
After it stops, if the switch is set to RUN, the tape which was just read will execute (assuming it contained an absolutized program).
1721 PTR - AUG '68
USDA
*CLEAR CONTROLLER FROM CONSOLE - CANNOT START MOTION & CLEAR CONTROLLER IN SAME FUNCTION
The following is a test routine for the 1711 teletype. It outputs an 11-word message from the buffer GET. The controller is cleared in a separate function before
a new function is selected. Write mode is s e 1 e c ted because Read mode is in
effect after the clear controller function.
0
0001
~IAM
800TSTRA~
0002
00 0 3
ENT
LOn
START
-f\l$A1
ENA
OUT
$20
-1
START
INO
-1
SET TO READ
-1
INPUT LEADER
0 00 4
OP05
00 0 6
0007
000 8
0009
00]0
0011
OOl~
0013
0014
0015
OOlg
0017
00·18
0019
00 2 0
0021
0022
~oOoo
POOOI
~?OO02
POO03
120004
POOOS
~n006
POOO7
12000 8
POOO9
PODOA
POOOB
poooe
POOOD
poooe;
POOOF
1200]0
POOll
120012
POO13
EXIT
o
BOOTST
Eono
OOAI
OA?O
03FE
oOFE
OBOO
!l2FE
0113
18FD
0800
START
LOAD]
bOl\02
NOP
H.IP
SAN
'MP*
NOP
PTB DJR ETINe
MOTION
3
LOADI
HI~
-}
INpUT FR I\ME
OFC8
ALS
B
SHIFT TO PACK
o~Oo
~IQI2
02FE
INP
STA*
SAZ
RAO*
JMP*
ADC
NUM
-1
( A(;)ORES)
EXIT-*-l
ADDRES
LOAD2
*+2
$0
START
INPUT NEXT FRAME
GO GET NEXT WORD
0006P 'OAD2
OOOAP ADORES
O~Fe;
~CO(I
0103
DB 02
18FB
00 1 4
0000
~
ADORES
EXIT
E~IO
DOFF START
00131-'
1725
oooO~
LOAD]
where bootstrap loaded
12-5
STORE WOOD
EXIT ON ZERO WORD
UPDf~TE
hDDRESS
LOI\D I\T POO14
ZERO FOR SLS
0012P
12.2
('
,--".
12.2 1723 PAPER TAPE PUNCH
The punch is grouped with Control Data I s low speed package. The punch is a character
device. It accepts the lower 8 bits of the A Register as data. These 8 bits may be ASCII
codes or binary.
The punch is addressed as Equipment 1, Station 4.
15
Q
11 10
0
~~III{IIIIIII~~rl
9
8
0
0
7
1
I
Equipment 1
LDQ
LDQ
6
1
5
0
3
4
0
2
1
0
Director
O-+Data
1-. Function/Status
Station 4
PTP, DATA
PTP, FUNC/STATUS
=N$OOCO
=N$00C1
12.2. 1 PTP Functions
The programmer may direct the operations and interrupt selections of the Punch
via the Director function. The clear interrupt and clear controller function may
be issued together but should not be issued with the other functions.
15
A
fr}\~(:~:~:tt~:~:~:~:~:~:tt~:~:~:~:~:~:~:~:~:~:~:~:~:t~:~:~:~:t~{{}{}{{r{r~IIrII
1
t
0
I
(~
I
~LR Controller
CLRINT
LDQ
ENA
OUT
PTP, FUNG
=N$OOCI
3
-1
The remaining functions may be issued together.
6
15
5
I I
4
t
3
~tt~1
2
1
O.
tttrt~J
bata Interrupt
Alarm Interrupt
Start Motion
1
LDQ
LDA
OUT
=N$OOCI
=NFUNC
-1
12-6
PTP, FUNC
FUNCTIONS
INITIATE FUNCTIONS
., .... -"
o
12.2.2
12.2.2 PTP Status
The programmer may status the Paper Tape Punch by setting the Director bit to
a '1' and is suing an INP instruction.
LDQ
=N$00C1
PTP, STATUS
NOP
INP
-1
STATUS TO A
15
A
12 11 10
~:~:~:~:~:~:~:~:~:~:~:~:~:~:~:~:~:~:~:~:~:I
I
k:.:.:-:-:-:.:.:.:.:-:.:.:.:-:.:.:.:.:.:.
Tape Supply Low
~ t
9
I
Power On ~
Tape Break
Existence Code
Protected
Alarm
o
8
,
6
7
1'.........,
. ....
5
4
3
2
1
r········)
. ....
J1
0
, I
[1
i
R~ady
Busy
Interrupt
Data
Ready (Bit 0): The paper tape punch is Ready when its power is on, tape has been
loaded, and the READY switch on the s tat ion console has been pressed. The
punch becomes NOT READY if tape break occurs or if power is turned off.
Busy (Bit 1): The pun chis Busy if a Start Motion is in effect or until the punch
has finished processing the data in the Data Hold register.
Interrupt (Bit 2): An interrupt condition exists. 0 the r bits can be monitored to
determine if one or more of the selected interrupts has occurred.
Data (Bit 3): The 8 bits of d a t a in the Data Hold register of the punch have been
pun c he d and the new data may be received from the computer. The data status
drops when a transfer from the computer is made.
Alarm (Bit 5): This status indicates that one of the following conditions has arisen:
a.
b.
c.
Tape Break
Power off
Tape low
The status drops when the condition is corrected.
Protected (Bit 7): The PROGRAM PROTECT switch on the peripheral equipment
is set. The status bit only indicates that the switch is set; it does not show if a
program protect violation occurred. If the PROGRAM PROTEC T switch on the
computer is on, the punch does not accept commands which are not protected. All
rules of program protection apply.
C)
12-7
12.2.2
Existence Code (Bit 8): A zero setting acknowledges that the paper tape punch is
attached. If the bit is a '1', the pun chis missing from the particular computer
system.
Tape Break (Bit 9): The tape break status bit is set if the punch supply tape has
broken or run out and approximately 2 inches of tape remain. '- If the tape supply
low bit is ignored, it results eventually in the Tape Break condition as the supply
of tape is exhausted. The Tape Break condition causes the punch to become Not
Ready. It can onlybe made Ready by loading paper tape and pressing the READY
switch. However, it is still able to receive the Clear Controller and Clear Interrupts function codes so that the Interrupt signal (if Interrupt on Alarm was selected)
can be dropped. It is considered an illegal operation to send any 0 the r function
code or a Write signal until the READY switch has been pressed.
Power On (Bit 10): The power to the punch is on. If this bit is not a '1', the
power is off and an Alarm interrupt may be generated.
Tape Supply Low (Bit 11): The available supply of tape remaining to be punched is
limited.
c
12-8
C)
12.2.3
12.2.3 PTP Example Program
0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013
0
0014
0015
0016
0017
0018
0019
0020
0021
0022
0023
0024
0025
0026
0027
0028
0029
0030
0031
0032
0033
0034
0035
0036
0037
0038
0039
0040
0041
0042
POOOO 0019
001A P
OOEA
00C1
POO19
POO18
P001C
P001D
POOlE
P001F
P0020
P0021
POO22
P0023
P0024
P0025
P0026
P0027
P0028
P0029
P002A
P002B
P002C
P002D
P002E
P002F
P0030
P0031
P0032
P0033
P0034
P0035
P0036
P0037
P0038
P0039
P003A
P003B
P003C
P003D
P003E
P003F
P0040
P0041
P0042
0002
0001
COOO
0000
9000
001A
0113
1400
7FFF
OBOO
68F5
0864
68F2
COOO
7FCD
60FF
EOOO
00C1
OA01
03FE
OA20
03FE
ODFE
0844
03FE
DOFF
01A1
18FC
C8E3
OFC8
OBOO
03FE
OFC8
OBOO
03FE
0844
60FF
C500
0000
88D9
68D8
START
NAM
ENT
BZS
EQU
EQU
EQU
EXT
BSS
BZS
LDA
PUNCH
START
AA(25) •
SUB
=XBB
LWA
SAN
JMP+
OK-*-l
ERROR
IF UNEQUAL, AL
CONTAINS SIZE 0
NOP
STA*
TCA
STA*
LDA
TEMP+1
A
TEMP
=X$7FFF-50
BLOCK SIZE COMPL
COMPLEMENT BLOCK SIZE
BLOCK SIZE A
STALnQ_
I
=XPUNCH
I EQUALS COUNTER FOR LEADER
PREPARE PUNCH TO RECEIV
ENA
OUT
ENA
OUT
INQ
CLR
OUT
RAOSOY
JMP*
LDA*
ALS
NOP
OUT
ALS
NOP
OUT
CLR
STALDA+
+1
-1
$20
-1
-1
A
-1
I
NEXT-*-l
LOOP1
TEMP+1
8
CLEAR CQNTROLLER
JUMP_ ON SELF UNTIL :OUT
UPDATE LEADER COUNT
WHEN 1=8000, 50 BLANKS
KEEP OUTPUTTING BLANK L
COMPLEMENT OF BLOCK SIZEHIGH ORDER BITS PUNCHED FIRST
-1
8
LOW ORDER BITS SECOND
BB(AA+25)~
ADISP (SF A)
PUNCH($00C1)
ERROR,DISP
TEMP(2)
CKS(l)
=XAA
SET BUFFER TO 1 tg
FROM CONSOLE
NOTE THAT 26 WORDS WILL
BE OUTPUT, NOT 25
RESERVED FOR BLOCK SIZE
FWA
P
P
X
X
OK
LOOP1
NEXT
LOOP2
PREPARE PUNCH FOR DATA
-1
A
I
AA,I
SIZE OF BLOCK NOW ON TAPE
CKS
CKS
CHECKSUM
ZERO OUT THE INDEX I
PLACE FIRST WORD OF DATA IN
P
[ ADD*
STA*
IS FINE
BLOCK
J
0
12-9
12.2.3'
0043
0044
0045
0046
0047
0048
0049
0050
0051
0052
0053
0054
0055
0056
0057
0058
0059
0060
0061
0062
0063
0064
0065
0066
0067
0068
0069
0070
0071
0072
0073
0074
0075
0076
P0043
P0044
P0045
P0046
P0047
P0048
P0049
C500
0000 P
OFC8
OBOO
03FE
OFC8
0800
P004A
P004B
P004C
P004D
P004E
P004F
P0050
P0051
P0052
P0053
P0054
P0055
P0056
P0057
P0058
P0059
P005A
P005B
P005C
P005D
P005E
P005F
P0060
P0061
P0062
P0063
P0064
P0065
P0066
03FE
DOFF
COFF
98CB
0101
18EF
C8CA
OFC8
OBOO
03FE
OFC8
OBOO
03FE
COOO
7FCD
60FF
0844
68BF
03FE
DOFF
OlAl
l8FC
ODOI
OAOI
03FE
COOO
C040
03FE
14EA
OOFF
00C1
0036P
7FFFX
I
PUNCH
NEXT
DISP
LDA+
ORIGINAL DATA IN A
-1
8
OUTPUT FIRST CH.
-1
I
I
TEMP
SUM-*-l
LOOP2
CKS
8
OUTPUT SECOND CH.
UPDATE INDEX
PLACE UPDATE IN A
-1
8
FIRST CH. OUT
-1
=X$7FFF-50
CHECKSUM ON PAPER TAPE
PREPARE FOR END LEAD
STACLR
STA*
OUT
RAOSOY
JMP*
INQ
ENA
OUT
LDA
I
A
CKS
-1
I
DONE-*-l
LOOP3
1
1
-1
=N$40
INITIALIZE INDEX I
OUT
JMPEND
-1
(ADISP)
START
ALS 8
NOP
OUT
ALS
NOP
Could
compute
OUT
CKSUM ---. RAOhere
LDASUB*
SAZ
JMP*
SUM
LDA*
ALS
NOP
OUT
ALS
NOP
sov 0 -----.OUT
LDA
LOOP3
DONE
START
TEMP
LOOP2
ERROR
C
AA,I
001CP
0019P
003FP
.0022X
AA
CKS
SUM
OOOOP BB
001BP OK
0050P LOOP3
BLOCK IS PUNCHED
OUTPUT BLANK LEADER
UPDATE INDEX
IF OVERFLOW FINISHED
PREPARE PTP FOR FUNCTION
CLEAR CONTROLLER
STOP MOTION
OUTPUT FUNCTION
OOlAP ADISP
0024P LOOPI
005CP DONE
OOEA
0032P
0060P
~-:~i~J!llll!!!!!=!1111!!II![ ~
. I'
CHECKSUM ---.J
t
J~
DATA: 26 vWORDS
SUM OF ALL DATA WORDS, DISREGARDING OVERFLOW
12-10
LWORD
COUNT
C'
o
12.3
12.3 1711 TELETYPEWRITER
The 1711 Teletype may send and receive information.
from the 1711 takes 100 milliseconds.
The data transmission to or
The Teletype is one of three devices composing the low speed package which is always
Equipment Number 1. All interrupts generated by the teletype shall be processed via
line 1 interrupts.
The Q Register will contain $0091or $0090 when communicating with the teletype. Break
this word down into Binary, and we have Equipment 1, Station 1.
W
E
············l··· .'..,.....J". '1··· ·1 0
Q:::::::::::::::::::::::::::::::::::::::::::::::::
I":.:.:.:.:.:_:.:-:.:":"::.:.:.:"_:.:.:.:.:.:.:.:.:.:.
,0
-
I0 I
.
.
'-----v..-----'
'-v-'
, '---v------"
Equipment 1
Station 1
Data 0
Function or Status 1
The Dportion denotes the transfer of data when set to zero. All data transmissions will
be to and from the lower 8 bits of the A Register. The characters will be transferred
in ASC II codes, one character at a time. The directional flow of the data will be governed
by the INP and OUT instructions.
LDQ
NOP
INP
0
LDQ
LDA
NOP
OUT
=N$0090
TTY FOR DATA
-1
READ DATA INTO A
=N$0090
BUF
TTY FOR DATA
PUT DATA IN A
-1
WRITE DATA ON TTY
12.3.1 TTY Functions
The D portion indicates a function or a status when set to a 1. A function is indicated by issuing an OUT instruction with A preset to the function.
LDQ
LDA
NOP
OUT
A
=N$0091
FUNC
TTY FOR FUNC OR STATUS
PLACE FUNCTION IN A
-1
OUTPUT A FUNCTION
I:~: ~:~:~:~:~: ~:~ ~ ~~ ~ ~ ~ ~ ~ ~ ~ ~: ~: ~:~: ~:~:~:~: ~: ~: ~:~: ~: ~: ~:~: ~:~: ~:~: ~: ~:~:~:~:~:~:~:~:~:~:~:~:~: ~:~:~:~:~:~:~:~:~:~: ~:~: ~:~:~:~:~:~:~: ~:~:~:~:~:~:~ ~ ~ ~ ~ ~:~
1
0
,
f
C·LR CONT
CLRINT
The clear controller and clear in t err u p t functions must be sent to the teletype
prior to selecting other functions.
12-11
12.3.1
15
A
10
!~??~~?(}r(}r~)f\{fJ
9
8
i
7
5
r~~tttt~~~t~J
4
3
2
1
tIl
f'
I
0
Select Read Mode t
·Clear Controller
Select Write Mode
~
Clear Interrupts
Select Interrupt on Alarm
Data Interrupt Request
Select Interrupts on End of Transmission
(EOT Key)
The 1711 provides the capability of selecting t h r e e interrupts; DATA, ALARM,
and END OF TRANSMISSION (EOT). The DATA interrupt will occur when the
teletype is pre par e d to send or receive d a t a. The ALARM interrupt will be
generated if data has been lost or if the teletype goes from READY to NOT READY.
The END OF TRANSMISSION interrupt will 0 c cur whenever the EOT key on the
console of the teletype has been pressed. None of these conditions will generate
an interrupt unless the programmer has selected them.
The motor will be started on the 1711 by an output of a dummy character - to the
teletype.
12. 3. 2 TTY status
Status will be sent to the A Register from the tel e t y p e with an INP instruction.
LDQ
NOP
INP
=N$0091
TTY FOR STATUS OR FUNC
-1
INPUT STATUS TO A
The A Register will contain the status and the pro g ram mer may examine it to
determine the next procedure he wishes to follow.
15
12 11 10
t
9
t.J
Manual Interrupt
Motor On~
Read Mode
876
J
Lost Data
Alarm
5
4
3
I
210
t I
I
teady
Busy
Interrupt
Data
End of Transmission
11
I
Ready (AO is 1): If this bit is set in the A Register, the Power switch on the console of the teletypewriter is in the ON-LINE position and the motor is on.
Busy (AI is 1): If this bit is set, one or more of the following conditions ex i s t:
a) The controller is in Read mode and is in the process of receiving a character from the teletypewriter or the Data Hold register contains data for
transfer to the computer. The Busy status drops upon completion of the
12-12
C'
/
12.3.2
transfer to the computer if data has not been lost. If data has been lost,
the con t roll e r requires 200 milliseconds to stop the teletypewriter and
remains Busy all this time.
b) Write mode and the Data Hold register contains data and is in the process
of transferring it to the teletypewriter. Busy drops upon completion of the
transfer.
c) Either mode and the controller is in the process of starting the motor in
the teletypewriter. In Write mode output of a character starts the motor
and this character is lost. In Read mode, the BREAK key must be pressed
to s tart the motor.
Interrupt (A2 is 1): An interrupt condition exists.
to determine the condition caus ing this interrupt.
Other bits must be monitored
Data (A3 is 1): An interrupt is generated and this status bit is a 1 under the following conditions:
a) Read mode and the Data Hold reg i s t e r contains data for transfer to the
computer. The status drops upon completion of a Read.
o
b) Write mode and the controller is ready to accept another Write from the
computer. The status drops upon completion of the Write.
End of Transmission (A4 is 1): The Data Hold register contains the End of Transmission code. This code is generated by pressing the EaT key on the keyboard
of the teletypewriter. The end of transmission status drops upon the completion
of the next Write or Read.
Alarm (A5 is 1): The teletypewriter is not in a Ready state or has lost data.
Lost Data (A6 is 1): The controller was not s e r vic e d by the computer before a
new character was sent by the teletypewriter. The keyboard and tape transmitter
are locked out. The status bit indicates a Lost Data condition, and a Busy status
indicates that the process of stopping the teletypewriter is in progress. Data held
in the Data Hold register is not disturbed, but the incoming data is ignored. The
lost data status can be cleared by a Clear Controller or a Select Write Mode command. These two functions are rejected while the controller is stopping the teletypewriter. The Select Write mode command must be preceded by a Read operation
to clear the Data Hold register. Mter the teletypewriter has stopped, the computer
may do an Output operation to notify the controller of the Error condition.
Read Mode (A9 is 1): If this bit is a 1, the controller is conditioned for an Input
operation from the teletypewriter. Read mode is automatically in effect after a
clear controller function has been issued.
o
12-13
12.3.2
Motor On (A10 is 1): The motor of the teletypewriter is on. The presence of this
bit indicates that the teletypewriter motor is on and up to speed.
a) Write mode: Motor starts with the output of a c h a r act e r. Two-second
delay occurs between output of the character and this status bit being set
to allow the motor to get up to speed.
b) Read mode: Press the BREAK key to turn on the motor. Tw 0 - sec 0 n d
delay. also occurs between the action of the BREAK key and the status bit
being set to allow the motor to get up to speed.
Manual Interrupt (All is 1): The manual interrupt button on the teletype has been
pressed.
Example:
The following is a test routine for the 1711 teletype. It outputs an II-word message from the buffer GET. The con t roll e r is cleared in a separate function
before a new function is selected. Write mode is selected because Read mode
is in effect after the clear controller function.
c.
12-14
12.3.3
0
12.3.3 TTY Example Program
QQQI
0002 POOOO
POOOl
POOO2
POOO]
POOO4
504C
1, 5 /,1
5345
GET
~Ll\M
+¥~~
ALF
11,PLEASE INPUT YOUR CODE
Olll
~
\
Message
20/,9
4f..50
POOO!:) 5b54
POOO6 20S9
POQ07 L+F!:J5
POOO8
POQ09
~)220
f. 3 * F
1
POOOA 4445
0
0003 POQ08 08440004 pooac 60FF
0005 POOOD EOOO
POOOE 0091
0006 PQQOF ell, Q]
0007 POOIO 03FE
0008 POOll GOOD
POO12 OlUO
POOl)
OdOO
0009
0010 POO14 03FE
0011 POO15 QDFE
0012 POO16 OHOO
0013 PO 01 -, 03FE
0014 POOI8 C9E.7
0015 POO19 orcs
OOIA POOIA 0800
0 01 7 DOO]R 03F E
0018 POOIC OFCB
0019 POOl!) (InDO
0020 POOlE 03FE
LOOP
A
I
-f\J$OO91
TTY DIR FUMe
$3
cr,B CONTB
-1
-f\J$100
'iVRITE MODE
NOP
OUT
INC)
NOP
-1
-1
WRITE DJJ:TJ.c FUNC
OIIT
-1
LDA{~
GET,!
l\LS
8
aliT
-1
ALS
8
"lOP
OUT
-1
T
0022 POO20 COFF
LOA-
I
09F4
INA
-] 1
0024 POO22 DI01
SAZ
00?5
f:>()()C1
I
OOFF
GET
DONE-{~-l
lOOP
0
IMPi}
ldF4
0026 POO24 0000
0027
SEND DUMMY CHAR
OUTPUT DATA
NOP
RAO-
0023 POO?]
DONE
& TNT
EN"
OUT
bOA
POOlE DOFF
002 J
C)
CLR
STAbDO
0
E~ID
OOOOP LOOP
OOlBP
12-15
DON~
002 1, P
12.3.3
Typewriter Printout
PP
*
MI
*K,I5
J
*p
J
*ASSEM
L,03 FAILED 01
ACTION
CU
L, 03 FAILED 01
ACTION
CU
L,03 FAILED 01
ACTION
CU
J
*p
J
Output from program
*L, 8
~LEASE
INPUT YOUR CODE /
USDA - August 1968
12-16
12.4
12.4 1713 TELETYPEWRITER
The 1713 is com po sed of a keyboard, printer, paper tape reader, and a paper tape
punch, each a c c e s sib 1 e by the computer. The 1713 is grouped with the low speed
package, equipment number 1, station number 1. The Q Register will be in the following
format when referencing the 1713.
Q
15
0
0
0
11 10
0 01 0
9
0
7 6
11 0
8
0
4
1
5
0
'---v----'
v
Equipment 1
Station 1
3
0
2
0
1 0
0 1-
+
o = Data
1 = Function/Status
LDQ
LDQ
=N$0090
=N$0091
SEL TTY, DATA
SEL TTY, STATUS OR FUNCTION
The programmer has the option of selecting the reader, punch, printer or keyboard. All
four units may be used together or s epa rat ely. The selection is made by setting an
appropriate bit in the function word.
o
15 14 13 12 11 10
A
o
l}}d
I I I I I
11
i
telect Keyboard Mode
Select Keyboard- Tape Mode
Select Tape Mode
Select Tape-To-Tape Send Mode
Select Tape-To-Tape Receive Mode
Bit 14 - . Connects the punch to the controller leaving the keyboard and reader inactive.
Bit 13 ----. Connects the reader only to the controller.
Bit 12 - . Connects the page printer and r e ade r to the controller. The keyboard and
punch are connected together as an off-line tape preparation de vic e. Read
operations transfer information from the paper tape reader to the controller
and the page printer. Write 0 per a t ion s transfer information to the page
printer. Simultaneously, a new tape can be prepared from keyboard entries.
Bit 11----. Connects the keyboard, page printer, reader and punch to the controller. A
character struck on the keyboard or sent from the reader is printed, punched
and transmitted. A character sent to the 1713 is printed and punched.
Bit 10 ----. Connects the keyboard and printer to the controller which act as a send/receive
page printer. The paper tape units are inactive in this mode.
C)
12-17
12.4
The 1713 accepts the lower eight bits of the A Register as data and sends eight bits of
data to the A Register. All codes going to the page p r in t e r must be eight bit ASC II
codes. The data transfer rate is 100 milliseconds per character.
12.4.1 1713 Functions
Prior to selecting a mode, the controller and interrupts may be cleared by issuing
a function to the ·1713.
15
1
0
I
A [:}\)
t6
LR Controller
C LR Interrupts
LDQ
ENA
OUT
SEL TTY, FUNCTION
CLR CONT & CLR INT
=N$91
$3
-1
Interrupts may be selected by setting the following bits.
15
4
A F:::::::]
:.:.:.:.:
3
I I I
t
1
2
+
Data INT Request
End of Operation Interrupt
Alarm Interrupt Request
Bit 2 ---.. Allows the 1713 to interrupt the computer whenever the holding register
is ready to send or receive data.
Bit 3
~
Notifies the 1713 to interrupt the computer whenever an operation is
completed.
Bit 4
~
Provides for an interrupt whenever an alarm condition arises. Alarm
conditions:
1. 1713 becomes NOT READY
2. LOST DATA
3. Out of Tape
LDQ
LDA
NOP
=N$91
=N$lC
OUT
-1
SEL TTY, FUNCTION
INT ON DA TA, ALARM, EOP·
12;.,..18
C~
12.4.1
The operating mode, READ or WRITE, is selected by setting a bit in the function
word.
15
9
8
t
t
Select Write Mode
Select Read Mode
LDQ
LDQ
NOP
OUT
LDQ
LDA
NOP
OUT
o
SEL TTY, FUNCTION
WRITE MODE
=N$91
=N$100
-1
SEL TTY, FUNCTION
READ MODE
=N$91
=N$200
-1
When running in Tape- To- Tape Send Mode, the pro g ram must issue a START
TAPE MOTION function. When reading data from the reader a start motion function
must be issued after each character.
15
5
I I
+
Start Tape Motion
LDQ
LDA
=N$91
=N$2220
NOP
OUT
-1
SEL TTY,I_:fl!!'ICTION
TAPE SEND, READ, START TAPE
MOTION
All of the functions ma v be iss u e d together with the exception of the clear con~roller and clear Interrupt functions which must be issued separately.
12.4.2 1713 status
Status may be taken on the 1713 at any time.
LDQ
NOP
INP
=N$91
SEL TTY, STATUS
-1
STATUS IN A
o
12-19
12.4.2
A
k~ttf})ttfjtl
11 10
9
I
J
It(ttt~
6
4
3
2
1
I
J
J)
Manual INT
Motor On
Read Mode
5
Lost Data
0
1
keady
Busy
Interrupt
Data
End of Operation
Alarm
11
When the corresponding bit is a 1, the condition exists.
READY
BUSY
----+~
The 1713 is in the process of performing an operation.
--,~~
INTERRUPT
The 1713 is capable of performing operations and accepting functions.
----.~
DATA
An interrupt has been generated.
The holding register in the 1713 is prepared to send or
receive data.
END OF OPERATION --+ The 1713 has completed an operation.
ALARM
An alarm condition exists in the 1713.
LOST DATA ---..
The 1713 had data in the holding register which was not
picked up by the computer before another character was
read into the register.
READ MODE
The 1713 is in are a d mode. If this bit were not set,
the write mode would be in effect.
MOTOR ON
----+~
---.~
MANUAL INTERRUPT
The 1713 mot 0 r is on.
motor is not on.
C~
If this bit were not set, the
~The
manual interrupt button on the 1713 has been
pressed.
12.4.3 Example Program, 1713 TTY
The following program generates 10 frames of data in the A Register and ·punches
them on paper tape. It then stops and waits for the tape to be put in the reader.
It reads 20 frames and stores them in a buffer. Program read can be checked by
sweeping the buffer.
c
12-20
C)
12.4.3
The STOP Switch should be set before the program is run.
OOOl
0002
OOOJ POOOO 0000
0004 POOOI EOOO
ROO£l2 00~1
0005 POO03 OA03
0009 ROOO4 03j::~
0007 POOOS 02FE
0
ENT
~l1113
0
LDQ
RIIZ13
PT1713
0
=N$91
TTY, FUNC/STATUS
INP
$3
-1
-1
O~T~
Al:S
15
READY
0009 POOO7 0131
0010 120008 18EC
0011 POOO9 COOO
ROOOO ~12()
0012 POOO8 0800
0013 Roooe o 3~-E
0014 pooon ODFE
00]5 ROOOE S8~)
001f1 POOOF OAOF
00]1 eOOl{) 03EE
0018 POOll DOFF
0019 eOO12 Clon
POOl3 FFF5
0020 eOO]~ 0] 0 )
0021 POOl5 1 HF 9
0022 eOOle 5839
0023 POO17 0000
0024- POOla 1)001
0025 POO19 OAOI
0026 e001{}' W3FE
0027 PODIA 02FE
0028 e001C (lECE
0029 POOIO 0131
0030 eOOlE 18fC
0031 POOIF COOO
120020 20un
0032 P0021 0800
0033 eQQ22 Q3EE
0034 POO23 OA20
0035 e002~ O]fE
0036 POO25 ODFE
0031 e0026 Ot::H1O
0038 P0027 02FE
0032 eOO2~ 0118
0040 P0029 0001
004] eOQ2A 1St: ~
0042 pa02A coon
eOO2C 2QUO
0043 P0020 onOl
OO~~ e002f UbQQ
0045 POO2F 03FE
OO~6 EOll30 OAZQ
0047 P0031 03rE
OO~B Ell!l32 QDEE
0049 POO33 02FE
OOSO EOO34 byo7
SAM
1
*-3
=N$4120
SKI P WHEN READY
0006
0
~IOM
~O'HIE>
ENA
0111
IMR*
LDA
CLR CONTR, CLR INT
INP STATUS
BIT
GG Wl.c±± ±Ibb &EAl)¥
TTR, WRITE, START MOTION
NOP
0111
-]
I N(l
ENA
-1
I EADE~
$F
DATA $F IN A
0111
-]
RAO-
I
QtJtFlJt DAXA
~I
WRITE
I
STOP
1*
D~
SAZ
)
JMP*
eI 1*
SLS
WRITE
I E~DEH
0
I~IQ
1
ENA
1
0111
-]
INP
~I 5
SAM
-1
IMe*
SEL
-~-]O!I
LDA
15
1
*-3
=N$2000
PREPARE TO SEND DATA
GG GlJ±PlJ± bEWER
lQ FRAMES
GO OIIT EI IT TRAILER
FREPARE FGR
FYNG~IQN
CLEAR CONTROLLER
INPUT STATUS
READY
BIT
SKI P WHEN READY
GO WAIl IJNTIL
READY
TTS MODE
NOP
~UI
MOTION
ENA
OllI
INQ
-1
$20
START MOTION
-1
-1
PREPARE FOR DATA
INPUT DATA
STORE WHEN DATA COMES
LDA
-1
SIOHE-*-l
1
SEI
=N$20aO
TTS MODE
INQ
1
FUNCTION
E~A
-1
$20
OUT
STABT TAEE MOTION
-1
~OE
LDR
READ
INP
SAD!
INQ
.H1e*
Dloe
OUT
STORE
GO WAIl EOR
I~Q
-1
DATA
INP
SIA*
-1
RlJE!!
STORE DATA
12-21
INPUT DATA
DATA
(\
12.4.3
'---'
0051 POQ35 OOFF
0052 PU036 CIOO
PIJQ3l
I
LOA
=N-20.I
SAl
SLS
FINI-*-l
RE;oD
0
azs
911f=:(~O)
0
0
-X-50
20 FRAMES
F~-l=fj
0053 P003H DIUl
0054 POY=i~ 1~1=1
0055 POO3A ()ouu
OOS~ ~O038 ODIc..
·0057 POO4F 0000
0058 ROOSO
ROO-
eono
JMI2i!
FINI
1:i1J~
LEADER
bDA
STOP AFTER READING
BW~EB XO CHECK
WRITE LEADER OR TRAILER
SWEEE
POOSl 7fCD
0059 PUO!3~ ~O~F
0060 POOS3 0844
0061 PQQ34 Q J~ E;
0062 P0055 DOFF
OQ~J
PGQ~~
QbJ+b6l~
g I tIl
~+I\-
I
CLR
A
-1
GlJ+
RAO~GV
00h4 P0057 IHFC
JMP*
9U~ ~
~+o-
00h6 P0059 lCF5
0061
JMP*
OQ6~
PCJo~a
I
1
OUTLDR
I
(LEADER)
E~ID
c
Plant 2 - September 1968
12-22
o
12.5
12.5 1726/405 CARD READER
The 405 is a Non-Buffered Card Reader capable of reading 1200 80-column cards per
minute or 1600 51-column cards per minute. The transfer rate for one 80-column card
is 384 microseconds.
The twelve rows in each column constitute the 12-bit data word transferred to the computer. Software packing must be performed in order to form a 16-bit word. The format
for the columns in relation to memory words is as follows:
15
4
7
I Col
ColI (12 rows)
Word 1
Col 2 (8 rows)
Word 2
Word 3
Col 3 (4 rows)
2 (4 rows)
Col 3 (8 rows)
I
I.
o
3
Col 4 (12 rows)
Four card col u m n s represent three computer words, therefore, one 80-column card
represents 60 memory words.
The data read by the 405 may be buffered if connected to the 1706.
The Q Register will be in the following format when referencing the 405 Card Reader.
o
15
11 10
7
6
1
0
··················································· ........... ~
W= 0
Q
??~ttt?tttmmmmmmmr~ D
E
1
I
The E portion will correspond with the setting of the equipment switch on the controller.
The D portion designates the operation to be performed.
12.5.1 CR Functions
D = 1 DIRECTOR FUNCTION (OUT)
LDQ
LDA
NOP
OUT
15 14 13 12 11 10
A
[:}~{{{:}\:J
Reload Memory+
=N$0101
=NFUNC
EQUIP 2, FUNC
FUNCTION IN A
-1
ESTABLISH LOGIC
I I I
9
876
4
3
I
2
1
o
t
t
~ LR Controller
Negate Hollerith to
I CLR INT
ASCII
Data INT
Release Negate Hollerith
EOPINT
to ASCII
Alarm INT
1
o
5
11
12-23
12.5.1
The functions for the 405 Card Reader may be issued jointly.
Clear Controller (Bit 0): Directs the clearing of all interrupt requests, mot ion
requests, errors, and other logic that may be cleared. This function is subordinate to all other functions.
Clear Interrupts (Bit 1): Clears all interrupt requests and their responses.
Data Interrupt Request (Bit 2): Sets the interrupt request to be set which causes
an interrupt to be generated when an information transfer may occur.
~terrupt on End of Operation (Bit 3): Requests an interrupt to be generated when
the last card column lias been read or a Reload Memory Function has been performed.
Interrupt on Alarm (Bit 4): Generates an interrupt whenever any of the following
conditions arise:
1.
2.
3.
4.
5.
6.
Compare or pre-read error
Stacker full or jam
Input tray empty
Fail to feed
Separator card is read into computer memory
Auto/man switch is in man position
Gate Card (Bit 9): This bit gates the card being read to the secondary s t a c k e r.
This function must be performed during the 1.5 milliseconds following the input
of the last column to the buffer memory of the Card Reader.
Negate Hollerith to ASCII (Bit 10): When bit A10 is selected, 7 and 9 punch positions
in column 1 are ignored and all information (binary or Hollerith) is read as binary.
Bit A10 is subordinate to bit All. Bit A10 is rejected if the controller is Busy.
NOTE
Before beginning a new operation, make certain that bit A10 and the
following bit, All, are appropriately selected. If this is not done,
the cards will be read in the mode or state that the card reader was
in during the previous operation.
Release Negate Hollerith to ASCII (All = 1): When bit All is selected, the 7 and 9
punch pos itions in column 1 determine whether the card information is to be transferred in ASCII code or in binary for m. The Release Negate Hollerith to ASCII
function takes precedence over the select Negate Hollerith to ASC II function, and
it is rejected if the controller is Busy. See Note.
12-24
o
12.5.1
Reload Memory (A12 = 1): This bit directs the controller to initiate a card feed
thereby reloading the controller memory with the data from the next card in the
card reader. The data that has not been t ran s mit ted from the memory to the
computer is lost when Reload Memory is executed. A Reload Memory is required
only if less than a full card of information is desired. Bit A12 is rejected if the
controller is Busy.
12.5.2 CR Status
D = 1 STATUS (INP)
LDQ
=N$0101
EQUIP 2, STATUS
-1
STATUS IN A
Nap
INP
15 14 13 12 11 10
A
o
9
8
I I I
7
+
6
·:·:·:·:·j
.........
f.........
I
5
43210
,
1 Ls:eadY
Alarm
Protected
Error
Interrupt
Binary Card
Data
EOP
Separator Card
Fail to Feed
Stacker Full of Jam
Input Tray Empty
End of File
Manual Switch or Motor Power Off
1
i
1
Ready (Bit 0): The presence of this bit indicates that the card reader is ready for
operation.
Busy (Bit 1): The controller is Busy whenever a card is being en t ere d into the
buffer memory.
Interrupt (Bit 2): The interrupt status is available if one or more of the selected
interrupts has occurred. Other bits must be monitored to determine the condition
causing the interrupt.
Data (Bit 3):
computer.
This status bit indicates that data is ready to be transferred to the
o
12-25
12.5.2
End of Operation (Bit 4): This status bit indicates that the last card column has
been read from the buffer memory, or a reload memory function has been sent.
This bit remains a 1 until a Reply signal is sent, or a Clear Controller function or
Master Clear is issued.
Alarm (Bit 5): The bit remains a 1 until whatever caused the Alarm condition is
removed. This s tat us bit indicates that one or more of the following conditions
has occurred:
1.
2.
3.
4.
5.
6.
Compare or Pre-read error
Stacker full or jam
Input tray empty
Fail to feed
A separator card has been transferred to the computer memory.
The AUTO/MAN switch is in the MAN position
Status bit A06 is not used.
Protected (Bit 7): This status bit indicates that the controller recognizes only the
I/O instructions that have the protect bit present. This status bit is a 1 when the
PROTECTED/UNPROTECTED switch is in the PROTECTED position.
Error (Bit 8): This bit indicates that a Pre-read or Compare error has occurred.
Binary Card (Bit 9): This bit is present when the contents of the first card column
have been transferred to the computer memory and a binary card (rows 7 and 9
punched in first column) was detected, or the Negate Hollerith to ASC II function
was selected. This bit remains a 1 until a Clear Con t roll e r or Master Clear
function is issued, or a Reply is sent when a card is read under the follow in g
conditions:
1. The card is not a binary or a separator card.
2. The Release Negate Hollerith to ASCII function is selected.
Separator Card (Bit 10): This bit is present when the contents of the fir s t card
column have been transferred to computer memory and a separator card (rows 6,
7, 8, and 9 punched in first column) was detected. This bit remains a 1 until a
Reply is sent when a card is read that is not a separator card, or until a Master
Clear or Clear Controller function is executed.
Fail to Feed (Bit 11): This bit is a 1 if another card is not detected at the primary
read station 500 ms after the previous card has cleared the secondary read station.
Stacker Full or Jam (Bit 12): This bit is a 1 when the stacker is full of cards or
when the cards have jammed.
Input Tray Empty (Bit 13): This bit is a 1 when the input tray is empty.
12-26
(~
o
12.5.2
End of File (Bit 14): This status bit becomes a 1 when the input tray is empty, the
buffer memory is unloaded, and the END OF FILE switch is on. When the input
tray does not contain the last card of a file, the switch should be off to inhibit this
status bit.
Manual (Bit 15): This status bit is a 1 when the A UTa/MAN switch is in the MAN
position or the MOTOR POWER switch is off.
DATA (INP)
D= 0
LDQ
NOP
INP
I
0
EQUIP 2, DATA
-1
DATA IN A REG
o
12 11
15
A
=N$0100
o
0
0
I
DATA
Packing must be performed in order to obtain 16 bit words as indicated earlier in
this discussion.
o
o
12-27
C:
12.5.3
12.5.3 CR Example Program
START
SECOND
LOOP
DONE
03FF
0004P
NAM
EQU
EQU
BSS
CLR
STALDQ
LDA
NOP
. OUT
INQ
NOP
INP
ALS
STA*
INP
STA*
ARS
AND
ADD*
STA*
LDA*
ALS
AND
STA*
INP
STA*
ARS
AND
ADD*
STA+
LDA*
AND
ALS
STA*
INP
AND
ADD*
STA*
LDAINA
STAINA
SAZ
JMP*
LDQ
RAO
LDA
SOV
JMP
SLS
END
CARD
LOOP
CARDRD
AA($3FF), CARD($0281)
MASKB($OOOF)
TEMP (2)
A
I
=XCARD
=N$lA03
SEL EQUIP 5 F
CLR CON CLR INT RM H TO A
-1
-1
OUTPUT FUNCTION
PREPARE FOR DATA INPUT
-1
4
TEMP
-1
TEMP+1
8
=XMASKB
TEMP
AA,I
TEMP+1
8
=N$FFOO
TEMP
-1
TEMP+1
4
=X$OOFF
TEMP
AA+1,I
TEMP+1
=XMASKB
12
TEMP
-1
=N$OFFF
TEMP
AA+2,I
I
3
I
-54
1
LOOP
=XCARD
*+3
=N$7FFA
1
SECOND
INPUT TO A FmST COLUMN (12)
DATA UPPER 1 I BITS ••• ZERO
INPUT 2nd COLUMN
SAVE THE DATA
UPPER 4 BITS IN LOWER 4
ZERO UPPER 12 BITS
FmST WORD PACKED
LOWER 8 BITS IN UPPER 8 BITS
ZERO LOWER 8 BITS
INPUT 3rd COLUMN
C
UPPER INPUT 8 BITS IN LOW 8BITS
ZERO UPPER 8 BITS
PACK 2nd WORD
PLACE IN BUFFER
ZERO UPPER 12 BITS
LOWER 4 BITS IN UPPER 4 BITS
THIRD WORD PACKED
GET INDEX
UPDATE INDEX
IF END OF CARD SKIP
CONTINUE
0281
OOOCP
MASKB OOOF TEMP OOOOP
DONE 003EP
12-28
c-'
o
12.6
12.6 1742 LINE PRINTER
The 1742 Line Printer (the Holley HR-300 Printer) prints 300 lines per min ute, each
line being 136 characters. The printer accepts ASCII codes with two characters per 16
bit word. The printer has a holding register capable of accepting an entire line before
printing: 136 characters (8 bits) or 68 words (16 bits). The ASCII codes require 7 bits,
therefore, the 8th bit is used as a print control bit. This bit on each character is set
by the controller when the c h a r act e r is received. As the printer actually prints the
character, the 8th bit is cleared. When all print con t r 0 1 bits have been zeroed, the
printer has completed the print operation and is ready to receive data from the computer.
The programmer is not required to send the maximum number of c h a r act e r s to the
printer. The p r in t e r accepts the characters sent by the program and blanks the remaining positions prior to printing.
The Q Register will address the printer in the following format:
15
6
1
0
w
Q
o
7
11 10
The W portion will equal zero. The equipment number will correspond to the equipment
setting of the hardware switch on the controller ($O-$F). The D portion will direct the
type of transmis sions to and from the A Register.
DATA
D=OO indicates the transfer of data to the printer's holding register.
issued with an OUT instruction.
LDQ
LDA
NOP
OUT
It will always be
=N$0380
DATA
EQUIP 7, DATA
PLACE DATA IN A
-1
DATA SENT TO PRINTER
12. 6. 1 LP Functions
DIRECTOR FUNCTION 1
D=01 denotes the transfer of Director Function 1, which allows the programmer
to CLEAR PRINTER and CLEAR INTERRUPTS. It also provides the medium for
selecting as many as three interrupts: DATA, EOP, and ALARM.
A
15
0
0
0
0
0
0
0
0
0
0
5
0
I
4 3 2
1 1111
1 top! r
Alarm
C)
12-29
I
1 0
1 11
I
+
Clear Controller
C lear Interrupts
Data Interrupt
c
12.6.1
LDQ
LDA
OUT
EQUIP 7, FUNC 1
PLACE FUNC IN A
SEND FUNC
=N$0381
FUNCI
-1
DIRECTOR FUNCTION 2
D=11 accompanied by an OUT instruction sends Director Function 2 to the printer
from the A Register.
LDQ
LDA
NOP
OUT
15 14 13 12 11 10
t
r
=N$0383
FUNC2
EQUIP, FUNC 2
PRE SET A TO FUNC
-1
SEND FUNC FROM A
9
8
7
6
5
4
, + + + + + I , +I + + I
3
I I I
12 11 10
9
8
7
6
5
4
3
2
8- Line Select
2
1
I I
t
r
1
0
+
Print
Single Space
Double Space
Levell
Print (Bit 0=1) - . Commands the printer 0 per a t ion to begin. Once the entire
line has been printed the 0 per a t ion is complete. The print
command must be issued for each line printed.
Single Space
(Bit 1 = 1) ~
Advances the page by one line.
Double Space
(Bit 2 = 1) ----+
Advances the page by two lines.
Format Level
(Bit 3 - Bit 14)
~
This command causes paper motion. The paper is moved to
the next hole punched in the specified level. The tape levels
are used for formatting documents, as the levels may be used
instead of the spacing commands. Levell usually specifies
top of page while level 12 usually s p e c ifi e s bottom of page.
8- Line Select
(Bit 15 = 1) ----. This bit changes the logic to allow for 8 lines per inch rather
than 6 lines per inch. Once 8 lines per inch has been selected
it remains in effect until a MASTER CLEAR, CLEAR CONTROLLER, or bit 15 is issued as a zero.
12-30
c
o
12.6.2
12.6.2 LP Status
D=Ol with an INP instruction requests status.
LDQ
NOP
INP
15
A
I
6/8 Lines
=N$0381
EQUIP #7, STATUS
-1
BRING STATUS TO A
10
9
I
8
7
6
COinCident~ ~
4
1
3 2 1
111
i
t
I
i
0
1
~eadY
Busy
Interrupt
Data
End of Operation
Alarm
1
Protected
o
5
1 k~{~ 1 r········1
.... 1
The status of the Line Printer notifies the program of the READY and BUSY states
of the printer by setting bits 0 and 1, respectively. Bit 2 indicates the existence
of an interrupt, while bits 3, 4, and 5, designate which interrupt was generated.
Bit 3 is the bit in d i cat ion that the printer is prepared to receive data from the
computer. Bit 4 notifies the pro g ram that an operation is complete, such as a
print or top of form command. Bit 5 indicates an ALARM condition has occurred,
such as out of paper, paper tear, fuse alarm, open interlock, or an illegal character. Bit 7 corresponds with the Protect Switch on the printer. If the switch is
on, bit 7 will be set and only protected programs will be allowed to use the printer.
Bit 9, when set, acknowledges that a c han g e from 6 to 8 lines per inch may be
effectively made.
12. 6. 3 Programming the Printer
Programming the printer simply requires advancing the page to the desired print
level. Once the page is positioned, data is sent to the printers holding register.
Once the data has been sent to the printer, the p r in t command is issued. When
the printer com pie t e s the print cycle, the program advances the page by level
selection, or spacing and outputs the next line. The programmer selects the top
of page level (usually Levell) once a page is complete.
o
12-31
12.6.4
12. 6. 4 Example, 1742 Line Printer
PRINT
0001
~.!AM
440~
------ --------------------~T_- - ___________ OQ -l-NT
. 0 0 f) i
',-,<
it n /l f)
;.I;)t)f) 1
~
!)
n ()
P
Q
rr\1 T
{}{)-04---··iJOOO-~··--oArq.-
.. ---
. -fNA .-- .. - ---1-·
()t1T-1
0005 ;:;0001 01FF
0006 P0004 Fnno
LnQ
---+p4-l04-lnH-JO~!L7_~-------.
o0 0 7
j-'
Ii () 0 IS
-----q
f1.l\'" ~
0
EQUIP 15, FUNC 2
. - - . - •• -
LEVEL 1 TOP OF FORM
~
-1
OIIT
-G-O-0-9--+' {} t}-Q-R -G 1) n1)----.- --.- .--.
P0009 7FFA
0010 POOOA 6A26
EQUIP .15, FUNC 1
CLR CONTROLLER-
=N~0781
_ h _ _ _ _ _ _ _ _ _ _ •. _ _ _ . _ _ _
DOOR F-'0007 OiFF.
0011 PO 0 Oq
= ;\1 q., f) 7 R 1
L i) ()
()7o.1
--- -LOA
.. =Xi)7FFF"';l"
STA*
LIN~CT
LOOP FOR OVERFLOW·· ..-·
6 LINES PER PAGE
A4'1 ----I:--1>.P"-------Gh..Q-·-------.-A-- ----- .-- .---- -
001? poooe ~()FF
0013 ~noon OOFC
STA-
T
INn-3
-0 Gl4-·--r' O-G-9-E·---G9-l--l-· --- -().lJ-T-· --- --LtJA-*- -. -----.. [)Al"-A.~ I
NOP
OUT-l
0015 POOOF ORno
0016 ~OOI0 03FE
ZERO INDEX.
PRINTER FOR DATA
2 ASCII CHARACTERS-··
CHECK WORD LOOP-------17 CHARACTER PER LINE
0019 ~OOI1 1110?
SAZ
hJEXTL
SKIP IF COMPLETE'
{t.g~O-·+tH)-l_4·PO~-F_-·--_:_----·------· ·--R-AC)--... -----.--1-----.--- ..-.-- -- -NOT GOMF,-- UPDATEINDE*----OO?1 POOle; lRF8
J~1P*
OUT
CONTINUE LINE OUTPUT
002? ~OOlt, ().I103
I\lFXTL·
H·.!Q
1
LINE COMPLETE FUNCTION
-{l~ PO 017 C) 0. O-l--··--···-----·-- . --·--..--·€-NA --------------1:---.------------ ·PRIN~eMMAND·'------- ---' .
0024 f-JOOI A fl1FF
OUT-I
OO?5 ~J001q Ofl()4
F.:"lA
4
DOUBLE SPACE
--&e+1-f4H.H 1 COFf'"
0018 (.Jon I? fl9FF
4{)~··~tlO_lA---q-'1FF_
1::-8-A-----... --'f-----.---- -..--.-----II\lll.
--- ----.-------. ---.- OU T----·---- ---
0027 POOIq OBlS
OOi?A ijOO 1 C () 1 Al
~Q--~l n 1 RFO
noon
0030
~001~
0011
;.JOOIF ·r.:;44R
-<1;
RAO*
11
·-1--- -- -
----------. -
------.---- ----.---- -.----
UPDATE LINE COUNT
SOV
cr-1p
SKIP IF PAGE COMPLETE
--------.--J14P-*------------CN:T---------- -CONTINUE .IF-P~E--NOT COMPLETE
CMP
I)ATfI
L!I\JECT
SLS
ALF
.
...
..
-I*",THIS PROGRAtA \~'()Pt P
T'\l T
12-32
c
o
12.6.4
THIS
PROGR,A'M ,INOPKS
THIS
PQORR4"1
THIS PQOGRAM
ON PRINTER 1742
1742
"/ORKS
ON PQINTfR 1742
.-.--
--.----.--.----.---.~
THTS
PROGRAM \A/ORKS
TIfTe; P P (U;-9-1\ ~ 4 h'ORKS
ON PRINTER 1742
O~j
PPI~jTE=R
1742
THIS PROr,QAM \,\1001<5 ON PPINTEQ 1742
o
Note what happens in the following program when the functions for print command
and double space are issued Simultaneously! (Line 23, ENA 5.)
12~33
12.6.4
0001
0002
0003
PRINT
I\!A~·1
FNT
~o~on
~n00
PRINT
;:";0001 07q]
r:::'{} ·0· !).?:--.1l-M.-l-.--------.. -----JF~._/\~ILlrl\,~0005 i;"OOOl 03FE OUT
-~- -fh.'}1}-4
0006· PQ004
fono
PRI"/T
=N1i0781
Lon
--1-1-·
-1
LDO
=.f\J$0783 .
E~A
8
Cl-R--··.GOf\C!:---
_--,-,-0 Q-4-{tS-f.LlR}-.--.
0007
~noo~
o008
DAOA
TOO OF FORM
p () 0 07 () 3 F E
0 II T
- 1
--·~{}-0-9-·-~tJ·90B_.... C_G-~-------·---.-_b~.+A_--- .. - . . ----=X..$_1f'F-F--'5-·· .
P0009 7FFA
0010 POOOA ~A?4
STA*
LINECT
~·e-l-]
;~o 04-0 0 844
-*'~
CLR
Q
0012 poooe 60FF
STAI
0013 ~000~ 0nFC
INQ-3
-_·-{)-O-l-4- -P-fJ-.f:)4E-- G-9.n.F---~---·-b.-DA*-----IJ-A.+.A.·._I-·-·----.
0015 POOOF OROO
NOP
0016 ROOlO 03FE
oa11 p 13 ell 1 € q F-F-
OUT-l
L Dl\ -
o0 1 8
\.:/{);) l? I) q F ~
001 9 \;;',0011 () 1 n?
---f; () 2-{}--,-;-J{t-O-l-4 f) 0 Ff
0021 POOlS 18FA
OO?2 P0016 0003
~3--+,,-*l-+ ('I~ (' S
00(>4 POOI P
OO?S
I
NEXTL
.
03FE
.
~OOlq'OR15
OUT
JMP*
INQ
E '~Q
our
-----~V- .. -
CMP
3
'5
:--
-1
J
LINECT
RAQ*
---..·trO-?-6----.p{H)-b~ 01 A+
0027 pnOlg 18EF
0028POOIC 0000
I
I I'.J A
- ~11
SAl
f\,JI:.)(, TL
R4G-------I------· . -----·-----
---.~----
JMP*
SLS
tNT
-B.~~ ~)-L/~I'''''''~Q~_.--40-:1-<,.ot.\-,Th.(JI.\-,---A-l'.'I-F~.----.x*..
,-+T-I=:1HI-l-I~-R.q-GQ·~-j,JJJ-QK.S----ON-AA-P1 TER
;J001~
4QSl
:;nOl~
;>050
- ..---__ --~..Lll{}-?4-t::; ?:4-F-----:-----------
?0021 4752
r:'002? 4140
-----·-~~#q~c:;+7--
)-Jt)024 4FS?
\-' 0 0 ?" '-'- R 5 3
··-------·----~-H·~--?44F--
P0027. 4E?O
P002R 50S2
-----------P-fh')-;.?q
494£.
Pon2L\ <=)445
~)QO?q
S2?O
.------.. - ---PG{}-2·{?---3-·l-3-+--------·--p'002n 3432
BSS
~INECT{l)
0030 P002E 0001
------------------E·~~!O~--~~P~Q~,I~~~'T~·
. 0031
12-34
17', 2*
12.6.4 .
P
r
T::)
R
'.
--:t+T S P RB GQ.o, q
T
~Ts pP0~qAM
_~.J,.
.
p·
~OPKS ON PRINT~P 174?
PROGRAM
o
.~.
______ "_ "..
ORKS ON
\it!
p
T R
-hlC}PK-s-SL~-f-N-~_-l--+4~
__ '___ .__ ..___.. __ " __ ..____ \#../"
T~TS
P
s
OG AMO K
ON
._.~._._.,.._
....
_~~,
__ . _______ ___ ..___.__
PRINT~q
P
IN~.
~
~
1742
1742
Digigrapbics - September 1969
C)
12-35
12.7
12.7 1738/853 DISK
The disk is a buffered peripheral device attached to the 1705 Direct Access Bus. All
data will be buffered in and out of memory via the 1705 in 16-bit words. The functions
will be sent from the A Register and status will be r e c e i v e d in the A Register, necessitating the connection to the A/Q channel. The disk transfers 16-bit data words in
12.8 microseconds. Access time for positioning the head is 165 milliseconds maximum.
Cylinder-to-cylinder pos itioning time is 30 milliseconds. The disk has a maximum
latency time of 25 milliseconds.
Ninety-six 16-bit words may be s tor e d on one sector with 1,536 words on a track and
15,360 words to a cylinder. The 853 disk pack allows a total of 1,536,000 words, while
the 854 disk pack has a capacity of ~, 118,080 words.
The data format may be summarized in the following:
16
96
16
10
100
203
Bit data words
Words to a sector
Sectors to a track
Tracks to a cylinder
Cylinders to an 853 file
Cylinders to an 854 file
The three interfaces for communications with the 1738 controller are the A/Q channel,
DAC (1705) and the CONTROLLER/FILE. The A/Q channel is the interface between
the con t roll e r and the programmer. It is via the A/Q channel that the programmer
may status the disk and issue functions. The DAC is the interface between the controller
and the computer's memory. It is via this channel that the data is transferred. The
DAC also provides the 1738 access to the LWA+1 of the programmer's buffer area.
CONTROLLER/FILE INTERFACE is used for communications between the controller
and the disk. It is through this interface that the con t roll e r informs the disk of the
Sector Record Address selected by the programmer. The SEEK operation which positions the read/write heads to the SECTOR RECORD ADDRESS is generated by the
controller once the controller receives the desired add res s from the A/Q interface.
The controller will issue a SEEK FORWARD or SEEK REVERSE command depending
upon the current position of the read/write heads. It does not return to a set address
prior to positioning on a new address.
12-36
c
12.7
SIDE VIEW:
850 DISK PACK
(6 DISKS)
L_ - - - - -- DISK SURFACE 0
C-------DISKSURFACE 1
------------~---------7-L ______ _
,------______ _
~-------;-----------7L--
.-- -
- - -
---
----------;-----------TL-______ _
,------- - - - -
------:--------~.--
-
. - - - - - - - DISK SURF ACE 9
-----------~-------~-
TOP VIEW:
DISK SURF ACE
o
CYLINDER 00 -
-
CYLINDER 99 -
-
1-----,
--SECTOR 15
--SECTOR 0
--SECTOR 1
DIRECTION OF
ROTATION
853 contains 100 cylinders; 854 contains 203 cylinders.
Figure 29. Disk
o
12-37
12.7
Figure 30. Sector Format on Disk
ADDRESS
\
DATA
HEAD
GAP
I
60
BITS
CHECKWORD
c
Each sector on the disk contains the above information. Note that the 96 16-bit words
of data (1536 data bits) are in addition to the other check bits in the sector.
12-38
o
12.7
Figure 31. Data Buffer for Disk
r-----------,
I
LWA + 1
I
I
FWA-.
DATA
o
LWA-+
FWA-1 must contain LWA+1 of buffer.
o
12-39
12.7
~,
l ..
The Q Register will contain the address of the disk.
Q
15
11 10
0
01 10Jo[0]
7
r
'-----v--~
E
D
I
'----v-----'
Director Bits
Equipment
W
o
6 5 4 3 2
r010Jolo]
W field is zero and E field contains equipment number (set on controller).
The setting of the director bits will define the desired operation to the controller.
The contents of the A Register will vary according to the director bits.
12.7.1 Disk Functions
DISK 'FUNCTION CODES
Value Set in Q
(Bits 02 - 00)
001
010
011
100
101
110
111
Output from A
Input to A
Director Function
Load Address
Write
Read
Compare
Checkword Check
Write Address
Director Status
Address Register Status
(
'
'-....
__ ..
12.7. 1. 1 Director Bits 001 - Director Functions
This setting with an OUT instruction prepares the controller for director functions
which are found in the A Register. The functions for the disk may all be sent at
the s arne time.
15
10
9
8765432
1
0
1::::::::::::::::::::1
cOde~l.
Unit Select
Unit Select
Release
I
blear Interrupt
Ready & Not Busy Interrupt
End of Operation Interrupt
Alarm Interrupt
11
The CLEAR INTERRUPT function will clear all selected interrupts allowing the
programmer to select the interrupts he des ires. Three interrupts may be
selected: NEXT READY AND NOT BUSY STATUS, END OF OPERATION, and
ALARM. The NEXT READY AND NOT BUSY interrupt occurs when the 1738
becomes not busy, but still maintains its ready status. This interrupt can be used
during an overlap seek. The overlap seek is used when two disks are connected
to one controller. The programmer may issue a sector record address for one
12-40
o
12.7.1.1
disk and then issue a sector r e cor d address for the other. The controller will
generate a NEXT READY AND NOT BUSY interrupt, if selected by the programmer,
when one of the disks reaches the requested addres s.
The END OF OPERATION interrupt allows the controller to inform the 1700 when
it has completed an operation such as a data transfer. The ALARM INTERRUPT
will notify the 1700 that an alarm condition has arisen. There are eight possible
alarm conditions; not ready, checkword error, lost data, seek error, address
error, defective track, storage parity error, and protect fault.
The RELEASE function allows an unprotected program to use the disk even though
the protect s wit chon the disk is still set. A protected program must issue the
release function. The next time a protected program accesses the disk, the disk
will become protected and must again be reI e as e d before the disk will become
accessible to an unprotected program.
The UNIT SELECT and UNIT SELECT CODE will always be zero unless two disks
are connected to the 1738. Bit 8 is the UNIT SELECT bit which informs the controller that the pro g ram will select unit 0 or unit 1. Bit 9 indicates which unit
bit 8 wishes to select. If bit 9 is a 0, unit 0 is s e 1 e c ted; if it is a 1, unit 1 is
selected. The controller ignores bit 9 unless hit 8 is set.
o
12.7.1.2 Director Bits 010 - Sector Record Address
This director code in the Q Register with an OUT instruction will send the SEC TOR
RECORD ADDRESS from the A Register to the controller. Once the controller
receives the address, it in it i ate s the seek operation. The SEC TOR RECORD
ADDRESS will be in the following format:
~
15
AI ______c_Y_L_I_ND
__E_R
________
8
7
4
3
o
~___H_E_A_D____~__S_E_C_T_O__R~
12.7. 1. 3 Director Bits 011 - WRITE
The WRITE function code requests the controller to pre par e to read data from
memory and write it on the disk. P rio r to this function, the programmer must
send the SECTOR RECORD ADDRESS to the controller.
The controller expects to find the first word address minus 1 (FWA-1) of the buffer area in the A Register when the write function is re c e i v e d. The controller
goes into memory via the DAC to the FWA-1 at which location he extracts the last
word address plus 1 (LWA+1). The controller keeps the LWA+1 and updates the
FWA-1 until the two are equal at which point the write 0 per at ion is complete.
Prior to issuing the WRITE function, the SECTOR RECORD ADDRESS must be
sent to the controller and the LWA+1 of the buffer area must be at the FWA-1.
12-41
12.7.1.4
12.7. 1.4 Director Bits 100 - READ
The READ function code follows the same programming procedure as the WRITE
function. The d iff ere nc e being the disk reads data into memory rather than
w r it in g data on the disk. An unprotected program may READ from a protected
disk without generating a protect FAULT, howe v e r, if an unprotected program
attempts to w r it e on a protected disk, a protect fault will occur. An alarm interrupt will be generated if previously seJected.
12.7.1.5 Director Bits 101 - COMPARE
The COMPARE function code follows the same programming pro c e d u r e as the
READ and WRITE function codes. The COMPARE function causes the controller
to read data from the computer's memory and compare it with the data stored on
the disk. If at any time during the compare, one word does not compare, the NO
COMPARE s tat us bit will be set. This function provides an extra check on the
validity of the data transferred.
12.7. 1.6 Other Director Functions
The remaining director functions (CHECKWORD CHECK and WRITE ADDRESS)
are used by the customer engineers for maintenance work.
12.7.2 Disk Status
12.7. 2. 1 Director Status
D = 001 accompanied by INP instruction, will request the 1738 to send status to
the A Register.
15 14 13 12 11 10
A
I:~{{~
Protect Fault
I I I
1 11
9
8
Storage Parity Error
Defective Track
Address Error
Seek Error
Lost Data
Checkword Error
7
6
5
4
3
2
1
0
I
I
heady
Busy
Interrupt
On Cylinder
End of Operation
Alarm
No Compare
Protected
11
c
12-42
12.7.2.1
The READY s tat us indicates that the unit is available. The BUSY bit indicates
that the controller and/or the drive unit is presently involved in the performance
of an operation. This bit is set with the acceptance of a LOAD ADDRESS, WRITE,
READ, COMPARE, CHECKWORD CHECK, or WRITE ADDRESS function. At the
completion of the function which set the BUSY status, the status will be cleared
and the disk will become NOT BUSY. Once the disk is NOT BUSY, a new function
may be issued.
The INTERRUPT bit acknowledges that an interrupt has occurred. Further examination of A will determine which of the three selected interrupts was generated;
bit 4 (EOP) and bit 5 (ALARM). If neither bit 4 nor bit 5 is set, the programmer
should check bits 0 and 1 for READY and NOT BUSY. If the alarm bit is set, the
programmer must evaluate A further to determine which of the eight alarm conditions caused the interrupt.
The ON C Y LIND E R status, bit 3, is set when the READ/WRITE heads have
rea c h e d the SECTOR RECORD ADDRESS initially sent to the controller via the
A/Q channel.
12.7.2.2 Address Register Status
o
The D=010 Q setting accompanied by an INP instruction will direct the controller
to return the cur r e n t sector record address of the disk to the A Register, the
location at which the READ/WRITE heads are currently positioned. It will be in
the same format as described in the Address Function.
c)
12-43
12.7.3
12. 7 • 3 Disk Sample Programs
.0001
N.A'"
OISK
. OOO?
----'---+-EN-~I~----------- ------- -------------0003 POOOO conn
DISK
LOA =XL~~'P()
LWA+1 IN 'A'
PODOl OOQ2 D
~4-~2-f,-A{H}--------------S-T-A---F\-/w)---------'-----'
P0003 OO?E
0005 P0004 DAOO
RAO
LWA+ 1 AT FWA-1
FLAG
UPDATE FLAG FOR LOOf
----.--- -_.----- -. --- =N$0181
EQUIP 3, FUNCTION
--~F-'~-&e--l-+-----------------------'
0006 POOOA EOOO
PO'007 0 UH
LDQ
00~8 P0009 03FE
_0009 POOOl\ -EOOO
nUT
LnQ
0007 ~~------~-------ENA--$-~H)-&2-------'- ----------CLR· INT
ZAP
--~pfrjO(H}~*R-?-- '
0010 poooe OAIO
0011 Pooon nlFE
-1
=N$01A2·
fNA
~OOlO
OUT
-1
EQUIP 3, LOAD ADDRESS
-------- ----CYL 0, HEAD 1, SECTOR
-{}&-l-2--P{l-O-oE--E-DtH)--·------tGfi}----~N_$_O I-B-l--
POOOF 0181
0013 POOIO OBOO
0
. ---------EQUIP 3, STA;TUS
NOP
--s-:fAr+T--HHIdtJPL..--+l-
-&Ol4 POOll f)2FE
0015 POOl? OFCC
0016 POOl) 0111
--{)-&l--7-.tJ-fH)--l-4----lA.F-Co0 .1 8 POOl SIC 0 0
0019 P0016 0000
-{H) 2 0 1-' (l 0 17 00 19
oa21 PO a 1 8 0 0 ? A
00?2 POOIQ COOO
------- POOlA n031-
0023 P0018 EOOO
--STATUS IN A
ON CYL
SA~
SKIP WHEN ON CYL
-----------------d!..4P-*-- ·-s TA--T -- - ------- -----WAIT
t-J U"'1
$ 1 COO .
JMP (0)
FLAA
0
0
D
--Af)-<>------w-R+TF--G(} WRITE
P A0 C
READ
GO READ
II/RITE LDA =XF',IMO
FWA-1 IN A
p--------------------- --.-------------------------- ---.
LOQ =N$0183
EQUIP 3, WRITE
ALS
12
1
h_
-
P001C 0183
-{H}-?-4--P-{HHtT-:-f)~-
OO?5 POOlE 03FE
0026 POOIF FOOO
NO P
nUT
xx
-1
LOQ =N$OI81
~---_ --fJf}-020----0'1 ~H------------ -----. ----------.-----: -- - -- -----, 0027 P0021 .OBOO
.' MOP
OO?8 P002? O?FE
LOOP
INP - I .
EQUI P 3, STATUS
STATUS IN 'A'
FOR END OF OP
0030 20024 0 131
SA~'"
1
SKIP WHEN COMP
.0031 P002S lAFC
JMP* LOOP
WAIT
-O-&-~fl02-6---{)-on~---------S~5---O---::...---~----- ----- '-STOP TO ZERO:BUF FROM CONSOLE
0033 P0027 DAOO
RAO FLAG
ADD 1 FLAG READ
~?4--?-{)&2-=t__f)_f"_€_B__-----------_A_l-5----11---·------------CH
P0028 FFED
~·O~-O~3*4~p~o~e~2~q~lA~F~_O~--------~2~:A*P~-----
0035
P002~
cnno
READ
LDA
=XFWMO
--eeNTlNUE-;---READ - --- --- ----- FWA-1 IN A
P002R 0031 0
003 6P-&fl2C--EfHH)--d---' -------l-M--zN$-O-l-84-------- --EQUI-F-- -3 -, -READ
P002D
OI~4
-,0037' P002F." OBOO _
NOP
r~'~R1-~Frg"lf~+-4~.1-f~H~h-~LF~~~~~;F~+-~-----·-t3-Jt-~H~-*-x-+~------G-O-S-T-li-TUS-FOR-END-·-OF- OP --875
FWMOC})
\.:_ Q42 . POQ92 0001
BZS
JIl043' ; - - - ; - END
LWPO (1)
DISK
'ri040 P003' QOOI
~<:", '>'-"
' ., ;-
-----t-Bt-JlZ~S.-----t-FWA-(~6_~---- --- -------,---
;
12-44
c
C,- 1
12.7.3
~::Q.QQ:,l;:,X:,.,:>, ,' .' c"~c~~'"'cc'
;;eeo2Pooorj-[(HlO
NA~1
LOo.
START
DISK
-N$OIBI
POOOI 0181
10003 POOO? 0844
CLR
A
EQUIP 3, FUNCTION
INITIALIZE INDEX
-I,,:p+f,O~:9ht.i't.,..,.,-Pr-A-.OA-;~O~P~,.-fo6.w;0~r+-r-----,-,----~Sr - A , - - - - - I I f - - - - - -
[;9.:~:?5'<,eRoqf4:, COQO:
/;~6~(N)6;;~g·g ,~,.~.: '~.g.~.~
.;
;0001 P0007 03FE
i0008 ?OOOA EOOO
~"" .... ·;·P0009 0182
' LOA
,
.
pJOP
JUT
-1
LDP
=N$0182
SECTOR RECORD ADDRESS
LOA
=N$460
CYL4,HEAD 6, SECTOR 0
NOP
OUT
LOQ
-1
!;'Qttl'~,;'>e.O~():J9:5Q,eJl.O
NOP
INP
r:ooiS'POOl:? 'OF43
ARS
AND
ItQOlit-::'.8.P9J}.' 02FE>JES.Ti' .,';'
1'~'~'~:7':g~i:
I
::gb
p
POQ LA 003C
..... , f ) COOO
',;,f*O.91P'QgpQ
P
-----,--,---------
=N$0002, CLEAR INTERRUPI'S
=N$0181
,~1
3
EQUIP 3, STATUS
STATUS'IN A
CHECK ON CYI..
=XMSK
STA
BUF-l
STORE AT FWA-l
LOA
-XBUF 1
LOAD -l--A-t-FWA-...-f:
L O Q E Q U I P 3, WRITE
;:POOID EOOO
~~~~~~~~~~~~~~~~~~~~_~~J_'~_ _ _ _ _ _ _ _ _ _~_ _ _~_
1'0023 P001F
P024 P0020
NOP
OUT-l
b.IHi~r--,-p-A-A-~-:-FlHHl---::--,------,-~---,--4--I-H-Q;;~---'----'---lC~~~~$IifOHl-+'8Hl~-~EQU-IF~-~3,-Sr-lcTA~A..T+UHiS~---------,---
TEST2;·
IN A
CK END OF OP
~~~~~~~~~~~~~~~~~~~~~--&fATUS
0028 P002S
,0029 P0026
k:+~9R27
.ARS
4
AND
=XMSK
ZERO
:'.TEST2 .
,'0033 P002R 6900
i
P002C 0028
STA
BUF,I
SAIv1
READ
JMP
ZERO
,SKIP WHEN COMPLETE
,CONTINUE WAITING BUFFER AREA
I
c.
j0031 P0031 0132
10038 P003? 1800
I . .... P0033 C(F6 ...
r;'Q()·.~·? . . .•. 0 .3•.':+. . . . O.() p•.O RE,4D
['00 4(»PQ 9:35'; E 0 00 c---c~---, _ _
b.
. PtHl36 f) 1 A2' ' .. '-'~.-'-.\.-"
PP.
IF COM SKIP
CONTINUE ZERO UNTIL COMPLETE
",.:
SLS
·LOQ.
=N$0182·
12-45
-------.
STOP TO CKBUFFER
EQUIP 3, LOAD ADDR
12.7.3
0042 P0039 0800
0043 Pf)03A 03FE
POO.3~ EOOO
f'003C 0.181
P003D 08QO... " ;3S,q 2Ft:
fJ003F OF43
Aoon
POO~+l .. OOOl
·0049' P()042 ,01··11··.·····
0050 P004318F7
PEADl
0051 DOO 44 C'l(H}
P004S 0056
"';1
NOP
INP
-I
TES
~'
P0040
NOP
OUT
CK 'ON CYL
ARS
3
AND
=XMSK
SAN·
"READ1
SKIP·0047 0184
NOP
. 0053 POQ480BnU
0054 P0049 03FE
l-=-----tt-o 55 PO 0 4~ F 0 0 9
~004P 0181
I 0056 P004C oRn6
1t' 057 ? 0 0 l~ C) 0 2F E
0058 P004E OF44
OUT'
I
I
TEST4
LOg
NOP
INP
'AND
\:>0050 OOPl
0060 ~0051 0111
SAN
lRF7
-1
STP..TUS IN. A
CKEND,OP
<4
=XMSK
ARS~
0059 P004F A'OOO
OO~l '~005?
NS0181
JMP*
SKIP WHEN COMP .
EXIT
TEST4,
'.- --..;')·1)42··-;2.0-0 S ;l're---1:0+-\:OH.('++,
" O,l----r.:~:-.IIXr-:l:I-l-T--~S-b.-5~--START
. 0063°0054. 1800
JMP
PO OS5 FFA-,o.
WAIT
- STOP
'BEGIN AGAIN .
__~----~n~O:HO~lr-~----~--~E~Q~'J~----~~~S~K~(H-IH)~~----~~~~~~~
'0065
. OOA6
000S~
(lOAr)
EQI)
COlJNT(96)
~n01
ASS
(1)
,-:--~61--AH1-5-=7---l}(}-64---~----.--------+»c;:;!..r-:---·-B-Y-F--+.Q.6r-t-)-------:----:-----,-----:---:-----'
0068
END
12-46
o
12.7.3.1
12.7.3.1 Address Tag Program
Write Addresses:
Every new disk pack has to have addresses written on it before it can be used for
data storage. Each sector must have an address tag. The hardware address tag
switch and the write' address function code are for writing the addresses. The
following program could be used to write tags.
NAM
*
*
*
WRITE ADDRESS TAGS
*
TURN ADDR TAG SWITCH ON * DISK IS EQUIP 3
FOR 854 CHANGE CYL EQU TO $CB
*
TAGS
o
LOOP
EXIT
EQU
ENT
0
LDA
LDQ
Nap
OUT
INQ
ENA
OUT
INQ
Nap
OUT
INQ
ENA
OUT
INQ
Nap
INP
EaR
SAZ
Nap
INP
JMP*
SLS
JMP*
END
*
*
*
EQUIP($0182) , CYL($64)
TAGS
0
=N$0102
*SEL UNIT 0, CLRINT
=XEQUIP-1
*DIR FUNC
-1
1
0
-1
5
*WRITE TAG FUNC 111
-1
-6
0
-1
1
*DUMMY DIR FUNC 001
*LAZY MAN'S BUSY CK
*F ALLS THRU WHEN BUSY
*LOAD ADDR FUNC 010
*SEEK FUNC 010
*ADDRESS 0000
-1
=XCYL
EXIT
*NEXT ADDR IN A
*FINISHED?
-1
LOOP
*GET NEXT ADDR BACK
TAGS+1
12-47
*STOP
*GO DO IT AGAIN
12.7.3.1
Usually the program to write tags is keyed in from the console rather than run in
assembly language. Therefore, it would be desirable to s h 0 r ten the program.
Error checks can be eli min ate d if the hardware is functioning properly. The
following code is used by the customer engineers:
EOOO
0182
02FE
OD05
03FE
ODF9
OAOO
03FE
18 F7
Decode the program and see what it does. A master clear sets the disk at address
0000 to begin. The program will stop on alarm when it is finished and is attempting
to write an address beyond the last cylinder (on an 853 or 854).
12. 7 • 4 Problem
Write apr 0 g ram to write zeroes on the entire disk pack after the new address
tags have been written. Include error checks.
12.8 1751 DRUM CONTROLLER
The 1751 Drum Controller interfaces with drums ranging in size from 65,536 10 words
to 8,388,508 10 words. The drum word size is 20 hits composed of 16 data bits, 1 parity
bit (odd), 1 protect hit and 2 spacing bits.
o
19 18 17 16 15
DRUM
WORD
I I II I
DATA BITS
~lc~g 1 tarity
Protect
The transfer rate for one word is 8 microseconds. All data transfers to and from the
1700 are via the DAC. The access time for the drum is 8 milliseconds, with a maximum
of 16 milliseconds.
The Q Register will be in the following format when addressing the 1751.
Q
7
11 10
15
W=O
E
································1
:::::::::::::8·::::::::::::::::
:=:::::=:::=:::::::::::::::::::::
1
12-48
o
3
D
C'
C)
12.S
The D portion of Q determines the type of information be in g sent or received in the A
Register. The INP and OUT instructions, accompanied by the Q setting, con t r 0 1 the
information flow to A (INP) and from A (OUT).
Figure 32. Interim Drum Interface Codes
~
C\1 M
000
0
0
DESCRIPTION
1700 I/O
(§(§(§ (§
Write
x x x 1
Director function
AO = Not used
A1 = 1 Clear Interrupt
A2 = Not used
A3 = 1 End of Operation Interrupt Request
Write
0
0
0
0
0
a
0
0
1
1
b
0
1
0
1
0
0
0
0
0
Initiate Operation
ab = 00 Write Data From Core
ab = 01 Write Zeros
ab = 10 Read Data to Core
ab = 11 Check Parity on Drum
Write
1
1
1
1
1
a
0
0
1
1
b
0
1
0
1
0
0
0
0
0
Load Address Register
ab = 00 Track
ab = 01 Initial Sector
ab = 10 Initial Core
ab = 11 Final Core
Read
x x 0 1
o
Director Status I
Ao = 1 Ready
A1 = 1 Busy
A2 = 1 Interrupt
A3 =. Not used
A4 = 1 End of Operation
A5 = 1 Not used
A6 = 1 Lost Data
A7 = 1 Protected
AS = 1 Parity Error
A9 = 1 Not used
A = 1 Guarded Address
10
All = 1 Timing Track Error
x x 1 1
Director Status II
Sector Address
AO - All
()
12-49
12.8.1
12.8.1 Drum Functions
When the D portion equals 0001 2 accompanied by an OUT instruction, the A Register
must be preset. The setting of A determines the function or functions to be sent
to the 1751.
A
1~~~~~~{}}}}}{}{{~~{}{}{{}{}~~}{}}f~~~~~~~~~))~~J
3
1
i
k~{~
1
1
I~r~tl
blears Interrupt
EOP Interrupt
The Clear Interrupt bit clears the in t err up t. The EOP INT (End of Operation
Interrupt) takes precedence overthe CLR INT. When the EOP bit is set, the 1751
will g e n era t e an interrupt when it has completed an operation. The remaining
bits in A are not used, therefore, they should be set to zeros.
When programming the drum the programmer first clears interrupts. If writing
in iilterrupt mode, he should also select the EOP interrupt.
LDQ
ENA
OUT
=N$0101
$OOOA
-1
EQUIP 2, DRUM FUNC
CLR INT, SEL EOP
OUTPUT FUNCTION
C~
Once the interrupts have been cleared and res elected, the programmer must tell
the controller the first word address (FWA) of his buffer area in core memory, as
well as the last word address (LWA) of the core memory buffer. This is accomplished by two D settings: D = 1100 2 denotes FWA, D = 1110 2 indicates the last
word add res s. These settings are accompanied by an OUT instruction with the
address preset in the A Register.
LDQ
LDA
NOP
OUT
LDQ
LDA
NOP
OUT
=N$010C
=XFWA
EQUIP 2, FWA
A=FWA
-1
OUTPUT ADDRESS
=N$010E
=XLWA
EQUIP 2, LWA
A=LWA
-1
OUTPUT ADDRESS
The controller then knows the area and length of the computer buffer area. Once
the con t roll e r knows the memory limits, the programmer must give the drum
area by sending the beginning track address and sector address. Both are sent
from the lower 12 bits of the A Register. The D portion of the Q Register distinguishes be tw e e n sector and track add res s: D = 1000 indicates TRACK,
2
r-'"
'\..
12-50
... '
C)
12.8.1
D = 10102 specifies sector. The programmer may select anyone of 409610 tracks.
(Note: Not all s y s t ems have the maximum number of tracks, therefore, check
your configuration.) The programmer may select one of 2048 10 sectors. (A sector is the drum address of a word within a track.)
LDQ
ENA
OUT
=N$0108
$0004
-1
EQUIP 2, TRACK ADDR
TRACK 4
OUTPUT TRACK NUMBER
LDQ
ENA
OUT
=N$010A
0
-1
EQUIP 2, SECTOR ADDR
SECTOR 0
OUTPUT SECTOR NUMBER
The controller now knows the core memory and drum memory to be used for an
operation. The programmer must now specify one of four operations. The operations are also indicated by the D setting of the Q Register in conjunction with
an OUT instruction. The four operations are as follows:
D = 0000
D = 0010
o
D = 0100
D = 0110
2
initiates a w r i t e operation. This write operation instructs the
1751 to write data on the drum from core memory.
2
instructs the 1751 to write zeros on the designated drum area. No
data is transferred from memory.
2
initiates a read 0 per at ion. The read operation transfers data
from the drum to core memory.
2
initiates a check operation. The check 0 per a t ion causes the
designated drum area to be read and checked for parity err 0 r s
without any transfer of data into core memory.
LDQ
Nap
OUT
LDQ
NOP
OUT
LDQ
Nap
OUT
LDQ
Nap
OUT
=N$0100
EQUIP 2, WRITE
-1
INITIA TE WRITE
=N$0102
EQUIP 2, WRITE ZEROS
-1
INITIA TE ZERO WRITE
=N$0104
EQUIP 2, READ
-1
INITIA TE READ
=N$0106
EQUIP 2, CHECK
-1
INITIATE CHECK
0
12-51
C~
12.8.1
The d rum at this point will be in the process of performing an operation. If the
END OF OPERATION interrupt were selected, the 1751 will generate an interrupt
when the operation is completed.
12. 8. 2 Drum Status
The programmer may take status while the operation is being performed in order
to monitor the progress of the operation. He may also take status again at the end
of the operation to verify an error free operation.
12. 8.2. 1 Director Status I
status may be requested by a D setting of 0001 2 accompanied by an INP instruction.
The status will be brought into the A Register.
LDQ
NOP
INP
15 14 13 12 11 10
! =N$OlOl
EQUIP 2, DffiECTOR STATUS
-1
BRINGS STATUS INTO A
987
Ir:::mI
654
3
2
1
0
+
INT
t
+
Ready
111 11 kmm 1tIIl1 11 11 I
+
Parity
Error
1+
Lost
Data
+
EOP
c
Busy
Protected
A 1 in the corresponding bit indicates that the stated status exists. For example,
a 1 in bit 11 indicates a timing track error.
Timing Track Error
Bit 11 is an error in the timing track which insinuates a hardware problem.
The programmer should attempt the 0 per a t ion three or four times before
accepting the status as a hardware failure.
Guarded Address
Bit 10 indicates that a core to drum transfer was attempted to a track with an
address lower than the one set on the track protect switch.
Parity Error
Bit 8 indicates that the parity was not odd, i. e., it did not have an odd number of one bits in the word.
12-52
c
12.8.2.1
Protect
Bit 7 indicates that the protect switch on the drum has been set.
Lost Data
Bit 6 in d i cat e s that data was not transferred from the controller's holding
register before new data was read into the register.
EOP
Bit 4 notifies the programmer that an operation has been completed.
Interrupt
Bit 2 indicates that an interrupt has been generated by the 1751.
Busy
Bit 1 ind i cat e s that the 1751 is in the process of performing an operation.
Ready
o
Bit 0 indicates that the controller is in a ready state.
12.8.2.2 Director Status II
The programmer may also request the 1751 to send the current sector address of
the drum to the lower 12 bits of the A Register.. This is accomplished by setting
D = 0011 and executing an INP instruction.
2
LDQ
=N$0103
EQUIP 2, SECTOR STATUS
NOP
-1
INP
INPUT SECTOR ADDRESS
12.8.3 Programming the Drum
In summary, the programmer must first clear interrupts and select desired interrupts. Once this has been issued, the programmer notifies the 1751 of the first
word address and the last'word add res s of core memory. Then, he must send
the track and sector addresses of the drum. Finally, he specifies the operation
to be performed. Status may be taken d uri n g the operation to monitor the progress and should be taken at the end of the operation to confirm that the operation
was performed correctly.
o
When data is being written on or read from the drum, the track address is automatically incremented when the sector address overflows to the next track.
12-53
12.8.3
Also, the Write Zeros and Check Parity functions operate on a specified area of
the drum. Since only a beginning track and sec tor address were specified, the
core address must be sent also to indicate the number of words, even though the
data in core is not involved in those operations.
Example:
The following is a test program for the drum. It writes 100 words from a buffer beginning at FWA, on the drum beginning at track 4, sector o. It then checks
drum parity on the data written and reads it back in.
To operate the program, the initial buffer should be set to all one bits from the
console. The STOP switch should be set, and the program will stop before the
Read. The buffer should then be cleared from the console. By setting the STOP
switch again and continuing the RUN, the read will be done and the program will
stop. Then the buffer can be swept from the console to see that the data was read.
Note that the drum controller must be dialed to equipment #2 and that the drum
address registers and memory address reg is t e r s must be reset before each
operation.
Note also the nifty coding at lines 0026 - 0030 to jump different places on a flag.
c
c
12-54
c)
12.8.4
12.8.4 Drum Example Program
OOOl
0002
OOOJ 120000 0000
0004 POOOI OAOI
O()O~
POoo~
b)~II~
~~lf
0006 POOO3 OA02
0001 P£lO()4 EOOO
POOOS 0101
OOOB ~OOO6 OBOO
0009 POO07 03FE
OOJO ROOoa COIlO
POOO~
0
C)
00] 1 ROOOA
POO08
0012 poooe
0013 POOOO
0014 ROOOI;;
POOOF
0015 ROOIO
POOll
001~ ROO12
0017 POOl]
OOla ~OO14
POOl5
00]9 eOO]6
POO17
0020 POOl~
0021 POOl9
0022 eOO1{A
POO1B
0023 eOOlC
POOID
002?:!: eOOlE
0025 POOIF
0026 EO(}2D
0027 POO21
0028 eOO22
0029 POO23
0030 e002!±
0031 P0025
0032 e0026
P0027
0033 eOO28
0034 P0029
0035 EW02A
POO28
0036 eOO2C
0037 P0020
0038 e002f
0039 P002F
009:0 EOO3!)
0041 P003l
OO{t2 ~OO32
0043 P0033
e0034
O~IIM
~IOM
ENT
DRUM
0
()
FIRST JMP TO WRITE
ENA
1
S:J: Ai~
E:L..AG
ENA
bDO
$0002
CLEAR CONTROL
-~1$0101
EQYIP 2 I)IR FYNG
M08
MEM
OUT
LOA
-1
-~EWA
BIIEEEB
LOa
-~$O]OC
EWA(CORE) EIINC
l)03E P
EOOO
OlOC
O~OO
~I08
03FE
OUT
L.OA
-1
bDO
-~I$O
MOR
OUT
bDA
-1
-~1$4
TBACK
L OQ
=~I$Ol08
XR ACT<: ADDR
cuon
OOA1 P
EOOO
OlOE
1)800
03FE
Goao
A6HH~
0004
EOOO
-~EltJA
±99
1 OE
!,W.A
I,WA(COBE) EIINC
~IINC
0108
Q~()O
~JQR
03FE
rooo
0000
Eono
OIOA
OUT
IDA
-1
-~IO
SECTOR
I DQ
-~$O]O~
SECTOR ADDR FUNC
O!:H!U
~Ioe
03FE
] CII D
0000
OUT
FLAG
O{}25 e
0033 P
() ()
'~8
OAOO
EOO(l
0100
0800
03FE
EOOO
0101
(lBOO
02FE
OfCS
0131
lBEC
D8EF
-1
SlCDO
0
0
~DC
WH I IECHECK
ADC
e
WRITE
~DC
HE~D
ENA
L.D (l
0
-~I$O
JMP* CO}
WHERE TO JUMP
100
WRITE DATA
10]
DIR EIINC
~Ioe
SIAr
OUT
Loa
-1
-~I$()
~Ioe
INP
5
SAM
IMe*
RAO*
~I
U~H~*
IBli5
EOOO
0106
~IIIM
CHECK
LDQ
-1
]1
1
SIAI±3
FLAG
MEM
=N$0106
12-55
INP STATUS
CK EOP
SKIP ON EOP
WAIT ON EOE
NEXT JMP
GO BEINIXII\LIZE
CKPAR E~R ON DRUM (ONLY)
12.8.4
00', i, rOO3S 01300
0045 POO36 03FE
0046 rOe31 181'2
0047 P0038 0000
e OllB
POO39
Nor
OUT
SLS
-1
SfAf
0
1::89
~~!J,
;:H1r~
READ
E{HH~
GO
13lAI~
ON EOP
CLEAR BUFFER FROM
01 QII
REA;g
CON~
~:gNQ
POO3A 0104
ggll9
rgg~H
QtHHI
~J8P
0050 POO3C 03FE
0051 POQ39 (HHlQ
0052 P003E 0004
0053
OUT
Dr~UP1
I
Q 0 FF
WRITE
0025P STAT
-1
S~OP AF~ER
51::5
FWA
QOQQP
BZS
FII/A(100)
~~m
9RbI~4
~4E~4
002AP CHECK
QOQ8P
SET BUFFER TO 1 ' !
0021P
AgDr~
0033P READ
RE A;g
0038P FWA
003EP
c
La Jolla..-September 1968
('
\. --
12-56
o
12.9
12.9 1731/601 MAGNE TIC TAPE
The 1731 magnetic tape con t roll e r is used with 601 tape transports. A maximum of
eight 601's may be connected to one 1731. Buffering may be accomplished via the 1706.
The 601 is a 7-track t ran s p 0 r t capable of reading or writing at 200 or 556 Bits Per
Inch (BPI). The tape is moved at a rate of 37 1/2 inches per second.
Reading and writing may be done in either Binary or BCD codes. The 601 accepts six
bits of data and generates parity for the 7th bit. The parity will be odd for binary and
even for BCD.
The data is arranged in groups of records and files. Consecutive frames of information
con s tit ute a record. A record may consist of a minimum of one frame. A file is a
group of records with the minimum being one record. Lon g it u din a 1 parity (even) is
generated on each record and stored four spaces past the last data character. A record
gap is 3/4' of unrecorded tap e surface which denotes the end of a record. A BCD 17 8
code is placed six inches from the last record to indicate the end of a file.
C)
Each time a character is written by a 601, it transfers the character to the 1731 which
checks the parity. If the parity is inc 0 r r e c t, the Parity Error status is set and an
alarm interrupt is generated. (Note: The alarm interrupt will be generated only if the
programmer has selected this interrupt.) The controller also checks for correct parity
on a read operation.
The Q Register will be in the following format when programming the 1731.
15
11 10
7
6
2
1
0
.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:
QI,-_~_ _L_~_~I::::::::::~::::::::::·.:~::::::::::~:::::::::::~::::::::::I~D~1
....................................................
The W field will always be zero when going to the 1731. This field will be used for
programming the 1706 which will be discussed later. The E specifies the equipment
number of a 1731. The equipment number corresponds with a switch selection on the
1731 ranging from 0 to $F. (Check the equipment setting for your site.) The D fie 1 d
specifies a command.
12.9.1 D = 00 MT Data
This setting specifies a data transfer. A write operation is indicated by an OUT
instruction. The write sends the lower six bits of A to the 1731 which generates
parity and writes the data and parity on the tape. Whenever the computer breaks
the continuity of the character outputs, the controller initiates an End of Record
sequence. If no new control functions are iss u e d after the end of record is recorded, tape motion stops.
C)
An INP instruction with D = 00 denotes a Read 0 per at i 0 D. The read operation
transfers data from the tape to the controller. The controller checks parity and
12-57
12.9.1
sends the 6 data bits to the lower 6 bits of the A Register. The 1731 stops sending
data to the computer when the computer stops requesting data or when the End of
Record is sensed. Tape motion will not terminate except when the End of Record
gap is sensed.
If the 1731 is connected to the 1706, the data will be buffered into the computer's
memory. The lower six bits of each word in the buffer area will con t a in data.
The A Register will contain the FWA-1 of the buffer area for both read and write
ope rat ion s, therefore, the data transfer will always be initiated with an OUT
instruction. The FWA-1 in memory must contain LWA+1 of the buffer area.
c
12-58
o
12.9.1
Figure 33. 1731 Functions
D
COMPUTER INSTRUCTION
Input to A
Output from A
00
Write
Read
01
Control Function
Director Status I
10
Unit Select
Directo"t' Status II
-
(A) - Control Function
NOT USED
ALARM I NTERRUPT REQUEST
END OF OPERATION INTERRUPT REQUEST
DATA INTERRUPT REQUEST
CLEAR INTERRUPT
~ ;LEAR CONTROLLER
MOTION CONTROL
NOT USED
15
+
11110
I1
j
~
71
~~~~----~--5~1-4~13~1-2~11~1~01
6
1
o
\
I
I
Bits 10-7
of A
Motion Function
0001
0010
0011
0101
1000
1100
Write Motion
Read Motion
Backspace
Write File Mark
Rewind Load
Rewind Unload
(A) - Unit Select Function
NOT USED
SELECT
TAPE UNIT
l
115
121"11019
1
BPI
SELEC.T
BPI
SELECT
BPI
BINARY
BCD
[
0 - 7
SELECT TAPE UNIT
DESELECT TAPE UNIT
NOT USED,
~
200
556800
1l i
700514131211101
,NOT USED
12-59
12.9.2
12. 9.2 MT Functions
12. 9. 2. 1 D = 01 Control Function
This D setting, accompanied by an OUT instruction, indicates that the A Register
contains control functions. The control function gives the programmer the capability of clearing interrupts, c 1ear in g the controller, selecting interrupts, and
establishing motion control. All control functions may be issued together. The
pro gr amme r is allowed to select three interrupts: Data, Ala rm and End of
Operation.
15
11 10
6
7
543
2
1
0
ktfittl I
MotionA.......
Co-n-tr--..ol
111 t
bLR Controller
CLR INT
Data INT
EOPINT
Alarm
0001
Write Motion
Sets the write logic in the selected 601. Once the logic is set, a data
transfer function must be sent with an OUT instruction in 0 r de r for
the data to actually be written on tape.
0010
Read Motion
Sets the read logic within the selected 601. A data transfer function
must be sent with an INP instruction in order for the data to be transferred to the A Register.
0011
Backspace
Causes the 601 to backspace one record.
0101
Write File Mark
Write file mark generates six inches of blank tape followed by a 17 8 •
When the end of file mark is w r itt e n or read, longitudinal parity is
checked. If the controller is in binary mode, a parity error will be
generated, as the 17 8 is in BCD mode (even parity).
1000
Rewind Load
The rewind controls bring the tape back to the mag net i c load point
indicator. The ready status stays up without any manual intervention.
12-60
C
12.9.2.1
1100
Rewind Unload
The rewind load keeps the ready status while the rewind unload causes
the 601 to drop ready.
12. 9.2.2 D = 10 Unit Select Function
Allows the programmer to select the desired 601, density, and mode, when accompanied by an OUT instruction. The 601 tape units can read at 200 and 556 BPI.
The deselect function, bit 11, is used to deselect a protected 601 in order that an
unprotected program may "get access to the 1731 to use an unprotected 601.
15
12 11 10
9
7
6
5
4
j 1
Deselect Tape Unit
'---------v---'J
Select Tape Unit
Tape Unit 0-7
o
1
3
2
1
0
1 tm~~D
Bits in A
Register
Select 800 BPI
Select 556 BPI
Select 200 BPI
The Select Tape Unit, Bit 10, indicates that the unit number in Bits 9-7 is to be
the desired unit. If Bits 10 and 11 are not set, the controller ignores Bits 7-9.
12. 9. 3 MT Status
12.9.3.1 D = 01 Status I
This D setting brings Director Status I into the A Register when accompanied with
an INP instruction.
15
A
13 12 11 10
I~~~~~~~~~~~~~/~~~~~~/~~~~I
9
I I
til 1
8
7
6
5
4
3
o
12-61
1
0
I I
I I I
Controller Active
File Mark
'
Load Point
End of Tape
Parity Error
Protected
2
t
1
1
Ready
Busy
Interrupt
Data
End of Operation
Alarm
Lost Data
1
c
12.9.3.2
12.9.3.2 D = 10 Status II
Director Status II is requested with this D setting on an INP instruction.
15
5
4
3
2
1
o
I
•
556 BPI
800 BPI
12.9.4 Magnetic Tape Example Programs
12.9.4. 1 . MT Example 1
The following is a test program for a 601 magnetic tape on a 1731 controller. (It
could also be used for a 608 tape on a 1732 controller.) The program generates
200 frames of data in the ARe g i s t e r and outputs 1 frame at a time (the lower
order 6 bits of A) to the tape unit. The pro g ram then backspaces the tape and
reads the data back in, s tor in g it in the buffer DATA. Each frame of data occupies the lower 6 bits of a word in the buffer.
The program can be run with the STOP switch set. It will stop when finished, and
the buffer can be swept from the console. One cannot "step through" the program
because the tape is moving as soon as the first tape motion command is issued.
12-62
C=
12.9.4.1
0
USEL
WRITEMO
DATA
BACKSP
0
READMO
RDDATA
STOP
DATA
NAM
LDQ
LDA
Nap
OUT
INQ
LDA
Nap
OUT
LDA
STAINQ
LDA
Nap
OUT
RAOLDASAZ
JMP*
INQ
LDA
Nap
OUT
LDA
Nap
OUT
LDA
STAINQ
Nap
INP
STA*
RAGLDASAZ
JMP*
SLS
BZS
END
MT601
=N$0382
=N$0494
Q382
EQUIP 7, UNIT SE L
UNIT1, 556BPI, BIN
-1
-1
=N$81
Q381
MOTION FUNC
WRITE MOT, CLR CaNT.
-1
=N-200
I
-1
=N$FF
-1
I
I
BACKSP
DATA+3
1
=N$0180
200 FRAMES
Q380
DATA FUNC
DATA 3F
Q381
MOTION FUNC
BACKSPACE
-1
=N$0100
READ MOTION
-1
=N-200
I
-1
Q830
-1
DATA+200, I
DATA FUNC
STORE DATA
I
I
STOP-*-l
RDDATA+1
0
DATA(200)
o
12-63
SWEEP BUFFER TO CHECK
12.9.4.2
12. 9.4.2 MT Example 2 - With Error Checks
This test program for magnetic tape is the same as Example 1, with the addition
of error checks. Note that the program never hangs in a loop on a reject.
NOP
OUT
-1
Instead it jumps to REJINT for any internal reject or REJEXT for any external
reject. Even with no error analysis, note that con side r ably more coding is
required just to allow for errors. Also note that the program is con tin u all y
waiting for the tape.
The program will stop either on normal termination or after a reject. It can be
restarted after a reject by simply correcting the error condition and setting the
RUN switch.
This particular program has been run with the 1706 code set but it is still an unbuffered operation. The site where it was run had their magnetic tapes connected
through the 1706, but the Direct Storage Access line was not also connected so
operations simply went through the 1706 in unbuffered mode.
c
C~'
12-64
12.9.4.2
(j
Select
lrite
/lotion
o
Status
Data
Ready?
Output
Data
Busy?
0
0001
0002 POOOO
POOOI
0003 POO02
POO03
0004 POO04
0005 POO05
0006 POO06
0007 POO07
0008 POO08
0009 POO09
POOOA
0010 POOOS
POOOC
0011 POOOD
0012 POOOE
0013 POOOF
0014 POOIO
0015 P0011
0016 POO12
POO13
0017 POO14
0018 POOlS
POO16
0019 POO17
0020 POO18
0021 POO19
0022 POOlA
0023 POOlS
0024 P001C
0025 POOI0
0026 POOlE
0027 POOIF
0028 P0020
P0021
0029 P0022
0030 P0023
0031 P0024
0032 P002S
0033 P0026
0034 P0027
0035 P0028
0036 P0029
0037 P002A
P002B
0038 P002C
0039 P002D
P002E
0040 P002F
0041 P0030
0042 P0031
0043 POO32
0044 P0033
0045 P0034
P0035
EOOO
1382
COOO
0494
0302
1804
58bA
5861
18F 7
EOOO
13E:H
COOO
0081
0302
1804
5861
5858
18F7
COOO
FF37
60FF
EOOO
1381
0202
1804
5857
S84E
18F9
OFCC
0131
18F6
ODFE
COOO
OOFF
0305
DOFF
COFF
0104
18EE
5849
5840
18E8
EOOO
1381
0205
AOOO
0002
0104
18F9
583F
5836
18F6
EOOO
1381
A
A2
NAM
LOQ
TEST
=N$1382
LUA
=N$0494
OUT
JMP*
RTJ*
RTJ*
JMP*
LOU
2
LDA
=N$OO81
A2
REJINT
REJEXT
A
=N$1381
1706
EQUIP 7
UNIT SEL
UNIT 1, %%¢ BPI, BINARY
GOOD
INTERNAL REJECT
EXTERNAL REJECT
RETURN AFTER REJECT
CONTROL FUNCTION
WRITE MOT - CLR CONTROL
A4
OUT
JMP*
RTJ*
RTJ*
JMP*
LDA
STALDQ
I
AS
INP
JMP*
RTJ*
RTJ*
JMP*
ALS
SAM
JMP*
INQ
LOA
2
ASS
REJINT
REJEXT
AS
12
*+2
AS
OUT
RAOLDASAL
JMP*
RTJ*
RTJ*
JMP*
LDQ
5
INP
AND
5
zN$2
SAl
JMP*
RTJ*
RTJ*
JMP*
LOQ
A9-"-1
A7
REJINT
REJEXT
A7
=N$1381
ASS
OUT
A7
A9
2
A4
REJINT
REJEXT
A2
=N-200
=N$1381
-1
=N$FF
I
I
A7-"-1
AS
REJINT
REJEXT
AS
=N$138l
12-65
EOR 200 FRAMES
DIR STAT 1
STATUS
DATA READY?
WRITE DATA FUNC
0000 0000 1111 1111
GO STATUS AGAIN FOR DATA READy
DIR STATUS 1
CHECK BUSY
SKIP WHEN NOT BUSY
CONTROL FUNCTION
12.9.4.2
Backspace
Busy?
Read
Motion
E-7
Data
Ready?
Input
Data
External
Reject
0046 P003b
P0037
0047 P0038
0048 P0039
0049 POO3A
0050 P003B
0051 P003C
0052 P003D
P003E
0053 P003f
0054 P0040
0055 P0041
0056 P0042
0057 P0043
0058 P0044
0059 P0045
0060 P0046
0061 POO4·/
P0048
0062 P0049
0063 P004A
0064 P004B
0065 P004C
0066 P004D
0067 P004E
POO4f
0068 POOSO
0069 POOSI
POOS2
0070 POOS3
0071 POOS4
0072 POOS5
0073 POOS6
0074 POOS7
0075 POOS8
0076 P0059
0077 POOSA
0078 POOSB
0079 POOSC
0080 POOSO
0081 POOSE
POOSF
0082 P0060
0083 P0061
0084 P0062
0085 POO63
0086 P0064
0087 P0065
0088 P0066
0089 P0067
0090 P006B
0091 P0069
P006A
0092 P006B
0093 P006C
COOO
OIBO
0302
1804
5836
5820
l8f7
EOOO
1381
0202
1804
582f
5826
1801
OfCE
0121
18f6
COOO
0100
0302
1804
5825
S81e
18Ef
eooo
Ff37
60FF
EOOO
1381
0202
1804
5818
5812
18F9
OfCe
0131
18F6
OOFE
OAOO
0207
6900
00E2
DOff
eOFF
0104
18EO
S80e
5803
18EA
0000
0000
EOOO
1381
OBOO
02fE
All
INP
AlII
LOA
LOA
=N$0180
BACKSPACE
OUT
JMP*
RTJ*
RTJ*
JMP*
LOQ
2
All
REJINT
REJEXT
A9
=N$1381
DIR STATUS 1
2
JMP*
AlII
RTJ*
REJINT
RTJ*
REJEXT
AlII
JMP*
14
ALS
*+2
SAP
JMP*
All
=N$0100
A13
OUT
JMP*
RTJ*
RTJ*
JMP*
LOA
2
A13
REJINT
REJEXT
All
=N-200
STALOQ
I
A14
A44
A16
REJEXT
INP
JMP*
RTJ*
RTJ*
JMP*
ALS
SAM
JMP*
INQ
ENA
INP
STA
=N$1381
2
A44
REJINT
REJEXT
A14
12
*+2
A14
-1
0
7
OATA+200.1
RAOLOASAZ
JMP*
RTJ*
RTJ*
JMP*
SLS
0
LOQ
0
=N$1381
NOP
INP
-1
12-66
C
BUSY?
SKIP WHEN NOT BUSY
SEL READ MOTION
STATUS
C
WAIT FOR DATA READY
INPUT DATA
STORE DATA NOT
ASSEMBLED
I
I
A16-*-1
A14
REJINT
REJEXT
A14
STOP WHEN THROUGH
EXT REJ
TAKE STATUS
AND STOP
C
12.9.4.2
o
0094
0095
0096
0097
0098
0099
0100
0101
0102
0103
0104
0105
0106
P006D
P006E
P006F
P0070
P0071
P0072
P0073
P0074
P0075
POO76
P0077
P007B
P0079
EBFA
0000
lCF8
0000
EOOO
1381
0800
02FE
EBFA
D8F9
0000
lCF7
ooca
LDQ*
SLS
JMP*
REJINT
0
LDQ
NDP
INP
LDQ*
RAD*
SLS
JMP*
BZS
REJEXT
0
(REJEXT)
0
-N$13Bl
-1
REJINT
REJINT
0
(REJINT)
DATA(200)
END
0
Lockheed - September 1968
o
12-67
RUN TO RETURN
INTERNAL REJECT
TAKE STATUS
AND STOP
RUN TO RE TURN
DATA BLOCK
12.10
12.10 1732/608-609 MAGNETIC TAPE
The 1732 controller for 608 and 609 Magnetic tapes is very similar to the 1731 and can
be programmed in identically the same way as the 1731. For that reason, a separate
program for the 1732 is not included here. Instead, the 1731 program was run on the
1732/608.
The 1732 provides an additional feature which was not available on the 1731: option for
selecting assembly/disassembly mode. This means that two frames at a time can be
sent to or received from the controller in one OUT or INP (consequently meaning the
controller has to be accessed half as often). The controller takes care of assembling
or disassembling the frames on the tape. Bit 6 (not used on the 1731) in the function
code is used to select this mode.
This is especially useful on the 609 (9-track tape) in that two 8-bit frames exactly fit
in one 16-bit 1700 word. Repacking the buffer· can be eliminated since a word at a
time is sent to the controller. The 609 uses only 800 BPI density, and normal end of
files are not used on it. For example:
• Load 601 MT program from lockheed (or reassemble with changes).
• Clear 1706 code from all Q addresses - MT's are not on 1706 (i. e., change $1382
to $0382)
• Change P0003 to:
$4D4 for 608 (adds selection of assembly)
$4CC for 609 (800 BPI only, assembly)
c
• Change P0021 to FFFF
• Follow operating instructions on 601 program
• Output from A will be (in assembly/disassembly):
608 - bits 8-13 and 0-5
Ix X I
I I I I I
Ix X I
I I I I II
"----v---J ~
609 - bits 8-15 and 0-7
v--------I
II I I I I I I III I I I I I I I
,
• Input to A will be:
'V'
I\.
I
608
100 I
I 11100 I II I I II
609
II I I
I I III I I I I I I
II
• The upper bits in A are the first frame; the lower bits are the second frame.
12.11 1706 BUFFER DATA CHANNEL
The 1706 is a 16-bit, bid ire c t ion a 1, buffer channel with word transfer rates up to
900 KC (approximately 1. 1 microseconds per 16-bit word).
The 1706 buffers data between the computer's memory and a peripheral. The 1706 is
capable of buffering as many as eight devices. The 1700 system may have three 1706's
attached.
12-68
C·
12.11
The 1706 has no indicators nor control panels, therefore, all operations are initiatad
by the computer via the A/Q channel. The 1706 is considered as one of the eight devices
attached to the A/Q channel and the DSA channel with each peripheral connected to the
1706 being a substation. Consequently, only one of the 1706's peripherals may be
referenced at a time.
The program requests direct access to a peripheral via the 1706 to establish the logic.
Once the logic has been established, the program requests the 1706 to perform the data
transfer.
Bits 11-15, the W field, of the Q Register are used to reference the 1706 and to indicate the desired operation. Bits 0:-10 of the Q Register will contain the same bit setting
used to reference a particular peripheral when it is not attached to the 1706.
11 10
15
Q
W
V'
I
I
7
S
E
\
D
I
'V'
Peripheral
1706
o
0
6
It is possible to perform direct I/O on a device connected to the 1706 simply by setting
W to 00010 and sending all the codes for the device thru the 1706. (However, normally
if a device is on the 1706, it is desired to perform data transfers in a buffered mode
by letting the 1706 perform the operations.)
12. 11. 1 1706 Functions
The setting of the W field is dependent upon which of the possible three 1706's the
program is referencing. There are four settings for each 1706.
COMPUTER OPERATION
W SETTING*
1706
#3
1706
#2
1706
#1
1.
oC
07
2.
oD
3.
4.
INP
OUT
02
Direct Input
Direct Output
08
03
Terminate Buffer:
Current Addr of 1706
Function
oE
09
04
1706 Status
Buffered Output
of
oA
05
1706 Current Addr
Buffered Input
* The left digit is binary, the right digit is hexadecimal.
C)
12-69
12.11.1
The first W setting provides the computer direct access to the peripheral. The
peripheral may be requested to send to the A Register a data word or status word.
The computer may send to the peripheral a function or data word from the A Register. This mode of operation is identical in every way to that on the A/Q channel.
12.11.2 Programming the Peripheral Through the 1706
The 609 magnetic tape unit shall be used as an example with 1706 number 1. It is
neces sary to set up the equipment prior to tell in g the 1706 to do any I/O on the
equipment.
LDQ
=N$1202
DIRECT OUT
LDA
=N$4CC
SEL UNIT 1, ASSEMBLY,
SOO BPI, BIN
NOP
OUT
-1
INQ
-1
PREPARE FOR TAPE MOTION
LDA
=N$80
WRITE MOTION
c
NOP
OUT
-1
The 609 tape unit has now been functioned. The next step is to function the 1706,
requesting it to interrupt the computer when the data transfer is complete. (This
is if the 1706 will be operated in interrupt mode.)
LDQ
=N$1S00
1706 FOR FUNCTION #3
LDA
=N$S001
INT ON EOP
-1
1706 IS FUNCTIONED
NOP
OUT
The 1706 and the peripheral have both been functioned. The next step is to initiate
the I/O operation. At this point the 1706 will take over and do the data transfer.
It will now be impossible to directly access the peripheral until the 1706 is finished
or becomes hung up.
The 1706 expects to find the First Word Address minus one (FWA-1) of the buffer
area in the A Register when the I/O operation is in it i ate d. Upon receiving the
FWA-1 the 1706 goes into the computer's memory and extracts the Last Word Address plus one (LWA+1) from that location. The 1706 then updates the FWA-1 by
1 until it equals the LWA+1 at which point the data transfer is complete.
12-70
c
12.11.2
0
LDA
STA
LDQ
LDA
NOP
OUT
=XLWA+1
FWA-l
=N$2200
=XFWA-1
LAST WORD ADDR + 1 IN A
LWA=1 AT FWA-1
BUFFER OUT. EQUIP #4
FWA-l IN A
-1
OPERA TION INITIA TED
The program at this poi n t may exit and wait for the End of Operation interrupt.
Two other alternatives are available: s tat us for End of Operation or status for
current address.
LDQ
=N$2200
STATUS 1706
INP
-1
STATUS IN A
ALS
11
EOP BIT AT SIGN BIT
SAM
CMP
WHEN SET OP COMPLETE
JMP*
STAT
WAIT UNTIL COMPLETE
LDQ
=N$2AOO
CURRENT ADDR, EQUIP 4
INP
-1
CURRENT ADDR IN A
SUB
=XLWA+l
SUBT LWA+l
SAZ
CMPI
ZERO, OPERATION CMP
JMP*
STADR
CONTINUE STATUS FOR ADDR
NOP
STAT
CMP
0
NOP
STADR
CMP1
12.11.3 1706 Status
Once the data transfer is complete, the program may process the data. The program may at any time status the 1706 for the current address and for the 1706
status word. The program may check the status word for the following information.
15
A
10
9
8
7
i
o
6
5
4
3
2
1
0
((....-.-r-;"((.~{}-;-;-;-:-}{~}\~\}~:-:-:-:-l{q.-.-------r:"'""r·:-,-,-,--;·:-1
.......
------rrrrr~..........,...,---r----r-___,
[t] 1·········1 1 1 I
I,.............,}(...............
Device RePl)
Device Reset
Program Protect Fault
12-71
1
+
EOP
1I
+
Ready
Busy
Interrupt
Note that this is the status of the 1706, not the peripheral. It is not possible to
get the status of the peripheral while the 1706 is working on it.
Ready (Bit 0
= 1)
c
This bit is set when power is on.
Busy (Bit 1 = 1)
This bit is set from the tim e the 1706 accepts
an output w 0 r d from the computer initiating a
block transfer until the b 10 c k transfer is terminated, or during a direct operation.
Interrupt (Bit 2 = 1)
A buffer transfer input or output has been completed.
Program protect fault (Bit 6=1) --. A reference to computer storage caused a program protect fault.
Device Reject (Bit 8 = 1)
---~..
This bit, if set, means the peripheral de vic e
rejected the last word transfer attempted from
the 1706.
Device Reply (Bit 9 = 1) -'----.. This bit, if set, means the peripheral de vic e
accepted the last word transfer attempted from
the 1706.
It is possible for the 1706 to get hung up as it continually rep eat s an attempt to
make a data transfer to the peripheral if the peripheral fails.
The program may status and find a Device Reject status. If this condition were to
arise, the program may terminate the buffer operation. This t e r min a t ion is
always necessary when the buffer becomes hung up. When the operation is terminated, the current address is sent to the A Register automatically.
LDQ
NOP
INP
=N$1AOO
TERMINATE BUFFER, EQUIP 4
-1
CURRENT AD DR IN A
12.11.4 Summary of 1706
In summary, the computer functions the peripheral direct via the 1706. Once the
peripheral is functioned, the End of Operation interrupt is requested. The program
must have the LWA+1 at the FWA-1 prior to initiating a buffer operation. When
the buffer operation is initiated, the FWA-1 is in the A Register and sent to the 1706.
The status word of the 1706 may be requested anytime as well as the current address. The program cannot status the per ip her a 1 itself until the operation is
completed or terminated.
12-72
c
o
12.11.5
12.11.5 1706 Example Program
Example:
The following is a test program for a 609 magnetic tape on a 1732 controller, operated in buffered mode by the 1706. The program outputs 50 words of data from
the buffer beginning at BUF+1, rewinds the tape, and reads the data back in.
The buffer should be set to all one bits from the console. Then the program should
be operated with the STOP switch set so that the program will stop after writing
(to allow the programmer to clear the buffer from the console). After reading,
it will stop again where- the buffer can be swept to see the data.
o
12-73
12.11.5
OO'H
0002
loog
(HlOJ
0004
leuo
OOO~
~I~O
0006
QQg1
OOOR
gggq
0010
gQll
0012
0013 ROOOO
POOOI
0014- 1=10002
0015 POOO3
001~ QOOO4
POO05
0011 ROOO6
POOO7
0018 ROOO8
0019 POOO9
0()20 POOOA
0021 POOOH
8000C
0022 POOOO
28UO
1281
OA01
03FE
gooO
12b2
992~
8dr~
pggg~
0024
0025
002p
0021 ROOOt::
/
POOIO
002S POOll
POO12
0029 ROO13
0030 POO14
0031 800]5
0032 POO16
0033 ROOIZ
0034 PO 0 U:~
0035 ~OOl~
0036 POOIA
0031 ~OOIB
POOle
0038 8001[1
POOlE
0039 e001E
0040 POO?O
OO~]
~OO21
POO?2
00~2 80023
0043 POO24
-
-
00~4
~OO25
00~5
P0026
eOO2-l
POO28
0
\};?~Q
Mlb09
E;QtJ
E;QIJHH
C-',
MT
QIIlOb ($1 01l0)
FLJN06($lBOO)
1;i11t::O!) ($2000)
RUFIN($2800)
./
DlREC± QU±
FUNCTION
BtwFER QtJ± GR
BUFFER IN
17J2 EQYIP #4
~;;HW)
~±A±g:~
*
:!l:~~+
!:Jy~~g~
+0
Qt>jg,,~
~RQ~I
CQt>JSObE.
*SET STOP SWITCH
:II:
~O(JO
*
Ml
bOO
e;~J
A
- X0 II I (} 6 + E(lll I e + 1
DIRECT OIlT
1
CL~
CON~~OLLER
OUT
bOQ
-XOlll06±E(JIII e±2
DI~ECX
COIlO
bOA
-tll$4CC
04CC
0800
03FE
SEL UNIX 1, ASSEMBL¥,
800 bpi, BINARY
OUT
-1
BIQ
-1
LOA
=N$BO
-1
~Ioe
oQ~' E;
COUO
OIlX
WRITE MOTION
(lOBO
0800
NOP
gbl+
1
goOO
2280
COIlO
OOcC P
bDO
HERE IS WHERE NORMALLY WE
SEt EGP Im AN:9
OUTPUT IT
-)(BIIE06±EOllle
BYFFER GYt
bOA
-XSIIE
()~OO
t:>I08
OUT
-1
*
*
*
G3FE
IlBOO
SIAl
02FE
(lECS
0131
OOuo
EOOO
12Bl
CIIIII)
0400
OI:3I1U
03FE
CODA
0100
OBOO
03FE
E' 0 (I (I
2A80
COOO
(102C P
992G P
0051 P002C OO~F P
g8SF P
9052
0053
~tjGYlJ)
~-lA
C'
1
~oe
INP
ilLS
SAM
IMe*
SLS
LD(l
18£:13
9 9 £1/, P(J·921~ 8H~e
0047 POO?A U3FE
9 g'lf=! P8928 09UlJ
0049 POO2C 0033
995(:)
t:>IAM
ENT
1;:011
EQU
!;:QII
EQU
LDCI
-1
1]
i~+2
INPUT STATUS
FGR EGP
EOP IMPLIES GOOD PARITY
~,\I±
SIAl
a
-XOII!06:tEQllle±]
=~1$400
CLEAR BUF FROM CONSOLE
DI~EC~
OUI
REHIND
~A~E
~IO~
OUT
IDA
-1
=rJ$)OO
READ MOTION
I [} (;)
-1
-XBIIEHJ+EQI1I2
BIIEEEB IN
LDA
-l':BIIE
EWA-l
~Ioe
OUT
~WP
BUF
OUT
SLS
RZS
ORC
ADC
-1
9
BlJF(51)
OYF
BUF+Sl
onc~;
END
1 CONTROL WORD,
SO DAtA wORDS
PUT LWA+l IN FWA-l
C
12-74
o
CHAPTER XIII
PERIPHERAL PROGRAMMING - II
o
II
o
('
. -..
.
CHAPTER XIII - Peripheral Programming II
l'l
TOPIC
",/
o
PAGE
13.0
Introduction
13-1
13.1
Initiator Section of Driver
13-1
13.2
Interrupt from Equipment
13-1
13.3
Common Interrupt Handler
13-3
13.4
Interrupt Line Processor
13-3
13.5
Continuator Section of Driver
13-3
13.6
Error Section of Driver
13-4
13.7
Summary
13-5
13.8
ADSD Bulletin, Number 4
13-7
13.9
Listing of Interrupt Handler
13-12
13.10
Lis ting of Dispatcher
13-13
· \.
13.0
r'
.
""\...-)
13. 0 INTRODUCTION
The preceding chapter, Peripheral Programming I, discussed in detail the procedures
for programming the standard 1700 peripherals. Inefficiency would result if each user
program were required to contain the coding necessary to drive a peripheral; therefore,
the 0 per a tin g sys tem contains programs that per for m all input/output operations.
These programs are referred to as drivers.
Drivers are divided into three main parts: initiator, continuator and error.
13.1 INITIATOR SECTION OF DRIVER
The initiator portion sets up the logic to be used and initiates the operations to be performed. The paper tape reader shall be used as an example. All of the d r tv e r s are
written in interrupt mode. Interrupt mode allows the driver to initiate an operation and
select interrupts, exit to the operating system and regain control when the peripheral
has completed the operation.
LDQ
SEL PTR, FUNC
=N$A1
ENA
1
CLR CONTROLLER
OUT
-1
START MOTION, SEL INT ON
ENA
$34
-1
ALARM OR DATA
OUT
EXIT TO OPERATING SYSTEM
o
Via the above coding, the in i t i a tor portion of the paper tape reader has selected the
e qui p men t, selected interrupts, and exited to wait for an interrupt. The initiator
portion of every driver initiates these three operations.
13.2 INTERRUPT FROM EQUIPMENT
The equipment will generate an interrupt when a selected in t err up t condition arises.
The aclmowledgement of interrupt is on a priority basis. The priority depends on the
setting of the 16-bit mask register. A maximum of 16 interrupt lines may be connected
to the 1700, with each line corresponding to a bit in the mask register.
15
14
13
12
11
10
M
o
Line 13
Line 12
Line 11
Line 10
Line 9
Line 8
13-1
Line 1
Line 2
Line 3
Line 4
Line 5
Line 6
Line 7
13.2
The bit in the corresponding bit position must be a 1 in order for the in t e r ru p t to be
aclmowledged. If the bit is a 0, the interrupt holds and is not acknowledged until the bit
becomes a 1.
Once the bit is set to a 1 in the M regis ter , control is transferred to the interrupt trap
region. The trap region is set up to allow four words for each interrupt line. The core
locations are always from location 10016 to 13F1 6. See section 1.3 to review the interrupt sys tem.
13F
}
13E 1 - - - - - - - - - 1
13D I - - - - - - - - - - - t
l3C I - - - - - - - - - - - t
LINE 15
Interrupts may be nes ted 16 deep I
LINE 1
Four core locations reserved for each
interrupt line:
(11--
t "ItO
,of
e. .... "'"
--LO-C-:.- -1,0
,/
I
'10
107
106
105
104
103
102
101
100
LINE 0
-
word
word
word
word
4 - address of interrupt processor
3 - priority level for line
2 - RT J to interrupt handler
1- - overflow and P
Figure 34. 1700 Interrupt Hardware and Software Functions
Hardware:
• Disables interrupts
• Stores overflow indicator and P of interrupted program in word 1
• Transfers control to word 2
13-2
c
13.2
Software:
• Word 2 contains RTJ to common interrupt handler
• Interrupt handler saves registers of interrupted program, sets new mask from
priority level in word 3, enables interrupts, and t ran s fer s control to interrupt
processor for that line (from address in word 4).
• Interrupt processor must exit to the driver con tin u at 0 r which will service the
equipment (i. e., input data).
• The continuator must exit through the dispatcher to restore the interrupted program.
The computer hardware dis a b 1 e s interrupts and stores the contents of the P register
in the lower 15 bits of the first trap word for the interrupting line. The hardware sets
the upper bit of the firs t word to a 1 if the overflow in die a tor is on and to a 0 if the
indicator is off. Control is then passed to the second word.
Once con t r 0 I is passed to the second word, the processing is under software control.
See Figure 36 for hardware and software functions.
13.3 COMMON INTERRUPT HANDLER
o
The second word contains a return jump to the common interrupt handler. The common
interrupt handler saves the contents of all the per tin e n t registers: A, Q, M, and I.
The M regis ter is set to the priority for the interrupting line by using the priority level
set in the third word. Interrupts are then enabled by the common in t err u p t handler.
The interrupt handler transfers control indirectly t h r 0 ugh the fourth word to the processor for that line.
13. 4 INTERRUPT LINE PROCESSOR
The processor for the interrupt line (LYNEI or EPROC) takes status on all equipment
on the interrupting line and checks bit 2 of each status word.
The processor will be able to determine which peripheral interrupted bee au s e the interrupt bit (bit 2) of the status word will be set. The interrupt pro c e s so r will pass
control to the appropriate continuator portion or a driver.
13.5 CONTINUATOR SECTION OF DRIVER
The continuator checks the alarm bit to de t e r min e if control should be passed to the
error portion of the driver.
o
13-3
13.5
LDQ
NOP
INP
STA
AND
SAZ
JMP
=N$A1
SEL PTR, STATUS
-1
STATUS
=N$20
1
ERR
STATUS IN A
SAVE STATUS
CK FOR ALARM
IF ZERO CONTINUE
IF NOT ZERO ALARM
C_ . ~
If the alarm bit were not set the interrupting condition would be processed by the continuator. The continuator checks further to determine which interrupt was generated.
The paper tape reader allows the s e Ie c ti on of only two interrupts, alarm and data;
therefore, if the alarm bit was not set the data in t err u p t was probably generated. It
would be wise to check the data in t err u p t bit and if it is not set, pass control to GI
(ghost interrupt) in the error section:
LDA
AND
SAN
JMP
STATUS
=N8
DATA
GI
Input data if the data bit was set:
DATA
LDQ
NOP
INP
=N$AO
SEL PTR, DATA
-1
DATA IN A
C
The continuator then performs the n e c e s sa r y packing operations to form one 16-bit
word. A check is made to determine if all data has been processed. If not, the continuator exits to wait for the next interrupt.
SEL PTR, FUNC
LDQ
=N$A1
INT ON DATA OR ALARM
ENA
$14
OUT
-1
EXIT TO OPERATING SYSTEM
The continuator could s imp I y exit without res electing interrupts because the interrupt
reques t is s till up if it has not been cleared.
13. 6 ERROR SECTION OF DRIVER
The ERROR portion takes s tat us to determine which alarm condition has arisen. Thel
error routine then performs the necessary operation to correct the error. If the error
cannot be corrected without operator intervention, the operator should be notified.
c
13-4
13.6
o
LDQ
NOP
INP
ALS
SAM
ALS
SAP
ALS
SAM
JMP
=N$A1
SEL PTR, STATUS
-1
5
POWOFF
1
PMF
3
LOSTD
GI
STATUS IN A
POWER ON BIT AT 15
The above coding establishes the condition at fault.
routines that process the various errors.
PAPER MOTION FAIL BIT AT 15
LOST DATA BIT AT 15
IF HERE NO ALARM OCCURRED
The skip address sends control to
GI is where control is passed for a ghost interrupt. The equipment interrupted but apparently for no reason. This would indicate a hardware malfunction.
13. 7 SUMMARY
o
The driver can be summarized as follows. The initiator is the first to have control. It
selects the e qui pm e n t and selects interrupts, then it exits to the operating system.
The continuator gains control via the interrupt trap area after the peripheral generates
an in t err up t. It checks for alarm and if one is present, sends control to the error
portion. If no error occurred, it maintains control and processes the interrupt. If the
operation is not complete the continuator exits to the operating syst~m. The error portion determines which alarm condition occurred and attempts to correct the fault and/or
notifies the operator. Figure 35 illustrates the flow of the interrupts through the continuator.
It is important to note that the primary purpose of this chapter is to ill u s t rat e tech-
niques for programming the h a r d war e in interrupt mode.
routines is secondary.
The linkage through MSOS
The logical division of programming func ti ons into initiator, continuator, and error
sections could be utilized to program any peripheral, either in a stand-alone system or
under MSOS. The operations to be included in each section are the important consideration here -- what the e qui pm e ntis capable of doing, its timing, and the status of
responses it can send. At this point the pro g ram mer should be able to write an interrupt-mode driver which would not run under MSOS.
To actually write a driver to run under MSOS, it would be n e c e s s a r y to study all the
linkage to MSOS since system tables and common subroutines are used by all the MSOS
drivers.
Some of the MSOS routines are included at the end of this chapter for illustration.
C)
13-5
13.7
Example
The following is a test program to print a message on the teletype in interrupt mode. It
uses the MSOS Interrupt Handler to save the state of the interrupted program (probably
the idle loop) each time the interrupt comes in. It by pas s e s the Line 1 Interrupt Processor (interrupt response routine) and MSOS driver by s tor in g its own address in the
fourth word of the interrupt trap for Line 1 (location $107).
After the program has been assembled and loaded under MSOS, the computer should be
stopped, the protect switch turned off, and P set to the address TTYI; then it should be
run. A master clear should not be done because that would disable the interrupt system
and clear M.
In reality, if a program such as this were used in a stand alone system, it would assure
that bit 1 was set in the M register and execute an EIN. It would also have a routine corresponding to the interrupt handler to save the state of an interrupted program.
The test routine here simulates the operations on the equipment which would logically be
performed by different portions of a driver.
1.
TTY! sets up the trap.
2.
INIT is the initiator to set up the equipment.
terrupt.
3.
CONT is the continuator and it outputs a character each time the interrupt comes in.
It also must keep track of the number of words des ire d to be written. It hangs at
CMPLET when finished. An MSOS d r i v e r would schedule the programmer's completion address when his request was finished.
4.
ERR. The error section a n a I y z e s errors. It hangs in the test r
error, but in MSOS it would attempt to correct the error.
5.
The TABLES used by the routine contain information which is used by the driver for
the write; they simulate a physical device table.
6.
INTRES. The interrupt response routine is actually not a part of the driver. It must
status each device on the line to see which one interrupted. Our example only checks
the TTY.
13"':'6
It then exits and waits for the first in-
0
uti neon each
c
13.7
o
0001
0002
0003
NAM
TTY
EQU
ENT
ADISP($EA)
TTYI.CON1,ERR,INTRES
INTE~kUPT
MODE
* LOAU THE PkOGRAM UNO~R MSOS - TURN OFF PROTECT SWITCH
* rUHN OfF DISC - LJO NOT MASTER CLEAR - SET P AND RUN
·0004
UOt:.A
0005
0006 PuOOO
0001 puOOl
PU002
0008 P0003
'PU004
OUuO
TTYl
CUVU
UOJA P
0
U
LDA
=XINIRES
LOQ*
ENA
OUT
LOA
TTY
SUHSTITUET INTRES IN TRAP
b400
0107
0009
0010
0011 POOO~ r:8JU
. 0 0'1 2 PO 0 0 bOA 0 J
0013 P0007 03FE
-~fOT4· '-PO 00 e co 0 0
POOOY ulOO
INIT
-0015 POOOA 0800
NOP
OUT
INQ
NOP
OUT
INQ
ENA
OUT
JMP-
0016 PUOOt:5 OJFE
OU17
poooe
0D~'E
0018 POOOLJ GbDO
n
"0 19'"' PO 0 0 E 0 3 F E
o
0020
0021
0022
0023
0024
POOOF
POOIO
POO 11
P0012
0001
OAl403f E
141:..A
3
-1
INITIATOR
GET TTY FUNC CODE
CL~ CONTROL
CLR INTERRUPT
=N$100
SELECT WRITE MOOE
-1
-1
CHANGE TO DATA FUNCTION
-1
1
~14
OUTPUT DUMMY CHARACTER
SEND FUNCTION
SEL INTERRUPT ALARM OR DATI
-1
(AOISP)
GO wAIT
FO~
INT
*
'0"0·25
0026 POOIJ
0027 P0014
0028 POOlS
0029' P0016
0030 POOl7
"0 n3 1'" P 0 0 1 a
ulel
1817
UFC2
a1 J 1
0032 POOIY
Id~l
ce~S
*
CONT
UrCA
'0033 P001A CCOO
OK
DATA
CONTINUAI0~
LOA*
ALS
SAP
JMP*
ALS
SAM
JMP*
LDA
STAT
10
OK-*-1
ERR
GET STATUS BACK
CK ALARM BIT 5
2
ALARM UP
CK DATA 8IT 3
DATA
GI
(FWA)
NOT ALARM OR DATA
GET DATA
P0018 uU1H
GET CHAR FLAG
8
UPPER CHAR
FLAG
OUTPUT
FLAG
FWA
TTY
CLR FLAG FOR LOWER NEXT
GO OUTPUT DATA
SET FLAG FOR UPPER NEXT
UPDATE HUFfER ADDR
-1
DATA fUNC
-1
OUTPUT 1 CHAR
LAST WORD YET
LDQ*
SQZ
ALS
ENQ
o
0038 P0020 4819
5TQ*
JMP*
RAO*
RAO*
LDQ*
INQ
NOP
OUT
LDA*
EOt<*
0039 P0021 1803
-UO'40' PO 0 22 081 I
0041 P0023 lJe13
-OO-liZ PO 0 24 E811
0043 P002S OI)~E
0044 P0026 0800
LOwER
OU1PUT
0045 P0027 U3fE
0046 P0028 C80E
0047 pa02'i beOE
-on 0'48 PO 0 2 A
C)
FLAG
LOWER
'0034 POD'le E81D
0035 POOlO U144
"0'030" PO OlE OFCB
0037 POOlf UCOU
0 10 1
004Y POU21j lltt.A
0050 P002C 18FF
CMPLET
OOSl
*
SAl
JMPNUM
FWA
LwA
CMPLET
(ADISP)
!i>ldFF
13-7
GO AWAIT NEXT INT
HANG WHEN FI~IShED
1.3.7
Ekk
"O(rS5 -p'o 6-2 E .UF t S
00S6
0057
0058
0059
0060
POOet'POOJO
P0031
POOJ2
P0033
"'o-ob-C p'o '034'
0062
0131
ItjrF
UFC'+
01el
lefF
1 eO C
ERkOR SECTION
FINU CAUSE OF ERROR
LDA*
ALS
SAM
NUM
ALS
SAP
NUM
JMP*
STAT
S
1
~18FF
'+
1
~ltjFF
Gl
*
0064
*
-era 65-- P 603 S' U() ';I i T T Y
00b6 P003b 00'+1 P FWA
'ou6-,+ P LwA
0068 P003ti 0001
-O~69 P0039 OOUI
STAT
0070
*
0072
*
NUM
ADC
AOC
BLS
BZS
$91
BUF
BUF+35
STAT(1)
FLAG(1)
*
--0071------···
- 0 0 7 j--po 0'"3 A"Eti VA-
.
I NT RI::: S
CK MUTOR aNN
-
MOTOk OFF
HANG HERE
Ct<. LOST DATA
-
LOST DATA
HANG HERE
NO EkROI-< APPARENT •••
TA~LES (PHYSTB)
USEU BY URIVER
TTY FUNe CODE
CUkRENT 8UFFER ADDRESS
LWA+l
STATUS wORD
INTtRRUPl I-S •
Absolutize on lun S (disk scratch)
IN
- - - - - - Absolutize in 96-word blocks for disk
*P,F
L,16 FAILED
Printer failed
ACTION
RP
L,02 FAILED
Out of tape. Complete absolutizing
ACTION
CU
..
E *
IN
Unpatched externals (unnecessary modules were taken out of sys. ini.) - ignore
•
*K,IS
IN
Input now on S
-*N~
-I,Q4-
IN
*N,SYSINI" ,B .•- - - - - - File SYSINI, binary, placed in pgm. lib.
IN
l~·rn
....
• - - - - Input now on lun 2 PTR (GETSI)
IN
4
~----
*L,GETSI
LOS
Put GETSI in pgm. lib. in reI. bin. form
IN
*z
J
*p
J
*SI
J
SI IN
SI
*1,1
..
Sign off LIBEDT
CHECK IT OUT
..•
Turn off protect switch here!
....- - - - - - Call in GETSI
•
•
•
GETSI gets SYSINI and types SI IN
System initializer types SI
Begin initialization!
Q
*V
*Y, QQTEST, 2, QQQ8AB, 3, QQSPAC, 4
*YM, LOADSD. 1, JOBENT, 2, JOB PRO, 3, JPLOAD, 4
*YM, JPST, 5, JPCHGE, 6, JBKILL, 7, JPT13, S
*YM, RCOVER, 9, LIBEDT, 10, MODI, 11, MOD2, 12
*YM, MOD3, 13, BRKPT, 14, RESTOR, 15, MOD4, 16
*YM, DEBUG, 17, DSUTIL, lS, TYPEID, 19, DSTART, 20, RSTART, 21
*YM, QQFMTl, 22, QQCOM, 23, QQANAB, 24, QQUTLl, 25
etc.
14-6
14.4
14.4 TRANSFERRING RECORDS
In this example, LIBEDT was used to t r an s fer a card image from the card reader to
paper tape. The *T image in the example was then a t t a c h e d to the end of a series of
paper tape programs being loaded, to cause the loader to end loading.
o
o
14-7
14.4
TRANSFER RECORDS FROM ONE LUN TO ANOTHER
LIBEDT *T
(*T option is used to transfer reI. bin. pap e r
tapes which are SI input to high portion of disk
so that disk input may be made to SI.)
*z
J
*p
J
*LIBEDT
LIB
IN
*T,12,A,11,A,1
IN
Transfer from LUN 12 (CR), ASCII mode, to LUN 11 (PTP),
ASCII mode, one record (1 card)
c
14-8
14.5
o
14.5 ABSOLUTIZING AND LINKING SUBPROGRAMS
Next, LIBEDT was used to build a utopia system. This involves loading, absolutizing,
and linking a series of relocatable binary paper tapes. Only the routines applicable to
the particular configuration were included. The new utopia in core can then be used to
punch out an absolute paper tape image of itself.
o
14-9
14.5,
BUILD UTOPIA SYSTEM USING LIBEDT
*p
J
*LIBEDT
LIB
....
4~---- Call in LIBEDT
IN
*K, 12, P11 .....- - - - - - - Assign input LUN 2 (PTR) output LUN 11 (PTP)
IN
*p ....~------ Load and: absolutize tapes
L,02 FAILED 02
UTOPIA
ACTION
RP
L, 02 FAILED 02
UMAINF
ACTION
1
RP
L,02 FAILED 02
ACTION
RP
L,02 FAILED 02
ACTION
RP
L, 02 FAILED 02
ACTION
USILLY
U1711
UDISK
RP
L,,02 FAILED 02
ACTION
CARDIN
RP
L,02 FAlLED 02
ACTION
RP
L, 02 FAILED 02
ACTION
RP
L,02 FAILED 02
ACTION
U1729
U601MT
UTODMP
RP
L,02 FAILED 02
ACTION
UDALP
RP
L,02 FAILED 02
ACTION
CKOUT
RP
L,02 FAILED
UTLAST
ACTION
CU
....~----- Wind up load and link
E *
44~-----
Externals missing; ignore; punch tape
IN
*z
.....f - - - - - Sign off LIBEDT
J
14-10
14.5
BUILD UTOPIA PRINT OUT
()
UTOPIA
UMAINF
USILLY
U1711
UDISK
CARDIN
U1729
U601MT
UTODMP
UDALP
CKOUT
UTLAST
0
E10
CKD
peR
DKM
MAR
VDM
LPRINT
RDM
WDM
2210
2392
25A8
3258
343E
3680
3707
38A9
39BE
3AA2
444A
4F23
Routine names and addresses where loaded
Missing Externals
(These are for modules not included in this
system)
Applicable Utopia routines for customer's configuration can be loaded and linked together, then an abs olutized tape can be punched. It can then be loaded by a cksum
loader (which must be loaded by a bootstrap loader).
Utopia modules could also be loaded and linked and put on program library in reI bin
form (with Libedt * L). Then Utopia could be called from TTY with *UTOPIA.
14-11
c
APPENDIXES
o
o
c
APPENDIXES
TABLE OF CONTENTS
I'~-'
~
U
0
TOPIC
PAGE
APPENDIX A
References
A-1
APPENDIX B
1700 Instruction Execution Times
B-1
APPENDIX C
utility Assembler Pseudo Instructions
C-1
APPENDIX D
Assembly Error Messages
D-1
APPENDIX E
ASCII Codes
E-1
APPENDIX F
Answers to Exercises
F-l
Chapter II
F-1
Chapter V
F-2
Chapter VI
F-7
Chapter VI
F-8
Chapter VIII
F-9
APPENDIX G
Solutions to Problems
G-1
APPENDIX H
Examples of Instructions
H-1
APPENDIX I
Communications Region
1-1
C',
o
APPENDIX A
o
C)
C~
()
APPENDIX A
Reference Title
Ref. No.
Publication No.
1
Reference Manual
60153100
2
Codes
60163500
3
Assembler Reference Manual
60171600
4
1700 Macro/Assembler Reference Manual
60176300
5
utility Reference Manual *
60172300
6
Operating System Reference Manual
60174600
7
1700 4K Assembly System (ADB)
60176500
8
Input/ Output Specifications Manual
60165800
9
Sys tems Manual
60152900
ADSD General Information Manual
60187600
10
*utility Assembler requires 8K system.
·
C
--,
'I
)
A-1
APPENDIX B
o
C~:
APPENDIX B
()
1700 INSTRUCTION EXECUTION TIMES
STORAGE REFERENCE
Execution Time
" (microseconds)*
Ins truction
o
LDA
STA
LDQ
STQ
ADD
SUB
ADQ
AND
EOR
RAO
MUI
JMP
RTJ
DVI
SPA
2.2
2.2
2.2
2.2
2.2
2.2
2.2"
2.2
2.2
3.3
7.0
1.1
2.2
9.0
2.2
Load A
Store A
Load Q
Store Q
Add A
Subtract
AddQ
AND with A
Exclusive OR with A
Replace Add One in Storage
Multiply Integer
Jump
Return Jump
Divide Integer
Store A, Parity to A
*Add 1. 1 microsecond if Storage Index Regis ter is used.
Add 1.1 microsecond for each level of Indirect Addressing.
Add 1.1 microsecond for two word instructions.
REGISTER REFERENCE
Execution Time
(microseconds)
Ins truction
SLS
INP
OUT
ENA
ENQ
INA
INQ
ARS
QRS
ALS
QLS
Selective Stop
Input to A
Output from A
Enter A
Enter Q
Increase A
Increase Q
1.1
1.1 min., 10 max.
1.1 min., 10 max.
1.1
1.1
o
1.1
1.1
A Right S h i f )
Q Right Shift
A Left Shift
Q Left Shift
)-._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 1.1 +(shift count *.1)
C)
B-1
REGISTER REFERENCE (Cont)
Execution Time
(microseconds)
Instruction
LRS
LLS
Long Right Shift)
Long Left Shift
> - - - - - - - - - - - - - - - - 1. 1 + (shift count *.2)
NOP
EIN
IIN
EXI
SPB
CPB
No Operation
Enable Interrupt
Inhibit Interrupt
Exit Interrupt State
Set Program Protect
Clear Program Protect
1.1
1.1
1.1
2.2
2.2
2.2
B-2
INTERREGISTER
0
Execution Time
(microseconds)
Instruction
0
SET
CLR
TRA
TRM
TRQ
TRB
TCA
TCM
TCQ
TCB
AAM
AAQ
AAB
EAM
EAQ
EAB
LAM
LAQ
LAB
CAM
CAQ
CAB
Set to Ones
Clear to Zero
Transfer A
Transfer M
Transfer Q
Transfer Q V M
Transfer Complement A
Transfer Complement M
Transfer Complement Q
Transfer Complement Q V M
Transfer Arithmetic Sum A, M
Transfer Arithmetic Sum A, Q
Transfer Arithmetic Sum A, Q V M
Transfer Exclusive or A, M
Transfer Exclusive or A, Q
Transfer Exclusive or A, Q V M
Transfer Logical Product, A, M
Transfer Logical Product A, Q
Transfer Logical Product A, Q V M
Transfer Complement Logical Product A, M
Transfer Complement Logical Product A, Q
Transfer Complernent Logical Product
A, Q VM
B-3
1.1
SKIPS
Execution Time
(microseconds)
Ins truction
SAZ
SAN
SAP
SAM
SQZ
SQN
SQP
SQM
SWS
SWN
SOY
SNO
SPE
SNP
SPF
SNF
Skip
Skip
Skip
Skip
Skip
Skip
Skip
Skip
Skip
Skip
Skip
Skip
Skip
Skip
Skip
Skip
if A = +0
if A f: +0
if A = +
if A = if Q = +0
if Q f: +0
if Q = +
if Q = if Switch Set
if Switch Not Set
on Overflow
on No Overflow
on Storage Parity Error
on No Storage Parity Error
on Program Protect Fault
on No Program Protect Fault
1.1
c
c
B-4
APPENDIX C
o
C)
c
c
c
APPENDIX C
UTILITY ASSEMBLER PSEUDO INSTRUCTIONS
NAMn
First ins truc tion in source program. The
name, n, if given, identifies the program. A
numeric location fi e 1 d for this ins t r u c t ion
specifies the absolute starting location for the
program; a symbolic location field is ignored.
ENDe
Last instruction in source program. The entry
point, e, if given, is the start of the. program.
Entry points, ni' that may be ref err e d to by
other programs.
External locations, ni' of other programs that
are referred to by this program.
EXT*n 1 , n 2 ' • • •
S i mil a r to EXT except that references to the
external names, ni, are made relative.
Reserves a block of program storage locations.
The names, ni' identify segments of si words in
length.
o
BZS n 1 (S1)' n 2 (S2) , • • •
COM n 1 (S1)' n 2 (S2) •• •
Similar to BSS. In addition, zero fills the block.
Reserves a block of common storage locations.
The names, ni' identify segments of si words in
length. Data may not be prestored in the common block.
Reserves a block of data storage locations. The
names, ni' identify s e g men t s of si words in
length. Data may be pre s tor e d in the data
block.
Defines add res s expressions to be stored as
address constants. The addresses maybepositive or negative and a b sol ute or relocatable.
Parentheses indicate indirect addressing.
ALF n <:2n
character~
Stores ASCII alphanumeric characters into consecutive locations of program storage.
Stores decimal or hexadecimal constants, ci' in
consecutive locations in program storage.
o
C-1
UTILITY ASSEMBLER PSEUDO INSTRUCTIONS (CONT)
ORGe
Assemble subsequent instructions beginning at
the address expression, e, which may be program relocatable, data relocatable or absolute.
ORG* e
Resumes assembling instructions immediately
after the location preceding the ORO instruction
or the firs t ORG if more than one in a string.
EQU n (e ), n (e ) , •••
2 2
1 1
NLS
Equates names,
LST
Enables list output of ass em b 1 y following issuance of a NLS instruction. (Listing is automatic unless NLS is given.)
SPC v
Spaces v lines on the typewriter.
~,
to address expression, ei.
Inhibits list output of assembly.
('
'--- ..
C-2
APPENDIX D
o
c'
c
· APPENDIX D
ASSEMBLY ERROR MESSAGES
ERROR LISTING
A list of errors occurring in passes 1 and 2 precedes the program listing on the standard
comment Ilo unit. If the L option is selected, errors in pass 3 pre c e d e the source line on
the list output. A decimal error count is printed at the end of each subprogram. If L is not
selected, error messages are output on the standard comment unit.
Format for pass 1 and 2 error messages:
Column
Contents
1-3
3 -digit line number
4
space
5-6
**
7-8
2-character error code
Format for pass 3 error messages:
Column
Contents
1-6
******
7-8
2-character error code
9-18
**********
Following are the error message codes and their definitions.
Message
**DS
Meaning
Doubly defined symbol. A name in
1) location field of a machine instruction or an ALF, NUM, or ADC
pseudo instruction
or
2) address field of an EQU, COM, DAT, EXT, BSS, or BZS pseudo
ins truction
has been used again in one of the above fields.
**UD
Undefined symbol in an address expression.
**SO
Available storage for saving symbol names exceeded; no more names
may be defined. Symbol table overflow.
D-1
Meaning
Message
**EX
Illegal expression.
One of the following:
1) No forward referencing of some symbolic operands
2) No relocation of certain expression values
3) A violation of relocation
4) Possibly a comment is being interpreted as an address field in an
ins truction which has no address field
**LB
Numeric or symbolic label contains illegal character. The I abe I is
ignored.
**IX
Illegal index register; specified by symbol other than Q, I or B.
**OP
1) illegal symbol in operation code field, e. g., LDI
TAG
2) illegal operation code terminator
3) Could also be caused by error in macro
**OR
Numeric or symbolic operand in address expression contains illegal
characters.
**RG
Illegal register for interregister instructions, e. g., CLR
I
1) Symbol other than A, Q, or Mused in address field of interregister
instruction, or the same symbol used more than once.
/~
2) Registers separated by other than a comma.
**RL
1) Violation of relocation.
2) Violation of a ru1e for instructions which r e qui r e the expression
value to
a) be absolute
b) have no forward referencing of symbolic operands.
**OV
Numeric operand overflow-numeric value greater than allowed, e. g. ,
1 wd. reI. more than $7 F.
**SQ
Sequence error
**MD
Macro definition error
**MC
Macro instruction error
**PP
Error in previous pass of compilation
**NN
No NAM statement. Blank name will be inserted by assembler.
**MO
Overflow of the load-and-go area .of mass storage.
D-2
r0
()
LOADER ERROR MESSAGES
All loading error messages appear on the standard print output device.
EOl
Irrecoverable input error; terminates loading.
E03
Illegal or out-of-order input block; terminates load. Also, this diagnos tic appears
on the comment device when illegal input from that device is detected. The comment
device is interrogated for a new statement.
E04
Incorrect common block storage reservation. Occurs if the first NAM block to declare common storage does not declare the I a r g est amount. The loader uses the
previously declared length and continues.
E05
Program too long or loader table overflow. Terminates loading. Occurs if program
to be loaded exceeds available unprotected core. It may be possible to load the program by rearranging the 0 r d e r of loading to insure entry points are defined before
they are referred to as external symbols. Loader produces a memory map and list
of unpatched externals prior to terminating the load.
E06
Attempt to load information in protected core; terminates loading.
E07
Attempt to ORG into part of data storage beyond assigned block; terminates loading.
E08
Duplicate entry point; loading continues. The succeeding program is loaded, overlaying the program with the duplicate entry point.
E10
Unpatched external. External name is p r i n ted following diagnostic. The operator
may c h 00 s e to terminate the job or continue execution in spite of unpatched externals (with *(CR». A *E(CR) will cause the loader to sea r c h the directory of core
resident entry points for the missing external.
Ell
Error in HEX block; loader skips remainder of block and resumes loading with the
next block. Image of HEX block in error is printed following diagnostic.
E12
Two programs reference same external name, one with a b sol ute addressing, the
other relative addressing.
E13
Undefined or missing transfer address; occurs when loader does not encounter a
name for the t ran sf e r address to begin execution, or the name encountered is not
defined in loader's table as an entry point name.
D-3
JOB PROCESSOR ERROR MESSAGES
PARITY, hhhh
Memory parity error at location hhhh16 •
comment device.
Message appears on output
OV
Overflow of volatile storage. Message a p pea r s on output comment
device.
L, nn FAILED ee
Informs operator of device failure.
nn
logical unit number
ee
code indicating cause of failure as follows:
00
01
02
03
04
05
06
I/O hangup
Internal or external reject
Alarm
Parity error
Checksum error
Internal reject
External reject
ALT,aa
Informs oper.ator an alternate device, aa, has been assigned.
ACTION
Requests operator action when a failed device has no alternate.
device is identified in the FAILED diagnostic.
J01,hhhh
Program protect violation. hhhh is cur r e n t contents of P register.
Standard print output device.
J02,hhhh
illegal request or parameters at location hhhh 16 - Standard print output device.
J03, statement
Unintelligible control statement is output with the diagnostic. Standard
output device.
J04, statement
illegal or unintelligible parameters in con t r
print output device.
J05
Statement entered after manual in t err u p t illegal.
device.
J06,hhhh
A threadable request was made at level one when noprotect processor
stack space was available, or an unprotected t h rea d e d request was
made at level one. Standard print output device.
J07,hhhh
Unprotected program tried to a c c e s s protected device from location
hhhh. Standard print output device.
J08,hhhh
Attempt to access read only unit for write, or write only unit for read,
or an attempt to access an unprotected r e que s t on a protected unit.
0
The
I statement. Standard
Output comment
('"
\" ..
D-4
APPENDIX E
("'I
('
\-
.'
APPENDIX E
r~
AMERICAN STANDARD CODE FOR INFORMATION INTERCHANGE (ASCII)
Bit Configuration
Symbol
000 0000
NUL
001 1011
ESC
000 0001
SOH
001 1100
FS
000 0010
STX
001 1101
GS
000 0011
ETX
001 1110
RS
000 0100
EOT
001 1111
US
000 0101
ENQ
010 0000
SP
000 0110
ACK
010 0001
000 0111
BEL
010 0010
"
000 1000
BS
010 0011
=If
000 1001
HT
010 0100
$
000 1010
LF
010 0101
%
000 1011
VT
010 0110
&
000 1100
FF
010 0111
000 1101
CR
010 1000
000 1110
SO
010 1001
000 1111
SI
010 1010
*
001 0000
DLE
010 1011
+
001 0001
DC1
010 1100
001 0010
DC2
010 1101
001 0011
DC3
010 1110
001 0100
DC4
010 1111
/
001 0101
NAK
011 0000
0
001 0110
SYN
011 0001
1
001 0111
ETB
011 0010
2
001 1000
CAN
011 0011
3
001 1001
EM
011 0100
4
001 1010
SS
011 0101
5
~
I
I
'..............-
(')
\
Symbol
Bit Configuration
,.,_.- .'
E-1
ASCII (Cont)
Bi t C onfigurati on
Symbol
Bit Configuration
Symbol
011 0110
6
101 0010
R
011 0111
7
101 0011
S
011 1000
8
101 0100
T
011 1001
9
101 0101
U
011 1010
101 0110
V
011 1011
101 0111
W
011 1100
<
101 1000
X
011 1101
=
101 1001
y
011 1110
101 1010
Z
011 1111
>
?
101 1011
[
100 0000
\
100 0001
A
101 1101
---]
100 0010
B
101 1110
A
100 0011
C
101 1111
100 0100
D
110 0000
@
100 0101
E
110 0001
a
100 0110
F
110 0010
b
100 0111
G
110 0011
c
100 1000
H
110 0100
d
100 1001
I
110 0101
e
100 1010
J
110 0110
f
100 1011
K
110 0111
g
100 1100
L
110 1000
h
100 1101
M
110 1001
i
100 1110
N
110 1010
j
100 1111
0
110 1011
k
101 0000
P
110 1100
1
101 0001
Q
110 1101
m
101 1100
i
"--
--
r'
I\
'--.
r
\
E-2
-
.---
...
ASCII (Cont)
~
,-- "'..,
)
~
Bit Configuration
Symbol
110 1110
n
110 1111
0
111 0000
p
111 0001
q
111 0010
r
111 0011
s
111 0100
t
111 0101
u
111 -0110
v
111 0111
w
111 1000
x
111 1001
y
111 1010
z
111 1011
0
111 1100
111 1101
[
---,
]
111 1110
,
111 1111
DEL
E-3
c
APPENDIX F
o
c:·~
\
APPENDIX F
to
"---J
ANSWERS TO EXERCISES ON CHAPTER II
1.
a.
0010 1101 1010 1110 is 2DAE
b.
1000 1111 1100 0111 is 8FC7
c.
16
16
1111 1111 1100 0000 is FFC0
16
2DAE
8FC7
16
= -28728
16
FFC0
2DAE
16
16
= 1169410
10
= -63 10
+ 8FC7
BD75
16
16
+ FFC0
+ FFC0
16
16
=
= BD3616
No overflow was generated.
2.
C'
3.
a.
4095
b.
-17
c.
255
10
10
10
= OFFF 16 = 0000
= FFEE
=
16
OOFF 16
1111 1111 11112
= 1111
1111 1110 1110
= 0000
0000 1111 11112
By extending the sign.
2
Consider the 8 bit positive number:
OOOOOii1 - Decimal value 7
2
i
Sign Bit. Extend the sign bit to the left 8 places - 0000 0000 0000 0111 2 - same value
of 7 but the number now occupies a 16-bit field.
The same applies for a negative number. FE 16 is -1 in an 8-bit field and FFFE16 is also
-1, but in a 16-bit field.
F-1
ANSWERS TO EXERCISES ON CHAPTER V - Shift and Skip Instructions
1.
2.
a.
Shifts QA left 16 bits. This effectively switches the data in A to Q and Q to A.
b.
Will JUMP to P + 4 if the overflow indicator is on, and clear the indicator. Will go
to P + 1 if overflow indicator is not on.
c.
Shifts the data in A right 18 bits. This will clear A if bit 15 was originally a 0 or will
set A to all 1 's if bit 15 was originally a 1. It also wastes time since the maximum
necessary shift count to accomplish the same result is 15.
d.
Neither the A nor the Q register is specified so the instruction is essentially a time
delay. It takes 1. 1 + • 1 x8 = 1. 9 microseconds to execute and does nothing to the A
or Q registers.
Q = 0000
A = E3C4
I
"
" ..
('
\
F-2
ANSWERS TO EXERCISES ON CHAPTER V - Constant Mode of Addressing
(')
'"-'....
1.
a.
b.
c.
= 1059
A = 0024
A = 4142
A
Q =0000
Q = 0000
Q = 4040
o
F-3
ANSWERS TO EXERCISES ON CHAPTER V - Absolute Mode of Addressing
1.
LDAADD
STA-
C·'
$FF
=N$10
$FF
also
LDAADD
STA-
I
=N$10
I
I can be used in place of $FF for storage reference class of instructions.
One-word ab-
solute mode is used since $FF is in the communications region.
2.
3.
a.
4016
b.
003F
c.
4016
a.
This will dec 0 d e as COOO; ~ will be 0, yielding not one-word absolute but the first
word of constant mode. The base address for one-word absolute must be 01 to FF.
b.
One-word absolute could have been used since the base address is F3.
c.
Nothing. This is a legitimate example of two-word absolute indirect. Bit 15 of the
sec ond word (P+l) will be set because of the parentheses and bits 14-0 of P+l will
contain the address equivalent for TEST.
(However, this is two-word absolute indirect which requires two core cells
and 1. 1 microseconds more time. Since the base address is in the communications region, one-word absolute indirect should be used. )
F-4
c
ANSWERS TO EXERCISES ON CHAPTER V - Relative Mode of Addressing
1.
a.
Forward, 31 hex locations from P.
b.
Backward, 1000
c.
2.
a.
b.
c.
d.
e.
f.
g.
h.
3.
or 4096 from P+1, or OFFF 16 or 4095 from P.
16
10
10
Backward, one location back from P.
Two-word relative
One-word absolute indirect
Two-word absolute indirect
One-word relative
Constant. Two-word.
Two-word relative indirect
Constant. Two-word.
One-word absolute
The communications region is fix e d and will never move with the program. If the program moved and not the communications region, the rei a t i v e distance which had been
established would be worthless. Fixed areas of core are addressed absolutely, and those
that move with the program are addressed relatively.
F-5
ANSWERS TO EXERCISES ON CHAPTER V - Indexing
1.
2.
3.
a.
B is used to in d i cat e use of both Q and lin d e x regis ters.
LDA AB,B.
Should be w r itt e n
b.
Nothing, if A is defined as a legitimate symbol elsewhere in the program.
c.
No indexing with shift class instructions, only storage reference class.
a.
A = 0000
b.
A = 0023
c.
A = 0023
It will loop forever since the reduced index register I value is never stored back. Need
a. STQ- I after the ADQ =N-1.
Answer to indexing problem:
a.
$1234
b.
$02ED
c.
$2311
d.
$1111
F-6
C_
ANSWERS TO EXERCISES ON CHAPTER VI - Utility Assembler
/'-
,
"'<'oJ
1.
a.
Symbols for the EQU and BSS pseudo ops are defined by appearing in the address
field.
b.
TAG is a doubly defined symbol.
It cannot be an EXT.
c.
START should be an entry point.
The program should look like:
Location
TAG
START
o
Opcode
Address
NAM
ENT
EQU
NUM
BSS
EXT
LDA+
STA+
EXAMP
START
LED(720)
-72, $FFFF, 72
TAG11(25)
LAD
TAG
LAD
END
START
Comments
2.
The common area cannot be preset.
3.
Since the common area is fixed, all references to it can safely be made absolutely.
is necessary instead of a relative addressed mode for run anywhere programs.
4.
When the reference is made to LIST+3, the operand is unpredictable. The loader skips
over the LIST area at load time. A BZS should have been used. It would be worthwhile
at this point to refer to reference 5 or 6 for more information concerning the loader since
this information is not covered in this manual.
C)
F-7
This
ANSWERS TO EXERCISES ON CHAPTER VI - Macro Assembler
1.
a.
FEE9
002F
b.
4142
c.
OAOO
d.
FFFE
l_. -
. =N$lOOO
=N$lOOO
2.
LDA
ADD
3.
TAG
TAGl
4.
The symbol TE is declared local to the macro and cannot be called by the main program.
Also, since the code is inserted in-line, the $7FF3 could be executed as an instruction.
ALF
ALF
Z,ERROR6 Z
Z, LOGICAL UNIT8 Z
~
(
'--..
F-8
ANSWERS TO EXERCISES ON CHAPTER VIII
1.
LOOP
FIRST
STA*
ENA
LDQ
OUT
INQ
INP
SAN
JMP*
INP
ALS
INP
STA*
RAO*
JMP*
ADC
FIRST
$20
=N$Al
-1
-1
-1
1
*-2
-1
8
-1
(FIRST)
FIRST
LOOP
0
a.
This program is run anywhere.
b.
Starting location for the checksum program is initially placed in the A regis ter.
c.
Reader will run out of tape and stop on a lost data condition.
o
F-9
c·
c
APPENDIX G
c'
APPENDIX G
o
SOLUTIONS TO PROBLEMS IN CHAPTER V
ADDRESSING PROBLEM
a.
1234
b.
02ED
c.
2311
d.
1111
MOVE
The MOVE routine moves 1001 numbers from $1000-$2000, inclusive, to $3000-$4000, in16
clusive.
$2000
$4000
etc.
o
$3000
$1000
SUM
The SUM routine sums 1001 16 numbers from $1000-$2000, inclusive.
in $3000.
$2000
sum
$1000
.r
-G-1
The answer is stored
CHNG
The CHNG routine swaps two arrays, inverting them. The contents of locations $1000-$2000
are swapped and inverted with the contents of locations $3000-$4000.
$2000
$4000
$1000
$3000
C
~/
The swap is completed when the last address in ADDR has been decremented past $3000.
SUB
The SUB pro g ram picks up the actual data from the calling program and stores them in its
locations SUBAG1, SUBAG2, and SUBAG3. The EOR =N$8000 put an indi re c t bit on the
contents of location SUB (which in the example was $502). This caused the LDA * (SUB) to get
the actual data, 10, etc. Mter picking up all the data, the subroutine updated the return address to $505 and ANDed off the extra indirect bit, AND =N$7FFF, so the return would be!
to the proper place.
The subroutine saved the reg i s t e r s when it was entered, and restored them when it exited,
which most subroutines would do.
(
'-.,'
SORT
The SORT r ou tine sorts 16 numbers, in ascending order, in core locations $500-$50F, inclusive. The method used is to push the smallest number to the top, the next smallest number
to the next-to-top, etc.
CLRPB
The CLRPB subroutine clears protect bits on the core area from $2000-$4000, inclusive. The
parameters pas s ed by the calling routine are the la~t word address of the buffer (LWA) and
the first word address (FWA). The subroutine will work for any addresses passed to it. It
uses the A register and overflow indicator for loop con t r 01. When the last word address is
subtracted from $7FFF in A, the number left will be: such that when Q reaches the last word
address +1 and the AAQ 0 instruction is executed, overflow will occur, and the exit will be
made from the loop. The SOV 0 ins truction before entering the loop turned off the overflow
indicator in case it may have been on. The CLRPB subroutine must be a protected routine
itself or the protect switch must be off.
('
\
'-...
o
CONVRT
The CONVRT subroutine converts a hexadecimal number which it receives in A to the ASCII
codes for the decimal number. It packs the codes in a buffer, BUF, and returns to the caller
with the buffer address in A.
The method used is to divide the number by 10, in hexadecimal arithmetic, and save the remainders. Each time a divide is done, the remainder in Q will be used to get the ASCII code
for the number from a table, TAB.
It would have been possible in this example to simply add $30 to each remainder for the conversion. However, the table-look-up method is used for ill us t rat ion. Also note that the
routine puts the characters in one buffer, BUF1, then packs them in BUF for the caller.
The CONTST pro g ram checks out CONVRT by calling it to convert a number $37 CO, then
writing the answer on the teletypewriter in ASCII.
o
o
G-3
SOLUTIONS TO PROBLEMS IN CHAPTER VI
VALUE
MASK
START
SEARCH
EXIT
PROBLEM
NAM
COM
DAT
EQU
ENT
EXT*
BZS
0
CLR
STQ
LDA
ANDALS
STA*
ENQ
LDA+
AND
EOR*
SAN
RAO
SQZ
INQ
JMP*
JMP*
END
TEST
DUMMY(10), X(10)
DUM(6), COUNT(l)
LPMASK($2)
START
VALUE
MASK(1)
0
Q
COUNT
VALUE
LPMASK+6
8
MASK
9
X,Q
=N$3FOO
MASK
2
COUNT
EXIT-*-1
-1
SEARCH
(START)
c
NAM gives the pro g ram a name. ENT gives it an entry point. START is where execution
begins, but it does not a p pea r on the END card, implying that it is a subroutine. COM declares the XIS in COMMON; COUNT declares the 7th word of the data block for the answe!.
DUMMYandDUM space over locations not used in this program. The EXT* declares VALUE
ex t ern a 1 (it must be an entry point in the other program), and the * implies it is relative.
The BZS initializes MASK to O. The EQU declares that LPMASK is location $2.
INI MACRO
The two lis tings on the follow i n g pages show one way to w r i t e the INI macro.
listing does not have the macro expanded, while the second does (M option).
The firs t
'.The test routine was run with the STOP switch set. When the computer stopped, the Q register was s e 1 e c ted on the console for display. It contained a 6, to indicate that the macro
worked.
The INI is not exactly like an INA or INQ because of the size of operands allowed.
has an ADD =N'N' instead of an INA 'N'.
Line 0008
('
G-4
,'-
0001
0002
0003
0004
L/
QOOS
0006
0007
0008
0009
0010
0011
0012
0013
0014
0015
0016
0016
0016
0016
0016
0016
eOQOQ 0000
POOOI 0842
POO02 40FF
POO03
POO04
POOOS
Pq006
eQQOl
POOOS
0016 POOOe)
0016 POOOA
0017 poooa
0018 poooe
0019
C"
I
INI
NAM
MAC
LOC
JMP*
'SA'
NUM
IMIMAC
STA*
LDAADD
STALDA*
EMC
ENT
0
CLR
STOINI
1802
0000
68FE
COFF
8000
0006
60FF
C8F9
EOFF
0000
OOFF
INIMAC
LDOSLS
END
OOOOP
roo
C)
G-5
INIMAC
N
SA
*+2
0
'SA'
I
=N'N'
I
'SA'
INIMAC
0
Q
I
6
I
INIMAC
0004P
/
I
"--
0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013
0014
0015
0016
0016
0016
0016
0016
0016
INI
'SA'
POOOO 0000
POOOI 0842
POO02 40FF
POO03
POO04
POOOS
POO06
POO07
1802
0000
68FE
COFF
8000
poooa 0006
0016 POO09 60FF
0016 POOOA C8F9
0017 POOOS EOFf
0018 poooe 0000
0019
I
OOFf
INIMAC
[00
INIMAC
NAM
MAC
LOC
JMP*
NUM
STA*LDAADD
STALDA*
EMC
ENT
0
CLR
STQINI
JMP*
NUM
STA*
LDAADD
STALDA*
LDQSLS
END
OOOOP [00
G-6
INIMAC
N
SA
*+2
0
'SA'
I
=N'Nt
I
'SA'
INIMAC
0
Q
I
6
*+2
0
(00
I
=N6
I
(00
I
INIMAC
0004P
,r~'
' ......
SOLUTION TO PROBLEMS IN CHAPTER VIn
CKASSM PROBLEM (8.4)
The first INDIR request, line 13, is for the w r it e request at line 34, out of the buffer MSG,
line 25, on the teletypewriter. "NEXT MESSAGE SHOULD INDICATE VERIFICATION."
The next, at line 15, is to s tar t the write request at line 32 to write a message from MSG1,
line 26, on the disk. "MACRO ASSEMBLER ON 1700 NOW OK." This message will be written
on the disk concurrently with the first message which is going out on the TTY.
At line 16, a status request is made to wait for the disk write to finish. Then, at line 19, the
message on the disk is read back in, line 28, into a different buffer, BUF, which is a BZS at
line 27. At line 20, status is taken from line 28 to wait for com p let ion of the disk read.
Finally, this message is transferred out of BUF to the teletypewriter at line 23, after which
an exit is made at line 24.
The program works out the assembler by the ass 0 r tm e n t of requests used to transfer the
message around. Note that no completion routines are used; it will be obvious that if the two
messages come out, it 'worked; and if they don't, it didn't.
The errors which could be found are:
1.
o
SQN 1 at lines 17 and 21. This is the main error and the instruction effectively doesn't
do anything. It was intended to loop on the indirect status request until the operation in
progress bit (bit 15 of Q) be cam e clear. To accomplish that, a SQP instruction should
have been used. Since Q is word 8 of the disk physical de vic e table, it will never be a
whole word of zero (upon which the SQN could be used). Only bit 15 should be checked
for zero. Therefore, as the program is set up, control falls right through to initiate the
disk read at line 19, then the teletypewriter write at line 23.
The program works because of the speed of the peripherals involved and the threading of
r e que s t s onto the driver for each logical unit. The correct message is written, not
garbage.
What actually happens (if the SQN's are used ins tead of SQP' s) is:
o
a.
The firs t TTY message is initiated.
b.
The disk write is initiated.
c.
The disk read is initiated; it is t h rea d e d onto the disk driver after the disk write,
since both are at priority O. Therefore, the read will not be done until the write is
finished.
d.
The second TTY write is initiated and is t h rea de d on behind the first write, again
since the priority is the same (RP = 0). That is why the second line comes out after
the first, as it should.
e.
The second line does not contain garbage because the TTY is slow compared with the
disk; the disk buffer has been w r itt en and read back in before the TTY driver gets
ready to write it out. Any change in hardware or priorities involved could cause a
mess.
G-7
2.
The next item to note is the bin a r y write on the teletypewriter at line 23. Normally an
ASCII write would be used. No damage is done because the words being written already
contain ASCII characters which can be sent directly to the teletypewriter.
3.
Note the formatted write and read on the disk. This is not an error but implies that the
disk sector driver is in the system, not the disk word driver.
4.
Note the disk sector address words which must be inserted after the macros at lines 30
and 33. They indicate sector 1 in the scratch area. This is not an error.
The version of the CKASSM routine which is used to check out the macro assembler contains
SQN instructions at P0007 and POOOD. This is probably to test the s tat us request itself and
then also to check out the operation of MSOS.
(
--.
-,~-_/
o
SOLUTIONS TO PROBLEMS IN CHAPTER XI
SOLUTION TO RUN ANYWHERE PROBLEM
Program AVERAGE is written as a nondestructive run anywhere subroutine which may be
called to compute an average. The buffer address in the calling routine is X, and the number
of words is 10. Note that all of the addressing in the program is relative.
0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013
0
0014
0015
0016
0017
0018
0019
0020
0021
0022
POOOO
POOO1
POO02
POO03
POO04
POOO5
POO06
POO07
POO08
POO09
POOOA
POOOB
POOOC
POOOD
POOOE
POOOF
P0010
P0011
POO12
POO13
P0014
0001
0000
OC09
OAOO
68FB
01AO
8AOO !X
7FFFX
01B3
D8F6
AOOO
7FFF
0142
ODFE
18F7
E8FO
OFC1
OF61
3000
OOOA
1CEC
AVG
LOOP
TEST
AV
NAM
EXT *
ENT
BZS
0
ENQ
ENA
STA*
SOV
ADD
AVERAGE
X
AVG
OVFL(l)
SNO
RAO*
AND
TEST-*-l
OVFL
=N$7FFF
SQZ
INQ
JMP*
LDQ*
ALS
LRS
DVI
AV-*-l
-1
LOOP
OVFL
1
1
=NIO
JMP*
END
(AVG)
o
G-9
RELATIVE EXTERNAL X
0
9
0
OVFL
0
X,Q
N WORDS 9
CLEAR A AND OVFL
RELATIVE TO OVFL
2 WORD RELATIVE EXT
RELATIVE TO OVFL
RELATIVE TO LOOP
RELATIVE TO OVFL
RELATIVE TO AVG
PROBI calls AVERAGE and punches out the answer, 4, and remainder, 5. The program is
run anywhere, and note the relative addressing used in the punch request. ANS is before the
request and COMPL is after the request.
0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013
0014
0015
0016
0017
0018
0019
0020
0021
POOOO
POOOl
POO02
POO03
POO04
POO05
POO06
POO07
POOOS
P0009
POOOA
0001
0002
0003
0004
0005
0006
0007
OOOS
0009
0000
0003
OOEA
POOOD 5S00
POOOE 7FFF
POOOF 6800
P0010 FFF9
POOll 4S00
P0012 , FFF9
P0013 54F4
POO14 0501
POO15 0007
POO16 0000
POO17 0003
POOlS' 0003
P0019 7FF5
P001A 14EA
P001B 0162
P001C 5S00
P001D 7FFF
POOlE lSFF
X
ANS
X
X
START
COMPL
X
X
NAM
EXT*
ENT
NUM
PROBl
,AVG,IOERR
START, X
1, 2, 3, 4, 5, 6,7, S, 9, 0
c=
RELATIVE EXTERNAL A VG
BZS
EQU
RTJ
ANS(3)
ADISP($EA)
AVG
TWO-WORD RELATIVE EXT
STA
ANS
RELATIVE TO ANS
STQ
ANS+2
RTJNUM
ADC*
NUM
NUM
NUM
ADC
JMPSQP
RTJ
($F4)
$0501
COMPL+l
0
$0003
3
ANS-*+5
(ADISP)
2
IOERR
PUNCH OUT ANS AND REM
SET X BIT
RELA TIVE TO COMPL (FWD)
NUM
END
$lSFF
START
HANG WHEN FINISHED
C~\
RELATIVE TO ANS
c
G-IO
o
Here is an error example of incorrect relative addressing used in the punch request. Note at
line 16 that the ADC* ANS+5 assembles as FFF5, because ANS comes before the ADC in the
program. A positive inc rem e ntis required, relative to the first word of the parameter
string, so it should have been 7FF5. The ADC ANS-*+5 should have been used.
In de bugging this program, the punch tape was studied •. (Be sure to get it right side up.)
Note that the codes punched are:
03
FF
F5
14
EA
By studying the output, it was no ti c e d that these are the codes for part of the program, indicating that the buffer ANS was not output, but program codes were. Hence the discovery of
the FFF5 at P0019.
o
o
G-l1
0001
0002
0003
0004
PROYl
Til- AVG"IOERR
ENT START,X
hJ.A!"1
EX
pooon
0001
~j\)OOI
(1002
X
C~
1.2.3,,4,5,6,7,8,9,,0
NI Jt"1
?OOO? 0001
r}UOOl 0004
eOOO4 0005
PO()OS 0006
paOOA 0007
"JO 0 0 7 n00A
j-; tJ 0 0 q
OO()g
POOOg 0000
,iZS
ANS
0005 ';'UO 0 A Don3
EOU
OOEA
0006
0007 t)ooon 5800 X START RTJ
!JOOOI=" 7FFF X
STA
0008 POOOI=" AROO
~UOl() FFF9
STO
0009 ~)OOll 4800
":'0012 FFF9
RTJ0010 POOL~ S/+F4
!\JIJ :-1
0011 ":"0014 0501
Af)C·n·
0012 PO 01 c; 0007
0000
NtH"-~"O{)l~
0013
i\jUi'4
0014 POOl7 0003
000]
0015 POOIR
NUf'"
------.{) 0 1 6 POOIQ FFF5
I.\OC*C·
.Jf\1Pr-'OO]fl
14EA
0017
COMPL SQP
0018 ~JOO IP 0162
)(
t;.iOO
le
RTJ
5800
0019
lJO 01 {I 7FFF X
NlJi'.t1
0020 POOIF' lRFF
END
0021
1
ANS(3)
Af)ISP($EA)
AVG
At-·!S
ANS+2
(~F4)
$0501
CO~PL+l
0
'~OOO3
C~
3
AI\IS+5
)
(ADISP)
2
I OERR---'-'
1118FF
ST.ART
c
G-12
o
In order to verify that the programs were indeed run anywhere andnondestructive and did link
correctly, coding was inserted to move them (after they ran one time) to higher core and run
again. Two identical answers would indicate that the programs did run correctly.
The following example includes coding added which will move 100 10 words, beginning at
START, to $4000, and then jump to $4000 to reexecute. This continues repeatedly. Since
the program lengths are 2816 and 1D16 , for a total of 45 16 , the 100
(6416 ) words moved is
10
sufficient.
Another method would be to use the contents of locations $F7 and $ED to find the core address
and program length, and use them in the move.
When checkout methods such as this are used, remember that if the breakpoint package is in
core it is physically located immediately above the last subroutine. Therefore, it would be
wise not to move the programs on top of the breakpoint package and wipe it out.
o
G-13
0001
NAfv1
0002
EXT~}
0003
ENT
OOFA
0005 1-10000 SHOO X START
POOOI "lFFF X.
0006 POOO? 6800
!::f,)U
PROSl
AVG.IOERR
START.X
ADISP($EA)
RTJ
AVG
STA
ANS
ST(~
A"JS+2
0004
POOO) 0024
0007 ~O 0 O{~ 4AOO
0000S Of) ?'+
0008 i'OOOf; 54F4
0009 r>OOO7 0501
0010 POOOq 0007
.0011 1.)0009 0000
0012 ~OOOl\ 0003
0013 ,"0008 0003
RTJ- ($F4)
NUM <;0501
ADC'u, COMPL+l
NUM 0
NUM $0003
NU"'"
ADC
3
0014 POOOC ()O?O
0015 POOOD 14E.A
JMP- (ADISP)
POOOE 0162
COMPL
0017 POOOF 5800 X
SQP
2
RTJ
IOERR
0016
~OOlO
0018
0019
0020
0021
ANS-~}+5
7FFF X
;JO 01 1 OAOO
1-'001? 60FF
POOl3 C9Ee
f"OOl!+ 6500
~)O 015 l+OOO
OO?? POOIA f)OFF
0023 I~O 01 7 COFF
0024 rJOO18 099C
()O25 ~;;o 019 0101
002(1 ,·;001 A I8F8
00?7 POOIR l400
!-IOOIC 4000
OO?R i~;OOlf) 0001
I-'OOlF 0002
~OOIF
LOOP
ENA 0
STA- I
LDA·n· START,I
STA+ 4000.1
R.AQ- I
0030
~OO27
I f\·JA
-99
OUT
SAl OUT
JMP* LOOP
JMP+ $4000
X
NUrw1
1,2.3,4,5,6,7,8,9,0
ANS
fiZS
END
START
00(l3
0003
MOVE
LOA- I
POO20 0004
~OO21 0005
POO22 0006
POO23 0007
rJ OO24 OOOR
t-JOO25 OO()q
POO2A 0000
0029
C_~~
ANS(3)
G-14
(~'
\,'
........
'
o
To illustrate the use of the conversion routine, the following program MAIN calls AVa to compute an average, then calls CONVRT to convert the answer (which was returned inA by AVG).
CONVRT returns a 3-word buffer address of the ASCII characters (in A) which the main program then stores down in the write reques t.
Note that this is an absolute buffer address. The completion address, COMPL, must also be
absolute, yet it is in the run anywhere program MAIN. For that reason, the program must
absolutize the completion address at each run and store it at C in the write request.
After the answer is computed once, MAIN calls the MOVE sub r 0 uti n e to move everything
except CONVRT up to higher core locations, immediately following the 0 rig ina I programs.
Absolute addressing is used in MAIN to CONVRT so that the original copy of CONVRT is used
for conversion, since it is not a run anywhere program.
This would simulate a mass memory mod u I e using a core resident subroutine which always
remained in the same place. Even if CONVRT had been moved, the original copy would still
have been the one called.
Note also that the flag used to control the move is addressed absolutely. This is so the original flag in core will be used: set by one routine and checked by another. This will simulate
run anywhere routines communicating with each other t h r 0 ugh a core resident flag cell. In
the current example, the flag could have been addressed relatively.
o
G-15
0001
~J" ~4
0002
~4,\I~~
.a.
0004
ENT
eees
EXT~$.
0006
EXT
0007
~~
0008
'i~
~1A
*
~4A
0009
0010
MAIN,X,MVFLAG
AVG, ~~OVE
CONVRT
C~'
/'
IN MUST BE LOADED FIRST, CONVRT LAST, FOR CHECKOUT
I N ENT~Y POI~n MUST BE FIRST LaC ,\T I O~J IN MAI~J
~~
0011 PQOOO
3~H'
0012 POOOI
0013 POOO2
0014 POOO3
PODOl,
0015 POO05
ODIe PGGOa
POO07
0017 POOOR
POOO9
OG18 poao'\
0019 POOOH
002(;) PQOOe
0021 POOOO
0000
C~H
~~
1
A I PI
T
E
tjOOO
1
RTJ*
;1:+
0
LDA*
ADD
it-I
a
a.Og~
=XCOMPL-T
680H
5fHJO
x
STA*
FlTJ
C
.o.VG
GO
RTJ+
CONVRT
GO CONVE:RT
STA~c
WRITE+6
($F4)
BUfFER ADORESS
RTJ-
GO '.tJR 1 TE: ," ~IS'/JER
I\V£~AGE:
~E:T
lFFF X
5 / ,00
'Ii
h,
ANSWE~
"lFFF X
6R.u7
54F4
OeOI
0000
~~R
I TE
~JlI ~1
~geOl
0
0023 POOOF 1004
$1004-
002', POOIO 0003
NU~4
3
0025 POOll 0000
ADC
'MPSQP
0
C
0022 POOOE 00 11 0
120012 14EA
0027 POO13 0161
COMPL
0028 POO14 U3FF
0029 POOlS
POO16
0030 POO17
0 0 3 1 POO18
0032 POO19
PODIA
0033 POOlS
POOIC
POOll)
POOlE
P001F
1'8S0LIIT1£[ COMPL
0012
ADC
NUM
NUM
002~
-
FRAN GIACOBBE
PHILA
CLASS PROQLE:M NO. 1 PI
*
oe03
t\jIIM
C400
CKMOVE
LOA+
0
($[")
CKMOVE
$18FF
HANG IF
MVFLAG
FIRST
OR
ERROR
SECOND RUN '?
C
0025 P
JMP
GOMOVE-*-l
('SEAl
MOVE
;<.
NUM
$15F9,$7FFF,$65,2,0,$100O,8,$12,4,3
MVFLAG
BlS
MVFLAG(!)
E~ID
MAI~J
0101
14EA
IHOO X GOMOVE
'ZFF F
SAl
I~p-
X
l5F9
7FFF
00b5
0002
OOUO
P0020 1000
P0021 DOOR
PQO?2 0012
POD23 0004
P0024 0003
0034- POO?5 aOul
0035
I
DOFF
WRITE
0008P C
eO~d'JRT
GOQ')X
"AIN
'10V~
0900P X
OOlBP r1VFLAG
0925P T
9091P
OOOOP COMPL
9QlPeX A'IG
0013P CKMOVE
OOY7X
0015P GOMOVE
0019P
(~
,
G-16
.,\..
."
-
u
~-
QQQl
~JAM
t\'1ER/\GE
0002
gggJ
0004 POOOO
ggO~ POgOI
0006 POO02
ggO:]: pgQQ;J
0008 POOO'+
gOO~ PO 0 (H;i
0010 POO06
PQQQ7
0011 POOO8
gg12 pgggg
0013 POOOA
pg9gB
0014 POOOC
EXT*
X
E~J+
A~JG
SZS
OVFL(l)
ggl~
0001
OVFL
I~~~
OOg"
OC09
YAOQ
68FB
OlAO
SAOO X LOOP
7f~V
01B3
QBfe
AOOO
"
I
E~J~
9
0
STA*
OVFL
N WORDS 10
CLEAR A
O~t=:
,A~IO
O~Jt=:b
O\lERt=:LOlfJ IMOICAlOI
~Q~,l
0
::r:WR~1
ADD
X,Q
ADD UP DATA
SNO
TEST-*-l
GVfb
=N$7FFF
If OVERfbGltt
RA9~i:
AND
TEST
.
0016 POOOE 18F7
AV
CJ
ENQ
+FfF
0142
0017 POOOF E8FO
C'
0
I
PtHHlIJ QQt==g
0018 POOIO
OOl~ POOll
0020 P0012
P001;;3
0021 POO14
0022
0023
BUFFER IN MAIN PGM
A \l
OFCI
SQZ
AV-*-l
I~JQ
-1
JMP*
LOOP
LOQil-
GVFL
ALS
1
U~~l
LR~
1
3000
gOOo.
ICEC
DVI
=NIO
OOFF AV~
OOOFP X
(AVG)
,JMP*
*
bE A \lE
A~JS~IER
COMP11lE AVERAGE
I
~I
A
A~JO
REMA I~IDER
I~I
Q
A~ID . RElIIR~1 lO CALLER
END
aDaIR Q"FL
0007X
OOOOP LOOR
o
G-17
0006P TEST
OOOCP
0001
NAM
DOD?
ENT
EXT
00 0 3
0004
0022
0005 POaoo
no"o
EQU
MOVf.
0006 POOOI CUt.D
0007 POO o 2 9C!f7
DOOR POOO] 90()O
POQOL!.
a(Itt 4
00 10 pon05
f'B??
0009
0
0
LDA-
$ED
5 11 8-
$F7
SU8
=N$44
IRA
LDA-
Q
0011 POOO6 ChF7
SUHTRACT OFF SIZE OF CONVR'
SO IT WONT GET MOVED
MOVLP
5T4-
6bFfi
0013 POOOR OOFE
INQ
0014 pnoog
50l
(,141
0015 POOOA 1 R~· B
0016 POoOH 0400 x
POOOC 7F FF
0017 PODOl) EDED
0018 paonE 0001
0019 POOOE ]622
0020
I
FIGURE OUT N WORDS
~;.
0012 P (, 0 07
MVFLAG
MOVE
MOVE
MVELAG
ZERO($22)
QaFF
oonex
ollT
JMP*
RAO+
($F7) ,Q
(:hEo) ,0
-1
0111-*-1
MOVLP
MVEI AG
X
MOVE
I D(,)INQ
IMPEND
OQQOP ZERO
$Eo
1
(ZERO)
MOVE IT
SET MOVED EI AG
FIGURE OUT ,JUMp ADDRESS
,0
,JlJMP TO MAIN
l'
'--.
0022
MO"lP
0006P 0' 'T
OOOBP
('
G-18
--'"
U
eQgl
0002 POOOO
P99gl
POOO2
QQQ;1 PCHHlJ
0004 POOO6
0003 POQ(lG
POOOO
OOO~ POOgg
POOOF
~JA~4
DOOl
~Hl
n1
PG'=I~
~HJ~
ij~~
0006
y 0 6~~
8UFl
RSS
SIG~~
~JUM
~11f:: (J)
AUFl(6)
~2~h $21;)
lA~
~JIIM
$30,~31,$32,$33,$34,$35,$36,$31,$38,$39
g~n:
GQ~PJRl
0
0
~+Q*
~AVgQ
002D
oo~O
0031
pgQIG
yOJ~
0033
OOJl,
0035
yGJe
0037
QQd~
0039
0001
0008 PO 0 lf~ OOUO
OOOQ POQIQ "~~9
0010 PODIA EIJFF
9911 P991B "
0
GQNVRl
SAVEQ(l),SAVEI{l),SAVEA{l)
00U1
POOll
PGGIt1
POO13
pg GIl,
POOl5
PQQls
P0017
0012 POOIC
QQl;;l PQGIQ
0014 POUIE
0015 POOIF
OOln POO20
gQl1 PQQ~1
001P. POO22
gQIQ PGQ~J
0020 POO24
Oggl PQO~;}
P0026
OO~g pggg1
0023 P0028
0024- 12002~
0025 P002A
002~ P0028
0027 POOcC
0028 ~OO~O
POO?E
0029 ~002~
0030 P0030
0031 120031
0032 POO32
OOJJ POOJ~
0034 POO34
OOJ5 1200JS
0036 P(j036
00J1 PClOJ1
003A POO38
0039 g0039
0040 POO3A
004] PO 0 '-\b
BSS
CONVRT
~E;9
oe42
I,
LOQ-
I
£+Q~
510 lJE; J
CLR
Q
j
F=
~+Q-
I
0122
OUOI
SAP
INQ
TCA
bQQ*
STQ*
bQQ*
STO*
bQQ
POS
-~J$gg
" I:HJ~
~+Q1i:
~11r::
48DF
STO*
SlQ*
STCJ*
CbR
SAZ
OHI
BUFI+2
611r::l '*=3
BUFl+4
bQQ-l!
STOilRAQJMP*
lA6,Q
~+Q-
I
5
Q~.
0864-
gAgA
4REH
PQ~
E;~gA
48£1
ggyQ
0020
4~Qr::
48DF
O~42
bQQP
0106
3000
1
A
~IG~J,Q
BUFl+5
+JH~:i: 0
BUFI
l:i: 1
Q
OUT
-~Il
0
aOUA
E:Ab)~
49U5
gO~r::
18FB
1.0 r:: r::
QkJ+
OCU5
C~lbh)
OFC8
QQFE;
8AeD
(;)9C9
DuFF
ilDf~
ENQ
~ACK
BUFI,I
I
LOOP
bg~*
QlJ~l,Q
ALS
8
-1
J ~JQ
ADD*
SltUt
RAOINQ
BUFl,Q
~11f::,
I
-1
()
G-19
I
SQM
JMPit
DO~JE
LOQJc
S.AVEQ
0045 POO3F CBel
LDA*
SAVEl
00 1 , (, P II 0" 0
STA
I
LOA
=XRUF
JMPit
(CONVRT)
00',2 POO:1G 01 11
0043 POOJD 1 Hf-(
00 /,/, POO3£ EgGl
DO~~E
bO~F
0047 P(1041 COOO
PO 0 /12 UOO3 f'
004R POO43 lC04
00 / ,9
I
SUFI
LOOP
(~
BACK
E~JD
gOfF SAVEQ
0006P SIGN
OOOOP SAVEl
OOOCP TAB
Q02fjP OUT
gY33P
~/\Cl:<
OOOlP SA'IEA
OOOEP CONVRT
OOJ5P
DO~JE
0002P BUf
0018P POS
0003P
002lP
QOJEP
ADDRESSES WHERE -------------------------PROGRAMS LOADED
AVERA.G
2392
MOVE
2347
MAP
1 Et>lTRY POINT T"tlLE-
~
MAIN
236C
X
MOVE
23ft7
AVG
2381'
MVFLAG'
239J
G-20
2391
CONVRT
23CF
c
TTY PRINTOUT
u
o
*
MI
*p
J
*K, 113, P6
J
*ASSEM
OPTIONS LX
J
*p
J
*L,8
J
*X
+ 4263 ~
+ 4263
J
Answers
MI
*p
J
*UTOPIA
E
*
CKDISK - ENTER CKD/ FOR HEADING
o
ADH, 15F9, 7 FFF /
95F8
ADH, 95F8, 65/
965D
ADH, 965D, 2/
965F
ADH, 965F, 100D/
A66C
ADH, A66C, 8/
A674
ADH, A674, 12/
A686
ADH, 4, A686/
A68A
ADH, A68A, 3/
A68D
G-21
utopia was used to sum the hex n urn be r s, to check out the answer. The sum is A68D 16 =
42637 10 • Divide by 10 10 for a decimal answer of 4263. The remainder 7 was not considered
when the answer was printed. Note that the numbers used did generate 'overflow in the sum,
thereby checking out the average routine. (The average routine would work only for positive
numbers. )
In analyzing and planning the move portion, the following s imp I e method could be used with
imaginary core addresses:
Core
Address.
~----+-----~--
1014
100B
100A
move 10 words
1001
1000
00F7
OOED
100A
-1000
100A
A
1014
+A
c
1000
100A
By drawing a simple picture to move only 10 words, beginning at 1001 and showing the contents of $ED and $F7 (which will be used for indirect addressing) it can be determined that the
program should subtract the contents of $F7 from $ED and use that answer, $A, for the index
in Q. The store through $ED would be analyzed the same way: ($ED) + $A = $1014. By
looking at the picture, one can see that Q should go from $A to 1; hence, the skip out of the
loop should be after the last move when Q equaled 1.
c
G-22
The actual addresses involved after loading were:
0
MOVE
-----AVERAG
------
second run:
CONVRT not moved
MAIN
23FB
CONVRT
23B7
-------
23AC
----AVERAG
------
2392
MOVE
first run
MAIN
236C
o
00F7
236B
OOED
23FA
23FA
-236B
8F
-44 CONVRT
4B moved
26
15
10
4B
The total number of locations involved was 8F16 • Less CONVRT, left 4B16 to move.
indexed from 4B16 (the last location in MOVE) through 1 (the first location in MAIN).
o
G-23
Q was
Solution to the AVG Reentrant Problem (11.3.2)
0001
0002
0003
0004
0005
0006
0007
0008
0009
-0010
0011
0012
0013
0014
0015
0016
0017
0018
0019
0020
0021
0022
0023
0024
0025
0026
0027
0028
0029
0030
0031
0032
0033
0034
0035
0036
0037
0038
0039
POOOO
POOOI
POO02
POO03
POO04
POO05
POO06
POO07
POO08
POO09
POOOA
POOOB
POOOC
POOOD
POOOE
POOOF
POOlO
POOll
POO12
POO13
POO14
POO15
POO16
POO17
POO18
P0019
POOlA
POOlB
POOlC
POOlD
POOlE
POOlF
P0020
P002l
P0022
P0023
NAM
ENT
EQU
OOBB
OOBA
0022
0002
0000
0500
54BB
0006
0400
C8FA
6103
0844
6104
FlOl
4i05
OlAO
E4FF
8622
01B2
Dl04
AOll
ODOI
4522
0852
Fl05
0141
l8F5
El04
OFCI
OF6l
3101
6101
4500
0000
Cl03
0500
68DF
54BA
0400
lCDC
5
4
:8
2
1
(1)+0
AVG
LOOP
TEST
DV
DIV
EXIT
0
lIN
RTJNUM
EIN
LDA*
STACLR
STAADQSTQSOV
LDQADDSNO
RAGANDINQ
STQTCQ
ADQSQZ
JMP*
LDQALS
LRS
DVISTASTQ+
LDAlIN
STA*
RTJEIN
JMP*
END
AVG
AVG
AVOLA($BB),AVOLR($BA), ZERO($22), LPMASK($2)
C~
0
(AVOLA)
6
AVG
3,1
A
4,1
1, I
5,1
0
(I)
(ZERO),Q
TEST-*-l
4,1
LPMASK+15
1
(ZERO), I
Q
5,1
DV-*-l
LOOP
4,1
1
1
1,1
1,1
0,1
SAVE RETURN ADDRESS
DIVIDE FOR AVERAGE
RETURN ANSWER IN A
RETURN REMAINDER IN Q
3,1
RESCUE RETURN ADDRESS
ZERO OVERFLOW CELL
LWA+l IN Q
SAVE IN VOLA+5
TURN OFF OVERFLOW
FWA IN Q
ADD DATA TOA
COUNT OVERFLOW
AND OUT SIGN BIT
UPDATE ADDRESS
SA VE NEXT ADDRESS
COMPLEMENT NEXT ADDRESS
ADD LWA+l
FINISHED WHEN MATCH
PICK UP OVERFLOW
SQUEEZE OUT SIGN BIT
C'
AVG
(AVOLR)
(AVG)
LWA+l
OVERFLOW
RETURN
I
A (N WORDS)
Q (FWA)
C~
G-24
The following routine, NAM A VGTST, was used to check out the subroutine to see if it returned the correct answer. It only checks the answer and does not check the reentrancy. It
asked AVG for an average of 9 words of a lO-word buffer X, and then punched the average 4
and remainder O.
The method used to run the routine in the background, since VOLA is a protected routine, was:
1.
Assemble and load AVGTST and AVG under MSOS. Do not execute yet.
2.
Turn off protect switch on console.
3.
Turn off disk (to protect the system).
4.
Set P on the console to the beginning address of AVGTST and RUN.
This method could be used to check out any r ou tin e in the background which links to system
routines in pro t e c ted core. If the system in core gets clobbered, the image on the disk is
intact.
o
o
G-25
c~
0001
0002
0003
0004
0005
0006
0007
0008
0009
0009
0009
0009
0009
0009
0010
0010
0010
0011
0012
0013
0014
POOOO
POOOI
POO02
POO03
POO04
POO05
POO06
OA09
EOOO
0011 P
5800 X
7FFFX
6816
4816
POO07
POO08
POO09
POOOA
POOOB
POOOD
54F4
0501
0008
0000
0003
0002
0013
POOOE
POOOF
P0010
P0011
POO12
POO13
POO14
POO15
POO16
POO17
POO18
POO19
P001A
P001B
54F4
OAOO
14EA
0000
0001
0002
0003
0004
0005
0006
0007
0008
0009
0002
BEGIN
XA
poooe
NAM
ENT
EXT*
ENA
LDQ
AVGTST
X, BEGIN
AVG
9
=XX
RTJ
AVG
STA*
STQ*
WRITE
TEMP
SAVE ANSWER
TEMP+1
SAVE REMAINDER
3, XB-XA-1, TEMP-XA-1, 2, B, 0, 1, A, X
NUMBER OF WORDS
BUFFER ADDRESS
EXIT
XB
X
JMPNUM
($EA)
0,1,2,3,4,5,6,7,8,9
TEMP
BSS
END
TEMP (2)
BEGIN
C
ANSWER: 4
C'
G-26
After tes ting out AVG to see if it gives an answer, it is then necessary to check out itsreentrancy. In the following computer run, two pro g ram s (PGMA and PGMB) were set up,
each to call AVG as a subroutine. Links and a flag were added to the routines for test purposes only. PGMA calls AVG and AVG begins its calculation. It then checks a flag and causes
a pseudo interrupt of itself, and c au s e s PGMB to begin its run. PGMB calls AVG, gets an
answer, punches it, and returns control back to the location in AVG where the pseudo interrupt
occurred. AVG completes its calculation for PGMA, returns to PGMA, and PGMA punches
its answer and hangs.
Again, the programs are loaded under MSOS. Then the protect switch and disk are turned off
while they execute.
This method could be used as a skeleton to check a routine's reentrancy.
The coding for testing reentrancy is marked by brackets in the example.
o
()
G-27
0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013
0014
0015
0016
0017
'P
~
00
00i8
0019
POOOO
POOOI
POO02
POO03
POO04
POO05
POO06
POO07
POO08
POO09
POOOA
POOOB
POOOC
POOOD
POOOE
POOOF
pool0
P0011
POO12
POO13
POO14
POO15
POO16
POO17
POO18
P0019
0000
OAOA
EOOO
OOOF P
5400 X
7FFFX
6813
54F4
0401
0000
0000
0003
oooi
00i9 P
i8FF
0000
0001
0002
0003
0004
0005
0006
0007
0008
0009
0001
PGMA
PGMA
PGNtA
AVG
0
10
NAM
ENT
EXT
0
ENA
LDQ
=xx
10 ~UMBERS
BUFFER ADDRESS X
RTJ+
AVO
COMPUTE AVERAGE
STA*
RTJNUM
ADC
NUM
NUM
NUM
ADC
NUM
X
NuM
ANS
($F4)
$0401
0
0
$0003
1
ANS
$18FF
0,1,2;3,4,5;6,7;8,9
ANS
BSS
END
ANS(l)
PGMA
PUNCH ANSWER
HANG
ANSWER: 4
~)
n
,
/
n
0
0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013
0014
0015
0016
0017
0018
0019
0020
0021
0022
0023
0024
0025
0026
0027
0
C')
0028
0029
0030
0031
0032
0033
0034
0035
0036
0037
0038
0039
0040
0041
0042
0043
0044
0045
0046
0047
0048
0049
0050
0051
0052
0053
0054
0055
0056
POOOO
POOOI
POO02
POO03
POO04
POO05
POO06
POO07
POO08
P.0009
POOOA
POOOB
POOOC
OOBB
OOBA
0022
0002
0000
0500
54BB
0007
0400
C8FA
6103
0844
6014
F101
4105
01AO
E4FF
'POOOD
POOOE
POOOF
P0010
P0011
POO12
POO13
POO14
6106
C820
0115
OA01
681D
C106
1400 :X
7FFFIx
POO15
P0016 .
C106
0000
POO17
POO18
POO19
P001A
POOIB
P001C
P001D
POOlE
POOIF
P0020
P0021
P0022
P0023
P0024
P0025
P0026
P0027
P0028
P0029
P002A
P002B
P002C
P002D
P002E
8622
01B2
D104
A011
OD01
4522
0852
F105
0141
18EB
E104
OFC1
OF61
3101
6101
4500
0000
C103
0500
68D5
54BA
0400
1CD2
0001
AVG
LOOP
*
*
*
C
FIN!
*
*
TEST
DV
DIV
EXIT
NAM
ENT
ENT
EXT
EQU
AVG
AVG
FIN!
PGMB
AVOLA ($BB) , AVOLR ($BA), ZERO($22), LPMASK($2)
0
!IN
RTJNUM
EIN
LDA*
STACLR
STAADQSTQSOY
LDQ-
0
AVG
3,1
A
4, I
1,1
5,1
0
(I)
STALDA*
SAN
ENA
STA*
LDAJMP+
6,1
FLAG
C
1
FLAG
6,1
PGMB
LDA0
6,1
0
ADDSNO
RAOANDINQ
STQTCQ
ADQSQZ
JMP*
LDQALS
LRS
DVISTASTQ+
(ZERO),Q
TEST-*-l
4, I
LPMASK+15
1
(ZERO), I
Q
5,1
DV-*-l
LOOP
4, I
1
1
1,1
1,1
0,1
LDA!IN
STA*
RTJEIN
JMP*
BZS
END
3, I
(AVOLA)
7
AVG
(AVOLR)
(AVG)
FLAG(l)
G-29
ONE MORE WORD VOLATILE
NEEDED
FIRST OR SECOND CALL?
RETURN AFTER INTERRUPT
ANSWERS:
3
4
r-'
0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013
0014
0015
0016
0017
0018
0019
0020
0021
0022
0023
0024
0025
0026
0027
POOOO
POOOI
POO02
POO03
POO04
POO05
POO06
POO07
POO08
POO09
POOOA
POOOB
POOOC
POOOD
POOOE
POOOF
P0010
P0011
POO12
POO13
POO14
POO15
POO16
POO17
POO18
POO19
P001A
P001B
P001C
P001D
POOlE
P001F
P0020
P0021
P0022
P0023
0000
6817
4814
COFF
680F
NAM
ENT
EXT
0
STA*
STQ*
LDASTA*
ENA
LDQ
SA+!
}
SQ+1
I
SI+1
8
=XX
RTJ+
AVG
SI
STA*
RTJNUM
ADC
NUM
NUM
NUM
ADC
LDA
ANS
($F4)
$0401
0
0
$0003
1
ANS
=NO
SQ
STALDQ
I
=NO
SA
LDA
=NO
JMP+
FIN!
X
NUM
0, 1,2,3,4,5,6,7
ANS
BSS
END
ANS(l)
PGMB
OA08
EOOO
001B P
5400 X
7FFFX
6819
54F4
0401
0000
0000
0003
0001
0023 P
COOO
0000
60FF
EOOO
0000
COOOO
0000
1400 X
7FFFX
0000
0001
0002
0003
0004,
0005
0006
0007
0001
~---'
PGMB
PGMB
AVG, FINI
0
SAVE REGISTERS
8 NUMBERS
BUFFER ADDRESS X
COMPUTE AVERAGE
PUNCH AmWER
RESTORE REGISTERS~
,,--.,'
)
RETURN TO AVG
ANSWER: 3
(~
.......
-
Another possible solution would be:
()
AVG
LOOP
C'
TEST
DV
DIV
EXIT
o
NAM
ENT
EQU
EQU
0
IIN
RTJNUM
E1N
LDA*
STA-
AVG
AVG
A VOLA($BB), A VOLR($BA), ZERO($22)
LPMASK($2),ONEB1T($23)
0
LDAEORSTACLR
STALDQINQ
ADDSNO
RAOANDSQZ
INQ
JMP*
LDQALS
LRS
DV1STASTQ+
LDAIIN
STA*
LDA.ANDSTARTJEIN
JMP*
END
I
ONEB1T+15
I
A
4,1
1,1
-1
(I), Q
TEST-*-1
4,1
LPMASK+15
DV-*-1
-1
LOOP
4,1
1
1
1, I
1,1
0, I
3,1
(AVOLA)
5
AVG
3,1
AVG
1
LPMASK+15
1
(AVOLR)
(AVG)
The indirect bit on the contents of I causes proper addressing to be used to add up the buffer.
Only 15 bits of the address are used for the direct addressing used to access the other volatile
locations.
G-31
SOLUTION TO THREAD PROBLEM. (11.4.3.3)
Solution: Never.
The problem here is that the programmer thinks the request priority of 14 will override the
running priority of 12, but this is not so. It is the driver's priority which must be considered,
and the slow-equipment drivers usually run at 10. So, since the requestis threaded as
highest priority (14) on the queue for the logical unit (TTY,4) and will be processed when the
driver gets to run at its p rio ri ty (10), the write will never be done. This is because the
running program is hung in a loop at priority 12, waiting for an event which cannot occur (the
thread word becoming zero) because the loop at 12 is locking out the driver.
Process programs usually run at 4, 5, and 6 (below the drivers); this would eli min ate the
problem in the example program. However, any looping like this at any priority is going to
slow down a system by locking out lower priorities. For example, if many process programs
were coded this way, they could a 1m 0 s t completely lock out job processing (which runs at 0
and 1). It would be much better to code the write as follows, if it mus t run at 12:
EQU
~
OK
COMPL
RTJNUM
ADC
NUM
NUM
NUM
ADC
SQP
JMP
JMP-
ADISP($EA)
($F4)
$OCED
COMPL
0
$18FC
35
BUF
OK-*-l
REJ
(ADISP)
G-32
FWRITE, RP=14, CP=13
C
o
SOLUTION TO MMPGM PROBLEM.
(11. 5.7)
Note that afte~ the FWRITE is initiated (at P0017), the program return jumps to CORSUB and
then schedules SYSPGM. CORSUB will run at the calling program's priority (4). Then, since
SYSPGM is scheduled to run at 4 also, it will r')t begin until MMPGM is finished. (This is
per f e c t I y legal, as long as SYSPGM does not need any of the data in MMPGM and does not
store anything in MMPGM.) At P001C a jump is then made to the dispatcher to a w a i t completion of the 1/0. This all looks very good.
However, the 110 has been going on concurrently and the driver runs at a very high priority
(usually 10). If by any chance it finishes the write and t r an sf e r s control to the completion
routine WROTE (at P001D) at priority 6 before the RTJ+ CORSUB and the schedule for SYSPGM
are finished, the space MMPGM is in will be released. Surprise!
This is quite possible because other system programs at intermediate priorities (i. e., 7 and
9) could be locking out the MMPGM at 4, yet the driver at 10 would be plod din g away at its
write. Naturally the completion at 6 will be done (after the 7 and 8 are finished) be for e the
p rio r i t Y drops back down to 4 to try to do the return jump to CORSUB and the schedule request, which, of course, aren't there any more.
The word on mass memory coding is: Be careful, and think!
o
o
G-33
A possible correction for the program would be:
ADISP
MMPGM
MSGBUF
WRITE
REQOK
WROTE
REL
NAM
ENT
EXT *
EXT
EXT
EQU
NUM
STA*
JMP*
ALF
FWRITE
SQP
RTJ
RTJ+
JMPSQP
RTJ
SCHDLE
SQP
RTJ
SCHDLE
SQP
RTJ
JMPRELEAS
END
MMPGM
MMPGM
REQREJ,IOERR
CORSUB
SYSPGM
ADISP($EA)
$C8FE
REL+2
WRITE
*,MASS MEMORY EXAMPLE*
$FC, WROTE-*+l, MSGBUF-*+5, 10, A, 5,6, I, X
REQOK-*-l
REQREJ
CORSUB
(ADISP)
2
IOERR
REL,4,X
2
REQREJ
(SYSPGM), 4,
°
2
REQREJ
(ADISP)
0, T,
MMPGM
°
In this solution, if the completion routine is entered before the RTJ+ to CORSUB is finished,
REL and SYSPGM will be put on the scheduler stack to be executed after the completion exit
to the dispatcher allows MMPGM to be picked up from the interrupt stack.
Another possible correction to the program, perhaps better, would be s imp I y to change the
completion priority in the FWRITE request from 6 to 3. That would insure that any priority 4
work would be finished before the release is executed. However, this would cause the space
MMPGM is in to be tied up until SYSPGM is finished, which was not the intent.
G-34
C--:
C~
APPENDIX H
o
c
c)
::q
I
I-'
********pp********
0001
0002
********Op********
********UD********
0003 POOOO 0000
********OP********
********UD********
0004 P0001 0000
0000
0005
0006
0000 OBOO
0007
0001 7FFF X
0008
OOFE
0009
OOFE OOBD P
0010
OOFF 0000
0100 0000
0011
0012
0002 P
0013 P0002 0000
0014
0015
0016
0017
0018
0019
0020 P0003 COFE
0021 P0004 C2FE
0022 P0005 C1FE
0023 P0006 C3FE
0024 P0007 C020
0025 P0008 C014
********FX********
0026 P0009 COOO
********PL********
0027 POOOA C002
********RL********
0028 POOOB COlO
* * ** ** * *RL* ** * ** **
0029 POOOC COOO
********UD********
0030 POOOD COOO
n
*p
*ASSEM
NAM
LOWCOR
TEMP1
INDEX2
ABSRNG
RELOW
*
*
*
*
*
*LABEL*
NAM
ORG
NOP
0
ORG
0
0
0
ORG*
0
1700
ADDRESSING EXAMPLES
ASSEMBLED UNDER MSOS 2. 0
OCT. 1968
C.'
L
DAN
0
SET ABSOLUTE ADDRESS
DPNDNT
$FE
ANYWHR
0
0
EXTERNAL SYMBOL
RE-SET ABSOLUTE ADDRESS
0
1700 ASSEMBLY EXAMPLES
********STORAGE REFERENCE********
**GROUP 1**
EVALUATION OF ADDRESS FIELD RESULTS IN DESIRED OPERAND ADDRESS
*ABSOLUTE*
*DESCRIPTION*
*BA*
*EFA*
*OPN*
*ADDRESS*
TEMP1 TEMP1
LDATEMPI
NO INDEXING
TEMPI TEMP1+(Q)
LDAQ INDEXING
TEMP1, Q
LDATEMPI TEMP1 +(OOFF)
TEMP1, I
I INDEXING
LDATEMPI TEMP1+(Q)+(00FI
TEMPI, B
DOUBLE INDEXING
LDA$20
NUMERIC HEX EXAMPLE 20 HEX 20 HEX
LDA20
NUMERIC DEC EXAMPLE 20 HEX 20 DEC
LDA-
ABSRNG
LDA-
RELOW
PROGRAM RELOCATABLE ADDRESS
LDA-
BLOCK6
DATA RELOCATABLE ADDRESS
LDA-
BLOCK3
COMMON RELOCATABLE
LDA-
UNDEFINED
UNDEFINED SYMBOL
4DELTA OUT OF RANGE
~
0032
0033
0034 POOOE C822
0035 POOOF CA21
0036 P0010 CB20
0037 P0011 C8FC
0038 P0012 C8FD
0039 P0013 181D
********RL********
0040 P0014 C017
* ** * ** **RL* ** * ** **
0041 P0015 COlO
* ** *** **RL***** ***
0042 P0016 COOOO
*RELATIVE*
*
*LABEL* *OPN*
*ADDRESS*
BAKREL
LDA*
RELADR
LDA*
RELADR,Q
LDA*
RELADR,B
LDA*
BAKREL
LDA*
*-2
JMP*
RELADR
********FX********
0043 P0017 COA6
*DESCRIPTION*
DELTA=RELADR+(-*)
DE L T A= RE LADR+ (- *)
DELTA=RELADR+(-*)
DELTA=BAKREL+(-*)
DELTA+*-2+(-*)
JUMP ADDRESS=EFA
*BA*
RELADR
RELADR
RELADR
BAKREL
*-2
RELADR
LDA*
TAGLRM-BAKREL
FORM RELATIVE ADDRESS
LDA*
$10
ABSOLUTE ADDRESS
LDA*
ABSRNG
ABSOLUTE ADDRESS
LDA*
ANYWHR
DELTA OUT OF RANGE
*EFA*
RELADR
RELADR+(Q)
RELADR+(Q)+(OOFF)
BAKREL
*-2
RELADR
p::
I
l\:)
0045
0046
0047
0048
0049
0050
0051
0052
0053
0054
0055
0056
(~
P0018
P0019
P001A
P001B
P001C
P001D
POOlE
P001F
P0020
P0021
P0022
P0023
P0024
P0025
C800
0017
C800
00A2
CAOO
OOAO
5800
009E
C400
OOFE
C400
0500
C800
0000
****CONTINUATION OF STORAGE REFERENCE****
*
****GROUP 1****
*
*LONG
RELATIVE*
*
*ADDRESS*
*DESCRIPTION*
*LABEL* *OPN
*BA*
*EFA*
M=RELADR+(-*. +1)
LDA
RELADR
RELADR
RELADR
TAGLRM
LDA
ANYWHR
M=16 BIT REL ADDRESS
LDA
ANYWHR,Q
Q INDEXING
ANYWHR
ANYWHR+(Q)
RTJ
ANYWHR
JUMP ADDRESS=EFA
ANYWHR
ANYWHR
LDA
TEMP1
ABSOLUTE ADDRESS, ASSEMBLED AS STORAGE
LDA
$500
ASSEMBLED AS STORAGE MODE
LDA*
0
*
0
WORD ONE OF LONG RELATIVE
WORD TWO OF LONG RELATIVE
(\
)
ANYWHR ANYWHR
n
0
0
0058
0059
0060
0061
0062
0063
0064
0065
~
I
~
0067
0068
0069
0070
0071
0072
0073
0074
0075
0076
0077
0079
0080
0081
0082
0083
0084
0086
0087
0088
0089
0090
P0026
P0027
P0028
P0029
P002A
P002B
P002C
P002D
P002E
P002F
C400
OOBD P
C600
OOBD P
C700
0500
C400
0000
5400
OOBD P
P0030 C4FE
P0031 C4FF
P0032 C420
P0033 14FE
P0034
P0035
P0036
P0037
P0038
P0039
P003A
P003B
C600
8027 P
C700
802B P
C400
8700
5400
8027 P
P003C CCEA
P003D CDED
P003F CFF6
*STORAGE*
*
*LABEL* *OPN*
BACIND
LDA+
("
"--'
*ADDRESS*
ANYWHR
*DESCRIPTION*
2ND WORD=ANYWHR
*BA*
ANYWHR
*EFA*
ANYWHR
LDA+
ANYWHR,Q
Q INDEXING
ANYWHR
ANYWRR+(Q)
MEMADR
LDA+
$500, B
NUMERIC EXAMPLE
$500
$500+(Q)+(00FF)
TAGSM
LDA0
RTJ+
(0)
0
ANYWHR
WORD ONE Of!' ~TORAGE MODE
WORD TWO OF STORAGE MODE
ANYWHR
JUMP ADDRESS=EFA
ANYWHR
*
*
EVALUATION OF ADDRESS FIELD RESULTS IN DESIRED ADDRESS OF OPERAND ADDRESS
*
*INDIRECT*
*
*ADDRESS*
*DESCRIPTION*
*BA*
*EFA*
*LABEL* *OPN*
(TEMPI)
(TEMPI)
LDADELTA=TEMPI
(TEMPI)
RELADR
(TEMPl)+(Q)
LDADELTA=TEMPI
(TEMPI)
(TEMPl),Q
*
(TEMPI)
(TEMPI )+(Q)+(OO FF)
LDADELTA=TEMPI
. (TEMPl),B
*
DELTA=TEMPI +1
(TEMPl+l) (TEMPl+l)
LDA(TEMPl+l)
($20)
($20)
LDADELTA=$20
($20)
JMPJUMP ADDRESS=EFA
(TEMPI)
ANYWHR
(TEMPI)
*STORAGE INDIRECT*
*
*ADDRESS*
*LABEL* *OPN*
LDA+
(BACIND+l), Q
RELIND
*DESCRIPTION*
2ND WORD=BACIND+l
*EFA*
*BA*
(BACIND+l) ANYWHR+(Q)
(MEMADR+l)
LDA+
(MEMADR+l), B 2ND WORD=MEMADR+l
LDA+
($700)
NUMERIC EXAMPLE
($700)
RTJ+
(BACIND+l)
JUMP ADDRESS=EFA
(BACIND+l)
*RELA TIVE INDIRECT*
*
*ADDRESS*
*LABEL* *OPN
(BACIND+l)
LDA*
(MEMADR+l),
I
LDA*
(RELIND+l), B
LDA*
*DESCRIPTION*
DELTA=BACIND+1 +(-*)
DELTA=MEMADR+1 +(-*)
DELTA=RELIND+1 +(-*)
$500+(Q)+(00 FF)
($700)
ANYWHR
*BA*
*EFA*
(BACIND+l)
ANYWHR
(MEMADR+l)
$500+(00FF)
(RELIND+l) ANYWHR+(Q)+(OOFF)
0092
0093
0094
0095
0096
P003F
P0040
P0041
P0042
P0043
P0044
CCOO
FFE6
CEOO
007B
C400
8700
(ANYWHR)
(ANYWHR)+(Q)
LDA
($700)
ASSEMBLED AS STORAGE INDIRECT
*CONSTANT*
*
*ADDRESS*
*LABEL* *OPN*
LDA
=N1000
/
*EFA*
ANYWHR
16 BIT REL ADDRESS
0103
0104
0105
f\
I
*BA*
(BACIND+1)
(ANYWHR),Q
*
*
*
*
TAGCM
*DESCRIPTION*
M=BACKIND+(-*)+l
LDA
0098
0099
0100
0101
P0045 COOO
P0046 03E8
0106 P0047 COOO
P0048 1000
0107 P0049 COOO
P004A EFFF
0108 P004B COOO
P004C 0026 P
0109 P004D COOO
P004E 7FD9-P
0110 P004F COOO
P0050 4243
0111 P0051 C200
P0052 1000
0112 P0053 COOO
0113 P0054 0000
********EX********
0114 P0055 6400
P0056 0000
0115 P0057 COOO
P0058 7FFB
0116 P0059 COOO
P005A 8026 P
~
I
..p..
*LONG RELATIVE INDIRECT*
*
*LABEL* *OPN*
*ADDRESS*
LDA
(BACIND+1)
****CONTINUATION OF STORAGE REFERENCE****
****GROUP 3****
EVALUATION OF ADDRESS FIELD RESULTS IN DESIRED OPERAND
N = NUMERIC
X = ADDRESS
A = ALPHANUMERIC
*DESCRIPTION*
*BA*
NUMERIC EXAMPLE DEC P+1
*EFA*
P+1
LDA
=N$1000
NUMERIC EXAMPLE HEX P+1
P+1
LDA
=N-$1000
NUMERIC EXAMPLE NEG P+1
P+1·
LDA
=XBACIND
ADDRESS EXAMPLE
P+1
P+1
LDA
=X-BACIND
ADDRESS EXAMPLE NEG P+1
P+1
LDA
=ABC
ALPHA EXAMPLE
P+1
LDA
=N$1000, Q
RA=(P+1) *INDEXING* $1000
LDA0
0
0
WORD ONE OF CONSTANT MODE
WORD TWO OF CONSTANT
STA
=N$O
ASSEMBLER WILL NOT ALLOW
LDA
=X-4
NUMERIC WITH ADDRESS INDICATOR
LDA
=X(BACIND)
SET INDIRECT BIT ON ADDRESS VALUE
f)
P+1
OPERAND
.r----"'\
/'
o
0118
0119
0120
0121
0122
0123
0124
0125
01 ~(i
01~7
01~H
0129
0130
0131
o
*
*
*LABEL*
P005B
P005C
P005D
P005E
P005F
P0060
P0061
1>0062
0847
080C
0811
0823
081C
0801
0854
0834
POO():~ 086A
POO()--! 08B2
POOG5 08F4
c~
********REGISTER TRANSFER********
EVALUATION OF ADDRESS FIELD RESULTS IN DESIRED DESTINATION HEGISTER
*OPN*
*ADDHESS*
*DESCRIPTION*
CLR
A,Q,1\'1
CLEAH A Q AND 1\1 REGISTERS
THlVl
A
TRANSFER 1\'1 TO A
TRQ
M
TRANSFER Q TO M
Q,M
TAA
TRANSFER A TO Q AND 1\1
A
TRB
TRANSFER INCLUSIVE OR OF M Q TO A
SET
M
SET M TO ALL ONES
TCQ
A
TRANSFER THE COMPLEMENT OF Q TO A
A
AAQ
TRANSFER SUM OF A Q TO A
EAM
Q
TRANSFER EXCLUSIVE OR OF A M TO Q
LAQ
TRANSFER LOGICAL AND OF A Q TO Q
Q
CAQ
A
TRANSFER COMPLEMENT OF LOGICAL AND OF A Q TO A
*****~~~EX********
0132
P0066 0820
0134
~, 0135
01
0136
0137 P0067 0105
0138 P006H 0156
0139 P0069 0115
-1- *******EX* * ******
0140 P006A 0120
. ********EX********
0141 P006B 013A
0143
0144
0145
0146
0147
0148
0149
0150
0151
0152
TAA
*
*
*LABEL*
*
*
*LABEL*
P006C
P006D
P006E
P006F
P0070
P0071
P0072
OFAC
OFD2
OF7F
OBOA
OF53
OF5F
OFDA
SKI PAD
x
ILLEGAL DESTINATION REGISTER
********SKIPS********
EVALUATION OF ADDRESS FIELD RESULTS IN DESIRED SKIP COUNT
*OPN*
*ADDRESS*
*DESCRIPTION*
SAZ
5
IF(A) IS 0 SKIP FORWARD 6 PLACES ++l+SKIPCOUNT
SKI PAD .. *-1
SQN
IF(Q) NEG SKIP TO SKIPAD (NON ABSOLUTE METHOD)
SAN
SKI PAD
SKIP COUNT OUT OF RANGE
SAP
$10
SKIP COUNT OUT OF RANGE
SAM
-5
NEG SKIP COUNT
********SHIFTS********
EVALUATION OF ADDRESS FIELD RESULTS IN DESIRED SIDFT COUNT
*OPN*
*ADDRESS*
*DESCRIPTION*
12
QLS
LEFT SHIFT Q 12 DECIMAL POSITIONS
ALS
LEFT SIDFT A 12 HEX POSITIONS
$12
31
RIGHT SHIFT Q/ A 31 DECIMAL POSITIONS (31:::: MAX)
LRS
10
NOP
WAIT XX MICROSECONDS
ARB
SHIFT COUNT GREATER THAN $31
$33
DELTA
SYMBOLIC SHIFT COUNT
ARB
ALS
NEG SHIFT' COUNT
-5
~
I
m
0154
0155
0156
0157 P0073 OA75
0158 P0074 OCEA
0159 P0075 OA7F
********EX********
0160 P0076 OA80
********EX********
0161 P0077 OA01
0162 P0078 OA1F
0163 P0079 OAEO
********EX********
0164 P007 A OAFF
********EX********
0165 P007B OA02
********EX********
0166 P007C OA10
********EX********
0167 P007D OAOO
0168 P007E 09FE
0169 P007F OD25
0170 P0080 0206
********EX********
0171 P0081 0287
0172 P0082 0400
0173 P0083 0500
0174 P0084 OE04
0175 P0085 0600
0176 P0086 0700
0177 P0087 0000
0178
00lF
r,
*
*
EVALUATION OF ADDRESS FIELD RESULTS IN VARIOUS PORTIONS OF ASSEMBLED INSTS
*ADDRESS*
*LABEL* *OPN*
*DESCRIPTION*
$75
ENA
ENTER A WITH VALUE SPECIFIED IN ADDRESS FIELD
-$15
ENQ
NEG EXAMPLE
127
DEC EXAMPLE (MAX VALUE)
ENA
REJCTA
ENA
128
NEG.
ENA
ENA
ENA
257
DELTA
-DELTA
OUT OF RANGE NUMERIC VALUE
POSe SYMBOLIC VALUE
NEG. SYMBOLIC VALUE
ENA
INDEX2
NEG.
ENA
RELOW
PROGRAM RELOCATABLE VALUE
ENA
BLOCK6
DATA RELOCATABLE VALUE
ENA
INA
INQ
INP
BLOCK3
-1
COMMON RELOCATABLE VALUE
INCREASE A BY THE VALUE SPECIFIED IN ADDRESS FD
INCREASE Q
INPUT TO A REJECT ADDRESS-P+1+DELTA
INP
EIN
IIN
EXI
SPB
CPB
SLS
EQU
$25
REJCTA-*-l
REJCTA
o
o
4
o
o
o
DELTA($lF)
f)
NUMERIC VALUE
SYMBOLIC VALUE
DELT OUT OF RANGE
ENABLE INTERRUPT SYSTEM
INHIBIT INTERRUPT SYSTEM
EXIT INTEHRUPT ADDRESS FIELD = INTERRUPT
SET PROTECT BIT (Q) = ADDRESS
CLEAR PROTECT BIT (Q) = ADDRESS
STOP IF STOP KEY SET
EQUATE SYlVIBOLIC VALUE FOR ABOVE USE
r--"',
.
j
o
C)
0180
0181
0182
0183
0184
0185
0186
0187
::c:
I
..::J
0189
0190
0191
0192
0193
0195
0196
0197
0198
P0088 0030 P
P0089 0026 P
P008A 802A P
POO~B 7FCF-P
P008C 7FFO
P008D
P008E
P008F
P0090
1000
03E8
EFFF
FF9B
C)
********CLASS 2 PSEUDOS********
*
*
*ADC* ADDRESS CONSTANT PSEUDO
*
THE ADDRESS EXPRESSIONS IN SUBFIELD ARE ASSEMBLED INTO CONSECUTIVE CELL
*
LOCATIONS. IF ADDRESS EXPRESSION IS ENCLOSED IN PARENTHESIS THE ADDRESS
*
BECOMES INDIRECT.
*LABEL* *OPN*
*ADDRESS*
ADLIST
ADC
RELADR, BACIND, (MEMADR), -RELADR
o
-$F
TREATED AS ONE WORD ADC
*
*NUM*NUMERIC CONSTANT PSEUDO
*
THE NUMERIC EXPRESSIONS IN SUBFIELD ARE ASSEMBLED INTO CONSECUTIVE CELL
*
LOCATIONS. THE CONSTANTS CAN BE EITHER DECIMAL OR HEX VALUES.
*LABEL*
*OPN*
*ADDRESS*
CONLST
NUM
$1000, 1000, -$1000, -100
*
*ALF* ALPHANUMERIC MESSAGE PSEUDO
*
THE ADDRESS FIELD CONTAINS THE NUMBER OF CELLS TO BE RESERVED FOR THE
*
REMAINING CHARACTERS IN FIELD.
*LABEL* *OPN*
*ADDRESS*
~
I
00
0200
0201
0202
0203
0204
0205
*
*
*
*
*
*****CONTINUATION OF CLASS 2 PSEUDOS*****
*ENT* ENTRY PSEUDO
TillS PSEUDO WILL CAUSE A BINARY OUTPUT WHICH WILL ALLOW -EXTERNAL
SYMBOLS OF OTHER PROGRAMS TO BE DEFINED AT *LOAD TIME*
*ADDRESS*
*OPN*
START, BACIND
ENT
0207
0208
0209
0210
0211
0212
0213
*
*
*
*
*EXT* EXTERNAL PSEUDO
TillS PSEUDO WILL ALLOW SYMBOLIC VALUES UNDEFINED IN THE INDEPENDENT
PROGRAM TO BE MATCHED WITH ENTRY VALUES AND DEFINED AT LOAD TIME.
*OPN*
*ADDRESS*
*DESCRIPTION* ,
EXT
DPNDNT
DPNDNT WILL BE MATCHED WITH ENTRY POINT
AT LOAD TIME.
RTJ
DPNDNT
DPNDNT IS UNDEFINED IN CURRENT ROUTINE
P0091 5400 X
P0092 0001 X
0214 P0093 OBOO
0215 P0094 5400 X
P0095 0092 X
0216 P0096 OBOO
0217 P0097 5401
0218 P0098 OBOO
********EX********
0219 P0099 5400 X
0220 P009A OBOO
********EX********
0221 P009B 5000 X
r~)
I
*
NOP
RTJ
NOP
RTJNOP
DPNDNT
ASSEMBLED AS STORAGE
(LOWCOR)
INDIRECT LINKING
RTJ*
NOP
DPNDNT
RTJ-
DPNDNT
/\
I
r~
o
f --"
U
0223
0224
0225
0226
0227
0228
0230
0231
0232
0233
0234
0235
0236
0237
~
I
c.o
0239
0240
0241
0242
0243
0244
0246
0247
0248
0249
0250
0251
0253
0254
0255
0256
0257
0258
****CLASS 3 PSEUDOS****
*EQU* EQUATE PSEUDO
TillS PSEUDO WILL CAUSE A SYMBOLIC VALUE TO BE EQUATED TO ANOTHER
SYMBOLIC VALUE OR TO A NUMERIC VALUE AND PLACED IN SYMBOL TABLE.
*ADDRESS*
*OPN*
START($100), HERE(*)
EQU
*
*
*BSS*
*LABEL*
P009C OBOO
P009D 0010
POOAD OBOO
BLOCK STORE PSEUDO
TillS PSEUDO WILL CAUSE A RESERVATION OF THE NUMBER OF CELLS SPECIFIED
BY THE VALUE IN THE ADDRESS FIELD. THE CONTENTS OF THESE CELLS WILL BE
UNCHANGED AT LOAD TIME.
*DESCRIPTION*
*OPN*
*ADDRESS*
o
INDICATOR TO SHOW CURRENT ADDRESS
NOP
BLOCK8($10)
BSS
o
INDICATOR TO SHOW CURRENT ADDRESS
NOP
*
*BZS* BLOCK ZERO STORE PSEUDO
*
SAME AS BSS EXCEPT CELLS WILL BE SET TO ZERO AT LOAD TIME.
*LABEL* *OPN*
*ADDRESS*
*DESCRIPTION*
o
NOP
INDICATOR TO SHOW CURRENT ADDRESS
BZS
BLOCK2
BLOCK9($5)
o
NOP
INDICATOR TO SHOW CURRENT ADDRESS
*
*
*
*
*
*COM* COMMON STORAGE PSEUDO
THE NAME OF THE BLOCKS AND THE SIZE ARE DEFINED IN THE ADDRESS FIELD
OF PSEUDO. THE STORAGE AREA WILL BE ASSIGNED TO THE AREA OF THE
LOADER AT LOAD TIME.
*ADDRESS*
*DESCRIPTION*
*OPN*
COM
BLOCK3($30), BLOCK4($100)
BLOCK4=BLOCK3+$30
*
*
*
*
*DAT* DATA STORAGE PSEUDO
THE METHOD OF RESERVATION IS THE SAME AS COM EXCEPT THE AREA CAN
BE PRESET.
*ADDRESS*
*DESCRIPTIQN*
*OPN*
DAT
BLOCK5($10), BLOCK6($20*$20)
0000 C
0030 C
0000 D
0010 D
POOB5 OBOO
,-.-/
*
*
*
*
*
0100
009C P
POOAE OBOO
POOAF 0005
POOB4 OBOO
(--\
NOP
o
INDICATOR TO SHOW CURRENT ADDRESS
0260
0261
METHODS OF PRESETTING DATA IN DATA AREA
ALSO SHOWN IS ILLEGAL USE OF COMM AREA
*
*
0000 D
DOOOO 0088 P
DOOOI 002A P
D0002 008D P
D0003 009C P
********UD********
D0004 8000
0265 D0005 0001
D0006 0002
D0007 0003
D0008 0004
D0009 0005
00B6 P
0266
0267 POOB6 OBOO
*** * ** **RL*** * ** **
0268
0000
0269 POOB7 0001
POOB8 0002
POOB9 0003
POOBA 0004
POOBB 0005
0263
0264
~
I
I-'
0
0271
0272
0273
0274
0275
0276
*
*
*
*
*
*
0278
0279
*
*
()
NAM
ORG
ADC
PRESET TO DATA AREA
BLOCK5
ADLIST, MEMADR, CONLST, HERE, (WORD2A)
NUM
1,2,3,4,5
ORG*
NOP
0
0
RESET TO NORMAL COUNTER
INDICA TOR TO SHOW CURRENT ADDRESS
ORG
NUM
BLOCK3
1,2,3,4, 5
SET COUNTER TO COMMON AREA
ILLEGAL TO SET DATA IN COMMON
********CLASS 1 PSEUDOS********
NAME PSEUDO
THE NUMERIC VALUE IN LABEL FIELD WILL SET PROGRAM COUNTER TO AN
ABSOLUTE VALUE. THE ADDRESS FIELD CONTAINS THE PROGRAM NAME.
ONLY ONE NAM ALLOWED PER PROGRAM. NAM IS USED TO IDENTIFY INDEPENDENT PROGRAMS.
ORG PROGRAM COUNTER CONTROL PSEUDO
COUNTER. IF NUMERIC IS USED PROGRAM WILL BE ASSEMBLED ABSOLUTE.
.f\
(\
n
r-)
l
•
l
0281
0282
0283
0284
0285
*
*
*
POOBC OBOO
0287
ORG* RETURN PROGRAM COUNTER PSEUDO
USED TO RETURN COUNTER TO NORMAL VALUE
*DESCRIPTION*
*ADDRESS*
*OPN*
ORG*
o
INDICATOR TO SHOW CURRENT ADDRESS
NOP
EQU
OOBD P
*
*
*
*
0289
0290
0291
0292
0293
0294
0295
*
*
(':
ANYWHR(*)
*END* END PSEUDO
MUST BE LAST CARD OF EACH PROGRAM, SYMBOL IN ADDRESS FIELD IS THE
ADDRESS CONTROL WILL BE TRANSFERRED TO AT LOAD TIME.
*ADDRESS*
*OPN*
END
START
T
t-l
t-l
I
RELOW
TAGSM
REJCTA
HERE
BLOCK5
030 ERRORS
OOFF
0002P
0002DP
0087P
009CP
OOOOD
LOWCOR
BAKREL
RELADR
DELTA
BLOCK8
BLOCK6
0001
OOOEP
0030P
001F
009DP
0010D
TEMPI
TAGLRM
RELIND
ADLIST
BLOCK9
ANYWHR
OOFE
0025P
0034P
0088P
OOAFP
OOBDP
INDEX2
BACIND
TAGCM
CONLST
BLOCK3
DPNDNT
OOFF
0026P
0054P
008DP
OOOOC
0095X
ABSRNG
MEMADR
SKI PAD
START
BLOCK4
0100
002AP
006FP
0100
0030C
c-
APPENDIX I
c-
'''-''-/
'-...
APPENDIX I
COMMUNICATION REGION
The communication region is the area of core below FF16. It can be addressed directly by a
one-word instruction. Contents are defined by the follow i n g table. All locations are protected except as noted. EQU names are noted also.
Contents
",Location
o &1
LPMASK
Reserved for the system
0000000000000000
0000000000000001
0000000000000011
0000000000000111
.
...
HEX Equivalent
2
3'.
4
5.
___
a~.
• __ ._.,. ___
.~
.... _____
._K"--"'~'
OOOOOOOOOOOOllll~
-. _. --' ."....
.-, .-.. __J',~.
..~
-.~.~~.
7
000000000001111Jl
8
000000000011111~
I-.~..... _.~ .... ~
9'·
0000000001111111
0000000011111111
B
0000000111111111
C
0000001111111111
l)
0000011111111111
0000111111111111
E
0001111111111111
E
l(t
0011111111111111
.---l-L-_--------..---Jf~~_!!!.!!!lJJlJl~.--.. .12
1111111111111111
.......... _--' _.....
13
111111111111111~
14
1111111111111100
15
1111111111111000
16
1111111111110000
17
1111111111100000
18
1111111111000000
19
1111111110000000
1A
1111111100000000
1B
1111111000000000
1C
1111110000000000
1D
1111100000000000
1E
1111000000000000
1F
1110000000000000
20
1100000000000000
21
1000000000000000
.. 22
pOOOOOOOOOOOOOOO
A-
--.,
.~
NZERO
ZERO
--,
......
~' ___~ •. "''''·''_K_'~. _.".._,...:.,.~ ........ ,_.. _., .. ,,_.~.~._ ->-.1'".,;:, ..."-............ ~-.--.,~""---- ••,---,,...~-.~ ... --' .. "~ •
1-1
0
1
3
7
F
1F
3F
7F
FF
1FF
3FF
7FF
FFF
1FFF
3FFF
7FFF
FFFF
FFFE
FFFC
FFF8
FFFO
FFEO
FFCO
FF80
FFOO
FEOO
FCOO
F800
FOOO
EOOO
COOO
8000
0000
Location
ONE BIT
ZROBIT
...
23
24
2.5
26
2[1
28
29
2A
2B
2C
2D
2E
2F
30
31
32
... 33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47 through B2
B3
B4
B5
B6
B7
B8
B9
Contents
0000000000000001
0000000000000010
0000000000000100
0000000000001000
0000000000010000
0000000000100000
0000000001000000
0000000010000000
0000000100000000
0000001000000000
HEX Equivalent
0001
0002
0004
0008
0010
0020
0040
0080
0100
0200
0400
0800
1000
2000
4000
8000
FFFE
FFFD
FFFB
FFF7
FFEF
FFDF
FFBF
FF7F
FEFF
FDFF
FBFF
F7FF
EFFF
. DFFF
BFFF
7FFF
oooootOOOOOOOOOO
0000100000000000
0001000000000000
0010000000000000
0100000000000000
1000000000000000
1111111111111110
1111111111111101
1111111111111011
1111111111110111
1111111111101111
1111111111011111
1111111110111111
1111111101111111
1111111011111111
1111110111111111
1111101111111111
1111011111111111
1110111111111111
1101111111111111
1011111111111111
0111111111111111
5
6
9
A16
Reserved for process
Logical unit number of scratch unit
Top of thread of entries in schedule stack
Address of FNR
Address of COMPRQ
Address of mask table
Address of top of interrupt stack
Address of request exit
1-2
r-.
Location
''"'''~,.
\...../
BA
BB
BC
BD
BE
BF
CO
Cl
C2
C3
C4
(
\---...-
..
/
C5 through E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
'.
ED
EE
EF
FO
Fl
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Contents
HEX Equivalent
Address of volatile storage release routine - VOLR
Address of volatile storage assignment routine - VOLA
Address of absolutizing routine for logical unit number
Address of S absolutizing routine
Address of C absolutizing routine
Address of N absolutizing routine
Most significant bits of first scratch area sector number
Least significant bits of first scratch area sector number
Logical unit number of the library unit
Most significant bits of sector number of first program library directory block
Least significant bits of sector number of first pro g ram library
directory block
Reserved for FORTRAN (unprotected)
Used for load and. go (unprotected)
Address of timer handler
Length of system library directory
Index to firs t mas s storage entry in the s y s tern library direc tory
Countdown register
Real time clock
Address. of dispatcher
Address of sys tern library directory
Temporary highest unprotected location + 1
Temporary lowest unprotected location - 1
Used by job processor for returns from loader, etc.
Current priority level/- PRLVL
Address of firs t available volatile storage
Length of table of presets
Address of table of presets
Address of breakpoint program when in core (unprotected)
Address of entry for system requests (unprotected)
Highest core location - MAXCOR
Highes t unprotected location + 1
Lowes t unprotected location - 1
Address of internal interrupt processor
Logical unit number of standard input device
Logical unit number of standard binary output device
Logical unit number of standard print output device
Logical unit number of output comment device
Logical unit number of input comment device
Address of the common interrupt handler
Memory index (unprotected) - I register
1-3
.
~"'''''
I
"
__ .J
{'"
'--:'''.
'-../.
INDEX
c
..
/
rr ..... _.
\'--"'-"
'-,
,,--
.-.,
/'
........
INDEX
CJ~~· absolute addressing
5-49
absolute addressing mode
one-word
one-word indirect
two-word
two-word indirec t
5-7
5-8
5-8, 5-52
5-9
11-10, 11-12
absolutized program
absolutizing addresses
11-17
absolutizing programs
14-5
2-6, 5-35
adder
address expressions
5-5
address field
3-3
5-2, 5-13
addressing modes
allocatable core
11-1, 11-38, 11-43, 11-47
C·
r-·"·
-"".
alphanumeric characters
6-7
arithmetic
2-1
assembler errors
9-13
assembler format
3-2
as sembling a program
9-2
automatic res tart
1-3
background
8-1, 8-4, 9-1, 11-1
basic assembler
breakpoint package
9-17
buffer data channel
12-66
card reader
12-23
characteristics of 1700
checksum
checkword, disk
CKASSM program
\. . . ,..... ._.. .J
6-1
1-1
12-9
12-38
8-61
comment field
3-5
common block
6-12, 9-6, 11-15
11-1
communications region
8-8, 8-16
completion address
6-15, 6-18
conditional assembly
configuration
1-10
console
1-11
constant addressing mode
continuator, driver
control statements
job processor
breakpoint
recovery
5-3, 5-49
13-3
9-2, 9-7
9-18
9-24
conversion
5-45
core request
8-55
core size
cylinder
1-1, 1-6
12-41
data block
6-12, 6-14, 9-5
debugging
9-13
delta
device assignment
device failure
5-1
9-7, 9-17
9-15
direct access channel (1705)
1-3, 1-6, 12-36
disk
dispatcher
drivers
drum
entering memory
7-:12
11-3, 13-9, 13-13
13-5, 13-9
12-48
1-12
INDEX (CONT)
entry points
6-2
error bit in Q
8-16, 8-17, 8-19
error checking, peripherals
12-63
als 0 see error bits on each peripheral
error section, driver
13-4
executing a program
9-7
execution times
shift class
storage reference class
5-32
5-32
6-2, 9-5, 11-14, 11-46, 11-49
2-7
11-11
flow of program
8-1, 8-4, 11-1
foreground
8-8
FREAD request
jump
5-22
LIBEDT
14-1
8-8
GTFILE request
8-47, 14-3
2-1
idle loop
11-3
indexing
3-4, 5-13, 5-15, 5-50.
8-59, 8-61
11-6
loader errors
9-17
loading a program
9-6, 9-16, 14-2, 14-7
initiator, driver
13-1
logical operations
5-34
input/output
1-6, 5-44, 7-1
buffered 7-11, 12-36, 12-48, 12-66
functj.ons
7 -5, 7 -12
8-54, 8-55
LOADER request
location field
5-1
9-3
loader blocks
5-53
interregister instructions
3-5, 3-7
load-and-go
indirect addressing
instruction classes
~
'--~-t
11-1, 11-12 . -"
listing
FWRITE request
INDIR reques t
9-1
job processor
libraries
function codes
see specific peripheral
hexadecimal numbers
2-4
13-3, 13-7
line processor
13-1
mode programming
11-3
stack
system
1-3, 5-43, 7-10., 11-29, 13-1, 13-7
externals
floating point numbers
7-10., 13-1
7-4
11-35
11-35
11-37
7-9, 7-16
7-1
interrupt
handler, common
11-3, 13-3, 13-9, 13-12
8-7
EXIT request
-r--
integer numbers
8-7, 11-3, 11-30., 11-38
exits
input/ output
interrupts
reply or reject
requests
priorities
rejects
status
unbuffered
3-2
"5-21, 5-36, 6-16
logical units
8-19
low-speed I/O package
7-3
M
5-1
macro assembler
6-1
r··
,"
INDEX (CONT)
~-,~---
macros
sys tem macros
6-16, 6-19
6-19
.--...../
magnetic tape
1731
1732
12-57
12-66
11-1, 11-12, 14-3
9-1
protect bit
mask regis ter
1-3
protect sys tem
1-2, 5-29, 5-42
masks
6-5
protected core
11-1
11-42
mass memory program replacement
14-1
mass storage addressing
8-15, 8-50
mass storage files
8-47, 14-5
mass storage operating system 8-1, 8-4
memory
memory parity
MONI
1-1
5-29
8-2, 8-4
--.,.
I
program library
manual interrupt
mass memory program coding
'",,-.,,;'
priorities
11-47
mass memory programs
11-34
schedule reques ts
space
11-38, 11-43
object program
opcode field
11-4
3-3
options for assembly (OPT card)
6-20, 9-3
overflow
paper tape punch
paper tape reader
parity bit
physical devic e tables
power failure
printer
2-7, 5-24, 5-28
8-11, 12-6
7-5, 8-11, 12-1
1-2
8-44
1-3
12-29
priorities
11-3, 11-24, 8-28, 8-30
hardware
13-10
I/O reques ts
11-35, 11-38,. 8-9, 8-16
1-2
pseudo-ops
6-1
READ request
8-8
real numbers
2-7
8-10
record formats
11-24
reentrant coding
1-7
registers
register reference instructions
5-40
rejects
input/output requests 11-35, 11-37
schedule reques ts
7-4
release request
11-40, 11-46
relative addressing
5-50, 11-14, 11-17, 11-19
relative addressing mode
one-word
one-word indirect
two-word
two-word indirect
5-10, 5-52
5-12
5-12
5-13
requests
8-1, 11-32
REQXT
runanywhere coding
buffer addresses
externals
8-2, 8-4
11-12
11-17
11-12
schedule request
11-32, 11-44, 8-8, 8-29, 8-36
INDEX (CONT)
scheduler stack
sector
11-3
unprotected core
11-1
12-37
utility assembler
6-1
shift ins tructions
5-31, 5-51
utility system
short read
8-17, 8-47
utopia
skip instructions
5-26, 5-51
variable fields
source program
11-4
space request
11-39, 11-46
STATUS request
8-42
status responses
also see specific peripheral
8-44
volatile storage
word size
WRITE request
.- .....
~--
-.
8-1, 8-4, 8-5
14-9
6-9
11-26, 11-28, 11-30
1-1, 1-2
8-8
storage reference addressing mode 5-18
storage reference instructions
5-18
storage reservation
6-10
subroutine parameters
5-37, 11-29, 11-32
11-40
swapping core
sweeping memory
1-13
system initializer
14-3, 14-6
system library
--
11-1, 11-12, 11-42
system recovery package
9-17
tape
see magnetic or paper
teletypewriter
1711/1712
1713
thread word
timer reques t
track
transfer address
transferring records
traps for interrupts
8-10
12-11
12-17
8-19, 8-28, 11-36
8-40, 11-34
12-37
6-2
14-7
1-4, 13-2, 13-7
-'10-
'.
CONTROL DATA
CORPORA TI ON
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