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PRELIMINARY

WD1002·05! HDO
Winchester! Floppy Disk
Controller
OEM Manual
Document No.: 61·031050·0030

IIIIESTERN DIGITAL
COR

PO

RAT

ION

2445 McCabe Way
Irvine, California 92714
(714) 863-0102
TWX 910-595-1139
July 1983

TABLE OF CONTENTS
SECTION 1

INTRODUCTION

1.1
1.2

SECTION 2

3.2

2-1
2-1
2-1
2-1
2-2
2-2
2-3
2-3
2-4

HostlnterfaceTiming ....................................................
3.1.1 Host Task File Read Timing ...........................................
3.1.2 Host Task File Write Timing .............................. ; . . . . . . . . . . . .
3.1.3 Host Sector Buffer Read Timing .......................................
3.1.4 Host Sector Buffer Read Timing (Long Mode) .............................
3.1.5 Host Sector Buffer Write Timing .......................................
3.1.6 Host Sector Buffer Write Timing (Long Mode) .............................
Miscellaneous Timing ....................................................

3-1
3-1
3-1
3-2
3-3
3-4
3-4
3-5

HOST INTERFACING

4.1
4.2
SECTION 5

Organization...........................................................
Host Interface Connector Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4O-Pin Host Interface Connector ............................................
Winchester Drive Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.25" Winchester 34-Pin Drive Control Connector ..............................
Winchester Drive Data Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Con nector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Floppy Drive Signals .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.25" Floppy 34-Pin Drive Control Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

INTERFACE TIMING

3.1

SECTION 4

1-1
1-2
1-3
1-3
1-3
1-3

INTERFACE CONNECTORS

2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
SECTION 3

Description............................................................ 1-1
1.1.1 On-Board Processing and Control Devices ...............................
1.1.2 Communications Between Host and WD1002-05 ..........................
Specifications..........................................................
1.2.1 Performance.......................................................
1.2.2 Physical ..........................................................
1.2.3 Environmental ............................................. : .......

General............................................................... 4-1
Host Interface Example ................................................... 4-1

TASK FILE

5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11

Task File Basics .........................................................
Data Register ...........................................................
WD1002-05 Error Register .................................................
Diagnostic Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Precomp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sector Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sector Number .........................................................
Cylinder Number ........................................................
SDH Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Status Register .........................................................
Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iii

5-1
5-1
5-1
5-2
5-2
5-2
5-2
5-2
5-2
5-3
5-4

SECTION 6

COMMANDS
6.1
6.2
6.3

6.4

6.5

SECTION 7

General...............................................................
WD1002-05 Command Summary ............................................
6.2.1 Steppi ng Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Type I Commands .......................................................
6.3.1 Test Command .....................................................
6.3.2 Restore...........................................................
6.3.3 Seek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Type II Commands .......................................................
6.4.1 Read Sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.1.1 Readlong Command ..........................................
6.4.1.2 DMA Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.1.3 Normal Completion ...........................................
Type III Commands ......................................................
6.5.1 Write Sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
6.5.1.1 Writelong Command ..........................................
6.5.2 Format Track ......................................................

6-1
6-1
6-1
6-2
6-2
6-2
6-2
6-2
6-2
6-2
6-3
6-3
6-3
6-3
6-3
6-3

PROGRAMMING
7.1
7.2
7.3

7.4

7.5

7.6

General ............................................................... 7-1
Setting Up Task Files ..................................................... 7-1
7.2.1 Cylinders and Tracks ................................................- 7-1
Type I Command Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.3.1 Use of Busy Bit ..................................................... 7-1
7.3.2 Use of Interrupts .................................................... 7-2
7.3.3 Use of Error Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.3.4 Use of Corrected Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Type II Command Programming ............................................ 7-2
7.4.1 DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.4.2 Block Moves ....................................................... 7-2
7.4.3 Using DMA ........................................................ 7-3
7.4.4 Multiple Sector Transfers ............................................. 7-3
7.4.4.1 Partial Sector Transfers ........................................ 7-3
7.4.4.2 Interrupt Source Selection ..................................... 7-3
7.4.4.3 Clearing Hardware DRO ....................................... 7-3
7.4.4.4 Interrupt Selection Circuit ...................................... 7-3
7.4.5 Simulated Completions .............................................. 7-4
Type III Command Programming ............................................ 7-4
7.5.1 Formatting ........................................................ 7-4
7.5.2 Interleaving ........................................................ 7-5
Bad Block Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
7.6.1 Sector Pre-Allocation ................................................ 7-5
7.6.2 Alternate Tracks .................................................... 7-6
7.6.3 Spare Sectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
7.6.4 Bad Block Bit ...................................................... 7-6

iv

SECTION 8

THEORY OF OPERATION
8.1
8.2

SECTION 9

8-4
8-4

8-4
8-4
8-5
8-5

General...............................................................
Oscillator Frequency .....................................................
WD2797 Adjustment Procedure ............................................
Test/Operation Jumper Variations ...........................................

9-1
9-1
9-1
9-1

DISK DRIVE EXAMPLES
A.1
A.2

A.3

Introduction ...........................................................
Polled Status Driver .....................................................
A.2.1 Initialization .......................................................
A.2.2 Read Sector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.2.3 Write Sector ......................................................
A.2.4 Task File Updating ..................................................
Interrupt Driven Driver ....................................................
A.3.1 Initialization .......................................................
A.3.2 Read Sector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.3.3 Write Sector ......................................................
A.3.4 Task File Updating ..................................................
A.3.5 Interrupt Service Routine ............................................

APPENDIX B

INTERLEAVE CALCULATING

APPENDIX C

CALCULATING SECTORS PER TRACK

APPENDIX D

PROGRAMMERS QUICK REFERENCE
D.1
0.2
D.3
D.4

APPENDIX E

8-1
8-1
8-1
8-3
8-3
8-3
8-3
8-3

MAINTENANCE
9.1
9.2
9.3
9.4

APPENDIX A

Generai...............................................................
WD1002-05 Architecture and Functional Description ............................
8.2.1 Host Int6ifaC6 Logic (HIL) ............................................
8.2.2 Control Processor (CP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2.2.1 Clock Generator .............................................
8.2.2.2 Task/Syndrome File (TSF) ......................................
8.2.3 Error Detection and Support Logic (EDS) .................................
8.2.3.1 Error Detection ..............................................
8.2.3.2 Support Logic ...............................................
8.2.4 Sector Buffer (SB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2.5 Winchester Drive and Buffer Interface (WOBI) .............................
8.2.5.1 Write Precompensation (WPC) ..................................
8.2.5.2 Data Separator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2.6 Floppy Drive and Buffer Interface (FDBI) .................................

Task File ..............................................................
Valid Commands ........................................................
SDH Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Status and Error Register Bits .............................................

LSI DATA SHEETS (to be supplied)

v

A-1
A-1
A-2
A-2
A-3
A-4
A-4
A-5
A-6
A-6
A-7
A-8

D-1
0-1
D-1
D-2

APPENDIX F

SCHEMATICS AND ASSEMBLY DIAGRAMS

APPENDIX G

BILL OF MATERIALS (to be supplied)

vi

LIST OF TABLES
TABLE

TITLE

PAGE

2-1
2-2
2-3
2-4
2-5

Host Interface Connector Pin Description .........................................
Winchester Drive Control Connector Pin Description ................................
Winchester Drive Data Connector Pin Description ..................................
Power Connector Pin Description ...............................................
Floppy Drive Control Connector Pin Description ...................................

2-1
2-2
2-3
2-3
2-4

3-1
3-2
3-3
3-4
3-5
3-6
3-7

Host Task File Read Timing ....................................................
Host Task File Write Timing ....................................................
Host Sector Buffer Read Timing (Normal Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Host Sector Buffer Read Timing (Long Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Host Sector Buffer Write Timing (Normal Mode) ....................................
Host Sector Buffer Write Timing (Long Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Miscellaneous Timing ........................................................

3-1
3-1
3-2
3-3
3-4
3-5
3-5

5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8

Task File Register Array .......................................................
Error Register Bits ...........................................................
SOH Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOH Bits6 &5 ..............................................................
SOH Bits 4 & 3 ..............................................................
SOH Bits 2, 1 & 0 Hard Disk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOH Bits 2, 1 & 0 Floppy Disk ..................................................
Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-1
5-1
5-3
5-3
5-3
5-3
5-3
5-3

6-1
6-2

Command Types ............................................................ 6-1
r3-rO - Stepping Rates ....................................................... 6-1

7-1
7-2
7-3
7-4

File Read On 4-Head, 2-Platter Disk Drive .........................................
Interleave Table with 32 Sectors and 4:1 Interleave ..................................
Interleave Table with 32 Sectors and 4:1 Interleave-Physical Sector Five Mapped Out .......
Interleave Table with Redundant Sectors, No Interleave, and
All Sectors Marked as Bad Blocks ...............................................

vii

7-1
7-5
7-6
7-6

LIST OF ILLUSTRATIONS
TABLE

TITLE

PAGE

1-1

WD1002-05 Simplified Data/Command Flow Block Diagram .......................... 1-2

3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8

Host Task File Read Timing ....................................................
Host Task File Write Timing ....................................................
Host Sector Buffer Read Timing: Prog I/O .........................................
Host Sector Buffer Read Timing: DMA Mode ......................................
Host Sector Buffer Read Timing (Long Mode) ......................................
Host Sector Buffer Write Timing (Normal Mode) ....................................
Host Sector Buffer Write Timing (Long Mode) ......................................
Miscellaneous Timing ........................................................

4-1

Host Interfacing Example ..................................................... 4-1

7-1

Interrupt Selection Circuit ..................................................... 7-4

8-1

WD1002-05IWD1002-HDO Functional Block Diagram ................................ 8-2

ix

3-1
3-2
3-2
3-3
3-3
3-4
3-5
3-6

SECTION 1
INTRODUCTION
interface Circuitry is also included. Winchester disk
drive signals are based on the floppy disk, look-alike
interface available with the Seagate Technology
8T506 and other compatible drives.

1.1 DESCRIPTION
The WD1002-05 Winchester/Floppy Disk Controller
(WFC) is a stand-alone, general purpose board that
allov"fs a host processor to control up to three VVinchester 5.25-in. disk drives and four floppy 5.25-in.
disk drives. The following is a synopsys of the
WD1002-05 features:
• User-selectable 5.25" Winchester or Floppy
operation
• controls up to 3 Winchester and up to 4 Floppy
drives
• Single

I/O connections are made with standard ribbon cable
connectors. The disk interface connectors have
standard pinout configurations to allow direct pin-forpin connection to the Winchester and Floppy disk
drives. Power (+ 5 VDC) and ground for the
WD1002-05 are furnished on a separate connector.

1.1.1 ON·BOARD PROCESSING AND
CONTROL DEVICES
The WD1002-05 consists of a set of devices specifically designed for host dual control of Winchester
and Floppy disk drives. The heart of the control logic
is the Control Processor Buffer Manager (WD1015)
that manages the on-board static RAM sector buffer
(2048-word-by-8-bit). All bytes of data written to, and
read from disk is first stored in this sector buffer.
When the buffer is full, the data is transferred, on
command, to its intended destination.
The WD1015, besides controlling data flow between
host, sector buffer, and disk controllers, also translates the host Winchester command format to Floppy disk format when addressing the Floppy Disk
Controller (WD2797). This permits the host to maintain a single command format (Wincheste~ while in
effect controlling two different disk command formats (Winchester vs. Floppy). This is possible since
the SDH register is used to select either type of drive.
The WD1015 maintains the current copies of necessary host command data in the task files; a set of
registers physically located in the Winchester Disk
Control device (WD1 01 0) and the Error Detection and
Support logic device (WD1014).

+ 5V Power Supply

• 8-bit universal host interface
• On-Board data separation circuitry
• On-Board write precompensation for floppy and
hard disks
• On-Board sector buffer supports up to 1K-byte
sectors
• Programmable sector sizes 1024 bytes

128, 256, 512, or

• Automatic track formatting on hard and floppy
disks
• Multiple sector operations on all disks
• Data rates up to 5 Mbits/sec on hard disk
• Single burst error correction up to 5 bits on hard
disk data
• CRC generation/verification for data and all I.D.
fields
• Automatic retries on all errors with simulated
completion
• ECC diagnostic commands included (READLONG
& WRITELONG)

The WD1010 is the link between the host processor
(via sector buffe~ and the Winchester disk drives.
During transfer of data from the host to the WD1010
the WD1014 computes a 4-byte ECC which is appended to the end of the data being transferred to the
WD1010 and recorded on disk. During data transfers
from the WD1010 to the host (via the sector buffe~,
the WD1015 uses the ECC syndrome to validate the
data. Retries and corrections are attempted automatically in case of corrupted data.

• WD1002-05 internal diagnostics
• 16 different stepping rates for both hard and floppy
drives
The WD1002-HDO is a depopulated version of the
WD1002-05. All Floppy drive control and associated
circuitry has been deleted from the board, providing a
Winchester Drive Controller board that will drive up
to three 51/4" Winchester disk drives. All parameters,
programming, and timing in this document that
appl ied to Wi nchester Drive Control pertai n to the
WD1002-05 and the WD1002-HDO.

The WD1015 performs error correction in conjunction
with the WD1014 on data transferred to the disk.
While the WD1015 controls the operation of the onboard error-correction logic, the WD1014 generates
and checks the Error Correction Code (ECC) if SDH
bit 7
O. Thus the WD1014 also provides the
WD1015 its real-time control capability. Specifically,

All buffers and driver/receivers needed for direct connection to the disk drives are furnished as part of the
WD1002-05 circuitry. The logic for the WD1002-05's
variable-length sector buffer, as well as logic necessary for error correction, data separation, and host

=

1·1

the real-time function is provided for Winchester disk
operation only (real-time function is not available for
Floppy disk operation).

The Master Reset strobe (MR) must be used to
initialize the WD1002-05 on power-up. This always
initiates the internal diagnostics of the WD1002-05
and no command may be processed until the BUSY
bit is cleared (approx. 1-2 seconds).

If CRC format Winchester disks are used, CRC is selected by the WD1010 by setting SDH7
O. CRC for
the floppy disks is performed by the WD2797, a de-vice that furnishes ail control functions for floppy
disk drives, including necessary data separation and
write precompensation. SDH7 must be set to zero for
floppy disk operation.

=

To communicate with the WD1002-05, the host processor must first access a set of registers called the
task files (see SECTION 5 for a description of the task
file registers and SECTION 7 for programming information). All parameters necessary for a command
to be executed are set into the task files. The task
files tell the WD1002-05 what is to be done, i.e. sector
size to be selected, disk drive selected and head or
side desired, sector number, and any other
information needed to execute the command.

A simplified data flow and command flow block diagram is illustrated in Figure 1-1.
1.1.2 COMMUNICATIONS BETWEEN HOST
AND WD1002·05

After a command has been issued, the host can
verify that the command has been executed either by
polling the BUSY bit in the task file or by waiting for
an interrupt request (See SECTION 6 for description
of commands).

Two-way communications between the host processor and the WD1002-05 is via a parallel access
port and an 8-bit, bi-directional bus. Appropriate control signals are used to transmit disk READIWRITE
data, status information, and macro commands over
the data bus.
Communications between the host processor and
the WD1002-05 uses~ight data bus lines (DAL7DALO), a Card Select (CS), a Read Enable (RE), a Write
Enable (WE), three address lines (A2-AO), a Master
Reset (MR), a Data ReQuest (DRQ), and an INTerrupt
ReQuest (INTRQ). (See SECTION 2 for a complete
description of control signals.)

For all write operation commands, including format,
the host must fill up the sector buffer no less than
the sector size chosen, otherwise the WD1002-05 will
not execute the command. The sector buffer need
only contain the required valid data to execute the
command while the rest of the bytes serve as fillers
(especially for a format operation). Once the sector
buffer is filled all communications with the host are
I

-

-

-

-

-

-

-

-

-

-

-

-

-

-I

r

HOST
INTERFACE
LOGIC

WD2797
FLOPPY
CONTROLLER

DATA BUS

FLOPPY
IFC

I
I

I
·NOT ON WD1002-HDO

WD1015
CONTROL
PROCESSOR

I
I

_-.J
ADDR
LOGIC

SECTOR
BUFFER

WD1010
WINCHESTER
CONTROLLER

WD1014
EDS

CONTROL BUS

Figure 1·1.

WD1002·05 Simplified Data/Command Flow Block Diagram

1·2

DATA
SEP
LOGIC

The data request (DRa) will always be set at the start
of a write command, indicating that the sector buffer
is available for sequentially inputting data. If the data
request is set on a read command, it indicates that
data requested by the host is in the sector buffer.

terminated.
Multiple transfer commands are handled one sector
at a time. If the host wants to transfer ten sectors, the

\AJD1002-05 sequentially accepts one sector of data at
a time and processes it until all sectors have been

The interruot reauest (INTRa) is set after comoletion
of a command. Status'and error information may now
be read by the host.

transferred. At the completion of the multiple
transfer, the interrupt request is set, and the BUSY bit
is cleared.

1.2

SPECIFICATIONS

1.2.1 PERFORMANCE
DRIVE PARAMETERS

WINCHESTER DISKS

FLOPPY DISKS

Encoding method:
Cylinders:
Sectors per track:
Heads:
Drive selects:

MFM
Up to 1024
Up to 64

MFM
Up to 256
Upt064

8

2

3 (ST506)

4 (SA450)

3511s to 7.5 ms (500 I1sec
increments)

rv1511S, 1ms, 2ms, 3ms, 4ms, 5ms,
6ms, 8ms, 10ms, 12ms, 14ms, 16ms,
18ms, 20ms, 25ms, 40ms.

5.0 Mbits/s
12 ns
Soft

250 KbitS/s
100 to 300 ns adj.
Soft

Step rate:

Data transfer rate:
Write Precomp time:
Sectoring:

General
CRC polynomial:
ECC polynomial:
ECC polynomial reciprocal:

X16
X32
X32

+ X12 + X5 + 1
+ X28 + X26 + X19 + X17 + X10 + X6 + X2 + 1
+ X30 + X26 + X22 + X15 + X13 + X6 + X4 + 1

256 byte sector

512 byte sector

Non-detection probabi Iity:
Miscorrection probability:
Correction span:
Single burst detection span:
Double burst detection span:

rv2.30 E-10

rv2.30 E-10
1.57 E-5
5 bits
19 bits
3 bits

Host interface:
Drive capabi Iity:
Drive cable length:
Host cable length:
Power requirements:

8-bit bi-directional bus
10 LS loads
10 ft max
3 ft max
+ 5V ± 5 % ,3.0 A max

MTBF:
MTTR:

10,000 POH
30 min.

8.00 E-6
5 bits
20 bits
4 bits

1.2.2 PHYSICAL
Length:
Width:
Height:

8.00 in.
5.75 in.
0.75 in.

1.2.3 ENVIRONMENTAL
Ambient temperature ................... 0-50°C
Relative Humidity (non-condensing) .... 20% - 800/0
Air flow at 1/4" from component surfaces .. 150 cubic ftJmin

1·3

SECTION 2
INTERFACE CONNECTORS
ORGANIZATION
The WD1002-05 board has seven connectors for user
application:
(J6) Power connector
(J5) Host interface connector
(J7, J8) Drive control connectors
(J1, J2, J3) Winchester high speed data connectors
The drive control cables are daisy-chained to each of
the three Winchester drives. The three drive data connectors carry differential signals and are radially
connected.

host. This line is reset whenever the
sector buffer is exhausted, or when
MR is asserted.
The Master Reset (MR) line initializes
all internal logic on the WD1002-05.
Vvhenever ivi R is received by the
WD1002-05, the internal diagnostics
are automatically initiated.
All eVen numbered pins on this
connector are to be used as signal
grounds. Power grounds are available on the power connector.

2.1

MR

GND

4O·PIN HOST INTERFACE CONNECTOR
The host interface connector (J5) is a 40-pin vertical
header. Cabling should be less than three feet long.
Either flat ribbon or twisted pair cable can be used.
The connector pinouts are given in Table 2-1.
2.3

HOST INTERFACE CONNECTOR SIGNALS
The signals of the host interface connector (J5) are
compatible with most microprocessors and many
minicomputers. The connector consists of an 8-bit bidirectional bus, a 3-bit address bus, and seven
control lines. All commands, status, and data are
transferred over this bus. The control signals are as
follows:
DALO-DAL7
8-bit bi-directional Data Access
Lines. These lines are in a high-impedance state whenever the CS line
is inactive.
When Card Select (CS) is active
along with RE or WE, data is read or
written via the DAL bus.
When Write Enable (WE) is active
along with CS, the host may write
data to a selected register of the
WD1002-05.
When Read Enable (RE) is active
along with CS, the host may read
data from a selected register of the
WD1002-05.
Three Address lines are used to
A2-AO
select one of eight registers of the
WD1002-05. They must remain stable
during all read and write operations.
The INTerrupt ReQuest line is actiINTRQ
vated whenever a command has
been completed. It is reset to the inactive state when the status register
is read, or a new command is issued
to the WD1002-05, or when MR is
asserted.
The Data ReQuest line is activated
DRQ
whenever the sector buffer contains
data to be read by the host, or is
awaiting data to be loaded by the

2.2

Table 2·1.

Host Interface Connector Pin Description

Signal
Ground

Signal
Pin

2
4
6

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

Signal Name
DALO
DAL1
DAL2
DAL3
DAL4
DAL5
lJAL6
DAL7
AO
A1
A2
CS
WE
RE
Pull-up (PUP)
Not Connected
Not Connected
INTRQ
DRQ
MR

2.4 WINCHESTER DRIVE CONTROL SIGNALS
The Winchester Drive Control connector (J7) is a
relatively low-speed bus, daisy-chained to each of the
Winchester drives in the system. To properly terminate the open collector outputs from the WD1002-05,
the last drive in the daisy chain should have a 2201
330-0hm line termination resistor pack installed. All
other drives should have no termination. Drive con-

2·1

restore, the step pulse period is determined by the seek complete time
from the drive.

trol signals are as follows:
RWG

When the Reduce Write Current
(RWC) line is activated with write
gate, a lower write current is used to
compensate for greater bit-packing
density on the inner cylinders. The
RWC line is activated when the cylinder number is greater than or equal
to four times the contents of the
write precomp register. This output is
valid only during write and format
commands.

DS1-DS3

These three Drive Select lines
(DS1-DS3) are used to select one of
three possible drives.
Direction In determines the direction
of motion of the R/W head when the
step line is pulsed. A high on this line
defines the direction as out, and a
low defines direction as in.

WG

The Write Gate signal enables the
disk write data circuitry.

2.5

SC

Seek Complete line informs the
WD1oo2-05 that the head of the selected drive has reached the desired
cylinder and has stabilized. Since
Seek Complete is not checked after a
seek command, overlapped seeks
are allowed.

This drive control connector (J7) is a 34-pin vertical
header on 0.10-inch centers. Cabling should be flat
ribbon or twisted-pair cable less than 10 feet long.
The cable pinouts are given in Table 2.2.

TROOO

WF

HS2-HSO

Signal
Pin

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33

Head Select lines (HS2-HSO) are used
by the WD1002-05 to select a specific
R/W head on the selected Winchesterdrive.

ROY

Ready informs the WD1oo2-05 that
the desired drive is selected and that
its motor is up to speed. The
WD1oo2-05 will not execute commands unless this line is true.

Winchester Drive Control Connector
Pin Description

Signal
Ground

Write Fault informs the WD1002-05
that some fault has occurred on the
selected drive. The WD1oo2-05 will
not execute commands when this
signal is true.

Index is used to indicate the index
pOint for synchronization during formatting and as a timeout mechanism
for retries. This Signal should pulse
once every rotation of the disc.

STE>P

Table 2-2.

TRack 000 indicates that the R/W
heads are positioned on the outermost cylinder. This line is sampled
before each step pulse is issued.

IND

5.25" WINCHESTER 34-PIN DRIVE
CONTROL CONNECTOR

2.6

1/0

Signal Name

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32

0
0
0

34

0

RWC
Head Select 2
Write Gate
Seek Complete
TROOO
Write Fault
Head Select 0
NC
Head Select 1
Index
Ready
Step
Drive Select 1
Drive Select 2
Drive Select 3
NC
Direction In

I
I
I

0
0
I
I

0
0
0
0

WINCHESTER DRIVE DATA CONNECTOR

Three data connectors (J1-J3) allow data to pass
between the WD1002-05 and each Winchester disk
drive. All lines associated with the transfer of data
between a drive and the WD1002-05 system are differential in nature and may not be multiplexed. The
three Winchester drive data connectors are 20-pin
vertical headers on 0.10-inch centers. Cabling should
be either flat ribbon or twisted-pair cable, less than 10
feet long. Cable pinouts are given in Table 2-3.

Step is pulsed once for every cylinder
to be stepped. The direction of the
step will be determined by the direction tine. The Step pulse period is
determined by the internal Winct}e~ter,stepping rate register during
.implied seek operations, or explicitly
during seek commands. During auto

2·2

Table 2·3.

DS3-DSO

Winchester Drive Data Connector
Pin Description

I Sianal I Sianal I

I Ground I
I
I

Pin

I I/O

1
3

2
4
6
8

5

I'

7
9
10

11
12

13
14

0
0

17
18

I
I

15
16

19
20
2.7

The MOtOi On line is used to directly
control the dc spindle motor of the
floppy drive. !f Motor On Mode
(MOM) = 0 (user selectable jumper
option) then a 40 nsec delay occurs,
otherwise a one-second delay occurs
after Motor On and before any reading or writing is attempted. If the floppy drive is not accessed for "'3
seconds, the motor is turned off by
the WD1015. Also the drives supported must be configured so that
the R/W heads are loaded when the
motor is turned on. This is usually
available as an option on most drives.

Signal Name
NC
NC
,NC
NC
NC
NC
GND
GND
M FM Write Data
MFM Write Data
GND
GND
M FM READ Data
MFM READ Data
GND
GND

I

The Direction In line determines the
direction of motion of the R/W head
when the step line is pulsed. A high
on this line defines the direction as
out, and a low defines the direction
as in.

POWER CONNECTOR

A 4·pin amp connector (J6) is provided for power and
ground inputs to the board. The pinouts are given in
Table 2-4.
Table 2-4.
Pin
1
2
3
4
2.8

These four Drive Select lines
(DS3-DSO) are used to select one of
four possible drives.

The Step line is pulsed once for each
cylinder to be stepped. The direction
of the step will be determined by the
direction line. The step pulse period
is determined by the internal floppy
stepping rate register during implied
seek operations, auto restore, or explicitly during seek and restore commands. During any restore operation,
the stepping-rate period is limited to
8 ms minimum.

Power Connector Pin Description
Signal Name
NC
GROUND
GROUND
+ 5V regulated @ 3 amps (max)

The Write Data interface line provides data to be written on the disk.
This line is enabled by write gate
being active.

FLOPPY DRIVE SIGNALS

The Floppy Drive Control connector (J8) is a relatively
low-speed bus, daisy-chained to each of the floppy
drives in the system. To properly terminate each TTLlevel output signal from the WD1oo2-05, the last drive
in the daisy chain should have line terminations as
specified by the drive manufacturer. The other drives
should not have any terminations. Drive control signals for the floppy -diSCS are functionally similar to
those for the hard discs, except that all data is
transferred via one connector instead of the separate
connectors used for the Winchester drives. Floppy
drive signals are as follows:

The Write Gate output signal enables
disk write data circuitry.
TROoo indicates that the R/W heads
are positioned on the outermost cyl·
inder. This line is sampled before
each step is issued.
The Write Protect interface signal
provided by the drive indicates to the
WD1oo2-05 that a write-protected
disk is installed. When write protect
is active, no data can be written to
the disk by the WD1002-05.

The Index line contains a reference
index pulse once every disk rotation
to indicate the beginning of a track.

2·3

2.9

The Read Data line provides the "raw
data" (clock and data together) as detected by the drive logic.

Table 2·5.

Selects side of floppy disk to be
written or read.

Signal
Ground

Signal
Pin

1
3
5
7

2
4
6
8
10
12
14
16
18
20
22
24

5.25" FLOPPY 34-PIN DRIVE CONTROL
CONNECTOR

This floppy drive control connector (J8) is a 34-pin vertical header on 0.10-inch centers. Cabling should be
flat ribbon or twisted-pair cable, less than 10 feet
long. The cable pinouts are given in Table 2-5.

9
11
13
15
17
19
21
23
25
27

29
31
33

2·4

Floppy Drive Control Connector
Pin Description

26
28

30
32

34

I/O

Signal Name

-

NC
NC
Drive Select 0
Index
Drive Select 1
Drive Select 2
Drive Select 3
Motor On
Direction In
Step
Write Data
Write Gate
Track 000
Write Protect
Read Data
Side Select
NC

0
I

0
0
0
0
0
0
0
0
I
I
I

0

-

SECTION 3
INTERFACE TIMING
3.1

HOST INTERFACE TIMING

3.1.1 HOST TASK FILE READ TIMING
The task fiies read by the host are physicaiiy iocated
in the WD1010 Winchester Disk Controller. The error
register is located in the V'v'D1014 EDS device, and the
status register is implemented using TTL gates.
Table 3·1.

Host Task File Read Timing

SYMBOL
tSET
tHLD
tRE
tRDR
tDA
tDH

CHARACTERISTIC

MIN.

Addr, Card select setup to RE
Addr, Card select hold from RE
Read enable pulsewidth
Read Recovery til'lliL
Data access after RE active
Data hold after RE inactive

200
0
0.4
300

MAX.

UNITS

400
25

ns
ns
I-ls
ns
ns
ns

MAX.

UNITS

10

ADDR

I

tHLD ---.:

~tSET

~:

I

I
I

I
I

X·...4:~~~~_tR_E_-_-_-_-_-_ ::zr" I
-......

I~tDA~rI
-.J ~tDH
_____ I

-------------«

DATA VALID

DBO-7

Figure 3·1.

7>-----

Host Task File Read Timing

3.1.2 HOST TASK FILE WRITE TIMING
The task files written to by the host are physically
located in the WD1 01 0 device except for the command register, which is located in the WD1014 EDS
device.
Table 3·2.

I SYMBOL
tSET

I tHLD
twE
twER
tDS
tDH

Host Task File Write Timing
CHARACTERISTIC

MIN.

Addr, Card select setup to WE
Addr, Card select hold from WE
Write enable pulsewidth
Write Recovery time __
Data access se..!!:!2..to WE active
Data hold after WE inactive

0.1
30
0.2
1.0
0.2
10

3-1

!

10
10
10

I

I-ls
ns
I-ls
I-ls
I-ls
ns

~__________A_0_,A_1_,A_2_ST_A_B_LE__________~______

AD DR

tHLD~

..--

~
......_ _
tS_E_T--'_----&...:_ _ _ _ _ _ _ _--+-:_Jt+=---tW-E-R----.._~"

CS

__

I

I

WE - - - - - - - - - - - - " I

~~--tWE---...
1t1

~:4- tDH

!.-- tDS

i~/~~~~

I

DBO-7

DATA MUST BE VALIDA><><><

Figure 3-2.

Host Task File Write Timing

3.1.3 HOST SECTOR BUFFER READ TIMING
After a read command, the host can read the sector
buffer by accessing the data register. The ORO line is
set at the start of every sector transfer and is reset
when the sector buffer has been emptied.
Table 3-3.

Host Sector Buffer Read Timing (Normal Mode)

SYMBOL

CHARACTERISTIC

MIN.

337

Read Cycle time
Addr, Card select to Data Valid
Read enable pulsewidth
Read Recovery tim~
Data access from RE active
Data hold after RE inactive

tRC
tACC
tRE
tRR
tOA
tOH

MAX.

337
200

137
200
25

I

1.......l - - - - - - t R C

.'

I

CS, ADDRESS

,4

I
RE

I

~--------------

7'\..
tACC

-I

&tDA~11

~

14
DOUT

I

-~--~i
..-.-/!\

.

tRE;

--------.----IOK
UNKNOWN

Figure 3·3.

~ tRR

1
-I'"
i

OUTPUT DATA

I

14--

I

tDH~

i

VALiD~"""""---I

Host Sector Buffer Read Timing: Prog 1/0

3·2

,
I

UNITS
ns
ns
ns
ns
ns
ns

~!111

I
ADDR,CS

~.- ____=~~L============_+·===--=-=-~~~/======~
~~:
!.~
~"=========
: . -tACC---+j
I
--.,
tDA

:... tRR ....1

I

. !"
Y--.-

I.-!

~~---.......
--~

I
I

I

14= tRE
DOUT

I

t

I -rl
I
1

~

DH

I

1
I
y-====f~~-~--~--~---~=

'"-----'

I

-----~

~---~~--~~

Figure 3·4.

Host Sector Buffer Read Timing: DMA Mode
sector buffer. The host is only required to generate
four additional read strobes subject to the timings in·
dicated. Multiple sector transfers are also permitted.

3.1.4 HOST SECTOR BUFFER READ TIMING
(LONG MODE)
In the long mode of sector buffer read timing, the
host reads four extra check bytes after the sector
buffer has been emptied. These bytes are actually
read from the WD1014 EDS device and not from the
Table 3·4.

1_----

....
; ..1 - - - - t R C - - - I I..

DMA data transfer speed should be limited in order
to read the four check bytes in this special diagnostic
mode.

Host Sector Buffer Read Timing (Long Mode)
MIN.

CHARACTERISTIC

SYMBOL

Read Cycle time _
Address setup to C~
Address hold from CS
Card select setup to RE
Card select hold to RE inactive
Addr, Card select to Data Valid
Read enable pulsewidth
Data access from RE active
Data hold after RE inactive

tRP
tAS
tAH
tcs
tCH
tACC
tRE
tDA
tDH

ADDR

=1
I
I

I
I

RE

I
I
1
I

800
0
0
0
0
237
50
100
25

x==-

X\

~ tAS
CS

MAX.

~

I

I

~

1
I

I
I

~

I

I'"

1

I

I

1

~I

!I

tAH !~-

--..J

I

I

l

I

\

I
I

,

tcs ~ tRF--"
.. I tCH~

tACC~
I
~ tDA

:....

~

DOUT

Figure 3·5.

!
I

\

I ...

,f

.'I

TRP

~I tDHt....-I
I
I

~

~

Host Sector Buffer Read Timing (Long Mode)

3·3

~

UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns

3.1.5 HOST SECTOR BUFFER WRITE TIMING

DRO line is set at the start of every data transfer and
is reset when the SB has been filled.

After a write or a format command has been issued,
the host can write to the sector buffer by accessi ng
the data register. Both the address lines A2-AO, and
the CS line can be held in their active states without
being toggled while writing the sector of data. The
Table 3·5.

The DMA write cycle timing diagram is similar to the
DMA read cycle timing shown in Figure 3-4.

Host Sector Buffer Write Timing (Normal Mode)
CHARACTERISTIC

SYMBOL

MIN.

Write Cycle time
Address setup time
Addr, Card select to end of WE
Write enable pulsewidth
Write Recovery ti~
Data access from WE active
Data hold after WE inactive

twc
tAS
tcw
twE
twR
tDS
tDH

MAX.

257
0
257
120
137
60

15

~I.~---------twc--------------~.~I

ADDRESS

------*~-----------------------*--------1/!!111/&
\\\\\\\\\\\\~
1

RE

I

I
I.....
...i-----tcw----~~~I

1

cs

~\\\\\~~
~tAS"
-,

:

I

I

lVillLb//J///I!/IA
1_____ tWE
~

\\\\
\\\\\\1
,

----.I

--i.~1

tWR

I....-1

f
l4-----tDS~:tDH ~

-----------------~ ' 1 - - - - - - - - - - - -

X

-------------------~

Figure 3·6.

DATA IN STABLE

I

I~----------

Host Sector Buffer Write Timing (Normal Mode)

3.1.6 HOST SECTOR BUFFER WRITE TIMING
(LONG MODE)

In the long mode of sector buffer write timing, four
extra check bytes are written by the host after the
sector buffer has been fi lied. The bytes are actually
written to the WD1014 EDS device and not to the sector buffer. The host is required to generate four additional write strobes subject to the timings indicated.
Muftjpte sector transfers are permttted.
DMA data transfer speed should be limited in order
to write the four check bytes in this special diagnostic mode.

3-4

UNITS

ns
ns
ns
ns
ns
ns
ns

j.-tBS~
BUSY

INTRa

~

I
I

I

I.-tIV-+j

\.--tIR~

I

:

'}

I

I

1

I..

tMR

YI

I
I

~toA~1

I

J.-tOVj
ORO

1

I

I

I

-MR

(CMO. WRITE)

tlRW

~
I

~
(STATUS)

~
I

I
I
INTRa

-I

t+I /

/

~~LASTI
WE

tlRR

~
I

I

RE

/

BYTE / '

CMO.

I

I

RE

I

~
~

WE

X

I

I

I

I

I

~~
BYTE

I

tosw~

I

'k

DRO

Figure 3-8.

Miscellaneous Timing

3-6

I

/4-

tORW-+/

j.....-

l,r-J~

SECTION 4
HOST INTERFACING
4.1 GENERAL
The WD1002-05 easily interfaces with most microcomputers and many minicomputers. Interfacing is
accomplished with the host interface connector (J5).

HOST INTERFACING EXAMPLE
Figure 4-1 shows the absolute minimum hardware required to interface the WD1002-05 board to a small
8085 microcomouter system. In the illustration. buffers are not used, nor -is the I/O completely decoded.
The user will most likely want to completely decode
the I/O to minimize the amount of I/O or memory
space required in the host forWD1002-05 interfacing.
If the interface cable length is kept to a few inches, it
is often possible to directly interface the WD1002-05
to the buffered bus of a host microcomputer.
4.2

The interface is very similar to that used for other
'fJestem Digital LS! peripheral devices, and the signal
pinouts are compatible with the Western Digital
WD1000 and WD1001 series of Winchester Disk Controller boards.
The WAIT line is not used in the WD1002-05. The
WAIT signal, however, is still provided for compatibility with WD1000 and WD1001 controllers.

RESOUT
READ
WR
RD
A15

MR
WAIT
WE
RE
CS
DAL7
DAL6
DAL5
DAL4
DAL3
DAL2 WD1002
DAL1
DALO

8085
74LS373

ALE
AD7
AD6
AD5
AD4
AD3
AD2
AD1
ADO

G
8D
7D
6D
5D
4D
3D
2D

INTRO
DRO

80
70
60
50
40
30
20
10 10
OC

A2
A1
AO
+5GND -V

AO·7

Figure 4-1.

Host Interfacing Example

4-1

Host Sector Buffer Write Timing (Long Mode)

Table 3·6.

I SYMBOL
tAH
tcs
tCH
twE
tos
tOH

ADDR

~

tAS

~

~

tAH

I

------'l~

50

60
15

I
l....-

I,------..\~_ _-----J/

Figure 3·7.

Host Sector Buffer Write Timing (Long Mode)

MISCELLANEOUS TIMING

Table 3·7.

Miscellaneous Timing

SYMBOL

CHARACTERISTIC

I tov
tlV
I

0

0
0

I

I

3.2

ns
ns
ns
ns
ns
ns
ns
ns

0

__________________~¥~________________~x~____

I

--.J

UNITS

800

Write Cycle time _
Address setup to C§......
Address hold from CS
Card select setup to WE
Card select hold to WE inactive
Write enable Rulsewidth
Data setup to WE inactive
Data hold after WE inactive

I twp
tAS

MAX.

MIN.

CHARACTERISTIC

tMR

I IBS
tlR

tDR

I, tlRW
tlRR
tosw
tORW

II

I

MIN.

MAX.

INTRQ valid from BUSY inactive

60

ORQ valid from BUSY inactive
Master Reset pulsewidth
MR to BUSY set
MR to Interrupt reset
MR to Data request reset
WR (cmd.) to Interrupt reset
RE (status) to Interrupt reset
Write command to ORQ set
WEIRE to DRQ reset

60

3-5

II

I

50

II
I

I

200
200
200
200
200
200
300

UNITS

!

I

ns
ns
ms
ns
ns
ns
ns
ns
ns
ns

SECTION 5
TASK FILE
S.1

TASK FILE BASICS
Individual registers are selected via AO-A2 for both
types
of drives. The registers shown in Table 5-1 are
____ :1_1-1_

The WD1002-05 performs all disk functions through a
set of registers called the task files. The task files are

loaded with parameters such as sector numbei,

i:1Vi:1IIi:1UIt:::.

cylinder number, etc., prior to issuing a command.
Table 5-1.

Task File Register Array

CS

A2

A1

AO

1
0
0

X

X

X

0
0

0
0
1
1
0
0
1
1

0
1

0

0

0
0
0
0
0

0
1
1
1
1

I

0
1
0
1
0
1

RE

WE

Deselected
Data Register
Error Register
Sector Count
Sector Number
Cylinder Low
Cylinder High* *
Size/Drive/Head
Status Register

Deselected
Data Register
Write Precomp*
Sector Cou nt
Sector Number
Cylinder Low
Cylinder High**
Size/Drive/Head
Command Register

* Not used on floppies
* * LSB of cylinder high, if set to 1, permits a 48 t.p.L floppy disk to be read on a 96 t.p.L floppy disk system.
S.2

DATA REGISTER

This register is the user's window to the on-board full
sector buffer. It contains the next byte of data to be
written to or read from the internal sector buffer.
When the ORO (Data Request) line is asserted, the
sector buffer contains data to be read during a Type II
command, or is awaiting data to be written during a
Type III command. If the WD1002-05 is interfaced
using programmed I/O, data transfers to this register
can be implemented using programmed block
moves. This register may not be read from or written
to except in the context of a valid command.
S.3

DAM NOT FOUND

Will be set during a read sector
command if, after successfully
identifying the 10 field, the data
add ress mark was not detected
within 16 bytes of ID field.

TROOO ERROR

Will be set during a restore
command if the track 000 line
was not asserted by the drive
after all stepping pulses have
been issued. The Winchesters
are issued a maximum of 1023
stepping pulses and the floppies, a maximum of 256
stepping pulses.

ABORTED
COMMAND

Indicates that a valid command
has been received that cannot
be executed based on status
information from the drive, Le.
drive not ready, seek complete
not asserted, or write fault.
Interrogation of the status
register by the host may be performed to determine the cause
of this failure.

ID NOT FOUND

When set, this bit indicates that
an ID field containing a specified cyl i nder, head, sector
number, or sector size was not
found after all the retries have
been executed.

WD1002·0S ERROR REGISTER

This Register contains specific fault information pertaining to the last command executed. This register
is only valid if the error bit in the status register is set.
The error register is read only. Table 5-2 shows the
error register bits.
Table 5-2.
Bit
7

6
5

4
3
2
1

o

Error Register Bits
Error Register
Bad Block Detect
Uncorrectable Error
CRC Error ID Field
ID Not Found
Aborted Command
TROOO Error
DAM not found

S·1

sector handling with one command. The value of zero
implies a transfer of 256 sectors (any size). For read
and write multiple sector commands, the sector
count is decremented, and the sector number is incremented after each sector transfer to or from the
buffer. During a format command, this register is
loaded with the number of sectors to be formatted
and decremented as each sector is formatted until it
reaches zero. During format, sector numbers are
specified using interleave tables loaded in the sector
buffer.

UNCORRECTABLE Indicates that an ECC or CRC
ERROR
error was encountered in a data
field during a read sector command and the error was uncorrectable.
BAD BLOCK
DETECT

5.4

Indicates that a bad block mark
has been detected in the specified 10 field. If the command
issued was a write sector command, write gate may be pulsed
but the sector wi II not be
written if generated from a read
sector command, the data field
will not be read. Note that bad
block may not be detected if
there is a flaw in the ID field.

5.7

This register is loaded with the desired sector number prior to a read or write command. The sector
number register may be read or written to by the host.
5.8

DIAGNOSTIC ERRORS

5

4

3
2
1
5.5

°

Cylinder High

Cylinder Low

Re~isterb!ts: 171615141312111°
171615141312111°1
9 8 7 6 5 4 3 2 1 °

Major Functional Failure

Cylmder bits:

WD1 015 error
WD1014 or bus error
sector buffer error
WD1 01 ° error
WD2797 error
Pass - WD1002-05 is functional

When bit ° of the cylinder high register (bit 8 of cylinder registe" is set to a 1 during floppy operation, 48
tpi disks can be used in 96 tpi disk drives for all
commands. When this bit is set to 0, only 96 tpi disks
can be used.

WRITE PRECOMP

5.9

The write precompensation register holds the cylinder number where the RWC line will be asserted
and write precompensation logic is to be turned on.
This write-only register is loaded with the cylinder
number divided-by-4 to achieve a range of 1024 cylinders. For example, if write precompensation is desired for cylinder 128 (80 Hex) and higher, this register
must be loaded with 32 (20 Hex). The write precompensation delay is fixed. at 12 nanoseconds from
nominal.

SDH REGISTER

This register contains the ECC/CRC sector size, drive
select, and head select bits. The SOH register is a
read/write register organized as shown in Tables 5-3
through 5-7.

This register is not used for floppy disk drives. Floppy
disk write precompensation is contained in WD2797
and set as described in the "Summary of Adjustment
Procedure" in SECTION 9 (MAINTENANCE) of this
manual.
5.6

CYLINDER NUMBER

These two registers form the cylinder number where
the head is to be positioned on a seek, read, or write
command. The two least significant bits of the cylinder high register form the most significant bits of
the cylinder number as illustrated below:

On power-up, or when specifically commanded to,
the WD1002-05 will run a series of internal diagnostic
tests. When an error is encountered, the diagnostic
routine is terminated. A binary error code is set in the
error register without the error bit of the status
register being set. The diagnostic routines are
exercised in the following order:
Error Code

SECTOR NUMBER

SECTOR COUNT

The sector count register is used in read sector, write
sector, and format commands to implement multiple

5·2

Table 5·3.

I7

Bit
Function

Table 5·7.

SDH Register

6

4

5

2

3

1

Bit
2

0

1

~RC/I
ECC
I
I

Sec
Size

Drive
Select

Head!
Drive
Select

I
I
I

Table 5·4.

I

SDH Bits 6 & 5

Bit

Bit

6

5

0
0
1
1

0
1
0
1

Table 5·5.

5.10

256 Bytes
512 Bytes
1024 Bytes
128 Bytes

Bit

4

3

0
0
1
1

0
1
0
1

Drive Selected
(decoded & latched)

1

Bit
0

Head Selected
Hard Disk

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Head 0
Head 1
Head 2
Head 3
Head 4
Head 5
Head 6
Head 7

Bit

0
0
0
0
1
1
1
1

Bit
0

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Floppy Drive &
Head Select

FD1FD1 FD2FD2FD3FD3FD4FD4-

HSO
HS1
HSO
HS1
HSO
HS1
HSO
HS1

STATUS REGISTER

Status register bits are shown in Table 5-8.

DriveSel1
DriveSel2
DriveSel3
Floppy Dr Sel

Table 5-8.

SDH Bits 2, 1 & 0 Hard Disk

Bit
2

Bit
1

After execution of a command, the status register is
loaded with status information pertaining to the command executed. The host must read this register to
ascertain successful execution of the command. The
status register is a read-only register; it cannot be
written to by the host. If the BUSY bit is set, no other
bits in this register are valid. Accessing this register
will cause the INTRQ line to be reset.

SDH Bits 4 & 3

Bit

Table 5·6.

Sector Size

I,
I

0
0
0
0
1
1
1
1

SDH Bits 2, 1 & 0 Floppy Disk

Bit

Status Register

7
6
5
4
3
2
1
0

Busy
Drive Ready
Write Fault
Seek Complete
Data Request
Corrected Data
Not used
Error

ERROR

The SDH register is used to select either the Winchester or the floppy disk drives as implied by bits 3
and 4 shown in Table 5-5. If either bit is set to zero,
then one of the hard disks is selected, and Table 5-6
is used to select one of eight heads.

Status Register Bits

I

When set, indicates that one or
more bits are set in the error
register. It provides an efficient
means of checki ng for an error
condition by the host. This bit is
reset on receipt of a new
command.

CORRECTED DATA This bit indicates that an error
correction has been successfully completed on the data
field just read from the Winchester disk. For multiple mode
operations, this bit indicates
one or more data fields have
been successfully corrected. If
an uncorrectable error occurs,
the command is terminated
with the appropriate bit being
set in the error register.

When bits 3 and 4 are both set to 1, then a floppy disk
will be selected. Table 5-7 is used to select one of
four drives with side select 0 or 1 as shown.
Whenever different drives are to be accessed, the
SDH register must be updated by the host prior to a
command being issued.

5·3

DATA REQUEST

SEEK COMPLETE

WRITE FAULTI
WRITE PROTECT

Functions the same as the DRQ
line. When set, it indicates that
the sector buffer is ready to accept data or contai ns data to be
read by the host. The data request bit is reset when the
sector buffer has been fully
read or written. Normally, the
host need not consult this bit to
determine if a byte should be
transferred.
Indicates the condition of the
seek complete line on the selected Winchester drive. For
Floppy drives, this line is asserted when the SDH register is
reloaded.

READY

BUSY

Indicates the condition of the
write fault line on a selected
Winchester drive. The WD100205 will not execute any command if this bit is set.
If a write-protected disk is
sensed in a selected floppy
drive during a write operation,
the write fault bit will be set.
The command will then be aborted and no writing will take
place.

Indicates condition of ready
line on drive. WD1002-05 will
not execute any commands unless the ready bit is set. Normally this line is asserted for
Floppy drives when the SDH
register selects any floppy
drive. A user available jumper
option can be implemented if
the READY line is available
from the floppy drive.
After issuing a command, or
initialing WD1002-05 internal
diagnostics, this bit will be set
indicating that the WD1002-05
is busy executing a command.
No other bits or registers are
valid when this bit is set.

COMMAND REGISTER
All commands are loaded into this register after the
task files have been set. Writing to this register will
cause the INTRQ Line to be reset. The command register is a write-only register. Refer to SECTION 6
(COM MAN DS), subsection 6.1 for further details.
5.11

5-4

SECTION 6
COMMANDS
6.1

GENERAL

Table 6-1.

The WD1oo2-05 executes six, easy-to-use, macro
commands. Most commands feature automatic "im-

Command Types

I TYPE ICOMMAND

I7

tell the WD1oo2-05 where the RlW heads of each
drive are nor when to move them- The controller automatically performs all retries on errors encountered,
including data ECC errors. If the RlW head mis-positions, the WD1002-05 will automatically perform a
restore and a re-seek. If the error is completely unrecoverable, the WD1oo2-05 will simulate a normal
completion to simplify the host's software.

II

11

The commands executed by the WD1oo2-05 are
mapped to the commands supported by the two disk
controllers. The format of the WD1oo2-05 commands
is the same as that of the WD1 01 0 commands. The
onboard WD1015 buffer manager translates this format for the WD2797, transparent to the user. Error correction and the Long modes are only supported for
the Winchester Disk Controller, therefore the host
0 and L
0 for all the
must set SDH bit 7
commands when a floppy disk is selected.

L = Long bit
: 0
M Multiple sect: 0
D read interrupt: 0

nlion" coo~ \Alhil"h rnO!lnc tho hnct c\l~torn noon nnt
t-"''"'~
.... """"'." •• 1""" II."'......... ..., ... ,"" •• ..., ...... """1""''''''''' •• .....,.....,"'" I.","

=

.. _....... -

I
II
III
III

Seek
Read Sector
Write Sector
Format Track

=
=

1
1
1
6.2.1

=

No command will execute if the seek complete or
ready lines are false, or the write fault line is true.
Normally it is not necessary to poll these signals before issuing a command. If the WD1oo2-05 receives a
command that is not defined in Table 6-1, undefined
results will occur.

Commands have been divided into three types as
summarized in Table 6-1_

.t:,.

• I

'V

r3
D
0
0

r2
M
M
0

r1
L
L
0

ro
0
0
0

= Long mode

= Multiple sector
= DMAMode

ra-ro - Stepping Rate
Floppy Disk Drives
~15

I-is

1.0 ms

1.0 ms

2.0ms

1.5 ms

3.0 ms

2.0 ms

4.0 ms

2.5 ms

5.0ms

3.0 ms

6.0 ms

3.5 ms

8.0 ms

4.0 ms

10

ms

1001

4.5 ms

12

ms

1010

5.0 ms

14

ms

1011

5.5 ms

16

ms

1100

6.0 ms

18

ms

6.5 ms

20

ms

25

ms

40

ms

1101

6-1

'v

= Programmed I/O Mode

0.5 ms

1000

WD1002-OS COMMAND SUMMARY

1
0
1
1

= normal mode
= Single sector

~35 I-is

0000
0001
0010
1 0011
0100
0101
0110
0111

• For any write/format operations, the sector buffer
must be filled with the appropriate data before the
command can be executed by the WD1 002-05.

-- -

0 1 1
0 0 1
0 0 1
0 1 0

Winchester Disk Drives

r3-ro

• The task file must be loaded prior to issuing a
command. Only parameters that change from the
previous command need be entered.

0 0

STEPPING RATES

Table 6-2.

Commands are executed by loading the command
byte into the command register while the controller
is not busy. The host must observe the following
simple protocol:

6.2

I Test

BITS
6 5 43210

I

1110

7.0 ms

11111 1

7.5 ms

I

I

6.3 TYPE I COMMANDS
Type I commands do not effect transfer of data between the host and the WD1002-05 but merely position the RJW heads of the selected drive or run
diagnostics. The restore and seek commands have
explicit stepping rate fields. The lower four bits of
these commands form the stepping rate for the
drives.
6.3.1

6.3.3

Bit code: 0

1

1

1

R3

R2

R1

RO

The seek command positions the RJW head at a certain cylinder: It is primarily used to start two or more
concurrent seeks on drives that support buffered
stepping. Note that the seek complete line is not
sampled after the seek command so that multiple
seek operations may be started using drives with
buffered seek capabi Iity.

TEST COMMAND

Bit code: 1 0 0 1 o· 0 0 0
The test command is used to run internal diagnostics
for checking WD1002-05 board function. It is mainly
employed to isolate faults in the board logic. This
command is always executed on a MR strobe. Any
faults are reported as error codes. (See Section 5.4 for
a description of the error codes.)
6.3.2

SEEK

6.4

TYPE II COMMANDS

Type II commands characteristically transfer blocks
of data from the WD1002-05 buffer to the host. This
type of command has an implicit stepping rate as set
by the last restore or seek command.
6.4.1

READ SECTOR

Bit code: 0

RESTORE

0

1

0

D

MOO

The read sector command is used to enable the host
computer to read a sector of data from the disk. If
ECC is enabled, ECC bytes are recomputed by the
WD1002-05. After the buffer is full, the recorded ECC
bytes are compared to the recomputed check bytes
to generate the syndrome bytes. If the syndrome is
non-zero, errors have occurred. Error correction is
invoked by the WD1015 if two consecutive syndromes match, otherwise a maximum of 8 retries is
attempted by the WD1015. If the data is correctable,
the WD1015 makes the correction and passes the
data in the buffer to the host. If, after eight retries, the
syndromes do not match, the WD1002-05 sends an
error status to the host along with the status from the
WD1010. Multiple sector read commands are modified to single sector commands and are issued a multiple number of times. The status and error registers
are updated for every block of data transferred.

Bit code: 0 0 0 1 R3 R2 R1 RO
The restore command is used to calibrate the position of the RJW head on each drive by stepping the
head outward until the TROOO line goes true. Upon receipt of the restore command, the BUSY bit in the
status register is set. Cylinder high and cylinder low
registers are cleared. For Winchester operation, the
actual stepping rate is determined by the Seek Complete period. For Floppy operation, a minimum stepping pulse of 8 msec. is used. However, the stepping
rate field specified by the host is saved internally for
use in all future implied seeks. The state of seek
complete, ready and write fault are sampled, and if an
error condition exists, the aborted command bit in
the error register is set, the error bit in the status register is set, an interrupt is generated, and the BUSY
bit is cleared.
Regardless of errors encountered, the internal head
position register for the selected drive is cleared. The
TROOO line is sampled. If TROOO is true, an interrupt is
generated and the BUSY bit is reset. If TROOO is not
true, stepping pulses at a rate determined by the
stepping rate field are issued until the TROOO line is
activated. When TROOO is activated, the busy bit is
reset and interrupt is issued. If the TROOO line is not
activated within 1024 stepping pulses, the TROOO
error bit in the error register and the error bit in the
status register are set, the BUSY bit is reset, and an
interrupt is issued.

During a Floppy read sector operation only CRC is
used with the data fields. If a CRC error occurs in the
data field, the WD1015 buffer manager attempts a
maximum of 8 retries and reports the error only if it
persists. Regardless of the drive accessed (Winchester or Floppy), CRC is used on alliD fields.
6.4.1.1

READLONG Command

Bit code: 0

0

1

0

D

M

1

0

This command is similar to the read sector command
except that the ECC operation producing the syndrome is inhibited in the WD1002-05. Instead, the
W01002-05 copies the four recorded check bytes
from the disk and passes them unaltered to the host.
This command is useful in debugging and verifying
the ECC hardware and software. To do this, first write

6·2

normally and then issue the REAOLONG command.
The data, or the check bytes may now be altered by
the host and written to the disk using the WRITELONG command. If a read command is now issued,
the W01002-05 will correct it as long as the error induced is within the correction capability of the EGG
polynomial. This mode is not supported for floppy
disk.
6.4.1.2

6.5.1

Bit code: 0

o = OMA Read Mode
o = Programmed 110 mode

6.5.1.1

= OMAMode

=

6.5.2

0

0

0

1

10M

1

0

FORMAT TRACK

Bit code: 0
Normal Completion

1

0

1

0

0

0

0

The format command is used for initializing the 10
and data fields on a particular disk. Upon receipt of
the format command, the controller sets the ORO for
the interleave table to be written to the buffer. In all
cases, the number of bytes transferred to the buffer
must correspond to the current sector size.

A normal completion occurs when the W01002-05 encounters no errors. The BUSY bit is reset. The status
of the OMA bit in the command byte is examined. If
this bit is reset (0 = 0; programmed 1/0 mode), an interrupt is issued at this time. ORO is set until all
bytes of data have been read from the buffer. (Note: It
is recommended that programmed 1/0 transfers
should take place as a block move without consulting the ORO bit in the Status Register.) After all the
data has been moved from the buffer, the OMA bit in
the command byte is consulted again. If this bit is set
(0 1; OMA mode) then an interrupt will be issued.

When the buffer has been completely filled, the
specified number of sectors are written and the ORO
is reset. The data field is written with 00 for the hard
disks and E5 (hex) for the floppies. EGG or GRG bytes
are automatically computed and written.

=

6.5

10M

The WRITELONG command functions similarly to
the write sector command except that the EGG operation that computes the EGG word is inhibited in the
W01002-05. Instead, the W01002-05 accepts a 4-byte
appendage from the host and passes it unaltered to
be written on the disc at the end of the data as check
bytes. This mode is not supported for the floppy
discs.

=

6.4.1.3

1

WRITELONG Command

Bit code: 0

The OMA bit is used to position INTRa in relation to
OROs during the read sector command. If the OMA
bit is reset (0 0), the interrupt will occur along with
the ORO. This allows the programmed 1/0 host to intervene and transfer the data from the sector buffer.
For programmed 1/0, multiple transfer is not permitted (M 0). If the OMA bit is set (0 1), then the
interrupt will occur only after the system OMA controller has transferred the entire buffer of data. This
mode is always used with multiple sector transfers.

=

0

The Write Sector command is used to write a sector
of data from the host computer to the disk. Upon receipt of the write command, the controller sets ORO
untii the entire sector iength of data has been written
into the buffer. (Note: It is recommended that programmed 1/0 transfers should take place as a block
move without consulting the ORO bit in the Status
Register.)

DMA Read

1

WRITE SECTOR

Once the index is found, a number of 10 and data
fields are written to the disk. As each sector is written, the sector count register is decremented and
consequently must be updated before each format
operation.

TYPE III COMMANDS

This type of command is characterized by a transfer
of a block of data from the host to the W01002-05 buffer. These commands have implicit stepping rates as
set by the last restore or seek command.
The command wili not be executed by the W01002-05
controller unless the buffer has been completely
filled by the host.

6·3

SECTION 7
PROGRAMMING
7.1

GENERAL

ware should be designed to read or write all data that
is directly accessible by all the heads on a positioner
before stepping to a new cylinder. Table 7-1 presents
a cylinder-by-cylinder sequential file read on a four
head, two-piatter disk drive.

Users will find programming the WD1oo2-05 relatively
simple as a substantial amount of intelligence formerly required by host computers has been incorporated into the WD1 002-05 board.
The \'I./D1002-05 performs all needed retries, even on
head positioning errors. If there is an error in the data
field, the WD1oo2-05 will attempt to correct it.

Table 7·1.
Physical
Cylinder

Most commands feature automatic "implied" seek,
which means that seek commands need not be issued to perform basic read/write functions. The
WD1oo2-05 keeps track of the head position up to
eight read/write head assemblies, eliminating the
need for the host system to maintain track tables.

Logical
Head
Number

3

25
26
26
26
26
27

All transfers to and from disk are through an on-board
sector buffer. This means that data transfers are fully
interruptable and can take place at any speed that is
convenient to the system designer. In the event of an
unrecoverable error, the WD1oo2-02 simulates a
normal completion so that special error recovery
software is not needed.

7.3

0
1
2

3
0

Physical
Head Side

Physical
Platter

Top
Bottom
Top
Bottom
Top
Bottom

SETTING UP TASK FILES

B

A
A
B
B
A

I

TYPE I COMMAND PROGRAMMING

1. Set up task file and issue command with stepping
rate (WD1oo2-05 will attempt to execute Type I

Before any of the six macro commands may be executed, a set of parameter registers called the task
files must be set up. For most commands, this
informs the WD1oo2-05 of the exact location on the
disk where the data involved in the transfer is located
or will be placed. For a normal read or write sector
operation, the sector number, the size/drive/head, the
cylinder number, and the command registers (usually
in that order) wi II be written.

command)
2. Wait for interrupt or for BUSY bit in status register
to be reset
3. Check error bit in status register for proper
completion
7.3.1

USE OF BUSY BIT

Note that although most of these registers are readable as well as writable, they are normally are not
read from. Read capability for them is provided, however, so that error-reporting routines can determine
physically where an error occurred without recalculating the sector, head, and cylinder parameters.

Smaller, single-user systems can sense the completion of a command by polling the BUSY bit of the
status register. This bit (bit 7) is set whenever the controller starts a disk operation or internal diagnostics,
and is reset whenever the controller is ready to communicate with the host computer.

Since all the task file parameters can be recalled by
the WD1oo2-05, it is recommended that task file
parameters be stored in the WD1oo2-05 as they are
calculated. This will save the programmer a few instructions and microseconds by not maintaining two
copies of the same information.

On the WD1002-05, the BUSY bit is located in the
same place as the sign bit of many computers to simplify the polling process.

7.2.1

I

Test, Restore and seek are Type I commands that
position the R/W heads of the selected drive and set
the implied stepping-rate register. No data is
transferred to or from the data register. To execute a
Type I command, the system software must perform
the following functions in the order shown:

This section assumes that the user has read Section
5 (Task File) and Section 6 (Commands).
7.2

File Read on 4-Head, 2·Plaiter Disk Drive

One way to poll this bit using 8080 code is as follows:
WAIT:

CYLINDERS AND TRACKS

Since most hard-disk drives contain more than one
head per positioner, it is more efficient to step the
R/W head assemblies of most disk drives by cylinders, not tracks, In other words, the disk driver soft-

7=1

IN

STATUS

ANA

A

JM

WAIT

;lnputWD1002-05
Status register
;Update 8080 sign
flag
;Wait if BUSY (sign)
bit set

This is another way to poll the BUSY bit using PDP-11
code:
WAIT:

7.3.2

7.4

The only Type II command is the read sector command. This command is characterized by the transfer
of a block of data from the WD1oo2-05 buffer to the
host. The command features implied seek with an
implicit stepping rate. To execute a Type II singlesector command in programmed I/O mode, the system software must perform the following functions
in the order shown:

MOVB @#STATUS,R> ;Input status,
update sign flag
;Wait if BUSY (N) bit
BMI
WAIT
set
USE OF INTERRUPTS

Another, more efficient way of notifying the CPU that
the WD1oo2-05 has completed a command is through
interrupts. The INTRQ line on the WD1oo2-05 makes
a low to high transition whenever the disk controller
requires CPU intervention. This allows the host CPU
to run other tasks while the WD1oo2-05 is reading or
writing data to the disk.
7.3.3

1. Set up task file and issue command with DMA bit
reset (WD1 002-05 will attempt to read sector)
2. Wait for interrupt or for BUSY bit in status register
to be reset

3. Perform a block move from WD1oo2-05 buffer to
system memory

USE OF THE ERROR BIT

4. Check error bit in status register for proper
completion

As the WD1oo2-05 simulates normal completions
when errors have been encountered, the only way to
determine error status is to check the error bit in the
status register. The WD1002-05 error bit is so located
that it can be easily tested by rotating it into the carry
bit of many processors. The contents of the error register are not valid unless the error bit is set.

Note: Steps 3 and 4 above can be reversed.
To execute a Type II single or multiple sector command in DMA mode with interrupts, the system software does the following:
1. Set up task file and issue command with DMA bit
set

One way to check the Error bit using 8080 code is as
follows:
IN

STATUS

TYPE II COMMAND PROGRAMMING

2. Set up DMA controller (WD1002-05 will attempt to
read single or multiple sectors) (DMA controller
will move data from WD1002-05 to memory)

;Get status (if not
al ready inA)
;Rotate error bit
intoC
;Jump if error found

4. Check error bit in status register for proper
completion

In certain hardware configurations, the following can
check the error bit using PDP-11 code:

Note: The above sequence is preferred, but steps 1
and 2 above can be reversed.

RAR
JC

BIT
BNE

7.3.4

ERROR

3. Wait for interrupt from WD1002-05

@#STATUS,#1 ;Bit test the error bit
ERROR
;Branch if error
found

7.4.1

The DMA mode bit (D) in the foregoing read sector examples is a special bit in the command byte used to
optimize the WD1002-05 interrupts during programmed 1/0 and DMA operations. If the DMA bit is
reset (D 0), the interrupt will come before the buffer
is transferred. This allows a programmed 1/0 host to
intervene and transfer the buffer of data. If the DMA
bit is set (D 1), then the interrupt will occur only
after the data has been transferred. This allows the
host to go uninterrupted until the entire buffer has
been transferred.

USE OF THE CORRECTED BIT

Correctable errors are usually quite benign and can
almost always be ignored. Some systems designers,
however may wish to log their occurrence. The corrected bit has been placed in the status register to
facilitate error logging. Correctable and fatal errors
can be detected with the following 8080 code:
IN

STATUS

ANI

5

JNZ

SOMERR

DMA MODE

=

=

;Get WD1oo2-05
status
;Mask off Error and
Correct bits
;Jump if we have
either a
;correctable or fatal
error

7.4.2

BLOCK MOVES

The WD1002-05 performs all transfers between itself
and the disk drive through an on-board full sector buffer. Once the disk has been read, the data is available
to the host at any rate from DC to as high as a byte

7·2

every 500 ns. In programmed 1/0 applications there is
no need to consult the DRO bit in the status register
to determine if another byte is ready to be processed.
Once an interrupt occurs or the BUSY bit is reset on a
read, the host computer should do a block move of
all the bytes in the sector.
The following 8080 code demonstrates a transfer
from the WD1oo2-05 to system memory. The transfer
address is in HL and the byte count is in B:
READ IT: IN

DATA

MOV
INX

M,A
H

DCR

B

JNZ

READIT

7.4.4.1 Partial Sector Transfers
The WD1oo2-05 permits partial sector transfers on
read operations. This allows the user to read the first
part of a sector and discard the rest. During programmed 1/0, the byte counter in the block move
routine is set to the number of bytes to be read.
During DMA operations, the DMA controller is set
with the number of bytes to be transferred.
Normally, during a DMA read operation, the
WD1002-05 interrupts the host after a sector has
been transferred. However, if only a partial sector is
being read, the WD1oo2-05 does not know that the
operation has been completed. Therefore, the 'transfer complete' interrupt must come from the DMA
controller.

;Get data from
WD1oo2-05 sector
buffer
;Store it in memory
;Increment memory
pOinter
;Decrement byte
counter
;Do it again if whole
sector not xferred

During write sector operations, the DMA controller
will interrupt the system after the buffer has been
transferred to the WD1oo2-05, but before the data
have been written. Some systems with advanced interrupt handling capabilities can easily mask off this
spurious DMA interrupt. For those systems that cannot, the WD1oo2-05 has a provision built into its
command structure to detect read operations.

The following Z-80 instruction does it all. The transfer
address is in HL, byte count is in Band WD1002-05
data register address in C:
READIT: INIR

7.4.3

;Transfer buffer
from WD1oo2-05 to
memory

7.4.4.2

Bit 4 of all commands determines whether the operation will be a read sector operation or something
else. Those commands that require the interrupt from
the WD1oo2-05 have this bit set to 1. The read sector
command (the only one that might need the DMA
controller's interrupt) has this bit set to a O. Bit 3 of
the command is then used to select either
programmed 1/0 interrupts or DMA type interrupts.

USING DMA

A special bit in the read sector command optimizes
the WD1oo2-05 in terrupts for DMA operation.
7.4.4

Interrupt Source Selection

MULTIPLE SECTOR TRANSFERS

The WD1oo2-05 can transfer more than one sector
per command, if interfaced, using DMA and interrupts. Transfers as large as an entire track can be executed. The sector count register holds the number of
records to be transferred (if sector count is zero, then
256 records will be transferred.) The sector number
register holds the starting sector of the transfer.
When a multiple sector transfer is successfully
completed, the sector count register will be equal to
zero and the sector number register will be equal to
the last sector transferred plus one.

7.4.4.3

Clearing Hardware DRQ

During partial sector reads, the DMA controller will
stop the DMA transfer before the WD1oo2-05 has a
chance to issue its last data request. Because of this,
the DRO line might be set the next time transfer parameters are sent to the DMA controller. To avoid
spurious (and often fatal) DROs, the user must do a
hardware clear of the DRO line unless another command is issued. DRO is actually cleared by doing
dummy reads of the data register to dump the rest of
the data.

If a fatal error is encountered during a multiple sector
transfer, the sector number register will be left pointing to the sector that contained the fatal error, and
the sector count register will hold the number of sectors that were not transferred.

7.4.4.4 Interrupt Selection Circuit
If the user is reading partial sectors with the
WD1oo2-05 and wants to have the system automaticaUy configure its interrupts! a circuit similar to that
shown by Figure 7-1 will have to be implemented.

tf a correctabfe error is encountered during a multiple
sector read, the corrected bit in the status register
will be set, but the operation will not be terminated
because correctable errors are not considered fatal.

7-3

WD1002
INTRQ
MR
DAL4

~

I

r.4:,

)

u

u

SYSTEM
INTRQ

CS
Q

WE
AO
DMA
INTRQ

Figure 7·1.

Interrupt Selection Circuit

SIMULATED COMPLETIONS
All W01002-05 commands (except multiple sector
transfers) act in precisely the same manner, whether
or not an error was encountered. The only way to determine whether an error has occurred is to sample
the error bit in the status register. Simulated completions offer the system designer the following tangi·
ble benefits:
• Simplifies masking and generation of interrupts
• Simplifies non·error handling portions of the
system software
• Eliminates the software overhead of handling
different types of errors

7.4.5

3. Wait for interrupt or for BUSY bit in status register
to be reset
4. Check error bit in status register for proper
completion
To execute a single or multiple sector Type III command in OMA mode with interrupts, the system software goes through the following steps:
1. Set up task file and issue command
2. Set up OMA controller (OM A controller will move
data from memory to WD1002-05) (W01002-05 will
attempt to write sector or format)
3. Wait for interrupt from W01002-05
4. Check error bit in status register for proper
completion

• Simplifies system software error handling
validation (any error is handled the same way as
any other errory

Note: Steps 1 and 2 above can be reversed.

• Prevents system failure in the event of some
obscure error condition that the system program·
mer did not antiCipate

FORMATTING
The format command is very similar to the write sector command, except that the sector buffer is filled
with interleave and bad block information instead of
with user data. Two bytes will be written to the buffer
for each sector to be formatted.
The first (lowery byte will be either a 00 or an 80 in hex.
If the lower byte is a 00, the sector is marked as good.
If the lower byte is an 80, and there is any attempt to
read it or write to it, the sector will set the bad block
bit in the status register. See cautions regarding
media imperfections mapping in subsection 7.5 Bad
Block Mapping.
The second (uppery byte is the logical sector number
of the next sector to be formatted. This number will
be recorded on the disk. The sector number register
is not used during format.
7.5.1

TYPE III COMMAND PROGRAMMING
Write sector and format are Type III commands.
These commands are characterized by the transfer of
a block of data from the host to the W01 002-05 buffer.
Like the Type II commands, these commands feature
implied seek with an implicit stepping rate. To execute a Single sector Type III command in programmed I/O mode, the system software must go
through the following functions in the order
indicated:
1. Set up task file and issue command
2. Perform block move from system memory to
W01002·05 buffer (W01002·05 will attempt to write
a sector or format)
7.5

7·4

On a 32-sector-per-track disk, 32 pairs of bytes containing formatting information must be supplied to
the drive during each format operation. To start the
format operation, the buffer must be completely
filled, even if the sector table is not as long as the
buffer. This means that on a 32-sector-per-track disk,
with 64 bytes of formatting information supplied, if
the sector size is 256 bytes, then 192 bytes of garbage must be passed to the controller to start the for. mat operation.

The first byte in each byte-pair in Table 7-2 is set to 00.
This marks each block as a "good" block. The second byte of each byte-pair is the logical sector number. The first byte pair in Table 7-2 represents the first
logical sector of the track. The underlined byte pair
represents the second logical sector.
7.6

Winchester and thin-film-technology drives often do
not have perfect media Manufacturers allow imperfections in the media to reduce cost which consequently lowers the cost of drives.

As the contents of the sector buffer do not imply how
many sectors are to be formatted, a dedicated register is provided. This Sector Count register must be
loaded with the number of sectors to be formatted
before every format operation. To calculate the maximum number of sectors per track, see Appendix C.
7_5.2

BAD BLOCK MAPPING

The user of the W01002-05 which interfaces with
Winchester and thin-film-technology drives is required to map out any media imperfections. This can
be accomplished in various ways, some highly operating-system dependent. Here are a few ideas:

INTERLEAVING

If sequential sectors on the disk are to be read, the
next sector will pass by the read/write head before a
read or write can be set up. The disk will then have to
make a complete rotation to pick up this next sector.
If an attempt is made to read all 32 sectors on a.particular track, it requires 32 rotations or about a half-.a
second per 8K bytes. This performance can be significantly improved by interleaving, a technique that
allows the system to read or write more than one
sector per rotation.

7.6.1

SECTOR PRE·ALLOCATION

If the operating system supports random sector or
group allocation, the bad blocks can sometimes be
mapped out by recording an un-deletable file, using
all the bad sectors on the disk. When the operating
system tries to write to the bad block, it wi II see that
the sector or group that contains the error has already been allocated. The operating system will automatically map over the bad sector.

Suppose the system takes less than three sector
times (3 times 32 rotational periods with 256 byte sectors) to digest the data that it has read and to set up
the next read operation. This means that if the second logical sector can be physically placed four sectors away from the fi rst one, the controller wi II be
able to read it without much delay. This four-to-one interleave factor will allow a potential reading of the entire track in only four rotations. In the example given,
the throughput will be increased by a factor of eight.

There are some minor restrictions associated with
this form of bad-block mapping: the file that contains
the bad sector must never be moved to another section of the disk, the bad sector file may not be read
(for obvious reasons), and reads or writes to the disk
that do not consult the disk allocation map (physical
reads/writes) are not allowed.
Table 7·2.

The simplest way to determine the optimum interleave for any particular system is through experimentation. If the system maintains its directories or
virtual memory-swapping areas in a certain place on
the disk, it sometimes makes sense to have more
than one interleave.

00
00
00
00
00
00
00
00

To simplify driver software, the W01002-05 will automatically map logical sectors to physical sectors to
achieve interleave. This logical-to-physical map is recorded during the format operation on each track of
the disk in the 10 fields of the sectors. Table 7-2 is an
example of an interleave table for a 32-sector track
with 4:1 interleave and no bad blocks.

00
01
02
03
04
05
06
07

Interleave Table with 32 Sectors and
4:1 Interleave

00
00
00
00
00
00
00
00

08
09
OA
OB
OC
00
OE
OF

00
00
00
00
00
00
00
00

10
11
12
13
14
15
16
17

00
00
00
00
00
00
00
00

18
19
1A
1B
1C
10
1E
1F

Note: The balance of the buffer must be filled with
something to start the format operation.

7·5

7.6.2

ALTERNATE TRACKS

Please note that when formatting the disk in this
manner, at least one sector must have an illegal sector number. Also, as one sector has been allocated to
bad block mapping, a sector 1 F no longer exists.

The alternate-track method works on most operating
systems but requires more software overhead. Whenever a read or write is attempted, the track number
(cylinder and head select) is checked against a table
maintained by the operating system or driver. If the
track number matches the table, the driver knows
that there is a flaw somewhere on that track and
looks up the alternate track for the flawed one. The
read or write is then performed elsewhere.

7.6.4

The WD1oo2-05 allows the user to set a marker that is
recorded into the ID field. When the WD1oo2-05 attempts to read or write a sector with a bad-block mark
set, the operation will be aborted and the error bit in
the status register and the bad-block bit in the error
register will be set. The size, head, cylinder, sector
and 10 CRC fields of the selected sector must be
correct in order to detect a bad-block mark. This
means the ID field must be error-free in order to detect the bad block mark.

The primary disadvantage of this type of bad-block
mapping is the high software overhead. When the
system is brought up, the alternate-track table has to
be read from a flawless area of the disk. After it has
been read, every read or write operation must check
the alternate-track table before performing its respective operation.
7.6.3

Table 7-4 shows an interleave table where the
user has marked all the sectors with a bad-block
mark and recorded all sectors redundantly. The
interleave is not very important here, because it is
assumed that the driver will not attempt to read bad
sectors sequentially.

SPARE SECTORS

The spare-sector method is probably the simplest to
implement in most systems. Its primary disadvantage is that at least one sector must be set aside as a
spare for each track. During format, the physical sector that contains the flaw is written with some illegal
sector number. The physical sector following it contains the real logical sector and its data. Table 7-3 is
an interleave table that shows how the user mapped
out the fifth physical sector by telling the WD1oo2-05
to write a logical sector number of FF to it.
Table 7·3.

00
00
00
00
00
00
00
00

Table 7·4.

80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80

Interleave Table with 32 Sectors and
4:1 Interleave - Physical Sector Five
Mapped Out

00

00

FF
19
1A
1B
1C
1D
1E

00
00

00
00
00

00
00

08
01
02
03
04
05

00
00
00

06

00
00
00
00

07

00

10
09
OA
OB
OC
OD
OE
OF

00
00

00
00
00

00
00

00

BAD BLOCK BIT

18
11
12
13
14
15
16
17

7·6

00
04
08
OC
10
14
18
1C

00
04
08
OC
10
14
18
1C

Interleave Table with Redundant Sectors,
No Interleave, and All Sectors Marked as
Bad Blocks
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80

01
05

09
OD
11
15
19
1D
01
05

09
OD
11
15
19
1D

80
80
80

80
80
80
80
80
80
80
80
80
80
80
80
80

02

06
OA
OE
12
16
1A
1E
02

06
OA
OE
12
16
1A
1E

80
80
80

80
80
80
80
80
80
80
80
80
80
80
80
80

03
07
OB
OF
13
17
1B
1F
03
07
OB
OF
13

17
1B
1F

SECTION 8
THEORY OF OPERATION
8.1

GENERAL

Prior to issuing any command to the WD1002-05, the
host must first set up command parameters in the
task file registers, i.e. sector size, drive select information, settor number accessed, etc. The host must
then fill the sector buffer with the required data if
either a WRITE or FORMAT command is to be executed by the WD1002-05. The WD1002-05 BUSY
status bit is set when the sector buffer has been
filled by the host, or immediately upon receipt of
any other type of command from the host. The
WD1002-05 then executes the command issued, at
which time all communications between the host
and the WD1002-05 are suspended. The only access
available to the host is the ability to poll the status of
the BUSY bit. The command issued by the host is
read by the CP from the command register in the task
file, interpreted, and re-issued to either the Winchester or floppy disk processor, or executed directly
by the CPo Upon completion of the command, the
WD1002-05 sets the INTRa/DRa lines, dependant
upon the type of command issued, and clears the
BUSY bit. At this time, the host can read status and
error information from the task files before issuing
another command.

The WD1002-05 Winchester Floppy Disc Controller
(WFC) is a stand-alone general purpose controller
board designed to provide a buffer interface between
a host controller and a combination of up to three
Winchester disc drives and four floppy disk drives.
The WD1002-05 is fabricated using a proprietary chip
set designed specifically for Winchester Floppy disc
control.
The design of the WD1002-05 circuitry implements all
of the logic required for host interface, WD1002-05 internal diagnostics, variable length sector buffer, task
files, ECC diagnostics and correction, data separation, and WD1002-05 control. The Winchester drive
signals from the host controller are based upon the
floppy look-alike interface with the Seagate Technology ST506 and other compatible drives. All necessary drive signal decoding for the floppy disc drives
is performed solely by the WD1002-05 so that the
host controller sees only Winchester drive signal
format.
8.2

WD1002·05 ARCHITECTURE AND
FUNCTIONAL DESCRIPTION

The internal structure of the WD1002-05, illustrated in
Figure 8·1, consists of six major functional blocks as
well as all necessary support logic. They are as
follows:

8.2.1

The HIL contains the requisite logic to buffer all datal
command access between the host, the WD1002-05,
the WD1010, and the WD2797 controllers. Bus protocol is exactly the same as the WD1010 Hard Disc
Controller device. All data and command information
is transferred on an 8-bit DAL bus. This tristate asynchronous bus is controlled by the host, only if the
WD1002-05 is not BUSY. The host accesses the
WD1002-05 ~resenting a stable address (AO-A2)
along with a RE or WE strobe qualified bY' CS. The direction of transfer is determined by the RE and WE
signals. For DMA transfers, the WD1002-05 provides
a DRa signal to inform the DMA controller of a pending transfer. HIL also produced INTRa for interrupts
after commands, or to signal a transfer completion
for Interrupt Driven Systems. The host may reset the
WD1002-05 by asserting MR (if MR is asserted, the
WD1002-05 internal diagnostics routine is initiated
and the host must wait for BUSY to be cleared before
issuing a command to the WD1002-05).

1. Host Interface Logic (HIL)
2. Buffer Manager Control Processor (CP)

3.
4.
5.
6.

HOST INTERFACE LOGIC (HIL)

Error Detection and Support Logic (EDS)
Sector Buffer (SB)
Winchester Disc Drive and Buffer Interface (WDBI)
Floppy Disc Drive and Buffer Interface (FDBI)

The host can communicate with the Winchester or
floppy disc via the SB. On power·up, the host is
required to strobe MR which in turn causes the
WD1002-05 to execute a speCial TEST command that
initiates internal diagnostic routines within the
WD1002-05 to ensure the functionality of the
WD1002-05. The internal diagnostic routines can also
be exercised by the host explicitly, in addition to five
other macro commands used to execute disk operations. The six macro commands are as follows:

The HIL passes DATA and COMMANDS to the EDS
and CP along with processed strobes derived from
WE, RE, CS, and A2-AO signals. HIL receives DATA
and STATUS from the EDS and CP along with control
information concerning DRa and INTRa generation.

1. TEST
2. RESTORE

3. SEEK
4. READ

5. WRITE
6. FORMAT

8·1

- MFMRD
+MFMRD

HOST
1/0 BUS

DATA
SEPARATORI
WRITE
PRECOMP,

-MFMWD
+MFMWD
R[5r1-RO~ (:'j)
DS1-DS3 (3)
WG

WD1010
WINCHESTER
DRIVE
CONTROLLER
(WDC)

SECTOR
BUFFER
(SB)

SDH LATCH,
WINCHESTER
DRIVE BUFFER
INTERFACE
(WDBI)

RWC
STEP PULSE

WINCHESTER
DI~IVE

DIR IN

110

(MAX3
DmVES)

TNi)"E'5(

1K X 8

.. TROOO
SEEK COMP
WRITE FLT
READY
WD1014
ERROR
DETECTIONI
SUPPORT LOGIC
(EDS)
WD1015
CONTROL
PROCESSOR
(CP)

,.. . , ; - - - - - - - - - - - - - - - - 1
__ -/

WD2797
FLOPPY DRIVE
Wm"77,;~~ CONTROLLER
(FDC)

.. READ DATA
FLOPPY DISC
DRIVE BUFFER
INTERFACE
(FDBI)

I
L
____ --,
17'.b777.~~'TTH777.~'7'777'TT'.Q.A,.,_,~~/h,.,..,..,.,..".
I

0

1 MHZ
20 MHZ Cl

CLOCK
GENERATOR

2 MHZ
5 MHZ
10 MHZ

f

f

~

DATA BUS
CONTROL BUS

-

TKOO
4_INDEX
WRITE PROTECT

SIDE SELECT
STEP

FLOPPY DISC
DIRIVE 1/0
(MAX 4
DI=!IVES)

I

I

I

MOTOR ON
DSO-DS3 4

I

I
I

I
I

LNOTONWD1002-HDO

Figure 8·1.

WD1002·0SIWD1002·HDO Functional Block Diagram

___ _

_ _ ._._ _ --1

8.2.2

!he C~ uses a 10 MHz clock (2XDR), giving an
instruction cycle time of 1.5 I-ls. Most instructions
execute i n 3~O I-ls, or two cycles.

CONTROL PROCESSOR (CP)

The main control center of the WD1002-05 is the CP
(WD1015), used in conjunction with the EDS
(WD1014) device, the clock generator, and the task
files (TSF). The EDS device is the right hand of the CP
and of sufficient complexity to be treated as a
separate functional entity.
The CP controls the transfer of information within the
WD1002-05 and maintains the necessary copies of
the TSF found on both drives. Host access to the
WD1002-05 causes the CP to access task file information in the TSF after a command is issued. The
TSF are physically located in the controller chips and
on-board external logic is used to reflect any
changes such as error and status information required to integrate the floppy format to that of the
Winchester controller. Depending upon the command, the CP will make the buffer accessible to the
host, the WD1 01 0, or the WD2797 controllers.

8.2.2.2

8.2.3

ERROR DETECTION AND SUPPORT
LOGIC (EDS)

The WD1014 EDS chip provides the WD1002-05 with
Err?r Correction Capabilities (ECC) and support
logic. The EDS chip is a single chip device
specifically designed to add ECC to the 5.25"
Winchester disc drives. The EDS also contains three
8-bit registers, three counters, and several latches
that enhance the CP capabilities for control functions in a real time operation. This 40 pin chip
replaces approximately 35 TTL packages consisting
of shift registers, flip-flops, and combinatorial logic
gates.

The CP also controls the operation of the Error Correcting logic. During the transfer of data from the
host to the WD1010, the EDS monitors the data bus
(if so enabled), to compute a 4-byte ECC which is a~
pended to the end of the data transferred to the
WD1010 and recorded on the disc. During data transfers from the WD1 01 0 to the host, the CP uses the
ECC to validate the data. If the data is corrupted, the
CP envokes recovery techniques such as retries and
correction. A maximum of eight retries are attempted
if two consecutive syndromes do not match. Correction is attempted only if two consecutive syndromes
match. If the error is uncorrectable, the operation is
terminated.
The CP is also used to handle data transfers to and
from the SF for the floppy disc controller, which only
uses CRC check byte for its data fields.

8.2.3.1

Error Detection

The EDS processes all data transfers in either direction between the S8 and the WD1 01 0, if SDH bit 7 is
set. This bit should only be set for hard disc operation. The EDS generates the ECC/SYN DROM E bytes
by using a polynomial division process which can
provide unique code words for long streams of data.
The polynomial selected is a computer generated
code optimized for sector sizes of 128, 256, 512, and
1024 byte data fields. During NormallWrite operation
this division process produces a 32-bit remainde~
which is used as the four ECC bytes. In Normal/Read
operation, the ECC bytes are recomputed and
compared to the recorded ECC bytes to generate the
Four SYNDROME bytes. If the syndrome is zero,
there were no errors detected. Otherwise, the nonzero syndrome is used by the CP to compute the displacement of the error vector within the bad sector.
This information is then used to correct the data if a
stngte burst of no more than 5 bits in error occurred.

During status reads by the host, the CP consolidates
the normal completion status from the WD1010, the
WD2797, and the current EDS status into a form consistant with established WD1010 error reporting format. This consolidated status is then presented to
the host.
8.2.2.1

Task/Syndrome File (!SF)

The TSF provides on-chip storage of the required
task fi les for the WD1 01 0IWD2797 controllers and
the 4 bytes of syndrome used for ECC. The cheCk!
syndrome bytes are physically stored in the ECC generator/checker. The WD1014 (EDS) maintains its own
?ommand register which serves also as an error regIster upon command completion. All other registers
compriSing the TSF are physically part of the
WD1010 and WD2797 controllers. The CP controls all
access to the TSF. Refer to separate sections on task
files for their use.

Clock Generator

The 20 MHz oscillator drives the Clock Generator
which provides all timing clocks for the WD1002-05.
The crystal frequency divided by 2 is used as a reference clock (2XDR) and then divided again by 2 for a
1X clock (WCLK) which is used to clock the WD1010.
The Floppy Disc Controller (WD2797) operates with a
1 MHz clock for 5.25" drives. 2XDR divided by 10 is
used to produce the required 1 MHz clock.

During a WRITELONG operation, the EDS is inhibited
from computing the 32 bit ECC word. The EDS then
accepts a 32-bit appendage from the host and passes

8·3

WD1002-05 uses a multiplexed data/address bus to
share SB access and control lines with the WD1010.
Proper use of this interface results in having only a
presettable counter to control the buffer and a
latch/decoder to control up to three Winchester
drives. The counter is preset using two separate
strobes, one for each byte of the address, one 8-bit
counter package provides addressing capability for a
128 or 256 byte sector buffer size. By using more than
one counter package, the WD1002-05 permits a multiple sector buffer size of 64K bytes. The SOH latch is
used to provide drive selects 1-3 and head selects 0-7.

it on, unaltered, to the WD1010 to be recorded on the
disk. This permits the host to induce errors anywhere
in the data stream so that the operation of the EDS
can be validated during a subsequent READSHORT
operation.
Durina a READLONG ooeration. the EDS is inhibited
frorn producing a syndrome. Instead, it copies the recorded ECC check bits and passes them unaltered to
the host, appended to the end of the sector da~a
being read. As with WRITELONG, this command IS
useful when validating EDS performance.
The EDS uses a 2-bit serial implementation of the
generator polynomial during ECC generation and
error detection. During correction operations, a serial
reverse polynomial is used by the CP to compute the
error vector and displacement. Correctable errors are
corrected in the buffer without host intervention. Uncorrectable errors are reported to the host and the uncorrected data is transferred to the host for further
action.

8.2.5.1 Write Precompensation (WPC)
The generation of Modified Frequency Modulation
(MFM) write data takes place in the WD1010. This
device accepts a byte of data and a WCLK to produce
MFM data through internal circuitry which decides
when and where to write clocks and data on the data
stream under the MFM encoding rules. The MFM
data stream is now totally compatible with the
recording rules and may be sent to suitable line
drivers for transmission to the drive except for one
modification. Due to the decreasing radius on the
physical surface of the disk, the inside tracks have
less circumference and therefore exhibit a increase
in recording flux density over the outside tracks. This
increase in flux density aggravates a problem in
magnetic recording known as 'dynamic bit shift.'

8.2.3.2 Support Logic
The support logic consists of two 8-bit latches (command/error register and SOH latch). Data requests,
interrupts, BUSY, multiple mode, and read command
information is also maintained and updated in the
WD1014 to enhance the capability of the CP to
handle control functions in real time.
The EDS controls the buffer counter, incrementing
and presetting due to commands from the host, and
contains all the necessary logic to handle sector buffer overflow. Data, buffer addresses, and Drive/Head
select control are handled by the same multiplexed
8-bit address and data bus.
8.2.4

Dynamic bit shift comes about as the result of one bit
on the disk (a flux reversal) influencing an adjacent
bit. The effect is to shift the leading edge of both bits
closer together or further apart than recorded. The
net result is that enough jitter is added to the data
recorded on the inside tracks to make them harder to
recover without error.

SECTOR BUFFER (SB)

Write precompensation is used to reduce the effect
of dynamic bit shift. It is a way of predicting which
direction a particular bit will be shifted and intentionally writing that bit out of position in the opposite
direction to the expected shift. This is done by
examining the next two data bits, the last and the
present bits to be written and producing three signals depending on what these bits are. The three
signals are EARLY, LATE and NOMINAL. They are
used in conjunction with a delay line to cause the
leading edge of a data or clock bit to be written
earlier, later, or on time.
The processor can enable or disable the generation
of these signals by controlling the Write Pre-Comp
rNPC) line from the addressable latch. When WPC is
high, precomp is in effect. When WPC is low, no
precomp is generated and the nominal output of the
device is held true.

The S8 is used to buffer a sector of data being transferred to or from the host. The sector size may be
programmed for 128, 256, 512, or 1024 bytes. Thus,
the minimum RAM size required is 1KX8. The address counters are controlled by the CP and EDS. All
control signals for SB access are provided by 'the
WD1010, or the CP when communicating with the
floppy controller rND2797).

WINCHESTER DRIVE AND BUFFER
INTERFACE (WDBI)
The WDBI consists of the Winchester Disc Controller
rND1010), an 8-bit SOH latch, write precomp logic
rNPC), data separator, and appropriate drivers and receivers. The WD1010 is connected to the Winchester
drives and the SB by means of 20 signal lines that
form the WDBI. As previously mentioned, the
8.2.5

8·4

8.2.5.2

Data Separator

8.2.6

Data is recorded on Winchester discs using an MFM
technique. This technique requires clock bits to be
recorded only when two successive data bits are
missing in the serial data stream. The fact that clock
bits are not recorded with every data bit cell requires
circuitry that can remain in sync with data during the
absence of clock bits. Synchronous decoding of
MFM data streams requires the decoder circuitry to
synthesize clock bit timing when clock bits are missing and synchronize to clock bits when they are present. This is accomplished by using a phase-locked
oscillator employing an error amplifier and filter to
sync onto and hold a specific phase relationship to
the data and clock bits in the data stream. The phaselock occurs at 2x average data rate frequency (fo),
which in turn is used to synthesize a clock called
RCLK with a frequency 1/2 fo . This synthesized
clock can then be used to separate data bits from
clock bits with external logic to shift the resultant
serial data into registers for byte parallelization
within the WD1010.

FLOPPY DRIVE AND BUFFER
INTERFACE (FDBI)

The FDBI consists of a Floppy Disc Controller
tyVD2797), a drive select latch, head load, motor-on,
buffer management logic, and appropriate drivers
and receivers. The write precomp and data separator
are internal to the WD2797. The WD1oo2-05 can
support up to four 5.25" floppy drives, double density
and single ordouble sided tyVD1002-05 only).

=

8·5

SECTION 9
MAINTENANCE
9.1

GENERAL

9.3

When the board is shipped from the factory, all adjustments have been made using ST506 and SA450
drives. The user need not make any adjustments if
the drives supported are compatible with the forementioned drives.

WRITE PRECOMPENSATION
Strobe M R (U 15-19).
Jumper across E3-E4.
Observe pulse width on WD (U15-31).

There are four adjustments associated with the
WD1002-05 on-board data separation/write precomp
circuitry and VCO that might have to be made if a
drive with a different data rate is installed. On the
WD2797, the write precompensation value is
adjustable and the data separator might have to be
adjusted for drives of different data rates.
9.2

Adjust WPW (U15-33/R24) for desired pulse width
(Precomp Nominal Value).
DATA SEPARATOR
Observe pulse width on TG43 (U15-29).
Adjust RPW (U15-18/R25) for 1/8 of the read clock
(500 ns for 5.25" DD).

OSCILLATOR FREQUENCY

Observe frequency on DIRe (U15-16).

Data separation circuitry on the WD1002-05 uses a
voltage-controlled oscillator (V co) which phase-locks
onto incoming data and provides a clock suitable for
separating data and clock bits on an MFM-encoded
data stream. The Vco must be adjusted using the following procedures:

Adjust variable capacitor (C7) on Veo pin (U15-26) for
Data Rate (250 KHz for 5.25" DD)
Remove jumper between E3-E4.
Note: To maintain interval Veo operation, insure that
1 whenever a Master Reset pulse (MR) is
applied.

TEST

Connect a frequency counter to Test Connector
U30-10 (V co OUT).

9.4

Connect a DVM to Test Connector U30-1 (Vci IN).
Make all connections to the board, including the host
and drive. Adjust the variable capacitor C19 until the
frequency output locks onto the desired center frequency for the drive being used which is 10.000 MHz
for ST506 or compatable drive. Once this "locked-on"
frequency is achieved, continue the same adjustment for an input voltage of 2.5 ± 0.5 V.

RCLK

,4

=

TEST/OPERATION JUMPER VARIATIONS

1. E1 to E2

N.A.

2. E16 to E15

N.A.

3. E4 to E3

Normally open. Ground for
Floppy Write Precomp/Data
Separator adj. only.

4. E8/E10 to E9

GND (E8-E9)
No Write
Precomp.
Open
Write Precomp always.
E10 to E9
Write Precomp
aboveTG43.

6. E11 to E12

GND
OPEN

7. E13 to E14

N.A.

8. E17/E19 to E18

E18 to E19
E18 to E17

I

9. E20 to E21

N .A.

t2~

10. E22 to E23

N.A.

11. E24 to E25

N.A.

-I

~I

if

I
I
I
I

I

= 40msec MOM delay.
= 1 sec MOM delay.

I

j.-t1

=

t1
t2
t1 + t2

=
=

E5 to E7
Normal READY
latch.
E6 to E7
If FRDY line available from Floppy drive.

I

RDATA

·1--

=

5. E5/E7 to E6

200 NSEC NOM

t3

=

=

To complete the adjustment, monitor RCLK and
RDATA inputs to the WD1010 (U19-39,37 respectively)
and fine tune variable capacitor C19 until the rising
edge of RDATA is exactly centered in either Half
Phase or RCLK.

1--

WD2797 ADJUSTMENT PROCEDURE

= t3

9·1

= 10 MHz.
= 20 MHz.

APPENDIX A
DISK DRIVER EXAMPLES
A.1

INTRODUCTION

The two sample disk drivers presented in this appendix are intended to serve as a catalyst to help the user set up
his own first driver. Note that although the drivers shown are simplistic, they represent everything needed to
satisfy WD1002-05 operating requirements. Retry software is not included in the examples because all
necessary retries are performed by the WD1 002-05.
The first example shown is a programmed 1/0 and polled status driver using the 8-bit Intel 8085 microprocessor.
The second example is of a programmed 1/0 and interrupt driven driver and is written for the 16-bit Western
Digital WD16 microprocessor.
A.2

POLLED STATUS DRIVER

;***********************************************;

WD1002·05 Hard Disk Controller Driver
Example for 8085 Microprocessor
with programmed 1/0 and polled status
;***********************************************;
;This driver is intended to demonstrate one simple approach to writing a
;driver for the WD1002-05. It assumes that the WD1002-05 is interfaced using
;programmed 1/0 without interrupts.
;The specifications of the imaginary demonstration drive are:
;Sector size:
;Sectors per track:
;Surfaces per drive:
;Cylinders per drive:
;Stepping rate:
STRATE = 2

256 bytes
33
4 (two platters)
512
2 milliseconds
;Define stepping rate for assembler

;As the WD1002 is being allowed to map around the bad blocks, one
;sector per track has to be sacrificed. This brings down the logical
;sector per track count to 32.
;Experienced systems programmers will note that the driver is not
;being made as flexible as it should be. As WD1002-05 compatible drives will
;be introduced in the future, and present manufacturers will be
;increasing the density of their current drives, the driver written
;should be built with sufficient equates and conditional
;assemblies.
;The imaginary operating system of this example can access up to 65536
;Iogical records of 256 bytes each. It has three types of calls:
;initialize, read, and write. Three numerical parameters are passed
;in the following registers:
Drive number
Logical record number
Transfer address

C
DE
HL

;Upon completion of all commands, the carry bit of the 8085 will be
;reset if the operation terminated properly and set if there was an
;error. If there was an error during read or write, the error-handling
;routine will decode it and print it out on the user console.

A-1

;************************;
EaUATES

; * * * * * * * * * * * * * * * * * * * * * * * *;
;* * *

Port Definition * * *
BASADD
DATA
= BASADD
ERROR
= BASADD+1
BASADD+1
WPC
BASADD+2
SECNT
BASADD+3
SECNO
BASADD+4
CYLLO
BASADD+5
CYLHI
BASADD+6
SOH
BASADD+ 7
STATUS
BASADD+ 7
COMND

= oca

;Base address of WD1002-05
;Data register
;Error Register
;Write Precomp
;Sector Cou nt
;Sector Number
;Cylinder Number
;Cylinder High
;Size/Head/Drive
;Status register
;Command register

=
=
=
=
=
=
=
=

; * * * Command Definition

=
=
=

REST
READ
WRITE
A.2.1

***
;Restore command
;Read command (programmed 110 mode)
;Write command

10
20
30

INITIALIZATION

; * * * * * * * * * * * * * * * * * * * * * * *;
INITIALIZE

; * * * * * * * * * * * * * * * * * * * * * * *;
;This routine is called once whenever the system is powered up or reset.
;It sets the stepping rate and restores the head on the selected drive.
RESTOR:
RSWAIT:

A.2.2

CALL
MVI
OUT
IN
ANA
JM
RAR
RET

UPTASK
A,REST + 
COMND
STATUS
A
RSWAIT

;Select drive, don't care about record
;Get stepping rate and restore
;Output command to WD1002-05
;Wait 'till restore done
;by updating sign flag in 8085
;and wait 'till bit 7 (Busy) goes low
;Put error bit in carry
;Return to operating system

READ SECTOR

; * * * * * * * * * * * * * * * * * * * * * * *;
READ

; * * * * * * * * * * * * * * * * * * * * * * *;
;This is the read routine for the imaginary operating system.
READIT:

CALL
MVI
OUT

UPTASK
A, READ
COMND

;Update WD1002-05 task file
;Get READ command
;Output command to WD1002-05

;Wait for WD1 002-05 to read ina sector
RWAIT:

IN
ANA
JM

STATUS
A
RWAIT

;Check Busy bit
;by updating sign flag in 8085
;and wait 'till bit 7 goes low

A·2

;Transfer sector from WD1oo2-05 to system memory
;(Transfer address in HL)
READLP:

A_2.3

MVI
IN
MOV
INX
DCR
JNZ
IN
JMP

B,O
DATA
M,A
H
B
READLP
STATUS
DONE

;Init byte counter to 256 bytes
;Get a byte of data from WD1oo2-05
;Move it to memory
;Increment memory pointer
;Decrement byte counter and continue
;if we haven't transferred 256 yet
;Re-read status for errors
;Now check the completion status

WRITE SECTOR

; * * * * * * * * * * * * * * * * * * * * * * * *;
WRITE

;************************;
;This is the write routine for the driver
WRITIT:

CALL
MVI
OUT

UPTASK
A,WRITE
COMND

;Update WD1oo2-05 task file
;Get WRITE command
;Output command to WD1 002-05

;Transfer sector from system memory to WD1oo2-05
;(Transfer address in HL)
WRITLP:

MVI
MOV
OUT
INX
DCR
JNZ

B,O
A,M
DATA
H
B
WRITLP

;Init byte counter to 256 bytes
;Get a byte of data from memory
;Move it to WD1002-05
;Increment memory pointer
;Decrement byte counter and continue
;if we haven't transferred 256 yet

;Wait for WD1 002-05 to write the sector
WWAIT:

IN
ANA
JM

STATUS
A
WWAIT

;Check Busy bit
;by updating sign flag in 8085
;and wait 'till bit 7 goes low

; * * * * * * * * * * * * * * * * * * * * * * *;
DONE

; * * * * * * * * * * * * * * * * * * * * * * *;
;Both READ and WRITE commands finish here to check for errors
DONE:

RAR
RNC
IN

ERROR

;«
STC
RET

;Rotate Error bit to carry
;and return to OS if no error
;Get WD1oo2-05 error code
;Set carry to flag an error
;and return to OS with error

A-3

A.2.4

TASK FILE UPDATING

;********************************;
UPiASK SUBROUiiNE
;********************************;
;This subroutine sets up the task file registers
;Sector number
UPTASK:

MOV
ANI
OUT

A,E

31.
SECNO

;Get lower 8 bits of record number
;Mask off lower 5 bits (bits 0-4)
;and send to sector number register

;Size/Drive/Head
MOV
RLC
RLC
RLC
ANI
MOV
MOV
ADD
ADD
ADD
ORA
ORI
OUT

A

;Get lower 8 bits agai n
;Rotate remaining 3 bits
;to get an effective right shift of 5
;Mask off next two bits (5-6)
;to make head number
;and store it away momentari Iy
;Get drive number
;and left shift it by 3

A
A
B
80
SDH

;OR in head number and
;OR in ECC flag and size field
;send it to Size/Drive/Head register

A,E

3.
B,A
A,C

;Cylinder low
MOV
RAL
MOV
RAL
OUT

A,E
A,D
CYLLO

;Get last bit of lower record number
;and put it in carry
;Get upper half of record number
;Left shift it and merge in carry
;Send it to lower cylinder register

;Cylinder high
MVI
RAL
OUT
RET
END
A.3

A,O
CYLHI

;Clear all bits except for the
;the least significant and send
;to the upper cylinder register

INTERRUPT DRIVEN DRIVER

;***********************************************;
WD1002·05 Hard Disk Controller Driver
Example for the Western Digital
WD16 Microprocessor
using interrupts and programmed I/O

;***********************************************;
;This example driver demonstrates the type of driver that would be
;used in a multitasking environment. Like the 8085 driver, it uses pro-

A-4

;grammed 1/0 for data transfers. Unlike the last driver, this one
;supports interrupts.
;This new driver uses the same drive used in the 8085 example.
;Like the last driver, this one can access up to 65536 logical records
;of 256 bytes each. It still has three types of calls: initialize, read,
;and write. Three numerical parameters are passed in the following
;registers:
Drive number
Logical record number
Transfer address

R1
R2
R3

;Upon completion of all commands, the carry bit of the WD16 will be
;reset if the operation terminated properly and set if there was an
;error. If there was an error during read or write, the error-handling
;routine will decode it and print it out on the user console.

; * * * * * * * * * * * * * * * * * * * * * * * *;
EQUATES

; * * * * * * * * * * * * * * * * * * * * * * * *;
;* * *

Port Definition

BASADD
DATA
ERROR
WPC
SECNT
SECNO
CYLLO
CYLHI
SOH
STATUS
COMND

;***
REST
READ
WRITE

=
=
=
=
=
=
=
=
=
=
=

***

OFFD8
BASADD
BASADD+ 1
BASADD+1
BASADD+2
BASADD+3
BASADD+4
BASADD+5
BASADD+6
BASADD+ 7
BASADD+ 7

Command Definition

=
=
=

;Base address of WD1002-05
;Data register
;Error Register
;Write Precomp
;Sector Count
;Sector Number
;Cylinder Number
;Cylinder High
;Size/HeadlDrive
;Status register
;Command register

***
;Restore command
;Read command (programmed 1/0 mode)
;Write command

10
20
30

; * * * Drive stepping rate
STRATE
2

***

=

A.3.1

;Drive stepping rate

INITIALIZATION

; * * * * * * * * * * * * * * * * * * * * * * *;
INITIALIZE

; * * * * * * * * * * * * * * * * * * * * * * *;
;This routine is called once whenever the system is powered up or reset.
;It sets the stepping rate and restores the head on the selected drive.

RESTOR:
CAll
UPTASK
;Setect drive, don't care about record
;As a multitasking computer is being interfaced with,
;the calling job should be put to sleep while the restore is being done.
;The SLEEP instruction in this listing is actually a monitor call to

A-5

;the operating system which does the dirty work. Once the WD1002-05 has
;completed the restore, it will interrupt the CPU and the interrupt
;routine will wake the job. Putting the job to sleep will allow other
·t!lC!VC!
,1.II.AV.'\....., tn
.. ""

IICO
U""""'"

tho
"'I'" r.DII
"' • ...., \Alhilo
•••••• ...., tho
"'II....., roctnro
• .....,...., ... ....,."" ic
• ...., in
.,. nrnnrocc
___ •
,..,.._~.

LOCK
•• ,,' I

#REST + ,@#COMND

SLEEP
MOVB
RORB
RTN

10WAIT
@#STATUS,RO
RO

IVIVV

A.3.2

;Disable interrupts until sleep
;Get stepping iate and i6StOi6
;and output command to WD1 002-05
;Put job in an 1/0 wait state
;Get status register
;Put error bit in carry
;Return to operating system

READ SECTOR

; * * * * * * * * * * * * * * * * * * * * * * *;
READ

; * * * * * * * * * * * * * * * * * * * * * * *;
;This is the read routine for the imaginary operating system.
READIT:

CALL
LOCK
MOVB

UPTASK
#READ,@#COMND

;Update WD1002-05 task file
;Disable interrupts 'til we go to sleep
;Issue READ command to WD1002-05

;Wait forWD1002-05 to read in a sector
10WAIT

SLEEP

;While waiting, go into 1/0 wait state

;After wakeup, transfer sector from WD1002-05 to system memory
;(Transfer address in R3, WD1002-05 data register address in R4)
MOV

#256.,RO

;Init byte counter to 256 bytes

;The following instruction, MABB (Move Address to Block of Bytes), does
;a block move by reading the data pOinted to by R4 (WD1002-05 data
;register) and puts them in a block of memory pOinted to by R3. RO bytes
;are moved.
R4,R3
DONE

MABB
BR

A.3.3

;Move data from WD1002-05 to memory
;Now check the completion status

WRITE SECTOR

; * * * * * * * * * * * * * * * * * * * * * * * *;
WRITE

; * * * * * * * * * * * * * * * * * * * * * * * *;
;This is the write routine for the imaginary driver
WRITIT:

CALL
MOVB

UPTASK
#WRITE,@#COMND

;Update WD1002-05 task file
;Issue WRITE command to WD1002-05

;Transfer sector from system memory to WD1002-05
;(Transfer address in R3, WD1002-05 data register address in R4)
MOV

#256.-1.,RO

;Init byte counter to 256-1 bytes

;The following instruction, MBBA (Move Block of Bytes to Address) is the
;converse of the MABB instruction, above. This time the block of memory
;pointed to by R3 will be moved to the WD1002-05 data register (pointed to
;by R4). RO bytes will be moved.

A-6

MBBA
LOCK
MOVB

R3,R4
@R3,@R4

;Move most of the data
;Disable ints. 'till last byte xferred
;Write last byte of data to WD1 002-05

;Wait for WD1 002-05 to write the sector
SLEEP

10WAIT

;Wait in I/O wait state

; * * * * * * * * * * * * * * * * * * * * * * *;
DONE
; * * * * * * * * * * * * * * * * * * * * * * *;

;Both READ and WRITE commands finish here to check for errors
DONE:

MOVB
RORB
BCC
MOVB

@#STATUS,RO
RO
DONEOK
@#ERROR,RO

;Get status byte from WD1002-05
;Rotate Error bit to carry
;and return to OS if no error
;Get WD1oo2-05 error code

;«
DONEOK:
A.3.4

LCC
RTN

CARRY

;Set carry to flag an error
;and return to OS with error

TASK FILE UPDATING

;********************************;
UPTASK SUBROUTINE
;********************************;

;This subroutine sets up the task file registers
;Sector number
UPTASK:

MOV
AND
MOV
MOVB

R2,RO
#31.,RO
#SECNO,R4
RO,(R4)+

;Get record number
;Mask off lower 5 bits (bits 0·4)
;Index WD1002-05 sector number register
;and send to sector number register
;and increment R4 to pOint to WD1002-05
;Cylinder Low register

;Size/Drive/Head
;(The following instruction does a right arithmetic shift 5 times)
SSRA
R2,5
;Discard SECNO bits from record number
MOV
R2,RO
;Get remaining record number bits
#3.,RO
;Mask off bits 5-6 to make head number
AND
;(The following instruction does a left arithmetic shift 3 times)
SSLA
OR
OR
MOVB

R1,3
R1,RO
#80,RO
RO,@#SDH

;Shift drive number into position
;OR drive number and head together
;OR ECC flag and sector size field
;send it to Size/Drive/Head register

R2,2
R2,(R4) +

;Discard HEAD bits from record number
;Send Cylinder Low to WD1002-05 and
;increment R4 to point to Cylinder High

;Cylinder Low
SSRA
MOVB

A-7

;Cylinder High
;(The following instruction SWAps the upper and lower Byte of a word)
SWAB
AND
MOVB
MOV
RTN

A.3.S

R2
#1,R2
R2,(R4)
#DATA,R4

;Get upper byte of cylinder
;Mask to ieast significant bit
;and send it to WD1002-05
;index \lVOloo2-05 Data Reg for RlVI/ ops

INTERRUPT SERVICE ROUTINE

;***************************************;
INTERRUPT SERVICE ROUTINE
;***************************************;
;This routine gets called whenever the WD1002-05 interrupts. All it does is
;read the status register of the WD1002-05 to clear INTRQ and revives the
;original calling job.
INTSER:

PUSH
MOVB
WAKEUP
POP

RTT

RO
@#STATUS,RO
10WAIT
RO

;Save this register
;Acknowledge the interrupt to WD1002-05
;Wake up job (from I/O wait state)
;Return from trap

END

A-8

APPENDIX B
INTERLEAVE CALCULATING
This BASIC program simplifies the process of generating interleave tables. It is written in a fairly standard
subset of the BASIC language and should run on many BASIC interpreters and compilers. Some implementations of BASIC may require the variable names to be converted to single letter names and the IF THEN ELSE
constructs may have to be rewritten.
The two questions at the beginning of the program should be answered in decimal. The interleave table is
printed in hexadecimal.

BASIC INTERLEAVE CALCULATING PROGRAM
10 PRINT "WD1oo2-05lnterleave calculating program"
20 PRINT
30 INPUT "Number of sectors? ";COUNT
40 INPUT "Interleave Factor? ";INTER
50 DIM HEX$(16),SECTOR(COUNl)
60 FOR INDEX = 1 TO 16
70 READ HEX$(INDEX)
80 NEXT
90 FOR INDEX = 1 TO COUNT
100 SECTOR(INDEX) = -1
110 NEXT
115 RES=O
120 FOR INDEX=OTO COUNT-1
130 IF RES>=COUNTTHEN RES= RES-COUNT
140 IF SECTOR(RES + 1) = - 1 TH EN SECTOR(RES + 1) = INDEX ELSE RES = RES + 1:G
150 RES= INTER+ RES
160 NEXT
170 PRINT
180 PRINT "Interleave table with";COUNT;"sectors and";INTER;": 1 interleave"
190 FOR INDEX = 1 TO COUNT
200 X = INT(SECTOR(INDEX)/16)
210 PRINT HEX$(X + 1);H EX$(SECTOR(I NDEX) - X*16 + 1),
220 NEXT
230 PRINT
240 DATA 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
250 END

B-1

APPENDIX C
CALCULATING SECTORS PER TRACK
Changes in WD1oo2-05 compatible disk drives consisting of higher bit-packing densities and higher accuracy
spindle motors will increase the amount of data that can be put on a track. This appendix will help users
determine the maximum number of sectors that can be recorded on their disk drive.
The unformatted byte capacity can be figured from this formula:
Capacity

=Bits per second I Revolutions per second x (1-Error) 18

Assuming a hypothetical drive (the same one as in the disk driver examples) with a data rate of 5M bits per
second, a revolution rate of 3600 RPM, and a spindle speed accuracy of 3%, these values applied to the
foregoing formula yield:

=5,OOO,OOO/60x(1 -

0.03)/8
To be on the safe side, a fractional value will always be rounded down. The unformatted capacity of this drive is
10,104 bytes. To figure the number of sectors per some number of bytes apply this formula:
10,104

Sectors

=Capacity I (Data field size + Gap3 + Check bytes + Other overhead)

Using 512 byte sectors with a Gap3 size of 30 bytes, running ECC results in:

17= 10,104/(512+30+4+41)
The BASIC program on the next page can be used to automate the sector-per-track calculations presented here.

BASIC SECTORS PER TRACK UTILITY
10 PRINT "WD1ooX Sectors per Track Calculating Utility"
20 PRINT
30 INPUT "Data rate of drive in bits per second: "; DATARATE
40 INPUT "Revolutions per minute: ";RPM
50 INPUT "Rotational speed error in percent: ";RERROR
60 CAPACITY INT(DATARATElRPM*60*(1 - RERRORl1oo)l8)
70 PRINT "Unformatted capacity is"CAPACITY"bytes."
80 PRINT
90 INPUT "Data field size in bytes (128, 256, etc.): ";SIZE
100 INPUT "Formatted with CRC or ECC: ";ECCMODE$
110 ECCMODE$ LEFT$(UCS(ECCMODE$),1)
120 IF ECCMODE$<>"E" AND ECCMODE$<>"C" THEN 100
130 IF ECCMODE$ "E" THEN CHECKBYTES 4 ELSE CHECKBYTES 2
140 IF SIZE>256 THEN GAP3 30 ELSE GAP3 15
150 SECTORS INT(CAPAC ITY/(SIZE + GAP3 + CHECKBYTES + 41))
160 PRINT "Formatted capacity is"; SECTORS*SIZE;"bytes per track using";
170 PRINTSECTORS;"sectors per track."
180 END

=

=

=

=

=

=
=

=

C-1

APPENDIX D
PROGRAMMER'S QUICK REFERENCE
0.1

TASK FILE

BSY

cso

A2

A1

AO

RE

WE

X

X

X

X

0
0
0
0
0
0
0
0

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Deselected
Data Register
Error Register
Sector Cou nt
Sector Number
Cylinder Low
Cylinder High* *
Size/Drive/Head
Status Register

Deselected
Data Register
Write Precomp*
Sector Count
Sector Number
Cyl i nder Low
Cylinder High**
Size/Drive/Head
Command Register

1
0
0
0
0
0
0
0
0

* Not used on floppies
* * LSB of cylinder high, if set to 1, permits a 48 t.p.i. floppy disk to be read on a 96 t.p.i. floppy disk system.
0.2

VALID COMMANDS

BITS
TYPE

COMMAND

I
I
I
II

Test
Restore
Seek
Read Sector
Write Sector
Format Track

III

III
0.3

765 4 3 210
1
0
0
0
0
0

o
0
1
0
0
1

0 1 0
0 1 r3
1 1 r3
1 0 D
1 1 o
0 1 o

000
r2 r1 ro
r2 r1 ro
M L 0
M L 0
0 0 0

SOH REGISTER FORMAT

Bit
Function

Bit

Bit

6

5

0
0
1
1

0
1
0
1

7

6

CRC/
ECC

5
Sec
Size

4

3

Drive
Select

Sector Size
256 Bytes
512 Bytes
1024 Bytes
128 Bytes

D·1

1

2

0

Head/Drive
Select

Bit

Bit

4

3

0
0
1
1

0
1
0
1

Drive Selected
(decoded & latched)
Drive Sel1
Drive Sel2
DriveSel3
Floppy Dr Sel

Bit

Bit

2

1

Bit
0

Head Selected
Hard Disk

o

o

o

Head 0
Hearl
1
..
Head 2
Head 3
Head 4
Head 5
Head 6
Head?

o-

D.4

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1

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1
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...:'_---

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0
1

0
0

1
1

0

1
1
1
1

0

0

0
1
1

0

1
1
1

STATUS AND ERROR REGISTER BITS

Bit

Status Register

Error Register

?

Busy
Drive Ready
Write Fault
Seek Complete
Data Request
Corrected
Not used
Error

Bad Block Detect
Uncorrectable Error

6
5
4
3
2
1
0

-

10 Not Found

-

Aborted Command
TROOO Error
DAM not found

D-2

Floppy Drive &
Head Select
FD1FD1 FD2FD2FD3FD3FD4FD4-

HSO
HS1
HSO
HS1
HSO
HS1
HSO
HS1

APPENDIX E
LSI DATA SHEETS

(to be supplied)

E-1

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UNLEo:.S, OTHERWISE SPECIFIED.
5, ADD .I ... ~ C~P FROM ALL
TO GND.
J9 GND PINS: ~IIO,IZ.,I~,14115,1r...

C2l 106Ft
14

JI

12
QUTC

15

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10

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PHY:'ICALLY

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TO CHIP.

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(204) ORI
OUTA II

r...

DR UNaUTO 13

INB

(~rA+1

N.c.
PUP22.

i--------l

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2r.. L S.~2

~~-----.9~ IN~

tSV

c

+SY

I

IZ.

GND

I

L____ _

R5~

220n

CR+

R

DLYIN(~B41

CR"

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GND

~

GND PLANEC,

,...C_R-j&..1"'_4_14.6_ _...

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1.

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11'14148

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R

I

R52.

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C2S
3~.r

_____________________________

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(~·B~)

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I

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fRANCES

(At ·~t~~D

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SIGNATuFiE

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7

6

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IV

DESCAIPTICN

O"A."~, YRII\RT£. • ·1- 8.}

CK

",'''1

DATE

A

APPENDIX G
BILL OF MATERIALS

(to be supplied)

G-1

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