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----- --- ---- ---

------,-

Persona! Computer
Hardware Reference
Library

Technical
Reference

Revised Edition (March, 1986)
The following paragraph does not apply to the United Kingdom or any country
where such provisions are inconsistent with local law: INTERNATIONAL
BUSINESS MACHINES CORPORATION PROVIDES THIS PUBLICATION
"AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR
IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
PARTICULAR PURPOSE. Some states do not allow disclaimer of express or
implied warranties in certain transactions, therefore, this statement may not
apply to you.
This publication could include technical inaccuracies or typographical errors.
Changes are periodically made to the information herein; these changes will be
incorporated in new editions of the publication. IBM may make improvements
and/ or changes in the product(s) and/or the program(s) described in this
publication at any time.
It is possible that this publication may contain reference to, or information

about, IBM products (machines and programs), programming, or services that
are not announced in your country. Such references or information must not be
construed to mean that IBM intends to announce such IBM products,
programming, or services in your country.
Products are not stocked at the address below. Requests for copies of this
publication and for technical information about IBM Personal Computer
products should be made to your authorized IBM Personal Computer dealer,
IBM Product Center, or your IBM Marketing Representative.
The following paragraph applies only to the United States and Puerto Rico: A
Reader's Comment Form is provided at the back of this publication. If the form
has been removed, address comments to: IBM Corporation, Personal
Computer, P.O. Box 1328-C, Boca Raton, Florida 33429-1328. IBM may use
or distribute any of the information you supply in any way it believes
appropriate without incurring any obligations whatever.

© Copyright International Business Machines Corporation 1985, 1986

Federal Communications Commission
Radio Frequency Interference Statement
Warning: The equipment described herein has been certified to
comply with the limits for a Class B computing device, pursuant
to Subpart J of Part 15 of the FCC rules. Only peripherals
(computer input/output devices, terminals, printers, etc.) certified
to comply with the Class B limits may be attached to the
computer. Operation with non-certified peripherals is likely to
result in interference to radio and TV reception. If peripherals
not offered by IBM are used with the equipment, it is suggested to
use shielded grounded cables with in-line filters if necessary.
CAUTION
This product described herein is equipped with a grounded plug for

the user's safety. It is to be used in conjunction with a properly
grounded receptacle to avoid electrical shock.

iii

Notes:

iv

Preface

This manual describes the various units of the IBM PERSONAL
COMPUTER AT® and how they interact. It also has
information about the basic input/output system (BIOS) and
about programming support. Where timing considerations
between 6- and 8-MHz are different, the 8-MHz time is shown in
parentheses.
The information in this publication is for reference, and is
intended for hardware and program designers, programmers,
engineers, and anyone else who needs to understand the design
and operation of the IBM PERSONAL COMPUTER AT.
This manual consists of nine sections:
•
•
•
•
•
•
•

The first three sections describe the IBM PERSONAL
COMPUTER AT including hardware, charts, and register
information
Section 4 describes keyboard operation, the commands to and
from the system, and the various keyboard layouts
Section 5 contains information about the usage of BIOS and a
system BIOS listing
Section 6 contains instruction sets for the 80286
microprocessor and the 80287 math coprocessor
Section 7 provides information about characters, keystrokes,
and colors
Section 8 has general communications information
Section 9 contains information about the compatibility of the
IBM PERSONAL COMPUTER AT and the rest of the IBM
Personal Computer family.

A glossary and a bibliography are included.

v

Prerequisite Publications
Guide to Operations for the IBM PERSONAL COMPUTER AT

Suggested Reading
•

BASIC for the IBM Personal Computer

•

Disk Operating System (DOS)

•

Macro Assembler for the IBM Personal Computer

vi

Contents

SECTION 1. SYSTEM BOARD ..................... 1-1
Memory ..................................... 1-4
Microprocessor ................................ 1-4
System Performance ............................ 1-7
Direct Memory Access .......................... 1-9
System Interrupts ............................. 1-12
Hardware Interrupt Listing ................... 1-13
Interrupt Sharing ... . . . . . . . . . . . . . . . . . . . . . . .. 1-14
System Timers ............................... 1-22
System Clock ................................ 1-23
ROM Subsystem .............................. 1-23
RAM Subsystem .............................. 1-24
110 Channel ................................. 1-24
Connectors ............................... 1-25
I/O Channel Signal Description ............... 1-31
NMI and Coprocessor Controls ............... 1-38
Other Circuits ................................ 1-40
Speaker .................................. 1-40
RAM Jumpers ............................. 1-40
Display Switch ............................ 1-41
Variable Capacitor ......................... 1-41
Keyboard Controller ........................ 1-42
Real-Time Clock/CMOS RAM Information ..... 1-56
Specifications ................................ 1-69
System Unit .............................. 1-69
Connectors ............................... 1-71
Logic Diagrams - Type 1 .................... 1-76
Logic Diagrams - Type 2 .................... 1-98
2-1
SECTION 2. COPROCESSOR
Description .................................. . 2-3
Programming Interface ......................... . 2-3
Hardware Interface ............................ . 2-4

!

SECTION 3. POWER SUPPLY ..................... 3-1
Inputs ....................................... 3-3
Outputs ...................................... 3-3

vii

DC Output Protection ..........................
Output Voltage Sequencing ......................
No-Load Operation ............................
Power-Good Signal .............................
Connectors ...................................

3-4
3-4
3-4
3-4
3-7

SECTION 4. KEYBOARD ......................... 4-1
Introduction .................................. 4-5
84-Key Keyboard Description ................. 4-5
Power-On Routine .......................... 4-7
Commands from the System ................... 4-7
Commands to the System .................... 4-12
Keyboard Scan-Code Outputs ................ 4-13
Clock and Data Signals ...................... 4-14
Keyboard Encoding and Usage ................ 4-17
Keyboard Layouts ......................... 4-27
Specifications ............................. 4-34
Logic Diagram ............................ 4-35
1Ol/102-Key Keyboard Description .............. 4-36
Power-On Routine ......................... 4-39
Commands from the System .................. 4-40
Commands to the System .................... 4-47
Keyboard Scan Codes ....................... 4-49
Clock and Data Signals ...................... 4-61
Keyboard Encoding and Usage ................ 4-64
Keyboard Layouts ......................... 4-74
Specifications ............................. 4-81
Logic Diagram ............................ 4-82
SECTION 5. SYSTEM BIOS ....................... 5-1
System BIOS Usage ............................ 5-3
Quick Reference .............................. 5-14
SECTION 6. INSTRUCTION SET ................... 6-1
80286 Instruction Set ........................... 6-3
Data Transfer .............................. 6-3
Arithmetic ................................. 6-6
Logic ..................................... 6-9
String Manipulation ........................ 6-11

~~~~~;o;r~~~~~l':::::::::::::::::::::::::: ~~~~ ~
Protection Control ......................... 6-18
80287 Coprocessor Instruction Set ................ 6-22

viii

Data Transfer .............................
Comparison ..............................
Constants ................................
Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Transcendental ............................

6-22
6-23
6-24
6-25
6-26

SECTION 7. CHARACTERS, KEYSTROKES, AND
COLORS ...................................... 7-1
Character Codes ............................... 7-3
Quick Reference .............................. 7-14
SECTION 8. COMMUNICATIONS ................. 8-1
Hardware .................................... 8-3
Establishing a Communications Link ............... 8-5
SECTION 9. IBM PERSONAL COMPUTER
COMPATIBILITY ............................... 9-1
Hardware Considerations ........................ 9-3
System Board .............................. 9-3
Fixed Disk Drive ............................ 9-5
Diskette Drive Compatibility .................. 9-5
Copy Protection ............................ 9-5
Application Guidelines .......................... 9-7
High-Level Language Considerations ............ 9-7
Assembler Language Programming Considerations . 9-8
Multitasking Provisions ...................... 9-16
Machine-Sensitive Code ..................... 9-19
Glossary

..................................

Bibliography .............................

Glossary -1

Bibliography -1

Index ...................•.................... Index-1

ix

Notes:

x

INDEX TAB LISTING
Section 1: System Board ............................... .

Section 2: Coprocessor ................................ .

Section 3: Power Supply ............................... .

Section 4: Keyboard .................................. .

Section 5: System BIOS ............................... .

Section 6: Instruction Set

.. . .. . ... . . .. . . . . . . . . ... . . ... .
~

Notes:

xii

Section 7: Characters, Keystrokes, and Colors .............. .

Section 8: Communications ............................ .

Section 9: Compatibility ............................... .

Glossary ........................................... .

Bibliography ........................................ .

Index

...............................................

xiii

System Block Diagram
System Unit
Power Supply
115/230

System Board
80286(-6 or -8)
Microprocessor

80287
Coprocessor

Osc i 11 ator

16 Interrupt
Levels

ROM

Speaker
Connector

Speaker

7 Channel
DMA

RAM

Keyboard
Contro ller

Keyboard

CMOS

Real-Time
Clock

Battery
Connector

Battery

1/0

Channel

00000000
DDDDD D

xiv

Fixed
Disk
Dr i ves

Diskette
Drives

Fixed Disk and
Diskette Adapter

SECTION 1. SYSTEM BOARD

Memory ..................................... 1-4
Microprocessor ................................ 1-4
Real Address Mode ...................... 1-4
Protected (Virtual Address) Mode ........... 1-5
System Performance ............................ 1-7
Direct Memory Access .......................... 1-9
System Interrupts ............................. 1-12
Hardware Interrupt Listing ................... 1-13
Interrupt Sharing ..... . . . . . . . . . . . . . . . . . . . . .. 1-14
Design Overview ........................ 1-14
Program Support ........................ 1-15
Precautions ............................ 1-17
Examples ........................... ... 1-18
System Timers ............................... 1-22
System Clock ................................ 1-23
ROM Subsystem .............................. 1-23
RAM Subsystem .............................. 1-24
I/O Channel ..................... "........... 1-24
Connectors ............................... 1-25
II0 Channel Signal Description ............... 1-31
NMI and Coprocessor Controls ............... 1-38
Other Circuits ................................ 1-40
Speaker .................................. 1-40
RAM Jumpers ............................. 1-40
Display Switch ............................ 1-41
Variable Capacitor ......................... 1-41
Keyboard Controller ........................ 1-42
Keyboard Controller Initialization .......... 1-42
Receiving Data from the Keyboard . . . . . . . . .. 1-43
Scan Code Translation ................... 1-43
Sending Data to the Keyboard ............. 1-48
Inhibit ................................ 1-48
Keyboard Controller System Interface ....... 1-48
Status Register ......................... 1-49
Status-Register Bit Definition .............. 1-49
Output Buffer .......................... 1-51
Input Buffer ........................... 1-51

System Board

1-1

Commands (I/O Address Hex 64) ..........
I/O Ports .............................
Real-Time Clock/CMOS RAM Information .....
Real-Time Clock Information ..............
CMOS RAM Configuration Information .....
1/0 Operations .........................
Specifications ................................
System Unit ..............................
Size ..................................
Weight ...............................
Power Cables ..........................
Environment ...........................
Heat Output ...........................
Noise Level ............................
Electrical ..............................
Connectors ...............................
Logic Diagrams - Type 1 ....................
Logic Diagrams - Type 2 ....................

1-2

System Board

1-51
1-54
1-56
1-57
1-59
1-68
1-69
1-69
1-69
1-69
1-69
1-69
1-70
1-70
1-70
1-71
1-76
1-98

The type 1 system board is approximately 30.5 by 35 centimeters
(12 by 13.8 inches). The type 2 system board is approximately
23.8 by 35 centimeters (9.3 by 13.8 inches). Both types of
system boards use very large scale integration (VLSI) technology
and have the following components:
•

Intel 80286 Microprocessor

•

System support function:
Seven-Channel Direct Memory Access (DMA)
Sixteen-level interrupt
Three programmable timers
System clock

•

64K read-only memory (ROM) subsystem, expandable to
128K

•

A 512K random-access memory (RAM) Subsystem

•

Eight input/output (I/O) slots:
Six with a 36-pin and a 62-pin card-edge socket
Two with only the 62-pin card-edge socket

,

"'

•

Speaker attachment

•

Keyboard attachment

•

Complementary metal oxide semiconductor (CMOS)
memory RAM to maintain system configuration

•

Real-Time Clock

•

Battery backup for CMOS configuration table and
Real-Time Clock

System Board

1-3

Memory
The type 1 system board has four banks of memory sockets, each
supporting 9 128K-by-l-bit modules for a total memory size of
512K, with parity checking.
The type 2 system board has two banks of memory sockets, each
supporting 9 256K-by-l-bit modules for a total memory size of
512K, with parity checking.

Microprocessor
The Intel 80286 microprocessor has a 24-bit address, 16-bit
memory interface 1, an extensive instruction set, DMA and
interrupt support capabilities, a hardware fixed-point multiply and
divide, integrated memory management, four-level memory
protection, IG (1,073,741,824 bytes) of virtual address space for
each task, and two operating modes: the 8086-compatible real
address mode and the protected or virtual address mode. More
detailed descriptions of the microprocessor may be found in the
publications listed in the Bibliography of this manual.

Real Address Mode
In the real address mode, the microprocessor's physical memory is
a contiguous array of up to one megabyte. The microprocessor
addresses memory by generating 20-bit physical addresses.
The selector portion of the pointer is interpreted as the upper 16
bits of a 20-bit segment address. The lower 4 bits of the 20-bit
segment address are always zero. Therefore, segment addresses
begin on multiples of 16 bytes.

In this manual, the tenn interface refers to a device that carries signals between
functional units.

1-4

System Board

All segments in the real address mode are 64K in size and may be
read, written, or executed. An exception or interrupt can occur if
data operands or instructions attempt to wrap around the end of a
segment. For example, a word with its low-order byte at offset
FFFF and its high-order byte at 0000. If, in the real address
mode, the information contained in the segment does not use the
full 64K, the unused end of the segment may be overlayed by
another segment to reduce physical memory requirements.

Protected (Virtual Address) Mode
The protected mode offers extended physical and virtual memory
address space, memory protection mechanisms, and new
operations to support operating systems and virtual memory.
Note: See "BIOS Programming Hints" in Section 5 for
special cautions while operating in the protected mode.
The protected mode provides a 1G virtual address space for each
task mapped into a 16M physical address space. The virtual
address space may be larger than the physical address space,
because any use of an address that does not map to a physical
memory location will cause a restartable exception.
As in the real address mode, the protected mode uses 32-bit
pointers, consisting of 16-bit selector and offset components.
The selector, however, specifies an index into a memory resident
table rather than the upper 16 bits of a real memory address. The
24-bit base address of the desired segment is obtained from the
tables in memory. The 16-bit offset is added to the segment base
address to form the physical address. The microprocessor
automatically refers to the tables whenever a segment register is
loaded with a selector. All instructions that load a segment
register will refer to the memory-based tables without additional
program support. The memory-based tables contain 8-byte
values called descriptors.

System Board

1-5

Following is a block diagram of the system board.

1-6

System Board

System Performance
Where timing considerations between 6- and
8-MHz are different, the 8-MHz time is shown in
parentheses.

Note:

The 80286 microprocessor operates at 6 MHz (8 MHz), resulting
in a clock cycle time of 167 nanoseconds (125 nanoseconds).
A bus cycle requires 3 clock cycles (which includes 1 wait state)
so that a 500-nanosecond (375-nanosecond), 16-bit,
microprocessor cycle time is achieved. Eight-bit bus operations
to 8-bit devices take 6 clock cycles (which include 4 wait states),
resulting in a 1000-nanosecond (750-nanosecond)
microprocessor cycle. Sixteen-bit bus operations to 8-bit devices
take 12 clock cycles (which include 10 wait states) resulting in a
2-microsecond (1. 5-microsecond) microprocessor cycle.
The refresh controller steps one refresh address every 15
microseconds. Each refresh cycle requires 8 clock cycles to
refresh all of the system's dynamic memory; 256 refresh cycles
are required every 4 milliseconds but the system hardware
refreshes every 3.89ms. The following formula determines the
percentage of bandwidth used for refresh for the 6 MHz clock.

% Bandwidth used
for Refresh

8 cycles X 256

2048

3.89ms/167ns

23293

= -------------- = ----- = 8.7%

The following formula determines the percentage of bandwidth
used for refresh for the 8 MHz clock.

% Band\,!.i dth used
for Refresh

8 cycles X 256
-------------3.89ms/125ns

2048
31120

= 6.5%

The DMA controller operates at 3 MHz (4 MHz), which results
in a clock cycle time of 333 nanoseconds (250 nanoseconds). All
DMA data-transfer bus cycles are 5 clock cycles or 1.66
microseconds (1.25 microseconds). Cycles spent in the transfer
of bus control are not included.

System Board

1-7

DMA channels 0, 1, 2, and 3 are used for 8-bit data transfers, and
channels 5, 6, and 7 process 16-bit transfers. Channel 4 is used
to cascade channels 0 through 3 to the microprocessor.
The following figure is a system memory map.
Address

Name

Function

000000 to
07FFFF

S12K system
board

System board memory

080000 to
09FFFF

128K

I/O channel memory - IBM Personal
Computer AT 128K Memory Expansion
Option or 128/640K Memory Card

OAOOOO to
OBFFFF

128K video
RAM

Reserved for graphics display buffer

OCOOOO to
ODFFFF

128K I/O
expansion ROM

Reserved for ROM on I/O adapters

OEOOOO to
OEFFFF

64K reserved
on system board

Duplicated code assignment at
address FEOOOO

OFOOOO to
OFFFFF

64K ROM on the
system board

Duplicated code assignment at
address FFOOOO

100000 to
FDFFFF

Maximum
memory 15M

I/O channel memory - S12K to 15M
installed on memory expansion options

FEOOOO to
FEFFFF

64K reserved
on system board

Dupl icated code assignment at
address OEOOOO

FFOOOO to
FFFFFF

64K ROM on the
system board

Dupl icated code assignment at
address OFOOOO

System Memory Map

1-8

System Board

Direct Memory Access
The system supports seven direct memory access (DMA)
channels. Two Intel 8237 A-5 DMA Controller chips are used,
with four channels for each chip. The DMA channels are
assigned as follows:
Controller 1
Ch 0 - Reserved
Ch 1 - SOLC
Ch 2 - Diskette ( IBM
Personal Computer)
Ch 3 - Reserved

Controller 2
Ch 4 - Cascade for Ctlr 1
Ch 5 - Reserved
Ch 6 - Reserved
Ch 7 - Reserved

DMA Channels

DMA controller 1 contains channels D through 3. These channels
support 8-bit data transfers between 8-bit I/O adapters and 8- or
16-bit system memory. Each channel can transfer data
throughout the 16M system-address space in 64K blocks.
The following figures show address generation for the DMA
channels.
Source

DMA Page Registers

Controller

Address

A23<---------->A16

A15<---------->AO

Address Generation for DMA Channels 0 through 3

Note: The addressing signal, I byte high enable I (BHE), is
generated by inverting address line AD.

System Board

1-9

DMA controller 2 contains channels 4 through 7. Channel 4 is
used to cascade channels 0 through 3 to the microprocessor.
Channels 5, 6, and 7 support 16-bit data transfers between 16-bit
I/O adapters and 16-bit system memory. These DMA channels
can transfer data throughout the 16M system-address space in
128K blocks. Channels 5, 6, and 7 cannot transfer data on
odd-byte boundaries.
Source

DMA Page Registers

Controller

Address

A23<---------->AI7

AI6<---------->Al

Address Generation for DMA Channels 5 through 7

Note: The addressing signals, BHE and AO, are forced to a
10gicalO.
The following figure shows the addresses for the page register.
Page Register
DMA Channel
DMA Channel
DMA Channel
DMA Channel
DMA Channel
DMA Channel
DMA Channel
Refresh

0
1
2
3
5
6
7

1/0 Hex Address

0087
0083
0081
0082
008B
0089
008A
008F

Page Register Addresses

Addresses for all DMA channels do not increase or decrease
through page boundaries (64K for channels 0 through 3, and
128K for channels 5 through 7).
DMA channels 5 through 7 perform 16-bit data transfers. Access
can be gained only to 16-bit devices (I/O or memory) during the
DMA cycles of channels 5 through 7. Access to the DMA
controller, which controls these channels, is through I/O
addresses hex OCO through ODF.

1-10

System Board

The DMA controller command code addresses follow.
Hex
Address

Register Function

OCO
OC2
oc4
OC6
oc8
OCA
OCC
OCE

CHO
CHO
CHI
CHI
CH2
CH2
CH3
CH3

000
002
004
006
008
ODA
ODC
ODE

Read Status Register/Write Command Register
Write Request Register
Write Single Mask Register Bit
Write Mode Register
Clear Byte Pointer Flip-Flop
Read Temporary Register/Write Master Clear
Clear Mask Register
Write All Mask Register Bits

base
base
base
base
base
base
base
base

and
and
and
and
and
and
and
and

current
current
current
current
current
current
current
current

address
word count
address
word count
address
word count
address
word count

DMA Controller

All DMA memory transfers made with channels 5 through 7 must
occur on even-byte boundaries. When the base address for these
channels is programmed, the real address divided by 2 is the data
written to the base address register. Also, when the base word
count for channels 5 through 7 is programmed, the count is the
number of 16-bit words to be transferred. Therefore, DMA
channels 5 through 7 can transfer 65,536 words, or 128Kb
maximum, for any selected page of memory. These DMA
channels divide the 16M memory space into 128K pages. When
the DMA page registers for channels 5 through 7 are
programmed, data bits D7 through D 1 contain the high-order
seven address bits (A23 through A17) of the desired memory
space. Data bit DO of the page registers for channels 5 through 7
is not used in the generation of the DMA memory address.
At power-on time, all internal locations, especially the mode
registers, should be loaded with some valid value. This is done
even if some channels are unused.

System Board

1-11

System Interrupts
The 80286 microprocessor's non-maskable interrupt (NMI) and
two 8259A Controller chips provide 16 levels of system
interrupts.
Note: Any or all interrupts may be masked (including the
microprocessor's NMI).

1-12

System Board

Hardware Interrupt Listing
The following shows the interrupt-level assignments in decreasing
priority.
Level

Function

Microprocessor NMI

Parity or I/O Channel Check

Interrupt Controllers
CTRL 1
CTRL 2
IRQ 0
IRQ 1
IRQ 2 +-

Timer Output 0
Keyboard (Output Buffer Full)
Interrupt from CTRL 2
IRQ 8
IRQ 9

-

IRQ 3

IRQ 4

IRQ 5
IRQ 6
IRQ 7

*
**

***

The
The
The
3

IRQ
IRQ
IRQ
IRQ
IRQ
IRQ

10
11
12
13
14
15

Realtime Clock Interrupt
Software Redirected to INT OAH
PC Network *
PC Network(Alt.} *
Reserved
Reserved
Reserved
Coprocessor
Fixed Disk Controller
Reserved
Serial Port 2
BSC
BSC (Alt.)
Cluster (Primary)
PC Network *
PC Network (Alt.) *
SDLC
Serial Port 1
BSC
BSC (Alt.)
SDLC
Parallel Port 2
Diskette Controller
Fixed Disk and Diskette Drive
Parallel Port 1
Data Aquisition and Control ***
GPIB *11
Cluster (Secondary)

PC Network is jumper selectable.
GPIB Adapter can be set to interrupts 2 through 7.
Data Acquisition Adapter can be set to interrupts
through 7. The default interrupt is 7.

Hardware Interrupt Listing

System Board

1-13

Interrupt Sharing
A definition for standardized hardware design has been
established that enables mUltiple adapters to share an interrupt
level. This section describes this design and discusses the
programming support required.
Note: Since interrupt routines do not exist in ROM for
protected mode operations, this design is intended to run
only in the microprocessor's real address mode.

Design Overview
Most interrupt-supporting adapters hold the 'interrupt request'
line (IRQ) at a low level and then drive the line high to cause an
interrupt. In contrast, the shared-interrupt hardware design
allows IRQ to float high through pull-up resistors on each
adapter. Each adapter on the line may cause an interrupt by
pulsing the line to a low level. The leading edge of the pulse arms
the 8259A Interrupt Controller; the trailing edge signals the
interrupt controller to cause the interrupt. The duration of this
pulse must be between 125 and 1,000 nanoseconds.
The adapters must have an 'interrupt' status bit (INT) and a
'interrupt enable' bit (ENA) that can be controlled and
monitored by its software.
Each adapter sharing an interrupt level must monitor the IRQ
line. When any adapter drives the line low, all other adapters on
that line must be prevented from issuing an interrupt request until
they are rearmed.
If an adapter's INT status bit is at a high level when the interrupt

sharing logic is rearmed, the adapter must reissue the interrupt.
This prevents lost interrupts if two adapters issue an interrupt at
the same time and an interrupt handler issues a Global Rearm
after servicing one of the adapters.

1-14

System Board

The following diagram is an example of the shared interrupt
hardware logic.
INT

Q

ENA

1-------1

+5

Q

-Q

>ClK

2.2K Ohms

-ClR
System

Cl o c k - - + - - - - ! - - - - - - - '
~--+-

IRQ

+5
Q

'------I>ClK
-Q
-ClR
- Global

Rearm----+-------'

Shared Interrupt Logic Diagram

Program Support
During multitasking, tasks are constantly being activated and
deactivated in no particular order. The interrupt-sharing program
support described in this section provides for an orderly means to:
•

Link a task's interrupt handler to a chain of interrupt
handlers

•

Share the interrupt level while the task is active

•

Unlink the interrupt handler from the chain when the task is
deactivated.

Linking to a Chain
Each newly activated task replaces the interrupt vector in low
memory with a pointer to its own interrupt handler. The old
interrupt vector is used as a forward pointer (FPTR) and is stored
at a fixed offset from the new task's interrupt handler.

System Board

1-15

Sharing the Interrupt Level
When the new task's handler gains control as a result of an
interrupt, the handler reads the contents of the adapter's interrupt
status register to determine if its adapter caused the interrupt. If
it did, the handler services the interrupt, disables the interrupts
(eLI), issues a non-specific End of Interrupt (EOI), and then, to
rearm the interrupt hardware, writes to address 02FX, where X
corresponds to interrupt levels 3 through 7, and 9 (IRQ9 is
02F2). A write to address 06FX, where X may be 2 through 7, is
required for interrupt levels 10 through 15, respectively. Each
adapter in the chain decodes the address which results in a Global
Rearm. An adapter is required to decode the least significant 11
bits for this Global Rearm command. The handler then issues a
Return From Interrupt (IRET).
If its adapter did not cause the interrupt, the handler passes

control to the next interrupt handler in the chain.

Unlinking from the Chain
To unlink from the chain, a task must first locate its handler's
position within the chain. By starting at the interrupt vector in
low memory, and using the offset of each handler's FPTR to find
the entry point of each handler, the chain can be methodically
searched until the task finds its own handler. The FPTR of the
previous handler in the chain is replaced by the task's FPTR, thus
removing the handler from the chain.

Error llecovery
Should the unlinking routine discover that the interrupt chain has
been corrupted (an interrupt handler is linked but does not have a
valid SIGNATURE), an unlinking error-recovery procedure must
be in place. Each application can incorporate its own unlinking
error procedure into the unlinking routine. One application may
choose to display an error message requiring the operator to
either correct the situation or power down the system. Another
application may choose an error recovery procedure that restores
the original interrupt vector in low memory, and bypasses the
corrupt portion of the interrupt chain. This error recovery

1-16

System Board

procedure may not be suitable when adapters that are being
serviced by the corrupt handler are actively generating interrupts,
since unserviced interrupts lock up that interrupt level.

ROS Considerations
Adapters with their handlers residing in ROS may choose to
implement chaining by storing the 4 byte FPTR (plus the FIRST
flag if it is sharing interrupt 7 or 15) in on-adapter latches or
ports. Adapter ROS without this feature must first test to see
that it is the first in the chain. If it is the first in the chain, the
adapter can complete the link; if not, the adapter must exit its
routine without linking.

Precautions
The following precautions must be taken when designing
hardware or programs using shared interrupts:
•

Hardware designers should ensure the adapters:
Do not power up with the ENA line active or an
interrupt pending.
Do not generate interrupts that are not serviced by a
handler. Generating interrupts when a handler is not
active to service the adapter causes the interrupt level to
lock up. The design relies on the handler to clear its
adapter's interrupt and issue the Global Rearm.
Can be disabled so that they do not remain active after
their application has terminated.

•

Programmers should:
Ensure that their programs have a short routine that can
be executed with the AUTOEXEC.BAT to disable their
adapter's interrupts. This precaution ensures that the
adapters are deactivated if the user reboots the system.

System Board

1-17

Treat words as words, not bytes. Remember that data is
stored in memory using the Intel format (word 424B is
stored as 4B42).

Interrupt Chaining Structure
ENTRY,

JMP
FPTR
SIGNATURE

SHORT PAST
DD
q2qBH
DW

FLAGS
FIRST
JMP
RES BYTES

DB
EQU
SHORT
DB

-

PAST,

SOH
RESET
DUP 7

, Jump around structure
, Forward Pointer
, Used when unlinking to identify
, compatible interrupt handlers

, Flags
, Flag for
(0 )

, Future
, Actual

being first in chain

expansion

start of code

The interrupt chaining structure is a 16-byte format containing
FPTR, SIGNATURE, and RES BYTES. It begins at the third
byte from the interrupt handler'sentry point. The first
instruction of every handler is a short jump around the structure
to the start of the routine. Since the position of each interrupt
handler's chaining structure is known (except for the handlers on
adapter ROS), the FPTRs can be updated when unlinking.
The FIRST flag is used to determine the handler's position in the
chain when unlinking when sharing interrupts 7 and 15. The
RESET routine, an entry point for the operating system, must
disable the adapter's interrupt and RETURN FAR to the
operating system.

Note: All handlers designed for interrupt sharing must use
424B as the signature to avoid corrupting the chain.

Examples
In the following examples, notice that interrupts are disabled
before control is passed to the next handler on the chain. The
next handler receives control as if a hardware interrupt had
caused it to receive control. Also, notice that the interrupts are
disabled before the non-specific EOI is issued, and not reenabled
in the interrupt handler. This ensures that the IRET is executed
(at which point the flags are restored and the interrupts

1-18

System Board

reenabled) before another interrupt is serviced, protecting the
stack from excessive build up.

Example of an Interrupt Handler
YOUR_CARD

EQ.U

xxxx

Loeat i on of your card lsi nter rupt
control/status register

I SB

EQ.U

xx

Interrupt bit in your card's interrupt
control status register

REARM

EQ.U

2F7H

Global Rearm location for interrupt
level 7

67H

; Specific EOI for 8259's interrupt
level 7
Non-spec i f i c EO I
Location of 8259 operational control

SPC_EOI

EQ.U

EOI
OCR

EQ.U
EQ.U

20H
20H

IMR

EQ.U

2lH

register
Locat i on of 8259 interrupt mask

register
MYCSEG

SEGMENT
ASSUME
ENTRY
PROC
JMP
FPTR
DO
SIGNATURE OW

FLAGS
FIRST
JMP

DB
EQ.U
SHORT

RES BYTES DB
PAS!:
STI
PUSH
MOV
IN
TEST
JNZ
TEST
JNZ
POP
CL I
JMP

PARA
CS: MYCSEG ,OS: DSEG
FAR
SHORT PAST

o

424BH

o
80H
RESET
DUP 7 (0)

; Future expansion
; Actual start of handler code
; Save needed reg i sters

OX, YOUR CARD
AL ,OX AL,ISB
SERVICE
CS: FLAGS ,F I RST
EXIT

; Select your status register
Read the status reg i ster

Your card caused the interrupt?
Yes, branch to service logic
Are we the first ones in?
I f yes, branch for EOI and Rearm

Restore registers
DWORD PTR CS: FPTR

SERV I CE:
EXIT:

Disable interrupts
Pass contro I to next guy on cha i n
Service the interrupt

CL I
MOY
OUT
MOY
OUT
POP
IRET

Disable the interrupts
AL,EOI
OCR,AL
DX,REARM
DX,AL

RET
ENDP
MYCSEG
END

I ssue non-spec i f i c EO I to 8259

Rearm the cards
Restore registers

RESET:
ENTRY

Entry point of handler
Forward Pointer
Used when un link i ng to i dent i fy
compatible interrupt handlers
Flags

Disable your card
Return FAR to operat ing system
ENDS
ENTRY

System Board

1-19

Linking Code Example
PUSH

ES

ell

; Disable interrupts

Set forward pointer to value of interrupt vector in low memory
ASSUME
CS:CODESEG,DS:CODESEG
PUSH
ES
DOS get interrupt vector
MOV
AX,350FH
INT
21H
Get offset of your forward pointer
MOV
5 I ,OFFSET CS: FPTR
in an indexable register

MOV
MOV
CMP
JNZ
MOV
SETVECTR: POP
PUSH

CS:[SI1,BX
Store the old interrupt vector
; in your forward pointer for chaining
CS:[SI+21,ES
ES:BYTE PTR[BX1,CFH ; Test for IRET
SETVECTR
j Set up first in chain flag
CS:FLAGS,FIRST
ES
DS

; Make interrupt vector in low memory point to your handler
DX,OFFSET ENTRY
Make interrupt vector point to your handler
MOV

MOV
MOV
MOV
INT
POP
Unmask (enab Ie)
IN
JMP
AND
OUT
MOV
JMP
OUT
OCR,AL
STI
POP

1-20

If DS not ~ CS, get it
and put it in DS
DOS set interrupt vector

AX,SEG ENTRY
DS,AX
AX,250FH
21H
DS

interrupts for your

AL,IMR
$+2
AL,07FH
IMR,AL
AL,SPC EOI
$+2

level

Read interrupt mask register

10 delay
Unmask interrupt leve I 7

Write new interrupt mask
; Issue specific EOI for level

. to allow pending level 7 interrupts
(if any) to be serviced
Enable interrupts

ES

System Board

Unlinking Code Example
PUSH
OS
PUSH
ES
CLI
MOV
AX,350FH
INT
21H
MOV
CX,ES
Are we the first hand ler in the chain?
MOV
AX,CS
CMP
BX ,OFFSET ENTRY

Disable interrupts
DOS get interrupt vector
ES:BX points to first of chain

Pickup segment part of interrupt vector
Get code seg into comparab Ie reg i ster

Interrupt vector in low memory
pointing to your handler's offset?

JNE
CMP

UNCHA I N A
AX,CX -

; No, branch
; Vector pointing to your
; handler's segment?

JNE
UNCHA I N A
; No, branch
Set interrupt vector in low memory to point to the handler
pointed to by your pointer
PUSH
MOV
MOV
MOV
I NT
POP
JMP
UNCHAIN

A:
-

CMP

OS
OX,WORO PTR CS:FPTR
OS ,WORD PTR CS FPTR[2]
AX,250FH
DOS set interrupt vector
21H
DS
UNCHA I N X
BX = FPTR offset, ES
ES:[BX+6],4B42H

JNE

except ion

LDS
CMP

S I ,ES: [BX+2]
S I ,OFFSET ENTRY

JNE
MOV
CMP

UNCHA I N B
CX,DS AX,CX

FPTR segment, CX = CS
; Is handler using the appropriate
conventions (is SIGNATURE present in

;
the interrupt chaining structure)?
; No, invoke error exception handler
; Get FPTR' s segment and offset

Is this forward pointer pointing to
your handler's offset?

No, branch
Move to compare
Is this forward pointer pointing to

your handler's segment?
JNE
UNCHAIN B
No, branch
Located your handler in trle chain
MOV
AX,WORD PTR CS:FPTR ; Get your FPTR's offset
MOV
ES: [BX+2] ,AX
; Rep 1ace offset of FPTR of hand 1er
;
that points to you
MOV
AX ,WORD PTR CS: FPTR[2] ; Get your FPTR' s segment
MOV
ES: [BX+4] ,AX
; Rep 1ace segment of FPTR of hand 1er
that points to you
MOV
AL,CS:FLAGS
Get your flags
AND
AL,FIRST
Isolate FIRST flag
OR
ES:[BX + 6],AL
Set your first flag into prior routine
JMP
UNCHA IN

B: MOV
PUSH
PUSH
JMP

UNCHA I N X: ST I
POP
POP

UNCHAIN_X
BX ,S I
DS
ES
UNCHAIN

Move new offset to BX

A

Examine next handler in chain
Enable interrupts

ES
DS

System Board

1-21

System Timers
The system has three programmable timer/counters, Channels 0
through 2. They are controlled by an Intel 8254-2
Timer/Counter chip, and are defined as follows:
Channel 0

System Timer

GATE 0
CLKINO
CLKOUTO

Tied on
1.193182 MHz OSC
8259AIRQ 0

Channell

Refresh Request Generator

GATE 1
CLKIN 1
CLKOUT 1

Tied on
1.193182 MHz OSC
Request refresh cycle

Note: Channel 1 is programmed as a rate generator to
produce a IS-microsecond period signal.
Channel 2

Tone Generation for Speaker

GATE 2
CLKIN2
CLKOUT2

Controlled by bit 0 of port hex 61, PP! bit
1.193182 MHz OSC
Used to drive the speaker

The 8254-2 Timer/Counter is a programmable interval
timer/counter that system programs treat as an arrangement of
four external I/O ports. Three ports are treated as counters; the
fourth is a control register for mode programming. The following
is a system-timer block diagram..

1-22

System Board

+5 Vdc
-Refresh

Refresh Request
D Q
Clock
L - Clear

System Bus _ _
Gate

+5 Vdc
I/O Add ress
Hex 006 I Port Bi t a

a

Clock In

a

Gate I

-

Clock I n I

-

Gate 2

-

Clock In 2
Clock Out

IRQ

a

Clock Out I

r-

I Driver I

Clock Out 2

I AND I

I/O Add ress
Hex 006 I
Port Bi t I
PC LK

(2 .38MHz)

Divide
by 2

a

Low

Pass
Filter

1----+

To Speaker

I

System-Timer Block Diagram

System Clock
The 82284 System Clock Generator is driven by either a 12-MHz
or 16-MHz crystal. Its output 'clock' signal (CLK) is the input
to the system microprocessor, the coprocessor, and I/O channel.

ROM Subsystem
The system board's ROM subsystem consists of two 32K by 8-bit
ROM/EPROM modules in a 32K-by-16-bit arrangement. The
code for odd and even addresses resides in separate modules.
ROM is assigned at the top of the first and last 1M address space
(OFOOOO and FFOOOO). ROM is not parity-checked. Its
maximum access time is 260 nanoseconds (190ns) and its
maximum cycle time is 480ns (360ns).

System Board

1-23

RAM Subsystem
The system board's RAM subsystem starts at address 000000 of
the 16M address space. It is 256K or 512K of 128K-by-l-bit
RAM modules (type 1 system board) or 512K of 256K-by-l-bit
RAM modules (type 2 system board). Memory access time is 150
nanoseconds and the cycle time is 275 nanoseconds.
Memory refresh requests one memory cycle every 15
microseconds through the timer/counter (channell). The RAM
initialization program performs the following functions:
•

Initializes channel 1 of the timer/counter to the rate
generation mode, with a period of 15 microseconds

•

Performs a memory write operation to any memory location.
Note: The memory must be accessed or refreshed eight
times before it can be used.

I/O Channel
The I/O channel supports:
•

I/O address space hex 100 to hex 3FF

•

24-bit memory addresses (16M)

•

Selection of data accesses (either 8- or 16-bit)

•

Interrupts

•

DMA channels

•

I/O wait-state generation

1-24

System Board

•

Open-bus structure (allowing mUltiple microprocessors to
share the system's resources, including memory)

•

Refresh of system memory from channel microprocessors.

Connectors
The following figure shows the location and the numbering of the
I/O channel connectors. These connectors consist of six 36-pin
and eight 62-pin edge connector sockets.
Note: The 36-pin connector is not present in two positions
on the I/O channel. These positions can support only 62-pin
I/O bus adapters.
I/O CHANNEL
CONNECTORS

r--------~~,--------,
REAR PANEL

""'"

o

r

I/O Channel Connector Location

System Board

1-25

The following figure shows the pin numbering for I/O channel
connectors J1 through J8.
Rear Panel
B1

Al

Bl0

Al0

B20

A20

B31

l!J U l!J-t

A31

Component Side

I/O Channel Pin Numbering (J1-J8)

1-26

System Board

The following figure shows the pin numbering for I/O channel
connectors JIO through JI4 and JI6.
Rear Panel
01

C1

010

C10

018

c18
Component Side

I/O Channel Pin Numbering (J10-J14 and J16)

Syste. &o.nI

1-17

The following figures summarize pin assignments for the I/O
channel connectors.
I/O Pin

Signal Name

I/O

Al
A2
A3
A4
A5
A6
A7
A8
A9
AIO
All
Al2
Al3
A14
Al5
Al6
Al7
Al8
Al9
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A3l

-I/O CH CK
S07
S06
S05
so4
S03
S02
SOl
SOO
-I/O CH ROY
AEN
SAl9
SAl8
SAl7
SAl6
SAl5
SAl4
SAl3
SAl2
SAIl
SAIO
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SAl
SAO

I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0

I/O Channel (A-Side, J1 through Ja)

1-18

System Board

I/O Pin

Signal Name

I/O

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
Bll
B12
613
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31

GND
RESET DRV
+5 Vdc
IRQ 9
-5 Vdc
DRQ2
-12 Vdc
OWS
+12 Vdc
GND
-SMEMW
-SMEMR
-lOW
-lOR
-DACK3
DRQ3
-DACKI
DRQl
-REFRESH
CLK
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
-DACK2
T/C
BALE
+5Vdc
OSC
GND

Ground
0
Power
I
Power
I
Power
I
Power
Ground
0
0
I/O
I/O
0
I
0
I
I/O
0
I
I
I
I
I
0
0
0
Power
0
Ground

I/O Channel (B-Side, J1 through J8)

System Board

1-29

I/O Pin

Signal Name

I/O

C1
C2
C3
C4
C5
C6
C7
c8
C9
C10
C11
C12
C13
c14
C15
C16
C17
C18

SBHE
LA23
LA22
LA21
LA20
LA19
LA18
LA17
-MEMR
-MEMW
5008
SD09
5010
SD11
5012
SOl3
5014
5015

/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0

I/O Channel (C-Side, J10 through J14 and 16)
I/O Pin

Signal Name

I/O

D1
02
03
04
05
06
07
D8
09
010
011
012
013
014
015
016
017
D18

-MEM CS16
-I/O CS16
IRQ10
IRQ11
IRQ12
IRQ15
IRQ14
-OACKO
ORQO
-OACK5
DRQ5
-OACK6
DRQ6
-OACK7
ORQ7
+5 Vdc
-MASTER
GND

I
I
I
I
I
I
I
0
I
0
I
0
I
0
I
POWER
I
GROUND

I/O Channel (D-Side, J10 through J14 and 16)

1-30

System Board

110 Channel Signal Description
The following is a description of the system board's I/O channel
signals. All signal lines are TTL compatible. I/O adapters should
be designed with a maximum of two low-power Shottky (LS)
loads per line.

SAO through SA19 (I/O)
Address signals 0 through 19 are used to address memory and
I/O devices within the system. These 20 address lines, in
addition to LA17 through LA23 , allow access of up to 16M of
memory. SAO through SA19 are gated on the system bus when
'buffered address latch enable' signal (BALE) is high and are
latched on the falling edge of BALE. These signals are generated
by the microprocessor or DMA Controller. They also may be
driven by other microprocessors or DMA controllers that reside
on the II0 channel.

LA17 through LA23 (I/O)
These signals (unlatched) are used to address memory and I/O
devices within the system. They give the system up to 16M of
address ability. These signals are valid when BALE is high. LA17
through LA23 are not latched during microprocessor cycles and
therefore do not stay valid for the whole cycle. Their purpose is
to generate memory decodes for 16-bit, 1 wait-state, memory
cycles. These decodes should be latched by I/O adapters on the
falling edge of BALE.
These signals also may be driven by other microprocessors or
DMA controllers that reside on the I/O channel.
eLK (0)

This is the 6- or 8-MHz system 'clock' signal. It is a synchronous
microprocessor cycle clock with a cycle time of 167 nanoseconds
(125 nanoseconds). The clock has a 50% duty cycle. This signal
should be used only

System Board

1-31

for synchronization. It is not intended for uses requiring a fixed
frequency.

RESET DRV (0)
The 'reset drive' signal is used to reset or initialize system logic at
power-up time or during a low voltage condition. This signal is
active high.

SDO through SD15 (I/O)
These signals provide bus bits 0 through 15 for the
microprocessor, memory, and 110 devices. DO is the
least-significant bit and D15 is the most-significant bit. A118-bit
devices on the 1/0 channel should use DO through D7 for
communications to the microprocessor. The 16-bit devices will
use DO through D15. To support 8-bit devices, the data on D8
through D15 will be gated to DO through D7 during 8-bit
transfers to these devices; 16-bit microprocessor transfers to 8-bit
devices will be converted to two 8-bit transfers.
BALE (0) (buffered)

The 'buffered address latch enable' signal is provided by the
82288 Bus Controller and is used on the system board to latch
valid addresses and memory decodes from the microprocessor. It
is available to the 110 channel as an indicator of a valid
microprocessor or DMA address (when used with 'address
enable' signal, AEN). Microprocessor addresses SAO through
SA19 are latched with the falling edge of BALE. BALE is forced
high (active) during DMA cycles.

-I/O CO CK (I)
The '-I/O channel check' signal provides the system board with
parity (error) information about memory or devices on the I/O
channel. When this signal is active (low), it indicates a
non-correctable system error.

1-32

System Board

I/O CH RDY (I)
The 'I/O channel ready' signal is pulled low (not ready) by a
memory or I/O device to lengthen I/O or memory cycles. Any
slow device using this line should drive it low immediately upon
detecting its valid address and a Read or Write command.
Machine cycles are extended by an integral number of clock
cycles (167 nanoseconds). This signal should be held low for no
more than 2.5 microseconds.

IRQ3-IRQ7, IRQ9-IRQ12, IRQ14, and IRQ15 (I)
Interrupt requests 3 through 7,9 through 12, 14, and 15 are used
to signal the microprocessor that an I/O device needs attention.
The interrupt requests are prioritized, with IRQ9 through IRQI2,
IRQI4, and IRQ15 having the highest priority (IRQ9 is the
highest), and IRQ3 through IRQ7 having the lowest priority
(IRQ7 is the lowest). An interrupt request is generated when an
IRQ line is raised from low to high. The line is high until the
microprocessor acknowledges the interrupt request (Interrupt
Service routine).
Note: Interrupt 13 is used on the system board and is not
available on the I/O channel. IRQ 8 is used for the real-time
clock.

-lOR (I/O)
The '-I/O read' signal instructs an I/O device to drive its data
onto the data bus. This signal may be driven by the system
microprocessor or DMA controller, or by a microprocessor or
DMA controller resident on the I/O channel. This signal is active
low.

-lOW (I/O)
The '-I/O write' signal instructs an I/O device to read the data
off the data bus. It may be driven by any microprocessor or
DMA controller in the system. This signal is active low.

System Board

1-33

-SMEMR (0) -MEMR (I/O)
These signals instruct the memory devices to drive data onto the
data bus. -SMEMR is active only when the memory decode is
within the low 1M of memory space. -MEMR is active on all
memory read cycles. -MEMR may be driven by any
microprocessor or DMA controller in the system. -SMEMR is
derived from -MEMR and the decode of the low 1M of memory.
When a microprocessor on the I/O channel wishes to drive
-MEMR, it must have the address lines valid on the bus for one
clock cycle before driving -MEMR active. Both signals are active
low.

-SMEMW (0) -MEMW (I/O)
These signals instruct the memory devices to store the data
present on the data bus. -SMEMW is active only when the
memory decode is within the low 1M of the memory space.
-MEMW is active on all memory write cycles. -MEMW may be
driven by any microprocessor or DMA controller in the system.
-SMEMW is derived from -MEMW and the decode of the low
1M of memory. When a microprocessor on the I/O channel
wishes to drive -MEMW, it must have the address lines valid on
the bus for one clock cycle before driving -MEMW active. Both
signals are active low.

DRQO-DRQ3 and DRQ5-DRQ7 (I)
The DMA request signals 0 through 3 and 5 through 7 are
asynchronous channel requests used by peripheral devices and a
microprocessor to gain DMA service (or control of the system).
They are prioritized, with DRQO having the highest priority and
DRQ7 the lowest. A request is generated by bringing a DRQ line
to an active (high) level. A DRQ line is held high until the
corresponding I DMA acknowledge I (DACK) line goes active.
DRQO through DRQ3 perform 8-bit DMA transfers; DRQ5
through DRQ7 perform 16-bit transfers. DRQ4 is used on the
system board and is not available on the I/O channel.
I

1-34

I

System Board

-DACKO to -DACK3 and -DACK5 to -DACK7 (0)
-DMA acknowledge 0 through 3 and 5 through 7 are used to
acknowledge DMA requests. These signals are active low.

AEN (0)
The address enable signal is used to de gate the microprocessor
and other devices from the I/O channel to allow DMA transfers
to take place. When this line is active, the DMA controller has
control of the address bus, the data-bus Read command lines
(memory and I/O), and the Write command lines (memory and
1/0). This signal is active high.
I

I

-REFRESH (I/O)
This signal is used to indicate a refresh cycle and can be driven by
a microprocessor on the I/O channel. This signal is active low.

T/C (0)
The I terminal count I signal provides a high pulse when the
terminal count for any DMA channel is reached.

SHHE (I/O)
The I system bus high enable I signal indicates a transfer of data
on the upper byte of the data bus, SD8 through SDI5.
Sixteen-bit devices use SBHE to condition data bus buffers tied to
SD8 through SD 15. This signal is active high.

-MASTER (I)
This signal is used with a DRQ line to gain control of the system.
A processor or DMA controller on the I/O channel may issue a
DRQ to a DMA channel in cascade mode and receive a -DACK.
Upon receiving the -DACK, a microprocessor may pull

System Board

1-35

-MASTER active (low), which will allow it to control the system
address, data, and control lines (a condition known as tri-state).
After -MASTER is low, the microprocessor must wait one clock
cycle before driving the address and data lines, and two clock
cycles before issuing a Read or Write command. If this signal is
held low for more than 15 microseconds, the system memory may
be lost because of a lack of refresh.

-MEM CS16 (I)
The '-memory 16-bit chip select' signal indicates to the system
that the present data transfer is a 1 wait-state, 16-bit, memory
cycle. It must be derived from the decode of LA17 through
LA23. -MEM CS16 is active low and should be driven with an
open collector or tri-state driver capable of sinking 20 mA.

-I/O CS16 (I)
The '-I/O 16-bit chip select' signal indicates to the system that
the present data transfer is a 16-bit, 1 wait-state, I/O cycle. It is
derived from an address decode. -I/O CS16 is active low and
should be driven with an open collector or tri-state driver capable
of sinking 20 rnA.

OSC (0)
The 'oscillator' signal is a high-speed clock with a
70-nanosecond period (14.31818 MHz). This signal is not
synchronous with the system clock. It has a 50% duty cycle.

OWS (I)
The 'zero wait state' signal tells the microprocessor that it can
complete the present bus cycle without inserting any additional
wait cycles. In order to run a memory cycle to a 16-bit device
without wait cycles, OWS is derived from an address decode gated
with a Read or Write command. In order to run a memory cycle
to an 8-bit device with a minimum of two wait states, OWS should

1-36

System Board

be driven active one clock cycle after the Read or Write command
is active, and gated with the address decode for the device.
Memory Read and Write commands to an 8-bit device are active
on the falling edge of eLK. OWS is active low and should be
driven with an open collector or tri-state driver capable of sinking
20mA.

The following figure is an I/O address map.
Hex Range
000-01F
020-03F
040-05F
060-06F
070-07F
080-09F
OAO-OBF
OCO-ODF
OFO
OFI
OF8-0FF

Device
DMA controller 1,8237A-5
Interrupt controller 1, 8259A, Master
Timer 8254-2
8042 (Keyboard)
Real-time clock, NMI (non-maskable interrupt) mask
DMA page register , 74LS612
Interrupt Controller 2, 8259A
DMA controller 2, 8237A-5
Clear Math Coprocessor Busy
Reset Math Coprocessor
Math Coprocessor

Note: I/O Addresses, hex 000 to OFF, are reserved for the
system board I/O. Hex 100 to 3FF are available on the I/O
channe 1.

I/O Address Map (Part 1 of 2)

System Board

1-37

Device

Hex Range
lFO-1F8
200-207
20C-20D
21F
278-27F
2BO-2DF
2El
2E2 & 2E3
2F8-2FF
300-31F
360-363
364-367
368-36B
36C-36F
378-37F
380-38F
390-393
3AO-3AF
3BO-3BF
3CO-3CF
3DO-3DF
3FO-3F7
3F8-3FF
6E2 & 6E3
790-793
AE2 & AE3
B90-B93
EE2 & EE3
1390-1393
22El
2390-2393
42El
62El
82El
A2El
C2El
E2El

Fixed Disk
Game I/O
Reserved
Reserved
Parallel printer port 2
Alternate Enhanced Graphics Adapter
GPIB (Adapter 0)
Data Acquisition (Adapter 0)
Serial port 2
Prototype card
PC Network (low address)
Reserved
PC Network (high address)
Reserved
Parallel printer port 1
SDLC, bisynchronous 2
Cluster
Bisynchronous 1
Monochrome Display and Printer Adapter
Enhanced Graphics Adapter
Color/Graphics Monitor Adapter
Diskette controller
Serial port 1
Data Acquisition (Adapter 1)
Cluster (Adapter 1)
Data Acquisition (Adapter 2)
Cluster (Adapter 2)
Data Acquisition (Adapter 3)
Cluster (Adapter 3)
GPIB (Adapter 1)
Cluster (Adapter 4)
GPIB (Adapter 2)
GPIB (Adapter 3)
GPIB (Adapter 4)
GPIB (Adapter 5)
GPIB (Adapter 6)
GPIB (Adapter 7)

Note: I/O Addresses, hex 000 to OFF, are reserved for the
system board I/O. Hex 100 to 3FF are available on the I/O
channe I.

I/O Address Map (Part 2 of 2)

NMI and Coprocessor Controls
At power-on time, the non-maskable interrupt (NMI) into the
80286 is masked off. The mask bit can be set and reset with
system programs as follows:

1-38

System Board

Mask On

Write to I/O address hex 070, with data bit 7
equal to a logic O.

Mask Off

Write to I/O address hex 070, with data bit 7
equal to a logic 1.

Note: At the end of POST, the system sets the NMI mask
on (NMI enabled).

The following is a description of the Math Coprocessor controls.
OFO

An 8-bit Out command to port FO will clear the latched
Math Coprocessor -busy signal. The -busy signal will
be latched if the coprocessor asserts its -error signal
while it is busy. The data output should be zero.
I

I

I

I

OF1

I
I

An 8-bit Out command to port Fl will reset the Math
Coprocessor. The data output should be zero.

1/a address hex 080 is used as a diagnostic-checkpoint port or
register. This port corresponds to a read/write register in the
DMA page register (74LS612).
The -1/ a channel check signal (-I/O CH CK) is used to report
non-correctable errors on RAM adapters on the I/O channel.
This check will create an NMI if the NMI is enabled. At
power-on time, the NMI is masked off and -I/O CH CK is
disabled. Follow these steps when enabling -I/O CH CK and the
NMI.
I

I

1.

Write data in all I/O RAM-adapter memory locations; this
will establish good parity at all locations.

2.

Enable -I/O CH CK.

3.

Enable the NMI.
Note:

All three of these functions are performed by POST.

When a check occurs, an interrupt (NMI) will result. Read the
status bits to determine the source of the NMI (see the figure,
"I/O Address Map", on page 1-37). To determine the location
of the failing adapter, write to any memory location within a given

System Board

1-39

adapter. If the parity check was from that adapter, -I/O CH CK

will be reset to inactive.

Other Circuits

Speaker
The system unit has a 2-1/4 inch permanent-magnet speaker,
which can be driven from:
•
•
•

The I/O-port output bit
The timer/counter's eLK OUT 2
Both of the above

RAM Jumpers
The system board has a 3-pin, Berg-strip connector (118).
Starting at the front of the system, the pins are numbered 1
through 3. Jumper placement across these pins determines how
much system board RAM is enabled. Pin assignments follow.
Pin

Assignments

1

No Connection
- RAM SEL
Ground

2

3

RAM Jumper Connector (J18)

1-40

System Board

The following shows how the jumpers affect RAM.
Jumper Positions
1 and 2
2 and 3

Function
Enable 2nd 256K of system board RAM
Disable 2nd 256K of system board RAM

RAM Jumper

Note: The normal mode is the enable mode. The other
mode permits the additional RAM to reside on adapters
plugged into the II0 bus.

Display Switch
Set the slide switch on the system board to select the primary
display adapter. Its positions are assigned as follows:

On (toward the front of the system unit): The primary display
is attached to the Color/Graphics Monitor Adapter or
Professional Graphics Controller.

Off (toward the rear of the system unit): The primary display
is attached to the Monochrome Display and Printer Adapter.
The switch may be set to either position if the primary display is
attached to an Enhanced Graphics Adapter.
Note: The primary display is activated when the system
is powered on.

Variable Capacitor
The system board has a variable capacitor. Its purpose is to
adjust the 14.31818 MHz oscillator signal COSC), used to obtain
the color-burst signal required for color televisions.

System Board

1-41

Keyboard Controller
The keyboard controller is a single-chip microcomputer (Intel
8042) thatis programmed to support the keyboard serial
interface. The keyboard controller receives serial data from the
keyboard, checks the parity of the data, translates scan codes, and
presents the data to the system as a byte of data in its output
buffer. The controller can interrupt the system when data is
placed in its output buffer, or wait for the system to poll its status
register to determine when data is available.
Data is sent to either keyboard by first polling the controller's
status register to determine when the input buffer is ready to
accept data and then writing to the input buffer. Each byte of
data is sent to the keyboard serially with an odd parity bit
automatically inserted. Since both keyboards are required to
acknowledge all data transmissions, another byte of data should
not be sent to the keyboard until acknowledgement is received for
the previous byte sent. The output-buffer-full interrupt may be
used for both send and receive routines.

Keyboard Controller Initialization
At power-on, the keyboard controller sets the system flag bit to O.
After a power-on reset or the execution of the Self Test
command, the keyboard controller disables the keyboard interface
by forcing the 'keyboard clock' line low. The keyboard interface
parameters are specified at this time by writing to locations within
the 8042 RAM. The keyboard-inhibit function is then disabled
by setting the inhibit-override bit in the command byte. A hex 55
is then placed in the output buffer if no errors are detected during
the self test. Any value other than hex 55 indicates that the 8042
is defective. The keyboard interface is now enabled by lifting the
'keyboard data' and 'keyboard clock' signal lines, and the system
flag is set to 1. The keyboard controller is then ready to accept
commands from the system unit microprocessor or receive
keyboard data.
The initialization sequence causes the 10l/102-Key Keyboard to
establish Mode 2 protocol (see "Data Stream" on page 4-61).

1-42

System Board

Receiving Data from the Keyboard
The keyboard sends data in a serial format using an II-bit frame.
The first bit is a start bit, and is followed by eight data bits, an
odd parity bit, and a stop bit. Data sent is synchronized by a
clock supplied by the keyboard. At the end of a transmission, the
keyboard controller disables the interface until the system accepts
the byte. If the byte of data is received with a parity error, a
Resend command is automatically sent to the keyboard. If the
keyboard controller is unable to receive the data correctly after a
set number of retries, a hex FF is placed in its output buffer, and
the parity bit in the status register is set to 1, indicating a receive
parity error. The keyboard controller will also time a byte of data
from the keyboard. If a keyboard transmission does not end
within 2 milliseconds, a hex FF is placed in the keyboard
controller's output buffer, and the receive time-out bit in the
status register is set. No retries will be attempted on a receive
time-out error.
Note: When a receive error occurs in the default mode
(bits 5, 6, and 7 of the command byte set to 0), hex 00 is
placed in the output buffer instead of hex FF. See
"Commands (I/O Address Hex 64)" on page 1-51 for a
detailed description of the command byte.

Scan Code Translation
Scan codes received from the keyboard are converted by the
keyboard controller before being placed into the controller's
output buffer. The following figures show the 84-key and the
10l/102-key keyboard layouts. Each key position is numbered
for reference.

System Board

1-43

84-Key Keyboard

1-44

System Board

IOI-Key Keyboard

System Board

1-45

l02-Key Keyboard

1-46

System Board

The following figure is the scan-code translation table.
System
Scan Code

Keyboard
Scan Code

Key
(101/102-key)

Key
(84-key)

01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B

76
16
1E
26
25
2E
36
3D
3E
46
45
4E
55
66
OD
15
1D
24
2D
2C
35
3C
43
44
4D
54
56
5A
14
1C
1B
23
2B
34
33
3B
42
4B
4c
52
OE
12
5D

90
2
3
4
5
6
7
8
9
10
11
12
13
15
16
17
18
19
20
21
22
23
24
25
26
27
28
43
30
31
32
33
34
35
36
37
38
39
40
41
1
44
14

2C
2D
2E
2F

1A
22
21
2A

110
2
3
4
5
6
7
8
9
10
11
12
13
15
16
17
18
19
20
21
22
23
24
25
26
27
28
43
58
31
32
33
34
35
36
37
38
39
40
41
1
44
29 (U.S. only)
42 (except U.S.)
46
47
48
49

46
47
48
49

Scan-Code Translation Table (Part 1 of 3)

System Board

1-46.1

System
Scan Code
30
31
32
33
34
35
36
38
39
3A
3B
3C
30
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4c
40
4E
4F
50
51
52
53
54
05
09
OA
FF
2A 37
45 C5
EO lC
EO 10
EO 35
EO 37
EO 38
EO 47

Keyboard
Scan Code

Key

(101/102-key)

32
31
3A
41
49
4A
59
11
29
58
05
06
04
OC
03
OB
02 or 83
OA
01
09
77
7E
6C
75
70
7B
6B
73
74
79
69

50
51
52
53
54
55
57
60
61
30
112
113
114
115
116
117
118
119
120
121
-

125
91
96
101
105
92
97
102
106
93
98
103
99
104

72

7A
70
71
7F or 84
FO 60
FO OF
FO 17
00
12 7C
77 FO 77
FO 47 5A
FO 47 14
FO 47 4A
FO 47 7C
FO 47 11
FO 47 6C

Scan-Code Translation Table (Part 2 of 3)

1-46.2

System Board

-

45 (except u. S. )
122
123
-

124
90
108
64
95
100
62
80

Key
(84-key)
50
51
52
53
54
55
57
58
61
64
70
65
71
66
72

67

73

68
74
69
95
100
91
96
101
107
92
97
102
108
93
98
103
99
104
105
-

-

-

System
Scan Code
EO 48
EO 49
EO 46
EO 4D
EO 4F
EO 50
EO 51
EO 52
EO 53
1D EO 45 EO C5 9D

Keyboard
Scan Code

Key
(101/102-key)

FO 47 75
FO 47 7D
FO 47 66
FO 47 74
FO 47 69
FO 47 72
FO 47 7A
FO 47 70
FO 47 71
14 FO 47 77 FO 47
FO 77 FO 14

83
85
79
89
81
84
86
75
76
126

Key
(84-key)
-

-

Scan-Code Translation Table (Part 3 of 3)

System Board

1-46.3

Notes:

1-46.4 System Board

The following scan codes are reserved.
Key

Keyboard
Scan Code

System
Scan Code

Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

60
61
78
07
OF
17
1F
27
2F
37
3F
47
4F
56
5E
08
10
18
20
28
30
38
40
48
50
57
6F
13
19
39
51
53
5C
5F
62
63
64
65
67
68
6A
60
6E

55
56
57
58
59
5A
56
5C
50
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
66
6C
60
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
76
7C
70
7E
7F

Reserved Scan-Code Translation Table

System Board

1-47

Sending Data to the Keyboard
The keyboard sends data in the same serial format used to receive
data from the keyboard. A parity bit is automatically inserted by
the keyboard controller. If the keyboard does not start clocking
the data from the keyboard controller within 15 milliseconds, or
complete that clocking within 2 milliseconds, a hex FE is placed
in the keyboard controller's output buffer, and the transmit
time-out error bit is set in the status register.
The keyboard is required to respond to all transmissions. The
keyboard responds to any valid command and parameter, other
than Echo and Resend, with an Acknowledge (ACK) response,
hex FA. If the response contains a parity error, the keyboard
controller places a hex FE in its output buffer, and the transmit
time-out and parity error bits are set in the status register. The
keyboard controller is programmed to set a 25-millisecond time
limit for the keyboard to respond. If this time limit is exceeded,
the keyboard controller places a hex FE in its output buffer and
sets the transmit time-out and receive time-out error bits in the
status register. No retries are attempted by the keyboard
controller for any transmission error.

Inhibit
The keyboard interface may be inhibited by setting input port bit
7 (keyboard inhibit switch) to o. All transmissions to the
keyboard will be allowed regardless of the state of this bit. The
keyboard controller tests data received from the keyboard to
determine if the byte received is a command response or a scan
code. If the byte is a command response, it is placed in the
keyboard controller's output buffer. If the byte is a scan code, it
is ignored.

Keyboard Controller System Interface
The keyboard controller communicates with the system through a
status register, an output buffer, and an input buffer. The
following figure is a block diagram of the keyboard interface.

1-48

System Board

~ RAM on the system board
N ~ Manufacturing mode
P ~ Display type

Input
Buffer

r
.

System
Data

Bus

~
U

T

~

:: ~~~~e~2~eset

~

1----+ U -

Output
+---ir-,_======~
Buffer

Keyboard Inhibited

T -

IRQ I
Keyboard Clock--r-+

TPu

Keyboa r d Data

-

-+--.-+

~2_K_R~_~_8~r··_ _ _~.-_ _ _ _ _ _~
Keyboard Controller Interface Block Diagram

Status Register
The status register is an 8-bit read-only register at I/O address
hex 64. It has information about the state of the keyboard
controller (8042) and interface. It may be read at any time.

Status-Register Bit Definition
Bit 7

Parity Error-A 0 indicates the last byte of data received
from the keyboard had odd parity. A 1 indicates the last
byte had even parity. The keyboard should send data
with odd parity.

Bit 6

Receive Time-Out-A 1 indicates that a transmission was
started by the keyboard but did not finish within the
programmed receive time-out delay.

Bit S

Transmit Time-Out-A 1 indicates that a transmission
started by the keyboard controller was not properly
completed. If the transmit byte was not clocked out
within the specified time limit, this will be the only error.

System Board

1-49

If the transmit byte was clocked out but a response was

not received within the programmed time limit, the
transmit time-out and receive time-out error bits are set
to 1. If the transmit byte was clocked out but the
response was received with a parity error, the transmit
time-out and parity error bits are set to 1.
Bit 4

Inhibit Switch-This bit is updated whenever data is
placed in the keyboard controller's output buffer. It
reflects the state of the keyboard-inhibit switch. A 0
indicates the keyboard is inhibited.

Bit 3

Command/Data-The keyboard controller's input buffer
may be addressed as either I/O address hex 60 or 64.
Address hex 60 is defined as the data port, and address
hex 64 is defined as the command port. Writing to
address hex 64 sets this bit to 1; writing to address hex 60
sets this bit to O. The controller uses this bit to determine
if the byte in its input buffer should be interpreted as a
command byte or a data byte.

Bit 2

System Flag-This bit is monitored by the system during
the reset routine. If it is a 0, the reset was caused by a
power on. The controller sets this bit to 0 at power on
and it is set to 1 after a successful self test. This bit can
be changed by writing to the system flag bit in the
command byte (hex 64).

Bit 1

Input Buffer Full-A 0 indicates that the keyboard
controller's input buffer (I/O address hex 60 or 64) is
empty. A 1 indicates that data has been written into the
buffer but the controller has not read the data. When the
controller reads the input buffer, this bit will return to O.

Bit 0

Output Buffer Full-A 0 indicates that the keyboard
controller's output buffer has no data. A 1 indicates that
the controller has placed data into its output buffer but
the system has not yet read the data. When the system
reads the output buffer (I/O address hex 60), this bit will
return to a O.

1-50

System Board

Output Buffer
The output buffer is an 8-bit read-only register at I/O address
hex 60. The keyboard controller uses the output buffer to send
scan codes received from the keyboard, and data bytes requested
by command, to the system. The output buffer should be read
only when the output-buffer-full bit in the status register is 1.

Input Buffer
The input buffer is an 8-bit write-only register at I/O address hex
60 or 64. Writing to address hex 60 sets a flag, which indicates a
data write; writing to address hex 64 sets a flag, indicating a
command write. Data written to I/O address hex 60 is sent to the
keyboard, unless the keyboard controller is expecting a data byte
following a controller command. Data should be written to the
controller's input buffer only if the input buffer's full bit in the
status register is O. The following are valid keyboard controller
commands.

Commands (I/O Address Hex 64)
20

Read Keyboard Controller's Command Byte-The
controller sends its current command byte to its output
buffer.

60

Write Keyboard Controller's Command Byte-The next
byte of data written to I/O address hex 60 is placed in
the controller's command byte. Bit definitions of the
command byte are as follows:
Bit 7

Reserved-Should be written as a O.

Bit 6

IBM Personal Computer Compatibility
Mode-Writing a 1 to this bit causes the
controller to convert the scan codes received
from the keyboard to those used by the IBM
Personal Computer. This includes converting a
2-byte break sequence to the 1-byte IBM
Personal Computer format.

System Board

1-51

Bit 5

IBM Personal Computer Mode-Writing a 1 to
this bit programs the keyboard to support the
IBM Personal Computer keyboard interface. In
this mode the controller does not check parity or
convert scan codes.

Bit 4

Disable Keyboard-Writing a 1 to this bit
disables the keyboard interface by driving the
I clock I line low. Data is not sent or received.

Bit 3

Inhibit Override-Writing a 1 to this bit disables
the keyboard inhibit function.

Bit 2

System Flag-The value written to this bit is
placed in the system flag bit of the controller's
status register.

Bit 1

Reserved-Should be written as a O.

Bit 0

Enable Output-Buffer-Full Interrupt-Writing a
1 to this bit causes the controller to generate an
interrupt when it places data into its output
buffer.

AA

Self-Test-This commands the controller to perform
internal diagnostic tests. A hex 55 is placed in the output
buffer if no errors are detected.

AD

Interface Test-This commands the controller to test the
keyboard clock and keyboard data lines. The test
result is placed in the output buffer as follows:
I

00
01
02
03
04

1-52

I

I

I

No error detected.
The I keyboard clock I line is stuck low.
The keyboard clock line is stuck high.
The I keyboard data I line is stuck low.
The keyboard data line is stuck high.
I

I

System Board

I

I

AC

Diagnostic Dump-Sends 16 bytes of the controller's
RAM, the current state of the input port, the current
state of the output port, and the controller's program
status word to the system. All items are sent in scan-code
format.

AD

Disable Keyboard Feature-This command sets bit 4 of
the controller's command byte. This disables the
keyboard interface by driving the clock line low. Data
will not be sent or received.

AE

Enable Keyboard Interface-This command clears bit 4
of the command byte, which releases the keyboard
interface.

CO

Read Input Port-This commands the controller to read
its input port and place the data in its output buffer. This
command should be used only if the output buffer is
empty.

DO

Read Output Port-This command causes the controller
to read its output port and place the data in its output
buffer. This command should be issued only if the output
buffer is empty.

D1

Write Output Port-The next byte of data written to I/O
address hex 60 is placed in the controller's output port.
Note: Bit 0 of the controller's output port is
connected to System Reset. This bit should not be
written low as it will reset the microprocessor.

EO

Read Test Inputs-This command causes the controller
to read its TO and T1 inputs. This data is placed in the
output buffer. Data bit 0 represents TO, and data bit 1
represents T 1.

System Board

1-53

FO-FF Pulse Output Port-Bits 0 through 3 of the controller's

output port may be pulsed low for approximately 6
microseconds. Bits 0 through 3 of this command indicate
which bits are to be pulsed. A 0 indicates that the bit
should be pulsed, and a 1 indicates the bit should not be
modified.
Note: Bit 0 of the controller's output port is
connected to System Reset. Pulsing this bit resets
the microprocessor.

I/O Ports
The keyboard controller has two I/O ports, one assigned for
input and the other for output. Two test inputs are used by the
controller to read the state of the keyboard's I clock I (TO) and
I data I (T 1) lines.
The following figures show bit definitions for the input and output
ports, and the test-inputs.

1-54

System Board

Bit 7
Bit 6
Bit 5
Bit

4

Bit
Bit
Bit
Bit

3
2
1

0

Keyboard inhibit switch
o = Keyboard inhibited
1 = Keyboard not inhibited
Display switch - Primary display attached to:
o = Color/Graphics adapter
1 = Monochrome adapter
Manufacturing Jumper
o = Manufacturing jumper installed
1 = Jumper not installed
RAM on the system board
o = Enable 512K of system board RAM
1 = Enable 256K of system board RAM
Reserved
Reserved
Reserved
Reserved

Input-Port Bit Definitions
B
B
B
B

B
B

B
B

t
t
t
t
t
t
t
t

7
6
5

4
3

2
1
0

Keyboard data (output)
Keyboard clock (output)
Input buffer empty
Output buffer full
Reserved
Reserved
Gate A20
System reset

Output-Port Bit Definitions
Keyboard data (input)
Keyboard clock (input)

Test-Input Bit Definitions

System Board

1-55

Real-Time Clock/CMOS RAM Information
The RT!CMOS RAM chip (Motorola MC146818) contains the
real-time clock and 64 bytes of CMOS RAM. The internal clock
circuitry uses 14 bytes of this RAM, and the rest is allocated to
configuration information. The following figure shows the CMOS
RAM addresses.
Addresses

00 - 00
OE
OF
10
11
12

13
14

15
16
17
18

19
lA
18 - 20

2E - 2F
30

31
32
33
34 - 3F

Description

*
*
*

Real-time clock information
Diagnostic status byte
Shutdown status byte
Diskette drive type byte - drives A and B
Reserved
Fixed disk type byte - types 1-14
Reserved
Equipment byte
Low base memory byte
High base memory byte
Low expansion memory byte
High expansion memory byte
Disk C extended byte
Disk 0 extended byte
Reserved
2-byte CMOS checksum
* Low expansion memory byte
* High expansion memory byte
* Date century byte
* Information flags (set during power on)
Reserved

CMOS RAM Address Map

... These bytes are not included in the checksum calculation and
are not part of the configuration record.

1-56

System Board

Real-Time Clock Infonnation
The following figure describes real-time clock bytes and specifies
their addresses.
Byte

Function

Address

0
1
2
3
4
5
6
7
8
9
10
11
12
13

Seconds
Second Alarm
Minutes
Minute Alarm
Hours
Hour Alarm
Day of Week
Date of Month
Month
Year
Status Register
Status Register
Status Register
Status Register

00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD

A
B
C
D

Real-Time Clock Information (Addresses 00 - OD)

Note: The setup program initializes registers A, B, C, and
D when the time and date are set. Also Interrupt lA is the
BIOS interface to read/set the time and date. It initializes
the status bytes the same as the Setup program.

Status Register A
Bit 7

Update in Progress (UIP)-A 1 indicates the
time update cycle is in progress. A 0 indicates
the current date and time are available to read.

Bit 6-Bit 4

22-Stage Divider (DV2 through DVO)-These
three divider-selection bits identify which
time-base frequency is being used. The system
initializes the stage divider to 010, which selects a
32.768-kHz time base.

System Board

1-57

Bit 3-Bit 0

Rate Selection Bits (RS3 through RSO)-These
bits allow the selection of a divider output
frequency. The system initializes the rate
selection bits to 0110, which selects a 1.024-kHz
square wave output frequency and a
976.562-microsecond periodic interrupt rate.

Status Register B
Bit 7

Set-A 0 updates the cycle normally by
advancing the counts at one-per-second. A 1
aborts any update cycle in progress and the
program can initialize the 14 time-bytes without
any further updates occurring until a 0 is written
to this bit.

Bit 6

Periodic Interrupt Enable (PIE)-This bit is a
read/write bit that allows an interrupt to occur at
a rate specified by the rate and divider bits in
register A. A 1 enables an interrupt, and a 0
disables it. The system initializes this bit to o.

Bit 5

Alarm Interrupt Enable (AIE)-A 1 enables the
alarm interrupt, and a 0 disables it. The system
initializes this bit to O.

Bit 4

Update-Ended Interrupt Enabled (UIE)-A 1
enables the update-ended interrupt, and a 0
disables it. The system initializes this bit to O.

Bit 3

Square Wave Enabled (SQWE)-A 1 enables the
the square-wave frequency as set by the rate
selection bits in register A, and a 0 disables the
square wave. The system initializes this bit to O.

Bit 2

Date Mode (DM)-This bit indicates whether
the time and date calendar updates are to use
binary or binary coded decimal (BCD) formats.
A 1 indicates binary, and a 0 indicates BCD. The
system initializes this bit to O.

1-58

System Board

Bit 1

24/ 12-This bit indicates whether the hours byte
is in the 24-hour or 12-hour mode. A 1 indicates
the 24-hour mode and a 0 indicates the 12-hour
mode. The system initializes this bit to 1.

Bit 0

Daylight Savings Enabled (DSE)-A 1 enables
daylight savings and a 0 disables daylight savings
(standard time). The system initializes this bit
to O.

Status Register C
Bit 7-Bit 4

IRQF, PF, AF, UF-These flag bits are
read-only and are affected when the AlE, PIE,
and VIE bits in register B are set to 1.

Bit 3-Bit 0

Reserved-Should be written as a O.

Status Register D
Bit 7

Valid RAM Bit (VRB)-This bit is read-only and
indicates the status of the power-sense pin
(battery level). A 1 indicates battery power to
the real-time clock is good. A 0 indicates the
battery is dead, so RAM is not valid.

Bits 6-Bit 0

Reserved-Should be written as a O.

CMOS RAM Configuration Information
The following lists show bit definitions for the CMOS
configuration bytes (addresses hex OE - 3F).

Diagnostic Status Byte (Hex OE)
Bit 7

Power status of the real-time clock chip-A 0
indicates that the chip has not lost power, and a 1
indicates that the chip lost power.

System Board

1-59

Bit 6

Configuration Record (Checksum Status
Indicator)-A 0 indicates that checksum is good,
and a 1 indicates it is bad.

Bit 5

Incorrect Configuration Information-This is a
check, at power-on time, of the equipment byte
of the configuration record. A 0 indicates that
the configuration information is valid, and a 1
indicates it is invalid. Power-on checks require:
•

At least one diskette drive to be installed (bit
o of the equipment byte set to O.

•

The primary display adapter setting in
configuration matches the system board's
display switch setting and the actual display
adapter hardware in the system.

Bit 4

Memory Size Comparison-A 0 indicates that
the power-on check determined the same memory
size as in the configuration record, and a 1
indicates the memory size is different.

Bit 3

Fixed Disk Adapter/Drive C Initialization
Status-A 0 indicates that the adapter and drive
are functioning properly and the system can
attempt "boot up." A 1 indicates that the
adapter and/or drive C failed initialization, which
prevents the system from attempting to "boot
up."

Bit 2

Time Status Indicator (POST validity check)- A
o indicates that the time is valid, and a 1 indicates
that it is invalid.

Bit 1-Bit 0

Reserved

1-60

System Board

Shutdown Status Byte (Hex OF)
The bits in this byte are defined by the power on diagnostics. For
more information about this byte, refer to "System BIOS".

Diskette Drive Type Byte (Hex 10)
Bit 7-Bit 4

Type of first diskette drive installed:
0000 No drive is present.
0001 Double Sided Diskette Drive (48 TPI).
0010 High Capacity Diskette Drive (96 TPI).

Note:
Bit 3-Bit 0

0100 through 1111 are reserved.

Type of second diskette drive installed:
0000 No drive is present.
0001 Double Sided Diskette Drive (48 TPI).
0010 High Capacity Diskette Drive (96 TPI).

Note:

0100 through 1111 are reserved.

Hex address 11 contains a reserved byte.

System Board

1-61

Fixed Disk Type Byte (Hex 12)
Bit 7-Bit 4

Defines the type of first fixed disk drive installed
(drive C):
0000 No fixed disk drive is present.
0001 Define type 1 through type 14 as shown
to
in the following table (also see BIOS
1110 listing at label FD_TBL)
1111 Type 16 through 255. See "Drive C
Extended Byte (Hex 19)" on page 1-65.

Bit 3-Bit 0

Defines the type of second fixed disk drive
installed (drive D):
0000 No fixed disk drive is present.
0001 Define type 1 through type 14 as shown
to
in the following table (also see BIOS
1110 listing at label FD_TBL)
1111 Type 16 through 255. See "Drive D
Extended Byte (Hex lA)" on page 1-65.

1-62

System Board

The following table shows the BIOS fixed disk parameters.
Type

Cylinders

Heads

Write
Pre-Comp

Landing
Zone

1
2
3
4
5
6
7
8
9
10
11
12
13
14

306
615
615
940
940
615
462
733
900
820
855
855
306
733

4
4
6
8
6
4
8
5
15
3
5
7
8
7

128
300
300
512
512
None
256
None
None
None
None
None
128
None

305
615
615
940
940
615
511
733
901
820
855
855
319
733

15

Extended Parameters (hex 19 and lA)

BIOS Fixed Disk Parameters

Hex address 13 contains a reserved byte.
Equipment Byte (Hex 14)
Bit 7-Bit 6

Indicates the number of diskette drives installed:
00 1 drive
01 2 drives
10 Reserved
11 Reserved

Bit 5-Bit 4

Primary display
00 Primary display is attached to an adapter that
has its own BIOS, such as one of the
following:

•
•

the Enhanced Graphics Adapter
the Professional Graphics Controller.

System Board

1-63

01 Primary display is in the 40-column mode and
attached to the Color/Graphics Monitor
Adapter.
10 Primary display is in the 80-column mode and
attached to the Color/Graphics Monitor
Adapter.
11 Primary display is attached to the
Monochrome Display and Printer Adapter.
Bit 3-Bit 2

Not used.

Bit 1

Math Coprocessor presence bit:

o

Math Coprocessor not installed
1 Math Coprocessor installed

Bit 0

Diskette drive presence bit:

o

Diskette drive not installed
1 Diskette drive installed

Note: The equipment byte defines basic equipment in the
system for power-on diagnostics.

Low and High Base Memory Bytes (Hex 15 and 16)
Bit 7-Bit 0

Address hex 15-Low-byte base size

Bit 7-Bit 0

Address hex 16-High-byte base size
Valid Sizes:
01000 256K-system board RAM
02000 512K-system board RAM
02800 640K-512K system board RAM, the
IBM Personal Computer AT 128KB
Memory Expansion Option, or the
128/640KB Memory Expansion
Option

1-64

System Board

Low and High Expansion Memory Bytes (Hex 17 and 18)
Bit 7-Bit 0

Address hex 17-Low-byte expansion size

Bit 7-Bit 0

Address hex 18-High-byte expansion size
Valid Sizes:
0200H 512K-Expansion Memory
0400H 1024K-Expansion Memory
0600H 1536K-Expansion Memory

through
3COOH 15360K-Expansion Memory (15M
maximum).

Drive C Extended Byte (Hex 19)
Bit 7-Bit 0

Defines the type of first fixed disk drive installed
(drive C):
00000000 through 0000 1111 are reserved.
000 10000 to 11111111 define type 16 through
255 as shown in the following table (see BIOS
listing at label FD_TBL).

Drive D Extended Byte (Hex lA)
Bit 7-Bit 0

Defines the type of second fixed disk drive
installed (drive D):
00000000 through 0000 1111 are reserved.
000 10000 to 11111111 define type 16 through
255 as shown in the following table (see BIOS
listing at label FD_TBL).

System Board

1-65

The following table shows the BIOS fixed disk parameters for
fixed disk drive types 16 through 23.
Note:

Types 24 through 255 are reserved.

Type

Cylinders

Heads

16
17
18
19
20
21
22
23

612
977
977
1024
733
733
733
306

4
5
7
7
5
7
5
4

Write
Pre-Camp
All Cyl

300

None

512
300
300
300

None

24

Reserved

255

Reserved

Landing
Zone

663
977
977
1023
732
732
733
336

BIOS Fixed Disk Parameters (Extended)

Hex addresses 1B through 2D are reserved.

Checksum (Hex 2E and 2F)
Bit 7-Bit 0

Address hex 2E-High byte of checksum

Bit 7-Bit 0

Address hex 2F-Low byte of checksum

Note:

1-66

Checksum is calculated on addresses hex 1O-2D.

System Board

Low and High Expansion Memory Bytes (Hex 30 and 31)
Bit 7-Bit 0

Address hex 30-Low-byte expansion size

Bit 7-Bit 0

Address hex 31-High-byte expansion size
Valid Sizes:
0200H
0400H
0600H
through
3COOH

512K-Expansion Memory
1024K-Expansion Memory
1536K-Expansion Memory
15360K-Expansion Memory (15M
maximum).

Note: These bytes reflect the total expansion memory
above the 1M address space as determined at power-on
time. This expansion memory size can be determined
through system interrupt 15 (see the BIOS listing). The
base memory at power-on time is determined through the
system memory-size-determine interrupt (hex 12).

Date Century Byte (Hex 32)
Bit 7-Bit 0

BCD value for the century (BIOS interface to read
and set).

Information Flag (Hex 33)
Bit 7

When set, this bit indicates that the top 128K of
base memory is installed.

Bit 6

This bit is set to instruct the Setup utility to put
out a first user message after initial setup.

Bit 5-Bit 0

Reserved

Hex addresses 34 through 3F are reserved.

System Board

1-67

110 Operations
Writing to CMOS RAM involves two steps:
1. OUT to port hex 70 with the CMOS address that will be
written to.
2. OUT to port hex 71 with the data to be written.
Reading CMOS RAM also requires two steps:
1. OUT to port hex 70 with the CMOS address that is to be read

from.
2. IN from port hex 71, and the data read is returned in the AL
register.

1-68

System Board

Specifications
System Unit
Size
•

Length: 538 millimeters (21.2 inches)

•

Depth: 429 millimeters (16.9 inches)

•

Height: 142 millimeters (5.6 inches)

Weight
•

19.5 kilograms (43 pounds)

Power Cables
•

Length: 1.8 meters (6 feet)

Environment
•

Air Temperature
-

System On: 15.6 to 32.2 degrees C (60 to 90 degrees F)
System Off: 10 to 43 degrees C (50 to 110 degrees F)

•

Wet Bulb Temperature
System On: 22.8 degrees C (73 degrees F)
-

System Off: 26.7 degrees C (80 degrees F)

System Board

1-69

•

Humidity
System On: 8% to 80%
System Off: 20% to 80%

•

Altitude
-

Maximum altitude: 2133.6 meters (7000 feet)

Heat Output
•

1229 British Thermal Units (BTU) per hour

Noise Level
•

42 decibels average-noise rating (without printer)

Electrical

• Power: 450 VA
•

Range 1
Nominal: 115 Vac
Minimum: 100 Vac
Maximum: 125 Vac

•

Range 2
Nominal: 230 Vac
Minimum: 200 Vac
Maximum: 240 Vac

1-70

System Board

Connectors
The system board has the following additional connectors:
•

Two power-supply connectors (PS8 and PS9)

•

Speaker connector (J19)

•

Power LED and key lock connector (120)

•

Battery connector (121)

•

Keyboard connector (122)

The pin assignments for the power-supply connectors, PS8 and
PS9, are as follows. The pins are numbered 1 through 6 from the
rear of the system.
Connector

Pin

Assignments

ps8

1
2
3
4
5

Power Good
+5 Vdc
+12 Vdc
-12 Vdc
Ground
Ground

1
2
3
4
5

Ground
Ground
-5 Vdc
+5 Vdc
+5 Vdc
+5 Vdc

6

PS9

6

Power Supply Connectors (PS8, PSg)

System Board

1-71

The speaker connector, 119, is a 4-pin, keyed, Berg strip. The
pins are numbered 1 through 4 from the front of the system. The
pin assignments are as follows:
Pin

Function

1

Data out
Key
Ground
+5 Vdc

2

3
4

Speaker Connector (J19)

The power LED and key lock connector, 120, is a 5-pin Berg
strip. The pins are numbered 1 through 5 from the front of the
system. The pin assignments are as follows:
Pin

Assignments

1
2

LED Power
Key
Ground
Keyboard Inhibit
Ground

3
4
5

Power LED and Key Lock Connector (J20)

The battery connector, 121, is a 4-pin, keyed, Berg strip. The
pins are numbered 1 through 4 from the right of the system. The
pin assignments are as follows:
Pin
1
2

3
4

Assignments
Ground
Not Used
Key
6 Vdc

Battery Connector (J21)

1-72

System Board

The keyboard connector, 122, is a 5-pin, 90-degree Printed
Circuit Board (PCB) mounting, DIN connector. For pin
numbering, see the "Keyboard" Section. The pin assignments are
as follows:
Pin
1

2

3

4

5

Assignments
Keyboard Clock
Keyboard Data
Reserved
Ground
+5 Vdc

Keyboard Connector (J22)

System Board

1-73

The following figure shows the layout of the system board.

Rear Panel
Battery

~~ Connector

~@====t=J (J21)

Power
Supply
Connectors

1/0
Channel
Connectors

Variable
Capacitor

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1-74

System Board

Note: The memory module
layout and system board
dimensions may vary.

Notes:

System Board

1-75

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SECTION 2. COPROCESSOR

Contents
Description ...................................... 2-3
Programming Interface

............................. 2-3

Hardware Interface .........................•.....• 2-4

Coprocessor

2-1

Notes:

2-2

Coprocessor

Description
The IBM Personal Computer AT Math Coprocessor enables the
IBM PERSONAL COMPUTER AT to perform high-speed
arithmetic, logarithmic functions, and trigonometric operations.
The coprocessor works in parallel with the microprocessor. The
parallel operation decreases operating time by allowing the
coprocessor to do mathematical calculations while the
microprocessor continues to do other functions.
The coprocessor works with seven numeric data types, which are
divided into the following three classes:
•

Binary integers (3 types)

•

Decimal integers (1 type)

•

Real numbers (3 types).

Programming Interface
The coprocessor offers extended data types, registers, and
instructions to the microprocessor.
The coprocessor has eight 80-bit registers, which provides the
equivalent capacity of forty 16-bit registers. This register space
allows constants and temporary results to be held in registers
during calculations, thus reducing memory access and improving
speed as well as bus availability. The register space can be used as
a stack or as a fixed register set. When used as a stack, only the
top two stack elements are operated on.

Coprocessor

2-3

The following figure shows representations of large and small
numbers in each data type.
Significant
Digits
Bits (Decimal) Approximate Range (Decimal)

Data Type
Word Integer

16

4

-32,768

$

X $ +32,767

Short Integer

32

9

-2xl0 9

$

X $ +2xl0 9

Long Integer

64

18

-9xl0 18 $

Packed Decimal

80

18

-9 .. 99

32

6-7

64

Short Real
Long Real

*
*

Temporary Real

80

$

X $ +9xl0 18
X $ +9 .. 99 (18 dig its)

8.43xl0-37

$

IXI

$

3.37xl0 38

15-16

4.19xl0- 307

$

IXI

$

1. 67x 10308

19

3. 4x 10- 4932 $

IXI

$

1. 2x 104932

Data Types

* The Short Real and Long Real data types correspond to the
single and double precision data types.

Hardware Interface
The coprocessor uses the same clock generator as the
microprocessor. It works at one-third the frequency of the system
microprocessor. The coprocessor is wired so that it functions as
an I/O device through I/O port addresses hex OOF8, OOFA, and
OOFC. The microprocessor sends OP codes and operands through
these I/O ports. The microprocessor also receives and stores
results through the same I/O ports. The coprocessor's 'busy'
signal informs the microprocessor that it is executing; the
microprocessor's Wait instruction forces the microprocessor to
wait until the coprocessor is finished executing.
The coprocessor detects six different exception conditions that
can occur during instruction execution. If the appropriate
exception mask within the coprocessor is not set, the coprocessor
sets its error signal. This error signal generates a hardware
interrupt (interrupt 13) and causes the 'busy' signal to the
coprocessor to be held in the busy state. The 'busy' signal may

2-4

Coprocessor

be cleared by an 8-bit I/O Write command to address hex FO
with DO through D7 equal to O.
The power-on self-test code in the system ROM enables IRQ 13
and sets up its vector to point to a routine in ROM. The ROM
routine clears the busy signal's latch and then transfers control
to the address pointed to by the NMI interrupt vector. This
allows code written for any IBM Personal Computer to work on
an IBM Personal Computer AT. The NMI interrupt handler
should read the coprocessor's status to determine if the NMI was
caused by the coprocessor. If the interrupt was not generated by
the coprocessor, control should be passed to the original NMI
interrupt handler.
I

I

The coprocessor has two operating modes similar to the two
modes of the microprocessor. When reset by a power-on reset,
system reset, or an I/O write operation to port hex 00F1, the
coprocessor is in the real address mode. This mode is compatible
with the 8087 Math Coprocessor used in other IBM Personal
Computers. The coprocessor can be placed in the protected mode
by executing the SETPM ESC instruction. It can be placed back
in the real mode by an I/O write operation to port hex OOF 1, with
D7 through DO equal to O.
The coprocessor instruction extensions to the microprocessor can
be found in Section 6 of this manual.
Detailed information for the internal functions of the Intel 80287
Coprocessor can be found in books listed in the bibliography.

Coprocessor

l-S

Notes:

2-6

Coprocessor

SECTION 3. POWER SUPPLY

Contents
Inputs

.......................................... 3-3

Outputs ......................................... 3-4

DC Output Protection ...........•.................. 3-4
Output Voltage Sequencing ..•...............•....•.. 3-4
No-Load Operation .....................•.....•.... 3-5
Power-Good Signal ...........•.•....•.......•....• 3-5
Load Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-5
Connectors .................•.................... 3-7

Power Supply

3-1

Notes:

3-2

Power Supply

The system power supply is contained inside of the system unit
and provides power for the system board, the adapters, the
diskette drives, the fixed disk drives, the keyboard, and the IBM
Monochrome Display.

Inputs
The power supply can operate at a frequency of either 60 ± 3 Hz
or 50 ±3 Hz and it can operate at 110 Vac, 5 A or 220/240 Vac,
2.5 A. The voltage is selected with the switch above the
power-cord plug at the rear of the power supply. The following
figure shows the input requirements.
Range
115 Vac

Voltage (Vac)
Minimum 100

Current (Amperes)
Maximum 5

Maximum 125

230 Vac

Minimum 200
Maximum 240

Maximum 3.0

Input Requirements

Note:

The maximum in-rush current is 100 A.

Power Supply

3-3

Outputs
The power supply provides +5, -5, + 12, and -12 Vdc. The
following figure shows the load current and regulation tolerance
for these voltages. The power supply also supplies either 115 Vac
or 230 Vac for the IBM Monochrome Display.
Nominal
Output

Load Current (A)
Min
Max

Regulation
Tolerance

+5
-5
+12
-12

7.0
0.0
2.5
0.0

+5% to -4%
+10% to -8%
+5% to -4%
+10% to -9%

Vdc
Vdc
Vdc
Vdc

19.8
0.3
7.3
0.3

DC Load Requirements

DC Output Protection
If any output becomes overloaded, the power supply will switch

off within 20 milliseconds. An overcurrent condition will not
damage the power supply.

Output Voltage Sequencing
Under normal conditions, the output voltage levels track within
300 milliseconds of each other when power is applied to, or
removed from the power supply, provided at least minimum
loading is present.

3-4

Power Supply

No-Load Operation
No damage or hazardous conditions occur when primary power is
applied with no load on any output level. In such cases, the
power supply may switch off, and a power-on reset will be
required. The power supply requires a minimum load for proper
operation.

Power-Good Signal
The power supply provides a I power-good I signal to indicate
proper operation of the power supply.
When the supply is switched off for a minimum of one second and
then switched on, the I power-good I signal is generated, assuming
there are no problems. This signal is a logical AND of the dc
output-voltage sense signal and the ac input-voltage sense signal.
The I power-good I signal is also a TTL-compatible high level for
normal operation, or a low level for fault conditions. The ac fail
signal causes power-good to go to a low level at least one
millisecond before any output voltage falls below the regulation
limits. The operating point used as a reference for measuring the
one millisecond is normal operation at minimum line voltage and
maximum load.
I

I

Load Resistor
If no fixed disk drive is connected to the power supply, the load
resistor must be connected to PIO. The load resistor is a 5 ohm,
50 watt resistor.

Power Supply

3-5

The dc output-voltage sense signal holds the I power-good I signal
at a low level when power is switched on until all output voltages
have reached their minimum sense levels. The I power-good I
signal has a turn-on delay of at least 100 milliseconds but not
longer than 500 milliseconds and can drive six standard TTL
loads.
The following figure shows the minimum sense levels for the
output voltages.
Level (Vdc)

Minimum (Vdc)

+5
-5
+12
-12
Sense Level

3-6

Power Supply

+4.5
-3.75
+10.8
-10.4

Connectors
The following figure shows the pin assignments for the
power-supply output connectors.
Load Point

Voltage (Vdc)

Max.
Current (A)

PSS-l
PSS-2
PSS-3
PSS-4
PSS-5
PsS-6

Power Good
+5
+12
-12
Ground
Ground

See Note
3.S
0.7
0.3
0.0
0.0

PS9-1
PS9-2
PS9-3
PS9-4
PS9-5
PS9-6

Ground
Ground
-5
+5
+5
+5

0.0
0.0
0.3
3.S
3.S
3.S

Pl0-l
Pl0-2
Pl0-3
Pl0-4

+12
Ground
Ground
+5

2.S
0.0
0.0
I.S

P11-1
P11-2
P11-3
P11-4

+12
Ground
Ground
+5

2.S
0.0
0.0
I.S

P12-1
P12-2
P12-3
P12-4

+12
Ground
Ground
+5

1.0
0.0
0.0
0.6

DC Load Distribution
Note:

For more details, see "Power-Good Signal".

Power Supply

3-7

Notes:

3-8

Power Supply

SECTION 4. KEYBOARD

Introduction .................................. 4-5
84-Key Keyboard Description ................. 4-5
Cabling ................................ 4-5
Sequencing Key Code Scanning ............. 4-5
Keyboard Buffer ......................... 4-6
Keys .................................. 4-6
Power-On Routine .......................... 4-7
Power-On Reset ......................... 4-7
Basic Assurance Test ..................... 4-7
Commands from the System ................... 4-7
Default Disable (Hex F5) .................. 4-8
Echo (Hex EE) .......................... 4-8
Enable (Hex F4) ......................... 4-8
No-Operation (NOP) (Hex FD through F7) ... 4-8
No-Operation (NOP) (Hex F2 through EF) ... 4-8
Resend (Hex FE) ........................ 4-9
Reset (Hex FF) ......................... 4-9
Set Default (Hex F6) ..................... 4-9
Set Typematic Rate/Delay (Hex F3) ......... 4-9
Set/Reset Mode Indicators (Hex ED) ....... 4-11
Commands to the System .................... 4-12
ACK (Hex FA) ........................ 4-12
BAT Completion Code (Hex AA) .......... 4-12
Break Code Prefix (Hex FO) .............. 4-12
Diagnostic Failure (Hex FD) .............. 4-12
ECHO Response (Hex EE) ............... 4-12
Overrun (Hex 00) ....................... 4-13
Resend (Hex FE) ....................... 4-13
Keyboard Scan-Code Outputs ................ 4-13
Clock and Data Signals ...................... 4-14
Keyboard Data Output ................... 4-15
Keyboard Data Input .................... 4-16
Keyboard Encoding and Usage ................ 4-17
Character Codes .......... :............. 4-17
Extended Functions ..................... 4-21
Shift States ............................ 4-22
Special Handling ........................ 4-24

Keyboard

4-1

Keyboard Layouts .........................
FrenchKeyboard .......................
German Keyboard ......................
Italian Keyboard ........................
Spanish Keyboard .......................
u.K. English Keyboard ...................
U.S. English Keyboard ...................
Specifications .............................
Size ..................................
Weight ...............................
Logic Diagram ............................
1Ol/102-Key Keyboard Description ..............
Cabling ...............................
Sequencing Key-Code Scanning ............
Keyboard Buffer ........................
Keys .................................
Power-On Routine .........................
Power-On Reset ........................
Basic Assurance Test ....................
Commands from the System ..................
Default Disable (Hex F5) .................
Echo (Hex EE) .........................
Enable (Hex F4) ........................
Invalid Command (Hex EF and F 1) .........
Read ID (Hex F2) ......................
Resend (Hex FE) .......................
Reset (Hex FF) ........................
Select Alternate Scan Codes (Hex FO) .......
Set All Keys (Hex F7, F8, F9, FA) .........
Set Default (Hex F6) ....................
Set Key Type (Hex FB, FC, FD) ...........
Set/Reset Status Indicators (Hex ED) .......
Set Typematic Rate/Delay (Hex F3) ........
Commands to the System ....................
Acknowledge (Hex FA) ..................
BAT Completion Code (Hex AA) ..........
BAT Failure Code (Hex FC) ..............
Echo (Hex EE) .........................
Keyboard ID (Hex 83AB) ................
Key Detection Error (Hex 00 or FF) ........
Overrun (Hex 00 or FF) ..................
Resend (Hex FE) .......................
Keyboard Scan Codes .......................

4-2

Keyboard

4-27
4-28
4-29
4-30
4-31
4-32
4-33
4-34
4-34
4-34
4-35
4-36
4-37
4-37
4-38
4-38
4-39
4-39
4-39
4-40
4-40
4-41
4-41
4-41
4-41
4-41
4-42
4-42
4-43
4-43
4-43
4-44
4-45
4-47
4-47
4-47
4-47
4-47
4-48
4-48
4-48
4-48
4-49

Scan Code Set 1 ........................
Scan Code Set 2 ........................
Scan Code Set 3 ........................
Clock and Data Signals ......................
Data Stream ...........................
Keyboard Data Output ...................
Keyboard Data Input ....................
Keyboard Encoding and Usage ................
Character Codes ........................
Extended Functions .....................
Shift States ............................
Special Handling ........................
Keyboard Layouts .........................
FrenchKeyboard .......................
German Keyboard ......................
Italian Keyboard ........................
Spanish Keyboard .......................
UK. English Keyboard ...................
US. English Keyboard ...................
Specifications .............................
Power Requirements .....................
Size ..................................
Weight ...............................
Logic Diagram ............................

Keyboard

4-49
4-54
4-58
4-61
4-61
4-62
4-63
4-64
4-64
4-68
4-70
4-72
4-74
4-75
4-76
4-77
4-78
4-79
4-80
4-81
4-81
4-81
4-81
4-82

4-3

Notes:

4-4

Keyboard

Introduction
The 84-Key Keyboard information starts below. Information
about the Enhanced Personal Computer Keyboard, hereafter
referred to as the lOl/102-Key Keyboard, begins on page 4-36.

84-Key Keyboard Description
The keyboard is a low-profile, 84-key, detachable unit. A
bidirectional serial interface in the keyboard is used to carry
signals between the keyboard and system unit.

Cabling
The keyboard cable connects to the system board through a 5-pin
DIN connector. The following table lists the connector pins and
their signals.
DIN Connector Pins

Signal Name

1

+KBD ClK
+KBD DATA
Reserved
Ground
+5.0 Vdc

2

3
4
5

Sequencing Key Code Scanning
The keyboard is able to detect all keys that are pressed, and their
scan codes will be sent to the interface in correct sequence,
regardless of the number of keys held down. Keystrokes entered
while the interface is inhibited (when the key lock is on) will be
lost. Keystrokes are stored only when the keyboard is not
serviced by the system.

84-Key Keyboard

4-5

Keyboard Buffer
The keyboard has a 16-character first-in-first-out (FIFO) buffer
where data is stored until the interface is ready to receive it.
A buffer-overrun condition will occur if more than 16 codes are
placed in the buffer before the first keyed data is sent. The 17th
code will be replaced with the overrun code, hex 00. (The 17th
position is reserved for overrun codes). If more keys are pressed
before the system allows a keyboard output, the data will be lost.
When the keyboard is allowed to send data, the characters in the
buffer will be sent as in normal operation, and new data entered
will be detected and sent.

Keys
All keys are classified as make/break, which means when a key is
pressed, the keyboard sends a make code for that key to the
keyboard controller. When the key is released, its break code is
sent (the break code for a key is its make code preceded by hex
FO).

All keys are typematic. When a key is pressed and held down, the
keyboard continues to send the make code for that key until the
key is released. The rate at which the make code is sent is known
as the typematic rate (The typematic rate is described under "Set
Typematic Rate/Delay"). When two or more keys are held
down, only the last key pressed repeats at the typematic rate.
Typematic operation stops when the last key pressed is released,
even if other keys are still held down. When a key is pressed and
held down while the interface is inhibited, only the first make
code is stored in the buffer. This prevents buffer overflow as a
result of typematic action.

4-6

84-Key Keyboard

Power-On Routine
Power-On Reset
The keyboard logic generates a POR when power is applied to the
keyboard. The POR lasts a minimum of 300 milliseconds and a
maximum of 9 seconds.
Note: The keyboard may issue a false return during the first 200
milliseconds after the +5 Vdc is established at the 90% level.
Therefore, the keyboard interface is disabled for this period.

Basic Assurance Test
Immediately following the POR, the keyboard executes a basic
assurance test (BAT). This test consists of a checksum of all
read-only memory (ROM), and a stuck-bit and addressing test of
.
all random-access memory (RAM) in the keyboard's
microprocessor. The mode indicators-three light emitting diodes
(LEDs) on the upper right-hand corner of the keyboard-are
turned on then off, and must be observed to ensure they are
operational.
Execution of the BAT will take from 600 to 900 milliseconds.
(This is in addition to the time required for the POR.)
The BAT can also be started by a Reset command.
After the BAT, and when the interface is enabled ('clock' and
'data' lines are set high), the keyboard sends a completion code
to the interface-either hex AA for satisfactory completion or
hex FC (or any other code) for a failure. If the system issues a
Resend command, the keyboard sends the BAT completion code
again. Otherwise, the keyboard sets the keys to typematic and
make/break.

Commands from the System
The commands described below may be sent to the keyboard at
any time. The keyboard will respond within 20 milliseconds.

84-Key Keyboard

4-7

Note: The following commands are those sent by the system.

They have a different meaning when issued by the keyboard.

Default Disable (Hex F5)
This command is similar to Set Default, except the keyboard stops
scanning and awaits further instructions.

Echo (Hex EE)
Echo is a diagnostic aid. When the keyboard receives this
command, it issues a hex EE response and continues scanning if
the keyboard was previously enabled.

Enable (Hex F4)
Upon receipt of this command, the keyboard responds with ACK,
clears its output buffer, and starts scanning.

No-Operation (NOP) (Hex FD through F7)
These commands are reserved and are effectively no-operation or
NOP. The system does not use these codes. If sent, the keyboard
will acknowledge the command and continue in its prior scanning
state. No other operation will occur.

No-Operation (NOP) (Hex F2 through EF)
These commands are reserved and are effectively no-operation
(NOP). The system does not use these codes. If sent, the
keyboard acknowledges the command and continues in its prior
scanning state. No other operation will occur.

4-8

84-Key Keyboard

Resend (Hex FE)
The system can send this command when it detects an error in
any transmission from the keyboard. It can be sent only after a
keyboard transmission and before the system enables the
interface to allow the next keyboard output. Upon receipt of
Resend, the keyboard sends the previous output again unless the
previous output was Resend. In this case, the keyboard will
resend the last byte before the Resend command.

Reset (Hex FF)
The system issues a Reset command to start a program reset and a
keyboard internal self-test. The keyboard acknowledges the
command with an 'acknowledge' signal (ACK) and ensures the
system accepts the ACK before executing the command. The
system signals acceptance of the ACK by raising the clock and
data for a minimum of 500 microseconds. The keyboard is
disabled from the time it receives the Reset command until the
ACK is accepted or until another command overrides the previous
one. Following acceptance of the ACK, the keyboard begins the
reset operation, which is similar to a power-on reset. The
keyboard clears the output buffer and sets up default values for
typematic and delay rates.

Set Default (Hex F6)
The Set Default command resets all conditions to the power-on
default state. The keyboard responds with ACK, clears its output
buffer, sets default conditions, and continues scanning (only if the
keyboard was previously enabled).

Set Typematic Rate/Delay (Hex F3)
The system issues this command, followed by a parameter, to
change the typematic rate and delay. The typematic rate and
delay parameters are determined by the value of the byte
following the command. Bits 6 and 5 serve as the delay
parameter and bits 4,3,2, 1, and 0 (the least-significant bit) are
the rate parameter. Bit 7, the most-significant bit, is always o.
The delay is equal to 1 plus the binary value of bits 6 and 5

S4-Key Keyboard

4-9

multiplied by 250 milliseconds ±20%. The period (interval from
one typematic output to the next) is determined by the following
equation:
Period = (8 + A) X (2B) X 0.00417 seconds.
where:
A = binary value of bits 2, 1, and o.
B = binary value of bits 4 and 3.
The typematic rate (make code per second) is 1 per period. The
period is determined by the first equation above. The following
table results.
Bit 4 - 0

Typematic
Rate ± 20%

Bit 4 - 0

Typematic
Rate ± 20%

00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111

30.0
26.7
24.0
21.8
20.0
18.5
17.1
16.0
15.0
13.3
12.0
10.9
10.0
9.2
8.0
8.0

10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111

7.5
6.7
6.0
5.5
5.0
4.6
4.3
4.0
3.7
3.3
3.0
2.7
2.5
2.3
2.1
2.0

The keyboard responds to the Set Typematic Rate/Delay
command with an ACK, stops scanning, and waits for the rate
parameter. The keyboard responds to the rate parameter with
another ACK, sets the rate and delay, and continues scanning (if
the keyboard was previously enabled). If a command is received
instead of the rate parameter, the set-typematic-rate function
ends with no change to the existing rate, and the new command is
processed. However, the keyboard will not resume scanning
unless instructed to do so by an Enable command.
The default rate for the system keyboard is as follows:
Typematic rate = 10 characters per second ±20%
Delay = 500 ms ±20%.

4-10

84-Key Keyboard

Set/Reset Mode Indicators (Hex ED)
Three mode indicators on the keyboard are accessible to the
system. The keyboard activates or deactivates these indicators
when it receives a valid command from the system. They can be
activated or deactivated in any combination.
The system remembers the previous state of an indicator so that
its setting does not change when a command sequence is issued to
change the state of another indicator.
A Set/Reset Mode Indicators command consists of 2 bytes. The
first is the command byte and has the following bit setup:
1110 11 0 1 - hex ED
The second byte is an option byte. It has a list of the indicators to
be acted upon. The bit assignments for this option byte are as
follows:
Bit
a
1
2

3-7

Indicator
Scroll Lock Indicator
Num Lock Indicator
Caps Lock Indicator
Reserved (must be a's)

Note: Bit 7 is the most-significant bit; bit 0 is the

least-significant.
The keyboard will respond to the Set/Reset Mode Indicators
command with an ACK, discontinue scanning, and wait for the
option byte. The keyboard will respond to the option byte with
an ACK, set the indicators, and continue scanning if the keyboard
was previously enabled. If another command is received in place
of the option byte, execution of the function of the Set/Reset
Mode Indicators command is stopped with no change to the
indicator states, and the new command is processed. Then
scanning is resumed.

84-Key Keyboard

4-11

Commands to the System
The commands described here are those sent by the keyboard.
They have a different meaning when issued by the system.

ACK(HexFA)
The keyboard issues an ACK response to any valid input other
than an Echo or Resend command. If the keyboard is interrupted
while sending ACK, it will discard ACK and accept and respond
to the new command.

BAT Completion Code (Hex AA)
Following satisfactory completion of the BAT, the keyboard
sends hex AA. Hex FC (or any other code) means the keyboard
microprocessor check failed.

Break Code Prefix (Hex FO)
This code is sent as the first byte of a 2-byte sequence to indicate
the release of a key.

Diagnostic Failure (Hex FD)
The keyboard periodically tests the sense amplifier and sends a
diagnostic failure code if it detects any problems. If a failure
occurs during BAT, the keyboard stops scanning and waits for a
system command or power-down to restart. If a failure is
reported after scanning is enabled, scanning continues.

ECHO Response (Hex EE)
This is sent in response to an Echo command from the system.

4-12

84-Key Keyboard

Overrun (Hex 00)
An overrun character is placed in position 17 of the keyboard
buffer, overlaying the last code if the buffer becomes full. The
code is sent to the system as an overrun when it reaches the top of
the buffer.

Resend (Hex FE)
The keyboard issues a Resend command following receipt of an
invalid input, or any input with incorrect parity. If the system
sends nothing to the keyboard, no response is required.

Keyboard Scan-Code Outputs
Each key is assigned a unique 8-bit make scan code, which is sent
when the key is pressed. Each key also sends a break code when
the key is released. The break code consists of 2 bytes, the first
of which is the break code prefix, hex FO; the second byte is the
same as the make scan code for that key.
The typematic scan code for a key is the same as the key's make
code. Refer to "Keyboard Layouts" beginning on page 4-27 to
determine the character associated with each key number.
The following table lists the positions of the keys and their make
scan codes.

84-Key Keyboard

4-13

Key
Number
1
2
3

4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
30

Make Code

Key
Number

Make Code

Key
Number

Make Code

OE
16
1E
26
25
2E
36
3D
3E
46
45
4E
55
5D
66
OD
15
1D
24
2D
2C
35
3C
43
44
4D
54
5B
14

31
32
33
34
35
36
37
38
39
40
41
43
44
46
47
48
49
50
51
52
53
54
55
57
58
61
64
65
66

1C
1B
23
2B
34
33
3B
42
4B
4C
52
5A
12
1A
22
21
2A
32
31
3A
3C
49
4A
59
11
29
58
06
OC

67
68
69
70
71

OB
OA
09
05
04
03
83
01
76
6C
6B
69

72

73
74
90
91
92
93
95
96
97
98
99
100
101
102
103
104
105
106
107
108

77

75
73
72

70
7E
7D
74
7A
71
84
7C
7B
79

Note: Break code consists of 2 bytes; the first is hex FO, the
second is the make scan code for that key.

Clock and Data Signals
The keyboard and system communicate over the 'clock' and
'data' lines. The source of each of these lines is an
open-collector device on the keyboard that allows either the
keyboard or the system to force a line to a negative level. When
no communication is occurring, both the 'clock' and 'data' lines
are at a positive level.
Data transmissions to and from the keyboard consist of II-bit
data streams that are sent serially over the 'data' line. The
following table shows the structure of the data stream.

4-14

84-Key Keyboard

Bit
1
2
3
4
5
6
7

8

9
10
11

Function
Start bit (always 1)
Data bit 0 (least-significant)
Data bit 1
Data bit 2
Data bit 3
Data bit 4
Data bit 5
Data bit 6
Data bit 7 (most-significant)
Parity bit (odd parity)
Stop bit (always 1)

The parity bit is either 1 or 0, and the eight data bits plus the
parity bit always equals an odd number.
When the system sends data to the keyboard, it forces the 'data'
line to a negative level and allows the 'clock' line to go to a
positive level.
When the keyboard sends data to, or receives data from the
system, it generates the 'clock' signal to time the data. The
system can prevent the keyboard from sending data by forcing the
'clock' line to a negative level; the 'data' line may go high or low
during this time.
During the BAT, the keyboard allows the 'clock' and 'data' lines
to go to a positive level.

Keyboard Data Output
When the keyboard is ready to send data, it first checks for a
keyboard-inhibit or system request-to-send status on the 'clock'
and' data' lines. If the' clock' line is low (inhibit status), data is
stored in the keyboard buffer. If the 'clock' line is high and
'data' is low (request-to-send), data is stored in the keyboard
buffer, and the keyboard receives system data.
If 'clock' and' data' are both high, the keyboard sends the 0
start bit, 8 data bits, the parity bit and the stop bit. Data will be
valid after the rising edge and before the falling edge of the
, clock' line. During transmission, the keyboard checks the
, clock' line for a positive level at least every 60 milliseconds. If

84-Key Keyboard

4-15

the system lowers the 'clock' line from a positive level after the
keyboard starts sending data, a condition known as line contention
occurs, and the keyboard stops sending data. If line contention
occurs before the rising edge of the 10th clock (parity bit), the
keyboard buffer returns the 'data' and 'clock' lines to a positive
level. If contention does not occur by the tenth clock, the
keyboard completes the transmission.
Following a transmission, the system can inhibit the keyboard
until the system processes the input or until it requests that a
response be sent.

Keyboard Data Input
When the system is ready to send data to the keyboard, it first
checks if the keyboard is sending data. If the keyboard is sending
but has not reached the tenth clock, the system can override the
keyboard output by forcing the' clock' line to a negative level. If
the keyboard transmission is beyond the tenth clock, the system
must receive the transmission.
If the keyboard is not sending, or if the system elects to override

the keyboard's output, the system forces the' clock' line to a
negative level for more than 60 microseconds while preparing to
send. When the system is ready to send the start bit (' data' line
will be low), it allows the 'clock' line to go to a positive level.
The keyboard checks the state of the 'clock' line at intervals of
no less than 60 milliseconds. If a request-to-send is detected, the
keyboard counts 11 bits. After the tenth bit, the keyboard forces
the 'data' line low and counts one more (the stop bit). This
action signals the system that the keyboard has received its data.
Upon receipt of this signal, the system returns to a ready state, in
which it can accept keyboard output, or goes to the inhibited state
until it is ready.
Each system command or data transmission to the keyboard
requires a response from the keyboard before the system can send
its next output. The keyboard will respond within 20 milliseconds
unless the system prevents keyboard output. If the keyboard
response is invalid or has a parity error, the system sends the
command or data again. A Resend command should not be sent
in this case.

4-16

84-Key Keyboard

Keyboard Encoding and Usage
The keyboard routine, provided by IBM in the ROM BIOS, is
responsible for converting the keyboard scan codes into what will
be termed Extended ASCII. The extended ASCII codes returned
by the ROM routine are mapped to the U.S. English keyboard
layout. Some operating systems may make provisions for
alternate keyboard layouts by providing an interrupt replacer,
which resides in the read/write memory. This section discusses
only the ROM routine.
Extended ASCII encompasses I-byte character codes, with
possible values of 0 to 255, an extended code for certain extended
keyboard functions, and functions handled within the keyboard
routine or through interrupts.

Character Codes
The character codes described later are passed through the BIOS
keyboard routine to the system or application program. A "-1"
means the combination is suppressed in the keyboard routine.
The codes are returned in the AL register. See "Characters,
Keystrokes, and Color" later in this manual for the exact codes.

84-Key Keyboard

4-17

The following table shows the keyboard layout and key positions.

4-18

84-Key Keyboard

Key
I

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
30 Ctrl
31
32
33
34
35
36
37
38
39
40
41
43
44 Sh i ft
(Left)
46
47
48

Base Case

Uppercase

I

~

1
2
3
4
5
6
7
8
9
0

!
@

#
$

%
A

&

*
(
)

=

+

\

Backspace
(008)
--+1 (009)
q

1

Backs)ace
(008
I+- (*)
Q

w

w

e
r
t
y
u
i

E
R
T

Y

U
1

0

0

p

P

{
}

{
}

-1
a
s
d
f
g
h

-1
A
S
D
F
G
H

j

J

k

K
L

I
;

:

I

"

CR
-1

CR
-1

z

Z

x
c

X
C

Ctrl

Alt

-1
-1
Nul(OOO) (* )
-1
-1
-1
RS(030)
-1
-1
-1
-1
US(031)
-1
FS(028)
Del(127)

-1
(* )
(* )
(*)
(*)
(*)
(* )
(*)
(*)
(*)
(*)
(*)
(*)
-1
-1

-1
DC1(017)
ETB(023)
ENQ(005)
DC2(018)
Dc4(020)
EM(025)
NAK(021)
HT(009)
SI(015)
DLE(016)
Esc(027)
GS(029)
-1
SOH(OOl )
DC3(019)
EOT(004)
ACK(006)
BEL(007)
B5(008)
LF(010)
VT (011 )
FF(012)
-1
-1
LF(010)
-1

-1
(*)
(* )
(*)
(*)
(*)
(*)
(*)
(*)
(*)
(*)
(*)
-1
-1
(* )
(*)
(*)
(* )
(*)
(* )
(* )
(*)
(*)
-1
-1
-1
-1

SUB(026)
CAN(024)
ETX(003)

( )
( )
( )

Notes:
(*) Refer to "Extended Functions" in this section.
(**) Refer to "Special Handling" in this section.
Character Codes (Part 1 of 2)

84-Key Keyboard

4-19

Key
49
50
51
52
53
54
55
57 Sh ift
(Right)
58 Al t
61
64 Caps
Lock
90
95 Num
Lock
100 Scro 11
Lock
107
108
112
113
114
115
116
117
118

Base Case

Uppercase

Ctrl

(*)
(*)
(*)
(*)
-1
-1
-1
-1

/
-1

-1

SYN(022)
STX(002)
50(014)
CR(013)
-1
-1
-1
-1

-1
Space
-1

-1
Space
-1

-1
Space
-1

Esc
-1

Esc
-1 (*)

Esc
Pause (**)

-1
-1

-1

-1

Break (**)

-1

Enter
Null (*)
Nu 11 (*)
Nu 11 (*)
Nu 11 (*)
Nu 11 (*)
Nu 11 (*)
Nu 11 (*)

Enter
Nu 11 (*)
Nu 11 (*)
Nu 11 (*)
Nu 11 (*)
Nu 11 (*)
Nu 11 (*)
Nu 11 (* )

(*)
LF(010)
Nu 11 (*)
Nu 11 (*)
Nu 11 (*)
Nu 11 (*)
Nu 11 (* )
Nu 11 (*)
Nu 11 (*)

v

V

b

B
N

n
m

M

,

<
>

?

Notes:
(*) Refer to "Extended Functions " in this section.
(**) Refer to "Special Hand 1 i ng " in this section.

Character Codes (Part 2 of 2)

4-20

Al t

84-Key Keyboard

-1
Space
-1

(*)
-1
Null(*)
Null(*)
Null(*)
Nul1(*)
Null(*)
Null(*)
Null(*)

The following table lists keys that have meaning only in Num
Lock, Shift, or Ctrl states. The Shift key temporarily reverses the
current Num Lock state.
Key

Num
Lock

91
92

7
4

93
96
97
98
99
101

Alt

Ctrl

Home (*)
.... (*)

-1
-1

Clear Screen
Reverse Word

1

End (* )

-1

Erase to EOL

8
5

t

(* )

2

~

0
9

Ins
Page Up (*)

-1
-1
-1
-1
-1

102

6

....

-1

-1
-1
-1
-1
Top of Text
and Home
Advance Word

103

3

Pa~e

Down

-1

Erase to EOS

-

Delete (*,**)
Sys Request

(**)

104
105
106

+

Base Case

-1

(*)
(*)

(" )

+

(*)

-1
-1

(* )
(* )

(*)

(*)
(**)

-1
-1

Notes:
(*) Refer to "Extended Functions " in this section.
(**) Refer to "Special Hand 1 i ng " in this section.

Special Character Codes

Extended Functions
For certain functions that cannot be represented by a standard
ASCII code, an extended code is used. A character code of 000
(nUll) is returned in AL. This indicates that the system or
application program should examine a second code, which will
indicate the actual function. Usually, but not always, this second
code is the scan code of the primary key that was pressed. This
code is returned in AH.

84-Key Keyboard

4-21

The following table is a list of the extended codes and their
functions.
Second
Code

3
15
16-25
30-38
44-50
59-68
71
72

73
75
77

79
80
81
82
83
84-93
94-103
104-113
114
115
116
117
118
119
120-131
132

Function
Nul Character
I+- (Back-tab)
Alt Q, W, E, R, T, Y, U, I, 0, P
Alt A, S, D, F, G, H, J, K, L
Alt Z, X, C, V, B, N, M
Fl to FlO Function Keys (Base Case)
Home
t (Cursor Up)
Page Up and Home Cursor
.- (Cursor Left)
-. (Cursor Right)
End
i (Cursor Down)
Page Down and Home Cursor
Ins (Insert)
Del (Delete)
Fll to F20 (Shift-Fl through Shift-FlO)
F21 to F30 (Ctrl-Fl through Ctrl-Fl0)
F31 to F40 (Alt-Fl through Alt-Fl0)
Ctrl PrtSc (Start/Stop Echo to Printer)
Ctrl .- (Reverse Word)
Ctrl -. (Advance Word)
Ctrl End (Erase to End of Line-EOL)
Ctrl PgDn (Erase to End of Screen-EOS)
Ctrl Home (Clear Screen and Home)
Alt 1,2, 3, 4, 5,6, 7,8, 9, 0, -, = keys 2-13
Ctrl PgUp (Top 25 Lines of Te~t and Cursor Home)

Keyboard Extended Functions

Shift States
Most shift states are handled within the keyboard routine, and are
not apparent to the system or application program. In any case,
the current status of active shift states is available by calling an
entry point in the BIOS keyboard routine. The following keys
result in altered shift states:

Shift: This key temporarily shifts keys 1 through 14, 16 through
28, 31 through 41, and 46 through 55, to uppercase (base case if
in Caps Lock state). Also, the Shift temporarily reverses the
Num Lock or non-Num Lock state of keys 91 through 93, 96, 98,
99, and 101 through 104.

4-22

84-Key Keyboard

Ctrl: This key temporarily shifts keys 3, 7, 12, 15, 17 through
28,31 through 39, 43, 46 through 52,91 through 93, and 101
through 103 to the Ctrl state. The Ctrl key is also used with the
Alt and Del keys to cause the system-reset function; with the
Scroll Lock key to cause the break function; and with the Num
Lock key to cause the pause function. The system-reset, break,
and pause functions are described under "Special Handling" later
in this section.
AU: This key temporarily shifts keys 1 through 13, 17 through
26, 31 through 39, and 46 through 52 to the Alt state. The Alt
key is also used with the Ctrl and Del keys to cause a system
reset.
The Alt key also allows the user to enter any character code from
1 to 255.
Note: Character codes 97-122 will display uppercase with Caps
Lock activated. The user holds down the Alt key and types the
decimal value of the characters desired on the numeric keypad
(keys 91 through 93, 96 through 99, and 101 through 103). The
Alt key is then released. If the number is greater than 255, a
modulo-256 value is used. This value is interpreted as a character
code and is sent through the keyboard routine to the system or
application program. Alt is handled internal to the keyboard
routine.
Caps Lock: This key shifts keys 17 through 26, 31 through 39,
and 46 through 52 to uppercase. When Caps Lock is pressed
again, it reverses the action. Caps Lock is handled internal to the
keyboard routine. When Caps Lock is pressed, it changes the
Caps Lock Mode indicator. If the indicator was on, it will go off;
and if it was off, it will go on.
ScroD Lock: When interpreted by appropriate application
programs, this key indicates that the cursor-control keys will
cause windowing over the text rather than moving the cursor.
When the Scroll Lock key is pressed again, it reverses the action.
The keyboard routine simply records the current shift state of the
Scroll Lock key. It is the responsibility of the application
program to perform the function. When Scroll Lock is pressed, it
changes the Scroll Lock Mode indicator. If the indicator was on,
it will go off; and if it was off, it will go on.

84- Key Keyboard

4-23

Nom Lock: This key shifts keys 91 through 93,96 through 99,
and 101 through 104 to uppercase. When Num Lock is pressed
again, it reverses the action. Num Lock is handled internal to the
keyboard routine. When Num Lock is pressed, it changes the
Num Lock Mode indicator. If the indicator was on, it will go off;
if it was off, it will go on.
If the keyboard Num Lock Mode indicator and the system get out

of synchronization, pressing the key combination of Shift and
Num Lock will synchronize them. This key combination changes
the Num Lock bit in the keyboard memory, but sends only the
scan code for the Shift key to the system.
Shift Key Priorities and Combinations: If combinations of the
Alt, Ctrl, and Shift keys are pressed and only one is valid, the
priority is as follows: the Alt key is first, the Ctrl key is second,
and the Shift key is third. The only valid combination is Alt and
Ctrl, which is used in the system-reset function.

Special Handling
System Reset
The combination of the Alt, Ctrl, and Del keys results in the
keyboard routine that starts a system reset or restart. System
reset is handled by BIOS.

Break
The combination of the Ctrl and Break keys results in the
keyboard routine signaling interrupt hex lB. The extended
characters AL=hex 00, and AH=hex 00 are also returned.
Pause
The Pause key (Ctrl and Num Lock) causes the keyboard
interrupt routine to loop, waiting for any key except Num Lock to
be pressed. This provides a method of temporarily suspending an
operation, such as listing or printing, and then resuming the

4-24

84-Key Keyboard

operation. The method is not apparent to either the system or the
application program. The key stroke used to resume operation is
discarded. Pause is handled internal to the keyboard routine.

Print Screen
The PrtSc key results in an interrupt invoking the print-screen
routine. This routine works in the alphameric or graphics mode,
with unrecognizable characters printing as blanks.

System Request
When the System Request (SysReq) key is pressed, a hex 8500 is
placed in AX, and an interrupt hex 15 is executed. When the
SysReq key is released, a hex 8501 is placed in AX, and another
interrupt hex 15 is executed. If an application is to use System
Request, the following rules must be observed:
Save the previous address.
Overlay interrupt vector hex 15.
Check AH for a value of hex 85:
If yes, process may begin.
If no, go to previous address.

The application program must preserve the value in all registers,
except AX, upon return. System Request is handled internal to
the keyboard routine.

Other Characteristics
The keyboard routine does its own buffering, and the keyboard
buffer is large enough to support entries by a fast typist.
However, if a key is pressed when the buffer is full, the key will
be ignored and the "alarm" will sound.

84-Key Keyboard

4-25

The keyboard routine also suppresses the typematic action of the
following keys: Ctrl, Shift, Alt, Num Lock, Scroll Lock, Caps
Lock, and Ins.
During each interrupt 09H from the keyboard, an interrupt 15H,
function (AH)=4FH is generated by the BIOS after the scan
code is read from the keyboard adapter. The scan code is passed
in the (AL) register with the carry flag set. This is to allow an
operating system to intercept each scan code prior to its being
handled by the interrupt 09H routine, and have a chance to
change or act on the scan code. If the carry flag is changed to 0
on return from interrupt 15H, the scan code will be ignored by
the interrupt handler.

4-26

84-Key Keyboard

Keyboard Layouts
The keyboard has six different layouts:
•

French

•

German

•

Italian

•

Spanish

•

U.K. English

•

U.S. English

The following pages show the six keyboard layouts.

84-Key Keyboard

4-27

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4-30

84-Key Keyboard

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4-32

84-Key Keyboard

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Length: 503 millimeters (19.8 inches)

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Depth: 213 millimeters (8.4 inches)

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Height: 58 millimeters (2.3 inches)

Weight
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2.8 kilograms (6.2 pounds)

4-34

84-Key Keyboard

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lOl/102-Key Keyboard Description
The keyboard has 101 keys (102 in countries outside the U. S.).
At system power-on, the keyboard monitors the signals on the
'clock' and 'data' lines and establishes its line protocol. A
bidirectional serial interface in the keyboard converts the 'clock'
and' data' signals and sends this information to and from the
keyboard through the keyboard cable.

4-36

101/102-Key Keyboard

Cabling
The keyboard cable connects to the system with a 5-pin DIN
connector, and to the keyboard with a 6-position SDL connector.
The following table shows the pin configuration and signal
assignments.

1

/7!\~
ABCEDF

SOL Connector

DIN Connector

DIN Connector
Pins
1
2

3

4
5
Shield

SDl Connector
Pins

Signal Name

Signal Type

D
B
F
C
E
A
Shield

+KBD ClK
+KBD DATA
Reserved
Ground
+5.0 Vdc
Not used
Frame Ground

Input/Output
Input/Output
Power
Power

Sequencing Key-Code Scanning
The keyboard detects all keys pressed, and sends each scan code
in the correct sequence. When not serviced by the system, the
keyboard stores the scan codes in its buffer.

lOl/102-Key Keyboard

4-37

Keyboard Buffer
A 16-byte first-in-first-out (FIFO) buffer in the keyboard stores
the scan codes until the system is ready to receive them.
A buffer-overrun condition occurs when more than 16 bytes are
placed in the keyboard buffer. An overrun code replaces the 17th
byte. If more keys are pressed before the system allows keyboard
output, the additional data is lost.
When the keyboard is allowed to send data, the bytes in the
buffer will be sent as in normal operation, and new data entered is
detected and sent. Response codes do not occupy a buffer
position.
If keystrokes generate a multiple-byte sequence, the entire

sequence must fit into the available buffer space or the keystroke
is discarded and a buffer-overrun condition occurs.

Keys
With the exception of the Pause key, all keys are make/break.
The make scan code of a key is sent to the keyboard controller
when the key is pressed. When the key is released, its break scan
code is sent.
Additionally, except for the Pause key, all keys are typematic.
When a key is pressed and held down, the keyboard sends the
make code for that key, delays 500 milliseconds ± 20%, and
begins sending a make code for that key at a rate of 10.9
characters per second ± 20%. The typematic rate and delay can
be modified (see "Set Typematic Rate/Delay (Hex F3)" on
page 4-45).
If two or more keys are held down, only the last key pressed

repeats at the typematic rate. Typematic operation stops when
the last key pressed is released, even if other keys are still held
down. If a key is pressed and held down while keyboard
transmission is inhibited, only the first make code is stored in the
buffer. This prevents buffer overflow as a result of typematic
action.

4-38

101/102-Key Keyboard

Note: Scan code set 3 allows key types to be changed by the
system. See "Scan Code Tables (Set 3)" on page 4-58 for the
default settings. Commands to change the default settings are
listed in "Commands from the System" on page 4-40.

Power-On Routine
The following activities take place when power is first applied to
the keyboard.

Power-On Reset
The keyboard logic generates a 'power-on reset' signal (paR)
when power is first applied to the keyboard. paR occurs a
minimum of 150 milliseconds and a maximum of 2.0 seconds
from the time power is first applied to the keyboard.

Basic Assurance Test
The basic assurance test (BAT) consists of a keyboard processor
test, a checksum of the read-only memory (ROM), and a
random-access memory (RAM) test. During the BAT, activity on
the 'clock' and 'data' lines is ignored. The LEDs are turned on
at the beginning and off at the end of the BAT. The BAT takes a
minimum of 300 milliseconds and a maximum of 500
milliseconds. This is in addition to the time required by the paR.
Upon satisfactory completion of the BAT, a completion code (hex
AA) is sent to the system, and keyboard scanning begins. If a
BAT failure occurs, the keyboard sends an error code to the
system. The keyboard is then disabled pending command input.
Completion codes are sent between 450 milliseconds and 2.5
seconds after paR, and between 300 and 500 milliseconds after a
Reset command is acknowledged.
Immediately following paR, the keyboard monitors the signals on
the keyboard 'clock' and 'data' lines and sets the line protocol.

lOl/102-Key Keyboard

4-39

Commands from the System
The following table shows the commands that the system may
send and their hexadecimal values.
Command
Set/Reset Status Indicators
Echo
Invalid Command
Select Alternate Scan Codes
Inval id Command
Read ID
Set Typematic Rate/Delay
Enable
Default Disable
Set Default
Set All Keys - Typematic
- Make/Break
- Make
- Typematic/Make/Break
Set Key Type - Typematic
- Make/Break
- Make
Resend
Reset

Hex Value
ED
EE

EF
FO
Fl

F2

F3
F4
F5
F6
F7
F8
F9

FA
FB
FC
FD
FE
FF

The commands may be sent to the keyboard at any time. The
keyboard will respond within 20 milliseconds, except when
performing the basic assurance test (BAT), or executing a Reset
command.
Note:

Mode 1 will accept only the 'reset' command.

The commands are described below, in alphabetic order. They
have different meanings when issued by the keyboard (see
"Commands to the System" on page 4-47).

Default Disable (Hex F5)
The Default Disable command resets all conditions to the
power-on default state. The keyboard responds with ACK, clears
its output buffer, sets the default key types (scan code set 3
operation only) and typematic rate/delay, and clears the last
typematic key. The keyboard stops scanning, and awaits further
instructions.

4-40

lOl/102-Key Keyboard

Echo (Hex EE)
Echo is a diagnostic aid. When the keyboard receives this
command, it issues a hex EE response and, if the keyboard was
previously enabled, continues scanning.

Enable (Hex F4)
Upon receipt of this command, the keyboard responds with ACK,
clears its output buffer, clears the last typematic key, and starts
scanning.

Invalid Command (Hex EF and Fl)
Hex EF and hex Fl are invalid commands and are not supported.
If one of these is sent, the keyboard does not acknowledge the

command, but returns a Resend command and continues in its
prior scanning state. No other activities occur.

Read ID (Hex F2)
This command requests identification information from the
keyboard. The keyboard responds with ACK, discontinues
scanning, and sends the two keyboard ID bytes. The second byte
must follow completion of the first by no more than 500
microseconds. After the output of the second ID byte, the
keyboard resumes scanning.

Resend (Hex FE)
The system sends this command when it detects an error in any
transmission from the keyboard. It is sent only after a keyboard
transmission and before the system allows the next keyboard
output. When a Resend is received, the keyboard sends the
previous output again (unless the previous output was Resend, in
which case the keyboard sends the last byte before the Resend
command).

lOl/102-Key Keyboard

4-41

Reset (Hex FF)
The system issues a Reset command to start a program reset and a
keyboard internal self test. The keyboard acknowledges the
command with an ACK and ensures the system accepts ACK
before executing the command. The system signals acceptance of
ACK by raising the 'clock' and 'data' lines for a minimum of
500 microseconds. The keyboard is disabled from the time it
receives the Reset command until ACK is accepted, or until
another command is sent that overrides the previous command.
Following acceptance of ACK, the keyboard is re-initialized and
performs the BAT. After returning the completion code, the
keyboard defaults to scan code set 2.

Select Alternate Scan Codes (Hex FO)
This command instructs the keyboard to select one of three sets
of scan codes. The keyboard acknowledges receipt of this
command with ACK, clears both the output buffer and the
typematic key (if one is active). The system then sends the
option byte and the keyboard responds with another ACK. An
option byte value of hex 01 selects scan code set 1, hex 02 selects
set 2, and hex 03 selects set 3.
An option byte value of hex 00 causes the keyboard to
acknowledge with ACK and send a byte telling the system which
scan code set is currently in use.
After establishing the new scan code set, the keyboard returns to
the scanning state it was in before receiving the Select Alternate
Scan Codes command.

4-42

lOl/102-Key Keyboard

Set All Keys (Hex F7, F8, F9, FA)
These commands instruct the keyboard to set all keys to the type
listed below:
Hex Value
F7
F8
F9
FA

Command
Set
Set
Set
Set

All
All
All
All

Keys
Keys
Keys
Keys

-

Typematic
Make/Break
Make
Typematic/Make/Break

The keyboard responds with ACK, clears its output buffer, sets
all keys to the type indicated by the command, and continues
scanning (if it was previously enabled). Although these
commands can be sent using any scan code set, they affect only
scan code set 3 operation.

Set Default (Hex F6)
The Set Default command resets all conditions to the power-on
default state. The keyboard responds with ACK, clears its output
buffer, sets the default key types (scan code set 3 operation only)
and typematic rate/delay, clears the last typematic key, and
continues scanning.

Set Key Type (Hex FB, Fe, FD)
These commands instruct the keyboard to set individual keys to
the type listed below:
Hex Value
FB
FC
FD

Command
Set Key Type - Typematic
Set Key Type - Make/Break
Set Key Type - Make

The keyboard responds with ACK, clears its output buffer, and
prepares to receive key identification. Key identification is
accomplished by the system identifying each key by its scan code
value as defined in scan code set 3. Only scan code set 3 values
are valid for key identification. The type of each identified key is
set to the value indicated by the command.

lOl/102-Key Keyboard

4-43

These commands can be sent using any scan code set, but affect
only scan code set 3 operation.

Set/Reset Status Indicators (Hex ED)
Three status indicators on the keyboard- Num Lock, Caps
Lock, and Scroll Lock-are accessible by the system. The
keyboard activates or deactivates these indicators when it receives
a valid command-code sequence from the system. The command
sequence begins with the command byte (hex ED). The keyboard
responds to the command byte with ACK, discontinues scanning,
and waits for the option byte from the system. The bit
assignments for this option byte are as follows:
Bit
0
1
2

3-7

Indicator
Scro 11 Lock Indicator
Num Lock Indicator
Caps Lock Indicator
Reserved (must be Os)

If a bit for an indicator is set to 1, the indicator is turned on. If a

bit is set to 0, the indicator is turned off.
The keyboard responds to the option byte with ACK, sets the
indicators and, if the keyboard was previously enabled, continues
scanning. The state of the indicators will reflect the bits in the
option byte and can be activated or deactivated in any
combination. If another command is received in place of the
option byte, execution of the Set/Reset Mode Indicators
command is stopped, with no change to the indicator states, and
the new command is processed.
Immediately after power-on, the lights default to the Off state. If
the Set Default and Default Disable commands are received, the
lamps remain in the state they were in before the command was
received.

4-44

lOl/102-Key Keyboard

Set Typematic Rate/Delay (Hex F3)
The system issues the Set Typematic Rate/Delay command to
change the typematic rate and delay. The keyboard responds to
the command with ACK, stops scanning, and waits for the system
to issue the rate/ delay value byte. The keyboard responds to the
rate/ delay value byte with another ACK, sets the rate and delay
to the values indicated, and continues scanning (if it was
previously enabled). Bits 6 and 5 indicate the delay, and bits 4, 3,
2,1, and 0 (the least-significant bit) the rate. Bit 7, the
most-significant bit, is always O. The delay is equal to 1 plus the
binary value of bits 6 and 5, multiplied by 250 milliseconds ±
20%.
The period (interval from one typematic output to the next) is
determined by the following equation:
Period = (8 + A) X (2B) X 0.00417 seconds.
where:
A = binary value of bits 2, 1, and o.
B = binary value of bits 4 and 3.

IOI/I02-Key Keyboard

4-45

The typematic rate (make codes per second) is 1 for each period
.
and are listed in the following table.
Bit

Typematic
Rate ± 20%

Bit

Typematic
Rate ± 20%

00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111

30.0
26.7
24.0
21.8
20.0
18.5
17.1
16.0
15.0
13.3
12.0
10.9
10.0
9.2
8.0
8.0

10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111

7.5
6.7
6.0
5.5
5.0
4.6
4.3
4.0
3.7
3.3
3.0
2.7
2.5
2.3
2.1
2.0

The default values for the system keyboard are as follows:
Typematic rate = 10.9 characters per second ± 20%.
Delay = 500 milliseconds

± 20%.

The execution of this command stops without change to the
existing rate if another command is received instead of the
rate/delay value byte.

4-46

lOl/102-Key Keyboard

Commands to the System
The following table shows the commands that the keyboard may
send to the system, and their hexadecimal values.
Command

Hex Value

Key Detection Error/Overrun
Keyboard ID
BAT Completion Code
BAT Failure Code
Echo
Acknowledge (ACK)
Resend
Key Detection Error/Overrun

00 (Code Sets 2 and 3 )
83AB
AA
FC
EE
FA
FE
FF (Code Set l)

The commands the keyboard sends to the system are described
below, in alphabetic order. They have different meanings when
issued by the system (see "Commands from the System" on
page 4-40).

Acknowledge (Hex FA)
The keyboard issues Acknowledge (ACK) to any valid input
other than an Echo or Resend command. If the keyboard is
interrupted while sending ACK, it discards ACK and accepts and
responds to the new command.

BAT Completion Code (Hex AA)
Following satisfactory completion of the BAT, the keyboard
sends hex AA. Any other code indicates a failure of the
keyboard.

BAT Failure Code (Hex FC)
If a BAT failure occurs, the keyboard sends this code,

discontinues scanning, and waits for a system response or reset.

Echo (Hex EE)
The keyboard sends this code in response to an Echo command.

lOl/102-Key Keyboard

4-47

Keyboard ID (Hex 83AB)
The Keyboard ID consists of 2 bytes, hex 83AB. The keyboard
responds to the Read ID with ACK, discontinues scanning, and
sends the 2 ID bytes. The low byte is sent first followed by the
high byte. Following output of Keyboard ID, the keyboard begins
scanning.

Key Detection Error (Hex 00 or FF)
The keyboard sends a key detection error character if conditions
in the keyboard make it impossible to identify a switch closure. If
the keyboard is using scan code set 1, the code is hex FF. For
sets 2 and 3, the code is hex 00.

Overrun (Hex 00 or FF)
An overrun character is placed in the keyboard buffer and
replaces the last code when the buffer capacity has been
exceeded. The code is sent to the system when it reaches the top
of the buffer queue. If the keyboard is using scan code set 1, the
code is hex FF. For sets 2 and 3, the code is hex 00.

Resend (Hex FE)
The keyboard issues a Resend command following receipt of an
invalid input or any input with incorrect parity. If the system
sends nothing to the keyboard, no response is required.

4-48

lOl/102-Key Keyboard

Keyboard Scan Codes
The following tables list the key numbers of the three scan code
sets and their hexadecimal values. The system defaults to scan set
2, but can be switched to set 1 or set 3 (see "Select Alternate
Scan Codes (Hex FO)" on page 4-42).

Scan Code Set 1
In scan code set 1, each key is assigned a base scan code and, in
some cases, extra codes to generate artificial shift states in the
system. The typematic scan codes are identical to the base scan
code for each key.

lOl/102-Key Keyboard

4-49

Scan Code Tables (Set 1)
The following keys send the codes as shown, regardless of any
shift states in the keyboard or the ~ystem. Refer to "Keyboard
Layouts" beginning on page 4-74 to determine the character
associated with each key number.
Key Number

Make Code

Break Code

1
2
3
4
5
6
7
8
9
10
11
12
13
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33

29
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
2B
3A
IE
IF
20

A9
82
83
84
85
86
87
88
89
8A
8B
8c
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
AB
BA
9E
9F
AO

*

4-50

~

101-key keyboard only.

lOl/102-Key Keyboard

Key Number
34
35
36
37
38
39
40
41
42 **
43
44
45 **
46
47
48
49
50
51
52
53
54
55
57
58
60
61
62
64
90
91
92
93
96
97
98
99
100
101
102
103
104
105
106
108
110
112
113
114
115
116
117
118
119

Make Code

Break Code

21
22
23
24
25
26
27
28
2B
lC
2A
56
2C
2D
2E
2F
30
31
32
33
34
35
36
lD
38
39
EO 38
EO 1D
45
47
4B
4F
48
4c
50
52
37
49
4D
51
53
4A
4E
EO lC
01
3B
3C
3D
3E
3F
40
41
42

Al
A2
A3
A4
A5
A6
A7
A8
AB
9C
AA
D6
AC
AD
AE
AF
BO
Bl
B2
B3
B4
B5
B6
9D
B8
B9
EO B8
EO 9D
C5
C7
CB
CF
C8
cc
DO
D2
B7
C9
CD
D1
D3
CA
CE
EO 9C
81
BB
BC
BD
BE
BF
CO
C1
C2

** 102-key keyboard only.

lOl/102-Key Keyboard

4-51

Key Number

Make Code

Break Code

120
121
122
123
125

43
44
57
58
46

C3
C4
D7
D8
C6

The remaining keys send a series of codes dependent on the state
of the various shift keys (Ctrl, Alt, and Shift), and the state of
Num Lock (On or Off). Because the base scan code is identical
to that of another key, an extra code (hex EO) has been added to
the base code to make it unique.
Key
No.

Base Case, or
Shift+Num Lock
Make/Break

75

EO 52
/EO D2
EO 53
/EO D3
EO 4B
/EO CB
EO 47
/EO C7
EO 4F
/EO CF
EO 48
/EO c8
EO 50
/EO DO
EO 49
/EO C9
EO 51
/EO Dl
EO 4D
/EO CD

76
79
80
81
83
84
85
86
89
~

Sh i ft Case
Make/Break

~

EO AA EO 52
/EO D2 EO 2A
EO AA EO 53
/EO D3 EO 2A
EO AA EO 4B
/EO CB EO 2A
EO AA EO 47
/EO C7 EO 2A
EO AA EO 4F
/EO CF EO 2A
EO AA EO 48
/EO c8 EO 2A
EO AA EO 50
/EO DO EO 2A
EO AA EO 49
/EO C9 EO 2A
EO AA EO 51
/EO Dl EO 2A
EO AA EO 4D
/EO CD EO 2A

Num Lock on
Make/Break
EO 2A EO 52
/EO D2 EO AA
EO 2A EO 53
/EO D3 EO AA
EO 2A EO 4B
/EO CB EO AA
EO 2A EO 47
/EO C7 EO AA
EO 2A EO 4F
/EO CF EO AA
EO 2A EO 48
/EO C8 EO AA
EO 2A EO 50
/EO DO EO AA
EO 2A EO 49
/EO C9 EO AA
EO 2A EO 51
/EO Dl EO AA
EO 2A EO 4D
/EO CD EO AA

If the left Shift key is held down, the AA/2A shift make
and break is sent with the other scan codes. If the right
Shift key is held down, B6/36 is sent. If both Shift
keys are down, both sets of codes are sent with the other
scan code.

4-52

10l/102-Key Keyboard

Key
No.

Scan Code Make/Break

Shift Case Make/Break

95

EO 35/EO B5

EO AA EO 35/EO B5 EO 2A

*

If the left Shift key is held down, the AA/2A shift make
and break is sent with the other scan codes. If the right
Shift key is held down, B6/36 is sent. If both Shift
keys are down, both sets of codes are sent with the other
scan code.

Key
No.

Scan Code
Make/Break

124

EO 2A EO 37
/EO B7 EO AA

Key No.
126

*

*

*

Ctrl Case, Shift Case
Make/Break

Make Code
El 10 45 El 90 C5

EO 37/EO B7

Alt Case
Make/Break
54/04

Ctrl Key Pressed
EO 46 EO C6

This key is not typematic. All associated scan codes
occur on the make of the key.

lOl/102-Key Keyboard

4-53

Scan Code Set 2
In scan code set 2, each key is assigned a unique 8-bit make scan
code, which is sent when the key is pressed. Each key also sends
a break code when the key is released. The break code consists of
2 bytes, the first of which is the break code prefix, hex FO; the
second byte is the same as the make scan code for that key. The
typematic scan code for a key is the same as the key's make code.

Scan Code Tables (Set 2)
The following keys send the codes shown, regardless of any shift
states in the keyboard or system. Refer to "Keyboard Layouts"
beginning on page 4-74 to determine the character associated
with each key number.
Key Number

Make Code

1
2
3
4
5
6
7
8
9
10
11
12
13
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

OE
16
IE
26
25
2E
36
3D
3E
46
45
4E
55
66
OD
15
lD
24
2D
2C
35
3C
43
44
4D
54
5B
5D
58
lC

*

4-54

*

101-key keyboard only.

lOl/102-Key Keyboard

Break Code
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO

OE
16
IE
26
25
2E
36
3D
3E
46
45
4E
55
66
OD
15
1D
24
2D
2C
35
3C
43
44
4D
54
5B
5D
58
lC

Key Number
32
33
34
35
36
37
38
39
40
41
42 **
43
44
45 **
46
47
48
49
50
51
52
53
54
55
57
58
60
61
62
64
90
91
92
93
96
97
98
99
100
101
102
103
104
105
106
108
110
112
113
114
115
116
117
118
119

Make Code
1B
23
2B
34
33
3B
42
4B
4c
52
50
5A
12
61
1A
22
21
2A
32
31
3A
41
49
4A
59
14
11
29
EO 11
EO 14
77
6C
6B
69
75
73
72
70
7C
70
74
7A
71
7B
79
EO 5A
76
05
06
04
OC
03
OB
83
OA

Break Code
FO 1B
FO 23
FO 2B
FO 34
FO 33
FO 3B
FO 42
FO 4B
FO 4c
FO 52
FO 50
FO 5A
FO 12
FO 61
FO 1A
FO 22
FO 21
FO 2A
FO 32
FO 31
FO 3A
FO 41
FO 49
FO 4A
FO 59
FO 14
FO 11
FO 29
EO FO 11
EO FO 14
FO 77
FO 6C
FO 6B
FO 69
FO 75
FO 73
FO 72
FO 70
FO 7C
FO 70
FO 74
FO 7A
FO 71
FO 7B
FO 79
EO FO 5A
FO 76
FO 05
FO 06
FO 04
FO OC
FO 03
FO OB
FO 83
FO OA

** 102-key keyboard only.

lOl/102-Key Keyboard

4-55

Key Number

Make Code

120
121
122
123
125

01
09
78
07
7E

Break Code
FO
FO
FO
FO
FO

01
09
78
07
7E

The remaining keys send a series of codes dependent on the state
of the various shift keys (Ctrl, Alt, and Shift), and the state of
Num Lock (On or Off). Because the base scan code is identical
to that of another key, an extra code (hex EO) has been added to
the base code to make it unique.
Key
No.

Base Case, or
Shift+Num Lock
Make/Break
EO
/EO
EO
/EO
EO
/EO
EO
/EO
EO
/EO
EO
/EO
EO
/EO
EO
/EO
EO
/EO
EO
/EO

75
76
79
80
81
83
84
85
86
89

*

4-56

70
FO
71
FO
6B
FO
6C
FO
69
FO
75
FO
72
FO
7D
FO
7A
FO
74
FO

70
71
6B
6C
69
75
72
7D
7A
74

Sh i ft Case
Make/Break
EO
/EO
EO
/EO
EO
/EO
EO
/EO
EO
/EO
EO
/EO
EO
/EO
EO
/EO
EO
/EO
EO
/EO

FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO

12
70
12
71
12
6B
12
6C
12
69
12
75
12
72
12
7D
12
7A
12
74

EO
EO
EO
EO
EO
EO
EO
EO
EO
EO
EO
EO
EO
EO
EO
EO
EO
EO
EO
EO

~

70
12
71
12
6B
12
6C
12
69
12
75
12
72
12
7D
12
7A
12
74
12

Num Lock on
Make/Break
EO 12 EO 70
/EO FO 70 EO FO
EO 12 EO 71
/EO FO 71 EO FO
EO 12 EO 6B
/EO FO 6B EO FO
EO 12 EO 6C
/EO FO 6C EO FO
EO 12 EO 69
/EO FO 69 EO FO
EO 12 EO 75
/EO FO 75 EO FO
EO 12 EO 72
/EO FO 72 EO FO
EO 12 EO 7D
/EO FO 7D EO FO
EO 12 EO 7A
/EO FO 7A EO FO
EO 12 EO 74
/EO FO 74 EO FO

12
12
12
12
12
12
12
12
12
12

If the left Shift key is held down, the FO 12/12 shift
make and break is sent with the other scan codes. If the
right Shift key is held down, FO 59/59 is sent. If both
Sh i ft keys are down, both sets of codes are sent with the
other scan code.

lOl/102-Key Keyboard

Key
No.

Scan Code Make/Break

95

EO 4A/EO FO 4A

"

Sh ift Case Make/Break

*

EO FO 12 4A/EO 12 FO 4A

If the 1eft Sh i ft key is held down, the FO 12/12 shift
make and break is sent with the other scan codes. If the
right Shift key is held down, FO 59/59 is sent. If both
Shift keys are down, both sets of codes are sent with the
other scan code.

Key
No.

Scan Code
Make/Break

Ctrl Case, Shift Case
Make/Break

Alt Case
Make/Break

124

EO 12 EO 7C
/EO FO 7C EO FO 12

EO 7C/EO FO 7C

84/FO 84

Key No.
126

*

*

Ctrl Key Pressed

Make Code
E1 14 77 E1 FO 14 FO 77

EO 7E EO FO 7E

This key is not typematic. All associated scan codes
occur on the make of the key.

lOl/102-Key Keyboard

4-57

Scan Code Set 3
In scan code set 3, each key is assigned a unique 8-bit make scan
code, which is sent when the key is pressed. Each key also sends
a break code when the key is released. The break code consists of
2 bytes, the first of which is the break-code prefix, hex FO; the
second byte is the same as the make scan code for that key. The
typematic scan code for a key is the same as the key's make code.
With this scan code set, each key sends only one scan code, and
no keys are affected by the state of any other keys.

Scan Code Tables (Set 3)
The following keys send the codes shown, regardless of any shift
states in the keyboard or system. Refer to "Keyboard Layouts"
beginning on page 4-74 to determine the character associated
with each key number.
Key Number

Make Code

1
2
3
4
5
6
7
8
9
10
11
12
13
15
16
17
18
19
20
21
22
23
24
25
26
27
28

OE
16
1E
26
25
2E
36
3D
3E
46
45
4E
55
66
OD
15
1D
24
2D
2C
35
3C
43
44
4D
54
5B

4-58

lO1/102-Key Keyboard

Break Code
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO

OE
16
1E
26
25
2E
36
3D
3E
46
45
4E
55
66
OD
15
1D
24
2D
2C
35
3C
43
44
4D
54
5B

Default Key State
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic

Key Number
29 *
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45 **
46
47
48
49
50
51
52
53
54
55
57
58
60
61
62
64
75
76
79
80
81
83
84
85
86
89
90
91
92
93
95
96
97
98

....

Make Code
5C
14
1C
1B
23
2B
34
33
3B
42
4B
4c
52
53
5A
12
13
1A
22
21
2A
32
31
3A
41
49
4A
59
11
19
29
39
58
67
64
61
6E
65
63
60
6F
6D
6A
76
6C
6B
69
77

75
73
72

Break Code
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO

5C
14
1C
1B
23
2B
34
33
3B
42
4B
4C
52
53
5A
12
13
1A
22
21
2A
32
31
3A
41
49
4A
59
11
19
29
39
58
67
64
61
6E
65
63
60
6F
6D
6A
76
6C
6B
69
77

75
73
72

Default Key State
Typematic
Make/Break
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Make/Break
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Make/Break
Make/Break
Make/Break
Typematic
Make only
Make only
Make only
Typematic
Typematic
Make only
Make only
Typematic
Typematic
Make only
Make only
Typematic
Make only
Make only
Make only
Make only
Make only
Make only
Make only
Make only

* 101-key keyboard only.
** 102-key keyboard only.

lOl/102-Key Keyboard

4-59

Key Number

Make Code

99
100
101
102
103
104
105
106
108
110
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126

70
7E
70
74
7A
71
84
7C
79
08
07
OF
17
1F
27
2F
37
3F
47
4F
56
5E
57
5F
62

4-60

lOl/102-Key Keyboard

Break Code
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO

70
7E
70
74
7A
71
84
7C
79
08
07
OF
17
1F
27
2F
37
3F
47
4F
56
5E
57
5F
62

Default Key State
Make only
Make only
Make only
Make only
Make only
Make only
Make only
Typematic
Make only
Make only
Make only
Make only
Make only
Make only
Make only
Make only
Make only
Make only
Make only
Make only
Make only
Make only
Make only
Make only
Make only

Clock and Data Signals
The keyboard and system communicate over the 'clock' and
'data' lines. The source of each of these lines is an
open-collector device on the keyboard that allows either the
keyboard or the system to force a line to an inactive (low) level.
When no communication is occurring, the 'clock' line is at an
active (high) level. The state of the 'data' line is held
active(high) by the keyboard.
When the system sends data to the keyboard, it forces the 'data'
line to an inactive level and allows the 'clock' line to go to an
active level.
An inactive signal will have a value of at least 0, but not greater
than +0.7 volts. A signal at the inactive level is a logical O. An
active signal will have a value of at least +2.4, but not greater
than +5.5 volts. A signal at the active level is a logical 1.
Voltages are measured between a signal source and the dc
network ground.
The keyboard 'clock' line provides the clocking signals used to
clock serial data to and from the keyboard. If the host system
forces the 'clock' line to an inactive level, keyboard transmission
is inhibited.
When the keyboard sends data to, or receives data from the
system, it generates the 'clock' signal to time the data. The
system can prevent the keyboard from sending data by forcing the
'clock' line to an inactive level; the 'data' line may be active or
inactive during this time.
During the BAT, the keyboard allows the 'clock' and 'data' lines
to go to an active level.

Data Stream
Data transmissions to and from the keyboard consist of an II-bit
data stream (Mode 2) sent serially over the 'data' line. A logical
1 is sent at an active (high) level. The following table shows the
functions of the bits.

lOl/102-Key Keyboard

4-61

Function

Bit
1
2
3
4
5
6
7

8
9

10
11

Start bit (always 0)
Data bit 0 (least-significant)
Data bit 1
Data bit 2
Data bit 3
Data bit 4
Data bit 5
Data bit 6
Data bit 7 (most-significant)
Parity bit (odd parity)
Stop bit (always 1)

The parity bit is either 1 or 0, and the 8 data bits, plus the parity
bit, always have an odd number of 1'so
Note: Mode 1 is a 9-bit data stream that does not have a
parity bit or stop bit and the start bit is always 1.

Keyboard Data Output
When the keyboard is ready to send data, it first checks for a
keyboard-inhibit or system request-to-send status on the 'clock'
and 'data' lines. If the 'clock' line is inactive (low), data is
stored in the keyboard buffer. If the 'clock' line is active (high)
and the 'data' line is inactive (request-to-send), data is stored in
the keyboard buffer, and the keyboard receives system data.
If the 'clock' and 'data' lines are both active, the keyboard sends

the 0 start bit, 8 data bits, the parity bit, and the stop bit. Data
will be valid before the trailing edge and beyond the leading edge
of the clock pulse. During transmission, the keyboard checks the
'clock' line for an active level at least every 60 milliseconds. If
the system lowers the 'clock' line from an active level after the
keyboard starts sending data, a condition known as line contention
occurs, and the keyboard stops sending data. If line contention
occurs before the leading edge of the 10th clock signal (parity
bit), the keyboard buffer returns the 'clock' and 'data' lines to
an active level. If contention does not occur by the 10th clock
signal, the keyboard completes the transmission. Following line
contention, the system mayor may not request the keyboard to
resend the data.

4-62

lOl/102-Key Keyboard

Following a transmission, the system can inhibit the keyboard
until the system processes the input, or until it requests that a
response be sent.

Keyboard Data Input
When the system is ready to send data to the keyboard, it first
checks to see if the keyboard is sending data. If the keyboard is
sending, but has not reached the 10th 'clock' signal, the system
can override the keyboard output by forcing the keyboard 'clock'
line to an inactive (low) level. If the keyboard transmission is
beyond the 10th 'clock' signal, the system must receive the
transmission.
If the keyboard is not sending, or if the system elects to override

the keyboard's output, the system forces the keyboard 'clock'
line to an inactive level for more than 60 microseconds while
preparing to send data. When the system is ready to send the start
bit (the 'data' line will be inactive), it allows the 'clock' line to
go to an active (high) level.
The keyboard checks the state of the' clock' line at intervals of
no more than 10 milliseconds. If a system request-to-send (RTS)
is detected, the keyboard counts 11 bits. After the 10th bit, the
keyboard checks for an active level on the 'data' line, and if the
line is active, forces it inactive, and counts one more bit. This
action signals the system that the keyboard has received its data.
Upon receipt of this signal, the system returns to a ready state, in
which it can accept keyboard output, or goes to the inhibited state
until it is ready.
If the keyboard 'data' line is found at an inactive level following

the 10th bit, a framing error has occurred, and the keyboard
continues to count until the 'data' line becomes active. The
keyboard then makes the 'data' line inactive and sends a Resend.
Each system command or data transmission to the keyboard
requires a response from the keyboard before the system can send
its next output. The keyboard will respond within 20 milliseconds
unless the system prevents keyboard output. If the keyboard
response is invalid or has a parity error, the system sends the
command or data again. However, the two byte commands
require special handling. If hex F3 (Set Typematic Rate/Delay),

lOl/102-Key Keyboard

4-63

hex FO (Select Alternate Scan Codes), or hex ED (Set/Reset
Mode Indicators) have been sent and acknowledged, and the
value byte has been sent but the response is invalid or has a parity
error, the system will resend both the command and the value
byte.

Keyboard Encoding and Usage
The keyboard routine, provided by IBM in the ROM BIOS, is
responsible for converting the keyboard scan codes into what will
be termed Extended ASCII. The extended ASCII codes returned
by the ROM routine are mapped to the U.S. English keyboard
layout. Some operating systems may make provisions for
alternate keyboard layouts by providing an interrupt replacer,
which resides in the read/write memory. This section discusses
only the ROM routine.
Extended ASCII encomp-asses 1-byte character codes, with
possible values of 0 to 255, an extended code for certain extended
keyboard functions, and functions handled within the keyboard
routine or through interrupts.

Character Codes
The character codes described later are passed through the BIOS
keyboard routine to the system or application program. A "-1"
means the combination is suppressed in the keyboard routine.
The codes are returned in the AL register. See "Characters,
Keystrokes, and Color" later in this manual for the exact codes.

4-64

lOl/102-Key Keyboard

The following figure shows the keyboard layout and key
positions.

lOl/102-Key Keyboard

4-65

Key

Base Case

Uppercase

I

1
2
3
4
5
6
7
8
9
10
11
12
13
15

~

1
2
3
4
5
6
7
8

!
@

#

$
%
1\

&

*
(
)

9

0
-

+

=

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30 Caps
Lock
31
32
33
34
35
36
37
38
39
40
41
43
44 Sh i ft
(Left )
46
47
48

Backs)ace
(008
-+1 (009)
q

Backspace
(008)
I~ (*)
Q

w

w

e
r
t
y
u
i

E
R
T
y

U
1

0

0

p

P
{
}

{
}

\

-1

1

-1

a
s
d
f

A
S
D
F
G
H

9

h
j

J

k

K
L

I
;

:

I

CR(013)
-1

"

CR(013)
-1

z

x
c

Z

X
C

Ctrl
-1
-1
Nul(OOO) (* )
-1
-1
-1
RS(030)
-1
-1
-1
-1
US(031)
-1
Del(12])

(* )
(* )
(* )
(*)
(* )
(*)
(* )
(*)
(* )
(*)
(*)
(*)
(*)
(*)

(*)
DCl(Ol])
ETB(023)
ENQ(005)
DC2(018)
DC4(020)
EM(025)
NAK( 021)
HT( 009)
SI(015)
DLE(016)
Esc(02])
GS(029)
FS(028)
-1

(*)
(*)
(*)
(*)
(*)
(*)
(*)
(*)
(*)
(*)
(*)
(*)
(*)
(*)
-1

SOH(OOl )
DC3(019)
EOT(004)
ACK(006)
BEL(OO])
BS(008)
LF(010)
VT (011 )
FF(012)
-1
-1
LF(010)
-1

(*)
(*)
(*)
(* )
(*)
(* )
(*)
(* )
(*)
(*)
(* )
(*)
-1

SUB(026)
CAN(024)
ETX(003)

( )
( )
( )

Notes:
i*) Refer to "Extended Functions" in this section.
(,,*) Refer to "Special Handl ing" in this section.
Character Codes (Part 1 of 2)

4-66

lOl/102-Key Keyboard

Alt

Key
49
50
51
52
53
54
55
57 Sh i ft
(Right)
58 Ctrl
(Left )
60 Alt
(Left )
61
62 Alt
(Right)
64 Ctrl
(Right)
90 Num
Lock
95
100
105
106
108
110
112
113
114
115
116
117
118
119
120
121
122
123
125 Scro 11
Lock
126

Base Case

Uppercase

Ctrl

Alt

/

-1

?
-1

-1
-1
-1

(*)
(* )
(* )
(*)
(*)
(* )
(*)
-1

-1

-1

-1

-1

-1

-1

-1

-1

Space
-1

Space

Space

-1

-1

Space
-1

-1

-1

-1

-1

-1

-1

-1

-1

/

/

v

V

b

B
N

n
m

SYN(022)
STX(002)
SO(014)
CR(013)
-1

M

,

<
>

Enter
Esc
Nu 11 (* )
Null (*)
Nu 11 (*)
Nu 11 (* )
Nu 11 (* )
Nu 11 (*)
Null (*)
Nu 11 (* )
Null (*)
Nu 11 (* )
Null (* )
Nu 11 (*)
-1

Enter
Esc
Nu 11 (*)
Nu 11 (*)
Nu 11 (*)
Null (*)
Nu 11 (*)
Null (*)
Nu 11 (*)
Null (*)
Nu 11 (*)
Null (*)
Null (*)
Nu 11 (*)
-1

(* )
(*)
(* )
(* )
LF(010)
Esc
Nu 11 (* )
Nu 11 (*)
Nu 11 (*)
Nu 11 (* )
Nu 11 (*)
Nu 11 (* )
Nu 11 (* )
Nu 11 (* )
Nu 11 (* )
Nu 11 (*)
Nu 11 (* )
Nu 11 (*)
-1

Pause(**)

Pause(**)

Break(**)

*

*

-

-

+

+

(*)
(*)
(* )
(*)
(* )
(* )
Null (*)
Null(*)
Null(*)
Null(*)
Nul1(*)
Null (*)
Null(*)
Null(*)
Null(*)
Null(*)
Null (*)
Null(*)
-1
Pause(**)

Notes:
(*) Refer to "Extended Funct ions" in this section.
(**) Refer to "Special Hand 1i ng " in this section.
Character Codes (Part 2 of 2)

lOl/102-Key Keyboard

4-67

The following table lists keys that have meaning only in Num
Lock, Shift, or Ctrl states. The Shift key temporarily reverses the
current Num Lock state.
Key

Num
Lock

91
92
93
96
97
98
99
101

7
4
1
8
5
2
0
9

102

6

....

(*)

-1

103

3

Pajile Down

-1

104

Base Case
Home (*)

+- (*)

End (*)
(*)
(*)
~ (*)
Ins
Page Up (*)

t

Alt

Ctrl

-1
-1
-1
-1
-1
-1
-1
-1

Clear Screen
Reverse Word(*)
Erase to EOL(*)
(*)
(*)
(*)
(* )
Top of Text
and Home
Advance Word
(*)
Erase to EOS
(*)
(**)

(" )

Delete (*,**)

(**)

Notes:
(*) Refer to "Extended Functions " in this section.
(**) Refer to "Special Hand 1 i ng " in this section.

Special Character Codes

Extended Functions
For certain functions that cannot be represented by a standard
ASCII code, an extended code is used. A character code of 000
(null) is returned in AL. This indicates that the system or
application program should examine a second code, which will
indicate the actual function. Usually, but not always, this second
code is the scan code of the primary key that was pressed. This
code is returned in AH.

4-68

lOl/102-Key Keyboard

The following table is a list of the extended codes and their
functions.
Second
Code
1

3
14
15
16-25
26-28
30-38
39-41
43
44-50
51-53

55

59-68
71
72
73
74
75
76
77
78
79
80
81
82
83
84-93
94-103
104-113
114
115
116
117
118
119
120-131
132
133-134
135-136
137-138
139-140
141
142
143
144
145
146
147
148
149
150

Function
Alt
Esc
Nul Character
A1t
Backspace
I+- (Back-tab)
Alt Q, W, E, R, T, Y, U, I, 0, P
Alt
[1 ~
Alt A, S, D, F, G, H, J, K, L
A1t

I

I

A It
Alt
Z, " X, C, V, B, N, M

A1t

,

Ctr 1

Keypad

.

/

Alt
Keypad *
F1 to FlO Function Keys (Base Case)
Home
t (Cursor Up)
Page Up
Alt
Keypad.... (Cursor Left)
Center Cursor
-. (Cursor Right)
Alt
Keypad +
End
~ (Cursor Down)
Page Down
Ins (Insert)
Del (Delete)
Shift F1 to FlO
Ctrl F1 to FlO
Alt
F1 to FlO
Ctrl PrtSc (Start/Stop Echo to Printer)
Ctrl .... (Reverse Word)
Ctrl -. (Advance Word)
Ctrl End (Erase to End of Line-EOL)
Ctrl PgDn (Erase to End of Screen-EOS)
Ctrl Home (Clear Screen and Home)
Alt I, 2, 3, 4, 5, 6, 7, 8, 9, 0, -, = keys 2-13
Ctrl PgUp (Top 25 Lines of Text and Cursor Home)
F 11, F 12
Shift F11, F12
Ctrl F11, F12
Alt
F11, F12
Ctr 1 Up/8
Ctrl KeypadCtrl Keypad 5
Ctrl Keypad +
Ctrl Down/2
Ctrl Ins/O
Ctrl Del/.
Ctrl Tab
Ctrl Keypad /

*

Keyboard Extended Functions (Part 1 of 2)

tOt/t02-Key Keyboard

4-69

Second
Code

151
152
153
155
157
159
160
161
162
163
164
165
166

Function
A1t
Alt
Al t
A1t
Al t
A1t
AIt
A1t
AIt
Alt
A1t
Alt
Alt

Home
Up
Page Up
Left
Right
End
Down
Page Down
Insert
Delete
Keypad /
Tab
Enter

Keyboard Extended Functions (Part 2 of 2)

Shift States
Most shift states are handled within the keyboard routine, and are
not apparent to the system or application program. In any case,
the current status of active shift states is available by calling an
entry point in the BIOS keyboard routine. The following keys
result in altered shift states:
Shift: This key temporarily shifts keys 1 through 13, 16 through
29,31 through 41, and 46 through 55, to uppercase (base case if
in Caps Lock state). Also, the Shift temporarily reverses the
Num Lock or non-Num Lock state of keys 91 through 93,96,98,
99, and 101 through 104.
Ctrl: This key temporarily shifts keys 3, 7,12,15 through 29,31
through 39,43,46 through 52, 75 through 89,91 through 93,95
through 108, 112 through 124 and 126 to the Ctrl state. The Ctrl
key is also used with the Alt and Del keys to cause the
system-reset function; with the Scroll Lock key to cause the break
function; and with the Num Lock key to cause the pause function.
The system-reset, break, and pause functions are described under
"Special Handling" later in this section.

4-70

lOl/102-Key Keyboard

Alt: This key temporarily shifts keys 1 through 29,31 through
43,46 through 55,75 through 89, 95, 100, and 105 through 124
to the Alt state. The Alt key is also used with the Ctrl and Del
keys to cause a system reset.

The Alt key also allows the user to enter any character code from
1 to 255. The user holds down the Alt key and types the decimal
value of the characters desired on the numeric keypad (keys 91
through 93, 96 through 99, and 101 through 103). The Alt key is
then released. If the number is greater than 255, a modulo-256
value is used. This value is interpreted as a character codl:. and is
sent through the keyboard routine to the system or application
program. Alt is handled internal to the keyboard routine.
Caps Lock: This key shifts keys 17 through 26, 31 through 39,
and 46 through 52 to uppercase. When Caps Lock is pressed
again, it reverses the action. Caps Lock is handled internal to the
keyboard routine. When Caps Lock is pressed, it changes the
Caps Lock Mode indicator. If the indicator was on, it will go off;
and if it was off, it will go on.
Scroll Lock: When interpreted by appropriate application
programs, this key indicates that the cursor-control keys will
cause windowing over the text rather than moving the cursor.
When the Scroll Lock key is pressed again, it reverses the action.
The keyboard routine simply records the current shift state of the
Scroll Lock key. It is the responsibility of the application
program to perform the function. When Scroll Lock is pressed, it
changes the Scroll Lock Mode indicator. If the indicator was on,
it will go off; and if it was off, it will go on.
Nom Lock: This key shifts keys 91 through 93,96 through 99,
and 101 through 104 to uppercase. When Num Lock is pressed
again, it reverses the action. Num Lock is handled internal to the
keyboard routine. When Num Lock is pressed, it changes the
Num Lock Mode indicator. If the indicator was on, it will go off;
if it was off, it will go on.
Shift Key Priorities and Combinations: If combinations of the
Alt, Ctrl, and Shift keys are pressed and only one is valid, the
priority is as follows: the Alt key is first, the Ctrl key is second,
and the Shift key is third. The only valid combination is Alt and
Ctrl, which is used in the system-reset function.

lOl/102-Key Keyboard

4-71

Special Handling
System Reset
The combination of any Alt, Ctrl, and Del keys results in the
keyboard routine that starts a system reset or restart. System
reset is handled by BIOS.

Break
The combination of the Ctrl and Pause/Break keys results in the
keyboard routine signaling interrupt hex 1B. The extended
characters AL=hex 00, and AH=hex 00 are also returned.

Pause
The Pause key causes the keyboard interrupt routine to loop,
waiting for any character or function key to be pressed. This
provides a method of temporarily suspending an operation, such
as listing or printing, and then resuming the operation. The
method is not apparent to either the system or the application
program. The key stroke used to resume operation is discarded.
Pause is handled internal to the keyboard routine.

Print Screen
The Print Screen key results in an interrupt invoking the
print-screen routine. This routine works in the alphameric or
graphics mode, with unrecognizable characters printing as blanks.

System Request
When the System Request (Alt and Print Screen) key is pressed, a
hex 8500 is placed in AX, and an interrupt hex 15 is executed.
When the SysRq key is released, a hex 8501 is placed in AX, and
another interrupt hex 15 is executed. If an application is to use
System Request, the following rules must be observed:

4-72

lOl/102-Key Keyboard

Save the previous address.
Overlay interrupt vector hex 15.
Check AH for a value of hex 85:
If yes, process may begin.
If no, go to previous address.

The application program must preserve the value in all registers,
except AX, upon return. System Request is handled internal to
the keyboard routine.
Other Characteristics

The keyboard routine does its own buffering, and the keyboard
buffer is large enough to support entries by a fast typist.
However, if a key is pressed when the buffer is full, the key will
be ignored and the "alarm" will sound.
The keyboard routine also suppresses the typematic action of the
following keys: Ctrl, Shift, Alt, Num Lock, Scroll Lock, Caps
Lock, and Ins.
During each interrupt hex 09 from the keyboard, an interrupt hex
15, function (AH)=hex 4F is generated by the BIOS after the
scan code is read from the keyboard adapter. The scan code is
passed in the (AL) register with the carry flag set. This is to
allow an operating system to intercept each scan code prior to its
being handled by the interrupt hex 09 routine, and have a chance
to change or act on the scan code. If the carry flag is changed to
o on return from interrupt hex 15, the scan code will be ignored
by the interrupt handler.

lOl/102-Key Keyboard

4-73

Keyboard Layouts
The keyboard is available in six layouts:
•

French

•

German

•

Italian

•

Spanish

• u.K. English
•

U.S. English

The various layouts are shown in alphabetic order on the
following pages. Nomenclature is on both the top and front face
of the keybuttons. The number to the upper right designates the
keybutton position.

4-74

lOl/102-Key Keyboard

French Keyboard

m
,.

o "
~

lOl/102-Key Keyboard

4-75

r

..j:::.
I

-.l
0'1

....
....
..........
....

~

Q

Q

~

I

~

'<

I

~

Q

I!

II~

Ilr I

i

g-.

§

i

~

Q

[

....
=
....

....
.........

=
N
I

E
~

g

a.
~
I

-..l
-..l

to NOI1::J3S

Spanish Keyboard

4-78

lOl/102-Key Keyboard

U.K. English Keyboard

lOl/102-Key Keyboard

4-79

U.S. English Keyboard

4-80

lOl/102-Key Keyboard

Specifications
The specifications for the keyboard follow.

Power Requirements
•
•

+5 Vdc ± 10%
Current cannot exceed 275 rnA

Size
•
•
•

Length: 492 millimeters (19.4 inches)
Depth: 210 millimeters (8.3 inches)
Height: 58 millimeters (2.3 inches), legs extended

Weight
2.25 kilograms (5.0 pounds)

lOl/102-Key Keyboard

4-81

Logic Diagram

"";" ":' '7

-r ":'

~

'":'

~

q~qqq!:lq!:l

..,. Cl_"' ... OO..,. ... "" ..... '"
"1M
__
_"' _
__
_

...

~~~~>'~>'>'>'>'>'>'>'>'>'>'

~~~~g;~~~~g;g;g;g;g;g;g;
~

~

~

c
a::

~

~o---<

~

+


W

~

::.:::

~

>
w

"A;~H·

Ig

~
~

~I~~

~

~

~

~

;!

;;

~

~

t.1E-

I~

,'t:

~

1-1E-

;;

;;

~

~

HE~

~
::l

;:1'

;;

~ ~~
~ ~

~:
~~

~T

~
~

t

~t.

t--1H"
~

';'
~

4-82

I

H"

1-1~E-

~

l:!

~

-'I

=

N

lOl/102-Key Keyboard

';'
~
~

::.:::
~

o
,..
.......
,..
o
,..

SECTION 5. SYSTEM BIOS

System BIOS Usage ............................ 5-3
Parameter Passing ........................ 5-4
Vectors with Special Meanings .............. 5-6
Other Read/Write Memory Usage ........... 5-9
BIOS Programming Hints ................. 5-10
Adapters with System-Accessible ROM
Modules ............................. 5-12
Additional System Board ROM Modules ..... 5-13
Quick Reference .............................. 5-14

System BIOS

5-1

Notes:

5-2

System BIOS

System BIOS Usage
The basic input/output system (BIOS) resides in ROM on the
system board and provides low level control for the major I/O
devices in the system and provides system services, such as
time-of-day and memory size determination. Additional ROM
modules may be placed on option adapters to provide device-level
control for that option adapter. BIOS routines enable the
assembly language programmer to perform block (disk or
diskette) or character-level I/O operations without concern for
device address and characteristics.
If the sockets labeled V17 and V37 on the system board are

empty, additional ROM modules may be installed in these
sockets. During POST, a test is made for valid code at this
location, starting at address hex EOOOO and ending at hex EFFFF.
More information about these sockets may be found under
"Additional System Board ROM Modules" on page 5-13.
The goal of the BIOS is to provide an operational interface to the
system and relieve the programmer of concern about the
characteristics of hardware devices. The BIOS interface isolates
the user from the hardware, allowing new devices to be added to
the system, yet retaining the BIOS level interface to the device.
In this manner, hardware modifications and enhancements are not
apparent to user programs.
The IBM Personal Computer Macro Assembler manual and the
IBM Personal Computer Disk Operating System (DOS) manual
provide useful programming information related to this section.
A complete listing of the BIOS is given later in this section.
Access to the BIOS is through program interrupts of the
microprocessor in the real mode. Each BIOS entry point is
available through its own interrupt. For example, to determine
the amount of base RAM available in the system with the
microprocessor in the real mode, INT 12H invokes the BIOS
routine for determining the memory size and returns the value to
the caller.

System BIOS

5-3

Parameter Passing
All parameters passed to and from the BIOS routines go through
the 80286 registers. The prolog of each BIOS function indicates
the registers used on the call and return. For the memory size
example, no parameters are passed. The memory size, in lK
increments, is returned in the AX register.
If a BIOS function has several possible operations, the AH

register is used at input to indicate the desired operation. For
example, to set the time of day, the following code is required:

MOV
MOV
MOV
INT

AH,l
eX,HIGH COUNT
DX,LOW_COUNT
lAH

function is to set time-of-day
establish the current time
set the time

To read the time of day:

MOV
INT

AH,O
lAH

function is to read time-of-day
read the timer

The BIOS routines save all registers except for AX and the flags.
Other registers are modified on return only if they are returning a
value to the caller. The exact register usage can be seen in the
prolog of each BIOS function.

5-4

System BIOS

The following figure shows the interrupts with their addresses and
functions.
Int

o

Address

Name

12

0-3
4-7
8-B
C-F
10-13
14-17
18-1B
lC-1F
20-23
24-27
28-2B
2C-2F
30-33
34-37
38-3B
3C-3F
40-43
44-47
48-4B

Divide by Zero
Single Step
Nonmaskable
Breakpoint
Overflow
Print Screen
Reserved
Reserved
Time of Day
Keyboard
Reserved
Communications
Communications
Alternate Printer
Diskette
Printer
Video
Equipment Check
Memory

13
14
15

4C-4F
50-53
54-57

Di skette/O i sk
Communications
Cassette

16
17
18

58-5B
5C-5F
60-63
64-67
68-6B
6C-6F
70-73
74-77
78-7B
7C-7F

Keyboard
Printer
Resident BASIC
Bootstrap
Time of Day
Keyboard Break
Timer Tick
Video Initialization
Diskette Parameters
Video Graphics Chars

1
2

3

4
5
6
7
8
9

A

B
C
D
E
F

10
11

19

lA

1B

1C
1D
1E
1F

BIOS Entry
011
011
NMI I NT
Dll
D11

PRINT SCREEN
D11
D11

TIMER INT
KB INT

Dn
D11

D11
D11

DISK INT
D11
VIDEO 10
EQUIPMENT
MEMORY SIZE
DETERMINEDISKETTE 10
RS232 10CASSETTE
10/System
Extensions
KEYBOARD 10
PR I NTER To
F600:0000
BOOTSTRAP
TIME OF DAY
DUMMY RETURN
DUMMY-RETURN
VIDEO-PARMS
DISK BASE

o

80286-2 Program Interrupt Listing (Real Mode Only)

Note: For BIOS index, see the BIOS Quick Reference on page
5-14.

System BIOS

5-5

The following figure shows hardware, BASIC, and DOS reserved
interrupts.
Interrupt

Address

Function

20
21
22
23
24
25
26
27
28-3F
40-5F
60-67
68-6F
70

80-83
84-87
88-8B
8C-8F
90-93
94-97
98-9B
9C-9F
AO-FF
100-17F
180-19F
1AO-1BF
1CO-1C3

71

1C4-1C7
1C8-1CB
1CC-1CF
100-103
104-107

DOS program terminate
DOS function call
DOS terminate address
DOS Ctr1 Break exit address
DOS fatal error vector
DOS absolute disk read
DOS absolute disk write
DOS terminate, fix in storage
Reserved for DOS
Reserved for BIOS
Reserved for user program interrupts
Not used
IRQ 8 Realtime clock INT (BIOS entry
RTC INT)
IRQ 9 \BIOS entry RE DIRECT)
IRQ 10 (BIOS entry OIl)
IRQ 11 (BIOS entry 011)
IRQ 12 (BIOS entry 011)
IRQ 13 BIOS Redirect to NMI interrupt
(BIOS entry INT 287)
IRQ 14 (BIOS entry-OIl)
IRQ 15 (BIOS entry 011)
Not used
Reserved for BASIC
Used by BASIC interpreter while
BASIC is running
Not used

72

73
74
75

78-7F
80-85
86-FO

108-10B
10C-10F
lEO-IFF
200-217
218-3C3

F1-FF

3C4-3FF

76
77

Hardware, Basic, and DOS Interrupts

Vectors with Special Meanings
Interrupt lS-Cassette I/O: This vector points to the
following functions:
•

Device open

•

Device closed

•

Program termination

•

Event wait

•

Joystick support

•

System Request key pressed

5-6

System BIOS

•

Wait

•

Move block

•

Extended memory size determination

•

Processor to protected mode

Additional information about these functions may be found in the
BIOS listing.

Interrupt IB-Keyboard Break Address: This vector points to
the code that is executed when the Ctrl and Break keys are
pressed. The vector is invoked while responding to a keyboard
interrupt, and control should be returned through an IRET
instruction. The power-on routines initialize this vector to point
to an IRET instruction so that nothing will occur when the Ctrl
and Break keys are pressed unless the application program sets a
different value.
This routine may retain control with the following considerations:
•

The Break may have occurred during interrupt processing, so
that one or more End of Interrupt commands must be sent to
the 8259 controller.

•

All IIa devices should be reset in case an operation was
underway at the same time.

Interrupt I C-Timer Tick: This vector points to the code that
will be executed at every system-clock tick. This vector is
invoked while responding to the timer interrupt, and control
should be returned through an IRET instruction. The power-on
routines initialize this vector to point to an IRET instruction, so
that nothing will occur unless the application modifies the pointer.
The application must save and restore all registers that will be
modified. When control is passed to an application with this
interrupt, all hardware interrupts from the 8259 interrupt
controller are disabled.

System BIOS

5-7

Interrupt ID-Video Parameters: This vector points to a data
region containing the parameters required for the initialization of
the 6845 on the video adapter. Notice that there are four
separate tables, and all four must be reproduced if all modes of
operation are to be supported. The power-on routines initialize
this vector to point to the parameters contained in the ROM video
routines.
Interrupt IE-Diskette Parameters: This vector points to a
data region containing the parameters required for the diskette
drive. The power-on routines initialize this vector to point to the
parameters contained in the ROM diskette routine. These default
parameters represent the specified values for any IBM drives
attached to the system. Changing this parameter block may be
necessary to reflect the specifications of other drives attached.
Interrupt IF-Graphics Character Extensions: When
operating in graphics modes 320 x 200 or 640 x 200, the
read/write character interface will form a character from the
ASCII code point, using a set of dot patterns. ROM contains the
dot patterns for the first 128 code points. For access to the
second 128 code points, this vector must be established to point
at a table of up to lK, where each code point is represented by 8
bytes of graphic information. At power-on time, this vector is
initialized to 000:0, and the user must change this vector if the
additional code points are required.
Interrupt 40-Reserved: When a Fixed Disk and Diskette
Drive Adapter is installed, the BIOS routines use interrupt 40 to
revector the diskette pointer.
Interrupt 41 and 46-Fixed Disk Parameters: These vectors
point to the parameters for the fixed disk drives, 41 for the first
drive and 46 for the second. The power-on routines initialize the
vectors to point to the appropriate parameters in the ROM disk
routine if CMOS is valid. The drive type codes in CMOS are
used to select which parameter set each vector is pointed to.
Changing this parameter hook may be necessary to reflect the
specifications of other fixed drives attached.

5-8

System BIOS

Other Read/Write Memory Usage
The IBM BIOS routines use 256 bytes of memory from absolute
hex 400 to hex 4FF. Locations hex 400 to 407 contain the base
addresses of any RS-232C adapters installed in the system.
Locations hex 408 to 40F contain the base addresses of any
printer adapters.
Memory locations hex 300 to hex 3FF are used as a stack area
during the power-on initialization and bootstrap, when control is
passed to it from power-on. If the user desires the stack to be in a
different area, that area must be set by the application.
The following figure shows the reserved memory locations.
Address

Mode

400-4Al
4A2-4EF
4FO-4FF

ROM BIOS

500-5FF
500

DOS

504
510-511
512-515
516-519

DOS
BASIC
BASIC
BASIC

51A-51D

BASIC

Function
See BIOS listing
Reserved
Reserved as intra-application
communication area for any appl ication
Reserved for DOS and BASIC
Print screen status flag store
O=Print screen not active or successful
print screen operation
l=Print screen in progress
255=Error encountered during print
screen operation
Single drive mode status byte
BASIC's segment address store
Clock interrupt vector segment:offset store
Break key interrupt vector segment:offset
store
Disk error interrupt vector segment:offset
store

Reserved Memory Locations

System BIOS

5-9

The following is the BASIC workspace for DEF SEG (default
workspace) .
Offset

Length

2E
347
30
358

2
2
2
2

6A

1

4E

1

Line number of current line being executed
Line number of last error
Offset into segment of start of program text
Offset into segment of start of variables
(end of program text 1-1)
Keyboard buffer contents
O=No characters in buffer
I=Characters in buffer
Character color in graphics mode*

*Set to I, 2, or 3 to get text in colors 1-3.
Do not set to O. The default is 3.

Basic Workspace Variables

Example
100 PRINT PEEK (&H2E)
L

H

Hex 64

Hex 00

+ 256 x PEEK (&H2F)

The following is a BIOS memory map.
Starting Address
00000
OOIEO
00400
00500
EOOOO
FOOOO

BIOS interrupt vectors
Available interrupt vectors
BIOS data area
User read/write memory
Read only memory
BIOS program area

BIOS Memory Map

BIOS Programming Hints
The BIOS code is invoked through program interrupts. The
programmer should not "hard code" BIOS addresses into
applications. The internal workings and absolute addresses within
BIOS are subject to change without notice.
If an error is reported by the disk or diskette code, reset the drive

adapter and retry the operation. A specified number of retries

5-10

System BIOS

should be required for diskette reads to ensure the problem is not
due to motor startup.
When altering I/O-port bit values, the programmer should change
only those bits necessary to the current task. Upon completion,
the original environment should be restored. Failure to adhere to
this practice may cause incompatibility with present and future
applications.
Additional information for BIOS programming can be found in
Section 9 of this manual.

Move Block BIOS
The Move Block BIOS was designed to make use of the memory
above the 1M address boundary while operating with IBM DOS.
The Block Move is done with the Intel 80286 Microprocessor
operating in the protected mode.
Because the interrupts are disabled in the protected mode, Move
Block BIOS may demonstrate a data overrun or lost interrupt
situation in certain environments.
Communication devices, while receiving data, are sensitive to
these interrupt routines; therefore, the timing of communication
and the Block Move should be considered. The following table
shows the interrupt servicing requirements for communication
devices.
Baud Rate
300
1200
2400
4800
9600

11 Bit (ms)
33.33
8.33
4.16
2.08
1. 04

9 bit (ms)
30.00
7.50
7.50
1. 87
0.93

Times are approximate

Communication Interrupt Intervals

System BIOS

5-11

The following table shows the time required to complete a Block
Move.
Buffer
Addresses

Block Size
Normal
512 Byte

Maximum
64K

Both even
Even and odd
Both odd
Both even
Even and odd
Both odd

Time in ms
0.98
1.04
1. 13
37.0
55.0
72.0

Time is approximate

Move Block BIOS Timing

Following are some ways to avoid data overrun errors and loss of
interrupts:
•

Do not use the Block Move while communicating, or

•

Restrict the block size to 512 bytes or less while
communicating, or

•

Use even address buffers for both the source and the
destination to keep the time for a Block Move to a minumum.

Adapters with System-Accessible ROM Modules
The ROM BIOS provides a way to integrate adapters with
on-board ROM code into the system. During POST, interrupt
vectors are established for the BIOS calls. After the default
vectors are in place, a scan for additional ROM modules occurs.
At this point, a ROM routine on an adapter may gain control and
establish or intercept interrupt vectors to hook themselves into
the system.
The absolute addresses hex C8000 through EOOOO are scanned in
2K blocks in search of a valid adapter ROM. A valid ROM is
defined as follows:
Byte 0
Byte 1

5-12

Hex 55
HexAA

System BIOS

Byte 2
Byte 3

A length indicator representing the number of 512-byte
blocks in the ROM
Entry by a CALL FAR

A checksum is also done to test the integrity of the ROM module.
Each byte in the defined ROM module is summed modulo hex
100. This sum must be 0 for the module to be valid.
When the POST identifies a valid ROM, it does a CALL FAR to
byte 3 of the ROM, which should be executable code. The
adapter can now perform its power-on initialization tasks. The
adapter's ROM should then return control to the BIOS routines
by executing a RETURN FAR.

Additional System Board ROM Modules
The POST provides a way to integrate the code for additional
ROM modules into the system. These modules are placed in the
sockets marked U17 and U37. A test for additional ROM
modules on the system board occurs. At this point, the additional
ROM, if valid, will gain control.
The absolute addresses, EOOOO through EFFFF, are scanned in
64K blocks for a valid checksum. Valid ROM is defined as
follows:
Byte 0

Hex 55

Byte 1

HexAA

Byte 2

Not used

Byte 3

Entry by a CALL FAR

A checksum is done to test the integrity of the ROM modules.
Each byte in the ROM modules is summed modulo hex 100. This
sum must be 0 for the modules to be valid. This checksum is
located at address EFFFF.
When the POST identifies a valid ROM at this segment, it does a
CALL FAR to byte 3 of the ROM, which should be executable
code.

System BIOS

5-13

Quick Reference
BIOS MAP ........................•............ 5-16
Testl ..........................................
Data Area Description ..........................
Common POST and BIOS Equates ................
Test .01 Through Test .16 .......................
POST and Manufacturing Test Routines ............

5-18
5-20
5-22
5-27
5-49

Test2 .......................................... 5-50
Test .17 Through Test .23 ....................... 5-50
Test3. POST Exception Interrupt Tests ................ 5-67
Test4. POST and BIOS Utility Routines ...............
CMOS READ ..............................
CMOS--VVRITE .............................
E MSG P MSG ...........................
ERR BEEP-- ................................
BEEP ......................................
VVAITF .....................................
CONFIG BAD ..............................
PRT SEG ..................................
KBD--RESET ...............................
D11 - Dummy Interrupt Handler .................
Hardware Interrupt 9 Handler (Type 71) ...........

5-73
5-73
5-73
5-74
5-74
5-75
5-75
5-75
5-76
5-76
5-79
5-79

Test5. Exception Interrupt Tests .....................
SYSINIT1 - Build Protected Mode Descriptors .......
GDT BLD - Build the GDT for POST ............
SIDT--BLD - Build the IDT for POST ............

5-80
5-81
5-81
5-82

Test6 ..........................................
STGTST CNT ..............................
ROM ERR .................................
XMIT-- 8042 ................................
BOOT-- STRAP ..............................

5-85
5-85
5-87
5-87
5-87

Diskette BIOS

.......................•.......... 5-89

Fixed Disk BIOS ................................ 5-114

5-14

System BIOS

Keyboard BIOS ................................. 5-127
Printer BIOS

5-138

RS232 BIOS

5-140

Video BIOS .................................... 5-143
BIOS ........................................
Memory Size Determine .......................
Equipment Determine .........................
NMI ......................................

5-161
5-161
5-161
5-162

BIOS1. .......................................
Event Wait .................................
Joystick Support .............................
Wait ......................................
Block Move ................................
Extended Memory Size Determine ...............
Processor to Virtual Mode .....................

5-163
5-164
5-165
5-166
5-167
5-172
5 -174

BIOS2 .......................................
Time of Day ................................
Alarm Interrupt Handler .......................
Print Screen .................................
Timer 1 Interrupt Handler ......................

5-176
5-176
5-179
5-180
5-181

ORGS - PC Compatibility and Tables ................ 5-182
POST Error Messages ......................... 5-182

System BIOS

5-15

Warn i ng: No STACK segment
Start
Stop
Length
Name
OOOOOH OFFFEH FFFFH
CODE
Origin
Address
FOOO:E129
FOOD :3BEA
FOOO:6000
FOOO: 19FO
FOOO: 181A
FOOO:2022
FOOO: OC96
FOOO:0396
FOOO:42FC
FOOOl1941
FOOO: 1958
FOOD: I A45
FOOO :E6F5
FOOO:FA6E
FOOO:E020
FOOO: 18CA
FOOO: E030
FOOO :E040
FOOO: 1915
FOOO:2143
FOOO :EFC1
FOOO :28DE
FOOD :2DF2
FOOO:2C49
FOOO: 28F5
FOOD :FF53
FOOD: ICI8
FOOO:E05E
FOOO :£011
FOOO:E090
FOOO:EOA9
FOOO :EOC2
FOOO:EOD8
FOOO :EOF4
FOOO:EIQO
FOOO:EI26
FOOO:EI3F
FOOO:EI68
FOOO:E 191
FOOO:EI81
FQOO:EI08
FOOO IE 1EE
FOOO:E209
FOOO:E224
FOOO :E239
FOOO:E2C6
FOOO:E2EA
FOOO :E30E
FOOO:E3IE
FOOO :E32E
FOOO :E343
FOOO:426F
FOOO: 1982
FOOO: 1910
FOOO:E364
FOOO :E319
FOOO:E38E
FOOO:E3AC
FOOO :E38F
FOOO:E302
FOOO:E25D
FOOO :E3DF
FOOO:E401
FOOO :4A4F
FOOO:FF5E
FOOO:46C8
FOOO:3316
FOOO:FF5A
FOOO: 1C22
FOOO :E8E 1
FOOO:E918
FOOO:E955
FOOO :E95F
FOOO:E969
FOOO :E976
FOOO:342E
FOOO:E81E
FOOO:0008
FOOO :E886
FOOO:E88E
FOOO :E8C8
FOOO: IAEF
FOOO: 33C5
FOOO:3339
FOOO:OOIO
FOOO:FOE4
FOOO :FOEC
FOOO:FOF4
FOOO:4265
FOOO :E2C3
FOOO:4219
FOOO:03A2
FOOO:OOOO
FOOO:OC96
FOOO: 1671
FOOO:1941
FOOO: IC38
FOOO:1E85
FOOO:38DO
FOOO:FF54
FOOO:4970
FOOO: IC31
FOOO: IA85
FOOO: 1.1.69
FOOO: IA70
FOOO: 19A4
FOOD :FFFO
FOOO:3D48
FOOO: 3803

5-16

C I ass

Group
Pub Ii cs by Name
AI
ACT 0 I SP PAGE
BASTc
BEEP
BLINK INT
BOOT STRAP 1
C21 C8042
CASSETTE 10 I
CMOS READ CMOS-WRITE
CONFTG BAD
CONF TSl
CRT CHAR CiEN
01 011

02
D2A
DDS
DISKETTE 10 I
DISK BASE
DISK-INT 1
DISK-IO DISK-SETUP
DSKETTE SETUP
DUMMY RETURN
DUMMY-RETURN I
EIOI EI02
EI03
EI04
El05
EI06
EI01
EI08
El09
EI61
EI62
EI63
EI64
E201
E202
E203
E301
E302
E303
E304
E401
E501
E601
E602
EQUIPMENT I
ERR BEEP
E MSG
FI180
F 118 f
F f 182
F 1190
F 179!
F3A
F3D
F3DI
FD TBL
FILL
FLOPPY
CATE A20
HO INT
HRO
I NT 287
K 10-

KII

Abs

Abs

K 12
K 13
K 14
K 1S
K 16
K6
K6L

K'
KB

K9
K8D RESET
KB TNT I
KEY80ARD 10 1
M4
--

"5
"6

"'

MEMORY SIZE DET 1
NMI INT
NMI-INT I
08F-42 POST!
PDST2
POST3
POSH
POST5
POST6
PRINTER 10 I
PR I NT SCREEN
PR I NT-SCREEN 1
PROC SHUTDOWN
PROT-PRT HEX
PRT REX PRT-SEG
P MSG
P-O R
READ AC CURRENT
READ=CURSOR

Address
FOOO:OOOO
FOOO: 0008
FOOO:OO!O
FOOO:0050
FOOO:0396
FOOD: 03A2
FOOO: OC96
FOO~: OC96
FOOD: 1052
FOOO: I 086
FOO~: I 089
FOOO: 1 00.1.
FOOO:1613
FOOO:1611
FOOO:1941
FOOO:1941
FOOD: 1958
FOOO: 1915
FOO~: 1910
FOOD: 19A4
FOOO: 1982
FOO~: 19FO
FOOD: I A36
FOOO: IA45
FOOO: IA59
FOOD: 1.1.69
FOOO: IA10
FOOO: lA85
FOOD: lAB!
FOOO: IA80
FOOO: 1 AEF
FOOD: ISlA
FOOO: 1828
FOOD: 18CA
FOOO:ICI8
FOOD: ICI9
FOOD: I C22
FOOD: IC31
FOOD: IC38
FOOD: ID2A
FOOO:1E85
FOOD: IE85
FOOO:1F85
FOOO: IFEI
FOOD: 2022
FOOO:2143
FOOO: 2A88
FOOO:2BOE
FOOO:2BF5
FOOO: 2C49
FOOO:2DF2
FOOO: 3316
FOOO: 3339
FOOO:33C5
FOOO:342E
FOOO: 3833
FOOO:38DD
FOOO: 3961
FOOO:3A17
FOOO: 3A86
FOOO: 3886
FOOO:3BAB
FOOO: 3803
FOOO: 38EA
FOOO: 3COE
FOOO:3C34
FOOO: 3C51
FOOO :3CF6
FOOO :3048
FOOD: 30.1.2
FOOO:3DD4
FOOO :3E84
FOOO: 3E95
FOOO:4139
FOOO:4ICO
FOOO: 4265
FOOO:426F
FOOO:4279
FOOO :42FC
FOOO: 4586
FOOO :46C8
FOOO:4184
FOOO:4906
FOOO: 4970
FOOO:4A06
FOOO:4A4F
FOOO: 6000
FOOO: E020
FOOO:E030
FOOO:E040
FOOO :E05E
FOOO:E017
FOOD; E090
FOOO:EOA9
FOOO:EOC2
FOOO :EOD8
FOOO :EOF4
FOOO:EIOD
FOOO:EI26
FOOO:EI3F
FOOO:EI68
FOOO:EI91
FOOO:EI81
FOOO:E10B
FOOO:EIEE
FOOO:E209
FOOO:E224
FOOO:E239
FOOO:E25D

BIOS MAP (11/15/85)

Publics by Value
Aba

POSTI
K6L

"4
START

I
C804208F 42
POST2
C21
SHUT3
SHUT2
SHUTT
SHUT6
SHUT4
POST3
CMOS READ
POST4
CMOS WRITE
ODS E MSG
P-MSG
ERR BEEP
BEEP
WAITF
CONF IG BAD
XPC BYTE
PRT-HEX
PRT-SEG
PROT PRT HEX
ROM CHECKSUM
ROM-CHECK
K8D-RESET
8L1NK INT
SET TOO
011-

~~M~i R~~iURN_I
INT 281
PROC SHUTDOWN
POSTS
SYSINITI
POST6
STCTST CNT
ROM ERR
XMIT 8042
800T-STRAP I
DISKETTE 10 1
SEEK
-DISK INT I
DSKETTE SETUP
01 SK SETUP
DISK-IO
HD INT
KEYBOARD_IO_I
K8 INT 1
K16
SND DATA
PRINTER 10 1
RS232 10 1VIDEO-IO-I
SET MODC
SET-CTYPE
SET-CPOS
READ CURSOR
ACT 01 SP PAGE
SET-COLOR
VIDEO STATE
SCROLL UP
SCROLL -DOWN
READ AC CURRENT
WR I TE AC CURRENT
WR 1TE-C CURRENT
READ DOT
WR I TE DOT
WR I TE-TTY
READ LPEN
MEMORY SIZE DET 1
EQUIPMENT 1NMI INT 1-

~~G~~TTE_I 0_1
GATE .1.20
TlME=OF_DAY_1
RTC I NT
PR I NT SCREEN I
TlMER-INT I Fill BASIC
01
D2
D2A
EIOI
EI02
El03
EI04
E I 05
El06
EI07
E I 08
El09
EI61
EI62
EI63
EI64
E201
E202
E203
E30 I
E302
F3D

FOOO
FOOO
FOOO
FOOO
FOOO
FOOO
FOOO
FOOO
FOOD
FOOO
FOOO
FOOO
FOOO
FOOO
FOOO
FOOO
FOOO
FOOO
FOOO
FOOO
FOOD
FOOO
FOOD
FOOO
FOOD
FOOD
FOOO
FOOD
FOOO
FOOO
FOOO
FOOO
FOOO
FOOO
FOOO
FOOD
FOOO
FOO~

FOOD
FOOO
FOOO
FOOO

3E84
41CO
ICI9
I ABO
IABI
I FB5
3961
4906
3CF6
3C51
2A88
FF62
3COE
3BAB
3886
3AB6
1828
IOB6
1052
1613
100A
1089
4586
FF23
3833
0050
IE85
ID2A
4A06
4184
FF66
FEF3
3A11
FOA4
3C34
1 A36
30A2
3004
3E95
4139
lFEI
1 A59

READ DOT
REAO-LPEN
RE DTRECT
ROM CHECK
Rm[CHECKSUM
ROM-ERR
RS232 10 I
RTC INT SCROLL DOWN
SCROLL-UP
SEEK
SEEKS 1
SET COLOR
SET-CPOS
SET-CTYPE
SET-MODE
SET-TOO
SHUT2
SHUT3
SHUT4
SHUT6
SHUT1
SHUT9
SLAVE VECTOR TA8LE
SNO -DATA
START 1
STGTST CNT
SYSINITI
TIMER INT 1
TIME OF DAY I
TUTOR VECTOR TABLE
VIDEO To 1
V IOEO-PARMS
VIDEO-STATE
WA ITFWR I TE AC CURRENT
WR I TE-C CURRENT
WR ITE-OOT
WR I TE-TTY
XMIT 8042
XPC_BYTE

FOOO
FOOO
FOOO
FOOO
FOOO
FOOO
FOOO
FOOD
FOOO
FOOO
FOOO
FOOO
FOOO
FOOO
FOOO
FOOO
FOOO
FOOO
FOOO
FOOO
FOOD
FOOD
FOOD
FOOO
FOOO
FOOO
FOOD
FOOO
FOOO
FOOO
FOOO
FOOO
FOOO
FOOO
FOOO
FOOO
FOOO
FOOO
FOOO
FOOD
FOOO
FOOO

E2C3
E2C6
E2EA
E30E
E31E
E32E
E343
E364
E319
E38E
E3AC
E3BF
E302
E30F
E401
E6F5
E129
E81E
E886
E88E
E8C8
E8El
E918
E955
E95F
E969
E916
EFC1
FOA4
FOE4
FOEC
FOF4
FA6E
FEF3
FF23
FF53
FF54
FF5A
FF5E
FF62
FF66
FFFO

NMI INT
E303
E304
E401
E501
E601
E602
FI180
F1181
F1182
F1190
F1191
F3A
F301
FD TBL
CONF TBL

AI

-

K6

K'

K8
K9
K 10

Kl1
K12
K13
K1'
K15

DISK BASE
VIDEO PARMS

"5

"6

-

"'

CRT CHAR GEN
VECTOR TABLE
SLAVE VECTOR TABLE
OUMMY-RETURNPR I NT-SCREEN
HRD
FLOPPY
SEEKS 1
TUTORP _O_R

BIOS MAP (11/15/85)

5-17

IBM Personal Computer MACRO Assembler
TESTI ---- 11/15/85
POWER ON SELF TEST

1

2
3

•
5
6
7
8
9

10
11
12

13

I.
15

16
17
18
19
20
21
22
23

2.
25

26
27
28
29
30
31

32
33

3.
35
36
37

38
39

PAGE 118,121
TITLE TESTI ---.286C

;

51
52

53
54
55

56
57

58
59
60
61
62

63

6.
65

66

67

68
69

70
71

72
73
74

75
76
77

78
79

80
81
82
83
84
85
86

87
88

89

90
91

92
93
9.
95
96

97
98
99

100

101
102
103
10.
105
106
107
108
109

110

5-18

BIOS

I/O

INTERFACE

THESE LISTINGS PROVIDE INTERFACE INFORMATION FOR ACCESSING
THE B I OS ROUT I NES.
THE POWER ON SELF TEST I S INCLUDED.
THE
8 I OS
ROUT INES
ARE
MEANT
TO
BE
ACCESSED
THROUGH
INTERRUPTS
ONLY.
ANY
ADDRESSES
PRESENT
IN
SOFTWARE
THESE
LIST I NGS
ARE
INCLUDED
ONL Y
FOR
COMPLETENESS,
NOT
FOR
REFERENCE.
APPL I CAT IONS
WH I CH
REFERENCE
ANY
ABSOLUTE
ADDRESSES
WITH I N
THE
CODE
SEGMENTS
OF
B I OS
VIOLATE
THE
STRUCTURE
AND
DESIGN
OF
BIOS.

.------------

,
,,,
,,
,
;

- --- - --- ------------- ---- --------------------------

MODULE REFERENCE
TEST I .ASM
DSEG.INC
POSTEQU. INC
SYSDATA. INC

~~>
~~>

TEST2.ASM

,

T£ST3.ASM
TEST4.ASM

,,
,

,,

50

(POST)

;

'2
43
44
45

.9

POWER ON SELF TEST

,--- ----- ------------------------------ -- -----

,,

47
48

11/15/85

-------- ----------------- ----------------

,
,,,
,,
,,,
,,
;

.0
.1
.6

Version 2.00
(POST)

,
,

,,,
,
,,,
,

,,
,,
,,

TEST5.ASM

,,
,,
,,
,

DSKETTE.ASM

,

,

,,,
,,,

TEST6.ASM

DISK.ASM

,,
,
,,,
,
,,,
,,,
,
,,,
,,,
,,
,
,,,
,,,

:

~ ~;~

KYBD.ASM

PRT .ASM
RS232.ASM
VIDEOI.ASM
BIOS.ASM

~~>
~~>

BIOSI.ASM

810S2.ASM

ORGS.ASM

- - - -- - -- -- - - - - - - -- --

TESTI (11/15/85)

POST AND MANUFACTURING TEST ROUTINES
DATA SEGMENTS LOCATIONS
COMMON EQUATES FOR POST AND BIO~
POWER ON SELF TEST EQUATES FOR PROTECTED MODE
POST TEST. 0 1 THROUGH TEST. 16
POST TEST AND INITIALIZATION ROUTINES
POST TEST .17 THROUGH TEST .22
POST EXCEPT I ON I NTERRUPT TESTS
POST AND BIDS UTILITY ROUTINES
CMOS READ
- READ CMOS LOCATION ROUTINE
CMOS-WRITE
- WRITE CMOS LOCATION ROUTiNE
DDS - LOAD (OS:) WITH DATA SEGMENT
- POST ERROR MESSAGE HANDLER
E MSG
MFG HALT
- MANUFACTURING ERROR TRAP
P MSG
- POST STRING DISPLAY ROUTINE
ERR BEEP
- POST ERROR BEEP PROCEDURE
BEEP
- SPEAKER BEEP CONTROL ROUT I NE
WAITF
- FIXED TIME WAIT ROUTINE
CONFIG BAD
- SET 8AD CONFIG IN CMOS DIAG
XPC BYTE
- DISPLAY-HEX 8YTE AS 00-- FF
PRT-HEX
- 0 I SPLA Y CHARACTER
PRT-SEG
- 0 I SPLA Y SEGMENT FORMAT ADDRESS
PROT PRT HEX
- POST PROTECTED MODE 0 I SPLA Y
ROM CHECKSUM
- CHECK ROM MODULES FOR CHECKSUM
ROM-CHECK
- ROM SCAN AND INiTiALIZE
KBD-RESET
- POST KEYBOARD RESET ROUTINE
8LINK INT
- MANUFACTURING TOGGLE BIT ROUTINE
SET TOO
- SET T I MER FROM CMOS RTC
01 1- DUMMY I NTERRUPT HANDLER
-> I NT
RE 0 I RECT
- HARDWARE I NT
9 RED I RECT (L 21
INT 287
- HARDWARE INT 13 REDIRECT (287)
PROC SHUTDOWN - 80286 RESET ROUTINE
EXCEPTION INTERRUPT TEST HANDLERS FOR POST TESTS
SYS I NIT 1
- BU I LD PROTECTED MODE PO INTERS
GOT BLD
- BU I LD THE GOT FOR POST
SlOT BLD
- BUILO THE lOT FOR POST
POST TESTS AND SYSTEM 800T STRAP
STGTST CNT
SEGMENT STORAGE TEST
ROM ERR
- ROM ERROR 0 I SPLA Y ROUT I NE
XMIT 8042
- KEYBOARD DIAGNOSTIC OUTPUT
BOOT=STRAP
- BOOT STRAP LOADER
- INT 19H
DISKETTE BIOS
DISKETTE 10 1 - ]NT 13H BIOS ENTRY (40H)
-INT 13H
DISK I NT-I - HARDWARE I NTERRUPT HANDLER - I NT OEH
DSKETTE SETUP - POST SETUP DR I VE TYPES
FIXED DISK BIOS
01 SK SETUP
- SETUP 0 I SK VECTORS AND TEST
DISK-IO
- INT 13H BIOS ENTRY
-INT 13H
HD INT
- HARDWARE INTERRUPT HANDLER -INT 76H
KEYBOARD B I OS
KEYBOARD 10 1 - [NT 16H 810S ENTRY
- ]NT 16H
K8 I NT 1- - HARDWARE INTERRUPT
-INT 09H
SND DATA
- KEYBOARD TRANSMISSION
PR I NTER ADAPTER B I OS
- ]NT 17H
COMMUNICATIONS BIOS FOR RS232
-INT 14H
VIDEO BIOS
-INT IOH
B I OS ROUT I NES
MEMORY SIZE DET 1 - REAL MODE S [ZE
-INT 12H
EQU I PMENT 1- -EQU I PMENT OETERM I NA T I ON
-[NT llH
NMI INT 1- NMI HANDLER
-INT 02H
INTERRUPT-15H B I OS ROUT [NES
-INT 15H
DEV OPEN
- NULL DEV I CE OPEN HANDLER
DEV-CLOSE
- NULL DEV I CE CLOSE HANDLER
PROG TERM
- NULL PROGRAM TERM] NAT I ON
EVENT WA I T
- RTC EVENT WA IT/ TIMEOUT ROUT I NE
JOY STICK
- JOYSTICK PORT HANDLER
SYS-REQ
- NULL SYSTEM REQUEST KEY
WAIT
- RTC TIMED WAIT ROUTINE
8LOCKMOVE
- EXTENDED MEMORY MOVE INTERFACE
GATE A20
- ADDRESS BIT 20 CONTROL
EXT MEMORY
- EXTENDED MEMORY SIZE DE TERM I NE
SET-VMODE
- SWITCH PROCESSOR TO VIRTUAL MODE
DEVICE BUSY
- NULL DEVICE BUSY HANDLER
I NT COMPLETE
- NULL 1NTERRUPT COMPLETE HANDLER
810S INTERRUPT ROUT I NES
TIME OF DAY' - TIME OF DAY ROUTINES
-INT IAH
RTC INT- I RQ LEVEL 8 ALARM HANDLER
-INT 70H
PR I NT SCREEN 1 - PR I NT SCREEN ROUT I NE
-INT 05H
T I MER-I NT 1
- T I MER 1 I NTERRUPT HANDLER
->]NT 1CH
COMP A T I Bill TY MODULE
POST ERROR MESSAGES
DISKETTE - DISK - VIDEO DATA TABLES

IBM Personal Computer MACRO Assembler
Version 2.00
TEST 1 ---- 11/15/85
POWER ON SELF TEST (POST)
OSEG. I NC
OAT A SEGMENTS

111
112
113
114
115
11.
117
liB
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135

PAGE
C
INCLUDE DSEG. INC
C
; ---- ----------------------------- ------C;
80286 INTERRUPT LOCATIONS
C;
REFERENCED BY POST & 8105
C
; ------------------ --------------- ------C
C
A850
SEGMENT AT 0
ADDRESS= 0000:0000
C
C IIISTG_LOCO
08
START OF INTERRUPT VECTOR TABLE

0000

C

0008
0008????????
0014
0014 ????????
0020
0020????????
0040
0040 ?????7??
004C
004C

13.
137
138
139
140
141
142
143
144
145
146
141
14B
149
150
151
152
153
154
155
156
157
158
159

0060
0060

0 \ CO
OICO

???????1

161
162

0108
0108

?????7??

164
165

0400
0 ... 00

????

,.0
,.3
,.7

??????77

0074
0014 ????????

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

IIINMI_PTR

ORG
"''"002H
DO?

NON-MASK ABLE

IIIINT5_PTR

ORG
",'"005H
DO?

PRINT SCREEN INTERRUPT VECTOR

III I NT _PTR

ORG
"''"008H
DO?

HARDWARE

IIIVJDEO_INT

DRG
... ·OIOH
DO?

VIOEO

"ORG_VECTOR

ORG
DO

DISKETTE/DISK

IIIBASIC_PTR

ORG
"''"OISH
DO?

POINTER TO CASSETTE BASIC

IIIPARM_PTR

ORG
",'"OIDH
DO?

POINTER TO VIDEO PARAMETERS

IIIDISK_POINTER

ORG
"''"OIEH
DO?

POINTER TO DISKETTE PARAMETER TABLE

II'EXT_PTR

ORG
"''"OIFH
DO?

POINTER TO GRAPHIC CHARACTERS

1110 I SK_ VECTOR

ORG
",'"040H
DO?

PO I NTER TO 0 I SKETTE I NTERRUPT CODE

IIIHF_TBL_VEC

ORG
4'"0 ... IH
DO?

POINTER TO FIRST DISK PARAMETER TABLE

IIIHF 1_TBL_ VEC

ORG
4'"046H
DO?

PO I NTER TO SECOND 0 15K PARAMETER TABLE

IIISLAVE_INT_PTR

ORG
4'"070H
DO?

POINTER TO SLAVE INTERRUPT HANDLER

IIIHDISK_INT

ORG
4'"076H
DO?

POINTER TO FIXED DISK INTERRUPT CODE

II'TOS

ORG
0400H
OW?

IIIMFG_TEST_RTN

ORG
LABEL

0500H
FAR

LOAD LOCATION FOR MANUFACTURING TESTS

IIIBOOT_LOCN

ORG
LABEL

leOOH
FAR

BOOT STRAP CODE LOAD LOCATION

ABSO

ENDS

"''"013H
1

] /0

INTERRUPT VECTOR

] NTERRUPT PO INTER

(8-F)

INTERRUPT VECTOR
INTERRUPT VECTOR

C

0078
0078
007C
007C

???????7
???????7

C
C
C
C
C

128-255

C

0100
0100 ????????
0104
0104 ??????71
0118
0 lIB????????

I ••

168
169
170
171
172
173
174

1-2
1 1-19-85

0500
0500

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

STACK -- USED DURING POST ONLY
USE WILL OVERLAY I NTERRUPTS VECTORS

C

7COO
1COO
7COO

C
C
C
C

TEST1 (11/15/85)

5-19

1-3

IBM Personal Computer MACRO Assembler
Version 2.00
TESTI ---- 11/15/85
POWER ON SELF TEST (POST)
OSEG.INC - DATA SEGMENTS

175
176
117
178
17'
180
181
182
183
184
185
186
187
188
18'
190
191
192
193
194
195
196
197
198
19'
200
201
202
203
204
205
206
207
208
20'
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
22'
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
24'
250
251
252
253
254
255
256
257
258
25'
260
261
262
263
264
265
266
267
268
26'
270
271
272
273
274
275
2'6
217
278
279

C
C
C
C
C
C

0000

PAGE

;

- - - - - --- - - - - - - - - - -- - - - - - -- -- -- - --- -- - ---

;

ROM 8105 DATA AREAS

DATA

SEGMENT AT 40H
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