64100 90910__64100A_Mainframe_Service_Manual_Dec83 90910 64100A Mainframe Service Manual Dec83

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HP64000
Logic Development
System

Model 64100A
Mainframe
Service Manual
r/i~ HEWLETT
~a PACKARD

CERTIFICATION
Hewlett-Packard Company certifies that this product met its published specifications at the
time of shipment from the factory. Hewlett-Packard further certifies that its calibration
measurements are traceable to the United States National Bureau of Standards, to the extent
allowed by the Bureau's calibration facility, and to the calibration facilities of other
International Standards Organization members.

WARRANTY
This Hewlett-Packard system product is warranted against defects in materials and
workmanship for a period of 90 days from date of installation. During the warranty period, HP
will, at its options, either repair or replace products which prove to be defective.
Warranty service of this product will be performed at Buyer's facility at no charge within HP
service travel areas. Outside HP service travel areas, warranty service will be performed at
Buyer's facility only upon HP's prior agreement and Buyer shall pay HP's round trip travel
expenses. In all other cases, products must be returned to a service facility designated by HP.
For products returned to HP for warranty service. Buyer shall prepay shipping charges to HP
and HP shall pay shipping charges to return the product to Buyer. However, Buyer shall pay all
shipping charges, duties, and taxes for products returned to HP from another country.
HP warrants that its software and firmware designated by HP for use with an instrument will
execute its programming instructions when properly installed on that instrument. HP does not
warrant that the operation of the instrument, or software, or firmware will be uninterrupted or
error free.
LIMITATION OF WARRANTY

The foregoing warranty shall not apply to defects resulting from improper or inadequate
maintenance by Buyer, Buyer-supplied software or interfacing, unauthorized modification or
misuse, operation outside of the environmental specifications for the product, or improper site
preparation or maintenance.
NO OTHER WARRANTY IS EXPRESSED OR IMPLIED. HP SPECIFICALLY DISCLAIMS THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE.
EXCLUSIVE REMEDIES

THE REMEDIES PROVIDED HEREIN ARE BUYER'S SOLE AND EXCLUSIVE REMEDIES. HP
SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR
CONSEQUENTIAL DAMAGES, WHETHER BASED ON CONTRACT, TORT, OR ANY OTHER
LEGAL THEORY.

ASSISTANCE
Product maintenance agreements and other customer assistance agreements are available for
Hewlett-Packard products.
For any assistance, contact your nearest Hewlett-Packard Sales and Service Office. Addresses
are provided at the back of this manual.
CW&A 2/81

SERVICE MANUAL

MODEL 64100A
MAINFRAME

SERIAL NUMBERS
This manual applies directly to MAINFRAMES with
serial numbers prefixed 2336A.

© COPYRIGHT HEWLETT-PACKARD COMPANY 1981, 1982, 1983
LOGIC SYSTEMS DIVISION
COLORADO SPRINGS, COLORADO, U.S.A

All Rights Reserved

Manual Part No. 64100-90910
Microfiche Part No. 64100-90810

PRINTED: DECEMBER 1983

SAFETY SUMMARY
The following general safety precautions must be observed during all phases of operation, service,
and repair of this Instrument. Failure to comply with these precautions or with specific warnings
elsewhere In this manual violates safety standards of design, manufacture, and Intended use of the
Instrument. Hewlett-Packard Company assumes no /lability for the customer's failure to comply
with these requirements.
GROUND THE INSTRUMENT.
To minimize shock hazard, the instrument chassis and cabinet must be connected to an electrical
ground. The instrument is equipped with a three-conductor ac power cable. The power cable
must either be plugged into an approved three-contact electrical outlet or used with a three-contact
to two-contact adapter with the grounding wire (green) firmly connected to an electrical ground
(safety ground) at the power outlet. The power jack and mating plug of the power cable meet
International Electrotechnical Commission (IEC) safety standards.
DO NOT OPERATE IN AN EXPLOSIVE ATMOSPHERE.
Do not operate the instrument in the presence of flammable gases or fumes. Operation of any
electrical instrument in such an environment constitutes a definite safety hazard.
KEEP AWAY FROM LIVE CIRCUITS.
Operating personnel must not remove instrument covers. Component replacement and internal
adjustments must be made by qualified maintenance personnel. Do not replace components with
power cable connected. Under certain conditions, dangerous voltages may exist even with the
power cable removed. To avoid injuries, always disconnect power and discharge circuits before
touching them.
DO NOT SERVICE OR ADJUST ALONE.
Do not attempt internal service or adjustment unless another person, capable of rendering first aid
and resuscitation, is present.
USE CAUTION WHEN EXPOSING OR HANDLING THE CRT.
Breakage of the Cathode-ray Tube (CRT) causes a high-velocity scattering of glass fragments (implosion).
To prevent CRT implosion, avoid rough handling or jarring of the instrument. Handling of the CRT shall
be done only by qualified maintenance personnel using approved safety mask and gloves.
DO NOT SUBSTITUTE PARTS OR MODIFY INSTRUMENT.
Because of the danger of introducing additional hazards, do not install substitute parts or perform
any unauthorized modification of the instrument. Return the instrument to a Hewlett-Packard
Sales and Service Office for service and repair to ensure that safety features are maintained.
DANGEROUS PROCEDURE WARNINGS.
Warnings, such as the example below, precede potentially dangerous procedures throughout this
manual. Instructions contained in the warnings must be followed.

I

WARNING

I

Dangerous voltages, capable of causing death, are present in this instrument.
Use extreme caution when handling, testing, and adjusting.
88-2-1/76

Model 64100A - Table of contents
Table of Contents
Section
I

Title

General Information .............................................. 1-1
1-1
1-4
1-6
1-15
1-17
1-20

II

Introduction ................................................ 2-1
Initial Inspection .......................................... 2-1
Packaging ................................................... 2-1
Original Packaging .......................................... 2-1
Installation and Removal of Mainframe Components ............ 2-2

Operation ........................................................ 3-1
3-1

IV

Manual Introduction .................................. " ..... 1-1
Chapter Introduction ........................................ 1-1
Physical Description ........................................ 1-1
Specifications ................................. , ............ 1-3
Instruments Covered In This Manual .......................... 1-3
Related Documents ........................................... 1-4

Installation ..................................................... 2-1
2-1
2-3
2-4
2-5
2-9

III

Page

General ..................................................... 3-1

Performance Verification ......................................... 4-1
4-1
4-4
4-6
4-9
4-10

Introduction ................................................ 4-1
Boot-Up Modes ............................................... 4-1
Power-Up Sequence ........................................... 4-2
Power-Up ROM Test ........................................... 4-3
Power-Up RAM Test ........................................... 4-4

4-11
4-12
4-15
4-16
4-17

Performance Verification Boot Procedure ..................... 4-6
Performance Verification Procedure .......................... 4-8
ROM Test Procedure ......................................... 4-11
RAM Test Procedure ......................................... 4-12
I/O Write Test Procedure ................................... 4-13

4-18
4-19
4-20
4-21
4-22

I/O Read Test Procedure .............. '" ................... 4-14
Time Interrupt Test Procedure .............................. 4-15
Keyboard Test Procedure .................................... 4-15
System Bus Test Procedure .................................. 4-16
RS232 Test Procedure ....................................... 4-17

4-23
4-24
4-25
4-26
4-29

PV On Existing Local Mass Storage Option ................... 4-17
Floppy Disc Test Procedure ................................. 4-18
Tape Test Procedure ........................................ 4-19
Troubleshooting PV Failures Using SA. '" ................... 4-20
Troubleshooting ............................................ 4-20
MF iii

Model 64100A - Table of contents

Table of Contents (Cont'd)

Section

v

Title

Adjustments ...................................................... 5-1
5-1

VI

Introduct ion ................................................ 7-1
Manual Changes .............................................. 7-1

Service .......................................................... 8-1
8-1

MF iv

Introduction ..........................•..................... 6-1
Abbreviations ............................................... 6-1
Major Components ............................................ 6-1
Ordering Information ........................................ 6-3
Direct Mail Order System .................................... 6-3
Parts List .................................................. 6-3

Manual Backdating ..........................•..................... 7-1
7 -1
7- 3

VIII

General ..................................................... 5-1

Replaceable Parts ................................................ 6-1
6-1
6-3
6-5
6-7
6-10
6-13

VI I

Page

Block Diagram Description ............. '" ................... 8-1

Model 64100A - Table of contents
List of Illustrations
Figure

Title

Page

1-1
1- 2
1-3

64100A Mainframe ................................................. 1-0
Mainframe Dimensions ............................................. 1-4
Mainframe Configuration .......................................... 1-5

4-1
4-2
4-3
4-4
4-5

Rear Panel Switch Locations ...................................... 4-9
Display Test Pattern ............................................. 4-9
Performance Verification Test ................................... 4-11
Keyboard PV Test Sequence ....................................... 4-16
Mainframe Troubleshooting Guide ................................. 4-22

6-1
6-2

Mainframe Component Locator (3 pages) ........................... 6-7
Mainframe Attach Screw Locator (7 pages) ....................... 6-10

8-1
8-2

Mainframe Simplified Block Diagram ............................... 8-6
A2 Motherboard Component Locator ................................. 8-7

List of Tables
Table

Title

Page

1-1
1-2

Basic Power Current Drain ........................................ 1-2
Power and Environmental Requirements ............................. 1-3

4-1
4-2
4-3

PV Boot Keys ..................................................... 4-8
Performance Verification Soft Keys .............................. 4-10
Failure Conditions and Routing .................................. 4-21

6-1
6-2
6-3
6-4

List of Manufacturers' Codes ..................................... 6-2
Reference Designators and Abbreviations .......................... 6-5
Replaceable Parts ................................................ 6-6
Attach Screw Index .............................................. 6-17

7-1

Serial Number vs. Manual Change Number ........................... 7-1

8-1
8-2
8-3
8-4
8-5

Card Type Vs. Supply Voltage ..................................... 8-3
Display Driver Connector J14 Signals ............................. 8-4
Keyboard Connector J15 Signals ................................... 8-4
BNC Connector J16 Signals ........................................ 8-5
Motherboard Signal Distribution .................................. 8-7

MFv

Model 64100A - General Information

r
,

\

\
j

1

1
\\

\
Figure 1 -1. 64100A Mainframe.

MF 1-0

"Model 64100A - General Information
SECTION I
GENERAL INFORMATION
1-1.

MANUAL INTRODUCTION.

1-2. This manual contains technical information to troubleshoot, install, and
maintain the 64100A Logic Development Station.
Each of the five chapters
(Mainframe, CPU, Display Controller, I/O, and Power Supply) is seperated by a
Tab. This allows the user to easily find any chapter.
1-3. Each of the five chapters is organized into eight sections:
Section I
introduces the reader to the manual and gives a brief physical description of
the product.
Section II presents the installation and removal procedures for
the system components.
Section III covers operation and handling. Section IV
describes how to troubleshoot and repair the system.
Section V references
those components that have adjustments. Section VI lists the replaceable parts
and Section VII contains backdating information needed to make this manual
applicable to older machines. Section VIII presents the theory-of-operation to
the block diagram level and is intended to support the troubleshooting
procedures.
1-4.

CHAPTER INTRODUCTION.

1-5. This chapter contains technical information concerning the installation,
maintenance, troubleshooting and theory-of-operation of the 64100A Mainframe.
The information contained in the Mainframe Chapter describes the overall system
and how the various components relate to each other with the emphasis on
troubleshooting and repairing. More detailed information on the components can
be found under the respective Chapter or the component in question (i.e., CPU,
DISPLAY CONTROLLER and DRIVER, I/O, POWER SUPPLY, and OPTIONS).
1-6.

PHYSICAL DESCRIPTION.

1-7. The 64100A Mainframe is a single enclosure similar to a CRT terminal (see
figure 1-1). It weighs 34.02 Kg (75 pounds) and thus some care should be used
in moving it.
The Mainframe dimensions are given in figure 1-2.
The five
major areas of the developement station mainframe are:
a.
b.
c.
d.
e.

CRT Display
Keyboard
Rear Panel
Card Cage
Power Supply

1-8. The four areas of display generation consist of
board, display driver, the CRT and CRT bezel assembly.

the display controller

MF 1-1

Model 64100A - General

Info~ation

1-9. The-four areas of the Rear panel are Power Control, HP-IB system interface
bus, RS-232 serial interface, and system control source. The power functions
are on the lower right-hand side of the rear panel.
The model 64100A requires
110/220 VAC +/-15%, 48-66 HZ.
The position of the LINE SELECTOR determines
either 110 V (10 AT fuse) or 220 V (5 AT fuse) operation. The power ON/OFF
switch is a rocker type.
1-10. A card cable opening is provided to the outside of the mainframe through
the space between the rear of the top cover and rear panel. Three slots with
clamps are provided for access.
Cable length for option boards is determined
at the factory and are shipped at maximum length.
1-11. There are 13 PC board slots (see figure 1-3). The first three slots have
printed circuit boards installed at the factory.
These PC boards must be
installed in the order given for the 64000 system to operate.
The three
required boards are:
slot A - I/O PC Board
slot B - Display Control PC Board
slot C - CPU PC Board
1-12. For convenience, board identifier labels for the first three boards are
located just above the cardcage on the left-hand side.
The remaining ten
option slots are numbered 0-9.
1-13. The PC boards interface to the system through the motherboard on the
bottom of the card cage.
A cable from the Rear Panel PC board (on the rear
panel) makes connection to the top center connector on the I/O board.
1-14. There is a limit to the number and types of option boards that may be
installed in the cardcage without exceeding the capability of the 400 watt
Power Supply. This limit is determined by the amount of available current from
the power supplies.
Table 1-1 lists the power supply current drain for the
mainframe with only the three mandatory boards installed.
Table 1-1.

Basic Power Supply Current Drain

(NO OPTIONS INSTALLED)
ITEM
Processor ,ROM
I/O
Disp Control,RAM
Keyboard
Display Driver
Rear Panel
Bus Pullups
Subtotal
Available Current
MF 1-2

+12V

+5V

-5V

0·595
0.164
0.640

1.429
0.708
1·533

0.0003

1·500

0.100
0.714
0.070

2.899
4 Amps

4.793
45 Amps

-12V

-3V
0.0003

0.078
0.0064
0.239

0.2457
25 Amps

0.0064
0.239

0.078
1 Amp

0.2457
30 Amps

Model 64100A - General Information
1-15. SPECIFICATIONS.
1-16. The environmental specifications and
Mainframe are supplied in Table 1-2.
Table 1-2.

power requirements for the

64100A

Power and Environmental Requirements

ITEM

OPERATING REQUIREMENTS

Line Voltage

110/220, + or - 15%
Single Phase

Line Frequency

50/60 Hz +15% or -10%

Operating Temperature

o Deg C (32 Deg F) to
40 Deg C (104 Deg F)

Operating Humidity

0% to 80% RH, non-condensing
(max wet bulb temp: 26 Deg C
(78 Deg F)

Power Outlets:
US, Canada, Japan

NEMA 5-15 (15A)

UK

BS 1363 (13A)

Australia, New Zealand

AS C112 (7-5A)

Europe (except UK and
Switzerland)

CEE 7-V11 (10/16A)

Switzerland

SEV 1011 (lOA)

1-17. INSTRUMENTS COVERED BY THIS MANUAL.
1-18. Attached to the instrument is a serial number plate.
The serial number
is in the form:
OOOOA 00000.
It is in two parts; the first four digits and
the letter are the serial prefix and the last five digits are the suffix.
The
prefix is the same for all identical instruments; it changes only when a change
is made to the instrument. However, the suffix is assigned sequentially and is
different for each instrument.
The contents of this manual apply to
instruments with serial number prefix(es) listed under SERIAL NUMBERS on the
title page.
1-19. An instrument manufactured after the printing of this manual may have a
serial number prefix that is not listed on the title page.
This unlisted
serial number prefix indicates the instrument is different from those described
in this manual. The manual for this modified instrument is accompanied by a
yellow Manual Changes supplement. the supplement contains "change information"
that explains how to adapt the manual to the newer instrument.
MF 1-3

Model 64l00A - General Information
1-20. In addition to
change information,
the supplement may
contain
information for correcting errors in the manual.
To keep this manual as
current
and accurate as possible,
Hewlett-Packard recommends that you
periodically request the latest Manual Changes supplement.
The supplement for
this manual is identified with the manual print date and part number, both of
which appear on the manual title page.
1-21. For information concerning a serial number prefix that is not listed on
the title page or in the Manual Changes supplement, contact your nearest
Hewlett-Packard Sales/Service Office.
1-22 RELATED DOCUMENTS.
1-23. The following documents provide addition~~ information pertaining to the
use of the HP 64000 system.
It is recommended that the System Overview Manual
be referenced first.
System Overview Manual
System Software Reference Manual
Installation and Configuration Manual
Editor Manual

~

0

Ir

II

NOTES:
1. DIMENSIONS ARE FOR GENERAL
INFORMATION ONLY. IF DIMENSIONS ARE REQUIRED FOR BUILDING
SPECIAL ENCLOSURES, CONTACT
YOUR HP FIELD ENGINEER.
2. DIMENSIONS ARE IN MILLIMETRES
AND (INCHES).

724
(28-1/2)

508
(20)

0

0=0

o:~:c:::::J

,/

Figure 1-2.

MF 1-4

Mainframe Dimensions

0
0
0
0

DI,

0

u

u

Model 64100A - General Information
REAR PANEL 1/0 A8)

POWER SUPPLY (Al)

FLOPPY OR TAPE CONTROL BOARD (OPTION) (All)
DISPLAY DRIVER (A7)

MICROPROCESSOR BOARD (A3)
DISPLAY CONTROL BOARD (AS)

I/O CONTROL BOARD (AS)

FAN

MOTHERBOARD (A2)

CRT

FLOPPY DISC DRIVE
OR
TAPE TRANSPORT
(OPTION)

,c::JCJCJCJCJCJCJCJ,
SOFTKEYS

c:::J c:::J c=Jc:::J

KEYBOARD (A4)

'--SYSTEM CONTROL./
KEYS

00000000000000

,

DDDDDDDDDDDDDD
DDDDDDDDDDD~
DDDDDDDDDDD
I

I

ASCII KEYBOARD

'"

DD

DDD
DDD

DO

 wAr;~mf.<,(

"

MP9
MP1

J2

Figure 6-1.
MF

6-8

J4

J3

1

MP4
(BOTTOM COVER)

RECP

Mainframe Component Locator (Rear View)

F1

lS;;IP~~' ]

Model 64100A - Replaceable Parts

MOTHERBOARD

KEYBOARD

I

III

I III /I

til "'-=-' ,,,,,
MP5

Figure 6-1.

MODULE
PROM PROGRAMMER
(OPTION)

Mainframe Component Locator (Bottom View)

MF

6-9

Model 64100A - Replaceable Parts

\

\

\

\\
4

Figure 6-2.
MF 6-10

Mainframe Attach Screw Locator (Sheet 1 of 7)

Model 64100A - Replaceable Parts

19

19

19

, . ._ _ _ 8V$1'('"

•

tlO!l{~

19

•
..,._,,,,,.,.,,,.00",,<,

.." _ _ _

..
11

8

Figure 6-2.

18

Mainframe Attach Screw Locator (Sheet 2 of 7)

MF 6-11

Model 64100A - Replaceable Parts

1III Illl])))

Figure 6-2.

MF 6-12

Mainframe Attach Screw Locator (Sheet 3 of 7)

)J~

Model 64100A - Replaceable Parts

2

Figure 6-2.

Mainframe Attach Screw Locator (Sheet

4 of 7)
MF 6-13

Model 64100A - Replaceable Parts

9

9

7

7

F.F:--+--8

Figure 6-2.
MF 6-14

Mainframe Attach Screw Locator (Sheet 5 of 7)

Model 64100A - Replaceable Parts

12--:= =
12-:==

5

Figure 6-2.

Mainframe Attach Screw Locator (Sheet 6 of 7)

MF 6 -15

Model 64100A - Replaceable Parts

3

\

Ht

3

3

\

~

18T:
3~ _

3

18J:

3

[ ;

'h

18~'" "

3

1

3

18-J1i"::t

~.

3

J

18

3

•..

!

UUUJ

, 11m
3

3

14

SYMBOL KEY: • - Screw, 16

Figure 6-2.
MF 6-16

• - Screw,

17

.. - Screw,

2

Mainframe Attach Screw Locator (Sheet 7 of 7)

3

Model 64100A - Replaceable Parts

Table 6-4. Attach Screw Index
Item (see figure 6-2)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

Description and Quantity of Items

Top Cover attach screws (5)
Power Supply attach screws (2) (plus 12 electrical connections; see PWR SUPP Tab)
Bottom Cover attach screws (18)
Prom Programmer hold-down thumbscrew (1)
Display Bezel attach screws (8)
Card cage attach screws (6)
CRT mounting screws (4)
Fan mounting screws (3)
Tape Transport and Floppy Drive mounting screws (4)
Power supply access port (2)
Rear-panel pC board mounting screws (4)
Fan Shroud attach screws (7)
Support Spring attach screws (4)
Keyboard mounting screws (6)
Beeper Speaker mounting screws (3)
Motherboard mounting screws (21)
Motherboard Top Plate mounting screws (6)
Rear-panel attach screws (10)
State/Timing Grounding Clips (2 or 4)

MF 6-17/(6-18 blank)

Model 64100A - Manual Backdating
SECTION VII
MANUAL BACKDATING
7-1. INTRODUCTION.
7-2. This section contains information for adapting
units with earlier serial prefix numbers.

this manual to Mainframe

7-3. MANUAL CHANGES.
7-4. This manual applies directly to the instrument having the same serial
prefix shown on the manual title page.
If the serial prefix of the instrument
is not the same as the one on the title page, find your serial prefix in table
7-1 and make the changes to the manual that are listed for that serial prefix.
When making changes listed in table 7-1, make the change with the highest
number first.
Example:
if backdating changes 1, 2, and 3 are required for
your serial prefix, do change 3 first, then change 2, and finally change 1. If
the serial prefix of the instrument is not listed either in the title page or
in table 7-1, refer to an enclosed MANUAL CHANGES sheet for updating
information. Also, if a MANUAL CHANGES sheet is supplied, make all indicated
ERRATA corrections.

Table 7-1.

Serial No. vs Manual Change No.

Serial Prefix

Make Changes

7-5. This chapter has no backdating
publication date of this manual.

Affects

information for

the

mainframe at

the

MF 7-1/(7-2 blank)

Model 64100A - Service
SECTION VIII
SERVICE
8-1.

BLOCK DIAGRAM DESCRIPTION.

8-2. The
areas:
a.
b.
c.
d.

64100A basic

(see figure 8-1)

Mainframe

is

comprised of the

following

functional

Power Supply
Keyboard and Softkeys
CRT Display
Cardcage
1) Central Processor Unit PCB
2) Input/Output PCB
3) Display Controller and Driver PCB's

e.
f.
g.

Rear Panel PCB
Bus Cabling
Motherboard (signal and power distribution)

8-3. In addition to the
added:
a.
b.
c.
d.
e.
f.

above basic functions,

the

following options can be

Floppy Disc System
PROM Programmer
Emulation Memory
Emulation Memory Control
Emulation Control
Logic Analyzer

8-4. The items listed in the first list are mandatory in order to have an
operating system.
These functions are shown on the left side of figure 8-1.
The items listed in the second list (options) are shown on the right side of
figure 8-1. A brief functional description of each of these items and how they
interrelate is presented in the following paragraphs.
8-5. CENTRAL PROCESSOR UNIT (CPU).
The CPU PC board contains a 16-bit
microprocessor that controls the execution of software/firmware instructions
and also: (1) services interrupt requests from the various external peripheral
devices (e.g., mass storage disc and line printer), (2) services interrupt
requests from the I/O interface circuits (e.g., RS-232, HP-IB, floppy disc
system, emulators, and time-interval monitoring circuits), (3) provides the
basic timing for the overall 64100A system, and (4) controls the transfer of
data and instructions along two independent 16-bit buses (I/O and the IDA
buses).
Additionally, the CPU board stores programs for "boot-up" and
performance verification in an array of on-board ROM's.
The CPU's scratch-pad
memory is located on the Display Controller PC board.

MF 8-1

Model 64100A - Service
8-6. INPUT/OUTPUT (I/O).
The I/O PC board contains the necessary circuits
for: (1) processing the various interrupt requests and informing the CPU that
an interrupt condition exists, (2) providing the· necessary "hand-shake"
operations with RS-232C and HP-IB peripheral devices (e.g., the mass storeage
disc, line printer or teletype), (3) decoding instructions from the CPU and
thereby providing a means by which the CPU can select specific circuits or
peripheral devices to communicate with, and (4) providing an audible alarm to
indicate when certain events have occurred.
8-7. DISPLAY CONTROLLER, DRIVER AND CRT. The display section of the 64100A
system consists of the Display Controller and Display Driver PC boards and the
CRT.
The Display Controller provides the CPU with "scratch-pad" memory
capability via an array of random-access (RAM) read/write memory chips.
In
addition, it generates the various video control signals for displaying system
operation on the CRT display.
The Display Driver PC board develops the
necessary sync, drive and high voltage signals for creating the CRT display.
8-8. REAR PANEL.
The Rear Panel PC board contains: (1) operator-controlled
switches for controlling the mode of operation of the 64100A Mainframe, (2) two
RS-232 interface connectors; one for when the Mainframe is serving as a "modem"
and one for when it is serving as a "terminal", (3) two sets of RS-232 current
loop (i.e., teletype) input/output terminals, (4) a HP-IB interface connector,
and (5) a "loop-back" circuit for testing the RS-232 circuits.
8-9. KEYBOARD.
The 64100A Mainframe uses a keyboard that provides the
operator with three basic means of communicating with the 64000 system: (1) a
77-character ASCI-II typewriter format basic keyboard, (2) a set of edit keys.
and (3) a set of "softkeys" for increasing the versitility and "friendliness"
of the system during system development operations and Mainframe self-testing.
8-10. MAINFRAME SIGNAL DISTRIBUTION.
Two methods are used to distribute and
route the various power, control and data signals throughout the 64100A
Mainframe:
(1) a printed circuit Motherboard and (2) a system of ribbon
cables.
The Motherboard, however, is the primary vehicle for distributing
power and most of the data and control signals to and from the various PC
boards in the Mainframe cardcage.
8-11. The Mainframe Power Supply is mounted directly to the Motherboard by
means of 12 screws that also serve as electrical connections between the power
supply and the Motherboard.
The screw pattern and the associated electrical
signals are shown below:
-12 Vdc
+17 Vdc
GSEN
+40 Vdc
LINE SYNC
LPOP
LIR15

0
0
0

o -3 Vdc
o -5.2 Vdc

0

o +12 Vdc

0
0

o GND
o +5 Vdc

0

Power Supply Connections (Bottom View)

MF 8-2

Model 64100A - Service
8-12. The appropriate power signals are routed to the Mainframe cardcage and
also to the Display Drive PCB (via J14) and the Keyboard PCB (via J15). The
Power Supply provides seven voltages (plus signal ground) and although all
seven voltages are routed to each of the 13 PC boards in the cardcage, not all
of the voltages are used by each card type that can be installed.
The 64100A
block diagram (figure 8-1) and table 8-1 show the voltages used by the various
card types. Also, a component locator is given for the motherboard (figure 8-

2).
Table 8-1.

Card-Type vs Supply Voltage

VDC I/O DISP CPU KYBD DISP TACO/ PROM PRGR EMUL EMUL MEM ANAL EMUL
CONT
DVR FLOPPY
CONT
MEM
CONT
CONT
-3
+5

-5
+12
-12
+17
+40

0
X
X
X
X
0
0

0
X
X
X
0
0
0

0
X
X
X
0
0
0

0
X
0
0
0
0
0

0
0
0
X
0
0
0

0

X
X
X
X

x/o
0

0
X
X
X
X
0
X

0
X
0
0
0
0
0

0
X
0
0
0
0
0

0
X
X
0
0
0
X

0
X
X
X
0
0
0

NOTE:
"XII Indicates Voltage Used
"0" Indicates No Voltage Used

8-13. As with the power supply signals, the control and data signals that are
distributed to the cardcage are also (in most cases) routed to the same pin
location (number) in each of the 13 card slots (see Table 8-5). Of course, not
all signals are used by each cardtype. Thus, if a particular PC board does not
use a certain signal that is tied to pin number 20, for example, this is
handled by simply creating a dead-end at pin 20 (i.e.
there is no conductive
path on the PCB).
In this manner the PC boards can be interchanged freely
(except for the first three slots) without fear of the signals being
incompatible with the board.
Table 8-5 shows the signal distribution for the
cardcage; it does not show the card-type vs. signal relationship since this
can be found from the appropriate circuit schematics.
8-14. SIGNAL ROUTING OFF THE MOTHERBOARD.
For signals that must leave the
Motherboard or the PC boards loaded in the cardcage, a series of ribbon cables
and connectors located on the Motherboard are used.
8-15. DISPLAY DRIVER CONNECTOR J14.
The Display Driver PCB receives its
signals by being plugged directly into J14 which is located on the Motherboard
immediately in front of the power supply.
The signal vs. pin number is shown
in table 8-2.

MF 8-3

Model 64100A - Service
Table 8-2.
Pin No.
1
2

3

4
5

6
7
8

9
10
11

12
13
14
15

Display Driver Connector J14 Signals

Signal
Sig. Gnd.
Sig. Gnd.
Sig. Gnd.
Sig. Gnd.
+5 Vdc
-5 Vdc
-5 Vdc
-5 Vdc
NC
NC
LIVID
LIVID

HDE
HDE
LVID

Pin No.
16
17
18

19
20
21
22
23
24
25
26
27
28

29
30

Signal
LVID
HC
HC
LVSYN
LVSYN
HC
HC
LHSYN
LHSYN
HC
HC
+12 Vdc
+12 Vdc
+12 Vdc
+12 Vdc

8-16. KEYBOARD CONNECTOR J15.
The Keyboard receives its signals via a ribbon
cable plugged into J15 (on the Motherboard) directly below the neck of the CRT.
The signal vs. pin number is shown in table 8-3.
Table 8-3.
Pin No.
1
2
3
4
5
6
7
8

Keyboard Connector J15 Signals
Signal

Pin No.

LPST
Ne
HKA2
HKA6
HKA5
HKA4
HKAl
GND

10
11
12
13
14
15
16

9

Signal
Gnd.
NC
LKA3
LKBCLK
HKA3
HKDN
HKAO
(No Name)

8-17. CONNECTOR J16. Four test signals from cardcage connector pins 73, 75, 77
and 78 are routed through J16 (at rear of Motherboard) to the four BNC
connectors on the Rear-panel. Although all four like-numbered pins in all card
slots are tied together, typically only the LTP and LMC signals, from the
analyzer PCB, on pins 78 (BNC port 1) and 77 (BNC port 2), respectively, are
used. Table 8-4 shows the pin assignment of J16.

MF 8-4

Model 64100A - Service

Table 8-4.
J16 Pin No.
1
2

3

4

5

BNC Connector J16 Signals

Card cage Pin No.

78

Destination
BNC 1

1,2

77

BNC 2

75

BNC 3

73

BNC 4

1,2

6

1,2

7
8

1,2

Signal
LTP
GND
LMC
GND
Not Used
GND
Not Used
GND

MF 8-5

Model 64100A - Service

SYSTEM
MEMORY
(DISC) &
PRINTER

TO
PERIPHERAL

i

i

HP-IB
SYSTEM
BUS

RS-232
SERIAL
BUS
I

.--

I'

- f-

I'

I

I

J1

J2

--

REAR
PANEL
PCB

--

--

--

SLOT A
JZr'"1

l~-

SLOT B

INPUTIOUTPUT
PCB

Pl L
,-

- Pl

l

!n

,U

I

I

~1),

I

~

~~

CPU
PCB

DISP, CaNT.
PCB

.1

I
I
I J15

SLOT

-

h

----Pl

I

PROM
PROGRAMMER
CONTROL
PCB

FLOPPY
CONTROLLER
PCB

I

I

J

Pl

t

I

Pl

I

'1

\

Jk~

Jl;'

EMULATOR
MEMORY
PCB
Pl 1

j

I

- -

-

Jl~

Jlr~

AJZ

EMULATOR
PROBE
PCB

EMULATION
BUS
MEMORY BUS

I

- - ...

--

INTERFACE CONNECTO R
FOR USER SYSTEM

T

PROM
PROGRAMMER
MODULE

FLOPPY
DRIVE
110 BUS

KEY BOARD
ASSY.

--

--

MAINFRAME OPTION PC BOARDS
(CARD SLOTS 0 THRU 9)

~

I
I

I
I

I
I

BASIC 64100A MAINFRAME

J4

--

--

--

--

EMULATOR
MEMORY
CONTROL
PCB

EMULATOR
MEMORY
PCB

1

Pl

I

I

-

Pl

r-,Jf,tS

LOGIC
ANALYZER
PCB

1 _...!,.1

I

1

IIDDRESS

!DJ~~
~

EMULATOR
CONTROL
PCB

I

-

Pl

I

~I

1

I

I
I
I
I
I
I

DIITII
~~NTRDL

I

I

CIIRD SLOT SELECT liND ID ENIIBLE

![)J-

I
I

I BEEPER

+5V

I
I
I
I
I

:
I
I

If

,.

LPDP

"

!

1-

5V
+12V
12V

12V
1+-12V
+17V

+5V
-5V
+12V

1

1
1
1
1
1
1
1
1

I
I

1

I
I
I

I
+rzv

!

_t'ut'

I

POWER
SUPPLY

l__ _

~

:
I
I
I
I
I
I

8-6

~

I

I

--

Figure 8-1.
Mainframe Simplified Block Diagram
MF

DISPLIIY
DRIVER

1
1
1

~-------------------~

--

t

+5V

_t

+5V

!

+5\1

!

+5V
-5V
-3V
-12V
+12V
HOV

i

+5V

I
I
1/8 2

I

------------1--------------------------------------------------------------------------------------------------- __ J

I

LIR15

I

+5V
-5V
j+12V
-12V
HOV

MAINFRAME MOTHERBOARD

1--------

1

LINE
VOLT

+5V
-5V

I
I
I
I
I
I
I
I
I

I
I
I
I

r-e

I

1

/5V
-5V
112V

I

J-!'!If>

.1

I

+5V

I

--

--

I
I

Model 64100A - Service
NOTE: For R1-R5, U1-U3, and J16, each pin that attaches to J13/J1 goes all the way through J1-J13.

SIGNAL
MNEMONIC
GNO
GNO
+5
+5
5
-5
5
-5
3
-3
12
-12
+12
+12
GNO
+17
+40
NC
LAO
LAI
LA2
LA3
LA4
LAS
LA6
LA7
LA8
LA9
LAID
LA11

SIGNAL
MNEMONIC
LA12
LA13
LA14
LA15
GNO
GNO
LOO
LOI
L02
LD3
L04
L05
L06
L07
L08
L09
LOI0
LOll

L012
L013
L014
LOIS
GNO
GNO
LHSYN
LVSYN

LVID
LIVID

GNO
GNO

SIGNAL
MNEMONIC
LBYTE
LUP8
L.STM
LSTB

LWRT
LMSYN
LID
LMAPI
LMAP2
LMAP3
L1RI
L5EL
BNCl
LOPCOOE
SNC2

LPOP
LSCLKl
GNO
GNO
L25MHZ

+5
+5
GNO
GNO

PIN1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Jl
X
X
X

J2

J3

J4

X
X
X
X

X
X
X

X
X

X

x

X
X
X

X
X
X

x
X
X

x
X
X
X
X
X

J15 7

X

X
X

x
x

X
X

X
X

X
X

X
X
X
X
X

x

X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X

X

X
X
X
X
X

X

X

X
X
X

X
X
X

J4

X

X

X

X

X
X
X

X

X

X
X
X
X
X
X
X
X
X

X
X
X
X

X

X

X
X

X

X
X
X

X

X
X
X

X

X

X

X

X

X

X
X

x

X

HOE JI4 PIN 13

X
X

X
X

Jl

J2

J3

X

X
X

x
X

x

X

X
X

X
X
X
X
X
X
X

X

X

X
X
X
X

X

73

x

X

x
x

--

a 14.
X

T -x-x

J4

J5

X

X

x

X

X
X
X
X
X

J7

X

X
X
X
X
X

x

X
X
X

X

X

x

x

X
X
X

X
X
X

X

X

X

X
X
X

X
X
X
X
X

X
X
X
X

X
X

X

--

..

~-

- ...x

I

X

Jll
X

x
X

X
X

X

X
X

X

x

x

X

X

X

-x

X

X

X

X

X
X
X

X

X

X
X
X

X

x

x

J7

J8

x

x
x
X
X

X

X

x
x

X

X
X

X

X

X

X

I

X
X

r

x

x

X
X

X
X

~....

X

X

X

X

X

X

x
x
X

x
X
x
x
x
X
x

X
X

X
X

X

X

J12

J13

X

X
X

x
X
X
X
X
X

x
X
x
X
x

X
X

X
X
X
X
X
X
X

X

X
X

X

X

x
X
x
x
x
X
x
X

X
X

X

J11

J12

J13

x
x

x

x
x
x

X

X
X
X

X
X

x
x

X

Jl 45

X

x

x

x

X

X

x

x

x

X
X
X

x

-x

X
X

X

X

X

X

X

x
x
X
X

x

x

x

X

X

x
X

x

x

X

x

"U1"
PIN 4 to 51
PIN 7 to 46
"U2"
PIN 2 to
PIN 3 to
PIN 4 to
PIN 5 to
PIN 6 to
PIN 7 to
PIN 8 to
PIN 9 to
"U3"
PIN 2 to
PIN 3 to
PIN 4 to
PIN 5 to
PIN 6 to
PIN 7 to
PIN 8 to
PIN 9 to
"J16"
PIN 1 to
PIN 3 to
PIN 5 to
PIN 7 to

51
52
46
45
49
50
47
48

41
42
39
40
44
43
37
38

~
:;

I

1

I
'"

8'

71--

86

+5v

86
r---

51-46-

32-

'"

:;)

I

- - - - 76

+5.

..

~

a::;!

----.J

--- -

---- - - -

.... - - --- ---

61

R5
10K

33

R6
10K

+5v

--- -29 - - - -

30-

:;)

I
1 I

---

27-28-

21- - - - -

- --

-- - - -

22-

19 - - - 20-

-- - - -

.....

---

-

17-18-

--

--- - - - -

--

I

---- --

+5v

ut of the Address Bus Inverters, U25, u26, and part ofU34 can be
observed using the falling edge of HADL for triggering.

*

Using Low ROM address (LRADDR) as a trigger for an Oscilloscope, you should
be able to observe Ul's outputs changing state.
These are the ROM chip
selects.

*

Using Low Data Buffer (LDBUF) as a trigger you can observe the outputs of the
ROMs. and the outputs of the Data Bus Buffers. U21 and U28.

* If the Microprocessor is not outputing a count sequence, then check the
Timing, Control, and Clock Circuits using an oscilloscope.

*

The Clock is two nonoverlapping waveforms.

*

Low Power On Pulse (LPOP), pin 11 of the Microprocessor should be high. Push
the processor reset switch on the I/O board and LPOP should go low
momentarily.

*

Low Bus Request (LBR), pin 18 of the Microprocessor should be high.

*

Low Unsynchronized Memory Complete (LUMC) can be changing states but should
never be high. A high state will cause the Microprocessor to "wait",

*

Low

*

Check the following lines for the state indicated while LPOP is low.
During
initialization, the indicated states must occur to properly initialize the
Microprocessor.
If this does not happen correctly, the Microprocessor may
not count correctly.

Clock frequency is 6.25 MHz.

Memory Sync (LMSYN) should be high.

**************** High State ********************
LBR
LDOUT

CPU 4-4

LSMC
LSTM

LERA
LINT

LUMC
HRD

LIDA 2,4-11,14,15

****** Low State *******
LPBO
HRAL

Model 64100A - Performance Verification and Troubleshooting
Table 4-1. Loop A Signature Analysis
PC Board: CPU/ROM Board
Test failure or circuit: No recognizable display or fails power-up ROM test.
Procedure: Remove Display Driver board.
Move E4 and E5 jumpers to test position.
Remove U27 and U28 (ROM data buffers).
S/A hookup:
START = NEG EDGE CPU BD TP5 (LDBUF)
STOP = NEG EDGE CPU BD TP5 (LDBUF)
CLOCK = pas EDGE CPU BD TP1 (LSTB)
Vh= 15C8
* = Probe Blinking

Sig

Node

U1-1
Ul-2
Ul-3
Ul-4
Ul-5
Ul-6
Ul-7
U1-11
Ul-12
Ul-13
Ul-14
Ul-15

0001
8AOH
OU39
HlCl
FC30
4P04
413F
15C8
0001
0001
0000
0000*

U2-5

15C8

Node

Sig

Node

Sig

U25-2
U25-4
U25-6
U25-8
U25-1O
U25-12

U368
5127
PUA1
2Fi39
476C
3927

U26-2
U26-4
U26-6
U26-8
U26-1O

8638
1P06
4168
F753
3PU7

U33-2
U33-5
U33-6
U33-9
U33-12
U33-15
U33-16
U33-19

338C
2C4U
H2PC
54HO
9UC5
1A81
15C8*
15C8*

U34-5
U34-9

2633
8AOH

U32-2
U32-5
U32-6
U32-9
U32-12
U32-15
U32-16
U32-19

3981
UA19
449U
P6HO
52H3
2F9U
9380
OCCP

U8, 9, 10, 11
REMOVED

ALL ROMs
INSTALLED

U9, 11, 18, 20
REMOVED

U27-2
U27-4
U27-6
U27-8
U27-11
U27-13
U27-15
U27-17

FH75
H7CH
HC41
2UCU
F2H7
5296
97FC
456H

U27-2
U27-4
U27-6
U27-8
U27-11
U27-13
U27-15
U27-17

9PlC
A9UA
H7AO
5910
8571
6969
HH4C
7HU1

U27-2
U27-4
U27-6
U27-8
U27-11
U27-13
U27-15
U27-17

46H6
6CUU
1959
6317
521P
2P47
5U38
2H24

U28-2
U28-4
U28-6
U28-8
U28-11
U28-13
U28-15
U28-17

PPHA
417P
57F2
6917
644F
4862
A77P
C13F

U28-2
U28-4
U28-6
U28-8
U28-11
U28-13
U28-15
U28-17

FCPH
3HUC
H205
9AP8
COU9
7H98
CPFP
09UH

U28-2
U28-4
U28-6
U28-8
U28-11
U28-13
U28-15
U28-17

308U
693H
907U
P647
F10H
2042
OF08
AH79

CPU 4-5

Model 64100A - Performance Verification and Troubleshooting

Table 4-2. ROM Signature Analysis Troubleshooting

ALL ROMS
INSTALLED

NOTE 1:
REMOVE U8, 9, 10, 11
PERFORM SA

TAKE SA

NOTE 2:
REPLACE U8, 10
REMOVE U18, 20
PERFORM SA

SA ON U27
BAD
POSSIBLY
U8, 9, 18, 19

SA ON U28
BAD
POSSIBLY
U10, 11, 20, 21

ALL SA GOOD
STOP

DO NOTE 1

DO NOTE 1

SA ON U27
BAD
POSSIBLY
U18,19

SA ON U27
GOOD
POSSIBLY
U8,9

SA ON U28
BAD
POSSIBLY
U20,21

SA ON U28
GOOD
POSSIBLY
U10,11

DO NOTE 2

DO NOTE 2

DO NOTE 2

DO NOTE 2

l

l

l

1

I

SA ON U27
BAD

SA ON U27
GOOD

SA ON U27
BAD

SA ON U27
GOOD

SA ON U28
BAD

SA ON U28
GOOD

SA ON U28
BAD

SA ON U28
GOOD

REPLACE U19

REPLACE U18

REPLACE U8

REPLACE U9

REPLACE U21

REPLACE U20

REPLACE U10

REPLACE U11

CPU 4-6

Model 64100A - Adjustments

SECTION V
ADJUSTMENTS
5-1. INTRODUCTION.
5-2. This section describes the adjustment required to return the +7 volt
regulator to normal operating capability after repairs have been made on the
CPU board.
5-3. SAFETY REQUIREMENTS.
5-4. Although
this
instrument
has
been designed in accordance
with
international safety standards, general safety precautions must be observed
during all phases of operation, service, and repair of the instrument. Failure
to comply with precautions listed in the Safety Summary at the front of this
manual (Mainframe) or with specific warnings given throughout the manual could
result in serious injury or death.
Service adjustments should be performed
only by qualified service personnel.
5-5. EQUIPMENT REQUIRED.
5-6. A Voltmeter capable of .01 Volt accuracy
Procedure.

is

required for this Adjustment

5-7. +7V ADJUSTMENTS.
5-8. There is only one Adjustment on the Central Processing Unit Board.
for the Regulator that provides +7V for the Microprocessor.
5-9. The Test Point,
the P.C. Board.

labeled +1V,

It is

is located in the center of the top edge of

5-10. The positive lead of the voltmeter is connected to the +7V Test Point,
and the negative lead is connected to ground.
R2 (located near the +7V Test
Point) is adjusted for +6.7V to +7.3V.

CPU 5-1/(5-2 blank)

Model 64100A - Replaceable Parts
SECTION VI
REPLACEABLE PARTS
6-1. INTRODUCTION.
6-2. This section contains information concerning replaceable parts. Table 6-1
lists abbreviations used in the parts list and throughout the manual. Table 6-2
lists all replaceable parts in reference designator order. Table 6-3 contains
the names and addresses that correspond to the manufacturers' five digit code
numbers.
6-3. ABBREVIATIONS.
6-4. Table 6-1 lists abbreviations used in the parts list, on the schematics
and throughout the manual.
In some cases, two forms of the abbreviations are
used: one, all in capital letters, and two, partial or no capitals. This occurs
because the abbreviations in the parts list are always capitals.
However, in
the schematics and other parts of the manual, other abbreviation forms are used
with both lowercase and uppercase letters.
6-5. REPLACEABLE PARTS LIST.
6-6. Table 6-2 is the list of replaceable parts and is organized as follows:
a. Chassis-mounted
designation.

parts

in

alphanumerical

b. Electrical assemblies and their
order by reference designation.

order

components

in

by

reference

alphanumerical

c. Miscellaneous parts.
6-7. The information given for each part consists of the following:
a. The Hewlett-Packard part number and the check digit (CD).
b. The total quantity (Qty) in the instrument.
c. The description of the part.
d. A five-digit code that indicates the manufacturer.
e. The manufacturer's part number.
6-8. The total quantity for each part is
appearance of the part number in the list.

given

only

once at

the

first

6-9. For ordering information see Section VI of the Mainframe Tab.

CPU 6-1

Model 64100A - Replaceable Parts

Table 6-l. Abbreviations
REFERENCE DESIGNATORS
A
B
BT
C
CP
CR
DL
OS
E

~

assembly

= motor
~ battery
:::: capacitor
= coupler
= diode
~ delay line
= device signaling (lamp)
=::: mise electronic part

F
FL
IC
J

K
L
LS
M
MK

MP
P

fuse
filter
= integrated circuit
~ jack
~ relay
= inductor
~ loud speaker
= meter
=::: microphone
=

~

Q

R
RT
S
T
TB
TP

= mechanical

part
plug
= transistor
= resistor
= thermistor
=::: switch
= transformer
= terminal board
~ test point
~

U
V

= vacuum, tube, neon

VR
W
X
Y
Z

bulb, photocell, etc
voltage regulator
~ cable
= socket
~ crystal
= tuned cavity network

= integrated circuit

~

ABBREVIATIONS
A
AFC
AMPL

= amperes
= automatic frequency

control
= amplifier

BFO
BE CU
BH
BP
BRS
BWO

= beat frequency oscillator

CCW
CER
CMO
COEF
COM
COMP
COMPL
CONN
CP
CRT
CW

= counter-clockwise

~

beryllium copper
= binder head
~ bandpass
= brass
= backward wave oscillator

= ceramic
= cabinet mount only

H
HOW
HEX
HG
HR
HZ

henries
hardware

N/O

= normally open

=

NOM

= nominal

~

hexagonal

NPO

negative positive zero
(zero temperature
coefficient)
= negative-positivenegative
= not recommended for
field replacement
~ not separately
replaceable

~

= mercury
~
=:::

houris)
hertz

NRFR
IF
IMPG
INCD
INCL
INS
INT

=
=

intermediate freq
impregnated
= incandescent
~ includels)
= insulation(edl
= internal

= coeficient

= common

NPN

K

~ kilo~1000

complete
= connector
= cadmium plate
~ cathode-ray tube
= clockwise

LH
UN
LK WASH
LOG
LPF

left hand
= linear taper
= lock washer
~ logarithmic taper
= low pass filter

DEPC
DR

= deposited

~ milli~10-;J

ELECT
ENCAP
EXT

electrolytic
= encapsulated
= external

M
MEG
MET FLM
MET OX
MFR
MHZ
MINAT
MOM
MOS
MTG
MY

NSR
OBD
OH
OX

=

= order by description
= oval head
= oxide

= composition
~

carbon

= drive
~

F
FH
FIL H
FXD

~

G
GE
GL
GRD

giga (109)
= germanium
~ glass
~ groundled)

~
~
~

~

CPU 6-2

farads
flat head
fill ister head
fixed

~

~ meg~106

~

PH BRZ
PHL
PIV
PNP

metal film

= metallic oxide

P/O

= manufacturer

POLY
PORC

= mega hertz
= miniature
= momentary

= metal

oxide substrate
= mounting
~ "mylar"

N

= nano (10-9)

N/C

~ normally closed
::::: neon
~ nickel plate

NE
NIPL

P
PC
PF

P~S

POT
PP
PT
PWV
RECT
RF
RH

RMO
RMS

= rack mount only

RWV

=

reverse working
voltage

S-B
SCR
SE
SECT
SEMI CON
SI
SIL
SL
SPG
SPL
SST
SR
STL

~

slow-blow

= root-mean square

= screw

= selenium
= section(s)

= semiconductor
= silicon
= silver
~

slide

= spring
= special

= stainless steel
~
~

split ring
steel

peak
= printed circuit
~ picofarads~ 10-12
farads
~ phosphor bronze
~ phillips
= peak inverse voltage
= positive-negativepositive
~ part of
~ polystyrene
= porcelain
= position(s)
= potentiometer
~ peak-to-peak
= pOint
~ peak worki ng voltage

WI

~

= rectifier

W
WIV

= working inverse

WW

= wirewound

W/O

= without

~

TA
TO
TGL
THO
TI
TOL
TRIM
TWT

= tantalum

U

= micro=10-B

VAR
VDCW

= variable
= de working volts

= radio

frequency
::::: round head or
right hand

time delay
toggle
~ thread
= titanium
= tolerance
= trimmer
= traveling wave tube
~
~

~

with
watts
voltage

Model 64100A - Replaceable Parts

MP2~O
I

~

MP1 ...........

I

I
I

I.........-H1 (6)

eI
I

U30~

J2~

I

H1~e
I

Figure 6-1. Illustrated Parts Breakdown

CPU 6-3

Model 64100A - Replaceable Parts
Table 6-2. Replaceable Parts
Reference
Designation

HP Part
Number

c Qty
0

Mfr
Code

Description

Mfr Part Number

A3

64100-66532

Cl
C2
C4
C5

0160-2308
0160-5321
1>160-5321
0160-5321
0160-5321

C6
C7
C8
C9
Cl0

0160-5321
0160-5321
0160-5321
0160-5321
0160-5321

Cll
C12
C13
C14
C15

0160-5321
0160-3470
0160-3470
0160-5321
0160-5321

,~I~

C16
C17
C18
C19
C20

0140-0200
0140-0200
0160-5321
0160-5321
0160-5321

10

C21
C22
C23
C24
C25

0160-5321
0160-5321
0160-5321
0160-5321
0180-0347

8
8

C26
C27
C28
C29, C30

0180-0347
0180-0116
0160-5321
0180-0347

!I

Hl
H2
H3

2260-0009
2200-0143
0360-0679

3
0
3

7
1
6

NUT-HEX-W/LKWR 4-40-THD .094-IN-THK
SCREW-MACH 4-40 .375-IN-LG PAN-HD-POZI
TERMINAL-STUD SPCL-STDF PRESS-MTG

J2

1251-4388

9

1

CONNECTOR 3-PIN M POST TYPE

28480

1251-4388

Ll

9140-0112

2

1

COIL-MLO 4.7UH 10%

28480

9140-0112

MPl
MP2
MP3
MP4
MP5
MP6

5040-6069
1480-0116
09825-67908
1205-0338
0340-0511
3050-0791

4
8
8
4
0
6

2
2
1
1
1
1

EXTRACTOR, BLUE
PIN-GRV .062-IN-DIA .25-IN-LG-STL
GASKET, MICROPROCESSOR
HEAD SI NK SGL PLSTC-PWR-C8
INSULATOR-XSTR KAPTON
INSULATOR-XSTR NYLON

28480
28480
28480
28480
28480
28480

5040-6069
1480-0116
09825-67908
1205-0338
0340-0511
3050-0791

Rl
R2
R3
R4
R5

0757-0282
2100-3350
0757-0422
0698-3446
0757-0200

5
5
5
3
7

1
1
1
1
3

RESISTOR 221 1% .125W F TC~0±100
RESISTOR-TRMR 200 10% C SIDE-ADJ 1-TRN
RESISTOR 909 1% .125W F TC~0±100
RESISTOR 3831% .125W F TC~0±100
RESISTOR 5.62K 1% .125W F TC~0±100

24546
28480
24546
24546
24546

C4-1I8-TO-221 R-F
2100-3350
C4-1/8-TO-909R-F
C4-1/8-TO-383R-F
C4-1/8-TQ-5621-F

R6
R7
R8
R9
Rl0

0757-0279
0698-3432
0757-0200
0757-0200
0698-3432

0
7
7
7
7

2
2

RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR

3.16K 1% .125W F TC~0±100
26.11% .125W F TC±0±100
5.62K 1% .125W F TC~0±100
5.62K 1% .125W F TC~0±100
26.11% .125W F TC~0±100

24546
03888
24546
24546
03888

C4-1/8-TO-3161-F
PME55-1/8-TO-26R 1-F
C4-1/8-TO-5621-F
C4-1/8-TO-5621-F
PME55-1/8-TO-26Rl-F

Rll
R12
R13
R14
R15
TPl thru 22

0757-0280
0757-0280
0757-0280
0757-0279
0757-0260
0360-0535

3
3
3
0
3 ',
0

4

22

RESISTOR lK 1% .125W F TC~0±100
RESISTOR lK 1% .125W F TC~0±100
RESISTOR lK 1% .125W F TC±0±100
RESISTOR 3.16K 1% .125W F TC~0±100
RESISTOR lK 1% .125W F TC~O±l00
TERMINAL TEST PONT'PCB '

24546
24546
24546
24546
24541'00000

C4-1/8-TO-l00l-F
C4-1/8-TO-l 001-F
C4-1/8-TQ-l00l-F
C4-1/8-TO-3161-F
C4-1/8-to-l00l-F
ORDER BY DESCRIPTION

Ul
U2
U3
U4
U5

1820-1281
1820-1112
1820-0693
1820-0693
1820-2024

2
8
8
8
3

2
1
3
3
4

IC
IC
IC
IC
IC

01295
01295
01295
01295
01295

74LS139
74LS74
74S74
74S74
74LS244

U6
U7

1820-2024
1810-0275

3
1

4
1

IC DRVR TTL LS LINE DRVR OCTL
NETWORK RES 10-SIP 1.0K OHM X 9

01295
01121

74LS244
210Al02

U9
Ul0

64100-80028
84100-80029

1
2

1
1

ROM 0
ROM 1

28480
28480

64100-80028
64100-80029

U12
U13
U14
U15

182Q-1243
1820-0693
1820-1112
1820-1112

6
8
8
8

1

IC
IC
IC
IC

01295
01295
01295
01295

C3

1

BOARD ASSEMBLY, CPU

28480

64100-66532

1
18

I!I
18

CAPACITOR-FXD
CAPACITOR-FXD
CAPACITOR-FXD
CAPACITOR-FXD
CAPACITOR-FXD

36PF ±5% 300VDC MICA
.01UF +80-20% 100VDC CER
.01UF +80-20% 100VDC CER
.01UF+80-20% lOOIVDC CER
.01UF+80-20% l00VDC CER

26480
26480
26480
28480
28480

0160-2308
0160-5321
0160-5321
0160-5321
0160-5321

8
81
8'
81
8,

CAPACITOR-FXD
CAPACITOR-FXD
CAPACITOR-FXD
CAPACITOR-FXD
CAPACITOR-FXD

.01UF
.01 UF
.01UF
.01UF
.01UF

+80-20%
+80-20%
+80-20%
+80-20%
+80-20%

100VDC
100VDC
100VDC
100VDC
100VDC

CER
CER
CER
CER
CER

28480
28480
28480
28480
28480

0160-5321
0160-5321
0160-5321
0160-5321
0160-5321

CAPACITOR-FXD
CAPACITOR-FXD
CAPACITOR-FXD
CAPACITOR-FXD
CAPACITOR-FXD

.01UF
.01 UF
.01UF
.01 UF
.01 UF

+80-20%
+80-20%
+80-20%
+80-20%
+80-20%

100VDC CER
50 VDC CER
50 VDC CER
100VDC CER
100VDC CER

28480
28480
28480
28480
28480

0160-5321
0160-3470
0160-3470
0160-5321
0160-5321

CAPACITOR-FXD
CAPACITOR-FXD
CAPACITOR-FXD
CAPACITOR-FXD
CAPACITOR-FXD

390PF ±5'10 300VDC MICA
390PF ±5% 300VDC MICA
.01 UF +80-20% 100VDC CER
.01UF +80-20% 100VDC CER
.01 UF +80-20% 100VDC CER

72136
72136
28480
28480
28480

DM15F391J0300WV1CR
DM15F391J0300WV1CR
0160-5321
0160-5321'
0160-5321

CAPACITOR-FXD
CAPACITOR-FXD
CAPACITOR-FXD
CAPACITOR-FXD
CAPACITOR-FXD

.01UF +80-20% 100VDC
.01 UF +80-20% 100VDC
.01UF +80-20% 100VDC
.01UF +80-20% 100VDC
10UF ±10% 20VDC TA

CER
CER
CER
CER

28480
28480
28480
28480
56289

0160-5321
0160-5321
0160-5321
0160-5321
150D106X9020B2

CAPACITOR-FXD
CAPACITOR-FXD
CAPACITOR~FXD
CAPACITOR-FXD

10UF ±10% 20VDC TA
6.8UF ±10% 20VDC TA
.01UF +80-20% 100VDC CER
10UF ±10% 20VDC TA

56289
28480
28480
56289

150Dl06X9020B2
0180-0116
0160-5321
150Dl06X9020B2

00000
00000
28480

ORDER BY DESCRIPTION
ORDER BY DESCRIPTION
0360-0679

12
5

, .1

2

I~9
8

I~
31

.'

2

Q~33

.155DX .375 LG-NOM

DCDR TTL LS 2-TO-4-LlNE DUAL 2-INP
FF TTL LS D-TYPE POS-EDGE-TRIG
FF TTL SO-TYPE POS-EDGE-TRIG
FF TTL SO-TYPE POS-EDGE-TRIG
DRVR TTL LS LINE DRVR OCTL

GATE TTL LS AND TPL 3-INP
FF TTL 8 D-TYPE POS-EDGE-TRIG
FF TTL LS D-TYPE POS-EDGE-TRIG
FF TTL LS 0-TYPE POS-EDGE-TRIG

See introduction to this section for ordering information

CPU 6-4

SN74LS15N
74874
74LS74
74LS74

Model 64100A - Replaceable Parts
Table 6-2. Replaceable Parts (con't)
c aty

Mfr
Code

HP Part
Number

0

U16
U17

1820-1322
181G-0276

2
2

1
1

IC GATE TTL 8 NOR QUAD 2-INP
NETWORK-RES IO-SIP 1.5K OHM X 9

01295
01121

74502
210A152

U22
U23
U24
U25

1820-1281
1810-0280
1810-0280
1820-1199

2
8
8
1

1
2
2

IC DCDR TTL LS 2-TO-4-LlNE DUAL 2-INP
NETWORK-RES IO-SIP 10.0K OHM X 9
NETWORK-RES lG-SIP 10.0K OHM X 9
IC INV TTL LS HEX 1-INP

01295
01121
01121
01295

74LS139
210Al03
210Al03
74LS04

U26
U27
U28
U29
U30

182G-1199
182G-2024
182G-2024
182G-1204
5061-3011

1
3
3
9
4

1
1

IC INV TTL LS HEX 1-INP
IC DRVR TTL LS LINE DRVR OCTL
IC DRVR TTL LS LINE DRVR OCTL
IC GATE TTL LS NAND DUAL 4-INP
MICROPROCESSOR W/HEAT SINK

01295
01295
01295
01295
28480

74LS04
74LS244
74LS244
74LS2O
5080-3011

U31
U32
U33
U34
U35

1820-1288
1820-2102
182G-2102
182G-1917
182G-1198

9
8
8
1
0

1
2
1
1

IC
IC
IC
IC
IC

04713
01295
01295
01295
01295

MMH0026CL
74LS373
74LS373
74LS240
74LS03

U36
U37
VRI

1820-0539
1820-1307
1826-0393

1
3
7

1
1
1

IC BFR TTL NAND QUAD 2-INP
IC SCHMITT-TBIG TTL S NAND QUAD 2-INP
IC RGL TR .TO=220

01295
01295
27014

7437
74S132
LM317T

El thru E6
XU9
XU10
XU27
XU28

8151-0013
1200-0567
1200-0567
1200-0639
1200-0639

91

6
2

JUMPER CLIP
SOCKET-IC 24-CONT
SOCKET-IC 24-CONT
SOCKET-IC 2O-CONT
SOCKET-IC 2O-CONT

28480
28480
28480
28480
,28480

8151-0013
1200-0567
1200-0567
1200-0639
200-0639

Reference
Designation

Description

DRVR TTL CLOCK DRVR TTL-TO-MOS HNP
LCH TTL LS D-TYPE OCTL
LCH TTL LS 0-TYPE OCTL
BFR TTL LS LINE DRVR OCTL
GATE TTL LS NAND QUAD 2-INP

Mfr Part Number

MISCELLANEOUS PARTS

~I

8'
8;

12

DIP
DIP
DIP
DIP

DIP-SLDR
DIP-SLDR
DIP-SLDR
DIP-SLDR

1

See introduction to this section for ordering information

CPU 6-5

Model 64100A - Replaceable Parts

Table 6-3. Manufacturers' Codes
Mfr
No.
00000
01121
01295
03888
04713
24546
27014
28480
56289
72136

CPU 6-6

Manufacturer Name
ANY SATISFACTORY SUPPLIER
ALLEN-BRAOLEY CO
TEXAS INSTR INC SEMICOND CMPNT DIV
KDI PYROFILM CORP
MOTOROLA SEMICONDUCTOR PRODUCTS
CORNING GLASS WORKS (BRADFORD)
NATIONAL SEMICONDUCTOR CORP
HEWLETT-PACKARD CO CORPORATE HO
SPRAGUE ELECTRIC CO
ELECTRO MOTIVE CORP SUB IEC

Zip
Code

Address
MILWAUKEE
DALLAS
WHIPPANY
PHOENIX
BRADFORD
SANTA CLARA
PALO ALTO
NORTH ADAMS
WILLIMANTIC

WI
TX
NJ
AZ
PA
CA
CA
MA
CT

53024
75222
07981
85062
16701
95051
94304
01247
06226

Model 64100A - Manual Changes

SECTION VII
MANUAL CHANGES
7-1.

INTRODUCTION.

7-2. This manual has no backdating
pUblication date of this manual.

information for the

CPU manual

at

the

CPU 7-1/(7-2 blank)

Model 64100A - Service
SECTION VIII
SERVICE
8-1. INTRODUCTION.
8-2. This section contains information for troubleshooting
Model 64100A's Central Processing Unit (CPU).

and repairing the

8-3. The CPU Block Diagram (see figure 8-2), Component Locator (see figure 86), Schematic (see figure 8-7), and other service information are provided on
fold-out service sheets to help you in servicing the CPU.
8-4. BLOCK DIAGRAM THEORY.
a. Microprocessor U30 controls Data
Input/Output Bus.

and Addresses

on both the CPU bus and the

b. Microprocessor Clock Generator U31, U37A,B,D develop LCLK1 and LCLK2.
c. Low Power On Pulse Generator U3A, U16A,B and part of U34 syncronize LPOP
with LCLK1.
The Generator also insures that any pulse from LPOP has a
minimum pulse width of approximately 35nS.
d. Low Upper Byte, part of U34, indicates to the device being addressed if the
information on the Data Bus is either the upper or lower byte of a word.
e. Low Byte part of U34, and U14B indicates to the device being addressed the
length of the word on the Data Bus: eight or 16 bits.
f. Timing Circuits U4A, U12C, U13, U14A, U15, U16D, part of U34, U36B,C,D, and
U37C develop the signals necessary for the Microprocessor to communicate
with the devices connected to it, i.e., Display Controller, Prom Programmer,
Proms, etc.
g. Addresses Latches U32
and U33 Latch the address from the Instruction/Data/Address Bus.
The information in these Latches is routed out
on the CPU multiplexed address/data Bus.
h. Address Buffers U25,
the ROM Addresses.

u26,

and P/O U34 provide the inversion for developing

i. Chip Select U1 (NOT USED) decodes the CPU Address Bus allowing the CPU's
Counter to select the ROM for execution of Software.
NOTE: The 27128 ROMs
presently used are jumpered to ground thru E6. If the 2764 ROMs (4) are used
then jumper E6 must be moved to position A.

CPU 8-1

Model 64100A - Service

j. ROMs U9 and UlO contain utility routines for power up of the Mainframe, and
Performance Verifications for the Mainframe including the Floppy and Tape
Control and Drive Options.
k. Data Buffers U27 and u28 Provide isolation
outputs and the CPU Data Bus.

buffering

between

the ROMs

1. Test/Reset Circuit Ul6c and U35 will cause the Microprocessor to count from
0020 Hex to 3COO Hex when the Test Mode jumpers E4 and E5 are in the TEST
position and U27 and u28 are removed.
m. SA latch U2 is used as an aid in taking signature analysis.
n. Input/Output Bus U3A,u4B,U5, and u6 is the path the Microprocessor uses to
communicate with the I/O Board, which in turn communicates with the
Periphial Devices (Disc, Printer, other Stations).

CPU 8-2

Model 64100A - Service

1/0 BUS

<'1'

z....

I

<> :::;

I

00

~

I SCHEMATIC

UJ

:;J

III

:::;

SCHEMATIC 1

;.

.... III

0

o

:::;

,

";'1";>-

~

I

CONTROL

ADDRESS

-'

2

I

..
II:

~I~
:il~

I
I
I
I

...-' --' !!O-' ::;-'<>

"l:
-' II:

-'

~

¢

<>

BUFFER

BUFFER

0

:::;

I

l>-

L

I
I
,

Gp

I

",7

7-

ADDR
LATCH

I
I

-)

~AO-15

AD DR
BUFFERS

HAO-~

I

+7V

REG

+12

,

7

I

MICROPROCESSOR

;<
±5_

N

0

"-'0

l:

l:

-'

"-

"0
"-

"-

-'

....W

::;

III

UJ

....

>

0

III

-'

-'

-'

I
I

0

<>
a:

::;
:;J

l:

-'

I
r

CLOCK DRIVER

I
I
I
I

~/y

I

U34

LPr

;<
-'
0

~

~

LBYTE
SYNC

I

S.A. LATCH

r

LCLK2

LWROM

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8-1-8

Figure 8-l.
CPU Board Block Diagram
CPU 8-3

Model 64100A - Service
8-5. THEORY OF OPERATION.
8-6. GENERAL.
8-7. The Microprocessor used in the Model 64100A Mainframe CPU is made by
Hewlett-Packard.
The Microprocessor uses INMOS II Silicon
on Sapphire
technology.
The version being used in the Model 64100A does not have
Calculator Math Capability.
The Microprocessor can be thought of as two
Microprocessors combined on one substrate.
(1) The basic Microprocessor,
called the CPU Processor, has a 16 bit bi-directional bus with the Data and
Address time multiplexed.
The 16 bit bus is demultiplexed into a 16 bit Data
Bus and a 16 bit Address Bus.
The Data Bus, Address Bus, and some Control
Lines, e.g., LWRT, LSTB, etc., are called the CPU Bus.
The CPU Bus is
distributed throughout the Mainframe over the Mother Board.
(2) The second
half of the Microprocessor is called the Input/Output Processor.
The I/O
Processor has a 16 bit bi-directional data bus, with a 4 bit address bus. Along
with the 4 bit address bus, there are two other control lines that can be used
to expand the I/O Address Bus.
In addition there are control lines that are
independent of the CPU Control Lines. The I/O Data Bus, Address Bus, and I/O
Control Lines form the I/O Bus.
8-8. CPU POWER SUPPLIES.
8-9. The CPU operates on +5V, -5V, +12V, and +7V. The +7V supply is derived
from an on board regulator (VR1) that is supplied by +12V on the CPU board. All
other supplies are derived from the power supply assembly
8-10. CLOCK GENERATOR.
8-11. Clock Generators U31 and U37A,B,D develop LCLK1 and LCLK2 (see figure 81).
The Clock is derived from LSCLK1 (from the Display Control Board).
The
frequency is 6.25 MHZ. LCLK1 and LCLK2 are non-overlapping signals.

~64_14

LCLK1

LCLK2

96

-1"64-1 4 96---1

I

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NOTE: TIMES ARE IN NS. THEY ARE TYPICAL
OF THE PROP DELAY THROUGH U37.

Figure 8-2.

CPU 8-4

Clock Generator Timing

Model 64100A - Service
8-12. LOW POWER ON PULSE GENERATOR.
8-13. UJA, u16A,B and PIO U34 form the Low Power On Pulse Generator. The Pulse
Generator synchronizes LPOP with LCLK1, and ensures LPOP has a minimum pulse
width of approx.
35 nS.
LPOP is generated by the Power Supply and the Ilo
board in the event the system software is not running correctly. In either
case, LPOP will cause the Microprocessor to be initialized.
8-14. LOW BYTE SYNC.
8-15. Ul4B synchronizes Low Byte with LCLK2.
8-16. MEMORY CYCLE TIMING.
8-17. U4A, Ul2C, Ul3, Ul4A, Ul5, Ul6D, part of U34, U36B,C,D and U37C develop
the signals necessary or the Microprocessor to communicate with the devices
connected to it, i.e., ROM, PROM Programmer, Display Controller, etc. These
signals are developed
from LCLK1,
LCLK2,
and five signals from the
Microprocessor; HRAL, LSTM, LPDR, HSYNC, and HRD. The timing relationship of
the signals needed for the Microprocessor to communicate are shown in figure
8-3 and 8-4. These signals are listed in table 8-1.
8 -18. CPU ADDRESS BUS.
8-19. Latches
U32 and U33 capture
the address from the Low Instruction/Data/Address Bus (LIDA) when High Address Latch (HADL) goes high.
8-20. ADDRESS BUFFERS.
8-21. Buffers U25, u26, and part of U34 inverts the Addresses for the ROMs.
8-22. CHIP SELECT.
8-23. Data selector Ul decodes the addresses for ROM chip selection.
8-24. ROMS.
8-25. U9 and UlO contain utility routines for power-up of the Mainframe, and
Performance Verifications for the Mainframe and the floppy and tape Control and
Drive options.
Jumpers E1, E2 and E3 have several combinations to allow
different storage capacity of ROMs to be used.
Jumper information is given on
the two CPU schematics.

CPU 8-5

Model 64100A - Service

4

LOW CLOCK 1
2

3

6

4

LOW CLOCK 2
LOW INSTRUCTION/
DATA/ADDRESS
LOW UPPER BYTE
HIGH READ
HIGH START
EXTERNAL MEMORY
HIGH ADDRESS LATCH
LOW START MEMORY
LOW PROCESSOR
BUFFER OUT
LOW PROCESSOR DRIVE

-----.:----....;,...1-

....

LOW MEMORY SYNC

ff/ff/ff/ff////W////#41

I
1

LOW STROBE
LOW UNSYNCHRONIZED
MEMORY COMPLETE

:

LOW DATA BUFFER

Figure 8-3.

CPU 8-6

I

W////////////
////4'
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Typical Write Memory Cycle

__~______~____

Model 64100A - Service

4

LOW CLOCK 1

LOW CLOCK 2
I

I

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LOW INSTRUCTIONI
DATA/ADDRESS

&&0<"'-~AD~D-:-RE~SS----">W~m,-_ _
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____________~____~____~-J~~0~~~~~~~0~~~

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HIGH START
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HIGH ADDRESS LATCH
LOW START MEMORY
LOW PROCESSOR
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LOW PROCESSOR DRIVE

$ff//$/////$////ffij

LOW MEMORY SYNC

w//////MYff/////4'

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LOW UNSYNCHRONIZED
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Figure 8-4.

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Typical Read Memory Cycle

8-26. DATA BUS.
8-27. Buffers U27 and U28 provide buffering between the ROM outputs and the CPU
Data Bus.
Because the Data Bus has addresses multiplexed on it, the data can
only be on the Data Bus at certain times.
Therefore, the outputs of U27 and
u28 are active only when Low Data Buffered (LDBUF) is true.
CPU 8-7

Model 64100A - Service
8-28. TEST/RESET.
8-29. u16c and U35 will cause the Microprocessor to increment the address lines
from 0020 HEX to 3COO Hex, then reset to 0020 Hex and count to 3COO Hex
again. This will continue as long as Jumpers, E4 and E5, are in the Test
mode and the buffers U27 and u28 are removed or disabled. The test mode is used
by a service person when troubleshooting with signature analysis (see Section
IV) .
8-30. INPUT/OUTPUT BUS.
8-31. Activity on the Input/Output Bus is Software dependent.
However, when
there is activity, the timing sequence is predictable.
Timing Diagrams for
both Read and Write Cycles are shown in figure 8-5.
8-32. SA LATCH.
8-33. The SA latch U2 is used while taking signature analysis for setting up
the intervals required to get valid signatures.
See CPU section IV for
information on the use of SA on the CPU board.
LOW DATA OUT

~~--------------------------~

LOW DATA OUT DELAYED

- ...._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.......

LOW PERIPHERAL
ADDRESS BUS

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~
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LOW INTERFACE CONTROL

~~~~~~~~~~~~~~~~

LOW INPUT
OUTPUT DATA
LOW INPUT OUTPUT
STROBE
LOW INTERRUPT
TYPICAL I/O WRITE CYCLE

LOW DATA OUT
LOW DATA OUT DELAYED
LOW PERIPHERAL
ADDRESS BUS
LOW INTERFACE CONTROL

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CPU Schematic 1 (1 of 2)
CPU 8-15

Model 64100A - Service

J1
49

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Figure 4-3. Total PV Display

DSP 4-8

o

Performance Verification - Model 64100A
4-13. Running the Total PV.
To run all the tests shown on the display, press
the "cycle" softkey.
Each test category is executed and the results are
displayed. A complete cycle requires approximately fifteen seconds. Press the
"next text" softkey to halt the iterations.
4-14. Using the Total PV Results.
When the tests are complete, exam ine the #
Fail column. All entries zero indicate that approximately 9910 of the circuitry
has been checked and no errors have been found.
4-15. A non-zero value represents the number of errors detected in the test
category.
Determine the exact cause of the error by running the failed test
category and viewing the results in detail.
Do this by positioning the
highlight line over the failed test category and pressing the "disp test"
softkey. This places the display in the next lower level where the "start"
initiates the PV test and the "exit test" ends the PV test.
4-16. OPERATION TEST.
4-17. Display.
This display shows the four Operation test categories and the
test results. Use the display to view test conditions in detail.

Host MeMory PerforMance VerIfIcation
Bank 1 Operation Test

32K MeMory Expander In cord slot 410
Results

(cuMulative)

Datil
Address

Po t ter'n

Datu· 0000 (0000)
Addr ••• ·OOOO (0000)

Datu- 0000 (0000)

Da •• -

0000 (0000)

Figure 4-4. Operation Test Display
4-18. Running the Operation Tests. The Operation tests are started by pressing
"disp test" and then the "start" softkeys. To stop the tests and return to the
Displi"y, press the "exit_test" softkey.
Each iteration of the tests takes
less than one second.
DSP 4-9

Performance Verification - Model 64100A
4-19. Using the Operation Test Results.
The total number of errors detected
during the tests is shown in the # Fail column. Each error code in the Results
column represents a single failure encountered during the last iteration. Each
error code in the (cumulative) column represents the sum of all errors detected
during the test.
Cumulative error codes that differ from Results error codes
indicate multiple, or intermittent errors. When the error codes are the same,
the errors are systematic. Refer to the appropriate test for an explanation of
what the test does and how to decode the errors.
4-20. DATA TEST.
4-21. Purpose. This test (figure 4-4) checks all data paths for signals LDO
through LD15 by writing data to the memory RAMs and then reading it back. When
a bit cannot be written and read back in both its high and low level, an error
is flagged.
During the test, data is written to only one address in each of
the 16 RAMs, therefore, a successful test indicates that the data paths are
functioning correctly, but it does not imply that all cells in all RAMs are
operating properly.
See Pattern Test for RAM cell check.
Note that address
bus failures generally do not affect the reliability of this test.
4-22. Decoding Data Test Errors.
All errors found are formatted as a four
character hexidecimal word. Each character represents four binary digits, each
digit corresponding to a single data line.
To decode an error word, convert
each character to its binary equivalent and compare it with the chart shown
below.
If necessary,
refer to Table 4-2.
for hexidecimal-to-binary
conversion.
For example, if the error word is 0005. there are errors on the
LDO and LD2 data paths. The U-number shown in the chart indicates the RAM that
may have a failure.
a. Data Test Errors.
Binary
Hex
xxxx= 0000 0000 0000 0000
---1
--1-1-1-----1
--1-1-1-----1
--1-1-1-----1
--1-1-1--LD = Low Data

DSP 4-10

Signal
None
LDO
LD1
LD2
LD3
LD4
LD5
LD6
LD7
LD8
LD9
LD10
LD11
LD12
LD13
LD14
LD15

in error/RAM
U1
U17
U2
U18
U3
U19
u4
U20
U5
U21
u6
U22
U7
U23
u8
u24

Performance Verification - Model 64100A
4-23. ADDRESS TEST.
4-24. Purpose. Fourteen address lines are checked in this test (figure 4-4) to
make certain they are intact.
Data is written to selected addresses in the
RAMs and read back.
When each bit at the selected addresses cannot be written
and read at its high and low state, an error is noted.
4-25. Decoding Address Test Errors.
Because data errors can cause an address
test to fail, both the address bits and data bits are flagged when a failure
occurs.
After the failure occurs, decode the four character "address error
word" using the chart shown below. To decode the "data error word", use the
chart shown in the Data Test.
Refer to Table 4-2 for hexidecimal-to-binary
conversion, if necessary. Significant error conditions follow.
a. Address Test Errors.
Hex
Binary
xxxx= 0000 0000 0000 0000
00----1
00---100--1-00-1--00----1
00---100--1-00-1--00-- ---1
00-- --100-- -1-00-- 1--00-1
001LA = Low Address

Signal in error
None
LAO
LA1
NOTE
LA2
When ...... LAl5 = False
LA3
LA4
and ... LA14 = True
then the Memory Mapped I/O
LA5
LA6
is addressed. The lower 32K
of RAM is addressed over the
LA7
LA8
Memory Mapped I/O.
LA9
LA10
When ...... LMAP1 = False then
LA11
BANK 2 is addressed
LA12
When ...... LMAP1 = True then
LA13
BANK 1 is addressed

b. Address Error = 3FFF. Indicates all address lines are failing.
This is because there are only 14 address lines and an error of
FFFF cannot be returned from the test.
c. Multiplexed Address Errors. When two address bits are in error,
check to see if they are separated by seven bits. This may
indicate a single line is failing that is carrying both bits in
multiplexed form. Multiplexed address bits are shown below.
Mult iplexed Address Bits
Bits
--------

0
1
2
3

and
and
and
and
4 and
5 and
6 and

7
8
9
10
11

12
13

Node
-------U37 -11
U37 - 13
U37 - 12
U37 - 18
U37 - 17
U37 - 16
U37 - 19

Hex
0081
0101
0204
0408
0810
1020
2040
DSP 4-11

Performance Verification - Model 64100A
4-26. BYTE OPERATION TEST.
4-27. Purpose. This test (figure 4-4) checks the module's ability to perform
byte operations.
When the upper and lower bytes cannot be written and read
back correctly, an error condition is noted.
4-28. Decoding Byte Operation Errors.
The errors found in this test are not
decoded.
When this test fails and all other tests pass, the failure is
probably associated with signals LWRTL and LWRTU in the read/write control
circuit.
4-29. PATTERN TEST.
4-30. Purpose.
All of the cells in each RAM are checked by this test (figure
4-4).
When both the high and low state cannot be written and read back from
each cell, a failure is noted.
4-31. Decoding Pattern Test Errors.
All errors found are formatted as a four
character hexidecimal word. Each character represents four binary digits, each
digit corresponding to a single bit.
To decode an error word, convert each
character to its binary equivalent and compare it with the chart shown below.
If necessary, see Table 4-2 for hexidecimal-to-binary conversion. For example,
if the error word is 0060, there are errors on the LD5 and LD6 data paths. The
U-number shown in the chart indicates the RAM that may have a failure.
a. Pattern Test Errors.
Binary
Hex
xxxx= 0000 0000 0000 0000
---1
--1-1-1-----1
--1-1-1-----1
--1-1-1-----1
--1-1-1--LD = Low Data

Signal
None
LDO
LD1
LD2
LD3
LD4
LD5
LD6
LD7
LD8
LD9
LD10
LD11
LD12
LD13
LD14
LD15

in error/RAM
01
017
U2
018
U3
019
u4
U20
U5
U21
u6
U22
U7
U23
u8
u24

4-32. REFRESH TEST.
4-33. Display.
This display shows the two Refresh test categories available
and their test results. Use the display to review test conditions.
DSP 4-12

Performance Verification - Model 64100A

Host MeMOry PerforMance Verification
Refreshino - No Test

32K MeMory Expander in card slot 110
• Fo..i.l

Bank 1

Opli.!7'at i(ln

I)

Refresh
Sianature Anulvsls

Operation

Bank 2.

Rt\ fresh
Signature Analysis

o

f: Test

o
I)

N/A

o

o

o

o

N/A

o

I)

Internctlon
Re'fresh

Onl

b T AT US:

Awa 1 t 1 n q

N/A

y"

0

P t 1 0 n .... t

Ii!: S t

c: 0 MM Q n d __... _._.... _ ... _.H. __..... __H._._ . _. __..H._ . . _. . ____. ,_"'_.HH.. _ _ _'. _ _ _ _" t () : 12

Figure 4-5. Refresh Test Display
4-34. Running the Refresh Tests. When this screen is displayed, the two tests
are always running. Press the "exit_test" softkey to stop the tests and return
to the Total PV Display. Each iteration takes approximately ten seconds.
4-35. Using the Refresh Results.
The total number of errors detected during
the tests is shown in the # Fail column. Each error code in the Results column
represents a single failure encountered during the last iteration.
Each error
code in the (cumulative) column represents the sum of all errors detected
during the test.
Cumulative error codes that differ from Results error codes
indicate multiple, or intermittent errors. When the error codes are the same,
the errors are systematic. Refer to the appropriate test for an explanation of
what the test does and how to decode the errors.
4-36. DELAY TEST.
4-37. Purpose. This test (figure 4-5) checks for hard failures in the refresh
circuitry (a HARD FAILURE implies· firmware failure).
When data cannot be
written to the RAMs and read back correctly after waiting several refresh
cycles, an error is noted. When this test fails and all other tests pass, the
problem lies in the refresh circuit.
4-38. Decoding Delay Test Errors.
All errors found are formatted as a four
character hexidecimal word. Each character represents four binary digits, each
digit corresponding to a single bit.
To decode an error word, convert each
character to its binary equivalent and compare it with the chart shown below.
See Table 4-2 for hexidecimal-to-binary conversion,if necessary.
For example,
if the error word is OAOO, there are errors on the LD9 and LD11 data paths.
The U-number shown in the chart indicates the RAM that may have a failure.
DSP 4-13

Performance Verification - Model 64100A
a. Delay Test Errors.
Binary
Hex
xxxx= 0000 0000 0000 0000
---1
--1-1-1-----1
--1-1-1-----1
--1-1-1-----1
--1-1-1--LD = Low Data

Signal
None
LDO
LD1
LD2
LD3
LD4
LD5
LD6
LD7
LD8
LD9
LD10
LD11
LD12
LD13
LD14
LD15

in error/RAM
U1
U17
U2
U18
U3
U19
u4
U20
U5
U21
u6
U22
U7
U23
u8
u24

4-39. TIMING TEST.
4-40. Purpose.
Soft failures of the refresh circuit are detected in this test
(figure 4-5).
A SOFT FAILURE implies a software failure.
When the circuit
refreshes memory more frequently than necessary, the power consumption on the
+12 volt supply increases. Also, the mainframe CPU accesses may be delayed by
this condition.
The test detects statistically significant deviations from
normal CPU access rates over a timed interval.
When the access rate is not
within the normal range, a failure is flagged.
4-41. Decoding Timing Errors.
The errors found in this test are not decoded.
When the test fails and all other tests pass, the failure is probably
associated with refresh operation or the multiplexers U49, U50, or U79 - U82.
4-42. SIGNATURE ANALYSIS TEST
4-43. There is no separate display for this test. This test is not used.
4-44. INTERACTION TEST.
4-45. Display.
There is no seperate display for this test.
Display, figure 4-3.

See the total

PV

4-46. Running the Interaction Test. Position the highlight line over the words
"Interaction" on the Total PV display and press the "disp test" softkey. Then
press the "start" softkey which appears on the lower level display.
To exit
the test, press the "exit test" softkey.

DSP 4-14

Performance Verification - Model 64100A
4-47. Purpose.
Tests whether BANK 1 and BANK 2 are operating independently.
It will also test whether or not RAM is always enabled.
The test writes 0000
HEX to BANK 1 and writes FFFF HEX to BANK 2.
It then reads BANK 1 and writes
0000 to BANK 2 and then reads BANK 2. This test is repeated with the same data
but with the BANKs switched.
Any bits which do not have the expected values
are flagged as errors.
4-48. Decoding the Errors.
Any interacion where some or all of the data
written to one BANK is found in the other will probably be associated with the
address bus. If LMAP1 is true during the address cycle, then BANK 1, the lower
16K, is being addressed.
If LMAP1 is false during the address cycle, then
BANK 2, the upper 16K, is being addressed. The enable lines should be checked.
4-49. REFRESH ONLY TEST.
4-50. Display.
is not used.

There is no

separate display for this test because this test

Table 4-2.
Hex
0
1
2
3

= Binary
---1
--1--11

Hex
4
5
6

7

Error Code Conversion

= Binary
-1--1-1
-11-111

Hex

= Binary

8
9
A
B

Hex

1--1--1
1-11-11

C
D
E
F

= Binary
11-11-1
1111111

4-51. TROUBLESHOOTING USING SIGNATURE ANALYSIS.
4-52. Signature Analysis (SA) offers a fast and convenient method of isolating
hardware logic failures down to the component level.
The basic concept is to
utilize a known set of start, stop and clock signals that constantly repeat
(loop) with the same timing relationships. When a suspect logic node is probed
with a Signature Analyzer while using the start, stop, and clock signals as
control inputs, the digital readout (signature) displayed on the analyzer can
be compared with the normal signature of that node to determine if the timing
relationships are proper. With the 64100A Mainframe, looping is provided by
the PV software program and the normal signatures for various nodes are listed
in the tables 4-10 thru 4-28.
4-53. SERVICE TOOLS.
4-54. SUGGESTED SERVICE TOOLS ARE:
1.
2.
3.
4.

HP 5004A or 5005A Signature Analyzer
Digital Voltmeter
Oscilloscope
Standard hand tools for electronic PC board repair.
DSP 4-15

Performance Verification - Model 64100A
4-55.

SA TABLES.

4-56. The basic procedure is to refer to the appropriate table (i.e., the one
that corresponds to the loop that PV was exercising when the failure was noted)
and connect the Signature Analyzer to the Test Points called for in the table.
Next, verify that the Vh signature indicated in the test set-up is proper.
This signature is very important since it verifies that the start, stop and
clock signals are normal.
If this signature is good, proceed with the
signatures listed in the table while referring to the appropriate schematic for
guidance. If an improper signature is noted, check on both sides of the device
to determine if it is causing the problem or if the problem has its origin
further upstream.
4-57. If SA is taken using a 5004A Signature Analyzer, and loop S is good, it
will be necessary to troubleshoot the shift registers U76 and U77 to the video
output signals LIVID and LIVD with an oscilloscope and logic probe.
However,
if a 5005A Signature Analyzer is used, SA can be taken. The reason being, this
circuitry is run by a 25 MHz signal called DOTCLK and the 5004A will not
operate at that speed. If the signatures in loop S are good, and the circuitry
from the shift registers U76 and U77 to the video output check good, then check
the high voltage, the horizontal sync, and the vertical sync on the Display
Driver board.
Waveforms for the sync signals are provided in section VIII.

4-58.

DISPLAY CONTROLLER TROUBLESHOOTING.

4-59.

RAM TROUBLESHOOTING.

4-60. RAM troubleshooting is divided into simple RAM failure and RAM refresh
failure. Different circuitry may be causing the different failure types.
Table 4-3.
REFRESH ERROR ON
shooting table.

DISPLAY .... go

RAM Troubleshooting
to

RAM

SIMPLE RAM ERROR ON DISPLAY .... go to
shooting table.

refresh

simple

RAM

failure

trouble-

failure

trouble-

ILLEGIBLE DISPLAY .... use signature analysis test loop
table to discern failure type.
REFRESH ERROR .... go
table.

to

RAM

refresh

SIMPLE RAM ERROR .... go to simple
table.

DSP 4-16

RAM

determination

failure

troubleshooting

failure

troubleshooting

Performance Verification - Model 64100A

Table 4-4.
STEP 1.

Simple RAM Failure Troubleshooting

LEGIBLE DISPLAY?
YES .... replace RAM(s)
DOESN'T
used to
rupting
failure

FIX PROBLEM .... go to step 2.
Since the RAM is
store display information, the failure may be corthe displayed failure information. The SA RAM
summary table will give you this information.

NO ..•. go to step 2. Since the RAM is used to store display
information, the failure may be corrupting the displayed failure information. The SA RAM failure summary table will give
you this information.
STEP 2.

RAM FAILURE SUMMARY .... use the RAM failure summary SA setup
table to find failing RAM IC(s) and replace.
DOESN'T FIX PROBLEM .... go to step 3. The failure may be due to
a failure in the data path to the RAM, addressing or control.
CPU RAM writes will allow you to check for this type of failure.

STEP 3.

CPU RAM WRlTES .••. use signature analysis setup K table (CPU
RAM writes setup). First, check the ability of the CPU to
write information to the RAM.
GOOD Vh ...• take signatures
BAD SIGS ON RAM TIMING AND CONTROL SIGNALS •..• use signature analysis setup U table (RAM cycle selector/generator
setup) to troubleshoot. If these signals are not correct
information may not be written to or read from RAM correctly. Since these signals are mostly Vh and 0000, an
error in these signals may not be detected.
BAD SIGS ON MEMORY DATA OR ADDRESS BUS.
These bad signatures indicate a failure of the CPU to
write correct data to RAM. This could be due to the CPU,
the connections from the CPU to the RAM, the pullups on
the MB, the address latches on the CPU I/O board, any IC
that connects to the buses, or the address multiplexers.
NO BAD SIGNATURES .... go to step 4. The addresses checked
in CPU RAM writes was only during the CAS strobe portion
of the address. A failure in the row/column multiplexers
might not be detected. CPU RAS address check will let you
find a failure of this type.

DSP 4-17

Performance Verification - Model 64100A

BAD Vh .... troubleshoot the signature analysis latch and the CPU
timing and control circuitry on the CPU,I/O board using a
scope.
STEP 4.

CPU RAS ADDRESS CHECK .... use signature analysis setup L table
(CPU RAS address check setup).
BAD Vh .... go to signature analysis setup U table
selector/generator setup) to troubleshoot.

(RAM

cycle

GOOD Vh.
NO BAD SIGS .... go to step

5.

TIMING AND CONTROL SIGNATURE ERRORS .... use
signature
analysis setup U table (RAM cycle select/generator setup)
to troubleshoot.
STEP

5. ADDRESS SIGNATURE ERRORS .... use signature analysis setup M
table (CPU RAM reads setup). Before signatures on the output
of the RAM can be correct, addressing and data from the CPU
must be correct. You should have already checked these functions using CPU RAM writes and CPU RAS address check.

BADVh.
NO CLOCK SIGNAL .... go to signature analysis setup U table
cycle selector/generator setup) to troubleshoot.

(RAM

NO START/STOP SIGNAL .... go to ROM troubleshooting table.
GOOD Vh.
RAM or RAM ADDRESS TIMING AND CONTROL SIG ERRORS .... go to signature analysis setup U table (RAM cycle selector/generator
setup) to troubleshoot.
DATA CONTROL AND DECODE SIG. ERRORS .... use signature analysis
setup N table (RAM access control and decode setup) to troubleshoot.
DATA OR ADDRESS SIGNATURE ERRORS .... troubleshoot.

DSP 4-18

Performance Verification - Model 64100A

4-61.

RAM REFRESH FAILURE TROUBLESHOOTING.

4-62. RAM refresh is accomplished by the display accesses to RAM.
Circuitry
in the display counters causes a RAS address for each of the 128 row addresses
of both banks of RAM to be generated as the display accesses the RAM for
display information. Troubleshooting in this section will allow you to isolate
problems with individual RAM ICs or with the display address counters, CRT
controller, and control circuitry.
4-63. Retention of the RAM ICs may be greater than 1 sec.
Even with refresh
not operating, only a few RAM ICs may fail the RAM refresh test.
Taking the
key signatures in display RAS Address check will verify that the refresh
circuitry is working.
Table 4-5.
STEP 1.

RAM Refresh Failure Troubleshooting

LEGIBLE DISPLAY?

YES .... replace failing RAM IC(s)
DOESN'T
used to
rupting
summary

FIX PROBLEM .... go to step 2.
Since the RAM is
store display information, the failure may be corthe displayed failure information. The RAM failure
SA setup table will give you this information.

NO .... go to step 2. Since the RAM is used to store display information, the failure may be corrupting the displayed failure
information. The signature analysis RAM failure summary table
will give you this information.
STEP 2.

RAM FAILURE SUMMARY .... use the RAM failure summary SA setup
table to find the failing RAM IC(s) and replace.
DOESN'T FIX PROBLEM .... go to step 3. Refresh is accomplished
by the display accesses to RAM, CRT controller outputs-hardware
setup will check to see that the CRT controller is operating
correctly.

STEP 3.

CRT CONTROLLER OUTPUTS-HARDWARE .... use Signature analysis
setup 0 table (CRT controller outputs-hardware loop setup).
BADVh.
NO CLOCK •..• troubleshoot.
NO START/STOP .... go to step 5.
VALID Vh.

DSP 4-19

Performance Verification - Model 64100A

CRT CONTROLLER IC PINS 1-5, 7-8 SIGNATURE ERRORS .... go to
step 5.
The CRT controller is not operating correctly,
CPU program of the CRT controller will allow you to verify
that the CRT controller is being programmed correctly by
the CPU.
OTHER SIGNATURE ERRORS .... troubleshoot
NO BAD SIGNATURES .... go to step 4. If the display address
counters are not working correctly, refresh may not be
done.
Addresses are checked only during the RAS portion
of the address since the RAS addressing is what does the
refresh for the RAM.
STEP 4.

DISPLAY RAS ADDRESS CHECK •... use signature analysis
table (display RAS address check setup).

setup

R

BADVh.
NO CLOCK .... use signature analysis setup U table
cycle selector/generator setup) to troubleshoot.

(RAM

NO START/STOP ••.. go to step 5.
VALID Vh.
ADDRESS TIMING AND CONTROL SIG ERRORS •... use signature
analysis setup U table (RAM cycle selector/generator
setup) to troubleshoot.
OTHER SIG ERRORS ..•• troubleshoot.
STEP

5.

CPU PROGRAM OF CRT CONTROLLER .... use signature analysis setup
P table (CPU program of CRT controller setup).
BADVh.
NO CLOCK .•.. use signature analysis setup N table
access control and decode setup) to troubleshoot.

(RAM

NO START/STOP •... go to ROM troubleshooting table, step 4.
VALID Vh.
BUFFER TIMING AND CONTROL srG ERRORS ••.. use signature
analysis setup N table (RAM access control and decode
setup) to troubleshoot.
NO BAD SIGNATURES ...• check power supplies and clock to CRT
controller. If outputs are bad and all inputs are good,
replace the CRT controller.
DSP 4-20

Performance Verification - Model 64100A

Table 4-6.

Display Troubleshooting

ARE THE DISPLAY AND CHARACTERS THE CORRECT SIZE AND INTENSITY? ...
First, isolate the problem to the Display Controller or driver
boards.
YES .... go to Display Controller troubleshooting table. The correct size indicates that the driver boards are operating correctly. If the display is wrong, it is because the display controller is sending the wrong video information.
NO .... are HSYN, VSYN, and VIDEO signals correct coming from the
Display Controller board?
YES .... troubleshoot Display Driver
NO .... go to Display Controller troubleshooting table.

Table 4-7.
STEP 1.

Display Controller Troubleshooting

CRT CONTROLLER OUTPUTS-DISPLAY TEST .... use signature analysis
setup S table (CRT controller outputs-display test setup).

BADVh.
NO CLOCK .... troubleshoot with scope
NO START/STOP .... go to step 3.
VALID Vh.
CRT CONTROLLER IC PINS 1-5, 7-8 SIGNATURE ERRORS .... go to
step 3.
The CRT controller is not operating correctly,
CPU program of the CRT controller will allow you to verify
that the CRT controller is being programmed correctly by
the CPU.
CRT CONTROLLER IC Hcco-6 OUTPUT SIGNATURE ERRORS .... go to
step 2. If the character code outputs are wrong, it may be
because the CRT controller is getting wrong information
from RAM
OTHER SIGNATURE ERRORS .... troubleshoot.
NO BAD SIGNATURES .... use scope to troubleshoot video circui try. The video circuitry runs at 25 MHz; this is too
fast for signature analysis so a scope is required to
troubleshoot.
DSP 4-21

Performance Verification - Model 64100A

STEP 2.

CRT CONTROLLER READ FROM RAM .... use signature analysis
T table (CRT controller read from RAM setup).

setup

BADVh.
NO CLOCK .... use signature analysis setup U table
cycle selector/generator setup) to troubleshoot.

(RAM

NO START/STOP .... use signature analysis setup 0 table (CRT
controller outputs-hardware loop setup) to troubleshoot.
VALID Vh.
RAM TIMING AND CONTROL OR ADDRESS MUX CONTROL SIG ERRORS ..
use signature analysis setup U table ( RAM cycle selectorgenerator setup) to troubleshoot.
RAM DATA OUTPUT SIGNATURE ERRORS ONLY .... use signature
analysis setup R table (display RAS address check setup)
to check RAS address to RAM. If no errors are found, suspect the RAM or any IC connected to the RAM memory data
bus.
OTHER BAD SIGNATURES .... troubleshoot.
NO BAD SIGNATURES .... check power supplies and clock to CRT
controller. If outputs are bad and all inputs are good,
replace the CRT controller.
STEP 3.

CPU PROGRAM OF CRT CONTROLLER .... use signature analysis setup
P table (CPU program of CRT controller).

BADVh.
NO CLOCK .... signature analysis setup N table
control and decode setup) to troubleshoot.

(RAM

access

NO START/STOP .... go to ROM troubleshooting table, step 4.
BUFFER TIMING AND CONTROL SIG ERRORS .... use signature
analysis setup N table (RAM access control and decode
setup) and signature analysis setup U table (RAM cycle
selector/generator setup) to troubleshoot.
OTHER SIGNATURE ERRORS .... troubleshoot.
NO BAD SIGNATURES .... check power supplies and clock to CRT
controller. If outputs are bad and all inputs are good,
replace the CRT controller.

DSP 4-22

Performance Verification - Model 64100A

Table 4-8. SA Loop Determination
LOOPNAME and SETUP NAME: TEST LOOP DETERMINATION
The memory signature analysis latch is set and reset during the execution of
the software tests. The interval is unique to the test being performed.
In the event that the display is not functioning correctly, this test
used to determine which of the tests the mainframe is executing.

can be

All option boards removed
All jumpers in the NORMAL position
ST/SP/START = pos. edge
CPU Bd. TP10 (MEM SA LATCH)
QUAL/STOP = neg. edge : CPU Bd. TP10 (MEM SA LATCH)
CLOCK = pos. edge: CPU Bd. TPl (LSTB)
Signatures
Vh = CA27

POWER-ON RAM TEST LOOP - SIMPLE RAM FAILURE
Go to simple RAM failure troubleshooting.

Vh

= AH68

POWER-ON RAM TEST LOOP - REFRESH FAILURE
Go to RAM refresh failure troubleshooting.

Vh

= AU94

DISPLAY TEST
If wrong or no display, go to display troubleshooting.

Vh = XXXX

NO RECOGNIZABLE Vh
Go to ROM troubleshooting

DSP 4-23

Performance Verification - Model 64100A

Table 4-9. RAM Failure Sumary
LOOPNAME: POWER-ON RAM TEST FAILURE OR REFRESH FAILURE
If a failure is detected during the power-on RAM self-test, the test enters a
signature analysis loop that writes and reads RAM and stimulates the CRT
controller.
The loop also outputs the error mask onto the memory data bus and
the CPU attempts to display the failing IC numbers.
Since the display information is stored in RAM, the output to the display of
the failing RAM IC numbers may be illegible.
This setup allows the taking of
signatures on the memory data hus during the time that the error mask are
present. The value of the signatures and data bit may be decoded to isolate the
failing RAM IC numbers.
Executing power-on RAM test or refresh failure loop:
ST/SP/START = pos. edge: CPU Bd. TP10 (MEM SA LATCH)
QUAL/STOP = pos. edge: CPU Bd. TP10 (MEM SA LATCH)
CLOCK = pos. edge: CPU Bd. TP9
Vh

= 0007
Signature
0000
Bit
LDO
LD1
LD2
LD3
LD4
LD5
LD6
LD7
LD8
LD9
LD10
LD11
LD12
LD13
LD14
LD15

DSP 4-24

0002
Failing RAM

no
no
no
no
no
no
no
no
no
no
no
no
no
no
no
no

failure
failure
failure
failure
failure
failure
failure
failure
failure
failure
failure
failure
failure
failure
failure
failure

U23
u24
U25
u26
U27
u28
U29
U30
U38
U39
u40
U41
U42
u43
u44
u45

0004

0006

on Display Controller Bd.
U51
U52
U53
U54
U55
U56
U57
U58
u65
u66
u67
u68
u69
U70
U71
U72

U23,
u24,
U25.
u26,
U27.
U28,
U29,
U30.
U38,
U39,
u40,
U41,
U42,
u43,
u44,
u45,

U51
U52
U53
U54
U55
U56
U57
U58
u65
u66
u67
u68
u69
U70
U71
U72

Performance Verification - Model 64100A

Table 4-10. Signature Analysis Loop A
PC Board: Display Controller Board
Test failure or circuit: Power-up RAM Test failure
Procedure:
S/A hookup:
Start = Pos edge CPU Bd. TP10 (S.A. Interval)
Stop = Neg edge CPU Bd. TP10 (S.A. Interval)
Clock = Pos edge CPU Bd. TP1 (LSTB)
\/ l··i :::; C"=', ;.:~ ?

Sig

Node

U C) '::; .... ::,1
l .'i 6 '::) .... S
..:. 1"":::. .. ,. :l. 1
U 1".,'

e~.::~ ?H
')c:'e U

":',
U i:) i;) ... i_.
U .:':) 6 -.,- I;':')
U 1'. b '''' 1 1
U <:) 'l:.•1. .... :l. it

':;~~ GC C'.'
U?4H
tiP H'::';

I·•••

b··:'{- 4 r.~'
...'

4S~:)·4

U \;.i .' .... ;~
t.J 6 '/".. 1:':)
:i. ~.
U ~;j "','.",
/
r'~f

U {,[$ ..

,'

/::\9 j. (i
jj 6 (:) .~'{.

F:3F'F'
~:)F 1;:'1 C
;~:~ ~:j ::?) [:

;:.:~

U ~:i ~~ ... S
U t) ~:s l. :1.
U '.J:. i:~ .... j. 4

. ..

;.':}p ~:~ ~':)

0 .\.1.

·':)(:"1
f ••• \.,1

Sig

Node
"x
U .f 0 ... ,.J
';7;
U '? 0
U / () .. /'
U )' 0 .. q,
U "'J/ () ...... .i. ;:::.
U i 0 .. :1. -4
U ? 0 :t f,
U )1 0 :l. B
1",1

\"1

l".1

!",'

1"":.'.. bUF
\:}

0 ...,',.J

.'

,.;

~ ••I

P i~:'1 j,I",'!""
4
U :i. .- ;.)
0 UU '/
H~:;H?

C6F 1::\
F4 ?H

F' ~:J \;:' .-t:!,
:t tf / :i.
C~':'; (;) "4
'::iCi'j :I.
H4i':) Ii
~i. ;;:, ':~;: ;. . ~

U ....)' :i. ... :L :~:"
U ,/ l ... :t i.:':
,- i ... .1.i ~::~
U "'.I
.,
U '.?T"} I;•1. ... :i. .';
(I 1'"
".
,U
i ... ::J
U ;;? :i. ... :1. ',:..1
U '"'JI,? :l. " :t ./
(;,
U i :1. .. :i. '-'

t· ...'

3GHF

," LJUr
!'"

Table 4-11. Signature Analysis Loop B
PC Board: Display Controller Board
Test failure or circuit: Power-up RAM failure - Data writes to RAM
Procedure:
S/A hookup:
Start = Pos edge CPU Bd. TP10 (S.A. Interval)
Stop = Neg edge CPU Bd. TP10 (S.A. Interval)
Clock = Neg edge Disp Controller U21-10 (HWRT)

*=

Pro be Blinking

Sig

Node

u '/0· ..·

U '/()"·:i.6
1...1

0000

:1.

lj ? 0· .. · .,:',1
U :? 0 ..·· I:':)
tJ :/0"" ?
U '/0", 7
1...1 '/O·,,:t;2
U ::.:' 0···· 1. 4
)'(}":i.D

Sig

Node

H'?H9

:'L '/'j"

2.~

{:i i:} ~'::)

t':"

PCdO

O/H;.::'

(It,6('1

:tH3P

PC~':'::C

iC {} C;
UCC:i.

:5 t.? ~:; i;':i

fJ {I ~;';f;
i~i,?3 (I
6U:'i.tl
40P?

DSP 4-25

Performance Verification - Model 64100A

Table 4-12. Signature Analysis Loop C
PC Board: Display Controller Board
Test failure or circuit: Power-up Ram failure
Procedure:
S/A hookup:
Start = Pos edge CPU Bd. TPIO (S.A. Interval)
Stop = Neg edge CPU Bd. TPIO (S.A. Interval)
Clock =" Pos edge Disp Controller TPll (HPRAS)

*=

Pro be Blinking
Node

;...1

...i,
i•

Sig

:1.

r'j

D

"."

\'l

" \:.) ...

r

o

::)

.h-(

'

Li ...,.:!, \) ... ,-j
U 41)
/
U . ;~ () .... (?
U 1"r:, i'.! ,,, . 4
..
! I
;;i I) ....
\.!
I
U f'"......' () .. .)~
i..I ::) II .... j, ;~:::
"of

1"j

'"

•• ,1

~

.'

""

"

~

f'
,)

D0 0

I)" },.) ~'::;~ I".'
.'

U
tJ
U
I!

L.t

;~:~HP :,';:)

6H
;1. I'.':.! 0 p
~:;! ,'.-::

i)LiC:FI
HI~iCPI
F-H;.:.~

()

463H

U
U

::-, ....

...

.':)

I'·

,

(":i 1;';') ".,
.," 1."::
\::' ' ".,

·4I'"

~':) J;';:; ... ,

'/

L

r•• }

..

(:) ::') ....

;:;

t?
6 r";:J"" J. 1

U {;;.B ..., ;.~
U ~':)i}'" ·AL t:· ....
';;)
'1..1
U 1..1
' I
6H..·:I- i
1..)
.':)
U {::rB ..· :i. I".
t)

DSP 4-26

Sig

Node

'!;i ~J"" :t

"+

;:2HP ~~S
:":i, ()..... j•. j •.;~}
1..,1,.... 6H
:i. U '::iPI
1• • • f

~:.' i:~1 ~~;) ')
~

....

.i. .' 0 P
'·)L.eF'

F' C~;~'::)
HI;;lCtl

FH;:.:: 0
3[0 ,.:.)
46JH

Performance Verification - Model 64100A

Table 4-13. Signature Analysis Loop D
PC Board: Display Controller
Test failure or circuit: Power-up RAM failure - Data write to RAM and column address
Procedure:
S/A hookup:
Start = Pos edge CPU Bd. TPIO (S.A. Interval)
Stop = Neg edge CPU Bd. TPIO (S.A. Interval)
Clock = Neg edge Disp Controller TP6 (LPCAS)
VH ::: '7H~5?
* = Probe Blinking
Node

Sig

U :1.8····
U

4~:$""

U 49 . ··

?

0000

nooo
-4.-, scoc
:3aHU
i'"

;:J

U ..:+-=;' .... /
U ·4 (/ .... ?

40P ()

u

';;) 0 ..· 4..,

DUH'?

0 ..·, 9

7 j.4~5

U
U

~':;
~)

() ....

~

/

03~3/'

~:;O""i;:~

OU';;d.

U 66··.. 2
66 ..- 4,_.

?2PP

U

u

u

66 ..-

J

OUH9

o3~:;'7

U 66 ..- .'
U \J {::. · .. l. i
U 66····1.~~

,?p 0 0

66 .... j.4

7;266
() U'::; l.

,.,
U 67 .... ,:
U 6'7···· 4

8coe

U ~:) ~;1 .••. 7
U {;)/ .... <;I
U 6 T···· i i

3HH'l

u

,.~

u 67 . .

~':)

Node

Sig
"or

U 70 ..·· ,.J
LJ '? 0···, S
u ·70·..· '7
U 70 .... 9
u ,/0"':\.;2

H49f':i

~?9S~~'

38:1.P

PFPD

A004

u '?O·"'i4
LJ '/0'-16
U 7 () .., j. t:I

UF':l'B

LJ '71 "·l.i

(!S4F

LJ

7:l.·-'i~~

U '? :I. ·.. i3
U '7:1...·,:1.4

LJ 71 ,.. 1 '::)
U ~"}~L···j.6
u ~:'l1 .. 1. '7

1'9;~~9

;'~Ui:~U

;~~ 9~; f'
U'??B
CF9(;'"

OHU4

U ~;i 0 (;J
C763

'7i43

U63r"
38HU
4 I::) P ~]

40PO

DSP 4-21

Performance Verification - Model 64100A

Table 4-14. Signature Analysis Loop E
PC Board: Display Controller
Test failure or circuit: Power-up RAM failure, RAM outputs
Procedure:
SfA hookup:
Start = Pos edge CPU Bd. TPIO (S.A. Interval)
Stop = Neg edge CPU Bd. TPIO (S.A. Interval)
Clock = Pos edge Disp Controller TP15
Vh= POOO
Node

l.J :3D····:1.4

f~~' i..l ~~ [:

U :? O····~:)

1''''H;:.~8

LJ ?:i. .... :l.:i.

of''t (..'iPI
OAr.:)A
BPI';;ll=-!

U ;.;~4 ,···:l4
U :·~):t ····S
U 1?j.··.. t2

P444
P444
P444

t.J 39····:i.4
U '?O····S

C;:.~:l

4

9B~5B

t.J 40 .... 14
U 70 ..··:)'

I;PH6
,;PHil

U 41····14
U ?O""9

6;:.~~:;

U 42 ..··j.4
U ? () ". 1. ~~:

CF46
CF4(::,

l.J 43 .. ··:1.4
U '7 () .... :1 4

FF'?H
FF7H

U 44 ..·:1.4
U '? ()"":1. (;,

Fn{~A

U 45····:1.4
U 70····18

CUUlJ

U ;.~3····:i.4
U ~:S i .... :o;}

LJ

~?::).",:I.

U :':) ~j. ··.. 7

'l83B

U 1'1.'''';1. 3

9B~58

U ;:~6"" :1.4
U ::; t .... c1
U '/':1.-14

4Aa'l
4A;;~H

4(.i;;?H

... :1.4

PU:~3

U :5i····j.;:2
U '7:1.··.. 15

PUS3
PU~:)3

U ;:.~i:)····:i. 4
U 3:1.····14
U ?1.''',j.6

401.3
Jl () :1.:3
40 :1.:3

U 29",,:1.4

t ... J.t>

'3AH:;}
'3 PI 1--1:5

U 1'1.-,3.7

Si~lH3

U 30 . ··:1.4
U :3i····:i.B

f"';.:~4 '7

l.J ?:l."··j.D

f.~;.:~ 4 '?

LJ

I.J

DSP 4-28

Sig

Sig

Node

;~~'?'

~!;

A;':~4'/

i

C;~:l.i

~:j ;.:.~ J;:)

i
:i '

FB(.~{:,

CUUU

Performance Verification - Model 64100A

Table

4-15. Signature Analysis Loop G

PC Board: Display Controller
Test failure or circuit: Power-up RAM failure
Procedure:
S/A hookup:
Start = Pos edge Disp Controller TP3 (Vert Sync)
Stop = Neg edge Disp Controller TP3 (Vert Sync)
Clock = Pos edge Disp Controller TP7 (HDRAS)
Vh= P5H2
* = Probe Blinking
Sig

Node

U

:1. 7 ..··3

u :1.8····?
····2

U

;.~j.

l.J

4a ..-~:>

U 49···-4
U 49-'7
U 49····(1
U ';;;0 ..·-4
U '::'; 0-·;'
U '::)0 .... 'i'
U ~:;O-'ii

CP

j.

:1

P';;iH;.~*

SFCi

Node

U S8··-j. i
U ~:; D·..· :1. 2.
U S8····:1.~)
U ~:)8····j.4
U ';;;B··· j. ';;";

Sig

I{~ '7 '7 ~:>

BH () ;.:~
~.::P 4(.~

C96;5
S~~1:1

U 6~;""4
U 6~;;""?
U 65··.. 9

~:;CF3

B8UH

6H:2U

U 68····4
U 6fj····?
U 68····9

A7'7S

U 68····:1.::?

PSH2*

CPij.

4U;;!.(.1

ACDF

(.~I~U8

4P~:iP

DHOi

4JO)

1.'''.1

.:.f·ll

6DHO
FC9()

i7~54

U S6··.. j. l.

P ~?(.:'IO

U ::;(;;.- :i.~?
U ';;i6···-:i.3
U ':':~ (:) -- 1. 4
U S'J .... :t ':)

f~II~l.J8

4PSP

6H;::?'U
SU8F

NOTE:

If the signatures of U6S and
U68 are unstable~ use NEG clock edgE
for these two cOMponents.

DSP 4-29

Performance Verification - Model 64100A

Taba.. 4;"'16'. Signature Analysis Loop H
PC Board: Display Controller
Test failure or circuit: Power-up RAM failure
Procedure:
S/A hookup:
Start = Pos edge Disp Controller TP3 (Vert Sync)
Stop = Neg edge Disp Controller TP3 (Vert Sync)
Clock = Neg edge Disp Controller TP13
Vh= P5H2
* = Probe Blinking
Node

Sig

U :i. .... :l. :t

U
U

Sig

~;;

/' .... j.

~~

/' .... j, ;.:~

:1.

U :t ? .... ~;)
U 1 ? ...,IS

P:;;H;'::*

l.J S'7····:i.:·:>

OOO(Pl<

U '::';'7 .... j. 4

U j. 8···· ?

P :;-;H;2*

U 66···-4

U 4'7····6

e~~H;.~*

l.J 66····'/
U 6(;)····~:?
U 66····;1.;.::

U 4B"'S

0000;:<

tt

U 4'?·..·/
U -4 \>J .... fi'

000 0*
00 () 0
O()OO*

U ':·;;0····4
,',,1
U ::;0··· /

6CD6
DP'::>4

U ';:·)0··.. 9
U SO .... :i. 2

U;.:::P6

U

DSP 4-30

PSH;:!.*

Node

4!:~i .....

*

'73P j'

U 6'7····4
U 6'?"":?
U (;)-7 .... (?

6CB6
Dpi;:"ilf
LJ~:::p b
'73P?

BPS4
6CBb
j. '73·4

r; (:) ~) ~':')
P~:;H;:?*

PSH;'?*

PSH;::'*

Performance Verification - Model 64100A

Table 4-17. Signature Analysis Loop I
PC Board: Display Controller
Test failure or circuit: Any test - Arbitrator circuit - No clocks on TP6, TP7, or TPll.
Procedure:
Remove CPU Bd., I/O Bd., and Disp Driver Bd. Move TEST jumper to TEST position.
S/A hookup:
Start == Pos edge TP14
Stop == Pos edge TP14
Clock == Pos edge TP2
Vh== UP73
* == Probe Blinking
Node

Sig

Node

Sig

Ul-3
Ul-8

55H1
UP51

U20-6
U20-8

UP73
H4C1

U2-11
U2-12
U2-14

8135
86F1
ACA2

U22-1
U22-4
U22-13

0000
0000
669P

U5-11

8117

U35-1
U35-4

0022
2275

U9-13

ACA2

U10-6
UlO-7

UP73*
55H1

U36-8
U36-11

UP73
HF06

U15-3
U15-6
U15-8

7U24
UP73
UP73

U37-3
U37-6
U37-8
U37-11

7U46
UP51
7U46
7U24

U16-6
U16-8

UF74
UF74

U18-7
U18-9

HF06
2275

U48-5
U48-9
U48-11

7U46
7U06
0022

DSP 4-31

Performance Verification - Model 64100A

Table 4-18. Signature Analysis Loop K
LOOPNAME:

POWER ON RAM TEST

-

SETUP NAME:

CPU RAM WRITES

If a failure is detected during the power-on RAM self test, the test enters a
signature analysis loop that writes and reads RAM and stimulates the CRT
controller.
The loop outputs the error mask onto the memory data bus and the
CPU attempts to display the failing IC number(s).
This setup allows the checking of the CPU data path to the RAM during the write
to RAM by the CPU.
The CPU address path from the CPU to the multiplexers is
also checked.
The mainframe may be forced to execute the power-on RAM failure
test by removing RAM IC A5U23.
ST/SP/START = pos. edge: CPU TP10 (SA LATCH)
QUAL/STOP = neg. edge : CPU TP10 (SA LATCH)
CLOCK = pos. edge: CPU TP13 (LMWRT)
VH = H37A
U 16- 6
U 16- 8

0001
0001

U 23- 3
U 23- 4

0001
0001

U 37- 8

0001

U 38- 3

0001

U
U
U
U

65- 2
65- 5
65-11
65-14

63F3
P8FC
61C1
1P3O

U
U
U
U

66- 2
66- 5
66-11
66-14

U7H3
HA56
44p6
8A4p

U
U
U
U

67- 2
67- 5
67-11
67-14

0001
1A8F
F7PA
683U

U
U
U
U

68- 2
68- 5
68-11
68-14

6U3A
87F2
6019
u08c

DSP 4-32

U
U
U
U
U
U
U
U

70- 3 728H
70- 5 UH82
70- 7 UF05
70- 9 lUPA
70-12 9093
70-14 P58U
70-16 84H6
70-18 F35F

U
U
U
U
U
U
U
U

71-11
71-12
71-13
71-14
71-15
71-16
71-17
71-18

7045
P6FF
C9HH
3H08
P1H6
4F3A
2AU8
3121

[NORMAL MODE]

Performance Verification - Model 64100A

Table 4-19. Signature Analysis Loop L
LOOPNAME:

POWER-ON RAM TEST

-

SETUP NAME:

CPU RAS ADDRESS CHECK

This setup checks CPU addressing during the RAS address to RAM.
The mainframe
may be forced to execute the RAM failure by removing RAM IC A5U23.
ST/SP/START = pos. edge: CPU TP10 (SA LATCH)
QUAL/STOP = neg. edge : CPU TP10 (SA LATCH)
CLOCK = pos edge : DSP TP11 (HPRAS)

VH

= 1H31

U 16- 6 1H31
U 16- 8 1H31
U 18- 1 0000
U 18-11 0000
U 18-12 0000
U 23- 3
U 23- 5
U 23- 6
U 23- 1
U 23- 9
U 23-10
U 23-11
U 23-12
U 23-13
U 23-15

1H31

463H
HACA
FH20
OU51
626H
110P
96cp
2HP3
7H31

U 38- 3 1H31
U 48- 4 7H31
U 48- 5 7H31
U
U
U
U

[NORMAL MODE]

49- 4
49- 1
49- 9
49-12

2HP3
626H
110P
OU51

U 50- 4
U 50- 1
U 50- 9
U 50-12

96cp
HACA
FH20
463H

U 65- 2
U 65- 4
U 65- 5
u 65- 1
U 65- 9
U 65-11
U 65-12
U 65-14

2HP3
50H4
626H
1U5A
6A39
110P
1266
OU51

U 66- 2
U 66- 4
U 66- 5
U 66- 1
U 66- 9
U 66-11
U 66-12
U 66-14

40po
3HH1
OUH9
12PP
1POO
0331
OF14
1143

U 61- 2
U 61- 4
U 61- 5
U 61- 1
U 61- 9
U 61-11
U 61-12
U 61-14

0000
7H31
8694
UCA3
u63F
8coc
45P8
38HU

U 68U 68U 68U 68U 68-

96cp
PC89
HACA
A18H
C011

2
4
5
1
9

u68-11 FH20
u68-12 3COA
u68-14 463H

DSP 4-33

Performance Verification - Model 64100A
Table 4-20. Signature Analysis Loop M
LOOPNAME: POWER-ON RAM TEST

-

SETUP NAME: CPU READS RAM

This setup checks the data as it is being read from RAM by the CPU, addressing
by the CPU, and CAS addressing to RAM. The mainframe may be forced to execute
the RAM failure loop by removing RAM IC A5U23.
ST/SP/START = pos. edge : CPU TP10 (SA LATCH)
QUAL/STOP = neg. edge : CPU TP10 (SA LATCH)
CLOCK = pos. edge: DSP TP15 (U31 ENABLE)
VH = POOO
U 1- 8

POOO

U 7- 3

POOO

U 15- 4
U 15- 5
U 15- 6
U 15- 8
U 15-10

H555
high
high
high
3555

U 16U 16U 16U 16U 16U 16-

1
2
4
5
6
8

high
0000
POOO
0000
POOO
POOO

U 18- 7
U 18- 9

31- 3
31- 4
31- 5
31- 6
31- 7
31- 8
31- 9
31-11
31-12
31-13
31-14
31-15
31-16
31-17
31-18
31-19

8AAA
5AH3
p444
4013
9838
PU53
4A2H
4A2H
PU53
9838
4013
p444
5AH3
8AAA
A247
0000

0000
POOO

U 35-10

0000

U 21- 8
U 21-10

3555
0000

U
U
U
U

37- 8
37-10
37-11
37-12

POOO
0000
POOO
0000

U
U
U
U
U
U
U
U
U
U
U

POOO
POOO
H555
9F7F
5CCC
3C89
1PFH
PAFA
CH21
C2F8
POOO

U 46- 1
U 46-11

POOO
POOO

23- 3
23- 4
23- 5
23- 6
23- 7
23- 9
23-10
23-11
23-12
23-13
23-15

U 31- 1 0000
U 31- 2 A247
DSP 4-34

U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U

U 48- 2 POOO
U 48- 4 0000
U 48- 5 pooo
U
U
U
U

49- 4 C2F8
49- 7 1PFH
49- 9 PAFA
49-12 3C89

[NORMAL MODE]

Performance Verification - Model 64100A

Table 4-20. Signature Analysis Loop M {Cont'd}

U 50- 4
U 50- 7
U 50- 9
U 50-12

CH21
9F7F
5CCC
H555

U 51- 6 0000
U 51- 8 955U
U 65- 2
U 65- 4
U 65- 5
U 65- 7
U 65- 9
U 65-11
U 65-12
U 65-14

C2F8
52F8
1PFH
UPFH
OAFA
PAFA
HC89
3C89

U 66- 2
U 66- 4
U 66- 5
U 66- 7
U 66- 9
U 66-11
U 66-12
U 66-14

3AP7
HAP 7
U293
1293
HPPO
3PPO
2H70
FH70

U 67- 2
U 67- 4
U 67- 5
U 67- 7
U 67- 9
U 67-11
U 67-12
U 67-14

0000
POOO
955U
755U
3827
H827
3C96
HC96

U 69- 8 POOO
POOO

U 70- 1
U 70- 2
U 70- 3
U 70- 4
U 70- 5
U 70- 6
U 70- 7
U 70- 8
U 70- 9
U 70-11
U 70-12
U 70-13
U 70-14
U 70-15
U 70-16
U 70-17
U 70-18

AH28
F8AA
C211
FF7H
APH6
CF46
6251
6251
CF46
APH6
FF7H
C211
F8AA
AH28

U 71- 1
U 71-11
U 71-12
U 71-13
U 71-14
U 71-15
U 71-16
U 71-17
U 71-18
U 71-19

POOO
8AAA
p444
9838
4A2H
PU53
4013
5AH3
A247
POOO

cmm

cmm

u 68- 2 CH21
U 68- 4
U 68- 5
U 68- 7
U 68- 9
U 68-11

5H21
9F7F
7F7F

cccc

5CCC

DSP 4-35

Performance Verification - Model 64100A

Table 4-21. Signature Analysis Loop N
LOOPNAME: POWER-ON RAM TEST

-

SETUP NAME: RAM ACCESS CONTROL AND DECODE

This setup is used to troubleshoot the control circuitry used to enable the RAM
data buffers during CPU accesses to RAM and to the CRT controller.
The
mainframe may be forced to execute the power-on RAM test failure loop by
removing RAM ICA5U23.
ST/SP/START = pos. edge: CPU TP10 (SA LATCH)
QUAL/STOP = neg. edge : CPU TP10 (SA LATCH)
CLOCK pos. edge: CPU TP1 (LSTB)
VH = CA27
U 1- 8

HC2U

U 5- 3

75FC

U 7- 3

3785

U 15-11

2347

U
U
U
U

21- 3 6645
21- 4 HF62
21-10 U869
21-11 424p

U 35-10

8HA2

U 47- 3

2347

U 64- 1
U 64- 2
U 64- 3
U 64- 4
U 64- 5
U 64- 6
U 64- 7
U 64- 9
U 64-10
U 64-11
U 64-12
U 64-13
U 64-14
U 64-15

u664
F8FF
5FAC
APH5
A91A
2838
4P85
5HCA
U94H
6445
9CPU
50CO
4534
P29H

DSP 4-36

U
U
U
U
U
U
U
U

69- 1
69- 2
69- 3
69- 5
69- 6
69- 8
69-10
69-11

HC2U
HF62
074H
HC2U
APP5
U869
0000
3785

[NORMAL MODE]

Performance Verification - Model 64100A

Table 4-22. Signature Analysis Loop 0
LOOPNAME and SETUP NAME:

CRT CONTROLLER OUTPUTS - HARDWARE LOOP

By moving jumpers A5J2 and A5J3 to the test position, the CRT accesses to RAM
are disabled.
The CRT controller still is still accessed by the CPU and
configured.
The CRT controller provides horizontal and vertical retrace
signals to horizontal and vertical sync circuitry.
This setup allows checking the horizontal and
proper configuration of the CRT controller IC.
ST/SP/START pos. edge: DSP TP16 (HVRTC)
QUAL/STOP pos. edge: DSP TP16 (HVRTC)
CLOCK pos. edge: DSP TP4 (HCHAR)
VH

vertical sync circuitry for

[NORMAL MODE]

= HU61

U 3- 3
U 3- 7
U 3- 9

745H

BC75
212H

U 11- 6 5B9H
U 11- B 4179
U 11- 9 AC3F

U 12- 9 9AOO
U 12-11

u 53- 6 Fu65
u 53- 9 34A6
U 61-11

P54H

U 62-15

26BH

u 63- 5 oBpu
u 63- 9 2AB2

Fu65
U 72- B

P54H

U 74-11

3A2F

U 7B- 5
U 7B- 9

2HCC
P54H

u 33- 1 AC3F
U 33- 2

5414

u 33- 3 63UP
u 33- 4 UP4F
U 33- 5

3763

U 33-30

HU61

u 33- 7 HAlH
U 33- B 2008

DSP 4-37

Performance Verification - Model 64100A

Table 4-23. Signature Analysis Loop P
LOOPNAME: POWER ON RAM TEST

-

SETUP NAME: CPU PROGRAM OF CRT CONTROLLER

This setup allows the checking of the data path from the CPU to the CRT
controller IC, addressing, and control. The mainframe may be forced to execute
the RAM failure loop by removing RAM IC A5U23.
ST/SP/START = pos. edge: CPU TP10 (SA LATCH)
QUAL/STOP = neg. edge : CPU TP10 (SA LATCH)
CLOCK = pos. edge: DSP TP17 (LCS)
VH = H7P4
U 5- 3 0000
U 5- 6 AP7C
U 7- 3 0000
U 7- 6 H7P4
U 15-11

H7P4

U 17- 6

0000

U 21- 3 H7P4
U 21- 4 0000
U 31- 1

H7P4

U 32- 1

H7P4

U
U
U
U
U
U
U
U

33-12
33-13
33-14
33-15
33-16
33-17
33-18
33-19

7172
0547
F9F3
OA5F
0915
55A6
U5H1
7475

U 35-13

12U8

U 46- 1
U 46-11

H7P4
H7P4

U 47- 8 H7P4

DSP 4-38

U 69- 8 H7P4
U 69-11 0000
U 69-12 H7P4
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U

71- 1
71- 2
71- 3
71- 4
71- 5
71- 6
71- 7
71- 8
71- 9
71-11
71-12
71-13
71-14
71-15
71-16
71-17
71-18
71-19

0000
A391
2235
8242
HPU1
A9A4
AA06
H2A3
u898
U898
H2A3
AA06
A9A4
HPUl
8242
2235
A391
0000

U 75- 8 H7P4
U 75-10 0000
U 75-11 0000

[NORMAL MODE]

Performance Verification - Model 64100A
Table 4-24. Signature Analysis Loop R
LOOPNAME: POWER-ON RAM TEST FAILURE

-

SETUP NAME: DISPLAY RAS ADDRESS CHECK

The refresh of dynamic RAM is performed by a RAS to each row address of RAM as
the CRT controller IC accesses RAM for display data. The display addressing and
refresh circuitry are checked during RAS. Since the display is operated during
the RAM failure loop,
the mainframe may be forced into this loop by removing
RAM IC A5U23.
ST/SP/START = pos. edge: DSP TP16 (HVRTC)
QUAL/STOP = pos. edge : DSP TP16 (HVRTC)
CLOCK = pos. edge : DSP TP7 (HDRAS)

[NORMAL MODE]

VH = 279A
U 5- 8
U 5- 9

279A
279A

U 35- 4

U 7-11
U 7-12

279A
P5H2

U 37- 6 high
U 37-11 279A
U 37-12 0000

U 8- 6
U 8- 8
U 8- 9

72P9
0000
279A

U 15- 5 high
U 15- 6 high
U 15- 8 high
U 16- 2
U 16- 6
U 16- 8
U 16-10

0000
279A
279A
0000

U 17- 3 9U8C
U 18- 7

23- 3
23- 4
23- 5
23- 6
23- 7
23- 9
23-10
23-11
23-12
23-13
23-15

U 38- 3

279A

U 48- 5

279A

U
U
U
U

49- 4
49- 7
49- 9
49-12

9U8C
355A
3P32
PF45

U
U
U
U

50- 4 46H1
50- 7 OH97
50- 9 AH4p
50-12 861H

U
U
U
U
U

56-11 7H02
56-12 355A
56-13 3P32
56-14 46H1
56-15 1355

U
U
U
U

57-11 A9FP
57-12 H3CP
57-13 6H44
57-14 PF45

279A

U 21- 2 P289
U
U
U
U
U
U
U
U
U
U
U

low

279A
279A
861H
OH97
AH4p
PF45
355A
3P32
46H1
9U8C
279A

U
U
U
U
U

58-11 OH97
58-12 AH4p
58-13 861H
58-14 F513
58-15 8447

U
U
U
U

65- 4
65- 7
65- 9
65-12

C811
12FO
19A8
FCHU

U
U
U
U

66- 4
66- 7
66- 9
66-12

279A
8P54
U424
4AHP

U
U
U
U

67- 4
67- 7
67- 9
67-12

279A
279A
279A
279A

U
U
U
U

68- 4
68- 7
68- 9
68-12

614c
2AOH
8AH4
A187

DSP 4-39

Performance Verification - Model 64100A

Table 4-25. Signaure Analysis Loop S
LOOPNAME: DISPLAY TEST

-

SETUP NAME: CRT CONTROLLER OUTPUTS-DISPLAY TEST

During the display test, signature analysis loops are set and reset around the
repetitive display pattern. Control stimulus is provided to the CRT controller
IC during the display loop.
This setup allows the checking of the CRT controller IC outputs including the
character code outputs and control signals. It also allows the checking of the
character generator ROM and HSYN and VSYN circuitry.
ST/SP/START = pos. edge: DSP TP16 (HVRTC)
QUAL/STOP = neg. edge : DSP TP16 (HVRTC)
CLOCK = pos. edge : DSP TP4 (HCHAR)
VH

= UAl1

U
U
U
U
U
U
U
U

3- 3
3- 5
3- 7
3- 9
3-12
3-14
3-16
3-18

676p
5HP8
5312
c18H
676p
5312
4489
c18H

U
U
U
U
U
U
U
U

4- 3
4- 5
4- 7
4- 9
4-12
4-14
4-16
4-18

U239
P328
890C
7U45
A2F2
89H9
0828
0000

U 9- 1

0472

U 11- 6 1U91
U 11-8 P1F7

U 33- 1
U 33- 2
U 33- 3
U 33- 4
U 33- 7
U 33- 8
U 33-23
U 33-24
U 33-25
U 33-26
U 33-27
U 33-28
U 33-29
U 33-35
U 33-36
U 33-37
U
U
U
U
U

9H7U
A903
CP98
4C9F
8554
UAl1
A7U9
731A
1939
58H3
73F8
U239
0828
UAl1
0000
0000

53- 3 0000
53- 6 8719
53- 8 up63
53- 9 0472
53-11 0000

[NORMAL MODE]

U
U
U
U

54- 2
54- 6
54-10
54-11

0000
0000
0000
UAl1

U 60- 9 738F
U 60-10 C67P
U 60-11 3930
U 60-13 417H
U 60-14 c8pU
U 60-15 56A6
U 60-16 2PP7
U 60-17 0000
U 61-15

9FAl

U 62-15

3F33

U 63- 5
U 63- 9

06H6
0520

U 72- 8 127U
p86p

U 12- 9

UAl1

U 74-11

U 17- 8

9H7U

U 78- 3 UAl1
U 78- 5 8719
U 78- 9 127U

DSP 4-40

Performance Verification - Model 64100A
Table 4-26. Signature Analysis Loop T
LOOP NAME: DISPLAY TEST

-

SETUP NAME: CRT'CONTROLLER READ FROM RAM

During the display test, signature analysis loops are set and reset around the
repetitive display pattern.
This setup checks circuitry associated with the CRT controller accesses to RAM
which consists of address counters, data path, and control of the data buffers
and data latch.
ST/SP/START = pos. edge : DSP TP3 (VSYN)
QUAL/STOP = neg. edge : DSP TP3 (VSYN)
CLOCK = pos. edge: DSP TP13 (LDCAS)

[NORMAL MODE]

VH = P5H2
U 1- 8
U 1-11

P5H2
5FC1

U 19- 3
U 19- 6
U 19- 8

A6FC
PUC 9
96uA

U 2-11

0000

U 21- 2

5FC1

U 5- 6
U 5- 8

0000
0000

U 7- 6
U 7-11

P5H2
P5H2

U 8- 6
U 8- 8
U 8- 9

72P9
0000
P5H2

U 9-10

H5AU

U
U
U
U
U
U
U
U
U
U
U

23- 3 P5H2
23- 4 P5H2
23- 5 u2P6
23- 6 6c86
23- 7 8P54
23- 9 0000
23-10 0000
23-11 0000
23-12 0000
23-13 0000
23-15 0000

U 12- 5
U 12- 6

P5H2
0000

13- 1
13- 4
13-10
13-13

74P7
6179
4186
75FH

U 15-11

P5H2

U 16- 6
U 16- 8

P5H2
P5H2

U 17- 3
U 17- 6

CP11
P5H2

U 18- 5
U 18- 7
U 18- 9

P5H2
P5H2
0000

U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U

32- 2
32- 3
32- 4
32- 5
32- 6
32- 7
32- 8
32- 9
32-11
32-12
32-13
32-14
32-15
32-16
32-17
32-18
32-19

75CF
901U
CF87
A454
78AH
84AC
2AF2
9135
5616
OA6c
7U21
307H
72CP
4319
A164
7328
5FC1

U 33- 5

0000

U
U
U
U

DSP 4-41

Performance Verification - Model 64100A

Table 4-26. Signature Analysis Loop T

U 35-13

0000

U 37- 3 low
U 37- 6 high
U 37- 8 P5H2
U 3.7-11 0000
U 38- 3 P5H2
U 46- 2
U 46- 3
U 46- 4
U 46- 5
U 46- 6
U 46- 7
U 46- 8
U 46- 9
U 46-12
U 46-13
U 46-14
U 46-15
U 46-16
U 46-17
U 46-18
U 46-19

7328
4657
FPPO
4319
30TH
CH8H
2522
OA6c
9135
FPHC
6U9U
84AC
A454
1315
PFUA
901U

U 47- 3 P5H2
U 47- 6 C963
U 47- 8 P5H2
U 49- 4
U 49- 7
U 49- 9
U 49-12

0000
0000
0000
0000

U 50- 4
U 50- 7
U 50- 9
U 50-12

0000
6C86
8P54
U2P6

U 56-11 P2AO
U 56-12 AAU8
U 56-13 4P5P
U 56-14 6H2U
U 56-15 5u8F

DSP 4-42

U 57-11 6c86
U 57-12 8P54
U 57-13 u2P6
U 57-14 73P7
U 57-15 high
U 58-11 A775
U 58-12 8H02
U 58-13 2P42
U 58-14 C963
U 58-15 52A2
U 65- 4
U 65- 7
U 65- 9
U 65-12

5CF3
4U2A
Ac8F
9635

U 66- 4
U 66- 7
U 66- 9
U 66-12

P5H2
8P54
6c86
1734

U 67- 4
U 67- 7
U 67- 9
U 67-12

P5H2
P5H2
P5H2
P5H2

U 68- 4
U 68- 7
U 68- 9
U 68-12

88UH
42A7
68HO
FC90

U 69- 5
U 69- 6
U 69-11
U 69-12
U 69-13

P5H2
P5H2
P5H2
P5H2
P5H2

U 75- 8 P5H2

(Cont'd)

Performance Verification - Model 64100A

Table 4-27. Signature Analysis Loop U
LOOPNAME and SETUP NAME: RAM CYCLE SELECTOR/GENERATOR
This is a hardware loop.
By moving the test jumper A5P4 from the normal (XU2)
to the test (XU1) position,
the RAM cycle selector/generator is forced to run
at the RAM clock rate.
This setup checks the RAM cycle selector/generator circuitry.
ST/SP/START = pos. edge: DSP TP14 (RCARRY)
QUAL/STOP = pos. edge : DSP TP14 (RCARRY)
CLOCK = pos. edge : DSP TP2 (HRAMCLK)
VB

= UP73

U 1- 3
U 1- 8

ACA2
UP51

2-11
2-12
2-13
2-14

8135
86F1
98PH
ACA2

U 5-11

8117

U 9-11
U 9-12
U 9-13

ACA2
low
55H1

U
U
U
U

U
U
U
U

[NORMAL MODE]

15151515-

3 7U24
5 high
6 high
8 high

U 16- 6
U 16- 8

UF74
UF74

U 18- 7 HF06
U 18- 9 2275
U 18-12 high

U
U
U
U
U
U

22- 1 low
22- 4 low
22- 8 low
22- 9 high
22-10 lot.r
22-13 669P

U 23- 3 UF74
U 23- 4 7U46
U 23-15 7U06

U 35- 1 0022
U 35- 4 low
U 36- 3 high
U 36- 6 ACU7
U
U
U
U

37- 3 low
37- 6 high
37- 8 7U46
37-11 7U06

U 38- 3 UF74
U 20- 6
U 20- 8
U
U
U
U
U
U

high
H4c1

21- 3 high
21- 4 low
21- 6 7U46
21- 8 low
21-10 high
21-11 low

U 48- 5
U 48- 8
U 48- 9

7U46
8175
7U06

U 51-15

high

U 73-13

0022
DSP 4-43/(4-44 blank)

Adjustments - Model 64100A
SECTION V
ADJUSTMENTS

5-1.

DISPLAY DRIVER AND CRT ADJUSTMENTS.

a. Completely remove the five screws that secure the top cover.
Also. remove the two (or four) screws that secure the state and
timing ground clips to the rear panel. Lift and remove cover.
b. Set the system control source switches (see

figure 5-1). located
on the back panel. to the Performance Verification position; top
part of both rocker switches should be pressed in.

c. Set the main power switch OFF and then ON.

test
5-2.

pattern

Note. the display
should now be on the screen. as shown in figure

d. Adjust variable inductor L3.(H Gain) for a

display

width

of

between 22.0cm (8-1/2 in) and 23.0cm (9 in).
e. Adjust potentiometer R1(H POS) so that the display test
tern is centered in the bezel as close as possible.

pat-

f. Adjust potentiometer R26 (V GAIN) so

that the display test
pattern is from 14.0cm (5-1/2 in) to 15.0cm (5-3/4 in) high.
NOTE

There is no vertical position
adjustment and
pattern may be offset up to
.6cm (1/4 in).
Magnetic fields from soldering irons. transformers.
and other electromagnetic field producing electronics may cause a portion of the display to be
off screen in the vertical direction. Reducing the
vertical gain or removing the electromagnetic field
producing device should fix this problem.
g. Adjust potentiometer R15 (FOCUS) for the best

n.

overall

focus.

If the display is not level. loosen the yoke neck screw. rotate until the display is level. then retighten yoke neck
screw (see figure 5-3).

DSP 5-1

Adjustments - Model 64100A

R15
FOCUS

R9
INTENSITY

~ ~
J1

L3
HGAIN

J2

!:I

D

Ri
HPOS

R26VGAIN

0
DISPLAY DRIVER BD

(64100-66527)

Figure 5-1.

DSP 5-2

Location of Display Driver Adjustments

Adjustments - Model 64100A

Figure 5-2.

Display Test Pattern

DSP 5-3

Adjustments - Model 64100A

"
POWER SUPPLY

I

I

DISPLAY DRIVER

NECK YOKE SCREW

L0

I

I

I

I

I

I

I

I

!

I

I

I

I.

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

FAN

(

CRT

----

~

DDDDDDDD

c:::::J c:::::J c:::::J c:::::J

OOOOOOOOOODOOO

DO

DODDDODODODD

DD

00000000000000
00000000000000
I

I

Figure

DSP 5-4

5-3.

000

ODD

Location of Yoke Neck Screw

aD

Replaceable Parts - Model 64100A
SECTION VI
REPLACEABLE PARTS
6-1.

INTRODUCTION

6-2. This section contains information for ordering parts for your 64100A
Display circuitry.
Table 6-1 lists abbreviations used in the parts list and
throughout this manual.
Table 6-2 lists all the replaceable parts for the
Display circuitry.
Table 6-3 contains the names and addresses that correspond
to the manufacturers' code numbers.
6-3.

REPLACEABLE PARTS LIST

6-4. The organization of the parts list in table 6-2 is by electrical
assemblies
and their
components in alphanumerical order
by reference
designation. The information given for each part consists of the following:
1. The reference designation as used on component locators and
schematics.
2. The Hewlett-Packard part number.
3. The check digit (CD), for HP internal use only.
4. The quantity. The total quantity for each part is given
only once, at the first appearance of the part number for
each assembly.
5. The part description.
6. The manufacturer's code (a five digit number).
7. The manufacturer's part number.
6-5.

ORDERING INFORMATION

6-6. To order a part listed in the replaceable parts table, quote the HewlettPackard part number and check digit, indicate the quantity required, and
address the order to the nearest Hewlett-Packard office.
6-7.
include
and the
Packard

To order a part that is not listed in the replaceable parts table,
the instrument serial number, the description and function of the part,
number of parts required.
Address the order to the nearest Hewlettoffice.

DSP 6-1

Replaceable Parts - Model 64100A

6-8.

DIRECT MAIL ORDER SYSTEM

6-9. Within the USA, Hewlett-Packard can supply parts through a direct mail
order system. The advantages of using the system are as follows:
1. Direct ordering and shipment from the HP parts center in
Mountain View, California.
2. No maximum or minimum on any mail order (there is a minimum order amount for parts ordered through a local HP
when the order requires billing and invoicing).
3. Prepaid transportation (there is a small handling charge
for each order).
4. No invoicing (to provide these advantages, a check or
money order must accompany each order).
6-10. Mail order forms and specific ordering information are available through
your local Hewlett-Packard office.

DSP 6-2

Replaceable Parts - Model 64100A

Table 6-1- Reference Designator Abbreviations
REFERENCE DESIGNATORS
A
B
BT
C
CP
CR
OL
OS
E

~

assembly

=

motor

~

battery

=

capacitor

F
FL
IC

= coupler
~

diode
~ delay line
= device signaling (lamp)
= mise electronic part

K
L
LS
M
MK

MP
P

::::: fuse
~ filter
= integrated circuit
~ jack
~ relay
= inductor
~ loud speaker
= meter
= microphone

a
R
RT
S
T
TB
TP

mechanical part
plug
= transistor
= resistor
= thermistor
= switch
= transformer
= terminal board
= test point
=

~

U
V

= integrated

circuit

= vacuum, tube, neon

bulb, photocell, etc

VR
W
X
Y
Z

= voltage regulator
~

cable

= socket
~

crystal

= tuned cavity network

ABBREVIATIONS
A
AFC
AMPL
BFO
BE CU
BH
BP
BRS
BWO
CCW
CER
CMO
COEF
COM
COMP
COMPL
CONN
CP
CRT
CW

= amperes

= automatic

frequency

control
= amplifier

= beat

frequency oscillator

= beryllium copper

=

henries
hardware

HEX
HG
HR
HZ

= hexagonal

IF
IMPG
INCO
INCL
INS
INT

:::: intermediate freq
= impregnated
= incandescent
= include(s)
:::: insulation(edl
= internal

K

~ kilo~1000

RMO
RMS

= rack mount only

= nominal

NPO

= negative positive zero

RWV

=

SoB
SCR
SE
SECT
SEMICON
SI
SIL
SL
SPG
SPL
SST
SR
STL

= slow-blow
= screw

= mercury
~

houris)

= hertz

binder head
~ bandpass
= brass
:::: backward wave oscillator
= counter-clockwise

:::: ceramic
= cabinet mount only
= coeficient
:::: common
:::: composition
= complete
:::: connector
= cadmium plate
~ cathode-ray tube
= clockwise

NPN

:::: drive

ELECT
ENCAP
EXT

= electrolytic
= encapsulated
= external

F
FH
FIL H
FXD

= farads
~ flat head
~ fillister head
~ fixed

= deposited carbon

~

giga (109)

= germanium
~
~

glass
groundled)

NRFR

LH
LIN
LK WASH
LOG
LPF
M
MEG
MET FLM
MET OX
MFR
MHZ
MINAT
MOM
MOS
MTG
MY
N
N/C
NE
NI PL

~

left hand

= linear taper
= lock washer
= logarithmic taper
= low pass filter

NSR

= order by description

P
PC
PF

peak
= printed circuit
= picofarads= 10~12
farads
= phosphor bronze
~ phillips
= peak inverse voltage
= positive-negativepositive
~ part of
~ polystyrene
= porcelain
= position(s)
:::: potentiometer
~ peak-to-peak
= point
= peak working voltage

~ meg~106

~ metal film
= metallic oxide
= manufacturer
= mega hertz
= miniature
= momentary
:::: metal oxide substrate
= mounting
= "mylar"

P/O
POLY
PORC
POS
POT
PP
PT
PWV

~

nano 110-9)

= normally closed

:::: neon
= nickel plate

(zero temperature
coefficientl
= negative-positivenegative
= not recommended for
field replacement
= not separately
replaceable

OBO
OH
OX

PH BRZ
PHL
PIV
PNP

~ milli~10--'l

= normally open

N/O
NOM

~

OEPC
DR

G
GE
GL
GRD

H
HOW

~

RECT
RF
RH

= oval head

= oxide
~

= rectifier
= radio frequency
= round head or
right hand

= root-mean

sq uare

reverse working
voltage

= selenium

= section(s)
= semiconductor
= silicon
:::: silver
~ slide
= spring
= special
= stainless steel
~ split ring
= steel

TA
TO
TGL
THO
TI
TOL
TRIM
TWT

:::: tantalum
~ time delay
toggle
~ thread
= titanium
= tolerance
= trimmer
= traveling wave tube

U

= micro=10---6

VAR
VOCW

= variable
= dc working volts

WI
W
WIV

= with
= watts
;= working inverse
voltage
= wirewound
= without

WW
W/O

~

DSP 6-3

Replaceable Parts - Model 64100A
Replaceable Parts

Table 6-2.
Reference
Designation

HP Part
Number

AS

64100,-66530

6

Cl

0160-5:l21
0160-·5321
0160-4822

8
8

C2

C3
C4
GS

01611--S~,21

0160-S~321

0160-5321
0160·-5:,21
0160·-5321

CH

0160,-5321

C16
C17
CI.8
Ct9
C20

C2i
C2~~

C2:~

C24
C2S

B
8
EI

()j,60-S32i

~1

0160·-5321
0160-,5321
0160·-5321

8
8

01611-5321

o160·-532j.

0160-5321
01(,0-5321
0160 ·-53'! 1
0160-5:121
Oi60-'S~;21

o160-S:l21.

8

13
Il

8
8
B

fJ

01130-0374

3
8

0160-5321

13

Oi60-·S;32j.

0160-5321

8
8

Oi60-'S~~21

fl

1901-05;35
1901-,,11535
19111,-0535

9
9

190i-0535

91'70-0029

4

9
9

3

2

182

7

2

12513-0182
).8111--0307

7

MP1

5040-·(,067

MP~.~

~;040-6067

P :.:~
p;;

i~~SB"~O

2

o

07S7-0;~~80

07S7-"02fJO
07~·:)7-·0280

07S7 "0280
M

06913-3438
R6

07S7--0;.~80

~,

WI

07~:·)7-·0280

R8
R9

07S7 "0280

3
:;
3

R10

M

0698-3444
0683""11115
07S7·-0~_~8(}

0691l-702fJ
0698,-7028
069BM.. 702B

0698-7028
069B--70~~8

06913-7028

1~;=1

7

:1
s
5
S

5
5

0698-70f~8

S

07S7·-02ao
0757·-0;.:?80

3
3

0757-0,~BO

3

Ii( ~!~~

0684-i21i

7

fU23
N24
TP i ,-13

0757-0;:'BO

:1

TPGND
Ul
U2

U:l
U4
US
U6
U7
US

0698-3633
0360-0535

o

o

0360-,0535

0

1820-0681
1820-j.4S3
Hl20-1917
1820-1'H7

4

1820-1201

6

1.820-'1453

1820-0681
1820-1112

7

5

0
1
1

1

20
3
2
2

o

4
8

3

DISPLAY CONTROLLER BOARD ASSEMBL.Y

28480'

64100-66530

,0Iu'
,01uf
lOOp'
.01uf
.01u'

+80-201 100VDC CER
+80-,20% iOOVDC eEr~
+-5% 100VDC CER
... aO-20X iOOVDC CEr~
+80-201 100VDC CER

28480
28480

0160'-5321

284BO

0160-4822

213480
28480

Oi60-S~~21

GAPACrrOR-·FXD
CAPACITOR-FXD
CAPACITOR-FXD
CAPACITOR-FXD
CAPACITOR-FXD

,Oiuf
,01ul
,0luf
,01u'
,Oluf

+80-201
+80-20%
+80-2111
+80-20Z

!OGVDe
100VDC
100VDC
100VDC
100VDC

CER
CER
CER
CER
CER

28480
28480
28480
28480
28480

011>0",,5321
0160-.. 5321
0160-·5321

CAPACITOR-FXD
CAPACITOR-FXD
CAPACITOR-FXD
CAPACITrnl-FXD
CAPACITOR-FXD

,01u'
,Olu'
,01u'
.01uf
,01u'

+80-201
+tlO-20%
+80-201
+80-20%
+BO-201

100VDC
100VDC
loaVDC
iOOUDC
100VDC

CER
CER
CER
CER
CER

28480'

0160 .... 5321

+BO-2G~

,Oiu' +80-20% iOOUDC GER
,Oill .. '.80--201: 100VDC CER

,Hut' .·80-·211% 10llVDC CER
,Olu' +80-20X 100UDC CER
,O:l.u' +80-20:': iOOVDC eER

CAPACITOR-FXD
CAPACITOR"-FXD
CAPACITOR·-FXD
CAPACITOIl-FXD
CAPACITOR-FXD

,Olu' +130-201 100UDC
,Ohf +80-20% 10llVDG
,01u' +80·-20% IOOVDe
. Oluf +80-;~0% iOOVDC
lOu' +-10% 20VDC TA

CAPACITOR-FXD
CAPACITOR-FXD
CAPACITOR-FXD
CAPACITOR-FXD
CAPACITOR-FXD

,01u'
,1I1u"
,01u'
,01u'

CER
CER
CER
CER

;~8480

Oi60~··S3~~i

0160-·5321
0160-·S321

0160-·5321
Oi60·-~1321

;:'8480
284811

o160"~S3~?1

2a480

0160--5321

2t1480
28480
l!84tlO
;,fl4BO

0160-5321
0160-'5321
0160-'5321
OJ.60·-5321

Oi60 ··S32:i.
M

~~8480

Oi60-S3:':~i

28480

o160""5~,21

284BO

0160-'S~;2:\

2fJ480
28480

oi60-S3(,~i

~?'8480

01BO .... 0374

,0luf +80-201 1llOVDC eER
.80-20% 10llVDC CER

28480

+80-20% 100VDC CER
+80-20% 100VDC CER
+ElO-20;': 10QUDC CER

284EI0

oi60 ··S32i
0160",,5;,21
0160",,5:121
0160",,5:,21
0160-S321

DIODE-8M BIG SCHOTTKY
DIODE-8M SIG SCHOTTKY
DIODE-8M BIG SCHOTTKY
DIODE-BM BIG SCHOTTKY
CORE-SHIELDING BEAD

~,84i30
~,84811

;28480

284130

1901-0S3S

:1.901-,,0535
19111-0535

28480

9170'-0029

28480
28480

5040-606'7

28480
28480

12~J8·MO

;':~8480

18111-,0307

~,4S46

C4-"1/Il""TCI-"j. 0 0 i ""F

RESISTOR
RESISTOR
RESISTOR
RESISTDR
RESISTOR

lK 11 ,125W F TC=0+-100

RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR

1K 11 ,125W F Te-O+-IOIl
lK 1% ,125W F Te-0+-100
iK 11 .12SW F TC-O+-iOO
316 1% ,125W F TC=0.-100
100 1% .:l.2SW F TC-O+-iOO

24546
28480

iK 1% .i2SW F TC=O+-iOO
iK 1% ,125W F TC~O+-100
1K :1.% ,12SW F TC-0+-100
147 1% ,125W F TC-O+-l00

M

28480

28480

PC-EXTRACTOR
PC-EXTRACTOR
TEST :llIMPEll
TEST JUMPER
NETWORK-CNDeT MODULE DIP:16 PINS: ,1

Oi60·M·S~52i

l!13480

l.90i-OS3S

5040··.. 6067
12SEI""OiI32

iB2

24546

C4-1lil'-TO-"1 0 0 1 .... F

24546

C4·-l.I8-HI·- ill 0 l'-F

:.?4S46

C4-1/8-TO-iOlli-F

;.?848II

0698""34313

2~4S46

G4-'1/EI'-TO-i I) 0 1 '-F

~~4S46

C4-i/8-TO-1001-F
C4'-I/I)-"1'I:1"-1 0 0 i -·F
C4-1/13-TO-316-F'
0683'-1015

2~4S46

28480

0698-,71128
0698·_·70;"8
06'18-,71128
0698,-7028

28480

II 698",,7 1I;?1l

RESISTOR lK II ,125W F TC=-O+-lOO

28480

RESISTOR
RESISTOR
RESISTOR
RESISTOR

27
27
27
27

10%
10%
10%
10%

TC=-270/+S40
TC=-270/+S40
TC=-270/+S40
TC=-270/+540

28480
2<1480

RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR

27
27
27
lK
iK

10% .i2SW CC TC=-270/+S40
10% .125W CC TC a -270/+S40
10% ,125W CC IC=-270/+S40
IX ,125W F TC-0+-l011
i% ,12SW F TC=O+-iOO

213480

0698".. '7028

28480

0698""70~~B

28480
24546
24546

0698 .... '7021:l
C4-1/B-TO-1001-F
C4-1/1l-TO-l001-F

,125W
,125W
.i25W
,125W

CC
CC
CC
CC

RESISTrnl lK 1X .125W F TC-II+-iOO
RESISTOR 120 lOX ,25W FC TC--400/+6DO
RESISTOR lK iX ,125W F TC=O+-iOO
REllISHlr~ 390 Sl: 2W MO TC·'0+""200
TERMINAL TEST POINT PCB
TERMINAL rEST
IC GATE TTL 5
IC CNTR TTL B
I C BFR TTL. LS
IC BFR TTL LS
IC
IC
IC
IC

POINT PCB
NAND QUAD 2-INP
BIN SYNGHRO POS-EDGE-TRIG
LINE DRUR DClL
LINE DRVR OClL

GATE TTL L.S AND QUAD 2-IN?
CNTR TTL S BIN BYNCHRO POS-EDGE-TRIG
GATE TTL 5 NAND QUAD 2-INP
FF 11 L L,.S D-TYf'E POS'-EDGE-nUG

~?4S4(;)

C4-1/8'-TO'- 100 l-F

01121
24546

eJli2ii
C4-1/8-TO-i001-F

28480
011000

ORDER BY DESCRIPTION

00000
01295
(J :1~~9S

01295
01295
01295
01295
01295
01295

See introduction to this section for ordering information

DSP 6-4

Mfr Part Number

CAPACITOR-FXD
CAPACITOR-FXD
CAPACITOR-FXD
CAPAcnOll-FXD
CAPACITOR-FXD

CAPACITOR-FXD
CAPACITOR-"FXD
CAPACITOR-FXD
CAPACITOR-FXD
CAPACITOR-·FXD

B

8
II

II 160-,5321
OJ.60-·S~~21

P4

8
8
8
8

111.60-5321

28

Mfr
Code

Description

Qty

2

8

C6

C14
CtS

D

0160--5321

C7
GEl
C9
Cl0
(;12
C1:l

C

0698",,3633

ORDER BY DESCRIPTIDN
SN74S00N
SN74S16;3N
SN74LS240N
SN74LS240N
SN74LS08N
SN748163N
SN74S00N
SN74LS74N

Replaceable Parts - Model 64100A
Table 6-2.
Reference
Designation

HP Part
Number

c Qty
o

U9

1820'-1:~22

;:

ia~~O-0629

0
4

U10
UH
Lli2

IH;l
U14

IC
IC
IC
IC
IC

FF TTL S ,),-I( NEG-·EDGE-·TRIG
GATE TTl- S OR QUAD 2-INP
FF TTl.. S D·. TYPE POS-EDGE-TrUG
GATE TTL L.S NOR QUAD 2-·INP
INV TTL S HEX i-·HIP

IC
IC
IC
Ie
IC

GATE TTL.
GATE TTL
GATE TTL
FF TTL. S
GATE TTL

IC
IC
IC
IC
IC

28480

1818·";500~i

284fJO
28480
284811

Hl1fl'-300S
i81B .... 300S
1818,-30 OS
1818·.. 30 OS
1818-:111115

t820-120B

3

4

1820-0688

1
8
0
9

:2

1
3
2

TTL. S NOR

U1S
U1b
U17
UiB
U19

1820·-1197

U20
U21

1820-0688
1820'-0683.

6

U22

1820-'1322

;2

U23

1.818-30 OS
1818-,3005

7

18113-3005
1818-3005
181.13-30 OS
1818-3005
1818·"30 OS

7
7

IC NMOS 64K I)YNAMIC RAM :1. SOMMNB
IC NMOS 641( DYNAMIC RAM iSO-NS

'"}

IC NMOS 64K DYNAM:r.C RAM 150··N!>
IC NMOS 641< DYNAMIC RAM 1S0 "NS

U24

L125

1J26
UZ'j'

U28
U29

1I311
U:U
U32
U3:3
U34

1818-3005

1

7
7

U3S

1810,-0536
1820-1144

1I36
U37
LJ3fl
U39

1820-0681
1818,-3005
1818·-3005

7
6
3
4
7
7

U40
U41

3

3

5

U43
U44

11318-3005
1818'-3005
18Hl-3005
i818-3005
1B18-300S

7
7
7
7

U45
U46
U47
U48
U49

1818-3005
1820-1997
1820'-1208
1820-0693
1820,-1015

7
7
0

2

usa

1820-1015
i820·"1210

0
7
6

1

3

2

2
8
8

1

U4;':~

USi
IJS2
US:,
LJ54
US~'5

tJ5b
US?
US8
US9
Ll60
Ubi
U62

U63
U64

18<~0-1i44

1820-1112
1820-1191
1820,-0697
1fJ211-143S
18211'-1435
1820-1435

0960-0530
1816-1496
1820-'1432
1820-:1.432
1820-1112
1820-1130

7

3
8

:3

7

:,

0

i8<~1l-1428

9

1820-1428

18;<0-1428

'I
9

Ub9

iB20'-1;,~OB

:~

U70
U71

1820-2075

U72

1820-1451
j.820-1492

U74

1820··1191

U7S
U76

U78
XUi

j.821l-0685
1820-1303
1820-1303
1820-0693
1200-0607

XU2
XU33
XU34

i200-·0607
1200-0654
1200-0607

un

"

5

1.820-142B

'l

4

:1
(1

7
3
f)

2

(1

0
0
7
0

3

SN74LS=52N

111295

SN74LS86N
SN74Sl.12N
SN741..SIIIIN

01295

LS NAND QUAD

~~-INP

OJ.29S

GATE T'TL S NAND DUAL 4-INP
INV TTI_ So-HEX 1-INP
GATE TTL S NOll QUAD 2-INP
NMOS 1,4K DYNAMIC RAM 1S0'-NS
NMOS 641( DYNAMIC RAM 1S0-NS

01295
OJ.295
284811

01295

28480

IC NMOS 64K DYNAMIC RAM :t SO'-NS

2B480

IC NMOS 641( DYNAMIC RAM 1S0-NS
IC DRVR TTL L.B LINE DRVR DeTl
IC DRVR TTL 1..8 LINE llRVR OCTL
IC MI CROP ROC-·ACCESS NMOS B,-BIT
NETIoIORI(-RES 27 OHM 16 PIN DIP
IC GATE TTL LS NOR QUAD 2-INP
Ie GATE TTL LS OR QUAI) 2-INP
Ie GATE TTL S NAND [lIJAD 2·-INP
IC NMOS 64K DYNAMIC RAM iSO-·N8
Ie NMOS 64K DYNAMIC RAM 150-NS

28480

DYNAMIC
DYNAMIC
DYNAMIC
DYNAMIC
DYNAMIC

RAM
RAM
RAM
RAM
RAM

SN74S20N
SN74S114N
SN74S0;~N

1818-300S

o1~~9S

1818·"·30 liS
SN74LS244N
SN74LS244N

34649

C8~~7S

284ilO

1810--05:')6

SN74l.S02N

01295

SN741..S~'2N

01295

SN74S00N
1B18-·30 OS
11318-3005

28480

28480

1818-3005
j.llill·-30 05

150·-NS

28480

iSO-'NS

201480

iSO-NS

28480

1B18··300~:;

iSO'-NS

28480

iil18-~,0

iSO-NS

2B4BO

NMOS 64K
NMOS 641(
NMOS 64K
NMOS 64K
NMOS 641(

Ie
IC
IC
IC
Ie

NMOS 64K DYNAMIC RAM 150-NS
FF TTL l"
." D.... TYPE P OS-EDGE -. TRIG PRl IN
GATE TTl. LS DR QUAl) 2-INP
FF TTL. S D-·TYPE POS-EDGE'-TRIG
MUXR/DATA-SEL S 2'-Tll-1 LINE DRVR

Ie
IC
IC
IC
IC

MUXR/DATA-·SEl. s 2-TO-1 LINE DrlVR
GATE TTL. l..f;) AND-OR INV DUAL 2-IN?
GATE T'TL S NOR QUAD 2-INP
FF TTL LS D-TYPE POf)-EDGE-TRIG
FF T'TL. S I)-·TYPE POS·-EDGE-TRIG

Ie DRVR TTL. S NAND
IC CNTR TTL LS BIN
IC CNTR TTL LS BIN
Ie CNTR TTL L.S BIN
OSCILLATOR 2SMHZ

SN74S:':~ON

0129S

o129~i

Ie
Ie
Ie
II:
Ie

LINE DIJAI.. 4·-INP
LIP IDllWN SYNCHRO
UP/DOIolN SYNCHIlO
UP/DOWN SYNCHRO

21( x 8

IC CNTR TTL. l.S BIN SYNCHRCI POS--EDGE-TRIG
IC CNH~ TTL LS BIN SYNCHRO POS-·EDGE-·TRIG
IC FF TTL LS D-TYPE POS""EDGE>-TR IG
IC GATE:: TTL B NAND 13-INI'
MIJXR/DATA"·SEL. TTL L.S 2.~··TO-i
MUXR/DATA-SEL. lTl LS ;~-·TO"·1
MIJXR/DATA-SEL TTL U3 2···lCi- i
MUXR/DATA-·SEL TTL L8 2-T[)-j.
IG GATE: TTL. LS OR QIJAD 2·-INP

IC
Ie
IC
IC

LINE: QUAD
LINE QUAD
LINE QUAD
LINE QUAD

05
1818·-3005

O:1.~~9S

1818-300S
SN'74L.S374N

01295

SN74LS32N

01295

SN74S74N

01295

SN74S1SIlN

28480

01295

SN74SiS8N

~~B4ao

iB20~~i2iO

01295

SN74L50,!N
SN74Ui74N

01295
01295
0129S

01295
Oi29S

SN74Si7SN

SN74Si40N
SN74LS669N
SN741..S669N

0:1295

StJ74LE669N

28480

0960-115311

;~8480

18i6-·J.496
SN'I4L.Si6:lN

012<,5
0:1.295

0129S
01295
01295

SN74LSi63N
SN74LB74N

SN74S13:,N
SN'?4L81 S8N

Oi;':~95

SN74LSJ. SUN

OJ.295

SN74LBiS8N

01295
01295

SN'i'4LS;32N

IC DRVR TiL. L.S LINE L>RVR DCTL.

01295
01295

SN741.. S245N

2-·INP

Oi~~9S

SN74S31lN

Ie MIse TTL L.S
Ie GAlE TTL L. NAND QUAD

4

9
9

EXCL.-OR QUAD 2-INP

SN74S04N

01295
0129S

J-K NEG-EDGE-mIG

IG ROM

3

5

U67
U68

LJ73

3

8

UbS
Uf.)6

1820,-2024

3

SN74S1 j.2N

SN74S32N
SN74S74N
SN74LS02N

IIj.295
01295

LS OR "UAD 2-INP
S NAND DUAL. 4-·INP
LS

01295

0129S
01295

M

7

:3

1820-1208

16

7

1820-2024
1820-,2024
1820-2191

SN74S112N

2-

3

18<~0-0629

111295

[lUAD 2-'INP

Mfr Part Number

IC GATE

6
6

1a~~O'-12il

Mfr
Code

Description

2

1820-1449
1820-0693
j.8211-1144
1820-0683

B

Replaceable Parts (continued)

SN74LS158N
SN74LS244N

IC I83·1015

R8

0683-6825
2100-3892
0683-5645

R'I
RIO

Replaceable Parts (continued)

c Qty

Description

D

e
7

z

7

1

0
7

2
II

Mfr
Code

RESISTOR I~ 51 2W ~O Te-0 •• 200
RESISTOR 100 51 .25W FC TC •• 400/.S00

01121

RESISTOR 6.8K 10% .25W FC TC~0+-100
RESISTOR -TRMR 2.5M 10% C TOP-ADJ I-TRN
RESISTOR 560K 5% .25W FC TC.800/.900

28480

UUO
28480

UUO

Mfr Part Number
07114.00111
CBlOIS
0683-6825
2100-3892
0683-5645

RII
RI2
RU
RIQ
RU

0683-5645

7

RESISTOR 560K 5% .25W FC TC.800h900

28480

0683-5645

01183.1055

5

01l~3.10'5'5

'5

R!IIITOR 1M 51 .25w 'C Tc_.aOO/.'IOO
~E8ISTOR 1M 51 .2'5W FC TC_·~OO/.'IOO

CSlon
CBIOS5

0683-4745
2100-3892

6
0

RESISTOR 470K 5% .25W FC TC~0+-100
RESISTOR-TRMR 2.5M 10% C TOP-ADJ I-TRN

01121
OIlU
28480

UUO

0683-4745
2100-3892

Rh
RI7
R\8
RI'I
R20

01183.1055
01183.1045
01083.1045
01181.2215
01>83-2225

'5

All
R21
R23
R24
RIS

J

R!SISTOR
RESISTOR
RESISTOR
U!ISTOR
R~S1 STOR

1M 51 .25w 'C TC •• 800/.IIOO
10o~ 51 .25w FC TC-.400/.loo
lOOK 51 .25w FC TC-.400/.800
220 51 .25W FC TC •• 400/+1I00
2,2K 51 ,25w FC TC-.4001.700

OIUI
01121
01121
01121
01121

cSlon
CBI04I
CBlO41
CU211
CB2211

01183.2225
OlleJ.21U
OU3-102S
OIl83.lon
0118"'215

3
3
II
'I
7

I

RESISTOR
R!stSTOR
RESISTOR
RESISTOR
RESISTOR

2.aK 5' .25W FC TC-.400/.700
I,IK 51 ,zsw FC TC •• 400/.700
IK 51 .15w FC TC •• 400/./lOO
IK 51 .2Sw FC TC_.400/.,00
220 51 ,5W CC TC_0.5111

01121
OIUI
01111
OIUI
01121

Csun
csun
caloas
CBlon
!BUIS

AlII
R27
R2B
R2'
Uo

2100.3151>
OIl83.IOGS
01l8J.1045
OllBJ.1035
H57.04U

I

I

3
I
a

RE,ISTOR·TRMR 200~ lOX C IIDE.ADJ I.TRN
RESISTOR lOOK 5x ,25w ~c TC-.40~/+SOO
R!SISTOR lOOK 5x .25W Fe Tc-.aOO/.Soo
RESISTOR 10K " ,Z5W FC TC_.400/.700
RESISTOR 81.5K I~ ,IZ5W , Te_O •• IOO

UUO
OIUI
01121
01121
24541>

IIOO.USI>
C810a5
C81045
C810U
CQ.II8·T 0·U5Z·'

R31

0751.0470
0751.04113

3
4

~ESISTOR IUK IX ,I25W , TC-O+·IOO
RESISTOR eZ.5K IX .125W , Te-O •• IOO

U54,
145411

Chl/hTO.IOU·,
C4.I/"TO·I2U.F

0757-0280

3

IIU
R33

]
]

I

]

R34
R35

01183.1015
01>83·2235

R36
R37
RJ8
R3'
ROO

011'18.3450
011'8.3450
01>83.3315
01081>.03]5
01l8hl211

'I
'I
4
a
7

R41
R42
1143

ol>eQ.1211

7

0683-6815
0683-6815

5
5

R44
thru
R46

0683-8215

3

R47
IIU

071>4.0011>
01083·1015

R49
R50
Tl
T2

0757-0124
0683-1025
9100-4195
9100-0491

TPITP1
U\
U2
US
U4
. VRI

7
5

I

a
I

FTC~0+-100

24546

C4-1/8-TO-l00l-F

I

RESISTOR 100 51 ,Z5W FC TC •• 400/+S00
RESISTOR ilK 5~ .25W FC Tc-.aOO/t800

01111
01121

CBIOl5
CBia]!

I
I

RESISTOR
RESISTOR
RESISTOR
R!SISTOR

42.2K II .12'5W F TC-OhIOO
42.iK IX .125W , TC-OhIOO
330 51 .25W 'C TC-.400/+/000
3.3 51 ,5~ CC TC.0+4IZ
120 lOX ,25w Fe TC-.400/.IIOO

245a.
245411
01121
01121
01121

ChI/S.TO.4UI-F
C4.I/I.thaU2·'
CB3315

RESISTOR 120 101 ,25W Fe Te-.aOO/./loO

01121

CBI2I1

2

RESISTOR 680 5% .25 W FC TC~400/+600
RESISTOR 680 5% .25 W FC TC~400/+600

28480
28480

0683-6815
0683-6815

3

RESISTOR 820 5% .25W FC TC~-400/+600

2

2

8

IX

RESISTOR lK 1% .125W

~ESUTOR

0704.0011>
CBIOIS

28480
01121
28480
28480

0757-0124
CB1025
9100-4195
9100-0491

1
1

OHO·0535

0

7

TERMINAL TEST POINT pce

1820.1437
1121>.0120
t8ZO.1451
\820.04T1

0
8

0

I
I
I
1

Ie
Ie
Ie
IC

1902-0025

5

1'I02.0oal
1'102.0044

VR4

1902-0049
1902-3036

8

C!l211

28480
01121

•

0

unGS

RESISTOR IK 51 ~w MO TC-0.-200
RESISTOR 100 51 .25W FC TC_.400/+500
RESISTOR 39.2K 1% .12W F TC~0+-100
RESISTOR 1K 5% .25W FC TC~-400/+600
TRANSFORMER-HORIZONTAL DRIVE
TRANSFORMER FLYBACK, HI V 12.5 KV ±500V

VRl
VII]
VR5

"I

MV TTL LS MONOSTBL DUAL
OP AMP QP QUAD la.DIP.p
QATE TTL S NAND QUAD Z.INP
INV TTL HEX \.INP

00000
012'5
27014
OU'!
DIn!

ORDER BY DUCRIPTJDN
IN74L.I2Z\N
lMl900N
SN74838N
SN7aO.N
1902-0025

I

DIODE~ZNR

DO~7 PD~.4W

28480

]

I
I

OIOOE.ZNR 5.IIV SI 00.7 PO_.4W TC-.,GO'l%
DIODE.ZNR IN53~]8 30V 51 PD_5W TC-.ZIIMV

28410
11410

1'102.0041
I ,,0a-0044

2
3

1
1

DIODE-ZNR 6.19V 5% DO 35 PD~.4W
DIODE-ZNR 3.16V 2% 00-7 PD~4W TC~-0.64%

28480
28480

1902-0049
1902-3036

4

10V 5%

See introduction to this section for ordering information

DSP 6-7

Replaceable Parts - Model 64100A

Table 6-3.
Mfr
No.
00000
0046G
01121
01295
04713
09023
24546
27014
27264
27777
28480
32997
50088
56289
71590
72136

Manufacturers' Codes
Address

Manufacturer Name
ANY SATISFACTORY SUPPLIER
NORELCO NORTH AMER PHILIPS LTG CORP
ALLEN-BRADLEY CO
TEXAS INSTR INC SEMICOND CMPNT DIV
MOTOROLA SEMICONDUCTOR PRODUCTS
CORNELL-DUBILIER ELEK DIV FED PAC
CORNING GLASS WORKS (BRADFORD)
NATIONAL SEMICONDUCTOR CORP
MOLEX PRODUCTS CO
VARO SEMICONDUCTOR INC
HEWLETT-PACKARD CO CORPORATE HQ
BOURNS INC TRIMPOT PROD DIV
MOSTEK CORP
SPRAGUE ELECTRIC CO
CENTRA LAB ELEK DIV GLOBE-UNION INC
ELECTRO MOTIVE CORP SUB IEC

LOS ANGELES
MILWAUKEE
DALLAS
PHOENIX
SANFORD
BRADFORD
SANTA CLARA
DOWNERS GROVE
GARLAND
PALO ALTO
RIVERSIDE
CARROLLTON
NORTH ADAMS
MILWAUKEE
WILLIMANTIC

See introduction to this section for ordering information

DSP 6-8

CA
WI.
TX
AZ
NC
PA
CA
IL
TX
CA
CA
TX
MA
WI
CT

Zip
Code
90021
53204
75222
85062
27330
16701
95051
60515
75040
94304
92507
75006
01247
50501
06226

MANUAL BACKDATING - Model 64100A

SECTION VII

MANUAL BACKDATING
7-1.

INTRODUCTION.

7-2. This section contains information for adapting this manual to instruments
with various serial prefix numbers.
7-3.

MANUAL CHANGES.

7-4. To adapt this manual to your instrument, refer to table 7-1 and make all
of the manual changes listed under the serial prefix number for your
instrument. Perform these changes in the sequence listed.

Table 7-1. Manual Changes
Serial Prefix

Make Changes

Affects

2210A

1, 2

DSP

2212A

1, 2

DSP

NOTE: DSP is the abbreviation for Display Controller and Driver boards.

MANUAL BACKDATING

DSP 7-1

MANUAL BACKDATING -Model 64100A
CHANGE 1
NOTE
The 64100-66523 Display Driver board is compatible with the 64100-66527
board with the following changes:
Table 6-2 DSP, Replaceable Parts List,
A7: Change HP Part No. to 64100-66523, CD=l.
CR2: Change HP Part No. to 1901-0719, CD=l.
T1: Change HP Part No. 9100-4075, CD=O.
CR19: Delete.
CR29: Delete.
R50: Delete.
VR5: Delete.
Page 8-22 DSP,
Figure 8-6, Display Driver
locator on page 7-4 DSP.

Component Locator.

Replace

with

component

Page 8-23 DSP,
Figure 8-7, Display Driver Schematic. Replace with Display Driver schematic
on page 7-5 DSP.

CHANGE 2
NOTE
The 64100-66519 Display Controller board is compatable with the 6410066530 board. The newer 64100-66530 board has 64K x 16 memory locations
of RAM while the 64100-66519 board has only 32K x 16 memory locations
of RAM.
The 64100-66519 Display Controller board experiences LMSYN
PROBLEMS when several option cards (using LMYSYN) are loaded into the
card cage.
To correct this problem refer to SERVICE NOTE 64100A-12.
Contact the nearest Sales/Service Office for additional information.
Section IV
Pages 4-1 thru 4-29 DSP, Section IV, Performance Verification and SA Tables,
Change: Replace Section IV with Section IV pages 7-7 thru 7-23 DSP.
Section VI
Page 6-5 DSP, Replaceable Parts List,
Change: Replace Display Controller Material list with material list
on pages 7-25 DSP and 1-26 DSP.
Section VIII
Pages 8-13 DSP thru 8-"19 DSP, Display Controller Schematics 4A -' 4D,
Change: Replace Schematics
4A - 4D
with Display Controller
Schematics on pages 7-27 DSP thru 7-34 DSP.

MANUAL BACKDATING

DSP 7-2

MANUAL BACKDATING - Model 64100A

LIVID
I'

LVID

VIDEO
DRIVER

J

CRT

V

~
~
LVSYN
/

VERT
SWEEP
GEN

(V"VY"

>

~

....
N

LHSYN
/

HOE

V

I'

/

30

2

I' ~1

~

VERT
SWEEP
GEN

HIGH
VOLTAGE

2

I

MOTHER BOARD SIGNALS

Figure 7-1. Display Driver Block Diagram

MANUAL BACKDATING DSP 7-3

MANUAL BACKDATING - Model 64100A
INTENS

FOCUS

Rig

HGAIN

B

RI2
RI!

\29

RIG
RIO
RI4
i

~

(1/

...J

,JI
u

C9

OSI
(1/

GNO

R!8

L4

II)

•

(1/

CI4

CI2

TPI

~

L!

CI!

•

0

R39

CII

~

."

A::
U

(1/

u

CIO
RI7
VRI
RI8
R8
CRS

R48

I/)

A::

u

CXI

u

V
GAIN

R37
Q4c:::::J
CRII
CRIO
CR9
R!5
R29
CI8
R28

c::::J Q5

CRI2

EJ
COO
C2!
R32
R!3
R34

R~
I'f)

II:

u

CR8
VR4

tD

t\I
II:

c::J R26
R3G
R27

A::

u

CI9
CI7

B
I"II:

TP2

•

~
TI

QQ7

~ eQI eQ3

R49
CR7
CI6

GQ8
QsG T~4 CRI4
C28
CRI!
VR2
VR3
L5
R44
R45
R46 CRIG
R43
H POS
R42 CRI7
R47
C27
0
RI
C26

B

C21

TP5

•

R25
R4
R22

R5

8Rli

GNO

•

EJ

TP3

•

R24

R20
R21
R23

R41
R40
CI
R3
R2
LI

C2

~B

DISPLAY DRIVER 64100-66523

PI

Figure 7-2. Display Driver Component Locator
MANUAL BACKDATING DSP 7,;4

C22

MANUAL BACKDATING - Model 64100A
ORIVER
II DISPL;64100-66527

ICS ON THIS SCHEHATIC
REF. DES. HP PAR Nll. MFG. PART NO.
1820-1437
Ul
74L5ZZ1
1826-0120
LM3900
UZ
18l0-1451
74538
U3
18l0-0471
U4
7406

R44
810
R45
820

PARTS INCLUDED ON
THIS SCHEHATIC
EF.
CRT
IIIICRT CABLE)

HP PART N .
Z090-004Z

E

6410O:~61603

IC POWER SUPPLY
CONFIGURATIONS
+5VJti

U3.4

~
+lZ",

+5V~

R34
CR8100

I

I:I T

11)
12}!
15

Ul

~

R40

R41

Il0

120

LVIO

~.@t-I EJt:~~Q~~~r-~__~r-

I

_H

H
L
H

f~~~~~~N
H"

o
o

LVSYN

+3.5V

------.·.-11,

R23

----lJr---------iU

'0

+23V

----11

+12V - - - -

TPl

+17V

n

L-_ _ _ _ _ _ _--'.

----jl.

~

,.

I'
.-1.

L ._ _ _ _ _ _ _ _

.

n

.

ov - - - -:lilJi\lfri':1i::F:I'fWtrxX:1!iriW::::j~. 41:_:wrlll.WJllliIMJl. . ··

141 1

d

o

HSYN

OV - - - +5V - - - -

TP3

+20V - - - -

STPS
OV - - - -

o

+l50V - - - -

OV - - - -

R2l
2.2K

RZ5
210

C23- ..--

0.01"!"~
UF

R31
162K

,
I
I

I:
I:

lOOK

4

-....J4

Ll
100
UH

H POS

I

I:

C20 l'
IUF V'

I

I:I
I

:0

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Cl

f-!~O

23~c'N tJ
l~l~~
~

L

C3

+12V

9~

·
5

R6
lK
TP

II'

t050 : \

C5
10Uf

~4 ~,",>,-",,6:.....e.--'VIfv--i\HJJ_
'7

TP3

~5.

C7 T
2200±
UF

I .----

1

1

~
6 .

'------'-:'2

R7
100

m

ItECHANICAL
CONNECTION
TO CRT SHI~LD

--< 2 Hf==:::::;---'
'---< 4

'--f.I
V

R36
42.2K

10

R38
330

•

I
I
I
I

C25
33 UF

CR4 ~

~7

_L2

m

~~ --H-G-II-I-N-~Wr-"

VE~I~L

:I

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LINEARITY

~

: 1

HORIZONTAL
YOKE

19)

1

:

C9
1. 75Uf

::>-~-UIII~)----------~~----__----------~

7

6

I

112

+12KV

I

rYf->SL-_~.~j-5-.-_..-:2"~j.,~M.;..~
_ _.:;.,5~{Vl0 <;:K_. .:t,:;,lv;0IK.:. . . ., VR1~~
1~~~ T

C8
.015
UF

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5

-

7 «-"L-_ _ _ _.....

: I

R39
3.3 ~TP

Ie

Rl3
1M

CRT

.... 6 >-A~ll'-.!.)_ _ _ _ _ _-++-I-_Y:.:;O:;.K=E_.J
/
3>-~~1~6~)__________~~__________~

I

4

I

--'

J2

.L
RB
RIB
P/O Jl
5
V
CR6
2.2K
lOOK
jl
(5)
~~~______~____~________________~______-r__~~~__~____~-4~O~Y~I~7>-~~~__________
3

~-I--~>

L.----< 6 ,....

,..---<.,

T2

CR3

4 ,.JT1
1
CR2 .,.

'1r'~__________i-~B >-~~I~O~)~F~I~L~~M~E~N~T--,

--<

L3
20-80UH

+llV

6.19

o---l---*-''<--\----=-6~~ I,!-.+I'~.--I-rv\-I
02

rP:

5 NC
12

+llV

3

~~

470Pf

13
7"
USlsA lil-''''-,-+-f1'''01''' BUlB
R SS

3L~~C

--

C4 '"
470UF ~

R3
42_lK

!I

(&JOS2

~ TPI

WIOTH

YR4~

HIGH VOLTAGE CIRCUIT

0--

9 >-H--,I",l!...)_____-,

___________

T

R33
39. lK

HORIZONTAL
SWEEP GEN

1

CRIZ

R32
Sl.SK

+40V

+5V

I

r

..

R37
4Z.ZK

I

I
I
I

CRII

11 _"-

V GIIIN

I
I

C24
llOOUF

~CRIO ~

~\ Rl8

R26
lOOK

1

o

04

r---+....l.~;f

I
I
I

24"
HOE
13 ) , T
14...-

n~~
CRS l'

I

~

P/O WI

R34
100

~.,.

I U4 v-. 2

LVSYN

__________

C2l
2WF

lK

CISl
0.011' R20
UF V' 2. lK

I

OV - - - +40V - - - -

CATHODE
CRZ

3 .7 US

----.'-----li------.-US

+3.5V - - -

I

OSI

~

CR8

lK

20W
I

OV - - - -

UZ PIN 14

I:

_" 10

C21
22 l'
Uf V'

+5V--.,.----i

I

19
,+7V - - - -

R21
2.2K

I
I
I
I
I

L

ov----

UZ PIN S

ri>~_""-"4-=---.-~----.",I'-'I'-IU4

J~I:_~/6>-~~14~jL-

_____P/_0__

~

-1+ R24

VERTICAL

I
I

.8 ItS

~

l2UH
+12V~~~____~____-r____________~______________________JV~~

SWEEP GEN

~r-

~
:.
+-________~~IO>-~~I~l~J-------------+--------------------~
L4

I:

16.6 MS

____________

CR14

ItBiGHTNESS
F BRIGHTNESS
OfF

4 .1

Q>----

R¥1~ g

__________7__________________________

T~

.

~~I:.,~
""I

CZ8
0.01
UF

R49
3.9lK

R47
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CR13

l~7
~ m - I +12V f-L-iV~L=-I0-l-L-iIr!;-l

U2

L5
10
UH

LIVID

II

•
30

30YDC

,..----op-- +5V
R43
CR18
680

R4l
6S0

+5Vf IFILTERED)
Cl6];,'-Cl-7-1""",- fo U3.PIN 14
Zll' 0.011'
UFV'
UFV'

16+J-!
II

~
4

VIDEO
DRIVE

R46
810

CI0
0.01
UF

L'lIll
R14
lit

W

FOCUS

!

M2
1M

INTENSITY

WARNING

r HIGH VOLTAGE

1300V-BOOY)

Rll1'16

0

I
I

J

(O-500VI

Il)

I

(I

I

l

(6)

r-~~-+----+----+--~---'-----4~~~~~~~4/>-H~~----------~

+.

R15

R17
lOOK

C12 ..
0.01
Uf

~

C13
0.01
Uf

~

CI4
0.01
UF

L-__________~2~.~51t~__~--__~--~~~--~--~

_______ 7_ _

P/O III

1

4/27/81

Figure 7-2.
Display Driver Schematic

MANUAL BACKDATING DSP 7-5/(7-6 blank)

MANUAL BACKDATING - Model 64100A
SECTION IV
PERFORMANCE TESTS

4-1.

INTRODUCTION.

4-2. If the mainframe has failed in a display or RAM test, proceed to use this
section.
This section on Performance Verification applies directly to the
64100-66519 Display Controller board. If there is some doubt as to the failure
mode, return to section IV of the Mainframe chapter.
4-3.

RAM TESTS.

4- 4.

POWER UP RAM TEST.

Purpose:
The RAM test verifies the ability to read and write from
all RAM located on the Display Control board. Note that
this test occurs only on power up. Another RAM test occurs
during PV and has a different error message. Use SA table E
to isolate a RAM failure.
Area Tested:
All RAMs including refresh ability,
the
multiplexed
memory
Address/Data Bus
from the CPU,
motherboard
connections between CPU and Display Controller board, the
demultiplexed Address/Data bus to/from RAM, and the timing
and control circuitry.
Operation:
a. This is a
during PV.

different

test than the one performed

b. The RAM test takes approximately 7
c. All RAM locations are
operation.

seconds.

toggled to insure READ/WRITE

d. Refresh ability is verified.
e. The operation of the routine is as follows:
1. Load RAM with a count, starting with zero.
2. Read RAM and compare with count.
3. Check for an error. If error occurs go to error
sequence.

MANUAL BACKDATING

DSP 7-7

MANUAL BACKDATING - Model 64100A

4.

If there is no previous error, wait one second.

5. Read RAM and compare with count.
6. Check for an error.

If error

occurs

go to error

sequence.

7. If there is no previous error load

RAM with complement

of count, starting at zero.

8. Read RAM and compare with the complement of the count.
9. Check for an error.

If error

occurs

go to error

sequence.

10. If there is no previous error, wait one second.
11. Read RAM and compare with count.
12. Check for
sequence.

an

error.

If

error occurs go to error

f. If there are aren't any errors in either RAM error mask
then the system will beep twice. But, if an error exists
then following error sequence occurs:
1. Reset the delta timer to prevent auto restart.
2. Set the SA latch.

3. Write to and read from all of RAM.

4. Provide stimulus to CRT controller.
5. Output RAM error display header information (including
refresh error message if refresh error flag set).

6. Reset SA latch.
7. Output individual failing unit

number

for

lower 16K

RAM.

8. Output individual failing

unit

number for upper 16K

RAM.

g. When a failure occurs the routine attempts to output
an error message as follows:

SELF-TEST FAILURE
RAM TEST:

FAILING UNIT NUMBERS (S)
XY

MANUAL BACKDATING DSP 7-8

blinking

MANUAL BACKDATING - Model 64100A

"XY" corresponds to the UII of the failing RAM.
Depending on which RAM is failing, the display
could be affected. Evidence of this is a random
pattern on the CRT or incorrect spelling of
messages For this reason the accuracy of a RAM
test failure is always suspect.
Because the
RAMs are 1 bit wide, 16 of the 32 RAMs are used
to store display information.
U23-U30 and U38u45 on the display controller board are used for
display memory.
Thus, if any of these 16 RAMs
is failing, the display will be unintelligible
to various degrees.

~-5.

PV RAM TEST.

Purpose:
The RAM test verifies the ability to read and write from
all RAM located on the display control board and checks for
refresh. Note that this test occurs during PV.
Another RAM
test occurs during PV and has a different error message. Use
SA table E to isolate a RAM failure.
Area Tested:
All RAMs including refresh ability, the multiplexed
memory Address/Data Bus from the CPU,
motherboard
connections between CPU and Display Controller board,
the demultiplexed Address/Data bus to/from RAM, and the
timing and control circuitry.
:Operation:
a. This test takes approximately eight seconds.
b. Data from ROM is written into RAM, and then read back
and compared to the ROM contents.
c. The second step writes walking 1's and O's to each
RAM address and reads it back. The walking1's and O's
are visable on the CRT as a blinking pattern with
characters moving to the bottom of the screen.
d. The RAM test is interpreted as follows:

NOTE

Since the display uses 16 of the 32 RAMs,
a RAM failure may affect the ability to
display the bad RAM number.

MANUAL BACKDATING DSP 7-9

MANUAL BACKDATING - Model 64100A
RAM TEST:

BIT ERROR MASK

UPPER BANK=XXXX

LOWER BANK=XXXX

The XXXX is the hexidecimal representation of the 16 bit error
mask.
Since each RAM is 16K x 1 bit, each RAM IC is one data
bit for the entire 16K address range of the upper or lower bank.
There is a one to one correlation between the data bit set in
the error mask and the failing RAM.
If the error message reads, "UPPER BANK = 0201."
The problem is with U39 and U23.
If the error message reads, "LOWER BANK = 3000."
The problem is with U70 and u69.
4-6.

TROUBLESHOOTING USING SIGNATURE ANALYSIS.

4-7. Signature Analysis (SA) offers a fast and convenient method of isolating
hardware logic failures down to the component level.
The basic concept is to
utilize a known set of start, stop and clock signals that constantly repeat
(loop) with the same timing relationships. When a suspect logic node is probed
with a Signature Analyzer while using the start, stop, and clock signals as
control inputs, the digital readout (signature) displayed on the analyzer can
be compared with the normal signature of that node to determine if the timing
relationships are proper. With the 64100 Mainframe, looping is provided by the
PV software program and the normal signatures for various nodes are listed in
the tables 4-1 thru 4-13.
4-8.

SERVICE TOOLS.

4-9.

SUGGESTED SERVICE TOOLS ARE:
1.
2.

3.
4.
4-10.

HP 5004A or 5005A Signature Analyzer
Digital Voltmeter
Oscilloscope
Standard hand tools for electronic PC board repair.
SA TABLES.

4-11. The basic procedure is to refer to the appropriate table (i.e., the one
that corresponds to the loop that PV was exercising when the failure was noted)
and connect the Signature Analyzer to the Test Points called for in the table.
Next, verify that the Vh signature indicated in the test set-up is proper.
This signature is very important since it verifies that the start, stop and
clock signals are normal.
If this signature is good, proceed with the
signatures listed in the table while referring to the appropriate schematic for
guidance. If an improper signature is noted, check on both sides of the device
to determine if it is causing the problem or if the problem has its origin
further upstream.
MANUAL BACKDATING

DSP 7-10

MANUAL BACKDATING - Model 64100A
4-12. If SA is taken using a 5004A Signature Analyzer, and loop P is good, it
will be necessary to troubleshoot the shift registers u89 and U90 to the video
output signals LIVID and LIVD with an oscilloscope and logic probe.
However,
if a 5005A Signature Analyzer is used, SA can be taken. The reason being, this
circuitry is run by a 25 MHz signal called DOTCLK and the 5004A will not
operate at that speed. If the signatures in loop P are good, and the circuitry
from the shift registers u89 and U90 to the video output check good, then check
the high voltage, the horizontal sync, and the vertical sync on the display
driver board. Waveforms for the sync signals are provided in section VIII.

MANUAL BACKDATING

DSP 7-11

MANUAL BACKDATING - Model 64100A

Table 4-1. SA Loop A
PC Board: Display Controller Board
Test failure or circuit: Power-up RAM Test failure
Procedure:
S/A hookup:
Start = Pos edge CPU Bd. TPIO (S.A. Interval)
Stop = Neg edge CPU Bd. TPIO (S.A. Interval)
Clock = Pos edge CPU Bd. TPI (LSTB)
Vb :::: Cf:l~~/'

Sig

Node

,.

·i·-

::J

U
U

>~

'-ji ..,

r"

;~'.I

(/""i :1

644';;)

U

d

(J ...

,_.

U

~:~
~;;

0 -." \""'.:)
(I "':1. i

':::;OCO
U941·.1

U

u

i•••

:>

~:;

(lCPU

f:1PH';·;)
4:;~:)4

U ~:j 1
U :Ji··..

f.) 9 i j;."
U664

.",

2

~:;

U

*3 :1. ·":i. ).

U

....

U

~::: ~:.::~

i:;,~;:'"

~:J

I."

S

U E:;.:!"··j, :t
U aZ:···:I.4

"X
U i:;4···· ,.J
,_.
~:$·4
".
U
:J
''':}
,
U C;:·4····
U ~:) .if ..- ')
I.J ~:$ 14 .... i :~~~
U 04····:1.4
U 04·-i6
U G4··· :1.8

P~:~9H

U D 0····i4

Sig

Node

U

(:~!:)"" 1

1-

U i;j~:;;· ..·:l. 2
U i;; i:;') ... J. :':~
U D:;j···:t 4
U e~;j····i~3
U <::: ~:) ..- j. 6
,
U D':·;; ... i "?
U D:;j···· :1.8

FOFF

~;)F~iG
;~! ~j ~;~ t3
-lP B ~5
() ;( ':) ,::~
J.I••• \J

P!3UF

"y (') " .. '..

,:J ) ,;) ,.')

PA:i.4
l.jj.

"".,".
I :.i

OLJU?

H':;;I--/;'::
C6FI4
F'4:?H

t=='B~:) ~':>
j. (.:)7;i.

CS64

~:;CH:l.

H46'/

:l.f~9~:!

3f.lHF
pijUr

Table 4-2. SA Loop B
PC Board: Display Controller Board
Test failure or circuit: Power-up RAM failure - Data writes to RAM
Procedure:
S/A hookup:
Start = Pos edge CPU Bd. TPlO (S.A. Interval)
Stop = Neg edge CPU Bd. TPlO (S.A. Interval)
Clock = Neg edge Disp Controller U21-10 (HWRT)
Vb '"' -'lOP')
* = Probe Blinking

Sig

Node

U d4··.. :1.
L.l (; .~~( .... ::~
L.i ~:; ·4 ..- ':5
L.i ~::, ,·;'f ." '?
U ,34··· ')
U UA·"12
U b4··1·4
u ~;:: .~:( ... :i 6
U U4··.i.B

40 i="'/
C;F' P >.'

F'/C;.:::

H'7H!j
O?H;;!.

:i.H:3P

?COC
tJLCi

3'/9t~

MANUAL BACKDATING DSP 7-12

Node

Sig

MANUAL BACKDATING - Model 64100A

Table 4-3. SA Loop C
PC Board: Display Controller Board
Test failure or circuit: Power-up Ram failure
Procedure:
S/A hookup:
Start = Pos edge CPU Bd. TPlO (S.A. Interval)
Stop = Neg edge CPU Bd. TP10 (S.A. Interval)
Clock = Pos edge Disp Controller TP11 (HPRAS)
Vh = A6U4
* = Probe Blinking
Node

5ig

Node

51g

U18-7

0000*

U48-5

VH*

U49-4
U49-7
U49-9

CF7U
4HC3
P1H9

U50-4
U50-7
U50-9
U50-12

H7HF
574F
A41P
F7AF

U79-5
U79-7
U79-9
U79-11
U82-2
U82-4
U82-5
U82-11
U82-12
U82-14

4HC3
PC47
472H
P1H9
H7Hf
7128
574F
A41P
6158
F7AF

U79-2
U79-4

CF7U
1A8C

MANUAL BACKDATING DSP 7-13

MANUAL BACKDATING - Model 64100A

Table 4-4. SA Loop D
PC Board: Display Controller
Test failure or circuit: Power-up RAM failure - Data reads from RAM and column address
Procedure:
S/A hookup:
Start = Pos edge CPU Bd. TPlO (S.A. Interval)
Stop = Neg edge CPU Bd. TPI0 (S.A. Interval)
Clock = Neg edge Disp Controller TP6 (LPCAS)
Vh= A6U4
* = Probe Blinking
Node

Sig

Node

Sig

U18-7

0000*

U48-5

0000*

U49-4
U49-7
U49-9

6173
lCPA*
IF19

U84-3
U84-5
U84-7
U84-9
U84-12
U84-14
U84-16
U84-18

9343
2A93
03FP
9HOU
008C
253C
9316
PCPP

U50-4
U50-7
U50-9
U50-12

UC32
66UP
286P
PA39

A996
2CF3
4UIF
935P

U80-2
UBO-4
U80-5
UBO-7
UBO-ll
UBO-12
UBO-14

UC32
5HF6
66UP
FOOA
IF19
4FFH
PA39

U85-11
U85-12
U85-13
U85-14
U85-15
U85-16
U85-17

UBI-2
UBI-4
UBI-5
UBI-7
UBI-9
U81-11

6173
F787
lCPA
CHIP
CAPH
IF19

MANUAL BACKDATING DSP 7-14

UB5-1B

CPB6
AOHC
PF69
5U76

MANUAL BACKDATING - Model 64100A

Table 4-5. SA Loop E
PC Board: Display Controller
Test failure or circuit: Power-up RAM failure, RAM outputs
Procedure:
S/A hookup:
Start = Pos edge CPU Bd.,TP10 (S.A. Interval)
Stop = Neg edge CPU Bd. TP10 (S.A. Interval)
Clock = Pos edge Disp Controller TP15
Vh = POOO
Sig

Node

Sig

U23-14
U31-3
U85-11

8AAA
8AAA
8AAA

U38-14

AH28

U24-14
U31-5
U85-12

P444
P444
P444

U39-14

C211

U25-14
U31-7
U85-13

9838
9838
9839

U40-14

APH6

U26-14
U31-9
U85-14

4A2H
4A2H
4A2H

U41-14

6252

U27-14
U31-12
U85-15

PU53
PU53
PU53

U42-14

CF46

U28-14
U31-14
U85-16

4013
4013
4013

U43-14

FF7H

U29-14
U31-16
U85-17

5AH3
5AH3
5AH3

U44-14

F8AA

U30-14
U31-18
U85-18

A247
A247
A247

U45-14

CUUU

Node

MANUAL BACKDATING

DSP 7-15

MANUAL BACKDATING - Model 64100A

Table 4-6. SA Loop G
PC Board: Display Controller
Test failure or circuit: Power-up RAM failure
Procedure:
S/A hookup:
Start == Pos edge Disp Controller TP3 (Vert Sync)
Stop == Neg edge Disp Controller TP3 (Vert Sync)
Clock == Pos edge Disp Controller TP7 (HDRAS)
Vh == P5H2
* == Probe Blinking
Node

Sig

Node

Sig

U17-3

CPll

U1B-7

P5H2*

U21-2

5FC1

U64-11
U64-12
U64-13
U64-14
U64-15

A775
BH02
2P42
C963
52A2

U4B-5

P5H2*

5CF3
4U2A

U49-4
U49-7
U49-9

CPll
AAUB
4P5P

U79-4
U79-7
U79-9

U50-4
U50-7
U50-9
U50-11

6H2U
A775
BH02
1734

UB2-4
UB2-7
UB2-9
UB2-12

BBUH
42A7
6BHO
FC90

U62-11
U62-12
U62-13
U62-14
U62-15

P2AO
AAUB
4P5P
6H2U
5UBF

MANUAL BACKDATING

DSP 7-16

ACBF

NOTE: If the signatures of U79 and UB2
are unstable, use NEG clock edge for
these two components.

MANUAL BACKDATING - Model 64100A

Table 4-7.

SA

Loop H

PC Board: Display Controller
Test failure or circuit: Power-up RAM failure
Procedure:
S/A hookup:
Start = Pos edge Disp Controller TP3 (Vert Sync)
Stop = Neg edge Disp Controller TP3 (Vert Sync)
Clock = Neg edge Disp Controller TP13
Vh= P5H2
* = Probe Blinking
Node

5ig

U1-11

P5H2*

U17-5
U17-6

P5H2*
0000*

U1S-7

P5H2*

U47-6

P5H2*

U4S-5

0000*

U49-4
U49-7
U49-9

0000*
0000*
0000*

U50-4
U50-7
U50-9
U50-12

6C86
8P54
U2P6
73P7

Node

51g

U63-11
U63-12
U63-13
U63-14

6CS6
SP54
U2P6
73P7

USO-4
USO-7
USO-9
USO-12

SP54
6CS6
1734
9635

US1-4
US1-7
US1-9

P5H2*
P5H2*
P5H2*

MANUAL BACKDATING DSP 7-17

MANUAL BACKDATING - Model 64100A

Table 4-8. SA Loop I
PC Board: Display Controller
Test failure or circuit: Any test - Arbitrator circuit - No clocks on TP6, TP7, or TP11.
Procedure:
Remove CPU Bd., I/O Bd., and Disp Driver Bd. Move TEST jumper to TEST position.
S/A hookup:
Start = Pos edge TP14
Stop = Pos edge TP14
Clock = Pos edge TP2
Vh=UP73
* = Probe Blinking
Node

Sig

Node

Sig

Ul-3
Ul-8

55H1
UP51

U20-6
U20-8

UP73
H4C1

U2-11
U2-12
U2-14

8135
86F1
ACA2

U22-1
U22-4
U22-13

0000
0000
669P

U5-11

8117

U35-1

0022

U9-13

ACA2

U35-4

2275

10-6
U10-7

UP73*
55H1

U36-8
U36-11

UP73
HF06

U15-3
U15-6
U15-8

7U24
UP73
UP73

U16-6
U16-8

UF74
UF74

U37-3
U37-6
U37-8
U37-11

7U46
UP51
7U46
7U24

U18-7
U18-9

HF06
2275

U48-5
U48-9
U86-11

7U46
7U06
0022

MANUAL BACKDATING DSP 7-18

MANUAL BACKDATING - Model 64100A

Table 4-9. SA Loop P
PC Board: Display Controller
Test failure or circuit: Display pattern
Procedure:
Sf A hookup:
Start = Neg edge Disp Controller TP3 (Vert Sync)
Stop = Pos edge Disp Controller TP3 (Vert Sync)
Clock = Pos edge Disp Controller TP4
Vh=UAl1
* = Probe Blinking

Node

Sig

Node

Sig

UI-6

0000

U5-8

7P31

U59-2
U59-3
U59-8

UAlO
0000*
UFF7

U7-11

UA11*

U59-9

06H6

U9-1

06H6

Ul1-8

FHCF

U60-2
U60-6
U60-10
U60-11

0000*
0000*
0000*
UA11*

U12-9

UA11*

U33-1
U33-2
U33-3
U33-4
U33-5
U33-7
U33-8
U33-23
U33-24
U33-25
U33-26
U33-27
U33-28
U33-29
U33-35
U33-36
U33-37

34FH
5F34
7H30
990C
8F61
049A
UAI0
4UU3
P635
3272
CIA6
0000*
PA40
1051
UA11*
0000*
0000*

U74-9
U74-10
U74-11
U74-13
U74-14
U74-15
U74-16
U74-17

P719
6FUF
7260
82UA
71HU
AH4F
5HFP
0000*

U75-11

24UU

U76-15

7867

U77-5
U77-9-

OHAH
0472

U91-5
U91-9

0000*
24UU

MANUAL BACKDATING

DSP 7-19

MANUAL BACKDATING - Model 64100A

Table 4-10. SA Loop Q
PC Board: Display Controller
Test failure or circuit: Display pattern
Procedure:
S/Ahookup:
Start = Pos edge Disp Controller TP3 (Vert Sync)
Stop = Neg edge Disp Controller TP3 (Vert Sync)
Clock = Pos edge Disp Controller TP13
Vh=P5H2
-» = Probe Blinking
5ig

Node

U9-10

H5AU

U13-1
U13-4
U13-10
U13-13

74P7
6176
4186
75FH

U19-3
U19-6
U19-8

A6FC
PUC9
96AU

U46-2
U46-5
U46-6
U46-9
U46-12
U46-14
U46-15
U46-16

7328
4319
307H
OA6C
9135
6U9U
84AC
A454

U35-13

0000*

U49-6
U49-9
U49-12
U46-14
U46-15
U46-16
U49-6

307H
OA6C
9135
6U9U
84AC
A454
4U2A

Node

MANUAL BACKDATING DSP 1-20

5 19

· MANUAL BACKDATING - Model 64100A

Table 4-11. SA Loop R
PC Board: Display Controller
Test failure or circuit: Display pattern
Procedure:
S/A hookup:
Start = Pos edge Disp Controller TP3 (Vert Sync)
Stop = Neg edge Disp Controller TP3 (Vert Sync)
Clock = Pos edge Disp Controller Ul-ll
Vh = IF8C

Node

Sig

Node

Sig

U23-14

F5UO

U38-14

OHF9

U24-14

F88P

U39-14

IF61

U25-14

260A

U40-14

3734

U26-14

HOH7

U41-14

60PF

U27-14

6536

U42-14

5448

U28-14

2C74

U43-14

06C6

U29-14

C71P

U44-14

U5U9

U30-14

P8PH

U45-14

8H26

U32-3
U32-5
U32-7
U32-12
U32-14
U32-16
U32-18

OHF9
IF61
3734
5448
06C6
U5U9
8H26

MANUAL BACKDATING

DSP 7-21

MANUAL BACKDATING - Model 64100A

Table 4-12. SA Loop S
PC Board: Display Controller Board
Test failure or cir.cuit: Display Pattern
Procedure:
SfA hookup:
Start = Pos edge Disp Controller TP3 (Vert Sync)
Stop = Neg edge Disp Controller TP3 (Vert Sync)
Clock = Pos edge Disp Controller U47-6
Vh = 1F8C
Node

Sig

Comments

U23-14
U24-14
U25-14
U26-14
U27-14
U28-14
U29-14
U30-14

U767
HA7H
175F
355A
9015
210U
U711
2HA7

These signatures are at the RAM
outputs. When looking at latched
data from previous clock, they
show that the refresh addressing
and RAM output is OK and have
nothing to do with U42 signatures.

U46-2
U46-5
U46-6
U46-9
U46-12
U46-15
U46-16
U46-19

P8PH
C71P
2C74
6535
HOH7
260A
F88P
F5UO

These are the same as RAM
output in loop R; RAM output
is verified in loop R.

MANUAL BACKDATING DSP 7-22

MANUAL BACKDATING - Model 64100A

Table 4-13.

SA

Loop T

PC Board: Display Controller Board
Test failure or circuit: Display Pattern
Procedure:
S/A hookup:
Start =Pos edge CPU Bd. TP10 (S.A. Interval)
Stop =Neg edge CPU Bd. TPlO (S.A. Interval)
Clock = Pos edge CPU Bd. TP1 (LSTB)
Vh= AU94
* = Pro be Blinking
Node

Sig

Node

U5-3

1021

U7-3

51P7

U15-11

4472

U78-10
U78-11
U78-12
U78-13
U78-14
U78-15

OUUP
H98H
9UU9
5586
7F46
859U

U21-1O

PP52

U33-21

90A9

U35-1O

UP73

U47-3

4472

U78-1
U78-2
U78-3
U78-4
U78-5
U78-6
U78-7
U78-9

F99P
7942
5CH4
5452
5452
9C8H
6855
51P7

U83-1
U83-2
U83-3
U83-5
U83-6
U83-8
U83-10
U83-11

AA21
UCF6
51P7
AA21
CAOl
PP52
0000*
51P7

Sig

MANUAL BACKDATING DSP 7-23/(7-24 blank)

MANUAL BACKDATING - Model 64100A
Table 7-1. Replaceable Parts List
Reference
Designation
\5
C1,2

C3
C4,5
C6
C7
C8,9
CI0
Cll
C12
C13,-15
C16
C17-22
C23
C24,25
C26,27
C28,30
C31
C32-37
C38
C39,40
C41,42
C43-45
C46
C47-52
C53
C54,55
C56,57
C58
C59
C60-62
C63
C64
C65,66
C67,68
C69
C70
C71-76
CRl-4
Ll
MP1,2
P2,3
P4
Rl-4
R5
R6-9
RI0-15
R16-18
H19
TPl-13
TPGND
Ul
U2
U3,4
U5
U6
U7
U8
U9
UI0
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23-30
U31,32
U33
U34
U35
U36
U37
U38-45
U46
U47
U48
U49,50
U51-58
U59
U60
U61
U62-64
U65-72
U73
U74
U75,76

un

U78
U79-82
U83
U84
U85
U86
U87

c

Qty

Description

Mfr
Code

5
9
2
9
8
9
8
9
8
9
8
9
8
9
8
9
8
9
8
9
8
9
8
9
8
9
8
9
8
9
8
9
8
9
3
9
1
9
9
3
2
7
0
3
3
3
5
3
7
0
0
4
0
1
6
0
4
8
2
0
4
8
6
6
3
1
8
0
9
1
6
2
5
3
5

1
30
1

DISPLAY CONTROLLER BOARD ASSEMBLY
CAPACITOR-FXD .Q1~F +80-20% 100VDC CER
CAPACITOR-FXD 1000Pf +-5% 100VDC CER
CAPACITOR-FXD .D1~F +80-20% 100VDC CER
CAPACITOR-FXD .1~F +80-20% 100VDC CER
CAPACITOR-FXD .Q1~F +80-20% 100VDC CER
CAPACITOR-FXD .1~F +80-20% 100VDC CER
CAPACITOR-FXD .D1~F +80-20% 100VDC CER
CAPACITOR-FXD .1~F +80-20% 100VDC CER
CAPACITOR-FXD .D1~F +80-20% 100VDC CER
CAPACITOR-FXD .1~F +80-20% 100VDC CER
CAPACITOR-FXD .D1~F +80-20% 100VDC CER
CAPACITOR-FXD .1~F +80-20% 100VDC CER
CAPACITOR-FXD .01~F +80-20% 100VDC CER
CAPACITOR-FXD .1~F +80-20% 100VDC CER
CAPACITOR-FXD .01~F +80-20% 100VDC CER
CAPACITOR-FXD .1~F +80-20% 100VDC CER
CAPACITOR-FXD .Q1~F +80-20% 100VDC CER
CAPACITOR-FXD .1~F +80-20% 100VDC CER
CAPACITOR-FXD .01~F +80-20% 100VDC CER
CAPACITOR-FXD .1~F +60-20% 100VDC CER
CAPACITOR-FXD .01~F +80-20% 100VDC CER
CAPACITOR-FXD .1~F +80-20% 100VDC CER
CAPACITOR-FXD .D1~F +80-20% 100VDC CER
CAPACITOR-FXD .1~F +80-20% 100VDC CER
CAPACITOR-FXD .01~F +80-20% .100VDC CER
CAPACITOR-FXD .1~F +80-20% 100VDC CER
CAPACITOR-FXD .D1~F +80-20% 100VDC CER
CAPACITOR-FXD .1~F +80-20% 100VDC CER
CAPACITOR-FXD .D1~F +80-20% 100VDC CER
CAPACITOR-FXD .1~F +60-20% 100VDC CER
CAPACITOR-FXD .Q1~F +80-20% 100VDC CER
CAPACITOR-FXD .1~F +80-20% 100VDC CER
CAPACITOR-FXD .Q1~F +80-20% 100VDC CER
CAPACITOR-FXD 1O~F +-10% 20VDC TA
CAPACITOR-FXD .01~F +80-20% 100VDC CER
CAPACITOR-FXD 6.8~F +-10% 35VDC TA
CAPACITOR-FXD .01~F +80-20% 100VDC CER
DIODE-SM SIG SCHOTTKY
CORE-SHIELDING BEAD
PC EXTRACTOR
TEST JUMPER
NETWORK-CNDCT MODULE DIP; 16 PINS; 0.100
RESISTOR lK 1% .125W F TC~0+-100
RESISTOR 147 1% .125W F TC~0+-100
RESISTOR lK 1% .125W F TC~0+-100
RESISTOR 27 10% .125W CC TC~-2701+540
RESISTOR lK 1% .125W F TC~0+-100
RESISTOR 12010% .25W FC TC~00/+600
TERMINAL TEST POINT PCB
TERMINAL TEST POINT PCB
IC GATE TTL S NAND QUAD 2-INP
IC CNTR TTL S BIN SYNCHRO POS-EDGE-TRIG
IC BFR TTL LS LINE DRVR OCTL
IC GATE TTL LS AND QUAD 2-INP
IC CNTR TTL S BIN SYNCHRO POS-EDGE-TRIG
IC GATE TTL S NAND QUAD 2-INP
IC FF TTL LS D-TYPE POS-EDGE-TRIG
IC GATE TTL S NOR QUAD 2-INP
IC FF TTL S J-K NEG-EDGE-TRIG
GATE TTL S OR QUAD 2-INP
IC FF TTL S D-TYPE POS-EDGE-TRIG
IC GATE TTL LS NOR QUAD 2-INP
IC INV TTL S HEX l-INP
IC GATE TTL LS OR QUAD 2-INP
IC GATE TTL S NAND DUAL 4-INP
IC GATE TTL LS EXCL-OR QUAD 2-INP
IC FF TTL S J-K NEG-EDGE-TRIG
IC GATE TTL LS NAND QUAD 2-INP
IC GATE TTL S NAND DUAL 4-INP
IC INV TTL S HEX 1 INP
IC GATE TTL S NOR QUAD 2-INP
IC NMOS 16348-BIT RAM DYN 200NS 3S
IC DRVR TTL LS LINE DRVR OCTL
IC MICROPROC-ACCESS NMOS 8-BIT

28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
56289
28480
56289
28480
28480
28480
28480
28480
28480
24546
28480
24546
01121
24546
01121
00000
00000
01295
01295
01295
01295
01295
01295
01295
01295
01295
01295
01295
01295
01295
01295
01295
01295
01295
01295
01295
01295
01295
50088
01295
34649

64100-66519
0160-2055
0160-4822
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
150DI06X902082
0160-2055
150D685X9035B2
0160-2055
1901-0535
9170-{}029
5040-6067
1258-{}182
1810-0307
C4-1 /8-TO-l 001-F
0698-3438
C4-1/8-TO-I00I-F
BB2701
C4-1/8-TO-1001-F
CB1211
ORDER BY DESCRIPTION
ORDER BY DESCRIPTION
SN74S00N
SN74S163N
SN74LS240N
SN74LS08N
SN74S163N
SN74S00N
SN74LS74N
SN74S02N
SN74S112N
SN74S32N
SN74S74N
SN74LS02
SN74S04N
SN74LS32N
SN74S20N
SN74LS86N
SN74S112N
SN74LSOON
SN74S20N
SN74S04N
SN74S02N
MK4116N-3'
SN74LS244N
C8275

7
6
3
4
5
7
3
8
0
5
8
3
2
8
5
7
3
5
8
0
9
3
3
4
8
3

1

NETWORK-RES 270HM 16 PIN DIP
IC GATE TTL LS NOR QUAD 2-INP
IC GATE TTL LS OR QUAD 2-INP
IC GATE TTL S NAND QUAD 2-INP
IC NMOS 16384-BIT RAM DYN 200-NS 3-S
IC FF TTL LS D-TYPE POS-EDGE-TRIG PRL-IN
IC GATE TTL LS OR QUAD 2-INP
IC FF TTL S D-TYPE POS-EDGE-TRIG
IC MUXR/DATA-SEL S 2-TO-l-LiNE QUAD
IC NMOS 16384-BIT RAM DYN 200-NS 3-S
IC FF TTL LS D-TYPE POS-EDGE-TRIG
IC FF TTL S D-TYPE POS-EDGE-TRIG COM
IC DRVR TTL S NAND LINE DUAL 4-INP
IC CNTR TTL LS BIN UP/DOWN SYNCHRO
IC NMOS 16384-BIT RAM DYN 200-NS 3-S
OSCI LLATOR 25MHz
IC ROM 2KX8
IC CNTR TTL LS BIN SYNCHRO POS-EDGE-TRIG
IC FF TTL LS D-TYPE POS-EDGE-TRIG
IC GATE TTL S NAND 13-INP
IC MUXR/DATA-SEL TTL LS 2-TO-l-LiNE QUAD
IC GATE TTL LS OR QUAD 2-INP
IC DRVR TTL LS LINE DRVR OCTL
IC MISC TTL LS
IC GATE TTL S NAND QUAD 2-INP
IC FF TTL S D-TYPE POS-EDGE-TRIG COM

28480
01295
01295
01295
50088
01295
01295
01295
01295
50088
01295
01295
01295
01295
50088
28480
28480
01295
01295
01295
01295
01295
01295
01295
01295
01295

1810-0536
SN74LS02N
SN74LS32N
SN74S00N
MK4116N-3'
SN74LS374N
SN74LS32N
SN74S74N
SN74S158N
MK4116N-3.
SN74LS74
SN74S175N
SN74S140N
SN74LS669N
MK4116N-31
0960-0530
1816-1496
SN74LS163AN
SN74LS74
SN74S133N
SN74LS158N
SN74LS32N
SN74LS244N
SN74LS245N
SN74S38N
SN74S175N

HP Part
Number

D

64100-66519
0160-2055
0160-4822
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0180-0374
0160-2055
0180-0116
0160-2055
1901-0535
9170-0029
5040-6067
1258-0182
1810-0307
0757-0280
0698-3438
0757-0280
0698-7028
0757-0280
0684-1211
0360-0535
0360-0535
1820-0681
1820-1453
1820-1917
1820-1201
1820-1453
1820-0681
1820-1112
1820-1322
1820-0629
1820-1449
1820-0693
1820-1144
1820-0683
1820-1208
1820-0688
1820-1211
1820-0629
1820-1197
1820-0688
1820-0683
1820-1322
1818-1396
1820-2024
1820-2191
1810-0536
1820-1144
1820-1208
1820-0681
1818-1396
1820-1997
1820-1208
1820-0693
1820-1015
1818-1396
1820-1112
1820-1191
1820-0697
1820-1435
1818-1396
0960-0530
1816-1496
1820-1432
1820-1112
1820-1130
1820-1428
1820-1208
1820-2024
1820-2075
1820-1451
1820-1191

42

2
1
4
2
2
2
1
11
1
6
1
20
3
2
2
1
3
2
2
1
3
2
2
4
2
1
1

32
3
1

32
1
2
32
2
1
3
32
1
1
2
1
4
1
1

Mfr Part Number

See introduction to this section for ordering information

MANUAL BACKDATING

DSP 7-25

MANUAL BACKDATING - Model 64100A
Table 7-1. Replaceable Parts List (Cont' d)
Reference
Designation
U88
U89,90
U91
XU1,2
XU23-30
XU33
XU34
XU38-45
XU51-58
XU65-72
XU74

c Qty

HP Part
Number

0

1820-0685
1820-1303
1820-0693
1200-0607
1200-0607
1200-0654
1200-0607
1200-0607
1200-0607
1200-0607
1200-0541

8
9
8
0
0
7
0
0
0
0
1

1
2
32
1

1

Description
IC GATE TTL S NAND TPL 3-INP
IC SHF-RGTR TTL S R-S PRL-IN PRL-OUT
IC FF TTL S D-TYPE POS-EDGE-TRIG
SOCKET-IC 16-CONT DIP-SLDR
SOCKET-IC 16-CONT DIP-SLDR
SOCKET-I C 40-CONT DI P-SLDR
SOCKET-IC 16-CONT DIP-SLDR
SOCKET-IC 16-CONT DIP-SLDR
SOCKET-IC 16-CONT DIP-SLDR
SOCKET-IC 16-CONT DIP-SLDR
SOCKET-I C 24 CO NT DI P SLDR

Mfr
Code
01295
01295
01295
"28480
28480
24840
28480
28480
28480
28480
28480

See introduction to this section for ordering information

MANUAL BACKDATING DSP 7-26

Mfr Part Number
SN74S10N
SN74S195N
SN74S74N
1200-0607
1200-0607
1200-0654
1200-0607
1200-0607
1200-0607
1200-0607
1200-0541

MANUAL BACKDATING - Model 64100A

--

--

--

--

DISPLAY CONTROL BOARD
(64100-66519)

VH7

33~

TPll

GHD

______________________________________

,,~: 'G

TP,

BBB'B
BBBBBB6DBBB
BBD : : : : : : ", : : : : : :
BB~ B BDBDBB6B
BBBBBB6BBDB
C6

CB

C9

010

RlO
Rll

R1l

"13

"l<
"15

ClB

030

C3l

CZ'3

C31

C33

043

C45

C47

C44

046

048

034

04'

A 48

U10B
HRAMCLK

B

78

1
1

14

U73
25MHZ
OSC

B

C
K

4C

VHB

R

El

C

48
4C

VH9

B

Jl

T

LRAMCLK

U10A

SYSTEM CLOCK GENERATOR

Cll

011

,

O4l

R'

(7

+5

TP'

TP6

E1

J

J

ONO

TP16

TpZ

5

5

5

DDG: :. G':"G,. G: : G"'; a'9' ,B"" B 9

TP14

n,

~

J1

L5CLKli

C
K
R

4

VHB

PIO P1

I
10
11
3

VH9

DISPLAY CONTROL BOARD (64100-66519)

--

VH7

us

C37

C39

C36

C3B

(40

C50

OSl

054

C51

C53

C55

~ ~
B
~
BB
J'

[4

U33

ICS ON THIS SCHEMATIC
REF. DES.
U6
U7
U10
U11
U14
U61
U73

041

I

R16

TP9

.~-4r-------------------~~~'-~

MFG. PART NO
745163
74500
745112
74532
74504
74S140
0960-0534

CTR DIV 16

PARTS ON THIS SCHEMATIC

_ ___
TP4.9
P_l_ - - - - '
IL

E6

E5

HP PART NO.
1820-1453
lB20-06Bl
lB20-0629
lB20-1449
1B20-0683
1B20-0697
0960-0534

C56

15

NC

14
13
12

NC
NC

10

IC POWER SUPPLY
CONFIGURATIONS

TP4

"17

ONO

R18
C74

C66

C72

C76

ONO

~ U6.10
+5~

+5

11

U7.11.14
US1.73

40

~__________~L~C~HA~R~~
P1

1

:

85

LDOTCLK

L------------------------------------------------{K

40

PIO P1

1

L25MHZ-r7Bl
I
L---------------______________________________________

II

4A

"----- - - ---- Display Controller Component Locator

-

-----. -

6/3/61

- ---- - - ---- - - ---Display Controller Schematic 4~ (Sheet 1 of 4)
MANUAL BACKDATING DSP 7-27

MANUAL BACKDATING - Model 64100A

3 3 L . . . - . . - . . . . , - -_

1P11

eND

1P14

TPI

,,~:

__ _ _ _ _ _

J.

DISPLAY CONTROL BOARD (64100-66519)

GNO

8,~:, G':"8 ,. G: : [j"': a'~' ,8"" 8 Q
TP1&

'G

~ ~

TP·3

TP9

B

TPG

8 8 8'B
888BBBBBBBB
00
BBB : : : : : : '" : : : : :
"
'" EJ,~ B BBBBBBBB U~ 8 '"
B
8 BB BBBBBBBB 8nB 8
~ BB B,,,B,,, B,,,B. ,B",B . ,B , ,B 8 [j BB0
El

JZ N . U19
T
£3
E2

ell

r6

[7

CB

m

<30

e32

eZI]

e31

C33

C9

e34

[lO

ell

<35

e37

C39

[36

OS

[40

[50

C52

C54

C51

[53

C55

C42

R'3

T

~~~

:~!

cu

C45

Col 7

R12

R15

[44

[46

C04a

C.. 9

E4

N

ES

RlG

E6

[56

GND

Rl7

R.8

e14
C66

e12

Bm B ~ Q,B B",O

L - - - - -~
-..,.

P.

0 ~;'B
-

=

[76

8 B B. . B

Display Controller Component Locator
MANUAL BACKDATING

DSP 7-28

GND

85

r----'"

MANUAL BACKDATING - Model 64100A

3 3 1 - - - - -_

_ ______.

DISPLAY CONTROL BOARD (64100-66519)
TP11

eND

GNo

[J [J 8,: , G':"8 .. G:: 8'' ; a'~' ,8". 8Q

TPH
TPZ

TP16

.~: 'G

TP3

TP9

TP6
El

T

JZ

N

B
U19

8 88'B
88BBBBBBBBB
~ B
B8 G : : : : : : '" : : : : :
.,
GGBBGGBG
~
8
"
.
B B~B ~ ~ ~
U
B BB BGBBGBBG B" G B
E3

E2

CI2

0'

C6

(7

ell)

(31

C8

C9

C10

ell

=

=

_

=

=

e33

(36

(38

eso

C5Z

colla

C4Z

T

~~~

:~!

C43

C45

(47

C49

(54

E.tI

N

E5

R16

E6

9B° 0,,,0,,, B,,,B,. D,,,D,,,B . .D 8 [] BB~
R9

RlZ

R15

C4-1

C46

C48

CS1

(53

C55

C56

liND

RU

RI.

=

~

C7<

~

B. . B g8, B B'" ~
~

~

I

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rn

BB B B. B
=

PI

Display Controller Component Locator
MANUAL BACKDATING DSP 7-30

~

.5

..------------

MANUAL BACKDATING - Model 64100A

~SPLAY CONTROL BOARD A5 (64100-66519)

!

5EE NOTE'

16

rp;QU3

P/O PI
In
_

4B

R

IS

LAI-15

VH 1 a

I

LOa

LOI

LOZ

LD3

LD4

LOS

L06

L07

.----- U23

UZ4

U25

UZ6

U27

UZ8

U29

U30

8

1,..

27

..--

IU37C~~~8~~~~~~~~L~U~RA~S~

.----

----L..L/

RMO
RMI

8

I MAO/6
UZI>....:4'-----'H"'A.>.;14'--_r_-=I....
Z-\
11 .:
13
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L08 L09 L010 LOll L012 LO!3 L014 LOIS
27
8
.,
U36 0 }-"-'-'-----I--....:..:'--I
•
LUCAS
•.
~" ~
12 _U37~~~~~-r~r1~~~~~~l~t=~=+==t=======·~:===:j~==~
U38 U39 U40 U41 U42 ·U43 U44 U45
VH10
27
•
LLRAS
r-'-_'--_'--_'--_'--_'--_'--_'----'
3 1 8
U37~
,

3

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5

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RM3
RM4
RM5
M

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5

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18
17
14
13
8
7
:

0
10
10
10
10
10
10

l'

U46

v
V

v
v

v
v
v

J..I2!LO

19
16
15
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LOOI
LOOZ
L003
L004
LO

9
6
5

0

ffENI

~ffEN2

8
U3 7"l

O-LATCH

11

16

+---'--1_L..-'

• .---

LATCHES

16

16KX3Z OYNAMIC RAM

I HAn/"

7

RM8
RM9
RM10
RIll

8

17
15

ff'
ff

11

ff

~32

2 V
Z v
Z v
Z v

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o

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e<
ro
a:
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~

3.J..

Zv
Zv

ff
ff

Z v
Z v
1 v
1 v

ff

l-

1310

e

:E:

P/O. RAM CYCLE GENERATOR

VHI0----"H U20B

'"<
e

TP5
IS
N

P/O P4

I-

Zl'15
VH6

VHIO

I
I 46
46

P/O P4

5

6.I 1

161T

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TI
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I
9

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SR
HI
5 +-I-_-"R"'CA:!!R~Rc!.Y_ _
H2 3CT=lS!-1-12.
G3
G4
C5/ 2. 3 .4+

VHIO..ll.J::,

~r

I

9

~iENI

--.U

20
B
9
UIC./
R U4BBP-~-+------+~-+-~'--L-~

-

.......

-+__________-+_ _ _ _ _-+_-+_ _----,

~

l U2 r

LAl-13 15

7

'

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I nrA.

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7

U20A~~61~---~~o-~~===t==t:=j
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z
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V }---------,r-r~-"4':::,~f_-,
M

1011

'1

gZI~~~~6~-_·~_ _~I~Z-1

~

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16

14

IV

ff

· RM8

UB3./F--8"--T-----~
.....LL~

~UI5:J

RM10
· RMI
· RM1Z
· RMI3
· RM14
· RM15

-

U18

17

1EN2
ff

8

ff

4

ff

~
2
Z
Z
1
1
1

v

V
V

v
v
v
v

3

~

LO~

LD

l4

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8

1 50 [0 J

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11 1

T,i
13

I
I 4A

I

4 N

B

HRAMClK [

w~"~rrpruruIiROnL-

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P/O P4

13

MHZ)

•

TPl

40

__________________________________________________________________________________

-t----t-~

4B

P/O PI

Or"H~O~C~O______~r

N

TP17
ttt

65~L-_ _ _L~W~RrrT_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _I~0~~~R7~_ _ _ _ _---------------------r---~-----------~-----~~~i~ZI

I,

ICS ON THIS SCHEMATIC

REFOE 5 I HP -"MJ -'Ill LI!Ea -"AB' -'Ill
Ul.7.37
18Z0-0681
74500
UZ
18Z0-1453
745163
US
18Z0-1201
74LSOB
U1Z.48
18Z00-01629038
77 4 S73 4Z
U15.36,47.83 182 .
U16, ZO
18Z0-0688
74SZ0
U17
18Z0-1Z11
74LS86
U18
18Z0-06Z9
745112
UZI
18Z0-0683
74504
UZ3-30,38-45 1818-0341
MK4116P
51-58,65-72
U31,3Z,84
18Z0-Z0l4
74LSZ44N
U34
1810-0536
3168170
U35
18Z0-1144
74LSOlN SLT
U46
18l0-1997
74LS374N 5LT
,
U78
18Z0-1130
745133
~
IB20-Z075
74LSZ45
~______-L~1~8~Z~0-~1~4~5~1~7~4~5~3~8____~

I

lDCA'

@-

4B

P/O P4

~;) T
'¢'

PARTS ON THIS SCHEMATIC

I

IPI,Z,4

NOTE
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~

TPZ.5,6.,7,l1,!3,14,15,17

R~M

5'
+-&
U31,3l.46,85

-'"•

j,L

:fr
~
A6

IC POWER SUPPLY CONFIGURATIONS
+5

14
7

U1,5,7,lZ,15-17,
20,ZI,35-37,
48,83,B6

~
+5

. 8

UZ.1B,78

LRAS

-5.Z--!,.
8

Ul3-30,
3B-45,
51"58,
65-72

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15

1

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0

7

I
Z
34
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8
9
11 01
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6

13

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r---iM
-I r-'"U88C r~.8 4 - - - - - - - - - - - - - - - - - - - - - - - - - ( A A
_.~~~~::::::~~
10
U47CJ~.R-B--_a~~E=Z----------~4~
5
FF
5
LORD
BB
VHZ --'-f-t:' 5
5
9
/
E3 N 'I T . . L
3.1.J

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L____~------~4~B~~~~=L=S=TB========4===========================~-----------------------0~C~~~~~~--~~====================================================================~~~

TP14.9-.......--

2

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

MILLISECONDS

VERTICAL SYNC Pi, PIN 56

Figure 8-1.

Horizontal and Vertical Sync Waveforms

DSP 8-11

Service - Model 64100A

LATcH

LSB~

A

~DCNT_

VRTC
FROM
RAM CVCLF r.FN I nco<

LD

CHARACTER
COUNTER
CONTROL

!'

CHARACTER
ADDRESS

COUNTERS

V

14

/'6

=g~~~~~~~~

8

B

ADDRESS
SELECT
MUX

15

v lROW
CULUMN

I

-- -- --

--

--

-------

---

--

MSB~ [>

I
DOTCLK (25 MHz)
RAMCLK (12.5 MHz)
SCLK1 (6.25 MHz)
CCLK (2.78 MHz)
8FT/LO (2.78 MHz)

LMAO-7

----- -- - - - - -

LCPURD

/,.

MEMORY DATABUS

/16

MEMORY ADDRESS BUS

/8

MEMORY CONTROL BUS

'WRT
LAJ5
LSTM

I

LA14
1<<<,

; (64110AI

I

L __

I «Fl. DECODE
LMAPl

I LD1, LD10

----- ----

---~- - -

MEMORY
ENABLE
AND

GENERATOR

,7

~

,3

-

,2

LMSYN

UPPER
LOWER

ADDRESS
ENABLE

---- -

- 1--- --

- - - - --

I

t
, SIGNALS

Figure 8-2.
Display Controller Block Diagram
DSP 8-12

~

-,

I

~
-v

I

1/

r

DISPLAY

DATA

DATA
OUT

VD
LATCH

I

[>

r-V

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DIN

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7

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8

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2

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r
Z

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I

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l

1

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I

f-

LDISP CYCLE

, < 16 memory locations of RAM are
addressed over the Memory Address Bus. The lower 32K x 16 memory
locations of RAM are addressed by the Memory Address Bus and
Memory Mapped I/O

1

1/

I

115

-l1

DADDRESS

I

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LORD

•

LATCH

LWLBVTE. LWUBVTE

-------

Q

r

~
I

,~

~

~B

16

64K x 16
DYNAMIC
RAM

D

A

l/'

LADDCLK

V

SEE NOTE

~.

,. \

~

.
TTT
30

\
\

Service - Model 64100A
ICs ON THIS SCHEMATIC

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MFR PART NO.

U1
U3,4
U5
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U11
U12,78
U13
U14
U17
U19
U33
U53,63
U54,74
u60
U61,62
U72
U75
U76,77

1820-0681
1820-1917
1820-1201
1820-1322
1820-1449
1820-0693
1820-1144
1820-0683
1820-1211
1820-1197
1820-2191
1820-1112
1820-1191
1816-1496
1820-1432
1820-1451
1820-0685
1820-1303

74s00N
74LS240N
74LS08N
74s02N
74s32N
74S74N
74LS02N
74so4N
74LS86N
74LSOON
C8275
74LS74N
74s175N
IC ROM
74LS163N
74s38N
74s10N
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.,-.---.-~-~-~-~-~-------~---~---~-~---------~-~-,--------~---------------~-~-~-~-~

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IC POWER CONFIGURATION

1

1

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""

I

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351;9;

U3a

~~

+5

'ii

U!i-'l

1

PARTS ON THIS SCHEMATIC

8

1
1

U54,76,77

GND -----1

1 _ _ _ _ _-

Figure 8-4.
Display Controller Schematic (Sheet 4 of 4)
DSP 8-19/(8-20 blank)

Service - Model 64100A

LIVID
I'

LVID

VIDEO
DRIVER

J

CRT

V

~

~

LVSYN
,/

VERT
SWEEP
GEN

(VVY"I

>

~

N

.....

LHSYN
/

I

2
I

I

,

HOE

VERT
SWEEP
GfN

HIGH
VOLTAGE

1 , 2

MOTHER BOARD SIGNALS

30

Figure

I

8-5. Display Driver Block Diagram

DSP 8-21

Service - Model 64100A
INTENS

FOCUS

B

RI2
RI3

HGAIN

RI9

8

RI6
RIO
RI4

(II

oJ

RII

i

JI

..,.

L3

CI3

CI4
C9

OSI

CI2

C\I

•

GNO

R38

L4

(J)

TPI

C\I
U

•

0

R39

CII

V
GAIN I:=::J R26
R36
R37
R27

I/)

C\I
()

CIO
RI7
VRI
RI8
R8
CR6

R48

Q4c::::::J
It)

It:

u

c::::::JQ5

CRII
CRIO
CR9
R35
R29
CI8
R28
R!O
eR8
VR4

II)
()

,.,
It:

()

CRI2
R31

EJ
C20
C23
R32
R33
R34

CI9
CI7

iO
()

C21
TP2

•

QQ7

R49
QQ8

Q6Q TP4 CRI4

C28
VR3

"POS

oRI

B
C27

CRI3
VR2
L5
R44
R45
R46 CRIG
R42 ~Rli
R43
CRI7
R47

8

0)
-.;~.

GNO

•

TP3

•

C26

VR5
C29

TP5

•

R25
R4
R5
R22

R24

B

R20
R21
R23

CIS

RSO
R41
R40

CR2
CR19

CR7
CIG

}~B

DISPLAY DRIVER 64100-66527
1 - - - - - - - - - - - - - - 29
PI

Figure 8-6.
DSP 8-22

A7 Display Driver Component Locator

Service - Model 64100A

I

64100-66531

I

VIDEO
DRIVE

R46
620

1~1

HP PART NO.
2090-0042
64100"61603

30VOC
L5
10
UH

+5V

I

R42
680

5 ~_,..-+"'5'-'Y--.-_r---.._--__.---.._-+5.Yf (FI LTEREO I
6
C26.i+ C27 +
fo U3,PIN 14
Z21' 0.011'
7
8
R40 R41
UF'V
UF'V
1:
120 IZO

IC POWER SUPPLY
CONfIGURATIONS

R43
6BO

CR16

R49
3.9ZK

CZ6
0.01
UF

CRll

II~·~L~I~V~IO~~-+_--~----_.---~

-:II

U
+5V-~-8 ~
U11

~,-_U_'3_,4_

+5 V

eR6 R34

+12V

R44
620
R45
620

PARTS INCLUDED ON
THIS SCHEKATIC
REF. DES.
CRT
Io/lleRT CABLEI

--~

I DISPLAY DRIVER

ICS ON THIS SCHEKATIC
REF. DES. HP PART NO. MFG. PART NO.
Ul
1620-1437
74L5Zl1
1626-0120
U2
LM3900
1620-1451
U3
74536
U4
1620-0471
7406

16

I:
I

R50
IK

CRI9

CR2

29
30

I
I

TP2

CR15

Z7 m-I +12Y
28 1

~
~U2

R4B
100

12L~~I~~L~V~I~0_~-~------~--~~~__~}~---+--4---~~~
15,
CR14

C29

L4

.01

22UH

1%1:
. GNO
TP
2
3
4

I:
i-'>-I~-- 16.6 MS -

o ",--o

__
D!

!

I
I
I
I

.B MS

LVSYN +3.5Y - - - ·lJr--------U;.--------~

U2 PIN 5

VERTICAL
SWEEP GEN

I
I
.1

LYID
L
H
H

CRB
CZZ
2WF

4

Y
L
H
L
H

FUNCTION
NORMAL
BRIGHTNESS
HALF BRIGHTNESS
OFF

R21
2.2K
+5V

L

AU

+

2_ 21-:"

RZS
2Z0

C16

CIS
0.011' RZO
UF'V 2. 2K

t

4700

,'

OY----

U2 PIN 14

(]

+23Y

----Jl

+12Y - - - -

'-._ _ _ _ _ _ _

C16
lUF

n
~_.J. -----------.11

+

RZ6
200K

RZ7

-"3.SV

d

HSYN

0-

~--'

OV ----

[

~~~;
_

41 US j 3 . 7 U S

I

WARNING

o

20-BOIJH

~

6.19

-& ",\

12

+12V-~~-~-------~~-+_~,

GAIN

-- _

UiOR19
220

CR6

OV ----

TP5

RI3
1M
6

OY---+Z50V - - - .

CATHODE
CRZ

6

I

I

R6
2.2K

I

I I

I

HORIZONTAL

r-H--'--''--'---+____+--++___Y_OK_E_ _ _ __

I

+12KY

WARNING
HIGH VOLTAGE

P/O JI
-40V

151

!

~

RJ.Z.
1M

INTENSITY

Cl0
0.01
UF

RI6
1M
R14
1M

fOCUS
RI5

2. 5_M_ _

----

:I

J--- -- ----! ;:
AlB
lOOK

L _______________________,______
ov ----

~~D

A9
2.5M

CR5

+20V ----

C9
1 75UF

- - - - --'1( _

+5V - - _ .

TP3

I

•

L2

(61

7

+4DV ----

0

LINEARITY

YR4

VERTICAL
YOKE

121

3.3

U

I

J2

R39

WIDTH
+IZV

2
4 ~+---..
3 """-f--.../
I
6

7,_'-_ _ _ _____

[25
33 uF

HIGH VOL TAGE CIRCUIT _ _ _ _ - . _

0J
C4 +
470UF;

R33
lK

R30
B2.SK

+40V

'-----<

L--------~--~~~t--~~----------------~~
I
+

3
2

H==:::;-----J

TPI

R3B
330

R37
4Z.ZK

R3Z
BZ.SK

lOOK

TPl

I"

R36
42.2K

R29
10K

R2B
lOOK

•

+

R31
162K

L.

GAIN

0

C24
2200UF

33uF

.

UK

R34
100

CR'

CI9

+7Y ----

MECHANICAL
CONNECTION
TO CRT SHI~LD

R~5

R17
lOOK

CI2
0.01
UF

(300V-BOOY J

(21

(O-SOOVI

(61

I

P/O 10/1

I

I
I

=--_-d--- __ -.J

1
Figure 8-7.
Display Driver Schematic
DSP 8-23/(8-24 blank)

SERVICE MANUAL
MODEL 64100A
INPUT OUTPUT/FUNCTIONS

~

COPYRIGHT HEWLETT-PACKARD COMPANY 1981, 1982, 1983
LOGIC SYSTEMS DIVISION
COLORADO SPRINGS, COLORADO, U.S.A.

All Rights Reserved

Manual Part No.: Part of Mainframe Manual
Microfiche Part No.: See Mainframe Manual

Model 64100A - Table of Contents

TABLE OF CONTENTS
Page

Section
I

GENERAL INFORMATION ............................................. 1-1
1-1. Introduction ............................................... 1-1
1-4. Purpose .................................................... 1-1

II

INSTALLATION and REMOVAL ........................................ 2-1
2-1.
2-2.
2-3.
2-4.
2-6.

III

Removing the I/O PC Board .................................. 2-1
Removing the Rear-Panel PC Board ...... '" .................. 2-1
Removing the Keyboard PC Board ....................... , ..... 2-1
Installing the I/O PC Board ................................ 2-2
Installing the Rear-Panel and Keyboard PC Board ............ 2-2

OPERATION ....................................................... 3-1
3-1. Introduction ............................................... 3-1

IV

v

PERFORMANCE VERIFICATION ........................................ 4-1
4-1.
4-3.
4-4.
4-5.
4-6.

PV Theory .................................................. 4-1
I/O Write Test Procedure ................................... 4-1
I/O Read Test Procedure .................................... 4-2
Time Interrupt Test Procedure .............................. 4-3
Keyboard Test Procedure .................................... 4-4

4-7.
4-8.
4-9.
4-10.
4-13.

System Bus Test Procedure .................................. 4-6
RS-232 Test Procedure ...................................... 4-6
Troubleshooting Using Signature Analysis ................... 4-7
Service Tools .............................................. 4-7
SA Tables .................................................. 4-8

ADJUSTMENTS ..................................................... 5-1
5-1. General .................................................... 5-1

VI

REPLACEABLE PARTS ............................................... 6-1
6-1.
6-3.
6-5.
6-8.
6-11.

VII

Introduction ............................................... 6-1
Abbreviations .............................................. 6-1
Ordering Information ....................................... 6-1
Direct Mail Ordering System ................................ 6-3
Replaceable Parts List ..................................... 6-3

MANUAL BACKDATING ............................................... 7-1
7-1. Introduction ............................................... 7-1

I/O iii

Model 64100A - Table of Contents
TABLE OF CONTENTS
Section
VIII

(Cont'd)
Page

SERVICE ......................................................... 8-1
8-1.
8-3.
8-6.
8-19.
8-24.

Introduction ............................................... 8-1
Block Diagram Descriptions ................................. 8-1
I/O Control Section ........................................ 8-1
HP-IB Control Section ...................................... 8-4
RS-232 Control Section ..................................... 8-5

8-32.
8-38.
8-43.
8-44.
8-71.
8-84.
8-92.

Keyboard Control Section ................................... 8-8
Schematic Description ..................................... 8-12
I/O Control ............................................... 8-12
Beeper Decoder u45A ....................................... 8-12
HP-IB Control ............................................. 8-18
RS-232 Control ............................................ 8-22
Signal Mnemonics .......................................... 8-29
LIST OF TABLES

Table Number

Page

I

1-1. Power Supply Current Loading ................................ 1-1

III

3-1. I/O PCB Switch Functions .................................... 3-1
3-2. Rear-Panel Switch Functions ................................. 3-2

IV

4-1.
4-2.
4-3.
4-4.
4-5.

I/O
I/O
I/O
I/O
I/O

Write Signature Analysis ................................ 4-9
Write Signature Analys is ............................... 4-11
Read Signature Analysis ................................ 4-12
Bus Signature Analysis ................................. 4-13
RS-232 Signature Analysis .............................. 4-14

4-6. I/O Keyboard Signature Analysis ............................ 4-15
VI

6-1. List of Manufacturers' Codes ................................ 6-2
6-2. Reference Designators and Abbreviations ..................... 6-4
6-3. Replaceable Parts List ...................................... 6-5

VIII

8-1.
8-2.
8-3.
8-4.
8-5.

I/O Internal Addresses ...................................... 8-2
Beeper Decoder u45A Truth Table ............................ 8-13
Card ID Decoder u45B Truth Table ........................... 8-14
Decoder Enable Logic Truth Table ........................... 8-14
Peripheral Address Decoder U17/U18 Truth Table ............. 8-15

8-6.
8-7.
8-8.
8-9.

Interrupt Buffer Enable Truth Table ........................ 8-15
Interrupt ID Codes ......................................... 8-17
Slot Select Decoder U53 Enable Truth Table ................. 8-18
PHI Control Logic Truth Table .............................. 8-19

I/o iv

Model 64100A - Table of Contents
LIST OF TABLES

(Cont'd)

Section

Table Number

Page

VIII

8-10. RS-232 Interface Connector Pin Functions ................ 8-23
8-11. RS-232C Voltage Levels .................................. 8-29
8-12. I/O Signal Mnemonics ...•................................ 8-29
LIST OF ILLUSTRATIONS

Section

Figure Number

Page

III

3-1. I/O PCB Switch Locations and Functions .................... 3-3
3-2. Rear-Panel Switch Locations and Functions ..........•...... 3-4

IV

4-1. Keyboard Test Sequence .................................... 4-5

VIII

8-1.
8-2.
8-3.
8-4.
8-5.

I/O PCB Switch Locations and Functions .................... 8-9
Rear-Panel Switch Locations and Functions ..•..•.......... 8-10
I/O Block Diagram ........................................ 8-11
HP-IB Signal Lines ................•.......•.............. 8-20
HP-IB Handshake Timing ...•............................... 8-21

8-6.
8--7.
8-8.
8-9.
8-10.

RS-232C and Current Loop Schematic ....................... 8-22
Terminal as a Talker ..................................... 8-24
Terminal as a Listener ...................•....•.......... 8-25
Modem as a Talker ........................................ 8-26
Modem as a Listener ...................................... 8-27

8-11.
8-12.
8-13.
8-14.
8-14.

RS-232 Data Format ..............................•........ 8-28
Typical Sequence of Events for RS-232C Data Transfer ..... 8-28
I/O Component Locator .................................... 8-40
I/O Schematic 1 .......................................... 8-41
I/O Schematic 2 ....................................•..... 8-43

8-14.
8-14.
8-14.
8-15.

I/O Schematic 3 .......................................... 8-45
I/O Schematic 4 ...............................•.......... 8-47
I/O Schematic 5 .......................................... 8-49
Rear-Panel Component Locator ............................. 8-46

I/O v

Model 64100A - General Information
SECTION I
GENERAL INFORMATION
1-1.

INTRODUCTION.

1-2. This Chapter contains the physical description, troubleshooting and
theory-of-operation for the Input/Output, Rear-panel, and the Keyboard PC
boards.
1-3. The I/O, Rear-panel, and Keyboard PC boards comprise part of the set of
mandatory circuit boards that are required for operation of the basic 64000
Logic Development Station. This means that all of these boards, (plus the CPU,
Display Control and Display Driver PCB's), must be installed in every 64100A
Mainframe before operation is possible.
1-4.

PURPOSE;

1-5. The I/O, Rear-panel, and Keyboard PC boards contain circuits required by
the Mainframe CPU board to:
(1) process data and instructions sent to and
received from remote peripheral equipment (e.g., disc drives, printers, modems,
etc.)
via various buses, (2) process interrupts from remote peripherals and
internal (Mainframe) circuits, (3) decode card select signals, (4) decode
Keyboard status signals, and (5) generate a beeper tone when certain events
occur. In addition, the I/O and Rear-panel boards contain many of the switches
that allow the operator to select the system mode of operation (see Section
III) .

1-6. Table 1-1 lists the power supply current loads for the I/O,
and Keyboard PC boards.

Rear

Panel

Table 1-1. Power Supply Current Loading
PC BOARD
I/O
Rear panel
Keyboard

+12V Supply
0.164 Amps

+5V Supply

-5V & -3V Supply

0.708 Amps
0.714 "
0.239

I/O 1-1/(1-2 blank)

Model 64100A - Installation and Removal
SECTION II
INSTALLATION AND REMOVAL

2-1.

2-2.

REMOVING THE I/O PC BOARD.
a.

Shut off system power.

b.

Remove the 50-pin
panel ribbon cable.

c.

Pull up on the two extractor levers
be lifted from the Motherboard slot.

I/O

ribbon cable

and the 50-pin Rearuntil

the

board

REMOVING THE REAR-PANEL PC BOARD.
a. Remove the 50-pin ribbon
Panel PCB.

cable from the I/O PCB to the Rear-

b. Remove two studs holding System Bus
Panel).

connector

(J1 on

Rear-

c. Remove two studs holding each RS232C connector (J2 and J4
Rear-Panel).
d. Remove four screws holding Rear-Panel PCB to
frame.
2-3.

can

rear

of

on

Main-

REMOVING THE KEYBOARD PC BOARD.
a. Tilt front panel bezel forward and disconnect keyboard ribbon
cable from Motherboard connector J15.
b. Remove PROM Programmer Module and remove two screws
Keyboard Assembly to Mainframe.
c. Carefully stand mainframe on the
bottom cover.
d. Remove the
Mainframe.

six

screws

holding

Rear-panel
the

and

Keyboard

securing
remove the

PCB to

the

I/O 2-1

Model 64100A - Installation and Removal
2-4. INSTALLING THE I/O PC BOARD.
2-5. To install the I/O PC board, perform the removal steps in reverse order
being careful that the board is properly aligned with the Motherboard connector
before seating the board.
Be sure that the component-side of the PC board is
facing the front of the Mainframe.

CAUTION
The I/O PC board is ALWAYS installed
in the forward-most slot in the Mainframe
card cage (identified as the "I/O" slot on
the slot identification label).

2-6. INSTALLING REAR-PANEL AND KEYBOARD PCB'S.
2-7. To re-install the Rear-Panel and Keyboard PCB's, perform the removal steps
in reverse order.

I/O 2-2

Model 64100A - Operation
SECTION III
OPERATION
3-1.

INTRODUCTION.

3-2. There are no special handling instructions for these PC boards. The only
operating instructions concern defining the function of the various mode
control switches on the I/O and Rear-panel PC boards.
The functions of these
switches are defined for the I/O and Rear-panel PC boards in tables 3-1 and
3-2 respectively. Refer to Section VIII of this manual for more information
about their use.

Table 3-1. I/O PCB Switch Functions
SWITCH

NAME

FUNCTION

Sl

20 MA/60 MA

Selects appropriate current level
of 20 mA or 60 mA for peripherals
such as a teletype (TTY).

S2

INT/EXT Clock

Selects either internal or external
clock
source
for
asynchronous
operations. The internal clock frequency is determined by the baud
rate dip switch S5 on the I/O PCB.

S3

CUR LOOP/RS-232

Selects current loop or
RS-232
operation modes.
In the current
loop operation, a logic 1 is 20 mAl
60 mA while a logic 0 is 0 mAo In
the RS-232 operation, a logic 1 is
any voltage
between -3 and -25
volts while a logic 0 is any voltage between +3 and +25 volts.

s4

RS-232 MODE

Controls the parameters of the
RS-232 mode by the position of
the 8 bit dip switch s4.
Bits 1 and bit 2 set the number
of stop bits.
Bit 3 sets the Even/Odd Parity
line.
Bit 4 sets the
Parity Enable.
Bits 5 and 6 set the Character
Length.

I/O 3-1

Model 64100A - Operation
s4

(cont'd)

Bit 7 sets the baud rate factor (Xl
or X16) which will configure the
USART chip via the CPU to recieve
transmission at a faster rate. This
will give the CPU more time to
perform other functions (see the
64100A operating manual).
Bit 8 sets the terminal as either a
Modem or Terminal.

BAUD RATE

S5

Is a 5 bit dip switch that controls
the Baud rate and Duplex mode.
Bit 1 sets the terminal in the
Full or Half Duplex. The other
four switches set the Baud rate
from 50 to 19200 in 16 steps.

NOTE: Refer to figure 3-1 for more information on the location and
function of the I/O PCB dip switches Sl - S5.

Table 3-2. Rear-Panel Switch Functions
SWITCH

NAME

FUNCTION

S2 Be S3

SYSTEM BUS

S2 and S3 are both 8 bit dip
switches which control the mainframe as a controller or as a
non-controller (see the 64100A
operating manual for description
of how to set S2 and S3 ).

Sl

CONTROL SOURCE

Sl is a 7 bit dip switch which
controls the boot-up source and
the mainframe's address.
Bits 1 - 5 select the mainframe
addresses. There are 32 addresses available, but only up to 6
mainframes are allowed on the
the system bus. Bits 6 and 7 are
Boot-up source addresses (System
Bus, Local Mass Storage, etc.).

NOTE: Refer to figure 3-2 for more information on the locations
and functions of Rear-panel dip switches Sl - S3.

I/O 3-2

Model 64100A - Operation

20(
MA

)

,,,
,,
,,
,,

,
,,,

'--I

60
MA

r-

RS-232
CUR LOOP
DRV SEL
51

,,
,,
,

LJ -

EXT (

) INT

,,' ,,
,,
~~

TXCLK

tJ
,, ,,
,, ,,
G
L..J

RXCLK

RS-232
CLK SOURCE
SEL
52

'__I

CUR
LOOP

,,r.,,

IU

RS-232

S4 BITS
6
5

RS-232
CURRENT LOOP
SELECT
53

NO. OF 5TOP BIT5
TRUTH TABLE
S4 BITS
STOP
BITS
1
2

CHAR LENGTH
TRUTH TABLE

0
0
1
1

0
1
0
1

CHAR
BITS

0
0
1
1

5
6
7
8
1(

NO. STOP BITS

INVALID
1
1.5
2

)0

{== 00

BAUD RATE
EVEN/ODD PARITY - - E
TRUTH TABLE FOR 55
PARITY ENABLE ~
55545352 RATE
CHAR LENGTH
0 0 o 0
50
0 0 o 1
75
0 0 1 0
BAUD RATE FACTOR-X16
110
0 0 1 1
134.5
MODEM
1(
~o
0 1 o 0
150
0 1 o 1
300
0 1 1 0
600
0 1 I HALF DUPLEX
FULL DUPLEX 0 1 1 1
1200
1 0 o 0
1800
0 2 I
1 0 o 1 2000
0 3 I
1 0 1 0
2400
BAun{
1 0 1 1 3600
RATE
0 4 I
1 1 o 0
4800
0 5 I
1 1 o 1 7200
1 1 1 0
9600
1 1 1 1 9200
RS-232
BAUD RATE
AND
RTS SEL
55

0
1
0
1

0
0
0
0
0
0

1
2
3
4
5
6
7
8

I
I
I
I
I
I
I
I

0
0

RS-232
MODE
SEL
84

X1
TERMINAL

Figure 3-1. I/O PCB Switch Locations and Functions

I/O 3-3

Model 64100A - Operation

S2

S1

COIlfTROl SOURCE

CJ~tD41~~~~;;;;"+-- BOOT-UP SOURCE
J1 HP-IB ---';"""""';;;;;;:;;0:;;:::

" ._ _ _ _ _ RS 232-C _ _ _ __ _

TO MODEM

i
SEleCTOR

','

. . ... ',"."'.'
,. "....... .... .,..
<;~.
','J
"
\

---,

.

~

[

"ROM
SRC

H'flrTO Ttv!
fltl<

I SRC

ftHI

I

'''S'D~

0" *0 SOMD

I

TO TtRMINAL

J2

J4

J3

MAINFRAME
ADDRESSES

BOOT-UP SOURCE
ADDRESSES
MSB

a
a

LSB CONTROL
a SYS BUS (D ISC)
LOCAL MASS STORAGE TALK ONLY
a LOCAL MASS STORAGE ADDRESSABLE
PERFORMANCE VERIFICATION

NOT
USED

MSB

00

a

a

00

a

a

LSB

ADDRESS

a

a
NOT VALID

--

00
00
00
00
00
00

--

- - --

a
a

-----------------a

2

1

1

a
a

a

3
4
5
6
7

1

a

VALID
MAINFRAME
ADDRESSES

Figure 3-2. Rear-Panel Switch Locations and Functions

I/O 3-4

Model 64100A - Performance Verification

SECTION IV
PERFORMANCE VERIFICATION
4-1.

PV THEORY.

4-2. The following paragraphs briefly describe the I/O circuits that are being
exercised by the various I/O PV tests.
NOTE

Refer to section IV of the Mainframe
tab for an explanation of PV initiation.
4-3. I/O WRITE TEST PROCEDURE.
Purpose:
This test provides
audible
feedback that the
test is
executing by beeping, and provides the following SA stimulus.
The I/O WRITE TEST increments the PHI chip register addresses,
accessess the interrupt masks, cycles the slot select lines,
and stimulates the four Rear-panel BNe connectors. Use SA
loops A and B for trouble isolation.
Area Tested:
This test is not of the pass/fail type.
It provides stimulus
signature analysis for the following cicuitry:
Option slot
select lines on the Motherboard, all connections from option
slots to the Rear-panel BNC connectors, the beeper circuitry,
PHI register address latch, all LMAP lines, and the interrupt
mask circuitry.
Operation:
a. This test will not display a failure. The
of the test is for signature analysis (SA).
b. The only noticeable
audible beeper.

failure

will

be

the

main purpose
loss

of

the

I/O 4-1

Model 64100A - Performance Verification
4-4. I/O READ TEST PROCEDURE.
Purpose:
This test checks the Rear-panel switches, the hardware
configuration jumpers, the RS-232 switch settings, and the
master controller and non controller configuration and displays the information on the screen.
If the information
differs from the switch settings then use SA loop C for
trouble isolation.
Area Tested:
Rear panel dipswitches, the cable to the Rear-panel, I/O
circuitry, and the RS-232 dipswitches.
Operation:
a. Upon
initiation of the I/O READ TEST,
displays the following in inverse video:
I/O READ TEST:

is the HPIB
switches.

BOOT=XX

is the boot
follows:

source

Bit 1

Bit 0

0
0
1
1

1
0
1

address

(O-lF)
set

by

as

set by the Rear-panel

the Rear-panel switches as

Control Source
System Bus
Local Mass Storage Talk only
Local Mass Storage Addressable
Performance Verification

0

X=l for CONTROLLER (MASTER)
X=O for NON-CONTROLLER (SLAVE)

RS232=XXXXXXXX Read from s4 on the I/O board.
Bit 76543210

I/O 4-2

PV menu

ADDR=XX BOOT=XX M=X RS-232=XXXXXXXX HC=XX

ADDR=XX

M=X

the

Bit 0

Term/Modem

0= Terminal

Bit 1

Baud rate

X1/X16

Bit 2
Bit 3

Word Length
Word Length

Bit 3
0
0
1
1

1= Modem

Bit 2
0
1
0
1

Word Length

5

6
7
8

Bit 4

Parity Enable

0= Parity Disabled
1= Parity Enabled

Bit 5

Parity

0= Odd Parity
1= Even Parity

Odd/Even

Model 64100A - Performance Verification
Bit 6
Bit 7

Number of stop bits
Number of stop bits
Bit 7
0
0
1
1

HC=XX

Bit 6
0
1
0
1

# of Stop Bits
INVALID
1
1.5
2

The hexidecimal representation of the six hardware jumpers.
HC is not used for this test.
b. Use SA loop C for trouble isolation.

4-5.

TIME INTERRUPT TEST PROCEDURE.

Purpose:
The TIME INTERRUPT TEST checks the operation of the 50 to
60 Hz line sync to the CPU via the delta time interrupt
circuitry.
Area Tested:
The LINE SYNC a 50 to 60 Hz signal from the power supply, the
delta time
interrupt circuitry on the I/O board, and
interrupts to the CPU.
Operation:
a. Upon initiation, the PV test counts and displays line sync
interrupts to the CPU. The display will show the amount
tests that have passed or failed.
NOTE

Since LINE SYNC is asynchronous with the CPU
timing, SA cannot be used for troubleshooting.
The circuit functions
must be verified by
checking the I/O "Write" and "Read" SA's (Loops
A, B and C) and by using a scope or logic probe
to confirm operation of other IC circuits.

I/O 4-3

Model 64100A - Performance Verification
4-6. KEYBOARD TEST

PROCEDURE.

Purpose:
The KEYBOARD TEST checks for keyboard switch closure and
keyboard decoding. Use SA loop F for trouble isolation.
Area Tested:
All 77 keyswitches, keyboard decoding electronics, keyboard
cable, and the keyboard RAM/state machine.
Operation:
a. When initiated, the KEYBOARD TEST instructs the user to
press all of the
keyboard keys in a left-to-right
top-to-bottom sequence.
b. The
sequence begins with the left-most softkey
includes all display and cursor control keys.

and

c. The keyboard test requires
this
specific sequence.
Furthermore, even if all keyswitches and the decoding
circuitry are working, a key that is pressed out of
sequence will cause a "FAILED TEST" message and end
the test.
d. The order in which the keys are pressed is given on figure
4-1.
e. There is a second test that involves observing if the
correct character is displayed on the CRT each time a key
is depressed while the system is in the PV mode. This
latter test can be observed any time during PV and is
useful
for
checking intermittent operation
of the
keyboard.
f. Note the keyboard
cycle mode.

test

is

skipped

while PV is in the

NOTE

Neither of the above tests is useful if
the keyboard is completely dead since the
keyboard must be working so that you can
press NEXT TEST in the Display Pattern to
get to the above tests.

I/O 4-4

Model 64100A - Performance Verification

I
\

\
\
\

Figure 4-1. Keyboard Test Sequence

I/O 4-5

Model 64100A - Performance Verification
4-7. SYSTEM BUS TEST PROCEDURE.
CAUTION
THIS TEST SHOULD NOT BE RUN IF THE
MAINFRAME IS
CONNECTED TO THE SYSTEM BUS. IT WILL CAUSE THE
OTHER MAINFRAMES ON THE BUS TO ABORT THERE SESSION.
Purpose:
During the System Bus Test, the PHI (U20 I/O board) chip is
taken off line and the CPU writes to and reads from its
internal registers.
The circuitry on the input side of
the PHI chip and most of the PHI chip itself is tested.
None of the output circuitry to the system bus is tested.
Use SA tables A, C and D to isolate a problem.
Area Tested:
The Data, address, control and interrupt lines from
to the PHI chip.

the

CPU

Operation:
a. The SYSTEM BUS TEST takes the PHI chip off line and reads
and writes to various registers in the PHI chip.
b. The transceiver lines and the cable to the Rear-panel
HP-IB connector are not presently being checked.
c. If an error occurs, it may
detected.
4-8.

take

up

to

2

minutes to be

RS-232 TEST PROCEDURE.
NOTE

I/O switch S5 must be set to return to
sender - grant aknowledgement "RTS" ( right
position).
The baud rate select switches
(S5) must be set to the fastest baud rate
( left position).
Switch S3 must must be
set to the "RS-232" (down position) and S2
must be set to "INTERNAL" (unless external
clocks are used) before tests can be run.
Purpose:
This test checks proper operation of the USART (U28 I/O PCB)
and the data/control circuitry associated with RS-232. Use
SA loop E for trouble isolation.
Area Tested:
The 8251 USART, the baud rate generator, loop back relays,
line drivers, the interface to the CPU, and the Rear-panel
cable.
I/O 4-6

Model 64100A - Performance Verification
1. The voltage translators cannot be signaturized on
higher voltage side.
Operation:
a. Energizes the loop back relays to loop transmit data,
handshake lines back on receive data.

the

and

b. Sends a character stream.
c. compares
receive
character stream.

character

stream

to

the

transmit

d. Notes:
1. If an error occurs it may take up to
to be detected.

two minutes

to

2. If all previous PV tests have passed, a problem in
this test will almost always indicate a failure in
the mentioned circuits under RS-232 Test Procedure
"Area Tested". Also, this test does
not check
the setting of the RS-232 mode switches on the
I/O board (S1,S2, S3 and S4) or the baud rate select
switch (S5).
4-9.

TROUBLESHOOTING USING SIGNATURE ANALYSIS.

4-10. Signature Analysis (SA) offers a good method of isolating hardware
logic failures down to the component level.
The basic concept is to
utilize a known set of start, stop and clock signals that constantly repeat
(loop) with the same timing relationships. When a suspect logic node is probed
with a Signature Analyzer while using the start, stop, and clock signals as
control inputs, the digital readout (signature) displayed on the analyzer can
be compared with the normal signature of that node to determine if the timing
relationships are proper.
With the 64100A Mainframe, looping is provided by
the PV software program and the normal signatures for various nodes are listed
in the tables 4-1 thru 4-6.
4-11.

SERVICE TOOLS.

4-12.

Suggested service tools are:
1.

2.
3.
4.

HP 5oo.4A or 5005A Signature Analyzer
Digital Voltmeter
Oscilloscope
Standard hand tools for electronic PC board repair.

I/O 4-1

Model 64100A - Performance Verification
4-13.

SA TABLES.

4-14. The I/O function signatures are categorized into 6 groups (loops) that
are a result of the type of test the PV was performing at the time a failure or
problem was noted. These loops are:
1.
2.
3.
4.
5.
6.

I/O Write (Loops A and B)
I/O Read (Loop C)
Time Interrupt (SA does not apply)
Keyboard (Loop F)
System HP-IB Bus (Loop D)
RS-232 Bus (Loop E)

4-15. The basic procedure is to refer to the appropriate table (i.e., the one
that corresponds to the loop that PV was exercising when the failure was noted)
and connect the Signature Analyzer to the Test Points called for in the table.
Next, verify that the "Vh" signature indicated in the test set-up is proper.
This signature is very important since it verifies that the start, stop and
clock signals are normal.
If this signature is good, proceed with the
signatures listed in the table while referring to the appropriate schematic for
guidance. If an improper signature is noted, check on both sides of the device
to determine if it is causing the problem or if the problem has its origin
further upstream.

NOTE

One of the first things that should be done
when isolating System Bus (HP-IB) and RS-232
failures is to replace the PHI or USART
chip. If this doesn't fix the problem, go
back to I/O write and I/O read and verify
the various signatures that show that the
buffered bus is working properly. In I/O
read, it is not necessary every time to
take signatures; simply toggle the switches
that are shown on the CRT display and verify
that the display is correct.

I/O 4-8

Model 64100A - Performance Verification
Table 4-1.

I/O Write Signature Analysis

Loop: A
PC Board: I/O Board.
Test failure: I/O S.A latch failure.
Procedure: Execute I/O Write test (to disable the beeper, jumper Q5 base (center lead) to emitter (dot).
S/A hookup:
START = POS EDGE CPU BD TP10 (S.A. INTERVAL)
STOP = POS EDGE CPU BD TP10 (S.A. INTERVAL)
CLOCK = POS EDGE I/O BP TP1 (LIOSB)
VH = 91C2
* = Probe blinking
Node

Sig

Node

Sig

U2-1
U2-2
U2-3
U2-4
U2-5
U2-6
U2-7
U2-8
U2-9
U2-11
U2-12
U2-13
U2-14
U2-15
U2-16
U2-17
U2-18
U2-19

0021
5807
FCU6
68PO
1CPF
PP8H
H72H
5A37
3FC8
AHOA
FC85
469U
7U3U
8A5P
U952
5A44
F9C5
0000*

U5-2
U5-3
U5-4
U5-5
U5-6
U5-7
U5-8
U5-9
U5-11
U5-12
U5-13
U5-14
U5-15
U5-16
U5-17
U5-18
U5-19

A14H
0000*
P405
9A2U
0021
0858
52F5
5A9H
5A9H
52F5
0858
0021
9A2U
P405
91C2
A14H
0000

U4-1
U4-2
U4-3
U4-4
U4-5
U4-6
U4-7
U4-8
U4-9
U4-11
U4-12
U4-13
U4-14
U4-15
U4-16
U4-17
U4-18
U4-19

0021
5C53
F54C
9CCP
P947
U639
3H09
0743
CCA3
2All
96U1
AFCC
678C
78U5
OAOF
54U9
FAP1
0000*

U6-2
U6-9
U6-11
U6-18

91C2
0000
0021
0000

U7-3
U7-6
U7-8
U7-11

OC8U
91C2
91C2
OC8U

Ull-2
Ull-7
Ull-ll
Ull-15

CC15
7C65
6987
96U3

U14-2
U14-5
U14-6
U14-9
U14-12
U14-15
U14-16
U14-19

90UU
P5P2
3460
2153
7756
6C86
2HOC
9P4F

I/O 4-9

Model 64100A - Performance Verification
Table

4-1.

I/O Write Signature Analysis (Cont'd)

Loop: A
PC Board: I/O Board.
Test failure: I/O S.A latch failure.
Procedure: Execute 1/0 Write test (to disable the beeper, jumper Q5 base (center lead) to emitter (dot).
S/A hookup:
START = POS EDGE CPU BD TP10 (S.A. INTERVAL)
STOP = POS EDGE CPU BD TPlO (S.A. INTERVAL)
CLOCK = POS EDGE 1/0 BP TP1 (LIOSB)
VH = 91C2
* = Probe blinking

I/O 4-10

Node

Sig

Node

Sig

UI6-S
U16-12

OC9H
91C2

U43-S
U43-9
U43-10

C363
2All
22Hl

U17-9
U17-1O
U17-12
U17-15

FSUS
FOC2
9265
91C2

U1S-7
UlS-10
UlS-13
UlS-14
UlS-15

91C2
91AO
91C2
91C2
OCSU

U44-1
U44-2
U44-5
U44-6
U44-9
U44-11
U44-16
U44-19

91C2
AU70
F7HF
CUIF
HHU6
FOC2
7HUO
C927

U22-12

91C2

U23-2
U23-3
U23-5
U23-6
U23-S
U23-10
U23-11
U23-13

0000
91C2
0000
91C2
91C2
0000
91C2
0000

U45-1
U45-2
U45-3
U45-4
U45-5
U45-6
U45-7
U45-9
U45-10
U45-11
U45-12

0000
30UU
HU55
S5FF
FC2C
24S1
UCH4
9193
FSH9
91C2
91C2

U24-2
U24-3
U24-6
U24-S
U24-10
U24-11
U24-13

0000
91C2
91C2
91C2
0000
91C2
0000

U30-6
U30-S

91C2
91C2

U53-1
U53-2
U53-3
U53-4
U53-5
U53-6
U53-7
U53-S
U53-9
U53-10
U53-11

91C2*
91C2*
91C2*
91C2*
91C2*
91C2*
91C2*
91C2*
91C2*
91C2*
91C2*

U31-4
U31-10
U31-14

0021
9193
0000*

U54-3
U54-5
U54-14
U54-16

UCH4
FC2C
S5FF
24S1

Model 64100A - Performance Verification
Figure 4-2. I/O Write Signature Analysis
Loop: B
PC Board: I/O Board.
Test failure or circuit: I/O WRITE TEST.
Procedure: Execute I/O Write Test. (To disable the beeper, Q5 may be jumpered, base to emitter.)
S/A hookup:
START = POS EDGE 1/0 BD TP2 (S.A. INTERVAL)
STOP = NEG EDGE I/O BD TP2 (S.A. INTERVAL)
CLOCK = POS EDGE CPU BD TPI (LSTB)
VH = 7468

Node

Sig

Node

Sig

U43-8
U43-9

C79A
CU6P

U53-1
U53-2
U53-3
U53-4
U53-5
U53-6
U53-7

P291
U197
U4Al
CUOP
AC3A

U53-8
U53-9
U53-10
U53-11
U53-18
U53-19
U53-20
U53-21
U53-22
U53-23

53P5
FACI
4AFC
6H3U
C79A
CC65
APH6
3UOP
OU77
8UHP

C265

H018

I/O 4-11

Model 64100A - Performance Verification
Table 4-3.

I/O Read Signature Analysis

Loop: C
PC Board: I/O Board.
Test failure or circuit: I/O READ.
Procedure: Execute I/O Read Test.
S/A hookup:
START = POS EDGE I/O BD TP2 (S.A. INTERVAL)
STOP = NEG EDGE I/O BD TP2 (S.A. INTERVAL)
CLOCK = POS EDGE I/O BD TPI (LIOSB)
VH = 0007
* = Probe Blinking

Node

Sig

Node

Sig

ALL S4 SET ON (RIGHT), S3 SET
SET TO CL (UP)
U4-2
U4-3
U4-4
U4-5
U4-6
U4-7
U4-8
U4-9

0007*
0001
0003
0001
0003
0003
0003
0003

U35-3
U35-5
U35-7
U35-9
U35-12
U35-14
U35-16
U35-18

Node

Sig

000*
0006
0001
0004
0001
0001
0004
0001
0006
0007*

U6-2
U6-9
U6-11
U6-18

0007
0000*
0007*
0000

U7-3
U7-5
U7-6
U7-8

0007
0005
0005
0007

I/O 4-12

Sig

ALL S4 SET OFF (LEFT), S3 SET
TO RS-232 (DOWN)
0003
0001
0003
0007*
0003
0003
0003
0003

U4-2
U4-3
U4-4
U4-5
U4-6
U4-7
U4-8
U4-9

0007*
0005
0007
0005·
0007*
0007*
0007*
0007*

IMMATERIAL HOW S3 OR S4 ARE SET
U5-3
U5-5
U5-7
U5-8
U5-9
U5-11
U5-12
U5-13
U5-15
U5-17

Node

UI4-2
UI4-5
UI4-6
UI4-9
UI4-12
U14-15
UI4-16
UI4-19

0007*
0000
0000
0000
0000
0000
0000
0000

UI7-9
UI7-IO
UI7-12
UI7-15

0006
0007
0007*
0007

UI8-7
UI8-IO
UI8-13
UI8-14
UI8-15

0007
0007*
0007
0003
0005

U22-12

0007

U22-12

0007

U23-2
U23-3
U23-5
U23-6
U23-8
U23-10
U23-11
U23-13

0000
0007
0000
0007
0007
0000
0007
0000

U24-2
U24-3
U24-5
U24-6
U24-8
U24-IO
U24-11
U24-13

0000
0007
0000*
0007
0007
0000
0007
0000

U31-4
U3I-IO
U31-13

0007*
0000*
0000*

U35-3
U35-5
U35-7
U35-9
U35-12
U35-14
U35-16
U35-18

0007*
0005
0007*
0007*
0007*
0007*
0007*
0007*

Model 64100A - Performance Verification
Table

4-4 I/O Bus Signature Analysis

Loop: D
PC Board: 110 Board.
Test failure or circuit: 110 SYS BUS TEST.
Procedure: Execute System Bus Test.
S/A hookup:
START = POS EDGE I/O BD TP2 (S.A. INTERVAL)
STOP = NEG EDGE 110 BD TP2 (S.A. INTERVAL)
CLOCK = POS EDGE 110 BD TPI (LIOSB)
VH = 9A4A
* = Probe blinking
Node

Sig

Node

Sig

Node

Sig

U2-2
U2-3
U2-4
U2-5
U2-6
U2-7
U2-8
U2-9
U2-ll
U2-l2
U2-l3
U2-l4
U2-l5
U2-l6
U2-l7
U2-l8

4F66
4PUH
5549
H32F
A18F
8CP6
574F
61U6
UCCF
FH06
llAF
3CF6
4966
FU03
H4C7
H62F

U5-ll
U5-l2
U5-l3
U5-l5
U5-l7

0001
0000*
0001
9A4C
9A4A*

U16-2
U16-3
U16-4
U16-10
U16-ll

OA63
9A4A*
0000*
0000*
9A4A*

U6-2
U6-9
U6-ll
U6-18

9A4A*
OA63
9029
0000*

U17-9
U17-l0
U17-l2
U17-l4

9A4C
9A4A
9A4A*
9A4A
9A4A
9A4A*
9A4A
9A4A
0001

C4l5
98A3
3A12
3C9P
3C9P
3C9P
ACC6
ACC6
3lUF
3lUF
AlH4
AlH4
AlH4
A058
02P9
2P5U

9029
HU64
OA63
9A4A
452U
HU64
HU65
0001

U18-7
U18-10
U18-l3
U18-l4
U18-l5

U4-2
U4-3
U4-4
U4-5
U4-6
U4-7
U4-8
U4-9
U4-ll
U4-l2
U4-l3
U4-l4
U4-l5
U4-l6
U4-l7
U4-l8

U7-2
U7-3
U7-4
U7-6
U7-9
U7-ll
U7-l2
U7-l3

U22-l2

9A4A*

Ull-l
Ull-2
Ull-4
Ull-5
Ull-7
Ull-ll
Ull-12
Ull-13
Ull-15

9A4A
2427
C4l5
3A12
l7FA
9A4A
3C9P
98A3
07A8

U23-2
U23-3
U23-5
U23-6
U23-8
U23-10
U23-ll
U23-l3

0000
9A4A*
0000
9A4A*
9A4A*
0000*
9A4A
9A4A

U5-3
U5-5
U5-7
U5-8
U5-9

0000*
9A4C
0001
0000*
0001

U14-2
U14-5
U14-6
U14-9
U14-l2
U14-l5
U14-l6
U14-l9

0000*
0000
0000
0000
0000
0000
0000
0000*

U24-2
U24-3
U24-5
U24-6
U24-8
U24-10
U24-ll
U24-l3

0000
9A4A
9A4A/395l
9A4A
9A4A
0000
9A4A
0000

U3l-4
U3l-l3

9029
0000*

I/O 4-13

Model 64100A - Performance Verification
Table 4-5.

I/O

RS232 Signature Analysis

Loop: E
PC Board: I/O Board.
Test failure or circuit: RS-232 FAILURE.
Procedure: Set S5 to half-duplex and fastest baud rate. Set S3 to RS-232.
Set all switches on S4 to the left. Execute RS-232 Test.
S/A hookup:
START = POS EDGE I/O BD TP2 (S.A. INTERVAL)
STOP = NEG EDGE I/O BD TP2 (S.A. INTEVAL)
CLOCK = POS EDGE I/O BD TPI (LIOSB)
VH = OOUP
* = Probe blinking

I/O 4-14

Node

Sig

Node

Sig

U2-2
U2-3
U2-4
U2-5
U2-6
U2-7
U2-8
U2-9
U2-11
U2-l2
U2-l3
U2-l4
U2-l5
U2-l6
U2-l7
U2-l8

0019
005U
OOlH
OOlH
OOlH
OOlH
003H
005H
00A3
00F3
00P3
00P3
00P3
00P3
OOAI
00P7

U18-7
U18-10
U18-l3
U18-l4
U18-l5

OOUP
OOUF
009A
00P6
007U

U22-l2

OOUp*

U23-3
U23-5
U23-6
U23-8
U23-l0
U23-11
U23-l3

U23-2
OOUP
0000*
OOUp*
OOUP
0000
OOUp*
0000*

U5-3
U5-5
U5-7
U5-8
U5-9
U5-11
U5-l2
U5-l3
U5-l5
U5-l7

0000*
OOUU
0003
OOIA
0065
0065
OOIA
0003
OOUU
OOUP*

U24-2
U24-3
U24-5
U24-6
U24-8
U24-10
U24-11
U24-l3

0000
OOUP
OOUH
OOUP
OOUP
0000
OOUP
0000

U17-9
U17-10
U17-l2
U17-l5

OOUU
OOUP
OOUp*
OOUP

U28-3
U28-l7
U28-l9
U28-22
U28-23
U28-24

OOUp*
003U
OOUp*
OOlU
003U
OOlU

U3l-4
U3l-l0
U3l-l3

0019
00P7
0000*

Model 64100A - Performance Verification
Table 4-6.

I/O Keyboard Signature Analysis

Loop: F
PC Board: I/O Board.
Test failure or circuit: KEYBOARD FAILURE.
Procedure: Set all test jumpers to "Test" position, Except EI and E2. Executer Keyboard Test.
S/A hookup:
START = POS EDGE I/O BOARD TP7
STOP = POS EDGE I/O BOARD TP7
CLOCK = POS EDGE I/O BOARD TP8
VH = 8P54
* = Probe Blinking

Node

Sig

Node

Sig

U25-6
U25-8

C4FP
3A9A

U34-3
U34-4
U34-5
U34-6
U34-8
U34-9
U34-10
U34-11

0863
HH53
HIOF
3A9A
FCF2
2946
F6IC
0108

U38-I
U38-4
U38-8
U38-10
U38-I3

84H4
I8A5
2046
API2
A492

U39-1
U39-5
U39-6
U39-7
U39-9

0000*
HH89
53HH
29PP
A7CA

U40-5
U40-6
U40-8

FCF2
OA80
3I4C

I/O 4-15/(4-16 blank)

Model 64100A - Adjustments
SECTION V
ADJUSTMENTS

5-1.

GENERAL •

5-2.

The I/O, Keyboard and Rear-Panel PC boards have no adjustments.

I/O 5-1/(5-2 blank)

Model 64100A - Replaceable Parts
SECTION VI
REPLACEABLE PARTS
6-1. INTRODUCTION.
6-2. This
names and
6-2 lists
Table 6-3
boards in

section contains information for ordering parts. Table 6-1 lists the
addresses that correspond to the manufacturers' code numbers. Table
the abbreviations used in the parts list and throughout this manual.
lists all replaceable parts for the I/O, Rear-panel, and Keyboard PC
reference designator order.

6-3. ABBREVIATIONS.
6-4. Table 6-2 lists abbreviations used in the parts list, the schematics, and
elsewhere in this manual.
In some cases, two forms of the abbreviation are
used; one, all in capital letters, and two, partial or no capitals.
This
occurs because the abbreviations in the parts list are always all capitals.
However, in the schematics and other parts of the manual, other abbreviation
~orms may be used with both lowercase and uppercase letters.
6-5. ORDERING INFORMATION.

6-6. To order a part listed in the replaceable parts list

(See table 6-3),
quote the Hewlett-Packard part number and check digit, indicate the quantity
required, and address the order to the nearest Hewlett-Packard Office (refer to
Sales and Service offices listed at the back of the mainframe manual).

6-7. To order a part that is not listed in table 6-3, include the HP Part
Number for the part, the description and function of the part, and the quantity
of parts required.
Address the order to the nearest Hewlett-Packard office.

I/O 6-1

Model 64100A - Replaceable Parts

Table 6-1. List of Manufacturers' Codes
MFR NO.
00000
00466
01121
01295
01928
03888
04713
07263
09023
13103
19701
20940
24546
26654
27014
27777
28480
30983
32997
34344
34649
56289
71590
72136
75042
75382
75915

I/O 6-2

MANUFACTURER NAME
Any Satisfactory Supplier
Norelco N. Amer philips Corp
Allen-Bradley Co
Texas Instr Semicond Div
RCA Corp Solid State Div
IIDI Pyrofilm Corp
Motorola Semicond Products
Fairchild Semicond Div
Cornell-Dubilier Eleck Div
Thermalloy Co
Mepco/Electra Corp
Micro-Ohm Corp
Corning Glass Wks
Varadyne Inc
National Semicond Corp
Varo Semicond Inc
Hewlett-Packard Hq
Mepco/Electra Corp
Bourns Trimpot Div
Motorola Inc
Intel Corp
Sprague Elect Co
Centralab Eleck Div
Electro Motive Corp
TRW Inc
Kulka Elect Corp
Littlefuse Inc

ADDRESS

ZIP CODE

Los Angeles Ca
Milwaukee Wi
Dallas Tx:
Somerville NJ
Whippany NJ
Phoenix Az
Mountain View Ca
Sanford NC
Dallas Tx
Mineral Wells Tx:
EI Monte Ca
Bradford Pa
Santa Monica Ca
Santa Clara Ca
Garland Tx
Palo Alto Ca
San Diego Ca
Riverside Ca
Franklin Park II
Mountain View Ca
North Adams Ma
Milwaukee Wi
Willimantic Ct
Philade Iphia Pa
Mt Vernon NY
Des Plaines II

90021
53204
75222
08876
07981
85062
94042
27330
75234
76067
91731
16701
90404
95051
75040
94304
92121
92507
60131
95051
01247
50501
06226
19108
10550
60016

Model 64100A - Replaceable Parts
6-8. DIRECT MAIL ORDER SYSTEM
6-9. Within the USA, Hewlett-Packard can supply parts
order system. Advantages of using this system are:
from

through a direct mail

1.

Direct ordering and shipment
in Mountain View, California.

the HP Parts Center

2.

No maximum or minimum on any mail order (there is a
minimum order amount for parts ordered through a local
HP office when the orders require billing and invoicing).

3.

Prepaid transportation (there is a small handling
for each order).

charge

4. No invoices

(to provide these advantages, a check or
money order must accompany each order).

6-10. Mail-order forms
your local HP office.
this manual.

and specific ordering information are available through
Addresses and phone numbers are located at the back of

6-11. PARTS LIST
6-12. Table 6-3 lists the replaceable parts for
Keyboard PC boards and is organized as follows:

the I/O,

1.

Electrical assemblies and their components in
alphanumerical order by reference designation.

2.

Miscellaneous parts.

Rear-panel,

and

6-13. The information given for each part consists of the following:
1.

Hewlett-Packard part number
(for HP internal use).

and

check digit.

2.

Total quantity (Qty) on the PC board.

3.

Description of the part.

4. TYpical manufacturer of the part in a five-digit
code.

5. Manufacturer's number for the part.

NOTE

The total quantity for each part is given only at
the first appearance of the part number in the list.

I/O 6-3

Model 64100A - Replaceable Parts

Table 6-2. Reference Designators and Abbreviations
REFERENCE DESIGNATORS

CP
CR
DL
OS

= assembly
= motor
= battery
= capacitor
= coupler
= diode
= delay line
= device signaling !lamp)

E

= mise electronic part

MK

A

= amperes

H

AFC

= automatic frequency

HOW

A

B

BT
C

F

FL
IC

MP

= fuse
= filter

P

= mechanical part
= plug
= transistor
= resistor

U
V

= integrated circuit
= vacuum, tube, neon

VR

= voltage regulator

=
=
=
=

= integrated circuit

a
R

K

= jack
= relay

RT

= thermistor

W

L

= inductor
= loud speaker

M

= meter
= microphone

TB
TP

= switch
= transformer
= terminal board
= test point

X

LS

5
T

J

bulb, photocell, etc

Y
Z

cable
socket
crystal
tuned cavity network

ABBREVIATIONS
= henries
= hardware

N/O

= normally open

NOM

= nominal

= hexagonal

NPO

= negative positive zero
(zero temperature

RMO
RMS

= rack mount only

RWV

= reverse working

= root-mean square

control

AMPL

= amplifier

BFO
BE CU
BH
BP
BRS
BWO

= beat frequency oscillator
= beryllium copper
= binder head
= bandpass
= brass
= backward wave oscillator

CCW
CER
CMO
COEF
COM
COMP
COMPL
CONN
CP
CRT
CW

= counter-clockwise
= ceramic

HEX
HG
HR
HZ

= mercury

= houris)
= hertz

= intermediate

IF
IMPG
INCD
INCL
INS
INT

= incandescent
= includels)

= common
= composition

K

= kilo=1000

= complete

= left hand
= linear taper

= clockwise

LH
LIN
LK WASH
LOG
LPF

DEPC
DR

= deposited carbon

M

= drive

ELECT
ENCAP
EXT

= electrolytic

MEG
MET FLM
MET OX
MFR
MHZ
MINAT
MOM
MOS
MTG
MY

= milli=10-3
= meg=106
= metal film

= cabinet mount
= coeficient

only

= connector
~

cadmium plate
= cathode-ray tube

= encapsulated
= external

= insulation(ed)
= internal

washer

= logarithmic taper
= low pass filter

NRFR

negative
= not recommended for

NSR

= order by description

P

= peak

PC
PF

= printed circuit
= picofarads= 10-12

PH BRZ
PHL
PIV
PNP
POLY
PORC
POS
POT
PP
PT
PWV

=
=
=
=

miniature
momentary
metal oxide substrate
mounting

G

= giga (109)

GE
GL
GRD

= germanium

N
N/C

"" nano 110--1l)
= normally closed

= glass
= groundled)

NE
NIPL

= neon

= "mylar"

= nickel plate

= oval head

= oxide

farads
= phosphor bronze
= phillips

= peak inverse voltage
= positive-negativepositive

= manufacturer

= mega hertz

field replacement
= not separately
replaceable

OBD
OH
OX

P/O

= farads
= flat head
= fiIIister head
= fixed

I/O 6-4

= negative-positive-

= metallic oxide

FH
FIL H
FXD

F

NPN
freq

= impregnated

= lock

voltage

coefficient)

RECT
RF
RH

= part of
= polystyrene
= porcelain

S-B
SCR
SE
SECT
SEMICON
51

SIL
SL
SPG
SPL
SST
SR
STL
TA
TO
TGL
THO
TI
TOL
TRIM
TWT

= slow-blow

= screw
= selenium

= sectionls)
= semiconductor

= silicon
= silver
= slide
= spring
= special
= stainless steel
= split ring
= steel

= tantalum
= time delay
= toggle
= thread

= titanium
= tolerance

= trimmer
= traveling

wave tube

U

= micro=10-6

VAR
VDCW

= variable

WI
W

= with
= watts

WIV

=

= positionls)
= potentiometer

peak-to-peak
= point
= peak working voltage
~

= rectifier

= radio frequency

= round

head or

right hand

WW
W/O

= dc working volts

working inverse
voltage
= wirewound
= without

Model 64100A - Replaceable Parts
Table 6-3. Replaceable Parts List
Reference
Designation

HP Part
Number

c Qty
0

A6

64100-66520

8

I

CI
Cl
el
Cq
cs

0100-2055
QUO-20SS
01110-2055
011>0_2055
a 1I>0_lOSS

9
9
9

IS

q
q

CII
C7
C8
Cq
CIO

0IqO_Oc07
01qO-0207
0140_0207

7
7
7

0180-0197

8

S

Mfr
Code

Description

Mfr Part Number

aUlo

64100-66520

21410
U480
laUD
28410

ouo-aoss
OIIlO-lOn
01100.20n
Oillo.aoss
o III00lon

CAPACITOR-FXIl HOPF .-51 SOOVOC MICA
CAPACITOR-'XD 330PF .-51 SOOVOC MICA
CAPACITOR-FXO HOP' ._51 SOOVOC MICA

721311
721311
HUll

OMISF131JOSOOWVICR
OMIS'33IJOSOOWVICR
OMI5F331JOSOOWVICR

CAPACITOR-FXD 2.2UF +-10% 20VDC TA

56289

1 50D225X9020A2

1/0 CIRCUIT eo.~o .aaEMe~V

CAPACITOR-'XO
CAPACITOR-nO
CAPAcnOR-FXD
CAPAC nOR-no
CAPACITOR-FXO

,DIU'
,DIU'
,0 \U'
,OIUF
,DIUF

.80-cOl
+80-20X
.80-201
tao-lOX
.80-2OX

100VOC
100VOC
100VOC
100VOC
100VOC

CER
CER
CER
CER
CER

UUO

01110-2055

q

CII
CIi!
C\3
CU
CIS

01100_2055
a I 00-0207
01qO_0207
oaO-20SS
01100_2055

q

7
q
Ii

Ch
C17
Cu
Clq
C20

01110-2055
o II>O-~055

q
q

OI~0-2055

'I
'I
'I

C21
C22
CH
Cl4
CZ5

01/00_2055
01/00-2055
01110_2055
0100-2055
0100-2055

CU
C27
C28
C2q
CIO

0140_01'15
01eo-015Q
0100-2055
0100-2055
01110-2055

2
5

Cll
CI2

C]Q
CI5

01/00_2055
011l0-Z055
0Iso_01'l7
01bO-20S5
OIOO-Olbi

q
q
I
q

CIb
cn
C38
C3'I
C40

01110-2055
ouo-oln
01100_2055
0100-2055
0100-2055

'I

e41
CQz
CUI
C44
C45

01110-2055
01110-2055
01100-2055
Oleo-ona
0180-0374

q
'I

cQ.
C41
CQe

0180_0374
01b0-205S

•

3

C4~

C50

01100_2055
011>0-2055

C51

0180_01U

CRI
CRe
CRI
CR.

1'101-0000
1901_00QO
190 1e0040
1'101_0040

I
I
I
I

4

CR5

1901-0535

9

1

DIODE-SM SIG SCHOTTKY

28480

1901-0535

5040-1>073
8151-0013
IcOO-0475
1200-0519
UOO-Obl!

Q
0
7
7

I
I
6

nTRACTOR (REO)
WIRE 2?AwG I X22
CONNECTOR-SG~ CONT SKT ,OII>-IN-8SC-SZ
SOCKET-IC \~-CONT oIP-a~OR
SOCKET_IC IQ-CONT DIP-S~OR

.IUO
28480
28UO
21410
28480

5nQO-1I07J
8\SI-0013
IlOO-O"n
IZOO-OSH

1200-0Sc7
1200-0819
1251-4388
'Qeo-o \I b

I
0

I
I
1

SOCKET-IC 2S-CONT

21480
ZIUO
2!GlD
28UO

1200-0Sb7
1200-063.
1251-438S
UAO-Ollo

IS51-0000
18SQ_OQ72
\854-02011
IASQ-047l
,SSQ_024b

0
2
8

04711
OQ713
OQ713
00713
04713

2~3\IQ

cn

MPI
MP2
MPI
MP4
MP5
MPII
MP7
~P8

,,"P'I
QI
Q2
Q3
QQ
Q5

01/00-2055
o 1Io0_l055

7

'I
'I

Ii
Ii
'I

I
I

Ii

'I
'I

4

3
I

8
'I
Ii
~

CAPACITOR-,XO ,olUF .80-cOI loovoe CER

Zlno

CAPACITOR-no
CAPAC ITOR-nO
CAPAC ITOR-, xo
CAPACITOR-FXO
CAPAC ITOR-nO

,DIU'
330PF
nOPF
,DIU'
,OIUF

t80-20X 100VOC CER
.. 51 SOOVOC MICA
.-51 SOOVOC MICA
t10-20l 100VOC CER
.80.201 100VOC CER

21ql0
721311
7ZIJII
21ql0
aUlo

01110-2055
OMI5F331JDSOOWVICR
oMIS'33IJ0500WVICR
01110.2055
OleO-lOSS

CAPACITOR-FXO
CAPACITOR-nO
CAPAC nOR-no
CAPAC nOR-no
CAPAC nOR-no

,OIUF
,OIUF
,OIUF
,OIU'
,OIU'

+SO-20l
.80-l0l
+80-Z0X
.10-20X
+10-20X

100vOC
100VOC
100VOC
100VOC
100VOC

CER
CER
CER
CER
C!R

21410
28410
2Uao
28410
21410

01.o·z0n
01100-Z055
oao-zon
OIIlO-i055
o III0d055

CAPAC ITOR-nO
CAPAC ITOR_nO
OPACITOR-nO
CAPACITOR-'XO
CAPAClTOR-FXO

,OIUF
,DIU'
,OIUF
,OIUF

+10-20X
+80-201
+10-20X
+80-20X
,0 IU' t80-20X

100VOC
100VOC
100VOC
100VOC
100VOC

CER
CER
CER
CER
CER

21410
21410
2&410
UUO
28480

OlllOdon
OlllOdon
Olloo.zon
0\110.2055
0100-2051

CAPAC ITOR-FXO
CAPACITOR-FxO
CAPACITOR-nO
CAPAC ITOR-nO
OPACITOR-nO

110PF ._5' 100VOC ~ICA
2200PF +-10' 200VOC PO~VE
,OIU' +SO-201 100VoC C[R
,DIU' +SO-20l IOOVOC CER
,OIU' +80-Z01 100VOC CER

7ZUII
ZUIO
zuao
21410
HUO

OIIlO.Ol5a
Olllod051
01110-2055
0100-2055

CAPACITOR-nO
CAPAC ITOR-FXO
CVAC ITOR-FXO
CAPACITOR-nO
CAPACITOR-'XO

,olUF +80-2U 100VOC CER
,OIU' .80-201 100VOC CER
2,2UF.-IOI 20VOC TA
,OIUF +80-201 IDOVOC CER
,OIUF .-101 200VOC PO~V[

sun

CAPACITOR-nO
CAPACITOR-no
CAPAClTOR-FXO
CAPAC ITOR-FXO
CAPAC I TOR-no

,OIUF .80-201 100vOC
2,2UF.-IOI 20VOC TA
,OIUF t80-l0X 100VoC
,OIU' .80-201 100Voc
,OIUF .10-ZOl loovoe

CAPACITOR-nO
CAPACITOR-nO
CAPACITOR-nO
CAPAC ITOR-nO
CAPAC ITOR-nO

,OIU' +80-2OX 100VOC CER
,DIU' +10-201 100VOC CER
,OIUF .eO-lOl 10OVOC CER
IOU~.-IOl 20VOC TA
10UF.-IOX 20VOC TA

CER
CER
CER
CER

28480
28410
28480
UQ80
UUO

sun
ZlUO
21410
nuo

0\100-2015

0~15FI3IJOJOOWVICR

Oillo.aon
OloOdOS.
1500225X'OZOAZ
01110-2055
oIllO-OIU
01/00-2055
150022U'I0i0Al
01100-2055
0100.2055
01U-20S5

n4ao
21410
UUO

olu.zon
01110-2055
01ll0-ZOS5
150DIOU'IOaoez
15001 OIoX~Oi08i

CAPACITOR-no 10UF.-IOX 20VOC TA
CA'AcnOR-FXD ,CIUF .eO-20X 100vOC CER

5021'1

21410

1500 I OOXQ02081
011l0-20S5

9
q

CAPAcnOR-nD ,OIU~ .80-cOl 100VOC CER
CAPAClTOR_FXO ,OIU' +~O-iiOl 100VOC C~R

iilGlO
2UIO

01110-2055

3

CA'AClTOR-FXO 10ur.-10, ?oVOC TA

sun

1~0010bn0208c

iiUIO
.IUO
21Ql0
2SQl0

IqOI.0040
ICIOI_OOQO
1'01-0040
1901_0040

'I
3
I

a

q

e

Z

e

Q

I
I

OIOOE-SWITC~ING
OIOOE-SwITC~ING
OIOO!-SWITCHI~G
OIODE-S~ITCHI~G

10V 50~A 2NS 00-35
10V 50~A 2NS ~0_35
lOV 50MA 2NS 00_35
10V 50~A 2NS 00_]5

DIP_S~OR

SOCKET-Ie 48-PIN (FOR U20,

PHI)

,

CONNECTOR 3-PIN M POST TYPE
PIN-GRV .Ob2-IN_OIA ,25-IN-~G

2
2

TRANSISTOR p,p 2NII]4 51 TO-5 PO'bOO~.
TUNSISTOR ~PN SI OAR~ Po.500~w
TRANSISTOR NPN SI ~D.]50MW FT.lSOM~Z
TRANSlaTOR NPN SI OAR~ ~D.5noM.
TRANSISTOR NPN SI PO.150~. FT.250M~Z

,

ST~

See introduction to this section for ordering information

sun
sun

OIIl0_i!0~5

1C0o.O~le

MPS-AI~

S~S 2ll
MPS-A\4
SPS ill

I/O 6-5

Model 64100A - Replaceable Parts
Table 6-3. Replaceable Parts List (continued)
Reference
Designation

HP Part
Number

c Qty
o

07S7_0290
0757_02'0
07S7-IOOI
0757_072 4
0757-044]

5
5
8

7

o

5

R7
R&
R9
RIO

0757-0720
0757_07

iI

\

8
2

4

!I

I
I

2
3

t

9
8
1

I
I

1
J

..

IC
IC
IC
IC
IC

GATE TTL LI NOR QUAD a-INP
,~ TTL La D-TVPE POI-EDaE-TRIG
MY TTL L8 MON08TIL RETAIG DUAL
tNTR TTL LI BIN DUAL 4-81T
DRVR TTL LS LINE DRVR OCTL

It
IC
IC
IC

10-IIPI.'M OH~ X 9
CNTR TTL LI 81N DUAL .-aIT
GAT! TTL LI ~OR QUAD a-INP
" TTL LI J-K NEG-EDGE_TRIG
" TTL L8 D-TVPE POS-EDGE-TRIG

IC
IC
IC
Ie
IC

TIMER TTL MONO/iITIL
SCHMITT-TRIG TTL LI NAND DUAL 4-INP
GATE TTL LS NAND QUAD a-INP
~, TTL LI D-TVP! POI-EDaE-TRIG CD~
DCDA TTL LS 2-TO-4-LI~E DUAL 2-INP

~!T~ORM-AE8

2
I>

Description

t

I

IC RCVR DTL
NETWORK_RE8
Ie GEN DUAL
IC CNTR TTL
IC GATE TTL

NAND LINE QUAD
10-SIPt.IM OHM x 9
LI 81N SVNCHRD PDI-EDGE-TRIG
LI NAND QUAD I-INP

IC I~A TTL NAND QUAD I-INP
It MV TT~ La MONOSTBL RETRIG
It DC DR TTL 4-TO-lll-LINE a-INP
IC D~VR TTL LI LINE DRVR OCTL
IC SCHMITT-TAIG TTL LS INy ~EX I-INP
DIODE_ZNR 2.37V 51 00_7 PD-.IW TC--.OUI
DIODE_ZNR 1 •• 2V 51 DO_7 PD_.aw TC-t.OI"

Mfr
Code
01'"

un.

OU95
072113
0119.
01111

ouu
OU95
011'5
OU9I

04713

OIl'S
01291

olltS

01191

0.7U
01121
IU"

01191
OU"

OU9I

oun

01195

olnl
OU'S

IIno
28110

Mfr Part Number
IN74LIOIN
IN74LU4N
IN7GLIIUN
ULIJUPC
IN74LIU4N
21OAII2
ULUUPC
IN7.LI02N
IN74LII12N
IN74LI14N
MCI4!1!iP'1
INUL8UN
IN74LUON
SNULII7JN
IN74LIU'N
MCtG"AL
"OAIII
KUllA
IN74LIIUAN
IN74LIOON
IN74J1N
SN74LIIZlN
INUtS4N
IN74LUUN
IN74LIUN
,'ohIOOl
190hl10.

See introduction to this section for ordering information

I/O 6-7

Model 64100A - Replaceable Parts
Table 6-3. Replaceable Parts List (continued)
HP Part
Number

D

A4

UIOO-"S04

I

I

M!V80A~0

CI
C2
C3
C4
CS

0180-0230
Oho_2ns
01'0-20!5
0140_01"
01.0.1204

0

I

'I

4

CApAcno~-~xo
CApAcno.-~xD
CAPAC nOR-~xo

C'
C7
CI
C'
CIO

Oho_20SS
oho·IO!!!
011.0_3443
OhO-2I . .
OhO·21'11

CII
CII
CI3
CI4
CIS

·OIU.U'1
01'1-21'1
OhO.)40
01U·21'11
01&0·2191

I
I
I
I
I

CAPAC%TDR-'xD

Ch

cn

OIU_lIn
OhO.2198

I
I

CAPACtTOR-~XO 20P~
CAPAC%TOR.~XD 20p~

HI

2UO.0IU

2

6

1011'1

1101.1137

7

77

QI

IIS4-02 . .
1153.0015
I 854-0 ill 5
185 . . 0215

I
7
I
I

I
I
2
I
I
I

Reference
Designation

Q2

Q]
Q4

c

"
3
0

Qty

I
I

•

R1

0757-0389,

5

R2
RS
R4
RI

on1.0U,
0751.0401
0757.0280
on1·0UO

0
3
3

R.
Ra
R'
RIO

0751.0438
UQa.3151
un.JISI
0751.0120
0157.041'

3
1
7
3
1

RII

0751.04,4

UI
U2
U3
U4

•

CIRCUIT BOARD

Ala!~eLY

a
8

UIOO-"104

5'1"
21410
UUO
7U,.
uuo

I SOOI OIXonOAI
OI'O.lon
01'0-1015

,OIU~ .10-'01 IDOVOC CER
CAPAcnOR-~xo ,0IU~ .eO.201 100VOC CER
CApAcnOR-~xo ,I U~ .10-201 SOVOC CIR
CAI'ACnOR-~xO 20l'~ .-,. )DOVOC M%CA
CAPAcnOR-'XO 20l'~ . . n JOOVOC M%CA

U4IO
"410
uno
uno
UIIO

OI.o-IOSI
OI.OdOS.
OUO-U4J
OIu-au.
OI"ell"

CApAcnOR_~xo

t-51 300VOC M%CA
t-SI 300YOC M%CA
t10-201 sovOC CER
.-u JOOVOC IoI%CA
. . 51 300vDC MICA

UUO
UUO
11 . . 0
11410

OIUdl"
Ol".al"

IUeo

OI,o.ill'l
01.0-21"

. . SI JoOYOC IoltCA
•• 51 300YOC IoI%CA

U4l0
21410

01'0.11'1
01.0-11'1'

CAI'AC nOR-~xo
CApAcnOR-~xo

20l'~

O~IS~I'IJOJOOWYIC~

ol,o-no.

01.0-.. -1

SCREW_MACH '-32 ,U.%N.LG pAN.HO.POrI

00000

OROIR IY DEICR%PT%GN

MEV IWnCM (INDUCTIVE)

uno

3101-1137

T'UNUSTOR NPN at PO_JSOMW ~hISOMHZ
TRANaUTOR I'NP It PO_200MW ~hSOOMHZ
TRANIUTOR N~N 1% PO-JSO~w n_JOOMHZ
TUNaUTOR !/'N at pD_nOMW ~UlOOIolHZ

04713
U4IO
047U
04711

1851.001.
INUO_
INI".

RESISTOR 33.2 1% .125W F

TC~0+-100

REatlTOR 10K II ,I21W ~ TC-O •• IOO
RES%STOR 100 IX ,I2SW ~ TC-Ot.IOO
~!StSTOR 1M IX ,I'~W ~ TC_O._IOO
REStSTOR 1M II ,I'IW ~ TC_Ot.IOO
~ TC-0"100
, Te-OhIOO
~ Te-OhIOO
TC-O.-IOO
TC-Ot·100

IU

0757-0389

,.1 ..

,.,..

C4·III.TO·IOU·'

24"&
14S4,

C4-I/I·TO·100I-~

C4.I/I·TO-1001·'

1414'

C4.I/I-T'·'III-~

14 . . .
141 . .

C4-1/ •• tO.1171·'
C•• I/I-TO·II?I·'
C4.I/I.TO-nl-'

C4-III·To·101·~

I
I

7

I

uaUTOR I,IK II ,lnW , Te ... ·IOO

I4S . .

C4.I/I-TO-IIU-'

4
4
2
I
5

I

tC DC DR TTL BCO.TO.O!C 4.TO_IO·~tNE
IC DC OR TTL SCO-TO_OIC 4.TO-10.L%NE
le.O%PISO,O OHM • a
T~ANa%'TO~ ARRAY
TRANaaTOR ARRAY

012"

us

IUO.O •• I
1120.0 . . 1
IIIO.OU5
1121.0002
1811.0002

.N74\UN
SN74\UN
IIUISI
CUOU
CUOU

Ue
U7

1810.0275
IUO.OU2

I

H2
H3

64100-00606
00180-09104

I

2

S,IIM II ,I2S1'1
I,I1M II ,1251'1
1,17K II ,I2SW
no II ,USIII ,
Sli II ,IIS\OI ~

28480

'1"

RUUTOR
UIUTOR
REltaTOR
REunOR
REUITOR

ItT

I

Mfr Part Number

18"0

20l'~
CAI'AC%TOR-~XD 20P~
CApAC%TOR-~XD ,IU~
CAI'AC%TDR-~XD aop~

,
,

Mfr
Code

IU~.-20' 5aYOC TA
,OIU~ .aO-201 IOOyOC CER
,0IU~ teO-201 100YOC C!~
ISOl'~ •• 51 300YOC M%CA
IOOp~ •• 51 300YOC M%CA

CApAcno~-~xo

'I

I
I
I

Description

~!TWORM.RES

3

I
I

!/!TWDRM.RES 10.a%pl.OK OHM x •
%C MUlR/OATA-SEL TT~ I.TD_I.~%NI a·INI'

3
6

1
5

KEYBOARD SHIELD
KEYBOARD GROUNDING CLIPS

u ....

1414,

all"

0\ III

onu

01'11

01111

Oll'~
28480
28480

C4-1"·TO-IIIR·~

ZlOAIOI
aN7411UN
64100-00606
00180-09104

NOTE
THE PARTS LISTED BELOW HAVE PART
NUMBERS SEPARATE TO THE KEYBOARD
ASSEMBLY.

MP2
MP3
MP4
MP5

5001-2815
5001-2816
1530-1983
1460-1562

8
9
6
8

1
2
2
1

SPACE
SPACE
SPACE
SPACE

BAR
BAR
BAR
BAR

RUBBER GROMMET
PLUNGER
HOUSING
TORSION SPRING

See introduction to this section for ordering information

I/O 6-8

28480
28480
28480
28480

5001-2815
5001-2816
1530-1983
1460-1562

Model 64100A - Replaceable Parts
Table 6-3. Replaceable Parts List (continued)
Reference
Designation
IMI_I

HP Part
Number

c Qty
0

onhOU.
OJ7I-113Q
0371-IIU
OJ7I·U ••
0371.UU

0
7
I

0371-U ••
OJ7I-UU
017I-UIol
017I-U.,
OUI-U70
oJ7I-II7I
o17I-UU
0371·1171
oJ71-Uf.
037I-un
0171-117.
0171-1371
0371-1371
au I-un
0371-1310
O371.U8I
0371-ue2
oUI-un
oJ7I-UU
0371-1385
OJ7I-U . .
0371-U87
OJ7I-un
0171-13 . .
0171_1615
oJ1I-IU.
0371.1631
OUI-IUI
0171-161"
0371-1600

oJ7I-IUI
03f1-1 ...
0171.'US
oJ7I-I ...
0371-1."
0371-1'"
OJ7I-1 . . 7
oJ7I.I'"
oJ7I-l'"
037leIUO
ani-lUI
OUI-IUI
0171-IU3
0J71-IU4
0171-1'"
0311-'."
0371-'U7
0371-I.U
037leIU'
0371-1 . . 0
0371.1 . . 1
037\-".2
0171_1 . . 3
037\-,".
0371-".5
0371-". .
0371_1 •• 7
0371-1."
0371-1 . . "
0371-1.,0
0371-1.,1
0371-1611

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Description

Mfr
Code

Mfr Part Number

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See introduction to this section for ordering information

I/O 6-9

Model 64100A - Replaceable Parts
Table 6-3. Replaceable Parts List (continued)
Reference
Designation

,

c Oty
0

HP Part
Number

Mfr
Code

Description

Mfr Part Number

A8

64100-66524

2

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AEAR

CI
C2
CJ
C4

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OhO.2O!!!!
OhO-20!!!!
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9
9
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CAPAcnOR-FXO
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U480

1'01_0040

JI
JI
JJ
J4

1251_4040
IUI·4U6
0360.1'46
USt-n.6

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CONNECTOR, 24-PIN HP.II
CONNECfOR 2S·PIN F D IUBMIN (RS-232)
BARRIER I~OCK .·TERM PC BoARD PO~YP
CONNECfOR n.PIN F 0 .UIMIN (RS-232)

21410
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75382
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1251.4040
1251-""6
4693-4
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K2
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0490-0617
0490-0617
0490-0617

14

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;? fl41i 0
28480
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0490"'0617
0490·..·0617

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1 0360·1706

9

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18480

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QI

1154.0215
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fRANII.TOR NPN II PDaJSOMW FTaJOOMHZ
TRANSISTOR NPN II D'R~ PDa!lOOMW

04713
04711

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R2

0757-0280
0757-0280

2

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24546

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REUnOR 100 II .IISW , TCaO •• IOO
RuraioR 100.11 .12!lW F TCaOt.IOO
R!lInOR 10 II ,I25W F TCaO •• IOO
~UUTOR 10 II .12SW , TCaO •• IOo
RUUTOR 10 II ~12SW , TCaO •• IOO

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RUreTOR
RElInOR
R!l%nOIl
R!UnOR

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R!lUTOR 10 II ,IISW

82

3101-1974
3101-2102

8 '

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U4
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U7
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1810.2051
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1110.0298
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U12
U13
U14

1200-0607
1200-0607
1820-1917
1810-0307

0
0
1
0

1
2

IC SOCKET, 16 PIN
IC SOCKET, 16 PIN
IC BFR TTL LS LINE DRVR OCTL
CNDT JUMPER MODULE, 16 PIN

loll

8120-3771

2.

1

RIBBON CABLE, REAR PANEL

61

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5

2

9
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2

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,olUF .10-201 IOOYDC CER
,OIUF •• 0-201 100yDC CER
IUF.-IOI SOyDC fA

;250MA
250MA

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10 II ,lUll
10 II ,lUll
10 II ,125W
10 II ,I2!1W
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TC_O.·JOO
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TCaOt-100
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21410

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21410
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28480

3101-"1974

6

1
1

28480

3101-2102

1810.2051
1110.105.

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IC MISC TTL • QUAD

18410
28410

IUO.zO!18
\8Io.z051

1200-0607
1200-0607

0

1820·205.

0

IC SOCKET, 16 PIN
IC SOCKET, 16 PIN

3

IC

28410

luo-Use

28410
01111
01121
01121
01121

1120-2Ose
210AUI
210AUI
210A241
IIOU41

28480
28480
01295
28480

1200-0607
1200-0607
8N74LS240N
1810-0307

28480

8120 .... 3771

3

3

6j

4

a
2

.WrTeM.I~

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IC MIIC TTL
NeTWORK.RU
NeTWORK.REI
NETwORK.REa
NETWORK·RES

• QUAD
• QUAD
10.1%'''0.0
10-11'610,0
10-I%P240,O
10.I%P240,O

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OHM X
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,

See introdl,lction to this section for ordering information

I/O 6-10

C4_I/I.TO·IORO.~

C4.III.tO.1 ORO.~

IU46

1200-0607
1200-0607

Model 64100A - Manual Backdating

SECTION VII

MANUAL BACKDATING

7-1.

INTRODUCTION.

7-2. There is no backdating information for the I/O chapter at the publication
of this manual.

I/O 7-1/(7-2 blank)

Model 64100A - Service
SECTION VIII
SERVICE
8-1. INTRODUCTION.
8-2. This section contains the theory-of-operation for the I/O circuits.
The
first part discusses the block diagram functions while the second part
elaborates on these functions by referring to detailed circuit schematics and
other aids such as truth tables and timing diagrams.
8-3. BLOCK DIAGRAM DESCRIPTIONS.
8-4. GENERAL. The I/O circuits are contained on the I/O Control, Keyboard and
Rear-panel PC boards (see figure 8-3).
The I/O Control PC board contains the
control and handshake circuits for communicating over the HP-IB link to
the disc and printer and the RS-232C link to the various peripheral devices
connected to this bus. The I/O board also contains circuits necessary for:
1. Processing the various interrupts from the keyboard,
RS-232 and HP-IB circuits.

2. Driving the beeper.
3. Allowing the CPU to select and interchange data with any
of the sev~ral PC boards in the card cage.
4. Monitoring line sync and power fail status and providing
such information to the CPU.

8-5. The I/O circuits are divided into four major functional areas on Figure
8-3: (1) I/O Control (upper left on the block diagram), (2) Keyboard Control
(lower left), (3) HP-IB Control (upper right), and (4) RS-232 Control (lower
right).
8-6. I/O CONTROL SECTION.

8-7. The I/O Control section provides most of the control functions for the
other three I/O sections (i.e., HP-IB, RS-232 and Keyboard) and also serves as
the data and interrupt service interface between the CPU and the other three
I/O sections.
Interfacing between the CPU and the I/O control circuits is
accomplished via the I/O Bus and Motherboard connector J1.
Interfacing with
the internal I/O sections is accomplished via the internal buffered I/O bus and
discrete lines (i.e., the peripheral addresses and interrupt signals shown on
figure 8-3).

I/O 8-1

Model 64100A - Service
8-8. I/O BUS. The CPU communicates with the I/O circuits primarily via the I/O
bus.
This bus is a traditional bus in that it carries data, address and
control information. The data bus is a 16-bit bi-directional bus that carries
data to and from the HP-IB interface chip, the RS232 interface chip, and the
Low Priority Interrupt circuit.
This bus also receives data from the keyboard
circuits and switch mode status from the RS-232 circuits.
8-9. The address portion of the I/O bus consists of 4-bits of peripheral
address (LPAO-LPA3).
These bits allow up to 16 peripheral addresses to be
decoded (by the Peripheral Address Decoder) which allows the CPU to select the
various I/O circuits it wants to talk to.
However, only 9 of the possible 16
peripheral addresses are used in the 64000 system (see Table 8-1).
Table 8-1. I/O Internal Addresses
MNEMONIC
LKYBD
L(DELTA)T
LRSWR
LRSRD
LHP-IB
LBEEP
LSSEL
LIMASK
LPFS

FUNCTION
Keyboard Address
Time Interval Address
RS-232 Write Address
RS-232 Read Address
HP-IB Select and Read/Write Control Address
Beeper Select Address
Card Slot Select Address
Sets Interrupt Mask Latch Address
Power Fail Set Address

8-10. BEEPER, SA INTERVAL, CARD ID ENABLE AND DISPLAY ENABLE. In addition to
the nine peripheral addresses, there are two interface control addresses (LIC1
and LIC2) that the CPU uses to control the beeper, the signature analyzer
start-stop signals (SA INT) and the card ID address decoder.
This latter
circuit produces the ID enable signal (LIDEN) that is distributed to each of
the option card slots where it enables the various option PC boards to
communicate their unique identification codes to the CPU.
8-11. The output of the Beeper Decoder is sent to the Display Enable Latch and
the beeper circuits.
When the first beeper signal is generated (by signals
LBEEP, LDOur, LICl and LIC2), a binary "1" is latched into the display enable
latch and causes the CRT to be activated by HDE (display enable).
This latch
keeps the CRT display enabled until power is turned off or when a power failure
is eminent as indicated by the high priority interrupt flag (LIR15). This flag
resets the display enable latch causing the CRT to go blank and also sets the
high priority interrupt latch (when interrogated by peripheral address Power
Fail Set, LPFS). This in turn causes the high priority interrupt signal (LIRH)
to be sent to the CPU (via the I/O bus) .

I/O 8-2

Model 64100A - Service
8-12. LOW PRIORITY INTERRUPT LOGIC.
The low priority interrupt circuitry is a
series of gates and latches.
By generating a particular peripheral address
(LKYB, LRSRD, LRSWR, or LBEEP), the CPU can turn on I/O Data Buffers u2/u4. It
writes an interrupt mask into this logic, and then the low priority interrupt
(LIRL) will only be generated when one of the enabled (unmasked) circuits
requests an interrupt.
When this happens, the CPU again enables I/O Data
Buf'fers u2/u4 and reads the "Interrupt IDOl to determine which circuits have
requested the interrupts.
Once it determines this, the CPU then writes out
another peripheral address to the device which will service the circuit that
requested the interrupt.
8-13. DELTA TIME LATCH.
This circuit monitors (counts) the 60Hz line sync
pulses (LINE SYNC) from the power supply and simultaneously sends a low level
interrupt (HIR2) to the CPU during each sync pulse.
If the CPU becomes
"lost" (Le., loses track of time) and doesn't respond with peripheral address
L(DELTA)T before 128 pulses have been counted (approx. 2.2 seconds), the Delta
Time Latch circuit triggers the Auto Reset circuit which in turn generates the
LPOP reset signal. LPOP is routed to the seven I/O circuits listed below where
it serves as a reset pulse:
1.

2.

3.
4.
5.
6.

7.

SA Latch
High Priority Interrupt Latch
Power Fail Latch
Delta-Time Counters
Slot-Select Address Latch
Interrupt Mask Latch
PHI Address Latch

8-14. HIGH PRIORITY INTERRUPT LATCH.
Whenever power is about to fail, the
Power Supply sends interrupt request signal LIR15 to the high priority
interrupt latch.
This produces high priority interrupt request LIRH which is
sent to the CPU to inform it that power is failing. The CPU then responds with
the appropriate address code for generating the power fail set peripheral
addres s (LPFS).
8-15. POWER FAIL SET LATCH. The power fail set address (LPFS) sets the power
fail set latch thus producing the power fail signal LPFAIL.
This signal is
sent to the auto-reset circuits where it disables the output from the deltatime counters. The purpose of disabling the delta-time counters is to inhibit
the generation of power-on pulse LPOP.
This in turn prevents the CPU cicuits
from being reset during a power-fail condition.
8-16. AUTO RESET CIRCUIT.
This circuit produces the power-on signal (LPOP)
whenever either of two events occur:
(1) when the delta-time counters are
allowed to time-out due to the CPU taking too long to respond to the sync-pulse
interrupts, and (2) when the processor reset switch is pressed. The delta-time
feature is disabled by either the power-fail signal (LPFAIL) or by the AutoReset Enable jumper E8 (on the I/O board).

I/O 8-3

Model 64100A - Service
8-17. I/O DATA BUFFERS.
The I/O data buffers are bi-directional transceivers
that interface the I/O bus with the buffered I/O bus. These transceivers allow
communication between the CPU and the various I/O circuits.
8-18. SLOT SELECT ADDRESS LATCH AND DECODER.
This circuitry provides the
ability to address up to 48K specific locations on each of the option cards
occupying any of the 10 option card slots.
This is accomplished by decoding
four I/O address bits from the CPU (the other two bits indicated on figure 8-3
are for enabling the decoder chip) thus producing a total capability of
selecting 1 of 16 outputs (only 11 are used).
Each of these 11 card-slot
select signals (LSSO thru LSSI0) is routed to a specific card slot in the
card cage where it causes that particular card slot to be enabled.
Slot Select
signal LSSI0 is routed to the Display Controller and CPU card slots but has no
function.
8-19.

HP-IB CONTROL SECTION.

8-20. GENERAL. This circuitry allows the CPU to communicate over the HewlettPackard Interface Bus (HP-IB) with peripheral devices that are designed to be
compatible with the IEEE 488 general purpose interface bus. However, since the
64000 operating system (software) incorporates instruction code only for the HP
7910, 7906, 7920, 7908 and 7925 disc Drives and the HP 2631A and 2608 Line
Printers. Thus, these are the only peripheral devices that can be driven from
the HP-IB bus.
8-21. CONTROL LOGIC, ADDRESS LATCH AND STATUS BUFFER.
The Control Logic
decodes four control signals (LICI, LIC2, LDOUT, and LBEEP) and produces a set
of outputs that control the selection of Status Buffer U12, Address Latch U11,
and PHI chip U20.
Address latch U11 stores I/O bits 8-11 which are used to
select specific registers internal to the PHI chip.
Status Buffer U12 reads
(stores) the status of Rear-panel Switch Sl.
Switch Sl controls the system
"boot-up" source (Le., disc, local mass storage, or performance verification).
Switch Sl also selects the desired ID address for the subject mainframe (see
figure 8-2).
Switches S2 and S3 determine controller (MASTER) or noncontroller (SLAVE) station status.
8-22. PHI CHIP U20.
The acronym "PHI" stands for Processor to HP-IB
Interface.
This chip is a self-contained microcontroller that adapts a wide
variety of microprocessor chips to the HP-IB bus.
Some of the general
characteristics of the PHI chip are:
(1) data is sent at the rate of the
slowest listener (up to one megabyte per second), (2) data transfer is
asynchronous, and (3) more than one peripheral device can accept data
simultaneously.
To ensure that the transfer of data is accomplished in an
orderly manner, a set of three "handshake" signals are used: Data Valid (DAV) ,
Ready for Data (RFD) , and Data Accepted (DAC). These three handshake signals
ensure: (1) that each listener is ready to accept data, (2) that the data on
the data bus in valid, and (3) that the data has been accepted by all
listeners.

I/O 8-4

Model 64100A - Service
8-23.
BUFFERS/INVERTORS.
HP-IB Data XCVRS, and Bus Loads.
The transmit
control signals from the PHI chip are buffered and inverted by U9 before being
sent to the HP-IB Data Transceivers.
These signals control channel selection
and the direction of data flow thru the data transceivers.
The HP-IB Data
Transceivers are bi-directional and handle three types of signals:
(1) HP-IB
data, (2) handshake, and (3) bus management.
The HP-IB data consists of
instructions and data that are passed back and forth between the CPU and the
peripheral devices on the HP-IB bus (i.e., printer or disc).
The handshake
signals were discussed above and are used to control and coordinate the
transfer of data.
The Bus Management signals consist of five control/status
signals that are used for such things as activating all peripheral devices at
the same time, clearing the interface, service request, etc.
The Bus Loads
block represents a resistive load that can be applied or removed from the data
lines.
The two states are controlled by switches S2 and S3. In one position,
the subject Mainframe is configured as the "master" controller station and in
the other position it is a "slave" non-controller station.
8-24.

RS-232 CONTROL SECTION.

8-25. GENERAL.
This circuitr,y allows the CPU to communicate over the RS-232C
serial interface bus to peripheral devices that require this type of interface.
In addition, this section also allows selecting the "current loop" mode of
operation for interfacing with teletypes and other peripherals that require
this type of electrical interface.
8-26. RS-232C STANDARD.
Most voltage interfaces in North America conform to
the EIA RS-232C Interface Standard (the corresponding European standard is
CCITT v24).
This standard specifies a 25-pin connector as the standard
interface in datacomm networks, with lettered pin assignments for ground, data,
control and timing circuits.
The standard also specifies the mechanical and
electrical requirements of an interface, within an operating range of 0 to
20,000 bps in bit-serial operation, synchronous or asynchronous.
It provides
interface compatibility between many types of equipment and manufacturers and
thus provides great flexibility in the selection of equipment for datacomm
networks.
8-27. BUFFER AND RS-232 MODE SWITCHES.
Buffer U35 reads the status of RS-232
Mode Switches s4 and S3 on the I/O board.
Switch S3 controls the selection of
the RS-232 or current loop modes while s4 controls the following five
parameters (see figure 8-1):
1. The number of stop bits (1, 1.5 or 2)
2. Type of parity (odd, even or none)
3. Character length (5-8 bits)
4. Baud rate factor (Xl or X16)
5. Terminal or Modem

I/O 8-5

Model 64100A - Service
8-28. BAUD RATE SWITCHES AND GENERATOR. Switch S5 on the I/O board allows the
operator to select the baud rate at which the RS-232 data is transmitted and
received by the RS-232 circuitry.
Sixteen discrete rates can be selected
within the range of 50 to 19200 baud (See figure 8-1).
Switch S5 has five
segments. The first of which selects full duplex or half duplex operation while
the remaining four segments control the baud rate by selecting the operating
frequency of Baud Rate Generator u48. The output of the Baud Rate Generator is
applied to a divider circuit that is controlled by a segment of switch s4 to
select the baud rate factor (Xl or X16).
8-29. CLOCK SOURCE SWITCH AND JUMPERS.
The 64100A RS-232 circuits have the
capability to drive or receive both the TX and RX clocks independently.
Control of these options is provided by switch S2, and jumpers E1 and E2, on
the I/O board.
This option allows the operator to select the source of
transmit and receive clocks for the USART chip U28.
The dual SPDT dip switch
S2 selects, independently for TX and RX, whether the clock for the USART is
supplied by the internal baud rate generator or from an external remote
terminal or modem type equipment.
The following is how the switch and jumpers
must be configured to take advantage of this option:

a. When the RXCLK switch is set for internal clock, the E1 jumper does
the following:
1. If the RS-232 cable is connected to the PERIPHERAL connector,
on the Rear-panel, placing a jumper from A to B will connect
the TXCLK on J2, pin 15.
2. If the RS-232 cable is connected to the MODEM connector,
placing a jumper from B to C will supply the identical
clock on the RXCLK output on J4, pin 17.
3. If an output clock is not desired then no jumper is required.

b. When the TXCLK switch is set for internal clock, the E2 jumper
does the following:
1. With the RS-232 cable connected to the PERIPHERAL connector,
on the Rear-panel board, placing a jumper from A to B
supply the RXCLK on J2, pin 17.
2. With the RS-232 cable connected to the MODEM connector,
placing· a jumper from A to C will supply the clock on
the TXCLK output of J4, pin 15.
3. If an output clock is not desired then no jumper is required.

I/O 8-6

Model 64100A - Service
c. If the RXCLK switch is in the external clock position then the
E1 jumper does the following:
1. With the RS-232 cable connected to the PERIPHERAL connector,
a jumper from A to C is required to receive TXCLK from J2,
pin 15.
2. If the RS-232 cable is connected to the MODEM connector, no
jumper is required to receive RXCLK from J4, pin 17.
d. With the TXCLK switch set to external clock then the E2 jumper
does the following:
1. With the RS-232 cable connected to the PERIPHERAL connector,
a jumper from A to C is required to receive RXCLK from J2,
pin 17.
2. If the RS-232 cable is connected to the MODEM connector, a
jumper is not required to' receive TXCLK from J4, pin 15.
NOTE

The E1 jumper corresponds with the RX clock switch.
E2 jumper corresponds with the TX clock switch.

B*

E1

E2

A*

A*
C*

B*

EXT

r,

I
I
I
I
L ...

C*

r1

I
I

I
I

1-J

INT

The

E2

S2

[;J

TX clock

0

RX clock

8-30. MODE SELECT AND DRIVE.
The RS-232C transmit and receive data passes
through the mode select switches and drive circuitry. The mode select switches
allow the operator to select: (1) Current Loop or RS-232, (2) Full Duplex or
Half Duplex, and (3) 20mA or 60mA (current loop) modes of operation.
8-31. LOOP-BACK TEST FEATURE.
To test the RS-232 circuits during performance
verification, the transmitted data and handshake signals are "looped-back" to
the RS-232 circuits as "receive" data. This feature is under software control
and is used during the RS-232 segment of the PV test.

I/O 8-7

Model 64100A - Service

8-32.

KEYBOARD CONTROL SECTION.

8-33. GENERAL.
This circuitry allows the operator to interface with the CPU
and Operating System Software via the Mainframe Keyboard.
The Keyboard
consists of four blocks of keys: (1) a 128-character ASCII main keyboard, (2)
10 edit keys, (3) four special function keys, and (4) eight softkeys. The
function of these keys are described in the 64000 system operating manual.
8-34. DATA BUFFER.
This 8-line buffer connects the 7-bit key address code
from the Keyboard Address Counter and the key status bit (bit 7) onto the
internal I/O bus when the CPU produces peripheral address LKYBD.
This is a
uni-directional buffer and is enabled as a result of an interrupt request from
the keyboard circuits (i.e., a change in key status).
8-35. BASIC CONCEPT.
The State Machine is clocked by HSTB from the CPU and
sequentially generates a series of strobe signals that: (1) clock the Keyboard
Strobe Generator, (2) clock the Keyboard Address Counter, (3) activate the
Past State Memory and control the read/write functions, and (4) clock
he
interrupt Latches.
The general concept is to sequentially step the Keyboard
Address Counter through its entire counting range of 255 and applying this
count code simultaneously to a one-bit wide RAM (Past State Memory) and also to
a 1-of-16 column selector (U1/U2) and a 1-of-8 row selector (U7).
8-36. The row and column selectors select a X-Y coordinate on the keyboard
which in effect reads the status of a specific key for each step of the address
code. This status information (i.e., key up or key down) is encoded in signal
HKYDN which is sent to the interrupt latches where it is stored momentarily.
The chip select signal from the state Machine causes the "present-state" key
status to be stored in the RAM in a specific location that is a function of the
address code of the current key being interrogated.
When the Keyboard Address
Counter completes a complete cycle, the address location that initially stored
the "present state" data is now caused to read this data out of RAM as "past
state" data.
The past state status is compared with the present state status
by the interrupt Latches.
If the present state and past state are not the
same, this indicates that the key status has changed and an interrupt request
(HIRKB) is sent to the CPU. Simultaneously, a stop signal is sent to the State
Machine which causes the Address Counter to stop on the address of the subject
key.
When it has time, the CPU responds with the keyboard peripheral address
(LKYBD) which enables Data Buffer U27 and puts the address code on the I/O bus
so that the CPU can determine which key is involved. LKYBD also resets the
interrupt Latches thus enabling the State Machine and allowing the address
cycling to begin again.
8-37. An lin-key" scanning techinque is used when scanning the keyboard.
This
means that any number of keys can be depressed or released in any order or at
any time and the keyboard interrupts will be processed rapidly enough to
prevent missing any status changes.

I/O 8-8

Model 64100A - Service

20 (
MA

)

--,
,, ,
I
I
I
I

I
I

,,
,,

I
I
I
I
I
I

LJ

r--

RS-232
CUR LOOP
DRV SEL
Sl

)

EXT (

' ,
~~

TXCLK

I
I
I

I
I

I

L...J

RXCLK

CUR
LOOP

I
,
I
I
I
I
I
I
I_-I

tl
~

INT

RS-232
CLK SOURCE
SEL
S2

I
I

S4 BITS
6
5

RS-232
CURRENT LOOP
SELECT
S3

0
0
1
1

0
1
0
1

o

CHAR
BITS

0
0
1
1

5
6
7
8

1(

0
0
EVEN/ODD PARITY - - E 0
PARITY ENABLE ~ 0
0
CHAR LENGTH
0
BAUD RATE FACTOR -X16 0
MODEM 0
~O
NO. STOP BITS{==

BAUD RATE
TRUTH TABLE FOR S5
RATE
S5 S4 S3 S2
0 0
0
50
75
0 0 0 1
0 0 1 0
110
0 0 1 1
134.5
1(
0 1
0
150
300
0 1 0 1
0 1 1 0
600
0 1 I HALF DUPLEX
FULL DUPLEX 1200
0 1 1 1
1 0
0
1800
2 I
0
1 0 0 1
2000
3 I
0
1 0 1 0
2400
BAun{
1 0 1 1
3600
RATE
0 4 I
4800
1 1
0
0 5 I
1 1 0 1
7200
1 1 1 0
9600
1 1 1 1
9200
RS-232
BAUD RATE
AND
RTS SEL
55

o

NO. OF STOP BITS
TRUTH TABLE
STOP
S4 BITS
BITS
2
1

CHAR LENGTH
TRUTH TABLE

r-.

I
I

1U

RS-232

60
MA

0
1
0
1

INVALID
1
1.5
2

)0
1
2
3
4
5
6
7
8

I
I
I
I
I
I
I
I

0
D

RS-232
MODE
SEL
S4

X1
TERMINAL

o

o

Figure 8-1. I/O PCB Switch Locations and Functions

I/O 8-9

Model 64100A - Service

S2

S1

S3

BOOT-UP SOURCE

J 1 HP-I B ------l---::.~~i\Ii]
, . ._ _ _ _ _ RS232-C _ _ _ _

~

CURRENT LOOP

f

TO MODEM

FROM TTYlr TO
SAt:;

RTN

TtY-1

I SACRfN

i

SElECrOR IN$lO£
O'lIOaOAIlo

I

TO TERMINAL

J2

I
J3

J4

BOOT-UP SOURCE
ADDRESSES
MSB

a
a

LSB CONTROL
a SYS BUS ( DISC)
1 LOCAL MASS STORAGE TALK ONLY
a LOCAL MASS STORAGE ADDRESSABLE
PERFORMANCE VERIFICATION

MAINFRAME
ADDRESSES
NOT
USED

MSB

00

a

a

00

a

a

00
00
00
00
00
00

a
a

LSB

a

ADDRESS

a

NOT VALID

- - --

--------- --------a

2

1

1

a
a

a

3
4
5
6
7

1

a

VALID
MAINFRAME
ADDRESSES

Figure 8-2. Rear-panel Switch Locations and Functions

I/O 8-10

Model 64100A - Service

1-----I/O PC BOARD
TO CPU

HPIB CONTROL
~

50

I
I

~

P
LT

Iio BUS

~

, '"
w
"''''

:r:

N

0::
~

u

~

I/O CONTROL

H

..J

..J

,2

I

J
DECODER &
51" LATCH
U32A,45A

I

I
I

f-------j

I

I
I

00::
"'0
0..0

IIODRESS
LIITCH
P/O U44

I

~

....
..J

LPFS

DISPLAY
ENflBLE
LflTCH
U42

J
HI PRI

~

ADDRESS
DECODER
U45B

I

INTR
LATCH t--U6,16,
2911,30,
55

I

I

......J

I

I
I

86

~
>=

w

'"

0

0::

0

'"

I

'",

z

~

w

:;
~

J

LKYBD
L6T
LRSWR
LRSRD
LHPIB
LBEEP
LSSEL
L1MIISK
LPFS

..J

MOTHERBOARO

~

I

~ LIMASK
LOW
HI R.?-, PRIORITY
LOGIC
HIR4
HIR3
A
HI R1
INTERRUPT MASK
HIR2
'J
OUT
INTERRUPT ID

~
LDFS

ADDRESS BITS
(SELECT SIGNlIlS)

3

IfI

~
~

JJ

/

It}

z

........
:r: I

PERIHERIIL IIDDR
DECODER
U5,5,17,18,31

BEEPER CKTS
U33,44,
03,4,5

0

"'".
0::0::

~5~!

-1:3 ~I

, 4L_

L:1SEL

u

col

>-

LIRLT

..J'"

~

Sill

INT

'"

>-

I

POIIER FAIL
LIITCH
U32B

LPOP

I/O OIlTIl
BUFFERS
U2,4

~

dJ

I r----j

IIUTO RESET
U43, 51, 52

J

~

z

a

0..
..J

"'w
....
00::,
"'DO

>-0

KEYBOARD
CONTROl

~'"

r

I DATil UZl
~FFER

LKYBO

U25. 38. 40

HSTB

8

-=l ]
lI Tr
INTERRUPT
LATCHES

HIRO

PIO MDTHERBOIIRO
,---

STIITE
MIICHINE
U38,39

jfE

....
>-

'"'"

'"
..J

'"
PIIST STIITE
PRESENT
STIITE

J

PAST STIITE
MEMORY (RAM)
U26

9

HKYONJ

,

J KEYBOARD J
CLK'IIDDRESS CNTR
'I U34

<

"'

~:r:

+~v

--

I

ROil
SELECT
U7

A

8

I
I

KEYBOARD
MATRIX
8 X 16

1

~~7

<",>

-

I

I

1

I

I

I

'"
<.:>''""

z
....

I

It I

'I

~

KEYBOIIRO
CIIBLE

I

'l

1--------

I
I

I
I

}=4

~

A

HPIB DIITII BUS

B

"

1
>z
w

I '"

XCVR
CNTL
HPIB DATA
XCVRS

::J

0::

I '"z
I ....

' B7-

I

>-

BUS LOIIDS

J

W

0..

>-

>-

....
"'0

Zz
"'<
>=",

!goO

'"":r:

>-

A

8

"

I

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,

,

z ....
....
"'<
WI

'"

f'.-

.Jl

V

<.:>'
"
"'0

Zz
<",
>=:r:

~

I

/I

HPIB CONTROL BUS
~

8
v,

'"

I-

J

~oO

ID

ID

I
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r

I

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,

-'L~I'-'C"'l_ _ _ _ _ _ _ _ _ _ _ _ ____7l:::

B 1S B-15

PID

U5

1<]
I

1
1
MODEM~~A-...~~"'~~~--_+_r------~,
CONTROL~'J~4--~R~T~S~C~TS~DuT~5£C~S~R~-I-~--------./
v

KI ~3.

I

a~

,---; "'u
:i'

BUFFER
U35

Fyi

RSs-W2llcHMEOSDE
54,P/0 S3

I

SERIIIL
DflTIl

J MODE SELECT I I

4

.---""'---, CLK
BAUD RATE 1-"='--------'
GENERATOR
RATE
U43,48,49,50

l

CRI

t

5

"v

4

"

I

I

&

RXCLK

I
I
(

HIR5

J4

TO REMOTE
TERMINIIL

RS-232 RXD/TxJ

I

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I
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I

I
(

~(-~H~IR=6~----------------~

TO REMOTE
MODEM

CURRENT
LOOP TO TTY

RCRDY f - - - - - - ,

CLOCK SOURCE
XMI flREC
SW S2,
& JUMPERS 1t-------7tCLOCKS
E1, 2
'--_ _ _ _ _--'

I

J2

I

TXRDY f - - - - ,

I
I

I

01.

CURRENT LOOP XMIT IRCV
TXD/RXD ~-----7I
& DRIVE
.1--++-----"-''''''''-'-'-'-''''''''-'---'''-'''--'-'-'-'''-'-----------------7
J3
'IU19,Q1,2,Sl,21 I
USflRT
U30

BAUD RATE
SWITCHES
S5

/I

"',~

RD

' - -_ _ _ _..J

I

DRIVE

..J

LRSWR -1I"'R-'----_ _ _ _ _ _ _ _ _ _ _ _ _ ____7l~ ~

tL

I
I

RS-Z3Z CONTROL

'--_ _ _ _~T"'E'-"RH/MOD TXCLK
LKBCLK JCURRENT RIIMP
GENERIITOR
Ql,2,3,4

BUFFERS &
INVERTERS

>-

Zw
....
>=<

l'

KEYBOIIRO 1
ClK" STROBE
GEN 1
U33

-t-v HPIB
DATA

u

PHI CHIP
U20

I

-<57
COLUMN
SELECT
U1,2

I

RLYCNTL

V(REF)

I

I

1

L8i'

~ '"
uw
.-

HKIIO-3

REF VOLT
R9,10,l!

><~
u

0..0::

LRSRO

H
,

u>-

::JLL

HIR7

~

~

KEYBOARD ASSY

~
c---

CHIP SELECT

L

7

--

0:: 0
>0::

I

'I

w

~-------------------~~
PflR~LLEL
; = = - - - - - - - - - - - - - - - - - - - - - - - v CPU OflTA

,--I

I-------~

..J

REG
IIOOR

"

~
CPU ADDRESS

,

7

T

001

BIT 8

HPIB
DATil

I

,

BEEPER L--l.

0",
0::",

CONTROL
LOGIC
U7,16A

d=+

CPU DATil
& REG
SELECT

I

I

REIIR PIINEL
SWITCHES

a

,.c.,

~---::,.

"ADDRESS
LflTCH
U11

v

I

'=*

"I

J

~

~

0..
0
0..
..J

LL

:::0

ADDRESS
DECODER
U31,43,53

~

:;:

8-11

I
R TS An-7

kB

I
I

.----J

LBEEP

J

6

It)

..J

z

in

BIT

~4

STIITUS
BUFFER
U12

>-

-1

LPOP1~

(RESEll

u

~

1

'1

LIC1,2"

IIDDRESS
LIITCH
PID U44

LSSEL

T

L6T

r«----::::--------~l~ :,:, _, ""

6

0::

6 T LflTCH
U29B,37,50
C
J

LR5RD
LBEEP

BUFFEREO I/O BUS

N

....
I

~

LKYBD
LHPIB

I

-,

REAR PANEL PC BOARD

REIIR
PIINEL
CIIBLE

I

J2

TO REMOTE
TERMINIIL

I
I

I
I

_________________
~ __ ~

._--- - - ----- - - ---- -

- ---- Figure 8-3.
I/O Block Diagram
I/O 8-11

Model 64100A - Service

8-38.

SCHEMATIC DESCRIPTIONS.

8-39. This section provides additional detailed information concerning the I/O
circuits that was not appropriate for the Block Diagram description.
This
includes more details on how the various circuits perform the specific
functions.
Logic truth tables and timing diagrams are used to illustrate some
of the relationships. Schematics are provided on 5 sheets, figure 8-14.
8-40. LOGIC CONVENTION.
The positive logic convention is used for logic
variables and the circuits comprising the 64100A I/O circuits. This convention
defines a logic 1 as the more positive voltage (high) and a logic 0 as the more
negative voltage (low).
Most integrated circuit logic devices in the 64100A
are 7400 devices and ultilize transistor-to-transistor logic (TTL) levels.
Ideally, the low and high voltage levels for 7400 devices are OV and +5V,
respectively.
But due to voltage drops over the interconnecting PC board
traces and other causes, the actual levels can vary from these ideal values.
Therefore, the voltage levels for a logic 1 and 0 are defined as follows:
TTL VOLTAGE LEVELS
BINARY

QUANTITY

Input
Input
Output
Output

0
1
0
1

VOLTAGE
<
:>

<
:>

LIMIT

o.8v
2.0V

o.4v
2.4v

8-41. MNEMONICS.
Signals in the 64100A have been assigned mnemonics that
describe the active state and function of the signal line (see table 8-12). A
prefix letter (H or L) or superscript bar is used to indicate the active state
of the signal and the remaining letters indicate its function. A "H" prefix or
the absence of a bar indicates that the function is active in the "high" state;
a "L" prefix or the presence of a bar above a mnemonic indicates that the
function is active in the low state.
8-42. SIGNATURE ANALYSIS LOOPS. The letters on the I/O schematics identify
circuit nodes where signature analysis "signatures" have been taken to
aid
in troubleshooting the logic circuits.
Refer to Section IV for
instructions on how to use signature analysis for troubleshooting.
8-43.

I/O CONTROL.

8-44. BEEPER DECODER u45A (see figure 8-14, sheet 1)
u45A is a 2-to-4 line decoder that decodes the LDOUT and LIC1 commands from the
CPU for the purpose of generating the SA start-stop interval and activating the
beeper circuits.
Peripheral command LBEEP from U17 enables this decoder when
the CPU Operating System has determined the proper conditions exist. Table 8-2
is the Truth Table for u45A.

I/O 8-12

Model 64100A - Service

Table 8-2. Beeper Decoder u45A Truth Table
G
LBEEP

F1
LIC1

F2
LDOUT

Pin 15

Pin 13

Pin 14

Output Pins
12

10

11

9

Function Activated

1

X

X

1

1

1

1

None

a

1

a

1

1

0

1

Beeper & Display

a

1

1

1

1

1

0

S/A Interval

8-45. BEEPER START PULSE GEN U33.
Monostable multivibrator U33 is triggered
when LBEEP and LIC1 are true and LDOUT is false (see table 8-2).
When
triggered, U33 generates a pulse approximately 220 milliseconds in duration
which turns Q3 on and causes C33 to rapidly charge up to +5 Vdc thru R24. When
the U33 output pulse terminates, C33 exponentially discharges thru R25 thus
creating a pulse that has a steep leading edge and a sloping trailing edge
which causes the beeper to produce a "bell" sound. This pulse turns on Q4 thus
providing +5 Vdc (HBON) to one side of the beeper speaker.
8-46. 2500 HZ TONE GENERATOR U41.
Timer U41 is a monolithic timing circuit
that is operated in the astable (free running) mode to generate a 2500 Hz tone.
The tone frequency is determined by R29, R30 and C35.
The output of U41
controls Q5 which in turn modulates the five volts, appearing across R27, with
the 2500 Hz tone signal.
8-47. DISPLAY ENABLE LATCH U42.
Latch U42 is set simultaneously with the
activation of the Beeper Start Pulse Generator.
When U42 is set, the Display
On signal (HOE) is produced which is sent to the Display Driver PCB to activate
the CRT display.
U42 is reset whenever system power is cycled OFF and ON and
whenever a power interrupt (LIR15) is generated by the mainframe power supply.
8-48. SA LATCH U32A.
command LIC2 as its D
(see table 8-2). The
SA start-stop signal
power-on pulse LPOP.

This is one-half of a D-type flip-flop that has interface
input and is clocked by the pin 9 output of Decoder u45A
output of U32A is fed to test point TP2 and serves as the
for troubleshooting the 1/0 circuits.
U32A is reset by

8-49. CARD ID LATCH AND DECODER u44 AND u45B. Latch u44 is a D-type flipflop,
a portion of which is used for storing interface commands LIC1 and LIC2 when
the CPU causes peripheral address LSSEL to occur. The remaining segment of u44
is used for latching the address bits for generating the card slot select
commands (see Slot Select circuit description).

1/0 8-13

Model 64100A - Service
8-50. The two outputs on pins 12 and 15 of u44 are fed to decoder u45B where
they are decoded into four discrete signals:
ID Enable (LIDEN) and MAP
commands LMAP1 thru LMAP3.
Signal LIDEN is output on pin 67 of J1 and enables
the option card ID circuits for the PROM Controller, Emulation Memory Control,
Logic Anayzer,
and Emulation
Control that may be located in any of
the ten option card slots.
The three MAP signals serve as address lines for
future expansion of the option card memory capabilities.
Table 8-3 is the
truth table for u45B.
Table 8-3.
LIC2

LIC1

0
0
1
1

0
1

Card ID Decoder u45B Truth Table
LIDEN

LMAP1
1

0
1
1
1

0

1

0

1
1

LMAP2
1
1
0
1

LMAP3
1
1
1
0

8-51. PERIPHERAL DECODER ENABLE LOGIC U5, u6, U31. The I/O strobe (LIOSB),
Interrupt (LINT), Data Out Delayed (LDOUTD), and Data Out (LDOUT) commands from
the CPU are ANDed by U31B and U31C and then ORed by U31D to produce an enable
signal for enabling Peripheral Address Decoders U17 and u18.
This enable
signal appears at output pin 12 of U31D and is fed to gate input pin 5 of both
U17 and U18 (Note, however, that the two other gate inputs to U17 and u18 must
also be of the proper state). Table 8-4 is the truth table for the Decoder Enable Logic.
Table 8-4.
LIOSB

LDOUT

o

o

X

X

Decoder Enable Logic Truth Table
LINT
X
1

LDOUTD
X
1

U31D-13 OUTPUT

o

o

U31D-13 = 1 for all other combinations
8-52. PERIPHERAL ADDRESS DECODERS U17, u18. Decoders U17 and U18 decode oneof-eight lines each (for a maximum capability of 16 lines) depending on the
states of the three binary select inputs (pins 1, 2, and 3) and the three
enable inputs (pins 4, 5 and 6). The same address inputs can be used for both
decoder chips because only one chip is enabled at a time.
This is implemented
by feeding peripheral address signal LPA3 to the low true enable input of U18
and to the high true enable input of U17.
This means that U17 and u18 are
never enabled at the same time. Also, note that pin 4 of U17 is tied to ground
thus requiring that only pins 5 and 6 be low for U17 to be enabled.
8-53. Although U17 and U18 have the capability of decoding up to 16 lines,
only 9 are used in the current 64100A system application.
Five of the
peripheral addresses (LKYBD, L(delta)T, LRSWR, LRSRD, and LHPIB) are produced
by u18 and the remaining four addresses (LBEEP, LSSEL, LlMASK, and LPFS) are
produced by U17. Table 8-5 is the truth table for U17 and U18. Notice in this
table that the address selected depends both on the state of the peripheral
addresses binary outputs (LPAO thru LPA2) and also LPA3 which determines which
decoder chip (U17 or U18) is enabled.
I/O 8-14

Model 64100A - Service
Table 8-5. Peripheral Address Decoder
U17/U18 Truth Table
U17/U18

ADDRESS

SELECT

FROM CPU
U17 U17

LPA3

PERIPHERAL ADDRESSES
U18
u18

LPA2 LPAl LPAO
LBEEP LKYBD

U17

HPIB/LPFS

u18

u18

U17

LRSRD

LRSWR

LIMASK

u18

L T/LSSEL

O=HP-IB
1=LPFS

0
0

0
0

0
0

0
0

1
1

1
1

1
1

1
1

O=LRSRD

0

0

1

1

0

1

1

1

O=LRSWR

0

1

0

1

1

0

1

1

1=LIMASK

0

1

1

1

1

1

0

1

O=L T
1=LSSEL

1
1

0
0

1
1

1
1

1
1

1

1

1
1

0
0

1=LBEEP

1

1

0

1

1

1

1

1

O=LKYBD

1

1

1

1

1

1

1

1

8-54. INTERRUPT BUFFER ENABLE LOGIC u16, U30.
Inverters u16F and
u16D together with gates U30A and U30B decode LPA3, LINT and LDOUTD to
produce the Interrupt Buffer Enable signal (LIBE). Table 8-6 is the
truth table for LIBE.

Table 8-6.
LPA3
1

Interrupt Buffer Enable Truth Table
LINT

o

LDOUTD
1

LIBE

o

LIBE = 1 for all other combinations
8-55. HIGH PRIORITY INTERRUPT LATCH U29A.
This latch is a D-type flip-flop
that is clocked by the negative-going edge of Power Fail Interrupt (LIR15) and
set by either LPOP or peripheral address LPFS.

I/O 8-15

Model 64100A - Service
8-56. Latch U29A is set by HPOP at system power-up (or by pressing the Reset
Test switch).
This is done by HPOP passing thru OR gate U30D, invertor U55F
and on to the set input of U29A, pin 4.
Latch U29A remains in the set state
until a power fail interrupt (LIR15) occurs. When the power supply senses that
a power failure is eminent, LIR15 goes low which is inverted by U55C before
clocking U29A.
The clocking of U29A causes output pin 6 (HLIRH) to go high
which is inverted by U6G thus producing the high priority (unmaskable)
interrupt signal LIRH.
This signal is sent via the I/O bus to the CPU and informs the controller that power is failing.
8-57. After receiving the message that power is failing, the CPU responds by
writing to Peripheral Address Decoder U17/U18 to produce the Power Fail Set
(LPFS) address. The LPFS bit performs two functions: (1) it sets Power Fail
Latch U32B to disable the LPOP Pulse Generator U52, and (2) it sets High
Priority Interrupt Latch U29A thus canceling the high priority interrupt caused
earlier by LIR15.
8-58. DELTA-T INTERRUPT LATCH U29B.
The 6o/50Hz LINE SYNC signal from the
Power Supply enters on pin 75 of J1 and is buffered by U54F before being
applied to D-type flip-flop U29B and modulo-16 counter U37A.
Latch U29B is
clocked by each positive-going edge of LINE SYNC thus causing the Q output at
U29B-9 to latch high due to the D input of U29B being tied to +5 Vdc.
The Q
output of U29B is interrupt signal HIR(Delta).
It is routed to the Low
Priority Interrupt Logic and causes a low priority interrupt (LIRL) to be sent
to the CPU via the I/O bus.
After a nominal delay, the CPU responds with
peripheral address L (Delta) T which resets latch U29B which in turn causes HIR
(Delta) T to go low and reset counters U37A and U37B.
8-59. If the CPU takes longer than 2.24 seconds (2.6 seconds for 50Hz line
frequency) to respond with the L(Delta)T address, the Delta-T Interrupt Timers
(U37A and U37B) will time-out thus producing a high output on U37B-8 which is
fed to gate U51D.
The output to U51D-11 then goes low and is routed thru U54
(assuming the Auto Reset Enable mode is selected) to the A2 trigger input of
LPOP Pulse Generator U52.
The triggering of U52 causes the LPOP signal to be
produced which in turn resets all of the circuits to which it is tied.
8-60. DELTA-T INTERRUPT COUNTERS U37A/B.
Binary counters U37A and U37B are
each modulo-16 counters that are a modulo-128 counter.
Counter 37A is
incremented one count by each occurrence of LINE SYNC.
When this counter
reaches a count of 8, pin 8 goes high.
At a count of 16, pin 8 goes low at
which time U37B is incremented.
When U37B has been incremented 8 times, its
pin 8 output goes high which corresponds to 16x8=128 pulses of LINE SYNC or
about 2.2 seconds for a line frequency of 60Hz.
If the output of U37B is
allowed to go high (i.e., time out) before being reset by the occurrence of
L(Delta)T, the LPOP reset signal is generated.

I/O 8-16

Model 64100A - Service
8-61.

POWER FAIL LATCH U32B.

Latch U32B is a D-type flip-flop that is clocked

b.y each occurrence of LPOP (i.e., at system power-on and any time the Mainframe

is reset). LPOP causes output pin 8 to latch high which enables NAND gate U51D
thus enabling the output from counter U37B.
8-62. If a Power Fail Set (LPFS) address is received from the Peripheral
Address Decoder as a result of the CPU responding to a power fail interrupt
request (LIR15), latch U32B is set thus causing output pin 8 to latch low.
This circuit is latched with the
8-63. MANUAL RESET DE-BOUNCE LATCH u43.
first contact closure of the Processor Reset Switch and thus prevents multiple
triggering (due to contact bounce) of LPOP Generator U52 when the system is
manually reset.
8-64. LOW PRIORITY INTERRUPT LOGIC U22,23,23,14,21 (see figure 8-13, sheet 2).
The eight, low priority interrupts are gated thrti NAND gates U23 and u24.
These gates can be disabled (masked) by the CPU as a result of latching the
masking code into the Interrupt Mask Latch u14.
Latching is under CPU control
(i.e., enabled) by means of peripheral address LlMASK from U11. Latch u14 is
cleared by LPOP.
8-65. The unmasked interrupts are routed to Interrupt Data Buffer U21 and also
are ORed by U22 to produce low priority interrupt signal LIRL.
This signal is
routed to the CPU and causes the CPU to initiate an interrupt poll to determine
which peripheral device requested the interrupt.
The interrupt poll consists
of the CPU sending interrupt signals LINT and LDOUT to the 16-bit wide I/O Data
Transceivers U2 and u4 via OR gate U15B.
LINT enables the two transceivers
while LDOUT controls the direction of data flow which in this case is back
towards the CPU.
LIBE enables buffer U21 to put the interrupt code on the I/O
data lines.
The format of the interrupt code sent to the CPU identifies the
device that requested the interrupt (i.e., the location of the logic 0 in bits
L10DO thru LIOD7 identifies the interrupting device).
Table 8-1 shows the 1D
code for the eight interrupts.

Table 8-1.

Interrupt ID Codes

Interrupting Device

7

6

HP-IB
RS-232 Receive
RS-232 Transmit
(not used)
Local Mass Storage
Delta Time
Emulator
Keyboard

0
1
1
1
1
1

1
0
1
1
1
1
1
1

1

1

I/O Data Bits
5 4 3 2 1

0

1
1
1
1
1
1
0
1

1
1
1
1
1
1
1
0

1
1
0
1
1
1
1
1

1
1
1
0
1
1
1
1

1
1
1
1
0
1
1

1

1
1
1
1
1

0
1
1

I/O 8-11

Model 64100A - Service
8-66. I/O DATA TRANSCEIVERS U2, u4. I/O data and instructions are routed thru
transceivers U2 and u4 to the various I/O circuits that require communications
with the CPU. This includes the Low Priority Interrupt Logic, Card Slot Select
Logic, HP-IB Controller, RS-232 Transceiver, and the Keyboard.
These two
transceivers are bi-directional and are each 8 bits wide. The transceivers are
enabled by eitherLDOUT or LINT or by any of the following peripheral
addresses:
LKYBD, LRSRD, LRSWR, or LBEEP.
The direction of data flow is
controlled by LDOUT where the flow is to the CPU when LDOUT = 1 and from the
CPU to the I/O circuits when LDOUT = O.
8-61. SLOT SELECT LATCH u44.
Latch u44 consists of six segments of an 8element D-type flip-flop (the other two sections serve as the Card ID Latch).
Its purpose is to latch (store) I/O address bits 8-13 and is under CPU control
(i.e., enabled) via peripheral address LSSEI. When the CPU wants to store I/O
bits 8-13, it causes the LLSEL perpheral address line to be pulsed.
This
causes I/O bits 8-13 to be latched at the positive-going edge of LLSEL.
8-68. SLOT SELECT DECODER U53.
Address bits 8-11 from latch u44 serve as the
address input to Slot Select Decoder U53.
Address bits 12 and 13 from u44 are
combined with CPU addresses LA14 and LA15 to provide the chip select function
of U53 as shown in truth table 8-8.
Table 8-8.
I/O Bits
13
12

o

Slot Select Decoder 053 Enable Truth Table
CPU Address Bits
LA15
Lll4

o

1

U53 Selected

o

Yes

All other conditions

No

8-69. Decoder U53 is a 4-line to 16-line decoder that decodes the four input
address lines (in the Model 64100A only eleven of the 16 outputs are wired).
Each of the eleven outputs from U53 (LSSO-LSS10) is routed to pin 72 of each of
the option card slots as follows:
LSSO
LSS1
LSS2
LSS3
Lss4
LSS5

J4-12
J5-12
J6-12
J1-12
J8-12
J9-12

Lss6
~S1

Lss8
LSS9
LSS10

J10-12
Jll-12
J12-12
J13-12
J2/3-12 (not used)

8-10. A truth table for U53 is unnecessary since the ANSI chip symbol
the input addresses and corresponding output line selected.
8-11.

defines

HP-IB CONTROL.

8-12. REAR-PANEL SWITCH BUFFER U12 (see figure 8-14, sheet 3).
This is an
uni-directional, 8 channel buffer that relays the status of the Rear-panel mode
contr.,l switch Sl to the CPU. Control is provided by the PHI Control Logic.

I/O 8-18

Model 64100A - Service
8-73. ADDRESS LATCH Ull.
This is a D-type flip-flop that is used to store
four bits (HIOD8-HIOD11) of the I/O address data.
Bits 9-11 control the
selection of the PHI chip internal address registers while bit 8 serves to
control the RS-232 loop-back test feature.
8-74. PHI CONTROL LOGIC U7. This circuit is an array of four NAND gates (U7AU7D) that decode five input control signals from the CPU.
Its purpose is to
control the selection of Rear-panel Switch Buffer 012, Address Latch Ull, and
PHI chip U20. The five input control signals are: HDOUTD, LIC1, LIC2, LDOUT
and LHP-IB. Truth table 8-9 shows the control relationships.
Table 8-9.
LICl
X
X

0

PHI Control Logic Truth Table

Input Control Signals
LIC2 LHP-IB LDOUT HDOUTD
0
0
X

0
0
0

X

0

0

X
X

X

Chip Select Status
BUF u14
LTCH Ull
PHI U20
Yes
No
No

No
Yes
No

No
No
Yes

X=Don't Care
8-75. PROCESSOR TO HP-IB INTERFACE (PHI) U20.
The PHI chip provides a high
speed (up to 1 Mbyte/sec) interface to the HP Interface Bus (HP-IB) for processors and other state-oriented devices.
It is compatible with nearly any 8 or
16-bit CPU and requires a minimum of external logic.
Together with the four
bipolar tri-state transceivers (U5-U8 on the Rear-panel), the PHI chip provides
the complete logical and electrical interface between the CPU and the HP-IB.
In addition, it provides buffering for inbound and outbound data transfer
through two First-In-First-Out (FIFO) registers which can be addressed by the
host CPU.
.
8-76. The following I/O signals are provided by the PHI chip for
interfacing:
1. An 8-bit wide bi-directional data bus (D8-D15).
2. DO and Dl are status bits that indicate which byte
of the record is being transferred.
3. A 3-bit address (A13-A15) for selecting one of eight
internal registers
4. A read/write control (R/W) that controls the
direction of data flow.
5. An interrupt line (INT) to alert the CPU of selected
events.
6. Three handshake lines RFD, DAC and DAV
to cooridinate data transfer with the HP-IB.
7. A Direct Memory Request line (DMARQ) for
directly accessing the CPU memory (not used).

CPU

8-77. HP-IB LINES AND OPERATIONS.
The HP Interface Bus transfers data and
commands between the components of the 64000 Logic Development System on 16
signal lines.
The interface functions for each system component are performed
within the component so only passive cabling is needed to connect the system.
The cables connect all instruments, controllers, and other components of the
system in parallel.
I/O 8-19

Model 64100A - Service
8-78. The eight Data I/O lines (DI01 thru 0108) are reserved for the transfer
of data and other messages in a byte-serial, bit-parallel manner.
Data and
message transfer is asynchronous and is coordinated by the three handshake
lines:
Data Valid (DAV) , Not Ready for Data (NRFD) , and Not Data Accepted
(NDAC). The other five lines are for management of bus activity (see figure 84) .

DEVICE A
ABLE TO TALK,
LlSTEN,AND

HtH ttt 11
~

r--

DATA BU S
(8 LINES)

( D~

CONTROL
(MAINFRAME)

DEVICE B

c----r-~

ABLE TO TALK
AND LISTEN

('

DATA BY TE
TRANSFE R
CONTRO

)

(DISC)

DEVICE C
ONLY ABLE
TO LISTEN

:=j

GENERAL
INTERFAC E
MANAGE MENT

"

,)

(PRINTER)

~}
'--

0101 .. . 8

~~~D
NDAC
IFC
ATN
SRQ
REN
EOI

Figure 8-4. HP-IB Signal Lines
8-79. Devices connected to the bus may be talkers, listeners, or controllers.
The controlling Mainframe dictates the role of each of the other devices (disc
or printer) by setting the ATN (Attention) line true and sending talk or listen
addresses on the data lines.
8-80. Addresses are set into each device by switches built into the device.
While the ATN line is true, all devices must listen to the data lines.
When
the ATN line is false, only devices that have been addressed will actively send
or receive data; all others ignore the data lines.
8-81. Several listeners can be active simultaneously but only one talker can
be active at a time. Whenever a talker address is put on the data lines (while
ATN is true), all other talkers are automatically inhibited from talking.

I/O 8-20

Model 64100A - Service

8-82.

Information is transmitted on the data lines under sequential control of
the three handshake lines (DAV, NRFD and NDAC). No step in the sequence can be
initiated until the previous step is completed.
Information transfer can
proceed as fast as devices can respond, but no faster than allowed by the
slowest device presently addressed as active.
This permits several devices to
receive the same message byte concurrently (for timing, see figure 8-5).

_x'--__,----Jx_
(ATN = FALSE)

DATA

SOURCE

DAV
(COMPLEMENT OF DAV)

VALID
SOURCE
SOME RDY ALL RDY

ALL RDY
RFD
(COMPLEMENT OF NRFD)

NONE RDY

I
SOME ACC

fcA2MPLEMENTOFN_D_A_C_)__________________________________

IIIII

I ALL ACC ACCEPTOR

~I~I~I~I~r-!l~-----------I

DATA
TRANSFER
BEGINS

DATA
TRANSFER
ENDS

ACCEPTOR

Figure 8-5. HP-IB Handshake Timing

8-83.

The ATN line is one of the five bus management lines. When ATN is true,
addresses and universal commands are transmitted on only seven of the data
lines using the ASCII code.
When ATN is false, any code of 8 bits or less
understood by both the talker and listener(s) may be used. The IFC (Interface
Clear) line places the interface system in a quiescent state via the
abort message. The REN (Remote Enable) line is used with the Remote, Local and
Clear Lockout/Set Local messages to select either local or remote control of
each device.
Any active device can set the SRQ (Service Request) line true.
This indicates to the CPU that the device on the bus wants attention.
The EOI
(End or Identify) line is used by a device to indicate the end of a multiplebyte transfer sequence.
When the controlling mainframe sets both the ATN and
EOI lines true, each device capable of a parallel poll indicates its current
status on the DIO line assigned to it.

I/O 8-21

Model 64100A - Service
8-84.

RS-232 CONTROL.

8-85. RS-232 INTERFACE (see figure 8-14, sheet 4). The Electronic Industries
Associations (EIA) standard RS-232C defines the electrical characteristics for
an interface between Data Communication Equipment (DCE) and Data Terminal
Equipment (DTE).
A DCE is a modulator/ demodulator (modem) for encoding
digital data for transmission on the telephone system. A DTE is a terminal for
the time-share user. Normally, a. male connector is used on the computer or
terminal end; and a female connector is used on the modem end.
The 64100A
Mainframe has two identical female connectors labled: "TO MODEM" (J2) and "TO
TERMINAL" (J4) that have the transmit and receive lines reversed so it can act
like either as a modem or as a terminal (see figure 8-6) .

110

co NTROL
J1
12

14
17

16
1

2
15
9

10

(

",

3

19
20

(

21 <.
22 ,

I

,,
,,
,
,,
,,

B

,
5
13

6

...--

,

I
I

,
I
J
,
I
,I

<

- - ---- - - - - - - - - - - - - - --.

PIO REAR PANEL BOARD

J5
1 TXD
RXD
RTS
CTS
I S GNIIl GRO NO
I S [GNAI
GROL NO
I DSR
ERMJXClK
TERMRXCLK
I
DTR
CARDET Nt:
I +5

~!'>

1

RBI

1

R4

10

RTf:" 10

IP/D

+5

CHASSlt
~;j~
UJZa:

7

S

4

J3]

5
15
17

,,
,, I
,
I,
~

~

__ J

Figure 8-6. RS-232C and Current Loop Schematic
8-86. There are several wires (up to 25) used to provide the RS-232 interface
but only 11 are used with the 64000 System. Two of these are the data-carrying
wires:
one each for transmitted and received data.
In addition, there is a
signal ground wire and many more that serve as control wires between the DTE
and the DCE (see table 8-10).

I/O 8-22

j

~

I
N

TYn

ilfN

TXSINK

:I:

B

15

J2]
<:IH FI n cAnlJNn:

I

I
I TXSC

w

C\

O:;IlTFt n r.RmIND,'

<:Rr
R' N

I RCVSINK
II

>:

7

Rlirti(

i RCSC

LL __

!I

R'rc;
rs

TYf'IK

a:

'- __

U
~b~BIIBlllr:l
I '" ...
$ II
IrB
III

11
i I
E~ __

a:: w

ott

U8

J

N

'"

55 ~ a:

Jl:tlL
I I I

U9

,cr

U19

UH III
5g:a:a:~1

TP1

DIB
D
U26

1 J 1 1 "'I

r

10 D D r

BiD DOl

DI:!? B

BI

"1

is

I

B/\C
B I,'\C
,
I
\

TP6

I

S3

EJ. ~.
U20

~
'"I

J
¥
I I I c:oI

It)

U)

.....

a: a: a: a:

U28

I I I I

I

!:i

i

n $~n
oD

81
.1

I
~

I

"'~

TPGND

0'"

.1

1

+1·

I

G
~C50"

P1

Figure 8-13. I/O Component Locator

I/O 8-40

85

I'!'

~~

""I

Model 64100A - Service

LEVEL

- ,:

HI

/
19

17

liD

CONTROL----------------~,INTR.~ADDRESS~

1/0
8

25

26

34

32

24

23

22

21

/------

4344454647484950

2028293033

~ - ';~ ~~~~~~,'~~=----------~---g --t~~~~~~~~~~~~~=~~~~~~~~==~~~~~~~~'~~ "~~ =~~r~~ ~~ ~--~,~ ~ ~ ~ ~ ~:JITI~r ~frg~fm

~
I
I

~

,:"
1

!'r ,:'

~l~i

1 LBEEP

BEEPE~'I

U45A
DCDR

DECODER

G

12

t-----;G~22..... .9 p,
G1

R22
221K
BEEPER.
START
PULSE
GEN

C27
2200

11

5..r.;

+5BC~I'...i..J,... ~

FF
U32A

10

~

~

U33 ss
..r-t..

~

+5E1A

61.~~

5 I 12

P/O

CR5

U44

NC

~

b

CARD 10
LATCH &
DECODER

I.,

R ::c

:=
:s

tt

U3 1
0

4 - - , lH l
2
2
3 .....
+5E---+--6~5
-1

\

N

S

G G, 3

"'it" NC

ii:;.:

G,~

U45B

2500

HZ TONE
GENERATOR.

R24
14.7

~3 +
~

2..4
2. ,3

7
rc'
LBEEP
, ~ g-- NC ,----"..(.-"..(._ _ _ _ _ _ _ _~C-".f.--I 1
10
'J::
LSSEL
~, 1 '~f-">-l'""'lc----""'-.wO-----------'=.:e=--l 4
-----,.' G,.3
NC
'JI.
LIMASK 12
~,1,2
13
_
G,_~~NC
_
G,,l.-TsNC
LPFS
" '1
G

1,2
1, 2

C34
.01

CR4 , r

T ,

12

HIGH PRIORITY
INTERRUPT LATCH

1~
+5E~

"
R28
0 5 ....-..-l.......j--'\4"'2'y-2_ _----'

P

23,24,28-32
3942

-.?~1'

~

.

~'

13
I
=-C51

C14,43

~ ~~Q'Ol ~ (l~'Ol
':J

~IUF

':J

~r

~

~

P~~ ~_ v-~ v-:,~--.J;------~-t:.-~. ~~'u..n~lluu~J~-i.-uu u=un"
n~
--'v-,

I
LE1

••

C44

.••

,,474834

1314

1112

49

73

; : :;: ; :
3

7
U5
F

J8~

R37
IK

2.

3

U6.;>C>.!1",4-"Lo.=I-=T

+5~.

L;

U
37A
16

I

CNJR

1;d~

110~

C FF
~ S
13" R U29B

~NC

1820-2024
1820-1917
1820-1216
1820-1112
1820-1208
1820-1144
1820-1423
1820-1989
1826-0180
1820-1415
1820-1197
1820-1730
1820-0621
1820-1422
1820-1416
1820-1281

74LS244
74LS240N
74LS138
74LS74
74LS32
74LS02
74LS123
74LS393N
555
74LS13
74LSOO
74LS273
7438
74LS122
74LS14
74L5139

PARTS ON THIS SCHEMATIC
CI-5,10-12,14-20,22-24,
27-35,37-39,42-46
CR4
03-5
R23-34
S4
TPl-3
U5-6,17-18,29-33,37,
41-45,50-52,54-55

2.

2

13 .....

I

HIRH

9

U32,42,43,
51,52

L~I~N~T~~2.

4

®2

------------------.------------~----------------------___________________________'L~P_"0~P~__118

lor
DC

3,5

3

RI9

C FF

1

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IC POWER SUPPLY
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I
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HP PART NO.
1820-1917
1820-1208
1820-0509
1820-1195
1820-2024
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015
014
013
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REF. DES,
U6
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21
22
23
24
25
26
27
28
29
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LATCH
1
1
1
1
1

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HIOOO
HIOOl
HI002
HI003
HI004
HI005
HI006
HI007
HIOO14
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LENGTH
RATE FACTOR (XI OR X16)

54
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24r-------------------------------------------..J

3

RSZ3Zj6

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rtf

11

CR2

9 101

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13

9

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U35
U43,50
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07 0..

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7,8

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1
1
1
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2

3

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(64100-66524)

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14
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15 161

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SIG GND ~

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10
GROUND VIA
REIIR PIINEL
SCREWS
L-

tJOTEI
J4 PINS 9-12,14,16,18,19
21-24
J2 PINS 6,9-19,21-25
ARE NOT CONNECTED

I

NOTES'
1. Sl & S3 SWITCHES ARE EACH GANG TYPE SWITCHES.
2. ~THI5 CHIP'S VCC IS SWITCHED ON
ONLY WHEN S3 OS SET TP RS232.

-

MOOEM/PERIPHERIIL

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I/O Schematic 4 (Sheet 4 of 5)
I/O 8-47

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...
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Mfr
Code

Description

0

Mfr Part Number

PRIMARY PC ASS~J'BLY

28400

CAPAC nOR ·-F XD
CAPAClTOR···FXD
CAPACITIJR-FX.o
CAPAC1 TOR···FXD
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CAPAcr roR·-FXD
CAPAr:nOR-··FXD
CAPACITOR·-FXD
CAPAr:nOR···FXD

lUF·.·-l0X 35VDC TA
tUFI··_·1OX :'~!=jVDC TA
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2200PF +-··10'l: nOV1)C cr:.R
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2, 2IJFi·-1 OX 20VDC TA
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150Dl05X9035A?

562139
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56289

150Dl05X9035A2
016 0 -o483<~
1!5:lDlIl5X9035A2
o t('0-483,~
0160--40:;2
0160-4EJ30
o 16{J-·4:n:i
1 ~;3D22SX90;.!nA2
0160····0159
0160-4811

CAPAC nOR -FXD
CAPAr:ITOR-FX»
CAPACITOR-FXD
CAPAr:ITOR···FXU
CAPACITOR·-·rXD

lUF ... ··-l0X 35VDr. TA
lIJFi·_··IOX ~5V1)C TA
1500PF +-5X 100VOC CER
1500pr +···5X 100VDC tF..R
lUF·.·-l0'. 35VDC TA

CAPAI~ITC)R

1I.JFi·_·10X ~~~,VT)C TA
1500PF "'-·5~, 100VDC CEll
15U OPF ·,· ..·:='Jx 100llDC CER
lUr .. ···l0"- 35VDC TA
llW .. -··l0X 35VDC lA

51>289
;?O4£l0
21'14110

284BO
28480
2134BO

284RO
~;6269

20480
28480

56289
56289
28480
2B4BO
56;~89

64100·-66515

150Dl05X'103:1A2.
150Dl 00X903~';A2
0160···4846
0160-41346
150Dl 05)(90:!~;A2.

011'10···0291
0160-4846
011,11·-·4846
018U··-0291
OHlII···1I291

3
0
0
3

-F XD
CAPACITOR·-FXD
CAPAcnOR···F xu
CAPACITIlR·_·FXD
CAPACITOR··fXD

0160·-4846
0160-AB41,
0180··-0291
011,0 ·-o4B32
0180-2946

0
0
3
4
9

CAP Ae nOR ·-FXIl
CAPACITOR ··FIID
CAPAC nOi~ -·FXD
CAPACITOR ··FX1)
CAPAC! fllR-FXD

1500PF ... ·,,57.. 100VOC CER
15001'F I·-:;X 130VDC CE.R
111F .. --t 0"- 35VDC lA
, 0 lIJF +-·10X 100VDC CF.:R
3,lQUF+50-·1 U% 35VDC Al.

28480

011,0··5347
o 160 -·5~~47
11160-·~.347

13
8
8

o 160···5~147

8

0160·.. ·~!347

8

CAPAr:nOR···F XD
CAPAer TOR·-FXO
CAPACITOR-··F XD
CAPACITOR·-FXII
CAPACITOR···FX1)

1,OUF
1,OUF
1,OUF
1 ,01Jl'·
1,01Jr

2F.l48 0
28480
21HEI0
2848r.
;'0480

0160·_·$147
0160-:'>347

o 160-·5~~47
0140··-11180
0140·_·0156
0140-01:16
0180-1743

8
5
5
5
3

28480
721:Jb

DH19F202r.D300~V1CR

C46
C47
C4B
C49
e50

0180-·0229
0180--0291

3

o 160-AI'I22
0160--4832

4
2
4

C~;l

0160--4832

C:?8
C29
r.:30
C31
C32
C~U

C34
C:55
CJ6
C;57
C3B
C39
C40
C41

C42
C43
C44

C45

otil 0 --4832

C52

01l,O-·48~,2

C~;3

0160··-4832
11160 ··4832
0160-··41311

(;54
C~:j5

~~

6

2

7

~~

4
2
4

4
9

40DVDC
400VDC
4i10VDI:
400VIlC
40llVlIC

33UFi····l0X 1 DVJ)C TA
1I.IF+-··l0% 35VDC Til
, 0 lIJF I· ··1 OX 100VDC Cl:.R
1000pr "'·-5:1:. 100VllC CErl
,0lUF "'···10% 10.V»C erR

5(,289
284fJlI
2134BO
~~B4a 0

CAPACITOll·--FXII
CAPACl1(lR ··F XD
CAPAC7TOR-FXIl
CAPAr:lTIlR ··FXD
CAPACITOR-·FXD

,01UF ·'··-10:1:.
1 iI.orr ....H·~)X
,01UF +··-IOX
,01UF ... ··1iIX

1(lOl""OO;.~9

6

CRb
CR7
eRa

19n1···00~;O

:\

1 '1Gl····0 050
1701····0050
1901···0050
1901·-0050

:~

1901···0050
1901·_·0050

;5
:5
3
3

CR12
CR1:3
CR1?
CR18
crU9
CR20
CR21
LR22
CI~2J

CR24
eR2S
CR?I..
CIl27
CR2B
CI~29

PS 6-6

1901··~OO50

19111····0050
1 'J06-01l51

DIODE ··BWllriUNG
Il mIlle ··SWl TCHI Nt:
Dl(lJ)E···!:;WJ.TCHl.NG
»IODr·-SWrTCHTNG
»101)E-·SWITnnNG

9
1
1
1
1

1'701-0719
1')01-0719
1 ('J02-3082
1701-·0029
1901-00;:!9

1
1
9
1.0
6

c"lOOMA

i~NB

DO"'3~j

200MA ?NS

J)IJ-·~:.;

200MA 2NS nO"-3~j
~.~[) f)MA 2~S D()···~5
750MA DO -2'1

'30V 200MA eNS DO--35
BOV 200M(~ 2NS !lO· 3~j
80V 20DMA '.~NS DO "3~j
eov 200MA ~:!NS DO·· 3~-j
OOV :':~I) ilr.A ~?N!3 1)1) .)\~

OIODE···SWITCHING BOV 200MA
lH01)E·_·SWIlCHING aov ;!OOMA
llIOD[···SWITCftTNG BOV 200MA
»1IJD[-··r,WITr.JUNG OOV ~~o DMA
DIODC·-FW BRDG 10llV IA

4

1706-0006
1'701·_·0719
1901-·0719
1901····0719
1901·_·0719

1
I..

15 OD336X90 10112
150Dl05X9035A2
OlbO·-A8J;~

016(\"·4822
0160-41332

01 bO-4F.l32

CI~5

:1

DM19Fl ~i2GIJ:~0 GW\ll CR
DMI9F152C0300WV1CR
150Dl05X9035A2

20480

CR3
CR4

eRl0

01&0--5347

CER

CAPACITOR ··FXD ,011.JF +-·IOX 100VT)C
»IODE···SWITCflING OOV
DtODE··f,WIITHtNG BOV
llIODE····sWnCHING nuv
DHJI)[ -·swnn·IJNG aov
DIODE···PWR RECT 600V

CI~9

0160-5347

28480
"8480

4

3
3

5626'1

0160-~,347

0160-0;~47

o 160··-4113;:!
01bO-4sa2
01 (, (l'-483?
01bO-4EI:32
01(,0···04811

3

3

72'1~'56

0160·-4846
0160-4846
150 D t 05x90:55A;~
0160····4832
01ll0···2946

100VIIC CEIl
1:1 .VDC CC,:R
100VIlC CER
1110VDC CER
270rr ",··-5., 100VDC CE:R

01,~0·-4(l32

3

~!o4BO

CAPAr:ITDR ··FXD
CAPACl rOR··-FXD
CAPAr:ITClR ··f XI)
CAPAC ITOil·-F XO
CAPACITOR -F Xl)

1901--0()50
1901-0050
1901····0()50
1901··0050

L3

284 F.l 0

72136
5t>?B9

C5b

3
3

2F.H80
'56:.~f~9

CAPACITOR·-FXII 1,OUF 400VDC
CAPAI~lTOR-··F XU 2iJOOPF "'-~24 300VI)C MICA
CAPACITOI~-·FXO 1500PF .. ··-2X 300V»C MICA
CAPACITOR ··F X1) 15i10PF f'-2X :500vliC Ml('A
CAPACITOR-FXD .IUF +-10% 35VDAC TC

CIH
CR2

56~!a9

56201"1

150Dl05X903:1A2
OH.0·-4846
0160-041346
1:;UD105X9035A2
1511Dl05X9035A2

»lIJDE -FW ,IRDG 40JV lA
DIonE 'PWI~ nrcr 41l0V 3A
»tr.mr. ··PWR I~E[;T 400V 3A
DIOD[···PWR REel 41l0V 3A
D101)r,:···PWR RECl 4110V 3A

2NS DO

'3~:i

'.~NS DO ··35
:?NS Dl}· 35
t,)N8 DO"';"'S!)

301l"'S
300M3
300NB
3:1 IJN!:~

IlIODE:·-PW{~ RECl 41l0V 3A 300Nn
TlHJDr···PWR RE(;T 40DV 3A lOONS
DIODE:···ZNr~ 4,t.4V 5% DO" 35 PD",4W
(111))[ ··P~IR REel I..OOV 75DMA 1)0·_·29
DIODE:--rWR REcr bOOV 750M'" 00-29

See introduction to this section for

orde~ing

"F.l4f11l
:.:.~r:~4HO

28480

2[1400
""14BO
~~a4BQ

;?041311
~~84BO

;:8480
<'64(10

1 tltll"·'OO50
1')01-0050
1901·-0050
19111-0050
1901···01i29
1901--30,,0
1'?01····0050

;.~8

48 0
;'8480

lCjOl-00~.:jO

28480

19:Jl·-Oi)SO

28480
;.0>[1480
2B4all

1901·-0050
1901-30:.'iO
19()1·-OU50
1\1111 -0 O~jO
1906 .. 0051

,,~7'i'i7

VE4B

114713
114713
()4713
114?1 :3

MR8~'j4

114713
114713

M~'BM

28480

1902···3082
19J1-01129
t901" OOj~9

28-1BO
2B4FHI

2H4BO
2a41l1l

in formation

1901"'OO~~O

,

MRI'~:14

MRln4
MRE/54

~RB::=;4

Model 64100A - Replaceable Parts
Table 6-2. Replaceable Parts List A2 (Cont'd)
Reference
Designation
DSI
DG2

HP Part
Number

C
D

1990-0836
1'790 .... 11662

o

H~:!

0590-0076
0590--0U7i.

113
H4
H5

0:=:.. 90···0076
2190·-0469
21 ')0··0469

f'll

2'J 90-,0469
2190",,0469
21.90--0469

2190-D4b9
2190,,,0469
1-111
H12

2;:!OO···0139

HI3

2200'-0139

2200--0139

o
3

7

o
o
o
o
o
4
4

f114

2;:~OO-0139

4
4

HIS

2200-01759

4

IH6

2200"·OL39
2200-0139

4

HI7

t~;:::60

..·0 00 e;'

;.:26(J-OO()'?
::?2t.lO-OOO'l
2;~~bO

..· (I(JO?

~:;:!'60-0009

4
4
4
4
4

2260"'o(J(J9

H27

;:':~~60-0009

H;~B

305C-·0003
3050",0003
31l50-0U03

3
3

MPI
MP2
MP3
MP4
MP5

6 ..f100 .... 01104
64.1110·,,1111114
64i.1I0·.. 0U.04

8
B
8

64100-0U.04
b4100"OU.04

8

MI'6
MP7

64100" (J1104
64tOO"'OH04

8

f'3
P4

1 ;?51-:3192

1

1251-,3195

4

P~5

1;?51 .... 3195

4

185~~·-

2
I
I

QI
Q3
Q4
la:'i

0 036

1854'-0827

Qb

1854-,0827
1854-0027
1I'J54--0027

Q7

t 1354,,-0827

QS

IB54-08~7

RI
R2

21. 00 ..·2514
2100·.. t.~514
2.t OO"-2~H4
0757--0424
0757-,0447

R:~

R4
RS

RI>
R7
RS
R9
RIO

0'7f,7-·0424
0757-0451
0757--0424
11'757-.. 0458
0'7~,7··0429

Rl1
RI2

0'757-,,0429

RI3
RI4

0757-0442
oni7--046S

R15

0'757-'0442
O'i'~,7- 0442

0'i'~,7-'0409

3

7

a

a

I
I
I
7
4

2

3

3
i

7
7
2
2
8
9
6
9

0757,-0283

R20
R21
R22
R23

0757-'0280
0757-0469
0757-'0442
0757-0388
0757-'0448
0698-6977
0757-0453
0757-,0442

5
I
2
9

0698-4157

5

6
3

o

1990-0836

28480

19'?OH·0662

NUT ·-HI'.x .. punc I..~G 4'''AO .. 1 HI) ,14;5 .. TN· lHK
N!H--HEX'-PLSTC l..I(C 4-40-THD ,143--IN ·nil'-.
NLJT"HEX--[,I... fJTC l.I(G 4·"40 .. ·THD ,143 .. IN·1HK
WASHER"·l.K INTI.. T NQ, 4 ,116 .. "IN ..·ID
WASHER "LK INTI.. T NO, 4 ,116·-IN-·ID

2[14S0
2H480
28480
2.84BO
2848(}

0:590-0076
05911 ..·0076

WASHER ..·1...K
WASHER "I .. K
WASHER-I..K
WASHER .. I.K
WASHER-LK

284[10

SCREW··MAr.H
SCRE:W .. ·MACfi
SCRE.W· .. MACH
Sr.REW,,·MACH
SCRLW"'MACH

INTI..
Ilfll_
INTI...
IN1L
INTI.

T
T
T
T
T

4··AU

4 .. 40
4·-40
4·... 40
4"'40

Nil, 4
NO, -4
NO, 4
Nil, 4
Nil, 4

,116·-IN ..·ID
,116-·1N·.. 1D
,1.lb-IN"ID
,116--·IN-·ID
,116·-IN .. ·ID

.25-·IN ·LG
,25-"11'1' ·L(;
. ,-~5"'IN ·LG
,25 ..-IN· ·1...G
,25·.. 1111·LG

·+ID "POZ]
PAN-\·m"POlI
PAN-HD·"POlt
PAN·"HD .."FOZ [
PAN--HD-PO:l1
I')~IN

.25·"IN·"LG PAN ..-fID -Pill'[
,25·"IN"·I .. G PAN''')'ID ·pon

NUT ..·HFX-.. DT.ll.·GHAM
NUf,,·HEX-Dlll.·-CHAM
NIJT"·HF.X--DF.ll. CHAM
NUT·-HEX-D13L.-CHAM
NUT +IEX"-DF.ll. "CHAM

4--40 ... THD
4·-40·-nm
4"-40"lHD
4'-40--THD
4--40"'H-ID

NUT·-HE:X"·DB\.. --CHAM
NLJT"'H[X-DT.-130 09

TRANBJHTO\~ NPN HI TO ..··220AB PD:=l COW
TRANSI8TOR NPN 81 lO-'c2DAl) PD=l now

04713
04713

MJE"1300'?
M;n:·-130 119

IiE'AT
flEAT
IiE'AT
HEAT
HE'AT

SINK
SIN1(
SINK
SINI(
SINK

RESlSTllIl-TIlMR
RESISTDR--TRMR
RESISTOR-TRMR
RESISTOR 1,1K

201(
;!DK
?OK
lZ

PD=31 OMW
TO"'2211AB

204811
28400

2:3:4BO

FT=2~i0I1H'Z
PD~1

OIlW

TO--220AB PD::::l00W

10% C SIDE'-ADJ I-TPM
10% C StDE-ADJ 1-1~N
10% C SIDE-ADJ I--TAN
,12514 F 1C-0+-IOO

r

30t;'a:~

64tOIl-lItt04

12~'H-31

(;'2

1;.~~~il-3195

E.T~50W2{l3

30983

ET:';OW21l3

30983

FT50W203

24546

C4-'I/B-TO-IIIl 1· F

24546

C4-i/8-TO-1622-F

245~6

C4"-I/B'''TO-1!31 ·F

RcsrSTOR 24.3K 1% .125W r TC=G+--l00

24:;46

C4-i/B-TO-2432-F

REiHS10R 1.1\( lZ ,12e,\oI F 1'C-O+ .. IOO
RESJSTIJR 51, lie 17., ,125101 F TC-O+-"IOIl

24546
24546
24546

C4 .. I/S" .. TO·-I 821 .. F

RESISTOR i6.2K 1% .125W
,I~!.~,W

TC=O+-100

F T(;=O+ ·100

RESISTOR 1,02K 1% ,12511 F TC-O.-IOO
RESISTOR ~~74 1% ,u~~;w F lC=O+"100
RESISTOR 10~ 1% ,125\1 r TC-O+-IOO

2454fJ
24~546

24546

RESISTOR tOOK IX .12SW F TC=O+"'lDO

24~S46

RESISTOR 10K 1% ,125\1 r

Te-O"-'IOO

2.4';.46

PESISTOR 10K IX .125W F TC=O+-100

24546

RESISTOR 10K 1%

1
4
'1

f!.04BO

n~i90-0076

21 (70'··(1469
21 r)O-0469

.1I9;l .... J.N-·l'HK

RESISTOR 1.B2K 1% .125W F TC=O+-'100

9
9

0757--0442

2El48 I)

RESIS10R 1.1K lZ

o

Mfr Part Number

L.U) "l..P,Mf' ARRAY 1.IJM·"INT~500UCD
LED .. LAMP Af!RAY LUM·-INf"211I1UCD IF-SMA·"MAX

lRANSISH'R PNP 81
TRANSISTOll NPN 51
lRM~~1IS10R NPN 51
TRANSISTOI~ NPN 81
TRANSISTDR NPN HI

7

RIEl

R25
R26
R27
R;28

7

Mfr
Code

Description

SCREW·,,·MACH 4"-40
SCREW 'MACH 4-,40

4
4

RI6
RI7

R24

7

4

H~~6

H29
H30

Oty

,125\1 F Te-O+-IOO

24~4b

RESISTOR 2K i% ,12SW F TC=O+-100
RESISTOR lK 1X .125W F TC=O+-'100

24546
24546

RESISfOR
RES1STDR
RESISTOR
RESISTOR
RESISTOR
RES1ST(JR
RESISTOR
RESISTOR

24~i46

150K 1% ,125W F Te-O+-IOO
IIlK 17G ,1:?5W F Te-O+'IOO
30,11% ,12.5W F TC=O+ .. ·\cO
10,2K 1% ,125W F TC-O+-IOO
30K ,1 % ,1 ;;"',W F TC-O+-i!S
;50.1 K 17G ,125W F TC=O+-I 0 0
10K IX ,125W F TC-U+-l00
10K ,1% ,125W F TC-0+-50

C4 .. 1/8 .. TO-·1131 .. r

C4,,"t IS·-TO···5112 .. ·r
C4 ..·1/8 ..·TO--I1321.·-F
C4· ·1/8 ... TO ... 274R·F
C4 -1/9--TO'-1 0112""F
C4 .. I 18-.. TO-·1 00:5· F
C4 .. 11l1-TO-·l01l2·-F
C4"·I/B-TO-I032 .. r
C4'-1/8- TO ·.. 1 0 02·-F

C4-1/8-10-2001-F

24~4b

C4··1 18 ..·T 0,-1001",[
C4·.. 1/9 ..·TO·,,·1 ~",03·,,·r
C4"1/8""TO-I002"'F
C4·-1 18·-TO -30~ I .... F

24546

C4·-·1/S·-TO"-1822:·-F

2f.J4BO

0698-/,'177
C4 ... 1 18· .. T 0·... 30 I;~ . F
C4 .... 1/S·-TO-l002 'F'
0698,-4157

?4546

i~4546

24546
284)30

See introduction to this section for ordering information

PS

6-7

Model 64100A - Replaceable Parts
Table 6-2. Replaceable Parts List A2 (Cont'd)
Reference
Designation

HP Part
Number

c Qty
0

R30
R31
R32
R37
R38

01.90-'4157
0757-0450
on,7'-0453
0757-·0442
0757-,,0442

5

R:~9

R41
R43
R44
R45

0757-0436
0757·-0481
0698--3432
0757-1090
0757-1090

R46
R47
R49
R49
R52

07~j7·-·0414

:5

0757-0414
on,7-'1090
0757-·1090
0757 .. ·0442

Description

Mfr
Code

Mfr Part Number

RESISTOR
RESISTOR
RESISTOR
RESISTOR
RF.!3ISTOR

10K .t:.: .125101 F TC=0+-'50
51.1K n. .125101 F TC=0+"-100
30.1K 1% .125101 F TC=01·_·100
10K n. .125101 r TC-0+-1DO
10K 1% .125101 F TC=O+-IOO

I
1
1
4

REsrSTOR
RESISTOR
RESISTOR
PESIsrOR
RESISTOR

4.32K n. .125101 F TC=O+"-IOO
47SK IX .125101 F TC=O.,,·IOO
26.1 1% .125101 F TC=0+-100
261 IX .5101 F TC-O+-'I 00
261 1% .5101 F TC=O+-'IOO

2

5
5
5
9

RESISTOR 432
RESISTor~ 432
RE!3ISTOR 261
RESISTOR 2M
RE!3ISTOR 10K

R54
R55
RS6
R57

0757-02BO
0757-0442
0757-,,0199
0757·_·0401
0764-0013

3
9
3
0
5

lK n. .125101 F Te=0+-100
RESISTOR 10K n .125101 F TC=D+'''I 0 0
RESISTOR 21.51< 1% .125101 F TC-O+-IDO
RE!3HiTOR !DO IX .125101 F TC=0+-100
RESISTOR 56 5" 2101 MO TC=0+'-200

R5B
R59
R60
R61
R62

0761-·0044
069B-.. 36IB
0757-·0394
0757-0394
0757-,0394

6
1
0
0
0

RESIBTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR

B2 ~X 1101 MO TI::=0+-'200
B2 5X 2W MO TC=O +,,-20 0
51.1 1'1: .Iasw F TC-O+-IOO
51.1 1lr. .125101 F TC=0+'-100
51.1 1% .125101 F TI::=' 0+",,1 00

?B4BO
27167
24546
24546
24546

0761-0044
FP42-2--TO O--Bf.1R O-J
C4"'1/8-TO"'5IRI .. F
1::4 .... 1/9-TO--51~1-.. F
C4 ..·1 IB-"T 0-51R I . F

R63

0757--0394

0

RESISTOR 51.1 Ill'. .125101 F TC=0+"-100

24546

C4"-I/B-TO-51 R1·-·r

R64

0751-0394

0

RESISTOR 51.1 1lr. .125101 F Te=0+-·100

24546

C4--I/B-TO'-51R I"-F

R65

0757-·0394

0

RESISTOR 51.1

24546

C4'-1I9-TO'-51FI -F

Riolo
Rf.7
RItS
R69
R70

0757-0280
0757-02BO
0757·-0429
0757-0428
0757 -0417

3
3
2
1
9

RESISTOR lK 1':1: • 12~,W F TC=O+-IOO

24546
24546
24546
24:546
24546

C4-I/B-TO-l001-F
C4'-1 18-TO'-1 0 Ol-·F
C4"'1 19-T 0-,1 821"F
C4·-1/8--TO--162.1-F
C4·_·1 18--TO'-562R" F

R71

0757-0442

9

.1

RESISTOR 10K 1l<. .125101 r

RTI
RT2
R13

0837-01BO
0837-·0180
0837--0180

2
2
2

3

TI-1E.RMtSTOR lK-"OHM
THERMtSTOR \K"-OfiM
ll-1ERMISTOR lK 'O~'M

T;?,

9100-4163
9100--4304
910 ()-.. 4:304
9100-4304
91011-·-4:504

7
9
9
9
9

I

TID
TIl
Tl2
Tl3

TRANSFORMER
lRANSFORMER-BASE
TRANSFORMER-BASI'TRANSFORMF..R-BASE
TR ANSFOR MER -BASE

Tl4
T15

9100-4304
910IJ-4304

9
9

III
1I2
1J3
U4
U5

1821.,-0719
1926-0565
IBIO-'0279
H126-05b5
1826-0565

5

1.1(,
1J7
UI3
U9
1.110

1820-2111
1(120-2111
1f.12b-04I"B
1926-,,0468
11310-0279

UII
lI12
1.113

HIIO-'0273
1826-·0346
lB2&·-0345

R5.~

PS 6-8

y

2
9
9
1
6
7

:;

5

0

5
:5

IX
IX
IX
IX
IX

.125101 F TC=O+--IOO
.125101 F T(;=0+-100
.5W F TC=O+-'IOO
.5101 F TC.D+--IOO
.125101 F TC=O+-IOO

RESISTOR

1
I
1
I
1
6

I

1
I

6

1
3
2
3

5
9
9

2

7

2

7
5
9

I

0

f

9

1

RESISTOR
RE!31STOR
RESISTOR
RESISTOR

n.

.125101 F TG=0+'-100

IK 1lr. .125101 F TC=0+-'100
I.B2K 1% .125101 F TI::=0+-'100
l.b2K 1% .125111 F TC=0·...-100
562 IX ,12~;W F TC"O.·_·I 0 0
TC=O+-IOO

20400

01.98-4157

28480

0757-0450

24541.
24541.
24546

C4-"1/8-TO--3012-' F
C4-1/9--TO --I 002--F
C4-"1/9-'TO--I 002·.. F

24546
19"101
03088
28480
28480

C4--1/9-TO--4321'-F
I'IF 4CI/8"-TO'-4753"'F
PME55 ..-1 18'-TO-2bR 1 ·-r
0757 ..·1090
0757'-'1090

24546
24546
2B490
28480
2454~)

(;4-'1I0--'TO-432R-F
C4-'1/9'-TO'-432R-r
0757-1090
0757'-1090
C4-1/9-TO-I002-F

24546
24546
24546
24546
28490

C4-1/8-TO-l00l-F
C4'-'1/9-"TO-IOO<~ ·F
C4·-1/9-TO-2152 .... r
C4-'1I8-TO-101 "F
0764 ..·0013

24546

C4-I/B-TO-l002-F

01295
01295
01295

TSPI02J
TSP102J
TSP102J

DRIVE
DRIVE
DRIVE
DRIVE

284BO
2f:l4BO
28480
2B4BO
28480

9100--4163
'11 0 0--4~;O4
910 IJ-·4304
910IJ·-43f14
91110-4:504

TRANSFORMER --BASE DRiVE
TR ANSFOR MER·-BASE DRIVE

28480
294fiO

9100 .... 4304
910IJ--4304

IC-SV REFERENCE
IC'-TL494
NEl WOR K·-RIC!3 10-!31P4.7K OHM X 9
IC-TL494
IC-TL494

28490
284fJO
01121
28490
28480

1826-071B
1826"'0565
210A472
ttl2b'-0565

IC DRVR TfL INV
1C DRVR TTL INV
IC COMPARATOR r;p 8'-DIP'-P PKG
1C COMPARATOR GP 8"'DIP-P PKG
NETWORK-RES IO-SIP4.7K Oi~M X 9

012?5
01295
04713
04713
01121

SN'7546BN
SN754/,BN
MC3423Pl
MC3423Pl
2tOA472

NF_TWORK-"RF.:S 10-SIP470.0 [lHM X 9
IC OP AMP GP DUAL B--DIP-P PKG
Ie V R[;LlR TO-"2~!0

01121
27014
07263

211A471
LM3SElN
UA79H12UC

See introduction to this section for ordering informatiori

1826-051.5

Model 64100A - Replaceable Parts
Table 6-2. Replaceable Parts List A3
Reference
Designation

HP Part
Number

00-66~H

A3

641

Cl

0170-0066
0180-,3046
01130-··3046
0160·-0168
0180····3046

C2
C3
C4
C5
Cb
C7

cn

C9
CIO
CII

01130-3046
0160-0174
0160····0156
0180-·2946
0180-0197

C

D

7

Qty

3

9
2

SFCONDARY-·PC ASSEMBL.Y

2
(,

2

I

2
2
9
9

9
B

Mfr
Code

Description

1
1
;.

,

i

Mfr Part Number

2840(1

6410 0 ~~665 t 7

23480
284EHl
28480
28·480
213430

0171J-0066
0100,,-3046
0180-3046
0160--0168
OH10-3046

28480
2B431l
2B480
28480

0100'-3046
0160-··0174
0160'-01513
o1BO-2C"/46

CAPACHOR···FXD
CAPACITIlR·-rXD
CAPACITOR ··FXD
CAPACITOR-FXD
CAPAClTOR-FXD

. 1l27IJF '.'-'1 0'% ~o OVl)C POL.H:
330 our /.,. 3VDG
3300UF 6.3VDC
.Iur +,,-10,," 200VDC POLYE
3300I.JF h.3VDC

CAPACITOR-·FXll
CAPACJ.TOR ··FXD
CAPACITIlR·-rXD
CAPACIHlR·fXD
CAPAcnOR·--fXD

3;~0 our b. 3VDC
. 47UF' +-··10% 50VDC CER
S('OOPF +,,-1 (Ill. 200VDC POLYE.
330llF 35VDC
2. 1'UF+"'1 0% 20VDC TA

56289

t50D;~25X9(}20A2

CAPAClTCJR··fXl) I GOUF+75-'lOX 2~;Vl)r; AL.
CAPACITOR·_·FXll .02·7UF +"-10% 200VDC POl.YE
CAPAClTOR"'fXD 3,100UF 1". 3Vl)C
CAPAClTOR·_·FXll 3;~0 our 6. 3VDC
CAPACITOR ··fXD .0lUr +"'IIl% 200VDC POLY~

56289
28480
28431l
2.8480
28480

30DI 07G02~,DD2
01'70-0066
OHI0--3046
011:10,-3046
0160-011:,1

CAPACJTOll'--FXD tOOOPF + ,5% 100VilC CER
CAPACITOR-FXD 1500PF +-10'% 200VliC POLYE

213480
28481l

o160-0,~98

C13
C14
C15

0180-0094
0170'-'006b
0180-··3041.
0180····3046
011.0-'0161

ell"

o160 '--4822

2

CI7

0160'-0298

8

CI~

6
6
5

2

3

3

CR5

1906,-0079
1'106-0079
1'701-'0026
1901-,·0050
1 '701··-0050

3

DIODE-FW BRDG 100V tOA
DlODII"FW BRI)G 100V lOA
DIODE'-.-PWI~ RECT 400V 750MA DO'-29
Dll)1)E-'SWlTCHING BOV 200MA eNS 1)0-35
DIODE"'SWITCHING 80V 200MA 2NS DO"'35

eR6

1901-0050

3

DIODE-··SWITCHING BOV ,!O QMA l?NS

CR8

1901,·-0727
1901·_·0727
1901-G727

DHlDE··PWR RECT 3~,v bOA IONS 1)0-·5
DI0DE-PWR RECT 35V bOA IONS DO"'5
DUll)f>-PWR RECT 3~,v 60A IONS DO-·5

1901·"·(17~~7

DIOllE'-PWR RECT 35V 100A IONS DO"-5
1)IODE:--PWR RECT 3~,v 60A IONS \)0'-'5
DIODE··PWll RFCT 3~W bOA 10N\, DO"'S

28480
c~B4B(l

t901-·0n7
1901-0727
1901·-072'1

28480
01,(1011
011000
1I001l1l
OIlOOO

ORIlER
ORDER
ORDER
OIl1)ER

C12

I
CR2
CR3
CR4

CI~9

CR I 0
CRll
CR12
CI~13

4

9
2
2.

4

1 I

1901-0727
1901-·072.7

27"77"7

27777
1'84fJO
284BO

28400

DO-3~;

0160,-4822

V,Tl4flX
VJI4f.1X
1901,·-0028
1?01-00~;0

1901,-0050
1901-0050

213480
2841~0

;.'8480
2\14BO

1901-0727
1901·_·0727
1901-0727

::3

f.5

0340-,0473
0380····0339
03110-0339
0;:180·- 0 7 41
0380,-0741

2

INSI.JLATDR····XSTR 1 HERMA ··FILM
STANDl1FF-·RVT·-ON .25··-IN-··L.G 4·-40THD
STANDnF r ··RVT···(1N • 2~i-·IN···1.G 4'-o401I-1D
STANDOFF'-RVT-'ON .187··-IN··-U; b"32THD
STANDOFF -RVT'-(1N .1El7··JN···LG 1,-321 HD

E6

3050-··0791

6

INStJL.ATOR···TRANSISTOR, NYLON

284130

30~7j(1-07(i't

I-li ···17
Hl8
1i19
H20

2190···0017
2,!00'-0 1 05
2200-0105
2200··~O 1 05

4

WASHER"LK HL.r.L NO.8. 160-·IN-··ID
SCREW··MACH 4,-40 .31)!-IN·LG PAN··HD·-PtllI
SCRE.W··MACH 4···40 .312·-1N··I.G PAN +ID-··P07.:l
SCREW··-MACH 4·· 40 . 31'~'-'IN-LG PAN'-HD'-POZI

l"848 II
00000
0111100
00011 0

2190-0017
OllDER BY DEseR IPTION
ORDER IIY DESCRIPTION
m!DER BY DESCRIPTION

SCREW-·MACH
SCREW··-tlACH
SCREW-· MACH
SCREW·-MACfl
llCREW···MACH

00000
011000
00000
000110
001100

DRDER
OIHiER
ORDER
ORDEll
OH1)ER

01i1l00
1l0ilOil
0111:00
[) () {JOO
00000

ORDEIl BY
BY
ORDER BY
ORDER BY
ORDER BY

DESCRIPTION
DEseR IPTIDN
DESCRIPTION
DESCRIPHON
DESCRIPTION

00000

OR1)ER BY

DE5C~IPTION

EI
E~!

1'.3
E4

2

2

2

4
4
4

2200-0111

2

2200·-01 t 1
2200-0121

2
4
4
4

2200····0121
2200""Ol;:~1

H2D

4
4

;~200·"·0121

,'200·_·0IElO

5

2200-018U

5

H29
H30

t.~360··-0

22110·_·11180
121

2

H33
H34
1-135

c,
'J

076
0590·_·1)076
0:';90·_·00'76
0:590··0076
0~,90-0

0590,,-0076
0590-0076

H38

0~'.;90··-0076

H53
1-154
H:55
H56

2580-0004
),5[10"0004
;!c;;80-··0 0 04
3050-,,0003
3(15U-'0003

4"40 .5--1N-··U; PAN··+ID·-[>OZI
4'-40 .5·-IN··-I..G PAN·-Hll···POZ.1
4"'40 1. 1 (~S-'l N-'I...G P~,NM"HD-"POZI
4,,-40 1.125··IN-··L.G PAN··HD··POZI
4-040 1.lc:~;·-1N···LG PAN "HD"'P(JZI

SCREW"MACI~ 4"-40

3

23hO-0121

1-137

H36

2
4

4

H27
H~!8

1-131
H32

17
3

l,CRLW"MACH
\,CREW···MACH
SLRr.;:W-·MACH
SCRE:W·-MACH

I .1'~5···IN···L.G PAN-·-HD··POl.I
4-,-411 t.3'15··YN-I .. G PAN·+lD·I'Oll
4--40 I. 375··-IN-L.G PAN·· flD"'POll
4-0411 1.375 -JioH_.G PAN ··HD-··PIl7.I
;',,3<: .5··-IN··-LG rr,N··I·\D ··rnn

5CREW ··MAn·1 /,,-,32 .5-·lN··LG pr,N"HD ··pon
NlH·I·1E:X··-PLSTC U(G 4···o40··TI-ID .143·_·IN··THI(
NI.IT-··HEX ··PI..STC LKG 4··o40···lIlD .143··IN··Tl-IK
NlIT···I·ICX··-Pl.STC I..KG 4-o4C--THll .143-···1N·· Tlw'
NUT +IE-X "PLSTC LKG 4-,-4 0'-'1 liD .143-··IN··lHK
NlIT··-IIEX 'PLSTC U(G 4·-4\1··-THD
NUT··IIF,X ·PI..STC J..l(G 4--40····1I1D
NUr·-HFX·· PLSTC LKG 4···40-THD

.143··1N·· THII.
. 143····IN ··1HK
.14:1·-1"·· THI(

14

H~i7

H5B
H~i9

H60
1161

1-162

30511"'01103
3050-,0003
30~iO-0003

3050'-0003
3050·_·0100

6

3

6

6
3
3

6

BY
BY
BY
BY

DES['RIPTION
DEseR IPTION
DE,;CRIPTION
DESCRIPTION
i)Y DESOR IPTlON

OR1)E~

2r:l4BO

0590"-0076

C'B48 0

0590-0076
0590,,-0076
0590-0076

28480
28480

DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION

28480

05'70,,-0076
0:';'10--0076
0590 .... 0G76

2.8480
(~84ao

00000

OR1)E R BY DEseR IPTl ON

01l1l1l0
001100
011000
28480
:'8480

ORIiEP BY DESCIlJPTION
ORJ)r'R {IY DE~;CR IPTION
ORnER BY IiESCR IPTION
JOf-iO-·nOQ3
30:,0-0003

6 .141 MIN"ID .:375""(N·OD
NM NO.6. 141··IN ·ID . 3"7~; ·IN· ·OD
NM NO.6 .141-·IN··ID .375··J.N-I)!)
NM NO.6. 141··-IN· ·ID . 3n; 'IN-OD
M1l..C NO. 6 .147-IN···lJ)

28480
28480
2tl431l
26480
28480

3050-0003
3050·· 0003
:1050-0033

3

I,o..IA$HER TI.. NM NO.
WASI~[R' oFL
WASHER··FL.
WASHER -Fl
WASH":R "['L

4

BY
BY
BY
BY

NUT···IKX·-DEtL. .. ·CHAM f)·-3)'··-Tl-m .l<':.:;···IN··-THI(
NUT-·HEX··DI'l..··rW,M !l-·32··1HD .12~;-·IN····1Hi(
NUT···HEX--Dlll_-·CI·IAM 8·-3c·-THD .1;~5--:[N·-THI(
~lASHFR"FL NM NO.6 .t41···JN-·lD .375-·JN·DD
WASHER-VI.. NM NO. ;, .141-1N-ID .3"75-11'1 ~D

3
3
3
I

0~140-0473

30~iO'-OOO:~
30~0-011l0

See introduction to this section for ordering information

PS 6-9

Model 64100A - Replaceable Parts
Table 6-2. Replaceable Parts List A3 (Cont'd)
HP Part
Number

c
o Qty

H65
HI:06
1-167

3050 -0100
1 00
:3050 ..·0100
:1050--1049
3050"'1049

1
1
I

H68

Reference
Designation
H63

H64

Description

Mfr
Code

Mfr Part Number

9

WASHER-·H. MTLC NO. " .147 ..·1.N"·ID
WASHER ..·FL l!ftC NO.6 .147·.. 1N"·ID
WASHER'-I'L MlLC NO.6 .147"·IN-.. JD
WASHER-·FLAT) INSL
WASHER"FLAT, INnL

284E10
28480
28480
86928
Bb928

3050 "-1 049

9

WASHER···FLAT) INSL

86928

5b~O-35·

9140-,,0618
9140 . · 0(:123
9140-,,0617
9140,,,0619
'1140·-0625

3

INDl)CT(JR-'39uH
INDLICTOR·-·2UH
INDI.ICTDR-.. 14UH
INDUCTOR-3UH
INDUCTOR ..·I ~IJH

284130
28490
28480
28480
28480

9140-0618
914U'-0623
9140-0617
'114(i-"0619

INDLICTOR"·14lJH
INDI.)CH,R·-·2UH

28480
,;>8400

9140,,-0617
9140-0("'23

~,050--0

9

o
2

3

2
2

4

2

3050-0100
3050-0100
3050-0100
5620-35"'31
5420-35~"31

31

9140-()625

L6
L7

'7140·_·0617
9140-0623

HPI
MP2
HP3
MP4
MP5

/,4100-·61103
64100·"61102
64100-61101
1205-0266
64100-01101

3
2
I
7
5

HE:AT SINI( ASSY-3
HEAT SINK SGL 10--3 "CS
HEAT BINK-DRIDGE

213480
2fJ4FJO
28480
213-430
28480

1.41110-·61103
641 GO'-611 02
64100-61101
1205···0266
64100,-01101

MPI>
MP7

64100··011113
64100'--47501

7
5

HEAT SlNK-·t-12
TFRItINAI. llLOCK

284BO
28486

641 il 0-,,011 03
Ml00-'4niOI

P3
P4

6

I

4

P5

3

28480

1251 ..·3767
12f::.t···3195

12~51-·361a

6

I

CONNECTOR 7 .. PJN It POST TyrE
CONNfCTOR 4-PIN It POST TYPE
CONNfCCTOR 2-PIN M POST lYPE

?fJ480

t;:?51·· .. 3195

28480

12~t-36tB

lB54 ..··0B28

2

01295
04713

TIP···122

2

TllANSISTOR NPN 81 TO"'220AFI PD~65W
1 H'TR T STOR"'f,rR
THYRIS.TO~·-·SCR

0471~3

12~jl-·3767

1884-'0217'5
H184-'0295
0698 ..·0093
ODII·_·3579
5080·"1014
0'757····0280
0698-0093

:=.;

I
3

HEAT SINK ASSY·.S
HF::AT HINK ASSY-5

RESISTOR 10 51

4

SHUNT -, liMB 25M
RESISTOR 11 11 .125W F Te-0+-l00
RESISTOR 10 51 lW MO TC-0'-200

;'?El4BO
28480
2fJ4BO
2454iJ
28480

SHUNT·-DMB 25M
RESISTOR lK I I

284811
24546

o

R6
R7
R8
R9
RIO

5080'''1814
0757-02130
0757-0420
0698-'3444
0757-,0465

3
1
6

Rll
R12
R13
R14
R15

07f)7-"0795
0698····3132

5
4

07~j7"··O(,~74

0.,98····0093
5080"'1814

RESISrDR 10 57..
SHUNT-"DMS 2'e,M

RIb
R17
RIB
RI9
R20

0757,·-1000
5080·.. 1814
0757-"0420
0757-0465
0'757'''0452
069f.1 ..·3401
0757--0409
0698·,·8812

SI
T7

Hi
T9

9100'-4161
9100·--4160
9100-·'41 ::;2

Ul

1826'-0:,46

U2

1826-0677

I

3

7
I
3
I>
1

IW

3
I

2

MO Te-0.-200

.125W F Te-O+-IOO

RESISTOR 750 1% .125W F TC=O+-100

24~::i4()

RESISTOR 316 I I .125W F Te-0+-l00
RESISTOR lOOK I I .125W F Te-O+-IOO

24546

REST.BTnR 75 1'7. .5W F TC=O+···100
RESISTOR 261 I I .125W F TC-O+ .. ·IOO

24~.46

RESlSTOR t.21K 1X ,125W F TC=O.-lno

24546

I~I tiC}

28480
20480

TI:-0·... ·200

RESISTOR 51.1 I I .5W , TC-O+-IOO
SHUNT-· DMS '.!5M
RESISTOR 750 1% .125W F Te-0+-l00
RESISTOR lOOK I I .125W F Te-0.-l00
RESISTOR 27.41( n •• 125W F TC-O+"·IOO

24~j46

19701

28480
284BO

0698-0093
onll"'~3S79

51180-1 B14
C4-1 18·.. TO "-I 0 0 1 ..-,
06'18-0093
50110'-1814
C4 .. 1/8 .... TO-I00'1 ·F
C4-1/S-TU-7501-F
C4 ..·1 18 ..·T 0 -316R" F
C4"-1 18·-TO·.. I 0 0 3-F

MF .. I 12 .. ·T3·-75R 0 ·F
C4·"1 18-TO"-21.1 O-F
C4··1 18"'TO-1211 "F
ot:8?--O 0 9;-S
~;{)80-1814

24546
24546

0757 .. ·1000
5080-1814
C4·-1/8·-TO-751 ..-F
C4' ·1/8-.. TO-l 003-F
C4-1/8'''TO--274?''-F

2454~.

o

RESlSTCJR 215 1% .5W F TC=O+- .. 130

8

7

RESISTOR 274 IX .1:~5W f' n>=O+"'100
RESISTOR I 11 .125W F TC-O'-IOO

28480
24546
28480

06?8-.. 340 1
C4--lIB-'TO .. 274R· .. F
0698-8812

2

THF.R MAl

..,
4
4

SW ITCH

28480

310~3"'0091

TRAN5FIlRMER
TR ANSr:llR MER
1 RAN[;FORME:R

28480
28480

28480

9100-4161
9100"·-4160
9nO-4152

lC OP AMP CP DUAL B-DIP-P PKG

27014
28480

LM:3'.5HN
Hl26· ·0677

See introduction to this section for ordering information

PS 6-10

MCR69"'1
MCR6(]-1

Model 64100A - Replaceable Parts
Table 6-2. Replaceable Parts List A4
HP Part
Number

D

A4

64100-66528

6

Cl
1::2
C3
C4
C5

011.0 .... 362:;>
011>0-31>22
0160'-3508
0160-·3622
0180-0197

8

C6
C7

C9
CIO

01130-0197
011.0·_·4822
0160-4833
0180-2941.
0180-0197

8
2
5
9

Cll
CI2
CI3
CI4
C15

0180·-3127
0180-0141
0180-0197
0160-·4832
0180--2946

o
8

Reference
Designation

CB

c Qty

2130Y5VI00RI04Z
2130Y5VI OORI 041
0160-3508
2130Y5VI OORI 04Z
1501):22SX9020A2

CAPACITOR--F"!)
CAPACn(lR-FXD
CAPACITOR---Fl50--10X 3SVDC AI..
:2. ;!lJF·,-·-1 OX 20VDC TA

56289
?84BO
21,14130
28480
50~a9

150D:225X9020A2
0160---4822
0160-4833
0180-2946
1501)225X9020A2

CAPACITOR--FXD
CAI'ACITOR--'F"D
CAPACITOR---FXD
CAPACITClR---FXD
CAPAcnOR-FXD

180U, 7SUDC
SOUF+'75--10X SOVDC AL
2.2UF+---IO% 20VDC TA
.01UF +-1 DX 100VDC CE:R
330IJF+SO-IOX 35VDC AI..

284BO
56289
56289
28480
28480

0180--3127
3 DDS 0 6G 05 0 DD2
150D225X9020A2
0163-,-4832
0180-2946

I:APAr:nOR---FXD 2. 2IJF+---I OX 20VDC TA

56289

150D225X902DA2

DIODE---SWITCHING SOV
DIODE-SWITr.HING BOV
DIODE-SWI'fCHING 80V
DIODE --PIoIR RECT 400V
DJODF:-SWITCHING 80V

2NS DO--35
2NS DO---35
2NS DO---35
1)0-29
2NS DO--35

28480
28480
28480
28480

1901--0050
1901-0D50
1901--00S0
1901-0028
1901--0050

DIODE--SWITr.HING 80V 20DMA 2NS 1)0-35
DIODE--PWR RECT 400V 7S0MA DO--29
DI01)E --PIoIR RECT 400V 750MA 1)0-29
DIODE-·-FW BRDG 100V IA
DIODE·-SM SIG l'lCHOl T~Y

28480
28480
284BO
28480
28480

1901-0050
1901-0028
1901-0028
1906·--0051
1901-0535

i

l.EIl--·LAMP ARRAY LUM--INT=20 OUCD IF=SMA'--MAX

28480

1990-0662

3

NlIT·-HE.X-·PLSTC LKG 4-40-THD • 143---IN-'-1 H~
NIJT-HEX-PL.STC L.KG 4-40-THD .143-IN·_·THK
NUT --HE.X-PLSTC I __ KG 4-·40-lHD .143-IN-TBK
SCREW-MACH 4-40 I • 125-IN--LG PAN-HD--POZI
SCREW--·MACIi 4--40 1. 125--IN--'LG PAN -·I-ID--POZ!

28460
28480
28480
00000
00000

0590-0076
OS90--0076
0590-0076
ORDER BY DESCRIPTION
ORn~R BY DESCRIPTION

SCREW-MACH 4-40 I. 125-IN-L.G PAN-flD-POZI
SCRE-W·-·MACH /,,--32 • 25-IN --LG PAN -HD -POZI
SCREW-MACH 6--32 .25-IN·-LG PAN--Hll'-POZI
NUT---HEX-DBL -·CHAM 6--32--THD .094·-IN-TliK
NIJT-HEX-DBL-CHAM 6-32--Trm .094--IN·--THK

00000
DO 000
00000
00000
00000

ORDER
ORDER
ORDER
ORDER
ORDER

WASI-IER-·fL NM NO.6. 141 --IN'-ID .375--IN-"OD
WASHER---FL NM NO.6 .141-IN---ID .37S-·IN--OD
WASHER -FL NM N(). 6 .141--IN--ID .375·-IN-OD

28480
284BO
2F.l4BO

3053-0003
3050-0003
"3053-0003

INDUCTOR--120 OIJH
INDllCTOR-6BnUH
INDUCTOR -b80IJI-t

28480
28480
28480

9140-0622
9140-0620
9140--0621

5
1

I
2

2
4
9
8

1901-·0050
1901-0050
1901-'0050
1901-0028
1901-·0050

3
3
3
5
3

CR6
CR7
CRI3
CR9
CR10

1901'-0050
1901-0028
1901-0028
1901.-0051
1901-0535

3
5
5
4
9

nst

1990-061.2

HI
H2
H3
H4
H5

0590-0076
0590-·0076
0590--0076
2200-0121

26654
rY)h54
20480
26654
'5():?B9

8

0180--0197

2t.!OO-0121

28480

.IUF +80-20% 100VDC C:ER
.IUF +80-20% 100VDC CER
lUF +80-20% SOVDC CER
.WF +80--20% I aOVDC CER
2. 2IJF->--1 0% 20VDC TA

8

Clio

I

s
3

1

I

I
I

4
4

Mfr Part Number

CON1ROl. "pc ASSEMBLY

8

CRI
CR2
CR3
CR4
CR5

Mfr
Code

CAPACITOR-·FXD
CAPACITOR "F"D
CAPACITOR'-FXIl
CAPACITOR -F"D
CAPAcnOR---rXIl

3

9
8

Description

3

:?OOMA
200MA
200MA
750MA
200MA

28480

HI.
H7
H8
H9
HID

2200-0121
2360-0113
2360-0113
2420-0003

4
2
2
7
7

HI1

3050--0003
3050-0003
3050--0003

3
3
3

L2
L3

9'140'-0622
9140-D620
9140-0621

9
7
8

HPI
MP2

'205-0373
1205-0373

7
7

2

fir::AT SINK SGL PLSTC '-'PWR -CS
HEAT SINK SGL PLSTC-PWR--CS

13103
13103

I,,030B---1T
6030B-TT

QI
&12
&13
&14
&15

1853-0020
1854-0215
1854-0215
1853-0468
1853-0020

4

2
2

TRANSISTOR
TRANSISTOR
lRANSISTOR
TRANSISTOR
TRANSISTOR

28480
04713
04713
01295
284BO

1853-0020
2N:1904
2N3904
TIP--12?
1853-0020

RI
R2
R3
R4
R5

0757--0415
0757-0426
0757-0280
Dl>9B-3405
0757-0402

9
3
4
1

R6
R7
RB
R9
RID

0757--0426
0757-0280
07:17-1090
0757-0402
0757-0280

Rll
RI2
R13
RI4
RI5
Rib
RI8
RI9
R20
R21

HI2
H13

1.1

2420-0003

I

1
4
4

3

1

PNP
NPN
NPN
PNP
PNP

SI PD=300MW FT=150HHZ
51 PD=350M'" FT=300MHZ
SI PD=3501'fW FT=300I'lHZ
SI DARL TO---220AB PD=65W
51 PD=300MW FT=15DMHZ

BY
BY
BY
BY
BY

DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION

RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR

47S 1% .125W r TC=0+-100
1. 3K 1 X • 125W F TI:=O+--I 0 0
IK 1% .125W F TC=0+-100
422 IX .SW F TI:=O+-IOO
110 1% .12SW F TC=0+-100

24546
24546
24541.
:284130
24546

C4-1/8--TO-47SR-F
C4-'-\/8-TO-'-1301 --F
C4-1 IB--TO-l 0 0 I-F
069S'-3405
C'\-'I/B-TO-lll-F

9
3
5
I
3

RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR

1.3K IX .125W F TC=O+--IDO
lK 1% .125W F TC=0+-100
261 I X .5W F TC=O+·-1 DO
110 1% .125W F TC=0+-100
IK IX .125W F T[;=D'-100

24546

24546

C4-\/8-TO-1301-F
C4-·1 IB--TO-I 0 0 l--F
0757-1090
C4-1/B-TO-Il1--F
C4-I/B-TO-l001-F

0757-0280
0757-0438
0757-0283
0757-0Z80
0757-0418

3
3

RESISTOR
RESISTOR
REsrSTOR
RESISTOR
RESISTOR

IK 1% .125W F TC=O+--IOO
5.11K 1% .125W F TC=O+---IOO
2K 1% .125W F TC=O+-IOO
lK IX .125W F TC=D>-100
619 IX .125W F TC=O+-IOO

24546
24546
24546
24546
24546

C4-1/B-TO-1001-F
C4-·-I/B-·TO--51 I 1--'F
C4-1/8-TO-2001-r
C4---1I8-TO-'-1001-F
C4-1/8-TO-619R-F

0757-0280
0757-0281
0757-0458
0757-0442
07:17-0481

3
3

RESISTOR
RESISTOR
RESISTOR
RESISTOR
RF.:SISTOR

lK IX .125W F TC=0+-100
1~ 1% .125W F TC=0+-100
51.1K 1% .12l;W F H:=0+"-100
10~ IX .125W F TC=0+-100
475K IX .H.'5W F TC=O+"'IOO

24546
24546
24546
24546
19701

C4-'-1/8-'TO-IOOI---F
C4-1/B-TO-1001-F
C4·-1/8-TO-51 12- F
C4-1/B-TO-I002--F
MF4CI/8-TO-47:13---F

6

1
2
B
1
2

6

3
9

9

2
4

6

2

7

2454~J

284130
24546

See introduction to this section for ordering information

PS 6-11

Model 64100A - Replaceable Parts
Table 6-2. Replaceable Parts List A4 (Cont'd)
Reference
Designation

c Qty

HP Part
Number

0

R22
1123
R24
R25
R26

0757-0465
0757-0438
0757'-0472
0757-0465
0757-0442

b
3
5
6
9

R27
R28
R30
R31

0757-0280
0757-0413
OBl1-1659
0757-·0284
0757-0465

3
4
8
7
6

R32
R33
R34
R35
R36

0757·-0452
0757-0458
0757'-0465
0757--02Bl
0757·-0448

1
7
4
5

1

R37
R3B
R39
R4D
R41

0698--0085
0757-·0472
0757-0442
0757-0491
0761-0010

0
5
9
b
b

1

Ul
lI2
U3
U4
U5

1820-"1577
1820-·2019
lB26·-0346
H:l26--0bBO
1826···0600

9
b
0
5
5

UI>

5
5

U9

1£126-0680
lEI26·-0I>110
H126-0221
1818-0277

0
9

1
1

XU4
XU5
XU6
XU7

1200-0796
1200-0796
1200-0796
1200-0796

B
8

4

Ri:!9

U7
US

4
1
2

I
1
I
1

IJ

B

B

1

1
1
I
1

4

Description

Mfr
Code

RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR

lOOK IX .125W F TC-O.'·-IOO
S.11K u: .125W F TC=O +-100
l!OOK 1:C .125W F TC=O+-IOO
lOOK n. .125111 I' TC=0+-'100
10K IX .125W I' TC-0"·-l00

24546
24546
24546
24546
24546

C4-'I/8"'TO-I003 -F
C4-1/8-TO-S111-F
C4-·1/8····TO-2003···F
C4···1 18-TO-I 003-1'
C4"'1/8-TO--I002-'F

RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR

1~ n. .125W F TC=O+-IOO
392 1:C .125W F TC=O+'-I DO
.27 5:C 2W Pili TC=0+'-800
150 1:C .125W F TC-Ot-IOO
lOOK n. .125111 F TC=O+-IOO

24546
24546
75042
24546
24546

C4-1/B-TO-IOOI-F
C4-·tlB···TO-392R-F
BWH2"'27/100-J
C4··tll3-·TO-151 ···F
C4-'1 19-TO-I 003-1'

245·46
24546
24546
?4546
24546

C4-·1 IB-'TO-2742" F
C4'-1 IB-TO'-51 12·-1'
C4"'1/8'-TO-l 003'F
C4"'! IB'-TO'-2741 '-1'
C4-'1 IB···T 0-t82;!- F

245·46
24546
24546
19701
28460

C4-1/B-TO-2(,tl-F
C4"'1/8--TO--2003'-F
C4'-1 IB···TO·-1 0 C2-F
HF4Cl 18-T 0···4753-·F
071,,1"-0010

01929
04713
27314
2B4130
2I;J4BO

CD4093BF
MCt45B41lCP
LM358N
1826'-0690
1926-0690

IC B-DIP-P PKG
Ie S--DIP -P PKG
IC -··12 v Rr.LTR TO-·220
RES NETWORK i.~, 2K X 9

28480
28480
04713
28480

1926-06BO
1926-06BO
MC7912CT
1810-,11277

8
8
8
8

28480
28480
284BO

1200-0796
1200,-0796
1200·-0796
1200"-0796

RESIST!IR 27.4K 1% .125W F TC=0+-100
RE8ISTOR 51.1~ t:c .125111 I' TCe O+-l00
RESISTOR lOOK IX .125W F TC-0+-l00
RESISTOR 2.74K n. .125W F TC=O+-IOO
RESISTOR HI.~K a .125W F TC-O+-IOO
RESISTOR
RESISTOR
RESISTOR
RF.:SIf.iTClR
RESISTOR
IC
IC
lC
IC
Ie

a

2.6H

.125111 f

Te=O+-IOO

20DK IX .125W F TC-Ot-l00

n.

10K
.125111 F TC=0+-100
475K t:c .1~5W F TC=0+'-100
l.f:1K
lW 1'10 TC=0+"'200

5"

SCHMITT-TRIG CMOS NAND QI.IAD 2·-INP
SCHMITT·-TRIG CMIlS HEX
OP AMP GP DliAl. B···DIP .. p PKG
8 ..·DIP·-P PI(G
B-·DIP -P PKG

PIN
PIN
PIN
PIN

DIP
DIP
DIP
DIP

SOCKET
SOCI(ET
SOCKET
SOCKET

28480

See introduction to this section for ordering information

PS 6-12

Mfr Part Number

Model 64100A - Replaceable Parts

Table 6-3. List of Manufacturers' Codes
MFR NO.
00000
00466
01121
01295
01928
03888
04713
07263
09023
13103
19701
20940
24546
26654
27014
27777
28480
30983
32997
34344
34649
56289
71590
72136
75042
75382
75915

MANUFACTURER NAME
Any Satisfactory Supplier
Norelco N. Amer Philips Corp
Allen-Bradley Co
Texas Instr Semicond Div
RCA Corp Solid State Div
lIDI Pyrofilm Corp
Motorola Semicond Products
Fairchild Semicond Div
Cornell-Dubilier Eleck Div
Thermalloy Co
Mepco/Electra Corp
Micro-Ohm Corp
Corning Glass Wks
Varadyne Inc
National Semicond Corp
Varo Semicond Inc
Hewlett-Packard Hq
Mepco/Electra Corp
Bourns Trimpot Div
Motorola Inc
Intel Corp
Sprague Elect Co
Centralab Eleck Div
Electro Motive Corp
TRW Inc
Kulka Elect Corp
Littlefuse Inc

ADDRESS

ZIP CODE

Los Angeles Ca
Milwaukee Wi
Dallas Tx
Somerville NJ
Whippany NJ
Phoenix Az
Mountain View Ca
Sanford NC
Dallas Tx
Mineral Wells Tx
El Monte Ca
Bradford Pa
Santa Monica Ca
Santa Clara Ca
Garland Tx
Palo Alto Ca
San Diego Ca
Riverside Ca
Franklin Park 11
Mountain View Ca
North Adams Ma
Milwaukee Wi
Willimantic Ct
Philade lphia Pa
Mt Vernon NY
Des Plaines II

90021
53204
75222
08876
07981
85062
94042
27330
75234
76067
91731
16701
90404
95051
75040
94304
92121
92507
60131
95051
01247
50501
06226
19108
10550
60016

PS 6-13/(6-14 blank)

Model 64100A - Manual Changes

SECTION VII
MANUAL CHANGES

7-1.

INTRODUCTION.

7-2. There is no backdating
pUblication of this manual.

information for the

power

supply

as

of

the

PS 7-1/(7-2 blank)

Model 64100A - Service
SECTION VIII
SERVICE

8-1.

INTRODUCTION.

8-2. This section contains the theory-of-operation for the power supply.
The
first part discusses the block diagram functions while the second part
elaborates on these functions by referring to detailed circuit schematics.
8-3.

BLOCK DIAGRAM THEORY (Figure 8-1).

8-4. PRIMARY RECTIFIER and FILTER BOARD (Al). This board provides the supply
with a rectified and conditioned "plus and minus primary DC rail, along with
transformation for control power.
The rails are used as the source for the
switching supplies. The Al board provides protection to the supply from AC
input surge current and overvoltage conditions.
Furthermore, this board
supplies the power for the forward mainframe fan and the internal cooling
fan.
8-5. PRIMARY BOARD (A2). The -5.25, +5 and -3.25 volt supplies are generated
on the Primary board along with some control and reference signals.
LED
failure indicators are installed for convenient troubleshooting references on
the Primary board.
8-6. SECONDARY BOARD (A3).
rectification and feedback
secondary board provides the
Motherboard.

The secondary board is responsible for filtering,
for the DC power supplies.
Furthermore, the
-5.25V, +5V, -3.25V, +12V and GND outputs to the

8-7. CONTROL BOARD (A4). LED failure indication and failure execution are the
main functions of the control board.
However, this board also creates LIR15,
LINE SYNC, +4ov, -12V, GSEN and +17V for the 64100A system.

8-8.

THEORY OF OPERATION.

8-9.

FILTER BOARD AND PRIMARY WIRING (Figure 8-7).

8-10.

110 VOLT OPERATION.

8-11. The primary side of T1 is stacked by S2 so there is effectively 220V
across it.
Outputs are in parallel.
The varistors (RV1 and RV2) on the
primary side of T1 are for transient suppression.
8-12. Because of the way that the neutral line is wired to the primary output
rails of the bridge rectifier (CR1) , only two of the diodes are being used.
These are the two that connect the hot AC line to the + and
outputs.
Configuratively, this produces -315 VDC across the primary rails. Also notice
that the neutral line does not have to be connected to the bridge diode for
normal operation at 110V.

PS 8-1

Model 64100A - Service
8-13.

220 VOLT OPERATION.

8-14. The windings on the primary side of T1 are wired in series by S2 so that
there is still 220V across them.
8-15. During 220 VAC operation, all four diodes of the bridge rectifier are in
use and the output across the primary is still -315 VDC. In this mode both AC
inputs to the bridge rectifier must be connected.
8-16.

SAFETY CONSIDERATIONS.

8-17. R2/c4 and R3/C5 have a time constant of 2 min. The primary bus has -315V
across it, + or - 160VDC to ground.
The main filter bank is a potential
hazard to life, even with the supply off!
8-18.

PRIMARY BOARD (Figure 8-7).

8-19.

DESCRIPTION (See Figure 8-4 for timing waveforms).

8-20. The Primary board consists of the three pulse width modulators PWM (U5,
U2, U4) and the switching circuitry for the primary side of the switching
transformers. It also includes some control circuitry.
As an overview, each
modulator requires four signals for proper modulation. A reference voltage, a
feed back voltage from the output to compare to the reference voltage for error
detection, feedback current from the output for output current limiting, and a
predetermined switching frequency.
The PWMs control the switching transistors
that alternate the current through the primary side
of the switching
transformers (TID-T15). Since all three PWMs are similar in operation, the +5V
PWM will be explained.
8-21.

OPERATION.

8-22. The PWMs modulate the output pulse width according to the demands of
the system.
In this manner they can control the amount of current each
switcher can deliver and therefore they control the power. In reference to the
+5V PWM, if the +5V feedback voltage going to pin 1, U5, is higher than the
reference voltage going to pin 2, U5, the PWM determines that the output
voltage is too high and reduces the pulse width to return it to within limits.
If the +5CL (Current Limit voltage determined by the voltage drop across L4, a
coil in the current return path of the +5V supply) becomes more positive than
it should, more current flows into pin 15, U5. The PWM detects this condition
and reduces the output pulse width for current limiting. The thermister (RT2)
is to compensate for the thermal characteristics of the coil in the current
return path of the +5V supply output. The potentiometer (R2) provides a means
for adjusting the current limit.

PS 8-2

Model 64100A - Service
8-23. Tile open collector outputs, U5 pins 8 and 11, are complimentary and
nonoverlapping.
For zero on-time (zero modulation time), both outputs are
high.
As demand increases, each output stays low (at different times,
nonoverlapping) for longer and longer until one is going high as the other is
going low or until one of the feedback signals limits the pulse duration. Each
output is inverted through u6, another open-collector device, and alternately
causes changing current through the primaries of T10 and Til.
These
transformers alternately turn Q6 and Q3 on and off which causes the current in
the primary of T7 to alternate. The signals +5A and +5B are used to prevent or
delay the switching of Q6 a,nd Q3. For example, suppose the following condition
exists. The power supply is experiencing a heavy demand and must allow close to
100% modulation to meet it.
Q6 has turned on per the request of the PWM and
has pulled the one node of T7 to the + primary rail voltage.
Then the PWM
tells Q6 to turn off and Q3 to turn on.
Q3 can turn on immediately, but Q6
cannot turn off that quickly because of charge storage considerations. The +5B
signal is a feedback signal from the secondary of T7 that senses this condition
and and will not allow Q3 to turn on until Q6 turns off and the voltage on the
secondary of T7 stabilizes.
To allow Q3 to turn on sooner would have the
effect of shorting the + primary rail to the - primary rail for a short period
of time may damage other components.
8-24. Other signals that have to be present for the PWMs to operate are: U5
pin 3 (FEEDBACK control) must be allowed to float. It is pulled high by several
error states to turn off the outputs. And U5 pin 4 (DEADTIME control) must be
held low.
It is forced high by several error states to turn off the outputs.
The 20 KHz switching frequency of the PWMs is determined by a Ric time
constant on pins 5 and 6 of u4. The 20 KHz clock is tied to all three PWMs
to switch them syncronously.
8-25.

PRIMARY PCB CONTROL CIRCUIT OPERATION.

8-26. As soon as the filter board is switched ON, CR20 rectifies the AC and
starts charging C35, a ripple filter for the +12V regulator U13. The output of
U13 lags the input by about 1V on power-up until it stabilizes at +12V. U13 is
the power supply +12C (a control power supply used only in the power supply
assembly).
+12C supplies U1 which is the +5 REF source. Observe the sequence
of events on power-up. As +12C first comes up (this happens very rapidly), C12
has not had time to develop a voltage drop across it and both sides are at
4.64v as determined by the zener diode CR27.
The collector of Q1 also goes to
pin 4 (DEADTIME control) of all three PWMs.
As C12 charges through R32 and
R13, the collector voltage of Q1 goes to Ov and allows the PWMs to gradually
modulate to 100% or until limited by some other signal.
8-29. The SHUTDOWN signal (which can be generated in several places) enters
this circuit between R13 and R32 and is used for the following purpose:
Suppose there was a momentary power interruption that caused the power supply
to start its shutdown procedure and then the power came back on. When SHUTDOWN
was generated on powerfail, C12 was discharged immediately so that if power was
quickly restored, DEADTlME would be high and would not allow the PWMs to
attempt to draw a huge surge current to recover. Once again, as DEADTIME goes
low (according to the time constant of C12 x [R32+R13]) the PWMs are allowed a
greater and greater percent of modulation unless limited by some other signal.

PS 8-3

Model 64100A - Service

~

8-30. u8 and U9 are overvoltage sensors.
Both of them will turn ON an LED if
an error condition is detected and both of them will generate SHUTDOWN.
They
work in the following manner:
TH2 is a line that is normally grounded by a
thermal switch on the Secondary board and travels through a jumper trace on the
Control board to U8 on the Primary board.
This is used to detect several
errors; first, if the temperature of the heat sink on the secondary board
exceeds 105 C then the thermal switch opens and an error is detected, second,
if the control board is removed for service, an error is detected, third, if
one of the boards is not plugged into the edge connector, an error is detected.
If any of these three errors are detected by U8, it turns on the TH LED and
sets SHUTDOWN high.
U9 works in a similar fashion except that it detects its
errors via T2.
The primary side of T2 is in the return loop to the "Minus
Primary Rail" for all three switchers.
The change of current through the
primary of T2 establishes a voltage drop in the secondary, rectified by CR19,
divided by R43 and R71, and detected at pin 2, U9. If the voltage at pin 2, U9
is greater than -+2.6v, (a slight delay is provided by C20), U9 latches and
turns on the Primary Current Limit LED and sets SHUTDOWN high.
8-31. The rest of the control circuitry on the Primary board has to do with
the -5.25 CL which is slightly different than the other two PWMs.
One of the
considerations of this supply is that when the -5.25 supply is down, the others
are also disabled. This is done to protect the Dynamic RAMs. So when -5.25 CL
exceeds the limits set for it, pin 1, U12 goes high. This generates SHUTDOWN
and also forces the FEEDBACK control high on all three PWMs.
Notice also that
if SHUTDOWN is generated elsewhere, it forces the FEEDBACK control high on all
three PWMs.
8-32.

SAFETY CONSIDERATIONS.

The primary bus has -315VDC across it and can supply 400 Watts of power.
The
main filter bank contains a lot of energy and is a potential hazard to life,
even when the supply is off!
8-33.

SECONDARY BOARD (Figure 8-10).

8-34.

OPERATION.

8-35. The three switching supply secondaries are relatively simple.
supply will be used for an example of this boards' operation.

The

+5V

8-36. The alternating voltage on the center tapped secondary of T7 is full
wave rectified by two schottky diodes (CR8, CR9) mounted on a heat sink. The
R5/c4 combination is a snubber network that limits the "dv/dt" to protect the
diodes.
+5A and +5B are taken from here to prevent both switching transistors
from being on at the same time and shorting the + and - primary rails together.
L3. C5. and c6 are the filter for the supply. The voltage drop across L4, in
the return path, provides the signal +5CL for current limiting.
The gate
current for the SCR Q3 is called +5CB (crowbar) and is generated on the Control
board.

PS 8-4

Model 64100A - Service

8-37. Except for polarity and the lack of an SCR, the -3.25 supply is the same
as the +5V supply.
8-38. Except for polarity considerations and the addition of Q1 and
-5.25V supply is the same as the +5V supply.

U1,

the

8-39. Q1 and U1 combine to form an active minimum load for the -5.25V supply
under the following conditions:
Suppose that the -5.25V supply has an
extremely light load on it.
In this case the switcher for the -5.25V supply
might have a very narrow duty cycle or indeed it might skip several cycles
before it turns on again to supply the -5.25V.
If this happens, because the
-5.25V secondary also supplies the +12V,+17V, and +4ov, these supplies can lose
power and go out of regulation.
The integrator, C7 and U1, detects that the
switcher has been off for several cycles and causes Q1 to load the -5.25V
supply causing the -5.25V switcher to increase its duty cycle.
CR2/U2 is the
rectifier/regulator for +12VDC.
CR1 rectifies for the +17VDC supply and also
for U1, a SHUTDOWN generator. There are also secondary windings for the +40VDC
supply.

8-40.

SAFETY CONSIDERATIONS

8-41. The secondary circuits can supply high current.
The three heat-sinks
for the secondaries could be very warm.
Also, the primary sides of the
switching transformers (T10-T15) are connected to the primary rails.
These
rails are a potential hazard to life even with the supply off!

8-42.

CONTROL BOARD (Figure 8-10)

8-43.

OPERATION.

8-44. u4, U5, and U7 are overvoltage protectors (OVP) that wlrk in the
following manner:
when the voltage at pin 2 exceeds the voltage at pin 7 by
+2.6v, the output pin 8 latches high to turn on the failure LEDs and, in the
case of the +5 and -5.25 volt supplies, to supply current to crowbar the
respective circuits.
Also, whenever anyone of the OVPs turn on, pin 6 goes
low drawing current through R1, turning Q1 on and producing SHUTDOWN.
The
capacitors on pin 3 and pin 4 of the OVPs determine the minimum amount of time
that the error has to exist before they turn on, a means of transient
protection.
8-45. U1 and U2 combine to provide the signal Low Interrupt Request 15 (LIR15)
to the I/O board.
This signal goes low to signal the CPU that a powerfail has
been detected. U2 and Q2 provide Low Power On Pulse (LPOP) to the mainframe.
This signal goes low for a short time during power-on to initialize circuitry.
U2 and Q3 provide Line Sync (LINE SYNC). This signal enables a square wave at
the same frequency as the line. U1 and U2 are CMOS devices.
8-46. The signal THERMAL comes onto the power supply from the secondary board.
There is a jumper trace installed in-line, and it leaves this board as TH2 to
go to US, OVP sensor, on the Primary board. In normal operation this line is
at or near ground.
If the thermal switch opens or the interconnect cable P2 is
removed, SHUTDOWN will be generated on the Primary board and the TH LED will be
ON.
PS S-5

Model 64100A - Service
8-47. u6 provides voltage ratio protection in case
the +12, +5 and -5.25 volt supplies. For example:
drops between R10, 11, 12 should change, resulting in
over pin 7, then pin 8 would turn on the RATIO
SHUTDOWN.
This is important because a loss of one
would cause substrate damage to mainframe memory.

of a loss or reduction of
if the sum of the voltage
a +2.6v increase of pin 2
LED and in turn produce
of the the ratio voltages

8-48. CR9 is the rectifier for the 40 VDC supply.
Q4 is the regulator.
Q5
and R29 form the high level current limiter that turns Q4 off if the current is
too large.
U3 is the overvoltage sensor that will turn Q4 off if the voltage
formed by the voltage divider R36/37 goes too high.
U3 and C13 form an
integrator that limits the average current through Q4.
8-49.

SAFETY AND HANDLING CONSIDERATIONS.

8-50. The power supply boards contain CMOS devices. Cl1 in the 40v supply will
remain charged after the supply is shut off!

PS 8-6

Model 64100A - Service
8-51.

MNEMONICS.

Table 8-1. Mnemonics
Mnemonics

Description

CB

Crowbar

Used by the -5.25V and the +5V supplies.
When crowbar goes high, the corresponding
SCR conducts, and effectively puts a short
across the supply, causing the supplies
to shutdown.

CL

Current Limit

Used by the +5V,-5.25V and -3.25V supplies.
Current limit is used by the supply as
feedback to the PWMs to determine if the
maximum current of the individual supply
is being exceeded. The current limit of
each switching supply is adjustable.

GSEN

Ground Sense

GSEN is used by the supply to determine
the voltage drop of the high current
carrying control ground, due to the
parasitic resistance of the Motherboard.
Then, this voltage drop is used to adjust
the +5V REF regulator.

LINE SYNC

Line Sync

LINE SYNC is processed from the line input
and used for timing throughout the
mainframe.

LIR15

Low Interrupt
Request 15

This signal is used as a power fail
indicator which is sent to the I/O board.

LPOP

Low Power On
Pulse

LPOP is generated shortly after the power
is turned on. This signal initializes
several ICs throughout the mainframe.

OV

Over Volt

Used by the +5V,-5.25V and -3.25V supplies.
If any of the above supplies should
increase enough to bring about a +2.6v
difference between pin 2 and 7 of u4, US,
or U7 on the Control board then SHUTDOWN
will be generated and the supplies will
turn off.

peL

Primary Current
Limit

PCL detects an unlinear surge of current
internal to the supply. If a surge is
encountered
then
a
shutdown is
initiated.

PS 8-7

Model 64100A - Service
Table 8-1. Mnemonics (Cont'd)
PON

Power On

PON is generated on a power up of the
system. This signal is used for
initializing the LIR15 circuitry.

RATIO

The ratio signal is used in detecting
loss or reduction in the +12V,-5.25V and
+5V supplies and generating SHUTDOWN.

SHUTDOWN

SHUTDOWN is generated in several places
and is responsible for turning off the
PWMs by pulling U2, u4, U5 pin 3 high.

SYNC

Sychronize

AC line frequency and sync are the same.

TH

Thermal

Thermal, TH and TH2 all relate to the
thermal switch located on the secondary
board. The switch will open when the
internal temperature of the supply is
greater than 105 degrees C. Also, the
TH LED will be indicating a problem.

+5 REF

+5V Reference

This signal is used throughout the supply
and provides a stable reference voltage
for the PWMs.

+12C

+12V Control

+12C is the control signal used throughout
the supply. If +12C is not up the supply
will not operate.

PS 8-8

Model 64100A - Service

SECONDARY BOARD A3

r---------..,

I-~-------------~----------------------~-I
~

l o o N
N
I"~
10
Z
I'll....
In.
+
C)
I
+

10
I

I

I

I
I

+12C

I ,
I "

+12

I
I
I
I

,

'- - - - - - - -,..... - - - - - - - - - - - - - - f- - - - - - - - - - - - - - - - _.J

+5

+5 REF

OUTPUT

+5

-3.25 OUTPUT

/1' "

-5.25 OUTPUT

SHUTDOWN

I
I
I

"
/

"

/

CONTROL
BOARD

-,
/

A4

+5C8

l' Y

-5eB
-5

"

/

-3

"

r-----'

"

1

/

PON

/

"
SYNC

I

-12R

Z

FAN

....
a::

D...

.
<:

.

<:
N

....+

10

+

:3

o
o

--l
U
10

I-

U

::l

N

I

(I)

:c

N

10

+

:c

I-

Z

o
n.

u
>Z

(I)

F1
AC LINE

RAILS

+5
:t PRl
.. SWITCHER 1""'1 +12C'"

-3.25
:t PRl
SWITCHER... +12C~

-5.25
SWITCHER

PRIMARY

,..

AND
FILTER BOARD

1
1

I

1

-1-17

I,
'/
I

I
I
I

40A. 8

I

I
I
I

I

+40

I

THERMAL

I
I
I

RECTIFIER

I

+17R

I

GSEN
1
LlNESYNC:

1

I

I

1
1
I

I "

-12

,

I):

1

1 /

I
I

,

:t PR1

1---'-1- LPOP
r---rl-

l--------f---f---------f---f-----------f---I--'-------------i-----I----1-----,
CD
I-

I

PIO Pl

1
I UR15

./

FORWARD

1

TH2

1

I

I

1

-12

+ 17

1

,

I
1
I

1

,,'

,

'/'

1

I
I

"
/

I
I

1 ",

1 /
I
I

-1-40

L _____

I

1
I

.J

t ___.______ J

A1

....

CONTROL

PRIMARY BOARD AZ
FAN
1/82

INTERNAL

Figure 8-1.
Power Supply Block Diagram
PS 8-9

Model 64100A - Service
Table 8-2. P2 Board Connections
Pin
Label

+12C
SENSE GND
-12R
+17R
+17R
+5REF
+17R
-5CB
-3CL
-3A
+12
RETURNGND
-3B
RETURNGND
-5CL
RETURNGND
-12
SHUTDOWN
TH2
+5CB
THERMAL
+5
+12B
CUR.SEN.GND
+12A
-3
-5.2
40B
CONTROLGND
40A
PON
+5B
SYNC
+5A
+5CL

P2
Pin No.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

A2
Primary Bd

A3
Secondary Bd

A4
Control Bd

X
X

X
X
X

X
X
X

X

X

X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X

X

X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X

X
X
X
X
X
X

X
X
X
X

NOTE: An X on a given Pin Number denotes a line connection.

PS 8-10

X
X
X
X

Model 64100A - Service
NOTE

The waveforms below relate to the +5V switching supply. The numbered
stars below represent the signals seen at the location of the numbered
stars on the schematics (Figures 8-7 and 8-10). Note that the same
signals can be seen on the corresponding parts on the -5.25V and
-3. 25V supplies.

REMOVE THESE
SCREWS TO GAIN
ACCESS TO THE
FilTER BOARD (A1)

REMOVE THESE
SCREWS TO GAIN
ACCESS TO THE
FilTER BOARD (A1)

1!r Top

waveform - The primary of T7 with
the +5V supply loaded; this signal
320V p-p.

t!r Middle

waveform - The signal shown is
the output of U5 pin 8 at 12V p-p.

~Bottom waveform - This signal is the

other output of U5 pin 11 at 12V p-p.

INTERNAL
-"'--""""-FAN

1!1ToP waveform - The signal on the
the left is the anode of CR8.
Note: These signals are with
the +5V supply loaded.
1!1Bottom waveform - This signal is on
the cathode of CR8.

1!r This

waveform is the primary of T7
with the +5V supply unloaded.

W1

Figure 8-2.

P2

+5 -5

TH PCl -3 -12 +12 R3

R2

R1

PRIMARY SUPPLY
BOARD (A2)

Board Placement and Partial Component Locator

Figure 8-3. Primary Filter Board Removal

Figure 8-4.
Timing Waveforms
PS 8-11

Model 64100A - Service

-3CL

8

1

5

A

r - ------.

Be)

4

I

C3

--R2--R3-

3

-R1--

0

0

o

5

T1

0

I·G

0

0

~

7
P2

C2

I

0

0

a::

1

C4

4 0

0

0

1 0

0

0

-RV1-

o1

BALUN

-R16-R17-C4-R6S-CSO-C4S-CS-R20.--C6R21 -R22-

6

-RV2-

00

I
M

I

I-

l-

a:: a::
I

I

CS

us

B

C

REF
DESIG

C-l
C2
C3
C4
C5
OSl
OS2

Figure 8-5.

I
I

D

GRID
LOC

REF
DESIG

A-4
E-4
8-3
8-2
E-2
C-1
0-1

R1
R2
R3
RV1
RV2
RT1
RT2

I
I

GRID
LOC

E-5
8-3
8-3
E-3
F-3
L-2
C-l

REF
DESIG

RT3
T1
T2
P1
P2

E

I

GRID
LOC

1

I.

I..

co

a:

Primary Filter Board Component Locator

T8P

P31000\

C36

1

P4

0

C37

C38

T9P

001

Pslo 0

01

C40

C41

C39

-C43-

---RS9---

--RS8--

--C44--

oo.~

REF
DESIG

---R44--U6

U3

•

Cl
C2
C4
C5
C6
C8
C9
Cll
C12
C15
C20
C2l
C22
C23
C24
C25
C26
C27
C28
C29

•

---R4S---

I.

U10
R46
-C26.

-

C27-

-C2S-C29 •
-R47-

I.

U11

-C30-CSS_
-CS6-R39-

GRID
Loe

REF
DESIG

•

•
---R49---

C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
C41
C42
C43
C44
C45
C46
C47
C48
C49

A

L

~---~--~

A2
A

B

c

D

E

F

I

GRID
LOC

REF
DESIG

I
C-8
A-7
A-6
A-5
A-5
A-4
A-4
A-2
8-7
8-1
8-5
8-5
C-4
C-4
C-4
C-4
C-3
C-3
C-3
C-3

-C31-C32-C33-

- - C1S--

1

I
I

-C22 •
_C23_
-C24--C2S_

- - - R 4 8 -_ _

•
U4

J

;

-R37-R2S- - R 3 S -R70- R30R31- C11U7
.C47-

0-1
0-4
0-2
0-5
F-4

T7P

-CR27- - C 4 S 1 - R27.... R41U9
~ - RS2- RS3-RS4_
_RSS_

_CS4_

2

64100-66515 PRIMARY SUPPLY BOARD

I·'" I

~

-CS3-CS1-

F

I /.

-R71-R43-C20_
C21 ~
_
CR9..! MP1
-CR10....!

64100-66514 PRIMARY FILTER BOARD
A

~I.I

fl
LJ -

L.Q1

U2

3

I

39 \-:_ _---,

P2

I

•

l iJ
A1

i!: 'I' 'I'

-C34CR17=-

-R69-'-R24-R2S-R26-CS_
-C9-CS2-

4
N

@ill

-=::,-. =:::::=

-C2• -R14_·
-R1S_C49_

T2

I-

~

los11

-CR7.
- CR8.

U1

I

7 0

5

...

~ ~ '?

I ~~~ I -C~6~ II

...1

0

-5CL

!!~l!
.,l!~b~·t~k~~ I
a: a:
a:a:@a:a:a:a:a:u(J(J(Ja; ~

P1

I

I

L- - - - - _ _ _

+5CL

G G G

G

Figure 8-6. Primary Supply Board Component Locator
PS 8-12

I

GRID
LOC

REF
DESIG

C50
C51
C52
C53
C54
C55
C56
CRl
CR2
CR3
CR4
CR5
CR6
CR7
CR8
CR9
CR10
CR12
CR13
CR17

GRID
LOC

REF
DESIG

8-6
C-6
C-5
E-5
E-4
E-2
F-4
F-3
F-2
C-6
C-5
C-5
C-8
C-8
L-5
E-4
E-3
E-2
F-4
F-3

MP7
Pl
P2
P3
P4
P5
01
03
04
05
06
07
08
Rl
R2
R3
R4
R5
R6
R7

A-6
8-3
A-4
8-3
8-3
8-2
8-1
C-8
C-8
C-8
C-8
A-7
8-7
8-7
8-7
8-5
8-5
8-5
8-5
C-7

CR18
CR19
CR20
CR21
CR22
CR23
CR24
CR25
CR26
CR27
CR28
CR29
OS1
OS2
MP1
MP2
MP3
MP4
MP5
MP6

I

GRID
LOC

REF
DESIG.

I

I

1
C-2
C-2
C-1
C-l
C-7
C-5
0-6
E-6
E-6
F-6
F-6
G-6
E-5
E-5
F-5
C-6
8-5
8-2
A-6
A-6

I

I

GRID
LOC

REF
DESIG

R8
R9
Rl0
R11
R12
R13
R14
R15
R16
R17
R18
R20
R21
R22
R23
R24
R25
R26
R27
R28

GRID
LOC

REF
DESIG

1

.1
F-2
E-l
E-8
0-7
E-7
F-7
C-6
E-4
E-3
E-2
F-4
F-3
F-l
A-8
8-8
8-8
A-8
A-8
8-8
8-8

I

.. 8-8
' 8-8
E)-8
8-8
8-8
C-8
A-6
A-6
A-6
A-6
8-6
A-5
A-5
A-5
A-7
A-5
A-5
A-4
C-6
A-3

R30
R31
R32
R37
R38
R39
R41
R43
R44
R45
R46
\R47
R48
R49
R52
R~3

R54
R5'S
R56
R57
R58'

I

GRID
LOC

REF
DESIG

F-5
E-4
E-3
E-2
F-4
F-3
F-2
C-7
C-6
A-6
A-5
A-3
8-6
A-8
A-7
8-8
0-5
0-4
0-4
0-3

T13U
T14L
T15U
Ul
U2
U3
U4
U5
U6
U7
U8
U9
Ul0
U11
U12
U13

R59
R60
R61
R62
R63
R64
R65
R66
R67
R68
R69
R70
R71
RTl
RT2
RT3
T2
T10L
T11 LJ
T12L

GRID
LOC

I

1
A-2
A-2
8-7
8-3
8-3
8-1
C-6
8-5
C-4
C-3
C-3
C-2
C-2
C-l
C-6
C-6
C-6
C-6
C-7
0-5
E-5

I

0-2
0-2
0-1
A-7
C-7
8-3
A-2
8-6
8-4
8-2
C-7
C-6
C-3
C-2
A-4
C-5

Model 64100A - Service

b~~\
8
(J
L4~
~
O

4

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-R6-

(+5)

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Cl4

88

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)

P3

0

P4

:~:~
~I (

B"

7

/

39
T9

a

-

R2 CR4_.
-CR3. _R18_
-Rl9- _--C16
R20 -_

rg
Ul

-C7- @01j
=-_ RIOR9 _. CRS_
R8- ~CR6-

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-R11-C2 -R2-R3-Cl-

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-64100-66517 SECl5'ONDARY POWER

-C10-

I ~"' I
a1 U2

- R24--RB - -

-CR2•-R20
-

L2

-R21-RS-

A

B

c

o

E

F

G

-C13-R33-R34-C16-R31-

-R9-CR3.!.

Oas

-CB-R39-R40- ra3
-R2S- \..::::i

-cs- CR1.!
- R19-R3S-

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e

-CRB ..!.

()
In
I

-C6-

R4 _ _

SUPPLY

•

-CR4-

-R12-

•

-R23- R7 - - R4 -

_ R6 _

-R7-

I.

\:.:Ju

CONTROL BOARD

U9-

-R1B-

!. CR10-

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64100-66528

o

V

Ul

U
~
~

8

R30 -

U1
U2
U3
U4
U5
U6
U7
U8
U9

C9

8-1

E-2
0-1
0-1
E-4 "
MP2

C-4
G-2
F-4

C-l
F-3

mounted on assembly
bly MPl
"ThesE; parts mounted on asse:
MP3
tThese parts mounted on asse bly
j tThese parts

Figure 8-8.

Secondary Board Componen t Locator

Figure 8-9. Contro 1 Board Componen t Locator

PS 8-14

R14
R15
R16
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R3l
R32
R33
R34
R35
R36
R37
R38
R39
R40
R4l

A-6
8-5
8-5
8-6

8-3
8-4
8-4

8-2
8-5
8-5

8-3
8-2
8-2
8-2
C-2
0-3
A-3
8-2
A-3
A-3
8-2
A-2
A-2

0-6
8-3

8-3
C-2
C-4
C-5
8-4
A-4
A-4
A-6
8-6

C-6
8-6

'7

MP3 T8

MP2T9 -------------

MP1 ----------------=---~

MP2 --------------~\~----~~~~~
MP3 ------------------------~------~~

MP1

T7 --------------~~

SECOND ARY
POW ER SUPPLY
BOARD

Figure 8 - 11. Locations of MP1 , MP2, and MP3 heatsink assemblies

~\

,

\

Note: Remove the screws and/or nut and lockwasher that go
with the faulty MP assembly. Also, the faulty assembly
must be ordered as a complete assembly. Each assembly
PiN is given in section VI, table 6-2.
Figure 8-12.

MP1, MP2, and MP3 Heatsink Assembly Removal

Model 64100A - Service

CR8

HEAT81NK

/

5

P3------------~

81

CR9

C4

Note: The MP1 and MP3 assemblies are nearly identical in component
locations.
Figure 8-13.

PS 8-16

Separate MP1 Assembly



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