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HP64000

Logic Development
System

Model 64110A
Mainframe

Fli:n-

HEWLETT

~a PACKARD

CERTIFICATION
Hewlett-Packard Company certifies that this product met its published specifications at the
time of shipment from the factory. Hewlett-Packard further certifies that its calibration
measurements are traceable to the United States National Bureau of Standards, to the extent
allowed by the Bureau's calibration facility, and to the calibration facilities of other
International Standards Organization members.

WARRANTY
This Hewlett-Packard system product is warranted against defects in materials and
workmanship for a period of 90 days from date of installation. During the warranty period, HP
will, at its options, either repair or replace products which prove to be defective.
Warranty service of this product will be performed at Buyer's facility at no charge within HP
service travel areas. Outside HP service travel areas, warranty service will be performed at
Buyer's facility only upon HP's prior agreement and Buyer shall pay HP's round trip travel
expenses. In all other cases, products must be returned to a service facility designated by HP.
For products returned to HP for warranty service. Buyer shall prepay shipping charges to HP
and HP shall pay shipping charges to return the product to Buyer. However, Buyer shall pay all
shipping charges, duties, and taxes for products returned to HP from another country.
HP warrants that its software and firmware designated by HP for use with an instrument will
execute its programming instructions when properly installed on that instrument. HP does not
warrant that the operation of the instrument, or software, or firmware will be uninterrupted or
error free.
LIMITATION OF WARRANTY
The foregoing warranty shall not apply to defects resulting from improper or inadequate
maintenance by Buyer, Buyer-supplied software or interfacing, unauthorized modification or
misuse, operation outside of the environmental specifications for the product, or improper site
preparation or maintenance.
NO OTHER WARRANTY IS EXPRESSED OR IMPLIED. HP SPECIFICALLY DISCLAIMS THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE.
.
EXCLUSIVE REMEDIES
THE REMEDIES PROVIDED HEREIN ARE BUYER'S SOLE AND EXCLUSIVE REMEDIES. HP
SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR
CONSEQUENTIAL DAMAGES, WHETHER BASED ON CONTRACT, TORT, OR ANY OTHER
LEGAL THEORY.

ASSISTANCE
Product maintenance 'agreeme(lts and other customer assistance agreements are available for
Hewlett-Packard products.
For any assistance, contact your nearest Hewlett-Packard Sales and Service Office. Addresses
are provided at the back of this manual.
CW&A 2/81

,,

HEWLETT-PACKARD
SERVICE MANUAL
MODEL 64110A
MAINFRAME

SERIAL NUMBERS
This manual applies directly to models with serial
numbers prefixed 2103A - 2138A.

©copyright Hewlett-Packard Company/Colorado Springs Division 1982
1900 Garden of the Gods Road, Colorado Springs, Colorado, U.S.A.
All Rights Reserved

Manual Part Number 64110-90901
Microfiche Part Number 64110-90801

PRINTED: MARCH 1982

SAFETY SUMMARY
The following general safety precautions must be observed during all phases of operation, service,
and repair of this Instrument. Failure to comply with these precautions or with specific warnings
elsewhere In this manual violates safety standards of design, manufacture, and Intended use of the
Instrument. Hewlett-Packard Company assumes no liability for the customer's failure to comply
with these requirements.

GROUND THE INSTRUMENT.
To minimize shock hazard, the instrument chassis and cabinet must be connected to an electrical
ground, The instrument is equipped with a three-conductor ac power cable. The power cable
must either be plugged into an approved three-contact electrical outlet or used with a three-contact
to two-contact adapter with the grounding wire (green) firmly connected to an electrical ground
(safety ground) at the power outlet. The power jack and mating plug of the power cable meet
International Electrotechnical Commission (IEC) safety standards.
DO NOT OPERATE IN AN EXPLOSIVE ATMOSPHERE.
Do not operate the instrument in the presence of flammable gases or fumes. Operation of any
electrical instrument in such an environment constitutes a definite safety hazard.

KEEP AWAY FROM LIVE CIRCUITS.
Operating personnel must not remove instrument covers. Component replacement and internal
adjustments must be made by qualified maintenance personnel. Do not replace components with
power cable connected. Under certain conditions, dangerous voltages may exist even with the
power cable removed. To avoid injuries, always disconnect power and discharge circuits before
touching them,
DO NOT SERVICE OR ADJUST ALONE.
Do not attempt internal service or adjustment unless another person, capable of rendering first aid
and resuscitation, is present.
USE CAUTION WHEN EXPOSING OR HANDLING THE CRT.
Breakage of the Cathode-ray Tube (CRT) causes a high-velocity scattering of glass fragments (implosion).
To prevent CRT implosion, avoid rough handling or jarring of the instrument. Handling of the CRT shall
be done only by qualified maintenance personnel using approved safety mask and gloves,
DO NOT SUBSTITUTE PARTS OR MODIFY INSTRUMENT.
Because of the danger of introducing additional hazards, do not install substitute parts or perform
any unauthorized modification of the instrument. Return the instrument to a Hewlett-Packard
Sales and Service Office for service and repair to ensure that safety features are maintained.
DANGEROUS PROCEDURE WARNINGS.
Warnings, such as the example below, precede potentially dangerous procedures throughout this
manual. Instructions contained in the warnings must be followed.

I

WARNING

I

Dangerous voltages, capable of causing death, are present in this Instrument.
Use extreme caution when handling, testing, and adjusting.
88-2-1/76

Table of Contents - Model 64110A
TABLE OF CONTENTS
Section
I

Page

GENERAL INF'ORMATION ................................•......•. 1-1

1-l.
1-4.
1-6.
1-9·
1-16.

Introduction ..••...•.••
Safety Considerations ••
Physical Description .•...••.••
Mainframe Configuration ••
Instruments Covered By This Manual ..

1-21.
1-23.
1-25.
1-27.
1-29·

Mainframe Options .•.
Analysis Options .••
Rack Mounting .•.•.
Accessories Supplied ..
Accessories Available •.

1-3~. Recommended Test Equipment.
1-32. Level Of Service .•....•••..

II

.1-1
.1-1
.1-1
.1-3
••• 1-4

· .... .. 1-5

.1-5
.1-5

· .... .. 1-6
. .••. 1-6

.1-7
.1-7

INSTALLATION ..•......•...................................... 2-1

2-l.
2-3.
2-4.
2-6.

Introduction ..••••.•
Initial Inspection •.
Power Requirements ••
Power Requirements Worksheet ••.

2-8.

Power Cord .................... .

Site Selection and System Bus Operation ••.
Operating Environment .•
Storage Environment.
Original Packaging .•
2-18. Other Packaging ....
2-10.
2-12.
2-14.
2-16.

.2-1
.2-1
.2-1
.2-2
.2-3
.. .2-3
. ... 2-3
• •. 2-3
.2-3
.2-4

2-20. Assembly and Disassembly •••.••••••••..•••..••.•••.•.•• 2-4
III

OPERATION ................................................... 3-1

IV

PERFORMANCE TESTS.
4-l.

Introduction .....•.•.••.•..•..••.

4-5. Starting Performance Verifcation ..
4-8. PV Power-Up Event Sequence.
4-1~. Power-Up ROM Test .•
4-17. Power-Up RAM Test ••

.4-1
.4-1
.4-2
· ..... . 4-2

· ..... . 4-4
· ..... . 4-5

i

Table of Contents - Model 64110A
TABLE OF CONTENTS
Page

Section
IV

4-22. Using The PV Display Test •••
4-25. Using the PV-Tests Display ..
4-27. PV ROM Test.
4-33. PV RAM Test.
4-39. PV I/O Write Test ••
4-45. PV I/O Read Test •••
4-5l. PV Time Interrupt Test.
4-58. PV Keyboard Test •.•.•••
4-64. PV System Bus Test ••••••
4-70. RS232 Test Procedure •••.

V

Introduction ••.•••••••••
Safety Considerations •••
Direction Standard.
+7V Adjustment .••••
Display Adjustments.

REPLACEABLE PARTS LIST.

6-9.

Introduction •••
Abbreviations ••
Replaceable Parts List ••
Ordering Information •••.
Direct Mail Order System.

6-12.
6-13.
6-14.
6-15.

Power Supply Removal ••••••••.•...•
Primary Board Removal •••.•••••••••
+5/+12 Volt Supply Board Removal .•
-3/-5 Volt Supply Board Removal.

6-l.
6-3.
6-5.

6-7.

6-16. Interconnect Board Removal ..
6-17. CRT Display Removal •••••.•..

VII

ii

.4-10
.4-11
.4-11
. .••. 4-13
.4-13
.4-15
.4-16

ADJUSTMENTS. • • • • • . • • • • • • • • • • • • • • • • • • • . • • • • • • • . • • . • • . • . • • . . • • 5-1

5-l.
5-4.
5-6.
5-8.
5-10.
VI

....... . 4-6
· .4-7
. ........ . 4-9

M.AN'UAL CHANGE s.

·5-1
·5-1
·5-1
.5-1
· ·5-2
.6-1
.6-1
.6-1
.6-1
• .6-1
· .6-2
.6-4
.6-4
.6-5
.6-5

.6-7
.6-6

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Table of Contents - Model 64110A
List of Illustrations
TABLE OF CONTENTS
Section
VIII

Page
SERVICE ..................................................... 8-1

8-l.

8-4.
8-6.
8-9.
8-33.

Introduction ......................................... 8-1
Safety Cons iderations ................................ 8-1
Mainframe Ov'erview ................................... 8-1

Mainframe Ov'erall Block Description .•...•••••.•..•••. 8-2
Mainframe Ov'erall Troubleshooting .•••.••....••••••••• 8-9

8-48. Power Supply Block Description ••.••.••...•••.••.•••• 8-38
8-79. Power Supply Schematic Description •.••..••••.•...••• 8-45
8-122. Power Supply Troubleshooting ••••••...•...•.•.•...••• 8-51
8-162. CPU/IO Block Description ..••••••••.•.••••••.••..•..• 8-61
8-205. CPU/IO Schematic Description .•.•••••..••••....•.•.•• 8-69
8-320. CPU/IO Troubleshooting .•.••.••.••....••••..••••••••• 8-86
8-321. Display Controller Block Description .••..•••••••••. 8-109
8-335. Display Controller Schematic Description .••....•... 8-113
8-348. Display Controller Troubleshooting ..••..•.•........ 8-114
8-354. Display Driver Block Description •.••.•••.••••••••.• 8-155
8-357. Display Driver Schematic Description .•...••••.•••.• 8-155
8-373. Mn.emonics •.•.•••....••.••••.••.•.•.•••.•.•••••••••. 8-161
LIST OF ILLUSTRATIONS
Figure

Title

Page

1-1.
1-2.

Mainframe Dimensions ....•••....••.•...•................. 1-2
Mainframe Configuration ..•.•.•.••..•.....•••...••.••..•• 1-3

4-1.
4-2.

Rear Panel Switches ..................................... 4-1
PV Display-Test ......................................... 4-7

4-3.
4-4.

PV-Tests Display ..........•..•.••..................•.••. 4-8
Keyboard Test, Key Sequence ..•••..•...••.••..•....••.•. 4-14

5-1.

Display Test Pattern .•.•.....•.••.••.••....•....•••••••• 5-3

6-1.
6-2.
6-3.
6-4.
6-5.

CRT Display Discharge Point ..•••...•.•.•...•.•.......•.• 6-9
Top Cover Parts Locator .•..•.......•.•.......•.••••.••. 6-33
Bottom Cover Parts Locator ..•••••..••••.•••..•.••.•.••• 6-35
Cardcage Parts Locator .•....••.••..•.•...••....•••••••. 6-37
CRT Parts Locator ......••........•...............•.•... 6-39

iii

List of Illustrations - Model 64110A
LIST OF ILLUSTRATIONS
Figure

Title

Page

6-6.
6-7.
6-S.
6-9.
6-10.

Keyboard Parts Locator ...............................•. 6-41
Power Supply Parts Locator ....•.....•.................. 6-43
Mainframe Cables Parts Locator ......................... 6-45
Power Supply Subassemblies Parts Locator ............... 6-47
Primary Board Component Locator •..•..•........•....•... 6-49

6-11.
6-12.
6-13.
6-14.
6-15.

+5/-12 Volt Board Component Locator ...........•..•.•.•. 6-51
-3.25/-5.2 Volt Board Component Locator ................ 6-53
Interconnect Board Component Locator ..............•.... 6-55
Motherboard Component Locator .......................... 6-57
CPU/IO Board Component Locator ......................... 6-59

6-16.
6-17.
6-18.
6-19.
6-20.

CPU/IO Board Mechanical Parts Locator .........•........ 6-61
Keyboard Component Locator ....•.•...................... 6-63
Display Controller Board Component Locator ............. 6-65
Secondary Drive Board Component Locator ................ 6-67
Transformer Flyback Board Component Locator ............ 6-69

6-21. Rear Board Component Locator ...•....................... 6-71
8-1.
8-2.
8-3.
8-4.
8-5.

Mainframe Overall Block Diagram .•....................•.. 8-7
Power Supply Block Diagram .......•..................... 8-43
Power Supply Schematic ..•.............................. 8-57
Motherboard Schematic •..•.............................. 8-59
CPU/IO Block Diagram ...••............................•. 8-67

8-6.
8-7.
8-S.
8-9.
8-10.

CPU Clock Generator Timing ..•.......................... 8-70
Typical Write Memory Cycle ...........................•. 8-71
Typical Read Memory Cycle ...••.•....................... 8-72
Typical I/O Read and Write Cycle ....................... 8-72
HP-IB Signal Lines .•...••............................•. 8-81

8-11.
8-12.
8-13.
8-14.
8-15.

HP-IB Handshake Timing ..•.......•..............•....••. 8-81
CPU, CPU/IO Schematic ..........•...............•....... 8-95
Peripheral Address Decoder, CPU/IO Schematic ........... 8-97
ROM, CPU/IO Schematic .................................. 8-99
HP-IB Controller, CPU/IO Schematic .................... S-101

8-16.
8-17.
8-18.
8-19.
8-20.

Keyboard Scanner, CPU/IO Schematic ..............•..... 8-103
Keyboard, CPU /10 Schematic .•....................•..•.• S-105
LPOP Generator/Interrupt Logic, CPU/IO Schematic ...... 8-107
Display Controller Block Diagram ...................... S-111
System Clock/Generator, Display Controller Schematic .. 8-147

8-21.
8-22.
8-23.
8-24.
8-25.

Character Address Ctr/Mux, Display Cont. Schematic .... 8-149
Character Generator/Latches, Display Cont. Schematic .. 8-151
RAM, Display Controller Schematic ........•...•.•...... 8-153
Horizontal and Vertical Sync Waveforms .........•...... 8-158
Display Driver Block Diagram ...................•.•.... 8-161

iv

List of Tables - Model 64110A
LIST OF ILLUSTRATIONS
Figure

Title

Page

8-26. A6 and A7 Boards, Display Driver Schematic ...•.•...... 8-163
8-27. Beeper, Display Driver Schematic •.......•.•..•.....•.. 8-165
List of Tables
Table

1-I.

Title

Page

1-2.
1-3.
1-4.

Ma in frame Opt ions ...............••.•........•.•......... 1-5
Accessories Supplied ................•................... 1-6
Accessories Available .•................................. 1-6
Recommended Test Equipment ......•....................... 1-7

2-I.
2-2.

Power Requirements Worksheet .....................•...... 2-2
Power Cord Opt ions ..............•.....................•. 2 - 3

4-I.

4-5.

PV Power-Up Sequence ............•....................... 4-2
PV Power-Up Beeper Sequence .....••...................... 4-3
Power-Up ROM Test Errors .........•........•.........•... 4-4
Power-Up RAM Test Errors ........•..........•............ 4-6
PV Display-Test Softkeys ........•....................... 4-7

4-6.
4-7.
4-8.
4-9.

PV -Tests Display Softkeys .......•....................... 4-8
PV ROM Test Errors .......•......•.......•.......•.....•• 4-9
PV RAM Test Errors ...•..........•...................... 4-10
I/O Read Test Errors ............•...•........•......... 4-12

5-I.

Display Adjustments ..........•..••..•..•................ 5-4

6-I.

Reference Designators and Abbreviations ............•.... 6-3
Mainframe Replaceable Parts List ....................... 6-10
Al Power Supply Replaceable Parts List ...............•. 6-12
A1Al Primary Board Replaceable Parts List .............. 6-13
AlA2 +5/-12 Volt Board Replaceable Parts List .........• 6-15

4-2.
4-3.

4-4.

6-2.
6-3.

6-4.
6-5.

6-6.

AlA3 -3/-5 Volt Board Replaceable Parts List .........•. 6-17
6-7. AlA4 Power Supply Interconnect Board
Replaceable Parts List .............. ; .................. 6-19
6-8. A2 Motherboard Replaceable Parts List .................• 6-20
6-9. A3 CPU/IO Board Replaceable Parts List .......•......... 6-21
6-10. A4 Keyboard Replaceable Parts List ..................... 6-24
6-11.
6-12.
6-13.
6-14.
6-15.

A5 Display Controller Replaceable Parts List ........... 6-26
A6 Secondary Drive Board Replaceable Parts List .......• 6-28
A7 Transformer Flyback Board Replaceable Parts List .... 6-30
A8 Rear Board Replaceable Parts List .........•......... 6-31
List of Manufacturers' Codes ..................•....•... 6-32

v

List of Tables - Model 64110A
LIST OF TABLES
Table
8-l.
8-2.
8-3.
8-4.
8-5.

Title

Page

,,8-5
Power-Up Failure - Beep Sequence Failing .•••••..•.•.••• 8-11
Power-Up Failure - Beep Sequence Passing •.....•....••.. 8-12
PV Menu Self-Test Failure ...........•••........•.....•. 8-13
Signature Analysis Test Loop Determination •••..•.•••••• 8-15

MemoI'Y Map .•.•••.•••.••.. " ..••...•..••..•.. " ..... " . " " " ..

8-6.
8-7.
8-8.
8-9.
8-10.

Signature
Signature
Signature
Signature

8-11.
8-12.
8-13.
8-14.
8-15.

Signature Analysis Setup E •.••••••.•••..•.••••..••••••• 8-28
Signature Analysis Setup F •••••••••..•.•..••.....••.••. 8-31
Signature Analysis Setup G••••.•••.••••••...•.••.•••••. 8-34
Signature Analys is Setup H.•.••.••..•••••...•.••••••••. 8 - 36
Power Supply Test Point Specifications .•.•.••••.•.••••. 8-54

8-16.
8-17.
8-18.
8-19.
8-20.

Power Supply Load Specifications •••..•.•••.......•..••. 8-54
I/O Internal Addresses ••.•••••••••..•.••••..•..•.••••.. 8-62
Decoder Enable Logic Truth Table .•.•••...•••.•••.•••••. 8-63
Beeper Decoder Truth Table .•.•••.•..•.••••.••••.•••.•.. 8-74
Card ID Decoder Truth Table ••••••••.•.•.••.••••••..•••. 8-75

8-21.
8-22.
8-23.
8-24.
8-25.

Slot Select Decoder Enable Truth Table .•••.•.•.•.••.••. 8-76
Interrupt Buffer Enable Truth Table ••.••.•.••..••.•••.. 8-76

System Bus Failure ............. "..... ".. "" ............. 8-16

Analysis
Analysis
Analysis
Analysis

Setup
Setup
Setup
Setup

A.•••.•••.••••.•..••••....•.•. 8-17
B•••.••.•.•.•.•••••...•.•.•••. 8-20
C••••••••..••.•.•....••••..••. 8-23
D............................. 8-26

Interrupt IO Code s .......... ".................. "....... 8 -78

PHI Control Logic Truth Table .••••.•••.•.•.••.••.•.••.. 8-79
Keyboard States .......... "..... ".......... "......... ".. 8-85

8-26.
8-27.
8-28.
8-29·
8-30.

ROM Troubleshoot ing ..................... "............ " .8-86

8-3l.
8-32.
8-33.
8-34.
8-35·

RAM Troubleshooting .... "............... ".............. 8-115
Simple RAM Failure Troubleshooting .•••••.•••••.••••.•. 8-115
RAM Refresh Failure Troubleshooting ..•••.•••••.••••••• 8-118
Display Troubleshooting ••••••..••••.•.••••••••..•••.•. 8-120
Display Controller Troubleshooting ..•.•.•...•••..••••• 8-120

8-36.
8-37.
8-38.
8-39.
8-40.

Signature
Signature
Signature
Signature
Signature

vi

Worst Case Troubleshooting •.••••...•..•••••.•••••.•.••• 8-88
Power-Up ROM Test ......•.•................ " .......••... 8-89
Signature Analysis Setup I. ............................ 8-90
Signature Analysis Setup J .••••.•..•...••••••..•••••••. 8-92

Analysis
Analysis
Analysis
Analysis
Analysis

RAM Failure Summary .••••....••.•.•. 8-122
Setup K.••..••.•••.••••.••••••••••. 8-124
Setup L.•••.••..••..••.•.••.••••••• 8-126
Setup M••.••••..•••.••.••••.••••••• 8-128
Setup N.••..••..•••.•.•.•••.•••••.• 8-131

List of Tables - Model 64110A
List of Tables
Table

Title

8-41.
8-42.
8-43.
8-44.
8-45.

Signature
Signature
Signature
Signature
Signature

Analysis
Analysis
Analysis
Analysis
Analysis

Setup
Setup
Setup
Setup
Setup

Page

0 ............................ 8-133
P....•.........•..........•.. 8-135
R............................ 8-137
S •.•••••••••..•••....•••••••• 8-139
T ••••.••.•••..••••...•••••.•. 8-141

8-46. Signature Analysis Setup U...•....•.............•.•.•. 8-144
8-47. Video Truth Table ..................................... 8-156
8-48.

Mnemonics •••••.•..•••.••••.•.•.•••••••.••••••.•••••••. 8-161

vii/(viii blank)

General Information - Model 64110A
SECTION I
GENERAL INFORMATION
1-1.

INTRODUCTION.

1-2. This manual contains technical information and theory necessary
to install, maintain, and troubleshoot the Model 64110A mainframe.
This information describes the overall system and how the various components relate to one another with the emphasis on troubleshooting and
repair.
1-3. The manual is organized into eight sections: Section I introduces the reader to the manual and gives a brief physical description
of the 64110A mainframe. Section II describes the installation, removal and handling procedures. Section III discusses operation and
Section IV describes performance tests. Section V contains adjustment
procedures.
Section VI lists the replaceable parts and Section VII
contains backdating information needed to make this manual applicable
to older instruments. Section VIII presents theory of operation and
troubleshooting of the mainframe.
1-4.

SAFETY CONSIDERATIONS.

1-5. This product is a Safety Class 1 instrument provided with a
protective earth terminal. The instrument and manual should be
reviewed for safety markings and instructions before operation.
1-6.

PHYSICAL DESCRIPTION.

1-7. The 64110A is a transportable mainframe with integral accessory
storage.
It has a high resolution 9 inch CRT display which is protected during transportation by the foldup keyboard.
The standard
cabinet feet are extendable for both bench and vertical operation.
1-8. The flexible disc drive and option slots allow a variety of
analysis configurations and if fitted with the rack mount option,
using HP-IB or RS-232C interfaces, the Model 64110A can be used in
automated test applications.
The mainframe dimensions are given in
figure 1-1.

1-1

General Information - Model 64110A

II
II
II
II
II

-- - - - - - - - - - - - - - - - -

- - --------

~

r-

~i'v

~
01

I-Pc
200[77

~~

,p~ 'n41
r-

~

)

--------------- -

6286[24-3/4)

254[11

l
69911' 141
I

I
I
I
I
I
I

:n 00
0'~i
00 00

18

COIID

', _____ --- ---- ---- --- --

--)

~

1'-''-''-'1

<

0

~ ~

'uu

~

536[21-1/101

I

800[3-1/41

NOTES

DIMENSIONS ARE FOR GENERAL INfOAMATlON ON[Y IF DIMENSIONS ARE RHlUIRHl FOR BUILDING SPECIAL ENCLOSURES.

CONTACTYOUA HP FIELD ENGINEER
DIMENSIONS ARE 11\1 MILLIMETERS AIliD [INCHES)

~~~/

DDDDDDDDDDDDDD
DDDDDDDDDDDDDD
DDDDDDDDDDDDDO
000000000000
I

I

DO
DOD
DO
DOD

' - OISPLAY KEVS - . /

Figure 1-1. Mainframe Dimensions

1-2

I--

L-4191116-112)

DDDDDDDD

168316·5/8)

m~0
o

We'Qhr236 Kg [52 Ibsj

General Information - Model 64110A
1-9.

MAINFRAME CONFIGURATION.

1-10. Figure 1-2 shows the configuration
major areas of the mainframe are:

of

the

mainframe.

The

CPU/IO Board
Display Controller Board
Display Driver Boards (2)
Local Mass Storage/RS-232C Board
Local Mass Storage Unit

CRT Display
Keyboard
Rear Panel
Cardcage
Power Supply

PORT VOLTAGES SHALL
NOT EXCEED ±12V.

I

CPU/IO

I

DISPLAV CONTROL

I

A,7HORIISWEEPAND

r--- --,

HIGHVOLTAGEBOAIID

Ir---t------,
:'

I

L -_ _--I

1:
/

I

OPTION SLOT 2

I

OPTION SLOT 3

I

OPTION SlOT4

f--------,

I

A6veRTsJEEPANoviDIO

:I

OPTION SLOT 1

I

:

:::

1:

OPTIONSlOT 0

I

BOARO:

I

t

\\

!

ADORESS

rr

S;I~CH

Lo

1111111

i

'\,
...J

L _ _ _ _ _ _ _, _ _ _

;

PAfM VERIF

rLIlMS1ADRSA6LE

Lr

ILMS) TALK ONLY

\

'"'

\

,DOOggOOD/
c::::Jc::J c::::Jc::::J
' - - SYSTEM CONTROl KEVS ----

DDDDDDDDDDDDDD
DDDDDDDDDDDDDD
DDDDDDDDDDDDDO
DDDDDDDDDDOD
I

.

I

,~-----====-:;;:
c" ,:;;;;"""';;;;=."===~~/

DO
DOD
DO
ODD
'--

DISPLAY KEYS ----'"

Figure 1-2. Mainframe Configuration

1-3

General Information - Model 64110A
1-11. The four areas of the rear panel are power input, HP-IB system
interface bus, RS-232C serial interface, and system control source.
The power functions are at the top of the rear panel.
1-12. There are seven printed circuit board slots. See figure 1-2.
The top two slots have printed circuit boards installed at the factory. These boards must be installed in the order given for the Model
64110A to operate. The two required boards are:
CPU/IO in slot A
Display Controller in slot B
1-13. The printed circuit boards interface through the motherboard at
the back of the card cage, and through cables connecting the CPU/IO
board to the keyboard,flexible disc drive/RS-232C board and rear panel
board. A cable also connects the flexible disc drive/RS-232C board to
the rear panel board.
1-14. For convenience, board identifier labels for the top two boards
are located on the right hand side, between the rear panel and the
cardcage. The five option slots are numbered 0-4.
1-15. There is a limit to the number and types of option boards that
may be installed in the cardcage without exceeding the capability of
the power supply. This limit is determined by the amount of available
current from the power supplies. Refer to the installation section,
Section II, for the determination of the power limitations.
1-16.

INSTRUMENTS COVERED BY THIS MANUAL.

1-17. Attached to the instrument is a serial number plate.
The
serial number is in the form: OOOOAOOOOO. It is in two parts; the
first four digits and the letter are the repair prefix and the last
four digits are the suffix. The prefix is the same for all identical
instruments; it changes only when a change is made to the instrument.
However, the suffix is assigned sequentially and is different for each
instrument. The contents of this manual apply to instruments with
serial number prefix(es) listed under SERIAL NUMBERS on the title
page.
1-18. An instrument manufactured after the printing of this manual
may have a serial number prefix that is not listed on the title page.
This unlisted serial number prefix indicates the instrument is different from those described in this manual. The manual for this newer
instrument is accompanied by a yellow Manual Changes supplement. This
supplement contains "change information" that explains how to adapt
the manual to the newer instrument.
1-19. In addition to change information, the supplement may contain
information for correcting errors in the manual. To keep this manual
as current and accurate as possible, Hewlett-Packard recommends that
you periodically request the latest Manual Changes supplement. The
1-4

General Information - Model 64110A
supplement for this manual is identified with the manual print date
and part number, both of which appear on the manual title page. Complimentary copies of the supplement are available from the HewlettPackard sales/service office.
1-20. For information concerning a serial number prefix that is not
listed on the title page or in the Manual Changes supplement, contact
your nearest Hewlett-Packard sales/service office.
1-21.

MAINFRAME OPl'IONS.

1-22. The mainframe options are the options available from the factory when ordering a mainframe. These do not include analysis options
such as state and timing.
Table 1-1. Mainframe Options

1-23.

Model 64110A

Logic Development System
with Flexible Disc Drive

Option 032

Includes Host RAM Expansion

Option 034

Includes Accessories Pouch

ANALYSIS OPl'IONS.

1-24. There are many possible options and configurations including
State and Timing Analysis. Refer to the 64000 Configuration Guide,
available at any Hewlett-Packard sales/service office, for possible
configurations.
1-25.

RACK MOUNTING.

1-26. The 64110A can be rack mounted.
It requires a standard HP
SYSTEM-II, 7H rack mount kit. Refer to the Hewlett-Packard Catalog
for ordering information.

1-5

General Information - Model 64110A
1-27.

ACCESSORIES SUPPLIED.

1-28. A list of accessories supplied with this mainframe is contained
in table 1-2.
Table 1-2. Accessories Supplied

1-29.

Accessory

Part Number

Power Cord

See table 2-2

Operating Manual

64110-90902

Service Manual

64110-90901

Operating System
On Flexible Disc

64110AF

ACCESSORIES AVAILABLE.

1-30. The Service Tool Kit, part number 64110-68701, contains all the
accessories shown in table 1-3, except the power supply test board.
Table 1-3. Accessories Available

1-6

Accessory

Part Number

Extender Board

64110-66503

Flexible Disc Drive Extender Cable

64110-61620

Flexible Disc Drive Extender Cable

64110-61621

Flexible Disc Drive Extender Cable

64110-61622

I/O Extender Cable

64110-61618

Power Supply Flexible Extender

64110-66520

Power Supply Test Board

64110-66519

Rear Panel Cable Extender

64110-66522

RS-232C Extender Cable

64110-61619

General Information - Model 64110A
1-31.

RECOMMENDED TEST EQUIPMENT.
Table 1-4. Recommended Test Equipment
HP 5004A or 5005A Signature Analyzer
Digital voltmeter capable of .01 V resolution
Oscilloscope
Standard hand tools for electronic printed circuit
board repair

1-32.

LEVEL OF SERVICE.

1-33. This is a Preliminary Component Level Manual. It contains information that provides component level servicing of the Model 64110A.
Detailed schematics, theory of operation and Signature Analysis loops
are provided in Section VIII.

1-1/(1-8 Blank)

Installation - Model 64110A
SECTION II
INSTALLATION
2-1.

INTRODUCTION.

2-2. This section contains information for unpacking, initial inspection, and installation of the Model 64110A Logic Development System
mainframe.
2-3.

INITIAL INSPECTION.

a.

Unpack the mainframe.

b.

Keep the Shipping carton and cushioning material until the contents have been checked. The carrier will want to inspect the
shipping materials if a claim is made.

c.

Check the mainframe mechanically and electrically.
The
trical performance verification is given in Section IV.

d.

If the contents are not complete, there is mechanical damage or
defect, or it does not pass the performance verification test
then notify the carrier as well as the Hewlett-Packard salesservice office.
HP will arrange for repair or replacement at
its option without waiting for the claim against the carrier to
be settled.

2 - 4.

elec-

POWER REQUIREMENTS.

2-5. The Model 64110A requires 110 or 220 VAC (+-15%) at 48-66 Hz.
The line voltage selector switch is located along the left side, under
the side cover. The fuse required is a non-delay type of 8 A for the
110 V and 4 A for the 220 V. The power on/off switch is a push type
labeled LINE and is located at the top left corner of the front panel.

**********************

*

*

*

*

CAUTION

**********************

The instrument can be damaged if the line voltage
switch is not set to the correct input voltage.

*
*
*
*

*******************************************************

2-1

Installation - Model 64110A
2-6.

POWER REQUIREMENTS WORKSHEET.

2-7. There is a limit to the number and types of option boards that
may be installed in the cardcage without exceeding the capability of
the power supply. This limit is determined by the amount of available
current from the power supply. Table 2-1 lists the power supply loads
for the basic mainframe with the mandatory mainframe boards installed.
Refer to the flexible disc drive appendix of this manual for its power
usage and fill in the current values in table 2-1. Subtract the total
of the mainframe plus the flexible disc drive to determine the available current for remaining options. Space has been left to do calculations in the manual.
Table 2-1.

Power Requirements Worksheet

-3.25 V -5.20 V +5.00 V +12.00 V -12.00 V +12.00 VDD
AVAILABLE
CURRENT

see
note

see
note

0.00 A

0.01 A

30.00 A

4.50 A

1.00 A

1.50 A

5.70 A

2.80 A

0.01 A

1.11 A

REQUIRED
CURRENT
Mainframe
w/floppy
Option 1
Option 2
Option 3
Option 4
Option 5
TOTAL

REQUIRED

NOTE. Sum of -3.25V and -5.20 V available current is 20.0 amperes.

2-2

Installation - Model 64110A
2-8.

POWER CORD.

2-9. The proper power cord is listed by mainframe option number in
table 2-2.
If the appropriate power cord is not included with the
instrument, notify the nearest HP sales/service office and a replacement cord will be provided.
Table 2-2. Power Cord Options

2-10.

Location

Part Number

USA
Great Britian
Australia
Europe
Switzerland
Denmark

8120-1378
8120-1351
8120-1369
8120-2857
8120-2104
8120-2957

SITE SELECTION AND SYSTEM BUS OPERATION.

2-11. The Model 64110A is a transportable mainframe and may be used
as a stand alone unit or as part of an HP-IB or RS-232C bused system.
Refer to the Operation Reference Manual for specific information.
2-12.

OPERATING ENVIRONMENT.

2-13. The Model 64110A may be operated in environments within the
limits shown below. It should be protected from temperature extremes
which cause condensation within the instrument.
Temperature ••••••••••...•.•••• +10 to +44 degrees Celsius
Humidity .....••.•••.••...•••• 20 to 80% relative humidity
Altitude ............................. 4.600 m (15,000 ft)
2-14.

STORAGE ENVIRONMENT.

2-15. The Model 64110A may be stored or shipped in environments within the following limits:
Temperature ••••••.•••••..•••• -40 to +70 degrees Celsius
Humidity .••••••••••..••••..• 20 to 80% relative humidity
Altitude ••••••••••••••••••••••••••• 15 300 m (50 000 ft)
2-16.

ORIGINAL PACKAGING.

2-17. Containers and packing materials identical to those used in
factory packaging are available through Hewlett-Packard sales and service offices.
2-3

Installation - Model 64110A
2-18.

OTHER PACKAGING.

2-19. The following general instructions should be used for repacking
with commercially available materials:
a.

Wrap the Model 64110A in heavy paper or plastic.

b.

Use a strong shipping container. A double-wall
350 pound test material is adequate.

c.

Use a layer of shock absorbing material 70 to 100 mm (3 to 4
inch) thick around all sides of the 64110A to provide firm cushioning and prevent movement inside the container.

d.

Seal shipping container securely.

e.

Mark shipping container FRAGILE to ensure careful handling.

f.

In any correspondence, refer to the instrument by
and full serial number.

carton

made

of

model

number

2-21. Specific procedures for assembly and disassembly of the
mainframe can be found in Section VI, Replaceable Parts.

64110A

2-20.

2-4

ASSEMBLY AND DISASSEMBLY.

Operation - Model 64110A
SECTION III
OPERATION

Complete operation of this system from the keyboard is described in
the Model 64110A Operating Reference Manual and is not duplicated in
this service manual.

3-1/ (3-2 Blank)

Performance Tests - Model 64110A
SECTION IV
PERFORMANCE TESTS
4-1.

INTRODUCTION.

4-2. This section describes the mainframe
(PV) power-up sequence and tests.

performance

verification

4-3. The mainframe PV is a series of tests resident in the mainframe
that confirm correct operation of the mainframe hardware and firmware.
The PV can be started at any time using the rear panel switches. It
can also be started from the front panel when the operating system has
been loaded and a disc drive is connected.
4-4. The mainframe power-up mode is determined by
the control source switches on the rear panel.

the

positions

of

a.

When the switches are set to performance verification, the
system will power-up with the performance verification display
test on the screen.

b.

When the source switches are set to either of the local
storage modes the display will read "SELF TEST COMPLETE".

c.

When the switches are in the system bus mode, the power-up is
from disc, and the system bus configuration will be displayed.

mass

CPU/IO

DISPLAY CONTROL
OPTION SLOT 0
OPTION SLOT 1

OPTION SLOT 2
OPTION SLOT 3
OPTION SLOT 4

CONT SOURCE

SYS BUS

r

1

~0

r'---'-'--,

rr

rL
Lr

PRFM VEAIF

(LMS) ADRSABLE
(LMS) TALK ONLY

LL

SYSTEM BUS

Figure 4-1. Rear Panel Switches

4-1

Performance Tests - Model 64110A
4-5.

STARTING PERFORMANCE VERIFCATION.

4-6.

To start the mainframe PV, perform the following steps.

a.

Set rear panel switches to PV positions. See figure 4-1.

b.

Turn power off, then on.

4-7. The mainframe will beep several times and then show the PV display test screen. See paragraphs on how to use the PV test displays.
Refer to the next paragraphs for a description of the automatic powerup ROM and RAM tests.
4-8.

PV POWER-UP EVENT SEQUENCE.

4-9. The mainframe automatically executes the power-up ROM and RAM
tests every time the power has been turned off, then on. Table 4-1
shows the events that occur during PV power-up.
Table 4-1. PV Power-Up Sequence (1 of 2)

4-2

a.

Check power-up status by reading
tion in RAM.

reserved

loca-

b.

Initialize

c.

Blank

d.

Initiate ROM test. A failing
and byte will be displayed.

e.

Initiate RAM test. If a failure occurs, an SA
loop is entered and the failing RAM IC numbers are
displayed.

f.

Read rear panel switches
mode) .

g.

Suspend operation of the PHI chip
CPU/IO board) and take it off-line.

h.

Initialize the CRT chip U33 on display control
board and enable the display and sounds the beeper
once.

i.

Disable interrupts and CPU direct memory access.

j.

Clear base page RAM (FOOO - FFFF hex).

k.

Set up interrupt vector.

CRT controller chip (U33).

the screen.

and

ROM

address

powers-up
(U36

range

(in
on

PV
the

Performance Tests - Model 64110A
Table 4-1. PV Power-Up Sequence (2 of 2)
1.

Clear keyboard power-up interrupts and clear
play.

m.

Set up and enable keyboard interrupts for
test and move cursor off screen.

n.

Determine which flexible disc drive is present so
the correct softkey will appear, then display the
softkeys.

o.

Start SA interval.

display

1.

Write display test pattern to screen
able keyboard interrupts.

2.

Toggle I/O data lines and
time interrupt.

3.

Cycle through interrupt masks and service
delta time interrupt.

4.

Read rear panel switches and
mass storage control board.

service

and

the

write

dis-

to

endelta
the
local

5. Toggle all even I/O address lines and read
keyboard.

6.

Send
val.

..

move cursor

II

p.

Read and write from RAM.

q.

Read keyboard.

r.

Issue an I/O write.

s.

Begin SA interval again.

commands and clear SA inter-

4-10. The beeper is used to indicate the sucessful completion of certain phases of power-up. See table 4-2.
Table 4-2. PV Power-Up Beeper Sequence
a.

BEEP ••••••........ hardware initialization.

b.

BEEP •••••......... ROM software initialization.

c.

BEEP BEEP BEEP ••.. ROM test completed.

d.

BEEP BEEP ......... RAM test completed.

4-3

Performance Tests - Model 64110A
4-11.

POWER -UP ROM TEST.

4-12.

Purpose.

4-13. The ROM test verifies that all of the firmware in ROM used for
power-up and performance verification is good. The test also checks
that the CPU is able to access ROM memory via the bi-directional address and data buses.
4-14.

Area Tested.

4-15. Multiplexer, memory address/data bus, address latches, demultiplexed data bus from ROM, demultiplexed address bus to/from ROM, CPU
and associated timing circuitry.
4-16.

Operation.

a.

This test executes a checksum on each of the ROMs as long as the
kernel of ROM needed to run the test is good.

b.

If an error is detected, then a bit is set in an error mask.

c.

The error mask is then used to output an error message to the
screen stating a ROM failure, the address range of the failure,
and the byte (0 or 1).

d.

If a failure is detected the test will loop
CPU section IV for more information.

e.

On failures, the power-up ROM test will display the

Power-up ROM Test Errors

SELF-TEST FAILURE
ROM TEST:
FAILING ADDRESS RANGE

BYTE(S)

xxxx-xxxx

xx

Failed
Addresses

Byte

0020-1FFF
0020-1FFF

0
1

U51

2000-3BFF
2000-3BFF

0
1

U50

---------

4-4

See

error message shown in table 4-3, assuming that the kernel of ROM required to run the power-up test is good. Use the table to determine which ROM unit number is failing.
Table 4-3.

g.

continuously.

Failed
ROM Unit

u48

Lower 8K ROM
Upper 8K ROM

u49

When the ROM test passes, the mainframe will beep three
and begin the RAM test.

times

Performance Tests - Model 64110A
4-17.

POWER-UP RAM TEST.

4-18.

Purpose.

4-19. The RAM test verifies the ability to read from and write to all
RAM located on the display control board and checks for refresh. Note
that this test occurs only on power-up. Another RAM test occurs during
PV and has a different error message.
4-20.

Area Tested.

4-21. All RAMs including refresh ability, the multiplexed memory address/data bus from the CPU, motherboard connections between CPU and
display controller board, demultiplexed address/data bus to and from
RAM, and timing counter circuitry.
4-22.

Operation.

a.

This is a different test than the one performed during PV.

b.

The RAM test takes approximately 7 seconds.

c.

All RAM locations are toggled to insure READ/WRITE operation.

d.

Refresh ability is verified.

e.

The actual operation of the routine is as follows:
1.

Load RAM with a count, starting with zero.

2.

Read RAM and compare with count.

3.

Check for an error. If error occurs, go to error sequence.

4.

If there is no previous error, wait one second.

5. Read RAM and compare with count.
6.

Check for an error. If error occurs, go to error sequence.

7.

If there is no previous error, load RAM with complement of
count, starting at zero.

8.

Read RAM and compare with the complement of the count.

9.

Check for an error. If error occurs go to error sequence.

10.

If there is no previous error, wait one second.

11.

Read RAM and compare with count.

12.

Check for an error, if error occurs, go to error sequence.

4-5

Performance Tests - Model 64110A
f.

g.

If there are not any errors in either RAM error mask then the
system will beep twice. But, if an error exists then the following error sequence occurs:
1.

Reset the delta timer to prevent auto-restart.

2.

Set the SA latch.

3.

Write to and read from all of RAM.

4.

Provide stimulus to CRT controller.

5.

Output RAM error display header information (including
refresh error message if refresh error flag set) .

6.

Reset SA latch.

7.

Output individual failing unit number for lower 16K RAM.

B.

Output individual failing unit number for upper 16K RAM.

When a failure occurs, the routine attempts to output the error
message shown in table 4-4. Depending on which RAM is failing,
a random pattern on the CRT, or incorrect spelling of messages
can occur. Therefore, a RAM test failure is always suspect.
If Chips U23-U30 and U38-U45 on the display controller board are
failing, the display will be in error. If this occurs, see Section VIII troubleshooting.
Table 4-4. Power-Up RAM Test Errors
SELF-TEST FAILURE

*RAM TEST:
FAILING UNIT NUMBERS (S)

XY
Where XY is the RAM U-number.
* Displays RAM TEST: or RAM TEST: REFRESH FAILURE
4-23.

USING THE PV DISPLAY-TEST.

4-24. The PV display-test should be on screen after the power-up
tests. See figure 4-2. To continue to the PV-Tests Display, press the
 softkey.

4-6

Performance Tests - Model 64110A

Figure 4-2. PV Display-Test

Table 4-5. PV Display-Test Softkeys
 ... displays
screen.

the

performance

verification

tests

 ....... starts the floppy disc diagnostic.
 ... terminates PV tests, clears error counts and
repeats power-up sequence to PV display test.
[B] .......... causes the mainframe beeper to beep. This
indicates that the CPU is able to recognize and
process interrupts. A failure to beep indicates
the CPU is "lost" or the I/O or beeper circuitry is faulty.
4-25.

USING THE PV-TESTS DISPLAY.

4-26. The PV-tests display first appears showing only the first line
of the screen, which is the ROM test. Press the  softkey
until all tests are shown on the display. The highlighted test is the
test that is ready to be run. See figure 4-3.

4-7

Performance Tests - Model 64110A

Figure 4-3. PV-Tests Display
Table 4-6. PV-Tests Display Softkeys
 ..••.. moves highlight line to following test.
When pressed during a test, the test is completed before the next one is selected.
 •...•..... begins the test highlighted test. Pressing
 during a test causes the test to
complete at the end of the current repetition.
 •...•..•.. cycles through all tests, except the keyboard test. This is a good initial inspection test.
 ........ presents the PV display test. When pressed
during a test, returns to the PV display
test after completion of the test.
 •..... repeats power-up sequence to PV display
test. If pressed during a test, the test
finishes, then the power-up is performed.

NOTES:

4-8

If the rear panel switches are unaltered,
the repower-up will be back to the display
test. The key being pressed is displayed in
the lower left corner as: Key Down=IX"

Performance Tests - Model 64110A
4-27.

PV ROM TEST.

4-28.

Purpose.

4-29. The ROM test verifies that all of the firmware in ROM used for
boot-up and performance verification is good. The test also checks
that the CPU is able to access ROM memory via the bidirectional address and data buses.
4-30.

Area Tested.

4-31. Multiplexer, memory address/data bus, address latches, demultiplexed data bus from ROM, demultiplexed address bus to and from ROM,
CPU and associated timing circuitry.
4-32.

Operation.

a.

This test is similar to the ROM test which is performed
power-up; although, there is a different error message.

b.

Each test takes approximately 1/2 second.

c.

A routine reads the ROM contents, computes a checksum
pares it with a checksum also located in ROM.

d.

Assuming that the kernel of ROM required to run the ROM TEST is
alright, the test will attempt to output an error mask if the
test fails. The mask is a 16 bit word shown in table 4-7. A one
in any of the bits signifies a ROM. Use the table to determine
which ROM is failing.

and

during

com-

Table 4-7. PV ROM Test Errors

IC MASK = OOOOOOOOOOOOABCD
15--------------0

Bit

Failed
Addresses

Byte

D
C

0020-1FFF
0020-1FFF

0
1

U51
u48

Lower 8K ROM

B
A

2000-3BFF
2000-3BFF

0
1

U50
u49

Upper 8K ROM

---------

Failed
ROM Unit

-------------------

4-9

Performance Tests - Model 64110A
4-33.

PV RAM TEST.

4-34.

Purpose.

4-35. This PV RAM TEST is executed only from the PV menu. Note that
this is a different test from the power-up RAM test and gives a different error message. The test verifies the ability to read and write
from all RAM located on the display control board and checks for refresh.
4-36.

Area Tested.

4-37. All RAMs including refresh ability, the multiplexed memory address/data bus from the CPU, motherboard connections between CPU and
display controller board, demultiplexed address/data bus to and from
RAM, and timing counter circuitry.
4-38.

Operation.

a.

This test takes approximately eight seconds.

b.

Data from ROM is written into RAM, and then read back
pared to the ROM contents.

c.

The second step writes walking l's and O's to each RAM address
and reads it back. The walking l's and O's are visible on the
CRT as a blinking pattern with characters moving to the bottom
of the screen.

d.

Table 4-8 shows the PV RAM test error mask. The XXXX is the hexadecimal form of the 16 bit error mask. There is a one-to-one
correlation between the data bit set in the error mask and the
failing RAM.

and

com-

Depending on which RAM is failing, a random pattern on the CRT,
or incorrect spelling of messages can occur. Therefore, a RAM
test failure is always suspect. If Chips U23-U30 and U38-U45 on
the display controller board are failing, the display will be in
error. If this occurs, see Section VIII troubleshooting.
Table 4-8. PV RAM Test Errors
RAM TEST:

UPPER BANK=XXXX

LOWER BANK=XXXX

Example,

UPPER BANK=0201

LOWER BANK=3000

RAMs in Error

U39, U23

U70, u69

Bit
UPPER
LOWER

4-10

BIT ERROR MASK

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
u-45 44 43 42 41 40 39 38 30 29 28 27 26 25 24 23
U-72 71 70 69 68 67 66 65 58 57 56 55 54 53 52 51

Performance Tests - Model 64110A
4-39.

PV I/O WRITE TEST.

4-40.

Purpose.

4-41. This test provides audible feedback that the test is executing
by beeping, and provides the following SA stimulus. The I~WRlTE
TEST cycles the PHI chip register addresses, cycles the interrupt
masks, cycles the slot select lines, and stimulates the four rear
panel BNC connectors.
4-42.

Area Tested.

4-43. The test is not a pass/fail test.
It provides stimulus for
signature analysis in the following circuitry: Option slot select
lines on the motherboard, all connections from option slots to the
rear panel BNC connectors, the beeper circuitry, PHI register address
latch, and the interrupt mask circuitry.
4-44.

Operation.

a.

This test will not display a failure. The main
test is for signature analysis (SA).

purpose

of

b.

The only noticeable failure will be
beeper.

of

audible

4-45.

PV I/O READ TEST.

4-46.

Purpose.

the

loss

the

the

4-47. This test reads the rear panel switches, the hardware configuration jumpers, the RS-232C switch settings, and the master controller, noncontroller configuration. It is also used with signature analysis.
4-48.

Area Tested.

4-49. Rear panel dip-switches, the cable to the rear panel, I/O
cuitry, and the RS-232C dip-switches.
4-50.
a.

cir-

Operation.
Upon initiation of the I/O READ TEST, the PV menu
message shown in table 4-9.

displays

the

4-11

Performance Tests - Model 64110A
Table 4-9.
I/O READ TEST:

I/O Read Test Errors

ADDR=xx BOOT=xx M=x RS-232=xxxxxxxx HC=xx

Where:
ADDR=xx ..........•.•..• is the HP-IB address (O-lF)
rear panel switches.

as set by the

BOOT=xx .....•...••..•••. shows the source set by the rear panel
switches.
M=x ..................... is the mainframe mode.
x=l for master controller
x=O for non-controller (slave)
RS-232=xxxxxxxx ......... read from u60 on the CPU/IO board.
76543210
Bit 0

0 = Mainframe as terminal
1 = Mainframe as modem

Bit 1

Not used

Bit 2
Bit 3

Word Length
Bit 3

Bit 2

0
0
1
1

0
1
0
1

Word
Length
-----5
6
7

8

Bit 4

Parity Enable

Bit 5

Parity

Bit 6
Bit 7

Number of stop bits
Bit 7
0
0
1
1

Odd/Even

Bit 6
0
1
0

1

0= Parity Disabled
1= Parity Enabled
0= Odd Parity
1= Even Parity

# of Stop Bits
INVALID
1
1.5
2

HC=xx ................... The hexadecimal representation of the six
hardware jumpers. They are not used at this
time.

4-12

Performance Tests - Model 64110A
4-51.

PV TIME INTERRUPT TEST.

4-52.

Purpose.

4-53. The TIME INTERRUPT TEST indicates proper operation of the 50 to
60 Hz LINSYN to the CPU via the delta time interrupt circuitry.
4-54.

Area Tested.

4-55. LINSYN, a 50 to 60 Hz signal from the power supply, the delta
time interrupt circuitry on the CPU/IO board, and interrupts to the

CPU.
4-56.

Operation.

4-57. Upon initiation, the PV test counts and displays LINSYN
rupts to the CPU.
4-58.

PV KEYBOARD TEST.

4-59.

Purpose.

inter-

4-60. The KEYBOARD TEST indicates proper keyboard switch closure
keyboard decoding.
4-61.

Area Tested.

4-62. All 77 keyswitches, keyboard decoding
cable, and the keyboard RAM/state machine.
4-63.

and

electronics,

keyboard

Operation.

a.

When initiated, the KEYBOARD TEST instructs the user to press
all of the keyboard keys in a left-to-right top-to-bottom sequence.

b.

The sequence begins with the leftmost softkeyand
display and cursor control keys.

c.

The keyboard test requires this specific sequence. Furthermore,
even if all keyswitches and the decoding circuitry are working,
a key tha~ is pressed out of sequence will cause a "FAILED TEST"
message and end the test.

includes

all

4-13

Performance Tests - Model 64110A
d.

The order in which the keys are pressed is given in figure 4-4.

I

!

START

1 -

-<=;.;;;;

2----'-

3---+-

4--""""

5--6 _ __

Figure
e.

4-14

4-4. Keyboard Test, Key Sequence

Note the KEYBOARD TEST is skipped while PV is in the cycle mode.

Performance Tests - Model 64110A
4-64.

PV SYSTEM BUS TEST.

********************

*
*
*
*
*

CAUTION

*********************

This test should NOT be run if the mainframe
is connected to a system bus and is the master
controller.

*
*
*
*
*

****************************************************
4-65.

Purpose.

4-66. This test checks for proper operation of the PHI chip (U36 on
the CPU/IO board). It also checks the data, address and counter circuitry from the CPU to the PHI chip.
4-67.

Area Tested.

4-68. Data, address, control and interrupt lines from the CPU to
PHI chip.
4-69.

the

Operation.

a.

The SYSTEM BUS TEST takes the PHI chip off-line, then reads
writes to various registers on the chip.

b.

The transceivers and the cable to the rear panel HP-IB connector
are not presently being checked.

c.

If a failure occurs, this test may take up
fail.

to

two

minutes

and

to

4-15

Performance Tests - Model 64110A
4-70.

RS-232 TEST PROCEDURE.

4-71.

Purpose.

4-72. The test checks proper operation of the USART, U57 on the local
mass storage/RS-232C board. It also checks the data and control circuitry associated with RS-232C.
4-73.

Area Tested.

4-74. The 8251 USART, the baud rate generator, loop back relays, line
drivers, the interface to the CPU, and the rear panel cable.
4-75.

Operation.
NOTE

Before starting the test, locate slide switch u60 on
the flexible disc drive/RS-232C board. Set the front
switch to the left or full duplex position. Set the
remaining switches on u60 to the right side to establish the maximum baud rate. The test may be run at
any baud rate, but will run faster at maximum.
a.

Energizes the loop back relays to loop transmit data, and
shake lines back on receive data.

b.

Sends a character stream.

c.

Compares receive character
stream.

d.

Notes:

stream

to

cannot

the

be

transmit

character

1.

The voltage translators
higher voltage side.

signaturized

on

the

2.

This test may take up to two minutes if a failure
tected.

is

de-

4-76.

PV FLEXIBLE DISC DRIVE TEST.

4-77.

See flexible disc drive appendix to this manual.

4-16

hand-

Adjustments - Model 64110A
SECTION V
ADJUSTMENTS
5-1.

INTRODUCTION.

5-2. This section describes adjustments and checks required to return
the instrument to peak operating capability after repairs have been
made.
5-3. The seven adjustments described are the +7 V, focus, intensity,
horizontal position, width (horizontal gain), yoke, and height (vertical gain) adjustment.
5-4.

SAFETY CONSIDERATIONS.

5-5. Although this instrument has been designed in accordance with
international safety standards, general safety precautions must be
observed during all phases of operation, service, and repair of the
instrument.
Failure to comply with precautions listed in the Safety
Summary at the front of this manual or with specific warnings given
throughout the manual could result in serious injury or death. Service adjustments should be performed only by qualified service personnel.
5-6.

DIRECTION STANDARD.

5-7. All directions assume the operator is facing the front panel
the instrument.
5-8.

of

+7 VOLT ADJUSTMENT.

5-9. The +7 V adjustment is found on the CPU/IO A3 board and sets the
+7 V supply to the CPU, chip U29.
a.

Equipment required - a voltmeter capable of .01
is required.

VDC

resolution

b.

Remove the top cover.

c.

Locate the test point, labeled "+7V adj". It is located near
the right edge of the board, near the lower right corner of the
U29 heat sink.

d.

Connect the positive lead of the voltmeter to the "+7V adj."
test point and the negative lead to the ground test point in the
lower right corner of the board.

Refer to figure 6-1.

5-1

Adjustments - Model 64110A
e.

Adjust R6 (+7V adjust) for +7.0V +/- O.3V.

5-10.

DISPLAY ADJUSTMENTS.

5-11. The display adjustments are found on the secondary board A6,
the flyback board A7 and the yoke. Table 5-1 lists the adjustments
and gives their locations.

***********************

WARNING

***********************

*

*

* The display adjustments are performed with the *
* instrument energized
Read the Safety Summary at *
* the front of this manual before making any *
*
* adjustments.
*
*
*********************************************************
a.

Equipment required - nonconducting screwdriver or an
tool.

b.

Remove the top cover.

c.

Remove the bottom cover.

d.

Lay the mainframe on its right side.

5-2

Refer to figure 6-1.
Refer to figure 6-2.

adjustment

Adjustments - Model 64110A
Table 5-1. Display Adjustments

ADJUSTMENT

SPEC.

COMPONENT COMMENTS

FOCUS

best focus

A7R13

INTENSITY

readable

A7R12

16.5 cm

WIDTH

A7L2

Component side of flyback
A7 board. Access is direct
with bottom cover removed.

A6R3

Back of A6 secondary board
Access is direct with the
bottom cover removed.

+- 0.2 cm

HORIZONTAL
POSITION

centered

HEIGHT
(VERT. GAIN)

+- 0.2 cm

YOKE

level

11.0 cm

Back of flyback A7 board.
Access is through the high
voltage cover with the top
cover removed.

A6R20

Yoke

Located around the neck of
the CRT. The high voltage
cover must be removed. See
warning on the cover.

e.

Set the system control switches to the performance
position.

verification

f.

Set main power switch off then on. Note, the display test
tern should be on the screen. Refer to Figure 5-1.

pat-

5-3

Adjustments - Model 64110A

Figure 5-1. Display Test Pattern

g.

h.

Width (Horizontal Gain) Adjustment.
1.

Insert adjustment tool throuh the HORIZ
high voltage cover.

2.

Adjust the variable inductor, L1, for
16.5cm +/- O.2cm.

hole

display

in

the

width

of

Adjust potentiometer R3 so that the display test pattern
centered in the bezel.

is

Horizontal Position Adjustment.
1.

5-4

a

GAIN

Adjustments - Model 64110A
i.

Height (Vertical Gain) Adjustment.
1.

Adjust potentiometer R20 (V GAIN) so that the
pattern is 11.0 cm +/- 0.2 cm high.

display

test

NOTE

There is no vertical position adjustment
and
pattern may be offset up to 1 cm. Magnetic fields
from soldering irons, transformers, and
other
electromagnetic field producing electronics may
cause a portion of the display to be off screen in
the vertical direction. Reducing the vertical gain
or removing the electromagnetic field producing
device should fix this problem. Also, distortion
may occur when the A6 and A7 boards are out of
position.
j.

k.

Focus Adjustment.
1.

Insert the adjustment tool through the FOCUS access hole
the high voltage cover.

in

2.

Adjust potentiometer R13 (FOCUS) for the best overall focus.

Intensity Adjustment.
1.

Insert adjustment tool through the intensity access hole
the high voltage cover.

2.

Adjust potentiometer R12 (INTENSITY) to increase the intensity from its lowest level until the display is clearly readable.

********************

*
*
*
*

CAUTION

in

********************

If the intensity is set too bright damage may
result to the CRT.

*
*
*
*

***************************************************

5-5

Adjustments - Model 64110A
1.

Yoke Adjustment.

********************* WARNING *************************

*
*
*
*
*
*
*
*

This adjustment requires removal of the
high
voltage cover. There are dangerous voltages (12KV)
beneath this cover, capable of causing death. Use
extreme caution when serv1c1ng. All adjustments
should b~ performed only by qualified service
personnel.

*
*
*
*
*

*
*

*

*********************************************************

1.

Equipment required - a non-conducting (shielded)
screw driver.

2.

Remove the high voltage cover.
ginning of this procedure.

3.

Loosen the yoke neck screw.

4.

Rotate the yoke until the display is level.

flat

Note the warning at the

5. Retighten the yoke neck screw.
********************

*
*
*
*

CAUTION ***********************

The yoke must be positioned forward, against the
CRT bell. Tighten the yoke securely.

*
*
*
*

******************************************************

5-6

head
be-

Replaceable Parts - Model 64110A
SECTION VI
REPLACEABLE PARTS
6-1.

INTRODUCTION.

6-2. This section contains information for ordering parts. Table 6-1
lists abbreviations used in the parts list and through tout the manual.
Table 6-2 lists all replaceable parts in reference designator order.
Table 6-3 contains the names and addresses that correspond to the
manufacturer's five-digit code numbers.
6-3.

ABBREVIATIONS.

6-4. Table 6-1 lists abbreviations used in the parts list, schematics
and throughout the manual. In some cases, two forms of the abbreviation are used: one all in capital letters, and two partial or no capitals. This occurs because the abbreviations in the parts list are
always capitals.
However, in the schematics and other parts of the
manual, other abbreviation forms are used with both lowercase and uppercase letters.
6-5.

REPLACEABLE PARTS LIST.

6-6. Tables 6-2 through 6-14 are the lists of replaceable parts. Each
list is organized as follows:
a.

Chassis-mounted parts in alphanumerical order by reference
ignator.

b.

Electrical assemblies and their
order by reference designator.

c.

Miscellaneous.

6-7.

components

in

des-

alphanumerical

ORDERING INFORMATION.

6-8. To order a part listed in the replaceable parts table, quote the
Hewlett-Packard part number and check digit, indicate the quantity required, and address the order to the nearest Hewlett-Packard sales and
service office.

6-1

Replaceable Parts - Model 64110A
6 -9.

DIRECT MAIL ORDER SYSTEM.

6-10. Within the USA, Hewlett-Packard can supply parts through a direct mail order system. Advantages of using the system are as follows:
a.

Direct ordering and shipment from the HP Parts Center in Mountain View, California.

b.

No maximum or minimum on any mail order (there is a m1n1mum
order amount for parts ordered through a local HP sales and
service office when the orders require billing and invoicing).

c.

Prepaid transportation (there is a small handling
each order).

d.

No invoices - to provide these advantages,
order must accompany each order.

a

check

charge
or

for
money

6-11. Mail-order forms and specific ordering information are available through your local HP Sales/Service Office. Addresses and phone
numbers are located at the back of this manual.

6-2

Replaceable Parts - Model 64110A
Table 6-1.

Reference Designators and Abbreviations

REFERENCE DESIGNATORS
A
B
BT
C
CP
CR
DL
OS
E

== assembly
:::: motor

A
AFC

~

F
FL
IC

battery

~

= capacitor

J

coupler
~ diode
~ delay line
= device signaling (lamp)
= mise electronic part

K
L
LS
M
MK

H
HOW

=

AMPL

== amperes
= automatic frequency
control
= amplifier

BFO
BE CU
BH
BP
BRS
BWO

:::: beat frequency oscillator
~ beryllium copper
= binder head
= bandpass
= brass
= backward wave oscillator

HEX
HG
HR
HZ

== hexagonal
:::: mercury
= hour(s)
= hertz

=

MP
P

fuse
filter
= integrated circuit
~ jack
~ relay

=

Q

R
RT
S
T
TB
TP

== inductor
== loud speaker
== meter
= microphone

= mechanical part
~ plug
= transistor
:::: resistor
= thermistor
= switch
= transformer
= terminal board
~ test point

U
V
VR
W
X
Y
Z

integrated circuit
== vacuum, tube, neon
bulb, photocell, etc
= voltage regulator
~ cable
:::: socket
= crystal
= tuned cavity network

normally open
== nominal

RMO
RMS

= root-mean

negative positive zero
(zero temperature
coefficientJ
= negative-positivenegative
= not recommended for
field replacement
= not separately
replaceable

RWV

=

S-B
SeR
SE
SECT
SEMICON
SI
SIL
SL
SPG
SPL
SST
SR
STL

= slow-blow

silicon
silver
~ slide
~ spring
= special
= stainless steel
= split ring
~ steel

TA
TO
TGL
THO
TI
TOL
TRIM
TWT

tantalum
time delay
~ toggle
~ thread
= titanium
=.; tolerance
= tnmmer
= traveling wave tube

U

= micro=10-6

VAR
VDCW

=

=

ABBREVIATIONS

CCW
CER
CMO
COEF
COM
COMP
COMPL
CONN
CP
CRT
CW
DEPC
DR

= counter-clockwise
= ceramic

= cabinet

mount only
= coeficient
= common
= composition
= complete
= connector
= cadmium plate
~ cathode-ray tube
= clockwise

= deposited
=

carbon

drive

ELECT
ENCAP
EXT

electrolytic
= encapsulated
= external

F
FH
FIL H
FXD

=

G
GE
GL
GRD

=

farads
flat head
= fillister head
= fixed

~

~

giga (109)

= germanium
~
~

glass
groundled)

~

henries
hardware

N/O

NOM
NPO
NPN
NRFR

= intermediate freq

IF
IMPG
INCD
INCL
INS
INT

=

K

~ kilo~1000

LH
LIN
LK WASH
LOG
LPF

left hand
linear taper
= lock washer
= logarithmic taper
= low pass filter

M
MEG
MET FLM
MET OX
MFR
MHZ
MINAT
MOM
MOS
MTG
MY

~ milli~10-3

N
N/C

NE
NI PL

= impregnated

= incandescent
= include(s}
= insulatlon(ed)
internal

~

=

~ meg~106

NSR

metal film
metallic oxide
= manufacturer
= mega hertz
= miniature
= momentary
= metal oxide substrate
= mounting
~ "mylar"
nano 110-9)
normally closed
= neon
~ nickel plate
~

=

=

OBD
OH
OX

= order

P
PC
PF

peak
printed circuit
~ picofarads~ 10-12
farads
~ phosphor bronze
~ phillips
= peak inverse voltage
= positive-negativepositive
~ part of
~ polystyrene
= porcelain
= position(s)
= potentiometer
~ peak-to-peak
= pOint
= peak working voltage

PH BRZ
PHL
PIV
PNP

=

=

=

P/O

POLY
PORC
POS
POT
PP
PT
PWV
RECT
RF
RH

by description
oval head
= oxide
~

~

== rack mount only
square
reverse working
voltage

= screw
=

selenium

= section(s)
= semiconductor
=
=

=

rectifier
::::: rad io freq uency
= round head or
right hand
=

WI
W
WIV
WW
W/O

=

~

=

variable
dc working volts

with
watts
= working inverse
voltage
= wirewound
= without
~

=

6-3

Replaceable Parts - Model 64110A
6-12.

POWER SUPPLY REMOVAL.
ASSEMBLY Ai.

***********************

WARNING

***********************

*
*
* Ensure the instrument is deenergized prior to power *
* supply removal.
*
*
*

*********************************************************
a.

Remove the power cord W2.

b.

Remove the top cover MP1, rear door MP5, bottom cover
left side cover MP3. Refer to Figures 6-1 and 6-2.

c.

Remove eight H37 screws.

d.

Disconnect the line switch extender MP11 from line switch.

e.

Tilt power supply up at the front then slide it forward
until it clears the mainframe.

f.

Install in reverse order.

6 -13.

PRIMARY BOARD REMOVAL.
ASSEMBLY AlAl.

MP4,

and

Refer to figure 6-6.

and

up

a.

Remove the power supply assembly Al from the mainframe.

b.

Remove the six H22 corner strut screws. The two corner struts
MP20, MP21 , and the power board brace MP19, can be removed as
one piece. See figure 6-9.

c.

Unscrew shaft MP18 from coupler MP22.

d.

Slide the shaft out.

e.

Disconnect the cables from connectors AlAlJ1-J5.

f.

Remove the AC line filter AlA5 by removing the four H13

6-4

screws.

Replaceable Parts - Model 64110A
g.

Slide the primary board AlAl, out of the power supply
Al.

assembly,

******************* CAUTION ********************

*

*
* The control return (Cont Ret) and control in *

*
*
*

(Cont In) test points can be bent during removal.

*
*
*

**************************************************
h.

Assemble in reverse order.

6-14. +5/+12 VOLT SUPPLY BOARD REMOVAL.
ASSEMBLY AlA2.
a.

Remove the power supply assembly Al.

b.

Remove the six H22 corner strut screws. The two corner struts
MP20, MP21 and the power board brace MP19, can be removed in one
piece. Refer to figure 6-9.

c.

Lay the power supply on its side with the fans facing down.

d.

Remove the two H19 +5, -12 volt board screws.
There are two
access holes in the -3.25, -5.2 volt board that allow access to
the +5, -12 volt board.

e.

Disconnect the cables at AlAlJ4 and AlA3J1.

f.

Lift the +5, +12 volt board up
assembly.

g.

Assemble in reverse order. Ensure the board
board guide and sets properly in AlA4J3.

********************

*
*
*
*
*
*
*

CAUTION

and

out

of

the

power

slides

supply

into

the

**********************

The cable that connects from the top of transformer AlA2T1 to the AlAl board above has heat
shrink tubing protecting it. The cable from the
bottom of the transformer connects to the AlA3
board below.

*
*
*
*
*
*
*

*****************************************************
6-15.
a.

-3.25, -5.2 VOLT SUPPLY BOARD REMOVAL.
ASSEMBLY AlA3.
Remove the power supply assembly Al.
6-5

Replaceable Parts - Model 64110A
b.

Remove the six H22 corner strut screws. The two corner struts
MP20, MP21,
and the power board brace can be removed in one
piece. Refer to figure 6-9.

c.

Lay the power supply on its side with the fans facing down.

d.

Remove the two H19 screws holding the -3.25, -5.2 volt board.

e.

Disconnect the cable to AlA3J1.

f.

Lift the -3.25, -5.2 volt board up and out of the power supply
assembly.

g.

Assemble in reverse order.

6-16.

POWER SUPPLY INTERCONNECT BOARD REMOVAL.
ASSEMBLY AlA4.

a.

Remove the power supply assembly Al.

b.

Remove the two H22 from the bottom and top
figure 6-9.

c.

Remove the shaft extent ion MP18 from switch AlAlS1.

d.

Remove the two H22 from the front power supply bracket MP17.

e.

Lay the power supply on its side with the fans facing up.

f.

Lift the front power supply bracket MP17 up, until AlA4J2 and J3
separate from both the +5,+ 12 volt board and the -3.25, -5.2
volt board.

******************

*
*
*
*

CAUTION

corner

struts.

See

*******************

Do not pull too hard since AlAlW1 is still
connected to AlA4J1 and damage may result.

*
*
*
*

************************************************
g.

Disconnect AlW1 from AlA4J2.

h.

Remove one H13 and three H65 screws holding the board.

i.

Separate the power supply interconnect
power supply front bracket MP17.

j.

Assemble in reverse order.

6-6

board

AlA4

from

the

Replaceable Parts - Model 64110A
6-11.

CRT DISPLAY REMOVAL.

**********************

*
*
*
*
*
*
*
*

WARNING

***********************

Hazardous voltages exist on the display driver
boards and on the CRT. To avoid electrical shock,
use the following procedure. Wear safety glasses
when handling the CRT.
The

*
*
*
*

*
*
*

CRT may charge by itself while disconnected.

*

********************************************************

a.

Turn off the power and remove the power cord W1.

b.

Lay the instrument on its left side.

c.

Remove the two H26 screws
figure 6-4.

d.

Swing the key board out so it forms a
bottom of the mainframe.

e.

Gently pry out the CRT bezel MP32.

from

the

bottom

of

straight

the

CRT.

See

line

with

the

H19

and

NOTE

The CRT filter MP33 does not need to be removed
from the CRT bezel. If the filter is removed,
replace it with the non-reflecting side facing
out.
f.

Remove the top cover MP1.

Refer to figure 6-1.

g.

Remove the high voltage cover MP66, by removing
two H24 screws.

h.

Swing the display driver A6 secondary board and the
board out of the way.

i.

Disconnect the CRT socket W2.

j.

Remove three H8 screws that retain the CRT, leaving
screw which holds the ground strap in place.

seven
A1

flyback

the

one

6-1

Replaceable Parts - Model 64110A
k.

Discharge the CRT.
1.

Connect a jumper wire between the ground strap of
and the metal shaft of an insulated screwdriver.

the

CRT

2.

Slip the screwdriver tip under the protective rubber cap of
the post accelerator lead and momentarily press the tip
against the lead to discharge the CRT.

CAUTION ************************

*********************

*

*

* Discharge the CRT to the ground test point shown *
* on the AT flyback board in figure 4-1. Component *
* damage may occur if the CRT is discharged to other *
*
* areas.
*
*
********************************************************
TP3

~8

I

r

0

MPl

I

I

8

0

lJ

T

lJ

I\)

I

3

8

4 S 6

I

lJ

--C2---R3-

T

--CR2--

--CR3--

I I
lJ lJ
I I
..,.

I
'"
I

00

I
0

...
I

,

rii13'

0

lJ

FOCUS, ON

INTEN

r R12,

'ON'

~~~

-Rl0-Rll-

-R16--C7-

bJ
DS2

II

,... lJ
"'~

P2

I

--C3--

lJ
ID

I

-CR4-

A7W11

I l'

I

-R14-Rl5GND
-C8-

TPl

0

HHORDR

TP4

G

Figure 6-1. CRT Display Discharge Point

6-8

0
I\)

I
0
m
I
8

Jl---

TP2

--R6--

-CS-

LB.e.£.K...J

-Cl0-

0

-R4--VR1-RS-

0

0

ID

Replaceable Parts - Model 64110A
1.

Remove the high voltage lead from the CRT.

m.

Remove the remaining H8 screw.

n.

Disconnect the yoke cable from A7J2.

o.

Remove the CRT through the front of the instrument.

p.

Assemble in reverse order; except, start the H8 screw in step m
before inserting the CRT. The CRT may charge by itself while
disconnected; be sure to discharge it before handling.
NOTE

Be sure that the ground strap makes good
connection to the CRT mounting ear and
that all H8 mounting screws are tightened
securely.

6-9

Replaceable Parts-Model 64110A

Table 6-2. Mainframe Replaceable Parts List
Reference
Designation

HP Part
Number

C
D

Qty

64III1A

A!.';;
A6
A'/

641'1 (] ··.. 62t:dl '1

0

6411 O····66~.'jOl
64110··.. 66507

7
3

Mfr
Code

Description

MAINf' I411 0····66~'iO'1
64"1 "J.O····61.-J~':;!l;.?
641 J O'-66~:i19
641'1 ()H··66~.:;D6
641 t O····66~)(l~:i
64".1 to"H66~:jOB
l:1411(l····66~iO(jl

64110···61001
b411 O'-6:';i1 o:~

nE.FLF:CnON YDI(E

HI
1.12

11:,00- 0 0 16
I):"lUIl····j:n4

H~l

O:3BO···I:n7

1
4
4
1

SPACER-RND ,188-IN-U; ,194-IN-ID
Sf)Acr:R-·RND .75·-IN-·L.C ,156···(N-ID
SPACER-RND ,1El~'-IN-LG .25-IN-ID ,S-IN-OD

t

GROMMET-RND

1111000

ORnER BY Dr~SCRIPTION
ORDER BY DESCRIPTION
ORDER BY DESCRIPTION

::?H4BO

o:·~n~)·--"lA·61

,2S-IN-GRU-OD

~?n400

0400····0110<)

,0(94 ··TN ":OIA !:nt..

21!l48IJ
2841'10

O:'.:i1 O""OI7'~:';~?'
II ~'i H·-I "!flO

IIIICIlIl
(11)000

H4

[)~'I:III····146·j

H~::j

114011···11 0 11'1

9

H6
H'?

1) ~.:; 1

4

0~'il0···111l0

"

1

HOOK-LOOP

HfJ
H?
H10

01,,<'4···11441
0905-,0923
14111)··1)611

7
6
II

·4

DOOnO

ORDER BY DESCRIPTION

f:l?);:.1.~':j9

;~L···O

;l

8···16 ,6?5-IN-l.G PAN· ~JD-POZI
Q-RING ,176-IN-ID ,07-IN-X[~CT-DIA EPR
CLAMP-FE-CA 1-WD

OM,"l

~:.'j

CFCC··1l

I

PIN-GRV ,125-IN-DIA t·-IN·'·l.G CARB-·s·rl_

~.:!.B4U

[)

() -, {} 9 ~:; ~:.~

14nO"··O~.:jB;:~
;:~~~DO-"Ol

0:'5

6

14
4

;'?2110···0·j·j 1

n

;.?;:~OO-0"1:~9

HI?

?~:?'OO""O'14?

;.';.".011····11 1 64
;.';' fJ O···1116~'i
;:!? 00··· () 1 '7::5

1

?360-'011:~

H;:.~

:7i

"

6

I
Iii
'7

I

6

0 ... n1 ~:.~ (.>'

~:.':·~!:)O····(11133

0 1?4

n····O!)9?

~?~"jlO-·()106

H~I'7

0 .... 0'1

,~.~····IN····t .. G

MACH 4···40

P(.IN····t·tD····PDl.I

,312-·IN-L.I; "l00 DFC
,1BB-IN-l.e UNCI 82 DE~
,25-'[N-LG 82 DEI;

SI:RFW-MACH 4 ·40
4 ·40
SCRfW··MACH 4-40
SCRF:W-MACH 4 ·40
nCF~EI,.) 'M(::,CH 6 3?
SCREW~ACH

1-1N-LG 82 DEG
,:·.~~5~··[N··I. .. G PAN····J·!D····POl·1
,312·-IN-·J_G

PAN·-HD .... POZI
,37~.)···-(N····l .. G PAN····HD····PIJ"lI

6-32

nCRF1N"'Mt-JCH f::.

,375-·IN·l .. G f!?

<~2

,~'.'j-··IN···I..G

D~G

'1 ;)0 DEG

SCREW·· MACH 6-32 ,875--IN-'L_C PAN·_·HD··P071

2;'560···0436

1 O~· 0 0 4::;

~:~Cl~FIAI'

PAN-flD-POll

!~I:REW···MAI:H

5
'7

~:.~~'.)"l

,375-IN-~G

SCREW·-MACH 6-32 .312-IN-L.G 100 Dr:G

?::~60···0;.:?O'7

~~4::'~O'~'0003

SCREW· MACH 4-40

Pf:IN-··:·ID····POZT

/:)

n

~:.~!.;:;

,~.i.~':;····JN····I .. G

4····4D

(I

~;):'~60""{)?()O
?;·~/:;O····04~:~.3

\:)CHFW ·MACH

SCREW MACH 6-32 ,5-IN-LG PAN-HD-POII
SI:REW·· MA1:H 6··32 l-·IN-·L.G PAN-.·ID··-P01I
SCREW ·MACH 6··32 ,312-IN-LG 82 DEC

??;60-··01B;.~

i?;·160~·

sr:HfW·-TPG

SCREW··MACH 6 .. 32
!3CRr:: 1,.j i"'1ACH 6·· ;.~;.:.~

??i60-·· 0 1 ;:~1
?;'~6

E····R EXT
FASTENER

SCREW·-MAC.4 4"40 ,25·--IN-I._G PAN·-HD··P01I

?;'560~'Oll!5

<.>;:\611····1111'7

,125-IN-ID

HFTAJNU~""'I~ING

;:~;,),OO~·OlO'7

HID
HI"
H;:.~ 0

BPACf:.R

'7
8

II!

2
2

4

,~:)6;.:~····TN····L.G

OR1)ER BY DESCRIPTION

0110011
II 0 I) DO
oII I) 00

ORDER BY DESCRIPTION
ORDER BY DESCRIPTION
ORI)[R BY DESCRIPTION

{) n OJ 0

ORDER BY DESUiIPTION

01J1l1l1l

on nil 0

ORDER BY DESCRIPTION
CRDER BY DESCRIPTION
ORDER BY DESCRIPTION
ORDER BY DESCRIPTION

110 Il 1111
OllOO()
1I1l1l1l1l

ORDUI

()DDOO
1101100

ORDE.R BY DESCRIPTION
OI~DFR BY DESCRIPTION

1101100

nRD[R BY DESCRIPTIllN
ORI>ER BY DFS~RIPTION
ORD~R BY DEsr:RIPTION
ORDER BY DESCRIPTION

0111100
0(10011

oeeoo
O[lODO
IIOOIlIl

I:> ···3?

Pr.IN·· Hn ··P07.1

2U4f111

;:;;~6~····:)423

S[~EW-MACH

6-32 ,b88-IN-LG PAN flD·POII

onoeo

ORDeR BY DESCRIPTION
DR1)FR BY DF~ll:RIPTION

NI.JT····HEX···DBl.····CH(.:IM
i"CREW·MACH B· 3::'
~;CHFW-"MACH B ·:·3;:.~

6-··3~:.~·····f

,1)'14, IN fHl<
PAN . +il) ·.pIl71
,?~.';····IN-··! .. G Pr.,N····1·1D····P07.1

!·I·O

,T7~'i···1N···LG

OODull
IInOIiO

111111110

SCREW"-MAC~~

8,-32 ,5--IN-LG 100 DEG

oe(;no

~:CPFI"··MACH

n···;j:,

oonoo

26BO'··O"l'7;:!.

U,39

:·'Il~'iO···O 11116
64110····0l.lS01

"
B

I,..!A!:;H[P··EHL.t)R 1\0, 10
WAf:;HFR·· 1< FYllUAf~n

O·-OBUD;.:~

If

\...IA\;l!-·jE'R 'I I)
'11 ;.'1,··1:,40

HANDI...F

6-10

BY

nRDER BY DESCRIPTION

FXTFNl)[ 1< ····:'iWITCH

Mpr)
MP10

CAP-BTJ~AP

DES~RIPT]:ON

641 UI-OUl!IlIl
64110-·08D02

LAliEI···INFfJ

B

n

n

BY DESCRIPTION

:'S n-4 0 -. 7 ;:.~ ;.:.~ 0

:'.'; 0 -40 ····7 ~:.~3~'.'i
~:j040-·7;:?1?

[) _. 0 ~:'.;99

BY

ORl)~R

:.:!.H4flO
?04f111
204UO
:.'U481l

MP7

MP;.:~4

OI~DrR

;'::l41l0
2!J4UII

;:;U4UO

RETAINER RING-LED CLIP

ORDeR BY DESCRIPTION
ORDER 1
1

;·.::~.'il

(lEI E::i40 .. ··80

::'J 04

()-7;:.~::~~:!

:,(}40····7~::1ry

64110····()060:.:!
641111··04111'7
h411 0···041 11'7
eL.F ;.'DO ATP

Replaceable Parts-Model 64110A

Table 6-2. Mainframe Replaceable Parts List (Cont'd)
Reference
Designation

c Qty

HP Part
Number

0

MP~.~9

64111)····1)1::'1)4
64'110",,01204
~.\ 1)41-,,::'>. 0 113

1
'7

MP30

64'110""012()~:j

MI<11

(4111)"-012HI

MF)32
MP3:1
MI:)34

41140-HI'l6

8

4:no-"ll)~.\7

-4

MP;.:.~7

MP28

':)

DR ~ICK ET ····CABLE CL.?IMP
BRACKEr-CABLE CLAMP
KEYCAP-L.INE
111~ACI(LT·-nTI1AIN RF.I._H::F
BI,ACI{ FT···L.ED
BLZEI_·-CI~T

CRT FILHTl

Mfr
Code
~.~n4H

()
284BO

Mfr Part Number

:01'141'10

64110 .... 01:."114
6411U .... Ol?1I4
5114! .... 20HI

2B4no

641"J.

;.:.~B4no

64"l 1 0 .~. 0 "1

?841HI
?1:l480

41140"'1Bl6
43:30--1D:i'7
411411"1814
411411-H1l4

O····Ol;:.~(J~::;
;:.~"l

':!

nIllE FDClT ..-FRCINT

':)

STI~UT·"·COl~NFI~

284J.:10

~';(l21l"Hln'7

(,

[iTAUT-CDRNER

:'.'jil:? ()-f:iH/;'J

o····n~.:I~;nl

'I

64110 .... ()011)1
4040 .... 11'1'17

';.'j

BOX ···C;HT ELl)
DLCI(
Ctf\:~D CUIDE

:.·."D4011
:..'1:\400
284E10
:"041.11)

4040''181'7
4i14()-IDIID

MP36

41140-''11'114
4041)'-'11'114
50:.,0-·mB'7

"

MP37

:.) 11:'.'0 ..·1:\1'1:;'7

MI':Hl
MP39
MP40

MP:~~j

Description

6411

6
6

GIllE FllllT ..--FRONT

'I

;:?fl4flO
::"IHOII

B

64·.\ lO····O::i~.'jDl
641111·_·11111111
404i)· Hll '7

MP41
MP42
MP43
MP44
MI:145

9

CARll CUIDE

2841'111

I'l
8

HE2.EI .. ·..·FI1DNT

"D4f10

~::jO;E.O-·BB()5

~~84H

4I)AO-'181l'1
64110 ..-IlIlSIl1

'I

EllAMI'o·..·FIlUNT
r:Fl.EI.·.. !lE(.,!l

:.':1:1400

9

GTRUT·-TUP

~:.~84n(]

4040-·! 1:109
6411(1,,01150'1

MP46
MI:)47
MP4B
Mr)49

6411 1l"-1I0~)1l3
64110 .... 1)::.:01)1
6411 0-"1I1:~1)6
64110 .. ·01206

n·lrnn···HOTTCM

:.'.'0400
;,8400

6411 O·"OO~';r13
64110 "-O:'UI II '1

3

CA,iTING'-REA!l
SPACE:R-·BCARD GlJIDE
SPACER-BOARD GUIDE

MP~50

71:"I .... I:.'TI

;.:.~

1... ABEt..···l.JPPFr<

HEt.I!~

LABEI.. ·-·CAllll CAer"
1.. ABEL·LOW l'EAH
LABEI..··.. INFCI
TI'OUCH-·CABLEKE.FP

~?n4·nfl

?1l4BO

71 ?1····12::36
'7 .J ~.ll _...\ ~:.~ ~~ ~::j

2841111

71:.:?1····1611

,'1'14130
:!(401)

64'.1 1. ()'-'O;"3111
6411 0 ···O"J.;':~l;:~

MP51

4040-·HI17
41)41)-·181l13

1

8
':1

'71;.,1-,1:':36

MP5;~

'?:l~:~1""'l?3~';

MP53
MP54
MP55

71?1-,t611
b4110-'0:'3111
64110 ... () 121 :?

6
1

MP56

641111 ..·2:',:;1;)3
64 t 1 0 ···0 '12,1 ::.'j
6 i fl '1 0 "?370'l
64"1 10···'~?::5'70?
4041)-.. 1011'7

'7
4
'7

MP57
MP~.;iB

Mfl59

MPbO
Mr)61

MPb2
MP63
MP64
MP66
MPh?

CLAMP-CABLE REAR BOARD

0
7

~:s

b4110··"0410~.'.:i

7

~j040····?;.~n~:.~

I]

'?
4

64:1".1.

,~84011

64110····0"l20b

::'D4811

71;:.~·1····1?3'7

?B4BfI

r.

'I

2B4HO

6411

VI

:'<11'711·_·11 04\'

II

TUBE ELECTRON LRI

;::1141'10

20?O···O(}4 r:;

WI

B12(J····"1~57H

1
B
9
1

CABL_E ASSY 18AWG 3-·CNDCT JCK-JKl
CABI.. F· elH BAbE

::;1)4011
;:~n4n()

1'I1?1i····l:.1'lB
641:\0'''61601

CABLE (REAR)

284UII

64110····6tbO;.:~.

3

CABLE~DWER

?B4nO
28400

64110'616114
64110·-61614

w:?

W3

W4
Wl1

64'11(1,-,6'1611'1
64'11 II · .. 6 160 :.".
641111"616114
64110 ..-61614

e!\F!LE . KEYfiOARD

LIGHT

See introduction to this section for ordering information
"'Indicates factory selected value

O····Ol;.:~();:!

6-11

Replaceable Parts-Model 641l0A

Table 6-3. Ai Power Supply Replaceable Parts List
Reference
Designation

HP Part
Number

D

6411 0···66~d I
64110-665t:3

9
I

C

Al
AlAI
A1 A~~

Al A3
A1A4

64"11 O····66~:i14

A1 AS

~)4t to··-6~.~70·1

A1Bl

3160-0339

At B2

:n 60···0:539

A1Fl

2110-0342
;~;'.OO-·OI1l3

A1HI9
A'lH22
AIH23
A1H32

2200·-0165
~~~560-H0115

~

2
6
4

13
4
8

;.?B4BO

BOARD ASSEMBLY
BOARD ASSEMBLY} +5/-12
BOARD ASSEMBLY} P.S. -3/-5
BOARD ASSEMBLY-P,B, INTERCONNECT
LINE FILTER ASSEMBLY

2H400

FAN-TBAX 95-CFM 95/128V 50/bO-HZ

a!480

~lI60···03:l'Y

FAN-TIAX 95-CFM 95/128V 50/60-HZ

;.~~:t4aO

3160-0;1:59

FUSE 8A 250V NTD 1.25X.25 UL

'J~:.:j

SCREW-MACH 4-40

11110011

,25-IN-LG PAN-HD-POZI

6

/;

SCI~EW~··MACH

B

SCREW····MACH 6·-32

6····3~~

AIH37

i~510-··0192

6

SCREW-·MACH 8-32 .25-IN-LG 100 DEG

AIH64

2'1.

'10-·O~i69

3

A1H65
Al H66
AIH67

09
2;:?OO·.. ·Otb7
2~360-·0;.?1 ()

B

8

o

FUBEHOL.DER COMPONENT NUTI THREAD M12.7
SCREW-MACH 4-40 ,438-IN-LG PAN-HD-POlI
SCREW-MACH 4-40 ,375-IN-L.G 82 DEG

8

SCREW-MACH 6-32

AIH6B

~.~360--0

'1 B2

5

4

AIH69

:H60-()~~29

9

SCREW-MACH 6--32 .312-IN-LG 82 DEG

B

FASTENING CLIP

A1MP12
AI MP t:3
A IMP 14

;.'?1111···1156~i

9
0

AIM? I ~'i

641l0-04101
6411 O·-·Ol~?Ol

A IMP 16

1

€I

:1

AIM?I?
A IMP 18

64110-0L.:?17
64110·-23'703

AIMPI9

64110-0U.~16

6
I
:7i

A1MPt?O

50~~

0 -Bf:l3'7

6

AIMP21

50;.~O-88~~7

6

Al WI

.625-IN-LG 82 DEG
,:WO IN WI) BY

91 ~:.:i

,:57:5 IN H

II 00 0

Ii 0 liD 0
1100011
II 0 0011
;>1:14811
11011 0 II

3141108

ORDER BY DESCRIPTION
OR_)ER BY DESCRJP·fION
ORDER BY DESCRIPTION
ORDER BY DESCRIPTION
ORDER BY DESCRIPTION
ORDER BY DESCRIPTION
:.:.~l

J

O····O~:j69

111111011

ORDER BY DE!:;CRIPTION
ORDER BY DESCRIPTION

0000 II

ORDER BY DESCRIPTION

000011

ORDER BY DESCRIPTION

;'.'1'141'111

;.:') 160 ..··0 ;·5~~9

FUSEHOL.DER CAP 12A MAX FOR UL

;,~n4f111

FUSEHOLDER-EX·fR POST 12A 250 V

:.?1 t

;"1l4E10

;.:.~"I1 O-O~:.'i66

O····O~:i6~:;

284UO

64110··.. 01::?07

1

CUR-·LOW VOLTAGE

20480

(J

BRACKET-FAN

2B4HO

641 j 11···041111
b4110···01;'!01

BI160:0
641111··6160:5

0
0

CABLE····FAN
CABL.E-FAN

AIW3

641lO····616lt

II

CABLE-POWER SUPPLY

6-12

(,41·10·-62?Ol

O·~·66!:.'j13

[{RACKET-FUSE

3

A"I PI

0

2H4~3

OO(}OO

2

4

()4"J.10··-66~:51;.?

I)

;~360-·011'1

2110--0566
641 H-01207

64"11

64"1 1 0-66~:i14

2B4BO

SCREW-MACH 4-40 .25-IN-LG 82 DEG
,312-IN-LG PAN-HD-POZI
,T75··~IN·~·I...G PAN-HD····POZI
,681l···IN·-LG PAN·-HD···PUZI

641 1 0--66~:;11

~~B4BO

213480

SCREW-MACH 6-32

2360-0436

~~200-'Ol

Mfr Part Number

POWER SUPPLY ASSEMBLY
PRIMARY

6411 0 H"66~)1 ~~

A I H1:l

Mfr
Code

Description

Qty

2D4BO
;284BO

See introduction to this section for ordering information
*Indicates factory selected value

~!::.:.i 1····316~:l

Replaceable Parts-Model 64110A

Table 6-4. AlAl Primary Board Replaceable Parts List
Reference
Designation

HP Part
Number

c Oty
o

Mfr
Code

Description

Mfr Part Number

All-II

64110""66::;;11

9

BOARD ASSEMBLY-PRIMARY

Al AIAt1'l

64110 .. ··01~.)1;?l

2.

BRACKET-SWITCH ASSEMBLY

211400

AIAICI
Al AIC:,
AIAIC3
A I AIC4
Al Al C~·.;

OlbO-AH34

6

?D480

11160 ..·4831.,

0160"-4~:i~j4

7
6

CAPACIHIR·.. FXD
CAPACITOR-FXD
CAPACITOR-FXD
CAPACITOR-FXD
CAPACITOR-FXD

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AIAIC'I
Al AIel 0
AIA1CIl
A1A1C"l;;.~

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CAPACITIJI,"+XD ,1. UF +f.10"·20% :·.'.OI)VOC CER
CAPACITOR-FXD IOOOPF +-5% 11.)0VDC CER

;:.~D4BO

01.60··.. ei?,46

;:'[1480
;'~1]41l0

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o160·-·~;;~67
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CAPACITOR-FXD

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At Ale?::?

0180--0:3T1

A1A·.IC:<1

01CO-,·304()

A1AIC24

01BO"':1040
1I160 .... 404B

CAPACITUR"EXD
CAPACITOR"Fxn
CAPACITOR--FXD
CAPACITOR-FXD

0160"-45~:;4

o·160·-4Bl1

O·160·.. ·46;.:.1~5

o"t60·-·!S:?46

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;?D4UO

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1500PF +-5% 100VDC CEA
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CAPACI·fOR·-FXD

()

A 1 A 1 C:.\~·i

01BO--O:":f74

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CAPACITOR-FXD ,1UF +-20% 50VDC eER
CAPACITOR-EXD 10UF+-I0% 20VDC TA

~:; 6 :.:,~ B 9

1\1 AIC:16

o 1130 "·'~946
0160-··4;:;::57

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:.::,D400

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16?99

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;.:.'B4BO
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DIODE ,SWITCHING 80V 200MA 2NS D(]-35
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DIODE··FW BRnG 6DOV 25A

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DIOD[-PWR

t901-00~jO

19'0 1····(} ()~)O

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o~;o

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A1 AICR'l

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DIODF-FW BRDG 1110V lA
DIO])C .. FW BRUG 400V lA

;:!.D4HO
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2B4UO
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pl... TIM .. ·[I

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onDER BY

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1400-'O?4()

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AIAIH16

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4

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~.~190·"O()O~5

I.)

AH~lH'S".l

:."1 '? 0·..·0 0 '.[ 1

U

CABl.,F rIr ,062'-,625·-DIA ,091-WD NYI
SCREW"-MACH 4",,40 ,375-IN-L.G PAN-HD·-POII
SCREW-MACH 4-40 ,25-IN-LG PAN-~iD-PDZI
WASHFR-LK EXT T NO, 4 ,Ilb-IN-IO
WA~:;H[n~"LK
INTI... T NO, "11) ,1 ?::.'j ..··IN-··ID

?

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"l 90

"J.··"OO~].9

90

1-()O;.:.~9

'.l.

1906"OO~:il

1,)[413

ORDFR BY DFSCRIPTtON
DEEC:RIPTION

;?OAHO

?'J.90·"·OOO~:;

;.:?B4B 0

;:.~"l90-~O()·) "1

NUT-HEX-DBL-CHAM 4-4l!-THD ,094-IN-THK
SCRFW-MACH 6-32 ,375-IN-LG PAN-~1D-'POZI
SCREW'-MACH 6-32 1,5·-IN-L.G PAN-HD-P01I
N\.JT ..··HEX····W/\ . KWI~ f.., ···3::.:····THD ,"1 o1)""1 N·_·THI{
SCREW-MACH 10-32 ,25-IN-L,.G PAN-HD-POZI

;::'D4B()

??60"'OOO"l

WASHER-FL NM NO, 8 ,17-"IN-ID ,375-'IN-OD
WI RF ?2.AWG t X;.?:?'
P DL :,>lIK WHT
33 FT,

;.:::D4BO

A·.lA1H~52

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H~,::j6

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t~lA1H59

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'7
4

(,:)1 (,)1

0\3'10 .. [) 10!l

U

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1 ?~'j 1-" 0 ~i(y9

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A!.AU::\

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A1A1J4

"1

6
'I

CONNECTOR 5-PIN M POST
CONNECTOR 3-"PTN M rOST
CONNFCTOR 3-PIN M PUSl
CONNECTOR 4-PIN M POST

INDUCTOR 430UH 10% ,6DX1,6lG

?B480

'J
'7

CLAMP-'CABL,E ,125-DIA .375,-WD NYL
rUB["[[[CTI10N

;:.:B4f:l 0

Hf,AT!;;JNK
I-IIC,\TS INI(

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1;:' (I ~J'" (Jij 4:1

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1. 40 () _. 0 0 H;.:.~

l,lAHiP4

l'i'lO ..·OOIB

AUHMP5

120~.'i··"044~)

AIAIMP6

1 ~~05-"0373

4

;.;!

270PF +-5% 100VDC CER

[)16[) .. Alll1
0160-'A5~:;'J

AIC::I'I

~.::i ;.:.~

CAPACITOR-FXD 470UPF +-5% SOUDC CER

Al Al G;l:l

AIAICM

Al

0 A?

60-4~:.:.i:::;4

270PF +-5% 100vnc eFR

CAPACITOR-FXD j,OllF 4()OVDC
CAPACITWl-FXD I,DUF 2511UDC
CAPACITOR-FXD I,OUE 400VDC
CAPACITOR-FXD 1,IIUF 400VDC
CAPACITOR-FXD 1,0UE 400VllC
CAPAc:rTDR-FXD

~:,:j62e(f

47()OPF +-5% SOUDC eER
,IlH!F +'''2!!% :'iOVDC CF:r!
,11JF +nO";'~IIr., 50VD!:: LER
2,2UF+-I0% 20vnc TA

CAPACITOR-FXD .68UF+-IO% 35VDC TA
CAPACITOR ..+XD ,6IJUF+·.. 1 0" T'iVDC TA
CAPACITOR-FXD 85DUF+50"lOZ 20DVllC AL
CAPACITOR-EXD 85I1UC+50-10% 200UDC AI
CAPACIT(JR--FXD ,022ur
t-·20% 250VACCRMS)

6
6

A1 A:I Ci!'7
A1 A1C20

A'l.A1C3;:'

;:>1l48 0
~.:j6?B9

CAPACITOI~""FXD

A:IA1.Ci'1.

A"l At

,1W' +8[)-2[)% 5DVDC eER
2,2UF+"II1% 20VDC TA
2,2UF+-I0% 20VDC TA

64110-0'1:"13

'7

o"1 6 0 -·A6?~i

{~1

,0471.1F + .... lli% 1110Vl)C CEfl
,0IUF +-20% 50VDC eFR

0160"'A~)~j4

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AIA1C'l7
Al AICHI
AlA1CI'!
A1 AIC;.'O

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TYPF
TVf)E
TYPE
TYPE

() 00 () 0

Clf.i:DEH

0110110
() 0 00 0

ORDER BY DESCRIPTION
ORDER BY DESCRIP1'I(JN
orDER BY DESCRIPTION

00000

BY

?l:I4HO

30 ;','.; 0·- 0 :~~3 9
01 '·i'l·..·OO 1:1

?84B 0

OD?O-O·.\ 00

;?n480
:."0480

'1

:::.0480

1 ?~:;1'''O~';9(?
1 ;.:.:'~.;·1 - 4 6 W.';

;"D41ll!

204UO

See introduction to this section for ordering information
*Indicates factory selected value

DFbCF~IPTIOi"J

;?;~;"J. ·-4;.:~91

"1 :'::'~.';1-O~:.:,;9
A1I1H!'l
Al AIR8
A1!,1F<9
A1AlI110

Onj7·-046;.:

RESISTOR

;:?.4~j46

AlA1Rll
AIAIRI:.'

:l
9

75K 1%

,125W F Te-O+-IOO

11698 .... 3430

RESISTOR 10K 1% ,125~ F TC=O+-100
RESISTOR 5.11K 1% ,125W F TC=O+-100
REBIBTOR 10 1% .1;:~~.:;W F TC=O+····100
RESl.STUI~ 21 .~i 1% ,12~5~J F TC=0+···100

06'10·-;'3161

RESISTOR 38,3K 1% ,125W F TC-0+-11111

II n;7·-0 4:19

117::;7-,,11442
1175'/-" 0 43U

3

0'7~.'i'7-·0346

2

;~4::i46

24~546
?4~;46

C4-1/8-TO-5111-F
[4-'.I/B-TO"-IORO""F

0:lB8E1

PMES5-1/8-TO-21R5-F

:.?4546

24~.';46

C4'-1 IIJ.-TO-;3832-F
C4 .... 1I8·_·T 0 ..-6011 .... F
C4 .... 1 /8-T 0 .... 5111 .. ·F
C4 ..·1/8-TO .... Sll1·-F
C4·..·1/8-TO·_·cjI11· .. F

24~:j46

C4"'1 18-T Il'-'I 0 Ill-"F

RESISTOR 6,81K 1% ,125W F TC-O+-IOO
RESISTOR 5.11K 1% ,125W F TC=O+-100

;.?.4~:j46

0'7~.\7""1I4:1fJ
0,!~j7-'043l1

RESISTOR

;:.~4::j46

AjAII~16

0'7~.:;7-·02BO

3

I11AIRI'!
AIA1RIIl
AI A1Ill'?

0698 -6450
0698·_·8=O+-"lll0

;:.~4:::j46

C4····1/8-·TO ···56;?R····F

Hill :'iZ IW Mil

21l4BO
'!.04E111

0761,,-00'14
0761-·0014

0

Onj7--0367

'1'?'701

()

RESIf:;TCll~

RESISTOR Hill ,;X, I W MU n:"Il+-20 0
RESIS1'DR lOOK 1% ,SIN F TC=O+·· . 100

~:.~84B

REBHiTClR 1001< 1%

:'IJ4BO

(,1 AII,31

07~57"-0367
0'7~:i'i-··O:.36'7

7
'7

IUA11l3:1

06?f:)-361B

1

A1R34

0'757-.. 0:394

AIA1In:';

1I'7~j7-'03'f4

o
o

Al AIR::!6

U698 .... 343,!

7

Id!,IR:l7

07~57--042B

'j

AIAlfna

on;7-"043D

3
4
4

TC::"~O+····;:.~O{)

,5W F

TC~~O+'-100

RESISTIJR 82 5% 21,01 MO TC=Ot·-200
RESISTOR ~j1. 1 "l % ,1;?~:jW F TC:~O"'-"l 00
IH::nHnnr~

~.:j·l.l

1%

,"l?.::;W F

T(>~O·t·~··100

PME55-1/B-TO-·26Rl-F

THERMISTOR-SIJRGE PTCTR IJSE:n AS SURGE
THERMISTOR-SURGE PTCTR USED AS SURGE
THERM:[STOR DISC 2,5-0HM

1 ",454
l ~:;4~54
1 ::)454

s c ;.~ ;.:.~ 0

VAR HiTIlR'-1 :lIlVAC
VAfn,;TIlR-l,lOVAC

;::'8400

:.'.'134811

08?i7·-01 :?O
01;137-01 :,0

;'H480

19'/0"-00:;0

0837--0;.?1:7;

IIB;l7-1I1 'n

I,) AIRVI

on37--01:~0

AtA1RV;'::

111337-,,0120

A1A1BGl
AlAiSC;.:.:

1 '1'70 .... 00:;0

8

TUBE-ELECTRIlN

SURGE V PTeTR

·.l(i'70-··OO~;O

B

TUBE~ELECTRUN

SURGE V PTeTA

AIA1Tl
~11A'1 T:?

(?10 0 '-41 9;:!.
91 0 O·-·26~.:i2

AlAIn
Al A1T4
A1AIT,;

'1100"-041'7

TRANSFORMER-BALUN
TI,ANSFOf{MER

O'-;~659

24:';46

C4-1/8-TO-1621-[-"
C4· .. 1 18'- TIl'-'~;lll'-'F

OB:37·-();.:~1~:i

TRANN'ORMER~POWER

?

C4-1/8-TO-51Rl-F
C4-1/8-TO-5IR1-F

;.:.:4546

Al AlfHI

6

FP42-2-TOO-B2RO-J

;.?.4~:j46

0:1HBIl

IUAlfH3

91 0 O-"~~6:=;;9

115/230U 48-66HZ

TRANI"FORME:I{

~~4~:i46

0

19'70-00\:;0

284~;1

0

9100····419;~

:'~848

0

f/l 0 0-26~:i;:.~
9100 .... 041'7
9"100-265 1»

::'iJ4UO

;:'B480
284[10

TRANi3FfJRMER

()360····0~i;·3~5

fERMINAL TEST POINT PCB

A1A1TP~':::

O;·~60··-0~j3~:j

TERMINAL TEST POINT PCB

AIAlT!':l

0~56

OM" {) ::'j:'3::;

TERMINAL rEST POINT PCB

Al A1lJI
AJA1U;.?
PC! AlI.n

1 n;.:~6-- 0 ~"56:::;

IC . -TL4'Y4

1B;.:.~6··-006~5

Ie COMPARATOR PRCN 8-DIP-P PKG

t)O~:;4::j

"l

AIAHl4
A I AIU~)

lB;.:.~O·-·?11

f~d

AHJRl
fHA1VR?

11:);26··- 0 34~;

MAlVin

:\ U;.:.~6····O?76
11l::'.6·-01347

182.0

··14;:.~~1

Ie D·J)Ip ..-P PKG
'I
4

f.e

Dr~VR

TTL. INV

tlG~.l20

SG····3

:';~B48

A1A'!TI"j

1826····06BO

07~57-036'7

~::~~167

RESISTOR 26,1 "1% ,1;?~5W F TC=0+···100
1~ESI!3Tf]I~ l .6::~1< 1% ,12~5W F TC::::O+····100
RESIS'TOR 5,11K 1% ,125W F TC=0+-100

A1AIIH?

91 ()

24~546

o

A'J.A1R3~~

Al

RESIST[~

REsnnOR
REBISTOR

IJ
8

,125W F Te=U+-IOO
,!25W F TC-0+-l00

C4-1/8-TO-7502-F
C4-"!/\3-TII-I002""[-"

24~~j46

MAIRl3
AlAIR14
AlAI RI,;

o'n:; 7 .... 0 4;lll

Mfr Part Number

9100····;.?6:i9

011000
00000
0011 0 U

ORDEll ElY

2()4HO

1026"'0680

:.'.'13480

1 B~:.~6-0~.:;65
UPC311C

o 129~:j

Ie MV TTL. LS MONOSTBL RETRJG DlJAL.

().\

Ie v RGLTR 10-220
Ie 78l(15A v RGLTR rO-92

07:.:::63

;:.)9~)

ORDER

AlI\lXUI
A1A1XU2

1200,,-0796

B

SOCKE'T-IC 8-CONT DIP DIP-SLDR

1200,-0607

4

SO[~ll-IC

,\1 AIXlJ3
il1f;'.IXU4
A1A1XU::.:;

1;:~OO'-0796

1:'1111-,,116117
1 ;.::.00·..·0607

A1A1XU6

1;~~OO~··()796

AIAISI

3101····2150

8
II
II
B
1

SOCKET-Ie S--CONT DIP DIP-SL.DR
SOCKE'f--Ie 16-CON1' DIP DTP···SI.DR
SOCKE'f-IC 16-CONT DIP DIP-SI .. DR
SOCKET-IC 8-CONT DIP DIP-BLDR

6-14

"iWITCH-·PE<

16-CONT

DJP-ALPR

BY DESCRIPTIDN

r;N'7546BN
f:)N'74L.S12~3N

'j

Ie ·RFF--O;?

8;.'6-·116BO

UA78M12UC

047B

MC?m"O~iACP

;:.~n480

11:1:'6-111:147

:."1l481l

1 ;.:~O 0-0'/96

;:.~El4UO

1:"00-0796
! ;'0 O-Ob07
I?OO"'060'7
I ;~O 0-0796

1200'-0607
;.:.~n4B

[)

;'1'14811

:.:.:13480

See introduction to this sectioD for ordering information
*Indicates factory selected value
-

DEHCIHPTIIlN

ORDER BY DESCRIPTION

3101-;~150

Replaceable Parts-Model 64110A

Table 6-5. A1A2 +5/-12 V Board Replaceable Parts List
Reference
Designation

HP Part
Number

c
o Qty

Mfr
Code

Description

A'IA2

641111··66524

4

BOARD ASSEMBLY,

AIA2CI

01<,O'-4B3:,!
11160 ..·48:,2
0160'-4B32

4

CAPACITOR·-FX!)
CAPACITOR·.. FXO
CAPACITOR-FXD
CAPACITDR-FX!)
CAPACITOR·-FXD

. 01lJF +'·'10% 100V!)C
.011.JF ,+·,,10% IIlOVDC
.011.11' +-10% 100VDC
100UF+50-10Z 35VDC
III OUF+50'-1 0% 35VDC

CAPACITOR-FXD
CAPACITOR-FXD
CAPACIHIR .. Fxn
CAPACITOR-FXD
CAPACITOR-FX!)

IIlI.IF+-10% 21lVDC TA
10UF+-l0% 20UDC TA
:l:3IlUF+~iO·"IIl% :15VDC At.
10UF+-l0% 20UDC TA
1000I.lF+50-10% 10UDe AL

CAPACITOR-FXD
CAPACITtJR .... FXII
CAPACITClR-FXD
CAPACIHIR···FXD
CAPACITOR-FXD

6. aUF+-·l 0% :,~'iUDC TA
.IUF "-10% 50VDC CER
1000PF +,-5% 100UDC CER
;,. 2UF+-l 0% ~~OUDC TA
2.21.11'+-10% 20UDC TA

A1A2C~!

A1A2C:S
Al A~~C4
A1 A2C5
A 1 A~.~C6
A1 A2C7
AIA~?'CI3

A1A2C9
A1A2C10

4
4

III 1]0-2945

B

0180-2'745

8

11180·.. 0374
0180·.. 0374
IllEI0 .... 2946
0180 ..·0374

;S
3
9

3

1I1f.11I-·;~948

1

A2Cl;~

0180-0116

A'J A:2Cl:1
At A2C14
A1 A~~Cl~"5

11160-Arn~j

1
7

0160-4822

2

A1

A1A2C16

01BO·"1I197
0'1.80-0197

AIM!Cl'7
Al A2CHI
Al A:~CI9
A1A2C20
A1A2C21

0160-AE122
0160-40:,:2

A"1A2C;.~2

() 160-04032
01BO-294B
0'180'-2948
() 1 BO···:2948

Al A~.~C~~]
Al A2[;24
A1A2C2::j
A"l A2C26

0160·-0164

0160,-011>1
O'160-4f.l32

OHI0"·0'~91

Al A~?'G~:~7

01BO·-O~~11'1

A1A2C28

0180-0291
IIHI0-'0291

A1M~C2IJ

A1A2CRI

7
4
4

4
1
1
'I
;\

A1 A~.~CR;~
A1A2CR3

1901-00~iO

3

A1A~~CR4

190 1·-0 n~:jO

A2CR~i

:,

'I '~01··11 050

3

AIA2CI16

190 1-·11 O~jO
1'701·-00:50
1 "06-·112:39
1901-11028
'I'?Ol-'0021l

Al A~,CRIl
Al A2CR 1~?
Al A;.?CR 13

4

'I
1
f.1

0160-4f.13:~

AL
At..

0

~~.B480

0180-2945
011'10-,2945

CAPACITOR-FXD
CAPACIHIR ..·FXD
CAPAClTOR"·FXD
CAPACITOR-FXD
CAPACITOR-FXD

.0IUF +-101 100UDC CER
10001.11',+50"·10% 1 Ov!)e Al..
1000UF+50···10% 10U!)C At..
1000I.JF+50-IIiZ 10UDC AL
lUF+-l0% 35UDC TA

5
5
5

A1 A;:~CR 19
AIA2CRi"0
Al A:.~CR21

1901-'OO~jO

1901--0050
1 ~T!llHHOO~jO

3
3

Al A2DSl
A1A2H16
AIA2H23
A1A2H24

2360-0117

DIODE-FW BR!)C 100V lOA
DIDDE-FW BRDG 400V 'IA
DIODE-SWITCHING SOV 200MA 2ND DO-35

DIODE--SWITCHING 80V 200MA 2NS DO-35

:;

1901-0028
'I901-'00;,!13
1(1'01-0028

IIIODE .."SWITGHING f.10U 200MA
DIODE-SWITCfHNG 80U 200MA
DIODE-CT-RECT 45V 30A
DIODE-PWR RECl 400V 750MA
DIODE-PWR RECl 400U 750MA
DIODE-PWR RECT
DI0D~-PWR REGl
DIIlDE-PWR RECT
DIODE'~WR REGT
DIODE-PWR RECT

1~T01-'OO~:~B

400U
400U
400U
400U
400U

750MA
750MA
750MA
751lMA
750MA

"NEI DI}-3'.,
2NB DO"·35
DO-29

00-29

;:~a48

~.~b2BC'

1~'iODI116X902I1f'2

1 !:iODl

'.!B4BO

180-';,!946
150D1 06X90 :,!OB,~
0'180-':'.'948

~j62B9

:.?'84BII
~i6c~89

;'.!1l4ElIl
2e4tlO
5621;19

211480

'.!B4BO
2i:l480

o1130-294E1

2B480

OH10"·294B
() 1110-29413
1 ~:jODl 05X9035A;:~

,~ll4EIO
56~~B9

~5b2B'"

l~:;ODl 05X903~:jA;:J

'1 ~SODl

1fJ546

UJ'l4flX
UE41il
190'1-0050
1'?1I1-01l50

lB~:j46

2f.1400
"B4BO
2t14tlO
,.'13480

19(Jl-OO~jO

SDM··241

A1A~~Wll

031:10 ..·01 '1'1
O:lBO-OB43

4

;!.04BO

1901"·00'!B

~'.!El4BO

1 '90 1-00;?f.l

DIJ···2'~

2H4BO
:?1l48 II

1'101,-0020
1 '?III-OO;"]
'1901'-0028

DO-29
DO-29

O~j(tO"H0076

1
6

:'.:'i80·"000:1

:":i

~~050'-000~:j

5
7

A 1 A~?H7~.)
A1 A2H76
A 1 A;,H7'7
At A2H71l
Al A:2H7'?

3050-0791
O;IB 0·..· 0;S;,7

A 1 A2H80

'1400-02.4"

A1A140HH04~.:;9

:30~.:;O-0239

9140-045'1
'1140 ..·04:';7
9'l40-0~iO 0

,;.~5"··lN··I..G PAN·"t·IJ)···P07..1
.3'75-IN .... U; PAN·-HD·-PIlZI

SCReW-MACH

,5-IN-l.G PAN-HD-PDZI

WASHER-LK EXT T NO.4 .1Ib-IN-ID
NLJT ..·HEX··.IHCR lPH l1N
o lUI Ell BY DICSCrnPTIDN
O~5Cy

0-0 076

~~B4f:1O

30~:;O-OOO~.:;

;'~B480

3n~)O-O;:.~:39

284110
,~0480

3051l .... 0791
0380-03:27

CABLE TIE ,062-.625-DIA ,091-WD NYL

06383

PLTlM-S

CONNECTOR 4-PIN M POST TYPE
CONNECTOR 4-PIN M POST TYPE

,'04BII

1 ;~:=;1-31 '/5

~~8480

12~:i1-3195

;"B480
284E10

9140-0459

::'1l4BO

9'140-04~)?

284fJO

9140'-OSOO

SPACER-·RND .125-XN-LG ,09-'[N-ID

2

1911'l-'00;~1l
1';>OI-00;~8

DO-29
DO-29

HCREW .. ··MACH 4-··40
SGRt:::W ..·MACH 6 ..·32

NUT-~~X-W/LKWR

lS'Ol-0050
1901-0()50

~~B4f:10

4
6

1

05X903::jA~!.

111281
204130
,!1l480

~:'~2(JO""Ol;')9

;.:J.4~~O-OOOl

l~'=;ODl 05X90:~~:iA2

\:j6?89
~562B('1

21l4!l0

A'1A2H56

01f.IO·.. ·48:~r~

i.~B480

L.ED-LAMP LlIM-INl'=200UCD

:.:':.:!60-·OO 111

1 ~:SOD;.:~~?'5X90;':'~ OA~~
0160·'-4822
o'160 '--483~~
1l160-0'l64
0160···0161
0160-4E132

~~~B48 0

7

2.190-0005

1 ::iOD68~iXC?O 3~'H):':~
0160--4835
0'16 0 ·-482~.~

;;?B4BO
:':>.1'141'10

1990-06B~7j

6-:~2

06X9020B;:~

150 D22eiX90 2. 0 A;:!

nl4BO
;,:?H480

4
I

o

~j6;:!89

DIODF.>··!lWnCfHNG nou 200MA :'.NS DI}··3~;
DIODE-SWITCHING 80U 200MA 2NB DO-35
DI0DE·-!,WITCHING 1l0U :'.OOMA :.:~NS llll·-:l~.)

;.:~360··H012"l

0160··4B:1,!

o160-4B32

5~1;?f.19

3

A1A2H50
A 1 A;.?H5;.~

Al A2H72
1\1 A2H7:,
AIA2H74

~~n4l10

DIIJI)[--SWITCHING SIlU 200MA 2NS DCI"·3c.i

I
'7

A1 A2CR14
A 1 At~CI~ '1 ~5
A1 A2CR I;'
A1A,!Cll'1'7
A1A2CRlil

'I'~01-·01128

2.H4flO
,!1l4E10

CE~

CAPACITDR-FXO lUFo-l0% 35VDC TA
CAPACITOR-FXD lW=+-10% 35UDC TA
CAPACITDR-FX!) IUF+-IO% 35UlIC TA
6
9

A1A2cr~7

21l4EI0
CEI<
CEil

CAPACITOR-FXD 1000PF +-5% 100VDC eER
CAPACITOR-FXD .0'11.11' +-101 100UDC CER
CAPAClTDR .... FXD • O:39UF +·"1 0% ;~ 0 OV!)C POL YE
CAPACITOR-FXD .0'lUF +-10% 200U!)C POLYE
CAPACITOR-FX!) .O\I.IF +-10% 100VDC CER

4

1906-0079
'1906·.. 00116

A1

4

+5/--12

Mfr Part Number

INDUCTUR
INDUCTOR
INDUCTOR
INDUCTOR

lMH lOX
IMH 10%
100l.lH 10%
22UH lOX

See introduction to this section for ordering information
*Indicates factory selected value

9140--0459

6-15

Replaceable Parts-Model 64110A

Table 6-5. A1A2 +5/-12 V Board Replaceable Parts List (Cont'd)
Reference
Designation

HP Part
Number

C

D

Qty

Description

1205-0219

o

1205-0242

9

1205-0242
1'205-0373

9

7

1205-0~~n

7

HEAT
flEAT
HEAT
HEAT
HEAT

At A2MP6
A1A2MP7
A'IA2MP8
A1A2MP9
A'I A2MPI 0

3103-003B
;110;3-0038
64110··61613
64110-09101
64110'-09101

7
7
2
3
3

A1A2Ql
AtA2Q2

1fl54-021f!
1854-0215

A1A2Rl
AtA2R2
AIA2R3
Al A2R4
A1A2R5

0698-:5156
075'7'-0437
07:57··028;3
0757-0437
on;7-0280

2
2

Al A2R6
A1A2R7
AlA2RB
AIA2R9
AtA2Rl0

0757-·0444
0757-0437
0757-028:5
0757-0280
0757-0437

1

;3
2

A1A2Rll
A1A2R12
A1A2Rl:l
A1A2R14
AIA2R15

06'18-00134
0757-0437

2

0699-0752

o

2

AtA2Rl6
AIA2R17
AtA2R1B
A1A2R19
At A2R20

0698-7518
0757-04513
0'757-0290
0757··11194
0757-0458

8

2

7

2

5

I
1

A1A2MPl
AtA2MP2
A1A2MP3
A1A2MP4
A1A2MPS

A1A2R21
A'I A2R22
Al A2R2~~
AtA2R24
A1A2R25

07~j7'-04~'17

0'757-0428

1
/,

6

SWITGH·-THERMAl.
SWITCH-·THERMAL
CABLE··TEMP REGULATOR
SPRING··THERMAL nr!ACKET
SPRING-THERMAL BRACKET

28400

28400

310;5 .... 00:58
:HO;3-0038
64110'-616U
64110···0910'1
641"10-09101

TRANSISTOR NPN f:iI Pl)=350MW FT=;IOOMH'l
TRANSISTOR NI'N 5): PD=350MW FT=300MHZ

04713
0471;3

2N~:"i904

RESISTOR 14,7K 1% ,125W F TC-0+-l00
RESISTOR 4,751 1% ,125W F TC=O+-IOO

24546
<'4::;46

RESISTDR 2K 1% .125W F

24:'.;46

;':~B480

2B4BO
284(lO

TC:::O"'~~100

RESISTOR 4,751 1% ,125W F TC=O+-IOO
RESISTOR IK 1% ,125W F re-0+-l00

24~i46

24546

2N:3904

C4-'I/8~rO-1472-F

[;4····1/8- TO --4751'-F
C4···1/I3-TO .... 2001··"F
C4-1/8-TO-4751-F
C4 ..-1/8-TO-·1001 .... F

~:l.4~:j46

I I ,125W F TC=Oi-l00
1% ,125W F TC=O+···IOO
1% ,12~;W F Te=0+-100
1% ,125W F TC=O+-IOO
,1 % ,125W F TC=0+-25

24546

28480

C4-1/8-TO-2151-F
C4··-1/8-TO··4751""F
C4 .. ·1/B·-'1"O-A751····F
C4 ..··1 18·-TO ..·1621···F
0699--0752

F 1'C=0+·-50
F TC-II+-IOII
F TC=0+'-100
F TC-II+-100
F TC=0+'-100

'l'i'70'1

MF4Cl/B-T2-200R-C

9
2
1

9

1

7
1
2

0757-0442
oni7-·02BO
0698'-7:118
0699 "0752
11698-3696

A1A2R31
AlA2R32
A1A2R33
AtA2R34
A1A2R35

11698-·0093
0757-0280

AtA2R36
A1A2R37

2100-2633
0757-0431

5

A1A2ST'l
A1A2ST2

3103-0038
:51113·.. 00:513

AIA2T1

9100-2657

A1A2Ul
A1A2lJ2
A1A2U3
Al A2lJ4
A1A2115

1826··0680
1820"·1577

A'IA2U6

1 B;~6-0680

:;

A1A2VRl
Al A2VR2
A1A2VR3

1826"~039;'5

7

1 f:l~~6-0221
18:?6-0677

o

1;~00'-0796

8

4

1200-06:58

"I

2

9

RESISTOR
RESISTOR
RESli3TOR
RESISTOR
RESISTDR

2,151
4,751
4,751(
1,62K
1, 78K

RESISTOR
RESISTOR
RESISTOR
RESISTDR
RESISTOR

200 ,25%
51,IK 1%
6,19K 1%
1,47K 1%
51, IK 1%

RESIIlTOR
RESISTOR
RESIi3TOR
RESISTOR
RESISTOR

499K 1% ,12~;W F rC=0+··"1011
lOOK 1% ,125W F TC=0+-100
101( 1% ,125W F TC-O+··lOO
II< 1% ,125W F TC-O+-IOO
lOOK 1% ,125W F TC-O+-IOO

,125W
,125W
,125W
,125W
,\,!5W

RESISTOR 10K 1% ,125W F TC=0+-100
RESISTOR lK 1% ,125W F TC-II+-100
RESISTOR 200 .2~j% .12.5W F TC=0+-'50
RESISTOR 1,78K ,1% ,125W F Te=II+-25
RESISTOR 39 5% lW MO TC=0+··-200

3
B

o

5

o

RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESI!3TIlR

3

;1
4

2

10 5%
lK IX
'IK 1%
b,81K
10 IX

IW MO TC=0+-200
,125W F TC-0+-l00
,12~!W F Te··Oi···l00
1% ,125W F TC=0+-1011
,125W F TC=O+-·IOO

24546
2.4~:146

2.4~i46

24546
~?4546

G4"·l 18-TO··1 ,!12'-F
C4 .... 1 18-T 0--47:5 1····F
C4"·I/S-TO-2001-F
C4·,,1 18-'1" 0-,1 00 'I···F
G4·-·I/S-TO-4n;I-F

24546

C4-1/8-TO-5112-F

'l'i'701

MF4CI/8~rO-6191-F

~:~4546

C4-·1/13-TO"·1471 "·10
C4"1/S-TO-5112-F

~~4~=:j46

'.~B4BO

06l)B-~~~.:'~1 ~j

~~4~:j46

G4 .. ··1 IS·-TO·.. ! 0 O;~···F
C4···1 IS ..• '1' O-·j OO;'~··F
C4 ..··1/S·-TO···1 00 '1···F
C4-1/S-TO-I003-¥

~~4~.'j46

24546
~?4546
24~=:j46

24546
1 (1'70 1
?fl4HO

C4 ··I/S·"TO·.. IOO:?·.. F
C4-1/B-TII-l001-F
MF4Cl 18 ..··T2-·;!.0 OR·-C
0699'-07~:)2

nl67

FP32-1-TOO-39RO-J

20480
24546
24546

06'?B···0 119;3
C4-I/B-TO-l01l1-F
C4···I/B··TO"·1001 ··F
1::4····1 18·-TO -·6811-·F
C4·.. 1 18·-TO .... \ OR II···F

~~4!:,:j46
24~)46

30(lB3

E'''T=iOX10~!

I>

RESlilTOR-TRMR 1I( 10% C smE-·ADJ 1"·Tr'N
RESISTIlR 2,431< 1% ,12e;w F TC=O+···IOO

(.~454f:)

C4-·1 18 ..·1' O··243j-··r

7
7

SWITCH-THERMAL
SWITCH···THERMAl.

2,1400
;!':l480

3 un··· 0 0 :SEI
:111l:3-00:m

5

4

1820-201 1?

9
6

1
I

lB,~6-0680

5

18"6··06130

7
B

1200··0'196
I ;~00-079(,

8

A1A2XI.I6

1200··0796

EI

TRANSFORMER

284,10

IC 8··Dlp····P PKG
IC SGHMITT-TRIG CMOS NAND QUAD 2····INP
IC SCHMITr-TRIG CMOS HEX
Ie 8"··DIP-P PI(G
Ie S·..·Dlp ..··P PKG

;':~B4BO

IC B ··l)IP-P PI(G
IC

o

AtA2XU~;

6-16

6030B-TT
6030B-TT

24::;46

2

1;~00-063B

13103
1310:3

'j

24546

A1A2R26
A1A2R27
A1A2R2B
A1A2R29
AlA2R30

AtA2XUl
A1A2XU2
AtA2XU3
A1A2XU4

12!05-0242

RESISTOR 4.75K 1% .125W F TC=O+-100

9
3
6

0757-0439
IIn;7-Q;l46

205-0219
120 ~:j-0242

,!8480

RESISTOR 12.1K 1% .125W F TC=O+-100

4

07~l7-02130

;,!1348 0
284BO

RESISTOR 21< 1" ,1,!5W F T(;.'O+-IOO
REiHB1'DR IK 1% ,125W F TC=Oi···100
RESISTOR 4,751( 1% ,125W F TG=0+-100

6

M

TO-66-CS
TO-3··CB
TO-3-'CS
PLSTC-PWR-CB
Pl.STC····PWR-CS

2

06'18-3;~15

0757-0465

SGL
SGL
BGL
SGL
SGL

Mfr Part Number

I,

0'757-0465
0757··0442
07~'i7-0~~80

SINK
SINK
BINK
SINK
SINK

Mfr
Code

V

RGLTR TO-220

04713
2B400

11'126-0680
CD4093BF
MC14584BCP
18"('''·0680

~:~B4BO

10;'6-116110

3L~=:jB5

2134BO

Ie v RGLTR TO-2?0

271114
04713

IC"l..M331l

;!f.14BO

SOGKET-IC
SOGKET-II:
SOCKET-It:
SIlCKET···IC
Sl1CKET-IC

8"·Cl1NT DIP Dlp·-SLDR
14···CIlNT DIP Dlp···i3LllR
14 ..·cmn DIP DIP···SI...DR
8·"CDNT DIP ]llp···:ll..DR
8-CONT DIP DIP-SLDR

I...M;317T
MC7912CT
10"6-06'7'7

~~B4no

1;;~OO"~0796

;,B480
2f1480

I ;.'.!II 0-06:\8
1,'00-·0631'1

;:~B480

1;.:'~()O-0'7t1'6

;,84011

'1200 ..·0·196

1200-0796

See introduction to this section for ordering information
*Indicates factory selected value

Replaceable Parts-Model 64110A

Table 6-6. A1A3 -3.2S/-S.20V Board Replaceable Parts List
Reference
Designation

HP Part
Number

c
o Oty

'BOARD ASnEMHLY .. ··P. S.

A1 A3CI
Al A:3C2
A'1 A3C3
AIA:IC4

0160-483,~

4

o160-4fl33

o

6
4

5

2

o160'M'4~j~:;'7
0160""4557

A1A3C5

0'160-4557

AIA:IC6
Al A3C7

0160 ··ti267
016 0 -48:"~
0IBO"-1I1'n
016(1-483;'.
01 f.) 0-'45:=:;'1

Al A~~CB
A1 A3C9
AIA:ICIO
AIA3Cll
AIA:\C12
AIA3CB
AIA:3CI4
AtA3CI~'i

AIA:ICI6
At A3CI7
AIA:3CIEI
A1A3CI9
AIA:3C20

R

1
4
B

4

4

o

o"l60-~j267

I

'!ll4f.10
284flO
t7ib2B9

()160·-5;.:~67

~~B4BO

'16299

016 0 "~483;;?'
CAC04X7RI1I4M050A

CAPACITOR-FX!)
CAPAClTOR ..+XD
CAPACITOR-FXD
CAPACITOR-FXD
CAPACITOR-FXD

4700PF +-5% SOVDC CER
,0IUF .....-111% 1111lVDC cr:R
2,?UF+-IO% 20VDC TA
2,2UF+-IO% 2DV!)C TA
,039UF +-10% 200VDC POI~E

;!.n4110
;.!B4ElO

o16il-4B~12

11160-,,0164

7
1
I
'I
1

CAPACITOR-FXD
CAPACITClR ..-FXD
CAPAcnOR"'FX!)
CAPACITOR-FX!)
CAPACITOR-FXD

,0391.1F ~-lI1X 2110VDC
10 II OI.lF+~iO-·IIIX IIIVDe
11I00IJF"'~;II"1 0% 1 OVDC
1000UF+50-l0% 10VDC
10001.11'+50-111% 10V!)C

6
6

CAPACITOR-FXD
CAPACIHIR .... FXD
CAPACITOR ..-FXD
CAPM:ITOR ..·FXD
CAPACITOR-FXD

1000UF+50-10% IOVDC
l 0 0 OUF+~iO ,,111% lOUDC
100 0IlF+50-'1 0% 10VDC
:nOOPF +'-'111% :'.!OIlVl)C
3300PF +-10% 200VDC

1I11l0·-~~9413

1I1BO-294B
II 1 1l0-·2941l
0180-29413
OHI0-.. ;29413
olIl0-294B

A1A3C26
A1 A3C;~7
Al A:IC2B
Al A3C29
Al A:IC:\O

II 160-514'}
0160-5149
01130,,-29413
oIBO-O 19'7
1J160-ABIlIl

Al A3C:11
A1A:'3G3;i!
A1 A3C3:,
AIA:,C:14

o160-483~~

4

OI60"-4fn~,

4

AIA3CRl

1 (~06'-O~~39

ou)o-o 15::=i

0160,-0 '155

I

8
4

CAPACITOR-FX\)
CAPACITOR ..·FXl)
CAPACITOR-FXD
CAPACIHIR .... FXD

0160-4822
0160-.. 4tl:n

POLYE
AI..
AI._
AI..

5

o

~~1'141l0

01bO· ·483'?

16299

CACII4X7RI04M050A
o 1611'-4tI:l3
CAC04X7RI04M050A
CAC04X7R I 04MO~'iOA

,~1'141l0

16299
1 tl~~99

5l:t~!.H9
!;;~)2B9'

01611 .... 4f.1:l2
1 t:"iOD;.:.~;,~5X90 ~~OA;~

0160 .... 5267

150 J)~~25X9t) ;?OA~"l
15 OD2~~5X90~!'OA2
0160-,,0164

,~84EIII

11160-0164
OHIO-"2'141'1
O'j 1311-29413
o1 1'1 1I"-2941l
OH10-294B

;:.0480
;0 Il 4fl II
;!.IHIlO
~.:~B4BO

AI.

~~.B4BO

AI..

;'B480

AI...
PDLYE
PGI.YE

;;~H4BO

,0IUF +-10% 100VDC CER
,011.1F + .... IOX lOOVDC CP.I
1000PF +-5% 100VDC CEI
,1I221JF + .... IOX IIIOVDC eEl

M

2(,l4BO

Al

CAPACTTDR-· FXD :1, 3I.JF ,!~iOVDC
CAPACITDR·-FXD :!. 31lF 2~:iOV!)C
CAPACITOR· .. FXD 1000UF+~0-IOZ 10VDC AI..
CAPAC:ITor~'-FX\) 2,21.11"+--10% 2I1V!)C TA
CAPACITDR-FXD 470PF "'-5% llJOVDC eEl

Il
(j

<~134BO
~;!B4BO

01011'-29411
OH10-294B
OHIO--2'f4fl
O'j 611-0 15~.'
0160-01 ~i~j

2H4DO

01 f.dl-5149
01611,-514',

;:.~84BO

0180-2',413

,~1l480

56289

1 ~j 0 l)~?25X('; 0 ;:!. 0 A;:~

0

11160-·4808

2El4BO
,!1l4BO

0"160-4B~~f!.

~:.~848

01611 ..-483,!

'~.84BO

016\1"-4B2:;~

(~!;I480

01611-4El:l:1

01~!.Bl

8D-;~41

4

DIODE-CT-RECT 45V 30A
DIODE-CT-RECT 45V 30A
VOl..TAGE SLiPPRESSOR VRM=2B7V
IHODF .... FW flRDG 400V 5A
DIODE-FW BRDG 400V 5A

2134flO
;'1'1480
284110

1901···0919
I '~06-1I1I'77
1906,-0077

1901--091'y

3

VIJl .. lAGE BIJPPRESnOR VRM=2H?V

;.:'~El480

1'?01-0',19

SCREW-MACH 6-32

,375-IN-LG PAN-HD-POZI
STANl)nFF····RV,.·~·nN ,2~3-·IN····LG 6 ":~;?THD
STANI>DFF-RV1'--DN ,12~:;-IN"-1.I; 4-40THD
NUT .... Hf::X·-·punr.: U·F

6-17

Replaceable Parts-Model 64110A

Table 6-6. AIA3 -3.25/-5.20 V Board Replaceable Parts List (Cont'd)
Reference
Designation
A1A:lR'j1
A1A3rn2.
A1 A:W L>
A 1 A3R 14

HP Part
Number

C
D

Qty

117~5'7"1I401
O'7~r7-0;~80

Description

Mfr
Code

Mfr Part Number

RESISTOR 1011 1% ,125W F TC-II+-1011

;.:~4546
;?4~i46

~?

RESISTOR lK 1% .125W F TC=O+-100
RESISTOR 90.9K 1% ,125W F TC=0+"-100
RESISTOR 10 1/., ,1,;:51,) F TI::"'II+'-1011

9

RESHrrnR 90,9' 1%

RESIS'fCIR 20K 1% .125W F TC=O+-100
RESISTOR 6,8IK 1% ,125W F fC-O+-lOIl

24::'.i46

C4' ·1/8-·T 0 ... 681 1 ..

;'?'4~.:i46

(;4 ·lI8-.. IIl ..·11101 ..·F

3
5

1::4 .. lIl:1-.. TO-!OI··F
[;4 .. 1I8 ..·TO ..·11101 ..·F
C4 ..· 'j 18 ..·T 0·-'/09?· .. F
C4 ·lI8-TO .... lI1PO ..·F
C4 ,,·1/8-·T O"'YOR9"· F

A1A;3Rl~.)

117:57··0464
0'r';7-0:346
11'/';7 .... 04110

A1A3R16

0'75'7--0449

6

A1A31<17

o'n'j?'~'0439

A1A3RHI
A1A;!R19
A1A:lR;'O

07tS'7-()~:.~80

4
:!

RESlf:lTClf~

0757····0446
11'7:5'7-·0400

3
'I

RESISTOR 15K 1% .125W F TC=D+-100

;>4:-.':46

C4

RESnH[)R 911,9 1%

;:~4~.:;46

C4 ·1/8 ..·TO .... 9I1f!S' .... F

F TC-II+-IIiO

;:·.~4546

TC-O~-1110

;':;.4~:i46

C4 .. 1/B··..fO-133'j .. F
C4 .. lI8·.. TO·"".1I0:' ..·F

A"l

u<

"1%

.t2~!W

.1~.~~;IN

F 1I::'::::O+""100

TC::::O+-~100

F

F TC·0+ .... 11111

,1,!~'iW

RESISTOR 1,33K 1% ,l25W
RESISTOR 20K 1% ,125W r

24!:":i46
;.?4~:.'i46

?4~.'j46
~~4~:i46

1::4 ·118 ..·10 .... ;"00,' ·F

+

·1/8···Tn····150;.:.~

··F

A3R~~;'~

on',7-0:117

7

A1A3R23

117~i7'-044'1

6

07~'.)7-04~39

4
6

RESIST[)R 6.81K 1% ,125W F '"C=0+-100

;:~4:546

C4 118 .... '] 0·-1.81 ·.I·T

O'7~)7·-0;':~8~3

C4 '1/8-TII-21101-F

1

RESISTOR 2K 1% .125W F TC=O+-100
RESISTjJR 9,53K 1% .12SW F TC=O~'-100

;.:.1.4::.'j46

069!3·-40~:.~O

;:.~4~.'.i46

C4"· 1/8-'1' 0"''?531''F

0'/~i'7"'11400

'I

RESU:1TOR 90,9 1%

~:.).4:::;46

C4 ··1/B·-TO··. 90R9···F

IIn;7"0446

3

RESI:3TOR
RESISTOR
RESISTOR
RFSIGTUR

;.:.:4~:;46

C4 lIB .... TO .. 1511:! ..·F

1
4

;.?U4f:10

li6'18"'40Hl

0698·_·6612
PME55·-1/B-·l·2-·1821-B

A1A:m;!4
A'~ A3R2~:;
A:lR;~6

A1A3R2'/
A1A:IR:!1I
Al A3R3l
AlA3R32

A1

o69B-66 t~:

A 1 A:.lIl:1:3

o69'!}-~5449

A1A:'11<:l4

() 61.?B~·A;~ 0 {)
06'11)·-3601

"

06 IJ'n····3.60·1

;,~

A 'J. A3R 3~5
Al A31,:\6
AIA3R37
AIA3f<:!1l
A1 A3R:I?
A1A:'m411
Al A3R4I
A'1 A:q~lJ;:~
Al A31< 4:3
A1 A:3R44

Al A3R 4~i
AIA:IR46

~:j

0 ;.~ ()

'N.

;,~ ~51

(,

11761·.. 11044
0'161-0044

9
6

15K 1% ,125W F TC=O·~-100
2K ,1% ,125W F TC=O+-50
1, B;.:.~I< ,1% ,1?:5W F TC:::()+····~.'!1)
51( ,17., ,1~:.'.~jW F TC:::O+··.. ~:iO

1 ;:.~~.';w F "1"C'"-"0+ .. :1 00
r~ESIST()I~ 1 () :=:i7., 2.1.1-1 MO n>=I1+ .. 200
I~E~:;I!:;TOI~ 'j I) ~.';'i.: ?W Mil H>I)''';.,OIl
RESISTOR··-FXD RFt; SEN 2 M[GOHM
REnIBTOR Dr.:. ~:;% 'lW MIJ TI>O+-:'?IIII
:'5, 4"191<

l~EE)I!;;TI·)I~

9
':1

"~.~

.12!:M F TC>=0+·_·'100

, ~~~~;%

RESISTOR 82 5% 1W MO TC=0+-200

0'157 .... 11446

6
'1
3

07t:.;7····039B

'I

RESISTOR 15K 1% ,125W F TC=0+-100
RESISTOR 75 1% ,1?5W F TC=O+·_·100

IIn;7"'0:!46

2

RESIST[W

117:';7-·11346
oni7'-1I4111

;.~

RESIST()R 10 1% .125W F TC=O·t·-··tGO
RESISTOR 100 1% ,125W F TC=O·~-100

~.:iO;.::O····2~51 (~

117~';7-"1I4111

0
11

l~Ef:n:~nm{

··FXD HEB SEN

10 1% ,125W

RESISTOR 100

1% ,125W

;.~

MEGDHM

F

TC-O~-lOO

r

TC-O+-IOII

O:lBIlB
t (}I '7 I) 1
07~BDB

?,?16'7

M1..41::1/8-T2-50111-1
PM~55-1/8-TO····3491R·C

FP42-2-TOO-l0RO-J

~::716'7

FP42 ···r.:'···TO 0-··1 OR 0 ··,T

:"n400
;:0480

~;O;:.~O

:"H4t10
:'!1'I4811

... ~~:il C?
07(,1--0044
11'7,.j ..·0044

::jO~.~O·-2~'.i·l

(l

;:.~ -4 ~'.'; 4 6

C4 ·l/8·.. TII .... 1~;II? ..·F
C4 "lI8 ..·TO-'75R 11·+

;:.14~:i46

C4 ·1/8-.. IIl .. ·1I1Po .. ·r

;.:.14:546

C4 .. 1I8 .... TII·.. 1 OfH)"F
1::4 ·1/8 .. TII .. 'j IIl .. -F
C4 .. l/fl .... TO .. 101·F

;:~4~.:j46

~~4~.:i46

;:.~454b

Al A3T1
A'j A:H;.'

'110 0 -'26~)B

TI~AN~:IFORMER

284f:lO

()100····~~6~IB

()O~"26~.)6

'I

TRAW,FOH MER

:"1:141]0

'):100-26:'56

At AWl
A1A3U;.'
AIA3U3

1820 ..·1200

9

IC DRVR TTL CLOCK DRUR Tn.-IO-MOS 1-INP

A1A:'11J4

'lEl;_:,~6··"OO6~5

At A3U5

18;:.~6·-· 0 56~5

5

1C-T1...494

;<'841:10

lU2.('··'O~:565

AIA:lUXl

L'II 0 .... 0607

11

?1J480

A1A3UX2

t

7

lb····CONT DIP DIP"Sl.DR
SOCKET-Ie '14-CON·'· DIP DIP-SL.DR

1:?OO-06117
1?OO-··06:.3H

6-18

(Pl

"1 H;:~6""O~)6~:i

10;:?6-006ti

~:~OO-'063B

"

04'713

MMHIIII:!6CL

[c····"1"1...494

:"ll4BO

Ie COMPARATOR PRCN B-·Dlp··P PKG

f.; (\ ~54::j

Ie COMPARATrni PRCN 8-DIP-P PKG

nO::.;4~j

..\ n?6-0~.'i6~5
U1"C;q lC
I.IPC:1l1C

SOl~KET-[C

~~~:14BO

See introduction to this section for ordering information
*Indicates factory selected value

Replaceable Parts-Model 64110A

Table 6-7. A1A4 Interconnect Board Replaceable Parts List
Reference
Designation

HP Part
Number

0'-6651,~

A1A4

6411

A1A4Jl
A1A4J2
A1A4:r3
AIA4J4

1251-6481
lt~51-64BO

A'lA4RI
A1A4R2

0757-0346
11698-8812

1200-·0607
1251·-6480

c Qty

Description

D

ABBEMBL.Y,P,B. INTEI1CDNNECT

Mfr
Code

Mfr Part Number

0

E
I.
2

7

2

I

See introduction to this section for ordering information
*Indicates factory selected value

H~1l0-06117
12~i1"-64BO

1 ;:~::H-64130

6-19

Replaceable Parts-Model 64110A

Table 6-8. A2 Motherboard Replaceable Parts List
Reference
Designation

A2

HP Part
Number

C

D

Qty

Description

64110-66501

7

BOARD A!3BEMBl..Y·"MOTHERBIlARD '~I

0180-0094

4

CAPACITOR-FXD 10 OlJF+75-1 0% 25VDC AI..

A2HBO

1400-0249

A~;.~Jl

1 ;:.~~51-:'30r~4

A2.T2

12:::i1-'5702

A~:~J3

1;.~51-·5702

CABI..E TIF.:

1
7

,062·.. , 6''.5''·DIA

Mfr
Code

284130

Mfr Part Number

64110-66501

30Dl07G025l)1)2
PLTI M·.. 8

,091-WD NYl ..

CONNECTOR 26-PIN M RECTANGUL.AR
CIlNNECTIJR'''PC El)"~E 43 .... CIlNT IROW 2-'ROWB
CONNECTOR-PC EDGE 4:l·-CllNT IROW 2·-RClW13
CONNECTOR-'PC EDGE 4~~-CONT IROW 2 .... ROWS
CONNECTOR-PC EDGE 4:1-·CONT IROW 2'-ROIll8

cB4flO

1~!~t'-3024

;'.1l4BO

1~.~~.H-570;=

CONNECTIJR"'PC EDGE
CONNECTOR-PC EDGE
CONNr::cnlR-·pc EDGE
CONNECTOR 3-PIN M

;"3480

1;~~jl-5702

2a480

12~jl'-5702

;'.1:1480

'l2~jl'-5702

2f:14<10

12~:i1-5702

A2J4

1251-5702

A~:~J5

12~)1-~)'7()2

A2J6
A;'!J7
A2JIl

12!::H-'~:;702
12~)1-~j702

A~:?'Jl~~

1251-4:32;.~

A2.Ll

9140-0254

3

INDIJCTOR 4301lH '10%

M!MPI

O~)90MMO~;19

THREADED INSERT--NUT 4 ..·40 ,062-IN'-U; BTL
CDNNECTIJR·"4 PIN
POLARIZING KI;:Y-PDST CONN

284130

0590'-0519

213480
284f:IO

12~51'-71 1~~

RESISTOR 196 1% ,I25W F TC-0<-100
RESISTOR 130 1% ,125W F TC-0+-l00
RE1HHTOR 2.21< ::)/! .25W Fe TC::::--40 Il/+71l 0

~~4546
;:~4ei46

C4-1/8-TO-196R-F
C4"'1/8--T 0 --I :l1·-F

TERMINAL
TE.RMINAL
TERMINAL
TERMINAL
TERMINAL

PCB

000(10
00000
00 (I 00
00000
00 (I (10

OIlllER E'Y DE:~;CRIPTHIN
O[mER BY DEflCRIPTHIN
DRllER BY DESCRIPTION
QRl)[,R BY DEflCIHPTlfJN

TERMINAL TEST POINT PCB
TERMINAL TEST POINT PCB

00000
00 (I (10

ORDER IlY DEflCRIPTIDN
OlmER BY D[SCIHPTICIN

NETWORK .... REB 10'''!HP MI.H_ n: . VALUE

;!1348 0

12~::;1~~571l2

A2MP2

12~j]-7112

7
3

A::~MP3

1~~51-·~j5cj)5

2

Ai?Rl
A;:?R2

06'18-3440
0'757"0404
0683-·2225

7

A2R3

A;:!TPl
A~~'lP2

A;:!TP3

O~S60-01~j3~

0360 ..·05:35

o:~bO-~ O!.:i:35

Ac~TP4

0360-'0~i35

A::!TP5

0;':')60-· 0 ~5:3~j

A2TP6

0360-0~j~,~5

A::~TP7

0360-0~:j~5~j

A2UI
A;.:.~U2

11l10-021lB
HII 0-0~~88

A:3L13

Ill'! 0 ..·0288

6-20

3
:~

o

o
o
o
o

6
6
6

7

TEST
TEST
TEST
TEST
TEBT

43"'CONT IRIlW 2-·ROWfi
43-CONT/RDW 2-ROW9
4:3"·GDNT/RIlW 2"'ROWil
POST TYPE

POINT
PDINT
POINT
POINT
POINT

28480

1;.~~jl-5702

:?:t.l480

1 ~?~51 MM4:~~~;~

,6DX1, 61..G

PCB
PCE'

PCB
PCIl

NETWOflK·-RES 10--SH' MlJl.TI ..·VAL.UF
NETWORK-RES 10'''SIP MULTI-VALUE

120;1 -5702

;;.~B480

('/140-0254

n11 ~~ 1

'1251 .... 559::i

Cf.lt~22:=:j

m!liER IlY DESCRIPTION

;:.~a480

1131 0-' 0 'J.B8
1f:11 0-'028f:1

;:.!B480

11l10-02BIl

See introduction to this section for ordering information
*Indicates factory selected value

Replaceable Parts-Model 64110A

Table 6-9. A3 CPUIIO Board Replaceable Parts List
Reference
Designation

HP Part
Number

c Qty

A;3

64110-,6650"

;3

A;~Cl

0'160-'2055
01bO·..·2055
0160 .... ;~055

9

A;3C4

0160"'20~,:;

9

A~IC5

0160-2055

9

A3C2
A~IC3

9
9

A3C6

o16 O'-'20~:/~)

,~

A~IC7

01r.IO-·20:::j~j

9

A3CB

OI60-20~,5

9

A~IC9

0160-2.055

9

A;3Clll

0160--£~O~j5

9

A~lCI

0160-~~O~55

A~~C15

0"160·-2055
O"l60-20l:i5
01611-205:;
01 BO-0228

A:ICI6

o160-'~!O5~)

9

A~lCI7

o 160·.. ~11155

9

A:lCI8

01bO--,!O~;5

9

A~'~C19

0160 .... 2!l~'j5

9
9

'1
A:IG'12
A:ICl;1
A:lCl4

,~

9

b

o1f.)O·-·;"~O~j5

A~lC21

oll")O-;"~(}~55

A.~Ct.~2

()160--20~.:i5

A~~C2~\

0160-20f.i5

'I
9

A:3C24

IlH10-11197
0160-2055

9

0160-2055
() 160,,-2055

9

A3C26
A~IC2·1

A:\C2B
A3C29
A:3C31l
A~~C31
A3C;3~~

A::lC33
A3C;34
A~3C35

A:3C;36
A3C37
A:\C31l
A:lG39
A;3C40
A:lC41
A~5C42

A;'lC43
A:lC44
A;3C45
A:lC46
A:lC47
A3C4El
A;3C49
1'1:11:511

O"l60-~~ilr5~~

0160-2055
0160-~!O:::;5

,~

9
9
9

0160-'20~55

9
9
6
1

o160-'20~)5

01130,,-011 b
01BO-O:?28

b

()160-20~;~5

,~

0160,,-2055

9
9
9

ot bO-·2055
o'l60-20~55
o16()-21l~f5
o1 tIO-205~j

'I
9

0160-21155

'I

0160--20~:J::=j

9
9
5

o160-20!7i5
o 160-;~308
11180--0309
0140-0;~00

0140--02011
0140·-0;,00

4
0
0
0

0160-"::'~O:::j5

,~

1 ~~.~:;8-() 1 B2
1 ~?'~513- 0 1 B;':!
"l c~.l)8- 0 18~~
1 :~~~'58- 0 1 B:=

7
7
7
2
7

A:lEll

1 (~58-"O

7

A~IH7B

A~IEI

A;3E2
A:IE3
A:IE4
A:IEl0

1~~~5B--Ol~),3

18~:!

3

0

0"180- 0 ~~;.~8

1

3

~j

CPU/I. D.

31150-0'7'11

6

1

A;IH86

~~;~60--1I1109

;3

7

2;:~OO-O"l4;3

0

A3H92

9151-0013

1
1

A~3J5

1;"?~;1-4:5813

9

A~ILI

9140-011,'

A;'MPI
A3MP2
A3MP;1
A~IMP4

1205-.. 03;38
o '~1325"-6'790 n
1480-,0116
14130-·0116

A~,MP5

~.:;{l40·-60617

A~IMP6

5040-6069
1;,00-0844

'7

1;~OO-O114'7

0

100VDC
IOOVDe
1 !)IIVOC
IOIIVDC
100VDC

CER
C[R
CF.R
CER
CER

CAF' ACI Tor~ ·-FXD .01lJF +BO--20X, 10llVDC CCR
GAPACITDR ...·FXD .011.JF +BO''';!II% 100VDC CER
CAPAC1Tor~ '-Fxn .01l1F +80-"20% 10llVDC CER
CAPAC '[ TI1R .... FXD .0111F ... aO····20% 10llVDC GER
CAPACITOR-FXD 2~~l.IF+-l OX 1 ~:iVDC TA
",[:1 o .... ;.! 11% 100VDC
+r~O"-20% 100VDC
"'El 0 .... 2 O'Y. 10llVDC
+80"-~~O% 10llVDC
·t·130 .... ~~O% 10llVDC

CAPACITOR ... ·FXD
CAPAc:nOR-FXD
CAPACITOR .... FXD
CAPACITClR·-Fxn
CAPACITDR ..·FXD

.OIUF
.OWF
.0111F
.0lUF
.011.JF

CAPACITOR-FXD
CAPACHIlR-.. FXD
CAPAcnOR-FXD
CAPACITDR·.. ·FXD
CAPACITOR-FXD

.01l1F +80-·20X, 100VDC CU~
,0l1JF +80-'20% IOOVDC CE.R
.01L1F +80,-20% 100VOC CFR
2.2lJF+-IO% ;:!OVl)C TA
.0HlF +80-20% 100Vl)G CER

CAPACITDR .... FXD
CAPAC nOR -FXD
CAP ACHOR ",FXD
CAPACITOR-·FXD
CAPACITDR-·FXD

.0lUF
.OIIJF
.lllUF
.011JF
.011.1[-"

CER
CEil
CE'R
CFll
CER

+BO"'~~O% lOOVDC CER
+80'-20% IOOVDC CE:R
+81l--,10% 10 OVDC CER
;·80 '-r~o% 100Vl)C CER
+80 .... ~~OA: 100VDC CER

Mfr Part Number

0-66~;07

21'l41'l0

641 '1

2[:1400
;"1480
2.H480

0160'-205~i

(!8480
2~14[:10

0160-20~,5

0·160 .... 20~,5
o l60-2055
0160···2055

;~114BO

O"l60-205~5

2H4f:10
;?O480

01£,0--2055
0'1 bO-20!:"i5

~1H4BO

0160·-20sei

O-205!:i

151lD6f:15X903~m2

() 15fJ~:.~

CE.R
CER
CER

0
2B4f.lO
"13480

0160-20::;;5

C[[~

CER

c~B480
~!\34aO

o16()-20~55

CAPACIHJR-FXD
CAPACITDR ..·FXD
CAPACITl1R-FXD
CAPACITIJR· .. FXD
CAPACITOR-FXD

.0IUF +80-'20% 100VDC CER
.OII.JF +f)0"'20% 10llVDC CER
.011.lF +BO'-20% 100VDC CER
.01l.JF +00-'20% HOVDC CER
36PF +-'5% 300VI)C MICA

~~f:l480

11160-20~,5

~~848 0
2H4f:l0
211480
2(J48 II

11160-2055
0160--2055
II 1 100-2055
0160 ...·230El

CAPACITIJR .... FXD
CAl' AC I TClIl-FXD
CAPACITOR ..·FXD
CAPAcnOR'-F'XD
CAPACITDR .... FX]l

4,7IJF+ ...·20% ll1VDC TA
390PF +-5% 31111VOC MICA
390PF '.-5% :\OOVDC MICA
3'/OPF +R-5'Y.. 3110VDC MICA
.O'lI.JF .·90-·211, 100V!)C CER

5b2BIf

1<,OD475X0010A;.?'
DM15F391JII3110WVICR
DM15F391J0300WVICR
DMl5F391J0300WV1CR
0160 ...·2055

7~~ 1 ~56

72136
7;'~136

,!84f:l0
~?H480

01 i:)OM-2055
O160'-20~j5

CONNECTOR '-R .I<
CONNECTOR ..·R I..
CONNECTf.IR-·R
P
PROGRAM HEADER
CONNECHlIl ..-R .I< P

MALE PLUG
MALE PU.JG
MALE PI..lJG
MALE PI...l.lG

;"tI480
2H480
;,!1l4BO
211480

CONNECTDR .... R /, P

MALE PLUG

213480

12t;8-0 113;.?

'"

A~\HB'l

A:3MP7
A:lMPfJ

A13BEMBLY··~

CAPACITOR-FXO .OlllF +80'-20% 100Vl)C CER
CAPACITDR-·FXD .0IUF +80--20% 10llVDC CER
CAPACIHIR-FXD .0IUF +BO--20% 100VDe: e:ER
CAPACTTDR-"FXD • 0 1lJF +1'10·_·211% lOOVDC CER
CAPACITOR-FXO .01L1F +1'10,-20% 100VDC CER
CAPACITIlR--FXD ,1I1l.JF H10"-20%
CAPACITOR-FXD .01L1!" +1'10-,20%
CAPACITOR ..··FXD ,01l.JF +130-,211%
CAPACITor~'-FXD .0'lllF HIO-20%
CAPACHDR ..·FXD .1I1lJF +130-,211%

9

A:3C20

A:~C2~:j

BOARD
40

Mfr
Code

Description

0

1 ;':?~:;H-O 182
1 ~?'~j8-0 1 B;~
1 ;.?'~:jn-o 18c.~
1258-0153
12~~if.t ..-0

t Be?

INSlll.ATOR-X6TR NYLON
NllT·+IEX·"W/LKWR 4 ..-40-.. THD ,1I94 ...·1N-THI(
SCREW .... MAGH 4"·40 ,3'7~j·- IN"-1.. G PAN'-fm'-PDZI
FJNf_ WJREc
CONNECTOR :I ..·PJ.N M POST rYPE

284tlO
00000
00000

3050 .... 0791
ORDER BY DESCRIPTIIlN
111mER BY DESCIHPTI!1N

,!1l4BO

1;"~51-4388

2

INDLICTOR RF-CH·-MI...D 4.'711H 10%

28480

9140'-0'112

4

HEAT !3INK

;.!04BO
284E10
;! IJ.413 0
21)4BO
;'.!848 0

1205-0;,3B
0(?8?5-'6790a
1400'-0116
1400,,-0116

8
13
8
4

SGL PL.STC-.. PWR-.. CS

GASKET-BPC
~~

PIN·"Gr~V

,;:.~5 .... T.

N·.. LG STL

2

• 062 ..-IN "IHA
P IN'-GRV .062·-IN ..-\)lA
EXTRACTOR-IJI .. UE

2
1

EXTIlACTllR'-BLUI"
RETA:\NH ..-SlIFJSTRATE srEEL~ NICKEL PLATE
BOCI(ET-SBSTR 4(l ..-C(lNT CEllAMIC nIP-SLDR

4

,2.5-IN"-LG STL

284~'1

0
2134811

20480

See introduction to this section for ordering information
*Indicates factory selected value

~j040-6069

5040,-6069
1 ;!O 0-0044
1;'OO-OB47

6-21

Replaceable Parts-Model 64110A

Table 6-9. A3 CPUIIO Board Replaceable Parts List (Cont'd)
Reference
Designation

HP Part
Number

C
D

Qty

::;;

A31~

"I
A:3R;;':

O'757"~()290

A::IR:J

0n';7-·0;'1l0
06913··-31 ~:;It

3

07:i7"-O~.~(tO

A3R4
A:IR5

A:,H6
1\::lR7

A:lRD
A3R9
A31~ 10
A31H 1
A:ll<1 ;.>
A::"~ 1:\

Description

Mfr Part Number

I~EGISTDR

6,t(~1(

5

RESISTI)R
RESISTOR
RESIST[)R
RESISTOR

6,191<
1K 1%
26,1K
6,'19K

5

RESI[ITOR 221 1% ,125W F TC=O+-lOO

£~.il::'j46

0698-343;~

7

RESISTOR 26,1 1% .125W F TC=0+-100

031'101'1

O'7~:;'7""O;?,OO

RES·[S·TOR 5.62K 1% ,125W F 1·C=0+-100

PME55·-1/8-TO-·26Rl-F

'7

;.:~4546

1:4--I/D .... T 1I ...·~.'i6;"I ..··F

RESISTOR 3B3 1% .12SW F TC-O~-ll1l1
RESISTOR 11< 1% .125W F ,·C=Ot·"·100
RESISTOR 1K 1% ,125W F TC=0+-100

;.?4~:r46

n'757'-'O:~90

;.:.~l

••• J

0 0-3{~1 ~~

o'757 .., 04~?2
(J7~.'.i7"'·()2Elr.?

o698~<;4:·5;.~

1%

.1;:~~jW

Mfr
Code

F TC::::O+··M100

1% ,'125W r TC~O+--100
,125W F TC=Ot·-100
1% .125W F 1C=0+-100
1% .125W F TC::::0+--100

1 '1'/ll 1

MF4CI/B-TII-6191-F

19'1111

MF4C1/8-TII-6191-F

;:')4::;;46
;.? 4::=; 46
"1 ?'70"1

C4····1 18'-I U·,·1 U01 ..,1'"

RESISTOR-IRMR 200 lliX C TOP"'ADJ I-TRN

::?f:l413 0

RESISTOR 909 '1% ,125W F TC=O+-100

:?4~.:;46

;,11111"';521 ;,!
C4 .... l/8 .... TII ... 'I(l'III .. ·F
C4 ... 1/B·-TU ",~21R+

RESl~;T(W 26,1 11., ,1~~~5W F TC::~O+····"lOO
RESIST()R 5,621< 1% .125W F TC=O~·-·100

C4·1 18 . -TO-·261 :'!F
MF4C1/B-TO·-6191-F

A3r<14

()7~.:;'7··HO~?BO

A:lR l~j

O'?~'=;7-·0;:~HO

7
7
3
:3
3

A:':m16

1),!~';'7 ....

I);'BI)

::1

RESISTOR 1K 1% .125W r TC=O+-"100

;.:.~4:'.:;46

A:JRI7
A:,\RII3
A::lR19

C4 .. 1/8-TII-·1001"F

0'7~::i7'''O;.:BO

3

07:::;7 .... 044~1

C4 ..

1)698 .... 3446
I) '?~:.:i'7···· 0 44;.:

3
<;>

RESIs·rOR 1K 1% ,125W F TC=O·~-100
RESISTOR 20K 1% .125W F TC=Oi·-l00
RESISTOR 383 1% ,125W F TC=O+-100
RESI~lTr)R 10K 1% .125W F TC=O+-lOO

::~.4~::146

(,

:llOl-,~Lln

8

SWITCH·-PB SPDT MOM ,02A 20VAC

::>.1]4011

TERMINAL
TERMINAL
'·ERMINAL
TERMINAL

Pf:B
PCB
PCB
PCB
POINT PCB

110000
011 0 0 0
111101111

TERMINAL TEST POINT PCB
TERMINAL TEST POINT PCB
TERMINAL TEST POINl pc:e
lE~MINAL ITST POINT PCB
TERMINAL TESI POINT PCB

0011110
1111111111
o II II II 0

ORI)ER BY DESCRIp·fION

l·E.RMINAL '·[61 PO:[NT
TERMINAL TEST POINT
TEHMINAL TEST POINT
TERMINAL TEST POINT
TERMINAL TEST POINT

PCB
PCB

II 110 1111
OOO!l 0

PCB

PCB

DilOIiO
o II II II II

PCB

01101111

DI1DER
ORDER
ORDER
ornER
ORDER

TERMINAL TEST POINT PCB
TFRM·[NAL I·EST POINT PCB

11011110

A:~~I~

20

()7~.';7M··O~:~O

0

Ob98·H·~~446

A:lTPI

0360····0~i:·~~:i

A3TP;.~

()]60-·0~:i3~:i

A,:n\' 4

1):360H··()~53::i

A::lTP~';

OJ60-·0~=:;]~3

A:HP6

I) ;\6 0 .. _1) ~.;.:\~:;

1;::lTP7

O~560-0~j3~:;

A:lTPEI

0360H··O::-i3~3

A:lTP?

OJ60~·O~:i3~':j

AT1Plil
A:lTPll

O::l60 .... 0;;;I',,;

A3'TP'12

O~360-·0535

0360H"053~7i

A:lTP 13

{L360-0~5]~:j

A3TP 1 ~:.'j

0360MHO~i3~5

A:lTPI6
A::HP17

0::560-·0~:i3~i

A::lTPI13

TEST
TEST
lEs·r
TEST
TERMINAL TEST

0360-0~.)3:=:;

11360 ..-05:3";

A:lIPI9

n~36 0 M.· 0 ~:;:·5:=:j

tl3U"l
A3U~~

1 B ;.:~ 0 -;.:~ 0 ~.:jH
t01 O·.. ·()~519

IdU3

lD"10-·{)~::;lrJ

A?U4
,;::OU6

"\ U;:.~O-·~?'O~.)B
1820-20:=:;8
10<'0-,1 ;"4:J

A~'~U'7

tB?O-·11')7

'I

Ie r';AH:

9
4

Ie <:."?l..GOUN RAM

A~~1I5

IC

A:::;U8

1B:,0-11'n

A:'~U9

·.lB"16""1 {l(/;.:!
1 H;.?,O-19~:l9

'7

A~~Ul1

"1 f:l? 0 .- ;.;~ 0 ;.:.~ 4

:l

A::1Ul?
(UtiLI
A::lUI4

In;~)O-·t;:~"l6

3

"1U?O····;.?O?4

:l

r-l~~Ut~5

1010 .. ··0;:>.'76
1 n;.:.~ 0 "M;.? 0 :':.~4

t:l~!)1J16

10to-'O,>'76

A:;U17

1 B;.:~O-··069:3

1'1

A:lUHI

1B(~O·"·119?

A::~l.J·J

9

1 o:"o--,'O:';FI

A3U20
A3U;.:.~'1

1 B;:?O-·t ;:?11
1 n·1 0···· 0:276

1
:1
8

A3U22.

1 n ;.:~ 0 -. ;.:.~ () ;:~ 4

A:II.I;.~3

"1

A3U24

1 B;'~0-1 '730

n~::'O-"1

A3U~:~:::;

"1

1a:.:?O-"}::?Bl

A:':HJ;?'7
A:::;U2B

10:':11-·1 '11 '7

1

"1U;:~O-·'1;.?16

3

A:'~U:~9

::)[16"1-<"3011

4

A::lU30

llJ;.'.0-1;:~on

1,:lU31

1131 0-- 02'/6

3

H;:~OH··;':.~O;:.~4

1B;.~O-1;:?1;~~

A:lU3::l

1 0:"0-111"
1 U;'~0"'1144

A:'~U3~j

·lB;:.~O····12~05

A::OU36

"1 AA6-·~:;0 04

6-22

TTl... r.. !'; NAN]) QUAD ;:""·11,1·>

"

IC CNTR TTL LS BIN DUAL 4-BIT
IT DH\.':~ Tn.. L!:; LINE DRVR UCTL
Ie DCDR TTL LS 3"TO-8-LINE 3-INP
Ie nliVH TTl.. l..G 1... 1hl[ DRVR Dell..

NETWORK-RES 10-SIP1,5K Ol1M X 9
IC DRVR TTL LS LINE DRVR m:1L
NETWURK-RES 10-SIP1.5K OHM X 9

Ie FI.. TTL S D·TYPE PDS-TDGE~rRIG
IC INV TTL LS HI..X I-INP
IC MIse rlL SQUAD
Ie GATE TTL LS EXGL-OR QUAD 2-INP
NETWORK-·RFS 10-SlPl.5K l)HM X 9
Ie DRVR TTL . LS LINE DRVR OC·fL
r.e I.W~~ TTL l..B 1.. 1NE Dr~\/R nelL
IC 1..1.. TTL LS D"TYPE POS-E~GE-TRIG COM
IC m~UR ITL LS LINE DRUR FleTl
Ie DCDA TTL LS 2-TO-4-LINL DUAL 2-INP

917

A::jU3~::'

·1·\ ···~;IP MULTI·· V(.:"ll .. UE
11-SIP MLILTI-VA1_UF
SQUAD
SQUAD
LS AND TPL 3 INP

Ie GATI.. TTL La NAND QUAD 2·1N?

7

A3U26

A3U34

MIse TTL SQUAD

NE·l·I..JD\:~l<···!~F!:)

NETWORK·-RES
IC MIse lTL
Ie-MIse TTL
IC GATE TTL

A::lUII\

PO·[NT
POINT
POINT
POINT

9
13
6
II

o

[C BFR 11·L LS LINE DRVR OC·l~.
Ie Deml TTL LS 3-TO-8-LINL 3-INP
HYBRID-BPI::
IC GATE TTL LS OR QUAD 2··INP
NE·T!...,JD1~K-··I~En "10 nIP1 ,~.'!!{ DJ·1M X 11

Ie FF TTL LS J"K NFG-FDGE-TRIG
IC FE rTL LS D· TYPE PDS'EDGE-TRIG
IC GATE TTL L8 HEIR QUAD 2 INP
Ie CA1·F TTL LS AND DlJAL 4-INP
IC-PHI CHIP

O:,I'I"U

PMFS5-t/B-TO-26R1-F

;~~4~j4f:)

1:4-1/10TO-5621-F
C4·1/8-·TO ...63

MC3441'lAL
BN'I4L.Sf:)6N

01

o1 ;:~95
I)

1121

01?9~:i

;? 1 () At ~:; ;.:.~

() 1 ?9~:i
{} t ;.:~Sl:i

o1 ;.:?9~j

SN'74L.S;::)44N
BN?4I...S;?4 ON
SN'741 S~:.~73N
SN'?41... S244N

(}"1 ;:~9~5

BN'?4t.S 1 ~5~rN

01 ;.?9:i

DESCRIPTION
DE:SCRIPTION
DESCRIPTION

ORnER BY DESCRIP1·ION
ORDER BY DESCRIPTION

?U4!l1l
'2H4DO

DE!',crHPTIIlN
DfSCRIPTION

GN'l4I.S?40N

0"1 ;:).9:':;

SN'74L..S 130N

;'1'14011
01295

~.:i()f:d

01121

:.:.:1 OAt ~:j;:!.

{} t ;:.~9~;
111 ;::9~5

SN'J41..S112AN
SN'74LS'74AN
f:lN'741...S0:.?N

o1 ?9~':'j

·-3011

SN'?4\.,S3?N

n·1 '~9~:.;

nN74U:~;:~1

2841'111

IAAI"6004

See introduction to this section for ordering information
*Indicates factory selected value

N

Replaceable Parts-Model 641l0A

Table 6-9. A3 CPU/IO Board Replaceable Parts List (Cont'd)
Reference
Designation

HP Part
Number

c Qty

A31J37
A3U38
A3U39
A:5U40
A31J41

1820-1208
1820-·1195
1810-0276
H120-22tl6
1820-1112

:1

A3U42
A3U43
A:3U44
A3U45
A:5U46
A3U47
113U48
113U49
113U50
113U51
A3U52
A3U53
A3U54
A3U55
A3U56
A;5U57
A3U58
A:3U59

lBl0--0276
1820-2024
18"10-0280
1820-2024
1810-0276

2
3
B
3
2

A:~UbO

A;3U61
A3lJb2
A3U63
A:IU64

7
2

1

3

2

8

1B20-2206

:3

64110·-10006
64110-1111107

0
I
9

64110-1000~i

64110-·10004
1810-02BO

Il

11:120-2024

3

1820-1730

6
8
8

lB;~0-1112

18,!0-1112
lB20-0693
lBi20-12Bl
1820-1243
lB20-1322
11320-1423
1820-1212
Hl20-19B9
1820-1112

:?

4

B

8
2
6
2
4
9
7
8

1
1

A3U65
A;llJ66
A:3U67
A3U6B
A;3U69

1820-0693
lBl0-027B
1820-1204
11320-1917

B
4
2
9
1

A3U70
113U71
A3U72
A:5U73
A3U74

lB'!0-1917
11320-2102
1820-2102
1820-1240
1820--1917

1
8
8
3
1

A;5U75
A3U76
A:5U77
A31178
A3U79

1820-1072

1
1

18;~0-128B

9
1
3
6
9

A3VRI

IB,!6-0393

A3XEl
A3XE2

125t-1556
1251-·1556
1251-1556
1251-1556

A~IXE3

A3XE10

lB;.~0-12Bl

18}~0-053'1

1820-2024
1820-1425

Description

D

IC GAlE TTl. l..B OR qUAD 2··INP
IC FF TTL lS D-··TYPE POS-EDGE-TRIG COM
NETWDRK····RES 1 O-·SIP 1 .5K IlHH X 9
IC HISC TTL LS
IC FF HL LS D-TYI'E PDS·_·EDI;E-·l RIG
NETWllRK-RES 10·-SlPl.51( OI-1M X 9
IC DRVR TTL I..s LINE DRVR OCll
NETWORK-RES 10-SlPl0.0K OHM X 9
IC DRVR TTL LS LINE DRVR DCll.
NETWORK-RES 10-SIP1.5K OHH X 9
IC HISC TTL l.t=l
ROM 1
ROM 3
ROil 2
ROil 0
NETWORK-·RES 1 O··-SIPI O. OK OHM X 9
IC DRVR TTL LS LINE DRVR oeTL
IC FF TTL l.S D-··TYf'E P 06-EI)I;E --TR IG CDM
IC FF TTl.. LS D·-TYPE POS··-EDGE·-TR IG
IC FF TTL LS D,··TYPE POS--EDr;E-TRIG
IC FF TTL S D-TYPE POS-EDGE-TR IG
IC DCDR ITL L.S 2-·TO-4····LINE DUAL 2-·INP
IC - GATE: TTl. LS ANI> TPL. 3····INP
IC GATE TTL B NOR -I~UAD 2-··INP
IC MV TTL. L.S MtlNflSTBl. RETRIG DUAL
IC FF TTL LS J-K NEG-·EDGE-··TR IG
IC CNTR TTL LS BIN DUAl.. 4·-BIT
IC FF TTL LS D····TYPE PDS-·E])GE-TRIG

Mfr
Code
11129[;
01295
111121

012'J5
01295
01121
01295
01121
01295
01121
01295

01121
01295
01295
o 1;~95
01295
o 1
IC DC DR TTL LS 2-TO-4-LINE DUAL 2··-IN!"
IC GATE HL l.S NAND DUAL 4···INP
IC BFR TTL LS LINE DRVR CICTL

01295
01121

IC
IC
IC
IC
IC

BFR TTL LS
L.CH TTL l.S
LCH TTL L.S
DCDR TTL S
BFR TTL 1..8

01295

1
1

IC
IC
IC
IC
IC

DCDR TTL 8 2·-Tll-4--L.INE nUAl_ 2-INP
BFR TTL NAND QUAD 2-·1NP
DRVR TTL LS LINE DRVR DClL.
SCHMITT-TRIG TTL LS NAND l~lJAD 2,-tNP
DRVR TTL CL.OCK DRVR TTl_·-T[l-MOS 1····IN?

7

1

IC V RGL1R TO-220

7
7
7

4

CONNECTOR-SGL
CONNECTOR-SGL
CONNEC10R--SGL.
CDNNECTOR-SGL

1
1

2
1

7

LINE I>RVR DeTL
D-TYPE OCT I..
D--TYPE [leTL.
3··-TfJ--8--LINE 3··-INP
LINE DRVR llCTl

CONT
CONT
CONT
CONT

01295
01295
01295

0129~;

0129~i

01295
111295

o1 ~.~95
01 29~-;
01295
01295
04713

,~7014

SKT
SKT
SKT
SKT

.018·-IN·-Bse·-IlZ
.0113-IN·-BSC-··SZ
.0IB·_·IN-BSC-SZ
.01B--IN--B8C--8Z

28480
284BO
284BO
28480

Mfr Part Number
BN74LS:52N
SN'7 4LS 175N
210A152
SN·74I..S640N
SN74LS74AN
210A152

SN74LS244N
210A103

SN74lS244N
210A152
SN74LS640N
64110-10018
64110-10018
64110-10018
104110-10018
21 OAI 0:1
SN'74LS244N
SN74LS273N
SN74L.S74AN
SN"14L.S74AN
SN74874N
SN74LSB9N
SN74l..S15N
SN74S0~?N

SN74LS123N
BN74LS112AN
741..S393PC:
SN74LS74AN
SN"14S74N
210A:I:12
SN74l..S139N
SN74LS211N
SN·74l..S240N
SN74LS240N
SN74I..S373N
SN74LS373N
SN74S138N
SN"14LS240N
SN'74St39N
SN7437N
SN74L.S244N
SN74LSI3,~N

MIIH0026CL

L.H317T
12~H-15::i6

1 '?51-1 ~j56
1251-1556
1251-1556

A3XE11

1251-·1551>

7

CONNECTOR-SGL CONT SKT .018-IN--BSC-5Z

28490

1251-1556

A3XUl
A3XU2
A3XU3
A3XU4
A3XU5
A3XU10
A3XlJ19
A:5XU22
A3X1l23
A;5XU24
A3XU25

1200·-0607
1200-0612
1200-0612
1200-0607
1200-0607
1200-0638
1200-0607
1200-0639
1200-06:19
1200·_·0639
1200-01039

0
7

SOCKET-IC 16-CfJNl DIP
Sl1t:KET-tC 22-·CDNT DIP
SOCKET-Il~ 22-CONT DIP
SOCKET-IC 16-·CDNT DIP
SOCKET·-IC 16-CONT DIP
SOCKET-IC 14--CONT DIP
SOCKET-IC 16·'·CONT DIP
SllCKET-IC 20-CONT DIP
SOCKET-IC 20-Cl1NT DIP
SOCKET-IC 20-CDNT DIP
SOCKET-IC 20-·eONT DIP

DIP-SLDR
DIP-·SLDR
DIP-SI..DR
DIP--i3l.. DR
DIP-··SI..DR
DIP-SloDR
DIP··SL.DR
DIP-Sl.DR
DIP-·SLDR
DIP--SLDR
Dlp····SLDR

284BO
'.!B4BO
28480
'!.134BO
284BO
284BO
28480
28480
28480
2B4BO
284BO

1200·-01>07
1:100-0612
1200··-0612
1200-01>07
1200-01>07
1200-0638
1200-0607
1200-0639
1200-0639
1200-0639
1200-0639

A3XU40
A3XU43
A3XU47
A3XU48

1200-0639
1200-0639
1200-0639
1200-06:59
1200-0541

8
8
8
8
1

SOCKET-IC 20-CDNT DIP
SOCKET-·IC 20--Cl1NT DIP
SOCKET-Il~ 20-CONT DIP
SOCKET-·IC 20-··CONT DIP
SOCKET-IC 24-CONT DIP

DIP-SLDR
DIP-·SL.DR
DIP-SLDR
DIP-··8LDR
DIP-SL.DR

28480
284BO
2B4BO
28480
28480

1200-0639
1200-0639
1200·-0639
1 '!.O 0-06:59
1200--0541

A3XU49
A3XU50
A3XLJ51
A:5XU53
A3XlJ54

1200-0541
1200-054·1
1200-0541
1200-0639
1200-06:59

1
1
1
8
8

Sl1CKET-IC
SOCKET-IC
SOCKET-·IC
SOCKET-IC
SOCKET-·IC

DIP-BLDR
DIP--SLDR
DIP-SLDR
DIP--Sl.DR
lHP DIP-SL.l)R

A:5XU61
A3XU74

1200-0607
1200-0639

0
8

SllC:KEr-iC 16-CONT DJP DIP--SLDR
8llCKET-·IC 20··-CDNT DIP DIP-·BL.DR

A~iXU45

2

7
0
0
7
0
8
8
8
8

1
11

4

24-··CONT
24-CONT
24-··CONT
20-CONT
20·-·eONT

DIP
DIP
DIP
DIP

2B490

1,~00-0541

2~1480

2B480
2B4BO
119480

1200-0541
1200-0541
1?'.00-0639
1200-06:39

2B4BO
29480

l<'llO-0607
1200-0639

See introduction to this section for ordering information
*Indicates factory selected value

6-23

Replaceable Parts-Model 64110A

Table 6-10. A4 Keyboard Replaceable Parts List

HP Part
Number

C
D

A4

64110··6650;.'

13

MCI
A4C2

o 1611···205!:;

'I
'J
4

Reference
Designation

0160-20 155
01tlO-·0:109

A4C3

A4C4

11160-·21155

o1 (:lO-~~O ~S5

A4C5

Me6
A4H70

1251-·5649

A4L1

9100-2::?4'7

A4MPI
A4MP2
A4MP3
A4MP4
A4MP5

O~~71""~?'3n~~

A4MPII
A4MP 12
A4MPL3
A4MP 14
A4MP I ~l
A4MPI6
A4MPI7
A4MP18
A4MPI9
A4MP20

4

9
9

~-5Z

2

CER

CER

;'!I'I 41'1 0
?El480
~i6~.11:19

ITR
crR

~:?B4!:IO

1101100

ORDER

;;;1l4DII

300VDC MICA

SCREW···TPG 2-32 .25-IN-LG PAN-HD-SLT

0160 .... 2(J~i5

0160-20:'.';5
1 ~';(ID475X II 0 1 OA?
()'160 .... ;.:~05S
() 'l b(J"-20~:j::j

DM15F241J0300WVICR

CONNECTOR 20-'PIN M POST TYPE

13

Mfr Part Number

'?1341l0

CAPACITtlR···FXD ,0 11.1F +[10····,'0% 10 OVDe
CAPACITOR···FXl) ,I) II.)[ +80·";"0% llillVDC
CAPACITOR-FXD 4,7W'+-20% 10VDC TA
CAPACITDR··Fx.D ,I) 1 UF +130··20% 1 I) OVDC
CAPACITOR-FXD ,OII.lF +80-20% 100VDC
CAPACITOR-FX!) 240PF

06~~4-02.'70

A4Jl

A4MP6
A4MP7
A4MPB
A4MP9
A4MPIO

BIlARD AfifiEMBl..Y-·I1'1400

:::j

037'l·-2;:?17

;>

A4MP31
A4MP:12
A4MP:13
A4MP34

O:371-~~2~.~:3

o

0371-2,~0!)

8

O~~71 ~";':.~218

;5

0371·-22;' 0

7

A4MP35

0:571 ~~2225

.,

A4MP36
A4MP:W
A4MP38
A4MP39
A4MP40

0371·-2;;?,fl1

8

KEY CAP

o

28400
:>[14011
2841'10
:"1:1480

A4MP41
A4MP42
A4MP4:1
A4MP44
A4MP4ei
A4MP46
A4MP47
A4MP48
A4MP49
A4MP50
A4MP51
A4MPei2

"F:"
KEY CAP "R"
KEY CAP "T"
KEY CAP "Y"

284IJO

;'>D400

"U"

o;371·-;.?;.;~;.?~.'i
o;J71 ....
~?;;~;?1

1

7

KEY CAP "AT SIGN"

28480

0371-·;:~;;.~46

KEY CAP "LET BRACKET"
"DEL"
URDU. UP"

;.:'n4BO
213400
:·':B480

o;·571-;.?;.:.~30

I([:Y CAP
KEY CAP

KEY CAP "ARROW UP"

~~84B

n

O/)'71-?;:!~j4

1l;57'1~"2~2;50

'?

0371-2~?47

8

o;571-;':~2~j 0
0371-2::?54

;\

·7

?

O;·571-·2;.:'~09

O;371 .... ;:.2'l~i
{L:\71-;~);:.~·1('

(1;>71··-2;'4'7
03'11-2;;.~~':';O

O;~71'-2~251

4

KEY CAP "NEXT PAGE

;:'IHElO

0371-2~~55

8
4
4
7
'I

KEY CAP "CNTI..
KEY CAP "A"
KEY CAP "S"
KEY CAP "D"
KE.Y CAP "F"

2D4BO

01'7 t

:"fl480

03'J'1-£)(.~()l

;,8400
<':1:1480
284HO

03·71 .... ;.?;?19

;'·E14fJO
;.?U480
:"1'1400

o371-~?;.:.~ 0 '7
0371-2;:>01:1

;''>.fJ48II

O~3'11 .. -~~.;:j.'11

7

I(EY CAP "C;"
"H"
"J"
KEY CAP "K"
KEY CAP "L"

(L371~"~?,;?Ol

0371·-2;.?19
n~571·-;.:.~204

0371-2206
O;371"M~?,;~07

O:~71-2212

A4MP56

I) 371·-22.4B
11371-·2249

9

KEY CAP

03'11,-2229

"

KEY CAP "RT BRACKET"
KEY CAP "RETURN"
KEY CAP "ARll/t"

6-24

03'71·"-;~?;?O

0371-2;.:~46

A4MP5fj

A4MP::;i7

03'71 .... 2~!.O~i
() ;·~71-Z~;.:?1 B

1)371-,!21 "

A4MP54

A4MP58
A4MP5'1'
A4MP60

o;~ 7 '1 - ;.:.~ ~:? ;.:~ 3

KEY CAP "I"
KEY CAP "IJ"
KEY CAP "I'''

0371-2215

0371""22013
O·:571·.. ·2;.:~1 0
03'71'-2211

A4MP5~5

o::~'7'l"";.:.~;.?;.?7

"TAEI"

O:.lj71-·(.~22B

0371~"2209

11:371·-2;:'44

"11"

A4MP29
A4MP30

KEY CAP
KEY CAP

O]?1· .. ·2;~~:i?

o;'; '7 1... ;.:.~ ;.:.~ 4 ::,'i

0:171-·2263

o;'571-'~~264

I([Y CAP
I(EY CAP

"
o

fJ
9

"SEMIcnL

KEY CAP "COL & STAR

I.

O~:\?l-;:.);':?~.)l

'-2;;~~::;~i

D371-2;:.~04

0371 .... ;??06

0371·-(.~?1

0

:'1~480

o371-~:.;;.:~ l;?-

2841:10
;'.'1'1480
2841:10
:'.'84130

o::~i'71·"·;:~?48

2B4DO

0:~'71""2;:~.64

See introduction to this section for ordering information
*Indicates factory selected value

O;'~7'1'-2,,~49

o 3'71 .... 2;:?;.:~(y

o3'71-;.:.~;.?'b3

Replaceable Parts-Model 64110A

Table 6-10. A4 Keyboard Replaceable Parts List (Cont'd)
Reference
Designation

HP Part
Number

A4MPI>I
A4MP62
MMP6:3
A4MP64

0371··;!.2b4
0:371-2265
0:171 ..·2226

A4MP65

0:171-220:1

A4MP66

037 t

A4MP~17

(l371'-;':'~202

A4MP68
A4MP69
A4MP'70

0371-2214

0371-2t,~24

-·222~-.':

c Oty
9
0
3
1
6

2
1
1
1

CAP "ARIl/R"

KEY
KEY
KEY
KEY
KEY

CAP
CAP
CAP
CAP

"Z"
"X"

KEY
KEY
KEY
KEY
KEY

CAP
CAP
CAP
CAP
CAP

liN I.

CAP
CAP
CAP
CAP
CAP

'!.B4BO
284110
2134BO

"SHIFT"

O;·~'71·-2'?24

0371-2203

"V"

2B4EIO
211480
2B41l1l
'.!84BO
2B4130

0371·-2222
0371-2202
0:371·"2214
0;171-2213

'!.I;I481l
284HO
28480
2B41l0

0371-2;':'~3;3

1

A4MP71
A4MP72
A4MP?;!
A4MP74
A4MPn;

0:371-223;\
0371-2231
0:371-2265
037'1,-2253

2
0
0

6

{)~r71·-;':'~~~54

7

KEY
KEY
KEY
KEY
KEY

A4MP76
A4MP'77
A4MP7B
A4MP79

A4HP80

0371 ·-22f.i2
0371-14'?O
15;50-·0344
1530-0345
1460'-1841

5
1
1
2
6

KEY CAP "ROLL DOWN"
SPACE BAR
LINK
CRANK GUIDE
CRANI(

A4Rl

0757-0401

A4R2

on;'7-0~HE>

2

A4S76

3101·-;2409
310'1-2466

6
5

76
1

1["~ 0 -124 0

3

2

A4577
A41.11
A4U2
A4113
A4\)4
A41l5
A4\.16

A41l7
A4UB
A4119
A4UIO

lB(,~O-l240

3

1 '?06··0229

B

190b-O,!~~9

8

1906-0229

B

1906"·022"
1906-1l;:>;!.9
1 ("I'06-0;?:=9
18~?'O-'1217

tl
13
B
4

lB26-0BfJ

8
B
B
Il

MUll

11326·-11 t:!ll

A4U1~~

1906-0~.~~~9

A4U1:3
A4UI4

1906-'O~~29

19 06-0~~~?'9
19116"·1I2'!.9

8

A4tJ15

A4U16
MU17
A4U18
A4U'l9

19 06~·O2~~9
1 c1'06""02c~(1'
tfJ'10-02'75
1810-02'75

8

A4VRl
A4Wl

1902-300;:!

12

;:>

B

Il
I
1

~~

0371-2t.~~~b

t.~8480

O:~71-223'.~

1

0371-21.!64
0371-2265

,!,[l4BO

O~i"11-'.~213

2

Mfr Part Number

"C"

9
:;
9
13

~~

Mfr
Code

Description

0

"1:-1"

"M"
"COMMA"
"PERIllD"
IISl.ASH"

"B"HFT II
"PREV PAGE"
"ARROW DIlWN"

28480

0371'-22~52

03'7'1-223'1

o;?71-~.12b~)
O~~71·"·2t.?'53
O:~71-2;:'~54

28480

0;~71··'!252

;·.~f34BO

0:371-1490
1 ~,30-0344
1530·"0345
·14&0 .... 1841

2134BO
2B480
2B4BO

REBISTOR '100 1% . 12::?,W F n:=o+""IOO
RESISTOR 10 1% . 1~~5W F TC=()+'-100

24546
:~454~1

C4·.. 1/il .... TO-l0l· F
(;4",1 18-TO ··1 or~ O-F'

BWIl'CI+"PB BPBT·N·NO MOM .IA
SWITCH-·PB Sf'ST-NCI MOM .1A

;!B4BO
2B4BO

:3101-2409
3101·· 2466

01295
01295

!3N74SI:~BN

IC DCllR TTL
IC DCDR TTL
DH1D~' .... ARRAY
DIllDE-ARRAY
DlIJDE ..·ARRAY

S ;\··TD".. 8·.. LINE ;\ .... INP
S 3·-TO···B-LINE 3-INP
50V 400MA
50V 400MA
50V 400MA

DIODE'-ARRAY 50V 400MA
DIODE .... ARRAY 50V 400MA
DIODE-ARRAY 50V 400MA
IC MI.IXR/DATA·.. sa. TTL LS IFTl1··1··LINE
Ie: CllMPAf~ATCIR GP QUAD 14··DIP-P PKG

0"1295
012(?~5

o1 ~~95

Ot,~95

01295
0129~:.~

0129~)

01295

N

SN'74S13E1N
TlD13:1
TIDI;13
TID133
TI!)133
TID133
TIDt:l3
SN74LSl
LM:n9N

~;1

IC CDMF'ARATIlR GP I,LJAD 14·"lHf'",P PKG
DIODE.-ARRAY !:iOV 400MA
IHl1DE ..·ARRAY 50V 400MA
DIl1I>E-·ARRAY 50V 400MA
DIDDE·.. ARRAY 50V 400MA

01295

DIOlI['-ARRAY
DIODE-'ARRAY
NETWORK'-RES
NEl WORK .... RES

OH!95

TID133
TIDl:13

01121

210A102

() 11 ;~~1

21 OAl 02

<~1l4BO

190;.~M"300~~

5UV 400MA
50V 400MA
10·-SIP1.0K
10··SIP1,OK

DIIlD['-ZNI~ 2.3?V
GROUND WIR~.

IIH~95
01~~('15

012'15
01295

01 ~~9~:;

OHM X
OHM X

9
9

5% DO-7 PD".4W TI:=···.1I74%

See introduction to this section for ordering information
. *Indicates factory selected value

N

LM3;l9N
TIDI ;53
TID'l:l3
TID133
TIDl ;13

6-25

Replaceable Parts-Model 641l0A

Table 6-11. AS Display Controller Replaceable Parts List
HP Part
Number

c

AS
81,2
83
C4,5
C6
C7
C8,9
Cl0
Cll
C12
C13,-15
C16
C17-22
C23
C24,25
C26,27
C28,30
C31
C32-37
C38
C39,40
C41,42
C43-45
C46
C47-52
C53
C54,55
C56,57
C58
C59
C60-62
C63
C64
C65,66
C67,68
C69
C70
C71-76
CRl-4
Ll
MP1,2
P2,3
P4
Rl-4
R5
R6-9
RlO-15
R16-18
R19
TPl-13
TPGND
Ul
U2
U3,4
US
U6
U7
U8
U9
Ul0
Ull
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23-30
U31,32
U33

64100-66519
0160-2055
0160-4822
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0180-0374
0160-2055
0180-0116
0160-2055
1901-0535
9170-0029
5040-6067
1258-0182
1810-0307
0757-0280
0698-3438
0757-0280
0698-7028
0757-0280
0684-1211
0360-0535
0360-0535
1820-0681
1820-1453
1820-1917
1820-1201
1820-1453
1820-0681
1820-1112
1820-1322
1820-0629
1820-1449
1820-0693
1820-1144
1820-0683
1820-1208
1820-0688
1820-1211
1820-0629
1820-1197
1820-0688
1820-0683
1820-1322
1818-1396
1820-2024
1820-2191

U34
U35
U36
U37
U38-45
U46
U47
U48
U49,50
U51-58
U59
U60
U61
U62-64
U65-72
U73
U74
U75,76
U77
U78
U79-82
U83
U84
U85
U86
U87

1810-0536
1820-1144
1820-1208
1820-0681
1818-1396
1820-1997
1820-1208
1820-0693
1820-1015
1818-1396
1820-1112
1820-1191
1820-0697
1820-1435
1818-1396
0960-0530
1816-1496
1820-1432
1820-1112
1820-1130
1820-1428
1820-1208
1820-2024
1820-2075
1820-1451
1820-1191

Reference
Designation

Qty

Description

Mfr
Code

5
9
2
9
8
9
8
9
8
9
8
9
8
9
8
9
8
9
8
9
8
9
8
9
8
9
8
9
8
9
8
9
8
9
3
9
1
9
9
3
2
7
0
3
3
3
5
3
7
0
0
4
0
1
6
0
4
8
2
0
4
8
6
6
3
1
8
0
9
1
6
2
5
3
5

1
30
1

DISPLAY CONTROLLER BOARD ASSEMBLY
CAPACITOR-FXD .01"F +80-20% 100VDC CER
CAPACITOR-FXD 1000Pf +-5% 100VDC CER
CAPACITOR-FXD .01"F +80-20% .100VDC CER
CAPACITOR-FXD .1"F +80-20% 100VDC CER
CAPACITOR-FXD .01"F +80-20% 100VDC CER
CAPACITOR-FXD .1"F +80-20% 100VDC CER
CAPACITOR-FXD .01"F +80-20% 100VDC CER
CAPACITOR-FXD .1"F +80-20% 100VDC CER
CAPACITOR-FXD 01"F +80-20% 100VDC CER
CAPACITOR-FXD l"F +80-20% 100VDC CER
CAPACITOR-FXD .01"F +80-20% 100VDC CER
CAPACITOR-FXD .1"F +80-20% 100VDC CER
CAPACITOR-FXD .01"F +80-20% 100VDC CER
CAPACITOR-FXD .1"F +80-20% 100VDC CER
CAPACITOR-FXD 01"F +80-20% 100VDC CER
CAPACITOR-FXD l"F +80-20% 100VDC CER
CAPACITOR-FXD .01"F +80-20% 100VDC CER
CAPACITOR-FXD .1"F +80-20% 100VDC CER
CAPACITOR-FXD .01"F +80-20% 100VDC CER
CAPACITOR-FXD l"F +80-20% 100VDC CER
CAPACITOR-FXD .01"F +80-20% 100VDC CER
CAPACITOR-FXD .1"F +80-20% 100VDC CER
CAPACITOR-FXD .01"F +80-20% 100VDC CER
CAPACITOR-FXD .1"F +80-20% 100VDC CER
CAPACITOR-FXD .01"F +80-20% 100VDC CER
CAPACITOR-FXD .1" F +80-20% 100VDC CER
CAPACITOR-FXD .01"F +80-20% 100VDC CER
CAPACITOR-FXD .1"F +60-20% 100VDC CER
CAPACITOR-FXD .01"F +80-20% 100VDC CER
CAPACITOR-FXD .1"F +80-20% 100VDC CER
CAPACITOR-FXD .01"F +80-20% 100VDC CER
CAPACITOR-FXD .1"F +80-20% 100VDC CER
CAPACITOR-FXD .01"F +80-20% 100VDC CER
CAPACITOR-FXD 10"F +-10% 20VDC TA
CAPACITOR-FXD .01"F +80-20% 100VDC CER
CAPACITOR-FXD 6.8"F +-10% 35VDC TA
CAPACITOR-FXD .01"F +80-20% 100VDC CER
DlODE-SM SIG SCHOTTKY
CORE-SHIELDING BEAD
PC EXTRACTOR
TEST JUMPER
NETWORK-CNDCT MODULE DIP; 16 PINS; 0.100
RESISTOR 1 K 1% .125W F TC~0+-100
RESISTOR 1471% .125W F TC~0+-100
RESISTOR lK 1% .125W F TC~0+-100
RESISTOR 27 10% .125W CC TC~-2701+540
RESISTOR lK 1% .125W F TC~0+-100
RESISTOR 120 10% .25W FC TC~-400/+600
TERMINAL TEST POINT PCB
TERMINAL TEST POINT PCB
IC GATE TTL S NAND QUAD 2-INP
IC CNTR TTL S BIN SYNCHRO POS-EDGE-TRIG
IC BFR TTL LS LINE DRVR OCTL
IC GATE TTL LS AND QUAD 2-INP
IC CNTR TTL S BIN SYNCHRO POS-EDGE- TRIG
IC GATE TTL S NAND QUAD 2-INP
IC FF TTL LS D-TYPE POS-EDGE-TRIG
IC GATE TTL S NOR QUAD 2-INP
IC FF TTL S J-K NEG-EDGE-TRIG
GATE TTL S OR QUAD 2-INP
IC FF TTL S D-TYPE POS-EDGE-TRIG
IC GATE TTL LS NOR QUAD 2-INP
IC INV TTL S HEX 1-INP
IC GATE TTL LS DR QUAD 2-INP
IC GATE TTL S NAND DUAL 4-INP
IC GATE TTL LS EXCL-OR QUAD 2-INP
IC FF TTL S J-K NEG-EDGE- TRIG
IC GATE TTL LS NAND QUAD 2-INP
IC GATE TTL S NAND DUAL 4-INP
IC INV TTL S HEX 1 INP
IC GATE TTL S NOR QUAD 2-INP
IC NMOS 16348-BIT RAM DYN 200NS 3S
IC DRVR TTL LS LINE DRVR OCTL
IC MICROPROC-ACCESS NMOS 8-BIT

28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
28480
56289
28480
56289
28480
28480
28480
28480
28480
28480
24546
28480
24546
01121
24546
01121
00000
00000
01295
01295
01295
01295
01295
01295
01295
01295
01295
01295
01295
01295
01295
01295
01295
01295
01295
01295
01295
01295
01295
50088
01295
34649

64100-66519
0160-2055
0160-4822
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
0160-3622
0160-2055
150Dl06X902082
0160-2055
150D685X9035B2
0160-2055
1901-0535
9170-0029
5040-6067
1258-0182
1810-0307
C4-1/8-TO-l00l-F
0698-3438
C4-1/8-TO-1001-F
BB2701
C4-1/8-TO-l00l-F
CB1211
ORDER BY DESCRIPTION
ORDER BY DESCRIPTION
SN74S00N
SN74S163N
SN74LS240N
SN74LS08N
SN74S163N
SN74S00N
SN74LS74N
SN74S02N
SN74S112N
SN74S32N
SN74S74N
SN74LS02
SN74S04N
SN74LS32N
SN74S20N
SN74LS86N
SN74S112N
SN74LSOON
SN74S20N
SN74S04N
SN74S02N
MK4116N-3
SN74LS244N
C8275

7
6
3
4
5
7
3
8
0
5
8
3
2
8
5
7
3
5
8
0
9
3
3
4
8
3

1

28480
01295
01295
01295
50088
01295
01295
01295
01295
50088
01295
01295
01295
01295
50088
28480
28480
01295
01295
01295
01295
01295
01295
01295
01295
01295

1810-0536
SN74LS02N
SN74LS32N
SN74S00N
MK4116N-3
SN74LS374N
SN74LS32N
SN74S74N
SN74S158N
MK4116N-3
SN74LS74
SN74S175N
SN74S140N
SN74LS669N
MK4116N-3'
0960-0530
1816-1496
SN74LS163AN
SN74LS74
SN74S133N
SN74LS158N
SN74LS32N
SN74LS244N
SN74LS245N
SN74S38N
SN74S175N

0

42

2
1
4
2
2
2
1
11
1
6
1
20
3
2
2
1
3
2
2
1
3
2
2
4
2
1
1

32
3
1

32
1
2
32
2
1
3
32
1
1
2
1
4
1
1

NETWORK-RES 270HM 16 PIN DIP
IC GATE TTL LS NOR QUAD 2-INP
IC GATE TTL LS OR QUAD 2-INP
IC GATE TTL S NAND QUAD 2-INP
IC NMOS 16384-BIT RAM DYN 200-NS 3-S
IC FF TTL LS D-TYPE POS-EDGE-TRIG PRL-IN
IC GATE TTL LS OR QUAD 2-INP
IC FF TTL S D-TYPE POS-EDGE-TRIG
IC MUXR/DATA-SEL S 2-TO-l-LiNE QUAD
IC NMOS 16384-BIT RAM DYN 200-NS 3-S
IC FF TTL LS D-TYPE POS-EDGE-TRIG
IC FF TTL S D- TYPE POS-EDGE-TRIG COM
IC DRVR TTL S NAND LINE DUAL 4-INP
IC CNTR TTL LS BIN UP/DOWN SYNCHRO
IC NMOS 16384-BIT RAM DYN 200-NS 3-S
OSCILLATOR 25MHz
IC ROM 2KX8
IC CNTR TTL LS BIN SYNCHRO POS-EDGE- TRIG
IC FF TTL LS D-TYPE POS-EDGE-TRIG
IC GATE TTL S NAND 13-INP
IC MUXR/DATA-SEL TTL LS 2-TO-l-LiNE QUAD
IC GATE TTL LS OR QUAD 2-INP
IC DRVR TTL LS LINE DRVR OCTL
IC MISC TTL LS
IC GATE TTL S NAND QUAD 2-INP
IC FF TTL S D-TYPE POS-EDGE-TRIG COM

Mfr Part Number

See introduction to this section for ordering information

6-26

Replaceable Parts-Model 64110A

Table 6-11. AS Display Controller Replaceable Parts List (Cont'd)
Reference
Designation
U88
U89,90
U91
XU1,2
XU23-30
XU33
XU34
XU38-45
XU51-58
XU65·72
XU74

HP Part
Number
1820-0685
1820-1303
1820-0693
1200-0607
1200-0607
1200-0654
1200-0607
1200-0607
1200-0607
1200-0607
1200-0541

c
0
8
9
8
0
0
7
0
0
0
0
1

Qty
1
2
32
1

1

Description
IC GATE TTL S NAND TPL 3-INP
IC SHF-RGTR TTL S R-S PRL-IN PRL-OUT
IC FF TTL S D-TYPE POS-EDGE-TRIG
SOCKET-IC 16-CONT DIP-SLDR
SOCKET-IC 16-CONT DIP-SLDR
SOCKET-IC 40-CONT DIP-SLDR
SOCKET-IC 16-CONT DIP-SLDR
SOCKET-IC 16-CONT DIP-SLDR
SOCKET-IC 16-CONT DIP-SLDR
SOCKET-IC 16-CONT DIP-SLDR
SOCKET-IC 24 CONT DIP SLDR

Mfr
Code
01295
01295
01295
28480
28480
24840
28480
28480
28480
28480
28480

See introduction to this section for ordering information

6-27

Mfr Part Number
SN74S1ON
SN74S195N
SN74S74N
1200-0607
1200-0607
1200-0654
1200-0607
1200-0607
1200-0607
1200-0607
1200-0541

Replaceable Parts-Model 64110A

Table 6-12. A6 Secondary Drive Board Replaceable Parts List
Reference
Designation

A6

HP Part
Number

C

D

64110,-665116

2

II 180'-2879
0180--2879
0160-2930
11160-29:10
0'180-2879

7
7
9

A6CB
A6C9
AbelO
A6CII
A6CI2

0160-2930
0180-2879
11160-2930
0180-0197
0140-0149

9
7

A6CI3
A6CI4
A6CI5
A6CI6
A(,CI?

0160-2940
0160-29:50

I
9

0160-01~j'1

0180-2879
0160-0168

8
7

A6CIB
A6CI9
A6C20
A6C22
1'16(:2:1

01130-0094
11180-0291
0160-:55013
0180-2fl1l0
0180-1l094

4
3

A6C24
A6C25
A6[;27
A6C,!B
A6C29

0160-0154
0'160-48:52
01 60-,~930
0180-0197
0160-48:32

5
4

A6C:50
A6C31

0IbO-A8:12

A6Cl
A6C2
A6C3
A6C4
'AbC?

A6CRI
A6CR2
A6CR3
A6CR4
A6CR5
A6CRb
A6CR7
A6CR8
AbCR9
AbCRIO

o160-48:3;~'

Qty

BOARD ASSEMBLy-·m,cnON DRIVE

2f~480

64110-66506

2;WF+50-10% 25VDC AI..
22UF+~;0"-1 0% 2SVDC AL
.0IUF +80-20% !OIIVDC CER
. O'IIJF +80",,211% 100VDC CER
22UF+50-10% 25UDC AI..

2fl480

OHIO'-2879
0180-2879
0160-2930
0160-'29:50
0180--2879

CAPACHOR-·FXD .0tuF +80'"'211% ! OOVDe eER
CAI'ACITOf~'-FXD 22L1F+50-10% 25UDC AICAPACITDR -FXD .0tuF +80--20:>:: 100VDe CER
CAPACITOR-FXD 2.2UF+-IO% 20VDG TA
CAPAClTDR"'FXD 470PF +-5% :IOOUDe MICA

211480
2,B480
;,!0480

CAPACITOR-FXD
CAPACIH)R'"'FXD
CAPACITOR-FXD
CAPACITIJR-·FXD
CAPACITOR-FXD

470PF +-5% 3110VDC MICA
.OIIJF +80-20% 'IOOVl)C Gf,R
4700PF +-10% 200VDe POI~E
;!,~UF'50-"1 0% 25VDC AL
.IIJF +'-10% 2,00VDC POLYE

2134110
284BIl
2B4BO
21.1480

CAPACITIJR'"'FXD
CAPACITOR-FXD
CAPACITI)R-"FXD
CAPACITOR-FXD
CAPACITIlR-"FXI)

10 olJF+75"'11l% 25VDC AI..
tuF+'-1 OX 3~lV1)C TA
I UF +BO'-211% ~;ovl)e eE:R
2,!0 OUF+50-1 11% 16VDC AL
1 00LJF+75"10% 25VI)C AL

4

CAPACITOR-FXD
CAPAClTOR"'FXI>
CAPACITOR-'FXD
CAPACITIJR-"FXD
CAPACITOR-FXD

2200PF +-10% 200VDC PDI..YE
. OtuF +-10% 100VDC Cf:,R
.0IUF HlO-20% 100VDC CER
2. 2UF+-'1 0% 20VDC TA
.0IUF +,-10% lOOVDC CER

4
4

5

6

9
7

9

B

;,>

I>

I

"

o

2
'1
1
1

4
I
4

9
B

I
7

1901-0050
3

1901-01l~jO

:1

1'101-0050
1'101-116211

3
3
9

190 t -0 022

A6CRll
A6CR12
A6CRI3
A6CR14

1901-0022
1901-0022
1901-0022
1901-0040

A6HI:l
A6H50
A6H52

2190-0 Il 05
2260-0001

A6J2

1'~00-·0607

A6L1
A6L2
A6L3

',100--,.1276
9140-1l115
',140-0114

9
5

A6LSI
AbMPl

~~~20

0-01 0;3

Mfr Part Number

CAPACITOR-FXD
CAPACITOR-'FXD
CAPAClTOR-FXD
CAPACITIlR""FXD
CAPACITOR-FXD

1901-1l535
1901-'0Ile;0
19111--0050
1'101-01150

1901-00~;0

Mfr
Code

Description

1

4

9
1

2

5

~j6289
;~8480

;~,B480

56~:~89'

562.89
~!84BO
;~fJ4nO
~j621l9

2B4BO
;,8480
2B480
~.i62B9

OI60-2'no
OHIO--2879
11160-,.19:50
1 ~50D225X9020A2
0140-0149
0160--2940
OJ 61l-29:10
0160'-0157
01(10-28'79
0'160-,,011>9
30Dl07G025DD2
1 ~;onl 05X9035A2.
0160-":1508
0180'-2880
30Dlil7G02SDD2
0160'-0154
11160-4832
0160"-2930
1 ~iOD(.~i.~5X902I)A2
0160-4B3;~

CAPACITOR""FXD . II!IJF +--10% 100VDC CER
CAPACITOR-FXD .0IUF +-10% 100UDC CER

284110
2B480

0160-48:12
0160-4832

DIODE-8M SIG SCHOTTKY
DIODf,'-SWITCHING 80V 200MA
DlDDE--8WITCfHNG 130V 200MA
DIOI>E-SW1:TCHING 80V 200MA
DIlll)E--BWITCHING 130V 200MA

213480
2f.14BO
«8480
2B480
211480

1901-0S:55
I'IOI-OOSO
1']01-0050
190 1-00~;0
1'701-0050

28480
:,0480
2f.14BO
'm171
284811

1'701-0050
1'701--0050
NDP250
1901"-0022

2B4BII
284BIl
284EIO
2B4flO

190 1-0 0,~2
1901",0022
1'701-0022
1901--01140

00000
2,84BO
;!13480

ORDER BY DEECRIPTION
21'70'-0005

;!8480

9100-2276
9140,-0115
9140-0114

DIODE-SWITCHING
IHOJ)E"-flWITCfHNG
DIODE-SWITCHING
D'[IJDE--!3WnCfHNG
DIODE-STABISTOR

811U
80V
BOU
60V
10V

2110MA
200MA
200MA
400MA
250MA

2NS
2NS
2NS
2NS

DO-35
DO-35
DO-35
DIJ'-35

2NS DCI-3l:'
2NS D[I--35
2NB DO'-35
])1l-35

250MA
250MA
250M
50MA 2N~; DO'-35

SCRfW"'MACH 4-AO . ;!5-IN"'L.G PAN-"HD'"'PDlI
WASftER--LK EXT T NO. 4 .116"'IN'-ID
NIJT-+IEX-'DBL"'CftAM 4-"40,, HID . 094--IN" THK

o

2~1480

2B481l

DIOl)E"-flTABISTOR 1 OV
DIllDE-STABISTOR 10V
DT.ODE"·BTAIH!3TDR I OU
DIIlDE-~;WITC:HING 30V

9
9

;~8480

28480
;!13480

SIlCKET-IC 16-CDNl DIP DJP--SLDR

1901-'00~iO

2~~60-0001

1,~OO"-Ob07

~~B4BO

4

INDIJCTIlR RF-'CH""MLD 10 OIJH 111';( .1 05DX. 26LG
INDUCTOf~ RF-CH'-MLD 22l1H 10% • 23DX. 57L(;
INI)l)CTDR RF-"CH-'ML.D lIJUH 10:>:: . 16bDX. :5135L.G

9160-0244

3

SPEAKER'- .1 W

2841111

2

CLIP""CABL.E
TERMINAL TEST POINT PCB

2fl480
00000

014;,!5-01,~07

A6MP~~

1l1425--0120?
0:560-05:35

A6Ql

18~)4···0215

A6Q2
A61l3
A6Q4

lB54--0215

A6Q5

1854,,-07',8

TRANSISTOR NPN
TRANSISTOf~ NI'N
TRANSISTllR NPN
TRANSISTOR PNP
TRANSISTOR NPN

047'13
04713
0:3e;08
04713
04713

2N:3904
2N:l904
2N4401
c,N4403
Mf'S·-U45

TRANSISTor~ PNP 81 DARL PI)"IW
TRANSISTOR Nf'N iH PD"3~;OMW FT=250MHZ
TRANSI8TOR NPN SI DARL PD,m500MW
TRANBISTOR NPN Sl PD=350MW FT=~~50MHZ

0471:5
04713
04713
04713

MPS-"U95
Sf'S ;~:53
MPS"'AI4
SPS ;~~~~3

RESISTOR 61.9K I I .12514
RESISTDR 2.21K IX .125W
RESISTOR-TRMR 50K 101 C
RESISTOR 42.2K 1% ,12~jW
RESISTOR 820 5% .2514 Fe

24~j46

,!,11480
2-4546
oItl!1

C4"-1 18-TO'-6 'I9:?""F
C4-1/8-TO-2211-F
2100-0558
C4-1/8-TO-4222-F
CB0215

A6Q6
A61l7
A6Q8
A6f~9

A6RI
A6R2
Abl~3

1854-0467

lB53-02'il
Hl~j3-0449

19,;4,-0246
I B54-0 472
H154-0246
0757-0460
0"157-04:50
2100-0558

A6R4

0698-'~H50

A6R5

01.,(33-8215

A6R6
A6R7
A6RB
A6R9
A6RIO

6-28

7
5
1
8

2
B

I
4

7
9
3

061];\-13215

~~

Ol,.B3-8215

3

06133-1215
0"157-0419
0764-0016

9

o
B

I
3

:1
2

2

RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR

HI PD-3,;OMW FT=30 OMHZ
S1 PD-350MW FT=:51l0MHZ
;~N4,401 51 TIl--92 PD-:31IJMW
21'1440:3 51 TO'-92 PD-:l1IJMW
HI DARl PD-1W

F Te-O+-IOII
F TC=0+--100
TOP-ADJ I-TRN
F TC::O'f'~"100
TC--400/+601l

820 5% .25W FC TC--400/+bOO
82,0 5% .25W FC TI::-,-400/+600
120 c;% .25W FC TC--"400/+600
6BI 1% .125W F Te-oo-IOO
IK 51 2W MO TC-0+-200

;!B48 0

24546

111121
0"112.1

01121
24~j46

284flO

See introduction to this section for ordering information
*Indicates factory selected value

ORDER BY D[SCRIPTION

CBB215
Cflt:\c,15
CIlI;".15
C4-1/8-TO-68IR-F
0764-0016

Replaceable Parts-Model 64110A

Table 6-12: A6 Secondary Drive Board Replaceable Parts List (Cont'd)
Reference
Designation

HP Part
Number
0'15?-·fJ 124

C
D

A6R14

0'757-0419
IJbIB-·1215
0'757-04311

4
0
'7
5

A6Rl~:)

1J?~S7-0430

~i

O'7~i7-04:;0

5

AbRIl
A6R12

A6R13

A6R16
A6R17
A6RlEi

()6t:l~5~Ml 02~.'i

<;>

9
6

A6R20

06133-,1025
07:'57···· 0465
;!I 0 0-:;i,'1:5

AbR21

oni7'''044,!

<;>

A6R2~~

o'7~::;7- 046~i

A6R2:;
A6R24
A6R25

oni7,,,O!i'.'4
0'757-'0463

6
4
4
7

A61l1 '7

0606--22'1 fi

9

A6R26

06B3-1015

A6Il;!7
A6R28

Ohf:l3-~~2:'~5

~i

0'757-,0470

A6R ~~9

1l?~;7--0463

3
4

A6R30

069B-34~.:jO

9

Description

Qty
RESISTOR
RESISTOR
RESISTI)R
RESISTOR
RESISTOR

39,2K 1% ,125W
681 1% ,125W F
120 5% .25W FC
2,21K 1% ,125W
2,21K 1% ,125W

F ·rC=O+-100
TC=O+-100

i"B4BO
2.4~~46

O?~.:.i7-0 1 :.?4
[:4,1/8- TII"'601 r!'-F

TC=--400/~·600

() "11 ~.~"1

CB121~:j

F TC=O+-100
F 1·C=0+-100

~.~4~:;46

[;4 '1/8'''TO''',~i'!11 ..·F
C4·.. 1I8 .... TO,,221·j .... F

~!B4nO

~'.'1110"3'!13

rlEfiJbTDR 'jlll( 1% .12:·.iW F TC~O+""1110
RESISTOR lOOK 1% .I25W F TC-O+-IOII

;.:.~4~':'i41.")

;.~. 4 ~.'j 4 6

111121

r::n;.:~:.:.~15

RESISTOR 100 5% ,25W Fe TC=-400/+500
RESlflTOR 22K 5% .25W Fe ·rC=-400/+800
RESISTOR 162K 1% ,125W F T8=0+-100
RESI:~TOR 82,5K 1% .125W F rC=O+-100
RESISTOR 42,2K 1% ,125W F TC=0.·-100

01'1:' 1

CB2;?:·:l;~)

?4~.:i46

[;4 .. 1/8"TO"·'16;:>:\

;.:~4;':';46
;.:.).4~.:i46

··F
[;4",'1 18'''TO''Ai,,;:>i,! "'1"

;:~4546

C4····1/B····T 0 ·-42?;.:? ···F

RES:[STOR 42.2K 1% .125W F TC=O+-100
RESISTOR 220 5% ,25W FC TC=-400/+l)OO
RESISTOR 3.3 5% ,5W CC TC=O~·412

06'fll"';14~jll

I
EI

A6R34
A6R:35

0606·.. 0335
O?:;i7-04'73
Ob'1E1 ..·344:;

6
II

RESIS·TOR 221K 1% .125W F

A6R36

06'78<14i~1l

RESI~;TDR

T(~=O+-100

287 1% ,125W F 1·C=0+-100

A6RTl

IIn"7"04~jI3

A6R3fJ

06136-,1

OO~j

1
7
I

A6R:39

il6(9!:l'--3157

;:\

A6R40

06<18-31

~::;'7

3

RESls·rOR 14,7 1% ,125W F T(~=O+-100
RESI!:IlOR ;:;d ,ll{ 1% .1~:~~.:}W F TC::::IH··~100
RESISTOR 10 5% .5W CC TC=0+412
RESISTOR 19.6K 1% ,125W F TC=Oi·-10D
RESISTOR 19,6K 1% .125W F TC=O+·-iOO

A6R41

116'18'<1447

A6R42

0'7~j7-1144;,

4
0

RESISTf)R 422 1% .125W F TC=0+-100
RESIS·I·OR 11K 1% ,125W F TC=O·~-100

A6Ul

'l1li!1I·"14:".1
IH

Mfr
Code

~:~

4 ~:.:i 4 6

i'1;)4130

U11 ;.:! 1

CFl1015

II 11 i,!1
01 l ,! 1

Cn ;:~ :.:.). "1 ~:i

?4;::i46

(::4·1/0·-T 0 "·2;.! '1 :; .. F

EB33C~5

,~4546

C4· .. ·.l/B .. TII ..·i28711 ..+

n:lUl'lB

PME55-1/8-TO-14R7-F

II 1'J 21

C4-1/8-10"5112 .. r
ED'I 0 ()~:;

;:~4546

[;·4-1/8"TO"·191>:'.'· F

~:~4~:;46

[;4-1/8"TO-1962-F

;.:.~ -4 ~.'j 4

6
~:!. 4 ~.:; 4 6

C4 '1I8'''TII-42211 ·F
C4 .. 1/8 .... TO ·.. 11 '.Ii" ..·F

n129~::;

!::'N74S3BN

01 ;.:.l.(?!.'.'i
27[114

BN7406N

?4;:;;46

l.M2900N
SN'? 41..SC.:.?"1 N

IC MV TTL LB MONUSTIL DUAL
Ie GATE TTL LS NAND DUAL 4-INP

O"l??5

lH;:~O-14:.:~:.:

Ie MV ·TTL LS MONOSTBL RElRTG

()

1 fI;.!6"·1I11311

Ie TIMER TfL MONO/ASTIL

{) 12 rt:::i

DIODE-·ZNR lN5363B 30V 5% PD=5W TC=+29MV
DI01)E~··ZNR 5.11V 5% D()-35 PD=.4W

2.B4HO

19()?····0644

:';1l480

190;.?'-0041

CABLE ASSEMBLY-MOTHER

21l4DO

lB2~O"··1~:.~04

3
4

+.

C4··1/B~··TO·~·82.~i;.:.~

o·.I29~:;

See introduction to this section for ordering informatioD
*Indicates factory selected value

1;:!9~j

EN?4LS,!IIN
SN.'7 41 ... S1 ;:~;:~N
NE~.:i~~;5P

6-29

Replaceable Parts-Model 64110A

Table 6-13. A7 Transformer Flyback Board Replaceable Parts List
Reference
Designation

HP Part
Number

c Qty

0-6651)~j

A7

6411

A7CI
A7C2
A'7C3
A7C4
A'7C5

0160-4740
0180-28131
0180-2<1<11
1)160-2902
o IbO-4;~30

3
1
I
5
6

A'lGb
A7C7
A7C8
A'7C9
A7CIO

0160-4230
o '160-4,!30
0180-2913
0160-·3:3:55
0180--,!880

6
6
0
4
0

A'7GRI
A7CR2
A'7CR3
A?GR4
A'7CR5

1901-00~jO

3

1901-,0719
1901-0'719
1901-·0845
1901-0B45

I
I
4
4

A71)SI
A'7DS2

2140'-11013
2140-·00t:!

5
5

;:>

A7H2:3
A7HBO
A7fUm
A7H89

2.360--0117

2
1
3

1
2
2

I>
0

'I

2

9

~~

A7J1
A'7J2

'!2~:)1-:3475

:1

12~51-ej502

I

A7L1
A7L.2
A71..3

'n40--0179
9140-0:319
9140-,,04131

I
I

A'7MP 1
A7MP2

1~~O5-02l")7

8

1400-,,1 '1313

8

A'7QI
A71l2

18::;4-0467
Illf;4·- 0 623

5

A'7RI
A7R2
A7R3
A'7R4
A'7RS

06~13-;~215

1
7
3

OMl3-.. 1015
O~d33~'1

045

11683-·22;:!5
0683-1045

A7R6
A'7R7
A7R8
A'7R9
A7RIO

1l6fl3-1025
06B3-4'745

1
;1
2

3
9
6
6

1
4

0683-1055

5

2

116B:~-'4745

6

A'7Rll
A7R'12
A"lR1 :1
A7RI4
A7R15

0683-4745
~.~1 0 0-38It~?
;~'l 00-,3892
06lB--1 01~;
0764-01116

6

A7RI6
A'7R17

11683-1055
0683-1015

A7T1
A'7T2

,OIIJF +80-,,20% lKVDC CE.R
,OIL1F +80-20% lKVDC CER
4701.JFi·50 '-1 0% 50VDC AI..
tuF +-'5% 200vnc MET-PIJI..YC
2?00IJF+50·-10% 16VDC AI..

<~8480

2f.H80
28480

0160-2902

71~j90

GAP'-103

71590
71590

GAP-·I03
GAP-I03
01 BO-2913
0160-3355
01BO-2880

~~B4BO

21:14f:l0
,!13480

IHODE-SWITCHING 80V 200MA 2NS DO ..-3ei
IH Ol)E:--'P WR REGl 400V 3A 300NS
DHl1>E--PWI, REeT 400V 3A :IOONS
I>IODE ..+IV RECT ;:'~KV 50MA ~~5nNS
DIllDE-tiV RECT 2.KV 511MA t.~50N8

284BO
0471 :~
04713
lB546
1 }):546

1901-0050
MR854

L.AMP-·GUlW 5AB·_·A 70/57VDC 300UA T .... 2 .... r

SCRF:,W···MACH 6-;~E~ ,375-IN-"I..G PAN·-·llD-·P IlZ I
CABLE TIE .062-, 6c.~5-DIA ,091-Wll NYL_
STANDIlf'F .... RVT·-ON .375-IN····LG 4 ..-40THD
STANDOFF-RVT-ON ,125'-IN-LG 6-3;~nm

00000
06:lEl3
000 00
00000

IlRDER BY DEfiCRIPTIDN
Pl.T1 M·-8
ORDER BY DESCRIPTION
ormr.R BY Dr,,:SCRIPTION

CDNNECTOR lO--PIN M POST TYPE
CONNECTOR 4-"PIN M UTILITY

~!1l480

1 ~~-:::j1-3475

284BO

1251--5502

~?B4BO

9140-0179
9140 ..-0319
9'140-04111

5AB~"A

70/57VDC 300UA T .... 2 .... BUl.B

RESISTOR 2;;!O 5% .2~;W Fe: T(;=-400/+600
RESH1TOR 100 ~1% .2:"jl,d Fe TC= .... 400/·.·500
RESISTOR lOOK 5% ,25W Fe T(:=-400/+(l00
RESISTOR ~!. }?K :::j% .25W
TC= .. -400/+700
RESISTOR lOOK 5% .25W FC TC='-40 0 1 +Il 00

Fe

RESISTOR
RESISTOR

-e,4

, ~.~~jW FC TC=-.. 400/+600
lK
470K 5% • 2~:iW FC TC=-BII O/+'lO 0
~J% .2:':HII fC TC= .... 80 O/HII 0
RESIf.iTOR 1M 5% .25W Fe T(;=-(l00/+900
RESISTOR 470K 5% • (~~5W FC rC=-"800/+900

RESISTDR 470K

20480
;.!1l4BO

Mr~El54
VG'-'(~X

VG-.. 2X

2<1400

120~5"-O267

(?8480

1400-1139

03~;08

2N4401
2N6:l06

04713

{l1t;:!1

CB~:!215

H~l

CDI 015

01121
0'1121
01121

CH1045

01

01121
01121

01121

o11~!1
01121

CB22;~5

CB1045
CBI025
CE<4745
CB4745
CB1 O~iej
CB4745

o11 ;:.~ 1

CFl474~;

284811

2100-";5892
2100,,-3892
CIII 01~:;
0764--0016

RESISTCIR 4701( eiZ ,25101 Fe TC=-800/+9110
RESJ~3TnR····TRMR 2. ~!M 10% C Hlp .... ADJ 1"-TRN
RESISTIlR-TRMR 2.• ~jM 10% C TOP-ADJ 1 ~~TI~N
RESISTOR 1011 ~)% .2~jW FC TC= ..-400/+500
RESISTCIR lK 5% 2W MCI TC=II+·_·20 0

;'~B480

~"5

RESISTOR 1M ~)% • ('~5W FC TC="BOO/i"~OO
RESISTOR 100 ::i% ,25W FC TC=-4110/+500

111121
11'1121

CB105fj

9100·..·4195

5

9100-418;=

0

TRANSFDRMER-HORIZONTAL
TRANSFORMER '-FL Y11ACK NORMAL DIUVE 24500l-tZ

213480
284811

9100-4195
9100,-4182

TE.RMINAL TEST POINT PCB
TERMINAL TE8T POINT PCB
TERMINAL. TEST P01NT PCB
TERMINAl... TEST POINT PCB
TERMINAL lEST POINT PCl)

001100
000(10
00000
00000
00000

ORDER BY
OI~J.)r::R BY
ORDER BY
OIH>ER BY
ORDER BY

DIfJl)E·-ZNR 21.5V 5% DO-3::i PD",4W

;!8480

19 0 ;:.~-324~j

CABL.E: AB:3EMBLy····DIHPl.AY DRnE

2134130

64110'-616111

II
0
7
8

O~360-053~:;
O:~60-0535

0:360-05:35
O~~I.)O-05:~5
1902-~5245

A7Wl

641111-61610

2

~5

0360····05:~tj

A'7VR 1

6-30

0160-4740
0180-2BBI
0If.10-·2881

TRANSISTOR NPN 2N4401 S1 TO-.. 92 PD=3'10MW
1 RAN818TOR NI'N t~N6;306 131 TD .... ~3 PD=12r7JW

061l:~-4745

ATl!'1
A'7TP2
A71P:3
A'7TP4
A'7"TP5

64110-66505

28480

HEAT SINI( SGI.. TO'-3-C8
CLl P -.. eMP NT , :17·-D1A NYL.

fj

:1

28480

INDUCTDR RF·_·CH-.. MLD 22IJH 111% , 166DX, ;51351...G
INIHJCTOI,·-FIXED LINEAR ITY; DEFL ClJllRENT
COII.. .... VAR ,~IILJH .... 130I.)H PC"-MTG

8

Mfr Part Number

TR ANilFIlR MER-'F l.. YBACK

LAMP·-GI..OW

113flO-1I334
0:380-0342

Mfr
Code

CAPAClTOR-FXD .015F +-5;( 4COVDC POl.YP
CAPACITOR-"FXD 1 0IJF+50····1 0% ~;IIVDC AL
CAPAClTOR-FXD 10UF+50-10;( 50VDC AI..
CAPAC1TIlR·-FXD ,OIIJF +-··211<: lKVDC CER
CAPACITOR'-FXD ,Oll1F +80--20% lKVDC CER
CAPACITDR····FXD
CAPACITOR-FXD
CAPACITDR·_·FXD
CAPACITOR-FXD
CAPACITDR-'FXD

,.~

1400-·0;~49

Description

0

'l

111121
2~:t4BO

See introduction to this section for ordering information
*Indicates factory selected value

Cl'll015

DEf,CRIPTION
Df'SCR IPTION
DESCRIPTION
DFSCRIPTION
DESCRIPTIDN

Replaceable Parts-Model 64110A

Table 6-14. A8 Rear Board Replaceable Parts List
Reference
Designation
AS
ASSNI
ABBN2
AElBN3
ABfjN4

HP Part
Number

C
D

64110-66501;1

4

1250-103,!
1250-10;32

2
2
2
2

1 ~?'50-1 032
12~jO-l

0;12

Qty

Mfr Part Number

BOARD ASSEMBLY-REAR

21;14BO

64110,-66508

4

CONN RF SNC-BHD MIG
eONN RF IlNC-·BHD MTr;
CONN RF BNC-BHD MTG
CONN RF fjNC .... BHD MTG

284EHI
2B4S0
28480
;.!B480

1;.:"'50'-'1032
1250-1 O~32
'1 ;.~50·"·1 032
1250-1 O;~2

7
5
1
6

1
4
4
4

STANl)(lFF'-RVT'-ON • 187-IN·"·I...(:; 4 .... 40 TflD
WAi3H[R-·L.K IN1L T 1/2 IN .~;1l5-·IN-ID
NUT-HEX-DBL-CHAM 1/2-;~fl""IH!l . 1 (,~~)'-1. N··· TtH(
l.OCK .... SllBMIN D CONN

OCOOO

ORIIER BY DEsc:r~ IPTION
<.!l'?O·-1l06E1

00000
;!l1480

1
2

'.!B4BO

;11 01-1974

ABH81
AllHB3
AElH84
ASHBS

03!lO-0332
,!190'-0 068
2'?50-0054

A!3JI
ABJ2
A!lJ3

12.51-7100
1 ~1~'.i·1-4946

9
5

1~~51-4946

::;

CONNECTOR 26-PIN M POST TYPE
CONNECT DR 25-'PIN F D llllllMIN
CONNECTOR 25'-P IN F D SlIllMIN

ABSI

3101·-1974

B

SWITCH-·RKR Dlp·..·RKR" A!3!3Y 7 .... 1 A ,

1251-0218

Mfr
Code

Description

O~.~A

;3tlVDC

~"34BO

orHlER BY

;:.~B480

H!~:jl'-7100

;:.~04BO

1 ~?r51-4946

~~B480

1 ;':!~:il'-4946

See introduction to this section for ordering information
*Indicates factory selected value

DEfH~lnpTIllN

1{.~~:;1-··O21l~

6-31

Replaceable Parts-Model 64110A

Table 6-15. List of Manufacturers' Codes
Mfr
No.
C0633
80545

00000
0"1121
012[11
01295

021'11
0;5508

03888
04713
0638:5
0691~j

0726:1

07416
OB806
lB546

13103
1 ~:j454

16299
113324

19701
24546

2"1014
;,'7167
28480
31...585
309B~~
3~:?293

34344
34649
51506

56289
71590
71744
72136
7~j042

75915
e~:'S259

9Nl '71

Manufacturer Name
RIFA
NIPPON EL.ECTRIC CO
ANY SATISFACTORY SUPPl..IER
Al..L.EN--[

I I
..."" '"
I I

-C15-

-C20-

-C16_
-R25-C17_R26-

-C21_C22_

8

-C32- _R36_
-C34-C33-

-R37-

:ll

-C18-R27_C19_
-R28-

-

B

<9

I

C')

R30

U4

•

...

R29

•

G
US

r-,
r-,

:

..J

I

J4

-RT3_

J1

II
C30

C28

C27

I

II

I

R33

I

C26

j

;]:I

;]:I

"

I

'I

;]:I
CD

-R21-R22-C13-R23-R24-C14-

-RH_R3_
U1
-C5- -C9-C1-R10- -C10-C2-R11- -R18- R 4 - - R 8 - -R12-C12-

.....

II

.. 02-

II
II

-R13-

[!]

-OSl-

-R38-

:D

U1

8

I
I

C')

'"
U1

I

C')

'"en

I

•

<

:D

'"•

I

C')

'".....

I

G

Figure 6-10.
Primary Board AlAl Component Locator
6-49/(6-50 blank)

Replaceable Parts - Model 64110A

MP2

r-

m!L_

_----MP1

MP3

-C29I~@-.
<
:c
I
~..>
1.-_ •
N

-L1-

(\

-R4-

IIII
11 i i

:c

0

<0

..................

00

-R28-C21-

I

o

N
UI

----C6----

I

I
o

N

""I

000

:c:c:c
...............
(.)-..IUI

-L2-

-RS-R9-

-053-

-C3-

-R10-

-R14-

-R11-

-052-

-R6-

-C18-

-R8-

-R7_

-R12-

II
Ti
.....

I

:c
.....
00

I

-CR7-R22-C17-

-R34-

-CR3-

:c
.....

(')

-CR21-

J2

III
:c

-R1_R13_

-C2-

---C9---

----R30--_

---C19----

III

-R2-R3-

J1

_ _ _ _ R31 ____

N:C:C:C

-C1-

CR1

----C7----

_____C20 _ _ _ _- - - - M P S - - - -....

r-------------MP4----~

-CR6-

I
o

""I

I

o

i

I

o

UI

I

---L3---

-R21-

I

•

•

-C16-CRS-R20-C1S-

U2

-R27-R24-

I

"I r
N

"

-R33-R32-

-C14-

I

-R23-

~

~

N

-CR4-R2S-1

U3
-R26-

I

I
8

-CR20-CR19-:c

_C13_
_R19_

R2

I

T1

I

-C10-

-R18_

Figure 6-11.
+5. -12 Volt Board AlA2 Component Locator
6-51/(6-52 blank)

Replaceable Parts - Model 64110A

-C34-

==~=

-C1-

•
U1

III

IIn

-RS-

::II 0 0

::II

iii

if·

!!! 11!!
lifIlfl

-C14-R30-R4S-

01

1I I I

::II ::II ::II

U2

iIi i

•

II I II

•

n~~~~

L-......I

-R31- -R32-

::II

i rT I i

-C28-

U3

U4

II

~

02

ri
0

~

-R12-

'"

r

1111111

::II 0

0

0

...::11 ::II

"I,ill
-R33- -R34-

•
us

1I I

TIr
III

0::11::11

"'''''''

iiT

LtJ88888
88
8

LJ-

R37

Q3

-CR6-

CR3C24R38

CR4

CRS

-C2S--R391--

C27

C2b

I

I I I

::II

....

::II
....

::II

....

i Ti

R40

Figure 6-12.
-3.25, -5.2 Volt Board AlA3 Component Locator
6-53/(6-54 blank)

Replaceable Parts - Model 64110A

I

J2

I
J3

I

J1

J4

I

Figure 6-13.
Interconnect Board AlA4 Component Locator
6-55/(6-56 blank)

Replaceable Parts - Model 64110A

,--..,

~-----~,

I

C1

,,----

I J11 I
L __ .J

I

r--,
I J10 I
L __ .J

-

-_/

(:---U1---....) (--:---u-;---'
..... _------./ ' - - - - - - - _ . . /

J9

,- J8
r-

"1

I
I
I H 801

I

I
.J

86

2

,- J7
86

2

,- J6
2

86

,-

J5

86

2

,- J4
86

2

,- J3

86

2

,- J2

86

r-----------,
IL _ _ _ _ _J1
_ _ _ _ _ _ .JI

2
+12 -12-3.25 -5.2 +5 +12VDD

888888 GND
8

Figure 6-14.
Motherboard A2 Component Locator
6-57/(6-58 blank)

Replaceable Parts - Model 64110A

-C1-

-C2-

~~::

-R1-R2-

-R16-R17-C4-

-C3-

I"u'l I"u'l

-cs-

-C6-

Hr 1r 1tj 1::1 H1~121
U7

D 18'
o
I rB

U8

DO DbJ
8 MErDla
o LJrU22 0 0 DOH

-cs-

U15

-C7-

1~281

U3
U2

EHa
GBBa
~~
I
ID D
DBB rO LJ
18
f
fB fB~:- H1~'·II~51II~58II~"II~"1
I
DDDDID BB
r:l r:J
•

XU21

XU3

~I

NORMAL

U29

-C11·

•

~

U36

c;i

~l
. . 00°
Elr~ I
I I'"

U45

~

-C17·
-R4-RS--

-C22·

~

C21

C2D

.£li

-C2S

-~1~:-

-C28-

oooorg
LI DOD
r
Ef
B
B
B
8 B
II I B BB8 aBD
U54

U61

C27

~ ~

C3D

'C31-

~

C32
-

11 !
C')

C')

I-R9--L1-R1D- -R13-R11- C45
-R12--

U79

C')

C44

C36

-C41·

C3f

C3S

CaS

C4D

·C42·

-C43

-R19-

-R14-C47-

£1§.

-R15-C49

Figure 6-15.
CPU/IO Board A3 Component Locator

6-59/(6-60

blank)

Replaceable Parts - Model 64110A
H86

®

H87

i
~

~'
H78

~~~n~

~
1

e
H86

Figure 6-16.
CPU/IO Mechanical Parts Locator
6-61/(6-62 blank)

Replaceable Parts - Model 64110A

C6

CPU/IO

to

I~

-L 1-

D W4 r1
~. J1
~

-R2-

A4W1

Figure 6-17.
Keyboard Board A4 Component Locator
6-63/(6-64 blank)

Replaceable Parts - Model 64110A

Jl
eND

TPll

GNO

TP14

DOG : :, G':"G G: : G"': 0' ,9' 'B ' ' B Q
B

TP2

TP16

,,~: 'G

TP3

'eo

TPG

B B B,o
BBB06666600
B8 0 : : : : : : '" : : : : : :
'" B,~ B 00000000
B
'"
Boo 0 0 0 0 0 0 0 0
C6

(29

C7

(6

(30

C3Z

e31

e33

C9

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(43

(45

C47

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TP2

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I

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....

I

0

-R4--VR1-RS-

-C8-

TP1

0

HHORDR

TP4

:a

....

G

II

0

Figure 6-20. Flyback Board A7 Component Locator

6-69/(6-70 blank)

(')

ID

Replaceable Parts - Model 64110A

I

BNC1

•

•
BNC2

J2

J3

BNC3

BNC4

I
Figure 6-21. Rear Board AS Component Locator

6-71/(6-72 blank)

Manual Changes - Model 64110A

SECTION VII
MANUAL CHANGES
This section
for models
title page.
first serial

normally contains information for backdating this manual
with serial number prefixes prior to the one shown on the
Because this edition includes the information for the
number prefixes, there is no backdating material.

7-1/(7-2 Blank)

Service - Model 64110A
SECTION VIII
SERVICE
8-1. INTRODUCTION.
8-2. The service section contains information necessary to service
the Model 64110A Logic Development System mainframe. The information
is presented in the following order:
Subject

Page

Mainframe overview .....•.•.•..•.. 8-1
Power supply .•..•.•........•..... 8-38
CPU/IO, including keyboard .•..... 8-61
Display controller .....••..••.... 8-109
Display driver ••..•....••..••..•. 8-155
8-3. Within each mainframe subject area the information is presented
in sequence of block level description, schematic level description,
troubleshooting, and finally, performance verification setups.
8-4. SAFETY CONSIDERATIONS.
8-5. This section contains warnings and cautions that must be followed for your protection and to avoid damage to the equipment. Read the
safety summary on the back of the title page and all warnings given at
the beginning of procedures, prior to servicing.
8-6. MAINFRAME OVERVIEW.
8-7. The overall mainframe consists of the following:
Power supply

Cardcage and motherboard

Rear panel

CPU/IO board

Keyboard

Display controller board

Display driver boards (2)

CRT display

Local mass storage/RS-232C board

Flexible disc drive

8-1

Service - Model 64110A
8-8. The flexible disc drive and local mass storage/RS-232C board
formation is included in the appendix.
8-9.

MAINFRAME OVERALL BLOCK DESCRIPTION.

8-10. The relationships between
shown on figure 8-1.
8-11.

in-

the

overall

functional

areas

are

POWER SUPPLY BLOCK DESCRIPTION.
ASSEMBLY Al.

8-12. The power supply assembly consists of four printed circuit
boards and many discrete components. The printed circuit boards are:
Primary supply board
+5, +-12 volt supply board
-3.25, -5.2 volt supply board
Interconnect board
8-13. The power supply accepts AC line voltage and provides other
circuits with the following regulated dc voltages: +12V display driver, +12V, +5V, -5.2V, -3.25V and -12V. It also provides the LPOP,
LIR15 and LINSYN signals.
8-14. The +12V display driver supplies power exclusively to the display driver circuitry.
The LPOP signal is generated when power is
first turned on and whenever there is a power failure on the AC line
or +5V supply. This signal goes to the CPU/IO section where it initializes the CPU and I/O circuits.
8-15. LIR15 is generated when the power supply senses a line voltage
drop below a set value. It is the only high priority interupt and
goes to the CPU/IO and display driver sections. It blanks the display
driver, and retracts the head from the flexible disc.
8-16. The LINSYN is a TTL signal generated from line power at line
frequency and goes to the CPU/IO section where it is used in the autoreset circuit.
8-17.

CPU/IO BLOCK DESCRIPTION.
ASSEMBLY A3.

8-18.
board
tabs.

The CPU/IO functions are contained on a single printed circuit
located in card slot A. It is identified by the blue extractor

8-2

Service - Model 64110A
8-19. The CPU communicates through the input/output section to collect, process and redistribute data as supplied or requested by the
peripherals. The input/output section contains the keyboard and HP-IB
interface circuitry. Also, it contains the circuits necessary to process various interrupts, LINSYN, power fail information, and to select
and interchange data with any particular slot in the cardcage.
8-20. The CPU/IO, printed circuit board A3, hosts the following functions; CPU, program ROMs, interrupt mask, mapped I/O and cardselect,
keyboard scan, HP-IB, bank switching, and auto-reset.
8-21. The CPU collects, processes and redistributes data as defined
in service routines stored in the program ROMs. The data is supplied
or requested by the peripherals through interrupt request to the interrupt mask. Data interchange between card slots in the cardcage is
controlled by the mapped I/O and card-select sections.
8-22. The CPU/IO board contains the necessary control and handshake
circuits for communicating over the HP-IB link to the disc and printer
and the RS-232C link to the various peripheral devices connected to
this bus. The CPU/IO board also contains circuits necessary for:
a.

Processing the various interrupts from the keyboard, RS-232C and
HP-IB circuits.

b.

Enabling the beeper via the CPU/IO board.

c.

Allowing the CPU to select and interchange data with any of
several boards in the cardcage.

the

d.

Monitoring LINSYN and power fail status and providing
formation to the CPU.

in-

8-23.

such

DISPLAY CONTROLLER BLOCK DESCRIPTION.
ASSEMBLY A5.

8-24. Located in card slot B is the display controller board. It is
identified by white extractor tabs. The display controller board provides three functions:
System clock generator
System RAM and RAM controller
CRT controller

8-3

Service - Model 64110A
8-25. The system clock generator provides the following clocks for
use by the entire system:
L25MHz ....... used by the CPU and sent to all option slots.
LSCLK1 ...... used by the CPU
DOTCLK ...... 25 MHz
RAMCLK ...... 12.5 MHz
LCHAR ....... 2.78 MHz
8-26. The RAM and RAM control provides 32k x 16 bits of dynamic RAM
to be used by the system processor and the CRT controller chip. It
also regulates access by the system processor and CRT controller chip
to and from the RAM.
8-27. The CRT control is provided by the CRT controller chip which
functions like a microprocessor to determine the information to be
displayed, and to control the display drive section.
8-28.

DISPLAY DRIVER BLOCK DESCRIPTION.
ASSEMBLIES A6 AND A7.

8-29. The display driver block includes two printed circuit boards.
The secondary drive board contains the secondary drive and beeper circuitry. It is called assembly A6 and is mounted by hinges on the bottom of the chassis. The flyback board, assembly A7, is mounted by
hinges to the top of the mainframe.
8-30. The two display driver boards provide the video, vertical,
horizontal, and bias voltages to drive the CRT. The video drive circuit, on the secondary board, features two signal levels, one for regular video, and one for inverse video. The inverse video level is
less to compensate for the brightness of a lit background.
8-31. The beeper provides an audio tone which is activated to alert
the operater at designated points in performance verification or normal operation.
8-32. The high voltage circuit, on the flyback board, generates CRT
grid voltage of -40 v, +200 to 700 v, and 0 to 470 V necessary to provide intensity and focus adjustments.

8-4

Service - Model 64110A
Table 8-1. Memory Map
ADDRESS

MEMORY FUNCTION

FFFF
FEOO

BASE PAGE RAM (512)

FDFF
FA18

DISPLAY (1040)

F9FO

BLANKED DISPLAY ROW

F9EF
COCO

HOST RAM (15,216)

BFFF
8002

HOST RAM (16K)

8001
8000

DISPLAY CONTROL

7FFF
4000

MEMORY MAPPED I/O
SLOT SELECTED (16K)

3FFF
0020

HOST ROM (16K)

001F
0000

BPC REGISTERS (INTERNAL)

8-5/(8-6 blank)

Service - Model 64110A

I

I

INTERRUPT LINES, FLAG LINES, I/O CONTROL, ADDRESS AND DATA BUSES

INTERRUPTS
FLAGS

{

25
CONTROL
I/O { ADDRESS
DATA

LDMAR
LINT
LlOSB
I/O ADDRESS & DATA

33
/

V

4

LOCAL MASS STORAGE
CONTROL

±12V, 5V, LPOP

r-----~~--L-~------~5~----------------------------------------~RS232
DISPLAY CONTROL & RAM

RAM AND
RAM CONTROL
DISPLAY DRIVER
CPU/1.0.
POWER
SUPPLY
±12V
+12VDD
& DO RET
+5V
--5.2V
3.25V
-3.25V
LPOP
L1R15
LINE SYNC

PROGRAM ROMS

H. VOLTAGE
HORIZONTAL
SWEEP GEN.

HPIB
KEYBOARD
BEEPER
INTERRUPT MASK
BANK SWITCHING
MAPPED 1.0. &
CARD SELECT
AUTO RESET

SYSTEM CLOCK
GENERATOR
DOT CLK (25 MHz)
RAM CLK (12.5 MHz)
SCLK1 (6.25 MHz)
CCLK (2.78 MHz)
SFT/LD (2.78 MHz)

CRT CONTROL

43

'/
en
w
en
:J


en
>
ci

ID

,....
~

....I

0

en

MEMORY {

DATA }
ADDRESS
CONTROL

N
J:

BUSES

MOTHERBOARD
SIGNALS
(EXCEPT -12V & -3.25V)

VV 75

V

en
en

:iE

w
a::

II)
('II

2

0
0

a::

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
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L

2

>
en

r - - - - -,

I
I
I
I
I
I
I
I
I
I
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I
I
I
I
I

0
P
T
I

0
N

S

--",,--

.-J

J:

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> ~

iii

C'! 3::iE

'P

....1....1

LlR15
LBEEP
+12VDD
DDRET
+5V

:> :i
ai' ~
I- a. ....I
II)

+• ....I
en >
....I
ci
> ·W :>
~ ID I- ....I
+ I- >
4
enID
....1....1

V 9
/

LHSYN
SVSYN
SVID
LIVID

86
/

V

MOTHERBOARD SIG NALS

{

tONTROL}

MEMORY

ADDRESS
DATA

BUSES

0

:iE

w

:iE

,

I

7

MOTHERBOARD SIGNALS. MEMORY CONTROL. ADDRESS. AND DATA BUSES

J
Figure 8-1.
Mainframe Overall Block Diagram (Sheet 1 of 2)

8-7

Service - Model 64110A
INTERRUPT LINES (LINT, lIRH, lIRL, LDMAR)
FLAG LINES (LSTS , LFLG , LHL T)

INTERRUPT LINES

'\

4
11/0 CONTROL BUS_(LDOUT, lIOSB, LDOUTD, HDOUTD) /

'\

"-

6

) 1/0 ADDRESS BUS (lIC1, 2, LPA 0-3)

/

LI/O DATA BUS (liOD 0-15)

/

,

"

"'\

16

1

>

,

FLAG LINES

3

1/0 CONTROL BUS

(

1/0 ADDRESS BUS

i

TO FLOPPY CONTROL

'\

'\

(

1/0 DATA BUS

,

/

"./
a

14

1 ,,1

1 1 1

va

......,
0

0
0

:::i

P/O LOCAL MASS STORAGE

".:
,....

I::J
0"'"
02
...J...J

0

6 1/16
,

"

II)
,....
..;
,....

0
I::J
0
0
...J

'\

'\

r-----l

0
II-::J
...JO ('II
J:O 0
...JJ: :::i

,

0
0

:::i

I

'";"

L I R RS232 RD, TO

0

0
0

:::i

FROM P.A.D.

{,"smOD

LIRRS232WR
I
A
RS232

RS232
PORT

...

LRS232 WR

I

,-

0
I::J
0
0
...J

FROM
P.A.D

,.

"-

LKB

lIOD7
lim 6
lIC D5
lIOD4
lIC D3
.I0D2
lIOD1
'liOD

KEYBOARD
INTERFACE
LO

~

HKA 0-6
HKYDET

,

ID

PAO

~

0

et

HIRO

/
/

<=)

y...
)J'

-

KEY BOAR

f

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P.A.D./
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TO I.M.
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20
HP-IB

20
L

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I

v

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I HIODO-7

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lLMSTR

/

LIe 2 HP IBJ

·f

I

DATA

,!f!B.Z-TO 10M. HDOUTD I INTERFROM P.A.D:~FACE
HMSTR
BUFFER

I

/

a

HP-IB
BUFFER

I-

(J)

I

•I

16
/

~

HP-IB

v

I

::iii

HP-IB
CONTROL

I-I~

A

I
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et lei:

I

LIl.
~MASTER ~ ----------g~------------ - - ~
",1

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111

V.BN' 4

Y
,....

L

0

BNC1
/BNC2
VBNC3
VBNC4

-...,

/

BNC11
BNC2
/

___ J

LRLY CNTRL

I

/

v

- - - - ------ - - - - - - - - - - - - - - - - l

I

/

-'>

REAR
PANEL

I
I

LPOP

L __

I

,I.M.

REAR
PANEL

I
I

2/
5
//4 BNC 1-4.
/

V
/

- - .J

z
m

cL

a:i

0

l-

ll.

(J)

...J

...J

) MEMORY DATA BUS (LD 0-15)

~5

/

16

L

MEMORY DATA BUS

<.

16
) MEMORY ADDRESS BUS (LAO-15)

/
)MEMORY CONTROL BUS

/

MEMORY ADDRESS BUS

/

) MOTHERBOARD SIGNALS

(

a
I
. / (LSTM, LMSYN, LSTB, LWRT, HWRT LOPCODE, LBYTE, LUPB)
MEMORY CONTROL BUS (
/
30
30
/ (GND, +12V, -12V, +12VDD -3.25 -5.2 LHSYN LVSYN, LVID, LIVID, LID, LMAP 1-3, lIR1, LSElO-4.BNC1-4 25 MEG, lIR15, LINE SYNC, LPOP, LBEEP, LPHI1) /MOTHERBOARD SIGNALS

<

Figure 8-1. Maintrame Overall Block Diagram (Sheet 2 of 2) .
8-8

TO DISPLAY
AND OPTIONS

Service - Model 64110A
8-33. MAINFRAME OVERALL TROUBLESHOOI'ING.

****************

*
*
*
*
*

WARNING

******************

Read the Safety Summary at the front of
this manual before troubleshooting the
instrument.

*
*
*
*
*

*********************************************

8-34. Before troubleshooting, refer to the Model 64110A Operating
Reference Manual for general operating information as suspected malfunctions may be caused by improper operation.
8-35. Visually inspect the instrument. Look for loose or burned components that might suggest a source of trouble. Verify that all circuit board connections are making good contact and are not shorting to
an adjacent circuit. Attempt to complete the Performance Verification
in Section IV. If no obvious trouble is found, check the instrument
power-supply voltages and external line voltage before any extensive
troubleshooting.
8-36. Troubleshooting for the 64110A mainfame consists of a step by
step procedure based on failures in performance verification tests,
failures of signatures in signature analysis, and traditional oscilloscope troubleshooting.
The procedure reflects the following hierarchy.
8-37.

The hierarchy for troubleshooting the mainframe is:

a.

First, the power supply must be fully operational before any
other part of the mainframe will work.

b.

Second, the CPU must be able to access ROM properly since the
code for basic operations and performance verification is resident in ROM.

c.

Third, the CPU must be able to acces RAM for scratch pad memory
and display functioning.

d.

Fourth, the display should be operational for feedback on the
operation of the mainframe.

e.

Fifth, the I/O functions are repaired.

8-38. Before troubleshooting the mainframe, remove all option cards
and make sure that all jumpers are in the normal position. The procedure assumes that all jumpers are in the normal position.
Any
option card has the potential of causing the mainframe to operate incorrectly by interfering with the memory bus transactions of the CPU
or causing the power supply to shut down.

8-9

Service - Model 64110A

8-39.

When using signature analysis the approach is to troubleshoot:

a.

First, the control signals. If the control signals are bad, the
output of the IC's will be bad.

b.

Second, addressing if appropriate.

c.

Third, if the above are correct, the actual data bit failure
checking the input versus the output of the IC.

8-40.
output

Any device connected to the signature analysis node (input or
to an IC or passive components) may cause the bad signature.

8-41.

Always use the schematics when taking signatures.

8-42.

POWER-UP SELF TEST FAILURE.

8-43.

First, draw as much information as possible from the power-up
self test beep sequence. These tests will verify the ability of the
CPU to access ROM and RAM correctly. The display test pattern verifies the display operation, and then the PV menu tests allow the
checking of the I/O functions.

8-44. A failure in the power on self tests may be determined by
noting the beep sequence. Table 8-2 details the beep sequence during
power-up self tests and the step to go to on failure.

8-10

Service - Model 64110A
Table 8-2.

Power-Up Failure - Beep Sequence Failing

BEEP .... the beeper beeps when power is first turned on.
not mean that the power supply is fully operational.

This does

BEEP NOT PRESENT .... check power supply
POWER SUPPLY FAILURE .... go to power supply troubleshooting
paragraphs.
POWER SUPPLY OK .... go to signature analysis test loop determination table.
BEEP .... software is initiated and the display is enabled.
BEEP NOT PRESENT .... check power supply
POWER SUPPLY FAILURE .... go to power supply troubleshooting
paragraphs.
POWER SUPPLY OK .... go to signature analysis test loop determination table.

3 BEEPS .... Indicates ROM test passed
SEQUENCE OF 3 BEEPS NOT PRESENT .... check power supply
POWER SUPPLY FAILURE .... go to power supply troubleshooting paragraphs.
POWER SUPPLY OK .... go to power-up ROM test table.
APPROXIMATE 7 SECOND DELAY
2 BEEPS .... Indicates RAM test passed

SEQUENCE OF 2 BEEPS NOT PRESENT .... check power supply
POWER SUPPLY FAILURE .... go to power supply troubleshooting
paragraphs.
POWER SUPPLY OK .... go to RAM troubleshooting paragraphs.

8-11

Service - Model 64110A
Table 8-3.

Power-Up Failure - Beep Sequence Passing

NO DISPLAY .•.. Press [B] key.
MAINFRAME BEEPS .... go to display troubleshooting paragraphs.
NO BEEP .... go to signature analysis test loop determination
table.
WRONG BOOT SOURCE .... use signature analysis setup A table.
(Power-up boot rear panel switch read setup).
NO KEYS BEING READ .... go to keyboard test failure in PV-tests
ures table.

fail-

INCORRECT IDENTIFICATION OF OPTION CARDS .... use signature analysis
setup C (PV menu I/O write test setup) to troubleshoot the slot
select circuitry, and check for stuck bits on the CPU memory bus.
MAINFRAME REBOOTS APPROXIMATELY EVERY 2 SECONDS .... move jumper J6 to
test to disable auto-reset. Check low priority interrupt circuitry
to find possible constant low priority interrupt and use appropriate
SA setup to troubleshoot. Use signature analysis setup C table (PV
menu I/O write test setup) to troubleshoot delta time interrupt circuit.
LOSS OF KEYBOARD REPEATER FUNCTION .... go to time interrupt test
failure in PV-tests failures table.

8-12

Service - Model 64110A
8-45.

PV MENU SELF-TEST FAILURE.
Table 8-4. PV-Tests Failures (1 of 2)

ROM TEST FAILURE .... Decode error mask and replace failing ROM(s).
DOESN'T FIX PROBLEM .... go to ROM troubleshooting table.
SELF-TEST FAILURE
ROM TEST:
FAILING ADDRESS RANGE

BYTE(S)

xx

xxxx-xxxx
Failed
Addresses

Byte

Failed
ROM Unit

--------0020-1FFF
0020-1FFF

0
1

U51

2000-3BFF
2000-3BFF

0

U50

1

u49

u48

Lower 8K ROM
Upper 8K ROM

RAM TEST FAILURE .... Decode error mask and replace failing RAM(s).
DOESN'T FIX PROBLEM .... go to RAM troubleshooting paragraph.
SELF-TEST FAILURE
*RAM TEST:
FAILING UNIT NUMBERS (S)

Xy
Where XY is the RAM U-number.
* Displays RAM TEST: or RAM TEST: REFRESH FAILURE

8-13

Service - Model 64110A
Table 8-4.

PV-Tests Failures (2 of 2)

I/O READ ERROR .... use signature analysis setup F table (PV menu I/O
read test setup) to troubleshoot.
TIME INTERRUPT TEST FAILURE.
CHECK LINSYN SIGNAL FROM POWER SUPPLY.
BAD .•.. go to power supply troubleshooting paragraphs.
GOOD .... use signature analysis setup C table (PV
write test setup) to check that the interrupts
issued from delta time interrupt circuitry, and
CPU is clearing delta time interrupt latch and
counters.
KEYBOARD TEST FAILURE .... use
(keyboard freerun setup).

signature

analysis

setup

menu I/O
are being
that the
autoreset
E

table

BADVh.
NO CLOCK .... use signature analysis setup 0 table (CRT controller outputs-hardware loop setup) to troubleshoot HSYN.
NO START/STOP .... use signature analysis setup E table
(keyboard freerun setup) to troubleshoot state machine and
keyboard counters.
VALID Vh.
BAD SIGS .... troubleshoot.
NO BAD SIGS .... use signature analysis setup
(keyboard buffer test setup) to troubleshoot.
SYSTEM BUS
paragraph.

TEST

FAILURE .... go

to

system

bus

D table

troubleshooting

RS232 TEST FAILURE .... use signature analysis setup H table (PV menu
rs232 test setup) and signature analysis setup C (PV menu I/O write
test setup) to troubleshoot. The RS232 connectors and cable are not
tested in the PV menu RS232 test.

8-14

Service - Model 64110A
8-46.

TEST LOOP DETERMINATION SIGNATURE ANALYSIS SETUP
TROUBLESHOOTING.
Table 8-5. Signature Analysis Test Loop Determination

LOOPNAME:

TEST LOOP DETERMINATION

The memory signature analysis latch
execution of the software tests.
test being performed.
SETUP NAME:

is

set and reset during the
The interval is unique to the

TEST LOOP DETERMINATION

In the event that the display is not functioning correctly, this
setup can be used to determine which of the tests the mainframe
is executing.
All option boards removed
All jumpers in normal position
ST/SP/START: A3TP5, rising edge (MEM SA LATCH)
QUAL/STOP: A3TP5, falling edge (MEM SA LATCH)
CLOCK: A3TP1, rising edge (LSTB)
Signatures
Vb

= CA27

POWER ON RAM TEST LOOP-SIMPLE RAM FAILURE
Go to simple RAM failure troubleshooting.

Vb

= AH68

POWER ON RAM TEST LOOP-REFRESH FAILURE
Go to RAM refresh failure troubleshooting.

Vb

= AU94

DISPLAY TEST
If wrong or no display, go to display troubleshooting.

HO RECOGNIZABLE Vh

Go to ROM troubleshooting.

8-15

Service - Model 64110A

8-41.

SYSTEM BUS TROUBLESHOOTING.
Table 8-6.

System Bus Failures

FAILING PV MENU SYSTEM BUS TEST.
YES .... use signature analysis setup G table (PV menu system bus
test setup) and signature analysis setup C (PV menu I/O write
test setup) to troubleshoot.
NO •••. setup G, the PV menu system bus test does not completely
check the mainframe. The following suggestions will help you
to isolate the failure to the mainframe, system bus cables, or
other devices connected to the system bus if a failure exists
on the system bus.
1. Verify that the system bus configuration is correct.
If
the configuration is wrong, this can cause problems in bus
communications. Refer to the site selection and installation manual for proper bus configuration.
Disc set to address 0 and printer set to address 1;
quired by operating system software.

re-

Mainframes set to addresses 2-1 with no two at the
address.

same

No more than
two
connectors
connected
to
device. Twenty meters maximum total cable length.

any

Only one master controller, and the
the end of the chain of devices.

master

located

at

2. Suspect the HP-IB cables.

3. If there are more than the disc and one mainframe,

remove
all but the master controller and disc from the bus. If
the failure goes away, add one device at a time until the
failing device is found. Troubleshoot that device. If
the failure remains, swap the components listed below for
troubleshooting a failing mainframe. If that doesn't work
then the problem is with the disc or system bus cable.

4. If the problem is isolated to a mainframe, swap the HP-IB
transceivers, PHI chip, and rear panel cables and connectors. These are not tested in the system bus test. The
HP-IB transceivers and PHI chip are in sockets, so the
socket could be causing the problem.

5. Problems may be caused by the line power source. Refer to
section I for proper power sources.

8-16

Service - Model 64110A
Table 8-7.
LOOPNAME:

Signature Analysis Setup A (1 of 3)

POWER-UP BOOT REAR PANEL SWITCH READ

The Memory SA latch is set and
rear panel switches on boot up.

reset

around

the

reading

of

the

SETUP NAME: POWER-UP BOOT REAR PANEL SWITCH READ
This setup is used to troubleshoot the circuitry associated with
the reading of the rear panel seitches in the event that the
mainframe fails to read the rear panel seitches correctly.
ST/SP/START: A3TP5, rising edge (HEM SA LATCH)
QUAL/STOP: A3TP5, falling edge (HEM SA LATCH)
CLOCK: A3TP1, rising edge (LBIOSB)
Vh

= U952
Node

Signature

Node

Signature

U 11- 5

low

U 27-14 high

U 13- 4
U 13- 5
U 13- 6
U 13- 7
U 13- 8
U 13- 9
U 13-11
U 13-12
U 13-13
U 13-14
U 13-15
U 13-16

U952
high
high
high
0000
U952
U952
0000
high
high
high
U952

U 28- 5 high
U 28-15 high

U 15- 3

low

U 17- 8 high
U 17- 9 low

8-17

Service - Model 64110A
Table 8-7. Signature Analysis Setup A (2 of 3)
Node

Signature

Set switches to
HPIB address-iF
Boot source to PV
TERM/MOD jumper A3Jl0 to MOD
Master controller
U
U
U
U
U
U
U
U
U
U
U

22- 1 high
22- 3 low
22- 5 low
22- 7 low
22- 9 low
22-12 low
22-14 low
22-15 low
22-16 low
22-18 low
22-19 low

U
U
U
U
U
U
U
U
U
U

40- 1
40-11
40-12
40-13
40-14
40-15
40-16
40-17
40-18
40-19

U
U
U
U
U
U
U
U
U
U
U

43- 1 high
43- 3 low
43- 5 low
43- 7 low
43- 9 low
43-12 low
43-14 low
43-16 low
43-17 low
43-18 low
43-19 high

8-18

low
U952
U952
U952
U952
U952
U952
U952
U952
low

Node

Signature

U
U
U
U
U
U
U
U
U
U

low
U952
U952
U952
U952
U952
U952
U952
U952
low

47- 1
47-11
47-12
47-13
47-14
47-15
47-16
47-17
47-18
47-19

Set switches to
HPIB address 00
Boot source to System Bus
TERM/MOD jumper A3Jl0 to TERM
U
U
U
U
U
U
U
U
U
U
U

22- 1 high
22- 2 high
22- 3 low
22- 5 low
22- 7 low
22- 9 low
22-12 low
22-14 low
22-16 low
22-18 low
22-19 high

U
U
U
U
U
U
U
U
U
U

40- 1
40-11
40-12
40-13
40-14
40-15
40-16
40-17
40-18
40-19

low
U952
U952
U952
U952
U952
U952
U952
U952
low

Service - Model 64110A
Table 8-7.
Node

Signature

u 43- 1
U 43- 3
u 43- 5
U 43- 7
u 43- 9
U 43-12
U 43-14
u 43-16
u 43-18
U 43-19

high
low
low
low
low
low
low
low
low
high

u

low
U952
U952
U952
U952
U952
U952
U952
U952
low

U
U
U
U
U
U
U
U
U

47- 1
47-11
47-12
47-13
47-14
47-15
47-16
47-17
47-18
47-19

Signature Analysis Setup A (3 of 3)

8-19

Service - Model 64110A
Table 8-8. Signature Analysis Setup B (1 of 3)
LOOPNAME:

DISPLAY TEST

During the display test the following I/O functions are performed.
I/O data lines are toggled
Delta time interrupt latch and counters are cleared
Interrupt masks are cycled
Rear panel switches are read
The floppy is written to
Even I/O addresses are toggled
Keyboard is read
SETUP NAME: I/O BUS TEST
This setup may be used to troubleshoot the
above
circuitry.
Executing display test and with keyboard buffer A3U25 removed,
set switches as follows:
HPIB addr 0
Boot source PV
Term/Mod jumper JI0 to Term
Hardware configuration jumpers-none installed
Mainframe set to normal (non-master controller)
ST/SP/START: A3TP5, rising edge (MEM SA LATCH)
QUAL/STOP: A3TP5, falling edge (MEM SA LATCH)
CLOCK: A3TP7, rising edge (LBIOSB)

Vh

=

8-20

8oCO

Service - Model 64110A
Table 8-8.

Signature Analysis Setup B (2 of 3)

Node

Signature

Node

U 11- 5
U 11- 7
U 11- 9
U 11-12
U 11-14
U 11-16
U 11-lB

OOOC
3BA9
HFC7
UAHB
UAH5
7A6p

U 24- 2
U 24- 5
U 24- 6
U 24- 9
U 24-12
U 24-15
U 24-16
U 24-19

U 12- 9
U 12-10
U 12-12
U 12-15
U 13- 4
U 13- 5
U 13- 6
U 13- 7
U 13- B
U 13- 9
U 13-11
U 13-12
u 13-13
U 13-14
U 13-15
U 13-16

BOC9
BOC1
high

UAH9

Signature

u6cc
7c65

B971
U1H9
AUA9
7ACP
UB35
96u3

U 26- 9 80C1

high

U 27-14 80cc

UAHB

U
U
U
U
U

3BA9
UAH5
HFC7
7A6p

BOC9

28- 7 80e2
28-10 7A66
28-13 high

2B-14 high
2B-15 80e8

80C9
7A6p
HFC7
UAH5

U 30- 3 Boe8
U 30- 6 BoeB

UAH8

U 35- 6 80ee
U 35- B 0000

3BA9

U 34- 1

0002

U 15- 3 oooe
U 15-17 oooe
U 17- 5 Boca
U 17- B Boce
U 17- 9 oooe
U 20- 3 80e2

8-21

Service - Model 64110A
Table 8-8.
Node

Signature

U 40- 2
U 40- 3
U 40- 4
U 40- 5
U 40- 6
U 40- 7
U 40- 8
U 40- 9
U 40-11
U 40-12
u 40-13
u 40-14
u 40-15
u 40-16
u 40-17
u 40-18

3839
952H
F644
6H5A
c4C9
6AFO

F1UU
1792
9722
414u
PA70
3409
PHPA
46u4
159H
c889

u 41- 5 80co
u 47- 2
u 47- 3
u 47- 4
u 47- 5
u 47- 6
u 47- 7
u 47- 8
u 47- 9
U 47-11
U 47-12
U 47-13
U 47-14
U 47-15
U 47-16
U 47-17
U 47-18

PA4F
P57c
5HU1
545C
6A37
2H32
0187
c69U
362U
8137
AH82
PA87
H4pc
HH41
65FC
6AUF

U 58- 4 oooc
U 58- 5 80cc

8-22

Signature Analysis Setup B (3 of 3)

Service - Model 64110A
Table 8-9.
LOOPNAME:

Signature Analysis Setup C (1 of 3)

PV MENU I/O WRITE

During the test, the following I/O writes are performed:
Cycle interrupt masks
Bank switching, slot select
PHI register addresses
Beeper
SETUP NAME:

PV MENU I/O WRITE TEST

The setup allows the troubleshooting of the above I/O circuitry
and I/O busses.
Executing PV menu I/O write test
ST/SP/START: A3TP5, rising edge (MEM SA LATCH)
QUAL/STOP: A3TP5, falling edge (MEM SA LATCH)
CLOCK: A3TP7, rising edge (LBIOSB)
VH = UF8H

8-23

Service - Model 64110A
Table 8-9. Signature Analysis Setup C (2 of 3)
Node

Signature

Node Signature

U 11- 5
U 11- 7
U 11- 9
U 11-12
U 11-14
U 11-16
U 11-18

0001
550A
7720
PFH1
7842
PAH4
9296

U 24- 2
U 24- 5
U 24- 6
U 24- 9
U 24-12
U 24-15
U 24-16
U 24-19

U 12- 9 7P47
U 12-10 0605
U 12-12 9493
U 12-15 high
U 13- 4
U 13- 5
U 13- 6
U 13- 7
U 13- 8
U 13- 9
U 13-11
U 13-12
U 13-13
U 13-14
U 13-15
U 13-16

PFH1
550A
7842
7720
PAH4
9296
9296
PAH4
7720
7842
550A
PFH1

U 15- 3 0001
U 17- 8 UF8F
U 17- 9 0001
U 18- 8 UF8F

8-24

2487
09A3
23CA
A968
C4U2
135F
990A
2U2U

U 26- 5 high
U 27-14 UF8F
U 28- 7
U 28-10
U 28-13
U 28-14
U 28-15

high

UF8H
high
high

105F

U 30- 6 105F
U 34- 4 0000
U 34-13 UF8F
U 35- 6 7P47
U 35- 8 0000
U 37- 3 105F
U 38- 2
U 38- 7
U 38-11
U 38-15

P4C7
FCHC
4c4F
2HH8

U 40U 40U 40U 40U 40U 40-

69P5
52H1
26c9
4774
COHU
1347

2
3
4
5
6
7

Service - Model 64110A
Table 8-9.

Signature Analysis Setup C (3 of 3)

Signature

Node

U 41- 9 high
U 41-10 0000
U
U
U
U
U
U
U
U

2
3
4
5
6
7
8
9

9HHH
u83A
U9P8
07Cl
774A
64HH
762A
62HA

U 54- 2
U 54- 5
U 54- 6
U 54- 9
U 54-12
U 54-15
U 54-16
U 54-19

OPPU
FHU8
PCPU
9P3P
6HF9
657C
A9B7
FPUA

U
U
U
U
U
U

73- 6
73-11
73-12
73-13
73-14
73-15

6150
UF8H
UF8H
UFBH
UFBH
UFBH

U
U
U
U
U
U

75- 1
75- 4
75- 9
75-10
75-11
75-12

04C7
UFBH
7THP
C924
HP59
PF2P

On

4747474747474747-

A1.0 Mini and RS232

U 63- 2 4c4F
U 63- 3 low

8-25

Service - Model 64110A
Table 8-10.
LOOPNAME:

Signature Analysis Setup D (1 of 2)

DISPLAY TEST

Included in the display test is
signatures on the keyboard buffer.
SETUP NAME:

the

software

necessary

to

take

KEYBOARD BUFFER TEST

If the keyboard buffer or I/O bus transceivers fail, this test can be
used to isolate the failure. When in this setup, the low priority
interrupts are disabled so the keyboard interrupt routine is not called. Keys with alternate l's and O's are pressed to provide the stimulous.
Executing display test
LIRL jumper J9 to test
Auto-reset jumper J6 to test
Keyboard RAM A3U9 removed
Press dash key and take signatures
Press return key and take signatures
ST/SP/START: A3TP5, rising edge (MEM SA LATCH)
QUAL/STOP: A3TP5, falling edge (MEM SA LATCH)
CLOCK: A3TP18, rising edge (LRDKYBD)
Vb

8-26

= 0001

Service - Model 64110A
Table 8-10.

Signature Analysis Setup D (2 of 2)

With [RETURN]
Depressed

With Dash Key
Depressed

Node

Signature

Node

Signature

U 10- 3
U 10- 4
U 10- 5
U 10- 6
U 10- 9
U 10-10
U 10-11

0001
0000
0001
0001
0001
0000
0000

U
U
U
U
U
U
U

10- 3
10- 4
10- 5
10- 6
10- 9
10-10
10-11

0000
0001
0000
0001
0000
0000
0001

U
U
U
U
U
U
U
U

0000
0001
0001
0001
0001
0000
0001
0001

U
U
U
U
U
U
U
U

25- 3
25- 5
25- 7
25- 9
25-12
25-14
25-16
25-18

0001
0001
0000
0001
0000
0001
0000
0000

25- 3
25- 5
25- 7
25- 9
25-12
25-14
25-16
25-18

U 33- 9 0001

U 33- 9 0001

U
U
U
U
U
U
U
U

U
U
U
U
U
U
U
U

40-11
40-12
40-13
40-14
40-15
40-16
40-17
40-18

0000
0001
0000
0000
0001
0000
0000
0000

40-11
40-12
40-13
40-14
40-15
40-16
40-17
40-18

0001
0000
0001
0000
0000
0001
0001
0000

8-27

Service - Model 64110A
Table 8-11.
LOOPNAME:

Signature Analysis Setup E (1 of 3)

KEYBOARD FREERUN

This is a hardware loop in which the keyboard circuitry is allowed to
freerun.
The asynchronous operations of the CPU servicing the keyboard interrupts and the pressing of a key are disabled by moving the
jumper in A3XUl to the test position. All locations in the keyboard
status RAM are written high and then low to allow checking of the RAM.
SETUP NAME:

KEYBOARD FREERUN

Keyboard freerun causes a unique signature to be generated on the
HKYDET line for each key pressed. A failure in the keyboard scanning
circuitry may be isolated using this setup.
Move keyboard freerun jumper A3XUl to test
Move the auto reset enable jumper A3J6 to test
ST/SP/START: A3TP17, rising edge (HKA7)
QUAL/STOP: A3TP17 , rising edge (HKA7)
CLOCK: A3TP19, rising edge (LHSYN)
Vh

8-28

= 8P54

Service - Model 64110A
Table 8-11.
Node

Signature

U 9- 6

65P1

U 10- 3
u 10- 4
u 10- 5
U 10- 6
U 10- 9
U 10-10
U 10-11

0863
HH53
H10F
3A9A
2946
F61C
0108

Signature Analysis Setup E (2 of 3)

Keyboard scan circuitry on
the A3 cpu/ro board.

U 15- 9 FCF2
U 20-11

71CC

U 33- 5 CU1U
U 33- 6 314c
U 33- 9 65P1
U
U
U
U
U
U
U
U

1- 7
1- 9
1-10
1-11
1-12
1-13
1-14
1-15

14H1
2603
OC2P
H9UH

U
U
U
U
U
U
U
U

2- 7
2- 9
2-10
2-11
2-12
2-13
2-14
2-15

9UH4
9658
OP9F
82H3
462F
09HF
U6H6
067U

OFPO
A51H
3AFP

Keyboard A4 multiplexers and
demultiplexers.

F7UF

Keyboard A4 comparator rcs.
U
U
U
U
U
U
U
U

9- 1
9- 2
9- 3
9- 4
9-12
9-13
9-14
9-15

F878
1180
80F8
882C
1180
80F8
1180
1180

SK8 depressed
[RESET] depressed
[BACK SPACE] depressed
[I] depressed
[PREVo PAGE] depressed
[RETURN] depressed
[NEXT PAGE] depressed
[DELETE CHAR] depressed

8-29

Service - Model 64110A
Table 8-11.

Signature Analysis Setup E (3 of 3)

The following signatures are taken on the HKYDET line A3XU1 pin
15 or A4u3 pin 5. A unique signature applies to each key
depressed.
Key
Pressed
SKi
SK2
SK3
SK4
SK5
SK6
SK7
SK8
CLR LINE
RECALL
CAPS LOC
RESET
1
2
3
4
5
6
7
8
9
0
DASH
CARROT

\

BACK SPACE
INSERT CHAR
DELETE CHAR
TAB
Q

W
E
R
T
y

U
I
0

P

8-30

Signature
84uu
F84u
47F8
047F
2160
0216
3021
UA30
4A3A
U4A3
UU4A
4uu4
7CF5
87CF
887C
7887
H788
lH78
CU17
HCUl
6HCU
46HC
146H
P146
AP14
5APl
A026
FA02
4Buc
A4Bu
F307
FF30
2FF3
P2FF
6P2F
16p2
516p
FFPF
UFFP

Key
Pressed
@

[

UNDERSCORE
ROLL UP
UP ARROW
NEXT PAGE
CNTL
A
S
D
F
G

H
J

K
L
;
:

]

RETURN
LEFT ARROW
RIGHT ARROW
LEFT SHIFT
Z
X

C
V
B
N
M

,

.

/

RIGHT SHIFT
ROLL DOWN
DOWN ARROW
PREV PAGE
SPACE BAR

Signature
P3F8
OP3F
70P3
H70P
6H70
A6H7
077P
3077
ACUA
2ACU
H2AC
AH2A
FAH2
8AA4
CH2F
3CH2
C3CH
8C3C
o8C3
608c
F608
CF60
UAlH
A8UF
3ABU
43AB

FAOU
2FAO
F719
BF71
7BF7
H7BF

5H7B
95H7
U95H
FU95
lFU9
7190

Service - Model 64110A
Table 8-12.
LOOPNAME:

Signature Analysis Setup F (1 of 3)

PV MENU I/O READ TEST

A read of the RS232 switch settings, rear panel switch settings.
and
master or non-master controller is done during the I/O read test. The
switch settings are output to the display in the following format.
I/O READ TEST

ADDR=XX

BOOT=XX

M=X RS232=XXXXXXXXX

HC=XX

ADDR is the HPIB address 00 to 1F as set by rear panel switches.
BOOT is the boot source as set by the rear panel switches.
00
01
10
11

=
=
=
=

System bus
Local mass storage talk only
Local mass storage addressable
Performance Verification

M is l=master controller, O=normal (non-master controller)
RS232 switch settings are:
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit

O•••. A3J10
1. ... not used

2 •... A10U55
3 •••. A10U55
4 .••. A10U55
5 •••. A10U55
6 •.•. A10U55
7 •••. A10U55

s6
S5
s4
S3
S2
Sl

0 = TERM,
always = 1
0 = closed,
0 = closed,
0 = closed,
0 = closed,
0 = closed,
0 = closed,

1 = MOD

1 = open
1 = open

1
1
1
1

=
=
=
=

open
open
open
open

HC are the hardware configuration jumpers, not used at this time.
SETUP NAME:

PV MENU I/O READ TEST

By setting the switches such that all zeros should be read and then so
all ones should be read, the bit or bits that are in error may by
traced through the circuitry to find the failed component.
Executing I/O read test
No hardware configuration jumpers installed
ST/SP/START: A3TP5, rising edge (MEM SA LATCH)
QUAL/STOP: A3TP5, falling edge (MEM SA LATCH)
CLOCK: A3TP7, rising edge (LB10SB)
Vb

= 0007

8-31

Service - Model 64110A
Table 8-12.

Signature Analysis Setup F (2 of 3)

Signature

Node Signature

Node
U 11- 5
U 11- 7
U 11- 9
U 11-12
U 11-14
U 11-15
U 11-16
U 11-18

0007
0003
0004
0006
0001
0007
0001
0004

U 12- 9
U 12-10
U 12-12
U 12-15

0006
high
0007
high

U 13- 4
U 13- 5
U 13- 6
U 13- 7
U 13- 8
U 13- 9
U 13-11
U 13-12
U 13-13
U 13-14
U 13-15
U 13-16

0006
0003
0001
0004
0001
0004
0004
0001
0004
0001
0003
0006

U 15- 3
U 15-17

0007
0007

U 17- 5
U 17- 8
U 17- 9

0007
0000
0007

U 27-14

0000

U
U
U
U
U

28- 7 high
28-10 0007
28-13 high
28-14 0003
28-15 0005

U 30- 3
U 30- 6

8-32

0005
0005

U 34- 4
U 34-13

0000
0000

U 35- 6
U 35- 8

0004
0004

Switch settings
HPIB address lF
Boot source-PV
RS232 switches AlOU5-open
TERM/MOD jumper A3J1-MOD
Master controller
U
U
U
U
U
U
U
U
U
U

22- 1
22- 3
22- 5
22- 7
22- 9
22-12
22-14
22-16
22-18
22-19

0005
0007
0007
0007
0007
0007
0007
0007
0007
0005

U
U
U
U
U
U
U
U
U
U

40- 1
40-11
40-12
40-13
40-14
40-15
40-16
40-17
40-18
40-19

0007
0000
0000
0000
0000
0000
0000
0000
0000
0004

U
U
U
U
U
U
U
11
U
U

43- 1
43- 3
43- 5
43- 7
43- 9
43-12
43-14
43-16
43-18
43-19

0005
0007
0007
0007
0007
0007
0007
0007
0007
0005

Service - Model 64110A
Table 8-12.

Signature Analysis Setup F (3 of 3)

Node

Signature

Node

Signature

u

47- 1

0007

U 47-12
U 47-13
u 47-14
u 47-15
u 47-16
u 47-17
u 47-18
u 47-19

0000
0000
0000
0000
0000
0000
0000
0004

U 43- 1
u 43- 3
u 43- 5
u 43- 7
u 43- 9
u 43-12
U 43-14
u 43-16
u 43-18
u 43-19

0005
0007
0007
0007
0005
0005
0007
0007
0007
0005

u 47- 1
u 47-11

0007
0006
0002
0004
0004
0004
0004
0004
0004
0004

u 47-11 0000

Switch settings
HP-IB address-OO
Boot source-System Bus
See note below.
RS232 switches AlOU5-closed
TERM/MOD jumper A3J1-TERM
Normal (non-master controller)
U
U
U
U
U
U
U
U
U
U

22- 1 high
22- 3 0005
22- 5 0005
22- 7 0007
22- 9 0005
22-12 0005
22-14 0005
22-16 0005
22-18 0005
22-19 high

U
U
U
U
U
U
U
U
U
U

40- 1
40-11
40-12
40-13
40-14
40-15
40-16
40-17
40-18
40-19

U 47-12
U 47-13
u 47-14
u 47-15
u 47-16
u 47-17
u 47-18
u 47-19

NOTE: Change switches from PV to
system bus after test is
executing.

0007
0002
0002
0002
0002
0002
0000
0002
0002
0004

8-33

Service - Model 64110A
Table 8-13.
LOOPNAME:

Signature Analysis Setup G (1 of 2)

PV MENU SYSTEM BUS TEST

During the test, the PHI chip is taken off line and the internal registers of the PHI chip are written to and read from. Note: The failure code given should the test fail does not present usable information. If the test fails, it may take up to two minutes to complete.
SETUP NAME:

PV MENU SYSTEM BUS TEST

Stimulus is provided for troubleshooting the I/O bus transceivers, PHI
control circuitry, and the functioning of most of the PHI chip itself.
Executing PV menu system bus test
ST/SP/START: A3TP5, rising edge (MEM SA LATCH)
QUAL/STOP: A3TP5, falling edge (MEM SA LATCH)
CLOCK: A3TP7, rising edge (LBIOSB)
Vb = 9A4A
Node

Signature

Node

Signature

U 11- 5
U 11- 7
U 11- 9
U 11-12
U 11-14
U 11-15
U 11-16
U 11-18

9029
452U
HU65
9A4c
0001
9029
0001
0000

U 12- 9
U 12-10
U 12-12
U 12-13
U 12-15

9A4c
high
9A4A
high
high

U 13- 4
U 13- 5
U 13- 6
U 13- 7
U 13- 8
U 13-.9
U 13-11
U 13-12
U 13-13
U 13-14
U 13-15
U 13-16

9A4c
452U
0001
HU65
0001
0000
0000
0001
HU65
0001
452U
9A4c

8-34

Service - Model 64110A
Table 8-13.
Node

Signature

U 15- 3 9029
U 15-17 9029
U 17- 5 9A4A
U 17- 8 OA63
U 17- 9 9029
U 18- 8 OA63
U 27-14 OA63
U 28- 7
U 28-10
U 28-13
U 28-14
U 28-15

high

9A4A
high
high

0001

U 30- 4 0001
U 30- 5 HU65
U 30- 6 HU64
U 34- 4 0000
U 34-13 OA63
U 35- 6 9A4c
U 35- 8 0000
U 37- 3 HU64
U 37- 6 452U
U 38- 2
U 38- 7
U 38-11
U 38-15

07A8
17FA
high

Signature Analysis Setup G (2 of 2)
Node

Signature

U 40- 2
U 40- 3
U 40- 4
U 40- 5
U 40- 6
U 40- 7
U 40- 8
U 40- 9
U 40-11
U 40-12
U 40-13
U 40-14
U 40-15
U 40-16
U 40-17
U 40-18

61U6
574F
8cp6
Al8F
H32F
5549
4PUH
4F66
H62F
H4c7
FU03
4966
3CF6
11AF
FH06
UCCF

U 47- 2
U 47- 3
U 47- 4
U 47- 5
U 47- 6
U 47- 7
U 47- 8
U 47- 9
U 47-11
U 47-12
U 47-13
U 47-14
U 47-15
U 47-16
U 47-17
U 47-18

Acc6
Acc6
3C9P
3C9P
3C9P
3Al2
98A3
C415
2P5U
02P9
A058
AlH4
AlH4
AlH4
31UF
31UF

2427
U 63- 2 high
U 63- 3 low

8-35

Service - Model 64110A
Table 8-14.

Signature Analysis Setup H (1 of 2)

LOOPNAME: PV MENU RS232 TEST
The mainframe has loopback relays to loop back control and data signals from the output of the USART chip through the voltage translators
and back to the receive ports. SA stimulus is provided in this testing loop.
NOTE

The failure code given, should the test fail,
does not present usable information. If the test
fails, it may take up to 2 minutes to complete.
SETUP NAME:

PV MENU RS232 TEST

A failure in the RS232 circuitry may be isolated using this setup.
Executing PV menu RS232 test
Top switch of S2 (AlOU60) in closed position
RS232 switches Sl (AlOU55) in closed position
ST/SP/START: A3TP5, rising edge (MEM SA LATCH)
QUAL/STOP: A3TP5, falling edge (MEM SA LATCH)
CLOCK: A3TP7, rising edge (LBIOSB)
VH

= OOUP
Node

Signature

Node

Signature

U 11- 5
U 11- 7
U 11- 9
U 11-12
U 11-14
U 11-15
U 11-16
U 11-18

0019
00p6
007P

U 13- 4
U 13- 5
U 13- 6
U 13- 7
U 13- 8
U 13- 9
U 13-11
U 13-12
U 13-13
U 13-14
U 13-15
U 13-16

OOUU
00p6
0003
007P
0065
001A
001A
0065
007P
0003
00p6

U 12-

0003
0019
0065
001A

9 OOUU

U 12-10
U 12-12
U 12-15

8-36

oouu

high
OOUP
high

oouu

Service - Model 64110A
Table 8-14.

Signature Analysis Setup H (2 of 2)
Signature

Signature

Node

U 15- 3
U 15-17

0019
0019

ON AlO MINI AND RS232

U 17- 5
U 17- 8
U 17- 9

OOUP
00P7
0019

U 27-14

00P7

U
U
U
U
U

high
OOUF
009A
00p6
OOro

Node

28- 7
28-10
28-13
28-14
28-15

U 30- 3 high
U 34- 4
U 34-13

0000
00P7

U 35- 6
U 35- 8

oouu

U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U

0059
0039
0019
0019
0019
0019
005U
0019
OOUU
00C9

40- 2
40- 3
40- 4
40- 5
40- 6
40- 7
40- 8
40- 9
40-11
40-12
40-13
40-14
40-15
40-16
40-17
40-18

0018

U
U
U
U
U
U
U
U

43-11
43-12
43-13
43-14
43-15
43-16
43-17
43-18

0041
0021
0001
0001
0001
0001
0047
0001

U
U
U
U
U
U
U
U

57- 3
57-14
57-15
57-17
57-19
57-22
57-23
57-24

003U
00F1
0000
003U
OOUP
001U
003U
001U

U
U
U
U
U
U
U
U

62- 3
62- 5
62- 7
62- 9
62-12
62-14
63- 2
63- 3

0081
009A
00F1
low
00p6
00p6
0081
0000

oouu
oouu
oouu
OOUU
OOHU
OOCU

8-37

Service - Model 64110A
8-48.

POWER SUPPLY BLOCK DESCRIPTION.
ASSEMBLY Al.

8-49. The relationships between the power supply functional areas are
shown on figure 8-2.
8-50. The Model 64110A uses a switching power supply which provides
all other circuits with the following regulated voltages and signals:
+12 volt main supply
+12 volt display driver supply (12VDD)
-12 volt supply
-5 volt supply
-5.2 volt supply
-3.25 volt supply
LPOP, Low power-on pulse
LIR15, Power failure interrupt
LINSYN, Line synchronization
8-51. The power supply contains an overcurrent shutdown, individual
overcurrent protection on the -3.25 and -5.2 V supplies, RAM protect,
a 40 KHz clock, and control power circuits.
8-52.

PRIMARY POWER BLOCK DESCRIPTION.

ASSEMBLY AlAl.

8-53. Line voltage, either 110 or 220 V, is supplied through the AC
line filter, fuse F1, and the power on/off switch Sl, to the line
voltage selector AS2.
8-54. The line voltage selector does two things. First, it determines
if there will be straight through rectification at 220 V, or rectification with voltage doubling at 110 V. This maintains approximately
160 VDC, switched at 40 kHz, on the primary of the power transformer
A2T1. Second, it ensures the primary of T4 sees only 110 V for either
line supply voltage.
8-55.

CONTROL-POWER BLOCK DESCRIPTION.
ON ASSEMBLY AlAl.

8-56. The power supply control circuitry provides supply and reference power for use in the power supply. Control-power is the first to
come up and consists of +12VCONT, +5VREF, and +5VCONT. The power is
8-38 PS

Service - Model 64110A
continuously available
voltage selector.
8-57.

whenever line voltage is supplied to the line

TEST POINTS AND 40 kHz CLOCK BLOCK DESCRIPTION.
ON ASSEMBLY AlAl.

8-58. Test points VCONTIN and CONTRET provide an access point to
apply external power to the control power circuits. This will allow
generation of control power without requiring main system power.
The
40 kHz clock is generated by two one-shot multivibrators in U5 and
is used to set the base frequency of the regulator circuits for the
+5, -5.2 and -3.25 V supplies.
8-59.

OVERPOWER PROTECTION BLOCK DESCRIPTION.
ON ASSEMBLY AlAl.

8-60. The overpower protection circuit must sense current in order to
make a determination of the supply power consumption. The current
sensor is transformer T3, which has its primary wired in series with
the primary of the power transformer. This current is input to the
overpower protection circuit u6, which produces a SHUTDOWN signal and
turns on the overpower indicator DS1, when an overpower condition is
reached. The SHUTDOWN signal is wire ORed with the other shutdown
signals to the +5 V regulator U2.

8-61. +5 VOLT SUPPLY BLOCK DESCRIPTION.
ON ASSEMBLY AlA2.
8-62. This is the dominant supply. Its regulator controls the power
to the primary of the power transformer. Therefore, the other lines
will go down if the +5 V line goes down.
8-63. The first of four transformer primaries supplies power directly
to the fullwave rectifier CR8 which rectifies it to +5 VDC. The +5 V
line is filtered by L4 and C10, 11, 23-25 and then regulated at +5 V
(+-5%) by regulator AlU2.
8-64. The regulator senses the line level and compares it to the +5VREF level from the control power circuits. If the level is not correct, the regulator will increase or decrease the duty cycle of the
switching transistors AlQ1 and AlQ2 in the primary of the power transformer.
8-65. The regulator circuit AlU2, combines with the overvoltage protection circuits of the supply lines to shutdown the supply in an
overvoltage situation. This is accomplished by wire ORing the SHUTDOWN signals of the overvoltage protection circuits to the dead time
control comparator input of the +5 V regulator AlU2. When a SHUTDOWN
signal is applied to this input, the regUlator will turn both switching transistors A1Q1 and AlQ2 off, thus, no power will be supplied to
the primary of the power transformer.
8-39 PS

Service - Model 64110A
8-66.

+-12 VOLT SUPPLY BLOCK DESCRIPTION.
ON ASSEMBLY AlA2.

8-67. The fourth secondary supplies fullwave rectifier AlCR1, which
supplies approximately 20 VDC to the linear regulators A2VR1, 2 and 3,
producing +12 V, -12 V, and +12 VDD, regulated at +-5%. The +12 VDD
line supplies the display driver circuits, and the +12 V and -12 V
supplies are general purpose supplies for all other circuits.
8-68.

RAM PROTECT BLOCK DESCRIPTION.
ON ASSEMBLY AlA2.

8-69. The RAM protect circuit u6 is used to detect the presence of
the -5.2 V supply. The -5.2 V supply must be present at any time the
+5 and +12 V supplies are supplied to RAM or damage may result to the
RAM. If the -5.2 V supply is not present, the RAM protect indication
DS3, is lighted and a SHUTDOWN signal is sent to the +5 V regulation
circui t AlA2.
8-70.

-3.25 VOLT SUPPLY BLOCK DESCRIPTION.
ON ASSEMBLY AlA3.

8-71. The second secondary supplies power through switching transistor Q3, to the -3.25V transformer T1. Rectifier CR2, rectifies the
voltage from the -3.25 V transformer which is filtered by L1 and C1720.
The regulator circuit U5 senses the voltage level on the -3.25 V
line, monitors the voltage drop across R37 for current levels through
the -3.25 V line, compares the levels with the +5VREF and varies the
duty cycle of the switching transistor Q3 to maintain -3.25 V (+-3%).
8-72. The over current protection circuit A2U5 senses the -3.25 V and
compares it with +5VREF. When an overcurrent condition exists, it
lights the -3.25 V overvoltage indicator A2DS2, and sends a SHUTDOWN
signal to the +5 V regulator circuit AlU3.
8-73.

-5.2 VOLT SUPPLY BLOCK DESCRIPTION.
ON ASSEMBLY AlA3.

8-74. The -5.2 V supply operates the same as the -3.25 V supply and
is maintained at -5.2 V (+-5%). It receives its power from the third
power transformer secondary through switching transistor Q4, the -5.2
V transformer T2, the fullwave rectifier CR5, and filter circuit L2
and C21-23, 28. The -5.2 V power is sensed by R40 and regulator U2.
8-75. Overcurrent protection is provided by A2U4 which lights the
-5.2 V overcurrent indicator A2DS1, and sends a SHUTDOWN signal to
the +5 V regulator AlU2.

8-40 PS

Service - Model 64110A
8-76.

LPOP, LIR15, AND LINE SYNC BLOCK DESCRIPTION.
ON ASSEMBLY AlA2.

8-77. The power supply produces three signals to be used by the other
circuits; LPOP, LIR15 and LINSYN. LPOP is generated when power is
first turned on and whenever there is a power failure on the AC line
or +5 V supply. This signal goes to the CPU and I/O section where it
initializes the CPU and I/O circuits.
8-78. LIR15 is generated when line voltage drops below a set value
and goes to the CPU/IO and display driver sections. It blanks the
display and aborts any writes to the floppies. LINSYN is a TTL signal
generated from the line frequency and goes to the CPU and I/O section
where it is used in the auto-reset circuitry.

8-41/(8-42 blank) PS

Service - Model 64110A
AIA2, 64110-66513,+12V,-12V, 12V DISPLAY DRIVER ,+5V

--- PRIMARY
I AlAI, 64110-66511,
POWER

I

1

1

1

~

--~ ----l--

...

--

~

'D

+SV REF

eRB

l

J'

'D

---------------------------------------------

220
RECTIFIER/115
RECTIFIER &
OoUBLEfl

I

--

--

--

--

AIA3, 64110-66514, -3.25V, -5.2V

"7

,---------------------------------I

rt--t---1
I
I

1
I
I

-160

I

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IJ- ~:!"?~_Jr
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I

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i-L-i

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i-04-j

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BRIDGE

H

n

1
1-

--

I

t-=-?--9-

REGULATIONS

>US

>U4

R40

U6

V. SENSE

--

--

I
1

I

.1
OVER
VOLTAGE
PROTECT
-S.2V

J:

DSl
/

IRAM

1

1M
CLOCK

OVER
VOLTAGE [ } : DS2
PROTECT
-3.25V
~

+sv
REF

u~

3. 25

I

PROTECT
OIFF.5/
-S.2V

[j.:

CR3

~+5V

I
_I

-5. 2V

I

I
I
[
~

~

+1 2V
+1 2V DISPLAY DRIVER
o DISPLAY DRIVER

~GN
CRl

--

~

--

--

--

--

--

-1 2V

1

,..-.-

SHUTDOWN
I. SENSE

V.SENSE

OVERPOWER
PROTECTION
CIRCUIT
U6

[1.:

CLK
CR9

!

40 KHZ
CLOCK
US

T4

t--,........, BRIDGE
CR6

PWR. SUP.
CONTROL
(CONTINUOUS)

--

I

1

--

-LINEAR

o CoNTR~

--

I

J

'(

~

VCoNTIN

~m

1

1
R37

13

COMMON

1

+5V
REF

l

--

V. SENSE
CLOCK

+5V REF

CRS

I

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1. LIMIT

I

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'[J

1______ ----------------------------

I
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I

-I

"-B,"

oJ'

II~

I
I
I
I
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--

/~

+5V REF

+160

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~

U2

V. SENSE
:HI nWN
C1 JCK

+sv
+SE NSE
-SE NSE

I

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<:1=1-

C10,ll,23-25

1

1

LINE
VOLTAGE
SELECTOR
S2

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I

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POWER FAIL
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Figure 8-2.
Power Supply Block Diagram

8-43/(8-44 blank)

Service - Model 64110A
8-79.

POWER SUPPLY SCHEMATIC DESCRIPTION.
ASSEMBLY Al.

8-80.

General.

8-81. The power supply assembly schematic functionally corresponds to
the power supply block diagram (figure 8-2). The four boards which
make up the power supply are shown on the schematic, service sheet
number 1 (figure 8-3).

Description

Ref
Des

64110Number

Location

Primary

AlAl

66511

Top of chassis

+5, +-12 Volt

AlA2

66513

Middle of chassis

-3.25, -5.2 Volt

AlA3

66514

Bottom of chassis

Interconnect

AlA4

66512

Side of chassis

8-82. The line voltage is fed through the AC line filter, fuse, and
power switch. Capacitor C27 provides additional RFI filtering. Thermistor RT3 nominally keeps any peak in-rush currents below 100 amperes
to protect the power switch. The voltage select switch has two positions selecting 110 or 220 volt input.
8-83. The line selector switch effectively reconnects the input
bridge from full wave configuration in the 220 mode to a half wave
doubler configuration in the 110 mode. The line filter is a modular
unit which starts to provide effective filtering at frequencies above
150KHz.
8-84.

PRIMARY SUPPLY SCHEMATIC DESCRIPTION.
ASSEMBLY AlAl.

8-85. Assembly AlAl is the primary power supply board.
It sets up
correct primary voltages and supplies the current drive to the primaries of A2T1 and T2 through a 40 kHz pulse width modulated switching
network.
8-86. Diode CR4 is a full wave rectifier bridge that supplies power
to the main energy storage capacitors C23 and c24 to develop the primary supplies. Resistors R31 and R32 are 100 k ohm bleeder resistors
for the main capacitors.
8-87. Spark gaps SG1 and SG2 in series with thermistors RT1 and
provide a non-destructive means of catching incorrect strapping on
power supply input. In the event that the supply is connected for
volt operation and plugged into 220 volt main, one or both of
spark gaps will fire and discharge the energy.

RT2
the
110
the

8-45 PS

Service - Model 64110A
8-88. Transformer Tl and C25 are a common mode filter, and c26, C29
and Ll are a CLC filter. Both provide filtering at a lower freqency
than the input modular line filter.
8-89. The main power switching transistors Q3 and Q4 are connected
across the half bridge capacitors C28, C30. The two transistors turn
on alternately, causing current to flow in alternate directions
through the primaries of T2 and A2T1, thus supplying power for the
supplies. The main power transistors have diodes CR5, CR6 across the
collector/emitter junctions to insure the storage energy in any leakage inductance in the primaries of T2 and A2Tl will be returned to the
energy storage network.
8-90. The +5 V supply is regulated by controlling the duty cycle ontime of the 40 kHz switching transistors. Chip U2 monitors the +5 V
supply and compares it to the +5 V reference via the voltage sense
amplifier. The pulse width on output pins 8 and 11 increases as the
voltage differential on the voltage comparitor increases.
The +5 V
reference comes from VR3 on the AlAl primary board. Resistor R16 and
C7 filter noise, and R15 compensates for the input bias current for
the voltage sense amplifier.
The +5 V sense is detected at the
motherboard to help compensate for printed circuit board trace voltage
drops. Ten ohm resistor Rl on the AlA4 interconnect board provides +5
V sense when the supply is removed from the mainframe. Resistor R17
and C8 filter noise and R13 compensates for the input bias current.
8-91. The open collector outputs of U2 turn on and off the darlington
pair devices u4 which cause current to flow in the primaries of T4 and
T5. Transformers T4 and T5 comprise the base drive circuitry for the
power switches Q3 and Q4. The primary windings of T4 and T5 are connected in such a polarity that when primary current is forced to flow
by the darlington switches U4A/BC, the respective power switch base is
driven off. These transformers are actually energy storage elements.
During the time that the drive transistors are turned on, each transformer stores energy which is later released into the secondary when
the darlington switches are turned off. On the primary, components
R27, C19, R28 and c18 form what is called a snubber network to reduce
RF interference problems.
8-92. The other two darlington pair devices u4 are driven by signals
CCl and CC2, Cross Conductor 1 and 2. During heavy load situations
when the switching transistors are on for full duty cycle, stored
charge could keep one switching transistor turned on when the other is
turning on. This would have the effect of shorting the two primary
supplies together thus destroying components. Signals CCl and CC2 keep
one switching transistor turned off until the other is completely
turned off.
8-93. The +5 V current being supplied to the instrument is sensed by
monitoring the voltage across the +5 V inductor A2L4. This voltage is
supplied to the current limit amplifier sense input of U2. When this
voltage becomes large enough, the current limit amplifier of U2 begins
to limit the duty cycle on the +5 V supply. The current limit foldback
point is 33-35 amperes.

8-46 PS

Service - Model b4110A
8-94. Integrated circuits U5A/B are two halves of a monostable multivibrator connected in a loop. It is the 40 kHz clock for the power
supply. The clock is low true with a very short duty cycle. Its frequency of operation is determined by R25 and C17 connected to pin 15
of U5A and R26, C32 connected to pin 7 of U5B.
8-95. Resistor R11 and C5 provide the soft start at power-up. Pin 4
of U2 is the dead time control input. This input controls the maximum
on-time of the output pulse. Until C12 has discharged to approximately
100 mV, the dead time control comparator is limiting the maximum pulse
width, thus causing the pulse width to increase gradually, causing the
supply to come-up in a slower manner.
8-96. Transistors Q2 and Q1 and their passive components form a discrete SCR which latches or triggers when current is sunk through R1 to
ground. This circuit latches whenever sufficient current is sunk
through R1 to ground. The input side of R1 is clamped to 5 volt control supply. The input current is limited by R4 and noise on the input line is filtered by C2.
8-97. Chip U1 and its associated components provide low voltage lockout to U2. Until the 12 volt control power supply is above 11 volts,
it keeps the VCC line to U2 off. If the 12 V control power drops below 10 V, U1 shuts down power to U2. It also resets the dead time control circuitry via RB and CR3 to ensure that if power is being cycled
rapidly, the supply will still come up slowly. Resistors R5, R6 and
R7 set the trip point for U1.

8-9B.

Network R13, R15 and cB provide some input filtering against 40
kHz noise on the error sensing line.
The reference line includes
filtering in the form of R15, R16, and C7 to reduce susceptibility to
noise. Resistors R13 and R15 balance the input bias current and set
up the AC gain.
8-99. Chip U3 is the clock receiver circuit. It is a 311 OP AMP arranged with its passive components R23, R24, R9, and c14 to set up the
clock threshold voltage at 2.5 V. The input of U3 is clocked by the
40 kHz generator U5A/B. The output of U3 is directly across U2 timing
capacitor C12 to provide a discharge path, thus setting the switching
rate of 40 kHz.
8-100.

+5, +-12 VOLT SUPPLY SCHEMATIC DESCRIPTION.
ASSEMBLY AlA2.

8-101. Assembly AlA2 generates +5, +-12, +12 VDD supply voltages along
with LINSYN to the processor. It also generates the LPOP signal which
resets the processor and low line signal LIR15.
8-102. Signal LINSYN input comes from AlT3. In this case, one of the
secondary lines is connected to a resistive voltage divider R17 and
R25 whose output is clamped to ground and to the 12 V control voltage.
That line then becomes one of two inputs to the Schmitt input gate U2C
with the other input held high. The output is then nearly square with
8-47 PS

Service - Model 64110A
a 60 Hz period. The output drives the base of Q2. Transistor Q2 collector is pulled up to 5 volts through R27.
That collector signal
then becomes the LINSYN output.
8-103. Part of the main power transformer T1 is used for generating
the +5 V supply. Diodes CR8, CR19 , CR20 make up a full wave centertapped bridge rectifier. Components L4 and five 1000 uF capacitors,
C10-11 and C23-25, make up the +5 V supply filter. In addition to
conventional components, a pair of diodes CC1 and CC2 are provided in
order to sense potential for cross-conduction and to hold the main
power switching devices off until conduction due to storage time in
the main switches Q1 and Q2 has ceased. These two diodes also have
pull up resistors R32, R33 in order to reduce any storage time problems associated with the darlingtons AlU4A/BCD, which they control.
8-104. Part of the main power transformer T1 is used to generate +12 V
for the display driver, +-12 V supplies for other loads. The supplies
are fed from T1 through a fast recovery bridge rectifier CR1. The +12
VDD supply is separate from the main +12 V output because of the sensitivity of the display driver circuitry to noise. Voltage regulator
VR1 (+12VDD) regulates the +12 V for the display driver. Its filtering
is done through L1, c4 and c6. Diode CR12 and CR13 are placed in the
circuit for reverse polarity protection in case of a short.
8-105. Voltage regulator VR2 regulates the -12 V main supply and its
filtering is done through L2, C5 and C7. Diodes CR14 and CR16 are the
reverse polarity protection diodes. Voltage regulator VR3 regulates
the main +12 V supply. The filter network consist of L3, C8 and C9.
Diodes CR15 and CR17 are the reverse polarity protection diodes for
this circuit. All three outputs are routed to the AlA4 interconnect
board and out to the instrument.
8-106. Chips U5 and u4 are used to sense -3.25 and -5.2 V overvoltage.
IC u6 is used to sense the condition when +5 V is available and -5.2 V
is not. The availability of +5 V without -5.2 V could cause damage to
the RAM circuitry of the peripheral processor memory. Once a shutdown
is activated, a divider network drives the remote activate input to
the shutdown ICs and a LED. The shutdown is then latched and requires
a power-on reset.
8-107. The LED provides a visual indication of the failure mode. The
shutdown signals go to the AlAl board where they shut down the main
switching transistors via the switching regulator AlU2.
The overtemperature thermostats provided in the power supply utilize u4. They
latch u4 in the shutdown mode, thus keeping the supply from turning on
again when it cools. Therefore, LED DS1 indicates either a -5.2 V
shutdown or temperature shutdown.
8-108. Integrated circuit AlU6 is part of the overcurrent detector.
Transformer AlT2 is the over current transformer and is connected in
series with the main power transformer primary of T1. The secondary of
AlT2 contains a full wave bridge AlCR7, and a filter network AlR36 and
C34. In the event that the voltage at pin 2 of AlU6 exceeds the trip
point of 2.6 volts, it will issue a shutdown signal to the AlAl board
and latch itself. In addition, LED AlAlDS1 will come on and stay on
8-48 PS

Service - Model 64110A
indicating that the shut down mode was due to an over power condition.
8-109. LINSYN is a TTL level square wave signal generated by U2C and
Q2 running at line frequency. Chip U2 is driven by line voltage transformed down to CMOS levels by AlT3. Diodes CR3 and CR4 clamp the inputs to the CMOS gate U2 to +12 V and ground to keep line transients
from damaging the IC.
8-110. Signals LPOP and LIR15 are generated through U1 from the AlT3
secondary. Full wave bridge CR2 output is divided and filtered to
drive U1 which provides low-line indication. Whenever the line voltage drops into the low-line region, it sets the RS flip-flop U2A/D.
At power-up, the state of the flip-flop is reset. As long as that is
true, U2B output can not go low until time-out of the input pin 6 of
U2B, which is set by R21 and c16. Therefore, about one second after
+12 V main power supply output is up, pin 4 of U2 will go low. That
low signal will be coupled through C17 and will drive the output of
U3A high for about 70 microseconds which will in turn drive the LPOP
line low for about 70 microseconds.
8-111. The circuit also interlocks the timing between an LIR15 low
true output and any subsequent LPOP signal following restoration of
power. If the input line voltage drops below acceptable limits for a
very brief period of time, the flip-flop will be delayed by about 100
microseconds. Therefore, no LPOP will be delivered any closer to the
LIR15 negative edge than 100 microseconds. That timing is required by
the central processing unit.
8-112. Voltage regulators AlVR1 (+12 V control), VR2 (+5 V control),
and VR3 (+5 V reference), supply the control voltages that enable the
power supply to start-up and shut-down in an orderly way. Regulator
VR3 supplies the precision +5 V reference so that no adjustment for
the +5 V supply is needed. The input for the regulators comes from
AlT3 and a full wave bridge AlCR8. The filter capacitors AlC13, C15,
c16, C35, and C37 provide high frequency stability.
8-113. -3.25, -5.2 VOLT SUPPLY SCHEMATIC DESCRIPTION.
ASSEMBLY AlA3.
8-114. The AlA3 board generates the -3.25 and -5.2 V supplies. The two
supplies are pulse width modulated switching supplies similar to the
+5 V supply. Power for these switching supplies comes from the secondary coils of the +5 V primary transformer A2T1. For this reason, the
+5 V supply must be regulating for a minimum load before the -3.25 and
-5.2 V supplies can regulate.
8-115. The -3.25 volt supply is generated through CR4, A2T1, and the
power switching transistor Q3. Transistor Q3 is a FET power switch.
The FET switch is driven by a 40z kH signal from the pulse width modulator U5 control regulator via Q2 and UlA. The FET switch provides
the power drive to the primary of T1. The secondary of T1 feeds the
-3.25 V supply filter network L1 and C17-20.

8-49 PS

Service - Model 64110A
8-116. The power switch contains a snubber network consisting of c24
and R3B.
Resistor R45 provides turn off stability. Resistor R30
insures the FET is protected in the event that the drive crcuitry is
removed from the board. The -3.25 and -5.2 V outputs are fed through
transformer T1 to the filter network L1, C17-20.
8-117. The -5.2 V supply is set up like the -3.25 V supply.
The
passive components are of different values for the different voltage
outputs of two supplies. The -5.2 V circuit consists of CR5, Q4, T2,
L2, C21-23, C2B. Chip U2 is its control regulator and functions the
same as U5 but have different clocking signals. The timing control is
C11, R24 (for U5) and c6, R17 (for U2). The timing is set up so that
the external clock signal always overrides and provides the reset.
The controller incorporates fold back current limit which is set at
just above 20 amperes. Both controllers use remote sensing to the
output voltage. A separate sense line is brought out to the mother
board distribution bus.

8-11B. Both supplies' modulating regulators have a clock network similar to the +5 V supply. The 40 kHz clock signal from the clock circuitry on the AlA1 primary board overrides and resets the timing capacitors on pin 5 of the regulator ICs to set the pulse width modulated signal at 40 kHz.
8-119. The voltage sense for the voltage sense amplifier for the regulator ICs are remotely sensed at the motherboard. The 10 ohm resistors
A3R43 and A3R44 insure that the supply is still functional in the
event that the supply is removed from the mainframe.
8-120. As in the +5 volt regulator there are some additional capacitors C31 and C32. These capacitors in combination with C30 and C33
provide rejection of 40 kHz noise. Tight tolerance resistors are used
to insure the input reference quality is maintained. Both U2 and U5
have conventional RC compensation networks.
8-121. Components C1, C7-8, C12-14, C29, RB, R14, R42 are simply
filtering for the +12 V control power supply and the +5 V reference supply.

B-50

PS

Service - Model 64110A
8-122. POWER SUPPLY TROUBLESHOOTING.
8-123. Power Supply troubleshooting consists of failure modes and suggested steps to take in troubleshooting. When a failure is isolated
to a block of components, refer to the theory and troubleshoot those
components.

**************************** WARNING **************************

*
*
*
*
*
*
*

Hazardous voltages and charges exist on the power supply.
The main filter capacitors take approximately 2 minutes to
discharge after line power is removed from the supply. Use
tool to discharge the main filter capacitors before servicing.

*
*
*
*
*

*
*

*****************************************************************

8-124. Remove the power supply from the mainframe and install the
power supply test board. It contains minimum loads required to bring
the 12V supplies into full regulation and LED indicators to indicate
operation of the different supplies. Removing the supply from the
mainframe will verify that the failure is with the supply and not with
the mainframe motherboard or boards installed in the frame.
8-125. The AlA2 and AlA3 boards may be extended using the power supply
flexible extender cable. The AlAl board should be left in the supply
frame during troubleshooting because of the hazardous voltages and
charges present on the primary rails.
8-126. FUSE IS BLOWN.
8-127. Line voltage is rectified by AlAlCR4 and filtered to develop
the primary rails.
Shorts in the rectifier or filter components
will cause the fuse to blow.
8-128. AlAlQ3 and 4 are the main switching transistors.
The control
network for these transistors should never turn on both at the same
time. If it does, the primary rails will be shorted together, the
fuse will blow and Q3 and 4 will be destroyed.
8-129. If AlAlQ3 and 4 are found bad, use the troubleshooting outlined
in the 5V supply control circuitry troubleshooting to isolate any
problems there before turning on the supply in a fully functional
mode.
8-130. If the supply fails intermittently under heavy loads where
AlAlQ3 and 4 fail, check the cross conduction diodes AlA2CR19 and 20.
The signals CCl and CC2 are supposed to keep the transistors from
turning on at the same time when stored charge is holding on one of
the transistors.

8-51 PS

Service - Model 64110A
8-131. There are three LED indicators on the AlA2 board and one on the
AlA2 board to indicate shutdown modes of the power supply.
8-132. LED AlAlDSl ON.
8-133. This LED indicates that the power supply was shut down due to
an overpower condition. The possible reasons for this and suggested
troubleshooting steps are listed below.
8-134. AlAlQ3 and 4 turned on at the same time. Use the troubleshooting outlined in the 5V regulator control circuitry troubleshooting to
isolate possible problems there.
8-135. A short on circuitry on the secondaries of AlA2Tl, AlA3Tl or T2
may be translated back through the transformers and cause the shutdown
due to overpower. The secondary windings of AlA2Tl connect via cables
and connectors. These may be disconnected to isolate which of the
secondaries is causing the heavy load. Disconnecing AlA3Jl will cause
the RAM protect shutdown to shut down the supply.
Disconnecting
AlA2Jl will remove power from the plus and minus 12V and 12V display
supplies. Check for shorted components.
8-136. LED AlA2DSl ON.
8-137. The LED indicates either a -5.2V overvoltage or a thermal shutdown or an overvoltage of the 5V reference volatage. If
either
of
the thermal switches close due to an overtemperature condition, AlA2U4
is used to latch the shutdown so that the supply remains shutdown until power is cycled even if the supply has cooled. If the -5.2V supply becomes more negative than -6.47 volts, or the 5V ref becomes more
positive than 6.27 volts, u4 issues a shutdown signal, lights LED DSI
and latches itself.
8-138. Disconnect AlA2J2 and check the thermal switches.
8-139. Remove AlA2U4 to disable the shutdown. Check the -5.2V and 5V
ref supplies to isolate which is failing. The 5V ref supply is a
voltage regulator IC located on the AlAl board.
Use the regulator
control troubleshooting to troubleshoot the -5.2 volt supply.
8-140. LED AIA2DS2 ON.
8-141. The LED indicates a -3.25 overvoltage or 5V ref. overvoltage
shutdown.
If the -3.25V supply becomes more negative than -4.2 volts
or if the 5V ref. supply becomes more positive than 6.0 volts, AlA2U5
issues a shutdown signal, lights LED AlA2DS2, and latches itself to
keep the supply shut down.
8-142. Remove AlA2U5 to
ref supplies to isolate
voltage regulator IC
control troubleshooting
8-52 PS

disable the shutdown. Check the -3.25V and 5V
which is failing. The 5V ref supply is a
located on the AlAl board. Use the regulator
to troubleshoot the -3.25 volt supply.

Service - Model 64110A
8-143. LED AlA2DS3 ON.
8-144. The LED indicates a RAM protect shutdown. If the 5V supply is
present without the -5.2 supply, or if the difference between the two
supplies becomes too great, the RAM may be damaged. If the -5.2V supply becomes more positive than -2.7 volts, or if the 5V supply becomes
more positive than 6.1 volts, AlA2U6 issues a shutdown signal, lights
LED AlA2DS1 and latches itself to keep the supply shut down.
8-145. Remove AlA2 u6 to diable the shutdown. Check the 5V and -5.2V
supplies to isolate which is failing, and troubleshoot the appropriate
supply using the regulator control troubleshooting.
8-146. CONTROL REGULATOR TROUBLESHOOTING.
8-147. Disconnect AlAlJ4.
This will open the connection between
AlAlQ3 and Q4, and remove the power drive for the primary of AlA2T1,
thus removing the chance of shorting the primary rails together if Q3
and Q4 should turn on together. Removing the drive from the primary
of T1 will cause the supply voltages to never come up so that the regulator ICs will run at full duty cycle.
8-148. Check the output waveforms of the regulator ICs. If they are
correct troubleshoot the darlington pairs and the associated drive
circuitry for the switching transistors. If these are okay, suspect
the switching transistors.
8-149. If the output waveforms of regulator ICs are not correct
the inputs as outlined below.

check

8-150. Check the 12V supply voltage for the regulator IC.
AlAlU2 is
responsible for the supply voltage for AlAlU2. It does not apply the
supply voltage to U2 until the control voltage has reached 11 volts
and on power down disables the supply voltage to U2 when the 12 volt
control voltage has dropped below 10 volts. The supply voltage for
the other regulator ICs comes from the 12V control regulator AlAlVR1
with some additional filtering capacitors on the AlA3 board. (12 Volt
control 11.5 to 12.5 volts.)
8-151. Check the 5 volt reference voltage.
regulator AlAlVR3. (4.975V to 5.025V)

It is supplied by

voltage

8-152. Check the current limit Amp inputs. Pin 15 should be at 5
volts, pin 15 should be less than 5 volts. An error here could indicate an failure in U2 reference voltage output, or a possible short on
the output filtering capacitors for the 5V supply.
8-153. Check the clock input waveform on pin 5. Trace the waveform to
the clock generator circuitry AlAlU5 to troubleshoot.
8-154. Check the dead time control input pin 4. This should be low.
If it is high, check for a shutdown signal. If there is no shutdown
signal, troubleshoot the discreet SCR AlAlQ1 and Q2.

8-53 PS

Service - Model 64110A
8-155. PROCEDURE FOR USING THE POWER SUPPLY TEST BOARD 64110-66519.
8-156. First, verify that all green LEDs are lit signifying
supplies are operational.

that

8-157. Second, verify that all power supplies are in spec at the
points on the test board.
Table 8-15.

all
test

Power Supply Test Point Specifications

Supply
5 volt
12 volt
-12 volt
12 volt display
-3.25 volt
-5.2 volt

spec
4.75-5.25
11. 4-12.6
-11.4-(-12.6)
11. 4-12.6
-3.153- (-3.347)
-4.94-(-5.46)

8-158. Third, verify that all supplies are in spec at full load by
pressing one load switch at a time. (5V load switch must be pressed
simultaneously with each of the other loads to insure adequate duty
cycle for the main switcher.)
Table 8-16.

Power Supply Load Specifications

Supply
5 volt
12 volt
-12 volt
12 volt display
-3.25 volt
-5.2 volt

spec
4.75-5.25
11.4-12.6
-11. 4- (-12.6)
11.4-12.6
-3.153-(-3.347)
-4.94-(-5.46)

8-159. Remove the RAM protect shutdown IC AlA2U6 and Check the -3.25
and -5.2 volt supply current limit by pressing the +5, -3.25 and -5.2
volt load switches simultaneously and checking the voltage at the
-3.25V and -5.2V test points. The voltage at the -3.25V test point
should be less than or equal to 1.8 volts in magnitude.
The voltage
at the -5.2V test point should be less than or equal to 1.4 volts in
magnitude.
8-160. Fourth, verify the RAM protect shutdown
protect test switch on the test board.

by

pressing

the

RAM

8-161. POWER SUPPLY SIGNATURE ANALYSIS.
There

are

8-54 PS

no

signature

analysis

loops

for

the

power

supply.

Service - Model 64110A

NOTES

8-55

PS

Service - Model 64110A
NOTES

8-56 PS

Service - Model 64110A
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Figure 8-4.
Motherboard Schematic
8-59/(8-60 blank) PS

Service - Model 64110A
8-162. CPU/IO BLOCK DESCRIPTION.
ASSEMBLY A3.
8-163. The relationships between the CPU/IO functional areas are shown
on figure 8-5.
8-164. CENTRAL PROCESSING UNIT BLOCK DESCRIPTION.
8-165. The microprocessor CPU controls data and addresses on both the
CPU bus and the input/output bus. The CPU clock generator develops
LPHll and LPHI2.
8-166.

LOW POWER-ON PULSE GENERATOR BLOCK DESCRIPTION.

8-167. The Low Power-on pulse generator (LPOP) syncronizes LPOP with
LPHl1. The generator also insures that any pulse from LPOP has a minimum pulse width of approxitmately 35 ns.
8-168.

MEMORY BUS TIMING BLOCK DESCRIPTION.

8-169. The Low upper byte, P/O memory bus timing indicates to the
device being addressed if the information on the data bus is the upper
or lower byte of a word. Low byte, P/O memory bus timin~ indicates to
the device being addressed if the word on the data bus is eight or
sixteen bits.
8-170. The memory bus timing develops the control signals necessary
for the CPU to communicate with the device connected to it via the CPU
memory bus, ie. ROMs, option cards, display controller and RAM, etc.
8-171.

ADDRESS LATCH BLOCK DESCRIPTION.

8-172. The address latch latches the address from the multiplexed
instruction/data/address bus. The information on the output of these
latches produce the CPU memory address bus.
8-173.

ROM DECODING BLOCK DESCRIPTION.

8-174. ROM decoding decodes the CPU address bus allowing the CPU
program counter to select the various ROMs for execution of software.
8-175.

I/O BUS BLOCK DESCRIPTION.

8-176. The CPU communicates with the I/O circuits primarily via the
I/O bus. This bus is a traditional bus in that it carries data, address and control information. The data bus is a 16-bit bidirectional
bus that carries data to and from the HP-IB interface chip, the RS232C interface chip, and the low priority interrupt circuit. This bus
also receives data from the keyboard circuits and switch mode status
8-61 CI

Service - Model 64110A
from the RS-232 circuits.
8-177. The address portion of the I/O bus consists of 4-bits of peripheral address (LPAO-LPA3).
These bits allow up to 16 peripheral
addresses to be decoded (by the peripheral address decoder) which allows the CPU to select the various I/O circuits it wants to talk to.
However, only 9 of the possible 16 peripheral addresses are used in
the 64110 system. See table 8-17.
Table 8-17. I/O Internal Addresses

8-178.

MNEMONIC

FUNCTION

PAO
PA2
PA5
PA6
PA7
PA9
PAlO
PAl 2
PAl 5

Keyboard
Auto-reset timer clear
Serial interface write
Serial interface read
Rear panel board, HP-IB
DSA latch, beeper, display enable
Bank switching, slot select latch
Interrupt mask
Clear high order interrupt

LDYBD
L(DELTA)T
LRS232WR
LRS232RD
LHP-IB
LBEEP
LSLOT SEL
LINT MASK
LIRHCLR

PERIPHERAL ADDRESS DECODER SCHEMATIC DESCRIPTION.
FIGURE 8-13; U12, u28.

8-179. Decoders U12 and U28 decode one-of-eight lines each (for a
maximum capability of 16 lines) depending on the states of the three
binary select inputs (pins 1, 2, and 3) and the three enable inputs
(pins 4, 5 and 6). The same address inputs can be used for both decoder chips because only one chip is enabled at a time. This is implemented by feeding peripheral address signal LPAB3 to the low true
enable input of U12 and to the high true enable input of u28.
This
means that U12 and u28 are never enabled at the same time. Also, note
that pin 4 of u28 is tied to ground thus requiring that only pins 5
and 6 be low for U28 to be enabled.
8-180. Although U12 and u28 have the capability of decoding up to 16
lines, only 9 are used in the current 64110 system application. Five
of the peripheral addresses LKYBD, L(DELTA)T, LRS232RD. LRS232WR, and
LHPIB are produced by U28 and the remaining four addresses LBEEPEN,
LSLOT SEL, LINT MASK, and LIRH are produced by U12.
8-181.

PERIPHERAL DECODER ENABLE bOGIC SCHEMATIC DESCRIPTION.
FIGURE 8-13, U34B/CD.

8-182. The I/O strobe (LBIOSB), Interrupt (HINT), Data Out Delayed
(HDOUTD) , and Data Out (LDOU'l'B) commands from the CPU are ANDed by
U34c,D and then NORed by U34B to produce an enable signal for enabling
Peripheral Address Decoders U12 and u28. This enable signal appears
at output pin 4 of U34B and is fed to gate input pin 5 of both U12 and
u28 (note, however, that the two other gate inputs to U12 and u28 must
8-62 CI

Service - Model 64110A
also be of the proper state).
Decoder Enable Logic.
Table 8-18.
LIOSB

LINT

LDOUTD

o

o

X

X

X

X

1

1

=1

for

the

Decoder Enable Logic Truth Table

LDOUT

U34B
8-183.

Table 8-18 is the truth table

U34B

o
o

for all other combinations

SA INTERVAL, CARD ID ENABLE BLOCK DESCRIPTION.

8-184. In addition to the nine peripheral addresses, there are two
interface control addresses (LIC1 and LIC2) that the CPU uses to
control the signature analyzer start/stop signals (SA interval) and
the card ID address decoder.
This latter circuit produces the ID
enable signal (LID) that is distributed to each of the option card
slots where it enables the various option PC boards to communicate
their unique identification codes to the CPU.
8-185.

LOW PRIORITY INTERRUPT MASK BLOCK DESCRIPTION.

8-186. The low priority interrupt circuitry is a series of gates and
latches. By generating a particular peripheral address (LINT MASK and
other I/O read/write control signals), the CPU can turn on I/O data
buffers, write an interrupt mask into this logic, and then the low
priority interrupt (LIRL) will only be generated when one of the enabled (unmasked) circuits requests an interrupt. When this happens,
the CPU again enables I/O data buffers and reads the Interrupt ID to
determine which circuits have requested the interrupts. Once it determines this, the CPU then writes out another peripheral address to
the device to service the circuit that requested the interrupt.
8-187.

HIGH LEVEL INTERRUPT LATCH BLOCK DESCRIPTION.

8-188. Whenever power is about to fail, the Power Supply sends interrupt request signal LIR15 to the high priority interrupt latch.
This
produces high priority interrupt request HIRH which is sent to the CPU
to inform it that power is failing. The CPU then responds with the
appropriate address code for generating the power fail set peripheral
address (LIRHCLR) to clear the high priority interrupt.
8-189.

AUTO-RESET BLOCK DESCRIPTION.

8-190. This circuit produces the power-on signal (LPOP) whenever
either of two events occur: (1) when the delta-time counters are allowed to time-out due to the CPU taking too long to respond to the
sync-pulse interrupts, and (2) when the processor reset switch is
8-63 CI

Service - Model 64110A
pressed. The delta-time feature maybe disabled by the auto-reset
able jumper.
8-191.

en-

MEMORY MAPPED I/O CARD SELECT
AND BANK SWITCHING CONTROL BLOCK DESCRIPTION.

8-192. This circuitry provides the ability to select each of the
option cards occupying any of the 5 option card slots. This is accomplished by decoding four I/O data bits from the CPU (the other two
bits are for enabling the decoder chip). When the CPU writes or reads
from an address in the range reserved for the option slots, LA14 and
LA15 from the memory address bus enable the card select decoder. Each
of these 5 cards lot select signals (LSELO thru LSEL4) is routed to a
specific card slot in the cardcage where it causes that particular
card slot to be enabled.
8-193.

HP-IB CONTROL, BLOCK DESCRIPTION.

8-194. The PHI chip and associated circuitry allows the CPU to communicate over the HP-Interface Bus (HP-IB) with peripheral devices
that are designed to be compatible with the IEEE 488 general purpose
interface bus.
However, since the 64110 operating system software
incorporates instruction code only for the HP disc drives and the HP
2631A and 2608 line printers, these are the only peripheral devices
that can be driven from the HP-IB bus.
8-195.

HP-IB INTERFACE BLOCK DESCRIPTION.

8-196. The acronym PHI stands for Processor to HP-IB Interface. This
chip is a self-contained micro controller that adapts a wide variety of
microprocessor chips to the HP-IB bus. Some of the general characteristics of the PHI chip are:
a.

Data is sent at the rate of the slowest listener, up to one
megabyte per second.

b.

Data transfer is a asynchronous.

c.

More than one peripheral device can accept data simultaneously.

8-197. To ensure that the transfer of data is accomplished in an
orderly manner, a set of three handshake signals are used: Data
Valid (HDAV) , Ready for Data (HRFD), and Data Accepted (HDAC).
These
three handshake signals ensure that each listener is ready to accept
data, that the data on the data bus in valid, and that the data has
been accepted by all listeners.

8-64 CI

Service - Model 64110A
8-198.

HP-IB BUFFER BLOCK DESCRIPTION.

8-199. HP-IB Data XCVRS, the transmit control signals from the PHI
chip, are buffered and inverted before being sent to the HP-IB data
transceivers. These signals control channel selection and the direction of data flow thru the data transceivers. The HP-IB data transceivers are bidirectional and handle three types of signals: HP-IB
data, handshake, and bus management.
8-200. The HP-IB data consists of instructions and data that are
passed back and forth between the CPU and the peripheral devices on
the HP-IB bus (i.e., printer or disc).
The handshake signals were
discussed above and are used to control and coordinate the transfer of
data. The bus management signals consist of five control/status
signals that are used for such things as activating all peripheral
devices at the same time, clearing the interface, service request,
etc.
8-201.

RS-232C PORT BLOCK DESCRIPTION.

8-202. This circuitry allows the CPU to communicate over the RS-232C
serial interface bus to peripheral devices. It is located on the
local mass storage device. Refer to the local mass storage appendix
of the manual.
8-203.

KEYBOARD BLOCK DESCRIPTION.

8-204. The keyboard is composed of two basic blocks, the keyboardscan circuitry and the keyboard. The keyboard-scan circuitry is found
on the CPU/IO board; it scans the keyboard to detect key changes and
status.
The keyboard is a switch matrix. The columns and rows are
continually scanned, and if a key is depressed, a HKYDET signal is
generated for use by the scan circuitry.

8-65/(8-66 blank) CI

Service - Model 64110A
HHERRUPT LINES
CPU

FLAG LINES

4

4
L

3

3

I······."'.

r------Jo- - 5 • 2 V
r--~

+5V

~ +12V

LSTS I-+---"J

+-______________---..::."'-1-".2V~--l '12 v LFL
G 1--+--..../1
LHL l 1-..----/
L.

~+~1~2VL-_+~~-;r:+~7;V~R~E~G~----~+27~V~~+7V
~.~5~V--_+~----------------~.~5~V-·~~+SV

TPl1
LIOIIRlTE

r--~S~.2~V~+_--------------------~S~.2~1~~-S.2V
~G~N~D~--------------------~G~N~O~~GNO

7

LOOUT

@

l.'t¥:;,i

I/O DATA BUS

TP12
LIOREI\O

LD~

~IIZ~ 3~RSK

P A 0
. . .
105

HDO.UTB

~~~~;

SEL ~
LHp.IB
.:::
LR5232

LBIOSS

~

"-:",LP",,A~BO'-__--1-

II

I

)

liD REA~~
TIMING

LPHI2

Tn~R

i i

@

r-

INTERRUPT MASK
BANK SIiITCHING CNT. 8 MEMORY MAPPED 10
BEEPER AND S.A. LATCH DECODER
HPIB
RS 2 3 Z

III1NUIIL
RESET

l,--;L",PA:.;B,:,;-'__--I PER I PHERAL p"-:-:-,---__~::: I
LPAB2
ADDRESS
UI
S
LPAB3
DECODER
AUTO RESET
LKYBO
,
KEYBOARD

I nnllTn

10-

~

HIGH LEVEL INTERRUPT LATCH

'nniIT

LOOUTr-------~---------------------L~Tn~~R-/

8

UT FROM P_A D

:

LIOSBI-------~---------------------L~UL-/

1-____________~~4---------------------Up~A\~ln-~~

LPAO-3./

~

. T C .2.

~8

LIC1.21------,~----------------------------LU~~

/8

LIODO-7

TO BUS TIMING
A

CIRCUITS

,~,

LIOOO-1S

6

OOD-lS
FROM P.A.D.

r-----~L~PH~I2~--~~B
Il

Ir-'L~rlH_'__'__I CLOCK

~~-t----j
Li~T
I
MASK

I LArCH

POP

I

8

LINT
LPAB3
HDDL

LIRL

L-JJ------+------'

/

U

LPOPB

N -C

NoRMAL OP

N 0

MIINUAL RESET
LINE SYNC

A

LIOAD-15

LDO-1S

.S -

TO 1. M.

:;:;J
1-----1_--------+-<_>

_--,.J,

LATCH

_01

LIRH

rp6
~L~IC~20~________________~II~C2~D____I

HIR RS232WR RS232 TRANS

LlC1D

HIR RS232RD RS232 RECEIVE
HIR HPIB HPIB

~

nnur

I/O 5.11.
LATCH
OUTPUT

0

h

1.0.

WDECODER

FROM (P . A . '-0-.)--:-:'LB!:-':EE~PE~N~ EN

_POP

.J..ll.E.EI'.

'"

C
R

S.A.~

LATCH

~

Z

HEXBG

L

a::
~~

r-----------+--(

'"

,....----,

"-

~

LSTM I-----~
HRAL I -____..i.~
L UM C f-oII-------j
HRDII I-----~
LSYNC .I-----..i.~

o
~

r------~+.L~IIR~T~R~OtlH--------~>
HRAO

______~L~5±'TB'!____I

:r-______-"H"'-liccRT'----1

i

LAO-1S

HALEN

LSTB

5. A. &
ROM
DECODING

L______

I

TPS
S.A. I--------{. MEMORY BUS 5.A.
LATCH
LATCH OUTPUT

I

PROGRAM
J:!CB~:QjI~~~LE~LErC~T~5~/=
'~h ROMS

~OOOO-38FFHH

~+S~VN

_IIRT
IJPA
ES

LDO-iS

/16

LSLOT SEL
LPOP
HIOOB8
HIODB9
HIOD810

EPER

1----''''-''-''-''-----,,,,,<---...,

[

A6

l,_ _ _ _ _ _ _ _ _ _ _ _ _ -....J

HIQDB11

LRDROM

HIODB12
HIODB1::l

u

LCPURUNFREE~
I CKT

z

>-

T

'"
....

0-

D-

~---~LSTUrBL-----~j[=~~JLJD~li4~1~3~lL1~5~,,~·4
.~

:

IU
IU

0

0-

~

--'

z

;HEMORyDlATA.EiU.S·

LPB E

/
......... .

L
L

c..SE.L

110
C/IRO
SELECT

L/I 4
LAI5

D-

o

D-

...J

Z

U

...

LSELO
MEMORY
MAPPED

16

I
LPOPB

LSLOT SEL

i------------,
t--+---i'H BE
II

,,12

LPOP

I

7.-----....-1

-{3:>

FROM P.A.O.

3

LBR
LPDR I -____..i.~
LPBD J-ooII-----J

..l.!!1f RESET I LPOP

~+--'F>----'_-l SYNC.

LRAO-ll

HIJR'

LBYTEr-----~

C

o

0

~ TP1

MEMORY
BUS
TIMING

1.lew
LID
LlC20
BANK
MAP I
"-"'=.0:__--1 SII I r CHI NG HI1"'A""P-:!-Z----"I
pnp
CONTROL
HIIP3

:;:)u

>- -

~

H.H

TO RESET
SYNC.

LIOOO-7

INTERRUPT MASK
P .A.ll

HIR1
Hj. T AUTO RESET
HIR FLOPPY FLOPPY DISK

LBR r - - - - - - - <

LPOP

2S6CLK

V

lBUFFERr

8
/

HIRKI::3 KEYBOARD

16

kPASS-THRU

::: v

6 ,,2
LPDP

v----"'----______

1t>BUS TIMING
CIRCUITS

~,~~6p

AUTO
RESET

INTERRUPT
POLL

L'H-;:;P,:.:,HI:7-'___
~ HPH 12
I-c"H-,::P.c::Hlc..'____________--)l~ HPHI1

~G_E_N__JiL~PIi~I1~--~~A

i

tJ

IR I

~

', .

"

"

)
MEMO~Y

. . . . . . . .. . . . . ~. . . ·i,·'.

t1.~MO~t ADDRES.$·.~U!;).......

7

~..' .......•.

.......••.....

............•

)

;,.

16/

,

......

cONl"JibL

16 . /

)
.'~'.' .

..........

)
BUS'.···.,···.· ••• ·•..•• •.•·•.• · .• ··•· • . . •,· .·..••••..•.•••...•.

.....

a/

.' .

........

)
..··.·.···7 ..•

.< ...

. . . . . . . . . ............. .. . . .•. . . ,. .

••••

.
••••••

....

•...•.......

...................

.

............

....

.

....

.....

.....

..•.

. ....

'·'·30

]

Figure 8-5.
CPU/IO Block Diagram
8-67/(8-68 blank) CI

Service - Model 64110A
8-205.

CPU/IO SCHEMATIC DESCRIPTION.

8-206. The following paragraphs describe functions shown on the
CPU/IO schematics, figures 8-12 through 8-19.
8-201.

CPU SCHEMATIC DESCRIPTION.
FIGURE 8-12.

8-208.

The microprocessor used in the Model 64110A mainframe is made
be thought of as two microprocessors combined on one substrate. First, the basic microprocessor, called the CPU processor, has a 16 bit bidirectional bus with the
data and address time multiplexed. The 16 bit bus is demultiplexed
into a 16 bit data bus and a 16 bit address bus. The data bus, address
bus, and some control lines, (e.g., LWRT, LSTB, etc.), are called the
CPU memory bus.
The CPU memory bus is distributed throughout the
mainframe over the mother board.

b.Y Hewlett-Packard. The microprocessor can

8-209. The second half of the microprocessor is called the inputoutput processor. The I/O processor has a 16 bit bidirectional data
bus, with a 4 bit address bus. Along with the 4 bit address bus, there
are two other control lines that can be used to expand the I/O address
bus. In addition there are control lines that are independent of the
CPU control lines. The I/O data bus, address bus, and I/O control
lines form the I/O bus.
8-210.

CPU POWER SUPPLY SCHEMATIC DESCRIPTION.
FIGURE 8-12.

8-211. The CPU requires +5 v, -5.2 V, +12 V, and +1 V. The +1 V supply is derived from on board regulator VR1, that is supplied by +12 V.
8-212.

CLOCK GENERATOR SCHEMATIC DESCRIPTION.
FIGURE 8-12.

8-213. Clock generators U19 and U18B/CD develop LPHI1 and LPHI2. See
figure 8-6.
The Clock is derived from the 6.25 MHz signal LSCLK1 on
the display control board. LPHI1 and LPHI2 are nonoverlapping signals.

8-69 CI

Service - Model 64110A

LPHI1

LPHI2

1-

64

-I-

U

..fa~a~ ..

96

-,-64-1-

96----..

L

I

~aJ.

...ta~al"

J I I -,-I I
~ao

.. t-

ao _l_ ao

ao...-4

NOTE: TIMES ARE IN NS.

Figure 8-6.
8-214.

CPU Clock Generator Timing

LOW POWER-ON PULSE GENERATOR SCHEMATIC DESCRIPTION.
FIGURE 8-12.

8-215. Chips U57B, U60B/C, U61A, U76C, and plo U77 form the low
power-on pulse syncronizer.
The circuitry synchronizes LPOP with
LPHI1, and ensures LPOP has a minimum pulse width of approximately 35
ns. LPOP is generated by the power supply (and the CPU/IO board in the
event the system becomes lost in its software).
In either case,
LPOP will cause the CPU to be initialized.
8-216.

MEMORY CYCLE TIMING SCHEMATIC DESCRIPTION.
FIGURE 8-12.

8-217. Chips U55A/B, U56A, U57A, U58B, U59, U60D, U65A/B, U74, and
U76A/B develop the signals necessary for the CPU to communicate with
the devices connected to it, i.e., ROM, PROM programmer, display controller, etc. These signals are developed from LPHI1, LPHI2, and five
signals from the CPU; HRAL, LSTM, LPDR, HSYNC, and HRD.
The timing
relationship of the signals needed for the CPU communications are
shown in figures 8-7 and 8-8. An explanation of each of these signals
may be found in table 8-48.
8-218.

CPU ADDRESS BUS SCHEMATIC DESCRIPTION.
FIGURE 8-12.

8-219. Latches U7i and U72 capture the address from the low instruction/data/address bus (LIDA) at the correct time, indicated to the
latches by High Address Latch (HADL).
8-70 CI

Service - Model 64110A
8-220.

ADDRESS BUFFERS SCHEMATIC DESCRIPTION.
FIGURE 8-12.

8-221. Buffers u69, U70 provide the necessary inversion
dress bus for the ROMs.
8-222.

the

ad-

chip

se-

CHIP SELECT SCHEMATIC DESCRIPTION.
FIGURE 8-14.

8-223. Data selector u67A,B
lection.
8-224.

of

decodes the addresses for ROM

ROM SCHEMATIC DESCRIPTION.
FIGURE 8-14.

8-225. ROMs u48-51 contain utility routines for power up of the mainframe, and performance verifications for the mainframe and the local
mass storage options. The jumpers in the ROM address lines have several combinations to allow different sizes of ROMs to be used. Jumper
information is given on the schematic for the indicated board revision.
LOW CLOCK 1
6

3

LOW CLOCK 2
LOW INSTRUCTIONI
DATA/ADDRESS
LOW UPPER BYTE
HIGH READ
HIGH START
EXTERNAL MEMORY
HIGH ADDRESS LATCH
LOW START MEMORY
LOW PROCESSOR
BUFFER OUT
LOW PROCESSOR DRIVE

LOW MEMORY SYNC
LOW STROBE

W////////////W//£
I
I

//////ff/////W/W///tMI
I

I

~I

I

~~------~--~I

:

$ffd0'///0/ff$/#/#/$/ffAJ

LOW UNSYNCHRONIZED
~$
MEMORY COMPLETE
~-~·~·~~~~I~~~~~~~~~I~~~--~--~~~I~~~~~~
LOW DATA BUFFER

:
Figure 8-7.

~I--I------~--~L-

__~:_____________

TYPical Write Memory Cycle

8-71 CI

Service - Model 64110A
LOW CLOCK 1
3

4

5

6

LOW CLOCK 2
I

I

LOW INSTRUCTION/
DATA/ADDRESS

~~--~AD-D-RE-S-S--~~~~__~DA~TA~-J~~,"~~~~

LOW UPPER BYTE

~-""*""~""'m""'7'"%<""
:~,...._-_-_-_-_-_..:...._-_-_-_-_-_-..:...,...._-_-_-_-_-_-~-_-_-_-_-_-_
~_---,-">Wff/ff/ff

I

I

HIGH READ
HIGH START
EXTERNAL MEMORY
HIGH ADDRESS LATCH
LOW START MEMORY
LOW PROCESSOR
BUFFER OUT

LOW PROCESSOR DRIVE
LOW MEMORY SYNC
LOW STROBE
I

I

:

I

LOW UNSYNCHRONIZED
MEMORY COMPLETE

W//&/////ffff////

LOW DATA BUFFER

Figure 8-8.

I

I

:

I

I

Typical Read Memory Cycle

--,~--------------------------~

LOW DATA OUT

--'~--------------------------------_I

LOW DATA OUT DELAYED
LOW PERIPHERAL
ADDRESS BUS

~______________~AD~DR~ES~S____________-J~~~~

LOW INTERFACE CONTROL

~A::><'\o.

LOW INPUT
OUTPUT DATA

~~/%%/~~

____________-IXW/ff//ff//$///////A
__~D~AT_A_ _ _-J~~~;e

LOW INPUT OUTPUT
STROBE
LOW INTERRUPT
TYPICAL 1/0 WRITE CYCLE

LOW DATA OUT
LOW DATA OUT DELAYED
LOW PERIPHERAL
ADDRESS BUS

LOW INPUT OUTPUT DATA

&/////////////////ffdff///////ff////X

LOW INPUT OUTPUT
STROBE
LOW INTERRUPT
TYPICAL I/O READ CYCLE

Figure 8-9.
8-72 CI

DATA

LJ

Typical I/O Read and Write Cycle

~//l///A

Service - Model 64110A
8-226.

DATA BUS SCHEMATIC DESCRIPTION.
FIGURE 8-14.

8-227. Buffers U53 and u45 provide buffering between the ROM outputs
and the CPU data bus. Because the data bus has addresses multiplexed
on it, the data can only be on the data bus at certain times.
Therefore, the outputs of U53 and u45 are active only when Low Data Buffered (LDBUF) is true.
8-228.

TEST/RESET SCHEMATIC DESCRIPTION.
FIGURE 8-14.

8-229. ICs u67A and U74 will cause the CPU to count from 0020 hex to
3COO hex, then reset to 0020 hex and count to 3COO hex again. This
cycle will continue as long as jumper E10 is in the test mode and the
buffers U53 and u45 are removed or disabled. The test mode is used by
a service person when troubleshooting with signature analysis.
8-230.

SA INTERVAL LATCH SCHEMATIC DESCRIPTION.
FIGURES 8-12, 8-13 and 8-14.

8-231. The SA latches U58A/B and u64A are used while taking signature
analysis for setting up the intervals required to get valid signatures. There is the memory bus SA latch u64A, CPU memory latch U58B,
and the I/O memory latch U58A.
8-232.

INPUT/OUTPUT BUS SCHEMATIC DESCRIPTION.

8-233. Activity on the input/output bus is software dependent.
However, when there is activity, the timing sequence is predictable.
8-234. Timing diagrams for both read and write cycles
figures 8-7 and 8-8.
8-235.

are

shown

in

I/O DATA TRANSCEIVER SCHEMATIC DESCRIPTION.
FIGURE 8-13; u40, u47.

8-236. I/O data and instructions are routed thru transceivers U41 and
u47 to the various I/O circuits that require communications with the
CPU. This includes the low priority interrupt logic, card slot select
logic, HP-IB controller and the keyboard. These two transceivers are
bidirectional and are each 8 bits wide. The transceivers are enabled
by either LDOUTB, LINT an4 LRORP, or by any of the following peripheral addresses: LKYBD, LHP-IB or LBEEPEN. The direction of data flow
is controlled by LDOUTB where the flow is to the CPU when LDOUTB = 1
and from the CPU to the I/O circuits when LDOUTB = O.

8-73 CI

Service - Model 64110A
8-237.

BEEPER DECODER SCHEMATIC DESCRIPTION.
FIGURE 8-17, u26B.

8-238. Beeper decoder u26B is a 2-to-4 line decoder that decodes the
LDOUTB and LICID commands from the CPU for the purpose of generating
the SA start-stop interval and activating the beeper circuits on the
A6 secondary board. Peripheral command LBEEPEN enables this decoder
when the CPU operating system has determined the proper conditions
exist. Table 8-19 is the truth table for u26B.
Table 8-19.
EN
LBEEPEN
Pin 15

0
LICID
Pin 13

1
0
0
0
0

X
0

8-239.

0
1
1

Beeper Decoder Truth Table

1
LDOUT
Pin 14

X
0
1
0
1

12
1
0
1
1
1

Outputs
11 10
1
1
0
1
1

1
1
1
0
1

9

Function Activated

1
1
1
1
0

None
None
None
Beeper & Display
S/A Interval

BEEPER START PULSE GENERATOR SCHEMATIC DESCRIPTION.
FIGURE 8-27, U6A.

8-240. Monostable multi vibrator U6A is triggered when LBEEP and
LICID are true and LDOUT is false. When triggered, u16A generates a
pulse approximately 220 milliseconds in duration which turns Q7 on and
causes c28 to rapidly charge up to +5 VDC thru R36.
When the u16A
output pulse terminates, C28 exponentially discharges thru R37 thus
creating a pulse that has a steep leading edge and a sloping trailing
edge which causes the beeper to produce a bell sound. This pulse
turns on Q8 thus providing +5 VDC (HBON) to one side of the beeper
speaker.
8-241.

SA LATCH SCHEMATIC DESCRIPTION.
FIGURE 8-17, U41A.

8-242. This is one-half of a D~type flip-flop that has interface command LIC2D as its D input and is clocked by the pin 9 output of decoder u26B. The output of U41A is fed to test point TP6 and serves as
the SA start-stop signal for troubleshooting the I/O circuits.
8-243.

CARD ID LATCH AND DECODER SCHEMATIC DESCRIPTION.
FIGURE 8-17; U54, U75B.

8-244. Latch U54 is a D-type flipflop a portion of which is used for
storing interface commands LICID and LIC2D when the CPU causes peripheral address LSLOT SEL to occur. The remaining segment of U54 is used
for latching the I/O data bits for generating the card slot select
8-74 CI

Service - Model 64110A
commands (see slot select circuit description).
8-245. The two outputs on pins 16 and 19 of U54 are fed to decoder
U75B where they are decoded into four discrete signals: ID Enable (LID) and MAP commands LMAP1 thru LMAP3. Signal LID is output on pin
67 of J1 and enables the option card ID circuits for the option cards
that may be located in any of the five option card slots.
The three
MAP signals serve as address lines for expansion of the option card
memory capabilities. Table 8-20 is the truth table for U75B.
Table 8-20.
LIC2D
0
0
1
1
8-246.

LIC1D
0
1
0
1

Card ID Decoder Truth Table
LID
0
1
1
1

LMAP1

LMAP2

1
0

1
1

1
1

0

1
1
1

1

0

LMAP3

SLOT SELECT LATCH SCHEMATIC DESCRIPTION.
FIGURE 8-17, U54.

8-247. Latch U54 consists of six segments of an 8-element D-type
flipflop (the other two sections serve as the card In latch). Its
purpose is to latch (store) I/O address bits 8-13 and is under CPU
control (i.e., enabled) via peripheral address LSLOT SEL. When the
CPU wants to store I/O bits 8-13, it causes the LSLOT SEL perpheral
address line to be pulsed. This causes I/O bits 8-13 to be latched at
the positive going edge of LSLOT SEL.
8-248.

SLOT SELECT DECODER SCHEMATIC DESCRIPTION.
FIGURE 8-17, U73.

8-249. Address bits 8-13 from latch U54 serve as the address input to
Slot Select Decoder U73. Addresses LA14 and LA15 from the memory address bus are are used to provide the chip select function of U73 as
shown in truth table 8-21. Whenever the CPU reads or write to the address range reserved for the option slots, LA14 and LA15 are in a
state to enable the slot selector. The jumpers in the memory address
lines LA13-15 must be in the A position for operation of the mainframe.

8-75 CI

Service - Model 6411()A
Table 8-21.

Slot Select Decoder Enable Truth Table

CPU Memory
Address Bits
LA14
LA15

U73 Selected

1
0
All other conditions

Yes
No

8-250. Decoder U73 is a 4-line to 16-line decoder that decodes the
four input address lines. Each of the five outputs from U73 (LSELOLSEL4) is routed to pin 72 of each of the option card slots as follows:
LSELO
LSELl
LSEL2
LSEL3
LSEL4
8-251.

J6-72
J5-72
J4-72
J3-72
J2-72
INTERRUPT BUFFER ENABLE LOGIC SCHEMATIC DESCRIPTION.
FIGURE 8-17, u26A.

8-252. Latch u26A is a D-type together with gate U20 decode LPA3.
LINT and HDOUTB to produce the Interrupt Buffer Enable signal (LIBE).
Table 8-22 is the truth table for LIBE.
Table 8-22.

LINT

LPA3

o

1

LIBE
8-253.

Interrupt Buffer Enable Truth Table

=1

HDOUTB

o

LIBE

o

for all other combinations

HIGH PRIORITY INTERRUPT LATCH SCHEMATIC DESCRIPTION.
FIGURE 8-17, U62.

8-254. This latch is a D-type flip-flop that is clocked by the negative going edge of Power Fail Interrupt (LIR15) and set by either
LPOP or peripheral address LIRHCLR
8-255. Latch U62 is set by LPOP at system power-up (or by pressing
the Reset Test switch). This is done by LPOP passing thru AND gate
U59B and on to the set input of U62 , pin 10. Latch U62 remains in
the set state until a power fail interrupt (LIR15) occurs. When the
power supply senses that a power failure is imminent, LIR15 goes low
which is inverted by U77 before clocking U62. The clocking of U62
causes output pin 7 (HIRH) to go high which is inverted by U27 thus
producing the high priority (unmaskable) interrupt signal LIRH. This
8-76 CI

Service - Model 64110A
signal is sent via the I/O bus to the CPU and informs
that power is failing.

the

controller

8-256. After rece1v1ng the message that power is failing, the CPU responds by writing to peripheral address decoders U12/U28 to produce
the power fail set (LIRHCLR) address. The LIRHCLR bit performs two
functions. First, it sets power fail latch to disable the LPOP pulse
generator U61, and second, it sets high priority interrupt latch U62
thus canceling the high priority interrupt caused earlier by LIR15.
8-257.

DELTA-T INTERRUPT LATCH SCHEMATIC DESCRIPTION.
FIGURE 8-17, u64B.

8-258. The 60/50 Hz LINSYN signal from the power supply enters on pin
75 of J1 and is buffered by U77 before being applied to D-type flipflop u64B and modulo-16 counter u63A. Latch u64B is clocked by each
positive-going edge of LINSYN thus causing the Q output at u64B to
latch high due to the D input of u64B being tied to +5 vdc.
8-259. The Q output of u64B is interrupt signal HIR (Delta) T and is
routed to the low priority interrupt logic and causes a low priority
interrupt (LIRL) to be sent to the CPU via the I/O bus. After a nominal delay, the CPU responds with peripheral address L(DELTA)T which
resets latch u64B which in turn causes HIR (Delta) T to go low and
reset counters of u63A,B.
8-260. If the CPU takes longer than 2.24 seconds (2.6 seconds for
50Hz line frequency) to respond with the L(DELTA)T address, the DeltaT Interrupt Timers (U63A,B) will time-out thus producing a high output
on u63A which is fed to gate U30D. The output to U30D then goes low
and is routed (assuming the auto-reset enable mode is selected) to the
A2 trigger input of LPOP pulse generator U61A. The triggering of U61A
causes the LPOP signal to be produced which in turn resets all of the
circuits that it is tied to.
8-261.

DELTA-T INTERRUPT COUNTER SCHEMATIC DESCRIPTION.
FIGURE 8-17, u63A, B.

8-262. Binary counters u63A/B are each modulo-16 counters that are
decaded thus creating a modulo-128 counter. Counter 63B is incremented one count by each occurance of LINSYN. When this counter reaches a
count of 8, pin 8 goes high. At a count of 16, pin 8 goes low at
which time u63A is incremented.
When u63A has been incremented 8
times, its pin 8 output goes high which corresponds to 16 x 8
128
pulses of LINSYN or about 2.2 seconds for a line frequency of 60Hz.
If the output of u63A is allowed to go high (i.e., time out) before
being reset by the occurance of L(DELTA)T, the LPOP reset signal is
generated (see paragraph 8-145).

=

8-77 CI

Service - Model 64110A
8-263.

MANUAL RESET DE-BOUNCE LATCH SCHEMATIC DESCRIPTION.
FIGURE 8-17, U62A.

8-264. This circuit is latched with the first contact closure of the
Processor Reset Switch and thus prevents multiple triggering (due to
contact bounce) of LPOP Generator U61 A when the system is manually
reset.
LOW PRIORITY INTERRUPT LOGIC SCHEMATIC DESCRIPTION.
FIGURE 8-17; U8A/BCD, U6A/BC.

8-265.

8-266. The eight, low priority interrupts are gated thru AND gates
U6A/BCD.
These gates can be disabled (masked) by the CPU as a result
of latching the masking code into the interrupt mask latch u24. Latch
u24 is cleared by LPOPB.
8-267. The unmasked interrupts are routed to interrupt data buffer
U23 and also are ANDed by U6A/BC to produce low priority interrupt
signal LIRL. This signal is routed to the CPU and causes the CPU to
initiate an interrupt poll to determine which peripheral device
requested the interrupt. The interrupt poll consists of the CPU sending interrupt signals LINT and LDOUT to the 16-bit wide I/O data tranceivers u40 and u47 via AND gate U35B.
8-268. LINT enables the two data transceivers, while LDOUTB controls
the direction of data flow which in this case is back towards the CPU.
LIBE enables buffer U23 to put the interrupt code on the I/O data
lines.
The format of the interrupt code sent to the CPU identifies
the device that requested the interrupt (i.e., the location of the
logic 0 in bits LIODO thru LIOD7 identifies the interrupting device).
Table 8-23 shows the ID code for the eight interrupts.
Table 8-23.
Interrupting Device
HP-IB
RS-232 Receive
RS-232 Transmit
(NOT USED)
Local Mass Storage
Delta Time
Option
Keyboard
8-269.

Interrupt ID Codes
7

I/O Data Bits
6 5 4 3 2 1

0

0
1
1

1
0
1

1
1
1

1
1
1
1
1

1
1
1
1
1

1
1
0
1
1

1
1
1

1
1
1
0

1
1
1
1

1
1
1
1

1
1

1
1
1
1

0
1
1
1

1
0
1
1

1
1

1

1
0
1

1
1
1
1
0

REAR PANEL SWITCH BUFFER SCHEMATIC DESCRIPTION.
FIGURE 8-15, U22.

8-270. This is an uni-directional, 8 channel buffer that relays the
status of the rear panel mode control switch S1 to the CPU. Control is
8-78 CI

Service - Model 64110A
provided by the PHI control logic.
8-271.

ADDRESS LATCH SCHEMATIC DESCRIPTION.
FIGURE 8-15, U38.

8-272. This is a D-type flip-flop that is used to store four bits
(HIOD8-HIOD11) of the I/O address data. Bits 9-11 control the selection of the PHI chip internal address registers while bit 8 serves to
control the RS-232 loop-back test feature.
8-273.

PHI CONTROL LOGIC SCHEMATIC DESCRIPTION.
FIGURE 8-15; U30A/B, U37A/B.

8-274. This circuit is an array of four NAND gates that decode five
input control signals from the CPU. Its purpose is to control the
selection of rear panel switch buffer U22, address latch U38, and PHI
chip U36.
The five input control signals are: HDOUTD, LIC1D, LIC2D,
LDOUT and LHP-IB. Truth table 8-24 shows the control relationships.
Table 8-24. PHI Control Logic Truth Table

LIC1

x

X

o

Input Control Signals
LIC2 LHP-IB LDOUT HDOUTD

o
o
X

o
o
o

X

o

o
X

X

X

Chip Select Status
BUF U22
LTCH U38
PHI U36
Yes
No
No

No
Yes
No

No
No
Yes

X=Don't Care
8-275.

PHI SCHEMATIC DESCRIPTION.
FIGURE 8-15, U36.

8-276. The PHI chip provides a high speed (up to 1 Mbyte) interface
to the HP Interface Bus (HP-IB) for processors and other state oriented devices. It is compatible with nearly any 8 or 16-bit CPU and requires a m1n1mum of external logic. Together with the four bipolar
tri-state transceivers (U1,U4,U5,U19 on the rear panel), the PHI chip
provides the complete logical and electrical interface between the CPU
and the HP-IB. In addition, it provides buffering for inbound and
outbound data transfer through two First-In-First-Out (FIFO) registers
which can be addressed by the host CPU.

8-79 CI

Service - Model 64110A
8-277. The following I/O signals are provided by the PHI chip for CPU
interfacing:
1.

A 8-bit wide bi-directional data bus (LD8-D15)

2.

LDO and LD1 are status bits that
record is being transferred.

3.

A 3-bit address (LA13-LA15) for selecting one of eight
registers

internal

4.

A read/write control (R/W) that controls the direction
flow.

of

5.

An interrupt line (LINT) to alert the CPU of selected events.

6.

Three handshake lines HRFD, HDAC and HDAV
transfer with the HP-IB.

7.

A Direct Memory Request line (LDMARQ) for directly accessing the
CPU memory (not used).

8-278.

indicate

which

to

byte

of

cooridinate

the

data

data

HP-IB LINES, SCHEMATIC DESCRIPTION.
FIGURE 8-15.

8-279. The HP-IB transfers data and commands between the components
of the 64110 Logic Development System on 16 signal lines. The interface functions for each system component are performed within the component so only passive cabling is needed to connect the system.
The
cables connect all instruments, controllers, and other components of
the system in parallel.
8-280. The eight data I/O lines (HDIOl-8) are reserved for the transfer of data and other messages in a byte-serial, bit-parallel manner.
Data and message transfer is asynchronous and is coordinated by the
three handshake lines: Data Valid (HDAV), Ready for Data (HRFD) , and
Data Accepted (HDAC). The other five lines are for management of bus
activity. See figure 8-10.
8-281. Devices connected to the bus may be talkers, listeners, or
controllers.
The controlling mainframe dictates the role of each of
the other devices (disc or printer) by setting the LATN (Attention)
line true and sending talk or listen addresses on the data lines.
8-282. Addresses are set into each device by switches built into the
device.
While the LATN line is true, all devices must listen to the
data lines. When the LATN line is false, only devices that have been
addressed will actively send or receive data; all others ignore the
data lines.

8-80 CI

Service - Model 64110A

HtH Ht {

DEVICE A

ABLE TO TALK, I - LISTEN, AND

f--

DATA BU S
(8 LINES)

( D'"

CONTROL
(MAINFRAME)

DEVICE B
ABLE TO TALK
AND LISTEN

.

--

(

-

DATA BY TE
TRANSFE R
CONTRO L

~

(DISC)

DEVICE C
ONLY ABLE
TO LISTEN

'"

S

GENERA L
INTERFA CE
MANAGE MENT

~

(PRINTER)

~}

DI01

L - - DAV
NRFD
NDAC
IFC
ATN
SRQ
REN
EOI

Figure 8-10. HP-IB Signal Lines

----.Jx'---___x'--(ATN = FALSE)

DATA

SOURCE

DAV
(COMPLEMENT OF DAV)

VALID
ALL RDY

I
I

SOURCE
SOME ROY ALL ROY

I
RFD
(COMPLEMENT OF NRFD)

I

I
I
I
I

DAC
(COMPLEMENT OF NDAC)

I
I
I

11111

STrfl m

NONE RDY

I

LL ACC ACCEPTOR

I
I
I

DATA
TRANSFER
BEGINS

I

DATA
TRANSFER
ENDS

ACCEPTOR

Figure 8-11. HP-IB Handshake Timing

8-81 CI

Service - Model 64110A
8-283. Several listeners can be active simultaneously but only one
talker can be active at a time. Whenever a talk address is put on the
data lines (while LATN is true), all other talkers are automatically
unaddressed.
8-284. Information is transmitted on the data lines under sequential
control of the three handshake lines (HDAV, HRFD and HDAC). No step
in the sequence can be initiated until the previous step is completed.
Information transfer can proceed as fast as devices can respond, but
no faster than allowed by the slowest device presently addressed as
active. This permits several devices to receive the same message byte
concurrently. See figure 8-11.
8-285. The LATN line is one of the five bus management lines.
When
LATN is true, addresses and universal commands are transmitted on only
seven of the data lines using the ASCII code. When LATN is false, any
code of 8 bits or less understood by both the talker and listener(s)
may be used.
8-286. The LIFC (Interface Clear) line places the interface system
in a known quiescent state via the abort message. The LREN (Remote
Enable) line is used with the Remote, Local and Clear Lockout/Set Local messages to select either local or remote control of each device.
8-287. Any active device can set the LSRQ (Service Request) line
true.
This indicates to the CPU that the device on the bus wants attention. The LEOI (End or Identify) line is used by a device to indicate the end of a multiple~byte transfer sequence. When the controlling main frame sets both the LATN and LEOI lines true, each device
capable of a parallel poll indicates its current status on the HDIO
line assigned to it.
8-288.

KEYBOARD-SCAN SCHEMATIC DESCRIPTION.

8-289.
areas:

The

keyboard-scan

Control state machine
Key-depressed latch
Key status RAM
Address counter
Interrupt request latch
Address decoder
Output buffer

8-82 CI

circuitry

consists

of

seven

functional

Service - Model 64110A
8-290. When a key change occurs, an interrupt is sent to the processor.
The processor then reads the key address and status and sends
the appropriate information to the display circuitry.
8-291.

CONTROL STATE MACHINE SCHEMATIC DESCRIPTION.

8-292. The keyboard control state machine is clocked through its four
states by Low Horizontal Sync, LHSYN. The output states are determined
by the Q outputs of the two J-K flip-flops U32A/B.
8-293.

Keyboard Control States.

8-294.

Control State 1. The keyboard status RAM is disabled.

8-295. Control State 2. The keyboard address counter is incremented,
and the keyboard status RAM remains disabled to allow the outputs of
the address counter to stabilize. Also, the signals to write the old
status at the RAM output are present.
8-296. Control State 3. Signal HKYDET is sampled, the RAM is activated and its output is compared to High Key Detect, HKYDET. The comparison is sampled in state 1 for key change detection.
8-297. Control State 4. The scan circuitry checks for a key change.
If a change is detected, High Interrupt Request Keyboard is generated
and the scan circuitry is placed in a halt state until the processor
acknowledges the interrupt and reads the key address and status. Also,
the current key status is stored in the keyboard status RAM.
8-298.

KEY-DEPRESSED LATCH SCHEMATIC DESCRIPTION.

8-299. The key-depressed latch, latches the status of HKYDET at the
beginning of state 4. Pin U32-7 goes high and latches the HKYDET signal at pin U33-9. This status is maintained through all other states.
8-300.

KEY STATUS RAM SCHEMATIC DESCRIPTION.

8-301. The key status RAM stores the status of every key for
detection of key changes.
8-302.

use

in

Key Status States.

8-303. Status State 1. The RAM is disabled to eliminate
erroneous key change detection.
8-304. Status State 2. The address counter is incremented and the RAM
is disabled to allow the outputs of the counter to stabilize.
8-305. Status State 3. The RAM is activated and the addressed key's
previous state is available to be compared with the current state.

8-83 CI

Service - Model 64110A
8-306. Status State 4. The current status of
written into memory.
8-307.

ADDRESS COUNTER

the

addressed

key

is

SCHEMATIC DESCRIPTION.

8-308. The address counter is an eight bit count up counter which is
incremented at the beginning of status state 3. Its output defines the
key being checked and is used by the CPU, the keyboard status RAM, and
the keyboard.
8-309.

INTERRUPT REQUEST LATCH SCHEMATIC DESCRIPTION.

8-310. The interrupt request latch compares the current with the
status of the addressed key using an exclusive OR gate and an interrupt request latch. If the status has changed at the beginning of
Status State 1 (refer to 8-289), a High Interrupt Request Keyboard is
sent to the CPU. The keyboard control state machine is halted, keeping
the keyboard address counter frozen at the address of the key which
has changed status until the CPU has acknowledged the interrupt request.
8-311.

ADDRESS DECODER SCHEMATIC DESCRIPTION.

8-312. The address decoder monitors High Data Out Delayed, HDOUTD,
and LO. When both are low, it enables the keyboard output buffer which
places the key address and status on the I/O buffered data bus. Signal
HDOUTD will be low when the CPU is not writing to the data bus, and LO
will be low when the CPU wishes to access the keyboard.
8-313.

OUTPUT BUFFER SCHEMATIC DESCRIPTION.

8-314. The output buffer places the key address and status on the I/O
buffered data bus when Low Read Keyboard, the output of the keyboard
address decoder, goes low.

8-84 CI

Service - Model 64110A
Table 8-25.

8-315.

Keyboard States

State

U32A

U32B

1

0

1

Keyboard status RAM disabled

2

1

1

Increment keyboard address
counter, RAM remains disabled.

3

1

0

Sample HKYDET, activate RAM
compare output to HKYDET.

4

0

0

Check for change, store new
status, halt ~d wait for
processor read if ch~ge is
detected.

Action

~d

KEYBOARD SCHEMATIC DESCRIPTION.

8-316. The keyboard is a switch matrix composed of sixteen columns
~d
eight rows. The columns are defined by High Key Address 0-3,
HKAO-3, ~d two binary-to-octal decoders. The rows are defined by A4-6
~d ~ eight input demultiplexer. The selected row and
column determine the particular key being scanned. If a key is depressed when it
is being scanned, a High Key Detect, HKYDET, signal is sent to the
keyboard sc~ circuitry.
8-317. The row selected is determined by HKAO-3. Signal HKAO-2 determines which of eight outputs from the selected binary-tooctal decoder
is sent low, and HKA3 determines which binary-tooctal decoder is enabled.
8-318. The column selector decodes HKA4-6 ~d determines which of
eight inputs will be seen at its output. Its output is High Key Detect, HKYDET.
8-319. The keyboard is continually scanned by the keyboard scan circuitry. The current status of HKYDET for each value of HKAO-6 is compared in the sc~ circuitry with each previous status to determine if
a change was made and its status. Signal HKYDET high indicates the key
is depressed ~d low indicates it is released.

8-85 CI

Service - Model 64110A
8-320. CPU/IO TROUBLESHOOTING.
Table 8-26. ROM Troubleshooting (1 of 2)
STEP 1.

ROM FAILURE LEGIBLE ON DISPLAY?

YES .... replace failing ROM IC(s).
Failed
Addresses

Byte

Failed
ROM Unit

0020-1FFF
0020-1FFF

0
1

U51
u48

Lower 8K ROM

2000-3BFF
2000-3BFF

0

U50
u49

Upper 8K ROM

1

DOESN'T FIX PROBLEM .•.. go to step 3. The test may be interpreting the failure of an IC other than the ROM IC(s) as
a ROM IC failure. CPU Freerun will allow you to isolate
failures in other IC's.
NO .... Go to step 2. A failure in the display may be masking the
output of the ROM failure to the display. ROM failure decode
will give you this same information.
STEP 2.

ROM FAILURE SUMMARY .... use
failure summary setup).

power-up

ROM

GOOD Vh .... use the setup to isolate the failing
replace.

test
ROM

table
IC(s)

(ROM
and

DOESN'T FIX PROBLEM .... go to step 3. The test may be interpreting the failure of an IC other than the ROM IC(s) as
a ROM IC failure. CPU Freerun will allow you to isolate
failures in other IC's.
BAD Vh .•.. go to step 3. The bad Vh indicates that the ROM failure setup is not running because the CPU is not able to access
ROM or the kernel of ROM needed for running the setup is not
good.
CPU freerun allows you to troubleshoot the ROM circuitry
with a minimum of timing and control circuitry working.

8-86 CI

Service - Model 64110A
Table 8-26.
STEP 3.

ROM Troubleshooting (2 of 2)

CPU FREERUN .... use signature
freerun setup).

analysis

setup

I

table

(CPU

GOOD Vh .... Take signatures and troubleshoot.
NO BAD SIGNATURES .... Check LMSYN signal from display controller.
Part of the setup for CPU freerun is to disable
LMSYN coming from the display controller board. If LMSYN
is low, in normal operation it will cause the CPU to wait
indefinately.
LMSYN IS LOW ..•. use signature analysis setup U table (RAM
cycle selector/generator setup) to troubleshoot the display controller board.

BAD Vh .... go to signature analysis setup J table (freerun decode
setup). Freerun decode will allow you to isolate failures in the
CPU freerun hardware.
STEP 4.

FREERUN DECODE .... use
(freerun decode setup).

signature

analysis

setup

J

table

GOOD Vh .... Take signatures and troubleshoot.

BAD Vh .... go to worst case troubleshooting table. Not even the
minimum hardware of the CPU, timing and control and the address
latches is operating. Worst case troubleshooting will give you
suggestions for troubleshooting this hardware.

8-87 CI

Service - Model 64110A
Table 8-27.

Worst Case Troubleshooting

CHECK BPC INPUTS:
Power Supplies
Clocks
Check tor pulse low on LPOP on pressing ot reset button.
Check tor LMSYN signal low.
It LMSYN is low, in normal operation
the CPU to wait indetinately.

it

will

cause

LMSYN IS LOW •... use RAM cycle selector/generator
SA setup to troubleshoot the display controller
board.
Check low and high priority interrupt inputs to BPC.
LAST RESORT TROUBLESHOOTING .•.. Use a data probe and
button to check for activity on memory buses.

8-88 CI

the

reset

Service - Model 64110A
Table 8-28.
LOOPNAME :

Power-Up ROM Test

POWER -UP ROM TEST

On power-up, checksums of the program ROMs are computed to verify the
program content of ROM. If a failure is detected a bit in an error
word is set. This error word is used to output an error message to
the display and the test repeats indefinately.

SETUP NAME:

ROM FAILURE SUMMARY

During self test ROM test the error word is output to the data bus.
If the display is inoperative, the user may determine the address
range of and byte of the failing ROM by taking signatures on the data
bus and using the table below.
CPU executing Self Test ROM Test
ST/SP/START: A3TP5, rising edge (MEM SA LATCH)
QUAL/STOP: A3TP5, falling edge (MEM SA LATCH)
CLOCK: A3TP10, rising edge (MEM SA LATCH CLOCK LWRTROM)
byte 0

byte 1

byte 0

byte 1

0000 3FFF

00003FFF

0000 C300

0000 C300

LOO

L01

L02

L03

A signature
the address
A signature
the address

of 0000 means
range is good.
of 0001 means
range is bad.

8-89 CI

Service - Model 64110A
Table 8-29.
LOOPNAME:

Signature Analysis Setup I (1 of 2)

CPU FREERUN

This is a hardware forced loop which forces the CPU to execute LDA
with A instruction beginning with address 0020H and counting through
the ROM address range to C300H at which time a JMP direct, base page
to 0020H is jammed onto the data bus and the loop repeats.
SETUP NAME:

CPU FREERUN

This loop is used to troubleshoot the program
buses in the event that the software is
software.
CPU Freerun jumper A3J7 to Test
LMSYN Jumper A3J8 to Test
Auto Reset Jumper A3J6 to Test
ROM Buffers A3U45 and A3U53 Removed
Display Driver Disabled.
ST/SP/START: A3TP4, falling edge (LRDROM)
QUAL/STOP: A3TP4, rising edge (LRDROM)
CLOCK: A3TPl, rising edge (LSTB)
Vh = 8AHF

8-90 CI

ROMs and CPU memory
unable to execute any

Service - Model 64110A
Table 8-29.
Node

Signature Analysis Setup I (2 of 2)

Signature

Signature

all ROMs
A3U49 and 50
installed
removed
U 45- 2
U 45- 4
U 45- 6
U 45- 8
U 45-11
U 45-13
U 45-15
U 45-17

99Cl
1255
7H08
1227
A876
2880
487A
93H2

769C
8674
9PH6
H58U
7AH6
lF90
9HFl
9HUO

U 53- 2
U 53- 4
U 53- 6
U 53- 8
U 53-11
U 53-13
U 53-15
U 53-17

UU7P
9625
P277
AF21
7C29
3A6p
8A9A
lF91

3AAU
4804
037C
OA75
C34H
8406
PPP3
A8C5
Signature

Node

Signature

Node

U 67-11
U 67-12

OH40
879F

U 72- 6 P975
U 72- 9 AA68

U 69- 3
U 69- 5
U 69- 7
U 69- 9
U 69-12
U 69-14
U 69-15
U 69-16
U 69-18

OU03
F31F
lF93
23C5
79C4
2893
49FO
U7HO
961F

U 70-12 20c4
U 70-14 63A9
U 71- 2
U 71- 5
U 71- 6
U 71- 9
U 71-12
U 71-15
u 71-16
u 71-19

lFFO
7HOF
A24u
U368
A969
964u
49FO
85HU

8-91 CI

Service - Model 64110A
Table 8-30.
LOOPNAME:

Signature Analysis Setup J

FREERUN DECODE

This is a hardware interval which must be initiated
RESET button on the CPU I/O board.
SETUP NAME:

by pressing the

FREERUN DECODE

Freerun decode allows the troubleshooting of the circuitry used to
generate the CPU freerun loop and the memory SA latch.
Auto reset jumper A3J6 to test
LMSYN jumper A3J8 to test
ROM buffers A3U45 and A3U53 removed
Press the RESET button on the A3 CPU I/O board for each signature
ST/SP/START: A3TP8, falling edge (LAO)
QUAL/STOP: A3TP9, rising edge (LA15)
CLOCK: A3TP1, rising edge (LSTB)
Vb

= 782P
Node

Signature

U 64- 5

low

U 67- 5 high
U 67- 8 0093
u 67- 9 high
U 67-11 36c7
U 67-12 4POA

U 68- 6 FHP3

u
u
u
u

70- 5
70- 9
70-16
70-18

3C96
3C96
HPPO
1293

u 72- 2 6ACH
U 72- 5 A6FP
U 72-12 A2F9
U 72-15 43C8
u 72-16 4009
u 72-19 OH71

8-.92 CI

Service - Model 64110A

NOTES

8-93 CI

Service - Model 64110A

-C1-

-R16-R17-C4-

-C3-

-C2-

-C5-C6-

aBBBB_Q ~B B BfBtG
M(jRDIDD8or:l
B o Lj, 0 0 0 0 1~2711~281
a!a BBB~ 10

-R1-R2-

;~:

-C7-

U24

U3
U2

XU21
XU3

-09-

NORMAL

<01>

I

D

U36

U29

DBB fO U
D 'D
fB I L::J~22 f~;~L::l H1~56II~571 1~581 1~59II~601
·C12·

,

M

(;>

~I

'11)

..,...,.

::J

C16

.en

-R4-RSC18

C20

C19

U49

E]ii I

C21

BBBB
U48

I I'"
..... 00 ()

U50

U51

B B 0D

8'70

C36

C37

C38

0
D
U
~
6
2
1
5
'
_
B
·
R
U
C
.
1
6
l
2
6
~
DD

ID
r0C
53
29

C30

0
0
U [J
C39

C40

-C28·

C27

B Ba
l

<0

U65

'C31-

C32

3

I-R9--L1-R10- -R13-R11- C45
-R12--

B DU aB BB B

()

'C41'

C43
·C42·-

C44
-R19C48

-R14-C47-R15-

C49

CPU/IO Component Locator

8-94 CI

I

..,.

<0

I

Service - Model 64110A

-C1-

-C2-

~~~:

-R1-R2-

-R16-R17-C4-

-C3-

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Service - Model 64110A
8-321.

DISPLAY CONTROLLER BLOCK DESCRIPTION.

8-322.

The display controller board serves two main functions,

1.

Provides the processor with a read/write (RAM) memory.

2.

Generates the video control signals.

8-323. The address range alloted to the RAM is from 8002 (hexadecimal)
to FFFF. A part of this memory (from F9FO to FFOO) is dedicated to
storing display information. See table 8-1.
8-324.

RAM WRITE BLOCK DESCRIPTION.

8-325. The processor writes data into the RAM by placing the address
of the location to be written to on the address bus, selecting the
memory and write functions by means of the RAM cycle selector/generator circuitry, and then presenting the data to be stored on the
data bus. The RAM cycle selector/generator circuitry is responsible
for gating the address through to the RAM address lines. Since the
RAM address lines are multiplexed into two 7-bit segments, the RAM
cycle selector/generatormust also control the byte select function
(U49-50).
8-326.

RAM READ BLOCK DESCRIPTION.

8-327. The processor reads data from the RAM by placing the address
of the location to be read on the address bus, selecting the memory
and read function and then gating the RAM data out to the data bus
through buffers U31,U85, and u84. The RAM cycle selector/generator
and the RAM control and decode are responsible for the correct selection of the RAM output buffers.
8-328.

DISPLAY SETUP BLOCK DESCRIPTION.

8-329.

The CRT controller U33 must be programmed with display paramei.e. number of characters per row, number of rows, and number
of lines per character row, before a display can be generated. The
bi-directional buffer U85, allows the processor to directly load the
display parameters into the CRT controller. This programming takes
place very early in the systems operating program and is latched into
the CRT controller, thus occuring only once during power up.
~ers,

8-330.

DISPLAY OPERATION DESCRIPTION.

8-331. A display operation is similar to a RAM read operation.
However, the address for the display data is not taken from the address
bus, but from the binary counters U62-64. When the binary counters
are reset by the LLDCNT (Load Counter) signal, the address of the
8-109 DC

Service - Model 64110A
first display location is loaded into the counters.
The RAM cycle
selector/generator circuitry now gates the display address, instead of
the address bus, through to the address input lines of the RAM.
8-332.

The data out is now gated through the display buffers U32 and
Since the CRT controller can only accept an 8 bit slice of data
at a time, U42 latches half the 16 bit output of the RAM and passes
its data after the data from U32 has been accepted by the CRT controller. This sequence also saves the processor the task of calling that
display address again to retrieve the other 8 bits. The saved time
frees the RAM for a refresh operation.

u46.

8-333. The CRT controller (U33) primary function is to refresh the
display by buffering the display data and to keep track of the character position. The CRT controller also generates the vertical and
horizontal sync pulses used to trigger the sweep circuits of the display driver board. The CRT controller outputs a code to the character
generating ROM at U74 that describes the character to be displayed and
what horizontal line is to be sent to the video drive circuits.
8-334. The character generating ROM parallel loads the display information into the shift registers U89 and U90, which serially output the
display information to the display driver board.

8-110 DC

Service - Model 64110A

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8-111/(8-112 blank) DC

Service - Model 64110A
8-335.

DISPLAY CONTROLLER SCHEMATIC DESCRIPTION.

8-336. The following paragraphs describe functions shown on figures
21 through 24.
8-337. The display controller board produces signals for the CRT,
contains a system clock and RAM which is shared by the CPU. The RAM
cycle selector/generator circuitry controls timesharing of this RAM
between the display controller board and the CPU.
8-338. Information to be displayed on the screen is written into the
RAM space by the CPU at the addresses that are addressed by the counters for the display circuitry. Fourteen address bits are required to
decode one location in RAM. Signal LA14 is used to select the upper or
lower banks of RAM.
8-339.

RAM WRITE SCHEMATIC DESCRIPTION.

8-340. The CPU initiates a RAM write function by pulling address bit
15 (LA15) low. Address bit 15 is sent to the RAM selector/generator
circuitry producing a gating signal, output from U18, pin 7. This
gating signal selects the CPU address lines LAO-13 from the address
select circuit.
The address lines (LAO-13) are input to the byte
select circuit and the upper or lower byte is selected by a gating
signal from u48A, pin 5 to produce output address line LAO-6.
8-341. Address lines Ao-6, sent to the RAM circuit determine where
data (LDO-15) from the CPU will be stored in RAM. The row address
bits are strobed into the upper or lower bank of RAM by means of
clocking signals LURAS and LLRAS respectively. The column address
bits are strobed into the upper or lower bank of RAM by clocking signals LUCAS and LLCAS respectively. Control signals LWLB and LWUB determine whether data is written into the upper or lower byte.
8-342.

RAM READ SCHEMATIC DESCRIPTION.

8-343. The CPU reads data from the RAM by placing the address of the
location to be read on the address bus (LAO-14). Data (LDO-15) is
read from the RAM when signals LWLB and LWUB are inactive (high).
Data LDO-15 is gated to the data bus through buffers U31. u85, and
U84. The arbitrator sequencer and RAM data out routing circuits select the RAM output buffers U31, u84, and u85. Data is routed to the
CPU on the LDO-15 bus.

8-113 DC

Service - Model 64110A
8-344.

DISPLAY SCHEMATIC DESCRIPTION.

8-345. The CRT controller (U33) is loaded with display parameters
(LDO-7) directly from the CPU by means of U85. The display parameters
are loaded once during power up. The CRT controllers primary function
is to refresh the display and keep track of character position.
8-346. The address for display information is taken from the character address counters circuit (U62 thru 64). Signal Load Counter
(LLDCNT) resets the address counters and the address of the first display location is loaded. This address is set to the address select
circuitry.
The RAM cycle selector/generator circuitry now gates the
display address, instead of the address bus through the Row/Column
Address MUX circuitry to the address input lines of the RAM.
8-347. The output data (LDO-7) is gated through the display controller (U33). Since the CRT controller can accept only 8 bits of data at
a time, u46 latches half of the 16 bit output of the RAM.
Data from
u46 is accepted by the CRT controller after the data from U32 is accepted. Th.e CRT controller then produces an address which is sent to
the character generator ROM circuit U74, describing the character to
be displayed and what horizontal line is to be sent to the video drive
circuits. The character generator ROM circuit then parallel loads the
display information into the shift register circuit (U89 and U90).
The character patterns are shifted to the output circuitry in serial
form.
8-348.

DISPLAY CONTROLLER TROUBLESHOOTING.

8-349. RAM TROUBLESHOOTING.
8-350. RAM troubleshooting is divided into simple RAM failure and RAM
refresh failure. Different circuitry may be causing the different
failure types.

8-114 DC

Service - Model 64110A
Table 8-31.
REFRESH ERROR ON
shooting table.

RAM Troubleshooting

DISPLAY .... go

to

RAM

SIMPLE RAM ERROR ON DISPLAY .... go to
shooting table.

refresh

simple

RAM

failure

trouble-

failure

trouble-

ILLEGIBLE DISPLAY .... use signature analysis test loop
table to discern failure type.
REFRESH ERROR .... go
table.

to

RAM

refresh

SIMPLE RAM ERROR .... go to simple
table.

Table 8-32.
STEP 1.

RAM

determination

failure

troubleshooting

failure

troubleshooting

Simple RAM Failure Troubleshooting (1 of 3)

LEGIBLE DISPLAY?
YES .... replace RAM(s)
DOESN'T
used to
rupting
failure

FIX PROBLEM .... go to step 2.
Since the RAM is
store display information, the failure may be corthe displayed failure information. The SA RAM
summary table will give you this information.

NO .... go to step 2. Since the RAM is used to store display
information, the failure may be corrupting the displayed failure information. The SA RAM failure summary table will give
you this information.
STEP 2.

RAM FAILURE SUMMARY ..•. use the RAM failure summary
find failing RAM Ie(s) and replace.

table

to

DOESN'T FIX PROBLEM .... go to step 3. The failure may be due to
a failure in the data path to the RAM, addressing or control.
CPU RAM writes will allow you to check for this type of failure.

8-115 DC

Service - Model 64110A
Table 8-32.
STEP 3.

Simple RAM Failure Troubleshooting (2 of 3)

CPU RAM WRITES .•.. use signature analysis setup K table (CPU
RAM writes setup). First, check the ability of the CPU to
write information to the RAM.
GOOD Vh ..•. take signatures
BAD SIGS ON RAM TIMING AND CONTROL SIGNALS .... use signature analysis setup U table (RAM cycle selector/generator
setup) to troubleshoot. If these signals are not correct
information may not be written to or read from RAM correctly. Since these signals are mostly Vh and 0000, an
error in these signals may not be detected.
BAD SIGS ON MEMORY DATA OR ADDRESS BUS.
These bad signatures indicate a failure of the CPU to
write correct data to RAM. This could be due to the CPU,
the connections from the CPU to the RAM, the pullups on
the MB, the address latches on the CPU I/O board, any IC
that connects to the buses, or the address multiplexers.
NO BAD SIGNATURES .... go to step 4. The addresses checked
in CPU RAM writes was only during the CAS strobe portion
of the address. A failure in the row/column multiplexers
might not be detected. CPU RAS address check will let you
find a failure of this type.
BAD Vh •••• troubleshoot the signature analysis latch and the CPU
timing and control circuitry on the CPU,I/O board using a
scope.

STEP 4.

CPU RAS ADDRESS CHECK •.•. use signature analysis setup L table
(CPU AS address check setup).
BAD Vh .... go to signature analysis setup U table
selector/generator setup) to troubleshoot.

(RAM

cycle

GOOD Vh.
NO BAD SIGS .... go to step 5.
TIMING AND CONTROL SIGNATURE ERRORS .... use
signature
analysis setup U table (RAM cycle select/generator setup)
to troubleshoot.

8-116 DC

Service - Model 64110A
Table 8-32.

Simple RAM Failure Troubleshooting (3 of 3)

STEP 5. ADDRESS SIGNATURE ERRORS •••• use signature analysis setup M
table (CPU RAM reads setup). Before signatures on the output
of the RAM can be correct, addressing and data from the CPU
must be correct. You should have already checked these functions using CPU RAM writes and CPU RAS address check.
BAD Vh.

NO CLOCK SIGNAL .•.• go to signature analysis setup U table
cycle selector/generator setup) to troubleshoot.

(RAM

NO START/STOP SIGNAL ...• go to ROM troubleshooting table.
GOOD Vh.
RAM or RAM ADDRESS TIMING AND CONTROL SIG ERRORS •••• go to signature analysis setup U table (RAM cycle selector/generator
setup) to troubleshoot.
DATA CONTROL AND DECODE SIG. ERRORS •... use signature analysis
setup N table (RAM access control and decode setup) to troubleshoot.
DATA OR ADDRESS SIG ERRORS .••• troubleshoot.

8-351. RAM REFRESH FAILURE TROUBLESHOOTING.
8-352. RAM refresh is accomplished by the display accesses to RAM.
Circuitry in the display counters causes a RAS address for each of the
128 row addresses of both banks of RAM to be generated as the display
accesses the RAM for display information. Troubleshooting in this
section will allow you to isolate problems with individual RAM ICs or
with the display address counters, CRT controller, and control circuitry.
8-353. Retention of the RAM ICs may be greater than 1 sec. Even with
refresh not operating, onlY a few RAM ICs may fail the RAM refresh
test. Taking the key signatures in display RAS Address check will verify that the refresh circuitry is working.

8-117 DC

Service - Model 64110A
Table 8-33.
STEP 1.

RAM Refresh Failure Troubleshooting (1 of 2)

LEGIBLE DISPLAY?

YES .••. replace failing RAM IC(s)
DOESN'T FIX PROBLEM .••• go to step 2.
Since the RAM is
used to store display information, the failure may be corrupting the displayed failure information. The signature
analysis RAM failure summary table will give you this information.
NO •.•• go to step 2. Since the RAM is used to store display information, the failure may be corrupting the displayed failure
information. The signature analysis RAM failure summary table
will give you this information.
STEP 2.

RAM FAILURE SUMMARY ••.• use signature analysis RAM
summary table to find failing RAM IC(s) and replace.

failure

DOESN'T FIX PROBLEM •.•. go to step 3. Refresh is accomplished
by the display accesses to RAM, CRT controller outputs-hardware
setup will check to see that the CRT controller is operating
correctly.
STEP 3.

CRT CONTROLLER OUTPUTS-HARDWARE •••. use signature analysis
setup 0 table (CRT controller outputs-hardware loop setup).
BAD Vh.

NO CLOCK •••. troubleshoot.
NO START/STOP ••.• go to step 5.
VALID Vh.
CRT CONTROLLER IC PINS 1-5, 7-8 SIGNATURE ERRORS ..•• go to
step 5.
The CRT controller is not operating correctly,
CPU program of the CRT controller will allow you to verify
that the CRT controller is being programmed correctly by
the CPU.
OTHER SIGNATURE ERRORS •••. troubleshoot
NO BAD SIGNATURES .•.• go to step 4. If the display address
counters are not working correctly, refresh may not be
done.
Addresses are checked only during the RAS portion
of the address since the RAS addressing is what does the
refresh for the RAM.

8-118 DC

Service - Model 64110A
Table 8-33. RAM Refresh Failure Troubleshooting (2 of 2)
STEP 4.

DISPLAY RAS ADDRESS CHECK .... use signature analysis
table (display RAS address check setup).

setup

R

BADVh.
NO CLOCK .... use signature analysis setup U table
cycle selector/generator setup) to troubleshoot.
NO START/STOP .... go to step

(RAM

5.

VALID Vh.
ADDRESS TIMING AND CONTROL SIG ERRORS .... use signature
analysis setup U table (RAM cycle selector/generator
setup) to troubleshoot.
OTHER SIG ERRORS .... troubleshoot.
STEP

5.

CPU PROGRAM OF CRT CONTROLLER .... use signature analysis setup
P table (CPU program of CRT controller setup).
BADVh.
NO CLOCK .... use signature analysis setup N table
access control and decode setup) to troubleshoot.

(RAM

NO START/STOP .... go to ROM troubleshooting table, step 4.
VALID Vh.
BUFFER TIMING AND CONTROL SIG ERRORS .... use signature
analysis setup N table (RAM access control and decode
setup) to troubleshoot.
OTHER SIG ERRORS .... troubleshoot.
NO BAD SIGNATURES .... check power supplies and clock to CRT
controller. If outputs are bad and all inputs are good,
replace the CRT controller.

8-119 DC

Service - Model 64110A
Table 8-34.

Display Troubleshooting

ARE THE DISPLAY AND CHARACTERS THE CORRECT SIZE AND INTENSITY? .••
First, isolate the problem to the display controller or driver
boards.
YES .... go to display controller troubleshooting table. The correct size indicates that the driver boards are operating correctly. If the display is wrong, it is because the display controller is sending the wrong video information.
NO .... are HSYN, VSYN, and VIDEO signals correct coming from
display controller board?

the

YES .••. troubleshoot display driver
NO .... go to display controller troubleshooting table.
Table 8-35.
STEP 1.

Display Controller Troubleshooting (1 of 2)

CRT CONTROLLER OUTPUTS-DISPLAY TEST .... use signature analysis
setup S table (CRT controller outputs-display test setup).

BADVh.
NO CLOCK .... troubleshoot with scope
NO START/STOP .... go to step 3.
VALID Vh.
CRT CONTROLLER IC PINS 1-5, 7-8 SIGNATURE ERRORS .... go to
step 3.
The CRT controller is not operating correctly,
CPU program of the CRT controller will allow you to verify
that the CRT controller is being programmed correctly by
the CPU.
CRT CONTROLLER IC Hcco-6 OUTPUT SIGNATURE ERRORS .•.. go to
step 2. If the character code outputs are wrong, it may be
because the CRT controller is getting wrong information
from RAM
OTHER SIGNATURE ERRORS .... troubleshoot.
NO BAD SIGNATURES .... use scope to troubleshoot video circui try. The video circuitry runs at 25 MHz; this is too
fast for signature analysis so a scope is required to
troubleshoot.

8-120 DC

Table 8-35. Display Controller Troubleshooting (2 of 2)

STEP 2.

CRT CONTROLLER READ FROM RAM .... use signature analys is
T table (CRT controller read from RAM setup).

setup

BADVh.
NO CLOCK .•.. use signatu~e analysis setup U table
cycle selector/generator setup) to troubleshoot.

(RAM

NO START/STOP .... use signature analysis setup 0 table (CRT
controller outputs-hardware loop setup) to troubleshoot.
VALID Vh.

RAM TIMING AND CONTROL OR ADDRESS MUX CONTROL SIG ERRORS ..
use signature analysis setup U table ( RAM cycle selectorgenerator setup) to troubleshoot.

RAM DATA OUTPUT SIGNATURE ERRORS

ONLY .... use signature
analysis setup R table (display RAS address check setup)
to check RAS address to RAM. If no errors are found, suspect the RAM or any IC connected to the RAM memory data
bus.
OTHER BAD SIGNATURES .... troubleshoot.
NO BAD SIGNATURES .•.. check power supplies and clock to CRT
controller. If outputs are bad and all inputs are good,
replace the CRT controller.
STEP 3.

CPU PROGRAM OF CRT CONTROLLER .... use signature analysis setup
P table (CPU program of CRT controller).

BADVh.
NO CLOCK .... signature analysis setup N table
control and decode setup) to troubleshoot.

(RAM access

NO START/STOP .... go to ROM troubleshooting table, step

4.

BUFFER TIMING AND CONTROL SIG ERRORS .... use signature
analysis setup N table (RAM access control and decode
setup) and signature analysis setup U table (RAM cycle
selector/generator setup) to troubleshoot.
OTHER SIG ERRORS .... troubleshoot.
NO BAD SIGNATURES .... check power supplies and clock to CRT
controller. If outputs are bad and all inputs are good,
replace the CRT controller.

8-121 DC

Service - Model 64110A
Table 8-36.

Signature Analysis RAM Failure Summary (1 of 2)

LOOPNAME: POWER ON RAM TEST FAILURE OR REFRESH FAILURE
If a failure is detected during the power on RAM self-test, the test
enters a signature analysis loop that writes and reads RAM and stimulates the CRT controller. The loop also outputs the error masks onto
the memory data bus and the CPU attempts to display the failing IC
numbers.
SETUP NAME:

RAM FAILURE SUMMARY

Since display information is stored in RAM, the output to the display
of the failing RAM IC numbers may be illegible. This setup allows the
taking of signatures on the memory data bus during the time that the
error masks are present on the memory data bus. The value of the signature and the data bit may be decoded to isolate the failing RAM IC
numbers.
Executing power on RAM test or refresh failure loop
ST/SP/START: A3TP5, rising edge (MEM SA LATCH)
QUAL/STOP: A3TP5, rising edge (MEM SA LATCH)
CLOCK: A3TP10, rising edge (MEM SA CLOCK)

Vh

= 0007

8~122

DC

Service - Model 64110A
Table 8-36.

Power On RAM or Refresh Test Failure (2 of 2)
RAM Failure Summary
Signature

0000

0006

Failing RAM

Bit

LDO
LD1
LD2
LD3
LD4
LD5
LD6
LD7
LD8
LD9
LD10
LD11
LD12
LD13
LD14
LD15

0002 0004

no
no
no
no
no
no
no
no
no
no
no
no
no
no
no
no

fail
fail
fail
fail
fail
fail
fail
fail
fail
fail
fail
fail
fail
fail
fail
fail

U23
u24
U25
u26
U27
u28
U29
U30
U38
U39
u40
U41
U42
u43
u44
u45

U51
U52
U53
U54
U55
U56
U57
U58
u65
u66
u67
u68
u69
U70
U71
U72

U23,
u24,
U25,
u26,
U27,
U28,
U29,
U30,
U38,
U39,
u40,
U41,
U42,
u43,
u44,
u45,

U51
U52
U53
U54
U55
U56
U57
U58
u65
u66
u67
u68
u69
U70
U71
U72

8-123 DC

Service - Model 64110A
Table 8-37.

Signature Analysis Setup K (1 of 2)

LOOPNAME: POWER ON RAM TEST FAILURE
If a failure is detected during the power on RAM self-test, the test
enters a signature analysis loop that writes and reads RAM and stimulates the CRT controller. The loop also outputs the error masks onto
the memory data bus and the CPU attempts to display the failing IC
numbers.
SETUP NAME:

CPU RAM WRITES

This setup allows the checking of the CPU data path to the RAM during
the write of data to RAM by the CPU. It also allows the checking of
the CPU address path from the CPU to the address multiplexers.
The
mainframe is forced to execute the power on RAM failure test loop by
removing RAM IC A5U23.
Remove RAM IC A5U23
Executing power on RAM test failure loop
ST/SP/START: A3TP5, rising edge (HEM SA LATCH)
QUAL/STOP: A3TP5, falling edge (HEM SA LATCH)
CLOCK: A3TP13, rising edge (LMEM WRITE)
Vh

= H37A

8-124 DC

Service - Model 64110A
Table 8-37.
Node

Signature

U 16- 6 0001
U 16- 8 0001
U 23- 3 0001
U 23- 4 0001
U 23-1~ 1A8H
U 37- 3
U 37- 6
U 37- 8
U 37-11

0001
F9U6
0001
1A8H

Signature Analysis Setup K (2 of 2)
Node

Signature

U 85-11
U 85-12
U 85-13
U 85-14
U 85-15
U 85-16
U 85-17
U 85-18

7045
P6FF
C9HH
3H08
P1H6
4F3A
2AU8
3121

U 38- 3 0001
U 51- 4 0001
U 51-15 F9U6
U 79- 2 63F3
U 79- 5 P8FC
U 79-11 61C1
U 80- 2
U 80- 5
U 80-11
U 80-14

HA56
44p6
8A4p
1P30

U 81- 2 F7PA
U 81- 5 683U
U 81-11 U7H3
U 82- 2
U 82- 5
U 82-11
U 82-14

6U3A
87F2
6019
u08c

U 84- 3
U 84- 5
U 84- 7
U 84- 9
U 84-12
U 84-14
U 84-16
U 84-18

728H
UH82
UF05
1UPA
9093
P58U
84H6
F35F

8-125 DC

Service - Model 64110A
Table 8-38.

Signature Analysis Setup L (1 of 2)

LOOPNAME: POWER ON RAM TEST FAILURE
If a failure is detected during the power on RAM self-test, the test
enters a signature analysis loop that writes and reads RAM and stimulates the CRT controller. The loop also outputs the error masks onto
the memory data bus and the CPU attempts to display the failing IC
numbers.
SETUP NAME:

CPU RAS ADDRESS CHECK

This setup allows the checking of CPU addressing during the RAS address to RAM.
Executing power on RAM test failure loop
ST/SP/START: A3TP5, rising edge (MEM SA LATCH)
QUAL/STOP: A3TP5, falling edge (MEM SA LATCH)
CLOCK: A5TP11, rising edge (HPRAS )
Vh

= 7H37

8-126 DC

Service- Model 64110A
Table 8-38.
Node

Signature

U 16- 6 7H37
U 16- 8 7H37
U 18- 7 0000
U 18-11 0000
U 18-12 0000
U 23- 3
U 23- 4
U 23- 5
U 23- 6
U 23- 7
U 23-10
U 23-11
U 23-12
U 23-13
U 23-15

PUC 5
0000
OU51
0337
7143
38HU
40po
OUH9
8coC
UCA3

U 37- 3
U 37- 6
U 37- 8
U 37-11

0000
UCA3
0000
8694

U 38- 3 PUC 5
U 51- 4 0000
U 51-15 UCA3
U 48- 4 0000
U 48- 5 7H37
U 49- 4 8coc
U 49- 7 38HU
U 49- 9 40po

Signature Analysis Setup L (2 of 2)
Node

Signature

U 50- 4
U 50- 7
U 50- 9
U 50-12

OUH9
0337
7143
OU51

U 79- 2
U 79- 4
U 79- 5
U 79- 7
U 79- 9
U 79-11

2HP3
50H4
626H
1U5A
6A39
170P

U 80- 2
U 80- 4
U 80- 5
U 80- 7
U 80- 9
U 80-11
U 80-12
U 80-14

OUH9
72PP
0337
7POO
OF74
7143
7266
OU51

U 81- 2
U 81- 4
U 81- 5
U 81- 7
U 81- 9
U 81-11

8coc
u63F
38HU
45P8
3HH7
40po

U 82- 2
U 82- 4
U 82- 5
U 82- 7
U 82- 9
U 82-11
U 82-12
U 82-14

96cp
PC89
HACA
A78H
C017
FH20
3COA
463H

8-127 DC

Service - Model 64110A
Table 8-39.

Signature Analysis Setup M (1 of 3)

LOOPNAME: POWER ON RAM TEST FAILURE
If a failure is detected during the power on RAM self-test, the test
enters a signature analysis loop that writes and reads RAM and stimulates the CRT controller. The loop also outputs the error masks onto
the memory data bus and the CPU attempts to display the failing IC
numbers.
SETUP NAME:

CPU RAM READS

This setup allows the checking of data as it is being read from RAM by
the CPU, addressing by the CPU, and CAS addressing to RAM.
Executing power on RAM test failure loop
ST/SP/START: A3TP5, rising edge (MEM SA LATCH)
QUAL/STOP: A3TP5, falling edge (MEM SA LATCH)
CLOCK: A5TP15, rising edge (LCPU READ)
Vb

= POOO

8-128 DC

Service - Model 64110A
Table 8-39.
Node

Signature

U 1- 8 POOO

u 7- 3 POOO
u 15- 4
U 15- 5
U 15- 6
U 15- 8
U 15-10

H555
high
high
high
3555

U 16U 16U 16U 16U 16U 16-

high
0000
POOO
0000
POOO
POOO

1
2
4
5
6
8

Signature Analysis Setup M (2 of 3)
Node

Signature

U 31- 1
U 31- 2
U 31- 3
U 31- 4
u 31- 5
U 31- 6
U 31- 7
U 31- 8
U 31- 9
U 31-11
U 31-12
U 31-13
U 31-14
U 31-15
U 31-16
U 31-17
U 31-18

0000
A247
8AM
5AH3
p444
4013
9838
PU53
4A2H
4A2H
PU53
9838
4013
p444
5AH3
8AM
A247

U 18- 7 0000
U 32- 1 POOO
U 21- 8 3555
U 21-10 0000
U
U
U
U
U
U
U
U
U

23- 3
23- 4
23- 5
23- 6
23- 7
23-10
23-11
23-12
23-13

POOO
POOO
H555
9F7F
0344
91P6
F760
3987
7302

U 35- 5 0000
U 35-10 0000
U 36-11

755U

U 37- 3
U 37- 4
U 37- 6
U 37- 8
U 37-10
u 37-11
U 37-12

POOO
955U
POOO
POOO
0000
POOO
0000

U 38- 3 POOO
U 46- 1 POOO
U 46-11 POOO

8-129 DC

Service - Model 64110A
Table 8-39.
Node

Signature

U 48- 2 POOO
U 48- 4 0000
U 48- 5 POOO
U 49- 4 C2F8
U 49- 7 1PFH
U 49- 9 PAFA
U 50- 4
U 50- 7
U 50- 9
U 50-12

CH21
9F7F
5CCC
H555

U 51- 4 POOO
U 51-15 POOO
U 79- 2
U 79- 4
U 79- 5
U 79- 7
U 79- 9
U 79-11

C2F8
52F8
1PFH
UPFH
OAFA
PAFA

U 80- 2
U 80- 4
U 80- 5
U 80- 7
U 80- 9
U 80-11
U 80-12
U 80-14

U293
1293
3PPO
HPPO
2H70
FH70
HC89
3C89

U 81- 2
U 81- 4
U 81- 5
U 81- 7
U 81- 9
U 81-11

H827
3827
HC96
3C96
HAF7
3AP7

8-130 DC

Signature Analysis Setup M (3 of 3)
Node

Signature

U 82- 2
U 82- 4
U 82- 5
U 82- 7
U 82- 9
U 82-11
U 82-12
U 82-14

CH21
5H21
9F7F
7F7F
CCCC
5CCC
3555
H555

U 83- 8 POOO
U 84- 1
U 84- 2
U 84- 3
U 84- 4
U 84- 5
U 84- 6
U 84- 7
U 84- 8
U 84- 9
U 84-11
U 84-12
U 84-13
U 84-14
U 84-15
U 84-16
U 84-17
U 84-18

0000
cuuu
AH28
F8AA
C211
FF7H
APH6
cF46
6251
6251
CF46
APH6
FF7H
C211
F8AA
AH28
cuuu

U 85- 1
U 85-11
U 85-12
U 85-13
U 85-14
U 85-15
U 85-16
U 85-17
U 85-18
U 85-19

POOO
8AAA
p444
9838
4A2H
pU53
4013
5AH3
A247
0000

Service - Model 64110A
Table 8-40.

Signature Analysis Setup N (1 of 2)

LOOPNAME: POWER ON RAM TEST FAILURE
If a failure is detected during the power on RAM self-test, the test
enters a signature analysis loop that writes and reads RAM and stimulates the CRT controller. The loop also outputs the error masks onto
the memory data bus and the CPU attempts to display the failing IC
numbers.
SETUP NAME:

RAM ACCESS CONTROL AND DECODE

This setup is used to troubleshoot the control circuitry used to
enable the RAM data buffers during CPU accesses to RAM and to the CRT
controller The mainframe is forced to execute the power on RAM test
failure loop by removeing RAM IC A5U23.
Remove RAM IC A5U23
Executing power on RAM failure loop
ST/SP/START: A3TP5, rising edge (MEM SA LATCH)
QUAL/STOP: A3TP5, falling edge (MEM SA LATCH)
CLOCK: A3TP1, rising edge (LSTB)
Vh

= CA27

8-131 DC

Service - Model 64110A
Table 8-40.
Node

Signature

U 1- 8 HC2U
U 5- 3 75FC
U 7- 3 3785
U 15-11 2347
U 21- 3 6645
U 21-10 U869
U 21-11 424p
U 35-10 8HA2
U 47- 3 2347
U 78- 1
U 78- 2
U 78- 3
U 78- 4
U 78- 5
U 78- 6
U 78- 7
U 78- 9
U 78-10
U 78-11
U 78-12
U 78-13
U 78-14
U 78-15

A91A
50CO
5FAC
u664
F8FF
2838
4P85
5HCA
APH5
6445
9CPU
U94H
4534
P29H

U 83- 1
U 83- 2
U 83- 5
U 83- 6
U 83- 8
U 83-10
U 83-11

HC2U
HF62
HC2U
APP5
U869
0000
3785

8-132 DC

Signature Analysis Setup N (2 of 2)
Node

Signature

Service - Model 64110A
Table 8-41.
LOOPNAME:

Signature Analysis Setup 0 (1 of 2)

CRT CONTROLLER OUTPUTS-HARDWARE LOOP

By moving jumpers J2 and J3 to the test position, the CRT accesses to
RAM are disabled. The CRT controller is still accessed by the CPU and
configured. The CRT controller runs providing horizontal and vertical
retrace signals to horizontal and vertical sync circuitry.
SETUP NAME:

CRT CONTROLLER OUTPUTS-HARDWARE LOOP

This setup allows checking the horizontal and vertical sync circuitry
and checking for proper configuration of the CRT controller IC.
Move jumpers A5J2 and A5J3 to TEST.
ST/SP/START: A5TP16, rising edge (HVRTC)
QUAL/STOP: A5YP16, rising edge (HVRTC)
CLOCK: A5TP4, rising edge (HCAHR)
Vb

= HUM

8-133 DC

Service - Model 64110A
Table 8-41.
Node

Signature

U 3- 3 745H
U 3- 7 8C75
u 3- 9 212H
U 11- 6 589H
U 11- 8 4179
U 12- 9 9AOO
U 33- 1
U 33- 2
U 33- 3
U 33- 4
U 33- 5
U 33- 7
U 33- 8
U 33-30

AC3F
5414
63UP
UP4F
3763
HAlH
2008
HU61

U 59- 6 Fu65
U 59- 9 34A6
U 75-11

P54H

U 76-15

268H

U 77- 5 08pu
U 77- 9 2A82
U 86- 8 P54H
U 87-11 3A2F
U 91- 5 2HCC
U 91- 9 P54H

8-134 DC

Signature Analysis Setup 0 (2 of 2)
Node

Signature

Service - Model 64110A
Table 8-42.

Signature Analysis Setup P (1 of 2)

LOOPNAME: POWER ON RAM TEST FAILURE
If a failure is detected during the power on RAM self-test, the test
enters a signature analysis loop that writes and reads RAM and stimulates the CRT controller. The loop also outputs the error masks onto
the memory data bus and the CPU attempts to display the failing IC
numbers.
SETUP NAME:

CPU PROGRAM OF CRT CONTROLLER

This setup alllows the checking of the data path from the CPU to the
CRT controller IC, addressing, and control. The mainframe is forced
to loop on RAM failure test by removing RAM IC U23.
Remove RAM IC U23
Executing power on RAM failure test
ST/SP/START: A3TP5, rising edge

(HEM SA LATCH)

QUAL/STOP: A3TP5, falling edge (HEM SA LATCH)
CLOCK: A5TP17 , rising edge (LCS)
Vh

= H7P4

8-135 DC

Service - Model 64110A
Table 8-42.
Node

Signature

U 5- 3 0000
u 5- 6 AP7C
U 7- 3 0000

u 7- 6 H7P4

U 15-11 H7P4
U 17- 6 0000
U 21- 3 H7P4
U 31- 1 H7P4
U 32- 1 H7P4

u 33-12 7172
u 33-13 0547

U 33-14
U 33-15
U 33-17
U 33-18
U 33-19

F9F3
OA5F
55A6
U5H1
7475

U 35-13 12U8
U 46- 1 H7P4
U 46-11 H7P4
U 47- 8 H7P4

8-136 DC

Signature Analysis Setup P (2 of 2)
Node

Signature

u 83- 8 H7P4
U 83-11 0000
U 83-12 H7P4
U 85- 1
U 85- 2
U 85- 3
U 85- 4
U 85- 5
U 85- 6
U 85- 7
U 85- 8
U 85- 9
U 85-11
U 85-12
U 85-13
U 85-14
U 85-15
U 85-16
U 85-17
U 85-18
U 85-19

0000
A391
2235
8242
HPUl
A9A4
AA06
H2A3
U898
U898
H2A3
AA06
A9A4
HPUl
8242
2235
A391
0000

U 88- 8 H7P4
U 88-10 0000
U 88-11 0000

Service - Model 64110A
Table 8-43.

Signature Analysis Setup R (1 of 2)

LOOPNAME: POWER ON RAM TEST FAILURE
If a failure is detected during the power on RAM self-test, the test
enters a signature analysis loop that writes and reads RAM and stimulates the CRT controller. The loop also outputs the error masks onto
the memory data bus and the CPU attempts to display the failing IC
numbers.
SETUP NAME:

DISPLAY RAS ADDRESS CHECK

The refresh of the dynamic RAM is performed by a RAS of each of the
row addresses of the RAM as the CRT controller IC accesses RAM for
display data. This setup is used to check the display addressing
during RAS and therefore refresh circuitry during the CRT controller
accesses to RAM. Since the display is operative during the RAM failure loop, the mainframe is forced into this known loop by removing RAM
IC A5U23.
Remove RAM IC A5U23
Executing power on RAM test failure loop
ST/SP/START: A5TP16 , rising edge (HVRTC)
QUAL/STOP: A5TP16, rising edge (HVRTC)
CLOCK: A5TP7, rising edge (HORAS)
Vh

= 279A

8-137 DC

Service - Model 64110A
Table 8-43.
Node

Signature

U 5- 8 279A
U 5- 9 279A
U 7-11
U 7-12

279A
279A

Signature Analysis Setup R (2 of 2)
Node

Signature

U 48- 5 279A
U 49- 4 9U8c
U 49- 7 355A
U 49- 9 3P32
46H1
OH97
AH4p
861H

U 8- 6 0000
U 8- 8 72P9
U 8- 9 72P9

U 50- 4
U 50- 7
U 50- 9
U 50-12

U 15- 5 high
U 15- 6 high
U 15- 8 high

U 51- 4 279A
U 51-15 high

U 16- 2
U 16- 6
U 16- 8
U 16-10

0000
279A
279A
0000

U 17- 3 9u8c
U 18- 7 279A
U 21- 2 P289
U 23- 3
U 23- 4
U 23- 5
U 23- 6
U 23- 7
U 23-10
U 23-11
U 23-12
U 23-13
U 23-15

279A
279A
861H
OH97
AH4p
355A
3P32
46H1
9U8C
279A

U 35- 4 0000
U 36-11
U 36-13

279A
279A

U 37- 3
U 37- 6
U 37- 8
U 37-10
U 37-11
U 37-12

279A
279A
279A
279A
279A
0000

U 38- 3 279A

8-138 DC

U 62-11
U 62-12
U 62-13
U 62-14
U 62-15

7H02
355A
3P32
46H1
1355

U 63-11
U 63-12
U 63-13
U 63-14

A9FP
H3CP
6H44
PF45

U 64-11
U 64-12
U 64-13
U 64-14
U 64-15

OH97
AH4p
861H
F513
8447

U 79- 4 C811
U 79- 7 12FO
U 79- 9 19A8
U 80- 4
U 80- 7
U 80- 9
U 80-12

8P54
U424
4AHP
FCHU

U 81- 4 279A
U 81- 7 279A
U 81- 9 279A
U 82- 4
U 82- 7
U 82- 9
U 82-12

614c
2AOH
8AH4
Al87

Service - Model 64110A
Table 8-44.

Signature Analysis Setup S (1 of 2)

CRT CONTROLLER OUTPUTS - DISPLAY TEST
LOOPNAME:

DISPLAY TEST

During the display test signature analysis loops are set
and
reset around the repetitive display pattern.
Control stimulus
is provided to the CRT controller IC during the display loop.
SETUP NAME:

CRT CONTROLLER OUTPUTS -DISPLAY TEST

DESCRIPTION: This setup allows the checking of the CRT controller IC
outputs including the character code outputs and control signals. It
also allows the checking of the character generator ROM and HSYN and
VSYN circuitry.
Executing display test
STjSPjSTART: A5TP16, rising edge (HVRTC)
QUAL/STOP: A5TP16, rising edge (HVRTC)
CLOCK: ASTP4, rising edge (HCHAR)
Vh =

UA11

8-139 DC

Service - Model 64ll0A
Table 8-44.

Signature Analysis Setup S (2 of 2)

Node

Signature

Node

Signature

U
U
U
U
U
U
U
U

3- 3
3- 5
3- 7
3- 9
3-12
3-14
3-16
3-18

676p
5HP8
5312
c18H
676p
5312
4489
c18H

U 59- 3
U 59- 6
U 59- 8
U 59- 9
U 59-11

0000
8719
up63
0472
0000

U
U
U
U
U
U
U
U

4- 3
4- 5
4- 7
4- 9
4-12
4-14
4-16
4-18

U239
P328
890C
7045
A2F2
89H9
0828
0000

U 60- 2
U 60- 6
U 60-10
U 60-11

0000
0000
0000
UA11

U 9- 1

0472

U 74- 9
U 74-10
U 74-11
U 74-13
U 74-14
U 74-15
U 74-16
U 74-17

738F
C67P
3930
41TH
C8pU
56A6
2PP7
0000

U 11- 6 1U91
U 11- 8 P1F7

U 75- 2 0000
U 75-11 1270

U 12- 9 UA11

U 76- 2 0000
U 76-15 3F33

U 17- 8 9H7U
U 33- 1
U 33- 2
U 33- 3
U 33- 4
U 33- 7
U 33- 8
U 33-23
U 33-24
U 33-25
U 33-26
U 33-27
U 33-28
U 33-29
U 33-35
U 33-36
U 33-37

8-140 DC

9H7U
A903
CP98
4C9F
8554
UA11
A7U9
731A
1939
58H3
73F8
U239
0828
UA11
0000
0000

U 77- 5 06H6
U 77- 9 0520
U 86- 8 127U
U 87-11

p86p

U 91- 3 UA11
U 91- 5 8719
U 91- 9 127U

Service - Model 64110A
Table 8-45.
LOOPNAME:

Signature Analysis Setup T (1 of 3)

DISPLAY TEST

During the display test signature analysis loops are set and reset
around the repetitive display pattern. Control stimulus is provided
to the CRT controller IC during the display loop.
SETUP NAME:

CRT CONTROLLER READ FROM RAM

This setup is used to troubleshoot the circuitry associated with the
CRT contoller access to RAM. This consists of the address counters,
data path, and control of the data buffers and data latch.
The
address is during the CAS portion of the address.
Executing display test
ST/SP/START: A5TP3, rising edge (LSYNC VRTC)
QUAL/STOP: A5TP3, falling edge (LSYNC VRTC)
CLOCK: A5TP13, rising edge (LDCAS)
Vh

= P5H2

8-141 DC

Service - Model 64110A
Table 8-45.
Node

Signature

U 1- 8 high
U 1-11 5FC1
U 2-11

0000

U 5- 6 0000
U 5- 8 0000
U 7- 6 P5H2
U 7-11 P5H2
U 8- 6 72P9
U 8- 8 0000
U 8- 9 P5H2
U 9-10 H5AU
U 12- 5 P5H2
U 12- 6 0000
U 13- 1
U 13- 4
U 13-10
U 13-13

74P7
6179
4186
75FH

U 15-11 high
U 16- 6 high
U 16- 8 high
U 17- 3 CP11
U 17- 6 P5H2

Signature Analysis Setup T (2 of 3)
Node

U 21- 2 5FC1
U 23- 3
U 23- 4
U 23- 5
U 23- 6
U 23- 7
U 23-10
U 23-11
U 23-12
U 23-13
U 23-15

high

U 32- 2
U 32- 3
U 32- 4
U 32- 5
U 32- 6
U 32- 7
U 32- 8
U 32- 9
U 32-11
U 32-12
U 32-13
U 32-14
U 32-15
U 32-16
U 32-17
U 32-18
U 32-19

75CF
901U
CF87
A454
78AR
84AC
2AF2
9135
5616
OA6c
7021
307H
72CP
4319
A164
7328
5FC1

P5H2
73P7
8P54
u2P6
0000
0000
6c86
0000
0000

U 33- 5 0000

U 18- 5 P5H2
U 18- 7 P5H2
U 18- 9 0000

U 35-10
U 35-13

U 19- 3 A6FC
U 19- 6 PUC9
U 19- 8 96uA

U 37- 3
U 37- 6
U 37- 8
U 37-11

8-142 DC

Signature

loW'

0000
P5H2
high

P5H2
0000

Service - Model 64110A
Table 8-45.
Node

Signature

U 38- 3 high
U 46- 2
U 46- 3
U 46- 4
U 46- 5
U 46- 6
U 46- 7
U 46- 8
U 46- 9
U 46-12
U 46-13
U 46-14
U 46-15
U 46-16
U 46-17
U 46-18
U 46-19

7328
4657
FPPO
4319
307H
CH8H
2522
OA6c
9135
FPHC
6U9U
84AC
A454
1315
PFUA
901U

U 47- 3 high
U 47- 6 C963
U 47- 8 P5H2

Signature Analysis Setup T (3 of 3)
Node

Signature

U 62-11
U 62-12
U 62-13
U 62-14
U 62-15

P2AO
AAu8
4P5P
6H2U
5U8F

U 63-11
U 63-12
U 63-13
U 63-14
U 63-15

6c86
8P54
u2P6
73P7
high

U 64-11
U 64-12
U 64-13
U 64-14
U 64-15

A775
8H02
2P42
C963
52A2

U 79- 4 5CF3
U 79- 7 4U2A
U 79- 9 Ac8F

U 48- 2 P5H2
U 48- 4 0000
U 48- 5 P5H2

U 80- 4
U 80- 7
U 80- 9
U 80-12

U 49- 4 0000
U 49- 7 0000
U 49- 9 0000

U 81- 4 P5H2
U 81- 7 P5H2
U 81- 9 P5H2

U 50- 4
U 50- 7
U 50- 9
U 50-12

A2U8
8P54
u2P6
73P7

U 51- 4 P5H2
U 51-15 high

U 82- 4
U 82- 7
U 82- 9
U 82-12

8P54
6c86
1734
9635

88UH
42A7
68HO
FC90

'I

U 83- 5 high
u 83- 6 high
U 83-11 high
U 88- 8 low

8-143 DC

Service - Model 64110A
Table 8-46.
LOOPNAME:

Signature Analysis Setup U (1 of 2)

RAM CYCLE SELECTOR/GENERATOR

This is a hardware loop. By moving the test jumper p4 from the normal
(XU2) to the test (XU1) position, the RAM cycle selector/generator
circuitry is forced to run at the RAM clock rate.
SETUP NAME:

RAM CYCLE SELECTOR/GENERATOR

This setup is used to troubleshoot the
circuitry.

RAM

cycle

selector/generator

Remove the CPU I/O board
Disable the display driver by disconnecting the cable that connects
from the A6 vertical and secondary drive board to the A7 flyback
board.
Move p4 from normal (XU2) to test (XUl).
ST/SP/START: A5TP14, rising edge (RCARRY)
QUAL/STOP: A5TP14, rising edge (RCARRY)
CLOCK: A5TP2, rising edge

8-144 DC

(RAMCLOCK)

Service - Model 64110A
Table 8-46.
Node

Signature

U 1- 3 55H1
U 1- 8 UP51
U
U
U
U

2-11
2-12
2-13
2-14

8135
86F1
98PH
ACA2

U 5-11 8117
U 9-11 55H1
U 9-12 low
U 9-13 ACA2
U 15U 15U 15U 15U 15-

3
4
5
6
8

7U24
high
high
high
high

U 16- 6 UF74
U 16- 8 UF74
U 18- 7 HF06
U 18- 9 2275
U 18-12 high

Signature Analysis Setup U (2 of 2)
Node

Signature

U 22- 1
U 22- 4
U 22- 5
U 22- 8
U 22- 9
U 22-10
U 22-13

low
low

UP73
low
high
low

669P

U 23- 3 UF74
U 23- 4 7U46
U 23-15 7U24
U 32-11 high
U 35- 1 0022
U 35- 4 2275
U 36- 3 high
U 36- 6 ACU7
U 36-11 HF06
U 37- 3
U 37- 6
U 37- 8
U 37-11

7U46
UP51
7U46
7U24

U 38- 3 UF74
U 20- 6 high
U 20- 8 H4c1
U 21- 3
U 21- 4
U 21- 6
U 21- 8
U 21-10
U 21-11

high
low

7U46
low
high
low

U 48- 5 7U46
u 48- 8 8175
U 48- 9 7U06
U 51- 4 7U46
U 51-15 UP51
U 86-11 0022

8-145 DC

Service - Model 64110A

3 3 L . . . - - - -_

JI

_- - - - - - - .
GND

TP 11

GND

TPI ~

'G [J [J tr:, G':lr' G: : []"': on ~y ,a,,,, B 9
B

TPZ

,,~:

TPI6

TP3

a a a,o
TP6

EI

J2

N

UI9

E3

EZ

CIZ

C6

C7

CB

C9

Clo

Cl1

B0

BGB 8B808888

1'~'I 1: ,·1 B

T

TP9

::: ::: :::

no

:::

:::

:::

""

'B" B,,886B66B6
~
B
B '" '" '" '" '"
U
BBBoB 0 0 0 0 0 0 B" B G
98 0 0",0",0",8",0,,,6,,,0,,,0 B GoB 9
''----'41

CZ9

C31

C33

on

'"

C36

C3B

C40

C50

C52

C54

C51

C53

C55

T

C4Z

R9

RID

RI3

C43

C45

C47

~~~

:~:

C44

C46

C4B

C49

E4

N

E5

RI6

E6

C56

~D

M7
RIB
C74

C66

C7Z

C76

o'" 0 ~ S. 0 B'" 0 ~ ~'" 0 BoB JJ
E

C6B

'-----I

CR3

PI

C75

B5

. - - - - - -

Display Controller Component Locator
8-146 DC

GNo

Service - Model 64110A

--

--

--

--

DISPLAY CONTROL BOARD

--

(6411 0-665191

I
10
11

VH7
5

76

J

C
K
R

14

VH6

L5CLK1 1

5

13
VH9

PIO Pl

VH7

U106

7

H5CLK1

5

HRIIMCLK

6

LRAMCLK

II

41

B

4C

I

J

14
"5

U73
25MHZ
05C

6

C
K
R

VH6

U10A

C

41

4C

VH9

SYSTEM CLOCK GENERATOR

TP9

ICS ON THIS SCHEMATIC
REF. OE5.
U6
U7
Ul0
Ull
U14
U61
U73

HP PIIRT NO.
1620-1453
1620-0661
1620-0629
1620-1449
1620-0663
1620-0697
0960-0534

I PARTS ON THIS
I L_ _
_

MFG. PIIRT NO
745163
74500
745112
74532
74504
745140
0960-0534

SCHEMATIC

.~~~

__________________~__~~--~

1
9

VH2

12

10
7

3

4
5

TP4.9
P_1_ - - - - - - '

CTR DIV 16
15

HC

14
13
12

He

HC

10

6

9

IC POWER SUPPLY
CONFIGURATIONS

~ U6.10
"5~

11

U7.11.14
U61.73

4D

....:LC....:H-'-IIR--11u\ 4D

L -_ _ _ _ _

-

LDOTCLK

~ 4C

I

f.:\

~----------------------------------------------~~ 4D

I

PIO Pl
L25MHZ I
~------------------------------------------------------~-7 61

II

4A

'------ - -

----- -- - ----.... - - ------ - - ----- -- - ----8/3/81

Figure 8-20.
System Clock/Generator, Display Controller Schematic 1 of 4
8-141 DC

Service - Model 64110A

3 3 ' - - - - -_

__ _ _ _ _ .

JI
TPll

GND

TPI~

GND
TP2

,,~:.

Goo

G':ll" G: : G'' ; on 9" tj,,,, 8 Q
TPI6

[l~:,

TP3

TP9

8

TP6
N

888"0
88B 00000000
I:~i'l I:~"I 0 : : : : : :

00

B B B ODoBoOOD
"" ""

H
U

C6

C7

C8

m

::

C9

CIO

Cll

:::

:::

:::

EI

C29

C31

'"

C33

m

m

'"

C36

C38

C40

J2

UI9

E3

E2

C12

""

""E""

m

T

8

'"

L---...J

Boo BoB BBBBB B" 0 8
C42

N

T

R9

RIO

RI3

C43

C45

C47

~:~

~::

C44

C46

C48

C49

C50

C52

C54

C51

C53

C55

E4

E5

RI6

E6

C56

goo D,,,D,,,D,,,O,,,O,,,oJJ,,,O 8 [J BB~
eND

RI7
RI8

CH
C66

C72

C76

B'" B ~ 8, 0 BmOD
~

'----------.1

PI

~"j 0 Boo ". B
~

~

85

Display Controller Component Locator
8-148 DC

eND

r--------./

Service - Model 64110A

I

P/O ASOISPLAY CONTROL BOARD164110-665191

ICS ON THIS SCHEMATIC
CTR DIV 16

I
I

-&

CHARACTER ADDRESS
COUNTERS

LAO

LA3

CTR DIV 16
HI
L
H2
T ~
G3
15
10 ~ G4
3,5CTk
I
7 "
G5
',5C1= 0 r------'
2
G6
I
2,3,5,6+/C7
~ >2,4,5,6-/C7
l

LADDCLK

40
40
4C
PIO PI
I
I LSTB
I

64

YH2f
2

S
C

YHB~

R

EE

Z

V

10

S

g

C

9

1 70 [11
I 70 21
70 .~

j

LLDCNT

VHB..!l..b'--~_--'-U8;:.;B:..&~~13
U7D

r;8

I

BT
11

I

II ; T

10

11~

I

13

~8p.~1'-'0'- '1'_'1u., J
"'''1

U22C

12~

_

-

PIO P4

16

L __

111
~

'"-'

4C
4C
4A
16

U

HRC

T

LRC

C

LRAMCLK

3~

2

,-

......J

r

LA6

-

LCPURO

M

~NC

0

H2

3,5C1=15
4, 5C T= 0

~ NC

G6

1

0

1

•.

7

UI,S,7-9,
17,21,
22,4B

4

0

+5

U 18.

49,50,62-64,
79-82

HUX

110
v7 ~ ~~1
UBO

r---------~h_..._----I_M'--r1--1
13
1
LA7
14
0
pJL. -

6

10
11
6
5
3
2

LA8

I 70 [II

I 70 [21
70 .3

LA9

1121

LAIO

1

~.--

0

1

~-

r\1-..
1

1:>-4

0

4C
NUX

A~~1
0

4C

UBI

I--_________________________________.!!.HD""C""0'-j

0

RAM CYCLE SELECTOR

N

~.

0

15

13
14
10
11
6
S
3
2

LAll

4C

LA12

!5

1

IS

\I

IC POWER SUPPLY
CONFIGURATIONS

'7

V

~13___________ ,

N
3________~.-~~~____~3~~
~
, T
--....
2 I U22A J--'-1_ _ _1-Q2 5 ,'12
14 ..
' T
U36A "'p--",-3_-"-,,J'L____

~

2

LAS

vII

VH10
14

3

VHIO

4C

U22':1J-

PIO P4

LORD

UIA

HCPURO

Y /----------------------+-----~~----------~~~--~

BB

2

. I
,-l-t

!

4C

P4
RlO-15
TPI ,B
Ul,5,7-9,17,IB,ll,22,34,36,47,4B,49,
50,62-64,79-82

~c=~3~~l~lj7DiU~~~31~~r~~11~43~1[~~~~~~-=.-=~~~~~~~~~~~fv~~~~~--~
~

12r--J U90.J
HSCLKI
A ~~~----------------------------------~~~~-~
VHIO
PIO P4
8
\ T
9 8)9
.4
U22B

4C

U21

~P3

SU: U~~g

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MFG. PART NO.
74500
74L508
74L574AN SLT
7-4.502
74L586
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74504
3168270
74L532
74574
7451.58
74L5669N
74L5158

PARTS ON THIS SCHEMATIC

4

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HP PART NO.
IB20-0681
1820-1201
1820-11ll
IB20-1322
1820-1211
1820-0629
IB20-0683
1820-0536
lB20-120B
lB20-0693
1820-1015
1820-1435
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CTR DIV 16
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~
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7
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5 "

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9

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CPU DECODE
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N

14
13
12
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r

1

12

I LSTM
I
I
I
LAO
LAI
LA2
LA3
LA4
LA5
LA6
LA7
LA8
LA9
LAID
LAII
LAI2
LAI3
LAI4
LAI5

I

UBA

6

00 /---+------------------'

I

19
20
21
22
23
24
25
26
27
2B
29
30
31
32
33
34

a

II

PIO P4

63

r-L- Ne

1

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4
10
11
6
5
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VHIo-t3!~~~1~7ID~[~0~1~~~~~~~~~~~~~~~~~====~~::~~~~~~~~~~ti======1
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U62

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IS

v4

12

0

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>

r

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6
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UI ,7
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13

I

9

S
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0
1

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0

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9

7
4

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HOISP/LCPU CYCLE

VH7 ~L-~R~U~I~B~B~-7~----------------------------------------------------------t_------+-----------------

4

5

s

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o

VHIO --Lt::,

R

14

U48A ~ NC

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a 4C

LAO
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)

15 LA1-15
/

L
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40
4C

I
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48

Figure 8-21.
Character Address CounterjMux, Display Controller Schematic 2 of 4
8-149 DC

Service - Model 64110A

33~

_

_- - - - - ,

Jl

TPll

GNO

GNO

TPI4

DD tr:,', G':lr' 8 : : 8 [J" 9" [l", B Q
B
B B [l [J
TP2

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m

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C6

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U
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B [] [] BBBBBBB[]
C29

C31

C33

m

m

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C36

C38

C40

C50

C52

C54

C51

(53

(55

L---..J

C42

RIO
Rll
RI2

R9

R13
RI4
R15

C43

C45

C47

C44

C46

C48

C49

PBB B""B",B,,"B,,,BJJJ~J...B

T

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N

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m

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~I

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(76

0 ~'j B B B B'"' B
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85

.-------../

Display Controller Component Locator
8-150 DC

GNO

Service - Model 64110A

SEE NOTE'

16

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37~~
p=

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39

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11

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l

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Cl
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~I R~HI0~ IBt=I:I 0~ ViJ_I~9!: ~~~~~~~~~~~~~~~~~~~L~01010~ 0
RMI
RM2
RH3
RH4
RM5

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-t--l--+-+-------+-t----l U38

U39 U40 U41 U42 .U43 U44 U45
r-'-_"'-_"'-_-'-_-'-_-'-_-'-_-'-----'

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17
14
13
8
7

10
10
10
10
10
10

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V
V
V
V
V
V

16
IS
12
9
6

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l002
l003
L004
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1

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-f---+--+--+--+--+--+--+----i

1)-...

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LOI

LATCHES

16

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Me

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13
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--

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LOO

LOC

16KX32 OYNAMIC RAM

L...j_ _

-+-----1I--_LO_C_--"8_~-+_t____l

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U51

LOI

L02

L03

L04

LOS

L06

L07

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U53

U54

U55

U56

U57

U58

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RMnn-7

RH8

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I HP PAR NO. 'HFR. . PAR. ...NO
1820-0681
74500
1820-1453
745163
1820-1201
74LS08
1820-0693
74574
1820-1208
74532
1820-0688
74520
1820-1211
74lS86
1820-0629
745112
1820-0683
74504
1818-0341
MK4116P
1820-2024
1810-0536
1820-1144
1820-1997
1820-1130
IB20-2075

74L5-244N
316B270
74L502N 5LT
74L5374N SLT
745133
74L5245

PIO P4

PARTS ON THI S SCHEMATIC

I

PI, 2,4
TP2,5,6,7,l1,13,14,15,17

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NOTE

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4
5

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Ul,5,7,12,15-17,
20,21,35-37,
48,83,86

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38-45,
51"58,
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1-'"
I

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2

6

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LOCA5

U7B
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16383

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J
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9

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ICS ON THIS SCHEMATIC
REF

'----------------------~~

TPI7

0 }-'H"'O"'C"'O_ _ _ _ _t-'

f-L-______hLW~RDT~__________________________________________________~1~0~~7-------------------------------------------------------r-----l------------------------t-----------~~'~'i~21

I

16

J U830 p>-..ll--~
@--

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Pia PI

65

LAI5

P/O

40

PI

~L~C~Chl~K-------t~~UL==========================================================================================================================~________________________~~____~I~ 66

HI

C2

-"-rri---,--I

OISPLAY REOUEST LATCH
C3

~------~--IB-2-0--~14-s-1~-7-45-3-8----~

LOO-I~=::==-~~~==~~~=4~

RMOO-15 _____

---~

4C

Figure 8-22.
Character Generator/Latches, Display Controller Schematic 3 of 4
8-151 DC

Service - Model 64110A

JI
TPII

GND

GND

TPI4

0 0 [j,~:, G':lr' G::lJ': on 9" B' ' B Q

TP2

TPI6

,,~: 'G

TP3

TP9

TP6

B B B,o

EI

J2

N

B
UI9

E3

E2

CI2

C6

C7

CB

C9

CIO

CII

00"

B B B Omo",oJJJl"o",o",o

I!~i'l I:~'"I B

T

n.

'"

no

n,

n"

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C29

C31

C33

m

m

m

m

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m

C36

C3B

C40

C50

C52

C54

C51

C53

C55

:::""'""
B
BuB oooBoooB U~ B '~
"
BBoB 0 0 BBBoB B., 0 B
9BB O",D",O",D",DJJ",O",O B tJ ° B9
""

C42

N

T

R9

RIO

RI3

C43

C45

C47

~:~

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C44

C46

C48

C49

E4

E5

RI6

E6

C56

GND

RI7
RIB
C74
C66

C72

C76

~l" 0 g 8 B BmOD ~'" 0 BOD JJ
5

C68

CR3

'------I

PI

C75

B5

~--/

Display Controller Component Locator
8-152 DC

GND

Service - Model 64110A

--

PIO /\5 DISPLAY CONTROL 164110-66519)
HOOTCLK 125MHZI
4/\
411

1
14/\

0

t--~

~---!-~
~-L-'J
~---!--'J

LOOI

HVSP
HOBI
5
1

LOO3
X LOO4

6
2

HOB2

3

HOB3

U33
CRT
CONTROLLER

VHl
35

6

12
13

+5

12

R7
lK
LLTEN
HRVV

13

NC

37
36

19

HDB4

HLCO

17

3
LDD6
LOO7
VH3

6

NC
NC

0

.ROM
Zt< X 8

8

9

LCS

18

LOCAS
NC
VH3

HOB6

19

HDB7

21

HIIO

22

LCS

10
6
11
9

HIRO
HHLCT
HPGAO
HGPIIl
HLi\l
HLJlO

31
32
33
34
38
9

Il

4
3
2
1

HLCO
HLCI
HLC2
HLC3

HCCO
HCCI
::; UJ HCC2
<8 HCC3
~u HCC4
:I:
HCCS
u
HCC6

23
24
25
26
27
28
29

HCCO
HCCI
Hee2
HCC3
HCC4
Hces
HeC6

,... 'HLCO

a:

UJ

LWR
LDIIC
HLPEN
LRO

13

R19
120

D

Ll

LH5YN

5!

LIVIO

NC

HCCO
Cl
HCCl
CC3

,; l

LCC1B
CClB
CC3B
LCC4B
CC5B
CC6B
LVF\TCB
LHRTCB

C

VH5

15
16
17
18
19
20 ;:;
8 UJ
10 '"
::>

14
13

13

7

HLCO
HLCI
HLCZ
HLC3
HCCO
HLC3
HLCZ
HLCO

NC
NC

12

2,3D

11

CH/\AACTER
GENERATOR

NC

LLCOB
LLC1B
LLCZB
LLC3B
LCCOB

..rr
..rr

II

7

9

HOOTCLK

411

~E4

P3

HSYN

VH4

Ne

CTF\ OIV 16

+5

+5

VH5

1 48
1

oOr---------~~----------------------4-----~

~

VH5

l

_

_ _ _ _ __ __ _ _ _ _

+5

5

C

0

I-_R_~U~59:.;i\.J~6~-_~---*~~

1-----==:...a

HCHIIR
P/O PI
I

+5------------------~-----~----~
Cl-S,7,10,12,16,l3,26,27,~I,

38,4142,46,53,56,57,65,66,
69,71-76

l'
\7

\7

NC
Ne
Ne
NC

NC
NC
NC

CI3,15,17,19,20,
22,Z4.28.30.32.1'
34.35,37.39.43. \7
4S,47.49.50,52.
54,58.60-62,64

R5
147

4

5

S
C

.......____"'-1-0- +5

--

CR4

C6,8,9,11,14,18,
ZI,25,29,33,36, T .IUF
40,44,48,51,55 \7

U91i\

6

R8
lK

3
4
83
84

R4
lK

13
14

R16
lK

R17
lK

R2
lK

R3
lK

R9
lK

VHl
VH2
VH3
VH4
VHS
VH6
VH7
VH8
VH9
VH10

5
6
7
8

C68

+T 10UF
\7

L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~-----_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~L~V~5YuNL__~

0

R

+5

8

R6
lK

J

C67'
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-5.2---------------------~----~~--~

VH5

"-

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Rl
lK

Rl8
lK

t

+12------------.-----~----.~--+~

+5

NC

_

NC

-5

VSYN
S

VH4
Ne

+5
+5
4,,~,~H~C~H~AR~______________________~________________-+~________________________~____________________~~--_---------------~------~--~

VH4

8

VH5

NC

L-----~_f)

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0

VH5
VH4

w
r

23 zw
24 <
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25 UJ
14
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3

H~L~CH2i\~R~----------------------f1~~~N;:~=======t====1=~========================================~=t======~~::::::~~~===:r=========================~------------------------~r-----~:=======~--~----------------t:1t----------------------~9~1
E5
E6
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17,19.S9.76.
10
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77 86 88 91

,...~

6

NC

LDO

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+S

c

15

11

CC HORO

IC POWER SUPPLY
CONFIGUAATIONS

,...

14

15
16
17
9
10

11

MFG. PART NO.
74500
74LS240N
74L508
74502
73532
74574
74L502N SLT
74504
74lS86
74L500
827511
74L574AN SLT
745175
1816-1496
74L5163
74538N
74510
745195

PIIRTS ON THIS SCHEMIITIC

58

P/O
HIVID
HVID

HP PIIRT NO.
1820-0681
1820-1927
1820-1201
1820-1322
1820-1449
1820-0693
18.2"0-1144
1820-0683
1820-1211
1820-1197
1820-2191
1820-1112
1820-1191
1816-1496
1820-1432
1820-1451
1820-0685
1820-1303

Cl-76
CRI-4
Ll
P3
RI-9.16-19
TP3
Ul.3-S,9,11-14,17.19,33.S9,60,74-77.
86-91

CR3

+5

SF\G4

HHRTC
HVRTC
HDRO

CCLK

_ _ _ _ _ _ _ _ _~LV~I~O~_--!--'J 57

NC
NC

2
1
23
22
21

~ ~ HLCI
::;0 HLCl
w HLC3

~~_*-

NC

4
3

NC
NC
NC
NC
NC
NC

3S
36
53
54
59
60
79
80
85
86

SRG4

VIDEO

11

4C

+5

6
5

HOBS

~-L-'J
~-!---4

2

NC

0

7

LAO

t--~

VH5

6

~-L-'J

NC
NC

LOO5

48
4C
4C
4C

t--~

O-FF
HOBO

4C

~---!--'J

LOOO

LOO2

REF. DE5.
Ul
U3,4
US
U9
Utl
U12,91
U13
U14
U17
U19
U33
U59.77
U60.87
U74
U75,76
U86
U88
U89,90

1

VH5

DIN & CRT
CONTROL

ICS ON THIS SCHEMIITIC

P/O PI

56

NC
1/82

40
Figure 8-23.

RAM, Display Controller Schematic 4 of 4
8-153/(8-154 blank) DC

Service - Model 64110A
8-354.

DISPLAY DRIVER BLOCK DESCRIPTION.

8-355. The display driver board provides the video drive, sweeps, and
bias voltages to drive the CRT. The video drive circuit features two
drive levels, one for regular video, one for inverse video. The inverse video drive is about half the intensity of the regular video
drive to avoid glare.
8-356. The high voltage circuit generates grid voltage of -40 v, +200
to 700 v, and 0 to 470 V necessary to provide intensity and focus adjustments. The beeper circuit provides an audible feedback to signify
the occurrence of specific events during performance verification and
normal operation.
8-357.

DISPLAY DRIVER SCHEMATIC DESCRIPTION.

8-358. The display driver boards provide the video drive, sweeps, and
bias voltages to drive the CRT.
8-359. The display controller IC U33 on the display controller board
is responsible for providing horizontal and vertical retrace signals
and the low video and low inverse video signals.
The other signal
necessary for the display driver to operate is LBEEP from the CPUjIO
board.
8-360. With no video signal applied, low inverse video (LIVID) and
low video (LVID) are high, forcing the outputs of U1A and U1B low.
Transistor Q3 is an emitter follower and supplies necessary current to
k~ep the Q3 emitter voltage near 30 V and the video off.
8-361. If LVID goes low with LIVID high, the output of U1A releases
the base of Q2 and allows it to turn on. CR2 and CR3 prevent it from
saturating. When Q2 turns on, it holds the base voltage of Q3 low
forcing the emitter voltage of Q3 low and the video full on.
8-362. If LIVID were to go low while LVID was low, Q1 would be allowed to turn on. But since the base voltage of Q3 is being held low by
Q2, it makes no difference what state Q1 is in.
8-363. If LIVID is low while LVID is high, the input of U1B releases
Q1 to turn on while UlA holds Q2 off. The voltage drop across VR2,
CR6 and Q1 establishes an intermediate base voltage on the emitter
follower Q3, and the video is at an intermediate intensity level.

8-155 DD

Service - Model 64110A
Table 8-47.

8-364.

Video Truth Table

LVID

LIVID

FUNCTION

L

H

NORMAL BRIGHTNESS

L

L

NORMAL BRIGHTNESS

H

L

HALF BRIGHTNESS

H

H

OFF

2500 Hz TONE GENERATOR SCHEMATIC DESCRIPTION.
FIGURE 8-27, U7.

8-365. Timer U7 is a monolithic timing circuit that is operated in
the astable (freerunning) mode to generate a 2S00 Hz tone. The tone
frequency is determined by R39, R40 and C30. The output of U7 controls Q9 which in turn modulates the five volts, appearing across R42,
with the 2S00 Hz tone signal.
8-366.

DISPLAY ENABLE LATCH SCHEMATIC DESCRIPTION.
FIGURE 8-26; USA, B.

8-367. The latch U5A/B is found on the flyback A7 board.
Latch
USA/B is set simultaneously with the activation of the beeper start
pulse generator. When U5A/B is set, the display-on signal (HDE) is
produced which is sent to the display driver to activate the CRT display. U5A/B is reset whenever system power is cycled off and on and
whenever a power interrupt (LIR15) is generated by the mainframe power
supply.
8-368.

HORIZONTAL SWEEP AND HIGH VOLTAGE SCHEMATIC DESCRIPTION.

8-369. When low Horizontal Sync (LHSYN) occurs, the falling edge
triggers the single shot UlA. By adjusting the pulse width of U1A,
the falling edge of the output of UlA is being delayed in triggering
UlB, thus providing horizontal position control (TP3). The pulse
width of UlB is fixed (TPS).
8-370. The negative output of UlB gets reinverted by u4c (a high
voltage output, open-collector inverter). u4c switches Q1 off and on
to drive current through T1. When T1 turns Q2 on, current is drawn
from the 12V suPPly through the primary of T2 and the other secondary
of T1. Q2 drives the current through the yoke for horizontal deflection.
CR4 and c4 form the rectifier/filter for the +40v supply. The
+12KV supply is internally rectified by the flyback, T2, with the
aquadag of the CRT acting as the filter. The -40v supply is rectified
and filtered by CR6 and C11, aided by clamp VR1.
The intensity and
focus voltages are formed by voltage divider networks supplied by CRS.

8-1S6 DD

Service - Model 64110A
8-371. When low Vertical Sync (LVSYN) occurs, it's inverted through
the high voltage, open-collector output, U4A to drive the inverting
input of the current mode op-amp U2B which is configured as an integrator. Variable feedback from U2A provides a means of adjusting vertical gain. The threshold detector, U2C, drives the complementary
pair, Q4 and Q5, for Vertical Sweep (TP1).
8-372. LVSYN is also used to switch Q3 on and off. Q3, C22 and blocking diode CR8 form a voltage doubler circuit to double the voltage
available to U2 and the pair, Q4 and Q5, during retrace (see signal on
U2P14).

8-157 DD

Service - Model 64110A

5

4

2

Horizontal Sync PI, Pin 55

5

4
VI

~3

o
>

2

2

3

4

5

6

7
8
9
MILLISECONDS

10

II

12

13

14

15

Vertical Sync PI, Pin 56

Figure 8-24.

8-158 DD

Horizontal and Vertical Sync Waveforms

16

Service - Model 64110A
NOTES

8-159 DD

Service - Model 64110A
NOTES

8-160 DD

Service - Model 64110A

r---------------,

I

~10V

(TO VIDEO AMP)

r----------- Q+

-------1
HORIZONTAL PoSN.

~~

HORIZONTAL

DISPLAY

0

V

I

I

~HHSYNDI

I

LATCH

?\JL SE

GEN

SIZ E

I

I
I

I

I

I
I

SINE E"P
GEN

--:-_-...:.."'.-OV'---l __ - I - "1

L -_ _ _ _ _ _

I

I

I

I

I

I

<--------+------1- - - -

EIIJASL E

LHSYH

1

FOCUS

I---J~--=--+I--"""'-~"
tiOftlZOHTAL HoRlZONTld..

P---, S

I

~---+I----~ ___ -~

S YNC

,.::L....=B..::.,E::....;,E

,

I

I
I
I

t-------.-IR

+/:lKY'

HIG;!
VOI..TAftE

L-------------

l _______________ ,
VERlICltL

~E
~

VER.TICAl

I

I

I

I

I

I

1)

,I

I

II

f--_+l_+-_ _ _+--I

SWEEP
Gftl

lVSYN

i

I

I

I

L ____ --.I

I

'~4DV

(Fi\oM Hl~H Vt>LTA4EJ

I
I

I
+1;NDl>

bDRET

I
I

+5V

lyle
LIVIl>

VIDEO
AMP

I

CZ AXIS)

I
I
L ____ - 1------ - - - - -

f--

---- -

-- -

-----

30

Figure 8-25.

Display Driver Block Diagram
8-161 DD

Service - Model 64110A

I
coC")

TP1

J2

TP2
LVID

~

• C22.

a::"'"

i

I

a:: a::

o•

U1

0)

o

U

I

I

o

~

0)

I

I

a:: a::

o
I

A6W1

a:: a::
I I

it)

,....

o

lebo

a:

(0

r - --,
I

GND
LVSYN

CO
,....
a::
I

"I':t"l':tit)
I

0

I

a::

~
I~

04

I

0,.... ....

U2

J1

I

I

I
.....
,....

I

a::

C20

I

zO

V~~~ O~

TP9
~
LHSYN
....
TP10 VRAMP
LHORDR

I
0)

0

I

it)

N

a::

I

•

a::1~

I

a:: a:: a:: a:: a::
I I I I I

Om

•
U4

I

~I

N

a:: .....

I

CO

,....

I

-I

0

0

o.

I

-R1-CR1-

I •

•

r

~ ~I U7!

U6

CO
C")

a::

I

C")C")

OS

U

07 I

D D~

a:: a::
I I -R3S-C3-

--C2

Display Driver Component Locator
8-162 DD

-R40-R39-

I

I I
..... (0

CR14

TP11

-VDEF

-C24-C34-

us

TP6

VRTCDBEL
BEEPTONE

TPS

a::

-C2S-

~

C")

I

"I':t

A

B

1

C")

,....

LS1

C")

C")

a::
I
-C11-

a:: 1
L __ J

GND

N

fl

~r---'

a::

I~

~I

I

a::

C1S

o,....

I

-R30-

01
Z«I

.....I"'"
a::
a:: >

TP7
+VDEF

I
CO

0

~

0)

U3

'i I I

CR12 CR11

N

I
~ ~ ~

~ N

I

I

03

~ O~!O ~

o 9~ a::

C\I

I

TP7
+VDEF

•

~

M

-R30----C1S---C11-R1-CR1-

I

U4
M
,...
o.

C\I

U6

0

I

I%:

I
I

A

,...

'III:t

I

...... CD

-C2S-

CO
M

I%:

CR14

I

M

M

1%:1%:

09

07

DD 0
C\I

'III:t

I%:

I I -R3S-C3-

-R40-R39-

-C34-

an

OS

TP11

-VDEF

-C24-

US

I

TPS

•

I •

TP6

VRTCDBEL
BEEPTONE

I

CO

--C2

Display Driver Component Locator

8-164 DD

M

I%:

0 .....I

B

I
C\I

I

LS1

GND

U3

VGAIN
TP9
an
en
a.
,...
LHSYN
I- 0
TP10 VRAMP
LHORDR

I~

~I

I

'III:t

I%:

I

G
I I I

en..-

0

C\lMM

000

I I I

Service - Model 64110A

L-6eeP

~

....,-

n

'0

tJL

'"
,,~

~31-/
"~IK.

+<)

13

u
c.I-ITt.. vt,..T"

1\

~

c3'

,O/~
\AI'

c.~'O

~

,0' C\f'-

;;.

T~I64E.A.:.

r
'0

~

:r
+6

i>1":s{ ,~

- -- --

,--,1..----

Figure 8-27.
Beeper, Display Driver Schematic 2 of 2
8-165/(8-166 blank) DD

Service - Model 64110A
8-373.

MNEMONICS.

8-374. Signals in the 64110A have been assigned mnemonics that describe the active state and function of the signal line. A prefix letter (H, L, P, or N) indicates the active state of the signal, and the
rema1n1ng letters indicate its function. An H prefix indicates that
the function is active in the high state; an L prefix indicates that
the function is active in the low state. Mnemonics with no L or H
prefix should be assumed H. The prefix P indicates that the function is active on the positive-going transition and an N means the
function is active on the negative-going transition. Mnemonic definitions are listed alphabetically in table 8-48.
Table 8-48. Mnemonics (1 of 11)
BNCl-4

BNC outputs from rear panel.

CLKIN

Clock Input. Not used.

DOTCLK

Dot Clock.

HADL

High Address Latch. When high, latches the 16 bit address
from the LIDA bus into two 8 bit latches, to be sent out on
the address Bus.

RBG

High Bus Grant. When high, acknowledges Low Bus Request
(LBR) has been received. However, the requesting device
must wait until High External Bus Grant is true before
using the LIDA bus.

HBON

High Beeper On.

HCLKCNTL

High Clock Control. When high, allows HPHI1 and 2 to be
input directly, as opposed to inputing the clock into CLKIN
and having the CPU derive its own HPHI1 and 2.

HDAC

High Data Accepted.
devices.

HDBUF

High Data Buffered. When high, enables two 8
to transfer data from ROM to the data bus.

HDCO

High Display Counter Zero. Active high, indicates least
significant bit of the display address counter is logic
low.

HDE

High Display Enable.

When high, enables the CRT display.

HDIOl-8

High Data I/O Bits.
transceiver chips.

Connected

HDOUTB

High Data Out Buffered. Inverted LDOUTB.

25 MHz clock for video circuitry.

When high, activates the beeper.

Indicates acceptance of

to

HP-IB

data

I/O

bit

by

all

buffers

lines

via

8-167

Service - Model 64110A
Table 8-48. Mnemonics (2 of 11)
HDOUTD

High Data Out Delayed. When high t indicates to the addressed peripheral device the CPU will write data to it. Similar to LDOUT, but delayed until LPHI2.

HEXBG

When high t indicates
High External Bus Grant.
requesting device that it may use the LIDA bus.

HINT

High Interrupt.

HIODO-15

High Input/Output Data 0 through 15.
appears on device side of transceiver.

HIR

High Interrupt Request RS232 Write. When high t the CPU
being requested to write to the RS232 port.

HIR
(DELTA)T

High Interrupt Request Delta Time.
from the delta-time circuitry.

HIRH

High Interrupt Request High. The only high priority interrupt which is sent to the CPU to inform it that power is
failing.

HIRH CLR

High Interrupt High Clear.
level interrupt latch.

HIRHP-IB

High Interrupt Request HP-IB. When high, it requests a low
priority interrupt of the processor allowing access through
the HP-IB port.

HIRKB

High Interrupt Request Keyboard. When high, a low priority
interrupt is sent to the processor requesting it to service
the keyboard.

HIRMINI

High Interrupt Request Mini.
When high a low priority
interrupt is sent to the processor requesting it to service
the mini drives.

HIR
RS232 RD

High Interrupt Request RS232 Read. When high,
being requested to read from the RS232 port.

HIRL

High Interrupt Request Low. An external device requests an
interrupt by pulling this line high. HIRL is the lowest
priority
interrupt,
and
has
no preempt abilities,
therefore, must wait its turn. HIRR and LPOP can preempt
HIRL.

8-168

to

the

Inverted LINT.
Inverted

LIODO-15;
is

Interrupt signal coming

When high, it resets

the

the

high

CPU

is

Service - Model 64110A
Table 8-48. Mnemonics (3 of 11)
HIR15

High Interrupt 15.
Generated
in
power
supply
to
indicate that a power failure is imminent and causes high
level interrupt HIRH.

BKAo-6

High Keyboard Address.

BKYDET

High Key Detect. Indicates a key is depressed and will step
the keyboard scan and send an interrupt to the processor if
this is a key change.

BMSTR

High Master.

HPBOOTO-1

Boot signals from rear panel. Determines how instrument is
booted; PV, flexible disc drive, system bus, etc.

HPCLK1-2

High Processor Clock 1 and 2. Two complementary,
lapping clocks; required by the CPU.

HPHI1-2

High PHI 1-2.
Two complementary, nonoverlapping clocks
required by several devices on the CPU/IO board for timing.

HPRAS

High BPC Row Address Strobe. Active
high, indicates
processor accessing RAM. Used only for Signature Analysis
troubleshooting.

HPWE

CPU Write Enable. Active high, enables
either into RAM or CRT controller.

HRAL

High Register Access Line. When an address on the LIDA bus
is within the range reserved for register designation,
HRAL goes high to prevent external memory from responding
to any memory cycle having the same address.

HRD

High Read. When high, indicates the CPU will read from
devices external to it. When low, the CPU will write to
devices such as memory.

HRDW

High Read/Write. When high, indicates the CPU will read
from devices external to it. When low, the CPU will write
to devices such as memory.

BROM

When
high,
High Read Only Memory.
CPU is addressing ROM (0000-4000 HEX).

HSCLK1

High System Clock 1.

HSTB

High Strobe. Complement of LSTB. When high, and in the
write mode, indicates the data bus has valid information on
it. When high and in the read mode, indicates the CPU is
not driving the bus, and the device addressed can now drive
it.

Used to decode keyboard.

System is acting as master on the bus.

write

nonover-

operation

indicates

the

A 6.25 MHz clock for CPU/IO board.

8-169

Service - Model 64110A
Table 8-48. Mnemonics (4 of 11)
HSYNC

High Sync.
opcode.

L25MHz

Low 25 MHz Clock. For general purpose bus use.

LAO-15

Low Address 0 through 15. A 16 bit bus demultiplexed from
the LIDAO-15 bus.
Used by the CPU to address various
devices in the system, including ROM. The bus is sent only
from the CPU.

LADDCLK

Low Address Clock. Active low, clock
ments the display counters.

LATN

Low Attention. Ties to HP-IB ATN line via transceiver.
Defines type of data on data bus; address/commands or data.

LBE

Low Bus Enable.

LBEEP

Low Beep. Output from LBEEPEN.

LBEEPEN

Low Beep
enabled.

LBIOSB

Low Buffered
LIOSB.

LBL

Low Byte Left. When low, indicates the left or upper eight
data bits of a memory cycle will be used, as opposed to the
right or lower eight data bits and is used only when LBYTE
is low.

LBR

Low Bus Requested. Provides the way for an external device
to request uninterrupted use of the LIDA bus.

LBYTE

Low Byte. When low, indicates that a memory cycle is to
involve an eight bit byte, rather than the full sixteen
bits of the word.

LCHAR

Low Character Clock.
controller chip.

LCS

Low Chip Select. Active low, enables both
write functions for the CRT controller.

LDO-15

Low Data 0 through 15.
A 16 bit bidirectional bus
connected to the LIDAO-15 bus. Used to transfer data to
and from the CPU. When LSTB is low, data is present on
bus.

8-110

When high, indicates the

CPU

is

signal

fetching

that

an

incre-

Tied to ground.

Enable.

When

low,

Input/Output

the

Strobe.

Character

beeper

circuits

Buffered

clock

version

are
of

used

by

CRT

the

read

and

Service - Model 64110A
Table 8-48. Mnemonics (5 of 11)
LDAV

Low Data Valid. Ties to HP-lB
chip. Indicates availability
data bus.

DAV line via transceiver
and validity of data on the

LDBUF

Low Data Buffered. When low, enables two 8 bit buffers
transfer data from the ROMs to the data bus.

LDCAS

Low Display Column Address Strobe. Active low, indicates
data request from CRT controller is being serviced.

LDMAR

Low Direct Memory Access Request.
A peripheral device
pulls this line low when it wants direct access to memory.

LDMARQ

Low Direct Memory Request. Used to request direct memory
access cycles to transfer data to the outbound FIFO or from
the inbound FIFO. See LHLT.

L(DELTA)T

Low Delta Time.
When low it clears the
interrupt and resets the auto-reset counter.

LDOUT

Low Data Out. When low, indicates to the addressed peripheral device, the CPU will write to it.

LDOUTB

Low Data Out Buffered.

LOOUTD

Low Data Out Delayed. Complement of HDOUTD.
When low,
indicates to the addressed peripheral device the CPU will
write data to it. Similar to LDOUT, but delayed until
LCLK2.

LDRQ

Low Data Request.
requesting data.

LEO I

Low End Or Identify.
Bidirectional line that ties to
HP-lB EOl line via transceiver chip. Indicates end of data
transfer or identifies initiation of polling operation.

LERA

Low Extended Register Addressing. When pulled low by an
external device, the internal registers have increased
addressing range on the LIDA Bus.

LFLG

Low Flag. Can be tested by software. Used as a flag
by
any peripheral device connected to the CPU. The peripheral
devices are wire OR'ed to this line.

LHLT

Low Halt. Can be tested by software.
the CPU by HP-lB.

LHP-lB

Low HP-lB.

to

LlR(DELTA)T

Buffered version of LDOUT.

Active low signal

from

CRT

Used as a

controller

flag

to

When low the HP-IB port is being accessed.

8-171

Service - Model 64110A
Table 8-48. Mnemonics (6 of 11)
LHSYN

Low Horizontal Sync.
Active low, signal from display
controller to display driver circuitry that enables the
horizontal electron beam retrace function.

LIBE

Low Interrupt Buffer.

LICl-2

Low Interface Control 1 and 2. These two lines can provide
up to four states used to control peripheral devices.
How
these lines are controlled is determined by software.

LICIB

Low Interface Control 1 Buffered. LIC1 signal
buffered once.

after

being

LIC2B

Low Interface Control 2 Buffered. LIC2 signal
buffered once.

after

being

LIC1D

Low Interface Control 1 Delayed. LIC1
buffered twice.

signal

after

being

LIC2D

Low Interface Control 2 Delayed. LIC2
buffered twice.

signal

after

being

LID

Low ID.

LIDAO-15

Low Instruction/Data/Address 0 through 15.
A 16 bit
bidirectional
bus the CPU uses to communicate over.
Information is true low.
In this system, the bus is
demultiplexed into separate address and data buses.

LIFC

Low Interface Clear.
Ties to HP-IB
IFC
line
via
transceiver chip. Places I/O system into known idle state.

LIMASK

Low Interrupt Mask Address.
mask latch.

LINSYN

Line Synchronization. Generated by the power supply. The
sync pulses are counted by delta time counter which reaches
its terminal count in about 2 seconds at which time reset
signal LPOP is generated if the CPU doesn't reset the
counter before the terminal count is reached.

LINT

Low Interrupt. The CPU pulls this line low to poll the
input/output bus to determine which peripheral device needs
service.

LINT MASK

Low Interrupt Mask. When low the interrupt mask is enabled
to allow decoding of the low level interrupts.

8-172

Enables interrupt buffer.

Enables Card Select to output ID of option.

When

low,

enables

interrupt

Service - Model 64110A
Table 8-48. Mnemonics (7 of 11)
LIODO-15

Low Input/Output Data 0 through 15. A 16 bit bidirectional
bus. The CPU uses this bus to communicate with I/O ports.
Information is true low, and is used in conjunction with
LPABO-3.

LIOSB

Low Input/Output Strobe. When low, indicates the
the input/output bus is valid.

LIR
(DELTA)T

Low Interrupt Request Delta Time.
Generated from HIR
(DELTA)T.
When low, it requests a low priority interrupt
of the CPU and if not serviced in 2.3 seconds a LPOP will
be generated, in the auto-reset circuit, resetting the processor.

LIRHP-IB

Low Interrupt Request HP-IB.
Generated from HIRHP-IB.
When low, it requests a low priority interrupt of the processor allowing access through the HP-IB port.

LIRKB

Low Interrupt Request Keyboard.

LIRMINI

Low Interrupt Request Mini. Generated from HIRMINI.
When
low a low priority interrupt is sent to the processor
requesting it to service the mini drives.

LIR
RS232 RD

Low Interrupt Request RS232 Read. Generated from HIR RS232
RD. When low, the CPU is being requested to read from the
RS232 port.

LIR
RS232

Low Interrupt Request RS232 Write.
Generated from HIR
RS232 WH.
When low the CPU is being requested to write to
the RS232 port.

WR

data

on

Inverted HIRKB.

LIRH

Low Interrupt Request High.
Generated from HIRH. An
external device requests an interrupt by pulling this line
low. LIRH has a higher priority than Low Interrupt Request
Low (LIRL), and can preempt the lower priority even while
it is in process. LPOP can preempt LIRH.

LIRHCLR

Low Interrupt High Clear.
Generated from HIRHCLR.
low it resets the high level interrupt latch.

LIRL

Low Interrupt Request Low.
Generated from HIRL.
An
external device requests an interrupt by pulling this line
low. LIRL is the lowest priority interrupt, and has no
preempt abilities, therefore, must wait its turn. LIRH and
LPOP can preempt LIRL.

LIR15

Low Interrupt 15. Generated from HIR15 in power supply to
indicate that a power failure is imminent and causes high
level interrupt LIRH.

When

8-173

Service - Model 64110A
Table 8-48. Mnemonics (8 of 11)
LIVID

Low Inverse Video. Active low, signal from display controller to display driver circuitry that enables halfbright dot on CRT screen.

LKYBD

Low Keyboard. When low and the interrupt mask is
LIRKB is generated.

LLCAS

Low Lower Byte Column Address Strobe.
column address to lower byte in RAM.

LLDCNT

Low Load Display Counter.
Active low, loads the first
address
of
display memory into the display address
counters U58, U59, and u60.

LLRAS

Low Lower Byte Row Address Strobe.
row address to lower byte in RAM.

LMAPl-3

Low Peripheral Addresses. Selects one of nine peripheral
address commands used to enable or activate various I/O
circuits.

LMSYN

Low Memory Sync. A signal from addressed devices.
When
low, forces the CPU to wait until the addressed device can
complete the read or write operation.

LOPCODE

Low Opcode. When low, indicates to a HP Model 1611A Logic
State Analyzer the information on the data bus is an
opcode. Used for factory troubleshooting.

LPABO-3

Low Peripheral Address Bus 0-3. Identifies which one of 16
peripheral devices will be involved in an I/O operation.

LPAO-3

Low Peripheral Address Bus 0 through 3.
Identifies which
one of 16 peripheral devices will be involved in I/O operation.

LPBE

Low Processor Buffer Enable.
Always
internal CPU buffers for the LIDA bus.

LPBO

Low Processor Buffer Out. Controls the direction of the
CPU's internal, bidirectional, LIDA buffers. When low,
information is transmitted from the CPU.

LPCAS

Low Processor Column Address Strobe. Active low, indicates
CPU is accessing RAM in either read or write operation.

LPFAIL

Low Power Fail. Active low, indicates
too low to operate system.

8-174

When

When

low.

main

low,

low,

enabled,
strobes

strobes

Enables

AC

power

the

is

Service - Model 64110A
Table 8-48. Mnemonics (9 of 11)
LPFS

Low Power Fail Set Address.
When low, sets power fail
latch which in turn provides LPFAIL to the CPU/IO board via
the mainframe bus.

LPHIl-2

Low Clock 1-2. Two complementary,
required by several devices on
timing.

LPDR

Low Processor Drive.
bus.

LPOP

Low Power On Pulse. When low, initializes and prevents the
CPU from running. When LPOP is released, the processor
begins operation at address 20 Hex. LPOP is synchronized
with LPHI1 before being input to the CPU. LPOP can preempt
LIRL and LIRH.

LPOPB

Low Power On Pulse Buffered.

Buffered LPOP.

LRKBD

Low Read Keyboard.
keyboard.

data

LRAMCLK

Low RAM Clock.
functions.

LRSRD

Low RS-232C Read Address. When low, serves as read command
to RS-232C transceiver (USART).

LRSWR

Low RS-232C Write Address.
When low,
command to RS-232C transceiver (USART).

LRS232RD

Low RS232 Read.
When low and the
enabled, LIR RS232 RD is generated.

interrupt

mask

is

LRS232WR

Low RS232 Write.
When low and the
enabled, LIR RS232 WR is generated.

interrupt

mask

is

LSCLK1

Low System Clock 1.
system.

LSLOT SEL

Low Slot Select.
enabled.

LSMC

Low Synchronized Memory Complete.
in this system.

LSELO-4

Low Slot Select. Goes to each of the 5 card slots and
causes each card to generate its unique ID code. LIDEN must
also be present.

nonoverlapping clocks;
the CPU/IO board for

When low, the CPU is driving the LIDA

When low

A 12.5

MHz

on

clock

data

for

RAM

bus
and

serves

A 6.1 MHz clock used

is

from

display

as

write

throughout

When low the slot select buffer (UXX)
A CPU output,

not

the
is
used

8-115

Service - Model 64110A
Table 8-48. Mnemonics (10 of 11)
LSTB

Low Strobe. Active low, during write operation, indicates
data bus information is valid; during read operation indicates CPU is not driving the data bus and addressed device
can drive data bus.

LSTM

Low Start Memory. Used to initiate a memory cycle.
When
low, indicates that the information on the address bus is
valid.

LSTS

Low Status. Can be tested by software. Used as a
flag
by
any
peripheral
device
connected
to
the CPU.
The peripheral devices are wire OR'ed to this line.

LUMC

Low Unsynchronized Memory Complete.
CPU to complete its memory cycle.
make the processor wait, due to long
LMSYN low, causing LUMC to go high.
CPU must wait.

LUCAS

Low Upper Byte Column Address Strobe.
column address to upper byte in RAM.

LUPB

Low Upper Byte. Active low, indicates only upper eight
bits of data bus involved in memory operation. When this
signal is high, indicates lower eight bits being used.
LUPB is gated by LBYTE.

LURAS

Low Upper Byte Row Address Strobe.
row address to upper byte in RAM.

LVID

Low Video. Active low, signal from display controller to
display
driver
that enables full-bright dot on CRT
screen.

LVSYN

Low Vertical Sync. Active low, signal from display controller to display driver circuitry that enables the
vertical electron beam retrace function.

LWLB

Low Write Lower Byte.
in RAM.

LWRT

Low Write.

LWUB

Low Write Upper Byte.
in RAM.

PAO-1S

Peripheral Address 0 through 15. Outputs from
address decoder used to select I/O functions.

8-176

When low, allows the
If the memory needs to
access times, it pulls
When LUMC is high the
When

When

low,

low,

strobes

strobes

When low, writes data to lower

byte

Active low, CPU writes to addressed device.
When low, writes data to upper

byte

peripheral

Service - Model 64110A
Table 8-48. Mnemonics (11 of 11)
RAMCLK

RAM Clock.

Timing signal used in all RAM operations.

(Low) Remote Enable.
transceiver.
Enables
programming data.
Indicates

Ties to HP-IB
REN line via
to
provide
alternate
devices
sequencer U2

RCARRY

Ripple Carry.
initial state.

RFD

(High) Ready For Data. Indicates that devices are ready to
accept data. Ties to HP-IB NRFD line via transceiver chip.

R/W

Read/Write Command. When high, specifies that the PHI chip
perform a write function; when low, specifies a read
function.

SHUTDOWN

Is generated in several
turning off the PWMs.

SRQ

(Low) Service Request.
Ties to HP-IB SRQ line
via
transceiver.
Indicates
a
need
for service; causes
interrupt of current sequence in cpu.

places

and

has

is

returned

responsible

to

for

8-177/(8-178 blank)

HEWLETI' PACKARD
MODEL 64110A
MAINFRAME FLEXIBLE DISC DRIVE
(FLOPPY)

REPAIR NUMBERS
This mainframe manual applies directly to Models with
serial numbers prefixed 2103A - 21038A.

©

copyright Hewlett-Packard Company/Colorado Springs Division 1982
1900 Garden of the Gods Road, Colorado Springs, Colorado, U.S.A.

All Rights Reserved

Manual Part Number 64110-90901
Microfiche Part Number 64110-90801

PRINTED: MARCH 1982

SAFETY SUMMARY
The following general safety precautions must be observed during all phases of operation, service,
and repair of this instrument. Failure to comply with these precautions or with specific warnings
elsewhere in this manual violates safety standards of design, manufacture, and intended use of the
instrument. Hewlett-Packard Company assumes no liability for the customer's failure to comply
with these requirements.

GROUND THE INSTRUMENT.
To minimize shock hazard, the instrument chassis and cabinet must be connected to an electrical
ground. The instrument is equipped with a three-conductor ac power cable. The power cable
must either be plugged into an approved three-contact electrical outlet or used with a three-contact
to two-contact adapter with the grounding wire (green) firmly connected to an electrical ground
(safety ground) at the power outlet. The power jack and mating plug of the power cable meet
International Electrotechnlcal Commission (I EC) safety standards.

DO NOT OPERATE IN AN EXPLOSIVE ATMOSPHERE.
Do not operate the instrument in the presence of flammable gases or fumes. Operation of any
electrical instrument in such an environment constitutes a definite safety hazard.

KEEP AWAY FROM LIVE CIRCUITS.
Operating personnel must not remove instrument covers. Component replacement and internal
adjustments must be made by qualified maintenance personnel. Do not replace components with
power cable connected. Under certain conditions, dangerous voltages may exist even with the
power cable removed. To avoid injuries, always disconnect power and discharge circuits before
touching them.

DO NOT SERVICE OR ADJUST ALONE.
Do not attempt internal service or adjustment unless another person, capable of rendering first aid
and resuscitation, is present.

DO NOT SUBSTITUTE PARTS OR MODIFY INSTRUMENT.
Because of the danger of introducing additional hazards, do not install substitute parts or perform
any unauthorized modification of the instrument. Return the instrument to a Hewlett-Packard
Sales and Service Office for service and repair to ensure that safety features are maintained.

DANGEROUS PROCEDURE WARNINGS.
Warnings, such as the example below, precede potentially dangerous procedures throughout this
manual. Instructions contained in the warnings must be followed.

I WARNING

I

Dangerous voltages, capable of causing death, are present in this instrument.
Use extreme caution when handling, testing, and adjusting.
88-1-1·76

Table of Contents - Model 64110A

Section

I

II

III

Page

GENERAL INFORMATION ..........................•.........•..... 1-1
1-l.
1-3.
1-5.
1-1l.
1-12.

Introduction .........••.......•.....•.................. 1-1
Safety Considerations ........•......................... 1-1
Physical Description ................................... 1-1
Environmental and Physical Specifications .............. 1-2
Operating Environment ...................•.......•...... 1-2

1-14.
1-16.
1-17.
1-18.
1-19·

Storage Environment .................................•.. 1- 2
Recording Characteristics ..•....................•••.... 1-2
HP Physical Track Format ....................•.......... 1-2
Media Life ............................................. 1-2
Performance Specifications .......................•..... 1-2

1-20.
1-2l.
1-23.
1-25.
1-29.

Alignment Limits ..................................•.... 1-2
Phys ical Dimens ions •••.••.............................. 1-3
Power Requirements ....•............•................... 1-3
Flexible Disc Drive Assemblies .••...................... 1-3
Recommended Test Equipment ..•.......................... 1-5

INSTALLATION AIm REMOVAL .••.••...........•....•........•.•.. 2-1
2-l.
2-4.
2-7.
2-1l.
2-13.
2-15·

Introduction .....••..•................................ 2-1
Flexible Disc Drive Removal Procedure ................. 2-1
Flexible Disc Drive Jumper Configuration .............. 2-3
Termination Resistor Packages ......................... 2-4
Soldered Jumpers .•..•.................•.........•..•.. 2-4
Packaging ............................................. 2-4

2-16.
2-18.
2-20.

Original Packaging ....•..........................•.... 2-4
Other Packag ing ...•................•..•.....•......... 2 - 4
Flexible Disc Media ..•................................ 2-4

OPERATION ........................•...................•...... 3-1
3-1.
3-3.
3-5.
3-7.
3-9.

IV

TABLE OF CONTENTS

Introduction .......................................... 3-1
Operating Cleanliness .................•............... 3-1
Disc Loading .......................................... 3-1
Write Protection ....•.................•...........•... 3-1
Formatting the Disc .•............•.................... 3-2

PERFORMANCE TESTS ............•...........................•.. 4-1
4-l.
4-5.
4-10.
4-13.
4-14.

Introduction ................................•......... 4-1
Performance Verification Test Procedure ..............• 4-1
Operation Verification Tests ...........•........•..... 4-4
Media Change Test ...........................•....•.... 4-7
Motor Control Test ..............................•..... 4-7

i

Table of Contents - Model 64110A
Section

V

Drive Ready Test ........••.••.••...............•..•..• 4-8
Drive Select Test .•....•.....•.....................•.. 4-8
FOI1llat a Disc ......................................... 4-8

4-22.

Soft Error Rate Test ..••...•.•.•..................... 4-10

In troduct ion .......................................... 5-1

5-4.
5-6.
5-7.
5-9·

Test and Adjustment Drive Access Procedure ...•.•..•.•. 5-1
Field Adjustments .......•.......•................•.•.. 5-1
Spindle Motor Speed Adjustment ...•......•.....•....... 5-1
Known Primary Power and Fluorescent Lighting .....•.... 5-2

5-11.
5-13.
5-15.
5-18.
5-19.

Primary Power Frequency is Unstable or Unknown •....•.• 5-2
Spindle Drive Belt Adjustment ...•.•.........•....•.... 5-3
Factory Adjustments ....•.............................. 5-4
Required Tools and Test Equipment ............•......•. 5-5
Radial Head Alignment ....•............................ 5-5

5-21.
5-23.

Track 0 Switch Adjustment ............................. 5-7
Index Emitter/Detector Adjustment ..................... 5-9
Write Protect Switch Adjustment ........•..••..•.•.... 5-11

REPLACEABLE PARTS .......•...••••............................ 6-1
Introduction ...............••.•..............•....••.. 6-1
Abbreviations ........•...•...••...................•••. 6-1
Replaceable Parts List ...•.••.•••............•....•... 6-1
Ordering Information ......................•......•.... 6-1
Direct Mail Order System .............................. 6-1

MANUAL CHANGES ...........•.........•...............•........ 7-1
General ............................................... 7-1

SERVICE ..•..•...................•.................•......... 8-1

8-l.

ii

Head Azimuth Alignment Check ••.....•.......•......•... 4-8

5-l.

7-1.
VIII

Head Alignment Test ................................... 4-8

ADJUSTf.iENTS . • • • • . • . . . . • . • . . . . • . . . • . . . • . . . . . . . . . . • . . . . . . • . . .• 5-1

6-1.
6-2.
6-3.
6-4.
6-5.
VI I

Page

4-15.
4-16.
4-17.
4-18.
4-20.

5-25·
VI

TABLE OF CONTENTS

8-4.
8-6.
8-17.
8-20.

Introduction ....................•..................... 8-1
Safety Considerations ................................• 8-1
Flexible Disc Recording Fundamentals .................. 8-1
Floppy Block Diagram Theory ........................... 8-4
RS-232/Mini Control Block Theory ...................... 8-4

8-23.
8-25.

Interface Control Latch ...••......•.................•. 8-5
DMA/CPU Address Selector ..•.......•................••. 8-5

Table of Contents - Model 64110A
Section

TABLE OF CONTENTS

Page

8-27.
8-29.
8-31.

Signature Analysis Stimulus Latch ..................... 8-5
CPU Interface/DMA State Machine ................•...... 8-5
Data Latches ...................................•.•...• 8-5

8-33.
8-35.
8-37.
8-39·
8-41.

4mIz Oscillator ....................................... 8-6
Mini Drive Controller (MDC) Chip ...................... 8-6
Drive Control Latch/Buffer ..................•.....•... 8-6
Drive Status Buffers .................................. 8-6
Data Separator ........................................ 8-6

8-43.
8-45.
8-47.
8-49.
8-51.

Disc Drive Multiplexer and Control Buffering ....•.•... 8-6
Disc Drive Block Theory ...........................•... 8-8
Index Pulse Shaping Network ........................... 8-8
Write Protect Sensor .•••.....•............•........... 8-8
Track 0 Switch •.......•...........................•... 8-8

8-53.
8-58.
8-60.
8-62.
8-65.

Spindle Motor Drive Control ........................... 8-8
Head Position Control •...........•.................... 8-8
Power On Circui t ...............................•...... 8-9
Data Circuitry ........................................ 8-9
Wri t ing Data .....••................................•. 8-11

8-76.
8-82.
8-83.
8-94.
8-101.

Reading Data ......................................... 8-12

8-103.
8-105.
8-107.
8-109.
8-111.

Troubleshooting .•..........................•......... 8-16
Performance Verification (PV) Test Descriptions ...... 8-16
Floppy Controller Response Test ...................... 8-16
Select Test .......................................... 8-16
Track 00 Test .....•.................................. 8-17

8-113.
8-115.
8-117.
8-119.
8-121.

Read Track 0 Test .................................... 8-17
Read Track 34 Test ........•.......................... 8-17
Track 34 Check Test .................................. 8-17
Track 34 Write Test .................................. 8-18
Track 34 Read/Verify Write ........................... 8-18

8-123.
8-125.
8-127.
8-130.
8-133.

PV Error Messages .................................... 8-18
Description of Error Codes and Troubleshooting ....... 8-19
Troubleshooting Hints ................................ 8-23
Troubleshooting Using Signature Analysis (SA) ........ 8-24
Key Signatures ....................................... 8-24

RS-232/Mini Control Theory of Operation ...•....••.... 8-13
Mini Control .............•..........••..........•.... 8-13
Mini Control Data Separator .....•....•............... 8-15
RS-232/Mini Drive Theory of Operation ................ 8-16

iii

Table of Contents - Model 64110A
Section

iv

TABLE OF CONTENTS

Page

8-135.
8-138.
8-140.
8-142.
8-144.

In terrace Loop ...............•••...•...........•..... 8 - 2 4
Data Separator Loop ...............•.........••.•.•.•. 8-25
Service Sheet Layout ........•......•..........•...... 8-49
RS-232/Mini Control and Drive Service Sheet Layout ..• 8-49
Logic Convent ion ....•................•........••..... 8-66

8-146.
8-148.

Mnemonics ............................................ 8-70

Logic Symbology ....................•..•.......•.••... 8-66

List of Illustrations - Model 64110A
LIST OF ILLUSTRATIONS
Figure

Title

Page

1-1.
1-2.

Physical Dimensions ................................... 1-3
Exchange Assembly ..•...............•.............•.... 1-4

2-1.

Flexible Disc Drive RemovaL ...••..............•.•.•.. 2-2

3-1.

Write Protect Tab Installation ................•.•..... 3-1

4-1.
4-2.
4-3.
4-4.
4-5.

Display Test Pattern .....••.•.•••..•.......•.......•.. 4-2
PV Test Display ....••.............•..•................ 4-2
Floppy Disc Diagnostic Display ...................••.•. 4-6
Floppy Test Menu First LeveL .....•................... 4-6
Floppy Test Menu Second Level ..•.•..................•. 4-7

4-6.

Head Azimuth Waveform ..•..••....................•••.. 4-10

5-1.
5-2.
5-3.
5-4.
5-5·

Spindle Motor Speed Adjustment ..••......•......•.•.... 5-3
Spindle Drive Belt Adjustment ..................•••..•. 5-4
Radial Head Alignment Waveform .•....•....•......•..... 5-6
Head Assembly Retaining Screws ...••.............•..... 5-7
Track 0 Waveform ...................................... 5-8

5-6.
5-7.
5-8.

Track 0 Retaining Screw •........•......•..•....•.•.... 5-9
Index Detector Retaining Screw .•..•.............••... 5-10
Index to Burst Waveform •.•..•....••....•.........••.. 5-11

8-1.
8-2.
8-3.
8-4.
8-5.

ID and Data Field Content ............•.••......••..... 8-2
Media Sector and Track Structure ...............•.•..•. 8-3
Head Positioning Assembly .....•...•.....•.•........... 8-4
Mini Control Block Diagram ............................ 8-7
Mini Drive Block Diagram ......................•.••... 8-10

8-6.
8-7.
8-8.
8-9.

Write Timing Diagram ..••...••.•...•.........•••.••... 8-12
Read Timing Diagram ....•...••.....•...............•.. 8-13
Component Locator for Service Sheet 11A ........•••... 8-50
RS-232/Mini Control Block Diagram
for Service Sheet 11A ........•....•.............••... 8-50
RS-232/Mini Control Service Sheet 11A ..•........•.... 8-51

8-10.
8-11.
8-12.
8-13.
8-14.
8-15.
8-16.

Component Locator for Service Sheet 11B .........•.... 8-52
RS-232/Mini Control Block Diagram
for Service Sheet 11B ••................•............. 8-52
RS-232/Mini Control Service Sheet 11B ................ 8-53
Component Locator for Service Sheet 11C .............. 8-54
RS-232/Mini Control Block Diagram
for Service Sheet 11C ••....•..•.•.................... 8-54
RS-232/Mini Control Service Sheet 11C ......•..•...... 8-59
v

List of Illustrations - Model 64110A
LIST OF ILLUSTRATIONS (Cont'd)

Figure

Page

Title
8-17.

RS-232/Mini Control Component Locator ......•...•••.•• 8-60

8-18.
8-19.
8-20.
8-21.
8-22.

RS-232/Mini Control Service Sheet IlD .....•.••....•.. 8-61
Component Locator for Service Sheet 1 ................ 8-62
Servo Electronics Service Sheet 1 ................•... 8-63
Component Locator for Service Sheet 2 ••....•..••...• 8-64
Drive Electronics Service Sheet 2 ........•...•...••.. 8-65

LIST OF TABLES
Table

1-1.

Page

1-2.

Power Requirements ................................... 1-3
Exchange Assembly ..............•....•.......••..•.•.. 1-5

2-1.

Flexible Disc Drive Jumpers and Functions ....•..••..• 2-3

6-1.

Reference Designators and Abbreviations ....•.••...•.. 6-3
Replaceable Parts List ........•.•...........•.•...... 6-4
List of Manufacturers' Codes ...•.•.•..•..•.....•.... 6-17

6-2.
6-3.

8-1.
8-2.
8-3.
8-4.
8-5.

Mini Floppy PV Error Messages .....•....••...•....•.. 8-18
Description of PV Error Codes ••..•••.............•.. 8-19
SA Loop A ........................................... 8-26

SA Loop B.•..................••.•......•..•......... 8-34
SA Loop M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8 -3 7

8-6.

SA Loop C............. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 39

8-7.

SA Loop D ...........•......•..•.••.•..............•. 8-41
SA Loop E ...................•.•.••.•..•.••....•..... 8-43

8-8.
8-9.
8-10.
8-11.
8-12.
8-13.
8-14.
8-15.
8-16.
8-17.

8-18.

vi

Title

SA Loop F ................•....•.....•..•............ 8-45
SA Loop G ....•..............•...••••..••............ 8 - 46
SA Loop H. . . . . . . . . . . . . . . . . . . . . . . . ., . . . . . . . . . . . . . . . . . . 8 - 47

SA Loop
SA Loop
Service
SA Loop

I........................................... 8 - 48
J ...........•.......•.•.•.......••.......... 8-49
Sheet to Function ........................... 8-49
K .••.••••••••••••••••••••••••••••••••••••••• 8-55

SA Loop L... . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . 8 - 57
Logic Symbology ............•..••.•.................. 8-67
Mnemonics ......................•.•.................. 8-70

General Information - Model 64110A
SECTION I
GENERAL INFORMATION
1-1.

INTRODUCTION.

1-2. This manual contains information and theory necessary to operate,
install, maintain, and troubleshoot the (FLOPPY) flexibe disc drives
in the 64110A mainframe.
1-3.

SAFETY CONSIDERATIONS.

1-4. The flexible disc drive units are installed in a 64110A Mainframe
and contains voltages in +-12 V range. Review the mainframe service
manual for general safety considerations.
1-5.

PHYSICAL DESCRIPTION.

1-6. Each flexible disc drive is a semi-random access mass storage
system employing a flexible magnetic medium. It consists of a servo
electronics circuit board, a drive electronics circuit board, and a
RS-232/mini control board.
1-7. Each drive module contains all the mechanical parts necessary for
physically handling the disc. These include the drive spindle and
motor, 2 heads each having read/write and erase capability, write
protect sensor, track 0 sensor, index sensor, and activity LED on the
front panel.
Each drive module also contains a servo control board
which controls the DC drive motor speed and a drive electronics board
which interprets and generates control signals, controls movement of
the read/write head to the correct position, and also reads and writes
data.
1-8. The flexible magnetic medium used for Local Mass Storage is
called a flexible disc. A disc measures 133.4 mm (5.25 inches) in
diameter and has a 3.8 cm (1.5 inch) hole for alignment on the disc
drive spindle. The disc is enclosed in a protective polyvinylcholride
(PVC) jacket with a slot for access to the recording surfaces. Both
sides of the flexible disc are used for data storage.
1-9. The recording head in the
mechanism driven by a stepper
positioning mechanism operates in
there is no feedback to the drive
actual position of the head.

drive module is positioned by a
motor and taut metal band. The head
an open loop configuration; that is,
electronics board to determine the

1-10. The heads are mechanically coupled to the door mechanism so that
closing of the door (pushing the latch to the left) causes the heads
to make contact with the media.

1-1 AP

General Information - Model 64110A
1-11. ENVIRONMENTAL AND PHYSICAL SPECIFICATIONS.
1-12. OPERATING ENVIROMENT.
1-13. The flexible disc drives may be operated in
environments within the following limits:
a. Relative Humidity: 20~ to 80~ while at 29.4°c
b. Altitude: 0 to 4572 m (0 to 15000 ft)
It should be protected from temperature
condensation within the instrument.
1-14.

(85°F)

extremes

which

cause

STORAGE ENVIRONMENT.

1-15.
The fexible disc drive may be
environments within the following limits:

stored

or

shipped

in

a. Temperature: -41°C to 71°C (-40.SoF to 159.8°F)
b. Relative Humidity: 20~ to 80~ at 29.4°c (85°F)
c. Altitude: 0 to 4572 m (0 to 15000 feet)
1-16. RECORDING CHARACTERISTICS.
1-17. HP PHYSICAL TRACK FORMAT.
a.
b.
c.
d.
e.
f.
g.
h.
i.

Recording Mode: Modified Frequency Modulated (MFM)
Rotational Speed: 300 RPM +-1.5~ (+-4.5 RPM)
Bit Density: 5456 BPI on Track 34
Tracks Per Inch: 48
Sides Per Disc: 2
Tracks Per Sides: 35
Sectors Per Track: 16
Bytes Per Sector: 256 (362 including overhead bytes)
Bytes Per Disc: 286,720 (formatted) 420,000 (unformatted)

1-18. MEDIA LIFE.
a. Revolutions 2,500,000 revolutions on any track.
b. Head Life: More than 15,000 hours of operation with HP media.
1-19.

PERFORMANCE SPECIFICATIONS.

a. Soft Read Errors: 1 in 10 billion bits read on innermost track.
b. Seek Errors: 1 in 10 million seeks.
c. "Soft Error" is defined as an error that cannot be recovered
from using an HP approved retry scheme.
1-20. ALIGNMENT LIMITS.
a. Radial Alignment: 1.1 mils maximum of track center at track 16
measured at 20°C (68°F) and 50~ humidity.
b. Azimuth: 18 degrees maximum clockwise or counterclockwise on
tracks 16 and 34.
1-2 AP

General Information - Model 64110A
1-21. PHYSICAL DIMENSIONS.
1-22. Figure 1-1 illustrates
flexible disc drive unit.

the

physical

dimensions

of

a

single

144.5
15-11/161

14---'--1-

212.72
18-3/81

21.43
17/81

79.37
13-1/81

+

34.92
47.62'
11-3/81 11-7/8,'

~~~~~==~~~

155.57~

127/321~~

~85.72.~
13-3/81

16-1/81

149.22'
15-7/81*

SEE NOTE 3

19.84 . -

NOTES:
1. DIMENSIONS GIVEN AS MILLIMETRES(INCHES).
2. ·DENOTES DIFFERING TANDON DRIVE DIMENSIONS.
3. THIS DIMENSION FROM BACK OF FACEPLATE.

Figure 1-1. Physical Dimensions
1-23. POWER REQUIREMENTS.
1-24. Table 1-1 gives the power requirements for a single or double
flexibl disc drive plus a RS-232/mini control board. The values
include the power-up transient which is considered to be the most
limiting case.
Table 1-1. Power Requirements
With

(1) drive

+5V current use

With

(2) drives

+5V current use

1-25.

=
=

1.7A - 1.8A During PV
3.4A - 3.6A During PV

FLEXIBLE DISC DRIVE ASSEMBLIES.

1-26. The flexibe disc drives used in the 64110A mainframe are Model
HP9130K drives with the following:
1-3 AP

General Information - Model 64110A
1-27. Drive board PiN 09130-66501.
1-28. Mechanical drive assembly with servo board and front panel
PiN 4040-1915 and door latch PIN 4040-1913 and associated hardware.
This part also has an exchange assembly number HP PIN 09130-69600.

OPTI O N #0 10
DRIVE ELE CTR O NI C
PC B OARD
HP PI N 09130-66501

O PTI O N #052
OR
ASS EMBL Y EXC HA NG E NUM B ER
HP PI N 09130-69600

SERVO PC B OARD

Figure

1-4 AP

1-2.

Exchange Assembly

General Information - Model 64110A
1-29.

RECOMMENDED TEST EQUIPMENT.

1-30. Refer to table 1-2 for a list of recommended test equipment.
Table 1-2. Recommended Test Equipment
Product Support Package
Service Kit
Alignment tool or small shank screwdriver
HP 5314A or equivalent frequency counter
Spindle motor adjustment tool PIN 8710-1385
Oscilloscope
HP 1740A or equivalent
Alignment Disc
PIN 9164-0151
Torque Driver
PiN 8710-0670
#1 Posidriv Screwdriver
PIN 8710-0899
#2 Posidriv Screwdriver
PIN 8710-0900
3/16 Thin Wall Nutdriver
PIN 8720-0001
5004 or 5005 Signature Analyzer.

1-5/(1-6 blank) AP

Installation and Removal - Model 64110A
SECTION II
INSTALLATION AND REMOVAL
2-1.

INTRODUCTION.

2-2. This section contains information for
unpacking,
initial
inspection, installation and removal of the flexible disc drives.
2-3. The flexible disc drive units are installed in a 64110A Mainframe
at the factory. Therefore, the initial inspection procedure assumes
the units are installed. An installation and removal procedure will
be included for installing a new unit or removing a defective unit.
2-4. FLEXIBLE DISC DRIVE REMOVAL PROCEDURE.
2-5. The following procedure should be used when removing
disc drive unit from a 64110A Mainframe.
a. Switch power OFF on the mainframe and disconnect
cord.

the

a

flexible

AC

power

b. Remove the top and bottom covers. There is one screw for each
cover on the rear that holds it in place. Gently slide the
covers back for removal (see fig. 2-1).
c. Remove two screws (H26) on the
bezel (AlOMP1).

underneath

of

the

mini

drive

d. Pull the bezel forward from its top. There are two tabs on the
top of the bezel which need to be gently pried away from
the front panel with a flat screwdriver while pulling the bezel
out from the top. Remove bezel.
e. Remove the two screws attaching the right side cover (side with
handle) and the one screw holding the left side cover and
remove.
f. Remove the high voltage cover (MP66) by removing the six
screws (H29) and two flexible disc drive hold down screws (H24).

**************************************************************

*
*
*
*
*
*

WARNING
Exercise EXTREME CAUTION with the high voltage cover off!
Lethal voltages exist in the area under the HV cover.

*

*
*
*
*
*

**************************************************************

2-1 AP

Installation and Removal - Model 64110A
g. Remove four screws (H24) on top and bottom of EM shield (MP2)
which hold both left and right flexible disc drives in place.
h. Unplug the drive keyed-power-cable P2 from J2 and disconnect
ribbon control cable P1 from J1. Exercise caution when removing
and installing cable connectors.
i. Slide flexible disc drive(s) out of mainframe gently.
2-6. Reverse the removal procedure for installation of the flexible
disc drive(s). Make sure cables and connectors are firmly attached.
H29

MOTHERBOARD ASSEMBLY
A2

MP13

MOTHER
BOARD
66501

A10W1

LEFT FLEXIBLE DISC DRIVE ASSEMBL Y
A9

MP1

RIGHT FLEXIBLE DISC DRIVE ASSEMBLY
A10

Figure 2-1.

2-2 AP

Flexible Disc Drive Removal

Installation and Removal - Model 64110A
2-7.

FLEXIBLE DISC DRIVE JUMPER CONFIGURATIONS.

2-8. Each flexible disc drive is shipped with a jumper block installed
on the drive electronics board. The specific configuration of the
jumper block installed depends on the board part number and the
particular installation.
2-9. The jumper configurations described
09130-66501 drive electronics board.

here

are

found

on

the

2-10. The jumpers on the 09130-66501 drive electronics board are
located in a 16 pin DIP socket designated U1E. The jumpers and their
functions are listed in table 2-1.
Table 2-1. Flexible Disc Drive Jumpers and Functions

Jumper Name

OlE Pin Numbers

Function

HS

1 and 16

The head load solenoid is activated
when the drive is selected if this
jumper is left installed.
Since the
flexible disc drive does not have a
head load solenoid, this jumper is a
don't care.

2 DSO

2 and 15

When this jumper is intact, the
responds to drive address O.

drive

3

DS1

3 and 14

When this jumper is intact, the
responds to drive address 1.

drive

4 DS2

4 and 13

When this jumper is intact, the
responds to drive address 2.

drive

5 DS3

5 and 12

When this jumper is intact, the
responds to drive address 3.

drive

6 MUX

6 and 11

When this jumper is intact, the drive
is
always selected.
This jumper
should only be used in installations
having one drive on the mainframe. The
64110A has two drives so this is not
installed.

7 NOT USED

7 and 10

This jumper is not used.

8

8 and 9

If both the HS and HM jumpers are left
intact, the motor will come on when
the drive is selected. The drives are
shipped with 7 jumpers in the jumper
block (the HM jumper is left open).

1

HM

2-3 AP

Installation and Removal - Model 64110A
2-11.

TERMINATION RESISTOR PACKAGES.

2-12. On drive electronics board PiN 09130-66501, the 16 pin DIP
socket U2F is for insertion of the termination resistor package. The
resistor package
must
be
installed.
The
unit
is
shipped
this way.
2-13.

SOLDERED JUMPERS.

2-14. Jumper wires are soldered in R50 and R56. Locations R51 and
are left open. The unit is shipped this way.
2-15.

PACKAGING.

2-16.

ORIGINAL PACKAGING.

2-17. Containers and packing materials identical to those used
factory packaging are available through Hewlett-Packard offices.
2-18.

R57

in

OTHER PACKAGING.

2-19.
The
re-packing
materials:

following . general instructions
the flexible disc drive with

should be
used
for
commercially available

a.

Wrap the flexible disc drive PIN
drive in heavy paper or plastic.

b.

Use a strong shipping container. A double-wall carton made
350-pound test material is adequate.

c.

Use a layer of shock-absorbing material 70 to 100 mm (3 to 4
in) thick around all sides of the flexible disc drive to
provide firm cushioning and prevent movement inside
the
container.

d.

Seal shipping container securely.

e.

Mark shipping container FRAGILE to ensure careful handling.

f.

In any correspondence, refer to instrument by model number
full serial number.

2-20.

09130-69600

flexible

disc
of

and

FLEXIBLE DISC MEDIA.

2-21. The storage medium used in the flexible disc drive, is a
flexible disc. Both sides of the flexible disc are used for data
storage. Each disc must be initialized before it can be used for data
storage.
The initialization procedure marks each disc track, checks
for defective tracks, and establishes file directories. Refer to the
formatting procedure in section III of this manual and the Flexible
Disc Drive Reference Manual for specifi details.

2-4 AP

Installation and Removal - Model 64110A

********************************************************

*
*
*
*
*
*
*

*
*
*
*
*
*
*
*
*
*
*
*
*
*
*

CAUTION
Only HP media is approved for use in the 9130K
flexible disc drive. Use of other media may result
in premature disc failure or damage to the drive.
HP media will always have an HP label on it.
HP rigorously tests each batch of media for error
rate and wear performance in addition to initial
vendor qualification. Only in this way can HP
assure reliable media performance.
The use of non-HP media for single use applications
such as data interchange will probably not damage
the drive or media but, if extended use is
anticipated, the data must be transferred to HP
media.
Extended use of non-HP approved media will void
warranty and service contracts on the instruments.

*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*

********************************************************

2-5/(2-6 blank) AP

Operation - Model 64110A
SECTION III
OPERATION
3-1.

INTRODUCTION.

3-2. Complete operation of the flexible disc drive is beyond the
scope of this manual.
Please refer to the Flexible Disc Drive
Reference Manual for complete operating instructions.
3-3.

OPERATING CLEANLINESS.

3-4. To prevent potential damage or data loss, it is extremely
important to maintain the cleanliness of the disc and air within the
disc drive. The disc drive should not be operated in an environment in
in which dust, smoke, moisture, oil or chemical vapor or other foreign
matter are present. Also, be sure to strictly follow the disc handling
guidelines, found in the Flexible Disc Drive Reference Manual.
3-5.

DISC LOADING.

3-6. Insert the flexible disc into the drive (be sure that the label
faces right and the notch is facing up). Push the disc in until it
hits against the rear of the disc drive, then close the door latch.
Never force the latch, as the media can be latched off center within
the protective jacket.
3-7.

WRITE PROTECTION.

3-8. The disc has the capability of being write protected. This
feature prevents the accidental erasure of data previously recorded on
the disc. The write protect is enabled when the write protect notch on
the jacket of the disc is covered (see fig. 3-1). When the notch is
uncovered, data can be written on the disc.
WRITE
PROTECT NOTCH

FOLD OVER TO
BACK OF DISC

TAB

r------,L--------...
o

o

Figure 3-1.

o

Write Protect Tab Installation

3-1 AP

Operation - Model 64110A

3-9. FORMATTING THE DISC.
3-10.

Use the following procedure to format a disc:

*****************************************
CAUTION
*
*

*
*
*

Formatting a disc causes all data on
that disc to be destroyed.

*
*
*

*****************************************
a.

Turn on mainframe.

b.

Press --Floppy-- soft key.

c.

Press

d.

Press format.

e.

Type in the number of the drive (0 or 1) that the formatting
is to occur on (O=left drive, l=right drive).

f.

Press return.

3-2 AP

disc_utility

soft key.

Performance Test - Model 64110A
SECTION IV
PERFORMANCE TESTS
4-1.

INTRODUCTION.

4-2. This section describes the Performance tests for the flexible
disc drive . There are two modes of testing, performance verification
and operation verification. Refer to the portion of the mainframe
service
manual
for more information on initiating performance
verification.
4-3. The performance verification test will verify to an
confidence level that the mini drives are functioning correctly.

85%

4-4. The operation verification procedures allow the operator to
verify all specifications; and, with the aid of error codes in the
troubleshooting portion of Section VIII (see par. 8-125), troubleshoot
the flexible disc drives from the mainframe keyboard.
4-5.

PERFORMANCE VERIFICATION TEST PROCEDURE.

4-6.
In order to initiate mainframe
the following methods may be used:

performance

verification

(PV)

a. Place the control
source
switches
in
the
performance
verification position shown on the control source label on the
rear panel.
b. Turn power OFF then back ON. The display test pattern (see
4-1) should be on screen.

fig.

c. Press the PVTESTS softkey.
d. Press the NEXT TEST softkey until the FLOPPY
is displayed (see fig. 4-2).
e. Press START to initiate the test. Press
test.

START

DISC

DRIVE

again

to

test
stop

f. If no more tests are required, change control source switches
to the desired boot source and press END TESTS and the system
will re-boot.
OR
g. There is another method that can be initiate~· from the front
panel when a boot is from a hard disc or floppy disc if the
operating software has been loaded. To do this, press CNTL and
RESET together.

4-1 AP

Performance Test - Model 64110A

4-2 AP

Figure 4-1.

Display Test Pattern

Figure 4-2.

PV Test Display

Performance Test - Model 64110A
4-7. During the Floppy test the mainframe software will perform eight
tests on the flexible disc drives. A description of each test is given
in section VIII (see par. 8-105). The following is the sequence of
events that occurs during a test cycle.

***************************************************

*
*
*
*
*
*
*
*
*
*
*
*

NOTE

It is required that a formatted disc be used
when performing the floppy PV. Also, the
WRITE electronics are not tested if a disc
containing data on track 34 is present in the
drive being tested. Furthermore, the floppy
PV will only verify to an 85% confidence
level that the disc drives are operational.
In order to completely test the drives,
the floppy drive diagnostics (operation
verification) must also be performed.

*
*
*
*
*
*
*
*
*
*
*
*

***************************************************
Purpose:
The FLOPPY DISC TEST tests several
flexible disc
drives
and
the
board electronics.

functions of the two
RS-232/mini controller

Area Tested:
CPU and I/O data lines, floppy controller board electronics,
the cable from the RS-232/mini board to the drives, drive
READ/WRITE electronics and mechanics, and the CPU/IO and
floppy I/O data and control line cable.
Operation:
a. Response from floppy controller chip is tested by writing
a pattern to the track register in the mini drive
controller chip (MOC) and reading it back.
b. When initiated, each floppy drive is
following series of tests:

cycled

through

the

1. The drive is selected.
2. The drive is restored (head moved to track 00).
3. Step inward to track 1 (check TRKOO indicator OFF)

4. Step out to track

00, check track 0 indicator ON.

5. Read all sectors on track

0, side 0;

check

for

all

errors.

6. Step to track 34, read all sectors on both sides.

4-3 AP

Performance Test - Model 64110A
c. The PV routines now check to see if there is any data
on track 34. Track 34 will be a spare track on a disc
with no bad tracks. However, if there is a bad track
on a disc, then track 34 is allocated as useable even
though it may contain information.
d. If data exists on track 34, a READ/WRITE test is not
performed and a message indicating this is displayed
on the CRT. If track 34 is available, the following
is performed:
7. Known data on side 0, sector 0 is read.
8.

A random
sector 1.

data

pattern

is

written

9.

The pattern is read from side
compared with what was written.

0

to

side

sector

1

0,

and

10. Steps 7,8 and 9 are repeated on track 34,side 1.
4-8. When a test fails an error message is displayed. Refer to table
8-1 (Mini Floppy PV Error Messages) for a quick reference explanation
of the error messages, and refer to table 8-2 for a detailed
description of each error message and some possible trouble and
corrective measures to service a failure.
4-9. When the test passes, a binary error word is displayed which
indicates the area of previous failures. This word will contain a one
wherever a failure has previously occured and can be decoded to
correspond with the error messages normally displayed. Refer to table
8-1 for an explanation of the error messages.
4-10.

OPERATION VERIFICATION TESTS.

4-11 In order to perform the operation verification tests
following sequence should be used to access the DIAG mode tests:

the

a. Place the control source switches in the performance
verification position shown on the control source label on the
rear panel.
b. Turn power OFF then back ON. The display test pattern (see fig.
4-1) should be on screen.
c. Press the DIAG softkey. The Floppy Disc Diagnostic Display (see
fig. 4-3) should be displayed.
d. Press the DIAG softkey again. The Floppy Test Menu First Level
(see fig. 4-4) should be displayed.

4-4 AP

Performance Test - Model 64110A
e. Set up desired tests and press the TEST softkey to initiate.
The Floppy Test Menu Second Level (see fig. 4-5) should be
displayed.
f. When the desired test is finished press the STOP TEST softkey.
g. Press END DIAG to exit the DIAG mode. The display test pattern
should be on screen.

4-5 AP

Performance Test - Model 64110A

4-6 AP

Figure 4-3.

Floppy Disc Diagnostic Display

Figure 4-4.

Floppy Test Menu First Level

Pertormance Test - Model 64110A

Figure 4-5.

Floppy Test Menu Second Level

4-12. Perform all or part of the following tests to verify that the
flexible disc drives are operating properly:
**************************************************************

*
*

NOTE

*

The Performance Verification should be
*
*
* performed prior to the Operation Verification
* procedures.When the DIAG mode is required use the sequence*
*
* described in section IV (see par. 4-10) to access the
DIAG
tests.
*
*
**************************************************************
4-13.
a.
4-14.

MEDIA CHANGE TEST.
Go to DIAG mode and make sure media change indication occurs
when media is removed and reset when other drive is selected.
MOTOR CONTROL TEST.

a.

Remove both discs from drives and leave doors open.

b.

Go to DIAG mode and observe that drive spindle only turns when
motor indication for that drive is in the TEST mode.

4-7 AP

Performance Test - Model 64110A
4-15.
a.

4-16.
a.
4-17.
a.
4-18.

DRIVE READY TEST.
When running the Operation Verification READ test, open the
door of each drive and observe " •.• Disc Down .•• " failure for
the drive being tested.
DRIVE SELECT TEST.
Go to DIAG mode and observe drive select LEDs to make sure
that the corresponding LED is only on when drive is selected.
FORMAT A DISC.

(check for index pulses at FDCC.)

Refer to disc format procedure given in
manual.

Section

III

of

this

HEAD ALIGNMENT TEST.

**************************************************
*
*
*
*
CAUTION
*
*
* All previous tests should have passed before *
* executing this test to prevent possible
*
* damage to the alignment disc.
*
*
*
**************************************************
4-19. This test requires performing Steps a through i of the
Radial Head Alignment procedure and then the Head Azimuth Alignment
Check. The Radial Head Alignmemt procedure is found in Section V
(see par. 5-19).

***********************************************
*
*
*
*
CAUTION
*
*
* The Radial Head Alignment is a difficult *
* procedure! (Steps a through i of section *
* V (see par. 5-19) are a check only.
*
*
*
***********************************************

4-20.

HEAD AZIMUTH ALIGNMENT CHECK.

4-21. The head azimuth is not field adjustable due to its very
delicate nature. For this reason, the nearest HP Sales/Service office
should be contacted to have this adjustment done. To determine whether
the head azimuth is out of limits, perform the following procedures:

4-8 AP

Performance Test - Model 64110A
a.

Use the procedure in section V (see par. 5-5) to set-up
flexible disc drives as shown in section V (see fig. 5-1).

b.

Call up the DIAG test on the mainframe.

c.

Insert the alignment disc PIN 9164-0151 into
the latch.

d.

Select drive to be adjusted.

e.

Connect and set-up scope as follows:
Trigger on
Display

Sensitivity
TIME/Div
Coupling
Connections
Singals
Gnd
f.

drive

and

close

Channel A (pos)
Channel B

Channel A
Channel B
N/Div
1V/Div
1msec/Div
1msec/Div
DC
AC
(Drive Electronics Board)
TP7(INDEX)
TP4(READ DATA)
TP6(GND)
TP10(GND)

Observe the waveform at TP4 should look similar to that of
Figure 4-6. Examine the waveform for heads 1 and 2. If lobe A
is greater in amplitude than lobe B or if lobe D is greater in
amplitude than lobe C, then the head azimuth is out of
alignment.

4-9 AP

Performance Test - Model 64110A

Figure 4-6.
g.

Head Azimuth Waveform

Check both heads by selecting one side, perform the check then
select the other side. The side selection is made during test
set-up from the mainframe.

4- 22.

SOFT ERROR RATE TEST.

34.

a.

Select drive and seek to track

b.

Go to DIAG and do a RD/WRT/VR test once.

c.

Do READ test 30,518 times (approx. 3 hrs. 25 min.)

*******************************************

*

*

*
*
NOTE
*
*
* After this test is executed the disc *
* used must be reformated before the
*
* performance verification will pass.
*
*
*
*******************************************

d. Verify that there is not more than one error displayed.

4-10 AP

Adjustments - Model 64110A

SECTION V
ADJUSTMENTS
5-1.

INTRODUCTION.

5-2. This section provides the adjustment procedures for the flexible
disc drives. These procedures are recommended to return the drive to
its original optimum performance after maintenance or repair. Included
at the beginning of each procedure is a list of required tools. Table
1-2 in section I is a list of all the required tools.
All these
procedures assume the access to the service equipment listed in table
1-2 of this manual.
5-3. There are two catagories of adjustments given in this section.
the first two are the spindle motor speed and spindle motor drive
adjustments. These may be performed in the field. The second set of
adjustments are; radial head alignment, track 0 switch adjustment,
index emitter/detector adjustment, and the write protect switch
adjustment. These adjustments should not be performed except in
emergency situations due to their delicate nature. These adjustments
are never to be performed at the customers location. If a non-field
adjustment needs to be done, contact the nearest HP sales/service
office. Locations and addresses are given at the back of this manual.
5-4.

TEST AND ADJUSTMENT DRIVE ACCESS PROCEDURE.

5-5. The following procedure is a general set up procedure which
allows access to the flexible disc drive for testing and adjustments:
a.

Remove flexible disc drive from mainframe by following the
procedures in section II (see par. 2-4) and place it along side
the mainframe.

b.

Supply power and control to the flexible disc drive by connecting the power and control extender cables between the
RS-232/mini control board and the drive unit. Make sure that
pin one on the control board is connected to pin one on the
drive under test. The part number for the mini power extender
cable is HP PIN 64110-61620, and the part number for the
RS-232/mini control extender cable is HP PIN 64110-61621.

5-6.

FIELD ADJUSTMENTS.

5-7.

SPINDLE MOTOR SPEED ADJUSTMENT.

5-8.

The spindle motor speed should be re-adjusted whenever a new
spindle motor or servo electronics board is installed. Refer to
section V (see fig. 5-1) while making this adjustment.

5-1 AP

Adjustments - Model 64110A
a.

Required Tools:
1.

Alignment tool or small insulated shank screwdriver.

2.

HP 5314A or equivalent frequency counter (if primary power
frequency is unknown or unstable or when adjusting motor
speed under incandescent lighting).

5-9.

KNOWN PRIMARY POWER AND FLUORESCENT LIGHTING.

5-10. Follow these instructions when primary power is a known
60 Hz and this adjustment is done under fluorescent lighting.
a.

Check the spindle pulley to see that

it

has

a

50

strobe

or

label

PIN 7121-1451.

Enter the DIAG Test on the mainframe.
operation verification tests.

c.

Select the drive to be adjusted.

d.

Press TEST and note the motor status
the drive motor is running.

e.

Observe the strobe pattern on the spindle pulley.
For 50Hz
primary power observe inner pattern. For 60Hz, observe the
outer pattern.

f.

Locate and adjust the potentiometer on the servo board
the proper pattern on the strobe label stabilizes.

5-11.

Refer

light

to

is

section

IV,

b.

ON

indicating

until

PRIMARY POWER FREQUENCY IS UNSTABLE OR UNKNOWN.

5-12. If the primary power frequency is unstable or
these instructions:

unknown,

a.

Connect the frequency counter input to TP7
(ground) on the drive electronics board.

b.

Enter the DIAG Test on the mainframe.
operation verification tests.

c.

Select the drive to be adjusted.

d.

Press TEST and note the motor status
the drive motor is running.

e.

Locate and adjust the potentiometer on the servo board until a
200ms +1-1~ period is observed on the counter display. This
will assure a 300 RPM spindle speed.
(see
fig.
5-1)

5-2 AP

(index)

follow

Refer

light

is

to

ON

and

section

TP6
IV

indicating

Adjustments - Model 64110A

SERVO PC BOARD

SPEED
ADJUST
POTENTIOMETER

Figure 5-1.
5-13.

Spindle Motor Speed Adjustment

SPINDLE DRIVE BELT ADJUSTMENT.

5-14. This adjustment is to ensure proper drive belt tension.
This
adjustment should be made whenever the drive belt or drive spindle
motor is replaced.
a.

Required Tools:
1. #1 posidrive screwdriver
2. Spindle motor adjustment tool PiN 8710-1385

b.

Refer to section V
steps:

(see

fig.

5-1)

while

performing

these

c.

Place the drive assembly on its side so that the bottom of
drive faces you.

d.

Remove the drive belt.

e.

Place the spindle motor adjustment tool on the bottom of the
drive as shown (see fig. 5-2) so that the small end of the
adjustment tool rests against the motor pulley and the large
end rests against the spindle pulley.

f.

Slightly loosen the spindle motor retaining screws and move the
motor until it rests firmly against the adjustment tool.

g.

Re-tighten the spindle motor retaining screws and reinstall the
drive belt.

the

5-3 AP

Adjustments - Model 64110A

***************************************************

*
*
*
*
*
*
*
*
*
*

NOTE

There is a good chance that the drive motor is
not exactly perpendicular to the drive casting
on which it is mounted. This will cause the
drive belt to slip trom the drive pulley when
it is rotated. After a belt is installed,
rotate the drive spindle approximately 10
revolutions to insure the belt will not
slip from the drive pulley.

*

*
*
*
*
*

*
*

*

*

***************************************************

Figure 5-2.

5 -15.

Spindle Drive Belt Adjustment

FACTORY ADJUSTMENTS.

5-16. The following adjustments should not be performed except in
emergency situations due to their delicate nature. These adjustments
are never to be performed at the customers location.
5-17. The adjustments described in this section are:
a.
b.
c.
d.

5-4 AP

Radial Head Alignment
Track 0 Switch Adjustment
Index Emitter/Detector Adjustment
Write Protect Switch Adjustment

Adjustments - Model 64110A
5-18.
a.
b.
c.
d.
e.
f.
5-19.

REQUIRED TOOLS AND TEST EQUIPMENT.
Oscilloscope
Alignment Disc
Torque Driver
#1 Posidriv Screwdriver
#2 Posidriv Screwdriver
3/16 Thin Wall Nutdriver

HP 1740A or equilvalent

PiN
PiN
PiN
PiN
PIN

9164-0151
8710-0670
8710-0899
8710-0900
8720-0001

RADIAL HEAD ALIGNMENT.

********************************************
*
*
*
*
NOTE
*
*
*
*
Steps a through i serve as a
*
*
radial head alignment check.
*
*
********************************************
********************************************
*
*
*
*
NOTE
*
*
* If radial alignment steps j through 1 *
* are performed track 0 adjustment will *
* be required. The track 0 adjustment
*
* should only be done in an extreme
*
*
* emergency due to its delicate nature.
* Never should this procedure be done
*
* at customer location.
*
*
*
********************************************
5-20.
To properly align the read/write heads, perform to the
following steps in the order shown. Refer to table 8-2, section VIII
for head misalignment symptoms.

a.

Set-up flexible disc drive
par. 5-5).

b.

Enter the DIAG test on the mainframe.
operation verification tests.

c.

Insert the alignment disc PiN
close the latch.

d.

Select drive to be tested and press TEST softkey.

e.

Press RESTORE softkey.

f.

Step to track 16

Use procedure in section

9164-0151

V

Refer

to

section

into

the

drive

(see
IV
and

5-5 AP

Adjustments - Model 64110A
g.

Connect and set-up the scope as follows:
TRIGGER
Display

Sensitivity
TIME/Div
Coupling
Connection
Signal
Gnd

Channel A (Pos)
Channel B

Channel A
Channel B
lV/Div
.1V/Div
20msec
20msec
AC
DC
(Drive Electronics Board)
TP7(INDEX)
TP4 (READ DATA)
TP6(GND)
TP10(GND)

h.

With the scope connected, the pattern shown in section V (see
fig. 5-3) should be observed.

i.

Both lobes of the pattern should be within
each other.

Figure 5-3.
j.

5-6 AP

BO%

in amplitude of

Radial Head Alignment Waveform

If the amplitude of one of the lobes of the waveform is less
than Bo% (.B mils) of the other, slightly loosen the three
screws shown in section V (see fig. 5-4) and adjust the radial
head alignment by gently turning the head alignment cam screw.

Adjustments - Model 64110A

Figure 5-4.

Head Assembly Retaining Screws

k.

After the radial alignment has been completed, re-tighten the
three screws loosened in step j while observing the scope
pattern (see fig. 5-3).
Tighten the retaining screws with
the torque-driver set at 8 inch pounds.

1.

Check the other side by selecting the other side
set-up.

5-21.

in

the

test

TRACK 0 SWITCH ADJUSTMENT (extremely difficult adjustment).

5-22. Track O, switch adjustment should be performed only in an extreme
emergency due to its delicate nature. Never should this be performed
at the customer's location. It should be performed whenever the radial
head alignment is changed. To properly adjust the track o switch,
follow these steps in the order shown:
a.

Connect the equipment as in the procedure
par. 5-5).

in

section

b.

Insert a formatted disc into the drive.

c.

Go to DIAG mode (refer to section IV operation
test) and set MIN TRACT to 0 and MAX TRACK to 4.

d.

Press TEST then RESTORE and then ALT SEEK.

V

(see

verification

5-7 AP

Adjustments - Model 64110A
e.

Connect and setup scope as follows:
TRIGGER
DISPLAY
Sensitivity
Time/DIV
Coupling
Connections
Signal
GND

f.

Channel A (pos)
Channel B
Channel A
Channel B
2VjDIV
lV/DIV
5mSjDIV
5mS/DIV
DC
AC
(Drive Electronics Board)
Channel A
Channel B
U4F pin 1
TP12 (STEP)
TP6 (GND)
TP10 (GND)

With the scope connnected and set-up, the waveform should be
similar to that in section V (see fig. 5-5). The duration from
TO to Tl must be less than l8ms and the duration from TO to T2
must be less than 24ms. If these times are within the limits,
no adjustment is neccesary. If either of the time limits is
exceeded, proceed with steps g thru 1.

Figure 5-5.

Track 0 Waveform

g.

Remove connectors P5 and p6 from the front of the drive board.

h.

Rest the drive board on a piece
as cardboard.

5-8 AP

of

insulating

material

such

Adjustments - Model 64110A
i.

Slightly loosen the track 0 switch
section V (see fig. 5-6).

Figure 5-6.

retaining

screw

shown

in

Track 0 Retaining Screw

j.

Adjust the switch position
f are met.

k.

With the torque driver adjusted to 8 inch pounds, re-tighten
the
track 0 switch retaining screw while observing the
oscilloscope pattern (see fig. 5-5).

1.

Reinstall the drive board and connectors P5 and p6 . Tighten
the board retaining screws with the torque driver set to 8
inch pounds.

5-23.

until the time requirements in step

INDEX EMITTER/DETECTOR ADJUSTMENT .

5-24. This adjustment is required when the index emitter/detector
assembly has been replaced . To do this adjustment use the following
steps:
a.

Connect the equipment as in the procedure
par . 5-5).

in

section

b.

Place drive on its side as in section V (see fig . 5-1).

V

(see

5-9 AP

Adjustments - Model 64110A
c.

Go to DIAG mode. See section IV operation verification tests.

Figure 5-7.

Index Detector Retaining Screw

d.

Insert alignment disc into the disc and close the latch .

e.

Select drive to be tested and press TEST soft key.

f.

Press Restore, step to track 16, side 0 soft key.

g.

Connect and setup the

oscil~oscope

as follows:

Connect channel A to TP7/E7 (INDEX) and ground lead to TP6/E11.
Connect channel B to TP1/E1 (READ DATA) and ground TP10/E11.
Trigger:
Display:
Volts/DIV:
Time/DIV:

Internal on channel A (POS)
Channel B
.02V/DIV (using 10:1 probe)
.1ms/DIV

h.

The oscilloscope presentation should look
Burst Waveform (see fig. 5-8).

i.

Loosen the index detector retaining screw (see fig. 5-7) and
move the detector until the INDEX to DATA burst time is
approximately 400 us +/= 300 us for side O.

5-10 AP

like

the

Index

to

Adjustments - Model 64110A
j.

Re-tighten the index detector retaining screw using the torque
driver set to 8 inch pounds while observing the pattern on the
scope (see fig. 5-8).

k.

Check the INDEX and DATA time for head 1 by depressing
releasing the SELECT HEAD 1 push button switch on the DSU.

1.

If the INDEX to DATA time is too far out, adjust the index
emitter located on the top side of the drive assembly and then
re-do steps i through k.

m.

Tighten the index emitter and detector retaining
the torque driver set to 8 inch pounds.

n.

Reassemble the drive assembly.

Figure 5-8.
5-25·

screws

and

using

Index to Burst Waveform

WRITE PROTECT SWITCH ADJUSTMENT.

5-26. The disc drive head assembly may be severely damaged while
performing this adjustment. For this reason, replacement or adjustment
of this switch is not to be done in the field.

5-11/(5-12 blank) AP

Parts - Model 64110A

Replace~ble

SECTION VI
REPLACEABLE PARTS

6-1.

INTRODUCTION.

This section contains information for ordering parts. Table 6-1 lists
abbreviations used in the parts list and throughtout the manual.
Table 6-2 lists all replaceable parts in reference designator order.
Table 6-3 contains the names and addresses that correspond to the
manufacturer's five-digit code numbers.
6-2.

ABBREVIATIONS.

Table 6-1 lists abbreviations used in the parts list, schematics, and
throughout the manual. In some cases, two forms of the abbreviation
are used: one; all in capital letters, and two; partial or no
capitals. This occurs because the abbreviations in the parts list are
always capitals. However, in the schematics and other parts of the
manual, other abbreviation forms are used with both lowercase and
uppercase letters.

6-3.

REPLACEABLE PARTS LIST.

Table 6-2 is the
follows:

list

of

replaceable

a.

Chassis-mounted parts
designator.

b.

Electrical assemblies and their
order by reference designator.

c.

Miscellaneous.

6-4.

in

parts

and

alphanumerical

is

order

components

in

organized
by

as

reference

alphanumerical

ORDERING INFORMATION.

To order a part listed. in the replaceable parts table, quote the
Hewlett-Packard part number and check digit, indicate the quantity
required, and address the order to the nearest Hewlett-Packard
sales/service office.

6-5.

DIRECT MAIL ORDER SYSTEM.

Within the USA, Hewlett-Packard can supply parts through a direct mail
order system. Advantages of using the system are as follows:
a.

Direct ordering and shipment
Mountain View, California.

from

the

HP

Parts

Center

in

b.

No maximum or minimum on any mail order (there is a m1n1mum
order amount form ordered through a local HP sales/service
office when the orders require billing and invoicing).

6-1 AP

Replaceable

Parts - Model 64110A

c.

Prepaid transportation (there is a small
each order).

d.

No invoices - to provide these advantages,
order must accompany each order.

handling
a

check

charge
or

for
money

Mail-order forms and specific ordering information are available
through your local HP sales/service office.
Addresses and phone
numbers are located at the back of this manual.

Replaceable
Table 6-1.

Parts - Model 64110A

Reference Designators and Abbreviations

REFERENCE DESIGNATORS
A

= assembly

F

B

= motor

BT

= battery

FL
IC

C

== capacitor

J

CP
CR
DL
OS

= coupler
= diode

K
L

= delay line

LS

= device signaling Ilamp)

M

E

-:=

mise electronic part

MK

=
=
==
=

fuse
filter

MP

integrated circuit

Q

jack

R

P

= relay
==
=
==
==

RT

inductor

S

loud speaker

T

meter
microphone

TB
TP

= mechanical part
= plug
== transistor
= resistor
= thermistor
= switch
== transformer
= terminal board
= test point

U
V

VR
W
X

Y
Z

== integrated circuit
== vacuum, tube, neon
bulb, photocell, etc
= voltage regulator
= cable
= socket
= crystal

== tu ned cavity network

ABBREVIATIONS
A

AFC

== amperes
== automatic frequency

H

HOW

= henries
== hardware

N/O

= normally open

== nominal

RMO
RMS

= rack mou nt only

NOM

= hexagonal

NPO

== negative positive zero

RWV

== reverse working
voltage

== root-mean square

control

AMPL

= amplifier

BFO
BE CU
BH
BP
BRS
BWO

=
=
=
=
==

CCW
CER
CMO
COEF
COM
COMP
COMPL
CONN
CP
CRT
CW

= counter-clockwise

beat frequency oscillator
beryllium copper
binder head
bandpass
brass

= backward wave oscillator

== ceramic
= cabinet mount only

HEX
HG
HR
HZ

== mercury
= houris)
= hertz

IF
IMPG
INCD
INCL
INS
INT

= intermediate freq
= impregnated

K

= kilo=1000

LH
LIN
LK WASH
LOG
LPF

coefficient)

NPN

= negative-positive-

NRFR

negative
== not recommended for

NSR

field replacement
= not separately

= incandescent
= includels)
= insulationled)

replaceable

OBD
OH
OX

= order by description
= oval head

= left hand

P

= linear taper
= lock washer

PC
PF

= peak
= printed circuit
= picofarads= 10-12

= internal

= coeficient
= common

' () "'-b6~:,:;:) 0

j~)(')(~2

o'p no

A9~1~:~

D913{) . 6'/9;-) ()

4

Mf')T(IR ASSE:MBLY

(t'?A4

O?".1. 30

7

INDFX A:::'n[MnL.Y

f~1 (?A~,:;

!!')lIO· 6'??-l '?

Pl')A6

OJ? 130 ··6 t 604

9

L [,J)

DRIVE ELECTRONICS EllARD

. 66~:)O 1

'6'/?2::~

Mfr
Code

A~:~n[:MBL

4040""1 ':;15

?C4f:lO

()(?~.'.;O-044B

2B400

404()·,,·191::5

2.n4UO
2H400

64J '.! [j .. 6J bO'?
64110·· 6·16".1.;.:.~

2D4CO

SEI~V()

'( ··.. FR UN r

2U4flO

P (.':IN[j

284HO

091,3(;

61,(:>04

*************************************************
*
*
*
*
NOTE
*
*
* Subassemblies A9Al through A9A6 are the same *
* as AlOAl through AlOA6. Refer to the AlO
*
* Listing for these parts and numbers.
*
*
*
*************************************************

*

6-4 AP

The part number given for the mini drive is an exchange
assembly part number. It includes all parts listed for
A9 or AlO except A9/AlOA2, Drive Electronics Board.

See introduction to this section for ordering information
*Indicates factory selected value

Replaceable Parts - Model 64110A

Table 6-2. Replaceable Parts List (Cont'd)
Reference
Designation

HP Part
Number

c Qty
o

Description

Mfr
Code

AlII

Mfr Part Number

09',130""69600

AT liMP 1

4040'""19"1 15

(:):[ ()MP;.:~
AlIIMI':.1

40411···1'i13

ilfl~::jO""044n

DRIUF (FRONT PANFLJ
IILLTDR 1 VE
HI" LATCH CHI! CIIAN J

?84DO

4040·-·191:':'i

;:::U4BO
2B4f,IO

()17'~;O-()44n

2E14:]O
?84Bn

Al III.')

6411()'-61bri6

3

A10W::?

64110··b'161~:.~

1

CAI)!...I> MINI
CAFJU··MINI

5

IJIHVI'- ETECTPONIC:', HOAPD

crUCI·ITJ
(POWLRJ

4041; ···1913
641'.( () ··61606
64"110 ,,6161:?
()9Lllj "6101.',110

09130

A J 11M

(')"J.

OA6

"'66~:jO'J

M01"iJR

A~;SrrMBLY

TNDEX

A~:;HEMf!\.

LED

*

··66~::jOl

2.f:14DO

091?iO

2U4UO

091.

::~

2HAno

(II"!')

.]0·, 674'17

SERViJ

y

ASS~MB1".Y(FRONr

PANFl)

O·"6'79;?3

09130···61604

The part number given for the mini drive is an exchange
assembly part number. It includes all parts listed for
A9 or A10 except A9/AlOA2, Drive Electronics Board.

See introduction to this section for ordering information
*Indicates factory selected value

6-5 AP

Replaceable Parts - Model 64110A

Table 6-2. Replaceable Parts List (Cont'd)
Reference
Designation

HP Part
Number

O?1:·~O·'··66~.:;~)O

Allild

AI0AICI
A'lIlAIC?
Fd OM Cl
(4111AIC4

0"1

BO····()()~.:jU

i) '.(

no···· 0 O:::;B

1',111(\1 C6

{) '1 60····40::0,3

P,lOAIUl

ntil H;.:,~

Qty

;'1 () D~:.:j D(;, C 0 2;:~ c C;.:.J

t 6;;'??

c(.~cn4X'7R"1 04Mn~::i()(.:1

~:';f::.?n9

CAPACITOR-FXD

;?B . . l-HO

'J ~::.;DDI O!:SX(?03~it~?
01(-.1; ··5334

,,'

HeAT SJN!< ~:lCL

ro

Nln····I·IF.X··I~/l...KI.

f:~

"'04~:i4

<\

~:;C!"F\.)

;:.':·.~,60 "O,4~::;4

-4

Gc~:~r:.L.,l·

.Jn

n(..) 1 H~5

;:):";h {) ..-() 1 ;.:.~ '1

nc.:n f

;.:!l9()···0060

WA~:;HF::1~

0,1:10 --ILl411

nPACFR

o.-~n()

hPt-,cr:R Pi'll)

:.~

,OIl'll

1:,'II","1!4]f(
:!4?()-01i1i1

(.~:I

H"1

~"j[)I.lr+7'.'.'i····1

0';(.

;':'~:'iV"()C

11111VDC

~)

,,'

()340

() D ~.:5 () 6 C () ;.:.~ ~."; c: C ;.:.1

!':;/:;?H9

C.f.1P (.-,Cl TIJI:{ FYI)

A10AIH6

i)1~1·J.

:.~

(..'11

CAPACITUR ··FXD ,·J.ur +·····20;" ~~OVDC CCI~
r::APAr::lTnl~ r·:xn ·.lI..lF··l "1n'K, 3~:~vnc 1'A

?::360

t'l"j

Mfr Part Number

f;[.Rva F.l . EC1R()Nlf·:S BIJARD

AIIiAI U,l
,;IIIAI U'\

('~JO(.!t'lH'l;?

Mfr
Code

Description

CAflAr:I'rOR-FXD 50l.jF+75-·10% 25VDC AI

()"100""O??1

o'J. bO-~:j~?i;14

(:,1

4

o16 0--4~:;::=j7

C~::j

At HAl

C

D

···MACH 6····:.3:;1

tI6····C~:;

2~:14n I.)

:~? .... "f \'IX)
,'J n 9
.5····JN·-L . C PAN

j~tlCH

f:l .....:.~?

,~.'.:i····r:N···\.[.";

1,0,1"'1'1(:,(:1-)

(). ,..::)

, ~:j . .

. ?~5
.r:.,.'

11··:j{

l'ID ):'1),:1
r N··· I.. C P FIN HD P f)7 I
PI~N

(J i) ()!)

'043H
BY DU::,I.~H H'T I

Dr:sr~ff)'l'lON

I)!.) 0 J 0

T.lY

DF~::·CI~Ir·Tlnf.J

I:N····\..(".:

.14::5····TN ID

00(;00

(N I..G

,1q ..~

ii :1

OI~I)(R

DES(:,RIP1'Ir1t~

n0 0

AIOAIJl
(110l11l...1

Al OAI IH
A ',\ 0 (.1".(

[,!;:.~

lNDI.!CTI:R
tn~:;4"'064H

4

'1

1

F~ ~:_)

-4 . 0 ;.:.>"1

~::j

AIllAIIll

() 6n:.J·"·;;~.O:.3~::;

AII1Alr<:"
I'd OAt R]

D,?~_::j'7 ··o;:~no

Al1!Al114
AI 01-,1 R";

J)t;B3·· '1

:::100··

()~::'::.';

~'3"l~54

O'/,i7 --0;,'1'10

i:~F"'C:'I'

i"1l.l) ·;:f,,?I.IH .\

j'RANSIS'rOR NPN 2Nf,300 SI

?f'~l.3(j f)

04'l·.i 3

;.:.)tn~)n4

011 ?l

cn?O~'J~:j

01'.1 :'1
4 ~:.:, 4 b

C4"1/D TO '"lOOl ·F

46

<'I- ';~r) "I n;.:~
C4····"!./U···rO··100·! ··r

07~.'j'?·

·0469

RESIS1()R 153K 1% ,125W

06U3

'4'?1~:i

RESISTOR

A10A'llHl

0603···1

AI0A1R'?
(.',"1 D(.~ll~'l 0
MIIA1R11
i41I1A1In:,'
AIilAIR1::l
A"J.('JA1IdA

6-6 AP

9140· 060'/
1.\4':'13

;.:~

(d DA1R6

!4111Al Ul

.?J.)X,A~".:\ .. G

.. r()'-6(,

RESJ'S'rOR 20K 5% ,2~W FC '1'(:=-400/~'800
RES:I:GT,lR 1M ~% .?5W f~(~ T(:= 1300/i·900
RES1:STOR 1K 1% .125W F l'C=O'~--100
RESr!~"'OR-1RMR lK 11)% C Sll)r~ ADJ 17 lRN
REsrSl'OR lK l% ,125W r l'C=O+--lOO

AIIIA1P7

[);.:?~j

(j'y'

DA~I

9

l~f:~:~I::;TnR

06IB--4'71,';
[)6Fq····l ()?~':i

o

\~FSJnTO\~

9

r~F!:;rnTor<

01'111 --'16613

9

REB:u:nnl~

470 5%
.ll< ~::.;%
4'/0 ~:;/"
'II( ~::!/"

l'C:~Oi'-'lO[1

;.:.)A·~::!4b

C.t~··1/B··l() ···"l~:.;OJ 'F~

O"J."J.:.:.)l

CH1'?'1~::j

Fe lC::"'4U()/+6IlD
,;.:!.~.::iW Fe TC:::····40()/+6()O
,?~.:!W Fe "1"[:::; 4~)(J/+6Iln

01",\ :.:.:1

CH10~:j5

o"). "J. ;:.~ 1.

CB4'/1~:;

II :11:"1

CB:l

F(:

,;·.::~.'!W

1 ,~5 ~:jl., ;?W PW ""1"(>0+",-400
11< ~:'.;% ,;:.::::.'.;W Fe fC:::' 4DO/+600

fibUJ···· J O~:.~~:.;
6 B 3 ·"·1 t.'.). ;:.) ~:;

')

r-~E!:)J!:';T01~

I)

1

REBTSTOR

'1. ;.:.~I<

~.';t..:

,;:~.!::iW

Ff.: 1'C"""'400/+'700

() (, B 3 .... ;.:.~ ;.:.~ ;.:.~ ~5

;\

RF!:;I!::;TOR

;.:.~,;?l<

~::!/"

,;:.'~:.:'W

I·:·C

[C CGNU FREQ/V

() ;:.~:l I. "1
;:.;4~::!

C El1 :) ~:.;; ~:i

l'r~-'400/+(I(lO

.25W

14'~IP"P

r·C"····40D/-I·'.lon

PKG

D~~

BY
[lRl)ER BY

'lHO

co

I~

fi ()

;) f) [.1

IN . ?~::;i, IN
I:N

i;.:!e~:.'!·

0

nocno

1/4

... \...!( INT!
PND

rN

'~11)-fl071

lbO····4D33

n4?

~) ;::~.';

;) 1121

HI;..!I:?····1 1~~:1 ... :J
c:n·.1 O~.~~i

II II ;",1

en"J. 2.;:!~:'

'?~:"J

[)i.

1?1

?"70 14

See introduction to this section for ordering information
*Indicates factory selected value

cnc;?;?~':'i

LfYi;:.'(/17N

Replaceable Parts - Model 64110A

Table 6-2. Replaceable Parts List (Cont'd)
HP Part
Number

D

A'jOA;>Cl
AlI1A;,:',C;,

111UO"'OI9'?

8

A '1

0160····:::i;:~06

B

1

A'1l1A;"C4

0"160····4441

[)A~?'C~:j

01611 ..A441

1
1

4

At

Allil,;,!C6
A'10A;"C7
Il'lOA;,!CH

016 () .... ;.:.~ () ~.:!~5

1i'l60"A44'l
11'1611,4441

OA?C(y

016()'-~:,?,1(~

Reference
Designation

C

Mfr
Code

Description

Qty

mlIVE ELECTRONICS BOARD
f)

OA;:.~C3

't6 0 . ~.:;;,? n:'.~

CAPACITClI~-FXD

'7

16

?,

;.:.~UF+"··l

0%

2U400
;;~(I\.'DC

"fA

C;AflA!:·[TI)R·FXU 470pr f""'13% 21l0VDC ~:f:R
CAPACITOR·-FXD bUrF +,-10% ?OOVDC Cr:R
CP\Pr.-1CIT[)I<····FXD

ern

,4''/IJF

t·,,··1 OX

~."'i()V"()C

CAPACITOR-FXD ,47ur

+~10%

5DUDC CU.

'FXI) ,11"1I.1F I·BO-"·?DZ 1 nn'JDC LER
CAPACI'TClR-FXD ,47Uf +""11)% 50VDI: CE:R
CAP(:,CITn\~

cp.-,p(.:lr:lTn~<'''F:X::O

,4,?1,q::

1,·",1 O'y.

~:';DVDC

C[F<

?H-4UO

'1 ;:iOli;.:!25X?O;?,OA?
D"I. 6 D.... ~.'.i ;,:.~ 0 ~)
Olb(1· ..·5,l(l6

?D4BO

:11611-4441

~':'ib;,]H9

;":J4UII
~.l(:l4H()

(11,(" () "-4441

?B400
?U,il·UO

()") f.)

;:~H4nn

I', 111M,' C'l 0

f)

J. 6 [) .... ;.:l (J ~:'.;~:j

'1

CAPACITOR-FXD 4700PF 100UDC
CAf>Af'[TjJR-'FXl) ,:11IJF Ij3U"-2D% lOOV1)C r;rR

?H4B(]
;,:,iU4BO

Il10A;'Cll.

016()-··~::j;:.~OB

II

CAPAC:ITOR-FXD 270PF'

;?H4HO

Al OA;}Cl;.:.~
rY10A?C13

(J160····~.'i;.:.~O~:j

'J

o160'-~'5;:~O!;:;

[t 16 O-.. :'.;j'~ () 'l
o '160'-4IB~;

7
'Y
'7

CER
CAPA[:rl'r:1R . ·FXD 4'lOPF ~'''-10% 20DV1)C efR
CAPACITOR-FXD 470PF i··-l0% 200VDC CEI~
CAPAI~l"OR FXD 1200PF +-10% 111(lVDC ~:rR
CAPACITOR~rXD
,Iur +-10% 50UDC eER

{~"J.

A'lO(.\;?C14
A'l

OA;:.~Cl ~:i

Id OA;'C'l6
A 1 OA;,C 1 '7
IdOI\;"C11'1

D16n .. ··4B:·;1.~.)

'I

CAPf:ICTTI)I~''''Fxn

011'10"1111111

3

CAPACITOI~"-FXl)

0"1 h 0 .... ;.:.~ () :::,i~5

(.~lOA2C19

016 () -;;!. (} ':':;::j

(.ilOA:.:.:C:.:'l,O

f)

Pd OA2C?1
(~'l \) A;?C;~:f..:

016n"-2{\~i~i

CAPACITOR-FXD ,OIUF +80,,20% 100UDC erR
CAP~IClrOR'-"F:x:.:o
,f)lUr +BO ?O/.', '100VDC eLk
CArlACITOR-FXD ,(]lIJr: ~80-2CZ 10(]VDC CER
CAPAC'[TOR ·FXD .O"JI.;F .80 '20X 100VDC (::~R
eAPACII0R~FXD 4,7UF+~III% 35VDC TA

;.:!n4f::O

,311.lF +80 ·?O% lDOVDC CER
CAPACITOR-FXD ,1IIUF +80~2D% 100UDC CFR
CAPACIIDR~FXD ,IIIUF +UlI~2DZ IDOVDC erR
CAPACITOR-FXD 4,7LW+-l0% 35VDC TA
CAPAC·[TOR-·FXD ,OlIJF +8D-20% loovnc erR

;','84130

'I

OWll-1I100

3

At OA;.:.:C:,?7

D16 {) .. -;.:.~ () ~'!~;

A'lOA;'C2fl
(,~·lIlA;.::C;~1)

016Q-20::-;!;:i
O"l b 0 .... ;~l, 0 ~.'!~)

9
9

Al

3

A'IOA2c:l'J
AlOA;!C3B

"'4U3~':;

il 16 o-~? 0 ~.';:':;

A'lOA::?C26

AlI1A;'C:5b

01.6 ()

;,'1341]11

'I
'f

("-}

CAPA~11'OR-'FX1)

"

Ij.l

CAPACITOR~=XD

,0IUF +80-2DZ 100UDC CFA

'f
9

CAP{':,CJTO!~"'FX"()

,Ull,IF +Bn·.. ·;.:.~n% 100VDC C!:::R

0160'-20~j~:j

CAPACIIOR-FXD ,0IUF

1111:111--11100
0'1ll0-1I'100

:3
3

1111:10--11100
0'1ll0-0100

:3
3

[)160 .. ··?O~.)~'i

;:~n4no

;:~n4HO

O·.\60····20~.'j~.:j

o160-"205~i

~)160-~:;;.:.~O'7

CAP~,c'rTr:!R""FX1)

()A;.:.:C;.?~:'.;

A'I,OA,'C33
A'j lIA2C:l4
A'lOA2C3:";

bO .... ~,;:!(I!;:;

(\"1.

:','1:14011

CAPACITOR-FXD ,01ur +80,20% 100Vl)~ CE:,R
CAPAI·::lTC1R,,··FXD ,Oll.)F ~'I~O"20% lOOVDC I:E,R

(.1'1

n'160····;.~O~.';5

01. (:I\l····5i.lon

n '.I. 6 () - ~.:.; ;:.~ 0 ~.:j

;.:~H4UO

'I

{)16()-.. :.:~O~,'!~.'!
() 160 ..·;?'()~j5

OH10-'1I11111

()"J60-?()~.'!~)

'1

OA~~C~?':·5

OA;2C~30

:J'I4011

()"J. b()""5?1. (",

:'1:14011

At

('~1 OA?C~~::.:

200VPC;

o-? ()~5:'5

0'1 (,11",4441
01611-4441

,'il)F + ..··1 0% ~:.:;~ljJDC crr~
4, '?UF+--l n:x, 3~.:.:i'vlnc: T?~
,D1IiF t·DO ;:~O% 1 f)()~'J;C erR

1 6 0 .... ;.:.~ 0 ~.'" ~:;

ol6{)-"~:~O~i~5

+'-10%

Mfr Part Number

+811~20%

CAPf:d::ITDR····Fxn -4, 7IJF+··.. t

n:i.:

101lUDC CFR

;'84F!0

016() .... 20::=j:~i

;>U400

o1 b o-~:.~ () ~.'j ~=:.;

;?H4f:lO
;',"B4BII

n 1.6 o-;.:.~ 0 ~!~~j

()l(:,i1···20~i~:j

1 ~:; () !)475X? 0 J~::in;:,l
[)160

"'::.~O~i~:'i

;.:~n4no

0160····20~:j~:j

;"1341:111

0160-i.~05~)

:::i/:,,?n,?l

1~, 0 D475X?

,,'841'10

:)·.l6 0 ".. ;.:.~ O~.:.i5

?f14f:lO

01.6(}·-20::=;::=i

::':1:1480
;:~~:14n

tl

TA

~','.;62Ei9

CAPACITOR-FXD 4,7UF+-l0Z 35VDC TA

~i6;:~B9

?,~·.','Jl)C

0160·.. ·;.:.~O~i~:i

0 3::=;B?

0160-:':I()~.:j~j

0160'-20~i~:j

t!;:; OD4?~:;X903~Yf.!;.?
1 ~~j () 1)4 'l5X 9 () ~3~ifl?

CAPACITOR"+XJ) 4, 7I.1F+"'1 0% :lc,VDC TA

~.:;6~~B'1

1 ~50D47::';X903~.'"f.i~~

~jf:,~~f:l9

1 ~::jO D47~jX90]~jfl;:?
;)1 bO -"~.';;:.) 0 9
0160····5209
1 ~5 OD 1 ~56X90;.:.~ !lB;=

AlllA;,C40
A'lOA2C4'1

D160"-5:.:09

1

0"160-:j;:'Ol~

1

td

OA;.:~C4~:~

01BO···'1746

CAPACITOR-FXD 4,71.1F+-l0Z 35VDe TA
CAPACITOR~FXD 33DPF +~IOZ ?ODVDC eE11
CAPACITOR-FXD 330PF +-10X 200UDC CER
CAPACITllR-·Fxn 15ur~+-10X 20VDC TA

A'IOA2C43
Al0A<'C44

11180-0100
1111:10-,,11374

CAPACITOR-FXD 4,7UF+-l0Z 35VDC TA
CAPACITOR~FXD 10UF~ lOX 20VDC TA

56;:!B9

1 ~.':'i 0 D4 75X<"1 0 3~J.~;:,~

::'.i62D(},

1 !:'; OD1.

At OA2CRl

1'?01-0050

DIODE-SWITCHING 80U 200MA 2NS
DIODE"'SWITCHING 80V 2DOMA 2NS
DIODE-SWITCHING 80U 200MA 2NB
DIODE~SWITCHING UOV 200MA 2MB
DIODE-SWITCHING 80V 200MA 2NS

DO-35
DO-35
DO-35
DO-35
DO·-35

21'14011

DIODE~SWITCHIMG 80U 20DMA 2NB
DIODE-SWITCHING 80U 200MA 2NS
DIODE-SWITCHING ~~OV 200MA 2NS
DIODE-SWITCHING 811U 2110MA 2NS
DIODE--SWITCHING 80V ?OOMA 2NS

DO-35
DO-35
00-35
DO-33
DO-35

At OA2C;39

AlIlA;.?,Cl~~?

lttnl-·nll~.:iO

A10A2CR3

1'701-1I0~;O

Al
Al

OA~:.~CR4

"1 Ij) 01-' 0 O:':'j n

OA2Cj~~3

1'}0I,.. 0050

At

OA~?CR6

1911I'-00:'d)
1901-0050
19111-1111,';0
1'1111-0050

A'IOA2CR7
AIlIA2CrHl
(.!t'1 OA2CR (j)

3
S
3
:I
3

III

1901-00~;0

At OA~~CR t1
A"1 0 A;.:CI~ '1 ;.~

1(}'01-00~,O
l'j)Ol-00~;O

:5

Al OA2CR '1:1

1'101-0050

Al OA2Cln 7
Al OA2CR 1 tJ

1901-0050

3
3
3

All1A2CR 1 'f

l'11l1'-OO~;0

3

All1A;?,CI~

l'ilOl-0050

3

11101-'OO~)0

OA2CR;:.~~~

1'701-0704

3
4

AIOA2Hl
A10A2H2

031'10-1331
41l40-1854

8
4

Al11A2;r2
AI0A2J3

1~?51-4051

7
3

A10A2J4

1 ~~51-~5m55

7

A'lOA2Ll
A10A;?L.2

9100-2283

8
8
b

AI0A2L3
AIOA2L4

12~'j1-4617

'71110-2283
9100-2281
9140-0118

DIODE-SWITCHING
DIODE-'SWITCtiING
DIODE-SWITCHING
DIODE-SWITCHING
DIODE-SWITCHING

3

OA2Cr~,!1

A·10A2CR;:?O
Al
At

1901-00~.'iO

In

B

80U 200MA
80V

2NB D~-35
?DOMA 2NS DO-35
200MA 2NB DO-35

SOU
80U 20DMA 2NB DO-35
SOU 200MA 2NS DO-35

80U 200MA 2NB
DIODE-SWITCHING 80U 200MA 2NB
DIODE-SWITCHING 80V 200MA 2NS
DIODE-PWR REeT IN4002 100U lA
DIODE~SWITCHING

2
1

DO-35
DO-35

~.'.i62f.l!j'

ObX90?OB~?

;:13480

19111'-000;11
',I '10 1-1I11~;0

2H4HO
21148 11

'1901-11110;0

?B4BO

19(1"l'-OOSO

;"13480

1'101-0050

"l901'-O(J50

;:~.G4BO

l'IOI'-OIl~;11

?IH80
~:.!B4BO

1 '101-01l~;0
19111'-00511

:O::D48 II

1901-00!':;0

20480

1(y(l1-00::iO

;'.134811

'1901-01150

204BO

1901'-00!:,0

,'l>400

1'101-00~;0

2H480

1(J01'-OO~iO

;,1'1480
21l41l0

1901-0050
1901-0050
1901-0050

DO-35

(?'134BO

01;"95

lN4002

00000

ORDER BY DESCR IPT IllN

284ElO

4040 ..··1854

20480

1 ~~51-4617

CONNECTOR 4 .... PIN M UTII..ITY
CONNECTOR 10-PIN M POST TYPE
CONNECTOR lb,-PIN M POST TYPE
390 UH
3'701.)H
2701.lH
500LJH

;>"'4[[11

DO-41

SPACER
SHIEL.D

INDUCTOR RF-CH'-MI.D
INDUCTOR RF- CH-'M1..D
INDUCTor~ Rf'-CH'-MI.D
INDUCTOR 11F--CH'''MLD

:"E141lil

10% ,1 0 ~jDX , 26LG
107. ,1 05DX, 2bL.G
10% ,1 Oo;DX, 26LG
5% ,2DX,45I..G

;:~B480

1~?51-4051

i~B48

0

l251-5B55

20480

9100-2283

28480

';1 0 0-2r~83

20480
28480

9140-0119

See introduction to this section for ordering information
*Indicates factory selected value

9100,-2281

6-7 AP

Replaceable Parts - Model 64110A

Table 6-2. Replaceable Parts List (Cont'd)
Reference
Designation

HP Part
Number

AI fll\?Il'l

'1

{')"1 OA~?Q;.?

1 B;:i4-'

A·IIIi-):'.'I':'

In;;54-·n21~5

AI
A1

B~:i4····O~?l ~.;j
M

Qty
6

O;:~ '1 ~:j

IIA::!Q~';

,[1:I~";3"-1I

n(.);.:?(~6

'[ 1'):·':; .... 1111;36

1\ 1 OAi,rrl
A 1 () A;.:.~\~n
Al0Ai'I 1
0'1 '.10"'1
1111:" 1
011::"1

RESISTOR
RESISTOR
RESISTOR
RESl!;TnR
RESIS'rOR

1K 5% ,251,.,1 Fe TI:=-400/+600
1K 5% ,251,.,1 Fe TC=·-400/+600
tK 5% .25W Fe TC=-400/+600
750 5% ,25W Fe T8=-400/+600
390 5% ,25W FC TC=-400/+600

111 '1 ,'!1
01'1 ::.!'I
1111:''1
O'l'l ::! 'I
nt 1 ;;~ 1

CHl n::~~-:j
GIll ();.:.~:;s
CfllO;.:!5

RESlSTIJR 10K 5% ,25W Fe TC=-'400/+70()
RESISTOR 390 5% ,25W Fe rC=-400/+600
RESISTOR 3,09K 1% ,1251,.,1 f TC=O~'-100

0:1') 21
11'11 ::'1

CEll ~)3:7j
CB39 1. ~:i

~~4546

C4-1/8-10-309,[-F

RESISTOR 768 1%

il1IlA::.'Rl

117;';'7"-11441

Al

A111A<~rnl

06133··-'1

4

,~

'I
"

()i?~.:;

'I

;:.~

068~5'-1 O;:.~~i

iHIIA<'11B

06U;'5-"'lB?::'i

9
'7

Al

068:.3 .... 1 ~.~1~:;
068:3 ..-1 n;:.~~.'j

'r

A 1 OAi,R 1 'I
AlI1A:.'!RHI
A '1 OA;;.~R 19
(.~ '1 n('~;;~l~ ~:~ 0
A'l OA~·~r~;:.~t

06t:n-1

'I

A"1 nA ;:~ R ;.:.~ ;.:~

1161'):; .... 111;,5

A"1

OA~:.~R:.?:·5

o68::'/j·-<591 ~j

tIl

OA21~24

At

A"1

OA~?R

'1

()A~?R14

t~·.1 nA?I~

16

O~?~:i

ii6B~~""1 ()~?::)

'I

06f:r5--t

02.~:;

'I

()6B3-··7~·:jl ~3

4

0(:)83-:39'1 !.:i

OA~?r~;:.:;:i

II 6"I]-·-44:l 8
0698-4462

At OA?R;'?'6

n613:'5-" :5S;;:.~~.:i

Al

OA2R~?.'7

o6B3,·,·1 0 ~?'5

Al

nA~_?R;.?B

06H3·"·473~·.'j

At OA(~R29
1\111A:'.'R30

o 6a:3··"~?;:~;.?::i

A10Ai'!R.il'l

o698'-~549~j

AlI1Ai.'Ri·14

{) 6()B·.. ·442~j

069B- 4462

A1IIAi'RiI6
At OAZ~R3'7
AlI!A:'R31:1

n6B~5-M7::i1 ~j

0683'-3<115

Al0A2R:W

0683,-3915

4

2

M

4

o

0603-·B2i?:':i

AlI1A?R40

06B3 .... 7515

A10A2R4l
Al0A2R4:.1

0683-0;~25

AIOA21143

o

() 6B~5'·· ;'?,2 ;:.~~.'j

A1I1A2R3~';

IIbln-111:',5
0683-1 O;:~~i

1
;1

o
4

5
'I
9

\:l,?::,:d< l'X.
~~6, 1K "II:,
26,11< :Ii::

,'1~::'~.:;W

F rC'~"O+····1()O
,1;:!.;':iW F TC=O+"Mtoo
,1~:.~~.:;W F Tf>::O+····100

CH1

CB?;?;:!.~:i

REGIBT01~

RESISTOR
RESISTOR
RESISTOR
RESISTOR

1,~541< 'IX
,t?~.:!w F 1"C=0+····100
768 1% .12SW F TC=0+-100
750 5% ,251,.,1 Fe 'rC=-400/~'600
390 5% ,251,.,1 FC: TC=-400/+600
8,2K ~% ,251,.,1 Fe 1C=-400/+700

RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR

390 5% ,251,.,1 Fe T(:=-400/+600
750 5% ,25W Fe TC=···400/·t600
8,2K 5% ,25W F'e TC=-400/+700
1K 5% .25W Fe TC=-400/~'600
lK 5% ,25W Fe TC~-400/+600

0603-1515
06B:5-·10?5

A'lOA2R64
A1 OA2R6~)
A10A2R66
Al0A2R6fJ
Al OA~~R6(t
Al0A2R70
A'lOA2R71
Al0A2R72
Al OA;,R7~1
Al0A2R74

6-8 AP

RESISTOR 10K 5%

,25W Fe TC--400/+7011

1:':;0 5% ,2~)W Fe TC~--400/+60(]
11( 5% ,25W FC TC=-400/+600
13.3K 1% .125W F TC=0+-100
28,7K 1% ,125W F TC=0+-100

~:.~4~:';46

C4-"1/8-·TII-·1541· F
-r

~.1.4;:.:i46

C4--1IB'-'TII'-'7101'1!~

01121
011 ?1

C:07:1S1::i
CB3?15

011 ::!1

CB8f.!.;:?5

011 :.?1
111121
1111,'1

CB39t5

011 :':?l

CBl O'."~'

CB7~.'i1 ~'i
CBa;.:!;;~:i

1111:" 1

CH'l

111121

CK5[);:.~:5

O;.?'~j

OU:,,1

CB111:3~,

0'.\1 :.'1
011 :'!.1
011,,,1

CB31115

01121

CBt51~i

CB1D?5
C8l

0~:.~5

9

RESIS1UR 150 5%

9
9

011;:~1

,25W Fe TC--41111/+6110
,2~jW Fe TC:;:"'AOO/+700

CBn'i15
CK1915

2~

HO TC-0+-200

()I:>B3-'11l~:.~t3

'I
2

RESISTOR 1511 5%

0683-1025

CB?;:?'~:5

;?4~:j46

RESISTOR
RESISTOR
RESISTOR
RESISTOR

0683-1515

O::'~5

0;:.~5

CB4~;>3~.~

'I
2
6

RESISTOR lK 5% ,25W Fe TC=-·400/+600
RESISTOR 11( 5% ,25W FC TC=-400/+600
Rr:::SIST()f~ 1 K ~;%
,(~~5W FC TC=~"400/+600

0683-1

CJ:·!;·~("/15

Oll;:~l

OA2R5c.~

Al0A2R59
A10A2R60
Al0Ai,1161
At OA2R6~?'
Al0A2R6;;

CB7~:i".l ~5

0'1 '1 i' 1
() 11 ;.:!l
0'1 '.I :'!1

0613:3'-1025

116'?Il-';l44'7
0698-3624

();.:?~.:;

CB1 B;.:.:~.)
CH'l :':';1~;
CBl 0 ~.:~5

lK 5% ,2SW Fe TC=-400/+600
47K 5% .25W Fe ,·C=····400/+800
2,2K 5% ,25W Fe TC=-400/+700
2,2K 5% ,25W Fe TC=-400/+700
866 1% ,125W F TC=0+-100

At OA2R4',il

0'757-02B9

CEl'!

CDll.1:.:1.5

RESISTOR
RESISTOR
RESISTOR
RESI!;TOR
RESISTOR

RESISTOR tK 5% ,25W FC TC=-400/+600

OA2R5~5

(I ;:.~::'j

[;4···· 'l 18'-T 1.1 'M·'76Hl~ "*F

RESISTOR 3110 5% ,25W Fe TC--400/+600
RESISTOR 1K 5% ,25W FC TC=-400/+600

A10A2R54
At OA2R:':i5
Al OA2R~:;8

CEll

CBtO?5

CB;3'Y2~i

0603-3015

At
At

cnt n;,:~~:;

011 ;,1

RESISTOR 3K 5% ,251,.,1 FC TC='-400/+700

03~;

RESI:3TOR 1 01(

061:1:5-·10:\5

F
··F

;:!.4~S46

,125W F fe-lIf-11111

() 6B~)-'1 0 t.?~;

061:13-1

;:.~

RESISTOR 3,9K 5% ,25W FC 1(:=-'400/+700

A11IAi'R44
A"1 OA~~R 4::.)
A111Ai'1147
A10A2R413

06U~5-·,::'1j0~~5

;:~4~;:;46

~.)%

01 1 ~:.~ 1

CEll

197111

MF4C1/8-TII-133?-F
C4--1 18- TO -·2sn' .... F

24:'.';46

O;:~~j

,,,1:141]0

06S18'-36~~4

o'l1;~ 1
01 '121

CB1 02~5
CBt O;.:~:i
CB10;'>5

011;:~1

CB1515

o117!."1

CB10:35

02~i

9

06f:l3-7ei15
0683-3915

4

o

RESISTOR lK 5% ,25W FC TC--4110/+600
RESISTOR 7:':;0 ::=/~ ,2~:';W Fe TC=···AOO/+600
REBISTOR 390 5% ,25W FC TC--400/+600

!l6133-1025
0683-1025

9

RESISTOR lK 5% ,25W Fe TC=-400/+600

01121
o 11,~ 1
1111 ;,,1
0'1 "1 r.?l

9

RESJ.STCII~

011;.~1

CBt(J~~5

07",7-0416
069[1-3158

7
4
8

REBI~rOR 511 1% ,125W F TC-0+-l00
RESISTOR 23,7K 1% ,125W F TC-0+-l00
RESISTOR 8.2~iK 1% ,125W F 'TC=O+'~'100
RESISTOI~ 10K 5% ,25W Fe TC'=-400/+700
RESISTOR 5.1K -ei% .25W Fe TC=M~400/+70{)

24546

C4-1/8'~0-511R-F

~.~4~:j46

C4-1/8-TO-2372-F

0683-1

07~;7-0441

0683-1 03~;
1l683- 51 ~~5
M

1

B

1I( 5%

,25W FC TC=-400/+600

CBt(l;~5

CBln;~5

24546

C4····1 18-T O·~B25 t ·,·F

Oll~~l

C"l

01121

CB51 ~:.~5

See introduction to this section for ordering information
*Indicates factory selected value

O:~5

Replaceable Parts - Model 64110A

Table 6-2. Replaceable Parts List (Cont'd)
Reference
Designation
(.)1 () (.~;:? I~ 'l:'S
OA;:.~R '? b

A"1

HP Part
Number

C
D

I) 6n:~··· 1 () ;.:.~:·.:i

('lIJM"U1F

'1

1 n;:~o··

AIIJA;:>Ui'U
At OA?l.l;.?C

10;:>0··114'11

~:.:.~:'i

1 H :':'i 0 .. ;.:.i.~:;;:.~ ()
lO:.:?6···0400
"lO:.:!:()·'"1416

AIlJi'?U;:>F

"1 H 1 0 .... [) 3 :,:.::::.:;

AIOM'ILIA
!UIJA?IMB

"1 H:.:!.6-- 0 0 64

'I

In?.O····1~:.~04

I)

'\1IJA~:>IMC:

la;.:!,O·-()6~:~1

A10A?\.J3D
(~t OA;?U:5E"::

1U<'II····0174
1 H;.:.I.O '". 0 660

Ie

'lH?6····(1 1)4

I>

'I

"1

'/.,

Dl~VI',!.

;,:;.'dA F·C

Fe

;:.1 ~::jW

[!

o :l 1 ~~ 1.

CB'l

Olt?t

CB~:it O~i

;·'U41:111
01 ;.:!?;')
Q1. ;.:;:?~'.'j

1 ?~,;i 1-' ,,1- ;.:.::9:;:'
SN'l43BN
\:iN74I1bN

[I> All 11/+611

n

B;:.~ 0 .-~~;:~ 0 B

1 H~:.~O-,;:~?on
In;.:!.O·.. ·06;;.~1

[ll

12~

IC WIDCDAND AMPL V]!) 14····))11"""C PKG
Ie !;A1E lll . l"t; NAND DlJAl" 4··'[NP

1l4'il:5
nt ;:.(t~.:j

In;.:.~6 .. ··()06~j

II

At
Al

OM?'U~:jC

lG;.:~O'"·l

t

l;;~

nA;_?u~.)n

'1

;:.~

(~\.IAl)

IC BFR Tl'L NON'-INV

;,:.1.

·INP

HI~X

l,,·INP

nN74Lb:.:~()N

;:~?~S

~:;N'?43nN

o 1 ;.:!9~:i

~:;N'74n'7N

o1;::~9~.'j

!:~N74()4N

NE ~'i 9 ~:.l (.,

() t ;:~ 9::;

~:;N'741,.S?(JN

[C FF "l'L L. S D,,·,'lYPE
IC DAVR TTL DUAl

(I '\

SN'J41... S'l4(.~N

P[lS-'~DI~E·'lRIG

o1 ;,:~? ~;.'j

QL~AD

2'-INf

l

EI

'1 '1

n

tB;.:!O'-1;.~60

7

IC MV

i,11J1\;cXU1F
A 1 OA~?XU;:!.F

.I?O

1I-·I1I3~.":·l

Il

hOCI' ·411 O/+;:i(j 0

TTL. DUAL

IC fiFR fTL NAND
II
'7

'1 B::?O,"'t :.:!.04
'1 !:l ;.:.~ () .... 11 "1 ;.:.~

,\lIlA?U4D
A11IA;.',U4C
1\ 1 OA?U4F

~:i

Ie O.. "l)[P-·-P P)

A 111MI' 1 (j

1 ;:~~:j 1

"'3("r6~':;

6

A1I1MI,1

19(;0

.. () '7!) ;;.~

'7

MIlA4
tIl

OA4CI~

(.)'J

OA4Hl

1

AI0A4H::'
A10A4H:l

6-11 AP

Description

Mfr
Code

Mfr Part Number

I Nl)I::. X AbHEMBLY

204::)0

~3CRFW'-"M~rCH

:,1')48 II
00(\00

;?:':~6

:,:?Fl4nO

3D~~:;O- [)63~5

6-·3:,:.~

nCRF1,o.,1--··MACH 6"-3;:,>
I,o.IAbH~; 1:.(-' FLA"T

0 -- () 3 '?;"J.

ornE~R

BY

HOLDER ",EM TTTER
HClLDf' P-I)E'1 [CTlm

2H400

4f}4(]""18~':i?

:,'1l4IJ I)

41140-1W:'il

CONNECTOR-4-PTN FFMALE

20400

r J I... 99

See introduction to this section for ordering information
*Indicates factory selected value

D[S~RIP1'ICIN

Replaceable Parts - Model 64110A

Table 6-2. Replaceable Parts List (Cont'd)
Reference
Designation

Al

IIA~;

Al0A5Hl

HP Part
Number

c Qty
o

O'~1;30--('7917

,~

SWITCH

2360-0331

(,

BCREW'-'MACH 6-32 ,25-IN'-LG PAN'-HD'-P()ZI
BCREW-"MI>.CH 4"-411 ,6t!5'-'IN·"·I..I; PAN-HD'-'PlllI
WABHEfl-FL MTl_C NO, 4 ,125"-IN"-ID
SPR ING"'MOJ)UL.E
SCREW"-MACH 6'-3,! ,3ni""IN--LG PAN-Hl)'-PIlZI

AlI1A~5H2

{~(~OO-'O149

(,

At OASH:!
Al II Acifi4
Al OA5H~j

3050-0222

B
6
3

At OA:=-.:iMPl
A'10A5MP2
Al OA~iMP;1

Description

16011-10:'"
2;%0-0;370

LEFT

Mfr Part Number

2B4!)O

091 :111-'67917

~~B4f.iO

2:lf,II--0;l;31

II 00 110

CR.OER BY DHlCRIPTIDN

;~H4f.lO

30r7;O"M02~~~!

,"f;480

1611 0-11159
ormER BY Drf'CiHPTHIN

BRACKET-'SWITCH

213·4£10

'1600-1 02~7i
ORDER BY DFBCRIPTION
4040-,,1847

oeoco

O~590-131;~

6
II

4040'-'1847

5

NUT PLATE. 4'-040
HOL.DE.R""BPR IN!;

,!fH80

Al0A~:;P'l'l

1 ;.~51-3965

6

CONNECTOIl-4'-P IN FEMALE

284f.l1l

AlOA5S2

:1101-i.!4:IB

[,WHUl",HAGK (LU"T DR RIGHT>

'?1l48 II

6-12 AP

1600-'11125

2
2

ABBEMBLY"fRACK

Mfr
Code

00000

See introduction to this section for ordering information
*Indicates factory selected value

Replaceable Parts - Model 64110A

Table 6-2. Replaceable Parts List (Cont'd)
Reference
Designation

(·'110A6

AJ

UA6CI~3

HP Part
Number

BI)130····61i104

C
D

!)

Qty

Description

\.["0

A~;!:;FMBLY···rRuNT

PANEl

'/

Mfr
Code

?1l41lfl

09J:~O""61l:)n4

7'1'744

A1M6H'I4

BI.lGH1NG "'[:OLLI~'\~ l. En

?1I4EiIl

(.~

CONNfCIOR-4 PIN FEMAlE

2D4no

1 OA6P 9

Mfr Part Number

See introduction to this section for ordering information
*Indicates factory selected value

6-13 AP

Replaceable Parts - Model 64110A

Table 6-2. Replaceable Parts List (Cont'd)
Reference
Designation
1><11

HP Part
Number

c

64110" 66;.'i09
64 '11 O"-66~:;n9

;'.:;
5

fi

All

D

Mfr
Code

Description

Qty

MINI CONTROL AND RS232
BOARD ASSEMBLY-MINI/RS232

Al H:l

n160· .. ·;:.~O~5:':;

9

CA~)ACITOR-'FXD

A11C;:?

01(30-0116

I

AUC:3
A'llC4

{)160····2(J~:,~5

o160-;:~O~:i~':i

A"i '1

C~.':';

WI f:1I) .... ;.~ 0 ~)~:)

9
9
9'

CAPAClfOR-FXD
CAPACITOR-EXD
CAPACITOR-FXD
CAPACITOR-FXD

.811JF ~'80""2D% 100VDC
6,8UF+-IIiZ 35VDC fA
.BIUE +80 .. 201 IDOVDC
,01UF +80-201 100VDC
,0'lUF .80-20% 100VDC

AlIC6

111 fJO-O:lO'1
II 1 (,11 .... 112')1'1
0160 .... 0300

4
101
:5

()"l60 ..··2n~.)~.)

9
9

CAPACITOR-FXD
CAPACIT()R-FXD
CAPACITOR-FXD
CAPACITrni-FXD
CAPACITOR-EXV

4,7UF+-211% 10VDC TA
15DOPF +·,,10% ~!ODV])C POLYE
2700PF +-10% 20llVDC PDLYE
,OlUF +80,,20% 10DVDC CER
,0IUF +80-20% 100VDC CER

1\111::'7

A'j'lCB
AIlC9
A'l'lCIO

01bO····~~O~j~5

Allen

IIHIII·-0116

Al'lCL,
1\'11 CD

ot 6 {) ..-;:!. n~:i~.:;

A'lICI4

0160 ·.. ~~O=j~.:j

('~l"l

C"1:;

f)140····0;.:~{.~6

MIC16

OI60 .... 0,,9E1

Al1Cl'l
A'llCl8

0160 .... ;.~O~.'}~5

,~

()160'-20::i~:;

'I

AIlCl')
A11C,'O

I)

1\'11e,"1
1\'11C;~3

O'lBO···1I3'?4
01811···11374
II HIli ..· lI:l74

Al1C"4

{}

A"i '1 C;:~~'.'.i

016()H"2()~.:i~5

A11C~:!t)

0140""02?6

At

lC~~~~

1 hl)'H'2~:~n4

II

0160-·2~:?04

Il

A1H::.''?

I)

16 o-·;.:.~ 0 ~:)5

9

1>,'1 '1C2B
AllC?ly

016()··.. ;.~05~·:i
16 0 ,... ;.~ 0 ~.'!~.:;

'I
'?

A'IIC:IO

0160·H·20~:;~i

9

Alle:ll
A'IIC32

0160-··~:.~()!'.'j5

0160-20~5~:j

'I
9

0160-~~O~55

9

AIlC:14

0160·-20~5~.:j

9

AU C;l~j

0160"";:.!055

9

A'llC:16

0160H"20~j!.:j

,~

AUC:!'?

01 6 () "";.:!. O~:j~:;

A'I1C3B
AI'I C:.l')
A'IIC40

01411 "·0:.'0'7
!J 1 4 II"·O'!II 7
11141l'-0;,~07

'I
7
'7
7

AllC4l

0160""Z:~O~!5

9

AllC42

11160 ···'~;.'04

o

All c:n

CAPACITUR· .. FX()
CAPACITOR-FXD
CAPACITOR-FlD
CAPACITOR-FXD
CAPAcnOR . -FXD

,OWF
,01UE
,01UF
,OlUF
,OHJF

+130-'20%
+80-20%
.80-20%
+80-20%
+BO .. ,>.OI

+1010-20% 10llVDC erR
+-5% 31lllVDC MICA
+80-2D% 100UDC eCR
+-5% 300VDC MICA
+80"';"11% l (lOUDC CCR

DIODE-SWITCHING 30V 50MA 2NS DO-35
DIODE-6WITC~iING 30V SOMA 2NS DO-35

AllCRS

A1'lCR6

'j9111-0040

DIODE-SWITCHING 30V SOMA 2NS DO·"35

A11EI

1;:?5B-Ol~:i1

All Et~

o

A1IE:1

1 ~~~.~i8H" 0 183
1 ;? 5B- (} 1 B/~

PROGRAM HEADER
PRD@AM HEADER

7

C:llNNECTCJr~'-R

A'IIJ1

lc!.~:;1-56·15

7

DIODE-SWITCHING 30V 50MA 2NB DO-35
DIODE-·SWITCHING 30V 50MA 2NS DO-35
DIODE-SWITCHING 30V 50MA 2NB DO-35

~

P 1 MALF

!lCREW-MACH 4··-40

AllJ5

1 ~.~~'51-7335

All MP 1

64110-04701

9

A'IIMP2

64110-0~;1I0'l

4

AllQl

11l54-0215
07~57-0442

9

Al'lR2

07::;7·-0442
0'757-02130
0757-0200
on;7-02flO

9
3

AI1R3
AllR4
Al1R5

6-14 AP

CONNECTOR
CONNECTOR
CONNFCTOR
CDNNECTDR
CONNI':CTOll

,2~;-'IN"

34-PIN
34-PIN
50-PIN
:14 .... P IN

~3

3

M POST
M POST
M POST
M POST

PLUG
U; PAN-·I·ID "PlIn:

7

1 ~.:j ODbB::.'jX903:':_JB;.~

016 () .._;:! 0~;;~.;j

;.:!H4Btl

016n""20!,;i~::i

::':U41l11

D1 b

o·,,;.:.~

{) ~.)~:i

:.:!.04E10

Ott!o,·,,;,:!O~:;~)

'??136

DM13F321F0300WVIC

2U4UII

01.611·· . 0:0'.'/1]
D '16 O-;:.~ 0 ~:'i~~'j

;>U4[111
f.~H4n

()

016()·"'2()~::j~:j

;:?0480

()

;:~n4nn

Ol(:.O··~2?U4

'l60-;.:?;:'~04

:-.'.i6?DI)

:l~·50D·l n6X90;':.~OH;,:~

~':j6;:~B9

"l ~:iO D '1 06X? () ;?nl<.:~
1 ~ODl ()6X9020n;.:.~
016{)·.. ·~~O::j~.~i

~:;6?B'?

?B4nn
?B4ElO

0160-~:~()~~!~';

'7;:!L'56

DMl5F32lF03110WV1C

2U41'!0

016{) .... 20~.'j~:;
()160· .. ·2n~:'i~7i

?i14·IJIl

;'10140 II

n160-;.~O~i~i

;:.~n4~:1

(} 16 0 .... ~? 0 ~;!,::j

n

i.?B4BO

O'l60-~~n~5~:j

;"04011

o160··"2.0:':i!;':j

;,'B41l II

n 16 o-;,:!. ()~:'i5

7~:~13b

7;:! 1 ~~6

DM15r331J0500WV1CR
DMI5F331J05I1DWV'lCR
DM15F331J0500WV1CR

:'84130

016 0 "";:~ O~j~:'j

~!_n4HO

0160··"2?:04

;"[1480
,~D41'11I

0·160-20::';':;'j
01611,·,,2204

;"1034811

O·160-;:~n~.:j~"5

,!IHOO

'1'1111,-00411
190'1-0040
19(11·-00411
')9111-0040
1 '10 1,,-00411

:"0480
;?0400

:'[J4BO
,!D4f10

l '/01-0040

2[14101 0

125n'···Ol~j'l

;->El48 0

'I

;.~B480

1 ~!~::jn··-o 18;.~

00000

ORDER BY DESCRIPTION

;',5U··0 1. B3

TYPE
TYPE
TYPE

'?0480
20480

1 ;'~.~j t·-561 ~j
1;:.:!'.'jl-5b15

,'1,1480

TYPF.

;~IH80

1 ~~~:j 1-56~;3
1 ;':.~51-~jf.) 1 ~3
1 ;.:.~51-7:3~35

28480

SUPPIlRT·-TOP BOM1D
CATCH
TRANSISTDR NPN [>I

Al1Rl

~·.'i62B(t

OlbO·'''~~O~j~:i

A'IlCR 1
AIlCR;2

7
3
'7
2

n16 0 -~;.' D~::}:~i

Ot60-t..~D~.'i5

'1901 .... 00411
19111-110411
'190'1-00411
19111···110411
1911'1,-00411

1?:::jl-~.)615

?U4flO
;>U41,10

;.:'1014811
7?136

,1I1UF
IOOPE
,01UE
1110PF
,O·.I.UF

2101480
Pl)=3~;OMW

FT=300MH'Z

RESISTOR 10K 1% .12SW F TC-O+-IOO
RESISTOR 10K 1X .125W F TC=()+-lOO
RESISTOR 1K II ,125W F TC-0+-l00
RESISTOR lK 1% .125W F TC=O+-100
RESISTOR lK 1% ,125W F TC-O+-IOO

III (1M'

D160 ...' D ~.~rtB

;'!IHBO

o

1 '!.51-·~j6~:j3

(11611· . ·0:100

CAPACITOR-FXD ,01UF +80-20% 100VDC CER
CAPM:HDR·+XO ,IIWE +1010·<'01 lOOVDe CrR
CAPACITClR·-FXD 330l'F + ... ~jx. 51111VDC MICA
CAPACITOR-FXD ~30PF .-5% 50llVDC MICA
CAPACITOR-FXD 330PF +-5% 500VDC MICA

9

All J;"~

1:';1Il\4'7~;XO

~,I~:l4an

(}1f.dl·-·20~j!:j

0160-·;.:~O!'.'j~j

AllJ3
AI1J4

:':ib?D9
;,' 134 I'! II

0160-~:?'O~::;~5

0160··-~?2(}4

3

·l60-~~O~.~~:j

;->D480

CAPACITOR-FXD
CAPACITClR-FXD
CAPACtTOR-FXD
CAPACITOR-FXD
CAPI>,I:ITDR .... FXD

o

n".l6o""~;.~()~:i5

,!U400

C4~:;

It.~~51-5615

CI".R
CER
CER
CER

;'.:841'111

CER

Al"j

AIICIH

O'J.60··"2.(}~;i~:5

()

+-1% 3DOVDC MICA
080-2111 100VDC CFR
+80-20% 100VDC CER
'·BO·""~II% l OOVl)C eER
+80-20% 100Vl)C CER

o16 o--~? () ~'.;~.'j

A'llCR3

0160··";':!O~.:'~S

:':B4HII

320PF
,01UF
,OIUF
,01UF
,0IUF

AllC43
A'IlC44

9

?B4BO

O'~'66::';OI)

?B4BO

CAPACITOR-FXD
CAPACITOR-FXD
CAPACITOR-FXD
CAPACITOIl··FXD
CAPACITOR-FXD

1110VDC
100VDC
1DOVDC
100VDC
lOOVDC

6411(l····66~iO'ji

eER

CAPACITDR .. FXD 10UF~-1111 20VDC fA
CAPACITOR-FXD 10UF+-lO% 2Dvnc TA
CAPACITOR-·FXD 10lJF~'-'10% ?DUnC 'fA
CAPACITOR-FXD ,0IUF +80-20% 100VDC CER
CAPACITOR-FXD ,0IUF >811-20% 1110VDC CER

160HH~~.O~j5

6411

284f:lO

~:;6;~H9

CAPACIT[~-FXD 1500PF +-10% 200VDC PULYE
CAPACI10R-FXD ,OlUF +80-20% lOOVDC CER
CAPACITOR-EXD ,0IUE +80-20% 100VDC CER
CAPACITOR-FXD IDOPF +-51 30llVDC MICA
CAPACITOR-FXD IIIOPF +-5% 300VDC MICA

B

;.,13480

FER
eFA

CAPACl'TI]R-·FXD 6.BIJF+"'·10% 35vnc TA
CAPACIT[~-FXD ,0IUF +80-20% IIIOVDC crR
CAPACITOR-FlO ,IIIUF +80-20% IDOVDC CER
CAPACITOR-LXD ,0IUE +~0-2I1Z 1110VDC CER
CAPACITDR-FXD 3211PF +-11 3DIIUDC MICA

0160··-~~O::j~.:5

I)

C[:,R

Mfr Part Number

284HO

64110-04701
641111,-05001

04713

2N3'~04

24~:j46

C4"1 18-TII-ll1 O,' ..·F
C4-1/8-TO-I002-F
C4-1/8-TO-1.001-F
C4·.. 1I8-TO-IOOI .. ·F
C4 .... 1 18-TO ,-10 II 1'-F

24546
24ei46
24546
~~4~i46

See introduction to this section for ordering information
*Indicates factory selected value

Replaceable Parts - Model 64110A

Table 6-2, Replaceable Parts List (Cont'd)
Mfr
Code

HP Part
Number

c Qty
o

AI1R6
AIIR7
AtlR8
AIIR9
AtlRIO

0757-1094
0757-0438
0757-02T3
on:i7-027:3
0'757-0455

9
:\

AIIRII
AtlRI2
AIIRI3
AIIRI4
AllRl ~s
AtlRI6
AIIRI7
AIIRI8
AllRI9
Al1R20

075'7-044;.'
07:57-0442
0698-·3154
069'8-:3154
0698-3156

9

F Te-O+-IOO

~!.4~:j46

RESIS1·OR 4.22K 1% .125W F '·C=0+-100
RESISTOR 14.7K 1% .12SW F TC=O+-lOO

~~4~)46

2

AIII:!1
AtlR22
AIIR,!;3
A'llR24

06',B-;11 ~i 0

(,

RESISTOR 2.37K IX .125W F TC=O+-100

;'.4546

0'757-~0429

2

RESISTOR 1,82K II ,125W F Te-O+-IOO
RESISTOR lK 1% .125W F TC=0+--100
RESISTOR I.B2K 1% ,125W F TC=O+-IOO

24~j46

RESISTOR lK 1% ,125W F

~~4~.'i46

Reference
Designation

Description

4
4

2

RESHH[lI~ 1,4'7K 1% ,1,!5W F TC=O+'-IIIO
RESli3TDR 5,11K 'IX ,t2~W F TC-Oi-IOO
RESISTOR 3,01K 1% ,125W F TC=O+-IOO

4

2

RESISTOR 3.01K 1% .125W F TC=O+-100
RESISTOR 36.5K 1% .125W F TC=O+-100

tl7!:i7-04fj5

4

075'7-044,~

9

07!'S7-0442
0757·-044INP
NETWORK-RES 10-SIP200,0 OHM X 9
Ie MUXR/l)ATA'''I''EL TTL. 1..8 ,~""Tl1'''I''LINE QUAl)

7

C4"'1/8-TO'-1471'-F
C4-1/8-TO-5111-F
C4 ..· 1/8-TO"'301 1""['
C4-1/8-TO-3011-F
C4 ..·1 18'-T 0 "36~,,"-F

24~:j46

T~·O+-IOO

TC=O~·-100

Mfr Part Number

o129~i

SN'74L.S;3'74N

01;:'!SI~5

SN74;.:.~;.~1N

07263
01295

SN74LS'I :5BN
74LS:I93PC
SN741..S164N

n1 ~~95

01 ;:!'~~5

o1 ~~9:=:;
2H4BO

o1 ~:~95
0"1 r!9ti

01295
01295
{) 1 ~:~95

() 1295
01295

See introduction to this section for ordering information
*Indicates factory selected value

SN74~:~~~lN

SN74LSI23N
64'110-10001
SN74LS240N
SN'74L.SII'!.AN
SN74LSI ~.'7N
£IN'7 4lS 13tlN
SN'74LS240N
BN746S62.0N

SN'74LS:174N

6-15 AP

Replaceable Parts - Model 64110A

Table 6-2. Replaceable Parts List (Cont'd)
Reference
Designation

HP Part
Number

c Oty

Mfr
Code

Description

D

AllU4'.';
AI1U46
A1H14'7
A "I. Hl48
A1HJ4'7

If:I?O''''1997
10;,0···1 "730

'7

[C FF TTL 1. 8 n l'YPE f10S-ECGE-TR'[G PRI . -IN

(:)

B?O·'"~~O?4

:1

'J.a~~()

.. ··t?q'7
641111,·111110;"

'7

Ie FE TTL LS D .. TYPE POS-EDGE-TRIG CUM
[I:: D:,VI1 lTL I S LINE DRVfl OCH,
re FF "'TL 1_8 D··TYPF POS-EDGE-TRIG PRI._-IN
RUM· A!:;M !JUT DC

A"l.W';O
{~"1 '1 U~:i"1

1820".. 1246
'1 n;.:'~()""11 (/7
18;:'()-14'?B

?

At

'lU~.'i2

Al1Uc,;o

AlIU,';4
At '1U~.'i~~i
A"llU~~6
Al1U~.'j7
~I·J. lU~.'i8

At

'lU~.:i9

'1

'1 n;:~()'-'1197
Hll 0 ···o;;?oo
31ill ..·.;>;!71
1810 .... 02.IJO
1 f:l;_:.~ [) ""??I:l 9
1 fll ::5 .... 0131
'\ 0'10--0;:'7:,

6

B

II... GATF lTL LS AND QUAD 2-INP
IC GA'I'E '··l·l .. L.n NAND I~LJAD 2 . INP
IC MlJXR/DATA'-SFL T·Tt.. LS 2·"TCl-l-I.INE QltAD
lC ~Al'E I'TL l.S NAND ~~lJAD 2····[NP
NETW()RK-RES 10··SIF)10,OK OHM X 9

1

SW1T(~H'-SL

B

NETtM]RK·-r~EB

;.:~

Ie Ut-dx T NMDS
IC GFN DUAL

'I

"

'I

8 . 1A D.[P . ··!3l.IOE . ·ASSY ,1A 5DVDC

n1 ;:.19~.)
o129~:i

8N741...S~574N

D".l ;.:.:9~:;
(} '1 ?9~:j
?IHBII

SN'l4LS?44N
BN'l4t..S]74N

() 1 ;?9~';;

HN?4U.:'10CfN

D12SJ~':;

() 1 ;.:.19~:j

n12(1~.:j
1111;' '1

NETWORK-··RES lO"SIPl,OK OHM X 9

;"04811
OU21
:54649
:34:344
IIIU.'!

;:.~

SWITCH-SI_ 5'-lA DIP-SI_II)F-ASSY ,tA 50VDC

;:.~n4ao

10"SIP'lO,Ol( (KIM X 9

A "l.1U60
AIHJ61
AllU6;!.

3l01·.. ·~~~57~:?
1 n;.:.~O·-·19t '7

1
:!

lC DFR Tll

H!2()··-20:?4

!'11U6~l

In;-!.O'''0:';09
18;-.'.0-'0'190

B

IC RCVR DTl

RELAY-·RE:E:D lC 2S0MA 28VDC svnC-CO·[l.
RELAY-REED lC 250MA 28vnc 5VOC"CQII

::~a4Bn

IlFLAY·flf' E.D 1 C ;-"',)!lMA ;:!DUDC fW1)C'

;"1'14011

IC MV TTL MUNOSTBI ... DIJAt._

01??~1

:.:;'n48 0

AllUM
Al'lU6~3

POllU66
AIIUI>'7

AI1U68

H!20--'l260

4
4
·4
7

AI1WIJ
AltWl0

641'IO"'61601'l

,.,

CABl. E -·r< S~.:.~3~~

6411

A'llwn

64110·..·6160(;

;,~

MINI

O··-616l;.~

CAHI..E~··FL()P

AlIXE3

12::i"l'-1~7j~i6

'7

Al 1 XU;,,
A 11XU5
AltXU6
AltXU10
Alt XLII ,,'

'1 :2:0 0·_·06:7;4
'1,'0 () .... 1I63U
'1 :.:.). [) 0 .... 0 6:~.B
·t::'OO ..·II?%

"l
'7
"l

1~:~OO"HOb:59

I-I

A1IXlII~!

1~?OO-O639

8
11
8
1'1
8

Al I XU26
A'll XU;.~7
!111 XU;.~1l
A11XU30

AIIXIJ:l"l

'1;,'00 .... 063'1
1;.;~{]O-O639
1;:~OO--O6311

1::!OO-O639

AlIXU36
Al I XU:17

'l;-!OO·"060?
1;=00-0638
1"011-116117
1;:!01l··O607
1,'011--11607

AlIXIJ38

1::"?OO-063'j)

AI1xu:n
Al1XU;3~:j

°

1;:!01l-'1I6:,',

n

1~:~OO-O639
1;:~OO-O639

8
13
8

AI1XU4B

"1~:.?OO-·063tl

Il

AllXIJ4',
Al1XU57

1 ;'.0 0-0607
'1 ~?o 0-0567

AllXU58

1;;~OO-O:=:i39

Al"lXU61l

1211 0·-0607
04'10-129!3

Al1Z1

1»164-0128

6-16 AP

°

114713

MC1481lL
HN7~':j

:"1:14811

04IJO-()61 '7
114'111,-0617
04'10-061'7
SN'74;:1;:~1 N

con,

POWEt~

21:1400
;,' IH 13 0

., liAR
,0'l8-IN-BSC-Bl

40····r:ON·T Dlf) DIP"'SL])R
SOCKE'T-IC 14-CUN'r DIP DIP-BL.DR
S~)I~K~T-IC

l HCfAJ

64'1 'I lI-b'1601]
64"1. 1 O··.. 616'J.?
64·.t·.IO-·6'l6n:=:i

::~n4H[)

D1P-Bl~R

:.:!.H4f.10
;'.:1:1 4110

SOCKF'T-IC B·-CONT DIP DIP·-S( .. DR
~30CKET-IC 20-·[I)N·r DIF) DIP SLUR

;',:1')4811

;:~D 0-06::'j4
'1:;)0 ()····063H
'1 ;:.~() 0-06:'~n
l;,:!OO"-O'l'y6
'1 ;-!1l0'-lIb39

1 ;:~I.l n""06~5'Y
'1 :.?O O.... 063(Y
'1::!O O'-O(:d'Y
'1 ;:.~n 0-"0639
t :.?n (1"-063'1

;-~n4811

;:~H4DO

SOLtIJCI(ET ..··IC ,'O . ·CONT DIP DIP ··nLDR
SIJCKET·.. IC ~.~ 0 '-CONT DIP DI P '-SLDI~
HOCI

0
II
0

;';1;:1 n1-?3'l1.
;."II1Al O~l

NAND LINE QUAD

,;(]CKET ...·IC :::.O-CON·l

?

ON

nN'/41."Sl~)nN

3'). (\ 1··"2~r7;.?
SN'?4LS24IJN

SOCKET-IC 14"CDNT DIP

8

Al1XU45
AllXIJ46
AllXU47

1;,,011·-116:19

3

nN74U:~O

E;N74LSOilN
2l IIA'l 1);1

SN'? 4LS(!.44N

CONNECTOR-SGL CONT SIT
',1

64 '1'10'''10 [) II;"

o'1 ?9~:1

LINE DIVR CCTl

r.c "Olx'v'f< IHL LINE DRIJR

114'11J'"0617
0490 .... 0617
0·4'10-'06'17

SN'?41...S;:~7:.3"N.

o·t:.:.:95

L~

Ie I)RVR T·fL L. S LINE DRVR ocrL

,.,

Mfr Part Number

FLOPPY DISK

,.'1'14811
r:.~H48

0

'.I

'l~:.~OO-0607

1;?IIII""Ob:lB
'1 ;~o 0-·116117
1?1I 0''',060'7
"l ;.:~O 0-'0607

;-.'1'l4011

t

;:.'134811
~!B4B()

1 ~.:.~o 0-06:39
1 ;:.~(i 0····063(7

;::1')4811
,'U4811

t ;:! (10 '-0 6:59

,!B480

'1 ;20 0-11639

;.~ (l

0·- 0 6:'5'1

1~:~OO-06;'39

1)IP"·!';L.DR
Dlp··-flLDR
DlP-··!:lL.l)H

;.~H4BO

t;:~on·"·060'7

;-<1'1480

'1

DIP"-HL.DR

r.~n4BO

l;:~OO'-0'5~5ty

D [p··nU)ll

;:1:14811

1;,!OO-[)bIl7

HC-18/~-HLDR

;:.~o

0-0:'.')67

'?U-4fJlI

041 [J'-·129H

'.'fl4BII

9164-01?8

See introduction to this section for ordering information
*Indicates factory selected value

Replaceable Parts - Model 64110A
Table 6-3. List of Manufacturers' Code
Mfr
No.
S0545
00000
01121
01295
02111
04713
16299
18324
19701
24546
27014

28480
32293
51506
56289
71744
72136
75042

Manufacture Name
NIPPON ELECTRIC CO
ANY SATISFACTORY SUPPLIER
ALLEN-BRADLEY CO
TEXAS INSTR INC SEMICOND CMPNT DIV
SPECTROL ELECTRONICS CORP
MOTOROLA SEMICONDUCTOR PRODUCTS
CORNING GLASS WKS COMPONENT DIV
SIGNETICS CORP
MEPCO/ELECTRA CORP
CORNING GLASS WORKS (BRADFORD)
NATIONAL SEMICONDUCTOR CORP
HEWLETT-PACKARD CO CORPORATE HO
INTERSIL INC
ACCURATE SCREW MACHINE CO
SPRAGUE ELECTRIC CO
CHICAGO MINIATURE LAMP WORKS
ELECTRO MOTIVE CORP
TRW INC PHILADELPHIA DIV

Address
TOKYO

Zip
Code

JP

MILWAUKEE
WI
DALLAS
TX
CITY OF IND
CA
PHOENIX
AZ
RALEIGH
NC
SUNNYVALE
CA
MINERAL WELLS
TX
PA
BRADFORD
SANTA CLARA
CA
PALO ALTO
CA
CUPERTINO
CA
MONTVALE
NJ
NORTH ADAMS
MA
CHICAGO
IL
FLORENCE
SC
PHILADELPHIA
PA

53204
75222
91745
85008
27604
94086
76067
16701
95051
94304
95014
07645
01247
60640
06226
19108

6-17/(6-18 blank) AP

Manual Changes - Model 64110A
SECTION VII
MANUAL CHANGES

7-1.

GENERAL •

7-2. This section normally contains information for backdating this
manual for models with serial number prefixes prior to the one shown
on the title page. Because this edition includes the information for
the first serial number prefixes, there is no backdating material.

7-1 AP

Manual Changes - Model 64110A

7-2 AP

Service - Model 64110A
SECTION VIII
SERVICE
8-1.

INTRODUCTION.

8-2. The service section provides the user with information necessary
to service the flexible disc control and drives.
8-3. This section is divided into two groups. The first contains
the fundamentals of flexible disc recording, and block and component
level theory of operation. This information will enable the user to
understand the operation of the floppy system in order to more
effectively troubleshoot a problem. The second portion contains
troubleshooting information. This includes descriptions of the error
messages given during PV and DIAG tests, troubleshooting using
signature
analysis, troubleshooting hints, and detailed service
sheets.
8-4.

SAFETY CONSIDERATIONS.

8-5. Read the Safety Summary at the front of this manual before
servlclng this instrument. Review each procedure ( before performing
it) for cautions and warnings. For example, when working around the
power supply and the display circuitry in the mainframe; caution
should be taken to avoid the potentially lethal voltages. In general
however, the flexible disc drives use only +-12 Volts and +5 Volts.
8-6.

FLEXIBLE DISC RECORDING FUNDAMENTALS.

8-7. To better understand the operation of the flexible disc drive,
read this description of disc recording principles. Refer to figures
8-1 through 8-3 while reading this section.
8-8. The flexible magnetic media used with the 64110A disc drive
measures 5.25 inches in diameter. Both surfaces are coated with a
ferromagnetic iron oxide. Both sides are used for data storage.
Each
side contains 35 circular tracks. Each track is divided into 16 pie
slice shaped regions called sectors. A sector can contain up to 256
bytes of data. Surface, track and sector information is used to
reference data location on the disc. Data is encoded on the disc (ones
and zeros) by changing the orientation of small magnetic dipoles in
the magnetic coating on the disc. There is no correlation between
magnetic polarity of the dipoles and the ones and zeros. The ones and
zeros
are
indicated
by the location of the dipole polarity
transitions.
8-9. The disc is soft sectored; that is, there is no physical
features on the disc indicating of where each sector begins. In order
to allow soft sectoring, each sector is divided into two fields.
For
each sector there is an ID field which contains information to
identify the sector. Next there is a data field which contains the
actual data.
Thus, the ID field serves as a fixed marker for the
beginning of each sector.
8-1 AP

Service - Model 64110A
8-10. The makeup ot the ID and DATA tields are similar. Both tields
begin with a series ot synchronization bytes (zeros). These bytes
allow the decoder circuitry ot the controller time to synchronize
itselt with the data on the disc. Following the synchronizing bytes,
is the address mark byte which indicates that the beginning ot an ID
or DATA tield has been located.
The address mark is a specially
recorded data pattern that does not occur in any data stream and is
used to sychronize the data decoding circuits in the RS-232/Mini Disc
Controller (MOe).
8-11. A series ot intormation bytes tollows the address mark. In an
ID tield, these bytes indicate the logical cylinder, head and sector
address. In a DATA tield, these bytes are the data being stored in the
sector.
8-12. At the end ot each tield are two cyclic redundancy check (CRC)
bytes. This check word (16 bits long) allows detection ot most errors
that occur in the data storage and recovery ot intormation trom a
disc.
8-13. There are two gaps tollowing each tield on a track. The gaps
allow
tor variations in disc rotational speed, index detector
alignment variations and time tor the hardware to prepare tor the next
tield.

24 BYTES OF 4E HEX

I
5

2- - - _

BYTES

BYTES

-

" "'"'"

-

"'-.

CRC

12 BYTES OF
00 HEX

3 BYTES OF
A1 HEX
WIMISSING CLOCK

--- ----

GAP

/

21 BYTES OF
4E HEX

Figure 8-1.

8-2 AP

-- -_

ID and Data Field Content

Service - Model 64110A
8-14. The logical sectors are numbered consecutively. However, the
sectors (see figure 8-2) may occur in any physical order around the
track. This allows the sectors to be staggered to optimize system
performance (interleaving).

SECTOR
NUMBERS
(16 TOTAL)

35 CONCENTRIC TRACKS
ON EACH SIDE.
(2 ARE RESERVED)

ADDRESSABLE SECTORS:
16 SECTORS

33 TRACKS

x
TRACK

Figure 8-2.

x 2 SIDES

=

1056 SECTORS

SIDE

Media Sector and Track Structure

8-15. The outermost track on the disc is track 0 and the innermost
track
is 34. Each track has a physical address as described
previously. There is also a logical track address associated with
each good track. The logical track address is written in the ID field
of each sector on the track. If a flexible disc has no bad tracks, the
logical track has the same address as the physical track.

8-16.

The recording head (see Figure 8-3) is moved in and out by a
stepper motor assembly.
Write current passes through the head coil
to selectively magnetize portions of the disc.
To read back data,
the magnetized material is passed under the head, thereby inducing
read-current into the head coil.

8-3

AP

Service - Model 64110A

Figure 8-3. Head Positioning Assembly
8-17.

FLOPPY BLOCK DIAGRAM THEORY.

8-18. The flexible disc drive is divided into two major functions; the
first function is the RS-232/mini controller, and the seco~d is
the
flexible disc drives.
8-19. The block diagram for
the
RS-232/mini
controller
and
flexible disc drive functions are shown on figure 8-4 and 8-5. The
left half of the block diagram is the RS-232/mini control board All
and the right half is showing the flexible disc drives (Drive 0 and 1)
with drive 0 showing the internal functions. Mini Drive Block Diagram
is a more detailed diagram (see fig. 8-5).
8-20.

RS-232/MINI CONTROL BLOCK THEORY.

8-21. The RS-232/mini controller is part of the 64110A mainframe.
It interfaces the flexible disc drives with the mainframe by supplying
the drive with power, data, timing, and control signals.
8-22.

The RS-232/mini controller is divided into eleven subfunctions.

a.

Interface Control Latch

b.

DMA/CPU Address Selector

8-4 AP

Service - Model 64110A
c.

SA Stimulus Latch

d.

CPU Interface/DMA State Machine

e.

Data Latches

f.

4MHz Oscillator

g.

Mini Drive Controller

h.

Drive Control Latches/Buffers

i.

Drive Status Buffers

j.

Data Separator

k.

Disc Drive Multiplexer and Control Buffering

8-23.

INTERFACE CONTROL LATCH.

8-24. Refer to figure 8-5. The control latch is responsible for
capturing the upper byte of I/O data and providing this information to
the DMA/CPU address selector.
8-25.

DMA/CPU ADDRESS SELECTOR.

8-26. Refer to figure 8-5. The address selector, which is gated by
the state machine, generates control signals to the mini drive
control chip (MOC). The state of the control signals is determined
by the output of the interface control latch.
8-27.

SIGNATURE ANALYSIS STIMULUS LATCH.

8-28. Refer to figure 8-5. The output of the SA
connected to either the input of the DMA state
to the inputs of the data separator circuitry,
provided for the user as an effective way
DMA state machine and data separator by forcing
sequences.
8-29.

stimulus latch can be
machine, jumper E2, or
jumper E1. This is
of troubleshooting the
them into known state

CPU INTERFACE/DMA STATE MACHINE.

8-30. Refer to figure 8-5. The CPU Interface/DMA State Machine
performs two functions. First, a major portion of the circuitry does
byte packing and unpacking so that the 16 bit I/O bus can interface to
the 8 bit bus of the MDC in an effective way. Second, the state
machine provides signals for enabling the data latches and providing
next state information for itself.
8-31.

DATA LATCHES.

8-32. Refer to figure 8-5. The
transfering 8 bit read/write,
the drive circuitry from the 16
clocking of the data latches is

data latches are used for loading and
status and control signals to and from
bit 64110A I/O bus. The enabling and
performed by the DMA state machine.
8-5 AP

Service - Model 64110A
8-33.

4MHz OSCILLATOR.

8-34. Refer to figure 8-4. The oscillator block is comprised of a 4MHz
crystal oscillator that is used to clock a 4 bit binary counter.
The
2MHz and 500KHz outputs are used to clock the data separator and the
1MHz output is used to clock the mini drive controller chip.
8-35.

MINI DRIVE CONTROLLER (MOC) CHIP.

8-36. Refer to figure 8-4. The mini drive controller (MOC) chip is
divided into two functions. The first is the microprocessor interface
that uses control signals to determine whether it is in a read or a
write mode. Then, once it has determined its R/W status it will then
read or write data via the data access lines to the data latches. The
second section, the disc interface, implements the commands from the
microprocessor interface section. The disc interface section processes
commands and status signals from the disc drive MUX. Also, the MOC
will provide encoded information to be written onto the disc and a
means of decoding read data to be output to the system.
8-37.

DRIVE CONTROL LATCH/BUFFER.

8-38. Refer to figure 8-4. This block is
control signals to each disc drive.
8 -39.

responsible

for

providing

DRIVE STATUS BUFFERS.

8-40. Refer to figure 8-4. The drive status buffers provide the system
with information necessary to determine the status of the disc drives.
8-41.

DATA SEPARATOR.

8-42. Refer to figure 8-4. This block is responsible for dividing
the l's and O's on the data stream into half bit cells, and phase
locking this data for use by the MOC. The data stream consists
of raw encoded information from the disc. Furthermore, the raw
read-information is delayed and phase locked with a read clock
as soon as seven sync bytes have been read from the disc.
8-43.

DISC DRIVE MULTIPLEXER AND CONTROL BUFFERING.

8-44. Refer to figure 8-4. This block is the final interface to the
disc drives. The multiplexer selects between the two sets of signals
going to/from the two flexible disc drives depending on which drive is
currently active.

8-6 AP

Service - Model 64110A

4 INTERRUPT LINES

•

L3 FLAG LINES

I

4

110 CONTROL BUS

4

I

r01

1

5

I/O ADDRESS BUS

5

I

OSCILLATOR
14MHZ)

6

1

I/O DATA BUS

116
.L.

KHZ
Z MHZ

500

16

MHZ

DISC DRIVE

CLK

I

4

~

/

LIP
.. TRACK 00
: WRT PROTECT

r

LINT

ORO

CPt.:
INTERFACEI
OMA STATE
MACHINE

"-

6

V

---

LIooa 15

~

INTERFACE
CONTROL
LATCH
DMA / CPU
ADDRESS
SELECT

:;±-

3

/

f-----@
TP6

~).

3

L.:-

WRITE GATE
SIDE SELECT

'"UJ--'
'"Zf°

1

UJ

•

a:0

~

"'RITE DATA

()

>

~K

~

"'RITE
CIRCU IT

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

~
~

~

aWe:>
xz

w-

LRST
L ·DDD· S

"
16
v

DATA
LATCHES

~

a

DAL 0-7

'J

~

V

--,'"UJ

~U-

7

>-U-

--,::>
::>CD

---_._--

RG
LWF/LVFOE
LRAWREAD
RCLK

HSAD 0-7

/

:E--,

O

~f-

---

a-

"'0

DATA
SEPARATOR

~z

0'"
z

NRD
DATA

I

I
I
I
I

I

Il.

uP
INTERFACE

0 (0)

""

,

::!E

u

S.A
STIMULAS
LATCH

:~Y~9/

~.~

0

,.. LMR

r-+---·~

DISC
INTERFACE

LlOD 0 7

•

READ
CIRCUIT

--'

V3

v
6

LRE
LWE
LCS
AD
Ai

I

I-~

-~

LIOSB
LDOUT

Il

I

... READ DATA

LDMAR

\ +

0

.~

HEAD
POSN.
MOTOR

~+

I*-

I
I
I
I

I
I

I

I
I
I
I

Y

MOTOR' SPEED
SERVO
MOTOR
CONTROL

"

I
I
I

ACTIVITY

TfPT

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

~

~

W~

WD

SERVO
DRIVE
MOTOR

7

I~

I'{

~

DRIVE
CONTROL
LATCH/
BUFFER

4
/

8
/

DISC DRIVE .. 1 "
SAME AS DISC DRIVE .. 0"

~
~
INTERRUPTING SOURCE

"
-{Y

DRIVE
S TA TUS
BUFFERS

5
/

7

STATUS LINES
/

~
Mini

Control

Figure
8-4.
Block
Diagram

8-7 AP

Service - Model 64110A
8-45.

FLEXIBLE DISC DRIVE BLOCK THEORY.

8-46. This section describes the block digram theory for the disc
drives. Figure 8-5 is a detailed block diagram of the disc drives
and should be used with this section.
8-41.

INDEX PULSE SHAPING NETWORK.

8-48. The index pulse circuitry consists of an index LED, photo
transistor and pulse shaping network. The index hole in the flexible
disc passes between the index LED and photo transistor, causing
the photo transistor to conduct. The detected signal is then shaped
and buffered and output on the Index Pulse interface line (Jl-8).
This signal, although inverted, may be observed at TP7 on the drive
electronics board.
8 - 49.

WRITE PROTECT SENSOR.

8-50. The write protect sensor consists of a switch which is opened
when a write protected disc is inserted into the drive. This signal
is delayed by an RF filter to eliminate transient noise from the
switch.
This will cause the write protect line (Jl-28) to go low and
TP9 to go high.
8-51.

TRACK 0 SWITCH.

8-52. The level on the track 0 interface is a function of the head
assembly position.
When the head assembly is positioned at track 0
and the stepper motor indicates phase 0, J4-19 is pulled low, causing
TP8 and the track 0 interface line to be pulled low.
8 - 53.

SPINDLE MOTOR DRIVE CONTROL.

8-54. The spindle drive system consists of a spindle assembly driven
by a DC motor-tachometer combination and the servo electronics board.
8-55. The servo electronics includes a current limiter and
control line.

interface

8-56. When the Drive Motor Enable line is low, the drive motor
allowed
to
come up to speed.
This speed is adjustable
potentiometer R4 located on the servo electronics board.

is
by

8-51.
A current sensing resistor, also located on the
servo
electronics board limits the motor current to 900mA. If this limit is
exceeded, the motor is disabled.
8-58.

HEAD POSITION CONTROL.

8-59. The head position control conists of a four phase stepper
motor drive which changes one phase for each track advancement of
the head assembly. In addition to the logic for motion control,
a gate is provided to inhibit repositioning during a write operation.

8-8 AP

Service - Model 64110A
8-60.

POWER-ON CIRCUIT.

8-61. This circuit detects when the +5VDC and +12VDC are
prevents writing/reading/erasing/stepping until such time.
8-62.

valid

and

DATA CIRCUITRY.

8-63. All signals required to control the data circuitry are provided
by the host system and are shown in the functional block diagram of
Figure 8-5. These signals are as follows:
a.
b.
c.
d.

Drive Select
Write Enable
Write Data
Side Select

8-64.
There are 4 drive select lines connected to the
data
electronics.
A shunt block determines the drive number. The drive
number is established by clipping three of the jumpers on the shunt
block or adding a shunt to an empty block. When the selected drive
select line is pulled low, the data circuitry is enabled and the drive
is conditioned to respond to step or read/write commands. On the
64110A
all
of
the
jumpers
are
intact
and the drive is
enabled with DSO.

8-9 AP

Service - Model 64110A

INDEX
PULSE

-

WRITE
PROTECT -

TRACK

00

DIRECTION

STEP

WRITE
DATA
DRIVE
SELECT
WRITE
ENABLE
SIDE
SELECT
READ
DATA

DRIVE
MOTOR
ENABLE

-

-

-

-

INDEX
EMITTER
AND
DETECTOR

INDEX
PULSE
SHAPING
NETWORK

WRITE
PROTECT
SWITCH

I- - -

- - .....

FLEXIBLE
DISC

POWER
ON
CIRCUIT

TRACK

00
SWITCH

,
HEAD
POSITION
CONTROL

DC
STEPPER
MOTOR

1

WRITE BUSY

WRITE
CURRENT
SOURCE

Y

f--HEAD
ASSEMBLY

r---

HEAD
BIAS

~~

i-

RED
AMPLIFIER
AND
DIGITIZER

SPINDLE
MOTOR
DRIVE
CONTROL

DC DRIVE
MOTOR

f
SERVO
ELEC.
BOARD

Figure

8-10 AP

8-5.

Mini

Drive

Block

Diagram

Service - Model 64110A
8-65.

WRITING DATA.

8-66.

The write electronics consists of the following circuits:
a.
b.
c.
d.
e.

Write/erase current source
Waveform generator
Trim erase current source
Head select logic
Bias Source

8-67. The read/write winding on the head is center tapped.
During
a write operation, the current from the write-current source flows in
the alternate halves of the winding under the control of the write
waveform generator.
8-68.
Before recording can begin, certain conditions must
be
satisfied. The conditions required before writing (i.e., unit ready)
must be established by the host system as follows:
a.

Drive speed stabilization.
starting the drive motor.

This

will

b.

Subsequent to any step operation, the positioner must be
allowed to settle.
This requires 20ms total after the
last step pulse is initiated, i.e., 5ms for the step motion
and 15ms for settling.

8-69. The following operations are performed
These operations may be overlapped if required.

exist

when

250ms

writing

after

data.

8-70. Figure 8-6 shows the relevent timing diagram for a write
operation.
At T=O when the unit is ready, the write enable line
goes low. This enables the write-current source and bias circuitry.
8-71. Since the trim erase gaps are behind the read/write gap, the
TRIM ERASE control goes true 390us after the WRITE ENABLE interface
line. It should be noted that this value is optimized between the
requirements at track 0 and track 34 so that the effect of the trim
erase gaps on previous information is minimized.
8-72. Figure 8-6 shows the information on the WRITE DATA interface
line, and the output of the write waveform generator which toggles
on the leading edge of every WRITE DATA pulse.
8-73. At the end of recording, at least one additional pulse on the
WRITE DATA line must be inserted after the last significant WRITE DATA
pulse to avoid excessive peak shift effects.
8-74. The TRIM ERASE signal must remain true for 800us after the
termination of WRITE ENABLE to ensure that all recorded data are trim
erased. This value is again optimized between the requirements at
track 0 and 34.

8-11 AP

Service - Model 64110A

8-75. The duration of a write operation is from the true going edge
of WRITE ENABLE to the false going edge of TRIM ERASE. This is
indicated by the internal WRITE BUSY waveform shown.
NOTE1
NOTE2

I

I

I

WRITE ENABLE

I

~
I
I
BOO

r~S~~St-

TRIM ERASE

I

INTERNAL
WRITE BUSY

I

NWRITEDATA

I

i

~

I--t"I
I

NOTE2
WRITE
WAVEFORM
GENERATOR

I
I

I
I
I

WRITE CURRENT

I

NOTE4~

NOTES:

1.

1 ~ a ~ 250 Milliseconds after drive motor
starts or 20 milliseconds after last step
pulse, (whichever is the latest time)

2.

Unsynchronized

3.

B.5 ma peak to peak

4.

4

~

seconds minimun, B ~ seconds maximum

Figure 8-6. Write Timing Diagram
8-76.

READING DATA.

8-77.

The read-electronics consists of the following circuitry:

a.
b.
c.
d.
e.

Read switch/side select
Read amplifier
Filter
Differentiator
0 Crossing detector

8-78. The read-switch is used to isolate the read-amplifier from the
voltage excursion across the magnetic head during a write operation.
The side select is used to enable one of the read/write/erase heads.
8-79. Before reading can begin, the drive must be in a ready
condition. As with the data recording operation, this ready condition
must be established for data recording. A 100us delay must exist from
the trailing edge of the TRIM ERASE signal to allow the read-amplifier
to settle after the transient caused by the read-switch returning to
the read mode.
8-80. Referring to figure 8-7, the output signal from the read/write
head is amplified by a read-amplifier and filtered to remove noise by
a linear phase filter. The linear output from the filter is passed
to the differentia tor which generates a waveform whose zero crossovers
8-12 AP

Service - Model 64110A
correspond to the peaks of the read signal. This signal is then fed to
the comparator and digitizer circuit.
8-81. The comparator and digitizer circuitry generates a lus READ
DATA pulse corresponding to each peak of the read signal. This
composite read-data-signal is then sent to the host system via the
READ DATA interface line.

LINEAR OUTPUT
FROM FILTER

OUTPUT FROM
DIFFERENTIATOR

READ DATA INTERFACE ~----j r---~ ~----I,

+t=0
NOTES:

t = = 250 milliseconds after drive motor siarts,
or 20 milliseconds after step command, or
100 f!. seconds after termination of write
busy, (whichever is the latest time)

Figure 8-1. Read Timing Diagram
8-82.

RS-232/MINI CONTROL THEORY OF OPERATION.

8-83.

MINI CONTROL. (See service sheets llA,B figures 8-10 and 8-13)

8-84. The CPU may execute I/O to any 1 of 16 peripheral addresses
(defined by LPA 0-3) and to anyone of four registers at each address.
The state of the CPU registers are defined by the state of LICl and
LIC2:

8-13 AP

Service - Model 64110A
LIC2

LIC1

Register

Function

H

H

R4

All DMA except last byte

H

L

R5

Command

L

H

R6

Last byte of DMA

L

L

R7

SA test

6-85.
Address and register information is guaranteed valid while
LIOSB is low or, in other ~ords, LIOSB is the I/O bus clock. U41
causes LMYPA to go low whenever peripheral address 4 is addressed.
If the access is a write to R5 (a command) the data is clocked into
u8 and u28 (PCMD) via U52. A write to R7 (used only for SA testing)
enables 011. Through U52, a write to any register other than R7 (DMA
or command) enables U27 and u45. Whereas, a read from R4 or R6 (DMA)
reads data from u26 and u44 (LRD).
8-86. U8B enables DMA upon command through R5 (PCMD). HDMAEN allows
U7B to be set on the rising edge of HDMARQ from the state machine
output u48. This generates a DMA request through U7B and U50C. An
access through R6 (LR6), the last byte of DMA, clears the enable. This
in turn, generates an interrupt (LIR3) through u14c, U29B, U51A,B and
U50A indicating the end of a DMA cycle.
8-87. U30, U37, u49 and u48 comprise the controller state machine.
U30 and u48, used to synchronize the state machine, are clocked by the
normal and inverted outputs of a 2 MHz clock which runs asynchronously
to the CPU clock. U37 and U49 are ROMs. The purpose of the state
machine is to interface between the CPU's 16 bit I/O bus and control
bus, to U2's 8 bit bus. The state machine provides packing and and
unpacking of words into bytes when required (during DMA), and passing
single bytes through without waiting for a second byte during
commands.
8-88. u46 and u47 form a data control register. One example of this
registers operation is as follows: During a read operation the
RS-232/mini disc controller U2 is reading data from disc 0 and needs
to write to disc 1 after its read routine is executed. First, the disc
o drive operating conditions will be captured by the control latch
u46.
Then, the MDC will execute a read on disc o. After the read is
done the control latch is loaded with the operating conditions for
disc 1 via the data latches. Then, the MDC will execute a write on
disc 1. The drive control buffer U47 is used for determining drive
status and to provide a return path for SA stimulus.
8-89. U28, U29 and U8 form a drive status register that informs the
system
if the drives are operating, media has changed, write
protected, requesting DMA, or the MDC U2 has generated an interrupt.
6-90. u40 the DMA/CPU address selector is used to generate control
signals for the internal data register of the mini disc controller
U2.

6-14 AP

Service - Model 64110A
8-91. U36 is used to detect that there is media in the drives and
that the motor is turning. Index pulses will occur every 200 ms, which
will keep the monostables retriggered. U25 detects a media change
by monitoring the write protect switch.
8-92. U19, u24 and
Control and data
control latch, u46.
by u24. The reason
drive controller is

U1 are the final interface to the disc drives.
signals are sent to U19 and U1 from U2 and
Status information from the drives is multiplexed
for mUltiplexing this information is that the mini
designed for single drive operation.

8-93. The control board clock generation is done by the circuitry
surrounding Y1, a 4 MHz crystal oscillator. R22, R23 and R24 bias
U20C,D so the chip will operate in the linear region if the
crystal
is not oscillating. The crystal oscillates in the series-resonant
mode.
8-94. MINI CONTROL DATA SEPARATOR. (See service sheet 11C figure 8-13)
8-95. Due to the encoding scheme used, data from the disc drive
consists of a train of pulses whose pulse-to-pulse spacing may be
4us, 6us or 8us. In practice, up to 200ns of jitter may exist around
these nominal values. The function of the data separation circuitry
is to recover a clock from this data stream. Each block of data to be
recovered is preceded by a sync field consisting of 96 pulses spaced
at 4us (12 bytes of O's).
8-96.
U33 and U50 detect the presence of the sync field in the
following manner: U33B counts a 2 MHz clock so if 5uS or more elapses
between sent pulses on pin 12, U33A will be reset by U50B. Since the
sync field pulses occur at a nominal 4us, U33A will count sync field
pulses and QD will present a positive edge to U34 after 8, 24, 40, 56
pulses. U34 QB and QD will transition from low to high after 24
(3 bytes) and 56 (7 bytes) pulses respectively. After U2 has
recognized four bytes of the sync field, it will set HRG high which
will prevent U34 from being reset by the interpulse spaces of 6us
and 8us which will occur in the data. However, HRG will be reset if an
address mark is not found in 16 bytes or if the head is in the
incorrect position.
8-97. u14, U15, u16, U9 , U10 and U35 comprise a phase locked loop.
U35, the VCO, runs at a nominal 500KHz. When no data is being
inspected off the disc, the PLL is locked to a 500KHz reference in
order to keep the loop in its active region. The DC voltage at TP2
should be within +- 2V of ground under these conditions.
8-98. U15 is responsible for three operations. First, when no data
is being inspected it will lock the VCO, U35, to the 500KHz reference
signal. Second, after U34 QB goes high U15 will lock the VCO to the
250KHz signal while inspection is done of the sync field. Last, when
U34 QD goes high the VCO is locked to the 4us, 6us, or 8uS data
pulses.

8-15 AP

Service - Model 64110A
8-99. Ul1, U18, and u14 cause an in-phase switch between the 500KHz
reference and the sync field (these signals have a random phase
relationship). Assume that U34 QB has just gone high: The next time
u14 pin 9 transitions low, U11A will be clocked true. This will lock
u14 pins 9 and 5 low (the PLL will be locked to the reference) and
stop the VCO, U35. The second sync pulse which occurs after this will
clock U18 true w.hich will switch U15. Then, the sync field is
presented to the PLL and the VCO is restarted in phase. The second
sync pulse is the one necessary to insure that both halves of U35 have
timed out before they are restarted.
8-100. U31A moves the data transition, either 1-0 or 0-1, to the
center of each half bit cell. U31B then sets the data transition pulse
width for U2.
8-101. RS-232/MINI DRIVE THEORY OF OPERATION.
and 2 figures 8-10 and 8-13)

(See service

sheets

1

8-102. The theory of operation for the flexible disc drives will be
provided at a later date. The block diagram theory for the mini drives
should be used at this time for an understanding of the operation of
the flexible disc drives.
8-103. TROUBLESHOOTING.
8-104. This section contains troubleshooting information necessary
to service the Flexible Disc System in conjunction with the host
64110A Logic Developement Station. Contained are descriptions of
each of the eight PV tests, decriptions of the PV error codes, the
use of signature analysis, service sheet layout, the logic convention
used on service sheets, definitions of mnemonics on service sheets,
and some troubleshooting hints.
8-105. PERFORMANCE VERIFICATION (PV) TEST DESCRIPTIONS.
8-106. The following is a description of each of the eight tests
performed during a single performance verification (PV) test cycle.
8-101. FLOPPY CONTROLLER RESPONSE TEST.
8-108. During this test the CPU writes AA hex to the track register in
the mini disc controller chip and then reads it back and compares it.
If this test fails error message 14 (NO RESPONSE FROM DISC CONTROLLER)
is displayed.
8-109. SELECT TEST.
8-110. This test selects the drive to be tested, turns on the motor
and checks for drive ready indication from the drive. If this test
fails error message 1 ( ••• DISC DOWN .•. ) will be displayed.

8-16 AP

Service - Model 64110A
8-111. TRACK 00 TEST.
8-112. This test issues a restore command to the drive and checks for
the TRACK 00 indicator line to be active over track 0 and inactive
over track 1. If this test fails error messages 2, 3, or 4 may be
displayed. These are:
TRACK 00 INDICATOR ON OVER TRACK XX
TRACK 00 INDICATOR NOT ON OVER TRACK 0
TRACK 0 NOT FOUND
8-113. READ TRACK 0 TEST.
8-114. This test reads all 16 sectors of track 0 on both sides of the
disc. The possible error messages generated are message 1, 5, 6, ,7, 8
9.
These
are:
and
· .. DISC
DOWN ...
LOST DATA:
TRK XX SEC XX SIDE X-R/W
DATA CRC ERROR:
TRK XX SEC XX SIDE X-R/W
ID CRC ERROR:
TRK XX SEC XX SIDE X-R/W
RECORD NOT FOUND:
TRK XX SEC XX SIDE X-R/W
SEEK ERROR:
TRK XX NOT VERIFIED
8-115. READ TRACK 34 TEST.
8-116. This test reads all 16 sectors of track 34 on both sides of the
disc. The possible error messages generated are message 1, 5, 6, 7, 8
and 9. These are:
· .. DISC DOWN ...
TRK XX SEC XX SIDE X-R/W
LOST DATA:
DATA CRC ERROR:
TRK XX SEC XX SIDE X-R/W
ID CRC ERROR:
TRK XX SEC XX SIDE X-R/W
RECORD NOT FOUND:
TRK XX SEC XX SIDE X-R/W
SEEK ERROR:
TRK XX NOT VERIFIED
8-117. TRACK 34 CHECK TEST.
8-118. This test checks track 34 to determine if it has been used.
This is done by reading the data on track 34, sector 0 on both sides.
If the track is not used the data read will be all zeros. The possible
error
messages
are
1,
5,
6,
7,
8,
9,
11,
and
12.
These are:
· .. DISC DOWN ...
LOST DATA:
TRK XX SEC XX SIDE X-R/W
DATA CRC ERROR:
TRK XX SEC XX SIDE X-R/W
ID CRC ERROR:
TRK XX SEC XX SIDE X-R/W
RECORD NOT FOUND:
TRK XX SEC XX SIDE X-R/W
SEEK ERROR:
TRK XX NOT VERIFIED
READ KNOWN DATA ERROR:
SIDE X
NO DISC SPACE AVAILABLE FOR WRITE TEST

8-17 AP

Service - Model 64110A
8-119. TRACK 34 WRITE TEST.
8-120. This test writes to track 34 sector 1 on both sides of the
disc.
The error messages that can be generated are 1, 5. 6, 7, 8, 9,
and 10. These are:
... DISC DOWN ...
LOST DATA:
TRK XX SEC XX SIDE X-R/W
DATA CRC ERROR:
TRK XX SEC XX SIDE X-R/W
ID CRC ERROR:
TRK XX SEC XX SIDE X-R/W
RECORD NOT FOUND:
TRK XX SEC XX SIDE X-R/W
SEEK ERROR:
TRK XX NOT VERIFIED
NO WRITE--DISC PROTECTED
8-121. TRACK 34 READ/VERIFY WRITE.
8-122. This test reads the data written in the previous test and
verifies that it is the same as the data written. The error messages
that can be generated are 1,
5, 6, 7, 8, 9, and 13.
These are:
... DISC DOWN ...
LOST DATA:
TRK XX SEC XX SIDE X-R/W
DATA CRC ERROR:
TRK XX SEC XX SIDE X-R/W
ID CRC ERROR:
TRK XX SEC XX SIDE X-R/W
RECORD NOT FOUND:
TRK XX SEC XX SIDE X-R/W
SEEK ERROR:
TRK XX NOT VERIFIED
WRITE ERROR: SIDE X
8-123. PV ERROR MESSAGES.
8-124. While running the floppy PV test an error may be encountered
and an error number given. Table 8-1 gives the error number to
message conversion.
Table 8-1.
ERROR #
1
2

3
4

5

6

7
8
9

10
11

12
13
14

15
8-18 AP

Mini Floppy PV Error Messages
ERROR MESSAGE

... DISC DOWN ...
TRACK 00 INDICATOR ON OVER TRACK XX
TRACK 00 INDICATOR NOT ON OVER TRACK 0
TRACK 0 NOT FOUND
LOST DATA:
TRK XX SEC XX SIDE X-R/W
DATA CRC ERROR:
TRK XX SEC XX SIDE X-R/W
ID CRC ERROR:
TRK XX SEC XX-SIDE X-R/W
RECORD NOT FOUND: TRK XX SEC XX SIDE X-R/W
SEEK ERROR: TRACK XX NOT VERIFIED
NO WRITE--DISC WRITE PROTECTED
READ KNOWN DATA ERROR: SIDE X
NO DISC SPACE AVAILABLE FOR WRITE TEST
WRITE ERROR: SIDE X
NO RESPONSE FROM DISC CONTROLLER
not currently used

Service - Model 64110A

When the current test passes a record of previous errors
is
displayed in the form of an error mask. A "1" is set in each of
the bit positions corresponding to the ERROR I of previous errors.
ERROR # ->
PREVIOUS ERROR MASK:

15 --------------1
XXXXXXXXXXXXXXX

For example, an error message reads:
PASSED

PREV ERRORS: 000000001000001

This indicates that the present test passes but during one or
of the previous tests, errors occurred due to the disc being
(ERROR 11) and ID CRC errors (ERROR 17).

more
down

8-125. DESCRIPTION OF ERROR CODES AND TROUBLESHOOTING.
8-126. Table 8-2. is a description of each error code in table 8-1.
Also,
some possible troubleshooting and corrective measures to
follow if one of these error codes is given during PV.
Table 8-2. Description Of PV Error Codes
CODE #
1

DESCRIPTION
" ... DISC DOWN .•. " This message indicates that the drive
ready line of the disc being tested was not read in the
true state.
Possible trouble/corrective measure:
a. No media in drive/Insert media and close door.
b. No index pulses from drive or motor not running/Check
index pulse circuitry and servo motor.
c. Index pulses but no drive ready indication/Check drive
ready circuitry.
d. Drive ready signal true on floppy control board/Check
CPU interface with interface DSA loops.

2

"TRACK 00 INDICATOR ON OVER TRACK XX" This message indicates
that the MOC was able to verify, by reading the ID portion
of the track data, that the head was positioned over track
XX. However, the CPU read the TRACK 00 status bit from the
Mini Drive Controller (MOC) and it was in the true state.

8-19 AP

Service - Model 64110A
Possible trouble/corrective measures:
a. Go to DIAG mode (see section IV operation verification
tests) and select correct drive and step to TRACK xx.
b. TRACK 00 signal is true at input to Mini Controller
Chip (MOC)/Troubleshoot TRACK 00 detector circuitry,
may have to do TRACK 00 switch adjustment.
c. TRACK 00 signal is false at input to MOC/Troubleshoot
CPU interface circuitry with DSA interface loops.

3

"TRACK 00 INDICATOR NOT ON OVER TRACK 0" This message
indicates that it was verified by reading the ID portion
of the track data, that the head was positioned over track
o but the CPU read the TRACKOO status bit from the MOC and it
was in the false state.
Possible trouble/corrective measures:
a. Go to DIAG mode (see section IV operation verification
tests) and select correct drive and restore it.
b. TRACKOO signal is false at input to MOC/Troubleshoot
track 00 detector circuitry; may have to do a Track 00
switch adjustment.
c. TRACKOO is true at input to MOC/Troubleshoot
interface circuitry with DSA interface loops.

4

CPU

"TRACK 0 NOT FOUND" This message indicates that after the
restore command the CPU read the TRACKOO indicator to be
false and that the head was not positioned over track o.
Possible trouble/corrective measures:
a. Go to DIAG mode (see section IV operation verification
tests) and try the RESTORE command for the drive that
failed.
b. Bad head positioning circuit/Check step and direction
lines
from the mini drive controller and stepper
motor circuitry.
c. CPU interface to MOC bad/Check
using DSA interface loops.

5

8-20 AP

interface

circuitry

"LOST DATA TRK XX SEC XX SIDE X R/W" This message indicates
that the CPU did not respond to either an interrupt or a DMA
request from the m1n1 drive controller. Also, the data
in the MDC was lost.

Service - Model 64110A
Possible trouble/corrective measures:
a. CPU interface to MOC is bad/Check
using DSA interface loops.

interface

circuitry

b. DMA path to CPU bad/Check using logic probe or ohmmeter.
c. Mainframe interrupt circuitry bad/Troubleshoot
DSA in mainframe I/O write test.
6

with

"DATA CRC
TRK XX SEC XX SIDE X R" This message is generated
when the mini drive controller chip detects a CRC error
in the data portion of a sector read operation.
Possible trouble/corrective measures:
a. Bad media/Reformat a new disc and repeat test.
b. Data separator circuit
separator loops.

bad/Check

using

DSA

data

c. Bad drive read electronics/Check read data waveforms
with the ones shown in the drive and drive head
alignment procedures.
See
radial
head
alignment
procedure in Section V (see par. 5-19).

7

"ID CRC TRK XX SEC XX SIDE X R/W" When this message is
generated the MOC chip has detected a CRC error in the ID
portion of a sector read operation.
Possible trouble/corrective measure:
a. Same as
above.

8

trouble/corrective

measures

used

in

code

6

"RECORD NOT FOUND TRK XX SEC XX SIDE X R/W" This message
is generated when the code for the desired track, sector,
and side were not found on the current track in any of the
ID fields.
Possible trouble/corrective measure:
a. Bad media/Reformat a new disc and repeat test.
b. Data separator circuit
separator loops.

bad/Check

using

DSA

data

c. Bad drive elect~onics/Check the read data waveforms
with the waveforms given in the drive and drive head
alignment procedures given in Section V.
d. Bad head positioning circuit/Check
the
step
and
direction lines from the mini drive controller and
stepper motor circuitry.

8-21 AP

Service - Model 64110A

9

"SEEK ERROR: TRK XX
generated the code
in the ID field.

NOT
for

VERIFIED" When this message is
the desired track is not found

Possible trouble/corrective measure:
a. The trouble and corrective
code 8 above.
10

measures

are

the

same

as

"NO WRITE DISC WRITE PROTECTED" This message is generated
when the CPU reads the write protect line (through the
activity register) for the selected drive in the true state
during a write operation.
Possible trouble/corrective measure:
a. Disc write
protected.

protected/Use

disc

that

is

not

b. The write protect signal is true when the disc
write
protected/Troubleshoot
the
write
circuitry.

write
is not
protect

c. Write protect line operates correctly, but, the CPU
interface is bad/Check CPU interface using DSA with
activity buffer moved to mode buffer location.
11

"READ KNOWN DATA ERROR: SIDE X"
track 34, during the track 34
then an error is displayed.

When the data read on
check, is not all zeros

Possible trouble/corrective measure:
a. Bad media/Reformat a new disc and perform test again.
b. Data separator circuit bad/Check using DSA data
separator loops.
c. Bad drive read electronics/Check the read data waveforms
with the waveforms given in the drive and head alignment
procedures given in Section V.
d. Bad head positioning circuit/Check step and direction
lines from the mini drive controller and stepper motor
circuitry.
12

"NO DISC SPACE AVAILABLE FOR WRITE TEST" This message is
generated when the first byte of data read on track 34,
during the track 34 check, is not all zeros.
Possible trouble/corrective measure:

8-22 AP

Service - Model 64110A
a. The trouble and corrective measures are the same as
code 11 above.
13

"WRITE ERROR: SIDE X" When the data written to track 34
during the track 34 write test does not match the data
read back during the track 34 read/verify test this message
will be generated.
Possible trouble/corrective measure:
a. Bad media/reformat a new disc and perform the test
again.
b. Bad write circuitry/check write gate, write data, and
write protect signals to the MDC and the write waveforms
to the drive units.

14

"NO RESPONSE FROM DISC CONTROLLER" This message is generated
when the CPU cannot write 55 Hex to the track register in the
Mini Drive Controller and read it back correctly.
Possible trouble/corrective measure:
a. CPU interface to MDC bad/check interface circuitry
using DSA interface loops.

8-127. TROUBLESHOOTING HINTS.
8-128. The following are some things to check before troubleshooting
the RS-232/mini control board.
a.

Make sure the clocks on U30 pin 11 and u48 pin 11 are clocking
at 2MHz.

b.

Check that U41 pin 12 (LMYPA) is toggling. This indicates that
the CPU is working and communicating with the mini disc
controller.

c.

The CPU will not work at all if LIR3 or LDMAR are pulled low
at the wrong time. U50 may be removed to disable these signals.

d.

Test STEP and RESTORE commands before a READ or WRITE to disc.
These require that a lot less circuitry be functional.

e.

The phase detector u16 locks the NEGATIVE transitions of
"vco Data" and "vco OSC" together.

f.

For a simple analysis, consider 010 to be an integrator.

g.

Check that the VCO will lock to the 500KHz reference record.

h.

If in real trouble, wire a header which will hold HVFOE high
and HRG low. This breaks the loop between the sync detector,
PLL, and U2 (MDC).
8-23 AP

Service - Model 64110A
8-129. The following is some specification that should be tested
before troubleshooting.
a.

U2 pin 24

1MHz +-1% square wave

b.

U36 pins 5 and 13

225mS

PW

<=

300mS

c.

U31 pin 13
U31 pin 12

1uS +- 50nS
150nS <= PW

<=

190nS

U35 pin 4
U35 pin 13 with TP1
grounded

period = 2uS +- lOOnS
asymmetry of square wave

TP2 PLL locked to 500KHz
reference

+-2V of ground

d.

e.

<=

<=

5%

8-130. TROUBLESHOOTING USING SIGNATURE ANALYSIS (SA).
8-131. The RS-232/mini control board has been designed to use
signature analysis for troubleshooting to component level. Signature
analysis is a technique that enables the signature analyzer to display
a compressed four digit "fingerprint" or signature of the data stream
at a given node. Any fault associated with a device on that node will
force a change in the data stream and, therefore, result in an
erroneous signature.
8-132. The troubleshooting consists of connecting the signature
analyzer and tracing good and bad signatures back through gates and
memory elements until a part with correct inputs and faulty outputs is
isolated. Signatures are determined to be good or bad by comparison to
the good signatures given in this section. SA tables 8-6 thru 8-18 are
represented by a red shaded letter at a given node that correlates to
the letter given with the SA table. For example, Table 8-6. Loop A,
the red shaded letter "A" is given on the schematic where loop A
signatures can be taken.
8-133.

KEY SIGNATURES.

8-134. While using SA on the RS-232/mini Control Board some of the
loops may contain key signatures. The use of the key signatures will
reduce troubleshooting time considerably. A key signature is indicated
with a "+" next to the node on the SA table and is a red unshaded
letter on the service sheet. The key signatures should be checked
before doing all of that loop. If the key signatures are good then the
rest of the signatures in that loop are good.
8-135.

INTERFACE LOOP.

8-136. The SA tables for the interface loop contain key signatures
However, it is recommended that the key signatures in loops A, B and M
be taken first. If all of the key signatures are good then no more
signatures need to be taken in the interface loop. Although, if some
of the key signatures in loops A, Band M are wrong other SA loops may
8-24 AP

Service - Model 64110A
be necessary to find a problem.
8-137. In the interface loop, SA tables A-J are used to exercise all
of the CPU/MOC interface circuitry. In this loop it the test jumper E2
is in the interface TEST position, XU12. This connects the output of
the SA stimulus latch to the inputs of DMA state machine. This allows
the CPU to directly control the state machine. Also, the clock for the
state machine is connected to LMYPA so that the state machine is
clocked only when the CPU communicates with register 4. This makes all
interface circuitry synchronous with the CPU and thus allows SA.
SA
tables A-J are outlined below:
Table A

Check overall interface

Table B

Check Floppy ASM

Table M
Check all Data (I/O Bus) to/from RS-232/mini
controller

8-138.

Table C

To check I/O bus decoding

Table D

Check Data written to Floppy drives

Table E

Checks Floppy Read Latches

Table F

Check Data out of U27

Table G

Check Data from U45

Table H

Check Data from mode buffer u47

Table I

Check Data from the MOC (MSB)

Table J

Check Data from the MOC (LSB) and from u47

DATA SEPARATOR LOOP.

8-139. In this loop the test jumper E1 is in the Data Separator TEST
position, XU5. This connects the output of the SA latch to the data
separator inputs. Also, LMYPA is connected to the L2MHZ input to the
data separator. This makes all of the data separator circuitry
synchronous to the CPU and thus allows for SA. SA tables K and L are
outlined below:
Table K

Check Data Separator circuitry

Table L

To check U15 multiplexer to make sure it is
mUltiplexing the HDATAlUS signal properly. There
are no signature nodes for this loop. just check
for correct VH.

8-25 AP

Service - Model 64110A
Table 8-3.

SA Loop A

INTERFACE LOOP A
PC BOARD: 64110-66509

Floppy control

CIRCUITRY TESTED: Overall interface
PROCEDURE: Remove U29 mode buffer (U29 can be tested by exchanging
with u47). Remove all option boards. Move E2 TEST jumper
to interface TEST position in XUl2. Press DSA 1 soft key
to initiate test.
SETUP: CLOCK - neg. edge TPI0 (LMYPA)
START - neg. edge TP7 (SA GATE)
STOP - pOSe edge TP7 (SA GATE)
VH
- PCP5
- KEY SIGNATURE
+
This signature is with drive 1 connected.
,;
- This signature is with drive o connected.
U I- I FHP9
U 1- 3 FHP9 +
u 1- 7 2603 +
u 1-13 FHP6
u 1-14 0000 +/FHP9 +1
U 1-17 260F
U 2- 2
u 2- 3
u 2- 4
U 2- 5
U 2- 6
U 2- 7
u 2- 8
U 2- 9
U 2-10
u 2-11
U 2-12
U 2-13
U 2-14
U 2-19
u 2-38
u 2-39

C6F7
CH09
H18D
CU94
5944
H700
9PIH
H70D
C8H3
059F
9PIH
059F
4F81
PCP5
0000
2814

u 4- 1 0000
u 4- 2 AHA7
u 4- 3 PCP5
U 44u 4U 4U 4U

4
5
6
8
9

8-26 AP

559F
CUH5
AHA7
10HO
CUH5

+
+
+
+

+
+
+
+

Service - Model 64110A

U
U
U
U

4-10 UC35
4-11 080F
4-12 3A65
4-13 CH09

U
U
U
U
U
U
U
U
U

7- 1
7- 2
7- 3
7- 4
7- 6
7- 8
7-11
7-12
7-13

UC35
PCP5
PCP5
PCP5
10HO
PCP5
UC35 +
5430 +
PCP5

U
U
U
U
U
U
U
U

8- 1
8- 3
8- 6
8- 8
8- 9
8-10
8-11
8-13

S88P
PCPS
FU75
S430
CUHS
PCP5
PCP5
PCP5

U 11- 1
U 11- 2
U 11- 5
U 11- 6
U 11- 9
U 11-11
U 11-12
U 11-15
U 11-16
U 11-19

248A
SU1F
12HU
p6cc
7U1F
PCPS
P943
C4PA
PS7A
1199

U 12- 1
U 12- 2
U 12- 3
U 12- 4
U 12- 5
U 12- 6
U 12- 7
U 12- 8
U 12- 9
U 12-10
U 12-11
U 12-12
U 12-13
U 12-14
U 12-15
U 12-16
U 12-17
U 12-18
U 12-19

SU1F
1199
12HU
P57A
p6cc
C4PA
7U1F
P943
PCP5
0000
0000
PCPS
P943
7U1F
C4PA
p6cc
P57A
12HU
1199
8-27 AP

Service - Model 64110A

U 12-20 5U1F
U 13- 1
U 13- 2
U 13- 3
U 13- 4
U 13- 5
U 13- 6
U 13- 7
U 13- 8
U 13- 9
U 13-10
U 13-11
U 13-13
U 13-14
U 13-15
U 13-16
U 13-17
U 13-18
U 13-19
U 13-20

5U1F
1199
12HU
P57A
p6cc
C4PA
7UlF
P943
PCP5
0000
PCP5
FU75
5F17
PCP5
10HO
559F
H50F
H42F
2C8P

U 19- 1
U 19- 3
U 19- 7
U 19-12
U 19-13
U 19-17

2603
FHP9 +
FHP9 +
0000/2603 "
260F
260F

U 22- 4
U 22- 5
U 22- 6
U 22- 8
U 22- 9
U 22-10
U 22-11
U 22-12
U 22-13

FHP6
2603
2603
FHP9
FHP9
260F
260F
FHP6
OOOU

U 24- 1 FHP9
U 25- 1
U 25- 2
U 25- 3
U 25- 4
U 25- 5
U 25- 6
U 25- 8
U 25- 9
U 25-10
U 25-11
U 25-12
U 25-13

8-28 AP

260F
PCP5
PCP5
0000
PCP5
FHP9
2603
PCP5
0000
PCP5
PCP5
FHP6

+

+
+
+
+
+
+
+
+

Service - Model 64110A

U 26- 1
U 26- 3
U 26- 4
U 26- 7
U 26- 8
U 26-11
U 26-13
U 26-14
U 26-17
U 26-18

PCP5
059F
059F
H700
H700
PU2A
4F81
9P1H
C8H3
9P1H

U 27- 1
U 27- 2
U 27- 5
U 27- 6
U 27- 9
U 27-11
U 27-12
U 27-15
U 27-16
U 27-19

1UFH
059F
059F
H700
H700
PCP5
4F81
9P1H
C8H3
9P1H

U 28- 2
U 28- 5
U 28- 6
U 28- 9
U 28-11
U 28-12
U 28-15
U 28-16
U 28-19

C215
PCP5
7316
FUU2
PCP5
19A1
0000
6PHO
2922

U 29- 1
U 29- 3
U 29- 5
U 29- 6
U 29- 7
U 29- 8
U 29- 9
U 29-11
U 29-12
U 29-13
U 29-14
U 29-15
U 29-16
U 29-18
U 29-19

588P
H700
H700
FHP9
OS9F
6UF8
059F
CFCA
4F81
PCP5
9P1H
2603
C8H3
9P1H
588P

U 30U 30U 30U 30U 30U 30U 30-

0000
A199
7U1F
5U1F
3199
88FF
1199

1
2
3
4
5
6
7

+
+
+
+
+
+
+
+

+

+
+
+

8-29 AP

Service - Model

U 30- 8
U 30- 9
U 30-11
u 30-12
U 30-13
u 30-14
u 30-15
u 30-16
u 30-17
u 30-18
u 30-19

12HU
096u
PCP5 +
PAc6
P943
P57A
6FAA
PH4A
p6cc
C4PA
4462

u 32- 1
U 32- 2
U 32- 3
U 32- 4
U 32- 5
U 32- 6
U 32- 7
U 32- 9
U 32-10
U 32-11
U 32-12
U 32-13
u 32-14
u 32-15

P810
FF9A
FF9A
277U
277U
PCP5
03u5
277U
FF9A
PCP5
248A
FF9A
0000
0000

u 37- 1
u 37- 2
U 37- 3
U 37- 4
u 37- 5
u 37- 6
u 37- 7
u 37- 9
U 37-10
U 37-11
U 37-12
U 37-13
u 37-14
u 37-15

Al99
4462
PH4A
6FAA
3199
88FF
096u
559F
H50F
H42F
2C8P
0000
0000
PAc6

u 38- 1
u 38- 3
u 38- 4
u 38- 8
u 38-12
U 38-16
u 38-17

0000
PCP5
FHP5
260F
FHP9
2603
0000

u 39U 39u 39u 39u 39-

F3Ul
0000
PCP5
PCP5
842H

1
2
3
4
5

8-30 AP

64110A

Service - Model 64110A
U 39- 6
u 39- 7
U 39- 9
U 39-10
U 39-11
U 39-12
U 39-13
U 39-14
U 39-15

6UF8
CFCA
575U
PCP5
PCP5
0000
10HO
19A1
19A1

U 40- 1
U 40- 2
U 40- 3
U 40- 4
U 40- 5
U 40- 6
U 40- 7
U 40- 9
U 40-10
U 40-11
U 40-12
U 40-13
U 40-14
U 40-15

559F
PCP5
FUU2
CU94
PCP5
2922
5944
CH09
7316
0000
5F17
6PHO
C215
0000

U 44- 1
U 44- 3
U 44- 4
U 44- 7
U 44- 8
U 44-11
U 44-13
U 44-14
U 44-17
U 44-18

PCP5
059F
059F
H700
H700
6624
4F81
9P1H
C8H3
9P1H

U 45- 1
U 45- 2
U 45- 5
U 45- 6
U 45- 9
U 45-11
U 45-12
U 45-15
U 45-16
U 45-17

AHU4
059F
059F
H700
H700
PCP5
4F81
9P1H
C8H3
79H8

U 46U 46U 46U 46U 46U 46U 46U 46-

PCP5
FHP6
H700
H700
FHP6
260F
9P1H
4F81

1
2
3
4
5
6
7
8

+
+
+
+
+
+
+
+
+
+

+
+

+
+

8-31 AP

Service - Model 64ll0A
U 46- 9
U 46-10
U 46-11
U 46-12
U 46-13
U 46-14
U 46-15
u 46-16
U 46-17
u 46-18
U 46-19

260F
0000
CHHU
FHP6
059F
059F
FHP6
260F
c8H3
9P1H
260F

U 47- 1
U 47- 2
U 47- 3
u 47- 4
U 47- 5
U 47- 6
U 47- 7
U 47- 8
U 47- 9
U 47-11
U 47-12
U 47-13
U 47-14
u 47-15
U 47-16
U 47-17
u 47-18
U 47-19

080F
260F
H700
260F
H700
260F
059F
260F
059F
FHP6
4F81
FHP6
9P1H
FHP6
C8H3
FHP6
9P1H
080F

U 48- 1
u 48- 2
U 48- 3
U 48- 4
u 48- 5
U 48- 6
U 48- 7
U 48- 8
U 48- 9
U 48-11
U 48-12
U 48-13
U 48-14
U 48-15
U 48-16
u 48-17
U 48-18
u 48-19

0000
588p
8H32
u66c
UC35
C6F7
51A1
9U2U
H180
0000
PU2A
P27A
03c4
lUFH
6624
u067
67F7
AHU4

u 49u 49U 49u 49U 49-

67F7
u067
03c4
P27A
8H32

1
2
3
4
5

8-32 AP

+
+
+
+

Service - Model 64110A

U 49- 6
u 49- 7
u 49- 9
U 49-10
U 49-11
U 49-12
U 49-13
U 49-14
U 49-15

u66c
51Al
9U2U
2C8P
H42F
H50F
559F
0000
0000

U 50- 1
U 50- 2
U 50- 3
U 50- 8
U 50- 9
U 50-10

3897 +
OOOU +
ooou
PCP5 +
PCP5
PCP5

U 51U 51U 51U 51U 51U 51-

CFCA +
6UF8 +
H372
H372
H372
3897

1
2
3
4
5
6

U 52- 1
U 52- 2
U 52- 3
U 52- 4
U 52- 5
U 52- 6
U 52- 7
U 52- 9
U 52-10
U 52-11
U 52-12
U 52-13
U 52-14
U 52-15

A754
2770
2770
PCP5
0000
03U5
PCP5
PCP5
248A
0000
PCP5
0000
248A
PCP5

U 61- 2
U 61- 3
U 61- 4
U 61- 5
U 61- 6
U 61- 8
U 61- 9
U 61-11
U 61-12
U 61-14
U 61-15
U 61-16
U 61-17
U 61-18

0000
FF9A
4FC1
P810
0000
PCP5
0000
PCP5
0000
PCP5
03U5
A754
2770
0000

8-33 AP

Service - Model 64110A
Table 8-4.

SA Loop B

INTERFACE LOOP B
PC BOARD: 64110-66509

Floppy control

CIRCUITRY TESTED: Floppy State Machine
PROCEDURE: Remove U29 mode buffer (U29 can be tested by exchanging
with U47). Remove all option boards. Move E2 TEST jumper
to interface TEST position in XU12. Press DSA 1 soft key
to initiate test.
SETUP: CLOCK - neg. edge TP10 (LMYPA)
START - neg. edge TP8 (LRST)
STOP - pos. edge TP8 (LRST)
VH
- H9AO
- KEY SIGNATURE
+
U 2- 2 PCF9 +
U 2- 4 12P3 +

u 4- 4 1875 +
u 4-10 7226
U 4-12 Fc43 +

u 7- 1 7226
u 7-11 7226

+
+

u 8- 1 1046

+

U 11- 1
U 11- 2
U 11- 3
U 11- 5
U 11- 6
U 11- 9
U 11-11
U 11-12
U 11-15
U 11-16
U 11-19

0001
8211
6PF2
7c65
2137
33FH
H9AO
635A
FPOC
C623
25CF

U 26-11

A240 +

U 27- 1 F020 +
U 29- 1 1046 +
U 29- 19 1046 +
U 30U 30U 30U 30-

1
2
3
4

8-34 AP

0000
99P6
33FH
8211

Service - Model 64110A

U 30- 5
u 30- 6
U 30- 7
U 30- 8
u 30- 9
U 30-11
U 30-12
u 30-13
u 30-14
u 30-15
u 30-16
u 30-17
u 30-18
u 30-19

u478
92HP
25CF
7c65
CHC2
H9AO
04HH
635A
C623
6p61
25PC
2137
FPOC
H275

u 37- 1
u 37- 2
u 37- 3
u 37- 4
u 37- 5
u 37- 6
u 37- 7
u 37- 9
u 37-10
U 37-11
U 37-12
u 37-13
u 37-14
u 37-15

99P6
H275
25PC
6p61
u478
92HP
CHC2
1875
6P9H
9354
UH4A
0000
0000
04HH

u
u
u
u

Fc43
0000
H9AO
12P3

38- 5
38- 9
38-11
38-15

u 44-11 AOP5 +
u 45- 1 C425 +
u 48- 1
u 48- 2
u 48- 3
u 48- 4
u 48- 5
u 48- 6
u 48- 7
u 48- 8
U 48- 9
U 48-11
U 48-12
U 48-13
U 48-14
U 48-15
U 48-16
U 48-17

0000
1046
4A6F
p44F
7226
PCF9
CH73
4U26
12P3
0000
A240
2P61
PAAO
F020
AOP5
2C2C
8-35 AP

Service - Model 64l10A

u 48-18 02AA
u 48-19 C425
u 49- 1
U 49- 2
U 49- 3
U 49- 4
U 49- 5
U 49- 6
U 49- 7
u 49- 9
u 49-10
U 49-11
U 49-12
U 49-13
u 49-14
u 49-15

8-36 AP

02AA
2C2C
PAAO
2P61
4A6F
p44F
CH73
4U26
UH4A
9354
6P9H
1875
0000
0000

Service - Model 64110A
Table 8-5.

SA Loop M

INTERFACE LOOP M
PC BOARD: 64110-66S09

Floppy control

CIRCUITRY TESTED: All data (I/O bus) to and from floppy controller
PROCEDURE: Remove U29 mode buffer (U29 can be tested by exchanging
with U47). Remove all option boards. Move E2 TEST jumper
to interface TEST position in XUl2. Press DSA 1 soft key
to initiate test.
SETUP:

CLOCK - pos. edge TP10 (LMYPA)
START - neg. edge TP7 (SA GATE)
STOP - pos. edge TP7 (SA GATE)
VH
- PCPS
- KEY SIGNATURE
+

U 8-12

407C +

U 11- 3
U 11- 4
U 11- 7
U 11- 8
U 11-13
U 11-14
U 11-17
U 11-18

HPOC
Ac42
FF31
HS82
403H
8198
HF8A
F858

U
U
U
U
U
U
U
U

26- 2
26- S
26- 6
26- 9
26-12
26-15
26-16
26-19

UCA9
438U
P366
FS96
6HA3
407C
3841
CF2H

U
U
U
U
U
U
U
U

27- 3
27- 4
27- 7
27- 8
27-13
27-14
27-17
27-18

UCA9
438U
P366
FS96
6HA3
407C
3841
CF2H

U
U
U
U

28282828-

+
+

+
+
+
+
+
+
+

+
+
+
+
+
+
+
+

+
+
+

+
+
+
+

3 UCA9 +
4 438U +
7 P366 +
8 F596 +
8-37 AP

Service - Model 64110A

U 28-13
U 28-14
U 28-17
U 28-18

6HA3
407C
3841
CF2H

+
+

U 44- 2
U 44- 5
U 44- 6
U 44- 9
U 44-12
U 44-15
U 44-16
U 44-19

H582
FF31
Ac42
HPOC
403H
8198
HF8A
F858

+
+
+

u 45- 3
U 45- 4
U 45- 7
U 45- 8
U 45-13
U 45-14
U 45-17
U 45-18

H582
FF31
Ac42
HPOC
403H
8198
HF8A
F858

8-38

AP

+
+

+
+
+
+
+

+
+
+
+
+
+
+
+

Service - Model 64110A
Table 8-6.

SA Loop C

INTERFACE LOOP C
PC BOARD: 64110-66509 Floppy control
CIRCUITRY TESTED: I/O bus decoding
PROCEDURE: Remove U29 mode buffer (U29 can be tested by exchanging
with U47). Remove all option boards. Move E2 TEST jumper
to interface TEST position in XUl2. Press DSA 1 soft key
to initiate test.
SETUP: CLOCK - pos. edge TP7 CPU/IO board (LBIOSB)
START - pos. edge TP6 CPU/IO board (I/O SA LATCH)
STOP ~ neg. edge TP6 CPU/IO board (I/O SA LATCH)
VH
- 9CCH
+
- KEY SIGNATURE

U 5- 6 H164 +
U 7- 3 H164 +
U 7-13 H164 +
U 8- 3 lFAA +
U 8-10 H543 +
U 8-11 lFAA +
U 11- 1 la8H +
U 11-11 H164 +
U 12- 9 H164
U 13- 9 H164 +
U 26- 1

02HP +

U 27-11 FC37 +
U 28-11

lFAA +

U 30-11 H164 +
U 32- 1
U 32- 2
U 32- 3
U 32- 4
U 32- 5
U 32- 6
U 32- 7
U 32- 9
U 32-10

3H75
P552
P552
7PPU
7PPU
9CCH
6662
cp45
P552
8-39 AP

Service - Model 64110A

U 32-11 9CCH
U 32-12 188H
U 32-13 P552
U 32-14 0000
U 32-15 0000
U 41- 1
U 41- 2
U 41- 3
U 41- 4
U 41- 5
U 41- 6
U 41-12

FF56
3CHU
190F
0000
0000
8CUl
H164

U 44- 1

02HP +

U 45-11 FC37 +
U 48-11

4AH9 +

U 52- 1
U 52- 2
U 52- 3
U 52- 4
U 52- 5
U 52- 6
U 52- 7
U 52- 9
U 52-10
U 52-11
U 52-12
U 52-13
U 52-14
U 52-15

02HU
CP45
cp45
H543
0000
6662
1FAA
FC37
188H
0000
02HP
0000
188H
H164

U 61- 3
U 61- 4
U 61- 5
U 61- 6
U 61- 8
U 61- 9
U 61-11
U 61-12
U 61-14
U 61-16
U 61-17

7PPU
9962
3H75
0000
9CCH
104F
8CUl
0000
9CCH
02HU
7PPU

8-40 AP

Service - Model 64110A
Table 8-7.

SA Loop D

INTERFACE LOOP D
PC BOARD: 64110-66509

Floppy control

CIRCUITRY TESTED: Data written to floppy drives
PURPOSE: Remove U29 mode buffer (U29 can be tested by exchanging
with U47). Remove all option boards. Move E2 TEST jumper
to interface TEST position in XU12. Press DSA 1 soft key
to initiate test.
SETUP: CLOCK - neg. edge TP16 (near U 53)
START - pos. edge TP6 CPU/IO board (I/O SA LATCH)
STOP - neg. edge TP6 CPU/IO board (I/O SA LATCH)
VH
- 399F
+
- KEY SIGNATURE

U 2-19

6C35 +

U 4- 5

OA66 +

u 4- 9 OA66

+

u 7-12 33UA

+

U 8- 3

5613

u 8- 8 33UA
U
U
U
U

8- 9 OA66
8-10 6U8U
8-11 5613
8-12 U74A

U 11- 3 1443 +
U 11- 4 1443 +
U 11- 7 46cA +
U 11- 8 46cA +
U 11-13 7c48 +
U 11-14 29C1 +
U 11-17 29UO +
U 11-18 29C1 +
U 26- 2
U 26- 5
U 26- 6
U 26- 9
U 26-12
U 26-15
U 26-16
U 26-19

C4F8
98F4
71P3
606H
HAl5
U74A
U834
52PF

+
+
+
+
+
+
+
+

8-41 AP

Service - Model 64110A

U 27- 3
U 27- 4
U 27- 7
U 27- 8
U 27-13
U 27-14
U 27-17
U 27-18

C4F8
98F4
71P3
606H
HAl5
U74A
U834
52PF

U 28- 2
U 28- 3
U 28- 4
U 28- 5
U 28- 6
U 28- 7
U 28- 8
U 28- 9
U 28-11
U 28-12
U 28-13
U 28-14
U 28-15
U 28-16
U 28-17
U 28-18

5u64
C4F8
98F4
6C35
19P9
71P3
606H
9064
5613
6651
HAl 5
U74A
UTUC
H45F
U834
52PF

+
+
+
+
+
+
+
+

U 39-14 6651
U 39-15 6651

+
+

U 40- 3
U 40- 6
U 40-10
U 40-13
U 40-14

9064
086p
19P9
H45F
5u64

+
+
+
+
+

U 44- 2
U 44- 5
u 44- 6
U 44- 9
U 44-12
U 44-15
U 44-16
U 44-19

46cA
46cA
1443
1443
7c48
29C1
29UO
29C1

+
+
+
+
+
+
+
+

U 45- 3
U 45- 4
U 45- 7
U 45- 8
U 45-13
U 45-14
U 45-17
U 45-18

46cA
46cA
1443
1443
7c48
29C1
29UO
29C1

+
+
+
+
+
+
+
+

8-42 AP

Service - Model 64110A
Table 8-8.

SA Loop E

INTERFACE LOOP E
PC BOARD: 64110-66509 Floppy control
CIRCUITRY TESTED: Floppy read latches
PROCEDURE: Remove U29 mode buffer (U29 can be tested by exchanging
with U47). Remove all option boards. Move E2 TEST jumper
to interface TEST position in XUl2. Press DSA 1 soft key
to initiate test.
SETUP: CLOCK - pos. edge TP11 (LRD)
START - neg. edge TP7 (SA GATE)
STOP - pos. edge TP7 (SA GATE)
VH
- 0007
- KEY SIGNATURE
+

U
U
U
U
U
U
U
U

26- 2
26- 5
26- 6
26- 9
26-12
26-15
26-16
26-19

0003
0003
0003
0003
0003
0003
0003
0003

U
U
U
U
U
U
U
U

27- 3
27- 4
27- 7
27- 8
27-13
27-14
27-17
27-18

0003
0003
0003
0003
0003
0003
0003
0003

U
U
U
U
U
U
U
U

44- 2
44- 5
44- 6
44- 9
44-12
44-15
44-16
44-19

0002
0002
0002
0002
0001
0001
0001
0001

U
U
U
U
U
U

45- 3
45- 4
45- 7
45- 8
45-13
45-14

0002
0002
0002
0002
0001
0001

+
+
+
+
+
+

+
+

8-43 AP

Service - Model 64110A

u 45-17 0001
u 45-18 0001

8-44 AP

Service - Model 64110A
Table 8-9.

SA Loop F

INTERFACE LOOP F
PC BOARD: 64110-66509 Floppy control
CIRCUITRY TESTED: Data out of U29
PROCEDURE: Remove U29 mode buffer (U29 can be tested by exchanging
with U47). Remove all option boards. Move E2 TEST jumper
to interface TEST position in XU12. Press DSA 1 soft key
to initiate test.
SETUP: CLOCK - pos. edge TP14 (LOEM)
START - neg. edge TP7 (SA GATE)
STOP - pos. edge TP7 (SA GATE)
VH
- 0003
- KEY SIGNATURE
+

U
U
U
U
U
U
U
U

2- 7
2- 8
2- 9
2-10
2-11
2-12
2-13
2-14

0002
0002
0002
0002
0002
0002
0002
0002

U
U
U
U
U
U
U
U

27- 2 0002
27- 5 0002
27- 6 0002
27- 9 0002
27-12 0002
27-15 0002
27-16 0002
27-19 0002

U
U
U
U
U
U

46- 7
46- 8
46-13
46-14
46-17
46-18

0002
0002
0002
0002
0002
0002

+
+
+
+
+
+
+
+

+
+
+
+
+
+

8-45 AP

Service - Model 64110A
Table 8-10.

SA Loop G

INTERFACE LOOP G
PC BOARD: 64110-66509

Floppy control

CIRCUITRY TESTED: Data from u45
PROCEDURE: Remove U29 mode buffer (U29 can be tested by exchanging
with U47). Remove all option boards. Move E2 TEST jumper
to interface TEST po.si tion in XUl2. Press DSA 1 soft key
to initiate test.
SETUP: CLOCK - pos. edge TP12 (LOEL)
START - neg. edge TP7 (SA GATE)
STOP - pos. edge TP7 (SA GATE)
VH
- OUP7
+
- KEY SIGNATURE

U
U
U
U
U
U
U
U

2- 7
2- 8
2- 9
2-10
2-11
2-12
2-13
2-14

OA2H
OF24
OA2H
OF14
0201
OF24
0201
0408

+
+
+
+
+
+
+
+

U 45- 6 OA2H
U 45- 9 OA2H
U 45-12 0408
U 45-15 OF24
U 45-16 OF14
U 45-19 OF24
U 46- 3
U 46- 4
U 46- 7
U 46- 8
U 46-13
U 46-14
U 46-17
u 46-18

8-46 AP

OA2H
OA2H
OF24
0408
0201
0201
OF14
OF24

+
+
+
+
+
+

+
+

Service - Model 64110A
Table 8-11.

SA Loop H

INTERFACE LOOP H

PC BOARD: 64110-66509

Floppy control

CIRCUITRY TESTED: Data from u47
PROCEDURE: Remove U29 mode buffer (U29 can be tested by exchanging
with U47). Remove all option boards. Move E2 TEST jumper
to interface TEST position in XUl2. Press DSA 1 soft key
to initiate test.
SETUP: CLOCK - pos. edge TP9
START - neg. edge TP7
STOP - pos. edge TP7
VH
- 0003
- KEY SIGNATURE
+

u

44- 3
44- 4
44- 7
44- 8
44-13
44-14
44-17
44-18

0002
0002
0002
0002
0001
0001
0001
0001

U 47- 1

0000

U
U
U
U
U
U
U

(SA GATE)
(SA GATE)

+
+
+
+
+
+
+
+

u 47- 3 0002
U
U
U
U
U

47- 5
47- 7
47- 9
47-12
47-14
u 47-16
U 47-18
u 47-19

0002
0002
0002
0001
0001
0001
0001
0000

8-47 AP

Service - Model 64110A
Table 8-12.

SA Loop I

INTERFACE LOOP I
PC BOARD: 64110-66509

Floppy control

CIRCUITRY TESTED: Data from floppy controller (MSB)
PROCEDURE: Remove U29 mode buffer (U29 can be tested by exchanging
with U47). Remove all option boards. Move E2 TEST jumper
to interface TEST position in XU12. Press DSA 1 soft key
to initiate test.
SETUP: CLOCK - pos. edge u26-PIN 11 (LLM)
START - neg. edge TP7 (SA GATE)
STOP - pos. edge TP7 (SA GATE)
VH
- 07U3
- KEY SIGNATURE
+

U
U
U
U
U
U
U
U

2- 7
2- 8
2- 9
2-10
2-11
2-12
2-13
2-14

07H3
07H3
07H3
07H3
07H3
07H3
07H3
07H3

U
U
U
U
U
U
U
U

26- 3
26- 4
26- 7
26- 8
26-13
26-14
26-17
26-18

07H3
07H3
07H3
07H3
07H3
07H3
07H3
07H3

U 29- 1 0020
U 29- 3 07H3
U 29- 5 07H3
U 29- 7 07H3
U 29- 9 07H3
U 29-12 07H3
U 29-14 07H3
U 29-16 07H3
U 29-18 07H3
U 29-19 0020

8-48 AP

+
+
+
+
+
+
+
+

Service - Model 64110A
Table 8-15.

SA Loop K

DATA SEPARATOR LOOP K
PC BOARD: 64110-66509 Floppy control
CIRCUITRY TESTED: Data separator circuitry
PROCEDURE: Remove all option boards. Move E1 TEST jumper to
separator TEST position in XU5. Press DSA 2 soft key
to initiate test.
SETUP: CLOCK
START
STOP
VH
+

U
U
U
U
U
U

555555-

1 5944
2 5U2F
3 8p80
4 CAHF
5 5A44
6 0000

U
U
U
U

9999-

1
2
6
7

7CA3
7CA3
55AP
55AP

U 11- 1
U 11- 2
U 11- 3
U 11- 4
U 11- 5
U 11- 6
U 11- 7
U 11- 8
U 11- 9
U 11-11
U 11-12
U 11-13
U 11-14
U 11-15
U 11-16
U 11-17
U 11-18
U 11-19

5690
5944
HPu6
27PU
8p80
5A44
H8u7
64A3
846p
0000
C107
OP71
5691
0000
CAHF
19F6
P8F9
5U2F

-

pos. edge TP10 (LMYPA)
neg. edge U11-PIN 15 (SA GATE)
pos. edge U11-PIN 15 (SA GATE)
HCH5
- KEY SIGNATURE

+
+
+
+

U 14- 1
U 14- 2
U 14- 3
U 14- 5
U 14- 9
U 14-11
U 14-12
U 14-13

5A44
HCH5
383P
HH3A
H015
383P
HCH5
CAHF

U 15- 1
U 15- 2
U 15- 3
U 15- 4
U 15- 5
U 15- 6
U 15- 7
U 15- 9
U 15-10
U 15-11
U 15-12
U 15-13
U 15-14
U 15-15

0000
P733
5A44
0000
0000
4H3A
0000
4U2F
H015
0000
0000
0000
5C86
0000

U 16U 16U 16U 16U 16U 16-

1 4FA6
2 0000
3 HCH5
4 HCH5
5 7CA3
7 55AP

U 16-10 HCH5
U 16-11 HCHF
U 16-12 0000
U 16-13 4U2F
u 16-14 4FA6
U 16-15 4U2F
U 17- 1
U 17- 2
U 17- 3
U 17- 4
U 17- 5
U 17- 6
U 17- 9
U 17-10
U 17-11
U 17-12
U 17-13
U 17-14
U 17-15
U 18U 18U 18U 18-

H015
0000
OHA5
165A
2P64
383P
6P1C
HCH5
2P64
0000
0000
OHA5
5623

1 0000
2 0000
3 6P1C
4 HCH5

8-55 AP

Service - Model 64110A

5C86
8053
5944
OHA5

U 38- 8
U 38-12
U 38-14
U 38-16

5690
8H45
HCH5
HCH5

U 28- 4 UUCF
U 28- 5 165A
U 28-11 8H45

U 50- 4
U 50- 5
U 50- 6
U 50-11
U 50-12
U 50-13

CH11
82F8
82A4
5623
8053
OHA5

U 51- 8
U 51- 9
U 51-10
U 51-11
U 51-12

0000
HCH5
HCH5
HCH5
0000

U 18- 5
U 18- 6
U 18-11
U 18-15

U 31- 4
U 31-10
U 31-11
U 31-12
U 31-13

HCH5
HCH5
5944
HCH5
0000

U 32- 1 8H45
U 32-12 5690
U 32-13 HCH5

u 51-13 0000
U 33- 1
U 33- 2
U 33- 6
U 33- 8
U 33-10
U 33-12
U 33-13

HCH5
82A4
488C
82F8
CH11
0000
0000

34u 34U 34u 34U 34u 34-

HCH5
HCH5
OHA5
P733
488C
F82F

U

U

1
2
4
6
8
9

35- 9 2P64

U 38- 4 0000
U 38- 6 0000

8-56 AP

u 52- 1
u 52- 5
u 52- 6
U 52- 7
U 52- 9
u 52-10
U 52-12
U 52-14
U 52-15

HCH5
0000
5690
8H45
8H45
5690
HCH5
5690
0000

u 53- 1
u 53- 2
U 53- 3
U 53-11
U 53-12
U 53-13

82A4
84u9
F82F
84U9
5U2F
HCH5

Service - Model 64110A
Table 8-16.

SA Loop L

DATA SEPARATOR LOOP L
PC BOARD: 64110-66509

Floppy control

CIRCUITRY TESTED: U15 multiplexer
PROCEDURE: Remove all option boards. Move E1 TEST jumper to
separator TEST position in XU5. Check 015 multiplexer
to make sure it is multiplexing the HDATAlUS signal
properly. There are no signature nodes for this loop,
just verify that VB is correct. Press DSA 2 soft key
to initiate test.
SETUP:

CLOCK - pos. edge Ol5-PIN 9
START - pos. edge Ol8-PIN 11
STOP - pos. edge Ol8-PIN 11
VH
- 72A2

8-57/(8-58 blank) AP

Service - Model 64110A

,....I
()

a·
a·

TP1

~

Iu I
J1

I

U1

U3

0

,,

~

U20

l'Y1i

cr

BGB tIl:]
I

,I

U11

U13

T0 U12

U19
TP4

IIIIII

B36

-C17-

o

U27

TP7

U28

0
TP9
0

U30

U29

,

I

o

a>

M

N

()

()

B~8

,....
M

o

U47

U46

~
Ir

,....

,

N

Ir

0N

Y

-C15-1i:
I

TP88c25_

U38

U 39

BU40

I

,

-R36-

'?

TP10

BU41

-C43-

-C41-

U52

TP16

EJU53

o

-R29-

()
I

MARGIN -R37TEST
TP17

U59

D0D~

I

....

M

()
I

U61

I

Ir

0

I

N
....

TP14

M

CO)

-C26-

B B
00
0 B BB

. o
U48

N

U56

0 7 Or
....

TP12

I

U45

0' [1'

I

I

U44

-R11-

()

()

0 TP15

I

....
N

-C28-

-C27-

-R8,.... - R 9 [i - R10-

,

TP13

I

-C5- - C 6 -

~0TP

'?I

006D []'
0'0 o~

U37

TP11

0,

-C14-

TP5

- C18-

-C23-

o

_ R 3 _ - R4 - R 5_-CR1-_
CR2
- R 6 - _ R7 _

BB
-C13-

U2'

~~~~~~hI I

U8

I

o

U26

If

-C3-

-C22-

U54

U7

Irlr

U22

U21

I~~ ~

I

....

()

NM
,....,....

U2

~23B
BI E]*B
!.
I

~

()

I

- C12-

~

I

N

L:::J

M

()
I

C34
J3

~

Figure 8-17.
8-60 AP

;~~':_:

________J_4_______

_ _ _J_5_ _

~:~

RS-232/Mini Control Component Locator llD

0:

2

Service - Model 64110A

Figure 8-19.

8-62 AP

Component Locator for Service Sheet 1

Service - Model 64110A

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Figure 8-20.
Servo Electronics Service Sheet 1

8-63 AP

Service - Model 64110A

Figure 8-21. Component Locator for Service Sheet 2
8-64 AP

Service - Model 64110A
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Figure 8-22.
Drive Electronics Service Sheet 2
8-65 AP

Service - Model 64110A
8-144. LOGIC CONVENTION.
8-145. The positive logic convention is used for logic variables and
the circuits comprising the 64110A flexible disc drive. positive
logic difines a logic 1 as a more positive voltage (high) and a logic
o as the more negative voltage (low). Ideally, the low and high
voltage levels are OV and +5V, respectively. Due to voltage drops over
interconnecting PC board traces, etc., the actual levels may vary from
these ideal values. Therefore, the voltage levels for a logic 1 and 0
are defined as follows:
TTL Voltage Levels
Binary Quantity
Input
Input
Output
Output

0
1
0
1

Voltage Limit
<

0.8 V

>

2.0 V

<
>

0.4 V

2.4 V

8-146. LOGIC SYMBOLOGY.
8-141. Table 8-4 gives a summary of the logic symbology used in this
manual.

8-66 AP

Service - Model 64110A
Table 8-17.

Logic Symbology

GENERAL
All signals flow from left to right, relative to the symbol's orientation with inputs on the left side of the symbol, and
outputs on the right side of the symbol (the symbol may be reversed if the dependency notation is a single term.)
All dependency notation is read from left to right (relative to the symbol's orientation).
An external state is the state of an input or output outside the logic symbol.
An internal state is the state of an input or output inside the logic symbol. All internal states are True = High.

SYMBOL CONSTRUCTION
Some symbols consist of an outli ne or combination of outlines together with one or more qualifying symbols, and the
representation of input and output lines.

&

INPUTS--'-<

OUTPUTS

"""U98

Some have a common Control Block with an array of elements:
CONTROL
BLOCK

CHIP
FUNCTION
CTR DIV 16
M1

COMMON
~OUTPUT

COMMON
CONTROL
INPUTS

15
DEPENDENCY
NOTATION

ARRAY
ELEMENTS

INPUTS

~

LEAST
U99

4
5
6

~SIGNIFICANT

ELEMENT

[0]
7D
7D
7D

[1 ]
[2]
[3]

13
14

12

}

~OUTPUTS

11

~MOST

SIGNIFICANT
ELEMENT

CONTROL BLOCK - All inputs and dependency notation affect the array elements directly. Common outputs are
located in the control block. (Control blocks may be above or below the array elements.)
ARRAY ELEMENTS -All array elements are controlled by the control block as a function of the dependency notation.
Any array element is independent of all other array elements. Unless indicated, the least significant element is always
closest to the control block. The array elements are arranged by binary weight. The weights are indicated by powers
of 2 (shown in [ ]).
LS-09-81 - 1

8-67 AP

Service - Model 64110A
Table 8-17.

Logic Symbology

INPUTS - Inputs are located on the left side of the symbol and are affected by their dependency notation.
Common control inputs are located in the control block and control the inputs/outputs to the array elements
according to the dependency notation.
Inputs to the array elements are located with the corresponding array element with the least significant element
closest to the control block.

OUTPUTS - Outputs are located on the right side of the symbol and are effected by their dependency notation.
Common control outputs are located in the control block.
Outputs of array elements are located in the corresponding array element with the least significant bit closest to
the control block.

CHIP FUNCTION - The labels for chip functions are defined, i.e., CTR - counter, MUX - multiplexer.

DEPENDENCY NOTATION
Dependency notation is always read from left to right relative to the symbol's orientation.
Dependency notation indicates the relationship between inputs, outputs, or inputs and outputs. Signals having a
common relationship will have a common number, i.e., C7 and 7D .... C7 controls D. Dependency notation
2,3,5,6+/1,C7 is read as when 2 and 3 and 5 and 6 are true, the input will cause the counter to increment by one
count .... or (I) the input (C7) will control the loading of the input value (7D) into the D flip-flops.
The following types of dependencies are defined:

a.

AND (G), OR (V), and Negate (N) denote Boolean relationship between inputs and outputs in any
combi nation.

b.

Interconnection (Z) indicates connections inside the symbol.

c.

Control (C) identifies a timing input or a clock input of a sequential element and indicates which inputs are
controlled by it.

d.

Set (S) and Reset (R) specify the internal logic states (outputs) of an RS bistable element when the R or S
input stands at its internal 1 state.

e.

Enable (EN) identifies an enable input and indicates which inputs and outputs are controlled by it (which
outputs can be in their high impedance state).

f.

Mode (M) identifies an input that selects the mode of operation of an element and indicates the inputs and
outputs depending on that mode.

g.

Address (A) identifies the address inputs.

h.

Transmission (X) identifies bi-directional inputs and outputs that are connected together when the
transmission input is true.

A
C
EN
G
M

DEPENDENCY NOTATION SYMBOLS
Address (selects inputs/outputs) (indicates binary range)
Negate (compliments state)
N
Control (permits action)
R
Re~et Input
Enable (permits action)
S
S~t Input
AND (permits action)
V
OR (permits action)
Interconnection
Mode (selects action)
Z
X
Transmission
LS-09-81 - 2

8-68 AP

Service - Model 64110A
Table 8-17_

Logic Symbology

OTHER SYMBOLS

n

Analog Signal

&

t:.. L:J Inversion

o

AND

~

Negation

Solidus (allows an input or output to have
more than one function)

/

~ Nonlogic Input/Output

} { Bit Grouping

[:>

Shift Right (or up)

\l

Buffer

~

Open Circuit (NPN) (external resistor)

Compare

\?

Open Circuit (PNP) (external resistor)

Dynamic

21

OR

Tri-State
Causes notation and symbols to effect
inputs/outputs in an AND relationship, and to
occur in the order read from left to right.

=1 Exclusive OR

~ Passive Pull Down (internal resistor)

( ) Used for factoring terms using algebraic
techniques.

1L Hysteresis

fr

[

?

-, Postponed

Interrogation
Internal Connection

Passive Pull Up (internal resistor)

] Information not defined.

«P

Logic symbol not defined due to complexity.

Shift Left (or down)

LABELS
BG
BI
BO
BP
CG
CI

Borrow Generate
Borrow Input
Borrow Output
Borrow Propagate
Carry Generate
Carry Input

CO
CP
CT
D
E
F

Carry Output
Carry Propagate
Content
Data Input
Extension (input or output)
Function

J
K

P
T

+

J Input
K Input
Operand
Transition
Count Up
Count Down

MATH FUNCTIONS

L
ALU
COMP
DIV

=

Adder
Arithmetic Logic Unit
Comparator
Divide By
Equal To

>
<

CPG
IT

P-Q

Greater Than
Less Than
Look Ahead Carry Generator
Multiplier
Subtractor

CHIP FUNCTIONS
BCD
BIN
BUF
CTR
DEC

Binary Coded Decimal
Binary
Buffer
Counter
Decimal

DIR
DMUX
FF
MUX
OCT

Directional
Demultiplexer
Flip-Flop
Multiplexer
Octal

RAM
RCVR
ROM
SEG
SRG

Random Access Memory
Line Receiver
Read Only Memory
Segment
Shift Register

DELAY and MUL TIVIBRATORS

n..n.

Astable

~

Delay

!J1

Nonretriggerable Monostable

NV

Nonvolatile

J1-

Retriggerable Monostable

LS-09-81 - 3

8-69 AP

Service - Model 64110A
8-148. MNEMONICS.
8-149. Signals in the 64110A flexible disc drive have been assigned
mnemonics that describe the active state and function of the signal
(see table 8-17). A prefix letter (H~ L, P, or N) is used to indicate
the active state of the signal and the remaining letters indicate its
function A "H" prefix indicates that the function is active in the
"high" state; a "L" prefix indicates that the function is active in
the "low" state; a "p" prefix indicates the clock signal is active on
the positive edge of the clock; a "N" indicates the clock is active on
the negative edge of the clock. Table 8-18 is a listing of the
mnemonics used on the service sheets.
Table 8-18. Mnemonics
MNEMONIC

DESCRIPTION

DSO-3

Drive Select 0 through 3.
When low, the drive is selected and will respond to step
or read/write commands. This system uses DSO only.

SA 0-1

High Address inputs 0-1.
These inputs in conjunction with the chip select and
write inputs select between the status register, track
register~ sector register, data register and command
registers internal to the mini disc controller chip.

HBYTE 3

High Byte 3.
When true,this signal indicates that three consecutive
bytes of zeros or ones have been received from the disc.

HBYTE 7

High Byte 7.
When true, this signal indicates that seven consecutive
bytes of zeros or ones have been received from the
floppy disc read electronics.

BDATAlUS

High Data 1 microsecond.
This signal pulses true for 1 microsecond whenever a
flux transition is detected from the disc drive.

HOIRC

High Direction.
When high the heads are stepped out (away from center) and
when low the heads are stepped in with each step pulse.

BDMAEN

High DMA Enable.
This signal is set true by the CPU wh~n it is ready for
a DMA operation. This signal is set to the false state
when the DMA operation is completed.

HOMARQ

High DMA Request.
Signal from CPU Interface/DMA state machine that indicates
that the mini disc controller chip is requesting a
DMA cycle.

8-70 AP

Service - Model 64110A
HDRQ

High Data Request.
When high indicates that the mini disc controller's data
register is full if a read operation is occurring, or empty
during a write operation. This line cleared when the CPU
does a read or write to the data register.

HINHIBIT

High Inhibit.
Signal in data separator circuitry which halts the VCO
during a sinkup cycle. When this signal goes to the
false state, the VCO is again started in phase with
incoming data.

HMDCRQ

High Mini Disc Controller Request.
HINTRQ a signal from mini disc controller chip which, when
true, indicates that the mini disc controller chip
wishes to interrupt the CPU operation.

HR5,6

High Register 5,6.
When in the true state indicates that the CPU is
communicating with the mini disc controller via
either register 5 or register 6 internal to the CPU.
The state of the registers is determined by LIC1 and LIC2.

HRCLK

High Read Clock.
Clock signal from data separator circuitry which is in
phase with the LRAWRD signal.

HRG

High Read Gate.
Signal from the mini disc controller chip which
indicates to the data separator circuitry that a field
of zeros or ones has been encountered. When true, it does
not allow data separator to re-syncronize.

HSA DO-7

High Signiture Analysis Data 0-7.
These signals are the outputs of the SA stimulus latch.
The lower byte of the LIOD (0-7) bus is used by the CPU
to make the interface and data separator circuitry
synchronous with the CPU.

HVCOE

High Voltage Control Oscillator Enable.
Compliment of LVCOE.

H2MHZC

High 2 MHz Clock.
The inverted 2 MHz clock used to clock data from the
output of the state machine.

LAO-2

Low Address 0-2.
Signals from CPU which are used to select the address
of mini disc controller chip or other registers in
which read and write operations are to occur.

LBEN

Low Buffer Enable.
When low, this signal enables the drive status buffers
and also resets the processor request flip-flop.

8-71 AP

Service - Model 64110A
LCS

Low Chip Select.
Input to the mini disc controller chip which enables
the CPU interface portion of the mini disc controller
chip.

LCRMCO,l

Low Clear Media Change 0,1.
Low true signals which clear there respective media
change flip-flops. These signals are controlled by the
CPU.

LDAL 0-7

Low Data Access Lines 0-7
Bidirectional lines that carry data and commands to and
from the mini disc controller chip, drive status register,
etc.

LDMAAK

Low DMA Acknowledge.
Signal to the CPU interface state machine which
indicates that the DMA request from the mini disc
controller has been acknowledged.

LDMAEN

Low DMA Enable.
Compliment of HDMAEN.

LDMAI

Low Direct Memory Access Interrupt.
An interrupt to the CPU when the MOC is requesting DMA and

LDMAEN is not true.
LDMAR

Low Direct Memory Access Request.
When low, indicates to the CPU that the MOC wants direct
access to memory.

LDOUT

Low Data Out.
Signal from CPU which indicates read or write operation on
the I/O bus (Low=Write). This is valid when LIOSB is low.

LDRQ

Low Data Request.
Compliment of HDRQ.

LICl-2

Low Interface Control 1 and 2.
These lines can provide up to four states used to control
peripheral devices. How these lines are controlled is
determined by software.

LINT

Low Interrupt.
The microprocessor pulls this line low to poll the
Input/Output Bus to determine which peripheral
device requested the interrupt.

LIODO-15

Low
The
bus
and

8-72 AP

Input/Output Data 0 through 15.
LIOD bus is a bi-directional bus. The CPU uses this
to communicate with I/O ports. Information is true low,
is used in conjunction with LPABO-3.

Service - Model 64110A
LIOSB

Low Input/Output Strobe.
When this signal goes from low to high, the data on the I/O
bus is valid.

LIR3

Low Interrupt Request 3.
Interrupt request from mini controller board to the
interrupt circuitry on the I/O board that the mini
controller is in need of service by the CPU.

LLL

Low Latch Least.
Signal from CPU interface state machine which latches
the least significant byte of data during a CPU read
cycle.

LLM

Low Latch Most.
Signal from CPU interface state machine which latches
the most significant byte of data during a CPU read
cycle.

LMDCI

Low Mini Disc Controller Chip Interrupt.
Flags signal to CPU that indicates that the mini disc
controller chip is currently requesting an interrupt.

LMCIR

Low Media Change Interrupt Request.
Interrupt signal from media change flip-flops indicating
that media has been changed on the disc.

LMDCHGO,l Low Media Change 0,1.
When low, the corresponding signal indicates that the
media has been changed on the appropriate disc.
LMR

Low Master Reset.
Input to the mini disc controller chip, when true, resets
internal status registers.

LMDCRQ

Low Mini Disc Controller Request.
Compliment of HMDCRQ.

LMYPA

Low My' Peripheral Address.
Goes low when the CPU is communicating with the mini drive
circuitry. This signal is formed when Peripheral Address 4
is accessed by the CPU. Also, LMYPA is used as the clock
during SA.

LNTRDYO,l Low Not Ready 0,1
When true, these signals indicate that the
corresponding disc drive is not ready. i.e.
index pulses have dropped below a specified rate.
LOEL

Low Output Enable Lower.
When true, this signal enables the least significant 8
bits of data to appear on the disc interface bus during
a microprocessor write cycle.

8-73 AP

Service - Model 64110A
LOEM

Low Output Enable Most.
When true, this signal enables the 8 most significant
bits to the disc interface bus during a microprocessor
write cycle.

LPOP

Low Power On Pulse.
This signal pulses low when power is cycled. When pulsed
low, it will initialize and reset the CPU and mini drive
control circuitry.

LPOPB

Low Power On Pulse Buffered.
When low, resets drive and interface control latches.

LPAO-3

Low Peripheral Address 0 through 3.
Identifies which one of the 16 peripheral devices will be
involved in a I/O operation.

LPRQ

Low Processor Request.
When true, this signal indicates that the CPU is
requesting a cycle from the the CPU interface/DMA state
machine.

LRAWRD

Low Raw Read.
Read data from data separator circuitry which has
a specific phase relationship to HRCLK.

LR7

Low Register 7.
When true, this signal indicates that the CPU is
communicating on the I/O bus through register 7.

LRDDATA

Low Read Data.
When true, indicates to the data separation circuitry that
a flux transition has occurred on the disc.

LRD

Low Read.
When true, this signal indicates that the
microprocessor is executing a read cycle from the
mini disc control circuitry through the data latches.

LRST

Low Reset.
Signal from microprocessor when true, resets the
mini disc controller circuits.

LRSTINT

Low Reset Interrupt.
Signal from the microprocessor. When true, it resets
the mini disc controller chip interrupts and DMA
interrupt request flip-flops.

LVCO

Low Voltage Control Oscillator.
Low true output of VCO oscillator.

LVCOE

Low Voltage Control Oscillator Enable.
Signal from mini disc controller chip which is made
true when the mini disc controller is inspecting data
coming from the disc. When true, enables data separator

8-74 AP

Service - Model 64110A
circuitry.
LWE

Low Write Enable.
Signal to mini disc controller chip which enables
write circuitry with in conjunction with LCS.

LWRT

Low Write.
When true, corresponding signal indicates that the CPU
is executing a write to the mini disc circuitry through
the data latches.

LWRTSM

Low Write State Machine.
Signal from microprocessor which indicates whether a
read or write operation should be executed during the
next CPU/DMA state machine interface cycle.

LWPRTO,l

Low Write Protect 0,1.
When true, corresponding signal indicates that the disc
installed in the disc drive is write protected. See Write
Protect. Also, used to set corresponding media change
flip-flop.

LRE

Low Read Enable.
Input to mini disc controller chip which enables read
circuitry in conjunction with LCS.

L2MHz

Low 2 MHz.
2 MHz signal derived from the 4 MHz oscillator circuit.

L2MHZC

Low 2 MHz Clock.
Used to clock data to the input of the state machine.

L500KHz

Low 500 KHz.
A 500 KHz signal derived from the 4MHz oscillator circuit.
This signal is used by the PLL to sync the VCO when not
inspecting data from the disc.

PCMD

Positive Command.
Control signal from the CPU which
to the mini disc through register
this signal latches data into the
and the DMA enable latch and sets
latch.

pulses low during a write
5. The positive edge of
interface control latch
the processor request

VCODATA

Voltage Controlled Oscillator Data.
This signal is compared with VCOOSC in the phase
comparator circuitry.

VCOOSC

Voltage Control Oscillator.
This signal is compared with VCODATA in phase
comparator circuit.

8-75 AP

Service - Model 64110A

HIGH
DECREASE
FVCO

LOW

Signal from phase detector when true decreases the
frequency of the voltage control oscillator.

INCREASE
FVCO

When in the true state, this signal changes the voltage
to the voltage control oscillator in such a way as to
increase its frequency.

INDEX

An index pulse occurs once every revolution of the disc
(200 msec. nominal) to indicate the beginning of a track.

MOTOR ON

A low logic level on this line causes the drive motor to
accelerate and stabilize in less than 250 msec. When this
line goes high, the drive motor decelerates to a stop.

SIDE ONE A high logic level selects the side "0" read/write head and
SELECT

a low logic level selects the side "I" read/write head.

STEP

Pulses low to step the head in or out. Direction is
Direction is controlled by HDIRC.

TRACKO

This line indicates to the controller that the read/write
head is positioned on track O. The track 0 signal remains
low until the head is moved from track O. This is
accomplished by anding the track 0 switch and phase 0 of the
stepper motor control.

WRITE

When the disc drive is
serial composite write
switching of the write
write electronics must

DATA

selected, this line provides the bit
data pulses that control the
current in the selected head. The
be enabled by the write gate line.

WRITE
GATE

When this line is low, the write electronics are enabled for
writing data (read electronics are disabled), This line
enables write current to flow in the selected read/write
head.

WRITE

This line goes low when the disc is write protected to
disable ~he write electronics.

PROTECT

8-76 AP

64110-90901

Printed in USA



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