Intel® 64 And IA 32 Architectures Software Developer’s Manual Volume 2C: Instruction Set Reference, V Z Developer Vol 2c
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- Chapter 5 Instruction Set Reference, V-Z
- 5.1 Ternary Bit Vector Logic Table
- 5.2 Instructions (V-Z)
- VALIGND/VALIGNQ—Align Doubleword/Quadword Vectors
- VBLENDMPD/VBLENDMPS—Blend Float64/Float32 Vectors Using an OpMask Control
- VBROADCAST—Load with Broadcast Floating-Point Data
- VPBROADCASTM—Broadcast Mask to Vector Register
- VCOMPRESSPD—Store Sparse Packed Double-Precision Floating-Point Values into Dense Memory
- VCOMPRESSPS—Store Sparse Packed Single-Precision Floating-Point Values into Dense Memory
- VCVTPD2QQ—Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers
- VCVTPD2UDQ—Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers
- VCVTPD2UQQ—Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers
- VCVTPH2PS—Convert 16-bit FP values to Single-Precision FP values
- VCVTPS2PH—Convert Single-Precision FP value to 16-bit FP value
- VCVTPS2UDQ—Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values
- VCVTPS2QQ—Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values
- VCVTPS2UQQ—Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values
- VCVTQQ2PD—Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values
- VCVTQQ2PS—Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values
- VCVTSD2USI—Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer
- VCVTSS2USI—Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer
- VCVTTPD2QQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Quadword Integers
- VCVTTPD2UDQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers
- VCVTTPD2UQQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers
- VCVTTPS2UDQ—Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values
- VCVTTPS2QQ—Convert with Truncation Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values
- VCVTTPS2UQQ—Convert with Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values
- VCVTTSD2USI—Convert with Truncation Scalar Double-Precision Floating-Point Value to Unsigned Integer
- VCVTTSS2USI—Convert with Truncation Scalar Single-Precision Floating-Point Value to Unsigned Integer
- VCVTUDQ2PD—Convert Packed Unsigned Doubleword Integers to Packed Double-Precision Floating-Point Values
- VCVTUDQ2PS—Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values
- VCVTUQQ2PD—Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values
- VCVTUQQ2PS—Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values
- VCVTUSI2SD—Convert Unsigned Integer to Scalar Double-Precision Floating-Point Value
- VCVTUSI2SS—Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value
- VDBPSADBW—Double Block Packed Sum-Absolute-Differences (SAD) on Unsigned Bytes
- VEXPANDPD—Load Sparse Packed Double-Precision Floating-Point Values from Dense Memory
- VEXPANDPS—Load Sparse Packed Single-Precision Floating-Point Values from Dense Memory
- VERR/VERW—Verify a Segment for Reading or Writing
- VEXP2PD—Approximation to the Exponential 2^x of Packed Double-Precision Floating-Point Values with Less Than 2^-23 Relative Error
- VEXP2PS—Approximation to the Exponential 2^x of Packed Single-Precision Floating-Point Values with Less Than 2^-23 Relative Error
- VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4—Extr act Packed Floating-Point Values
- VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4—Extract packed Integer Values
- VFIXUPIMMPD—Fix Up Special Packed Float64 Values
- VFIXUPIMMPS—Fix Up Special Packed Float32 Values
- VFIXUPIMMSD—Fix Up Special Scalar Float64 Value
- VFIXUPIMMSS—Fix Up Special Scalar Float32 Value
- VFMADD132PD/VFMADD213PD/VFMADD231PD—Fused Multiply-Add of Packed Double- Precision Floating-Point Values
- VFMADD132PS/VFMADD213PS/VFMADD231PS—Fused Multiply-Add of Packed Single- Precision Floating-Point Values
- VFMADD132SD/VFMADD213SD/VFMADD231SD—Fused Multiply-Add of Scalar Double- Precision Floating-Point Values
- VFMADD132SS/VFMADD213SS/VFMADD231SS—Fused Multiply-Add of Scalar Single-Precision Floating-Point Values
- VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD—Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values
- VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS—Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values
- VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD—Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values
- VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS—Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values
- VFMSUB132PD/VFMSUB213PD/VFMSUB231PD—Fused Multiply-Subtract of Packed Double- Precision Floating-Point Values
- VFMSUB132PS/VFMSUB213PS/VFMSUB231PS—Fused Multiply-Subtract of Packed Single- Precision Floating-Point Values
- VFMSUB132SD/VFMSUB213SD/VFMSUB231SD—Fused Multiply-Subtract of Scalar Double- Precision Floating-Point Values
- VFMSUB132SS/VFMSUB213SS/VFMSUB231SS—Fused Multiply-Subtract of Scalar Single- Precision Floating-Point Values
- VFNMADD132PD/VFNMADD213PD/VFNMADD231PD—Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values
- VFNMADD132PS/VFNMADD213PS/VFNMADD231PS—Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values
- VFNMADD132SD/VFNMADD213SD/VFNMADD231SD—Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values
- VFNMADD132SS/VFNMADD213SS/VFNMADD231SS—Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values
- VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD—Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values
- VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS—Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values
- VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD—Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values
- VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS—Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values
- VFPCLASSPD—Tests Types Of a Packed Float64 Values
- VFPCLASSPS—Tests Types Of a Packed Float32 Values
- VFPCLASSSD—Tests Types Of a Scalar Float64 Values
- VFPCLASSSS—Tests Types Of a Scalar Float32 Values
- VGATHERDPD/VGATHERQPD — Gather Packed DP FP Values Using Signed Dword/Qword Indices
- VGATHERDPS/VGATHERQPS — Gather Packed SP FP values Using Signed Dword/Qword Indices
- VGATHERDPS/VGATHERDPD—Gather Packed Single, Packed Double with Signed Dword
- VGATHERPF0DPS/VGATHERPF0QPS/VGATHERPF0DPD/VGATHERPF0QPD—Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint
- VGATHERPF1DPS/VGATHERPF1QPS/VGATHERPF1DPD/VGATHERPF1QPD—Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint
- VGATHERQPS/VGATHERQPD—Gather Packed Single, Packed Double with Signed Qword Indices
- VPGATHERDD/VPGATHERQD — Gather Packed Dword Values Using Signed Dword/Qword Indices
- VPGATHERDD/VPGATHERDQ—Gather Packed Dword, Packed Qword with Signed Dword Indices
- VPGATHERDQ/VPGATHERQQ — Gather Packed Qword Values Using Signed Dword/Qword Indices
- VPGATHERQD/VPGATHERQQ—Gather Packed Dword, Packed Qword with Signed Qword Indices
- VGETEXPPD—Convert Exponents of Packed DP FP Values to DP FP Values
- VGETEXPPS—Convert Exponents of Packed SP FP Values to SP FP Values
- VGETEXPSD—Convert Exponents of Scalar DP FP Values to DP FP Value
- VGETEXPSS—Convert Exponents of Scalar SP FP Values to SP FP Value
- VGETMANTPD—Extract Float64 Vector of Normalized Mantissas from Float64 Vector
- VGETMANTPS—Extract Float32 Vector of Normalized Mantissas from Float32 Vector
- VGETMANTSD—Extract Float64 of Normalized Mantissas from Float64 Scalar
- VGETMANTSS—Extract Float32 Vector of Normalized Mantissa from Float32 Vector
- VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4—Insert Packed Floating-Point Values
- VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4—Insert Packed Integer Values
- VMASKMOV—Conditional SIMD Packed Loads and Stores
- VPBLENDD — Blend Packed Dwords
- VPBLENDMB/VPBLENDMW—Blend Byte/Word Vectors Using an Opmask Control
- VPBLENDMD/VPBLENDMQ—Blend Int32/Int64 Vectors Using an OpMask Control
- VPBROADCASTB/W/D/Q—Load with Broadcast Integer Data from General Purpose Register
- VPBROADCAST—Load Integer and Broadcast
- VPCMPB/VPCMPUB—Compare Packed Byte Values Into Mask
- VPCMPD/VPCMPUD—Compare Packed Integer Values into Mask
- VPCMPQ/VPCMPUQ—Compare Packed Integer Values into Mask
- VPCMPW/VPCMPUW—Compare Packed Word Values Into Mask
- VPCOMPRESSD—Store Sparse Packed Doubleword Integer Values into Dense Memory/Register
- VPCOMPRESSQ—Store Sparse Packed Quadword Integer Values into Dense Memory/Register
- VPCONFLICTD/Q—Detect Conflicts Within a Vector of Packed Dword/Qword Values into Dense Memory/ Register
- VPERM2F128 — Permute Floating-Point Values
- VPERM2I128 — Permute Integer Values
- VPERMD/VPERMW—Permute Packed Doublewords/Words Elements
- VPERMI2W/D/Q/PS/PD—Full Permute From Two Tables Overwriting the Index
- VPERMILPD—Permute In-Lane of Pairs of Double-Precision Floating-Point Values
- VPERMILPS—Permute In-Lane of Quadruples of Single-Precision Floating-Point Values
- VPERMPD—Permute Double-Precision Floating-Point Elements
- VPERMPS—Permute Single-Precision Floating-Point Elements
- VPERMQ—Qwords Element Permutation
- VPEXPANDD—Load Sparse Packed Doubleword Integer Values from Dense Memory / Register
- VPEXPANDQ—Load Sparse Packed Quadword Integer Values from Dense Memory / Register
- VPLZCNTD/Q—Count the Number of Leading Zero Bits for Packed Dword, Packed Qword Values
- VPMASKMOV — Conditional SIMD Integer Packed Loads and Stores
- VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q—Convert a Mask Register to a Vector Register
- VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M—Convert a Vector Register to a Mask
- VPMOVQB/VPMOVSQB/VPMOVUSQB—Down Convert QWord to Byte
- VPMOVQW/VPMOVSQW/VPMOVUSQW—Down Convert QWord to Word
- VPMOVQD/VPMOVSQD/VPMOVUSQD—Down Convert QWord to DWord
- VPMOVDB/VPMOVSDB/VPMOVUSDB—Down Convert DWord to Byte
- VPMOVDW/VPMOVSDW/VPMOVUSDW—Down Convert DWord to Word
- VPMOVWB/VPMOVSWB/VPMOVUSWB—Down Convert Word to Byte
- PROLD/PROLVD/PROLQ/PROLVQ—Bit Rotate Left
- PRORD/PRORVD/PRORQ/PRORVQ—Bit Rotate Right
- VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ—Scatter Packed Dword, Packed Qword with Signed Dword, Signed Qword Indices
- VPSLLVW/VPSLLVD/VPSLLVQ—Variable Bit Shift Left Logical
- VPSRAVW/VPSRAVD/VPSRAVQ—Variable Bit Shift Right Arithmetic
- VPSRLVW/VPSRLVD/VPSRLVQ—Variable Bit Shift Right Logical
- VPTERNLOGD/VPTERNLOGQ—Bitwise Ternary Logic
- VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ—Logical AND and Set Mask
- VPTESTNMB/W/D/Q—Logical NAND and Set
- VRANGEPD—Range Restriction Calculation For Packed Pairs of Float64 Values
- VRANGEPS—Range Restriction Calculation For Packed Pairs of Float32 Values
- VRANGESD—Range Restriction Calculation From a pair of Scalar Float64 Values
- VRANGESS—Range Restriction Calculation From a Pair of Scalar Float32 Values
- VRCP14PD—Compute Approximate Reciprocals of Packed Float64 Values
- VRCP14SD—Compute Approximate Reciprocal of Scalar Float64 Value
- VRCP14PS—Compute Approximate Reciprocals of Packed Float32 Values
- VRCP14SS—Compute Approximate Reciprocal of Scalar Float32 Value
- VRCP28PD—Approximation to the Reciprocal of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error
- VRCP28SD—Approximation to the Reciprocal of Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error
- VRCP28PS—Approximation to the Reciprocal of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error
- VRCP28SS—Approximation to the Reciprocal of Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error
- VREDUCEPD—Perform Reduction Transformation on Packed Float64 Values
- VREDUCESD—Perform a Reduction Transformation on a Scalar Float64 Value
- VREDUCEPS—Perform Reduction Transformation on Packed Float32 Values
- VREDUCESS—Perform a Reduction Transformation on a Scalar Float32 Value
- VRNDSCALEPD—Round Packed Float64 Values To Include A Given Number Of Fraction Bits
- VRNDSCALESD—Round Scalar Float64 Value To Include A Given Number Of Fraction Bits
- VRNDSCALEPS—Round Packed Float32 Values To Include A Given Number Of Fraction Bits
- VRNDSCALESS—Round Scalar Float32 Value To Include A Given Number Of Fraction Bits
- VRSQRT14PD—Compute Approximate Reciprocals of Square Roots of Packed Float64 Values
- VRSQRT14SD—Compute Approximate Reciprocal of Square Root of Scalar Float64 Value
- VRSQRT14PS—Compute Approximate Reciprocals of Square Roots of Packed Float32 Values
- VRSQRT14SS—Compute Approximate Reciprocal of Square Root of Scalar Float32 Value
- VRSQRT28PD—Approximation to the Reciprocal Square Root of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error
- VRSQRT28SD—Approximation to the Reciprocal Square Root of Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error
- VRSQRT28PS—Approximation to the Reciprocal Square Root of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error
- VRSQRT28SS—Approximation to the Reciprocal Square Root of Scalar Single-Precision Floating- Point Value with Less Than 2^-28 Relative Error
- VSCALEFPD—Scale Packed Float64 Values With Float64 Values
- VSCALEFSD—Scale Scalar Float64 Values With Float64 Values
- VSCALEFPS—Scale Packed Float32 Values With Float32 Values
- VSCALEFSS—Scale Scalar Float32 Value With Float32 Value
- VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD—Scatter Packed Single, Packed Double with Signed Dword and Qword Indices
- VSCATTERPF0DPS/VSCATTERPF0QPS/VSCATTERPF0DPD/VSCATTERPF0QPD—Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint with Intent to Write
- VSCATTERPF1DPS/VSCATTERPF1QPS/VSCATTERPF1DPD/VSCATTERPF1QPD—Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint with Intent to Write
- VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2—Shuffle Packed Values at 128-bit Granularity
- VTESTPD/VTESTPS—Packed Bit Test
- VZEROALL—Zero All YMM Registers
- VZEROUPPER—Zero Upper Bits of YMM Registers
- WAIT/FWAIT—Wait
- WBINVD—Write Back and Invalidate Cache
- WRFSBASE/WRGSBASE—Write FS/GS Segment Base
- WRMSR—Write to Model Specific Register
- WRPKRU—Write Data to User Page Key Register
- XACQUIRE/XRELEASE — Hardware Lock Elision Prefix Hints
- XABORT — Transactional Abort
- XADD—Exchange and Add
- XBEGIN — Transactional Begin
- XCHG—Exchange Register/Memory with Register
- XEND — Transactional End
- XGETBV—Get Value of Extended Control Register
- XLAT/XLATB—Table Look-up Translation
- XOR—Logical Exclusive OR
- XORPD—Bitwise Logical XOR of Packed Double Precision Floating-Point Values
- XORPS—Bitwise Logical XOR of Packed Single Precision Floating-Point Values
- XRSTOR—Restore Processor Extended States
- XRSTORS—Restore Processor Extended States Supervisor
- XSAVE—Save Processor Extended States
- XSAVEC—Save Processor Extended States with Compaction
- XSAVEOPT—Save Processor Extended States Optimized
- XSAVES—Save Processor Extended States Supervisor
- XSETBV—Set Extended Control Register
- XTEST — Test If In Transactional Execution