Intel® 64 And IA 32 Architectures Software Developer’s Manual, Volume 4: Specific Registers Developer Vol 4 Manual
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Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 4: Model-Specific Registers NOTE: The Intel® 64 and IA-32 Architectures Software Developer's Manual consists of ten volumes: Basic Architecture, Order Number 253665; Instruction Set Reference A-L, Order Number 253666; Instruction Set Reference M-U, Order Number 253667; Instruction Set Reference V-Z, Order Number 326018; Instruction Set Reference, Order Number 334569; System Programming Guide, Part 1, Order Number 253668; System Programming Guide, Part 2, Order Number 253669; System Programming Guide, Part 3, Order Number 326019; System Programming Guide, Part 4, Order Number 332831; Model-Specific Registers, Order Number 335592. Refer to all ten volumes when evaluating your design needs. Order Number: 335592-070US May 2019 Intel technologies features and benefits depend on system configuration and may require enabled hardware, software, or service activation. Learn more at intel.com, or from the OEM or retailer. No computer system can be absolutely secure. Intel does not assume any liability for lost or stolen data or systems or any damages resulting from such losses. You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. This document contains information on products, services and/or processes in development. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1800-548-4725, or by visiting http://www.intel.com/design/literature.htm. Intel, the Intel logo, Intel Atom, Intel Core, Intel SpeedStep, MMX, Pentium, VTune, and Xeon are trademarks of Intel Corporation in the U.S. and/or other countries. *Other names and brands may be claimed as the property of others. Copyright © 1997-2019, Intel Corporation. All Rights Reserved. CONTENTS PAGE CHAPTER 1 ABOUT THIS MANUAL 1.1 1.2 1.3 1.3.1 1.3.2 1.3.3 1.3.4 1.3.5 1.3.6 1.3.7 1.4 INTEL® 64 AND IA-32 PROCESSORS COVERED IN THIS MANUAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OVERVIEW OF THE SYSTEM PROGRAMMING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NOTATIONAL CONVENTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit and Byte Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reserved Bits and Software Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hexadecimal and Binary Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Segmented Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Syntax for CPUID, CR, and MSR Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RELATED LITERATURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1-4 1-4 1-4 1-4 1-5 1-5 1-5 1-6 1-7 1-7 CHAPTER 2 MODEL-SPECIFIC REGISTERS (MSRS) 2.1 2.2 2.3 2.4 2.4.1 2.4.2 2.5 2.6 2.7 2.8 2.8.1 2.8.2 2.9 2.10 2.11 2.11.1 2.11.2 2.11.3 2.12 2.12.1 2.12.2 2.12.3 2.13 2.13.1 2.13.2 2.14 2.14.1 2.15 2.16 2.16.1 2.16.2 2.17 2.17.1 2.17.2 2.17.3 2.18 ARCHITECTURAL MSRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 MSRS IN THE INTEL® CORE™ 2 PROCESSOR FAMILY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46 MSRS IN THE 45 NM AND 32 NM INTEL® ATOM™ PROCESSOR FAMILY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-60 MSRS IN INTEL PROCESSORS BASED ON SILVERMONT MICROARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-71 MSRs with Model-Specific Behavior in the Silvermont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-84 MSRs In Intel Atom Processors Based on Airmont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-87 MSRS IN INTEL ATOM PROCESSORS BASED ON GOLDMONT MICROARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-90 MSRS IN INTEL ATOM PROCESSORS BASED ON GOLDMONT PLUS MICROARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-113 MSRS IN INTEL ATOM PROCESSORS BASED ON TREMONT MICROARCHITECTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-117 MSRS IN THE INTEL® MICROARCHITECTURE CODE NAME NEHALEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-119 Additional MSRs in the Intel® Xeon® Processor 5500 and 3400 Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-137 Additional MSRs in the Intel® Xeon® Processor 7500 Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-139 MSRS IN THE INTEL® XEON® PROCESSOR 5600 SERIES (BASED ON INTEL® MICROARCHITECTURE CODE NAME WESTMERE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-153 MSRS IN THE INTEL® XEON® PROCESSOR E7 FAMILY (BASED ON INTEL® MICROARCHITECTURE CODE NAME WESTMERE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-154 MSRS IN INTEL® PROCESSOR FAMILY BASED ON INTEL® MICROARCHITECTURE CODE NAME SANDY BRIDGE. . . . . . . 2-156 MSRs In 2nd Generation Intel® Core™ Processor Family (Based on Intel® Microarchitecture Code Name Sandy Bridge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-176 MSRs In Intel® Xeon® Processor E5 Family (Based on Intel® Microarchitecture Code Name Sandy Bridge) . . . . . . .2-180 Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-184 MSRS IN THE 3RD GENERATION INTEL® CORE™ PROCESSOR FAMILY (BASED ON INTEL® MICROARCHITECTURE CODE NAME IVY BRIDGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-188 MSRs In Intel® Xeon® Processor E5 v2 Product Family (Based on Ivy Bridge-E Microarchitecture) . . . . . . . . . . . . . . .2-191 Additional MSRs Supported by Intel® Xeon® Processor E7 v2 Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-199 Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 v2 and E7 v2 Families. . . . . . . . . . . . . . . . . . . . . . . . . .2-201 MSRS IN THE 4TH GENERATION INTEL® CORE™ PROCESSORS (BASED ON HASWELL MICROARCHITECTURE) . . . . . . . 2-205 MSRs in 4th Generation Intel® Core™ Processor Family (based on Haswell Microarchitecture) . . . . . . . . . . . . . . . . . . . .2-210 Additional Residency MSRs Supported in 4th Generation Intel® Core™ Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-222 MSRS IN INTEL® XEON® PROCESSOR E5 V3 AND E7 V3 PRODUCT FAMILY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-224 Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-234 MSRS IN INTEL® CORE™ M PROCESSORS AND 5TH GENERATION INTEL CORE PROCESSORS . . . . . . . . . . . . . . . . . . . . . . . 2-244 MSRS IN INTEL® XEON® PROCESSORS E5 V4 FAMILY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-248 Additional MSRs Supported in the Intel® Xeon® Processor D Product Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-259 Additional MSRs Supported in Intel® Xeon® Processors E5 v4 and E7 v4 Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-260 MSRS IN THE 6TH GENERATION, 7TH GENERATION AND 8TH GENERATION INTEL® CORE™ PROCESSORS, INTEL® XEON® PROCESSOR SCALABLE FAMILY, AND FUTURE INTEL® CORE™ PROCESSORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-264 MSRs Specific to 7th Generation and 8th Generation Intel® Core™ Processors based on Kaby Lake Microarchitecture and Coffee Lake Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-286 MSRs Specific to Future Intel® Core™ Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-288 MSRs Specific to Intel® Xeon® Processor Scalable Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-295 MSRS IN INTEL® XEON PHI™ PROCESSOR 3200/5200/7200 SERIES AND INTEL® XEON PHI™ PROCESSOR 7215/7285/7295 SERIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-307 Vol. 4 iii CONTENTS PAGE 2.19 2.19.1 2.20 2.21 2.22 2.23 2.24 iv Vol. 4 MSRS IN THE PENTIUM® 4 AND INTEL® XEON® PROCESSORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-324 MSRs Unique to Intel® Xeon® Processor MP with L3 Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-349 MSRS IN INTEL® CORE™ SOLO AND INTEL® CORE™ DUO PROCESSORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-351 MSRS IN THE PENTIUM M PROCESSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-360 MSRS IN THE P6 FAMILY PROCESSORS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-367 MSRS IN PENTIUM PROCESSORS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-376 MSR INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-377 CONTENTS PAGE FIGURES Figure 1-1. Figure 1-2. Bit and Byte Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Syntax for CPUID, CR, and MSR Data Presentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Vol. 4 v CONTENTS PAGE TABLES Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 2-6. Table 2-7. Table 2-8. Table 2-9. Table 2-10. Table 2-11. Table 2-12. Table 2-13. Table 2-14. Table 2-15. Table 2-16. Table 2-17. Table 2-18. Table 2-19. Table 2-20. Table 2-21. Table 2-22. Table 2-23. Table 2-24. Table 2-25. Table 2-26. Table 2-27. Table 2-28. Table 2-29. Table 2-30. Table 2-31. Table 2-32. Table 2-33. Table 2-34. Table 2-35. Table 2-36. Table 2-37. Table 2-38. Table 2-39. Table 2-40. Table 2-41. Table 2-42. Table 2-43. Table 2-44. Table 2-45. Table 2-46. Table 2-47. Table 2-48. Table 2-49. Table 2-50. Table 2-51. vi Vol. 4 CPUID Signature Values of DisplayFamily_DisplayModel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 IA-32 Architectural MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 MSRs in Processors Based on Intel® Core™ Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46 MSRs in 45 nm and 32 nm Intel® Atom™ Processor Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-60 MSRs Supported by Intel® Atom™ Processors with CPUID Signature 06_27H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70 MSRs Common to the Silvermont Microarchitecture and Newer Microarchitectures for Intel Atom Processors . . . 2-71 MSRs Common to the Silvermont and Airmont Microarchitectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-80 Specific MSRs Supported by Intel® Atom™ Processors with CPUID Signatures06_37H, 06_4AH, 06_5AH, 06_5DH2-84 Specific MSRs Supported by Intel® Atom™ Processor E3000 Series with CPUID Signature 06_37H. . . . . . . . . . . . . . . 2-86 Specific MSRs Supported by Intel® Atom™ Processor C2000 Series with CPUID Signature 06_4DH. . . . . . . . . . . . . . . 2-86 MSRs in Intel Atom Processors Based on the Airmont Microarchitecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-88 MSRs in Intel Atom Processors Based on the Goldmont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-90 MSRs in Intel Atom Processors Based on the Goldmont Plus Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-113 MSRs in Intel Atom Processors Based on the Tremont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-118 MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-119 Additional MSRs in Intel® Xeon® Processor 5500 and 3400 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-137 Additional MSRs in Intel® Xeon® Processor 7500 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-139 Additional MSRs Supported by Intel Processors (Based on Intel® Microarchitecture Code Name Westmere). . . . . .2-154 Additional MSRs Supported by Intel® Xeon® Processor E7 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-155 MSRs Supported by Intel® Processors based on Intel® microarchitecture code name Sandy Bridge . . . . . . . . . . . . . .2-156 MSRs Supported by 2nd Generation Intel® Core™ Processors (Intel® microarchitecture code name Sandy Bridge) 2-177 Uncore PMU MSRs Supported by 2nd Generation Intel® Core™ Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-178 Selected MSRs Supported by Intel® Xeon® Processors E5 Family (based on Sandy Bridge microarchitecture) . . . .2-180 Uncore PMU MSRs in Intel® Xeon® Processor E5 Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-184 Additional MSRs Supported by 3rd Generation Intel® Core™ Processors (based on Intel® microarchitecture code name Ivy Bridge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-188 MSRs Supported by Intel® Xeon® Processors E5 v2 Product Family (based on Ivy Bridge-E microarchitecture) . . .2-191 Additional MSRs Supported by Intel® Xeon® Processor E7 v2 Family with DisplayFamily_DisplayModel Signature 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-199 Uncore PMU MSRs in Intel® Xeon® Processor E5 v2 and E7 v2 Families. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-202 Additional MSRs Supported by Processors based on the Haswell or Haswell-E microarchitectures . . . . . . . . . . . . . .2-205 MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture). . . . . . . . . . . . . . . . . . . . . . .2-210 Additional Residency MSRs Supported by 4th Generation Intel® Core™ Processors with DisplayFamily_DisplayModel Signature 06_45H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-223 Additional MSRs Supported by Intel® Xeon® Processor E5 v3 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-224 Uncore PMU MSRs in Intel® Xeon® Processor E5 v3 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-234 Additional MSRs Common to Processors Based the Broadwell Microarchitectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-244 Additional MSRs Supported by Intel® Core™ M Processors and 5th Generation Intel® Core™ Processors . . . . . . . . . .2-246 Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family Based on the Broadwell Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-248 Additional MSRs Supported by Intel® Xeon® Processor D with DisplayFamily_DisplayModel 06_56H . . . . . . . . . . . .2-259 Additional MSRs Supported by Intel® Xeon® Processors with DisplayFamily_DisplayModel 06_4FH . . . . . . . . . . . . .2-261 Additional MSRs Supported by 6th Generation Intel® Core™ Processors and the Intel® Xeon® Processor Scalable Family Based on Skylake Microarchitecture, 7th Generation Intel® Core™ Processors Based on Kaby Lake Microarchitecture, 8th Generation Intel® Core™ Processors Based on Coffee Lake Microarchitecture, and Future Intel® Core™ Processors Based on Cannon Lake Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-264 Uncore PMU MSRs Supported by 6th Generation, 7th Generation, and 8th Generation Intel® Core™ Processors, and Future Intel® Core™ Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-284 Additional MSRs Supported by 7th Generation and 8th Generation Intel® Core™ Processors Based on Kaby Lake Microarchitecture and Coffee Lake Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-286 Additional MSRs Supported by Future Intel® Core™ Processors Based on Cannon Lake Microarchitecture. . . . . . . .2-288 Uncore PMU MSRs Supported by Intel® Core™ Processors Based on Cannon Lake Microarchitecture. . . . . . . . . . . . .2-292 MSRs Supported by Future Intel® Core™ Processors Based on Ice Lake Microarchitecture . . . . . . . . . . . . . . . . . . . . . .2-294 MSRs Supported by Intel® Xeon® Processor Scalable Family with DisplayFamily_DisplayModel 06_55H . . . . . . . . .2-295 Selected MSRs Supported by Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signatures 06_57H and 06_85H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-307 Additional MSRs Supported by Intel® Xeon Phi™ Processor 7215, 7285, 7295 Series with DisplayFamily_DisplayModel Signature 06_85H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-323 MSRs in the Pentium® 4 and Intel® Xeon® Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-324 MSRs Unique to 64-bit Intel® Xeon® Processor MP with Up to an 8 MB L3 Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-350 MSRs Unique to Intel® Xeon® Processor 7100 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-350 MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV . . . . . . . . . . . . . . .2-351 CONTENTS PAGE Table 2-52. Table 2-53. Table 2-54. MSRs in Pentium M Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-360 MSRs in the P6 Family Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-367 MSRs in the Pentium Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-377 Vol. 4 vii CONTENTS PAGE viii Vol. 4 CHAPTER 1 ABOUT THIS MANUAL The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 4: Model-Specific Registers (order number 335592) is part of a set that describes the architecture and programming environment of Intel® 64 and IA32 architecture processors. Other volumes in this set are: • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture (order number 253665). • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C & 2D: Instruction Set Reference (order numbers 253666, 253667, 326018 and 334569). • The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 3A, 3B, 3C & 3D: System Programming Guide (order numbers 253668, 253669, 326019 and 332831). The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, describes the basic architecture and programming environment of Intel 64 and IA-32 processors. The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C & 2D, describe the instruction set of the processor and the opcode structure. These volumes apply to application programmers and to programmers who write operating systems or executives. The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 3A, 3B, 3C & 3D, describe the operating-system support environment of Intel 64 and IA-32 processors. These volumes target operatingsystem and BIOS designers. In addition, Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B, and Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C address the programming environment for classes of software that host operating systems. The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 4, describes the model-specific registers of Intel 64 and IA-32 processors. 1.1 INTEL® 64 AND IA-32 PROCESSORS COVERED IN THIS MANUAL This manual set includes information pertaining primarily to the most recent Intel 64 and IA-32 processors, which include: • • • • • • • • • • • • • • • • • • • Pentium® processors P6 family processors Pentium® 4 processors Pentium® M processors Intel® Xeon® processors Pentium® D processors Pentium® processor Extreme Editions 64-bit Intel® Xeon® processors Intel® Core™ Duo processor Intel® Core™ Solo processor Dual-Core Intel® Xeon® processor LV Intel® Core™2 Duo processor Intel® Core™2 Quad processor Q6000 series Intel® Xeon® processor 3000, 3200 series Intel® Xeon® processor 5000 series Intel® Xeon® processor 5100, 5300 series Intel® Core™2 Extreme processor X7000 and X6800 series Intel® Core™2 Extreme QX6000 series Intel® Xeon® processor 7100 series Vol. 4 1-1 ABOUT THIS MANUAL • • • • • • • • Intel® Pentium® Dual-Core processor • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • Intel® Core™ i7 processor Intel® Xeon® processor 7200, 7300 series Intel® Core™2 Extreme QX9000 series Intel® Xeon® processor 5200, 5400, 7400 series Intel® Core™2 Extreme processor QX9000 and X9000 series Intel® Core™2 Quad processor Q9000 series Intel® Core™2 Duo processor E8000, T9000 series Intel® Atom™ processors 200, 300, D400, D500, D2000, N200, N400, N2000, E2000, Z500, Z600, Z2000, C1000 series are built from 45 nm and 32 nm processes. Intel® Core™ i5 processor Intel® Xeon® processor E7-8800/4800/2800 product families Intel® Core™ i7-3930K processor 2nd generation Intel® Core™ i7-2xxx, Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx processor series Intel® Xeon® processor E3-1200 product family Intel® Xeon® processor E5-2400/1400 product family Intel® Xeon® processor E5-4600/2600/1600 product family 3rd generation Intel® Core™ processors Intel® Xeon® processor E3-1200 v2 product family Intel® Xeon® processor E5-2400/1400 v2 product families Intel® Xeon® processor E5-4600/2600/1600 v2 product families Intel® Xeon® processor E7-8800/4800/2800 v2 product families 4th generation Intel® Core™ processors The Intel® Core™ M processor family Intel® Core™ i7-59xx Processor Extreme Edition Intel® Core™ i7-49xx Processor Extreme Edition Intel® Xeon® processor E3-1200 v3 product family Intel® Xeon® processor E5-2600/1600 v3 product families 5th generation Intel® Core™ processors Intel® Xeon® processor D-1500 product family Intel® Xeon® processor E5 v4 family Intel® Atom™ processor X7-Z8000 and X5-Z8000 series Intel® Atom™ processor Z3400 series Intel® Atom™ processor Z3500 series 6th generation Intel® Core™ processors Intel® Xeon® processor E3-1500m v5 product family 7th generation Intel® Core™ processors Intel® Xeon Phi™ Processor 3200, 5200, 7200 Series Intel® Xeon® Processor Scalable Family 8th generation Intel® Core™ processors Intel® Xeon Phi™ Processor 7215, 7285, 7295 Series Intel® Xeon® E processors 9th generation Intel® Core™ processors 1-2 Vol. 4 ABOUT THIS MANUAL P6 family processors are IA-32 processors based on the P6 family microarchitecture. This includes the Pentium® Pro, Pentium® II, Pentium® III, and Pentium® III Xeon® processors. The Pentium® 4, Pentium® D, and Pentium® processor Extreme Editions are based on the Intel NetBurst® microarchitecture. Most early Intel® Xeon® processors are based on the Intel NetBurst® microarchitecture. Intel Xeon processor 5000, 7100 series are based on the Intel NetBurst® microarchitecture. The Intel® Core™ Duo, Intel® Core™ Solo and dual-core Intel® Xeon® processor LV are based on an improved Pentium® M processor microarchitecture. The Intel® Xeon® processor 3000, 3200, 5100, 5300, 7200, and 7300 series, Intel® Pentium® dual-core, Intel® Core™2 Duo, Intel® Core™2 Quad, and Intel® Core™2 Extreme processors are based on Intel® Core™ microarchitecture. The Intel® Xeon® processor 5200, 5400, 7400 series, Intel® Core™2 Quad processor Q9000 series, and Intel® Core™2 Extreme processors QX9000, X9000 series, Intel® Core™2 processor E8000 series are based on Enhanced Intel® Core™ microarchitecture. The Intel® Atom™ processors 200, 300, D400, D500, D2000, N200, N400, N2000, E2000, Z500, Z600, Z2000, C1000 series are based on the Intel® Atom™ microarchitecture and supports Intel 64 architecture. P6 family, Pentium® M, Intel® Core™ Solo, Intel® Core™ Duo processors, dual-core Intel® Xeon® processor LV, and early generations of Pentium 4 and Intel Xeon processors support IA-32 architecture. The Intel® AtomTM processor Z5xx series support IA-32 architecture. The Intel® Xeon® processor 3000, 3200, 5000, 5100, 5200, 5300, 5400, 7100, 7200, 7300, 7400 series, Intel® Core™2 Duo, Intel® Core™2 Extreme, Intel® Core™2 Quad processors, Pentium® D processors, Pentium® DualCore processor, newer generations of Pentium 4 and Intel Xeon processor family support Intel® 64 architecture. The Intel® Core™ i7 processor and Intel® Xeon® processor 3400, 5500, 7500 series are based on 45 nm Nehalem microarchitecture. Westmere microarchitecture is a 32 nm version of the Nehalem microarchitecture. Intel® Xeon® processor 5600 series, Intel Xeon processor E7 and various Intel Core i7, i5, i3 processors are based on the Westmere microarchitecture. These processors support Intel 64 architecture. The Intel® Xeon® processor E5 family, Intel® Xeon® processor E3-1200 family, Intel® Xeon® processor E78800/4800/2800 product families, Intel® Core™ i7-3930K processor, and 2nd generation Intel® Core™ i7-2xxx, Intel® CoreTM i5-2xxx, Intel® Core™ i3-2xxx processor series are based on the Sandy Bridge microarchitecture and support Intel 64 architecture. The Intel® Xeon® processor E7-8800/4800/2800 v2 product families, Intel® Xeon® processor E3-1200 v2 product family and 3rd generation Intel® Core™ processors are based on the Ivy Bridge microarchitecture and support Intel 64 architecture. The Intel® Xeon® processor E5-4600/2600/1600 v2 product families, Intel® Xeon® processor E5-2400/1400 v2 product families and Intel® Core™ i7-49xx Processor Extreme Edition are based on the Ivy Bridge-E microarchitecture and support Intel 64 architecture. The Intel® Xeon® processor E3-1200 v3 product family and 4th Generation Intel® Core™ processors are based on the Haswell microarchitecture and support Intel 64 architecture. The Intel® Xeon® processor E5-2600/1600 v3 product families and the Intel® Core™ i7-59xx Processor Extreme Edition are based on the Haswell-E microarchitecture and support Intel 64 architecture. The Intel® Atom™ processor Z8000 series is based on the Airmont microarchitecture. The Intel® Atom™ processor Z3400 series and the Intel® Atom™ processor Z3500 series are based on the Silvermont microarchitecture. The Intel® Core™ M processor family, 5th generation Intel® Core™ processors, Intel® Xeon® processor D-1500 product family and the Intel® Xeon® processor E5 v4 family are based on the Broadwell microarchitecture and support Intel 64 architecture. The Intel® Xeon® Processor Scalable Family, Intel® Xeon® processor E3-1500m v5 product family and 6th generation Intel® Core™ processors are based on the Skylake microarchitecture and support Intel 64 architecture. The 7th generation Intel® Core™ processors are based on the Kaby Lake microarchitecture and support Intel 64 architecture. Vol. 4 1-3 ABOUT THIS MANUAL The Intel® Atom™ processor C series, the Intel® Atom™ processor X series, the Intel® Pentium® processor J series, the Intel® Celeron® processor J series, and the Intel® Celeron® processor N series are based on the Goldmont microarchitecture. The Intel® Xeon Phi™ Processor 3200, 5200, 7200 Series is based on the Knights Landing microarchitecture and supports Intel 64 architecture. The Intel® Pentium® Silver processor series, the Intel® Celeron® processor J series, and the Intel® Celeron® processor N series are based on the Goldmont Plus microarchitecture. The 8th generation Intel® Core™ processors, 9th generation Intel® Core™ processors, and Intel® Xeon® E processors are based on the Coffee Lake microarchitecture and support Intel 64 architecture. The Intel® Xeon Phi™ Processor 7215, 7285, 7295 Series is based on the Knights Mill microarchitecture and supports Intel 64 architecture. IA-32 architecture is the instruction set architecture and programming environment for Intel's 32-bit microprocessors. Intel® 64 architecture is the instruction set architecture and programming environment which is the superset of Intel’s 32-bit and 64-bit architectures. It is compatible with the IA-32 architecture. 1.2 OVERVIEW OF THE SYSTEM PROGRAMMING GUIDE A description of this manual’s content follows: Chapter 1 — About This Manual. Gives an overview of all eight volumes of the Intel® 64 and IA-32 Architectures Software Developer’s Manual. It also describes the notational conventions in these manuals and lists related Intel manuals and documentation of interest to programmers and hardware designers. Chapter 2 — Model-Specific Registers (MSRs). Lists the MSRs available in the Pentium processors, the P6 family processors, the Pentium 4, Intel Xeon, Intel Core Solo, Intel Core Duo processors, Intel Core 2 processor family, and Intel Atom processors, and describes their functions. 1.3 NOTATIONAL CONVENTIONS This manual uses specific notation for data-structure formats, for symbolic representation of instructions, and for hexadecimal and binary numbers. A review of this notation makes the manual easier to read. 1.3.1 Bit and Byte Order In illustrations of data structures in memory, smaller addresses appear toward the bottom of the figure; addresses increase toward the top. Bit positions are numbered from right to left. The numerical value of a set bit is equal to two raised to the power of the bit position. Intel 64 and IA-32 processors are “little endian” machines; this means the bytes of a word are numbered starting from the least significant byte. Figure 1-1 illustrates these conventions. 1.3.2 Reserved Bits and Software Compatibility In many register and memory layout descriptions, certain bits are marked as reserved. When bits are marked as reserved, it is essential for compatibility with future processors that software treat these bits as having a future, though unknown, effect. The behavior of reserved bits should be regarded as not only undefined, but unpredictable. Software should follow these guidelines in dealing with reserved bits: • Do not depend on the states of any reserved bits when testing the values of registers which contain such bits. Mask out the reserved bits before testing. • • • Do not depend on the states of any reserved bits when storing to memory or to a register. Do not depend on the ability to retain information written into any reserved bits. When loading a register, always load the reserved bits with the values indicated in the documentation, if any, or reload them with values previously read from the same register. 1-4 Vol. 4 ABOUT THIS MANUAL NOTE Avoid any software dependence upon the state of reserved bits in Intel 64 and IA-32 registers. Depending upon the values of reserved register bits will make software dependent upon the unspecified manner in which the processor handles these bits. Programs that depend upon reserved values risk incompatibility with future processors. Highest 31 Address Data Structure 8 7 24 23 16 15 Byte 3 Byte 2 Byte 1 Bit offset 0 Byte 0 28 24 20 16 12 8 4 0 Lowest Address Byte Offset Figure 1-1. Bit and Byte Order 1.3.3 Instruction Operands When instructions are represented symbolically, a subset of assembly language is used. In this subset, an instruction has the following format: label: mnemonic argument1, argument2, argument3 where: • • • A label is an identifier which is followed by a colon. A mnemonic is a reserved name for a class of instruction opcodes which have the same function. The operands argument1, argument2, and argument3 are optional. There may be from zero to three operands, depending on the opcode. When present, they take the form of either literals or identifiers for data items. Operand identifiers are either reserved names of registers or are assumed to be assigned to data items declared in another part of the program (which may not be shown in the example). When two operands are present in an arithmetic or logical instruction, the right operand is the source and the left operand is the destination. For example: LOADREG: MOV EAX, SUBTOTAL In this example LOADREG is a label, MOV is the mnemonic identifier of an opcode, EAX is the destination operand, and SUBTOTAL is the source operand. Some assembly languages put the source and destination in reverse order. 1.3.4 Hexadecimal and Binary Numbers Base 16 (hexadecimal) numbers are represented by a string of hexadecimal digits followed by the character H (for example, F82EH). A hexadecimal digit is a character from the following set: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F. Base 2 (binary) numbers are represented by a string of 1s and 0s, sometimes followed by the character B (for example, 1010B). The “B” designation is only used in situations where confusion as to the type of number might arise. Vol. 4 1-5 ABOUT THIS MANUAL 1.3.5 Segmented Addressing The processor uses byte addressing. This means memory is organized and accessed as a sequence of bytes. Whether one or more bytes are being accessed, a byte address is used to locate the byte or bytes memory. The range of memory that can be addressed is called an address space. The processor also supports segmented addressing. This is a form of addressing where a program may have many independent address spaces, called segments. For example, a program can keep its code (instructions) and stack in separate segments. Code addresses would always refer to the code space, and stack addresses would always refer to the stack space. The following notation is used to specify a byte address within a segment: Segment-register:Byte-address For example, the following segment address identifies the byte at address FF79H in the segment pointed by the DS register: DS:FF79H The following segment address identifies an instruction address in the code segment. The CS register points to the code segment and the EIP register contains the address of the instruction. CS:EIP 1.3.6 Syntax for CPUID, CR, and MSR Values Obtain feature flags, status, and system information by using the CPUID instruction, by checking control register bits, and by reading model-specific registers. We are moving toward a single syntax to represent this type of information. See Figure 1-2. 1-6 Vol. 4 ABOUT THIS MANUAL CPUID Input and Output CPUID.01H:EDX.SSE[bit 25] = 1 Input value for EAX register Output register and feature flag or field name with bit position(s) Value (or range) of output Control Register Values CR4.OSFXSR[bit 9] = 1 Example CR name Feature flag or field name with bit position(s) Value (or range) of output Model-Specific Register Values IA32_MISC_ENABLE.ENABLEFOPCODE[bit 2] = 1 Example MSR name Feature flag or field name with bit position(s) Value (or range) of output Figure 1-2. Syntax for CPUID, CR, and MSR Data Presentation 1.3.7 Exceptions An exception is an event that typically occurs when an instruction causes an error. For example, an attempt to divide by zero generates an exception. However, some exceptions, such as breakpoints, occur under other conditions. Some types of exceptions may provide error codes. An error code reports additional information about the error. An example of the notation used to show an exception and error code is shown below: #PF(fault code) This example refers to a page-fault exception under conditions where an error code naming a type of fault is reported. Under some conditions, exceptions which produce error codes may not be able to report an accurate code. In this case, the error code is zero, as shown below for a general-protection exception: #GP(0) 1.4 RELATED LITERATURE Literature related to Intel 64 and IA-32 processors is listed and viewable on-line at: https://software.intel.com/en-us/articles/intel-sdm Vol. 4 1-7 ABOUT THIS MANUAL See also: • The latest security information on Intel® products: https://www.intel.com/content/www/us/en/security-center/default.html • Software developer resources, guidance and insights for security advisories: https://software.intel.com/security-software-guidance/ • • • The data sheet for a particular Intel 64 or IA-32 processor • Intel® Fortran Compiler documentation and online help: http://software.intel.com/en-us/articles/intel-compilers/ • Intel® Software Development Tools: https://software.intel.com/en-us/intel-sdp-home • Intel® 64 and IA-32 Architectures Software Developer’s Manual (in one, four or ten volumes): https://software.intel.com/en-us/articles/intel-sdm • Intel® 64 and IA-32 Architectures Optimization Reference Manual: https://software.intel.com/en-us/articles/intel-sdm#optimization • Intel 64 Architecture x2APIC Specification: The specification update for a particular Intel 64 or IA-32 processor Intel® C++ Compiler documentation and online help: http://software.intel.com/en-us/articles/intel-compilers/ http://www.intel.com/content/www/us/en/architecture-and-technology/64-architecture-x2apic-specification.html • Intel® Trusted Execution Technology Measured Launched Environment Programming Guide: http://www.intel.com/content/www/us/en/software-developers/intel-txt-software-development-guide.html • Developing Multi-threaded Applications: A Platform Consistent Approach: https://software.intel.com/sites/default/files/article/147714/51534-developing-multithreaded-applications.pdf • Using Spin-Loops on Intel® Pentium® 4 Processor and Intel® Xeon® Processor: https://software.intel.com/sites/default/files/22/30/25602 • Performance Monitoring Unit Sharing Guide http://software.intel.com/file/30388 Literature related to selected features in future Intel processors are available at: • Intel® Architecture Instruction Set Extensions Programming Reference https://software.intel.com/en-us/isa-extensions • Intel® Software Guard Extensions (Intel® SGX) Programming Reference https://software.intel.com/en-us/isa-extensions/intel-sgx More relevant links are: • Intel® Developer Zone: https://software.intel.com/en-us • Developer centers: http://www.intel.com/content/www/us/en/hardware-developers/developer-centers.html • Processor support general link: http://www.intel.com/support/processors/ • Intel® Hyper-Threading Technology (Intel® HT Technology): http://www.intel.com/technology/platform-technology/hyper-threading/index.htm 1-8 Vol. 4 CHAPTER 2 MODEL-SPECIFIC REGISTERS (MSRS) This chapter lists MSRs across Intel processor families. All MSRs listed can be read with the RDMSR and written with the WRMSR instructions. The scope of an MSR defines the set of processors that access the same MSR with RDMSR and WRMSR. Thread-scope MSRs are unique to every logical processor. Core-scope MSRs are shared by the threads in the same core; similarly for module-scope, die-scope, and package-scope. When a processor package contains a single die, die-scope and package-scope are synonymous. When a package contains multiple die, they are distinct. NOTE For information on hierarchical level types supported, refer to the CPUID Leaf 1FH definition for the actual level type numbers: “V2 Extended Topology Enumeration Leaf” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A. Also see Section 8.9.1, “Hierarchical Mapping of Shared Resources” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A. Register addresses are given in both hexadecimal and decimal. The register name is the mnemonic register name and the bit description describes individual bits in registers. Model specific registers and its bit-fields may be supported for a finite range of processor families/models. To distinguish between different processor family and/or models, software must use CPUID.01H leaf function to query the combination of DisplayFamily and DisplayModel to determine model-specific availability of MSRs (see CPUID instruction in Chapter 3, “Instruction Set Reference, A-L” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A). Table 2-1 lists the signature values of DisplayFamily and DisplayModel for various processor families or processor number series. Table 2-1. CPUID Signature Values of DisplayFamily_DisplayModel DisplayFamily_DisplayModel Processor Families/Processor Number Series 06_85H Intel® Xeon Phi™ Processor 7215, 7285, 7295 Series based on Knights Mill microarchitecture 06_57H Intel® Xeon Phi™ Processor 3200, 5200, 7200 Series based on Knights Landing microarchitecture 06_7DH, 06_7EH Future Intel® Core™ processors based on Ice Lake microarchitecture 06_66H Intel® Core™ processors based on Cannon Lake microarchitecture 06_8EH, 06_9EH 7th generation Intel® Core™ processors based on Kaby Lake microarchitecture, 8th and 9th generation Intel® Core™ processors based on Coffee Lake microarchitecture, Intel® Xeon® E processors based on Coffee Lake microarchitecture 06_6AH, 06_6CH Future Intel® Xeon® processors based on Ice Lake microarchitecture 06_55H Intel® Xeon® Processor Scalable Family based on Skylake microarchitecture, 2nd generation Intel® Xeon® Processor Scalable Family based on Cascade Lake product, and future Cooper Lake product 06_4EH, 06_5EH 6th generation Intel Core processors and Intel Xeon processor E3-1500m v5 product family and E31200 v5 product family based on Skylake microarchitecture 06_56H Intel Xeon processor D-1500 product family based on Broadwell microarchitecture 06_4FH Intel Xeon processor E5 v4 Family based on Broadwell microarchitecture, Intel Xeon processor E7 v4 Family, Intel Core i7-69xx Processor Extreme Edition 06_47H 5th generation Intel Core processors, Intel Xeon processor E3-1200 v4 product family based on Broadwell microarchitecture 06_3DH Intel Core M-5xxx Processor, 5th generation Intel Core processors based on Broadwell microarchitecture Vol. 4 2-1 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-1. CPUID Signature (Contd.)Values of DisplayFamily_DisplayModel (Contd.) DisplayFamily_DisplayModel Processor Families/Processor Number Series 06_3FH Intel Xeon processor E5-4600/2600/1600 v3 product families, Intel Xeon processor E7 v3 product families based on Haswell-E microarchitecture, Intel Core i7-59xx Processor Extreme Edition 06_3CH, 06_45H, 06_46H 4th Generation Intel Core processor and Intel Xeon processor E3-1200 v3 product family based on Haswell microarchitecture 06_3EH Intel Xeon processor E7-8800/4800/2800 v2 product families based on Ivy Bridge-E microarchitecture 06_3EH Intel Xeon processor E5-2600/1600 v2 product families and Intel Xeon processor E5-2400 v2 product family based on Ivy Bridge-E microarchitecture, Intel Core i7-49xx Processor Extreme Edition 06_3AH 3rd Generation Intel Core Processor and Intel Xeon processor E3-1200 v2 product family based on Ivy Bridge microarchitecture 06_2DH Intel Xeon processor E5 Family based on Intel microarchitecture code name Sandy Bridge, Intel Core i7-39xx Processor Extreme Edition 06_2FH Intel Xeon Processor E7 Family 06_2AH Intel Xeon processor E3-1200 product family; 2nd Generation Intel Core i7, i5, i3 Processors 2xxx Series 06_2EH Intel Xeon processor 7500, 6500 series 06_25H, 06_2CH Intel Xeon processors 3600, 5600 series, Intel Core i7, i5 and i3 Processors 06_1EH, 06_1FH Intel Core i7 and i5 Processors 06_1AH Intel Core i7 Processor, Intel Xeon processor 3400, 3500, 5500 series 06_1DH Intel Xeon processor MP 7400 series 06_17H Intel Xeon processor 3100, 3300, 5200, 5400 series, Intel Core 2 Quad processors 8000, 9000 series 06_0FH Intel Xeon processor 3000, 3200, 5100, 5300, 7300 series, Intel Core 2 Quad processor 6000 series, Intel Core 2 Extreme 6000 series, Intel Core 2 Duo 4000, 5000, 6000, 7000 series processors, Intel Pentium dual-core processors 06_0EH Intel Core Duo, Intel Core Solo processors 06_0DH Intel Pentium M processor 06_86H Intel® Atom™ processors based on Tremont Microarchitecture 06_7AH Intel Atom processors based on Goldmont Plus Microarchitecture 06_5FH Intel Atom processors based on Goldmont Microarchitecture (code name Denverton) 06_5CH Intel Atom processors based on Goldmont Microarchitecture 06_4CH Intel Atom processor X7-Z8000 and X5-Z8000 series based on Airmont Microarchitecture 06_5DH Intel Atom processor X3-C3000 based on Silvermont Microarchitecture 06_5AH Intel Atom processor Z3500 series 06_4AH Intel Atom processor Z3400 series 06_37H Intel Atom processor E3000 series, Z3600 series, Z3700 series 06_4DH Intel Atom processor C2000 series 06_36H Intel Atom processor S1000 Series 06_1CH, 06_26H, 06_27H, 06_35H, 06_36H Intel Atom processor family, Intel Atom processor D2000, N2000, E2000, Z2000, C1000 series 0F_06H Intel Xeon processor 7100, 5000 Series, Intel Xeon Processor MP, Intel Pentium 4, Pentium D processors 0F_03H, 0F_04H Intel Xeon processor, Intel Xeon processor MP, Intel Pentium 4, Pentium D processors 06_09H Intel Pentium M processor 2-2 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-1. CPUID Signature (Contd.)Values of DisplayFamily_DisplayModel (Contd.) DisplayFamily_DisplayModel Processor Families/Processor Number Series 0F_02H Intel Xeon Processor, Intel Xeon processor MP, Intel Pentium 4 processors 0F_0H, 0F_01H Intel Xeon Processor, Intel Xeon processor MP, Intel Pentium 4 processors 06_7H, 06_08H, 06_0AH, 06_0BH Intel Pentium III Xeon processor, Intel Pentium III processor 06_03H, 06_05H Intel Pentium II Xeon processor, Intel Pentium II processor 06_01H Intel Pentium Pro processor 05_01H, 05_02H, 05_04H Intel Pentium processor, Intel Pentium processor with MMX Technology The Intel® Quark™ SoC X1000 processor can be identified by the signature of DisplayFamily_DisplayModel = 05_09H and SteppingID = 0 2.1 ARCHITECTURAL MSRS Many MSRs have carried over from one generation of IA-32 processors to the next and to Intel 64 processors. A subset of MSRs and associated bit fields, which do not change on future processor generations, are now considered architectural MSRs. For historical reasons (beginning with the Pentium 4 processor), these “architectural MSRs” were given the prefix “IA32_”. Table 2-2 lists the architectural MSRs, their addresses, their current names, their names in previous IA-32 processors, and bit fields that are considered architectural. MSR addresses outside Table 2-2 and certain bit fields in an MSR address that may overlap with architectural MSR addresses are model-specific. Code that accesses a machine specified MSR and that is executed on a processor that does not support that MSR will generate an exception. Architectural MSR or individual bit fields in an architectural MSR may be introduced or transitioned at the granularity of certain processor family/model or the presence of certain CPUID feature flags. The right-most column of Table 2-2 provides information on the introduction of each architectural MSR or its individual fields. This information is expressed either as signature values of “DF_DM” (see Table 2-1) or via CPUID flags. Certain bit field position may be related to the maximum physical address width, the value of which is expressed as “MAXPHYADDR” in Table 2-2. “MAXPHYADDR” is reported by CPUID.8000_0008H leaf. MSR address range between 40000000H - 400000FFH is marked as a specially reserved range. All existing and future processors will not implement any features using any MSR in this range. Table 2-2. IA-32 Architectural MSRs Register Address Hex Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 0H 0 IA32_P5_MC_ADDR (P5_MC_ADDR) See Section 2.23, “MSRs in Pentium Processors.” Pentium Processor (05_01H) 1H 1 IA32_P5_MC_TYPE (P5_MC_TYPE) See Section 2.23, “MSRs in Pentium Processors.” DF_DM = 05_01H 6H 6 IA32_MONITOR_FILTER_SIZE See Section 8.10.5, “Monitor/Mwait Address Range Determination.” 0F_03H 10H 16 IA32_TIME_STAMP_COUNTER See Section 17.17, “Time-Stamp Counter.” 05_01H IA32_PLATFORM_ID (MSR_PLATFORM_ID ) Platform ID (RO) The operating system can use this MSR to determine “slot” information for the processor and the proper microcode update to load. 06_01H 49:0 Reserved (TSC) 17H 23 Vol. 4 2-3 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 52:50 Platform Id (RO) Contains information concerning the intended platform for the processor. 52 0 0 0 0 1 1 1 1 1BH 27 58 50 0 1 0 1 0 1 0 1 Processor Flag 0 Processor Flag 1 Processor Flag 2 Processor Flag 3 Processor Flag 4 Processor Flag 5 Processor Flag 6 Processor Flag 7 63:53 Reserved IA32_APIC_BASE This register holds the APIC base address, permitting the relocation of the APIC memory map. See Section 10.4.4, “Local APIC Status and Location” and Section 10.4.5, “Relocating the Local APIC Registers”. (APIC_BASE) 3AH 51 0 0 1 1 0 0 1 1 7:0 Reserved 8 BSP flag (R/W) 9 Reserved 10 Enable x2APIC mode. 11 APIC Global Enable (R/W) (MAXPHYADDR - 1):12 APIC Base (R/W) 63: MAXPHYADDR Reserved IA32_FEATURE_CONTROL Control Features in Intel 64 Processor (R/W) If any one enumeration condition for defined bit field holds. 0 Lock bit (R/WO): (1 = locked). When set, locks this MSR from being written; writes to this bit will result in GP(0). If any one enumeration condition for defined bit field position greater than bit 0 holds. Note: Once the Lock bit is set, the contents of this register cannot be modified. Therefore the lock bit must be set after configuring support for Intel Virtualization Technology and prior to transferring control to an option ROM or the OS. Hence, once the Lock bit is set, the entire IA32_FEATURE_CONTROL contents are preserved across RESET when PWRGOOD is not deasserted. 2-4 Vol. 4 06_01H 06_1AH MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Enable VMX inside SMX operation (R/WL): This bit enables a system executive to use VMX in conjunction with SMX to support Intel® Trusted Execution Technology. If CPUID.01H:ECX[5] = 1 && CPUID.01H:ECX[6] = 1 Decimal 1 BIOS must set this bit only when the CPUID function 1 returns VMX feature flag and SMX feature flag set (ECX bits 5 and 6 respectively). 2 Enable VMX outside SMX operation (R/WL): This bit enables VMX for a system executive that does not require SMX. If CPUID.01H:ECX[5] = 1 BIOS must set this bit only when the CPUID function 1 returns the VMX feature flag set (ECX bit 5). 3BH 59 7:3 Reserved 14:8 SENTER Local Function Enables (R/WL): When set, each bit in the field represents an enable control for a corresponding SENTER function. This field is supported only if CPUID.1:ECX.[bit 6] is set. If CPUID.01H:ECX[6] = 1 15 SENTER Global Enable (R/WL): This bit must be set to enable SENTER leaf functions. This bit is supported only if CPUID.1:ECX.[bit 6] is set. If CPUID.01H:ECX[6] = 1 16 Reserved 17 SGX Launch Control Enable (R/WL): This bit must be set to enable runtime reconfiguration of SGX Launch Control via the IA32_SGXLEPUBKEYHASHn MSR. If CPUID.(EAX=07H, ECX=0H): ECX[30] = 1 18 SGX Global Enable (R/WL): This bit must be set to enable SGX leaf functions. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1 19 Reserved 20 LMCE On (R/WL): When set, system software can program the MSRs associated with LMCE to configure delivery of some machine check exceptions to a single logical processor. 63:21 Reserved IA32_TSC_ADJUST Per Logical Processor TSC Adjust (R/Write to clear) 63:0 THREAD_ADJUST: If IA32_MCG_CAP[27] = 1 If CPUID.(EAX=07H, ECX=0H): EBX[1] = 1 Local offset value of the IA32_TSC for a logical processor. Reset value is zero. A write to IA32_TSC will modify the local offset in IA32_TSC_ADJUST and the content of IA32_TSC, but does not affect the internal invariant TSC hardware. Vol. 4 2-5 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex 48H Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 72 IA32_SPEC_CTRL Speculation Control (R/W) The MSR bits are defined as logical processor scope. On some core implementations, the bits may impact sibling logical processors on the same core. If any one of the enumeration conditions for defined bit field positions holds. This MSR has a value of 0 after reset and is unaffected by INIT# or SIPI#. 49H 73 0 Indirect Branch Restricted Speculation (IBRS). Restricts speculation of indirect branch. If CPUID.(EAX=07H, ECX=0):EDX[26]=1 1 Single Thread Indirect Branch Predictors (STIBP). Prevents indirect branch predictions on all logical processors on the core from being controlled by any sibling logical processor in the same core. If CPUID.(EAX=07H, ECX=0):EDX[27]=1 2 Speculative Store Bypass Disable (SSBD) delays speculative execution of a load until the addresses for all older stores are known. If CPUID.(EAX=07H, ECX=0):EDX[31]=1 63:3 Reserved IA32_PRED_CMD Prediction Command (WO) Gives software a way to issue commands that affect the state of predictors. 79H 121 0 Indirect Branch Prediction Barrier (IBPB). 63:1 Reserved IA32_BIOS_UPDT_TRIG (BIOS_UPDT_TRIG) BIOS Update Trigger (W) If any one of the enumeration conditions for defined bit field positions holds. If CPUID.(EAX=07H, ECX=0):EDX[26]=1 06_01H Executing a WRMSR instruction to this MSR causes a microcode update to be loaded into the processor. See Section 9.11.6, “Microcode Update Loader.” A processor may prevent writing to this MSR when loading guest states on VM entries or saving guest states on VM exits. 8BH 139 IA32_BIOS_SIGN_ID (BIOS_SIGN/BBL_CR_D3) BIOS Update Signature (RO) Returns the microcode update signature following the execution of CPUID.01H. A processor may prevent writing to this MSR when loading guest states on VM entries or saving guest states on VM exits. 31:0 2-6 Vol. 4 Reserved 06_01H MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 63:32 It is recommended that this field be preloaded with zero prior to executing CPUID. If the field remains zero following the execution of CPUID, this indicates that no microcode update is loaded. Any non-zero value is the microcode update signature. 8CH 140 IA32_SGXLEPUBKEYHASH0 IA32_SGXLEPUBKEYHASH[63:0] (R/W) Bits 63:0 of the SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset, the default value is the digest of Intel’s signing key. 8DH 141 IA32_SGXLEPUBKEYHASH1 IA32_SGXLEPUBKEYHASH[127:64] (R/W) Bits 127:64 of the SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset, the default value is the digest of Intel’s signing key. 8EH 142 IA32_SGXLEPUBKEYHASH2 IA32_SGXLEPUBKEYHASH[191:128] (R/W) Bits 191:128 of the SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset, the default value is the digest of Intel’s signing key. 8FH 143 IA32_SGXLEPUBKEYHASH3 IA32_SGXLEPUBKEYHASH[255:192] (R/W) Read permitted If CPUID.(EAX=12H,ECX=0H): EAX[0]=1 && CPUID.(EAX=07H, ECX=0H):ECX[30]=1. Write permitted if CPUID.(EAX=12H,ECX=0H): EAX[0]=1 && IA32_FEATURE_CONTROL[ 17] = 1 && IA32_FEATURE_CONTROL[ 0] = 1. Bits 255:192 of the SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset, the default value is the digest of Intel’s signing key. 9BH 155 IA32_SMM_MONITOR_CTL SMM Monitor Configuration (R/W) 0 Valid (R/W) 1 Reserved 2 Controls SMI unblocking by VMXOFF (see Section 34.14.4). 11:3 Reserved 31:12 MSEG Base (R/W) 63:32 Reserved If CPUID.01H: ECX[5]=1 || CPUID.01H: ECX[6] = 1 If IA32_VMX_MISC[28] 9EH 158 IA32_SMBASE Base address of the logical processor’s SMRAM image (RO, SMM only). If IA32_VMX_MISC[15] C1H 193 IA32_PMC0 General Performance Counter 0 (R/W) If CPUID.0AH: EAX[15:8] > 0 General Performance Counter 1 (R/W) If CPUID.0AH: EAX[15:8] > 1 General Performance Counter 2 (R/W) If CPUID.0AH: EAX[15:8] > 2 (PERFCTR0) C2H 194 IA32_PMC1 (PERFCTR1) C3H 195 IA32_PMC2 Vol. 4 2-7 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal C4H 196 IA32_PMC3 General Performance Counter 3 (R/W) If CPUID.0AH: EAX[15:8] > 3 C5H 197 IA32_PMC4 General Performance Counter 4 (R/W) If CPUID.0AH: EAX[15:8] > 4 C6H 198 IA32_PMC5 General Performance Counter 5 (R/W) If CPUID.0AH: EAX[15:8] > 5 C7H 199 IA32_PMC6 General Performance Counter 6 (R/W) If CPUID.0AH: EAX[15:8] > 6 C8H 200 IA32_PMC7 General Performance Counter 7 (R/W) If CPUID.0AH: EAX[15:8] > 7 CFH 207 IA32_CORE_CAPABILITY IA32 Core Capability Register 06_86H 4:0 Reserved. 5 #AC(0) exception for split locked accesses supported. 31:6 Reserved. IA32_UMWAIT_CONTROL UMWAIT Control (R/W) 0 C0.2 is not allowed by the OS. Value of “1” means all C0.2 requests revert to C0.1. 1 Reserved 31:2 Determines the maximum time in TSCquanta that the processor can reside in either C0.1 or C0.2. A zero value indicates no maximum time. The maximum time value is a 32-bit value where the upper 30 bits come from this field and the lower two bits are zero. IA32_MPERF TSC Frequency Clock Counter (R/Write to clear) E1H E7H 225 231 63:0 If CPUID.06H: ECX[0] = 1 C0_MCNT: C0 TSC Frequency Clock Count Increments at fixed interval (relative to TSC freq.) when the logical processor is in C0. Cleared upon overflow / wrap-around of IA32_APERF. E8H 232 IA32_APERF Actual Performance Clock Counter (R/Write to clear) 63:0 C0_ACNT: C0 Actual Frequency Clock Count If CPUID.06H: ECX[0] = 1 Accumulates core clock counts at the coordinated clock frequency, when the logical processor is in C0. Cleared upon overflow / wrap-around of IA32_MPERF. FEH 2-8 Vol. 4 254 IA32_MTRRCAP MTRR Capability (RO) (MTRRcap) See Section 11.11.2.1, “IA32_MTRR_DEF_TYPE MSR.” 06_01H MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex 10AH 10BH 174H Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 266 267 372 7:0 VCNT: The number of variable memory type ranges in the processor. 8 Fixed range MTRRs are supported when set. 9 Reserved 10 WC Supported when set. 11 SMRR Supported when set. 12 PRMRR supported when set. 63:13 Reserved IA32_ARCH_CAPABILITIES Enumeration of Architectural Features (RO) 0 RDCL_NO: The processor is not susceptible to Rogue Data Cache Load (RDCL). 1 IBRS_ALL: The processor supports enhanced IBRS. 2 RSBA: The processor supports RSB Alternate. Alternative branch predictors may be used by RET instructions when the RSB is empty. SW using retpoline may be affected by this behavior. 3 SKIP_L1DFL_VMENTRY: A value of 1 indicates the hypervisor need not flush the L1D on VM entry. 4 SSB_NO: Processor is not susceptible to Speculative Store Bypass. 63:5 Reserved IA32_FLUSH_CMD Flush Command (WO) If CPUID.(EAX=07H, ECX=0):EDX[29]=1 Gives software a way to invalidate structures with finer granularity than other architectural methods. If any one of the enumeration conditions for defined bit field positions holds. 0 L1D_FLUSH: Writeback and invalidate the L1 data cache. If CPUID.(EAX=07H, ECX=0):EDX[28]=1 63:1 Reserved IA32_SYSENTER_CS SYSENTER_CS_MSR (R/W) 15:0 CS Selector. 31:16 Not used. Can be read and written. 63:32 Not used. Writes ignored; reads 06_01H return zero. 175H 373 IA32_SYSENTER_ESP SYSENTER_ESP_MSR (R/W) 06_01H 176H 374 IA32_SYSENTER_EIP SYSENTER_EIP_MSR (R/W) 06_01H 179H 377 IA32_MCG_CAP (MCG_CAP) Global Machine Check Capability (RO) 06_01H 7:0 Count: Number of reporting banks. Vol. 4 2-9 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex 17AH Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 378 8 MCG_CTL_P: IA32_MCG_CTL is present if this bit is set. 9 MCG_EXT_P: Extended machine check state registers are present if this bit is set. 10 MCP_CMCI_P: Support for corrected MC error event is present. 11 MCG_TES_P: Threshold-based error status register are present if this bit is set. 15:12 Reserved 23:16 MCG_EXT_CNT: Number of extended machine check state registers present. 24 MCG_SER_P: The processor supports software error recovery if this bit is set. 25 Reserved 26 MCG_ELOG_P: Indicates that the processor allows platform firmware to be invoked when an error is detected so that it may provide additional platform specific information in an ACPI format “Generic Error Data Entry” that augments the data included in machine check bank registers. 06_3EH 27 MCG_LMCE_P: Indicates that the processor supports extended state in IA32_MCG_STATUS and associated MSR necessary to configure Local Machine Check Exception (LMCE). 06_3EH 63:28 Reserved IA32_MCG_STATUS Global Machine Check Status (R/W0) 06_01H 0 RIPV. Restart IP valid. 06_01H 1 EIPV. Error IP valid. 06_01H 2 MCIP. Machine check in progress. 06_01H 3 LMCE_S If IA32_MCG_CAP.LMCE_P[2 7] =1 63:4 Reserved Global Machine Check Control (R/W) 06_01H (MCG_STATUS) 17BH 379 IA32_MCG_CTL (MCG_CTL) 180H185H 384389 Reserved 186H 390 IA32_PERFEVTSEL0 (PERFEVTSEL0) 2-10 Vol. 4 If IA32_MCG_CAP.CTL_P[8] =1 06_0EH1 Performance Event Select Register 0 (R/W) If CPUID.0AH: EAX[15:8] > 0 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex 187H Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 391 7:0 Event Select: Selects a performance event logic unit. 15:8 UMask: Qualifies the microarchitectural condition to detect on the selected event logic. 16 USR: Counts while in privilege level is not ring 0. 17 OS: Counts while in privilege level is ring 0. 18 Edge: Enables edge detection if set. 19 PC: Enables pin control. 20 INT: Enables interrupt on counter overflow. 21 AnyThread: When set to 1, it enables counting the associated event conditions occurring across all logical processors sharing a processor core. When set to 0, the counter only increments the associated event conditions occurring in the logical processor which programmed the MSR. 22 EN: Enables the corresponding performance counter to commence counting when this bit is set. 23 INV: Invert the CMASK. 31:24 CMASK: When CMASK is not zero, the corresponding performance counter increments each cycle if the event count is greater than or equal to the CMASK. 63:32 Reserved IA32_PERFEVTSEL1 Performance Event Select Register 1 (R/W) If CPUID.0AH: EAX[15:8] > 1 (PERFEVTSEL1) 188H 392 IA32_PERFEVTSEL2 Performance Event Select Register 2 (R/W) If CPUID.0AH: EAX[15:8] > 2 189H 393 IA32_PERFEVTSEL3 Performance Event Select Register 3 (R/W) If CPUID.0AH: EAX[15:8] > 3 18AH197H 394407 Reserved 198H 408 IA32_PERF_STATUS 06_0EH2 Current Performance Status (RO) 0F_03H See Section 14.1.1, “Software Interface For Initiating Performance State Transitions”. 15:0 Current performance State Value. 63:16 Reserved Vol. 4 2-11 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex 199H Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 409 IA32_PERF_CTL Performance Control MSR (R/W) 0F_03H Software makes a request for a new Performance state (P-State) by writing this MSR. See Section 14.1.1, “Software Interface For Initiating Performance State Transitions”. 15:0 Target performance State Value. 31:16 Reserved 32 IDA Engage (R/W) 06_0FH (Mobile only) When set to 1: disengages IDA. 19AH 410 63:33 Reserved IA32_CLOCK_MODULATION Clock Modulation Control (R/W) If CPUID.01H:EDX[22] = 1 See Section 14.7.3, “Software Controlled Clock Modulation.” 19BH 411 0 Extended On-Demand Clock Modulation Duty Cycle. If CPUID.06H:EAX[5] = 1 3:1 On-Demand Clock Modulation Duty Cycle: Specific encoded values for target duty cycle modulation. If CPUID.01H:EDX[22] = 1 4 On-Demand Clock Modulation Enable: Set 1 to enable modulation. If CPUID.01H:EDX[22] = 1 63:5 Reserved IA32_THERM_INTERRUPT Thermal Interrupt Control (R/W) If CPUID.01H:EDX[22] = 1 Enables and disables the generation of an interrupt on temperature transitions detected with the processor’s thermal sensors and thermal monitor. See Section 14.7.2, “Thermal Monitor.” 2-12 Vol. 4 0 High-Temperature Interrupt Enable If CPUID.01H:EDX[22] = 1 1 Low-Temperature Interrupt Enable If CPUID.01H:EDX[22] = 1 2 PROCHOT# Interrupt Enable If CPUID.01H:EDX[22] = 1 3 FORCEPR# Interrupt Enable If CPUID.01H:EDX[22] = 1 4 Critical Temperature Interrupt Enable If CPUID.01H:EDX[22] = 1 7:5 Reserved 14:8 Threshold #1 Value If CPUID.01H:EDX[22] = 1 15 Threshold #1 Interrupt Enable If CPUID.01H:EDX[22] = 1 22:16 Threshold #2 Value If CPUID.01H:EDX[22] = 1 23 Threshold #2 Interrupt Enable If CPUID.01H:EDX[22] = 1 24 Power Limit Notification Enable If CPUID.06H:EAX[4] = 1 63:25 Reserved MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex 19CH Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 412 IA32_THERM_STATUS Thermal Status Information (RO) If CPUID.01H:EDX[22] = 1 Contains status information about the processor’s thermal sensor and automatic thermal monitoring facilities. See Section 14.7.2, “Thermal Monitor”. 1A0H 416 0 Thermal Status (RO) If CPUID.01H:EDX[22] = 1 1 Thermal Status Log (R/W) If CPUID.01H:EDX[22] = 1 2 PROCHOT # or FORCEPR# event (RO) If CPUID.01H:EDX[22] = 1 3 PROCHOT # or FORCEPR# log (R/WC0) If CPUID.01H:EDX[22] = 1 4 Critical Temperature Status (RO) If CPUID.01H:EDX[22] = 1 5 Critical Temperature Status log (R/WC0) If CPUID.01H:EDX[22] = 1 6 Thermal Threshold #1 Status (RO) If CPUID.01H:ECX[8] = 1 7 Thermal Threshold #1 log (R/WC0) If CPUID.01H:ECX[8] = 1 8 Thermal Threshold #2 Status (RO) If CPUID.01H:ECX[8] = 1 9 Thermal Threshold #2 log (R/WC0) If CPUID.01H:ECX[8] = 1 10 Power Limitation Status (RO) If CPUID.06H:EAX[4] = 1 11 Power Limitation log (R/WC0) If CPUID.06H:EAX[4] = 1 12 Current Limit Status (RO) If CPUID.06H:EAX[7] = 1 13 Current Limit log (R/WC0) If CPUID.06H:EAX[7] = 1 14 Cross Domain Limit Status (RO) If CPUID.06H:EAX[7] = 1 15 Cross Domain Limit log (R/WC0) If CPUID.06H:EAX[7] = 1 22:16 Digital Readout (RO) If CPUID.06H:EAX[0] = 1 26:23 Reserved 30:27 Resolution in Degrees Celsius (RO) If CPUID.06H:EAX[0] = 1 31 Reading Valid (RO) If CPUID.06H:EAX[0] = 1 63:32 Reserved IA32_MISC_ENABLE Enable Misc. Processor Features (R/W) Allows a variety of processor functions to be enabled and disabled. 0 Fast-Strings Enable 0F_0H When set, the fast-strings feature (for REP MOVS and REP STORS) is enabled (default). When clear, fast-strings are disabled. 2:1 Reserved Vol. 4 2-13 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 3 Automatic Thermal Control Circuit Enable (R/W) 0F_0H 1 = Setting this bit enables the thermal control circuit (TCC) portion of the Intel Thermal Monitor feature. This allows the processor to automatically reduce power consumption in response to TCC activation. 0 = Disabled. Note: In some products clearing this bit might be ignored in critical thermal conditions, and TM1, TM2 and adaptive thermal throttling will still be activated. The default value of this field varies with product . See respective tables where default value is listed. 6:4 Reserved 7 Performance Monitoring Available (R) 0F_0H 1 = Performance monitoring enabled. 0 = Performance monitoring disabled. 10:8 11 Reserved Branch Trace Storage Unavailable (RO) 0F_0H 1 = Processor doesn’t support branch trace storage (BTS). 0 = BTS is supported. 12 Processor Event Based Sampling (PEBS) Unavailable (RO) 06_0FH 1 = PEBS is not supported. 0 = PEBS is supported. 15:13 Reserved 16 Enhanced Intel SpeedStep Technology Enable (R/W) 0= Enhanced Intel SpeedStep Technology disabled. 1 = Enhanced Intel SpeedStep Technology enabled. 17 2-14 Vol. 4 Reserved If CPUID.01H: ECX[7] =1 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 18 ENABLE MONITOR FSM (R/W) 0F_03H When this bit is set to 0, the MONITOR feature flag is not set (CPUID.01H:ECX[bit 3] = 0). This indicates that MONITOR/MWAIT are not supported. Software attempts to execute MONITOR/MWAIT will cause #UD when this bit is 0. When this bit is set to 1 (default), MONITOR/MWAIT are supported (CPUID.01H:ECX[bit 3] = 1). If the SSE3 feature flag ECX[0] is not set (CPUID.01H:ECX[bit 0] = 0), the OS must not attempt to alter this bit. BIOS must leave it in the default state. Writing this bit when the SSE3 feature flag is set to 0 may generate a #GP exception. 21:19 Reserved 22 Limit CPUID Maxval (R/W) 0F_03H When this bit is set to 1, CPUID.00H returns a maximum value in EAX[7:0] of 2. BIOS should contain a setup question that allows users to specify when the installed OS does not support CPUID functions greater than 2. Before setting this bit, BIOS must execute the CPUID.0H and examine the maximum value returned in EAX[7:0]. If the maximum value is greater than 2, this bit is supported. Otherwise, this bit is not supported. Setting this bit when the maximum value is not greater than 2 may generate a #GP exception. Setting this bit may cause unexpected behavior in software that depends on the availability of CPUID leaves greater than 2. 23 xTPR Message Disable (R/W) If CPUID.01H:ECX[14] = 1 When set to 1, xTPR messages are disabled. xTPR messages are optional messages that allow the processor to inform the chipset of its priority. 33:24 Reserved Vol. 4 2-15 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 34 XD Bit Disable (R/W) When set to 1, the Execute Disable Bit feature (XD Bit) is disabled and the XD Bit extended feature flag will be clear (CPUID.80000001H: EDX[20]=0). If CPUID.80000001H:EDX[2 0] = 1 When set to a 0 (default), the Execute Disable Bit feature (if available) allows the OS to enable PAE paging and take advantage of data only pages. BIOS must not alter the contents of this bit location, if XD bit is not supported. Writing this bit to 1 when the XD Bit extended feature flag is set to 0 may generate a #GP exception. 1B0H 432 63:35 Reserved IA32_ENERGY_PERF_BIAS Performance Energy Bias Hint (R/W) 3:0 Power Policy Preference: If CPUID.6H:ECX[3] = 1 0 indicates preference to highest performance. 15 indicates preference to maximize energy saving. 63:4 1B1H 433 IA32_PACKAGE_THERM_STATUS Reserved Package Thermal Status Information (RO) Contains status information about the package’s thermal sensor. See Section 14.8, “Package Level Thermal Management.” 2-16 Vol. 4 0 Pkg Thermal Status (RO) 1 Pkg Thermal Status Log (R/W) 2 Pkg PROCHOT # event (RO) 3 Pkg PROCHOT # log (R/WC0) 4 Pkg Critical Temperature Status (RO) 5 Pkg Critical Temperature Status Log (R/WC0) 6 Pkg Thermal Threshold #1 Status (RO) 7 Pkg Thermal Threshold #1 log (R/WC0) 8 Pkg Thermal Threshold #2 Status (RO) 9 Pkg Thermal Threshold #1 log (R/WC0) 10 Pkg Power Limitation Status (RO) 11 Pkg Power Limitation log (R/WC0) 15:12 Reserved 22:16 Pkg Digital Readout (RO) If CPUID.06H: EAX[6] = 1 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex 1B2H Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 434 63:23 Reserved IA32_PACKAGE_THERM_INTERRUPT Pkg Thermal Interrupt Control (R/W) If CPUID.06H: EAX[6] = 1 Enables and disables the generation of an interrupt on temperature transitions detected with the package’s thermal sensor. See Section 14.8, “Package Level Thermal Management.” 1D9H 473 0 Pkg High-Temperature Interrupt Enable 1 Pkg Low-Temperature Interrupt Enable 2 Pkg PROCHOT# Interrupt Enable 3 Reserved 4 Pkg Overheat Interrupt Enable 7:5 Reserved 14:8 Pkg Threshold #1 Value 15 Pkg Threshold #1 Interrupt Enable 22:16 Pkg Threshold #2 Value 23 Pkg Threshold #2 Interrupt Enable 24 Pkg Power Limit Notification Enable 63:25 Reserved IA32_DEBUGCTL Trace/Profile Resource Control (R/W) 06_0EH 0 LBR: Setting this bit to 1 enables the processor to record a running trace of the most recent branches taken by the processor in the LBR stack. 06_01H 1 BTF: Setting this bit to 1 enables the processor to treat EFLAGS.TF as single-step on branches instead of single-step on instructions. 06_01H 5:2 Reserved 6 TR: Setting this bit to 1 enables branch trace messages to be sent. 06_0EH 7 BTS: Setting this bit enables branch trace messages (BTMs) to be logged in a BTS buffer. 06_0EH 8 BTINT: When clear, BTMs are logged in a BTS buffer in circular fashion. When this bit is set, an interrupt is generated by the BTS facility when the BTS buffer is full. 06_0EH 9 1: BTS_OFF_OS: When set, BTS or BTM is skipped if CPL = 0. 06_0FH (MSR_DEBUGCTLA, MSR_DEBUGCTLB) Vol. 4 2-17 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex 1F2H Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 498 10 BTS_OFF_USR: When set, BTS or BTM is skipped if CPL > 0. 06_0FH 11 FREEZE_LBRS_ON_PMI: When set, the LBR stack is frozen on a PMI request. If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1 12 FREEZE_PERFMON_ON_PMI: When set, each ENABLE bit of the global counter control MSR are frozen (address 38FH) on a PMI request. If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1 13 ENABLE_UNCORE_PMI: When set, enables the logical processor to receive and generate PMI on behalf of the uncore. 06_1AH 14 FREEZE_WHILE_SMM: When set, freezes perfmon and trace messages while in SMM. If IA32_PERF_CAPABILITIES[ 12] = 1 15 RTM_DEBUG: When set, enables DR7 debug bit on XBEGIN. If (CPUID.(EAX=07H, ECX=0):EBX[11] = 1) 63:16 Reserved IA32_SMRR_PHYSBASE SMRR Base Address (Writeable only in SMM) Base address of SMM memory range. 7:0 Type. Specifies memory type of the range. 11:8 Reserved 31:12 PhysBase If IA32_MTRRCAP.SMRR[11] =1 SMRR physical Base Address. 1F3H 499 63:32 Reserved IA32_SMRR_PHYSMASK SMRR Range Mask (Writeable only in SMM) Range Mask of SMM memory range. 10:0 11 If IA32_MTRRCAP[SMRR] =1 Reserved Valid Enable range mask. 31:12 PhysMask SMRR address range mask. 63:32 Reserved 1F8H 504 IA32_PLATFORM_DCA_CAP DCA Capability (R) If CPUID.01H: ECX[18] = 1 1F9H 505 IA32_CPU_DCA_CAP If set, CPU supports Prefetch-Hint type. If CPUID.01H: ECX[18] = 1 1FAH 506 IA32_DCA_0_CAP DCA type 0 Status and Control register. If CPUID.01H: ECX[18] = 1 0 DCA_ACTIVE: Set by HW when DCA is fuseenabled and no defeatures are set. 2:1 TRANSACTION 6:3 DCA_TYPE 2-18 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 10:7 DCA_QUEUE_SIZE 12:11 Reserved 16:13 DCA_DELAY: Writes will update the register but have no HW side-effect. 23:17 Reserved 24 SW_BLOCK: SW can request DCA block by setting this bit. 25 Reserved 26 HW_BLOCK: Set when DCA is blocked by HW (e.g. CR0.CD = 1). 31:27 Reserved 200H 512 IA32_MTRR_PHYSBASE0 (MTRRphysBase0) See Section 11.11.2.3, “Variable Range MTRRs.” If CPUID.01H: EDX.MTRR[12] =1 201H 513 IA32_MTRR_PHYSMASK0 MTRRphysMask0 If CPUID.01H: EDX.MTRR[12] =1 202H 514 IA32_MTRR_PHYSBASE1 MTRRphysBase1 If CPUID.01H: EDX.MTRR[12] =1 203H 515 IA32_MTRR_PHYSMASK1 MTRRphysMask1 If CPUID.01H: EDX.MTRR[12] =1 204H 516 IA32_MTRR_PHYSBASE2 MTRRphysBase2 If CPUID.01H: EDX.MTRR[12] =1 205H 517 IA32_MTRR_PHYSMASK2 MTRRphysMask2 If CPUID.01H: EDX.MTRR[12] =1 206H 518 IA32_MTRR_PHYSBASE3 MTRRphysBase3 If CPUID.01H: EDX.MTRR[12] =1 207H 519 IA32_MTRR_PHYSMASK3 MTRRphysMask3 If CPUID.01H: EDX.MTRR[12] =1 208H 520 IA32_MTRR_PHYSBASE4 MTRRphysBase4 If CPUID.01H: EDX.MTRR[12] =1 209H 521 IA32_MTRR_PHYSMASK4 MTRRphysMask4 If CPUID.01H: EDX.MTRR[12] =1 20AH 522 IA32_MTRR_PHYSBASE5 MTRRphysBase5 If CPUID.01H: EDX.MTRR[12] =1 20BH 523 IA32_MTRR_PHYSMASK5 MTRRphysMask5 If CPUID.01H: EDX.MTRR[12] =1 20CH 524 IA32_MTRR_PHYSBASE6 MTRRphysBase6 If CPUID.01H: EDX.MTRR[12] =1 20DH 525 IA32_MTRR_PHYSMASK6 MTRRphysMask6 If CPUID.01H: EDX.MTRR[12] =1 20EH 526 IA32_MTRR_PHYSBASE7 MTRRphysBase7 If CPUID.01H: EDX.MTRR[12] =1 20FH 527 IA32_MTRR_PHYSMASK7 MTRRphysMask7 If CPUID.01H: EDX.MTRR[12] =1 Vol. 4 2-19 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 210H 528 IA32_MTRR_PHYSBASE8 MTRRphysBase8 if IA32_MTRRCAP[7:0] > 8 211H 529 IA32_MTRR_PHYSMASK8 MTRRphysMask8 if IA32_MTRRCAP[7:0] > 8 212H 530 IA32_MTRR_PHYSBASE9 MTRRphysBase9 if IA32_MTRRCAP[7:0] > 9 213H 531 IA32_MTRR_PHYSMASK9 MTRRphysMask9 if IA32_MTRRCAP[7:0] > 9 250H 592 IA32_MTRR_FIX64K_00000 MTRRfix64K_00000 If CPUID.01H: EDX.MTRR[12] =1 258H 600 IA32_MTRR_FIX16K_80000 MTRRfix16K_80000 If CPUID.01H: EDX.MTRR[12] =1 259H 601 IA32_MTRR_FIX16K_A0000 MTRRfix16K_A0000 If CPUID.01H: EDX.MTRR[12] =1 268H 616 IA32_MTRR_FIX4K_C0000 (MTRRfix4K_C0000 ) See Section 11.11.2.2, “Fixed Range MTRRs.” If CPUID.01H: EDX.MTRR[12] =1 269H 617 IA32_MTRR_FIX4K_C8000 MTRRfix4K_C8000 If CPUID.01H: EDX.MTRR[12] =1 26AH 618 IA32_MTRR_FIX4K_D0000 MTRRfix4K_D0000 If CPUID.01H: EDX.MTRR[12] =1 26BH 619 IA32_MTRR_FIX4K_D8000 MTRRfix4K_D8000 If CPUID.01H: EDX.MTRR[12] =1 26CH 620 IA32_MTRR_FIX4K_E0000 MTRRfix4K_E0000 If CPUID.01H: EDX.MTRR[12] =1 26DH 621 IA32_MTRR_FIX4K_E8000 MTRRfix4K_E8000 If CPUID.01H: EDX.MTRR[12] =1 26EH 622 IA32_MTRR_FIX4K_F0000 MTRRfix4K_F0000 If CPUID.01H: EDX.MTRR[12] =1 26FH 623 IA32_MTRR_FIX4K_F8000 MTRRfix4K_F8000 If CPUID.01H: EDX.MTRR[12] =1 277H 631 IA32_PAT IA32_PAT (R/W) If CPUID.01H: EDX.MTRR[16] =1 2:0 PA0 7:3 Reserved 10:8 PA1 15:11 Reserved 18:16 PA2 23:19 Reserved 26:24 PA3 31:27 Reserved 34:32 PA4 39:35 Reserved 42:40 PA5 47:43 Reserved 50:48 PA6 2-20 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex 280H Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 640 55:51 Reserved 58:56 PA7 63:59 Reserved IA32_MC0_CTL2 MSR to enable/disable CMCI capability for bank 0. (R/W) See Section 15.3.2.5, “IA32_MCi_CTL2 MSRs”. 14:0 Corrected error count threshold. 29:15 Reserved 30 CMCI_EN 63:31 Reserved If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > 0 281H 641 IA32_MC1_CTL2 (R/W) Same fields as IA32_MC0_CTL2. If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > 1 282H 642 IA32_MC2_CTL2 (R/W) Same fields as IA32_MC0_CTL2. If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > 2 283H 643 IA32_MC3_CTL2 (R/W) Same fields as IA32_MC0_CTL2. If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > 3 284H 644 IA32_MC4_CTL2 (R/W) Same fields as IA32_MC0_CTL2. If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > 4 285H 645 IA32_MC5_CTL2 (R/W) Same fields as IA32_MC0_CTL2. If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > 5 286H 646 IA32_MC6_CTL2 (R/W) Same fields as IA32_MC0_CTL2. If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > 6 287H 647 IA32_MC7_CTL2 (R/W) Same fields as IA32_MC0_CTL2. If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > 7 288H 648 IA32_MC8_CTL2 (R/W) Same fields as IA32_MC0_CTL2. If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > 8 289H 649 IA32_MC9_CTL2 (R/W) Same fields as IA32_MC0_CTL2. If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > 9 28AH 650 IA32_MC10_CTL2 (R/W) Same fields as IA32_MC0_CTL2. If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > 10 28BH 651 IA32_MC11_CTL2 (R/W) Same fields as IA32_MC0_CTL2. If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > 11 Vol. 4 2-21 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 28CH 652 IA32_MC12_CTL2 (R/W) Same fields as IA32_MC0_CTL2. If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > 12 28DH 653 IA32_MC13_CTL2 (R/W) Same fields as IA32_MC0_CTL2. If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > 13 28EH 654 IA32_MC14_CTL2 (R/W) Same fields as IA32_MC0_CTL2. If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > 14 28FH 655 IA32_MC15_CTL2 (R/W) Same fields as IA32_MC0_CTL2. If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > 15 290H 656 IA32_MC16_CTL2 (R/W) Same fields as IA32_MC0_CTL2. If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > 16 291H 657 IA32_MC17_CTL2 (R/W) Same fields as IA32_MC0_CTL2. If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > 17 292H 658 IA32_MC18_CTL2 (R/W) Same fields as IA32_MC0_CTL2. If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > 18 293H 659 IA32_MC19_CTL2 (R/W) Same fields as IA32_MC0_CTL2. If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > 19 294H 660 IA32_MC20_CTL2 (R/W) Same fields as IA32_MC0_CTL2. If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > 20 295H 661 IA32_MC21_CTL2 (R/W) Same fields as IA32_MC0_CTL2. If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > 21 296H 662 IA32_MC22_CTL2 (R/W) Same fields as IA32_MC0_CTL2. If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > 22 297H 663 IA32_MC23_CTL2 (R/W) Same fields as IA32_MC0_CTL2. If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > 23 298H 664 IA32_MC24_CTL2 (R/W) Same fields as IA32_MC0_CTL2. If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > 24 299H 665 IA32_MC25_CTL2 (R/W) Same fields as IA32_MC0_CTL2. If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > 25 29AH 666 IA32_MC26_CTL2 (R/W) Same fields as IA32_MC0_CTL2. If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > 26 2-22 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 29BH 667 IA32_MC27_CTL2 (R/W) Same fields as IA32_MC0_CTL2. If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > 27 29CH 668 IA32_MC28_CTL2 (R/W) Same fields as IA32_MC0_CTL2. If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > 28 29DH 669 IA32_MC29_CTL2 (R/W) Same fields as IA32_MC0_CTL2. If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > 29 29EH 670 IA32_MC30_CTL2 (R/W) Same fields as IA32_MC0_CTL2. If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > 30 29FH 671 IA32_MC31_CTL2 (R/W) Same fields as IA32_MC0_CTL2. If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > 31 2FFH 767 IA32_MTRR_DEF_TYPE MTRRdefType (R/W) If CPUID.01H: EDX.MTRR[12] =1 2:0 Default Memory Type 9:3 Reserved 10 Fixed Range MTRR Enable 11 MTRR Enable 63:12 Reserved 309H 777 IA32_FIXED_CTR0 Fixed-Function Performance Counter 0 (R/W): Counts Instr_Retired.Any. If CPUID.0AH: EDX[4:0] > 0 30AH 778 IA32_FIXED_CTR1 Fixed-Function Performance Counter 1 (R/W): Counts CPU_CLK_Unhalted.Core. If CPUID.0AH: EDX[4:0] > 1 30BH 779 IA32_FIXED_CTR2 Fixed-Function Performance Counter 2 (R/W): Counts CPU_CLK_Unhalted.Ref. If CPUID.0AH: EDX[4:0] > 2 345H 837 IA32_PERF_CAPABILITIES Read Only MSR that enumerates the existence of performance monitoring features. (RO) If CPUID.01H: ECX[15] = 1 5:0 LBR format 6 PEBS Trap 7 PEBSSaveArchRegs Vol. 4 2-23 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex 38DH Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 909 11:8 PEBS Record Format 12 1: Freeze while SMM is supported. 13 1: Full width of counter writable via IA32_A_PMCx. 14 Reserved 15 1: Performance metrics available. 16 1: PEBS output will be written into the Intel PT trace stream. 63:17 Reserved IA32_FIXED_CTR_CTRL Fixed-Function Performance Counter Control (R/W) If CPUID.0x7.0.EBX[25]=1 If CPUID.0AH: EAX[7:0] > 1 Counter increments while the results of ANDing respective enable bit in IA32_PERF_GLOBAL_CTRL with the corresponding OS or USR bits in this MSR is true. 2-24 Vol. 4 0 EN0_OS: Enable Fixed Counter 0 to count while CPL = 0. 1 EN0_Usr: Enable Fixed Counter 0 to count while CPL > 0. 2 AnyThread: When set to 1, it enables counting the associated event conditions occurring across all logical processors sharing a processor core. When set to 0, the counter only increments the associated event conditions occurring in the logical processor which programmed the MSR. 3 EN0_PMI: Enable PMI when fixed counter 0 overflows. 4 EN1_OS: Enable Fixed Counter 1to count while CPL = 0. 5 EN1_Usr: Enable Fixed Counter 1to count while CPL > 0. 6 AnyThread: When set to 1, it enables counting the associated event conditions occurring across all logical processors sharing a processor core. When set to 0, the counter only increments the associated event conditions occurring in the logical processor which programmed the MSR. 7 EN1_PMI: Enable PMI when fixed counter 1 overflows. 8 EN2_OS: Enable Fixed Counter 2 to count while CPL = 0. If CPUID.0AH: EAX[7:0] > 2 If CPUID.0AH: EAX[7:0] > 2 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex 38EH Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 910 9 EN2_Usr: Enable Fixed Counter 2 to count while CPL > 0. 10 AnyThread: When set to 1, it enables counting the associated event conditions occurring across all logical processors sharing a processor core. When set to 0, the counter only increments the associated event conditions occurring in the logical processor which programmed the MSR. If CPUID.0AH: EAX[7:0] > 2 11 EN2_PMI: Enable PMI when fixed counter 2 overflows. 63:12 Reserved IA32_PERF_GLOBAL_STATUS Global Performance Counter Status (RO) If CPUID.0AH: EAX[7:0] > 0 0 Ovf_PMC0: Overflow status of IA32_PMC0. If CPUID.0AH: EAX[15:8] > 0 1 Ovf_PMC1: Overflow status of IA32_PMC1. If CPUID.0AH: EAX[15:8] > 1 2 Ovf_PMC2: Overflow status of IA32_PMC2. If CPUID.0AH: EAX[15:8] > 2 3 Ovf_PMC3: Overflow status of IA32_PMC3. If CPUID.0AH: EAX[15:8] > 3 31:4 Reserved 32 Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0. If CPUID.0AH: EAX[7:0] > 1 33 Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1. If CPUID.0AH: EAX[7:0] > 1 34 Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2. If CPUID.0AH: EAX[7:0] > 1 47:35 Reserved 48 OVF_PERF_METRICS: If this bit is set, it indicates that PERF_METRIC counter has overflowed and a PMI is triggered; however, an overflow of fixed counter 3 should normally happen first. If this bit is clear no overflow occurred. 54:49 Reserved 55 Trace_ToPA_PMI: A PMI occurred due to a ToPA entry memory buffer that was completely filled. 57:56 Reserved 58 LBR_Frz. LBRs are frozen due to: If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA = 1 If CPUID.0AH: EAX[7:0] > 3 • IA32_DEBUGCTL.FREEZE_LBR_ON_PMI=1. • The LBR stack overflowed. Vol. 4 2-25 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment CTR_Frz. Performance counters in the core PMU are frozen due to: If CPUID.0AH: EAX[7:0] > 3 Decimal 59 • IA32_DEBUGCTL.FREEZE_PERFMON_ON_ PMI=1. • One or more core PMU counters overflowed. 38FH 911 60 ASCI: Data in the performance counters in the core PMU may include contributions from the direct or indirect operation Intel SGX to protect an enclave. If CPUID.(EAX=07H, ECX=0):EBX[2] = 1 61 Ovf_Uncore: Uncore counter overflow status. If CPUID.0AH: EAX[7:0] > 2 62 OvfBuf: DS SAVE area Buffer overflow status. If CPUID.0AH: EAX[7:0] > 0 63 CondChgd: Status bits of this register have changed. If CPUID.0AH: EAX[7:0] > 0 Global Performance Counter Control (R/W) If CPUID.0AH: EAX[7:0] > 0 IA32_PERF_GLOBAL_CTRL Counter increments while the result of ANDing the respective enable bit in this MSR with the corresponding OS or USR bits in the general-purpose or fixed counter control MSR is true. 390H 2-26 Vol. 4 912 0 EN_PMC0 If CPUID.0AH: EAX[15:8] > 0 1 EN_PMC1 If CPUID.0AH: EAX[15:8] > 1 2 EN_PMC2 If CPUID.0AH: EAX[15:8] > 2 n EN_PMCn If CPUID.0AH: EAX[15:8] > n 31:n+1 Reserved 32 EN_FIXED_CTR0 If CPUID.0AH: EDX[4:0] > 0 33 EN_FIXED_CTR1 If CPUID.0AH: EDX[4:0] > 1 34 EN_FIXED_CTR2 If CPUID.0AH: EDX[4:0] > 2 47:35 Reserved 48 EN_PERF_METRICS: If this bit is set and fixed counter 3 is effectively enabled, builtin performance metrics are enabled. 63:49 Reserved IA32_PERF_GLOBAL_OVF_CTRL Global Performance Counter Overflow Control (R/W) If CPUID.0AH: EAX[7:0] > 0 && CPUID.0AH: EAX[7:0] <= 3 0 Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > 0 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex 390H Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 912 1 Set 1 to Clear Ovf_PMC1 bit. If CPUID.0AH: EAX[15:8] > 1 2 Set 1 to Clear Ovf_PMC2 bit. If CPUID.0AH: EAX[15:8] > 2 n Set 1 to Clear Ovf_PMCn bit. If CPUID.0AH: EAX[15:8] > n 31:n Reserved 32 Set 1 to Clear Ovf_FIXED_CTR0 bit. If CPUID.0AH: EDX[4:0] > 0 33 Set 1 to Clear Ovf_FIXED_CTR1 bit. If CPUID.0AH: EDX[4:0] > 1 34 Set 1 to Clear Ovf_FIXED_CTR2 bit. If CPUID.0AH: EDX[4:0] > 2 54:35 Reserved 55 Set 1 to Clear Trace_ToPA_PMI bit. 60:56 Reserved 61 Set 1 to Clear Ovf_Uncore bit. 06_2EH 62 Set 1 to Clear OvfBuf bit. If CPUID.0AH: EAX[7:0] > 0 63 Set 1 to clear CondChgd bit. If CPUID.0AH: EAX[7:0] > 0 IA32_PERF_GLOBAL_STATUS_RESET Global Performance Counter Overflow Reset Control (R/W) If CPUID.0AH: EAX[7:0] > 3 0 Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > 0 1 Set 1 to Clear Ovf_PMC1 bit. If CPUID.0AH: EAX[15:8] > 1 2 Set 1 to Clear Ovf_PMC2 bit. If CPUID.0AH: EAX[15:8] > 2 n Set 1 to Clear Ovf_PMCn bit. If CPUID.0AH: EAX[15:8] > n 31:n Reserved 32 Set 1 to Clear Ovf_FIXED_CTR0 bit. If CPUID.0AH: EDX[4:0] > 0 33 Set 1 to Clear Ovf_FIXED_CTR1 bit. If CPUID.0AH: EDX[4:0] > 1 34 Set 1 to Clear Ovf_FIXED_CTR2 bit. If CPUID.0AH: EDX[4:0] > 2 47:35 Reserved 48 RESET_OVF_PERF_METRICS: If this bit is set, it will clear the status bit in the IA32_PERF_GLOBAL_STATUS register for the PERF_METRICS counters. 54:49 Reserved 55 Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA = 1 If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA[8] = 1 Vol. 4 2-27 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex 391H 392H 2-28 Vol. 4 Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 913 914 57:56 Reserved 58 Set 1 to Clear LBR_Frz bit. If CPUID.0AH: EAX[7:0] > 3 59 Set 1 to Clear CTR_Frz bit. If CPUID.0AH: EAX[7:0] > 3 58 Set 1 to Clear ASCI bit. If CPUID.0AH: EAX[7:0] > 3 61 Set 1 to Clear Ovf_Uncore bit. 06_2EH 62 Set 1 to Clear OvfBuf bit. If CPUID.0AH: EAX[7:0] > 0 63 Set 1 to clear CondChgd bit. If CPUID.0AH: EAX[7:0] > 0 IA32_PERF_GLOBAL_STATUS_SET Global Performance Counter Overflow Set Control (R/W) If CPUID.0AH: EAX[7:0] > 3 0 Set 1 to cause Ovf_PMC0 = 1. If CPUID.0AH: EAX[7:0] > 3 1 Set 1 to cause Ovf_PMC1 = 1. If CPUID.0AH: EAX[15:8] > 1 2 Set 1 to cause Ovf_PMC2 = 1. If CPUID.0AH: EAX[15:8] > 2 n Set 1 to cause Ovf_PMCn = 1. If CPUID.0AH: EAX[15:8] > n 31:n Reserved 32 Set 1 to cause Ovf_FIXED_CTR0 = 1. If CPUID.0AH: EAX[7:0] > 3 33 Set 1 to cause Ovf_FIXED_CTR1 = 1. If CPUID.0AH: EAX[7:0] > 3 34 Set 1 to cause Ovf_FIXED_CTR2 = 1. If CPUID.0AH: EAX[7:0] > 3 47:35 Reserved 48 SET_OVF_PERF_METRICS: If this bit is set, it will set the status bit in the IA32_PERF_GLOBAL_STATUS register for the PERF_METRICS counters. 54:49 Reserved 55 Set 1 to cause Trace_ToPA_PMI = 1. 57:56 Reserved If CPUID.0AH: EAX[7:0] > 3 58 Set 1 to cause LBR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3 59 Set 1 to cause CTR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3 58 Set 1 to cause ASCI = 1. If CPUID.0AH: EAX[7:0] > 3 61 Set 1 to cause Ovf_Uncore = 1. If CPUID.0AH: EAX[7:0] > 3 62 Set 1 to cause OvfBuf = 1. If CPUID.0AH: EAX[7:0] > 3 63 Reserved IA32_PERF_GLOBAL_INUSE Indicator that core perfmon interface is in use. (RO) 0 IA32_PERFEVTSEL0 in use. 1 IA32_PERFEVTSEL1 in use. If CPUID.0AH: EAX[7:0] > 3 If CPUID.0AH: EAX[15:8] > 1 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex 3F1H Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 1009 2 IA32_PERFEVTSEL2 in use. If CPUID.0AH: EAX[15:8] > 2 n IA32_PERFEVTSELn in use. If CPUID.0AH: EAX[15:8] > n 31:n+1 Reserved 32 IA32_FIXED_CTR0 in use. 33 IA32_FIXED_CTR1 in use. 34 IA32_FIXED_CTR2 in use. 62:35 Reserved or model specific. 63 PMI in use. IA32_PEBS_ENABLE PEBS Control (R/W) 0 Enable PEBS on IA32_PMC0. 3:1 Reserved or model specific. 31:4 Reserved 35:32 Reserved or model specific. 63:36 Reserved 06_0FH 400H 1024 IA32_MC0_CTL MC0_CTL If IA32_MCG_CAP.CNT >0 401H 1025 IA32_MC0_STATUS MC0_STATUS If IA32_MCG_CAP.CNT >0 402H 1026 IA32_MC0_ADDR1 MC0_ADDR If IA32_MCG_CAP.CNT >0 403H 1027 IA32_MC0_MISC MC0_MISC If IA32_MCG_CAP.CNT >0 404H 1028 IA32_MC1_CTL MC1_CTL If IA32_MCG_CAP.CNT >1 405H 1029 IA32_MC1_STATUS MC1_STATUS If IA32_MCG_CAP.CNT >1 406H 1030 IA32_MC1_ADDR2 MC1_ADDR If IA32_MCG_CAP.CNT >1 407H 1031 IA32_MC1_MISC MC1_MISC If IA32_MCG_CAP.CNT >1 408H 1032 IA32_MC2_CTL MC2_CTL If IA32_MCG_CAP.CNT >2 409H 1033 IA32_MC2_STATUS MC2_STATUS If IA32_MCG_CAP.CNT >2 40AH 1034 IA32_MC2_ADDR1 MC2_ADDR If IA32_MCG_CAP.CNT >2 40BH 1035 IA32_MC2_MISC MC2_MISC If IA32_MCG_CAP.CNT >2 40CH 1036 IA32_MC3_CTL MC3_CTL If IA32_MCG_CAP.CNT >3 40DH 1037 IA32_MC3_STATUS MC3_STATUS If IA32_MCG_CAP.CNT >3 40EH 1038 IA32_MC3_ADDR1 MC3_ADDR If IA32_MCG_CAP.CNT >3 40FH 1039 IA32_MC3_MISC MC3_MISC If IA32_MCG_CAP.CNT >3 410H 1040 IA32_MC4_CTL MC4_CTL If IA32_MCG_CAP.CNT >4 411H 1041 IA32_MC4_STATUS MC4_STATUS If IA32_MCG_CAP.CNT >4 412H 1042 IA32_MC4_ADDR1 MC4_ADDR If IA32_MCG_CAP.CNT >4 413H 1043 IA32_MC4_MISC MC4_MISC If IA32_MCG_CAP.CNT >4 414H 1044 IA32_MC5_CTL MC5_CTL If IA32_MCG_CAP.CNT >5 Vol. 4 2-29 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex 415H Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 1045 IA32_MC5_STATUS 1 MC5_STATUS If IA32_MCG_CAP.CNT >5 416H 1046 IA32_MC5_ADDR MC5_ADDR If IA32_MCG_CAP.CNT >5 417H 1047 IA32_MC5_MISC MC5_MISC If IA32_MCG_CAP.CNT >5 418H 1048 IA32_MC6_CTL MC6_CTL If IA32_MCG_CAP.CNT >6 419H 1049 IA32_MC6_STATUS MC6_STATUS If IA32_MCG_CAP.CNT >6 41AH 1050 IA32_MC6_ADDR1 MC6_ADDR If IA32_MCG_CAP.CNT >6 41BH 1051 IA32_MC6_MISC MC6_MISC If IA32_MCG_CAP.CNT >6 41CH 1052 IA32_MC7_CTL MC7_CTL If IA32_MCG_CAP.CNT >7 41DH 1053 IA32_MC7_STATUS MC7_STATUS If IA32_MCG_CAP.CNT >7 41EH 1054 IA32_MC7_ADDR1 MC7_ADDR If IA32_MCG_CAP.CNT >7 41FH 1055 IA32_MC7_MISC MC7_MISC If IA32_MCG_CAP.CNT >7 420H 1056 IA32_MC8_CTL MC8_CTL If IA32_MCG_CAP.CNT >8 421H 1057 IA32_MC8_STATUS MC8_STATUS If IA32_MCG_CAP.CNT >8 422H 1058 IA32_MC8_ADDR1 MC8_ADDR If IA32_MCG_CAP.CNT >8 423H 1059 IA32_MC8_MISC MC8_MISC If IA32_MCG_CAP.CNT >8 424H 1060 IA32_MC9_CTL MC9_CTL If IA32_MCG_CAP.CNT >9 425H 1061 IA32_MC9_STATUS MC9_STATUS If IA32_MCG_CAP.CNT >9 426H 1062 IA32_MC9_ADDR1 MC9_ADDR If IA32_MCG_CAP.CNT >9 427H 1063 IA32_MC9_MISC MC9_MISC If IA32_MCG_CAP.CNT >9 428H 1064 IA32_MC10_CTL MC10_CTL If IA32_MCG_CAP.CNT >10 429H 1065 IA32_MC10_STATUS MC10_STATUS If IA32_MCG_CAP.CNT >10 42AH 1066 IA32_MC10_ADDR1 MC10_ADDR If IA32_MCG_CAP.CNT >10 42BH 1067 IA32_MC10_MISC MC10_MISC If IA32_MCG_CAP.CNT >10 42CH 1068 IA32_MC11_CTL MC11_CTL If IA32_MCG_CAP.CNT >11 42DH 1069 IA32_MC11_STATUS MC11_STATUS If IA32_MCG_CAP.CNT >11 42EH 1070 IA32_MC11_ADDR1 MC11_ADDR If IA32_MCG_CAP.CNT >11 42FH 1071 IA32_MC11_MISC MC11_MISC If IA32_MCG_CAP.CNT >11 430H 1072 IA32_MC12_CTL MC12_CTL If IA32_MCG_CAP.CNT >12 431H 1073 IA32_MC12_STATUS MC12_STATUS If IA32_MCG_CAP.CNT >12 432H 1074 IA32_MC12_ADDR1 MC12_ADDR If IA32_MCG_CAP.CNT >12 433H 1075 IA32_MC12_MISC MC12_MISC If IA32_MCG_CAP.CNT >12 434H 1076 IA32_MC13_CTL MC13_CTL If IA32_MCG_CAP.CNT >13 435H 1077 IA32_MC13_STATUS MC13_STATUS If IA32_MCG_CAP.CNT >13 436H 1078 IA32_MC13_ADDR1 MC13_ADDR If IA32_MCG_CAP.CNT >13 437H 1079 IA32_MC13_MISC MC13_MISC If IA32_MCG_CAP.CNT >13 438H 1080 IA32_MC14_CTL MC14_CTL If IA32_MCG_CAP.CNT >14 439H 1081 IA32_MC14_STATUS MC14_STATUS If IA32_MCG_CAP.CNT >14 2-30 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 43AH 1082 IA32_MC14_ADDR1 MC14_ADDR If IA32_MCG_CAP.CNT >14 43BH 1083 IA32_MC14_MISC MC14_MISC If IA32_MCG_CAP.CNT >14 43CH 1084 IA32_MC15_CTL MC15_CTL If IA32_MCG_CAP.CNT >15 43DH 1085 IA32_MC15_STATUS MC15_STATUS If IA32_MCG_CAP.CNT >15 43EH 1086 IA32_MC15_ADDR1 MC15_ADDR If IA32_MCG_CAP.CNT >15 43FH 1087 IA32_MC15_MISC MC15_MISC If IA32_MCG_CAP.CNT >15 440H 1088 IA32_MC16_CTL MC16_CTL If IA32_MCG_CAP.CNT >16 441H 1089 IA32_MC16_STATUS MC16_STATUS If IA32_MCG_CAP.CNT >16 442H 1090 IA32_MC16_ADDR1 MC16_ADDR If IA32_MCG_CAP.CNT >16 443H 1091 IA32_MC16_MISC MC16_MISC If IA32_MCG_CAP.CNT >16 444H 1092 IA32_MC17_CTL MC17_CTL If IA32_MCG_CAP.CNT >17 445H 1093 IA32_MC17_STATUS MC17_STATUS If IA32_MCG_CAP.CNT >17 446H 1094 IA32_MC17_ADDR1 MC17_ADDR If IA32_MCG_CAP.CNT >17 447H 1095 IA32_MC17_MISC MC17_MISC If IA32_MCG_CAP.CNT >17 448H 1096 IA32_MC18_CTL MC18_CTL If IA32_MCG_CAP.CNT >18 449H 1097 IA32_MC18_STATUS MC18_STATUS If IA32_MCG_CAP.CNT >18 44AH 1098 IA32_MC18_ADDR1 MC18_ADDR If IA32_MCG_CAP.CNT >18 44BH 1099 IA32_MC18_MISC MC18_MISC If IA32_MCG_CAP.CNT >18 44CH 1100 IA32_MC19_CTL MC19_CTL If IA32_MCG_CAP.CNT >19 44DH 1101 IA32_MC19_STATUS MC19_STATUS If IA32_MCG_CAP.CNT >19 44EH 1102 IA32_MC19_ADDR1 MC19_ADDR If IA32_MCG_CAP.CNT >19 44FH 1103 IA32_MC19_MISC MC19_MISC If IA32_MCG_CAP.CNT >19 450H 1104 IA32_MC20_CTL MC20_CTL If IA32_MCG_CAP.CNT >20 451H 1105 IA32_MC20_STATUS MC20_STATUS If IA32_MCG_CAP.CNT >20 452H 1106 IA32_MC20_ADDR1 MC20_ADDR If IA32_MCG_CAP.CNT >20 453H 1107 IA32_MC20_MISC MC20_MISC If IA32_MCG_CAP.CNT >20 454H 1108 IA32_MC21_CTL MC21_CTL If IA32_MCG_CAP.CNT >21 455H 1109 IA32_MC21_STATUS MC21_STATUS If IA32_MCG_CAP.CNT >21 456H 1110 IA32_MC21_ADDR1 MC21_ADDR If IA32_MCG_CAP.CNT >21 457H 1111 IA32_MC21_MISC MC21_MISC If IA32_MCG_CAP.CNT >21 458H 1112 IA32_MC22_CTL MC22_CTL If IA32_MCG_CAP.CNT >22 459H 1113 IA32_MC22_STATUS MC22_STATUS If IA32_MCG_CAP.CNT >22 45AH 1114 IA32_MC22_ADDR1 MC22_ADDR If IA32_MCG_CAP.CNT >22 45BH 1115 IA32_MC22_MISC MC22_MISC If IA32_MCG_CAP.CNT >22 45CH 1116 IA32_MC23_CTL MC23_CTL If IA32_MCG_CAP.CNT >23 45DH 1117 IA32_MC23_STATUS MC23_STATUS If IA32_MCG_CAP.CNT >23 1118 IA32_MC23_ADDR1 MC23_ADDR If IA32_MCG_CAP.CNT >23 45EH Vol. 4 2-31 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 45FH 1119 IA32_MC23_MISC MC23_MISC If IA32_MCG_CAP.CNT >23 460H 1120 IA32_MC24_CTL MC24_CTL If IA32_MCG_CAP.CNT >24 461H 1121 IA32_MC24_STATUS MC24_STATUS If IA32_MCG_CAP.CNT >24 1 462H 1122 IA32_MC24_ADDR MC24_ADDR If IA32_MCG_CAP.CNT >24 463H 1123 IA32_MC24_MISC MC24_MISC If IA32_MCG_CAP.CNT >24 464H 1124 IA32_MC25_CTL MC25_CTL If IA32_MCG_CAP.CNT >25 465H 1125 IA32_MC25_STATUS MC25_STATUS If IA32_MCG_CAP.CNT >25 466H 1126 IA32_MC25_ADDR1 MC25_ADDR If IA32_MCG_CAP.CNT >25 467H 1127 IA32_MC25_MISC MC25_MISC If IA32_MCG_CAP.CNT >25 468H 1128 IA32_MC26_CTL MC26_CTL If IA32_MCG_CAP.CNT >26 469H 1129 IA32_MC26_STATUS MC26_STATUS If IA32_MCG_CAP.CNT >26 46AH 1130 IA32_MC26_ADDR1 MC26_ADDR If IA32_MCG_CAP.CNT >26 46BH 1131 IA32_MC26_MISC MC26_MISC If IA32_MCG_CAP.CNT >26 46CH 1132 IA32_MC27_CTL MC27_CTL If IA32_MCG_CAP.CNT >27 46DH 1133 IA32_MC27_STATUS MC27_STATUS If IA32_MCG_CAP.CNT >27 46EH 1134 IA32_MC27_ADDR1 MC27_ADDR If IA32_MCG_CAP.CNT >27 46FH 1135 IA32_MC27_MISC MC27_MISC If IA32_MCG_CAP.CNT >27 470H 1136 IA32_MC28_CTL MC28_CTL If IA32_MCG_CAP.CNT >28 471H 1137 IA32_MC28_STATUS MC28_STATUS If IA32_MCG_CAP.CNT >28 472H 1138 IA32_MC28_ADDR1 MC28_ADDR If IA32_MCG_CAP.CNT >28 473H 1139 IA32_MC28_MISC MC28_MISC If IA32_MCG_CAP.CNT >28 480H 1152 IA32_VMX_BASIC Reporting Register of Basic VMX Capabilities (R/O) If CPUID.01H:ECX.[5] = 1 See Appendix A.1, “Basic VMX Information.” 481H 1153 IA32_VMX_PINBASED_CTLS Capability Reporting Register of Pin-Based VM-Execution Controls (R/O) If CPUID.01H:ECX.[5] = 1 See Appendix A.3.1, “Pin-Based VMExecution Controls.” 482H 1154 IA32_VMX_PROCBASED_CTLS Capability Reporting Register of Primary Processor-Based VM-Execution Controls (R/O) If CPUID.01H:ECX.[5] = 1 See Appendix A.3.2, “Primary ProcessorBased VM-Execution Controls.” 483H 1155 IA32_VMX_EXIT_CTLS Capability Reporting Register of VM-Exit Controls (R/O) If CPUID.01H:ECX.[5] = 1 See Appendix A.4, “VM-Exit Controls.” 484H 1156 IA32_VMX_ENTRY_CTLS Capability Reporting Register of VM-Entry Controls (R/O) See Appendix A.5, “VM-Entry Controls.” 2-32 Vol. 4 If CPUID.01H:ECX.[5] = 1 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 485H 1157 IA32_VMX_MISC 486H 1158 IA32_VMX_CR0_FIXED0 Reporting Register of Miscellaneous VMX Capabilities (R/O) If CPUID.01H:ECX.[5] = 1 See Appendix A.6, “Miscellaneous Data.” Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) If CPUID.01H:ECX.[5] = 1 See Appendix A.7, “VMX-Fixed Bits in CR0.” 487H 1159 IA32_VMX_CR0_FIXED1 Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) If CPUID.01H:ECX.[5] = 1 See Appendix A.7, “VMX-Fixed Bits in CR0.” 488H 1160 IA32_VMX_CR4_FIXED0 Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) If CPUID.01H:ECX.[5] = 1 See Appendix A.8, “VMX-Fixed Bits in CR4.” 489H 1161 IA32_VMX_CR4_FIXED1 Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) If CPUID.01H:ECX.[5] = 1 See Appendix A.8, “VMX-Fixed Bits in CR4.” 48AH 1162 IA32_VMX_VMCS_ENUM Capability Reporting Register of VMCS Field Enumeration (R/O) If CPUID.01H:ECX.[5] = 1 See Appendix A.9, “VMCS Enumeration.” 48BH 1163 IA32_VMX_PROCBASED_CTLS2 Capability Reporting Register of Secondary Processor-Based VM-Execution Controls (R/O) If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C TLS[63]) See Appendix A.3.3, “Secondary ProcessorBased VM-Execution Controls.” 48CH 48DH 1164 1165 IA32_VMX_EPT_VPID_CAP IA32_VMX_TRUE_PINBASED_CTLS Capability Reporting Register of EPT and VPID (R/O) See Appendix A.10, “VPID and EPT Capabilities.” If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C TLS[63] && ( IA32_VMX_PROCBASED_C TLS2[33] || IA32_VMX_PROCBASED_C TLS2[37]) ) Capability Reporting Register of Pin-Based VM-Execution Flex Controls (R/O) If ( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ) See Appendix A.3.1, “Pin-Based VMExecution Controls.” 48EH 1166 IA32_VMX_TRUE_PROCBASED_CTLS Capability Reporting Register of Primary Processor-Based VM-Execution Flex Controls (R/O) If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ) See Appendix A.3.2, “Primary ProcessorBased VM-Execution Controls.” 48FH 1167 IA32_VMX_TRUE_EXIT_CTLS Capability Reporting Register of VM-Exit Flex Controls (R/O) If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ) See Appendix A.4, “VM-Exit Controls.” 490H 1168 IA32_VMX_TRUE_ENTRY_CTLS Capability Reporting Register of VM-Entry Flex Controls (R/O) If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ) See Appendix A.5, “VM-Entry Controls.” Vol. 4 2-33 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 491H 1169 IA32_VMX_VMFUNC Capability Reporting Register of VMFunction Controls (R/O) If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ) 4C1H 1217 IA32_A_PMC0 Full Width Writable IA32_PMC0 Alias (R/W) (If CPUID.0AH: EAX[15:8] > 0) && IA32_PERF_CAPABILITIES[ 13] = 1 4C2H 1218 IA32_A_PMC1 Full Width Writable IA32_PMC1 Alias (R/W) (If CPUID.0AH: EAX[15:8] > 1) && IA32_PERF_CAPABILITIES[ 13] = 1 4C3H 1219 IA32_A_PMC2 Full Width Writable IA32_PMC2 Alias (R/W) (If CPUID.0AH: EAX[15:8] > 2) && IA32_PERF_CAPABILITIES[ 13] = 1 4C4H 1220 IA32_A_PMC3 Full Width Writable IA32_PMC3 Alias (R/W) (If CPUID.0AH: EAX[15:8] > 3) && IA32_PERF_CAPABILITIES[ 13] = 1 4C5H 1221 IA32_A_PMC4 Full Width Writable IA32_PMC4 Alias (R/W) (If CPUID.0AH: EAX[15:8] > 4) && IA32_PERF_CAPABILITIES[ 13] = 1 4C6H 1222 IA32_A_PMC5 Full Width Writable IA32_PMC5 Alias (R/W) (If CPUID.0AH: EAX[15:8] > 5) && IA32_PERF_CAPABILITIES[ 13] = 1 4C7H 1223 IA32_A_PMC6 Full Width Writable IA32_PMC6 Alias (R/W) (If CPUID.0AH: EAX[15:8] > 6) && IA32_PERF_CAPABILITIES[ 13] = 1 4C8H 1224 IA32_A_PMC7 Full Width Writable IA32_PMC7 Alias (R/W) (If CPUID.0AH: EAX[15:8] > 7) && IA32_PERF_CAPABILITIES[ 13] = 1 4D0H 1232 IA32_MCG_EXT_CTL Allows software to signal some MCEs to only a single logical processor in the system. (R/W) If IA32_MCG_CAP.LMCE_P =1 See Section 15.3.1.4, “IA32_MCG_EXT_CTL MSR”. 500H 2-34 Vol. 4 1280 0 LMCE_EN 63:1 Reserved IA32_SGX_SVN_STATUS Status and SVN Threshold of SGX Support for ACM (RO). If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex 560H Architectural MSR Name / Bit Fields (Former MSR Name) 570H Comment Decimal 1376 0 Lock 15:1 Reserved 23:16 SGX_SVN_SINIT 63:24 Reserved IA32_RTIT_OUTPUT_BASE Trace Output Base Register (R/W) 6:0 Reserved 3-1:7 561H MSR/Bit Description 1377 1392 MAXPHYADDR Base physical address. 63:MAXPHYADDR Reserved IA32_RTIT_OUTPUT_MASK_PTRS Trace Output Mask Pointers Register (R/W) 6:0 Reserved 31:7 MaskOrTableOffset 63:32 Output Offset IA32_RTIT_CTL Trace Control Register (R/W) 0 TraceEn 1 CYCEn 2 OS 3 User 4 PwrEvtEn 5 FUPonPTW 6 FabricEn 7 CR3 filter 8 ToPA 9 MTCEn See Section 41.11.3, “Interactions with Authenticated Code Modules (ACMs)”. See Section 41.11.3, “Interactions with Authenticated Code Modules (ACMs)”. If ((CPUID.(EAX=07H, ECX=0):EBX[25] = 1) && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1) || (CPUID.(EAX=14H,ECX=0): ECX[2] = 1) ) ) If ((CPUID.(EAX=07H, ECX=0):EBX[25] = 1) && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1) || (CPUID.(EAX=14H,ECX=0): ECX[2] = 1) ) ) If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1) If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1) If (CPUID.(EAX=07H, ECX=0):ECX[3] = 1) If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1) Vol. 4 2-35 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex 571H 572H 580H 2-36 Vol. 4 Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 1393 1394 1408 10 TSCEn 11 DisRETC 12 PTWEn 13 BranchEn 17:14 MTCFreq 18 Reserved, must be zero. 22:19 CYCThresh 23 Reserved, must be zero. 27:24 PSBFreq 31:28 Reserved, must be zero. 35:32 ADDR0_CFG If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 0) 39:36 ADDR1_CFG If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 1) 43:40 ADDR2_CFG If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 2) 47:44 ADDR3_CFG If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 3) 63:48 Reserved, must be zero. IA32_RTIT_STATUS Tracing Status Register (R/W) If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1) 0 FilterEn (writes ignored) If (CPUID.(EAX=07H, ECX=0):EBX[2] = 1) 1 ContexEn (writes ignored) 2 TriggerEn (writes ignored) 3 Reserved 4 Error 5 Stopped 31:6 Reserved, must be zero. 48:32 PacketByteCnt 63:49 Reserved IA32_RTIT_CR3_MATCH Trace Filter CR3 Match Register (R/W) 4:0 Reserved 63:5 CR3[63:5] value to match. IA32_RTIT_ADDR0_A Region 0 Start Address (R/W) If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1) If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1) If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1) If (CPUID.(EAX=07H, ECX=0):EBX[1] > 3) If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1) If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 0) MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex 581H 582H 583H 584H 585H 586H 587H 600H Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 1409 1410 1411 1412 1413 1414 1415 1536 47:0 Virtual Address 63:48 SignExt_VA IA32_RTIT_ADDR0_B Region 0 End Address (R/W) 47:0 Virtual Address 63:48 SignExt_VA IA32_RTIT_ADDR1_A Region 1 Start Address (R/W) 47:0 Virtual Address 63:48 SignExt_VA IA32_RTIT_ADDR1_B Region 1 End Address (R/W) 47:0 Virtual Address 63:48 SignExt_VA IA32_RTIT_ADDR2_A Region 2 Start Address (R/W) 47:0 Virtual Address 63:48 SignExt_VA IA32_RTIT_ADDR2_B Region 2 End Address (R/W) 47:0 Virtual Address 63:48 SignExt_VA IA32_RTIT_ADDR3_A Region 3 Start Address (R/W) 47:0 Virtual Address 63:48 SignExt_VA IA32_RTIT_ADDR3_B Region 3 End Address (R/W) 47:0 Virtual Address 63:48 SignExt_VA IA32_DS_AREA DS Save Area (R/W) Points to the linear address of the first byte of the DS buffer management area, which is used to manage the BTS and PEBS buffers. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 0) If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 1) If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 1) If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 2) If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 2) If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 3) If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 3) If( CPUID.01H:EDX.DS[21] =1 See Section 18.6.3.4, “Debug Store (DS) Mechanism.” 63:0 The linear address of the first byte of the DS buffer management area, if IA-32e mode is active. Vol. 4 2-37 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 31:0 The linear address of the first byte of the DS buffer management area, if not in IA32e mode. 63:32 Reserved if not in IA-32e mode. 6E0H 1760 IA32_TSC_DEADLINE TSC Target of Local APIC’s TSC Deadline Mode (R/W) If CPUID.01H:ECX.[24] = 1 770H 1904 IA32_PM_ENABLE Enable/disable HWP (R/W) If CPUID.06H:EAX.[7] = 1 0 HWP_ENABLE (R/W1-Once) If CPUID.06H:EAX.[7] = 1 See Section 14.4.2, “Enabling HWP”. 771H 1905 63:1 Reserved IA32_HWP_CAPABILITIES HWP Performance Range Enumeration (RO) If CPUID.06H:EAX.[7] = 1 7:0 Highest_Performance If CPUID.06H:EAX.[7] = 1 See Section 14.4.3, “HWP Performance Range and Dynamic Capabilities”. 15:8 Guaranteed_Performance If CPUID.06H:EAX.[7] = 1 See Section 14.4.3, “HWP Performance Range and Dynamic Capabilities”. 23:16 Most_Efficient_Performance If CPUID.06H:EAX.[7] = 1 See Section 14.4.3, “HWP Performance Range and Dynamic Capabilities”. 31:24 Lowest_Performance If CPUID.06H:EAX.[7] = 1 See Section 14.4.3, “HWP Performance Range and Dynamic Capabilities”. 772H 1906 63:32 Reserved IA32_HWP_REQUEST_PKG Power Management Control Hints for All Logical Processors in a Package (R/W) If CPUID.06H:EAX.[11] = 1 Minimum_Performance If CPUID.06H:EAX.[11] = 1 7:0 See Section 14.4.4, “Managing HWP”. 15:8 Maximum_Performance If CPUID.06H:EAX.[11] = 1 See Section 14.4.4, “Managing HWP”. 23:16 Desired_Performance If CPUID.06H:EAX.[11] = 1 See Section 14.4.4, “Managing HWP”. 31:24 Energy_Performance_Preference See Section 14.4.4, “Managing HWP”. 41:32 Activity_Window See Section 14.4.4, “Managing HWP”. 773H 2-38 Vol. 4 1907 63:42 Reserved IA32_HWP_INTERRUPT Control HWP Native Interrupts (R/W) If CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[10] = 1 If CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[9] = 1 If CPUID.06H:EAX.[8] = 1 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 0 EN_Guaranteed_Performance_Change If CPUID.06H:EAX.[8] = 1 See Section 14.4.6, “HWP Notifications”. 1 EN_Excursion_Minimum If CPUID.06H:EAX.[8] = 1 See Section 14.4.6, “HWP Notifications”. 774H 1908 63:2 Reserved IA32_HWP_REQUEST Power Management Control Hints to a Logical Processor (R/W) If CPUID.06H:EAX.[7] = 1 Minimum_Performance If CPUID.06H:EAX.[7] = 1 7:0 See Section 14.4.4, “Managing HWP”. 15:8 Maximum_Performance If CPUID.06H:EAX.[7] = 1 See Section 14.4.4, “Managing HWP”. 23:16 Desired_Performance If CPUID.06H:EAX.[7] = 1 See Section 14.4.4, “Managing HWP”. 31:24 Energy_Performance_Preference See Section 14.4.4, “Managing HWP”. 41:32 Activity_Window See Section 14.4.4, “Managing HWP”. 42 Package_Control See Section 14.4.4, “Managing HWP”. 777H 1911 If CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[10] = 1 If CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[9] = 1 If CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[11] = 1 63:43 Reserved IA32_HWP_STATUS Log bits indicating changes to Guaranteed & excursions to Minimum (R/W) If CPUID.06H:EAX.[7] = 1 0 Guaranteed_Performance_Change (R/WC0) If CPUID.06H:EAX.[7] = 1 See Section 14.4.5, “HWP Feedback”. 1 Reserved 2 Excursion_To_Minimum (R/WC0) If CPUID.06H:EAX.[7] = 1 See Section 14.4.5, “HWP Feedback”. 802H 2050 63:3 Reserved IA32_X2APIC_APICID x2APIC ID Register (R/O) See x2APIC Specification. If CPUID.01H:ECX[21] = 1 && IA32_APIC_BASE.[10] =1 803H 2051 IA32_X2APIC_VERSION x2APIC Version Register (R/O) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 808H 2056 IA32_X2APIC_TPR x2APIC Task Priority Register (R/W) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 80AH 2058 IA32_X2APIC_PPR x2APIC Processor Priority Register (R/O) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 Vol. 4 2-39 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 80BH 2059 IA32_X2APIC_EOI x2APIC EOI Register (W/O) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 80DH 2061 IA32_X2APIC_LDR x2APIC Logical Destination Register (R/O) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 80FH 2063 IA32_X2APIC_SIVR x2APIC Spurious Interrupt Vector Register (R/W) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 810H 2064 IA32_X2APIC_ISR0 x2APIC In-Service Register Bits 31:0 (R/O) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 811H 2065 IA32_X2APIC_ISR1 x2APIC In-Service Register Bits 63:32 (R/O) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 812H 2066 IA32_X2APIC_ISR2 x2APIC In-Service Register Bits 95:64 (R/O) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 813H 2067 IA32_X2APIC_ISR3 x2APIC In-Service Register Bits 127:96 (R/O) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 814H 2068 IA32_X2APIC_ISR4 x2APIC In-Service Register Bits 159:128 (R/O) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 815H 2069 IA32_X2APIC_ISR5 x2APIC In-Service Register Bits 191:160 (R/O) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 816H 2070 IA32_X2APIC_ISR6 x2APIC In-Service Register Bits 223:192 (R/O) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 817H 2071 IA32_X2APIC_ISR7 x2APIC In-Service Register Bits 255:224 (R/O) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 818H 2072 IA32_X2APIC_TMR0 x2APIC Trigger Mode Register Bits 31:0 (R/O) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 819H 2073 IA32_X2APIC_TMR1 x2APIC Trigger Mode Register Bits 63:32 (R/O) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 81AH 2074 IA32_X2APIC_TMR2 x2APIC Trigger Mode Register Bits 95:64 (R/O) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 81BH 2075 IA32_X2APIC_TMR3 x2APIC Trigger Mode Register Bits 127:96 (R/O) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 2-40 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 81CH 2076 IA32_X2APIC_TMR4 x2APIC Trigger Mode Register Bits 159:128 (R/O) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 81DH 2077 IA32_X2APIC_TMR5 x2APIC Trigger Mode Register Bits 191:160 (R/O) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 81EH 2078 IA32_X2APIC_TMR6 x2APIC Trigger Mode Register Bits 223:192 (R/O) If ( CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1) 81FH 2079 IA32_X2APIC_TMR7 x2APIC Trigger Mode Register Bits 255:224 (R/O) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 820H 2080 IA32_X2APIC_IRR0 x2APIC Interrupt Request Register Bits 31:0 (R/O) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 821H 2081 IA32_X2APIC_IRR1 x2APIC Interrupt Request Register Bits 63:32 (R/O) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 822H 2082 IA32_X2APIC_IRR2 x2APIC Interrupt Request Register Bits 95:64 (R/O) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 823H 2083 IA32_X2APIC_IRR3 x2APIC Interrupt Request Register Bits 127:96 (R/O) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 824H 2084 IA32_X2APIC_IRR4 x2APIC Interrupt Request Register Bits 159:128 (R/O) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 825H 2085 IA32_X2APIC_IRR5 x2APIC Interrupt Request Register Bits 191:160 (R/O) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 826H 2086 IA32_X2APIC_IRR6 x2APIC Interrupt Request Register Bits 223:192 (R/O) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 827H 2087 IA32_X2APIC_IRR7 x2APIC Interrupt Request Register Bits 255:224 (R/O) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 828H 2088 IA32_X2APIC_ESR x2APIC Error Status Register (R/W) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 82FH 2095 IA32_X2APIC_LVT_CMCI x2APIC LVT Corrected Machine Check Interrupt Register (R/W) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 830H 2096 IA32_X2APIC_ICR x2APIC Interrupt Command Register (R/W) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 Vol. 4 2-41 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 832H 2098 IA32_X2APIC_LVT_TIMER x2APIC LVT Timer Interrupt Register (R/W) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 833H 2099 IA32_X2APIC_LVT_THERMAL x2APIC LVT Thermal Sensor Interrupt Register (R/W) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 834H 2100 IA32_X2APIC_LVT_PMI x2APIC LVT Performance Monitor Interrupt Register (R/W) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 835H 2101 IA32_X2APIC_LVT_LINT0 x2APIC LVT LINT0 Register (R/W) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 836H 2102 IA32_X2APIC_LVT_LINT1 x2APIC LVT LINT1 Register (R/W) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 837H 2103 IA32_X2APIC_LVT_ERROR x2APIC LVT Error Register (R/W) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 838H 2104 IA32_X2APIC_INIT_COUNT x2APIC Initial Count Register (R/W) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 839H 2105 IA32_X2APIC_CUR_COUNT x2APIC Current Count Register (R/O) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 83EH 2110 IA32_X2APIC_DIV_CONF x2APIC Divide Configuration Register (R/W) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 83FH 2111 IA32_X2APIC_SELF_IPI x2APIC Self IPI Register (W/O) If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] =1 C80H 3200 IA32_DEBUG_INTERFACE Silicon Debug Feature Control (R/W) If CPUID.01H:ECX.[11] = 1 0 Enable (R/W) If CPUID.01H:ECX.[11] = 1 BIOS set 1 to enable Silicon debug features. Default is 0. C81H 2-42 Vol. 4 3201 29:1 Reserved 30 Lock (R/W): If 1, locks any further change to the MSR. The lock bit is set automatically on the first SMI assertion even if not explicitly set by BIOS. Default is 0. If CPUID.01H:ECX.[11] = 1 31 Debug Occurred (R/O): This “sticky bit” is set by hardware to indicate the status of bit 0. Default is 0. If CPUID.01H:ECX.[11] = 1 63:32 Reserved IA32_L3_QOS_CFG L3 QOS Configuration (R/W) If ( CPUID.(EAX=10H, ECX=1):ECX.[2] = 1 ) MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 0 Enable (R/W) Set 1 to enable L3 CAT masks and COS to operate in Code and Data Prioritization (CDP) mode. C82H 3202 63:1 Reserved. Attempts to write to reserved bits result in a #GP(0). IA32_L2_QOS_CFG L2 QOS Configuration (R/W) 0 Enable (R/W) If ( CPUID.(EAX=10H, ECX=2):ECX.[2] = 1 ) Set 1 to enable L2 CAT masks and COS to operate in Code and Data Prioritization (CDP) mode. C8DH C8EH C8FH 3213 3214 3215 63:1 Reserved. Attempts to write to reserved bits result in a #GP(0). IA32_QM_EVTSEL Monitoring Event Select Register (R/W) 7:0 Event ID: ID of a supported monitoring event to report via IA32_QM_CTR. 31: 8 Reserved N+31:32 Resource Monitoring ID: ID for monitoring hardware to report monitored data via IA32_QM_CTR. If ( CPUID.(EAX=07H, ECX=0):EBX.[12] = 1 ) N = Ceil (Log2 ( CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)) 63:N+32 Reserved IA32_QM_CTR Monitoring Counter Register (R/O) 61:0 Resource Monitored Data 62 Unavailable: If 1, indicates data for this RMID is not available or not monitored for this resource or RMID. 63 Error: If 1, indicates an unsupported RMID or event type was written to IA32_PQR_QM_EVTSEL. IA32_PQR_ASSOC Resource Association Register (R/W) If ( (CPUID.(EAX=07H, ECX=0):EBX[12] =1) or (CPUID.(EAX=07H, ECX=0):EBX[15] =1 ) ) N-1:0 Resource Monitoring ID (R/W): ID for monitoring hardware to track internal operation, e.g., memory access. N = Ceil (Log2 ( CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)) 31:N Reserved 63:32 COS (R/W): The class of service (COS) to enforce (on writes); returns the current COS when read. If ( CPUID.(EAX=07H, ECX=0):EBX.[12] = 1 ) If ( CPUID.(EAX=07H, ECX=0):EBX.[15] = 1 ) Vol. 4 2-43 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex C90H+ n 3216 Reserved MSR Address Space for CAT Mask Registers See Section 17.19.4.1, “Enumeration and Detection Support of Cache Allocation Technology”. IA32_L3_MASK_0 L3 CAT Mask for COS0 (R/W) 31:0 Capacity Bit Mask (R/W) 63:32 Reserved 3216+n IA32_L3_MASK_n D10H D4FH D10H 3344 DA0H 2-44 Vol. 4 3472 3488 L3 CAT Mask for COSn (R/W) 31:0 Capacity Bit Mask (R/W) 63:32 Reserved Reserved MSR Address Space for L2 CAT Mask Registers See Section 17.19.4.1, “Enumeration and Detection Support of Cache Allocation Technology”. IA32_L2_MASK_0 L2 CAT Mask for COS0 (R/W) 31:0 Capacity Bit Mask (R/W) 63:32 Reserved D10H+ 3344+n IA32_L2_MASK_n n D90H MSR/Bit Description Comment Decimal C90H D8FH C90H Architectural MSR Name / Bit Fields (Former MSR Name) L2 CAT Mask for COSn (R/W) 31:0 Capacity Bit Mask (R/W) 63:32 Reserved IA32_BNDCFGS Supervisor State of MPX Configuration (R/W) 0 EN: Enable Intel MPX in supervisor mode. 1 BNDPRESERVE: Preserve the bounds registers for near branch instructions in the absence of the BND prefix. 11:2 Reserved, must be zero. 63:12 Base Address of Bound Directory. IA32_XSS Extended Supervisor State Mask (R/W) 7:0 Reserved 8 Trace Packet Configuration State (R/W) 63:9 Reserved. If (CPUID.(EAX=10H, ECX=0H):EBX[1] != 0) n = CPUID.(EAX=10H, ECX=1H):EDX[15:0] If (CPUID.(EAX=10H, ECX=0H):EBX[2] != 0) n = CPUID.(EAX=10H, ECX=2H):EDX[15:0] If (CPUID.(EAX=07H, ECX=0H):EBX[14] = 1) If( CPUID.(0DH, 1):EAX.[3] =1 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex DB0H Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Comment Decimal 3504 IA32_PKG_HDC_CTL Package Level Enable/disable HDC (R/W) If CPUID.06H:EAX.[13] = 1 0 HDC_Pkg_Enable (R/W) If CPUID.06H:EAX.[13] = 1 Force HDC idling or wake up HDC-idled logical processors in the package. See Section 14.5.2, “Package level Enabling HDC”. DB1H 3505 63:1 Reserved IA32_PM_CTL1 Enable/disable HWP (R/W) If CPUID.06H:EAX.[13] = 1 0 HDC_Allow_Block (R/W) If CPUID.06H:EAX.[13] = 1 Allow/Block this logical processor for package level HDC control. See Section 14.5.3. DB2H 3506 63:1 Reserved IA32_THREAD_STALL Per-Logical_Processor HDC Idle Residency (R/0) If CPUID.06H:EAX.[13] = 1 Stall_Cycle_Cnt (R/W) If CPUID.06H:EAX.[13] = 1 63:0 Stalled cycles due to HDC forced idle on this logical processor. See Section 14.5.4.1. 4000_ 0000H 4000_ 00FFH Reserved MSR Address Space All existing and future processors will not implement MSRs in this range. C000_ 0080H IA32_EFER Extended Feature Enables 0 SYSCALL Enable: IA32_EFER.SCE (R/W) If ( CPUID.80000001H:EDX.[2 0] || CPUID.80000001H:EDX.[2 9]) Enables SYSCALL/SYSRET instructions in 64-bit mode. 7:1 Reserved 8 IA-32e Mode Enable: IA32_EFER.LME (R/W) Enables IA-32e mode operation. 9 Reserved 10 IA-32e Mode Active: IA32_EFER.LMA (R) Indicates IA-32e mode is active when set. C000_ 0081H 11 Execute Disable Bit Enable: IA32_EFER.NXE (R/W) 63:12 Reserved IA32_STAR System Call Target Address (R/W) If CPUID.80000001:EDX.[29] =1 Vol. 4 2-45 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-2. IA-32 Architectural MSRs (Contd.) Register Address Hex C000_ 0082H Architectural MSR Name / Bit Fields (Former MSR Name) MSR/Bit Description Decimal IA32_LSTAR IA-32e Mode System Call Target Address (R/W) Target RIP for the called procedure when SYSCALL is executed in 64-bit mode. C000_ 0083H Comment IA32_CSTAR IA-32e Mode System Call Target Address (R/W) Not used, as the SYSCALL instruction is not recognized in compatibility mode. If CPUID.80000001:EDX.[29] =1 If CPUID.80000001:EDX.[29] =1 C000_ 0084H IA32_FMASK System Call Flag Mask (R/W) If CPUID.80000001:EDX.[29] =1 C000_ 0100H IA32_FS_BASE Map of BASE Address of FS (R/W) If CPUID.80000001:EDX.[29] =1 C000_ 0101H IA32_GS_BASE Map of BASE Address of GS (R/W) If CPUID.80000001:EDX.[29] =1 C000_ 0102H IA32_KERNEL_GS_BASE Swap Target of BASE Address of GS (R/W) If CPUID.80000001:EDX.[29] =1 C000_ 0103H IA32_TSC_AUX Auxiliary TSC (RW) If CPUID.80000001H: EDX[27] = 1 or CPUID.(EAX=7,ECX=0):ECX [bit 22] = 1 31:0 AUX: Auxiliary signature of TSC. 63:32 Reserved NOTES: 1. In processors based on Intel NetBurst® microarchitecture, MSR addresses 180H-197H are supported, software must treat them as model-specific. Starting with Intel Core Duo processors, MSR addresses 180H-185H, 188H-197H are reserved. 2. The *_ADDR MSRs may or may not be present; this depends on flag settings in IA32_MCi_STATUS. See Section 15.3.2.3 and Section 15.3.2.4 for more information. 3. MAXPHYADDR is reported by CPUID.80000008H:EAX[7:0]. 2.2 MSRS IN THE INTEL® CORE™ 2 PROCESSOR FAMILY Table 2-3 lists model-specific registers (MSRs) for Intel Core 2 processor family and for Intel Xeon processors based on Intel Core microarchitecture, architectural MSR addresses are also included in Table 2-3. These processors have a CPUID signature with DisplayFamily_DisplayModel of 06_0FH, see Table 2-1. MSRs listed in Table 2-2 and Table 2-3 are also supported by processors based on the Enhanced Intel Core microarchitecture. Processors based on the Enhanced Intel Core microarchitecture have the CPUID signature DisplayFamily_DisplayModel of 06_17H. 2-46 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) The column “Shared/Unique” applies to multi-core processors based on Intel Core microarchitecture. “Unique” means each processor core has a separate MSR, or a bit field in an MSR governs only a core independently. “Shared” means the MSR or the bit field in an MSR address governs the operation of both processor cores. Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture Register Address Register Name / Bit Fields Shared/ Unique Bit Description Hex Dec 0H 0 IA32_P5_MC_ADDR Unique See Section 2.23, “MSRs in Pentium Processors.” 1H 1 IA32_P5_MC_TYPE Unique See Section 2.23, “MSRs in Pentium Processors.” 6H 6 IA32_MONITOR_FILTER_SIZE Unique See Section 8.10.5, “Monitor/Mwait Address Range Determination.” and Table 2-2. 10H 16 IA32_TIME_STAMP_COUNTER Unique See Section 17.17, “Time-Stamp Counter,” and see Table 2-2. 17H 23 IA32_PLATFORM_ID Shared Platform ID (R) See Table 2-2. 17H 23 MSR_PLATFORM_ID Shared Model Specific Platform ID (R) 7:0 Reserved 12:8 Maximum Qualified Ratio (R) The maximum allowed bus ratio. 49:13 Reserved 52:50 See Table 2-2. 63:53 Reserved 1BH 27 IA32_APIC_BASE Unique See Section 10.4.4, “Local APIC Status and Location” and Table 2-2. 2AH 42 MSR_EBL_CR_POWERON Shared Processor Hard Power-On Configuration (R/W) Enables and disables processor features; (R) indicates current processor configuration. 0 Reserved 1 Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not all processors implement R/W. 2 Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not all processor implements R/W. 3 MCERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not all processors implement R/W. 4 Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not all processors implement R/W. 5 Reserved 6 Reserved Vol. 4 2-47 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.) Register Address Hex Register Name / Bit Fields Shared/ Unique Bit Description Dec 7 BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not all processors implement R/W. 8 Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled 9 Execute BIST (R/O) 1 = Enabled; 0 = Disabled 10 MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled 11 Intel TXT Capable Chipset. (R/O) 1 = Present; 0 = Not Present 12 BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled 13 Reserved 14 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes 15 Reserved 17:16 APIC Cluster ID (R/O) 18 N/2 Non-Integer Bus Ratio (R/O) 0 = Integer ratio; 1 = Non-integer ratio 3AH 58 19 Reserved 21: 20 Symmetric Arbitration ID (R/O) 26:22 Integer Bus Frequency Ratio (R/O) MSR_FEATURE_CONTROL Unique Control Features in Intel 64 Processor (R/W) See Table 2-2. 3 Unique SMRR Enable (R/WL) When this bit is set and the lock bit is set, this makes the SMRR_PHYS_BASE and SMRR_PHYS_MASK registers read visible and writeable while in SMM. 40H 64 MSR_LASTBRANCH_0_FROM_IP Unique Last Branch Record 0 From IP (R/W) One of four pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction. See also: • Last Branch Record Stack TOS at 1C9H. • Section 17.5. 41H 65 MSR_LASTBRANCH_1_FROM_IP Unique Last Branch Record 1 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 42H 66 MSR_LASTBRANCH_2_FROM_IP Unique Last Branch Record 2 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 2-48 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.) Register Address Hex Dec 43H 67 Register Name / Bit Fields MSR_LASTBRANCH_3_FROM_IP Shared/ Unique Unique Bit Description Last Branch Record 3 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 60H 96 MSR_LASTBRANCH_0_TO_IP Unique Last Branch Record 0 To IP (R/W) One of four pairs of last branch record registers on the last branch record stack. This To_IP part of the stack contains pointers to the destination instruction. 61H 97 MSR_LASTBRANCH_1_TO_IP Unique Last Branch Record 1 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 62H 98 MSR_LASTBRANCH_2_TO_IP Unique Last Branch Record 2 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 63H 99 MSR_LASTBRANCH_3_TO_IP Unique Last Branch Record 3 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 79H 121 IA32_BIOS_UPDT_TRIG Unique BIOS Update Trigger Register (W) See Table 2-2. 8BH 139 IA32_BIOS_SIGN_ID Unique BIOS Update Signature ID (RO) See Table 2-2. A0H 160 MSR_SMRR_PHYSBASE Unique System Management Mode Base Address register (WO in SMM) Model-specific implementation of SMRR-like interface, read visible and write only in SMM. 11:0 Reserved 31:12 PhysBase: SMRR physical Base Address. 63:32 A1H 161 MSR_SMRR_PHYSMASK Reserved Unique System Management Mode Physical Address Mask register (WO in SMM) Model-specific implementation of SMRR-like interface, read visible and write only in SMM. C1H 193 10:0 Reserved 11 Valid: Physical address base and range mask are valid. 31:12 PhysMask: SMRR physical address range mask. 63:32 Reserved IA32_PMC0 Unique Performance Counter Register See Table 2-2. C2H 194 IA32_PMC1 Unique Performance Counter Register See Table 2-2. CDH 205 MSR_FSB_FREQ Shared Scaleable Bus Speed(RO) This field indicates the intended scaleable bus clock speed for processors based on Intel Core microarchitecture. Vol. 4 2-49 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.) Register Address Hex Register Name / Bit Fields Shared/ Unique Bit Description Dec 2:0 • • • • • • 101B: 100 MHz (FSB 400) 001B: 133 MHz (FSB 533) 011B: 167 MHz (FSB 667) 010B: 200 MHz (FSB 800) 000B: 267 MHz (FSB 1067) 100B: 333 MHz (FSB 1333) 133.33 MHz should be utilized if performing calculation with System Bus Speed when encoding is 001B. 166.67 MHz should be utilized if performing calculation with System Bus Speed when encoding is 011B. 266.67 MHz should be utilized if performing calculation with System Bus Speed when encoding is 000B. 333.33 MHz should be utilized if performing calculation with System Bus Speed when encoding is 100B. 63:3 CDH 205 MSR_FSB_FREQ Reserved Shared Scaleable Bus Speed(RO) This field indicates the intended scaleable bus clock speed for processors based on Enhanced Intel Core microarchitecture. 2:0 • • • • • • • 101B: 100 MHz (FSB 400) 001B: 133 MHz (FSB 533) 011B: 167 MHz (FSB 667) 010B: 200 MHz (FSB 800) 000B: 267 MHz (FSB 1067) 100B: 333 MHz (FSB 1333) 110B: 400 MHz (FSB 1600) 133.33 MHz should be utilized if performing calculation with System Bus Speed when encoding is 001B. 166.67 MHz should be utilized if performing calculation with System Bus Speed when encoding is 011B. 266.67 MHz should be utilized if performing calculation with System Bus Speed when encoding is 110B. 333.33 MHz should be utilized if performing calculation with System Bus Speed when encoding is 111B. 63:3 Reserved E7H 231 IA32_MPERF Unique E8H 232 IA32_APERF Unique Maximum Performance Frequency Clock Count (RW) See Table 2-2. Actual Performance Frequency Clock Count (RW) See Table 2-2. FEH 254 IA32_MTRRCAP Unique See Table 2-2. 11 Unique SMRR Capability Using MSR 0A0H and 0A1H (R) 174H 372 IA32_SYSENTER_CS Unique See Table 2-2. 175H 373 IA32_SYSENTER_ESP Unique See Table 2-2. 2-50 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.) Register Address Hex Register Name / Bit Fields Shared/ Unique Bit Description Dec 176H 374 IA32_SYSENTER_EIP Unique See Table 2-2. 179H 377 IA32_MCG_CAP Unique See Table 2-2. 17AH 378 IA32_MCG_STATUS Unique Global Machine Check Status 0 RIPV When set, bit indicates that the instruction addressed by the instruction pointer pushed on the stack (when the machine check was generated) can be used to restart the program. If cleared, the program cannot be reliably restarted. 1 EIPV When set, bit indicates that the instruction addressed by the instruction pointer pushed on the stack (when the machine check was generated) is directly associated with the error. 2 MCIP When set, bit indicates that a machine check has been generated. If a second machine check is detected while this bit is still set, the processor enters a shutdown state. Software should write this bit to 0 after processing a machine check exception. 63:3 Reserved 186H 390 IA32_PERFEVTSEL0 Unique See Table 2-2. 187H 391 IA32_PERFEVTSEL1 Unique See Table 2-2. 198H 408 IA32_PERF_STATUS Shared See Table 2-2. 198H 408 MSR_PERF_STATUS Shared Current performance status. See Section 14.1.1, “Software Interface For Initiating Performance State Transitions”. 15:0 Current Performance State Value 30:16 Reserved 31 XE Operation (R/O). If set, XE operation is enabled. Default is cleared. 39:32 Reserved 44:40 Maximum Bus Ratio (R/O) Indicates maximum bus ratio configured for the processor. 45 Reserved 46 Non-Integer Bus Ratio (R/O) Indicates non-integer bus ratio is enabled. Applies processors based on Enhanced Intel Core microarchitecture. 63:47 199H 409 IA32_PERF_CTL Reserved Unique See Table 2-2. Vol. 4 2-51 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.) Register Address Hex Dec 19AH 410 Register Name / Bit Fields IA32_CLOCK_MODULATION Shared/ Unique Unique Bit Description Clock Modulation (R/W) See Table 2-2. IA32_CLOCK_MODULATION MSR was originally named IA32_THERM_CONTROL MSR. 19BH 411 IA32_THERM_INTERRUPT Unique Thermal Interrupt Control (R/W) See Table 2-2. 19CH 412 IA32_THERM_STATUS Unique Thermal Monitor Status (R/W) See Table 2-2. 19DH 413 MSR_THERM2_CTL Unique Thermal Monitor 2 Control 15:0 Reserved 16 TM_SELECT (R/W) Mode of automatic thermal monitor: 0 = Thermal Monitor 1 (thermally-initiated on-die modulation of the stop-clock duty cycle). 1 = Thermal Monitor 2 (thermally-initiated frequency transitions). If bit 3 of the IA32_MISC_ENABLE register is cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled. 63:16 1A0H 416 Reserved IA32_MISC_ENABLE Enable Misc. Processor Features (R/W) Allows a variety of processor functions to be enabled and disabled. 0 Fast-Strings Enable See Table 2-2. 2:1 3 Reserved Unique Automatic Thermal Control Circuit Enable (R/W) See Table 2-2. 6:4 7 Reserved Shared Performance Monitoring Available (R) See Table 2-2. 8 9 Reserved Hardware Prefetcher Disable (R/W) When set, disables the hardware prefetcher operation on streams of data. When clear (default), enables the prefetch queue. Disabling of the hardware prefetcher may impact processor performance. 2-52 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.) Register Address Hex Register Name / Bit Fields Shared/ Unique Bit Description Dec 10 Shared FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by the processor to indicate a pending break event within the processor. 0 = Indicates compatible FERR# signaling behavior. This bit must be set to 1 to support XAPIC interrupt model usage. 11 Shared Branch Trace Storage Unavailable (RO) See Table 2-2. 12 Shared Processor Event Based Sampling Unavailable (RO) See Table 2-2. 13 Shared TM2 Enable (R/W) When this bit is set (1) and the thermal sensor indicates that the die temperature is at the pre-determined threshold, the Thermal Monitor 2 mechanism is engaged. TM2 will reduce the bus to core ratio and voltage according to the value last written to MSR_THERM2_CTL bits 15:0. When this bit is clear (0, default), the processor does not change the VID signals or the bus to core ratio when the processor enters a thermally managed state. The BIOS must enable this feature if the TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is not set, this feature is not supported and BIOS must not alter the contents of the TM2 bit location. The processor is operating out of specification if both this bit and the TM1 bit are set to 0. 15:14 16 Reserved Shared Enhanced Intel SpeedStep Technology Enable (R/W) See Table 2-2. 18 Shared ENABLE MONITOR FSM (R/W) See Table 2-2. 19 Shared Adjacent Cache Line Prefetch Disable (R/W) When set to 1, the processor fetches the cache line that contains data currently required by the processor. When set to 0, the processor fetches cache lines that comprise a cache line pair (128 bytes). Single processor platforms should not set this bit. Server platforms should set or clear this bit based on platform performance observed in validation and testing. BIOS may contain a setup option that controls the setting of this bit. Vol. 4 2-53 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.) Register Address Hex Register Name / Bit Fields Shared/ Unique Bit Description Dec 20 Shared Enhanced Intel SpeedStep Technology Select Lock (R/WO) When set, this bit causes the following bits to become read-only: • Enhanced Intel SpeedStep Technology Select Lock (this bit). • Enhanced Intel SpeedStep Technology Enable bit. The bit must be set before an Enhanced Intel SpeedStep Technology transition is requested. This bit is cleared on reset. 21 22 Reserved Shared Limit CPUID Maxval (R/W) See Table 2-2. 23 Shared xTPR Message Disable (R/W) See Table 2-2. 33:24 34 Reserved Unique XD Bit Disable (R/W) See Table 2-2. 36:35 37 Reserved Unique DCU Prefetcher Disable (R/W) When set to 1, the DCU L1 data cache prefetcher is disabled. The default value after reset is 0. BIOS may write ‘1’ to disable this feature. The DCU prefetcher is an L1 data cache prefetcher. When the DCU prefetcher detects multiple loads from the same line done within a time limit, the DCU prefetcher assumes the next line will be required. The next line is prefetched in to the L1 data cache from memory or L2. 38 Shared IDA Disable (R/W) When set to 1 on processors that support IDA, the Intel Dynamic Acceleration feature (IDA) is disabled and the IDA_Enable feature flag will be cleared (CPUID.06H: EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H: EAX[1] reports the processor’s support of IDA is enabled. Note: The power-on default value is used by BIOS to detect hardware support of IDA. If the power-on default value is 1, IDA is available in the processor. If the poweron default value is 0, IDA is not available. 2-54 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.) Register Address Hex Register Name / Bit Fields Shared/ Unique Bit Description Dec 39 Unique IP Prefetcher Disable (R/W) When set to 1, the IP prefetcher is disabled. The default value after reset is 0. BIOS may write ‘1’ to disable this feature. The IP prefetcher is an L1 data cache prefetcher. The IP prefetcher looks for sequential load history to determine whether to prefetch the next expected data into the L1 cache from memory or L2. 63:40 1C9H 457 MSR_LASTBRANCH_TOS Reserved Unique Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) that points to the MSR containing the most recent branch record. See MSR_LASTBRANCH_0_FROM_IP (at 40H). 1D9H 473 IA32_DEBUGCTL Unique 1DDH 477 MSR_LER_FROM_LIP Unique Debug Control (R/W) See Table 2-2. Last Exception Record From Linear IP (R/W) Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled. 1DEH 478 MSR_LER_TO_LIP Unique Last Exception Record To Linear IP (R/W) This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled. 200H 512 IA32_MTRR_PHYSBASE0 Unique See Table 2-2. 201H 513 IA32_MTRR_PHYSMASK0 Unique See Table 2-2. 202H 514 IA32_MTRR_PHYSBASE1 Unique See Table 2-2. 203H 515 IA32_MTRR_PHYSMASK1 Unique See Table 2-2. 204H 516 IA32_MTRR_PHYSBASE2 Unique See Table 2-2. 205H 517 IA32_MTRR_PHYSMASK2 Unique See Table 2-2. 206H 518 IA32_MTRR_PHYSBASE3 Unique See Table 2-2. 207H 519 IA32_MTRR_PHYSMASK3 Unique See Table 2-2. 208H 520 IA32_MTRR_PHYSBASE4 Unique See Table 2-2. 209H 521 IA32_MTRR_PHYSMASK4 Unique See Table 2-2. 20AH 522 IA32_MTRR_PHYSBASE5 Unique See Table 2-2. 20BH 523 IA32_MTRR_PHYSMASK5 Unique See Table 2-2. 20CH 524 IA32_MTRR_PHYSBASE6 Unique See Table 2-2. 20DH 525 IA32_MTRR_PHYSMASK6 Unique See Table 2-2. 20EH 526 IA32_MTRR_PHYSBASE7 Unique See Table 2-2. 20FH 527 IA32_MTRR_PHYSMASK7 Unique See Table 2-2. Vol. 4 2-55 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.) Register Address Register Name / Bit Fields Shared/ Unique Bit Description Hex Dec 250H 592 IA32_MTRR_FIX64K_00000 Unique See Table 2-2. 258H 600 IA32_MTRR_FIX16K_80000 Unique See Table 2-2. 259H 601 IA32_MTRR_FIX16K_A0000 Unique See Table 2-2. 268H 616 IA32_MTRR_FIX4K_C0000 Unique See Table 2-2. 269H 617 IA32_MTRR_FIX4K_C8000 Unique See Table 2-2. 26AH 618 IA32_MTRR_FIX4K_D0000 Unique See Table 2-2. 26BH 619 IA32_MTRR_FIX4K_D8000 Unique See Table 2-2. 26CH 620 IA32_MTRR_FIX4K_E0000 Unique See Table 2-2. 26DH 621 IA32_MTRR_FIX4K_E8000 Unique See Table 2-2. 26EH 622 IA32_MTRR_FIX4K_F0000 Unique See Table 2-2. 26FH 623 IA32_MTRR_FIX4K_F8000 Unique See Table 2-2. 277H 631 IA32_PAT Unique See Table 2-2. 2FFH 767 IA32_MTRR_DEF_TYPE Unique Default Memory Types (R/W) See Table 2-2. 309H 777 IA32_FIXED_CTR0 Unique Fixed-Function Performance Counter Register 0 (R/W) See Table 2-2. 30AH 778 IA32_FIXED_CTR1 Unique 30BH 779 IA32_FIXED_CTR2 Unique Fixed-Function Performance Counter Register 1 (R/W) See Table 2-2. Fixed-Function Performance Counter Register 2 (R/W) See Table 2-2. 345H 837 IA32_PERF_CAPABILITIES Unique See Table 2-2. See Section 17.4.1, “IA32_DEBUGCTL MSR.” 345H 837 MSR_PERF_CAPABILITIES Unique RO. This applies to processors that do not support architectural perfmon version 2. 38DH 909 5:0 LBR Format. See Table 2-2. 6 PEBS Record Format 7 PEBSSaveArchRegs. See Table 2-2. 63:8 Reserved IA32_FIXED_CTR_CTRL Unique Fixed-Function-Counter Control Register (R/W) See Table 2-2. 38EH 910 IA32_PERF_GLOBAL_STATUS Unique See Table 2-2. See Section 18.6.2.2, “Global Counter Control Facilities.” 38EH 910 MSR_PERF_GLOBAL_STATUS Unique See Section 18.6.2.2, “Global Counter Control Facilities.” 38FH 911 IA32_PERF_GLOBAL_CTRL Unique See Table 2-2. See Section 18.6.2.2, “Global Counter Control Facilities.” 38FH 911 MSR_PERF_GLOBAL_CTRL Unique See Section 18.6.2.2, “Global Counter Control Facilities.” 2-56 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.) Register Address Register Name / Bit Fields Shared/ Unique Bit Description Hex Dec 390H 912 IA32_PERF_GLOBAL_OVF_CTRL Unique See Table 2-2. See Section 18.6.2.2, “Global Counter Control Facilities.” 390H 912 MSR_PERF_GLOBAL_OVF_CTRL Unique See Section 18.6.2.2, “Global Counter Control Facilities.” 3F1H 1009 MSR_PEBS_ENABLE Unique See Table 2-2. See Section 18.6.2.4, “Processor Event Based Sampling (PEBS).” 0 Enable PEBS on IA32_PMC0. (R/W) 400H 1024 IA32_MC0_CTL Unique See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 401H 1025 IA32_MC0_STATUS Unique See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 402H 1026 IA32_MC0_ADDR Unique See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” The IA32_MC0_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC0_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 404H 1028 IA32_MC1_CTL Unique See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 405H 1029 IA32_MC1_STATUS Unique See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 406H 1030 IA32_MC1_ADDR Unique See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” The IA32_MC1_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC1_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 408H 1032 IA32_MC2_CTL Unique See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 409H 1033 IA32_MC2_STATUS Unique See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 40AH 1034 IA32_MC2_ADDR Unique See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” The IA32_MC2_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC2_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 40CH 1036 IA32_MC4_CTL Unique See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 40DH 1037 IA32_MC4_STATUS Unique See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 40EH 1038 IA32_MC4_ADDR Unique See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” The MSR_MC4_ADDR register is either not implemented or contains no address if the ADDRV flag in the MSR_MC4_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. Vol. 4 2-57 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.) Register Address Hex Dec Register Name / Bit Fields Shared/ Unique Bit Description 410H 1040 IA32_MC3_CTL See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 411H 1041 IA32_MC3_STATUS See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 412H 1042 IA32_MC3_ADDR Unique See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” The MSR_MC3_ADDR register is either not implemented or contains no address if the ADDRV flag in the MSR_MC3_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 413H 1043 IA32_MC3_MISC Unique Machine Check Error Reporting Register: Contains additional information describing the machine-check error if the MISCV flag in the IA32_MCi_STATUS register is set. 414H 1044 IA32_MC5_CTL Unique Machine Check Error Reporting Register: Controls signaling of #MC for errors produced by a particular hardware unit (or group of hardware units). 415H 1045 IA32_MC5_STATUS Unique Machine Check Error Reporting Register: Contains information related to a machine-check error if its VAL (valid) flag is set. Software is responsible for clearing IA32_MCi_STATUS MSRs by explicitly writing 0s to them; writing 1s to them causes a general-protection exception. 416H 1046 IA32_MC5_ADDR Unique Machine Check Error Reporting Register: Contains the address of the code or data memory location that produced the machine-check error if the ADDRV flag in the IA32_MCi_STATUS register is set. 417H 1047 IA32_MC5_MISC Unique Machine Check Error Reporting Register: Contains additional information describing the machine-check error if the MISCV flag in the IA32_MCi_STATUS register is set. 419H 1045 IA32_MC6_STATUS Unique Applies to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 23. 480H 1152 IA32_VMX_BASIC Unique Reporting Register of Basic VMX Capabilities (R/O) See Table 2-2. See Appendix A.1, “Basic VMX Information.” 481H 1153 IA32_VMX_PINBASED_CTLS Unique Capability Reporting Register of Pin-Based VM-Execution Controls (R/O) See Table 2-2. See Appendix A.3, “VM-Execution Controls.” 482H 1154 IA32_VMX_PROCBASED_CTLS Unique Capability Reporting Register of Primary Processor-Based VM-Execution Controls (R/O) See Appendix A.3, “VM-Execution Controls.” 483H 1155 IA32_VMX_EXIT_CTLS Unique Capability Reporting Register of VM-Exit Controls (R/O) See Table 2-2. See Appendix A.4, “VM-Exit Controls.” 2-58 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.) Register Address Hex Dec 484H 1156 Register Name / Bit Fields IA32_VMX_ENTRY_CTLS Shared/ Unique Unique Bit Description Capability Reporting Register of VM-Entry Controls (R/O) See Table 2-2. See Appendix A.5, “VM-Entry Controls.” 485H 1157 IA32_VMX_MISC Unique Reporting Register of Miscellaneous VMX Capabilities (R/O) See Table 2-2. See Appendix A.6, “Miscellaneous Data.” 486H 1158 IA32_VMX_CR0_FIXED0 Unique Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Table 2-2. See Appendix A.7, “VMX-Fixed Bits in CR0.” 487H 1159 IA32_VMX_CR0_FIXED1 Unique Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Table 2-2. See Appendix A.7, “VMX-Fixed Bits in CR0.” 488H 1160 IA32_VMX_CR4_FIXED0 Unique Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Table 2-2. See Appendix A.8, “VMX-Fixed Bits in CR4.” 489H 1161 IA32_VMX_CR4_FIXED1 Unique Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) See Table 2-2. See Appendix A.8, “VMX-Fixed Bits in CR4.” 48AH 1162 IA32_VMX_VMCS_ENUM Unique Capability Reporting Register of VMCS Field Enumeration (R/O) See Table 2-2. See Appendix A.9, “VMCS Enumeration.” 48BH 1163 IA32_VMX_PROCBASED_CTLS2 Unique Capability Reporting Register of Secondary ProcessorBased VM-Execution Controls (R/O) See Appendix A.3, “VM-Execution Controls.” 600H 1536 IA32_DS_AREA Unique DS Save Area (R/W) See Table 2-2. See Section 18.6.3.4, “Debug Store (DS) Mechanism.” 107CC H MSR_EMON_L3_CTR_CTL0 107CD H MSR_EMON_L3_CTR_CTL1 107CE H MSR_EMON_L3_CTR_CTL2 Unique GBUSQ Event Control/Counter Register (R/W) Applies to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 17.2.2 Unique GBUSQ Event Control/Counter Register (R/W) Applies to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 17.2.2 Unique GSNPQ Event Control/Counter Register (R/W) Applies to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 17.2.2 Vol. 4 2-59 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.) Register Address Hex Register Name / Bit Fields Bit Description Dec 107CF H MSR_EMON_L3_CTR_CTL3 107D0 H MSR_EMON_L3_CTR_CTL4 107D1 H MSR_EMON_L3_CTR_CTL5 107D2 H MSR_EMON_L3_CTR_CTL6 107D3 H MSR_EMON_L3_CTR_CTL7 107D8 H MSR_EMON_L3_GL_CTL C000_ 0080H IA32_EFER C000_ 0081H IA32_STAR C000_ 0082H IA32_LSTAR C000_ 0084H IA32_FMASK C000_ 0100H IA32_FS_BASE C000_ 0101H IA32_GS_BASE C000_ 0102H IA32_KERNEL_GS_BASE 2.3 Shared/ Unique Unique GSNPQ Event Control/Counter Register (R/W) Applies to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 17.2.2 Unique FSB Event Control/Counter Register (R/W) Applies to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 17.2.2 Unique FSB Event Control/Counter Register (R/W) Applies to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 17.2.2 Unique FSB Event Control/Counter Register (R/W) Applies to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 17.2.2 Unique FSB Event Control/Counter Register (R/W) Applies to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 17.2.2 Unique L3/FSB Common Control Register (R/W) Applies to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 17.2.2 Unique Extended Feature Enables See Table 2-2. Unique System Call Target Address (R/W) See Table 2-2. Unique IA-32e Mode System Call Target Address (R/W) See Table 2-2. Unique System Call Flag Mask (R/W) See Table 2-2. Unique Map of BASE Address of FS (R/W) See Table 2-2. Unique Map of BASE Address of GS (R/W) See Table 2-2. Unique Swap Target of BASE Address of GS (R/W) See Table 2-2. MSRS IN THE 45 NM AND 32 NM INTEL® ATOM™ PROCESSOR FAMILY Table 2-4 lists model-specific registers (MSRs) for 45 nm and 32 nm Intel Atom processors, architectural MSR addresses are also included in Table 2-4. These processors have a CPUID signature with DisplayFamily_DisplayModel of 06_1CH, 06_26H, 06_27H, 06_35H and 06_36H; see Table 2-1. The column “Shared/Unique” applies to logical processors sharing the same core in processors based on the Intel Atom microarchitecture. “Unique” means each logical processor has a separate MSR, or a bit field in an MSR 2-60 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) governs only a logical processor. “Shared” means the MSR or the bit field in an MSR address governs the operation of both logical processors in the same core. Table 2-4. MSRs in 45 nm and 32 nm Intel® Atom™ Processor Family Register Address Register Name / Bit Fields Shared/ Unique Bit Description Hex Dec 0H 0 IA32_P5_MC_ADDR Shared See Section 2.23, “MSRs in Pentium Processors.” 1H 1 IA32_P5_MC_TYPE Shared See Section 2.23, “MSRs in Pentium Processors.” 6H 6 IA32_MONITOR_FILTER_ SIZE Unique See Section 8.10.5, “Monitor/Mwait Address Range Determination.” and Table 2-2. 10H 16 IA32_TIME_STAMP_ COUNTER Unique See Section 17.17, “Time-Stamp Counter,” and see Table 2-2. 17H 23 IA32_PLATFORM_ID Shared Platform ID (R) See Table 2-2. 17H 23 MSR_PLATFORM_ID Shared Model Specific Platform ID (R) 7:0 Reserved 12:8 Maximum Qualified Ratio (R) The maximum allowed bus ratio. 63:13 Reserved 1BH 27 IA32_APIC_BASE Unique See Section 10.4.4, “Local APIC Status and Location” and Table 2-2. 2AH 42 MSR_EBL_CR_POWERON Shared Processor Hard Power-On Configuration (R/W) Enables and disables processor features; (R) indicates current processor configuration. 0 Reserved 1 Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled Always 0. 2 Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled Always 0. 3 AERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Always 0. 4 BERR# Enable for initiator bus requests (R/W) 1 = Enabled; 0 = Disabled Always 0. 5 Reserved 6 Reserved 7 BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Always 0. 8 Reserved Vol. 4 2-61 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-4. MSRs in 45 nm and 32 nm Intel® Atom™ Processor Family (Contd.) Register Address Hex Register Name / Bit Fields Shared/ Unique Bit Description Dec 9 Execute BIST (R/O) 1 = Enabled; 0 = Disabled 10 AERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled Always 0. 11 Reserved 12 BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled Always 0. 13 Reserved 14 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes 15 Reserved 17:16 APIC Cluster ID (R/O) Always 00B. 19: 18 Reserved 21: 20 Symmetric Arbitration ID (R/O) Always 00B. 26:22 3AH 58 IA32_FEATURE_CONTROL Integer Bus Frequency Ratio (R/O) Unique Control Features in Intel 64Processor (R/W) See Table 2-2. 40H 64 MSR_LASTBRANCH_0_FROM_IP Unique Last Branch Record 0 From IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: • Last Branch Record Stack TOS at 1C9H. • Section 17.5. 41H 65 MSR_LASTBRANCH_1_FROM_IP Unique Last Branch Record 1 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 42H 66 MSR_LASTBRANCH_2_FROM_IP Unique Last Branch Record 2 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 43H 67 MSR_LASTBRANCH_3_FROM_IP Unique Last Branch Record 3 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 44H 68 MSR_LASTBRANCH_4_FROM_IP Unique Last Branch Record 4 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 45H 69 MSR_LASTBRANCH_5_FROM_IP Unique Last Branch Record 5 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 46H 70 MSR_LASTBRANCH_6_FROM_IP Unique Last Branch Record 6 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 2-62 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-4. MSRs in 45 nm and 32 nm Intel® Atom™ Processor Family (Contd.) Register Address Hex Dec 47H 71 Register Name / Bit Fields MSR_LASTBRANCH_7_FROM_IP Shared/ Unique Unique Bit Description Last Branch Record 7 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 60H 96 MSR_LASTBRANCH_0_TO_IP Unique Last Branch Record 0 To IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the destination instruction. 61H 97 MSR_LASTBRANCH_1_TO_IP Unique Last Branch Record 1 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 62H 98 MSR_LASTBRANCH_2_TO_IP Unique Last Branch Record 2 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 63H 99 MSR_LASTBRANCH_3_TO_IP Unique Last Branch Record 3 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 64H 100 MSR_LASTBRANCH_4_TO_IP Unique Last Branch Record 4 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 65H 101 MSR_LASTBRANCH_5_TO_IP Unique Last Branch Record 5 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 66H 102 MSR_LASTBRANCH_6_TO_IP Unique Last Branch Record 6 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 67H 103 MSR_LASTBRANCH_7_TO_IP Unique Last Branch Record 7 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 79H 121 IA32_BIOS_UPDT_TRIG Shared BIOS Update Trigger Register (W) See Table 2-2. 8BH 139 IA32_BIOS_SIGN_ID Unique BIOS Update Signature ID (RO) See Table 2-2. C1H 193 IA32_PMC0 Unique Performance counter register See Table 2-2. C2H 194 IA32_PMC1 Unique Performance Counter Register See Table 2-2. CDH 205 MSR_FSB_FREQ Shared Scaleable Bus Speed(RO) This field indicates the intended scaleable bus clock speed for processors based on Intel Atom microarchitecture. 2:0 • • • • 111B: 083 MHz (FSB 333) 101B: 100 MHz (FSB 400) 001B: 133 MHz (FSB 533) 011B: 167 MHz (FSB 667) 133.33 MHz should be utilized if performing calculation with System Bus Speed when encoding is 001B. 166.67 MHz should be utilized if performing calculation with System Bus Speed when encoding is 011B. 63:3 Reserved Vol. 4 2-63 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-4. MSRs in 45 nm and 32 nm Intel® Atom™ Processor Family (Contd.) Register Address Hex Dec E7H 231 Register Name / Bit Fields IA32_MPERF Shared/ Unique Unique Bit Description Maximum Performance Frequency Clock Count (RW) See Table 2-2. E8H 232 IA32_APERF Unique Actual Performance Frequency Clock Count (RW) See Table 2-2. FEH 254 IA32_MTRRCAP Shared Memory Type Range Register (R) See Table 2-2. 11EH 281 MSR_BBL_CR_CTL3 Shared Control Register 3 Used to configure the L2 Cache. 0 L2 Hardware Enabled (RO) 1 = Indicates the L2 is hardware-enabled. 0 = Indicates the L2 is hardware-disabled. 7:1 Reserved 8 L2 Enabled (R/W) 1 = L2 cache has been initialized. 0 = Disabled (default). Until this bit is set, the processor will not respond to the WBINVD instruction or the assertion of the FLUSH# input. 22:9 Reserved 23 L2 Not Present (RO) 0 = L2 Present 1 = L2 Not Present 63:24 Reserved 174H 372 IA32_SYSENTER_CS Unique See Table 2-2. 175H 373 IA32_SYSENTER_ESP Unique See Table 2-2. 176H 374 IA32_SYSENTER_EIP Unique See Table 2-2. 179H 377 IA32_MCG_CAP Unique See Table 2-2. 17AH 378 IA32_MCG_STATUS Unique Global Machine Check Status 0 RIPV When set, bit indicates that the instruction addressed by the instruction pointer pushed on the stack (when the machine check was generated) can be used to restart the program. If cleared, the program cannot be reliably restarted. 1 EIPV When set, bit indicates that the instruction addressed by the instruction pointer pushed on the stack (when the machine check was generated) is directly associated with the error. 2-64 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-4. MSRs in 45 nm and 32 nm Intel® Atom™ Processor Family (Contd.) Register Address Hex Register Name / Bit Fields Shared/ Unique Bit Description Dec 2 MCIP When set, bit indicates that a machine check has been generated. If a second machine check is detected while this bit is still set, the processor enters a shutdown state. Software should write this bit to 0 after processing a machine check exception. 63:3 Reserved 186H 390 IA32_PERFEVTSEL0 Unique See Table 2-2. 187H 391 IA32_PERFEVTSEL1 Unique See Table 2-2. 198H 408 IA32_PERF_STATUS Shared See Table 2-2. 198H 408 MSR_PERF_STATUS Shared Performance Status 15:0 Current Performance State Value 39:16 Reserved 44:40 Maximum Bus Ratio (R/O) Indicates maximum bus ratio configured for the processor. 63:45 Reserved 199H 409 IA32_PERF_CTL Unique See Table 2-2. 19AH 410 IA32_CLOCK_MODULATION Unique Clock Modulation (R/W) See Table 2-2. IA32_CLOCK_MODULATION MSR was originally named IA32_THERM_CONTROL MSR. 19BH 411 IA32_THERM_INTERRUPT Unique 19CH 412 IA32_THERM_STATUS Unique Thermal Interrupt Control (R/W) See Table 2-2. Thermal Monitor Status (R/W) See Table 2-2. 19DH 413 MSR_THERM2_CTL Shared Thermal Monitor 2 Control 15:0 Reserved 16 TM_SELECT (R/W) Mode of automatic thermal monitor: 0 = Thermal Monitor 1 (thermally-initiated on-die modulation of the stop-clock duty cycle). 1 = Thermal Monitor 2 (thermally-initiated frequency transitions). If bit 3 of the IA32_MISC_ENABLE register is cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled. 63:17 1A0H 416 IA32_MISC_ENABLE Reserved Unique Enable Misc. Processor Features (R/W) Allows a variety of processor functions to be enabled and disabled. 0 Fast-Strings Enable See Table 2-2. Vol. 4 2-65 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-4. MSRs in 45 nm and 32 nm Intel® Atom™ Processor Family (Contd.) Register Address Hex Register Name / Bit Fields Shared/ Unique Bit Description Dec 2:1 3 Reserved Unique Automatic Thermal Control Circuit Enable (R/W) See Table 2-2. Default value is 0. 6:4 7 Reserved Shared Performance Monitoring Available (R) See Table 2-2. 8 Reserved 9 Reserved 10 Shared FERR# Multiplexing Enable (R/W) 1= FERR# asserted by the processor to indicate a pending break event within the processor. 0 = Indicates compatible FERR# signaling behavior. This bit must be set to 1 to support XAPIC interrupt model usage. 11 Shared Branch Trace Storage Unavailable (RO) See Table 2-2. 12 Shared Processor Event Based Sampling Unavailable (RO) See Table 2-2. 13 Shared TM2 Enable (R/W) When this bit is set (1) and the thermal sensor indicates that the die temperature is at the pre-determined threshold, the Thermal Monitor 2 mechanism is engaged. TM2 will reduce the bus to core ratio and voltage according to the value last written to MSR_THERM2_CTL bits 15:0. When this bit is cleared (0, default), the processor does not change the VID signals or the bus to core ratio when the processor enters a thermally managed state. The BIOS must enable this feature if the TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is not set, this feature is not supported and BIOS must not alter the contents of the TM2 bit location. The processor is operating out of specification if both this bit and the TM1 bit are set to 0. 15:14 16 Reserved Shared Enhanced Intel SpeedStep Technology Enable (R/W) See Table 2-2. 18 Shared ENABLE MONITOR FSM (R/W) See Table 2-2. 19 2-66 Vol. 4 Reserved MODEL-SPECIFIC REGISTERS (MSRS) Table 2-4. MSRs in 45 nm and 32 nm Intel® Atom™ Processor Family (Contd.) Register Address Hex Register Name / Bit Fields Shared/ Unique Bit Description Dec 20 Shared Enhanced Intel SpeedStep Technology Select Lock (R/WO) When set, this bit causes the following bits to become read-only: • Enhanced Intel SpeedStep Technology Select Lock (this bit). • Enhanced Intel SpeedStep Technology Enable bit. The bit must be set before an Enhanced Intel SpeedStep Technology transition is requested. This bit is cleared on reset. 21 22 Reserved Unique Limit CPUID Maxval (R/W) See Table 2-2. 23 Shared xTPR Message Disable (R/W) See Table 2-2. 33:24 34 Reserved Unique XD Bit Disable (R/W) See Table 2-2. 63:35 1C9H 457 MSR_LASTBRANCH_TOS Reserved Unique Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2) that points to the MSR containing the most recent branch record. See MSR_LASTBRANCH_0_FROM_IP (at 40H). 1D9H 473 IA32_DEBUGCTL Unique Debug Control (R/W) See Table 2-2. 1DDH 477 MSR_LER_FROM_LIP Unique Last Exception Record From Linear IP (R) Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled. 1DEH 478 MSR_LER_TO_LIP Unique Last Exception Record To Linear IP (R) This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled. 200H 512 IA32_MTRR_PHYSBASE0 Shared See Table 2-2. 201H 513 IA32_MTRR_PHYSMASK0 Shared See Table 2-2. 202H 514 IA32_MTRR_PHYSBASE1 Shared See Table 2-2. 203H 515 IA32_MTRR_PHYSMASK1 Shared See Table 2-2. 204H 516 IA32_MTRR_PHYSBASE2 Shared See Table 2-2. 205H 517 IA32_MTRR_PHYSMASK2 Shared See Table 2-2. 206H 518 IA32_MTRR_PHYSBASE3 Shared See Table 2-2. 207H 519 IA32_MTRR_PHYSMASK3 Shared See Table 2-2. Vol. 4 2-67 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-4. MSRs in 45 nm and 32 nm Intel® Atom™ Processor Family (Contd.) Register Address Register Name / Bit Fields Shared/ Unique Bit Description Hex Dec 208H 520 IA32_MTRR_PHYSBASE4 Shared See Table 2-2. 209H 521 IA32_MTRR_PHYSMASK4 Shared See Table 2-2. 20AH 522 IA32_MTRR_PHYSBASE5 Shared See Table 2-2. 20BH 523 IA32_MTRR_PHYSMASK5 Shared See Table 2-2. 20CH 524 IA32_MTRR_PHYSBASE6 Shared See Table 2-2. 20DH 525 IA32_MTRR_PHYSMASK6 Shared See Table 2-2. 20EH 526 IA32_MTRR_PHYSBASE7 Shared See Table 2-2. 20FH 527 IA32_MTRR_PHYSMASK7 Shared See Table 2-2. 250H 592 IA32_MTRR_FIX64K_00000 Shared See Table 2-2. 258H 600 IA32_MTRR_FIX16K_80000 Shared See Table 2-2. 259H 601 IA32_MTRR_FIX16K_A0000 Shared See Table 2-2. 268H 616 IA32_MTRR_FIX4K_C0000 Shared See Table 2-2. 269H 617 IA32_MTRR_FIX4K_C8000 Shared See Table 2-2. 26AH 618 IA32_MTRR_FIX4K_D0000 Shared See Table 2-2. 26BH 619 IA32_MTRR_FIX4K_D8000 Shared See Table 2-2. 26CH 620 IA32_MTRR_FIX4K_E0000 Shared See Table 2-2. 26DH 621 IA32_MTRR_FIX4K_E8000 Shared See Table 2-2. 26EH 622 IA32_MTRR_FIX4K_F0000 Shared See Table 2-2. 26FH 623 IA32_MTRR_FIX4K_F8000 Shared See Table 2-2. 277H 631 IA32_PAT Unique See Table 2-2. 309H 777 IA32_FIXED_CTR0 Unique Fixed-Function Performance Counter Register 0 (R/W) See Table 2-2. 30AH 778 IA32_FIXED_CTR1 Unique Fixed-Function Performance Counter Register 1 (R/W) See Table 2-2. 30BH 779 IA32_FIXED_CTR2 Unique Fixed-Function Performance Counter Register 2 (R/W) See Table 2-2. 345H 837 IA32_PERF_CAPABILITIES Shared 38DH 909 IA32_FIXED_CTR_CTRL Unique See Table 2-2. See Section 17.4.1, “IA32_DEBUGCTL MSR.” Fixed-Function-Counter Control Register (R/W) See Table 2-2. 38EH 910 IA32_PERF_GLOBAL_STATUS Unique See Table 2-2. See Section 18.6.2.2, “Global Counter Control Facilities.” 38FH 911 IA32_PERF_GLOBAL_CTRL Unique See Table 2-2. See Section 18.6.2.2, “Global Counter Control Facilities.” 390H 912 IA32_PERF_GLOBAL_OVF_CTRL Unique See Table 2-2. See Section 18.6.2.2, “Global Counter Control Facilities.” 3F1H 1009 MSR_PEBS_ENABLE Unique See Table 2-2. See Section 18.6.2.4, “Processor Event Based Sampling (PEBS).” 0 400H 2-68 Vol. 4 1024 IA32_MC0_CTL Enable PEBS on IA32_PMC0 (R/W) Shared See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” MODEL-SPECIFIC REGISTERS (MSRS) Table 2-4. MSRs in 45 nm and 32 nm Intel® Atom™ Processor Family (Contd.) Register Address Register Name / Bit Fields Shared/ Unique Bit Description Hex Dec 401H 1025 IA32_MC0_STATUS Shared See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 402H 1026 IA32_MC0_ADDR Shared See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” The IA32_MC0_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC0_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 404H 1028 IA32_MC1_CTL Shared See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 405H 1029 IA32_MC1_STATUS Shared See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 408H 1032 IA32_MC2_CTL Shared See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 409H 1033 IA32_MC2_STATUS Shared See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 40AH 1034 IA32_MC2_ADDR Shared See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” The IA32_MC2_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC2_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 40CH 1036 IA32_MC3_CTL Shared See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 40DH 1037 IA32_MC3_STATUS Shared See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 40EH 1038 IA32_MC3_ADDR Shared See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” The MSR_MC3_ADDR register is either not implemented or contains no address if the ADDRV flag in the MSR_MC3_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 410H 1040 IA32_MC4_CTL Shared See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 411H 1041 IA32_MC4_STATUS Shared See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 412H 1042 IA32_MC4_ADDR Shared See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” The MSR_MC4_ADDR register is either not implemented or contains no address if the ADDRV flag in the MSR_MC4_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 480H 1152 IA32_VMX_BASIC Unique Reporting Register of Basic VMX Capabilities (R/O) See Table 2-2. See Appendix A.1, “Basic VMX Information.” 481H 1153 IA32_VMX_PINBASED_CTLS Unique Capability Reporting Register of Pin-Based VM-Execution Controls (R/O) See Table 2-2. See Appendix A.3, “VM-Execution Controls.” Vol. 4 2-69 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-4. MSRs in 45 nm and 32 nm Intel® Atom™ Processor Family (Contd.) Register Address Register Name / Bit Fields Shared/ Unique Hex Dec 482H 1154 IA32_VMX_PROCBASED_CTLS Unique 483H 1155 IA32_VMX_EXIT_CTLS Unique Bit Description Capability Reporting Register of Primary Processor-Based VM-Execution Controls (R/O) See Appendix A.3, “VM-Execution Controls.” Capability Reporting Register of VM-Exit Controls (R/O) See Table 2-2. See Appendix A.4, “VM-Exit Controls.” 484H 1156 IA32_VMX_ENTRY_CTLS Unique Capability Reporting Register of VM-Entry Controls (R/O) See Table 2-2. See Appendix A.5, “VM-Entry Controls.” 485H 1157 IA32_VMX_MISC Unique Reporting Register of Miscellaneous VMX Capabilities (R/O) See Table 2-2. See Appendix A.6, “Miscellaneous Data.” 486H 1158 IA32_VMX_CR0_FIXED0 Unique Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Table 2-2. See Appendix A.7, “VMX-Fixed Bits in CR0.” 487H 1159 IA32_VMX_CR0_FIXED1 Unique Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Table 2-2. See Appendix A.7, “VMX-Fixed Bits in CR0.” 488H 1160 IA32_VMX_CR4_FIXED0 Unique Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Table 2-2. See Appendix A.8, “VMX-Fixed Bits in CR4.” 489H 1161 IA32_VMX_CR4_FIXED1 Unique Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) See Table 2-2. See Appendix A.8, “VMX-Fixed Bits in CR4.” 48AH 1162 IA32_VMX_VMCS_ENUM Unique Capability Reporting Register of VMCS Field Enumeration (R/O) See Table 2-2. See Appendix A.9, “VMCS Enumeration.” 48BH 1163 IA32_VMX_PROCBASED_CTLS2 Unique Capability Reporting Register of Secondary ProcessorBased VM-Execution Controls (R/O) See Appendix A.3, “VM-Execution Controls.” 600H 1536 IA32_DS_AREA Unique DS Save Area (R/W) See Table 2-2. See Section 18.6.3.4, “Debug Store (DS) Mechanism.” C000_ 0080H IA32_EFER C000_ 0081H IA32_STAR C000_ 0082H IA32_LSTAR 2-70 Vol. 4 Unique Extended Feature Enables See Table 2-2. Unique System Call Target Address (R/W) See Table 2-2. Unique IA-32e Mode System Call Target Address (R/W) See Table 2-2. MODEL-SPECIFIC REGISTERS (MSRS) Table 2-4. MSRs in 45 nm and 32 nm Intel® Atom™ Processor Family (Contd.) Register Address Hex Register Name / Bit Fields Shared/ Unique Bit Description Dec C000_ 0084H IA32_FMASK C000_ 0100H IA32_FS_BASE C000_ 0101H IA32_GS_BASE C000_ 0102H IA32_KERNEL_GS_BASE Unique System Call Flag Mask (R/W) See Table 2-2. Unique Map of BASE Address of FS (R/W) See Table 2-2. Unique Map of BASE Address of GS (R/W) See Table 2-2. Unique Swap Target of BASE Address of GS (R/W) See Table 2-2. Table 2-5 lists model-specific registers (MSRs) that are specific to Intel® Atom™ processor with the CPUID signature with DisplayFamily_DisplayModel of 06_27H. Table 2-5. MSRs Supported by Intel® Atom™ Processors with CPUID Signature 06_27H Register Address Hex Dec 3F8H 1016 Register Name / Bit Fields MSR_PKG_C2_RESIDENCY Scope Package Bit Description Package C2 Residency Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. 63:0 Package Package C2 Residency Counter (R/O) Time that this package is in processor-specific C2 states since last reset. Counts at 1 Mhz frequency. 3F9H 1017 MSR_PKG_C4_RESIDENCY Package Package C4 Residency Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. 63:0 Package Package C4 Residency Counter. (R/O) Time that this package is in processor-specific C4 states since last reset. Counts at 1 Mhz frequency. 3FAH 1018 MSR_PKG_C6_RESIDENCY Package Package C6 Residency Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. 63:0 Package Package C6 Residency Counter. (R/O) Time that this package is in processor-specific C6 states since last reset. Counts at 1 Mhz frequency. 2.4 MSRS IN INTEL PROCESSORS BASED ON SILVERMONT MICROARCHITECTURE Table 2-6 lists model-specific registers (MSRs) common to Intel processors based on the Silvermont microarchitecture. These processors have a CPUID signature with DisplayFamily_DisplayModel of 06_37H, 06_4AH, 06_4DH, Vol. 4 2-71 MODEL-SPECIFIC REGISTERS (MSRS) 06_5AH, and 06_5DH; see Table 2-1. The MSRs listed in Table 2-6 are also common to processors based on the Airmont microarchitecture and newer microarchitectures for next generation Intel Atom processors. Table 2-7 lists MSRs common to processors based on the Silvermont and Airmont microarchitectures, but not newer microarchitectures. Table 2-8, Table 2-9, and Table 2-10 lists MSRs that are model-specific across processors based on the Silvermont microarchitecture. In the Silvermont microarchitecture, the scope column indicates the following: “Core” means each processor core has a separate MSR, or a bit field not shared with another processor core. “Module” means the MSR or the bit field is shared by a pair of processor cores in the physical package. “Package” means all processor cores in the physical package share the same MSR or bit interface. Table 2-6. MSRs Common to the Silvermont Microarchitecture and Newer Microarchitectures for Intel Atom Processors Register Address Register Name / Bit Fields Scope Bit Description Hex Dec 0H 0 IA32_P5_MC_ADDR Module See Section 2.23, “MSRs in Pentium Processors.” 1H 1 IA32_P5_MC_TYPE Module See Section 2.23, “MSRs in Pentium Processors.” 6H 6 IA32_MONITOR_FILTER_SIZE Core See Section 8.10.5, “Monitor/Mwait Address Range Determination.” and Table 2-2. 10H 16 IA32_TIME_STAMP_COUNTER Core See Section 17.17, “Time-Stamp Counter,” and Table 2-2. 1BH 27 IA32_APIC_BASE Core See Section 10.4.4, “Local APIC Status and Location,” and Table 2-2. 2AH 42 MSR_EBL_CR_POWERON Module Processor Hard Power-On Configuration (R/W) Writes ignored. 63:0 34H 52 MSR_SMI_COUNT Reserved Core 31:0 SMI Counter (R/O) SMI Count (R/O) Running count of SMI events since last RESET. 63:32 79H 121 IA32_BIOS_UPDT_TRIG Reserved Core BIOS Update Trigger Register (W) See Table 2-2. 8BH 139 IA32_BIOS_SIGN_ID Core BIOS Update Signature ID (RO) See Table 2-2. C1H 193 IA32_PMC0 Core Performance counter register See Table 2-2. C2H 194 IA32_PMC1 Core Performance Counter Register See Table 2-2. E4H 228 MSR_PMG_IO_CAPTURE_BASE Module Power Management IO Redirection in C-state (R/W) See http://biosbits.org. 2-72 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-6. MSRs Common to the Silvermont Microarchitecture and Newer Microarchitectures for Intel Atom Processors Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 15:0 LVL_2 Base Address (R/W) Specifies the base address visible to software for IO redirection. If IO MWAIT Redirection is enabled, reads to this address will be consumed by the power management logic and decoded to MWAIT instructions. When IO port address redirection is enabled, this is the IO port address reported to the OS/software. 18:16 C-state Range (R/W) Specifies the encoding value of the maximum C-State code name to be included when IO read to MWAIT redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4 is the max C-State to include 110b - C6 is the max C-State to include 111b - C7 is the max C-State to include 63:19 E7H 231 IA32_MPERF Reserved Core Maximum Performance Frequency Clock Count (RW) See Table 2-2. E8H 232 IA32_APERF Core Actual Performance Frequency Clock Count (RW) See Table 2-2. FEH 254 IA32_MTRRCAP Core Memory Type Range Register (R) See Table 2-2. 13CH 52 MSR_FEATURE_CONFIG Core AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP handler to handle unsuccessful read of this MSR. 1:0 AES Configuration (RW-L) Upon a successful read of this MSR, the configuration of AES instruction sets availability is as follows: 11b: AES instructions are not available until next RESET. Otherwise, AES instructions are available. Note: AES instruction set is not available if read is unsuccessful. If the configuration is not 01b, AES instructions can be mis-configured if a privileged agent unintentionally writes 11b. 63:2 Reserved 174H 372 IA32_SYSENTER_CS Core See Table 2-2. 175H 373 IA32_SYSENTER_ESP Core See Table 2-2. 176H 374 IA32_SYSENTER_EIP Core See Table 2-2. 179H 377 IA32_MCG_CAP Core See Table 2-2. 17AH 378 IA32_MCG_STATUS Core Global Machine Check Status Vol. 4 2-73 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-6. MSRs Common to the Silvermont Microarchitecture and Newer Microarchitectures for Intel Atom Processors Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 0 RIPV When set, bit indicates that the instruction addressed by the instruction pointer pushed on the stack (when the machine check was generated) can be used to restart the program. If cleared, the program cannot be reliably restarted. 1 EIPV When set, bit indicates that the instruction addressed by the instruction pointer pushed on the stack (when the machine check was generated) is directly associated with the error. 2 MCIP When set, bit indicates that a machine check has been generated. If a second machine check is detected while this bit is still set, the processor enters a shutdown state. Software should write this bit to 0 after processing a machine check exception. 63:3 186H 390 IA32_PERFEVTSEL0 Reserved Core See Table 2-2. 7:0 Event Select 15:8 UMask 16 USR 17 OS 18 Edge 19 PC 20 INT 21 Reserved 22 EN 23 INV 31:24 CMASK 63:32 Reserved 187H 391 IA32_PERFEVTSEL1 Core See Table 2-2. 198H 408 IA32_PERF_STATUS Module See Table 2-2. 199H 409 IA32_PERF_CTL Core See Table 2-2. 19AH 410 IA32_CLOCK_MODULATION Core Clock Modulation (R/W) See Table 2-2. IA32_CLOCK_MODULATION MSR was originally named IA32_THERM_CONTROL MSR. 19BH 411 IA32_THERM_INTERRUPT Core Thermal Interrupt Control (R/W) See Table 2-2. 2-74 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-6. MSRs Common to the Silvermont Microarchitecture and Newer Microarchitectures for Intel Atom Processors Register Address Hex Dec 19CH 412 Register Name / Bit Fields IA32_THERM_STATUS Scope Core Bit Description Thermal Monitor Status (R/W) See Table 2-2. 1A2H 418 MSR_TEMPERATURE_TARGET Package 15:0 Temperature Target Reserved 23:16 Temperature Target (R) The default thermal throttling or PROCHOT# activation temperature in degrees C. The effective temperature for thermal throttling or PROCHOT# activation is “Temperature Target” + “Target Offset”. 29:24 Target Offset (R/W) Specifies an offset in degrees C to adjust the throttling and PROCHOT# activation temperature from the default target specified in TEMPERATURE_TARGET (bits 23:16). 63:30 Reserved 1A6H 422 MSR_OFFCORE_RSP_0 Module Offcore Response Event Select Register (R/W) 1A7H 423 MSR_OFFCORE_RSP_1 Module Offcore Response Event Select Register (R/W) 1B0H 432 IA32_ENERGY_PERF_BIAS Core See Table 2-2. 1D9H 473 IA32_DEBUGCTL Core Debug Control (R/W) See Table 2-2. 1DDH 477 MSR_LER_FROM_LIP Core Last Exception Record From Linear IP (R/W) Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled. 1DEH 478 MSR_LER_TO_LIP Core Last Exception Record To Linear IP (R/W) This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled. 1F2H 498 IA32_SMRR_PHYSBASE Core See Table 2-2. 1F3H 499 IA32_SMRR_PHYSMASK Core See Table 2-2. 200H 512 IA32_MTRR_PHYSBASE0 Core See Table 2-2. 201H 513 IA32_MTRR_PHYSMASK0 Core See Table 2-2. 202H 514 IA32_MTRR_PHYSBASE1 Core See Table 2-2. 203H 515 IA32_MTRR_PHYSMASK1 Core See Table 2-2. 204H 516 IA32_MTRR_PHYSBASE2 Core See Table 2-2. 205H 517 IA32_MTRR_PHYSMASK2 Core See Table 2-2. 206H 518 IA32_MTRR_PHYSBASE3 Core See Table 2-2. 207H 519 IA32_MTRR_PHYSMASK3 Core See Table 2-2. 208H 520 IA32_MTRR_PHYSBASE4 Core See Table 2-2. Vol. 4 2-75 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-6. MSRs Common to the Silvermont Microarchitecture and Newer Microarchitectures for Intel Atom Processors Register Address Register Name / Bit Fields Scope Bit Description Hex Dec 209H 521 IA32_MTRR_PHYSMASK4 Core See Table 2-2. 20AH 522 IA32_MTRR_PHYSBASE5 Core See Table 2-2. 20BH 523 IA32_MTRR_PHYSMASK5 Core See Table 2-2. 20CH 524 IA32_MTRR_PHYSBASE6 Core See Table 2-2. 20DH 525 IA32_MTRR_PHYSMASK6 Core See Table 2-2. 20EH 526 IA32_MTRR_PHYSBASE7 Core See Table 2-2. 20FH 527 IA32_MTRR_PHYSMASK7 Core See Table 2-2. 250H 592 IA32_MTRR_FIX64K_00000 Core See Table 2-2. 258H 600 IA32_MTRR_FIX16K_80000 Core See Table 2-2. 259H 601 IA32_MTRR_FIX16K_A0000 Core See Table 2-2. 268H 616 IA32_MTRR_FIX4K_C0000 Core See Table 2-2. 269H 617 IA32_MTRR_FIX4K_C8000 Core See Table 2-2. 26AH 618 IA32_MTRR_FIX4K_D0000 Core See Table 2-2. 26BH 619 IA32_MTRR_FIX4K_D8000 Core See Table 2-2. 26CH 620 IA32_MTRR_FIX4K_E0000 Core See Table 2-2. 26DH 621 IA32_MTRR_FIX4K_E8000 Core See Table 2-2. 26EH 622 IA32_MTRR_FIX4K_F0000 Core See Table 2-2. 26FH 623 IA32_MTRR_FIX4K_F8000 Core See Table 2-2. 277H 631 IA32_PAT Core See Table 2-2. 2FFH 767 IA32_MTRR_DEF_TYPE Core Default Memory Types (R/W) See Table 2-2. 309H 777 IA32_FIXED_CTR0 Core Fixed-Function Performance Counter Register 0 (R/W) See Table 2-2. 30AH 778 IA32_FIXED_CTR1 Core Fixed-Function Performance Counter Register 1 (R/W) See Table 2-2. 30BH 779 IA32_FIXED_CTR2 Core Fixed-Function Performance Counter Register 2 (R/W) See Table 2-2. 345H 837 IA32_PERF_CAPABILITIES Core 38DH 909 IA32_FIXED_CTR_CTRL Core See Table 2-2. See Section 17.4.1, “IA32_DEBUGCTL MSR.” Fixed-Function-Counter Control Register (R/W) See Table 2-2. 38FH 911 IA32_PERF_GLOBAL_CTRL Core See Table 2-2. See Section 18.6.2.2, “Global Counter Control Facilities.” 3FDH 1021 MSR_CORE_C6_RESIDENCY Core Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. 2-76 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-6. MSRs Common to the Silvermont Microarchitecture and Newer Microarchitectures for Intel Atom Processors Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 63:0 CORE C6 Residency Counter (R/O) Value since last reset that this core is in processorspecific C6 states. Counts at the TSC Frequency. 400H 1024 IA32_MC0_CTL Module See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 401H 1025 IA32_MC0_STATUS Module See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 402H 1026 IA32_MC0_ADDR Module See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” The IA32_MC0_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC0_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 404H 1028 IA32_MC1_CTL Module See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 405H 1029 IA32_MC1_STATUS Module See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 408H 1032 IA32_MC2_CTL Module See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 409H 1033 IA32_MC2_STATUS Module See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 40AH 1034 IA32_MC2_ADDR Module See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” The IA32_MC2_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC2_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 40CH 1036 IA32_MC3_CTL Core See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 40DH 1037 IA32_MC3_STATUS Core See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 40EH 1038 IA32_MC3_ADDR Core See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” The MSR_MC3_ADDR register is either not implemented or contains no address if the ADDRV flag in the MSR_MC3_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 410H 1040 IA32_MC4_CTL Core See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 411H 1041 IA32_MC4_STATUS Core See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 412H 1042 IA32_MC4_ADDR Core See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” The MSR_MC4_ADDR register is either not implemented or contains no address if the ADDRV flag in the MSR_MC4_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 414H 1044 IA32_MC5_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” Vol. 4 2-77 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-6. MSRs Common to the Silvermont Microarchitecture and Newer Microarchitectures for Intel Atom Processors Register Address Register Name / Bit Fields Scope Bit Description Hex Dec 415H 1045 IA32_MC5_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 416H 1046 IA32_MC5_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” The MSR_MC4_ADDR register is either not implemented or contains no address if the ADDRV flag in the MSR_MC4_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 480H 1152 IA32_VMX_BASIC Core Reporting Register of Basic VMX Capabilities (R/O) See Table 2-2. See Appendix A.1, “Basic VMX Information.” 481H 1153 IA32_VMX_PINBASED_CTLS Core Capability Reporting Register of Pin-Based VM-Execution Controls (R/O) See Table 2-2. See Appendix A.3, “VM-Execution Controls.” 482H 1154 IA32_VMX_PROCBASED_CTLS Core Capability Reporting Register of Primary ProcessorBased VM-Execution Controls (R/O) See Appendix A.3, “VM-Execution Controls.” 483H 1155 IA32_VMX_EXIT_CTLS Core Capability Reporting Register of VM-Exit Controls (R/O) See Table 2-2. See Appendix A.4, “VM-Exit Controls.” 484H 1156 IA32_VMX_ENTRY_CTLS Core Capability Reporting Register of VM-Entry Controls (R/O) See Table 2-2. See Appendix A.5, “VM-Entry Controls.” 485H 1157 IA32_VMX_MISC Core Reporting Register of Miscellaneous VMX Capabilities (R/O) See Table 2-2. See Appendix A.6, “Miscellaneous Data.” 486H 1158 IA32_VMX_CR0_FIXED0 Core Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Table 2-2. See Appendix A.7, “VMX-Fixed Bits in CR0.” 487H 1159 IA32_VMX_CR0_FIXED1 Core Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Table 2-2. See Appendix A.7, “VMX-Fixed Bits in CR0.” 488H 1160 IA32_VMX_CR4_FIXED0 Core Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Table 2-2. See Appendix A.8, “VMX-Fixed Bits in CR4.” 2-78 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-6. MSRs Common to the Silvermont Microarchitecture and Newer Microarchitectures for Intel Atom Processors Register Address Hex Dec 489H 1161 Register Name / Bit Fields IA32_VMX_CR4_FIXED1 Scope Core Bit Description Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) See Table 2-2. See Appendix A.8, “VMX-Fixed Bits in CR4.” 48AH 1162 IA32_VMX_VMCS_ENUM Core Capability Reporting Register of VMCS Field Enumeration (R/O) See Table 2-2. See Appendix A.9, “VMCS Enumeration.” 48BH 1163 IA32_VMX_PROCBASED_CTLS2 Core Capability Reporting Register of Secondary ProcessorBased VM-Execution Controls (R/O) See Appendix A.3, “VM-Execution Controls.” 48CH 1164 IA32_VMX_EPT_VPID_ENUM Core Capability Reporting Register of EPT and VPID (R/O) See Table 2-2 48DH 1165 IA32_VMX_TRUE_PINBASED_CTLS Core Capability Reporting Register of Pin-Based VM-Execution Flex Controls (R/O) See Table 2-2 48EH 1166 IA32_VMX_TRUE_PROCBASED_CTLS Core Capability Reporting Register of Primary Processorbased VM-Execution Flex Controls (R/O) See Table 2-2 48FH 1167 IA32_VMX_TRUE_EXIT_CTLS Core Capability Reporting Register of VM-Exit Flex Controls (R/O) See Table 2-2 490H 1168 IA32_VMX_TRUE_ENTRY_CTLS Core 491H 1169 IA32_VMX_FMFUNC Core Capability Reporting Register of VM-Entry Flex Controls (R/O) See Table 2-2 Capability Reporting Register of VM-Function Controls (R/O) See Table 2-2 4C1H 1217 IA32_A_PMC0 Core See Table 2-2. 4C2H 1218 IA32_A_PMC1 Core See Table 2-2. 600H 1536 IA32_DS_AREA Core DS Save Area (R/W) See Table 2-2. See Section 18.6.3.4, “Debug Store (DS) Mechanism.” 660H 1632 MSR_CORE_C1_RESIDENCY Core 63:0 Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. CORE C1 Residency Counter. (R/O) Value since last reset that this core is in processorspecific C1 states. Counts at the TSC frequency. 6E0H 1760 IA32_TSC_DEADLINE Core TSC Target of Local APIC’s TSC Deadline Mode (R/W) See Table 2-2. Vol. 4 2-79 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-6. MSRs Common to the Silvermont Microarchitecture and Newer Microarchitectures for Intel Atom Processors Register Address Hex Register Name / Bit Fields Scope Bit Description Dec C000_ 0080H IA32_EFER C000_ 0081H IA32_STAR C000_ 0082H IA32_LSTAR C000_ 0084H IA32_FMASK C000_ 0100H IA32_FS_BASE C000_ 0101H IA32_GS_BASE C000_ 0102H IA32_KERNEL_GS_BASE C000_ 0103H IA32_TSC_AUX Core Extended Feature Enables See Table 2-2. Core System Call Target Address (R/W) See Table 2-2. Core IA-32e Mode System Call Target Address (R/W) See Table 2-2. Core System Call Flag Mask (R/W) See Table 2-2. Core Map of BASE Address of FS (R/W) See Table 2-2. Core Map of BASE Address of GS (R/W) See Table 2-2. Core Swap Target of BASE Address of GS (R/W) See Table 2-2. Core AUXILIARY TSC Signature (R/W) See Table 2-2 Table 2-7 lists model-specific registers (MSRs) that are common to Intel® Atom™ processors based on the Silvermont and Airmont microarchitectures but not newer microarchitectures. Table 2-7. MSRs Common to the Silvermont and Airmont Microarchitectures Register Address Hex Dec 17H 23 Register Name / Bit Fields MSR_PLATFORM_ID Scope Module Bit Description Model Specific Platform ID (R) 7:0 Reserved 13:8 Maximum Qualified Ratio (R) The maximum allowed bus ratio. 3AH 58 49:13 Reserved 52:50 See Table 2-2. 63:33 Reserved IA32_FEATURE_CONTROL Core Control Features in Intel 64Processor (R/W) See Table 2-2. 2-80 Vol. 4 0 Lock (R/WL) 1 Reserved 2 Enable VMX outside SMX operation (R/WL) MODEL-SPECIFIC REGISTERS (MSRS) Table 2-7. MSRs Common to the Silvermont and Airmont Microarchitectures Register Address Hex Dec 40H 64 Register Name / Bit Fields MSR_LASTBRANCH_0_FROM_IP Scope Core Bit Description Last Branch Record 0 From IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction. See also: • Last Branch Record Stack TOS at 1C9H. • Section 17.5 and record format in Section 17.4.8.1. 41H 65 MSR_LASTBRANCH_1_FROM_IP Core Last Branch Record 1 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 42H 66 MSR_LASTBRANCH_2_FROM_IP Core Last Branch Record 2 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 43H 67 MSR_LASTBRANCH_3_FROM_IP Core Last Branch Record 3 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 44H 68 MSR_LASTBRANCH_4_FROM_IP Core Last Branch Record 4 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 45H 69 MSR_LASTBRANCH_5_FROM_IP Core Last Branch Record 5 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 46H 70 MSR_LASTBRANCH_6_FROM_IP Core Last Branch Record 6 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 47H 71 MSR_LASTBRANCH_7_FROM_IP Core Last Branch Record 7 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 60H 96 MSR_LASTBRANCH_0_TO_IP Core Last Branch Record 0 To IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the destination instruction. 61H 97 MSR_LASTBRANCH_1_TO_IP Core Last Branch Record 1 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 62H 98 MSR_LASTBRANCH_2_TO_IP Core Last Branch Record 2 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 63H 99 MSR_LASTBRANCH_3_TO_IP Core Last Branch Record 3 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 64H 100 MSR_LASTBRANCH_4_TO_IP Core Last Branch Record 4 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 65H 101 MSR_LASTBRANCH_5_TO_IP Core Last Branch Record 5 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 66H 102 MSR_LASTBRANCH_6_TO_IP Core Last Branch Record 6 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 67H 103 MSR_LASTBRANCH_7_TO_IP Core Last Branch Record 7 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. Vol. 4 2-81 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-7. MSRs Common to the Silvermont and Airmont Microarchitectures Register Address Hex Dec E2H 226 Register Name / Bit Fields MSR_PKG_CST_CONFIG_CONTROL Scope Module Bit Description C-State Configuration Control (R/W) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. See http://biosbits.org. 2:0 Package C-State Limit (R/W) Specifies the lowest processor-specific C-state code name (consuming the least power) for the package. The default is set as factory-configured package C-state limit. The following C-state code name encodings are supported: 000b: C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b) 100b: C4 110b: C6 111b: C7 (Silvermont only). 9:3 Reserved 10 I/O MWAIT Redirection Enable (R/W) When set, will map IO_read instructions sent to IO register specified by MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions. 14:11 Reserved 15 CFG Lock (R/WO) When set, locks bits 15:0 of this register until next reset. 63:16 11EH 281 MSR_BBL_CR_CTL3 Reserved Module Control Register 3 Used to configure the L2 Cache. 0 L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled. 0 = Indicates if the L2 is hardware-disabled. 7:1 Reserved 8 L2 Enabled (R/W) 1 = L2 cache has been initialized. 0 = Disabled (default). Until this bit is set the processor will not respond to the WBINVD instruction or the assertion of the FLUSH# input. 22:9 Reserved 23 L2 Not Present (RO) 0 = L2 Present. 1 = L2 Not Present. 63:24 2-82 Vol. 4 Reserved MODEL-SPECIFIC REGISTERS (MSRS) Table 2-7. MSRs Common to the Silvermont and Airmont Microarchitectures Register Address Hex Dec 1A0H 416 Register Name / Bit Fields Scope IA32_MISC_ENABLE Bit Description Enable Misc. Processor Features (R/W) Allows a variety of processor functions to be enabled and disabled. 0 Core Fast-Strings Enable See Table 2-2. 2:1 3 Reserved Module Automatic Thermal Control Circuit Enable (R/W) See Table 2-2. Default value is 0. 6:4 7 Reserved Core Performance Monitoring Available (R) See Table 2-2. 10:8 11 Reserved Core Branch Trace Storage Unavailable (RO) See Table 2-2. 12 Core Processor Event Based Sampling Unavailable (RO) See Table 2-2. 15:13 Reserved 16 Module 18 Core Enhanced Intel SpeedStep Technology Enable (R/W) See Table 2-2. ENABLE MONITOR FSM (R/W) See Table 2-2. 21:19 22 Reserved Core Limit CPUID Maxval (R/W) See Table 2-2. 23 Module xTPR Message Disable (R/W) See Table 2-2. 33:24 34 Reserved Core XD Bit Disable (R/W) See Table 2-2. 37:35 Reserved Vol. 4 2-83 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-7. MSRs Common to the Silvermont and Airmont Microarchitectures Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 38 Module Turbo Mode Disable (R/W) When set to 1 on processors that support Intel Turbo Boost Technology, the turbo mode feature is disabled and the IDA_Enable feature flag will be cleared (CPUID.06H: EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H: EAX[1] reports the processor’s support of turbo mode is enabled. Note: The power-on default value is used by BIOS to detect hardware support of turbo mode. If the power-on default value is 1, turbo mode is available in the processor. If the power-on default value is 0, turbo mode is not available. 63:39 1C8H 456 MSR_LBR_SELECT Reserved Core Last Branch Record Filtering Select Register (R/W) See Section 17.9.2, “Filtering of Last Branch Records.” 1C9H 457 0 CPL_EQ_0 1 CPL_NEQ_0 2 JCC 3 NEAR_REL_CALL 4 NEAR_IND_CALL 5 NEAR_RET 6 NEAR_IND_JMP 7 NEAR_REL_JMP 8 FAR_BRANCH 63:9 Reserved MSR_LASTBRANCH_TOS Core Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2) that points to the MSR containing the most recent branch record. See MSR_LASTBRANCH_0_FROM_IP. 38EH 910 IA32_PERF_GLOBAL_STATUS Core See Table 2-2. See Section 18.6.2.2, “Global Counter Control Facilities.” 390H 912 IA32_PERF_GLOBAL_OVF_CTRL Core See Table 2-2. See Section 18.6.2.2, “Global Counter Control Facilities.” 3F1H 1009 MSR_PEBS_ENABLE Core See Table 2-2. See Section 18.6.2.4, “Processor Event Based Sampling (PEBS).” 0 3FAH 1018 MSR_PKG_C6_RESIDENCY 63:0 Enable PEBS for precise event on IA32_PMC0 (R/W) Package Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C6 Residency Counter (R/O) Value since last reset that this package is in processorspecific C6 states. Counts at the TSC Frequency. 2-84 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-7. MSRs Common to the Silvermont and Airmont Microarchitectures Register Address Register Name / Bit Fields Hex Dec 664H 1636 MSR_MC6_RESIDENCY_COUNTER Scope Module Bit Description Module C6 Residency Counter (R/0) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. 63:0 Time that this module is in module-specific C6 states since last reset. Counts at 1 Mhz frequency. CEH 206 MSR_PLATFORM_INFO Package 7:0 Platform Information: Contains power management and other model specific features enumeration. See http://biosbits.org. Reserved 15:8 Package Maximum Non-Turbo Ratio (R/O) This is the ratio of the maximum frequency that does not require turbo. Frequency = ratio * Scalable Bus Frequency. 63:16 2.4.1 Reserved MSRs with Model-Specific Behavior in the Silvermont Microarchitecture Table 2-8 lists model-specific registers (MSRs) that are specific to Intel® Atom™ processor E3000 Series (CPUID signature with DisplayFamily_DisplayModel of 06_37H) and Intel Atom processors (CPUID signatures with DisplayFamily_DisplayModel of 06_4AH, 06_5AH, 06_5DH). Table 2-8. Specific MSRs Supported by Intel® Atom™ Processors with CPUID Signatures 06_37H, 06_4AH, 06_5AH, 06_5DH Register Address Hex Dec 606H 1542 Register Name / Bit Fields MSR_RAPL_POWER_UNIT Scope Package Bit Description Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1, “RAPL Interfaces.” 3:0 Power Units Power related information (in milliWatts) is based on the multiplier, 2^PU; where PU is an unsigned integer represented by bits 3:0. Default value is 0101b, indicating power unit is in 32 milliWatts increment. 7:4 12:8 Reserved Energy Status Units Energy related information (in microJoules) is based on the multiplier, 2^ESU; where ESU is an unsigned integer represented by bits 12:8. Default value is 00101b, indicating energy unit is in 32 microJoules increment. 15:13 Reserved Vol. 4 2-85 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-8. Specific MSRs Supported by Intel® Atom™ Processors with CPUID Signatures 06_37H, 06_4AH, 06_5AH, 06_5DH Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 19:16 Time Unit The value is 0000b, indicating time unit is in one second. 63:20 610H 1552 Reserved MSR_PKG_POWER_LIMIT Package 14:0 PKG RAPL Power Limit Control (R/W) Package Power Limit #1 (R/W) See Section 14.9.3, “Package RAPL Domain.” and MSR_RAPL_POWER_UNIT in Table 2-8. 15 Enable Power Limit #1 (R/W) See Section 14.9.3, “Package RAPL Domain.” 16 Package Clamping Limitation #1 (R/W) See Section 14.9.3, “Package RAPL Domain.” 23:17 Time Window for Power Limit #1 (R/W) In unit of second. If 0 is specified in bits [23:17], defaults to 1 second window. 63:24 611H 1553 Reserved MSR_PKG_ENERGY_STATUS Package PKG Energy Status (R/O) See Section 14.9.3, “Package RAPL Domain.” and MSR_RAPL_POWER_UNIT in Table 2-8. 639H 1593 MSR_PP0_ENERGY_STATUS Package PP0 Energy Status (R/O) See Section 14.9.4, “PP0/PP1 RAPL Domains.” and MSR_RAPL_POWER_UNIT in Table 2-8. CDH 205 MSR_FSB_FREQ Module Scaleable Bus Speed(RO) This field indicates the intended scaleable bus clock speed for processors based on Silvermont microarchitecture. 2:0 • • • • • 100B: 080.0 MHz 000B: 083.3 MHz 001B: 100.0 MHz 010B: 133.3 MHz 011B: 116.7 MHz 63:3 Reserved Table 2-9 lists model-specific registers (MSRs) that are specific to Intel® Atom™ processor E3000 Series (CPUID signature with DisplayFamily_DisplayModel of 06_37H). Table 2-9. Specific MSRs Supported by Intel® Atom™ Processor E3000 Series with CPUID Signature 06_37H Register Address Hex Dec 668H 1640 Register Name / Bit Fields MSR_CC6_DEMOTION_POLICY_CONFIG 63:0 2-86 Vol. 4 Scope Package Bit Description Core C6 Demotion Policy Config MSR Controls per-core C6 demotion policy. Writing a value of 0 disables core level HW demotion policy. MODEL-SPECIFIC REGISTERS (MSRS) Table 2-9. Specific MSRs Supported by Intel® Atom™ Processor E3000 Series (Contd.)with CPUID Signature 06_37H Register Address Hex Dec 669H 1641 Register Name / Bit Fields MSR_MC6_DEMOTION_POLICY_CONFIG Scope Package 63:0 664H 1636 Bit Description Module C6 Demotion Policy Config MSR Controls module (i.e., two cores sharing the second-level cache) C6 demotion policy. Writing a value of 0 disables module level HW demotion policy. MSR_MC6_RESIDENCY_COUNTER Module Module C6 Residency Counter (R/0) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. 63:0 Time that this module is in module-specific C6 states since last reset. Counts at 1 Mhz frequency. Table 2-10 lists model-specific registers (MSRs) that are specific to Intel® Atom™ processor C2000 Series (CPUID signature with DisplayFamily_DisplayModel of 06_4DH). Table 2-10. Specific MSRs Supported by Intel® Atom™ Processor C2000 Series with CPUID Signature 06_4DH Register Address Hex Dec 1A4H 420 Register Name / Bit Fields Scope MSR_MISC_FEATURE_CONTROL 0 Bit Description Miscellaneous Feature Control (R/W) Core L2 Hardware Prefetcher Disable (R/W) If 1, disables the L2 hardware prefetcher, which fetches additional lines of code or data into the L2 cache. 1 2 Reserved Core DCU Hardware Prefetcher Disable (R/W) If 1, disables the L1 data cache prefetcher, which fetches the next cache line into L1 data cache. 63:3 1ADH 429 Reserved MSR_TURBO_RATIO_LIMIT Package Maximum Ratio Limit of Turbo Mode (RW) 7:0 Package Maximum Ratio Limit for 1C Maximum turbo ratio limit of 1 core active. 15:8 Package Maximum Ratio Limit for 2C Maximum turbo ratio limit of 2 core active. 23:16 Package Maximum Ratio Limit for 3C Maximum turbo ratio limit of 3 core active. 31:24 Package Maximum Ratio Limit for 4C Maximum turbo ratio limit of 4 core active. 39:32 Package Maximum Ratio Limit for 5C Maximum turbo ratio limit of 5 core active. 47:40 Package Maximum Ratio Limit for 6C Maximum turbo ratio limit of 6 core active. Vol. 4 2-87 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-10. Specific MSRs Supported by Intel® Atom™ Processor C2000 Series (Contd.)with CPUID Signature Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 55:48 Package Maximum Ratio Limit for 7C Maximum turbo ratio limit of 7 core active. 63:56 Package Maximum Ratio Limit for 8C Maximum turbo ratio limit of 8 core active. 606H 1542 MSR_RAPL_POWER_UNIT Package Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1, “RAPL Interfaces.” 3:0 Power Units Power related information (in milliWatts) is based on the multiplier, 2^PU; where PU is an unsigned integer represented by bits 3:0. Default value is 0101b, indicating power unit is in 32 milliWatts increment. 7:4 Reserved 12:8 Energy Status Units. Energy related information (in microJoules) is based on the multiplier, 2^ESU; where ESU is an unsigned integer represented by bits 12:8. Default value is 00101b, indicating energy unit is in 32 microJoules increment. 15:13 Reserved 19:16 Time Unit The value is 0000b, indicating time unit is in one second. 63:20 610H 1552 MSR_PKG_POWER_LIMIT Reserved Package PKG RAPL Power Limit Control (R/W) See Section 14.9.3, “Package RAPL Domain.” 66EH 1646 MSR_PKG_POWER_INFO 14:0 Package PKG RAPL Parameter (R/0) Thermal Spec Power (R/0) The unsigned integer value is the equivalent of the thermal specification power of the package domain. The unit of this field is specified by the “Power Units” field of MSR_RAPL_POWER_UNIT. 63:15 2.4.2 Reserved MSRs In Intel Atom Processors Based on Airmont Microarchitecture Intel Atom processor X7-Z8000 and X5-Z8000 series are based on the Airmont microarchitecture. These processors support MSRs listed in Table 2-6, Table 2-7, Table 2-8, and Table 2-11. These processors have a CPUID signature with DisplayFamily_DisplayModel including 06_4CH; see Table 2-1. 2-88 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-11. MSRs in Intel Atom Processors Based on the Airmont Microarchitecture Register Address Hex Dec CDH 205 Register Name / Bit Fields MSR_FSB_FREQ Scope Module Bit Description Scaleable Bus Speed(RO) This field indicates the intended scaleable bus clock speed for processors based on Airmont microarchitecture. E2H 226 3:0 • • • • • • • • • 63:5 Reserved MSR_PKG_CST_CONFIG_CONTROL Module 0000B: 083.3 MHz 0001B: 100.0 MHz 0010B: 133.3 MHz 0011B: 116.7 MHz 0100B: 080.0 MHz 0101B: 093.3 MHz 0110B: 090.0 MHz 0111B: 088.9 MHz 1000B: 087.5 MHz C-State Configuration Control (R/W) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. See http://biosbits.org. 2:0 Package C-State Limit (R/W) Specifies the lowest processor-specific C-state code name (consuming the least power) for the package. The default is set as factory-configured package Cstate limit. The following C-state code name encodings are supported: 000b: No limit 001b: C1 010b: C2 110b: C6 111b: C7 9:3 Reserved 10 I/O MWAIT Redirection Enable (R/W) When set, will map IO_read instructions sent to IO register specified by MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions. 14:11 Reserved 15 CFG Lock (R/WO) When set, locks bits 15:0 of this register until next reset. 63:16 E4H 228 MSR_PMG_IO_CAPTURE_BASE Reserved Module Power Management IO Redirection in C-state (R/W) See http://biosbits.org. Vol. 4 2-89 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-11. MSRs in Intel Atom Processors Based on the Airmont Microarchitecture (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 15:0 LVL_2 Base Address (R/W) Specifies the base address visible to software for IO redirection. If IO MWAIT Redirection is enabled, reads to this address will be consumed by the power management logic and decoded to MWAIT instructions. When IO port address redirection is enabled, this is the IO port address reported to the OS/software. 18:16 C-state Range (R/W) Specifies the encoding value of the maximum C-State code name to be included when IO read to MWAIT redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3 is the max C-State to include. 001b - Deep Power Down Technology is the max CState. 010b - C7 is the max C-State to include. 63:19 638H 1592 MSR_PP0_POWER_LIMIT 14:0 Reserved Package PP0 RAPL Power Limit Control (R/W) PP0 Power Limit #1 (R/W) See Section 14.9.4, “PP0/PP1 RAPL Domains” and MSR_RAPL_POWER_UNIT in Table 2-8. 15 Enable Power Limit #1 (R/W) See Section 14.9.4, “PP0/PP1 RAPL Domains.” 16 Reserved 23:17 Time Window for Power Limit #1 (R/W) Specifies the time duration over which the average power must remain below PP0_POWER_LIMIT #1(14:0). Supported Encodings: 0x0: 1 second time duration. 0x1: 5 second time duration (Default). 0x2: 10 second time duration. 0x3: 15 second time duration. 0x4: 20 second time duration. 0x5: 25 second time duration. 0x6: 30 second time duration. 0x7: 35 second time duration. 0x8: 40 second time duration. 0x9: 45 second time duration. 0xA: 50 second time duration. 0xB-0x7F - reserved. 63:24 2-90 Vol. 4 Reserved MODEL-SPECIFIC REGISTERS (MSRS) 2.5 MSRS IN INTEL ATOM PROCESSORS BASED ON GOLDMONT MICROARCHITECTURE Intel Atom processors based on the Goldmont microarchitecture support MSRs listed in Table 2-6 and Table 2-12. These processors have a CPUID signature with DisplayFamily_DisplayModel of 06_5CH; see Table 2-1. In the Goldmont microarchitecture, the scope column indicates the following: “Core” means each processor core has a separate MSR, or a bit field not shared with another processor core. “Module” means the MSR or the bit field is shared by a pair of processor cores in the physical package. “Package” means all processor cores in the physical package share the same MSR or bit interface. Table 2-12. MSRs in Intel Atom Processors Based on the Goldmont Microarchitecture Register Address Hex Dec 17H 23 3AH 58 Register Name / Bit Fields MSR_PLATFORM_ID Scope Module Bit Description Model Specific Platform ID (R) 49:0 Reserved 52:50 See Table 2-2. 63:33 Reserved IA32_FEATURE_CONTROL Core Control Features in Intel 64 Processor (R/W) See Table 2-2. 3BH 59 0 Lock (R/WL) 1 Enable VMX inside SMX operation (R/WL) 2 Enable VMX outside SMX operation (R/WL) 14:8 SENTER local functions enables (R/WL) 15 SENTER global functions enable (R/WL) 18 SGX global functions enable (R/WL) 63:19 Reserved IA32_TSC_ADJUST Core Per-Core TSC ADJUST (R/W) See Table 2-2. C3H 195 IA32_PMC2 Core Performance Counter Register See Table 2-2. C4H 196 IA32_PMC3 Core Performance Counter Register See Table 2-2. CEH 206 MSR_PLATFORM_INFO Package Platform Information Contains power management and other model specific features enumeration. See http://biosbits.org. 7:0 15:8 Reserved Package Maximum Non-Turbo Ratio (R/O) This is the ratio of the maximum frequency that does not require turbo. Frequency = ratio * 100 MHz. 27:16 Reserved Vol. 4 2-91 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-12. MSRs in Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 28 Package Programmable Ratio Limit for Turbo Mode (R/O) When set to 1, indicates that Programmable Ratio Limit for Turbo mode is enabled. When set to 0, indicates Programmable Ratio Limit for Turbo mode is disabled. 29 Package Programmable TDP Limit for Turbo Mode (R/O) When set to 1, indicates that TDP Limit for Turbo mode is programmable. When set to 0, indicates TDP Limit for Turbo mode is not programmable. 30 Package Programmable TJ OFFSET (R/O) When set to 1, indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to specify a temperature offset. 39:31 47:40 Reserved Package Maximum Efficiency Ratio (R/O) This is the minimum ratio (maximum efficiency) that the processor can operate, in units of 100MHz. 63:48 E2H 226 MSR_PKG_CST_CONFIG_CONTROL Reserved Core C-State Configuration Control (R/W) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. See http://biosbits.org. 3:0 Package C-State Limit (R/W) Specifies the lowest processor-specific C-state code name (consuming the least power) for the package. The default is set as factory-configured package Cstate limit. The following C-state code name encodings are supported: 0000b: No limit 0001b: C1 0010b: C3 0011b: C6 0100b: C7 0101b: C7S 0110b: C8 0111b: C9 1000b: C10 9:3 Reserved 10 I/O MWAIT Redirection Enable (R/W) When set, will map IO_read instructions sent to IO register specified by MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions. 2-92 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-12. MSRs in Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 14:11 Reserved 15 CFG Lock (R/WO) When set, locks bits 15:0 of this register until next reset. 63:16 17DH 381 MSR_SMM_MCA_CAP Reserved Core Enhanced SMM Capabilities (SMM-RO) Reports SMM capability enhancement. Accessible only while in SMM. 57:0 Reserved 58 SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the SMM code access restriction is supported and the MSR_SMM_FEATURE_CONTROL is supported. 59 Long_Flow_Indication (SMM-RO) If set to 1 indicates that the SMM long flow indicator is supported and the MSR_SMM_DELAYED is supported. 63:60 Reserved 188H 392 IA32_PERFEVTSEL2 Core See Table 2-2. 189H 393 IA32_PERFEVTSEL3 Core See Table 2-2. 1A0H 416 IA32_MISC_ENABLE Enable Misc. Processor Features (R/W) Allows a variety of processor functions to be enabled and disabled. 0 Core Fast-Strings Enable See Table 2-2. 2:1 3 Reserved Package Automatic Thermal Control Circuit Enable (R/W) See Table 2-2. Default value is 1. 6:4 7 Reserved Core Performance Monitoring Available (R) See Table 2-2. 10:8 11 Reserved Core Branch Trace Storage Unavailable (RO) See Table 2-2. 12 Core Processor Event Based Sampling Unavailable (RO) See Table 2-2. 15:13 16 Reserved Package Enhanced Intel SpeedStep Technology Enable (R/W) See Table 2-2. 18 Core ENABLE MONITOR FSM (R/W) See Table 2-2. Vol. 4 2-93 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-12. MSRs in Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 21:19 22 Reserved Core Limit CPUID Maxval (R/W) See Table 2-2. 23 Package xTPR Message Disable (R/W) See Table 2-2. 33:24 34 Reserved Core XD Bit Disable (R/W) See Table 2-2. 37:35 38 Reserved Package Turbo Mode Disable (R/W) When set to 1 on processors that support Intel Turbo Boost Technology, the turbo mode feature is disabled and the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H: EAX[1] reports the processor’s support of turbo mode is enabled. Note: The power-on default value is used by BIOS to detect hardware support of turbo mode. If the poweron default value is 1, turbo mode is available in the processor. If the power-on default value is 0, turbo mode is not available. 1A4H 420 63:39 Reserved MSR_MISC_FEATURE_CONTROL Miscellaneous Feature Control (R/W) 0 Core L2 Hardware Prefetcher Disable (R/W) If 1, disables the L2 hardware prefetcher, which fetches additional lines of code or data into the L2 cache. 1 2 Reserved Core DCU Hardware Prefetcher Disable (R/W) If 1, disables the L1 data cache prefetcher, which fetches the next cache line into L1 data cache. 63:3 1AAH 426 MSR_MISC_PWR_MGMT Reserved Package Miscellaneous Power Management Control Various model specific features enumeration. See http://biosbits.org. 0 EIST Hardware Coordination Disable (R/W) When 0, enables hardware coordination of Enhanced Intel Speedstep Technology request from processor cores. When 1, disables hardware coordination of Enhanced Intel Speedstep Technology requests. 21:1 2-94 Vol. 4 Reserved MODEL-SPECIFIC REGISTERS (MSRS) Table 2-12. MSRs in Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 22 Thermal Interrupt Coordination Enable (R/W) If set, then thermal interrupt on one core is routed to all cores. 63:23 1ADH 429 MSR_TURBO_RATIO_LIMIT Reserved Package Maximum Ratio Limit of Turbo Mode by Core Groups (RW) Specifies Maximum Ratio Limit for each Core Group. Max ratio for groups with more cores must decrease monotonically. For groups with less than 4 cores, the max ratio must be 32 or less. For groups with 4-5 cores, the max ratio must be 22 or less. For groups with more than 5 cores, the max ratio must be 16 or less. 7:0 Package Maximum Ratio Limit for Active Cores in Group 0 Maximum turbo ratio limit when the number of active cores is less than or equal to the Group 0 threshold. 15:8 Package Maximum Ratio Limit for Active Cores in Group 1 Maximum turbo ratio limit when the number of active cores is less than or equal to the Group 1 threshold, and greater than the Group 0 threshold. 23:16 Package Maximum Ratio Limit for Active Cores in Group 2 Maximum turbo ratio limit when the number of active cores is less than or equal to the Group 2 threshold, and greater than the Group 1 threshold. 31:24 Package Maximum Ratio Limit for Active Cores in Group 3 Maximum turbo ratio limit when the number of active cores is less than or equal to the Group 3 threshold, and greater than the Group 2 threshold. 39:32 Package Maximum Ratio Limit for Active Cores in Group 4 Maximum turbo ratio limit when the number of active cores is less than or equal to the Group 4 threshold, and greater than the Group 3 threshold. 47:40 Package Maximum Ratio Limit for Active Cores in Group 5 Maximum turbo ratio limit when the number of active cores is less than or equal to the Group 5 threshold, and greater than the Group 4 threshold. 55:48 Package Maximum Ratio Limit for Active Cores in Group 6 Maximum turbo ratio limit when the number of active cores is less than or equal to the Group 6 threshold, and greater than the Group 5 threshold. 63:56 Package Maximum Ratio Limit for Active Cores in Group 7 Maximum turbo ratio limit when the number of active cores is less than or equal to the Group 7 threshold, and greater than the Group 6 threshold. Vol. 4 2-95 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-12. MSRs in Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.) Register Address Hex Dec 1AEH 430 Register Name / Bit Fields Scope MSR_TURBO_GROUP_CORECNT Package 7:0 Package Bit Description Group Size of Active Cores for Turbo Mode Operation (RW) Writes of 0 threshold is ignored. Group 0 Core Count Threshold Maximum number of active cores to operate under the Group 0 Max Turbo Ratio limit. 15:8 Package Group 1 Core Count Threshold Maximum number of active cores to operate under the Group 1 Max Turbo Ratio limit. Must be greater than the Group 0 Core Count. 23:16 Package Group 2 Core Count Threshold Maximum number of active cores to operate under the Group 2 Max Turbo Ratio limit. Must be greater than the Group 1 Core Count. 31:24 Package Group 3 Core Count Threshold Maximum number of active cores to operate under the Group 3 Max Turbo Ratio limit. Must be greater than the Group 2 Core Count. 39:32 Package Group 4 Core Count Threshold Maximum number of active cores to operate under the Group 4 Max Turbo Ratio limit. Must be greater than the Group 3 Core Count. 47:40 Package Group 5 Core Count Threshold Maximum number of active cores to operate under the Group 5 Max Turbo Ratio limit. Must be greater than the Group 4 Core Count. 55:48 Package Group 6 Core Count Threshold Maximum number of active cores to operate under the Group 6 Max Turbo Ratio limit. Must be greater than the Group 5 Core Count. 63:56 Package Group 7 Core Count Threshold Maximum number of active cores to operate under the Group 7 Max Turbo Ratio limit. Must be greater than the Group 6 Core Count, and not less than the total number of processor cores in the package. E.g., specify 255. 1C8H 456 MSR_LBR_SELECT Core Last Branch Record Filtering Select Register (R/W) See Section 17.9.2, “Filtering of Last Branch Records.” 2-96 Vol. 4 0 CPL_EQ_0 1 CPL_NEQ_0 2 JCC 3 NEAR_REL_CALL 4 NEAR_IND_CALL 5 NEAR_RET MODEL-SPECIFIC REGISTERS (MSRS) Table 2-12. MSRs in Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.) Register Address Hex 1C9H Register Name / Bit Fields Scope Bit Description Dec 457 6 NEAR_IND_JMP 7 NEAR_REL_JMP 8 FAR_BRANCH 9 EN_CALL_STACK 63:10 Reserved MSR_LASTBRANCH_TOS Core Last Branch Record Stack TOS (R/W) Contains an index (bits 0-4) that points to the MSR containing the most recent branch record. See MSR_LASTBRANCH_0_FROM_IP. 1FCH 508 MSR_POWER_CTL Core 0 1 Power Control Register. See http://biosbits.org. Reserved Package C1E Enable (R/W) When set to ‘1’, will enable the CPU to switch to the Minimum Enhanced Intel SpeedStep Technology operating point when all execution cores enter MWAIT (C1). 63:2 Reserved 210H 528 IA32_MTRR_PHYSBASE8 Core See Table 2-2. 211H 529 IA32_MTRR_PHYSMASK8 Core See Table 2-2. 212H 530 IA32_MTRR_PHYSBASE9 Core See Table 2-2. 213H 531 IA32_MTRR_PHYSMASK9 Core See Table 2-2. 280H 640 IA32_MC0_CTL2 Module See Table 2-2. 281H 641 IA32_MC1_CTL2 Module See Table 2-2. 282H 642 IA32_MC2_CTL2 Core See Table 2-2. 283H 643 IA32_MC3_CTL2 Module See Table 2-2. 284H 644 IA32_MC4_CTL2 Package See Table 2-2. 285H 645 IA32_MC5_CTL2 Package See Table 2-2. 286H 646 IA32_MC6_CTL2 Package See Table 2-2. 300H 768 MSR_SGXOWNEREPOCH0 Package Lower 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in the package. 63:0 301H 769 MSR_SGXOWNEREPOCH1 Lower 64 bits of an 128-bit external entropy value for key derivation of an enclave. Package Upper 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in the package. 63:0 Upper 64 bits of an 128-bit external entropy value for key derivation of an enclave. Vol. 4 2-97 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-12. MSRs in Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.) Register Address Hex Dec 38EH 910 390H 2-98 Vol. 4 912 Register Name / Bit Fields IA32_PERF_GLOBAL_STATUS Scope Core Bit Description See Table 2-2. See Section 18.2.4, “Architectural Performance Monitoring Version 4.” 0 Ovf_PMC0 1 Ovf_PMC1 2 Ovf_PMC2 3 Ovf_PMC3 31:4 Reserved 32 Ovf_FixedCtr0 33 Ovf_FixedCtr1 34 Ovf_FixedCtr2 54:35 Reserved 55 Trace_ToPA_PMI 57:56 Reserved 58 LBR_Frz. 59 CTR_Frz. 60 ASCI 61 Ovf_Uncore 62 Ovf_BufDSSAVE 63 CondChgd IA32_PERF_GLOBAL_STATUS_RESET Core See Table 2-2. See Section 18.2.4, “Architectural Performance Monitoring Version 4.” 0 Set 1 to clear Ovf_PMC0. 1 Set 1 to clear Ovf_PMC1. 2 Set 1 to clear Ovf_PMC2. 3 Set 1 to clear Ovf_PMC3. 31:4 Reserved 32 Set 1 to clear Ovf_FixedCtr0. 33 Set 1 to clear Ovf_FixedCtr1. 34 Set 1 to clear Ovf_FixedCtr2. 54:35 Reserved 55 Set 1 to clear Trace_ToPA_PMI. 57:56 Reserved 58 Set 1 to clear LBR_Frz. 59 Set 1 to clear CTR_Frz. 60 Set 1 to clear ASCI. 61 Set 1 to clear Ovf_Uncore. 62 Set 1 to clear Ovf_BufDSSAVE. MODEL-SPECIFIC REGISTERS (MSRS) Table 2-12. MSRs in Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.) Register Address Hex Register Name / Bit Fields Scope Dec 63 391H 913 IA32_PERF_GLOBAL_STATUS_SET Set 1 to clear CondChgd. Core Set 1 to cause Ovf_PMC0 = 1. 1 Set 1 to cause Ovf_PMC1 = 1. 2 Set 1 to cause Ovf_PMC2 = 1. 3 Set 1 to cause Ovf_PMC3 = 1. 31:4 Reserved 32 Set 1 to cause Ovf_FixedCtr0 = 1. 33 Set 1 to cause Ovf_FixedCtr1 = 1. 34 Set 1 to cause Ovf_FixedCtr2 = 1. 54:35 Reserved 55 Set 1 to cause Trace_ToPA_PMI = 1. 57:56 Reserved 58 Set 1 to cause LBR_Frz = 1. 59 Set 1 to cause CTR_Frz = 1. 60 Set 1 to cause ASCI = 1. 61 Set 1 to cause Ovf_Uncore. 62 Set 1 to cause Ovf_BufDSSAVE. 63 Reserved See Table 2-2. 914 IA32_PERF_GLOBAL_INUSE 3F1H 1009 MSR_PEBS_ENABLE Core 0 1016 See Table 2-2. See Section 18.2.4, “Architectural Performance Monitoring Version 4.” 0 392H 3F8H Bit Description MSR_PKG_C3_RESIDENCY See Table 2-2. See Section 18.6.2.4, “Processor Event Based Sampling (PEBS).” Enable PEBS trigger and recording for the programmed event (precise or otherwise) on IA32_PMC0. (R/W) Package 63:0 Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C3 Residency Counter (R/O) Value since last reset that this package is in processor-specific C3 states. Count at the same frequency as the TSC. 3F9H 1017 MSR_PKG_C6_RESIDENCY 63:0 Package Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C6 Residency Counter (R/O) Value since last reset that this package is in processor-specific C6 states. Count at the same frequency as the TSC. Vol. 4 2-99 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-12. MSRs in Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.) Register Address Hex Dec 3FCH 1020 Register Name / Bit Fields MSR_CORE_C3_RESIDENCY Scope Core 63:0 Bit Description Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. CORE C3 Residency Counter (R/O) Value since last reset that this core is in processorspecific C3 states. Count at the same frequency as the TSC. 406H 1030 IA32_MC1_ADDR Module See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” The IA32_MC2_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC2_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 418H 1048 IA32_MC6_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 419H 1049 IA32_MC6_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. 41AH 1050 IA32_MC6_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 4C3H 1219 IA32_A_PMC2 Core See Table 2-2. 4C4H 1220 IA32_A_PMC3 Core See Table 2-2. 4E0H 1248 MSR_SMM_FEATURE_CONTROL Package Enhanced SMM Feature Control (SMM-RW) Reports SMM capability Enhancement. Accessible only while in SMM. 0 Lock (SMM-RWO) When set to ‘1’ locks this register from further changes. 1 Reserved 2 SMM_Code_Chk_En (SMM-RW) This control bit is available only if MSR_SMM_MCA_CAP[58] == 1. When set to ‘0’ (default) none of the logical processors are prevented from executing SMM code outside the ranges defined by the SMRR. When set to ‘1’ any logical processor in the package that attempts to execute SMM code not within the ranges defined by the SMRR will assert an unrecoverable MCE. 63:3 4E2H 1250 MSR_SMM_DELAYED Reserved Package SMM Delayed (SMM-RO) Reports the interruptible state of all logical processors in the package. Available only while in SMM and MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1. 2-100 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-12. MSRs in Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec N-1:0 LOG_PROC_STATE (SMM-RO) Each bit represents a processor core of its state in a long flow of internal operation which delays servicing an interrupt. The corresponding bit will be set at the start of long events such as: Microcode Update Load, C6, WBINVD, Ratio Change, Throttle. The bit is automatically cleared at the end of each long event. The reset value of this field is 0. Only bit positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be updated. 63:N 4E3H 1251 MSR_SMM_BLOCKED Reserved Package SMM Blocked (SMM-RO) Reports the blocked state of all logical processors in the package. Available only while in SMM. N-1:0 LOG_PROC_STATE (SMM-RO) Each bit represents a processor core of its blocked state to service an SMI. The corresponding bit will be set if the logical processor is in one of the following states: Wait For SIPI or SENTER Sleep. The reset value of this field is 0FFFH. Only bit positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be updated. 63:N 500H 1280 IA32_SGX_SVN_STATUS Reserved Core 0 Status and SVN Threshold of SGX Support for ACM (RO) Lock See Section 41.11.3, “Interactions with Authenticated Code Modules (ACMs)”. 15:1 Reserved 23:16 SGX_SVN_SINIT See Section 41.11.3, “Interactions with Authenticated Code Modules (ACMs)”. 63:24 560H 1376 IA32_RTIT_OUTPUT_BASE Reserved Core Trace Output Base Register (R/W) See Table 2-2. 561H 1377 IA32_RTIT_OUTPUT_MASK_PTRS Core Trace Output Mask Pointers Register (R/W) See Table 2-2. 570H 1392 IA32_RTIT_CTL Core Trace Control Register (R/W) 0 TraceEn 1 CYCEn 2 OS 3 User 6:4 Reserved, must be zero. Vol. 4 2-101 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-12. MSRs in Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 7 CR3 filter 8 ToPA Writing 0 will #GP if also setting TraceEn. 571H 1393 9 MTCEn 10 TSCEn 11 DisRETC 12 Reserved, must be zero. 13 BranchEn 17:14 MTCFreq 18 Reserved, must be zero. 22:19 CYCThresh 23 Reserved, must be zero. 27:24 PSBFreq 31:28 Reserved, must be zero. 35:32 ADDR0_CFG 39:36 ADDR1_CFG 63:40 Reserved, must be zero. IA32_RTIT_STATUS Core 0 Tracing Status Register (R/W) FilterEn Writes ignored. 1 ContexEn Writes ignored. 2 TriggerEn Writes ignored. 572H 580H 1394 1408 3 Reserved 4 Error (R/W) 5 Stopped 31:6 Reserved, must be zero. 48:32 PacketByteCnt 63:49 Reserved, must be zero. IA32_RTIT_CR3_MATCH Core 4:0 Reserved 63:5 CR3[63:5] value to match. IA32_RTIT_ADDR0_A Core 63:0 581H 1409 IA32_RTIT_ADDR0_B 63:0 2-102 Vol. 4 Trace Filter CR3 Match Register (R/W) Region 0 Start Address (R/W) See Table 2-2. Core Region 0 End Address (R/W) See Table 2-2. MODEL-SPECIFIC REGISTERS (MSRS) Table 2-12. MSRs in Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.) Register Address Hex Dec 582H 1410 Register Name / Bit Fields IA32_RTIT_ADDR1_A Scope Core 63:0 583H 1411 IA32_RTIT_ADDR1_B 1542 MSR_RAPL_POWER_UNIT Region 1 Start Address (R/W) See Table 2-2. Core 63:0 606H Bit Description Region 1 End Address (R/W) See Table 2-2. Package Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1, “RAPL Interfaces.” 3:0 Power Units Power related information (in Watts) is in unit of 1W/2^PU; where PU is an unsigned integer represented by bits 3:0. Default value is 1000b, indicating power unit is in 3.9 milliWatts increment. 7:4 Reserved 12:8 Energy Status Units Energy related information (in Joules) is in unit of 1Joule/ (2^ESU); where ESU is an unsigned integer represented by bits 12:8. Default value is 01110b, indicating energy unit is in 61 microJoules. 15:13 Reserved 19:16 Time Unit Time related information (in seconds) is in unit of 1S/2^TU; where TU is an unsigned integer represented by bits 19:16. Default value is 1010b, indicating power unit is in 0.977 millisecond. 63:20 60AH 1546 MSR_PKGC3_IRTL Reserved Package Package C3 Interrupt Response Limit (R/W) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. 9:0 Interrupt Response Time Limit (R/W) Specifies the limit that should be used to decide if the package should be put into a package C3 state. 12:10 Time Unit (R/W) Specifies the encoding value of time unit of the interrupt response time limit. See Table 2-20 for supported time unit encodings. 14:13 Reserved 15 Valid (R/W) Indicates whether the values in bits 12:0 are valid and can be used by the processor for package C-sate management. 63:16 Reserved Vol. 4 2-103 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-12. MSRs in Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.) Register Address Hex Dec 60BH 1547 Register Name / Bit Fields MSR_PKGC_IRTL1 Scope Package Bit Description Package C6/C7S Interrupt Response Limit 1 (R/W) This MSR defines the interrupt response time limit used by the processor to manage a transition to a package C6 or C7S state. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-states. 9:0 Interrupt Response Time Limit (R/W) Specifies the limit that should be used to decide if the package should be put into a package C6 or C7S state. 12:10 Time Unit (R/W) Specifies the encoding value of time unit of the interrupt response time limit. See Table 2-20 for supported time unit encodings. 14:13 Reserved 15 Valid (R/W) Indicates whether the values in bits 12:0 are valid and can be used by the processor for package C-sate management. 63:16 60CH 1548 MSR_PKGC_IRTL2 Reserved Package Package C7 Interrupt Response Limit 2 (R/W) This MSR defines the interrupt response time limit used by the processor to manage a transition to a package C7 state. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. 9:0 Interrupt Response Time Limit (R/W) Specifies the limit that should be used to decide if the package should be put into a package C7 state. 12:10 Time Unit (R/W) Specifies the encoding value of time unit of the interrupt response time limit. See Table 2-20 for supported time unit encodings. 14:13 Reserved 15 Valid (R/W) Indicates whether the values in bits 12:0 are valid and can be used by the processor for package C-sate management. 63:16 60DH 2-104 Vol. 4 1549 MSR_PKG_C2_RESIDENCY Reserved Package Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-states. MODEL-SPECIFIC REGISTERS (MSRS) Table 2-12. MSRs in Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 63:0 Package C2 Residency Counter (R/O) Value since last reset that this package is in processor-specific C2 states. Count at the same frequency as the TSC. 610H 1552 MSR_PKG_POWER_LIMIT Package PKG RAPL Power Limit Control (R/W) See Section 14.9.3, “Package RAPL Domain.” 611H 1553 MSR_PKG_ENERGY_STATUS Package PKG Energy Status (R/O) See Section 14.9.3, “Package RAPL Domain.” 613H 1555 MSR_PKG_PERF_STATUS Package PKG Perf Status (R/O) See Section 14.9.3, “Package RAPL Domain.” 614H 1556 MSR_PKG_POWER_INFO Package 14:0 PKG RAPL Parameters (R/W) Thermal Spec Power (R/W) See Section 14.9.3, “Package RAPL Domain.” 15 Reserved 30:16 Minimum Power (R/W) See Section 14.9.3, “Package RAPL Domain.” 31 Reserved 46:32 Maximum Power (R/W) See Section 14.9.3, “Package RAPL Domain.” 47 Reserved 54:48 Maximum Time Window (R/W) Specified by 2^Y * (1.0 + Z/4.0) * Time_Unit, where “Y” is the unsigned integer value represented by bits 52:48, “Z” is an unsigned integer represented by bits 54:53. “Time_Unit” is specified by the “Time Units” field of MSR_RAPL_POWER_UNIT. 63:55 618H 1560 MSR_DRAM_POWER_LIMIT Reserved Package DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, “DRAM RAPL Domain.” 619H 1561 MSR_DRAM_ENERGY_STATUS Package DRAM Energy Status (R/O) See Section 14.9.5, “DRAM RAPL Domain.” 61BH 1563 MSR_DRAM_PERF_STATUS Package DRAM Performance Throttling Status (R/O) See Section 14.9.5, “DRAM RAPL Domain.” 61CH 1564 MSR_DRAM_POWER_INFO Package DRAM RAPL Parameters (R/W) See Section 14.9.5, “DRAM RAPL Domain.” 632H 1586 MSR_PKG_C10_RESIDENCY 63:0 Package Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-states. Package C10 Residency Counter (R/O) Value since last reset that the entire SOC is in an S0i3 state. Count at the same frequency as the TSC. Vol. 4 2-105 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-12. MSRs in Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.) Register Address Hex Dec 639H 1593 Register Name / Bit Fields MSR_PP0_ENERGY_STATUS Scope Package Bit Description PP0 Energy Status (R/O) See Section 14.9.4, “PP0/PP1 RAPL Domains.” 641H 1601 MSR_PP1_ENERGY_STATUS Package PP1 Energy Status (R/O) See Section 14.9.4, “PP0/PP1 RAPL Domains.” 64CH 1612 MSR_TURBO_ACTIVATION_RATIO Package 7:0 ConfigTDP Control (R/W) MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this field. 30:8 Reserved 31 TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the content of this register is locked until a reset. 63:32 64FH 1615 MSR_CORE_PERF_LIMIT_REASONS Reserved Package Indicator of Frequency Clipping in Processor Cores (R/W) (Frequency refers to processor core frequency.) 0 PROCHOT Status (R0) When set, processor core frequency is reduced below the operating system request due to assertion of external PROCHOT. 1 Thermal Status (R0) When set, frequency is reduced below the operating system request due to a thermal event. 2 Package-Level Power Limiting PL1 Status (R0) When set, frequency is reduced below the operating system request due to package-level power limiting PL1. 3 Package-Level PL2 Power Limiting Status (R0) When set, frequency is reduced below the operating system request due to package-level power limiting PL2. 8:4 Reserved 9 Core Power Limiting Status (R0) When set, frequency is reduced below the operating system request due to domain-level power limiting. 10 VR Therm Alert Status (R0) When set, frequency is reduced below the operating system request due to a thermal alert from the Voltage Regulator. 11 Max Turbo Limit Status (R0) When set, frequency is reduced below the operating system request due to multi-core turbo limits. 2-106 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-12. MSRs in Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 12 Electrical Design Point Status (R0) When set, frequency is reduced below the operating system request due to electrical design point constraints (e.g., maximum electrical current consumption). 13 Turbo Transition Attenuation Status (R0) When set, frequency is reduced below the operating system request due to Turbo transition attenuation. This prevents performance degradation due to frequent operating ratio changes. 14 Maximum Efficiency Frequency Status (R0) When set, frequency is reduced below the maximum efficiency frequency. 15 Reserved 16 PROCHOT Log When set, indicates that the PROCHOT Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 17 Thermal Log When set, indicates that the Thermal Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 18 Package-Level PL1 Power Limiting Log When set, indicates that the Package Level PL1 Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 19 Package-Level PL2 Power Limiting Log When set, indicates that the Package Level PL2 Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 24:20 25 Reserved Core Power Limiting Log When set, indicates that the Core Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. Vol. 4 2-107 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-12. MSRs in Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 26 VR Therm Alert Log When set, indicates that the VR Therm Alert Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 27 Max Turbo Limit Log When set, indicates that the Max Turbo Limit Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 28 Electrical Design Point Log When set, indicates that the EDP Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 29 Turbo Transition Attenuation Log When set, indicates that the Turbo Transition Attenuation Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 30 Maximum Efficiency Frequency Log When set, indicates that the Maximum Efficiency Frequency Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 63:31 680H 1664 MSR_LASTBRANCH_0_FROM_IP Reserved Core Last Branch Record 0 From IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: • Last Branch Record Stack TOS at 1C9H. • Section 17.6 and record format in Section 17.4.8.1. 681H 1665 0:47 From Linear Address (R/W) 62:48 Signed extension of bits 47:0. 63 Mispred MSR_LASTBRANCH_1_FROM_IP Core Last Branch Record 1 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 682H 1666 MSR_LASTBRANCH_2_FROM_IP Core Last Branch Record 2 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 683H 1667 MSR_LASTBRANCH_3_FROM_IP Core Last Branch Record 3 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 2-108 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-12. MSRs in Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.) Register Address Hex Dec 684H 1668 Register Name / Bit Fields MSR_LASTBRANCH_4_FROM_IP Scope Core Bit Description Last Branch Record 4 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 685H 1669 MSR_LASTBRANCH_5_FROM_IP Core Last Branch Record 5 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 686H 1670 MSR_LASTBRANCH_6_FROM_IP Core Last Branch Record 6 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 687H 1671 MSR_LASTBRANCH_7_FROM_IP Core Last Branch Record 7 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 688H 1672 MSR_LASTBRANCH_8_FROM_IP Core Last Branch Record 8 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 689H 1673 MSR_LASTBRANCH_9_FROM_IP Core Last Branch Record 9 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 68AH 1674 MSR_LASTBRANCH_10_FROM_IP Core Last Branch Record 10 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 68BH 1675 MSR_LASTBRANCH_11_FROM_IP Core Last Branch Record 11 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 68CH 1676 MSR_LASTBRANCH_12_FROM_IP Core Last Branch Record 12 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 68DH 1677 MSR_LASTBRANCH_13_FROM_IP Core Last Branch Record 13 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 68EH 1678 MSR_LASTBRANCH_14_FROM_IP Core Last Branch Record 14 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 68FH 1679 MSR_LASTBRANCH_15_FROM_IP Core Last Branch Record 15 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 690H 1680 MSR_LASTBRANCH_16_FROM_IP Core Last Branch Record 16 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 691H 1681 MSR_LASTBRANCH_17_FROM_IP Core Last Branch Record 17 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 692H 1682 MSR_LASTBRANCH_18_FROM_IP Core Last Branch Record 18 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 693H 1683 MSR_LASTBRANCH_19_FROM_IP Core Last Branch Record 19From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 694H 1684 MSR_LASTBRANCH_20_FROM_IP Core Last Branch Record 20 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 695H 1685 MSR_LASTBRANCH_21_FROM_IP Core Last Branch Record 21 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 696H 1686 MSR_LASTBRANCH_22_FROM_IP Core Last Branch Record 22 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. Vol. 4 2-109 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-12. MSRs in Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.) Register Address Hex Dec 697H 1687 Register Name / Bit Fields MSR_LASTBRANCH_23_FROM_IP Scope Core Bit Description Last Branch Record 23 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 698H 1688 MSR_LASTBRANCH_24_FROM_IP Core Last Branch Record 24 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 699H 1689 MSR_LASTBRANCH_25_FROM_IP Core Last Branch Record 25 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 69AH 1690 MSR_LASTBRANCH_26_FROM_IP Core Last Branch Record 26 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 69BH 1691 MSR_LASTBRANCH_27_FROM_IP Core Last Branch Record 27 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 69CH 1692 MSR_LASTBRANCH_28_FROM_IP Core Last Branch Record 28 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 69DH 1693 MSR_LASTBRANCH_29_FROM_IP Core Last Branch Record 29 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 69EH 1694 MSR_LASTBRANCH_30_FROM_IP Core Last Branch Record 30 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 69FH 1695 MSR_LASTBRANCH_31_FROM_IP Core Last Branch Record 31 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 6C0H 1728 MSR_LASTBRANCH_0_TO_IP Core Last Branch Record 0 To IP (R/W) One of 32 pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the Destination instruction and elapsed cycles from last LBR update. See Section 17.6. 6C1H 1729 0:47 Target Linear Address (R/W) 63:48 Elapsed cycles from last update to the LBR. MSR_LASTBRANCH_1_TO_IP Core Last Branch Record 1 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6C2H 1730 MSR_LASTBRANCH_2_TO_IP Core Last Branch Record 2 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6C3H 1731 MSR_LASTBRANCH_3_TO_IP Core Last Branch Record 3 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6C4H 1732 MSR_LASTBRANCH_4_TO_IP Core Last Branch Record 4 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6C5H 1733 MSR_LASTBRANCH_5_TO_IP Core Last Branch Record 5 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6C6H 1734 MSR_LASTBRANCH_6_TO_IP Core Last Branch Record 6 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6C7H 1735 MSR_LASTBRANCH_7_TO_IP Core Last Branch Record 7 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 2-110 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-12. MSRs in Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.) Register Address Hex Dec 6C8H 1736 Register Name / Bit Fields MSR_LASTBRANCH_8_TO_IP Scope Core Bit Description Last Branch Record 8 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6C9H 1737 MSR_LASTBRANCH_9_TO_IP Core Last Branch Record 9 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6CAH 1738 MSR_LASTBRANCH_10_TO_IP Core Last Branch Record 10 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6CBH 1739 MSR_LASTBRANCH_11_TO_IP Core Last Branch Record 11 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6CCH 1740 MSR_LASTBRANCH_12_TO_IP Core Last Branch Record 12 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6CDH 1741 MSR_LASTBRANCH_13_TO_IP Core Last Branch Record 13 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6CEH 1742 MSR_LASTBRANCH_14_TO_IP Core Last Branch Record 14 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6CFH 1743 MSR_LASTBRANCH_15_TO_IP Core Last Branch Record 15 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6D0H 1744 MSR_LASTBRANCH_16_TO_IP Core Last Branch Record 16 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6D1H 1745 MSR_LASTBRANCH_17_TO_IP Core Last Branch Record 17 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6D2H 1746 MSR_LASTBRANCH_18_TO_IP Core Last Branch Record 18 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6D3H 1747 MSR_LASTBRANCH_19_TO_IP Core Last Branch Record 19To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6D4H 1748 MSR_LASTBRANCH_20_TO_IP Core Last Branch Record 20 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6D5H 1749 MSR_LASTBRANCH_21_TO_IP Core Last Branch Record 21 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6D6H 1750 MSR_LASTBRANCH_22_TO_IP Core Last Branch Record 22 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6D7H 1751 MSR_LASTBRANCH_23_TO_IP Core Last Branch Record 23 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6D8H 1752 MSR_LASTBRANCH_24_TO_IP Core Last Branch Record 24 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6D9H 1753 MSR_LASTBRANCH_25_TO_IP Core Last Branch Record 25 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6DAH 1754 MSR_LASTBRANCH_26_TO_IP Core Last Branch Record 26 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. Vol. 4 2-111 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-12. MSRs in Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.) Register Address Hex Dec 6DBH 1755 Register Name / Bit Fields MSR_LASTBRANCH_27_TO_IP Scope Core Bit Description Last Branch Record 27 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6DCH 1756 MSR_LASTBRANCH_28_TO_IP Core Last Branch Record 28 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6DDH 1757 MSR_LASTBRANCH_29_TO_IP Core Last Branch Record 29 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6DEH 1758 MSR_LASTBRANCH_30_TO_IP Core Last Branch Record 30 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6DFH 1759 MSR_LASTBRANCH_31_TO_IP Core Last Branch Record 31 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 802H 2050 IA32_X2APIC_APICID Core x2APIC ID register (R/O) 803H 2051 IA32_X2APIC_VERSION Core x2APIC Version register (R/O) 808H 2056 IA32_X2APIC_TPR Core x2APIC Task Priority register (R/W) 80AH 2058 IA32_X2APIC_PPR Core x2APIC Processor Priority register (R/O) 80BH 2059 IA32_X2APIC_EOI Core x2APIC EOI register (W/O) 80DH 2061 IA32_X2APIC_LDR Core x2APIC Logical Destination register (R/O) 80FH 2063 IA32_X2APIC_SIVR Core x2APIC Spurious Interrupt Vector register (R/W) 810H 2064 IA32_X2APIC_ISR0 Core x2APIC In-Service register bits [31:0] (R/O) 811H 2065 IA32_X2APIC_ISR1 Core x2APIC In-Service register bits [63:32] (R/O) 812H 2066 IA32_X2APIC_ISR2 Core x2APIC In-Service register bits [95:64] (R/O) 813H 2067 IA32_X2APIC_ISR3 Core x2APIC In-Service register bits [127:96] (R/O) 814H 2068 IA32_X2APIC_ISR4 Core x2APIC In-Service register bits [159:128] (R/O) 815H 2069 IA32_X2APIC_ISR5 Core x2APIC In-Service register bits [191:160] (R/O) 816H 2070 IA32_X2APIC_ISR6 Core x2APIC In-Service register bits [223:192] (R/O) 817H 2071 IA32_X2APIC_ISR7 Core x2APIC In-Service register bits [255:224] (R/O) 818H 2072 IA32_X2APIC_TMR0 Core x2APIC Trigger Mode register bits [31:0] (R/O) 819H 2073 IA32_X2APIC_TMR1 Core x2APIC Trigger Mode register bits [63:32] (R/O) 81AH 2074 IA32_X2APIC_TMR2 Core x2APIC Trigger Mode register bits [95:64] (R/O) 81BH 2075 IA32_X2APIC_TMR3 Core x2APIC Trigger Mode register bits [127:96] (R/O) 81CH 2076 IA32_X2APIC_TMR4 Core x2APIC Trigger Mode register bits [159:128] (R/O) 81DH 2077 IA32_X2APIC_TMR5 Core x2APIC Trigger Mode register bits [191:160] (R/O) 81EH 2078 IA32_X2APIC_TMR6 Core x2APIC Trigger Mode register bits [223:192] (R/O) 81FH 2079 IA32_X2APIC_TMR7 Core x2APIC Trigger Mode register bits [255:224] (R/O) 820H 2080 IA32_X2APIC_IRR0 Core x2APIC Interrupt Request register bits [31:0] (R/O) 821H 2081 IA32_X2APIC_IRR1 Core x2APIC Interrupt Request register bits [63:32] (R/O) 822H 2082 IA32_X2APIC_IRR2 Core x2APIC Interrupt Request register bits [95:64] (R/O) 823H 2083 IA32_X2APIC_IRR3 Core x2APIC Interrupt Request register bits [127:96] (R/O) 2-112 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-12. MSRs in Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.) Register Address Register Name / Bit Fields Scope Bit Description Hex Dec 824H 2084 IA32_X2APIC_IRR4 Core x2APIC Interrupt Request register bits [159:128] (R/O) 825H 2085 IA32_X2APIC_IRR5 Core x2APIC Interrupt Request register bits [191:160] (R/O) 826H 2086 IA32_X2APIC_IRR6 Core x2APIC Interrupt Request register bits [223:192] (R/O) 827H 2087 IA32_X2APIC_IRR7 Core x2APIC Interrupt Request register bits [255:224] (R/O) 828H 2088 IA32_X2APIC_ESR Core x2APIC Error Status register (R/W) 82FH 2095 IA32_X2APIC_LVT_CMCI Core x2APIC LVT Corrected Machine Check Interrupt register (R/W) 830H 2096 IA32_X2APIC_ICR Core x2APIC Interrupt Command register (R/W) 832H 2098 IA32_X2APIC_LVT_TIMER Core x2APIC LVT Timer Interrupt register (R/W) 833H 2099 IA32_X2APIC_LVT_THERMAL Core x2APIC LVT Thermal Sensor Interrupt register (R/W) 834H 2100 IA32_X2APIC_LVT_PMI Core x2APIC LVT Performance Monitor register (R/W) 835H 2101 IA32_X2APIC_LVT_LINT0 Core x2APIC LVT LINT0 register (R/W) 836H 2102 IA32_X2APIC_LVT_LINT1 Core x2APIC LVT LINT1 register (R/W) 837H 2103 IA32_X2APIC_LVT_ERROR Core x2APIC LVT Error register (R/W) 838H 2104 IA32_X2APIC_INIT_COUNT Core x2APIC Initial Count register (R/W) 839H 2105 IA32_X2APIC_CUR_COUNT Core x2APIC Current Count register (R/O) 83EH 2110 IA32_X2APIC_DIV_CONF Core x2APIC Divide Configuration register (R/W) 83FH 2111 IA32_X2APIC_SELF_IPI Core x2APIC Self IPI register (W/O) C8FH 3215 IA32_PQR_ASSOC Core Resource Association Register (R/W) D10H 3344 31:0 Reserved 33:32 COS (R/W) 63: 34 Reserved IA32_L2_QOS_MASK_0 Module L2 Class Of Service Mask - COS 0 (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=0. D11H 3345 0:7 CBM: Bit vector of available L2 ways for COS 0 enforcement. 63:8 Reserved IA32_L2_QOS_MASK_1 Module L2 Class Of Service Mask - COS 1 (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=1. 0:7 CBM: Bit vector of available L2 ways for COS 0 enforcement. 63:8 D12H 3346 IA32_L2_QOS_MASK_2 Reserved Module L2 Class Of Service Mask - COS 2 (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=2. 0:7 CBM: Bit vector of available L2 ways for COS 0 enforcement. Vol. 4 2-113 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-12. MSRs in Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.) Register Address Hex Register Name / Bit Fields Scope Dec 63:8 D13H Bit Description 3347 Reserved IA32_L2_QOS_MASK_3 Package L2 Class Of Service Mask - COS 3 (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=3. 0:19 CBM: Bit vector of available L2 ways for COS 3 enforcement. 63:20 Reserved D90H 3472 IA32_BNDCFGS Core See Table 2-2. DA0H 3488 IA32_XSS Core See Table 2-2. See Table 2-6, and Table 2-12 for MSR definitions applicable to processors with CPUID signature 06_5CH. 2.6 MSRS IN INTEL ATOM PROCESSORS BASED ON GOLDMONT PLUS MICROARCHITECTURE Intel Atom processors based on the Goldmont Plus microarchitecture support MSRs listed in Table 2-6, Table 2-12 and Table 2-13. These processors have a CPUID signature with DisplayFamily_DisplayModel of 06_7AH; see Table 2-1. For an MSR listed in Table 2-13 that also appears in the model-specific tables of prior generations, Table 2-13 supercede prior generation tables. In the Goldmont Plus microarchitecture, the scope column indicates the following: “Core” means each processor core has a separate MSR, or a bit field not shared with another processor core. “Module” means the MSR or the bit field is shared by a pair of processor cores in the physical package. “Package” means all processor cores in the physical package share the same MSR or bit interface. Table 2-13. MSRs in Intel Atom Processors Based on the Goldmont Plus Microarchitecture Register Address Hex Dec 3AH 58 Register Name / Bit Fields IA32_FEATURE_CONTROL Scope Core Bit Description Control Features in Intel 64Processor (R/W) See Table 2-2. 0 Lock (R/WL) 1 Enable VMX inside SMX operation (R/WL) 2 Enable VMX outside SMX operation (R/WL) 14:8 SENTER local functions enables (R/WL) 15 SENTER global functions enable (R/WL) 17 SGX Launch Control Enable (R/WL) This bit must be set to enable runtime reconfiguration of SGX Launch Control via IA32_SGXLEPUBKEYHASHn MSR. Valid if CPUID.(EAX=07H, ECX=0H): ECX[30] = 1. 8CH 2-114 Vol. 4 140 18 SGX global functions enable (R/WL) 63:19 Reserved IA32_SGXLEPUBKEYHASH0 Core See Table 2-2. MODEL-SPECIFIC REGISTERS (MSRS) Table 2-13. MSRs in Intel Atom Processors Based on the Goldmont Plus Microarchitecture (Contd.) Register Address Register Name / Bit Fields Scope Bit Description Hex Dec 8DH 141 IA32_SGXLEPUBKEYHASH1 Core See Table 2-2. 8EH 142 IA32_SGXLEPUBKEYHASH2 Core See Table 2-2. 8FH 143 IA32_SGXLEPUBKEYHASH3 Core See Table 2-2. 3F1H 1009 MSR_PEBS_ENABLE Core (R/W) See Table 2-2. See Section 18.6.2.4, “Processor Event Based Sampling (PEBS).” 570H 1392 0 Enable PEBS trigger and recording for the programmed event (precise or otherwise) on IA32_PMC0. 1 Enable PEBS trigger and recording for the programmed event (precise or otherwise) on IA32_PMC1. 2 Enable PEBS trigger and recording for the programmed event (precise or otherwise) on IA32_PMC2. 3 Enable PEBS trigger and recording for the programmed event (precise or otherwise) on IA32_PMC3. 31:4 Reserved 32 Enable PEBS trigger and recording for IA32_FIXED_CTR0. 33 Enable PEBS trigger and recording for IA32_FIXED_CTR1. 34 Enable PEBS trigger and recording for IA32_FIXED_CTR2. 63:35 Reserved IA32_RTIT_CTL Core Trace Control Register (R/W) 0 TraceEn 1 CYCEn 2 OS 3 User 4 PwrEvtEn 5 FUPonPTW 6 FabricEn 7 CR3 filter 8 ToPA Writing 0 will #GP if also setting TraceEn. 9 MTCEn 10 TSCEn 11 DisRETC 12 PTWEn 13 BranchEn Vol. 4 2-115 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-13. MSRs in Intel Atom Processors Based on the Goldmont Plus Microarchitecture (Contd.) Register Address Hex 680H Register Name / Bit Fields Scope Bit Description Dec 1664 17:14 MTCFreq 18 Reserved, must be zero. 22:19 CYCThresh 23 Reserved, must be zero. 27:24 PSBFreq 31:28 Reserved, must be zero. 35:32 ADDR0_CFG 39:36 ADDR1_CFG 63:40 Reserved, must be zero. MSR_LASTBRANCH_0_FROM_IP Core Last Branch Record 0 From IP (R/W) One of the three MSRs that make up the first entry of the 32-entry LBR stack. The From_IP part of the stack contains pointers to the source instruction. See also: • Last Branch Record Stack TOS at 1C9H. • Section 17.7, “Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Goldmont Plus Microarchitecture.” 681H 69FH 1665 1695 MSR_LASTBRANCH_i_FROM_IP 6C0H 1728 MSR_LASTBRANCH_0_TO_IP Core Last Branch Record i From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP; i = 1-31. Core Last Branch Record 0 To IP (R/W) One of the three MSRs that make up the first entry of the 32-entry LBR stack. The To_IP part of the stack contains pointers to the Destination instruction. See also: • Section 17.7, “Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Goldmont Plus Microarchitecture.” 6C1H 6DFH 1729 1759 MSR_LASTBRANCH_i_TO_IP DC0H 3520 MSR_LASTBRANCH_INFO_0 Core Last Branch Record i To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP; i = 131. Core Last Branch Record 0 Additional Information (R/W) One of the three MSRs that make up the first entry of the 32-entry LBR stack. This part of the stack contains flag and elapsed cycle information. See also: • Last Branch Record Stack TOS at 1C9H. • Section 17.9.1, “LBR Stack.” DC1H 3521 MSR_LASTBRANCH_INFO_1 Core DC2H 3522 MSR_LASTBRANCH_INFO_2 Core Last Branch Record 1 Additional Information (R/W) See description of MSR_LASTBRANCH_INFO_0. Last Branch Record 2 Additional Information (R/W) See description of MSR_LASTBRANCH_INFO_0. DC3H 3523 MSR_LASTBRANCH_INFO_3 Core Last Branch Record 3 Additional Information (R/W) See description of MSR_LASTBRANCH_INFO_0. 2-116 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-13. MSRs in Intel Atom Processors Based on the Goldmont Plus Microarchitecture (Contd.) Register Address Hex Dec DC4H 3524 Register Name / Bit Fields MSR_LASTBRANCH_INFO_4 Scope Core Bit Description Last Branch Record 4 Additional Information (R/W) See description of MSR_LASTBRANCH_INFO_0. DC5H 3525 MSR_LASTBRANCH_INFO_5 Core Last Branch Record 5 Additional Information (R/W) See description of MSR_LASTBRANCH_INFO_0. DC6H 3526 MSR_LASTBRANCH_INFO_6 Core Last Branch Record 6 Additional Information (R/W) See description of MSR_LASTBRANCH_INFO_0. DC7H 3527 MSR_LASTBRANCH_INFO_7 Core Last Branch Record 7 Additional Information (R/W) See description of MSR_LASTBRANCH_INFO_0. DC8H 3528 MSR_LASTBRANCH_INFO_8 Core Last Branch Record 8 Additional Information (R/W) See description of MSR_LASTBRANCH_INFO_0. DC9H 3529 MSR_LASTBRANCH_INFO_9 Core Last Branch Record 9 Additional Information (R/W) See description of MSR_LASTBRANCH_INFO_0. DCAH 3530 MSR_LASTBRANCH_INFO_10 Core Last Branch Record 10 Additional Information (R/W) See description of MSR_LASTBRANCH_INFO_0. DCBH 3531 MSR_LASTBRANCH_INFO_11 Core Last Branch Record 11 Additional Information (R/W) See description of MSR_LASTBRANCH_INFO_0. DCCH 3532 MSR_LASTBRANCH_INFO_12 Core Last Branch Record 12 Additional Information (R/W) See description of MSR_LASTBRANCH_INFO_0. DCDH 3533 MSR_LASTBRANCH_INFO_13 Core Last Branch Record 13 Additional Information (R/W) See description of MSR_LASTBRANCH_INFO_0. DCEH 3534 MSR_LASTBRANCH_INFO_14 Core Last Branch Record 14 Additional Information (R/W) See description of MSR_LASTBRANCH_INFO_0. DCFH 3535 MSR_LASTBRANCH_INFO_15 Core Last Branch Record 15 Additional Information (R/W) See description of MSR_LASTBRANCH_INFO_0. DD0H 3536 MSR_LASTBRANCH_INFO_16 Core Last Branch Record 16 Additional Information (R/W) See description of MSR_LASTBRANCH_INFO_0. DD1H 3537 MSR_LASTBRANCH_INFO_17 Core Last Branch Record 17 Additional Information (R/W) See description of MSR_LASTBRANCH_INFO_0. DD2H 3538 MSR_LASTBRANCH_INFO_18 Core Last Branch Record 18 Additional Information (R/W) See description of MSR_LASTBRANCH_INFO_0. DD3H 3539 MSR_LASTBRANCH_INFO_19 Core Last Branch Record 19 Additional Information (R/W) See description of MSR_LASTBRANCH_INFO_0. DD4H 3520 MSR_LASTBRANCH_INFO_20 Core Last Branch Record 20 Additional Information (R/W) See description of MSR_LASTBRANCH_INFO_0. DD5H 3521 MSR_LASTBRANCH_INFO_21 Core Last Branch Record 21 Additional Information (R/W) See description of MSR_LASTBRANCH_INFO_0. DD6H 3522 MSR_LASTBRANCH_INFO_22 Core Last Branch Record 22 Additional Information (R/W) See description of MSR_LASTBRANCH_INFO_0. Vol. 4 2-117 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-13. MSRs in Intel Atom Processors Based on the Goldmont Plus Microarchitecture (Contd.) Register Address Hex Dec DD7H 3523 Register Name / Bit Fields MSR_LASTBRANCH_INFO_23 Scope Core Bit Description Last Branch Record 23 Additional Information (R/W) See description of MSR_LASTBRANCH_INFO_0. DD8H 3524 MSR_LASTBRANCH_INFO_24 Core Last Branch Record 24 Additional Information (R/W) See description of MSR_LASTBRANCH_INFO_0. DD9H 3525 MSR_LASTBRANCH_INFO_25 Core Last Branch Record 25 Additional Information (R/W) See description of MSR_LASTBRANCH_INFO_0. DDAH 3526 MSR_LASTBRANCH_INFO_26 Core Last Branch Record 26 Additional Information (R/W) See description of MSR_LASTBRANCH_INFO_0. DDBH 3527 MSR_LASTBRANCH_INFO_27 Core Last Branch Record 27 Additional Information (R/W) See description of MSR_LASTBRANCH_INFO_0. DDCH 3528 MSR_LASTBRANCH_INFO_28 Core Last Branch Record 28 Additional Information (R/W) See description of MSR_LASTBRANCH_INFO_0. DDDH 3529 MSR_LASTBRANCH_INFO_29 Core Last Branch Record 29 Additional Information (R/W) See description of MSR_LASTBRANCH_INFO_0. DDEH 3530 MSR_LASTBRANCH_INFO_30 Core Last Branch Record 30 Additional Information (R/W) See description of MSR_LASTBRANCH_INFO_0. DDFH 3531 MSR_LASTBRANCH_INFO_31 Core Last Branch Record 31 Additional Information (R/W) See description of MSR_LASTBRANCH_INFO_0. See Table 2-6, Table 2-12 and Table 2-13 for MSR definitions applicable to processors with CPUID signature 06_7AH. 2.7 MSRS IN INTEL ATOM PROCESSORS BASED ON TREMONT MICROARCHITECTURE Intel Atom processors based on the Tremont microarchitecture support MSRs listed in Table 2-6, Table 2-12, Table 2-13 and Table 2-14. These processors have a CPUID signature with DisplayFamily_DisplayModel of 06_86H; see Table 2-1. For an MSR listed in Table 2-14 that also appears in the model-specific tables of prior generations, Table 2-14 supercede prior generation tables. In the Tremont microarchitecture, the scope column indicates the following: “Core” means each processor core has a separate MSR, or a bit field not shared with another processor core. “Module” means the MSR or the bit field is shared by a pair of processor cores in the physical package. “Package” means all processor cores in the physical package share the same MSR or bit interface. 2-118 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-14. MSRs in Intel Atom Processors Based on the Tremont Microarchitecture Register Address Hex Dec 33H 51 Register Name / Bit Fields TEST_CTRL Scope Core Bit Description Test Control Register 28:0 Reserved. 29 Enable #AC(0) exception for split locked accesses: Cause #AC(0) exception for split locked access at all CPL irrespective of CR0.AM or EFLAGS.AC. If bits 29 and 31 are both set, bit 29 takes precedence. CFH 207 30 Reserved. 31 Disable LOCK# assertion for split locked access. IA32_CORE_CAPABILITY Core IA32 Core Capability Register See Table 2-2. 3F1H 1009 MSR_PEBS_ENABLE Core (R/W) See Table 2-2. See Section 18.6.2.4, “Processor Event Based Sampling (PEBS)”. n:0 Enable PEBS trigger and recording for the programmed event (precise or otherwise) on IA32_PMCx. The maximum value n can be determined from CPUID.0AH:EAX[15:8]. 31:n+1 Reserved. 32+m:32 Enable PEBS trigger and recording for IA32_FIXED_CTRx. The maximum value m can be determined from CPUID.0AH:EDX[4:0]. 59:33+m Reserved. 60 Pend a PerfMon Interrupt (PMI) after each PEBS event. 62:61 Specifies PEBS output destination. Encodings: 00B: DS Save Area 01B: Intel PT trace output. Supported if IA32_PERF_CAPABILITIES.PEBS_OUTPUT_PT_AVAIL[ 16] and CPUID.07H.0.EBX[25] are set. 10B: Reserved 11B: Reserved 1309H 130BH 14C1H 14C8H 4873 4875 5313 5320 63 Reserved. MSR_RELOAD_FIXED_CTRx Reload value for IA32_FIXED_CTRx (R/W) 47:0 Value loaded into IA32_FIXED_CTRx when a PEBS record is generated while PEBS_EN_FIXEDx = 1 and PEBS_OUTPUT = 01B in IA32_PEBS_ENABLE, and FIXED_CTRx is overflowed. 63:48 Reserved. MSR_RELOAD_PMCx Reload value for IA32_PMCx (R/W) 47:0 Value loaded into IA32_PMCx when a PEBS record is generated while PEBS_EN_PMCx = 1 and PEBS_OUTPUT = 01B in IA32_PEBS_ENABLE, and PMCx is overflowed. 63:48 Reserved. Vol. 4 2-119 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-14. MSRs in Intel Atom Processors Based on the Tremont Microarchitecture (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec See Table 2-6, Table 2-12, Table 2-13 and Table 2-14 for MSR definitions applicable to processors with CPUID signature 06_86H. 2.8 MSRS IN THE INTEL® MICROARCHITECTURE CODE NAME NEHALEM Table 2-15 lists model-specific registers (MSRs) that are common for Intel® microarchitecture code name Nehalem. These include Intel Core i7 and i5 processor family. These processors have a CPUID signature with DisplayFamily_DisplayModel of 06_1AH, 06_1EH, 06_1FH, 06_2EH, see Table 2-1. Additional MSRs specific to 06_1AH, 06_1EH, 06_1FH are listed in Table 2-16. Some MSRs listed in these tables are used by BIOS. More information about these MSR can be found at http://biosbits.org. The column “Scope” represents the package/core/thread scope of individual bit field of an MSR. “Thread” means this bit field must be programmed on each logical processor independently. “Core” means the bit field must be programmed on each processor core independently, logical processors in the same core will be affected by change of this bit on the other logical processor in the same core. “Package” means the bit field must be programmed once for each physical package. Change of a bit filed with a package scope will affect all logical processors in that physical package. Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem Register Address Register Name / Bit Fields Scope Bit Description Hex Dec 0H 0 IA32_P5_MC_ADDR Thread See Section 2.23, “MSRs in Pentium Processors.” 1H 1 IA32_P5_MC_TYPE Thread See Section 2.23, “MSRs in Pentium Processors.” 6H 6 IA32_MONITOR_FILTER_SIZE Thread See Section 8.10.5, “Monitor/Mwait Address Range Determination” and Table 2-2. 10H 16 IA32_TIME_STAMP_COUNTER Thread See Section 17.17, “Time-Stamp Counter,” and see Table 2-2. 17H 23 IA32_PLATFORM_ID Package Platform ID (R) See Table 2-2. 17H 23 MSR_PLATFORM_ID Package Model Specific Platform ID (R) 49:0 Reserved 52:50 See Table 2-2. 63:53 Reserved 1BH 27 IA32_APIC_BASE Thread See Section 10.4.4, “Local APIC Status and Location,” and Table 2-2. 34H 52 MSR_SMI_COUNT Thread SMI Counter (R/O) 31:0 SMI Count (R/O) Running count of SMI events since last RESET. 63:32 2-120 Vol. 4 Reserved MODEL-SPECIFIC REGISTERS (MSRS) Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.) Register Address Hex Dec 3AH 58 Register Name / Bit Fields IA32_FEATURE_CONTROL Scope Thread Bit Description Control Features in Intel 64Processor (R/W) See Table 2-2. 79H 121 IA32_BIOS_UPDT_TRIG Core BIOS Update Trigger Register (W) See Table 2-2. 8BH 139 IA32_BIOS_SIGN_ID Thread BIOS Update Signature ID (RO) See Table 2-2. C1H 193 IA32_PMC0 Thread Performance Counter Register See Table 2-2. C2H 194 IA32_PMC1 Thread Performance Counter Register See Table 2-2. C3H 195 IA32_PMC2 Thread Performance Counter Register See Table 2-2. C4H 196 IA32_PMC3 Thread Performance Counter Register See Table 2-2. CEH 206 MSR_PLATFORM_INFO Package Platform Information Contains power management and other model specific features enumeration. See http://biosbits.org. 7:0 15:8 Reserved Package Maximum Non-Turbo Ratio (R/O) This is the ratio of the frequency that invariant TSC runs at. The invariant TSC frequency can be computed by multiplying this ratio by 133.33 MHz. 27:16 28 Reserved Package Programmable Ratio Limit for Turbo Mode (R/O) When set to 1, indicates that Programmable Ratio Limit for Turbo mode is enabled. When set to 0, indicates Programmable Ratio Limit for Turbo mode is disabled. 29 Package Programmable TDC-TDP Limit for Turbo Mode (R/O) When set to 1, indicates that TDC and TDP Limits for Turbo mode are programmable. When set to 0, indicates TDC and TDP Limits for Turbo mode are not programmable. 39:30 47:40 Reserved Package Maximum Efficiency Ratio (R/O) This is the minimum ratio (maximum efficiency) that the processor can operate, in units of 133.33MHz. 63:48 E2H 226 MSR_PKG_CST_CONFIG_CONTROL Reserved Core C-State Configuration Control (R/W) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. See http://biosbits.org. Vol. 4 2-121 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 2:0 Package C-State Limit (R/W) Specifies the lowest processor-specific C-state code name (consuming the least power) for the package. The default is set as factory-configured package C-state limit. The following C-state code name encodings are supported: 000b: C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b) 010b: C3 011b: C6 100b: C7 101b and 110b: Reserved 111: No package C-state limit. Note: This field cannot be used to limit package C-state to C3. 9:3 Reserved 10 I/O MWAIT Redirection Enable (R/W) When set, will map IO_read instructions sent to IO register specified by MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions. 14:11 Reserved 15 CFG Lock (R/WO) When set, locks bits 15:0 of this register until next reset. 23:16 Reserved 24 Interrupt filtering enable (R/W) When set, processor cores in a deep C-State will wake only when the event message is destined for that core. When 0, all processor cores in a deep C-State will wake for an event message. 25 C3 state auto demotion enable (R/W) When set, the processor will conditionally demote C6/C7 requests to C3 based on uncore auto-demote information. 26 C1 state auto demotion enable (R/W) When set, the processor will conditionally demote C3/C6/C7 requests to C1 based on uncore auto-demote information. 2-122 Vol. 4 27 Enable C3 Undemotion (R/W) 28 Enable C1 Undemotion (R/W) 29 Package C State Demotion Enable (R/W) MODEL-SPECIFIC REGISTERS (MSRS) Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.) Register Address Hex E4H Register Name / Bit Fields Scope Bit Description Dec 228 30 Package C State UnDemotion Enable (R/W) 63:31 Reserved MSR_PMG_IO_CAPTURE_BASE Core Power Management IO Redirection in C-state (R/W) See http://biosbits.org. 15:0 LVL_2 Base Address (R/W) Specifies the base address visible to software for IO redirection. If IO MWAIT Redirection is enabled, reads to this address will be consumed by the power management logic and decoded to MWAIT instructions. When IO port address redirection is enabled, this is the IO port address reported to the OS/software. 18:16 C-state Range (R/W) Specifies the encoding value of the maximum C-State code name to be included when IO read to MWAIT redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3 is the max C-State to include. 001b - C6 is the max C-State to include. 010b - C7 is the max C-State to include. 63:19 E7H 231 IA32_MPERF Reserved Thread Maximum Performance Frequency Clock Count (RW) See Table 2-2. E8H 232 IA32_APERF Thread Actual Performance Frequency Clock Count (RW) See Table 2-2. FEH 254 IA32_MTRRCAP Thread See Table 2-2. 174H 372 IA32_SYSENTER_CS Thread See Table 2-2. 175H 373 IA32_SYSENTER_ESP Thread See Table 2-2. 176H 374 IA32_SYSENTER_EIP Thread See Table 2-2. 179H 377 IA32_MCG_CAP Thread See Table 2-2. 17AH 378 IA32_MCG_STATUS Thread Global Machine Check Status 0 RIPV When set, bit indicates that the instruction addressed by the instruction pointer pushed on the stack (when the machine check was generated) can be used to restart the program. If cleared, the program cannot be reliably restarted. 1 EIPV When set, bit indicates that the instruction addressed by the instruction pointer pushed on the stack (when the machine check was generated) is directly associated with the error. Vol. 4 2-123 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 2 MCIP When set, bit indicates that a machine check has been generated. If a second machine check is detected while this bit is still set, the processor enters a shutdown state. Software should write this bit to 0 after processing a machine check exception. 63:3 186H 390 IA32_PERFEVTSEL0 Reserved Thread See Table 2-2. 7:0 Event Select 15:8 UMask 16 USR 17 OS 18 Edge 19 PC 20 INT 21 AnyThread 22 EN 23 INV 31:24 CMASK 63:32 Reserved 187H 391 IA32_PERFEVTSEL1 Thread See Table 2-2. 188H 392 IA32_PERFEVTSEL2 Thread See Table 2-2. 189H 393 IA32_PERFEVTSEL3 Thread See Table 2-2. 198H 408 IA32_PERF_STATUS Core See Table 2-2. 15:0 Current Performance State Value. 63:16 Reserved 199H 409 IA32_PERF_CTL Thread 19AH 410 IA32_CLOCK_MODULATION Thread See Table 2-2. Clock Modulation (R/W) See Table 2-2. IA32_CLOCK_MODULATION MSR was originally named IA32_THERM_CONTROL MSR. 0 19BH 411 Reserved 3:1 On demand Clock Modulation Duty Cycle (R/W) 4 On demand Clock Modulation Enable (R/W) 63:5 Reserved IA32_THERM_INTERRUPT Core Thermal Interrupt Control (R/W) See Table 2-2. 2-124 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.) Register Address Hex Dec 19CH 412 Register Name / Bit Fields IA32_THERM_STATUS Scope Core Bit Description Thermal Monitor Status (R/W) See Table 2-2. 1A0H 416 IA32_MISC_ENABLE Enable Misc. Processor Features (R/W) Allows a variety of processor functions to be enabled and disabled. 0 Thread Fast-Strings Enable See Table 2-2. 2:1 3 Reserved Thread Automatic Thermal Control Circuit Enable (R/W) See Table 2-2. Default value is 1. 6:4 7 Reserved Thread Performance Monitoring Available (R) See Table 2-2. 10:8 11 Reserved Thread Branch Trace Storage Unavailable (RO) See Table 2-2. 12 Thread Processor Event Based Sampling Unavailable (RO) See Table 2-2. 15:13 16 Reserved Package Enhanced Intel SpeedStep Technology Enable (R/W) See Table 2-2. 18 Thread 21:19 ENABLE MONITOR FSM. (R/W) See Table 2-2. Reserved 22 Thread 23 Thread Limit CPUID Maxval (R/W) See Table 2-2. xTPR Message Disable (R/W) See Table 2-2. 33:24 34 Reserved Thread XD Bit Disable (R/W) See Table 2-2. 37:35 Reserved Vol. 4 2-125 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 38 Package Turbo Mode Disable (R/W) When set to 1 on processors that support Intel Turbo Boost Technology, the turbo mode feature is disabled and the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H: EAX[1] reports the processor’s support of turbo mode is enabled. Note: The power-on default value is used by BIOS to detect hardware support of turbo mode. If the poweron default value is 1, turbo mode is available in the processor. If the power-on default value is 0, turbo mode is not available. 63:39 1A2H 418 MSR_TEMPERATURE_TARGET Reserved Thread 15:0 Temperature Target Reserved 23:16 Temperature Target (R) The minimum temperature at which PROCHOT# will be asserted. The value is degrees C. 1A4H 420 63:24 Reserved MSR_MISC_FEATURE_CONTROL Miscellaneous Feature Control (R/W) 0 Core L2 Hardware Prefetcher Disable (R/W) If 1, disables the L2 hardware prefetcher, which fetches additional lines of code or data into the L2 cache. 1 Core L2 Adjacent Cache Line Prefetcher Disable (R/W) If 1, disables the adjacent cache line prefetcher, which fetches the cache line that comprises a cache line pair (128 bytes). 2 Core DCU Hardware Prefetcher Disable (R/W) If 1, disables the L1 data cache prefetcher, which fetches the next cache line into L1 data cache. 3 Core DCU IP Prefetcher Disable (R/W) If 1, disables the L1 data cache IP prefetcher, which uses sequential load history (based on instruction pointer of previous loads) to determine whether to prefetch additional lines. 63:4 1A6H 422 MSR_OFFCORE_RSP_0 1AAH 426 MSR_MISC_PWR_MGMT Reserved Thread Offcore Response Event Select Register (R/W) Miscellaneous Power Management Control Various model specific features enumeration. See http://biosbits.org. 2-126 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 0 Package EIST Hardware Coordination Disable (R/W) When 0, enables hardware coordination of Enhanced Intel Speedstep Technology request from processor cores. When 1, disables hardware coordination of Enhanced Intel Speedstep Technology requests. 1 Thread Energy/Performance Bias Enable (R/W) This bit makes the IA32_ENERGY_PERF_BIAS register (MSR 1B0h) visible to software with Ring 0 privileges. This bit’s status (1 or 0) is also reflected by CPUID.(EAX=06h):ECX[3]. 1ACH 428 63:2 Reserved MSR_TURBO_POWER_CURRENT_LIMIT See http://biosbits.org. 14:0 Package TDP Limit (R/W) TDP limit in 1/8 Watt granularity. 15 Package TDP Limit Override Enable (R/W) A value = 0 indicates override is not active; a value = 1 indicates override is active. 30:16 Package TDC Limit (R/W) TDC limit in 1/8 Amp granularity. 31 Package TDC Limit Override Enable (R/W) A value = 0 indicates override is not active; a value = 1 indicates override is active. 63:32 1ADH 429 MSR_TURBO_RATIO_LIMIT Reserved Package Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0. RW if MSR_PLATFORM_INFO.[28] = 1. 7:0 Package Maximum Ratio Limit for 1C Maximum turbo ratio limit of 1 core active. 15:8 Package Maximum Ratio Limit for 2C Maximum turbo ratio limit of 2 core active. 23:16 Package Maximum Ratio Limit for 3C Maximum turbo ratio limit of 3 core active. 31:24 Package Maximum Ratio Limit for 4C Maximum turbo ratio limit of 4 core active. 63:32 1C8H 456 MSR_LBR_SELECT Reserved Core Last Branch Record Filtering Select Register (R/W) See Section 17.9.2, “Filtering of Last Branch Records.” 0 CPL_EQ_0 1 CPL_NEQ_0 2 JCC Vol. 4 2-127 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.) Register Address Hex 1C9H Register Name / Bit Fields Scope Bit Description Dec 457 3 NEAR_REL_CALL 4 NEAR_IND_CALL 5 NEAR_RET 6 NEAR_IND_JMP 7 NEAR_REL_JMP 8 FAR_BRANCH 63:9 Reserved MSR_LASTBRANCH_TOS Thread Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) that points to the MSR containing the most recent branch record. See MSR_LASTBRANCH_0_FROM_IP (at 680H). 1D9H 473 IA32_DEBUGCTL Thread 1DDH 477 MSR_LER_FROM_LIP Thread Debug Control (R/W) See Table 2-2. Last Exception Record From Linear IP (R) Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled. 1DEH 478 MSR_LER_TO_LIP Thread Last Exception Record To Linear IP (R) This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled. 1F2H 498 IA32_SMRR_PHYSBASE Core See Table 2-2. 1F3H 499 IA32_SMRR_PHYSMASK Core See Table 2-2. 1FCH 508 MSR_POWER_CTL Core Power Control Register See http://biosbits.org. 0 1 Reserved Package C1E Enable (R/W) When set to ‘1’, will enable the CPU to switch to the Minimum Enhanced Intel SpeedStep Technology operating point when all execution cores enter MWAIT (C1). 63:2 Reserved 200H 512 IA32_MTRR_PHYSBASE0 Thread See Table 2-2. 201H 513 IA32_MTRR_PHYSMASK0 Thread See Table 2-2. 202H 514 IA32_MTRR_PHYSBASE1 Thread See Table 2-2. 203H 515 IA32_MTRR_PHYSMASK1 Thread See Table 2-2. 204H 516 IA32_MTRR_PHYSBASE2 Thread See Table 2-2. 2-128 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.) Register Address Register Name / Bit Fields Scope Bit Description Hex Dec 205H 517 IA32_MTRR_PHYSMASK2 Thread See Table 2-2. 206H 518 IA32_MTRR_PHYSBASE3 Thread See Table 2-2. 207H 519 IA32_MTRR_PHYSMASK3 Thread See Table 2-2. 208H 520 IA32_MTRR_PHYSBASE4 Thread See Table 2-2. 209H 521 IA32_MTRR_PHYSMASK4 Thread See Table 2-2. 20AH 522 IA32_MTRR_PHYSBASE5 Thread See Table 2-2. 20BH 523 IA32_MTRR_PHYSMASK5 Thread See Table 2-2. 20CH 524 IA32_MTRR_PHYSBASE6 Thread See Table 2-2. 20DH 525 IA32_MTRR_PHYSMASK6 Thread See Table 2-2. 20EH 526 IA32_MTRR_PHYSBASE7 Thread See Table 2-2. 20FH 527 IA32_MTRR_PHYSMASK7 Thread See Table 2-2. 210H 528 IA32_MTRR_PHYSBASE8 Thread See Table 2-2. 211H 529 IA32_MTRR_PHYSMASK8 Thread See Table 2-2. 212H 530 IA32_MTRR_PHYSBASE9 Thread See Table 2-2. 213H 531 IA32_MTRR_PHYSMASK9 Thread See Table 2-2. 250H 592 IA32_MTRR_FIX64K_00000 Thread See Table 2-2. 258H 600 IA32_MTRR_FIX16K_80000 Thread See Table 2-2. 259H 601 IA32_MTRR_FIX16K_A0000 Thread See Table 2-2. 268H 616 IA32_MTRR_FIX4K_C0000 Thread See Table 2-2. 269H 617 IA32_MTRR_FIX4K_C8000 Thread See Table 2-2. 26AH 618 IA32_MTRR_FIX4K_D0000 Thread See Table 2-2. 26BH 619 IA32_MTRR_FIX4K_D8000 Thread See Table 2-2. 26CH 620 IA32_MTRR_FIX4K_E0000 Thread See Table 2-2. 26DH 621 IA32_MTRR_FIX4K_E8000 Thread See Table 2-2. 26EH 622 IA32_MTRR_FIX4K_F0000 Thread See Table 2-2. 26FH 623 IA32_MTRR_FIX4K_F8000 Thread See Table 2-2. 277H 631 IA32_PAT Thread See Table 2-2. 280H 640 IA32_MC0_CTL2 Package See Table 2-2. 281H 641 IA32_MC1_CTL2 Package See Table 2-2. 282H 642 IA32_MC2_CTL2 Core See Table 2-2. 283H 643 IA32_MC3_CTL2 Core See Table 2-2. 284H 644 IA32_MC4_CTL2 Core See Table 2-2. 285H 645 IA32_MC5_CTL2 Core See Table 2-2. 286H 646 IA32_MC6_CTL2 Package See Table 2-2. 287H 647 IA32_MC7_CTL2 Package See Table 2-2. 288H 648 IA32_MC8_CTL2 Package See Table 2-2. Vol. 4 2-129 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.) Register Address Hex Dec 2FFH 767 Register Name / Bit Fields IA32_MTRR_DEF_TYPE Scope Thread Bit Description Default Memory Types (R/W) See Table 2-2. 309H 777 IA32_FIXED_CTR0 Thread Fixed-Function Performance Counter Register 0 (R/W) See Table 2-2. 30AH 778 IA32_FIXED_CTR1 Thread Fixed-Function Performance Counter Register 1 (R/W) See Table 2-2. 30BH 779 IA32_FIXED_CTR2 Thread Fixed-Function Performance Counter Register 2 (R/W) See Table 2-2. 345H 837 IA32_PERF_CAPABILITIES Thread 5:0 See Table 2-2. See Section 17.4.1, “IA32_DEBUGCTL MSR.” LBR Format See Table 2-2. 6 PEBS Record Format 7 PEBSSaveArchRegs See Table 2-2. 11:8 PEBS_REC_FORMAT See Table 2-2. 12 SMM_FREEZE See Table 2-2. 63:13 Reserved 38DH 909 IA32_FIXED_CTR_CTRL Thread Fixed-Function-Counter Control Register (R/W) 38EH 910 IA32_PERF_GLOBAL_STATUS Thread See Table 2-2. See Section 18.6.2.2, “Global Counter Control Facilities.” 38EH 910 MSR_PERF_GLOBAL_STATUS Thread Provides single-bit status used by software to query the overflow condition of each performance counter. (RO) See Table 2-2. 61 UNC_Ovf Uncore overflowed if 1. 38FH 911 IA32_PERF_GLOBAL_CTRL Thread See Table 2-2. See Section 18.6.2.2, “Global Counter Control Facilities.” 390H 912 IA32_PERF_GLOBAL_OVF_CTRL Thread See Table 2-2. See Section 18.6.2.2, “Global Counter Control Facilities.” Allows software to clear counter overflow conditions on any combination of fixedfunction PMCs (IA32_FIXED_CTRx) or general-purpose PMCs via a single WRMSR. 390H 912 MSR_PERF_GLOBAL_OVF_CTRL Thread (R/W) 61 CLR_UNC_Ovf Set 1 to clear UNC_Ovf. 2-130 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.) Register Address Hex Dec 3F1H 1009 3F6H 1014 Register Name / Bit Fields MSR_PEBS_ENABLE Scope Thread Enable PEBS on IA32_PMC0 (R/W) 1 Enable PEBS on IA32_PMC1 (R/W) 2 Enable PEBS on IA32_PMC2 (R/W) 3 Enable PEBS on IA32_PMC3 (R/W) 31:4 Reserved 32 Enable Load Latency on IA32_PMC0 (R/W) 33 Enable Load Latency on IA32_PMC1 (R/W) 34 Enable Load Latency on IA32_PMC2 (R/W) 35 Enable Load Latency on IA32_PMC3 (R/W) 63:36 Reserved MSR_PEBS_LD_LAT Thread MSR_PKG_C3_RESIDENCY See Section 18.3.1.1.2, “Load Latency Performance Monitoring Facility.” Minimum threshold latency value of tagged load operation that will be counted. (R/W) 63:36 1016 See Section 18.3.1.1.1, “Processor Event Based Sampling (PEBS).” 0 15:0 3F8H Bit Description Reserved Package 63:0 Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C3 Residency Counter (R/O) Value since last reset that this package is in processorspecific C3 states. Count at the same frequency as the TSC. 3F9H 1017 MSR_PKG_C6_RESIDENCY Package 63:0 Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C6 Residency Counter (R/O) Value since last reset that this package is in processorspecific C6 states. Count at the same frequency as the TSC. 3FAH 1018 MSR_PKG_C7_RESIDENCY Package 63:0 Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C7 Residency Counter (R/O) Value since last reset that this package is in processorspecific C7 states. Count at the same frequency as the TSC. 3FCH 1020 MSR_CORE_C3_RESIDENCY Core Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. Vol. 4 2-131 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 63:0 CORE C3 Residency Counter (R/O) Value since last reset that this core is in processorspecific C3 states. Count at the same frequency as the TSC. 3FDH 1021 MSR_CORE_C6_RESIDENCY Core 63:0 Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. CORE C6 Residency Counter (R/O) Value since last reset that this core is in processorspecific C6 states. Count at the same frequency as the TSC. 400H 1024 IA32_MC0_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 401H 1025 IA32_MC0_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 402H 1026 IA32_MC0_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” The IA32_MC0_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC0_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 403H 1027 IA32_MC0_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 404H 1028 IA32_MC1_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 405H 1029 IA32_MC1_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 406H 1030 IA32_MC1_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” The IA32_MC1_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC1_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 407H 1031 IA32_MC1_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 408H 1032 IA32_MC2_CTL Core See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 409H 1033 IA32_MC2_STATUS Core See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 40AH 1034 IA32_MC2_ADDR Core See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” The IA32_MC2_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC2_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 40BH 1035 IA32_MC2_MISC Core See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 40CH 1036 IA32_MC3_CTL Core See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 2-132 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.) Register Address Register Name / Bit Fields Scope Bit Description Hex Dec 40DH 1037 IA32_MC3_STATUS Core See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 40EH 1038 IA32_MC3_ADDR Core See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” The MSR_MC4_ADDR register is either not implemented or contains no address if the ADDRV flag in the MSR_MC4_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 40FH 1039 IA32_MC3_MISC Core See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 410H 1040 IA32_MC4_CTL Core See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 411H 1041 IA32_MC4_STATUS Core See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 412H 1042 IA32_MC4_ADDR Core See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” The MSR_MC3_ADDR register is either not implemented or contains no address if the ADDRV flag in the MSR_MC3_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 413H 1043 IA32_MC4_MISC Core See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 414H 1044 IA32_MC5_CTL Core See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 415H 1045 IA32_MC5_STATUS Core See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 416H 1046 IA32_MC5_ADDR Core See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 417H 1047 IA32_MC5_MISC Core See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 418H 1048 IA32_MC6_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 419H 1049 IA32_MC6_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. 41AH 1050 IA32_MC6_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 41BH 1051 IA32_MC6_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 41CH 1052 IA32_MC7_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 41DH 1053 IA32_MC7_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. 41EH 1054 IA32_MC7_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 41FH 1055 IA32_MC7_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 420H 1056 IA32_MC8_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 421H 1057 IA32_MC8_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. 422H 1058 IA32_MC8_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 423H 1059 IA32_MC8_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” Vol. 4 2-133 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.) Register Address Hex Dec 480H 1152 Register Name / Bit Fields IA32_VMX_BASIC Scope Thread Bit Description Reporting Register of Basic VMX Capabilities (R/O) See Table 2-2. See Appendix A.1, “Basic VMX Information.” 481H 1153 IA32_VMX_PINBASED_CTLS Thread Capability Reporting Register of Pin-based VM-execution Controls (R/O) See Table 2-2. See Appendix A.3, “VM-Execution Controls.” 482H 1154 IA32_VMX_PROCBASED_CTLS Thread Capability Reporting Register of Primary ProcessorBased VM-Execution Controls (R/O) See Appendix A.3, “VM-Execution Controls.” 483H 1155 IA32_VMX_EXIT_CTLS Thread Capability Reporting Register of VM-Exit Controls (R/O) See Table 2-2. See Appendix A.4, “VM-Exit Controls.” 484H 1156 IA32_VMX_ENTRY_CTLS Thread Capability Reporting Register of VM-Entry Controls (R/O) See Table 2-2. See Appendix A.5, “VM-Entry Controls.” 485H 1157 IA32_VMX_MISC Thread Reporting Register of Miscellaneous VMX Capabilities (R/O) See Table 2-2. See Appendix A.6, “Miscellaneous Data.” 486H 1158 IA32_VMX_CR0_FIXED0 Thread Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Table 2-2. See Appendix A.7, “VMX-Fixed Bits in CR0.” 487H 1159 IA32_VMX_CR0_FIXED1 Thread Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Table 2-2. See Appendix A.7, “VMX-Fixed Bits in CR0.” 488H 1160 IA32_VMX_CR4_FIXED0 Thread Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Table 2-2. See Appendix A.8, “VMX-Fixed Bits in CR4.” 489H 1161 IA32_VMX_CR4_FIXED1 Thread Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) See Table 2-2. See Appendix A.8, “VMX-Fixed Bits in CR4.” 48AH 1162 IA32_VMX_VMCS_ENUM Thread Capability Reporting Register of VMCS Field Enumeration (R/O) See Table 2-2. See Appendix A.9, “VMCS Enumeration.” 2-134 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.) Register Address Hex Dec 48BH 1163 Register Name / Bit Fields IA32_VMX_PROCBASED_CTLS2 Scope Thread Bit Description Capability Reporting Register of Secondary ProcessorBased VM-Execution Controls (R/O) See Appendix A.3, “VM-Execution Controls.” 600H 1536 IA32_DS_AREA Thread DS Save Area (R/W) See Table 2-2. See Section 18.6.3.4, “Debug Store (DS) Mechanism.” 680H 1664 MSR_LASTBRANCH_0_FROM_IP Thread Last Branch Record 0 From IP (R/W) One of sixteen pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction. See also: • Last Branch Record Stack TOS at 1C9H. • Section 17.9.1 and record format in Section 17.4.8.1. 681H 1665 MSR_LASTBRANCH_1_FROM_IP Thread Last Branch Record 1 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 682H 1666 MSR_LASTBRANCH_2_FROM_IP Thread Last Branch Record 2 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 683H 1667 MSR_LASTBRANCH_3_FROM_IP Thread Last Branch Record 3 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 684H 1668 MSR_LASTBRANCH_4_FROM_IP Thread Last Branch Record 4 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 685H 1669 MSR_LASTBRANCH_5_FROM_IP Thread Last Branch Record 5 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 686H 1670 MSR_LASTBRANCH_6_FROM_IP Thread Last Branch Record 6 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 687H 1671 MSR_LASTBRANCH_7_FROM_IP Thread Last Branch Record 7 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 688H 1672 MSR_LASTBRANCH_8_FROM_IP Thread Last Branch Record 8 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 689H 1673 MSR_LASTBRANCH_9_FROM_IP Thread Last Branch Record 9 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 68AH 1674 MSR_LASTBRANCH_10_FROM_IP Thread Last Branch Record 10 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 68BH 1675 MSR_LASTBRANCH_11_FROM_IP Thread Last Branch Record 11 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 68CH 1676 MSR_LASTBRANCH_12_FROM_IP Thread Last Branch Record 12 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 68DH 1677 MSR_LASTBRANCH_13_FROM_IP Thread Last Branch Record 13 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. Vol. 4 2-135 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.) Register Address Hex Dec 68EH 1678 Register Name / Bit Fields MSR_LASTBRANCH_14_FROM_IP Scope Thread Bit Description Last Branch Record 14 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 68FH 1679 MSR_LASTBRANCH_15_FROM_IP Thread Last Branch Record 15 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 6C0H 1728 MSR_LASTBRANCH_0_TO_IP Thread Last Branch Record 0 To IP (R/W) One of sixteen pairs of last branch record registers on the last branch record stack. This part of the stack contains pointers to the destination instruction. 6C1H 1729 MSR_LASTBRANCH_1_TO_IP Thread Last Branch Record 1 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6C2H 1730 MSR_LASTBRANCH_2_TO_IP Thread Last Branch Record 2 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6C3H 1731 MSR_LASTBRANCH_3_TO_IP Thread Last Branch Record 3 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6C4H 1732 MSR_LASTBRANCH_4_TO_IP Thread Last Branch Record 4 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6C5H 1733 MSR_LASTBRANCH_5_TO_IP Thread Last Branch Record 5 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6C6H 1734 MSR_LASTBRANCH_6_TO_IP Thread Last Branch Record 6 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6C7H 1735 MSR_LASTBRANCH_7_TO_IP Thread Last Branch Record 7 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6C8H 1736 MSR_LASTBRANCH_8_TO_IP Thread Last Branch Record 8 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6C9H 1737 MSR_LASTBRANCH_9_TO_IP Thread Last Branch Record 9 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6CAH 1738 MSR_LASTBRANCH_10_TO_IP Thread Last Branch Record 10 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6CBH 1739 MSR_LASTBRANCH_11_TO_IP Thread Last Branch Record 11 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6CCH 1740 MSR_LASTBRANCH_12_TO_IP Thread Last Branch Record 12 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6CDH 1741 MSR_LASTBRANCH_13_TO_IP Thread Last Branch Record 13 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6CEH 1742 MSR_LASTBRANCH_14_TO_IP Thread Last Branch Record 14 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6CFH 1743 MSR_LASTBRANCH_15_TO_IP Thread Last Branch Record 15 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 802H 2-136 Vol. 4 2050 IA32_X2APIC_APICID Thread x2APIC ID Register (R/O) MODEL-SPECIFIC REGISTERS (MSRS) Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.) Register Address Register Name / Bit Fields Scope Bit Description Hex Dec 803H 2051 IA32_X2APIC_VERSION Thread x2APIC Version Register (R/O) 808H 2056 IA32_X2APIC_TPR Thread x2APIC Task Priority Register (R/W) 80AH 2058 IA32_X2APIC_PPR Thread x2APIC Processor Priority Register (R/O) 80BH 2059 IA32_X2APIC_EOI Thread x2APIC EOI Register (W/O) 80DH 2061 IA32_X2APIC_LDR Thread x2APIC Logical Destination Register (R/O) 80FH 2063 IA32_X2APIC_SIVR Thread x2APIC Spurious Interrupt Vector Register (R/W) 810H 2064 IA32_X2APIC_ISR0 Thread x2APIC In-Service Register Bits [31:0] (R/O) 811H 2065 IA32_X2APIC_ISR1 Thread x2APIC In-Service Register Bits [63:32] (R/O) 812H 2066 IA32_X2APIC_ISR2 Thread x2APIC In-Service Register Bits [95:64] (R/O) 813H 2067 IA32_X2APIC_ISR3 Thread x2APIC In-Service Register Bits [127:96] (R/O) 814H 2068 IA32_X2APIC_ISR4 Thread x2APIC In-Service Register Bits [159:128] (R/O) 815H 2069 IA32_X2APIC_ISR5 Thread x2APIC In-Service Register Bits [191:160] (R/O) 816H 2070 IA32_X2APIC_ISR6 Thread x2APIC In-Service Register Bits [223:192] (R/O) 817H 2071 IA32_X2APIC_ISR7 Thread x2APIC In-Service Register Bits [255:224] (R/O) 818H 2072 IA32_X2APIC_TMR0 Thread x2APIC Trigger Mode Register Bits [31:0] (R/O) 819H 2073 IA32_X2APIC_TMR1 Thread x2APIC Trigger Mode Register Bits [63:32] (R/O) 81AH 2074 IA32_X2APIC_TMR2 Thread x2APIC Trigger Mode Register Bits [95:64] (R/O) 81BH 2075 IA32_X2APIC_TMR3 Thread x2APIC Trigger Mode Register Bits [127:96] (R/O) 81CH 2076 IA32_X2APIC_TMR4 Thread x2APIC Trigger Mode Register Bits [159:128] (R/O) 81DH 2077 IA32_X2APIC_TMR5 Thread x2APIC Trigger Mode Register Bits [191:160] (R/O) 81EH 2078 IA32_X2APIC_TMR6 Thread x2APIC Trigger Mode Register Bits [223:192] (R/O) 81FH 2079 IA32_X2APIC_TMR7 Thread x2APIC Trigger Mode Register Bits [255:224] (R/O) 820H 2080 IA32_X2APIC_IRR0 Thread x2APIC Interrupt Request Register Bits [31:0] (R/O) 821H 2081 IA32_X2APIC_IRR1 Thread x2APIC Interrupt Request Register Bits [63:32] (R/O) 822H 2082 IA32_X2APIC_IRR2 Thread x2APIC Interrupt Request Register Bits [95:64] (R/O) 823H 2083 IA32_X2APIC_IRR3 Thread x2APIC Interrupt Request Register Bits [127:96] (R/O) 824H 2084 IA32_X2APIC_IRR4 Thread x2APIC Interrupt Request Register Bits [159:128] (R/O) 825H 2085 IA32_X2APIC_IRR5 Thread x2APIC Interrupt Request Register Bits [191:160] (R/O) 826H 2086 IA32_X2APIC_IRR6 Thread x2APIC Interrupt Request Register Bits [223:192] (R/O) 827H 2087 IA32_X2APIC_IRR7 Thread x2APIC Interrupt Request Register Bits [255:224] (R/O) 828H 2088 IA32_X2APIC_ESR Thread x2APIC Error Status Register (R/W) 82FH 2095 IA32_X2APIC_LVT_CMCI Thread x2APIC LVT Corrected Machine Check Interrupt Register (R/W) 830H 2096 IA32_X2APIC_ICR Thread x2APIC Interrupt Command Register (R/W) 832H 2098 IA32_X2APIC_LVT_TIMER Thread x2APIC LVT Timer Interrupt Register (R/W) 833H 2099 IA32_X2APIC_LVT_THERMAL Thread x2APIC LVT Thermal Sensor Interrupt Register (R/W) Vol. 4 2-137 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-15. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.) Register Address Register Name / Bit Fields Scope Bit Description Hex Dec 834H 2100 IA32_X2APIC_LVT_PMI Thread x2APIC LVT Performance Monitor Register (R/W) 835H 2101 IA32_X2APIC_LVT_LINT0 Thread x2APIC LVT LINT0 Register (R/W) 836H 2102 IA32_X2APIC_LVT_LINT1 Thread x2APIC LVT LINT1 Register (R/W) 837H 2103 IA32_X2APIC_LVT_ERROR Thread x2APIC LVT Error Register (R/W) 838H 2104 IA32_X2APIC_INIT_COUNT Thread x2APIC Initial Count Register (R/W) 839H 2105 IA32_X2APIC_CUR_COUNT Thread x2APIC Current Count Register (R/O) 83EH 2110 IA32_X2APIC_DIV_CONF Thread x2APIC Divide Configuration Register (R/W) 83FH 2111 IA32_X2APIC_SELF_IPI Thread x2APIC Self IPI Register (W/O) C000_ 0080H IA32_EFER Thread Extended Feature Enables C000_ 0081H IA32_STAR C000_ 0082H IA32_LSTAR C000_ 0084H IA32_FMASK C000_ 0100H IA32_FS_BASE C000_ 0101H IA32_GS_BASE C000_ 0102H IA32_KERNEL_GS_BASE C000_ 0103H IA32_TSC_AUX 2.8.1 See Table 2-2. Thread System Call Target Address (R/W) See Table 2-2. Thread IA-32e Mode System Call Target Address (R/W) See Table 2-2. Thread System Call Flag Mask (R/W) See Table 2-2. Thread Map of BASE Address of FS (R/W) See Table 2-2. Thread Map of BASE Address of GS (R/W) See Table 2-2. Thread Swap Target of BASE Address of GS (R/W) See Table 2-2. Thread AUXILIARY TSC Signature (R/W) See Table 2-2 and Section 17.17.2, “IA32_TSC_AUX Register and RDTSCP Support.” Additional MSRs in the Intel® Xeon® Processor 5500 and 3400 Series Intel Xeon Processor 5500 and 3400 series support additional model-specific registers listed in Table 2-16. These MSRs also apply to Intel Core i7 and i5 processor family CPUID signature with DisplayFamily_DisplayModel of 06_1AH, 06_1EH and 06_1FH, see Table 2-1. Table 2-16. Additional MSRs in Intel® Xeon® Processor 5500 and 3400 Series Register Address Hex Dec 1ADH 429 Register Name / Bit Fields MSR_TURBO_RATIO_LIMIT Scope Package Bit Description Actual maximum turbo frequency is multiplied by 133.33MHz. (Not available in model 06_2EH.) 2-138 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-16. Additional MSRs in Intel® Xeon® Processor 5500 and 3400 Series (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 7:0 Maximum Turbo Ratio Limit 1C (R/O) Maximum Turbo mode ratio limit with 1 core active. 15:8 Maximum Turbo Ratio Limit 2C (R/O) Maximum Turbo mode ratio limit with 2 cores active. 23:16 Maximum Turbo Ratio Limit 3C (R/O) Maximum Turbo mode ratio limit with 3 cores active. 31:24 Maximum Turbo Ratio Limit 4C (R/O) Maximum Turbo mode ratio limit with 4 cores active. 63:32 301H 769 MSR_GQ_SNOOP_MESF Reserved Package 0 From M to S (R/W) 1 From E to S (R/W) 2 From S to S (R/W) 3 From F to S (R/W) 4 From M to I (R/W) 5 From E to I (R/W) 6 From S to I (R/W) 7 From F to I (R/W) 63:8 Reserved 391H 913 MSR_UNCORE_PERF_GLOBAL_CTRL Package See Section 18.3.1.2.1, “Uncore Performance Monitoring Management Facility.” 392H 914 MSR_UNCORE_PERF_GLOBAL_STATUS Package See Section 18.3.1.2.1, “Uncore Performance Monitoring Management Facility.” 393H 915 MSR_UNCORE_PERF_GLOBAL_OVF_CTRL Package See Section 18.3.1.2.1, “Uncore Performance Monitoring Management Facility.” 394H 916 MSR_UNCORE_FIXED_CTR0 Package See Section 18.3.1.2.1, “Uncore Performance Monitoring Management Facility.” 395H 917 MSR_UNCORE_FIXED_CTR_CTRL Package See Section 18.3.1.2.1, “Uncore Performance Monitoring Management Facility.” 396H 918 MSR_UNCORE_ADDR_OPCODE_MATCH Package See Section 18.3.1.2.3, “Uncore Address/Opcode Match MSR.” 3B0H 960 MSR_UNCORE_PMC0 Package See Section 18.3.1.2.2, “Uncore Performance Event Configuration Facility.” 3B1H 961 MSR_UNCORE_PMC1 Package See Section 18.3.1.2.2, “Uncore Performance Event Configuration Facility.” 3B2H 962 MSR_UNCORE_PMC2 Package See Section 18.3.1.2.2, “Uncore Performance Event Configuration Facility.” 3B3H 963 MSR_UNCORE_PMC3 Package See Section 18.3.1.2.2, “Uncore Performance Event Configuration Facility.” 3B4H 964 MSR_UNCORE_PMC4 Package See Section 18.3.1.2.2, “Uncore Performance Event Configuration Facility.” Vol. 4 2-139 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-16. Additional MSRs in Intel® Xeon® Processor 5500 and 3400 Series (Contd.) Register Address Register Name / Bit Fields Scope Bit Description Hex Dec 3B5H 965 MSR_UNCORE_PMC5 Package See Section 18.3.1.2.2, “Uncore Performance Event Configuration Facility.” 3B6H 966 MSR_UNCORE_PMC6 Package See Section 18.3.1.2.2, “Uncore Performance Event Configuration Facility.” 3B7H 967 MSR_UNCORE_PMC7 Package See Section 18.3.1.2.2, “Uncore Performance Event Configuration Facility.” 3C0H 944 MSR_UNCORE_PERFEVTSEL0 Package See Section 18.3.1.2.2, “Uncore Performance Event Configuration Facility.” 3C1H 945 MSR_UNCORE_PERFEVTSEL1 Package See Section 18.3.1.2.2, “Uncore Performance Event Configuration Facility.” 3C2H 946 MSR_UNCORE_PERFEVTSEL2 Package See Section 18.3.1.2.2, “Uncore Performance Event Configuration Facility.” 3C3H 947 MSR_UNCORE_PERFEVTSEL3 Package See Section 18.3.1.2.2, “Uncore Performance Event Configuration Facility.” 3C4H 948 MSR_UNCORE_PERFEVTSEL4 Package See Section 18.3.1.2.2, “Uncore Performance Event Configuration Facility.” 3C5H 949 MSR_UNCORE_PERFEVTSEL5 Package See Section 18.3.1.2.2, “Uncore Performance Event Configuration Facility.” 3C6H 950 MSR_UNCORE_PERFEVTSEL6 Package See Section 18.3.1.2.2, “Uncore Performance Event Configuration Facility.” 3C7H 951 MSR_UNCORE_PERFEVTSEL7 Package See Section 18.3.1.2.2, “Uncore Performance Event Configuration Facility.” 2.8.2 Additional MSRs in the Intel® Xeon® Processor 7500 Series Intel Xeon Processor 7500 series support MSRs listed in Table 2-15 (except MSR address 1ADH) and additional model-specific registers listed in Table 2-17. These processors have a CPUID signature with DisplayFamily_DisplayModel of 06_2EH. Table 2-17. Additional MSRs in Intel® Xeon® Processor 7500 Series Register Address Hex Dec 1ADH 429 Register Name / Bit Fields MSR_TURBO_RATIO_LIMIT Scope Package Bit Description Reserved Attempt to read/write will cause #UD. 289H 649 IA32_MC9_CTL2 Package See Table 2-2. 28AH 650 IA32_MC10_CTL2 Package See Table 2-2. 28BH 651 IA32_MC11_CTL2 Package See Table 2-2. 28CH 652 IA32_MC12_CTL2 Package See Table 2-2. 28DH 653 IA32_MC13_CTL2 Package See Table 2-2. 28EH 654 IA32_MC14_CTL2 Package See Table 2-2. 28FH 655 IA32_MC15_CTL2 Package See Table 2-2. 2-140 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-17. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.) Register Address Register Name / Bit Fields Scope Bit Description Hex Dec 290H 656 IA32_MC16_CTL2 Package See Table 2-2. 291H 657 IA32_MC17_CTL2 Package See Table 2-2. 292H 658 IA32_MC18_CTL2 Package See Table 2-2. 293H 659 IA32_MC19_CTL2 Package See Table 2-2. 294H 660 IA32_MC20_CTL2 Package See Table 2-2. 295H 661 IA32_MC21_CTL2 Package See Table 2-2. 394H 816 MSR_W_PMON_FIXED_CTR Package Uncore W-box perfmon fixed counter. 395H 817 MSR_W_PMON_FIXED_CTR_CTL Package Uncore U-box perfmon fixed counter control MSR. 424H 1060 IA32_MC9_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 425H 1061 IA32_MC9_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. 426H 1062 IA32_MC9_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 427H 1063 IA32_MC9_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 428H 1064 IA32_MC10_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 429H 1065 IA32_MC10_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. 42AH 1066 IA32_MC10_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 42BH 1067 IA32_MC10_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 42CH 1068 IA32_MC11_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 42DH 1069 IA32_MC11_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. 42EH 1070 IA32_MC11_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 42FH 1071 IA32_MC11_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 430H 1072 IA32_MC12_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 431H 1073 IA32_MC12_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. 432H 1074 IA32_MC12_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 433H 1075 IA32_MC12_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 434H 1076 IA32_MC13_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 435H 1077 IA32_MC13_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. 436H 1078 IA32_MC13_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 437H 1079 IA32_MC13_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 438H 1080 IA32_MC14_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 439H 1081 IA32_MC14_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. 43AH 1082 IA32_MC14_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 43BH 1083 IA32_MC14_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 43CH 1084 IA32_MC15_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” Vol. 4 2-141 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-17. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.) Register Address Register Name / Bit Fields Scope Bit Description Hex Dec 43DH 1085 IA32_MC15_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. 43EH 1086 IA32_MC15_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 43FH 1087 IA32_MC15_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 440H 1088 IA32_MC16_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 441H 1089 IA32_MC16_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. 442H 1090 IA32_MC16_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 443H 1091 IA32_MC16_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 444H 1092 IA32_MC17_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 445H 1093 IA32_MC17_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. 446H 1094 IA32_MC17_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 447H 1095 IA32_MC17_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 448H 1096 IA32_MC18_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 449H 1097 IA32_MC18_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. 44AH 1098 IA32_MC18_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 44BH 1099 IA32_MC18_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 44CH 1100 IA32_MC19_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 44DH 1101 IA32_MC19_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. 44EH 1102 IA32_MC19_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 44FH 1103 IA32_MC19_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 450H 1104 IA32_MC20_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 451H 1105 IA32_MC20_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. 452H 1106 IA32_MC20_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 453H 1107 IA32_MC20_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 454H 1108 IA32_MC21_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 455H 1109 IA32_MC21_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. 456H 1110 IA32_MC21_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 457H 1111 IA32_MC21_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” C00H 3072 MSR_U_PMON_GLOBAL_CTRL Package Uncore U-box perfmon global control MSR. C01H 3073 MSR_U_PMON_GLOBAL_STATUS Package Uncore U-box perfmon global status MSR. C02H 3074 MSR_U_PMON_GLOBAL_OVF_CTRL Package Uncore U-box perfmon global overflow control MSR. 2-142 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-17. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.) Register Address Register Name / Bit Fields Scope Bit Description Hex Dec C10H 3088 MSR_U_PMON_EVNT_SEL Package Uncore U-box perfmon event select MSR. C11H 3089 MSR_U_PMON_CTR Package Uncore U-box perfmon counter MSR. C20H 3104 MSR_B0_PMON_BOX_CTRL Package Uncore B-box 0 perfmon local box control MSR. C21H 3105 MSR_B0_PMON_BOX_STATUS Package Uncore B-box 0 perfmon local box status MSR. C22H 3106 MSR_B0_PMON_BOX_OVF_CTRL Package Uncore B-box 0 perfmon local box overflow control MSR. C30H 3120 MSR_B0_PMON_EVNT_SEL0 Package Uncore B-box 0 perfmon event select MSR. C31H 3121 MSR_B0_PMON_CTR0 Package Uncore B-box 0 perfmon counter MSR. C32H 3122 MSR_B0_PMON_EVNT_SEL1 Package Uncore B-box 0 perfmon event select MSR. C33H 3123 MSR_B0_PMON_CTR1 Package Uncore B-box 0 perfmon counter MSR. C34H 3124 MSR_B0_PMON_EVNT_SEL2 Package Uncore B-box 0 perfmon event select MSR. C35H 3125 MSR_B0_PMON_CTR2 Package Uncore B-box 0 perfmon counter MSR. C36H 3126 MSR_B0_PMON_EVNT_SEL3 Package Uncore B-box 0 perfmon event select MSR. C37H 3127 MSR_B0_PMON_CTR3 Package Uncore B-box 0 perfmon counter MSR. C40H 3136 MSR_S0_PMON_BOX_CTRL Package Uncore S-box 0 perfmon local box control MSR. C41H 3137 MSR_S0_PMON_BOX_STATUS Package Uncore S-box 0 perfmon local box status MSR. C42H 3138 MSR_S0_PMON_BOX_OVF_CTRL Package Uncore S-box 0 perfmon local box overflow control MSR. C50H 3152 MSR_S0_PMON_EVNT_SEL0 Package Uncore S-box 0 perfmon event select MSR. C51H 3153 MSR_S0_PMON_CTR0 Package Uncore S-box 0 perfmon counter MSR. C52H 3154 MSR_S0_PMON_EVNT_SEL1 Package Uncore S-box 0 perfmon event select MSR. C53H 3155 MSR_S0_PMON_CTR1 Package Uncore S-box 0 perfmon counter MSR. C54H 3156 MSR_S0_PMON_EVNT_SEL2 Package Uncore S-box 0 perfmon event select MSR. C55H 3157 MSR_S0_PMON_CTR2 Package Uncore S-box 0 perfmon counter MSR. C56H 3158 MSR_S0_PMON_EVNT_SEL3 Package Uncore S-box 0 perfmon event select MSR. C57H 3159 MSR_S0_PMON_CTR3 Package Uncore S-box 0 perfmon counter MSR. C60H 3168 MSR_B1_PMON_BOX_CTRL Package Uncore B-box 1 perfmon local box control MSR. Vol. 4 2-143 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-17. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.) Register Address Register Name / Bit Fields Scope Bit Description Hex Dec C61H 3169 MSR_B1_PMON_BOX_STATUS Package Uncore B-box 1 perfmon local box status MSR. C62H 3170 MSR_B1_PMON_BOX_OVF_CTRL Package Uncore B-box 1 perfmon local box overflow control MSR. C70H 3184 MSR_B1_PMON_EVNT_SEL0 Package Uncore B-box 1 perfmon event select MSR. C71H 3185 MSR_B1_PMON_CTR0 Package Uncore B-box 1 perfmon counter MSR. C72H 3186 MSR_B1_PMON_EVNT_SEL1 Package Uncore B-box 1 perfmon event select MSR. C73H 3187 MSR_B1_PMON_CTR1 Package Uncore B-box 1 perfmon counter MSR. C74H 3188 MSR_B1_PMON_EVNT_SEL2 Package Uncore B-box 1 perfmon event select MSR. C75H 3189 MSR_B1_PMON_CTR2 Package Uncore B-box 1 perfmon counter MSR. C76H 3190 MSR_B1_PMON_EVNT_SEL3 Package Uncore B-box 1vperfmon event select MSR. C77H 3191 MSR_B1_PMON_CTR3 Package Uncore B-box 1 perfmon counter MSR. C80H 3120 MSR_W_PMON_BOX_CTRL Package Uncore W-box perfmon local box control MSR. C81H 3121 MSR_W_PMON_BOX_STATUS Package Uncore W-box perfmon local box status MSR. C82H 3122 MSR_W_PMON_BOX_OVF_CTRL Package Uncore W-box perfmon local box overflow control MSR. C90H 3136 MSR_W_PMON_EVNT_SEL0 Package Uncore W-box perfmon event select MSR. C91H 3137 MSR_W_PMON_CTR0 Package Uncore W-box perfmon counter MSR. C92H 3138 MSR_W_PMON_EVNT_SEL1 Package Uncore W-box perfmon event select MSR. C93H 3139 MSR_W_PMON_CTR1 Package Uncore W-box perfmon counter MSR. C94H 3140 MSR_W_PMON_EVNT_SEL2 Package Uncore W-box perfmon event select MSR. C95H 3141 MSR_W_PMON_CTR2 Package Uncore W-box perfmon counter MSR. C96H 3142 MSR_W_PMON_EVNT_SEL3 Package Uncore W-box perfmon event select MSR. C97H 3143 MSR_W_PMON_CTR3 Package Uncore W-box perfmon counter MSR. CA0H 3232 MSR_M0_PMON_BOX_CTRL Package Uncore M-box 0 perfmon local box control MSR. CA1H 3233 MSR_M0_PMON_BOX_STATUS Package Uncore M-box 0 perfmon local box status MSR. CA2H 3234 MSR_M0_PMON_BOX_OVF_CTRL Package Uncore M-box 0 perfmon local box overflow control MSR. CA4H 3236 MSR_M0_PMON_TIMESTAMP Package Uncore M-box 0 perfmon time stamp unit select MSR. CA5H 3237 MSR_M0_PMON_DSP Package Uncore M-box 0 perfmon DSP unit select MSR. 2-144 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-17. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.) Register Address Register Name / Bit Fields Scope Bit Description Hex Dec CA6H 3238 MSR_M0_PMON_ISS Package Uncore M-box 0 perfmon ISS unit select MSR. CA7H 3239 MSR_M0_PMON_MAP Package Uncore M-box 0 perfmon MAP unit select MSR. CA8H 3240 MSR_M0_PMON_MSC_THR Package Uncore M-box 0 perfmon MIC THR select MSR. CA9H 3241 MSR_M0_PMON_PGT Package Uncore M-box 0 perfmon PGT unit select MSR. CAAH 3242 MSR_M0_PMON_PLD Package Uncore M-box 0 perfmon PLD unit select MSR. CABH 3243 MSR_M0_PMON_ZDP Package Uncore M-box 0 perfmon ZDP unit select MSR. CB0H 3248 MSR_M0_PMON_EVNT_SEL0 Package Uncore M-box 0 perfmon event select MSR. CB1H 3249 MSR_M0_PMON_CTR0 Package Uncore M-box 0 perfmon counter MSR. CB2H 3250 MSR_M0_PMON_EVNT_SEL1 Package Uncore M-box 0 perfmon event select MSR. CB3H 3251 MSR_M0_PMON_CTR1 Package Uncore M-box 0 perfmon counter MSR. CB4H 3252 MSR_M0_PMON_EVNT_SEL2 Package Uncore M-box 0 perfmon event select MSR. CB5H 3253 MSR_M0_PMON_CTR2 Package Uncore M-box 0 perfmon counter MSR. CB6H 3254 MSR_M0_PMON_EVNT_SEL3 Package Uncore M-box 0 perfmon event select MSR. CB7H 3255 MSR_M0_PMON_CTR3 Package Uncore M-box 0 perfmon counter MSR. CB8H 3256 MSR_M0_PMON_EVNT_SEL4 Package Uncore M-box 0 perfmon event select MSR. CB9H 3257 MSR_M0_PMON_CTR4 Package Uncore M-box 0 perfmon counter MSR. CBAH 3258 MSR_M0_PMON_EVNT_SEL5 Package Uncore M-box 0 perfmon event select MSR. CBBH 3259 MSR_M0_PMON_CTR5 Package Uncore M-box 0 perfmon counter MSR. CC0H 3264 MSR_S1_PMON_BOX_CTRL Package Uncore S-box 1 perfmon local box control MSR. CC1H 3265 MSR_S1_PMON_BOX_STATUS Package Uncore S-box 1 perfmon local box status MSR. CC2H 3266 MSR_S1_PMON_BOX_OVF_CTRL Package Uncore S-box 1 perfmon local box overflow control MSR. CD0H 3280 MSR_S1_PMON_EVNT_SEL0 Package Uncore S-box 1 perfmon event select MSR. CD1H 3281 MSR_S1_PMON_CTR0 Package Uncore S-box 1 perfmon counter MSR. CD2H 3282 MSR_S1_PMON_EVNT_SEL1 Package Uncore S-box 1 perfmon event select MSR. CD3H 3283 MSR_S1_PMON_CTR1 Package Uncore S-box 1 perfmon counter MSR. CD4H 3284 MSR_S1_PMON_EVNT_SEL2 Package Uncore S-box 1 perfmon event select MSR. CD5H 3285 MSR_S1_PMON_CTR2 Package Uncore S-box 1 perfmon counter MSR. Vol. 4 2-145 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-17. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.) Register Address Register Name / Bit Fields Scope Bit Description Hex Dec CD6H 3286 MSR_S1_PMON_EVNT_SEL3 Package Uncore S-box 1 perfmon event select MSR. CD7H 3287 MSR_S1_PMON_CTR3 Package Uncore S-box 1 perfmon counter MSR. CE0H 3296 MSR_M1_PMON_BOX_CTRL Package Uncore M-box 1 perfmon local box control MSR. CE1H 3297 MSR_M1_PMON_BOX_STATUS Package Uncore M-box 1 perfmon local box status MSR. CE2H 3298 MSR_M1_PMON_BOX_OVF_CTRL Package Uncore M-box 1 perfmon local box overflow control MSR. CE4H 3300 MSR_M1_PMON_TIMESTAMP Package Uncore M-box 1 perfmon time stamp unit select MSR. CE5H 3301 MSR_M1_PMON_DSP Package Uncore M-box 1 perfmon DSP unit select MSR. CE6H 3302 MSR_M1_PMON_ISS Package Uncore M-box 1 perfmon ISS unit select MSR. CE7H 3303 MSR_M1_PMON_MAP Package Uncore M-box 1 perfmon MAP unit select MSR. CE8H 3304 MSR_M1_PMON_MSC_THR Package Uncore M-box 1 perfmon MIC THR select MSR. CE9H 3305 MSR_M1_PMON_PGT Package Uncore M-box 1 perfmon PGT unit select MSR. CEAH 3306 MSR_M1_PMON_PLD Package Uncore M-box 1 perfmon PLD unit select MSR. CEBH 3307 MSR_M1_PMON_ZDP Package Uncore M-box 1 perfmon ZDP unit select MSR. CF0H 3312 MSR_M1_PMON_EVNT_SEL0 Package Uncore M-box 1 perfmon event select MSR. CF1H 3313 MSR_M1_PMON_CTR0 Package Uncore M-box 1 perfmon counter MSR. CF2H 3314 MSR_M1_PMON_EVNT_SEL1 Package Uncore M-box 1 perfmon event select MSR. CF3H 3315 MSR_M1_PMON_CTR1 Package Uncore M-box 1 perfmon counter MSR. CF4H 3316 MSR_M1_PMON_EVNT_SEL2 Package Uncore M-box 1 perfmon event select MSR. CF5H 3317 MSR_M1_PMON_CTR2 Package Uncore M-box 1 perfmon counter MSR. CF6H 3318 MSR_M1_PMON_EVNT_SEL3 Package Uncore M-box 1 perfmon event select MSR. CF7H 3319 MSR_M1_PMON_CTR3 Package Uncore M-box 1 perfmon counter MSR. CF8H 3320 MSR_M1_PMON_EVNT_SEL4 Package Uncore M-box 1 perfmon event select MSR. CF9H 3321 MSR_M1_PMON_CTR4 Package Uncore M-box 1 perfmon counter MSR. CFAH 3322 MSR_M1_PMON_EVNT_SEL5 Package Uncore M-box 1 perfmon event select MSR. CFBH 3323 MSR_M1_PMON_CTR5 Package Uncore M-box 1 perfmon counter MSR. D00H 3328 MSR_C0_PMON_BOX_CTRL Package Uncore C-box 0 perfmon local box control MSR. D01H 3329 MSR_C0_PMON_BOX_STATUS Package Uncore C-box 0 perfmon local box status MSR. 2-146 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-17. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.) Register Address Register Name / Bit Fields Scope Bit Description Hex Dec D02H 3330 MSR_C0_PMON_BOX_OVF_CTRL Package Uncore C-box 0 perfmon local box overflow control MSR. D10H 3344 MSR_C0_PMON_EVNT_SEL0 Package Uncore C-box 0 perfmon event select MSR. D11H 3345 MSR_C0_PMON_CTR0 Package Uncore C-box 0 perfmon counter MSR. D12H 3346 MSR_C0_PMON_EVNT_SEL1 Package Uncore C-box 0 perfmon event select MSR. D13H 3347 MSR_C0_PMON_CTR1 Package Uncore C-box 0 perfmon counter MSR. D14H 3348 MSR_C0_PMON_EVNT_SEL2 Package Uncore C-box 0 perfmon event select MSR. D15H 3349 MSR_C0_PMON_CTR2 Package Uncore C-box 0 perfmon counter MSR. D16H 3350 MSR_C0_PMON_EVNT_SEL3 Package Uncore C-box 0 perfmon event select MSR. D17H 3351 MSR_C0_PMON_CTR3 Package Uncore C-box 0 perfmon counter MSR. D18H 3352 MSR_C0_PMON_EVNT_SEL4 Package Uncore C-box 0 perfmon event select MSR. D19H 3353 MSR_C0_PMON_CTR4 Package Uncore C-box 0 perfmon counter MSR. D1AH 3354 MSR_C0_PMON_EVNT_SEL5 Package Uncore C-box 0 perfmon event select MSR. D1BH 3355 MSR_C0_PMON_CTR5 Package Uncore C-box 0 perfmon counter MSR. D20H 3360 MSR_C4_PMON_BOX_CTRL Package Uncore C-box 4 perfmon local box control MSR. D21H 3361 MSR_C4_PMON_BOX_STATUS Package Uncore C-box 4 perfmon local box status MSR. D22H 3362 MSR_C4_PMON_BOX_OVF_CTRL Package Uncore C-box 4 perfmon local box overflow control MSR. D30H 3376 MSR_C4_PMON_EVNT_SEL0 Package Uncore C-box 4 perfmon event select MSR. D31H 3377 MSR_C4_PMON_CTR0 Package Uncore C-box 4 perfmon counter MSR. D32H 3378 MSR_C4_PMON_EVNT_SEL1 Package Uncore C-box 4 perfmon event select MSR. D33H 3379 MSR_C4_PMON_CTR1 Package Uncore C-box 4 perfmon counter MSR. D34H 3380 MSR_C4_PMON_EVNT_SEL2 Package Uncore C-box 4 perfmon event select MSR. D35H 3381 MSR_C4_PMON_CTR2 Package Uncore C-box 4 perfmon counter MSR. D36H 3382 MSR_C4_PMON_EVNT_SEL3 Package Uncore C-box 4 perfmon event select MSR. D37H 3383 MSR_C4_PMON_CTR3 Package Uncore C-box 4 perfmon counter MSR. D38H 3384 MSR_C4_PMON_EVNT_SEL4 Package Uncore C-box 4 perfmon event select MSR. D39H 3385 MSR_C4_PMON_CTR4 Package Uncore C-box 4 perfmon counter MSR. Vol. 4 2-147 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-17. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.) Register Address Register Name / Bit Fields Scope Bit Description Hex Dec D3AH 3386 MSR_C4_PMON_EVNT_SEL5 Package Uncore C-box 4 perfmon event select MSR. D3BH 3387 MSR_C4_PMON_CTR5 Package Uncore C-box 4 perfmon counter MSR. D40H 3392 MSR_C2_PMON_BOX_CTRL Package Uncore C-box 2 perfmon local box control MSR. D41H 3393 MSR_C2_PMON_BOX_STATUS Package Uncore C-box 2 perfmon local box status MSR. D42H 3394 MSR_C2_PMON_BOX_OVF_CTRL Package Uncore C-box 2 perfmon local box overflow control MSR. D50H 3408 MSR_C2_PMON_EVNT_SEL0 Package Uncore C-box 2 perfmon event select MSR. D51H 3409 MSR_C2_PMON_CTR0 Package Uncore C-box 2 perfmon counter MSR. D52H 3410 MSR_C2_PMON_EVNT_SEL1 Package Uncore C-box 2 perfmon event select MSR. D53H 3411 MSR_C2_PMON_CTR1 Package Uncore C-box 2 perfmon counter MSR. D54H 3412 MSR_C2_PMON_EVNT_SEL2 Package Uncore C-box 2 perfmon event select MSR. D55H 3413 MSR_C2_PMON_CTR2 Package Uncore C-box 2 perfmon counter MSR. D56H 3414 MSR_C2_PMON_EVNT_SEL3 Package Uncore C-box 2 perfmon event select MSR. D57H 3415 MSR_C2_PMON_CTR3 Package Uncore C-box 2 perfmon counter MSR. D58H 3416 MSR_C2_PMON_EVNT_SEL4 Package Uncore C-box 2 perfmon event select MSR. D59H 3417 MSR_C2_PMON_CTR4 Package Uncore C-box 2 perfmon counter MSR. D5AH 3418 MSR_C2_PMON_EVNT_SEL5 Package Uncore C-box 2 perfmon event select MSR. D5BH 3419 MSR_C2_PMON_CTR5 Package Uncore C-box 2 perfmon counter MSR. D60H 3424 MSR_C6_PMON_BOX_CTRL Package Uncore C-box 6 perfmon local box control MSR. D61H 3425 MSR_C6_PMON_BOX_STATUS Package Uncore C-box 6 perfmon local box status MSR. D62H 3426 MSR_C6_PMON_BOX_OVF_CTRL Package Uncore C-box 6 perfmon local box overflow control MSR. D70H 3440 MSR_C6_PMON_EVNT_SEL0 Package Uncore C-box 6 perfmon event select MSR. D71H 3441 MSR_C6_PMON_CTR0 Package Uncore C-box 6 perfmon counter MSR. D72H 3442 MSR_C6_PMON_EVNT_SEL1 Package Uncore C-box 6 perfmon event select MSR. D73H 3443 MSR_C6_PMON_CTR1 Package Uncore C-box 6 perfmon counter MSR. D74H 3444 MSR_C6_PMON_EVNT_SEL2 Package Uncore C-box 6 perfmon event select MSR. 2-148 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-17. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.) Register Address Register Name / Bit Fields Scope Bit Description Hex Dec D75H 3445 MSR_C6_PMON_CTR2 Package Uncore C-box 6 perfmon counter MSR. D76H 3446 MSR_C6_PMON_EVNT_SEL3 Package Uncore C-box 6 perfmon event select MSR. D77H 3447 MSR_C6_PMON_CTR3 Package Uncore C-box 6 perfmon counter MSR. D78H 3448 MSR_C6_PMON_EVNT_SEL4 Package Uncore C-box 6 perfmon event select MSR. D79H 3449 MSR_C6_PMON_CTR4 Package Uncore C-box 6 perfmon counter MSR. D7AH 3450 MSR_C6_PMON_EVNT_SEL5 Package Uncore C-box 6 perfmon event select MSR. D7BH 3451 MSR_C6_PMON_CTR5 Package Uncore C-box 6 perfmon counter MSR. D80H 3456 MSR_C1_PMON_BOX_CTRL Package Uncore C-box 1 perfmon local box control MSR. D81H 3457 MSR_C1_PMON_BOX_STATUS Package Uncore C-box 1 perfmon local box status MSR. D82H 3458 MSR_C1_PMON_BOX_OVF_CTRL Package Uncore C-box 1 perfmon local box overflow control MSR. D90H 3472 MSR_C1_PMON_EVNT_SEL0 Package Uncore C-box 1 perfmon event select MSR. D91H 3473 MSR_C1_PMON_CTR0 Package Uncore C-box 1 perfmon counter MSR. D92H 3474 MSR_C1_PMON_EVNT_SEL1 Package Uncore C-box 1 perfmon event select MSR. D93H 3475 MSR_C1_PMON_CTR1 Package Uncore C-box 1 perfmon counter MSR. D94H 3476 MSR_C1_PMON_EVNT_SEL2 Package Uncore C-box 1 perfmon event select MSR. D95H 3477 MSR_C1_PMON_CTR2 Package Uncore C-box 1 perfmon counter MSR. D96H 3478 MSR_C1_PMON_EVNT_SEL3 Package Uncore C-box 1 perfmon event select MSR. D97H 3479 MSR_C1_PMON_CTR3 Package Uncore C-box 1 perfmon counter MSR. D98H 3480 MSR_C1_PMON_EVNT_SEL4 Package Uncore C-box 1 perfmon event select MSR. D99H 3481 MSR_C1_PMON_CTR4 Package Uncore C-box 1 perfmon counter MSR. D9AH 3482 MSR_C1_PMON_EVNT_SEL5 Package Uncore C-box 1 perfmon event select MSR. D9BH 3483 MSR_C1_PMON_CTR5 Package Uncore C-box 1 perfmon counter MSR. DA0H 3488 MSR_C5_PMON_BOX_CTRL Package Uncore C-box 5 perfmon local box control MSR. DA1H 3489 MSR_C5_PMON_BOX_STATUS Package Uncore C-box 5 perfmon local box status MSR. DA2H 3490 MSR_C5_PMON_BOX_OVF_CTRL Package Uncore C-box 5 perfmon local box overflow control MSR. DB0H 3504 MSR_C5_PMON_EVNT_SEL0 Package Uncore C-box 5 perfmon event select MSR. Vol. 4 2-149 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-17. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.) Register Address Register Name / Bit Fields Scope Bit Description Hex Dec DB1H 3505 MSR_C5_PMON_CTR0 Package Uncore C-box 5 perfmon counter MSR. DB2H 3506 MSR_C5_PMON_EVNT_SEL1 Package Uncore C-box 5 perfmon event select MSR. DB3H 3507 MSR_C5_PMON_CTR1 Package Uncore C-box 5 perfmon counter MSR. DB4H 3508 MSR_C5_PMON_EVNT_SEL2 Package Uncore C-box 5 perfmon event select MSR. DB5H 3509 MSR_C5_PMON_CTR2 Package Uncore C-box 5 perfmon counter MSR. DB6H 3510 MSR_C5_PMON_EVNT_SEL3 Package Uncore C-box 5 perfmon event select MSR. DB7H 3511 MSR_C5_PMON_CTR3 Package Uncore C-box 5 perfmon counter MSR. DB8H 3512 MSR_C5_PMON_EVNT_SEL4 Package Uncore C-box 5 perfmon event select MSR. DB9H 3513 MSR_C5_PMON_CTR4 Package Uncore C-box 5 perfmon counter MSR. DBAH 3514 MSR_C5_PMON_EVNT_SEL5 Package Uncore C-box 5 perfmon event select MSR. DBBH 3515 MSR_C5_PMON_CTR5 Package Uncore C-box 5 perfmon counter MSR. DC0H 3520 MSR_C3_PMON_BOX_CTRL Package Uncore C-box 3 perfmon local box control MSR. DC1H 3521 MSR_C3_PMON_BOX_STATUS Package Uncore C-box 3 perfmon local box status MSR. DC2H 3522 MSR_C3_PMON_BOX_OVF_CTRL Package Uncore C-box 3 perfmon local box overflow control MSR. DD0H 3536 MSR_C3_PMON_EVNT_SEL0 Package Uncore C-box 3 perfmon event select MSR. DD1H 3537 MSR_C3_PMON_CTR0 Package Uncore C-box 3 perfmon counter MSR. DD2H 3538 MSR_C3_PMON_EVNT_SEL1 Package Uncore C-box 3 perfmon event select MSR. DD3H 3539 MSR_C3_PMON_CTR1 Package Uncore C-box 3 perfmon counter MSR. DD4H 3540 MSR_C3_PMON_EVNT_SEL2 Package Uncore C-box 3 perfmon event select MSR. DD5H 3541 MSR_C3_PMON_CTR2 Package Uncore C-box 3 perfmon counter MSR. DD6H 3542 MSR_C3_PMON_EVNT_SEL3 Package Uncore C-box 3 perfmon event select MSR. DD7H 3543 MSR_C3_PMON_CTR3 Package Uncore C-box 3 perfmon counter MSR. DD8H 3544 MSR_C3_PMON_EVNT_SEL4 Package Uncore C-box 3 perfmon event select MSR. DD9H 3545 MSR_C3_PMON_CTR4 Package Uncore C-box 3 perfmon counter MSR. DDAH 3546 MSR_C3_PMON_EVNT_SEL5 Package Uncore C-box 3 perfmon event select MSR. DDBH 3547 MSR_C3_PMON_CTR5 Package Uncore C-box 3 perfmon counter MSR. 2-150 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-17. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.) Register Address Register Name / Bit Fields Scope Bit Description Hex Dec DE0H 3552 MSR_C7_PMON_BOX_CTRL Package Uncore C-box 7 perfmon local box control MSR. DE1H 3553 MSR_C7_PMON_BOX_STATUS Package Uncore C-box 7 perfmon local box status MSR. DE2H 3554 MSR_C7_PMON_BOX_OVF_CTRL Package Uncore C-box 7 perfmon local box overflow control MSR. DF0H 3568 MSR_C7_PMON_EVNT_SEL0 Package Uncore C-box 7 perfmon event select MSR. DF1H 3569 MSR_C7_PMON_CTR0 Package Uncore C-box 7 perfmon counter MSR. DF2H 3570 MSR_C7_PMON_EVNT_SEL1 Package Uncore C-box 7 perfmon event select MSR. DF3H 3571 MSR_C7_PMON_CTR1 Package Uncore C-box 7 perfmon counter MSR. DF4H 3572 MSR_C7_PMON_EVNT_SEL2 Package Uncore C-box 7 perfmon event select MSR. DF5H 3573 MSR_C7_PMON_CTR2 Package Uncore C-box 7 perfmon counter MSR. DF6H 3574 MSR_C7_PMON_EVNT_SEL3 Package Uncore C-box 7 perfmon event select MSR. DF7H 3575 MSR_C7_PMON_CTR3 Package Uncore C-box 7 perfmon counter MSR. DF8H 3576 MSR_C7_PMON_EVNT_SEL4 Package Uncore C-box 7 perfmon event select MSR. DF9H 3577 MSR_C7_PMON_CTR4 Package Uncore C-box 7 perfmon counter MSR. DFAH 3578 MSR_C7_PMON_EVNT_SEL5 Package Uncore C-box 7 perfmon event select MSR. DFBH 3579 MSR_C7_PMON_CTR5 Package Uncore C-box 7 perfmon counter MSR. E00H 3584 MSR_R0_PMON_BOX_CTRL Package Uncore R-box 0 perfmon local box control MSR. E01H 3585 MSR_R0_PMON_BOX_STATUS Package Uncore R-box 0 perfmon local box status MSR. E02H 3586 MSR_R0_PMON_BOX_OVF_CTRL Package Uncore R-box 0 perfmon local box overflow control MSR. E04H 3588 MSR_R0_PMON_IPERF0_P0 Package Uncore R-box 0 perfmon IPERF0 unit Port 0 select MSR. E05H 3589 MSR_R0_PMON_IPERF0_P1 Package Uncore R-box 0 perfmon IPERF0 unit Port 1 select MSR. E06H 3590 MSR_R0_PMON_IPERF0_P2 Package Uncore R-box 0 perfmon IPERF0 unit Port 2 select MSR. E07H 3591 MSR_R0_PMON_IPERF0_P3 Package Uncore R-box 0 perfmon IPERF0 unit Port 3 select MSR. E08H 3592 MSR_R0_PMON_IPERF0_P4 Package Uncore R-box 0 perfmon IPERF0 unit Port 4 select MSR. E09H 3593 MSR_R0_PMON_IPERF0_P5 Package Uncore R-box 0 perfmon IPERF0 unit Port 5 select MSR. Vol. 4 2-151 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-17. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.) Register Address Register Name / Bit Fields Scope Bit Description Hex Dec E0AH 3594 MSR_R0_PMON_IPERF0_P6 Package Uncore R-box 0 perfmon IPERF0 unit Port 6 select MSR. E0BH 3595 MSR_R0_PMON_IPERF0_P7 Package Uncore R-box 0 perfmon IPERF0 unit Port 7 select MSR. E0CH 3596 MSR_R0_PMON_QLX_P0 Package Uncore R-box 0 perfmon QLX unit Port 0 select MSR. E0DH 3597 MSR_R0_PMON_QLX_P1 Package Uncore R-box 0 perfmon QLX unit Port 1 select MSR. E0EH 3598 MSR_R0_PMON_QLX_P2 Package Uncore R-box 0 perfmon QLX unit Port 2 select MSR. E0FH 3599 MSR_R0_PMON_QLX_P3 Package Uncore R-box 0 perfmon QLX unit Port 3 select MSR. E10H 3600 MSR_R0_PMON_EVNT_SEL0 Package Uncore R-box 0 perfmon event select MSR. E11H 3601 MSR_R0_PMON_CTR0 Package Uncore R-box 0 perfmon counter MSR. E12H 3602 MSR_R0_PMON_EVNT_SEL1 Package Uncore R-box 0 perfmon event select MSR. E13H 3603 MSR_R0_PMON_CTR1 Package Uncore R-box 0 perfmon counter MSR. E14H 3604 MSR_R0_PMON_EVNT_SEL2 Package Uncore R-box 0 perfmon event select MSR. E15H 3605 MSR_R0_PMON_CTR2 Package Uncore R-box 0 perfmon counter MSR. E16H 3606 MSR_R0_PMON_EVNT_SEL3 Package Uncore R-box 0 perfmon event select MSR. E17H 3607 MSR_R0_PMON_CTR3 Package Uncore R-box 0 perfmon counter MSR. E18H 3608 MSR_R0_PMON_EVNT_SEL4 Package Uncore R-box 0 perfmon event select MSR. E19H 3609 MSR_R0_PMON_CTR4 Package Uncore R-box 0 perfmon counter MSR. E1AH 3610 MSR_R0_PMON_EVNT_SEL5 Package Uncore R-box 0 perfmon event select MSR. E1BH 3611 MSR_R0_PMON_CTR5 Package Uncore R-box 0 perfmon counter MSR. E1CH 3612 MSR_R0_PMON_EVNT_SEL6 Package Uncore R-box 0 perfmon event select MSR. E1DH 3613 MSR_R0_PMON_CTR6 Package Uncore R-box 0 perfmon counter MSR. E1EH 3614 MSR_R0_PMON_EVNT_SEL7 Package Uncore R-box 0 perfmon event select MSR. E1FH 3615 MSR_R0_PMON_CTR7 Package Uncore R-box 0 perfmon counter MSR. E20H 3616 MSR_R1_PMON_BOX_CTRL Package Uncore R-box 1 perfmon local box control MSR. E21H 3617 MSR_R1_PMON_BOX_STATUS Package Uncore R-box 1 perfmon local box status MSR. E22H 3618 MSR_R1_PMON_BOX_OVF_CTRL Package Uncore R-box 1 perfmon local box overflow control MSR. E24H 3620 MSR_R1_PMON_IPERF1_P8 Package Uncore R-box 1 perfmon IPERF1 unit Port 8 select MSR. 2-152 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-17. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.) Register Address Register Name / Bit Fields Scope Bit Description Hex Dec E25H 3621 MSR_R1_PMON_IPERF1_P9 Package Uncore R-box 1 perfmon IPERF1 unit Port 9 select MSR. E26H 3622 MSR_R1_PMON_IPERF1_P10 Package Uncore R-box 1 perfmon IPERF1 unit Port 10 select MSR. E27H 3623 MSR_R1_PMON_IPERF1_P11 Package Uncore R-box 1 perfmon IPERF1 unit Port 11 select MSR. E28H 3624 MSR_R1_PMON_IPERF1_P12 Package Uncore R-box 1 perfmon IPERF1 unit Port 12 select MSR. E29H 3625 MSR_R1_PMON_IPERF1_P13 Package Uncore R-box 1 perfmon IPERF1 unit Port 13 select MSR. E2AH 3626 MSR_R1_PMON_IPERF1_P14 Package Uncore R-box 1 perfmon IPERF1 unit Port 14 select MSR. E2BH 3627 MSR_R1_PMON_IPERF1_P15 Package Uncore R-box 1 perfmon IPERF1 unit Port 15 select MSR. E2CH 3628 MSR_R1_PMON_QLX_P4 Package Uncore R-box 1 perfmon QLX unit Port 4 select MSR. E2DH 3629 MSR_R1_PMON_QLX_P5 Package Uncore R-box 1 perfmon QLX unit Port 5 select MSR. E2EH 3630 MSR_R1_PMON_QLX_P6 Package Uncore R-box 1 perfmon QLX unit Port 6 select MSR. E2FH 3631 MSR_R1_PMON_QLX_P7 Package Uncore R-box 1 perfmon QLX unit Port 7 select MSR. E30H 3632 MSR_R1_PMON_EVNT_SEL8 Package Uncore R-box 1 perfmon event select MSR. E31H 3633 MSR_R1_PMON_CTR8 Package Uncore R-box 1 perfmon counter MSR. E32H 3634 MSR_R1_PMON_EVNT_SEL9 Package Uncore R-box 1 perfmon event select MSR. E33H 3635 MSR_R1_PMON_CTR9 Package Uncore R-box 1 perfmon counter MSR. E34H 3636 MSR_R1_PMON_EVNT_SEL10 Package Uncore R-box 1 perfmon event select MSR. E35H 3637 MSR_R1_PMON_CTR10 Package Uncore R-box 1 perfmon counter MSR. E36H 3638 MSR_R1_PMON_EVNT_SEL11 Package Uncore R-box 1 perfmon event select MSR. E37H 3639 MSR_R1_PMON_CTR11 Package Uncore R-box 1 perfmon counter MSR. E38H 3640 MSR_R1_PMON_EVNT_SEL12 Package Uncore R-box 1 perfmon event select MSR. E39H 3641 MSR_R1_PMON_CTR12 Package Uncore R-box 1 perfmon counter MSR. E3AH 3642 MSR_R1_PMON_EVNT_SEL13 Package Uncore R-box 1 perfmon event select MSR. E3BH 3643 MSR_R1_PMON_CTR13 Package Uncore R-box 1perfmon counter MSR. E3CH 3644 MSR_R1_PMON_EVNT_SEL14 Package Uncore R-box 1 perfmon event select MSR. E3DH 3645 MSR_R1_PMON_CTR14 Package Uncore R-box 1 perfmon counter MSR. Vol. 4 2-153 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-17. Additional MSRs in Intel® Xeon® Processor 7500 Series (Contd.) Register Address Register Name / Bit Fields Scope Bit Description Hex Dec E3EH 3646 MSR_R1_PMON_EVNT_SEL15 Package Uncore R-box 1 perfmon event select MSR. E3FH 3647 MSR_R1_PMON_CTR15 Package Uncore R-box 1 perfmon counter MSR. E45H 3653 MSR_B0_PMON_MATCH Package Uncore B-box 0 perfmon local box match MSR. E46H 3654 MSR_B0_PMON_MASK Package Uncore B-box 0 perfmon local box mask MSR. E49H 3657 MSR_S0_PMON_MATCH Package Uncore S-box 0 perfmon local box match MSR. E4AH 3658 MSR_S0_PMON_MASK Package Uncore S-box 0 perfmon local box mask MSR. E4DH 3661 MSR_B1_PMON_MATCH Package Uncore B-box 1 perfmon local box match MSR. E4EH 3662 MSR_B1_PMON_MASK Package Uncore B-box 1 perfmon local box mask MSR. E54H 3668 MSR_M0_PMON_MM_CONFIG Package Uncore M-box 0 perfmon local box address match/mask config MSR. E55H 3669 MSR_M0_PMON_ADDR_MATCH Package Uncore M-box 0 perfmon local box address match MSR. E56H 3670 MSR_M0_PMON_ADDR_MASK Package Uncore M-box 0 perfmon local box address mask MSR. E59H 3673 MSR_S1_PMON_MATCH Package Uncore S-box 1 perfmon local box match MSR. E5AH 3674 MSR_S1_PMON_MASK Package Uncore S-box 1 perfmon local box mask MSR. E5CH 3676 MSR_M1_PMON_MM_CONFIG Package Uncore M-box 1 perfmon local box address match/mask config MSR. E5DH 3677 MSR_M1_PMON_ADDR_MATCH Package Uncore M-box 1 perfmon local box address match MSR. E5EH 3678 MSR_M1_PMON_ADDR_MASK Package Uncore M-box 1 perfmon local box address mask MSR. 3B5H 965 MSR_UNCORE_PMC5 Package See Section 18.3.1.2.2, “Uncore Performance Event Configuration Facility.” 2.9 MSRS IN THE INTEL® XEON® PROCESSOR 5600 SERIES (BASED ON INTEL® MICROARCHITECTURE CODE NAME WESTMERE) Intel® Xeon® Processor 5600 Series (based on Intel® microarchitecture code name Westmere) supports the MSR interfaces listed in Table 2-15, Table 2-16, plus additional MSR listed in Table 2-18. These MSRs apply to Intel Core i7, i5 and i3 processor family with CPUID signature DisplayFamily_DisplayModel of 06_25H and 06_2CH, see Table 2-1. 2-154 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-18. Additional MSRs Supported by Intel Processors (Based on Intel® Microarchitecture Code Name Westmere) Register Address Hex Dec 13CH 52 Register Name / Bit Fields MSR_FEATURE_CONFIG Scope Core Bit Description AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP handler to handle unsuccessful read of this MSR. 1:0 AES Configuration (RW-L) Upon a successful read of this MSR, the configuration of AES instruction set availability is as follows: 11b: AES instructions are not available until next RESET. Otherwise, AES instructions are available. Note, AES instruction set is not available if read is unsuccessful. If the configuration is not 01b, AES instructions can be mis-configured if a privileged agent unintentionally writes 11b. 63:2 Reserved 1A7H 423 MSR_OFFCORE_RSP_1 Thread Offcore Response Event Select Register (R/W) 1ADH 429 MSR_TURBO_RATIO_LIMIT Package Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0. RW if MSR_PLATFORM_INFO.[28] = 1. 7:0 Package Maximum Ratio Limit for 1C Maximum turbo ratio limit of 1 core active. 15:8 Package Maximum Ratio Limit for 2C Maximum turbo ratio limit of 2 core active. 23:16 Package Maximum Ratio Limit for 3C Maximum turbo ratio limit of 3 core active. 31:24 Package Maximum Ratio Limit for 4C Maximum turbo ratio limit of 4 core active. 39:32 Package Maximum Ratio Limit for 5C Maximum turbo ratio limit of 5 core active. 47:40 Package Maximum Ratio Limit for 6C Maximum turbo ratio limit of 6 core active. 63:48 1B0H 2.10 432 IA32_ENERGY_PERF_BIAS Reserved Package See Table 2-2. MSRS IN THE INTEL® XEON® PROCESSOR E7 FAMILY (BASED ON INTEL® MICROARCHITECTURE CODE NAME WESTMERE) Intel® Xeon® Processor E7 Family (based on Intel® microarchitecture code name Westmere) supports the MSR interfaces listed in Table 2-15 (except MSR address 1ADH), Table 2-16, plus additional MSR listed in Table 2-19. These processors have a CPUID signature with DisplayFamily_DisplayModel of 06_2FH. Vol. 4 2-155 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-19. Additional MSRs Supported by Intel® Xeon® Processor E7 Family Register Address Hex Dec 13CH 52 Register Name / Bit Fields MSR_FEATURE_CONFIG Scope Core Bit Description AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP handler to handle unsuccessful read of this MSR. 1:0 AES Configuration (RW-L) Upon a successful read of this MSR, the configuration of AES instruction set availability is as follows: 11b: AES instructions are not available until next RESET. Otherwise, AES instructions are available. Note, AES instruction set is not available if read is unsuccessful. If the configuration is not 01b, AES instructions can be mis-configured if a privileged agent unintentionally writes 11b. 63:2 Reserved 1A7H 423 MSR_OFFCORE_RSP_1 Thread Offcore Response Event Select Register (R/W) 1ADH 429 MSR_TURBO_RATIO_LIMIT Package Reserved Attempt to read/write will cause #UD. 1B0H 432 IA32_ENERGY_PERF_BIAS Package See Table 2-2. F40H 3904 MSR_C8_PMON_BOX_CTRL Package Uncore C-box 8 perfmon local box control MSR. F41H 3905 MSR_C8_PMON_BOX_STATUS Package Uncore C-box 8 perfmon local box status MSR. F42H 3906 MSR_C8_PMON_BOX_OVF_CTRL Package Uncore C-box 8 perfmon local box overflow control MSR. F50H 3920 MSR_C8_PMON_EVNT_SEL0 Package Uncore C-box 8 perfmon event select MSR. F51H 3921 MSR_C8_PMON_CTR0 Package Uncore C-box 8 perfmon counter MSR. F52H 3922 MSR_C8_PMON_EVNT_SEL1 Package Uncore C-box 8 perfmon event select MSR. F53H 3923 MSR_C8_PMON_CTR1 Package Uncore C-box 8 perfmon counter MSR. F54H 3924 MSR_C8_PMON_EVNT_SEL2 Package Uncore C-box 8 perfmon event select MSR. F55H 3925 MSR_C8_PMON_CTR2 Package Uncore C-box 8 perfmon counter MSR. F56H 3926 MSR_C8_PMON_EVNT_SEL3 Package Uncore C-box 8 perfmon event select MSR. F57H 3927 MSR_C8_PMON_CTR3 Package Uncore C-box 8 perfmon counter MSR. F58H 3928 MSR_C8_PMON_EVNT_SEL4 Package Uncore C-box 8 perfmon event select MSR. F59H 3929 MSR_C8_PMON_CTR4 Package Uncore C-box 8 perfmon counter MSR. F5AH 3930 MSR_C8_PMON_EVNT_SEL5 Package Uncore C-box 8 perfmon event select MSR. F5BH 3931 MSR_C8_PMON_CTR5 Package Uncore C-box 8 perfmon counter MSR. 2-156 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-19. Additional MSRs Supported by Intel® Xeon® Processor E7 Family (Contd.) Register Address Register Name / Bit Fields Scope Bit Description Hex Dec FC0H 4032 MSR_C9_PMON_BOX_CTRL Package Uncore C-box 9 perfmon local box control MSR. FC1H 4033 MSR_C9_PMON_BOX_STATUS Package Uncore C-box 9 perfmon local box status MSR. FC2H 4034 MSR_C9_PMON_BOX_OVF_CTRL Package Uncore C-box 9 perfmon local box overflow control MSR. FD0H 4048 MSR_C9_PMON_EVNT_SEL0 Package Uncore C-box 9 perfmon event select MSR. FD1H 4049 MSR_C9_PMON_CTR0 Package Uncore C-box 9 perfmon counter MSR. FD2H 4050 MSR_C9_PMON_EVNT_SEL1 Package Uncore C-box 9 perfmon event select MSR. FD3H 4051 MSR_C9_PMON_CTR1 Package Uncore C-box 9 perfmon counter MSR. FD4H 4052 MSR_C9_PMON_EVNT_SEL2 Package Uncore C-box 9 perfmon event select MSR. FD5H 4053 MSR_C9_PMON_CTR2 Package Uncore C-box 9 perfmon counter MSR. FD6H 4054 MSR_C9_PMON_EVNT_SEL3 Package Uncore C-box 9 perfmon event select MSR. FD7H 4055 MSR_C9_PMON_CTR3 Package Uncore C-box 9 perfmon counter MSR. FD8H 4056 MSR_C9_PMON_EVNT_SEL4 Package Uncore C-box 9 perfmon event select MSR. FD9H 4057 MSR_C9_PMON_CTR4 Package Uncore C-box 9 perfmon counter MSR. FDAH 4058 MSR_C9_PMON_EVNT_SEL5 Package Uncore C-box 9 perfmon event select MSR. FDBH 4059 MSR_C9_PMON_CTR5 Package Uncore C-box 9 perfmon counter MSR. 2.11 MSRS IN INTEL® PROCESSOR FAMILY BASED ON INTEL® MICROARCHITECTURE CODE NAME SANDY BRIDGE Table 2-20 lists model-specific registers (MSRs) that are common to Intel® processor family based on Intel microarchitecture code name Sandy Bridge. These processors have a CPUID signature with DisplayFamily_DisplayModel of 06_2AH, 06_2DH, see Table 2-1. Additional MSRs specific to 06_2AH are listed in Table 2-21. Table 2-20. MSRs Supported by Intel® Processors based on Intel® microarchitecture code name Sandy Bridge Register Address Register Name / Bit Fields Scope Bit Description Hex Dec 0H 0 IA32_P5_MC_ADDR Thread See Section 2.23, “MSRs in Pentium Processors.” 1H 1 IA32_P5_MC_TYPE Thread See Section 2.23, “MSRs in Pentium Processors.” 6H 6 IA32_MONITOR_FILTER_ SIZE Thread See Section 8.10.5, “Monitor/Mwait Address Range Determination” and Table 2-2. Vol. 4 2-157 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-20. MSRs Supported by Intel® Processors based on Intel® microarchitecture code name Sandy Bridge (Contd.) Register Address Register Name / Bit Fields Scope Bit Description Hex Dec 10H 16 IA32_TIME_STAMP_COUNTER Thread See Section 17.17, “Time-Stamp Counter” and see Table 2-2. 17H 23 IA32_PLATFORM_ID Package Platform ID (R) See Table 2-2. 1BH 27 IA32_APIC_BASE Thread See Section 10.4.4, “Local APIC Status and Location” and Table 2-2. 34H 52 MSR_SMI_COUNT Thread SMI Counter (R/O) 31:0 SMI Count (R/O) Count SMIs. 63:32 3AH 58 IA32_FEATURE_CONTROL Reserved. Thread Control Features in Intel 64 Processor (R/W) See Table 2-2. 0 Lock (R/WL) 1 Enable VMX Inside SMX Operation (R/WL) 2 Enable VMX Outside SMX Operation (R/WL) 14:8 SENTER Local Functions Enables (R/WL) 15 SENTER Global Functions Enable (R/WL) 79H 121 IA32_BIOS_UPDT_TRIG Core BIOS Update Trigger Register (W) 8BH 139 IA32_BIOS_SIGN_ID Thread BIOS Update Signature ID (RO) See Table 2-2. See Table 2-2. C1H 193 IA32_PMC0 Thread C2H 194 IA32_PMC1 Thread Performance Counter Register See Table 2-2. Performance Counter Register See Table 2-2. C3H 195 IA32_PMC2 Thread C4H 196 IA32_PMC3 Thread Performance Counter Register See Table 2-2. Performance Counter Register See Table 2-2. C5H 197 IA32_PMC4 Core Performance Counter Register (if core not shared by threads) C6H 198 IA32_PMC5 Core Performance Counter Register (if core not shared by threads) C7H 199 IA32_PMC6 Core Performance Counter Register (if core not shared by threads) C8H 200 IA32_PMC7 Core Performance Counter Register (if core not shared by threads) 2-158 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-20. MSRs Supported by Intel® Processors based on Intel® microarchitecture code name Sandy Bridge (Contd.) Register Address Hex Dec CEH 206 Register Name / Bit Fields MSR_PLATFORM_INFO Scope Package Bit Description Platform Information Contains power management and other model specific features enumeration. See http://biosbits.org. 7:0 15:8 Reserved Package Maximum Non-Turbo Ratio (R/O) This is the ratio of the frequency that invariant TSC runs at. Frequency = ratio * 100 MHz. 27:16 28 Reserved Package Programmable Ratio Limit for Turbo Mode (R/O) When set to 1, indicates that Programmable Ratio Limit for Turbo mode is enabled. When set to 0, indicates Programmable Ratio Limit for Turbo mode is disabled. 29 Package Programmable TDP Limit for Turbo Mode (R/O) When set to 1, indicates that TDP Limit for Turbo mode is programmable. When set to 0, indicates TDP Limit for Turbo mode is not programmable. 39:30 47:40 Reserved Package Maximum Efficiency Ratio (R/O) This is the minimum ratio (maximum efficiency) that the processor can operate, in units of 100MHz. 63:48 E2H 226 MSR_PKG_CST_CONFIG_CONTROL Reserved Core C-State Configuration Control (R/W) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. See http://biosbits.org. 2:0 Package C-State Limit (R/W) Specifies the lowest processor-specific C-state code name (consuming the least power) for the package. The default is set as factory-configured package C-state limit. The following C-state code name encodings are supported: 000b: C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b: C6 retention 100b: C7 101b: C7s 111: No package C-state limit Note: This field cannot be used to limit package C-state to C3. 9:3 Reserved Vol. 4 2-159 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-20. MSRs Supported by Intel® Processors based on Intel® microarchitecture code name Sandy Bridge (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 10 I/O MWAIT Redirection Enable (R/W) When set, will map IO_read instructions sent to IO register specified by MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions. 14:11 Reserved 15 CFG Lock (R/WO) When set, locks bits 15:0 of this register until next reset. 24:16 Reserved 25 C3 State Auto Demotion Enable (R/W) When set, the processor will conditionally demote C6/C7 requests to C3 based on uncore auto-demote information. 26 C1 State Auto Demotion Enable (R/W) When set, the processor will conditionally demote C3/C6/C7 requests to C1 based on uncore auto-demote information. 27 Enable C3 Undemotion (R/W) When set, enables undemotion from demoted C3. 28 Enable C1 Undemotion (R/W) When set, enables undemotion from demoted C1. 63:29 E4H 228 MSR_PMG_IO_CAPTURE_BASE Reserved Core Power Management IO Redirection in C-state (R/W) See http://biosbits.org. 15:0 LVL_2 Base Address (R/W) Specifies the base address visible to software for IO redirection. If IO MWAIT Redirection is enabled, reads to this address will be consumed by the power management logic and decoded to MWAIT instructions. When IO port address redirection is enabled, this is the IO port address reported to the OS/software. 18:16 C-State Range (R/W) Specifies the encoding value of the maximum C-State code name to be included when IO read to MWAIT redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3 is the max C-State to include. 001b - C6 is the max C-State to include. 010b - C7 is the max C-State to include. 63:19 E7H 231 IA32_MPERF Reserved Thread Maximum Performance Frequency Clock Count (RW) See Table 2-2. 2-160 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-20. MSRs Supported by Intel® Processors based on Intel® microarchitecture code name Sandy Bridge (Contd.) Register Address Hex Dec E8H 232 Register Name / Bit Fields IA32_APERF Scope Thread Bit Description Actual Performance Frequency Clock Count (RW) See Table 2-2. FEH 254 IA32_MTRRCAP Thread 13CH 52 MSR_FEATURE_CONFIG Core See Table 2-2. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP handler to handle unsuccessful read of this MSR. 1:0 AES Configuration (RW-L) Upon a successful read of this MSR, the configuration of AES instruction set availability is as follows: 11b: AES instructions are not available until next RESET. Otherwise, AES instructions are available. Note, AES instruction set is not available if read is unsuccessful. If the configuration is not 01b, AES instructions can be mis-configured if a privileged agent unintentionally writes 11b. 63:2 Reserved 174H 372 IA32_SYSENTER_CS Thread See Table 2-2. 175H 373 IA32_SYSENTER_ESP Thread See Table 2-2. 176H 374 IA32_SYSENTER_EIP Thread See Table 2-2. 179H 377 IA32_MCG_CAP Thread See Table 2-2. 17AH 378 IA32_MCG_STATUS Thread Global Machine Check Status 0 RIPV When set, bit indicates that the instruction addressed by the instruction pointer pushed on the stack (when the machine check was generated) can be used to restart the program. If cleared, the program cannot be reliably restarted. 1 EIPV When set, bit indicates that the instruction addressed by the instruction pointer pushed on the stack (when the machine check was generated) is directly associated with the error. 2 MCIP When set, bit indicates that a machine check has been generated. If a second machine check is detected while this bit is still set, the processor enters a shutdown state. Software should write this bit to 0 after processing a machine check exception. 63:3 Reserved 186H 390 IA32_PERFEVTSEL0 Thread See Table 2-2. 187H 391 IA32_PERFEVTSEL1 Thread See Table 2-2. Vol. 4 2-161 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-20. MSRs Supported by Intel® Processors based on Intel® microarchitecture code name Sandy Bridge (Contd.) Register Address Register Name / Bit Fields Scope Bit Description Hex Dec 188H 392 IA32_PERFEVTSEL2 Thread See Table 2-2. 189H 393 IA32_PERFEVTSEL3 Thread See Table 2-2. 18AH 394 IA32_PERFEVTSEL4 Core See Table 2-2. If CPUID.0AH:EAX[15:8] = 8. 18BH 395 IA32_PERFEVTSEL5 Core See Table 2-2. If CPUID.0AH:EAX[15:8] = 8. 18CH 396 IA32_PERFEVTSEL6 Core See Table 2-2. If CPUID.0AH:EAX[15:8] = 8. 18DH 397 IA32_PERFEVTSEL7 Core See Table 2-2. If CPUID.0AH:EAX[15:8] = 8. 198H 408 IA32_PERF_STATUS Package See Table 2-2. 198H 408 15:0 Current Performance State Value 63:16 Reserved MSR_PERF_STATUS Package 47:32 Performance Status Core Voltage (R/O) P-state core voltage can be computed by MSR_PERF_STATUS[37:32] * (float) 1/(2^13). 199H 409 IA32_PERF_CTL Thread See Table 2-2. 19AH 410 IA32_CLOCK_MODULATION Thread Clock Modulation (R/W) See Table 2-2. IA32_CLOCK_MODULATION MSR was originally named IA32_THERM_CONTROL MSR. 3:0 On demand Clock Modulation Duty Cycle (R/W) In 6.25% increment. 19BH 411 4 On demand Clock Modulation Enable (R/W) 63:5 Reserved IA32_THERM_INTERRUPT Core Thermal Interrupt Control (R/W) See Table 2-2. 19CH 412 IA32_THERM_STATUS Core Thermal Monitor Status (R/W) See Table 2-2. 0 Thermal Status (RO) See Table 2-2. 1 Thermal Status Log (R/WC0) See Table 2-2. 2 PROTCHOT # or FORCEPR# Status (RO) See Table 2-2. 3 PROTCHOT # or FORCEPR# Log (R/WC0) See Table 2-2. 4 Critical Temperature Status (RO) See Table 2-2. 5 Critical Temperature Status Log (R/WC0) See Table 2-2. 2-162 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-20. MSRs Supported by Intel® Processors based on Intel® microarchitecture code name Sandy Bridge (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 6 Thermal Threshold #1 Status (RO) See Table 2-2. 7 Thermal Threshold #1 Log (R/WC0) See Table 2-2. 8 Thermal Threshold #2 Status (RO) See Table 2-2. 9 Thermal Threshold #2 Log (R/WC0) See Table 2-2. 10 Power Limitation Status (RO) See Table 2-2. 11 Power Limitation Log (R/WC0) See Table 2-2. 15:12 Reserved 22:16 Digital Readout (RO) See Table 2-2. 26:23 Reserved 30:27 Resolution in Degrees Celsius (RO) See Table 2-2. 31 Reading Valid (RO) See Table 2-2. 63:32 1A0H 416 Reserved IA32_MISC_ENABLE Enable Misc. Processor Features (R/W) Allows a variety of processor functions to be enabled and disabled. 0 Thread Fast-Strings Enable See Table 2-2 6:1 7 Reserved Thread Performance Monitoring Available (R) See Table 2-2. 10:8 11 Reserved Thread Branch Trace Storage Unavailable (RO) See Table 2-2. 12 Thread Processor Event Based Sampling Unavailable (RO) See Table 2-2. 15:13 16 Reserved Package Enhanced Intel SpeedStep Technology Enable (R/W) See Table 2-2. Vol. 4 2-163 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-20. MSRs Supported by Intel® Processors based on Intel® microarchitecture code name Sandy Bridge (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 18 Thread ENABLE MONITOR FSM (R/W) See Table 2-2. 21:19 22 Reserved Thread Limit CPUID Maxval (R/W) See Table 2-2. 23 Thread xTPR Message Disable (R/W) See Table 2-2. 33:24 34 Reserved Thread XD Bit Disable (R/W) See Table 2-2. 37:35 38 Reserved Package Turbo Mode Disable (R/W) When set to 1 on processors that support Intel Turbo Boost Technology, the turbo mode feature is disabled and the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H: EAX[1] reports the processor’s support of turbo mode is enabled. Note: The power-on default value is used by BIOS to detect hardware support of turbo mode. If the poweron default value is 1, turbo mode is available in the processor. If the power-on default value is 0, turbo mode is not available. 63:39 1A2H 418 MSR_TEMPERATURE_TARGET Reserved Unique 15:0 Temperature Target Reserved 23:16 Temperature Target (R) The minimum temperature at which PROCHOT# will be asserted. The value is degrees C. 1A4H 420 63:24 Reserved MSR_MISC_FEATURE_CONTROL Miscellaneous Feature Control (R/W) 0 Core L2 Hardware Prefetcher Disable (R/W) If 1, disables the L2 hardware prefetcher, which fetches additional lines of code or data into the L2 cache. 1 Core L2 Adjacent Cache Line Prefetcher Disable (R/W) If 1, disables the adjacent cache line prefetcher, which fetches the cache line that comprises a cache line pair (128 bytes). 2-164 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-20. MSRs Supported by Intel® Processors based on Intel® microarchitecture code name Sandy Bridge (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 2 Core DCU Hardware Prefetcher Disable (R/W) If 1, disables the L1 data cache prefetcher, which fetches the next cache line into L1 data cache. 3 Core DCU IP Prefetcher Disable (R/W) If 1, disables the L1 data cache IP prefetcher, which uses sequential load history (based on instruction pointer of previous loads) to determine whether to prefetch additional lines. 63:4 Reserved 1A6H 422 MSR_OFFCORE_RSP_0 Thread Offcore Response Event Select Register (R/W) 1A7H 422 MSR_OFFCORE_RSP_1 Thread Offcore Response Event Select Register (R/W) 1AAH 426 MSR_MISC_PWR_MGMT Miscellaneous Power Management Control Various model specific features enumeration. See http://biosbits.org. 1B0H 432 IA32_ENERGY_PERF_BIAS Package See Table 2-2. 1B1H 433 IA32_PACKAGE_THERM_STATUS Package See Table 2-2. 1B2H 434 IA32_PACKAGE_THERM_INTERRUPT Package See Table 2-2. 1C8H 456 MSR_LBR_SELECT Thread Last Branch Record Filtering Select Register (R/W) See Section 17.9.2, “Filtering of Last Branch Records.” 1C9H 457 0 CPL_EQ_0 1 CPL_NEQ_0 2 JCC 3 NEAR_REL_CALL 4 NEAR_IND_CALL 5 NEAR_RET 6 NEAR_IND_JMP 7 NEAR_REL_JMP 8 FAR_BRANCH 63:9 Reserved MSR_LASTBRANCH_TOS Thread Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) that points to the MSR containing the most recent branch record. See MSR_LASTBRANCH_0_FROM_IP (at 680H). 1D9H 473 IA32_DEBUGCTL Thread Debug Control (R/W) See Table 2-2. 0 LBR: Last Branch Record 1 BTF 5:2 Reserved 6 TR: Branch Trace Vol. 4 2-165 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-20. MSRs Supported by Intel® Processors based on Intel® microarchitecture code name Sandy Bridge (Contd.) Register Address Hex 1DDH Register Name / Bit Fields Scope Bit Description Dec 477 7 BTS: Log Branch Trace Message to BTS buffer 8 BTINT 9 BTS_OFF_OS 10 BTS_OFF_USER 11 FREEZE_LBR_ON_PMI 12 FREEZE_PERFMON_ON_PMI 13 ENABLE_UNCORE_PMI 14 FREEZE_WHILE_SMM 63:15 Reserved MSR_LER_FROM_LIP Thread Last Exception Record From Linear IP (R/W) Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled. 1DEH 478 MSR_LER_TO_LIP Thread Last Exception Record To Linear IP (R/W) This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled. 1F2H 498 IA32_SMRR_PHYSBASE Core See Table 2-2. 1F3H 499 IA32_SMRR_PHYSMASK Core See Table 2-2. 1FCH 508 MSR_POWER_CTL Core See http://biosbits.org. 200H 512 IA32_MTRR_PHYSBASE0 Thread See Table 2-2. 201H 513 IA32_MTRR_PHYSMASK0 Thread See Table 2-2. 202H 514 IA32_MTRR_PHYSBASE1 Thread See Table 2-2. 203H 515 IA32_MTRR_PHYSMASK1 Thread See Table 2-2. 204H 516 IA32_MTRR_PHYSBASE2 Thread See Table 2-2. 205H 517 IA32_MTRR_PHYSMASK2 Thread See Table 2-2. 206H 518 IA32_MTRR_PHYSBASE3 Thread See Table 2-2. 207H 519 IA32_MTRR_PHYSMASK3 Thread See Table 2-2. 208H 520 IA32_MTRR_PHYSBASE4 Thread See Table 2-2. 209H 521 IA32_MTRR_PHYSMASK4 Thread See Table 2-2. 20AH 522 IA32_MTRR_PHYSBASE5 Thread See Table 2-2. 20BH 523 IA32_MTRR_PHYSMASK5 Thread See Table 2-2. 20CH 524 IA32_MTRR_PHYSBASE6 Thread See Table 2-2. 20DH 525 IA32_MTRR_PHYSMASK6 Thread See Table 2-2. 20EH 526 IA32_MTRR_PHYSBASE7 Thread See Table 2-2. 2-166 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-20. MSRs Supported by Intel® Processors based on Intel® microarchitecture code name Sandy Bridge (Contd.) Register Address Register Name / Bit Fields Scope Bit Description Hex Dec 20FH 527 IA32_MTRR_PHYSMASK7 Thread See Table 2-2. 210H 528 IA32_MTRR_PHYSBASE8 Thread See Table 2-2. 211H 529 IA32_MTRR_PHYSMASK8 Thread See Table 2-2. 212H 530 IA32_MTRR_PHYSBASE9 Thread See Table 2-2. 213H 531 IA32_MTRR_PHYSMASK9 Thread See Table 2-2. 250H 592 IA32_MTRR_FIX64K_00000 Thread See Table 2-2. 258H 600 IA32_MTRR_FIX16K_80000 Thread See Table 2-2. 259H 601 IA32_MTRR_FIX16K_A0000 Thread See Table 2-2. 268H 616 IA32_MTRR_FIX4K_C0000 Thread See Table 2-2. 269H 617 IA32_MTRR_FIX4K_C8000 Thread See Table 2-2. 26AH 618 IA32_MTRR_FIX4K_D0000 Thread See Table 2-2. 26BH 619 IA32_MTRR_FIX4K_D8000 Thread See Table 2-2. 26CH 620 IA32_MTRR_FIX4K_E0000 Thread See Table 2-2. 26DH 621 IA32_MTRR_FIX4K_E8000 Thread See Table 2-2. 26EH 622 IA32_MTRR_FIX4K_F0000 Thread See Table 2-2. 26FH 623 IA32_MTRR_FIX4K_F8000 Thread See Table 2-2. 277H 631 IA32_PAT Thread See Table 2-2. 280H 640 IA32_MC0_CTL2 Core See Table 2-2. 281H 641 IA32_MC1_CTL2 Core See Table 2-2. 282H 642 IA32_MC2_CTL2 Core See Table 2-2. 283H 643 IA32_MC3_CTL2 Core See Table 2-2. 284H 644 IA32_MC4_CTL2 Package Always 0 (CMCI not supported). 2FFH 767 IA32_MTRR_DEF_TYPE Thread Default Memory Types (R/W) See Table 2-2. 309H 777 IA32_FIXED_CTR0 Thread Fixed-Function Performance Counter Register 0 (R/W) See Table 2-2. 30AH 778 IA32_FIXED_CTR1 Thread Fixed-Function Performance Counter Register 1 (R/W) See Table 2-2. 30BH 779 IA32_FIXED_CTR2 Thread Fixed-Function Performance Counter Register 2 (R/W) See Table 2-2. 345H 837 IA32_PERF_CAPABILITIES 5:0 Thread See Table 2-2. See Section 17.4.1, “IA32_DEBUGCTL MSR.” LBR Format See Table 2-2. 6 PEBS Record Format. Vol. 4 2-167 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-20. MSRs Supported by Intel® Processors based on Intel® microarchitecture code name Sandy Bridge (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 7 PEBSSaveArchRegs See Table 2-2. 11:8 PEBS_REC_FORMAT See Table 2-2. 12 SMM_FREEZE See Table 2-2. 63:13 38DH 909 IA32_FIXED_CTR_CTRL Reserved Thread Fixed-Function-Counter Control Register (R/W) See Table 2-2. 38EH 910 IA32_PERF_GLOBAL_STATUS See Table 2-2. See Section 18.6.2.2, “Global Counter Control Facilities.” 0 Thread Ovf_PMC0 1 Thread Ovf_PMC1 2 Thread Ovf_PMC2 3 Thread Ovf_PMC3 4 Core Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4) 5 Core Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5) 6 Core Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6) 7 Core Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7) 31:8 Reserved 32 Thread Ovf_FixedCtr0 33 Thread Ovf_FixedCtr1 34 Thread Ovf_FixedCtr2 60:35 38FH 2-168 Vol. 4 911 Reserved 61 Thread Ovf_Uncore 62 Thread Ovf_BufDSSAVE 63 Thread CondChgd IA32_PERF_GLOBAL_CTRL Thread See Table 2-2. See Section 18.6.2.2, “Global Counter Control Facilities.” 0 Thread Set 1 to enable PMC0 to count. 1 Thread Set 1 to enable PMC1 to count. 2 Thread Set 1 to enable PMC2 to count. 3 Thread Set 1 to enable PMC3 to count. 4 Core Set 1 to enable PMC4 to count (if CPUID.0AH:EAX[15:8] > 4). 5 Core Set 1 to enable PMC5 to count (if CPUID.0AH:EAX[15:8] > 5). MODEL-SPECIFIC REGISTERS (MSRS) Table 2-20. MSRs Supported by Intel® Processors based on Intel® microarchitecture code name Sandy Bridge (Contd.) Register Address Hex Register Name / Bit Fields Scope Dec 6 Core Set 1 to enable PMC6 to count (if CPUID.0AH:EAX[15:8] > 6). 7 Core Set 1 to enable PMC7 to count (if CPUID.0AH:EAX[15:8] > 7). 31:8 390H 912 Reserved 32 Thread Set 1 to enable FixedCtr0 to count. 33 Thread Set 1 to enable FixedCtr1 to count. 34 Thread Set 1 to enable FixedCtr2 to count. 63:35 Reserved IA32_PERF_GLOBAL_OVF_CTRL See Table 2-2. See Section 18.6.2.2, “Global Counter Control Facilities.” 0 Thread Set 1 to clear Ovf_PMC0. 1 Thread Set 1 to clear Ovf_PMC1. 2 Thread Set 1 to clear Ovf_PMC2. 3 Thread Set 1 to clear Ovf_PMC3. 4 Core Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4). 5 Core Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5). 6 Core Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6). 7 Core Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7). 31:8 Reserved 32 Thread Set 1 to clear Ovf_FixedCtr0. 33 Thread Set 1 to clear Ovf_FixedCtr1. 34 Thread Set 1 to clear Ovf_FixedCtr2. 60:35 3F1H Bit Description 1009 Reserved 61 Thread Set 1 to clear Ovf_Uncore. 62 Thread Set 1 to clear Ovf_BufDSSAVE. 63 Thread Set 1 to clear CondChgd. MSR_PEBS_ENABLE Thread See Section 18.3.1.1.1, “Processor Event Based Sampling (PEBS).” 0 Enable PEBS on IA32_PMC0. (R/W) 1 Enable PEBS on IA32_PMC1. (R/W) 2 Enable PEBS on IA32_PMC2. (R/W) 3 Enable PEBS on IA32_PMC3. (R/W) 31:4 Reserved 32 Enable Load Latency on IA32_PMC0. (R/W) 33 Enable Load Latency on IA32_PMC1. (R/W) 34 Enable Load Latency on IA32_PMC2. (R/W) Vol. 4 2-169 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-20. MSRs Supported by Intel® Processors based on Intel® microarchitecture code name Sandy Bridge (Contd.) Register Address Hex 3F6H 3F8H Register Name / Bit Fields Scope Bit Description Dec 1014 1016 35 Enable Load Latency on IA32_PMC3. (R/W) 62:36 Reserved 63 Enable Precise Store (R/W) MSR_PEBS_LD_LAT Thread See Section 18.3.1.1.2, “Load Latency Performance Monitoring Facility.” 15:0 Minimum threshold latency value of tagged load operation that will be counted. (R/W) 63:36 Reserved MSR_PKG_C3_RESIDENCY Package 63:0 Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C3 Residency Counter (R/O) Value since last reset that this package is in processorspecific C3 states. Count at the same frequency as the TSC. 3F9H 1017 MSR_PKG_C6_RESIDENCY Package 63:0 Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C6 Residency Counter. (R/O) Value since last reset that this package is in processorspecific C6 states. Count at the same frequency as the TSC. 3FAH 1018 MSR_PKG_C7_RESIDENCY Package 63:0 Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C7 Residency Counter (R/O) Value since last reset that this package is in processorspecific C7 states. Count at the same frequency as the TSC. 3FCH 1020 MSR_CORE_C3_RESIDENCY Core 63:0 Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. CORE C3 Residency Counter (R/O) Value since last reset that this core is in processorspecific C3 states. Count at the same frequency as the TSC. 3FDH 1021 MSR_CORE_C6_RESIDENCY 63:0 Core Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. CORE C6 Residency Counter (R/O) Value since last reset that this core is in processorspecific C6 states. Count at the same frequency as the TSC. 2-170 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-20. MSRs Supported by Intel® Processors based on Intel® microarchitecture code name Sandy Bridge (Contd.) Register Address Hex Dec 3FEH 1022 Register Name / Bit Fields MSR_CORE_C7_RESIDENCY Scope Core 63:0 Bit Description Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. CORE C7 Residency Counter (R/O) Value since last reset that this core is in processorspecific C7 states. Count at the same frequency as the TSC. 400H 1024 IA32_MC0_CTL Core See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 401H 1025 IA32_MC0_STATUS Core See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. 402H 1026 IA32_MC0_ADDR Core See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 403H 1027 IA32_MC0_MISC Core See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 404H 1028 IA32_MC1_CTL Core See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 405H 1029 IA32_MC1_STATUS Core See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. 406H 1030 IA32_MC1_ADDR Core See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 407H 1031 IA32_MC1_MISC Core See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 408H 1032 IA32_MC2_CTL Core See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 409H 1033 IA32_MC2_STATUS Core See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. 40AH 1034 IA32_MC2_ADDR Core See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 40BH 1035 IA32_MC2_MISC Core See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 40CH 1036 IA32_MC3_CTL Core See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 40DH 1037 IA32_MC3_STATUS Core See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. 40EH 1038 IA32_MC3_ADDR Core See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 40FH 1039 IA32_MC3_MISC Core See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 410H 1040 IA32_MC4_CTL Core See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 0 PCU Hardware Error (R/W) When set, enables signaling of PCU hardware detected errors. 1 PCU Controller Error (R/W) When set, enables signaling of PCU controller detected errors. 2 PCU Firmware Error (R/W) When set, enables signaling of PCU firmware detected errors. 63:2 411H 1041 IA32_MC4_STATUS Reserved Core See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. Vol. 4 2-171 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-20. MSRs Supported by Intel® Processors based on Intel® microarchitecture code name Sandy Bridge (Contd.) Register Address Hex Dec 480H 1152 Register Name / Bit Fields IA32_VMX_BASIC Scope Thread Bit Description Reporting Register of Basic VMX Capabilities (R/O) See Table 2-2. See Appendix A.1, “Basic VMX Information.” 481H 1153 IA32_VMX_PINBASED_CTLS Thread Capability Reporting Register of Pin-Based VM-Execution Controls (R/O) See Table 2-2. See Appendix A.3, “VM-Execution Controls.” 482H 1154 IA32_VMX_PROCBASED_CTLS Thread Capability Reporting Register of Primary ProcessorBased VM-Execution Controls (R/O) See Appendix A.3, “VM-Execution Controls.” 483H 1155 IA32_VMX_EXIT_CTLS Thread Capability Reporting Register of VM-Exit Controls (R/O) See Table 2-2. See Appendix A.4, “VM-Exit Controls.” 484H 1156 IA32_VMX_ENTRY_CTLS Thread Capability Reporting Register of VM-Entry Controls (R/O) See Table 2-2. See Appendix A.5, “VM-Entry Controls.” 485H 1157 IA32_VMX_MISC Thread Reporting Register of Miscellaneous VMX Capabilities (R/O) See Table 2-2. See Appendix A.6, “Miscellaneous Data.” 486H 1158 IA32_VMX_CR0_FIXED0 Thread Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Table 2-2. See Appendix A.7, “VMX-Fixed Bits in CR0.” 487H 1159 IA32_VMX_CR0_FIXED1 Thread Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Table 2-2. See Appendix A.7, “VMX-Fixed Bits in CR0.” 488H 1160 IA32_VMX_CR4_FIXED0 Thread Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Table 2-2. See Appendix A.8, “VMX-Fixed Bits in CR4.” 489H 1161 IA32_VMX_CR4_FIXED1 Thread Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) See Table 2-2. See Appendix A.8, “VMX-Fixed Bits in CR4.” 48AH 1162 IA32_VMX_VMCS_ENUM Thread Capability Reporting Register of VMCS Field Enumeration (R/O) See Table 2-2. See Appendix A.9, “VMCS Enumeration.” 2-172 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-20. MSRs Supported by Intel® Processors based on Intel® microarchitecture code name Sandy Bridge (Contd.) Register Address Register Name / Bit Fields Scope Hex Dec 48BH 1163 IA32_VMX_PROCBASED_CTLS2 Thread 48CH 1164 IA32_VMX_EPT_VPID_ENUM Thread Bit Description Capability Reporting Register of Secondary ProcessorBased VM-Execution Controls (R/O) See Appendix A.3, “VM-Execution Controls.” Capability Reporting Register of EPT and VPID (R/O) See Table 2-2 48DH 1165 IA32_VMX_TRUE_PINBASED_CTLS Thread Capability Reporting Register of Pin-Based VM-Execution Flex Controls (R/O) See Table 2-2 48EH 1166 IA32_VMX_TRUE_PROCBASED_CTLS Thread 48FH 1167 IA32_VMX_TRUE_EXIT_CTLS Thread Capability Reporting Register of Primary ProcessorBased VM-Execution Flex Controls (R/O) See Table 2-2 Capability Reporting Register of VM-Exit Flex Controls (R/O) See Table 2-2 490H 1168 IA32_VMX_TRUE_ENTRY_CTLS Thread Capability Reporting Register of VM-Entry Flex Controls (R/O) See Table 2-2 4C1H 1217 IA32_A_PMC0 Thread See Table 2-2. 4C2H 1218 IA32_A_PMC1 Thread See Table 2-2. 4C3H 1219 IA32_A_PMC2 Thread See Table 2-2. 4C4H 1220 IA32_A_PMC3 Thread See Table 2-2. 4C5H 1221 IA32_A_PMC4 Core See Table 2-2. 4C6H 1222 IA32_A_PMC5 Core See Table 2-2. 4C7H 1223 IA32_A_PMC6 Core See Table 2-2. 4C8H 1224 IA32_A_PMC7 Core See Table 2-2. 600H 1536 IA32_DS_AREA Thread DS Save Area (R/W) See Table 2-2. See Section 18.6.3.4, “Debug Store (DS) Mechanism.” 606H 1542 MSR_RAPL_POWER_UNIT Package Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1, “RAPL Interfaces.” 60AH 1546 MSR_PKGC3_IRTL Package Package C3 Interrupt Response Limit (R/W) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. 9:0 Interrupt Response Time Limit (R/W) Specifies the limit that should be used to decide if the package should be put into a package C3 state. Vol. 4 2-173 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-20. MSRs Supported by Intel® Processors based on Intel® microarchitecture code name Sandy Bridge (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 12:10 Time Unit (R/W) Specifies the encoding value of time unit of the interrupt response time limit. The following time unit encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b: 32768 ns 100b: 1048576 ns 101b: 33554432 ns 14:13 Reserved 15 Valid (R/W) Indicates whether the values in bits 12:0 are valid and can be used by the processor for package C-sate management. 63:16 60BH 1547 MSR_PKGC6_IRTL Reserved Package Package C6 Interrupt Response Limit (R/W) This MSR defines the budget allocated for the package to exit from a C6 to a C0 state, where an interrupt request can be delivered to the core and serviced. Additional core-exit latency may be applicable depending on the actual C-state the core is in. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-states. 9:0 Interrupt Response Time Limit (R/W) Specifies the limit that should be used to decide if the package should be put into a package C6 state. 12:10 Time Unit (R/W) Specifies the encoding value of time unit of the interrupt response time limit. The following time unit encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b: 32768 ns 100b: 1048576 ns 101b: 33554432 ns 14:13 Reserved 15 Valid (R/W) Indicates whether the values in bits 12:0 are valid and can be used by the processor for package C-sate management. 2-174 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-20. MSRs Supported by Intel® Processors based on Intel® microarchitecture code name Sandy Bridge (Contd.) Register Address Hex Register Name / Bit Fields Scope Dec 63:16 60DH Bit Description 1549 MSR_PKG_C2_RESIDENCY Reserved Package 63:0 Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C2 Residency Counter (R/O) Value since last reset that this package is in processorspecific C2 states. Count at the same frequency as the TSC. 610H 1552 MSR_PKG_POWER_LIMIT Package PKG RAPL Power Limit Control (R/W) See Section 14.9.3, “Package RAPL Domain.” 611H 1553 MSR_PKG_ENERGY_STATUS Package PKG Energy Status (R/O) See Section 14.9.3, “Package RAPL Domain.” 614H 1556 MSR_PKG_POWER_INFO Package 638H 1592 MSR_PP0_POWER_LIMIT Package PKG RAPL Parameters (R/W) See Section 14.9.3, “Package RAPL Domain.” PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, “PP0/PP1 RAPL Domains.” 680H 1664 MSR_LASTBRANCH_0_FROM_IP Thread Last Branch Record 0 From IP (R/W) One of sixteen pairs of last branch record registers on the last branch record stack. This part of the stack contains pointers to the source instruction. See also: • Last Branch Record Stack TOS at 1C9H. • Section 17.9.1 and record format in Section 17.4.8.1. 681H 1665 MSR_LASTBRANCH_1_FROM_IP Thread Last Branch Record 1 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 682H 1666 MSR_LASTBRANCH_2_FROM_IP Thread Last Branch Record 2 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 683H 1667 MSR_LASTBRANCH_3_FROM_IP Thread Last Branch Record 3 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 684H 1668 MSR_LASTBRANCH_4_FROM_IP Thread Last Branch Record 4 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 685H 1669 MSR_LASTBRANCH_5_FROM_IP Thread Last Branch Record 5 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 686H 1670 MSR_LASTBRANCH_6_FROM_IP Thread Last Branch Record 6 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 687H 1671 MSR_LASTBRANCH_7_FROM_IP Thread Last Branch Record 7 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 688H 1672 MSR_LASTBRANCH_8_FROM_IP Thread Last Branch Record 8 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 689H 1673 MSR_LASTBRANCH_9_FROM_IP Thread Last Branch Record 9 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. Vol. 4 2-175 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-20. MSRs Supported by Intel® Processors based on Intel® microarchitecture code name Sandy Bridge (Contd.) Register Address Hex Dec 68AH 1674 Register Name / Bit Fields MSR_LASTBRANCH_10_FROM_IP Scope Thread Bit Description Last Branch Record 10 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 68BH 1675 MSR_LASTBRANCH_11_FROM_IP Thread Last Branch Record 11 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 68CH 1676 MSR_LASTBRANCH_12_FROM_IP Thread Last Branch Record 12 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 68DH 1677 MSR_LASTBRANCH_13_FROM_IP Thread Last Branch Record 13 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 68EH 1678 MSR_LASTBRANCH_14_FROM_IP Thread Last Branch Record 14 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 68FH 1679 MSR_LASTBRANCH_15_FROM_IP Thread Last Branch Record 15 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 6C0H 1728 MSR_LASTBRANCH_0_TO_IP Thread Last Branch Record 0 To IP (R/W) One of sixteen pairs of last branch record registers on the last branch record stack. This part of the stack contains pointers to the destination instruction. 6C1H 1729 MSR_LASTBRANCH_1_TO_IP Thread Last Branch Record 1 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6C2H 1730 MSR_LASTBRANCH_2_TO_IP Thread Last Branch Record 2 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6C3H 1731 MSR_LASTBRANCH_3_TO_IP Thread Last Branch Record 3 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6C4H 1732 MSR_LASTBRANCH_4_TO_IP Thread Last Branch Record 4 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6C5H 1733 MSR_LASTBRANCH_5_TO_IP Thread Last Branch Record 5 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6C6H 1734 MSR_LASTBRANCH_6_TO_IP Thread Last Branch Record 6 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6C7H 1735 MSR_LASTBRANCH_7_TO_IP Thread Last Branch Record 7 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6C8H 1736 MSR_LASTBRANCH_8_TO_IP Thread Last Branch Record 8 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6C9H 1737 MSR_LASTBRANCH_9_TO_IP Thread Last Branch Record 9 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6CAH 1738 MSR_LASTBRANCH_10_TO_IP Thread Last Branch Record 10 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6CBH 1739 MSR_LASTBRANCH_11_TO_IP Thread Last Branch Record 11 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 2-176 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-20. MSRs Supported by Intel® Processors based on Intel® microarchitecture code name Sandy Bridge (Contd.) Register Address Hex Dec 6CCH 1740 Register Name / Bit Fields MSR_LASTBRANCH_12_TO_IP Scope Thread Bit Description Last Branch Record 12 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6CDH 1741 MSR_LASTBRANCH_13_TO_IP Thread Last Branch Record 13 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6CEH 1742 MSR_LASTBRANCH_14_TO_IP Thread Last Branch Record 14 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6CFH 1743 MSR_LASTBRANCH_15_TO_IP Thread Last Branch Record 15 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6E0H IA32_TSC_DEADLINE Thread See Table 2-2. 802H83FH X2APIC MSRs Thread See Table 2-2. C000_ 0080H IA32_EFER Thread Extended Feature Enables C000_ 0081H IA32_STAR C000_ 0082H IA32_LSTAR C000_ 0084H IA32_FMASK C000_ 0100H IA32_FS_BASE C000_ 0101H IA32_GS_BASE C000_ 0102H IA32_KERNEL_GS_BASE C000_ 0103H IA32_TSC_AUX 2.11.1 1760 See Table 2-2. Thread System Call Target Address (R/W) See Table 2-2. Thread IA-32e Mode System Call Target Address (R/W) See Table 2-2. Thread System Call Flag Mask (R/W) See Table 2-2. Thread Map of BASE Address of FS (R/W) See Table 2-2. Thread Map of BASE Address of GS (R/W) See Table 2-2. Thread Swap Target of BASE Address of GS (R/W) See Table 2-2. Thread AUXILIARY TSC Signature (R/W) See Table 2-2 and Section 17.17.2, “IA32_TSC_AUX Register and RDTSCP Support.” MSRs In 2nd Generation Intel® Core™ Processor Family (Based on Intel® Microarchitecture Code Name Sandy Bridge) Table 2-21 and Table 2-22 list model-specific registers (MSRs) that are specific to the 2nd generation Intel® Core™ processor family (based on Intel microarchitecture code name Sandy Bridge). These processors have a CPUID signature with DisplayFamily_DisplayModel of 06_2AH; see Table 2-1. Vol. 4 2-177 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-21. MSRs Supported by 2nd Generation Intel® Core™ Processors (Intel® microarchitecture code name Sandy Bridge) Register Address Hex Dec 1ADH 429 Register Name / Bit Fields MSR_TURBO_RATIO_LIMIT Scope Package Bit Description Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0. RW if MSR_PLATFORM_INFO.[28] = 1. 7:0 Package Maximum Ratio Limit for 1C Maximum turbo ratio limit of 1 core active. 15:8 Package Maximum Ratio Limit for 2C Maximum turbo ratio limit of 2 core active. 23:16 Package Maximum Ratio Limit for 3C Maximum turbo ratio limit of 3 core active. 31:24 Package Maximum Ratio Limit for 4C Maximum turbo ratio limit of 4 core active. 63:32 60CH 1548 MSR_PKGC7_IRTL Reserved Package Package C7 Interrupt Response Limit (R/W) This MSR defines the budget allocated for the package to exit from a C7 to a C0 state, where interrupt request can be delivered to the core and serviced. Additional core-exit latency may be applicable depending on the actual C-state the core is in. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-states. 9:0 Interrupt Response Time Limit (R/W) Specifies the limit that should be used to decide if the package should be put into a package C7 state. 12:10 Time Unit (R/W) Specifies the encoding value of time unit of the interrupt response time limit. The following time unit encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b: 32768 ns 100b: 1048576 ns 101b: 33554432 ns 14:13 Reserved 15 Valid (R/W) Indicates whether the values in bits 12:0 are valid and can be used by the processor for package C-sate management. 63:16 2-178 Vol. 4 Reserved MODEL-SPECIFIC REGISTERS (MSRS) Table 2-21. MSRs Supported by 2nd Generation Intel® Core™ Processors (Intel® microarchitecture code name Sandy Bridge) (Contd.) Register Address Hex Dec 639H 1593 Register Name / Bit Fields MSR_PP0_ENERGY_STATUS Scope Package Bit Description PP0 Energy Status (R/O) See Section 14.9.4, “PP0/PP1 RAPL Domains.” 63AH 1594 MSR_PP0_POLICY Package PP0 Balance Policy (R/W) See Section 14.9.4, “PP0/PP1 RAPL Domains.” 640H 1600 MSR_PP1_POWER_LIMIT Package PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, “PP0/PP1 RAPL Domains.” 641H 1601 MSR_PP1_ENERGY_STATUS Package PP1 Energy Status (R/O) See Section 14.9.4, “PP0/PP1 RAPL Domains.” 642H 1602 MSR_PP1_POLICY Package PP1 Balance Policy (R/W) See Section 14.9.4, “PP0/PP1 RAPL Domains.” See Table 2-20, Table 2-21, and Table 2-22 for MSR definitions applicable to processors with CPUID signature 06_2AH. Table 2-22 lists the MSRs of uncore PMU for Intel processors with CPUID signature 06_2AH. Table 2-22. Uncore PMU MSRs Supported by 2nd Generation Intel® Core™ Processors Register Address Hex Dec 391H 913 392H 394H 914 916 Register Name / Bit Fields MSR_UNC_PERF_GLOBAL_CTRL Scope Package Bit Description Uncore PMU Global Control 0 Slice 0 select. 1 Slice 1 select. 2 Slice 2 select. 3 Slice 3 select. 4 Slice 4 select. 18:5 Reserved 29 Enable all uncore counters. 30 Enable wake on PMI. 31 Enable Freezing counter when overflow. 63:32 Reserved MSR_UNC_PERF_GLOBAL_STATUS Package Uncore PMU Main Status 0 Fixed counter overflowed. 1 An ARB counter overflowed. 2 Reserved 3 A CBox counter overflowed (on any slice). 63:4 Reserved MSR_UNC_PERF_FIXED_CTRL Package Uncore Fixed Counter Control (R/W) 19:0 Reserved 20 Enable overflow propagation. Vol. 4 2-179 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-22. Uncore PMU MSRs Supported by 2nd Generation Intel® Core™ Processors Register Address Hex 395H 396H Register Name / Bit Fields Scope Bit Description Dec 917 918 21 Reserved 22 Enable counting. 63:23 Reserved MSR_UNC_PERF_FIXED_CTR Package Uncore Fixed Counter 47:0 Current count. 63:48 Reserved MSR_UNC_CBO_CONFIG Package Uncore C-Box Configuration Information (R/O) 3:0 Report the number of C-Box units with performance counters, including processor cores and processor graphics. 63:4 Reserved 3B0H 946 MSR_UNC_ARB_PERFCTR0 Package Uncore Arb Unit, Performance Counter 0 3B1H 947 MSR_UNC_ARB_PERFCTR1 Package Uncore Arb Unit, Performance Counter 1 3B2H 944 MSR_UNC_ARB_PERFEVTSEL0 Package Uncore Arb Unit, Counter 0 Event Select MSR 3B3H 945 MSR_UNC_ARB_PERFEVTSEL1 Package Uncore Arb unit, Counter 1 Event Select MSR 700H 1792 MSR_UNC_CBO_0_PERFEVTSEL0 Package Uncore C-Box 0, Counter 0 Event Select MSR 701H 1793 MSR_UNC_CBO_0_PERFEVTSEL1 Package Uncore C-Box 0, Counter 1 Event Select MSR 702H 1794 MSR_UNC_CBO_0_PERFEVTSEL2 Package Uncore C-Box 0, Counter 2 Event Select MSR 703H 1795 MSR_UNC_CBO_0_PERFEVTSEL3 Package Uncore C-Box 0, Counter 3 Event Select MSR 705H 1797 MSR_UNC_CBO_0_UNIT_STATUS Package Uncore C-Box 0, Unit Status for Counter 0-3 706H 1798 MSR_UNC_CBO_0_PERFCTR0 Package Uncore C-Box 0, Performance Counter 0 707H 1799 MSR_UNC_CBO_0_PERFCTR1 Package Uncore C-Box 0, Performance Counter 1 708H 1800 MSR_UNC_CBO_0_PERFCTR2 Package Uncore C-Box 0, Performance Counter 2 709H 1801 MSR_UNC_CBO_0_PERFCTR3 Package Uncore C-Box 0, Performance Counter 3 710H 1808 MSR_UNC_CBO_1_PERFEVTSEL0 Package Uncore C-Box 1, Counter 0 Event Select MSR 711H 1809 MSR_UNC_CBO_1_PERFEVTSEL1 Package Uncore C-Box 1, Counter 1 Event Select MSR 712H 1810 MSR_UNC_CBO_1_PERFEVTSEL2 Package Uncore C-Box 1, Counter 2 Event Select MSR 713H 1811 MSR_UNC_CBO_1_PERFEVTSEL3 Package Uncore C-Box 1, Counter 3 Event Select MSR 715H 1813 MSR_UNC_CBO_1_UNIT_STATUS Package Uncore C-Box 1, Unit Status for Counter 0-3 716H 1814 MSR_UNC_CBO_1_PERFCTR0 Package Uncore C-Box 1, Performance Counter 0 717H 1815 MSR_UNC_CBO_1_PERFCTR1 Package Uncore C-Box 1, Performance Counter 1 718H 1816 MSR_UNC_CBO_1_PERFCTR2 Package Uncore C-Box 1, Performance Counter 2 719H 1817 MSR_UNC_CBO_1_PERFCTR3 Package Uncore C-Box 1, Performance Counter 3 720H 1824 MSR_UNC_CBO_2_PERFEVTSEL0 Package Uncore C-Box 2, Counter 0 Event Select MSR 721H 1825 MSR_UNC_CBO_2_PERFEVTSEL1 Package Uncore C-Box 2, Counter 1 Event Select MSR 722H 1826 MSR_UNC_CBO_2_PERFEVTSEL2 Package Uncore C-Box 2, Counter 2 Event Select MSR 2-180 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-22. Uncore PMU MSRs Supported by 2nd Generation Intel® Core™ Processors Register Address Register Name / Bit Fields Scope Bit Description Hex Dec 723H 1827 MSR_UNC_CBO_2_PERFEVTSEL3 Package Uncore C-Box 2, Counter 3 Event Select MSR 725H 1829 MSR_UNC_CBO_2_UNIT_STATUS Package Uncore C-Box 2, Unit Status for Counter 0-3 726H 1830 MSR_UNC_CBO_2_PERFCTR0 Package Uncore C-Box 2, Performance Counter 0 727H 1831 MSR_UNC_CBO_2_PERFCTR1 Package Uncore C-Box 2, Performance Counter 1 728H 1832 MSR_UNC_CBO_3_PERFCTR2 Package Uncore C-Box 3, Performance Counter 2 729H 1833 MSR_UNC_CBO_3_PERFCTR3 Package Uncore C-Box 3, Performance Counter 3 730H 1840 MSR_UNC_CBO_3_PERFEVTSEL0 Package Uncore C-Box 3, Counter 0 Event Select MSR 731H 1841 MSR_UNC_CBO_3_PERFEVTSEL1 Package Uncore C-Box 3, Counter 1 Event Select MSR 732H 1842 MSR_UNC_CBO_3_PERFEVTSEL2 Package Uncore C-Box 3, Counter 2 Event Select MSR 733H 1843 MSR_UNC_CBO_3_PERFEVTSEL3 Package Uncore C-Box 3, counter 3 Event Select MSR 735H 1845 MSR_UNC_CBO_3_UNIT_STATUS Package Uncore C-Box 3, Unit Status for Counter 0-3 736H 1846 MSR_UNC_CBO_3_PERFCTR0 Package Uncore C-Box 3, Performance Counter 0 737H 1847 MSR_UNC_CBO_3_PERFCTR1 Package Uncore C-Box 3, Performance Counter 1 738H 1848 MSR_UNC_CBO_3_PERFCTR2 Package Uncore C-Box 3, Performance Counter 2 739H 1849 MSR_UNC_CBO_3_PERFCTR3 Package Uncore C-Box 3, Performance Counter 3 740H 1856 MSR_UNC_CBO_4_PERFEVTSEL0 Package Uncore C-Box 4, Counter 0 Event Select MSR 741H 1857 MSR_UNC_CBO_4_PERFEVTSEL1 Package Uncore C-Box 4, Counter 1 Event Select MSR 742H 1858 MSR_UNC_CBO_4_PERFEVTSEL2 Package Uncore C-Box 4, Counter 2 Event Select MSR 743H 1859 MSR_UNC_CBO_4_PERFEVTSEL3 Package Uncore C-Box 4, Counter 3 Event Select MSR 745H 1861 MSR_UNC_CBO_4_UNIT_STATUS Package Uncore C-Box 4, Unit status for Counter 0-3 746H 1862 MSR_UNC_CBO_4_PERFCTR0 Package Uncore C-Box 4, Performance Counter 0 747H 1863 MSR_UNC_CBO_4_PERFCTR1 Package Uncore C-Box 4, Performance Counter 1 748H 1864 MSR_UNC_CBO_4_PERFCTR2 Package Uncore C-Box 4, Performance Counter 2 749H 1865 MSR_UNC_CBO_4_PERFCTR3 Package Uncore C-Box 4, Performance Counter 3 2.11.2 MSRs In Intel® Xeon® Processor E5 Family (Based on Intel® Microarchitecture Code Name Sandy Bridge) Table 2-23 lists additional model-specific registers (MSRs) that are specific to the Intel® Xeon® Processor E5 Family (based on Intel® microarchitecture code name Sandy Bridge). These processors have a CPUID signature with DisplayFamily_DisplayModel of 06_2DH, and also supports MSRs listed in Table 2-20 and Table 2-24. Table 2-23. Selected MSRs Supported by Intel® Xeon® Processors E5 Family (based on Sandy Bridge microarchitecture) Register Address Hex Dec 17FH 383 Register Name / Bit Fields MSR_ERROR_CONTROL 0 Scope Package Bit Description MC Bank Error Configuration (R/W) Reserved Vol. 4 2-181 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-23. Selected MSRs Supported by Intel® Xeon® Processors E5 Family (based on Sandy Bridge microarchitecture) (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 1 MemError Log Enable (R/W) When set, enables IMC status bank to log additional info in bits 36:32. 63:2 1ADH 429 MSR_TURBO_RATIO_LIMIT Reserved Package Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, RW if MSR_PLATFORM_INFO.[28] = 1 7:0 Package Maximum Ratio Limit for 1C Maximum turbo ratio limit of 1 core active. 15:8 Package Maximum Ratio Limit for 2C Maximum turbo ratio limit of 2 cores active. 23:16 Package Maximum Ratio Limit for 3C Maximum turbo ratio limit of 3 cores active. 31:24 Package Maximum Ratio Limit for 4C Maximum turbo ratio limit of 4 cores active. 39:32 Package Maximum Ratio Limit for 5C Maximum turbo ratio limit of 5 cores active. 47:40 Package Maximum Ratio Limit for 6C Maximum turbo ratio limit of 6 cores active. 55:48 Package Maximum Ratio Limit for 7C Maximum turbo ratio limit of 7 cores active. 63:56 Package Maximum Ratio Limit for 8C Maximum turbo ratio limit of 8 cores active. 285H 645 IA32_MC5_CTL2 Package See Table 2-2. 286H 646 IA32_MC6_CTL2 Package See Table 2-2. 287H 647 IA32_MC7_CTL2 Package See Table 2-2. 288H 648 IA32_MC8_CTL2 Package See Table 2-2. 289H 649 IA32_MC9_CTL2 Package See Table 2-2. 28AH 650 IA32_MC10_CTL2 Package See Table 2-2. 28BH 651 IA32_MC11_CTL2 Package See Table 2-2. 28CH 652 IA32_MC12_CTL2 Package See Table 2-2. 28DH 653 IA32_MC13_CTL2 Package See Table 2-2. 28EH 654 IA32_MC14_CTL2 Package See Table 2-2. 28FH 655 IA32_MC15_CTL2 Package See Table 2-2. 290H 656 IA32_MC16_CTL2 Package See Table 2-2. 291H 657 IA32_MC17_CTL2 Package See Table 2-2. 292H 658 IA32_MC18_CTL2 Package See Table 2-2. 293H 659 IA32_MC19_CTL2 Package See Table 2-2. 2-182 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-23. Selected MSRs Supported by Intel® Xeon® Processors E5 Family (based on Sandy Bridge microarchitecture) (Contd.) Register Address Hex Dec 39CH 924 Register Name / Bit Fields MSR_PEBS_NUM_ALT Scope Package 0 Bit Description ENABLE_PEBS_NUM_ALT (RW) ENABLE_PEBS_NUM_ALT (RW) Write 1 to enable alternate PEBS counting logic for specific events requiring additional configuration, see Table 19-19. 63:1 Reserved, must be zero. 414H 1044 IA32_MC5_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 415H 1045 IA32_MC5_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. 416H 1046 IA32_MC5_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 417H 1047 IA32_MC5_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 418H 1048 IA32_MC6_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 419H 1049 IA32_MC6_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. 41AH 1050 IA32_MC6_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 41BH 1051 IA32_MC6_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 41CH 1052 IA32_MC7_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 41DH 1053 IA32_MC7_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. 41EH 1054 IA32_MC7_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 41FH 1055 IA32_MC7_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 420H 1056 IA32_MC8_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 421H 1057 IA32_MC8_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. 422H 1058 IA32_MC8_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 423H 1059 IA32_MC8_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 424H 1060 IA32_MC9_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 425H 1061 IA32_MC9_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. 426H 1062 IA32_MC9_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 427H 1063 IA32_MC9_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 428H 1064 IA32_MC10_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 429H 1065 IA32_MC10_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. 42AH 1066 IA32_MC10_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 42BH 1067 IA32_MC10_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 42CH 1068 IA32_MC11_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 42DH 1069 IA32_MC11_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. Vol. 4 2-183 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-23. Selected MSRs Supported by Intel® Xeon® Processors E5 Family (based on Sandy Bridge microarchitecture) (Contd.) Register Address Register Name / Bit Fields Scope Bit Description Hex Dec 42EH 1070 IA32_MC11_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 42FH 1071 IA32_MC11_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 430H 1072 IA32_MC12_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 431H 1073 IA32_MC12_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. 432H 1074 IA32_MC12_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 433H 1075 IA32_MC12_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 434H 1076 IA32_MC13_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 435H 1077 IA32_MC13_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. 436H 1078 IA32_MC13_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 437H 1079 IA32_MC13_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 438H 1080 IA32_MC14_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 439H 1081 IA32_MC14_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. 43AH 1082 IA32_MC14_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 43BH 1083 IA32_MC14_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 43CH 1084 IA32_MC15_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 43DH 1085 IA32_MC15_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. 43EH 1086 IA32_MC15_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 43FH 1087 IA32_MC15_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 440H 1088 IA32_MC16_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 441H 1089 IA32_MC16_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. 442H 1090 IA32_MC16_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 443H 1091 IA32_MC16_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 444H 1092 IA32_MC17_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 445H 1093 IA32_MC17_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. 446H 1094 IA32_MC17_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 447H 1095 IA32_MC17_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 448H 1096 IA32_MC18_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 449H 1097 IA32_MC18_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. 44AH 1098 IA32_MC18_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 44BH 1099 IA32_MC18_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 44CH 1100 IA32_MC19_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 2-184 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-23. Selected MSRs Supported by Intel® Xeon® Processors E5 Family (based on Sandy Bridge microarchitecture) (Contd.) Register Address Register Name / Bit Fields Scope Bit Description Hex Dec 44DH 1101 IA32_MC19_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS” and Chapter 16. 44EH 1102 IA32_MC19_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 44FH 1103 IA32_MC19_MISC Package See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” 613H 1555 MSR_PKG_PERF_STATUS Package Package RAPL Perf Status (R/O) 618H 1560 MSR_DRAM_POWER_LIMIT Package DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, “DRAM RAPL Domain.” 619H 1561 MSR_DRAM_ENERGY_STATUS Package DRAM Energy Status (R/O) See Section 14.9.5, “DRAM RAPL Domain.” 61BH 1563 MSR_DRAM_PERF_STATUS Package DRAM Performance Throttling Status (R/O) 61CH 1564 MSR_DRAM_POWER_INFO Package DRAM RAPL Parameters (R/W) See Section 14.9.5, “DRAM RAPL Domain.” See Section 14.9.5, “DRAM RAPL Domain.” 639H 1593 MSR_PP0_ENERGY_STATUS Package PP0 Energy Status (R/O) See Section 14.9.4, “PP0/PP1 RAPL Domains.” See Table 2-20, Table 2-23, and Table 2-24 for MSR definitions applicable to processors with CPUID signature 06_2DH. 2.11.3 Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 Family Intel Xeon Processor E5 family is based on the Sandy Bridge microarchitecture. The MSR-based uncore PMU interfaces are listed in Table 2-24. For complete detail of the uncore PMU, refer to Intel Xeon Processor E5 Product Family Uncore Performance Monitoring Guide. These processors have a CPUID signature with DisplayFamily_DisplayModel of 06_2DH Table 2-24. Uncore PMU MSRs in Intel® Xeon® Processor E5 Family Register Address Hex Register Name / Bit Fields Scope Bit Description Dec C08H MSR_U_PMON_UCLK_FIXED_CTL Package Uncore U-box UCLK Fixed Counter Control C09H MSR_U_PMON_UCLK_FIXED_CTR Package Uncore U-box UCLK Fixed Counter C10H MSR_U_PMON_EVNTSEL0 Package Uncore U-box Perfmon Event Select for U-box Counter 0 C11H MSR_U_PMON_EVNTSEL1 Package Uncore U-box Perfmon Event Select for U-box Counter 1 C16H MSR_U_PMON_CTR0 Package Uncore U-box Perfmon Counter 0 C17H MSR_U_PMON_CTR1 Package Uncore U-box Perfmon Counter 1 C24H MSR_PCU_PMON_BOX_CTL Package Uncore PCU Perfmon for PCU-box-wide Control C30H MSR_PCU_PMON_EVNTSEL0 Package Uncore PCU Perfmon Event Select for PCU Counter 0 C31H MSR_PCU_PMON_EVNTSEL1 Package Uncore PCU Perfmon Event Select for PCU Counter 1 C32H MSR_PCU_PMON_EVNTSEL2 Package Uncore PCU Perfmon Event Select for PCU Counter 2 Vol. 4 2-185 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-24. Uncore PMU MSRs in Intel® Xeon® Processor E5 Family (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec C33H MSR_PCU_PMON_EVNTSEL3 Package Uncore PCU Perfmon Event Select for PCU Counter 3 C34H MSR_PCU_PMON_BOX_FILTER Package Uncore PCU Perfmon box-wide Filter C36H MSR_PCU_PMON_CTR0 Package Uncore PCU Perfmon Counter 0 C37H MSR_PCU_PMON_CTR1 Package Uncore PCU Perfmon Counter 1 C38H MSR_PCU_PMON_CTR2 Package Uncore PCU Perfmon Counter 2 C39H MSR_PCU_PMON_CTR3 Package Uncore PCU Perfmon Counter 3 D04H MSR_C0_PMON_BOX_CTL Package Uncore C-box 0 Perfmon Local Box Wide Control D10H MSR_C0_PMON_EVNTSEL0 Package Uncore C-box 0 Perfmon Event Select for C-box 0 Counter 0 D11H MSR_C0_PMON_EVNTSEL1 Package Uncore C-box 0 Perfmon Event Select for C-box 0 Counter 1 D12H MSR_C0_PMON_EVNTSEL2 Package Uncore C-box 0 Perfmon Event Select for C-box 0 Counter 2 D13H MSR_C0_PMON_EVNTSEL3 Package Uncore C-box 0 Perfmon Event Select for C-box 0 Counter 3 D14H MSR_C0_PMON_BOX_FILTER Package Uncore C-box 0 Perfmon Box Wide Filter D16H MSR_C0_PMON_CTR0 Package Uncore C-box 0 Perfmon Counter 0 D17H MSR_C0_PMON_CTR1 Package Uncore C-box 0 Perfmon Counter 1 D18H MSR_C0_PMON_CTR2 Package Uncore C-box 0 Perfmon Counter 2 D19H MSR_C0_PMON_CTR3 Package Uncore C-box 0 Perfmon Counter 3 D24H MSR_C1_PMON_BOX_CTL Package Uncore C-box 1 Perfmon Local Box Wide Control D30H MSR_C1_PMON_EVNTSEL0 Package Uncore C-box 1 Perfmon Event Select for C-box 1 Counter 0 D31H MSR_C1_PMON_EVNTSEL1 Package Uncore C-box 1 Perfmon Event Select for C-box 1 Counter 1 D32H MSR_C1_PMON_EVNTSEL2 Package Uncore C-box 1 Perfmon Event Select for C-box 1 Counter 2 D33H MSR_C1_PMON_EVNTSEL3 Package Uncore C-box 1 Perfmon Event Select for C-box 1 Counter 3 D34H MSR_C1_PMON_BOX_FILTER Package Uncore C-box 1 Perfmon Box Wide Filter D36H MSR_C1_PMON_CTR0 Package Uncore C-box 1 Perfmon Counter 0 D37H MSR_C1_PMON_CTR1 Package Uncore C-box 1 Perfmon Counter 1 D38H MSR_C1_PMON_CTR2 Package Uncore C-box 1 Perfmon Counter 2 D39H MSR_C1_PMON_CTR3 Package Uncore C-box 1 Perfmon Counter 3 D44H MSR_C2_PMON_BOX_CTL Package Uncore C-box 2 Perfmon Local Box Wide Control D50H MSR_C2_PMON_EVNTSEL0 Package Uncore C-box 2 Perfmon Event Select for C-box 2 Counter 0 D51H MSR_C2_PMON_EVNTSEL1 Package Uncore C-box 2 Perfmon Event Select for C-box 2 Counter 1 2-186 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-24. Uncore PMU MSRs in Intel® Xeon® Processor E5 Family (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec D52H MSR_C2_PMON_EVNTSEL2 Package Uncore C-box 2 Perfmon Event Select for C-box 2 Counter 2 D53H MSR_C2_PMON_EVNTSEL3 Package Uncore C-box 2 Perfmon Event Select for C-box 2 Counter 3 D54H MSR_C2_PMON_BOX_FILTER Package Uncore C-box 2 Perfmon Box Wide Filter D56H MSR_C2_PMON_CTR0 Package Uncore C-box 2 Perfmon Counter 0 D57H MSR_C2_PMON_CTR1 Package Uncore C-box 2 Perfmon Counter 1 D58H MSR_C2_PMON_CTR2 Package Uncore C-box 2 Perfmon Counter 2 D59H MSR_C2_PMON_CTR3 Package Uncore C-box 2 Perfmon Counter 3 D64H MSR_C3_PMON_BOX_CTL Package Uncore C-box 3 Perfmon Local Box Wide Control D70H MSR_C3_PMON_EVNTSEL0 Package Uncore C-box 3 Perfmon Event Select for C-box 3 Counter 0 D71H MSR_C3_PMON_EVNTSEL1 Package Uncore C-box 3 Perfmon Event Select for C-box 3 Counter 1 D72H MSR_C3_PMON_EVNTSEL2 Package Uncore C-box 3 Perfmon Event Select for C-box 3 Counter 2 D73H MSR_C3_PMON_EVNTSEL3 Package Uncore C-box 3 Perfmon Event Select for C-box 3 Counter 3 D74H MSR_C3_PMON_BOX_FILTER Package Uncore C-box 3 Perfmon Box Wide Filter D76H MSR_C3_PMON_CTR0 Package Uncore C-box 3 Perfmon Counter 0 D77H MSR_C3_PMON_CTR1 Package Uncore C-box 3 Perfmon Counter 1 D78H MSR_C3_PMON_CTR2 Package Uncore C-box 3 Perfmon Counter 2 D79H MSR_C3_PMON_CTR3 Package Uncore C-box 3 Perfmon Counter 3 D84H MSR_C4_PMON_BOX_CTL Package Uncore C-box 4 Perfmon Local Box Wide Control D90H MSR_C4_PMON_EVNTSEL0 Package Uncore C-box 4 Perfmon Event Select for C-box 4 Counter 0 D91H MSR_C4_PMON_EVNTSEL1 Package Uncore C-box 4 Perfmon Event Select for C-box 4 Counter 1 D92H MSR_C4_PMON_EVNTSEL2 Package Uncore C-box 4 Perfmon Event Select for C-box 4 Counter 2 D93H MSR_C4_PMON_EVNTSEL3 Package Uncore C-box 4 Perfmon Event Select for C-box 4 Counter 3 D94H MSR_C4_PMON_BOX_FILTER Package Uncore C-box 4 Perfmon Box Wide Filter D96H MSR_C4_PMON_CTR0 Package Uncore C-box 4 Perfmon Counter 0 D97H MSR_C4_PMON_CTR1 Package Uncore C-box 4 Perfmon Counter 1 D98H MSR_C4_PMON_CTR2 Package Uncore C-box 4 Perfmon Counter 2 D99H MSR_C4_PMON_CTR3 Package Uncore C-box 4 Perfmon Counter 3 DA4H MSR_C5_PMON_BOX_CTL Package Uncore C-box 5 Perfmon Local Box Wide Control DB0H MSR_C5_PMON_EVNTSEL0 Package Uncore C-box 5 Perfmon Event Select for C-box 5 Counter 0 Vol. 4 2-187 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-24. Uncore PMU MSRs in Intel® Xeon® Processor E5 Family (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec DB1H MSR_C5_PMON_EVNTSEL1 Package Uncore C-box 5 Perfmon Event Select for C-box 5 Counter 1 DB2H MSR_C5_PMON_EVNTSEL2 Package Uncore C-box 5 Perfmon Event Select for C-box 5 Counter 2 DB3H MSR_C5_PMON_EVNTSEL3 Package Uncore C-box 5 Perfmon Event Select for C-box 5 Counter 3 DB4H MSR_C5_PMON_BOX_FILTER Package Uncore C-box 5 Perfmon Box Wide Filter DB6H MSR_C5_PMON_CTR0 Package Uncore C-box 5 Perfmon Counter 0 DB7H MSR_C5_PMON_CTR1 Package Uncore C-box 5 Perfmon Counter 1 DB8H MSR_C5_PMON_CTR2 Package Uncore C-box 5 Perfmon Counter 2 DB9H MSR_C5_PMON_CTR3 Package Uncore C-box 5 Perfmon Counter 3 DC4H MSR_C6_PMON_BOX_CTL Package Uncore C-box 6 Perfmon Local Box Wide Control DD0H MSR_C6_PMON_EVNTSEL0 Package Uncore C-box 6 Perfmon Event Select for C-box 6 Counter 0 DD1H MSR_C6_PMON_EVNTSEL1 Package Uncore C-box 6 Perfmon Event Select for C-box 6 Counter 1 DD2H MSR_C6_PMON_EVNTSEL2 Package Uncore C-box 6 Perfmon Event Select for C-box 6 Counter 2 DD3H MSR_C6_PMON_EVNTSEL3 Package Uncore C-box 6 Perfmon Event Select for C-box 6 Counter 3 DD4H MSR_C6_PMON_BOX_FILTER Package Uncore C-box 6 Perfmon Box Wide Filter DD6H MSR_C6_PMON_CTR0 Package Uncore C-box 6 Perfmon Counter 0 DD7H MSR_C6_PMON_CTR1 Package Uncore C-box 6 Perfmon Counter 1 DD8H MSR_C6_PMON_CTR2 Package Uncore C-box 6 Perfmon Counter 2 DD9H MSR_C6_PMON_CTR3 Package Uncore C-box 6 Perfmon Counter 3 DE4H MSR_C7_PMON_BOX_CTL Package Uncore C-box 7 Perfmon Local Box Wide Control DF0H MSR_C7_PMON_EVNTSEL0 Package Uncore C-box 7 Perfmon Event Select for C-box 7 Counter 0 DF1H MSR_C7_PMON_EVNTSEL1 Package Uncore C-box 7 Perfmon Event Select for C-box 7 Counter 1 DF2H MSR_C7_PMON_EVNTSEL2 Package Uncore C-box 7 Perfmon Event Select for C-box 7 Counter 2 DF3H MSR_C7_PMON_EVNTSEL3 Package Uncore C-box 7 Perfmon Event Select for C-box 7 Counter 3 DF4H MSR_C7_PMON_BOX_FILTER Package Uncore C-box 7 Perfmon Box Wide Filter DF6H MSR_C7_PMON_CTR0 Package Uncore C-box 7 Perfmon Counter 0 DF7H MSR_C7_PMON_CTR1 Package Uncore C-box 7 Perfmon Counter 1 DF8H MSR_C7_PMON_CTR2 Package Uncore C-box 7 Perfmon Counter 2 DF9H MSR_C7_PMON_CTR3 Package Uncore C-box 7 Perfmon Counter 3 2-188 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) 2.12 MSRS IN THE 3RD GENERATION INTEL® CORE™ PROCESSOR FAMILY (BASED ON INTEL® MICROARCHITECTURE CODE NAME IVY BRIDGE) The 3rd generation Intel® Core™ processor family and the Intel® Xeon® processor E3-1200v2 product family (based on Intel microarchitecture code name Ivy Bridge) support the MSR interfaces listed in Table 2-20, Table 2-21, Table 2-22, and Table 2-25. These processors have a CPUID signature with DisplayFamily_DisplayModel of 06_3AH. Table 2-25. Additional MSRs Supported by 3rd Generation Intel® Core™ Processors (based on Intel® microarchitecture code name Ivy Bridge) Register Address Hex Dec CEH 206 Register Name / Bit Fields MSR_PLATFORM_INFO Scope Package Bit Description Platform Information Contains power management and other model specific features enumeration. See http://biosbits.org. 7:0 15:8 Reserved Package Maximum Non-Turbo Ratio (R/O) This is the ratio of the frequency that invariant TSC runs at. Frequency = ratio * 100 MHz. 27:16 28 Reserved Package Programmable Ratio Limit for Turbo Mode (R/O) When set to 1, indicates that Programmable Ratio Limit for Turbo mode is enabled. When set to 0, indicates Programmable Ratio Limit for Turbo mode is disabled. 29 Package Programmable TDP Limit for Turbo Mode (R/O) When set to 1, indicates that TDP Limit for Turbo mode is programmable. When set to 0, indicates that TDP Limit for Turbo mode is not programmable. 31:30 32 Reserved Package Low Power Mode Support (LPM) (R/O) When set to 1, indicates that LPM is supported. When set to 0, indicates LPM is not supported. 34:33 Package Number of ConfigTDP Levels (R/O) 00: Only Base TDP level available. 01: One additional TDP level available. 02: Two additional TDP level available. 11: Reserved 39:35 47:40 Reserved Package Maximum Efficiency Ratio (R/O) This is the minimum ratio (maximum efficiency) that the processor can operate, in units of 100MHz. 55:48 Package Minimum Operating Ratio (R/O) Contains the minimum supported operating ratio in units of 100 MHz. 63:56 Reserved Vol. 4 2-189 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-25. Additional MSRs Supported by 3rd Generation Intel® Core™ Processors (based on Intel® microarchitecture code name Ivy Bridge) (Contd.) Register Address Hex Dec E2H 226 Register Name / Bit Fields MSR_PKG_CST_CONFIG_CONTROL Scope Core Bit Description C-State Configuration Control (R/W) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. See http://biosbits.org. 2:0 Package C-State Limit (R/W) Specifies the lowest processor-specific C-state code name (consuming the least power) for the package. The default is set as factory-configured package Cstate limit. The following C-state code name encodings are supported: 000b: C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b: C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note: This field cannot be used to limit package Cstate to C3. 9:3 Reserved 10 I/O MWAIT Redirection Enable (R/W) When set, will map IO_read instructions sent to IO register specified by MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions. 14:11 Reserved 15 CFG Lock (R/WO) When set, locks bits 15:0 of this register until next reset. 24:16 Reserved 25 C3 State Auto Demotion Enable (R/W) When set, the processor will conditionally demote C6/C7 requests to C3 based on uncore auto-demote information. 26 C1 State Auto Demotion Enable (R/W) When set, the processor will conditionally demote C3/C6/C7 requests to C1 based on uncore autodemote information. 27 Enable C3 Undemotion (R/W) When set, enables undemotion from demoted C3. 28 Enable C1 Undemotion (R/W) When set, enables undemotion from demoted C1. 2-190 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-25. Additional MSRs Supported by 3rd Generation Intel® Core™ Processors (based on Intel® microarchitecture code name Ivy Bridge) (Contd.) Register Address Hex Register Name / Bit Fields Scope Dec 63:29 639H Bit Description 1593 MSR_PP0_ENERGY_STATUS Reserved Package PP0 Energy Status (R/O) See Section 14.9.4, “PP0/PP1 RAPL Domains.” 648H 1608 MSR_CONFIG_TDP_NOMINAL Package 7:0 Base TDP Ratio (R/O) Config_TDP_Base Base TDP level ratio to be used for this specific processor (in units of 100 MHz). 63:8 649H 1609 MSR_CONFIG_TDP_LEVEL1 Reserved Package 14:0 ConfigTDP Level 1 ratio and power level (R/O) PKG_TDP_LVL1 Power setting for ConfigTDP Level 1. 15 Reserved 23:16 Config_TDP_LVL1_Ratio ConfigTDP level 1 ratio to be used for this specific processor. 31:24 Reserved 46:32 PKG_MAX_PWR_LVL1 Max Power setting allowed for ConfigTDP Level 1. 47 Reserved 62:48 PKG_MIN_PWR_LVL1 MIN Power setting allowed for ConfigTDP Level 1. 63 64AH 1610 MSR_CONFIG_TDP_LEVEL2 Reserved Package 14:0 ConfigTDP Level 2 ratio and power level (R/O) PKG_TDP_LVL2 Power setting for ConfigTDP Level 2. 15 Reserved 23:16 Config_TDP_LVL2_Ratio ConfigTDP level 2 ratio to be used for this specific processor. 31:24 Reserved 46:32 PKG_MAX_PWR_LVL2 Max Power setting allowed for ConfigTDP Level 2. 47 Reserved 62:48 PKG_MIN_PWR_LVL2 MIN Power setting allowed for ConfigTDP Level 2. 63 64BH 1611 MSR_CONFIG_TDP_CONTROL Reserved Package ConfigTDP Control (R/W) Vol. 4 2-191 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-25. Additional MSRs Supported by 3rd Generation Intel® Core™ Processors (based on Intel® microarchitecture code name Ivy Bridge) (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 1:0 TDP_LEVEL (RW/L) System BIOS can program this field. 30:2 Reserved. 31 Config_TDP_Lock (RW/L) When this bit is set, the content of this register is locked until a reset. 63:32 64CH 1612 Reserved MSR_TURBO_ACTIVATION_RATIO Package 7:0 ConfigTDP Control (R/W) MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this field. 30:8 Reserved 31 TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the content of this register is locked until a reset. 63:32 Reserved See Table 2-20, Table 2-21 and Table 2-22 for other MSR definitions applicable to processors with CPUID signature 06_3AH. 2.12.1 MSRs In Intel® Xeon® Processor E5 v2 Product Family (Based on Ivy Bridge-E Microarchitecture) Table 2-26 lists model-specific registers (MSRs) that are specific to the Intel® Xeon® Processor E5 v2 Product Family (based on Ivy Bridge-E microarchitecture). These processors have a CPUID signature with DisplayFamily_DisplayModel of 06_3EH, see Table 2-1. These processors supports the MSR interfaces listed in Table 2-20, and Table 2-26. Table 2-26. MSRs Supported by Intel® Xeon® Processors E5 v2 Product Family (based on Ivy Bridge-E microarchitecture) Register Address Hex Dec 4EH 78 2-192 Vol. 4 Register Name / Bit Fields MSR_PPIN_CTL Scope Package Bit Description Protected Processor Inventory Number Enable Control (R/W) MODEL-SPECIFIC REGISTERS (MSRS) Table 2-26. MSRs Supported by Intel® Xeon® Processors E5 v2 Product Family (based on Ivy Bridge-E microarchitecture) (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 0 LockOut (R/WO) Set 1 to prevent further writes to MSR_PPIN_CTL. Writing 1 to MSR_PPINCTL[bit 0] is permitted only if MSR_PPIN_CTL[bit 1] is clear. Default is 0. BIOS should provide an opt-in menu to enable the user to turn on MSR_PPIN_CTL[bit 1] for privileged inventory initialization agent to access MSR_PPIN. After reading MSR_PPIN, the privileged inventory initialization agent should write ‘01b’ to MSR_PPIN_CTL to disable further access to MSR_PPIN and prevent unauthorized modification to MSR_PPIN_CTL. 1 Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible using RDMSR. Once set, attempt to write 1 to MSR_PPIN_CTL[bit 0] will cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP. Default is 0. 63:2 4FH 79 MSR_PPIN Reserved Package 63:0 Protected Processor Inventory Number (R/O) Protected Processor Inventory Number (R/O) A unique value within a given CPUID family/model/stepping signature that a privileged inventory initialization agent can access to identify each physical processor, when access to MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if MSR_PPIN_CTL[bits 1:0] = ‘10b’. CEH 206 MSR_PLATFORM_INFO Package Platform Information Contains power management and other model specific features enumeration. See http://biosbits.org. 7:0 15:8 Reserved Package Maximum Non-Turbo Ratio (R/O) This is the ratio of the frequency that invariant TSC runs at. Frequency = ratio * 100 MHz. 22:16 23 Reserved Package PPIN_CAP (R/O) When set to 1, indicates that Protected Processor Inventory Number (PPIN) capability can be enabled for a privileged system inventory agent to read PPIN from MSR_PPIN. When set to 0, PPIN capability is not supported. An attempt to access MSR_PPIN_CTL or MSR_PPIN will cause #GP. 27:24 Reserved Vol. 4 2-193 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-26. MSRs Supported by Intel® Xeon® Processors E5 v2 Product Family (based on Ivy Bridge-E microarchitecture) (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 28 Package Programmable Ratio Limit for Turbo Mode (R/O) When set to 1, indicates that Programmable Ratio Limit for Turbo mode is enabled. When set to 0, indicates Programmable Ratio Limit for Turbo mode is disabled. 29 Package Programmable TDP Limit for Turbo Mode (R/O) When set to 1, indicates that TDP Limit for Turbo mode is programmable. When set to 0, indicates TDP Limit for Turbo mode is not programmable. 30 Package Programmable TJ OFFSET (R/O) When set to 1, indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to specify a temperature offset. 39:31 47:40 Reserved Package Maximum Efficiency Ratio (R/O) This is the minimum ratio (maximum efficiency) that the processor can operate, in units of 100MHz. 63:48 E2H 226 MSR_PKG_CST_CONFIG_CONTROL Reserved Core C-State Configuration Control (R/W) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-states. See http://biosbits.org. 2:0 Package C-State Limit (R/W) Specifies the lowest processor-specific C-state code name (consuming the least power) for the package. The default is set as factory-configured package Cstate limit. The following C-state code name encodings are supported: 000b: C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b: C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note: This field cannot be used to limit package C-state to C3. 9:3 Reserved 10 I/O MWAIT Redirection Enable (R/W) When set, will map IO_read instructions sent to IO register specified by MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions. 2-194 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-26. MSRs Supported by Intel® Xeon® Processors E5 v2 Product Family (based on Ivy Bridge-E microarchitecture) (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 14:11 Reserved 15 CFG Lock (R/WO) When set, locks bits 15:0 of this register until next reset. 63:16 179H 17FH 377 383 IA32_MCG_CAP Reserved Thread Global Machine Check Capability (R/O) 7:0 Count 8 MCG_CTL_P 9 MCG_EXT_P 10 MCP_CMCI_P 11 MCG_TES_P 15:12 Reserved 23:16 MCG_EXT_CNT 24 MCG_SER_P 25 Reserved 26 MCG_ELOG_P 63:27 Reserved MSR_ERROR_CONTROL Package MC Bank Error Configuration (R/W) 0 Reserved 1 MemError Log Enable (R/W) When set, enables IMC status bank to log additional info in bits 36:32. 63:2 1A2H 418 MSR_TEMPERATURE_TARGET Reserved Package 15:0 Temperature Target Reserved 23:16 Temperature Target (RO) The minimum temperature at which PROCHOT# will be asserted. The value is degrees C. 27:24 TCC Activation Offset (R/W) Specifies a temperature offset in degrees C from the temperature target (bits 23:16). PROCHOT# will assert at the offset target temperature. Write is permitted only if MSR_PLATFORM_INFO.[30] is set. 63:28 1AEH 430 MSR_TURBO_RATIO_LIMIT1 Reserved Package Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0. RW if MSR_PLATFORM_INFO.[28] = 1. 7:0 Package Maximum Ratio Limit for 9C Maximum turbo ratio limit of 9 core active. Vol. 4 2-195 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-26. MSRs Supported by Intel® Xeon® Processors E5 v2 Product Family (based on Ivy Bridge-E microarchitecture) (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 15:8 Package Maximum Ratio Limit for 10C Maximum turbo ratio limit of 10 core active. 23:16 Package Maximum Ratio Limit for 11C Maximum turbo ratio limit of 11 core active. 31:24 Package Maximum Ratio Limit for 12C Maximum turbo ratio limit of 12 core active. 63:32 Reserved 285H 645 IA32_MC5_CTL2 Package See Table 2-2. 286H 646 IA32_MC6_CTL2 Package See Table 2-2. 287H 647 IA32_MC7_CTL2 Package See Table 2-2. 288H 648 IA32_MC8_CTL2 Package See Table 2-2. 289H 649 IA32_MC9_CTL2 Package See Table 2-2. 28AH 650 IA32_MC10_CTL2 Package See Table 2-2. 28BH 651 IA32_MC11_CTL2 Package See Table 2-2. 28CH 652 IA32_MC12_CTL2 Package See Table 2-2. 28DH 653 IA32_MC13_CTL2 Package See Table 2-2. 28EH 654 IA32_MC14_CTL2 Package See Table 2-2. 28FH 655 IA32_MC15_CTL2 Package See Table 2-2. 290H 656 IA32_MC16_CTL2 Package See Table 2-2. 291H 657 IA32_MC17_CTL2 Package See Table 2-2. 292H 658 IA32_MC18_CTL2 Package See Table 2-2. 293H 659 IA32_MC19_CTL2 Package See Table 2-2. 294H 660 IA32_MC20_CTL2 Package See Table 2-2. 295H 661 IA32_MC21_CTL2 Package See Table 2-2. 296H 662 IA32_MC22_CTL2 Package See Table 2-2. 297H 663 IA32_MC23_CTL2 Package See Table 2-2. 298H 664 IA32_MC24_CTL2 Package See Table 2-2. 299H 665 IA32_MC25_CTL2 Package See Table 2-2. 29AH 666 IA32_MC26_CTL2 Package See Table 2-2. 29BH 667 IA32_MC27_CTL2 Package See Table 2-2. 29CH 668 IA32_MC28_CTL2 Package See Table 2-2. 414H 1044 IA32_MC5_CTL Package 415H 1045 IA32_MC5_STATUS Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. 416H 1046 IA32_MC5_ADDR Package 417H 1047 IA32_MC5_MISC Package 2-196 Vol. 4 Bank MC5 reports MC errors from the Intel QPI module. MODEL-SPECIFIC REGISTERS (MSRS) Table 2-26. MSRs Supported by Intel® Xeon® Processors E5 v2 Product Family (based on Ivy Bridge-E microarchitecture) (Contd.) Register Address Register Name / Bit Fields Scope Bit Description Hex Dec 418H 1048 IA32_MC6_CTL Package 419H 1049 IA32_MC6_STATUS Package 41AH 1050 IA32_MC6_ADDR Package 41BH 1051 IA32_MC6_MISC Package 41CH 1052 IA32_MC7_CTL Package 41DH 1053 IA32_MC7_STATUS Package 41EH 1054 IA32_MC7_ADDR Package 41FH 1055 IA32_MC7_MISC Package 420H 1056 IA32_MC8_CTL Package 421H 1057 IA32_MC8_STATUS Package 422H 1058 IA32_MC8_ADDR Package 423H 1059 IA32_MC8_MISC Package 424H 1060 IA32_MC9_CTL Package 425H 1061 IA32_MC9_STATUS Package 426H 1062 IA32_MC9_ADDR Package 427H 1063 IA32_MC9_MISC Package 428H 1064 IA32_MC10_CTL Package 429H 1065 IA32_MC10_STATUS Package 42AH 1066 IA32_MC10_ADDR Package 42BH 1067 IA32_MC10_MISC Package 42CH 1068 IA32_MC11_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 42DH 1069 IA32_MC11_STATUS Package 42EH 1070 IA32_MC11_ADDR Package Bank MC11 reports MC errors from a specific channel of the integrated memory controller. 42FH 1071 IA32_MC11_MISC Package 430H 1072 IA32_MC12_CTL Package 431H 1073 IA32_MC12_STATUS Package 432H 1074 IA32_MC12_ADDR Package 433H 1075 IA32_MC12_MISC Package 434H 1076 IA32_MC13_CTL Package 435H 1077 IA32_MC13_STATUS Package 436H 1078 IA32_MC13_ADDR Package 437H 1079 IA32_MC13_MISC Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC6 reports MC errors from the integrated I/O module. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC7 and MC 8 report MC errors from the two home agents. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC7 and MC 8 report MC errors from the two home agents. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers. Vol. 4 2-197 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-26. MSRs Supported by Intel® Xeon® Processors E5 v2 Product Family (based on Ivy Bridge-E microarchitecture) (Contd.) Register Address Register Name / Bit Fields Scope Bit Description Hex Dec 438H 1080 IA32_MC14_CTL Package 439H 1081 IA32_MC14_STATUS Package 43AH 1082 IA32_MC14_ADDR Package 43BH 1083 IA32_MC14_MISC Package 43CH 1084 IA32_MC15_CTL Package 43DH 1085 IA32_MC15_STATUS Package 43EH 1086 IA32_MC15_ADDR Package 43FH 1087 IA32_MC15_MISC Package 440H 1088 IA32_MC16_CTL Package 441H 1089 IA32_MC16_STATUS Package 442H 1090 IA32_MC16_ADDR Package 443H 1091 IA32_MC16_MISC Package 444H 1092 IA32_MC17_CTL Package 445H 1093 IA32_MC17_STATUS Package 446H 1094 IA32_MC17_ADDR Package 447H 1095 IA32_MC17_MISC Package 448H 1096 IA32_MC18_CTL Package 449H 1097 IA32_MC18_STATUS Package 44AH 1098 IA32_MC18_ADDR Package 44BH 1099 IA32_MC18_MISC Package 44CH 1100 IA32_MC19_CTL Package 44DH 1101 IA32_MC19_STATUS Package 44EH 1102 IA32_MC19_ADDR Package 44FH 1103 IA32_MC19_MISC Package 450H 1104 IA32_MC20_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 451H 1105 IA32_MC20_STATUS Package 452H 1106 IA32_MC20_ADDR Package Bank MC20 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3. 453H 1107 IA32_MC20_MISC Package 454H 1108 IA32_MC21_CTL Package 455H 1109 IA32_MC21_STATUS Package 456H 1110 IA32_MC21_ADDR Package 457H 1111 IA32_MC21_MISC Package 2-198 Vol. 4 See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC17 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC18 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC19 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC21 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3. MODEL-SPECIFIC REGISTERS (MSRS) Table 2-26. MSRs Supported by Intel® Xeon® Processors E5 v2 Product Family (based on Ivy Bridge-E microarchitecture) (Contd.) Register Address Register Name / Bit Fields Scope Hex Dec 458H 1112 IA32_MC22_CTL Package 459H 1113 IA32_MC22_STATUS Package 45AH 1114 IA32_MC22_ADDR Package 45BH 1115 IA32_MC22_MISC Package 45CH 1116 IA32_MC23_CTL Package 45DH 1117 IA32_MC23_STATUS Package 45EH 1118 IA32_MC23_ADDR Package 45FH 1119 IA32_MC23_MISC Package 460H 1120 IA32_MC24_CTL Package 461H 1121 IA32_MC24_STATUS Package 462H 1122 IA32_MC24_ADDR Package 463H 1123 IA32_MC24_MISC Package 464H 1124 IA32_MC25_CTL Package 465H 1125 IA32_MC25_STATUS Package 466H 1126 IA32_MC25_ADDR Package 467H 1127 IA32_MC2MISC Package 468H 1128 IA32_MC26_CTL Package 469H 1129 IA32_MC26_STATUS Package 46AH 1130 IA32_MC26_ADDR Package 46BH 1131 IA32_MC26_MISC Package 46CH 1132 IA32_MC27_CTL Package 46DH 1133 IA32_MC27_STATUS Package 46EH 1134 IA32_MC27_ADDR Package 46FH 1135 IA32_MC27_MISC Package 470H 1136 IA32_MC28_CTL Package 471H 1137 IA32_MC28_STATUS Package 472H 1138 IA32_MC28_ADDR Package 473H 1139 IA32_MC28_MISC Package 613H 1555 MSR_PKG_PERF_STATUS Package 618H 1560 MSR_DRAM_POWER_LIMIT Package Bit Description See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC22 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC23 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC24 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC25 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC26 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC27 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC28 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3. Package RAPL Perf Status (R/O) DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, “DRAM RAPL Domain.” 619H 1561 MSR_DRAM_ENERGY_STATUS Package DRAM Energy Status (R/O) See Section 14.9.5, “DRAM RAPL Domain.” 61BH 1563 MSR_DRAM_PERF_STATUS Package DRAM Performance Throttling Status (R/O) See Section 14.9.5, “DRAM RAPL Domain.” Vol. 4 2-199 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-26. MSRs Supported by Intel® Xeon® Processors E5 v2 Product Family (based on Ivy Bridge-E microarchitecture) (Contd.) Register Address Hex Dec 61CH 1564 Register Name / Bit Fields MSR_DRAM_POWER_INFO Scope Package Bit Description DRAM RAPL Parameters (R/W) See Section 14.9.5, “DRAM RAPL Domain.” 639H 1593 MSR_PP0_ENERGY_STATUS Package PP0 Energy Status (R/O) See Section 14.9.4, “PP0/PP1 RAPL Domains.” See Table 2-20, for other MSR definitions applicable to Intel Xeon processor E5 v2 with CPUID signature 06_3EH. 2.12.2 Additional MSRs Supported by Intel® Xeon® Processor E7 v2 Family Intel® Xeon® processor E7 v2 family (based on Ivy Bridge-E microarchitecture) with CPUID DisplayFamily_DisplayModel signature 06_3EH supports the MSR interfaces listed in Table 2-20, Table 2-26, and Table 2-27. Table 2-27. Additional MSRs Supported by Intel® Xeon® Processor E7 v2 Family with DisplayFamily_DisplayModel Signature 06_3EH Register Address Hex Dec 3AH 58 Register Name / Bit Fields IA32_FEATURE_CONTROL Scope Thread Bit Description Control Features in Intel 64 Processor (R/W) See Table 2-2. 179H 17AH 2-200 Vol. 4 377 378 0 Lock (R/WL) 1 Enable VMX Inside SMX Operation (R/WL) 2 Enable VMX Outside SMX Operation (R/WL) 14:8 SENTER Local Functions Enables (R/WL) 15 SENTER Global Functions Enable (R/WL) 63:16 Reserved IA32_MCG_CAP Thread Global Machine Check Capability (R/O) 7:0 Count 8 MCG_CTL_P 9 MCG_EXT_P 10 MCP_CMCI_P 11 MCG_TES_P 15:12 Reserved 23:16 MCG_EXT_CNT 24 MCG_SER_P 63:25 Reserved IA32_MCG_STATUS Thread Global Machine Check Status (R/WO) 0 RIPV 1 EIPV MODEL-SPECIFIC REGISTERS (MSRS) Table 2-27. Additional MSRs Supported by Intel® Xeon® Processor E7 v2 Family with DisplayFamily_DisplayModel Signature 06_3EH Register Address Hex 1AEH Register Name / Bit Fields Scope Bit Description Dec 430 2 MCIP 3 LMCE Signaled 63:4 Reserved MSR_TURBO_RATIO_LIMIT1 Package Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0. RW if MSR_PLATFORM_INFO.[28] = 1. 7:0 Package Maximum Ratio Limit for 9C Maximum turbo ratio limit of 9 core active. 15:8 Package Maximum Ratio Limit for 10C Maximum turbo ratio limit of 10core active. 23:16 Package Maximum Ratio Limit for 11C Maximum turbo ratio limit of 11 core active. 31:24 Package Maximum Ratio Limit for 12C Maximum turbo ratio limit of 12 core active. 39:32 Package Maximum Ratio Limit for 13C Maximum turbo ratio limit of 13 core active. 47:40 Package Maximum Ratio Limit for 14C Maximum turbo ratio limit of 14 core active. 55:48 Package Maximum Ratio Limit for 15C Maximum turbo ratio limit of 15 core active. 62:56 63 Reserved Package Semaphore for Turbo Ratio Limit Configuration If 1, the processor uses override configuration1 specified in MSR_TURBO_RATIO_LIMIT and MSR_TURBO_RATIO_LIMIT1. If 0, the processor uses factory-set configuration (Default). 29DH 669 IA32_MC29_CTL2 Package See Table 2-2. 29EH 670 IA32_MC30_CTL2 Package See Table 2-2. 29FH 671 IA32_MC31_CTL2 Package See Table 2-2. 3F1H 1009 MSR_PEBS_ENABLE Thread See Section 18.3.1.1.1, “Processor Event Based Sampling (PEBS).” 0 Enable PEBS on IA32_PMC0 (R/W) 1 Enable PEBS on IA32_PMC1 (R/W) 2 Enable PEBS on IA32_PMC2 (R/W) 3 Enable PEBS on IA32_PMC3 (R/W) 31:4 Reserved 32 Enable Load Latency on IA32_PMC0 (R/W) 33 Enable Load Latency on IA32_PMC1 (R/W) Vol. 4 2-201 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-27. Additional MSRs Supported by Intel® Xeon® Processor E7 v2 Family with DisplayFamily_DisplayModel Signature 06_3EH Register Address Hex 41BH Register Name / Bit Fields Scope Bit Description Dec 1051 34 Enable Load Latency on IA32_PMC2 (R/W) 35 Enable Load Latency on IA32_PMC3 (R/W) 63:36 Reserved IA32_MC6_MISC Package Misc MAC Information of Integrated I/O (R/O) See Section 15.3.2.4. 5:0 Recoverable Address LSB 8:6 Address Mode 15:9 Reserved 31:16 PCI Express Requestor ID 39:32 PCI Express Segment Number 63:32 Reserved 474H 1140 IA32_MC29_CTL Package 475H 1141 IA32_MC29_STATUS Package 476H 1142 IA32_MC29_ADDR Package 477H 1143 IA32_MC29_MISC Package 478H 1144 IA32_MC30_CTL Package 479H 1145 IA32_MC30_STATUS Package 47AH 1146 IA32_MC30_ADDR Package 47BH 1147 IA32_MC30_MISC Package 47CH 1148 IA32_MC31_CTL Package 47DH 1149 IA32_MC31_STATUS Package 47EH 1150 IA32_MC31_ADDR Package 47FH 1147 IA32_MC31_MISC Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC29 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC30 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC31 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3. See Table 2-20, Table 2-26 for other MSR definitions applicable to Intel Xeon processor E7 v2 with CPUID signature 06_3AH. NOTES: 1. An override configuration lower than the factory-set configuration is always supported. An override configuration higher than the factory-set configuration is dependent on features specific to the processor and the platform. 2.12.3 Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 v2 and E7 v2 Families Intel Xeon Processor E5 v2 and E7 v2 families are based on the Ivy Bridge-E microarchitecture. The MSR-based uncore PMU interfaces are listed in Table 2-24 and Table 2-28. For complete detail of the uncore PMU, refer to Intel Xeon Processor E5 v2 Product Family Uncore Performance Monitoring Guide. These processors have a CPUID signature with DisplayFamily_DisplayModel of 06_3EH. 2-202 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-28. Uncore PMU MSRs in Intel® Xeon® Processor E5 v2 and E7 v2 Families Register Address Register Name / Bit Fields Scope Bit Description Hex Dec C00H 3072 MSR_PMON_GLOBAL_CTL Package Uncore Perfmon Per-Socket Global Control C01H 3073 MSR_PMON_GLOBAL_STATUS Package Uncore Perfmon Per-Socket Global Status C06H 3078 MSR_PMON_GLOBAL_CONFIG Package Uncore Perfmon Per-Socket Global Configuration C15H 3093 MSR_U_PMON_BOX_STATUS Package Uncore U-box Perfmon U-Box Wide Status C35H 3125 MSR_PCU_PMON_BOX_STATUS Package Uncore PCU Perfmon Box Wide Status D1AH 3354 MSR_C0_PMON_BOX_FILTER1 Package Uncore C-Box 0 Perfmon Box Wide Filter1 D3AH 3386 MSR_C1_PMON_BOX_FILTER1 Package Uncore C-Box 1 Perfmon Box Wide Filter1 D5AH 3418 MSR_C2_PMON_BOX_FILTER1 Package Uncore C-Box 2 Perfmon Box Wide Filter1 D7AH 3450 MSR_C3_PMON_BOX_FILTER1 Package Uncore C-Box 3 Perfmon Box Wide Filter1 D9AH 3482 MSR_C4_PMON_BOX_FILTER1 Package Uncore C-Box 4 Perfmon Box Wide Filter1 DBAH 3514 MSR_C5_PMON_BOX_FILTER1 Package Uncore C-Box 5 Perfmon Box Wide Filter1 DDAH 3546 MSR_C6_PMON_BOX_FILTER1 Package Uncore C-Box 6 Perfmon Box Wide Filter1 DFAH 3578 MSR_C7_PMON_BOX_FILTER1 Package Uncore C-Box 7 Perfmon Box Wide Filter1 E04H 3588 MSR_C8_PMON_BOX_CTL Package Uncore C-Box 8 Perfmon Local Box Wide Control E10H 3600 MSR_C8_PMON_EVNTSEL0 Package Uncore C-Box 8 Perfmon Event Select for C-Box 8 Counter 0 E11H 3601 MSR_C8_PMON_EVNTSEL1 Package Uncore C-Box 8 Perfmon Event Select for C-Box 8 Counter 1 E12H 3602 MSR_C8_PMON_EVNTSEL2 Package Uncore C-Box 8 Perfmon Event Select for C-Box 8 Counter 2 E13H 3603 MSR_C8_PMON_EVNTSEL3 Package Uncore C-Box 8 Perfmon Event Select for C-Box 8 Counter 3 E14H 3604 MSR_C8_PMON_BOX_FILTER Package Uncore C-Box 8 Perfmon Box Wide Filter E16H 3606 MSR_C8_PMON_CTR0 Package Uncore C-Box 8 Perfmon Counter 0 E17H 3607 MSR_C8_PMON_CTR1 Package Uncore C-Box 8 Perfmon Counter 1 E18H 3608 MSR_C8_PMON_CTR2 Package Uncore C-Box 8 Perfmon Counter 2 E19H 3609 MSR_C8_PMON_CTR3 Package Uncore C-Box 8 Perfmon Counter 3 E1AH 3610 MSR_C8_PMON_BOX_FILTER1 Package Uncore C-Box 8 Perfmon Box Wide Filter1 E24H 3620 MSR_C9_PMON_BOX_CTL Package Uncore C-Box 9 Perfmon Local Box Wide Control E30H 3632 MSR_C9_PMON_EVNTSEL0 Package Uncore C-Box 9 Perfmon Event Select for C-box 9 Counter 0 E31H 3633 MSR_C9_PMON_EVNTSEL1 Package Uncore C-Box 9 Perfmon Event Select for C-box 9 Counter 1 E32H 3634 MSR_C9_PMON_EVNTSEL2 Package Uncore C-Box 9 Perfmon Event Select for C-box 9 Counter 2 E33H 3635 MSR_C9_PMON_EVNTSEL3 Package Uncore C-Box 9 Perfmon Event Select for C-box 9 Counter 3 E34H 3636 MSR_C9_PMON_BOX_FILTER Package Uncore C-Box 9 Perfmon Box Wide Filter E36H 3638 MSR_C9_PMON_CTR0 Package Uncore C-Box 9 Perfmon Counter 0 Vol. 4 2-203 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-28. Uncore PMU MSRs in Intel® Xeon® Processor E5 v2 and E7 v2 Families (Contd.) Register Address Register Name / Bit Fields Scope Bit Description Hex Dec E37H 3639 MSR_C9_PMON_CTR1 Package Uncore C-Box 9 Perfmon Counter 1 E38H 3640 MSR_C9_PMON_CTR2 Package Uncore C-Box 9 Perfmon Counter 2 E39H 3641 MSR_C9_PMON_CTR3 Package Uncore C-Box 9 Perfmon Counter 3 E3AH 3642 MSR_C9_PMON_BOX_FILTER1 Package Uncore C-Box 9 Perfmon Box Wide Filter1 E44H 3652 MSR_C10_PMON_BOX_CTL Package Uncore C-Box 10 Perfmon Local Box Wide Control E50H 3664 MSR_C10_PMON_EVNTSEL0 Package Uncore C-Box 10 Perfmon Event Select for C-Box 10 Counter 0 E51H 3665 MSR_C10_PMON_EVNTSEL1 Package Uncore C-Box 10 Perfmon Event Select for C-Box 10 Counter 1 E52H 3666 MSR_C10_PMON_EVNTSEL2 Package Uncore C-Box 10 Perfmon Event Select for C-Box 10 Counter 2 E53H 3667 MSR_C10_PMON_EVNTSEL3 Package Uncore C-Box 10 Perfmon Event Select for C-Box 10 Counter 3 E54H 3668 MSR_C10_PMON_BOX_FILTER Package Uncore C-Box 10 Perfmon Box Wide Filter E56H 3670 MSR_C10_PMON_CTR0 Package Uncore C-Box 10 Perfmon Counter 0 E57H 3671 MSR_C10_PMON_CTR1 Package Uncore C-Box 10 Perfmon Counter 1 E58H 3672 MSR_C10_PMON_CTR2 Package Uncore C-Box 10 Perfmon Counter 2 E59H 3673 MSR_C10_PMON_CTR3 Package Uncore C-Box 10 Perfmon Counter 3 E5AH 3674 MSR_C10_PMON_BOX_FILTER1 Package Uncore C-Box 10 Perfmon Box Wide Filter1 E64H 3684 MSR_C11_PMON_BOX_CTL Package Uncore C-Box 11 Perfmon Local Box Wide Control E70H 3696 MSR_C11_PMON_EVNTSEL0 Package Uncore C-Box 11 Perfmon Event Select for C-Box 11 Counter 0 E71H 3697 MSR_C11_PMON_EVNTSEL1 Package Uncore C-Box 11 Perfmon Event Select for C-Box 11 Counter 1 E72H 3698 MSR_C11_PMON_EVNTSEL2 Package Uncore C-Box 11 Perfmon Event Select for C-Box 11 Counter 2 E73H 3699 MSR_C11_PMON_EVNTSEL3 Package Uncore C-Box 11 Perfmon Event Select for C-Box 11 Counter 3 E74H 3700 MSR_C11_PMON_BOX_FILTER Package Uncore C-Box 11 Perfmon Box Wide Filter E76H 3702 MSR_C11_PMON_CTR0 Package Uncore C-Box 11 Perfmon Counter 0 E77H 3703 MSR_C11_PMON_CTR1 Package Uncore C-Box 11 Perfmon Counter 1 E78H 3704 MSR_C11_PMON_CTR2 Package Uncore C-Box 11 Perfmon Counter 2 E79H 3705 MSR_C11_PMON_CTR3 Package Uncore C-Box 11 Perfmon Counter 3 E7AH 3706 MSR_C11_PMON_BOX_FILTER1 Package Uncore C-Box 11 Perfmon Box Wide Filter1 E84H 3716 MSR_C12_PMON_BOX_CTL Package Uncore C-Box 12 Perfmon Local Box Wide Control E90H 3728 MSR_C12_PMON_EVNTSEL0 Package Uncore C-Box 12 Perfmon Event Select for C-Box 12 Counter 0 E91H 3729 MSR_C12_PMON_EVNTSEL1 Package Uncore C-Box 12 Perfmon Event Select for C-Box 12 Counter 1 2-204 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-28. Uncore PMU MSRs in Intel® Xeon® Processor E5 v2 and E7 v2 Families (Contd.) Register Address Register Name / Bit Fields Scope Bit Description Hex Dec E92H 3730 MSR_C12_PMON_EVNTSEL2 Package Uncore C-Box 12 Perfmon Event Select for C-Box 12 Counter 2 E93H 3731 MSR_C12_PMON_EVNTSEL3 Package Uncore C-Box 12 Perfmon Event Select for C-Box 12 Counter 3 E94H 3732 MSR_C12_PMON_BOX_FILTER Package Uncore C-Box 12 Perfmon Box Wide Filter E96H 3734 MSR_C12_PMON_CTR0 Package Uncore C-Box 12 Perfmon Counter 0 E97H 3735 MSR_C12_PMON_CTR1 Package Uncore C-Box 12 Perfmon Counter 1 E98H 3736 MSR_C12_PMON_CTR2 Package Uncore C-Box 12 Perfmon Counter 2 E99H 3737 MSR_C12_PMON_CTR3 Package Uncore C-Box 12 Perfmon Counter 3 E9AH 3738 MSR_C12_PMON_BOX_FILTER1 Package Uncore C-Box 12 Perfmon Box Wide Filter1 EA4H 3748 MSR_C13_PMON_BOX_CTL Package Uncore C-Box 13 Perfmon Local Box Wide Control EB0H 3760 MSR_C13_PMON_EVNTSEL0 Package Uncore C-Box 13 Perfmon Event Select for C-Box 13 Counter 0 EB1H 3761 MSR_C13_PMON_EVNTSEL1 Package Uncore C-Box 13 Perfmon Event Select for C-Box 13 Counter 1 EB2H 3762 MSR_C13_PMON_EVNTSEL2 Package Uncore C-Box 13 Perfmon Event Select for C-Box 13 Counter 2 EB3H 3763 MSR_C13_PMON_EVNTSEL3 Package Uncore C-Box 13 Perfmon Event Select for C-Box 13 Counter 3 EB4H 3764 MSR_C13_PMON_BOX_FILTER Package Uncore C-Box 13 Perfmon Box Wide Filter EB6H 3766 MSR_C13_PMON_CTR0 Package Uncore C-Box 13 Perfmon Counter 0 EB7H 3767 MSR_C13_PMON_CTR1 Package Uncore C-Box 13 Perfmon Counter 1 EB8H 3768 MSR_C13_PMON_CTR2 Package Uncore C-Box 13 Perfmon Counter 2 EB9H 3769 MSR_C13_PMON_CTR3 Package Uncore C-Box 13 Perfmon Counter 3 EBAH 3770 MSR_C13_PMON_BOX_FILTER1 Package Uncore C-Box 13 Perfmon Box Wide Filter1 EC4H 3780 MSR_C14_PMON_BOX_CTL Package Uncore C-Box 14 Perfmon Local Box Wide Control ED0H 3792 MSR_C14_PMON_EVNTSEL0 Package Uncore C-Box 14 Perfmon Event Select for C-Box 14 Counter 0 ED1H 3793 MSR_C14_PMON_EVNTSEL1 Package Uncore C-Box 14 Perfmon Event Select for C-Box 14 Counter 1 ED2H 3794 MSR_C14_PMON_EVNTSEL2 Package Uncore C-Box 14 Perfmon Event Select for C-Box 14 Counter 2 ED3H 3795 MSR_C14_PMON_EVNTSEL3 Package Uncore C-Box 14 Perfmon Event Select for C-Box 14 Counter 3 ED4H 3796 MSR_C14_PMON_BOX_FILTER Package Uncore C-Box 14 Perfmon Box Wide Filter ED6H 3798 MSR_C14_PMON_CTR0 Package Uncore C-Box 14 Perfmon Counter 0 ED7H 3799 MSR_C14_PMON_CTR1 Package Uncore C-Box 14 Perfmon Counter 1 ED8H 3800 MSR_C14_PMON_CTR2 Package Uncore C-Box 14 Perfmon Counter 2 ED9H 3801 MSR_C14_PMON_CTR3 Package Uncore C-Box 14 Perfmon Counter 3 EDAH 3802 MSR_C14_PMON_BOX_FILTER1 Package Uncore C-Box 14 Perfmon Box Wide Filter1 Vol. 4 2-205 MODEL-SPECIFIC REGISTERS (MSRS) 2.13 MSRS IN THE 4TH GENERATION INTEL® CORE™ PROCESSORS (BASED ON HASWELL MICROARCHITECTURE) The 4th generation Intel® Core™ processor family and Intel® Xeon® processor E3-1200v3 product family (based on Haswell microarchitecture), with CPUID DisplayFamily_DisplayModel signature 06_3CH/06_45H/06_46H, support the MSR interfaces listed in Table 2-20, Table 2-21, Table 2-22, and Table 2-29. For an MSR listed in Table 2-20 that also appears in Table 2-29, Table 2-29 supercede Table 2-20. The MSRs listed in Table 2-29 also apply to processors based on Haswell-E microarchitecture (see Section 2.14). Table 2-29. Additional MSRs Supported by Processors based on the Haswell or Haswell-E microarchitectures Register Address Hex Dec 3BH 59 Register Name / Bit Fields IA32_TSC_ADJUST Scope Thread Bit Description Per-Logical-Processor TSC ADJUST (R/W) See Table 2-2. CEH 206 MSR_PLATFORM_INFO Package Platform Information Contains power management and other model specific features enumeration. See http://biosbits.org. 7:0 15:8 Reserved Package Maximum Non-Turbo Ratio (R/O) This is the ratio of the frequency that invariant TSC runs at. Frequency = ratio * 100 MHz. 27:16 28 Reserved Package Programmable Ratio Limit for Turbo Mode (R/O) When set to 1, indicates that Programmable Ratio Limit for Turbo mode is enabled. When set to 0, indicates Programmable Ratio Limit for Turbo mode is disabled. 29 Package Programmable TDP Limit for Turbo Mode (R/O) When set to 1, indicates that TDP Limit for Turbo mode is programmable. When set to 0, indicates TDP Limit for Turbo mode is not programmable. 31:30 32 Reserved Package Low Power Mode Support (LPM) (R/O) When set to 1, indicates that LPM is supported. When set to 0, indicates LPM is not supported. 34:33 Package Number of ConfigTDP Levels (R/O) 00: Only Base TDP level available. 01: One additional TDP level available. 02: Two additional TDP level available. 11: Reserved 39:35 47:40 Reserved Package Maximum Efficiency Ratio (R/O) This is the minimum ratio (maximum efficiency) that the processor can operate, in units of 100MHz. 2-206 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-29. Additional MSRs Supported by Processors based on the Haswell or Haswell-E microarchitectures Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 55:48 Package Minimum Operating Ratio (R/O) Contains the minimum supported operating ratio in units of 100 MHz. 63:56 186H 390 IA32_PERFEVTSEL0 Reserved Thread Performance Event Select for Counter 0 (R/W) Supports all fields described inTable 2-2 and the fields below. 32 IN_TX: See Section 18.3.6.5.1. When IN_TX (bit 32) is set, AnyThread (bit 21) should be cleared to prevent incorrect results. 187H 391 IA32_PERFEVTSEL1 Thread Performance Event Select for Counter 1 (R/W) Supports all fields described inTable 2-2 and the fields below. 32 IN_TX: See Section 18.3.6.5.1. When IN_TX (bit 32) is set, AnyThread (bit 21) should be cleared to prevent incorrect results. 188H 392 IA32_PERFEVTSEL2 Thread Performance Event Select for Counter 2 (R/W) Supports all fields described inTable 2-2 and the fields below. 32 IN_TX: See Section 18.3.6.5.1. When IN_TX (bit 32) is set, AnyThread (bit 21) should be cleared to prevent incorrect results. 33 IN_TXCP: See Section 18.3.6.5.1. When IN_TXCP=1 & IN_TX=1 and in sampling, a spurious PMI may occur and transactions may continuously abort near overflow conditions. Software should favor using IN_TXCP for counting over sampling. If sampling, software should use large “sample-after” value after clearing the counter configured to use IN_TXCP and also always reset the counter even when no overflow condition was reported. 189H 393 IA32_PERFEVTSEL3 Thread Performance Event Select for Counter 3 (R/W) Supports all fields described inTable 2-2 and the fields below. 32 IN_TX: See Section 18.3.6.5.1 When IN_TX (bit 32) is set, AnyThread (bit 21) should be cleared to prevent incorrect results. 1C8H 456 MSR_LBR_SELECT Thread Last Branch Record Filtering Select Register (R/W) 0 CPL_EQ_0 1 CPL_NEQ_0 2 JCC 3 NEAR_REL_CALL Vol. 4 2-207 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-29. Additional MSRs Supported by Processors based on the Haswell or Haswell-E microarchitectures Register Address Hex 1D9H Register Name / Bit Fields Scope Bit Description Dec 473 4 NEAR_IND_CALL 5 NEAR_RET 6 NEAR_IND_JMP 7 NEAR_REL_JMP 8 FAR_BRANCH 9 EN_CALL_STACK 63:9 Reserved IA32_DEBUGCTL Thread Debug Control (R/W) See Table 2-2. 491H 1169 0 LBR: Last Branch Record 1 BTF 5:2 Reserved 6 TR: Branch Trace 7 BTS: Log Branch Trace Message to BTS Buffer 8 BTINT 9 BTS_OFF_OS 10 BTS_OFF_USER 11 FREEZE_LBR_ON_PMI 12 FREEZE_PERFMON_ON_PMI 13 ENABLE_UNCORE_PMI 14 FREEZE_WHILE_SMM 15 RTM_DEBUG 63:15 Reserved IA32_VMX_VMFUNC Thread Capability Reporting Register of VM-Function Controls (R/O) See Table 2-2. 60BH 1548 MSR_PKGC_IRTL1 Package Package C6/C7 Interrupt Response Limit 1 (R/W) This MSR defines the interrupt response time limit used by the processor to manage a transition to a package C6 or C7 state. The latency programmed in this register is for the shorter-latency sub C-states used by an MWAIT hint to a C6 or C7 state. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. 9:0 Interrupt Response Time Limit (R/W) Specifies the limit that should be used to decide if the package should be put into a package C6 or C7 state. 2-208 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-29. Additional MSRs Supported by Processors based on the Haswell or Haswell-E microarchitectures Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 12:10 Time Unit (R/W) Specifies the encoding value of time unit of the interrupt response time limit. See Table 2-20 for supported time unit encodings. 14:13 Reserved 15 Valid (R/W) Indicates whether the values in bits 12:0 are valid and can be used by the processor for package C-sate management. 63:16 60CH 1548 MSR_PKGC_IRTL2 Reserved Package Package C6/C7 Interrupt Response Limit 2 (R/W) This MSR defines the interrupt response time limit used by the processor to manage a transition to a package C6 or C7 state. The latency programmed in this register is for the longer-latency sub C-states used by an MWAIT hint to a C6 or C7 state. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. 9:0 Interrupt response time limit (R/W) Specifies the limit that should be used to decide if the package should be put into a package C6 or C7 state. 12:10 Time Unit (R/W) Specifies the encoding value of time unit of the interrupt response time limit. See Table 2-20 for supported time unit encodings. 14:13 Reserved 15 Valid (R/W) Indicates whether the values in bits 12:0 are valid and can be used by the processor for package C-sate management. 63:16 613H 1555 MSR_PKG_PERF_STATUS Reserved Package PKG Perf Status (R/O) See Section 14.9.3, “Package RAPL Domain.” 619H 1561 MSR_DRAM_ENERGY_STATUS Package DRAM Energy Status (R/O) See Section 14.9.5, “DRAM RAPL Domain.” 61BH 1563 MSR_DRAM_PERF_STATUS Package DRAM Performance Throttling Status (R/O) See Section 14.9.5, “DRAM RAPL Domain.” 648H 1608 MSR_CONFIG_TDP_NOMINAL 7:0 Package Base TDP Ratio (R/O) Config_TDP_Base Base TDP level ratio to be used for this specific processor (in units of 100 MHz). Vol. 4 2-209 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-29. Additional MSRs Supported by Processors based on the Haswell or Haswell-E microarchitectures Register Address Hex Register Name / Bit Fields Scope Dec 63:8 649H Bit Description 1609 MSR_CONFIG_TDP_LEVEL1 Reserved Package 14:0 ConfigTDP Level 1 Ratio and Power Level (R/O) PKG_TDP_LVL1 Power setting for ConfigTDP Level 1. 15 Reserved 23:16 Config_TDP_LVL1_Ratio ConfigTDP level 1 ratio to be used for this specific processor. 31:24 Reserved 46:32 PKG_MAX_PWR_LVL1 62:47 PKG_MIN_PWR_LVL1 Max Power setting allowed for ConfigTDP Level 1. MIN Power setting allowed for ConfigTDP Level 1. 63 64AH 1610 MSR_CONFIG_TDP_LEVEL2 Reserved Package 14:0 ConfigTDP Level 2 Ratio and Power Level (R/O) PKG_TDP_LVL2 Power setting for ConfigTDP Level 2. 15 Reserved 23:16 Config_TDP_LVL2_Ratio ConfigTDP level 2 ratio to be used for this specific processor. 31:24 Reserved 46:32 PKG_MAX_PWR_LVL2 Max Power setting allowed for ConfigTDP Level 2. 62:47 PKG_MIN_PWR_LVL2 MIN Power setting allowed for ConfigTDP Level 2. 63 64BH 1611 MSR_CONFIG_TDP_CONTROL Reserved Package 1:0 ConfigTDP Control (R/W) TDP_LEVEL (RW/L) System BIOS can program this field. 30:2 Reserved 31 Config_TDP_Lock (RW/L) When this bit is set, the content of this register is locked until a reset. 63:32 64CH 2-210 Vol. 4 1612 MSR_TURBO_ACTIVATION_RATIO Reserved Package ConfigTDP Control (R/W) MODEL-SPECIFIC REGISTERS (MSRS) Table 2-29. Additional MSRs Supported by Processors based on the Haswell or Haswell-E microarchitectures Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 7:0 MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this field. 30:8 Reserved 31 TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the content of this register is locked until a reset. 63:32 C80H 3200 Reserved IA32_DEBUG_INTERFACE Package Silicon Debug Feature Control (R/W) See Table 2-2. 2.13.1 MSRs in 4th Generation Intel® Core™ Processor Family (based on Haswell Microarchitecture) Table 2-30 lists model-specific registers (MSRs) that are specific to 4th generation Intel® Core™ processor family and Intel® Xeon® processor E3-1200 v3 product family (based on Haswell microarchitecture). These processors have a CPUID signature with DisplayFamily_DisplayModel of 06_3CH/06_45H/06_46H, see Table 2-1. Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) Register Address Hex Dec E2H 226 Register Name / Bit Fields MSR_PKG_CST_CONFIG_CONTROL Scope Core Bit Description C-State Configuration Control (R/W) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-states. See http://biosbits.org. 3:0 Package C-State Limit (R/W) Specifies the lowest processor-specific C-state code name (consuming the least power) for the package. The default is set as factory-configured package Cstate limit. The following C-state code name encodings are supported: 0000b: C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6 0100b: C7 0101b: C7s Package C states C7 are not available to processors with a signature of 06_3CH. 9:4 Reserved 10 I/O MWAIT Redirection Enable (R/W) Vol. 4 2-211 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.) Register Address Hex 17DH Register Name / Bit Fields Scope Bit Description Dec 390 14:11 Reserved 15 CFG Lock (R/WO) 24:16 Reserved 25 C3 State Auto Demotion Enable (R/W) 26 C1 State Auto Demotion Enable (R/W) 27 Enable C3 Undemotion (R/W) 28 Enable C1 Undemotion (R/W) 63:29 Reserved MSR_SMM_MCA_CAP THREAD Enhanced SMM Capabilities (SMM-RO) Reports SMM capability Enhancement. Accessible only while in SMM. 57:0 Reserved 58 SMM_Code_Access_Chk (SMM-RO) If set to 1, indicates that the SMM code access restriction is supported and the MSR_SMM_FEATURE_CONTROL is supported. 59 Long_Flow_Indication (SMM-RO) If set to 1, indicates that the SMM long flow indicator is supported and the MSR_SMM_DELAYED is supported. 63:60 1ADH 429 MSR_TURBO_RATIO_LIMIT Reserved Package Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0. RW if MSR_PLATFORM_INFO.[28] = 1. 7:0 Package Maximum Ratio Limit for 1C Maximum turbo ratio limit of 1 core active. 15:8 Package Maximum Ratio Limit for 2C Maximum turbo ratio limit of 2 core active. 23:16 Package Maximum Ratio Limit for 3C Maximum turbo ratio limit of 3 core active. 31:24 Package Maximum Ratio Limit for 4C Maximum turbo ratio limit of 4 core active. 63:32 391H 2-212 Vol. 4 913 MSR_UNC_PERF_GLOBAL_CTRL Reserved Package Uncore PMU Global Control 0 Core 0 select. 1 Core 1 select. 2 Core 2 select. 3 Core 3 select. 18:4 Reserved MODEL-SPECIFIC REGISTERS (MSRS) Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.) Register Address Hex 392H 394H 395H 396H Register Name / Bit Fields Scope Bit Description Dec 914 916 917 918 29 Enable all uncore counters. 30 Enable wake on PMI. 31 Enable Freezing counter when overflow. 63:32 Reserved MSR_UNC_PERF_GLOBAL_STATUS Package Uncore PMU Main Status 0 Fixed counter overflowed. 1 An ARB counter overflowed. 2 Reserved 3 A CBox counter overflowed (on any slice). 63:4 Reserved MSR_UNC_PERF_FIXED_CTRL Package Uncore Fixed Counter Control (R/W) 19:0 Reserved 20 Enable overflow propagation. 21 Reserved 22 Enable counting. 63:23 Reserved MSR_UNC_PERF_FIXED_CTR Package Uncore Fixed Counter 47:0 Current count. 63:48 Reserved MSR_UNC_CBO_CONFIG Package Uncore C-Box Configuration Information (R/O) 3:0 Encoded number of C-Box, derive value by “-1“. 63:4 Reserved 3B0H 946 MSR_UNC_ARB_PERFCTR0 Package Uncore Arb Unit, Performance Counter 0 3B1H 947 MSR_UNC_ARB_PERFCTR1 Package Uncore Arb Unit, Performance Counter 1 3B2H 944 MSR_UNC_ARB_PERFEVTSEL0 Package Uncore Arb Unit, Counter 0 Event Select MSR 3B3H 945 MSR_UNC_ARB_PERFEVTSEL1 Package Uncore Arb Unit, Counter 1 Event Select MSR 391H 913 MSR_UNC_PERF_GLOBAL_CTRL Package Uncore PMU Global Control 0 Core 0 select. 1 Core 1 select. 2 Core 2 select. 3 Core 3 select. 18:4 Reserved 29 Enable all uncore counters. 30 Enable wake on PMI. 31 Enable Freezing counter when overflow. 63:32 Reserved Vol. 4 2-213 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.) Register Address Hex Dec 395H 917 Register Name / Bit Fields MSR_UNC_PERF_FIXED_CTR Scope Package Bit Description Uncore Fixed Counter 47:0 Current count. 63:48 Reserved 3B3H 945 MSR_UNC_ARB_PERFEVTSEL1 Package Uncore Arb Unit, Counter 1 Event Select MSR 4E0H 1248 MSR_SMM_FEATURE_CONTROL Package Enhanced SMM Feature Control (SMM-RW) Reports SMM capability Enhancement. Accessible only while in SMM. 0 Lock (SMM-RWO) When set to ‘1’ locks this register from further changes. 1 Reserved 2 SMM_Code_Chk_En (SMM-RW) This control bit is available only if MSR_SMM_MCA_CAP[58] == 1. When set to ‘0’ (default) none of the logical processors are prevented from executing SMM code outside the ranges defined by the SMRR. When set to ‘1’ any logical processor in the package that attempts to execute SMM code not within the ranges defined by the SMRR will assert an unrecoverable MCE. 63:3 4E2H 1250 MSR_SMM_DELAYED Reserved Package SMM Delayed (SMM-RO) Reports the interruptible state of all logical processors in the package. Available only while in SMM and MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1. N-1:0 LOG_PROC_STATE (SMM-RO) Each bit represents a logical processor of its state in a long flow of internal operation which delays servicing an interrupt. The corresponding bit will be set at the start of long events such as: Microcode Update Load, C6, WBINVD, Ratio Change, Throttle. The bit is automatically cleared at the end of each long event. The reset value of this field is 0. Only bit positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be updated. 63:N 4E3H 1251 MSR_SMM_BLOCKED Reserved Package SMM Blocked (SMM-RO) Reports the blocked state of all logical processors in the package. Available only while in SMM. 2-214 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec N-1:0 LOG_PROC_STATE (SMM-RO) Each bit represents a logical processor of its blocked state to service an SMI. The corresponding bit will be set if the logical processor is in one of the following states: Wait For SIPI or SENTER Sleep. The reset value of this field is 0FFFH. Only bit positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be updated. 63:N 606H 1542 Reserved MSR_RAPL_POWER_UNIT Package 3:0 Package Unit Multipliers Used in RAPL Interfaces (R/O) Power Units See Section 14.9.1, “RAPL Interfaces.” 7:4 Package Reserved 12:8 Package Energy Status Units Energy related information (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an unsigned integer represented by bits 12:8. Default value is 0EH (or 61 micro-joules). 15:13 Package Reserved 19:16 Package Time Units See Section 14.9.1, “RAPL Interfaces.” 63:20 639H 1593 MSR_PP0_ENERGY_STATUS Reserved Package PP0 Energy Status (R/O) See Section 14.9.4, “PP0/PP1 RAPL Domains.” 640H 1600 MSR_PP1_POWER_LIMIT Package PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, “PP0/PP1 RAPL Domains.” 641H 1601 MSR_PP1_ENERGY_STATUS Package PP1 Energy Status (R/O) See Section 14.9.4, “PP0/PP1 RAPL Domains.” 642H 1602 MSR_PP1_POLICY Package PP1 Balance Policy (R/W) See Section 14.9.4, “PP0/PP1 RAPL Domains.” 690H 1680 MSR_CORE_PERF_LIMIT_REASONS Package Indicator of Frequency Clipping in Processor Cores (R/W) (Frequency refers to processor core frequency.) 0 PROCHOT Status (R0) When set, processor core frequency is reduced below the operating system request due to assertion of external PROCHOT. 1 Thermal Status (R0) When set, frequency is reduced below the operating system request due to a thermal event. 3:2 Reserved Vol. 4 2-215 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 4 Graphics Driver Status (R0) When set, frequency is reduced below the operating system request due to Processor Graphics driver override. 5 Autonomous Utilization-Based Frequency Control Status (R0) When set, frequency is reduced below the operating system request because the processor has detected that utilization is low. 6 VR Therm Alert Status (R0) When set, frequency is reduced below the operating system request due to a thermal alert from the Voltage Regulator. 7 Reserved 8 Electrical Design Point Status (R0) When set, frequency is reduced below the operating system request due to electrical design point constraints (e.g., maximum electrical current consumption). 9 Core Power Limiting Status (R0) When set, frequency is reduced below the operating system request due to domain-level power limiting. 10 Package-Level Power Limiting PL1 Status (R0) When set, frequency is reduced below the operating system request due to package-level power limiting PL1. 11 Package-Level PL2 Power Limiting Status (R0) When set, frequency is reduced below the operating system request due to package-level power limiting PL2. 12 Max Turbo Limit Status (R0) When set, frequency is reduced below the operating system request due to multi-core turbo limits. 13 Turbo Transition Attenuation Status (R0) When set, frequency is reduced below the operating system request due to Turbo transition attenuation. This prevents performance degradation due to frequent operating ratio changes. 15:14 Reserved 16 PROCHOT Log When set, indicates that the PROCHOT Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 2-216 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 17 Thermal Log When set, indicates that the Thermal Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 19:18 20 Reserved Graphics Driver Log When set, indicates that the Graphics Driver Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 21 Autonomous Utilization-Based Frequency Control Log When set, indicates that the Autonomous UtilizationBased Frequency Control Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 22 VR Therm Alert Log When set, indicates that the VR Therm Alert Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 23 24 Reserved Electrical Design Point Log When set, indicates that the EDP Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 25 Core Power Limiting Log When set, indicates that the Core Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 26 Package-Level PL1 Power Limiting Log When set, indicates that the Package Level PL1 Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. Vol. 4 2-217 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 27 Package-Level PL2 Power Limiting Log When set, indicates that the Package Level PL2 Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 28 Max Turbo Limit Log When set, indicates that the Max Turbo Limit Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 29 Turbo Transition Attenuation Log When set, indicates that the Turbo Transition Attenuation Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 63:30 6B0H 1712 MSR_GRAPHICS_PERF_LIMIT_REASONS Reserved Package Indicator of Frequency Clipping in the Processor Graphics (R/W) (Frequency refers to processor graphics frequency.) 0 PROCHOT Status (R0) When set, frequency is reduced below the operating system request due to assertion of external PROCHOT. 1 Thermal Status (R0) When set, frequency is reduced below the operating system request due to a thermal event. 3:2 Reserved 4 Graphics Driver Status (R0) When set, frequency is reduced below the operating system request due to Processor Graphics driver override. 5 Autonomous Utilization-Based Frequency Control Status (R0) When set, frequency is reduced below the operating system request because the processor has detected that utilization is low. 6 VR Therm Alert Status (R0) When set, frequency is reduced below the operating system request due to a thermal alert from the Voltage Regulator. 7 2-218 Vol. 4 Reserved MODEL-SPECIFIC REGISTERS (MSRS) Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 8 Electrical Design Point Status (R0) When set, frequency is reduced below the operating system request due to electrical design point constraints (e.g., maximum electrical current consumption). 9 Graphics Power Limiting Status (R0) When set, frequency is reduced below the operating system request due to domain-level power limiting. 10 Package-Level Power Limiting PL1 Status (R0) When set, frequency is reduced below the operating system request due to package-level power limiting PL1. 11 Package-Level PL2 Power Limiting Status (R0) When set, frequency is reduced below the operating system request due to package-level power limiting PL2. 15:12 Reserved 16 PROCHOT Log When set, indicates that the PROCHOT Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 17 Thermal Log When set, indicates that the Thermal Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 19:18 Reserved 20 Graphics Driver Log When set, indicates that the Graphics Driver Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 21 Autonomous Utilization-Based Frequency Control Log When set, indicates that the Autonomous UtilizationBased Frequency Control Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 22 VR Therm Alert Log When set, indicates that the VR Therm Alert Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. Vol. 4 2-219 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 23 Reserved 24 Electrical Design Point Log When set, indicates that the EDP Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 25 Core Power Limiting Log When set, indicates that the Core Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 26 Package-Level PL1 Power Limiting Log When set, indicates that the Package Level PL1 Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 27 Package-Level PL2 Power Limiting Log When set, indicates that the Package Level PL2 Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 28 Max Turbo Limit Log When set, indicates that the Max Turbo Limit Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 29 Turbo Transition Attenuation Log When set, indicates that the Turbo Transition Attenuation Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 63:30 6B1H 1713 MSR_RING_PERF_LIMIT_REASONS Reserved Package Indicator of Frequency Clipping in the Ring Interconnect (R/W) (Frequency refers to ring interconnect in the uncore.) 0 PROCHOT Status (R0) When set, frequency is reduced below the operating system request due to assertion of external PROCHOT. 2-220 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 1 Thermal Status (R0) When set, frequency is reduced below the operating system request due to a thermal event. 5:2 6 Reserved VR Therm Alert Status (R0) When set, frequency is reduced below the operating system request due to a thermal alert from the Voltage Regulator. 7 Reserved 8 Electrical Design Point Status (R0) When set, frequency is reduced below the operating system request due to electrical design point constraints (e.g., maximum electrical current consumption). 9 Reserved 10 Package-Level Power Limiting PL1 Status (R0) When set, frequency is reduced below the operating system request due to package-level power limiting PL1. 11 Package-Level PL2 Power Limiting Status (R0) When set, frequency is reduced below the operating system request due to package-level power limiting PL2. 15:12 Reserved 16 PROCHOT Log When set, indicates that the PROCHOT Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 17 Thermal Log When set, indicates that the Thermal Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 19:18 Reserved. 20 Graphics Driver Log When set, indicates that the Graphics Driver Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. Vol. 4 2-221 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 21 Autonomous Utilization-Based Frequency Control Log When set, indicates that the Autonomous UtilizationBased Frequency Control Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 22 VR Therm Alert Log When set, indicates that the VR Therm Alert Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 23 Reserved 24 Electrical Design Point Log When set, indicates that the EDP Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 25 Core Power Limiting Log When set, indicates that the Core Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 26 Package-Level PL1 Power Limiting Log When set, indicates that the Package Level PL1 Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 27 Package-Level PL2 Power Limiting Log When set, indicates that the Package Level PL2 Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 28 Max Turbo Limit Log When set, indicates that the Max Turbo Limit Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 2-222 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 29 Turbo Transition Attenuation Log When set, indicates that the Turbo Transition Attenuation Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 63:30 Reserved 700H 1792 MSR_UNC_CBO_0_PERFEVTSEL0 Package Uncore C-Box 0, Counter 0 Event Select MSR 701H 1793 MSR_UNC_CBO_0_PERFEVTSEL1 Package Uncore C-Box 0, Counter 1 Event Select MSR 706H 1798 MSR_UNC_CBO_0_PERFCTR0 Package Uncore C-Box 0, Performance Counter 0 707H 1799 MSR_UNC_CBO_0_PERFCTR1 Package Uncore C-Box 0, Performance Counter 1 710H 1808 MSR_UNC_CBO_1_PERFEVTSEL0 Package Uncore C-Box 1, Counter 0 Event Select MSR 711H 1809 MSR_UNC_CBO_1_PERFEVTSEL1 Package Uncore C-Box 1, Counter 1 Event Select MSR 716H 1814 MSR_UNC_CBO_1_PERFCTR0 Package Uncore C-Box 1, Performance Counter 0 717H 1815 MSR_UNC_CBO_1_PERFCTR1 Package Uncore C-Box 1, Performance Counter 1 720H 1824 MSR_UNC_CBO_2_PERFEVTSEL0 Package Uncore C-Box 2, Counter 0 Event Select MSR 721H 1824 MSR_UNC_CBO_2_PERFEVTSEL1 Package Uncore C-Box 2, Counter 1 Event Select MSR 726H 1830 MSR_UNC_CBO_2_PERFCTR0 Package Uncore C-Box 2, Performance Counter 0 727H 1831 MSR_UNC_CBO_2_PERFCTR1 Package Uncore C-Box 2, Performance Counter 1 730H 1840 MSR_UNC_CBO_3_PERFEVTSEL0 Package Uncore C-Box 3, Counter 0 Event Select MSR 731H 1841 MSR_UNC_CBO_3_PERFEVTSEL1 Package Uncore C-Box 3, Counter 1 Event Select MSR 736H 1846 MSR_UNC_CBO_3_PERFCTR0 Package Uncore C-Box 3, Performance Counter 0 737H 1847 MSR_UNC_CBO_3_PERFCTR1 Package Uncore C-Box 3, Performance Counter 1 See Table 2-20, Table 2-21, Table 2-22, Table 2-25, Table 2-29 for other MSR definitions applicable to processors with CPUID signatures 063CH, 06_46H. 2.13.2 Additional Residency MSRs Supported in 4th Generation Intel® Core™ Processors The 4th generation Intel® Core™ processor family (based on Haswell microarchitecture) with CPUID DisplayFamily_DisplayModel signature 06_45H supports the MSR interfaces listed in Table 2-20, Table 2-21, Table 2-29, Table 2-30, and Table 2-31. Vol. 4 2-223 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-31. Additional Residency MSRs Supported by 4th Generation Intel® Core™ Processors with DisplayFamily_DisplayModel Signature 06_45H Register Address Hex Dec E2H 226 Register Name / Bit Fields MSR_PKG_CST_CONFIG_CONTROL Scope Core Bit Description C-State Configuration Control (R/W) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-states. See http://biosbits.org. 3:0 Package C-State Limit (R/W) Specifies the lowest processor-specific C-state code name (consuming the least power) for the package. The default is set as factory-configured package C-state limit. The following C-state code name encodings are supported: 0000b: C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6 0100b: C7 0101b: C7s 0110b: C8 0111b: C9 1000b: C10 630H 1584 9:4 Reserved 10 I/O MWAIT Redirection Enable (R/W) 14:11 Reserved 15 CFG Lock (R/WO) 24:16 Reserved 25 C3 State Auto Demotion Enable (R/W) 26 C1 State Auto Demotion Enable (R/W) 27 Enable C3 Undemotion (R/W) 28 Enable C1 Undemotion (R/W) 63:29 Reserved MSR_PKG_C8_RESIDENCY 59:0 Package Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C8 Residency Counter (R/O) Value since last reset that this package is in processorspecific C8 states. Count at the same frequency as the TSC. 63:60 2-224 Vol. 4 Reserved MODEL-SPECIFIC REGISTERS (MSRS) Table 2-31. Additional Residency MSRs Supported by 4th Generation Intel® Core™ Processors with DisplayFamily_DisplayModel Signature 06_45H Register Address Hex Dec 631H 1585 Register Name / Bit Fields MSR_PKG_C9_RESIDENCY Scope Package 59:0 Bit Description Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C9 Residency Counter (R/O) Value since last reset that this package is in processorspecific C9 states. Count at the same frequency as the TSC. 63:60 632H 1586 MSR_PKG_C10_RESIDENCY Reserved Package 59:0 Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C10 Residency Counter (R/O) Value since last reset that this package is in processorspecific C10 states. Count at the same frequency as the TSC. 63:60 Reserved See Table 2-20, Table 2-21, Table 2-22, Table 2-29, Table 2-30 for other MSR definitions applicable to processors with CPUID signature 06_45H. 2.14 MSRS IN INTEL® XEON® PROCESSOR E5 V3 AND E7 V3 PRODUCT FAMILY Intel® Xeon® processor E5 v3 family and Intel® Xeon® processor E7 v3 family are based on Haswell-E microarchitecture (CPUID DisplayFamily_DisplayModel = 06_3F). These processors supports the MSR interfaces listed in Table 2-20, Table 2-29, and Table 2-32. Table 2-32. Additional MSRs Supported by Intel® Xeon® Processor E5 v3 Family Register Address Hex Dec 35H 53 Register Name / Bit Fields MSR_CORE_THREAD_COUNT Scope Package Bit Description Configured State of Enabled Processor Core Count and Logical Processor Count (RO) • After a Power-On RESET, enumerates factory configuration of the number of processor cores and logical processors in the physical package. • Following the sequence of (i) BIOS modified a Configuration Mask which selects a subset of processor cores to be active post RESET and (ii) a RESET event after the modification, enumerates the current configuration of enabled processor core count and logical processor count in the physical package. 15:0 Core_COUNT (RO) The number of processor cores that are currently enabled (by either factory configuration or BIOS configuration) in the physical package. Vol. 4 2-225 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-32. Additional MSRs Supported by Intel® Xeon® Processor E5 v3 Family Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 31:16 THREAD_COUNT (RO) The number of logical processors that are currently enabled (by either factory configuration or BIOS configuration) in the physical package. 63:32 53H 83 MSR_THREAD_ID_INFO Reserved Thread 7:0 A Hardware Assigned ID for the Logical Processor (RO) Logical_Processor_ID (RO) An implementation-specific numerical value physically assigned to each logical processor. This ID is not related to Initial APIC ID or x2APIC ID, it is unique within a physical package. 63:8 E2H 226 MSR_PKG_CST_CONFIG_CONTROL Reserved Core C-State Configuration Control (R/W) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-states. See http://biosbits.org. 2:0 Package C-State Limit (R/W) Specifies the lowest processor-specific C-state code name (consuming the least power) for the package. The default is set as factory-configured package C-state limit. The following C-state code name encodings are supported: 000b: C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention) 011b: C6 (retention) 111b: No Package C state limits. All C states supported by the processor are available. 2-226 Vol. 4 9:3 Reserved 10 I/O MWAIT Redirection Enable (R/W) 14:11 Reserved 15 CFG Lock (R/WO) 24:16 Reserved 25 C3 State Auto Demotion Enable (R/W) 26 C1 State Auto Demotion Enable (R/W) 27 Enable C3 Undemotion (R/W) 28 Enable C1 Undemotion (R/W) 29 Package C State Demotion Enable (R/W) 30 Package C State UnDemotion Enable (R/W) 63:31 Reserved MODEL-SPECIFIC REGISTERS (MSRS) Table 2-32. Additional MSRs Supported by Intel® Xeon® Processor E5 v3 Family Register Address Hex Dec 179H 377 17DH 390 Register Name / Bit Fields IA32_MCG_CAP Scope Thread Bit Description Global Machine Check Capability (R/O) 7:0 Count 8 MCG_CTL_P 9 MCG_EXT_P 10 MCP_CMCI_P 11 MCG_TES_P 15:12 Reserved 23:16 MCG_EXT_CNT 24 MCG_SER_P 25 MCG_EM_P 26 MCG_ELOG_P 63:27 Reserved MSR_SMM_MCA_CAP Thread Enhanced SMM Capabilities (SMM-RO) Reports SMM capability Enhancement. Accessible only while in SMM. 57:0 Reserved 58 SMM_Code_Access_Chk (SMM-RO) If set to 1, indicates that the SMM code access restriction is supported and a host-space interface available to SMM handler. 59 Long_Flow_Indication (SMM-RO) If set to 1, indicates that the SMM long flow indicator is supported and a host-space interface available to SMM handler. 63:60 17FH 383 MSR_ERROR_CONTROL Reserved Package 0 MC Bank Error Configuration (R/W) Reserved 1 MemError Log Enable (R/W) When set, enables IMC status bank to log additional info in bits 36:32. 63:2 1ADH 429 MSR_TURBO_RATIO_LIMIT Reserved Package Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0. RW if MSR_PLATFORM_INFO.[28] = 1. 7:0 Package Maximum Ratio Limit for 1C Maximum turbo ratio limit of 1 core active. 15:8 Package Maximum Ratio Limit for 2C Maximum turbo ratio limit of 2 core active. 23:16 Package Maximum Ratio Limit for 3C Maximum turbo ratio limit of 3 core active. Vol. 4 2-227 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-32. Additional MSRs Supported by Intel® Xeon® Processor E5 v3 Family Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 31:24 Package Maximum Ratio Limit for 4C Maximum turbo ratio limit of 4 core active. 39:32 Package Maximum Ratio Limit for 5C Maximum turbo ratio limit of 5 core active. 47:40 Package Maximum Ratio Limit for 6C Maximum turbo ratio limit of 6 core active. 55:48 Package Maximum Ratio Limit for 7C Maximum turbo ratio limit of 7 core active. 63:56 Package Maximum Ratio Limit for 8C Maximum turbo ratio limit of 8 core active. 1AEH 430 MSR_TURBO_RATIO_LIMIT1 Package Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0. RW if MSR_PLATFORM_INFO.[28] = 1. 7:0 Package Maximum Ratio Limit for 9C Maximum turbo ratio limit of 9 core active. 15:8 Package Maximum Ratio Limit for 10C Maximum turbo ratio limit of 10 core active. 23:16 Package Maximum Ratio Limit for 11C Maximum turbo ratio limit of 11 core active. 31:24 Package Maximum Ratio Limit for 12C Maximum turbo ratio limit of 12 core active. 39:32 Package Maximum Ratio Limit for 13C Maximum turbo ratio limit of 13 core active. 47:40 Package Maximum Ratio Limit for 14C Maximum turbo ratio limit of 14 core active. 55:48 Package Maximum Ratio Limit for 15C Maximum turbo ratio limit of 15 core active. 63:56 Package Maximum Ratio Limit for16C Maximum turbo ratio limit of 16 core active. 1AFH 431 MSR_TURBO_RATIO_LIMIT2 Package Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0. RW if MSR_PLATFORM_INFO.[28] = 1. 7:0 Package Maximum Ratio Limit for 17C Maximum turbo ratio limit of 17 core active. 15:8 Package Maximum Ratio Limit for 18C Maximum turbo ratio limit of 18 core active. 62:16 2-228 Vol. 4 Package Reserved MODEL-SPECIFIC REGISTERS (MSRS) Table 2-32. Additional MSRs Supported by Intel® Xeon® Processor E5 v3 Family Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 63 Package Semaphore for Turbo Ratio Limit Configuration If 1, the processor uses override configuration1 specified in MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1 and MSR_TURBO_RATIO_LIMIT2. If 0, the processor uses factory-set configuration (Default). 414H 1044 IA32_MC5_CTL Package 415H 1045 IA32_MC5_STATUS Package 416H 1046 IA32_MC5_ADDR Package 417H 1047 IA32_MC5_MISC Package 418H 1048 IA32_MC6_CTL Package 419H 1049 IA32_MC6_STATUS Package 41AH 1050 IA32_MC6_ADDR Package 41BH 1051 IA32_MC6_MISC Package 41CH 1052 IA32_MC7_CTL Package 41DH 1053 IA32_MC7_STATUS Package 41EH 1054 IA32_MC7_ADDR Package 41FH 1055 IA32_MC7_MISC Package 420H 1056 IA32_MC8_CTL Package 421H 1057 IA32_MC8_STATUS Package 422H 1058 IA32_MC8_ADDR Package 423H 1059 IA32_MC8_MISC Package 424H 1060 IA32_MC9_CTL Package 425H 1061 IA32_MC9_STATUS Package 426H 1062 IA32_MC9_ADDR Package 427H 1063 IA32_MC9_MISC Package 428H 1064 IA32_MC10_CTL Package 429H 1065 IA32_MC10_STATUS Package 42AH 1066 IA32_MC10_ADDR Package 42BH 1067 IA32_MC10_MISC Package 42CH 1068 IA32_MC11_CTL Package 42DH 1069 IA32_MC11_STATUS Package 42EH 1070 IA32_MC11_ADDR Package 42FH 1071 IA32_MC11_MISC Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC5 reports MC errors from the Intel QPI 0 module. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC6 reports MC errors from the integrated I/O module. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC7 reports MC errors from the home agent HA 0. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC8 reports MC errors from the home agent HA 1. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers. Vol. 4 2-229 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-32. Additional MSRs Supported by Intel® Xeon® Processor E5 v3 Family Register Address Register Name / Bit Fields Scope Hex Dec 430H 1072 IA32_MC12_CTL Package 431H 1073 IA32_MC12_STATUS Package 432H 1074 IA32_MC12_ADDR Package 433H 1075 IA32_MC12_MISC Package 434H 1076 IA32_MC13_CTL Package 435H 1077 IA32_MC13_STATUS Package 436H 1078 IA32_MC13_ADDR Package 437H 1079 IA32_MC13_MISC Package 438H 1080 IA32_MC14_CTL Package 439H 1081 IA32_MC14_STATUS Package 43AH 1082 IA32_MC14_ADDR Package 43BH 1083 IA32_MC14_MISC Package 43CH 1084 IA32_MC15_CTL Package 43DH 1085 IA32_MC15_STATUS Package 43EH 1086 IA32_MC15_ADDR Package 43FH 1087 IA32_MC15_MISC Package 440H 1088 IA32_MC16_CTL Package 441H 1089 IA32_MC16_STATUS Package 442H 1090 IA32_MC16_ADDR Package 443H 1091 IA32_MC16_MISC Package 444H 1092 IA32_MC17_CTL Package 445H 1093 IA32_MC17_STATUS Package 446H 1094 IA32_MC17_ADDR Package 447H 1095 IA32_MC17_MISC Package 448H 1096 IA32_MC18_CTL Package 449H 1097 IA32_MC18_STATUS Package 44AH 1098 IA32_MC18_ADDR Package 44BH 1099 IA32_MC18_MISC Package 44CH 1100 IA32_MC19_CTL Package 44DH 1101 IA32_MC19_STATUS Package 44EH 1102 IA32_MC19_ADDR Package 44FH 1103 IA32_MC19_MISC Package 450H 1104 IA32_MC20_CTL Package 451H 1105 IA32_MC20_STATUS Package 452H 1106 IA32_MC20_ADDR Package 453H 1107 IA32_MC20_MISC Package 2-230 Vol. 4 Bit Description See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC17 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9, CBo12, CBo15. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC18 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7, CBo10, CBo13, CBo16. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC19 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8, CBo11, CBo14, CBo17. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC20 reports MC errors from the Intel QPI 1 module. MODEL-SPECIFIC REGISTERS (MSRS) Table 2-32. Additional MSRs Supported by Intel® Xeon® Processor E5 v3 Family Register Address Register Name / Bit Fields Scope Bit Description Hex Dec 454H 1108 IA32_MC21_CTL Package 455H 1109 IA32_MC21_STATUS Package 456H 1110 IA32_MC21_ADDR Package 457H 1111 IA32_MC21_MISC Package 606H 1542 MSR_RAPL_POWER_UNIT Package Unit Multipliers Used in RAPL Interfaces (R/O) 3:0 Package Power Units See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC21 reports MC errors from the Intel QPI 2 module. See Section 14.9.1, “RAPL Interfaces.” 7:4 Package Reserved 12:8 Package Energy Status Units Energy related information (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an unsigned integer represented by bits 12:8. Default value is 0EH (or 61 micro-joules). 15:13 Package Reserved 19:16 Package Time Units See Section 14.9.1, “RAPL Interfaces.” 63:20 618H 1560 MSR_DRAM_POWER_LIMIT Reserved Package DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, “DRAM RAPL Domain.” 619H 1561 MSR_DRAM_ENERGY_STATUS Package DRAM Energy Status (R/O) Energy Consumed by DRAM devices. 61BH 1563 31:0 Energy in 15.3 micro-joules. Requires BIOS configuration to enable DRAM RAPL mode 0 (Direct VR). 63:32 Reserved MSR_DRAM_PERF_STATUS Package DRAM Performance Throttling Status (R/O) See Section 14.9.5, “DRAM RAPL Domain.” 61CH 1564 MSR_DRAM_POWER_INFO Package DRAM RAPL Parameters (R/W) See Section 14.9.5, “DRAM RAPL Domain.” 61EH 1566 MSR_PCIE_PLL_RATIO Package 1:0 Package Configuration of PCIE PLL Relative to BCLK(R/W) PCIE Ratio (R/W) 00b: Use 5:5 mapping for100MHz operation (default). 01b: Use 5:4 mapping for125MHz operation. 10b: Use 5:3 mapping for166MHz operation. 11b: Use 5:2 mapping for250MHz operation. 2 Package LPLL Select (R/W) If 1, use configured setting of PCIE Ratio. 3 Package LONG RESET (R/W) If 1, wait an additional time-out before re-locking Gen2/Gen3 PLLs. 63:4 Reserved Vol. 4 2-231 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-32. Additional MSRs Supported by Intel® Xeon® Processor E5 v3 Family Register Address Hex Dec 620H 1568 Register Name / Bit Fields MSR UNCORE_RATIO_LIMIT Scope Package Bit Description Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio fields represent the widest possible range of uncore frequencies. Writing to these fields allows software to control the minimum and the maximum frequency that hardware will select. 63:15 Reserved 14:8 MIN_RATIO Writing to this field controls the minimum possible ratio of the LLC/Ring. 7 Reserved 6:0 MAX_RATIO This field is used to limit the max ratio of the LLC/Ring. 639H 1593 MSR_PP0_ENERGY_STATUS Package Reserved (R/O) Reads return 0. 690H 1680 MSR_CORE_PERF_LIMIT_REASONS Package Indicator of Frequency Clipping in Processor Cores (R/W) (Frequency refers to processor core frequency.) 0 PROCHOT Status (R0) When set, processor core frequency is reduced below the operating system request due to assertion of external PROCHOT. 1 Thermal Status (R0) When set, frequency is reduced below the operating system request due to a thermal event. 2 Power Budget Management Status (R0) When set, frequency is reduced below the operating system request due to PBM limit 3 Platform Configuration Services Status (R0) When set, frequency is reduced below the operating system request due to PCS limit 4 Reserved 5 Autonomous Utilization-Based Frequency Control Status (R0) When set, frequency is reduced below the operating system request because the processor has detected that utilization is low. 6 VR Therm Alert Status (R0) When set, frequency is reduced below the operating system request due to a thermal alert from the Voltage Regulator. 7 2-232 Vol. 4 Reserved MODEL-SPECIFIC REGISTERS (MSRS) Table 2-32. Additional MSRs Supported by Intel® Xeon® Processor E5 v3 Family Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 8 Electrical Design Point Status (R0) When set, frequency is reduced below the operating system request due to electrical design point constraints (e.g., maximum electrical current consumption). 9 Reserved 10 Multi-Core Turbo Status (R0) When set, frequency is reduced below the operating system request due to Multi-Core Turbo limits. 12:11 Reserved 13 Core Frequency P1 Status (R0) When set, frequency is reduced below max non-turbo P1. 14 Core Max N-Core Turbo Frequency Limiting Status (R0) When set, frequency is reduced below max n-core turbo frequency. 15 Core Frequency Limiting Status (R0) When set, frequency is reduced below the operating system request. 16 PROCHOT Log When set, indicates that the PROCHOT Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 17 Thermal Log When set, indicates that the Thermal Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 18 Power Budget Management Log When set, indicates that the PBM Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 19 Platform Configuration Services Log When set, indicates that the PCS Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 20 Reserved Vol. 4 2-233 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-32. Additional MSRs Supported by Intel® Xeon® Processor E5 v3 Family Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 21 Autonomous Utilization-Based Frequency Control Log When set, indicates that the AUBFC Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 22 VR Therm Alert Log When set, indicates that the VR Therm Alert Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 23 Reserved 24 Electrical Design Point Log When set, indicates that the EDP Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 25 Reserved 26 Multi-Core Turbo Log When set, indicates that the Multi-Core Turbo Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 28:27 Reserved 29 Core Frequency P1 Log When set, indicates that the Core Frequency P1 Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 30 Core Max N-Core Turbo Frequency Limiting Log When set, indicates that the Core Max n-core Turbo Frequency Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 31 Core Frequency Limiting Log When set, indicates that the Core Frequency Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 63:32 C8DH 3213 IA32_QM_EVTSEL Reserved THREAD Monitoring Event Select Register (R/W) If CPUID.(EAX=07H, ECX=0):EBX.RDT-M[bit 12] = 1. 2-234 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-32. Additional MSRs Supported by Intel® Xeon® Processor E5 v3 Family Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 7:0 EventID (RW) Event encoding: 0x0: No monitoring. 0x1: L3 occupancy monitoring. All other encoding reserved. C8EH 3214 31:8 Reserved 41:32 RMID (RW) 63:42 Reserved IA32_QM_CTR THREAD Monitoring Counter Register (R/O) If CPUID.(EAX=07H, ECX=0):EBX.RDT-M[bit 12] = 1. C8FH 3215 61:0 Resource Monitored Data 62 Unavailable: If 1, indicates data for this RMID is not available or not monitored for this resource or RMID. 63 Error: If 1, indicates and unsupported RMID or event type was written to IA32_PQR_QM_EVTSEL. IA32_PQR_ASSOC THREAD Resource Association Register (R/W) 9:0 RMID 63: 10 Reserved See Table 2-20, Table 2-29 for other MSR definitions applicable to processors with CPUID signature 06_3FH. NOTES: 1. An override configuration lower than the factory-set configuration is always supported. An override configuration higher than the factory-set configuration is dependent on features specific to the processor and the platform. Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family 2.14.1 Intel Xeon Processor E5 v3 and E7 v3 family are based on the Haswell-E microarchitecture. The MSR-based uncore PMU interfaces are listed in Table 2-33. For complete detail of the uncore PMU, refer to Intel Xeon Processor E5 v3 Product Family Uncore Performance Monitoring Guide. These processors have a CPUID signature with DisplayFamily_DisplayModel of 06_3FH. Table 2-33. Uncore PMU MSRs in Intel® Xeon® Processor E5 v3 Family Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 700H MSR_PMON_GLOBAL_CTL Package Uncore Perfmon Per-Socket Global Control 701H MSR_PMON_GLOBAL_STATUS Package Uncore Perfmon Per-Socket Global Status 702H MSR_PMON_GLOBAL_CONFIG Package Uncore Perfmon Per-Socket Global Configuration 703H MSR_U_PMON_UCLK_FIXED_CTL Package Uncore U-Box UCLK Fixed Counter Control 704H MSR_U_PMON_UCLK_FIXED_CTR Package Uncore U-Box UCLK Fixed Counter 705H MSR_U_PMON_EVNTSEL0 Package Uncore U-Box Perfmon Event Select for U-Box Counter 0 Vol. 4 2-235 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-33. Uncore PMU MSRs in Intel® Xeon® Processor E5 v3 Family (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 706H MSR_U_PMON_EVNTSEL1 Package Uncore U-Box Perfmon Event Select for U-Box Counter 1 708H MSR_U_PMON_BOX_STATUS Package Uncore U-Box Perfmon U-Box Wide Status 709H MSR_U_PMON_CTR0 Package Uncore U-Box Perfmon Counter 0 70AH MSR_U_PMON_CTR1 Package Uncore U-Box Perfmon Counter 1 710H MSR_PCU_PMON_BOX_CTL Package Uncore PCU Perfmon for PCU-Box-Wide Control 711H MSR_PCU_PMON_EVNTSEL0 Package Uncore PCU Perfmon Event Select for PCU Counter 0 712H MSR_PCU_PMON_EVNTSEL1 Package Uncore PCU Perfmon Event Select for PCU Counter 1 713H MSR_PCU_PMON_EVNTSEL2 Package Uncore PCU Perfmon Event Select for PCU Counter 2 714H MSR_PCU_PMON_EVNTSEL3 Package Uncore PCU Perfmon Event Select for PCU Counter 3 715H MSR_PCU_PMON_BOX_FILTER Package Uncore PCU Perfmon Box-Wide Filter 716H MSR_PCU_PMON_BOX_STATUS Package Uncore PCU Perfmon Box Wide Status 717H MSR_PCU_PMON_CTR0 Package Uncore PCU Perfmon Counter 0 718H MSR_PCU_PMON_CTR1 Package Uncore PCU Perfmon Counter 1 719H MSR_PCU_PMON_CTR2 Package Uncore PCU Perfmon Counter 2 71AH MSR_PCU_PMON_CTR3 Package Uncore PCU Perfmon Counter 3 720H MSR_S0_PMON_BOX_CTL Package Uncore SBo 0 Perfmon for SBo 0 Box-Wide Control 721H MSR_S0_PMON_EVNTSEL0 Package Uncore SBo 0 Perfmon Event Select for SBo 0 Counter 0 722H MSR_S0_PMON_EVNTSEL1 Package Uncore SBo 0 Perfmon Event Select for SBo 0 Counter 1 723H MSR_S0_PMON_EVNTSEL2 Package Uncore SBo 0 Perfmon Event Select for SBo 0 Counter 2 724H MSR_S0_PMON_EVNTSEL3 Package Uncore SBo 0 Perfmon Event Select for SBo 0 Counter 3 725H MSR_S0_PMON_BOX_FILTER Package Uncore SBo 0 Perfmon Box-Wide Filter 726H MSR_S0_PMON_CTR0 Package Uncore SBo 0 Perfmon Counter 0 727H MSR_S0_PMON_CTR1 Package Uncore SBo 0 Perfmon Counter 1 728H MSR_S0_PMON_CTR2 Package Uncore SBo 0 Perfmon Counter 2 729H MSR_S0_PMON_CTR3 Package Uncore SBo 0 Perfmon Counter 3 72AH MSR_S1_PMON_BOX_CTL Package Uncore SBo 1 Perfmon for SBo 1 Box-Wide Control 72BH MSR_S1_PMON_EVNTSEL0 Package Uncore SBo 1 Perfmon Event Select for SBo 1 Counter 0 72CH MSR_S1_PMON_EVNTSEL1 Package Uncore SBo 1 Perfmon Event Select for SBo 1 Counter 1 72DH MSR_S1_PMON_EVNTSEL2 Package Uncore SBo 1 Perfmon Event Select for SBo 1 Counter 2 72EH MSR_S1_PMON_EVNTSEL3 Package Uncore SBo 1 Perfmon Event Select for SBo 1 Counter 3 72FH MSR_S1_PMON_BOX_FILTER Package Uncore SBo 1 Perfmon Box-Wide Filter 2-236 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-33. Uncore PMU MSRs in Intel® Xeon® Processor E5 v3 Family (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 730H MSR_S1_PMON_CTR0 Package Uncore SBo 1 Perfmon Counter 0 731H MSR_S1_PMON_CTR1 Package Uncore SBo 1 Perfmon Counter 1 732H MSR_S1_PMON_CTR2 Package Uncore SBo 1 Perfmon Counter 2 733H MSR_S1_PMON_CTR3 Package Uncore SBo 1 Perfmon Counter 3 734H MSR_S2_PMON_BOX_CTL Package Uncore SBo 2 Perfmon for SBo 2 Box-Wide Control 735H MSR_S2_PMON_EVNTSEL0 Package Uncore SBo 2 Perfmon Event Select for SBo 2 Counter 0 736H MSR_S2_PMON_EVNTSEL1 Package Uncore SBo 2 Perfmon Event Select for SBo 2 Counter 1 737H MSR_S2_PMON_EVNTSEL2 Package Uncore SBo 2 Perfmon Event Select for SBo 2 Counter 2 738H MSR_S2_PMON_EVNTSEL3 Package Uncore SBo 2 Perfmon Event Select for SBo 2 Counter 3 739H MSR_S2_PMON_BOX_FILTER Package Uncore SBo 2 Perfmon Box-Wide Filter 73AH MSR_S2_PMON_CTR0 Package Uncore SBo 2 Perfmon Counter 0 73BH MSR_S2_PMON_CTR1 Package Uncore SBo 2 Perfmon Counter 1 73CH MSR_S2_PMON_CTR2 Package Uncore SBo 2 Perfmon Counter 2 73DH MSR_S2_PMON_CTR3 Package Uncore SBo 2 Perfmon Counter 3 73EH MSR_S3_PMON_BOX_CTL Package Uncore SBo 3 Perfmon for SBo 3 Box-Wide Control 73FH MSR_S3_PMON_EVNTSEL0 Package Uncore SBo 3 Perfmon Event Select for SBo 3 Counter 0 740H MSR_S3_PMON_EVNTSEL1 Package Uncore SBo 3 Perfmon Event Select for SBo 3 Counter 1 741H MSR_S3_PMON_EVNTSEL2 Package Uncore SBo 3 Perfmon Event Select for SBo 3 Counter 2 742H MSR_S3_PMON_EVNTSEL3 Package Uncore SBo 3 Perfmon Event Select for SBo 3 Counter 3 743H MSR_S3_PMON_BOX_FILTER Package Uncore SBo 3 Perfmon Box-Wide Filter 744H MSR_S3_PMON_CTR0 Package Uncore SBo 3 Perfmon Counter 0 745H MSR_S3_PMON_CTR1 Package Uncore SBo 3 Perfmon Counter 1 746H MSR_S3_PMON_CTR2 Package Uncore SBo 3 Perfmon Counter 2 747H MSR_S3_PMON_CTR3 Package Uncore SBo 3 Perfmon Counter 3 E00H MSR_C0_PMON_BOX_CTL Package Uncore C-Box 0 Perfmon for Box-Wide Control E01H MSR_C0_PMON_EVNTSEL0 Package Uncore C-Box 0 Perfmon Event Select for C-Box 0 Counter 0 E02H MSR_C0_PMON_EVNTSEL1 Package Uncore C-Box 0 Perfmon Event Select for C-Box 0 Counter 1 E03H MSR_C0_PMON_EVNTSEL2 Package Uncore C-Box 0 Perfmon Event Select for C-Box 0 Counter 2 E04H MSR_C0_PMON_EVNTSEL3 Package Uncore C-Box 0 Perfmon Event Select for C-Box 0 Counter 3 Vol. 4 2-237 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-33. Uncore PMU MSRs in Intel® Xeon® Processor E5 v3 Family (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec E05H MSR_C0_PMON_BOX_FILTER0 Package Uncore C-Box 0 Perfmon Box Wide Filter 0 E06H MSR_C0_PMON_BOX_FILTER1 Package Uncore C-Box 0 Perfmon Box Wide Filter 1 E07H MSR_C0_PMON_BOX_STATUS Package Uncore C-Box 0 Perfmon Box Wide Status E08H MSR_C0_PMON_CTR0 Package Uncore C-Box 0 Perfmon Counter 0 E09H MSR_C0_PMON_CTR1 Package Uncore C-Box 0 Perfmon Counter 1 E0AH MSR_C0_PMON_CTR2 Package Uncore C-Box 0 Perfmon Counter 2 E0BH MSR_C0_PMON_CTR3 Package Uncore C-Box 0 Perfmon Counter 3 E10H MSR_C1_PMON_BOX_CTL Package Uncore C-Box 1 Perfmon for Box-Wide Control E11H MSR_C1_PMON_EVNTSEL0 Package Uncore C-Box 1 Perfmon Event Select for C-Box 1 Counter 0 E12H MSR_C1_PMON_EVNTSEL1 Package Uncore C-Box 1 Perfmon Event Select for C-Box 1 Counter 1 E13H MSR_C1_PMON_EVNTSEL2 Package Uncore C-Box 1 Perfmon Event Select for C-Box 1 Counter 2 E14H MSR_C1_PMON_EVNTSEL3 Package Uncore C-Box 1 Perfmon Event Select for C-Box 1 Counter 3 E15H MSR_C1_PMON_BOX_FILTER0 Package Uncore C-Box 1 Perfmon Box Wide Filter 0 E16H MSR_C1_PMON_BOX_FILTER1 Package Uncore C-Box 1 Perfmon Box Wide Filter1 E17H MSR_C1_PMON_BOX_STATUS Package Uncore C-Box 1 Perfmon Box Wide Status E18H MSR_C1_PMON_CTR0 Package Uncore C-Box 1 Perfmon Counter 0 E19H MSR_C1_PMON_CTR1 Package Uncore C-Box 1 Perfmon Counter 1 E1AH MSR_C1_PMON_CTR2 Package Uncore C-Box 1 Perfmon Counter 2 E1BH MSR_C1_PMON_CTR3 Package Uncore C-Box 1 Perfmon Counter 3 E20H MSR_C2_PMON_BOX_CTL Package Uncore C-Box 2 Perfmon for Box-Wide Control E21H MSR_C2_PMON_EVNTSEL0 Package Uncore C-Box 2 Perfmon Event Select for C-Box 2 Counter 0 E22H MSR_C2_PMON_EVNTSEL1 Package Uncore C-Box 2 Perfmon Event Select for C-Box 2 Counter 1 E23H MSR_C2_PMON_EVNTSEL2 Package Uncore C-Box 2 Perfmon Event Select for C-Box 2 Counter 2 E24H MSR_C2_PMON_EVNTSEL3 Package Uncore C-Box 2 Perfmon Event select for C-Box 2 Counter 3 E25H MSR_C2_PMON_BOX_FILTER0 Package Uncore C-Box 2 Perfmon Box Wide Filter 0 E26H MSR_C2_PMON_BOX_FILTER1 Package Uncore C-Box 2 Perfmon Box Wide Filter1 E27H MSR_C2_PMON_BOX_STATUS Package Uncore C-Box 2 Perfmon Box Wide Status E28H MSR_C2_PMON_CTR0 Package Uncore C-Box 2 Perfmon Counter 0 E29H MSR_C2_PMON_CTR1 Package Uncore C-Box 2 Perfmon Counter 1 E2AH MSR_C2_PMON_CTR2 Package Uncore C-Box 2 Perfmon Counter 2 E2BH MSR_C2_PMON_CTR3 Package Uncore C-Box 2 Perfmon Counter 3 2-238 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-33. Uncore PMU MSRs in Intel® Xeon® Processor E5 v3 Family (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec E30H MSR_C3_PMON_BOX_CTL Package Uncore C-Box 3 Perfmon for Box-Wide Control E31H MSR_C3_PMON_EVNTSEL0 Package Uncore C-Box 3 Perfmon Event Select for C-Box 3 Counter 0 E32H MSR_C3_PMON_EVNTSEL1 Package Uncore C-Box 3 Perfmon Event Select for C-Box 3 Counter 1 E33H MSR_C3_PMON_EVNTSEL2 Package Uncore C-Box 3 Perfmon Event Select for C-Box 3 Counter 2 E34H MSR_C3_PMON_EVNTSEL3 Package Uncore C-Box 3 Perfmon Event Select for C-Box 3 Counter 3 E35H MSR_C3_PMON_BOX_FILTER0 Package Uncore C-Box 3 Perfmon Box Wide Filter 0 E36H MSR_C3_PMON_BOX_FILTER1 Package Uncore C-Box 3 Perfmon Box Wide Filter1 E37H MSR_C3_PMON_BOX_STATUS Package Uncore C-Box 3 Perfmon Box Wide Status E38H MSR_C3_PMON_CTR0 Package Uncore C-Box 3 Perfmon Counter 0 E39H MSR_C3_PMON_CTR1 Package Uncore C-Box 3 Perfmon Counter 1 E3AH MSR_C3_PMON_CTR2 Package Uncore C-Box 3 Perfmon Counter 2 E3BH MSR_C3_PMON_CTR3 Package Uncore C-Box 3 Perfmon Counter 3 E40H MSR_C4_PMON_BOX_CTL Package Uncore C-Box 4 Perfmon for Box-Wide Control E41H MSR_C4_PMON_EVNTSEL0 Package Uncore C-Box 4 Perfmon Event Select for C-Box 4 Counter 0 E42H MSR_C4_PMON_EVNTSEL1 Package Uncore C-Box 4 Perfmon Event Select for C-Box 4 Counter 1 E43H MSR_C4_PMON_EVNTSEL2 Package Uncore C-Box 4 Perfmon Event Select for C-Box 4 Counter 2 E44H MSR_C4_PMON_EVNTSEL3 Package Uncore C-Box 4 Perfmon Event Select for C-Box 4 Counter 3 E45H MSR_C4_PMON_BOX_FILTER0 Package Uncore C-Box 4 Perfmon Box Wide Filter 0 E46H MSR_C4_PMON_BOX_FILTER1 Package Uncore C-Box 4 Perfmon Box Wide Filter1 E47H MSR_C4_PMON_BOX_STATUS Package Uncore C-Box 4 Perfmon Box Wide Status E48H MSR_C4_PMON_CTR0 Package Uncore C-Box 4 Perfmon Counter 0 E49H MSR_C4_PMON_CTR1 Package Uncore C-Box 4 Perfmon Counter 1 E4AH MSR_C4_PMON_CTR2 Package Uncore C-Box 4 Perfmon Counter 2 E4BH MSR_C4_PMON_CTR3 Package Uncore C-Box 4 Perfmon Counter 3 E50H MSR_C5_PMON_BOX_CTL Package Uncore C-Box 5 Perfmon for Box-Wide Control E51H MSR_C5_PMON_EVNTSEL0 Package Uncore C-Box 5 Perfmon Event Select for C-Box 5 Counter 0 E52H MSR_C5_PMON_EVNTSEL1 Package Uncore C-Box 5 Perfmon Event Select for C-Box 5 Counter 1 E53H MSR_C5_PMON_EVNTSEL2 Package Uncore C-Box 5 Perfmon Event Select for C-Box 5 Counter 2 E54H MSR_C5_PMON_EVNTSEL3 Package Uncore C-Box 5 Perfmon Event Select for C-Box 5 Counter 3 Vol. 4 2-239 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-33. Uncore PMU MSRs in Intel® Xeon® Processor E5 v3 Family (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec E55H MSR_C5_PMON_BOX_FILTER0 Package Uncore C-Box 5 Perfmon Box Wide Filter 0 E56H MSR_C5_PMON_BOX_FILTER1 Package Uncore C-Box 5 Perfmon Box Wide Filter 1 E57H MSR_C5_PMON_BOX_STATUS Package Uncore C-Box 5 Perfmon Box Wide Status E58H MSR_C5_PMON_CTR0 Package Uncore C-Box 5 Perfmon Counter 0 E59H MSR_C5_PMON_CTR1 Package Uncore C-Box 5 Perfmon Counter 1 E5AH MSR_C5_PMON_CTR2 Package Uncore C-Box 5 Perfmon Counter 2 E5BH MSR_C5_PMON_CTR3 Package Uncore C-Box 5 Perfmon Counter 3 E60H MSR_C6_PMON_BOX_CTL Package Uncore C-Box 6 Perfmon for Box-Wide Control E61H MSR_C6_PMON_EVNTSEL0 Package Uncore C-Box 6 Perfmon Event Select for C-Box 6 Counter 0 E62H MSR_C6_PMON_EVNTSEL1 Package Uncore C-Box 6 Perfmon Event Select for C-Box 6 Counter 1 E63H MSR_C6_PMON_EVNTSEL2 Package Uncore C-Box 6 Perfmon Event Select for C-Box 6 Counter 2 E64H MSR_C6_PMON_EVNTSEL3 Package Uncore C-Box 6 Perfmon Event Select for C-Box 6 Counter 3 E65H MSR_C6_PMON_BOX_FILTER0 Package Uncore C-Box 6 Perfmon Box Wide Filter 0 E66H MSR_C6_PMON_BOX_FILTER1 Package Uncore C-Box 6 Perfmon Box Wide Filter 1 E67H MSR_C6_PMON_BOX_STATUS Package Uncore C-Box 6 Perfmon Box Wide Status E68H MSR_C6_PMON_CTR0 Package Uncore C-Box 6 Perfmon Counter 0 E69H MSR_C6_PMON_CTR1 Package Uncore C-Box 6 Perfmon Counter 1 E6AH MSR_C6_PMON_CTR2 Package Uncore C-Box 6 Perfmon Counter 2 E6BH MSR_C6_PMON_CTR3 Package Uncore C-Box 6 Perfmon Counter 3 E70H MSR_C7_PMON_BOX_CTL Package Uncore C-Box 7 Perfmon for Box-Wide Control E71H MSR_C7_PMON_EVNTSEL0 Package Uncore C-Box 7 Perfmon Event Select for C-Box 7 Counter 0 E72H MSR_C7_PMON_EVNTSEL1 Package Uncore C-Box 7 Perfmon Event Select for C-Box 7 Counter 1 E73H MSR_C7_PMON_EVNTSEL2 Package Uncore C-Box 7 Perfmon Event Select for C-Box 7 Counter 2 E74H MSR_C7_PMON_EVNTSEL3 Package Uncore C-Box 7 Perfmon Event Select for C-Box 7 Counter 3 E75H MSR_C7_PMON_BOX_FILTER0 Package Uncore C-Box 7 Perfmon Box Wide Filter 0 E76H MSR_C7_PMON_BOX_FILTER1 Package Uncore C-Box 7 Perfmon Box Wide Filter 1 E77H MSR_C7_PMON_BOX_STATUS Package Uncore C-Box 7 Perfmon Box Wide Status E78H MSR_C7_PMON_CTR0 Package Uncore C-Box 7 Perfmon Counter 0 E79H MSR_C7_PMON_CTR1 Package Uncore C-Box 7 Perfmon Counter 1 E7AH MSR_C7_PMON_CTR2 Package Uncore C-Box 7 Perfmon Counter 2 E7BH MSR_C7_PMON_CTR3 Package Uncore C-Box 7 Perfmon Counter 3 2-240 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-33. Uncore PMU MSRs in Intel® Xeon® Processor E5 v3 Family (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec E80H MSR_C8_PMON_BOX_CTL Package Uncore C-Box 8 Perfmon Local Box Wide Control E81H MSR_C8_PMON_EVNTSEL0 Package Uncore C-Box 8 Perfmon Event Select for C-Box 8 Counter 0 E82H MSR_C8_PMON_EVNTSEL1 Package Uncore C-Box 8 Perfmon Event Select for C-Box 8 Counter 1 E83H MSR_C8_PMON_EVNTSEL2 Package Uncore C-Box 8 Perfmon Event Select for C-Box 8 Counter 2 E84H MSR_C8_PMON_EVNTSEL3 Package Uncore C-Box 8 Perfmon Event Select for C-Box 8 Counter 3 E85H MSR_C8_PMON_BOX_FILTER0 Package Uncore C-Box 8 Perfmon Box Wide Filter 0 E86H MSR_C8_PMON_BOX_FILTER1 Package Uncore C-Box 8 Perfmon Box Wide Filter 1 E87H MSR_C8_PMON_BOX_STATUS Package Uncore C-Box 8 Perfmon Box Wide Status E88H MSR_C8_PMON_CTR0 Package Uncore C-Box 8 Perfmon Counter 0 E89H MSR_C8_PMON_CTR1 Package Uncore C-Box 8 Perfmon Counter 1 E8AH MSR_C8_PMON_CTR2 Package Uncore C-Box 8 Perfmon Counter 2 E8BH MSR_C8_PMON_CTR3 Package Uncore C-Box 8 Perfmon Counter 3 E90H MSR_C9_PMON_BOX_CTL Package Uncore C-Box 9 Perfmon Local Box Wide Control E91H MSR_C9_PMON_EVNTSEL0 Package Uncore C-Box 9 Perfmon Event Select for C-Box 9 Counter 0 E92H MSR_C9_PMON_EVNTSEL1 Package Uncore C-Box 9 Perfmon Event Select for C-Box 9 Counter 1 E93H MSR_C9_PMON_EVNTSEL2 Package Uncore C-Box 9 Perfmon Event Select for C-Box 9 Counter 2 E94H MSR_C9_PMON_EVNTSEL3 Package Uncore C-Box 9 Perfmon Event Select for C-Box 9 Counter 3 E95H MSR_C9_PMON_BOX_FILTER0 Package Uncore C-Box 9 Perfmon Box Wide Filter 0 E96H MSR_C9_PMON_BOX_FILTER1 Package Uncore C-Box 9 Perfmon Box Wide Filter 1 E97H MSR_C9_PMON_BOX_STATUS Package Uncore C-Box 9 Perfmon Box Wide Status E98H MSR_C9_PMON_CTR0 Package Uncore C-Box 9 Perfmon Counter 0 E99H MSR_C9_PMON_CTR1 Package Uncore C-Box 9 Perfmon Counter 1 E9AH MSR_C9_PMON_CTR2 Package Uncore C-Box 9 Perfmon Counter 2 E9BH MSR_C9_PMON_CTR3 Package Uncore C-Box 9 Perfmon Counter 3 EA0H MSR_C10_PMON_BOX_CTL Package Uncore C-Box 10 Perfmon Local Box Wide Control EA1H MSR_C10_PMON_EVNTSEL0 Package Uncore C-Box 10 Perfmon Event Select for C-Box 10 Counter 0 EA2H MSR_C10_PMON_EVNTSEL1 Package Uncore C-Box 10 Perfmon Event Select for C-Box 10 Counter 1 EA3H MSR_C10_PMON_EVNTSEL2 Package Uncore C-Box 10 Perfmon Event Select for C-Box 10 Counter 2 EA4H MSR_C10_PMON_EVNTSEL3 Package Uncore C-Box 10 Perfmon Event Select for C-Box 10 Counter 3 Vol. 4 2-241 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-33. Uncore PMU MSRs in Intel® Xeon® Processor E5 v3 Family (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec EA5H MSR_C10_PMON_BOX_FILTER0 Package Uncore C-Box 10 Perfmon Box Wide Filter 0 EA6H MSR_C10_PMON_BOX_FILTER1 Package Uncore C-Box 10 Perfmon Box Wide Filter 1 EA7H MSR_C10_PMON_BOX_STATUS Package Uncore C-Box 10 Perfmon Box Wide Status EA8H MSR_C10_PMON_CTR0 Package Uncore C-Box 10 Perfmon Counter 0 EA9H MSR_C10_PMON_CTR1 Package Uncore C-Box 10 perfmon Counter 1 EAAH MSR_C10_PMON_CTR2 Package Uncore C-Box 10 Perfmon Counter 2 EABH MSR_C10_PMON_CTR3 Package Uncore C-Box 10 Perfmon Counter 3 EB0H MSR_C11_PMON_BOX_CTL Package Uncore C-Box 11 Perfmon Local Box Wide Control EB1H MSR_C11_PMON_EVNTSEL0 Package Uncore C-Box 11 Perfmon Event Select for C-Box 11 Counter 0 EB2H MSR_C11_PMON_EVNTSEL1 Package Uncore C-Box 11 Perfmon Event Select for C-Box 11 Counter 1 EB3H MSR_C11_PMON_EVNTSEL2 Package Uncore C-Box 11 Perfmon Event Select for C-Box 11 Counter 2 EB4H MSR_C11_PMON_EVNTSEL3 Package Uncore C-box 11 Perfmon Event Select for C-Box 11 Counter 3 EB5H MSR_C11_PMON_BOX_FILTER0 Package Uncore C-Box 11 Perfmon Box Wide Filter 0 EB6H MSR_C11_PMON_BOX_FILTER1 Package Uncore C-Box 11 Perfmon Box Wide Filter 1 EB7H MSR_C11_PMON_BOX_STATUS Package Uncore C-Box 11 Perfmon Box Wide Status EB8H MSR_C11_PMON_CTR0 Package Uncore C-Box 11 Perfmon Counter 0 EB9H MSR_C11_PMON_CTR1 Package Uncore C-Box 11 Perfmon Counter 1 EBAH MSR_C11_PMON_CTR2 Package Uncore C-Box 11 Perfmon Counter 2 EBBH MSR_C11_PMON_CTR3 Package Uncore C-Box 11 Perfmon Counter 3 EC0H MSR_C12_PMON_BOX_CTL Package Uncore C-Box 12 Perfmon Local Box Wide Control EC1H MSR_C12_PMON_EVNTSEL0 Package Uncore C-Box 12 Perfmon Event Select for C-Box 12 Counter 0 EC2H MSR_C12_PMON_EVNTSEL1 Package Uncore C-Box 12 Perfmon Event Select for C-Box 12 Counter 1 EC3H MSR_C12_PMON_EVNTSEL2 Package Uncore C-Box 12 Perfmon Event Select for C-Box 12 Counter 2 EC4H MSR_C12_PMON_EVNTSEL3 Package Uncore C-Box 12 Perfmon Event Select for C-Box 12 Counter 3 EC5H MSR_C12_PMON_BOX_FILTER0 Package Uncore C-Box 12 Perfmon Box Wide Filter 0 EC6H MSR_C12_PMON_BOX_FILTER1 Package Uncore C-Box 12 Perfmon Box Wide Filter 1 EC7H MSR_C12_PMON_BOX_STATUS Package Uncore C-Box 12 Perfmon Box Wide Status EC8H MSR_C12_PMON_CTR0 Package Uncore C-Box 12 Perfmon Counter 0 EC9H MSR_C12_PMON_CTR1 Package Uncore C-Box 12 Perfmon Counter 1 ECAH MSR_C12_PMON_CTR2 Package Uncore C-Box 12 Perfmon Counter 2 ECBH MSR_C12_PMON_CTR3 Package Uncore C-Box 12 Perfmon Counter 3 2-242 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-33. Uncore PMU MSRs in Intel® Xeon® Processor E5 v3 Family (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec ED0H MSR_C13_PMON_BOX_CTL Package Uncore C-Box 13 Perfmon local box wide control. ED1H MSR_C13_PMON_EVNTSEL0 Package Uncore C-Box 13 Perfmon Event Select for C-Box 13 Counter 0 ED2H MSR_C13_PMON_EVNTSEL1 Package Uncore C-Box 13 Perfmon Event Select for C-Box 13 Counter 1 ED3H MSR_C13_PMON_EVNTSEL2 Package Uncore C-Box 13 Perfmon Event Select for C-Box 13 Counter 2 ED4H MSR_C13_PMON_EVNTSEL3 Package Uncore C-Box 13 Perfmon Event Select for C-Box 13 Counter 3 ED5H MSR_C13_PMON_BOX_FILTER0 Package Uncore C-Box 13 Perfmon Box Wide Filter 0 ED6H MSR_C13_PMON_BOX_FILTER1 Package Uncore C-Box 13 Perfmon Box Wide Filter 1 ED7H MSR_C13_PMON_BOX_STATUS Package Uncore C-Box 13 Perfmon Box Wide Status ED8H MSR_C13_PMON_CTR0 Package Uncore C-Box 13 Perfmon Counter 0 ED9H MSR_C13_PMON_CTR1 Package Uncore C-Box 13 Perfmon Counter 1 EDAH MSR_C13_PMON_CTR2 Package Uncore C-Box 13 Perfmon Counter 2 EDBH MSR_C13_PMON_CTR3 Package Uncore C-Box 13 Perfmon Counter 3 EE0H MSR_C14_PMON_BOX_CTL Package Uncore C-Box 14 Perfmon Local Box Wide Control EE1H MSR_C14_PMON_EVNTSEL0 Package Uncore C-Box 14 Perfmon Event Select for C-Box 14 Counter 0 EE2H MSR_C14_PMON_EVNTSEL1 Package Uncore C-Box 14 Perfmon Event Select for C-Box 14 Counter 1 EE3H MSR_C14_PMON_EVNTSEL2 Package Uncore C-Box 14 Perfmon Event Select for C-Box 14 Counter 2 EE4H MSR_C14_PMON_EVNTSEL3 Package Uncore C-Box 14 Perfmon Event Select for C-Box 14 Counter 3 EE5H MSR_C14_PMON_BOX_FILTER Package Uncore C-Box 14 Perfmon Box Wide Filter 0 EE6H MSR_C14_PMON_BOX_FILTER1 Package Uncore C-Box 14 Perfmon Box Wide Filter 1 EE7H MSR_C14_PMON_BOX_STATUS Package Uncore C-Box 14 Perfmon Box Wide Status EE8H MSR_C14_PMON_CTR0 Package Uncore C-Box 14 Perfmon Counter 0 EE9H MSR_C14_PMON_CTR1 Package Uncore C-Box 14 Perfmon Counter 1 EEAH MSR_C14_PMON_CTR2 Package Uncore C-Box 14 Perfmon Counter 2 EEBH MSR_C14_PMON_CTR3 Package Uncore C-Box 14 Perfmon Counter 3 EF0H MSR_C15_PMON_BOX_CTL Package Uncore C-Box 15 Perfmon Local Box Wide Control EF1H MSR_C15_PMON_EVNTSEL0 Package Uncore C-Box 15 Perfmon Event Select for C-Box 15 Counter 0 EF2H MSR_C15_PMON_EVNTSEL1 Package Uncore C-Box 15 Perfmon Event Select for C-Box 15 Counter 1 EF3H MSR_C15_PMON_EVNTSEL2 Package Uncore C-Box 15 Perfmon Event Select for C-Box 15 Counter 2 EF4H MSR_C15_PMON_EVNTSEL3 Package Uncore C-Box 15 Perfmon Event Select for C-Box 15 Counter 3 Vol. 4 2-243 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-33. Uncore PMU MSRs in Intel® Xeon® Processor E5 v3 Family (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec EF5H MSR_C15_PMON_BOX_FILTER0 Package Uncore C-Box 15 Perfmon Box Wide Filter 0 EF6H MSR_C15_PMON_BOX_FILTER1 Package Uncore C-Box 15 Perfmon Box Wide Filter 1 EF7H MSR_C15_PMON_BOX_STATUS Package Uncore C-Box 15 Perfmon Box Wide Status EF8H MSR_C15_PMON_CTR0 Package Uncore C-Box 15 Perfmon Counter 0 EF9H MSR_C15_PMON_CTR1 Package Uncore C-Box 15 Perfmon Counter 1 EFAH MSR_C15_PMON_CTR2 Package Uncore C-Box 15 Perfmon Counter 2 EFBH MSR_C15_PMON_CTR3 Package Uncore C-Box 15 Perfmon Counter 3 F00H MSR_C16_PMON_BOX_CTL Package Uncore C-Box 16 Perfmon for Box-Wide Control F01H MSR_C16_PMON_EVNTSEL0 Package Uncore C-Box 16 Perfmon Event Select for C-Box 16 Counter 0 F02H MSR_C16_PMON_EVNTSEL1 Package Uncore C-Box 16 Perfmon Event Select for C-Box 16 Counter 1 F03H MSR_C16_PMON_EVNTSEL2 Package Uncore C-Box 16 Perfmon Event Select for C-Box 16 Counter 2 F04H MSR_C16_PMON_EVNTSEL3 Package Uncore C-Box 16 Perfmon Event Select for C-Box 16 Counter 3 F05H MSR_C16_PMON_BOX_FILTER0 Package Uncore C-Box 16 Perfmon Box Wide Filter 0 F06H MSR_C16_PMON_BOX_FILTER1 Package Uncore C-Box 16 Perfmon Box Wide Filter 1 F07H MSR_C16_PMON_BOX_STATUS Package Uncore C-Box 16 Perfmon Box Wide Status F08H MSR_C16_PMON_CTR0 Package Uncore C-Box 16 Perfmon Counter 0 F09H MSR_C16_PMON_CTR1 Package Uncore C-Box 16 Perfmon Counter 1 F0AH MSR_C16_PMON_CTR2 Package Uncore C-Box 16 Perfmon Counter 2 E0BH MSR_C16_PMON_CTR3 Package Uncore C-Box 16 Perfmon Counter 3 F10H MSR_C17_PMON_BOX_CTL Package Uncore C-Box 17 Perfmon for Box-Wide Control F11H MSR_C17_PMON_EVNTSEL0 Package Uncore C-Box 17 Perfmon Event Select for C-Box 17 Counter 0 F12H MSR_C17_PMON_EVNTSEL1 Package Uncore C-Box 17 Perfmon Event Select for C-Box 17 Counter 1 F13H MSR_C17_PMON_EVNTSEL2 Package Uncore C-Box 17 Perfmon Event Select for C-Box 17 Counter 2 F14H MSR_C17_PMON_EVNTSEL3 Package Uncore C-Box 17 Perfmon Event Select for C-Box 17 Counter 3 F15H MSR_C17_PMON_BOX_FILTER0 Package Uncore C-Box 17 Perfmon Box Wide Filter 0 F16H MSR_C17_PMON_BOX_FILTER1 Package Uncore C-Box 17 Perfmon Box Wide Filter1 F17H MSR_C17_PMON_BOX_STATUS Package Uncore C-Box 17 Perfmon Box Wide Status F18H MSR_C17_PMON_CTR0 Package Uncore C-Box 17 Perfmon Counter 0 F19H MSR_C17_PMON_CTR1 Package Uncore C-Box 17 Perfmon Counter 1 F1AH MSR_C17_PMON_CTR2 Package Uncore C-Box 17 Perfmon Counter 2 F1BH MSR_C17_PMON_CTR3 Package Uncore C-Box 17 Perfmon Counter 3 2-244 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) 2.15 MSRS IN INTEL® CORE™ M PROCESSORS AND 5TH GENERATION INTEL CORE PROCESSORS The Intel® Core™ M-5xxx processors and 5th generation Intel® Core™ Processors, and Intel® Xeon® Processor E3-1200 v4 family are based on the Broadwell microarchitecture. The Intel® Core™ M-5xxx processors and 5th generation Intel® Core™ Processors have CPUID DisplayFamily_DisplayModel signature 06_3DH. Intel® Xeon® Processor E3-1200 v4 family and the 5th generation Intel® Core™ Processors have CPUID DisplayFamily_DisplayModel signature 06_47H. Processors with signatures 06_3DH and 06_47H support the MSR interfaces listed in Table 2-20, Table 2-21, Table 2-22, Table 2-25, Table 2-29, Table 2-30, Table 2-34, and Table 2-35. For an MSR listed in Table 2-35 that also appears in the model-specific tables of prior generations, Table 2-35 supercede prior generation tables. Table 2-34 lists MSRs that are common to processors based on the Broadwell microarchitectures (including CPUID signatures 06_3DH, 06_47H, 06_4FH, and 06_56H). Table 2-34. Additional MSRs Common to Processors Based the Broadwell Microarchitectures Register Address Hex Dec 38EH 910 Register Name / Bit Fields IA32_PERF_GLOBAL_STATUS Scope Thread Bit Description See Table 2-2. See Section 18.6.2.2, “Global Counter Control Facilities.” 0 Ovf_PMC0 1 Ovf_PMC1 2 Ovf_PMC2 3 Ovf_PMC3 31:4 Reserved 32 Ovf_FixedCtr0 33 Ovf_FixedCtr1 34 Ovf_FixedCtr2 54:35 Reserved 55 Trace_ToPA_PMI See Section 35.2.6.2, “Table of Physical Addresses (ToPA).” 390H 912 60:56 Reserved 61 Ovf_Uncore 62 Ovf_BufDSSAVE 63 CondChgd IA32_PERF_GLOBAL_OVF_CTRL Thread See Table 2-2. See Section 18.6.2.2, “Global Counter Control Facilities.” 0 Set 1 to clear Ovf_PMC0 1 Set 1 to clear Ovf_PMC1 2 Set 1 to clear Ovf_PMC2 3 Set 1 to clear Ovf_PMC3 31:4 Reserved 32 Set 1 to clear Ovf_FixedCtr0 33 Set 1 to clear Ovf_FixedCtr1 Vol. 4 2-245 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-34. Additional MSRs Common to Processors Based the Broadwell Microarchitectures Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 34 Set 1 to clear Ovf_FixedCtr2 54:35 Reserved. 55 Set 1 to clear Trace_ToPA_PMI. See Section 35.2.6.2, “Table of Physical Addresses (ToPA).” 560H 1376 60:56 Reserved 61 Set 1 to clear Ovf_Uncore 62 Set 1 to clear Ovf_BufDSSAVE 63 Set 1 to clear CondChgd IA32_RTIT_OUTPUT_BASE THREAD Reserved MAXPHYADDR1-1:7 Base physical address. 63:MAXPHYADDR 561H 570H 1377 1392 Trace Output Base Register (R/W) 6:0 IA32_RTIT_OUTPUT_MASK_PTRS Reserved THREAD Trace Output Mask Pointers Register (R/W) 6:0 Reserved 31:7 MaskOrTableOffset 63:32 Output Offset. IA32_RTIT_CTL Thread Trace Control Register (R/W) 0 TraceEn 1 Reserved, must be zero. 2 OS 3 User 6:4 Reserved, must be zero. 7 CR3 filter 8 ToPA Writing 0 will #GP if also setting TraceEn. 571H 1393 2-246 Vol. 4 9 Reserved, must be zero. 10 TSCEn 11 DisRETC 12 Reserved, must be zero. 13 Reserved; writing 0 will #GP if also setting TraceEn. 63:14 Reserved, must be zero. IA32_RTIT_STATUS Thread Tracing Status Register (R/W) 0 Reserved, writes ignored. 1 ContexEn, writes ignored. 2 TriggerEn, writes ignored. 3 Reserved MODEL-SPECIFIC REGISTERS (MSRS) Table 2-34. Additional MSRs Common to Processors Based the Broadwell Microarchitectures Register Address Hex 572H Register Name / Bit Fields Scope Bit Description Dec 1394 620H 4 Error (R/W) 5 Stopped 63:6 Reserved, must be zero. IA32_RTIT_CR3_MATCH THREAD Trace Filter CR3 Match Register (R/W) 4:0 Reserved 63:5 CR3[63:5] value to match. MSR UNCORE_RATIO_LIMIT Package Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio fields represent the widest possible range of uncore frequencies. Writing to these fields allows software to control the minimum and the maximum frequency that hardware will select. 63:15 Reserved 14:8 MIN_RATIO Writing to this field controls the minimum possible ratio of the LLC/Ring. 7 Reserved 6:0 MAX_RATIO This field is used to limit the max ratio of the LLC/Ring. NOTES: 1. MAXPHYADDR is reported by CPUID.80000008H:EAX[7:0]. Table 2-35 lists MSRs that are specific to Intel Core M processors and 5th Generation Intel Core Processors. Table 2-35. Additional MSRs Supported by Intel® Core™ M Processors and 5th Generation Intel® Core™ Processors Register Address Hex Dec E2H 226 Register Name MSR_PKG_CST_CONFIG_CONTROL Scope Core Bit Description C-State Configuration Control (R/W) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-states. See http://biosbits.org. Vol. 4 2-247 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-35. Additional MSRs Supported by Intel® Core™ M Processors and 5th Generation Intel® Core™ Processors Register Address Hex Register Name Scope Bit Description Dec 3:0 Package C-State Limit (R/W) Specifies the lowest processor-specific C-state code name (consuming the least power) for the package. The default is set as factory-configured package Cstate limit. The following C-state code name encodings are supported: 0000b: C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6 0100b: C7 0101b: C7s 0110b: C8 0111b: C9 1000b: C10 1ADH 429 9:4 Reserved 10 I/O MWAIT Redirection Enable (R/W) 14:11 Reserved 15 CFG Lock (R/WO) 24:16 Reserved 25 C3 State Auto Demotion Enable (R/W) 26 C1 State Auto Demotion Enable (R/W) 27 Enable C3 Undemotion (R/W) 28 Enable C1 Undemotion (R/W) 29 Enable Package C-State Auto-Demotion (R/W) 30 Enable Package C-State Undemotion (R/W) 63:31 Reserved MSR_TURBO_RATIO_LIMIT Package Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0. RW if MSR_PLATFORM_INFO.[28] = 1. 7:0 Package Maximum Ratio Limit for 1C Maximum turbo ratio limit of 1 core active. 15:8 Package Maximum Ratio Limit for 2C Maximum turbo ratio limit of 2 core active. 23:16 Package Maximum Ratio Limit for 3C Maximum turbo ratio limit of 3 core active. 31:24 Package Maximum Ratio Limit for 4C Maximum turbo ratio limit of 4 core active. 2-248 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-35. Additional MSRs Supported by Intel® Core™ M Processors and 5th Generation Intel® Core™ Processors Register Address Hex Register Name Scope Bit Description Dec 39:32 Package Maximum Ratio Limit for 5C Maximum turbo ratio limit of 5core active. 47:40 Package Maximum Ratio Limit for 6C Maximum turbo ratio limit of 6core active. 63:48 639H 1593 Reserved MSR_PP0_ENERGY_STATUS Package PP0 Energy Status (R/O) See Section 14.9.4, “PP0/PP1 RAPL Domains.” See Table 2-20, Table 2-21, Table 2-22, Table 2-25, Table 2-29, Table 2-30, Table 2-34 for other MSR definitions applicable to processors with CPUID signature 06_3DH. 2.16 MSRS IN INTEL® XEON® PROCESSORS E5 V4 FAMILY The MSRs listed in Table 2-36 are available and common to Intel® Xeon® Processor D product Family (CPUID DisplayFamily_DisplayModel = 06_56H) and to Intel Xeon processors E5 v4, E7 v4 families (CPUID DisplayFamily_DisplayModel = 06_4FH). They are based on the Broadwell microarchitecture. See Section 2.16.1 for lists of tables of MSRs that are supported by Intel® Xeon® Processor D Family. Table 2-36. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family Based on the Broadwell Microarchitecture Register Address Hex Dec 4EH 78 Register Name / Bit Fields MSR_PPIN_CTL Scope Package 0 Bit Description Protected Processor Inventory Number Enable Control (R/W) LockOut (R/WO) See Table 2-26. 1 Enable_PPIN (R/W) See Table 2-26. 63:2 4FH 79 MSR_PPIN Reserved Package 63:0 Protected Processor Inventory Number (R/O) Protected Processor Inventory Number (R/O) See Table 2-26. CEH 206 MSR_PLATFORM_INFO Package Platform Information Contains power management and other model specific features enumeration. See http://biosbits.org. 7:0 15:8 Reserved Package Maximum Non-Turbo Ratio (R/O) See Table 2-26. 22:16 Reserved. Vol. 4 2-249 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-36. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family Based on the Broadwell Microarchitecture Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 23 Package PPIN_CAP (R/O) See Table 2-26. 27:24 28 Reserved Package Programmable Ratio Limit for Turbo Mode (R/O) See Table 2-26. 29 Package Programmable TDP Limit for Turbo Mode (R/O) See Table 2-26. 30 Package Programmable TJ OFFSET (R/O) See Table 2-26. 39:31 47:40 Reserved Package Maximum Efficiency Ratio (R/O) See Table 2-26. 63:48 E2H 226 MSR_PKG_CST_CONFIG_CONTROL Reserved Core C-State Configuration Control (R/W) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-states. See http://biosbits.org. 2:0 Package C-State Limit (R/W) Specifies the lowest processor-specific C-state code name (consuming the least power) for the package. The default is set as factory-configured package C-state limit. The following C-state code name encodings are supported: 000b: C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention) 011b: C6 (retention) 111b: No Package C state limits. All C states supported by the processor are available. 9:3 Reserved 10 I/O MWAIT Redirection Enable (R/W) 14:11 Reserved 15 CFG Lock (R/WO) 16 Automatic C-State Conversion Enable (R/W) If 1, the processor will convert HALT or MWAT(C1) to MWAIT(C6). 2-250 Vol. 4 24:17 Reserved 25 C3 State Auto Demotion Enable (R/W) MODEL-SPECIFIC REGISTERS (MSRS) Table 2-36. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family Based on the Broadwell Microarchitecture Register Address Hex 179H 17DH Register Name / Bit Fields Scope Bit Description Dec 377 390 26 C1 State Auto Demotion Enable (R/W) 27 Enable C3 Undemotion (R/W) 28 Enable C1 Undemotion (R/W) 29 Package C State Demotion Enable (R/W) 30 Package C State UnDemotion Enable (R/W) 63:31 Reserved IA32_MCG_CAP Thread Global Machine Check Capability (R/O) 7:0 Count 8 MCG_CTL_P 9 MCG_EXT_P 10 MCP_CMCI_P 11 MCG_TES_P 15:12 Reserved 23:16 MCG_EXT_CNT 24 MCG_SER_P 25 MCG_EM_P 26 MCG_ELOG_P 63:27 Reserved MSR_SMM_MCA_CAP Thread Enhanced SMM Capabilities (SMM-RO) Reports SMM capability Enhancement. Accessible only while in SMM. 57:0 Reserved 58 SMM_Code_Access_Chk (SMM-RO) If set to 1, indicates that the SMM code access restriction is supported and a host-space interface available to SMM handler. 59 Long_Flow_Indication (SMM-RO) If set to 1, indicates that the SMM long flow indicator is supported and a host-space interface available to SMM handler. 63:60 19CH 412 IA32_THERM_STATUS Reserved Core Thermal Monitor Status (R/W) See Table 2-2. 0 Thermal Status (RO) See Table 2-2. 1 Thermal Status Log (R/WC0) See Table 2-2. Vol. 4 2-251 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-36. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family Based on the Broadwell Microarchitecture Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 2 PROTCHOT # or FORCEPR# Status (RO) See Table 2-2. 3 PROTCHOT # or FORCEPR# Log (R/WC0) See Table 2-2. 4 Critical Temperature Status (RO) See Table 2-2. 5 Critical Temperature Status Log (R/WC0) See Table 2-2. 6 Thermal Threshold #1 Status (RO) See Table 2-2. 7 Thermal Threshold #1 Log (R/WC0) See Table 2-2. 8 Thermal Threshold #2 Status (RO) See Table 2-2. 9 Thermal Threshold #2 Log (R/WC0) See Table 2-2. 10 Power Limitation Status (RO) See Table 2-2. 11 Power Limitation Log (R/WC0) See Table 2-2. 12 Current Limit Status (RO) See Table 2-2. 13 Current Limit Log (R/WC0) See Table 2-2. 14 Cross Domain Limit Status (RO) See Table 2-2. 15 Cross Domain Limit Log (R/WC0) See Table 2-2. 22:16 Digital Readout (RO) See Table 2-2. 26:23 Reserved 30:27 Resolution in Degrees Celsius (RO) See Table 2-2. 31 Reading Valid (RO) See Table 2-2. 63:32 1A2H 418 MSR_TEMPERATURE_TARGET 15:0 2-252 Vol. 4 Reserved Package Temperature Target Reserved MODEL-SPECIFIC REGISTERS (MSRS) Table 2-36. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family Based on the Broadwell Microarchitecture Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 23:16 Temperature Target (RO) See Table 2-26. 27:24 TCC Activation Offset (R/W) See Table 2-26. 63:28 1ADH 429 MSR_TURBO_RATIO_LIMIT Reserved. Package Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0. RW if MSR_PLATFORM_INFO.[28] = 1. 1AEH 430 7:0 Package Maximum Ratio Limit for 1C 15:8 Package Maximum Ratio Limit for 2C 23:16 Package Maximum Ratio Limit for 3C 31:24 Package Maximum Ratio Limit for 4C 39:32 Package Maximum Ratio Limit for 5C 47:40 Package Maximum Ratio Limit for 6C 55:48 Package Maximum Ratio Limit for 7C 63:56 Package Maximum Ratio Limit for 8C MSR_TURBO_RATIO_LIMIT1 Package Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0. RW if MSR_PLATFORM_INFO.[28] = 1. 606H 1542 7:0 Package Maximum Ratio Limit for 9C 15:8 Package Maximum Ratio Limit for 10C 23:16 Package Maximum Ratio Limit for 11C 31:24 Package Maximum Ratio Limit for 12C 39:32 Package Maximum Ratio Limit for 13C 47:40 Package Maximum Ratio Limit for 14C 55:48 Package Maximum Ratio Limit for 15C 63:56 Package Maximum Ratio Limit for 16C MSR_RAPL_POWER_UNIT Package Unit Multipliers Used in RAPL Interfaces (R/O) 3:0 Package Power Units See Section 14.9.1, “RAPL Interfaces.” 7:4 Package Reserved 12:8 Package Energy Status Units Energy related information (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an unsigned integer represented by bits 12:8. Default value is 0EH (or 61 micro-joules). 15:13 Package Reserved Vol. 4 2-253 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-36. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family Based on the Broadwell Microarchitecture Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 19:16 Package Time Units See Section 14.9.1, “RAPL Interfaces.” 63:20 618H 1560 MSR_DRAM_POWER_LIMIT Reserved Package DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, “DRAM RAPL Domain.” 619H 1561 MSR_DRAM_ENERGY_STATUS Package DRAM Energy Status (R/O) Energy consumed by DRAM devices. 61BH 1563 31:0 Energy in 15.3 micro-joules. Requires BIOS configuration to enable DRAM RAPL mode 0 (Direct VR). 63:32 Reserved MSR_DRAM_PERF_STATUS Package DRAM Performance Throttling Status (R/O) See Section 14.9.5, “DRAM RAPL Domain.” 61CH 1564 MSR_DRAM_POWER_INFO Package DRAM RAPL Parameters (R/W) See Section 14.9.5, “DRAM RAPL Domain.” 620H 1568 MSR UNCORE_RATIO_LIMIT Package Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio fields represent the widest possible range of uncore frequencies. Writing to these fields allows software to control the minimum and the maximum frequency that hardware will select. 63:15 Reserved 14:8 MIN_RATIO Writing to this field controls the minimum possible ratio of the LLC/Ring. 7 Reserved 6:0 MAX_RATIO This field is used to limit the max ratio of the LLC/Ring. 639H 1593 MSR_PP0_ENERGY_STATUS Package Reserved (R/O) Reads return 0. 690H 1680 MSR_CORE_PERF_LIMIT_REASONS Package Indicator of Frequency Clipping in Processor Cores (R/W) (Frequency refers to processor core frequency.) 0 PROCHOT Status (R0) When set, processor core frequency is reduced below the operating system request due to assertion of external PROCHOT. 1 Thermal Status (R0) When set, frequency is reduced below the operating system request due to a thermal event. 2-254 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-36. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family Based on the Broadwell Microarchitecture Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 2 Power Budget Management Status (R0) When set, frequency is reduced below the operating system request due to PBM limit. 3 Platform Configuration Services Status (R0) When set, frequency is reduced below the operating system request due to PCS limit. 4 Reserved 5 Autonomous Utilization-Based Frequency Control Status (R0) When set, frequency is reduced below the operating system request because the processor has detected that utilization is low. 6 VR Therm Alert Status (R0) When set, frequency is reduced below the operating system request due to a thermal alert from the Voltage Regulator. 7 Reserved 8 Electrical Design Point Status (R0) When set, frequency is reduced below the operating system request due to electrical design point constraints (e.g., maximum electrical current consumption). 9 Reserved 10 Multi-Core Turbo Status (R0) When set, frequency is reduced below the operating system request due to Multi-Core Turbo limits. 12:11 Reserved 13 Core Frequency P1 Status (R0) When set, frequency is reduced below max non-turbo P1. 14 Core Max N-Core Turbo Frequency Limiting Status (R0) When set, frequency is reduced below max n-core turbo frequency. 15 Core Frequency Limiting Status (R0) When set, frequency is reduced below the operating system request. 16 PROCHOT Log When set, indicates that the PROCHOT Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. Vol. 4 2-255 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-36. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family Based on the Broadwell Microarchitecture Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 17 Thermal Log When set, indicates that the Thermal Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 18 Power Budget Management Log When set, indicates that the PBM Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 19 Platform Configuration Services Log When set, indicates that the PCS Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 20 Reserved 21 Autonomous Utilization-Based Frequency Control Log When set, indicates that the AUBFC Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 22 VR Therm Alert Log When set, indicates that the VR Therm Alert Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 23 Reserved 24 Electrical Design Point Log When set, indicates that the EDP Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 25 Reserved 26 Multi-Core Turbo Log When set, indicates that the Multi-Core Turbo Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 28:27 2-256 Vol. 4 Reserved MODEL-SPECIFIC REGISTERS (MSRS) Table 2-36. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family Based on the Broadwell Microarchitecture Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 29 Core Frequency P1 Log When set, indicates that the Core Frequency P1 Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 30 Core Max N-Core Turbo Frequency Limiting Log When set, indicates that the Core Max n-core Turbo Frequency Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 31 Core Frequency Limiting Log When set, indicates that the Core Frequency Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 63:32 Reserved 770H 1904 IA32_PM_ENABLE Package See Section 14.4.2, “Enabling HWP”. 771H 1905 IA32_HWP_CAPABILITIES Thread See Section 14.4.3, “HWP Performance Range and Dynamic Capabilities”. 774H 1908 IA32_HWP_REQUEST Thread See Section 14.4.4, “Managing HWP”. 777H C8DH 1911 3213 7:0 Minimum Performance (R/W) 15:8 Maximum Performance (R/W) 23:16 Desired Performance (R/W) 63:24 Reserved IA32_HWP_STATUS Thread See Section 14.4.5, “HWP Feedback”. 1:0 Reserved 2 Excursion to Minimum (RO) 63:3 Reserved IA32_QM_EVTSEL THREAD Monitoring Event Select Register (R/W) If CPUID.(EAX=07H, ECX=0):EBX.RDT-M[bit 12] = 1. 7:0 EventID (RW) Event encoding: 0x00: No monitoring. 0x01: L3 occupancy monitoring. 0x02: Total memory bandwidth monitoring. 0x03: Local memory bandwidth monitoring. All other encoding reserved. 31:8 Reserved Vol. 4 2-257 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-36. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family Based on the Broadwell Microarchitecture Register Address Hex C8FH C90H Register Name / Bit Fields Scope Bit Description Dec 3215 3216 41:32 RMID (RW) 63:42 Reserved IA32_PQR_ASSOC THREAD Resource Association Register (R/W) 9:0 RMID 31:10 Reserved 51:32 COS (R/W) 63: 52 Reserved IA32_L3_QOS_MASK_0 Package L3 Class Of Service Mask - COS 0 (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=0. C91H 3217 0:19 CBM: Bit vector of available L3 ways for COS 0 enforcement. 63:20 Reserved IA32_L3_QOS_MASK_1 Package L3 Class Of Service Mask - COS 1 (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=1. C92H 3218 0:19 CBM: Bit vector of available L3 ways for COS 1 enforcement. 63:20 Reserved IA32_L3_QOS_MASK_2 Package L3 Class Of Service Mask - COS 2 (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=2. C93H 3219 0:19 CBM: Bit vector of available L3 ways for COS 2 enforcement. 63:20 Reserved IA32_L3_QOS_MASK_3 Package L3 Class Of Service Mask - COS 3 (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=3. C94H 3220 0:19 CBM: Bit vector of available L3 ways for COS 3 enforcement. 63:20 Reserved IA32_L3_QOS_MASK_4 Package L3 Class Of Service Mask - COS 4 (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=4. 0:19 CBM: Bit vector of available L3 ways for COS 4 enforcement. 63:20 C95H 3221 IA32_L3_QOS_MASK_5 Reserved Package L3 Class Of Service Mask - COS 5 (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=5. C96H 3222 0:19 CBM: Bit vector of available L3 ways for COS 5 enforcement. 63:20 Reserved IA32_L3_QOS_MASK_6 Package L3 Class Of Service Mask - COS 6 (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=6. 2-258 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-36. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family Based on the Broadwell Microarchitecture Register Address Hex C97H Register Name / Bit Fields Scope Bit Description Dec 3223 0:19 CBM: Bit vector of available L3 ways for COS 6 enforcement. 63:20 Reserved IA32_L3_QOS_MASK_7 Package L3 Class Of Service Mask - COS 7 (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=7. C98H 3224 0:19 CBM: Bit vector of available L3 ways for COS 7 enforcement. 63:20 Reserved IA32_L3_QOS_MASK_8 Package L3 Class Of Service Mask - COS 8 (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=8. 0:19 CBM: Bit vector of available L3 ways for COS 8 enforcement. 63:20 C99H 3225 IA32_L3_QOS_MASK_9 Reserved Package L3 Class Of Service Mask - COS 9 (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=9. C9AH 3226 0:19 CBM: Bit vector of available L3 ways for COS 9 enforcement. 63:20 Reserved IA32_L3_QOS_MASK_10 Package L3 Class Of Service Mask - COS 10 (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=10. C9BH 3227 0:19 CBM: Bit vector of available L3 ways for COS 10 enforcement. 63:20 Reserved IA32_L3_QOS_MASK_11 Package L3 Class Of Service Mask - COS 11 (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=11. C9CH 3228 0:19 CBM: Bit vector of available L3 ways for COS 11 enforcement. 63:20 Reserved IA32_L3_QOS_MASK_12 Package L3 Class Of Service Mask - COS 12 (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=12. C9DH 3229 0:19 CBM: Bit vector of available L3 ways for COS 12 enforcement. 63:20 Reserved IA32_L3_QOS_MASK_13 Package L3 Class Of Service Mask - COS 13 (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=13. C9EH 3230 0:19 CBM: Bit vector of available L3 ways for COS 13 enforcement. 63:20 Reserved IA32_L3_QOS_MASK_14 Package L3 Class Of Service Mask - COS 14 (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=14. Vol. 4 2-259 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-36. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family Based on the Broadwell Microarchitecture Register Address Hex C9FH Register Name / Bit Fields Scope Bit Description Dec 3231 0:19 CBM: Bit vector of available L3 ways for COS 14 enforcement. 63:20 Reserved IA32_L3_QOS_MASK_15 Package L3 Class Of Service Mask - COS 15 (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=15. 2.16.1 0:19 CBM: Bit vector of available L3 ways for COS 15 enforcement. 63:20 Reserved Additional MSRs Supported in the Intel® Xeon® Processor D Product Family The MSRs listed in Table 2-37 are available to Intel® Xeon® Processor D Product Family (CPUID DisplayFamily_DisplayModel = 06_56H). The Intel® Xeon® processor D product family is based on the Broadwell microarchitecture and supports the MSR interfaces listed in Table 2-20, Table 2-29, Table 2-34, Table 2-36, and Table 2-37. Table 2-37. Additional MSRs Supported by Intel® Xeon® Processor D with DisplayFamily_DisplayModel 06_56H Register Address Hex Dec 1ACH 428 Register Name / Bit Fields MSR_TURBO_RATIO_LIMIT3 Scope Package Bit Description Config Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0. RW if MSR_PLATFORM_INFO.[28] = 1. 62:0 Package Reserved 63 Package Semaphore for Turbo Ratio Limit Configuration If 1, the processor uses override configuration1 specified in MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1. If 0, the processor uses factory-set configuration (Default). 286H 646 IA32_MC6_CTL2 Package See Table 2-2. 287H 647 IA32_MC7_CTL2 Package See Table 2-2. 289H 649 IA32_MC9_CTL2 Package See Table 2-2. 28AH 650 IA32_MC10_CTL2 Package See Table 2-2. 291H 657 IA32_MC17_CTL2 Package See Table 2-2. 292H 658 IA32_MC18_CTL2 Package See Table 2-2. 293H 659 IA32_MC19_CTL2 Package See Table 2-2. 2-260 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-37. Additional MSRs Supported by Intel® Xeon® Processor D with DisplayFamily_DisplayModel 06_56H Register Address Register Name / Bit Fields Scope Hex Dec 418H 1048 IA32_MC6_CTL Package 419H 1049 IA32_MC6_STATUS Package 41AH 1050 IA32_MC6_ADDR Package 41BH 1051 IA32_MC6_MISC Package 41CH 1052 IA32_MC7_CTL Package 41DH 1053 IA32_MC7_STATUS Package 41EH 1054 IA32_MC7_ADDR Package 41FH 1055 IA32_MC7_MISC Package 424H 1060 IA32_MC9_CTL Package 425H 1061 IA32_MC9_STATUS Package 426H 1062 IA32_MC9_ADDR Package 427H 1063 IA32_MC9_MISC Package 428H 1064 IA32_MC10_CTL Package 429H 1065 IA32_MC10_STATUS Package 42AH 1066 IA32_MC10_ADDR Package 42BH 1067 IA32_MC10_MISC Package 444H 1092 IA32_MC17_CTL Package 445H 1093 IA32_MC17_STATUS Package 446H 1094 IA32_MC17_ADDR Package 447H 1095 IA32_MC17_MISC Package 448H 1096 IA32_MC18_CTL Package 449H 1097 IA32_MC18_STATUS Package 44AH 1098 IA32_MC18_ADDR Package 44BH 1099 IA32_MC18_MISC Package 44CH 1100 IA32_MC19_CTL Package 44DH 1101 IA32_MC19_STATUS Package 44EH 1102 IA32_MC19_ADDR Package 44FH 1103 IA32_MC19_MISC Package Bit Description See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC6 reports MC errors from the integrated I/O module. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC7 reports MC errors from the home agent HA 0. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC9 through MC 10 report MC errors from each channel of the integrated memory controllers. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC9 through MC 10 report MC errors from each channel of the integrated memory controllers. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC17 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9, CBo12, CBo15. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC18 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7, CBo10, CBo13, CBo16. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC19 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8, CBo11, CBo14, CBo17. See Table 2-20, Table 2-29, Table 2-34, and Table 2-36 for other MSR definitions applicable to processors with CPUID signature 06_56H. NOTES: 1. An override configuration lower than the factory-set configuration is always supported. An override configuration higher than the factory-set configuration is dependent on features specific to the processor and the platform. 2.16.2 Additional MSRs Supported in Intel® Xeon® Processors E5 v4 and E7 v4 Families The MSRs listed in Table 2-37 are available to Intel® Xeon® Processor E5 v4 and E7 v4 Families (CPUID DisplayFamily_DisplayModel = 06_4FH). The Intel® Xeon® processor E5 v4 family is based on the Broadwell Vol. 4 2-261 MODEL-SPECIFIC REGISTERS (MSRS) microarchitecture and supports the MSR interfaces listed in Table 2-20, Table 2-21, Table 2-29, Table 2-34, Table 2-36, and Table 2-38. Table 2-38. Additional MSRs Supported by Intel® Xeon® Processors with DisplayFamily_DisplayModel 06_4FH Register Address Hex Dec 1ACH 428 Register Name / Bit Fields MSR_TURBO_RATIO_LIMIT3 Scope Package Bit Description Config Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0. RW if MSR_PLATFORM_INFO.[28] = 1. 62:0 Package Reserved 63 Package Semaphore for Turbo Ratio Limit Configuration If 1, the processor uses override configuration1 specified in MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1 and MSR_TURBO_RATIO_LIMIT2. If 0, the processor uses factory-set configuration (Default). 285H 645 IA32_MC5_CTL2 Package See Table 2-2. 286H 646 IA32_MC6_CTL2 Package See Table 2-2. 287H 647 IA32_MC7_CTL2 Package See Table 2-2. 288H 648 IA32_MC8_CTL2 Package See Table 2-2. 289H 649 IA32_MC9_CTL2 Package See Table 2-2. 28AH 650 IA32_MC10_CTL2 Package See Table 2-2. 28BH 651 IA32_MC11_CTL2 Package See Table 2-2. 28CH 652 IA32_MC12_CTL2 Package See Table 2-2. 28DH 653 IA32_MC13_CTL2 Package See Table 2-2. 28EH 654 IA32_MC14_CTL2 Package See Table 2-2. 28FH 655 IA32_MC15_CTL2 Package See Table 2-2. 290H 656 IA32_MC16_CTL2 Package See Table 2-2. 291H 657 IA32_MC17_CTL2 Package See Table 2-2. 292H 658 IA32_MC18_CTL2 Package See Table 2-2. 293H 659 IA32_MC19_CTL2 Package See Table 2-2. 294H 660 IA32_MC20_CTL2 Package See Table 2-2. 295H 661 IA32_MC21_CTL2 Package See Table 2-2. 414H 1044 IA32_MC5_CTL Package 415H 1045 IA32_MC5_STATUS Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. 416H 1046 IA32_MC5_ADDR Package 417H 1047 IA32_MC5_MISC Package 418H 1048 IA32_MC6_CTL Package 419H 1049 IA32_MC6_STATUS Package 41AH 1050 IA32_MC6_ADDR Package 41BH 1051 IA32_MC6_MISC Package 2-262 Vol. 4 Bank MC5 reports MC errors from the Intel QPI 0 module. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC6 reports MC errors from the integrated I/O module. MODEL-SPECIFIC REGISTERS (MSRS) Table 2-38. Additional MSRs Supported by Intel® Xeon® Processors with DisplayFamily_DisplayModel 06_4FH Register Address Register Name / Bit Fields Scope Hex Dec 41CH 1052 IA32_MC7_CTL Package 41DH 1053 IA32_MC7_STATUS Package 41EH 1054 IA32_MC7_ADDR Package 41FH 1055 IA32_MC7_MISC Package 420H 1056 IA32_MC8_CTL Package 421H 1057 IA32_MC8_STATUS Package 422H 1058 IA32_MC8_ADDR Package 423H 1059 IA32_MC8_MISC Package 424H 1060 IA32_MC9_CTL Package 425H 1061 IA32_MC9_STATUS Package 426H 1062 IA32_MC9_ADDR Package 427H 1063 IA32_MC9_MISC Package 428H 1064 IA32_MC10_CTL Package 429H 1065 IA32_MC10_STATUS Package 42AH 1066 IA32_MC10_ADDR Package 42BH 1067 IA32_MC10_MISC Package 42CH 1068 IA32_MC11_CTL Package 42DH 1069 IA32_MC11_STATUS Package 42EH 1070 IA32_MC11_ADDR Package 42FH 1071 IA32_MC11_MISC Package 430H 1072 IA32_MC12_CTL Package 431H 1073 IA32_MC12_STATUS Package 432H 1074 IA32_MC12_ADDR Package 433H 1075 IA32_MC12_MISC Package 434H 1076 IA32_MC13_CTL Package 435H 1077 IA32_MC13_STATUS Package 436H 1078 IA32_MC13_ADDR Package 437H 1079 IA32_MC13_MISC Package 438H 1080 IA32_MC14_CTL Package 439H 1081 IA32_MC14_STATUS Package 43AH 1082 IA32_MC14_ADDR Package 43BH 1083 IA32_MC14_MISC Package 43CH 1084 IA32_MC15_CTL Package 43DH 1085 IA32_MC15_STATUS Package 43EH 1086 IA32_MC15_ADDR Package 43FH 1087 IA32_MC15_MISC Package Bit Description See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC7 reports MC errors from the home agent HA 0. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC8 reports MC errors from the home agent HA 1. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers. Vol. 4 2-263 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-38. Additional MSRs Supported by Intel® Xeon® Processors with DisplayFamily_DisplayModel 06_4FH Register Address Register Name / Bit Fields Scope Hex Dec 440H 1088 IA32_MC16_CTL Package 441H 1089 IA32_MC16_STATUS Package 442H 1090 IA32_MC16_ADDR Package 443H 1091 IA32_MC16_MISC Package 444H 1092 IA32_MC17_CTL Package 445H 1093 IA32_MC17_STATUS Package 446H 1094 IA32_MC17_ADDR Package 447H 1095 IA32_MC17_MISC Package 448H 1096 IA32_MC18_CTL Package 449H 1097 IA32_MC18_STATUS Package 44AH 1098 IA32_MC18_ADDR Package 44BH 1099 IA32_MC18_MISC Package 44CH 1100 IA32_MC19_CTL Package 44DH 1101 IA32_MC19_STATUS Package 44EH 1102 IA32_MC19_ADDR Package 44FH 1103 IA32_MC19_MISC Package 450H 1104 IA32_MC20_CTL Package 451H 1105 IA32_MC20_STATUS Package 452H 1106 IA32_MC20_ADDR Package 453H 1107 IA32_MC20_MISC Package 454H 1108 IA32_MC21_CTL Package 455H 1109 IA32_MC21_STATUS Package 456H 1110 IA32_MC21_ADDR Package 457H 1111 IA32_MC21_MISC Package C81H 3201 IA32_L3_QOS_CFG Package Bit Description See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC17 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9, CBo12, CBo15. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC18 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7, CBo10, CBo13, CBo16. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC19 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8, CBo11, CBo14, CBo17. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC20 reports MC errors from the Intel QPI 1 module. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC21 reports MC errors from the Intel QPI 2 module. Cache Allocation Technology Configuration (R/W) 0 CAT Enable. Set 1 to enable Cache Allocation Technology. 63:1 Reserved See Table 2-20, Table 2-21, Table 2-29, and Table 2-30 for other MSR definitions applicable to processors with CPUID signature 06_45H. NOTES: 1. An override configuration lower than the factory-set configuration is always supported. An override configuration higher than the factory-set configuration is dependent on features specific to the processor and the platform. 2-264 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) 2.17 MSRS IN THE 6TH GENERATION, 7TH GENERATION, 8TH GENERATION, AND 9TH GENERATION INTEL® CORE™ PROCESSORS, INTEL® XEON® PROCESSOR SCALABLE FAMILY, 8TH GENERATION INTEL® CORE™ I3 PROCESSORS, AND INTEL® XEON® E PROCESSORS 6th generation Intel® Core™ processors and the Intel® Xeon® Processor Scalable Family are based on the Skylake microarchitecture and have CPUID DisplayFamily_DisplayModel signatures of 06_4EH, 06_5EH, and 06_55H. 7th generation Intel® Core™ processors are based on the Kaby Lake microarchitecture, 8th generation and 9th generation Intel® Core™ processors and Intel® Xeon® E processors are based on the Coffee Lake microarchitecture; these processors have CPUID DisplayFamily_DisplayModel signatures of 06_8EH and 06_9EH. 8th generation Intel® Core™ i3 processors are based on Cannon Lake microarchitecture and have a CPUID DisplayFamily_DisplayModel signature of 06_66H. These processors support the MSR interfaces listed in Table 2-20, Table 2-21, Table 2-25, Table 2-29, Table 2-35, Table 2-39, and Table 2-40. For an MSR listed in Table 2-39 that also appears in the model-specific tables of prior generations, Table 2-39 supercede prior generation tables. The notation of “Platform” in the Scope column (with respect to MSR_PLATFORM_ENERGY_COUNTER and MSR_PLATFORM_POWER_LIMIT) is limited to the power-delivery domain and the specifics of the power delivery integration may vary by platform vendor’s implementation. Table 2-39. Additional MSRs Supported by 6th Generation Intel® Core™ Processors and the Intel® Xeon® Processor Scalable Family Based on Skylake Microarchitecture, 7th Generation Intel® Core™ Processors Based on Kaby Lake Microarchitecture, 8th Generation and 9th Generation Intel® Core™ Processors and Intel® Xeon® E Processors Based on Coffee Lake Microarchitecture, and 8th Generation Intel® Core™ i3 Processors Based on Cannon Lake Microarchitecture Register Address Hex Dec 3AH 58 Register Name / Bit Fields IA32_FEATURE_CONTROL Scope Thread Bit Description Control Features in Intel 64 Processor (R/W) See Table 2-2. FEH 254 IA32_MTRRCAP Thread MTRR Capability (RO, Architectural) See Table 2-2 19CH 412 IA32_THERM_STATUS Core Thermal Monitor Status (R/W) See Table 2-2. 0 Thermal Status (RO) See Table 2-2. 1 Thermal Status Log (R/WC0) See Table 2-2. 2 PROTCHOT # or FORCEPR# Status (RO) See Table 2-2. 3 PROTCHOT # or FORCEPR# Log (R/WC0) See Table 2-2. 4 Critical Temperature Status (RO) See Table 2-2. 5 Critical Temperature Status Log (R/WC0) See Table 2-2. 6 Thermal threshold #1 Status (RO) See Table 2-2. Vol. 4 2-265 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-39. Additional MSRs Supported by 6th Generation Intel® Core™ Processors and the Intel® Xeon® Processor Scalable Family Based on Skylake Microarchitecture, 7th Generation Intel® Core™ Processors Based on Kaby Lake Microarchitecture, 8th Generation and 9th Generation Intel® Core™ Processors and Intel® Xeon® E Processors Based on Coffee Lake Microarchitecture, and 8th Generation Intel® Core™ i3 Processors Based on Cannon Lake Microarchitecture Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 7 Thermal threshold #1 Log (R/WC0) See Table 2-2. 8 Thermal Threshold #2 Status (RO) See Table 2-2. 9 Thermal Threshold #2 Log (R/WC0) See Table 2-2. 10 Power Limitation Status (RO) See Table 2-2. 11 Power Limitation Log (R/WC0) See Table 2-2. 12 Current Limit Status (RO) See Table 2-2. 13 Current Limit Log (R/WC0) See Table 2-2. 14 Cross Domain Limit Status (RO) See Table 2-2. 15 Cross Domain Limit Log (R/WC0) See Table 2-2. 22:16 Digital Readout (RO) See Table 2-2. 26:23 Reserved 30:27 Resolution in Degrees Celsius (RO) See Table 2-2. 31 Reading Valid (RO) See Table 2-2. 63:32 1ADH 429 MSR_TURBO_RATIO_LIMIT Reserved Package Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, RW if MSR_PLATFORM_INFO.[28] = 1 7:0 Package Maximum Ratio Limit for 1C Maximum turbo ratio limit of 1 core active. 15:8 Package Maximum Ratio Limit for 2C Maximum turbo ratio limit of 2 core active. 23:16 Package Maximum Ratio Limit for 3C Maximum turbo ratio limit of 3 core active. 2-266 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-39. Additional MSRs Supported by 6th Generation Intel® Core™ Processors and the Intel® Xeon® Processor Scalable Family Based on Skylake Microarchitecture, 7th Generation Intel® Core™ Processors Based on Kaby Lake Microarchitecture, 8th Generation and 9th Generation Intel® Core™ Processors and Intel® Xeon® E Processors Based on Coffee Lake Microarchitecture, and 8th Generation Intel® Core™ i3 Processors Based on Cannon Lake Microarchitecture Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 31:24 Package Maximum Ratio Limit for 4C Maximum turbo ratio limit of 4 core active. 63:32 1C9H 457 MSR_LASTBRANCH_TOS Reserved Thread Last Branch Record Stack TOS (R/W) Contains an index (bits 0-4) that points to the MSR containing the most recent branch record. 1FCH 508 MSR_POWER_CTL Core Power Control Register See http://biosbits.org. 0 1 Reserved Package C1E Enable (R/W) When set to ‘1’, will enable the CPU to switch to the Minimum Enhanced Intel SpeedStep Technology operating point when all execution cores enter MWAIT (C1). 18:2 Reserved 19 Disable Race to Halt Optimization (R/W) Setting this bit disables the Race to Halt optimization and avoids this optimization limitation to execute below the most efficient frequency ratio. Default value is 0 for processors that support Race to Halt optimization. Default value is 1 for processors that do not support Race to Halt optimization. 20 Disable Energy Efficiency Optimization (R/W) Setting this bit disables the P-States energy efficiency optimization. Default value is 0. Disable/enable the energy efficiency optimization in P-State legacy mode (when IA32_PM_ENABLE[HWP_ENABLE] = 0), has an effect only in the turbo range or into PERF_MIN_CTL value if it is not zero set. In HWP mode (IA32_PM_ENABLE[HWP_ENABLE] == 1), has an effect between the OS desired or OS maximize to the OS minimize performance setting. 63:21 300H 768 MSR_SGXOWNEREPOCH0 Reserved Package Lower 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in the package. 63:0 Lower 64 bits of an 128-bit external entropy value for key derivation of an enclave. Vol. 4 2-267 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-39. Additional MSRs Supported by 6th Generation Intel® Core™ Processors and the Intel® Xeon® Processor Scalable Family Based on Skylake Microarchitecture, 7th Generation Intel® Core™ Processors Based on Kaby Lake Microarchitecture, 8th Generation and 9th Generation Intel® Core™ Processors and Intel® Xeon® E Processors Based on Coffee Lake Microarchitecture, and 8th Generation Intel® Core™ i3 Processors Based on Cannon Lake Microarchitecture Register Address Hex Dec 301H 768 Register Name / Bit Fields MSR_SGXOWNEREPOCH1 Scope Package Bit Description Upper 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in the package. 38EH 910 63:0 Upper 64 bits of an 128-bit external entropy value for key derivation of an enclave. IA32_PERF_GLOBAL_STATUS See Table 2-2. See Section 18.2.4, “Architectural Performance Monitoring Version 4.” 0 Thread Ovf_PMC0 1 Thread Ovf_PMC1 2 Thread Ovf_PMC2 3 Thread Ovf_PMC3 4 Thread Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4) 5 Thread Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5) 6 Thread Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6) 7 Thread Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7) 31:8 Reserved 32 Thread Ovf_FixedCtr0 33 Thread Ovf_FixedCtr1 34 Thread Ovf_FixedCtr2 54:35 55 Reserved Thread 57:56 390H 2-268 Vol. 4 912 Trace_ToPA_PMI Reserved 58 Thread LBR_Frz 59 Thread CTR_Frz 60 Thread ASCI 61 Thread Ovf_Uncore 62 Thread Ovf_BufDSSAVE 63 Thread CondChgd IA32_PERF_GLOBAL_STATUS_RESET See Table 2-2. See Section 18.2.4, “Architectural Performance Monitoring Version 4.” 0 Thread Set 1 to clear Ovf_PMC0. 1 Thread Set 1 to clear Ovf_PMC1. 2 Thread Set 1 to clear Ovf_PMC2. 3 Thread Set 1 to clear Ovf_PMC3. MODEL-SPECIFIC REGISTERS (MSRS) Table 2-39. Additional MSRs Supported by 6th Generation Intel® Core™ Processors and the Intel® Xeon® Processor Scalable Family Based on Skylake Microarchitecture, 7th Generation Intel® Core™ Processors Based on Kaby Lake Microarchitecture, 8th Generation and 9th Generation Intel® Core™ Processors and Intel® Xeon® E Processors Based on Coffee Lake Microarchitecture, and 8th Generation Intel® Core™ i3 Processors Based on Cannon Lake Microarchitecture Register Address Hex Register Name / Bit Fields Scope Dec 4 Thread Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4). 5 Thread Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5). 6 Thread Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6). 7 Thread Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7). 31:8 Reserved 32 Thread Set 1 to clear Ovf_FixedCtr0. 33 Thread Set 1 to clear Ovf_FixedCtr1. 34 Thread Set 1 to clear Ovf_FixedCtr2. 54:35 55 Reserved Thread 57:56 391H Bit Description 913 Set 1 to clear Trace_ToPA_PMI. Reserved 58 Thread Set 1 to clear LBR_Frz. 59 Thread Set 1 to clear CTR_Frz. 60 Thread Set 1 to clear ASCI. 61 Thread Set 1 to clear Ovf_Uncore. 62 Thread Set 1 to clear Ovf_BufDSSAVE. 63 Thread Set 1 to clear CondChgd. IA32_PERF_GLOBAL_STATUS_SET See Table 2-2. See Section 18.2.4, “Architectural Performance Monitoring Version 4.” 0 Thread Set 1 to cause Ovf_PMC0 = 1. 1 Thread Set 1 to cause Ovf_PMC1 = 1. 2 Thread Set 1 to cause Ovf_PMC2 = 1. 3 Thread Set 1 to cause Ovf_PMC3 = 1. 4 Thread Set 1 to cause Ovf_PMC4=1 (if CPUID.0AH:EAX[15:8] > 4). 5 Thread Set 1 to cause Ovf_PMC5=1 (if CPUID.0AH:EAX[15:8] > 5). 6 Thread Set 1 to cause Ovf_PMC6=1 (if CPUID.0AH:EAX[15:8] > 6). 7 Thread Set 1 to cause Ovf_PMC7=1 (if CPUID.0AH:EAX[15:8] > 7). 31:8 Reserved 32 Thread Set 1 to cause Ovf_FixedCtr0 = 1. 33 Thread Set 1 to cause Ovf_FixedCtr1 = 1. 34 Thread Set 1 to cause Ovf_FixedCtr2 = 1. Vol. 4 2-269 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-39. Additional MSRs Supported by 6th Generation Intel® Core™ Processors and the Intel® Xeon® Processor Scalable Family Based on Skylake Microarchitecture, 7th Generation Intel® Core™ Processors Based on Kaby Lake Microarchitecture, 8th Generation and 9th Generation Intel® Core™ Processors and Intel® Xeon® E Processors Based on Coffee Lake Microarchitecture, and 8th Generation Intel® Core™ i3 Processors Based on Cannon Lake Microarchitecture Register Address Hex Register Name / Bit Fields Scope Dec 54:35 55 Reserved Thread 57:56 Reserved Thread Set 1 to cause LBR_Frz = 1. 59 Thread Set 1 to cause CTR_Frz = 1. 60 Thread Set 1 to cause ASCI = 1. 61 Thread Set 1 to cause Ovf_Uncore. 62 Thread Set 1 to cause Ovf_BufDSSAVE. 63 Reserved See Table 2-2. 913 IA32_PERF_GLOBAL_INUSE 3F7H 1015 MSR_PEBS_FRONTEND 1280 Set 1 to cause Trace_ToPA_PMI = 1. 58 392H 500H Bit Description Thread FrontEnd Precise Event Condition Select (R/W) 2:0 Event Code Select 3 Reserved 4 Event Code Select High 7:5 Reserved 19:8 IDQ_Bubble_Length Specifier 22:20 IDQ_Bubble_Width Specifier 63:23 Reserved IA32_SGX_SVN_STATUS Thread 0 Status and SVN Threshold of SGX Support for ACM (RO) Lock See Section 41.11.3, “Interactions with Authenticated Code Modules (ACMs)”. 15:1 Reserved 23:16 SGX_SVN_SINIT See Section 41.11.3, “Interactions with Authenticated Code Modules (ACMs)”. 63:24 560H 1376 IA32_RTIT_OUTPUT_BASE Reserved Thread Trace Output Base Register (R/W) See Table 2-2. 561H 1377 IA32_RTIT_OUTPUT_MASK_PTRS Thread Trace Output Mask Pointers Register (R/W) See Table 2-2. 570H 2-270 Vol. 4 1392 IA32_RTIT_CTL Thread Trace Control Register (R/W) 0 TraceEn 1 CYCEn 2 OS MODEL-SPECIFIC REGISTERS (MSRS) Table 2-39. Additional MSRs Supported by 6th Generation Intel® Core™ Processors and the Intel® Xeon® Processor Scalable Family Based on Skylake Microarchitecture, 7th Generation Intel® Core™ Processors Based on Kaby Lake Microarchitecture, 8th Generation and 9th Generation Intel® Core™ Processors and Intel® Xeon® E Processors Based on Coffee Lake Microarchitecture, and 8th Generation Intel® Core™ i3 Processors Based on Cannon Lake Microarchitecture Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 3 User 6:4 Reserved, must be zero. 7 CR3 filter 8 ToPA Writing 0 will #GP if also setting TraceEn. 571H 572H 580H 1393 1394 1408 9 MTCEn 10 TSCEn 11 DisRETC 12 Reserved, must be zero. 13 BranchEn 17:14 MTCFreq 18 Reserved, must be zero. 22:19 CYCThresh 23 Reserved, must be zero. 27:24 PSBFreq 31:28 Reserved, must be zero. 35:32 ADDR0_CFG 39:36 ADDR1_CFG 63:40 Reserved, must be zero. IA32_RTIT_STATUS Thread Tracing Status Register (R/W) 0 FilterEn, writes ignored. 1 ContexEn, writes ignored. 2 TriggerEn, writes ignored. 3 Reserved 4 Error (R/W) 5 Stopped 31:6 Reserved, must be zero. 48:32 PacketByteCnt 63:49 Reserved, must be zero. IA32_RTIT_CR3_MATCH Thread Trace Filter CR3 Match Register (R/W) 4:0 Reserved 63:5 CR3[63:5] value to match IA32_RTIT_ADDR0_A 63:0 Thread Region 0 Start Address (R/W) See Table 2-2. Vol. 4 2-271 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-39. Additional MSRs Supported by 6th Generation Intel® Core™ Processors and the Intel® Xeon® Processor Scalable Family Based on Skylake Microarchitecture, 7th Generation Intel® Core™ Processors Based on Kaby Lake Microarchitecture, 8th Generation and 9th Generation Intel® Core™ Processors and Intel® Xeon® E Processors Based on Coffee Lake Microarchitecture, and 8th Generation Intel® Core™ i3 Processors Based on Cannon Lake Microarchitecture Register Address Hex Dec 581H 1409 Register Name / Bit Fields IA32_RTIT_ADDR0_B Scope Thread 63:0 582H 1410 IA32_RTIT_ADDR1_A 1411 IA32_RTIT_ADDR1_B Thread 1593 MSR_PP0_ENERGY_STATUS Region 1 Start Address (R/W) See Table 2-2. Thread 63:0 639H Region 0 End Address (R/W) See Table 2-2. 63:0 583H Bit Description Region 1 End Address (R/W) See Table 2-2. Package PP0 Energy Status (R/O) See Section 14.9.4, “PP0/PP1 RAPL Domains.” 64DH 1613 MSR_PLATFORM_ENERGY_COUNTER Platform* Platform Energy Counter (R/O) This MSR is valid only if both platform vendor hardware implementation and BIOS enablement support it. This MSR will read 0 if not valid. 64EH 1614 31:0 Total energy consumed by all devices in the platform that receive power from integrated power delivery mechanism, included platform devices are processor cores, SOC, memory, add-on or peripheral devices that get powered directly from the platform power delivery means. The energy units are specified in the MSR_RAPL_POWER_UNIT.Enery_Status_Unit. 63:32 Reserved MSR_PPERF Thread 63:0 64FH 1615 MSR_CORE_PERF_LIMIT_REASONS Productive Performance Count (R/O) Hardware’s view of workload scalability. See Section 14.4.5.1. Package Indicator of Frequency Clipping in Processor Cores (R/W) (Frequency refers to processor core frequency.) 0 PROCHOT Status (R0) When set, frequency is reduced below the operating system request due to assertion of external PROCHOT. 1 Thermal Status (R0) When set, frequency is reduced below the operating system request due to a thermal event. 3:2 Reserved 4 Residency State Regulation Status (R0) When set, frequency is reduced below the operating system request due to residency state regulation limit. 2-272 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-39. Additional MSRs Supported by 6th Generation Intel® Core™ Processors and the Intel® Xeon® Processor Scalable Family Based on Skylake Microarchitecture, 7th Generation Intel® Core™ Processors Based on Kaby Lake Microarchitecture, 8th Generation and 9th Generation Intel® Core™ Processors and Intel® Xeon® E Processors Based on Coffee Lake Microarchitecture, and 8th Generation Intel® Core™ i3 Processors Based on Cannon Lake Microarchitecture Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 5 Running Average Thermal Limit Status (R0) When set, frequency is reduced below the operating system request due to Running Average Thermal Limit (RATL). 6 VR Therm Alert Status (R0) When set, frequency is reduced below the operating system request due to a thermal alert from a processor Voltage Regulator (VR). 7 VR Therm Design Current Status (R0) When set, frequency is reduced below the operating system request due to VR thermal design current limit. 8 Other Status (R0) When set, frequency is reduced below the operating system request due to electrical or other constraints. 9 Reserved 10 Package/Platform-Level Power Limiting PL1 Status (R0) When set, frequency is reduced below the operating system request due to package/platform-level power limiting PL1. 11 Package/Platform-Level PL2 Power Limiting Status (R0) When set, frequency is reduced below the operating system request due to package/platform-level power limiting PL2/PL3. 12 Max Turbo Limit Status (R0) When set, frequency is reduced below the operating system request due to multi-core turbo limits. 13 Turbo Transition Attenuation Status (R0) When set, frequency is reduced below the operating system request due to Turbo transition attenuation. This prevents performance degradation due to frequent operating ratio changes. 15:14 Reserved 16 PROCHOT Log When set, indicates that the PROCHOT Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. Vol. 4 2-273 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-39. Additional MSRs Supported by 6th Generation Intel® Core™ Processors and the Intel® Xeon® Processor Scalable Family Based on Skylake Microarchitecture, 7th Generation Intel® Core™ Processors Based on Kaby Lake Microarchitecture, 8th Generation and 9th Generation Intel® Core™ Processors and Intel® Xeon® E Processors Based on Coffee Lake Microarchitecture, and 8th Generation Intel® Core™ i3 Processors Based on Cannon Lake Microarchitecture Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 17 Thermal Log When set, indicates that the Thermal Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 19:18 20 Reserved. Residency State Regulation Log When set, indicates that the Residency State Regulation Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 21 Running Average Thermal Limit Log When set, indicates that the RATL Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 22 VR Therm Alert Log When set, indicates that the VR Therm Alert Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 23 VR Thermal Design Current Log When set, indicates that the VR TDC Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 24 Other Log When set, indicates that the Other Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 25 Reserved 26 Package/Platform-Level PL1 Power Limiting Log When set, indicates that the Package or Platform Level PL1 Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 2-274 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-39. Additional MSRs Supported by 6th Generation Intel® Core™ Processors and the Intel® Xeon® Processor Scalable Family Based on Skylake Microarchitecture, 7th Generation Intel® Core™ Processors Based on Kaby Lake Microarchitecture, 8th Generation and 9th Generation Intel® Core™ Processors and Intel® Xeon® E Processors Based on Coffee Lake Microarchitecture, and 8th Generation Intel® Core™ i3 Processors Based on Cannon Lake Microarchitecture Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 27 Package/Platform-Level PL2 Power Limiting Log When set, indicates that the Package or Platform Level PL2/PL3 Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 28 Max Turbo Limit Log When set, indicates that the Max Turbo Limit Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 29 Turbo Transition Attenuation Log When set, indicates that the Turbo Transition Attenuation Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 63:30 652H 1618 MSR_PKG_HDC_CONFIG Reserved Package 2:0 HDC Configuration (R/W) PKG_Cx_Monitor Configures Package Cx state threshold for MSR_PKG_HDC_DEEP_RESIDENCY. 63: 3 653H 1619 MSR_CORE_HDC_RESIDENCY Reserved Core 63:0 655H 1621 MSR_PKG_HDC_SHALLOW_RESIDENCY Core_Cx_Duty_Cycle_Cnt Package 63:0 656H 1622 MSR_PKG_HDC_DEEP_RESIDENCY 1624 MSR_WEIGHTED_CORE_C0 Package 1625 MSR_ANY_CORE_C0 63:0 Package Cx HDC Idle Residency (R/O) Pkg_Cx_Duty_Cycle_Cnt Package 63:0 659H Accumulate the cycles the package was in C2 state and at least one logical processor was in forced idle (R/O) Pkg_C2_Duty_Cycle_Cnt 63:0 658H Core HDC Idle Residency (R/O) Core-count Weighted C0 Residency (R/O) Increment at the same rate as the TSC. The increment each cycle is weighted by the number of processor cores in the package that reside in C0. If N cores are simultaneously in C0, then each cycle the counter increments by N. Package Any Core C0 Residency (R/O) Increment at the same rate as the TSC. The increment each cycle is one if any processor core in the package is in C0. Vol. 4 2-275 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-39. Additional MSRs Supported by 6th Generation Intel® Core™ Processors and the Intel® Xeon® Processor Scalable Family Based on Skylake Microarchitecture, 7th Generation Intel® Core™ Processors Based on Kaby Lake Microarchitecture, 8th Generation and 9th Generation Intel® Core™ Processors and Intel® Xeon® E Processors Based on Coffee Lake Microarchitecture, and 8th Generation Intel® Core™ i3 Processors Based on Cannon Lake Microarchitecture Register Address Hex Dec 65AH 1626 Register Name / Bit Fields MSR_ANY_GFXE_C0 Scope Package 63:0 65BH 1627 MSR_CORE_GFXE_OVERLAP_C0 1628 MSR_PLATFORM_POWER_LIMIT Any Graphics Engine C0 Residency (R/O) Increment at the same rate as the TSC. The increment each cycle is one if any processor graphic device’s compute engines are in C0. Package 63:0 65CH Bit Description Core and Graphics Engine Overlapped C0 Residency (R/O) Increment at the same rate as the TSC. The increment each cycle is one if at least one compute engine of the processor graphics is in C0 and at least one processor core in the package is also in C0. Platform* Platform Power Limit Control (R/W-L) Allows platform BIOS to limit power consumption of the platform devices to the specified values. The Long Duration power consumption is specified via Platform_Power_Limit_1 and Platform_Power_Limit_1_Time. The Short Duration power consumption limit is specified via the Platform_Power_Limit_2 with duration chosen by the processor. The processor implements an exponential-weighted algorithm in the placement of the time windows. 14:0 Platform Power Limit #1 Average Power limit value which the platform must not exceed over a time window as specified by Power_Limit_1_TIME field. The default value is the Thermal Design Power (TDP) and varies with product skus. The unit is specified in MSR_RAPLPOWER_UNIT. 15 Enable Platform Power Limit #1 When set, enables the processor to apply control policy such that the platform power does not exceed Platform Power limit #1 over the time window specified by Power Limit #1 Time Window. 16 Platform Clamping Limitation #1 When set, allows the processor to go below the OS requested P states in order to maintain the power below specified Platform Power Limit #1 value. This bit is writeable only when CPUID (EAX=6):EAX[4] is set. 2-276 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-39. Additional MSRs Supported by 6th Generation Intel® Core™ Processors and the Intel® Xeon® Processor Scalable Family Based on Skylake Microarchitecture, 7th Generation Intel® Core™ Processors Based on Kaby Lake Microarchitecture, 8th Generation and 9th Generation Intel® Core™ Processors and Intel® Xeon® E Processors Based on Coffee Lake Microarchitecture, and 8th Generation Intel® Core™ i3 Processors Based on Cannon Lake Microarchitecture Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 23:17 Time Window for Platform Power Limit #1 Specifies the duration of the time window over which Platform Power Limit 1 value should be maintained for sustained long duration. This field is made up of two numbers from the following equation: Time Window = (float) ((1+(X/4))*(2^Y)), where: X = POWER_LIMIT_1_TIME[23:22] Y = POWER_LIMIT_1_TIME[21:17] The maximum allowed value in this field is defined in MSR_PKG_POWER_INFO[PKG_MAX_WIN]. The default value is 0DH, The unit is specified in MSR_RAPLPOWER_UNIT[Time Unit]. 31:24 Reserved 46:32 Platform Power Limit #2 Average Power limit value which the platform must not exceed over the Short Duration time window chosen by the processor. The recommended default value is 1.25 times the Long Duration Power Limit (i.e., Platform Power Limit # 1). 47 Enable Platform Power Limit #2 When set, enables the processor to apply control policy such that the platform power does not exceed Platform Power limit #2 over the Short Duration time window. 48 Platform Clamping Limitation #2 When set, allows the processor to go below the OS requested P states in order to maintain the power below specified Platform Power Limit #2 value. 690H 1680 62:49 Reserved 63 Lock. Setting this bit will lock all other bits of this MSR until system RESET. MSR_LASTBRANCH_16_FROM_IP Thread Last Branch Record 16 From IP (R/W) One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains pointers to the source instruction. See also: • Last Branch Record Stack TOS at 1C9H. • Section 17.12. 691H 1681 MSR_LASTBRANCH_17_FROM_IP Thread Last Branch Record 17 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 692H 1682 MSR_LASTBRANCH_18_FROM_IP Thread Last Branch Record 18 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. Vol. 4 2-277 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-39. Additional MSRs Supported by 6th Generation Intel® Core™ Processors and the Intel® Xeon® Processor Scalable Family Based on Skylake Microarchitecture, 7th Generation Intel® Core™ Processors Based on Kaby Lake Microarchitecture, 8th Generation and 9th Generation Intel® Core™ Processors and Intel® Xeon® E Processors Based on Coffee Lake Microarchitecture, and 8th Generation Intel® Core™ i3 Processors Based on Cannon Lake Microarchitecture Register Address Hex Dec 693H 1683 Register Name / Bit Fields MSR_LASTBRANCH_19_FROM_IP Scope Thread Bit Description Last Branch Record 19From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 694H 1684 MSR_LASTBRANCH_20_FROM_IP Thread Last Branch Record 20 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 695H 1685 MSR_LASTBRANCH_21_FROM_IP Thread Last Branch Record 21 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 696H 1686 MSR_LASTBRANCH_22_FROM_IP Thread Last Branch Record 22 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 697H 1687 MSR_LASTBRANCH_23_FROM_IP Thread Last Branch Record 23 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 698H 1688 MSR_LASTBRANCH_24_FROM_IP Thread Last Branch Record 24 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 699H 1689 MSR_LASTBRANCH_25_FROM_IP Thread Last Branch Record 25 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 69AH 1690 MSR_LASTBRANCH_26_FROM_IP Thread Last Branch Record 26 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 69BH 1691 MSR_LASTBRANCH_27_FROM_IP Thread Last Branch Record 27 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 69CH 1692 MSR_LASTBRANCH_28_FROM_IP Thread Last Branch Record 28 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 69DH 1693 MSR_LASTBRANCH_29_FROM_IP Thread Last Branch Record 29 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 69EH 1694 MSR_LASTBRANCH_30_FROM_IP Thread Last Branch Record 30 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 69FH 1695 MSR_LASTBRANCH_31_FROM_IP Thread Last Branch Record 31 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP. 6B0H 1712 MSR_GRAPHICS_PERF_LIMIT_REASONS Package Indicator of Frequency Clipping in the Processor Graphics (R/W) (Frequency refers to processor graphics frequency.) 0 PROCHOT Status (R0) When set, frequency is reduced due to assertion of external PROCHOT. 1 Thermal Status (R0) When set, frequency is reduced due to a thermal event. 4:2 2-278 Vol. 4 Reserved. MODEL-SPECIFIC REGISTERS (MSRS) Table 2-39. Additional MSRs Supported by 6th Generation Intel® Core™ Processors and the Intel® Xeon® Processor Scalable Family Based on Skylake Microarchitecture, 7th Generation Intel® Core™ Processors Based on Kaby Lake Microarchitecture, 8th Generation and 9th Generation Intel® Core™ Processors and Intel® Xeon® E Processors Based on Coffee Lake Microarchitecture, and 8th Generation Intel® Core™ i3 Processors Based on Cannon Lake Microarchitecture Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 5 Running Average Thermal Limit Status (R0) When set, frequency is reduced due to running average thermal limit. 6 VR Therm Alert Status (R0) When set, frequency is reduced due to a thermal alert from a processor Voltage Regulator. 7 VR Thermal Design Current Status (R0) When set, frequency is reduced due to VR TDC limit. 8 Other Status (R0) When set, frequency is reduced due to electrical or other constraints. 9 Reserved 10 Package/Platform-Level Power Limiting PL1 Status (R0) When set, frequency is reduced due to package/platform-level power limiting PL1. 11 Package/Platform-Level PL2 Power Limiting Status (R0) When set, frequency is reduced due to package/platform-level power limiting PL2/PL3. 12 Inefficient Operation Status (R0) When set, processor graphics frequency is operating below target frequency. 15:13 16 Reserved PROCHOT Log When set, indicates that the PROCHOT Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 17 Thermal Log When set, indicates that the Thermal Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 20:18 Reserved. 21 Running Average Thermal Limit Log When set, indicates that the RATL Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. Vol. 4 2-279 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-39. Additional MSRs Supported by 6th Generation Intel® Core™ Processors and the Intel® Xeon® Processor Scalable Family Based on Skylake Microarchitecture, 7th Generation Intel® Core™ Processors Based on Kaby Lake Microarchitecture, 8th Generation and 9th Generation Intel® Core™ Processors and Intel® Xeon® E Processors Based on Coffee Lake Microarchitecture, and 8th Generation Intel® Core™ i3 Processors Based on Cannon Lake Microarchitecture Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 22 VR Therm Alert Log When set, indicates that the VR Therm Alert Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 23 VR Thermal Design Current Log When set, indicates that the VR Therm Alert Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 24 Other Log When set, indicates that the OTHER Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 25 Reserved 26 Package/Platform-Level PL1 Power Limiting Log When set, indicates that the Package/Platform Level PL1 Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 27 Package/Platform-Level PL2 Power Limiting Log When set, indicates that the Package/Platform Level PL2 Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 28 Inefficient Operation Log When set, indicates that the Inefficient Operation Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 63:29 6B1H 1713 MSR_RING_PERF_LIMIT_REASONS Reserved Package Indicator of Frequency Clipping in the Ring Interconnect (R/W) (Frequency refers to ring interconnect in the uncore.) 0 PROCHOT Status (R0) When set, frequency is reduced due to assertion of external PROCHOT. 2-280 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-39. Additional MSRs Supported by 6th Generation Intel® Core™ Processors and the Intel® Xeon® Processor Scalable Family Based on Skylake Microarchitecture, 7th Generation Intel® Core™ Processors Based on Kaby Lake Microarchitecture, 8th Generation and 9th Generation Intel® Core™ Processors and Intel® Xeon® E Processors Based on Coffee Lake Microarchitecture, and 8th Generation Intel® Core™ i3 Processors Based on Cannon Lake Microarchitecture Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 1 Thermal Status (R0) When set, frequency is reduced due to a thermal event. 4:2 Reserved 5 Running Average Thermal Limit Status (R0) When set, frequency is reduced due to running average thermal limit. 6 VR Therm Alert Status (R0) When set, frequency is reduced due to a thermal alert from a processor Voltage Regulator. 7 VR Thermal Design Current Status (R0) When set, frequency is reduced due to VR TDC limit. 8 Other Status (R0) When set, frequency is reduced due to electrical or other constraints. 9 Reserved 10 Package/Platform-Level Power Limiting PL1 Status (R0) When set, frequency is reduced due to package/Platform-level power limiting PL1. 11 Package/Platform-Level PL2 Power Limiting Status (R0) When set, frequency is reduced due to package/Platform-level power limiting PL2/PL3. 15:12 Reserved 16 PROCHOT Log When set, indicates that the PROCHOT Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 17 Thermal Log When set, indicates that the Thermal Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 20:18 Reserved Vol. 4 2-281 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-39. Additional MSRs Supported by 6th Generation Intel® Core™ Processors and the Intel® Xeon® Processor Scalable Family Based on Skylake Microarchitecture, 7th Generation Intel® Core™ Processors Based on Kaby Lake Microarchitecture, 8th Generation and 9th Generation Intel® Core™ Processors and Intel® Xeon® E Processors Based on Coffee Lake Microarchitecture, and 8th Generation Intel® Core™ i3 Processors Based on Cannon Lake Microarchitecture Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 21 Running Average Thermal Limit Log When set, indicates that the RATL Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 22 VR Therm Alert Log When set, indicates that the VR Therm Alert Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 23 VR Thermal Design Current Log When set, indicates that the VR Therm Alert Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 24 Other Log When set, indicates that the OTHER Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 25 Reserved 26 Package/Platform-Level PL1 Power Limiting Log When set, indicates that the Package/Platform Level PL1 Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 27 Package/Platform-Level PL2 Power Limiting Log When set, indicates that the Package/Platform Level PL2 Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0. 63:28 6D0H 1744 MSR_LASTBRANCH_16_TO_IP Reserved Thread Last Branch Record 16 To IP (R/W) One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains pointers to the destination instruction. See also: • Last Branch Record Stack TOS at 1C9H. • Section 17.12. 2-282 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-39. Additional MSRs Supported by 6th Generation Intel® Core™ Processors and the Intel® Xeon® Processor Scalable Family Based on Skylake Microarchitecture, 7th Generation Intel® Core™ Processors Based on Kaby Lake Microarchitecture, 8th Generation and 9th Generation Intel® Core™ Processors and Intel® Xeon® E Processors Based on Coffee Lake Microarchitecture, and 8th Generation Intel® Core™ i3 Processors Based on Cannon Lake Microarchitecture Register Address Hex Dec 6D1H 1745 Register Name / Bit Fields MSR_LASTBRANCH_17_TO_IP Scope Thread Bit Description Last Branch Record 17 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6D2H 1746 MSR_LASTBRANCH_18_TO_IP Thread Last Branch Record 18 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6D3H 1747 MSR_LASTBRANCH_19_TO_IP Thread Last Branch Record 19To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6D4H 1748 MSR_LASTBRANCH_20_TO_IP Thread Last Branch Record 20 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6D5H 1749 MSR_LASTBRANCH_21_TO_IP Thread Last Branch Record 21 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6D6H 1750 MSR_LASTBRANCH_22_TO_IP Thread Last Branch Record 22 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6D7H 1751 MSR_LASTBRANCH_23_TO_IP Thread Last Branch Record 23 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6D8H 1752 MSR_LASTBRANCH_24_TO_IP Thread Last Branch Record 24 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6D9H 1753 MSR_LASTBRANCH_25_TO_IP Thread Last Branch Record 25 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6DAH 1754 MSR_LASTBRANCH_26_TO_IP Thread Last Branch Record 26 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6DBH 1755 MSR_LASTBRANCH_27_TO_IP Thread Last Branch Record 27 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6DCH 1756 MSR_LASTBRANCH_28_TO_IP Thread Last Branch Record 28 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6DDH 1757 MSR_LASTBRANCH_29_TO_IP Thread Last Branch Record 29 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6DEH 1758 MSR_LASTBRANCH_30_TO_IP Thread Last Branch Record 30 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 6DFH 1759 MSR_LASTBRANCH_31_TO_IP Thread Last Branch Record 31 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP. 770H 1904 IA32_PM_ENABLE Package See Section 14.4.2, “Enabling HWP”. 771H 1905 IA32_HWP_CAPABILITIES Thread See Section 14.4.3, “HWP Performance Range and Dynamic Capabilities”. 772H 1906 IA32_HWP_REQUEST_PKG Package See Section 14.4.4, “Managing HWP”. 773H 1907 IA32_HWP_INTERRUPT Thread See Section 14.4.6, “HWP Notifications”. 774H 1908 IA32_HWP_REQUEST Thread See Section 14.4.4, “Managing HWP”. Vol. 4 2-283 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-39. Additional MSRs Supported by 6th Generation Intel® Core™ Processors and the Intel® Xeon® Processor Scalable Family Based on Skylake Microarchitecture, 7th Generation Intel® Core™ Processors Based on Kaby Lake Microarchitecture, 8th Generation and 9th Generation Intel® Core™ Processors and Intel® Xeon® E Processors Based on Coffee Lake Microarchitecture, and 8th Generation Intel® Core™ i3 Processors Based on Cannon Lake Microarchitecture Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 7:0 Minimum Performance (R/W) 15:8 Maximum Performance (R/W) 23:16 Desired Performance (R/W) 31:24 Energy/Performance Preference (R/W) 41:32 Activity Window (R/W) 42 Package Control (R/W) 63:43 Reserved 777H 1911 IA32_HWP_STATUS Thread See Section 14.4.5, “HWP Feedback”. D90H 3472 IA32_BNDCFGS Thread See Table 2-2. DA0H 3488 IA32_XSS Thread See Table 2-2. DB0H 3504 IA32_PKG_HDC_CTL Package See Section 14.5.2, “Package level Enabling HDC”. DB1H 3505 IA32_PM_CTL1 Thread See Section 14.5.3, “Logical-Processor Level HDC Control”. DB2H 3506 IA32_THREAD_STALL Thread See Section 14.5.4.1, “IA32_THREAD_STALL”. DC0H 3520 MSR_LBR_INFO_0 Thread Last Branch Record 0 Additional Information (R/W) One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag, TSX-related and elapsed cycle information. See also: • Last Branch Record Stack TOS at 1C9H. • Section 17.9.1, “LBR Stack.” DC1H 3521 MSR_LBR_INFO_1 Thread Last Branch Record 1 Additional Information (R/W) See description of MSR_LBR_INFO_0. DC2H 3522 MSR_LBR_INFO_2 Thread Last Branch Record 2 Additional Information (R/W) See description of MSR_LBR_INFO_0. DC3H 3523 MSR_LBR_INFO_3 Thread Last Branch Record 3 Additional Information (R/W) See description of MSR_LBR_INFO_0. DC4H 3524 MSR_LBR_INFO_4 Thread Last Branch Record 4 Additional Information (R/W) See description of MSR_LBR_INFO_0. DC5H 3525 MSR_LBR_INFO_5 Thread Last Branch Record 5 Additional Information (R/W) See description of MSR_LBR_INFO_0. DC6H 3526 MSR_LBR_INFO_6 Thread Last Branch Record 6 Additional Information (R/W) See description of MSR_LBR_INFO_0. DC7H 3527 MSR_LBR_INFO_7 Thread Last Branch Record 7 Additional Information (R/W) See description of MSR_LBR_INFO_0. DC8H 3528 MSR_LBR_INFO_8 Thread Last Branch Record 8 Additional Information (R/W) See description of MSR_LBR_INFO_0. 2-284 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-39. Additional MSRs Supported by 6th Generation Intel® Core™ Processors and the Intel® Xeon® Processor Scalable Family Based on Skylake Microarchitecture, 7th Generation Intel® Core™ Processors Based on Kaby Lake Microarchitecture, 8th Generation and 9th Generation Intel® Core™ Processors and Intel® Xeon® E Processors Based on Coffee Lake Microarchitecture, and 8th Generation Intel® Core™ i3 Processors Based on Cannon Lake Microarchitecture Register Address Hex Dec DC9H 3529 Register Name / Bit Fields MSR_LBR_INFO_9 Scope Thread Bit Description Last Branch Record 9 Additional Information (R/W) See description of MSR_LBR_INFO_0. DCAH 3530 MSR_LBR_INFO_10 Thread Last Branch Record 10 Additional Information (R/W) See description of MSR_LBR_INFO_0. DCBH 3531 MSR_LBR_INFO_11 Thread Last Branch Record 11 Additional Information (R/W) See description of MSR_LBR_INFO_0. DCCH 3532 MSR_LBR_INFO_12 Thread Last Branch Record 12 Additional Information (R/W) See description of MSR_LBR_INFO_0. DCDH 3533 MSR_LBR_INFO_13 Thread Last Branch Record 13 Additional Information (R/W) See description of MSR_LBR_INFO_0. DCEH 3534 MSR_LBR_INFO_14 Thread Last Branch Record 14 Additional Information (R/W) See description of MSR_LBR_INFO_0. DCFH 3535 MSR_LBR_INFO_15 Thread Last Branch Record 15 Additional Information (R/W) See description of MSR_LBR_INFO_0. DD0H 3536 MSR_LBR_INFO_16 Thread Last Branch Record 16 Additional Information (R/W) See description of MSR_LBR_INFO_0. DD1H 3537 MSR_LBR_INFO_17 Thread Last Branch Record 17 Additional Information (R/W) See description of MSR_LBR_INFO_0. DD2H 3538 MSR_LBR_INFO_18 Thread Last Branch Record 18 Additional Information (R/W) See description of MSR_LBR_INFO_0. DD3H 3539 MSR_LBR_INFO_19 Thread Last Branch Record 19 Additional Information (R/W) See description of MSR_LBR_INFO_0. DD4H 3520 MSR_LBR_INFO_20 Thread Last Branch Record 20 Additional Information (R/W) See description of MSR_LBR_INFO_0. DD5H 3521 MSR_LBR_INFO_21 Thread Last Branch Record 21 Additional Information (R/W) See description of MSR_LBR_INFO_0. DD6H 3522 MSR_LBR_INFO_22 Thread Last Branch Record 22 Additional Information (R/W) See description of MSR_LBR_INFO_0. DD7H 3523 MSR_LBR_INFO_23 Thread Last Branch Record 23 Additional Information (R/W) See description of MSR_LBR_INFO_0. DD8H 3524 MSR_LBR_INFO_24 Thread Last Branch Record 24 Additional Information (R/W) See description of MSR_LBR_INFO_0. DD9H 3525 MSR_LBR_INFO_25 Thread Last Branch Record 25 Additional Information (R/W) See description of MSR_LBR_INFO_0. DDAH 3526 MSR_LBR_INFO_26 Thread Last Branch Record 26 Additional Information (R/W) See description of MSR_LBR_INFO_0. Vol. 4 2-285 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-39. Additional MSRs Supported by 6th Generation Intel® Core™ Processors and the Intel® Xeon® Processor Scalable Family Based on Skylake Microarchitecture, 7th Generation Intel® Core™ Processors Based on Kaby Lake Microarchitecture, 8th Generation and 9th Generation Intel® Core™ Processors and Intel® Xeon® E Processors Based on Coffee Lake Microarchitecture, and 8th Generation Intel® Core™ i3 Processors Based on Cannon Lake Microarchitecture Register Address Hex Dec DDBH 3527 Register Name / Bit Fields MSR_LBR_INFO_27 Scope Thread Bit Description Last Branch Record 27 Additional Information (R/W) See description of MSR_LBR_INFO_0. DDCH 3528 MSR_LBR_INFO_28 Thread Last Branch Record 28 Additional Information (R/W) See description of MSR_LBR_INFO_0. DDDH 3529 MSR_LBR_INFO_29 Thread Last Branch Record 29 Additional Information (R/W) See description of MSR_LBR_INFO_0. DDEH 3530 MSR_LBR_INFO_30 Thread Last Branch Record 30 Additional Information (R/W) See description of MSR_LBR_INFO_0. DDFH 3531 MSR_LBR_INFO_31 Thread Last Branch Record 31 Additional Information (R/W) See description of MSR_LBR_INFO_0. Table 2-40 lists the MSRs of uncore PMU for Intel processors with CPUID DisplayFamily_DisplayModel signatures of 06_4EH, 06_5EH, 06_8EH, 06_9EH, and 06_66H. Table 2-40. Uncore PMU MSRs Supported by 6th Generation, 7th Generation, and 8th Generation Intel® Core™ Processors, and Future Intel® Core™ Processors Register Address Hex Dec 394H 916 395H 396H 917 918 Register Name / Bit Fields MSR_UNC_PERF_FIXED_CTRL Scope Package Bit Description Uncore Fixed Counter Control (R/W) 19:0 Reserved 20 Enable overflow propagation. 21 Reserved 22 Enable counting. 63:23 Reserved MSR_UNC_PERF_FIXED_CTR Package Uncore Fixed Counter 43:0 Current count. 63:44 Reserved MSR_UNC_CBO_CONFIG Package Uncore C-Box Configuration Information (R/O) 3:0 Specifies the number of C-Box units with programmable counters (including processor cores and processor graphics). 63:4 Reserved 3B0H 946 MSR_UNC_ARB_PERFCTR0 Package Uncore Arb Unit, Performance Counter 0 3B1H 947 MSR_UNC_ARB_PERFCTR1 Package Uncore Arb Unit, Performance Counter 1 3B2H 944 MSR_UNC_ARB_PERFEVTSEL0 Package Uncore Arb Unit, Counter 0 Event Select MSR 3B3H 945 MSR_UNC_ARB_PERFEVTSEL1 Package Uncore Arb Unit, Counter 1 Event Select MSR 2-286 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-40. Uncore PMU MSRs Supported by 6th Generation, 7th Generation, and 8th Generation Intel® Core™ Processors, and Future Intel® Core™ Processors Register Address Register Name / Bit Fields Scope Bit Description Hex Dec 700H 1792 MSR_UNC_CBO_0_PERFEVTSEL0 Package Uncore C-Box 0, Counter 0 Event Select MSR 701H 1793 MSR_UNC_CBO_0_PERFEVTSEL1 Package Uncore C-Box 0, Counter 1 Event Select MSR 706H 1798 MSR_UNC_CBO_0_PERFCTR0 Package Uncore C-Box 0, Performance Counter 0 707H 1799 MSR_UNC_CBO_0_PERFCTR1 Package Uncore C-Box 0, Performance Counter 1 710H 1808 MSR_UNC_CBO_1_PERFEVTSEL0 Package Uncore C-Box 1, Counter 0 Event Select MSR 711H 1809 MSR_UNC_CBO_1_PERFEVTSEL1 Package Uncore C-Box 1, Counter 1 Event Select MSR 716H 1814 MSR_UNC_CBO_1_PERFCTR0 Package Uncore C-Box 1, Performance Counter 0 717H 1815 MSR_UNC_CBO_1_PERFCTR1 Package Uncore C-Box 1, Performance Counter 1 720H 1824 MSR_UNC_CBO_2_PERFEVTSEL0 Package Uncore C-Box 2, Counter 0 Event Select MSR 721H 1825 MSR_UNC_CBO_2_PERFEVTSEL1 Package Uncore C-Box 2, Counter 1 Event Select MSR 726H 1830 MSR_UNC_CBO_2_PERFCTR0 Package Uncore C-Box 2, Performance Counter 0 727H 1831 MSR_UNC_CBO_2_PERFCTR1 Package Uncore C-Box 2, Performance Counter 1 730H 1840 MSR_UNC_CBO_3_PERFEVTSEL0 Package Uncore C-Box 3, Counter 0 Event Select MSR 731H 1841 MSR_UNC_CBO_3_PERFEVTSEL1 Package Uncore C-Box 3, Counter 1 Event Select MSR 736H 1846 MSR_UNC_CBO_3_PERFCTR0 Package Uncore C-Box 3, Performance Counter 0 737H 1847 MSR_UNC_CBO_3_PERFCTR1 Package Uncore C-Box 3, Performance Counter 1 E01H 3585 MSR_UNC_PERF_GLOBAL_CTRL Package Uncore PMU Global Control E02H 3586 0 Slice 0 select. 1 Slice 1 select. 2 Slice 2 select. 3 Slice 3 select. 4 Slice 4select. 18:5 Reserved 29 Enable all uncore counters. 30 Enable wake on PMI. 31 Enable Freezing counter when overflow. 63:32 Reserved MSR_UNC_PERF_GLOBAL_STATUS Package Uncore PMU Main Status 0 Fixed counter overflowed. 1 An ARB counter overflowed. 2 Reserved 3 A CBox counter overflowed (on any slice). 63:4 Reserved Vol. 4 2-287 MODEL-SPECIFIC REGISTERS (MSRS) 2.17.1 MSRs Specific to 7th Generation and 8th Generation Intel® Core™ Processors based on Kaby Lake Microarchitecture and Coffee Lake Microarchitecture Table 2-42 lists additional MSRs for 7th generation and 8th generation Intel Core processors with a CPUID DisplayFamily_DisplayModel signatures of 06_8EH and 06_9EH. For an MSR listed in Table 2-42 that also appears in the model-specific tables of prior generations, Table 2-42 supersedes prior generation tables. Table 2-41. Additional MSRs Supported by 7th Generation and 8th Generation Intel® Core™ Processors Based on Kaby Lake Microarchitecture and Coffee Lake Microarchitecture Register Address Hex Dec 80H 128 Register Name / Bit Fields MSR_TRACE_HUB_STH_ACPIBAR_BASE Scope Package 0 Bit Description NPK Address Used by AET Messages (R/W) Lock Bit If set, this MSR cannot be re-written anymore. Lock bit has to be set in order for the AET packets to be directed to NPK MMIO. 17:1 Reserved 63:18 ACPIBAR_BASE_ADDRESS AET target address in NPK MMIO space. 1F4H 500 MSR_PRMRR_PHYS_BASE Core 2:0 Processor Reserved Memory Range Register Physical Base Control Register (R/W) MemType PRMRR BASE MemType. 11:3 Reserved 45:12 Base PRMRR Base Address. 63:46 1F5H 501 MSR_PRMRR_PHYS_MASK Reserved Core Processor Reserved Memory Range Register Physical Mask Control Register (R/W) 9:0 Reserved 10 Lock Lock bit for the PRMRR. 11 VLD Enable bit for the PRMRR. 45:12 Mask PRMRR MASK bits. 63:46 1FBH 2-288 Vol. 4 507 MSR_PRMRR_VALID_CONFIG Reserved Core Valid PRMRR Configurations (R/W) 0 1M supported MEE size. 4:1 Reserved 5 32M supported MEE size. 6 64M supported MEE size. 7 128M supported MEE size. 31:8 Reserved MODEL-SPECIFIC REGISTERS (MSRS) Table 2-41. Additional MSRs Supported by 7th Generation and 8th Generation Intel® Core™ Processors Based on Kaby Lake Microarchitecture and Coffee Lake Microarchitecture Register Address Hex Dec 2F4H 756 Register Name / Bit Fields MSR_UNCORE_PRMRR_PHYS_BASE Scope Package Bit Description (R/W) The PRMRR range is used to protect Xucode memory from unauthorized reads and writes. Any IO access to this range is aborted. This register controls the location of the PRMRR range by indicating its starting address. It functions in tandem with the PRMRR mask register. 11:0 Reserved 38:12 Range Base This field corresponds to bits 38:12 of the base address memory range which is allocated to PRMRR memory. 63:39 2F5H 757 MSR_UNCORE_PRMRR_PHYS_MASK Reserved Package (R/W) This register controls the size of the PRMRR range by indicating which address bits must match the PRMRR base register value. 9:0 Reserved 10 Lock Setting this bit locks all writeable settings in this register, including itself. 11 Range_En Indicates whether the PRMRR range is enabled and valid. 38:12 Range_Mask This field indicates which address bits must match PRMRR base in order to qualify as an PRMRR access. 63:39 620H 1568 MSR_RING_RATIO_LIMIT Reserved Package Ring Ratio Limit (R/W) This register provides Min/Max Ratio Limits for the LLC and Ring. 6:0 MAX_Ratio This field is used to limit the max ratio of the LLC/Ring. 7 14:8 Reserved MIN_Ratio Writing to this field controls the minimum possible ratio of the LLC/Ring. 63:15 Reserved Vol. 4 2-289 MODEL-SPECIFIC REGISTERS (MSRS) 2.17.2 MSRs Specific to 8th Generation Intel® Core™ i3 Processors Table 2-42 lists additional MSRs for 8th generation Intel Core i3 processors with a CPUID DisplayFamily_DisplayModel signature of 06_66H. For an MSR listed in Table 2-42 that also appears in the modelspecific tables of prior generations, Table 2-42 supersede prior generation tables. Table 2-42. Additional MSRs Supported by 8th Generation Intel® Core™ i3 Processors Based on Cannon Lake Microarchitecture Register Address Hex Dec 3AH 58 Register Name / Bit Fields IA32_FEATURE_CONTROL Scope Thread Bit Description Control Features in Intel 64 Processor (R/W) See Table 2-2. 0 Lock (R/WL) 1 Enable VMX Inside SMX Operation (R/WL) 2 Enable VMX Outside SMX Operation (R/WL) 14:8 SENTER Local Functions Enables (R/WL) 15 SENTER Global Functions Enable (R/WL) 17 SGX Launch Control Enable (R/WL) This bit must be set to enable runtime reconfiguration of SGX Launch Control via IA32_SGXLEPUBKEYHASHn MSR. Available only if CPUID.(EAX=07H, ECX=0H): ECX[30] = 1. 350H 848 18 SGX Global Functions Enable (R/WL) 63:21 Reserved MSR_BR_DETECT_CTRL Branch Monitoring Global Control (R/W) 0 EnMonitoring Global enable for branch monitoring. 1 EnExcept Enable branch monitoring event signaling on threshold trip. The branch monitoring event handler is signaled via the existing PMI signaling mechanism as programmed from the corresponding local APIC LVT entry. 2 EnLBRFrz Enable LBR freeze on threshold trip. This will cause the LBR frozen bit 58 to be set in IA32_PERF_GLOBAL_STATUS when a triggering condition occurs and this bit is enabled. 3 DisableInGuest When set to ‘1’, branch monitoring, event triggering and LBR freeze actions are disabled when operating at VMX non-root operation. 7:4 2-290 Vol. 4 Reserved MODEL-SPECIFIC REGISTERS (MSRS) Table 2-42. Additional MSRs Supported by 8th Generation Intel® Core™ i3 Processors Based on Cannon Lake Microarchitecture (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 17:8 WindowSize Window size defined by WindowCntSel. Values 0 – 1023 are supported. Once the Window counter reaches the WindowSize count both the Window Counter and all Branch Monitoring Counters are cleared. 23:18 Reserved 25:24 WindowCntSel Window event count select: ‘00 = Instructions retired. ‘01 = Branch instructions retired ‘10 = Return instructions retired. ‘11 = Indirect branch instructions retired. 26 CntAndMode When set to ‘1’, the overall branch monitoring event triggering condition is true only if all enabled counters’ threshold conditions are true. When ‘0’, the threshold tripping condition is true if any enabled counters’ threshold is true. 351H 849 63:27 Reserved MSR_BR_DETECT_STATUS Branch Monitoring Global Status (R/W) 0 Branch Monitoring Event Signaled When set to '1', Branch Monitoring event signaling is blocked until this bit is cleared by software. 1 LBRsValid This status bit is set to ‘1’ if the LBR state is considered valid for sampling by branch monitoring software. 7:2 8 Reserved CntrHit0 Branch monitoring counter #0 threshold hit. This status bit is sticky and once set requires clearing by software. Counter operation continues independent of the state of the bit. 9 CntrHit1 Branch monitoring counter #1 threshold hit. This status bit is sticky and once set requires clearing by software. Counter operation continues independent of the state of the bit. 15:10 Reserved Reserved for additional branch monitoring counters threshold hit status. Vol. 4 2-291 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-42. Additional MSRs Supported by 8th Generation Intel® Core™ i3 Processors Based on Cannon Lake Microarchitecture (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 25:16 CountWindow The current value of the window counter. The count value is frozen on a valid branch monitoring triggering condition. This is a 10-bit unsigned value. 31:26 Reserved Reserved for future extension of CountWindow. 39:32 Count0 The current value of counter 0 updated after each occurrence of the event being counted. The count value is frozen on a valid branch monitoring triggering condition (in which case CntrHit0 will also be set). This is an 8-bit signed value (2’s complement). Heuristic events which only increment will saturate and freeze at maximum value 0xFF (256). RET-CALL event counter saturate at maximum value 0x7F (+127) and minimum value 0x80 (-128). 47:40 Count1 The current value of counter 1 updated after each occurrence of the event being counted. The count value is frozen on a valid branch monitoring triggering condition (in which case CntrHit1 will also be set). This is an 8-bit signed value (2’s complement). Heuristic events which only increment will saturate and freeze at maximum value 0xFF (256). RET-CALL event counter saturate at maximum value 0x7F (+127) and minimum value 0x80 (-128). 354H 355H 852 853 63:48 Reserved MSR_BR_DETECT_COUNTER_CONFIG_i Branch Monitoring Detect Counter Configuration (R/W) 0 CntrEn Enable counter. 7:1 CntrEvSel Event select (other values #GP) ‘0000000 = RETs. ‘0000001 = RET-CALL bias. ‘0000010 = RET mispredicts. ‘0000011 = Branch (all) mispredicts. ‘0000100 = Indirect branch mispredicts. ‘0000101 = Far branch instructions. 2-292 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-42. Additional MSRs Supported by 8th Generation Intel® Core™ i3 Processors Based on Cannon Lake Microarchitecture (Contd.) Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 14:8 CntrThreshold Threshold (an unsigned value of 0 to 127 supported). The value 0 of counter threshold will result in event signaled after every instruction. #GP if threshold is < 2. 15 MispredEventCnt Mispredict events counting behavior: ‘0 = Mispredict events are counted in a window. ‘1 = Mispredict events are counted based on a consecutive occurrence. CntrThreshold is treated as # of consecutive mispredicts. This control bit only applies to events specified by CntrEvSel that involve a prediction (0000010, 0000011, 0000100). Setting this bit for other events is ignored. 63:16 3F8H 1016 MSR_PKG_C3_RESIDENCY Reserved Package 63:0 620H 1568 MSR_RING_RATIO_LIMIT Package C3 Residency Counter (R/O) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-states. Package Ring Ratio Limit (R/W) This register provides Min/Max Ratio Limits for the LLC and Ring. 6:0 MAX_Ratio This field is used to limit the max ratio of the LLC/Ring. 7 Reserved 14:8 MIN_Ratio Writing to this field controls the minimum possible ratio of the LLC/Ring. 63:15 660H 1632 MSR_CORE_C1_RESIDENCY Reserved Core 63:0 662H 1634 MSR_CORE_C3_RESIDENCY 63:0 Core C1 Residency Counter (R/O) Value since last reset for the Core C1 residency. Counter rate is the Max Non-Turbo frequency (same as TSC). This counter counts in case both of the core's threads are in an idle state and at least one of the core's thread residency is in a C1 state or in one of its sub states. The counter is updated only after a core C state exit. Note: Always reads 0 if core C1 is unsupported. A value of zero indicates that this processor does not support core C1 or never entered core C1 level state. Core Core C3 Residency Counter (R/O) Will always return 0. Vol. 4 2-293 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-43 lists the MSRs of uncore PMU for Intel processors with CPUID signature 06_66H. Table 2-43. Uncore PMU MSRs Supported by Intel® Core™ Processors Based on Cannon Lake Microarchitecture Register Address Hex Dec 394H 916 395H 396H 917 918 Register Name / Bit Fields MSR_UNC_PERF_FIXED_CTRL Scope Package Bit Description Uncore Fixed Counter Control (R/W) 19:0 Reserved 20 Enable overflow propagation. 21 Reserved 22 Enable counting. 63:23 Reserved MSR_UNC_PERF_FIXED_CTR Package Uncore Fixed Counter 47:0 Current count. 63:48 Reserved MSR_UNC_CBO_CONFIG Package Uncore C-Box Configuration Information (R/O) 3:0 Report the number of C-Box units with performance counters, including processor cores and processor graphics. 63:4 Reserved 3B0H 946 MSR_UNC_ARB_PERFCTR0 Package Uncore Arb Unit, Performance Counter 0 3B1H 947 MSR_UNC_ARB_PERFCTR1 Package Uncore Arb Unit, Performance Counter 1 3B2H 944 MSR_UNC_ARB_PERFEVTSEL0 Package Uncore Arb Unit, Counter 0 Event Select MSR 3B3H 945 MSR_UNC_ARB_PERFEVTSEL1 Package Uncore Arb unit, Counter 1 Event Select MSR 700H 1792 MSR_UNC_CBO_0_PERFEVTSEL0 Package Uncore C-Box 0, Counter 0 Event Select MSR 701H 1793 MSR_UNC_CBO_0_PERFEVTSEL1 Package Uncore C-Box 0, Counter 1 Event Select MSR 702H 1794 MSR_UNC_CBO_0_PERFCTR0 Package Uncore C-Box 0, Performance Counter 0 703H 1795 MSR_UNC_CBO_0_PERFCTR1 Package Uncore C-Box 0, Performance Counter 1 708H 1800 MSR_UNC_CBO_1_PERFEVTSEL0 Package Uncore C-Box 1, Counter 0 Event Select MSR 709H 1801 MSR_UNC_CBO_1_PERFEVTSEL1 Package Uncore C-Box 1, Counter 1 Event Select MSR 70AH 1802 MSR_UNC_CBO_1_PERFCTR0 Package Uncore C-Box 1, Performance Counter 0 70BH 1803 MSR_UNC_CBO_1_PERFCTR1 Package Uncore C-Box 1, Performance Counter 1 710H 1808 MSR_UNC_CBO_2_PERFEVTSEL0 Package Uncore C-Box 2, Counter 0 Event Select MSR 711H 1809 MSR_UNC_CBO_2_PERFEVTSEL1 Package Uncore C-Box 2, Counter 1 Event Select MSR 712H 1810 MSR_UNC_CBO_2_PERFCTR0 Package Uncore C-Box 2, Performance Counter 0 713H 1811 MSR_UNC_CBO_2_PERFCTR1 Package Uncore C-Box 2, Performance Counter 1 718H 1816 MSR_UNC_CBO_3_PERFEVTSEL0 Package Uncore C-Box 3, Counter 0 Event Select MSR 719H 1817 MSR_UNC_CBO_3_PERFEVTSEL1 Package Uncore C-Box 3, Counter 1 Event Select MSR 71AH 1818 MSR_UNC_CBO_3_PERFCTR0 Package Uncore C-Box 3, Performance Counter 0 71BH 1819 MSR_UNC_CBO_3_PERFCTR1 Package Uncore C-Box 3, Performance Counter 1 2-294 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-43. Uncore PMU MSRs Supported by Intel® Core™ Processors Based on Cannon Lake Microarchitecture Register Address Register Name / Bit Fields Scope Bit Description Hex Dec 720H 1824 MSR_UNC_CBO_4_PERFEVTSEL0 Package Uncore C-Box 4, Counter 0 Event Select MSR 721H 1825 MSR_UNC_CBO_4_PERFEVTSEL1 Package Uncore C-Box 4, Counter 1 Event Select MSR 722H 1826 MSR_UNC_CBO_4_PERFCTR0 Package Uncore C-Box 4, Performance Counter 0 723H 1827 MSR_UNC_CBO_4_PERFCTR1 Package Uncore C-Box 4, Performance Counter 1 728H 1832 MSR_UNC_CBO_5_PERFEVTSEL0 Package Uncore C-Box 5, Counter 0 Event Select MSR 729H 1833 MSR_UNC_CBO_5_PERFEVTSEL1 Package Uncore C-Box 5, Counter 1 Event Select MSR 72AH 1834 MSR_UNC_CBO_5_PERFCTR0 Package Uncore C-Box 5, Performance Counter 0 72BH 1835 MSR_UNC_CBO_5_PERFCTR1 Package Uncore C-Box 5, Performance Counter 1 730H 1840 MSR_UNC_CBO_6_PERFEVTSEL0 Package Uncore C-Box 6, Counter 0 Event Select MSR 731H 1841 MSR_UNC_CBO_6_PERFEVTSEL1 Package Uncore C-Box 6, Counter 1 Event Select MSR 732H 1842 MSR_UNC_CBO_6_PERFCTR0 Package Uncore C-Box 6, Performance Counter 0 733H 1843 MSR_UNC_CBO_6_PERFCTR1 Package Uncore C-Box 6, Performance Counter 1 738H 1848 MSR_UNC_CBO_7_PERFEVTSEL0 Package Uncore C-Box 7, Counter 0 Event Select MSR 739H 1849 MSR_UNC_CBO_7_PERFEVTSEL1 Package Uncore C-Box 7, Counter 1 Event Select MSR 73AH 1850 MSR_UNC_CBO_7_PERFCTR0 Package Uncore C-Box 7, Performance Counter 0 73BH 1851 MSR_UNC_CBO_7_PERFCTR1 Package Uncore C-Box 7, Performance Counter 1 E01H 3585 MSR_UNC_PERF_GLOBAL_CTRL Package Uncore PMU Global Control E02H 3586 0 Slice 0 select. 1 Slice 1 select. 2 Slice 2 select. 3 Slice 3 select. 4 Slice 4select. 18:5 Reserved 29 Enable all uncore counters. 30 Enable wake on PMI. 31 Enable Freezing counter when overflow. 63:32 Reserved MSR_UNC_PERF_GLOBAL_STATUS Package Uncore PMU Main Status 0 Fixed counter overflowed. 1 An ARB counter overflowed. 2 Reserved 3 A CBox counter overflowed (on any slice). 63:4 Reserved Table 2-44 lists MSRs for Future Intel Core processors based on Ice Lake microarchitecture. Vol. 4 2-295 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-44. MSRs Supported by Future Intel® Core™ Processors Based on Ice Lake Microarchitecture Register Address Hex Dec 33H 51 Register Name / Bit Fields TEST_CTRL Scope Core Bit Description Test Control Register 28:0 Reserved. 29 Enable #AC(0) exception for split locked accesses: Cause #AC(0) exception for split locked access at all CPL irrespective of CR0.AM or EFLAGS.AC. If bits 29 and 31 are both set, bit 29 takes precedence. 329H 809 30 Reserved. 31 Disable LOCK# assertion for split locked access. MSR_PERF_METRICS Thread Performance Metrics (R/W) Reports metrics directly. Software can check (and/or expose to its guests) the availability of PERF_METRICS feature using IA32_PERF_CAPABILITIES.PERF_METRICS_AVAILABL E (bit 15). 3F2H 1010 7:0 Retiring. 15:8 Bad Speculation. 23:16 Frontend Bound. 31:24 Backend Bound. 63:25 Reserved. MSR_PEBS_DATA_CFG Thread PEBS Data Configuration (R/W) Provides software the capability to select data groups of interest and thus reduce the record size in memory and record generation latency. Hence, a PEBS record's size and layout vary based on the selected groups. The MSR also allows software to select LBR depth for branch data records. 0 Memory Info. Setting this bit will capture memory information such as the linear address, data source and latency of the memory access in the PEBS record. 1 GPRs. Setting this bit will capture the contents of the General Purpose registers in the PEBS record. 2 XMMs. Setting this bit will capture the contents of the XMM registers in the PEBS record. 3 LBRs. Setting this bit will capture LBR TO, FROM and INFO in the PEBS record. 23:4 2-296 Vol. 4 Reserved. MODEL-SPECIFIC REGISTERS (MSRS) Table 2-44. MSRs Supported by Future Intel® Core™ Processors Based on Ice Lake Microarchitecture Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 31:24 LBR Entries. Set the field to the desired number of entries - 1. For example, if the LBR_entries field is 0, a single entry will be included in the record. To include 32 LBR entries, set the LBR_entries field to 31 (0x1F). To ensure all PEBS records are 16-byte aligned, software can use LBR_entries that is multiple of 3. 2.17.3 Intel® MSRs Specific to Intel® Xeon® Processor Scalable Family Xeon® Processor Scalable Family (CPUID DisplayFamily_DisplayModel = 06_55H) support the MSRs listed in Table 2-45. Table 2-45. MSRs Supported by Intel® Xeon® Processor Scalable Family with DisplayFamily_DisplayModel 06_55H Register Address Hex Dec 3AH 58 Register Name / Bit Fields IA32_FEATURE_CONTROL Scope Thread Bit Description Control Features in Intel 64 Processor (R/W) See Table 2-2. 4EH 78 0 Lock (R/WL) 1 Enable VMX Inside SMX Operation (R/WL) 2 Enable VMX Outside SMX Operation (R/WL) 14:8 SENTER Local Functions Enables (R/WL) 15 SENTER Global Functions Enable (R/WL) 18 SGX Global Functions Enable (R/WL) 20 LMCE_ON (R/WL) 63:21 Reserved MSR_PPIN_CTL Package 0 Protected Processor Inventory Number Enable Control (R/W) LockOut (R/WO) See Table 2-26. 1 Enable_PPIN (R/W) See Table 2-26. 63:2 4FH 79 MSR_PPIN Reserved Package 63:0 Protected Processor Inventory Number (R/O) Protected Processor Inventory Number (R/O) See Table 2-26. CEH 206 MSR_PLATFORM_INFO Package Platform Information Contains power management and other model specific features enumeration. See http://biosbits.org. 7:0 Reserved Vol. 4 2-297 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-45. MSRs Supported by Intel® Xeon® Processor Scalable Family with DisplayFamily_DisplayModel 06_55H Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 15:8 Package Maximum Non-Turbo Ratio (R/O) See Table 2-26. 22:16 23 Reserved. Package PPIN_CAP (R/O) See Table 2-26. 27:24 28 Reserved Package Programmable Ratio Limit for Turbo Mode (R/O) See Table 2-26. 29 Package Programmable TDP Limit for Turbo Mode (R/O) See Table 2-26. 30 Package Programmable TJ OFFSET (R/O) See Table 2-26. 39:31 47:40 Reserved Package Maximum Efficiency Ratio (R/O) See Table 2-26. 63:48 E2H 226 MSR_PKG_CST_CONFIG_CONTROL Reserved Core C-State Configuration Control (R/W) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-states. See http://biosbits.org. 2:0 Package C-State Limit (R/W) Specifies the lowest processor-specific C-state code name (consuming the least power) for the package. The default is set as factory-configured package Cstate limit. The following C-state code name encodings are supported: 000b: C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention) 011b: C6 (retention) 111b: No Package C state limits. All C states supported by the processor are available. 9:3 Reserved 10 I/O MWAIT Redirection Enable (R/W) 14:11 Reserved 15 CFG Lock (R/WO) 16 Automatic C-State Conversion Enable (R/W) If 1, the processor will convert HALT or MWAT(C1) to MWAIT(C6). 2-298 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-45. MSRs Supported by Intel® Xeon® Processor Scalable Family with DisplayFamily_DisplayModel 06_55H Register Address Hex 179H 17DH Register Name / Bit Fields Scope Bit Description Dec 377 390 24:17 Reserved 25 C3 State Auto Demotion Enable (R/W) 26 C1 State Auto Demotion Enable (R/W) 27 Enable C3 Undemotion (R/W) 28 Enable C1 Undemotion (R/W) 29 Package C State Demotion Enable (R/W) 30 Package C State UnDemotion Enable (R/W) 63:31 Reserved IA32_MCG_CAP Thread Global Machine Check Capability (R/O) 7:0 Count 8 MCG_CTL_P 9 MCG_EXT_P 10 MCP_CMCI_P 11 MCG_TES_P 15:12 Reserved 23:16 MCG_EXT_CNT 24 MCG_SER_P 25 MCG_EM_P 26 MCG_ELOG_P 63:27 Reserved MSR_SMM_MCA_CAP THREAD Enhanced SMM Capabilities (SMM-RO) Reports SMM capability Enhancement. Accessible only while in SMM. 57:0 Reserved 58 SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the SMM code access restriction is supported and a host-space interface is available to SMM handler. 59 Long_Flow_Indication (SMM-RO) If set to 1 indicates that the SMM long flow indicator is supported and a host-space interface is available to SMM handler. 63:60 19CH 412 IA32_THERM_STATUS Reserved Core Thermal Monitor Status (R/W) See Table 2-2. 0 Thermal Status (RO) See Table 2-2. 1 Thermal Status Log (R/WC0) See Table 2-2. Vol. 4 2-299 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-45. MSRs Supported by Intel® Xeon® Processor Scalable Family with DisplayFamily_DisplayModel 06_55H Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 2 PROTCHOT # or FORCEPR# Status (RO) See Table 2-2. 3 PROTCHOT # or FORCEPR# Log (R/WC0) See Table 2-2. 4 Critical Temperature Status (RO) See Table 2-2. 5 Critical Temperature Status Log (R/WC0) See Table 2-2. 6 Thermal Threshold #1 Status (RO) See Table 2-2. 7 Thermal Threshold #1 Log (R/WC0) See Table 2-2. 8 Thermal Threshold #2 Status (RO) See Table 2-2. 9 Thermal Threshold #2 Log (R/WC0) See Table 2-2. 10 Power Limitation Status (RO) See Table 2-2. 11 Power Limitation Log (R/WC0) See Table 2-2. 12 Current Limit Status (RO) See Table 2-2. 13 Current Limit Log (R/WC0) See Table 2-2. 14 Cross Domain Limit Status (RO) See Table 2-2. 15 Cross Domain Limit Log (R/WC0) See Table 2-2. 22:16 Digital Readout (RO) See Table 2-2. 26:23 Reserved 30:27 Resolution in Degrees Celsius (RO) See Table 2-2. 31 Reading Valid (RO) See Table 2-2. 63:32 1A2H 418 MSR_TEMPERATURE_TARGET 15:0 2-300 Vol. 4 Reserved Package Temperature Target Reserved MODEL-SPECIFIC REGISTERS (MSRS) Table 2-45. MSRs Supported by Intel® Xeon® Processor Scalable Family with DisplayFamily_DisplayModel 06_55H Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 23:16 Temperature Target (RO) See Table 2-26. 27:24 TCC Activation Offset (R/W) See Table 2-26. 63:28 1ADH 429 MSR_TURBO_RATIO_LIMIT Reserved Package This register defines the ratio limits. RATIO[0:7] must be populated in ascending order. RATIO[i+1] must be less than or equal to RATIO[i]. Entries with RATIO[i] will be ignored. If any of the rules above are broken, the configuration is silently rejected. If the programmed ratio is: • Above the fused ratio for that core count, it will be clipped to the fuse limits (assuming !OC). • Below the min supported ratio, it will be clipped. 7:0 RATIO_0 Defines ratio limits. 15:8 RATIO_1 Defines ratio limits. 23:16 RATIO_2 Defines ratio limits. 31:24 RATIO_3 Defines ratio limits. 39:32 RATIO_4 Defines ratio limits. 47:40 RATIO_5 Defines ratio limits. 55:48 RATIO_6 Defines ratio limits. 63:56 RATIO_7 Defines ratio limits. 1AEH 430 MSR_TURBO_RATIO_LIMIT_CORES 7:0 Package This register defines the active core ranges for each frequency point. NUMCORE[0:7] must be populated in ascending order. NUMCORE[i+1] must be greater than NUMCORE[i]. Entries with NUMCORE[i] == 0 will be ignored. The last valid entry must have NUMCORE >= the number of cores in the SKU. If any of the rules above are broken, the configuration is silently rejected. NUMCORE_0 Defines the active core ranges for each frequency point. 15:8 NUMCORE_1 Defines the active core ranges for each frequency point. Vol. 4 2-301 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-45. MSRs Supported by Intel® Xeon® Processor Scalable Family with DisplayFamily_DisplayModel 06_55H Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 23:16 NUMCORE_2 Defines the active core ranges for each frequency point. 31:24 NUMCORE_3 Defines the active core ranges for each frequency point. 39:32 NUMCORE_4 Defines the active core ranges for each frequency point. 47:40 NUMCORE_5 Defines the active core ranges for each frequency point. 55:48 NUMCORE_6 Defines the active core ranges for each frequency point. 63:56 NUMCORE_7 Defines the active core ranges for each frequency point. 280H 640 IA32_MC0_CTL2 Core See Table 2-2. 281H 641 IA32_MC1_CTL2 Core See Table 2-2. 282H 642 IA32_MC2_CTL2 Core See Table 2-2. 283H 643 IA32_MC3_CTL2 Core See Table 2-2. 284H 644 IA32_MC4_CTL2 Package See Table 2-2. 285H 645 IA32_MC5_CTL2 Package See Table 2-2. 286H 646 IA32_MC6_CTL2 Package See Table 2-2. 287H 647 IA32_MC7_CTL2 Package See Table 2-2. 288H 648 IA32_MC8_CTL2 Package See Table 2-2. 289H 649 IA32_MC9_CTL2 Package See Table 2-2. 28AH 650 IA32_MC10_CTL2 Package See Table 2-2. 28BH 651 IA32_MC11_CTL2 Package See Table 2-2. 28CH 652 IA32_MC12_CTL2 Package See Table 2-2. 28DH 653 IA32_MC13_CTL2 Package See Table 2-2. 28EH 654 IA32_MC14_CTL2 Package See Table 2-2. 28FH 655 IA32_MC15_CTL2 Package See Table 2-2. 290H 656 IA32_MC16_CTL2 Package See Table 2-2. 291H 657 IA32_MC17_CTL2 Package See Table 2-2. 292H 658 IA32_MC18_CTL2 Package See Table 2-2. 293H 659 IA32_MC19_CTL2 Package See Table 2-2. 2-302 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-45. MSRs Supported by Intel® Xeon® Processor Scalable Family with DisplayFamily_DisplayModel 06_55H Register Address Register Name / Bit Fields Scope Hex Dec 400H 1024 IA32_MC0_CTL Core 401H 1025 IA32_MC0_STATUS Core 402H 1026 IA32_MC0_ADDR Core 403H 1027 IA32_MC0_MISC Core 404H 1028 IA32_MC1_CTL Core 405H 1029 IA32_MC1_STATUS Core 406H 1030 IA32_MC1_ADDR Core 407H 1031 IA32_MC1_MISC Core 408H 1032 IA32_MC2_CTL Core 409H 1033 IA32_MC2_STATUS Core 40AH 1034 IA32_MC2_ADDR Core 40BH 1035 IA32_MC2_MISC Core 40CH 1036 IA32_MC3_CTL Core 40DH 1037 IA32_MC3_STATUS Core 40EH 1038 IA32_MC3_ADDR Core 40FH 1039 IA32_MC3_MISC Core 410H 1040 IA32_MC4_CTL Package 411H 1041 IA32_MC4_STATUS Package 412H 1042 IA32_MC4_ADDR Package 413H 1043 IA32_MC4_MISC Package 414H 1044 IA32_MC5_CTL Package 415H 1045 IA32_MC5_STATUS Package 416H 1046 IA32_MC5_ADDR Package 417H 1047 IA32_MC5_MISC Package 418H 1048 IA32_MC6_CTL Package 419H 1049 IA32_MC6_STATUS Package 41AH 1050 IA32_MC6_ADDR Package 41BH 1051 IA32_MC6_MISC Package 41CH 1052 IA32_MC7_CTL Package 41DH 1053 IA32_MC7_STATUS Package 41EH 1054 IA32_MC7_ADDR Package 41FH 1055 IA32_MC7_MISC Package 420H 1056 IA32_MC8_CTL Package 421H 1057 IA32_MC8_STATUS Package 422H 1058 IA32_MC8_ADDR Package 423H 1059 IA32_MC8_MISC Package Bit Description See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC0 reports MC errors from the IFU module. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC1 reports MC errors from the DCU module. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC2 reports MC errors from the DTLB module. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC3 reports MC errors from the MLC module. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC4 reports MC errors from the PCU module. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC5 reports MC errors from a link interconnect module. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC6 reports MC errors from the integrated I/O module. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC7 reports MC errors from the M2M 0. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC8 reports MC errors from the M2M 1. Vol. 4 2-303 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-45. MSRs Supported by Intel® Xeon® Processor Scalable Family with DisplayFamily_DisplayModel 06_55H Register Address Register Name / Bit Fields Scope Hex Dec 424H 1060 IA32_MC9_CTL Package 425H 1061 IA32_MC9_STATUS Package 426H 1062 IA32_MC9_ADDR Package 427H 1063 IA32_MC9_MISC Package 428H 1064 IA32_MC10_CTL Package 429H 1065 IA32_MC10_STATUS Package 42AH 1066 IA32_MC10_ADDR Package 42BH 1067 IA32_MC10_MISC Package 42CH 1068 IA32_MC11_CTL Package 42DH 1069 IA32_MC11_STATUS Package 42EH 1070 IA32_MC11_ADDR Package 42FH 1071 IA32_MC11_MISC Package 430H 1072 IA32_MC12_CTL Package 431H 1073 IA32_MC12_STATUS Package 432H 1074 IA32_MC12_ADDR Package 433H 1075 IA32_MC12_MISC Package 434H 1076 IA32_MC13_CTL Package 435H 1077 IA32_MC13_STATUS Package 436H 1078 IA32_MC13_ADDR Package 437H 1079 IA32_MC13_MISC Package 438H 1080 IA32_MC14_CTL Package 439H 1081 IA32_MC14_STATUS Package 43AH 1082 IA32_MC14_ADDR Package 43BH 1083 IA32_MC14_MISC Package 43CH 1084 IA32_MC15_CTL Package 43DH 1085 IA32_MC15_STATUS Package 43EH 1086 IA32_MC15_ADDR Package 43FH 1087 IA32_MC15_MISC Package 440H 1088 IA32_MC16_CTL Package 441H 1089 IA32_MC16_STATUS Package 442H 1090 IA32_MC16_ADDR Package 443H 1091 IA32_MC16_MISC Package 444H 1092 IA32_MC17_CTL Package 445H 1093 IA32_MC17_STATUS Package 446H 1094 IA32_MC17_ADDR Package 447H 1095 IA32_MC17_MISC Package 2-304 Vol. 4 Bit Description See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC9 - MC11 report MC errors from the CHA See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC9 - MC11 report MC errors from the CHA. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC9 - MC11 report MC errors from the CHA. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC12 report MC errors from each channel of a link interconnect module. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC13 through MC 18 report MC errors from the integrated memory controllers. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC13 through MC 18 report MC errors from the integrated memory controllers. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC13 through MC 18 report MC errors from the integrated memory controllers. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC13 through MC 18 report MC errors from the integrated memory controllers See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC13 through MC 18 report MC errors from the integrated memory controllers. MODEL-SPECIFIC REGISTERS (MSRS) Table 2-45. MSRs Supported by Intel® Xeon® Processor Scalable Family with DisplayFamily_DisplayModel 06_55H Register Address Register Name / Bit Fields Scope Bit Description Hex Dec 448H 1096 IA32_MC18_CTL Package 449H 1097 IA32_MC18_STATUS Package 44AH 1098 IA32_MC18_ADDR Package 44BH 1099 IA32_MC18_MISC Package 44CH 1100 IA32_MC19_CTL Package 44DH 1101 IA32_MC19_STATUS Package 44EH 1102 IA32_MC19_ADDR Package 44FH 1103 IA32_MC19_MISC Package 606H 1542 MSR_RAPL_POWER_UNIT Package Unit Multipliers Used in RAPL Interfaces (R/O) 3:0 Package Power Units See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Banks MC13 through MC 18 report MC errors from the integrated memory controllers. See Section 15.3.2.1, “IA32_MCi_CTL MSRs” through Section 15.3.2.4, “IA32_MCi_MISC MSRs.”. Bank MC19 reports MC errors from a link interconnect module. See Section 14.9.1, “RAPL Interfaces.” 7:4 Package Reserved 12:8 Package Energy Status Units Energy related information (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an unsigned integer represented by bits 12:8. Default value is 0EH (or 61 micro-joules). 15:13 Package Reserved 19:16 Package Time Units See Section 14.9.1, “RAPL Interfaces.” 63:20 Reserved 618H 1560 MSR_DRAM_POWER_LIMIT Package 619H 1561 MSR_DRAM_ENERGY_STATUS Package DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, “DRAM RAPL Domain.” DRAM Energy Status (R/O) Energy consumed by DRAM devices. 31:0 Energy in 15.3 micro-joules. Requires BIOS configuration to enable DRAM RAPL mode 0 (Direct VR). 63:32 61BH 1563 MSR_DRAM_PERF_STATUS Reserved Package DRAM Performance Throttling Status (R/O) See Section 14.9.5, “DRAM RAPL Domain.” 61CH 1564 MSR_DRAM_POWER_INFO Package DRAM RAPL Parameters (R/W) 620H 1568 MSR UNCORE_RATIO_LIMIT Package Uncore Ratio Limit (R/W) See Section 14.9.5, “DRAM RAPL Domain.” Out of reset, the min_ratio and max_ratio fields represent the widest possible range of uncore frequencies. Writing to these fields allows software to control the minimum and the maximum frequency that hardware will select. 63:15 Reserved Vol. 4 2-305 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-45. MSRs Supported by Intel® Xeon® Processor Scalable Family with DisplayFamily_DisplayModel 06_55H Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 14:8 MIN_RATIO Writing to this field controls the minimum possible ratio of the LLC/Ring. 7 Reserved 6:0 MAX_RATIO This field is used to limit the max ratio of the LLC/Ring. 639H 1593 MSR_PP0_ENERGY_STATUS Package Reserved (R/O) Reads return 0. C8DH 3213 IA32_QM_EVTSEL THREAD Monitoring Event Select Register (R/W) If CPUID.(EAX=07H, ECX=0):EBX.RDT-M[bit 12] = 1. 7:0 EventID (RW) Event encoding: 0x00: No monitoring. 0x01: L3 occupancy monitoring. 0x02: Total memory bandwidth monitoring. 0x03: Local memory bandwidth monitoring. All other encoding reserved. C8FH C90H 3215 3216 31:8 Reserved 41:32 RMID (RW) 63:42 Reserved IA32_PQR_ASSOC THREAD Resource Association Register (R/W) 9:0 RMID 31:10 Reserved 51:32 COS (R/W) 63: 52 Reserved IA32_L3_QOS_MASK_0 Package L3 Class Of Service Mask - COS 0 (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=0. C91H 3217 0:19 CBM: Bit vector of available L3 ways for COS 0 enforcement. 63:20 Reserved IA32_L3_QOS_MASK_1 Package L3 Class Of Service Mask - COS 1 (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=1. C92H 3218 0:19 CBM: Bit vector of available L3 ways for COS 1 enforcement. 63:20 Reserved IA32_L3_QOS_MASK_2 Package L3 Class Of Service Mask - COS 2 (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=2. 2-306 Vol. 4 0:19 CBM: Bit vector of available L3 ways for COS 2 enforcement. 63:20 Reserved MODEL-SPECIFIC REGISTERS (MSRS) Table 2-45. MSRs Supported by Intel® Xeon® Processor Scalable Family with DisplayFamily_DisplayModel 06_55H Register Address Hex Dec C93H 3219 Register Name / Bit Fields IA32_L3_QOS_MASK_3 Scope Package Bit Description L3 Class Of Service Mask - COS 3 (R/W). If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=3. C94H 3220 0:19 CBM: Bit vector of available L3 ways for COS 3 enforcement. 63:20 Reserved IA32_L3_QOS_MASK_4 Package L3 Class Of Service Mask - COS 4 (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=4. C95H 3221 0:19 CBM: Bit vector of available L3 ways for COS 4 enforcement. 63:20 Reserved IA32_L3_QOS_MASK_5 Package L3 Class Of Service Mask - COS 5 (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=5. C96H 3222 0:19 CBM: Bit vector of available L3 ways for COS 5 enforcement. 63:20 Reserved IA32_L3_QOS_MASK_6 Package L3 Class Of Service Mask - COS 6 (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=6. C97H 3223 0:19 CBM: Bit vector of available L3 ways for COS 6 enforcement. 63:20 Reserved IA32_L3_QOS_MASK_7 Package L3 Class Of Service Mask - COS 7 (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=7. C98H 3224 0:19 CBM: Bit vector of available L3 ways for COS 7 enforcement. 63:20 Reserved IA32_L3_QOS_MASK_8 Package L3 Class Of Service Mask - COS 8 (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=8. C99H 3225 0:19 CBM: Bit vector of available L3 ways for COS 8 enforcement. 63:20 Reserved IA32_L3_QOS_MASK_9 Package L3 Class Of Service Mask - COS 9 (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=9. C9AH 3226 0:19 CBM: Bit vector of available L3 ways for COS 9 enforcement. 63:20 Reserved IA32_L3_QOS_MASK_10 Package L3 Class Of Service Mask - COS 10 (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=10. 0:19 CBM: Bit vector of available L3 ways for COS 10 enforcement. 63:20 Reserved Vol. 4 2-307 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-45. MSRs Supported by Intel® Xeon® Processor Scalable Family with DisplayFamily_DisplayModel 06_55H Register Address Hex Dec C9BH 3227 Register Name / Bit Fields IA32_L3_QOS_MASK_11 Scope Package Bit Description L3 Class Of Service Mask - COS 11 (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=11. C9CH 3228 0:19 CBM: Bit vector of available L3 ways for COS 11 enforcement. 63:20 Reserved IA32_L3_QOS_MASK_12 Package L3 Class Of Service Mask - COS 12 (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=12. C9DH 3229 0:19 CBM: Bit vector of available L3 ways for COS 12 enforcement. 63:20 Reserved IA32_L3_QOS_MASK_13 Package L3 Class Of Service Mask - COS 13 (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=13. C9EH 3230 0:19 CBM: Bit vector of available L3 ways for COS 13 enforcement. 63:20 Reserved IA32_L3_QOS_MASK_14 Package L3 Class Of Service Mask - COS 14 (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=14. C9FH 3231 0:19 CBM: Bit vector of available L3 ways for COS 14 enforcement. 63:20 Reserved IA32_L3_QOS_MASK_15 Package L3 Class Of Service Mask - COS 15 (R/W) If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=15. 2.18 0:19 CBM: Bit vector of available L3 ways for COS 15 enforcement. 63:20 Reserved MSRS IN INTEL® XEON PHI™ PROCESSOR 3200/5200/7200 SERIES AND INTEL® XEON PHI™ PROCESSOR 7215/7285/7295 SERIES Intel® Xeon Phi™ processor 3200, 5200, 7200 series, with CPUID DisplayFamily_DisplayModel signature 06_57H, supports the MSR interfaces listed in Table 2-46. These processors are based on the Knights Landing microarchitecture. Intel® Xeon Phi™ processor 7215, 7285, 7295 series, with CPUID DisplayFamily_DisplayModel signature 06_85H, supports the MSR interfaces listed in Table 2-46 and Table 2-47. These processors are based on the Knights Mill microarchitecture. Some MSRs are shared between a pair of processor cores, the scope is marked as module. 2-308 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-46. Selected MSRs Supported by Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signatures 06_57H and 06_85H Register Address Register Name / Bit Fields Scope Bit Description Hex Dec 0H 0 IA32_P5_MC_ADDR Module See Section 2.23, “MSRs in Pentium Processors.” 1H 1 IA32_P5_MC_TYPE Module See Section 2.23, “MSRs in Pentium Processors.” 6H 6 IA32_MONITOR_FILTER_SIZE Thread See Section 8.10.5, “Monitor/Mwait Address Range Determination.” See Table 2-2. 10H 16 IA32_TIME_STAMP_COUNTER Thread See Section 17.17, “Time-Stamp Counter,” and see Table 2-2. 17H 23 IA32_PLATFORM_ID Package Platform ID (R) See Table 2-2. 1BH 27 IA32_APIC_BASE Thread See Section 10.4.4, “Local APIC Status and Location,” and Table 2-2. 34H 52 MSR_SMI_COUNT Thread SMI Counter (R/O) 3AH 58 31:0 SMI Count (R/O) 63:32 Reserved IA32_FEATURE_CONTROL Thread Control Features in Intel 64Processor (R/W) See Table 2-2. 3BH 59 0 Lock (R/WL) 1 Reserved 2 Enable VMX outside SMX operation (R/WL) IA32_TSC_ADJUST THREAD Per-Logical-Processor TSC ADJUST (R/W) See Table 2-2. 4EH 78 MSR_PPIN_CTL Package 0 Protected Processor Inventory Number Enable Control (R/W) LockOut (R/WO) Set 1 to prevent further writes to MSR_PPIN_CTL. Writing 1 to MSR_PPINCTL[bit 0] is permitted only if MSR_PPIN_CTL[bit 1] is clear. Default is 0. BIOS should provide an opt-in menu to enable the user to turn on MSR_PPIN_CTL[bit 1] for a privileged inventory initialization agent to access MSR_PPIN. After reading MSR_PPIN, the privileged inventory initialization agent should write ‘01b’ to MSR_PPIN_CTL to disable further access to MSR_PPIN and prevent unauthorized modification to MSR_PPIN_CTL. 1 Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible using RDMSR. Once set, an attempt to write 1 to MSR_PPIN_CTL[bit 0] will cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP. Default is 0. 63:2 4FH 79 MSR_PPIN Reserved Package Protected Processor Inventory Number (R/O) Vol. 4 2-309 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-46. Selected MSRs Supported by Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signatures 06_57H and 06_85H Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 63:0 Protected Processor Inventory Number (R/O) A unique value within a given CPUID family/model/stepping signature that a privileged inventory initialization agent can access to identify each physical processor, when access to MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if MSR_PPIN_CTL[bits 1:0] = ‘10b’. 79H 121 IA32_BIOS_UPDT_TRIG Core BIOS Update Trigger Register (W) See Table 2-2. 8BH 139 IA32_BIOS_SIGN_ID THREAD BIOS Update Signature ID (RO) See Table 2-2. C1H 193 IA32_PMC0 THREAD Performance Counter Register See Table 2-2. C2H 194 IA32_PMC1 THREAD Performance Counter Register See Table 2-2. CEH 206 MSR_PLATFORM_INFO Package Platform Information Contains power management and other model specific features enumeration. See http://biosbits.org. 7:0 15:8 Reserved Package Maximum Non-Turbo Ratio (R/O) This is the ratio of the frequency that invariant TSC runs at. Frequency = ratio * 100 MHz. 27:16 28 Reserved Package Programmable Ratio Limit for Turbo Mode (R/O) When set to 1, indicates that Programmable Ratio Limit for Turbo mode is enabled. When set to 0, indicates Programmable Ratio Limit for Turbo mode is disabled. 29 Package Programmable TDP Limit for Turbo Mode (R/O) When set to 1, indicates that TDP Limit for Turbo mode is programmable. When set to 0, indicates TDP Limit for Turbo mode is not programmable. 39:30 47:40 Reserved Package Maximum Efficiency Ratio (R/O) This is the minimum ratio (maximum efficiency) that the processor can operate, in units of 100MHz. 63:48 E2H 2-310 Vol. 4 226 MSR_PKG_CST_CONFIG_CONTROL Reserved Package C-State Configuration Control (R/W) MODEL-SPECIFIC REGISTERS (MSRS) Table 2-46. Selected MSRs Supported by Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signatures 06_57H and 06_85H Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 2:0 Package C-State Limit (R/W) Specifies the lowest C-state for the package. This feature does not limit the processor core C-state. The power-on default value from bit[2:0] of this register reports the deepest package C-state the processor is capable to support when manufactured. It is recommended that BIOS always read the power-on default value reported from this bit field to determine the supported deepest C-state on the processor and leave it as default without changing it. 000b - C0/C1 (No package C-state support) 001b - C2 010b - C6 (non retention)* 011b - C6 (Retention)* 100b - Reserved 101b - Reserved 110b - Reserved 111b - No package C-state limit. All C-States supported by the processor are available. Note: C6 retention mode provides more power saving than C6 non-retention mode. Limiting the package to C6 non retention mode does prevent the MSR_PKG_C6_RESIDENCY counter (MSR 3F9h) from being incremented. 9:3 Reserved 10 I/O MWAIT Redirection Enable (R/W) When set, will map IO_read instructions sent to IO registers at MSR_PMG_IO_CAPTURE_BASE[15:0] to MWAIT instructions. 14:11 Reserved 15 CFG Lock (RO) When set, locks bits [15:0] of this register for further writes until the next reset occurs. 25 Reserved 26 C1 State Auto Demotion Enable (R/W) When set, the processor will conditionally demote C3/C6/C7 requests to C1 based on uncore auto-demote information. 27 Reserved 28 C1 State Auto Undemotion Enable (R/W) When set, enables Undemotion from Demoted C1. 29 PKG C-State Auto Demotion Enable (R/W) When set, enables Package C state demotion. 63:30 Reserved Vol. 4 2-311 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-46. Selected MSRs Supported by Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signatures 06_57H and 06_85H Register Address Hex Dec E4H 228 Register Name / Bit Fields MSR_PMG_IO_CAPTURE_BASE Scope Tile 15:0 Bit Description Power Management IO Capture Base (R/W) LVL_2 Base Address (R/W) Microcode will compare IO-read zone to this base address to determine if an MWAIT(C2/3/4) needs to be issued instead of the IO-read. Should be programmed to the chipset Plevel_2 IO address. 22:16 C-State Range (R/W) The IO-port block size in which IO-redirection will be executed (0-127). Should be programmed based on the number of LVLx registers existing in the chipset. 63:23 Reserved E7H 231 IA32_MPERF Thread E8H 232 IA32_APERF Thread Maximum Performance Frequency Clock Count (RW) See Table 2-2. Actual Performance Frequency Clock Count (RW) See Table 2-2. FEH 254 IA32_MTRRCAP Core 13CH 52 MSR_FEATURE_CONFIG Core Memory Type Range Register (R) See Table 2-2. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP handler to handle unsuccessful read of this MSR. 1:0 AES Configuration (RW-L) Upon a successful read of this MSR, the configuration of AES instruction set availability is as follows: 11b: AES instructions are not available until next RESET. Otherwise, AES instructions are available. Note, the AES instruction set is not available if read is unsuccessful. If the configuration is not 01b, AES instructions can be mis-configured if a privileged agent unintentionally writes 11b. 63:2 140H 320 MISC_FEATURE_ENABLES Reserved Thread MISC_FEATURE_ENABLES 0 Reserved 1 User Mode MONITOR and MWAIT (R/W) If set to 1, the MONITOR and MWAIT instructions do not cause invalid-opcode exceptions when executed with CPL > 0 or in virtual-8086 mode. If MWAIT is executed when CPL > 0 or in virtual-8086 mode, and if EAX indicates a C-state other than C0 or C1, the instruction operates as if EAX indicated the C-state C1. 63:2 Reserved 174H 372 IA32_SYSENTER_CS Thread See Table 2-2. 175H 373 IA32_SYSENTER_ESP Thread See Table 2-2. 2-312 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-46. Selected MSRs Supported by Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signatures 06_57H and 06_85H Register Address Register Name / Bit Fields Scope Bit Description Hex Dec 176H 374 IA32_SYSENTER_EIP Thread See Table 2-2. 179H 377 IA32_MCG_CAP Thread See Table 2-2. 17AH 378 IA32_MCG_STATUS Thread See Table 2-2. 17DH 390 MSR_SMM_MCA_CAP Thread Enhanced SMM Capabilities (SMM-RO) Reports SMM capability Enhancement. Accessible only while in SMM. 31:0 Bank Support (SMM-RO) One bit per MCA bank. If the bit is set, that bank supports Enhanced MCA (Default all 0; does not support EMCA). 55:32 Reserved 56 Targeted SMI (SMM-RO) Set if targeted SMI is supported. 57 SMM_CPU_SVRSTR (SMM-RO) Set if SMM SRAM save/restore feature is supported. 58 SMM_CODE_ACCESS_CHK (SMM-RO) Set if SMM code access check feature is supported. 59 Long_Flow_Indication (SMM-RO) If set to 1, indicates that the SMM long flow indicator is supported and a host-space interface available to SMM handler. 63:60 186H 390 IA32_PERFEVTSEL0 Reserved Thread Performance Monitoring Event Select Register (R/W) See Table 2-2. 7:0 Event Select 15:8 UMask 16 USR 17 OS 18 Edge 19 PC 20 INT 21 AnyThread 22 EN 23 INV 31:24 CMASK 63:32 Reserved 187H 391 IA32_PERFEVTSEL1 Thread See Table 2-2. 198H 408 IA32_PERF_STATUS Package See Table 2-2. Vol. 4 2-313 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-46. Selected MSRs Supported by Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signatures 06_57H and 06_85H Register Address Register Name / Bit Fields Scope Bit Description Hex Dec 199H 409 IA32_PERF_CTL Thread See Table 2-2. 19AH 410 IA32_CLOCK_MODULATION Thread Clock Modulation (R/W) See Table 2-2. 19BH 411 IA32_THERM_INTERRUPT Module Thermal Interrupt Control (R/W) See Table 2-2. 19CH 412 IA32_THERM_STATUS Module Thermal Monitor Status (R/W) See Table 2-2. 1A0H 416 0 Thermal Status (RO) 1 Thermal Status Log (R/WC0) 2 PROTCHOT # or FORCEPR# Status (RO) 3 PROTCHOT # or FORCEPR# Log (R/WC0) 4 Critical Temperature Status (RO) 5 Critical Temperature Status Log (R/WC0) 6 Thermal Threshold #1 Status (RO) 7 Thermal Threshold #1 Log (R/WC0) 8 Thermal Threshold #2 Status (RO) 9 Thermal Threshold #2 Log (R/WC0) 10 Power Limitation Status (RO) 11 Power Limitation Log (RWC0) 15:12 Reserved 22:16 Digital Readout (RO) 26:23 Reserved 30:27 Resolution in Degrees Celsius (RO) 31 Reading Valid (RO) 63:32 Reserved IA32_MISC_ENABLE Thread Enable Misc. Processor Features (R/W) Allows a variety of processor functions to be enabled and disabled. 2-314 Vol. 4 0 Fast-Strings Enable 2:1 Reserved 3 Automatic Thermal Control Circuit Enable (R/W) 6:4 Reserved 7 Performance Monitoring Available (R) 10:8 Reserved 11 Branch Trace Storage Unavailable (RO) 12 Processor Event Based Sampling Unavailable (RO) 15:13 Reserved MODEL-SPECIFIC REGISTERS (MSRS) Table 2-46. Selected MSRs Supported by Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signatures 06_57H and 06_85H Register Address Hex 1A2H 1A4H Register Name / Bit Fields Scope Bit Description Dec 418 420 16 Enhanced Intel SpeedStep Technology Enable (R/W) 18 ENABLE MONITOR FSM (R/W) 21:19 Reserved 22 Limit CPUID Maxval (R/W) 23 xTPR Message Disable (R/W) 33:24 Reserved 34 XD Bit Disable (R/W) 37:35 Reserved 38 Turbo Mode Disable (R/W) 63:39 Reserved MSR_TEMPERATURE_TARGET Package Temperature Target 15:0 Reserved 23:16 Temperature Target (R) 29:24 Target Offset (R/W) 63:30 Reserved MSR_MISC_FEATURE_CONTROL Miscellaneous Feature Control (R/W) 0 Core DCU Hardware Prefetcher Disable (R/W) If 1, disables the L1 data cache prefetcher. 1 Core L2 Hardware Prefetcher Disable (R/W) If 1, disables the L2 hardware prefetcher. 63:2 Reserved 1A6H 422 MSR_OFFCORE_RSP_0 Shared Offcore Response Event Select Register (R/W) 1A7H 423 MSR_OFFCORE_RSP_1 Shared Offcore Response Event Select Register (R/W) 1ADH 429 MSR_TURBO_RATIO_LIMIT Package Maximum Ratio Limit of Turbo Mode for Groups of Cores (RW) 0 7:1 Reserved Package Maximum Number of Cores in Group 0 Number active processor cores which operates under the maximum ratio limit for group 0. 15:8 Package Maximum Ratio Limit for Group 0 Maximum turbo ratio limit when the number of active cores are not more than the group 0 maximum core count. 20:16 Package Number of Incremental Cores Added to Group 1 Group 1, which includes the specified number of additional cores plus the cores in group 0, operates under the group 1 turbo max ratio limit = “group 0 Max ratio limit” - “group ratio delta for group 1”. Vol. 4 2-315 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-46. Selected MSRs Supported by Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signatures 06_57H and 06_85H Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 23:21 Package Group Ratio Delta for Group 1 An unsigned integer specifying the ratio decrement relative to the Max ratio limit to Group 0. 28:24 Package Number of Incremental Cores Added to Group 2 Group 2, which includes the specified number of additional cores plus all the cores in group 1, operates under the group 2 turbo max ratio limit = “group 1 Max ratio limit” - “group ratio delta for group 2”. 31:29 Package Group Ratio Delta for Group 2 An unsigned integer specifying the ratio decrement relative to the Max ratio limit for Group 1. 36:32 Package Number of Incremental Cores Added to Group 3 Group 3, which includes the specified number of additional cores plus all the cores in group 2, operates under the group 3 turbo max ratio limit = “group 2 Max ratio limit” - “group ratio delta for group 3”. 39:37 Package Group Ratio Delta for Group 3 An unsigned integer specifying the ratio decrement relative to the Max ratio limit for Group 2. 44:40 Package Number of Incremental Cores Added to Group 4 Group 4, which includes the specified number of additional cores plus all the cores in group 3, operates under the group 4 turbo max ratio limit = “group 3 Max ratio limit” - “group ratio delta for group 4”. 47:45 Package Group Ratio Delta for Group 4 An unsigned integer specifying the ratio decrement relative to the Max ratio limit for Group 3. 52:48 Package Number of Incremental Cores Added to Group 5 Group 5, which includes the specified number of additional cores plus all the cores in group 4, operates under the group 5 turbo max ratio limit = “group 4 Max ratio limit” - “group ratio delta for group 5”. 55:53 Package Group Ratio Delta for Group 5 An unsigned integer specifying the ratio decrement relative to the Max ratio limit for Group 4. 60:56 Package Number of Incremental Cores Added to Group 6 Group 6, which includes the specified number of additional cores plus all the cores in group 5, operates under the group 6 turbo max ratio limit = “group 5 Max ratio limit” - “group ratio delta for group 6”. 63:61 Package Group Ratio Delta for Group 6 An unsigned integer specifying the ratio decrement relative to the Max ratio limit for Group 5. 1B0H 2-316 Vol. 4 432 IA32_ENERGY_PERF_BIAS Thread See Table 2-2. MODEL-SPECIFIC REGISTERS (MSRS) Table 2-46. Selected MSRs Supported by Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signatures 06_57H and 06_85H Register Address Register Name / Bit Fields Scope Bit Description Hex Dec 1B1H 433 IA32_PACKAGE_THERM_STATUS Package See Table 2-2. 1B2H 434 IA32_PACKAGE_THERM_INTERRUPT Package See Table 2-2. 1C8H 456 MSR_LBR_SELECT Thread Last Branch Record Filtering Select Register (R/W) See Section 17.9.2, “Filtering of Last Branch Records.” 1C9H 457 0 CPL_EQ_0 1 CPL_NEQ_0 2 JCC 3 NEAR_REL_CALL 4 NEAR_IND_CALL 5 NEAR_RET 6 NEAR_IND_JMP 7 NEAR_REL_JMP 8 FAR_BRANCH 63:9 Reserved MSR_LASTBRANCH_TOS Thread Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2) that points to the MSR containing the most recent branch record. See MSR_LASTBRANCH_0_FROM_IP. 1D9H 473 IA32_DEBUGCTL 0 Thread Debug Control (R/W) LBR Setting this bit to 1 enables the processor to record a running trace of the most recent branches taken by the processor in the LBR stack. 1 BTF Setting this bit to 1 enables the processor to treat EFLAGS.TF as single-step on branches instead of singlestep on instructions. 5:2 Reserved 6 TR Setting this bit to 1 enables branch trace messages to be sent. 7 BTS Setting this bit enables branch trace messages (BTMs) to be logged in a BTS buffer. 8 BTINT When clear, BTMs are logged in a BTS buffer in circular fashion. When this bit is set, an interrupt is generated by the BTS facility when the BTS buffer is full. 9 BTS_OFF_OS When set, BTS or BTM is skipped if CPL = 0. Vol. 4 2-317 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-46. Selected MSRs Supported by Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signatures 06_57H and 06_85H Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 10 BTS_OFF_USR When set, BTS or BTM is skipped if CPL > 0. 11 FREEZE_LBRS_ON_PMI When set, the LBR stack is frozen on a PMI request. 12 FREEZE_PERFMON_ON_PMI When set, each ENABLE bit of the global counter control MSR are frozen (address 3BFH) on a PMI request. 13 Reserved 14 FREEZE_WHILE_SMM When set, freezes perfmon and trace messages while in SMM. 31:15 Reserved 1DDH 477 MSR_LER_FROM_LIP Thread Last Exception Record from Linear IP (R) 1DEH 478 MSR_LER_TO_LIP Thread Last Exception Record to Linear IP (R) 1F2H 498 IA32_SMRR_PHYSBASE Core See Table 2-2. 1F3H 499 IA32_SMRR_PHYSMASK Core See Table 2-2. 200H 512 IA32_MTRR_PHYSBASE0 Core See Table 2-2. 201H 513 IA32_MTRR_PHYSMASK0 Core See Table 2-2. 202H 514 IA32_MTRR_PHYSBASE1 Core See Table 2-2. 203H 515 IA32_MTRR_PHYSMASK1 Core See Table 2-2. 204H 516 IA32_MTRR_PHYSBASE2 Core See Table 2-2. 205H 517 IA32_MTRR_PHYSMASK2 Core See Table 2-2. 206H 518 IA32_MTRR_PHYSBASE3 Core See Table 2-2. 207H 519 IA32_MTRR_PHYSMASK3 Core See Table 2-2. 208H 520 IA32_MTRR_PHYSBASE4 Core See Table 2-2. 209H 521 IA32_MTRR_PHYSMASK4 Core See Table 2-2. 20AH 522 IA32_MTRR_PHYSBASE5 Core See Table 2-2. 20BH 523 IA32_MTRR_PHYSMASK5 Core See Table 2-2. 20CH 524 IA32_MTRR_PHYSBASE6 Core See Table 2-2. 20DH 525 IA32_MTRR_PHYSMASK6 Core See Table 2-2. 20EH 526 IA32_MTRR_PHYSBASE7 Core See Table 2-2. 20FH 527 IA32_MTRR_PHYSMASK7 Core See Table 2-2. 250H 592 IA32_MTRR_FIX64K_00000 Core See Table 2-2. 258H 600 IA32_MTRR_FIX16K_80000 Core See Table 2-2. 259H 601 IA32_MTRR_FIX16K_A0000 Core See Table 2-2. 268H 616 IA32_MTRR_FIX4K_C0000 Core See Table 2-2. 269H 617 IA32_MTRR_FIX4K_C8000 Core See Table 2-2. 2-318 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-46. Selected MSRs Supported by Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signatures 06_57H and 06_85H Register Address Register Name / Bit Fields Scope Bit Description Hex Dec 26AH 618 IA32_MTRR_FIX4K_D0000 Core See Table 2-2. 26BH 619 IA32_MTRR_FIX4K_D8000 Core See Table 2-2. 26CH 620 IA32_MTRR_FIX4K_E0000 Core See Table 2-2. 26DH 621 IA32_MTRR_FIX4K_E8000 Core See Table 2-2. 26EH 622 IA32_MTRR_FIX4K_F0000 Core See Table 2-2. 26FH 623 IA32_MTRR_FIX4K_F8000 Core See Table 2-2. 277H 631 IA32_PAT Core See Table 2-2. 2FFH 767 IA32_MTRR_DEF_TYPE Core Default Memory Types (R/W) See Table 2-2. 309H 777 IA32_FIXED_CTR0 Thread Fixed-Function Performance Counter Register 0 (R/W) See Table 2-2. 30AH 778 IA32_FIXED_CTR1 Thread Fixed-Function Performance Counter Register 1 (R/W) See Table 2-2. 30BH 779 IA32_FIXED_CTR2 Thread Fixed-Function Performance Counter Register 2 (R/W) See Table 2-2. 345H 837 IA32_PERF_CAPABILITIES Package See Table 2-2. See Section 17.4.1, “IA32_DEBUGCTL MSR.” 38DH 909 IA32_FIXED_CTR_CTRL Thread Fixed-Function-Counter Control Register (R/W) See Table 2-2. 38EH 910 IA32_PERF_GLOBAL_STATUS Thread See Table 2-2. 38FH 911 IA32_PERF_GLOBAL_CTRL Thread See Table 2-2. 390H 912 IA32_PERF_GLOBAL_OVF_CTRL Thread See Table 2-2. 3F1H 1009 MSR_PEBS_ENABLE Thread See Table 2-2. 3F8H 1016 MSR_PKG_C3_RESIDENCY Package Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-states. 63:0 3F9H 1017 MSR_PKG_C6_RESIDENCY Package C3 Residency Counter (R/O) Package 63:0 3FAH 1018 MSR_PKG_C7_RESIDENCY Package C6 Residency Counter (R/O) Package 63:0 3FCH 1020 MSR_MC0_RESIDENCY 3FDH 1021 MSR_MC6_RESIDENCY Package C7 Residency Counter (R/O) Module 63:0 63:0 Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-states. Module C0 Residency Counter (R/O) Module Module C6 Residency Counter (R/O) Vol. 4 2-319 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-46. Selected MSRs Supported by Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signatures 06_57H and 06_85H Register Address Hex Dec 3FFH 1023 Register Name / Bit Fields MSR_CORE_C6_RESIDENCY Scope Core 63:0 Bit Description Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-states. CORE C6 Residency Counter (R/O) 400H 1024 IA32_MC0_CTL Core See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 401H 1025 IA32_MC0_STATUS Core See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 402H 1026 IA32_MC0_ADDR Core See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 404H 1028 IA32_MC1_CTL Core See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 405H 1029 IA32_MC1_STATUS Core See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 408H 1032 IA32_MC2_CTL Core See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 409H 1033 IA32_MC2_STATUS Core See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 40AH 1034 IA32_MC2_ADDR Core See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 40CH 1036 IA32_MC3_CTL Core See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 40DH 1037 IA32_MC3_STATUS Core See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 40EH 1038 IA32_MC3_ADDR Core See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 410H 1040 IA32_MC4_CTL Core See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 411H 1041 IA32_MC4_STATUS Core See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 412H 1042 IA32_MC4_ADDR Core See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” The MSR_MC4_ADDR register is either not implemented or contains no address if the ADDRV flag in the MSR_MC4_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 414H 1044 IA32_MC5_CTL Package See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 415H 1045 IA32_MC5_STATUS Package See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 416H 1046 IA32_MC5_ADDR Package See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 4C1H 1217 IA32_A_PMC0 Thread See Table 2-2. 4C2H 1218 IA32_A_PMC1 Thread See Table 2-2. 600H 1536 IA32_DS_AREA Thread DS Save Area (R/W) See Table 2-2. 606H 1542 MSR_RAPL_POWER_UNIT Package Unit Multipliers Used in RAPL Interfaces (R/O) 3:0 Package Power Units See Section 14.9.1, “RAPL Interfaces.” 7:4 2-320 Vol. 4 Package Reserved MODEL-SPECIFIC REGISTERS (MSRS) Table 2-46. Selected MSRs Supported by Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signatures 06_57H and 06_85H Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 12:8 Package Energy Status Units Energy related information (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an unsigned integer represented by bits 12:8. Default value is 0EH (or 61 micro-joules). 15:13 Package 19:16 Package Reserved Time Units See Section 14.9.1, “RAPL Interfaces.” 63:20 60DH 1549 MSR_PKG_C2_RESIDENCY Reserved Package 63:0 610H 1552 MSR_PKG_POWER_LIMIT Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-states. Package C2 Residency Counter (R/O) Package PKG RAPL Power Limit Control (R/W) See Section 14.9.3, “Package RAPL Domain.” 611H 1553 MSR_PKG_ENERGY_STATUS Package PKG Energy Status (R/O) See Section 14.9.3, “Package RAPL Domain.” 613H 1555 MSR_PKG_PERF_STATUS Package PKG Perf Status (R/O) See Section 14.9.3, “Package RAPL Domain.” 614H 1556 MSR_PKG_POWER_INFO Package PKG RAPL Parameters (R/W) See Section 14.9.3, “Package RAPL Domain.” 618H 1560 MSR_DRAM_POWER_LIMIT Package DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, “DRAM RAPL Domain.” 619H 1561 MSR_DRAM_ENERGY_STATUS Package DRAM Energy Status (R/O) See Section 14.9.5, “DRAM RAPL Domain.” 61BH 1563 MSR_DRAM_PERF_STATUS Package DRAM Performance Throttling Status (R/O) See Section 14.9.5, “DRAM RAPL Domain.” 61CH 1564 MSR_DRAM_POWER_INFO Package DRAM RAPL Parameters (R/W) See Section 14.9.5, “DRAM RAPL Domain.” 620H 1568 MSR UNCORE_RATIO_LIMIT Package Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio fields represent the widest possible range of uncore frequencies. Writing to these fields allows software to control the minimum and the maximum frequency that hardware will select. 63:15 14:8 Reserved MIN_RATIO Writing to this field controls the minimum possible ratio of the LLC/Ring. 7 Reserved Vol. 4 2-321 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-46. Selected MSRs Supported by Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signatures 06_57H and 06_85H Register Address Hex Register Name / Bit Fields Scope Bit Description Dec 6:0 MAX_RATIO This field is used to limit the max ratio of the LLC/Ring. 638H 1592 MSR_PP0_POWER_LIMIT Package PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, “PP0/PP1 RAPL Domains.” 639H 1593 MSR_PP0_ENERGY_STATUS Package PP0 Energy Status (R/O) See Section 14.9.4, “PP0/PP1 RAPL Domains.” 648H 1608 MSR_CONFIG_TDP_NOMINAL Package Base TDP Ratio (R/O) See Table 2-25. 649H 1609 MSR_CONFIG_TDP_LEVEL1 Package ConfigTDP Level 1 ratio and power level (R/O) See Table 2-25. 64AH 1610 MSR_CONFIG_TDP_LEVEL2 Package ConfigTDP Level 2 ratio and power level (R/O) See Table 2-25. 64BH 1611 MSR_CONFIG_TDP_CONTROL Package ConfigTDP Control (R/W) See Table 2-25. 64CH 1612 MSR_TURBO_ACTIVATION_RATIO Package ConfigTDP Control (R/W) See Table 2-25. 690H 1680 MSR_CORE_PERF_LIMIT_REASONS Package Indicator of Frequency Clipping in Processor Cores (R/W) (Frequency refers to processor core frequency.) 6E0H 1760 0 PROCHOT Status (R0) 1 Thermal Status (R0) 5:2 Reserved 6 VR Therm Alert Status (R0) 7 Reserved 8 Electrical Design Point Status (R0) 63:9 Reserved IA32_TSC_DEADLINE Core TSC Target of Local APIC’s TSC Deadline Mode (R/W) See Table 2-2. 802H 2050 IA32_X2APIC_APICID Thread x2APIC ID Register (R/O) 803H 2051 IA32_X2APIC_VERSION Thread x2APIC Version Register (R/O) 808H 2056 IA32_X2APIC_TPR Thread x2APIC Task Priority Register (R/W) 80AH 2058 IA32_X2APIC_PPR Thread x2APIC Processor Priority Register (R/O) 80BH 2059 IA32_X2APIC_EOI Thread x2APIC EOI Register (W/O) 80DH 2061 IA32_X2APIC_LDR Thread x2APIC Logical Destination Register (R/O) 80FH 2063 IA32_X2APIC_SIVR Thread x2APIC Spurious Interrupt Vector Register (R/W) 810H 2064 IA32_X2APIC_ISR0 Thread x2APIC In-Service Register Bits [31:0] (R/O) 811H 2065 IA32_X2APIC_ISR1 Thread x2APIC In-Service Register Bits [63:32] (R/O) 812H 2066 IA32_X2APIC_ISR2 Thread x2APIC In-Service Register Bits [95:64] (R/O) 2-322 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-46. Selected MSRs Supported by Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signatures 06_57H and 06_85H Register Address Register Name / Bit Fields Scope Bit Description Hex Dec 813H 2067 IA32_X2APIC_ISR3 Thread x2APIC In-Service Register Bits [127:96] (R/O) 814H 2068 IA32_X2APIC_ISR4 Thread x2APIC In-Service Register Bits [159:128] (R/O) 815H 2069 IA32_X2APIC_ISR5 Thread x2APIC In-Service Register Bits [191:160] (R/O) 816H 2070 IA32_X2APIC_ISR6 Thread x2APIC In-Service Register Bits [223:192] (R/O) 817H 2071 IA32_X2APIC_ISR7 Thread x2APIC In-Service Register Bits [255:224] (R/O) 818H 2072 IA32_X2APIC_TMR0 Thread x2APIC Trigger Mode Register Bits [31:0] (R/O) 819H 2073 IA32_X2APIC_TMR1 Thread x2APIC Trigger Mode Register Bits [63:32] (R/O) 81AH 2074 IA32_X2APIC_TMR2 Thread x2APIC Trigger Mode Register Bits [95:64] (R/O) 81BH 2075 IA32_X2APIC_TMR3 Thread x2APIC Trigger Mode Register Bits [127:96] (R/O) 81CH 2076 IA32_X2APIC_TMR4 Thread x2APIC Trigger Mode Register Bits [159:128] (R/O) 81DH 2077 IA32_X2APIC_TMR5 Thread x2APIC Trigger Mode Register Bits [191:160] (R/O) 81EH 2078 IA32_X2APIC_TMR6 Thread x2APIC Trigger Mode Register Bits [223:192] (R/O) 81FH 2079 IA32_X2APIC_TMR7 Thread x2APIC Trigger Mode Register Bits [255:224] (R/O) 820H 2080 IA32_X2APIC_IRR0 Thread x2APIC Interrupt Request Register Bits [31:0] (R/O) 821H 2081 IA32_X2APIC_IRR1 Thread x2APIC Interrupt Request Register Bits [63:32] (R/O) 822H 2082 IA32_X2APIC_IRR2 Thread x2APIC Interrupt Request Register Bits [95:64] (R/O) 823H 2083 IA32_X2APIC_IRR3 Thread x2APIC Interrupt Request Register Bits [127:96] (R/O) 824H 2084 IA32_X2APIC_IRR4 Thread x2APIC Interrupt Request Register Bits [159:128] (R/O) 825H 2085 IA32_X2APIC_IRR5 Thread x2APIC Interrupt Request Register Bits [191:160] (R/O) 826H 2086 IA32_X2APIC_IRR6 Thread x2APIC Interrupt Request Register Bits [223:192] (R/O) 827H 2087 IA32_X2APIC_IRR7 Thread x2APIC Interrupt Request Register Bits [255:224] (R/O) 828H 2088 IA32_X2APIC_ESR Thread x2APIC Error Status Register (R/W) 82FH 2095 IA32_X2APIC_LVT_CMCI Thread x2APIC LVT Corrected Machine Check Interrupt Register (R/W) 830H 2096 IA32_X2APIC_ICR Thread x2APIC Interrupt Command Register (R/W) 832H 2098 IA32_X2APIC_LVT_TIMER Thread x2APIC LVT Timer Interrupt Register (R/W) 833H 2099 IA32_X2APIC_LVT_THERMAL Thread x2APIC LVT Thermal Sensor Interrupt Register (R/W) 834H 2100 IA32_X2APIC_LVT_PMI Thread x2APIC LVT Performance Monitor Register (R/W) 835H 2101 IA32_X2APIC_LVT_LINT0 Thread x2APIC LVT LINT0 Register (R/W) 836H 2102 IA32_X2APIC_LVT_LINT1 Thread x2APIC LVT LINT1 Register (R/W) 837H 2103 IA32_X2APIC_LVT_ERROR Thread x2APIC LVT Error Register (R/W) 838H 2104 IA32_X2APIC_INIT_COUNT Thread x2APIC Initial Count Register (R/W) 839H 2105 IA32_X2APIC_CUR_COUNT Thread x2APIC Current Count Register (R/O) 83EH 2110 IA32_X2APIC_DIV_CONF Thread x2APIC Divide Configuration Register (R/W) 83FH 2111 IA32_X2APIC_SELF_IPI Thread x2APIC Self IPI Register (W/O) Vol. 4 2-323 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-46. Selected MSRs Supported by Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signatures 06_57H and 06_85H Register Address Hex Register Name / Bit Fields Scope Bit Description Dec C000_ 0080H IA32_EFER C000_ 0081H IA32_STAR C000_ 0082H IA32_LSTAR C000_ 0084H IA32_FMASK C000_ 0100H IA32_FS_BASE C000_ 0101H IA32_GS_BASE C000_ 0102H IA32_KERNEL_GS_BASE C000_ 0103H IA32_TSC_AUX Thread Extended Feature Enables See Table 2-2. Thread System Call Target Address (R/W) See Table 2-2. Thread IA-32e Mode System Call Target Address (R/W) See Table 2-2. Thread System Call Flag Mask (R/W) See Table 2-2. Thread Map of BASE Address of FS (R/W) See Table 2-2. Thread Map of BASE Address of GS (R/W) See Table 2-2. Thread Swap Target of BASE Address of GS (R/W) See Table 2-2. Thread AUXILIARY TSC Signature (R/W) See Table 2-2 Table 2-47 lists model-specific registers that are supported by Intel® Xeon Phi™ processor 7215, 7285, 7295 series based on the Knights Mill microarchitecture. Table 2-47. Additional MSRs Supported by Intel® Xeon Phi™ Processor 7215, 7285, 7295 Series with DisplayFamily_DisplayModel Signature 06_85H Register Address Hex Dec 9BH 155 Register Name / Bit Fields IA32_SMM_MONITOR_CTL Scope Core Bit Description SMM Monitor Configuration (R/W) This MSR is readable only if VMX is enabled, and writeable only if VMX is enabled and in SMM mode, and is used to configure the VMX MSEG base address. See Table 2-2. 480H 1152 IA32_VMX_BASIC Core Reporting Register of Basic VMX Capabilities (R/O) See Table 2-2. 481H 1153 IA32_VMX_PINBASED_ CTLS Core Capability Reporting Register of Pin-based VM-execution Controls (R/O) See Table 2-2. 482H 1154 IA32_VMX_PROCBASED_ CTLS Core 483H 1155 IA32_VMX_EXIT_CTLS Core Capability Reporting Register of Primary Processorbased VM-execution Controls (R/O) Capability Reporting Register of VM-exit Controls (R/O) See Table 2-2. 484H 1156 IA32_VMX_ENTRY_CTLS Core Capability Reporting Register of VM-entry Controls (R/O) See Table 2-2. 2-324 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-47. Additional MSRs Supported by Intel® Xeon Phi™ Processor 7215, 7285, 7295 Series with DisplayFamily_DisplayModel Signature 06_85H Register Address Register Name / Bit Fields Scope Hex Dec 485H 1157 IA32_VMX_MISC Core 486H 1158 IA32_VMX_CR0_FIXED0 Core Bit Description Reporting Register of Miscellaneous VMX Capabilities (R/O) See Table 2-2. Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Table 2-2. 487H 1159 IA32_VMX_CR0_FIXED1 Core Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Table 2-2. 488H 1160 IA32_VMX_CR4_FIXED0 Core Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Table 2-2. 489H 1161 IA32_VMX_CR4_FIXED1 Core Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) See Table 2-2. 48AH 1162 IA32_VMX_VMCS_ENUM Core Capability Reporting Register of VMCS Field Enumeration (R/O) See Table 2-2. 48BH 1163 IA32_VMX_PROCBASED_ CTLS2 Core Capability Reporting Register of Secondary ProcessorBased VM-Execution Controls (R/O) See Table 2-2. 48CH 1164 IA32_VMX_EPT_VPID_ENUM Core Capability Reporting Register of EPT and VPID (R/O) See Table 2-2. 48DH 1165 IA32_VMX_TRUE_PINBASE D_CTLS Core Capability Reporting Register of Pin-Based VM-Execution Flex Controls (R/O) See Table 2-2. 48EH 1166 IA32_VMX_TRUE_PROCBASED_CTLS Core Capability Reporting Register of Primary ProcessorBased VM-Execution Flex Controls (R/O) See Table 2-2. 48FH 1167 IA32_VMX_TRUE_EXIT_CTLS Core Capability Reporting Register of VM-Exit Flex Controls (R/O) See Table 2-2. 490H 1168 IA32_VMX_TRUE_ENTRY_CTLS Core Capability Reporting Register of VM-Entry Flex Controls (R/O) See Table 2-2. 491H 1169 IA32_VMX_FMFUNC Core Capability Reporting Register of VM-Function Controls (R/O) See Table 2-2. Vol. 4 2-325 MODEL-SPECIFIC REGISTERS (MSRS) 2.19 MSRS IN THE PENTIUM® 4 AND INTEL® XEON® PROCESSORS Table 2-48 lists MSRs (architectural and model-specific) that are defined across processor generations based on Intel NetBurst microarchitecture. The processor can be identified by its CPUID signatures of DisplayFamily encoding of 0FH, see Table 2-1. • MSRs with an “IA32_” prefix are designated as “architectural.” This means that the functions of these MSRs and their addresses remain the same for succeeding families of IA-32 processors. • MSRs with an “MSR_” prefix are model specific with respect to address functionalities. The column “Model Availability” lists the model encoding value(s) within the Pentium 4 and Intel Xeon processor family at the specified register address. The model encoding value of a processor can be queried using CPUID. See “CPUID—CPU Identification” in Chapter 3 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A. Table 2-48. MSRs in the Pentium® 4 and Intel® Xeon® Processors Register Address Register Name Fields and Flags Model Availability Shared/ Unique1 Bit Description Hex Dec 0H 0 IA32_P5_MC_ADDR 0, 1, 2, 3, 4, 6 Shared See Section 2.23, “MSRs in Pentium Processors.” 1H 1 IA32_P5_MC_TYPE 0, 1, 2, 3, 4, 6 Shared See Section 2.23, “MSRs in Pentium Processors.” 6H 6 IA32_MONITOR_FILTER_LINE_SIZE 3, 4, 6 Shared See Section 8.10.5, “Monitor/Mwait Address Range Determination.” 10H 16 IA32_TIME_STAMP_COUNTER 0, 1, 2, 3, 4, 6 Unique Time Stamp Counter See Table 2-2. On earlier processors, only the lower 32 bits are writable. On any write to the lower 32 bits, the upper 32 bits are cleared. For processor family 0FH, models 3 and 4: all 64 bits are writable. 17H 23 IA32_PLATFORM_ID 0, 1, 2, 3, 4, 6 Shared Platform ID (R) See Table 2-2. The operating system can use this MSR to determine “slot” information for the processor and the proper microcode update to load. 1BH 2AH 27 42 IA32_APIC_BASE MSR_EBC_HARD_POWERON 0, 1, 2, 3, 4, 6 Unique 0, 1, 2, 3, 4, 6 Shared APIC Location and Status (R/W) See Table 2-2. See Section 10.4.4, “Local APIC Status and Location.” Processor Hard Power-On Configuration (R/W) Enables and disables processor features. (R) Indicates current processor configuration. 0 Output Tri-state Enabled (R) Indicates whether tri-state output is enabled (1) or disabled (0) as set by the strapping of SMI#. The value in this bit is written on the deassertion of RESET#; the bit is set to 1 when the address bus signal is asserted. 2-326 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-48. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.) Register Address Hex Register Name Fields and Flags Dec 1 Model Availability Shared/ Unique1 Bit Description Execute BIST (R) Indicates whether the execution of the BIST is enabled (1) or disabled (0) as set by the strapping of INIT#. The value in this bit is written on the deassertion of RESET#; the bit is set to 1 when the address bus signal is asserted. 2 In Order Queue Depth (R) Indicates whether the in order queue depth for the system bus is 1 (1) or up to 12 (0) as set by the strapping of A7#. The value in this bit is written on the deassertion of RESET#; the bit is set to 1 when the address bus signal is asserted. 3 MCERR# Observation Disabled (R) Indicates whether MCERR# observation is enabled (0) or disabled (1) as determined by the strapping of A9#. The value in this bit is written on the deassertion of RESET#; the bit is set to 1 when the address bus signal is asserted. 4 BINIT# Observation Enabled (R) Indicates whether BINIT# observation is enabled (0) or disabled (1) as determined by the strapping of A10#. The value in this bit is written on the deassertion of RESET#; the bit is set to 1 when the address bus signal is asserted. 6:5 APIC Cluster ID (R) Contains the logical APIC cluster ID value as set by the strapping of A12# and A11#. The logical cluster ID value is written into the field on the deassertion of RESET#; the field is set to 1 when the address bus signal is asserted. 7 Bus Park Disable (R) Indicates whether bus park is enabled (0) or disabled (1) as set by the strapping of A15#. The value in this bit is written on the deassertion of RESET#; the bit is set to 1 when the address bus signal is asserted. 11:8 Reserved 13:12 Agent ID (R) Contains the logical agent ID value as set by the strapping of BR[3:0]. The logical ID value is written into the field on the deassertion of RESET#; the field is set to 1 when the address bus signal is asserted. 63:14 Reserved Vol. 4 2-327 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-48. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.) Register Address Hex Dec 2BH 43 Register Name Fields and Flags MSR_EBC_SOFT_POWERON Model Availability 0, 1, 2, 3, 4, 6 Shared/ Unique1 Shared Bit Description Processor Soft Power-On Configuration (R/W) Enables and disables processor features. 0 RCNT/SCNT On Request Encoding Enable (R/W) Controls the driving of RCNT/SCNT on the request encoding. Set to enable (1); clear to disabled (0, default). 1 Data Error Checking Disable (R/W) Set to disable system data bus parity checking; clear to enable parity checking. 2 Response Error Checking Disable (R/W) 3 Address/Request Error Checking Disable (R/W) Set to disable (default); clear to enable. Set to disable (default); clear to enable. 4 Initiator MCERR# Disable (R/W) Set to disable MCERR# driving for initiator bus requests (default); clear to enable. 5 Internal MCERR# Disable (R/W) Set to disable MCERR# driving for initiator internal errors (default); clear to enable. 6 BINIT# Driver Disable (R/W) Set to disable BINIT# driver (default); clear to enable driver. 63:7 2CH 44 MSR_EBC_FREQUENCY_ID Reserved 2,3, 4, 6 Shared Processor Frequency Configuration The bit field layout of this MSR varies according to the MODEL value in the CPUID version information. The following bit field layout applies to Pentium 4 and Xeon Processors with MODEL encoding equal or greater than 2. (R) The field Indicates the current processor frequency configuration. 15:0 Reserved 18:16 Scalable Bus Speed (R/W) Indicates the intended scalable bus speed: Encoding Scalable Bus Speed 000B 100 MHz (Model 2) 000B 266 MHz (Model 3 or 4) 001B 133 MHz 010B 200 MHz 011B 166 MHz 100B 333 MHz (Model 6) 2-328 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-48. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.) Register Address Hex Register Name Fields and Flags Dec Model Availability Shared/ Unique1 Bit Description 133.33 MHz should be utilized if performing calculation with System Bus Speed when encoding is 001B. 166.67 MHz should be utilized if performing calculation with System Bus Speed when encoding is 011B. 266.67 MHz should be utilized if performing calculation with System Bus Speed when encoding is 000B and model encoding = 3 or 4. 333.33 MHz should be utilized if performing calculation with System Bus Speed when encoding is 100B and model encoding = 6. All other values are reserved. 23:19 Reserved 31:24 Core Clock Frequency to System Bus Frequency Ratio (R) The processor core clock frequency to system bus frequency ratio observed at the deassertion of the reset pin. 63:25 2CH 44 MSR_EBC_FREQUENCY_ID Reserved 0, 1 Shared Processor Frequency Configuration (R) The bit field layout of this MSR varies according to the MODEL value of the CPUID version information. This bit field layout applies to Pentium 4 and Xeon Processors with MODEL encoding less than 2. Indicates current processor frequency configuration. 20:0 Reserved 23:21 Scalable Bus Speed (R/W) Indicates the intended scalable bus speed: Encoding Scalable Bus Speed 000B 100 MHz All others values reserved. 63:24 3AH 58 IA32_FEATURE_CONTROL Reserved 3, 4, 6 Unique Control Features in IA-32 Processor (R/W) See Table 2-2. (If CPUID.01H:ECX.[bit 5]) 79H 8BH 121 139 IA32_BIOS_UPDT_TRIG IA32_BIOS_SIGN_ID 0, 1, 2, 3, 4, 6 Shared 0, 1, 2, 3, 4, 6 Unique BIOS Update Trigger Register (W) See Table 2-2. BIOS Update Signature ID (R/W) See Table 2-2. Vol. 4 2-329 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-48. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.) Register Address Hex 9BH Register Name Fields and Flags Dec 155 IA32_SMM_MONITOR_CTL Model Availability 3, 4, 6 Shared/ Unique1 Unique Bit Description SMM Monitor Configuration (R/W) See Table 2-2. FEH 174H 254 372 IA32_MTRRCAP IA32_SYSENTER_CS 0, 1, 2, 3, 4, 6 Unique 0, 1, 2, 3, 4, 6 Unique MTRR Information See Section 11.11.1, “MTRR Feature Identification.”. CS Register Target for CPL 0 Code (R/W) See Table 2-2. See Section 5.8.7, “Performing Fast Calls to System Procedures with the SYSENTER and SYSEXIT Instructions.” 175H 373 IA32_SYSENTER_ESP 0, 1, 2, 3, 4, 6 Unique Stack Pointer for CPL 0 Stack (R/W) See Table 2-2. See Section 5.8.7, “Performing Fast Calls to System Procedures with the SYSENTER and SYSEXIT Instructions.” 176H 179H 17AH 17BH 374 377 378 379 IA32_SYSENTER_EIP IA32_MCG_CAP IA32_MCG_STATUS 0, 1, 2, 3, 4, 6 Unique 0, 1, 2, 3, 4, 6 Unique 0, 1, 2, 3, 4, 6 Unique CPL 0 Code Entry Point (R/W) See Table 2-2. See Section 5.8.7, “Performing Fast Calls to System Procedures with the SYSENTER and SYSEXIT Instructions.” Machine Check Capabilities (R) See Table 2-2. See Section 15.3.1.1, “IA32_MCG_CAP MSR.” Machine Check Status (R) See Table 2-2. See Section 15.3.1.2, “IA32_MCG_STATUS MSR.” IA32_MCG_CTL Machine Check Feature Enable (R/W) See Table 2-2. See Section 15.3.1.3, “IA32_MCG_CTL MSR.” 180H 384 MSR_MCG_RAX 0, 1, 2, 3, 4, 6 Unique See Section 15.3.2.6, “IA32_MCG Extended Machine Check State MSRs.” 63:0 181H 385 MSR_MCG_RBX Contains register state at time of machine check error. When in non-64-bit modes at the time of the error, bits 63-32 do not contain valid data. 0, 1, 2, 3, 4, 6 Unique 2-330 Vol. 4 386 MSR_MCG_RCX Machine Check EBX/RBX Save State See Section 15.3.2.6, “IA32_MCG Extended Machine Check State MSRs.” 63:0 182H Machine Check EAX/RAX Save State Contains register state at time of machine check error. When in non-64-bit modes at the time of the error, bits 63-32 do not contain valid data. 0, 1, 2, 3, 4, 6 Unique Machine Check ECX/RCX Save State See Section 15.3.2.6, “IA32_MCG Extended Machine Check State MSRs.” MODEL-SPECIFIC REGISTERS (MSRS) Table 2-48. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.) Register Address Hex Register Name Fields and Flags Dec Model Availability Shared/ Unique1 63:0 183H 387 MSR_MCG_RDX Contains register state at time of machine check error. When in non-64-bit modes at the time of the error, bits 63-32 do not contain valid data. 0, 1, 2, 3, 4, 6 Unique 388 MSR_MCG_RSI Contains register state at time of machine check error. When in non-64-bit modes at the time of the error, bits 63-32 do not contain valid data. 0, 1, 2, 3, 4, 6 Unique 389 MSR_MCG_RDI Contains register state at time of machine check error. When in non-64-bit modes at the time of the error, bits 63-32 do not contain valid data. 0, 1, 2, 3, 4, 6 Unique 390 MSR_MCG_RBP Contains register state at time of machine check error. When in non-64-bit modes at the time of the error, bits 63-32 do not contain valid data. 0, 1, 2, 3, 4, 6 Unique 391 MSR_MCG_RSP Contains register state at time of machine check error. When in non-64-bit modes at the time of the error, bits 63-32 do not contain valid data. 0, 1, 2, 3, 4, 6 Unique 392 MSR_MCG_RFLAGS Contains register state at time of machine check error. When in non-64-bit modes at the time of the error, bits 63-32 do not contain valid data. 0, 1, 2, 3, 4, 6 Unique 393 MSR_MCG_RIP 63:0 Machine Check EFLAGS/RFLAG Save State See Section 15.3.2.6, “IA32_MCG Extended Machine Check State MSRs.” 63:0 189H Machine Check ESP/RSP Save State See Section 15.3.2.6, “IA32_MCG Extended Machine Check State MSRs.” 63:0 188H Machine Check EBP/RBP Save State See Section 15.3.2.6, “IA32_MCG Extended Machine Check State MSRs.” 63:0 187H Machine Check EDI/RDI Save State See Section 15.3.2.6, “IA32_MCG Extended Machine Check State MSRs.” 63:0 186H Machine Check ESI/RSI Save State See Section 15.3.2.6, “IA32_MCG Extended Machine Check State MSRs.” 63:0 185H Machine Check EDX/RDX Save State See Section 15.3.2.6, “IA32_MCG Extended Machine Check State MSRs.” 63:0 184H Bit Description Contains register state at time of machine check error. When in non-64-bit modes at the time of the error, bits 63-32 do not contain valid data. 0, 1, 2, 3, 4, 6 Unique Machine Check EIP/RIP Save State See Section 15.3.2.6, “IA32_MCG Extended Machine Check State MSRs.” Contains register state at time of machine check error. When in non-64-bit modes at the time of the error, bits 63-32 do not contain valid data. Vol. 4 2-331 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-48. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.) Register Address Hex Dec 18AH 394 Register Name Fields and Flags MSR_MCG_MISC Model Availability 0, 1, 2, 3, 4, 6 Shared/ Unique1 Unique Bit Description Machine Check Miscellaneous See Section 15.3.2.6, “IA32_MCG Extended Machine Check State MSRs.” 0 DS When set, the bit indicates that a page assist or page fault occurred during DS normal operation. The processors response is to shut down. The bit is used as an aid for debugging DS handling code. It is the responsibility of the user (BIOS or operating system) to clear this bit for normal operation. 63:1 18BH 18FH 395 MSR_MCG_RESERVED1 MSR_MCG_RESERVED5 190H 400 MSR_MCG_R8 Reserved Reserved 0, 1, 2, 3, 4, 6 Unique See Section 15.3.2.6, “IA32_MCG Extended Machine Check State MSRs.” 63:0 191H 401 MSR_MCG_R9 Registers R8-15 (and the associated state-save MSRs) exist only in Intel 64 processors. These registers contain valid information only when the processor is operating in 64-bit mode at the time of the error. 0, 1, 2, 3, 4, 6 Unique 402 MSR_MCG_R10 Registers R8-15 (and the associated state-save MSRs) exist only in Intel 64 processors. These registers contain valid information only when the processor is operating in 64-bit mode at the time of the error. 0, 1, 2, 3, 4, 6 Unique 403 MSR_MCG_R11 63:0 2-332 Vol. 4 Machine Check R10 See Section 15.3.2.6, “IA32_MCG Extended Machine Check State MSRs.” 63:0 193H Machine Check R9D/R9 See Section 15.3.2.6, “IA32_MCG Extended Machine Check State MSRs.” 63:0 192H Machine Check R8 Registers R8-15 (and the associated state-save MSRs) exist only in Intel 64 processors. These registers contain valid information only when the processor is operating in 64-bit mode at the time of the error. 0, 1, 2, 3, 4, 6 Unique Machine Check R11 See Section 15.3.2.6, “IA32_MCG Extended Machine Check State MSRs.” Registers R8-15 (and the associated state-save MSRs) exist only in Intel 64 processors. These registers contain valid information only when the processor is operating in 64-bit mode at the time of the error. MODEL-SPECIFIC REGISTERS (MSRS) Table 2-48. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.) Register Address Hex Dec 194H 404 Register Name Fields and Flags MSR_MCG_R12 Model Availability 0, 1, 2, 3, 4, 6 Shared/ Unique1 Unique 405 MSR_MCG_R13 Registers R8-15 (and the associated state-save MSRs) exist only in Intel 64 processors. These registers contain valid information only when the processor is operating in 64-bit mode at the time of the error. 0, 1, 2, 3, 4, 6 Unique 406 MSR_MCG_R14 Registers R8-15 (and the associated state-save MSRs) exist only in Intel 64 processors. These registers contain valid information only when the processor is operating in 64-bit mode at the time of the error. 0, 1, 2, 3, 4, 6 Unique 407 MSR_MCG_R15 Machine Check R14 See Section 15.3.2.6, “IA32_MCG Extended Machine Check State MSRs.” 63:0 197H Machine Check R13 See Section 15.3.2.6, “IA32_MCG Extended Machine Check State MSRs.” 63:0 196H Machine Check R12 See Section 15.3.2.6, “IA32_MCG Extended Machine Check State MSRs.” 63:0 195H Bit Description Registers R8-15 (and the associated state-save MSRs) exist only in Intel 64 processors. These registers contain valid information only when the processor is operating in 64-bit mode at the time of the error. 0, 1, 2, 3, 4, 6 Unique Machine Check R15 See Section 15.3.2.6, “IA32_MCG Extended Machine Check State MSRs.” 63:0 Registers R8-15 (and the associated state-save MSRs) exist only in Intel 64 processors. These registers contain valid information only when the processor is operating in 64-bit mode at the time of the error. 198H 408 IA32_PERF_STATUS 3, 4, 6 Unique See Table 2-2. See Section 14.1, “Enhanced Intel Speedstep® Technology.” 199H 409 IA32_PERF_CTL 3, 4, 6 Unique See Table 2-2. See Section 14.1, “Enhanced Intel Speedstep® Technology.” 19AH 410 IA32_CLOCK_MODULATION 0, 1, 2, 3, 4, 6 Unique Thermal Monitor Control (R/W) See Table 2-2. See Section 14.7.3, “Software Controlled Clock Modulation.” 19BH 19CH 411 412 IA32_THERM_INTERRUPT IA32_THERM_STATUS 0, 1, 2, 3, 4, 6 Unique 0, 1, 2, 3, 4, 6 Shared Thermal Interrupt Control (R/W) See Section 14.7.2, “Thermal Monitor,” and see Table 2-2. Thermal Monitor Status (R/W) See Section 14.7.2, “Thermal Monitor,” and see Table 2-2. Vol. 4 2-333 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-48. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.) Register Address Hex Dec 19DH 413 1A0H 416 Register Name Fields and Flags Model Availability Shared/ Unique1 MSR_THERM2_CTL IA32_MISC_ENABLE Bit Description Thermal Monitor 2 Control 3, Shared For Family F, Model 3 processors: When read, specifies the value of the target TM2 transition last written. When set, it sets the next target value for TM2 transition. 4, 6 Shared For Family F, Model 4 and Model 6 processors: When read, specifies the value of the target TM2 transition last written. Writes may cause #GP exceptions. 0, 1, 2, 3, 4, 6 Shared Enable Miscellaneous Processor Features (R/W) 0 Fast-Strings Enable. See Table 2-2. 1 Reserved 2 x87 FPU Fopcode Compatibility Mode Enable 3 Thermal Monitor 1 Enable See Section 14.7.2, “Thermal Monitor,” and see Table 2-2. 4 Split-Lock Disable When set, the bit causes an #AC exception to be issued instead of a split-lock cycle. Operating systems that set this bit must align system structures to avoid split-lock scenarios. When the bit is clear (default), normal split-locks are issued to the bus. This debug feature is specific to the Pentium 4 processor. 5 Reserved 6 Third-Level Cache Disable (R/W) When set, the third-level cache is disabled; when clear (default) the third-level cache is enabled. This flag is reserved for processors that do not have a third-level cache. Note that the bit controls only the third-level cache; and only if overall caching is enabled through the CD flag of control register CR0, the page-level cache controls, and/or the MTRRs. See Section 11.5.4, “Disabling and Enabling the L3 Cache.” 7 Performance Monitoring Available (R) See Table 2-2. 8 Suppress Lock Enable When set, assertion of LOCK on the bus is suppressed during a Split Lock access. When clear (default), LOCK is not suppressed. 2-334 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-48. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.) Register Address Hex Register Name Fields and Flags Model Availability Dec 9 Shared/ Unique1 Bit Description Prefetch Queue Disable When set, disables the prefetch queue. When clear (default), enables the prefetch queue. 10 FERR# Interrupt Reporting Enable (R/W) When set, interrupt reporting through the FERR# pin is enabled; when clear, this interrupt reporting function is disabled. When this flag is set and the processor is in the stop-clock state (STPCLK# is asserted), asserting the FERR# pin signals to the processor that an interrupt (such as, INIT#, BINIT#, INTR, NMI, SMI#, or RESET#) is pending and that the processor should return to normal operation to handle the interrupt. This flag does not affect the normal operation of the FERR# pin (to indicate an unmasked floating-point error) when the STPCLK# pin is not asserted. 11 Branch Trace Storage Unavailable (BTS_UNAVILABLE) (R) See Table 2-2. When set, the processor does not support branch trace storage (BTS); when clear, BTS is supported. 12 PEBS_UNAVILABLE: Processor Event Based Sampling Unavailable (R) See Table 2-2. When set, the processor does not support processor event-based sampling (PEBS); when clear, PEBS is supported. 13 3 TM2 Enable (R/W) When this bit is set (1) and the thermal sensor indicates that the die temperature is at the predetermined threshold, the Thermal Monitor 2 mechanism is engaged. TM2 will reduce the bus to core ratio and voltage according to the value last written to MSR_THERM2_CTL bits 15:0. When this bit is clear (0, default), the processor does not change the VID signals or the bus to core ratio when the processor enters a thermal managed state. If the TM2 feature flag (ECX[8]) is not set to 1 after executing CPUID with EAX = 1, then this feature is not supported and BIOS must not alter the contents of this bit location. The processor is operating out of spec if both this bit and the TM1 bit are set to disabled states. Vol. 4 2-335 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-48. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.) Register Address Hex Register Name Fields and Flags Dec Model Availability Shared/ Unique1 17:14 18 Bit Description Reserved 3, 4, 6 ENABLE MONITOR FSM (R/W) See Table 2-2. 19 Adjacent Cache Line Prefetch Disable (R/W) When set to 1, the processor fetches the cache line of the 128-byte sector containing currently required data. When set to 0, the processor fetches both cache lines in the sector. Single processor platforms should not set this bit. Server platforms should set or clear this bit based on platform performance observed in validation and testing. BIOS may contain a setup option that controls the setting of this bit. 21:20 22 Reserved 3, 4, 6 Limit CPUID MAXVAL (R/W) See Table 2-2. Setting this can cause unexpected behavior to software that depends on the availability of CPUID leaves greater than 3. 23 Shared xTPR Message Disable (R/W) See Table 2-2. 24 L1 Data Cache Context Mode (R/W) When set, the L1 data cache is placed in shared mode; when clear (default), the cache is placed in adaptive mode. This bit is only enabled for IA32 processors that support Intel HyperThreading Technology. See Section 11.5.6, “L1 Data Cache Context Mode.” When L1 is running in adaptive mode and CR3s are identical, data in L1 is shared across logical processors. Otherwise, L1 is not shared and cache use is competitive. If the Context ID feature flag (ECX[10]) is set to 0 after executing CPUID with EAX = 1, the ability to switch modes is not supported. BIOS must not alter the contents of IA32_MISC_ENABLE[24]. 33:25 Reserved 34 Unique XD Bit Disable (R/W) See Table 2-2. 63:35 1A1H 417 MSR_PLATFORM_BRV 17:0 2-336 Vol. 4 Reserved 3, 4, 6 Shared Platform Feature Requirements (R) Reserved MODEL-SPECIFIC REGISTERS (MSRS) Table 2-48. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.) Register Address Hex Register Name Fields and Flags Dec Model Availability Shared/ Unique1 18 Bit Description PLATFORM Requirements When set to 1, indicates the processor has specific platform requirements. The details of the platform requirements are listed in the respective data sheets of the processor. 63:19 1D7H 471 MSR_LER_FROM_LIP Reserved 0, 1, 2, 3, 4, 6 Unique Last Exception Record From Linear IP (R) Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled. See Section 17.13.3, “Last Exception Records.” 31:0 From Linear IP Linear address of the last branch instruction. 63:32 1D7H 471 Reserved 63:0 Unique From Linear IP Linear address of the last branch instruction (If IA-32e mode is active). 1D8H 472 MSR_LER_TO_LIP 0, 1, 2, 3, 4, 6 Unique Last Exception Record To Linear IP (R) This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled. See Section 17.13.3, “Last Exception Records.” 31:0 From Linear IP Linear address of the target of the last branch instruction. 63:32 1D8H 472 Reserved 63:0 Unique From Linear IP Linear address of the target of the last branch instruction (If IA-32e mode is active). 1D9H 473 MSR_DEBUGCTLA 0, 1, 2, 3, 4, 6 Unique Debug Control (R/W) Controls how several debug features are used. Bit definitions are discussed in the referenced section. See Section 17.13.1, “MSR_DEBUGCTLA MSR.” 1DAH 474 MSR_LASTBRANCH_TOS 0, 1, 2, 3, 4, 6 Unique Last Branch Record Stack TOS (R/O) Contains an index (0-3 or 0-15) that points to the top of the last branch record stack (that is, that points the index of the MSR containing the most recent branch record). See Section 17.13.2, “LBR Stack for Processors Based on Intel NetBurst® Microarchitecture”; and addresses 1DBH-1DEH and 680H-68FH. Vol. 4 2-337 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-48. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.) Register Address Hex Dec 1DBH 475 Register Name Fields and Flags MSR_LASTBRANCH_0 Model Availability 0, 1, 2 Shared/ Unique1 Unique Bit Description Last Branch Record 0 (R/O) One of four last branch record registers on the last branch record stack. It contains pointers to the source and destination instruction for one of the last four branches, exceptions, or interrupts that the processor took. MSR_LASTBRANCH_0 through MSR_LASTBRANCH_3 at 1DBH-1DEH are available only on family 0FH, models 0H-02H. They have been replaced by the MSRs at 680H68FH and 6C0H-6CFH. See Section 17.12, “Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.” 1DCH 477 MSR_LASTBRANCH_1 0, 1, 2 Unique Last Branch Record 1 See description of the MSR_LASTBRANCH_0 MSR at 1DBH. 1DDH 477 MSR_LASTBRANCH_2 0, 1, 2 Unique Last Branch Record 2 See description of the MSR_LASTBRANCH_0 MSR at 1DBH. 1DEH 478 MSR_LASTBRANCH_3 0, 1, 2 Unique Last Branch Record 3 See description of the MSR_LASTBRANCH_0 MSR at 1DBH. 200H 201H 202H 203H 204H 205H 206H 207H 208H 209H 2-338 Vol. 4 512 513 514 515 516 517 518 519 520 521 IA32_MTRR_PHYSBASE0 IA32_MTRR_PHYSMASK0 IA32_MTRR_PHYSBASE1 IA32_MTRR_PHYSMASK1 IA32_MTRR_PHYSBASE2 IA32_MTRR_PHYSMASK2 IA32_MTRR_PHYSBASE3 IA32_MTRR_PHYSMASK3 IA32_MTRR_PHYSBASE4 IA32_MTRR_PHYSMASK4 0, 1, 2, 3, 4, 6 Shared 0, 1, 2, 3, 4, 6 Shared 0, 1, 2, 3, 4, 6 Shared 0, 1, 2, 3, 4, 6 Shared 0, 1, 2, 3, 4, 6 Shared 0, 1, 2, 3, 4, 6 Shared 0, 1, 2, 3, 4, 6 Shared 0, 1, 2, 3, 4, 6 Shared 0, 1, 2, 3, 4, 6 Shared 0, 1, 2, 3, 4, 6 Shared Variable Range Base MTRR See Section 11.11.2.3, “Variable Range MTRRs.” Variable Range Mask MTRR See Section 11.11.2.3, “Variable Range MTRRs.” Variable Range Mask MTRR See Section 11.11.2.3, “Variable Range MTRRs.” Variable Range Mask MTRR See Section 11.11.2.3, “Variable Range MTRRs.” Variable Range Mask MTRR See Section 11.11.2.3, “Variable Range MTRRs.” Variable Range Mask MTRR See Section 11.11.2.3, “Variable Range MTRRs”. Variable Range Mask MTRR See Section 11.11.2.3, “Variable Range MTRRs.” Variable Range Mask MTRR See Section 11.11.2.3, “Variable Range MTRRs.” Variable Range Mask MTRR See Section 11.11.2.3, “Variable Range MTRRs.” Variable Range Mask MTRR See Section 11.11.2.3, “Variable Range MTRRs.” MODEL-SPECIFIC REGISTERS (MSRS) Table 2-48. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.) Register Address Hex Dec 20AH 522 20BH 20CH 20DH 20EH 20FH 250H 258H 259H 268H 269H 26AH 26BH 26CH 26DH 26EH 26FH 277H 2FFH 523 524 525 526 527 592 600 601 616 617 618 619 620 621 622 623 631 767 Register Name Fields and Flags IA32_MTRR_PHYSBASE5 IA32_MTRR_PHYSMASK5 IA32_MTRR_PHYSBASE6 IA32_MTRR_PHYSMASK6 IA32_MTRR_PHYSBASE7 IA32_MTRR_PHYSMASK7 IA32_MTRR_FIX64K_00000 IA32_MTRR_FIX16K_80000 IA32_MTRR_FIX16K_A0000 IA32_MTRR_FIX4K_C0000 IA32_MTRR_FIX4K_C8000 IA32_MTRR_FIX4K_D0000 IA32_MTRR_FIX4K_D8000 IA32_MTRR_FIX4K_E0000 IA32_MTRR_FIX4K_E8000 IA32_MTRR_FIX4K_F0000 IA32_MTRR_FIX4K_F8000 IA32_PAT IA32_MTRR_DEF_TYPE Model Availability Shared/ Unique1 0, 1, 2, 3, 4, 6 Shared 0, 1, 2, 3, 4, 6 Shared 0, 1, 2, 3, 4, 6 Shared 0, 1, 2, 3, 4, 6 Shared 0, 1, 2, 3, 4, 6 Shared 0, 1, 2, 3, 4, 6 Shared 0, 1, 2, 3, 4, 6 Shared 0, 1, 2, 3, 4, 6 Shared 0, 1, 2, 3, 4, 6 Shared 0, 1, 2, 3, 4, 6 Shared 0, 1, 2, 3, 4, 6 Shared 0, 1, 2, 3, 4, 6 Shared 0, 1, 2, 3, 4, 6 Shared 0, 1, 2, 3, 4, 6 Shared 0, 1, 2, 3, 4, 6 Shared 0, 1, 2, 3, 4, 6 Shared 0, 1, 2, 3, 4, 6 Shared 0, 1, 2, 3, 4, 6 Unique 0, 1, 2, 3, 4, 6 Shared Bit Description Variable Range Mask MTRR See Section 11.11.2.3, “Variable Range MTRRs.” Variable Range Mask MTRR See Section 11.11.2.3, “Variable Range MTRRs.” Variable Range Mask MTRR See Section 11.11.2.3, “Variable Range MTRRs.” Variable Range Mask MTRR See Section 11.11.2.3, “Variable Range MTRRs.” Variable Range Mask MTRR See Section 11.11.2.3, “Variable Range MTRRs.” Variable Range Mask MTRR See Section 11.11.2.3, “Variable Range MTRRs.” Fixed Range MTRR See Section 11.11.2.2, “Fixed Range MTRRs.” Fixed Range MTRR See Section 11.11.2.2, “Fixed Range MTRRs.” Fixed Range MTRR See Section 11.11.2.2, “Fixed Range MTRRs.” Fixed Range MTRR See Section 11.11.2.2, “Fixed Range MTRRs.” Fixed Range MTRR See Section 11.11.2.2, “Fixed Range MTRRs”. Fixed Range MTRR See Section 11.11.2.2, “Fixed Range MTRRs”. Fixed Range MTRR See Section 11.11.2.2, “Fixed Range MTRRs.” Fixed Range MTRR See Section 11.11.2.2, “Fixed Range MTRRs.” Fixed Range MTRR See Section 11.11.2.2, “Fixed Range MTRRs.” Fixed Range MTRR See Section 11.11.2.2, “Fixed Range MTRRs.” Fixed Range MTRR See Section 11.11.2.2, “Fixed Range MTRRs.” Page Attribute Table See Section 11.11.2.2, “Fixed Range MTRRs.” Default Memory Types (R/W) See Table 2-2. See Section 11.11.2.1, “IA32_MTRR_DEF_TYPE MSR.” Vol. 4 2-339 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-48. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.) Register Address Register Name Fields and Flags Model Availability Shared/ Unique1 Bit Description Hex Dec 300H 768 MSR_BPU_COUNTER0 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.2, “Performance Counters.” 301H 769 MSR_BPU_COUNTER1 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.2, “Performance Counters.” 302H 770 MSR_BPU_COUNTER2 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.2, “Performance Counters.” 303H 771 MSR_BPU_COUNTER3 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.2, “Performance Counters.” 304H 772 MSR_MS_COUNTER0 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.2, “Performance Counters.” 305H 773 MSR_MS_COUNTER1 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.2, “Performance Counters.” 306H 774 MSR_MS_COUNTER2 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.2, “Performance Counters.” 307H 775 MSR_MS_COUNTER3 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.2, “Performance Counters.” 308H 776 MSR_FLAME_COUNTER0 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.2, “Performance Counters.” 309H 777 MSR_FLAME_COUNTER1 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.2, “Performance Counters.” 30AH 778 MSR_FLAME_COUNTER2 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.2, “Performance Counters.” 30BH 779 MSR_FLAME_COUNTER3 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.2, “Performance Counters.” 30CH 780 MSR_IQ_COUNTER0 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.2, “Performance Counters.” 30DH 781 MSR_IQ_COUNTER1 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.2, “Performance Counters.” 30EH 782 MSR_IQ_COUNTER2 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.2, “Performance Counters.” 30FH 783 MSR_IQ_COUNTER3 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.2, “Performance Counters.” 310H 784 MSR_IQ_COUNTER4 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.2, “Performance Counters.” 311H 785 MSR_IQ_COUNTER5 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.2, “Performance Counters.” 360H 864 MSR_BPU_CCCR0 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.3, “CCCR MSRs.” 361H 865 MSR_BPU_CCCR1 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.3, “CCCR MSRs.” 362H 866 MSR_BPU_CCCR2 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.3, “CCCR MSRs.” 363H 867 MSR_BPU_CCCR3 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.3, “CCCR MSRs.” 2-340 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-48. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.) Register Address Register Name Fields and Flags Model Availability Shared/ Unique1 Bit Description Hex Dec 364H 868 MSR_MS_CCCR0 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.3, “CCCR MSRs.” 365H 869 MSR_MS_CCCR1 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.3, “CCCR MSRs.” 366H 870 MSR_MS_CCCR2 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.3, “CCCR MSRs.” 367H 871 MSR_MS_CCCR3 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.3, “CCCR MSRs.” 368H 872 MSR_FLAME_CCCR0 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.3, “CCCR MSRs.” 369H 873 MSR_FLAME_CCCR1 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.3, “CCCR MSRs.” 36AH 874 MSR_FLAME_CCCR2 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.3, “CCCR MSRs.” 36BH 875 MSR_FLAME_CCCR3 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.3, “CCCR MSRs.” 36CH 876 MSR_IQ_CCCR0 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.3, “CCCR MSRs.” 36DH 877 MSR_IQ_CCCR1 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.3, “CCCR MSRs.” 36EH 878 MSR_IQ_CCCR2 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.3, “CCCR MSRs.” 36FH 879 MSR_IQ_CCCR3 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.3, “CCCR MSRs.” 370H 880 MSR_IQ_CCCR4 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.3, “CCCR MSRs.” 371H 881 MSR_IQ_CCCR5 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.3, “CCCR MSRs.” 3A0H 928 MSR_BSU_ESCR0 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3A1H 929 MSR_BSU_ESCR1 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3A2H 930 MSR_FSB_ESCR0 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3A3H 931 MSR_FSB_ESCR1 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3A4H 932 MSR_FIRM_ESCR0 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3A5H 933 MSR_FIRM_ESCR1 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3A6H 934 MSR_FLAME_ESCR0 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3A7H 935 MSR_FLAME_ESCR1 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” Vol. 4 2-341 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-48. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.) Register Address Register Name Fields and Flags Model Availability Shared/ Unique1 Bit Description Hex Dec 3A8H 936 MSR_DAC_ESCR0 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3A9H 937 MSR_DAC_ESCR1 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3AAH 938 MSR_MOB_ESCR0 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3ABH 939 MSR_MOB_ESCR1 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3ACH 940 MSR_PMH_ESCR0 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3ADH 941 MSR_PMH_ESCR1 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3AEH 942 MSR_SAAT_ESCR0 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3AFH 943 MSR_SAAT_ESCR1 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3B0H 944 MSR_U2L_ESCR0 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3B1H 945 MSR_U2L_ESCR1 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3B2H 946 MSR_BPU_ESCR0 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3B3H 947 MSR_BPU_ESCR1 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3B4H 948 MSR_IS_ESCR0 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3B5H 949 MSR_IS_ESCR1 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3B6H 950 MSR_ITLB_ESCR0 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3B7H 951 MSR_ITLB_ESCR1 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3B8H 952 MSR_CRU_ESCR0 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3B9H 953 MSR_CRU_ESCR1 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3BAH 954 MSR_IQ_ESCR0 0, 1, 2 Shared See Section 18.6.3.1, “ESCR MSRs.” This MSR is not available on later processors. It is only available on processor family 0FH, models 01H-02H. 3BBH 955 MSR_IQ_ESCR1 0, 1, 2 Shared See Section 18.6.3.1, “ESCR MSRs.” This MSR is not available on later processors. It is only available on processor family 0FH, models 01H-02H. 2-342 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-48. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.) Register Address Register Name Fields and Flags Model Availability Shared/ Unique1 Bit Description Hex Dec 3BCH 956 MSR_RAT_ESCR0 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3BDH 957 MSR_RAT_ESCR1 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3BEH 958 MSR_SSU_ESCR0 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3C0H 960 MSR_MS_ESCR0 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3C1H 961 MSR_MS_ESCR1 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3C2H 962 MSR_TBPU_ESCR0 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3C3H 963 MSR_TBPU_ESCR1 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3C4H 964 MSR_TC_ESCR0 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3C5H 965 MSR_TC_ESCR1 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3C8H 968 MSR_IX_ESCR0 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3C9H 969 MSR_IX_ESCR1 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3CAH 970 MSR_ALF_ESCR0 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3CBH 971 MSR_ALF_ESCR1 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3CCH 972 MSR_CRU_ESCR2 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3CDH 973 MSR_CRU_ESCR3 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3E0H 992 MSR_CRU_ESCR4 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3E1H 993 MSR_CRU_ESCR5 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3F0H 1008 MSR_TC_PRECISE_EVENT 0, 1, 2, 3, 4, 6 Shared See Section 18.6.3.1, “ESCR MSRs.” 3F1H 1009 MSR_PEBS_ENABLE 0, 1, 2, 3, 4, 6 Shared Processor Event Based Sampling (PEBS) (R/W) Controls the enabling of processor event sampling and replay tagging. 12:0 See Table 19-38. 23:13 Reserved 24 UOP Tag Enables replay tagging when set. Vol. 4 2-343 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-48. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.) Register Address Hex Register Name Fields and Flags Dec Model Availability Shared/ Unique1 25 Bit Description ENABLE_PEBS_MY_THR (R/W) Enables PEBS for the target logical processor when set; disables PEBS when clear (default). See Section 18.6.4.3, “IA32_PEBS_ENABLE MSR,” for an explanation of the target logical processor. This bit is called ENABLE_PEBS in IA-32 processors that do not support Intel HyperThreading Technology. 26 ENABLE_PEBS_OTH_THR (R/W) Enables PEBS for the target logical processor when set; disables PEBS when clear (default). See Section 18.6.4.3, “IA32_PEBS_ENABLE MSR,” for an explanation of the target logical processor. This bit is reserved for IA-32 processors that do not support Intel Hyper-Threading Technology. 63:27 Reserved 3F2H 1010 MSR_PEBS_MATRIX_VERT 0, 1, 2, 3, 4, 6 Shared See Table 19-38. 400H 1024 IA32_MC0_CTL 0, 1, 2, 3, 4, 6 Shared See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 401H 1025 IA32_MC0_STATUS 0, 1, 2, 3, 4, 6 Shared See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 402H 1026 IA32_MC0_ADDR 0, 1, 2, 3, 4, 6 Shared See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” The IA32_MC0_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC0_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 403H 1027 IA32_MC0_MISC 0, 1, 2, 3, 4, 6 Shared See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” The IA32_MC0_MISC MSR is either not implemented or does not contain additional information if the MISCV flag in the IA32_MC0_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 404H 1028 IA32_MC1_CTL 0, 1, 2, 3, 4, 6 Shared See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 405H 1029 IA32_MC1_STATUS 0, 1, 2, 3, 4, 6 Shared See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 2-344 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-48. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.) Register Address Hex Dec 406H 1030 Register Name Fields and Flags IA32_MC1_ADDR Model Availability 0, 1, 2, 3, 4, 6 Shared/ Unique1 Shared Bit Description See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” The IA32_MC1_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC1_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 407H 1031 IA32_MC1_MISC Shared See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” The IA32_MC1_MISC MSR is either not implemented or does not contain additional information if the MISCV flag in the IA32_MC1_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 408H 1032 IA32_MC2_CTL 0, 1, 2, 3, 4, 6 Shared See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 409H 1033 IA32_MC2_STATUS 0, 1, 2, 3, 4, 6 Shared See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 40AH 1034 IA32_MC2_ADDR See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” The IA32_MC2_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC2_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 40BH 1035 IA32_MC2_MISC See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” The IA32_MC2_MISC MSR is either not implemented or does not contain additional information if the MISCV flag in the IA32_MC2_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 40CH 1036 IA32_MC3_CTL 0, 1, 2, 3, 4, 6 Shared See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 40DH 1037 IA32_MC3_STATUS 0, 1, 2, 3, 4, 6 Shared See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 40EH 1038 IA32_MC3_ADDR 0, 1, 2, 3, 4, 6 Shared See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” The IA32_MC3_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC3_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. Vol. 4 2-345 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-48. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.) Register Address Hex Dec 40FH 1039 Register Name Fields and Flags IA32_MC3_MISC Model Availability 0, 1, 2, 3, 4, 6 Shared/ Unique1 Shared Bit Description See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” The IA32_MC3_MISC MSR is either not implemented or does not contain additional information if the MISCV flag in the IA32_MC3_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 410H 1040 IA32_MC4_CTL 0, 1, 2, 3, 4, 6 Shared See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 411H 1041 IA32_MC4_STATUS 0, 1, 2, 3, 4, 6 Shared See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 412H 1042 IA32_MC4_ADDR See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” The IA32_MC2_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC4_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 413H 1043 IA32_MC4_MISC See Section 15.3.2.4, “IA32_MCi_MISC MSRs.” The IA32_MC2_MISC MSR is either not implemented or does not contain additional information if the MISCV flag in the IA32_MC4_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 480H 1152 IA32_VMX_BASIC 3, 4, 6 Unique Reporting Register of Basic VMX Capabilities (R/O) See Table 2-2. See Appendix A.1, “Basic VMX Information.” 481H 1153 IA32_VMX_PINBASED_CTLS 3, 4, 6 Unique Capability Reporting Register of Pin-Based VM-Execution Controls (R/O) See Table 2-2. See Appendix A.3, “VM-Execution Controls.” 482H 1154 IA32_VMX_PROCBASED_CTLS 3, 4, 6 Unique Capability Reporting Register of Primary Processor-Based VM-Execution Controls (R/O) See Appendix A.3, “VM-Execution Controls,” and see Table 2-2. 483H 1155 IA32_VMX_EXIT_CTLS 3, 4, 6 Unique Capability Reporting Register of VM-Exit Controls (R/O) See Appendix A.4, “VM-Exit Controls,” and see Table 2-2. 2-346 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-48. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.) Register Address Hex Dec 484H 1156 Register Name Fields and Flags IA32_VMX_ENTRY_CTLS Model Availability 3, 4, 6 Shared/ Unique1 Unique Bit Description Capability Reporting Register of VM-Entry Controls (R/O) See Appendix A.5, “VM-Entry Controls,” and see Table 2-2. 485H 1157 IA32_VMX_MISC 3, 4, 6 Unique Reporting Register of Miscellaneous VMX Capabilities (R/O) See Appendix A.6, “Miscellaneous Data,” and see Table 2-2. 486H 1158 IA32_VMX_CR0_FIXED0 3, 4, 6 Unique Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix A.7, “VMX-Fixed Bits in CR0,” and see Table 2-2. 487H 1159 IA32_VMX_CR0_FIXED1 3, 4, 6 Unique Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Appendix A.7, “VMX-Fixed Bits in CR0,” and see Table 2-2. 488H 1160 IA32_VMX_CR4_FIXED0 3, 4, 6 Unique Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Appendix A.8, “VMX-Fixed Bits in CR4,” and see Table 2-2. 489H 1161 IA32_VMX_CR4_FIXED1 3, 4, 6 Unique Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) See Appendix A.8, “VMX-Fixed Bits in CR4,” and see Table 2-2. 48AH 1162 IA32_VMX_VMCS_ENUM 3, 4, 6 Unique Capability Reporting Register of VMCS Field Enumeration (R/O) See Appendix A.9, “VMCS Enumeration,” and see Table 2-2. 48BH 1163 IA32_VMX_PROCBASED_CTLS2 3, 4, 6 Unique Capability Reporting Register of Secondary Processor-Based VM-Execution Controls (R/O) See Appendix A.3, “VM-Execution Controls,” and see Table 2-2. 600H 1536 IA32_DS_AREA 0, 1, 2, 3, 4, 6 Unique DS Save Area (R/W) See Table 2-2. See Section 18.6.3.4, “Debug Store (DS) Mechanism.” 680H 1664 MSR_LASTBRANCH_0_FROM_IP 3, 4, 6 Unique Last Branch Record 0 (R/W) One of 16 pairs of last branch record registers on the last branch record stack (680H-68FH). This part of the stack contains pointers to the source instruction for one of the last 16 branches, exceptions, or interrupts taken by the processor. Vol. 4 2-347 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-48. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.) Register Address Hex Register Name Fields and Flags Dec Model Availability Shared/ Unique1 Bit Description The MSRs at 680H-68FH, 6C0H-6CfH are not available in processor releases before family 0FH, model 03H. These MSRs replace MSRs previously located at 1DBH-1DEH.which performed the same function for early releases. See Section 17.12, “Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.” 681H 1665 MSR_LASTBRANCH_1_FROM_IP 3, 4, 6 Unique Last Branch Record 1 See description of MSR_LASTBRANCH_0 at 680H. 682H 1666 MSR_LASTBRANCH_2_FROM_IP 3, 4, 6 Unique Last Branch Record 2 See description of MSR_LASTBRANCH_0 at 680H. 683H 1667 MSR_LASTBRANCH_3_FROM_IP 3, 4, 6 Unique Last Branch Record 3 See description of MSR_LASTBRANCH_0 at 680H. 684H 1668 MSR_LASTBRANCH_4_FROM_IP 3, 4, 6 Unique Last Branch Record 4 See description of MSR_LASTBRANCH_0 at 680H. 685H 1669 MSR_LASTBRANCH_5_FROM_IP 3, 4, 6 Unique Last Branch Record 5 See description of MSR_LASTBRANCH_0 at 680H. 686H 1670 MSR_LASTBRANCH_6_FROM_IP 3, 4, 6 Unique Last Branch Record 6 See description of MSR_LASTBRANCH_0 at 680H. 687H 1671 MSR_LASTBRANCH_7_FROM_IP 3, 4, 6 Unique Last Branch Record 7 See description of MSR_LASTBRANCH_0 at 680H. 688H 1672 MSR_LASTBRANCH_8_FROM_IP 3, 4, 6 Unique Last Branch Record 8 See description of MSR_LASTBRANCH_0 at 680H. 689H 1673 MSR_LASTBRANCH_9_FROM_IP 3, 4, 6 Unique Last Branch Record 9 See description of MSR_LASTBRANCH_0 at 680H. 68AH 1674 MSR_LASTBRANCH_10_FROM_IP 3, 4, 6 Unique Last Branch Record 10 See description of MSR_LASTBRANCH_0 at 680H. 68BH 1675 MSR_LASTBRANCH_11_FROM_IP 3, 4, 6 Unique Last Branch Record 11 See description of MSR_LASTBRANCH_0 at 680H. 68CH 1676 MSR_LASTBRANCH_12_FROM_IP 3, 4, 6 Unique Last Branch Record 12 See description of MSR_LASTBRANCH_0 at 680H. 2-348 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-48. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.) Register Address Hex Dec 68DH 1677 Register Name Fields and Flags MSR_LASTBRANCH_13_FROM_IP Model Availability 3, 4, 6 Shared/ Unique1 Unique Bit Description Last Branch Record 13 See description of MSR_LASTBRANCH_0 at 680H. 68EH 1678 MSR_LASTBRANCH_14_FROM_IP 3, 4, 6 Unique Last Branch Record 14 See description of MSR_LASTBRANCH_0 at 680H. 68FH 1679 MSR_LASTBRANCH_15_FROM_IP 3, 4, 6 Unique Last Branch Record 15 See description of MSR_LASTBRANCH_0 at 680H. 6C0H 1728 MSR_LASTBRANCH_0_TO_IP 3, 4, 6 Unique Last Branch Record 0 (R/W) One of 16 pairs of last branch record registers on the last branch record stack (6C0H-6CFH). This part of the stack contains pointers to the destination instruction for one of the last 16 branches, exceptions, or interrupts that the processor took. See Section 17.12, “Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture.” 6C1H 1729 MSR_LASTBRANCH_1_TO_IP 3, 4, 6 Unique Last Branch Record 1 See description of MSR_LASTBRANCH_0 at 6C0H. 6C2H 1730 MSR_LASTBRANCH_2_TO_IP 3, 4, 6 Unique Last Branch Record 2 See description of MSR_LASTBRANCH_0 at 6C0H. 6C3H 1731 MSR_LASTBRANCH_3_TO_IP 3, 4, 6 Unique Last Branch Record 3 See description of MSR_LASTBRANCH_0 at 6C0H. 6C4H 1732 MSR_LASTBRANCH_4_TO_IP 3, 4, 6 Unique Last Branch Record 4 See description of MSR_LASTBRANCH_0 at 6C0H. 6C5H 1733 MSR_LASTBRANCH_5_TO_IP 3, 4, 6 Unique Last Branch Record 5 See description of MSR_LASTBRANCH_0 at 6C0H. 6C6H 1734 MSR_LASTBRANCH_6_TO_IP 3, 4, 6 Unique Last Branch Record 6 See description of MSR_LASTBRANCH_0 at 6C0H. 6C7H 1735 MSR_LASTBRANCH_7_TO_IP 3, 4, 6 Unique Last Branch Record 7 See description of MSR_LASTBRANCH_0 at 6C0H. 6C8H 1736 MSR_LASTBRANCH_8_TO_IP 3, 4, 6 Unique Last Branch Record 8 See description of MSR_LASTBRANCH_0 at 6C0H. Vol. 4 2-349 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-48. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.) Register Address Hex Dec 6C9H 1737 Register Name Fields and Flags MSR_LASTBRANCH_9_TO_IP Model Availability 3, 4, 6 Shared/ Unique1 Unique Bit Description Last Branch Record 9 See description of MSR_LASTBRANCH_0 at 6C0H. 6CAH 1738 MSR_LASTBRANCH_10_TO_IP 3, 4, 6 Unique Last Branch Record 10 See description of MSR_LASTBRANCH_0 at 6C0H. 6CBH 1739 MSR_LASTBRANCH_11_TO_IP 3, 4, 6 Unique Last Branch Record 11 See description of MSR_LASTBRANCH_0 at 6C0H. 6CCH 1740 MSR_LASTBRANCH_12_TO_IP 3, 4, 6 Unique Last Branch Record 12 See description of MSR_LASTBRANCH_0 at 6C0H. 6CDH 1741 MSR_LASTBRANCH_13_TO_IP 3, 4, 6 Unique Last Branch Record 13 See description of MSR_LASTBRANCH_0 at 6C0H. 6CEH 1742 MSR_LASTBRANCH_14_TO_IP 3, 4, 6 Unique Last Branch Record 14 See description of MSR_LASTBRANCH_0 at 6C0H. 6CFH 1743 MSR_LASTBRANCH_15_TO_IP 3, 4, 6 Unique Last Branch Record 15 See description of MSR_LASTBRANCH_0 at 6C0H. C000_ 0080H IA32_EFER C000_ 0081H IA32_STAR C000_ 0082H IA32_LSTAR C000_ 0084H IA32_FMASK C000_ 0100H IA32_FS_BASE C000_ 0101H IA32_GS_BASE C000_ 0102H IA32_KERNEL_GS_BASE 3, 4, 6 Unique Extended Feature Enables See Table 2-2. 3, 4, 6 Unique System Call Target Address (R/W) See Table 2-2. 3, 4, 6 Unique IA-32e Mode System Call Target Address (R/W) See Table 2-2. 3, 4, 6 Unique System Call Flag Mask (R/W) See Table 2-2. 3, 4, 6 Unique Map of BASE Address of FS (R/W) See Table 2-2. 3, 4, 6 Unique Map of BASE Address of GS (R/W) See Table 2-2. 3, 4, 6 Unique Swap Target of BASE Address of GS (R/W) See Table 2-2. NOTES 1. For HT-enabled processors, there may be more than one logical processors per physical unit. If an MSR is Shared, this means that one MSR is shared between logical processors. If an MSR is unique, this means that each logical processor has its own MSR. 2-350 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) 2.19.1 MSRs Unique to Intel® Xeon® Processor MP with L3 Cache The MSRs listed in Table 2-49 apply to Intel® Xeon® Processor MP with up to 8MB level three cache. These processors can be detected by enumerating the deterministic cache parameter leaf of CPUID instruction (with EAX = 4 as input) to detect the presence of the third level cache, and with CPUID reporting family encoding 0FH, model encoding 3 or 4 (see CPUID instruction for more details). Table 2-49. MSRs Unique to 64-bit Intel® Xeon® Processor MP with Up to an 8 MB L3 Cache Register Address 107CCH Register Name Fields and Flags MSR_IFSB_BUSQ0 Model Availability 3, 4 Shared/ Unique Shared Bit Description IFSB BUSQ Event Control and Counter Register (R/W) See Section 18.6.6, “Performance Monitoring on 64bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache.” 107CDH MSR_IFSB_BUSQ1 3, 4 Shared IFSB BUSQ Event Control and Counter Register (R/W) 107CEH MSR_IFSB_SNPQ0 3, 4 Shared IFSB SNPQ Event Control and Counter Register (R/W) See Section 18.6.6, “Performance Monitoring on 64bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache.” 107CFH MSR_IFSB_SNPQ1 3, 4 Shared IFSB SNPQ Event Control and Counter Register (R/W) 107D0H MSR_EFSB_DRDY0 3, 4 Shared EFSB DRDY Event Control and Counter Register (R/W) See Section 18.6.6, “Performance Monitoring on 64bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache.” 107D1H MSR_EFSB_DRDY1 3, 4 Shared 107D2H MSR_IFSB_CTL6 3, 4 Shared EFSB DRDY Event Control and Counter Register (R/W) IFSB Latency Event Control Register (R/W) See Section 18.6.6, “Performance Monitoring on 64bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache.” 107D3H MSR_IFSB_CNTR7 3, 4 Shared IFSB Latency Event Counter Register (R/W) See Section 18.6.6, “Performance Monitoring on 64bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache.” The MSRs listed in Table 2-50 apply to Intel® Xeon® Processor 7100 series. These processors can be detected by enumerating the deterministic cache parameter leaf of CPUID instruction (with EAX = 4 as input) to detect the presence of the third level cache, and with CPUID reporting family encoding 0FH, model encoding 6 (See CPUID instruction for more details.). The performance monitoring MSRs listed in Table 2-50 are shared between logical processors in the same core, but are replicated for each core. Table 2-50. MSRs Unique to Intel® Xeon® Processor 7100 Series Register Address 107CCH Register Name Fields and Flags MSR_EMON_L3_CTR_CTL0 Model Availability 6 Shared/ Unique Shared Bit Description GBUSQ Event Control and Counter Register (R/W) See Section 18.6.6, “Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8MByte L3 Cache.” Vol. 4 2-351 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-50. MSRs Unique to Intel® Xeon® Processor 7100 Series (Contd.) Register Address Register Name Fields and Flags Model Availability Shared/ Unique 107CDH MSR_EMON_L3_CTR_CTL1 6 Shared 107CEH MSR_EMON_L3_CTR_CTL2 6 Shared Bit Description GBUSQ Event Control and Counter Register (R/W) GSNPQ Event Control and Counter Register (R/W) See Section 18.6.6, “Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8MByte L3 Cache.” 107CFH MSR_EMON_L3_CTR_CTL3 6 Shared GSNPQ Event Control and Counter Register (R/W) 107D0H MSR_EMON_L3_CTR_CTL4 6 Shared FSB Event Control and Counter Register (R/W) See Section 18.6.6, “Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8MByte L3 Cache.” 107D1H MSR_EMON_L3_CTR_CTL5 6 Shared FSB Event Control and Counter Register (R/W) 107D2H MSR_EMON_L3_CTR_CTL6 6 Shared FSB Event Control and Counter Register (R/W) 107D3H MSR_EMON_L3_CTR_CTL7 6 Shared FSB Event Control and Counter Register (R/W) 2.20 MSRS IN INTEL® CORE™ SOLO AND INTEL® CORE™ DUO PROCESSORS Model-specific registers (MSRs) for Intel Core Solo, Intel Core Duo processors, and Dual-core Intel Xeon processor LV are listed in Table 2-51. The column “Shared/Unique” applies to Intel Core Duo processor. “Unique” means each processor core has a separate MSR, or a bit field in an MSR governs only a core independently. “Shared” means the MSR or the bit field in an MSR address governs the operation of both processor cores. Table 2-51. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV Register Address Register Name Shared/ Unique Bit Description Hex Dec 0H 0 P5_MC_ADDR Unique See Section 2.23, “MSRs in Pentium Processors,” and see Table 2-2. 1H 1 P5_MC_TYPE Unique See Section 2.23, “MSRs in Pentium Processors,” and see Table 2-2. 6H 6 IA32_MONITOR_FILTER_SIZE Unique See Section 8.10.5, “Monitor/Mwait Address Range Determination,” and see Table 2-2. 10H 16 IA32_TIME_STAMP_COUNTER Unique See Section 17.17, “Time-Stamp Counter,” and see Table 2-2. 17H 23 IA32_PLATFORM_ID Shared Platform ID (R) See Table 2-2. The operating system can use this MSR to determine “slot” information for the processor and the proper microcode update to load. 1BH 2-352 Vol. 4 27 IA32_APIC_BASE Unique See Section 10.4.4, “Local APIC Status and Location,” and see Table 2-2. MODEL-SPECIFIC REGISTERS (MSRS) Table 2-51. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV Register Address Hex Dec 2AH 42 Register Name MSR_EBL_CR_POWERON Shared/ Unique Shared Bit Description Processor Hard Power-On Configuration (R/W) Enables and disables processor features; (R) indicates current processor configuration. 0 Reserved 1 Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not all processor implements R/W. 2 Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not all processor implements R/W. 3 MCERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not all processor implements R/W. 4 Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not all processor implements R/W. 6: 5 7 Reserved BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not all processor implements R/W. 8 Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled 9 Execute BIST (R/O) 1 = Enabled; 0 = Disabled 10 MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled 11 12 Reserved BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled 13 Reserved 14 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes 15 Reserved 17:16 APIC Cluster ID (R/O) 18 System Bus Frequency (R/O) 0 = 100 MHz 1 = Reserved 19 Reserved 21: 20 Symmetric Arbitration ID (R/O) 26:22 Clock Frequency Ratio (R/O) Vol. 4 2-353 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-51. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV Register Address Hex Dec 3AH 58 Register Name IA32_FEATURE_CONTROL Shared/ Unique Unique Bit Description Control Features in IA-32 Processor (R/W) See Table 2-2. 40H 64 MSR_LASTBRANCH_0 Unique Last Branch Record 0 (R/W) One of 8 last branch record registers on the last branch record stack: bits 31-0 hold the ‘from’ address and bits 63-32 hold the ‘to’ address. See also: • Last Branch Record Stack TOS at 1C9H • Section 17.15, “Last Branch, Interrupt, and Exception Recording (Pentium M Processors).” 41H 65 MSR_LASTBRANCH_1 Unique Last Branch Record 1 (R/W) See description of MSR_LASTBRANCH_0. 42H 66 MSR_LASTBRANCH_2 Unique Last Branch Record 2 (R/W) See description of MSR_LASTBRANCH_0. 43H 67 MSR_LASTBRANCH_3 Unique Last Branch Record 3 (R/W) See description of MSR_LASTBRANCH_0. 44H 68 MSR_LASTBRANCH_4 Unique Last Branch Record 4 (R/W) See description of MSR_LASTBRANCH_0. 45H 69 MSR_LASTBRANCH_5 Unique Last Branch Record 5 (R/W) See description of MSR_LASTBRANCH_0. 46H 70 MSR_LASTBRANCH_6 Unique Last Branch Record 6 (R/W) See description of MSR_LASTBRANCH_0. 47H 71 MSR_LASTBRANCH_7 Unique Last Branch Record 7 (R/W) See description of MSR_LASTBRANCH_0. 79H 121 IA32_BIOS_UPDT_TRIG Unique BIOS Update Trigger Register (W) See Table 2-2. 8BH 139 IA32_BIOS_SIGN_ID Unique BIOS Update Signature ID (RO) See Table 2-2. C1H 193 IA32_PMC0 Unique Performance Counter Register See Table 2-2. C2H 194 IA32_PMC1 Unique Performance Counter Register See Table 2-2. CDH 205 MSR_FSB_FREQ Shared Scaleable Bus Speed (RO) This field indicates the scaleable bus clock speed: 2:0 • 101B: 100 MHz (FSB 400) • 001B: 133 MHz (FSB 533) • 011B: 167 MHz (FSB 667) 133.33 MHz should be utilized if performing calculation with System Bus Speed when encoding is 101B. 166.67 MHz should be utilized if performing calculation with System Bus Speed when encoding is 001B. 63:3 2-354 Vol. 4 Reserved MODEL-SPECIFIC REGISTERS (MSRS) Table 2-51. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV Register Address Hex Dec E7H 231 Register Name IA32_MPERF Shared/ Unique Unique Bit Description Maximum Performance Frequency Clock Count (RW) See Table 2-2. E8H 232 IA32_APERF Unique Actual Performance Frequency Clock Count (RW) See Table 2-2. FEH 254 IA32_MTRRCAP Unique See Table 2-2. 11EH 281 MSR_BBL_CR_CTL3 Shared Control Register 3 Used to configure the L2 Cache. 0 L2 Hardware Enabled (RO) 1= 0= If the L2 is hardware-enabled Indicates if the L2 is hardware-disabled 7:1 Reserved 8 L2 Enabled (R/W) 1 = L2 cache has been initialized 0 = Disabled (default) Until this bit is set the processor will not respond to the WBINVD instruction or the assertion of the FLUSH# input. 22:9 Reserved 23 L2 Not Present (RO) 0= 1= 63:24 L2 Present L2 Not Present Reserved 174H 372 IA32_SYSENTER_CS Unique See Table 2-2. 175H 373 IA32_SYSENTER_ESP Unique See Table 2-2. 176H 374 IA32_SYSENTER_EIP Unique See Table 2-2. 179H 377 IA32_MCG_CAP Unique See Table 2-2. 17AH 378 IA32_MCG_STATUS Unique Global Machine Check Status 0 RIPV When set, this bit indicates that the instruction addressed by the instruction pointer pushed on the stack (when the machine check was generated) can be used to restart the program. If this bit is cleared, the program cannot be reliably restarted. 1 EIPV When set, this bit indicates that the instruction addressed by the instruction pointer pushed on the stack (when the machine check was generated) is directly associated with the error. Vol. 4 2-355 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-51. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV Register Address Hex Register Name Shared/ Unique Bit Description Dec 2 MCIP When set, this bit indicates that a machine check has been generated. If a second machine check is detected while this bit is still set, the processor enters a shutdown state. Software should write this bit to 0 after processing a machine check exception. 63:3 Reserved 186H 390 IA32_PERFEVTSEL0 Unique See Table 2-2. 187H 391 IA32_PERFEVTSEL1 Unique See Table 2-2. 198H 408 IA32_PERF_STATUS Shared See Table 2-2. 199H 409 IA32_PERF_CTL Unique See Table 2-2. 19AH 410 IA32_CLOCK_MODULATION Unique Clock Modulation (R/W) See Table 2-2. 19BH 411 IA32_THERM_INTERRUPT Unique Thermal Interrupt Control (R/W) See Table 2-2. See Section 14.7.2, “Thermal Monitor.” 19CH 412 IA32_THERM_STATUS Unique Thermal Monitor Status (R/W) See Table 2-2. See Section 14.7.2, “Thermal Monitor”. 19DH 413 MSR_THERM2_CTL Unique Thermal Monitor 2 Control 15:0 Reserved 16 TM_SELECT (R/W) Mode of automatic thermal monitor: 0 = Thermal Monitor 1 (thermally-initiated on-die modulation of the stop-clock duty cycle) 1 = Thermal Monitor 2 (thermally-initiated frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled. 63:16 1A0H 416 Reserved IA32_MISC_ENABLE Enable Miscellaneous Processor Features (R/W) Allows a variety of processor functions to be enabled and disabled. 2:0 3 Reserved Unique Automatic Thermal Control Circuit Enable (R/W) See Table 2-2. 6:4 7 Reserved Shared Performance Monitoring Available (R) See Table 2-2. 2-356 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-51. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV Register Address Hex Register Name Shared/ Unique Bit Description Dec 9:8 10 Reserved Shared FERR# Multiplexing Enable (R/W) 1= FERR# asserted by the processor to indicate a pending break event within the processor 0 = Indicates compatible FERR# signaling behavior This bit must be set to 1 to support XAPIC interrupt model usage. 11 Shared Branch Trace Storage Unavailable (RO) See Table 2-2. 12 13 Reserved Shared TM2 Enable (R/W) When this bit is set (1) and the thermal sensor indicates that the die temperature is at the pre-determined threshold, the Thermal Monitor 2 mechanism is engaged. TM2 will reduce the bus to core ratio and voltage according to the value last written to MSR_THERM2_CTL bits 15:0. When this bit is clear (0, default), the processor does not change the VID signals or the bus to core ratio when the processor enters a thermal managed state. If the TM2 feature flag (ECX[8]) is not set to 1 after executing CPUID with EAX = 1, then this feature is not supported and BIOS must not alter the contents of this bit location. The processor is operating out of spec if both this bit and the TM1 bit are set to disabled states. 15:14 16 Reserved Shared Enhanced Intel SpeedStep Technology Enable (R/W) 1= 18 Shared Enhanced Intel SpeedStep Technology enabled ENABLE MONITOR FSM (R/W) See Table 2-2. 19 22 Reserved Shared Limit CPUID Maxval (R/W) See Table 2-2. Setting this bit may cause behavior in software that depends on the availability of CPUID leaves greater than 2. 33:23 34 Reserved Shared XD Bit Disable (R/W) See Table 2-2. 63:35 1C9H 457 MSR_LASTBRANCH_TOS Reserved Unique Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) that points to the MSR containing the most recent branch record. See MSR_LASTBRANCH_0_FROM_IP (at 40H). Vol. 4 2-357 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-51. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV Register Address Hex Dec 1D9H 473 Register Name IA32_DEBUGCTL Shared/ Unique Unique Bit Description Debug Control (R/W) Controls how several debug features are used. Bit definitions are discussed in Table 2-2. 1DDH 477 MSR_LER_FROM_LIP Unique Last Exception Record From Linear IP (R) Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled. 1DEH 478 MSR_LER_TO_LIP Unique Last Exception Record To Linear IP (R) This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled. 200H 512 MTRRphysBase0 Unique Memory Type Range Registers 201H 513 MTRRphysMask0 Unique Memory Type Range Registers 202H 514 MTRRphysBase1 Unique Memory Type Range Registers 203H 515 MTRRphysMask1 Unique Memory Type Range Registers 204H 516 MTRRphysBase2 Unique Memory Type Range Registers 205H 517 MTRRphysMask2 Unique Memory Type Range Registers 206H 518 MTRRphysBase3 Unique Memory Type Range Registers 207H 519 MTRRphysMask3 Unique Memory Type Range Registers 208H 520 MTRRphysBase4 Unique Memory Type Range Registers 209H 521 MTRRphysMask4 Unique Memory Type Range Registers 20AH 522 MTRRphysBase5 Unique Memory Type Range Registers 20BH 523 MTRRphysMask5 Unique Memory Type Range Registers 20CH 524 MTRRphysBase6 Unique Memory Type Range Registers 20DH 525 MTRRphysMask6 Unique Memory Type Range Registers 20EH 526 MTRRphysBase7 Unique Memory Type Range Registers 20FH 527 MTRRphysMask7 Unique Memory Type Range Registers 250H 592 MTRRfix64K_00000 Unique Memory Type Range Registers 258H 600 MTRRfix16K_80000 Unique Memory Type Range Registers 259H 601 MTRRfix16K_A0000 Unique Memory Type Range Registers 268H 616 MTRRfix4K_C0000 Unique Memory Type Range Registers 269H 617 MTRRfix4K_C8000 Unique Memory Type Range Registers 26AH 618 MTRRfix4K_D0000 Unique Memory Type Range Registers 26BH 619 MTRRfix4K_D8000 Unique Memory Type Range Registers 26CH 620 MTRRfix4K_E0000 Unique Memory Type Range Registers 26DH 621 MTRRfix4K_E8000 Unique Memory Type Range Registers 26EH 622 MTRRfix4K_F0000 Unique Memory Type Range Registers 26FH 623 MTRRfix4K_F8000 Unique Memory Type Range Registers 2-358 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-51. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV Register Address Hex Dec 2FFH 767 Register Name IA32_MTRR_DEF_TYPE Shared/ Unique Unique Bit Description Default Memory Types (R/W) See Table 2-2. See Section 11.11.2.1, “IA32_MTRR_DEF_TYPE MSR.” 400H 1024 IA32_MC0_CTL Unique See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 401H 1025 IA32_MC0_STATUS Unique See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 402H 1026 IA32_MC0_ADDR Unique See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” The IA32_MC0_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC0_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 404H 1028 IA32_MC1_CTL Unique See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 405H 1029 IA32_MC1_STATUS Unique See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 406H 1030 IA32_MC1_ADDR Unique See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” The IA32_MC1_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC1_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 408H 1032 IA32_MC2_CTL Unique See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 409H 1033 IA32_MC2_STATUS Unique See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 40AH 1034 IA32_MC2_ADDR Unique See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” The IA32_MC2_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC2_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 40CH 1036 MSR_MC4_CTL Unique See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 40DH 1037 MSR_MC4_STATUS Unique See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 40EH 1038 MSR_MC4_ADDR Unique See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” The MSR_MC4_ADDR register is either not implemented or contains no address if the ADDRV flag in the MSR_MC4_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 410H 1040 IA32_MC3_CTL See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 411H 1041 IA32_MC3_STATUS See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 412H 1042 MSR_MC3_ADDR Unique See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” The MSR_MC3_ADDR register is either not implemented or contains no address if the ADDRV flag in the MSR_MC3_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. Vol. 4 2-359 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-51. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV Register Address Register Name Shared/ Unique Bit Description Hex Dec 413H 1043 MSR_MC3_MISC Unique Machine Check Error Reporting Register - contains additional information describing the machine-check error if the MISCV flag in the IA32_MCi_STATUS register is set. 414H 1044 MSR_MC5_CTL Unique Machine Check Error Reporting Register - controls signaling of #MC for errors produced by a particular hardware unit (or group of hardware units). 415H 1045 MSR_MC5_STATUS Unique Machine Check Error Reporting Register - contains information related to a machine-check error if its VAL (valid) flag is set. Software is responsible for clearing IA32_MCi_STATUS MSRs by explicitly writing 0s to them; writing 1s to them causes a general-protection exception. 416H 1046 MSR_MC5_ADDR Unique Machine Check Error Reporting Register - contains the address of the code or data memory location that produced the machine-check error if the ADDRV flag in the IA32_MCi_STATUS register is set. 417H 1047 MSR_MC5_MISC Unique Machine Check Error Reporting Register - contains additional information describing the machine-check error if the MISCV flag in the IA32_MCi_STATUS register is set. 480H 1152 IA32_VMX_BASIC Unique Reporting Register of Basic VMX Capabilities (R/O) See Table 2-2. See Appendix A.1, “Basic VMX Information”. (If CPUID.01H:ECX.[bit 5]) 481H 1153 IA32_VMX_PINBASED_CTLS Unique Capability Reporting Register of Pin-Based VM-Execution Controls (R/O) See Appendix A.3, “VM-Execution Controls”. (If CPUID.01H:ECX.[bit 5]) 482H 1154 IA32_VMX_PROCBASED_CTLS Unique Capability Reporting Register of Primary Processor-Based VM-Execution Controls (R/O) See Appendix A.3, “VM-Execution Controls”. (If CPUID.01H:ECX.[bit 5]) 483H 1155 IA32_VMX_EXIT_CTLS Unique Capability Reporting Register of VM-Exit Controls (R/O) See Appendix A.4, “VM-Exit Controls”. (If CPUID.01H:ECX.[bit 5]) 484H 1156 IA32_VMX_ENTRY_CTLS Unique Capability Reporting Register of VM-Entry Controls (R/O) See Appendix A.5, “VM-Entry Controls”. (If CPUID.01H:ECX.[bit 5]) 485H 1157 IA32_VMX_MISC Unique Reporting Register of Miscellaneous VMX Capabilities (R/O) See Appendix A.6, “Miscellaneous Data”. (If CPUID.01H:ECX.[bit 5]) 486H 1158 IA32_VMX_CR0_FIXED0 Unique Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix A.7, “VMX-Fixed Bits in CR0”. (If CPUID.01H:ECX.[bit 5]) 2-360 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-51. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV Register Address Hex Dec 487H 1159 Register Name IA32_VMX_CR0_FIXED1 Shared/ Unique Unique Bit Description Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Appendix A.7, “VMX-Fixed Bits in CR0”. (If CPUID.01H:ECX.[bit 5]) 488H 1160 IA32_VMX_CR4_FIXED0 Unique Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Appendix A.8, “VMX-Fixed Bits in CR4”. (If CPUID.01H:ECX.[bit 5]) 489H 1161 IA32_VMX_CR4_FIXED1 Unique Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) See Appendix A.8, “VMX-Fixed Bits in CR4”. (If CPUID.01H:ECX.[bit 5]) 48AH 1162 IA32_VMX_VMCS_ENUM Unique Capability Reporting Register of VMCS Field Enumeration (R/O) See Appendix A.9, “VMCS Enumeration”. (If CPUID.01H:ECX.[bit 5]) 48BH 1163 IA32_VMX_PROCBASED_CTLS2 Unique Capability Reporting Register of Secondary Processor-Based VM-Execution Controls (R/O) See Appendix A.3, “VM-Execution Controls”. (If CPUID.01H:ECX.[bit 5] and IA32_VMX_PROCBASED_CTLS[bit 63]) 600H 1536 IA32_DS_AREA Unique DS Save Area (R/W) See Table 2-2. See Section 18.6.3.4, “Debug Store (DS) Mechanism.” 31:0 DS Buffer Management Area Linear address of the first byte of the DS buffer management area. 63:32 C000_ 0080H 2.21 Reserved IA32_EFER Unique See Table 2-2. 10:0 Reserved 11 Execute Disable Bit Enable 63:12 Reserved MSRS IN THE PENTIUM M PROCESSOR Model-specific registers (MSRs) for the Pentium M processor are similar to those described in Section 2.22 for P6 family processors. The following table describes new MSRs and MSRs whose behavior has changed on the Pentium M processor. Table 2-52. MSRs in Pentium M Processors Register Address Hex Dec 0H 0 Register Name / Bit Fields P5_MC_ADDR Bit Description See Section 2.23, “MSRs in Pentium Processors.” Vol. 4 2-361 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-52. MSRs in Pentium M Processors (Contd.) Register Address Bit Description Register Name / Bit Fields Hex Dec 1H 1 P5_MC_TYPE See Section 2.23, “MSRs in Pentium Processors.” 10H 16 IA32_TIME_STAMP_COUNTER See Section 17.17, “Time-Stamp Counter,” and see Table 2-2. 17H 23 IA32_PLATFORM_ID Platform ID (R) See Table 2-2. The operating system can use this MSR to determine “slot” information for the processor and the proper microcode update to load. 2AH 42 MSR_EBL_CR_POWERON Processor Hard Power-On Configuration (R/W) Enables and disables processor features. (R) Indicates current processor configuration. 0 Reserved 1 Data Error Checking Enable (R) 0 = Disabled Always 0 on the Pentium M processor. 2 Response Error Checking Enable (R) 0 = Disabled Always 0 on the Pentium M processor. 3 MCERR# Drive Enable (R) 0 = Disabled Always 0 on the Pentium M processor. 4 Address Parity Enable (R) 0 = Disabled Always 0 on the Pentium M processor. 6:5 Reserved 7 BINIT# Driver Enable (R) 1 = Enabled; 0 = Disabled Always 0 on the Pentium M processor. 8 Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled 9 Execute BIST (R/O) 1 = Enabled; 0 = Disabled 10 MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled Always 0 on the Pentium M processor. 11 Reserved 12 BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled Always 0 on the Pentium M processor. 13 2-362 Vol. 4 Reserved MODEL-SPECIFIC REGISTERS (MSRS) Table 2-52. MSRs in Pentium M Processors (Contd.) Register Address Hex Bit Description Register Name / Bit Fields Dec 14 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes Always 0 on the Pentium M processor. 15 Reserved 17:16 APIC Cluster ID (R/O) Always 00B on the Pentium M processor. 18 System Bus Frequency (R/O) 0 = 100 MHz 1 = Reserved Always 0 on the Pentium M processor. 19 Reserved 21: 20 Symmetric Arbitration ID (R/O) Always 00B on the Pentium M processor. 40H 64 26:22 Clock Frequency Ratio (R/O) MSR_LASTBRANCH_0 Last Branch Record 0 (R/W) One of 8 last branch record registers on the last branch record stack: bits 31-0 hold the ‘from’ address and bits 63-32 hold the to address. See also: • Last Branch Record Stack TOS at 1C9H. • Section 17.15, “Last Branch, Interrupt, and Exception Recording (Pentium M Processors)”. 41H 65 MSR_LASTBRANCH_1 Last Branch Record 1 (R/W) See description of MSR_LASTBRANCH_0. 42H 66 MSR_LASTBRANCH_2 Last Branch Record 2 (R/W) See description of MSR_LASTBRANCH_0. 43H 67 MSR_LASTBRANCH_3 Last Branch Record 3 (R/W) See description of MSR_LASTBRANCH_0. 44H 68 MSR_LASTBRANCH_4 Last Branch Record 4 (R/W) See description of MSR_LASTBRANCH_0. 45H 69 MSR_LASTBRANCH_5 Last Branch Record 5 (R/W) See description of MSR_LASTBRANCH_0. 46H 70 MSR_LASTBRANCH_6 Last Branch Record 6 (R/W) See description of MSR_LASTBRANCH_0. 47H 71 MSR_LASTBRANCH_7 Last Branch Record 7 (R/W) See description of MSR_LASTBRANCH_0. 119H 281 MSR_BBL_CR_CTL Control Register Used to program L2 commands to be issued via cache configuration accesses mechanism. Also receives L2 lookup response. 11EH 281 63:0 Reserved MSR_BBL_CR_CTL3 Control register 3 Used to configure the L2 Cache. Vol. 4 2-363 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-52. MSRs in Pentium M Processors (Contd.) Register Address Hex Bit Description Register Name / Bit Fields Dec 0 L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled. 0 = Indicates if the L2 is hardware-disabled. 4:1 Reserved 5 ECC Check Enable (RO) This bit enables ECC checking on the cache data bus. ECC is always generated on write cycles. 0 = Disabled (default) 1 = Enabled For the Pentium M processor, ECC checking on the cache data bus is always enabled. 7:6 Reserved 8 L2 Enabled (R/W) 1 = L2 cache has been initialized 0 = Disabled (default) Until this bit is set the processor will not respond to the WBINVD instruction or the assertion of the FLUSH# input. 22:9 23 Reserved L2 Not Present (RO) 0 = L2 Present 1 = L2 Not Present 179H 377 63:24 Reserved IA32_MCG_CAP Read-only register that provides information about the machine-check architecture of the processor. 7:0 Count (RO) Indicates the number of hardware unit error reporting banks available in the processor. 8 IA32_MCG_CTL Present (RO) 1 = Indicates that the processor implements the MSR_MCG_CTL register found at MSR 17BH. 0 = Not supported. 17AH 378 63:9 Reserved IA32_MCG_STATUS Global Machine Check Status 0 RIPV When set, this bit indicates that the instruction addressed by the instruction pointer pushed on the stack (when the machine check was generated) can be used to restart the program. If this bit is cleared, the program cannot be reliably restarted. 1 EIPV When set, this bit indicates that the instruction addressed by the instruction pointer pushed on the stack (when the machine check was generated) is directly associated with the error. 2-364 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-52. MSRs in Pentium M Processors (Contd.) Register Address Hex Bit Description Register Name / Bit Fields Dec 2 MCIP When set, this bit indicates that a machine check has been generated. If a second machine check is detected while this bit is still set, the processor enters a shutdown state. Software should write this bit to 0 after processing a machine check exception. 63:3 Reserved 198H 408 IA32_PERF_STATUS See Table 2-2. 199H 409 IA32_PERF_CTL See Table 2-2. 19AH 410 IA32_CLOCK_MODULATION Clock Modulation (R/W). See Table 2-2. See Section 14.7.3, “Software Controlled Clock Modulation.” 19BH 411 IA32_THERM_INTERRUPT Thermal Interrupt Control (R/W) See Table 2-2. See Section 14.7.2, “Thermal Monitor.” 19CH 412 IA32_THERM_STATUS Thermal Monitor Status (R/W) See Table 2-2. See Section 14.7.2, “Thermal Monitor.” 19DH 413 MSR_THERM2_CTL Thermal Monitor 2 Control 15:0 Reserved 16 TM_SELECT (R/W) Mode of automatic thermal monitor: 0 = Thermal Monitor 1 (thermally-initiated on-die modulation of the stop-clock duty cycle) 1 = Thermal Monitor 2 (thermally-initiated frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled. 1A0H 416 63:16 Reserved IA32_MISC_ENABLE Enable Miscellaneous Processor Features (R/W) Allows a variety of processor functions to be enabled and disabled. 2:0 Reserved Vol. 4 2-365 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-52. MSRs in Pentium M Processors (Contd.) Register Address Hex Bit Description Register Name / Bit Fields Dec 3 Automatic Thermal Control Circuit Enable (R/W) 1 = Setting this bit enables the thermal control circuit (TCC) portion of the Intel Thermal Monitor feature. This allows processor clocks to be automatically modulated based on the processor's thermal sensor operation. 0 = Disabled (default). The automatic thermal control circuit enable bit determines if the thermal control circuit (TCC) will be activated when the processor's internal thermal sensor determines the processor is about to exceed its maximum operating temperature. When the TCC is activated and TM1 is enabled, the processors clocks will be forced to a 50% duty cycle. BIOS must enable this feature. The bit should not be confused with the on-demand thermal control circuit enable bit. 6:4 Reserved 7 Performance Monitoring Available (R) 1= 0= Performance monitoring enabled. Performance monitoring disabled. 9:8 Reserved 10 FERR# Multiplexing Enable (R/W) 1= FERR# asserted by the processor to indicate a pending break event within the processor. 0 = Indicates compatible FERR# signaling behavior. This bit must be set to 1 to support XAPIC interrupt model usage. Branch Trace Storage Unavailable (RO) 1 = Processor doesn’t support branch trace storage (BTS) 0 = BTS is supported 12 Processor Event Based Sampling Unavailable (RO) 1= Processor does not support processor event based sampling (PEBS); 0 = PEBS is supported. The Pentium M processor does not support PEBS. 15:13 Reserved 16 Enhanced Intel SpeedStep Technology Enable (R/W) 1 = Enhanced Intel SpeedStep Technology enabled. On the Pentium M processor, this bit may be configured to be read-only. 22:17 Reserved 23 xTPR Message Disable (R/W) When set to 1, xTPR messages are disabled. xTPR messages are optional messages that allow the processor to inform the chipset of its priority. The default is processor specific. 63:24 2-366 Vol. 4 Reserved MODEL-SPECIFIC REGISTERS (MSRS) Table 2-52. MSRs in Pentium M Processors (Contd.) Register Address Hex Dec 1C9H 457 Bit Description Register Name / Bit Fields MSR_LASTBRANCH_TOS Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) that points to the MSR containing the most recent branch record. See also: • MSR_LASTBRANCH_0_FROM_IP (at 40H). • Section 17.15, “Last Branch, Interrupt, and Exception Recording (Pentium M Processors)”. 1D9H 473 MSR_DEBUGCTLB Debug Control (R/W) Controls how several debug features are used. Bit definitions are discussed in the referenced section. See Section 17.15, “Last Branch, Interrupt, and Exception Recording (Pentium M Processors).” 1DDH 477 MSR_LER_TO_LIP Last Exception Record To Linear IP (R) This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled. See Section 17.15, “Last Branch, Interrupt, and Exception Recording (Pentium M Processors)” and Section 17.16.2, “Last Branch and Last Exception MSRs.” 1DEH 478 MSR_LER_FROM_LIP Last Exception Record From Linear IP (R) Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled. See Section 17.15, “Last Branch, Interrupt, and Exception Recording (Pentium M Processors)” and Section 17.16.2, “Last Branch and Last Exception MSRs.” 2FFH 767 IA32_MTRR_DEF_TYPE Default Memory Types (R/W) Sets the memory type for the regions of physical memory that are not mapped by the MTRRs. See Section 11.11.2.1, “IA32_MTRR_DEF_TYPE MSR.” 400H 1024 IA32_MC0_CTL See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 401H 1025 IA32_MC0_STATUS See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 402H 1026 IA32_MC0_ADDR See Section 14.3.2.3., “IA32_MCi_ADDR MSRs”. The IA32_MC0_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC0_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 404H 1028 IA32_MC1_CTL See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 405H 1029 IA32_MC1_STATUS See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 406H 1030 IA32_MC1_ADDR See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” The IA32_MC1_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC1_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 408H 1032 IA32_MC2_CTL See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 409H 1033 IA32_MC2_STATUS See Chapter 15.3.2.2, “IA32_MCi_STATUS MSRS.” Vol. 4 2-367 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-52. MSRs in Pentium M Processors (Contd.) Register Address Hex Dec 40AH 1034 Bit Description Register Name / Bit Fields IA32_MC2_ADDR See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” The IA32_MC2_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC2_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 40CH 1036 MSR_MC4_CTL See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 40DH 1037 MSR_MC4_STATUS See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 40EH 1038 MSR_MC4_ADDR See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” The MSR_MC4_ADDR register is either not implemented or contains no address if the ADDRV flag in the MSR_MC4_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 410H 1040 MSR_MC3_CTL See Section 15.3.2.1, “IA32_MCi_CTL MSRs.” 411H 1041 MSR_MC3_STATUS See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.” 412H 1042 MSR_MC3_ADDR See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” The MSR_MC3_ADDR register is either not implemented or contains no address if the ADDRV flag in the MSR_MC3_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception. 600H 1536 IA32_DS_AREA DS Save Area (R/W) See Table 2-2. Points to the DS buffer management area, which is used to manage the BTS and PEBS buffers. See Section 18.6.3.4, “Debug Store (DS) Mechanism.” 31:0 DS Buffer Management Area Linear address of the first byte of the DS buffer management area. 63:32 2.22 Reserved MSRS IN THE P6 FAMILY PROCESSORS The following MSRs are defined for the P6 family processors. The MSRs in this table that are shaded are available only in the Pentium II and Pentium III processors. Beginning with the Pentium 4 processor, some of the MSRs in this list have been designated as “architectural” and have had their names changed. See Table 2-2 for a list of the architectural MSRs. Table 2-53. MSRs in the P6 Family Processors Register Address Register Name / Bit Fields Bit Description Hex Dec 0H 0 P5_MC_ADDR See Section 2.23, “MSRs in Pentium Processors.” 1H 1 P5_MC_TYPE See Section 2.23, “MSRs in Pentium Processors.” 10H 16 TSC See Section 17.17, “Time-Stamp Counter.” 2-368 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-53. MSRs in the P6 Family Processors (Contd.) Register Address Hex Dec 17H 23 Register Name / Bit Fields IA32_PLATFORM_ID Bit Description Platform ID (R) The operating system can use this MSR to determine “slot” information for the processor and the proper microcode update to load. 49:0 52:50 Reserved Platform Id (R) Contains information concerning the intended platform for the processor. 52 0 0 0 0 1 1 1 1 1BH 27 51 0 0 1 1 0 0 1 1 50 0 1 0 1 0 1 0 1 Processor Flag 0 Processor Flag 1 Processor Flag 2 Processor Flag 3 Processor Flag 4 Processor Flag 5 Processor Flag 6 Processor Flag 7 56:53 L2 Cache Latency Read. 59:57 Reserved 60 Clock Frequency Ratio Read. 63:61 Reserved APIC_BASE Section 10.4.4, “Local APIC Status and Location.” 7:0 Reserved 8 Boot Strap Processor Indicator Bit 1 = BSP 10:9 11 Reserved APIC Global Enable Bit - Permanent till reset 1 = Enabled 0 = Disabled 2AH 42 31:12 APIC Base Address. 63:32 Reserved EBL_CR_POWERON Processor Hard Power-On Configuration (R/W) Enables and disables processor features; (R) indicates current processor configuration. 0 Reserved1 1 Data Error Checking Enable (R/W) 1 = Enabled 0 = Disabled 2 Response Error Checking Enable FRCERR Observation Enable (R/W) 1 = Enabled 0 = Disabled 3 AERR# Drive Enable (R/W) 1 = Enabled 0 = Disabled Vol. 4 2-369 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-53. MSRs in the P6 Family Processors (Contd.) Register Address Hex Register Name / Bit Fields Bit Description Dec 4 BERR# Enable for Initiator Bus Requests (R/W) 1 = Enabled 0 = Disabled 5 Reserved 6 BERR# Driver Enable for Initiator Internal Errors (R/W) 1 = Enabled 0 = Disabled 7 BINIT# Driver Enable (R/W) 1 = Enabled 0 = Disabled 8 Output Tri-state Enabled (R) 1 = Enabled 0 = Disabled 9 Execute BIST (R) 1 = Enabled 0 = Disabled 10 AERR# Observation Enabled (R) 1 = Enabled 0 = Disabled 11 Reserved 12 BINIT# Observation Enabled (R) 1 = Enabled 0 = Disabled 13 In Order Queue Depth (R) 1=1 0=8 14 1-MByte Power on Reset Vector (R) 1 = 1MByte 0 = 4GBytes 15 FRC Mode Enable (R) 1 = Enabled 0 = Disabled 17:16 19:18 APIC Cluster ID (R) System Bus Frequency (R) 00 = 66MHz 10 = 100Mhz 01 = 133MHz 11 = Reserved 2-370 Vol. 4 21: 20 Symmetric Arbitration ID (R) 25:22 Clock Frequency Ratio (R) 26 Low Power Mode Enable (R/W) MODEL-SPECIFIC REGISTERS (MSRS) Table 2-53. MSRs in the P6 Family Processors (Contd.) Register Address Hex 33H Register Name / Bit Fields Bit Description Dec 51 27 Clock Frequency Ratio 63:28 Reserved1 TEST_CTL Test Control Register 29:0 Reserved 30 Streaming Buffer Disable 31 Disable LOCK# Assertion for split locked access. 79H 121 BIOS_UPDT_TRIG BIOS Update Trigger Register. 88H 136 BBL_CR_D0[63:0] Chunk 0 data register D[63:0]: used to write to and read from the L2 89H 137 BBL_CR_D1[63:0] Chunk 1 data register D[63:0]: used to write to and read from the L2 8AH 138 BBL_CR_D2[63:0] Chunk 2 data register D[63:0]: used to write to and read from the L2 8BH 139 BIOS_SIGN/BBL_CR_D3[63:0] BIOS Update Signature Register or Chunk 3 data register D[63:0] Used to write to and read from the L2 depending on the usage model. C1H 193 PerfCtr0 (PERFCTR0) Performance Counter Register See Table 2-2. C2H 194 PerfCtr1 (PERFCTR1) Performance Counter Register See Table 2-2. FEH 254 116H 278 MTRRcap Memory Type Range Registers BBL_CR_ADDR [63:0] Address register: used to send specified address (A31-A3) to L2 during cache initialization accesses. BBL_CR_ADDR [63:32] Reserved, BBL_CR_ADDR [31:3] Address bits [35:3] BBL_CR_ADDR [2:0] Reserved Set to 0. 118H 280 BBL_CR_DECC[63:0] Data ECC register D[7:0]: used to write ECC and read ECC to/from L2 119H 281 BBL_CR_CTL Control register: used to program L2 commands to be issued via cache configuration accesses mechanism. Also receives L2 lookup response BL_CR_CTL[63:22] BBL_CR_CTL[21] Reserved Processor number2 Disable = 1 Enable = 0 Reserved Vol. 4 2-371 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-53. MSRs in the P6 Family Processors (Contd.) Register Address Hex Register Name / Bit Fields Bit Description Dec BBL_CR_CTL[20:19] User supplied ECC BBL_CR_CTL[18] Reserved BBL_CR_CTL[17] L2 Hit BBL_CR_CTL[16] Reserved BBL_CR_CTL[15:14] State from L2 BBL_CR_CTL[13:12] Modified - 11,Exclusive - 10, Shared - 01, Invalid - 00 BBL_CR_CTL[11:10] BBL_CR_CTL[9:8] BBL_CR_CTL[7] BBL_CR_CTL[6:5] BBL_CR_CTL[4:0] 01100 01110 01111 00010 00011 010 + MESI encode 111 + MESI encode 100 + MESI encode Way from L2 Way 0 - 00, Way 1 - 01, Way 2 - 10, Way 3 - 11 Way to L2 Reserved State to L2 L2 Command Data Read w/ LRU update (RLU) Tag Read w/ Data Read (TRR) Tag Inquire (TI) L2 Control Register Read (CR) L2 Control Register Write (CW) Tag Write w/ Data Read (TWR) Tag Write w/ Data Write (TWW) Tag Write (TW) 11AH 282 BBL_CR_TRIG Trigger register: used to initiate a cache configuration accesses access, Write only with Data = 0. 11BH 283 BBL_CR_BUSY Busy register: indicates when a cache configuration accesses L2 command is in progress. D[0] = 1 = BUSY 286 BBL_CR_CTL3 Control register 3: used to configure the L2 Cache BBL_CR_CTL3[63:26] Reserved BBL_CR_CTL3[25] Cache bus fraction (read only) BBL_CR_CTL3[24] Reserved BBL_CR_CTL3[23] L2 Hardware Disable (read only) BBL_CR_CTL3[22:20] L2 Physical Address Range support 11EH 111 110 101 100 011 010 001 000 2-372 Vol. 4 64GBytes 32GBytes 16GBytes 8GBytes 4GBytes 2GBytes 1GBytes 512MBytes BBL_CR_CTL3[19] Reserved BBL_CR_CTL3[18] Cache State error checking enable (read/write) MODEL-SPECIFIC REGISTERS (MSRS) Table 2-53. MSRs in the P6 Family Processors (Contd.) Register Address Hex Register Name / Bit Fields Bit Description Dec BBL_CR_CTL3[17:13 Cache size per bank (read/write) 00001 00010 00100 01000 10000 256KBytes 512KBytes 1MByte 2MByte 4MBytes BBL_CR_CTL3[12:11] Number of L2 banks (read only) BBL_CR_CTL3[10:9] L2 Associativity (read only) Direct Mapped 2 Way 4 Way Reserved 00 01 10 11 BBL_CR_CTL3[8] L2 Enabled (read/write) BBL_CR_CTL3[7] CRTN Parity Check Enable (read/write) BBL_CR_CTL3[6] Address Parity Check Enable (read/write) BBL_CR_CTL3[5] ECC Check Enable (read/write) BBL_CR_CTL3[4:1] L2 Cache Latency (read/write) BBL_CR_CTL3[0] L2 Configured (read/write ) 174H 372 SYSENTER_CS_MSR CS register target for CPL 0 code 175H 373 SYSENTER_ESP_MSR Stack pointer for CPL 0 stack 176H 374 SYSENTER_EIP_MSR CPL 0 code entry point 179H 377 MCG_CAP Machine Check Global Control Register 17AH 378 MCG_STATUS Machine Check Error Reporting Register - contains information related to a machine-check error if its VAL (valid) flag is set. Software is responsible for clearing IA32_MCi_STATUS MSRs by explicitly writing 0s to them; writing 1s to them causes a general-protection exception. 17BH 379 MCG_CTL Machine Check Error Reporting Register - controls signaling of #MC for errors produced by a particular hardware unit (or group of hardware units). 186H 390 PerfEvtSel0 (EVNTSEL0) Performance Event Select Register 0 (R/W) 7:0 Event Select Refer to Performance Counter section for a list of event encodings. 15:8 UMASK (Unit Mask) Unit mask register set to 0 to enable all count options. 16 USER Controls the counting of events at Privilege levels of 1, 2, and 3. 17 OS Controls the counting of events at Privilege level of 0. Vol. 4 2-373 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-53. MSRs in the P6 Family Processors (Contd.) Register Address Hex Register Name / Bit Fields Bit Description Dec 18 E Occurrence/Duration Mode Select 1 = Occurrence 0 = Duration 19 PC Enabled the signaling of performance counter overflow via BP0 pin 20 INT Enables the signaling of counter overflow via input to APIC 1 = Enable 0 = Disable 22 ENABLE Enables the counting of performance events in both counters 1 = Enable 0 = Disable 23 INV Inverts the result of the CMASK condition 1 = Inverted 0 = Non-Inverted 187H 391 31:24 CMASK (Counter Mask) PerfEvtSel1 (EVNTSEL1) Performance Event Select for Counter 1 (R/W) 7:0 Event Select Refer to Performance Counter section for a list of event encodings. 15:8 UMASK (Unit Mask) Unit mask register set to 0 to enable all count options. 16 USER Controls the counting of events at Privilege levels of 1, 2, and 3. 17 OS Controls the counting of events at Privilege level of 0. 18 E Occurrence/Duration Mode Select. 1 = Occurrence 0 = Duration 19 PC Enabled the signaling of performance counter overflow via BP0 pin. 2-374 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-53. MSRs in the P6 Family Processors (Contd.) Register Address Hex Register Name / Bit Fields Bit Description Dec 20 INT Enables the signaling of counter overflow via input to APIC. 1 = Enable 0 = Disable 23 INV Inverts the result of the CMASK condition. 1 = Inverted 0 = Non-Inverted 1D9H 473 31:24 CMASK (Counter Mask) DEBUGCTLMSR Enables last branch, interrupt, and exception recording; taken branch breakpoints; the breakpoint reporting pins; and trace messages. This register can be written to using the WRMSR instruction, when operating at privilege level 0 or when in real-address mode. 0 Enable/Disable Last Branch Records 1 Branch Trap Flag 2 Performance Monitoring/Break Point Pins 3 Performance Monitoring/Break Point Pins 4 Performance Monitoring/Break Point Pins 5 Performance Monitoring/Break Point Pins 6 Enable/Disable Execution Trace Messages 31:7 Reserved 1DBH 475 LASTBRANCHFROMIP 32-bit register for recording the instruction pointers for the last branch, interrupt, or exception that the processor took prior to a debug exception being generated. 1DCH 476 LASTBRANCHTOIP 32-bit register for recording the instruction pointers for the last branch, interrupt, or exception that the processor took prior to a debug exception being generated. 1DDH 477 LASTINTFROMIP Last INT from IP 1DEH 478 LASTINTTOIP Last INT to IP 200H 512 MTRRphysBase0 Memory Type Range Registers 201H 513 MTRRphysMask0 Memory Type Range Registers 202H 514 MTRRphysBase1 Memory Type Range Registers 203H 515 MTRRphysMask1 Memory Type Range Registers 204H 516 MTRRphysBase2 Memory Type Range Registers 205H 517 MTRRphysMask2 Memory Type Range Registers 206H 518 MTRRphysBase3 Memory Type Range Registers 207H 519 MTRRphysMask3 Memory Type Range Registers 208H 520 MTRRphysBase4 Memory Type Range Registers 209H 521 MTRRphysMask4 Memory Type Range Registers 20AH 522 MTRRphysBase5 Memory Type Range Registers Vol. 4 2-375 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-53. MSRs in the P6 Family Processors (Contd.) Register Address Register Name / Bit Fields Bit Description Hex Dec 20BH 523 MTRRphysMask5 Memory Type Range Registers 20CH 524 MTRRphysBase6 Memory Type Range Registers 20DH 525 MTRRphysMask6 Memory Type Range Registers 20EH 526 MTRRphysBase7 Memory Type Range Registers 20FH 527 MTRRphysMask7 Memory Type Range Registers 250H 592 MTRRfix64K_00000 Memory Type Range Registers 258H 600 MTRRfix16K_80000 Memory Type Range Registers 259H 601 MTRRfix16K_A0000 Memory Type Range Registers 268H 616 MTRRfix4K_C0000 Memory Type Range Registers 269H 617 MTRRfix4K_C8000 Memory Type Range Registers 26AH 618 MTRRfix4K_D0000 Memory Type Range Registers 26BH 619 MTRRfix4K_D8000 Memory Type Range Registers 26CH 620 MTRRfix4K_E0000 Memory Type Range Registers 26DH 621 MTRRfix4K_E8000 Memory Type Range Registers 26EH 622 MTRRfix4K_F0000 Memory Type Range Registers 26FH 623 MTRRfix4K_F8000 Memory Type Range Registers 2FFH 767 MTRRdefType Memory Type Range Registers 2:0 Default memory type 10 Fixed MTRR enable 11 MTRR Enable 400H 1024 MC0_CTL Machine Check Error Reporting Register - controls signaling of #MC for errors produced by a particular hardware unit (or group of hardware units). 401H 1025 MC0_STATUS Machine Check Error Reporting Register - contains information related to a machine-check error if its VAL (valid) flag is set. Software is responsible for clearing IA32_MCi_STATUS MSRs by explicitly writing 0s to them; writing 1s to them causes a general-protection exception. 15:0 MC_STATUS_MCACOD 31:16 MC_STATUS_MSCOD 57 MC_STATUS_DAM 58 MC_STATUS_ADDRV 59 MC_STATUS_MISCV 60 MC_STATUS_EN. (Note: For MC0_STATUS only, this bit is hardcoded to 1.) 61 MC_STATUS_UC 62 MC_STATUS_O 63 MC_STATUS_V 402H 1026 MC0_ADDR 403H 1027 MC0_MISC 2-376 Vol. 4 Defined in MCA architecture but not implemented in the P6 family processors. MODEL-SPECIFIC REGISTERS (MSRS) Table 2-53. MSRs in the P6 Family Processors (Contd.) Register Address Register Name / Bit Fields Bit Description Hex Dec 404H 1028 MC1_CTL 405H 1029 MC1_STATUS 406H 1030 MC1_ADDR 407H 1031 MC1_MISC 408H 1032 MC2_CTL 409H 1033 MC2_STATUS 40AH 1034 MC2_ADDR 40BH 1035 MC2_MISC 40CH 1036 MC4_CTL 40DH 1037 MC4_STATUS Bit definitions same as MC0_STATUS, except bits 0, 4, 57, and 61 are hardcoded to 1. 40EH 1038 MC4_ADDR Defined in MCA architecture but not implemented in P6 Family processors. 40FH 1039 MC4_MISC Defined in MCA architecture but not implemented in the P6 family processors. 410H 1040 MC3_CTL 411H 1041 MC3_STATUS 412H 1042 MC3_ADDR 413H 1043 MC3_MISC Bit definitions same as MC0_STATUS. Defined in MCA architecture but not implemented in the P6 family processors. Bit definitions same as MC0_STATUS. Defined in MCA architecture but not implemented in the P6 family processors. Bit definitions same as MC0_STATUS. Defined in MCA architecture but not implemented in the P6 family processors. NOTES 1. Bit 0 of this register has been redefined several times, and is no longer used in P6 family processors. 2. The processor number feature may be disabled by setting bit 21 of the BBL_CR_CTL MSR (model-specific register address 119h) to “1”. Once set, bit 21 of the BBL_CR_CTL may not be cleared. This bit is write-once. The processor number feature will be disabled until the processor is reset. 3. The Pentium III processor will prevent FSB frequency overclocking with a new shutdown mechanism. If the FSB frequency selected is greater than the internal FSB frequency the processor will shutdown. If the FSB selected is less than the internal FSB frequency the BIOS may choose to use bit 11 to implement its own shutdown policy. 2.23 MSRS IN PENTIUM PROCESSORS The following MSRs are defined for the Pentium processors. The P5_MC_ADDR, P5_MC_TYPE, and TSC MSRs (named IA32_P5_MC_ADDR, IA32_P5_MC_TYPE, and IA32_TIME_STAMP_COUNTER in the Pentium 4 processor) are architectural; that is, code that accesses these registers will run on Pentium 4 and P6 family processors without generating exceptions (see Section 2.1, “Architectural MSRs”). The CESR, CTR0, and CTR1 MSRs are unique to Pentium processors; code that accesses these registers will generate exceptions on Pentium 4 and P6 family processors. Vol. 4 2-377 MODEL-SPECIFIC REGISTERS (MSRS) Table 2-54. MSRs in the Pentium Processor Register Address Hex Dec 0H 0 P5_MC_ADDR See Section 15.10.2, “Pentium Processor Machine-Check Exception Handling.” 1H 1 P5_MC_TYPE See Section 15.10.2, “Pentium Processor Machine-Check Exception Handling.” 10H 16 TSC See Section 17.17, “Time-Stamp Counter.” 11H 17 CESR See Section 18.6.9.1, “Control and Event Select Register (CESR).” 12H 18 CTR0 Section 18.6.9.3, “Events Counted.” 13H 19 CTR1 Section 18.6.9.3, “Events Counted.” 2.24 Register Name Bit Description MSR INDEX MSRs of recent processors are indexed here for convenience. IA32 MSRs are excluded from this index. MSR Name and CPUID DisplayFamily_DisplayModel Location MSR_ALF_ESCR0 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_ALF_ESCR1 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_ANY_CORE_C0 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_ANY_GFXE_C0 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_B0_PMON_BOX_CTRL 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_B0_PMON_BOX_OVF_CTRL 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_B0_PMON_BOX_STATUS 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_B0_PMON_CTR0 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_B0_PMON_CTR1 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_B0_PMON_CTR2 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_B0_PMON_CTR3 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_B0_PMON_EVNT_SEL0 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_B0_PMON_EVNT_SEL1 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 2-378 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location MSR_B0_PMON_EVNT_SEL2 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_B0_PMON_EVNT_SEL3 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_B0_PMON_MASK 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_B0_PMON_MATCH 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_B1_PMON_BOX_CTRL 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_B1_PMON_BOX_OVF_CTRL 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_B1_PMON_BOX_STATUS 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_B1_PMON_CTR0 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_B1_PMON_CTR1 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_B1_PMON_CTR2 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_B1_PMON_CTR3 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_B1_PMON_EVNT_SEL0 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_B1_PMON_EVNT_SEL1 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_B1_PMON_EVNT_SEL2 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_B1_PMON_EVNT_SEL3 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_B1_PMON_MASK 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_B1_PMON_MATCH 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_BBL_CR_CTL 06_09H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-52 MSR_BBL_CR_CTL3 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-4 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-7 06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 06_09H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-52 Vol. 4 2-379 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location MSR_BPU_CCCR0 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_BPU_CCCR1 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_BPU_CCCR2 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_BPU_CCCR3 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_BPU_COUNTER0 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_BPU_COUNTER1 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_BPU_COUNTER2 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_BPU_COUNTER3 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_BPU_ESCR0 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_BPU_ESCR1 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_BR_DETECT_COUNTER_CONFIG_i 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-42 MSR_BR_DETECT_CTRL 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-42 MSR_BR_DETECT_STATUS 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-42 MSR_BSU_ESCR0 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_BSU_ESCR1 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_C0_PMON_BOX_CTRL 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C0_PMON_BOX_FILTER 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 MSR_C0_PMON_BOX_FILTER0 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C0_PMON_BOX_FILTER1 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C0_PMON_BOX_OVF_CTRL 2-380 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C0_PMON_BOX_STATUS 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C0_PMON_CTR0 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C0_PMON_CTR1 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C0_PMON_CTR2 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C0_PMON_CTR3 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C0_PMON_CTR4 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C0_PMON_CTR5 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C0_PMON_EVNT_SEL0 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C0_PMON_EVNT_SEL1 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C0_PMON_CTR1 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C0_PMON_EVNT_SEL2 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C0_PMON_CTR2 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 Vol. 4 2-381 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C0_PMON_EVNT_SEL3 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C0_PMON_EVNT_SEL4 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C0_PMON_EVNT_SEL5 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C1_PMON_BOX_CTRL 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C1_PMON_BOX_FILTER 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 MSR_C1_PMON_BOX_FILTER0 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C1_PMON_BOX_FILTER1 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C1_PMON_BOX_OVF_CTRL 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C1_PMON_BOX_STATUS 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C1_PMON_CTR0 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C1_PMON_CTR1 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C1_PMON_CTR2 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C1_PMON_CTR3 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 2-382 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location MSR_C1_PMON_CTR4 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C1_PMON_CTR5 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C1_PMON_EVNT_SEL0 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C1_PMON_EVNT_SEL1 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C1_PMON_EVNT_SEL2 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C1_PMON_EVNT_SEL3 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C1_PMON_EVNT_SEL4 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C1_PMON_EVNT_SEL5 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C10_PMON_BOX_FILTER 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 MSR_C10_PMON_BOX_FILTER0 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C10_PMON_BOX_FILTER1 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C11_PMON_BOX_FILTER 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 MSR_C11_PMON_BOX_FILTER0 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C11_PMON_BOX_FILTER1 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C12_PMON_BOX_FILTER 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 MSR_C12_PMON_BOX_FILTER0 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 Vol. 4 2-383 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location MSR_C12_PMON_BOX_FILTER1 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C13_PMON_BOX_FILTER 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 MSR_C13_PMON_BOX_FILTER0 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C13_PMON_BOX_FILTER1 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C14_PMON_BOX_FILTER 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 MSR_C14_PMON_BOX_FILTER0 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C14_PMON_BOX_FILTER1 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C15_PMON_BOX_CTL 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C15_PMON_BOX_FILTER0 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C15_PMON_BOX_FILTER1 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C15_PMON_BOX_STATUS 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C15_PMON_CTR0 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C15_PMON_CTR1 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C15_PMON_CTR2 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C15_PMON_CTR3 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C15_PMON_EVNTSEL0 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C15_PMON_EVNTSEL1 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C15_PMON_EVNTSEL2 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C15_PMON_EVNTSEL3 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C16_PMON_BOX_CTL 2-384 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C16_PMON_BOX_FILTER0 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C16_PMON_BOX_FILTER1 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C16_PMON_BOX_STATUS 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C16_PMON_CTR0 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C16_PMON_CTR3 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C16_PMON_CTR2 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C16_PMON_CTR3 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C16_PMON_EVNTSEL0 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C16_PMON_EVNTSEL1 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C16_PMON_EVNTSEL2 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C16_PMON_EVNTSEL3 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C17_PMON_BOX_CTL 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C17_PMON_BOX_FILTER0 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C17_PMON_BOX_FILTER1 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C17_PMON_BOX_STATUS 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C17_PMON_CTR0 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C17_PMON_CTR1 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C17_PMON_CTR2 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C17_PMON_CTR3 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C17_PMON_EVNTSEL0 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C17_PMON_EVNTSEL1 Vol. 4 2-385 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C17_PMON_EVNTSEL2 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C17_PMON_EVNTSEL3 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C2_PMON_BOX_CTRL 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C2_PMON_BOX_FILTER 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 MSR_C2_PMON_BOX_FILTER0 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C2_PMON_BOX_FILTER1 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C2_PMON_BOX_OVF_CTRL 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C2_PMON_BOX_STATUS 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C2_PMON_CTR0 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C2_PMON_CTR1 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C2_PMON_CTR2 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C2_PMON_CTR3 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C2_PMON_CTR4 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C2_PMON_CTR5 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C2_PMON_EVNT_SEL0 2-386 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C2_PMON_EVNT_SEL1 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C2_PMON_EVNT_SEL2 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C2_PMON_EVNT_SEL3 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C2_PMON_EVNT_SEL4 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C2_PMON_EVNT_SEL5 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C3_PMON_BOX_CTRL 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C3_PMON_BOX_FILTER 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 MSR_C3_PMON_BOX_FILTER0 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C3_PMON_BOX_FILTER1 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C3_PMON_BOX_OVF_CTRL 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C3_PMON_BOX_STATUS 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C3_PMON_CTR0 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C3_PMON_CTR1 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 Vol. 4 2-387 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C3_PMON_CTR2 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C3_PMON_CTR3 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C3_PMON_CTR4 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C3_PMON_CTR5 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C3_PMON_EVNT_SEL0 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C3_PMON_EVNT_SEL1 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C3_PMON_EVNT_SEL2 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C3_PMON_EVNT_SEL3 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C3_PMON_EVNT_SEL4 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C3_PMON_EVNT_SEL5 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C4_PMON_BOX_CTRL 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C4_PMON_BOX_FILTER 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 MSR_C4_PMON_BOX_FILTER0 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C4_PMON_BOX_FILTER1 2-388 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C4_PMON_BOX_OVF_CTRL 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C4_PMON_BOX_STATUS 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C4_PMON_CTR0 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C4_PMON_CTR1 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C4_PMON_CTR2 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C4_PMON_CTR3 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C4_PMON_CTR4 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C4_PMON_CTR5 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C4_PMON_EVNT_SEL0 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C4_PMON_EVNT_SEL1 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C4_PMON_EVNT_SEL2 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C4_PMON_EVNT_SEL3 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 Vol. 4 2-389 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C4_PMON_EVNT_SEL4 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C4_PMON_EVNT_SEL5 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C5_PMON_BOX_CTRL 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C5_PMON_BOX_FILTER 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 MSR_C5_PMON_BOX_FILTER0 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C5_PMON_BOX_FILTER1 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C5_PMON_BOX_OVF_CTRL 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C5_PMON_BOX_STATUS 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C5_PMON_CTR0 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C5_PMON_CTR1 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C5_PMON_CTR2 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C5_PMON_CTR3 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C5_PMON_CTR4 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C5_PMON_CTR5 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C5_PMON_EVNT_SEL0 2-390 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C5_PMON_EVNT_SEL1 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C5_PMON_EVNT_SEL2 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C5_PMON_EVNT_SEL3 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C5_PMON_EVNT_SEL4 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C5_PMON_EVNT_SEL5 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C6_PMON_BOX_CTRL 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C6_PMON_BOX_FILTER 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 MSR_C6_PMON_BOX_FILTER0 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C6_PMON_BOX_FILTER1 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C6_PMON_BOX_OVF_CTRL 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C6_PMON_BOX_STATUS 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C6_PMON_CTR0 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C6_PMON_CTR1 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 Vol. 4 2-391 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C6_PMON_CTR2 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C6_PMON_CTR3 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C6_PMON_CTR4 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C6_PMON_CTR5 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C6_PMON_EVNT_SEL0 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C6_PMON_EVNT_SEL1 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C6_PMON_EVNT_SEL2 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C6_PMON_EVNT_SEL3 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C6_PMON_EVNT_SEL4 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C6_PMON_EVNT_SEL5 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C7_PMON_BOX_CTRL 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C7_PMON_BOX_FILTER 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 MSR_C7_PMON_BOX_FILTER0 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C7_PMON_BOX_FILTER1 2-392 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C7_PMON_BOX_OVF_CTRL 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C7_PMON_BOX_STATUS 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C7_PMON_CTR0 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C7_PMON_CTR1 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C7_PMON_CTR2 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C7_PMON_CTR3 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C7_PMON_CTR4 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C7_PMON_CTR5 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C7_PMON_EVNT_SEL0 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C7_PMON_EVNT_SEL1 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C7_PMON_EVNT_SEL2 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C7_PMON_EVNT_SEL3 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 Vol. 4 2-393 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C7_PMON_EVNT_SEL4 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C7_PMON_EVNT_SEL5 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_C8_PMON_BOX_CTRL 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-19 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C8_PMON_BOX_FILTER 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 MSR_C8_PMON_BOX_FILTER0 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C8_PMON_BOX_FILTER1 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C8_PMON_BOX_OVF_CTRL 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-19 MSR_C8_PMON_BOX_STATUS 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-19 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C8_PMON_CTR0 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-19 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C8_PMON_CTR1 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-19 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C8_PMON_CTR2 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-19 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C8_PMON_CTR3 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-19 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C8_PMON_CTR4 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-19 MSR_C8_PMON_CTR5 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-19 MSR_C8_PMON_EVNT_SEL0 2-394 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-19 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C8_PMON_EVNT_SEL1 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-19 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C8_PMON_EVNT_SEL2 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-19 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C8_PMON_EVNT_SEL3 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-19 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C8_PMON_EVNT_SEL4 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-19 MSR_C8_PMON_EVNT_SEL5 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-19 MSR_C9_PMON_BOX_CTRL 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-19 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C9_PMON_BOX_FILTER 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 MSR_C9_PMON_BOX_FILTER0 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C9_PMON_BOX_FILTER1 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C9_PMON_BOX_OVF_CTRL 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-19 MSR_C9_PMON_BOX_STATUS 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-19 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C9_PMON_CTR0 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-19 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C9_PMON_CTR1 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-19 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 Vol. 4 2-395 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C9_PMON_CTR2 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-19 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C9_PMON_CTR3 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-19 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C9_PMON_CTR4 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-19 MSR_C9_PMON_CTR5 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-19 MSR_C9_PMON_EVNT_SEL0 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-19 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C9_PMON_EVNT_SEL1 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-19 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C9_PMON_EVNT_SEL2 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-19 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C9_PMON_EVNT_SEL3 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-19 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_C9_PMON_EVNT_SEL4 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-19 MSR_C9_PMON_EVNT_SEL5 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-19 MSR_CC6_DEMOTION_POLICY_CONFIG 06_37H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-9 MSR_CONFIG_TDP_CONTROL 06_3AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-25 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-29 06_57H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 MSR_CONFIG_TDP_LEVEL1 06_3AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-25 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-29 2-396 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_57H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 MSR_CONFIG_TDP_LEVEL2 06_3AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-25 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-29 06_57H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 MSR_CONFIG_TDP_NOMINAL 06_3AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-25 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-29 06_57H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 MSR_CORE_C1_RESIDENCY 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH, 06_5CH, 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-6 06_66H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-42 MSR_CORE_C3_RESIDENCY 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH, 06_25H, 06_2CH, 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH, 06_3AH, 06_3CH, 06_3EH, 06_3FH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 MSR_CORE_C6_RESIDENCY 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH, 06_5CH, 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-6 06_1AH, 06_1EH, 06_1FH, 06_2EH, 06_25H, 06_2CH, 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH, 06_3AH, 06_3CH, 06_3EH, 06_3FH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 06_57H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 MSR_CORE_C7_RESIDENCY 06_2AH, 06_2DH, 06_3AH, 06_3CH, 06_3EH, 06_3FH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 MSR_CORE_GFXE_OVERLAP_C0 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_CORE_HDC_RESIDENCY 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_CORE_PERF_LIMIT_REASONS 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 06_3F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-36 06_57H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 MSR_CORE_THREAD_COUNT 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 MSR_CRU_ESCR0 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_CRU_ESCR1 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_CRU_ESCR2 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_CRU_ESCR3 Vol. 4 2-397 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_CRU_ESCR4 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_CRU_ESCR5 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_DAC_ESCR0 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_DAC_ESCR1 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_DRAM_ENERGY_ STATUS 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH, 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-29 06_3F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-36 06_57H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 MSR_DRAM_PERF_STATUS 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH, 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-29 06_3F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-36 06_57H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 MSR_DRAM_POWER_INFO 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH, 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-36 06_57H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 MSR_DRAM_POWER_LIMIT 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH, 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-36 06_57H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 MSR_EBC_FREQUENCY_ID 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_EBC_HARD_POWERON 2-398 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_EBC_SOFT_POWERON 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_EBL_CR_POWERON 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-4 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH, 06_5CH, 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-6 06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 06_09H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-52 MSR_EFSB_DRDY0 0F_03H, 0F_04H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-49 MSR_EFSB_DRDY1 0F_03H, 0F_04H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-49 MSR_EMON_L3_CTR_CTL0 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 0F_06H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-50 MSR_EMON_L3_CTR_CTL1 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 0F_06H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-50 MSR_EMON_L3_CTR_CTL2 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 0F_06H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-50 MSR_EMON_L3_CTR_CTL3 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 0F_06H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-50 MSR_EMON_L3_CTR_CTL4 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 0F_06H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-50 MSR_EMON_L3_CTR_CTL5 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 0F_06H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-50 MSR_EMON_L3_CTR_CTL6 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 0F_06H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-50 MSR_EMON_L3_CTR_CTL7 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 0F_06H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-50 MSR_EMON_L3_GL_CTL 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 MSR_ERROR_CONTROL 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 Vol. 4 2-399 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_3F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 MSR_FEATURE_CONFIG 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH, 06_5CH, 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-6 06_25H, 06_2CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-18 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-19 06_2AH, 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 06_57H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 MSR_FIRM_ESCR0 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_FIRM_ESCR1 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_FLAME_CCCR0 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_FLAME_CCCR1 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_FLAME_CCCR2 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_FLAME_CCCR3 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_FLAME_COUNTER0 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_FLAME_COUNTER1 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_FLAME_COUNTER2 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_FLAME_COUNTER3 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_FLAME_ESCR0 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_FLAME_ESCR1 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_FSB_ESCR0 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_FSB_ESCR1 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_FSB_FREQ 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-4 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-7 06_4CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-11 06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 MSR_GQ_SNOOP_MESF 2-400 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-16 MSR_GRAPHICS_PERF_LIMIT_REASONS 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 MSR_IFSB_BUSQ0 0F_03H, 0F_04H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-49 MSR_IFSB_BUSQ1 0F_03H, 0F_04H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-49 MSR_IFSB_CNTR7 0F_03H, 0F_04H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-49 MSR_IFSB_CTL6 0F_03H, 0F_04H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-49 MSR_IFSB_SNPQ0 0F_03H, 0F_04H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-49 MSR_IFSB_SNPQ1 0F_03H, 0F_04H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-49 MSR_IQ_CCCR0 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_IQ_CCCR1 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_IQ_CCCR2 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_IQ_CCCR3 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_IQ_CCCR4 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_IQ_CCCR5 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_IQ_COUNTER0 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_IQ_COUNTER1 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_IQ_COUNTER2 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_IQ_COUNTER3 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_IQ_COUNTER4 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_IQ_COUNTER5 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_IQ_ESCR0 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_IQ_ESCR1 Vol. 4 2-401 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_IS_ESCR0 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_IS_ESCR1 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_ITLB_ESCR0 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_ITLB_ESCR1 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_IX_ESCR0 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_IX_ESCR1 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_LASTBRANCH_0 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 06_09H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-52 MSR_LASTBRANCH_0_FROM_IP 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-4 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-7 06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-13 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_LASTBRANCH_0_TO_IP 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-4 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-7 06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-13 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_LASTBRANCH_1_FROM_IP 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-4 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-7 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 2-402 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_LASTBRANCH_1_TO_IP 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-4 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-7 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_LASTBRANCH_10_FROM_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_LASTBRANCH_10_TO_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_LASTBRANCH_11_FROM_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_LASTBRANCH_11_TO_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_LASTBRANCH_12_FROM_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_LASTBRANCH_12_TO_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_LASTBRANCH_13_FROM_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 Vol. 4 2-403 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_LASTBRANCH_13_TO_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_LASTBRANCH_14_FROM_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_LASTBRANCH_14_TO_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_LASTBRANCH_15_FROM_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_LASTBRANCH_15_TO_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_LASTBRANCH_16_FROM_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_LASTBRANCH_16_TO_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_LASTBRANCH_17_FROM_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_LASTBRANCH_17_TO_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_LASTBRANCH_18_FROM_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 2-404 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location MSR_LASTBRANCH_18_TO_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_LASTBRANCH_19_FROM_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_LASTBRANCH_19_TO_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_LASTBRANCH_2 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 06_09H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-52 MSR_LASTBRANCH_2_FROM_IP 06_0FH, 06_17H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 06_1CH, 06_26H, 06_27H, 06_35H, 06_36H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-4 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-7 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_LASTBRANCH_2_TO_IP 06_0FH, 06_17H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 06_1CH, 06_26H, 06_27H, 06_35H, 06_36H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-4 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-7 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_LASTBRANCH_20_FROM_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_LASTBRANCH_20_TO_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_LASTBRANCH_21_FROM_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_LASTBRANCH_21_TO_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_LASTBRANCH_22_FROM_IP Vol. 4 2-405 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_LASTBRANCH_22_TO_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_LASTBRANCH_23_FROM_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_LASTBRANCH_23_TO_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_LASTBRANCH_24_FROM_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_LASTBRANCH_24_TO_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_LASTBRANCH_25_FROM_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_LASTBRANCH_25_TO_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_LASTBRANCH_26_FROM_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_LASTBRANCH_26_TO_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_LASTBRANCH_27_FROM_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_LASTBRANCH_27_TO_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_LASTBRANCH_28_FROM_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_LASTBRANCH_28_TO_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_LASTBRANCH_29_FROM_IP 2-406 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_LASTBRANCH_29_TO_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_LASTBRANCH_3 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 06_09H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-52 MSR_LASTBRANCH_3_FROM_IP 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-4 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-7 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_LASTBRANCH_3_TO_IP 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-4 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-7 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_LASTBRANCH_30_FROM_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_LASTBRANCH_30_TO_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_LASTBRANCH_31_FROM_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_LASTBRANCH_31_TO_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_LASTBRANCH_4 06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 06_09H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-52 MSR_LASTBRANCH_4_FROM_IP 06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-4 Vol. 4 2-407 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-7 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_LASTBRANCH_4_TO_IP 06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-4 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-7 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_LASTBRANCH_5 06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 06_09H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-52 MSR_LASTBRANCH_5_FROM_IP 06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-4 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-7 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_LASTBRANCH_5_TO_IP 06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-4 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-7 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_LASTBRANCH_6 06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 06_09H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-52 MSR_LASTBRANCH_6_FROM_IP 06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-4 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-7 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_LASTBRANCH_6_TO_IP 06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-4 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-7 2-408 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_LASTBRANCH_7 06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 06_09H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-52 MSR_LASTBRANCH_7_FROM_IP 06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-4 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-7 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_LASTBRANCH_7_TO_IP 06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-4 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-7 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_LASTBRANCH_8_FROM_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_LASTBRANCH_8_TO_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_LASTBRANCH_9_FROM_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_LASTBRANCH_9_TO_IP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_LASTBRANCH_TOS Vol. 4 2-409 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-4 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-7 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 06_09H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-52 MSR_LASTBRANCH_INFO_0 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-13 MSR_LBR_INFO_1 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-13 MSR_LBR_INFO_10 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-13 MSR_LBR_INFO_11 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-13 MSR_LBR_INFO_12 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-13 MSR_LBR_INFO_13 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-13 MSR_LBR_INFO_14 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-13 MSR_LBR_INFO_15 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-13 MSR_LBR_INFO_16 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-13 MSR_LBR_INFO_17 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-13 MSR_LBR_INFO_18 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-13 2-410 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location MSR_LBR_INFO_19 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-13 MSR_LBR_INFO_2 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-13 MSR_LBR_INFO_20 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-13 MSR_LBR_INFO_21 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-13 MSR_LBR_INFO_22 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-13 MSR_LBR_INFO_23 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-13 MSR_LBR_INFO_24 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-13 MSR_LBR_INFO_25 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-13 MSR_LBR_INFO_26 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-13 MSR_LBR_INFO_27 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-13 MSR_LBR_INFO_28 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-13 MSR_LBR_INFO_29 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-13 MSR_LBR_INFO_3 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-13 MSR_LBR_INFO_30 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-13 Vol. 4 2-411 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location MSR_LBR_INFO_31 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-13 MSR_LBR_INFO_4 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-13 MSR_LBR_INFO_5 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-13 MSR_LBR_INFO_6 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-13 MSR_LBR_INFO_7 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-13 MSR_LBR_INFO_8 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-13 MSR_LBR_INFO_9 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-13 MSR_LBR_SELECT 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-7 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-29 06_57H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 MSR_LER_FROM_LIP 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-4 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH, 06_5CH, 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-6 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 06_09H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-52 MSR_LER_TO_LIP 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-4 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH, 06_5CH, 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-6 2-412 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 06_09H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-52 MSR_M0_PMON_ADDR_MASK 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M0_PMON_ADDR_MATCH 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M0_PMON_BOX_CTRL 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M0_PMON_BOX_OVF_CTRL 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M0_PMON_BOX_STATUS 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M0_PMON_CTR0 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M0_PMON_CTR1 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M0_PMON_CTR2 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M0_PMON_CTR3 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M0_PMON_CTR4 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M0_PMON_CTR5 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M0_PMON_DSP 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M0_PMON_EVNT_SEL0 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M0_PMON_EVNT_SEL1 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M0_PMON_EVNT_SEL2 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M0_PMON_EVNT_SEL3 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M0_PMON_EVNT_SEL4 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M0_PMON_EVNT_SEL5 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 Vol. 4 2-413 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location MSR_M0_PMON_ISS 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M0_PMON_MAP 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M0_PMON_MM_CONFIG 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M0_PMON_MSC_THR 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M0_PMON_PGT 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M0_PMON_PLD 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M0_PMON_TIMESTAMP 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M0_PMON_ZDP 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M1_PMON_ADDR_MASK 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M1_PMON_ADDR_MATCH 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M1_PMON_BOX_CTRL 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M1_PMON_BOX_OVF_CTRL 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M1_PMON_BOX_STATUS 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M1_PMON_CTR0 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M1_PMON_CTR1 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M1_PMON_CTR2 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M1_PMON_CTR3 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M1_PMON_CTR4 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M1_PMON_CTR5 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M1_PMON_DSP 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M1_PMON_EVNT_SEL0 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 2-414 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location MSR_M1_PMON_EVNT_SEL1 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M1_PMON_EVNT_SEL2 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M1_PMON_EVNT_SEL3 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M1_PMON_EVNT_SEL4 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M1_PMON_EVNT_SEL5 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M1_PMON_ISS 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M1_PMON_MAP 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M1_PMON_MM_CONFIG 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M1_PMON_MSC_THR 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M1_PMON_PGT 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M1_PMON_PLD 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M1_PMON_TIMESTAMP 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_M1_PMON_ZDP 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 IA32_MC0_MISC / MSR_MC0_MISC 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 MSR_MC0_RESIDENCY 06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 IA32_MC1_MISC / MSR_MC1_MISC 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 IA32_MC10_ADDR / MSR_MC10_ADDR 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-37 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC10_CTL / MSR_MC10_CTL 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 Vol. 4 2-415 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-37 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC10_MISC / MSR_MC10_MISC 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-37 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC10_STATUS / MSR_MC10_STATUS 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-37 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC11_ADDR / MSR_MC11_ADDR 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC11_CTL / MSR_MC11_CTL 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC11_MISC / MSR_MC11_MISC 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC11_STATUS / MSR_MC11_STATUS 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 2-416 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location IA32_MC12_ADDR / MSR_MC12_ADDR 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC12_CTL / MSR_MC12_CTL 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC12_MISC / MSR_MC12_MISC 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC12_STATUS / MSR_MC12_STATUS 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC13_ADDR / MSR_MC13_ADDR 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC13_CTL / MSR_MC13_CTL 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC13_MISC / MSR_MC13_MISC 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 Vol. 4 2-417 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location IA32_MC13_STATUS / MSR_MC13_STATUS 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC14_ADDR / MSR_MC14_ADDR 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC14_CTL / MSR_MC14_CTL 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC14_MISC / MSR_MC14_MISC 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC14_STATUS / MSR_MC14_STATUS 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC15_ADDR / MSR_MC15_ADDR 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC15_CTL / MSR_MC15_CTL 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 2-418 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location IA32_MC15_MISC / MSR_MC15_MISC 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC15_STATUS / MSR_MC15_STATUS 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC16_ADDR / MSR_MC16_ADDR 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC16_CTL / MSR_MC16_CTL 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC16_MISC / MSR_MC16_MISC 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC16_STATUS / MSR_MC16_STATUS 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC17_ADDR / MSR_MC17_ADDR 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-37 Vol. 4 2-419 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC17_CTL / MSR_MC17_CTL 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-37 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC17_MISC / MSR_MC17_MISC 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-37 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC17_STATUS / MSR_MC17_STATUS 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-37 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC18_ADDR / MSR_MC18_ADDR 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-37 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC18_CTL / MSR_MC18_CTL 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-37 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC18_MISC / MSR_MC18_MISC 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-37 2-420 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC18_STATUS / MSR_MC18_STATUS 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-37 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC19_ADDR / MSR_MC19_ADDR 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-37 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC19_CTL / MSR_MC19_CTL 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-37 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC19_MISC / MSR_MC19_MISC 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-37 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC19_STATUS / MSR_MC19_STATUS 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-37 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC2_MISC / MSR_MC2_MISC 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 IA32_MC20_ADDR / MSR_MC20_ADDR 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 Vol. 4 2-421 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC20_CTL / MSR_MC20_CTL 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC20_MISC / MSR_MC20_MISC 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC20_STATUS / MSR_MC20_STATUS 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC21_ADDR / MSR_MC21_ADDR 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC21_CTL / MSR_MC21_CTL 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC21_MISC / MSR_MC21_MISC 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC21_STATUS / MSR_MC21_STATUS 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC22_ADDR / MSR_MC22_ADDR 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 IA32_MC22_CTL / MSR_MC22_CTL 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 IA32_MC22_MISC / MSR_MC22_MISC 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 2-422 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location IA32_MC22_STATUS / MSR_MC22_STATUS 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 IA32_MC23_ADDR / MSR_MC23_ADDR 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 IA32_MC23_CTL / MSR_MC23_CTL 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 IA32_MC23_MISC / MSR_MC23_MISC 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 IA32_MC23_STATUS / MSR_MC23_STATUS 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 IA32_MC24_ADDR / MSR_MC24_ADDR 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 IA32_MC24_CTL / MSR_MC24_CTL 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 IA32_MC24_MISC / MSR_MC24_MISC 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 IA32_MC24_STATUS / MSR_MC24_STATUS 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 IA32_MC25_ADDR / MSR_MC25_ADDR 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 IA32_MC25_CTL / MSR_MC25_CTL 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 IA32_MC25_MISC / MSR_MC25_MISC 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 IA32_MC25_STATUS / MSR_MC25_STATUS 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 IA32_MC26_ADDR / MSR_MC26_ADDR 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 IA32_MC26_CTL / MSR_MC26_CTL 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 IA32_MC26_MISC / MSR_MC26_MISC 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 IA32_MC26_STATUS / MSR_MC26_STATUS 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 IA32_MC27_ADDR / MSR_MC27_ADDR 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 IA32_MC27_CTL / MSR_MC27_CTL 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 IA32_MC27_MISC / MSR_MC27_MISC 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 IA32_MC27_STATUS / MSR_MC27_STATUS 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 Vol. 4 2-423 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location IA32_MC28_ADDR / MSR_MC28_ADDR 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 IA32_MC28_CTL / MSR_MC28_CTL 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 IA32_MC28_MISC / MSR_MC28_MISC 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 IA32_MC28_STATUS / MSR_MC28_STATUS 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 IA32_MC29_ADDR / MSR_MC29_ADDR 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-27 IA32_MC29_CTL / MSR_MC29_CTL 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-27 IA32_MC29_MISC / MSR_MC29_MISC 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-27 IA32_MC29_STATUS / MSR_MC29_STATUS 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-27 IA32_MC3_ADDR / MSR_MC3_ADDR 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-4 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH, 06_5CH, 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-6 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 06_09H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-52 IA32_MC3_CTL / MSR_MC3_CTL 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-4 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH, 06_5CH, 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-6 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 06_09H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-52 IA32_MC3_MISC / MSR_MC3_MISC 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 IA32_MC3_STATUS / MSR_MC3_STATUS 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-4 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH, 06_5CH, 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-6 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 2-424 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 06_09H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-52 IA32_MC30_ADDR / MSR_MC30_ADDR 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-27 IA32_MC30_CTL / MSR_MC30_CTL 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-27 IA32_MC30_MISC / MSR_MC30_MISC 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-27 IA32_MC30_STATUS / MSR_MC30_STATUS 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-27 IA32_MC31_ADDR / MSR_MC31_ADDR 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-27 IA32_MC31_CTL / MSR_MC31_CTL 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-27 IA32_MC31_MISC / MSR_MC31_MISC 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-27 IA32_MC31_STATUS / MSR_MC31_STATUS 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-27 IA32_MC4_ADDR / MSR_MC4_ADDR 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-4 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH, 06_5CH, 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-6 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 06_09H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-52 IA32_MC4_CTL / MSR_MC4_CTL 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-4 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH, 06_5CH, 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-6 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 06_09H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-52 IA32_MC4_CTL2 / MSR_MC4_CTL2 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 IA32_MC4_STATUS / MSR_MC4_STATUS 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-4 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH, 06_5CH, 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-6 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 Vol. 4 2-425 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 06_09H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-52 MSR_MC5_ADDR / MSR_MC5_ADDR 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH, 06_5CH, 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-6 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 IA32_MC5_CTL / MSR_MC5_CTL 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH, 06_5CH, 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-6 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 IA32_MC5_MISC / MSR_MC5_MISC 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 IA32_MC5_STATUS / MSR_MC5_STATUS 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH, 06_5CH, 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-6 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 IA32_MC6_ADDR / MSR_MC6_ADDR 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 2-426 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-37 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC6_CTL / MSR_MC6_CTL 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-37 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 MSR_MC6_DEMOTION_POLICY_CONFIG 06_37H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-9 IA32_MC6_MISC / MSR_MC6_MISC 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-37 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 MSR_MC6_RESIDENCY_COUNTER 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-7 06_37H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-9 06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 IA32_MC6_STATUS / MSR_MC6_STATUS 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-37 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC7_ADDR / MSR_MC7_ADDR 06_1AH, 06_1EH, 06_1FH, 06_2EH See Table 2-15 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-37 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC7_CTL / MSR_MC7_CTL 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 Vol. 4 2-427 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-37 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC7_MISC / MSR_MC7_MISC 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-37 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC7_STATUS / MSR_MC7_STATUS 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-37 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC8_ADDR / MSR_MC8_ADDR 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC8_CTL / MSR_MC8_CTL 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC8_MISC / MSR_MC8_MISC 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC8_STATUS / MSR_MC8_STATUS 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 2-428 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC9_ADDR / MSR_MC9_ADDR 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-37 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC9_CTL / MSR_MC9_CTL 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-37 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC9_MISC / MSR_MC9_MISC 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-37 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 IA32_MC9_STATUS / MSR_MC9_STATUS 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-37 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 MSR_MCG_MISC 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_MCG_R10 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_MCG_R11 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_MCG_R12 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_MCG_R13 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_MCG_R14 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_MCG_R15 Vol. 4 2-429 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_MCG_R8 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_MCG_R9 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_MCG_RAX 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_MCG_RBP 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_MCG_RBX 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_MCG_RCX 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_MCG_RDI 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_MCG_RDX 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_MCG_RESERVED1 - MSR_MCG_RESERVED5 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_MCG_RFLAGS 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_MCG_RIP 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_MCG_RSI 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_MCG_RSP 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_MISC_FEATURE_CONTROL 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 MSR_MISC_PWR_MGMT 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 MSR_MOB_ESCR0 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_MOB_ESCR1 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_MS_CCCR0 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_MS_CCCR1 2-430 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_MS_CCCR2 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_MS_CCCR3 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_MS_COUNTER0 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_MS_COUNTER1 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_MS_COUNTER2 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_MS_COUNTER3 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_MS_ESCR0 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_MS_ESCR1 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_MTRRCAP 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_OFFCORE_RSP_0 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH, 06_5CH, 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-6 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 MSR_OFFCORE_RSP_1 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH, 06_5CH, 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-6 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-18 06_2FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-19 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 MSR_PCIE_PLL_RATIO 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 MSR_PCU_PMON_BOX_CTL 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_PCU_PMON_BOX_FILTER 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_PCU_PMON_BOX_STATUS 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_PCU_PMON_CTR0 Vol. 4 2-431 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_PCU_PMON_CTR1 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_PCU_PMON_CTR2 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_PCU_PMON_CTR3 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_PCU_PMON_EVNTSEL0 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_PCU_PMON_EVNTSEL1 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_PCU_PMON_EVNTSEL2 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_PCU_PMON_EVNTSEL3 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_PEBS_ENABLE 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-4 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-7 06_5CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-13 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-27 06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_PEBS_FRONTEND 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_PEBS_LD_LAT 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 MSR_PEBS_MATRIX_VERT 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_PEBS_NUM_ALT 2-432 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 MSR_PERF_CAPABILITIES 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 MSR_PERF_GLOBAL_CTRL 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 MSR_PERF_GLOBAL_OVF_CTRL 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 MSR_PERF_GLOBAL_STATUS 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 MSR_PERF_STATUS 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-4 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 MSR_PKG_C10_RESIDENCY 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_45H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 and Table 2-31 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 MSR_PKG_C2_RESIDENCY 06_27H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-5 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_2AH, 06_2DH, 06_3AH, 06_3CH, 06_3EH, 06_3FH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 MSR_PKG_C3_RESIDENCY 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH, 06_25H, 06_2CH, 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH, 06_3AH, 06_3CH, 06_3EH, 06_3FH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-42 06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 MSR_PKG_C4_RESIDENCY 06_27H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-5 MSR_PKG_C6_RESIDENCY 06_27H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-5 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-7 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH, 06_25H, 06_2CH, 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH, 06_3AH, 06_3CH, 06_3EH, 06_3FH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 MSR_PKG_C7_RESIDENCY 06_1AH, 06_1EH, 06_1FH, 06_2EH, 06_25H, 06_2CH, 06_2FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 Vol. 4 2-433 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_2AH, 06_2DH, 06_3AH, 06_3CH, 06_3EH, 06_3FH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 MSR_PKG_C8_RESIDENCY 06_45H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-31 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 MSR_PKG_C9_RESIDENCY 06_45H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-31 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 MSR_PKG_CST_CONFIG_CONTROL 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-7 06_4CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-11 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 06_3AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-25 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 06_45H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-31 06_3F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_3DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-35 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-36 06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 MSR_PKG_ENERGY_STATUS 06_37H, 06_4AH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-8 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_2AH, 06_2DH, 06_3AH, 06_3CH, 06_3EH, 06_3FH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 MSR_PKG_HDC_CONFIG 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_PKG_HDC_DEEP_RESIDENCY 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_PKG_HDC_SHALLOW_RESIDENCY 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_PKG_PERF_STATUS 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH, 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 MSR_PKG_POWER_INFO 06_4DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-10 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_2AH, 06_2DH, 06_3AH, 06_3CH, 06_3EH, 06_3FH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 2-434 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 MSR_PKG_POWER_LIMIT 06_37H, 06_4AH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-8 06_4DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-10 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_2AH, 06_2DH, 06_3AH, 06_3CH, 06_3EH, 06_3FH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 MSR_PKGC_IRTL1 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_3CH, 06_45H, 06_46H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-29 MSR_PKGC_IRTL2 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_3CH, 06_45H, 06_46H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-29 MSR_PKGC3_IRTL 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 MSR_PKGC6_IRTL 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 MSR_PKGC7_IRTL 06_2AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-21 MSR_PLATFORM_BRV 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_PLATFORM_ENERGY_COUNTER 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_PLATFORM_ID 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-4 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-7 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 MSR_PLATFORM_INFO 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 06_3AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-25 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-29 and Table 2-30 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-36 06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 MSR_PLATFORM_POWER_LIMIT 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 Vol. 4 2-435 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location MSR_PMG_IO_CAPTURE_BASE 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH, 06_5CH, 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-6 06_4CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-11 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 06_3AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-25 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 MSR_PMH_ESCR0 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_PMH_ESCR1 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_PMON_GLOBAL_CONFIG 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_PMON_GLOBAL_CTL 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_PMON_GLOBAL_STATUS 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_POWER_CTL 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 MSR_PP0_ENERGY_STATUS 06_37H, 06_4AH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-8 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_2AH, 06_2DH, 06_3AH, 06_3CH, 06_3EH, 06_3FH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 MSR_PP0_POLICY 06_2AH, 06_45H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-21 MSR_PP0_POWER_LIMIT 06_4CH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-11 06_2AH, 06_2DH, 06_3AH, 06_3CH, 06_3EH, 06_3FH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 MSR_PP1_ENERGY_STATUS 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_2AH, 06_45H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-21 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 MSR_PP1_POLICY 06_2AH, 06_45H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-21 2-436 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 MSR_PP1_POWER_LIMIT 06_2AH, 06_45H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-21 06_3CH, 06_45H, 06_46H See Table 2-30 MSR_PPERF 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_PPIN 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-36 MSR_PPIN_CTL 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-36 MSR_PRMRR_PHYS_BASE 06_8EH, 06_9EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-41 MSR_PRMRR_PHYS_MASK 06_8EH, 06_9EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-41 MSR_PRMRR_VALID_CONFIG 06_8EH, 06_9EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-41 MSR_RING_RATIO_LIMIT 06_8EH, 06_9EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-41 MSR_R0_PMON_BOX_CTRL 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R0_PMON_BOX_OVF_CTRL 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R0_PMON_BOX_STATUS 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R0_PMON_CTR0 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R0_PMON_CTR1 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R0_PMON_CTR2 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R0_PMON_CTR3 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R0_PMON_CTR4 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R0_PMON_CTR5 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R0_PMON_CTR6 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R0_PMON_CTR7 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 Vol. 4 2-437 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location MSR_R0_PMON_EVNT_SEL0 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R0_PMON_EVNT_SEL1 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R0_PMON_EVNT_SEL2 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R0_PMON_EVNT_SEL3 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R0_PMON_EVNT_SEL4 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R0_PMON_EVNT_SEL5 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R0_PMON_EVNT_SEL6 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R0_PMON_EVNT_SEL7 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R0_PMON_IPERF0_P0 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R0_PMON_IPERF0_P1 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R0_PMON_IPERF0_P2 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R0_PMON_IPERF0_P3 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R0_PMON_IPERF0_P4 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R0_PMON_IPERF0_P5 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R0_PMON_IPERF0_P6 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R0_PMON_IPERF0_P7 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R0_PMON_QLX_P0 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R0_PMON_QLX_P1 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R0_PMON_QLX_P2 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R0_PMON_QLX_P3 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R1_PMON_BOX_CTRL 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 2-438 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location MSR_R1_PMON_BOX_OVF_CTRL 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R1_PMON_BOX_STATUS 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R1_PMON_CTR10 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R1_PMON_CTR11 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R1_PMON_CTR12 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R1_PMON_CTR13 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R1_PMON_CTR14 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R1_PMON_CTR15 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R1_PMON_CTR8 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R1_PMON_CTR9 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R1_PMON_EVNT_SEL10 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R1_PMON_EVNT_SEL11 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R1_PMON_EVNT_SEL12 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R1_PMON_EVNT_SEL13 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R1_PMON_EVNT_SEL14 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R1_PMON_EVNT_SEL15 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R1_PMON_EVNT_SEL8 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R1_PMON_EVNT_SEL9 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R1_PMON_IPERF1_P10 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R1_PMON_IPERF1_P11 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R1_PMON_IPERF1_P12 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 Vol. 4 2-439 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location MSR_R1_PMON_IPERF1_P13 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R1_PMON_IPERF1_P14 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R1_PMON_IPERF1_P15 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R1_PMON_IPERF1_P8 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R1_PMON_IPERF1_P9 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R1_PMON_QLX_P4 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R1_PMON_QLX_P5 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R1_PMON_QLX_P6 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_R1_PMON_QLX_P7 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_RAPL_POWER_UNIT 06_37H, 06_4AH, 06_5AH, 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-8 06_4DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-10 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_2AH, 06_2DH, 06_3AH, 06_3CH, 06_3EH, 06_3FH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-36 06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 MSR_RAT_ESCR0 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_RAT_ESCR1 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_RING_PERF_LIMIT_REASONS 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 MSR_S0_PMON_BOX_CTRL 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S0_PMON_BOX_FILTER 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S0_PMON_BOX_OVF_CTRL 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_S0_PMON_BOX_STATUS 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_S0_PMON_CTR0 2-440 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S0_PMON_CTR1 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S0_PMON_CTR2 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S0_PMON_CTR3 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S0_PMON_EVNT_SEL0 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S0_PMON_EVNT_SEL1 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S0_PMON_EVNT_SEL2 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S0_PMON_EVNT_SEL3 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S0_PMON_MASK 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_S0_PMON_MATCH 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_S1_PMON_BOX_CTRL 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S1_PMON_BOX_FILTER 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S1_PMON_BOX_OVF_CTRL 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_S1_PMON_BOX_STATUS 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_S1_PMON_CTR0 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S1_PMON_CTR1 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 Vol. 4 2-441 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location MSR_S1_PMON_CTR2 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S1_PMON_CTR3 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S1_PMON_EVNT_SEL0 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S1_PMON_EVNT_SEL1 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S1_PMON_EVNT_SEL2 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S1_PMON_EVNT_SEL3 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S1_PMON_MASK 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_S1_PMON_MATCH 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_S2_PMON_BOX_CTL 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S2_PMON_BOX_FILTER 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S2_PMON_CTR0 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S2_PMON_CTR1 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S2_PMON_CTR2 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S2_PMON_CTR3 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S2_PMON_EVNTSEL0 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S2_PMON_EVNTSEL1 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S2_PMON_EVNTSEL2 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S2_PMON_EVNTSEL3 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 2-442 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location MSR_S3_PMON_BOX_CTL 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S3_PMON_BOX_FILTER 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S3_PMON_CTR0 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S3_PMON_CTR1 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S3_PMON_CTR2 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S3_PMON_CTR3 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S3_PMON_EVNTSEL0 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S3_PMON_EVNTSEL1 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S3_PMON_EVNTSEL2 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_S3_PMON_EVNTSEL3 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_SAAT_ESCR0 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_SAAT_ESCR1 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_SGXOWNEREPOCH0 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_SGXOWNEREPOCH1 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_SMI_COUNT 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH, 06_5CH, 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-6 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 MSR_SMM_BLOCKED 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 MSR_SMM_DELAYED 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 MSR_SMM_FEATURE_CONTROL Vol. 4 2-443 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 MSR_SMM_MCA_CAP 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-36 06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 MSR_SMRR_PHYSBASE 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 MSR_SMRR_PHYSMASK 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 MSR_SSU_ESCR0 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_TBPU_ESCR0 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_TBPU_ESCR1 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_TC_ESCR0 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_TC_ESCR1 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_TC_PRECISE_EVENT 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_TEMPERATURE_TARGET 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH, 06_5CH, 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-6 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_2AH, 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-20 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 06_56H, 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-36 06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 MSR_THERM2_CTL 06_0FH, 06_17H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-3 06_1CH, 06_26H, 06_27H, 06_35H, 06_36H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-4 0FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 06_0EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 06_09H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-52 MSR_THREAD_ID_INFO 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 MSR_TRACE_HUB_STH_ACPIBAR_BASE 06_8EH, 06_9EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-41 MSR_TURBO_ACTIVATION_RATIO 2-444 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_3AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-25 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-29 06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 MSR_TURBO_GROUP_CORECNT 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 MSR_TURBO_POWER_CURRENT_LIMIT 06_1AH, 06_1EH, 06_1FH, 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 MSR_TURBO_RATIO_LIMIT 06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH, 06_5CH, 06_7AH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-6 06_4DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-10 06_5CH, 06_7AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-12 06_1AH, 06_1EH, 06_1FH, 06_2EH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-15 06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-16 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-18 06_2FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-19 06_2AH, 06_45H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-21 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-23 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 and Table 2-27 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_3DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-35 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-36 06_55H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-45 06_57H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-46 MSR_TURBO_RATIO_LIMIT1 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-26 and Table 2-27 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 06_56H, 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-36 MSR_TURBO_RATIO_LIMIT2 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-32 MSR_TURBO_RATIO_LIMIT3 06_56H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-37 06_4FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-38 MSR_TURBO_RATIO_LIMIT_CORES 06_55H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-45 MSR_U_PMON_BOX_STATUS 06_3EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-28 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 Vol. 4 2-445 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location MSR_U_PMON_CTR 06_2EH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_U_PMON_CTR0 06_2DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_U_PMON_CTR1 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_U_PMON_EVNT_SEL 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_U_PMON_EVNTSEL0 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_U_PMON_EVNTSEL1 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_U_PMON_GLOBAL_CTRL 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_U_PMON_GLOBAL_OVF_CTRL 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_U_PMON_GLOBAL_STATUS 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_U_PMON_UCLK_FIXED_CTL 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_U_PMON_UCLK_FIXED_CTR 06_2DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-24 06_3FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-33 MSR_U2L_ESCR0 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_U2L_ESCR1 0FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-48 MSR_UNC_ARB_PERFCTR0 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-40 MSR_UNC_ARB_PERFCTR1 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-40 MSR_UNC_ARB_PERFEVTSEL0 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 2-446 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-40 MSR_UNC_ARB_PERFEVTSEL1 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-40 MSR_UNC_CBO_0_PERFCTR0 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-40 MSR_UNC_CBO_0_PERFCTR1 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-40 MSR_UNC_CBO_0_PERFCTR2 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 MSR_UNC_CBO_0_PERFCTR3 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 MSR_UNC_CBO_0_PERFEVTSEL0 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 06_3CH, 06_45H, 06_46H See Table 2-30 06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-40 MSR_UNC_CBO_0_PERFEVTSEL1 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-40 MSR_UNC_CBO_0_PERFEVTSEL2 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 MSR_UNC_CBO_0_PERFEVTSEL3 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 MSR_UNC_CBO_0_UNIT_STATUS 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 MSR_UNC_CBO_1_PERFCTR0 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-40 MSR_UNC_CBO_1_PERFCTR1 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-40 MSR_UNC_CBO_1_PERFCTR2 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 Vol. 4 2-447 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location MSR_UNC_CBO_1_PERFCTR3 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 MSR_UNC_CBO_1_PERFEVTSEL0 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-40 MSR_UNC_CBO_1_PERFEVTSEL1 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-40 MSR_UNC_CBO_1_PERFEVTSEL2 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 MSR_UNC_CBO_1_PERFEVTSEL3 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 MSR_UNC_CBO_1_UNIT_STATUS 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 MSR_UNC_CBO_2_PERFCTR0 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-40 MSR_UNC_CBO_2_PERFCTR1 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-40 MSR_UNC_CBO_2_PERFCTR2 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 MSR_UNC_CBO_2_PERFCTR3 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 MSR_UNC_CBO_2_PERFEVTSEL0 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-40 MSR_UNC_CBO_2_PERFEVTSEL1 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-40 MSR_UNC_CBO_2_PERFEVTSEL2 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 MSR_UNC_CBO_2_PERFEVTSEL3 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 MSR_UNC_CBO_2_UNIT_STATUS 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 2-448 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location MSR_UNC_CBO_3_PERFCTR0 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-40 MSR_UNC_CBO_3_PERFCTR1 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-40 MSR_UNC_CBO_3_PERFCTR2 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 MSR_UNC_CBO_3_PERFCTR3 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 MSR_UNC_CBO_3_PERFEVTSEL0 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-40 MSR_UNC_CBO_3_PERFEVTSEL1 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-40 MSR_UNC_CBO_3_PERFEVTSEL2 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 MSR_UNC_CBO_3_PERFEVTSEL3 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 MSR_UNC_CBO_3_UNIT_STATUS 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 MSR_UNC_CBO_4_PERFCTR0 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 MSR_UNC_CBO_4_PERFCTR1 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 MSR_UNC_CBO_4_PERFCTR2 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 MSR_UNC_CBO_4_PERFCTR3 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 MSR_UNC_CBO_4_PERFEVTSEL0 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 MSR_UNC_CBO_4_PERFEVTSEL1 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 MSR_UNC_CBO_4_PERFEVTSEL2 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 MSR_UNC_CBO_4_PERFEVTSEL3 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 Vol. 4 2-449 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location MSR_UNC_CBO_4_UNIT_STATUS 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 MSR_UNC_CBO_CONFIG 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-40 MSR_UNC_PERF_FIXED_CTR 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-40 MSR_UNC_PERF_FIXED_CTRL 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-40 MSR_UNC_PERF_GLOBAL_CTRL 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-40 MSR_UNC_PERF_GLOBAL_STATUS 06_2AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-22 06_3CH, 06_45H, 06_46H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-30 06_4EH, 06_5EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-40 MSR_UNCORE_ADDR_OPCODE_MATCH 06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-16 MSR_UNCORE_FIXED_CTR_CTRL 06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-16 MSR_UNCORE_FIXED_CTR0 06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-16 MSR_UNCORE_PERF_GLOBAL_CTRL 06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-16 MSR_UNCORE_PERF_GLOBAL_OVF_CTRL 06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-16 MSR_UNCORE_PERF_GLOBAL_STATUS 06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-16 MSR_UNCORE_PERFEVTSEL0 06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-16 MSR_UNCORE_PERFEVTSEL1 06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-16 MSR_UNCORE_PERFEVTSEL2 06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-16 MSR_UNCORE_PERFEVTSEL3 06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-16 2-450 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location MSR_UNCORE_PERFEVTSEL4 06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-16 MSR_UNCORE_PERFEVTSEL5 06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-16 MSR_UNCORE_PERFEVTSEL6 06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-16 MSR_UNCORE_PERFEVTSEL7 06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-16 MSR_UNCORE_PMC0 06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-16 MSR_UNCORE_PMC1 06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-16 MSR_UNCORE_PMC2 06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-16 MSR_UNCORE_PMC3 06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-16 MSR_UNCORE_PMC4 06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-16 MSR_UNCORE_PMC5 06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-16 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_UNCORE_PMC6 06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-16 MSR_UNCORE_PMC7 06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-16 MSR_UNCORE_PRMRR_BASE 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_UNCORE_PRMRR_MASK 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MSR_UNCORE_PRMRR_PHYS_BASE 06_8EH, 06_9EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-41 MSR_UNCORE_PRMRR_PHYS_MASK 06_8EH, 06_9EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-41 MSR_W_PMON_BOX_CTRL 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_W_PMON_BOX_OVF_CTRL 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_W_PMON_BOX_STATUS 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_W_PMON_CTR0 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_W_PMON_CTR1 Vol. 4 2-451 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_W_PMON_CTR2 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_W_PMON_CTR3 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_W_PMON_EVNT_SEL0 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_W_PMON_EVNT_SEL1 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_W_PMON_EVNT_SEL2 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_W_PMON_EVNT_SEL3 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_W_PMON_FIXED_CTR 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_W_PMON_FIXED_CTR_CTL 06_2EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-17 MSR_WEIGHTED_CORE_C0 06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-39 MTRRfix16K_80000 06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-53 MTRRfix16K_A0000 06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-53 MTRRfix4K_C0000 06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-53 MTRRfix4K_C8000 06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-53 MTRRfix4K_D0000 06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-53 MTRRfix4K_D8000 06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-53 MTRRfix4K_E0000 06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-53 MTRRfix4K_E8000 06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 2-452 Vol. 4 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-53 MTRRfix4K_F0000 06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-53 MTRRfix4K_F8000 06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-53 MTRRfix64K_00000 06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-53 MTRRphysBase0 06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-53 MTRRphysBase1 06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-53 MTRRphysBase2 06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-53 MTRRphysBase3 06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-53 MTRRphysBase4 06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-53 MTRRphysBase5 06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-53 MTRRphysBase6 06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-53 MTRRphysBase7 06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-53 MTRRphysMask0 06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-53 MTRRphysMask1 06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-53 MTRRphysMask2 06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 Vol. 4 2-453 MODEL-SPECIFIC REGISTERS (MSRS) MSR Name and CPUID DisplayFamily_DisplayModel Location P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-53 MTRRphysMask3 06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-53 MTRRphysMask4 06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-53 MTRRphysMask5 06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-53 MTRRphysMask6 06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-53 MTRRphysMask7 06_0EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-51 P6 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Table 2-53 2-454 Vol. 4 INDEX A Addressing, segments, 1-6 Advanced programmable interrupt controller (see I/O APIC or Local APIC) APIC (see I/O APIC or Local APIC) B Backlink (see Previous task link) Binary numbers, 1-5 Bit order, 1-4 Branch trace message (see BTM) Branch trace store (see BTS) BTS (branch trace store) facilities BTS_UNAVAILABLE flag, IA32_MISC_ENABLE MSR, 2-335 Byte order, 1-4 C Capability MSRs See VMX capability MSRs Compatibility software, 1-4 Context, task (see Task state) CPUID instruction syntax for data, 1-6 Current privilege level (see CPL) D Debug store (see DS) DEBUGCTLMSR MSR, 2-375 Debugging facilities see DS (debug store) mechanism E Exceptions notation, 1-7 G Global descriptor table register (see GDTR) Global descriptor table (see GDT) H Hexadecimal numbers, 1-5 I IA32_APIC_BASE MSR, 2-326 IA32_BIOS_SIGN_ID MSR, 2-329 IA32_BIOS_UPDT_TRIG MSR, 2-329 IA32_CLOCK_MODULATION MSR, 2-52, 2-65, 2-74, 2-124, 2-162, 2-314, 2-333, 2-356, 2-365 IA32_CTL MSR, 2-330 IA32_DEBUGCTL MSR, 2-337 IA32_DS_AREA MSR, 2-347 IA32_MCG_CAP MSR, 2-330 IA32_MCG_MISC MSR, 2-332 IA32_MCG_R10 MSR, 2-332 IA32_MCG_R11 MSR, 2-332 IA32_MCG_R15 MSR, 2-333 IA32_MCG_RAX MSR, 2-330 IA32_MCG_RBX MSR, 2-330 IA32_MCG_RESERVEDn, 2-332, 2-430 IA32_MCG_RFLAGS MSR, 2-331, 2-430 IA32_MCG_RIP MSR, 2-331, 2-430 IA32_MCi_ADDR MSR, 2-344 IA32_MCi_CTL MSR, 2-344 IA32_MCi_MISC MSR, 2-344 IA32_MCi_STATUS MSR, 2-344 IA32_MISC_ENABLE MSR, 2-334 IA32_MTRRCAP MSR, 2-330 IA32_MTRR_PHYS BASEn MTRR, 2-338 IA32_MTRR_PHYSBASEn MTRR, 2-338 IA32_MTRR_PHYSMASKn MTRR, 2-338 IA32_P5_MC_ADDR MSR, 2-326 IA32_P5_MC_TYPE MSR, 2-326 IA32_PEBS_ENABLE MSR, 2-343 IA32_PLATFORM_ID, 2-47, 2-61, 2-120, 2-158, 2-309, 2-326, 2-352, 2-362, 2-369 IA32_STATUS MSR, 2-330 IA32_SYSENTER_CS MSR, 2-330 IA32_SYSENTER_EIP MSR, 2-330 IA32_SYSENTER_ESP MSR, 2-330 IA32_TERM_CONTROL MSR, 2-52, 2-65, 2-74, 2-124, 2-162 IA32_THERM_INTERRUPT MSR, 2-333 IA32_THERM_STATUS MSR, 2-333 IA32_TIME_STAMP_COUNTER MSR, 2-326 IA32_VMX_BASIC MSR, 2-58, 2-69, 2-78, 2-134, 2-172, 2-346, 2-360 IA32_VMX_CR0_FIXED0 MSR, 2-59, 2-70, 2-78, 2-134, 2-172, 2-347, 2-360 IA32_VMX_CR0_FIXED1 MSR, 2-59, 2-70, 2-78, 2-134, 2-172, 2-347, 2-361 IA32_VMX_CR4_FIXED0 MSR, 2-59, 2-70, 2-78, 2-134, 2-172, 2-347, 2-361 IA32_VMX_CR4_FIXED1 MSR, 2-59, 2-70, 2-79, 2-134, 2-172, 2-173, 2-347, 2-361 IA32_VMX_ENTRY_CTLS MSR, 2-59, 2-70, 2-78, 2-134, 2-172, 2-347, 2-360 IA32_VMX_EXIT_CTLS MSR, 2-58, 2-70, 2-78, 2-134, 2-172, 2-346, 2-360 IA32_VMX_MISC MSR, 2-59, 2-70, 2-78, 2-134, 2-172, 2-347, 2-360 IA32_VMX_PINBASED_CTLS MSR, 2-58, 2-69, 2-78, 2-134, 2-172, 2-346, 2-360 IA32_VMX_PROCBASED_CTLS MSR, 2-58, 2-59, 2-70, 2-78, 2-79, 2-134, 2-135, 2-172, 2-173, 2-208, 2-346, 2-360, 2-361 IA32_VMX_VMCS_ENUM MSR, 2-347 Instruction operands, 1-5 Intel 64 architecture definition of, 1-4 relation to IA-32, 1-4 Intel Core Solo and Duo processors model-specific registers, 2-352 Intel NetBurst microarchitecture, 1-3 Intel software network link, 1-8 Intel VTune Performance Analyzer related information, 1-8 Intel Xeon processor, 1-1 Interrupts interrupt descriptor table register (see IDTR) interrupt descriptor table (see IDT) IPI (see interprocessor interrupt) L Last branch record stack, 2-337, 2-338, 2-347 Local descriptor table register (see LDTR) Local descriptor table (see LDT) LVT (see Local vector table) M Memory type range registers (see MTRRs) Vol. 4 INDEX-1 INDEX Model-specific registers (see MSRs) Modes of operation (see Operating modes) MSRs architectural, 2-3 list of, 2-1 P6 family processors, 2-368 Pentium 4 processor, 2-46, 2-60, 2-189, 2-206, 2-223, 2-326, 2-351 Pentium processors, 2-377, 2-454 MSR_DEBUGCTLA MSR, 2-337 MSR_DEBUGCTLB MSR, 2-55, 2-67, 2-75, 2-128, 2-165, 2-208, 2-317, 2-358, 2-367 MSR_EBC_FREQUENCY_ID MSR, 2-328, 2-329 MSR_EBC_HARD_POWERON MSR, 2-326 MSR_EBC_SOFT_POWERON MSR, 2-328, 2-399 MSR_LASTBRANCH _TOS, 2-337 MSR_LASTBRANCH_0_TO_IP, 2-349 MSR_LASTBRANCH_n MSR, 2-338, 2-402 MSR_LASTBRANCH_n_FROM_IP MSR, 2-347 MSR_LASTBRANCH_n_TO_LIP MSR, 2-349 MSR_LER_FROM_LIP MSR, 2-337 MSR_LER_TO_LIP MSR, 2-337 MSR_PEBS_MATRIX_VERT MSR, 2-344, 2-432 MSR_PLATFORM_BRV, 2-336, 2-435 S Segmented addressing, 1-6 System-management mode (see SMM) T Translation lookaside buffer (see TLB) U Uncached (UC) memory type (see Strong uncached (UC) memory type) V NetBurst microarchitecture (see Intel NetBurst microarchitecture) Nonmaskable interrupt (see NMI) Notation bit and byte order, 1-4 conventions, 1-4 exceptions, 1-7 hexadecimal and binary numbers, 1-5 Instructions operands, 1-5 reserved bits, 1-4 segmented addressing, 1-6 VMX capability MSRs IA32_VMX_BASIC MSR, 2-58, 2-69, 2-78, 2-134, 2-172, 2-346, 2-360 IA32_VMX_CR0_FIXED0 MSR, 2-59, 2-70, 2-78, 2-134, 2-172, 2-347, 2-360 IA32_VMX_CR0_FIXED1 MSR, 2-59, 2-70, 2-78, 2-134, 2-172, 2-347, 2-361 IA32_VMX_CR4_FIXED0 MSR, 2-59, 2-70, 2-78, 2-134, 2-172, 2-347, 2-361 IA32_VMX_CR4_FIXED1 MSR, 2-59, 2-70, 2-79, 2-134, 2-172, 2-173, 2-347, 2-361 IA32_VMX_ENTRY_CTLS MSR, 2-59, 2-70, 2-78, 2-134, 2-172, 2-347, 2-360 IA32_VMX_EXIT_CTLS MSR, 2-58, 2-70, 2-78, 2-134, 2-172, 2-346, 2-360 IA32_VMX_MISC MSR, 2-59, 2-70, 2-78, 2-134, 2-172, 2-347, 2-360 IA32_VMX_PINBASED_CTLS MSR, 2-58, 2-69, 2-78, 2-134, 2-172, 2-346, 2-360 IA32_VMX_PROCBASED_CTLS MSR, 2-58, 2-59, 2-70, 2-78, 2-79, 2-134, 2-135, 2-172, 2-173, 2-208, 2-346, 2-360, 2-361 IA32_VMX_VMCS_ENUM MSR, 2-347 O W N Operands instruction, 1-5 P P5_MC_ADDR MSR, 2-47, 2-61, 2-72, 2-120, 2-157, 2-309, 2-352, 2-361, 2-368, 2-378 P5_MC_TYPE MSR, 2-47, 2-61, 2-72, 2-120, 2-157, 2-309, 2-352, 2-362, 2-368, 2-378 P6 family processors description of, 1-1 MSR supported by, 2-368 Page frame (see Page) PDBR (see CR3 control register) PEBS_UNAVAILABLE flag IA32_MISC_ENABLE MSR, 2-335 Pentium 4 processor, 1-1 MSRs supported, 2-46, 2-60, 2-71, 2-88, 2-91, 2-114, 2-118, 2-326, 2-351 Pentium II processor, 1-3 Pentium III processor, 1-3 Pentium M processor MSRs supported by, 2-361 Pentium Pro processor, 1-3 Pentium processor, 1-1 MSR supported by, 2-377 Precise event-based sampling (see PEBS) R Related literature, 1-7 Requested privilege level (see RPL) Reserved bits, 1-4 INDEX-2 Vol. 4 WC buffer (see Write combining (WC) buffer)
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