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Systems Technology
Sentry 400
Computer Controlled Test System
Instruction Manual
STOCK NO.: 67094471
ISSUED: October 1970
© 1970 by Fairchild Systems Technology, 974 East Arques Ave., Sunnyvale, Calif. 94086
FAIRCHIL.O
SYSTEMS TECHNOLOGY
VVarranty____________________________________
Seller warrants equipment of its manufacture against defective materials or workmanship for
a period of one year from date on which Seller determines the installation to be complete.
The liability of the Seller under this warranty is limited, at Sellers option, solely to repair,
replacement with equivalent Fairchild eOquipment, or an appropriate credit adjustment not
to exceed the original equipment sales price, of equipment returned to the Seller provided
that (a) Seller is promptly notified in writing by Buyer upon discovery of defects, (b) the
defective equipment is returned to Seller, transportation charges prepaid by Buyer, and (c)
Seller's examination of such equipment disclosed to its satisfaction that defects were not
caused .by negligence, misuse, improper installation, accident, or unauthorized repair or
alteration by the Buyer. This warranty does not include mechanical parts failing from
normal usage nor does it cover limited life electrical components which deteriorate with age
such as vacuum tubes, choppers, lamps, etc. In the case of accessories, ie, card punches,
typewriters, etc., not manufactured by Seller, but which are furnished with the Seller's
eq uipmen t. Seller's liability is limited to whatever warranty is extended by the
manufacturers thereof and transferable to the Buyer. This warranty is expressed in lieu of
all other warranties, expressed or implied, including the implied warranty of fitness for a
particular purpose, and of all other obligations or liabilities on the Seller's part, and it
neither assumes nor authorizes any other person to assume for the Seller any other
liabilities. This warranty should not be confused with or construed to imply free
preventative or remedial maintenance, calibration or other service required for normal
operation of the equipment.
F=AIRCHILD
SYSTEMS TEC~CX;Y
FORM 700617
List of Effective Pages _ _ _ _ _ _ _ _ _ __
SENTRY 400
The total number of pages of this publication is 136, consisting
of the following:
Page No.
Title.
Warranty.
i through vii .
Section I Title .
Frontispiece.
1-1 through 1-28 .
2-1 through 2-8
3-1 through 3-55
4-1 through 4-35
FORM 700620
Issue
Original
Original
Original
Original
Original
Original
Original
Original
Original
Table
of
Contents
Page
'SECTION I
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
GENERAL INFORMATION
Introduction
General Description
Typical System Configuration
Tester Operating Features
Automatic
Manual
Monitor
Timing
Sentry 400 System Description
Test Station
Monitor Station
FST-l Computer System
Functional Description
Multiplexing
Manual Mode
Output Pin Loading
Power Supply Decoupling
MOS Input Pin Stressing
Input Bias Voltage
Programming Characteristics
Physical Description and Specifications
Mainframe and Options
Test Station
Model 8103, 30-Pin Test Station
Model 8106, 60-Pin Test Station
Model 8109, 90-Pin Test Station
Model 8112, 120-Pin Test Station
Computer and Peripherals
Model 2101 FST-l Computer
Model 2060 Disc File
Model 2070 Magnetic Tape Controller
Model 2071 Magnetic Tape Transport
Model 2121 FST-l Software Package
Model 2084 Console Typewriter with Paper Tape
Model 2085 Console Typewriter with Paper Tape
Model 2087 Console Typewriter
Model 2086 Punched Card Reader
Model 2110 Extension Bay
Model 2130 Core Memory Expansion
.1-1
.1-1
.1-2
.1-3
.1-3
.1-3
.1-3
.1-6
.1-6
.1-7
.1-9
1-11
1-12
1-15
1-15
1-16
1-16
1-17
1-17
1-17
1-18
1-19
1-20
1-20
1-21
1-21
1-21
1-22
1-22
1-22
1-23
1-23
1-23
1-24
1-24
1-24
1-24
1-24
1-24
iii
TABLE OF CONTENTS (Continued)
Page
SECTION I
1.11
Systems Software
Model 8201 Sentry 400 Software Package
SECTION II
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.2
3.3
3.4
3.5
iv
1-25
1-25
INSTALLATION
General
Inspection
Un crating
Installation
Reshipment
Layout
Interconnecting Cables
AC Power
Air Conditioning and Humidity Requirements
SECTION III
3.1
GENERAL INFORMATION (Continued)
.2-1
.2-1
.2-1
.2-1
.2-1
.2-2
.2-2
.2-2
.2-2
OPERATION
Introd uction
Controls and Indica tors
System Power On Procedure
Power Failures and Alarms
System Power Off Procedure
Loading Sentry 400 Device Test Programs into the Computer
Loading DOPSY from Disc Memory
Compiling a Source Factor Program
Loading TOPSY from Disc
Loading Device Test Program from Disc Using TOPSY
Initialize or Modify Tester Operating Conditions with TOPSY
with TOPSY Monitor Commands
Initiation of Active Device Testing
Preparing Performance Board for Testing
Inserting Performance Board and Device into Tester
Select Test Mode and Commence Testing
Error Messages
Editing FACTOR Programs
.3-1
.3-1
3-29
3-29
3-29
3-30
3-31
3-32
3-35
3-36
3-36
3-38
3-38
3-41
3-41
3-42
3-51
TABLE OF CONTENTS (Continued)
Page
SECTION IV
4.1
4.2
4.3
PROGRAMMING
Introduction
Tester Statements, General Description
Programming Procedures
Preliminary Tester Setup Statements
Functional Testing Statements
Program Simplification
DC Testing Statements
Programming Rules
Device Program Preparation
.4-1
.4-2
.4-7"
.4-7
4-10
4-16
4-18
4-19
4-20
v
List
of
Illustrations
Figure
Frontispiece: Sentry 400 Computer Controlled Test System
1-1.
Functional Block Diagram
1-2.
Sentry400 Multiple Test Stations (Maximum Configuration)
1-3.
Engineering Wafer Test and Package Test Systems
1-4.
Sentry 400 Test Station
1-5.
Monitor Station and FST-1 Computer
1-6.
FST-1 Computer System, Simplified
Sentry 400 Test Station Block Diagram - Simplified
1-7.
1-8.
System Configuration and Model Numbers
2-1.
Sentry 400 Test System Suggested Layout A
Sentry 400 Test System Suggested Layout B
2-2.
2-3.
Sentry 400 Test System Cabling Diagram
2-4.
Interconnecting Cabling, FST-l Computer and Peripherals
3-1.
FST-1 Computer Control Panel
3-2.
Sentry 400 Test Station Console Control Panel
3-3.
Sentry 400 Monitor Station Control Panel
3-4.
Teletype Model ASR-33
3-5.
Teletype Model ASR-35
3-6.
FST-1 Model 2060 Disc Memory
3-7.
FST-1 Model 2086 Punched Card Reader
3-8.
Model 2071 Magnetic Tape Unit
3-9.
Model 2310 Line Printer Controls and Indicators
3-10A. Fairchild Universal Load Board (Front)
3-10B. Fairchild Universal Load Board (Rear)
3-11. Simplified Tester Schematic
3-12. Load Board, Two Values of Load Resistance
3-13. Load Board, Programmable Current Source
3-14. Load Board, Switched Load Resistance
3-15. Load Board, Programmable Power Supply
3-16. Load Board, High Frequency
4-1.
Actual Source Program Listing
4-2.
Simplified Block Diagram
4-3.
Programmed Clock Timing Examples
4-4.
Sentry 400 Factor Coding Form
4-5.
Sentry 400 Device Program
vi
Page
.1-2
.1-4
.1-5
.1-8
1-10
1-13
1-14
1-19
.2-3
.2-4
2-5/2-6
2-7/2-8
.3-9
3-13
3-16
3-18
3-21
3-22
3-24
3-26
3-28
3-39
3-40
3-43
3-44
3-45
3-46
3-47
3-48
4-11/4-12
· 4-13
· 4-16
4-23/4-24
· 4-25
List
of Tables
Table
I-I.
1-2.
3-I.
3-2.
3-3.
3-4.
3-5.
3-6.
3-7.
3-8.
3-9.
3-10.
3-11.
3-12.
3-13.
3-14.
3-15.
4-1.
Pages
Electrical Specification Summary
General Specifications
FST-l CPU Controls and Indicators
Sentry 400 Test Station Console, Controls and Indicators
Sentry 400 Monitor Control Panel Controls and Indicators
FST-l 2084 Teletype Model ASR-33 Controls and Indicators
FST-l 2085 Teletype Model ASR-35 Controls and Indicators
FST-l Model 2060 Disc File Controls and Indicators
FST-l Model 2086 Punched Card Reader Controls and Indicators
Model 2071 Magnetic Tape Unit Controls and Indicators
FST-l Model 2310 Line Printer Controls and Indicators
Summary of DOPSY Commands
Summary of TOPSY Commands
TOPSY Command Format Examples
Error Messages
DOPSY Edit Program Commands
DOPSY Editor Printout
Sentry 400 Tester Statements Summary
1-26
1-27
.3-2
3-10
3-14
3-17
3-19
3-22
3-23
3-25
3-27
3-30
3-37
3-38
3-49
3-52
3-54
.4-2
vii
Section I
General Information
Frontispiece
Sentry 400 Computer Controlled Test System.
Section I
General Information
1. 1 INTROD UCTION
This manual provides information for installation, operation and programming of the Sentry
400 Computer Controlled Test System. The description in this manual is confined to the
tester portion of the system; the FST-1 Fairchild computer and software packages are described in separate manuals. Section I contains a general description of the system together
with a table of specifications. The photograph on the facing page is a front view of a single
station Sentry 400 Computer Controlled Test System.
1.2 GENERAL DESCRIPTION
The Sentry 400 Computer Controlled Test System provides the capability to automatically
test digital networks such as; large scale integrated arrays (MOS, BIPOLAR), complex integrated circuits, printed circuit cards, and other digital subsystems. Multiplexing is provided
for operating four test stations with one FST-1 computer. Each test station can test
different electronic devices or modules with up to 120 pins. Each test station pin capability
is expandable in groups of 30 up to a maximum of 120 pins. Two 120 pin test enclosures
may be used for up to a 240 pin test configuration. Each pin has the capability to be defined
either as an input pin or an output pin. Through system software it is possible to instruct
the tester to perform various operations on the device-under-test such as assign input/output
pins, execute tests, indicate Go/No-Go results and print test results.
Basically, the system performs two types of tests; functional tests (that determine whether
the device performs the intended logic operations) and precision DC tests (that determine
whether component parameters meet device specifications). Functional tests are performed
by forcing programmed logic levels on the input pins of the device-under-test and comparing
the device outputs with programmed expected outputs. Absolute DC tests allow programmable measurement of network parameters such as saturation voltage and input leakage. In
addition, the magnitude of all test system reference voltages and currents such as Go/No-Go
thresholds, device supply voltages and functional logic level forcing magnitudes are programmable.
The number of tests required to adequately test an array has a large influence not only on
test throughput rate but also on test system configuration. The maximum test rate is
approximately 286,000 functional tests per second and 250 DC tests per pin per second.
The maximum number of tests that can be performed on a single device without using programming loops, is approximately 130,000. Using loops, programs can be extended to any
length.
1-1
1.3 TYPICAL SYSTEM CONFIGURATION
Figure 1-1 shows the basic block diagram of the system. The Fairchild FST-l computer is
the primary controller. Tester instructions are held in bulk storage (disc or magnetic tape)
and are transmitted to the computer memory when required. The test head, power supplies
and timing controls receive their instructions from core memory under control of the computer.
-
COMPUTER
r
r
PROGRAMMABLE
SUPPLIES, TEST
RATE CONTROL
BULK STORAGE
~
r
ELEMENT
UNDER TEST
MULTIPLEXER
,
I~
-
TEST HEAD
DRIVERS, SENSORS
-
I I I
I I I
I I I
I I I
I I I
UP TO FOUR
Figure 1-1. Functional Block Diagram
For functional tests, the tester applies logic levels representing forcing functions to the
input pins of the unit under test and compares actual outputs to the predicted responses on
a "Go/No-Go" basis. The expected output thresholds are programmable as are the input
logic levels.
For DC tests, a single pin can be addressed with an instruction that calls for a DC
(Absolute) measurement. A switching network then connects the Precision Measurement
Unit to the addressed pin and executes the measurement. A pin is always restored to its
previous functional test condition prior to being connected to, or released from, the DC
measurement unit.
1-2
The computer can control the unit-under-test device handler such that wafer indexing and
"class" sorting is automatic, depending on the result of tests performed. A fifteen bit
storage register is available for this purpose.
Figure 1-2 shows a Sentry 400 test system with multiple test stations. The configuration
allows independent testing of devices of different design, therefore increasing the testing
throughput rate. The amount of peripheral equipment required per system varies according to the environment of operation. For example, test engineering may require the most
peripherals since these groups will be continually generating new-design test programs
and new test techniques. The operations are typical electronic data processing operations
and are most efficiently done only if a card reader, magnetic tape, disc, printer, and teletype are available. In the production wafer-test environment, a minimum of peripherals are
required. Prepared programs on magnetic tape can easily be transferred to the disc. There
can be 350 programs of an average length of 1450 tests stored on the disc for immediate
access. Figure 1-3 shows probable peripheral configurations for the engineering, wafer-test,
and package test systems.
1.4 TESTER OPERATING FEATURES
There are three basic modes of operation for the test system: (1) Automatic, (2) Manual,
(3) Monitor.
1.4.1 Automatic
In the Automatic mode the test system operation is self-contained within the program. This
mode of operation is primarily intended for the production environment where there is
little need for operator intervention:
1.4.2 Manual
In the Manual mode a single programmed instruction is executed each time the "start"
button is depressed. This mode of operation is useful for program verification where the
operator needs to single step through a program.
With a multiple test system, any or all stations may be in Manual operation simultaneously.
A manual station will not inhibit other stations from testing. After executing a single step
at Station A, the controller will accept start requests from other stations before returning to
Station A.
1.4.3 Monitor
In the Monitor mode the operator is provided the opportunity to intervene with the programmed control of the test system. This mode is primarily intended for use in the prototype design test environment. In this mode the operator has a variety of options such as,
modifying programmed delays, selecting datalogging conditions, modifying programmed voltages, etc. (Voltages may be modified in any mode by the control panel override.)
1-3
Sentry 400
0
t
,......'--
Disc
Storage
--Unit
t
Q9
I
Magnetic
Tape
Unit
FST·l
Computer
and
Memory
I
I
--
I
Sentry 400
Reference
and
Multiplex
Unit
Test Station
(120 Pins)
-..
Test Station
(120 Pins)
~
Teletype
~
I
\
Card
Reader
I
Test Station
(120 Pins)
I
Line
printer} -'"
Figure 1-2. Sentry 400 Multiple Test Stations (Maximum Configuration)
1-4
Test Station
(120 Pins)
Section I
Sentry 400
Mag
Tape
Unit
Disc Storage
FST-l
Computer
and
Menory
Card
Reader
Sentry 400
Reference
and
MUltiplex
Unit
(]~
Teletype
-
line
Printer
(70Automatic Handler
~
I
~
--
--
Engineering
Station
Wafer
Probe
Station
Displays
-
....
QJD
Wafer
Probe
Station
~
II
QD
L.-.
I ~
Figure 1-3 Engineering Wafer-Test and Package Test Systems
1-5
When the monitor switch is on, and TOPSY is resident in core, the operator can instruct
the tester to perform functions that are primarily useful while debugging a prototype array.
Examples of these instructions are listed below:
1.
Title message (date, run number, etc.).
2.
Stop on failure.
3.
Stop on instruction Number N.
4.
Modify the test rate.
5.
Recycle on a group of functional tests. This allows the element-undertest response wave forms, to be displayed on an oscilloscope.
6.
Datalog on functional failure.
7.
Da talog DC parameter failures.
8.
Datalog any measurement so specified in the program.
9.
Datalog all functions listed above.
10.
Specify test programs on respective test stations.
11.
Sync on instruction Number N to trigger some external monitoring
device when the program executes Statement N.
12.
Specify values of global variables.
1. 4.4 Timing
The tester timing with respect to the element-under-test can be programmed such that
either combinatorial or sequential networks can be readily tested. For functional tests on
combinatorial networks the tester comparator "strobe" is delayed according to the programmed test rate.. counter. F~)f functional tests on sequential networks there are sync signals
·tft.~ li 0./ /tJt,;; ~ l",(l;,t.'"
available on a.rQAt patlel jaelt which can be wired to the clock pins on the element-undertest. Alternatively they can be wired to wave shaping circuits (supplied by the user) and
then to the element-under-test, or can be used to trigger external clock generators. The
timing for sequential tests supplies a minimum of one sync pulse followed by a "strobe" to
the comparators. The "strobe" is delayed according to the programmed test rate.
I.S SENTRY 400 SYSTEM DESCRIPTION
The Sentry 400 System consists of a single bay enclosing each test station and a double bay
enclosing the FST-I Computer and Monitor Station. A maximum of four test stations may
be used in a single installation. The following paragraphs briefly describe the functions of
each bay.
1-6
1. 5.1 Test Station
Figure 1-4 is an illustration of a test station. Directly below the controls and display panel
are the input/output connectors. Each connector provides two terminals (force and sense)
for each DUT pin. Pins 1-30 and 31-60 are accommodated by the bottom right and left
hand connectors and pins 61-120 are accommodated by the two top connectors. The user
may wire his test socket or probe ring to the appropriate pins of the connectors. Five load
boards for each 30 pin configuration are provided the user. The load boards, when inserted,
are connected in parallel with the appropriate pins of the connector. They may be used in
such applications as tests performed with output pins under load, collector outputs
requiring pull up resistors, recirculation logic for high speed shift register testing, etc.
Connection between the test socket and test circuits are provided by high speed relays. The
relays connect either the drivers, detectors, or utility lines to the pins according to programmed instructions.
The controls and display panel contains various controls and indicators that enable the
operator to start a test either in the automatic or manual mode of operation. For this
purpose a pushbutton labeled MAN is provided. When this pushbutton is depressed the
station is in Manual mode. A second button, ADV, enables the operator to single step
through a test program. If the MAN pushbutton is not depressed the system is in Automatic
mode. Indicator lamps inform the operator of the pass or fail status of the device both for
function testing and parameter testing; the end of a test is also displayed. These indicators
are updated any time testing pauses.
Register Selector pushbuttons allow the operator to select two long registers whose contents
will be simultaneously displayed by two rows of 15 register display lamps. There are eight
ranks to each register. By appropriate combination of rank selector and register selector the
status of all 120 pins can be displayed.
The rank fail indicator illuminates when a pin of a certain rank fails. This register may then
be displayed on the register display lamps to determine which pin has failed. This type of
dis play is useful while debugging prototype designs and test program verification.
Input/output pin assignments can be displayed on one row while the forcing and expected
outputs are displayed on the other row. The selector switches also allow the comparator
register mask (ignored pins), utility and input reference select registers to be displayed. The
selector switch will also enable a lamp test.
There is a numerical display of the test instruction number which is currently in the tester.
This is extremely valuable for program verification by the operator when the tester is in the
manual mode and is being single stepped. It is always updated with the number of the last
test executed when the test pauses.
A Precision Measurement Unit is provided for each test station to measure the DC characteristics of the pins of the device-under-test. This type of testing is essential for specifying
semiconductor parameters such as saturation voltage and input leakage. The Precision
Measurement Unit is capable of forcing a voltage or current on any tester pin. The Precision
Measurement Unit also is capable of measuring internal test head analog reference voltages
and power supply voltages and currents for purposes of system self-check under program
1-7
Section I
Sentry 400
POWER MOOULE
Figure 1-4. Sentry 400 Test Station
1-8
EACH MODULE IS 30 PINS
RO = PINS 1-30
R2 = PINS 31-60
R4 = PINS 61-90
R6 =PINS 91-120 .
control. Measurements are made with a high speed analog-to-digital converter with a 0.1%
accuracy and resolutions for voltages from 1 millivolt to 40 volts in three ranges and
currents from 1 nanoampere to 100 milliamperes in four ranges.
The mechanical configuration of the test station is designed not only for ease in operation
but also from the servicing and expansion point of view.
The control panel is hinged on the bottom; slight forward pressure on the top of the panel
will release the front panel and reveal the display lamps and circuitry associated with the
controls and indicators. The complete control and indicator module may be removed by
removing two thumb screws and a single connector at the rear of the module.
The power supplies are contained in the center section of the bay, and are accessible by
pulling on the black handle recessed in the side door frames. The power supplies are
mounted such that all potentiometer controls are available for adjustment. The side door
frame members contain all the connectors into which are inserted printed circuit cards, containing drivers, detectors, and logic circuits.
A convenience panel located below the working surface, provides 115 volts ac convenience
outlets, connectors for handlers, wafer probes, external clock pulses, vacuum and air outlets
and connectors for foot operated switches.
1.5.2 Monitor Station
Figure 1-5 is an illustration of the Monitor Station and FST-I Computer. The monitor
station is contained in the right hand half of the double bay. All digital programmable
supplies and Reference Voltage supplies are contained in this bay. The main function of this
station is to provide manual adjustments of all DPS's and RVS's. Selector switches enable
the operator to select a test station for monitor operation; all other stations continue
normal operation under program control.
Coarse and fine adjustments permit the operator to manually override the programmed voltages of the DPS's or RVS's. The voltages may be displayed on a Nixie light display provided
by a digital voltmeter. Many of the advantages and features of the monitor station are
described in the Tester Operating Features section of this manual.
The control panel, like the test station, is hinged and can be folded down. The control
panel and chassis is mounted on runners and can be pulled forward revealing a vertical
chassis which in turn is hinged at the rear and can be folded back. All DPS's and RVS's and
control circuits are mounted on plug-in boards and mounted in the vertical foldout chassis.
The main power distribution module for the entire Sentry 400 System is contained in the
rear of the monitor station main frame. Two 208 volts, AC, five-wire inputs are filtered and
distributed at the required voltage levels to the system. Power for the monitor station is
provided by six supplies. Potentiometer adjustments for these supplies are accessed through
a power adjustment panel, below the working surface. A power distribution unit (8005) is
also available which provides isolation/constant voltage for the Sentry 400 in sub-standard
power environments.
1-9
Section I
Sentry 400
INTERFACE
SENTRY
400
Figure 1-5. Monitor Station and FST-1 Computer
1-10
1.5.3 FST-l Computer System
The FST-1 is a general purpose digital computer occupying the left hand portion of the
double bay next to the monitor station (see Figure 1-5). Listed below are some of the
FST-I features:
24-bit data word
1.75 microsecond memory-cycle time
Magnetic ferrite-core memory
4096-word memory modules
Options to comprise a maximum of four memory modules, a total of 16,384
words per CPU
Dual memory-access subsystems via two memory busses
Random direct memory access, stored or retrieved at 571,000 words per second
per memory bus
Separate interface control between memory modules and CPU or peripheral units
Interrupt subsystem for communications and datum transfer between CPU and
peripheral units via accumulator bus
16 external interrupt channels and a maximum of 63 interrupt locations in
memory
Seven index registers for address modification
Indirect addressing for most instructions
A six bit operation code for the following types of instructions:
load and store
arithmetic
logical operations
register and state
conditional and unconditional branch (transfer-of-control)
shift
input/output
Two's-complement single and double precision arithmetic-add, subtract, and hardware multiply and divide.
The FST-I Computer System basically consists of three subsystems; the central processing unit,
memory and interface. The two memory modules (third and fourth optional) providing 4096
1-11
word locations each are contained in the bottom half of the bay below the controls and
indicator panel. The CPU and interface are contained on the same chassis as the front panel.
The front panel and chassis are mounted on runners and when pulled out, reveal the locations of the CPU and interface. The area generally is divided into four groups, AI, A2, A3,
and A4. Al contains the CPU, A2 contains Sentry 400 system interface, A3 and A4 contain
the peripheral unit interface.
All controls and indicators for the FST-l are contained on the front panel. The switch
register switches provide a means of manually setting up a 24 bit word, where a switch in
the up position represents a binary "1" and down a binary "0." The contents of the
registers are displayed by display lamps located above each switch.
The contents of various other working registers may also be displayed on the display lamps
by means of switches in the lower left portion of the panel. In the bottom right hand are
located the main computer switches; i.e., START, STOP, etc. A group of indicators display
the peripheral status of the various input/output units that interface with the CPU.
The basic configuration for the FST-l is shown in Figure 1-6. Data is held in the disc file
and on demand transferred to the memory.
The A memory and B memory· data buses are interfaced to the memory and are primarily
used for transmitting functional test data at memory speeds to and from the tester and
computer peripherals. Both of these memory buses may be in operation simultaneously providing they are communicating with two different peripherals. For instance; the B memory
could be transferring function test data to the tester, and simultaneously the disc file could
be transferring new test programs to memory. Access to memory is decided on a priority
basis.
The accumulator bus is interfaced to the CPU and is used for controlling the digital-toanalog and analog-to-digital converter subsystems. Systems falling into this group include the
Digital Programmable Power Supplies, Reference Voltage Supplies, Output Pin Reference
Supplies and data to the Precision Measurement Unit. The accumulator bus is also used for
communicating tester status, mode and interrupt information. A large and comprehensive
software package is provided by Fairchild for controlling the system. The Disc OPerating
SYstem program (DOPSY) is used for controlling data to and from the disc and memory.
The Tester OPerating SYstem (TOPSY) is used for controlling program transfer between
memory and the tester; FACTOR (Fairchild Algorithmic Compiler Tester ORiented)
language is very similar to FORTRAN and ALGOL-60 and used as the computer programming language. Various other subroutine library and diagnostic programs complete the
software package.
1.6 FUNCTIONAL DESCRIPTION
Figure 1-7 is a simplified block diagram of the Sentry 400 tester circuitry associated with one
pin. A minimum system consists of 30 pins worth of circuitry. Additions to the system are
made in groups of 30 up to a maximum of 120 pins. For a 240 pin configuration two 120 pin
enclosures are used. The driver and detector associated with each pin enables each pin to
1-12
A
MEMORY
B
MEMORY
A BUS
B BUS
COMMON MEMORY INTERFACE
COMMON
PERIPHERAL TESTER
INTERFACE
CENTRAL
PROCESSING
UNIT
1
ACCUMULATOR INTERFACE
l
_ ACCUMULATOR BUS
CPI
CARD
READER
1
CPI
DISC
FILE
UNIT
1
I I I
CPI
TTY
Figure 1-6. FST-1 Computer System, Simplified
be considered as an input pin, an output pin, or both depending upon programming of the
registers.
The system is provided with two pairs of analog input references, so that the programmer
has the flexibility of choosing between two levels. One of the two input analog buses is
selected by a "1" bit in the "S" register. Depending upon the excitation bit in the "F"
register, the driver is gated to produce a voltage equal to either the "1" or "0" level of the
pair selected by the "S" register.
If the device pin is an input pin a "1" bit in the "D" register closes relay Rl. The output
of the driver is applied to the pin of the DDT. If the device pin is an output pin a "0" bit
in the "D" register opens relay Rl. The pin of the DUT is now connected only to the input
of the detector. The detector also receives as an input a level proportional to the expected
output. If the device pin is an output, the expected output is compared with the actual
output of the pin. If the inputs are within the programmed limits, the detector will provide
a "0" output that is interpreted as a pass condition. If no comparison exists the detector
will provide a "1" output that is interpreted as a fail condition. The detectors are always
connected to the sense line through RO except when the PMU is addressed to that pin. The
level on a pin can therefore be sensed whether it be an input pin or an output pin.
1-13
Utility Line
Utility
Relay
"1"
A,,,log {
Input
"0"
Ref
"1"
{
Buses
"0"
REFERENCE
PAIR
SELECTOR
"1"
LOGIC ''1''
LOGIC "0"
SElECTOR
"0"
Force
Tester
Pin
Force
Sense
Sl
Expected
Output
Ref Buses
DECISION
LOGIC
_S::.;O:...-.-_ _ _ _ _ _.f--i
Fail
Relay Control
From PA
Register
RP 2
RP 1
F Reg M Reg Negative Strobe
Logic
r----------------I
D~~
OPS 1
I
~~I
>-
~k
--7Y.DPS 2
DPS 3
---7f---7:J.--
PRECISION
MEASUREMENT
UNIT
>-
I
~>!I
USERS
CLOCK
GENERATOR
OR WAVE
SHAPING
NETWORK
(
Sync
Sync
Output
Drivers
Output
Jack
I
I
TO LOAD BOARD
AND I/O CONNECTOR
MAIN
l
L FRAME
________________ JI
~
::l
r+
Figure 1-7. Sentry 400 Test Station Block Diagram - Simplified
-<
8o
'"'{he detector also receives an input from the M register (mask register). If the programmer is
interested in the output, the "M" register is programmed as a "1." The "1" condition
enables the detector to make the comparison between the actual output and the expected
output. If the programmer is not interested in the output level of the pin the "M" regsiter
is programmed as a "0." The "0" condition inhibits the output of the detector. The "C"
register and the function test fail output will indicate a pass. This feature is incorporated to
prevent unnecessary fail indications on a input pin, or an output pin with an undefined
logic state.
1.6.1 Multiplexing
The four test stations will initiate a test program by issuing a START request. Start requests
from all stations are stored in the Test Station Control (TSC) register which is located in
the mainframe.
At the completion of any station's test program, the tester operating system will read the
TSC register via the short register data bus. The Tester OPerating SYstem (TOPSY)
sequentially scans the four stations to find a start request. When the software pointer coincides with a start request in the TSC register, the appropriate test head address (two bit
code) will be issued and written into the TSC register. The test station address is hardware
decoded and one test head enable line (THEN) will become active. This signal resets the
station's start flip-flop in the TSC register and connects the long register data and analog
buses to the test station addressed.
A test program for each test station will be specified via the teletype monitor commands.
When a given test station is enabled, the appropriate test program is loaded from the disc
and then executed. At the end of test, the software pointer will start scanning all stations
for a start request. The pointer will stop at the next start request received. If the next start
request is from the same station that just completed a test, the test program is already
resident in main memory and won't be reloaded from the disc. Also, the multiplexer will
main tain connection to that test station. If the next start request was from a different test
station, and a different test program is being used at that station, then loading of the new
program from the disc will be executed and the multiplexer will connect the long register
data and analog buses to the ad~ressed station. The whole sequence takes about 30-40
milliseconds maximum.
There is no test station "priority." However, access is not necessarily granted on a first-come
first-served basis. Consider this example. Assume the software pointer moves in the 4-3-2-1-4
sequence, and a test at station one is in process. Start requests from stations 2, 3, and 4
that arrive in any order while station one is testing, will be serviced in order 4-3-2.
1.6.2 Manual Mode
Service of test stations in manual mode is handled as follows. The auto/manual switch at
each test station controls a bit in the TSC register. When the tester operating system reads
the TSC register, and a station with start request on and manual on is selected, the operating system allows one instruction to be executed. Then the TSC register is read and the
software pointer scans the start request bits. If no other station issues a start request before
1-15
the manual station sends start, the manual station's next start request, will cause another
instruction to be executed. Following each instruction executed at the manual station, the
operating system scans other stations to see if a start request has been sent. This procedure
prevents a station in manual mode from holding up testing at other stations. Therefore, if
none of the other stations ever send a start request, the manual station can keep executing
instructions without being interrupted. After each manual instruction, the operating system
reads the Instruction Number Counter via the short register data bus, and writes the number
into the test station Statement Number Display Register via the long register data bus.
Whenever another station issues a
operating system will record the
station, reset all short registers in
new test station. The multiplexer
will be executed.
start request, the manual station will be interrupted. The
number of the last statement executed by the manual
the mainframe (except TSC) and issue the address of the
will then connect to the new test station and its program
The long registers in the manual station will not be reset so the operator can analyze all
long register information at that point in the test program. When the manual station start
request is issued again, the test program will be executed automatically under computer
control up to the previous stopping point plus one more instruction. Again the TSC register'
will be scanned for start requests. Thus, in manual mode, one instruction is executed for
each start request. The manual station has no priority over any other station. If more than
one station is in manual, the operating system keeps track of the last statement executed by
each station when it becomes interrupted.
A station that is in manual mode and part way through a test program, may change to
automatic mode at any time. When start request is issued, the remainder of that test program will be executed automatically.
1.6.3 Output Pin Loading
Output pins can be loaded by either of the following methods:
(a)
Connect a resistive load, RL in series with the functional test driver and
the device output pin (the functional test level detector is also connected to the device output pin to allow concurrent Go/No-Go testing).
The load current for Va H /Va L is provided by electronically switching
the driver reference between EAI and EAO according to the output bit
in the F register.
(b)
Connect a resistive load, RL to the device output pin in series with a
utility relay and one of the programmable power supplies. Load current
is then applied when the power supply is programmed to the appropriate voltage level.
1.6.4 Power Supply Decoupling
Device power supply pins can be decoupled by connecting a capacitor in series with a
utility relay. If it is necessary to perform a precision leakage test on the device supply pin,
1-16
the utility relay can be opened prior to connecting the precision measurement unit to the
device pin.
1.6.5 MOS Input Pin Stressing
Low energy pulses can be applied to MOS input pins by connecting the user supplied pulse
source to input pins via the utility relays. Control for the pulse source is derived from one
of the external registers. However, up to 80 volts differential may be obtained from the
Sentry 400 DPS supplies.
1.6.6 Input Bias Voltage
Unused power supplies can be connected to device input pins via utility relays to provide
bias voltage.
1.7 PROGRAMMING CHARACTERISTICS
The format of the test program language, FACTOR, is reasonably simple to learn, apply and
interpret as to its meaning. In many respects the language is very similar to a high level
computer procedural language such as FORTRAN or ALGOL. The FACTOR language provides the following general features:
1.
Conditional and unconditional branching.
2.
Arithmetic and Boolean manipulations.
3.
Input/Output of data and control.
4.
Variable references.
5.
Statement labels.
6.
Procedure and functional calls.
7.
Tester statements.
Following are some typical programming statements. These demonstrate some of the
features described above.
LABI:
ON FCT, ABORT;
ON DCT, ABORT;
ENABLE DCTI GT 2E-6 AMPS;
ENABLE DCTO LT-2E-3 AMPS;
SET PMU SENSE, AUTO;
LAB2:
SET PMU FORCEV, RNG2; N = 3;
1-17
DCTEST:
FTEST:
FORCE PMU 3 VOLTS; CPMU PIN N;
MEASURE VALUE; ILEAK = VALUE; FORCE PMU 0 VOLTS;
MEASURE VALUE; IFWD = VALUE;
N=N-l;
IF N NEQ 0 THEN GO TO DCTEST;
CALL FUNCT;
Labels are terminated with colons (:)* and statements are terminated with semi-colons (;).
The statements between the labels LAB 1 and LAB2 are interpreted as follows: '
1. .
If functional or DC test failure is detected, transfer program control to
the statement labeled ABORT.
2.
The ENABLE statements establish limits for all subsequent DC measurem ents resulting from the statement MEASURE. If the measured
parameter is greater than 2 microamps or less than -2 milliamps the
tester will return DC fail status and transfer control to the statement
labeled ABORT.
3.
The measuring unit is preset to perform auto-ranging in order to obtain
the best resolution, and the forcing function is preset to force a voltage
in the range 0 to 10 volts.
The statements between labels LAB2 and FTEST form a loop that executes two DC parameter tests on pins 3, 2, and 1 respectively.
If all three DC tests "pass," the next statement to be executed is a call to execute a
procedure which might be a sequence of functional tests.
1.8 PHYSICAL DESCRIPTION AND SPECIFICATIONS
This section describes the main frame, test stations, and FST-l computer with the various
options available. Also included is a brief description of the software, general and electrical
specifications and physical dimensions. Figure 1-8 is a system configuration illustration
showing the model numbers of the various components and options within the system that
are described in the following paragraphs.
*Colons are represented by the 0-8-2 code on punch cards which is the "NUMERIC T" on the
IBM 29 punch - not the key labeled :
1-18
Section I
Sentry 400
2101/8201
FST·1
DIGITAL
COMPUTER
2130
8000
SENTRY 400
MAIN
FRAME
8014/81115
8103/6/9/12
TEST
STATION
8103/6/9/12
TEST
STATION
2086
CARD
READER
8103/6/9/12
TEST
STATION
8103/6/9/12
TEST
STATION
SYSTEM CONFIGURATION
Figure 1-8. System Configuration and Model Numbers
1.8.1 Mainframe and Options
MODEL 8000 SENTRY 400 MAINFRAME, including:
I)
Single bay enclosure.
2)
AC Power distribution assembly,
3)
Monitor control panel.
4)
Reference unit power system.
5)
Reference and multiplex chassis, including:
-Control logic for Model 8014's and 8015's.
-Multiplex control unit.
6)
Interfacing to Model 2101 computer.
1-19
MODEL 8014 DUAL REFERENCE SUPPLY. Digitally programmed to provide" logical "0"
and "1" voltage levels used as references by function drivers and comparators. Three Model
8014 units are required in a basic system to provide two pairs of input reference levels, and
a pair of "expected" output comparator levels. Up to two additional 8014's may be used to
provide bias levels connected to any device terminal through the Model 8020 load boards,
under program control.
MODEL 8015 POWER SUPPLY.
used to provide Vcc, VDD, etc.
Digitally programmed voltage/current source, normally
Programmable voltage or current trip circuitry is included to interrupt system if actual value
exceeds programmed trip limit.
Two Model 8015 supplies are recommended in a basic system while one additional unit may
be fitted optionally.
MODEL 8020 UNIVERSAL LOAD BOARD. The Model 8020 Universal Load Board as
available for the SENTRY 400 system may serve in the following applications:
1)
DUT has open collector outputs requiring external pullup resistors.
2)
Functional tests are performed with output pins under load.
3)
User requires special circuitry to be used under system program control.
Five load boards per each 30 pin module are included in the test stations.
The load boards have patch plugs and receptacles for solderless connection of components.
There are also fifteen address lines for the user to tie to ground or +5 volts to form a board
identification code. Thus, the test program can test to see if the correct load boards are
inserted.
1. 9 TEST STATION
1.9.1 Model 8103, 30-Pin Test Station, including:
1-20
1)
Standard test station enclosure.
2)
Power control module (including isolation filtering and fail monitor).
3)
Power supply module.
4)
Precision measurement unit.
5)
One, 30-pin module of drivers and detectors, including control logic.
6)
Station control panel.
7)
Five each Model 8020 boards.
1.9.2 Model 8106, 60-Pin Test Station, including:
1)
Standard test station enclosure.
2)
Power control module (including isolation, filtering and fail monitor).
3)
Power supply module.
4)
Precision measurement unit.
5)
Two 30-pin modules of drivers and detectors, including control logic.
6)
Station control panel.
7)
Ten each Model 8020 load boards.
1.9.3 Model 8109, 90-Pin Test Station, including:
1)
Standard test station enclosure.
2)
Power control module (including isolation filtering and fail monitor).
3)
Power supply module.
4)
Precision measurement unit.
5)
Three 30-pin modules of drivers and detectors, including control logic.
6)
Station control panel.
7)
Fifteen each Model 8020 load boards.
1.9.4 Model 8112, 120-Pin Test Station, including:
1)
Standard test station enclosure.
2)
Power control module (including isolation filtering and fail monitor).
3)
Power supply module.
4)
Precision measurement unit.
5)
Four 30-pin modules of drivers and detectors, including control logic.
1-21
6)
Station control panel.
7)
Twenty each Model 8020 load boards.
1.10 COMPUTER AND PERIPHERALS
1.10.1 Model 2101 FST-l Computer, including:
1)
Single bay enclosure.
2)
CPU logic and power system.
3)
4096 Word (24-bit) core memory.
4)
Memory expandable by addition of Model 2130.
5)
Computer control panel.
6)
24-bit word length.
7)
Full memory cycle time of 1.75 microseconds.
8)
Multi-level indirect addressing.
9)
Seven hardware index registers.
10)
Hardware multiply/divide.
11)
Two memory buses provide simultaneous access to two memory banks,
via separate DMA channels. Memory data transfer rates in excess of 1
mega-word per second.
1.10.2 Model 2060 Disc File
The disc file is used as a multi-purpose message storage device within the Sentry 400
system. Some of its major applications are:
1)
System software storage.
2)
Test program storage.
3)
Temporary working storage.
4)
Data buffer for I/O.
Performance characteristics:
1)
'-22
Rotation speed: 1745 RPM
2)
Access time: 17.8 milliseconds average, 35.5 milliseconds maximum.
3)
Data transfer rate: 113,000 words/second.
4)
Storage capacity: 768,000 words (24 bit).
The model 2060 includes the controller and interface to the FST-l computer.
1.10.3 Model 2070 Magnetic Tape Controller
Designed to interface and control up to three Model 2071 magnetic tape transports.
1.10.4 Model 2071 Magnetic Tape Transport
The digital tape memory system is used for a number of applications within the Sentry 400
system. Among these are:
1)
Datalogging for subsequent data analysis by FST-l or off-line computer
installation.
2)
Large test program library storage.
3)
System software storage as back-up for disc file.
4)
Data transfer media in multiple system installations, etc.
Performance Characteristics:
1)
Tape speed: 24 inches per second.
2)
Tape: lh inch width, 1.5 mil by 2400 feet.
3)
Reels: 10lhinch IBM or NAB type.
4)
Recording density: 800 BPI.
5)
Recording format:
compatible ).
6)
Rewind and fast forward speed: 150 IPS.
9-track ASCII, 0.6 inch IRG (IBM 360-2400 series
1.10.5 Model 2121 FST-l Software Package
The FST-l computer software package includes the following major components:
ASSEMBLER-Accepts computer programs written in FST-l assembly language
and assembles them into executable object code.
1-23
DEBUG-Provides full computer program debugging capabilities.
DOPSY -(Disc OPerating SYstem)
Nonreal time, batch operating disc system. Provides job control, loading, coreallocation and input/output services.
DIAGNOSTICS-Extensive diagnostic package includes programs for automatic
checkout of test system electronics, Sentry mainframe electronics, as well as
diagnostics for the FST-l computer instruction set, core memory and peripheral
equipment.
1.10.6 Model 2084 Console Typewriter With Paper Tape
The Model 2084 unit consists of a modified ASR-33 Teletypewriter with attached mechanical paper tape reader and punch and interface electronics to the FST-l computer.
1.10.7 Model 2085 Console Typewriter With Paper Tape
Sanle as Model 2084 except utilizing heavy duty ASR-35 Teletypewriter.
1.10.8 Model 2087 Console Typewriter
Same as Model 2085 except utilizing KSR-35 Teletypewriter, without paper tape facilities.
1.10.9 Model 2086 Punched Card Reader
The Model 2086 card reader photoelectrically reads standard 80 column punched cards
at a rate of up to 200 cards per minute.
1.10.10 Model 2110 Extension Bay
Used to house up to two Model 2071 magnetic tape transports.
1.10.11 Model 2130 Core Memory Expansion
4096 Word (24-bit) module with memory parity.
1-24
1.11 SYSTEMS SOFTWARE
1.11.1 Model 8201 Sentry 400 Software Package
The Sentry software package consists of two major components.
These are:
FACTOR-(Fairchild Algorithmic Compiler, Tester Oriented). Allows test programs to be written in a simple, easy to learn "English" like algorithmic language.
Generates object code for interpretation and execution by TOPSY. Includes
extensive error checking facilities.
TOPSY -(Tester OPerating SYstem). TOPSY is a real time operating system
designed to operate the Sentry 400 in its normal mode, testing on-line. The many
functions performed and supervised by TOPSY include:
System initialization
Multiplexing
Interrupt Processing
Fetching test instructions
Instruction interpretation
Performance of FACTOR arithmetic operations
Measurement limit comparison
Work stack manipulations
On-line user command processing
Datalogging of test data to selected I/O units.
DIAGNOSTICSTDIAG
MDEBUG
VCTST
PMUCAL
A/D
ADCON
DPS
1-25
Table 1-1.
Electrical Specification Summary
Programmable
Unit
Max.
No.
Maximum
Range
Functional
Test
Driver
120*
±30.72V at ±40mA
10m V /40m V
in 2 ranges
Current limits at 50mA, short circuit
protected, maximum slew rate
30V/J.1s.
Functional
Test
Comparator
120*
±30.72V: 2.5Mn
10mV/40mV
in 2 ranges
Detects open circuit lines, monitors
inputs and outputs 0.4J.1 s, response
time for 10mV overdrive at -30 to
+30V.
Resolution **
Special Features
Precision
Measu rement
Unit
1*
±40.92V; ±102.3mA
1mV/40mV
in 3 ranges
1nA/100J.1A
in 4 ranges
Voltage or current force and sense,
programmable current and voltage
limit, 1OOJ.1S A/D converter (11 Bits).
Programmable
Power
Supply
3
±40.92V; ±1.023A
10mV/40mV
in 2 ranges
0.1mA/1mA
in 2 ranges
Voltage or current force and sense,
Go/No-Go trip output for over or
under current or voltage,
current/voltage magnitude
measurement 1 ms setting time to
1% of full scale.
Programmable
Reference
10
±30.72V at ±40mA
10m V / 40m V
in 2 ranges
Four references for functional test
drivers, two for functional test
comparators, four for low current
bias supplies, 5 ms settling time to
0.1% of full scale.
Time Delay
5.73405s
0.35J.1/0.35ms
in 2 ranges
Clock-Burst
Generator
255 sync pulses
1 sync pulse
Sync Output
4
T2 L Driver 0 to 5V
Socket
Identification
* I n one standard test station enclosure, software is configured for up to 240 pins. Two
120 pin test station enclosures are used for a 240 pin tester configuration.
** Accuracy: All forcing and measuring units are accurate to ±1 least significant bit
±0.1 % of the value except the PMU 1 microampere and 1 volt ranges which are ±2
LSB and ±0.5%.
1-26
Table 1-2. General Specifications
I nput Power Requirements
Mainframe
Computer
Test Station
Two five wire three phase inputs at 208V /30A each if the
installation consists of more than one test station. For
installations with one test station only, one five wire three
phase input is required.
110Vac at 9A on Phase A
110Vac at 20A on Phase B
11 OVac at 20A on Phase C
Environmental Requirements
+15°C to +30°C, specifications apply at 25°C ±2°C and 50%
maximum relative humidity.
Size
Height
Width
Depth
66.75"
66.75"
48"
42.5"
38"
37.5"
Mainframe and Computer
Test Station
Weight
Mainframe and Computer
Test Station (each)
,,-,900Ibs.
varies
Memory Capacity
Up to four memory banks consisting of 4096, 24 bit words
each.
Type of Tests
Two types of tests. (1) Functional tests, that determine
whether the device performs the intended logic operations;
(2) DC tests that determine whether component parameters meet device specifications.
TEST Rate
Maximum 286,000 functional tests per second and 250 DC
tests per pin per second. Maximum number of tests that
can be performed on a single device is approximately
130,000 without programmed loops.
TEST STATIONS
Four stations may be multiplexed into the system and controlled by one FST-1 computer. Different device types may
be tested at each station in any given mode of operation
without affecting testing at other stations.
Tester Pin Capability
Pin capability is expandable in groups of 30 up to a maximum of 120 pins per test station. Two 120 pin test
enclosures are used for a 240 pin configuration.
Programming Language
FA C TOR. ( Fa i r chi I d A I g 0 r i t h m ice 0 mpile r Tester
ORiented) language. The language is very similar to FORTRAN and ALGOL-60.
Modes of Operation
( 1) Automatic
I n the automatic mode a complete device program will be
performed once the start button is depressed. I n the
1-27
Table 1-2. General Specifications (Continued)
production environment the start pulse is provided by the
mechanical handler and the complete program is performed
automatically on each device.
1-28
(2) Manual
I n the manual mode the system will perform a single test
of a program each time the start button is depressed.
(3) Monitor
I n the monitor mode the operator may intervene with the
programmed test and manually modify programmed
voltages, test rates, test times, etc. as desired. This mode is
ideal for debugging prototype arrays. While in the Monitor
mode testing continues uninterrupted at other stations
(regardless of mode). The only limitation is that while in
the monitor mode data logging on teletype is inhibited.
Software
The system is supplied with a complete software package.
Device test programs may be prepared by the user, or, if
desired, by Fairchild.
Ma i ntenance
The system-is provided with maintenance routines to help
in fault isolation. The hardware has built in self-test
capability.
Section II
Installation
2.1 GENERAL
It is Fairchild policy to provide a technical representative to supervise the installation of all
Fairchild System Technology products. The following instructions apply to deliveries and
installation made under this condition.
2.2 INSPECTION
It is the responsibility of the customer to inspect the crated system before releasing the
shipper. Any signs of external damage must be noted by both and called to the attention of
the insurance investigator.
2.3 UNCRATING
The customer must not uncrate the system without verbal or written consent from a
Fairchild representative. Any external damage discovered during uncrating will be noted and
uncrating stopped until the insurance investigator is notified. Do not proceed until so
instructed by the insurance investigator. After uncrating, the customer will make a careful
inspection to ensure that there is no concealed physical damage to internal electronic circuits or components.
2.4 INSTALLATION
Installation will be made by the customer's staff under direct supervision of a Fairchild
representative.
CAUTION
INITIAL POWER MUST NOT BE
APPLIED TO THE EQUIPMENT
WITHOUT WRITTEN PERMISSION
FROM FAIRCHILD.
2.5 RESHIPMENT
When a chassis is damaged in shipping, the insurance investigator can order it returned. The
insurance company will assume full responsibility for recrating and reshipment. Neither the
customer nor Fairchild are required to assume such responsibility without specific understanding with the insurance company through the proper representative.
2-1
When a physically undamaged, unoperational chassis is to be returned, an agreement will be
made between Fairchild and the customer as to procedure.
2.6 LAYOUT
Two suggested layouts of the Sentry 400 Test System are illustrated in Figures 2-1 and 2-2.
Installation should be such that a 4 foot clearance (minimum) exists at the rear and sides of
the bays.
2.7 INTERCONNECTING CABLES
Figure 2-3 is a cabling diagram showing the interconnecting cables for the Sentry 400 Test
System and Figure 2-4 shows the interconnecting diagram for the FST-I computer and
peripheral equipment. Caution should be exercised when handling the cables to prevent
broken wires, pins and sockets. Test station main frame multiplex and power cable length
should be specified and can be up to 50' long allowing a 40' separation between main frame
and test station.
2.B AC POWER
AC power for the system is provided by two five wire 20BV /30A three phase inputs. The
three phase inputs are connected to J 1 and J2 on the rear of the power distribution panel.
The three phase input connected to J 1 provides power for the main frame (including the
FST-I computer) and test station No. 1. The three phase input connected to J2 provides
power for test stations 2, 3 and 4. If the system consists of more than one station both
three phase inputs are required. If the sys!tjm consists of one station input power to J 1
only is required.
A. C. ,-'""-.., .(;.., 'tfI.'t.. J)\,c.. ... '''?\ItVO$ 2.0'".
Sl~SJ.. , ......... "$ ..... "....
o:f.s- ~ptr~s·
2.9 AIR CONDITIONING AND HUMIDITY REQUIREMENTS
Environmental requirements are as specified in Table 1-2. General specification: normal room
ambient (25°C) at less than 50% relative humidity are ideal conditions. One mainframe and a
single test station produces approximately 450 BTU's per minute. Each additional test station
produces approximately 170 BTU's per minute. Air conditioning requirements of existing
facilities should be modified as required to compensate.
2-2
Sentry 400
Section II
4'0"
DISC
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Figure 2-1 Sentry 400 Test System Suggested Layout ... A
2-3
Section II
Sentry 400
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NOTES:
1)
2)
3)
Cable lengths 20 feet approx. (40' to test station max)
Allow 4 foot clearance at side and rear
of each main unit for access.
Dimensions are approximately 3 inches
oversize.
Figure 2-2 Sentry 400 Test System Suggested Layout ... B
2-4
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Sentry 400
Section II
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2-5/2-6
Section II
Sentry 400
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Figure 2-4. Interconnecting Cabling FST-1 Computer and Peripherals
2-7/2-8
Sentry 400
Section III
Section III
Operation
3.1 INTRODUCTION
This section provides the operator with all necessary information to operate the Sentry 400
Test System in any testing environment, i.e., production testing, engineering development,
or test engineering. Included is a description of the control and indicators for the FST-l
computer, test console, teletype and disc memory, as well as all optional peripherals available at this time. Also included are instructions for turning system power on and off, and
loading CPU executive routines, utility routines, FACTOR, the Sentry 400 Tester OPerating
SYstem Program (TOPSY), and device test programs.
3.2 CONTROLS AND INDICATORS
Keys and switches on the CPU Front Panel provide manual control of the FST-l computer
portion of the test system. The contents of various registers may be displayed visually on
indicator lamps. The lamps light to denote the presence of a binary "1" in specific register
bits as well as control and program switch flip-flops.
Switches and pushbuttons on the test station console allow the operator to manually control the mode of operation of the test system. In addition, the Front Panel indicators and
displays inform the operator of test information such as DC and functional test pass or test
fail, function test logical inputs and expected outputs, Go/No-Go results for each output
pin during function testing, etc.
The Monitor Panel controls permit the operator to intervene, and manually vary the output
voltages of various system reference power supplies. The reference supply outputs can also
be monitored by a digital voltmeter. The MONITOR switch enables the Teletype key board
for TOPSY command entries.
The ASR-33 Teletype is the primary input/output device for the system; optional input/
output devices that can be redefined by the operator as the respective primary device
include the Card Reader, Line Printer and Mag Tape.
The functions and location of the controls and indicators for the FST-l Computer Test
Console, Teletype, Disc Memory, Card Reader, and Line Printer are found in Tables 3-1
through 3-9 and Figures 3-1 through 3-10.
3-1
Sentry 400
Section III
Table 3-1. FST-1 CPU Controls and Indicators
3-2
Panel Lock
Switch
When in the counterclockwise position, this key-operated
switch disables most CPU switches. (Switches not disabled
are START, STOP, RESET, LOAD MT, LOAD CDR, and
Console Sense Switches 1 through 6.) In the disable condition, inadvertent switch operation cannot disturb the
program. The program can, however, read the contents of
the switch register by execution of the RSR instruction.
START
Pushbutton/
Indicator
Pressing this pushbutton switch illuminates the START
indicator and causes the CPU to start executing program
instructions, beginning with the instruction currently held
in the command register. While the START indicator is lit,
all CPU control switches are disabled except STOP, SIC,
and SMC.
STOP
Pushbutton/
Indicator
Pressing this pushbutton switch halts the program processing at the termination of the instruction currently being
executed, turns off the START indicator, and turns on the
STOP indicator. While the STOP indicator is lit, all console
control switches are enabled if the SIC Switch is up.
SIC
Switch
When in the up (ON) position, this switch halts the CPU at
the end of the last memory cycle of the program instruction being executed: repreated depression of the START
switch steps the program one instruction at a time. This
switch is off in the down position.
SMC
Switch
When in the up (ON) position, this switch halts the CPU at
the end of one memory cycle-of-operation: repeated depression of the START switch steps the program one
memory cycle at a time so the contents of the· various
register displays and indicators may be examined. This
switch is off in the down position.
RESET
Pushbutton
Pressing this switch resets the control flip-flop and initializes the program counter to 00100 8 ,
Switch Register
Switches
These switches provide a means of manually setting up a
24-bit word, where a switch in the up position represents a
binary 111" and down is a 110." The contents of the Switch
Register are loaded into the program counter by the LOP
switch, into the command register by the LDCR switch,
into the A-register by the LOA switch, or by executing an
RSR instruction.
Sentry 400
Section III
Table 3-1. FST-1 CPU Controls and Indicators (Continued)
lOAD CDR
Pushbutton
Pressing this switch causes the card reader to read a single
card: the binary data on the card is loaded into 40 consecutive core memory locations beginning with address
00100 8 , This switch is primarily used to read the first card
of the six-card Card Object loader (COL) program or the
two-card Disc Bootstrap Program.
lOAD MT
Pushbutton
Pressing this pushbutton switch causes the Magnetic Tape
OOPSY System Bootstrap program to be read from magnetic tape and to be stored into 40 consecutive core-memory
locations beginning with address 00100 8 , With the Magnetic
Tape DOPSY System Bootstrap Program resident in core
memory, program control is transferred to the DOPSY
monitor, by loading the instruction BRU 100 (01000100 8 )
into the command register and then pressing the START
pushbutton.
lOA
Switch
Lifting this spring-loaded switch causes the contents of the
switch register to be loaded into the A-register. SI C must
be on to enable this function.
lOP
Switch
Lifting this spring-loaded switch loads the contents of the
switch register into the program counter. SI C must be on to
enable this function.
lDC
Switch
Lifting this spring-loaded switch loads the contents of the
switch register into the command register. SIC must be on to
enable this function.
ClK
Switch
The clock two-position switch is off in the down position.
When in the up (ON) position, it prevents the content of
the command register from being changed after the instruction in that register has been executed; it also causes the
contents of program counter bits 0 thru 11 and command
register bits 12 and 13 to be used as the effective operand
address instead of the actual operand address specified by
the instruction in the command register. Each time the
instruction is executed the content of the program counter
is incremented by one, thereby modifying the effective
operand address.
This switch, when used with the SIC and START switches,
affords an alternate means to load manually or to examine
consecutive core-memory locations, one at a time, with
either the STA or lDA. instruction, respectively, in the
command register. It may be used also to clear core
memory by loading a STA instruction in the command
register, zero in the A-register, and then pressing START.
3-3
Sentry 400
Section III
Table 3-1. FST-1 CPU Controls and Indicators (Continued)
3-4
STW
Switch
Lifting this spring-loaded switch stores the contents of the
switch register in the buffer register and the core-memory
location specified by the current content of the program
counter. When the store operation is completed, the program counter is then incremented by one. Thus, information in sequential memory addresses may be stored by
repeated operation of the STW switch.
EXM
Switch
Lifting this spring-loaded switch loads the contents of the
core-memory location specified by the current contents of
the program counter into the buffer register for visual
examination by the operator. When the examine operation
is completed, the program counter is incremented by one.
Thus, the contents of sequential core memory addresses
may be examined by repeated depression of the EXM
switch.
P COUNT
Indicators
Indicates the content of the 14-bit program counter. In the
STOP state, the program counter holds the core memory
address of the next instruction word that will be loaded
into the command register, if the current instruction is not
a branch instruction.
Register Display
Indicators
Indicates the contents of the 24-bit register selected by the
appropriate register-display-select push buttons.
Register-D isplay-Select
Pushbuttons
Each of the 12 pushbuttons, when pressed, cancels the
previously pressed pushbutton and causes the contents of
its associated register to be displayed by the register-display
indicators. The function of each of the selectable register
displays is as follows:
A-Register
Display
Indicates the content of the 24-bit accumulator regis- .
ter. The accumulator is the main arithmetic register
for such operations as ADD, SUB, MUL, and DIV
occur, as well as the logical operations of AND and
OR. It also serves as the input/output register for the
transfer of data under program control.
E-Register
Display
I ndicates the content of the 24-bit extension register.
This register is an extension of the accumulator registe ran d is used with double-precision arithmetic
instructions such as DADD, DSUB, MUL, and DIV.
C Register
Display
I ndicates the content of the 24-bit command register.
I n the idle state, the command register stores the next
instruction word.
Sentry 400
Section III
Table 3-1. FST-1 CPU Controls and Indicators (Continued)
I ndicates the content of the 24-bit buffer register. All
information written into or read out of core memory
from the CPU during the execute phase is temporarily
held in the buffer register. This information can thus
be monitored by the operator using the STW and
EXM switches while the SIC (single instruction cycle)
or the SMC (single memory cycle) switch is on.
B-Register
Display
I
Xo thru X 7 Register
Display
I ndicates the contents of the selected 14-bit index
register.
Console Sense
Switches
The six console sense switches manually control the execution sequence of any program that contains appropriate
BOS instructions. A switch in the up position represents a
binary "1," and down represents a binary "0." The state of
each switch may be individually tested with a BOS
instruction.
Program-SenseSwitch Indicators
Each of the eight lamps indicates the state of its corresponding program-sense-switch flip-flop. The state of a
program-sense-switch flip-flop may be used to automatically
control the execution sequence of any program that contains appropriate BOS instructions. An illuminated lamp
indicates its corresponding program-sense-switch fl ip-flop
has been set to the "1" state by a SST instruction. Each
flip-flop can be reset to the liD" state, turning its lamp off,
with a RST instruction. The state of each program-senseswitch flip-flop may be individually tested with a BOS
instruction.
Peripheral-Status
Indicators
Each of the nine lamps, when lit, indicates a particular
status condition of its associated peripheral device. The
definition of each indicator mnemonic follows:
Definition
Mnemonic
PEA
PEB
MBA
MBB
DER
DBU
MER
MTB
INP
Memory "A" parity error
Memory liB" parity error
A" memory is busy
liB" memory is busy
Disc parity error
Disc is busy
Magnetic tape error
Magnetic tape is busy
I nput pending
II
PEA
Th is indicator will be illuminated when an "A"
memory parity error is detected, if the system is
equipped with that option.
PEB
Performs same function for liB"
indicator.
memory as PEA
3-5
Sentry 400
Section III
Table 3-1. FST-1 CPU Controls and Indicators (Continued)
MBA
When illuminated, indicates that the "A" memory is
being accessed.
MBB
Performs same function for "B" memory as "A"
indicator.
DEH
When illuminated, indicates that a disc parity-check
error has been detected.
DBU
The disc busy flip-flop is set, lighting the DBU indicator,
when the disc is performing an operation such as read,
write, or parity check. The flip-flop is reset, turning the
indicator off, when the operation is completed.
MER
Magnetic tape parity error
MTB
Magnetic tape is busy.
INP
The input-pending flip-flop is set, lighting the I NP
indicator, by an ION instruction. This indicator is a
visual indication only to the operator that the program
is expecting data from an input device. The flip-flop is
reset, tu-rning the indicator off, by an IOFF instruction or by depressing the RESET switch. The state of
the flip-flop cannot be tested; hence, it cannot control
the program-execution sequence.
Status Register
Flip-Flop Indicators
Each of the six lamps indicates the state of its associated
status-register flip-flop. The mnemonic definition of each
indicator follows:
Mnemonic
Definition
GT
EQ
LT
BE
OV
SN
Greater than
Equal
Less than
Bit equal
Overflow
Sign
The indicators GT, EQ, L T, BE, and OV are lighted (with
the associated flip-flop set) in various configurations after
executing one of the instructions CAM, ATX, SPU, or
BRU* (BRU with indirect bit set). The indicators affected
by each instruction are shown below; refer to the detailed
description of each instruction to interpret the meaning of
each indicator for that specific condition.
3-6
Sentry 400
Section III
Table 3-1. FST-1 CPU Controls and Indicators (Continued)
I nstruction
CAM
ATX
SPU
BRU*
Used
GT,
GT,
GT,
GT,
EO,
EO,
EO,
EO,
LT,BE
L T, (ignore BE state)
LT,BE
LT, BE, OV.
OV
Indicator
The overflow flip-flop will be set and the OV indicator lighted, in addition to a BRU* instruction, by one
of the following conditions: If the accumulator overflows as the result of executing an ADD, SUB, DADO,
DSUB, or DTC instruction; by executing the appropriate SST instruction. The overflow flip-flop can be
reset, turning off the OV indicator by executing the
appropriate RST instruction.
SN
Indicator
The SN indicator indicates the sign of the number left in
the accumulator. Under these conditions, the SN indicator is interpreted as follows:
Condition
OFF
ON
Control Flip-Flop
Indicator
Interpretation
Number in AC is positive
Number in AC is negative
Each of the four lamps indicates the state of the corresponding control flip-flop. The definitions of indicator
mnemonics follow:
Mnemonic
IER
lEN
TIF
TOF
Definition
I nstruction Error
I nterrupt Enable
Time of I nstruction Fetch
Time of Operand Fetch
IER
The IE R (I nstruction Error) flip-flop is set, "illuminating
the IE R indicator, as the command register is loaded,
either from core memory or the switch register, with an
instruction containing an op code between 418 and 77 8 ,
inclusive.
lEN
The interrupt-enable flip-flop is set and the I EN
indicator lighted as the result of executing an I EN
instruction. The flip-flop may be reset, turning off the
indicator, by executing an IDA instruction, by
executing a priority interrupt, or by pressing the
RESET pushbutton.
TIF
When executing any instruction, the TI F (time-ofinstruction-fetch) flip-flop will be set, illuminating the
TI F indicator, while the CPU is in the instructionfetch cycle.
3-7
Sentry 400
Section III
Table 3-1. FST-1 CPU Controls and Indicators (Continued)
During the instruction-fetch cycle, the contents of the
program counter are transferred to core memory and
decoded. At the T1 phase of the instruction-fetch
cycle, the contents of the decoded memory address
are gated into the command register, and the program
counter is incremented by one in readiness for the
next instruction-fetch cycle; the TI F flip-flop is reset
at the end of this T1 phase.
TOF
When executing any memory-reference instruction, the
TOF (time-of-operand-fetch) flip-flop is set, illuminating the TOF indicator, while the CPU is in the
operand-fetch cycle.
During the T1 phase of an operand-fetch cycle, the
contents of the instruction operand are gated into the
buffer register. If the instruction requires only one
operand, the TOF flip-flop is reset at the end of the
T1 phase of the operand-fetch cycle. If two operands
are required, TOF is reset at the end of the second
operand-fetch cycle.
3-8
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Section III
Sentry 400
Table 3-2. Sentry 400 Test Station Console, Controls and Indicators
POWER Key
Turning this key in the clockwise direction applies primary
AC power to the test console, DC power supplies, fans,
DVM's and core memories. Primary AC power is also
supplies to the system input/output peripherals but is controlled by "power on" switches or pushbuttons on the
respective units.
POWER RESET
Pushbutton.
Depressing this pushbutton applies power to the test station
console after the Power key has been rotated clockwise. The
mai nframe power must be on before power can be enabled
at the station.
Cycles on and off when a power failure occurs.
POWER FAIL
Indicator
REGISTER SELECTOR
Push buttons
3-10
These pushbuttons allow the operator to select two "Long
Registers" whose contents will be simultaneously displayed
by the REGISTER DISPLAY LAMPS. Each pushbutton
when pressed cancels the previously pressed pushbutton and
ca uses the contents of the associated register to be
displayed. I n the following description of each "Long
Register" a binary "1" is represented by a lighted lamp
while an unlighted lamp represents a binary "0":
F:
Function Register-represents the input forcing logic
for those pins programmed as "I nputs" and the
expected output response for those pins programmed
as "Outputs" in the D Register.
M:
Mask Register-controls the "care" or "don't care"
condition for each tester pin. A binary "0" or "don't
care" inhibits the comparison operation for that
particu lar pin, while a binary "1" or "care" enables
the comparison operations.
R:
Utility Relay Register-controls the utility relays, one
per tester pin. A binary 111" indicates a closed relay
and a binary "0" indicates an open relay. The utility
relays can be used for such functions as to connect a
load resistor for an output pin to a programmable
power supply.
S:
Se I ect R efe rence Register-selects which set of
reference supplies are to be used by the functional
test driver for each tester pin. A binary "0" selects
the EO/E 1 reference supplies while a binary "1"
selects the EAO/EA 1 reference supplies.
D:
I nput/Output Pin Definition Register-this register
defines each tester pin as an input pin or an output
pin. A binary "1" represents an input and a binary
"0" represents an output for its associated tester pin.
C)ectio'n III
Sentry 400
Table 3-2. Sentry 400 Test Station Console, Controls and Indicators (Continued)
C:
Register Display
Indicators
Comparison Register-this register stores the Go/NoGo results of a comparison between the actual
outputs of a device and the expected outputs. A
binary 111" represents a comparison failure and a
binary 110" represents a pass condition.
This display, consisting of two horizontal rows of lamps
numbered from 1 to 15, allows the operator to simultaneously examine the contents of one rank of two selected
Long Registers.
The bottom row, or row 2, can display the contents of the F,
M, or R Register; the top row, or row 1, can display the
contents of the S, D, or C Register.
RANK SELECTOR
Push buttons
There are 8 ranks to each register. The register to be displayed is selected by the REGISTER SELECTOR and the
rank of pins to be displayed, is selected by the RAN K
SE LECTOR. Since there are 8 ranks for each register, the
status of all 120 pins (8 x 15) can be displayed by the
appropriate combination of REG I STE R SE LECTO Rand
RANK SELECTOR. e.g., if it is necessary to display the
status of all 120 pins of the liS" register, the REG ISTE R
SE LECTO R liS" button is depressed. Each rank of 15 pins
may now be displayed by depressing in turn RAN K
SELECTOR buttons 1 thru 8.
RANK FAIL
INDICATOR
If a functional failure occurs at a pin, the RAN K FAI L
INDICATOR associated with the rank of pins to which the
failed pin belongs, will illuminate. To determine the failed
pin, the failed rank of pins may be selected by the RANK
SE LECTOR and displayed on the Register Display Indicators.
STATEMENT NUMBER
Display
This is a five-digit octal display of the test instruction number
from 00000 8 to 77777 8 , Each time a tester statement or
instruction is executed the statement number display is incremented by one. This display will read 00001 while an
automatic test is in progress and be updated with the last test
nu mber at pauses.
EXTERNAL REGISTER
Display
Provides a display of the ten least significant bits of the
external interface register.
LAMP TEST
Pushbutton
This pushbutton, when depressed, will cause all display panel
lights to light, if they and their associated drivers are
operational.
START
Pushbutton/I ndicator
This pushbutton, when depressed, produces a START pulse
that initiates active testing of the device-under-test.
3-11
ntry 400
Section III
Table 3-2. Sentry 400 Test Station Console, Controls and Indicators (Continued)
3-12
MANUAL
Pushbutton/I ndicator
When ON, one tester statement or instruction is executed
each time the START switch is depressed until all statements
have been executed. NOTE: If the MAN switch is not depressed and the system is not in MONITOR, the system is in
automatic mode.
ADV
Pushbutton/I ndicator
While depressed, and in the MANUAL test mode, this
momentary switch allows START pulses to be generated at a
repetition rate of'three per second. This allows the operator
to perform such operations as verification of the test program
currently stored in'core memory; this feature also allows the
operator to advance the test program to a specific function
test number of interest for the purpose of varying the programmed voltage parameters normally applied to the device
during that test while observing the results. The START
button should be depressed once before using ADV.
ON LINE
Indicator
I ndicates that particular station is on line to the system.
RESET
Pushbutton/I nd icator
This momentary switch, when depressed, resets all tester
displays and registers with the exception of the STOP
ENAB LE bit in the Status (STAT) Register. This operation
also sets the STOP bit in the STAT Register.
FUNCTION TEST
PASS/FAIL
Indicators
At the completion of a function test the appropriate indicator will light to signify the PASS or FAI L status of the device
for that test, or seq uence.
PARAMETER TEST
PASS/FAI L
Indicators
At the completion of a DC parameter test, the appropriate
indicator will light to signify the PASS or FAI L status of the
device for that test, or seq uence.
EOT
Indicator
The EOT indicator (End-of-Test) is illuminated after the last
statement of a test program has been executed.
EXTERNAL SYNC
Under program control a SYNC pulse will be available at
this jack. The pulse may be used to trigger an oscilloscope
or some other equipment defined by the user.
GROUND
System ground.
Section III
Sentry 40(l
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.3-13
Section III
Sentry 400
Table 3-3. Sentry 400 Monitor Control Panel Controls and Indicators
POWER/OFF/ON
Key
Turning this key to the ON position and pressing the
RESET button will apply primary power to the system.
All electronics in the main frame wi!! power up at this
time. Individual peripheral devicef,"Test stations, -QQ' I
lutel ."811 iriii must be turned on via their individual
power on switches.
RESET
Pushbutton
When the POWE R OF FION key is set to the ON position, pressing this pushbutton applies power to the
system as described above.
MUX INHIBIT
OFF/ON Key
Rotating this key switch clockwise gives complete control to station No.1. Stations No.'s 2, 3, and 4 are
inhibited from operation.
PROGRAM
Indicator
The program indicator indicates that all DPS's and
RVS's are under program control.
MANUAL
Indicators
When illuminated indicates that one or more of the
DPS's or RVS's is being manually overridden.
POWER
Indicator
When illuminated indicates primary power is on for the
main frame. If one of the supplies fail,the indicator will
flash and an audible alarm will be heard.
MANUAL ADJUST
POWE R SUPPLY
Push buttons
Depressing anyone of these buttons permits the station
selected to manually adjust the DPS's and RVS's via the
manual controls, if that station is on line. Depressing the
RELEASE pushbutton returns the selected station to
program control. Only one station at a time may be
s~lected for manual operation.
STATIONS-'
-2
-3
-4
RELEASE
3-14
HI LO GUARD
Jacks
Allows the user to connect any external voltage for display on the DVM, when the EXT pushbutton is
depressed.
MON
Pushbutton/I ndicator
When TOPSY is resident in core memory and the MON
pushbutton is depressed, the user can enter TOPSY
commands via the primary input device (usually TTY).
The TTY is disabled for datalogging.
STROBE
Pushbutton/I ndicator
When the STROBE pushbutton is depressed and the test
station is in the MANUAL mode of operation, the function test comparators will be repetitively strobed at
approximately 1.5MHz. This allows the user to vary programmed DPS or RVS voltages to assist in determining
device pass/fail threshold values.
Section III
Sentry 400
Table 3-3. Sentry 400 Monitor Control Panel Controls and Indicators (Continued)
SYNC
Pushbutton/I ndicator
When the SYNC pushbutton is depressed and th';1
system is in MANUAL mode of operation, SYNC signals
will occur repetitively at a rate con trolled by the TD.I
(Time Delay) register.
~
Digital Voltmeter
Display
The Nixie light display provides a five-digit plus sign
display of all monitored voltages. If the AUTO RANGE
button is depressed, automatic ranging of the decimal
point occurs. If the REMOTE pushbutton is selected the
decimal point is located according to the 1, 10, 100,
1000, 10000, range selector pushbuttons. The DVM can
also measure resistance at the external jacks with the
kilolm button and EXT depressed.
EXT
Pushbutton
Depressing this pushbutton will permit any voltage connected to the HI LO GUARD terminals to be displayed
on the DVM.
PMU
Pushbutton
Depressing this pushbutton will permit any voltage
being monitored by the precision measurement unit
(PMU) to be displayed on the DVM.
DPT1,DPT2,DPT3
Depressing the appropriate pushbutton will display a
voltage proportional to the current the DPS 1, DPS2 or
DPS3 are supplying. Scale factors are 100 microamps
per millivolt if the DPS is in the 100mA current range
and 1 milliamp per millivolt on the 1 ampere range.
DPS1
Pushbutton
Depressing. this pushbutton permits the programmed
DPS 1 supply voltage to be displayed on the DVM. I f the
DPS1 polarity switch (+ OFF -) is set to the + or position, the DVM will display the manually adjusted
DPS 1 supply voltage.
DPS1
Fine Adjustment
Coarse Adjustment + OF F
- (polarity switch)
The DPS1 coarse and fine adjustments permit manual
variation of the DPS 1 supply voltage, (Manual over-ride
of programmed voltage), when the polarity switch (+
OFF -) is set to + or -. A three digit counter connected
to the COARSE ADJUST knob displays the approximate value of the voltage selected by the coarse adjustment control. The coarse adj ustment may be varied to a
maximum 9.99 volts as displayed on the digital counter.
If a back lighted 10V x 4 appears directly above the
three digit counter, the three digit readout must be
multiplied by 4 to obtain the true output value. The
manually adjusted voltage may be displayed on the
DVM by depressing the DPS 1 pushbutton.
DPS2, DPS3,SO,S1, EO, E1
EAO,EA1, EBO, EB1, ECO, EC1
Same functions and operation as DPS1.
3-15
Figure 3-3. Sentry 400 Monitor Station Control Panel
Section III
Sentry 400
Table 3-4. FST-1 2084 Teletype Model ASR-33 Controls and Indicators
Unit
Teletype
Control
LINE/OFF/LOCAL
Switch
Descri ption
Controls application of primary power in
the Teletype and controls data connection
to the CPU. I n the LI N E position the
Teletype is energized and connected as an
I/O device of the computer. In the OFF
position the Teletype is de-energized, i.e.,
primary power is removed.
I n the LOCA L position the Teletype is
energized for off-line operation, and signal
connections to the CPU are broken.
Paper Tape Punch
Keyboard
REL
Pushbutton
Disengages the tape in the punch to allow
tape removal or tape loading.
B. SP. Pushbutton
Backspaces the tape in the punch by one
space, allowing manual correction or rub
out of the character just punched.
ON Pushbutton
Turns TAPE PUNCH on for simultaneous
operation with Teletype keyboard/printer.
OFF Pushbutton
Turns TAPE PUNCH off.
START/STOP/FREE
Switch
Controls use of the tape reader with
operation of the Teletype. I n the lower
FREE position the reader is disengaged
and can be loaded or unloaded. I n the
center STOP position the reader mechanism is engaged but de-energized. I n the
upper START position the reader is
engaged and operated under program
control.
Provides a means of printing on paper
when used as a typewriter and punching
tape when the punch ON pushbutton is
depressed; also provides a means of
supplying input data to the computer
when the LINE/OFF/LOCAL switch is in
the LI N E position.
3-17
Sentry 400
Section III
Figure 3-4. Teletype Model ASR-33
3-18
Sentry 400
Section III
Table 3-5. FST-1 2085 Teletype Model ASR-35 Controls and 'Indicators
Unit
Teletype
Control
LINE/OFF/LOCAL
Switch
Description
Controls application of primary power in
the Teletype and controls data connection
to the CPU. In the LINE position the
Teletype is energized and connected as an
I/O device of the computer. In the OFF
position the Teletype is de-energized, i.e.,
primary power is removed.
I n the LOCA L position the Teletype is
energized for off-line operation, and signal
connections to the CPU are broken.
Break
Pushbutton/
Indicator
This pushbutton/indicator is illuminated if
keyboard or tape reader transmission is
broken, either by internal means (refer to
Teletype manual for theory of operation)
or by pressing the pushbutton. Transmission can be restored by pressing the B R K
R LS key on the keyboard.
Rotary Mode Switch
This 5-position rotary switch, located to
the left of the Teletype keyboard, is used
to select the mode of operation when in
LOCAL or ON LINE. The positions are as
follows:
K
KT
T
TTS
TTR
keyboard
keyboard tape
tape
tape-tape send
tape-tape receive
Of the five, only the K, KT, and T positions are used when the AS R-35 is used
with the Sentry 400 Test System. These
positions are defined as follows:
K
All information, received or typed
will be printed.
KT
A printed copy and punched tape
will be produced of any information received or typed.
T
In the LOCAL or ON LINE mode,
a punched tape only will be produced when using the keyboard. In
the ON LI N E mode, a printed copy
will be produced of any information received from the system.
3-19
Section \\\
Sentry 400
Table 3-5. FST-1 2085 Teletype Model ASR-35 Controls and Indicator (Con't)
Unit
Paper Tape
Reader
Keyboard
Control
START/STOP/FREE
Switch
Description
Controls use of the tape reader with
operation of the Teletype. In the lower
F R E E position the reader is disengaged
and can be loaded or unloaded. In the
center STOP position the reader mech. anism is engaged but de-energized. In the
upper START position the reader is
engaged and operated under program control.
Provides a means of printing on paper
when used as a typewriter and punching
tape when the punch is on; also provides
a means to supply input data to the
computer when the LINE/OFF/LOCAL
switch is in the LI NE position.
A number of supplementary keys are
present which provide the following
functions:
BRK RLS
Turns off BREAK light and
restores keyboard/tape reader
transmission.
LOC LF
Causes the paper to feed out
of the printer at an
accelerated rate.
LOC C R
Rei e a s est he t y p e box
carriage allowing it to return
to the left.
LOC BSP
Backspaces the tape punch
one space each time the key
is depressed.
REPT
I f simultaneously depressed
with any character key the
character will be continuously
. repeated until the REPT key
is released.
I
3-20
Se ion III
Sentry 400
Figure 3-5. Teletype Model ASR-35
3-21
Section III
Sentry 400
Table 3-6. FST-l Model 2060 Disc File Controls and Indicators
Description
Control/Indicator
POWER ON
Pushbutton/
Indicator
Depressing this pushbutton applies primary AC power to the disc
memory and illuminates the POWER ON pushbutton; also illuminates
the NOT READY indicator.
POWER OFF
Pushbutton
Depressing this pushbutton removes primary AC power from the disc
memory, turning off the NOT READY indicator and POWER ON
pushbutton illumination.
NOT READY
Indicator
This indicator is illuminated when any of the following System
Ready conditions are not met:
1.
2.
3.
4.
5.
Power On. (A.C. and D.C. power supplies)
Disc up to speed
Adequate reserve pressure in the air supply system.
Heads flying,
Touch circuit in Fly Ready Status.
Figure 3-6. FST-l Model 2060 Disc Memory
3-22
Sentry 400
Section III
Table 3-7. FST-1 Model 2086 Punched Card Reader Controls and Indicators
STOP
White Pushbutton/
Indicator
This momentary action pushbutton/indicator stops operation
and places the unit in a standby mode of operation when
pressed.
START
Yellow Pushbutton/
Indicator
This momentary action pushbutton/indicator, starts the unit
motor and drive train. It also clears and resets the logic when
pressed.
HOPPER
Amber Indicator
When this indicator lights, the input hopper is empty or the
output stacker is fu II.
READY
Amber Indicator
When lighted, on-line operation of the unit can begin or
resume. An error condition or failure to feed a card will cause
this light to go out.
FEED
Amber I nd icator
When lighted, a feed irregularity, a nonfeed, or interlock
switch open condition is present. After the malfunction is
cleared, the START pushbutton, must be pressed to restart
operation of the unit.
READ
Amber Indicator
When lighted, indicates that a card has failed to read
properly.
OFF
Red Pushbutton/
Indicator
This momentary action pushbutton when pressed, cuts off
AC power to the unit.
ON
Green Pushbutton/
Indicator
This momentary action pushbutton/indicator when pressed,
applies AC power to the power supply and logic circuits. This
indicator is lighted green when power is on.
3-23
Section III
Sentry 400
Figure 3-7. FST-l Model 2086 Punched Card Reader
3-24
Section III
Sentry 400
Table 3-8. Model 2071 Magnetic Tape Unit Controls and Indicator
Controlll ndicator
Descri ption
HIGH/LOW DENSITY
Switch (Slides)
Controls delay of read strobe pulse during reading.
This must be set to high density, 800 BPI.
REVE RSE - Momentary
ON pushbutton
Initiates movement of tape in reverse direction at normal
operating speeds.
REWI NO - Momentary
ON pushbutton
Initiates movement of tape in reverse direction at high speed
until BOT marker is reached.
STOP-RESET - Momentary
ON pushbutton indicator
Stops all tape movement, resets control circuits and returns
transport from remote to local control. Switch indicator
illuminates in local mode.
FORWARD - Momentary
ON pushbutton
Initiates movement of tape in forward direction at normal
operating speed. Forward tape motion stops when tape
reaches EOT tab.
FAST-FORWARD - Momentary Initiates movement of tape in forward direction at high
ON pushbutton
speed. Forward tape motion stops when tape reaches EOT
tab. The tape unit will not detect a BOT marker.
REMOTE - Momentary
ON pushbutton
Sets transport to remote. On-line control switch indicator
illuminates in Remote mode.
POWE R - indicator
lamp
Illuminates when regulated +12 vdc current is available at
transport.
FI LE PROTECT
I ndicator lamp
Illuminates when write enable ring is not in place, indicating
that tape data is protected. Also illuminates when no reel is
installed on file reel.
INTERLOCK - Automatic
door operated switch
Prevents tape movement, read or write operation, and tape
spillage when door is open during operation. Storage arms
retract to local position, and reels take up resultant tape
slack. When switch is pulled outward, permits operation with
door open.
BRAKE RELEASE SWITCH Momentary Button
This switch releases the reel brakes to facilitate loading of
tape.
All controls and indicators, except the HIGH/LOW DENSITY, INTERLOCK and BRAKE
RELEASE switches are located on the operator control panel. All other switches are located
at the bottom of the INTERNAL front panel.
3-25
Section III
Sentry 400
Figure 3-8. Model 2071 Magnetic Tape Unit
3-26
Table 3-9. FST-1 Model 2310 Line Printer Controls and Indicators
Control Panel
Control/Indicator
Description
POWER
Indicator
Lights when AC power is applied to line printer.
READY
Indicator
Lights when printer power is on, interlocks are satisfied, and
PRINT INHIBIT switch is off.
ON LINE
Indicator
Lights when printer is in ON LI N E mode of operation and
PRINT INHIBIT switch is off.
ON LINE/OFF LINE
Switch
Selects mode of operation for printer.
TOP OF FORM
Switch
Advances tractors to top-of-form position. Disabled when in
ON LI NE mode.
Maintenance Panel
Control/Indicator
Description
DRUM GATE
Indicator
Lights when drum gate is unlatched.
PAPER FAULT
Indicator
Lights when paper is torn or missing.
PRINT INHIBIT
Indicator
Lights when PRINT INHIBIT switch is in ON position.
PRINT INHIBIT
Switch
I nhibits hammer drivers during maintenance.
MASTER CLEAR
Switch
I nitializes the printer to ensure that the logic elements are in
proper states.
Main Power Circuit
Breaker
Appl ies AC power to printer.
3-27
Figure 3-9. Model 2310 Line Printer Controls and Indicators
3-28
Section III
3.3 SYSTEM POWER ON· PROCEDURE
J
The following procedure is used to apply power to the Sentry 400 Test System.
T~lS \~ ""~
1.
Set WRITE INHIBIT switch in the disc to the up position. ~
de£~'\'tt1
2.
Set the MAIN POWER circuit breakers to the ON position.
3.
Press POWER ON pushbutton on the disc memory unit. The POWER ON pushbutton and NOT READY indicator will illuminate. Wait for NOT READY lamp
to extinguish.
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4.
Set SIC (Single Instruction Cycle) and SMC (Single Memory Cycle) on the FST-I
computer to the on (UP) position.
5.
Turn the main frame Power key switch clockwise to the ON position then depress
the¥RESET button.
6.
Turn the Teletype LINE/OFF/LOCAL switch to the LINE position.
7.
Turn the test station Power key switch clockwise to the ON position then depress
the POWER RESET button.
Turn all other desired peripheral devices on by depressing the appropriate POWER
ON pushbuttons.
vei/Able
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8.
9.
10.
Set WRITE INHIBIT switch to the down position in the DISC.
Load the DOPSY monitor (Sect. 3.5.1).
3.3.1 Power Failures and Alarms
If the AC power input fails for a period of more than 8 milliseconds, system power will be
automatically turned off. To return system power, repeat power turn on procedure.
If a power failure occurs at the mainframe the power failure lamp at the mainframe will
cycle on and off, also an audible alarm at the mainframe will be heard. If a power supply
failure occurs in the test station, power failure lamps will cycle on and off, and audible
alarms will be heard at the mainframe and affected stations.
3.4 SYSTEM POWER OFF PROCEDURE
The following procedure is used to remove power from the Sentry 400 Test System.
1.
Set WRITE INHIBIT switch in the disc to the up position.
2.
Set SIC and SMC switches on the FST-I computer to the on (up) position.
3.
Turn the test station key switch counter clockwise.
3-29
·Sentry 400
Section III
4.
Set Teletype LINE/OFF/LOCAL switch to the OFF position.
5.
Turn the mainframe key switch counter clockwise.
6.
Press the POWER OFF pushbutton on the disc memory unit.
7.
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Remov~ power from all peripheral devices by pressing the POWER OFF pushbuttons and/or placing the power switch in the OFF position for each respective
device.
3.5 LOADING SENTRY 400 DEVICE TEST PROGRAMS INTO THE COMPUTER
After applying primary power to the test system, the Disc OPerating SYstem (DOPSY)
program is normally loaded into the computer core memory (Table 3-1) by the operator.
DOPSY has a repertoire of commands that allows the operator to perform such operations
as: assemble or compile a source Sentry 400 device test program and load the Tester
OPerating SYstem (TOPSY) program into computer core memory. Instructions for performing these operations are found in the following paragraphs. A repertoire of DOPSY commands is shown in Table 3-10, detailed instruction in their use can be found in the DapSY
manual.
Table 3-10. Summary of DOPSY Commands
Description
Command
JOB
Initializes system for processing a new job by clearing working storage on the disc and resets the Primary Input Device (PID) and
Primary Output Device (POD) to the standard system values.
ASM
Assembles a source program read by the PID from a specified device,
or from a named disc file. Options to this command will produce
assembly and symbol table listings, and generate an object program.
At the conclusion of an assembly, the object program is left in working storage.
EXEC
Causes object programs to be loaded from PID, a specified device,
disc working storage, or a named disc file; a core image program can
also be loaded from a named disc file.
CREATE
Accepts data from a specified device or disc working storage and
creates a new file named by this command. If a file by the name
specified by this command already exists (i.e., file lin" may have
been previously created using the ASSI GN command), the data will
be stored in the existing file.
ASSIGN
Allocates the specified amount of space on the disc as a new file
named by this command; or changes the amount of space allocated to
an existing file by that name.
Co~ttl.' ~ S.~tM ,...,~ UI.,'~.VIII
\\4
FAc..-rO'"
lo.-..>-'1L
....
3-30
(~ • 'p.t.~~/t;"" dt.v/t.A-1.t ~ 0.. ~~
r,\te..~ t!J,lt.~~ I... ~/) ~~ wlrl
,.,.tAJC4.
~ ....
n$-h"~$~ c'JJ c.tIJ. Il$N~/. a~ ~ e.o.tJM,l.
.. tAJ-.,lt" ~ rJ..AJ.. "s lefl- I~ 1ttIO'~/~ sIo~.
Sentry 400
Section III
Table 3-10. Summary of DOPSY Commands (Continued)
Command
Description
FDUMP
Allows the user to dump the contents of his directory, or a portion
thereof, to a specified device or PI D; also allows part or all of a
named disc file to be dumped to a specified device or to working
storage.
DELETE
Allows the user to remove (delete) a named disc file to clear the disc
working storage area. Also removes the file name from the directory.
RENAME
Allows the user to rename a specific disc file or to change the job
number required to access the files belonging to the current job.
DUMP
Allows the user to dump a specified portion of core memory to a
specified device.
NOTE
Allows the user to output the accompanying text, (between quotation marks), to a specified device.
SET
Allows the user to temporarily redefine the PI D and POD; effective
only until the next JOB or SET command.
PATCH
Allows the user to modify the existing contents of a named core
image disc file and/or to add to the data stored in the file, within the
limits of the file size as established by the ASSIGN command.
EDIT
Allows the user to modify disc resident programs
TOPSY
Calls the tester operating system.
3.5.1 Loading DOPSY From Disc Memory
The following procedure should be used to load the Disc OPerating SYstem (DOPSY) program into the FST-l computer core memory from the Model 2060 Disc Memory. :
1.
Verify that the system power is on and is in the Ready condition. See Section
3.3.
2.
Put the two card Disc Bootstrap program followed by a blank card in the card
reader hopper (face down with the top edge towards the operator). The Disc
Bootstrap program cards must be in the following order: BINARY BOOTSTRAP
No. I, then BCD BOOTSTRAP FOR ARR.
3-31
Section III
Section III
3.
Place the card reader in the Ready condition by pressing the following card reader
pushbuttons in the sequence listed: POWER ON, START. Wait for READY lamp.
4.
At the computer control panel, depress the STOP, RESET, and LOAD CDR (or
MT if supplied with system) switches in that order. After the LOAD CDR switch
is depressed, the card reader should read the first card of the Disc Bootstrap
program, i.e., the BINARY BOOTSTRAP No. 1 card.
NOTE
If the card reader fails to read the
card, visually check the status indicators on the card reader control panel.
If the card reader is still in the
Ready condition, repeat step 4; if a
IIcheck" indicator is illuminated, take
necessary corrective action to restore
the card reader to the Ready condition then repeat step 4.
5.
Set the CPU SWITCH REGISTER switches to 01000 100 8 , Set single instruction
Cycle (SIC) and depress LDC (load command register). Then put SIC down and
depress START. (The second card of the Disc Bootstrap program "BCD BOOTSTRAP FOR ARR," should now be read; if not, make sure that the card reader is
in the Ready condition and repeat step 5.)
6.
With the successful completion of step 5, the DOPSY program will be loaded into
core memory from the disc memory and an asterisk (*) printed on the Teletype
printer to signify that DOPSY is resident in core memory.
7.
Initialize the DOPSY system and start a job process by typing the DOPSY command "JOB" using the following format: / / JOB 'xxxx' where xxxx is the four
character alphanumeric job code, selected by and identifying the originator of a
desired repertoire of programs.
3.5.2 Compiling a Source Factor Program
After DOPSY is stored in the computer core memory using the procedure in paragraph
3.5.1, the operator can compile a FACTOR "source" device test program using the DOPSY
command COMPILE. If the "source" device test program does not presently reside on the
disc as a STRING file, the compilation can be performed in one of two ways:
3-32
Section III
Sentry 400
1.
Read and compile the "source" program directly from the desired input device
(i.e., card reader, TTR, magentic tape or TTK) and leave an object program in
working storage on the disc using the DOPSY command COMPILE. The resultant
object program can now be stored as a permanent DATA :disc file using the
DOPSY command CREATE. (This DATA disc file cannot be edited by the
EDIOTR program-only STRING files can be edited.)
Read the "source" program from the desired input device and create a permanent
STRING disc file using the DOPSY command CREATE. (This STRING file can
be edited at a later time if desired using the Editor program). The newly
"created" STRING file can now be read from the disc and compiled, with an
object program left in working storage on the disc, using the DOPSY command
COMPILE. The resultant object program can now be stored as a permanent
DATA disc file using the DOPSY command CREATE.
The following procedure should be used to compile a source device test program in
accordance with method number 2 if the input device is the card reader:
1.
Load the source card deck in the hopper face down with the top edge toward the
operator.
NOTE
The last three cards in the source deck
must be an END,
that order.
I I,
and a blank in
Turn the card reader on and place it in the READY condition.
2.
Initiate the card reader operation and store the program as a STRING file on the
disc by typing the CREATE command as follows:
II CREATE 'xxxxxx' STRING CR
where 'xxxxxx' is any allowable user defined file name. The cards will now be
read and the program stored on the disc. When the operation is finished, the
S"et. Nor£, fJ II' CR. E"".
teleprinter will respond by printing an asterisk.
"&!DIII"/
The "name" should indicate in some manner, for future reference, that it is a
STRING file; Fairchild programmers generally start the name with an asterisk to
indicate this, e.g., '* ADDER'.
3.
Type the COMPILE command, preceeded by two slashes and followed by the
desired compiler options:
3-33
Section III
Sentry 400
e.g., / / COMPILE 'xxxxxx' OBJ
where 'xxxxxx' is the file name assigned in step 2. This example causes the resultant
object program to be stored in the disc working storage also. The teleprinter will
print an asterisk when the operation is complete. Refer to the description of
COMPILE in the DOPSY manual for more detailed use of the command and its
options. Other options are LIST or LISTOBJ or any combination of the three.
4.
Store the object program left in working storage in step 3 as a permanent DATA
file" on the disc by typing the CREATE command as follows:
/ / CREATE 'xxxxxx' DATA
where 'xxxxxx' could be the same "name" used in step 2 without the STRING
file identifier~ e.g., 'ADDER' instead of '*ADDER'. The teleprinter will print an
asterisk when the operation is complete.
The following procedure should be used to compile a source device test program in
accordance with method number 2 if the input device is the Teletype paper tape reader:
1.
Type the CREATE command as follows:
/ / CREATE 'xxxxxx' STRING TTR
where 'xxxxxx' is any allowable user defined file name.
2.
Load the source tape into the Teletype paper tape reader such that the arrows on
the tape point toward the operator. Place the Teletype START/STOP/FREE
switch in the START position.
3.
Press the START pushbutton on the CPU Front Panel; the tape will now be read
and the program stored as a STRING file on the disc. When the CREATE operation is complete, the teleprinter will print an asterisk.
4.
Type the COMPILE command, preceeded by two slashes and followed by the
desired compiler options:
e.g., / / COMPILE 'xxxxxx' OBJ
where 'xxxxxx' is the file name assigned in step 1. This example causes the resultant object program to be stored in the disc working storage area. The teleprinter will
print an asterisk when the COMPILE operation is complete.
3-34
Sentry 400
Section III
5.
Place the Teletype START/STOP/FREE switch in the FREE position.
6.
Store the object program left in working storage in step 4 as a permanent DATA
file on the disc by typing the CREATE command as follows:
// CREATE 'xxx xxx' DATA
The teleprinter will print an asterisk when the CREATE operation is complete.
Although it is possible to compile a device test program entered via the Teletype keyboard,
the length of most device test programs would make this a cumbersome method. Therefore
this method will not be discussed here.
A program may be compiled directly from the source (cards, paper tape, keyboard) by typing
/ / COMPILE OBI CR
/ / CREATE DATA 'xxxxxx'
This does not create a source file on the disc and hence may conserve disc space. However,
source EDIT will not be possible.
3.5.3 Loading TOPSY From Disc
After the Sentry 400 device test program has been compiled and stored as a permanent "data"
file on disc memory the TOPSY (Tester OPerating SYstem) program is loaded into core
memory from the disc memory as follows:
I.
Type / / TOPSY on the teletype keyboard. The DOPSY program will now load
TOPSY into core memory from the disc memory.
NOTE
If DOPSY cannot locate TOPSY on
the disc, the error message
"ERROR-FUNCTION NOT IMPLEMENTED" will be printed and the
system will return to a "wait-forDOPSY -command" state. If TOPSY
is loaded but the TOPSY monitor
determines that a TOPSY subroutine
is missing (e.g., data logger or command processor), the error message
"ERROR SYSTEM 11" is printed,
DOPSY is automatically reloaded,
and an asterisk (*) is printed when
DOPSY is resident in core memory.
3-35
<)entry 400
Section III
3.5.4 Loading Device Test Program From Disc Using TOPSY
After the Tester OPerating SYstem (TOPSY) program is resident in core memory the device
test program is loaded into core memory from the disc memory as follows:
1.
Press the MON pushbutton-TTY will respond with a colon ":".
2.
Type /. LOAD 'xxxxxx' STATI where 'xxxxxx' is the name of the desired test
program as it appears in the disc directory under the current job number and I is the
station number assigned to execute the program. TOPSY now searches for and (as
far as the operator is concerned) loads the named test program; when the LOAD
operating conditions (See 3.5.5) and then start testing.
NOTE
The named device test program must
be type DATA (refer to preceeding
paragraphs) .
After the device test program is resident in core memory, along with TOPSY, the
operator can commence testing immediately, or initialize or modify the tester
operating conditions (e.g., change test delay) and then start testing.
3.5.5 Initialize or Modify Tester Operating Conditions with TOPSY Monitor Commands
Prior to the start of active device testing using the device test program currently resident in
core memory along with TOPSY, the operator may wish to initialize or modify the tester
operating conditions using any or all of the TOPSY monitor commands available. A brief
description of each command is found in Table 3-11 ; refer to the TOPSY Manual for a
detailed description and format options for each TOPSY command.
Table 3-12 gives a few examples of the format statements acceptable for TOPSY commands,
beginning with the loading of a device test program. In the examples all noise words are
ignored by the computer. A noise word is defined as a word or name other than those
reserved names recognized by the command which may be inserted freely in the command
statement to improve readability.
NOTE
Each TOPSY command must be
preceeded by 11/." (slash-period) and,
end with a STATI (Station number).
3-36
Sentry 400
Section III
Table 3-11. Summary of TOPSY Commands
Description
Command
LOAD
I nitializes the tester (equivalent to depressing tester R E.s,rr switch)
defines the name of the object test program to be loaded into core
memory from disc memory when the Station Start Switch is depressed. The modifications to the tester operation (performed with
commands MODI FY, PAUSE, DATALOG, TITLE, and SWiTCH) are, "
cleared by this commanq. v~ '('~S
SA"L ' • .. ,..... •••• , tet WI~
TITLE
This command normally follows & LOAD c~m!n~' *~IJO~i .~e
operator to enter a message ~"c~aracters~;
Ji:i\lvh IC~
will be stored internally by TOPSY until required. The TITLE
message will be printed at the top of the first page of data log information each time a test program is executed following the TITLE
command.
PAUSE
Initializes the data logger subroutine such that testing will pause
(halt) upon detecting each failure after the START switch is depressed while in the AUTO mode; PAUSE can also be used to
initialize the interpreter subroutine such that testing will pause (ha It)
after executing a specified statement number. I n both cases, testing is
resumed after depressing the START switch on the appropriate test
station.
This command allows the operator to specify a new test delay. The
original test delay instructions in the test program are ignored, not
destroyed, and can be reinstated by turning the MODI FY condition
off with another MODIFY command or with a CLEAR command.
'00« I '1'
MODIFY
;;;3
DATALOG
This command initializes the datalogger subroutine such that datalogging is accompl ished in accordance with the command options.
SET
This command allows the operator to temporarily specify a new
primary input or output device until changed by another SET
command. This command does not need to be followed by a station
number.
SWITCH
This command allows the operator to specify a floating point number
which is stored in the floating point global variable SWITCH. The
global variable is used with appropriate Sentry 400 Users Language
instructions to automatically control the device test program execution sequence.
CLEAR
Execution of this command rescinds all modified conditions established by the preceding commands; i.e., TITLE, PAUSE, MODI FY,
DATALOG, and SWITCH.
DOPSY
Execution of this command resets the Tester, stores TOPSY in its
present state on a disc file, then loads the DOPSY program into core
memory from the disc memory. This command does not need to be
followed by a station number.
SYNC
Causes a sy nc pulse at the test station panel jack to occur at the
specified statment number.
3-37
Section III
Sentry 400
Table 3-12. TOPSY Command Format Examples
I.
I.
I.
I.
I.
I.
I.
I.
I.
LOAD 'DTL4X' STAT2
CLEAR STAT2
TITLE '3/4/69 RUN NO. 15 ARRAY TYPE 9440' STAT2
DATALOG ON LP ALL FCT DCT AND MEASURE STAT2
SET LP AND CR
SWITCH 5 ST AT2
PAUSE ON FAIL STAT2
PAUSE ON STATEMENT 15 STAT2
MOD I FY ON 3.5E-6 SECON DS ST AT2
3.5.6 Initiation of Active Device Testing
Assuming the necessary software programs, i.e., TOPSY and the desired device test program,
are resident in the CPU core memory and the tester operating conditions have been
initialized (refer to preceeding paragraphs), the user is now ready to insert a prewired load
board if desired and connect the corresponding device to be tested into the test head and
commence active testing.
Testing with the Sentry 400 can be done without a load board. The programmable power
supplies are routed to the I/O connector and the user may wire his test socket or probe ring to
the appropriate pins. Functional testing can be made with no load on outputs, however, while
making DC parameter measurements on outputs, the PMU can force load currents.
The load board may be used for the following applications:
1.
DUT has open collector outputs requiring external pullup resistors.
2.
Functional tests are performed with output pins under load.
3.
Power supply pins are to be addressable under program control.
4.
User requires other special circuitry such as recirculation logic for high speed shift
register testing, etc.
3.5.7 Preparing Performance Board for Testing
Figure 3-10 shows the layout of a universal performance board provided by Fairchild
Systems Technology. Five load boards are provided per each 30 pin configuration. The
contact pins of the load board, when inserted into the load board socket, are connected in
parallel with the corresponding 30 pins of the tester. At the load board socket the force
and sense (utility) lines are laid out in two rows. Between the force and sense lines are
patch plugs and receptacles for solderless connection of components (I watt resistor lead
sizes).
3-38
Sentry 400
Section
III
DPS 1, DPS2, and DPS3, also EBO, EB 1, ECO and EC 1 are brought out to the load board
and connected as desired. The +5Vdc and ground may also be connected to the pins as
desired.
The user may stuff every pin of a load board with resistors connected to the utility lines
and use one board for a whole family of device types since the utility lines may be
switched under program control.
After the user has debugged a new device program it is suggested that a new printed circuit
load board be constructed for that particular device or family. The user will gradually build
up a library of load boards. These boards should be easy for the user to fabricate for the
tolerances are very wide, i.e., the edge pins are on 0.2 inch centers.
Figure 3-11 is a simplified schematic showing the association between the load board pins
and tester pins. Figure 3-12 thru 3-16 illustrate some of the many possible ways in which
the load board can be used. If further assistance in the use of these load boards is required,
please consult your local Fairchild representative.
The final step in wiring a performance board for a specific device type is to identify that
board so it is used only with the device type intended. This is done by wiring the SID
(socket identification) terminals 0 through 14 for a discrete 15 bit binary code, with SID 0
being the least significant bit of the code. A terminal tied to ground represents a binary
"0," while an open terminal represents a binary "1." This hard wired code can be checked
by a user programmed statement in the device test program, causing the test program to
halt if the hardwired code and the programmed SOCKET ID number do not compare.
3.5.8 Inserting Performance Board and Device into Tester
Following the wiring of a performance board for the specific device, the performance board
and device to be tested may be inserted in to the tester.
The performance boards are inserted through the narrow access doors in the tester side
doors. The load board for the first 30 pins (Le., pins 1-30) is inserted into the bottom right
hand load board socket and the load board for the second set of 30 pins (i.e., pins 31-60) is inserted into the bottom left hand socket. Two similar sockets are located on the upper left and
right side of the tester for the next two groups of 30 pins.
Following the insertion of the load boards, the user may connect his probe ring or test socket
to the appropriate I/O pins on the tester. The device to be tested may now be inserted into the
test socket and the device is now ready for testing.
3.5.9 Select Test Mode and Commence Testing
If all instructions in the preceeding paragraphs have been executed in the proper sequence, the
Tester OPerating SYstem (TOPSY) program and device test program are resident in core
memory, the proper performance board is in place and the device to be tested in inserted in
the test socket. The operator may now select the desired test mode of operation and
commence testing as follows:
3-41
Section III
Sentry 400
1.
Set the MAN switch on the Test Station Front Panel for the desired mode of
operation i.e., AUTO or MANUAL. The button will be illuminated for manual and
will be off for automatic. TOPSY MONITOR COMMANDS and the test mode.
2.
Depress the test station START switch. The device test program will now be
executed under program control according to the conditions established by the
TOPSY MONITOR COMMANDS and the TEST MODE switch.
3.5.10 Error Messages
When an error is detected the compiler will always type the full current record. For the most
part FACTOR's error messages are self-explanatory; they are listed below with some
comments. The error message text begins at the left margin. An upward pointing arrow
indicates the position in the source statement analysis at which the error was found.
When an error is detected one of two procedures is taken. If the error is recoverable, i.e., if the
compiler can continue, FACTOR will continue to compile and notify the user of further
errors. If the error is not recoverable, the DOPSY monitor will be called and an asterisk will be
typed to notify the user that he is back in monitor. The user then has the option of correcting
errors in the source program and redoing the compilation, or, if the program compiled error
free, he may save the object program by creating a data file on the disc.
The text of the messages MISSING )) and]] have doubled up on the parens and brackets
because the up arrow error position indicator might be placed within the error message text
and make the message unreadable if only one paren or bracket was specified and then replaced
with up arrow.
Examples:
MISSItG »
MISSING t)
MISSING »
3-42
t
VOLTAGE CONDITIONER
Ek1
.
-
El
EA~
EAl
-
CH.l
H
CH.3
~.
..
S
-
-
V
~
~UTILITY
~
EIN
SiJ
REF.
VOLTAGES
'"
V
'"
-V
-
-
Sl
-
~~
LDL
LDH
*LEVEL DETECTOR
*IF EIN
:
PMU~ PMU
I
SENSE
~>---____---t--_~ I> SENSE
BUSS
L.D.
I
1"'t.
(
TO E.U.T. }
WINCHESTER
V.C.
:>0- (...
CONNECTO
R
I
PMU
FORCE ~~PM-U~-~~--'~:>FORCE
BUSS
~
CH.4
SWITCH
DRIVERS
F
I
I"-
CH.2
~
TO
LOAD BOARD
> EREF, OUTPUT = LOW
Figure 3-11 Simplified Tester Schematic
FOR
ONE
TESTER
PIN
lin"
I
J
SENSOR
[>
LINE
- - - - - -SENSE
-- - + - - t - -I I
R=O
\
------+-.....
LU
2:
...J
FORCE LINE
>-
«
...J
D=O
LU
UTILITY
RELA Y
30 PIN
MODULE
~
~
DRIVER
0:
>-
I...J
~
LOAD BOARD
=>
,~ R2~
FORCE LINE
/
----------------------~
Rl~
---+---J
HI
~
LO
ONE OF SEVEN PROGRAMMABLE SUPPLY LlN~
~30 FORCE/SENSE PAIRS
cl~
T
I/O
CONNECTOR -75 PIN
~
D.U.T.
TWO VALUES OF LOAD RESISTANCE, Rl or Rl . R2I(Rl +R2)
Figure 3-12 Load Board, Two Values of Load Resistance
3-44
I
r
SENSOR
SENSE LINE
R=l
tC>
t
UJ
Z
-l
~
0=1
UJ
0:
UTILITY
RELAY
/
FORCE LINE
>-
«
-l
30 PIN
MODULE
>-
~
I--
I-l
~
LOAD BOARD
=>
RS
HI
LO~______~
~
'-----~
ONE OF SEVEN PROGRAMMABLE SUPPLY LlN<;J
~30 FORCE/SENSE PAIRS
:{;Y-I/O
CONNECTOR -75 PIN
IL_
D.U.T.
PROGRAMMABLE CURRENT SOURCE FROM FUNCTIONAL DRIVER
FORCE V F AND SENSE SO/Sl TO COMPUTE IL USING CLOSED LOOP
PROGRAM CONTROL
Figure 3-13 Load Board, Programmable Current Source
3-45
I
I
SENSOR
SENSE LINE
R=O
[>
\
30 PIN
MODULE
UTILITY
RELAY
w
;;::::
:::::i
>-
«
--l
FORCE LINE
D=O
W
a:
>-
I-
~-
~
--l
i=
::::)
LOAD BOARD
~---------------------'~
HI
T
LO
~-~
ONE OFSEVEN PROGRAMMABLE SUPPLY l I ' < J
I
~30 FORCE/SENSE PAIRS
J~
T
I/O
CONNECTOR -75 PIN
~
I
D.U.T.
SWITCHED LOAD RESISTOR TO PROGRAMMABLE SUPPLY.
RESISTOR CAN BE SWITCHED OUT FOR PRECISION MEASUREMENT.
Figure 3-14 Load Board, Switched Load Resistance
3-46
I
I
SENSOR
[>
SENSE LINE
------~~~------~~~~
30 PIN
MODULE
R=1
..-----....... t
-'
LU
Z
-I
>«
FORCE LINE
_
0=0
-I
LU
UTILITY
RELAY
~
~
DRIVER
0:
>I-I
t=
LOAD BOARD
=>
----------------------~~
HI
T
LO
'""""-----~
ONE OF SEVEN PROGRAMMABLE SUPPLY
L.----- 30 FO RCE/SENSE PAl RS
(9 ty-'
Vcc / VDD /etc.
D.U.T.
LI~
I
I
I/O
CONNECTOR -75 PIN
PROGRAMMABLE POWER SUPPLY PIN ADDRESSING
Figure 3-15 Load Board, Programmable Power Supply
3-47
I
1
SENSOR
[>
SENSE LINE
R=O
\1
r------.........
w
2:
....J
>-
«
....J
FORCE LINE
0=0
w
ex:
>I-
30 PIN
MODULE
UTI L1TY
RELAY
~ --
....J
~
LOAD BOARD
~--------------------~~
HI
LO
-=-
~_
3-51
Section III
SentrY 400
Table 3-14. DOPSY Edit Program Commands
Command
Name
Form(s)
OPEN
o Ifile name'
Open the named file as the OlDFI lE for editing
purposes.
COpy
CEOF
Copy to end of fi Ie.
CNN/NNB
Copy NN records to new file in working storage.
C lABEL
Copy all records from old file through record with label.
C lABEL + NN
Copy through the label plus NN number of records.
c
Copy next record.
CARRIAGE
RETURN
Copy next record.
COpy
Copies the file named, record by record to working
storage. The last record moved to working storage is
printed on the TTY.
DELETE
D
Dnn
BACKUP
SET
ALTER
lABE l
=
NOTE:
If label is not found, editor will copy to the
end of the input file.
the first 8 or less characters in the first
eight positions of the record.
Pass over next record without copying into W.S. Record
deleted is printed.
Pass over next nn records without copying into W.S.
(The last record deleted is printed on the TTY.)
B
Back up one record.
Bnn
Back up nn records in both input and output files.
(Printed on the TTY i~ the last record copied to the
output file.)
Take the following records, until terminated by a I I'
record, as STRING input to W.S.
INSERT
3-52
Definition
I
SCR
Change input device to card reader.
STTK
Change input device to Teletype Keyboard.
A
Pass over next record without copying into W.S.; then
allow insertion of one or more records, until terminated
by II record, as STRING input to W.S. Record to be
altered is printed on TTY.
Sentry 400
Section III
Table 3-14. DOPSY Edit Program Commands (Con't)
Command
Name
Form(s)
An
XOUT
x
Xnn/nnB
Definition
Pass over next n records without copying into W.S.;
then allow insertion of one or more records, until
terminated by II record, as STRING input to W.S. Last
record passed over is printed on TTY.
Delete last record from the W.S. output file. Last record
in output file is printed on TTY.
Delete the last nn records from the W.S. output file.
(Printed on the TTY is the last record remaining in
working storage after execution of the command.)
3.
Following the> in step 2, type 0 'file name' -l-. This statement informs the EDITOR
to open the named file for editing. The teletype will respond with a >.
4.
Assume that the named file, now open, has 100 octal statements and the operator
wishes to delete statement number 50 (octal). Immediately following the> in step
3, type C47B-l- (i.e., copy the first 47 octal statements into working storage). The
teletype will respond with the last record copied to W.S. and a >.
5.
Following the> in step 4, type D-l- (i.e., delete or pass over the next record without
copying into working storage). The teletype will respond with a>.
6.
Assume that after step 5, a new record is to be inserted after record 75. (Up to the
present time 47 octal records have been transferred to working storage.) Type after
the> in step 5, C25B~ (i.e., copy the next 25 octal statements into working
storage). The teletype responds with a >.
7.
Following the> in step 6, type I-l- (i.e., take the following records until terminated
by a 'I I' as STRING input to wroking storage.)
8.
After the carriage return in step 7, the teletype responds with an = and waits for the
new record to be typed. Assume the new record is FORCE VF 1 4.3 VOLTS,
RNG2;. TTY responds with an =. Type II-l- after the = (The II terminates the insert
command to the editor.) The teletype responds with a >.
9.
After the> of step 8, type CEOF -l- (i.e., copy to end of old file). The teletype
responds with EOF - INPUT, then does a carriage return and line feed and prints >.
10.
After the> of step 9, type IH (The II terminates the editor and restores control to
DOPSY monitor.) The teletype responds with an *.
3-53
Section III
11.
Sentry 400
The next step is to create a new string file of the records in working storage. This is
achieved by typing the following after the * of step 10.
II CREATE 'new file name' STRING. The teletype will respond with an *.
12.
The last step is to delete the old file. This is achieved by typing the following after
the * step of step 11.
/I DELETE 'old file name'.
The following Table 3-15 shows the teletype printou t of the 12 steps just described.
Table 3-15. DOPSY Editor Printout
STEP
1
2
3
4
5
6
7
I.
DOPSY~
*IIEDIT~
> 0 'file name' ~
> C47B~
(Re: Last record copied to output file)
> D~
> C25B~
>I~
(Insert record in output file here)
8
9
= II~
>CEOF~
EOF-INPUT
10
11
12
>II~
* II CREATE 'new file name' STRING;
* II DELETE 'old file name';
A further important feature of the Sentry 400 EDITOR program is the BACKUP command.
3-54
Sentry 400
Section III
If it is necessary to backup only a few records, the backup command is quite effective. On the
other hand, if the operator has edited all the way down to record 98 of a 100 record program
and then discovers it is necessary to edit an error in record 2, the backup method should not
be used because editing between record 2 and 98 would be overlaid and therefore lost. The
easiest method would be to continue editing from the current record, create a string file, then
reopen the file and correct the error.
If the backup command is to be used, the following method is recommended. Assume that
after step 8 (75 records have been copied into working storage) the operator realizes that an
error still exists in record number 73. After the> of step 8, the operator types Bnn (the B
informing the editor to backup and make the previous nn records available for reprocessing).
In this particular case, since the current record is record 75 and the operator wishes to backup
to record 73, the operator should type B2. (75-73). The teletype responds with a >. After the
>, the operator may use the DELETE, INSERT, or ALTER statement to perform the required
operation as shown in Table 3-14. If the records through which the backup statement was used
contained editing, this editing must again be performed.
3-55
Sentry 400
Section I V
Section IV
Programmi ng
4.1 INTRODUCTION
The Sentry 400 Computer Controlled Test System is controlled by the FST-I, a general
purpose digital computer. The sequence of operation is dependent upon programmed
instructions and statements resident in the CPU core memory.
Two programs must be resident in core memory before device testing can be performed.
The first, is referred to as TOPSY (Tester OPerating SYstem program). The individual
TOPSY instructions are normally of no concern to the user; however, it is possible to
modify the tester operation as determined by TOPSY with a repertoire of TOPSY command
statements entered via the teletype or card reader.
The TOPSY program will cause the CPU to execute the statements of the second program~
a device test program. The device test program consists of a number of statements written
in FACTOR language that is very similar to FORTRAN. The statements consist of a combination of English language words, abbreviations, and mathematical statements that are
descriptive of the operation to be performed by the tester.
The Sentry 400 Test System is capable of being programmed to automatically perform two
distinct types of tests, functional tests and DC measurements. These tests are performed on
digital networks such as: large scale integrated arrays (LSI), complex integrated circuits,
printed circuit boards, and other digital subsystems.
The Sentry 400 performs functional tests on devices that contain up to as many as 240
input/output logic pins. There are no restrictions on programming the division of logic pins
between inputs (to the device-under-test) and outputs (from the device-under-test); i.e., it is
possible to program all pins as inputs, as outputs, or as any combination of the two up to
the maximum of 240 pins.
The structure of the FACTOR Language is such that during the course of a functional test
program, any signal pin can be redefined from an "input" pin to an "output" pin, and vice
versa. It can also be redefined from a "don't care" terminal to a "care" terminal, and vice
versa. The "don't care" condition is useful, for example, to ignore specified output pin conditions if limited interim tests are being performed while the internal states of a device are
being set to a known condition. Redefining a signal pin as an "input" pin or an "output" pin
may be useful, for example, when testing a device that has bidirectional terminals.
4-1
Additional FACTOR statements allow the user to specify DC measurement parameters for
tests such as: force a voltage on pin "n" and measure the current, or force a current on pin
"n" and measure the voltage.
In addition, the magnitudes of all the test system reference _voltages and currents such as
device supply voltages, functional logic level forcing levels, and the Go/No-Go threshold
levels are programmable, as are the internal comparator strobes, synchronous sync signals,
and the system test delay.
4.2 TESTER STATEMENTS, GENERAL DESCRIPTION
A summary of the Sentry 400 Tester Statements is found in Table 4-1. For more detailed
information on the exact format variations, refer to the FACTOR (Fairchild Algorathmic
Compiler Tester ORiented) manual.
Table 4-1. Sentry 400 Tester Statements Summary
Statement
Description
SET DELAY,DC
Executing this statement presets the time delay for subsequent execution of DC tests; i.e., when executing a
FORCE PMU or FORCE VOLTAGE/CURRENT statement.
Executing SET DE LA Y without the modifier, IIDC," presets the strobe delay for subsequent execution of functional
tests; i.e., when executing a SET F statement.
SET S1/S0
Sets the comparator 111" or 110" reference power supply to
the value specified.
SET CLOCK
Specifies the number of clock (sync) signals that the tester
outputs during functional tests.
SET PMU SENSE/FORCEV/
FORCEI,RNG/AUTO
The 'SET PMU SENSE, RNG' form of this statement
initializes the PMU for a measurement in the specified
range. It is normally used in conjunction with a 'FORCE
va L TAG E/CU R RENT' statement, or a 'SET PMU
FORCEV/FORCEI, RNG' statement. The 'SET PMU
FORCEV/FORCEI, RNG' form of this statement initializes
the specified range before an accompanying 'FORCE PMU'
statement is executed. AUTO sets the automatic ranging to
best resolution for force or sense.
SET LOGIC paS/NEG
This statement initializes the functional test comparator
logic pass conditions for either positive or negative logic.
Positive Logic is assumed unless otherwise specified.
SET D
Set each tester pin in the specified rank to the defined
input or output pin configuration.
4-2
Table 4-1. Sentry 400 Tester Statements Summary (Continued)
Statement
Description
SET F
Set the input forcing logic state (111" or 110") for those pins
in the specified rank programmed as I nputs, and the
expected logical output state for those pins programmed as
Outputs.
SET M
Set the IIcare" (comparison enable) or "don't care"
(comparison disable) for each pin in the specified rank.
SET S
Select which set of input reference supplies
(EO/E 1,EAO/EA 1, etc.), are to be used to force the input
voltage on each pin of a specified rank.
SET R
Open or close the utility relay associated with each pin of a
specified rank.
ENABLE
I LO/I H I/VLO/VH I
Two ENAB LE LI M IT statements are used to specify the
upper and lower limits against which all following programmed current/voltage forcing statements are compared;
programmed VF /IF statements within these limits are
executed, while statements outside these limits cause a
terminal error.
ENAB LE CLOCK
Enables circuitry in the test head so that clock pulses from
SYNC jacks on the front panel will be connected to tester
pins 1, 2, 3, and/or 4 as specified.
ENAB LE STROBE
Enables the functional test comparator strobe to be controlled by the contents of F Register bits 0-3 and the
corresponding bits of this statement. This is used in conjunction with DISABLE COMPARATORS.
ENABLE TRIP
LT/GT
Enables the current trip detector of the corresponding voltage forcing unit DPS1, DPS2, DPS3. If the source/load
current of the forcing unit exceeds the enabled trip value
during a test sequence, program control is transferred to
the instruction specified by the liON TR I P" statement.
ENAB LE TR I PV
LT/GT
Enables the voltage trip detector of the corresponding DPS
supply and puts it in the current force mode.
ENAB LE/D ISAB LE
LATCHES
The DISABLE LATCHES form of this statement initializes
the functional test control so that the C Register is cleared
prior to strobing the functional test comparators for each
functional test. The disable mode is assumed unless otherwise specified.
4-3
Table 4-1. Sentry 400 Tester Statements Summary (Continued)
Statement
Description
The ENABLE LATCHES form of this statement initializes
the functional test control so that the C Register is not
cleared prior to strobing the functional test comparators,
thereby retaining a history of functional failures for each
tester pin throughout a test sequence.
ENABLE/DISABLE
COMPARATORS
The ENAB LE COMPARATORS form
initializes the functional test control
comparator outputs will be strobed to
each functional test. The enable mode
otherwise specified.
of this statement
logic so that the
the C Register for
is assumed unless
The DISABLE COMPARATORS form of this statement
initializes the functional test control logic so that the
comparator outputs will not be strobed to the C Register
for each functional test. (Unless ENABLE STROBE
matches the F register).
ENABLE/DISABLE RELAY
The D ISAB LE form of this statement initializes the pin
address control logic such that the voltage conditioner for
pin lin" will be automatically disconnected before the PMU
is connected to that pin. Disable is assumed unlessotherwise
specified.
The ENABLE form of this statement initializes the pin
address control logic such that the voltage conditioner for
pin lin" will remain connected even though the PMU is
connected to that pin; after the PMU is connected to pin
"n," the voltage conditioner can be disconnected by
executing the DISAB LE form of this statement.
ENABLE/DISABLE DCT
The ENABLE forms of this statement define flwindow"
comparison trip limits which establish the "pass" region for
all subsequent DC measurements resulting from the
MEASURE statement.
I
The DISABLE forms of this statement disable the
comparison limits and inhibit the DC fail, regardless of the
measured value.
FORCE E
4-4
This statement forces the specified voltage conditioner
reference supply to the programmed value. If the range is
not specified, then the lowest range is automatically set.
Table 4-1. Sentry 400 Tester Statements Summary (Continued)
Statement
FORCE VF
Description
This statement forces the specified programmable voltage
Forcing supply (DPS 1, DPS2, or DPS3) to the defined value,
and automatically connects the supply to the test head load
board.
FORCE IF
This statement forces the specified programmable DPS
supply to force a current to the defined value. It must be
preceded by an ENABLE TRIPV statement.
CPMU PIN
This statement connects the PMU to the specified pin
number. Tester pins are specified by values from 1 to,
120 10 , For diagnostic purposes, various internal nodes ~an!
be connected to the PMU by specifying a pin number!
. .
between 128 1 0 and 255 1 o·
FORCE VOL TAGE/
CURRENT
This statement forces a programmed voltage or current via
the PMU to the tester pin specified by the previously
executed CPM U PIN statement.
FORCE PMU
This instruction is used in conjunction with the conditions
established by a previously executed IISET PMU
FORCEV/FORCEI, RNG;" statement; i.e., the IISET
PMU---" statement establishes the FORCE, VOL TAGE/
CURRENT, and RANGE conditions for a DC measurement,
while the FORCE PMU statement specifies the numeric
value to be forced. When executed, this statement forces a
current or voltage as specified, at the tester pin specified by
a previously executed CPMU PI N statement.
FORCE STROBE
This statement forces a single functional test strobe (even
though the comparators may have been disabled by a
DISABLE COMPARATORS statement) thus strobing the
comparator outputs to the C Register.
FORCE CLOCK
This statement forces a single clock pulse to occur simultaneously at each of the four front panel SYNC output
jacks.
FORCE RESET
This statement forces the test system into the reset state,
thus clearing all programmable test conditions.
FORCE DELAY
This instruction forces a time delay to occur prior to
executing the next instruction; this delay is directly dependent upon the "tester delay" established by the last
SET DE LAY statement executed.
4-5
Table 4-1. Sentry 400 Tester Statements Summary (Continued)
Statement
Description
XPMU PIN
This statement disconnects the PMU from any tester pin or
internal node.
XCON VF 1/VF2/VF3
This statement disconnects the specified voltage forcing
unit (DPS 1, DPS2, or DPS3) from the test head load
board after automatically setting the output voltage of the
unit to zero volts.
MEASURE VALUE/
NODE, LOG
Execution of this statement causes an analog-to-digital conversion within the PMU of a DC voltage or current at a
tester pin or an internal monitor node point.
The "MEASURE VALUE" form of this statement is for a
DC measurement on the tester pin (i.e., pins 1 through
120) connected to the PMU; the measurement conditions
must be preset by a "SET PMU SENSE, RNG" statement.
The "MEASURE NODE" form of this statement causes a
measurement of an internal monitor node point. The
measurement conditions are automatically invoked and will
not be affected by such statements as referred to by the
"MEASURE VALUE" form.
The modifier ",LOG" causes data logging of the measured
value according to the conditions established by the TOPSY
MONITOR logging command "DATALOG".
ON OCT
This statement establishes program branch control conditional on DC test failures (OCT); it is used in conjunction
with, and executed prior to an liENABLE DCT" statement.
ON FCT
This statement establishes program branch control conditional on functional test failures (FCT).
SET CLAMP
POS/N EG/SYM
Sets the PMU voltage clamp levels. The POS selection
allows voltages less than the specified value and greater
than -0.7 volts. The NEG selection allows voltages greater
than the negative of the specified value and less than +0.7
volts. The SYM selection allows voltages between ± specified value.
ON TRIP
This statement establishes program branch control conditional on current trip failures (TRIP). It is used in
4-6
Table 4-1. Sentry 400 Tester Statements Summary (Continued)
Statement
Description
conjunction with and executed prior to an liE NAB LE
TR I P" statement; i.e., if current trips are enabled and a
current trip failure occurs, program control will branch to
the statement label specified by this statement.
SOCKET 10
Execution of this statement causes the hardwired identifier
code on the performance board in the test head socket to
be compared with the identifier code specified. If the two
codes do not compare, a system terminal error is issued and
the program is aborted; a true comparison allows the program execution to continue.
4.3 PROGRAMMING PROCEDURES
In the following paragraphs, an attempt is made to illustrate to the reader how to use the
Sentry 400 Tester Statements that are described in paragraph 4.2. Initially, typical ways of
implementing preliminary tester setup, functional tests, and DC tests will be shown. Finally,
an actual device test program is presented; it is used to show the reader how a typical
device test program could be written to perform both functional and DC testing.
4.3.1 Preliminary Tester Setup Statements
Preliminary tester setup would normally include such operations as: verify that the load board
used with the device test program resident in core memory is in the test head socket; establish
"window" limits that all programmed current/voltage forcing statements will be compared
against; establish a current trip limit for the Vee power supply, force the Vee supply to a
specified value, then measure the Vee current and compare it to a programmable limit; force
the voltage conditioner logical "0" and "1" reference supplies to specified values; and force
the comparator logical "0" and "I " reference supplies to specified values.
Assume the following test parameters for a device to be tested:
1.
Vee = +5.0V, with current limiting> ImA and
2.
Voltage conditioner reference supplies:
"0"
"I"
< 80mA
= +0.5V
= +3.0V
4-7
3.
Comparator reference supplies:
"0" = +0.5V
"1" = +2.5V
4.
Window limits of programmed voltages: -0.1 V to +7.0V
5.
Window limits of programmed currents forced by PMU: -SmA to +5mA
Tester statements to implement the above could be written as follows:
Statement
Number
2
3
4
5
6
7
10
11
12
13
14
IS
16
17
Statement
SOCKET ID 0:
ENABLE VHI LT 7.0, RNG2;
ENABLE VLO GT -.1, RNG2;
ENABLE IHI LT 5E-3, RNG2;
ENABLE ILO GT -5E-3, RNG2;
ON TRIP, ABORT;
ENABLE TRIPI GT 80E-3,RNG2;
FORCE VFI 5.0, RNG2;
MEASURE NODE 143;
IF VALUE LT IE-3 THEN GO TO ABORT;
FORCE EI 3.0, RNG2;
FORCE EO .5, RNG2;
SET SI 2.5, RNG2;
SET SO 0.5, RNG2;
ABORT: END;
The following is a brief analysis of the preceding tester statements:
S.N. 1
SOCKET ID O. This statement states that the load board identification code
is O. Execution of this statement causes the hardwired identifier code on the
performance board to be compared with the code specified.
S.N. 2 & 3
The statements are used to specify the upper and lower limits against which
all following programmed current/voltage statements are compared. The high
limit is set to +7 volts and the low limit to -.1 volt.
S.N. 4 & 5
Statement numbers four and five satisfy the requirements of step five of the
test parameters. The high and low current limits are set to +5 milliamps and
-5 milliamps. Notice that current is written as 5E-3. The 5 merely states that
it is 5 units of current, the E-3 represents 10- 3 and places the decimal point
three places to the left of the unit, i.e., .005 (5 milliamps). 5E-3 therefore is
5 milliamps. If the limit required was 5 microamps, the statement would be
written as 5E.,;6 (.000005), 5 nanoamps would be written as 5E-9.
4-8
S.N.6
This statement indicates that if the current from DPS 1 exceeds the value
specified in statement 7, transfer to the statement ABORT. ABORT can be
the terminal END statement or it could be a section of the program intended
to determine at what current level the device failed.
S.N.7
The current trip device TRIPI, associated with VFl is set to trip if power
supply current flow exceeds 80 milliamps.
S.N.I0
This statement forces the VFl (programmable voltage forcing supply) to 5.0
volts and sets the range to range 2.
S.N. 11
This statement causes a measurement of monitor point 143 in the tester
which is DPTI.
S.N. 12
This statement aborts the test if the current drawn is less than 1 milliamp.
S.N. 13 & 14 These two statements set the voltage conditioners (E 1 and EO reference
supplies) to specified values and ranges.
S.N. 15 & 16 These two statements set the comparator (Sl and SO reference supplies) to
specified values and ranges.
S.N. 17
This is the terminal END statement of the program.
In the example just completed, the test parameters were written out in five steps and were
not included in the program. The test parameters and any other information could have
been included as remarks. Any statement preceded by REM and terminated by a semicolon
will cause no action by TOPSY, the statements are included for information purposes or as
a reminder when examining a "source" program listing. e.g., REM EXPECTED VSAT IS 0.5
VOLTS, any statement preceded by the word WRITE with the statement enclosed in single
quotes and terminated by a semicolon, will be executed by TOPSY, e.g., WRITE 'EXPECTED
VSAT IS 0.5 VOLTS'; Executing this statement will cause EXPECTED VSAT IS 0.5 VOLTS
to be dumped to the current output device. Similarly the computer can be informed that
certain "noise words" exist in the program and should be ignored. "Noise words" are words
intended to give a statement more English language readability.
Figure 4-1 shows an actual program which tests a Fairchild 9300 MSI circuit.
4-9
4.3.2 Functional Testing Statements
The various operations involved in performing functional testing usually include the following: define each tester pin connected to the device as an input or an output; establish each
tester pin used as a "care" or "don't care" terminal; enable the comparators so that the
comparison results of the test are stored for future use, such as data logging; apply a programmed input pattern to the device and compare the actual device outputs to programmed
expected outputs. The user can also disable the comparators so that false failures are not
indicated while interim test patterns are applied to set the device to a known state. In
addition, the user can specify that the test program unconditionally branch to a specified
tester statement number (or to the end of the program) if a failure occurs during functional
testing.
Briefly, restated below are the functions of the various registers involved in function testing.
Function testing is the application of logic levels ("1 's" and "D's") to a digital device to
ensure that it performs its designated functions according to a truth table.
Figure 4-2 is a simplified block diagram showing the basic circuitry associated with one pin.
A minimum system consists of 30 pins worth of circuitry; additons to the system are made
in groups of 30 pins up to a maximum of 120 pins. The driver and detector associated with
each pin enables each pin to be considered as an input pin or an output pin, dependent
upon programming of the registers.
4-10
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I nAn 1
PT ..... ;
r",.r, E,.,.r
p~r"
"'''''''21 ~
1'(11'121 ;,
i'l~~~I.F
"IrT" ,
11I1II"'~1 I
rlo.~LE
~CT!I
1'\01":11 ;
1'l0~?1 ,\
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"Jrd1E
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LO(':1
~"~:?14
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LOGf
P"''''21 ~
io.'~'rr
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tjr"r II:
'.
01/1~2' ~
1'11111'121 A
DCI
rnL LU",
r,cT! GT
pr~:
01'1 III U 7
R~r.11
P,'hLE !'lCTI r.f "'H-~I
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"'T"'I~'
X~~ll
r'T"~lF
0"'~<"'~
"''''''';>~~
4.51
rl~·I'Y
"f~
1~~111!~r'1~,11111
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('I01'1IP
111('1 r 1 ~ 1
~~.17
FI"F(F. VFI Vr.r.~AX, ~Nr;21
FN'CF FI ~.~, "Nr.~'
FI'~r.F.
Dr.:
T>r 4
LFAKAG~
INPUT
J
~~JG~:
~.!,'·3,
L M 6M I
"'''''''11~
"''''~ 11 0
2.'"
PMU
r.rtvr;,
PTtJ,
r II I
"''''III 171
~11'''' '7 ,\
00 P 17 4
~lJ~~
~'H!LF.
Fnpr.~T,
.~. f;j.._~'
"'(1~ln
CALL IFnSTI
CALL IFTESTI
1'6011'.41
)'1'1"111
Pl1\1,
SF~':~H·,
"'0~ I ~6
""'''' 17 I
FAH'u~.31
1
1 t 111 , r'1 f" 1I}l(' ~(7I'
:' r 'f i" ~ T '),. 4 ,
1
'Tel
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rill. IFTEHI
I'T~".I\" I
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7
~
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0111~1~
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1Il0111123
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000123
0011123
000123
001'1124
001'11 ?~
0011126
001111;>7
pn~
I~'PLIT
"'0111 I I ~
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001! II
!'FT F" 111111 11'111 UIIPtJ
0~111~3'"
110""'3'
q~
1Il1/I~IV
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01!1P03~
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00111~7~
001'1 1!7
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IS IIfSFTI
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ell~"''-4
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0111'1031
PIN I
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1 ...
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I III! ~I ('II ~"'IPlI'" '''' I
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MT
11111111"11 111111'111
11
r
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CALL llAK/
"'QI~ I A 4
1'1"1'11 A 5
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~wtHH
14\
142
11~1111~1110\1111
/
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,
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~
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r F
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VALUE 1
1111'10216
0"'~;>1 ~
I'It1I~2
r.T
17
4.6~"-f\'
Figure 4-1. Actual Source Program Listing
4-11/4-12
INPUT/OUTPUT
-----I
EAl
EAO---.....
INPUT
OUTPUT
RELAYS
I/O
r - - --, CONNECTOR
~___
I
_--+)I~
l
E l - - -........
EO---........
L
CT
......._ ,
:
:~DUT
I
-_.J
ACTUAL
OUTPUT
F Reg
EXPECTED 0 UTPUT
O=COMPARE
l=MASK
Sl
SO
Figure 4-2. Simplified Block Diagram
The D register is termed the INPUT/OUTPUT register. If the D register is programmed as "1,"
the associated pin is defined as an input pin; consequently a relay is energized to connect the
output of the driver to the pin. If the D register is programmed "0," the associated pin is
defined as an output pin. The detector is always connected to the pin (except when the PMU is
programmed to that pin) therefore, programming of the M register will determine whether the
output of the detector is inhibited or enabled, to provide a pass/fail status for that pin.
The F register contains the logic patterns "0" or "1" to be applied to those pins defined as
input pins by the D register. If the F register is programmed as a ("1") high level, the F register
causes the high output of the driver to be applied to the associated pin. If the F register is
programmed with a ("O")-low level, the low output of the driver is applied to the pin. The F
register also contains the expected logical output of those pins defined as output pins. The
expected output is fed to the detector and compared with the actual output of the pin. If the
inputs are equal, the detector will provide a "0" output that is interpreted as a pass condition.
If no comparison exists, the detector will provide a "1" output that is interpreted as a fail
condition.
4-13
The M register is the "care/don't care" or "mask" register. The output of the M register is
applied as a third input to the detector. If the programmer is interested (care) in the pass/fail
condition of a pin, the output of the M register is programmed as a "I." The care or "1"
condition enables the detector to make the comparison between the actual voltage and the
expected voltage. If the programmer is not interested (don't care) in the level of a pin, the M
register is programmed as a "don't care" (Mask) or "D." The "don't care" condition inhibits
the output of the detector. However, logic circuitry at the output of the detector will still
provide a "0" level to the C register, and the function test fail output will indicate a pass. An
input pin, or an output pin with an undefined state, would normally be programmed as "don't
care" to prevent false failure indications on that pin.
Tester statements to accomplish function testing could be written as follows:
Statement
Number
2
3
4
5
6
7
10
11
12
13
14
15
Statement
ON FCT, ABORT;
o 110 III Ill;
SET D
o 001 000 000;
SET M
o
110 010 010;
SET F
o 011 000 000;
SET F
o 111101110;
SET F
o 100 100 100;
SET F
0110110011;
SET D
o 000 001 100;
SETM
a 000 011 000;
SET F
a 000 000 110;
SET F
a 000 000 000;
SET F
DISABLE COMPARATORS;
The R register is the utility relay register and controls the utility relays (one per tester pin).
A binary "1" indicates a closed relay and a binary "0" indicates an open relay. The utility
relays may be used for such functions as connecting a load resistor to an output pin.
If the design of the device-under-test is such that more than one set of input patterns must
be applied to set the DUT to a known state, a more efficient way to disable the comparators while the interim patterns are applied would be to use the ENABLE STROBE ~tate
ment. To compare the efficiency of the two methods, first examine the following set of
statements which use the ENABLE/DISABLE COMPARATOR statements:
Statement
Number
2
3
4-14
Statement
ON TRIP, ABORT;
DISABLE COMPARATORS;
SET F
a 000 III 000;
Statement
Number
4
5
6
7
10
11
12
13
14
15
Statement
ENABLE COMPARATORS;
SET F
1 000 111 000;
DISABLE COMPARATORS;
a 000 000 111;
SET F
ENABLE COMPARATORS;
SET F
1 000 000 111;
DISABLE COMPARATORS;
a 000 111 111;
SET F
ENABLE COMPARATORS;
1 000 111 111;
SET F
In the above example, test results are available to the user after executing statements 5, 11,
and 15. Let us examine the same program again. This time, however, the ENABLE
STROBE statement is used instead of the ENABLE/DISABLE COMPARATOR statements:
Statement
Number
1
2
3
4
5
6
7
10
Statement
ON TRIPP, ABORT; DISABLE COMPARATORS;
ENABLE STROBE 1000;
SET F
a 000 111 000;
SET F
1 000 111 000;
SET F
a 000 000 111;
SET F
1 000 000 111;
SET F
a 000 111 111;
SET F
1 000 111 111;
In the above example, the same functional tests are executed as in the first example.
Notice, however, that fewer program statements were required when using the ENABLE
STROBE statement rather than the ENABLE/DISABLE COMPARATOR statements.
If programmed synchronous clocks are required for signal conditioning beyond the capabilities of the test head functional test patterns, one or any combination of four clock (or
sync) pulses can be programmed to occur using the ENABLE CLOCK and SET CLOCK
statements in conjunction with a series of SET F-statements. As an example, assume a particular circuit on the DDT requires two successive clocks to cause the output state to go to a
known condition. A sequence of statements to accomplish that requirement could be
written as follows:
Statement
Number
2
3
Statement
SET DELAY 350E-6;
ENABLE CLOCK 1000;
SET CLOCK 2;
4-15
Statement
Number
Statement
4
ENABLE COMPARATORS;
SET F
1 000 000 000;
SET F
a 000 000 000;
SET F
1 000 000 111;
5
6
7
Figure 4-3 illustrates the timing sequence when executing statements 5, 6, and 7.
STATEMENT No
5
I
6
7
I
I
I
350 I
350 I
J.LseciJ.LSeci
350 I
350 I
J.Lsec~J.Lseci
I
I
I
I
I
SYNC
JACK 1
I
I
I
350
jJ.Lsec
I
STROBE
1050 J.Lsec
I
I 350
:- J.Lsec
I
Figure 4-3. Programmed Clock Timing Examples
4.3.3 Program Simplification
When writing bit patterns into a register, the pattern can be programmed by specifying each
bit of the pattern; the process is not too complicated if the device has 10 or 12 pins. However, if the device has 120 pins or 240 pins, which the system is quite capable of testing,
the programmers task would be practically impossible. To simplify the process, the bit
patterns can be modified by the use of two operators. The computer is programmed to
recognize parenthesis (:) (Pattern replicator) and the bracket [ ] (pin origin statement) as
modifiers to SET D, F, M, S, or R register instructions. Examine the two SET F instructions below:
1)
SET F 0000 11 0000 11 000000000000000000000001;
2)
SET F (4:0) 11 (4:0) 11 (23:0) 1;
In instruction No.1, the bit pattern was laborously written out. Instruction No. 2 reads as
follows. Set the first four bits to "0" followed by two "1 's." Set the next four bits to "0"
followed by two "1 's." Set the next 23 bits to "0" followed by one 1. The two statements
are identical.
4-16
Examine the two SET F instructions below:
1)
SETFOI0I0I0111 0101010111111001111111101011;
2)
SET F (4:01) 11 (4:01) (5:1) 00 (8:1) (2:01) 1;
Again the bit pattern was laboriously written out. Instruction No.2 reads as follows: Insert
four groups of 01, followed by two" 1's," followed by four groups of 0 1, followed by five
"1 's," followed by two "O's," followed by eight "1 's," followed by two groups of 0 1, '
followed by 1. We could just as easily write 120 bits alternating with "1 's" and "O's" as
(60: 10); another configuration could be (12:10001); i.e., the number of bits within the
parenthesis (pattern replicator) after the colon are repeated successively by the number before the colon. The pattern replicator is therefore used to reduce the number of "1 's" and
"O's" contained within a SET D, F, M, S, or R register instruction. The brackets [ ] (pin
origin) indicate the starting pin number to be affected by the following bit or bit pattern
when contained within any SET D, F, M, S, or R register instruction. Examine the four
statements below.
1)
SET F 0000 11 0000 11 0000 111100;
2)
SET F (4:0) 11 (4:00) 11 (4:0) (5:0) 00;
3)
SET F [6] 01;
4)
SETF [2] 11 [7] 11 [11] 00;
The first two statements are quite straight forward. In the third statement, starting with bit
[ 6], bit 6 is changed to 0 and bit 7 to 1, all other bits remain the same. In the fourth
statement starting with bit [2] bits 2 and 3 are changed to "1 's," starting with bit [7] bits
7 and 8 are changed to "1's," starting with bit [11] bits 11 and 12 are changed to "O's,"
all other bits remain the same. It is not necessary to initially program a register with "1 's"
and "O's" before either the pattern replicator or pin origin modifiers can be used. It is
assumed that all registers are set to "O's" before the program is started (either through a
computer RESET or manual RESET), therefore, all changes are made to the zero status,
subsequent changes are made to the preceding status, and all nonaddress pins will take on
previously specified values.
NOTE
The compiler only generates patterns
for the ranks in which pin changes
occur. If a conditional branch is used,
the registers must be redefi ned when
entering the loop.
4-17
4.3.4 DC Testing Statements
Two types of DC tests can be programmed using the Sentry 400 Tester Statements; they
are: Force a voltage on pin "n" and measure the current or force a current and measure the
voltage. The following paragraphs describe different methods by which these operations can
be implemented.
FORCE VOLTAGE/MEASURE CURRENT: This operation can be programmed by one of
two methods. If the measurement is to be made for one value of forcing voltage only, the
statements could be written as follows:
Statement
Number
1
2
3
Statement
SET PMU SENSE, RNG2;
FORCE VOLTAGE .45, RNG2;
MEASURE VALUE;
If a measurement is to be made for more than one value of forcing voltage, in the same
range, the statements could be written as follows:
Statement
Number
1
2
3
4
5
6
7
10
Statement
SET PMU SENSE, RNG2;
SET PMU FORCEV, RNG2;
FORCE PMU .45;
MEASURE VALUE;
FORCE PMU 4.0;
MEASURE VALUE;
FORCE PMU 4.5;
MEASURE VALUE;
FORCE CURRENT/MEASURE VOLTAGE: Programming this operation is similar to that of
the FORCE VOLTAGE/MEASURE CURRENT type: the only difference being the substitution of VOLTAGE for CURRENT, and CURRENT for VOLTAGE in the statements. A
single measurement could be written:
Statement
Number
2
3
Statement
SET PMU SENSE, RNG2;
FORCE CURRENT -180E-6, RNGl;
MEASURE VALUE;
For more than one value of forcing current, in the same range, the statements could be
written:
4-18
Statement
Number
Statement
SET PMU SENSE, RNG2;
SET PMU FORCEI, RNG 1 ;
FORCE PMU -180E-6;
MEASURE VALUE;
FORCE PMU -20E-6;
MEASURE VALUE;
2
3
4
5
6
MEASURE VOLTAGEjNO CURRENT FLOW: To make a voltage measurement only (i.e.,
with no loading or infinite impedance) the PMU must be programmed to force zero current;
this could be accomplished as follows:
Statement
Number
Statement
1
SET PMU SENSE, AUTO;
FORCE CURRENT 0, RNGO;
MEASURE VALUE;
2
3
4.3.5 Programming Rules
As in any computer controlled system there are certain rules to be followed if correct and
efficien t programming is to be achieved.
1.
A FACTOR language program consists of abbreviated English language
statements. The majority of these statements are contained in Table 4-1
and are supplemented by the FACTOR Manual.
2.
Noise words, are words that the programmer may use to give the
abbreviated statements more readibility. The words must be listed in a
statement, e.g.,
NOISE
VOLTS, AMPS, SECS;
3.
Remarks may be inserted throughout the program. Any statement preceded by REM and terminated by a semicolon will cause no action by
TOPSY. The statement will be printed on the source program listing.
4.
Any text (except quote marks) preceded by the word WRITE, enclosed
in single quotes and terminated by a semicolon will be dumped to the
output device. No test station action occurs.
5.
The REM statement may be listed by separate sequence number, or
they may be included on the same line of a statement to which the
remark refers.
4-19
6.
All statements must be terminated by a semicolon.
7.
FACTOR accommodates: numbers as integers, decimal fractions and
exponentials; handles Boolean and scalar variables; arrays (ordered series
of variables); parametered calls; and a wide variety of other functions,
as specified in the FACTOR Manual.
8.
Subroutines and Functions can be used to avoid rewriting the same
statements at various points in a program. Blocks are used to establish a
LOCAL context for the variables and labels defined therein.
BLOCK (a)
BLOCK (b)
END (b)
BLOCK (c)
BLOCK (d)
END (d)
END (c)
END (a)
Any number of subroutines can be placed in up to eight nesting levels,
and subroutines can be called as often as desired. The global variables
are quantities accessible to all blocks.
9.
Various statements such as IF, THEN, GOTO, and so on, may be used
to mix and match sequences of instructions and branches, in response
to test results. For instance, IF an element fails a critical test, GOTO an
analysis routine to find out why, and THEN put the element into the
reject bin.
4.3.6 Device Program Preparation
The initial step in preparing a device program is usually a handwritten list of FACTOR
commands comprising the program.
A FACTOR language program consists of abbreviated English language statements. Each
statement is a command to carry out some action. When the user program is executed,
these commands are carried out sequentially in the order written. There are, however, commands to change this sequential execution and cause it to begin again at a specified statement, quite possibly one other than the next sequential statement after the one last
executed. Because this transfer of control is possible FACTOR needs a definite way to
indicate where each statement ends. Consequently, every statement must be followed by a
semicolon, the word END or the word ELSE. The word END is used at the end of a program or subroutine. The word ELSE is used when a choice is involved and the semicolon is
used to terminate a statement in a series of statements. Of the three, the semicolon is the
most common.
The statement is the basic unit of a compiler language program. Examine the Sentry 400
FACTOR coding form.
4-20
Statements and labels can occupy any of the first 72 characters of an input record (card, MT,
TTY). The last 8 characters of each record are reserved for sequence numbers. Several
statements can appear on a record, as space permits, or a single statement can be strung over
several records. In any case there is one sequence number per record even if the remainder of
record is blank. It is suggested however, that column 65 should not be exceeded so listings
with statement numbers will fit on the 80 column teletype or line printer without
continuation lines.
The recommended method as shown in the coding form is to use the first eight columns for
the LABEL, the ninth column for a colon (:), the tenth column is a blank. The command is
started in the eleventh column and terminated by a semicolon.
The programmer mayor may not assign sequence numbers at his option since the compiler will
not flag blank sequence fields as sequence errors.
Labels, variables, arrays, subroutines, and functions must be named by a legal identifier
consisting of up to 8 alphanumeric characters, the first an alpha.
On the example coding form, several hand written statements are shown (the complete
program-369 10 statements-is not shown). The statements were then transferred onto
punched cards (one statement per card in this case). The punched cards were then fed into a
card reader and transferred to the computer. On typing / / COMPILE '* SAN1' LIST the
following listing was produced on the TTY. This test program should serve to illustrate how
the Sentry 400 Tester Statements were utilized to perform functional, as well as DC parameter
testing on an actual device. As a matter of interest, DOPSY took 33 seconds to compile this
program.
Statement 1 contains two remarks defining the following tests as function, parameter and probe test sequences. The probe test sequence contains a statement to
unconditionally branch to the location MSSAGE (Statement No. 001227) if a
function test failure occurs.
000025 8
This statement defines that the device uses negative true logic and sets the delay
to 50 microseconds.
000035 8 -000472 8
This is a group of SET F statements. The various combinations were developed by
a computer and hence each bit was printed out. This group illustrates quite
clearly the usefulness of the pattern replicator (:) and pin origin [ ] operators to a
programmer.
4-21
000506 8 -000561 8
These statements each call on the subroutine labeled NLEAK (Statement No.
00 152) and performs that subroutine on each specified pin. Further on in the
program, subroutines labeled, ZLEAK, YLEAK, and WLEAK, etc., are called
upon to perform tests on specified pins. Each of these subroutines call for the
PMU to force a voltage and measure the leakage current through a specified pin.
After the completion of each subroutine or statement, the tester moves to the
next statement and continues on to the end of the program.
4-22
FAIRCHIL..C
FACTOR
CODING
FORM
PAGE
r
OF
y.. 1'80
'4-23/4-24
Section IV
Sentry 400
1/ ·COMP I LE
00001211
01210001
000001
000001
0(~0002
~j
v;k)00 3
d00004
12100005
(}0001216
0012112107
0Dit301121
Qi0001 1
0C0(~ 12
800013
0121121014
00101014
12100014
(i.Wii':~ 14
0tji)015
001012116
01210017
0G012121
(~00022
100012123
:~\01211212 5
vi00027
0012103121
01310031
000032
000033
0012112134
00121035
00012136
000037
121010040
0012112141
1211.30042
000043
1210012144
0121121045
0121121121 46
1210012147
000050
00121051
000052
000053
00121054
00121055
01210056
001.3057
0001216121
0012112161
01210062
010121063
'.SAN1' LIST
REM SENTRY 41210 FUNCTION AND PARAMETER TEST SEQUENCE FOR '5.
REM PROBE TEST SEQUENCEJ
ON FCT" MSSAGEJ
SET SI2I -2" RNG2 J
SET M 10 (16:1) 0 (17:1);
SET DELAY 2I21E-3" DCJ
SET PMU FORCEV" RNG2J
SET PMU SENSE" RNG1J
CPMU PIN 2J
FORCE PMU -5J
SET F 01
F'ORCE PMU 0;
XPMU PINJ
REM
FUNCTION TEST SEQUENCEJ
ON FCT"ABORTJ
FORCE VF2 I2I"RNG2J
FORCE VF'1 -7.0 .• RNG2J
FORCE E0 12I.0J fORCE El -7.0J
FORCE EA0 -20.0"RNG3J
FORCE EAl -20.I2I"RNG3J
SET S0 -1.5J SET SI -4.0J
SET LOGIC NEGJ SET DELAY 5121E-61
SET R (2) 101 (7) 111 (16) 11
SET S [IJ 1 (12J IJ
SET D 1010110121121111112112112111011111111111111011211
SET M (36:1)J
SET M 00 (12) 121 (19) 0 [36J I2IJ
F'ORCE DELAY J
SET F' 0101112112111211211211111112101121121121121121121121121121121121121121012111J
SET F' 12I112111aI2l11210121111111210112112100121121121000001210011J
SET F' 0112111121121112100101110121100012112101210000000011J
SET F' 01121111011211111111121121112100000012112112100faI01211J
SET F' 0101110112111101110121101210012112112112112112112112112111211211J
SET F'12I1121111fal12111111111211211121121121012100121012112100112101J
SET F' 121101111211121111~1111211211121121121121121121001211211211210101211J
SET F' 1211121111121112111111111211211121121121012112112112112112112100112101J
SET F' 0101110112111101111211211012112112112101211211211211211210101211J
SET F' 011211111211011111110010121121121121121121121121121012112111211211J
SET F' 1211121111011211111211111211211121121121121121121121121121012112112111211211J
SET F' 121101110101111111012110012101210121121121012100112101J
SET'12I112111101011112111112101121000121121000001210112101J
SET F' 0112111101121111111112101012100012100000001001J
SET F' 010111010111011101211001210012101211210012101001J
SET r 121101110101111111001012112100000000121121112101J
SET F' 0101110101110111001000000000001211211001J
SET'12I101110101111111001000012101210121012112112111211211J
SET F' 01011101011101110010012112112112100012100121112101J
SET F'12I101111211011111110121100000001210012100101211;
SET F' 01011101121111011.'1121010-00012101210012101210112101J
SET F'12I1121111010111111100100001211210121000012111211211J
SET'010111010111011100100000000000001001;
Figure 4-5. Sentry 400 Device Program
4-25
Sentry 400
Section IV
000064
000065
000066
'100067
(iH~0070
000071
000072
000073
000074
k100075
000076
000077
000100
000101
000102
000103
000104
000105
000106
000107
0001 10
000111
000112
000113
000114
00011 5
0001 16
0001 1 7
000120
000121
000122
000123
000124
000125
000126
000127
000130
000131
000132
000133
000134
000135
000136
12'00137
000140
000141
000! 42
000143
000144
000145
000146
000147
000150
000151
SET r 0101110101111111001000000000000010011
SET r 0101110101110111001000000000000010011
SET r 010111010111111100100000000000001001;
SET r 0101110101110111001000000000000010011
SET r 010111010111111100100000000000001001;
SET ro010111010111011100100000000000001001J
SET r 010111010111111100100000000000001001;
SET'r 010111010111011100100000000000001001;
SET r 010111010111111100100000000000001001;
SET r 0101110101110111001~0000000000001001J
SET F 010111010111111100100000000000001001;
SET F 010111010111011100100000000000001001;
SET r 010111010111111100100000000000001001;
SET F 010111010111011100100000000000001001;
SET r 010111010111111100100000000000001001;
SET r 010111010111011100100000000000001001;
SET F 010111010111111100100000000000001001;
SET or 010111010111011100100000000000001001;
SET r 010111010111111100100000000000001001;
SET r 0101l1010111011100100000000000001001;
SET F 010111010111111100100000000000001001;
SET r 010111010111011100100000000000001001;
SET F 010111010111111100100000000000001001;
SET r 010111010111011100100000000000001001;
SET F 0101110101111111001000000000000010011
SET r 010111010111011100100000000000001001;
SET F 010111010111111100100000000000001001;
SET F 010111010111011100100000000000001001;
SET r 010111010111111100100000000000001001;
SET'0101110101110111001000000000000010011
SET r 010111010111111100100000000000001001;
SET r 010111010111011100100000000000001001;
SET '.010111010111111100100000000000001001;
SET r 010111010111011100100000000000001001;
SET r 0101110101111111001000000000000010011
SET r 010111010111011100100000000000001001;
SET r 010111010111111100100000000000001001;
SET' 010111010111011100100000000000001001;
SET r 010111010111111100100000000000001001;
SET r 010111010111011100100000000000001001;
SET' 010111010111111100100000000000001001J
SET r 010111010111011100100000000000001001;
SET r 010111010111111100100000000000001001;
SET r 010111010111011100100000000000001101;
SET r 010111010111111100100000000000001101;
SET r 010111010111011100100000000000001101;
SET r 010111010111111100100000000000001101;
SET r 0100110101110111001000000000000011011
SET r 010011010111111100100000000000001101;
SET r 010011010111011100100000000000001101;
Ll:
SET D 101011000111100011011111111111111110;
SET M 000100111000011100000000000000000000;
SET r 010011010111011111111111111111111101;
SET F 010011010111011111111111111111111001;
Figure 4-5. (Cant.)
4-26
Sentry 400
000152
000153
000154
~HJ0155
.H~0156
(100157
\;H~0160
0(10161
000162
000163
000164
1~00 1 65
000166
000167
vH10170
000171
0001 72
000173
00'1174
00111 75
~)00176
(100177
C00200
000201
I,H~0202
.000203
000204
~~0020 5
000206
000207
~1002 10
000211
000212
000213
000214
000215
000216
000217
000220
000221
000222
000223
000224
..000225
000226
000227
000230
000231
000232
000233
000234
000235
000236
000237
Section IV
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
r
r
r
r
r
r
r
r
r
r
r
F
F
F
F
F
r
F
r
r
r
F
r
r
r
F
F"
F
F
F
F
F
F
F
F
F
F
F
F
r
F
F
r
F
F
F
F
F
r
F
F
r
F
F
0100110101 1 1011111 1 11111111 1111 1 1101 ;
010011010111011111111111111111111001;
01001 10101 1 101 1 1 1 1 1111 1 1 1 1 1 1 1 1 1 1 1 101 ;
o 1 0 0 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1.1 1 1 1 0 0 1 ;
01001101011 101 11111111 1 111 1 111111 101 ;
010011010111011111111111111111111001 ;
01001 10101 1 101 1 1 1 1 1 11 11 1 1 1 1 1 11 11 1 101 ;
01001 10101 1 101 1 11 1 1 11 1 1 1 1 1 1 1 1 1 1 1 1001 ;
01001 10101 1 10111 111111 1 1111 1 11111 101 ;
01001 10101 1 10111111 1 1 1.1 1 111 1 1 1 1 1 1001 ;
01001 10101 1 101 11 11 1 1 1 11 1 11 1 1 11 1 1 1 101 ;
01001 10101 1 101 1 1 1 1 1 1 1 1 11 1 1 1 1 11 1 11001 ;
01001 10101 1 101 11 1 1 1 1 1 1 1 1 1 11 1 11 1 1 1 101 ;
010011010111011011111111111111111001;
01001 10101 1 101 1011 1 11 1 1 1 1 1 1 1 1 1 1 1 1 101 ;
01001 101011101111111 1 \ 11111111111001 ;
01001 10101 1 101 1 1 1 11 1 1 1 1 1 1 1 1 1 11 1 1 1 101 ;
01001 10101 1 1011 1 1 11 1 1 1 1 1 11 1 1 11 1 1 1001 ;
01001 10101 1 101 1 1 11 1 1 1 1 11 1 1 1 111 1 1 1 101 ;
01001 10101 1 101 1 1 1 11 1 1 1 1 1 1 11 111 1 1 1001 ;
01001 10101 1 101 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 1 1 1 101 ;
01001 10101 1 101 1 11 1111 1 1 1 111 1 1111 1001 ;
010011010111011111111111111111111101 ;
0100110101 110111 1 11 11 1 111 1 111 1 1 1 1001 ;
01001 101011101 11 1 1 1 1 1 1 1 1 111 1 1 1 1 1 1101 ;
01001 10101 1 101 1 1 1 1111 11 1 1 1 1 1 1 1 1 1 1001 ;
01001 10101 1 10111 1 1 1 1 1 1 1 1 1 1 1 1 11 1 1 1 101 .;
010011010111011111111111111111111001;
01001 10101 1 101 11 1 1 1 11 1 1 1 1 1 1 1 1 1 1 1 1 10 1 ;
010011010111011111111111111111111001;
01001 101011 101 1111111111 111111 1 1 1101 ;
010011010111011111111111111111111001)
01001101011 101 1 1 111 1 1 1 1 111111111 1 101 ;
01001101011 101011 1 1 1 111 1 1 11 1 111 11001 ;
0100110101110101111111111111111111011
01001101011 1011111111 1 111 1 1 1 11111001 ;
01001 1010111011 1 1 11 1111 1 1 111111 1 1101 ;
0100110101110111111111111111111110011
01001 101011101 1 11 111 1 1 1111 1 1 11 1 1 1101 ;
01001 10101 1 101111111111111 1 1 11 1 11001 ;
01001 10101 1101111 1 11111 1 1111111 11 101 ;
010011010111011111111111111111111001;
010011010111011 11 111 11 1 1 111 1 11 111 101 ;
010011010111011111111111111111111001 ;
0100110101 11011 1 11111111 1111111 1 1 1011
010011010111001111111111111111111001;
010011010111001 11111111 1 11111 1 111 101 ;
0100110101110011111 1 1 1 11 1111111 1 1001 1
01001 101011 1001 1 1 1 1 1 1 1 1 1 1 11 1 1 111 1 101 ;
01001 10101 1 10011111 11111 111 1 111 11001 J
01001 10101 1 10011 1 11 11 1 11 1 1 1 1 1 1 1 1 1 101 ;
010011010111001111111111111111111001;
01001 10101 1 10011 11 1 1 1 1 1111 1 1 1 1 1 1 1 101 ;
01001 10101 1 100111 1111 1111111111 1 1001 ;
F igu re 4-5. (Cont.)
4-27
Section IV
000240
000241
000242
000243
000244
000245
000246
000247
000250
000251
000252
000253
000254
000255
000256
000257
000260
000261
000262
000263
000264
000265
17100266
000267
000270
000271
000272
000273
000274
000275
000276
000277
000300
000301
000302
000303
000304
000305
000306
000307
000310
000311
000312
000313
000314
000315
000316
000317
000320
000321
000322
000323
000324
000325
Sentry 400
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
F'
F'
F'
F'
F'
F'
F'
F'
F'
F
F
F'
F
F'
F'
F
F'
F
F
F
F
F'
F'
F'
F'
F
F
F'
F
F'
F'
F'
F'
F'
F'
F'
F'
r
o 1001 10101 110011 1 1 1 1 1 1 1 1 1 1 11 1-1 1 1 1 101 J
0100110101 1 100111 1 111111 1 11111111001 J
01001 10101 1 1001 1 1 1 1 1 1 11 1 1 1 111 1 11 1 101 J
01001 101011 10011 1 1 11 1 1 1 1111 11 1 1 1 1001 J
01001 10101 1 1001 1 1 1 1 1 1 11 1 111111 11 1 101 J
01001101011100111111 111111111 111 1001 J
01001 10101 1 10011 1 11 11 1 1 1 111 1 1 1 1 1 1101 ;
01001 10101 1 10111 1111 1 1 1 111 111 111 1001 ;
010011010111011100100000000000000001;
010011010111011100100000000000000101;
010011010111011100100000000000000001;
010011010111011100100000000000000101;
010011010111011100100000000000000001;
0100110101110~1100100000000000000101;
010011010111011100100000000000000001;
010011010111011100100000000000000101;
010011010111011100100000000000000001;
010011010111011100100000000000000101;
010011010111011100100000000000000001;
010011010111011100100000000000000101J
010011010111011100100000000000000001;
010011010111011100100000000000000101;
010011010111011100100000000000000001;
010011010111011100100000000000000101;
010011010111011000100000000000000001;
010011010111011000100000000000000101;
010011010111011000100000000000000001;
010011010111011000100000000000000101;
010011010111011000100000000000000001;
01001101011101100010000000000000010!;
010011010111011000100000000000000001;
010011010111011000100000000000000101~
010011010111011000100000000000000001J
010011010111011000100000000000000101;
010011010111011000100000000000000001;
010011010111011000100000000000000101;
010011010111011000100000000000000001;
010011010111011000100000000000000101;
010011010111011000100000000000000001;
010011010111011000100000000000000101;
010011010111011000100000000000000001;
010011010111011000100000000000000101J
010011010111011000100000000000000001;
010011010111011000100000000000000101;
010011010111011000100000000000000001;
010011010111011000100000000000000101;
010011010111011000100000000000000001;
010011010111011000100000000000000101;
010011010111011000100000000000000001;
010011010111011000100000000000000101;
010011010111011000100000000000000001;
0100110101110110001000000000000001011
F
F'
F'
F'
F'
F'
F'
F'
F'
F'
F'
F
F'
F'
F' 01001101011101100~100000000000000001;
F' 010011010111011000100000000000000101;
Figure 4-5. (Cont.)
4-28
Sentry 400
01210326
'~0~32 7
00121330
000331
000332
000333
000334
1210121335
0~12I336
()00337
000340
~~00341
000342
(~00343
O(l)03'~4
~HH:1345
000346
0100347
C100350
1000351
000352
1211210353
0110354
000355
000356
12100357
VW0360
000361
000362
000363
000364
000365
000366
000367
000370
000371
l100372
000373
000374
000375
000376
000377
000400
000401
000402
000403
000404
000405
000406
000407
00041121
000411
000412
000413
Section IV
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
F'
F'
F'
F'
F'
F'
F'
F'
F'
F'
F'
F'
F
F
F
F
F'
F'
F
F
F'
F
F
F
F
F
r
F'
F
F'
F'
F
F'
F
F'
F'
F
r
F
F
F
F'
F'
F
F'
F'
F'
F'
F'
F'
F'
F'
F'
F'
0100110101111211100010000000000121000001;
121100110101110110001012112101211210121001210001011
010011010111012111012111211210121000000121000001;
01012111010,11112101 112112110121001210001210121000101 ;
01001112110111121011121121101210000000000121001211;
0100110101110011001001211210012101210121000101;
010(1112110)11001100112100000000121121000001;
0100111211011100110010012100000000000101;
0100110101110011001000012100000012100001;
0100110101110011001001211210000121000121121101;
121100110101110011001000000012112100000001;
010121111211011112101100100000000000000101;
01001112110111001100100000000000000001;
0101211101121111001100100000000000000101;
0100iI0101110011001012100000001210000001;
01001101011100110010000000000121000101;
01001101011100110010000000000121000001;
010011010111001100100000000000000101;
01001112110111011100100000000000000001;
01011001000111110010000000012100000011;
0101101211000101110010000000000000012111;
0111 1 10101 1 1 1 1 1 100100000000000000001 ;
011111010111011100100000000000000001;
0111110101 1 1 1 1 1 10010121000000000000001 J
0111110101110111001000000000000000011
011111010111111112112110012100000000000001;
0111110101110111121121101210000121012100000001;
0111110101111111001001Z100000001Z1000001J
01111101011101110010012100000001210000011
011111010111111100100000000000000001;
0111110101110111001000121000012100000001;
011111010111111100100000000000000001;
010111010111111100100000121000121121000012111
0101110101111111001000000000000001011
01001112110111011100100121000000121121000101;
011211211101011111110010000001210000012101011
01001101011101110010000000121000000101;
0100111Z110111111100100000000001Z1000101J
01001101011101110010000001Z10000000101J
010011010111111100100000000000000101J
010011010111011100100121000000000001011
01121011010111011100100000000000000001;
0100110101110111001001210000000000011211;
010121110101111211110010001211210000000000011
0112101101011101110010000000000121000101;
01001101121111121111012110000001210012100000011
011Z101101011101110011Z1000000000000010~;
010011011211110111001001211211210000121000001211;
01001101011101110010000001Z1001Z1000011Z11J
01012111010111121111001012101210000000000012111
12110011011211110111001121000000000000121101;
01001101011101110011210000000000000001;
01001101011101110010000000000001Z10101J
0100110101110111001000001210121000000001;
Figure 4-5. (Cont.)
4-29
Section IV
000414
000415
000416
000417
000 /420
000421
422
'100423
"0"
0;W)424
'" ~10 /t2 5
0130426
0(10427
(100430
000431
000432
000433
000434
000435
000436
000437
000440
000441
000442
000443
000444
000445
000446
000447
000450
000451
000452
000453
000454
000455
000456
000457
000460
000461
000462
000463
000464
000465
000466
000467
000470
000471
000472
000473
000476
000476
000476
000476
000477
000500
Sentry 400
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
r 010011010111011100100000000000000101;
F' 010011010111011000100000000000000001;
r 010011010111111000100000000000000001;
r 010011010111111000100000000000000101;
F' 010111010111011000100000000000000101J
F' 010111010111111000100000000000000101J
F' 010111010111011000100000000000000101;
r 0101 1 101011 1 1 1 1000100000000000000101 ;
r 010111010111011000100000000000000101J
r
r
r
r
r
F'
F'
r
F'
r
r
r
010111010111011000100000000000000001;
010111010111111000i00000000000000001;
010111010111011000100000000000000001;
010111010111111000100000000000000001;
010011010111011000100000000000000001;
010011010111011000100000000000000101J
0100110101110110001000000000001'300001;
010011010111011000100000000000000101;
010011010111011000100000001'3000000001;
010011010111011000100000000000000101J
010011010111011000100000000000000001;
0100110101110110001000000001'300000101;
r 010011010111011000100000000000000001;
r 010011010111011000100000000000000101;
r 010011010111011000100000000000000001;
r 010011010111011000100000000000000101;
F' 010011010111011000100000000000000001;
r 010011010111011000100000000000000101;
r 010011010111011000100000000000000001;
F' 010011010111011000100000000000000101;
r 010011010111011000100000000000000001;
r 010011010111011000100000000000000101;
F' 010011010111011000100J00000000000001;
r 010110101111011100100000000000001001;
r 010110101111011000100000000000000001;
F' 010110101101011000100000000000000001;
r 010011010101011000100000000000000001;
F' 010111101111011100100000000000001001;
F' 010111101111011000100000000000000001;
r 010011010101011000100000000000000001;
r 010101100101011100100000000000001001;
r 010101100101011000100000000000000001;
r 010011010101011000100000000000000001;
r 010111101111011100100000000000001001;
r 010111101111011000100000000000000001;
~ET F' 010011010011011000100000000000000001;
SET F' 010110010001111100100000000000000011;
010110010001011100100000000000000011;
~·.~·ET r
SET M (60:0); SET R (35:0);
SET o (60:0);
REM
PARAMETER TEST SEQUENCE;
DCL LEAKAGEIVrllrCIVOLTSIIPINIVOLTS1IVOLTS2ILEAKIILEAK2;
SET D (18:1)0<17:1);
FORCE E 1 -20.0;
Figure 4-5. (Cont.)
4-30
Section IV
Sentry 400
000501
000502
000503
;)00504
000505
000506
000510
000512
000514
0130516
000520
000522
000524
000525
000527
000531
0'10533
000535
'100537
000541
000 S'13
000545
000547
000551
000553
\~00555
000557
000561
000563
000564
000565
000567
000571
000573
000574
,"; ! '\
-,~)
,;;1('i) 76
l''\(;f';S77
(1(~0600
000602
0006(13
0(10604
00"~ 605
000606
C~00610
klD0611
1,100612
000613
000614
~:)0061 5
(j00616
000620
000621
000622
F'ORCE E0 0J
SET F' (37:0);
SET S (37:0);
VF'=-6.3;
LEAKAGE =-100E-9;
IPIN=17; CALL NLEAK;
IPIN=IS; CALL NLEAKJ
IPIN=22; CALL NLEAKJ
IPIN=23; CALL NLEAK;
IPIN=24J CALL NLEAKJ
IPIN=25J CALL NLEAKJ
IPIN=26J CALL NLEAK;
LEAKAGE=-500E-9;
IPIN=27; CALL NLEAK;
IPIN=28J CALL NLEAKJ
IPIN=29; CALL NLEAKJ
IPIN=30; CALL NLEAKJ
IPIN=31; CALL NLEAKJ
IPIN=32J CALL NLEAK;
IPIN=33; CALL NLEAKJ
IPIN=3SJ CALL NLEAKJ
IPIN=3
CALL NLEAKJ
IPIN=5 J CALL NLEAKJ
IPIN=6 J CALL NLEAKJ
IPIN=10; CALL NLEAKJ
IPIN=II; CALL NLEAKJ
IPIN=13; CALL NLEAK;
IPIN=21J CALL NLEAKJ
SET D 11(9:0)1(23:0)1;
SET F' 1(10:0)1(24:0);
IPIN=7; CALL NLEAKJ
IPIN=8J CALL NLEAK;
IPIN=9 J CALL NLEAKJ
F' OR CE EA 1 - 6 .3 J
F'ORCE EA0 01
SET [) [3531;
SET S [3511 I;
SET F (35 J1 1 ;
IPIN= 16; CALL NLEAKJ
SET D (18:1)0(17:1);
SET S (37: 0) ;
SET F' (37:0);
LEAKAGE = -100E-9)
IPIN=20J CALL NLEAK;
F' OR CEEl - 1 1 • 8 ;
F'ORCE EA 1 -6.3;
FORCE EAO 0 J
SET S (34:0) 10;
SET F 1(10:0)1(22:13)10;
LEAKAGE=-500E-9J
IPIN=4JCALL NLEAKJ
SET D 11(9:0)1(22:0>11;
SET S (34:0)111
SET F' 1(10:0)1(22:0)11;
Figure 4-5. (Cont.)
4-31
Sentry 400
Section IV
000623
000624
000625
000627
000630
000631
000632
000634
000635
000636
000637
000640
000641
000643
000644
000645
000646
000647
000650
000652
000653
000654
000655
000656
000657
000661
000662
000663
000665
000666
000667
000670
000672
000673
000675
000677
000701
000703
000704
000706
000710
000712
000714
000716
000720
000722
000724
000726
000730
000732
000734
000736
000740
000741
IfC=0J
VOL TS=-6.0 5.1
IPIN=14J CALL THRESHMINJ
SET 0 (33)1[35)0;
SET S (3311 .I
SET f (33)IJ
IPIN=15J CALL THRESHMINJ
SET 0 110011(3:0)(3:1)(23:0)1;
SET S (4:0)11(4:0)1(24:0)IJ
SET f (4:0)11(4:0)11(23:0)1;
LEAKAGE=-120E-6J
Vf=-6.3J
IPIN=36; CALL ZLEAK;
SET 0 C13Jl [35JIJ
SET S (13Jl[35JIJ
SET F' Cl J 1 Cl 3 J 1 [35 J 1 ;
LEAKAGE=-1.5E-3)
Vf=-6.3;
IPIN=36J CALL YLEAKJ
SET 011(33:0)1;
SET S (35:0)1;
SET f (35:0)1;
LEAKAGE=-100E-9;
Vr=-11.8;
IPIN=12J CALL NLEAK;
LEAKAGE =-1 .0£ -3;
Vr = -1 1 .8.1
IPIN=IJ CALL ZLEAKJ
SET D 11(9:0)1(23:0)1;
SET S (35:0)1;
SET r (11:0) 1 (23:0) 11
LEAKl=29.0E-6JLEAK2=11.0E-6;
Vr=-0.8J
IPIN=35J CALL WLEAK;
IPIN=5; CALL WLEAK;
IPIN=6J CALL WLEAK;
IPIN=10;
CALL WLEAKJ
SET r [1 J 1 J
IPIN=11; CALL WLEAK;
IPIN=31J CALL WLEAK;
IPIN=32J CALL WLEAK;
IPIN=20; CALL WLEAKJ
IPIN=21J CALL WLEAKJ
IPIN=27; CALL WLEAKJ
IPIN=28J CALL WLEAKJ
IPIN=29; CALL WLEAKJ
IPIN=30J CALL WLEAKJ
IPIN=3 J CALL WLEAK;
LEAK1=60.0E-6; LEAK2=22.0E-6;
IPIN=13J CALL WLEAK;
IPIN=33J CALL WLEAK;
LEAKl=80.0E-6; LEAK2=35.0E-6J
SET D [35Jl J
SET S [35Jl;
Figure 4-5. (Cont.)
4-32
Section IV
Sentry 400
000742
000743
000745
000747
000750
000751
000752
000754
000755
000757
0210761
000762
000763
000764
000765
000766
000767
000770
000774
000776
001000
001002
001004
001006
001010
001012
001014
001016
001017
001021
001022
001023
001026
001030
001032
001034
001036
001040
001042
001043
001045
001047
001050
001053
001055
001057
001061
001063
001065
001067
001071
001073
001074
001075
SET F' (35ll J
IPIN=14J CALL WLEAKJ
IPIN=15J CALL WLEAKJ
SET 0 11001(4:0)101(4'0)110(13:1)0011J
SET S (4:0)1(29:0)IIJ
SET F' 1(3:0)1(6:0)1(2210)IIJ
VOLTS1=-0.15J VOLTS2=-0.7J
IF'C=-100E-6J
IPIN=7; CALL WTHRESHJ
IPIN =9J CALL WTHRESH;
FORCE El -6.3J
FOR CE EA 1 - 1 1 .8;
F'ORCE E0 0J
F'ORCE EA0 0J
SET 0 (3:1)0(2:1)(3:0)(4:1)(3:0)(2:1)0(14:1)011;
SET S 1(10:0)1(24:0);
SET F' 10101(4:0)(4:1)(19:0)1001J
SET F' (1310~(1311~(1310~
C1 311 ~ C13 J0 ~
(1311~(13J0~
[1311'~(1310~
( 1 3 J 1 ~.[ 1 3 10 ~
(13Jl~(1310~
CI3ll~[1310~
[1311~CI310~
[1311~[13J0~[13JIJ
VOLTS1=-77E-3JVOLtS2=-210E-3J
IFC=-100E-6J
IPIN=4J CALL WTHRESHJ
SET F [13J0(34J1J
SET 0 (3411J ,
SET F (3410~[3411~
[3410~[34Jl"
(34l0"[34l1,,
[3410"[34l1,,
[34J0,,[34Jl~
[34l0~(34Jl~
[34l0~(3411~
(34l0~[3411J
VOLTS1=-0.15J VOLTS2=-0.7;
IPIN=16JCALL WTHRESHJ
SET F [10l0J
SET F (3410"(34]1,,
[3410~ (34ll"
[3410"[3411,,
[3410"[3411,,
(3.l110"(3.l1l1,,
(3410~ (3411"
[3410"(3411,,
(3.l110"(3.l1ll,,
(3410"[3.l111,,
[3410,,(3411J
VOLTS=-0.55J
IF'C =0 J
Figure 4-5. (Cant.)
4-33
Section IV
001076
1301 100
001101
001 104
001 106
001 1 10
130 1 1 12
1301 1 1 4
1301 1 1 5
1301117
1301121
1301124
1301 125
1301 126
001 130
001 1 31
1301 131
001 1 31
001132
001133
1301134
001 135
1301136
1301 137
1301 1 40
1301 1 41
001 141
001141
0131141
001 142
001143
1301 144
0131145
13131146
1301147
001 1 513
0131 1 51
13131 1 52
1301152
1313 1 152
0011 52
0131153
0131154
1301155
0011 56
0131157
0011613
1301 161
1301162
001 163
0131163
13131163
13131163
001 164
Sentry 400
IPIN=15JCALL THRESHMAXJ
SET P (10JIJ
'
SET P (34J0~t34Jl,
(34J0~(34Jl~
(34J0~[34Jl~
[34J0~(34Jl~
(34JeJ~[34Jl~
[34J0~[3411J
IPIN=14JCALL THRESHMAXJ
SET P [34Jf2J~(13]IJ
SET P [13J0,(13Jl~
(13J0~[13Jl;
IPC=-100E-6J
IPIN=8;CALL WTHRESH;
GOTOABORT J
SUBR WTHRESH;
SET PMU SENSE~ RNG2;
CPMU PIN IPINJ
SET DELAY 20E-3~ DC;
PORCE CURRENT IPC~RNGl;
ENABLE DCTI GT VOLTSIJ
ENABLE DCT0 LT VOLTS2;
MEASURE VALUE;
PORCE PMU 0;
END J
SUBR WLEAK;
SET PMU SENSE~ RNG1;
CPMU PIN IPIN;
SET DELAY 20E-3~ DCJ
PORCE VOLTAGE VPJ
ENABLE DCTI GT LEAKl;
ENABLE DCT0 LT LEAK2;
MEASURE VALUEJ
PORCE PMU 0J
XPMU PINJ
END;
SUBR NLEAKJ
DISABLE DCTI;
SET PMU SENSE~ RNG0;
CPMU PIN IPINJ
SET DELAY l00E-3~ DC;
PORCE VOLTAGE VFJ
ENABLE DCTeJ LT LEAKAGE;
MEASURE VALUE;
PORCE PMU 0;
XPMU PI NJ
END;
SUBR ZLEAKJ
o I SABLE DCTI J
SET PMU SENSE~ RNGl;
Figure 4-5. (Cant.)
4-34
Section IV
Sentry 400
.,
001165
001166
001 167
0011 70
0011 71
001 1 72
001173
12h31174
001174
001 174
001 174
001175
00 1 1 76
001177
001200
001201
001202
001203
001204
001205
001205
001205
001205
001206
001207
001210
001211
0'?J 1212
001213
001214
001215
001216
001216
001216
001216
001217
001220
001221
001222
001223
001224
001225
001226
001227
~j(3122 7
001227
001230
CPMU PIN IPINJ
SET DELAY 20E-3, DCJ
FORCE VOLTAGE VfJ
ENABLE DCT0 LT LEAKAGE;
MEASURE VALUEJ
FORCE PMU 0 J
XPMU PIN;
END;
SUBR THRESHMI NJ
DISABLE DCTl;
SET PMU SENSE, RNG2J
CPMU PIN IPIN;
SET DELAY 20E-3, DC;
FORCE CURRENT IFC, RNGIJ
ENABLE OCT0 GT VOLTS;
MEASURE VALUE;
FORCE PMU 0;
XPMU PI NJ
END;
SUBR THRESHMAXJ
DISABLE DCTIJ
SET PMU SENSE, RNG2;_
CPMU PIN IPIN;
SET DELAY 20E-3, DC;
FORCE CURRENT IfC, RNGIJ
ENABLE DCT0 LT VOLTS;
MEASURE VALUEJ
FORCE PMU 0 J
XPMU PINJ
END;
SUBR YLEAKJ
DISABLE DCTl;
SET PMU SENSE, RNG2J
CPMU PIN IP I NJ
SET DELAY 20E-3, DC;
fORCE VOLTAGE VFJ
ENABLE DCT0 LT LEAKAGE;
MEASURE VALUE;
FORCE PMU 0;
XPMU PINJ
ENDJ
MSSAGE:
ABORT:
WRITE
ENDJ
'ATTACHED LINES EQUAL OPEN PINS
Source Exif Data:
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Modify Date : 2011:01:02 16:59:46-08:00
Metadata Date : 2011:01:02 16:59:46-08:00
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