68X2537_XT286_Technical_Reference_Aug86 68X2537 XT286 Technical Reference Aug86

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---- -- -

- ----------,-

-

Personal Computer
Hardware Reference
Library

Technical
Reference

First Edition (August 1986)
The following paragraph does not apply to the United Kingdom or any country
where such provisions are inconsistent with local law: INTERNATIONAL
BUSINESS MAClllNES CORPORATION PROVIDES THIS PUBLICATION
"AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR
IMPLIED, INCLUDING, BUT NOT LIMII'ED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
PARTICULAR PURPOSE. Some states do not allow disclaimer of express or
implied warranties in certain transactions, therefore, this statement may not
apply to you.
This publication could include technical inaccuracies or typographical errors.
Changes are periodically made to the information herein; these changes will be

incorporated in new editions of the publication. IBM may make improvements
and/or changes in the product(s) and/or the program(s) described in this
publication at any time.
It is possible that this publication may contain reference to, or information
about, IBM products (machines and programs), programming, or services that
are not announced in your country. Such references or information must not be
construed to mean that IBM intends to announce such mM products,
programming, or services in your country.

Requests for copies of this publication and for technical information about IBM
Personal Computer products should be made to your authorized IBM Personal
Computer dealer or your IBM Marketing Representative.

© Copyright International Business Machines Corporation 1986

The following statement applies to all mM Personal Computer products unless otherwise
indicated by the information referring to that product.

FEDERAL COMMUNICATIONS COMMISSION RADIO
FREQUENCYENTERFERENCESTATEMENT
Warning: This equipment has been certified to comply with the
limits for a Class B computing device, pursuant to Subpart J of
Part 15 of FCC rules. Only peripherals (computer input/output
devices, terminals, printers, etc.) certified to comply with the
Class B limits may be attached to this computer when this
computer is operated in a residential environment. Operation
with noncertified peripherals is likely to result in interference to
radio and TV reception.
CAUTION
This product is equipped with a 3-wire power cord and plug for the
user's safety. Use this power cord in conjunction with a properly
grounded electrical outlet to avoid electrical shock.

iii

Notes:

iv

Preface

This manual describes the various units of the IBM Personal
Computer XT Model 286 and how they interact. It also has
information about the basic input/output system (BIOS) and
about programming support.
The information in this publication is for reference, and is
intended for hardware and program designers, programmers,
engineers, and anyone else who needs to understand the design
and operation of the IBM Personal Computer XT Model 286.
This manual consists of eight sections:
•
•
•
•
•
•

The first three sections describe the IBM Personal Computer
XT Model 286 including hardware, charts, and register
inforniation
Section 4 describes keyboard operation, the commands to and
from the system, and the various keyboard layouts.
Section 5 contains information about the usage of BIOS and a
system BIOS listing.
Section 6 contains instruction sets for the 80286
microprocessor and the 80287 math coprocessor.
Section 7 provides information about characters, keystrokes,
and colors.
Section 8 contains information about the compatibility of the
IBM Personal Computer XT Model 286 and the rest of the
IBM Personal Computer family.

A glossary, bibliography, and index are included.

v

Prerequisite Publications
Guide to Operations for the IBM Personal Computer XT Model

286
Suggested Reading
•

BASIC for the IBM Personal Computer

•

Disk Operating System (DOS)

•

Macro Assembler for the IBM Personal Computer

Additional Information
The Technical Directory lists all the service and technical
information that is available for the IBM Personal Computer
family of products. To receive a free copy of the Technical
Directory, call toll free 1-800-IBM-PCTB, Mop.day through
Friday,8:00a.m. to 8:00 p.m. EastemTime.

vi

Contents

SECTION 1. SYSTEM BOARD •••..•.•••••••••••••• 1-1
Memory ..................................... 1-4
Microprocessor ................................ 1-4
System Performance ............................ 1-7
System Memory Mapping ........................ 1-8
Direct Memory Access .......................... 1-9
System Interrupts ............................. 1-12
Hardware Interrupt Listing ................... 1-13
Interrupt Sharing ... . . . . . . . . . . . . . . . . . . . . . . .. 1-14
System Timers ............................... 1-22
System Clock ................................ 1-23
ROM Subsystem .............................. 1-23
RAM Subsystem .............................. 1-24
1/0 Channel ................................. 1-24
Connectors ............................... 1-25
I/O Channel Signal Description ............... 1-31
I/O Addresses ............................ 1-38
Other Circuits ................................ 1-43
Speaker .................................. 1-43
128K RAM Jumper (110) .................... 1-43
Display Switch ............................ 1-44
Keyboard Controller ........................ 1-44
Real-Time Clock CMOS RAM Information ...... 1-59
Specifications ................................ 1-72
System Unit .............................. 1-72
Connectors ............................... 1-74
Logic Diagrams ............................ 1-77
SECTION 2. COPROCESSOR ••...••••••.•.•••....
Description ...................................
Programming Interface ..........................
Hardware Interface .............................

2-1
2-3
2-3
2-4

SECTION 3. POWER SUPPLY ....•••••••.•.••••...
Inputs .......................................
Outputs ......................................
DC Output Protection ..........................

3-1
3-3
3-3
3-4

vii

Output Voltage Sequencing ......................
No-Load Operation ............................
Power-Good Signal .............................
Connectors ...................................

3-4
3-4
3-4
3-6

SECTION 4. KEYBOARD ......................... 4-1
Description ................................... 4-3
Power-On Routine .......................... 4-5
Commands from the System ................... 4-6
Commands to the System .................... 4-13
Keyboard Scan Codes ....................... 4-15
Clock and Data Signals ...................... 4-27
Keyboard Encoding and Usage ................ 4-30
Keyboard Layouts ......................... 4-40
Specifications ............................. 4-47
Logic Diagram ............................ 4-48

SECTION 5. SYSTEM BIOS .•.•.....•.••.••.•••... 5-1
System BIOS Usage ............................ 5-3
Quick Reference .............................. 5-14
SECTION 6. INSTRUCTION SET ••••..••.....•.•... 6-1
80286 Instruction Set ........................... 6-3
Data Transfer .............................. 6-3
Arithmetic .......... . . . . . . . . . . . . . . . . . . . . . .. 6-6
Logic ..................................... 6-9
String Manipulation ........................ 6-11
Control Transfer ........................... 6-13
Processor Control .......................... 6-17
Protection Control ......................... 6-18
80287 Coprocessor Instruction Set ................ 6-22
Data Transfer ............................. 6-22
Comparison .............................. 6-23
Constants ................................ 6-24
Arithmetic ................................ 6-25
Transcendental ............................ 6-26
SECTION 7. CHARACTERS, KEYSTROKES, AND
COLORS ...................................... 7-1
Character Codes ............................... 7-3
Quick Reference .............................. 7-14

viii

SECTION 8. mM PERSONAL COMPUTER
COMPATIBILITY ............................... 8-1
Hardware Considerations ........................ 8-3
System Board .............................. 8-3
Fixed Disk Drive ............................ 8-5
Diskette Drive Compatibility .................. 8-5
Copy Protection ............................ 8-5
Application Guidelines .......................... 8-7
High-Level Language Considerations ............ 8-7
Assembler Language Programming Considerations . 8-8
Multitasking Provisions ...................... 8-15
Machine-Sensitive Code ..................... 8-19

Glossary

...................................... . X-I

Bibliography ....................................

X-37

Index .........................................

X-39

ix

Notes:

/:

l',

x

INDEX TAB LISTING
Section 1: System Board ............................... .

Section 2: Coprocessor ................................ .

Section 3: Power Supply ............................... .

Section 4: Keyboard .................................. .

Section 5: System BIOS ............................... .

Section 6: Instruction Set
xi

Notes:

xii

Section 7: Characters, Keystrokes, and Colors .............. .

Section 8: Compatibility ............................... .

Glossary ........................................... .

Bibliography ........................................ .

Index .............................................. .

xiii

System Block Diagram
System Unit
Power Supply
115/230

System Board
80286-6
Microprocessor

80287
Coprocessor

Osc i llator

16 Interrupt
Levels

ROM

Speaker
Connector

Speaker

7 Channel
DMA

RAM

Keyboard
Controller

Keyboard

CMOS RAM

Rea I -Time
Clock

Battery
Connector

Battery

I/O
Channel

O~-' - - '--

r--

-DO

- -Adapters

xiv

I

Fixed
Disk
Drive

I

Diskette
Drives

I

Fixed Disk and
Diskette Adapter

I

SECTION 1. SYSTEM BOARD

Memory ..................................... 1-4
Microprocessor ................................ 1-4
Real Address Mode ...................... 1-4
Protected (Virtual Address) Mode ........... 1-5
System Performance ............................ 1-7
System Memory Mapping ........................ 1-8
Direct Memory Access .......................... 1-9
System Interrupts ............................. 1-12
Hardware Interrupt Listing ................... 1-13
Interrupt Sharing ..... . . . . . . . . . . . . . . . . . . . . .. 1-14
Design Overview .. . . . . . . . . . . . . . . . . . . . . .. 1-14
Program Support ........................ 1-15
Precautions ............................ 1-17
Examples ............................. 1-18
System Timers ............................... 1-22
System Clock ................................ 1-23
ROM Subsystem .............................. 1-23
RAM Subsystem .............................. 1-24
I/O Channel ................................. 1-24
Connectors ............................... 1-25
I/O Channel Signal Description ............... 1-31
1/a Addresses ............................ 1-38
NMI Controls .......................... 1-39
I/O Port (Read/Write) .................. 1-40
Diagnostic-Checkpoint Port ............... 1-42
Coprocessor Controls .................... 1-42
Other Circuits ................................ 1-43
Speaker .................................. 1-43
128K RAM Jumper (110) .................... 1-43
Display Switch ............................ 1-44
Keyboard Controller ........................ 1-44
Keyboard Controller Initialization .......... 1-45
Receiving Data from the Keyboard .......... 1-45
Scan Code Translation ................... 1-46
Sending Data to the Keyboard ............. 1-53
Keyboard Controller System Interface ....... 1-53
Status Register ......................... 1-54

System Board

1-1

Status-Register Bit Definition ..............
Output Buffer ..........................
Input Buffer ...........................
Commands (I/O Address Hex 64) ..........
I/O Ports .............................
Real-Time Clock CMOS RAM Information ......
Real-Time Clock Information ..............
CMOS RAM Configuration Information .....
I/O Operations .........................
Specifications ................................
System Unit ..............................
Connectors ...............................
Logic Diagrams ............................

1-2

System Board

1-54
1-56
1-56
1-56
1-58
1-59
1-60
1-63
1-70
1-72
1-72
1-74
1-77

The system board is approximately 22 by 33.8 centimeters (8.5
by 13.2 inches). It uses very large scale integration (VLSI)
technology and has the following components:
•

Intel 80286 Microprocessor

•

System support function:
Seven-Channel Direct Memory Access (DMA)
Sixteen-level interrupt
Three programmable timers
System clock

•

64K read-only memory (ROM) subsystem, expandable to
128K.

•

A 640K (may be set to 512K) random-access memory
(RAM) subsystem

•

Eight input/output (I/O) slots:
Five with a 98-pin card-edge socket
. Three with a 62-pin card-edge socket

•

Speaker attachment

•

Keyboard attachment

•

Complementary metal oxide semiconductor (CMOS) memory
RAM to maintain system configuration

•

Real-Time Clock

•

Battery backup for CMOS configuration table and Real-Time
Clock

System Board

1-3

Memory
The system board consists of two 256K-by-9 random access
memory module packages, plus two banks of 64K-by-4 random
access memory (RAM) modules. Total memory size is 640K,
with parity checking.

Microprocessor
The Intel 80286 microprocessor has a 24-bit address, 16-bit
memory interfacel , an extensive instruction set, DMA and
interrupt support capabilities, a hardware fixed-point multiply and
divide, integrated memory management, four-level memory
protection, 10 (1,073,741,824 bytes) of virtual address space for
each task, and two operating modes: the 8086-compatible real
address mode and the protected virtual address mode. More
detailed descriptions of the microprocessor may be found in the
publications listed in the Bibliography of this manual.

Real Address Mode
In the real address mode, the microprocessor's physical memory is
a contiguous array of up to one megabyte. The microprocessor
addresses memory by generating 20-bit physical addresses.
The selector portion of the pointer is interpreted as the upper 16
bits of a 20-bit segment address. The lower 4 bits of the 20-bit
segment address are always zero. Therefore, segment addresses
begin on multiples of 16 bytes.
All segments in the real address mode are 64K in size and may be
read, written, or executed. An exception or interrupt can occur if
data operands or instructions attempt to wrap around the end of a
segment. An example of this is a word with its low-order byte at
offset FFFF and its high-order byte at 0000. If, in the real
In this manual, the term interface refers to a device that carries signals
between functional units.

1-4

System Board

address mode, the information contained in the segment does not
use the full 64K, the unused end of the segment may be overlayed
by another segment to reduce physical memory requirements.

Protected (Virtual Address) Mode
The protected mode offers extended physical and virtual memory
address space, memory protection mechanisms, and new
operations to support operating systems and virtual memory.
Note: See "BIOS Programming Hints" in Section 5 for
special cautions while operating in the protected mode.
The protected mode provides a 1G virtual address space for each
task mapped into a 16M physical address space. The virtual
address space may be larger than the physical address space,
because any use of an address that does not map to a physical
memory location will cause a restartable exception.
As in the real address mode, the protected mode uses 32-bit
pointers, consisting of 16-bit selector and offset components.
The selector, however, specifies an index into a memory resident
table rather than the upper 16 bits of a real memory address. The
24-bit base address of the desired segment is obtained from the
tables in memory. The 16-bit offset is added to the segment base
address to form the physical address. The microprocessor
automatically refers to the tables whenever a segment register is
loaded with a selector. All instructions that load a segment
register will refer to the memory-based tables without additional
program support. The memory-based tables contain 8-byte
values called descriptors.

System Board

1-5

The following is a block diagram of the system board.

1-6

System Board

System Performance
The 80286 microprocessor operates at 6 MHz, resulting in a clock
cycle time of 167 nanoseconds.
A bus cycle requires two clock cycles, making a 334-nanosecond
16-bit, microprocessor cycle time. Eight-bit bus operations to
8-bit devices take six clock cycles (which include four wait
states), resulting in a I-microsecond microprocessor cycle.
Sixteen-bit bus operations to 8-bit devices take 12 clock cycles
(which include 10 wait states) resulting in a 2-microsecond
microprocessor cycle.
The refresh controller steps one refresh address every 15
microseconds. Each refresh cycle requires eight clock cycles to
refresh all of the system's dynamic memory; 256 refresh cycles
are required every 4 milliseconds, but the system hardware
refreshes every 3.84ms. The following formula determines the
percentage of bandwidth used for refresh for the 6 MHz clock.

% Bandwidth used
for Refresh

8 cycles X 256

2048

3.84ms/167ns

22994

= -------------- = ----- = 9%

The DMA controller operates at 3 MHz, which results in a clock
cycle time of 334 nanoseconds. All DMA data-transfer bus
cycles are five clock cycles or 1.66 microseconds. Cycles spent in
the transfer of bus control are not included.

System Board

1-7

System Memory Mapping
The following shows the mapping of the system memory.
Address

Name

Function

000000 to
07FFFF

512K system
board m!!!mory

First 512K of system board memory

080000 to
OgFFFF

128K system
bOard memory

System board memory (512K to 640K)
May be disabled with jumper Jl0.

OAOOOO to
OBFFFF

128K video
RAM

Reserved for graphics display buffer

aCOaOO to
ODFFFF

128K 1/0
expansion ROM

Reserved for ROM on 1/0 adapters

OEOOOO to
OEFFFF

64K reserved
Oil system board

Duplicated code assignment at
address FEOOOO

OFOOOO to
OFFFFF

64K ROM on the
system board

Duplicated code assignment at
address FFOOOO

100000 to
FDFFFF

Maximum
memory 15M

1/0 channel memory - 640K to 15M
Installed on memory expansion options

FEOOOO to
FEFFFF

64K reserved
oli system board

Duplicated code assignment at
address OEOOOO

FFOOOO to
FFFFFF

64K ROM on the
system board

Duplicated code assignment at
address OFOOOO

System Memory

1-8

System Board

Direct Memory Access
The system supports seven direct memory access (DMA)
channels. Two Intel 8237 A-5 DMA Controller chips are used,
with four channels for each chip. The DMA channels are
assigned as follows:
Controller 1
Ch
Ch
Ch
Ch

0
1
2
3

-

Reserved
SDLC
Diskette
LAN

Controller 2
Ch
Ch
Ch
Ch

4 - Cascade for Ctlr 1

5 - Reserved
6 - Reserved
7 - Reserved

DMA Channels

DMA controller 1 contains channels 0 through 3. These channels
support 8-bit data transfers between 8-bit I/O adapters and 8- or
16-bit system memory. Each channel can transfer data
throughout the 16M system-address space in 64K blocks.
The following figures show address generation for the DMA
channels.
Source

DMA Page Registers

Controller

Address

A23<---------->A16

A15<---------->AO

Address Generation for DMA Channels 0 through 3

Note: The addressing signal, 'byte high enable' (BHE),
is generated by inverting address line AO.

System Board

1-9

DMA controller 1 command code addresses follow.
Hex
Address

Register Function

000
001
002
003
004
005
006
007

CHO
CHO
CHI
CHI
CH2
CH2
CH3
CH3

base
base
base
base
base
base
base
base

and
and
and
and
and
and
and
and

current
current
current
current

address
word count
address
word count
curr~nt address
current word count
current address
current word count

008
009
OOA
OOB
OOC
000
OOE
OOF

Read Status Register/Write Command Register
Write Request Register
Write Single Mask Register Bit
Write Mode Register
Clear Byte Pointer Flip-Flop
Read Temporary Register/Write Master Clear
Clear Mask Register
Write All Mask Register Bits

DMA Controller 1 (Channels 0-3)

DMA controller 2 contains channels 4 through 7. Channel 4 is
used to cascade channels 0 through 3 to the microprocessor.
Channels 5, 6, and 7 support 16-bit data transfers between 16-bit
I/O adapters and 16-bit system memory. These DMA channels
can transfer data throughout the 16M system-address space in
128K blocks. Channels 5, 6, and 7 cannot transfer data on
odd-byte boundaries.
Source

OMA Page Registers

Controller

Address

A23<---------->A17

A16<---------->Al

Address Generation for DMA Channels 5 through 7

Note: The addressing signals, BHE and AO, are forced to
a logical O.

1-10

System Board

The following figure shows the addresses for the page register.
I/O Hex Address

Page Register
OMA Channel
OMA Channel
OMA Channel
OMA Channel
OMA Channel
OMA Channel
OMA Channel
Refresh

0

0087
0083
0081
0082
008B
0089
008A
008F

I

2
3
5
6
7

Page Register Addresses

Addresses for all DMA channels do not increase or decrease
through page boundaries (64K for channels 0 through 3, and
128K for channels 5 through 7).
DMA channels 5 through 7 perform 16-bit data transfers. Access
can be gained only to 16-bit devices (I/O or memory) during the
DMA cycles of channels 5 through 7. Access to the DMA
controller, which controls these channels, is through I/O
addresses hex OCO through ODF.
DMA controller 2 command code addresses follow.
Hex
Address

Register Function

OCO
OC2
oc4
OC6
oc8
OCA
OCC
OCE

CH4
CH4
CH5
CH5
CH6
CH6
CH7
CH7

base
base
ba:oe
base
base
base
base
base

and
and
and
and
and
and
and
and

current
current
current
current
current
current
current
current

address
word count
address
word count
address
word count
address
word count

000
002
004
006
008
OOA
OOC
OOE

Read Status Register/Write Command Register
Write Request Register
Write Single Mask Register Bit
Write Mode Register
Clear Byte Pointer Flip-Flop
Read Temporary Register/Write Master Clear
Clear Mask Register
Write All Mask Register Bits

DMA Controller 2 (DMA Channels 4-7)

All DMA memory transfers made with channels 5 through 7 must
occur on even-byte boundaries. When the base address for these

System Board

1-11

channels is programmed, the real address divided by 2 is the data
written to the base address register. Also, when the base word
count for channels 5 through 7 is programmed, the count is the
number of 16-bit words to be transferred. Therefore, DMA
channels 5 through 7 can transfer 65,536 words, or 128Kb
maximum, for any selected page of memory. These DMA
channels divide the 16M memory space into 128K pages. When
the DMA page registers for channels 5 through 7 are
programmed, data bits D7 through D1 contain the high-order
seven address bits (A23 through A17) of the desired memory
space. Data bit DO of the page registers for channels 5 through 7
is not used in the generation of the DMA memory address.
At power-on time, all internal locations, especially the mode
registers, should be loaded with some valid value. This is done
even if some channels are unused.

System Interrupts
The 80286 microprocessor's non maskable interrupt (NMI) and
two 8259A controller chips provide 16 levels of system interrupts.
Note: Any or all interrupts may be masked (including the
microprocessor's NMI).

1-12

System Board

Hardware Interrupt Listing
The following shows the interrupt-level assignments in decreasing
priority.
Function

Level
Microprocessor NMI

Parity or I/O Channel Check

Interrupt Controllers
CTRL 1
CTRL 2
Timer Output 0
Keyboard (Output Buffer Full)
Interrupt from CTRL 2

IRQ 0
IRQ 1
IRQ 2 +IRQ 8
IRQ 9
IRQ
'- IRQ
IRQ
IRQ
IRQ
IRQ
IRQ 3

IRQ 4

IRQ 5
IRQ 6
IRQ 7

*

**
***
****

10
11
12
13
14
15

Realtime Clock Interrupt
Software Redirected to INT OAH
PC Network *
PC Network(Alt.) *
Reserved
Reserved
Reserved
Coprocessor
Fixed Disk Controller
Reserved
Ser ial Port 2
BSC
BSC (Alt.)
PC Network *
PC Network (Alt.) *
SDLC
Serial Port 1
BSC
BSC (Alt.)
SDLC
Parallel Port 2
Diskette Controller
Fixed Disk and Diskette Drive
Parallel Port 1
Data Acauisition and Control **
GPIB **'11
Voice Communications Adapter ****

The PC Network is jumper selectable.
The Data Acquisition Adapter can be set to interrupts
3 through 7. The default interrupt is 7.
The GPIB Adapter can be set to interrupts 2 through 7.
The Voice Communications Adapter can be set to
interrupts 2, 3, 4, or 7 (Interrupt level 7 is
recommended).

Hardware Interrupt Listing

System Board

1-13

Interrupt Sharing
A definition for standardized hardware design has been
established that enables multiple adapters to share an interrupt
level. This section describes this design and discusses the
programming support required.
Note: Since interrupt routines do not exist in ROM for
protected mode operations, this design is intended to run
only in the microprocessor's real address mode.

Design Overview
Most interrupt-supporting adapters hold the 'interrupt request'
line (IRQ) at a low level and then drive the line high to cause an
interrupt. In contrast, the shared-interrupt hardware design
allows IRQ to float high through pull-up resistors on each
adapter. Each adapter on the line may cause an interrupt by
momentarily pulsing the line to a low level. The high-to-low
transition arms the 8259A Interrupt Controller; the low-to-high
transition generates the interrupt. The duration of this pulse must
be between 125 and 1,000 nanoseconds.
The adapters must have an 'interrupt' status bit (INT) and a
'interrupt enable' bit (ENA) that can be controlled and
monitored by its software.
Each adapter sharing an interrupt level must monitor the IRQ
line. When any adapter drives the line low, all other adapters on
that line must be prevented from issuing an interrupt request until
they are rearmed.
If an adapter's !NT status bit is at a high level when the interrupt
sharing logic is rearmed, the adapter must reissue the interrupt.
This prevents lost interrupts if two adapters issue an interrupt at
the same time and an interrupt handler issues a Global Rearm
after servicing one of the adapters.

1-14

System Board

The following diagram is an example of the shared interrupt logic.
Q

1------1

+5

Q

-Q

>CLK

2.2K Ohms

-CLR

System
Clock--+----i-------'

">'--+-

IRQ

+5
Q

---I >CLK

L - -_ _

-Q
-CLR

-Global
Rearm---~-------'

Shared Interrupt Logic Diagram

Program Support
During multitasking, tasks are constantly being activated and
deactivated in no particular order. The interrupt-sharing program
support described in this section provides for an orderly means to:
•

Link a task's interrupt handler to a chain of interrupt handlers

•

Share the interrupt level while the task is active

•

Unlink the interrupt handler from the chain when the task is
deactivated.

Linking to a Chain
Each newly activated task replaces the interrupt vector in low
memory with a pointer to its own interrupt handler. The old
interrupt vector is used as a forward pointer (FPTR) and is stored
at a fixed offset from the new task's interrupt handler.

System Board

1-15

Sharing the Interrupt Level
When the new task's handler gains control as a result of an
interrupt, the handler reads the contents of the adapter's interrupt
status register to determine if its adapter caused the interrupt. If
it did, the handler services the interrupt, disables the interrupts
(eLI), issues a non-specific End of Interrupt (EOI), and then, to
rearm the interrupt hardware, writes to address 02FX, where X
corresponds to interrupt levels 3 through 7, and 9 (IRQ9 is
02F2). A write to address 06FX, where X may be 2 through 7, is
required for interrupt levels 10 through 15, respectively. Each
adapter in the chain decodes the address which results in a Global
Rearm. An adapter is required to decode the least significant 11
bits for this Global Rearm command. The handler then issues a
Return From Interrupt (IRET).
If its adapter did not cause the interrupt, the handler passes

control to the next interrupt handler in the chain.

Unlinking from the Chain
To unlink from the chain, a task must first locate its handler's
position within the chain. By starting at the interrupt vector in
low memory, and using the offset of each handler's FPTR to find
the entry point of each handler, the chain can be methodically
searched until the task finds its own handler. The FPTR of the
previous handler in the chain is replaced by the task's FPTR, thus
removing the handler from the chain.

Error Recovery
Should the unlinking routine discover that the interrupt chain has
been corrupted (an interrupt handler is linked but does not have a
valid SIGNATURE), an unlinking error-recovery procedure must
be in place. Each application can incorporate its own unlinking
error procedure into the unlinking routine. One application may
choose to display an error message requiring the operator to
either correct the situation or power down the system. Another
application may choose an error recovery procedure that restores
the original interrupt vector in low memory, and bypasses the
corrupt portion of the interrupt chain. This error recovery

1-16

System Board

procedure may not be suitable when adapters that are being
serviced by the corrupt handler are actively generating interrupts,
since unserviced interrupts lock up that interrupt level.
ROS Considerations

Adapters with their handlers residing in ROS may choose to
implement chaining by storing the 4 byte FPTR (plus the FIRST
flag if it is sharing interrupt 7 or 15) in on-adapter latches or
ports. Adapter ROS without this feature must first test to see
that it is the first in the chain. If it is the first in the chain, the
adapter can complete the link; if not, the adapter must exit its
routine without linking.

Precautions
The following precautions must be taken when designing
hardware or programs using shared interrupts:
•

Hardware designers should ensure the adapters:
Do not power up with the ENA line active or an interrupt
pending.
Do not generate interrupts that are not serviced by a
handler. Generating interrupts when a handler is not
active to service the adapter causes the interrupt level to
lock up. The design relies on the handler to clear its
adapter's interrupt and issue the Global Rearm.
Can be disabled so that they do not remain active after
their application has terminated.

•

Programmers should:
Ensure that their programs have a short routine that can
be executed with the AUTOEXEC.BAT to disable their
adapter's interrupts. This precaution ensures that the
adapters are deactivated if the user reboots the system.
Treat words as words, not bytes. Remember that data is
stored in memory using the Intel format (word 424B is
stored as 4B42).
System Board

1-17

Interrupt Chaining Structure
ENTRY:

PAST:

JMP
SHORT PAST
FPTR
DO
0
SIGNATURE OW
424BH
FLAGS
FIRST
JMP
RES- BYTES

DB
EQ.U
SHORT
DB

BOH
RESET
DUP 7 (0)

; Jump around structure
; Forward Pointer

;
;
;
;

Used when un link i n9 to i dent i fy
compatible interrupt handlers
Flags
Flag for being first in chain

; Future expansion

; Actual start of code

The interrupt chaining structure is a 16-byte format containing
FPTR, SIGNATURE, and RES BYTES. It begins at the third
byte from the interrupt handler'sentry point. The first
instruction of every handler is a short jump around the structure
to the start of the routine. Since the position of each interrupt
handler's chaining structure is known (except for the handlers on
adapter ROS), the FPTRs can be updated when unlinking.
The FIRST flag is used to determine the handler's position in the
chain when unlinking when sharing interrupts 7 and 15. The
RESET routine, an entry point for the operating system, must
disable the adapter's interrupt and RETURN FAR to the
operating system.
Note: All handlers designed for interrupt sharing must
use 424B as the signature to avoid corrupting the chain.

Examples
In the following examples, notice that interrupts are disabled
before control is passed to the next handler on the chain. The
next handler receives control as if a hardware interrupt had
caused it to receive control. Also, notice that the interrupts are
disabled before the non-specific EOI is issued, and not reenabled
in the interrupt handler. This ensures that the IRET is executed
(at which point the flags are restored and the interrupts
reenabled) before another interrupt is serviced, protecting the
stack from excessive build up.
II

q

1-18

System Board

Example of an Interrupt Handler
YOUR_CARD

EQ.U

xxxx

ISB

EQ.U

xx

REARM

EQ.U

2F7H

SPC_EOI

EQ.U

67H

EOI
OCR

EQ.U
EQ.U

20H
20H

IMR

EQ.U

21H

Location of your card's interrupt
control/status register
Interrupt bit in your card's Interrupt
control status register
Global Rearm location for interrupt
level 7
; Specific EOI for 8259's interrupt
level 7
Non-specific EOI
Location of 8259 operational control
register

Location of 8259 interrupt mask
register

MYCSEG

SEGMENT
ASSUME
PROC
JMP
FPTR
DO
SI GNATURE OW

ENTRY

FLAGS
FIRST
JMP
RES BYTES
PAST":

SERVICE:
EXIT:

RESET:
ENTRY

DB
EQ.U
SHORT
DB
STI
PUSH
MOV
IN
TEST
JNZ
TEST
JNZ
POP
CL I
JMP

PARA
CS: MYCSEG ,OS: DSEG
FAR
SHORT PAST

o

424BH

o

80H
RESET
DUP 7 (0)
OX, YOUR CARD
AL,DX AL,ISB
SERVICE
CS:FLAGS,FIRST
EXIT
DWORD PTR CS:FPTR

Entry point of handler
Forward Pointer
Used when un link i ng to i dent i fy
compatible interrupt handlers
Flags
; Future expans ion

; Actual start of handler code
; Save needed reg i sters
; Select your status register
Read the status register
Your card caused the interrupt?
Yes, branch to service logic
Are we the first ones in?
If yes, branch for EOI and Rearm
Restore registers
Disable interrupts
Pass control to next guy on chain
Serv i ce the inter rupt

CL I
MOV
OUT
MOV
OUT
POP
IRET
RET
ENDP
MYCSEG
END

AL,EOI
OCR,AL
OX ,REARM
DX,AL

Disable the interrupts
Issue non-specific EOI to 8259
Rearm the cards
Restore reg i sters
Disable your card

Return FAR to ope rat i ng system
ENDS
ENTRY

System Board

1-19

Linking Code Example
PUSH
ES
Cli
j Disable Interrupts
Set forward pointer to value of Interrupt vector In low memory
ASSUHE CS: CODESEG ,DS: CODESEG
PUSH
ES
HOV
AX, 350FH
DOS get Interrupt vector
INT
21H
HOV
SI ,OFFSET CS: FPTR
Get offset of your forward pointer
j
In an Indexable register
HOV
Store the old Interrupt vector
CS:ISI1,BX
CS: SI+21,ES
j
I n your forward po I nter for cha i n i ng
HOV
CHP
ES:BVTE PTR[BX1,CFH j Test for IRET
JNZ
SETVECTR
CS:FlAGS,FIRST
j Set up first in chain flag
HOV
SETVECTR: POP
ES
PUSH
DS
; Hake Interrupt vector In low memory point to your handler
HOV
DX,OFFSET ENTRV
Hake interrupt vector point to your handler
HOV
AX,SEG ENTRV
If DS not· CS, get It
HOV
DS,AX
and put it In DS
HOV
AX,250FH
DOS set Interrupt vector
INT
21H
POP
DS
Unmask (enable) Interrupts for your level
IN
Al,lHR
Read Interrupt mask register
$+2
JHP
j 10 delay
AND
Al,07FH
j Unmask Interrupt level 7
OUT
IHR,Al
j Wr I te new I nterrupt mask
HOV
; Issue specific EOI for level 7
. to allow pending level 7 interrupts
JHP
OCR,Al
OUT
(If anyl to be serviced
Enable Interrupts
STI
POP
ES

1-20

System Board

Unlinking Code Example
PUSH
OS
ES
PUSH
Cli
MOV
AX,350FH
INT
2lH
MOV
CX,ES
Are we the first handler In the chain?
MOV
AX,CS
CHP
8X ,OFFSET ENTRY
JNE
CHP

UNCHAIN A
AX,CX -

01 sab I e Inter rupts
DOS get Interrupt vector
ES:8X points to first of chain
Pickup segment part of Interrupt vector
Get code seg Into comparable register
Interrupt vector In low memory
pointing to your handler's offset?
j
j

j

No, branch
Vector pointing to your
hand ler' s segment?

JNE
UNCHAIN A
j No, branch
Set Interrupt vector In lOW memory to point to the handler
po I nted to by your po Inter
PUSH
MOV
HOV
HOV
INT
POP
JMP
UNCHAI N_A: CHP

JNE
lOS
CMP
JNE
HOV
CHP

OS
DX,WORD PTR CS:FPTR
OS ,WORD PTR CS FPTR[2]
AX,250FH
j DOS set Interrupt vector
2lH
OS
UNCHA I N_X
8X • FPTR offset, ES • FPTR segment, CX • CS
ES: [8X+6] ,4842H
j I shand ler us I ng the appropr I ate
j
conventions (Is SIGNATURE present In
j
the Interrupt chaining structure)?
except Ion
j No, Invoke error exception handler
SI,ES:[8X+2]
j Get FPTR's segment and offset
S I ,OFFSET ENTRY
j Is this forward pointer pointing to
j
your handler's offset?
UNCHAIN 8
CX,DS AX,CX

j
j

j

No, branch
Hove to compare
Is this forward pointer pointing to
your handler's segment?

JNE
UNCHAI N 8
j No, branch
located your handler In tl1e chain
HOV
AX,WORD PTR CS:FPTR j Get your FPTR' s offset
HOV
ES:[8X+2],AX
j Replace offset of FPTR of handler
j
that points to you
HOV
AX,WORD PTR CS:FPTR[2] j Get your FPTR's segment
HOV
ES:[8X+4],AX
j Replace segment of FPTR of handler
j
that points to you
HOV
Al,CS:FlAGS
j Get your flags
AND
Al,FIRST
j Isolate FIRST flag
OR
ES:[8X + 6],Al
j Set your first flag Into prior routine
JHP
UNCHAIN_X
UNCHA I N_B: HOV
PUSH
PUSH

8X,SI
OS
ES

JMP
UNCHAIN_X: STI
POP
POP

UNCHAI N_A

j

Hove new offset to 8X

Examine next handler In chain
Enable Interrupts

ES
OS

System Board

1-21

System Timers
The system has three programmable timer/counters, Channels 0
through 2. They are controlled by an Intel 8254-2
Timer/Counter chip, and are defined as follows:
Channel 0

System Timer

GATE 0
CLKINO
CLKOUTO

Tied on
1.193182 MHz OSC
8259AIRQ 0

Channell

Refresh Request Generator

GATE 1
CLKIN 1
CLKOUT 1

Tied on
1.193182 MHz OSC
Request refresh cycle

Note: Channell is programmed as a rate generator to
produce a 15-microsecond period signal.
Channel 2

Tone Generation for Speaker

GATE 2
CLKIN2
CLK OUT 2

Controlled by bit 0 of port hex 61, PPI bit
1.193182 MHz OSC
Used to drive the speaker

The 8254-2 Timer/Counter is a programmable interval
timer/counter that system programs treat as an arrangement of
four external I/O ports. Three ports are treated as counters; the
fourth is a control register for mode programming. The following
is a system-timer block diagram.

1-22

System Board

+5 Vdc
-Refresh

System Bus ---+
,....-

+5 Vdc

D Q
Clock
L - Clear
Gate 0
Clock In 0
Gate 1

f-- Clock In 1
I/O Add ress
Hex 006 1 - r-- Gate 2
Port Bi t 0
f-- Clock In 2

IRQ 0

Clock Out 0
Clock Out 1 f-Clock Out 2
I/O Add ress
Hex 006 1
Port Bi t 1
PC LK

(2 .38MHz)

Refresh Request

I Driver I

I I
AND

Divide
by 2

Low
---+ To Speaker
Pass
F i Iter

I

System-Timer Block Diagram

System Clock
The 82284 System Clock Generator is driven by a 12-MHz
crystal. Its output 'clock' signal (CLK) is the input to the system
microprocessor and the I/O channel.

ROM Subsystem
The system board's ROM subsystem consists of two 32K by 8-bit
ROM/EPROM modules in a 32K-by-16-bit arrangement. The
code for odd and even addresses resides in separate modules.
ROM is assigned at the top of the first and last 1M address space
(OFOOOO and FFOOOO). ROM is not parity-checked. Its
maximum access time is 170 nanoseconds and its maximum cycle
time is 333 nanoseconds.

System Board

1-23

RAM Subsystem
The system board's RAM subsystem starts at address 000000 of
the 16M address space and consists of 640K of read/write
(R/W) memory. The 640K memory is composed of two
256K-by-9 random access memory module packages (512K), plus
two banks of 64K-by-4 RAM modules (128K). The 64K-by-4
RAM modules may be disabled at jumper no, located on the
system board. Memory access time is 150 nanoseconds and the
cycle time is 275 nanoseconds.
Memory refresh requests one memory cycle every 15
microseconds through the timer/counter (channell). The RAM
initialization program performs the following functions:
•

Initializes channell of the timer/counter to the rate
generation mode, with a period of 15 microseconds

•

Performs a memory write operation to any memory location.
Note: The memory must be accessed or refreshed eight
times before it can be used.

I/O Channel
The I/O channel supports:
•

I/O address space hex 100 to hex 3FF

•

24-bit memory addresses (16M)

•

Selection of data accesses (either 8- or 16-bit)

•

Interrupts

•

DMA channels

•

I/O wait-state generation

•

Open-bus structure (allowing multiple microprocessors to
share the system's resources, including memory)

•

Refresh of system memory from channel microprocessors.

1-24

System Board

Connectors
The following figure shows the location and the numbering of the
I/O channel connectors. These connectors consist of five 98-pin
and three 62-pin edge connector sockets.
Note:

The three 62-pin positions can support only 62-pin

II0 bus adapters.

I/O Channel
Connectors
Rear Panel

....
"")

('II
"")

M

"")

oq-

"")

It)
"")

co

"")

"'"

"")

IX)
"")

System Board

1-25

The following figure shows the pin numbering for the 62-pin I/O
channel connectors JI, 17 and J8.
Rear Panel

Bl

Al

Bl0

Al0

B20

A20

B3l

A3l
Component Side

I/O Channel Pin Numbering (J1, J7 and J8)

1-26

System Board

The following figure shows the pin numbering for the 98-pin I/O
channel connectors 12 through J6.
Rear Panel
Bl

Al

Bl0

Al0

B20

A20

B31

A31

01

C1

010

Cl0

018

C18
Component Side

I/O Channel Pin Numbering (J2-J6)

System Board

1-27

The following figures summarize pin assignments for the I/O
channel connectors.
I/O Pin

Signal Name

I/O

Al
A2
A3
A4
A5
A6
A7
A8
A9
AID
All
Al2
Al3
Al4
Al5
Al6
Al7
Al8
Al9
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31

-I/O CH CK
S07
S06
S05
so4
S03
S02
SOl
SOD
+1/0 CH ROY
AEN
SAl9
SAl8
SAl7
SAl6
SAl5
SAl4
SAl3
SAl2
SAil
SAID
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SAl
SAO

I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0

I/O Channel (A-Side)

1-28

System Board

I/O Pin

Signal Name

I/O

Bl
B2
B3
B4
B5
B6
B7
B8
B9
Bl0
Bll
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31

GND
RESET DRV
+5 Vdc
IRQ 9
-5 Vdc
DRQ2
-12 Vdc
OWS
+12 Vdc
GND
-SMEMW
-SMEMR
-lOW
-lOR
-DACK3
DRQ3
-DACKI
DRQl
-REFRESH
ClK
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
-DACK2
T/C
BALE
+5Vdc
14.318MHz OSC
GND

Ground
0
Power
I
Power
I
Power
I
Power
Ground
0
0
I/O
I/O
0
I
0
I
I/O
0
I
I
I
I
I
0
0
0
Power
0
Ground

I/O Channel (B-Side)

System Board

1-29

I/O Pin

Signal Name

I/O

C1
C2

-SBHE
LA23
LA22
LA21
LA20
LA19
LA18
LA17
-MEMR
-MEMW
5008
5009
5010
5011
5012
5013
5014
5015

/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0

~~

C5
C6
C7
C8
C9
Cl0
C11
C12
C13
C14
C15
C16
C17
C18

I/O Channel (C-Side, J2 through J6 only)
I/O Pin

Signal Name

I/O

01
02
03
04
05
06
07
08
09
010
011
012
013
014
015
016
017
018

-MEM CS16
-I/O CS16
IRQ10
IRQll
IRQ12
IRQ15
IRQ14
-OACKO
ORQO
-OACK5
ORQ5
-OACK6
ORQ6
-OACK7
ORQ7
+5 Vdc
-MASTER
GNO

I
I
I
I
I
I
I
0
I
0
I
0
I
0
I
POWER
I
GROUND

I/O Channel (D-Side, J2 through J6 only)

1-30 System Board

110 Channel Signal Description
The following is a description of the system board's I/O channel
signals. All signal lines are TTL compatible. 1/0 adapters should
be designed with a maximum of two low-power Shottky (LS)
loads per line and be capable of driving the data and address lines
similar to a 74LS245 driver.

SAO through SA19 (I/O)
Address signals 0 through 19 are used to address memory and

1/0 devices within the system. These 20 address lines, in

addition to LA 17 through LA23, allow access of up to 16M of
memory. SAO through SA19 are gated on the system bus when
'buffered address latch enable' signal (BALE) is high and are
latched on the falling edge of BALE. These signals are generated
by the microprocessor or DMA Controller. They also may be
driven by other microprocessors or DMA controllers that reside
on the I/O channel.

LA17 through LA23 (I/O)
These signals (unlatched) are used to address memory and I/O
devices within the system. They give the system up to 16M of
addressability. These signals are valid from the leading edge of
BALE to the trailing edge of the '-I/O Read' (-lOR) or '-I/O
Write' (-lOW) command cycle. These decodes should be latched
by I/O adapters on the falling edge of the 'buffered address latch
enable' signal (BALE).
These signals also may be driven by other microprocessors or
DMA controllers that reside on the 1/0 channel.

CLK(O)
This is the system 'clock' signal. It is a synchronous
microprocessor cycle clock with a cycle time of 167 nanoseconds.
The clock has a 50% duty cycle. This signal should be used only
for synchronization. It is not intended for uses requiring a fixed
frequency.

System Board

1-31

RESET DRV (0)

The 'reset drive' signal is used to reset or initialize system logic at
power-up time or during a low voltage condition. This signal is
active high.

SDO through SD15 (I/O)
These signals provide data bits 0 through 15 for the
microprocessor, memory, and I/O devices. DO is the
least-significant bit and D15 is the most-significant bit. All 8-bit
devices on the I/O channel should use DO through D7 for
communications to the microprocessor. The 16-bit devices will
use DO through D15. To support 8-bit devices, the data on D8
through D15 will be gated to DO through D7 during 8-bit
transfers to these devices; 16-bit microprocessor transfers to 8-bit
devices will be converted to two 8-bit transfers.
BALE (0) (buffered)

The 'buffered address latch enable' signal is available to the I/O
channel as an indicator of a valid microprocessor or DMA address
(when used with 'address enable' signal, AEN). Microprocessor
addresses SAO through SA19 are latched with the falling edge of
BALE. BALE is forced high (active) during DMA cycles. From
the trailing edge of a command cycle (for example, the trailing
edge of -lOR or -lOW) to the leading edge of BALE, the address
lines are in transition and are not stable.

-I/O CH CK (I)
The '-I/O channel check' signal provides the system board with
parity (error) information about memory or devices on the I/O
channel. When this signal is active (low), it indicates a
non-correctable system error.

1-32

System Board

I/O CH RDY (I)
The 'I/O channel ready' signal is pulled low (not ready) by a
memory or 1/0 device to lengthen I/O or memory cycles. Any
slow device using this line should drive it low immediately upon
detecting its valid address and a Read or Write command.
Machine cycles are extended by an integral number of clock
cycles (167 nanoseconds). This signal should be held low for no
more than 2.5 microseconds.

IRQ3-IRQ7, IRQ9-IRQ12, IRQ14, and IRQ15 (I)
Interrupt requests 3 through 7,9 through 12, 14, and 15 are used
to signal the microprocessor that an I/O device needs attention.
The interrupt requests are prioritized, with IRQ9 through IRQI2,
IRQI4, and IRQ15 having the highest priority (IRQ9 is the
highest), and IRQ3 through IRQ7 having the lowest priority
(IRQ7 is the lowest). An interrupt request is generated when an
IRQ line is raised from low to high. The line is high until the
microprocessor acknowledges the interrupt request (Interrupt
Service routine). See the figure on page 1-13 for additional
information.
Note: Interrupt requests IRQO-IRQ2, IRQ8, IRQ13 are
used on the system board and are not available on the I/O
channel.

-lOR (I/O)
The '-I/O read' signal instructs an I/O device to drive its data
onto the data bus. This signal may be driven by the system
microprocessor or DMA controller, or by a microprocessor or
DMA controller resident on the I/O channel. This signal is active
low.

-lOW (I/O)
The '-I/O write' signal instructs an I/O device to read the data
off the data bus. It may be driven by any microprocessor or
DMA controller in the system. This signal is active low.

System Board

1-33

-SMEMR (0) -MEMR (I/O)

These signals instruct the memory devices to drive data onto the
data bus. -SMEMR is active only when the memory decode is
within the low 1M of memory space. -MEMR is active on all
memory read cycles. -MEMR may be driven by any
microprocessor or DMA controller in the system. -SMEMR is
derived from -MEMR and the decode of the low 1M of memory.
When a microprocessor on the I/O channel wishes to drive
-MEMR, it must have the address lines valid on the bus for one
clock cycle before driving -MEMR active. Both signals are active
low.
-SMEMW (0) -MEMW (I/O)

These signals instruct the memory devices to store the data
present on the data bus. -SMEMW is active only when the
memory decode is within the low 1M of the memory space.
-MEMW is active on all memory write cycles. -MEMW may be
driven by any microprocessor or" DMA controller in the system.
-SMEMW is derived from -MEMW and the decode of the low
1M of memory. When a microprocessor on the I/O channel
wishes to drive -MEMW, it must have the address lines valid on
the bus for one clock cycle before driving -MEMW active. Both
signals are active low.

DRQO-DRQ3 and DRQ5-DRQ7 (I)
The 'DMA request' signals 0 through 3 and 5 through 7 are
asynchronous channel requests used by peripheral devices and a
microprocessor to gain DMA service (or control of the system).
They are prioritized, with DRQO having the highest priority and
DRQ7 the lowest. A request is generated by bringing a DRQ line
to an active (high) level. A DRQ line is held high until the
corresponding 'DMA acknowledge' (DACK) line goes active.
DRQO through DRQ3 perform 8-bit DMA transfers; DRQ5
through DRQ7 perform 16-bit transfers. DRQ4 is used on the
system board and is not available on the 110 channel.

1-34

System Board

-DACKO to -DACK3 and -DACK5 to -DACK7 (0)
-OMA acknowledge 0 through 3 and 5 through 7 are used to
acknowledge OMA requests. These signals are active low.

AEN (0)
The 'address enable' signal is used to degate the microprocessor
and other devices from the I/O channel to allow OMA transfers
to take place. When this line is active, the OMA controller has
control of the address bus, the data bus, Read command lines
(memory and I/O), and the Write command lines (memory and
I/O). This signal is active high.

-REFRESH (I/O)
This signal is used to indicate a refresh cycle and can be driven by
a microprocessor on the I/O channel. This signal is active low.

T/C (0)
The 'terminal count' signal provides a high pulse when the
terminal count for any OMA channel is reached.

-SHHE (I/O)
The 'system bus high enable' signal indicates a transfer of data
on the upper byte of the data bus, S08 through SOlS.
Sixteen-bit devices use -SBHE to condition data bus buffers tied
to S08 through SOlS. This signal is active low.

System Board

1-35

-MASTER (I)
This signal is used with a DRQ line to gain control of the system.
A processor or DMA controller on the I/O channel may issue a
DRQ to a DMA channel in cascade mode and receive a -DACK.
Upon receiving the -DACK, a microprocessor may pull
-MASTER active (low), which will allow it to control the system
address, data, and control lines (a condition known as tri-state).
After -MASTER is low, the microprocessor must wait one clock
cycle before driving the address and data lines, and two clock
cycles before issuing a Read or Write command. If this signal is
held low for more than 15 microseconds, the system memory may
be lost because of a lack of refresh.

-MEM CS16 (I)
The '-memory 16-bit chip select' signal indicates to the system
that the present data transfer is a 1 wait-state, 16-bit, memory
cycle. It must be derived from the decode of LA 17 through
LA23. -MEM CS16 is active low and should be driven with an
open collector or tri-state driver capable of sinking 20 rnA.

-I/O CS16 (I)
The '-I/O 16-bit chip select' signal indicates to the system that
the present data transfer is a 16-bit, 1 wait-state, I/O cycle. It is
derived from an address decode. -I/O CS16 is active low and
should be driven with an open collector or tri-state driver capable
of sinking 20 mA.

14.318MHz OSC(O)
The' 14.318MHz oscillator' signal is a high-speed clock with a
70-nanosecond period (14.31818 MHz). This signal is not
synchronous with the system clock. It has a 50% duty cycle.

1-36

System Board

OWS (I)
The 'zero wait state' signal tells the microprocessor that it can
complete the present bus cycle without inserting any additional
wait cycles. In order to run a memory cycle to a 16-bit device
without wait cycles, OWS is derived from an address decode gated
with a Read or Write command. OWS is active low and should be
driven with an open collector or tri-state driver capable of sinking
20mA.

System Board

1-37

I/O Addresses
The following describes the system board's I/O addresses.
Hex Range
000-01F
020-03F
040-05F
060
061
064
070-07F
080-09F
OAO-OBF
OCO-ODF
OFO
OFI
oF8-0FF
lFO-1F8
20C-20D
21F
278-27F
2BO-2DF
2El
2E2 & 2E3
2F8-2FF
300-31F
360-363
364-367
368-36B
36C-36F
378-37F
380-38F
3AO-3AF
3BO-3BF
3CO-3CF
3DO-3DF
3FO-3F7
3F8-3FF
6E2 & 6E3
AE2 & AE3
EE2 & EE3
22El
42El
62El
82El
A2El
C2El
E2El

Device
DMA Controller 1, 8237A-5
Interrupt Controller 1, 8259A, Master
Timer 8254-2
8042 (Keyboard)
System Board I/O port
8042 (Keyboard)
Real-Time Clock, NMI (Non-maskable Interrupt) Mask
DMA Page Register , 74LS612
Interrupt Controller 2, 8259A
DMA Controller 2, 8237A-5
Clear Math Coprocessor Busy
Reset Math Coprocessor
Math Coprocessor
Fixed Disk
Reserved
Voice Communications Adapter
Parallel Printer Port 2
Alternate Enhanced Graphics Adapter
GPIB (Adapter 0)
Data Acquisition (Adapter 0)
Serial Port 2
Prototype Adapter
PC Network (low address)
Reserved
PC Network (high address)
Reserved
Parallel Printer Port 1
SDLC, Bisynchronous 2
Bisynchronous 1
Monochrome Display and Printer Adapter
Enhanced Graphics Adapter
Color/Graphics Monitor Adapter
Diskette Controller
Serial Port 1
Data Acquisition (Adapter 1)
Data Acquisition (Adapter 2)
Data Acquisition (Adapter 3)
GPIB (Adapter 1)
GPIB (Adapter 2)
GPIB (Adapter 3)
GPIB (Adapter 4)
GPIB (Adapter 5)
GPIB (Adapter 6)
GPIB (Adapter 7)

Note: I/O Addresses, hex 000 to OFF, are reserved for the
system board I/O. Hex 100 to 3FF are available on the I/O
channel. The system board decodes up to 10 bits of I/O
address Information. I/O addresses above 3FF must not
conflict with the system board I/O addresses.

I/O Address Map

1-38

System Board

NMI Controls
During POST, the non-maskable interrupt (NMI) into the 80286
is masked off. The mask bit can be set and reset with system
programs as follows:
Mask On (Disable NMI)

Write to I/O address hex 070, with
data bit 7 equal to a logical 1.

Mask Off (Enable NMI)

Write to I/O address hex 070, with
data bit 7 equal to a logical O.

Note:

At the end of POST, the system enables NMI.

The '-I/O channel check' signal (-I/O CH CK) is used to report
noncorrectable errors on RAM adapters on the I/O channel.
This check creates an NMI if the NMI is enabled. During POST,
the NMI is masked off and -I/O CH CK is disabled. Follow
these steps when enabling -I/O CH CK and the NMI.
1. Write data in all I/O RAM-adapter memory locations; this
establishes good parity at all locations.

2. Enable -I/O CH CK.
3. Enable the NMI.
Note: All three of these functions are performed by
POST.
When a check occurs, an interrupt (NMI) results. Read the status
bits to determine the source of the NMI (see the figure, "I/O
Address Map" on page 1-38). To determine the location of the
failing adapter, write 'to any memory location within a given
adapter. If the parity check was from that adapter, -I/O CH CK
is reset to inactive.

System Board

1-39

I/O Port (Read/Write)
Address hex 061 is a read/write port on the system board.

Input (Read)
The following are the input (read) bit descriptions for this I/O
port.
Bit 7

+RAM Parity Check-System board memory parity
check.

o No memory parity check error has occurred.
1 A memory parity check error has occurred.
A non-maskable interrupt (NMI) will occur if
NMI is enabled. The error bit can be reset by
toggling. output port hex 061, bit 2, to a 1 and then
back to a O.
Bit 6

+I/O Channel Check-Error on an I/O channel
adapter (memory parity error or adapter errors).

o No I/O channel error has occurred.
1 An I/O channel error has occurred.
A non-maskable interrupt (NMI) will occur if
NMI is enabled. The error bit can be reset by
toggling output port hex 061, bit 3, to a 1 and then
back to a O.
Bit 5

Tinier 2 Channel Out-Reflects the level of the Timer
2 output.

Bit 4

Refresh Detect-Toggles every 15 microseconds,
indicating normal Refresh activity

Bits 3 to 0 Read the status of bits 3, 2, 1, and 0, respectively,
written to output port hex 061.

1-40

System Board

Output (Write)

The following are the output (write) bit descriptions for the
system board I/O port.
Bits 7 to 4 Not used
Bit 3

-Enable I/O Channel Check

o

Enables I/O Channel Check errors.

1 Disables I/O Channel Check errors.
During power-up this bit is toggled to ai, then
back to a 0, to clear the I/O channel check
flip-flop of previous errors.
Bit 2

-Enable System Board RAM Parity Check

o

Enables system board RAM parity check.

1 Disables system board RAM parity check.
During power-up this bit is toggled to ai, then
back to a 0, to clear the RAM parity check
flip-flop before BIOS checks the system memory
for parity errors.
Bit 1

+Speaker Data-Controls the speaker output (along
with Timer 2 Clock output).

Bit 0

+ Timer 2 Gate Speaker

o

Disables 8254 Timer 2 clock input (1.19 MHz).

1 Enables 8254 Timer 2 clock input (1.19 MHz).

System Board

1-41

Diagnostic-Checkpoint Port
I/O address hex 080 is used as a diagnostic-checkpoint port or
register. This port corresponds to a read/write register in the
DMA page register (74LS612). This port is used by POST during
power up.

Coprocessor Controls
The following is a description of the Math Coprocessor controls.
OFO An 8-bit Out command to port FO will clear the latched
Math Coprocessor' -busy' signal. The' -busy' signal will
be latched if the coprocessor asserts its' -error' signal while
it is busy. The data output should be zero.
OF1 An 8-bit Out command to port Fl will reset the Math
Coprocessor. The data output should be zero.

1-42

System Board

Other Circuits

Speaker
The system unit has a 2-1/4 inch permanent-magnet speaker,
which can be driven from:
•
•
•

The I/O-port output bit
The timer/counter's eLK OUT 2
Both of the above

128K RAM Jumper (JI0)
The system board has a three-pin, Berg-strip connector (110).
From the rear of the system to the front, the pins are numbered 1
through 3. Jumper placement across these pins determines
whether the last 128K RAM (512KB to 640KB) of system board
memory is enabled or disabled.
Pin

Assignments

1
2

No Connection
Ground
RAM Select

3
RAM Jumper Connector (J10)

With the jumper on pins 1 and 2, the 128K RAM is enabled.
When the jumper is on pins 2 and 3, the 128K RAM is disabled.
Note:

The normal mode is the enabled mode.

System Board

1-43

Display Switch
Set the slide switch on the system board to select the primary
display adapter. Its positions are assigned as follows:

On (toward the front of the system unit): The primary display
is attached to the Color/Graphics Monitor Adapter.
Off (toward the rear of the system unit): The primary display
is attached to the Monochrome Display and Printer Adapter.
The switch may be set to either position if the primary display is
attached to an Enhanced Graphics Adapter.
Note: The primary display is activated when the system
is powered on.

Keyboard Controller
The keyboard controller is a single-chip microcomputer (Intel
8042, or EPROM version 8742) that is programmed to support
the keyboard serial interface. The keyboard controller receives
serial data from the keyboard, checks the parity of the data,
translates scan codes, and presents the data to the system as a
byte of data in its output buffer. The controller can interrupt the
system when data is placed in its output buffer, or wait for the
system to poll its status register to determine when data is
available.
Data is sent to the keyboard by first polling the controller's status
register to determine when the input buffer is ready to accept data
and then writing to the input buffer. Each byte of data is sent to
the keyboard serially with an odd parity bit automatically
inserted. Since the keyboard is required to acknowledge all data
transmissions, another byte of data should not be sent to the
keyboard until acknowledgement is received for the previous byte
sent. The output-buffer-full interrupt may be used for both send
and receive routines.

1-44

System Board

Keyboard Controller Initialization
At power-on, the keyboard controller sets the system flag bit to O.
After a power-on reset or the execution of the Self Test
command, the keyboard controller disables the keyboard interface
by forcing the 'keyboard clock' line low. The keyboard interface
parameters are specified at this time by writing to locations within
the 8042 RAM. The keyboard-inhibit function is then disabled
by setting the inhibit-override bit in the command byte. A hex 55
is then placed in the output buffer if no errors are detected during
the self test. Any value other than hex 55 indicates that the 8042
is defective. The keyboard interface is now enabled by lifting the
'keyboard data' and 'keyboard clock' signal lines, and the system
flag is set to 1. The keyboard controller is then ready to accept
commands from the system unit microprocessor or receive
keyboard data.
The initialization sequence causes the keyboard to establish Mode
2 protocol (see "Data Stream" on page 4-27).

Receiving Data from the Keyboard
The keyboard sends data in a serial format using an II-bit frame.
The first bit is a start bit, and is followed by eight data bits, an
odd parity bit, and a stop bit. Data sent is synchronized by a
clock supplied by the keyboard. At the end of a transmission, the
keyboard controller disables the interface until the system accepts
the byte. If the byte of data is received with a parity error, a
Resend command is automatically sent to the keyboard. If the
keyboard controller is unable to receive the data correctly after a
set number of retries, a hex FF is placed in its output buffer, and
the parity bit in the status register is set to 1, indicating a receive
parity error. The keyboard controller will also time a byte of data
from the keyboard. If a keyboard transmission does not end
within 2 milliseconds, a hex FF is placed in the keyboard
controller's output buffer, and the receive time-out bit in the
status register is set. No retries will be attempted on a receive
time-out error.
Note: When a receive error occurs in the default mode
(bits 5, 6, and 7 of the command byte set to 0), hex 00 is
placed in the output buffer instead of hex FF. See

System Board

1-45

"Commands (I/O Address Hex 64)" on page 1-56 for a
detailed description of the command byte.

Scan Code Translation
Scan codes received from the keyboard are converted by the
keyboard controller before being placed into the controller's
output buffer. The following figures show the keyboard layouts.
Each key position is numbered for reference.

1-46

Syst~Pl

Board

tOt-Key Keyboard

System Board

1~4 7

l02-Key Keyboard

1-48

System Board

The following figure is the scan-code translation table.
System
Scan Code

Keyboard
Scan Code

Key
(101/102-key)

01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
10
11
12
13
14
15
16
17
18
19
lA
lB
lC
10
lE
lF
20
21
22
23
24
25
26
27
28
29
2A
2B

76
16
1E
26
25
2E
36
3D
3E
46
45
4E
55
66
00
15
10
24
20
2C
35
3C
43
44
40
54
5B
5A
14
lC
1B
23
2B
34
33
3B
42
4B
4c
52
OE
12
50

2C
20
2E
2F

1A
22
21
2A

110
2
3
4
5
6
7
8
9
10
11
12
13
15
16
17
18
19
20
21
22
23
24
25
26
27
28
43
58
31
32
33
34
35
36
37
38
39
40
41
1
44
29 (U.S. only)
42 (except U.S.)
46
47
48
49

Scan-Code Translation Table (Part 1 of 3)

System Board

1-49

System
Scan Code

Keyboard
Scan Code

30
31
32

32
31
3A
41
49
4A
59
11
29
58
05
06
04
OC
03
OB
83
OA
01
09

33

34
35
36
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
40
4E
4F
50
51
52
53
54
56
57
58
FF
EO 2A EO 37
EO 1C
EO 10
EO 35
EO 37
EO 38
EO 47

77

7E
6C
75
70
7B
6B
73
74
79
69
72

7A
70
71
7F or 84
61
78
07
00
EO 12 EO 7C
EO 5A
EO 14
EO 4A
7C
EO 11
EO 6C

Scan-Code Translation Table (Part 2 of 3)

1-50

System Board

Key

(101/102-key)

50
51
52
53
54
55
57
60
61
30
112
113
114
115
116
117
118
119
120
121
90
125
91
96
101
105
92
97
102
106
93
98
103
99
104

-

45 (except u. S. )
122
123

-

124
108
64
95
100
62
80

System
Scan Code

Keyboard
Scan Code

EO 48
EO 49
EO 4B
EO 40
EO 4F
EO 50
EO 51
EO 52
EO 53
E1 10 45 E1 90 C5

FO 47 75
FO 47 70
FO 47 6B
FO 47 74
FO 47 69
FO 47 72
FO 47 7A
FO 47 70
FO 47 71
E1 14 77 E1
FO 14 FO 77

Key
(101/102-key)
83
85
79
89
81
84
86
75
76
126

Scan-Code Translation Table (Part 3 of 3)

System Board

1-51

The following scan codes are reserved.
Key

Keyboard
Scan Code

System
Scan Code

Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

60
61
78
07
OF
17
IF
27
2F
37
3F
47
4F
56
5E
08
10
18
20
28
30
38
40
48
50
57
6F
13
19
39
51
53
5C
5F
62
63
64
65
67
68
6A
60
6E

55
56
57
58
59
5A
5B
5C
50
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
60
6E
6F
70
71

Reserved Scan-Code Translation Table

1-52

System Board

72

73
74
75
76
77

78
79
7A
7B
7C
70
7E
7F

Sending Data to the Keyboard
The keyboard sends data in the same serial format used to receive
data from the keyboard. A parity bit is automatically inserted by
the keyboard controller. If the keyboard does not start clocking
the data from the keyboard controller within 15 milliseconds, or
complete that clocking within 2 milliseconds, a hex FE is placed
in the keyboard controller's output buffer, and the transmit
time-out error bit is set in the status register.
The keyboard is required to respond to all transmissions. The
keyboard responds to any valid command and parameter, other
than Echo and Resend, with an Acknowledge (ACK) response,
hex FA. If the response contains a parity error, the keyboard
controller places a hex FE in its output buffer, and the transmit
time-out and parity error bits are set in the status register. The
keyboard controller is programmed to set a 25-millisecond time
limit for the keyboard to respond. If this time limit is exceeded,
the keyboard controller places a hex FE in its output buffer and
sets the transmit time-out and receive time-out error bits in the
status register. No retries are attempted by the keyboard
controller for any transmission error.

Keyboard Controller System Interface
The keyboard controller communicates with the system through a
status register, an output buffer, and an input buffer. The
following figure is a block diagram of the keyboard interface.

System Board

1-53

Processor

I~

Input
Buffer
System
Data
Bus

r

.

~

Manufacturing mode
P ~ Display type
U

T

~

-

1---+ U T -

~ T -

+----I....-O-u-tp-u-t--.
I' - -Buffer
-----'

System Reset
Gate A20
IRQ 1
Keyboard Clock--..-+
Keyboard Data -+---r+

--mJ.----------'

,--2_K_R~_~_8---,r . .

Keyboard Controller Interface Block Diagram

Status Register
The status register is an 8-bit read-only register at I/O address
hex 64. It has information about the state of the keyboard
controller (8042) and interface. It may be read at any time.

Status-Register Bit Definition
Bit 7 Parity Error-A 0 indicates the last byte of data received
from the keyboard had odd parity. A 1 indicates the last
byte had even parity. The keyboard should send data with
odd parity.
Bit 6 Receive Time..:Out-A 1 indicates that a transmission was
started by the keyboard but did not finish within the
programmed receive time-out delay.
Bit 5 Transmit Time-Out-A 1 indicates that a transmission
started by the keyboard controller was not properly
completed. If the transmit byte was not clocked out within
the specified time limit, this will be the only error bit on.

1-54

System Board

If the transmit byte was clocked out but a response was
not received within the programmed time limit, the
transmit time-out and receive time-out error bits are set to
1. If the transmit byte was clocked out but the response
was received with a parity error, the transmit time-out and
parity error bits are set to 1.
Bit 4

Always set to 1.

Bit 3

Command/Data-The keyboard controller's input buffer
may be addressed as either I/O address hex 60 or 64.
Address hex 60 is defined as the data port, and address hex
64 is defined as the command port. Writing to address hex
64 sets this bit to 1; writing to address hex 60 sets this bit
to O. The controller uses this bit to determine if the byte in
its input buffer should be interpreted as a command byte
or a data byte.

Bit 2 System Flag-This bit is monitored by the system during
the reset routine. If it is a 0, the reset was caused by a
power on. The controller sets this bit to 0 at power on and
it is set to 1 after a successful self test. This bit can be

changed by writing to the system flag bit in the command
byte (hex 64).
Bit 1 Input Buffer Full-A 0 indicates that the keyboard

controller's input buffer (I/O address hex 60 or 64) is
empty. A 1 indicates that data has been written into the
buffer but the controller has not read the data. When the
controller reads the input buffer, this bit will return to O.
Bit 0

Output Buffer Full-A 0 indicates that the keyboard
controller's output buffer has no data. A 1 indicates that
the controller has placed data into its output buffer but the
system has not yet read the data. When the system reads
the output buffer (I/O address hex 60), this bit Will return
to a O.

System Board

1-55

Output Buffer
The output buffer is an 8-bit read-only register at I/O address
hex 60. The keyboard controller uses the output buffer to send
scan codes received from the keyboard, and data bytes requested
by command, to the system. The output buffer should be read
only when the output-buffer-full bit in the status register is 1.

Input Buffer
The input buffer is an 8-bit write-only register at I/O address hex
60 or 64. Writing to address hex 60 sets a flag, which indicates a
data write; writing to address hex 64 sets a flag, indicating a
command write. Data written to I/O address hex 60 is sent to the
keyboard, unless the keyboard controller is expecting a data byte
following a controller command. Data should be written to the
controller's input buffer only if the input buffer's full bit in the
status register is O. The following are valid keyboard controller
commands.

Commands %

Address Hex 64)

20

Read Keyboard Controller's Command Byte-The
controller sends its current command byte to its output
buffer.

60

Write Keyboard Controller's Command Byte-The next
byte of data written to II0 address hex 60 is placed in the
controller's command byte. Bit definitions of the
command byte are as follows:

1-56

Bit 7

Reserved-Should be written as a O.

Bit 6

IBM Personal Computer Compatibility
Mode-Writing a 1 to this bit causes the controller
to convert the scan codes received from the
keyboard to those used by the IBM Personal
Computer. This includes converting a 2-byte break
sequence to the I-byte IBM Personal Computer
format.

System Board

Bit 5 mM Personal Computer Mode-Writing a 1 to this
bit programs the keyboard to support the mM
Personal Computer keyboard interface. In this
mode the controller does not check parity or
convert scan codes.
Bit 4 Disable Keyboard-Writing a 1 to this bit disables
the keyboard interface by driving the 'clock' line
low. Data is not sent or received.
Bit 3 Not used.
Bit 2 System Flag-The value written to this bit is placed
in the system flag bit of the controller's status
register.
Bit 1 Reserved-Should be written as a O.
Bit 0 Enable Output-Buffer-Full Interrupt-Writing a 1
to this bit causes the controller to generate an
interrupt when it places data into its output buffer.

AA

Self-Test-This commands the controller to perform
internal diagnostic tests. A hex 55 is placed in the output
buffer if no errors are detected.

AD

Interface Test-This commands the controller to test the
'keyboard clock' and 'keyboard data' lines. The test
result is placed in the output buffer as follows:
00 No error detected.
01 The 'keyboard clock' line is stuck low.
02 The' keyboard clock' line is stuck high.
03 The 'keyboard data' line is stuck low.
04 The' keyboard data' line is stuck high.

AD

Disable Keyboard Feature-This command sets bit 4 of
the controller's command byte. This disables the keyboard
interface by driving the clock line low. Data will not be
sent or received.

AE

Enable Keyboard Interface-This command clears bit 4 of
the command byte, which releases the keyboard interface.

System Board

1-57

CO

Read Input Port-This commands the controller to read its
input port and place the data in its output buffer .. This
command should be used only if the output buffer is
empty.

DO

Read Output Port-This command causes the controller to
read its output port and place the data in its output buffer.
This command should be issued only if the output buffer is
empty.

Dl

Write Output Port-The next byte of data written to I/O
address hex 60 is placed in the controller's output port.
Note: Bit 0 of the controller's output port is
connected to System Reset. This bit should not be
written low as it will reset the microprocessor.

EO

Read Test Inputs-This command causes the controller to
read its TO and Tl inputs. This data is placed in the output
buffer. Data bit 0 represents TO, and data bit 1 represents
Tl.

FO-FF Pulse Output Port-Bits 0 through 3 of the controller's
output port may be pulsed low for approximately 6
microseconds. Bits 0 through 3 of this command indicate
which bits are to be pulsed. A 0 indicates that the bit
should be pulsed, and a 1 indicates the bit should not be
modified.
Note: Bit 0 of the controller's output port is
connected to System Reset. Pulsing this bit resets
the microprocessor.

I/O Ports
The keyboard controller has two I/O ports, one assigned for
input and the other for output. Two test inputs are used by the
controller to read the state of the keyboard's' clock' (TO) and
'data' (Tl) lines.
The following figures show bit definitions for the input and output
ports, and the test-inputs.

1-58

System Board

Bit 7
Bit 6
Bit 5
Bit
Bit
Bit
Bit
Bit

4
3
2
1
0

Always set to 1
Display switch - Primary display attached to:
o = Color/Graphics adapter
1 = Monochrome adapter
Manufacturing Jumper
o = Manufacturing jumper installed
1 = Jumper not installed
Always set to 1
Reserved
Reserved
Reserved
Reserved

Input.Port Bit Definitions
Bt 7
Bt 6
Bt 5
Bt 4
Bt 3
Bt 2
Btl
Bt 0

Keyboard data (output)
Keyboard clock (output)
Input buffer empty
Output buffer full
Reserved
Reserved
Gate A20
System reset

Output-Port Bit Definitions

Note: In the real address mode Gate A20 prevents
address line A20 from being set, maintaining compatibility
with the 8088 microprocessor. When in the protected
(virtual address) mode, Gate A20 allows addressing above
the 1M range.
Keyboard data (input)
Keyboard clock (input)

Test-Input Bit Definitions

Real-Time Clock CMOS RAM Information
The RTC (Real-time Clock) CMOS RAM chip (Motorola
MC146818A) contains the real-time clock and 64 bytes of
CMOS RAM. The internal clock circuitry uses 14 bytes of this
RAM, and the rest is allocated to configuration information. The
following figure shows the CMOS RAM addresses.

System Board

1-59

Addresses
00 - OD
OE
OF
10
11
12

II15

16
17
18
19
lA
lB - 2D
2E - 2F
30
31
32
33
34 - 3F

Description

* Real-time clock information
status byte
* Shutdown status byte

* Diagnostic

Diskette drive type byte - drives A and B
Reserved
Fixed disk types byte - drives C and D
Reserved
Equipment byte
Low base memory byte
High base memory byte
Low expansion memory byte
High expansion memory byte
Disk C extended byte
Disk D extended byte
Reserved
2-byte CMOS checksum
* Low expansion memory byte
* High expansion memory byte
* Date century byte
* Information flags (set during power on)
Reserved

CMOS RAM Internal Address Map

* These bytes are not included in the checksum calculation and
are not part of the configuration record.
Real-Time Clock Information
The following figure describes real-time clock bytes and specifies
their addresses.
Byte
0
1
2

l5

6
7
8
9
10
11
12
13

Function

Address

Seconds
Second Alarm
Minutes
Minute Alarm
Hours
Hour Alarm
Day of Week
Date of Month
Month
Year
Status Register
Status Register
Status Register
Status Register

00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD

A
B
C
D

Real-Time Clock Internal Addresses 00 - 00

1-60

System Board

Note: The setup program initializes registers A, B, C,
and D when the time and date are set. Also Interrupt 1A
is the BIOS interface to read/set the time alld date. It
initializes the status bytes the same as the Setup program.

Status Register A
Bit 7

Update in Progress (UIP)-A 1 indicates the time
update cycle is in progress. A 0 indicates the
current date and time are available to read.

Bit 6-Bit 4

22-Stage Divider (DV2 through DVO)-These
three divider-selection bits identify which
time-base frequency is being used. The system
initializes the stage divider to 010, which selects a
32.768-kHz time base.
.

Bit 3-Bit 0

Rate Selection Bits (RS3 through RSO )-These
bits allow the selection of a divider output
frequency. The system iIlitializes the rate selection
bits to 0110, which selects a 1.024-kliz square
.
wave output frequency and a '
976.562-microsecond periodic interrupt rate.

Status Register B
Bit 7

Set-A 0 updates the cycle normally by advancing
the counts at one-per-s~cond. A 1 aborts any
update cycle in progress and the program can
initialize the 14 time-bytes without any further
updates occurring until a 0 iswritt~n to this bit.

Bit 6

Periodic Interrupt Enable (PID)-This bit is a
read/write bit that allows an interrupt to occur at
a rate specified by the rateancl divider bits in
register A. A 1 enabl~s all interrupt, and a 0
disables it. The syste:p:l initiafzes this bit to O.

Bit 5

Alarm Interrupt Enable (AIE)-A. 1 enables the
alarm interrupt, and a 0 disables it. The system
.
initializes this bit to o.

S)'st~m

Board

1-61

Bit 4

Update-Ended Interrupt Enabled (UIE)-A 1
enables the update-ended interrupt, and a 0
disables it. The system initializes this bit to o.

Bit 3

Square Wave Enabled (SQWE)-A 1 enables the
the square-wave frequency as set by the rate
selection bits in register A, and a 0 disables the
square wave. The system initializes this bit to O.

Bit 2

Date Mode (DM)-This bit indicates whether the
time and date calendar updates are to use binary or
binary coded decimal (BCD) formats. A 1
indicates binary, and a 0 indicates BCD. The
system initializes this bit to O.

Bit 1

24/ 12-This bit indicates whether the hours byte
is in the 24-hour or 12-hour mode. A 1 indicates
the 24-hour mode and a 0 indicates the 12-hour
mode. The system initializes this bit to 1.

Bit 0

Daylight Savings Enabled (DSE)-A 1 enables
daylight savings and a 0 disables daylight savings
(standard time). The system initializes this bit
to O.

Status Register C
Bit 7-Bit 4

IRQF, PF, AF, UF-These flag bits are read-only
and are affected when the AlE, PIE, and UIE bits
in register B are set to 1.

Bit 3-Bit 0

Reserved-Should be written as a O.

Status Register D
Bit 7

1-62

Valid RAM Bit (VRB)-This bit is read-only and
indicates the status of the power-sense pin
(battery level). A 1 indicates battery power to the
real-time clock is good. A 0 indicates the battery
is dead, so RAM is not valid.

System Board

Bits 6-Bit 0

Reserved-Should be written as a O.

CMOS RAM Configuration Information
The following lists show bit definitions for the CMOS
configuration bytes (addresses hex OE - 3F).

Diagnostic Status Byte (Hex OE)
Bit 7

Power status of the real-time clock chip-A 0
indicates that the chip has not lost power (battery
good), and a 1 indicates that the chip lost power
(battery bad).

Bit 6

Configuration Record (Checksum Status
Indicator)-A 0 indicates that checksum is good,
and a 1 indicates it is bad.

Bit 5

Incorrect Configuration Information-This is a
check, at power-on time, of the equipment byte of
the configuration record. A 0 indicates that the
configuration information is valid, and a 1
indicates it is invalid. Power-on checks require:
•

At least one diskette drive to be installed (bit 0
of the equipment byte set to 1).

•

The primary display adapter setting in
configuration matches the system board's
display switch setting and the actual display
adapter hardware in the system.

Bit 4

Memory Size Comparison-A 0 indicates that the
power-on check determined the same memory size
as in the configuration record, and a 1 indicates
the memory size is different.

Bit 3

Fixed Disk Adapter/Drive C Initialization
Status-A 0 indicates that the adapter and drive
are functioning properly and the system can
attempt "boot up." A 1 indicates that the adapter

System Board

1-63

and/ or drive C failed initialization, which prevents
the system from attempting to "boot up."
Bit 2

Time Status Indicator (POST validity check)- A
o indicates that the time is valid, and a 1 indicates
that it is invalid.

Bit 1-Bit 0

Reserved

Shutdown Status Byte (Hex OF)
The bits in this byte are defined by the power on diagnostics. For
more information about this byte, refer to "System BIOS".

Diskette Drive Type Byte (Hex 10)
Bit 7-Bit 4

Type of first diskette drive installed:
0000
0001
0010
0011

No drive is present.
Double Sided Diskette Drive (48 TPI).
High Capacity Diskette Drive (96 TPI).
720KB Diskette Drive (3.5 inch).

Note:
Bit 3-Bit 0

0100 through 1111 are reserved.

Type of second diskette drive installed:
0000
0001
0010
0011

No drive is present.
Double Sided Diskette Drive (48 TPI).
High Capacity Diskette Drive (96 TPI).
720KB Diskette Drive (3.5 inch).

Note:

0100 through 1111 are reserved.

Hex address 11 contains a reserved byte.
Fixed Disk Type Byte (Hex 12)

1-64

System Board

Bit 7-Bit 4

Defines the type of fixed disk drive installed (drive
C):
0000 No fixed disk drive is present.
0001 Define type 1 through type 14 as shown
to
in the following table (also see BIOS
1110 listing at label FD_TBL)
1111 Type 16 through 255. See "Drive C
Extended Byte (Hex 19)" on page 1-68.

Bit 3-Bit 0

Defines the type of second fixed disk drive
installed (drive D):
0000 No fixed disk drive is present.
0001 Define type 1 through type 14 as shown
to
in the following table (also see BIOS
1110 listing at label FD_TBL)
1111 Type 16 through 255. See "Drive D
Extended Byte (Hex lA)" on page 1-68.

The following table shows the BIOS fixed disk parameters.
Type

Cylinders

Heads

Wr i te
Precomp

Landing
Zone

1
2
3
4
5
6
7
8
9
10
11
12
13
14

306
615
615
940
940
615
462
733
900
820
855
855
306
733

4
4
6
8
6
4
8
5
15
3
5
7
8
7

128
300
300
512
512
None
256
None
None
None
None
None
128
None

305
615
615
940
940
615
511
733
901
820
855
855
319
733

15

Extended Parameters (hex 19 and lA)

BIOS Fixed Disk Parameters

System Board

1-65

Hex address 13 contains a reserved byte.

Equipment Byte (Hex 14)
Bit 7-Bit 6

Indicates the number of diskette drives installed:

00
01
10
11
Bit S-Bit 4

1 drive
2 drives

Reserved
Reserved

Primary display

00 Primary display is attached to an adapter that
has its own BIOS, such as the Enhanced
Graphics Adapter
01 Primary display is in the 40-column mode and
attached to the Color/Graphics Monitor
Adapter.
10 Primary display is in the 80-column mode and
attached to the Color/Graphics Monitor
Adapter.
11 Primary display is attached to the
Monochrome Display and Printer Adapter.
Bit 3-Bit 2

Not used.

Bit 1

Math Coprocessor presence bit:

o

Math Coprocessor not installed
1 Math Coprocessor installed

Bit 0

Diskette drive presence bit:

o

Diskette drive not installed
1 Diskette drive installed

1-66

System Board

Note: The equipment byte defines basic equipment in the
system for power-on diagnostics.
Low and High Base Memory Bytes (Hex 15 and 16)
Bit 7-Bit 0

Address hex 15-Low-byte base size

Bit 7-Bit 0

Address hex 16-High-byte base size
Valid Sizes:
0200H 512K-system board RAM
0280H 640K-system board RAM.

Low and High Expansion Memory Bytes (Hex 17 and 18)
Bit 7-Bit 0

Address hex 17-Low-byte expansion size

Bit 7-Bit 0

Address hex 18-High-byte expansion size
Valid Sizes:
0200H
0400H
0600H
through
3COOH

512K-Expansion Memory
1024K-Expansion Memory
1536K-Expansion Memory
15360K-Expansion Memory (15M
maximum).

System Board

1-67

Drive C Extended Byte (Hex 19)
Bit 7-Bit 0

Defines the type of first fixed disk drive installed
(drive C):
00000000 through 00001111 are reserved.
00010000 to 11111111 define type 16 through
255 as shown in the following table (see BIOS
listing at label FD_TBL).

Drive D Extended Byte (Hex lA)
Bit 7-Bit 0

Defines the type of second fixed disk drive
installed (drive D):
00000000 through 00001111 are reserved.
00010000 to 11111111 define type 16 through
255 as shown in the following table (see BIOS
listing at label FD_TBL).

The following table shows the BIOS fixed disk parameters for
fixed disk drive types 16 through 24.
Note:

Types 25 through 255 are reserved.

Type

Cyl inders

Heads

16
17
18
19
20
21
22
23
24

612
977
977
1024
733
733
733
306
612

4
5
7
7
5
7
5
4
4

Wr ite
Precomp

Landing
Zone

All Cyl inders

663
977
977
1023
732
732
733
336
663

300

None

512
300
300
300

None

305

25

Reserved

255

Reserved

BIOS Fixed Disk Parameters (Extended)

1-68

System Board

Hex addresses IB through 2D are reserved.

Checksum (Hex 2E and 2F)
Bit 7-Bit 0

Address hex 2E-High byte of checksum

Bit 7-Bit 0

Address hex 2F-Low byte of checksum

Note:

Checksum is calculated on addresses hex 10-2D.

Low and High Expansion Memory Bytes (Hex 30 and 31)
Bit 7-Bit 0

Address hex 30-Low-byte expansion size

Bit 7-Bit 0

Address hex 31-High-byte expansion size
Valid Sizes:
0200H 512K-Expansion Memory
0400H 1024K-Expansion Memory
0600H 1536K-Expansion Memory
through
3COOH 15360K-Expansion Memory (15M
maximum).

Note: These bytes reflect the total expansion memory
above the 1M address space as determined at power-on
time. This expansion memory size can be determined
through system interrupt 15 (see the BIOS listing). The
base memory at power-on time is determined through the
system memory-size-determine interrupt (hex 12).

Date Century Byte (Hex 32)
Bit 7-Bit 0

BCD value for the century (BIOS interface to read
and set).

System Board

1-69

Information Flag (Hex 33)
Bit 7

When set, this bit indicates that the top 128K of
base memory is installed.

Bit 6

This bit is set to instruct the Setup utility to put
out a first user message after initial setup.

Bit 5-Bit 0

Reserved

Hex addresses 34 through 3F are reserved.

110 Operations
Writing to RTC CMOS RAM involves two steps:
1. OUT to port hex 70 with the internal CMOS address. Bits
00 - 05 contain the required address.
Note: Bits 06 and 07 do not go to RTC CMOS
RAM. 06 is a "don't care" bit. 07 is the value of the
NMI mask: writing a 1 to 07 disables NMI; writing a
o to 07 enables NMI.
2. OUT to port hex 71 with the data to be written.

Reading CMOS RAM also requires two steps:
1. OUT to port hex 70 with the internal CMOS address. Bits
00 - 05 contain the required address.

Note: Bits D6 and 07 do not go to RTC CMOS
RAM. 06 is a "don't care" bit. 07 is the value of the
NMI mask: writing a 1 to 07 disables NMI; writing a
o to 07 enables NMI.
2. IN from port hex 71, and the data read is returned in the AL
register.

1-70

System Board

Note: Execute the steps in the order shown to ensure
acknowledgement of the MC146818A Standby lead during
system power-downs.

System Board

1-71

Specifications
System Uhlt
Size
•

Length: 500 millimeters (19.6 inches)

•

Depth: 410 millimeters (16.1 inches)

•

Height: 142 millimeters (5.5 inches)

Weight
•

12.7 kilograms (28 pounds)

Power Cables
•

Length: 1.8 meters (6 feet)

Environment
•

•

•

Air Temperature
-

System On: 15;6 to 32.2 degrees C (60 to 90 degrees F)

-

System Off: 10 to 43 degrees C (50 to 110 degrees F)

Wet BUlb Temperature
-

System On: 22.8 degrees C (73 degrees F)

-

System Off: 26.7 degrees C (80 degrees F)

Humidity
-

1-72

System On: 8 % to 80%

System Board

•

System Off: 20% to 80%

Altitude
-

Maximum altitude: 2545.1 meters (8350 feet)

Heat Output
•

824 British Thermal Units (BTU) per hour

Noise Level
•

Operating (without display or printer) - 46 decibels (dba)
maximum noise level.

Electrical
•

Range 1 (57-63 Hz)
Nominal: 115 Vac
Minimum: 90 Vac
Maximum: 137 Vac

•

Range 2 (47-53 Hz)
Nominal: 230 Vac

•

-

Minimum: 180 Vac

-

Maximum: 265 Vac

Lithium Battery
-

6.0Vdc

-

1 Ampere/Hour Capacity

-

UL Approved.

System Board

1-73

Connectors
The system board has the following additional connectors:
•

One power supply connector (Pt)

•

Battery connector (P2)

•

Speaker connector (P3)

•

Keyboard connector (J9).

The pin assignments for the system board connector (P 1) and the
power supply connectors P8 and P9, are as follows. Beginning at
the rear of the system, the pins on the system board connector are
numbered 1 through 12. Power supply connector P8 attaches to
system board connector PI, pins 1 through 6. P9 connects to PI,
pins 7 through 12.
System Board
Connector

PI

Pin

Assignments

1
2
3

6

Power Good
+5 Vdc
+12 Vdc
-12 Vdc
Ground
Ground

7
8
9
10
11
12

Ground
Ground
-5 Vdc
+5 Vdc
+5 Vdc
+5 Vdc

4

5

Power Supply
Connector
p8

Pin
1
2
3

4

5
6

P9

1
2
3

4

5
6

System Board Connector (P1) to Power Supply Connectors (P8
and P9)

1-74

System Board

The battery connector, P2, is a four-pin, keyed, Berg strip. The
pins are numbered 1 through 4 from the rear of the system. The
pin assignments are:
Pin

Assignments

1
2
3
Z.

+6 Vdc
Key
Ground
Ground

Battery Connector (P2)

The speaker connector, P3, is a four-pin, keyed, Berg strip. The
pins are numbered 1 through 4 from the rear of the system. The
pin assignments are:
Pin

Function

1
2

Data out
Key
Ground
+5 Vdc

3
Z.

Speaker Connector (P3)

The keyboard connector, J9, is a five-pin, 90-degree Printed
Circuit Board (PCB) mounting, DIN connector. For pin
numbering, see the "Keyboard" Section. The pin assignments
are:
Pin

Assignments

1
2

Keyboard Clock
Keyboard Data
Reserved
Ground
+5 Vdc

3

Z.

5

Keyboard Connector (J9)

System Board

1-75

The following figure shows the layout of the system board.
Rear Panel

Memory Module Packages

-

~

-

-

= =~ =
~

== ==

~

1-76

=nI

~

r--

frnii==:-+- Display Switch

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80286

80287

Processor

Math Co· Processor

System Board

Logic Diagrams

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System Board

1-77

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1-79

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System Board

1-81

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System Board

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1-83

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1-84

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1-85

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1-86

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System Board

1-87

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System Board

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1-89

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System Board

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1-91

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1-92

System Board

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System Board

1-93

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1-94

System Board

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System Board

1-97

1-98

System Board

SECTION 2. COPROCESSOR

Description ................................... 2-3
Programming Interface .......................... 2-3
Hardware Interface ............................. 2-4

Coprocessor

2-1

Notes:

2-2

Coprocessor

Description
The Math Coprocessor (80287) enables the IBM Personal
Computer XT Model 286 to perform high-speed arithmetic,
logarithmic functions, and trigonometric operations.
The coprocessor works in parallel with the microprocessor. The
parallel operation decreases operating time by allowing the
coprocessor to do mathematical calculations while the
microprocessor continues to do other functions.
The coprocessor works with seven numeric data types, which are
divided into the following three classes:
•

Binary integers (3 types)

•

Decimal integers (1 type)

•

Real numbers (3 types).

Programming Interface
The coprocessor offers extended data types, registers, and
instructions to the microprocessor.
.
The coprocessor has eight 80-bit registers, which provide the
equivalent capacity of forty 16-bit registers. This register space
allows constants and temporary results to be held in registers
during calculations, thus reducing memory access and improving
speed as well as bus availability. The register space can be used as
a stack or as a fixed register set. When used as a stack, only the
top two stack elements are operated on.

Coprocessor

2-3

The following figure shows representations of large and small
numbers in each data type.

Data Type

Bits

Word Integer

16

Significant
Digits
(Decimal) Approximate Range (Decimal)
4

-32,768

~

-2xl0 9 ~

X ~ +32,767
X ~ +2xl0 9

Short Integer

32

9

Long Integer

64

18

Packed Decimal

80

18

32

6-7

64

15-16

4. 19x10-307 ~ IXI

~

1.67xl0308

80

19

3 .4xl0-4932 ~ IXI

~

1.2xl04932

Short Real
Long Real

*
*

Temporary Real

-9xl0 18 ~ X ~ +9xl0 18
-9 .. 99

~

X ~ +9 .. 99 (18 digits)

8.43xl0-37 ~ IXI ~ 3.37xl038

Data Types

* The Short Real and Long Real data types correspond to the
single and double precision data types.

Hardware Interface
The coprocessor uses a 4.77 MHz clock (generated by a 14.318
MHz clock generator divided by three). The coprocessor is wired
so that it functions as an I/O device through I/O port addresses
hex 00F8, OOFA, and OOFC. The microprocessor sends OP codes
and operands through these I/O ports. The microprocessor also
receives and stores results through the same I/O ports. The
coprocessor's 'busy' signal informs the microprocessor that it is
executing; the microprocessor's Wait instruction forces the
microprocessor to wait until the coprocessor is finished executing.
The coprocessor detects six different exception conditions that
can occur during instruction execution. If the appropriate
exception mask within the coprocessor is not set, the coprocessor
sets its error signal. This error signal generates a hardware
interrupt (interrupt 13) and causes the 'busy' signal to the
coprocessor to be held in the busy state. The 'busy' signal may
be cleared by an 8-bit I/O Write command to address hex FO
with DO through D7 equal to o.
The power-on self-test code in the system ROM enables IRQ 13
and sets up its vector to point to a routine in ROM. The ROM
routine clears the 'busy' signal's latch and then transfers control

2-4

Coprocessor

to the address pointed to by the NMI interrupt vector. This
allows code written for any IBM Personal Computer to work on
an IBM Personal Computer XT Model 286. The NMI interrupt
handler should read the coprocessor's status to determine if the
NMI was caused by the coprocessor. If the interrupt was not
generated by the coprocessor, control should be passed to the
original NMI interrupt handler.
The coprocessor has two operating modes similar to the two
modes of the microprocessor. When reset by a power-on reset,
system reset, or an I/O write operation to port hex OOFt, the
coprocessor is in the real address mode. This mode is compatible
with the 8087 Math Coprocessor used in other IBM Personal
Computers. The coprocessor can be placed in the protected mode
by executing the SETPM ESC instruction. It can be placed back
in the real mode by an I/O write operation to port hex OOFt, with
D7 through DO equal to O.
The coprocessor instruction extensions to the microprocessor can
be found in Section 6 of this manual.
Detailed information for the internal functions of the Intel 80287
Coprocessor can b~ found in books listed in the bibliography.

Coprocessor

2-5

Notes:

2-6

Coprocessor

SECTION 3. POWER SUPPLY

Inputs .......................................
Outputs ......................................
DC Output Protection ..........................
Output Voltage Sequencing ......................
No-Load Operation ............................
Power-Good Signal .............................
Connectors ...................................

Power Supply

3-3
3-3
3-4
3-4
3-4
3-4
3-6

3-1

Notes:

3-2

Power Supply

The system power supply is located inside the system unit and
provides power for the system board, the adapters, the diskette
drives, the fixed disk drive, the keyboard, and the IBM
Monochrome Display.

Inputs
The power supply can operate at 110 Vac, 4.6 A or 220/240
Vac, 2.3 A at frequencies of either 60 ±3 Hz or 50 ±3 Hz. The
power supply automatically adjusts to input voltages of 110 Vac
or 220 Vac. The following figure shows the input requirements.
Range

Voltage (Vac)
Minimum

115 Vac

230 Vac

90

Current (Amperes)
Maximum 4.6

Maximum 137
Minimum 180
Maximum 265

Maximum 2.3

Input Requirements

Outputs
The power supply provides +5, -5, + 12, and -12 Vdc. The
following figure shows the load current and regulation tolerance
for these voltages. The power to the IBM Monochrome Display
display is controlled by the power supply.
Warning: The voltage provided to the monochrome display from
the power supply is the same as the input line voltage to the
power supply. Ensure that the monochrome display is the correct
model for the input line voltage.
Nominal
Output
+5
-5
+12
-12

Vdc
Vdc
Vdc
Vdc

Load Current (A)
Minimum
Maximum
4.0
0.0
1.0
0.0

20.0
0.3
4.2
0.25

Regulation
Tolerance
+5% to -4%
+10% to -8%
+5% to -4%
+10% to -9%

DC Load Requirements

Power Supply

3-3

DC Output Protection
An overcurrent condition will not damage the power supply.

Output Voltage Sequencing
Under normal conditions, the output voltage levels track within
50 milliseconds of each other when power is applied to, or
removed from the power supply, provided at least minimum
loading is present.

No-Load Operation
No damage or hazardous conditions occur when primary power is
applied with no load on any output level. In such cases, the
power supply may switch off, and a power-on reset will be
required. The power supply requires a minimum load for proper
operation.

Power-Good Signal
The power supply provides a 'power-good' signal to indicate
proper operation of the power supply.
When the supply is switched off for a minimum of one second and
then switched on, the 'power-good' signal is generated, assuming
there are no problems. This signal is a logical AND of the dc
output-voltage sense signal and the ac input-voltage sense signal.
The 'power-good' signal is also a TTL-compatible high level for
normal operation, and a low level for fault conditions. The ac fail
signal causes 'power-good' to go to a low level at least one
millisecond before any output voltage falls below the regulation
limits. The operating point used as a reference for measuring the
one millisecond is normal operation at minimum line voltage and
maximum load.
The dc output-voltage sense signal holds the 'power-good' signal
at a low level when power is switched on until all output voltages
have reached their minimum sense levels. The 'power-good'
signal has a turn-on delay of at least 100 milliseconds but not

3-4

Power Supply

longer than 500 milliseconds and is capable of sourcing 2
milliamperes and sinking 10 milliamperes.
The following figure shows the minimum sense levels for the
output voltages.
Level (Vdc)

+5
-5
+12
-12

Minimum (Vdc)

+4.5
-4.3
+10.8
-10.2

Sense Level

Power Supply

3-5

Connectors
The following figure shows the pin assignments for the
power-supply output connectors.
Load Point

*

Voltage (Vdc)

P8-l
P8-2
P8-3
p8-4
P8-5
p8-6

Power Good
+5
+12
-12
Ground
Ground

P9-1
P9-2
P9-3
P9-4
P9-5
P9-6

Ground
Ground
-5
+5
+5
+5

Pl0-l
Pl0-2
Pl0-3
Pl0-4

+12
Ground
Ground
+5

P11-1
P11-2
P11-3
P11-4

+12
Ground
Ground
+5

*

see "Power-Good Signal"

Power Supply Output Connectors

3-6

Power Supply

SECTION 4. KEYBOARD

Description ................................... 4-3
Cabling ................................ 4-3
Sequencing Key-Code Scanning ............. 4-4
Keyboard Buffer ......................... 4-4
Keys .................................. 4-4
Power-On Routine .......................... 4-5
Power-On Reset ......................... 4-5
Basic Assurance Test ..................... 4-5
Commands from the System ................... 4-6
Default Disable (Hex F5) .................. 4-7
Echo (Hex EE) .......................... 4-7
Enable (Hex F4) ......................... 4-7
Invalid Command (Hex EF and Fl) .......... 4-7
Read ID (Hex F2) ....................... 4-7
Resend (Hex FE) ........................ 4-8
Reset (Hex FF) ......................... 4-8
Select Alternate Scan Codes (Hex FO) ........ 4-8
Set All Keys (Hex F7, F8, F9, FA) .......... 4-9
Set Default (Hex F6) ..................... 4-9
Set Key Type (Hex FB, FC, FD) ............ 4-9
Set/Reset Status Indicators (Hex ED) ....... 4-10
Set Typematic Rate/Delay (Hex F3) ........ 4-11
Commands to the System .................... 4-13
Acknowledge (Hex FA) .................. 4-13
BAT Completion Code (Hex AA) .......... 4-13
BAT Failure Code (Hex FC) .............. 4-13
Echo (Hex EE) ......................... 4-13
Keyboard ID (Hex 83AB) ................ 4-14
Key Detection Error (Hex 00 or FF) ........ 4-14
Overrun (Hex 00 or FF) .................. 4-14
Resend (Hex FE) ....................... 4-14
Keyboard Scan Codes ....................... 4-15
Scan Code Set 1 ........................ 4-16
Scan Code Set 2 ........................ 4-20
Scan Code Set 3 ........................ 4-24
Clock and Data Signals ...................... 4-27
Data Stream ........................... 4-27

Keyboard

4-1

Keyboard Data Output ...................
Keyboard Data Input ....................
Keyboard Encoding and Usage ................
Character Codes ........................
Extended Functions .....................
Shift States ............................
Special Handling ........................
Keyboard Layouts .........................
French Keyboard .......................
German Keyboard ......................
Italian Keyboard ........................
Spanish Keyboard .......................
u.K. English Keyboard ...................
U.S. English Keyboard ...................
Specifications .............................
Power Requirements .....................
Size ..................................
Weight ...............................
Logic Diagram ............................

4-2

Keyboard

4-28
4-29
4-30
4-30
4-34
4-36
4-38
4-40
4-41
4-42
4-43
4-44
4-45
4-46
4-47
4-47
4-47
4-47
4-48

Description
The keyboard has 101 keys (102 in countries outside the U. S.).
At system power-on, the keyboard monitors the signals on the
'clock' and 'data' lines and establishes its line protocol. A
bidirectional serial interface in the keyboard converts the 'clock'
and 'data' signals and sends this information to and from the
keyboard through the keyboard cable.

Cabling
The keyboard cable connects to the system with a five-pin DIN
connector, and to the keyboard with a six-position SDL
connector. The following table shows the pin configuration and
signal assignments.

///\~

ABCDEF

DIN Connector

DIN Connector
Pins

SOL Connector
Pins

1

0

2
3

B
F
C

5

E

4
Shield

A
Shield

SDL Connector

Signal Name

Signal Type

+KBD ClK
+KBD DATA
Reserved
Ground
+5.0 Vdc
Not used
Frame Ground

Input/Output
Input/Output
Ground
Power

Keyboard

4-3

Sequencing Key-Code Scanning
The keyboard detects all keys pressed, and sends each scan code
in the correct sequence. When not serviced by the system, the
keyboard stores the scan codes in its buffer.

Keyboard Buffer
A 16-byte first-in-first-out (FIFO) buffer in the keyboard stores
the scan codes until the system is ready to receive them.

A buffer-overrun condition occurs when more than 16 bytes are
placed in the keyboard buffer. An overrun code replaces the 17th
byte. If more keys are pressed before the system allows keyboard
output, the additional data is lost.
When the keyboard is allowed to send data, the bytes in the
buffer will be sent as in normal operation, and new data entered is
detected and sent. Response codes do not occupy a buffer
position.
If keystrokes generate a multiple-byte sequence, the entire
sequence must fit into the available buffer space or the keystroke
is discarded and a buffer-overrun condition occurs.

Keys
With the exception of the Pause key, all keys are make/break.
The make scan code of a key is sent to the keyboard controller
when the key is pressed. When the key is released, its break scan
code is sent.
Additionally, except for the Pause key, all keys are typematic.
When a key is pressed and held down, the keyboard sends the
make code for that key, delays 500 milliseconds ± 20%, and
begins sending a make code for that key at a rate of 10.9
characters per second ± 20%. The typematic rate and delay can
be modified [see "Set Typematic Rate/Delay (Hex F3)" on
page 4-11].
If two or more keys are held down, only the last key pressed
repeats at the typematic rate. Typematic operation stops when

4-4

Keyboard

the last key pressed is released, even if other keys are still held
down. If a key is pressed and held down while keyboard
transmission is inhibited, only the first make code is stored in the
buffer. This prevents buffer overflow as a result of typematic
action.
Note: Scan code set 3 allows key types to be changed by the
system. See "Scan Code Tables (Set 3)" on page 4-24 for the
default settings. Commands to change the default settings are
listed in "Commands from the System" on page 4-6.

Power-On Routine
The following activities take place when power is first applied to
the keyboard.

Power-On Reset
The keyboard logic generates a 'power-on reset' signal (POR)
when power is first applied to the keyboard. POR occurs a
minimum of 150 milliseconds and a maximum of 2.0 seconds
from the time power is first applied to the keyboard.

Basic Assurance Test
The basic assurance test (BAT) consists of a keyboard processor
test, a checksum of the read-only memory (ROM), and a
random-access memory (RAM) test. During the BAT, activity on
the 'clock' and 'data' lines is ignored. The LEDs are turned on
at the beginning and off at the end of the BAT. The BAT takes a
minimum of 300 milliseconds and a maximum of 500
milliseconds. This is in addition to the time required by the POR.
Upon satisfactory completion of the BAT, a completion code (hex
AA) is sent to the system, and keyboard scanning begins. If a
BAT failure uccurs, the keyboard sends an error code to the
system. The keyboard is then disabled pending command input.
Completion codes are sent between 450 milliseconds and 2.5
seconds after POR, and between 300 and 500 milliseconds after a
Reset command is acknowledged.

Keyboard

4-5

Immediately following POR, the keyboard monitors the signals on
the keyhQard I clock I and I data I lines and sets the line protocol.

Commands from the System
The following table shows the commands that the system may
send and their hexadecimal values.
Command
Set/Reset Status Indicators
Echo
Inva 11 d Command
Select Alternate Scan Codes
1nva 11 d Command
Read ID
Set Typematic Rate/Delay
Enable
Default Disable
Set Default
Set All Keys - Typematic
- Make/Break
- Make
- Typematic/Make/Break
Set Key Type - Typematic
- Make/Break
- Make
Resend
Reset

Hex Value
ED
EE
EF
FO
Fl
F2
F3
F4
F5
F6
F7
Fa
F9
FA
FB
FC
FD
FE
FF

The commands may be sent to the keyboard at any time. The
keyboard will respond within 20 milliseconds, except when
performing the basic assurance test (BAT), or executing a Reset
command.
Note:

Mode 1 will accept only the I reset I command.

The commands are described below, in alphabetic order. They
have different meanings when issued by the keyboard (see
"Commands to the System" on page 4-13).

4-6

Keyboard

Default Disable (Hex F5)
The Default Disable command resets all conditions to the
power-on default state. The keyboard responds with ACK, clears
its output buffer, sets the default key types (scan code set 3
operation only) and typematic rate/delay, and clears the last
typematic key. The keyboard stops scanning, and awaits further
instructions.

Echo (Hex EE)
Echo is a diagnostic aid. When the keyboard receives this
command, it issues a hex EE response and, if the keyboard was
previously enabled, continues scanning.

Enable (Hex F4)
Upon receipt of this cominand, the keyboard responds with ACK,
clears its output buffer, clears the last typematic key, and starts
scanning.

Invalid Command (Hex EF and Fl)
Hex EF and hex Fl are invalid commands and are not supported.
If one of these is sent, the keyboard does not acknowledge the

command, but returns a Resend command and continues in its
prior scanning state. No other activities occur.

Read ID (Hex F2)
This command requests identification information from the
keyboard. The keyboard responds with ACK, discontinues
scanning, and sends the two keyboard ID bytes. The second byte
must follow completion of the first by no more than 500
microseconds. After the output of the second ID byte, the
keyboard resumes scanning.

Keyboard

4-7

Resend (Hex FE)
The system sends this command when it detects an error in any
transmission from the keyboard. It is sent only after a keyboard
transmission and before the system allows the next keyboard
output. When a Resend is received, the keyboard sends the
previous output again (unless the previous output was Resend, in
which case the keyboard sends the last byte before the Resend
command).

Reset (Hex FF)
The system issues a Reset command to start a program reset and a
keyboard internal self test. The keyboard acknowledges the
command with an ACK and ensures the system accepts ACK
before executing the command. The system signals acceptance of
ACK by raising the 'clock' and 'data' lines for a minimum of
500 microseconds. The keyboard is disabled from the time it
receives the Reset command until ACK is accepted, or until
another command is sent that overrides the previous command.
Following acceptance of ACK, the keyboard is re-initialized and
performs the BAT. After returning the completion code, the
keyboard defaults to scan code set 2.

Select Alternate Scan Codes (Hex FO)
This command instructs the keyboard to select one of three sets
of scan codes. The keyboard acknowledges receipt of this
command with ACK, clears both the output buffer and the
typematic key (if one is active). The system then sends the
option byte and the keyboard responds with another ACK. An
option byte value of hex 01 selects scan code set 1, hex 02 selects
set 2, and hex 03 selects set 3.
An option byte value of hex 00 causes the keyboard to
acknowledge with ACK and send a byte telling the system which
scan code set is currently in use.
After establishing the new scan code set, the keyboard returns to
the scanning state it was in before receiving the Select Alternate
Scan Codes command.

4-8

Keyboard

~

Set All Keys (Hex F7, F8, F9, FA)
These commands instruct the keyboard to set all keys to the type
listed below:
Command

Hex Value
F7
Fa
F9
FA

Set
Set
Set
Set

All
All
All
All

Keys
Keys
Keys
Keys

-

Typematic
Make/Break
Make
Typematic/Make/Break

The keyboard responds with ACK, clears its output buffer, sets
all keys to the type indicated by the command, and continues
scanning (if it was previously enabled). Although these
commands can be sent using any scan code set, they affect only
scan code set 3 operation.

Set Default (Hex F6)
The Set Default command resets all conditions to the power-on
default state. The keyboard responds with ACK, clears its output
buffer, sets the default key types (scan code set 3 operation only)
and typematic rate/delay, clears the last typematic key, and
continues scanning.

Set Key Type (Hex FB, Fe, FD)
These commands instruct the keyboard to set individual keys to
the type listed below:
Hex Value
FB
FC
FD

Command
Set Key Type - Typematic
Set Key Type - Make/Break
Set Key Type - Make

The keyboard responds with ACK, clears its output buffer, and
prepares to receive key identification. Key identification is
accomplished by the system identifying each key by its scan code
value as defined in scan code set 3. Only scan code set 3 values
are valid for key identification. The type of each identified key is
set to the value indicated by the command.

Keyboard

4-9

These commands can be sent using any scan code set, but affect
only scan code set 3 operation.

Set/Reset Status Indicators (Hex ED)
Three status indicators on the keyboard- Num Lock, Caps
Lock, and Scroll Lock-are accessible by the system. The
keyboard activates or deactivates these indicators when it receives
a valid command-code sequence from the system. The command
sequence begins with the command byte (hex ED). The keyboard
responds to the command byte with ACK, discontinues scanning,
and waits for the option byte from the system. The bit
assignments for this option byte are as follows:
Bit
0
1
2

3-7

Indicator
Scroll Lock Indicator
Num Lock Indicator
Caps Lock Indicator
Reserved (must be Os)

If a bit for an indicator is set to 1, the indicator is turned on. If a

bit is set to 0, the indicator is turned off.
The keyboard responds to the option byte with ACK, sets the
indicators and, if the keyboard was previously enabled, continues
scanning. The state of the indicators will reflect the bits in the
option byte and can be activated or deactivated in any
combination. If another command is received in place of the
option byte, execution of the Set/Reset Mode Indicators
command is stopped, with no change to the indicator states, and
the new command is processed.
Immediately after power-on, the lights default to the Off state. If
the Set Default and Default Disable commands are received, the
lamps remain in the state they were in before the command was
received.

4-10

Keyboard

Set Typematic Rate/Delay (Hex F3)
The system issues the Set Typematic Rate/Delay command to
change the typematic rate and delay. The keyboard responds to
the command with ACK, stops scanning, and waits for the system
to issue the rate/delay value byte. The keyboard responds to the
rate/delay value byte with another ACK, sets the rate and delay
to the values indicated, and continues scanning (if it was
previously enabled). Bits 6 and 5 indicate the delay, and bits 4, 3,
2, 1, and 0 (the least-significant bit) the rate. Bit 7, the
most-significant bit, is always O. The delay is equal to 1 plus the
binary value of bits 6 and 5, multiplied by 250 milliseconds ±
20%.
The period (interval from one typematic output to the next) is
determined by the following equation:
Period = (8 + A) X (2B) X 0.00417 seconds.
where:
A = binary value of bits 2, 1, and O.
B = binary value of bits 4 and 3.

Keyboard

4-11

The typematic rate (make codes per second) is 1 for each period
and are listed in the following table.
Bit

Typematic
Rate ± 20%

Bit

Typematic
Rate ± 20%

00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111

30.0
26.7
24.0
21.8
20.0
18.5
17.1
16.0
15.0
13.3
12.0
10.9
10.0
9.2
8.0
8.0

10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111

7.5
6.7
6.0
5.5
5.0
4.6
4.3
4.0
3.7
3.3
3.0
2.7
2.5
2.3
2.1
2.0

The default values for the system keyboard are as follows:
Typematic rate

= 10.9 characters per second

± 20%.

Delay = 500 milliseconds ± 20%.
The execution of this command stops without change to the
existing rate if another command is received instead of the
rate/ delay value byte.

4-12

Keyboard

Commands to the System
The following table shows the commands that the keyboard may
send to the system, and their hexadecimal values.
Command
Key Detection Error/Overrun
Keyboard ID
BAT Completion Code
BAT Failure Code
Echo
Acknowledge (ACK)
Resend
Key Detection Error/Overrun

Hex Value
00 (Code Sets 2 and 3)
83AB
AA
FC
EE
FA
FE
FF (Code Set 1)

The commands the keyboard sends to the system are described
below, in alphabetic order. They have different meanings when
issued by the system (see "Commands from the System" on
page 4-6).

Acknowledge (Hex FA)
The keyboard issues Acknowledge (ACK) to any valid input
other than an Echo or Resend command. If the keyboard is
interrupted while sending ACK, it discards ACK and accepts and
responds to the new command.

BAT Completion Code (Hex AA)
Following satisfactory completion of the BAT, the keyboard
sends hex AA. Any other code indicates a failure of the
keyboard.

BAT Failure Code (Hex FC)
If a BAT fai1ur~ occurs, the keyboard sends this code,

discontinues scanning, and waits for a system response or reset.

Echo (Hex EE)
The keyboard sends this code in response to an Echo command.

Keyboard

4-13

Keyboard ID (Hex 83AB)
The Keyboard ID consists of 2 bytes, hex 83AB. The keyboard
responds to the Read ID with ACK, discontinues scanning, and
sends the 2 ID bytes. The low byte is sent first followed by the
high byte. Following output of Keyboard ID, the keyboard begins
scanning.

Key Detection Error (Hex 00 or FF)
The keyboard sends a key detection error character if conditions
in the keyboard make it impossible to identify a switch closure. If
the keyboard is using scan code set 1, the code is hex FF. For
sets 2 and 3, the code is hex 00.

Overrun (Hex 00 or FF)
An overrun character is placed in the keyboard buffer and
replaces the last code when the buffer capacity has been
exceeded. The code is sent to the system when it reaches the top
of the buffer queue. If the keyboard is using scan code set 1, the
code is hex FF. For sets 2 and 3, the code is hex 00.

Resend (Hex FE)
The keyboard issues a Resend command following receipt of an
invalid input or any input with incorrect parity. If the system
sends nothing to the keyboard, no response is required.

4-14

Keyboard

Keyboard Scan Codes
The following tables list the key numbers of the three scan code
sets and their hexadecimal values. The system defaults to scan set
2, but can be switched to set 1 or set 3 (see "Select Alternate
Scan Codes (Hex FO)" on page 4-8).

Keyboard

4-15

Scan Code Set 1
In scan code set 1, each key is assigned a base scan code and, in
some cases, extra codes to generate artificial shift states in the
system. The typematic scan codes are identical to the base scan
code for each key.

Scan Code Tables (Set 1)
The following keys send the codes as shown, regardless of any
shift states in the keyboard or the system. Refer to "Keyboard
Layouts" beginning on page 4-40 to determine the character
associated with each key number.
Key Number

Make Code

Break Code

29
02
03
04
05
06
07
08
09
OA
OB

A9
82
83
84
85
86
87
88
89
8A
8B
8e
80
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
AB
BA
9E
9F
AO

1
2
3
4
5
6
7
8
9

10
11
12
13
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33

*

4-16

oc

*

00
OE
OF
10
11
12
13
14
15
16
17
18
19
lA
lB
2B
3A
lE
lF
20

101-key keyboard only.

Keyboard

I

Key Number

Make Code

Break Code

34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
57
58
60
61
62
64
90
91
92
93
96
97
98
99
100
101
102
103
104
105
106
108
110
112
113
114
115
116
117
118
119

21
22
23
24
25
26
27
28
2B
lC
2A
56
2C
20
2E
2F
30
31
32
33
34
35
36
10
38
39
EO 38
EO 10
45
47
4B
4F
48
4c
50
52
37
49
40
51
53
4A
4E
EO lC
01
3B
3C
3D
3E
3F
40
41
42

Al
A2
A3
A4
A5
A6
A7
A8
AB
9C
AA
06
AC
AD
AE
AF
BO
Bl
B2
B3
B4
B5
B6
90
B8
B9
EO B8
EO 90
C5
C7
CB
CF
C8
cc
DO
02
B7
C9
CO
01
03
CA
CE
EO 9C
81
BB
BC
BO
BE
BF
CO
C1
C2

**

**
**

102-key keyboard only.

Keyboard

4-17

Key Number

Make Code

Break Code

120
121
122
123
125

43
44
57
58
46

C3
c4
D7
D8
C6

The remaining keys send a series of codes dependent on the state
of tile various shift keys (Ctrl, Alt, and Shift), and the state of
NUlll Lock (On or Off). Because the base scan code is identical
to that of another key, an extra code (hex EO) has been added to
the pase code to make it unique.
Key

Base Case, or
Shift+Num Lock
Make/Break

75

EO 52
lEO D2
EO 53
lEO D3
EO 4B
lEO CB
EO 47
lEO C7
EO 4F
lEO CF
EO 48
lEO c8
EO 50
lEO DO
EO 49
lEt> C9
EO 51
lEO Dl
EO 4D
lEO CD

~o.

76
79
80
~1

83
84
85
86
89

*

Sh i ft Case
Make/Break

*

EO AA EO 52
lEO D2 EO 2A
EO AA EO 53
lEO D3 EO 2A
EO AA EO 4B
lEO CB EO 2A
EO AA EO 47
lEO C7 EO 2A
EO AA EO 4F
lEO CF EO 2A
EO AA EO 48
lEO c8 EO 2A
EO AA EO 50
lEO DO EO 2A
EO AA EO 49
lEO C9 EO 2A
EO AA EO 51
lEO D1 EO 2A
EO AA EO 4D
lEO CD EO 2A

Num Lock on
Make/Break
EO 2A EO 52
lEO D2 EO AA
EO 2A EO 53
lEO D3 EO AA
EO 2A EO 4B
lEO CB EO AA
EO 2A EO 47
lEO C7 EO AA
EO 2A EO 4F
lEO CF EO AA
EO 2A EO 48
lEO C8 EO AA
EO 2A EO 50
lEO DO EO AA
EO 2A EO 49
lEO C9 EO AA
EO 2A EO 51
lEO Dl EO AA
EO 2A EO 4D
lEO CD EO AA

If the left Shift key is held down, the AA/2A shift make
and break is sent with the other scan codes. If the right
Shift key is held down, B6/36 is sent. If both Shift
keys are down, both sets of codes are sent with the other
scan code.

4-18

Keyboard

Key
No.

Scan Code Make/Break

Shift Case Make/Break

95

EO 35/EO B5

EO AA EO 35/EO B5 EO 2A

*

If the left Shift key is held down, the AA/2A shift make
and break is sent with the other scan codes. If the right
Shift key is held down, B6/36 is sent. If both Shift
keys are down, both sets of codes are sent with the other
scan code.

Key
No.

Scan Code
Make/Break

124

EO 2A EO 37
/EO B7 EO AA

Key No.
126

*

*

*

Ctrl Case, Shift Case
Make/Break

Make Code
E1 10 45 El 90 C5

EO 371EO B7

Alt Case
Make/Break
54/04

Ctrl Key Pressed
EO 46 EO C6

This key is not typematic. All associated scan codes
occur on the make of the key.

Keyboard

4-19

Scan Code Set 2
In scan code set 2, each key is assigned a unique 8-bit make scan
code, which is sent when the key is pressed. Each key also sends
a break code when the key is released. The break code consists of
2 bytes, the first of which is the break code prefix, hex FO; the
second byte is the same as the make scan code for that key. The
typematic scan code for a key is the same as the key's make code.

Scan Code Tables (Set 2)
The following keys send the codes shown, regardless of any shift
states in the keyboard or system. Refer to "Keyboard Layouts"
beginning on page 4-40 to determine the character associated
with each key number.
Key Number
1
2
3
4
5
6
7
8
9
10
11
12
13
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

*

4-20

Make Code

*

OE
16
IE
26
25
2E
36
3D
3E
46
45
4E
55
66
00
15
10
24
20
2C
35
3C
43
44
40
54
5B
50
58
lC

101-key keyboard only.

Keyboard

Break Code
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO

OE
16
IE
26
25
2E
36
3D
3E
46
45
4E
55
66
00
15
10
24
20
2C
35
3C
43
44
40
54
56
50
58
lC

Key Number
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
57
58
60
61
62
64
90
91
92
93
96
97
98
99
100
101
102
103
104
105
106
108
110
112
113
114
115
116
117
118
119

**

**
**

Make Code
lB
23
2B
34
33
3B
42
4B
4C
52
50
5A
12
61
lA
22
21
2A
32
31
3A
41
49
4A
59
14
11
29
EO 11
EO 14
77
6C
6B
69
75
73
72
70
7C
70
74
7A
71
7B
79
EO 5A
76
05
06
04
OC
03
OB
83
OA

Break Code
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
EO
EO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
EO
FO
FO
FO
FO
FO
FO
FO
FO
FO

lB
23
2B
34
33
3B
42
4B
4C
52
50
5A
12
61
lA
22
21
2A
32
31
3A
41
49
4A
59
14
11
29
FO 11
FO 14
77
6C
6B
69
75
73
72
70
7C
70
74
7A
71
7B
79
FO 5A
76
05
06
04
OC
03
OB
83
OA

102-key keyboard only.

Keyboard

4-21

Key Number

Make Code

120
121
122
123
125

01
09
78
07
7E

Break Code
FO
FO
FO
FO
FO

01
09
78
07
7E

The remaining keys send a series of codes dependent on the state
of the various shift keys (Ctrl, Alt, and Shift), and the state of
Num Lock (On or Off). Because the base scan code is identical
to that of another key, an extra code (hex EO) has been added to
the base code to make it unique.
Key
No.

Base Case, or
Sh i ft+Num Lock
MakelBreak
EO
lEO
EO
lEO
EO
lEO
EO
lEO
EO
lEO
EO
lEO
EO
lEO
EO
lEO
EO
lEO
EO
lEO

75
76
79
80
81
83
84
85
86
89

*

4-22

70
FO
71
FO
6B
FO
6C
FO
69
FO
75
FO
72
FO
70
FO
7A
FO
74
FO

70
71
6B
6C
69
75
72
70
7A
74

Shift Case
MakelBreak
EO
lEO
EO
lEO
EO
lEO
EO
lEO
EO
lEO
EO
lEO
EO
lEO
EO
lEO
EO
lEO
EO
lEO

FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO

12
70
12
71
12
6B
12
6C
12
69
12
75
12
72
12
70
12
7A
12
74

EO
EO
EO
EO
EO
EO
EO
EO
EO
EO
EO
EO
EO
EO
EO
EO
EO
EO
EO
EO

*

Num Lock on
MakelBreak

70
12
71
12
6B
12
6C
12
69
12
75
12
72
12
70
12
7A
12
74
12

EO 12 EO 70
lEO FO 70 EO FO
EO 12 EO 71
lEO FO 71 EO FO
EO 12 EO 6B
lEO FO 6B EO FO
EO 12 EO 6C
lEO FO 6C EO FO
EO 12 EO 69
lEO FO 69 EO FO
EO 12 EO 75
lEO FO 75 EO FO
EO 12 EO 72
lEO FO 72 EO FO
EO 12 EO 70
lEO FO 70 EO FO
EO 12 EO 7A
lEO FO 7A EO FO
EO 12 EO 74
lEO FO 74 EO FO

12
12
12
12
12
12
12
12
12
12

If the Ieft Sh i ft key is held down, the FO 12/12 shift
make and break is sent with the other scan codes. If the
right Shift key is held down, FO 59/59 is sent. If both
Shift keys are down, both sets of codes are sent with the
other scan code.

Keyboard

Key
No.

Scan Code Make/Break

95

EO 4A1EO FO 4A

*

*

Shift Case Make/Break

EO FO 12 4A/EO 12 FO 4A

If the left Shift key is held down, the FO 12/12 shift
make and break is sent with the other scan codes. If the
right Shift key is held down, FO 59/59 is sent. If both
Shift keys are down, both sets of codes are sent with the
other scan code.

Key
No.

Scan Code
Make/Break

Ctrl Case, Shift Case
Make/Break

Alt Case
Make/Break

124

EO 12 EO 7C
/EO FO 7C EO FO 12

EO 7C/EO FO 7C

84/FO 84

Key No.
126

*

*

Make Code
E1 14 77 El FO 14 FO 77

Ctrl Key Pressed
EO 7E EO FO 7E

This key is not typematic. All associated scan codes
occur on the make of the key.

Keyboard

4-23

Scan Code Set 3
In scan code set 3, each key is assigned a unique 8-bit make scan
code, which is sent when the key is pressed. Each key also sends
a break code when the key is released. The break code consists of
2 bytes, the first of which is the break-code prefix, hex FO; the
second byte is the same as the make scan code for that key. The
typematic scan code for a key is the same as the key's make code.
With this scan code set, each key sends only one scan code, and
no keys are affected by the state of any other keys.

Scan Code Tables (Set 3)
The following keys send the codes shown, regardless of any shift
states in the keyboard or system. Refer to "Keyboard Layouts"
beginning on page 4-40 to determine the character associated
with each key number.
Key Number

Make Code

1
2
3
4
5
6
7
8
9
10
11
12
13
15
16
17
18
19
20
21
22
23
24
25
26
27
28

OE
16
IE
26
25
2E
36
3D
3E
46
45
4E
55
66
00
15
10
24
20
2C
35
3C
43
44
40
54
5B

4-24

Keyboard

Break Code
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
Fa
Fa
Fa
FO
FO
FO

OE
16
1E
26
25
2E
36
3D
3E
46
45
4E
55
66
00
15
10
24
20
2C
35
3C
43
44
40
54
5B

Default Key State
Typematic
Typematic
Typematic
TYDematic
Typemat'c
Typemat c
Typemat c
Typemat c
Typemat c
Typemat c
Typemat c
Typemat c
Typemat c
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic

Key Number
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
57
58
60
61
62
64
75
76
79
80
81
83
84
85
86
89
90
91
92
93
95
96
97
98

*
**

*

**
**

Make Code
5C
14
lC
lB
23
2B
34
33
36
42
46
4C
52
53
5A
12
13
lA
22
21
2A
32
31
3A
41
49
4A
59
11
19
29
39
58
67
64
61
6E
65
63
60
6F
60
6A
76
6C
6B
69
77
75
73
72

Break Code
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO

5C
14
1C
lB
23
2B
34
33
3B
42
4B
4C
52
53
5A
12
13
lA
22
21
2A
32
31
3A
41
49
4A
59
11
19
29
39
58
67
64
61
6E
65
63
60
6F
60
6A
76
6C
6B
69
77
75
73
72

Default Key State
Typematic
Make/Break
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Make/Break
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Make/Break
Make/Break
Make/Break
Typematic
Make only
Make only
Make only
Typematic
Typematic
Make only
Make only
Typematic
Typematic
Make only
Make only
Typematic
Make only
Make only
Make only
Make only
Make only
Make only
Make only
Make only

101-key keyboard only.
102-key keyboard only.

Keyboard

4-25

Key Number

Make Code

99
100
101
102
103
104
105
106
108
110
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126

70
7E
7D
74
7A
71
84
7C
79
08
07
OF
17
IF
27
2F
37
3F
47
4F
56
5E
57
5F
62

Break Code
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO

70
7E
7D
74
7A
71
84
7C
79
08
07
OF
17
IF
27
2F
37
3F
47
4F
56
5E
57
5F
62

Default Key State
Make only
Make only
Make only
Make only
Make only
Make only
Make only
Typematic
Make only
Make only
Make only
Make only
Make only
Make only
Make only
Make only
Make only
Make only
Make only
Make only
Make only
Make only
Make only
Make only
Make only

!~

4-26

Keyboard

Clock and Data Signals
The keyboard and system communicate over the 'clock' and
, data' lines. The source of each of these lines is an
open-collector device on the keyboard that allows either the
keyboard or the system to force a line to an inactive (low) level.
When no communication is occurring, the 'clock' line is at an
active (high) level. The state of the 'data' line is held
active(high) by the keyboard.
When the system sends data to the keyboard, it forces the 'data'
line to an inactive level and allows the 'clock' line to go to an
active level.
An inactive signal will have a value of at least 0, but not greater
than +0.7 volts. A signal at the inactive level is a logical 0. An
active signal will have a value of at least +2.4, but not greater
than +5.5 volts. A signal at the active level is a logical 1.
Voltages are measured between a signal source and the dc
network ground.
The keyboard 'clock' line provides the clocking signals used to
clock serial data to and from the keyboard. If the host system
forces the 'clock' line to an inactive level, keyboard transmission
is inhibited.
When the keyboard sends data to, or receives data from the
system, it generates the 'clock' signal to time the data. The
system can prevent the keyboard from sending data by forcing the
'clock' line to an inactive level; the 'data' line may be active or
inactive during this time.
During the BAT, the keyboard allows the 'clock' and 'data' lines
to go to an active level.

Data Stream
Data transmissions to and from the keyboard consist of an II-bit
data stream (Mode 2) sent serially over the 'data' line. A logical
1 is sent at an active (high) level. The following table shows the
functions of the bits.

lOl/102-Key Keyboard

4-27

Bit
1
2
3
4
5
6
7
8
9
10
11

Function
Start bit (always 0)
Data bit 0 (least-significant)
Data bit 1
Data bit 2
Data bit 3
Data bit 4
Data bit 5
Data bit 6
Data bit 7 (most-significant)
Parity bit (odd parity)
Stop bit (always 1)

The parity bit is either 1 or 0, and the 8 data bits, plus the parity
bit, always have an odd number of 1'so
Note: Mode 1 is a 9-bit data stream that does not have a
parity bit or stop bit and the start bit is always 1.

Keyboard Data Output
When the keyboard is ready to send data, it first checks for a
keyboard-inhibit or system request-to-send status on the 'clock'
and 'data' lines. If the 'clock' line is inactive (low), data is
stored in the keyboard buffer. If the 'clock' line is active (high)
and the 'data' line is inactive (request-to-send), data is stored in
the keyboard buffer, and the keyboard receives system data.
If the 'clock' and 'data' lines are both active, the keyboard sends

the 0 start bit, 8 data bits, the parity bit, and the stop bit. Data
will be valid before the trailing edge and beyond the leading edge
of the clock pulse. During transmission, the keyboard checks the
'clock' line for an active level at least every 60 milliseconds. If
the system lowers the 'clock' line from an active level after the
keyboard starts sending data, a condition known as line contention
occurs, and the keyboard stops sending data. If line contention
occurs before the leading edge of the 10th clock signal (parity
bit), the keyboard buffer returns the 'clock' and 'data' lines to
an active level. If contention does not occur by the 10th clock
signal, the keyboard completes the transmission. Following line
contention, the system mayor may not request the keyboard to
resend the data.

4-28

lOl/102-Key Keyboard

~l
~

Following a transmission, the system can inhibit the keyboard
until the system processes the input, or until it requests that a
response be sent.

Keyboard Data Input
When the system is ready to send data to the keyboard, it first
checks to see if the keyboard is sending data. If the keyboard is
sending, but has not reached the 10th 'clock' signal, the system
can override the keyboard output by forcing the keyboard 'clock'
line to an inactive (low) level. If the keyboard transmission is
beyond the 10th 'clock' signal, the system must receive the
transmission.
If the keyboard is not sending, or if the system elects to override
the keyboard's output, the system forces the keyboard 'clock'
line to an inactive level for more than 60 microseconds while
preparing to send data. When the system is ready to send the start
bit (the 'data' line will be inactive), it allows the 'clock' line to
go to an active (high) level.

The keyboard checks the state of the' clock' line at intervals of
no more than 10 milliseconds. If a system request-to-send (RTS)
is detected, the keyboard counts 11 bits. After the 10th bit, the
keyboard checks for an active level on the 'data' line, and if the
line is active, forces it inactive, and counts one more bit. This
action signals the system that the keyboard has received its data.
Upon receipt of this signal, the system returns to a ready state, in
which it can accept keyboard output, or goes to the inhibited state
until it is ready.
If the keyboard 'data' line is found at an inactive level following
the 10th bit, a framing error has occurred, and the keyboard
continues to count until the 'data' line becomes active. The
keyboard then makes the 'data' line inactive and sends a Resend.

Each system command or data transmission to the keyboard
requires a response from the keyboard before the system can send
its next output. The keyboard will respond within 20 milliseconds
unless the system prevents keyboard output. If the keyboard
response is invalid or has a parity error, the system sends the
command or data again. However, the two byte commands
require special handling. If hex F3 (Set Typematic Rate/Delay),

lOl/102-Key Keyboard

4-29

hex FO (Select Alternate Scan Codes), or hex ED (Set/Reset
Mode Indicators) have been sent and acknowledged, and the
value byte has been sent but the response is invalid or has a parity
error, the system will res end both the command and the value
byte.

Keyboard Encoding and Usage
The keyboard routine, provided by IBM in the ROM BIOS, is
responsible for converting the keyboard scan codes into what will
be termed Extended ASCII. The extended ASCII codes returned
by the ROM routine are mapped to the U.S. English keyboard
layout. Some operating systems may make provisions for
alternate keyboard layouts by providing an interrupt replacer,
which resides in the read/write memory. This section discusses
only the ROM routine.
Extended ASCII encompasses 1-byte character codes, with
possible values of 0 to 255, an extended code for certain extended
keyboard functions, and functions handled within the keyboard
routine or through interrupts.

Character Codes
The character codes described later are passed through the BIOS
keyboard routine to the system or application program. A" -1 "
means the combination is suppressed in the keyboard routine.
The codes are returned in the AL register. See "Characters,
Keystrokes, and Color" later in this manual for the exact codes.

4-30

lOl/102-Key Keyboard

The following figure shows the keyboard layout and key
positions.

mIl ~ 1111 ~ 11

mmmmrn
mrnmmr=ll
mrnmrnu

mm [!]
m mm mrn
m mm m
mJ

lOl/102-Key Keyboard

4-31

Key

Base Case

Uppercase

I

1
2
3
4
5
6
7
8
9
10
11
12
13
15

'"
!

1
2
3
4
5
6
7
8
9
0

@

#
$
%

"

&

*
(
)

-

+

=

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30 Caps
Lock
31
32
33
34
35
36
37
38
39
40
41
43
44 Sh ift
(Left )
46
47
48

Backs)ace
(008
-.1 (009)

Backs)ace
(008
I+- (*)
Q

q

w

w

e
r
t
y
u
i

E
R
T
y

U
1

0

0

p

p
{
}

[
]

\

I

-i

a
s
d
f
g
h

I

-i

S
0

F
G
H
J

k
I

K
L

; I

:

CR(013)
-1

"

CR(013)
-1

z

x
c

z

X
C

r)

Notes:

(*)
(*)
(*)
(*)
(*)
(*)
(*)
(*)
(*)
(*)
(*)
(*)
(*)
(*)

(*)
DC1(0171
ETB(023)
ENQ(005)
DC2(018)
DC4(020)
EM(025)
NAK(021)
HT(009)
SI(015)
DLE(016)
Esc(027)
GS(029)
FS(028)

(*)
(*)
(*)
(*)
(*)
(*)
(* )
(*)
(*)
(*)
(*)
(*)
(*)
(*)
-1

4-32

tOl/t02-Key Keyboard

(*)
(*)
(*)
(*)
(*)
(*)
(*)
(*)
(*)
(*)
(*)
(*)

SOH(OOl)
DC3(019)
EOT(004)
ACK(006)
BEL (007)
BS(008)
LF(OlO)
VT(OI1)
FF(012)
-1
-1
LF(010)
-1

-1

SUB(026)
CAN(024)
ETX(003)

(*)
(*)
(*)

Refer to "Extended Functions" in this section.
( *) Refer to "Special Handling" in this section.

Character Codes (Part 1 of 2)

Alt

-1
-1
Nu I (000) (*)
-1
-1
-1
RS(030)
-1
-1
-1
-1
US(031)
-1
De1(1271

-i

A

j

Ctrl

I

Key
49
50
51
52
53
54
55
57 Shift
(Right)
58 Ctrl
(Left)
60 Alt
(Left)
61
62 Alt
(Right)
64 Ctrl
(Right)
90 Num
Lock
95
100
105
106
108
110
112
113
114
115
116
117
118
119
120
121
122
123
125 Scroll
Lock
126

Base Case

Uppercase

Ctrl

Alt

(*)
(*)
(*)
(*)
(*)
(*)
(*)
-1

n
m

M

•

<
>

I
-1

-1

SYN(022)
STX(002)
SO(014)
CR(on)
-1
-1
-1
-1

-1

-1

-1

-1

-1

-1

-1

-1

Space
-1

Space
-1

Space
-1

-1

-1

-1

-1

-1

-1

-1

-1

V

v
b

B
N

?

Enter
Esc
Null (*)
Null (*)
Null (*)
Null (*)
Null (*)
Null (*)
Null (*)
Null (*)
Null (*)
Null (*)
Null (*)
Null (*)
-1

Enter
Esc
Nu I (*)
Nu I (*)
Nu I (*)
Nu I (*)
Nu 1 (*)
Nu I (*)
Nu 1 (*)
Nu I (*)
Nu I (*)
Nu 1 (*)
Nu I (*)
Nu I (*)
-1

(*)
(*)
(*)
(*)
LF(010)
Esc
Null (*)
Null (*)
Null (*)
Null (*)
Null (*)
Null (*)
Null (*)
Null (*)
Null (*)
Null (*)
Null (*)
Null (*)
-1

Pause(**)

Pause(**)

Break(**)

~

1*

-

+

+

Space
-1

(*)
(*)
(*)
(*)
(*)
(*)
Nu 1(*)
Nu 1(*)
Nu 1(*)
Nu 1(*)
Nu 1(*)
Nu 1(*)
Nu 1(*)
Nu 1(*)
Nu 1(*)
Nu 1(*)
Nu 1(*)
Nu 1(*)
-1
Pause(**)

Notes:

1*)

Refer to "Extended Functions" in this section.
( *) Refer to "Special Handling" in this section.

Character Codes (Part 2 of 2)

lOl/102-Key KeybQard

4-33

lists

The following table
keys that have meaning only in Num
Lock, Shift, or Ctrl states. The Shift key temporarily reverses the
current Num Lock state.
Key

Num
Lock
7
4
1
8

Base Case

Ctrl

-1
-1
-1
-1
-1
-1
-1
-1
-1

Clear Screen
Reverse Word(*)
Erase to EOL(*)
(*)
(*)
(*)
(*)
Top of Text
and Home
Advance Word
(*)
Erase to EOS
i*)
( *)

Home (*)

91
92
93
96
97
98
99
101

5

2
0
9

End ( )
t (*)
(*)
+ (*)
Ins
Page Up (*)

102

6

... (*)

103

3

Pa~e

104

Alt

.. (*1

Down

-1

Delete (*,**)

(**)

( )

Notes:
(*1 Refer to "Extended Functions" in this section.
(* ) Refer to "Special Handling" in this section.
Special Character Codes

Extended Functions
For certain functions that cannot be represented by a standard
ASCII code, an extended code is used. A character code of 000
(null) is returned in AL. This indicates that the system or
application program should examine a second code, which will
indicate the actual function. Usually, but not always, this second
code is the scan code of the primary key that was pressed. This
code is returned in AH.

4-34

lOl/102-Key Keyboard

The following table is a list of the extended codes and their
functions.
Second
Code
1

3
14
15
16-25
26-28
30-38
39-41
43
44-50
51-53
55
59-68
71
72
73
74
75
76
77
78
79
80
81
82
83
84-93
94-103
104-113
114
115
116
117

118
119
120-131
132
133-134
135-136
137-138
139-140
141
142
143
144
145
146
147
148
149
150

Function
Alt
Esc
Nul Character
Alt
Backspace
+- (Back-tab)

!

It Q, W, E, R, T, Y, U, I, 0, P
Alt
[ ] ......

Alt A, S, D, F, G, H, J, K, l
Alt
Alt
Alt Z, " X, C, V, B, N, M
AI t , . /
Keypad *
Alt
Fl to FlO Function Keys (Base Case)
Home
t (Cursor Up)
Page Up
Alt
Keypad.. (Cursor left)
Center Cursor
-. (Cursor Right)
Alt
Keypad +
End
+ (Cursor Down)
Page Down
Ins (Insert)
Del (Delete)
Shift Fl to FlO
Ctrl Fl to FlO
AIt
F1 to FlO
Ctrl PrtSc (Start/Stop Echo to Printer)
Ctrl .. (Reverse Word)
Ctrl -. (Advance Word)
Ctrl End (Erase to End of Line-EOl)
Ctrl PgDn (Erase to End of Screen-EOS)
Ctrl Home (Clear Screen and Home)
AIt 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, -, = keys 2-13
Ctrl PgUp (Top 25 lines of Text and Cursor Home)
Fll, F12
Shift Fll, F12
Ctrl Fll, F12
Alt
Fl1 F12
Ctr I Up/S
Ctrl KeypadCtrl Keypad 5
Ctrl Keypad +
Ctr 1 Down/2
Ctrl Ins/O
Ctrl Del/.
Ctrl Tab
Ctrl Keypad ~
Ctrl Keypad
I

I

Keyboard Extended Functions (Part 1 of 2)

lOl/102-Key Keyboard

4-35

Second
Code

151
152
153
155
157
159
160
161
162
163
164
165
166

Function
Alt
Alt
Alt
Alt
Alt
Alt
Alt
Alt
Alt
Alt
Alt
Alt
Alt

Home
Up
Page Up
Left
Right
End
Down
Page Down
Insert
Delete
Keypad /
Tab
Enter

Keyboard Extended Functions (Part 2 of 2)

Shift States
Most shift states are handled within the keyboard routine, and are
not apparent to the system or application program. In any case,
the current status of active shift states is available by calling an
entry point in the BIOS keyboard routine. The following keys
result in altered shift states:
Shift: This key temporarily shifts keys 1 through 13, 16 through

29,31 through 41, and 46 through 55, to uppercase (base case if
in Caps Lock state). Also, the Shift temporarily reverses the
Num Lock or non-Num Lock state of keys 91 through 93, 96, 98,
99, and 101 through 104.

Ctrl: This key temporarily shifts keys 3, 7, 12, 15 through 29,31
through 39, 43, 46 through 52, 75 through 89, 91 through 93, 95
through 108, 112 through 124 and 126 to the Ctrl state. The Ctrl
key is also used with the Alt and Del keys to cause the
system-reset function; with the Scroll Lock key to cause the break
function; and with the Num Lock key to cause the pause function.
The system-reset, break, and pause functions are described under
"Special Handling" later in this section.

4-36

lOl/102-Key Keyboard

AIt: This key temporarily shifts keys 1 through 29,31 through
43,46 through 55, 75 through 89,95, 100, and 105 through 124
to the Alt state. The Alt key is also used with the Ctrl and Del
keys to cause a system reset.
The Alt key also allows the user to enter any character code from
1 to 255. The user holds down the Alt key and types the decimal
value of the characters desired on the numeric keypad (keys 91
through 93, 96 through 99, and 101 through 103). The Alt key is
then released. If the number is greater than 255, a modulo-256
value is used. This value is interpreted as a character code and is
sent through the keyboard routine to the system or application
program. Alt is handled internal to the keyboard routine.
Caps Lock: This key shifts keys 17 through 26, 31 through 39,
and 46 through 52 to uppercase. When Caps Lock is pressed
again, it reverses the action. Caps Lock is handled internal to the
keyboard routine. When Caps Lock is pressed, it changes the
Caps Lock Mode indicator. If the indicator was on, it will go off;
and if it was off, it will go on.
Scroll Lock: When interpreted by appropriate application
programs, this key indicates that the cursor-control keys will
cause windowing over the text rather than moving the cursor.
When the Scroll Lock key is pressed again, it reverses the action.
The keyboard routine simply records the current shift state of the
Scroll Lock key. It is the responsibility of the application
program to perform the function. When Scroll Lock is pressed, it
changes the Scroll Lock Mode indicator. If the indicator was on,
it will go off; and if it was off, it will go on.

Nom Lock: This key shifts keys 91 through 93,96 through 99,
and 101 through 104 to uppercase. When Num Lock is pressed
again, it reverses the action. Num Lock is handled internal to the
keyboard routine. When Num Lock is pressed, it changes the
Num Lock Mode indicator. If the indicator was on, it will go off;
if it was off, it will go on.
Shift Key Priorities and Combinations: If combinations of the
Alt, Ctrl, and Shift keys are pressed and only one is valid, the
priority is as follows: the Alt key is first, the Ctrl key is second,
and the Shift key is third. The only valid combination is Alt and
Ctrl, which is used in the system-reset function.

101/102-Key Keyboard

4-37

Special Handling
System Reset
The combination of any Alt, Ctrl, and Del keys results in the
keyboard routine that starts a system reset or restart. System
reset is handled by BIOS.

Break
The combination of the Ctrl and Pause/Break keys results in the
keyboard routine signaling interrupt hex lB. The extended
characters AL=hex 00, and AH=hex 00 are also returned.

Pause
The Pause key causes the keyboard interrupt routine to loop,
waiting for any character or function key to be pressed. This
provides a method of temporarily suspending an operation, such
as listing or printing, and then resuming the operation. The
method is not apparent to either the system or the application
program. The key stroke used to resume operation is discarded.
Pause is handled internal to the keyboard routine.

Print Screen
The Print Screen key results in an interrupt invoking the
print-screen routine. This routine works in the alphameric or
graphics mode, with unrecognizable characters printing as blanks.

System Request
When the System Request (Alt and Print Screen) key is pressed, a
hex 8500 is placed in AX, and an interrupt hex 15 is executed.
When the SysRq key is released, a hex 8501 is placed in AX, and
another interrupt hex 15 is executed. If an application is to use
System Request, the following rules must be observed:

4-38

lOl/102-Key Keyboard

Save the previous address.
Overlay interrupt vector hex 15.
Check AH for a value of hex 85:
If yes, process may begin.
If no, go to previous address.

The application program must preserve the value in all registers,
except AX, upon return. System Request is handled internal to
the keyboard routine.

Other Characteristics
The keyboard routine does its own buffering, and the keyboard
buffer is large enough to support entries by a fast typist.
However, if a key is pressed when the buffer is full, the key will
be ignored and the "alarm" will sound.
The keyboard routine also suppresses the typematic action of the
following keys: Ctrl, Shift, Alt, Num Lock, Scroll Lock, Caps
Lock, and Ins.
During each interrupt hex 09 from the keyboard, an interrupt hex
15, function (AH)=hex 4F is generated by the BIOS after the
scan code is read from the keyboard adapter. The scan code is
passed in the (AL) register with the carry flag set. This is to
allow an operating system to intercept each scan code prior to its
being handled by the interrupt hex 09 routine, and have a chance
to change or act on the scan code. If the carry flag is changed to
o on return from interrupt hex 15, the scan code will be ignored
by the interrupt handler.

lOl/102-Key Keyboard

4-39

Keyboard Layouts
The keyboard is available in six layouts:
•

French

•

German

•

Italian

• Spanish
• U.K. English
•

U.S. English

The various layouts are shown in alphabetic order on the
following pages. Nomenclature is on both the top and front face
of the keybuttons. The number to the upper right designates the
keybutton position.

4-40

French Keyboard

4-41

German Keyboard

4-42

Italian Keyboard

4-43

Spanish Keyboard

4-44

U.K. English Keyboard

4-45

U.s. English Keyboard

4-46

Specifications
The specifications for the keyboard are as follows.

Power Requirements
•
•

+5 Vdc ± 10%
Current cannot exceed 275 mA

Size
•
•
•

Length: 492 millimeters (19.4 inches)
Depth: 210 millimeters (8.3 inches)
Height: 58 millimeters (2.3 inches), legs extended

Weight
2.25 kilograms (5.0 pounds)

4-47

--
-->
-->
-->

TEST2.ASM

31

32

n

TEST3.ASM
TEST4.ASM

3'
3.
3T
3.

-->
-->

POST AND MANUFAC1'URING TEST ROUTINES
DATA SEGMENTS LOCATIONS
COt,tMON EQUATES FOR POST AND BIOS
POWER ON SELF TEST EQUATES FOR PROTECTED MODE
POST TEST.OI THROUGH TEST. 16

PO~S~E~~S~~~ 7 I~~~~n~~ Z;~~~~ 2~OUT I NES
POST EXCEPTION INTERRUPT TESTS
POST AND 8105 UTILITY ROUTINES
CMOS READ
- READ CMOS L.OCAT I ON ROUT I NE

g~gS:WRITE

42

.,••
,.••••

:
-

BLIRK INT

:
- MANUFACTURING TOGGLE BIT ROUTINE

~~~:~~i~~SUM

51
52

.3

~~T-~D

••
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,.

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TEST6.ASM

.3

••
.,••••

.

••,.

POST ERROR MESSAGE HANDLER
MANUFACTUR I NO, ERROR TRAP
POST STRING DISPLAY ROUTINE
POST ERROR BEEP PROCEDURE
SPEAKER BEEP CONTROL ROUT I NE
FIXED TIME WAIT ROUTINE
SET BAD CONFIG IN CMOS DIAo,
DISPLAY-HEX BYTE AS 00-- FF
0 I SPLAY CHARACTER
DISPLAY SEGMENT FORMAT ADDRESS
POST PROTECTED MODE 0 I SPLAY

=~~~~~~~::~~I~~~~A~5~~::SUM
~~~~ ~~;E~~3=T C~~~D~~~

:
I
_> I NT 11"
RE 0 I RECT
- HARDWARE I NT 9 RED I RECT (L 2)
INT 287
- HARDWARE INT 13 REDIRECT (287)
PRO~ SHUTDOWN - 80286 RESET ROUTINE
EXCEPTTON INTERRUPT TEST HANDLERS f'OR POST TESTS
SYSINITI
- BUILD PROTECTED MODE POINTERS
GOT BLD
- BU I LD THE GOT FOR POST
SloT BLD
- BUILD THE lOT FOR POST
POST T!STS AND SYSTEM BOOT STRAP
STo,TST CNT
- SEGMENT STORAGE TEST
ROM ERR'
- ROM ERROR 0 I SPLAY ROUT I NE
XMIT 8042
- KEYBOARD DIAGNOSTIC OUTPUT
BOOT:STRAP
- BOOT STRAP LOADER
-INT 19H

TEST!i .... SM

.2

~~l~E(g~~r ~~~~T~~~ARg~~~~T

E MSG
MrG HALT
P M!G
E~ BEEP
BEEJiS
WAITF
CONFIG BAD
XPC ByTE
PRT-HEX
PRT-SEG
PRoT PRT HEX

DSKETTE. ASM

OISKETTE BIOS

,.,.
'2

DISK.ASM

:
DSKETTE !'I!TUP - POST SETUP DR I VE TYPES
FIXED DISR' 8105

TO
TO

KYBD.ASM

HD IRT
KEYBt5'ARD B I OS

g:~~ET~~_:O_1

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PRT.ASM
RS232.ASM
VIDEOI.ASM
BIOS.ASM

.,

BIOSI.ASM

PRO~ TERM
EVENT WAIT
.JOY STICK
SYS-REQ
WAIT
BLOCKMOVE
GATE A20

.

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I ••

BIOS2.ASM

I ••

ORGS.ASM

II.

I ••

I ••
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TESTl

: ~~t~ g~~: g: gr~~E H~~~~~~R
-

-INT 16H
-INT 09H
-INT 17H
-INT 14H
-INT IOH
-INT
-INT
- iNT
-INT

12H
IIH
02H
ISH

NULL PROGRAM TERMINATION
RTC EVENT WAIT/TIMEOUT ROUTINE
.JOYSTICK PORT HANDLER
NULL SYSTEM REQUEST KEY
RTC TIMED WAIT ROUTINE
EXTENDED MEMORY MOVE INTERFACE
ADDRESS BIT 20 CONTROL

~~T~~~E~R:~~:~R ~~E ~~~~:~ =~DE

5
:
V
I
DEVTcE BUSY
- NULL DEV I CE BUSY HANDLER
I NT COfllPLETE - NULL I NTERRUPT COMPLETE HANDLER
B I OS TNTERRUPT ROUT I NES
TIME OF DAY I - TIME OF DAY ROUTINES
-INT IAH
RTC TNT- IRQ LEVEL 8 ALARM HANDLER -INT 70H

~~_~~;ETNI

I ••

: ~~~U~3~1~~0~E~~~~~ AND TEST_ INT 13H
- HARDWARE INTERRUPT HANDLER -INT 7EtH

~:Y~~;R~_IO_I : ~~~D~:~EB:~~E~~~~+
SNl5' DATA
- KEYBOARD TRANSMISSION
PRINT!Jit ADAPTER BIOS
COMMUNICATIONS BIOS FOR RS232
VIDEO BIOS
BIOS ROUTINES
MEMORY SIZE DET I - REAL MODE SIZE
EQU I PMl!NT 1- - -EQU I PMENT DETERM I NAT I ON
NYI INT ,- NMI HANDLER
INTERR'UPT-15H BIOS ROUTINES

:~-~~E

'2

5-18

-->
-->
-->

~~~D~:~EB:~~E~~~~~ ~:~~ER ::~~ ~~~

~~~~I S~:~~~R~~¥T~~~DLER -;:~~ ~~~

:
COMPATI§ILITY MODULE
POST ERROR MESSAGES
DISKETTE - DISK - VIDEO DATA TABLES

:
I

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0020

0040

nnn??

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131

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0060
0060

140

nnnn

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143
144

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146

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141

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115

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116

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160
161
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163
16.
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16.
167

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169
110
1'71
112
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0001 11111111

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•••
•••
•••
•••
•••

10216 INTERRUPT LOCATIONS
REfI'EPtENCEO IY POST , II

•
I

SEGMENT AT 0

I ADDRESS. 0000.0000

01

I START OF INTERRUPT VECTOR TABLE

C

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131

1---------------------------------.. . ----1-------------------------------.as. . . . . . ----

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PAGE
I NCLUDI DSEa. I Ne

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ORG
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gC .'1 I DEO_I NT
gC eGRG_VECTOR
gC ftASIC_PTR

ORG
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ORG
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I DISKETTE/DISK INTERRUPT VECTOR

ORG
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I POINTER TO CASSETTE BASIC

C
g
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gC eoISK_POINTE"
gC eEXT_PTR
gC tID I SK_VECTOR
gC ....._TL_VEC
gC ..... '_TL_VEC
gC .SLAVE_INT_PTR
gC eHlISK_INT

ORG
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C
C
C
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ORG
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I PO I NTER TO 0 I SKETTE I NTERRUPT CODE

ORG
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I POINTER TO FIRST DISK PARAMETER TABLE

ORG
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I POINTER TO SECOND DISK PARAMETER TABL.E

oRG
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DO?

I POINTER TO SLAVE INTERRUPT HANDLER

oRG
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I POINTER TO FIXED DISK INTERRUPT CODE

• STACK -- USED DURING POST ONLY
I
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DIDO

0100

g ....G_TEST_RTN

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LABEL

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FAR

I LOAD LOCATION FOR MANUFACTURING TESTS

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TCOO

g .aoOT_LOCN

ORG
LABEL

lCOOH
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I BOOT STRAP CODE LOAD L.OCATION

TCOO

C

ENDS

C

ABSO

TESTl

5-19

1-3
04-21-86

IT.
IT.
ITT

27.

PAGE
, . --------------------.- ---.------ -- - - ---

C

,-- ----------------.-- ------ ------ --. - ---

c,

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179
180
181
102
18.
114
185
18.
lOT
188
18'
190
191
192
19.
194
195
19.
19T
190
19.
200
201
202
20.
204
200
20.
20T
208
20.
210
211
212
213
214
215
21.
21 T
218
219
220
221
222
223
224
22.
22.
22T
228
22.
230
231
232
233
234
235
23.
23T
238
23'
240
241
242
243
244
240
24.
24T
240
24.
250
251
252
253
2'4
2.0
25.
257
2.0
25'
2.0
2.,
2.2
263
2.4
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c
c
c

0002 1111

1111

0006 1111

c

0008 1111

c
c

OOOA 1111

aooe 7111

c
c
c
c
c

OOOE 1111
0010 1111
0012 11

0013 1111
0015 11
0016 11

0017 11

0018 11
0019 11
OOIA 1111
ODIC 1111

10

ODIE

SEGMENT AT 40H

DATA

c

0000 1111
OOO~

ROM BIOS DATA AREAS

1111

.EQUIP FL. ... G
.MFG TST

I
t

DW
DW
DW
DW
DW
DW
DW
DW
DW

SECOND L.OGICAL RS232 ADAPTER

DB

OMEMO'RY 5 I ZE

DW

OMFG_ERR'_FLAG

DB

ADDRESS= 0040 I 0000
BASE ADDRESSES OF RS232 ADAPTERS

c
DB
c
c ; ---------------------------------------KEYBOARD DATA AREAS
:
c I
c I -- - - - ------------- - ------- - -- - ------- --c
DB
I
c OKB FLAG
DB
;
c OKB-FLAG I
;
c OALT INPUT
DB
1
DW
c OBUFrER HEAD
c OBUFFER:TA I L
I
DW
c
HEAD = TAIL
INDICATES THAT
c ;-----c
DW
16 DUP! 1)
I
c
c
c
c
c ;---------------------------------------DISKETTE OAT A AREAS
:
c 1
c ;------- ---- ------------------------c
c
DB
c
c
DB
c
c
c
DB
c OMOTOR COUNT
;
c ODSKETTE_STATUS DB
1
c
7 DUP(?)
DB
I
c
c
c
c
c
c ;---------------------------------------VIDEO DISPLAY DATA AREA
:
c I
c 1- - --------------------- ---------- - - ----c
1
DB
c
?
1
c
DW
?
;
DW
c
?
I
DW
c
?
DW
c
e DUP! 1)
;
c
c
c
DW
c OCURSOR MODE
c OACTIVE-PAGE
DB
DW
c OADCR 684e
c OCRT gODE SET DB
c OCRT:PALETTE
DB
c
c I ----- ---------------- -- ---------- - - - - --POST AND B I OS WORK OAT A AREA
I
c ;
c 1------------- --------------- -----------c
I
c

RESERVED
RESERVED
BASE ADDRESSES OF PR I NTER ADAPTERS
SECOND LOG I CAL PR I NTER ADAPTER
THIRD LOGICAL PRINTER ADAPTER
RESERVED
INSTALLED HARDWARE FLAGS
INITIALIZATION FLAGS
IX 1024)
BASE MEMORY SIZE IN K BYTES
SCRATCHPAD FOR MANUFACTURING
ERROR CODES

KEYBOARD SHIFT STATE AND STATUS FLAGS
SECOND BYTE OF KEYBOARD STATUS
STORAGE FOR ALTERNATE KEY PAD ENTRY
PO I NTER TO HEAD OF KEYBOARD BUFFER
PO I NTER TO TAl L OF KEYBOARD BUFFER
THE BUFFER IS EMPTY
ROOM FOR 1 5 SCAN CODE ENTR I ES

-- - -

003E 11
D03F 1?

0040 11
004! 11

0042

OT

??

0049 11

004'" 1111
004C 1111
QO ...E 1111
0050
08

1111
0060
0062
0063
0065
0066

1111
11
1111
11
11

0061 1111
0069 1111
006B 11

c
c

OlD ROM INIT
OIO-ROM-SEG

DRIVE RECALIBRATION STATUS
BIT 3-0 = DRIVE 3-0 RECALIBRATION
BEFORE NEXT SEEK IF B IT I S = 0
MOTOR STATUS
BIT 3-0 = DRIVE 3-0 CURRENTLY RUNNING
BIT 7 = CURRENT OPERATION IS A WRITE
T I ME OUT COUNTER FOR MOTOR IS) TURN OFF
RETURN CODE STATUS BYTE
CMO BLOCK
IN STACK FOR DISK OPERATION
STAfus BYTES FROM DISKETTE OPERATION

CURRENT DISPLAY MODE (TYPE)
NUMBER OF COLUMNS ON SCREEN
LENGTH OF REGEN BUFFER I N BYTES
STARTING ADDRESS IN REGEN BUFFER
CURSOR FOR EACH OF UP TO 8 PAGES

CURRENT CURSOR MODE SETTING
CURRENT PAGE BEING DISPLAYED
BASE ADDRESS FOR ACTIVE DISPLAY CARD
CURRENT SETTING OF THE 3xe REGISTER
CURRENT PALETTE SETTING - COLOR CARD

STACK SAVE, etc.
; POINTER TO ROM INITIALIZATION ROUTINE
I POINTER TO I/O ROM SEGMENT
FLAG INDICATING AN INTERRUPT HAPPENED

DW
DW

I
c OINTR_FLAG
DB
c
c 1---- - ------------- --- -- ---- --------- - --TIMER DATA AREA
:
c I
c ;-------------------------------c
I
DW
c OTIMER LOW
1
DW
c OTiMER-HIGH
;
DB
c OTIMER:OFL
c
c ;---------------------------------------SYSTEM DATA AREA
:
c 1
c
-------------------c
1
DB
c OBIOS BREAK
I
c ORE SET_FLAG
DW
c
c 1-------------------- --- ---------- --- ---FIXED DISK DATA AREAS
I
c ;
c 1---- - ------------------ ---------- - - - ---c
c .DISK STATUS! DB
c OHF NOM
DB
c OCO'RTROL BYTE DB
c OPORT_OFr
DB

--- ----

OD6e 1111
006E 1111

0070 11

;------ -- --------

0071 11
0072 1111

0074 11

0075 11
0076 11

DOn 11

5-20

TESTl

LOW WORD OF T I MER COUNT
HIGH WORD OF TIMER COUNT
T I MER HAS ROLLED OVER SINCE LAST READ

---

BIT 7=1 IF BREAK KEY HAS BEEN PRESSED
WORD=1234H IF KEYBOARD RESET UNDERWAY

FIXED DISK STATUS
COUNT OF FIXED DISK DRIVES
HEAD CONTROL BYTE
RESERVED (PORT OFFSET)

T~~~I P~~~~n~!/~~ic~t·~O=~~RgN A;:~~b +:~T I~~~~j on

2.00
OSEG.INC - OATA SEGMENTS

280
201
282
283
20'
28'
280
2BT
2 ••
20'
2'0
2.,
2.2
2.3
2 ••
2 ••
2'0
2.T
2 ••
2"
300
301
302
303
30'
30'
300
30T
308
30'

liD

311
lI2
lI3
lI.
lI.
lIO
31T
lI.
lI.
320
321
322
323

...
320
320
32T
32.
32'
3.0

..,
"2
333

•••
•••

0018
0019
OOlA
OOla
OOlC
DOlO
DOTE
OOTF

71
11
71
11
11
11
71
71

0080 7171
0082 7171

0084
008S
0087
0088
0089
008A

008B
008C
0080
008E
008F
0090
0091
0092
0093
0094
00'ii'5

0096
0091

71
1711
71
71
71
71

71
71
71
71
71
71
71
11
71

71
71

11
11

"0
•• T

..••••••,
"0
•• 2
•• 3

•••
•••
•••
•••,

0098
009A
009C
009E
OOAO

7171
7171
7171
7171
11

"0
•• T

..

•• 0

OOAI

OT (

11

•• 2
•• 3

•••
•••
.OT
•••
•••
•• 0

.00
.01
'02
.03
'0'
'0'
.00

'67

'0.
.0.
'TO

'71

.T2

00A8 11111111

0100
0100
0101

11

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1-'

04-21-86

PAGE
1 ----------------------- - -- - -- - - - -------I
TIME-OUT VARIABLES
I

,----------------------------------------

OPRINT_TIM_OUT

ORS232_ TIM_OUT

T I ME OUT COUNTERS FOR PR I NTER RESPONSE
SECOND LOG I CAL PR I NTER ADAPTER
TH I RD LOG I CAL PR I NTER ADAPTER
RESERVED
TI ME OUT COUNTERS FOR RS232 RESPONSE
SECOND LOG I CAL RS232 ADAPTER
RESERVED
RESERVED

DB
DB
DB
DB
DB
DB
DB
DB

1---------- ------- ------------------ ----,
ADDITIONAL KEYBOARD DATA AREA
I
1-------- -------- ------------------- ----OBUFFER START
OBUFFER:END

I BUFFER LOCATION WITHIN SEGMENT 40H
I OFFSET OF KEYBOARD BUFFER START
I OFFSET OF END OF BUFFER

OW
OW

1----------- ---- ------------- ------- -----

,--------------- ----------.--------------,

EGA I PGA 0 I SPLAY WORK AREA

OROWS
OPOINTS
OINFD
OINFO_3

t

ROWS ON THE ACTI VE SCREEN 1LESS I)
BYTES PER CHARACTER
MODE OPTIONS
FEATURE BIT SW ITCHES
RESERVED FOR DISPLAY ADAPTERS
RESERVED FOR DISPLAY ADAPTERS

DB
OW
DB
DB
DB
DB

1--------------- -------------------- ----1
ADDITIONAL MEDIA DATA
I
1---------- ------ ------------------- ----OLASTRATE
OHF STATUS
OHF-ERROR
OHF-INT FLAG
OHF-CNTftL
OOSI(_STATE

ODSK_TRK

DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB

LAST DISKETTE DATA RATE SELECTED
STATUS REGISTER
ERROR REG I STER
FIXED DISK INTERRUPT FLAG
COMBO FIXED DISK/DISKETTE CARD BIT 0_1
DRIVE 0 MEDIA STATE
DRIVE I MEDIA STATE
DRIVE 0 OPERATION START STATE
DRIVE I OPERATION START STATE
DR I VE 0 PRESENT CYL I NDER
DRIVE I PRESENT CYLINDER

1--- - - -- ------------------------- - - -----1
ADO I T I ONAL KEYBOARD FLAGS
I
1--- - --- ----------- .----- ------- - - - -----OKB FLAG 3
OKB:FLAG:2

DB
DB

I KEYBOARD MODE STATE AND TYPE FLAGS
I KEYBOARD LED FLAGS

1---------------------------------------1
REAL T I ME CLOCK DATA AREA
I
1 ------------ - --- ----- - ------- ------- ---1 OFFSET ADDRESS OF USERS WAIT FLAG
I SEGMENT ADDRESS OF USER WA I T FLAG
I LOW WORD OF USER WA I T FLAG
I HIGH WORD OF USER WAIT FLAG
I WAIT ACTIVE FLAG (OlaBUSY, 80=POSTEC)
100=POST ACKNOWLEDGED)
I
1-- ----------- ------- ---- -- -- -- ---------I
AREA FOR NETWORK ADAPTER
I
1- - ----------- ------- ----- - - - -------- ---ONET

DB

1 DUPI?)

I

RESERVED FOR NETWORK ADAPTERS

1----------------------------------------

I
EGA/PGA PALETTE POINTER
I
1- - -- -------------- -- ---- ------ - - --------

I POINTER TO EGA PARAMETER CONTROL BLOCK

DO

1 RESERVED
1---------------------------------------1
DATA AREA - PRINT SCREEN
1----------------------------------------I
ORG

OSTATUS_BYTE

DB

OATA

ENDS

100H

I ADDRESS= 0040 I 0 I 00

(REF 0050 I 0000)

PRINT SCREEN STATUS BYTE
OI=BUSY, FF=ERROR
OO=REAOY/OK,
1 END OF B I OS DATA SEGMENT

.LIST

TESTl 5-21

.-.

04-11-1'
na
114

n.
n,

an

n.
n,

a ••

•••

.....
a ••

•••
,
a.4

an
a ••

.19

a,.
a"
I"
.,a
a'4

•••

a. .
ItT
.91
a. .
400
4 ••
40.
4.a
4.4
4 ••
4.'
40T
4 ••
4.'
4'0
411
4.2
4.a
4.4
4 ••
416
4.T
4 ••
419
4.0
.2.
4 ••
4.a
424
421
4.'
42T
42 •
42'
4ao
4.,
43.
4aa
434
4a.
4a,
431
4a.
439
440
44.
442
443
444
441
44.
44T
44'
44'
41.
411
452
411
414
455
41'
4.T
45.
41'
4'.
461
4'2
4,a

• OOFC

• 0002
• 0000
• F'TlD
• F9FD

• 0060

• 0061
• OOP'I
• DaDe
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

ODeD
0001
0002
0010
0020
0040
0010
00'4
0001
0002
0004
0001
0010
0020
0040
0010

•
•
•
•
•

0001
0010
0020
0040
0010

•
•
•
•
•
•
•
•
•
•
•

0060
OOAA
OOAR
OOAD
OOAE
OOCO
DODO
OOOF'
ODED
OOFE
0001

•
•
•
•
•
•
•
•

00"
OOFE
OOFA
00F4
00F3
00F2
OOEE
ODED

•
•
•
•
•

DOFF
OOFE
OOFA
OOFO
OOAA

•
•
•
•
•
•
•
•
•
•

0045
0046
0031
0010
OOIA
0053
0052
002A
0036
0054

•
•
•
•
•
•
•

OOAB
0041
0054
0051
0051
ODED
OOEI

5-22 TESTl

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PAGE
INCLUDE POSTEau. INC

__ ......... _---------------- .................
,....................
,------ ............. _---_ ............. _----------------•
EQUATES USED BY POST AND liDS

RATCU~PII'I:
~AT().a_

EQU
.QU
IQU
EQU
EQU

,-- ......... _ ..... 042
IIOlitT A
IIORT-.
RAM "AR ON
"A"-"AR-DFJI'

KEYIOARD INTERFACE AND DIAGNOSTIC CONTROL ftEGISTERS -----------EQU
060H
1042 KEYBOARD SCAN CODE/CONTROL. fIORT
EQU
061H
PORT 8 READ/IRITE DIAGNOSTIC REGISTER
EQU
111100111
AN) MASK FOR PARITY CHECKING ENABLE ON
EQU
0000 I looa
Oft "ASK FOfII: PAR I TY CHECK I NG ENABLE OFF'

;=~

~~ggggg~:

S~K.

!QU
EQU
EQU
EQU
EQU
EQU
!QU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

Ooooooioa
Ooolooooa
001000001
010000008
10000000a

MODEL BYTE

SUI MCoEL BYTE

l,a1' ~Evlt

::~rzY-!RR

ftEFftESH alT
OUT2
10 CHECK

pARITY CHECK
STATUSiaoIitT
OUT rAI PIJI.~

'IPT " " FILL
CMD""DATA
KTlIIi 'NO
SYS P\.AG-

TIIAN! TWUT
Rev TIIauT
PAATTy _EVEN

OFCH
.O.H
GOGH

O,.,aOH
OF9FDH

• SYSTEM MODEL BYTE

I SYSTEM SUB-NODEL. TYPE

I BIOS REYISION LEVEL
I LPPEft L.IMIT + 131
I LOWD: LIMIT" 20X

I

;{~.:O~~T ~~T~H~~ :~;ITY ERROR
SPEAKEft QUWIIUT DATA ENABLE alT
REF'RESH TEST II T
SPEAKER T I MER DUT2 I NI-UT a I T
I/O (MEMORY I CICCK OCCl.Iftltl!O lIT MASK
MEMORY PAR I TY CHECK OCCUftftlED II T MASK
1042 STATUS POftT
a • +OUTPVr IUF'FEIt FLLL.
, • + INPUT BLFFER FULL
2 • -SYSTEM FLAG -POST/-SELF TEST
3 • -COMMAND/+DATA
4 • +KEYIOAltD 1N4IBITED
I • +TRANSMIT TIMEOUT
6 • +RECEIYE TIME OUT
7 • +PAftITY IS EVEN

.'4H

oooooooia
00000010.
00000100.
OOOOIOOOB
OOOIOOOOB
00100000.
01000000.
10000000B

1--------.. 8042 INPUT PORT lIT DEP'INITION SAVED IN ....G TST --- .. -------------- .. lASE MIMI
EQU
OOOOIOOOB
I BASE PL.ANAR 1t7w MEMORY EXTENSION 640/X
IASEiEM
EQU
000100008
I BASE PL.ANAR R/W MEMORY SIZE 256/512

:~_~

~:~

g~~ggggg:

: ~~~=L:~S~Y~:~T~~T~~E~:-;ACTURING

KEY::m_IN4IB

EQU

loooooooa

I KEYBOAPtD 1N4IBIT SWITCH BIT

1-.... - ......... - 1041 COMMANDS .... -- .... --------------- .. --- .. ------- ... ------------- .. ------EQU
060H
I WR I TE 1042 COMMAND BYTE
EQU
OAAH
1 8042 SELF TEST
SELF TEST INTR-"ACE CK
EQU
OAIH
1 CHECK 1042 INTERFACE COMMAND
DIS Ra:J EQU
OADH
I D I SABLE K!YBOAftD COMMAND
ENAIca:)
EQU
OAEH
1 ENABLE KEYBOARD COMMAND
RE~ 1042 IfIFUT EQU
OCOH
1 READ e042 .,.PUT PORT
DISA~ BTT20
EQU
ODDH
I DISABLE ADDRESS LINE BIT 20
ENABLE IITIO
EQU
ODFH
I ENABLE ADDRESS L.INE 81T 20
KY80 c:tK DATA
EQU
OEOH
I GET KEYBOARD CLOCK AND DATA COMMAND
SHUT:CIII)EQU
OFEH
I CAUSE A SHUTDOWN COMMAND
KYa)_CLK
EQU
OOIH
1 KEYBOARD CL.OCK BIT 0

1ft I 1£ 1042 L.OC

,---------- KEYBOARD/LED COMMAf«)S
KB RESET
EQU
OF'FH
KB-.ESEND
EQU
OFEH
KII-..AKE BREAK
EQU
OFAH
KB-U

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