7095_Data_Processing_System_Functional_Objectives_Mar1964 7095 Data Processing System Functional Objectives Mar1964
7095_Data_Processing_System_Functional_Objectives_Mar1964 7095_Data_Processing_System_Functional_Objectives_Mar1964
User Manual: 7095_Data_Processing_System_Functional_Objectives_Mar1964
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;.
DRAFT
..... -
""
' : IBM CONFIDENTIAL
Date: 1'1./19/63'
. Rev II 3/17/64
.;J
.
"
7095 DATA PROCESSING SYSTEM
FUNCTIONAL OBJECTIVES.
.. ·a ...· .
1.
DESCRIPTION
•
1. 1
The 7095 is a new Data Processing System which extends the 7090/
7094/7094-U line by means of new technology and new. systems
or ganization.
1. 2.
The r.ystem will operate il,1 either the 7094 -Compatible Mode or .
the 7095 Mode.
1.2..1
1
In the Compatible Mode all instructbns which do not
refer to input-output will be executed as in the 7094 or
7094-II.
Those instructions which ref\;):;r to input-output
will cause a trap to a fixed loca.tion where they will be
simulated in 7095 Mode.
1. 2. 2
In the 7095 Mode the system
u~ilizes
a new instruction
format and a modified instruction set.
1. 3
The 7095 allows for the attachment of NPL input! output devices
by means of NPL control units.
The 7095 Data Channel will be
designed to meet the NPL Interface of .these control units.
1. 4
Bulk StQrage (LCM) will be attached to the system by means of
a parallel transmit channel which will control the transfer of data
'.
between high speed storage and bulk storage.
\e
1.5
A modified 7095 Data Channel designed to meet a parallel interface
enables attachment of some
non~NPL
Interface devices to the 7095.
'r-'------------- ---- -'j
t- •
""
-2-
c
1.
DESCRIPTION (Continued)
1. 6
Storage Protection and a Real Time Clock System will be standard
equipment on the 7095.
1. 7
The system will also be able to operate il'l a Problem Program
Mode.
When operating in this mode the program is pr.evented
from executing certain instructions such as those affecting
storage protection and all input-output instructions.
If the system
is not in the Problem Program Mode it is said to be in the Monitor'
Mode.
Z.
OENERAL CHARACTERISTICS
, 2. 1
o
The system will normally operate in the 7095 Mode.
In its reset
status it will be in the 7095 Mode (not in Compatible Mode) and
in the Monitor Mode (not in Problem Program Mode).
All traps
will return the system to the 7095 and Monitor Mode.
2.2
When in the 7095 Mode, all instructions will have the following
format:
.
I
S -8
9
10- 13 1 14-17
Operation !Flag Tag I · Tag 2
T2
0
F
TI
2.2. I
18-35
Address Field
Y
Tag 1 specifics t~e index register in those operations
involvin~
an index register.
In other operations Tag I
d
specifies an index register by which the address is
modified.
!
•*'
c'
2.
GENERAL CHARACTERISTICS (Continue'd)
2.2.2
..
Tag 2 always specifics an index register by which the
address is modified .
2.2.3
The fla.g field (F) specifies indirect addressing.
2.2.4
There will be 15 index registers of 18 bits each.
2.2.5
The 18 bit address field allows for directly addressing
Z6Z t 144 words of core storage.
2.2.6
Those 7094 instructions which contain a decrement field
have been replaced by equivalent instructions in the new
,'
3.
format.
·(See Table 1 t Section 3.4)
OPERATIONAL CHARACTERISTICS OF CENTRAL PROCESSOR
3. 1
Addressing
3. 1. 1
The program counter, index registers, the index adder
and all address paths are 18 bits and address arithmetic
is performed modulo Z6Z, 144.
3.1.2.
Indexing is subtractive.
For those instructions which
allow double indexing the effective address is obtained
by subtracting the contents of the index registers
,speCified by Tag 1 and Tag Z from Y, the address field
of the instruction.
In those instructions which allow only
single indexing, the effective address is obtained by sub-
c\
tracting the contents of the index register specified by
Tag 2 from Y.
....1
"."
o
1.
CHANCES TO 7095 DA l'A PROCESSING SYSTEM
FUNCTIONAL OBJECTIVES
REVISION III dated 3/ 11/64
Scction 3. 1. 3 should read as follows:
"Indirect Addressing is possible on aU instructions. Spcci:'ri:l;':,
indirect addres sing docs not change the [unction 01 ~hc 'L'.:l~~ iiclJ:> 111
the instructiof\ as defined in Section 3. 1.2. The wu!-d cv:.::::.illl n:.'
the direct address is fetched from the location spcci [iwd by tht.! cffcctive address of the instruction;
(T 1) .. (TZ) ] fo~: th0~C illFitructions which allow double indexing and [Y - ('1'2)J iQr l.il,;,riC
instructions which do not allow dvublc indexi:1;:.. The iorp.1.:lt oi t:.c
word fetchecl by the indirect' address is a~ fullvN::;:
LY -
S, 1-8
Not
Used
9
10-13
Flag Tag 2
yl
1'21
14 -17
T~2
1'21
-.-~
18 -35
Addrc S5 Field
y 1
'
I
When Fl is zero this word cont.lins the din.:ct addr(;bci. ,.",'ben 1'1 is
one this word contain!'> another indirect addr..:,,!;. In b.."li C ....·s..;;,:, ii1dependent of the instruction being ~xcc:.;tcd, tL...: elJ.t,;ctiv;.; ..... dd~-<.. s~) i-;
obta.ined by subtra.cting the ind\.!x rt.!gistcr!:! tip(.:.cificc.i by:' 11 ",'"d "_~.~ 1
from yl. ,Any nund.)er vf leveb of IndirecC addrcSbi!l.;'.... 1,; ',os;:;ii)l...:.
.
After the la!:>t level the use of the effective <.lddrcs;; d<..:pl! ;",i vn t!:c
instruction bei'ng executed and Inay rcprcsl!nt the IvC;.l.tI0:; 0: uter t
es the next
\
SeqU~ial instruction.
If the C(XR) s eoified by Tl are
greater than positi0ns 18-35 of C(Y}. the computer skips
a skip does
3. 6. 29
Ski
on Index
the computer skip
the C( XR) sp'eciiied
puter skips the next
3.6.30
the n xt sequential instruction.
If
1 are greater than Y, the com";
uential instruction.
With T 1 equal
Ski
--~----------~----~~~------~
If the C(XR) spjcified by T 1
/
18-35 of C( Yj then the comput r takes the next sequential
instructio;! 1£ the C(XR) are equ
18-35 of
skips the next s quential instruction.
equal to zero, a skip does not occur.
3. 6. 31
Ski
If
c\
n Index E ual Immediate (SXEI)
tIle C( XR) specified by T 1 are not equal to Y,
computer take s the next sequential instruction.
then the
1£ the
; t
-'-"-m=--==
,
..
..17-
.
OPERATIONAL CHARACTERISTICS OF CENTRAL PROCESSOR (Continued)
3. 6. 31
(Continued)
C{XR) are equal to Y. the computer skips the next sequential instructio'n.
With Tl equal to zero, a skip does
not occur.
3. 6. 3Z
Close Loop Forward
The contents of XRZ are added to the C(XR) speCified by
T 1 and the sum replace s the C( XR) specified by T 1.
The'
C(XR) specified by Tl is then compared with C(XR1).
If
C(XR .. Tl) are"less than or equal to C(XRl), the next
-
instruction is taken from location Y.
c
,
If C(XR ... T I)
~re
greater than C(XRI). the next sequential instruction is
taken.
3. 6. 33
Use of XRI and XRZi. implied by the instruction., .
Close Loop Reverse
Th~
contents of XRZ are to the C(XR) specified by T 1 and
the sum replaces the C(XR) specified by Tl.
The C(XR)
specified by TI is then compared with C(XRI).
If
C(XR-T I) are greater than or equal to C(XRI), the next
instruction is taken from location Y.
If C(XR-Tl) are
less than C(XRI), the next sequential instruction is taken.
Use of XRl and XRZ is implied by the instruction.
o
3.6.34
Exclusive OR to Storage (ERS)
The C( Y) are replaced by the result obtained by matching
bits of C(AC), positions P and 1-35, with the corresponding
..: .
..
c
-18-
3.
OPERATIONAL CHARACTERISTICS OF CENTRAL PROCESSOR (Continued)
3. 6. 34
(Continued)
bits of C( Y), positions S and 1-35.
The result will be a
,
one bit if one and only one of the two bits matched is a one
'bit.
Otherwise, the result is a zero bit.
The C(AC) are
unchanged.
3.6.35
OR Indicat()rs to Storage (OIS)
The C( Y) are replaced by the result obtained by matching,
bits of C(SI), positions 0-35, with the corresponding bits
of C( Y), positions 5 and 1-35.
A resulting bit will be a
one if either or both of the two bits matched is a one bit.
o
The result will be a zero only if both of the bits matched
are zeros,
3.6.36
The C(SI) are unchanged.
Place Characteristics in Index Register (PCHX)
This instruction places the C(AC) 1-8 into the specified
XR( 10 -1 7) and clear s the remaining bits of the XR.
3.
\
Section 3.6.37 Save CPU (SCPt;) should be changed to tbe iuL.·.·.'/l!
liThe C(AC) positions Sand 1-35 are stored in locatiorl Y. 'ILl:
flow trigger, the accumulator P and Q bits, and t.he Lhre..: inc.;x
\
OV\,~'
f
~e ister compare indicators (High, Low, ~d Equa~) arc sto~cc.l, in
th: left half of location Y + 1. Tag 1 SPCCiI1CS the l,nclcx re.~l,s..t\.;~,s
' h are to be stored. Index register 1 is stored 1n the l:'1~1-;'1. h_H
w h1 C .
..
'tl XRZ
. fIt'
\V1"'1
o oca lon Y + 1 . Pairs of indox registers. bcglnnlng
..
. h Y "- ...
and XR3 are .tared in succe8sive locations beg1nnmg Wlt
+ .:.... .
If Tag 1 contains an even number the right hal! of the 6torag~ lOc.ltlon
.
will be eet to zero.
lie
"
I
,
...
3.
OPERATIONAL CHARACTERISTICS OF CENTRAL PROCESSOR (Continued)
3. 6. 38
Restore CPU (RCPU)
Positions Sand 1-35 of the accumulator are replaced by
oositions Sand 1-35 of loeatinn V -
4.
POllitiona S and
Section 3. 6. 38 Restore CPU (RCPU) should be changed to thr.,
1-17
foll(;wi;;l~::,:
"Positions Sand 1-35 of the accumulator a:-c rcpL1.ccd by p()sitions S
and 1-35 of location Y. The overflow tri,gg/;r, the P d.nd Q bits, ,e':1d
the index register compare indica,tors (High, Low, a~d Eq'-t~l) ilrc set
from bits in the left half of location Y + 1. Index reQister 1 is replaced by positions 18-35 of Y + 1. The number of XH. s to be l,)..ld
is contained in Tag 1. Pairs of XR's beginning with XR2 ;l.!lci XR3
are loaded from successive locations beginning with Y +- 1. T,lg 1
may contain an even number. "
I
5.
•
Section 3.6.39 Block Index Store (SXR) should be ch
following:
:),t,:ca
to the
"XRl is stored in positions 18 - 35 of Y . Tag 1 specific s tb~ tot,l
number of XR's to be stored. Pairs of XR I s bcgin':1i:1r~ ',,,ith XH.';:
and XR3 are stored in consecutive locations beginning "/i th Y +- 1.
Ii T 1 is an even number the right half of that storage word is set
to zero. "
6.
Section 3.6.40 . Block Index Load (LXR) should be chim;..:d to the
following:
"Tag 1 specifies the number of XR's to be lO;ldcd, XRl is lo.H~cd
from positions 18-35 of location Y. Pairs 01 XR 1 S b('ginnin'~ wit:,
XR2 and XR3 arc loaded from consecutive location:; bC,c:innin,: with
Y+1.
7.
11
Section 3. 6. 41 Integer Multiply should be Changed to the
followin:~:
At the beginning of the operation the multiplier must be in the accumulator. The multiplicand is in 'location Y. Tj--.,: cnntc:'.ts of Y ;'Crc
multiplied by the contents of the accumulator. A 35 bit ~HOtLlct plus
sign iB developed and placed in the accumulator. The sign is "ct .~~c
cording to the normal rules for multiply. If the resultin7, prodclct;s
greater than 35 bits in length the 'overflow trigger is set and th.;:: hi~{h
order bits are stored in the MQ register. II
If
I
..
-20- '
3.
OPERATIONAL CHARACTERISTICS OF CENTRAL PROCESSOR (Continued)
~.
3. 6.42
Floating Reciprocal Divide
The C( Y) are divided by the C(AC).
The quotient appears
in the accumulator and the remainder in the MO.
•
The
sign of the AC is set according to normal rules of division.
The sign of the MO is set to the sign of Y.
not changed.
The C( Y) are
The rule s for divide check and trap are the
same as for Floating Divide.
3. 6.43
Convert Fixed Point to FloatingPoint (FLT)
The C( Y) is treated as a fixed point binary integer and
converted to a normalized floating point binary numt)el'.
The result is
ob~ained
in the C(AC), and the C( Y) are
unchanged.
3.6.44
Convert Floating Point to Fixed Point (FIX)
The C( Y) is treated as a floating point bin~ry number
and converted to a fixed point binary number.
The
integer portion of the converted number is obtained in the
AC. and the functional remainder is in the MO.
C(Y»
3. 6.45
If the
2 35 , a floating poiift trap will occur.
Transfer and Store Instruction Counter (TSL)
The location of the TSL instruction, plus one, is stored in
positions 18·35 of C(Y).
c'
unchanged.
location Y
Positions S, 1-19 of C(Y) are
The computer takes its next instruction from
+ 1.
"'
11
-3-
o
\
8.
Section 3. 6. 46 should be changed as follows:
"Shift MQ to Index Register
The C (MQ) position Sand 1-31$ are shifted left into the XR specifi(~d
by Tag 1. The number ot positions to be shifted is clesic;n.J.tcu by Y
modified by the XR specified bY" TZ. Bits shifted out of the XR .:l \'"c
lost. 1/
, 9.
Section 3.6.47 should be changed as folloy,rs:
/
"Shift Index Register to Accumu1.ltor
The right most n bits of the XR specified by Ta~~ 1 (pos:tions 19
minus n thru position 18) replace positions 36 minas n thru ~)()siti\)r.
35 of the accumul.ltor. The number of bits to be sh'ifted, n , i~
dcsign;ttcd by Y modified by the XR specified by T2
The rcm,~inin':
positions of AC are set to zero. The contents of the XR spcciikd
by T 1 are unchanged.
cumulator.
The number of bitato be .hilted.
de signated by Y modified by the XR
()
TZ.
f.
ft,
is
specified by T 1 and
The remaining positions of AC are aet to zero.
The
•
contents of XR 1 are unchanged.
3. 6.48
Shift MQ to Index Register One and Skip
Positions S and
i '-35
of the MQ are shifted left into
XRl after XRl has been reset to zero.
The address ot
the instruction. Y, modified by the contents of the XR
specified by TZ, is used as a count value, C.
C is eom-
pared with the contents of the XR specified by T 1.
The
smaller of the two numbers determines the number ot
positions to be shifted.
U the C(XR) specified by Tl
is greater than C, the next instruction is skipped. . .
o
"Otherwise, the next sequential instruction is taken.>
..
c
..zz3.
OPERATIONAL CHARACTERISTICS OF CENTRAL PROCESSOR (Continued)
3.6.48
(Continued)
The C{XR) Bpecified by T I is always decreased by C.
If this subtraction reduces the value in the XR below
,
zero, the result will be left in two's complement form.
3.6.49
Shift Index Register One to Accumulator and Skip
Positions P and
1-~5
of the Accumulator are shifted left
the number of places specified by the count C
(XR specified by T2)
y .. C
or by the contents of the XR
specified by T 1, whichever is smaller.
If the contents
of the XR epecified by T 1 is greater than C, the contents
of the XR are logically ORed with the contents of the
Accumulator and the result is placed in the Accumulator.
The next instruction is skipped.
If the XR specified by Tl is less than or equal to C, XRl
is shifted right C minus the contents of XRI positions.
The remaining contents of the XRI are ORed with the
Accumulator, the result is pla.ced in the a.ccumula.tor
.. and the next sequential instruction is taken.
The contents of the XR specified by Tl is alwa.ys decremented by C.
c\
If the result is less than zero it remain.
in two's complement form.
•
.
- - -_ _~ _ _=wc'"""'_~_',~_~~~__",-,,,,~~~~,--,.,.,-7t:"£'~"'·';!:.--"_"-~~'·_"c:,eC_':*>::I<7'_'":7i)_-''''''~\_~'',-~
,-
",,o;~'4>~_"""~_,,!,lIlI<'~.'$Y':~=:I:~)!1~,",,,,,'_,,,,,,,,,.."t in5truction is t:l.k'-~n
from Y. Otherwise, the next sequenti.al Llstruction is t'-1kcn.
3.6.75 Test Index and Transfer
The C(XR} specified by T 1 is decremented by onl:. if the' result is
not zero the next instruction is taken from Ioea.tion. Y. If the result
is ze ro, the next sequential instruction follow ...
3. 6. 76
Load Index Signed
.The C(XR} specified by Tl is loaded from po .. iti:J:1S 1 f)-')5 of C{ Y).
If the sign of C(Y) is positive positions IH-3S of C(Y} 'Af', 10.:10(.'<.1
directly. If the sign of C(Y) is negative the two's cCt11 1 ,l"tncnt of
pOSitions 18-35 of C( Y) arc loaded rnto the XR.
3. 6. 77 Add to Index Signed
If th~ C(Y) is positive, positions 18-35 of C(Y) arc .:ludcd to C(Xn)
specified by Tl. If the sign is negative, the tv.'o's cornpL-:rnc::t 1,[
positions 18~35 of C(Y) Clrc added to C(XR) specified by TI,
3. 6. 78 Subtract frorr. Index Signed
If the C(Y) is positive" positions 18-35 of C{Y) ,j,rc s:lb:;:nctcd fr(>n:
C(XR) specified by Tl. If the sign is neg .... tivc. the t\~()'b COln;Ji.:;nc:nt
of positions 18-35 of C(Y) are subtracted from C(XH) by:cifi.:u !)')" Tl.
3. 6. 79 Compare Index Signed
The C(XR} specified by Tl are compared with positions lS-35 of
C( Y) if the sign of Y is positive, and with the two's complement of
positions 18-35 of C( Y) if the 'sign of Y is negative. The rc::;mlt of the
compa.rison sets the Index High, Low, or Equal Inciic(ltor.
-6"
c
,I
....
3,6.80 Integer Divide or Trap
The C(AC} are divided by C(Y). At the completion of the oper;ttion
the quotient is in the accumulator and the remaindcl' is in the }"lQ,
Ii the divisor, C(Y), contains zero a trap occurl;;. rhe sign of the:
accwnulator is set according to the normal rules for di ..... ision. rhe
sign 01 the MQ is set to the original sign of the accumulator which
cont.'l.ined the dividend.
C:
C·'\
.
,
JJWcbstA:r/am
4/8/64
- - - - - - - - - - -_ _
~~=~_~~
_______.__. . .__
.
__
...._
~,A
M~'"Oj.~'W,j
"""II.:;;S;;
•
t!I!@BF.:iiii!M'.HJWli!iW\!j,'if
..
.
-25 ..
,C
3.
OPERATIONAL
3. 7
GHARAGTJ~HISTICS
OF CENTRAL PROCESSOR (Continued)
7094 Instructions Not, Included in New Instruction Format for
7095 Mode
3. 7. 1
Store Prefix - The function of this instruction is replaced
•
by "Store Accumulator Under .Control of the Mask" in
Expanded Memory Mode.
3.7.2
Store Decrement - The decrement field is not applicable
,
.
to the Expanded Memory Mode.
3. 7.3
Store Tag - In the Expanded Memory Mode there are two
tag fields either of which ca.n be stored by "Store Accumulator Under Control of Mask".
3. 7.4
Store Address - The function of this instruction is replaced
by "Store Accumulator into Right Half Word".
3.7. 5
Transfer on MQ Overflow
3.7.6
Enter Multiple Tag Mode
3.7.7
Leave Multiele Tag Mode
3.7.8
Transfer with Index Incremented .. See Table 1 for the
instructions which can replace this instruction.
\\
3.7.9
Transfer on Index High - See Table 1.-
3. 7.10
Transfer on Index ·Low or Equai - See Table 1.
3.7.11
Transfer on Inde,t - See Table L
3. 7. 12
Transfer on No Index· See Table 1.
"
'f
•
'eO.
-26-
c:
3.
OPERATIONAL CHARACTERISTICS OF CENTRAL PROCESSOR (Continued)
i
3. 7. 13
Variable Length Multiply (VLM)
3.7. 14
Divide or P.roceed (DVP)
3.7. 15
Variable Length Divide or Halt (VDH)
3.7. 16
Variable Length Divide or Proceed (VDP)
3.7. 17
Floating Divide or Proceed (FDP)
3.7.18
Double-Precision Floating-Point Divide and Proceed (DFDP)
, 3.7. 19
•
..
Convert by Replacement from the AC (CVR)
3.7.20
Convert by Replacement from the MO (CRO)
3. 7. 21
Convert by Addition from the MQ (CAQ)
3.7.22
All 7094 II 0 instructions have been dropped inithe 7095
Mode.
()
"'
The new I/O instructions are described in the,
7095 Data Channel Functional Objectives •
. 3.8
Instruction Execution Changes (Relative to 7094)
3.8. 1
All fixed point and floating point divide instructions ,cause
a trap if a divide check occurs.
Thus, the Divide
instruction becomes Divide or Trap, etc.
01"
(See Section ..
,
p.5 for CPU Trap)
3. 8. 2 '
Halt
Compare Accumulator with Storage
. In the 7095 a plus zero ia equal to a minus zero when
'
executing the Compare instruction.
at
$
$
, ;
, ,J
;
'.
-27-
CPU TRAP LOCATIONS,
Transfer Address
Type of Trap
Modes &t Return Addr
,
Floating P oint or
Other
Conditions
~ (Spill Code)
Divide Check
,;:e' 2 (Spill Code)
Protect Violation or
\,.
Illegal Operation
II 0 in Compatible
~ (Op.Code)
A:"" 8
#3
Mode
(Effective
Addr)
.;:("5 (I~atruction
Transfer Tril:P
Addre •• )
()
..;t" 1 0
Monitor Call
KZ(Efle'ctive
, .Addr)
.
.
"
.. \ .. ,
,',
"
"
.
.'
..
;.
TABLE 1
c
~.
,"
," l
"
'. ,.
.
, I
-28·'
c
7095 Instruction
3.7.8
Replacement
TXI
Instructions~
{ Add to Index Direct Immediate
Transfer
,
3.7.. 9
. 3. 7. 10
c
Skip on Index High
Direct/Immediate;
.
Skip on Index Low or Equal
Direct/ Immediate;
Skip on Index Equal
irect/Immediate
TXH1
TXL
r~kip on No Index Direc/ Immediate
'\ Transfer
,
3. 7. 11
TIX
3. 7.1Z
TNX
Note:
Also see Sections 3.6. 32 and 3.6.33 for the Oeneralized '
'{SkiP on Index Directl Immediate
Transfer
-,
Loop Close
inltr:uction8~
..
TABLE II
c
WORD l'H.ANSMISSION INSTRUCTIONS
c
"
Nadle
1.
2.
3.
'*.
5.
b,
7.
8.
9.
10.
11.
12.
13.
MnClnonic
Cl~,H
and Add
C1c;..t.r and Add LO;jical
Clear a.nd Subtract
Load Left Accumulator
Load Right Accumulator
Load MQ Rcgi.'lter
Double Load
Double Logical Load
Double Load Negative
Store Accumulator
Store Logical Word
Store Accumulator Left
Store Accumulator H.q;ht
Note ~;
CLA
CAL
2-10
- 2'1 0
CLS
LLA
LRA
l"DQ
DLD
DLLD
DLD0:
2
2
2, ,i:
30~
sro
SLW
SfAL
SfAR
302
~)
2
r; r.\l\:i
1 S.
10.
17.
18.
19.
20.
(~
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
Store Accumulator Negative
Store Prefix
Store Dccrelncnt
Store fag
Store Address
Store MQ Register
Store Left MQ
Double Store
Double Logical Store
Double Store N(;hativc
Store Zeros
Store Llstruction Counter
Exchan~c AC and MQ
Exchan 6 e Logical AC and MQ
Enter Keys
Save Central Processor
Rc!store C('ntral Procc::;:,;or
FIXED POIN
32..
33.
34.
35.
)G.
37.
3B.
'39.
r
S fA!':
srp
srD
SrI'
S L\
,=:;1'Q
-3Uu
SL(.2
- 31
rj
nSf
DLS1'
DsrN
srz
SfL
XCA
XCL
ENK
SCPU
RCPU
(; :) 1
·0:) l
:3 7 () ... ,;
2
OPERA TIONS
Add
Add Magnitude
Add and Cal"ry Logical
Subtract
Subtract Magnitude
Multiply
}'1ultiply and Round
Integer Multiply
.:.
ADD
ADM
ACL
.::Ui
1 -,' 1
SUB
SDM
:t\!,PY
MPR
IMP
q)
~u...:
- ~ \/(,1
10:-iOc!
?
~
FLXED POIN r OPERATIONS (Continued)
,
."
c
Name
l\·1ncmonic
40. Val'inblc Length Multiply
41. Round
42. Divide and Proceed
43. Divide or Halt
44. Divide or Trap
45. Inleger Divide or Trap
4l" V<"lriablc Divide and Proceed
•
47. Variable Divide or Halt
48. Variable Divide or rrap
Note"
VLM
HND
DVP
DVH
7
DVr
2,6
IDV
VDP
l
; 0·1
37U ..• 10
1 11
VDn
VDr
2, (1,7
1 1 :)
FLOA rING POIN r OPERA TIONS
49. Fl'o.1.ting Add
50. Floating Add Magnitude
51. unnormalized Floating Add
52. 'Unnol'malized Floating Add Magnitude
53. Floating Subtract
~'. 5·L Floatirlg Subtract Magnitude
(
/,55. Unnormalized Floating Subtract
56. U nnormalizcd Floating Subtract Magnitude
57. Floating Multiply
58. Unllormalized Floating Multiply
59. Floating Rot.lnd
60. Floating Divide and Proceed
61. l<~loating Divide ur Halt
02. Floating Divide or Trap
63. Floating Reciprocal Divide or Tra.p
64. Add to Exponent
.() 5. Double Floating Add
66. Double Floatill(! Add MaL!nitude
67. Double Unnormalizcd Floating Add
63. Double Unnorrnalized Floating Add Magnitude
69. Double Floatin,~ Subtra.ct
70. Double Floating Subtract Magnitude
71. Double UnnorrnalizcdFloating Subtract
72.. Double Unnorcnalizcd J:o:loatin~ Subtrad'
Magnitude
73. Double Floating Multiplr
7·1. Double Unnormalizcd Floating Multiply
75. Double Floating Dividc and Proceed
C,76. Doublcf Floating Divide or Halt
77. Double Floating Di v;ide or Trap
78.
Double Floating Reciprocal Divide or Trap
"-
l·i u
FAD
FAM
1 .;.}
UFA
-l·~U
UAM
FSl.i
FS1\1
UFS
- 1 -l.·1
1 ·12
1. .J:(,
-1·[ ..:
US~1
FMP
1 Ju
U F'l\l
.F1U\'
- 1 3\.)
:>'7\1 .• 11
FDP
FDIl
FDr
l~O
121
F'RD
ADXP
2
DFAD
1 ·t 1
j.lS
- l·t 1
DF'A~l
DUFA
DUAr.i
DFSB
- 1·1 ::i
DFSM
1· ~ 'j
143
DUFS
DUSM
DFMP
DUFM
DFDP
DFDH
DFDT
DFRD
-, I
1 J.
- 1.
31
-1
~.l
1
1
2,6
2
SI II F fING OPERA TIONS
...
C
.
Name
:--;otl':-'
Mnemonic
70 J S C(ldl.'
,
79. Accumulatol' Left Shift
ALS
)~.,.
80. Accumulator Right Shift
81. Long Left Shift
82. Long Right ShUt
83. Logi~al Lett Shift
84. Logical Right Shift
85. Rotate MQ Left
ARS
~377
LLS
LRS
LGL
LGR
RQL
373
375
-373
...
.-,
;
.-
-.:JI:;)
-
3-'"
I~
CONTROL OPERATIONS
86. No Operation
87. Halt and Proceed
8S. Halt and Transfer
89. Execute
90. Transfe r
91. Trap fransfer
92. Tl'ansfer on Zero
93. Transfer on No Zero
94. Tran:;Ier on Plus
95. Tran!-lfe r on, Minus
96. fransfer on Zero or 1.1inus
97. rransfer on Zero or Plus
98. Transfer Greater than Zero
99. Transfer Less than Zero
lOa. Transfer on Overflow
lO1. Transfer on No Overflow
102. . fransfer on MQ Plus
103. fransfer on Low MQ
104. Plus Sense
1 05. Minus Sense
l06. P Bit fest
107. Low Order Bit fest
108. Divide Check rest
109. Storage Zero fe8t
110. Storage Not Zero Te at
111. Compare Accumulator with Storage
112. Logical Compare Accumulator with Storage
113. fransfer and Store Location
114. Set Memory Protect
11·5. Enter Trapping Mode
(:;
NOP
HPR
BrR
XEC
TRA
rTR
TZE
010
01 1
0-10
TN~
- o·~ 0
371
210
(Joa
",
2
2
2
TLZ
I-
-0,0
.
SMP
EfM
')
o so
TPL
TMI
rZM
fZP
'feZ
TOV
TNO
rQP
fLQ
PSE
MSE
PBr
LBT
DCr
ZEr
NZT
CAS
LAS
rSL
~
'- :J6:.,.
")
060
-OI~O
07 ~
020
370
-370
.
.;
- 3 70 ... 1
370 .•. 1
370 .. 12
2. 50
-250
1(,0
-160
2
370. , . 7
C'
MiIiMi
oj
.7. .,.¥'"'¥.
,;
CONTROL
OPERATIONS (Continued)
.
Mnemoaic
C
.'
llG.
#117.
118.
1 1 <).
1 ZOo
12l.
122.
123.
12.4.
12.5 •.
126.
Leave frapping Mode
Elltcr Multiple fag Mode
Leave Multiple fag Mode
Load Inte rval ,finle r'
Store Interval fimer
Load Real ·rime Clock
Store Real Time Clock
Channel frap Return'
Processor Trap Return
Set Channel Assignment Return
Call Monitor
L fI>.l
EMTM
LMI'M
LfMR
STMR
LRfC
SRfC
CTR
PfR
SCAR
CMON
Note:;
il)):) C\}~l\
- 3 70 .. , 7
-3iG,,16
370 .. In
...
)
2
2
2
2
2
2.
...
')
INDEX REGISTER OPERATIONS
1 2. 7.
128.
129.
130.
131.
132.
',133.
(
134.
.j
135.
136.
137.
13<5 I
13'-) .
140.
141.
143.
144.
1-15.
I ":l; 6.
147.
148.
149.
150.
151.
152.
153.
e
154.
155.
Addrens to Index f rue
Address to Index Complemented
Place Address in Index
Place Complement of Address in Index
Place Index in Address
Place Index in Dec rernent
Place Conlplen1ent of Dec rerl1ent in Iudex
Place Cornp1crncnt of Lldex in Decrement
Place Complement of Index in Address
Store Index in Addrc::> s
Store Lldex in Dccrcrnent
Store Complement of Index in Address
Store COlnplelllcnt of Index in Decrenlcnt
Load Index frum Address
Load Illdcx from Decrement
Load C0111plernent of Address in Index
Load COInpiement of Decrement in "Index
Add to Index Si gncd
Add to Index Direct
Add to Index Immediate
Subtract from Index Signed
Subtract from Index Direct
Subtract from Index Immediate
Place Characteristic in Index
Transfer and Set Index
Transfer on Index Incremented
Transfer on Index High
Tra.nsfer on Index Low or Equal
Transfer on Index
AX r
AXe
PAX, PI(X
PAC, Pi~C;
PXA. PX1(
PXD, PXL
PDC,PLC
peD.peL
pcn.
PCA,
SXA, SXH.
SXD, SXL
SCA, SCH.
seD, SCL
LXA.LXH
LXD. LXL
LAC. LiZC
LDC. LLC
ADXS
ADXD
ADXI
SBXS
S13XD
SDXI
PClIX
fSX
fXI
TXII
TXL
TIX
J
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
37';
- 37-1
3 j.~
J ') 7
3tA
- ') vi
- 3 S7
- 3,)()
3 (', tl
311
-:;1-1
-31u
~ :>,1
~)
-
i
- '- J"t
2.::>i
- 2.:iS
2.
2.
...
)
2
2.
O~
1
1
1
INDEX REGISTER OPERA nONS (Continued)
..
C56.
. 157.
158,
1 5().
160.
161.
11)2.
1 u3.
16-1:.
1 tH).
167.
168.
loC).
1 70.
171.
172.
1vlnemonic
Transfer on No Index
fc 8t Index and Transfer
Transfer Index High
fran.:,fer Index Not High
fransfcr Index Low
fl"ansfer Index Not Low
fra nsier Index Equal
fransft.!l" Index Not Equal
Load Index Signed
t;Cdl e lileex 6i~]iCd
Cornpare Index Signed
C0mpare Index Direct
Compare Index Irnmediate
Close Loop Forwar,d
Close Loop Backward
Store lv1ultiple Index
Load Multiple Index,
TNX
•
Notes
7'() ',I S
C"d\.~
1
..
TXf
TXRII
TXNH
rxn.L
TXNL
rXRE
rXNE
LXS
Z
2
2.
2
2
5)(5
l
?
Z
Z
..
-)
CXS
CXD
CXI
XLF
XLB
'-
S~lX
2
LlvlX
2
2
')
'-
2.
')
LOGICAL OPERATIONS
'73.
C{7·1.
175.
1 70.
1 77.
1 7~.
1 7').
usa.
l8i.
182.
133.
184.
I
OH. to Accumulator
OR to Sto1'a :~C
AND to Accumulator
AND to Storage
Exclusive OR to Accumulator
Exclusive OR to Storage
Complement Magnitude
Clca r Magnitude
Cllangc Sign
Set Sign Plus
Set Siqn Minus
Add One to Storage
ORA
ORS
ANA
ANS
ERA
ERS
COM
<;LM
ellS
SSP
SSM
ADOS
- ~,11
-30.?
-1 SO
.
1 SO
1 :)~
-)
370 ...
3 7~) .•••'..
3 7t) ... 3
-370 ... '.)
2
SENSE INDICATOR OPERATIONS
. 185.
186.
187.
O~:
190.
Load Indicators
Store Indicators
Pl<.l.cc Accumulator in Indicators
Place Lldicators in Accumulator'
OR Accumulator to Indicators
OR ~torage to Indicators
LDI
SrI
PAl
PIA
OAI
051
t.
'370 ... \l
.221
30'L
o ).l
-020
o ))
~J
')
)
,.~
~
....
..
SE;..JSE
INDICATOR OPERA TIONS (Continued)
,
..
. ••
C
191.
1 ()2.
1 Q3.
194.
l ';15.
1 \)u.
197.
198.
199.
200.
2.01.
202.
203.
204.
205.
206.
207.
208.
209.
210.
211.
~ame
r..1netnonic
;.Jot.' ,>
....
OR Indica.tors to Storage
n.~S(,t Indicators Left
H.,-set Illdicators Hight
Set Indkators Lcit
Set Il\d~catol' s Right
It~:sct Indicators irom Accumulator
Reset Indicator s from Storage
Invert Indicators from Accumulator
Invel't Indica.tors irom Storage
Invl'rt Lldicator s Left
Invert Indicator s Right
Off fest for Indicators
On, Tc!;t for Indicators
Right Off Test for Indicators
Right On. Test for Indicators
Left Off fest for Indicators
Left On Test for Indicators
Load Accumulator Under Control of Indicator s
Store Accumulator Under Control of Indicator:-;
Insert Accumulator Under Control of Indicators
Cornpa re AccUlnulator Under Control of Indicatprs
...
')
OIS
hiL
lUR
,sIL
SIR
-037
OJ7
-03 ::i
03~
') ')
- l) _._
HL\
.
.. . ~
IUS
IV\
liS
IlL
lIR
0
")
,-
.)
!.!.o
-031
i
,
,
........ ·t
() J
)
010'1'
ONf
r
2 .~l.l
03'
03d
LFl'
-1l31
RFf
I\, 0:
LKL'
.,
LACI
SACI
...
L\SI
...
,-)
')
'~
CAS!
SPECIAL PURPOSE OPERATIONS
Convert Fixed to Floating Point
Convert Floating to Fixed Point
Convert BCD to Binary
Convert Binary to BCD
Convert by Addition from MQ
Convert by Repla.cement from MQ
Convert by Replacement from Accumulator
Shift MQ to LldC'x Left
Shift Index to Accumulator Right
Shift MQ to Index and rest
Shift Index to Accumulator and Test
Channel T\.!st or Start
Channel rest
Store Channel
Halt Channel
Llhibit Channel Traps
Set Bulk Storage Protect
~
U;':l
(:
212.
213.
214.
215.
216.
217.
218.
219.
220.
221.
222.
223-.
22-1.
225.
226.
227.
228.
Cud\,:
7l) - I";
-----~.
I'~L
f
"
-"
FL'\
cnsc
),
ClJl:'eJ
}
CAQ
~:lZQ
CVl{
SQXL
.~
SXAI~
t
SQXT
,~
SXAT
...
CTS
CIlr
SCllX
...
HerrX
1
l
.~
')
..
)
,
2..
ICT
2-
SBP
t.
-,
- 0 3 i,
,
,"
C
~\pplicaulc
anI:,' ill 709·1 mode.
7()(H codl.:s :lpply.
Applicablc oilly in 7095 moue.
2.
R(!defincd in "70,5 mude. Refercnce to "dl'...:rcrllcnt" bCCOlI1C.s .kft b,dt wonl.
bccomes l'ight half word .
3.
"addrcs~"
.-1.
Dependant upon definition of "Pit bit.
5.
None
6.
Divide ;lnd procecd codes ilrc us('d in 70'.15
7..
Count specified by r 1 field.
(
'
p'
c
,.T1ludc
for Dividt' ,.:ld [rap uiH:r,(ti.ul:.
DRAFT
113M CONFIDENTIAL
REVISION 113 April 10, 1964
7095 DATA CHANNEL
FUNCTIONAL OBJECTIVES
'I (,
I
II
!
1
!!
DESCRIPTION
1. 1
l
1
The 7095 Data Channel provides the input-output paths and control
flexibility es sential to the 7095 Data Proces sing System.
I
Effective
1
I
channel operation is attained by a streamlined instruction-command
,i
!
j
set and a comprehensive trap system.
I! \
1. 2
I
I
I
I,
GENERAL CHARACTERISTICS
2. 1
il
"IiI
the NPL Interface.
2
'Ii
C:
The Data Channel attaches NPL input-output devices to the system via
The 7095 Data Channel is a stored program channel providing seven
basic commands:
I)
Read
2)
Write
3}
Sense
4)
Control (including Control Immediate)
5)
Read Backward'
6)
Transfer in Channel
7)
Execute
Operations that require data transmis sion will fetch a Data Control Word
(DCW) which contains Word Count and Starting Address of the data,
along with flags for indirect addressing; non-transmission; and chaining
to anothe r DCW.
'C
'1----
-~
~
1
j
-2 -
1
I
I
!
2.2
i
t
I
1
(
When a trap condition occurs which has been previously enabled, the
">,
,"
channel will generate a trap.
1£ the condition occur s but is not enabled,
it will never generate a trap.
When a channel trap occurs, all subsequent channel traps are automatically inhibited until restored by the main program.
Traps may
also be inhibited selectively by channel under main program control.
Whenever a
ch.~nnel
is inhibited it will save all trap conditions that
are enabled until the inhibit is removed, at which time a trap will be
generated.
A channel trap will store address and status information in three
I
,j
c-
'11 -
fixed core locations.
;
The channel will then cause the CPU to execute
one of three fixed locations; one each per channel for end, unusual
end, and attention.
3
OPERATIONAL CHARACTERISTICS
3. 1
Channel Commands
All channel commands have the following format
-._---:.-:·T~l_"~~-:--F_la,g-~~ : --[----.-~----.--.~.-~-J
-;::-_ _ _O
__
p_N_ _
11
S
12
17 18
-
- 35
Pos. S -11 - ,?peration The format required by the NFL Control Units will be used.
Po-
sitions S, 1,2 equal to 7 octal cause the channel to decode 3-11
j
1
4 C'
as operation code, and if position 3 is zero then 4-11 are sent to
the control unit.
-3-
(~'
Channel Commands (continued)
3. 1
S
1
2
3
4
6
5
----~-.-----.~-,----~~
7
8
. . . -,..----..---.---.............-, . . . . .
9
".--~ --
...
10
--·"'~--·-···~---
11
. ·-'---.. . ··1--·-·-.. . . . . . . .
~
.-r~~-,.,- . . ~- ..'- ...~.-..-
... - _ ..... -
1
1
1
0
M
M
M
M
0
1
0
0
Sense
1
1
1
0
M
M
M
M
1
1
0
0
Read Backward
1
1
1
0
M
M
M
M
M
M
0
1
Write
1
1
1
0
M
M
M
M
M
M
1
0
Read
1
1
1
0
M
M ',M
M
M
M
1
1
Control
1
1
1
1
0
'0
0
0
0
0
0
0
Transfer in Channel
1
1
1
1
0
0
0
0
0
0
0
1
Execute
,i
, 1
( ~
1
-i
,
M - Modifier Bit - Interpreted by the COlltrol Unit.
;
,~
,
~
lJ
I
Pos 12 -17 - Command Flags
;i
-
;1
:1
;:
ji
I
li
j;
('
Pos 12 - Spare
Pos 13
I'
I'
- 6 Bit Mode
'j
I,
The channel normally operates in 8-bit mode.
This
I
position flags 6-bit operation.
Pos 14 - BCD Mode
The channel normally operates in Binary mode.
This
position flags BCD operation.
Pos 15 - Advance/Disconnect
~CAdvance
- The channel advances to the next sequential
command upon completion of the current operation.
Disconnect - The channel is disconnected upon completion
c
of the current operation.
*While ,advancirig the channel ignores Data Control words, and continues to advance
until a command is interpreted.
-4-
3. 1
Channel Commands (continued)
Pos 16 - Indirect Addressing Those operations which refer to Y. may be indirectly
addressed.
Pos 17 - Immediate 1) Indicates a Control operation which does not require
a Data Control Word.
2} Indicates
an immediate
address.
..
.
Pos 18 -35 - Addre 5S
-
The addre s s will contain:
1) The Transfer Address of a TCH.
2) The operand of an Execute.'
~'\
(
j
Command Operations
r____ ~~-~:ags_.---'!
__~.___.--~.~:~_.-~~~.-. -~
S
11 1 2 1 7 18
35
Control Unit Operations
Operation
Opn Code
Applicable Fla(Ys
b
Write
7001
A/D, 6/8, BCD
Read
7002
A/D, 6/8, BCD
;"Control
7003
A/Dp IMM, 1/ A
Sense
7004
A/D
Read Backward
7014
A/D, 6/8, BCD
All Control Unit Operations, require a Data Control Word except
Control Immediate.
;:cControl Immediate':' The control information is contained in Pos 4-9
of the control command.
-5 -
3. 1
Channel Commands (continued)
Sequence Operations
.. Applicable Flags
Operation
Opn Code
TCH, Y
7400
A/D, I/A
XEC, Y
7401
A/D, 1/ A
Description
TRANSF ER CHAN - TCH, Y
The channel transfer s to location Y, for its next command or data
control word.
EXECUTE - XEC. Y
The channel executes the command or control word at location Y.
When that command has been completed, the channel returns to the
location of the XEC command plus One for its next command.
3.2
Data Control Word
The following format will be used for the Data Control Word:
C
1./
f~
:;
-"~
YA INO
~1
S
1
--
. .. ---
Data Address
Word Count
2 3
17 18
-------
!
_J
35
Pos S - DCW Chaining Data transmis sion may be controlled as follows:
1.
With the chain bit on:
a. When the word counter is equal to 0 the channel proceeds
j
,
"
to the next sequential DCW. and Data transmission continues
under the current command.
-6-
,,
.
c
3.2
Data Control Word (continued)
b. When an End Signal is received from the control unit, data
transmission is terminated.
At this time the Option to dis-
connect the channel, or advance to a new command is determined by the status of the Advance/ Disconnect bit in the
current command.
2.
With the chain bit off:
Data transmission is terminated when either the Word Counter
is equal to zero or an End signal is received from the control
unit, whichever occurs first.
The Advance or Disconnect option
is again determined by the status of the Advance! Disconnect bit
in the current command .
. Pas 1 - Indirect Addressing Permits indirect addressing of the Data Address.
If sign bit is on
in indirect word, the channel will interpret pas 13 -35 as the data
address.
Pas 2 - No Transmission The transmission of Data to memory may be inhibited for (N) words
under control of the word counter.
Pas 3-17 - Word Count
Pas 18-35 - Data Address
Data Control Word Operations
c
lop~wo~~ Count - C
S 123
:I
17 18
y
35
-73.2
Data Control Word (continued)
Positions S, land 2 are coded to provide the following Data Control
Word operations:
Octal
Opn Code
Operation
TCW
(Terminate Control Word)
o
TCW*
(Terminate Control Word IA)
2
CCW
(Chain Control Word)
4
CCWN
(Chain Control Word Non-Transmit)
5
(Chain Control Word IA)
6
Description
Terminate Control Word - TCW, Y, C
The chan. terminates transmission under the current command
()
when the word counter is equal to zero or an end is received from
the control unit whichever Occurs first.
Terminate Control Word
II A - TCW*, Y, C
Positions 18-35 of location Y, replace the contents of the address
counter.
Transmis sion then proceeds under TCW control.
Chain Control Word - CCW, Y, C
The chan. terminates transmission under the current command when
an End signal is received from the control unit.
If the word counter
is equal to zero, and an End signal has not been received from the
control unit, the chan. proceeds to the next sequential location.
new DCW may be brought into continue Data Transmission under
the current command.
A
-8-
3.2.
Dat.l Control Word (continued)
Chain Control Word Non-Transmit - CCWN, Y, C
Data transmission is suppressed for C-words.
The chan then pro-
ceeds under CCW control.
Chain Control Word
II A - CCW';' , Y, C
Positions 18-35 of location Y, replace the contents of .the address
counter.
3. 3
Transmission then proceeds under CCW control.
Channel Trap
Each channel may be enabled to trap one of three locations.
The Trap
location is determined by the type of trap that occurs; End, Unusual
End or Attention.
The conditions which may cause each type of trap are listed as
follows:
1. End Trap - The Trap will occur if the chan. is free of any error, or
unusual conditions at the completion of a command which
does not have the advance bit on.
2.. Unusual End Trap - Will cause a trap when one of the following
unusual conditions appear at the completion of a command:
a. Data Error
b. Exceptional Condition (End of File, etc.)
c. Intervention Required
d. Incorrect Length
Enable Trap bits required -
Unusual End
(a, b, c)
Incorrect Length
(d)
r
i
-9 -
c
3.3
Channel Trap (continued)
If the channel advance bit is on in the current command, the channel
will be disconnected only if an unusual end occurs.
3. Attention Trap -" 1)
W ill cause a trap when an attention or unit
freed signal is received from the Control
Unit.
a)
Enabled Attention Immediate - The trap will
occur as soon as attention is received from
the Control Unit.
b)
Enabled Attention Not in Use - The trap will
occur
a~"
soon as the channel is not ill use
after an attention has been received.
c
2}
Will cause a trap when chaining between Data
Control Words.
Enable Trap Bit required - Chain Trap.
Each channel trap will perform a three word store.
follows:
Word 1
Word Z
Word 3
I
Ir--~
Channel
!
"
Status
10·
17
The format is as
-10-
3.4
L
11
C'
I/O Instructions
3.4. 1
"
II:1
STC
Start Channel (Skip Type)
All I/O Instructions, except Restore Channel Traps require a·
Channel Select Word (CSW).
The format for the CSW is as
follows:
Pos.
I/O Instruction
Function
S
STC, CRT, SCR
Ignore Memory Protect
1
ALL
Special Chan. Sei.
2
ALL
Sel Chan A
3
ALL
Sel Chan B
4
ALL
Sel Chan C
5
ALL
Sel Chan D
6
ALL
Sel Chan E
7
ALL
Scl Chan F
8
ALL
Sel Chan G
9
ALL
Sel Chan R
10-17
STC, CRT
Unit Address, 0-256
18-35
STC, .CRT, SCR
Memory Address
30-35
ENB
Trap Mask
•
!--T .~---. T 2 '--"-'--~--~'~---'---l
/s~~ ~._L_l____
IF
S,
y
8 9
10
II ~:~n.
S 1
i l
1
13 14
17 18
35
.______-,~-----~hann~ISel~ctWor~
UA
.
9 10
!
I
_----_.-_
I
17 18
x
.... ..........
-.
_-_ ,-_.__
35
....
.
-11-
3.4
I/O Instructions (continued)
The STC instruction specifie s the location (Y) of a Channel
Select Word (CSW).
The CSW contains the address of tho
channel and unit to be selected and the location (X) of the
first channel command.
If the selected channel is not busy it clear s previous status,
accepts the unit address and loads its first command from X.
The CPU then skips the ne:h1; sequential instructions.
If the selected channel is busy, no action is' taken and the
CPU proceeds to its next sequential instruction.
Only
0:1"
channel may be specified in the CSW.
3.4.2
Channel Test Instruction (Skip Type)
CHT
I C~T ~-:-T';~:-'--"'~J---------~Y==---1
s,
Y
1
8 9 10
35
Channel
Select
\Vord
. . . --------·--f-· ........-._....-.-......... .... ..... .... .. .... ..' - ,
Chan.
Sel.
I.
13 14
UA
.
17 18
i
I
!
X
'
_ _ _ _ _• _ _ _ _ ----1.. _____ ••..•_ •.__ .". __._.. ______•.•.. -.:..__ . ___. _ "" ____ . _ _ _-'
S
1
9 10
17 18
35
The CHT instruction specific s the locatitot:t, (Y) of a Channel
Select Word (CSW).
The CSW containlltthe-<:j.ddre:s:-;o£ th('
\
channel and unit to be tested and the locd.tion'{X) in which
status will be stored.
If the cha.nnel and device is available,
the CPU skips the next sequential instruc-ti0.n.
~C
..
,1
,
)
If the channel
and/ or device are not available, the CPU pr~ceeds to the ne)..1;
-12-
110 Instructions (continued)
,
sequential instruction.
In either case channel stores status
\
•
at location X,'
3.4.3
SCH
!
I
I
I
sC~!;-f-T~"'-~T~~-I'--
_--'-'
_
!
Only one chan. may be specified in the CSW.
Store Channel
S
~
I
__
. __ .....__ . _ _ _ _ J __••• _ _ •.J... _ _ _ _.
8 9
rr~~~~----l
y
.----,
10
13 14
17 18
Y
___
._ _ _ _ __
.
Channe~clect
Wi
35
'--__ .___ . ____..... ___ ._._____L___________.________________'
S 1
9 10
. 17 18
35
~
17 18
S
r--··~--·--·-·-·-~-·····-··-
ii
35
I
Data Address Counter
!
()
..---..--------.-------- --.-----
The SCH instruction specifies the location (Y) of a Channel
Select Word (CSW).
The CSW specifies the channel whose counters are to be
stored.
The address {X} specifies the locations (X and X + 1)
into which the Location Counter. Word Counter and Data
Address Counter are stored.
Only one channel may be specified in the CSW.
3.4.4
HCH
Halt Channel
I --'r- ---j-----I----------··----..--...-----------.... -----'1
HCH
Y
s
A
1 F \ Tl
1 T2
-.~-,.---.... ~.--.---
--cha: 9
11°
\
y
.... -.- ....... -~.-...... -.......... -.-.".- ..... ~~ ......--.---..
13 14
17
--.-- ..
I
.... -,.-----'
l~-.-Channe.LSelect....w..ox.d_~
il ..._ _.. ,.._ _.........._.__._••_ ••_ _ ••_._._ ........•••...••."
Sel _ _ _ _ .__• .1-.
S 1
9 10
!
~.".--.-
\
..•--_ .••... - -.. - - - -...- - ,
35
-13-
c
3.4
II 0 Instructions (continued)
The BCH instruction specifies the location (Y) of a Channel
Select Word (CSW).
halted.
The CSW specifics the channds to be
This instruction ca.uses the specified channel to come
to an orderly halt at the end of its current command.
Up to eight charmels may be specified in the CSW.
3.4.5
leT
Inhibit Channel Traps
r-·····_····..·..·..... -....
"
.... -........ ".-........"..... ·.-1-•.-·....................
ICT
F
1
5-----·-8·
..:-9·-.
. · ·....T ·-·····
. . 'T
· . · ;· ....2····
[._
y
I
....
__ ...........
__ -
..... ........,. ...... -.......
.. ..1. ....... __ ...
18
..
" ' " ...-- ....... .
Y
.................. ' .....................
35
.-............ ..
Chan·
I
L.~.. _. ~.G.1., __ .... _. ...t...... . ......_ .
S 1
9 10
The lCT instructions specifies the location (Y) of a Channel
!
Select Word (CSW).
from trapping.
The CSW selectively inhibits channels
If a channel trap has been enabled, and this
channel is inhibited, the trap will wait in the channel until
the inhibit is removed.
Up to eight channels may be specified in the CSW.
3.4.6
ENB
Enable Channel Traps
,---"---------'1-'--1 --· ..·....
FIT
y
-1- .. - · · · - - · .. ·.. · · , - - · - · - - · - · · · · ·
......
··-----·1
!
I ENB
!
1
T2
j
y
I
-------'-~.---- . -.-.. -'-- ....... --.... -... .- ..... ' .- --..
.-.. - ....... ___I
S, 1
8 9 10 13 14 . 17 18 Channel Select Word 35
r-r-"---.- ......-- ---- ._.__.. ....... .. ...
-- .. --......._--t
I I
Chan
!
, I
II
M
I
. ! . .- S _
e 1. . ,. - .....- ;.. . ----..
I
-----..
. . .-_. __.________ l..,_
. - "...____ ----..J
l
-------··-·-·~r
~
-.v---.~
S 1
c
9 10
30
35
j
1
I·
I.
!
i
-14 -
C-
3.4
II 0 Instructions (continued)
The END instruction specifie s the location (Y) of a Channel
,
Select Word (CSW).
The CSW specifies the channels to be
enabled, and the enable mask (M).
interpreted by the specified
The enable mask ,\\,111 be
cha~nels
as follows:
Pos 30 - Chain Trap
Pos 31 - Attention Immediate
Pos 32 - Attention Not in Use
Pos 33 - End
Pos 34 - Unusual End
Pos 35 - Incorrect Length.
Channels not specified are not affected.
()
3.4.7
RCT
r - - " " ..........
;
Restore Channel Traps
--~·
......
-~-
"..... ......
~
-.-.--.~
..,-....
-.--.-~
.. -..."' ...
--~
I
RCT
.... -"'.-.- ......-..........
~""
...... -...---.- .... - .
.
__.. _. __L............,.,........ . .. _......."_...... __ ._._ .................._...... _" ,... "... ..
S
8
After a channel trap has occurred, al1 further channel traps
are automatically inhibi'ted.
The RCT instruction allows
channel traps subject to the mask set by the most recent ICT.
c
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