71 218_3C_TCM 32_Core_Memory_Maint_May64 218 3C TCM 32 Core Memory Maint May64
71-218_3C_TCM-32_Core_Memory_Maint_May64 71-218_3C_TCM-32_Core_Memory_Maint_May64
User Manual: 71-218_3C_TCM-32_Core_Memory_Maint_May64
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TCM-32
Magnetic Core Me:rnory
Operating and Maintenance Manual
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COMPUTER CONTROL COMPANY,INC.
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Document No. 71-218
INSTRUCTION MANUAL
MAGNETIC CORE MEMORY SYSTEMS
SERIES TCM-32
II
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May 1964
Computer Control Company, Inc.
Old Connecticut Path
Framingham, Massachusetts
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COPYRIGHT 1964 by Computer Control Company, Incorporated,
Framingham, Massachusetts. Contents of this publication may not
be reproduced in any form, in whole or in part, without permission
of the copyright owner. All rights reserved.
.
1
Printed in U. S. A.
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MAGNETIC CORE MEMORY SYSTEM
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TABLE OF CONTENTS
Title
Paragraph
Page
SECTION I
INTRODUCTION
1-1
Purpose and Scope of this Manual
1-1
1-2
System Designation
1-1
1-3
General Description
1-1
1-4
Basic Elements and Organization
1-2
1-4. 1
Memory System Layout
1-3
1-5
Input Signals
1- 6
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SECTION II
SYSTEM INSTALLATION
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L-1
2-1
General
2-1
2-2
Electrical Interconnections
2-1
SECTION III
PRINCIPLES OF OPERATION
3-1
Principles of Magnetic Core Memories
3-1
3-1. 1
Magnetic Core Storage
3-1
3-1. 2
Addressing
3-4
3-1. 3
Information Sens ing
3-6
3-1. 4
Writing
3-7
3-1. 5
Information Retention
3-8
3-2
General Specifications, TCM-32 Memory System
3-8
3-3
TCM-32 Functional Description
3-10
3-3. 1
Addres s Register
3-10
3-3.2·
x-
3-10
3-3. 3
Memory Timing and Control
3-12
3-3.4
Memory Core Stack
3-12
3-3. 5
Information Register
3-12
3-3.6
Sense Amplifiers
3-12
r,
3-3.7
Inhibit Driver s
3-13
U
3-3.8
Current Drivers
3-13
3-4
Functional Description of Selection and Driving
Techniques
3-13
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and Y -Decoders, Switches, and Drivers
u
iii
MAGNETIC CORE MEMORY SYSTEM
,
1
"
1
TABLE OF CONTENTS (Cont)
Paragraph
Title
Page
3-4. 1
Memory Core Stack
3-13
3-4.2
Selection Switches
3-4.3
Indicator Option
3-15
3-18
3-5
3-5.1
Operating Cycles
3-18
Standard Cycles
3-18
3-5.2
Optional Cycles
3-25
3-6
3-6. 1
Optional Modes and Features
3-26
Sequential Addressing
3-26
3-6.2
Random-Sequential Addressing
3-26
3-6.3
Sequential-Interlace Addressing
3-26
3-6.4
Serial Addressing
3-28
3-6.5
Serial-Information Inputs
3-28
3-6.6
Memory Clear
3-28
3-6.7
Partial Substitution
3-28
3-6.8
Signal Compatibility
3-29
3-6.9
Indicators
3-29
,
"
.'_..,
--J
SECTION IV
LOGIC
4-1
Logic Diagrams
4-1
4-2
Input/ Output Logic Signals
4-1
.-"
SECTION V
MAINTENANCE
·5-1
5-2
5-3
Test Equipment
5-1
5-1
PAC Locations
5-1
5-4
PAC Handling and Repair Procedures
5-2
5-4. 1
5-4.2
Inserting and Removing System PACs
5-4.3
Component Checking
5-2
5-2
5-2
5-4.4
Component Replacement
5-3
5-5
Spare Parts
5-4
5-6
Maintenance Inspection
5-4
5-7
Preventive Maintenance Procedure
5-5
General
PAC Troubleshooting
iv
~-'1
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MAGNETIC CORE MEMOR Y SYSTEM
n
TABLE OF CONTENTS (Cont)
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Title
Paragraph
5-8
Corrective Maintenance Procedure
5-7
5-9
Magnetic Core Matrix Maintenance
5-11
Logic Circuit Maintenance
5-14
DC Power Distribution
5-14
5-10
5-11
\
SECTION VI
PAC COMPLEMENT LIST
6-1
6-1
General
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MAGNETIC CORE MEMOR Y SYSTEM
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LIST OF ILLUSTRATIONS
Title
Figure
Page
1-1
TCM-32 Magnetic Core Memory System
1-0
1-2
Memory System, Block Diagram
1-4
1-3
Memory System Layout
1-5
2-1
Installation Drawing (Sheet 1 of 2)
2-3
2-1
Installation Drawing (Sheet 2 of 2)
2-5
2-2
Connector Detail
2-7
2-3
Pin Numbering, Connectors J -102 through J -107
2-8
2-4
TCM-32 Power Wiring Diagram
2-9
3-1
Ferrite Core Hysteresis Loop
3-2
3-2
Core Control Windings
3-4
3-3
Coincident-Current Selection
3-6
3-4
TCM-32 Memory System, Block Diagram
3-11
3-5
Memory Core Stack, Simplified Schematic Diagram
of Y - Coordinate Sense, and Inhibit
3-14
3-6
Simplified Selection Diagram
3-16
3-7
Internal Timing
3-17
3-8
R ead/ R egener ate Cycle External Timing
3-19
3-9
Clear /Write Cycle External Timing
3-20
3-10
Load Cycle External Timing
3-22
3-11
Unload Cycle External Timing
3-23
3-12
S-PAC Location and Functions
3-27
4-1
Memory Timing and Control, Logic Diagram
4-5
4-2
Address Register, Logic Diagram (Random Addressing,
Sequential Addressing and Random-Sequential
Addres sing)
4-7
Address Register, Logic Diagram (Sequential-Interlace
Addressing Option)
4-9
4-4
X- Y Decoders and Selection Switches, Logic Diagram
4-11
4-5
Information Register, Sense Amplifiers, and Inhibit
Drivers, Logic Diagram (Bits 1 through 16)
4-13
Information Register, Sense Amplifiers, and Inhibit
Drivers, Logic Diagram (Bits 17 through 32)
4-15
Information Register, Sense Amplifiers, and Inhibit
Drivers, Logic Diagram (Bits 33 through 48)
4-17
4-3
4-6
4-7
vi
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MAGNETIC COREMEMOR Y SYSTEM
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LIST OF ILLUSTRATIONS (Cant)
Figure
Title
Page
Partial Substitution Option, Logic Diagram (Two- Zone,
Three- Zone, or Four- Zone Information-Register
Partitioning)
.
4-19
4-9
Clear Option, Logic Diagr am
4-20
5-1
Strobe Adjustment Waveform
5-6
5-2
Waveform (Sheet 1 of 3)
5-8
5-2
Waveform (Sheet 2 of 3)
5-9
5-2
Waveform (Sheet 3 of 3)
5-10
4-8
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vii
MAGNETIC CORE MEMORY SYSTEM
,
1
LIST OF TABLES
Table
Title
Page
2-1
Wiring Connector J -102
2-11
2-2
Wiring Connector J -103
2-12
2-3
Wiring Connector J -104
2-13
2-4
Wiring Connector J-105
2-15
2-5
Wiring Connector, J-106 and J-107
2-16
3-1
Internal Logic Signals
3-24
4-1
Logic Signal List
4-2
5-1
Test Equipment Required
5-1
5-2
Spare Parts List
5-4
5-3
Operation Failures
5-12
5-4
Partial Information Word Failures
5-15
5-5
Address,
5-17
5-6
Inhibit Winding Checklist
5-18
5-7
Sens e Winding Checklist
5-19
5-8
Intra- Unit Wiring Connector
5-21
5-9
X- Winding Checklist
5-25
5-10
Y - Winding Checklist
5-26
6-1
PAC Complement List
6-2
Decoding,
and Selection Failures
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viii
MAGNETIC CORE MEMORY SYSTEM
>-1.'
Figure 1-l.
1-0
TCM-32 Magnetic Core Memory System
MAGNETIC CORE MEMORY SYSTEM
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SECTION I
INTRODUCTION
1-1
PURPOSE AND SCOPE OF THIS MANUAL
This manual contains information on the theory of operation and
instructions for the installation, operation, and maintenance of Series
o
TCM- 32, Magnetic Core Memory Systems (Figure 1-1).
It is intended that
this manual will contain all information required to properly operate and
maintain the magnetic core memory system.
1-2
SYSTEM DESIGNATION
The TCM- 32 is a high- speed magnetic core memory system that
stores data in binary form at specific locations or addresses within the sys-
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tem.
The storage capacity and speed of any TCM- 32 memory system is in-
n
tion of the designation indicates that the system has a half-cycle (load or un-
dicated in the designation.
For example, a storage system designated
TCM-32 512/30-3.0/5.0 is identifiable as a TCM-32 system having 512
words of storage, each word of which contains 30 bits.
The "3. 0/5.0" por-
load) operating time of 3 jJ.sec and a full-cycle (clear/write or read/regen-
'.......J
erate) time of 5. 0 f-Lsec.
1-3
GENERAL DESCRIPTION
The basic storage elements of the TCM- 32 system are toroidal
ferrite cores.
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The cores are contained in a coincident-current core stack
consisting of a number of mats or planes equal to the number of bits per
word.
A mat or plane contains a number of cores equal to the number of
words of storage provided.
Each core is capable of storing one bit of infor-
mation; therefore, the total capacity of the memory equals the product of
the number of cores per plane and the number of planes.
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1-1
MAGNETIC CORE MEMORY SYSTEM
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The TCM- 32 magnetic core storage systems provide economical,
efficient, fast-access storage.
netically stored
inform~tion
The memory is equipped to retain the mag-
"
for an indefinite period even though primary
power is removed.
The data signal interface between the TCM- 32 and the external
digital equipment with which it is used is achieved via flip-flop registers.
This allows the addres s and the information signals from the external equipment to be specified as digital logic signals in the form of levels.
Command
signals are received by gates and are specified in the format of pulses.
,.-"
,
Memory operation is controlled by internal timing circuits and
occurs in response to one of several external command signals.
Certain
constraints exist between the timing of the command signals relative to the
data signals; however, once the timing requirements are satisfied in the design of the system, memory operation is essentially independent of the associated equipment.
Supervisory signals defining the status of the memory
operation or signaling the completion of various phases of operation can be
supplied to further augment the compatibility of the TCM- 32 with the as sociated external equipment (Figure 1-1).
1-4
BASIC ELEMENTS AND ORGANIZATION
Figure 1-2 presents a simplified block diagram showing the basic
elements and organization of a typical core memory system.
In brief, the
functions of these elements are as follows.
a.
Memory Timing and Control provides the sequence of pulses
necessary to perform a specified operation in response to a given command
(clear/write, read/regenerate, load, unload or read/m.odify/write).
(This unit generates the necessary timing signals for both the internal and
external requirements.)
b.
Address Register stores the specified address in binary 'form
(static flip-flops) for a specified cycle.
The outputs of the address register
are used to drive the X and Y decoders.
c.
X and Y Decoder s and Switches decode the contents of the ad-
dress register to select only the one proper address.
1-2
The selected switches
'-"1
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MAGNETIC CORE MEMORY SYSTEM
are set up to allow the drive current to read from or write into the ferrite
o
cores.
The current pulses are directed by the switches through the proper
X and Y drive lines.
d.
Core Stack utilizes a conventional four-wire coincident- current
wiring scheme.
The construction and operation of the core stack is described
in detail in Section III of this manual.
11
e.
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Information Register stores the information, one word at a time,
to be inserted into the memory during a clear/write or load cycle.
The
information register receives the output information of a selected addres s
during read/regenerate or unload cycles.
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This register also provides
double- rail outputs to the external equipment.
£.
Sense Amplifiers receive the output of selected cores, reject
noise, and amplify the outputs to set the information register.
amplifier is required for each bit of the information word.
One sense
The amplifiers
employ time and amplitude discrimination to determine a ONE or a ZERO
1
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core output.
g.
Inhibit Driver s are controlled by the information register and
timed by the inhibit timing pulse.
Each plane or bit is selectively driven in
the memory by its inhibit driver circuit during a write period.
When a ZERO
is to be written in the selected core, the inhibit driver produces a current
pulse which acts in opposition to the selected drive current.
If a ONE is to
be written, the inhibit driver is gated off by the appropriate flip-flop in the
information register.
1-4. 1
Memory System Layout
Figure 1- 3 identifies the unit layout of the memory system.
The
memory system is mechanically designed for standard 19-inch relay rack
mounting.
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Brief descriptions of each unit are listed below.
Unit 1 contains part of the information register, timing and control
circuits, and partitioning option.
Unit 2 contains selection switches, current drivers, read-write
gate driver, and inhibit drivers.
Unit 3 contains part of the information, and address registers.
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Unit 4 contains inhibit drivers, and address decoders .
.......-'
1-3
I-'
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READ
3
~~gAD:
REGENERATE
CLEAR-WRITE
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MEMORY TIMING AND CONTROL
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READ - WRITEl
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MEMORY
TIMING
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BUSY
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Z
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X DECODERS
DRIVERS
a SWITCHES
ADDRESS
STROBE
I-t
DIGIT
ISENSE
(INHIBIT) STROBE
TIMING
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ADDRESS , I
INPUT
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PARALLEL
LINES
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ADDRESS
REGISTER
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DECODERS
DRIVERS
SWITCHES
~
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CORE ARRAY
M
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SENSE
AMPLIFIERS t-
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Ul
K!
Ul
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INFORMATION
STROBE
~
INFORMATION
OUTPUT
M
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PARALLEL
LINES
--.-________________....J
INFORMATION -+r-\~,
INPUT
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PARALLEL
LINES
J
L________
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-
-
-
-
Figure 1-2.
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-
-
-
-
-
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-
-
-
-
-
-
- - -
Memory System, Block Diagram
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Figure 1- 3.
Memory System Layout
1- 5
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MAGNETIC CORE MEMOR Y SYSTEM
1- 5
INPU T SIGNALS
The addres s register varies from 7 to 12 bits, depending on mem-
ory capacity (size).
The minimum period of time and the time at which inputs
must be present for a random-address operation are shown in the timing diagrams of Section III.
Clear / write command initiates a cycle which clears the cores at the
address specified by the address register, and writes the information provided
in the information register.
Read/ regenerate initiates a cycle which reads the cores at the addres s specified by the addres s register and rewrites this information in the
cores previously read.
The information is held in the information register
until another cycle is started.
to the number of bits per word.
The size of the information register corresponds
Information is provided in parallel to this regis-
ter and must be timed as indicated in the timing diagrams of Section III.
1-6
MAGNETIC CORE MEMORY SYSTEM
SECTION II
SYSTEM INSTALLATION
1
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2-1
GENERAL
After unpacking the equipment, conduct a visual mechanical inspec-
tion to determine whether the equipment was damaged during shipment, and
immediately report any damage to the carrier or shipping agency.
During positioning and installation of the equipment, do not disturb
any factory adjustments.
Check that the AC power switch, located on the
front panel of the memory unit (Figure 1-1), is in the OFF position before
making any electrical connections.
The system is shipped with the core matrix, all S-BLOC chassis,
and 3C S-PACs® prewired and properly secured in place.
After completing
the mechanical installation of the equipment in the rack, conduct a second inspection to ensure that all wiring and PACs are secured.
Mechanical installa-
tion is illustrated in Figure 2-1.
2-2
J
ELECTRICAL INTERCONNECTIONS
The wiring of connectors J-l02 through J-I07 are defined in Tables
2-1 through 2-6.
The physical location of these connectors is shown in Fig-
ure 2;"2; the pin numbering scheme is illustrated in Figure 2-3.
A diagram
showing the power wiring of the TCM-32 is presented in Figure 2-4.
J
The AC
and DC power connections should be provided via the mating connector s
furnished by Computer Control Company.
Refer to the pin connections in
Figure 2-4 and note that two -18 volt connections are shown.
These connec-
tions should not be connected in PI0l but wired as separate leads back to the
power supply.
This will utilize the filtering capacitors in the power supply
and reduce noise on the -18 volt logic buses due to inhibit pulse current.
1
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2-1/2-2
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MAGNETIC CORE MEMORY SYSTEM
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UNIT NO. I TOP
UNIT NO 4 TOP
UNIT NO.3 BOTTOM
UNIT NO.2 BOTTOM
"s" PAC - INSERTED WITH
UNIT AT MAX. TILT POSITION
(SEE VIEW A-A)
+-- STD 3C
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CONVECTION
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INPUT _ OUTPUT -./14--__eo*__
A-A
CONNECTIONS
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VIEW
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LFAN
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(FILr~Ol
SLIDE MOUNTING ANGLE
STACK ENCLOSURE-
A
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A
STANDARD RELAY RACK
PANEL NOTCHING
_ _________. .t.
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Figur e 2 -1. Installation Dr awing
(Sheet 1 of 2)
2-3/2-4
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:MAGNETIC CORE MEMORY SYSTEM
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\TING
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ANGLE IN REAR OF CAsl N ET
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pos.
TILT
22 5/8 ~~~~LE
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10
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OUTER SLIDE RAIL
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SLIDE RAIL
--+-~:
I+-+----J~---___l_-----+- 27
14--t-----t- 16
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3/4 DIA. VENTING
HOLES IN BOTH SIDES
11/16--J
MAX. EXT.
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DIMENSIONS SHOWN ARE WITH
UNIT AT MAXIMUM EXTENSION.
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Figure 2-1. Installation Drawing
(Sheet 2 of 2)
2-5/2-6
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UNIT NO. I (REF.)
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AC INPUT JIOO
JI02
JI03
JI04
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JI05
JI06
..LL.lJL----- J 107
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MATING CONNECTORS (SHIPPED WITH TCM-32)
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1.
CONNECTOR, DD-50P 3C PART NO. 941 105 001
2.
PLUG, MRA-14S-JTC-H 3C PART NO. 941 114 001
3.
PLUG, M4S-LS 3C PART NO. 941 115 001
NOTES:
1.
UNIT WEIGHT (EMPTY) APPROX. 40 LB
2.
MAX. PAC EXTRACTION FORCE REQD 20 LB
3.
POWER INPUT -115 V AC FUSED ON FRONT PANEL.
DC INPUT INTERLOCKED THRU AC ACTUATED RELAY.
4.
MEMORY NORMALIZER BOARD (MN) IS LOCATED BEHIND
CONNECTORS Ji02, Ji03, Ji04, IN UNIT 1.
5.
INDICATOR POWER SUPPLY (WHEN INCLUDED AS AN
OPTION) IS LOCATED BEHIND CONNECTORS Ji05, J106,
Ji 07, IN UNIT 3.
Figure 2- 2.
Connector Detail
2-7
MAGNETIC CORE MEMORY SYSTEM
Figur e 2 - 3.
2-8
Pin Numbering, Connector s J - 102 through J -107
MAGNETIC CORE MEMORY SYSTEM
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POWER WIRING
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IIOVAC
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(J 100)
AC PLUG
7'/-18Z
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DC PLUG
(PIN SIDE )
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POWER BUSS IN UNITS 2
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2
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BOARDS A
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B
TO POWER BUSSES IN UNITS 2 EI 4
GND
11I--------------------------------~
46
46
45
44
43
45W
44 --,
43 ......J~----------------------------
Ploe
PII41JI14
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NORMALIZER BOARD
& && ~ 0
TO INHIBIT BOARDS e I} D
I~ ~ATO INHIBIT
__________________~~ 8
/
R ~--------------------~
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V ~--------------------~'-
FRONT PANEL
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SOCKETS
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UN ITS 2 a 4
UNITS 163
(A-BLOC)
I
BI
-k>o-
~
I 2
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ON
110 VAC
ROTRON
"MUFFIN"
FANS
I
51
I
I :B2-1~
II
I
I L:
--
J-:TCM-32 DOUBLE
ONLY
. ...J
Figure 2-4. TCM-32 Power
Wiring Diagram
2-9/2-10
J
MAGNETIC CORE MEMOR Y SYSTEM
TABLE 2-l.
WIRING CONNECTOR J-102
J
l
u
J
J
'I
I
l.J
I
.J
rr
I
LJ
J
(Connector location is found in Figure 2- 2
Figure 2-3 shows pin numbering)
Pin
Number
Signal
Function
Pin
Number
Signal
1
I-I
Information In
26
1-13
Information In
2
I-I
Information In
27
1-14
Information In
3
1-2
Information In
28
1-14
Information In
4
r:T
Information In
29
1-15
Information In
5
1-3
Information In
30
1-15
Information In
6
1-3
Information In
31
1-16
Information In
7
1-4
Information In
32
I=Tb
Information In
8
1-4
Infor mation In
33
1-17
Information In
9
1-5
Information In
34
1-17
Information In
10
1- 5
Information In
35
1-18
Information In
11
1-6
Information In
36
1-18
Information In
12
"[:"b
Information In
37
1-19
Information In
13
1-7
Information In
38
1-19
Information In
14
1-7
Information In
39
1-20
Information In
15
1-8
Information In
40
1-20
Infor mation In
16
1-8
Information In
41
1- 21
Information In
17
1-9
Information In
42
1-21
Information In
18
1-9
Infor mation In
43
1-22
Information In
19
1-10
Information In
44
y:-zz-
Information In
20
1-10
Information In
45
1-23
Information In
21
I-II
Information In
46
!-IT
Information In
22
I-II
Information In
47
1-24
Information In
23
1-12
Information In
48
r-vr
Information In
24
1-12
Infor mation In
49
Signal Gr ound
25
1-13
Information In
50
Chassis Ground
Function
'/
I
U
J
2-11
MAGNETIC CORE MEMORY SYSTEM
TABLE 2-2.
WIRING CONNECTOR J-103
Pin
Number
Signal
1
IR- i
2
Pin
Number
Signal
Function
Information Out
26
IR-13
Information Out
IR-l
Information Out
27
IR-14
Information Out
3
IR-2
Information Out
28
IR-14
Information Out
4
rrr:7
Information Out
29
IR-15
Information Out
5
IR-3
Information Out
30
IR-15
Information Out
6
IR-3
Information Out
31
IR-16
Information Out
7
IR-4
Information Out
32
IR-16
Information Out
8
IR-4
Information Out
33
IR-17
Information Out
9
IR-5
Information Out
34
IR-17
Information Out
10
IR-5
Information Out
35
IR-18
Information Out
11
IR-6
Information Out
36
IR-18
Information Out
12
IR-6
Information Out
37
IR-19
Information Out
13
IR-7
Information Out
38
IR-19
Information Out
14
IR-7
Information Out
39
IR-20
Information Out
15
IR-8
Information Out
40
IR-20
Information Out
16
IR-8
Information Out
41
IR-2l
Information Out
17
IR-9
Information Out
42
IR-21
Information Out
18
·IR-9
Information Out
43
IR-22
Information Out
19
IR-IO
Information Out
44
IR-22
Information Out
20
IR-IO
Information Out
45
IR-23
Information Out
21
IR-ll
Information Out
46
IR-23
Information Out
22
IR-ll
Information Out
47
IR-24
Information Out
23
IR-12
Information Out
48
IR-24
Information Out
24
IR-12
Information Out
49
Signal Ground
25
IR-13
Information Out
50
Chassis Ground
Function
n
r-·
1"-'
~,
2-12
J
MAGNETIC CORE MEMORY SYSTEM
'l
u
TABLE 2-3.
WIRING CONNECTOR J-104
Pin
Number
n
J
1
u
I
I
I__ .J'
lJ
Remarks
Function
1 and 2:
Twisted Pair
3 and 4:
Twisted Pair
5 and 6:
Twisted Pair
7 and 8:
Twisted Pair
1
.Input: Read/Regenerate
(SIG)
2
Input: Read/Regenerate
(GND)
3
Input: Clear /Write (SIG)
4
Input: Clear /Write (GND)
5
Input: Unload Buffer (SIG)
6
Input: Unload Buffer (GND)
7
Input: Load Buffer (SIG)
8
Input: Load Buffer (GND)
9
Input: Random / Sequential
Operation
-6 V: -Random
o V: Sequential
10
Input: Memory Clear (SIG)
10 and 11:
11
Input: Memory Clear (GND)
12
Input: Reset Unload Counter
13
Input: Reset Load Counter
(Addr e s s register)
14
Input: Reset Information
Register (SIG)
Pulse:
-6 V to 0 V
14 and 15:
Twisted Pair
15
Input: Reset Information
Register (GND)
16
Input: Drop-in (SIG)
Pulse:
-6 V to 0 V
16 and 17:
Twisted Pair
17
Input: Drop-in (GND)
18
Input: Read/Modify/Write
RMW
19
Input: Load Counter
(Advance SIG)
Pulse:
-6 Vto OV
19 and 20:
Twisted Pair
20
Input: Load Counter
(Advance GND)
21
Input: Unload Counter
(Advance SIG)
Pulse: -6VtoOV
21 and 22:
Twisted Pair
22
Input: Unload Counter
(GND)
23
Input: Addres s Register
Strobe (SIG)
Pulse:
Twisted Pair
Twisted Pair
-6 V to 0 V
i..J
2-13
l ....1
Ii
MAGNETIC CORE MEMORY SYSTEM
TABLE 2-3. (Cont)
WIRING CONNECTOR J-I04
Pin
Number
Ii
Function
Remarks
Ii
24
Input: Address Register
Strobe (GND)
25
Input: Address Register
Shift (SIG)
26
Input: Address Register
Shift (GND)
25 and 26: Twisted Pair
II
27
Input: Information Shift
(SIG)
28
Input: Information Shift
(GND)
29
Input: Information Register
Zone A
30
Input: Information Register
Zone B
31
Input: Information Register
Zone C
32
Input: Information Register
Zone D.-
27 and 28:
Twisted Pair
..
~
partitioning option
,'--'
33
Wired Spare
34
Wired Spare
35
Wired Spare
36
Wired Spare
,~'
37
Pulse:
-6 V to
aV
38 and 39:
Twisted Pair
Pulse:
-6 V to 0 V
40 and 41:
Twisted Pair
38
Output: End of Cycle
39
Output: End of Cycle
40
Output: Information Ready
(SIG)
41
Output: Information Ready
(GND)
42
Random Access
43
Sequential Acces s
44
Load Mode
45
Unload Mode
-6 V
-6 V
46
Power
+12 V
47
Power
-6 V
48
Power
-18 V
,~~
'~
-6 V
-6 V
49
Signal Ground
50
Chas sis Ground
2-14
,.-,
.,.-J
r~,
• .-1
I"l
'--'
r-'
c-'
J
MAGNETIC CORE MEMORY SYSTEM
TABLE 2-4.
WIRING CONNECTOR J-I05
J
J
1
U
I
'J
1
~J
1
LJ
Pin
Number
Pin
Number
Signal
Function
1
A-I
Address Reg. In
26
AR-7~:~
Address Reg. Out
2
A-2
Address Reg. In
27
AR-8
Address Reg. Out
3
A-3
Address Reg. In
28
AR-8*
Address Reg. Out
4
A-4
Addres s Reg. In
29
AR-9
Addres s Reg. Out
5
A-5
Address Reg. In
30
AR-9~:~
Addres s Reg. Out
6
A-6
Address Reg. In
31
AR-I0
Address Reg. Out
7
A-7
Address Reg. In
32
AR-I0*
Address Reg. Out
8
A-8
Address Reg. In
33
AR-ll
Address Reg. Out
9
A-9
Address Reg. In
34
AR-ll ~:c
Address Reg. Out
10
A-IO
Address Reg. In
35
AR-12
Address Reg. Out
11
A-II
Address Reg. In
36
AR-12~:~
Address Reg. Out
12
A-12
Address Reg. In
37
ARU-l~:~
Unload AR Out
13
AR-1
Address Reg. Out
38
ARU-2*
Unload AR Out
14
AR-l ~:~
Address Reg. Out
39
ARU-3~:~
Unload AR Out
15
AR-2
Address Reg. Out
40
ARU-4~:~
Unload AR Out
16
AR-2~:~
Address Reg. Out
41
ARU-5~:~
Unload AR Out
17
AR-3
Address Reg. Out
42
ARU-6~:~
Unload AR Out
18
AR-3~:~
Address Reg. Out
43
ARU-7*
Unload AR Out
19
AR-4
Addres s Reg. Out
44
ARU-8~:~
Unload AR Out
20
AR-4~:~
Address Reg. Out
45
ARU-9* - Unload AR Out
21
AR-5
Address Reg. Out
46
ARU-10~:~
22
AR-5~:~
Address Reg. Out
47
AR U-l1 ~:~ Unload AR Out
23
AR-6
Address Reg. Out
48
ARU-12~:~
24
AR-6~:~
Address Reg. Out
49
25
AR-7
Address Reg. Out
50
Signal
Function
Unload AR Out
Unload AR Out
'I
I
l.J
~:~AR U
and AR signals on request only
2-15
MAGNETIC CORE MEMORY SYSTEM
TABLE 2-5.
WIRING CONNECTOR J-106
11
Pin
Number
Signal
1
1-25
Information In
2
1-25
3
Function
Pin
Number
Signal
Function
26
1-37
Information In
Information In
27
1-38
Information In
1-26
Information In
28
1-38
Information In
4
I-2b
Information In
29
1-39
Information In
5
1-27
Information In
30
1-39
Information In
6
1-27
Information In
31
1-40
Information In
7
1-28
Information In
32
1-40
Information In
8
1-28
Information In
33
1-41
Information In
9
1-29
Information In
34
1-41
Information In
10
1-29
Information In
35
1-42
Information In
11
1-30
Information In
36
1-42
Information In
12
1-30
Information In
37
1-43
Information In
13
1- 31
Information In
38
1-43
Information In
14
Wi
Information In
39
1-44
Information In
15
1-32
Information In
40
r:44
Information In
16
1-32
Information In
41
1-45
Information In
17
1-33
Information In
42
1-45
Information In
18
r-"IT"
Information In
43
1-46
Information In
19
1-34
Information In
44
I=4b
Information In
20
1-34
Information In
45
1-47
Information In
21
1-35
Information In
46
r-47
Information In
22
1-35
Information In
47
1-48
Information In
23
1-36
Information In
48
1-48
Information In
24
I=3"b
Information In
49
Signal Ground
25
1-37
Information In
50
Chas sis Ground
2-16
1
U
MAGNETIC CORE MEMORY SYSTEM
TABLE 2-5. (Cont)
WIRING CONNECTOR J-I01
J
:J
1'1
I
U
J
n
I
\.J
Pin
Number
Signal
Function
Information Out
26
IR-37
Information Out
IR-25
Information Out
27
IR-38
Information Out
3
IR-26
Information Out
28
IR-38
Information Out
4
IR-26
Information Out
29
IR-39
Information Out
5
IR-27
Information Out
30
IR-39
Information Out
6
IR-27
Information Out
31
IR-40
Information Out
7
IR-28
Information Out
32
IR-40
Information Out
8
IR-28
Information Out
33
IR-41
Information Out
9
IR-29
Information Out
34
IR-41
Information Out
10
IR-29
Information Out
35
IR-42
Information Out
11
IR-30
Information Out
36
IR-42
Information Out
12
IR-30
Information Out
37
IR-43
Information Out
Pin
Number
Signal
1
IR-25
2
Function
13
IR-31
Information Out
38
IR-43
Infor mation Out
14
IR-31
Information Out
39
IR-44
Information Out
15
IR-32
Information Out
40
IR-44
Information Out
16
IR-32
Information Out
41
IR-45
Information Out
17
IR-33
Information Out
42
IR-45
Information Out
18
IR-33
Information Out
43
IR-46
Information Out
19
IR-34
Information Out
44
IR-46
Information Out
20
IR-34
Information Out
45
IR-47
Information Out
21
IR-35
Information Out
46
IR-47
Information Out
22
IR-35
Information Out
47
IR-48
Information Out
23
IR-36
Information Out
48
IR-48
Information Out
24
IR-36
Information Out
49
Signal Gr ound
25
IR-37
Information Out
50
Chassis Ground
.
~
lJ
2-17/2-18
r-r
J
MAGNETIC CORE MEMORY SYSTEM
SECTION III
PRINCIPLES OF OPERA TION
3-1
PRINCIPLES OF MAGNETIC CORE MEMORIES
3 -1. 1
Magnetic Core Storage
The memory core stack, housed in the magnetic core unit, is a
matrix configuration of individual small (50 mils O. D., 30 mils 1. D.) ferrite cores.
The cores are arranged in identical planes, each plane having
X-rows and Y-columns.
Basically, the ferrite core is a l-bit storage ele-
ment in the form of a ferrite ceramic ring that can be magnetically saturated
'l
lJ
to either positive or negative flux density.
The ferrite material retains a
large part of the magnetic flux developed at the time the core is saturated
which is an important characteristic of the core.
The time required to
switch a core from one polarity or state to another is primarily dependent
J
on the core material and size.
Consequently, cores measuring only milli-
meters in diameter are us ed in the memory core array to permit fast
switching speeds.
A similarity exists between the magnetic core and the flip-flop in
that both provide storage for one bit of data.
The two extremes of saturation
in a magnetic core represent ZERO and ONE, as do the two stable states of a
flip-flop.
A core can be set to a ONE state by the application of a current
pulse of similar magnitude applied in the opposite direction.
Similarly, a
flip-flop is set or reset by applying pulses to the appropriate inputs.
Both
the magnetic core and the flip-flop provide memory of the last pulse applied,
but the core does so without requiring power to hold its state.
The ferrite core has a nearly rectangular hysteresis loop.
The
hysteresis loop is a graphical representation of the flux density produced in
a magnetic material, plotted against the magnetizing force that produces it.
Figure 3-1 is a simplified drawing showing the generation of a typical ferrite
3-1
1..-1
~-
MAGNETIC CORE MEMORY SYSTEM
+8
A
----~~~---+
H
As Positive Current Increases
Rising Flux Density is Limited
by Core Saturation
+8
8
--_~""""fI/C-
___ + H
C ------:J+---+-.....~--+ H
Most of the FI ux Rema ins after the
Current is Removed.
As Negative Cu rrent Reaches the
Switching Point, the Core is Driven
to Negative Saturation
+8
D
+H
As with Positive Current, when Negative
Current is Removed, Most of t he Flux
Remains
+8
E
.-.
"-1
+H
Figure 3-1.
3-2
r-"',
Thus, the Core is always Saturated
in the Positive or Negative Direction
Ferrite Core Hysteresis Loop
'--1
'---',
",
1
I---.J
MAGNETIC CORE MEMORY SYSTEM
core hysteresis loop. Starting with an unmagnetized core, an increas e in magnetizing current (H) increases the flux density (B) along the S -shaped curve
(3 -lA).
The flux density levels off when the core is saturated, and any ad-
ditional current applied does not appreciably increase the flux density
caus e the core material is supporting as much flux as it can.
be-
A s the current
is decreased, then made to flow in the opposite direction, the flux does not
'i
U
I
collapse along the same line (3-lB); and most of the flux remains even after
the current has fallen to zero.
1L.l
The amount of flux actually remaining is a
function of the retentivity of the magnetic material.
As a magnetizing cur-
rent is applied in the opposite direction, it has little effect on the flux level
until the current reaches the knee of the hysteresis loop.
(Note that a cer-
tain amount of current is required to overcome the residual magnetism to
r-J
return the core to a neutral condition. )
1
I
A slight increase in current beyond the knee of the curve switches
'--..\
the core rapidly to negative saturation (3 -IC).
rr
l.J
The point on the curve rep-
resenting the amount of current required to change the state of the core is
termed the coercive current.
When the negative magnetizing current is re-
moved, most of the flux is retained as before (3-ID).
Note that the original
sweep from a magnetically neutral condition is never repeated (3-IE).
'I
u
'I
I
lJ
A
memory core in coincident-current use is never in a neutral condition, but
is switched from one saturated state to the other.
The core is thus an ex-
tremely useful binary component because it can exist in either of two stable
states and can switch rapidly from one to the other.
For any given toroidal magnetic core, the necessary magnetomotive
force required to effect switching is a
func~ionof
the product of the number of
turns of wire and the current driven through those turns.
It is not economi-
cally feasible to wind multiple turns of wire around the small toroidal cores
I
,-.J
used in core memories; rather the number of turns is reduced to two, one in
each of the perpendicular driving coordinates, and the current in these coor-
l.J
dinate wires is of such a magnitude as to cause switching (rapid flux change)
to occur.
'I
LJ
In addition to the perpendicular (X and Y) coordinate selection lines,
each core is also threaded by two other wires, each of which passes through
every core in a plane.
One is the sense winding, which detects flux-change
I.J
f'")
U
3-3
MAGNETIC CORE MEMORY SYSTEM
'~I
due to switching of a core and thus provides a readout
signal from the plane.
The other winding is the inhibit winding which is used, as its name suggests,
to inhibit or prevent the writing of a ONE into the core, thereby causing
ZERO to be stored.
A single memory core, with its associated control
'--'1
windings is illustrated in Figure 3-2.
A disadvantage of the memory core is that it does not provide a
static indication of its state, as does a flip-flop.
To obtain an indication of
1-'
the condition of the flux in a memory core, the state of the core must be
switched.
y- Line
.A-+-In'o-+-+--~
X- Line
Inhibit (Z) Line
Figure 3-2.
3-1.2
Core Control Windings
Addressing
The complete core stack for a magnetic core unit consists of a num-
ber of individual matrices or planes.
Each plane contains memory cores
assembled in a rectangular configuration.
The memory cores are threaded
by X - and Y -lines in each plane so that one memory core is physically 10cated at each junction of an X -line and Y -line.
As previously stated, pulses of current applied along the X - and Ylines switch a memory core from one state to another.
If one-half of the
current required to switch a core is applied along the X -line, and one -half of
the necessary current is applied along the Y -line, the core situated at the
3-4
r-,
MAGNETIC CORE MEMORY SYSTEM
junction of the energized X - and Y -lines will receive the full switching current.
This type of operation is termed coincident-current operation.
A coincident-current magnetic core memory depends upon the coin-
cidence of two half-currents to read data from or to write data into the cores.
Two additive half-current pulses will set the core to the ONE state, while
two half-current pulses applied in the opposite direction will reset the core to
the ZERO state.
A core with two half-current inputs is essentially an AND
circuit requiring that half-current be applied to both X - and Y -lines in the
same direction to change the state of the flux at the core.
A half-current
applied to one line without a similar half-current applied to the other line
has no effect on the core.
Only one X -line and one Y -line of a plane are energized during a
single cycle, and only that core situated at the junction of the activated Xand Y -lines will respond to the coincident half-current pulses.
Therefore,
only one core in each plane will be affected during a single cycle.
"
i
LJ
A simpli-
fied diagram of coincident-current selection of a memory core is illustrated
in Figure 3-3.
In effect, the X -line selects one row (X -row), and the Y -line
selects one column (Y -column).
In coincident-current memories, the X - and Y -lines are wired in
~
series through all planes of the memory core array.
Thus each X -line and
I
U
J
each Y -line threads corresponding rows or columns of cores in all memory planes.
Figure 3-3) supplies a half-current pulse to the appropriate row of cores in
every plane.
I
J
Energizing one of the X -lines (designated Xl through Xm in
Similarly, energizing one of the Y -lines (designated Y 1 through
Y n)' supplies a half-current pulse to the appropriate column of cores in
every plane.
When pulses occur· simultaneously on two lines (X and Y), they
s elect the same core position in each of the planes.
Therefore, the X - and
Y -lines select a word in the memory core array and enable read or write
operations.
l-.J
3-5
LJ
--1
MAGNETIC CORE MEMORY SYSTEM
Yn
,
---,
X,
--------~--------~------~~~~--~-----4~Half-Current
Half-Current
Figure 3-3.
3 -1. 3
Coincident-Current Selection
Information Sensing
-1
Sens e lines allow the reading of information stored in the cores.
One sense line (Figure 3-2) is threaded through all memory cores of each
plane.
To read any of the words stored in memory, half-currents in the
proper direction are generated in the selected X - and Y -lines (Figure 3 -3).
The read half-currents combine at the coincident junction of the X - and Ylines to change the state of the affected core in each melTIory plane.
If the
affected core is storing a ONE at that instant, the effect of the read halfcurrents will change the state of the core to ZERO.
If the core was previ-
ously in the ZERO state, the read half-currents will have no effect on the
core.
3-6
When the core is switched from the ONE to the ZERO state, the rapid
r-',
MAGNETIC CORE MEMORY SYSTEM
o
change in flux from positive saturation to negative saturation induces a volt-
o
o
age pulse in the corresponding sense line.
n
through Sk in the memory core stack are connected to sense amplifiers.
w
o
age pulse in the sense line during
been stored in the indicated core.
th~
Therefore, the presence of a volt-
read operation indicates that a ONE had
If no voltage pulse occurs in a sense line
during read operation, a ZERO is indicated.
The sense lines designated So
A
ONE input to any of the sense amplifiers is amplified and applied to the information register.
Thus, output data is transferred from its storage loca-
tion in the core stack to the information register.
3-1.4
Writing
Inhibit lines are used to enable a computer word or instruction to be
n
J
written into memory at a selected address location.
'1
of the magnetic core unit requires an individual inhibit line.
I
I
A single inhibit line is
threaded through each memory core in a plane (Figure 3-2), and each plane
U
To write information into memory, half-current pulses in the direction opposite to those generated for read operation are applied to the selected
X - and Y -coincident junction to switch the affected core in each memory
plane.
Since all the cores at the selected address have been cleared to the
ZERO state prior to the application of the write half-currents, the write halfcurrents operate to switch all cores to the ONE state.
If the incoming data
dictates that a ZERO is to be written into a specific core, some means must
be used to prevent the core from switching to the ONE state when the write
half-currents are generated.
o
designated Zl through Zk.
This is accomplished by the inhibit (Z) lines
An inhibit pulse, when transmitted through the
inhibit line of the memory plane at the same time that the write half-currents
are applied through the X- and Y -lines, prevents the writing of a ONE be-
r-"1
I
I
cause the inhibit current subtracts from X- and Y -write current.
L-J
The inhibit pulse is of the same magnitude but of the opposite polarity to the write half-current pulses.
Therefore, the inhibit pulse directly
cancels the effect of one write half-current pulse.
The net effect of the two
write half-current pulses and an inhibit pulse, is equivalent to a single write
J
3-7
MAGNETIC CORE MEMORY SYSTEM
n
half-current pulse on the addressed core.
This prevents the core from
switching from the ZERO to the ONE state.
Information to be written into memory is stored in the information
register prior to being transferred to the memory core stack.
During the
transfer operation, a binary ONE from the register flip-flop will prevent the
generation of an inhibit pulse whereas a binary level ZERO from the register
flip-flop allows an inhibit pulse to be generated.
In this
\Xlay
information is
rewritten (or new information is written) into the selected me:mory location
exactly as it appears in the information register.
3-1.5
Information Retention
The magnetic core unit does not require power to provide static
memory capability.
A pulse of power is required to switch the cores from
one state to another, but not to hold cores in their respective states.
All
cores remain in the state to which they have been switched, because of the
retentivity of the core magnetic material.
If power is removed or lost with-
out a severe transient pulse being generated, the core stack retains the stored
information indefinitely.
3-2
GENERAL SPECIFICATIONS, TCM-32 MEMORY SYSTEM
Capacity:
Words:
128, 256, 512, 1024, 2048, and 4096
11
Word Length: 8 to 48 bits (in 2-bit increments)
Cycle Time:
Full Cycle:
5 fJ.sec
Half Cycle:
3 fJ.sec
A cces s :
2. 3 fJ.s e c
Modes of Operation:
Clear/Write
Read/Reg enera te
Load
Unload
Read/Modify /W rite
3-8
r-,
MAGNETIC CORE MEMORY SYSTEM
Operating Temperature:
O°C to 50°C
Humidity:
950/0 without condensation
Power:
+12 VDC
-6 VDC
As supplied by S-PAC
Series RP-31 or equivalent
-18 VDC
Options:
Read/Modify /W ri te
1
1--.,)
Sequential Addressing
,...
Random-Sequential Addressing
J
Sequential-Interlace Addressing
i
Serial Addres s -Register Operation
Memory Clear
Information-Register Partitioning
J
]
Serial Information-Register Operation
Physical Description:
Standard 19-in. drawer mount
10-1/2 in. high
20-3/4 in. deep
135 lb maximum
Input Signal Specifications:
a.
Al1 input circuits are designed to operate between 0 V
and -6 V.
b.
Al1 inputs are diode coupled/isolated and provide noise
rejection margins of 1. 5 V minimum.
J
c.
Each input requires a flow of approximately 2.5 rna, when
the driving source is at ground and approximately 0 rna when
the driving source is at -6 V.
~J
d.
Each input that is not strobed or clocked must have a maximum rise time of 0.2 f.1sec (10% amplitude point to 900/0
amplitude point). Minimum pulse width is 0.3 f.1sec.
J
]
J
J
3-9
MAGNETIC CORE MEMORY SYSTEM
e.
Those inputs which are clocked or strobed may rise at any
desired rate as long as they fulfill specified timing requirements.
Output Signal Specifications:
3-3
a.
Outputs will swing between 0 V and -6 V.
clamped.
h.
All outputs are capable of driving 400 fJ.fJ.f of stray capacitanc e in addition to 20 ma from ground.
c.
Typical rise times are O. I jJ.sec.
0.15 jJ.sec.
All outputs
Typical fall times are
TCM-32 FUNCTIONAL DESCRIPTION
The basic function of the TC M-32 memory system is the magnetic
core storage of information which is fed to the memory by an external systern (typically, a computer) and the restoration of the information to the external system upon command.
A block diagram of the TCM-32 memory is
presented in Figure 3-4, to which this functional description is referenced.
3-3. 1
Address Register
The address register (AR) of the memory system is composed of
MF-30 flip-flops.
The AR stores the selected address in static flip-flops
for a specified cycle, and the AR outputs drive the X - and Y -decoders.
In
any of the optional sequential-addressing arrangements, the AR is wired and
operated as a counter.
3-302
X - and Y -Decoders, Switches, and Drivers
The X - and Y -decoders and switches decode the contents of the AR
so that only one memory location is selected.
A specific address input ac-
ti vates one X -row of memory cores and one Y -column of memory cores, as
shown in Figure 3-3.
The selected switches allow the drive currents to
read from and write into the corresponding cores of the memory array.
(The current pulses are generated from temperature-compensated, dynamically regulated drivers, the outputs of which are essentially independent of
supply voltages. )
3-10
r-->
I
MAGNETIC CORE MEMORY SYSTEM
[]
* EXTERNAL * EXTERNAL
RESET
AR IN
SHIFT -
READ/ ~
RESTORE - -
_ _ _ _ _ _"I_
!
--10
X-Y DECODER
CLEAR/ --.
WRITE
*MODIFY/
READ/
Y SWITCH
I
--,
I
I
I
1
INHIBIT
DRIVER
X
~
S
W
WRITE
I -
T
C
* MEMORY ___
H
CLEAR
J
COUNTER
(FOR SEQUENTIAL
ADDRESS REGISTER
I
SELECTION
L-_ _ _---,_ _ _ _ _--I _ _ _ --II
LOAD --.
]
1-----1,
L~I~CE ~~ON~
~_--lI:"'-"
UNLOAD
J
I
r---
I
AR.
OUT
lu
r
ADDRESS
REGISTER
* EXTERNAL
RESET
C01NT
1
* AR
* EXTERNAL
COUNT
MEMORY
CORE
ARRAY
~
r
-
r------0
---..JL
INFORMATION
OUT
lNFORMATION
IN
r------'"--'----lI-.......,
MEMORY
CLEAR OPTION
______ J
INFORMATION
REGISTER
·EXTERNAL
RESET
*
.EXTERNAL
DROP-IN
*
SENSE
AMPLIFIERS
I
U
*
I t SHIFT
J
L.....-... MEMORY- STATE
(LOAD/UN LOAD, RANDOM/SEQUENTIAL)
~ INFORMATION AVAILABLE
~ END OF CYCLE
Figure 3-4.
* INDICATES
OPTIONAL
SIGNALS
TCM-3Z Memory System, Block Diagram
J
3-11
MAGNETIC CORE MEMORY SYSTEM
3-3.3
Memory Timing and Control
The memory timing and control circuits provide the sequence of
pulses necessary to carry out the specific operation (read/regenerate,
clear/write, load, unload, and optionally, read/modify/write).
Timing and
control also generates the memory-busy signal, memory-state indicator
signal, an information-available marker, and an end-of-cycle marker pulse.
3-3.4
Memory Core Stack
The principles of the memory core stack are described in detail in
Section 3-1.
The core stack utilizes a four -wire coincident-current wiring
scheme and consists of a number of individual planes, each of which contains
magnetic cores as sembled in an X - and Y -configuration.
'--',
3-3.5
Information Register
The information register (IR) stores one information word which is
to be inserted into the memory during a load or clear/write cycle.
The IR
also provides output information during an unload or read/regenerate cycle.
This register is composed of flip-flops, and if the IR partitioning option is
employed, the portions, or zones, of the IR may be operated independently.
The IR provides double-rail outputs to the external system.
3-3.6
Sense Amplifiers
The sense amplifiers receive the output of the selected cores
tl~rough
the sense lines, reject noise, and amplify the outputs to set the in-
formation register.
The memory system has a separate sense amplifier for
each bit of an information word.
A sense winding comznon to all cores in a
memory plane detects a change of state of an addres sed core and provides an
input signal to the associated sense amplifier.
One bit of the selected word
is applied to each sense amplifier, thus transferring the addressed word from
storage to the IR, for further transfer to the external equipment.
3-12
n
l.J
J
MAGNETIC CORE MEMORY SYSTEM
Inhibit Drivers
3-3.7
Each inhibit Driver PAC, Model MI-32, contains eight circuits and
controls eight bits of a word.
Each channel of an MI-32 PAC receives an in-
put from the assertion output of one information register flip-flop.
A timing
signal (ZS or Z-step) is also received which is amplified to enable and properly time any channel.
l
.-1
The MI-32 PAC is described in the PAC appendix.
Each inhibit driver controls the flow of inhibit current through one plane of
the memory core stack.
Inhibit-driver conduction produces a half-select
current when a ZERO is to be stored during load, clear/write or read/regenerate memory operations.
An IR flip-flop disables its associated inhibit
driver when a ONE is to be stored.
'\
3-3.8
Current Drivers
I
~.J
The two Current Driver PACs, Model MD-32 are used in each
TCM-32.
A channel receives input signals from the RS or WS (read step or
write step) gate and provides a selection current of proper rise-time, falltime, and amplitude to a selected line.
appendix.
:J
The MD-32 is described in the PAC
Potentiometers for setting the output current amplitude are lo-
cated adjacent to the core stack enclosure in unit 2.
3-4
FUNC TIONAL DESCRIPTION OF SELEC TION AND DRIVING
TECHNIQUE
3-4.1
Memory C ore Stack
A typical schematic diagram of the memory core stack us ed in the
memory system is illustrated in Figure 3 -5.
drive lines are connected in groups.
switch on a Selection Switch PAC.
l..J
The ends of one side of the Y
Each group connects to a transistor
The other side of the Y drive lines con-
nect to outputs 16 through 31 of a Selection Switch PAC.
The decoded input
address information selects a transistor switch on each side of the Y drive
I
lines.
The logic design of the selection switches is such that only one line is
L.1
selected for any input address.
The X drive line connections are similar to
the Y drive line connections.
l ..:
3-13
... J
MAGNETIC CORE MEMORY SYSTEM
.-,
OUTPUTS 16 THRU 23
OF SELECTION
SwITCH #1
OUTPUTS 24 THRU 31
OF SELECTION
SWITCH "'1
OUTPUTS 24 THRU 31
r~'
OF SELECTION
SWITCH -4
OUTPUT 33 _ _ _ _ _ _.......
SEL. SW.
#,
OUTPUT 35 _ _ _ _ _ _ _ _ __
SEL. SW. -,
OUTPUT 33 ______________________
~
SEL. SW #2
OUTPUT 35 ___________________--'
SEL. SW. "'2
I
I
I
OUTPUT"'35
SEL.SW.#4 - - - - - - - - - - - - - - - - - - - '
71-163
Figure 3 -5.
Memory Core Stack, Simplified Schematic Diagram of
Y -Coordinate Sense, and Inhibit
r-'
3-14
J
J
J
J
J
J
J
MAGNETIC CORE MEMORY SYSTEM
Inhibit driver outputs are applied to the corresponding inhibit lines
designated Zk'
Resistors located on separate component·boards control in-
hibit current amplitude and provide transient damping.
component board is included in the appendix.)
(Information on the
The inhibit lines control the
insertion of data into the memory core stack for storage
The sense lines control the extraction of data from storage within
the memory core unit.
A sens e winding threads every core in a plane to
minimize output signals due to inductive or capacitive coupling to other
windings and those due to certain nonideal electrical characteristics of the
magnetic cor es.
3-4.2
Selection Switches
The X -row selection and Y -column selection are composed of
lLJ
Selection Switch PAC s.
Relevant sets of digits of the address register are
decoded and applied to the Y -column selection switches.
Similarly, other
sets of digits are decoded and applied to the X -row s election switches.
Since only one X drive line and one Y drive line are selected for a given adr-'1
dress register content, only one address receives the full coincident-current.
The method of selecting only one X drive line (or similarly one Y
drive line) is demonstrated by the simplified selection diagram (Figure 3-6).
To select drive line X o ' switches Q1 and Q3 are turned on by coincidence of
decoded address information (ODA and OD B ) and the read pulse (RP). The
I
I
other six switches are off.
'l
\. .J
Read current flows from ground through Q3,
memory line X o ' CR1 and Q 1 to the read current source. The diodes are
needed to steer the current through only the selected line. For instance, the
current can not flow through the path Q3-X2-CR6-CR8-X3-X1-CR3 and Q1 because of the reversed biased diode CR6.
During the write portion of the cycle, Q2 and Q4 are turned on by
coincidence of the write pulse (WP) and ODA and ODB' respectively.
Switches
Q 1 and Q3 are off due to the absence of a read pulse, and Q5, Q6, Q7, and Q8
are off due to the abs ence of an OD puIs e.
The write current flows from
ground through Q2, CR2, Xo and Q4 to the write current source.
The actual
method used by the memory system to select the memory lines is explained
as follows.
r]
I
3-15
MAGNETIC CORE MEMORY SYSTEM
'--"'1
"-"I
t
r~,
READ
DRIVE
CURRENT
r-~
RP
OD
A
QI
WP
ODA
RP
WP
PIN 33 .......- - - - - - - - _ e _ - - - - - - -
Q4
QS
-'
WRITE
DRIVE ~--------------------~---------------------------------~
CURRENT
Figure 3 -6.
3-16
Simplified Selection Diagram
IJ
J
,J
MAGNETIC CORE MEMORY SYSTEM
TO
l
---J
INPUT PULSE
l
,.J
SET ADDRESS REG.
a
RESET
INFO. REGISTER (SA- RI)
SELECTION SWITCH (RE)
31.1
2 1.1 SEC
11.1 SEC
SEC
4
JJ SEC
5 1.1 SEC
~
V
U
\
I
X-Y READ DRIVE (RS)
READ STROBE(STR)
I
INFO. DROP-IN (DO
'I
.J
J
INHIBIT (ZS)
I
X-V WRITE DRIVE (WS)
'
\
.....;
r-"-,
I
r-
MEMORY BUSY (MBS)
U
I
'._..J
~
I
Figure 3 -7 .
In te rnal TiITling
,,"\
3-17
MAGNETIC CORE MEMORY SYSTEM
Contents of the addres s register are decoded in groups; that is,
groups of three bits rnay be decoded into one of eight outputs via DP- 32
(S -117).
Enabled outputs of the decoders go to particular inputs of Selection
Switch PAC, SS-32, in which they are in turn gated against a read pulse or
write pulse input to enable driver current flow of one polarity or the other
".-,
through the selected coordinate lines.
3-4.3
Indicator Option
When used, the indicator option includes incandescent indicators on
the front panel, associated LD-30 Driver PACs, and the Indicator Power
Supply, Model PI.
3-5
OPERATING CYCLES
3 -5.1
Standard Cycles
The four standard operating cycles of the TCM-32 Magnetic Core
Mernory are load, unload, clear/write and read/regenerate.
The operating
cycle or rnode is selected by separate control pulses which are generated by
the cornputer or external systern.
The control circuits are shown in the rnern-
ory block diagrarn of Figure 3-4.
The internal tirning signals are shown in
Figure 3-7, and the various internal logic signals are identified in Table 3-1.
3-5.1.1
Read/Regenerate Cycle (Figure 3-8). - The read/regenerate
cycle transfers a selected word frorn storage to the inforrnation register
upon cornrnand.
As the reading process requires the resetting of all selected
cores to ZERO (destructive readout) the information in the information register is reinserted into core storage to avoid loss of the information.
The in-
forrnation is also retained in the inforrnation register for use by the external
system.
A read/regenerate command is required for each word unloaded.
The read/regenerate sequence is as follows.
1.
A core storage location corresponding to the word in the
address register is selected.
3-18
,'-',
J
J
MAGNETIC CORE MEMORY SYSTEM
I
READ/REGENERATE
1l.J
'1
,i
L-J
C
I
ADDRESS INPUTS
I
INFORMATION OUT
III NFORMATION AVAILABLE II
MARKER
D
I
MEMORY BUSY
To
I
IIJSEC
2PSEC
3IJSEC
4IJSEC
51..1SEC
'I
1
l)
Figure 3 -8.
Read/Regenerate Cycle External Timing
1
I.J
2.
Information stored in the selected core storage location is
read out into the information register, from which it is available to the external system.
3.
The information is also held in the information register.
The information in the information register is regenerated
'1
,I
L~
into core storage at the selected address.
The internal timing of the read/regenerate cycle is generated by
two TD-32 PACs in the timing and control section of the memory (positions
22 and 23 of Unit 1).
The first TD-32 generates the proper timing signals for
the read half of the cycle; the second TD-32 generates the outputs and internal timing signals required for the regenerate portion.
Upon the initiation of a read/regenerate pulse, two timing pulses
are generated by the TD, set address (SA), and reset information register
(RI).
These pulses set up the new address in the address register and clear
the information register to all ZEROs.
Pulse RE next enables the selection
switches to direct read the drive currents to the proper address.
1
l.-J
After the
selection switches are enabled, the X and Y drive currents are turned on and
timed by RS.
The outputs from the bits of the selected word are amptified by
the sense amplifier.
The read strobe pulse (STR) forms a part of the
" .J
l-l
3-19
MAGNETIC CORE MEMORY SYSTEM
detection of a logical ONE.
Pulse STR follows the X - Y drive currents so
that it occurs at the exact tilTIe when the core turnover
out is at its peak.
of a ONE being read
The outputs frolTI the read alTIplifier are directed to the
inforlTIation register which is then set up according to the inforlTIation read
frolTI the lTIelTIory stack.
[)
The outputs of the inforlTIation register supply the
word to the external systelTI.
The regenerate portion of the read/regenerate cycle is started by
the inhibit drive pulse (ZS) which turns on the inhibit drivers.
The width of
this pulse brackets the X-Y drive pulse (WS) and, together with WS, will restore the inforlTIation word into the selected storage location.
The end of ZS
signifies the end of the read/regenerate cycle.
3-5.1.2
Clear/Write Cycle (Figure 3-9).
- The clear/write cycle sets all
the storage cores of the selected address to ZERO, thenloads the cores with
an inforlTIation word.
A separate clear/write cOlTIlTIand is required for each
word loaded and inforlTIation is not read out when the cores are cleared.
C
J
ADDRESS INPUTS
I
CLEAR / WRITE
I
I
I NFORMATION IN
I
I.R. DROP-IN
I
I
MEMORY BUSY
To
Figure 3-9.
I~SEC
2 J,JSEC
3 J,JSEC
4 J,JSEC
5IJSEC
Clear/Write Cycle External Timing
,~,
3-20
J
MAGNETIC CORE MEMORY SYSTEM
The clear/write cycle is made up of the following steps.
J
J
J
1.
address register is selected.
2.
The selected location is cleared of all previously stored in-
3.
New information from the external system or computer is
formation.
loaded into the information register.
4.
J
J
~
\
l..J
1
L.,..,
The core storage location corresponding to the word in the
The information in the information register is then written
into the cleared storage location.
The clear/write cycle is initiated by an input pulse on the clear/
write line.
This cycle follows the same timing as does the read/regenerate
cycle with one exception:
a DI (information drop-in) signal will be generated
to transfer the information into the information registers, and the read strobe
(STR) puIs e will not be present.
The functional differences between the clear /
write cycle and the read/regenerate cycle are as follows.
The former will
s elect a location, clear the information from that location, and write in the
new information generated by the external system.
The read/regenerate
operation, on the other hand, will select a location, read the information
J
from this location into the information register from which it can be sampled,.
and then restore the identical information back into the selected location in
storage.
I
LJ
3-5.1.3
I
Load Cycle (Figure 3 -1 0). - In the load cycle one information
word is transferred from the information register to the storage cores at a
.~J
s elected address in response to a load command.
The number of words stored
J
is limited only by the word capacity of the core storage, but a separate load
n
sequencing the address register is used, an externally generated address is
command is required for each word. Unles s one of the optional methods of
required for each load command.
A load cycle consists of the following steps.
'I
I
LJ
1.
A core storage location is selected which corresponds to the
address word held in the address register.
'f
(
.•.-'\
3-21
MAGNETIC CORE MEMORY SYSTEM
I
LOAD
INFORMATION IN
I
I
I
DROP-IN
I
l
MEMORY BUSY
I
I~SEC
To
Figure 3-10.
2.
l
I
ADDRESS REGISTER
2~SEC
3~SEC
Load Cycle External Timing
An information word from the external system is loaded into
the information register.
3.
The information word in the information register is written
into the selected core storage location.
The load cycle is identical to the second half of a read/regenerate or
clear/write operating cycle.
Upon the application of an externally generated
load pulse, the second TD-32 PAC in the timing chain is activated.
The load
cycle has no provision for clearing the location to be written into.
Therefore,
this location must have been cleared (reset to ZERO) at the start of the load
cycle.
3-5.1.4
Unload Cycle (Figure 3 -11). - The unload cycle transfers one in-
formation word from core storage into the information register upon command.
An externally generated address is required for each unload command
unless the memory system is equipped with an optional method of automatically
sequencing the addres s.
3-22
,J
MAGNETIC CORE MEMORY SYSTEM
]
]
I
ADDRESS INPUTS
'1
J
UNLOAD
l
l ..-I
J
I
I
INFORMATION OUT
"INFORMATION AVAILABLE'
MARKER
I
D
I
MEMORY BUSY
I
l...J
To
,......,
I J,l5EC
2 J,l5EC
3 J,l5EC
I
I
~
t
.,' ,"
Figure 3 -11.
Unload Cycle External Timing
The unload cycle is identical to the first half of the read/regenerate
or clear/write cycle.
It is initiated by an external puIs e applied to the unload
"~
command line.
This pulse triggers the first TD-32 PAC in the timing chain.
,'-"
The timing chain produces the same timed sequences which are described in
the read portion of the read/regenerate cycle.
The second TD-32 is pre-
vented fro In being triggered by the "not half cycle" signal (He).
The HC
signal is generated by the output of a flip-flop, which is controlled by the unload input command. Becaus e the unload cycle results in a de s tructi ve read-
l.)
out, it will leave the addressed location in a cleared or "reset to ZERO"
state.
3-23
\
--'
MAGNETIC CORE MEMORY SYSTEM
TABLE 3-1.
INTERNAL LOGIC SIGNALS
NOTE
Positive-going (-6 volts to 0 volt) signals are indicated
by a bar over the signal designations.
Designation
3-24
Identification
CW
Clear/write command
RR
Read/ regenerate command
LB
Load command
UB
Unload command
SA
Set address register
RI
Reset information register
RE
Enable read selection switches
RS
X - Y read drivers
STR
Read strobe
DI
Information drop -in
ZS
Inhibit step and enable write selection switches
WS
X - Y write drivers
MBS
Memory busy signal
RMW
Re ad/ modify / wr i te
RDM
Random acces s input
LBA
Load set address
UCT
Unload addres s count puIs e
LCT
Load address count pulse
RU
Reset unload counter
RL
Reset load counter
LC
Load counter
UC
Unload counter
HC
Half cycle
RAN
Random address
RRF
Permit STR (read/regenerate flip-flop)
L
Load state
U
Unload state
'-",
,~,
r--'
MAGNETIC CORE MEMORY SYSTEM
J
TABLE 3-1. (Cont)
INTERNAL LOGIC SIGNALS
Designation
J
J
J
J
J
Identification
SB
Set busy
SR
Start read
ER
End read
EE
End extract
SZ
Start inhi bi t
EZ
End inhibit
EB
End busy
3-5.2
Optional Cycles
3-5.2.1
Read/Modify/Write. - A read/modify/write, cycle can be incor-
porated into the operation of a TCM-32 Core Memory System on request.
This option requires the addition of a read/modify/write control level.
J
~J
J
J
J
~J
The
read/modify/write cycle consists of an unload operation in which information
modified by the external equipment is read out.
then returned to storage at the same address.
The modified information is
The presence of the read/
modify/write signal (RMW) inhibits the address from changing while the load
cycle (LB) is being performed.
If the operation is sequential, RMW pre-
vents the generation of a count pulse at the end of the unload portion of this
operation.
Because both the load and the unload operations must be per-
formed at the same location, the address must remain the same for both half
cycles.
Thus an RMW operation consists of the following steps.
1.
Provide a ground level on the RMW line and hold it through-
out the extent of the operations below
2.
Provide a UB command puIs e
3.
Receive data and supply new data to the TC M
4.
Provide an LB command puIs e
J
J
3-25
MAGNETIC CORE MEMORY SYSTEM
(,
3-6
OPTIONAL MODES AND FEA TURES
i)
3-6.1
Sequential Addressing
When a memory is specified with a sequential method of addressing,
the address register is wired as a counter.
This is implemented in the wiring
of the three MF-30 PACs in positions 14, 15, and 16 of Unit 3 (Figure 3-10).
An external control is employed which will allow the operator to clear the
address register to all ZEROs, so that either load or unload operations may
be initiated at a defined address.
If an address -clear signal is given, ad-
dressing will start at ZERO andat each subsequent load or clear/write command, the memory will sequence to the next address until the desired information is written into the memory.
n
At this point an address-reset command
signal can clear the address register back to the ZERO address, and information can be read from the memory by a read/regenerate or an unload com-
"
mand until the information has been read from memory in the same order as
it was written.
3-6.2
Random-Sequential Addressing
The random-sequential mode of addressing is similar to the sequen-
tial method described above except that a random address may be provided
to the memory at any time and the memory can sequence from that point to
any of the operating modes.
Random-sequential addressing requires the ad",:
dition of two S-169 S-PACs in positions 12 and 13 of Unit 3 (Figure 3-12).
3-6.3
Sequential-Inter lac e Addr es sing
The sequential-interlace mode of addressing requires the addition of
r-'
a second address register, which is provided by the three MF-30 PACs in positions 21, 22, and 23 of Unit 3 (Figure 3-12).
This register is wired to
operate as a counter and stores the unload address.
i'
The register consisting
of the MF-30 PACs in positions 14, 15, and 16 of Unit 3 functions as the load
counter.
Gating of the load or unload register content to be used is per-
formed by the S-169S-PAC inposition18 (load) or the S-179S-PAC, position20
of Unit 3 (unload).
3-26
r-'I
I
L
J
[ J
C J
[ J
L_J
[-~
C J
L_J
L-_-J
l~~
L -]
L_~
l_~
L-J
r-
I
1
- - - - --
-
.
I
OVER 16 BITS
*
IR PARTIONING
INFORMATION REGISTER
a
SENSE AMPLI FiERS
LJ
L-J
[--3
2
4
6
8
10 12 14 16 18 20 22 24 26 28
B
R
B
R
B
R
B
R
B
R
B
R
B
R
B
R
B
R
B
R
B
R
B
R
B
R
B
R
D
L
P
N
P
N
P
N
:3
2
:3
:3
:3
:3
2
2
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
0
:3
2
3
2
3
0
3
0
I
2
3
4
5
6
7
8
9
10 II
A.
- - - -
~i~~R;1
x a
Y DECODERS,
TIMING a CONT/ROL
TIMING AND
CONTROL
\SPARE
INHIBIT
DRIVERS
~~t"\,-...A------..
_A
BITS
L~
FUNCTION
FUNCTION
A
LJ
~~~,.,....
BITS 24 32 40 48
0
S
I
6
9
D M T
L F D
T
D
M
1
M
I
M
I
M
I
D
P
D
P
D
P
0
P
C
L
C
L
C
L
3
0
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
:3
3
2
2
:3
2
0
I
2
3
4
5
6
7
8
9
10
II
12 13
3
0
3
2
D
1
:3
~
Cl
Z
POSITION NO
12 13 14 15 16 17 18 19 20 21 22 23
POSITION NO
UNIT I (TOP)
UNIT 4 (TOP)
UNIT 3 (BOTTOM)
UNIT 2 (BOTTOM)
M
1-3
H
o
o
o
:;d
M
POSITION NO
B
R
B
R
B
R
B
R
B
R
B
R
B
R
B
R
B
R
B
R
D
S
S
N
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
I
6
9
I
6
9
I
2
:3
4
5
6
7
8
9
0
10 II
12 13
M
F
M M
F F
P
N
3
0
3
0
3
0
3
0
a
S M
F
M M
F F
M
I
M
I
G
D
M
D
M
0
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
7
9
3
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
3
2
3
2
3
2
3
2
3
2
I
3
0
0
3
0
I
2
**
BITS
8
16
**
INFORMATION REGISTER
I
6
9
POSITION NO
L-
"
S
I
6
9
14 15 16 17 18 19 20 21 22 23
BITS 30 32 34 36 38 40 42 44 46 48
"-----..V'
S
L-
y
'''-.,---J
ADDRESS
REGISTER
SEQUENTIAL
INTERLACE
SENSE AMPLIFIER
:3
4
6
5
INHIBIT
DRIVERS
\
j
~
\
II
12 13
40961024
256(28)
SELECTION
DRIVERS
SWITCHES
l
~------------~v~--------------J
FUNCTION
**THESE POSITIONS
USED FOR MEMORIES OVER 256
WORDS CAPACITY
W
I
Figure 3-12.
10
"..,
* OPTION
THESE POSITIONS ARE SPARES
IF OPTION NOT USED
N
-.J
9
~
o
:;d
Kl
Ul
'-v-IV~
x- a YFUNCTION
8
""""-- L -
GATE DRIVER
y
7
2
~
M
S-PAC Location and Functions
Kl
Ul
1-3
M
~
MAGNETIC CORE MEMORY SYSTEM
The sequential-interlace option allows load and unload cycles to be
interlaced.
That is, the memory may be loaded, and while continuing to be
loaded, unload operations can be performed between the load cycles.
Load
and unload cycles may be interlaced in any sequence at any speed up to that
allowed by the minimum cycle time.
3-6.4
Serial Addres sing
'-";
The s erial-addres sing option is employed when it is desired to load
the address register in a bit-serial manner.
This is accomplished by wiring
the address register (positions 14 through 16 of Unit 3) to operate as a shift
register.
When this option is used the address register can be loaded in a
bit serial manner with a maximum shift rate of one megacycle.
r'
3-6.5
Serial-Information Inputs
The information register may be wired to operate in a serial shift
mode to receive a bit-serial input.
In a similar manner, data in the infor-
mation register can be shifted out bit-serial at a rate up to I MC, to convert
a parallel output of the memory to a single chain of puIs es.
3-6.6
Memory Clear
The memory-clear option, implemented by the inclusion of C L-32
PACs into positions 9, 10, and 11 of Unit 4 (Figure 3-12), provides a means
of clearing all information contained in the core stack with one operation.
This is accomplished by the application of a single positive-going pulse (from
-6 volts to 0 volt) which has a duration of at least 1.5 f.Lsec.
3-6.7
Partial Substitution
This optional feature provides the division of the information regis-
ter into independently controlled groups of flip-flops.
One group may be un-
dergoing a clear/write operation while another group is simultaneously
3-28
("-\
J
o
[J
J
o
J
J
J
J
J
J
n
MAGNETIC CORE MEMORY SYSTEM
operating in a read/regenerate mode.
The partial-substitution option allows
a portion of the information word to be changed without changing or destroying
other parts of the word.
The implementation of this option, shown in Figure 4-8, utilizes the
PACs located in positions 15, 16, 17, and 18 of Unit 1 (Figure 3-12).
These
PACs control the drop-in pulse to the information register and the strobe of
the sense amplifier so that the information register can be separated into
two, three, or four zones.
3-6.8
Signal Compatibility
Signal compatibility with voltage swings other than standard can be
accommodated.
3-6.9
Indicators
Individual display lamps for address register and information regis-
ter flip-flops can be added to the front panel of the TCM-32.
Other control
flip-flops can also be displayed to indicate the operating mode or condition of
the memory.
I
I
L.J
1
u
n
I
lJ
J
3-29/3-30
J
J
MAGNETIC CORE MEMORY SYSTEM
SECTION IV
LOGIC
4-1
This section provides detailed logic diagrams of the various mem-
rr
J
LOGIC DIAGRAMS
ory elements shown in the block diagram of Figure 3-4.
J
:J
The implementa-
tion of both standard and optional modes and operations are given as follows.
The logic diagram for the memory timing and control functions is
pres ented in Figure 4-1.
Figure 4-2 illustrates the logical connections of the addres s register for random addressing, sequential addressing, and random-sequential
addressing.
Figure 4-3 presents the logic diagram for the address registers as
connected for the optional sequential-interlaced addressing mode.
The logic diagram for the X - Y decoders and s election switches is
given in Figure 4-4.
1
I.J
'I
I
I
l.-J
Logic diagrams for the information register, sense amplifiers, and
inhibit drivers are presented in Figure 4-5 (bits 1 through 16); Figure 4-6
(bits 17 through 32), and Figure 4-7 (bits 33 through 48).
Figure 4-8 is a logic diagram of the partial substitution option which
shows the partitioning of the information register into two and four zones.
The optional memory-clear feature is shown in the logic diagram of
Figure 4-9.
The locations of the PAC s which provide these logic functions are
shown in Figure 3 -12.
4-2
INPUT/OUTPUT LOGIC SIGNALS
The various input and output logic signals used in the TCM-32 mem-
ory system are identified and defined in Table 4-1.
The designations given
in the following table are employed in the logic diagrams of Figures 4-1
4-1
I
1--1
MAGNETIC CORE MEMORY SYSTEM
through 4- 9.
Positive -going signals (- 6 volts rIsing to 0 volt) are indicated
by a bar over the designations.
TABLE 4-1.
LCXJIC SIGNAL LIST
Designation
Identifica tion
r,
Standard inputs
RR
Read/regenerate - operation cOIllIlland pulse
CW
Clear/write - operation comIlland pulse
LB
Load - cOIllmand puIs e
UB
Unload - command pulse
A-I
AR input - address inforIllation for random access
(levels)
I-I·
IR input - input data for inforIllation register
(double - rail levels)
RDM
RandoIll - level to distinguish random acces s froIll
sequential addres sing
Standard outputs
AR-l
AR outputs - addres s information froIll one side of
flip-flop
IR-l
IR outputs - output data from both s ides of flip -flop
Optional Inputs
RMW
Read/modify/write - level which allows memory to
unload, delay, then load at the saIlle addres s
MeIllory clear - pulse which clears all information
froIll meIllory
AR clear - pulse which clears the address register
AR shift - pulse which shifts the address register
hit-s erially (s erial addres s option)
Load address clear - pulse which clears the load
address register (sequential-interlace option)
Unload address clear - pulse which clears the unload address register (sequential-interlace option)
LCT
4-2
Load address count - count pulse which advances
load addres s register (s equential-interlace option)
r-·~
1
1•
MAGNETIC CORE MEMORY SYSTEM
.-1
TABLE 4-1. (Cont)
LOGIC SIGNAL LIST
Design~tion
Identification
Optional Inputs
(Cont)
n
LJ
:J
]
UCT
AR count - pulse which advances address register
(all other sequential modes of addressing)
SA
AR set - pulse which strobes addressing data into
address register
DI
IR set - pulse which strobes information into information register
RI
IR clear - pulse which clears information register
ICT
IR count - pulse which advances information register
TA, TB,
TC,TD
Partial substitution (IR partitioning) - levels which
control the information register zones as to RR
or CW mode
IRS
IR shift - puIs e which shifts information register
(in bit-serial mode of operation)
Optional Outputs
J
n
LJ
r:
EC
End of cycle - puIs e which signals the end of any
cycle
MBS
Memory busy -level which will be -6 volts throughout any operating cycle
IA
Information available - pulse which signals that information can be sampled from the information
register
PR
Power failure - indication of a power failure in
the system
RAN
Random - level which indicates that the memory is
operating in a random-addressing mode
SEQ
Sequential - level which indicates that the memory
is operating in one of the sequential-addressing
modes
L
Load - level which indicates that the memory is
operating in a load mode
U
Unload - level indicating that the memory is operating in an unload mode
lJ
4-3
L.J
MAGNETIC CORE MEMORY SYSTEM
---.1
11
TABLE 4-1. (Cont)
LOGIC SIGNAL LIST
Designation
Identification
Operating Voltages
+12 volts
Output of the power supply
- 6 volts
Output ,of the power supply
-18 volts
Output of the power supply
Signal ground
Ground level of the logic circuitry
Chas sis ground
Ground level of the memory frame and rack
'--1
4-4
J
J
J
MAGNETIC CORE MEMORY SYSTEM
(5-169)
RR
1-19
(5-169)
1-23
10-32
J
J
STR
2
BITS 17-32
RE
_USt~+-
]
1-20
-IIS;;..II-_ _ _ _ _-+
MF
cw>---+--+
J
1-21
__- .______~
OV--~1,.oI'
1-19
_us II
ER
_us 11
EE
3D
>-
~
UF
18-t--t-......---.......-:~
....-_.....
,.....,
i
(S-169)
L.J
HC
JIII-40
INFO. AVAILABLE.
J-104 PI N 40
EE
33
,~--
RI EXT
J-104
PIN 14
1-22
10-32
_us I
'I
JIII-
.J
HC -)30
RAN ~31
(S-169)
r -
EE 732
RMW733
_us 1...1---+----+
:
UCT)---7
EXT
I J-104 PIN 21 JIII-29
I
ZS
>-_-oE" I _US ;;..'1---1
_us 11
1-19
J
1-19
EZ
I
I
JIII-49
I
Jill-50
r - - - - - - - - - -»
RMW
~
20
Dr I BITS 1-16
I
-.J
3-11
1-19
1-21
r-;
I
LOAD MODE
J-104 PIN 44
L
LeT
RRF
ROM
1-20
DI2 BITS 17-32
LB*
: (8-169)
LBA(FOR SEQ. INT.>
~~~ . : " 0 . - -
RMW
I
MF
(FOR RANDOM-SEQ.)
O.v. - .,
J
-- - - - - - - -
JIII-39 (FOR SEQ. BLOCK)
J
-iJCT- - - -
-+-4t--
RANDOM ACCESS
J-I04 PIN 42
RAN
DI3 BITS 33-4€
"
l.J
U
UNLOAD MODE
J-104 PIN 45
1-19
SEQUENTIAL ACCESS
J-104 PIN 43
Figure 4-1. MelTIory TilTIing and
Control, Logic DiagralTI
4-5/4-6
MAGNETIC CORE MEMORY SYSTEM
1-19 PIN 11
J
J
LCT
ADDRESS REGISTER PART
'W---_
r
26
~ 27
3-12
~~~ 2~4
- ~I
r;1
3 -13
~
'---t-=e-~.J.. V
~
1O-+-.....+--t_~ LC2
2}
3-~F 1
. 3D-t---C~"LC3
......._ _ _+-........_22..
3-13
..... 31
'---+<134
~
r- 32
.... 17 9hLJo_-f-...2:.:.1~...
~V
JI05-6
,'--
A6.,,-~
3-12
II
13
16...
12h
I2Lr-~~----~r+~v~
.>-1;V
13-+---4I~"
-
-
.. LC3
..-
'"210 C
SAl
MF
'--
~ 12
14
-HI
17... 10-+-..----i.., LC6
}--+-+-I..~2Io B
~
13
1
LC 6
12
C
3-16
r ~~
14 11 .J-t......_ _---1t-t-~24..... MF
1'-..
AI2
~ G16
LC9
26-+--+--LC 12
..
--27
---
3-13
25
... 28
23...
_~3
~21
33-t-..-H-LC II
3-12
J105-12
3 -15
".:'\.
3-13
33-+-.....-
30-l--t--4~ LC
~~U
"'10 B
]
10~.-+--LCIO
L
~4
I
13+-........... LCIO
3-12
I"""""
~
MF
...... 12
~
3-12
~
~
_~5
6~'-~~LCI
19 ...
10
3-16
>--+------t-+-....1-!6--.
...
3-13
-~7
~15
JI05-2
r'\'----~
)--.___-+-+-+1~8.... MF
~
'-+----4~".LCI
(8-169)
]
ON
ON
(S~-169)~_14
AI)--
I~
LC5 _ 22
LC3 _ 23
24
LC4 -~.
LC2 - .33
LC6 _ 34
3-12
A
D D
25
35
RANDOM ADDRESS
SEQUENTIAL BLOCK
RANDOM-SEQUENTIAL
J105-1
3- I
3- I
33
29-+-+----4--LCI2
210 0
K
'--------'
~~------~------------------------~-----+-----------------------------~----+---------------------------------~
L:1"
3-17
~
1-18 PIN 24
EXTERNAL ADDRESS CLEAR
(-6 VOLT TO 0 VOLTS
..r-t.PULSE ;;
2~SEC)
.••~
~:
J
4~:13
SA3JIII_37
TO PIN 20 3-14,3-15 AND 3-16
8''''''''''-:---
~-I04-1~~
29 21
4 -13
~
JIII-34)-- 31
33
~J
01
28
24
~-13
SA 2
)-----j..-~.JO
JIII-35)-- 25
JIII-36 ~~
"
"--....;,,~,,)....--I
r--I-'
.26
23
]J
.!V
Figure 4-2. Address Register,
Logic Diagram (Random Addressing,
Sequential Addressing, and RandolTISequential Addressing)
r-,
J
4-7/-4- 8
J
MAGNETIC CORE MEMORY SYSTEM
]
ADDRESS REGISTER PART
SEQUENTIAL INTERLACE
J
n
-t----I!P-" U C 7
J
]
EXTERNAL LOAD
ADDRESS CLEAR
-6 VOLTS TO
0
VOLTS J1. 2~SEC
WIDTH
TO PIN 20 OF 3-14,
3-15, AND 3-16
LC4
l
"J
EXTERNAL UNLOAD
ADDRESS CLEAR
J
-6 VOLTS TO 0
VOLTS IL 2~SEC
WIDTH.
I
TO PIN 20
OF 3-21,3-22
AND 3-23
L.J
-+--.........~LCIO
-t----I!P-"U C 10
J
LC AND UC INPUTS CONNECTED
ONLY FOR SPECIFIED WORD CAPACITY.
EXAMPLE: FOR 2048 WORD MEMORY
LCI2 AN D UCI2 ARE REMOVED.
Lca
I
lJ
'1
-t----1~~LC5
+----1~.. L C II
-t----1r-p. UC II
l.J
-t-....,~--u C II
'I
L.. J
l.J
,-+-----.. LC 12
+-'----LCI2
l...J
J
'I
lJ
.. U C 12
-t---t~
3-18 {S'169l
Figure 4-3. Addres s Register,
Logic Diagram (Sequentia1Interlace Addressing Option)
4-9/4-10
J
J
MAGNETIC CORE MEMORY SYSTEM
2-4
4-5
~J
J
ARI
ARI
-
DP
6
35
AR2
AR2
AR9
AR9
B
33
1
34
001
002
003
004
AR3
AR3
J
AR4
AR4
ARII
ARII
RS--.
L
005
006
007
008
J
J
TO IRY
POT
TO lRX
'---
34
14
22
19
RPy
READ X
CURRENT
20
32
~
00-1
Wp·y
7
13
0015
32
0016
00-9
TOIWY
16
12
ViS ...
17
POT
WRITE Y
00-10
10
22
WRITE
20
'--
LJ
0021
RP X
0023
00-17
0024
WP x
]
2-3
4-8
AR7
AR8
AR8
ARI2
19
ARI2
6
ZS
0025
0026
0027
0028
0029
U
'I
lJ
~J
0031
0032
~
'14 ~
~
~
10
.E
1
13
•
tv
...
00-4
~~
YO, Y2, Y4, Y6,
YI6, YIB, Y20,
Y22
OD-II
---;::::L
~
RE
YI, Y3, Y5, Y7,
YI7, YI9, Y21,
Y23
rw
WP y
~~
'30
OD-G
G=L~
II
-=r~
-.
00-12
~~
10
J-
15
~
00-5
r!1-
r!!... r!!-
7
RP y
24
g
r;:l
12
'31
13
r-G~
21
~~"22
~
~ 24
I
~
12
rr=c~
~
~~
~~
..
...
YB, YIO,YI2,YI4'OO-i3
Y24, Y26, Y28,
Y30
Y9, Y II, YI3, Y15,
Y25, Y27, Y29, 00-14
Y31
II
~
30
~
p~
~~
..-
~~
15~~
10
GO
00-18
12
SS-32
,!!
g
...
~
rt2-
21
.~~
.~~
~23
~
24
26
~~
~
~~'2i
-
16- t- WP y
~
18- t-RPy
00-25
2-10
~
II
32- f-WP X
25
0030
rT
I
34
78
.r--G~
13
g
rrx ;;
34
0022
DP
WPy
24
.
7
SS-32
~
32
I-
YI6
YI7
Y24
Y25
Y4B
Y49
Y56
Y57
YIB
YI9
Y26
Y27
Y50
Y51
Y58
Y59
-
32
~
SS-32
34
RP y
00-7
7
13
I
WPy
00-8
Y32, Y34, Y36, 00-15
Y!8, Y48, Y60,
Y52,Y54
12
po
Y20
~
18
Y21
Y28
r"jg
r-'-
~
~ ~Jb22
~ ~
-...
24
~
r;:l~
~ 27
~
II
16
Y52
Y53
Y60
Y61
Y22
Y23
Y30
Y31
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ALL OUTPUTS GO TO CORE
STACK SELECTION LINES
Figure 4-4. X - Y Decoders and
Selection Switches, Logic
DiagralTI
4-11/4-12
J
MAGNETIC CORE MEMORY SYSTEM
1-4
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4-13/4-14
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Figure 4-6. Infor:mation Register,
Sense A:mplifiers, and Inhibit
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4-15/4-16
**
MAGNETIC CORE MEMORY SYSTEM
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-
J"Oo
IR45
20
21
t::t~. .
32
Z45
IR46
22
23
t:::t .I
-""\
33
Z46
IR47
24
25
~
H./
34
Z47
IR48
26
27
H}
35
Z48
BOARD
ZS
7
-
~
71-166
ri
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Figure 4-7. Information Register,
S ens e Amplifier s, and Inhibit
Drivers, Logic Diagram (Bits 33
through 48)
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1-:::1)-
RI
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31
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25
01-3
~-----------------------------.-----+~------------------------------+-t-
r,
Z35
17
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0...
22
23
12
29 IR'~ J 107-39
S
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30
4'4
to/A~
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H'
../
-
-V
27
MI-32 PAC'S
*** TO
TO CORE STACK VIA INHIBIT
J107-38
Z34
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15
Y
11 ~
29
20
21
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IA'4¥ J 107-37
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IR43
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JI06-39II-4'4 1i&\
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J106-37
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JI06-28'(i'73B :;M23
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12 IR'3? I J107-25
1t------G~~_'!./.18..&...oL
SW·37
V
Z33
29 IA'48y' J107-47
.....
3·8
BR-32 r---
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17
L....i-!!
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16
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R ,22
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/
IR38
Al
22
B
BR-32 ~
f~ )~==::J 12
tt-----4\,....;t":!-"'V 24
iff.421 J107-36
15
IR36
MI-32
..1'0
14
R
~
JI07-35
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IR35
IR'46Y J 107 -43
~21
'--~
J 106-4511-47 ~li)
V
V
SW·48
SW'48
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13
~
J 106-48"y;"748
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SW'42
SW·42
JI07-34
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....- - - -...-t~1-V24
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27 IR'4SI J107-44
9----~.-t-~:!.I.18....
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J106-35 /1.42
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I _ + 3'1',,23
r---
5
29 IR.3.§:( J107-23
SW-36-1-~
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r--
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R 22
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IS
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11
12
3-10
.....---~P-..,..,,~)18.....
SW·41
SW·41
A
'6.
3 1-46 126\
J 106-43
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JI06-44~46 ~23
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r"V 24
V
12 IR·45 1 J107-41
SW'46-1-~
R
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SW-46-1-~
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JI06-34'r!~ ~21 BR-32r--V
17\=)===1 12IR·4!J
J106-33 11'41
L....f:
JI06-24Y!'36 L5J23
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29 IA '4 Q]
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SW·40
~
SW'40-'-~
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T""'r
A
r---
fif.3~JI07-30
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4-3
3-9
...--------t!1)
3-7
SW'35-t-~
I
R
L#
J106-31 LI·40 126\
.......,~_22..-_ R I
17 }\===~
12
.--------.....-I"'t-''!I,II.....
S
r--.,
A
3~}
e--------4It--1~...Tij24
3-4
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11
J I 06-32'yI--:-;;w :;;\12j
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~
J 107 -29
*
1! ~-39
~~
L...-_+to/
R
B
BR·32-
.-r------~~~~_I~I~.~.~h
J106-29 P'39 15\
27 ~ I J107-20
126\
~21
SW·39-r-~
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SW'34-r--~
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JI06-30U-39
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SW'39-r-~
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J106 '2YION4 l,;\31~23
3D}
r.....,
V
IA'~ J107-17
3-6
4-17/4-18
**
MAGNETIC CORE MEMORY SYSTEM
1-20 PIN 18
ST--~
1LJ
D I 1-20 PIN 33
1-18
STA
DIA
n
J
TA
J-104 PIN 29
J
J
I
DIB
TB
J-104 PIN 30
n
J
L
1-17
DIC
TC
l
J-104 PIN 31
LJ
STD
J
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1-16
TO
J-104 PIN 32
L
INPUTS T(A,B,C,OR 0)
OV FOR READ/RESTORE
-6V FOR CLEAR/WRITE
CLEAR I WRI TE PULSE WILL START EITHER CYCLE
Figure 4-8. Partial Substitution Option, Logic Diagram
(Two-Zone, Three-Zone, or Four-Zone Information-Register
Partitioning)
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4-19
~
I
N
o
CLEAR
CLEAR
CLEAR
4-9
4-10
4-11
S103
S103
S103
~
C)
Z
I II ""'-.
*
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)
*
I II,
t-:I
\
M
t-3
H
*
()
()
0
~
M
~
M
~
0
~
~
C/l
~
C/l
t-3
M
~
JI04-10)
•
CLR
•
*
Figure 4-9.
5103
PAC OUTPUTS
GO TO INHIBIT COMPONENT BOARDS.
Clear Option, Logic Diagram
l
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1
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1
1
J
J
1
J
J
MAGNETIC CORE MEMORY SYSTEM
J
o
SECTION V
MAINTENANCE
o
o
5-1
GENERAL
This section of the manual contains information on the maintenance
of the TCM-32 system.
Data is included on the preventive maintenance,
corrective maintenance, service, and repair for the Model TCM-32 Magnetic
Core Memory.
Detailed PAC descriptions are included in the appendix of
this manual.
~
lJ
5-2
TEST EQUIPMENT
Table 5-1 lists the test equipment required to properly service the
memory system.
J
J
'I
i
.-1
TABLE 5-1.
TEST EQUIPMENT REQUIRED
Os cillo scope
Tektronix, Inc., Type 545A, or equivalent
Dual Trace Preamplifier
Tektronix, Inc., Type CA, or equivalent
Multimeter
Simpson, Type 260, or equivalent
Extender Card with Current Probe Leads
3C PAC, Model XP-30
r-"J
I
U
AC Current Probe
o
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5-3
Tektronix p60 16 probe and passive termination (or Type 131 amplifier), or equivalent
PAC LOCATIONS
The PAC locations in each BLOC of the TCM-32 system are shown
in Figure 3-1.
o
5-1
MAGNETIC CORE MEMORY SYSTEM
5-4
PAC HANDLING AND REPAIR PROCEDURES
5-4. 1
Inserting and Removing System PACs
a.
Never remove or insert printed circuit cards without turning
off the DC power to the unit.
Failure to turn off the power may result in dam-
age to the PAC.
b.
r-'"
S-PAC insertion is accomplished by engaging the S-PAC in the
appropriate slot of the S-BLOC and pressing the S-PAC into position until the
connector engages and sets.
The S- PAC is inserted with components on the
left.
c.
S- PAC removal in S-BLOCs is accomplished by engaging the two
holes at the handle end of the S-PAC with the S-PAC extractor tool.
A 20-lb
force is sufficient to disengage any S-PAC from its mating connector.
S-PAC can then be removed with the fingers.
The
The tool should be engaged
from the component side of the S- PAC to ensure against possible damage to
the etched wiring.
d.
A hold-down bar is provided which clamps the S-PACs in place
in the S-BLOC.
The bar is equipped with a quick release thumb latch and
bears against the S-PACs with a sponge rubber pad.
e.
Polarization of the connectors is accomplished by inserting two
nylon pegs in the appropriate slots of the connector.
This prevents any but
the desired S- PAC type from being inserted in that slot.
5-4. 2
PAC Troubleshooting
The Extender PAC, Model XP-30, can be used to gain access to
points on the PACs.
Signals on the pins of the PACs may be as certained from
the PAC descriptions. The actual PAC signals can be compared with the waveforms shown in Figure 5-2.
Leads for observing current waveforms with an
AC current probe are provided on special Extender PACs.
5-4. 3
Component Checking
a.
General.
Many PACs have several identical channels.
In most
cases components can be checked by resistance comparision with parts on other
channels or other PACs.
5-2
J
MAGNETIC CORE MEMORY SYSTEM
b.
Transistor checking.
with an ohmmeter.
Transistors on a PAC can be checked
This should be done carefully to avoid damaging the tran-
sistors by large meter currents.
Check the base-emitter and collector-
emitter junctions in both directions, by using the meter scale which will apply
I
~J
the least amount of current to the transistor and still provide a reading. Replace any transistors that have open or shorted junctions, or whose resistance
readings differ considerably from those obtained from a transistor on an identical channel or PAC.
c.
Diode checking.
Check diodes by comparing their forward and
back resistances with diodes of the same type on other channels or PACs.
d.
Resistor and Capacitors.
Using an ohmmeter in the conventional
manner, free one end of the component and check its resistance.
r;
I
I
\-..:
J
To check
most small capacitors for opens, a vacuum-tube ohmmeter will be needed to
induce a needle "kick".
5-4.4
1
Component Replacement
a.
Use only top quality rosin-core 60/40 solder (60% tin, 40% lead).
b.
A small hot soldering iron should be used.
A heat sink in the
L-)
form of a pair of plier s or an alligator clip on the lead of the component is
J
recommended to conduct heat away from the body of the component while
soldering.
c.
board.
J
1
Remove excess solder from the etched side of the printed circuit
A piece of spaghetti, large in diameter, can be used for blowing ex-
cess solder out of eyelets.
d.
Insert leads of the new component into and through the drilled
hole or eyelet, clip off excessive wire, and solder from the etched circuit
side of the PAC.
LJ
e.
Examine the PAC carefully for excess solder.
posits with a commercial cleaning solvent.
Remove rosin de-
Wipe the PAC clean with a dry
lint-free cloth.
f.
Recommended replacement parts for PAC components are
shown in the PAC parts list in Appendix A.
5-3
MAGNETIC CORE MEMORY SYSTEM
5-5
SPARE PARTS
Table 5-2 lists the PACs suggested as spare parts for maintenance
r1
and as aids in troubleshooting.
TABLE 5-2.
SPARE PAR TS LIST
Number Required
Per System
PAC De s ignation
Model
Selection Switch PAC
SS-32
Dynamic Current Driver PAC
MD-32
Bit Register PAC
BR-32
4-24
Inhibit Driver PAC
MI-32
1-6
Gate Driver PAC
GD-32
-1
1
Address Decoder PAC
DP-32
4
1
Memory Normalizer Board
MN
1
1
Inhibit Component Board
IB
1-4
1
Gate PAC
DN-30
1
1
1
1
NAND PAC
. DI-30
Spares~:c
4-8
2
2
1
2
NAND PAC
DL-30
1
1
Multi-Purpose Flip-Flop PAC
MF-30
3-7
1
Non- Inverting Power
Amplifier PAC
PN-30
2-4
1
Memory Clear Driver PAC
CL-32
0-3
1
Timing Distributor PAC
TD-32
2
1
~:cSuggested
5-6
number of spares (if PAC is used in customers system)
MAINTENANCE INSPECTION
Conduct a visual inspection periodically.
In conducting this inspec-
tion, watch specifically for accumulations of dust and dirt, improperly seated
PACs, and damaged or improperly dressed cable and signal leads.
see that
5-4
a~l
connectors are securely mated.
Check to
"
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'1L.J
MAGNETIC CORE MEMORY SYSTEM
5-7
PREVENTIVE MAINTENANCE PROCEDURE
a.
The TCM- 32 system is extensively tested at Computer Control
Company, Inc. prior to shipment.
All planes are tested simultaneously under
all ZEROs, all ONEs, and worst pattern conditions.
The inhibit and drive
line currents are set so that optimum operating margins result.
The mem-
ory should be tested periodically as a preventive maintenance procedure using
a memory test program or an optionally supplied Computer Control Company
memory exerciser.
b.
Voltage Adjustments.
tory preset to their nominal values.
The three power supply voltages are facA screwdriver adjustment of ± 2% is
provided if recalibration is necessary.
The power supply should be mounted
physically near the TCM- 32 system to minimize voltage drops and noise due
to long lead lengths.
c.
Drive
Current Adjustments.
The drive current amplitudes are
adjusted by means of the four potentiometers.
The adjustment procedure is
as follows.
(1)
Turn off the DC power and remove the Dynamic Current
Driver PAC, Model MD-32
(2)
Put the MD- 32 PAC on a special extender PAC.
brated AC current probe around the pin 1 7 lead.
Clip a cali-
Turn on the DC power and
adjust the current to 210 rna using the associated potentiometer (connected to
pin 16 of the MD-32 PAC).
I
\
l-<
l
(3)
Clip the current probe around pin 19 of the MD-32 PAC and
adjust the current pulse amplitude to 210 rna.
I
\.-1
(4) Repeat steps 1 through 3 for the other MD- 32 PAC.
(5)
I
I
I
The current amplitude of 210 rna is the nominal drive cur-
rent at 25°C which gives best operating margins, unless noted elsewhere.
l~-,
This current can vary typically ± 10% under most pattern testing without error.
'I
I
l~
r-'I
I
.J
l
L.J
The current is temperature compensated by a Thermistor- Zener diode network on the MD-32 PAC.
The current varies nominally -0. 50/0rC to match
the temperature characteristics of the magnetic cores used.
(6)
The drive line current amplitude is nominally 40 rna higher
than the current out of the MD-32 PAC due to the base current of the emitterfollower circuit on the Selection Switch PAC (Model SS-32).
The drive line
l
.-1
5-5
MAGNETIC CORE MEMORY SYSTEM
'"I
current amplitude observed by a current probe at the output of the Selection
Switch PAC is thus nominally 250 rna.
d.
Inhibit Current Adjustment.
The inhibit current is determined
by the -18-volt supply and two precision resistors and does not require amplitude adjustment.
The value of the inhibit current is nominally 210 rna, and
may be varied typically ± 150/0 under worst-pattern testing without causing errors.
The amplitude may be checked by putting the MI-32 PAC on a special
extender card and attaching a calibrated current probe to the appropriate output lead.
e.
Strobe Adjustment.
The most critical adjustment in a core mem-
ory is the timing of the sense amplifier strobe.
Strobe is that signal which
samples the sense winding voltage in order to discriminate between noise and
signal.
If strobe occurs too early, relative to the sense winding signal, it
may give erroneous sense amplifier outputs as a result of sampling ZERO
noise.
If strobe is too late, it may attempt to sample the proper ONE signal
after the signal amplitude has decreased to a value too low.
With reference to Figure 5-1, the upper trace shows proper strobe
timing, and the lower trace shows a strobe timing too late.
Proper strobe
timing is such that the strobe-enabled signal occurs superimposed upon a
pedestal which is due to the amplified core signal.
If there is no pedestal
ahead of the strobe pulse, strobe is too early.
CORRECT
TOO
I
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--.l.--------!--_
I
'_
~!_""~'_
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Figure 5-1.
5-6
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Strobe Adjustment Waveform
LATE
1
I...-J
MAGNETIC CORE MEMORY SYSTEM
J
This waveform is observed at TPI test point of any BR- 32 which
is sensing a ONE signal; this test point is the outermost one on the BR-32 adjacent to the handle, and may be probed with a Tektronix scope probe without
IL..J
removing the PAC.
Rarely should it be necessary to adjust strobe timing; an apparent
shift in timing may be due to a maladjusted drive current in the memory.
If
it becomes necessary to change the strobe timing, this is done on the TD-32
board by moving jumpers.
Refer to the TD-32 PAC write-up for this opera-
tion.
5-8
CORRECTIVE MAINTENANCE PROCEDURE
Corrective maintenance procedures consist of electrical and mechan-
ical inspection, power supply troubleshooting procedures, and memory system troubleshooting procedures.
a.
Corrective Maintenance Inspection.
Before beginning trouble-
shooting procedures, a thorough inspection of the system should be performed.
Check to see that the system is not physically damaged and that no wires have
been torn accidentally from the equipment.
and PACs fit firmly in their sockets.
1
.J
I
Make sure electrical connector s
b.
Power Supply Troubleshooting Procedures.
and DC power-on are provided on the power supply.
I
...J
Lamps indicating AC
The DC outputs are pro-
tected by fast acting circuit breaker s, and an indicator is provided to indicate
DC power failure.
c.
Memory Troubleshooting Procedures.
Memory troubleshooting
consists of determining the type of faulty memory operation, predicting the
fl
type of PAC at fault, and locating the particular faulty circuit.
Test proce-
I
I
•
~·t
dures to aid in troubleshooting are listed below .
(1)
''--.J
The normal waveforms at various test points and PAC con-
nector pins are shown in Figure 5-2.
A time scale of O. 5 ~sec/cm is used
throughout with 5 V / cm for voltages and O. 2 amp/ cm for currents.
An ex-
tender PAC should be used when checking the operating voltage and current
waveforms at the PAC connectors.
Oscilloscope probes should be used care-
fully because shorting of connector terminals or test points may damage the
PAC.
5-7
MAGNETIC CORE MEMORY SYSTEM
'I
RR/CW
1-20-34
SA
1-18-24
-6V
RI-I
1-18-11
,--,
-6V
STI
1-18 -8
'--'
I"'
OV
RR/CW
1- 20-34
OV
RE
4-7-10
4 .........._
. .-
-6V
RS
4-7-30
OA*
IRY
2-4-17
OV
RR/CW
1- 20-34
OV
WE (lS)
4-5-10
;_-r-6V
OA
*'
WS
4-5-30
IWY
2-5-H
*":
Figure 5- 2.
5-8
200MA/CM
Waveforms (Sheet 1 of 3)
Figure 5-2.
Waveforms (Sheet 2 of 3)
,.J
5-9
MAGNETIC CORE MEMORY SYSTEM
.....
II
II ,-
I-
'
....
lj....
II ' II
I
!.~ II
II..
..
-
~
-
II
I!!!!!!!!
:
IiI
II
II
!I.
•
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..
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~r,
II
RR/CW
1-20-34
OV
IR -I
1- 1-12
iii
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,
ov
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--
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BR-32
~
~..,.. i!l
~
~==,:;;;;:;,~~:~~!!::=:==;;;;~i=-7V
** TEST POINT TPI
~
~
~
II
I:
'4
I:
~
II I
OV
;;;;,;;
""""--
**=
DI-I
1- 18 -27
IV/CM
RR/CW
1-20-34
RPY
2-13-7
001
2-13-13
55-32
TEST POI NT TPI
* :; 20V/CM
Figure 5-2.
5-10
Waveforms (Sheet 3 of 3)
f-'
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J
J
MAGNETIC CORE MEMORY SYSTEM
(2) Spare PACs may be used to isolate faulty circuits, in some
cases, by interchanging identical PACs and noting any shift in the faulty bits
or addresses.
(3)
Refer to the PAC schematic and assembly drawings in Section
6 to isolate and replace the defective components on the printed circuit card.
(4)
Memory failures are generally of the following types:
opera-
tion failures, which are caused by faulty timing and control circuits; partial
information word failures, which are caused by faulty bit register circuits
(sense amplifier and information register flip-flop); and address failures
which are caused by faulty address register decoding or selection circuits.
(5)
1
L•• j
Memory failures may be localized by the following procedure.
(a)
Load the test pattern into the memory.
(b)
Initiate a read operation at each address sequentially and
check each readout information word.
(c)
Check the readout information words for the following
failures.
1.
rr
Operation failures.
No apparent response to com-
mands applied to the memory, or faulty operation at
\
', .• J
all addresses (see Table 5-3).
f""J
2.
,J
Partial information word failures.
Failures of one
bit or a series of two or more adjacent bits at all addresses (see Table 5-4).
3.
Address failures.
ticular
'I
Faulty memory operation at par-
addres ses only (see Table 5- 5).
I
' ..J
5-9
l
• .-J
MAGNETIC CORE MA TRIX MAINTENANCE
Troubles occuring within the magnetic core matrices are unlikely
under normal operating conditions.
However, continuity measurements of the
inhibit, sense, and drive windings will enable maintenance personnel to check
the wiring of the core stack. The stack measurements should be done carefully
'""1
to avoid damaging the matrix windings.
a.
rr
Inhibit Windings (Table 5-6)
(1)
Turn off memory power.
Remove the MI-32 Inhibit Driver
PAC as sociated with the inhibit winding to be checked.
5-11
---..'
MAGNETIC CORE MEMOR Y SYSTEM
TABLE 5-3.
OPERATION FAILURES
Trouble
Probable Cause
Remedy
Check
Waveforms
(At pin indicated)
No apparent response
to memory commands
(or faulty operation)
at all addresses
Readout information
is all ZEROs or all
ONEs at all addresses
(2)
Faulty input circuit
1-19, 1-22, 1-23
1-20
Faulty Timing DistriPAC
bu~or
Faulty read, write gates
4-5, 4-7
Faulty Gate Driver PAC
2-3-16, IS, 31,32
Faulty Dynamic Current
Driver PAC
2-3-17, 19
2-4-17, 19
Faulty inhibit step
4-5-10
Faulty Gate Driver PAC
2-3-16, IS, 31, 32
Faulty Dynamic Current
Driver PAC
2-3-17, 19
2-4-17, 19
Faulty Strobe Amplifier
PAC
1-1S-S (1-16 bits)
1 -1 7 - S (1 7 - 3 2 bits)
1-17-11 (33-4Sbits)
Place one ohmmeter lead on -IS-volt output (pin 2 of the
S-BLOC or at the inhibit component board).
,(3) Place the other ohmmeter lead on the output connector pin
of the inhibit driver channel in question, as shown on the logic block diagram.
For example, to check the bit 4 inhibit winding, place the ohmmeter leads on
connector pin 31 of the MI-32 connector.
(4)
The inhibit winding resistance is a function of the word length.
It will vary from O. 5 to 15 ohms for 12S to 4096 word memories.
The resis-
tance from the inhibit driver connector pin to the -IS-volt supply includes the
resistors on the inhibit component board.
The total resistance, including the
inhibit resistors and the inhibit line resistance, should read between 70 and
100 ohms, with a typical value of S3 ohms.
bits should agree within ± lO%.
5-12
The resistance readings of all
J
MAGNETIC CORE MEMORY SYSTEM
b.
J
(1)
l ;
l.J
(Refer to Table 5-8 for intra-unit
place the ohmmeter leads on connector pins 32 and 33 of the BR- 32 connector
in location 1- 2.
(3) Resistance readings should be between 1 and 20 ohms for
memory planes of 128 to 4096 words.
The resistance readings for all.bits
should agree within ± 10%.
I
,-1
c.
I
J
Drive Windings
(1)
'/
I ...
Place the ohmmeter leads across the s.ense wire input termi-
For example, to check the continuity of the bit 4 sense winding,
'r
l.J
Remove the BR-32 Bit Register
nations at the Bit Register PAC connector.
wiring.)
'I
Turn off memory power.
PAC associated with the sense winding to be checked.
(2)
l
l
Sense Windings (Table 5-7)
Turn off memory power.
Remove the Selection Switch PAC,
. Model SS-32, from the PAC connectors associated with the X or Y drive line
to be checked.
(2)
Place one ohmmeter probe on the appropriate single drive
line output of the Selection Switch PAC.
(3)
Place the other ohmmeter probe on the other end of the drive
line, at the appropriate bussed drive line output of the selction PAC.
For
example, to check continuity of the X5 drive line in a 2048 or 4096 word memory, place the ohmmeter leads on pins 2-10-17 and 2-11- 35.
(4)
I
I.J
Drive line resistance is a function of memory size (length
of word and number of bits).
Readings will vary from 1 ohm for small mem-
ories to approximately 15 ohms for large memories up to 4096/48.
resistance readings in a given coordinate should agree within ± 10%.
All the
The
drive line resistance for the X- and Y - coordinates should agree within ± 10%
for square matrices (i. e., 64 x 64) but will be different for non- square
planes (i. e., 32 x 64).
d.
'c ..
J
X- Windings (See Table 5-9)
(1)
Place the ohmmeter leads at the appropriate SS-32 selection
switch output indicated in the X-winding checklist.
.... j
(2) A normal reading is approximately 2 to 12 ohms.
All read-
ings should agree within ±10%.
'I
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5-13
... J
MAGNETIC CORE MEMORY SYSTEM
e.
Y - Windings (See Table 5-10)
(1)
Place the ohmmeter leads at the appropriate SS-32 selection
switch output indicated in the Y -winding checklist.
(2) A normal reading is approximately 2 to 12 ohms.
All read-
ings should agree within ± 100/0.
5-10
LOGIC CIR CUlT MAINTENANCE
Replacing malfunctioning packages is the quickest procedure for logic
circuit maintenance and is highly recommended. Troubleshooting to the package
level is best accomplished with a thorough understanding of the Principles of
Operation, Section III.
Some aids for troubleshooting the logic cir cuits are
listed below.
Aid
Location
(a) System Block Diagram
Section III
(b)
Logic Diagrams
Section IV
(c)
Timing Diagram
Section III
(d) Maintenance
Section V
(e)
Circuit Schematics
Appendix A
(f)
Special PAC Information
Appendix
(g) Instruction Manual, S-PAC
Digital Modules
Supplementary
Publication
Suspected faulty packages can be repaired by referring to the appropriate PAC circuit description, schematic diagram, and assembly drawing,
isolating the faulty component or components, and repairing the PAC by making
replacements with the recommended parts.
5-11
DC POWER DISTRIBUTION
The memory power supply receives AC power and supplies the
following DC system power, distributed as indicated below.
-18 V:
To all PACs, to inhibit component boards.
-6 V: To all PACs.
+12 V:
5-14
To all PACs.
"
J
MAGNETIC CORE MEMORY SYSTEM
l
TABLE 5-4.
PARTIAL INFORMATION WORD FAILURES
LJ
J
Trouble
Remedy
Probable Cause
Check
Waveforms
(At pin indicated)
1
l_~
Failure of one bit
(ZERO or ONE) at all
addresses
J
J
1
One bit is a ZERO
at all addresses
Faulty Bit Register
PAC stage
See Logic Diagram
(Figures 4-5,4-6,
4-7) for Pin Nutnber
(Function of wo rd
length)
Faulty Inhibit Driver
PAC channel
2 -1
2-2
4-1
4-2
4-3
4-4
Faulty Bit Register
PAC stage
See Logic Diagratn
(Figures 4-5, 4-6,
4-7) for Pin Nutnber
(Function of word
length)
Shorted sense winding
(See Table 4-7)
Faulty Inhibit Driver
PAC channel
2-1
2-2
4-1
4-2
4-3
4-4
Open inhibit winding
(See Table 4-6)
l~
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One bit is a ONE at
all addresses
I
(1-8 bits)
(9-16 bits)
(17-24 bits)
(25-32 bits)
(33-40 bits)
(41-48 bits)
Sho rted inhi bi t winding
Faulty inhibit Driver
PAC channel
2-1
2-2
4-1
4-2
4-3
4-4
Faulty Bit Register
PAC stage
See Logic Diagram
(Figures 4-5,4-6,
4-7) for Pin Number
(Function of wo rd
length)
Open sense winding
(See- Table 4-7)
LJ
1'/
(1 - 8 bits)
(9 - 16 bi t s )
(17-24 bits)
(25 -32 bits)
(33-40 bits)
(41-48 bits)
(1-8 bits)
(9-16 bits)
(17-24 bits)
(25-32 bits)
(33-40 bits)
(41-48 bits)
"
l..J
5-15
MAGNETIC CORE MEMORY SYSTEM
,'"I
TABLE 5-4. (Cont)
PARTIAL INFORMATION WORD FAILURES
Trouble
Probable Cause
Remedy
Check
Waveforms
(At pin indicated)
Failure of eight
adjacent bits (ZERO or
ONE) at all addresses
Faulty timing amplifier
on Inhibit Driver PAC
2-1
2-2
4-1
4-2
4-3
4-4
Failure of up to 16
adjacent bits (ZERO
or ONE) at all
addresses
Faulty information
Register drop-in
power circuit
1-18-27 (1-16 bits)
1 - 1 7 - 24 (1 7 - 32 bi t s )
1-17 -27 (33-48 bits)
r--',
(1-8 bits)
(9-16 bits)
(17-24 bits)
(25-32 bits)
(33-40 bits)
(41-48 bits)
11
,-'
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5-16
J
J
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MAGNETIC CORE MEMORY SYSTEM
TABLE 5-5.
ADDRESS, DECODING, AND SELECTION FAILURES
Trouble
Probable Cause
Check
Waveforms
(A t pin indicated)
J
J
J
l
Remedy
Faulty operation at 1/2
of memory capacity;
normal drive voltag e
and current waveforms
Faulty address register
flip -flop circuit
See Logic Diagram
(Figures 4-2, 4-3)
for Pin Number
(Function of word
capacity)
Faulty operation at
particular addresses;
incorrect drive voltage and/or current
waveforms
Faulty Selection Switch
PAC channel
See Logic Diagram
(Figure 4-4) for Pin
Number (Function of
word capacity)
Read (or write) drive
current missing in
either the X - or Ycoordinate for all
addresses
Bad channel on Gate
Driver PAC
2-3-16, 18, 31, 32
Bad channel on Dynamic
Current Driver PAC
2-3-17, 19
2-4-17, 19
Faulty read or write
gates (No signal inputs
to Gate Driver PAC or
Dynamic Current Driver
PAC)
4-5-30, 4-7-30
N 0 drive current flow
during read (or write)
operation at particular
addresses
Open current steering
diode on Selection
Switch PAC
See Logic Diagram
(Figure 4-4) for Pin
Number (Function of
word capacity)
No drive current flow
in either direction
(read and write) at a
number of addresses
equal to the number of
X - or Y -drive lines
Open drive line
(See Tables 4-9,
4-10)
Faulty addres s decoder
4-5 through 4-8
Defective Dynamic
Current Driver PAC
2-3 and 2-4
Shorted current steering
diode or transistor on
Selection Switch PAC
See Logic Diagram
(Figure 4-4) for Pin
Number (Function of
word capacity)
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Reduced drive current
amplitude in one or
both directions
l.J
1
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5-17
MAGNETIC CORE MEMORY SYSTEM
TABLE 5-6.
INHIBIT WINDING CHECKLIST
(Resistance measured between PAC
terminal and -18 -volt inhibit)
Memory Signal
5-18
Memory
Memory Signal
Memory
Z-1
2-1-28
Z-25
4-2-28
Z-2
2-1-29
Z-26
4-2-29
Z-3
2-1-30
Z-27
4-2-30
Z-4
2-1-31
Z-28
4-2-31
Z-5
2-1-32
Z-29
4-2-32
z-6
2-1-33
Z-30
4-2-33
Z-7
2-1-34
Z-31
4-2-34
Z-8
2-1-35
Z-32
4-2-35
Z-9
2-2-28
Z-33
4-3-28
Z-10
2-2-29
Z-34
4-3-29
Z-11
2-2-30
Z-35
4-3-30
Z-12
2-2-31
Z-36
4-3-31
Z-13
2-2-32
Z-37
4-3-32
Z-14
2-2-33
Z-38
4-3-33
Z-15
2-2-34
Z-39
4-3-34
Z-16
2-2-35
Z-40
4-3-35
Z-17
4-1-28
Z-41
4-4-28
Z-18
4-1-29
Z-42
4-4-29
Z-19
4-1-30
Z-43
4-4-30
Z-20
4-1-31
Z-44
4-4-31
Z-21
4-1-32
Z-45
4-4-32
Z-22
4-1-33
Z-46
4-4-33
Z-23
4-1-34
Z-47
4-4-34
Z-24
4-1-35
Z-48
4-4-35
11
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J
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MAGNETIC CORE MEMORY SYSTEM
TABLE 5-7.
SENSE WINDING CHECKLIST
(Resistance measured across terminals A and B;
BR-32 PACs must be removed)
Memory Signal
Memory
Test Point
Memory Signal
Memory
Test Point
SW-1
1-1-7
SW-13
1-7-7
SW-l.
1-1-8
SW -13
1-7 -8
SW-2
1-1-32
SW-14
1-7 -32
SW-2
1-1-33
SW-14
1-7-33
SW-3
1-2-7
SW -15
1-8-7
SW-3
1-2-8
SW -15
1-8-8
SW-4
1-2-32
SW-16
1-8-32
sw-4
1-2-33
SW-16
1-8-33
SW-5
1-3-7
SW -17
1-9-7
SW-5
1-3-8
SW -17
1-9-8
SW-6
1-3-32
SW-18
1-9-32
sW-6
1-3-33
SW -18
1-9-33
SW-7
1-4-7
SW -19
1-10-7
SW-7
1-4-8
SW-19
1-10-8
SW-8
1-4-32
SW-20
1-10-32
SW-8
1-4.-33
SW-20
1-10-33
SW-9
1-5-7
SW-21
1-11-7
SW-9
1-5-8
SW-21
1-11-8
J
SW-10
1-5-32
SW-22
1-11-32
SW-I0
1-5-33
SW-22
1-11-33
J
SW -11
1-6-7
SW-23
1-12-7
SW -11
1-6-8
SW-23
1-12-8
SW-12
1-6-32
SW-24
1-12-32
SW-IZ
1-6-33
SW-24
1-12-33
J
J
J
J
J
1
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5-19
MAGNETIC CORE MEMORY SYSTEM
n
TABLE 5 -7. (Cont)
SENSE WINDING CHECKLIST·
(Resistance Ineasured across terIninals A and Bj
BR- 32 PAC s Inust be reInoved)
MeInory Signal
MeInory
Test Point
MeInory Signal
MeInory
Test Point
SW-25
1-13-7
SW-37
3-5-7
SW-25
1-13-8
SW-37
3-5-8
SW-26
1-13-32
SW-38
3-5-32
sW-26
1-13-33
SW-38
3-5-33
SW-27
1-14-7
SW-39
3-6-7
SW-27
1-14-8
SW-39
3-6-8
SW-28
1-14-32
SW-40
3-6-32
SW-28
1-14-33
sw-40
3-6-33
SW-29
3-1-7
SW-41
3-7 -7
SW-29
3-1-8
SW-41
3-7 -8
SW-30
3-1-32
SW-42
3-7-32
SW-30
3-1-33
SW-42
3-7 -33
SW-31
3-2-7
SW-43
3-8-7
SW-31
3-2-8
SW-43
3-8-8
SW-32
3-2-32
SW-44
3-8-32
SW-32
3-2-33
SW-44
3-8-33
SW-33
3-3-7
SW-45
3-9-7
SW-33
3-3-8
SW -45
3-9-8
SW-34
3-3-32
SW-46
3-9-32
SW-34
3-3-33
SW-46
3-9-33
SW-35
3-4-7
SW-47
3-10-7
SW-35
3-4-8
SW-47
3-10-8
SW-36
3-4-32
SW-48
3-10-32
SW-36
3-4-33
SW-48
3-10-33
n
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5-20
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MAGNETIC CORE MEMORY SYSTEM
J
TABLE 5-8.
INTRA-UNIT WIRING CONNECTOR J-110
Designation
Pin
Number
Designation
1
SW-l
26
SW -13
2
SW-l
27
SW -13
3
SW-2
28
SW-14
4
SW-2
29
SW-14
5
SW-3
30
SW -15
6
SW-3
31
SW -15
7
SW-4
32
SW -16
8
SW-4
33
SW -16
9
SW-5
34
SW-17
10
SW-5
35
SW -17
11
SW-6
36
SW-18
12
sW-6
37
SW -18
13
SW-7
38
SW -19
14
SW-7
39
SW-19
15
SW-8
40
SW-20
16
SW-8
41
SW-20
42
SW -21
Pin
Number
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17
,...,
18
SW-9
43
SW -21
19
SW-9
44
SW-22
20
SW-I0
45
SW-22
21
SW-I0
46
SW-23
22
SW -11
47
SW-23
23
SW -11
48
SW-24
24
SW-12
49
SW.;.24
25
SW-12
50
I
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I
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5-21
MAGNETIC CORE MEMORY SYSTEM
TABLE 5-8. (Cant)
INTRA-UNIT WIRING CONNECTOR J-111
Pin
Number
Designation
Pin
Number
Designation
1
AR-1
26
Twisted Pair CL
2
AR-l
27
Gnd
3
AR-2
28
Twisted Pair Unload Counter
4
AR-2
29
Gnd
5
AR-3
30
Half Cycle
6
AR-3
31
RAN
7
AR-4
32
ER
8
AR-4
33
RMW
9
AR-5
34
SA
10
AR-5
35
SR
11
AR-6
36
SA 2
12
AR-6
37
SA3
13
AR-7
38
14
AR-7
39
LCT
15
AR-8
40
IA
16
AR-8
41
EE
42
EC
17
18
AR-9
43
MBS
19
AR-9
44
SB
20
AR-10
45
RS
21
AR-10
46
ER
22
AR-11
47
SZ
23
AR-11
48
WS
24
AR-12
49
EZ
25
AR-12
50
EB
r-
or-'
r-,
5-22
J
J
J
MAGNETIC CORE MEMORY SYSTEM
TABLE 5-8. (Cant)
INTRA-UNIT WIRING CONNECTOR J-112
Pin
Nutnber
Designation
Pin
Number
Designation
1
IR-l
26
IR-26
2
IR-2
27
IR-27
3
IR-3
28
IR-28
4
IR-4
29
IR-29
5
IR-5
30
IR-30
6
IR-6
31
IR-31
7
IR-7
32
IR-32
8
IR-8
33
IR-33
9
IR-9
34
IR-34
10
IR-I0
35
IR-35
11
IR-ll
36
IR-36
12
IR-12
37
IR-37
13
IR-13
38
IR-38
J
14
IR-14
39
IR-39
15
IR-15
40
IR-40
J
16
IR-16
41
IR-41
17
IR-17
42
IR-42
18
IR-18
43
IR-43
19
IR-19
44
IR-44
20
IR-20
45
IR-45
21
IR-21
46
IR-46
22
IR-22
47
IR-47
23
IR-23
48
IR-48
24
IR-24
49
25
IR-25
50
J
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5-23
MAGNETIC CORE MEMORY SYSTEM
r,
TABLE 5-8. (Cant)
INTRA-UNIT WIRING CONNECTOR J-113
("I
Pin
Number
-...
"
-
De signa tion
Designation
1
SW-25
26
SW-37
2
SW-25
27
SW-37
3
SW-26
28
SW-38
4
SW-26
29
SW-38
5
SW-27
30
SW-39
6
SW-27
31
SW-39
7
SW-28
32
SW-40
8
SW-28
33
SW-40
9
SW-29
34
SW-41
10
SW-29
35
SW-41
11
SW-30
36
SW-42
12
SW-30
37
SW-42
13
SW-31
38
SW-43
14
SW-31
39
SW-43
15
SW-32
40
SW-44
16
SW-32
41
SW-44
42
SW-45
17
5-24
Pin
Number
18
SW-33
43
SW-45
19
SW-33
44
SW-46
20
SW-34
45
SW-46
21
SW-34
46
SW-47
22
SW-35
47
SW-47
23
SW-35
48
SW-48
24
SW-36
49
SW-48
25
SW-36
50
'~1
J
MAGNETIC CORE MEMORY SYSTEM
TABLE 5-9.
X-WINDING CHECKLIST
Xk
Drive
Line
Xk'
2-11-33
2-11-20
32
2-7-33
1
2 -11- 3.5
2-11 .. 21
33
2-7 -35
2-11-24
2
2-11-33
2-11-28
34
2-7-33
2-11-25
3
2-11-35
2-11-29
35
2-7-35
rr,
2-10-16
4
2-11-33
2-10-20
36
2-7-33
lJ
2-10-17
5
2-11-35
2-10-21
37
2-7-35
2-10-24
6
2-11-33
2-10-28
38
2-7-33
2-10-25
7
2-11-35
2-10-29
39
2~7-35
2-11-18
8
2-10-33
2.-11-22
40
2-6-33
2-11-19
9
2-10-35
2-11-23
41
2-6-35
2-11-26
10
2-10-33
2-11-30
42
2-6-33
2-11-27
11
2-10-35
2-11-31
43
2-6-35
2-10-18
12
2-10-33
2-10-22
44
2-6-33
2-10-19
13
2-10-35
2-10-23
45
2-6-35
2-10-26
14
2-10-33
2-10-30
46
2-6-33
2-10-27
15
2-10-35
2-10-31
47
2-6-35
2-7-16
16
2'-11-33
2-7-20
48
2-7-33
2-7-17
17
2-11-35
2-7-21
49
2-7-35
2-7-24
18
2-11-33
2-7-28
50
2-7-33
2-7-25
19
2-11-35
2-7-29
51
2-7-35
2-6-16
20
2-11-33
2-6-20
52
2-7-33
2-6-17
21
2-11-35
2-6-21
53
2-7-35
2-6-24
22
2-11-33
2-6-28
54
2-7-33
2-6-25
23
2-11-35
2-6-29
55
2-7-35
2-7-18
24
2-10-33
2-7-22
56
2-6-33
2-7-19
25
2-10-35
2-7-23
57
2-6-35
2-7-26
26
2-10-33
2-7-30
58
2-6-33
2-7-27
27
2-10-35
2-7-31
59
2-6-35
2-6-18
28
2-10-33
2-6-22
60
2-6-33
2-6-19
29
2-10-35
2-6-23
61
2-6-35
2-6-26
30
2-10-33
2-6-30
62
2-6-33
2-6-27
31
2-10-35
2-6-31
63
2-6-35
J
LJ
TI
Xk
Drive
Line
2-11-16
0
2-11-17
Xk
I
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5-25
MAGNETIC CORE MEMORY SYSTEM
TABLE 5-10.
Y-WINDING CHECKLIST
,--',
Yk
Drive
Line
Yk
Yk
Drive
Line
Yk
2-13-16
0
2-13-33
2-13-20
32
2-9-33
2-13-17
1
2-13-35
2-13-21
33
2-9-35
2-13-24
2
2-13-33
2-13-28
34
2-9-33
2-13-25
3
2-13-35
2-13-29
35
2-9-35
2-12-16
4
2-13-33
2-12-20
36
2-9-33
2-12-17
5
2-13-35
2-12-21
37
2-9-35
2-12-24
6
2-13-33
2-12-28
38
2-9-33
2-12-25
7
2-13-35
2-12-29
39
2-9-35
2-13-18
8
2-12-33
2-13-22
40
2"';8-33
2-13-19
9
2-12-35
2-13-23
41
2-8-35
2-13-26
10
2-12-33
2-13-30
42
2-8-33
2-13-27
11
2-12-35
2-13-31
43
2-8-35
2-12-18
12
2-12-33
2-12-22
2-8-33
2-12-19
13
2-12-35
2-12-23
44
45 .
2-8-35
2-12-26
14
2-12-33
2-12-30
46
2-8-33
2-12-27
15
2-12-35
2-12-31
47
2-8-35
2-9-16
1'6
2-13-33
2-9-20
48
2-9-33
2-9-17
17
2-13-35
2-9-21
49
2-9-35
2-9-24
18
2-13-33
2-9-28
50
2-9-33
2-9-25
19
2-13-35
2-9-29
51
2-9-35
2-8-16
20
2-13-33
2-8-20
52
2-9-33
2-8-17
21
2-13-35
2-8-21
53
2-9-35
2-8-24
22
2-13-33
2-8-28
54
2-9-33
2-8-25
23
2-13-35
2-8-29
55
2-9-35
2-9-18
24
2-12-33
2-9~22
56
2-8-33
2-9-19
25
2-12-35
2-9-23
57
2-8-35
2-9-26
26
2-12-33
2-9-30
58
2-8-33
2-9-27
27
2-.12-35
2-9-31
59
2-8-35
2-8-18
28
2-12-33
2-8-22
60
2-8-33
2-8-19
29
2-12-35
2-8-23
61
2-8-35
2-8-26'
30
2-12-33
2~8-30
62
2-8-33
2-8-27
31
2-12-35
2-8-31
63
2-8-35
5-26
r~1
J
MAGNETIC CORE MEMORY SYSTEM
J
'1
SECTION VI
PAC COMPLEMENT LIST
I
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6-1
1
u
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J
GENERAL
This section contains a Magnetic Core Memory System PAC com-
plement list (Table 6 -1).
Parts lists for special S-PACs (p/o units 1 and 2) used in this system are contained in the appendix of this manual.
The parts lists for all
standard S -PAC modules are contained in the Instruction Manual for 1 MC
Series S-PAC Digital Modules.
1
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6-1
MAGNETIC CORE MEMORY SYSTEM'
TABLE 6-1.
PAC COMPLEMENT LIST
Temporary
Designation
Designation
..Description
Quantity
STANDARD PACS
TCM-32 Assembly
1
DL-30
NAND PAC
2
DC-30
Diode PAC
1
;.
"
MF-30
Flip-Flop PAC
7
PN-30
Non-Inverting Power Amplifier
PAC
4
NON -STANDARD PACS
S-086
BR-32
Bit Register PAC
24
o'
S-117
DP-32
Address Decoder PAC
4
S-091
GD-32
Gate Driver PAC
1
S-083
MD-32
Dynamic Current Driver PAC
2
S-087
MI-32
Inhibit Driver PAC
6
S-026
S8-32
Selection Switch PAC
8
S-219
TD-32
Timing Distributor PAC
2
S-103
Memory Clear Driver PAC
2
S-169
Transfer Gate PAC
5
S-179
Parallel Transfer Gate PAC
1
,_.',
r-~
r'
,-
6-2
J
MAGNETIC CORE MEMORY SYSTEM
J
J
APPENDIX
n
U
The appendix to this manual contains circuit descriptions, schematic
I
diagrams, and as sembly drawings for the following digital modules and component boards used in the Magnetic Core Memory System.
These modules are
not covered in the Instruction Manual for S-PAC Digital Modules.
They are
arranged in this appendix in the following order.
J
Bit Register PAC, model BR-32
Address Decoder PAC, model DP-32
J
n
J
Gate Driver PAC, model GD- 32
Dynamic Current Driver PAC, model MD-32
Inhibit Driver PAC, model MI-32
Selection Switch PAC, model SS-32
Timing Distributor PAC, model S-219
=1
J
J
Inhibit Component Board
Memory Normalizer Board
Memory Clear Driver PAC, m.odel S-103
Transfer Gate PAC, model S -169
Parallel Transfer Gate PAC, model S-179
J
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1
u
c
A-I
BIT REGISTER PAC, MODEL BR-32
J
GENERAL DESCRIPTION
The Bit Register PAC, Model BR-32 (Figures 1 and 2), contains
two sense amplifier s with as sociated information register flip-flops.
The
sense amplifiers provide amplitude discrimination, time discrimination, and
a high ratio of common-rIlode noise rejection.
J
signal appearing on the sense line.
The circuit amplifies the core
The amplified core signal is time- strobed
to provide a digital form of output that sets a standard flip-flop circuit. Inputs
to the information register flip-flops are provided for writing external information into the memory.
]
CIRCUIT DESCRIPTION
Transistors Ql and Q2 (Figure 3) are on and their emitters are at approximately 0 volt, without a sense signal applied.
The collector s of Ql and
Q2 are at a +6-volt potential and tra.nsistors Q3' and Q4 are off.
The collectors
of Q3 and Q4 are clamped at - 6. 3 volts by,the strobe input and resistor network R ll-R13.
J
Transistor Q5 is reverse-biased, and its collector is clamped
to +0. 3 volt by resistor R 16 and diode CR4'.
with its collector clamped at -6.3 volts.
Transistor Q6 is normally off,
The flip-flop is reset at the beginning
of the memory cycle that places Q7 on and Q8 off.
The sense inputs are connected directly to the base of input transistors
Ql and Q2.
]
Resistors RI and R12 terminate the sense winding. Resistors R3,
R6, and potentiometer R 5 provide AC stabilization for the differential amplifier
(Ql and Q2).
Resistor R8 is a DC stabilizing resistor, ahd,resistors R4 andR7
increase the resolution of potentiometer R5.
Common-mode noise is cancelled
by the high impedance of resistor R8 and no differential signal appears at the
collectors of Ql and Q2.
Transistor s Q3 and Q4 remain off, giving the sense
amplifier a high common-mode noise rejection ratio.
During the read cycle a ONE a.ppear s on the sense input.
When the base
of Ql goes positive, its conduction increases and its collector voltage goes negative.
1
LJ
The negative pulse on the base of Q2 causes its collector to go positive.
The pulse clamps to the Ql collector voltage through the emitter- base junction
of Q3.
J
The potentiometer adjusts the DC gain and balance of transistors Ql and
Q2.
Diodes CRI and CR2 form an AND gate for positive signals.
When the
strobe input goes to 0 volt, and the collector of Q3- 04 goes sufficiently positive
r;
I
U
1
(due to the amplified ONE input signal), the strobe .clamps the collector of
Ql or Q2 to ground.
Resistor RIO prevents the differential stage (Ql or Q2)
from saturating during a large digit transient and allows the base of Q5 to
become positive with respect to the emitter.
The positive pulse at the collec-
tor of Q6 sets the flip-flop that turns off Q7 and saturates Q8.
The flip-flop
therefore registers a binary ONE which corresponds to the state of the selected memory core.
A ZERO output does not have sufficient amplitude at strobe time to
saturate transistor Q5.
OFF state.
Resistor divider network RII-R13 holds Q5 in: the
The flip-flop will not receive a set input so it remains in the
zero state (since it was reset at the start of the cycle).
NOTE
For all applications of the BR- 32 , pin 35 should be
jumper ed to pin 5 (gr ound). The jumper attenuate s
noise picked up by distributed impedance of the etched
circuit.
SPECIFICA TIONS
Frequency of Operation
The maximum frequency of operation of the sense amplifier is 500 KC.
Frequency of operation of the flip-flop is DC to 1 MC (max).
Input
The minimum ONE input signal required is 50 MV (25 MV to each
base of the differential amplifier), while the maximum ZERO input
signal is 15 MV.
The strobe input is a - 6-volts to O-volt pulse with a nominal width of
O. 20 ~sec. The load on the strobe driver is O. 5 rna per channel (1 rna
per PAC) with the input at - 6 volts, and 0 rna with the strobe at 0 volt.
The inputs to the flip-flop portion of the circuit include AC set and reset inputs, set and reset node inputs, a common reset input, and AC
set inputs from the strobed sense amplifiers. Load and signal requirements are the same as for the FA-30 S-PAC.
Output
The outputs are flip-flop set and reset outputs.
istics are the same as for the FA-30 S-PAC.
The output character-
Cir cuit Delay
The analog signal delay between sense input and. monitor point (at the
collectors of Q3 and Q4) is O. 20 to O. 30 ~sec. The turn- on delay between the strobe input and sense amplifier strobed output (at the collector of Q6) is typically O. 20 I-Lsec, while the turn-off delay is 0.30
to O. 40 ~sec.
2
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J
Output Waveform Characteristics
The strobed output of the sensed amplifier (on the collector of Q6) is
a O. 30 to 0.40 f.Lsec width pulse with a maximum rise time of O. 10
f.Lsec and a falltime of typically O. 20 f.Lsec.
The flip-flop output pulses are standard S-PAC signals. The waveform characteristics are the same as for the FA-30 S-PAC.
Current Requirements
J
-18 V:
- 6 V:
+12 V:
100 rna
34 rna
50 rna
J
J
J
J
J
J
3/4
D
J
J
J
D
TPIA
TP2A
RI6A
TPIB
TP28
RI6B
RI7B
- RI4B
RI7A
RI4A
RI8A
RI8B
RI5B
RI5A
RI3B
D
D
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..--,
lJ
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J
J
RI3A
R98
R2A
RIOB
~--
RIOA
R7A
R4A
RIIA
R5A
R6A
R3A
R8A
R9A
~~--
RI2A
R4B
RIIB
R7B
R5B
R3B
R8B
R6B
R2B
RIB
RI2B
R21B
R20B
R22B
R23B
~--
.,...".,.",.--...-- RI A
----r-__
R34A
--r--- RI9B
- . - - - R33A
- ; - - - R32A
R30A
R25A
R27B
R24A
R29B
R31B
R288
R24B
R30B
R31A
R26A
R29A
R28A
R27A
R25B
R23A
R26B
R33B
R32B
R22A
R20A
R21A
RI9A
R34B
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Figure 1. Bit Register PAC, Model BR-32,
Parts Location (Resistors and Test Points)
5
n
---.J
[l
l.-.J
n
QSA
w
C7
CIA
Q5A
CR5A
CR2A
CR3A
Q3A
Q4A
CRIA
QIA
n
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I.-.J
rl
Q2A
r'
CRSB
CR4A
CSA
QaA
CRI9A
n
r-'
CRI8A
CR21
CRI7A
CRI2A
CRIIA
C4A
CR20A
CRI5A
C5A
CRI3A
Q7A
CRI4A
C3A
CRISA
CRIOA
CR9A
CRaA
CRSA
C2A
CR7A
I'
r·-'
r"
I'
Figure 2. Bit Register PAC, Model BR-32,
Parts Location (Capacitors, Diodes, and Transistors)
6
r--'
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CIRCUIT A
+12V
TPI
+12V
+12V
o
+12\1
-6V
R9
681
R2
681
TP2
+12V
RI5
5.6K
CR4
RIO
510
RI8
3K
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19.6K
-=
-18V
-18V
-18V
-IBV
R20
9.09K
RI
178
IJ
R6
15
R3
15
~
@--f - -SENSE INPUT
{
SET LEVEL
CONTROL
AC SET I
32
CIRCUIT B
~
SAME AS CIRCUIT A
AC SET 2
@---1
I
AC RESET
~
I
RESET LEVEL
CONTROL
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t::':\
-18V
_l
~
COMMON RESET
R23
14K
R29
21.5K
CRIO
CRI6
AC SET
+12V
R33
21.5K
+12V
2
Q
~
SET
OUTPUT
RESET
-IBV
-IBV
BR-32
AC SET 2 ........2_1_ _ _--1
OUTPUT
R24
4.02K
--.L-r-c-7-----0 -18V
I
0.GS8J::--0f
3 -6V
I
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,/ C8
O.068p18+ 12V
R25
14K
12
SET OUTPlJT
CRI7
AC RESET
RESET LEVEL CONTROL
RESET
LEVEL
CONTROL
R26
390
CRI2
16r-~~-------1~-
t - - - - - - - 1 COMMON RESET
AC SET 2
SET LEVEL CONTROL
AC SET I
STROBE INPUT -t:-"";;';"'--+lh
r:
SENSE INPUT {
I
AC RESET
RESET LEVEL CONTROL
lJ
RESET OUTPUT
R32
2.26K
CR8
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~_ _ _ _ .,. _____ I
II
-18V
-18V
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1
CRI9
-6vcr----_.M--.
AC SET
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R34
2.26K
.---..r----~.-___11____i
R21
4.02K
C2
250PF
R8
1960
I
R31
6.49K
CR20
-18V
R7
12.1
I
-IBV
SET OUTPUT
I
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Q . I
R30
6.49K
R27
2.26K
__--------~--{)-6V
L __ ,
I
-IBV
CRI3
SET
LEVEL
CONTROL
-=
STROBE
-IBV
- 6V
CRI4
R4
12.1
]
RI2
178
R5
50
-=
~J
CRS
RII
S 29 SET OUTPUT
27 RESET OUTPUT
22 COMMON RESET
1
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Figure 3. Bit Register PAC, Model BR-32,
Schematic and Logic Diagram
7/8
J
BIT REGISTER PAC, MODEL BR-32, PARTS LIST
ASSY LEVEL
fl
DESCRt PTtON
3C DWG NO.
CAP, fxd, mica diele c:
ISO pf ± So/a, 100 VDC
930 011 131
CAP, fxd, mica dielec:
2S0 pf ± S%, 100 VDC
930 011 137
REF.DEStG.
AJSJCJOJEJFJ
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Cl, CS, C6
C2,
J
C3~
C4
930 301 01S
O. 068 IJ.f ± 20%, 100 VDC
C7,C8
CAP, fxd, plastic dielec:
CR4, CR1S,
DIODE: Replacement type 1N816
-_._.
943 lOS 001
CR21
CR1-CR3,
943 023 001
DIODE: Replacement type 1N69S
CRS-CR14,
CR16- CR20
-
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R1, R12
RES, fxd, film:
178 ohms ± 2%, 1/4 W
932 102 113
R2, R9
RES, fxd, film:
681 ohms ± 1 %, 1/4 W
932 108 181
R3, R6
RES, fxd, film:
lS.0 ohms ± 1%, 1/4 W
932 108 018
R4,R7
RES, fxd, film:
12. 1 ohm s ± 10/0, 1/4 W
932 108 009
RS
RES, variable wirewound:
R8
RES, fxd, film:
RIO
RES, fxd, camp:
R11
RES, fxd, film:
R13
RES, fxd, camp:
33.2 K ±2%, 1/4 W
932 102 326
R14, R1S
RES, fxd, camp:
S.6 K ± S%, 1/2 W
932 004 067
RIb
RES, fxd, camp:
2.4 K ± S%, 1/2 W
932 004 OS8
R17
RES, fxd, camp:
39 K ±S%, 1/2 W
932 004 087
R18
RES, fxd, camp:
3 K ± So/a, 1/2 W
932 004 060
R19, R26
RES, fxd, camp:
390 ohms ± S%, 1/4 W
932 007 039
R20
RES, fxd, film:
9.09 K ±2%, 1/4 W
932 102 247
R21, R22, R24
RES, fxd, film:
4.02 K ±2%, 1/4 W
932 102 230
R23, R2S
RES, fxd, film:
14 K ±2%, 1/4 W
932 102 308
R27, R34
RES, fxd, film:
2.26 K ±2%, 1/2 W
932 103 218
R28, R32
RES, fxd, film:
2.26 K ±2%, 1/4 W
932 102 218
R29, R33
RES, fxd, film:
21. S K ±2%, 1/4 W
932 102 317
R30, R31
RES, fxd, film:
6.49 K ±2%, 1/4 W
932 102 240
SO ohms ±10% 1/4 W
1. 96 K ± 1 0/0, 1/4 W
S10 ohms ± S%, 1/2 W
19.6K±2%, 1/4 W
933 20S 002
932 108 229
932 004 042
932 102 31S
9/10
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]
BIT REGISTER PAC, MODEL BR-32, PARTS LIST (Cant)
ASSY LEVEL
REF. DESIG.
DESCRIPTION
3C
DWG NO.
AJBJCJDJEJFJ
Q2
TSTR:
Replacement type 2N388
943 507 001
P3, Q4, Q6
TSTR:
Replacement type 2N 1303
943 537 001
pS
TSTR:
Replacement type 2N706
943 700 001
Q7, Q8
TSTR:
Replacement type 2N 1301
943 535 002
'i
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11
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ADDRESS DECODER PAC, MODEL DP-32
GENERAL DESCRIPTION
The Address Decoder PA.C, Model DP-32 (Figures 1 and 2), contains
a prewired binary-to-octal decoder.
and eight output lines.
The octal matrix has nine input lines
Six inputs (three complementary pairs) are wired to
activate one of the eight outputs.
The three additional input line s are provided
to permit the matrix to be expanded to 16, 32, or 64 outputs by connecting additional PACs in parallel.
Two additional independent NAND gates are included
on each P A.C.
CIRCUIT DESCRIPTION
Octal Matrix
The octal matrix has nine input lines driving eight NA.ND gates (Figure
3).
Six of the nine input line s (pins 15 through 2 a inclus i ve) ar e driven by the
assertions and negations of a 3-bit binary number.
These six input lines are
prewired to three inputs on each of the eight gates.
The three inputs then be-
come discrete combinations of the three binary bits and their negations. As
0
1
an example, the gate driving output line six (pin 9) has 2 ,2 , and 22 as the
three inputs.
Each of the eight gates has six inputs.
J
1
LJ
Three inputs recognize a dis-
crete binary number from 000 through III as described above.
The other
three inputs are common to all eight gates and are brought out to pins 12, 13,
and 14 on the connector.
The six inputs to any gate must be a ONE (- 6 V) to
activate the gate output.
Since pins 12, 13, and 14 form three common and
direct inputs to all eight gates, all the inputs must be ONEs to have one of
the eight output lines activated (0 V).
When deactivated an output line is -18
volts.
J
No connection to pins 12, 13, or 14 is equivalent to having the input at
ONE.
The application of a ZERO to anyone of the common input lines inhibits
the octal matrix.
This feature is useful for application on multioctal matrices,
BCD-to-decimal decoding, and strobing.
J
Multioctal Matrices
Matrices having 16, 32, or 64 outputs are formed by driving multiple
octal matrices in parallel.
It is neces sary to inhibit all but the one matrix
that contains the significant output line.
trix, eight octal matrices are used.
A.s an example, in a 64- output ma-
It is necessary to inhibit seven of these
I
lJ
J
1
n
to activate one of 64 output lines.
The seven octal matrices are inhibited by
applying ZERO to either pin 12, 13, or 14. For example, if the binary bits
3
4
2 , 2 , and 25 are true (ONE), the seven matrices containing outputs 0 through
55 inclusive are inhibited.
ing on the states of bits
r-'
Only one output from 56 to 63 is activated, depend1
2
2 , and 2 .
o
2 ,
SPECIFICA TIONS
Input Loading
Binary-to-Octal and Multioctal Matrices
8 output decoder (3 bits):
3 unit loads each
1"1
16 output decoder (4 bits): 4unit loads each
32 output decoder (15 bits):
64 output decoder (6 bits):
7 unit loads each
14 unit loads each
BCD-to-Decimal Decoder
o
rl
-0
Binary bits 2 , and 2
1 -1
2
-2
Binary bits 2 , 2 , 2 , and 2
3
Binary bits 2
3
Binary bit 2
n
4 unit loads each
3 unit loads each
2 unit loads each
II
5 unit loads each
Frequency of Operation
r
DC to 500 KC
Circuit Delay
Turn-on delay:
O. 05 Jl sec (typ)
O. 10 Jl sec (max)
Turn-off delay:
o. 10 Jl sec (typ)
0.15 Jlsec (max)
Output Waveform Characteristics
Rise time:
Fall time:
0.40 Jlsec (typ)
Jl sec (max)
o. 60
0.80 Jl sec (typ)
1.0 Jlsec (max)
Output Drive Capability
17. 5 ma and 500 pf each output (s election switch load)
Power Requirements
-18 V:
77 ma
- 6 V:
11 ma (current from supply)
+12 V:
5 ma
Total Power
1.6 W
2
11
i1
J
J
J
J
J
R5
RI2
RIB
R3B
R3E
CIF
J
J
J
R2F
R2E
1
R2D
-R4C
__
:..l.-.:...-_-CI C
RIC
R3D
R3G
J
R2H
RIG
R3J
R3H
R2K
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]
Figure 1.
R3K
C3
CIH
QID
C2
RIJ
Address Decoder PAC, Model DP-32, Parts Location
(Resistors, Capacitors, and Transistors)
3
r-'
'1
CR2A
CR6A
CR4A
W
11
'--'
CR4E
fI
CR7B
r-l
L-.
11
CR4F
'--'
11
CRIF
11
CR3F
CRIC
'1
CR4C
I'
CRSK
CR4H
Figure 2.
4
CR2K
CRIK
CR2H
CR5J
CRIJ
CR3J
CR3G
CR4G
Address Decoder PAC, Model DP-32, Parts Location
(Diodes)
J
-SV
2
21
2"1
22
19
18
17
IS
LJ
22
I
t.J
COMMON
INPUTS
OUTPUTS
-18V
INJ-YiS
RI2
33K
BINARY
INPUTS
1
TYPICAL CIRCUIT
A THRU H
0
2"0
J
-18V
15
r:
14
Z
12
13
H
CIRCUITS
A THRU H
PIN NUMBERS
112W
RII
33K
B
C
D
E
F
15
15
15
IS
IS IS IS
17
17 18 18
17
17 18 18
1/2W
RIO
33K
1/2W
R9
33K
G H
A
15
CR3
R3
21.5K
19 20 19 20 19 20 19 20
1/2W
R8
33K
14
14 14 14
1/2W
R7
33K
14
2
+
CR4
1
CR5
13
13 13 13
12 12 12 12
12 12 12
13 13
13 13
112W
RS
33K
C4
0.OS8UF
CIRCUIT K
-18V
-18V
-18V
J
J
R2K CR7K
2.2SK
GATE
INPUTS
+
NODE
NODE
CIRCUITS
BINARY
INPUTS
u
I~
II
19
S
18
35
22
COMMON
INPUTS
{~
Z
CIRCUIT
K
20
21
22
12V
31 l - - - - - - - '
DP
20
21
R3K
21.5K
A-H
CIRCUIT
I
12V
1/2W
CIRCUIT J
L-J
8+
CRS
12
1/2W
R5
33K
-18V
1
0- sv
12V
14 14 14
-18V
ZERO
ONE
17
8
IS
15
14
33
THREE
TWO
:J
34
FOUR
FIVE
13
9
12
32
OUTPUT
OUTPUT
OCTAL
OUTPUT
NODE
SIX
SEVEN
'I
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Address Decoder PAC, Model DP-32, ScheITlatic and Logic Diagram.
5/6
]
]
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]
ADDRESS DECODER PAC , MODEL DP-32 PARTS LIST
REF. DESIG.
ASSY LEVEL
OEseR I PTION
3C
OWG NO.
AJsJeJoJEJFJ
Cl
CAP, fxd, mica dielec:
390 pf ±lO%, 100 VDC
930 011 142
C2, C3
CAP, fxd, mica dielec:
150 pf ±5%, 100 VDC
930 011 131
C4, C5
CAP, fxd, plastic dielec:
CRI-CR6
DIODE: Replacement type IN695
CR7
DIODE: Replacement type lN816
943 105 001
HI
RES, fxd, film:
6.49 K ±2%, 1/4 W
932 102 240
R2
RES, fxd, filrn:
2.26 K ±2%, 1/4 W
932 102 218
H.3
RES, fxd, film:
21. 5 K ±2%, 1/4 W
932 102 317
R4
RES, fxd, film:
2.26 K ±2%, 1/2 W
932 103 218
JZ 5 - R 13
RES, fxd, camp:
33 K ±5%, 1/2 W
932 004 085
f------
O. 068 ~f ±20%, 100 VDC
930 301 015
1\
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]
-_.-
943 023 001
1---
01
TSTR: Replacement type 2N1305
943 537 002
Q2,03
TSTR: Replacement type 2N130 1
943 535 002
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7
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GATE DRIVER PAC, MODEL GD-32
GENERAL DESCRIPTION
The Gate Driver PAC, Model GD-32 (Figures 1 and 2), consists of
four identical amplifier stages that provide read and write gating pulses to
X and Y selection switches.
CIRCUIT DESCRIPTION
A O-volt input to the NAND gate (Figure 3) holds transistor Ql off.
J
The collector of Ql is clamped to - 6.3 volts by ON transistor Q2.
CR4 and CR5 are normally off.
resistor R8.
Diodes
Transistor Q3 is off due to diode CR6 and
The output at the collector of Q3 is clamped to + 0.6 volts by
diode CR 7 and resistor R 7.
When all inputs to the NAND gate are at - 6 volts, transistor Ql sat-
J
J
urates.
The resulting +6-volt pulse at the collector of Ql turns on diode CR4
and transistor Q3 through capacitor C2.
diode CR4.
biased.
The collector of Q3 falls to -17 volts and diode CR 7 is reverse-
During the fall time of the input pulse the collector of transistor 01
is clamped to -6.3 volts by transistor Q2.
biased.
J
Transistor Q2 is reverse-biased by
Diode CR4 becomes reverse-
The negative puIs e at the emitter of Q2 is coupled through capacitor
C2 and turns off transistor Q3.
Capacitor C2 discharges rapidly through
transistor Q2 and diode CR5.
NOTE
For all applications of the GD-32, pin 35 should be
jumpered to pin 5 (ground). The jumper attenuates
noise picked up by distributed impedance of the etched
circuit.
SPECIFICA TIONS
Freque~cy
J
J
of Operation
The GD-32 can be used at frequencies up to 500 KC.
The minimum time between pulses is 1 Jlsec.
The maximum input pulse width is 5 Jlsec.
Input
The input is a standard S-PAC signal.
load and 320 pf per channel.
The input loading is 1 unit
Output
J
J
J
The output is a + O. 6 to - 17- volt puIs e. Each output will provide 70
rna when it is at -17 volts and 0 rna when it is at +0.6 volt.
1
Circuit Delay
n
Turn on delay (10% to 10%):
o. 3 0 J-l sec (typ )
o. 50 J-l sec (max)
Turn off delay (90% to 90%):
0.30 J-lsec (typ)
o. 5 0 J-l sec (max)
Output Waveform Characteristics
Rise time (10% to 90%):
o. 06 J.l sec (typ)
o. 1 0 J-l sec ( max)
Fall time (90% to 10%):
0.25 J-lsec (typ)
0.30 J-lsec (max)
Current Requirements
All channels off:
-18 V: 57 rna
- 6 V:
21 rna (from supply)
+12 V:
48 rna
Normal operating conditions:
2 J-l sec: read channels on, write channels off
2 J-l sec: write channels on, read channels on
1 J-lsec:
all channels off
-18 V:
172 rna
- 6 V:
12 rna (from supply)
+12 V:
78 rna
I'
11
,1
2
J
J
J
J
J
J
J
RBC
RBB
R7C
R78
Q3C
Q38
R6C
R68
R5C
R5B
R4C
R4B
Q2C
Q2B
QIC
QIB
R3C
R3B
J
R2C
R2B
RIC
RIB
1
RBD
RBA
LJ
J
J
J
-':;;---io-
R7 A
R6A
Q3D
Q3A
R5D
R5A
R4D
R4A
QID
QIA
R3A
RIA
'l
Q2A
U
R2A
J
J
J
rt
lJ
J
'I
lJ
Figure 1. Gate Driver PAC, Model GD-32,
Parts Location (Resistors and Transistors)
3
r-,
n
TPIC
TPID
CR7C
C3
CR7B
TPIA
TPIB
rl
C2B
C2C
CR5B
CR5C
CR6C
CR4C
CR6B
r-'
CR4B
CIB
CIC
r1
--..
CR3B
CR3C
r,
C5
C4
CR7D
CR7A
i1
CR5D
CR6D
CR5A
CR6A
r'
C2A
C2D
CR4A
CR4D
r- 1
CIA
CID
CR3D
CR3A
CR2D CRID CR2C CRIC
r-'
CR2B C.RIB CR2A CRIA
['
Figure 2. Gate Driver PAC, Model GD- 32,
Parts Location (Capacitors, Diodes, and Test Points)
4
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CIRCUIT A
+12V
-6V
J
TPI
GD-32
16
OUTPUT
INP~TS{
+12V
10
II
'1
J
8
A INPUTS
14
IN:UTS {
1
18
15
lJ
9
NODE A
a
CR5
RI
6.49K
J
-Iav
B INPUTS
.--,
@~--I
NODE B
INpCUTS {
31
22
R4
2.26K
-
-Iav
28
-
-18V
25
INpDUTS {
26
29
{@
l..J
OUTPUTS
21
CIRCUIT B
~--~~
SAME AS CIRCUIT A
OUTPUT
0""""--.. .__ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
,.----------------t 2
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LJ
C INPUTS
{@
- - - - - - - - - - - - - - - -
@--.....SAMEASCIRCUIT A
NODEC
- - - - - - - -
-,
~-~®
OUTPUT
I
@~-.....
I
-------------------------~
+
C3
6.8UF
1~c-4--~
+6.8UF
LJ
o
INPUTS {
NODE 0
~~----t
@--.. .
-18V
I,...-----~
-6V
+12V
.l: 6.8l)1='
C5
CIRCUIT D
SAME AS CIRCUIT A
~-. . .@
-----------------------~
OUTPUT
_ - - -....- - - - - - t l t - - - - - - - (
5
GND
-----------( 35
Figure 3. Gate Driver PAC, Model GD-32,
Schematic and Logic Diagram
S/6
:)
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GATE DRIVER PAC, MODEL GD-32, PARTS LIST
J
ASSY LEVEL
REF. OESIG.
OESCRI PTION
3C
OWG NO.
AJSJCJOJEJFJ
r-1
LJ
]
930 011 131
Cl
CAP, fxd, mic a dielec: 150 pf ±100/0, 100 V
C2
CAP, fxd, plastic dielec: 0.01
C3-C5
CAP, fxd, elec TANTalum: 6.8
CRl, CR2
DIODE: Replacement type 1 N69 5
943 023 001
CR3
DIODE: Replacement type lN8l6
943 105 001
CR4, CR5
DIODE: Replacement type CTP462
943 001 001
CR6
DIODE: Replacement type IN8l6
943 008 001
CR7
DIODE: Replacement type lN916
943 083 001
Rl
RES, fxd, film: 6. 49 K ±20/o, 1/2 W
932 103 240
R2, R4
RES, fxd, film: 2. 26 K ±2o/o, 1/2 W
932 103 218
R3
RES, fxd, film: 21. 5 K ±2%, 1/2 W
932 103 317
R5
RES, fxd, camp: 10 ahms ±50/0, 1/2 W
932 004 001
R6
RES, fxd, camp: 910 ahlns ±50/0, 1/2 W
932 004 048
R7
RES, fxd, camp: 1 K ±50/0, 1 W
932 005 049
R8
RES, fxd, camp: 3 K ±50/0, 1/2 W
932 004 060
Ql, Q2
TSTR: Replacement type 3C130l
943 535 002
Q3
TSTR: Replacement type 2N388
943 507 001
J.lf
±200/0, 100 V
930 301 009
±200/0, 35 V
930 217 020
J.lf
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,'--'
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'.-1
L ....
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7
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DYNAMIC CURRENT DRIVER PAC, MODEL MD-32
GENERA.L DESCRIPTION
The Dynamic Current Driver PAC, Model MD- 32 (Figure 1), contains two identical amplifier and current regulator stages that provide temperature-compensated currents of up to 300 rna to memory drive lines. Each
channel is a read or write constant-current source and is switched on and off
by memory control pulses.
A thermistor-controlled voltage reference net-
work provides currents that are compensated to match the temperature characteristics of the magnetic cores.
Rise and fall times of the output current
are controlled by pas si ve components.
The current amplitude is adjusted by
means of an externally mounted potentiometer.
J
CIRCUIT DESCRIPTION
Transistors Ql, Q3, Q4, and Q5 (Figure 2) are off and 02 is on with
1LJ
no input pulse applied.
... 18 V.
Transistor Q2 and diode CR3 hold the base of Q3 at
Diode CR4 is reverse-biased and its cathode is held at -14 V (at 25°C)
by the thermistor-controlled reference voltage network.
A. positive control input pulse (-6 to 0 V) turns on Ql.
The negative
pulse on the collector of QI is coupled through capacitor C2 to turn off transistor Q2.
When Q2 is turned off, its collector is clamped to.6 volts by
diode CR2.
This voltage turns off CR3 which clamps the base of Q3 to the
-14-volt reference voltage.
The positive pulse at the base of Q3 turns on the emitter-follower and
applies a 4-volt pulse to turn on Q4 and Q5.
The emitter currents of transis-
tors Q4 and Q5 are determined by the reference voltage and their respective
emitter resistors.
rents on 04 and Q5.
The output current flow is the sum of the collector curSince transistors 04 and Q5 are not saturated, the out-
put current is independent of the load voltage.
The output current amplitude
varies nominally -0. 5%/° C over a 0 to 50° C range to match the temperature
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coefficient of the magnetic cores.
SPECIFICA TIONS
Frequency of Operation
The maximum operating frequency is 400 KC with a maximum duty
cycle of 50%.
J
1
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]
Input
The input is a standard S-PA.C (-6 to 0 V) signal with a duration determined by the output current puIs e width desired. The input loading is I unit load plus 360 pf (input at 0 V) and 0.3 rna with input at
- 6 volts.
I
11
Output
Each output will provide constant-current pulses of 150 rna to 300 rna
(determined by setting of the externally mounted potentiometer) into
grounded loads. The currents will remain regulated for load back
voltages up to -12 volts. The output current rise and fall times are
controlled by C3 and C4 respectively.
n
Circuit Delay (at 250 rna, 25°C)
Turn on d ela y (1 0 % to 1 0 %) :
O. 25 Jl sec (typ)
0.50 Jl sec (max)
Turn off delay (90% to 90%):
0.25 Jlsec (typ)
0.50 Jlsec (max)
Output Current Waveform Characteristics (at 250 rna, 25°C)
Rise time (10% to 90%):
0.25 Jlsec (typ)
O. 30 Jl sec (max)
Fall time (90% to 10%):
0.25 Jlsec (typ)
0.30 Jlsec (max)
Current Requirern ents
Both Channels Off
Split Cycle
(50% duty cycle)
Full Cycle
(25% duty cycle)
-18 V:
125 rna
-18 V:
-18 V:
- 6 V: <0. 1 rna
- 6 V:
+12 V:
+12 V:
36 rna
280 rna
36 rna
(into supply)
26 rna
140 rna
- 6 V:
18 rna
(into supply)
+12 V:
13 rna
i'
2
J
J
R9B
J
J
C5
CG
CR4B CR5
RI2
RI3
RIO
RII
C7
CS
R9A
Q5B
Q5A
C4B
C4A
Q3B
Q3A
RSB
RSA
CR3B
CR3A
C3B
R7B
RGA
RGB
RI5B :--+-+--....;.,--
J
CR4A
----~~- RISA
CR2A
CR2B
Q2B
R4A
R4B
J
R5e
RIGe
R5A
RIGA
Q4A
Q4B
C2B
J
CRIB
CRIA
QIA
QIB
R2B
CIB
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]
Figure 1.
RIB
RI4B
RI4A
RIA
CIA
Dynamic Current Driver PAC, Model MD-32, Parts Location
3/4
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CIRCUIT A
r---+12V
+12V
-------------,
I
R3
750
MD-32
CRI
C3
250PF
R4
B.2K
CI
510PF
R7
10K
RB
.200
-
INPUT
r
R6
510
HEATSiNK
Q3
C2
1500PF
R14·
10
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LJ
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INPUT
14 }-----:-+-----JlN\i-.......---t-"1
CR2
01
R5
B.2K
C4
200PF
510
]
'-~-------+-~~17 CURRENT
OUTPUT
19
CURRENT
OUTPUT
22
CURRENT} 20
CONTROL
RI5
10
1-6V
-6V
-IBV
16r-~------------------------------_+-----------~------------~
-IBV
CURRENT
CONTROL
-6V
-IBV
I
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L
r-----------
..,
I
CIRCUIT B
SAME AS CIRCUIT A
RI2
100
L-@
I
~------------~ 2
RIO
220
RII
470
@
C5
22UF
+
CR5
RI3
270
25°C
C6
---------
......
-IBV
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I
CURRENT
OUTPUT
CONTROL
INPUT
R9 .
17
CURRENT} 16
02
RI
2.7K
14
1
C7
~ :~2:
I
I. . .
1.+_2_2u_F_ _ _I+-_0_.0_6_8_u_F__
-18V
CB
_0_.0_6_80 GND
Figure 2. Dynamic Current Driver PAC,
Model MD-.32, Schematic
and Logic Diagram
5/6
]
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DYNAMIC CURRENT DRIVER PAC, MODEL MD-32, PARTS LIST
ASSY LEVEL
I
]
]
]
REF. OESIG.
A
J BJ
C
I
0
OESCRI PTION
JEJFJ
3C
OWG NO.
Cl
CAP, fxd, mica die1ec: 5 10 pf ± 1 00/0, 100 VDC
930 011 046
C2
CAP, fxd, mic a die1ec: 1500 Ef ±100/0, 100 VDC
930 006 057
C3
CAP
C4
CAP, fxd, mica die1ec: 200 pf ±10%, 100 VDC
930 011 034
C5 C6
CAP, fxd, elec TANTalum: 22 IJ,f ±200/0, 35 VDC
930 217 023
C7 C8
CAP, fxd, pJ-astic dielec: 0.068 gf ±2~_0/0, 100 VDC
930 301 015
CRI-CR4
DIODE: Replacement type IN695
943 023 001
CR5
DIODE:
fxd
mica die1ec: 250 pf ±5%, 100 VDC
Rcpla.~~~_ment
930 011 137
943 102 001
type IN706
'1
,J
-
-----------
]
]
Rl
RES, fxd, c croYlP: 2. 7 K ±5%, 1/2 W
932 004 059
R2
RES, fxd, comp: 36 K ±50/0, 1/2 W
932 004 086
R3
RES, fxd, comp: 750 ohms ±50/0, 1/2 W
932 004 046
R4, R5
RES, {xd, comp: 8.2 K ±50/o,
932 004 071
R6, R9
RES, fxd, comp: 510 ohm s ±50/0, 1/2 W
932 004 042
RES, £xd, comp: 10 K ±50/o, 1/2 W
932 004 073
R7
1/2 W
--------------
--
~-----
RES, £xd, comp: 200 ohms ±50/o, 1/2 W
932 004 032
RES, £xd, comp: 220 ohms ±50/o, 1/2 W
932 004 033
RES, THERMal: 470 ohms (25°C)
932 300 002
RES, fxd, comp: 100 ohm s ±50/o, 1/2 W
932 004 025
n 13
RES, fxd, comp: 270 ohms ±50/o, 2W
932 006 -035
I
----i
n 14, n 1 S
RES, £xd, comp: 10 ohms ±50/o, lW
932 005 001
'• ....J
R16
RES, fxd, comp: 300 ohms ± 5%, 1/2 W
932 004 036
..J
Ql, Q2
TSTR: Replacement type 2N388
943 507 001
Q3
TSTR: Replacement type 2N 1959
943 703 001
Q4, Q5
TSTR: ReplacenJent type 2N2219
943 705 003
R8
J
f----
RIO
~ __ ~~\ 11
1\12
i
1------
1
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]
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7
i
J
INHIBIT DRIVER PAC, MODEL MI-32
GENERAL DESCRIPTION
The Inhibit Driver PA.C, Model MI-32 (Figures 1 and 2), contains
eight identical channels that provide inhibit current of 150 to 300 rna.
J
An
amplifier is provided to supply a COITlmon aITlplified tiITling signal to each
driver circuit.
The MI-32 can also be used as a solenoid driver or for
other high.;.power driving applications.
CIRCUIT DESCRIPTION
'1
lJ
J
The PAC contains eight switching circuits (Figure 3) that have positive
logic AND gate inputs.
Each switch can be inhibited by the output of tiITling
aITlplifier Q1 which supplies one input to each switch with an aITlplified, inverted, ITleITlory inhibit input signal (ZS).
Any gate input at - 6 volts will hold
output transistor Q4 off.
Transistors Q2 and Q3 are on and transistors Q4 and Q1 are off with
no signal applied.
J
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J
urates.
When a negative input (ZS) is applied, transistor Q1 sat-
When all inputs to the positive AND gate are at 0 volt, transistor Q2
is cut off.
The Q2 collector voltage rises toward -18 volts but it is clamped
at -6 volts by transistor 03.
The negative pulse at the emitter of transistor
Q3 saturates transistor Q4.
The inhibit current flows froITl ground, through
transistor 04 and the inhibit hoard precision resistors, to the -18- volt supply.
(During the fall time of the (ZS), input transistor Q1 turns off, turning on
transistor Q2.)
The positive pulse at the collector of transistor Q2 turns off
transistor Q3 and turns on diode CR5.
Transistor Q2 and diode CR5 provide
a low impedance discharge path for capacitor C2 to allow a fast turnoff of
transistor Q4.
SPECIFICA TIONS
Frequency of Operation
J
The ITlaxiITlum operating frequency is dependent on the reactance of
the load. Full cycle operation is at repetition frequencies of 200 KC
with a duty cycle of 40 percent. Split cycle operation results in repetition frequencies of 400 KC with a duty cycle of 80 percent.
Input
J
]
The inputs are standard S-PAC l-MC signals. The load on each -6volt gate input is 2.2 rna (to hold the output channel in the OFF condition). The load on a 0- volt gate input is 1/2 unit load. The tiITling
amplifier pres ents a load of 1. 2 units plus 50 pf to the inhibit step
timing input.
1
r,
Output
Each output can switch load currents between 150 and 300 rna. The
PA.C can handle inductive loads as large as 20 Jlh (provided an appropriate current-limiting resistor is connected in series). Inductive
back voltage up to 20 volts can be tolerated.
Circuit Delay
Turn on delay (10% to 10%):
Turn off delay (90% to 90%):
o. 1 5 Jl sec (typ)
0.20 Jlsec (max)
0.40 Jlsec (typ)
Jl sec (max)
o. 60
Output Current Waveform Characteristics (at 200 rna)
No Load Inductance
Ris e time (10% to 90%):
o. 3 0 Jl sec (typ)
0.40 Jlsec (max)
Fall time (90% to 10%):
O. 40 Jl sec (typ)
o. 80 Jl sec (max)
4096-word plane
L=15 Jlh (approx)
O. 6 Jl sec (typ)
o. 8 Jl sec ( max)
o. 60 Jl sec (typ)
1 . 0 Jl sec ( max)
Current Requirements
"
The current requirements of the MI-32 are catalogued according to
operation conditions below. The inhibit current drain from the -18volt supply is not included as it appears under the specifications of
the Inhibit Component Board.
Split Cycle
(80% Duty Cycle)
Full Cycle
(40% Duty Cycle)
All
Channels
OFF
All
Channels
OFF
All
Channels
ON.
All
Channels
ON
-18 V:
40 rna
58 rna
60 rna
43 rna
+12 V:
12 rna
60 rna
38 rna
29 rna
1 rna
110 rna
14 rna
46 rna
-
6 V:
(current
into supply)
1"'
,._,
"
,1
2
J
R7H
C3
C2G
R9G
J
RIOH
C2F
R9F
RIOG
RSE
C2E
J
J
Rac
R6C
R7B
RaB
R6B
R7A
RaA
R6A
R3
R4
R9A
R5B
R5A
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Figure 1.
Inhibit Driver PAC, Model MI-32, Parts Location
(Resistors and Capacitor s)
3
r-,
CR5F
Q4H
CR5H
CR5G
Q2H
Q'3H
r1
Q4G
Q4F
CR5E
I'
Q4E
Q4C
--..Io-":'~
CR5B
--'&""-L""
Q4B--+-i.~
11
CR5A
CR2G
CR'3H
CR4H
CR4G
CR'3G
CR2F
CR4F
CR'3F CR4E
CR2E
CR'3E CR2D CR4D CR'3D CR4C CR2C CR3C CR2B CR4B CR4A
CR'3A
I'
Figure 2.
4
Inhibit Driver PAC, Model MI-32, Parts Location
(Transistors and Diodes)
J
~--
+12V
CI
200PF
1
lJ
---------j
r----®
~
23
R3
30K
INHIBIT
TIMING
INPUT
: SAM~I=;~II~C~IT A
1... ___________ J
R4
560
CRI
A INFORMATION {
REGISTER
INPUTS
RI
5.6K
-=
-6V
~--------l
-IBV
~
CIRCUITG
ISAMEASCIRCUIT A
-Iav
~
~
_________ J
25
@-----L
J
CIRCUIT A
I
LJ
+12V
J
e-r--------l
l SAMEC~~C~/;C~IT ~
+12V
R6
8.2K
C2
2200 PF
CR2
RIO
1.5K
27
@-----L
- I
A
I
- ---- - - J
INHIBIT
OUTPUT
Q2
R5
INFORMATION {
REGISTER
INPUTS
2.7K
II
R7
CR5
12
14
15
o
f
16
E INFORMATION {
REGISTER
2D
21
F
INFORMATION
REGISTER
INPUTS
1
IN~~:~:~ION{
17
22
REGISTER
INPUTS
G INFORMATION {
REGISTER
INPUTS
23
H INFORMATION {
REGISTER
INPUTS
26
24
25
27
2.7K
CR4
~~~~
7
INHIBIT
TIMING INPUT
M)
MI-32
28
...
1D
13
C INFORMATION {
-6V
'1
J
REGISTER
INPUTS
REGISTER
INPUTS
--------------------------------,
r
B INFORMATION {
11
H)
...
29
H'
.,/
30
H)
..
HJ
H)
...
,
HJ
-
H)
31
32
INHIBIT
OUTPUTS
33
34
35
~
-IBV
L_ _ _ _ _ _ _ _ _ _ _ _ _
__________ --1I
'1,
U
'1
I
U
1C~
I
6.aJLf
+_
I
l,----~--,::
+1
-
C4
6 8JLf
•
8 ..
0
12 V
GND
lJ
J
I
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Figure 3. Inhibit Driver PAC,
Model MI-32, Schematic and
Logic Diagram
5/6
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REF. OESIG.
ASSY LEVEL
OESCR I PTION
3C OWG NO.
200 pf ± 10%, 100 VDC
930 011 034
AJSJCJOJEJFJ
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n
INHIBIT DRIVER PAC, MODEL MI-32, PAR TS LIST
Cl
CAP, fxd, mica dielec:
C2A-C2H
CAP, fxd, plastic dielec:
C3, C4
CAP, fxd, e1ec, TANTalum:
CRI-CR5
DIODE: Replacement type 1N695
943 023 001
Rl
RES, fxd, camp:
5.6 K ±5%, 1/2 W
932 004 067
R2
RES, fxd, camp:
3 K ±5%, 1/2 W
932 004 060
R3
RES, fxd, camp:
30 K ±5%, 1/2 W
932 004 084
R4
RES, fxd, camp:
560 ahms ±5%, 1W
932 005 043
R5, R7
RES, fxd, camp:
2.7 K ±5%, 1/2 W
932 004 059
R6
RES, fxd, camp:
8.2 K±5%, 1/2 W
932 004 071
R8
RES, fxd, camp:
10 ahms ±5%, 1/2 W
932 004 001
R9
RES, fxd, camp:
300 ahms ±5%, 1/2 W
932 004 036
RIO
RES, fxd, camp:
1.5 K ±5%, 1/2 W
932 004 053
01-03
TSTR: Replacement type 2N1301
943 535 002
04
TSTR: Replacement type 2N2374
943 553 002
2200 pf ±20%, 100 VDC
6. 8 fJ.f 20%, 35 VDC
930 301 004
930 217 020
I
, I
L.-l
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I
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..-,
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7
SELECTION SWITCH PAC, MODEL SS-32
GENERA.L DESCRIPTION
The Selection Switch PAC, Model SS-32 (Figures 1 and 2) contains
eight gated transistor switches with current steering diodes for doubleended s election of memory drive lines.
The proper output switch is turned
on in response to the decoded address information.
The read or write pulse
input and the dynamic current source input determine the direction of current
through the memory drive lines.
CIRCUIT DESCRIPTION
The eight input transistors, Ql and Q2 (Figure 3), are gating transistors that are normally off.
They are logical AND gates that saturate when a
simultaneous -18 to O-volt level and a +0. 6 to -17-volt pulse are present.
Four output transistors, Q3A-Q4A and Q3B-Q4B, are the top switch
pairs and are norInally off.
1
u
J
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]
Each top switch pair is connected through cur-
rent- steering diodes CR3- CRI8 to eight Inemory drive lines.
The four output
transistors Q3C-Q4C and Q3D-Q4D are the bottoIn (normally off) switch pairs
and connect to bused drive lines.
Selecting an individual drive line in the X or Y coordinate is aCCOInplished by turning on one top switch pair and one bottoIn switch pair.
The
selected switch pairs are activated by the presence of a decoder input level.
The read or write pulse input deterInines which input transistor in each switch
pair is selected.
The PAC outputs are connected to allow the decoded address
register data to select an individual drive line.
J
Transistor Q2A is turned on by coincidence of a O-volt decoder input
level and a -17-volt read pulse.
saturates transistor Q4A.
The -17-volt pulse on the collector of Q2A.
At the same tiIne one bottom switch pair turns on
if O-volt level is present at decoder input C, and transistors Ql C and Q3C
J
J
will saturate.
Read current flows froIn ground through the top switch transis-
tor (Q4A), a steering diode and selected drive line, and through the bottoIn
switch transistor (Q3C) to the current source.
The write portion of the cycle is similar except that alternate transistors in the top and bottoIn switch pairs turn on and the write current is steered
through the drive line in a direction opposite to the read current.
Application
of a decoder input A level and a write pulse turns on transistors QlA and
]
Q3A.
]
ing diode, and through Q3A to the current source.
l
w
The decoder C level and write pulse saturates Q2C and Q4C.
Write
current flows froIn ground, through Q4C and the selected drive line, a steer-
1
NOTE
In all applications of the SS-32 PAC, pin 15 should be
jumpered to pin 5 (ground) at the PAC connector.
SPECIFICA TrONS
Frequency of Operation
Frequency of operation is determined by load impedance and the timing relationship between the address signals and the load currents.
The SS- 32 is used normally at repetition frequencies from 200 KC to
400 KC.
n
Input
The inputs are a -18 to O-volt level at the decoder input and a +0. 6 to
-17-volt pulse at the read or write pulse input. The load on the address
decoder circuit is 14 rna with the input at 0 volt (during read or write
time) and less than 0.1 rna with the input at -18 volts.
The load on the read (or write) pulse input circuit is 70 rna when the
input is at -17 volts and less than 0.1 rna with the input at +0. 6 volts.
Output
The circuit will provide bipolar memory drive line currents of up to
300 rna and will tolerate load back voltages of 10 volts.
"
Circuit Delay (at 250 rna drive current)
The circuit delay is measured from the read or write pulse input to
the output emitter follower current flow (decoder level input at 0 volt ).
Turn on delay (10% of WP or RP to 10% of Q3 or Q4 emitter current):
O. 1 5 f1 sec (ty P )
0.30 f1 sec (max)
Turn off delay (90% of WP or RP to 90% of Q3 or Q4 emitter current):
O. 1 0 f1 sec (typ)
0.20 f1 sec (max)
Output Current Waveform Characteristics
The output current waveform is deterInined by the current source input except for the 40 rna pedestal caused by the output eInitter-follower
stage.
"
Current RequireInents
One Top
Switch Output Stage on,
All Circuits off Rest off
- 18 V: <0. 1 rna
-12 V:
2
32 rna
One Bottom
Switch Output Stage on,
Rest off
Two Output
Stages on. (One
Top Switch and
One BottoIn Switch)Rest off
8 Ina
8 Ina
17 rna
43 Ina
34 Ina
35 rna
"
"
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J
TP2A
TPIA
TPIB
TP2B
TP2C
TPIC
TPIO
TP20
R60
Reo
R50
R70
R7C
R5C
J
J
Rec
R6C
ReB
R7B
R6B
R7A
R5B
ReA
J
R5A
R6A
R3B
R3A
CIA
""'""-,...-......-RIA
~,---R4A
J
C2A
R2A
C3
C4
J
J
J
J
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Figure 1.
Selection Switch PAC, Model SS- 32, Parts Location
(Resistors, Capacitors and Test Points)
3
11
Q4D
Q3D
CR2D
CRID CRIC
Q2D
QID
QIC
r-,
~
Q3C
..--,
Q4C
Q4B
r-'
Q3B
Q3A
CR2C
CR2B
Q2C
r-'
r-'
Q4A
Q2B
CRI7A
CRISA
CRI5A
CRISB
CRI7S
CRIGB
CRI5B
CRI48
CRI3B
CRI2B
CRtlB
CRI08
CR9B
CR88
CR7S
CR4S
C'R3B
CR5S
CRGS
CRIB
CRIA
QIB
QIA
r'
r-'
CR2A
Q2A
CRIGA
CRI3A
CRI4A
CRIIA
CRI2A
CR9A
CRIOA
CR7A
CRSA
CR5A
CRGA
CR3A
r-'
r-'
r-'
CR4A
i'
Figure 2.
4
Selection Switch PAC, Model SS-32, Parts Location
(Diodes and Transistors)
J
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CIRCUIT A
WRITE
CURRENT INPUT
j--------r-e
32
TPI
J
J
J
R5
390
DECODER
INPUT A
CRI
J
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R7
4.71<
1'26'
~
CIRCUIT
~
SINGLE
SELECTION
OUTPUTS
SAME AS CIRCUIT A
0-1
~
L ________ J-@
R2
21<
R4
II<
WRITE CURRENT IN PU T 32
READ CURRENT INPUT a.
+12V
-IBV
READ PULSE
INPUT
CRIB
7
7_....-....
READ PULSE INPUT ...
DECODER INPUT A t-:1::.,.3-1-..
lJ
J
H§)
I~
I
R6
560
~
B
I
TP2
C2
220PF
J
~
I
+12V
B
J
r-€)
01
13
-18V
WRITE PULSE
INPUT
@--1
SINGLE
SELECTION
OUTPUTS
WRITE PULSE INPUT ..8+-1--4
CIRCUIT C
READ
34
CURRENT INPUT
DECODER INPUT 8 ...1-f2-+-.
TPI
J
J
CI
220PF
DECODER
INPUT II
C
R5
390
RI
2K
R7
4.7K
R3
IK
BUSSED
33 SELECTION
OUTPUT
'l
I
U
7
I
'I
R6
560
R2
2K
U
R4
IK
'l
LJ
'I
TP2
C2
220 PF
'I
U
+12V
-IBV
READ PULSE
INPUT
-IBV
WRITE PULSE
INPUT
r---------i
Q3
Q4
RB
1.5K
~I
~I
0-i
I
BUSSED
SELECTION
OUTPUTS
CIRCUIT
D
SAME AS CIRCUIT
DECODER INPUT D t-:1
1i:fo_
:~
C
L _______
+12V
~1~1.......
I
~
I
I
I
DECODER INPUT C
I
I
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..
GND -..:.;:;_ _ _ _ _
~
+
~
(2\-IBV
C3
6.BUF
\.V
~+12V
C4
6.BUF
-.1+ --
SEPARATE GROUND LEAD
0
B
U
J
l
lJ
Figure 3. Selection Switch PAC, Model SS- 32,
Schematic and Logic Diagram
5/6
'l
J
SELECTION SWITCH PAC, MODEL SS-32, PARTS LIST
'1
l.J
ASSY LEVEL
REF. OESIG.
OEseR I PTION
3C
OWG NO.
AJsJeJoJEJFJ
Cl. C2
C3
C4
CAP, fxd, mica dielec: 220 pf ±5o/o, 100 VDC
CAP
fxd. elec TANTalum: 6.8 uf ±20o/o, 35 VDC
930 011 135
930 217 020
CRI-CR18
DIODE: Replacement type CTP462
943 001 001
Rl, R2
RES, fxd, comp: 2 K ±5o/o, 1/2 W
932 004 056
R3, R4
RES, fxd, comp: 1 K ±5o/o, 1/2 W
932 004 049
R5
RES, fxd, comp: 390 ohms ±5o/o, 1W
932 005 039
.R6
RES, fxd, comp: 560 ohms ±5o/o, 1W
932 005 043
R7
RES, fxd, comp: 4.7 K ±5o/o, 1/2 W
932 004 065
R8
RES, fxd, comp: 1. 5 K ±5o/o, 1/2 W
932 004 053
Ql, Q2
TSTR: Replacement type 2N1302
943 550 001
Q3, Q4
TSTR: Replacement type 2N 1305
943 537 002
L1
,.---.,
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,
I
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~
I
I
L-l
..-,
I
I
I
_.• J
7
J
TIMING DISTRIBUTOR PAC, MODEL S-219
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GENERA'L DESCRIPTION.
The Timing Distributor PAC, model S-2l9
(Figures 1 and 2), provides accurately timed positive pulse sequences to
drive S-PACs.
The positive pulses are selected from a delay line.
The S-2l9
contains a gated input pulse generator, a 4 flsec passive delay line, and six
independent amplifiers.
The input to each amplifier can be connected to taps
on the delay line to provide output pulse sequences
J
J
J
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CIRCUIT FUNCTION.
Input negative logic signals activate a pair of
AND gates (2-legged and 3-legged) which are buffered through an OR gate to
the base of gating transistor Q6 (Figure 5).
Q6 turns it on which, in turn, sets flip-flop Q2 and Q3.
U
causes a pulse to be sent down the 4-fl sec delay line.
adjusted by selecting taps on the delay line
on the delay line tap.
J
J
This
The pulse width may be
Flip-flop reset is also dependent
Values of delay from the delay line can be obtained
from Table 1 and Figure 3.
Each delay line tapped output can be amplified and
inverted to provide an accurately timed, positive output pulse capable of
Input connection points for each amplifier are
located on the PAC to facilitate jumper connections to delay line tap points
(Figures 3 and 4).
l,
The reset output from
Q3 (a logical zero) will cause Q4 to cut-off and Q5 to start conduction,
dri ving five S- PAC unit loads.
I
A logic ONE (-6V) at the base of
Amplifiers A and B have AND gate inputs that can be
connected to any two separate points on the delay line.
arbitrarily narrow output pulses.
This will provide
A typical jumper connection arrangement is
illustrated in Figure 4.
J
J
J
J
l
.J
1
SPECIFICATIONS
Input Loading
Maximum Operating, Frequency
1/2 unit load (each gate)
500 KC
Output
Input Delay
5 unit loads (each output)
100 nsec, typical delay from
input to first delay line tap
Output Pulse Width
(max pulse width not to exceed
49% of the duty cycle) Adjustable
from 0.1 to 1. 0 j1sec. Two of
six channels can provide narrower
pulses.
Power Requirements
,1
I'
Quiescent:
+12 V: 6 rna
- 6 V: 35 rna (rev, )
-18 V: 120 rna
Total power 1. 2 W
Cycling at maximum rate:
r'
,1
65 rna
35 rna (rev.)
['
120 rna
Total power 1. 75 W
"
"
2
J
J
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TABLE 1
DELA Y LINE TAP POINTS WITH
CORRESPONDING DELAY LINE DELAYS
(Refer to Figure 3)
Delay Line
JUITlper Connection NR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Delay Line
Delay
(ns ±3%)
0
36
107
179
250
322
393
465
536
608
679
751
822
894
965
1000
1036
1107
1179
1250
1322
1393
1465
1536
1608
1679
1751
1822
1894
1965
2000
Delay Line
JUITlper Connection NR
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
Delay Line
Delay
(ns ±3%)
2036
2107
2179
2250
2322
2393
2465
2536
2608
2679
2751
2822
2894
2965
3000
3036
3107
3179
3250
3322
3393
3465
3536
3608
3679
3751
3822
3894
3965
4000
J
]
]
3
r""""J
C33
C6
C61
C34
C35
C60
C36
C59
C37
I'
C7
C4
C32
C58
C8
C5
C31
C38
C9
C62
C30
C63
CIO
C3
C29
C2
CII
C57
C28
CI
CI2
C39
C27
C56
CI3
C40
C26
C55
CI4
C41
C25
C54
CI5
C42
C24
C53
\..-..
11
r:
1',
\..-..
,"-'
I.-..
Ij
,
r-1
CI6
C43
C23
C52
CI7
C44
C22
C51
CI8
C45
C21
C50
CI9
C46
C20
C49
DLI
C47
DL2
C48
DL3
DL4
I,
r-'
r-'
r .... ·..
"
r-'
i'
i'
Figure 1. Timing Distributor PAC, Model S-219.
Parts Location (Capacitors and Delay Lines)
4
RII
R22
RI3
RI2
05
CR20
04
CR21
CR22
CRI3
CRI6
RI4
CRI9
RZI
CRI5
RZ
RIO
R6
J
J
J
CRII
R4
R9
R5
CRI7
R8
CRIO
R20
RI9
CRI4
R3
CRI2
02
CRI
06
RI
01
RI7
R7
RZ3A
J
J
RZ4A
03
---r--;;;';';'~'1·
CR23A
---r-";;;";"""'!"'!:"
07A
--j-"';:::';;"";:';"";;'
07B
--;.-",;;,,;,;-+
R23B
CR24A
J
CRZ5A
..;,;,;;......:.-- RZ4B
CR23B - - CR24B
CR25B
CR23C
R23C
RI6
R24C
RIa
CR25C
CR8
R23D
CR23D
R24D
CR9
07C
CR5
CR25D
CR6
R23E
CR7
R24E
CR25E
CRla
'I
RI5
CRZ
CRZ3E
CR23F
CR3
CR4
070
Q7E
Q7F
CR25F
R24F
R23F
J
l
LJ
l
]
Figure 2. Timing Distributor PAC, Model S-2l9,
Parts Location (Transistors, Diodes and Resistors)
5
ri
[1
31
61
30
32
29
60
2
33
28
59
3
34
4
58
27
35
5
57
r-'
r'
L-...
r-1
i'
26
36
6
56
25
37
r-'
7
55
24
r-'
54
8
38
9
53
23
39
52
22
40
(---,
II
51
21
41
12
50
42
20
49
13
43
14
48
19
44
15
47
18
45
46
16
r-'
r- 1
17
Figure 3.
6
r'
10
Timing Distributor PAC, Model 8-219,
Jumper Interconnection Diagram
r-'
r-'
J
J
J
J
J
J
J
ll.-J
J
J
:J
J
J
J
AI
A2
c
0
E
'I
J
I
LJ
'I
lJ
Figure 4.
]
]
Timing Distributor PAC, Model 8-219,
Jumper Interconnection Diagram
7/8
-IBV
-IBV
-IBV
-IBV
-Iav
+ 12V
R3
1.6K
R4
6.aK
R5
6.aK
CRI2
I
R7
3.9K
DLI
DL2
R21
IK
DL4
DL3
~:~:r-rI
I T~~:~T
T TH-R~-~T
CRI5
~----~----~-6V
J
R6
1.6K
-6VO---~~------.
c,750PF EA
t-------------------~----~------------------_+--------+_----------~20
SET OUTPUT
C20
750PF EA
..-___
C34
750PF EA
_
T
R22
91
C4B T-H-R-U C61
750PF EA
_
_ _......_ _ _....J
DELAY LINE
TAP 10
-IBV
CRI3
CRI6
~--------;4~------~--------b_--------~IB
RESET OUTPUT
-6V
r-:8V-------,8V-----'vl
RI
10K
R2
2.2K
RI4
47
CRIB
I
RII
2.2K
AI O-______
CRI9
CRII
+12V
A2
b~
R23A
7.5K
81
+ 12V
n-------~C~R~2~4~A---~------~
0
+12V
. , CR23B
CKT B
J
SAME AS_C_K_T_A___
~8V
CR3
INPUTS FROM
DELAY LINE TAPS
CR23C
C
S-219
CR5
_US 6
I
r
I ---
I
II--'C:..:.R:..=2..:.;4B=----'-~
I
I
I
I
-18V
RIB
6.BK
-IBV
~
13
-IBV
-6V
+ 12V
CD
0)
0
C63
O.IUF
:4
1
INPUTS
16
_US B
_US 9
_US 10
=D-
0
E
0
. , CR23D
~CR23E
---[}-
GND
CIRCUITS C,D,E,F
20
F 0
I
L
CIRCUITS A,B
_US"
lC62
O.IUF
I
U
OUTPUTS
D
. , CR23F
I
L
I
L
+------0
~
7
OUTPUT
8
OUTPUT
0
OUTPUT
-6V!
CR25C
I
I
-=-
CKT C_ _ _
_US 7
CR6
OUTPUT
~
___
CKTA
82 o _ _- t...
CR4
I
~C~R~2~3~A--~I------~--~~ ·------~------~1----~6
RI2
10K
R20
15K
1
u
CR25A
CKT D
SAME AS CKT C
CKT E
SAME AS CKT C
CKT F
SAME AS CKT C
~
I
I
@OUTPUT
~OUTM
'I
I
L.-J
l,.J
]
Figure 5.
Timing Distributor PAC,
Model S-219
Sche.matic and Logic Diagram
9/10
J
~ESIG'
J
TIMING DISTRIBUTOR PAC, MODEL S-219, PARTS LIST
ASSY LEVEL
OESCR I PTION
3C OWG NO.
AJSJ CJOJEJ FJ
Cl
Ci\P, fxd,
ITlica dielec:
62 pf ±50/0, 100 VDC
930 011 122
C2, C3, C4
CAP, fxd, mica dielec:
43 pf ±50/0, 100 VDC
930 011 116
-----
C5
CAP, fxd, ceramic dielec:
C6 - C61
CAP, fxd, ITlica dielec:
IC62, C63
CAP, fxd, plastic dielec:
CR 1-CR6,
DIODE:
O. 1 ~f ±200/0, 25 VDC
750 pf ±20/0, 100 VDC
O. 1 ~f ±200/0, 35 VDC
Replacement Type IN695
930 171 007
930 001 001
930217009
943 023 001
CR 1 O-CR 13,
, CR15-CR16,
CR l8-CR20,
CR23ACR23F,
CR25ACR25F
~
J
J
:J
I
I
\ ..-1
lL-J
J
J
943 083 001
CR7, CR9
DIODE:
,CR8
DIODE:
Replacernent Type 1 N702A
943 102 004
CR14, CR17,
DIODE:
ReplaceITlent Type 1 N816
943 105 001
CR19, CR2l,
CR22
DLI-DL4
COIL, Delay Line
Rl, R12
RES, fxd,
caITlp:
10K ±50/0, 1/4 W
932 007 073
R2, R 11
RES, fxd,
camp:
2.2 K ±50/0,
1/4 W
932 007 057
R3, R6
RES, fxd,
camp:
1.6 K ±50/0, 1/2 W
932 004 054
R4, R5, R16,
RES, fxd, camp:
6.8 K ±50/0,
1/4 W
932 007 069
R7
RES, fxd, camp:
3.9 K ±50/0, 1/4 W
932 007 063
R8,R9,R19
RES, fxd, camp:
1.6 K ±50/0, 1/4 W
932 007 054
991 005 001
R18
11/12
--
1
~l
TIMING DISTRIBUTOR PAC, MODEL S-21·9, PARTS LIST (Cant)
]
REF. OESIG.
J
l
ASSY LEVEL
OEseRI PTION
3C OWG NO.
AJaJ CJOJEJFJ
RIO, R20
RES, fxd,
camp:
15 K ±5%, 1/4 W
932 007 077
R13
RES, fxd,
camp:
2.7 K ±5%, 1/2 W
932 004 059
R14
RES, fxd,
com~:
47 ohms ±5%, 1/2 W
932 004 017
R15
RES, fxd,
camp:
220·ohms ±5%,
932 005 033
R17
RES, fxd,
camp:
20 K ±5%, 1/4 W
932 007 080
R21
RES, fxd,
camp:
1 K ±5%, 1/4 W
932 007 049
R22
RES, fxd,
camp:
91 ohms ±5%, 1/4 W
932 007 024
R23A-R23F
RES, fxd,
camp:
7.5 K ±5%,
1/4 W
932 007 070
R24A-R24F
RES, fxd,
camp:
2.2 K ±5%, 1/2 W
932 004 057
QI-Q7A-Q7F
TSTR:
L..J
r-I
J
]
]
1--
Replacement Type 2N965
lW
943 543 004
J
J
]
I
I
l-'
lu
,J
I
l-J
..--,
I
I
L.J
]
'I
I
1_)
13
INHIBIT COMPONENT BOARD
GENERAL DESCRIPTION
The Inhibit Component Board (Figures 1 and 2) contains the currentdetermining resistors and energy-storage capacitors used in the inhibit and
clear processes,
This board provides inhibit and clear currents for'up to 12
inhibit windings.
Bypass capacitors are provided to reduce voltage tran-
sients on the power supply.
Table 1 provides the component values and ref-
erence designations for two inhibi t board configurations.
J
CIRCUIT DESCRIPTION
In the inhibit process, current flows from ground to the Inhibit Component Board (Figure 3).
It is passed through a precision resistor, an inhibit
line, and another precision resistor to the -18-volt supply.
The amplitude of
the inhibit current is determined by the series resistance of the inhibit winding and two precision resistors,
During the memory clear process, current flows from ground to
the Inhibi t Component Board, through the inhibit line, and a preci sian re si stor to the -18-volt supply,
J
J
J
The amplitude of the clear current, determined
by the series resistance of the inhibit winding and one precision resistor, is
approximately equal to the sum of the X and Y drive line currents.
Provision is made on the board for additional resistors.
The clear
and inhibit currents through the memory-inhibit line can be reduced by shunt.;.
ing the inhibit winding with a resistor,
hibit line and reduce transients.
This also serves to terminate the in-
The currents through the inhibit line can be
increased by shunting one of the precision resistors.
SPECIFICA TIONS
Frequency of Operation
The frequency of operation is determined by the input currents.
Output Waveform Characteristics
The output waveform characteristics are determined by the input
currents,
Current Requirements
Inhibit Proces s
-18 V:
J
J
Nominal inhibit current of 270 rna
(270 rna) ,N, K
where N = number of bits inhibited
(0 to 12 per board)
K = duty cycle (40% full cycle, 80% split cycle)
- 6 V: None
-12 V: None
Clear Process
11
-18 V: Nominal clear current of 600 rna
(qOO rna)· N . K
where N = number of bits cleared
(0 to 12 per board)
K = duty cycle (1 00/0 max)
"
TABLE 1
COMPONENT VALUES AND REFERENCE DESIGNATIONS
2
Inhibit
Board
Word
Length
Rl
3 W, 10/0
IBI
128 to
2048
40
100
50
IB2
4096
40
100
33
R2
1/2 W, 50/0
R3
3 W, 10/0
R4
3 W, 10/0
40
,"
33
iJ
I
I
J
I
J
....,;::;::.:,:;.:.-1;-- R3A
I
J
,.;:.f. A"
R2A
RIA
R2B
RI B
---l!R~~~~;)
---;-1'-=,;:;;~-"'-'-:,~-~
R2C--rI~~
J
J
~;.;.-.·...;-I-R4B
~--;!-R3C
~~I--R4C
R2E-+~~
~~I:--R4E
R2F-~"=::::~~
RIF -.....;-~:=- _ _ _'
R2G
RIG
--!..~-==~
-~~~:-:_.~~__
R2H---f~~;
RIH-....;-~~
J
R2"
--;.0.;;..;;.;;..;.;0":::::::;:,:;
RI"
-~--='::~:"""'
R2K
RIK
R2L -~.......
RIL -----~~_:--~¥::t-
J
J
J
J
~~I~-R4D
~~I~-R3E
,-,--'
J
;';'-:~I-R3D
RID --+-~~-:.~_,
RI E --;.o.~~"""
J
J
J
----'~-+-- R3B
RIC--;-~~R2D---;.,;..-;;;.;;;;.~~
J
I
(~:r
~~I;---R4A
-..,.,;;,~.;:---
R3F
~~:"'--R4F
-=:.,...:.,..;...;...--R3G
~~--R4G
-;::..~--R3H
~~--R4H
-;:::.;..;.;.,.,,....;--R3"
~~--R4"
----'=...,.-;--
R3K
~--'-T--R4K
---:~~-
R3L
==-.,;..-.- R4L
---=;;..;.;...- R3M
:~: . . -~.;:;f~;fi.:.!:f~~,0!~~,. ~);g;;t:·~·~~~~=.~=~.o.;.;.;,.
-::U
.;...!
Figure 1.
Inhibit Component Board, Model IB
(Resistor s and Capacitor s)
Part s Location
3
r-'
I
I
i
53
50
49
4--i-....
2--~jj;~~~~~~~~
I
8
6----lr}~t5~~
I'
3 - - - i -...1IiiIL,&.i,)
12-~·.Y:bL;: . .
10
9
16
~~~-II
54
14--~~t~~~~~~~~
i'
~,:;,--;---15
13
20
18~
17
I
24
I.
22--,"'fK
i'
:~+
26~1'
25
32
.
I
--'.Mr
30
.,?,~
29--'.,,'3)'
I
-",,,,,
36--1-1~",
34---r-',
33
I'
40-r
3S--r,
37
I .. ~~~r
44
I
:t\hl:'" , ~-'-"'-
~'.< ,~,""~ ~ ~~_A~~
42~1--fl:~··;;;;;;;;,~:~~,;;;-~,J
4I'hlb#;..t'
I
.~lw':
-'
~v.:~
•
43
::-"'::I--.""'":I,-$,-n';,,,,~_.
I
.', ....... ,
45 --;I---...·~'~
'!.l
~~-i ~:~;~':;::~~;:::::mf~:; ':,':n~~~d~ <;:r-:;-56
Figure 2.
Inhibit Component Board, Model IB
(Pin Connections)
Part s Location
i'
4
]
]
J
]
]
CIRCUIT A
R2
RI
INHIBIT
DRIVER INPUT
R3
A
CI
CLEAR INPUT A
+ 22UF
J
J
J
J
J
J
INHIBIT {
WINDING A
INPUT
3
R4
}------------4I---\NY---+-(
I
I
CIRCUIT B
*
CIRCUIT E
*
CIRCUIT H
*
CIRCUIT L
1
.J
*
CIRCUIT F
@-i
@-J
*
-,
t::Lr----,
.J
.J
~----,
I
G-i
~
~
~
1
CIRCUIT G
*
1
CIRCUIT J
*
1
Gh____
C0---:
-,
I
@-i
~
I
I
@--,
I
..J
I
J
I
...J
1
*
I
..J
_...1
e---r
CIRCUIT C
*
1
1
CIRCUIT D
J
GND
@--I
1
CIRCUIT M*
I
1
9--L
..J
I
1
I
~
* SAME AS CIRCUIT A
I
.J
]
:J
]
J
Figure 3.
Inhibit Component Board, Model lB·
Schematic Diagram
5/6
J
INHIBIT COMPONENT BOARD, MODEL IB-I, PARTS LIST
n
J
J
REF.OESiG.
ASSY LEVEL
DESCRIPTION
3C DWG NO.
AJeJCJOJEJFJ
CI, C2
CAP, fxd: elec TANTalum:
Rl, R4
RES, fxd, wire wound:
R2
RES, fxd, comp:
R3
RE.S, fxd, wire wound:
22
J.lf
±20%, 35 VDC
40 ohms ±l%, 3W
100 ohms ±5% . 1/2 W
50 ohms ±1%, 3W
930 217 023
932 206 410
932 004 025
932 206 411
J
1L..J
I
LJ
'1
i
l~
l
l.-J
J
'I
,J
7/8
INHIBIT COMPONENT BOARD, MODEL IB-2, PARTS LIST
ASSY LEVEL
DEseRI PTION
REF. DESIG.
r-"!
,
LJ
J
~J
3C
DWG NO.
AJSJCJOJEJFJ
C1, C2
CAP, fxd, elec TANTalum: 22
R1
RES, fxd, wire wound: 40 ohms ±l%, 3W
932 206 410
R2
RES, fxd, comp:
932 004 025
R3, R4
RES, fxd, wire wound:
J.1f
±200/0, 35 VDC
100 ohms ±50/0, 1/2 W
33 ohms ±10/0, 3W
930 217 023
932 206 440
J
I
/ ,
J
J
]
'1
i
LJ
lu
..-,
I
ro
I
I
L-J
9
I
I
,.-J
MEMORY NORMALIZER BOARD
GENERAL DESCRIPTION
The Memory Normalizer Board (Figure 1) contains a tilne delay circuit used to normalize control flip-flops in the memory system when power
J
is turned on (initially condition the flip-flops to a proper state).
It also has
power supply bypass capacitors and a protection diode to keep the -6-volt
supply from accidentally going more positive than ground.
CIRCUIT DESCRIPTION
The circuit (Figure 2) has a single form A relay contact and an RC delay in the coil circuit.
The relay is normally open and permits a positive cur-
rent source, clamped to ground, to be supplied to the output terminals. After
a delay of approximately 0.1 second (in which time all supply voltages become
~
stabilized), the relay contact closes and the voltage at the output terminals falls
to -6 volts.
Th is action frees the control flip-flops for normal operation.
SPECIFICATIONS
Input
DC supply voltage:
J
+12 V, -6 V, -18 V (two)
Output
Ground or -6 volts, directed through diodes.
Board will drive 8 unit loads.
The Memory Normalizer
Power Requirements
-18 V:
- 6 V:
o
o
+12 V:
48 rna
5 rna (current from supply)
28 rna
Total Power (Static Dissipation)
1.1 W
I
U
o
o
J
1
II
12
13
14
15
16
CR9
"
CR5
r-'
CR4
CR3
I'
CR6
CRa
10
R3
r-~
CR7
r-'
2
r-'
C5
7
CI
KI
r--'
3
C2
4
1'-'
5
C3
6
CRI
a
CR2
9
R2
r-'
C4
RI
Figure 1.
2
r'
Memory Normalizer Board, Model MN-1,
Parts Location
J
J
+12V
1
MN
+12V
2 J---...J
10-
1
LJ
II12-
R3
560
13-
14.
NODE
NORMALIZER
OUTPUTS
IS·
Its-
,..--------410 NODE
'l
lJ
1
u
NORMALIZER
OUTPUTS
~J
J
J
J
J
J
]
J
]
KI
+
GND
C5
100UF
CR3
8r--1~------~------~---4~----------~--------~~--------~--------~
GND
Figure 2. Memory Normalizer Board,
Model MN -1, Schematic and
Logic Diagram
3/4
MEMORY NORMALIZER BOARD, MODEL MN-l, PARTS LIST
I
IJ
l
J
,
LJ
..,
w
REF. OESIG.
ASSY LEVEL
3C DWG NO.
Cl
CAP, fxd, elec TANTalum:
47 !-if ± 20%, 20 VDC
930 217 025
C2,C3 C5
CAP, fxd, elec TANTalum:
100 1J.f ± 20%, 20 VDC
930 216 027
C4
CAP
fxd, elec TANTalum:
200 IJ.f ± 20%, 15 VDC
930 220 317
CRI
DIODE: Replacement type 1 N2069
943 303 001
CR2-CR9
DIODE: Replacement type IN695
943 023 001
I
~
oESCR I PTiON
AJSJCJOJEJFJ
.
Kl
RELAY:
Replacement type CR Z 1 056
Rl
RES, fxd, camp: 300 ohms ± 5%, lW
932 005 036
R2
RES, fxd, camp: 390 ohms ± 5%, 1/2 W
932 004 039
R3
RES, fxd, camp:
963 002 001
)
,.. ....1
J
"
J
560 ohms ± 5%, lW
932 005 043
J
----;
i
!
L--I
I
LJ
l
'I
~.1
J
5
]
MEMORY CLEAR DRIVER PAC, MODEL S-103
]
REF. DESIG.
]
]
]
]
ASSY LEVEL
OESCR I PTION
3C OWG NO.
AJSJ CJOJEJ FJ
el
CAP, fxd, lTIica dielec:
C2,CS
CAP, fxd, ceralnic dielec:
C3
CAP, fxd, ITlica dielec:
C4,C6
CAP, fxd, plastic dielec:
C7
CAP, fxd, ITlica dielec: 680 pf ±S%, 100 VDC
930 011 149
C8
CAP, fxd, ITlica dielec:
930006151
C9
CAP, fxd, plastic dielec:
O. 1 jJ-f ± 1 00/0, 100 VDC
930 307 239
~10
CAP, fxd, ELEC Trol ytic:
22 jJ-f ±200/0, 3S VDC
930217023
K::l1, C12
CAP, fxd, ELECTrolytic:
~Rl,CR2, CR4,
DIODE:
ReplacelTIent Type 1 N69 5
943 023 00 1
DIODE:
ReplacelTIent Type 1 N816
943 105 001
~RI0
DIODE:
Replacement Type IN70S
943 102 002
~RI8-CR23
DIODE:
Replacement Type 1 N2069
943 303 001
~1,R8,R13
RES, fxd, COlTIP:
8.2 K ±50/0, 1/2 W
932 004 071
R2
RES, fxd, COITlP:
2~
932 004 059
R3
RES, fxd, comp:
30 K ±S%, 1/2 W
932 004 084
R4
RES, fxd, COlTIP:
16 K ±S%, 1/2 W
932 004 078
R5
RES, fxd, COITlP:
7 SO ohlTI s ±50/0, 1/2 W
932 004 046
R6
RES, fxd, comp:
18 K ±S%, 1/2 W
932 004 079
R7,R17
RES, fxd, COlTIP:
6.8 K ±50/0, 1/2 W
932 004 069
R9
RES, fxd, film:
4. 02 K ±20/0, 1/2 W
932 r03 230
RIO
RES, fxd, comp:
220 K ±S%, 1/2 W
932 004 lOS
R 11
RES, fxd, comp:
200 K ±S%, 1/2 W
932 004 104
R12
RES, fxd, COITlP:
10K ±S%, 1/2 W
932 004 073
1000 pf ±S%, 100 VDC
0.01 jJ-f GMV, 7S VDC
91 pf ±S%, 100 VDC
6800 pf ±100/0, 100 VDC
820 pf ±S%, 100 VDC
2. 2 jJ-f ±200/0, 20 VDC
930 011 lS3
930 lS6 001
930 011 126
930 307 227
930 216 017
]
J
:J
J
]
CRS,CR8,CR 9
CRll-CRIS,
CR17
CR3, CR6, CR7
CRi6
:J
J
J
]
l,-.J
J
J
7 K ±50/0, 1/2 W
7/8
--
l___ i
MEMORY CLEAR DRIVER PAC, MODEL S-103 (Cant)
REF. DESIG.
ASSY LEVEL
DESCRIPTION
3C DWG NO.
AJSJCJDJEJFJ
R14
RES, fxd, camp:
3.9K±5%, 1/2 W
932 004 063
RIS
RES, fxd,
1.3 K ±S%, 1,/2 W
932 004 OS2
R16
RES, £Xd, camp:
R18
RES, fxd, camp:
470 ohms ±S%, 1/2 W
932 004 0'41
I R19
RES, fxd, camp:
36 K ±S%, 1/2 W
932 004 086
RES, fxd, camp:
1 K ±S%, 1/2 W
932 004 049
RES, fxd, caITlp:
27 ohms ±5%, lW
932 OOS 011
]
~
..J R20, R22
r-'1
R21
camp:
20 K ±5%, 1/2 W
932 004 080
J
I
L.J QI-Q3
Q4
TSTR:
Replacement Type 2N404A
943 S19 002
TSTR:
Replacement Type 2N388
943 507 001
TSTR:
Replacement Type CRP-1732A
943 522 001
~.
QS
l
L-J
I
LJ
I
]
.J
~l
I
....J
I
'--'
9
J
MEMORY CLEAR DRIVER PAC, MODEL S-103
GENERAL DESCRIPTION.
The Memory Clear Driver PAC, model
S-103, (Figures land 2) contains a monostable multivibrator, a pulse arnplifier,
and four identical output stages.
The PAC can provide up to 500 rna of clear
current to each of 24 inhibit windings in a magnetic core memory system.
The
clear current provided by the PAC resets all cores to the ZERO state.
CIRCUIT FUNCTION.
The Memory Clear Driver PAC (Figure 3)
functions quiescently with Q2 on and Q1, Q3, Q4, and Q5 off.
The application
of a positive input pulse triggers the multivibrator which turns off Q2 and turns
on Ql, Q3, Q4, and Q5.
The negative pulse produced at the assertion output turns
on the NAND gate (Q3).
The positive puls.e at the collector of Q3 turns on the
Q4 transistors, which in turn saturate the Q5 output transistors.
SPECIFICA TIONS
Frequency of Operation
The maximum operating frequency is 5 KC.
lllust not be applied during the normal memory cycle.
A memo:r;y clear pulse
After a clear pulse is
applied, no other pulses s.hould be applied to the system for 200 J-Lsec.
This
precaution will provide the required recovery time for the power supply.
Not
Lnore than 20 clear pulses should be applied in any 1 O-msec period.
Input
The input to the multivibrator is a -6-volt to O-volt pulse with a maxin1.um rise tinle of 1 J-Lsec.
The trigger input must remain positive at least
1.5 I-lsec and ITlust be negative for at least 200 J-Lsec prior to triggering action.
The input loading is 2 W -loads.
Output
The multivibrator pulse width is nominally 30 J-Lsec.
The assertion
output will drive 2 W -loads, and the negation will dri ve 4 W -loads.
Each
clear output can provide up to 500 rna of clear current to a memory inhibit
winding.
The output transistors will tolerate an inductive back voltage of
50 volts.
I
~
1
Multivibrator Output Characteristics
a.
Assertion output
(neg~tive
i'
pulse measured from -0.6 volt to
-4.5 volts),
Rise time:
1.0 jJ.sec or O. 2 percent of pulse width, whichever
is longer,
Fall time:
b.
0.8 jJ.sec (typ)
Negation output.
R i s e ti me:
0, 5 jJ. sec (typ),
Fall time:
0.8 jJ.sec (typ).
i'
Circuit Delay
(Measured at 10% of voltage input to 10% of output current)
O. 5 jJ. sec (typ)
1. 0 jJ.sec (max)
Output Current Waveform Characteristics
Rise time:
10% to 90%
4 jJ.sec (typ)
5 jJ.sec (max)
Fall time:
90%' to 10%
1 0 jJ. sec (typ)
15 jJ.sec (max)
Power Requirements
Quiescent condition:
-18 V:
V:
- 6 V:
+ 12
18 V
23 rna
1 rna
6 rna (clamp current from power supply)
r -,
Output $tage on (duty cycle less than 20%)
-18 V:
24 rna (not including the 12 amperes of current
supplied at the inhibit component board)
+ 12 V: 120 rna
- 6 V: 864 rna (current into power supply)
r--'
2
J
R21A
RISD RISC RISS
RISA
RI7
CRI7
RI6 CRI6
R/5
RI4
R9
CRIQ
R5
RI2
RII
J
J
J
J
J
R7
eR9
r.RII
'---'--- CRI5
-------- R 13
--+--CRJ3
CR3
RS
R3
R2
RI
CRI
CR4
-CRS
J
-RIO
R6
J
J
J
J
J
J
J
J
]
R4
CRI2
CR2
CR21D
Figure 1.
CR23C
CR5
CRI4
Memory Clear Driver PAC, Model S-l 03, Parts Location
(Diodes and Resistors)
3
i[
'--'
Q4A
Q4B
Q4C
Q40
C9A
Q3
CaA
C7
CaB
C4
n
I
I
L-..
III
i
C5
C9B
C9C
cac
caD
]'
I,
L-
C3
Q2
]'
~
C90
CIOA
r-'
CIOB
CI2
Q50
Q5C
r--
CIOC
CII
ClOD
r--'
Q5B
Q5A
r-'
"
"
Figure 2.
4
Memory Clear Driver PAC, Model S-103, Parts Location
(Transistor s and Capacitor s)
]
CIRCUIT A
J
J
-18V
-18V
RI
8.2K
-18V
--18V
R7
6.8K
-18V
RI3
8.2K
J
7
RI4
3.9K
CRI7
RI7
6.8K
-6V
C7
680PF
NEGATION
OUTPUT
CRI2
r
I
I
I
RI9
36K
CLEAR
OUTPUTS
-6V
10 ASSERTION
OUTPUT
C3
91PF
J
J
-18V
CRI3
CRI5
RI5
1.3K
-6V
SEPARATE
GROUND
CRII
]
LEAD
+12V
R9 .
4.02K'
R2
2.7K
R3
30K
]
RII
200K
+12V
]
-18V
l
,J
r
RI2
10K
I
I
R4
16K
]
CLEAR
OUTPUTS
*
CLEAR
OUTPUTS
CIRCUIT 0*
CLEAR
OUTPUTS
I
CRI4
CR4
s*
CIRCUIT
+12V
R5
750
I
L
R6
18K
r
I
]
I
C2
O.OIUF
CIRCUIT C
C6
6800PF
'I
G)-18V
I
l.J
J
CLEAR
INPUT CR8
--------------~
-18V
J
J
1r-+---0
8 ~~--~------------------------------------------~
RIO
220K·
3
CII
2.2UF
CI2
r---I
+12V
I
~
2.2uFI·
1..-------+----0
-r_+
-6V
I
GND
I
* SAME
AS
CIRCUIT
A
L
Figure 3. Memory Clear Driver PAC,
Model S-103, Schematic Diagram
5/6
TRANSFER GATE PAC, MODEL S-169
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J
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J
GENERAL DESCRIPTION.
The Transfer Gate PAC, Model S-169,
Figures I and 2, contains 12 identical 2-input NAND gates.
The PAC is de-
signed to perform parallel loading of regi sters with a minimum of logic and
exte rnal conne ctions.
CIRCUIT FUNCTION.
The Transfer Gate PAC contains 12 NAND gates,
Figure 3, arranged in four groups.
4-gate group.
There is one 2-gate, two 3-gate, and one
Each group of gates has one common prewired input and one free
input to each gate.
The NAND gate circuits are standard; if both inputs are a
ONE (-6 V), the output is a ZERO (O V).
If either input goes to ZERO, the out-
put becomes a ONE.
The common inputs can be externally connected to transfer a maximum of 12 bits of data sirnultaneously.
With this arrangement, the data to
be transferred is connected to the individual input of each gate and a strobe
input is applied to the comITlon input.
Additional S-169 PACs ITlay be used to
expand the data bit transfer.
SPECIFICA TIONS.
Frequency of Operation
Input Loading
J
Indi vidual input s:
ComITlon inputs:
o
1 unit load per
circuit
1 unit load per
gate
Circuit Delay (ITleasures at -3 V
averaged over two stages)
O. 1 ~sec (max)
O. 06 ~sec (typ)
Output Drive Capability
7 unit loads and 400 pf stray
capacitance
Total Power
DC to 1 MC (ITlax)
Output Waveform Characteristics
Rise tirne:
Fall time:
O. 1 ~ sec (typ)
O. 1 5 ~ sec (typ)
Curr ent R equir ernents
-18 V:
- 6 V:
+ 12
V:
120 ITla
63 rna (reverse current
into supply)
8 rna
Handl e Colo r Code
None
2.2 W
Polarization
J
J
J
None
1
r-1
L-..
r
RIB
R4B
RIF
R4F
R3F
R3B
R2B
QIA
QIB
R2A
R3A
RIA
R4A
RIJ
R4J
R3J
R2J
QIJ
R2G
R3G
RIG
R4G
RIH
R4H
R3H
R2H
QIK
R2K
R3K
QIH
QIC
R2C
R3C
RIK
R4K
RIL
R4L
RIC
R4C
RID
R40
R3L
QIL
QIM
R3D
QID
QIE
R2L
R3M
RIM
R4M
R2D
R3E
RIE
R2M
R2E
Figure 1.
2
R2F
QIG
QIF
R4E
Transfer Gate PAC, Model 5-169, Parts Location
(Resistors and Transistors)
r
l-..
I'
i'
l-..
i'
r-
r--'
r-'
r'- ,
r --,
C3
CRIB
CIS
CR3B
C2
CRIF
CIF
CR3F
CR4F
CR4B
CR2B
CR3A
CR2A
CR4A
CRIA
CIA
CIJ
CRIJ
CR3J
CR4J
CRIH
CR3H
CR4H
CR2J
CR2H
CR4K
CIK
CR3K
CR2K
CRIK
CR4C
CIL
CR4L
CRIL
CR3L
CR2L
CR4M
CIM
CR3M
CR2M
CRIM
Figure 2.
CR2F
CR3G
CR2G
CR4G
CRIG
CIG
CIH
CIC
CR3C
CR2C
CRIC
CIO
CR4D
CRID
CR3D
CR2D
CR4E
CIE
CR3E
CR2E
CRIE
Transfer Gate PAC, Model 5-169, Parts Location
(Capacitors and Diodes)
3
]
]
]
]
]
PARALLEL TRANSFER GATE PAC, MODEL S-179
GENERAL DESCRIPTION.
The Parallel Transfer Gate PAC, Model
S-179 (Figures 1 and 2), contains twelve 2-input NAND gates without collector
resistors and clamp diodes; one 2-gate, two 3-gate, and one 4-gate group.
These circuits provide a facility for connecting the NAND gates in parallel
without decreasing the output drive capability (fanout).
levels, pulses, or with a combination of both.
The gates operate with
The PAC is designed to perform
a variety of functions which includes multiplexing of parallel groups of bits;
]
parity generation; decoding; and etc.
These functions are performed with
groups of NAND gates connected in parallel.
NAND gates with parallel collectors perform logic functions as
follows:
J
A
r--------.----~E
B
]
c
1
o
L..J
E
J
J
CIRCUIT FUNCTION.
twelve
circuit.
v CD
The Parallel Tr-ansfer Gate PAC contains
gates (Figure 3),
NAND
= AB
arranged in four groups, and one load
Each group has one common, pre-wired input and one free input
to each gate.
The NAND gate circuits are standard with the exception of
the common load circuit; if both inputs are a ONE (- 6 V), the output is a
ZERO (O-V).
If either input goes to ZERO, the output becomes a ONE.
The load circuit contains a pull-up resistor (to -lBV) anda clamp
J
J
diode (to -6 V).
Each gate or group of gates used on the PAC must have
the load circuit or a similar circuit connected to the output.
The load
circuit connected to the output of the parallel gate groups does not affect
the fanout.
If the inputs are such that only one transistor is conducting, the
J
J
1
output will be at zero volt.
The maximuITl drive capability, regardless
of how many collector outputs are jumpered in parallel, is 7 unit loads as
shown in the following illustration.
LOAD CIRCU IT
-lev
L..
-6V
OUTPUT
r-
-
r-'
'-
The common inputs can be externally connected to transfer a maximum of twelve bits of data simultaneously.
With thi s arrangement, the data
to be transferred is connected to the free input of each gate and a strobe input
is applied to the COITlITlon input.
the data bi t transfer.
2
Additional S-179 FACs may be used to expand
I
SF ECIFICA TIONS
Input Loading
Frequency of Operation
F lee inputs; 1 unit load per circuit
COITuTIon inputs: 1 unit load per gate
DC to 1 MC (ITlax)
Output Waveforrn Characteristics
Circuit Delay (rneasured at -3 V
averaged over two stages)
o. 1 p.sec (rnax)
O. 06 p. sec (typ)
Output D 1 i ve Capability
7 unit loads and 400 pf stray capacitance
Rise time:
Fall tirne:
o.
1 P. sec (typ)
O. 1 5 p. sec (typ)
Current Requirernents
-18 V:
- 6 V:
+ 12 V:
35 rna
o rna
8 rna
I
I~
3
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