DM74LS390 Dual 4 Bit Decade Counter 74390
User Manual: 74390
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© 2000 Fairchild Semiconductor Corporation DS006433 www.fairchildsemi.com
August 1986
Revised March 2000
DM74LS390 Dual 4-Bit Decade Counter
DM74LS390
Dual 4-Bit Decade Counter
General Description
Each of these monolithic circuits contains eight master-
slave flip-flops and additional gating to implement two indi-
vidual four-bit counters in a single package. The
DM74LS390 incorporates dual divide-by-two and divide-
by-five counters, which can be used to implement cycle
lengths equal to any whole and/or cumulative multiples of 2
and/or 5 up to divide-by-100. When connected as a bi-qui-
nary counter, the separate divide-by-two circuit can be
used to provide symmetry (a square wave) at the final out-
put stage. The DM74LS390 has parallel outputs from each
counter stage so that any submultiple of the input count fre-
quency is available for system-timing signals.
Features
■Dual version of the popular DM74LS90
■DM74LS390...individual clocks for A and B flip-flops
provide dual ÷ 2 and ÷ 5 counters
■Direct clear for each 4-bit counter
■Dual 4-bit version can significantly improve system den-
sities by reducing counter package count by 50%
■Typical maximum count frequency...35 MHz
■Buffered outputs reduce possibility of collector commu-
tation
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Order Number Package Number Package Description
DM74LS390M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS390N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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DM74LS390
Function Tables
BCD Count Sequence
(Each Counter) (Note 1)
Bi-Quinary (5-2)
(Each Counter) (Note 2)
H = HIGH Level
L = LOW Level
Note 1: Output QA is connected to input B for BCD count.
Note 2: Output QD is connected to input A for Bi-quinary count.
Logic Diagram
Count Outputs
QDQCQBQA
0LLLL
1LLLH
2LLHL
3LLHH
4LHLL
5LHLH
6LHHL
7LHHH
8HLLL
9HLLH
Count Outputs
QAQDQCQB
0LLLL
1LLLH
2LLHL
3LLHH
4LHLL
5HLLL
6HLLH
7HLHL
8HLHH
9HHLL
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DM74LS390
Absolute Maximum Ratings(Note 3)
Note 3: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Note 4: CL = 15 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V.
Note 5: CL = 50 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V.
Note 6: The symbol (↓) indicates the falling edge of the clear pulse is used for reference.
Note 7: TA = 25°C and VCC = 5V.
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Note 8: All typicals are at VCC = 5V, TA = 25°C.
Note 9: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 10: ICC is measured with all outputs OPEN, both CLEAR inputs grounded following momentary connection to 4.5 and all other inputs grounded.
Supply Voltage 7V
Input Voltage
Clear 7V
A or B 5.5V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range −65°C to +150°C
Symbol Parameter Min Nom Max Units
VCC Supply Voltage 4.75 5 5.25 V
VIH HIGH Level Input Voltage 2 V
VIL LOW Level Input Voltage 0.8 V
IOH HIGH Level Output Current −0.4 mA
IOL LOW Level Output Current 8 mA
fCLK Clock Frequency (Note 4) A to QA025
MHz
B to QB020
fCLK Clock Frequency (Note 5) A to QA020
MHz
B to QB015
tWPulse Width (Note 4) A 20
B25 ns
Clear HIGH 20
tREL Clear Release Time (Note 6)(Note 7) 25↓ns
TAFree Air Operating Temperature 0 70 °C
Symbol Parameter Conditions Min Typ Max Units
(Note 8)
VIInput Clamp Voltage VCC = Min, II = −18 mA −1.5 V
VOH HIGH Level VCC = Min, IOH = Max 2.7 3.4 V
Output Voltage VIL = Max, VIH = Min
VOL LOW Level VCC = Min, IOL = Max 0.35 0.5
Output Voltage VIL = Max, VIH = Min V
IOL = 4 mA, VCC = Min 0.25 0.4
IIInput Current @ Max VCC = Max, VI = 7V Clear 0.1
Input Voltage VCC = Max A 0.2 mA
VI = 5.5V B 0.4
IIH HIGH Level VCC = Max Clear 20
Input Current VI = 2.7V A 40 µA
B80
IIL LOW Level VCC = Max, VI = 0.4V Clear −0.4
Input Current A −1.6 mA
B−2.4
IOS Short Circuit Output Current VCC = Max (Note 9) −20 −100 mA
ICC Supply Current VCC = Max (Note 10) 15 26 mA
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DM74LS390
Switching Characteristics
at VCC = 5V and TA = 25°C
RL = 2 kΩ
Symbol Parameter From (Input) CL = 15 pF CL = 50 pF Units
To (Output) Min Max Min Max
fMAX Maximum Clock A to QA25 20 MHz
Frequency B to QB20 15
tPLH Propagation Delay Time A to QA20 24 ns
LOW-to-HIGH Level Output
tPHL Propagation Delay Time A to QA20 30 ns
HIGH-to-LOW Level Output
tPLH Propagation Delay Time A to QC60 81 ns
LOW-to-HIGH Level Output
tPHL Propagation Delay Time A to QC60 81 ns
HIGH-to-LOW Level Output
tPLH Propagation Delay Time B to QB21 27 ns
LOW-to-HIGH Level Output
tPHL Propagation Delay Time B to QB21 33 ns
HIGH-to-LOW Level Output
tPLH Propagation Delay Time B to QC39 51 ns
LOW-to-HIGH Level Output
tPHL Propagation Delay Time B to QC39 54 ns
HIGH-to-LOW Level Output
tPLH Propagation Delay Time B to QD21 27 ns
LOW-to-HIGH Level Output
tPHL Propagation Delay Time B to QD21 33 ns
HIGH-to-LOW Level Output
tPHL Propagation Delay Time Clear to Any Q 39 45 ns
HIGH-to-LOW Level Output
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DM74LS390
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
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DM74LS390 Dual 4-Bit Decade Counter
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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