74HC/HCT373 Octal D Type Transparent Latch; 3 State 74HCT373

User Manual: 74HC/HCT373 Octal D-type transparent latch; 3-state La Biblioteca de los 8 bits

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INTEGRATED CIRCUITS

DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT373
Octal D-type transparent latch;
3-state
Product specification
File under Integrated Circuits, IC06

September 1993

Philips Semiconductors

Product specification

Octal D-type transparent latch; 3-state

74HC/HCT373

input and an output enable (OE) input are common to all
latches.

FEATURES
• 3-state non-inverting outputs for bus oriented
applications

The “373” consists of eight D-type transparent latches with
3-state true outputs. When LE is HIGH, data at the Dn
inputs enters the latches. In this condition the latches are
transparent, i.e. a latch output will change state each time
its corresponding D-input changes.

• Common 3-state output enable input
• Functionally identical to the “563”, “573” and “533”
• Output capability: bus driver
• ICC category: MSI

When LE is LOW the latches store the information that was
present at the D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE. When OE is LOW, the
contents of the 8 latches are available at the outputs.
When OE is HIGH, the outputs go to the high impedance
OFF-state. Operation of the OE input does not affect the
state of the latches.

GENERAL DESCRIPTION
The 74HC/HCT373 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.

The “373” is functionally identical to the “533”, “563” and
“573”, but the “563” and “533” have inverted outputs and
the “563” and “573” have a different pin arrangement.

The 74HC/HCT373 are octal D-type transparent latches
featuring separate D-type inputs for each latch and 3-state
outputs for bus oriented applications. A latch enable (LE)
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

TYPICAL
SYMBOL

PARAMETER

CONDITIONS

UNIT
HC

tPHL/ tPLH

propagation delay

CL = 15 pF; VCC = 5 V

Dn to Qn

12

14

ns

LE to Qn

15

13

ns

3.5

3.5

pF

45

41

pF

CI

input capacitance

CPD

power dissipation capacitance per latch

notes 1 and 2

Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC. For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.

September 1993

HCT

2

Philips Semiconductors

Product specification

Octal D-type transparent latch; 3-state

74HC/HCT373

PIN DESCRIPTION
PIN NO.

SYMBOL

NAME AND FUNCTION

1

OE

3-state output enable input (active LOW)

2, 5, 6, 9, 12, 15, 16, 19

Q0 to Q7

3-state latch outputs

3, 4, 7, 8, 13, 14, 17, 18

D0 to D7

data inputs

10

GND

ground (0 V)

11

LE

latch enable input (active HIGH)

20

VCC

positive supply voltage

Fig.1 Pin configuration.

September 1993

Fig.2 Logic symbol.

3

Fig.3 IEC logic symbol.

Philips Semiconductors

Product specification

Octal D-type transparent latch; 3-state

74HC/HCT373
FUNCTION TABLE
INPUTS
OPERATING
MODES
OE LE Dn

INTERNAL
LATCHES

OUTPUTS
Q0 to Q7

enable and
read
register
(transparent
mode)

L

H

L

L

L

L

H

H

H

H

latch and
read register

L
L

L
L

l
h

L
H

L
H

latch register
and disable
outputs

H
H

X
X

X
X

X
X

Z
Z

Notes

Fig.4 Functional diagram.

1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the
HIGH-to-LOW LE transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the
HIGH-to-LOW LE transition
X = don’t care
Z = high impedance OFF-state

Fig.5 Logic diagram (one latch).

Fig.6 Logic diagram.

September 1993

4

Philips Semiconductors

Product specification

Octal D-type transparent latch; 3-state

74HC/HCT373

DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)

TEST CONDITIONS

74HC
SYMBOL

PARAMETER

+25

−40 to +85

−40 to +125

min. typ. max. min. max. min.

UNIT V
WAVEFORMS
CC
(V)

max.

tPHL/ tPLH

propagation delay
Dn to Qn

41
15
12

150
30
26

190
38
33

225
45
38

ns

2.0
4.5
6.0

Fig.7

tPHL/ tPLH

propagation delay
LE to Qn

50
18
14

175
35
30

220
44
37

265
53
45

ns

2.0
4.5
6.0

Fig.8

tPZH/ tPZL

3-state output enable time
OE to Qn

44
16
13

150
30
26

190
38
33

225
45
38

ns

2.0
4.5
6.0

Fig.9

tPHZ/ tPLZ

3-state output disable time
OE to Qn

47
17
14

150
30
26

190
38
33

225
45
38

ns

2.0
4.5
6.0

Fig.9

tTHL/ tTLH

output transition time

14
5
4

60
12
10

75
15
13

90
18
15

ns

2.0
4.5
6.0

Fig.7

tW

LE pulse width
HIGH

80
16
14

17
6
5

100
20
17

120
24
20

ns

2.0
4.5
6.0

Fig.8

tsu

set-up time
Dn to LE

50
10
9

14
5
4

65
13
11

75
15
13

ns

2.0
4.5
6.0

Fig.10

th

hold time
Dn to LE

5
5
5

−8
−3
−2

5
5
5

5
5
5

ns

2.0
4.5
6.0

Fig.10

September 1993

5

Philips Semiconductors

Product specification

Octal D-type transparent latch; 3-state

74HC/HCT373

DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.

INPUT

UNIT LOAD COEFFICIENT

Dn
LE
OE

0.30
1.50
1.00

AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)

TEST CONDITIONS

74HCT
SYMBOL

PARAMETER

+25

−40 to +85

−40 to +125

min. typ. max. min. max. min.

UNIT V
WAVEFORMS
CC
(V)

max.

tPHL/ tPLH

propagation delay
Dn to Qn

17

30

38

45

ns

4.5

Fig.7

tPHL/ tPLH

propagation delay
LE to Qn

16

32

40

48

ns

4.5

Fig.8

tPZH/ tPZL

3-state output enable time
OE to Qn

19

32

40

48

ns

4.5

Fig.9

tPHZ/ tPLZ

3-state output disable time
OE to Qn

18

30

38

45

ns

4.5

Fig.9

tTHL/ tTLH

output transition time

5

12

15

18

ns

4.5

Fig.7

tW

LE pulse width
HIGH

16

4

20

24

ns

4.5

Fig.8

tsu

set-up time
Dn to LE

12

6

15

18

ns

4.5

Fig.10

th

hold time
Dn to LE

4

−1

4

4

ns

4.5

Fig.10

September 1993

6

Philips Semiconductors

Product specification

Octal D-type transparent latch; 3-state

74HC/HCT373

AC WAVEFORMS

(1) HC : VM = 50%; VI = GND to VCC.
HCT : VM = 1.3 V; VI = GND to 3 V.

(1) HC : VM = 50%; VI = GND to VCC.
HCT : VM = 1.3 V; VI = GND to 3 V.

Fig.7

Fig.8

Waveforms showing the input (Dn) to output
(Qn) propagation delays and the output
transition times.

Waveforms showing the latch enable input
(LE) pulse width, the latch enable input to
output (Qn) propagation delays and the
output transition times.

(1) HC : VM = 50%; VI = GND to VCC.
HCT : VM = 1.3 V; VI = GND to 3 V.

Fig.9 Waveforms showing the 3-state enable and disable times.

The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC.
HCT : VM = 1.3 V; VI = GND to 3 V.

Fig.10 Waveforms showing the data set-up and hold times for Dn input to LE input.

September 1993

7

Philips Semiconductors

Product specification

Octal D-type transparent latch; 3-state
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.

September 1993

8

74HC/HCT373



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