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STD 7000
7703
Battery-Backed
CMOS RAM Card
USER'S MANUAL

o

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NOTICE
The information ir.l this document is provided for reference only. Pro-Log does not assume any
liability arising out of the application or use of the information or products described herein.
This document may contain or reference information and products protected by copyrights or
patents and does not convey any license under the patent rights of Pro-Log, nor the rights of
others.
Printed in U.S.A. Copyright © 1981 by Pro-Log Corporation, Monterey, CA 93940. All rights
reserved. However, any part of this document may be reproduced with Pro-Log Corporation
cited as the source.

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7703
Battery-Backed CMOS RAM Card
USER'S MANUAL

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FOREWORD
This manual explains how to use Pro-Log's 7703 Battery-Backed CMOS RAM Card. It is structured to reflect
the answers to basic questions that you, the user, might ask yourself about the 7703. We welcome your suggestions on how we can improve our instructions.

o

The 7703 is part of Pro-Log's Series 7000 STD BUS hardware. Our products are modular, and they are designed
and built with second-sourced parts that are industry standards. They provide the industrial manager with the
means of utilizing his own people to control the design, production, and maintenance of the company's
products that use STD BUS hardware.
Pro-Log supports its products with thorough and complete documentation. Also, to provide maximum
assistance to the user, we teach courses on how to design with, and to use, microprocessors and the STD BUS
products.
You may find the following Pro-Log documents useful in your work: Microprocessor User's Guide and the
Series 7000 STO BUS Technical Manual. If you would like a copy of these documents, please submit your
request on your company letterhead.

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Contents

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Page

Foreword ............................................................................................................................................................................ ii
Figures .................................................................................................................................................................................. iv
Section 1 - Purpose and Main Features ...................................................................................................... 1-1
Section 2 - Installation and Specifications ................................................................................................ 2-1
Introduction ........................................................................................................................................................................ 2-1
Mapped Card Addressing ................................................................................................................................................ 2-3
Alternatives to Soldered Wire Jumpers ...................................................................................................................... 2-3
Electrical and Environmental Specifications .............................................................................................................. 2-4
Mechanical Specifications . .............................................................................................................................................. 2-5

. Section 3 - Operation and Programming .................................................................................................... 3-1
Introduction .......................................................................................................................................................................... 3-1
Preparing the 7703 for Initial Use .................................................................................................................................. 3-1
Activati ng the 7703 ............................................................................................................................................................ 3-1
Saving Data When Power Fails ...................................................................................................................................... 3-1

o

7703 Power Monitor .......................................................................................................................................................... 3-3
Removing the 7703 Card without Losing Data .......................................................................................................... 3-3

Section 4 - Operating Software .......................................................................................................................... 4-1
Introduction .......................................................................................................................................................................... 4-1
Memory Addresses ............................................................................................................................................................ 4-1
Diagnostic Use ...................................................................................................~ ................................................................ 4-1
Shakedown (Confidence Level) Test ............................................................................................................................ 4-2
Memory Maps ...................................................................................................................................................................... 4-2
Subroutine (MOVE BLOCK) .......................................................................................................................................... 4-5
Subroutine (-(HL)) ............................................................................................................................................................ 4-7
Subroutine (COMPARE BLOCK) .................................................................................................................................., 4-9
Subroutine (LOAD BLOCK) ........................................................................................................................................ 4-12
Subroutine (LOAD A
Subroutine (VERIFY

= D) .........................................:................................................................................................
A = D) ........................................................................................................................................

4-14
4-16

Program Listing (Subroutines) .................................................................................................................................. 4-19
Demonstration/Test Program .................................................................................................................................... 4-22
Program Listing (Shakedown Test) .......................................................................................................................... 4-27

Section 5 - Maintenance ........................................................................................................................................ 5-1
Reference Drawings .......................................................:.................................................................................................. 5-1

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Card Layout ........................................................................................................................................................................ 5-4
Read Timing Diagram ........................................................................................................................................................ 5-4
Address Decoding Circuit ................................................................................................................................................ 5-6

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Contents (continued)
Ch i p-Enab Ie Decod in g Ci rc uit ...................................................................................................................................... 5-8

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Data Bus Buffer Circuit ................................................................................................................................................ 5-10
Write-Control Circuit .................................................................................................................................................... 5-11
7703 Save Ci rc uit .......................... .................................................................................................................... ..............

5-12

Power Monitori ng Ci rcuit' ............................................................................................................................................ 5-12
Bac kup Battery C irc uit .................................................................................................................................... ............

5-14

Chang ing the Lith iu m Battery .................................................................................................................................... 5-14
Si g nal G Iossa ry ... ~ ................................~..................................... .... .... ........ ........ ................................ ........ ................ ....

5-15

7703 Internal Sig nals .................................................................................................................................................... 5-16
Return for Repair Procedures .................................................................................................................................... 5-17

Appendix A - Guidelines for Handling Lithium Batteries .............................................................. A-1

Figures
Page

. Figure

1-1

7703 Battery-Backed CMOS RAM Card ................................................................................................ 1-1

1-2

Block Diagram of 7703 Battery-Backed CMOS RAM Card ............................................................ 1-2

2-1

Installation of 7703 Card in STD BUS Card Rack .............................................................................. 2-1

2-2

Standard Configurations of 7703 Card (250ns CMOS RAM) .......................................................... 2-2

2-3

Mappi ng the 7703 Card .............................................................................................................................. 2-2

2-4

Location of RAM Pairs on 7703 Card .................................................................................................... 2-3

2-5

Operating Limits of Electrical and Environmental Parameters for 7703 Card .......................... 2-4

2-6

STD BUS Electrical Specifications Over Recommended Operating Limits ................................. 2-5

2-7

Edge Connector Pin List for 7703 Card ................................................................................................ 3-2

3-1

Flowchart Showing Power Failure Procedure for 7703 Card .......................................................... 3-3

3-2

Flowchart Showing Insertion and Removal Procedure for 7703 Card ........................................ 3-3

4-1

Index of Subroutines for 7703 Card ........................................................................................................ 4-1

4-2

64K Memory Map for 7703 Software Package .................................................................................... 4-2

4-3

16K Memory Map for 7703 Software Package ......................................................... _. __ .. _.... _......... _..... 4-3

4-4

One-Page Memory Map for 7703 Software Package ......... _._ .... _......... _._ ..... _..... _._ .. _.. _...... __ .... _... _._ .... 4-4

4-5

Flowchart-Subroutine (MOVE BLOCK) for 7703 ................... __ ........... _..... _._ ..... _.... _..... _.... _.... _._._._ .... 4-5

4-6
4-7

Register and Memory Allocation for 7703 Subroutine (MOVE BLOCK), Entry 1 and Return 1 4-6

4-8

Flowchart-Subroutine (-(HL)) for 7703 _....... _....................... _......................... _..... _._ .. _.. _....... _.... _._. __ .. _.. 4-7

4-9

Register and Memory Allocation for 7703 Subroutine {-(HL)), Entry 2 and Return 2 ... _..... _.. 4-8

4-10

Characteristics of 7703 Subroutine {-(HL)), Entry 2 and Return 2 .... _........... _.... _..... ___ .. _.... _.... _.. _.. 4-8

4-11

Flowchart-Subroutine (COMPARE BLOCK) for 7703 .... _.. _............ _........ _..... _..... _..... _............... _

4-12

Register and Memory Allocation for 7703 Subroutine (COMPARE BLOCK),
Entry 3 and Retu rn 3 '............................. _.................................................. _........................ _.... _... _...... _ 4-10

4-13

Characteristics of 7703 Subroutine (COMPARE BLOCK), Entry 3 and Return 3 .... _........ _..

iv

Characteristics of 7703 Subroutine (MOVE BLOCK), Entry 1 and Return 1 _.. _.. _.. _... __ .__ ._._._ ...... 4-'6

4-9

4-10

0'

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Figures (continued)
Figure

Page

4-14

Register and Memory Allocation for 7703 Subroutine (COMPARE BLOCK),
Entry 3 and Return 4 .......................................................................................................................... 4-11

4-15

Characteristics of 7703 Subroutine (COMPARE BLOCK), Entry 3 and Return 4 ................ 4-11

4-16

Flowchart-Subroutine (LOAD BLOCK) for 7703 .......................................................................... 4-12

4-17

Register and Memory Allocation for 7703 Subroutine (LOAD BLOCK), Entry 4 and Return 5 4-13

4-18

Characteristics of 7703 Subroutine (LOAD BLOCK), Entry 4 and Return 5 .......................... 4-13

4-19

Flowchart-Subroutine (LOAD A = D) for 7703 ............................................................................ 4-'14

4-20

Register and Memory Allocation for 7703 Subroutine (LOAD A = 0), Entry 5 and Return 6 4-'15

4-21

Characteristics of 7703 Subroutine (LOAD A = 0), Entry 5 and Return 6 ............................

4-22

Flowchart-Subroutine (VERIFY A = D) for 7703 .......................................................................... 4-16

4-23

Register and Memory Allocation for 7703 Subroutine (VERIFY A = 0), Entry 6 and Return 7 4-17

4-24

Characteristics of 7703 Subroutine (VERIFY A

4-25

Register and Memory Allocation for 7703 Subroutine (VERIFY A = D), Entry 6 and Return 8 4-18

4-26

Characteristics of 7703 Subroutine (VERIFY A

4-27

Program Listing for 7703 Subroutines .............................................................................................. 4-19

4-28

Memory Map for Shakedown (Confidence Level) Test -

4-29

Memory Map for Error Storage Locations 7703 (Shakedown Test) -

4-30

Flowchart-Demonstration/Test Program for 7703 ........................................................................ 4-25

4-31

Program Listing for 7703 Shakedown (Confidence Level) Test ................................................ 4-27

5-1

Schematic for 7703 (Reference Only) .................................................................................................... 5-2

5-2

Assembly for 7703 (Reference Only) ......................... ~ ............................................................................ 5-3

5-3

Locations and Functions of Main Components for 7703 .................................................................. 5-5

5-4

Read Timing Diagram for 7703 ................................................................................................................ 5-5

5-5

Address Decoding Circuit for 7703 ........................................................................................................ 5-7

5-6

Decoding the 7703's 64K Address Space .............................................................................................. 5-7

5-7

Chip-Enable Decoding Circuit for 7703 ................................................................................................ 5-8

5-8

CEX* Signal Selection of 1K Byte RAM Pair to be Accessed - 7703 ............................................ 5-9

5-9

Data Bus Buffer Circuit for 7703 .......................................................................................................... 5-10

5-10

Write-Control Circuit for 7703 .............................................................................................................. 5-11

5-11

Write;"'lnhibit Switches for 7703 ............................................................................................................ 5-11

5-12

Sequence Diagram for 7703's Data-Save Circuit ............................................................................ 5-12

5-13

Power Monitoring Circuit for 7703 ...................................................................................................... 5-13

= D),

4-15

Entry 6 and Return 7 .......................... 4-17

= 0), Entry 6 and

Return 8 .......................... 4-18

7703 ................................................ 4-23
7703 .......................... 4-24

5-14

Battery Backup Circuit for 7703 .......................................................................................................... 5-14

5-15

STD BUS Edge Connector Signals for the 7703 ............................................................................ 5-15

5-16

7703 Internal Signals ............. _................................................................................................................ 5-16

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SECTION 1
Purpose and Main Features

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Purpose

The 7703 Card (Fig. 1-1) provides up to 16,384 bytes of high-speed (250ns), nonvolatile static CMOS RAM. It
has a lithium battery backup that allows it to retain data for a minimum of two years; also, it generates a lowbattery status signal (with an LED indicator) that may be jumpered to the STD nonmaskable interrupt. (See
Fig. 1-2 for the block diagram.)
An onboard, memory-protected circuit in the 7703 monitors the +5V power and automatically generates a
memory-save signal before switching to the lithium battery backup.
Write-protect switches (4K blocks) are available in the 7703 for preserving critical data and for nonvolatile
program execution. The card decodes all 16 address lines. On-board jumpers permit mapping in any consecutive 4K, 8K, or 16K address blocks within 16K boundaries. All 7703 cards are shipped with starting address
COOO.
Main Features
• Up to 16,384 bytes of nonvolatile static CMOS RAM
• Available In five configurations: 1 K, 2K, 4K, 8K, and 16K bytes
• Lithium backup battery (guaranteed to give two years of data retention, five years typical)
• Automatic memory protection upon loss of +5V power
• Transportable without loss of data
• Write-inhibit switches (4K blocks)

o

• Temperature range: 0 to 55°C ambient
• Single +5V power requirements
• Full 64K address decoding
• Industry-standard multisourced components
• LED for replace-battery indication
• Instant operation (no battery-charging time required)
• Universal processor compatibility: Z80, 8085A, 6800, and others.

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Figure 1-1. 7703 Battery-Backed CMOS RAM Card.
1-1
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DATA BUS 00-07

......

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ADDRESS BUS A10-A1):

...
...

RD*
M EMRQ*

....
...

WR*

....
....

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:>

••

DATA
BUS
BUFFER

ADDRESS BUS AO-A9

ADDRESS
DECODE
AND
READ/
WRITE
CONTROL

16/

I

/

~~
-

.....

4/

.....

I

MEMORY
PROTECT
CIRCUIT
~r

ADDRESS
BUS
BUFFER

10/

I

-......

RAM
(4K)

10/ ...
7---..0'"

.. ,

RAM
(4K)

....
...
REPLACE
BATTERY
LED

~
NMIRQ*

.....
......

4

I

POWER
CONTROL
~

+

1-=-

-I

II

10/ ...

'

...

RAM
(4K)

,,....

~

4V
I

10/..
/~

RAM
(4K)

~8/..

.....
8/...
....

....... 8/....
~~

+5V

.....-

~~

WRITE
INHIBIT
SWITCHES

:>

..,...

....

4 11
I

~

/~

4 11
I

LITHIUM
BACKUP
BATTERY

--

7703

Active low-level logiC.

Figure 1-2. Block Diagram of 7703 Battery-Backed CMOS RAM Card.

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SECTION 2
Installation and Specifications

o
Introduction

The 7703 operates as part of an STD BUS card rack system. You can plug in directly into any card slot on the
motherboard, provided that the slot next to the battery is unoccupied. Optionally, you can plug the 7703 into a
7901 extender card, which in turn may be plugged into any vacant card slot on the motherboard; this configuration allows you to access the 7703 for testing or other purposes.
CAUTION

To prevent possible damage to your STD BUS system, make sure that power is off before inserting a
card into the card rack, or before removing a card from the card rack.
At installation, the 7703's card ejector must be positioned towards the top of the card rack (see Fig. 2-1).

SPACE PROVIDED BY
UNOCCUPIED SLOT TO
ACCOMMODATE BATTERY
SIDE OF CARD

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Figure 2-1. Installation of 7703 Card In STD BUS Card Rack.

2-1
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You may configure the 7703 to operate within anyone ofthefour 16K-byte address ranges available within the
addressable 64K memory space. The 7703's 16K range is subdivided into four 4K blocks. Any combination of
these 4K blocks may be enabled or disabled by appropriate jumpering of the 7703. You may order the 7703 in
any of the standard configurations shown in Fig. 2-2. The boundaries established for each of the standard
configurations for the 1 K, 2K, 4K, 8K, and 16K options are sho",!n in Fig. 2-3.

PRODUCT
NUMBER
7703-1C
7703-2C
7703-4C
7703-8C
7703-16C
[1]

MEMORY
SIZE
1Kx8
2Kx8
4Kx8
8Kx8
16Kx8

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ADDRESS RANGE
AS SHIPPED [1]
COOO
COOO
COOO
COOO
COOO

-

C3FF
C7FF
CFFF
DFFF
FFFF

Address range may be remapped by the user, within any 16K
boundaries.

Figure 2-2. Standard Configurations of 7703 Card (250ns CMOS RAM).

ADDRESS RANGE
START

END

0000

03FF
07FF
OFFF

0000
0000
0000
0000

1FFF

4000
4000

43FF
47FF
4FFF
SFFF

SIZE
BLOCK
1K
2K
4K

RAM PAIRS
ENABLED
(Fig. 2-4)

SY TRACES
TO BE LEFT INTACT
OR CUT (X = CUT TRACE)
1 0
3 2

0

X

X

X

I

I

0-1

X

X

X

I

I

0-3

X

X

X

I

I

8K
16K

0-7

X

X

I

I

I

0-15

I

I

I

I

I

1K

0

X

X

X

I

I

0-1

X

X

X

I

I

0-3

X

X

X

I

I

0-7

X

X

I

I

I

7FFF

2K
4K
8K
16K

0-15

I

I

I

I

I

8000
8000
8000
8000

83FF
87FF
8FFF

1K
2K
4K

0

X

X

X

I

9FFF

8000

BFFF

8K
16K

COOO
COOO
COOO
COOO
COOO

C3FF

4000
4000
4000

3FFF

C7FF
CFFF
DFFF
EFFF

1K
2K
4K
8K
16K

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0-1

X

X

X

I

0-3

X

X

X

I

I

0-7

X

X

I

I

I

0-15

I

I

I

I

I

0

X

X

X

I

I

0-1

X

X

X

I

I

0-3

X

X

X

I

I

0-7

X

X

I

I

I

0-15

I

I

I

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Figure 2-3. Mapping the 7703 Card.
2-2

SX JUMPER
POSITION
2
1 0
3

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Mapping Card Addressing

Figure 2-4 shows the location of the SX jumpers, the SY jumpers, and the RAM pairs on the 7703 card. The
CMOS RAMs are NEC 6514-2, with 250nsaccess time. Each RAM device is 1Kx4 bits; therefore, each RAM pair
provides 1Kx8 bits of memory. Up to 32 devices may be placed on the 7703, allowing a maximum of 16K bytes
on one card. Four 7703 cards provide a full backup of 64K bytes of memory.
Alternatives to Soldered Wire Jumpers

If you anticipate making frequent changes in your 7703 memory address mapping, you may replace the wire
jumpers for SX and SY with 0.025 in. (0.635 mm) square posts. These posts are available individually or in
single or double strips that correspond to the 0.001 in. (0.025 mm) grid jumper-pad spacing. You then connect
the posts by wirewrap or by jumper clips. Be sure you check the height that the posts extend above the board to
insure they do ~ot interfere with an adjacent card. The recommended wirewrap square post for SX and SY is
AMP No. 87215-1, or equivalent. The recommended jumper clip is AMP No. 530153-2, or equivalent.

RAM PAIR

RAM PAIR

0

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Select
16K Quadrant
U4
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74LS156

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~ ~ ~~

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a 4K block

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(8)

U33

(1)

U17

U25

(9)

U34

U10

(2)

U18

U26

(10)

U35

U11

(3)

U19

U27

(11 )

U36

U12

(4)

U20

U28

(12)

U37

U13

(5)

U21

U29

(13)

U38

U14

(6)

U22

U30

(14)

U39

U15

(7)

U23

U31

(15)

U40

SY
0

U24

U9

SX

0000

U16

Figure 2-4. Location of RAM Pairs on 7703 Card.

2-3
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Electrical and Environmental Specifications
.,

RECOMMENDED OPERATING LIMITS

PARAMETER

SYMBOL

MIN

TYP

MAX

MIN

MAX

UNIT

4.75

5.00

5.25

0

5.50

V

+25

+55

-20

+70

°C

95

0

95

%RH

Vcc

Supply voltage

TA

Free-air temperature

0

RH

Humidity

5

[1]

ABSOLUTE NONOPERATING LIMITS

-

[1] Noncondensing.

Figure 2-5. Operating Limits of Electrical and Environmental Parameters for 7703 Card.

SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

145

230

rnA

-

yr

Icc

Vcc supply current

-

-

Data retention

2

5

Battery life (shelf)

-

10

-

STD BUS output load

STD BUS input load

See Fig. 2-7

yr

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See Fig. 2-7
I

See Fig. 2-7

See Fig. 2-7

Figure 2-6. STD BUS Electrical Specifications Over Recommended Operating Limits.

o
2-4

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PIN NUMBER

PIN NUMBER

OUTPUT (LSTTL DRIVE)

OUTPUT (LSTTL DRIVE)

INPUT (LSTTL LOADS)

INPUT (LSTTL LOADS)

MNEMONIC

MNEMONIC

+5V

Vee

2

1

Vee

GROUND

GND

4

3

GND

6

5

-5V

+5V
GROUND
-5V

D7

1

55

8

7

55

1

D3

D6

1

55

10

9

55

1

D2

D5

1

55

12

11

55

1

D1

D4

1

55

14

13

55

1

DO

A15

1

16

15

1

A7

A14

1

18

17

1

A6

A13

1

20

19

1

A5

A12

1

22

21

1

A4

A11

1

24

23

1

A3

A10

1

26

25

1

A2

A9

1

28

27

1

A1

f'

A8

1

30

29

1

AO

I

RD*

1

32

31

1

WR*

MEMRO*

1

34

33

IORO*

MEMEX

1

36

35

IOEXP

MCSYNC*

38

37

REFRESH*

STATUS 0*

40

39

STATUS 1*

BUSRO*

42

41

BUSAK*

INTRO*

44

43

INTAK*

Ie

NMIRO*

20[1]

46

45

WAITRO*

PBRESET*

OUT

48

47

SYSRESET*

50

49

ClOCK*

52

51

AUX GND

54

53

AUX GND

AUX -V

56

55

AUX +V

CNTRl*
PCI

* Active low-level logic

IN

OUT

PCO

[1] Open-collector driver

Figure 2-7. Edge Connector Pin List for 7703 Card.

Mechanical Specifications

o

The 7703 Card meets all general mechanical specifications of the STD BUS except for battery height, which is
0.678 in. (16.9 mm) maximum above center line of the card thickness. It requires two card slots when mounted
in an STD BUS card rack - one additional open slot next to the component side for clearance of the lithium
battery.
The 7703 is shipped with a Series 7000 insulating shield covering the back side of the card, providing protection
for the CMOS chips on board.
2-5
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SECTION 3
Operation and Programming

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Introduction

This section explains how to operate the 7703. It also describes how to retain or preserve critical data on the
7703 if power fails, and how to remove the card without losing data. The 7703 operates under program control
from the CPU.
Preparing the 7703 for Initial Use
First select the jumpering required for use of your card configuration (1,2,4,8, or 16K) in the desired address
space (see Fig. 2-3). Also, check Fig. 2-3 to determine which SY traces to leave intact and which SY traces to
cut, to enable the various 4K byte memory segments. The last column in the figure specifies which of the SX
jumpers must be activated to select the desired 16K byte segment.

NOTE
SX-3 is default-jumpered on all 7703 boards shipped. This activates the 7703 for operations in
the upper 16K bytes of memory, starting at COOO.

After completing the memory mapping, install the battery activation jumper (jumper A), if it is not already
installed. (This jumper is located in grid 86 of the assembly drawing for the 7703, Fig. 5-2.)

o

To verify that standby memory current is within specification, connect a voltmeter across the test points TP1
and TP2. (These pOints are located in grids 87 and 86, respectively, of the assembly drawing forthe 7703, Fig.
5-2.) The voltage should read not more than 0.003 VDC, although the reading may be considerably less. A
proper reading at this point verifies that the lithium backup battery is properly installed and operating. If the
voltage is more than 0.003, disconnect the battery and return the card to the factory (see "Return for Repair
Procedures" in Section 5.) Set all the write-inhibit switches to the write-enable position (if required), in preparation for using the 7703 (see Section 4). (These switches are located in grid C4 of the assembly drawing for the
7703, Fig. 5-2.)

Activating the 7703
With the 7703 installed as outlined in Section 2:
1. Apply system power.
2. As part of system initialization, perform a memory-read operation or a memory-write operation to a
random address within the address space allocated to the 7703 card. The first time a memory-read or
memory-write operation is performed, memory-inhibit is removed. This "dummy" memory reference step
is extremely important to insure that the system memory is enabled before it is actually referenced. The
memory reference sets the operate flip-flop, which then enables the 7703 card operation. The operate flipflop is reset automatically at power-down and again at power-up to insure data integrity on the 7703.
Further details on this operation are provided in Section 5.
3. Use the write-inhibit switches to inhibit writing to any of the four 4K-byte blocks within the 7703 card
address space. (See Fig. 5-3 for the location of the write-inhibit switches.) Figure 2-3 shows the enablejumpering required for the onboard memory devices.
4. You may now use the software provided in Section 4 to exercise the 7703.

o

Saving Data When Power Falls
The most effective method to insure that essential data is saved in event of system power failure is to store such
data, including the system stack, on the 7703 card. However, the user must provide the hardware for monitoring
system power failure at his +5V power supply.
3-1

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The ci rcuitry and software for detecti ng system power fai lure should mon itor the user's power su pply to detect
any deviation from normal power behavior. The hardware must then generate a nonmaskable interrupt and
allow time for the interrupt software to execute its power failure data-save functions. The interrupt software
should allow all essential CPU register data to be stored and all address and data bus activity to be halted; this
must be accomplished before the system power falls below the minimum operating level. A flowchart for a
suggested power failure system is depicted in Fig. 3-1.

,"II

oil
',I"
I

POWER
FAILURE

NO

SYSTEM
EXECUTION

SAVE REGISTERS
AND ESSENTIAL
DATA IN THE
7703 CARD

o

HALT CPU

NO

POWER-ON
INITIALIZATION

ACTIVATE 7703
OPERATE STATUS.
RESTORE SYSTEM.

o
Figure 3-1. Flowchart Showing Power Failure Procedure for 7703 Card.

3-2

7703 Power Monitor
The 7703 has a "Low Vcc Detect" circuit on board. This circuit generates the LOW Vcc· signal, which is used to
inhibit memory if Vec falls below 4.S2V. The low Vcc detect circuit is used to save the 7703 card memory only,
not the entire system.

o

Removing the 7703 Card without Losing Data
To remove the 7703 card from the card cage without losing data, follow these steps:

1. Halt the CPU.
2. Set all write-inhibit switches to the inhibit position.

3. Power-down the system.
4. Gently remove the 7703 card from the rack. Now the stored data is protected by the card's battery backup.
You may now transport or store the 7703 card for future use. When you do use it again in another system, follow
the installation procedure detailed in Section 2.
Figure 3-2 flowchart shows how to remove and insert the 7703, insuring full data retention.

,--------

---,
7703
REMOVAL

I
NO

o

TURN
OFF
POWER

HALT
CPU

I
ACTIVATE
WRITE-INHIBIT
SWITCHES

INSERT 7703
IN
SYSTEM

I
POWER-DOWN
SYSTEM

POWER-UP
SYSTEM

I
REMOVE 7703
FROM
SYSTEM

DEACTIVATE
WRITE-INHIBIT
SWITCHES
(IF REQUIRED)

I
END
ACTIVATE 7703
OPERATE STATUS

I

I

L _ _ _ _J

BATTERY BACKED DATA
RETENTION TIME
(TWO YEARS MIN.)

EXECUTE
SYSTEM
PROGRAM

o
Figure 3-2. Flowchart Showing Insertion and Removal Procedure for 7703 Card.
3-3

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3-4

SECTION 4
Operating Software

o
Introduction

This section contains hardware-level subroutines fhat can be used for testing the 7703 CMOS RAM card or for
diagnosing malfunctions. They are designed with the user in mind and assume that your 7703 card can be
mapped for use in other than the first 16K quadrant (0000-3FFF). See Fig. 4-1 for the subroutine index.

FUNCTION

SUBROUTINE NAME

o

SEE FIGURES

(MOVE BLOCK)

Moves a block of data from one location in memory to a
user-specified location in RAM.

4-5, 4-6, 4-7

(-(HL»

Forms 2's complement of HL register pair contents.

4-8, 4-9, 4-10

(COMPARE BLOCK)

Compares two blocks of data in memory.

4-11,4-12, 4-13,
4-14,4-15
4-16,4-17,4-18

(LOAD BLOCK)

Loads a designated data word into a specified block of
RAM. (Used with (MOVE BLOCK) and (COMPARE
BLOCK) to test memory's retention and erasure of
particular bit patterns.)

(LOAD A = D)

Loads a specified block of memory with an address
equal to the data format.

4-19,4-20, 4-21

(VERIFY A = D)

Verifies that correct address is contained within specified
data byte. Used in conjunction with (LOAD A = D).

4-22, 4-23, 4-24,
4-25,4-26

( ) Denotes subroutine labels.

Figure 4-1. Index of Subroutines for 7703 Card.
The software in the section can be used without license from Pro-Log. It has been tested and is believed to be
correct; however, we do not represent it to be free from errors or possible copyright infringement, nor is it
represented as being appropriate for any specific application.
The subroutines are written in STD instruction mnemonics, using 8080 assembly codes. They will execute in
8080,8085, Z80, NSC 800, and other 8080 code-compatible microprocessor systems. The coding forms are
grouped at the end of this section (Fig. 4-27), following the subroutine specifications.
Flowcharts are included that do not refer to microprocessor characteristics; thus, they allow the routines to be
easily adapted to other types of microprocessors.
Individual subroutine specifications show memory requirements, entry requirements, and exit characteristics
for each path in the program. Timing and other necessary information are also provided.
Memory Addresses
Full memory addresses are shown in the subroutine documentation. They are the preferred addresses that
allow the subroutines to work with those provided for other Series 7000 STD BUS cards from Pro-Log. The
program addresses correspond to those used by the 7801 and 7803 processor cards for their onboard ROMI
EPROM and RAM devices.
If your system cannot use the memory addresses in the 7703's software package, simply change the memory
page addresses, as required, when loading these subroutines into your system. Memory addresses that must
be located in RAM are identified on the program coding forms. Other memory addresses shown are intended to
be ROM locations, but they may also be RAM locations.

o

Diagnostic Use
The error routines place .relevant data in the various registers and set an error flag. The memory location where
the error occurred and the erroneous data can be retrieved by examining the registers containing the error
information.
4-1

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Shakedown (Confidence Level) Test
A flowchart and an example program module are provided to demonstrate a sequence of operations you may
use to perform a quick shakedown or confidence level test of the 7703. (See Figs. 4-28 and 4-29 at the end of
. the section.)
Memory Maps
Figure 4-2 shows a 64K memory map, which is divided into 256-byte pages and gives the location of the 7703's
software package, the location of the stack, and the location of the 7703's memory space, as shipped (COOOFFFF).
.
PAGE

F

0

ox
1X
2X
3X
4X

o

5X
6X
7X

ax
9X
AX

ex
ex
ox
EX
FX

Figure 4-2. 64K Memory Map for 7703 Software Package.
4-2

o

Figure 4-3 displays a 16K memory map, showing the location of the user's programs, the 7703 subroutines, and
the stack. It also shows the locations of the EPROM and RAM memory spaces on the 7801 and 7803 processor
cards.
PAGE

XO

PAGE

0000

I X1 I X2 I X3

I X5 I X6 I X7 xa!

X4

X9

! XA I XB

XC

1

XD

I XE I XF

0800

PROM 0 SOCKET

ox

PROM 1 SOCKET

(-USER's PROGRAM)

J

I

1000

1

I

1

107FF

,

1

1

1

~

1

I

1

I
18001

I
1

I
I

I

I

1

I

10FFF

I

1

1

I

1

11FFF

2COO I

1

I
I
I
1X

I
I
I
I
I

PROM 2 SOCKET

PROM 3 SOCKET

--11880

I

o

2000

o
W

I

1

2400

I

1

1

1

I17FF
I
1
2800 1

I
1

,1

,

II
I
cl

OWl

RAM

RAM

RAM

RAM

~ CI

1st 1K

2nd 1K

3rd 1K

4th 1K

Z~

2X

,I

1

I

:IE ~ I
oO~
CI

~r!

20FFI
3000 1

1

1 23FF

I

I

I

I

127FF
I

1
I

3X

J

I

1
I

128FF
1

I

I

I

,2FFF

I

I

I

I

L

~

NOT USED

\
\

I \

I

I

I

I

I

I

I

I

I

13FFF

NOTES

o

1. 7801 (808SA) and 7303 (Z80) processor cards have sockets for 8K ROM/PROM (sockets labeled PROM 0 - PROM 3).
These cards are shipped with these sockets empty. Also, the cards have sockets for 4K RAM, and the card is shipped with
1st 1K loaded and 2nd, 3rd, and 4th 1K sockets empty.
2. This map shows the 7303 software loaded. in user-supplied PROM 2. Page 20 (memory addresses 2000-20FF) is recommended
for subroutine return address stack.

Figure 4-3. 16K Memory Map for 7703 Software Package.
4-3
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Figure 4-4 illustrates a one-page memory map, subdivided into individual addresses, showing the 7703's subroutines starting at address 1800 and ending at 1880.

18

PAGE ADDRESS
LINE

LINE

LABEL

00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
10
11
12
13
14
15
16

(MOVE BLOC'2....

-

-

-

-

-

-------.,

--<
-

-----'

17
18
19
1A
1B
~,
1C
10
1E
1F
20
(-(HL» 21
22
23
24
25
26
27
28
29
2A
2B
2C
20
2E
2F
+,(COMPARE BLOCK)

"

32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F

-

-

-

-

--

40
41
42
43
44
45
46
47
48
49
4A
4B
4C
40
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
50
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
60
6E
6F
70
71

LABEL

-

-

--

-

-

--I

"

----"

-

-

-

(LOAD BLOCKL

-

-

72

73
74
75
76
77
78
79
7A
7B
7C
70
7E
7F

LINE

l'

-

-

-

80
81
82
83
84
85
86
87
88
89
8A
8B
8C
80
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
90
9E
9F
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
BO
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BO
BE
BF

LINE

LABEL
(LOAD A

= D)-

-

-

-

-------'

,

---I

-

-

(VERIFY A

= DL
-

-

-

-

"

-

CO
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
DO
01 '-.
02
03
04
05
06
07
08
09
OA
DB
DC
DO
DE
OF
EO
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
FO
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FO
FE
FF

Figure 4-4. One-Page Memory Map for 7703 Software Package.
4-4

o

LABEL

-

-

-

-

-

-

-

.-

o

-

-

-

-

--

o

o

E1

Subroutine (MOVE BLOCK)

Start Address:

1800

This subroutine moves a specified block of memory to a designated RAM area. The start and end addresses of
the source block and the start address of the destination block must be specified in the calling program as
follows:
ADR

Cx

JS

(MOVE BLOCK)

ADR+1
ADR+2
ADR+3
ADR+4

mL}
mP

Source block start address

ADR+5
ADR+6

mL}
mP

Source block end address

ADR+7
ADR+8

mL}
mP

Destination block start address
Next instruction upon return from (MOVE BLOCK), where mL refers to a
memory line address and mP refers to a memory page address.

ADR+9

(MOVE BLOCK) uses subroutine (-(HL»

o

1800
INITIALIZE
ADDRESS POINTERS
[SOURCE START (BC)
END (HL), DESTINATION START (DE)]

180F
FORM THE 2'8
COMPLEMENT OF
HE SOURCE END
ADDRESS

L L - _ - r -_ _,u

1820

1812
'GET DATA FROM
THE SOURCE

1813
STORE DATA IN
DESTINATION

1817
INCREMENT
ADDRESS
POINTERS

o
Figure 4-5. Flowchart - Subroutine (MOVE BLOCK) for 7703.

4-5
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o

REGISTER AND MEMORY ALLOCATION
PARAMETER
ADDRESS

ENTRY
REQUIREMENT

EXIT
CONDITION

Register pair

BC

XX

??

Register pair

DE

XX

??

Register pair

HL

XX

??

Register

A

XX

??

Register

F

XX

??

. ELEMENT

COMMENTS

NOTES
1. For registers not shown, entry contents are not used and remain unaltered at exit.
2. XX means no specific data required at entry, but entry contents will be lost.
3. ?? means contents are unknown or meaningless.

Figure 4-6. Register and Memory Allocation for 7703 Subroutine (MOVE BLOCK), Entry 1 and Return 1.

PROGRAM SPECIFICATIONS

SYMBOL

LIMITS

PARAMETER

MIN

I

UNITS

COMMENTS

0

MAX

Ns

Stack memory

4

Bytes

Np

Program memory

29

Bytes

Npt

Total program memory

39

Bytes

Nr

RAM memory

0

Bytes

Execution time

8085

271 + (N-1)68

Ne

Z80

274 + (N-1)68

Time
states

Uses (-(HL»

Uses (-(HL»

N = total number
of bytes in the block.

Figure 4-7. Characteristics of 7703 Subroutine (MOVE BLOCK), Entry 1 and Return 1.

o
4-6

4

o

E2

Subroutine (-(HL»

Start Address:

1820

This subroutine forms the two's complement of the contents of the HL register pair. Enterthis subroutine with
the 16-bit value that is to be complemented in the HL register pair. The two's complement of the original value
will be in the HL register pair upon exit from (-(HL)).

SAVE
AAND F
REGISTERS
1821
FORM THE 1'8
COMPLEMENT
of (HL)

o

1827
ADD ONE
TO (HL)

1828
RETRIEVE
A AND F
REGISTERS

Figure 4-8. Flowchart - Subroutine (-(HL» for 7703.

o
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o

REGISTER AND MEMORY ALLOCATION
PARAMETER

ENTRY
REQUIREMENT

EXIT
CONDITION

16-bit value to be
2's complemented

2's complement
of original value

/

ELEMENT

ADDRESS

Register pair

HL

'I

COMMENTS

NOTES
1. For registers not shown, entry contents are not used and remain unaltered at exit.
2. XX means no specific data required at entry, but entry contents will be lost.
3. ?? means contents are unknown or meaningless.

Figure 4-9. Register and Memory Allocation for 7703 Subroutine (-(HL», Entry. 2 and Return 2.

PROGRAM SPECIFICATIONS

SYMBOL

LIMITS

PARAMETER

MIN

I

MAX

UNITS

Ns

..Stack memory

2

Bytes

Np

Program memory

10

Bytes

Npt

Total program memory

10

Bytes

Nr

RAM memory

0

Bytes

Ne

Execution time

8085

62

Z80

68

Time
states

COMMENTS

o

Figure 4-10. Characteristics of 7703 SubrouUne (-(HL», Entry 2 and Return 2.

1

'1

o
4-8

o

E3

Subroutine (COMPARE BLOCK)

Start Address:

1830

This subroutine compares two blocks of memory. The start and end addresses of one block (the first block)
and the start address of the other block (the second block) must be specified in the calling program as follows:
ADR

JS

Cx

ADR+1

(COMPARE BLOCK)

ADR+2
ADR+3
ADR+4

mL }
mP

First block start address

ADR+5
ADR+6

mL }
mP

First block end address

ADR+7
ADR+8

mL }
mP

Second block start add ress

ADR+9

Next instruction upon return from (COMPARE BLOCK), where mL refers to a
memory line address and mP refers to a memory page address.

(COMPARE BLOCK) uses subroutine (-(HL). It utilizes the carry flag to indicate whether or not the two
blocks of memory are identical. If the two memory blocks are identical, the carry flag is cleared (CO) upon
exit from (COMPARE BLOCK). If the two memory blocks are not the same, the carry flag is set (C1) upon
exit from the subroutine. The BC register pair holds the address of the error location in the first block, the
A register holds the data from the first block's error location, and the HL register pair holds the addressof
the error location in the second block.

0

0

INITIALIZE ADDRESS
POINTERS [FIRST
START (BC), END (HL)
SECOND START (DE))

e

183F
FORM THE 2'.
COMPLEMENT OF
THE BLOCK END
ADDRESS

1820

NO

184C

1853
INCREMENT
ADDRESS
POINTERS

SET CARRY
FLAG
(ERROR)

NO

e
CLEAR CARRY
FLAG
(NO ERROR)

0

e
Figure 4-11. Flowchart - Subroutine (COMPARE BLOCK) for 7703.
4-9

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REGISTER AND MEMORY ALLOCATION
PARAMETER
ADDRESS

ENTRY
REQUIREMENT

EXIT
CONDITION

Register pair

Be

xx

??

Register pair

DE

XX

??

Register pair

HL

XX

??

Register pair

A

XX

??

Register pair

F

XX

CO

ELEMENT

COMMENTS

The two blocks compared
- no error.

NOTES
1. For registers not shown, entry contents are not used and remain unaltered at exit.
2. XX means no specific data required at entry, but entry contents will be lost.
3. ?? means contents are unknown or meaningless.

Figure 4-12. Register and Memory Allocation for 7703 Subroutine (COMPARE BLOCK), Entry 3 and Return 3.

o
PROGRAM SPECIFICATIONS

SYMBOL

LIMITS

PARAMETER

MIN

I

UNITS

COMMENTS

MAX

Ns

Stack memory

4

Bytes

Np

Program memory

37

Bytes

Npt

Total program memory

47

Bytes

Nr

RAM memory

0

Bytes

Ne

Execution time

8085

290 + (N-1 )83

Z80

296 + (N-1 )86

Time
states

Uses (-(HL»

Uses (-(HL»

N = total number
of bytes in the block.

Figure 4-13. Characteristics of 7703 Subroutine (COMPARE BLOCK), Entry 3 and Return 3.

o
4-10

o

REGISTER AND MEMORY ALLOCATION
PARAMETER

EXIT
CONDITION

ADDRESS

ENTRY
REQUIREMENT

Register pair

Be

xx

Register pair

DE

XX

??

Register pair

HL

XX

Second block error add ress

Register

A

XX

First block error data

Register

F

XX

C1

ELEMENT

COMMENTS

First block error address

Error - discrepancy in
the two blocks.

NOTES
1. For registers not shown, entry contents are not used and remain unaltered at exit.
2. XX means no specific data required at entry, but entry contents will be lost.
3. ?? means contents are unknown or meaningless.

Figure 4-14. Register and Memory Allocation for 7703 Subroutine (COMPARE BLOCK), Entry 3 and Return 4.

o

PROGRAM SPECIFICATIONS
LIMITS

PARAMETER

SYMBOL

MIN

I

MAX

UNITS

Ns

Stack memory

4

Bytes

Np

Program memory

37

Bytes

Npt

Total program memory

47

Bytes

Nr

RAM memory

0

Bytes

Ne

Execution time

-

Time
states

8085
Z80

COMMENTS
Uses (-(HL))

Uses (-(HL))

Execution time depends
on error. No value to user.

Figure 4-15. Characteristics of 7703 Subroutine (COMPARE BLOCK), Entry 3 and Return 4.

o
4-11
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Subroutine (LOAD BLOCK)

E4

Start Address:

1860

This subroutine allows the user to load a designated block of memory with a designated data byte. The start and
end addresses of the memory block and the data byte must be specified in the calling program as follows:
ADR

JS

ADR+1

o

Cx
(LOAD BLOCK)

ADR+2
ADR+3
ADR+4

mL }
mP

Block start address

ADR+5
ADR+6

mL }
mP

Block end address

ADR+7

dd

Data byte to be loaded into memory block

ADR+8

Next instruction upon return from (LOAD BLOCK), where mL refers to a
memory line address and mP refers to a memory page address.

(LOAD BLOCK) uses subroutine (-(HL)).

INITIALIZE ADDRESS
POINTERS [BLOCK
START (BC), END (HL)
AND DATA BYTE (A)

o

1860
~
......
--""""'---~\:::.J
FORM THE 2'5
COMPLEMENT OF
THE BLOCK END
ADDRESS

1870

~

STORE DATA
BYTE AT
CURRENT
_ADDRESS
_ _ _ _...... 1820

1874
INCREMENT
ADDRESS
POINTER

o
Figure 4-16. Flowchart - Subroutine (LOAD BLOCK) for 7703.
4-12

o

REGISTER AND MEMORY ALLOCATION
PARAMETER
ADDRESS

ENTRY
REQUIREMENT

EXIT
CONDITION

Register pair

BC

XX

??

Register pair

DE

XX

??

Register pair

HL

XX

??

Register

A

XX

??

Register

F

XX

??

ELEMENT

COMMENTS

NOTES
1. For registers not shown, entry contents are not used and remain unaltered at exit.
2. XX means no specific data required at entry, but entry contents will be lost.
3. ?? means contents are unknown or meaningless.

Figure 4-17. Register and Memory Allocation for 7703 Subroutine (LOAD BLOCK), Entry 4 and Return 5.

PROGRAM SPECIFICATIONS

SYMBOL

LIMITS

PARAMETER

MIN

I

MAX

UNITS

Ns

Stack memory

4

Bytes

Np

Program memory

25

Bytes

Npt

Total program memory

35

Bytes

Nr

RAM memory

N

Bytes

Execution time

8085

245 + (N-1 )55

Ne

Z80

248 + (N-1 )55

Time
states

?

COMMENTS
Uses (-(HL»

Uses (-(HL»

N = total number
of bytes in the block.

Figure 4-18. Characteristics of 7703 Subroutine (LOAD BLOCK), Entry 4 and Return 5.

o
4-13
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Subroutine (LOAD A = D)

E5

Start Address:

1880

This subroutine loads a designated block of RAM memory with an "address equals data" format. The memory
block's start and end addresses must be specified in the calling program as follows:
ADR

JS

o

ex
(LOAD A = D)

ADR+1
ADR+2
ADR+3
ADR+4

mL }
mP

Memory block start address

ADR+5
ADR+6

mLJ
mP

Memory block end address

ADR+7

Next instruction upon return from (LOAD A= D), where mL refers to a memory
line address and mP refers to a memory page address.

(LOAD A = D) uses subroutine (-(HL».
The data loaded into each memory location is equal to the line address of that location.

INITIALIZE
ADDRESS POINTERS
[BLOCK START (BC),
END (HL))

o

188B
FORM THE 2's
COMPLEMENT OF
THE BLOCK END
ADDRESS
...._ _
......_ _-w 1820

188E
STORE "A = D"
DATA AT
CURRENT
ADDRESS

1893
INCREMENT
ADDRESS
POINTER

o
Figure 4-19. Flowchart - Subroutine (LOAD A = D) for 7703.
4-14

o

REGISTER AND MEMORY ALLOCATION
PARAMETER
ADDRESS

ENTRY
REQUIREMENT

EXIT
CONDITION

Register pair

BC

XX

??

Register pair

DE

XX

??

Register pair

HL

XX

??

Register

A

XX

??

Register

F

XX

??

ELEMENT

COMMENTS

NOTES
1. For registers not shown, entry contents are not used and remain unaltered at exit.
2. XX means no specific data required at entry, but entry contents will be lost.
3. ?? means contents are unknown or meaningless.

Figure 4-20. Register and Memory Allocation for 7703 Subroutine (LOAD A = D), Entry 5 and Return 6.

PROGRAM SPECIFICATIONS

SYMBOL

o

LIMITS

PARAMETER

MIN

I

MAX

UNITS

Ns

Stack memory

4

Bytes

Np

Program memory

24

Bytes

N pt

Total program memory

34

Bytes

Nr

RAM memory

N

Bytes

Execution time

8085

Ne

236 + (N-1 )59

Z80

239 + (N-1 )59

Time
states

COMMENTS
Uses (-(HL))

Uses (-(HL))

N = total number of
bytes in the block.

Figure 4-21. Characteristics of 7703 Subroutine (LOAD A = D), Entry 5 and Return 6.

o
4-15
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Subroutine (VERIFY A

= D)

E6

Start Address:

18AO

This subroutine tests a memory block for "address equals data" format. The start and end addresses of the
memory block must be specified in the calling program as follows:
ADR

JS

o

Cx
(VERI FY A = D)

ADR+1
ADR+2
ADR+3
ADR+4

mL}
mP

Memory block start address

ADR+5
ADR+6

mL}
mP

Memory block end address

ADR+7

Next instruction upon return from (VERIFY A = D), where mL refers to a
memory line address and mP refers to a memory page address.

(VERIFY A = D) uses subroutine {-(HL)). It utilizes the carry flag to indicate whether or not the memory
block is in the "address equals data" format. If the block contains all A = D data, the carry flag is cleared
(CO) upon exit from (VERIFY A = D). If there is a location that does not have the A = D format, the carry
flag is set (C1) upon exit from the subroutine. The BC register pair holds the address of the location
with the error, and the A register holds the error data.

o

INITIALIZE
ADDRESS POINTERS
[BLOCK START (BC),
END (HL)]

t;\

18AB

~-.........- -.... Q
FORM THE 2'8
COMPLEMENT OF
THE BLOCK END
ADDRESS

..---~=::::;r----&.I

1820

18AE
GET CURRENT
DATA BYTE

NO

18BC
INCREMENT
ADDRESS
POINTER

SET CARRY
FLAG
(ERROR)

CLEAR CARRY
FLAG
(NO ERROR)

o
Figure 4-22. Flowchart - Subroutine (VERIFY A = D) for 7703.

4-16
-------~.

--

---------------.------~--

--

REGISTER AND MEMORY ALLOCATION

o

PARAMETER
ADDRESS

ENTRY
REQUIREMENT

EXIT
CONDITION

Register pair

BC

XX

??

Register pair

DE

XX

??

Register pair

HL

XX

??

Register

A

XX

??

Register

F

XX

CO

ELEMENT

COMMENTS

A = D throughout
block - no error.

NOTES
1. For registers not shown, entry contents are not used and remain unaltered at exit.
2. XX means no specific data required at entry, but entry contents will be lost.
3. ?? means contents are unknown or meaningless.

Figure 4-23. Register and Memory Allocation for 7703 Subroutine (VERIFY A = D), Entry 6 and Return 7.

PROGRAM SPECIFICATIONS

o

SYMBOL

LIMITS

PARAMETER

MIN

I

MAX

UNITS

COMMENTS
Uses (-(HL))

Ns

Stack memory

4

Bytes

Np

Program memory

30

Bytes

Npt

Total program memory

40

Bytes

Nr

RAM memory

0

Bytes

Execution time

8085

247 + (N-1 )66

Ne

Z80

247 + (N-1 )69

Time
states

Uses (-(HL))

N = total number
of bytes in the block.

Figure 4-24. Characteristics of 7703 Subroutine (VERIFY A = D), Entry 6 and Return 7.

!

I

o
4-17
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REGISTER AND MEMORY ALLOCATION
PARAMETER
ADDRESS

ENTRY
REQUIREMENT

EXIT
CONDITION

Register pair

BC

XX

Address of error location

Register pair

DE

XX

??

Register pair

HL

XX

??

Register

A

XX

Error data (A =F D)

Register

F

XX

C1

ELEMENT

COMMENTS

Error, A =F 0 at same
location.

NOTES
1. For registers not shown, entry contents are not used and remai n unaltered at exit.
2. XX means no specific data required at entry, but entry contents will be lost.
3. ?? means contents are unknown or meaningless.
,I'

Figure 4-25. Register and Memory Allocation for 7703 Subroutine (VERIFY A = D), Entry 6 and Return S.

PROGRAM SPECIFICATIONS

SYMBOL

LIMITS

PARAMETER

MIN

I

MAX

UNITS

Ns

Stack memory

4

Bytes

Np

Program memory

30

Bytes

Npt

Total program memory

40

Bytes

Nr

RAM memory

0

Bytes

Ne

Execution time

SOS5
ZSO

-

Time
states

COMMENTS

o

Uses (-(HL»

Uses (-(HL»

N = total number
of bytes in the block.

Figure 4-26. Characteristics of 7703 Subroutine (VERIFY A = D), Entry 6 and Return S.

o
4-18
~~~~~~~--~~~--------------------~------~----~~-~----------------

o

Program Listing
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4-20

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4-21
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Demonstration/Test Program:
Shakedown (Confidence Level) Test

Start Address:

0000

o

This program provides a quick test of the 7703 RAM. It programs all RAM bits with different patterns and tests for
valid data, giving the user a level of confidence in the 7703.
The program loads and tests for a known data pattern in the 7703 RAM, then loads and tests for a new data
pattern, and finally loads and tests for the complement of the second data pattern.
Error routines store any error parameters (address of memory location with error, data contained in the error
location). If there are no errors for a particular segment of the program, the program stores zeros for the error
addresses and data. Error data may be examined with a user-provided routine, which should test the error
storage locations to determine whether an error occurred. The user's routine must provide a means of displaying or communicating any error data.
This program uses all of the subroutines presented in the preceding pages. RAM locations 211 0 through 211 E,
inclusive, are used as error storage locations.
NOTE
This is a demonstration/test program; it is not a subroutine.

o

o
4-22
-------------------------

-------------------

---------

--------------------------------- - - - - - - - - -

o
PAGE ADDRESS
LINE
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
10
11
12
13
14
15
16

LINE
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
40
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
50
5E
5F
60
61
62

-

-

-

-

-

17

o

LABEL
TEST

18
19
1A
1B
1C
10
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
20
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F

-

-

-

LABEL

-

-

-

-

-

63
64
65
66
67
68
69
6A
6B
6C
60
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
70
7E
7F

-

-

-

-

LINE

-

-

-

-

-

,

-

LABEL

80
81

LINE

-

82

83
84
85
86
87
88
89
8A
8B
8C
80
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
90
9E
9F
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
BO
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BO
BE
BF

00

-

-

-

-

-

-

-

-

ERROR 1 _

r

-

-

ERROR 2

-

-

-

~,

-

-

CO
C1

LABEL
!ERROR 3

-

(;2

C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
DO
01
02
03
04
05
06
07
08
09
OA
DB
DC
DO
DE
OF
EO
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
FO
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FO
FE
FF

-

-

-

v

(SAVE)

-

-

-

"

-

-

-

-

-

-

-

-

-

o
Figure 4-28. Memory Map for Shakedown (Confidence Level) Test -

7703.

4-23
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PAGE ADDRESS
LINE
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
10
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
28
2C
20
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F

LINE

LABEL

-

-

-

-

-

-

-

ERROR 1 _

DATA

+

-

DATA

-

ERROR 2 _

t

-

ERROR 3 -'--

DATA

"

-

-

-

-

-

-

-

-

-

-

-

40
41
42
43
44
45
46
47
48
49
4A
4B
4C
40
4E
4F
50
51
52
53
54
55
56
57
58
59
SA
5B
5C
50
5E
SF
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
60
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
70
7E
7F

LABEL

LINE

-

-

-

-

-

-

-

--,

-

-

-

-

-

-

-

-

-

-

-

-

-

80
81
82
83
84
85
86
87
88
89
8A
8B
8C
80
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
90
9E
9F
AO
A1
A2
A3
A4
AS
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
BO
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BO
BE
BF

LINE

LABEL

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

.

-

LABEL

CO
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
DO
01
02
03
04
05
06
07
08
09
OA
DB
DC
DO
DE
OF
EO
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
FO
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FO
FE
FF

Figure 4-29. Memory Map for Error Storage Locations (Shakedown Test) - 7703.

4-24

o

21

-

-

-

-

-

-

o

-

-

-

-

--

-

-

o

o
INITIALIZE
SYSTEM
(STACK, MEMORY)

NO

OOC

0006
CLEAR ERROR
STORAGE
LOCATIONS

LOAD MEMORY
WITH
A = D PATTERN

SAVE ERROR DATA
(MEMORY
LOCATIONS
AND DATA)

0078
CHECK
FOR
ERRORS

NO

0

OOAO
~----~-------SAVE ERROR DATA
(MEMORY LOCAToN AND DATA)

CLEAR ERROR
STORAGE
LOCATIONS

0021
LOAD SECOND
PATTERN INTO
HALF OF MEMORY

o

0029
MOVE PATTERN
TO OTHER
HALF OF MEMORY

NO

0080
SAVE ERROR DATA
(MEMORY LOCA TIONS AND DATA)

CLEAR ERROR
STORAGE
LOCATIONS

004E
LOAD COMPLE MENT OF PATTERN
INTO HALF OF
MEMORY

0056
MOVE PATTERN
TO OTHER
HALF OF MEMORY

o
Figure 4-30. Flowchart - Demonstration/Test Program for 7703.

4-25
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INITIALIZE
STORAGE
LOCATIONS

INITIALIZE
STORAGE
LOCATIONS

SAVE
ERROR
PARAMETERS

8

OOC4

8

SAVE
ERROR
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00A6
SAVE
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DATA

8 ----SAVE FIRST
BLOCK ERROR
ADDRESS
(PAGE, LINE)

o

0003
SAVE FIRST
BLOCK ERROR
DATA

0005
SAVE SECOND
BLOCK ERROR
ADDRESS
(PAGE, LINE)
0009
SAVE SECOND
BLOCK ERROR
DATA

o
Figure 4-30. Flowchart-Demonstration/Test Program for 7703 (continued).

4-26

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4-28

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7703- Ie
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7703-8C
7703-I6C

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~t------~~_r
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107036
107037
107078
107078
107081
i07082
107085
107084
107087
107088
106298
106299

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Figure 5-1. Schematic for 7703 (Reference Only).

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CIRCUIT SIDE
"I[WOF BOARD.

REFERENCE ONLY
t.c.o. NO. -10700Z -Ibe
SCH!;MATiC NO. - IObZ 97
PARTS U';T NO. - 10"2.99

I!ID~

C1I
I
U>

Figure 5-2. Assembly for 7703 (Reference Only).

Card Layout
Figure 5-3 shows the physical location of the 7703's main components: the various switches, indicators, and
jumpers on the card. The functions of the various components are identified. Note the position of pin 1 on the
RAM elements and the other ICs. When replacing chips, be careful to insert them only with pin 1 positioned as
shown in the figure; also, make sure that no pins are bent beneath the body of the chip.

o

CAUTION
Remove jumper A from the battery-enable pad before removing or replacing any RAM chips on the
7703 card. After RAM chip removal and/or replacement, replace Jumper A before reinserting card
into the card cage connector. If jumper A is not replaced, the contents of the RAM on the 7703 card
are destroyed.
Read Timing Diagram
Figure 5-4 displays a read timing diagram for a ZaO-based CPU. The timing sequence is based on a 400-ns
clock. Because of slow propagation time through the read and write decoding circuitry, do not use the 7703
with 4-MHz (or faster) CPU cards.

o

o
5-4
---

~~

..

-----~~~~-~---~---~-

o

EACH MEMORY BLOCK (X)
IS A CHIP PAIR 6514-2

4K -4

SELECT
16K
QUADRANT

4K -1
OPEN FOR
UNUSED 4K
BLOCKS

TEST POINTS
TO MONITOR
BATTERY
CURRENT

o·

BATTERY
ENABLE
JUMPER PAD
(JUMPER A)

Figure 5-3. Location and Functions of Main
t,

CPU B

I

X

"
"
""
""

X

CARD SELECT
SX"
4K BLOCK DECODE
X4K",SY"
CHIP SELECT
CEO"-CE1S"
BLOCK SELECTED"
BLOCK READ"

for 7703 .

t3
400n5

X
STO BUS TIMING

/
X

MEMORY CHIP ADDRESS STABLE

/

/
/

7703 CARD

/
/

,~------------------~----_/

DATA BUS ENABLE"

o

•

/ ,--------- }

"

RD"
ADDRESS
AO-A9

400n5

INSTRUCTION ADDRESS STABLE

MEMRQ"

6S14-2

T

400n5

Com~onents

....

t2

--.J

ADDRESS BUS
AO-A1S

REPLACEBATTERY LED

WRITE INHIBIT SWITCHES
UP (OFF): INHIBIT
DOWN: WRITE ENABLE

HIGH
IMPEDANCE

HIGH IMPEDANCE
, . - - - - _ , . -___---..__~.....__~""""'"".......~-"
OUTPUT ---------<-(_..!L~O~W~Z~.JX
VALID RA
DATA OUT
)

®~ CPU READS DATA
Figure 5-4. Read Timing Diagram for 7703 (used with Pro-Log's 7803 2.5-MHz Z80 CPU card).

5-5
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Address Decoding Circuit

0

See Fig. 5-5. Address lines A15 and A14 are decoded by U4 to select the 16K memory space in which the 7703
operates. A15 and A14 decode the 64K address space as shown in Fig. 5-6.
The 16K address range that the 7703 will respond to is determined by the jumpering of SX as indicated in Fig.
5-6 and as specified in Section 2. Jumper SX is in the X3 position when the 7703 is initially shipped to you
from the factory.
Address lines A13 and A12 are decoded by U5 to select the active 4K block from the 16K bank controlled by
A 15 and A 14. The outputs from one-half of U5 are wire-ORed together to form the SY* signal, which must be
active to access the selected 4K block. The unused 4K block or-blocks are disabled by cutting one or more of
the traces at SYO, SY1, SY2, or SY3. The outputs from the other half of U5 are used in the chip-enable
decoding operation.

o

o
5-6

0
+5V
CARD
DECODER
R2-6

74LS156

ADDRESS RANGE

4

+5V

1G

1V3

1C

1Y2

5

2

MEMEX

A15

3

A14

13

U4
B

6

X2

8000-BFFF

X1

7
1YO

4K BLOCK
DECODER

4000-7FFF

1Y1

A

+5V

COOO-FFFF

R1
22K

74LS156

XO
0OOO-3FFF
+5V

+5V

1C

1Y2

B

1 V1

3
A13

74LS156

1Y3

2

SX*
4K BLOCK DECODER

1G

R2-4

14

13
2G

2Y3

A12

1YO

A
U5

2Y2

2C

US
A13

3

A12

13

BUS CONTROL
ENABLE
(4K BLOCKS)

2Y1

B

A

2YO
U5

0

TO CHIP-ENABLE
DECODERS

~

Figure 5-5. Address Decoding Circuit for 7703.

ADDRESS
LINE
A15

ADDRESS
LINE
A14

MEMORY
ADDRESS
RANGE

SX
JUMPERS

0

0

0OOO-3FFF

XO

0

1

4000-7FFF

X1

1

0

8000-BFFF

X2

1

1

COOO-FFFF

X3

o

Figure 5-6. Decoding the 7703's 64K Address Space.

5-7
,

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-

0

Chip-Enable Decoding Circuit
See Fig. 5-7. The block enables generated by U5 (04K, 14K, 24K, and 34K) are decoded (with address lines A 11
and A10) by U6 and U7. The CEX· signals select the 1K byte RAM pair that is to be accessed. (Fig. 5-8).
Signal OP is derived from the operate flip-flop, which is reset by power failure, or by power-up and power-down
of the system. U6 and U7 are open collector devices and are pulled up to CMOS +5V.
FROM
4K BLOCK
DE CODER

V

CMOS+5V

CHIP ENABLE
DECODERS

A~

74LS15S

~r

~

OP

34K*

1

-

1G

5

1

us

3
A11'- B

A10'

1
...

1Y2

1C

-2.:..

CE15*

.....

CE14*

R10-3
..A.A.A

.....

R11

S

1Y1

~
~

7
A

.........

.A.A.A

1Y3 Ioiio..
r-t"

2

'-I

R19-3
4

1YO

~

...

l.

.........

CE13*

R9-4

............

J..

"""

•••

CE12*

CMOS+5V

OP*

-

'"

24K*

12

14

'-I

-'"

2Y3 ~

2G

15

A11'~
13
A10'-

2Y2

2C

B

....11

'"10
"

us

2Y1 ;:
9

A"

2YO

.. '"

R9-S

....

~

All

A.A .....

1

-

CE11*

R7-S
..A.A .....

J..

."''''

CE10*

..
.. '"
RS-5

..A ..........

1

-

J.

-

'"

CE9*

R5-2

...........

CE8*

22K(TYP)
CMOS+5V

74LS15S

~

'"

OP

1

14K*

-

1G

4
1Y3 ~

1C

....

5

2

'-I

3
A11'13
A10'-

1Y2
U7

B

1Y1

'""
....I'-'S
7

A

1YO

iI-I.

""

R10-5
A ........

J.

1
...
J.

-

.L

-

A~

."''''

CE7*

.. '"

R10-2
A ..........

CES*

R5-S

.........
•••

CE5*

RS-3
A.A.A

•••

CE4*

04K*

-

-""

12
iI-I.
2Y3 r-

2G

11

15

'"

A11'-..!

A10'-.-!!

2C

2Y2
U7

B

A

'"

~

"""

10

2Y1" n

"""9

n.

2YO IV

.L
...

...

l.

R9-5
.........
.........
R7-5
.A.A.A

•••

-

...1

CE2*

RS-4

.........

.A.A ...

..L

CE3*

R5-3
..........

.... '"

11K(TYP)

CE1*

CEO*

'"
''""

'"

~,

Figure 5-7. Chip-Enable Decoding Circuit for 7703.
5-8

o

j~

74LS15S
14

''""
''""
''""

!.

~

22K(TYP)
CMOS+5V

OP*

'"

~

22K(TYP)

74LS15S

'"

TO CHIP-ENABLE
PINS (#8) OF EACH
1 K PAIR OF MEMORY
CHIPS.

o

o
OPERATE
SIGNAL

X4K

OP* - 0

04K

CEO*-3 *

Lowest

OP -1

14K

CE4*-7 *

Next lowest

OP* - 0

24K

CE8*-11 *

Next to highest

OP -1

34K

CE12*-15*

Highest

CEX*

4K SELECTED

Figure 5-8. CEX* Signal Selection of 1K Byte RAM Pair to be Accessed - 7703.

o

o
5-9
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Data Bus Buffer Circuit
See Fig. 5-9. The 7703 data bus buffering and directional control are provided by U1, which is a three-state
bidirectional bus controller. When the read (RD*) signal is active and when SY* and MEMRQ* are both active,
U1 is enabled to pass data from the 7703 card to the STD BUS (Le., read operation). When the RD* signal is
inactive and when WR*, SY*, and MEMRQ* are all active, U1 allows data to be transferred from the STD BUS to
the 7703 card (write operation). Otherwise, U1 is in a high impedance state.

o

TO DATA LINES
OF ALL MEMORY
CHIPS

DATA BUS BUFFER

8
FROM srD
DATA BUS ----------------~--+---.---------------~

15
EN·

74LS32
5
RD'--------------

Figure 5-13. Monitoring Circuit for 7703.

Backup Battery Circuit
See Fig. 5-14. The backup battery is a lithium primary cell rated at 3V, 1 ampere hour. The battery's shelf life is
10 years and its operating range is from -40 to 70°C. A Schottky diode protects the battery from system power.
You can monitor the battery current by measuring the voltage drop across the 100-0 resistor (R4) that is in
series with the battery. Battery drain or back leakage should never exceed 30ILA. See Appendix A for guidelines
on handling lithium batteries.
+5V----------~~----~

~------__----------__---------~CMOS+'5V

01
MPS6534

CR1
1NS518
TO "REPLACE
BATTERY"
....- - - - - - -..... INDICATOR
CIRCUIT

R12-1
2.2K

LOW Vee·

o

=

BAT 1
3V/1AH
- - LITHIUM

CR2
R12-4
2.2K
1N4148

C4-7
.1J.LF
50V

R12-2
2.2K

1000
1%

o

02
2N4123

R12-3
2.2K

CR3
1N4148

A

GND---------------~------------_4~--------------_.~-----------~-----------------------_1J) TP-1
NOTE: Short circuit of traces or exposure of the card to strong radiation shortens data retention and necessitates early battery replacement.

Figure 5-14. Battery Backup Circuit for 7703.
Changing the Lithium Battery
To change the lithium battery on the 7703 card, follow these steps:
1. Remove the battery activation jumper (jumper A).
2. Desolder the battery's leads from the card. DO NOT TRY TO REMOVE THE LEADS FROM THE BATTERY!
3. Remove the battery.
4. Place the new battery in position, checking for proper polarity.
5. Solder the battery leads to the card at the appropriate pads.
6. Replace jumper A.
7. Connect a voltmeter across the test points TP1 anq TP2. The voltage should not be more than 0.003V,
although it may be considerably less. A proper reading at this point verifies that the lithium battery is
properly installed and operating. If the voltage is more than 0.003V, disconnect the battery and call the
Customer Service department at Pro-Log (see "Return for Repair Procedures").
5-14

0'

,I
,

I

o

Signal Glossary

MNEMONIC

MEANING

PIN(S)

FUNCTION

00-07

Data bus

7-14

High-active

8-bit, 3-state bidirectional data bus

A15, A14

Address bus

16,18

High-active

Decode 64K address space through
16K bank decoder

A13, A12

Address bus

20,22

High-active

Select active 4K block from 16K bank
controlled by A 15 and A 14

A11, A10

Address bus

24,26

High-active

Decode block enables

AO-AS

Address bus

15,17, 19
21,23,25
27,28,29,30

High-active

Address bus for 1Kx8 CMOS RAM

MEMEX

Memory
expansion

36

High-active

Expands or enables memory add ressi ng

WR*

Write

31

Low-active

Indicates that the bus holds valid data
to be written in addressed memory

MEMRQ*

Memory
address select

34

Low-active

Indicates address bus holds valid address for memory read/write operations

RD*

Read

32

Low-active

+5V

Voltage
(bused)

2

-

~

o

DESCRIPTION

.. -

Indicates that processor is reading data
from memory

Provides main logic voltage

Note: Unused pins are open; pads are provided on some unused pins for user signals.

Figure 5-15. STD BUS Edge Connector Signals for the 7703. (See also edge connector pin list, Fig. 2-7.)

o
5-15

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,

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7703 Internal Signals

o

SCHEMATIC
GRID
LOCATION

MEANING

SX*

0-6

16K bank select

User-selectable. Oefines 16K address range by
decoding A15, A14. Block decode enable.

Sy*

0-5

4K block select

Indicates that one of the 4K banks has been selected
by decoding A13, A12 qualified by SX*. BUS control
enable.

34K*

0-6

Block 3 selected

Enables decoding circuitry for memory block 3 (RAM
pairs 12-15) by decoding A13, A12 qualified by SX*.

24K*

0-6

Block 2 selected

Enables decoding circuitry for memory block 2 (RAM
pairs 8-11) by decoding A13, A12 qualified by 8X*.

14K*

0-6

Block 1 selected

Enables decoding circuitry for memory block 1 (RAM
pairs 4-7) by decoding A13, A12 qualified by SX*.

04K*

0-6

Block 0 selected

Enables decoding circuitry for memory block 0 (RAM·
pairs 0-3) by decoding A 13, A 12 qualified by SX*.

BLOCK
SELECTED*

0-5,4

Block selected

Qualified with MEMRQ* to indicate that a memory
block has been selected.

BLOCK
SELECTED

0~4,3

Block selected

Complement of above signal. Used to set the operate
flip-flop upon a memory reference (enable memory).

BLOCKREAD*

0-4

Read strobe

Provides direction control for the data bus buffer.

BLOCK
WRITE*

0-4

Write strobe

Provides direction control for the data bus buffer.
Provides write-enable signals via the write-inhibit
switches.

OP

0-3

Chip-enable
decode strobe

Acts as strobe to the chip-enable decoder
(Blocks 1 and 3).

OP*

0-3

Chip-enable
decode strobe

Acts as strobe to the chip-enable decoder
(Blocks 0 and 2). Also, qualifies BLOCK WRITE*
to generate the write-enable signals.

WE3*

0-2

Write-enable
blocks

Provides write-enable for memory block 3 (RAM
pairs 12-15). 81-4 must be closed.

WE2*

0-2

Write-enable
block 2

Provides write-enable for memory block 2 (RAM
pairs 8-11). S1-3 must be closed.

WE1*

0-2

Write-enable
block 1

Provides write-enable for memory block 1 (RAM
pairs 4-7). 81-2 must be closed.

MNEMONIC

DESCRIPTION/FUNCTION

Figure 5-16. 7703 Internal Signal8 (8ee Schematic, Fig. 5-1, for reference).
5-16

o

o

o

7703 Internal Signals (Cont.)

MNEMONIC

o

SCHEMATIC
GRID
LOCATION

MEANING

DESCRIPTION/FUNCTION

WEO·

0-2

Write-enable
block 1

Provides write enable for memory block 0 (RAM
pairs 0-3). S1-2 must be closed.

CE15*

C-6

Chip-enable
RAM pair 15

Provides chip enable to RAM pair 15 by decoding
A11, A10 qualified by 34K* and OP.

CEO*

8-6

Chip-enable
RAM pair 0

Provides chip enable to RAM pair 0 by decoding
A 11, A 10 qualified by 04K* and OP*.

2.5 REF

A-7

2.5V reference
voltage

Reference voltage used in the power monitor circuit
(to test Vcc) and in the circuit that monitors the battery.

LOWVCC*

A-6

Low Vcc voltage

Used to clear the operate flip-flop when Vcc (+5V) is
too low (power-down <4.52V, power-up <4.663V).
Disables memory.

CMOS +5V

8-4

CMOS voltage
supply

Voltage supply for the CMOS devices. Alternate power
source to allow data retention when system power is
not provided.

Figure 5-16. 7703 Internal Signals (continued).

Return for Repair Procedures
Domestic Customers:
1. Call our factory direct at (408) 372-4593, and ask for CUSTOMER SERVICE.
2. Explain the problem and we may be able to solve it on the phone. If not, we will give you a Customer
Return Order (CRO) number.
Mark the CRO number on the shipping label, packing slip, and other paperwork accompanying the
return. We cannot accept returns without a CRO.
3. Please be sure to enclose a packing slip with CRO number, serial number of the equipment, if applicable,
reason for return, and the name and telephone number of the person we should contact (preferably the
user), if we have any further questions.
4. Package the equipment in a solid cardboard box secured with packing material.
CAUTION: Loose MOS integrated circuits, or any product containing CMOS integrated circuits, must
be protected from electrostatic discharge during shipment. Use conductive foam pads or conductive
plastic bags, and never place MOS or CMOS circuitry in contact with Styrofoam materials.
5. Ship prepaid and insured to:

o

Pro-Log Corporation
2411 Garden· Road
Monterey, California 93940
Reference CRO # _ _ _ _ __
5-17

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International Customers:

Equipment repair is handled by your local Pro-Log Distributor. If you need to contact Pro-Log, the factory
can be reached at any time by TWX at 910-360-7082.

o

Limited Warranty: Seller warrants that the articles furnished hereunder are free from defects in material
and workmanship and perform to applicable, published Pro-Log specifications for one year from date of
shipment. This warranty is in lieu of any other warranty expressed or implied. In no event will Seller be
liable for special or consequential damages as a result of any alleged breach of this warranty provision.
The liability of Seller hereunder shall be limited to replacing or repairing, at its option, any defective units
which are returned F.O.B. Seller's plant. Equipment or parts which have been subject to abuse, misuse,
accident, alteration, neglect, unauthorized repair or installation are not covered by warranty. Seller shall
have the right of final determination as to the existence and cause of defect. As to items repaired or
replaced, the warranty shall continue in effect for the remainder of the warranty period, or for ninety (90)
days following date of shipment by Seller or the repaired or replaced part whichever period is longer. No
liability is assumed for expendable items such as lamps and fuses. No warranty is made with respect to
custom equipment or products produced to Buyer's specifications except as specifically stated in
writing by Seller and contained in the contract.

o

o
5-18

APPENDIX A
Guidelines for Handling Lithium Batteries

o

NOTE
The information in this appendix is provided for reference only. Pro-Log does not assume any liability
that may arise out of the application or use of the information that follows.
Introduction
This appendix provides guidelines for utilizing lithium batteries. Lithium cells utilize lithium organic electrolytes, which produce much higher energy densities (capacity) than do conventional primary cells (carbon zinc).
This high capacity and the use of lithium require handling procedures more stringent than those required for
conventional cells. The cells used by Pro-Log are equipped with a pressure-sensitive vent mechanism
designed to safely deactivate a cell under the most abusive thermal environment, test, or operating condition.
CAUTION
To prevent recharge, short circuit, and puncture or exposure to high temperature or incineration, do
not store, test, or handle lithium cells near flammable solvents or materials.
Exposure to Short Circuit Conditions
Any cell that has been exposed to short circuit conditions should not be used in shippable equipment. The
cells should be hand inserted and soldered. No special precautions are required.

o

NOTE
If a wire breaks loose from the body of the lithium cell, do not attempt to resolder it.
The accidental short circuiting of a lithium cell will cause the internal temperature of the lithium cell to rise. If
the short remains long enough, one of the two following conditions will occur:
Either
Dissipated heat, burning, or glowing electrical connections will be evident with an accompanying loss of cell
output voltage.
Action: Remove the cause of the short circuit as soon as possible. Allow the cell to cool and remove it from
service. For disposal, see disposal recommendations on page A-2.
Or
40-50% of the cell's fumes will vent due to the internal temperature buildup. NOTE: Upon venting, the cell
chemistry will stop and the cell will become inactive.
Action: Remove the cause of the short circuit immediately, if possible without exposure to the venting fumes.
Evacuate the immediate area until venting has stopped. Move the cell or assembly to a dry ventilated area and
let it stabilize for 24 hours. After stabilization, dispose of the-cell (see disposal recommendations on page A-2).
Electrolyte Leakage
Characteristics: A leaking and/or vented cell can be readily detected by the presence of sulfur dioxide and
residual electrolyte solvents. The electrolyte consists primarily of sulfur dioxide, a highly irritating, nonflammable, colorless gas at room temperature and atmospheric pressure.

~I'(

0

Toxicity: Gaseous sulfur dioxide is highly irritating and is practically irrespirable. It is readily detected in
concentrations of 3-5 ppm and thus provides ample warning of its presence. Acute exposure to sulfur dioxide
has the following effects: throat irritation, coughing, constriction of the chest, tearing and smarting of the
eyes. There are no systemic effects of acute exposure to sulfur dioxide.

A-1
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Action: Electrically disconnect the suspected cell if it is under load. Store the cell or hardware in a ventilated,
dry area under ambient thermal conditions. After the concentrations of sulfur dioxide are reduced to a tolerable
value (approximately 5 ppm, i.e., when the irritating odor is significantly diminished), carefully unpack the
suspected cell or hardware and-visually examine it to determine the source of electrolyte leakage. Segregate
acceptable cells and get rid of the unacceptable ones (see disposal recommendations below).

0

Disposal Recommendations

1. Prepare the cell for disposal by packaging it in a suitable container that will prevent short circuiting or
crushing of the cell.
2. Dispose of low quantities of cells (10 or less) in the same manner as carbon zinc cells (flashlight batteries)
are disposed of.
CAUTION
Do not incinerate or compact the cells!
3. Dispose of larger quantities of cells as follows:
To effect the most environmentally safe disposal, place the cells in secured landfills ordisposal ponds with
provisions for leachate control and monitoring, documentation, and runoff control.
Sanitary landfills or special landfills can be used, where the cells can be dispersed in large quantities of
solid waster. When transporting the used cells or batteries for disposal, handle them in a safe manner to
prevent short circuiting.
CAUTION
Do not incinerate or compact the cells!
Shipping the Product

o

Shipping regulation requirements: Quantities less than 200 units/shipment are exempt from domestic regulation DOT-E-7042 and International Reg u lation lATA and may be sh ipped unrestricted. The sh i ppi ng package
should prevent short circuit or crushing the product.
Quantities greater than 200 units require that the following label be affixed:
Lithium - not restricted per DOT-E-7042, Section 173.206, Par. F; or lATA, Section 10.

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USER'S MANUAL

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2411 Garden Road
Monterey, California 93940
Telephone: (408) 372-4593
TWX: 910-360-7082

1 06293A

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Source Exif Data: 
File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37
Create Date                     : 2010:04:11 09:40:13-08:00
Modify Date                     : 2010:04:11 11:40:26-07:00
Metadata Date                   : 2010:04:11 11:40:26-07:00
Producer                        : Adobe Acrobat 9.31 Paper Capture Plug-in
Format                          : application/pdf
Document ID                     : uuid:236b2237-4935-46d8-97fa-dd82e43ad012
Instance ID                     : uuid:17afdeee-bd38-4ec2-9915-aa50516834b0
Page Layout                     : SinglePage
Page Mode                       : UseNone
Page Count                      : 72
EXIF Metadata provided by EXIF.tools

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