7 Series Product Tables And Selection Guide

7-series-product-selection-guide

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Spartan-7 FPGAs
I/O Optimization at the Lowest Cost and Highest Performance-per-Watt
(1.0V, 0.95V)

Logic Resources

Memory Resources
Clock Resources
I/O Resources

Embedded Hard IP
Resources

Speed Grades

Part Number
Logic Cells
Slices
CLB Flip-Flops
Max. Distributed RAM (Kb)
Block RAM/FIFO w/ ECC (36 Kb each)
Total Block RAM (Kb)
Clock Mgmt Tiles (1 MMCM + 1 PLL)
Max. Single-Ended I/O Pins
Max. Differential I/O Pairs
DSP Slices
Analog Mixed Signal (AMS) / XADC
Configuration AES / HMAC Blocks
Commercial Temp (C)
Industrial Temp (I)
Expanded Temp (Q)
Body Area
Ball Pitch
Package(1)
(mm)
(mm)
CPGA196
8x8
0.5
CSGA225
13x13
0.8
CSGA324
15x15
0.8
FTGB196
15x15
1.0
FGGA484
23x23
1.0
FGGA676
27x27
1.0

XC7S6
6,000
938
7,500
70
5
180
2
100
48
10
0
0
-1,-2
-1,-2,-1L
-1

XC7S15
12,800
2,000
16,000
150
10
360
2
100
48
20
0
0
-1,-2
-1,-2,-1L
-1

100
100

100
100

XC7S25
23,360
3,650
29,200
313
45
1,620
3
150
72
80
1
1
-1,-2
-1,-2,-1L
-1

XC7S50
52,160
8,150
65,200
600
75
2,700
5
250
120
120
1
1
-1,-2
-1,-2,-1L
-1

XC7S75
76,800
12,000
96,000
832
90
3,240
8
400
192
140
1
1
-1,-2
-1,-2,-1L
-1

XC7S100
102,400
16,000
128,000
1,100
120
4,320
8
400
192
160
1
1
-1,-2
-1,-2,-1L
-1

Available User I/O: 3.3V SelectIO™ HR I/O

100

100

150
150
100

210
100
250

338
400

338
400

Notes:
1.
Packages with the same last letter and number sequence, e.g., A484, are footprint compatible with all other Spartan-7 devices with the same sequence. The footprint compatible devices within this family are outlined.

Page 2

Artix-7 FPGAs
Transceiver Optimization at the Lowest Cost and Highest DSP Bandwidth
(1.0V, 0.95V, 0.9V)

Logic
Resources
Memory
Resources
Clock Resources
I/O Resources

Embedded
Hard IP
Resources

Speed Grades

Footprint
Compatible
Footprint
Compatible

Part Number
Logic Cells
Slices
CLB Flip-Flops
Maximum Distributed RAM (Kb)
Block RAM/FIFO w/ ECC (36 Kb each)
Total Block RAM (Kb)
CMTs (1 MMCM + 1 PLL)
Maximum Single-Ended I/O
Maximum Differential I/O Pairs
DSP Slices
PCIe® Gen2(1)
Analog Mixed Signal (AMS) / XADC
Configuration AES / HMAC Blocks
GTP Transceivers (6.6 Gb/s Max
Rate)(2)
Commercial Temp (C)
Extended Temp (E)
Industrial Temp (I)
Package(3), (4)

Dimensions
(mm)

Ball Pitch
(mm)

CPG236
CPG238
CSG324
CSG325
FTG256
SBG484
FGG484(5)
FBG484(5)
FGG676(6)
FBG676(6)
FFG1156

10 x 10
10 x 10
15 x 15
15 x 15
17 x 17
19 x 19
23 x 23
23 x 23
27 x 27
27 x 27
35 x 35

0.5
0.5
0.8
0.8
1.0
0.8
1.0
1.0
1.0
1.0
1.0

XC7A12T
12,800
2,000
16,000
171
20
720
3
150
72
40
1
1
1

XC7A15T
16,640
2,600
20,800
200
25
900
5
250
120
45
1
1
1

XC7A25T
23,360
3,650
29,200
313
45
1,620
3
150
72
80
1
1
1

XC7A35T
33,280
5,200
41,600
400
50
1,800
5
250
120
90
1
1
1

XC7A50T
52,160
8,150
65,200
600
75
2,700
5
250
120
120
1
1
1

XC7A75T
75,520
11,800
94,400
892
105
3,780
6
300
144
180
1
1
1

XC7A100T
101,440
15,850
126,800
1,188
135
4,860
6
300
144
240
1
1
1

XC7A200T
215,360
33,650
269,200
2,888
365
13,140
10
500
240
740
1
1
1

2

4

4

4

4

8

8

16

-1, -2
-2L, -3
-1, -2, -1L

-1, -2
-2L, -3
-1, -2, -1L

-1, -2
-2L, -3
-1, -2, -1L

-1, -2
-2L, -3
-1, -2, -1L

-1, -2
-2L, -3
-1, -2, -1L

-1, -2
-2L, -3
-1, -2, -1L

-1, -2
-2L, -3
-1, -2, -1L

-1, -2
-2L, -3
-1, -2, -1L

Available User I/O: 3.3V SelectIO™ HR I/O (GTP Transceivers)

106 (2)
112 (2)
150 (2)

106 (2)

106 (2)

210 (0)
150 (4)
170 (0)

210 (0)
150 (4)
170 (0)

210 (0)

210 (0)

170 (0)

170 (0)

250 (4)

250 (4)

285 (4)

285 (4)

112 (2)
210 (0)
150 (4)
170 (0)

150 (4)

285 (4)
250 (4)

285 (4)
300 (8)

Notes:

Page 3

1.
2.
3.
4.
5.
6.

Supports PCI Express Base 2.1 specification at Gen1 and Gen2 data rates.
Represents the maximum number of transceivers available. Note that the majority of devices are available without transceivers. See the Package section of this table for details.
Leaded package option available for all packages. See DS180, 7 Series FPGAs Overview for package details.
Device migration is available within the Artix-7 family for like packages but is not supported between other 7 series families.
Devices in FGG484 and FBG484 are footprint compatible.
Devices in FGG676 and FBG676 are footprint compatible.

300 (8)
400 (8)
500 (16)

Kintex-7 FPGAs
Optimized for Best Price-Performance
(1.0V, 0.95V, 0.9V)

Part Number
EasyPath™ Cost Reduction Solutions(1)
Slices
Logic Cells
CLB Flip-Flops
Maximum Distributed RAM (Kb)
Block RAM/FIFO w/ ECC (36 Kb each)
Total Block RAM (Kb)
CMTs (1 MMCM + 1 PLL)
Maximum Single-Ended I/O
Maximum Differential I/O Pairs
DSP48 Slices
PCIe® Gen2(2)
Analog Mixed Signal (AMS) / XADC
Configuration AES / HMAC Blocks
GTX Transceivers (12.5 Gb/s Max Rate)
Commercial Temp (C)
Extended Temp (E)
Industrial Temp (I)

Logic Resources

Memory
Resources
Clock Resources
I/O Resources

Integrated IP
Resources

Speed Grades

Package(3)
(4)

FBG484
FBG676(4)
FFG676
FBG900(4)
FFG900
FFG901
FFG1156

Footprint
Compatible
Footprint
Compatible

Dimensions
(mm)

Ball Pitch
(mm)

23 x 23
27 x 27
27 x 27
31 x 31
31 x 31
31 x 31
35 x 35

1.0
1.0
1.0
1.0
1.0
1.0
1.0

XC7K70T
—
10,250
65,600
82,000
838
135
4,860
6
300
144
240
1
1
1
8
-1, -2
-2L, -3
-1, -2

XC7K160T
—
25,350
162,240
202,800
2,188
325
11,700
8
400
192
600
1
1
1
8
-1, -2
-2L, -3
-1, -2, -2L

XC7K325T
XCE7K325T
50,950
326,080
407,600
4,000
445
16,020
10
500
240
840
1
1
1
16
-1, -2
-2L, -3
-1, -2, -2L

XC7K355T
XCE7K355T
55,650
356,160
445,200
5,088
715
25,740
6
300
144
1,440
1
1
1
24
-1, -2
-2L, -3
-1, -2, -2L

XC7K410T
XCE7K410T
63,550
406,720
508,400
5,663
795
28,620
10
500
240
1,540
1
1
1
16
-1, -2
-2L, -3
-1, -2, -2L

XC7K420T
XCE7K420T
65,150
416,960
521,200
5,938
835
30,060
8
400
192
1,680
1
1
1
32
-1, -2
-2L, -3
-1, -2, -2L

XC7K480T
XCE7K480T
74,650
477,760
597,200
6,788
955
34,380
8
400
192
1,920
1
1
1
32
-1, -2
-2L, -3
-1, -2, -2L

380, 0 (28)
400, 0 (32)

380, 0 (28)
400, 0 (32)

Available User I/O: 3.3V HR I/O, 1.8V HP I/Os (GTX)

185, 100 (4)
200, 100 (8)

185, 100 (4)
250, 150 (8)
250, 150 (8)

250, 150 (8)
250, 150 (8)
350, 150 (16)
350, 150 (16)

250, 150 (8)
250, 150 (8)
350, 150 (16)
350, 150 (16)
300, 0 (24)

Notes:
1.
2.
3.
4.

Page 4

EasyPath™ solutions provide a fast and conversion-free path for cost reduction.
Hard block supports PCI Express Base 2.1 specification at Gen1 and Gen2 data rates. Gen3 supported with soft IP.
See DS180, 7 Series FPGAs Overview, for package details.
GTX transceivers in FB packages support the following maximum data rates: 10.3Gb/s in FBG484; 6.6Gb/s in FBG676 and FBG900. See DS182, Kintex-7 FPGAs Data Sheet: DC and AC
Switching Characteristics, for details.

Virtex-7 FPGAs
Logic
Resources
Memory
Resources
Clocking
I/O
Resources

Integrated IP
Resources

Speed
Grades

Footprint
Compatible

Footprint
Compatible
Footprint
Compatible
Footprint
Compatible

Optimized for Highest System Performance and Capacity
(1.0V)
Part Number XC7V585T
XC7V2000T XC7VX330T XC7VX415T XC7VX485T XC7VX550T XC7VX690T
EasyPath™ Cost Reduction Solutions(1) XCE7V585T
—
XCE7VX330T XCE7VX415T XCE7VX485T XCE7VX550T XCE7VX690T
Slices
91,050
305,400
51,000
64,400
75,900
86,600
108,300
Logic Cells
582,720
1,954,560
326,400
412,160
485,760
554,240
693,120
CLB Flip-Flops
728,400
2,443,200
408,000
515,200
607,200
692,800
866,400
Maximum Distributed RAM (Kb)
6,938
21,550
4,388
6,525
8,175
8,725
10,888
Block RAM/FIFO w/ ECC (36 Kb each)
795
1,292
750
880
1,030
1,180
1,470
Total Block RAM (Kb)
28,620
46,512
27,000
31,680
37,080
42,480
52,920
CMTs (1 MMCM + 1 PLL)
18
24
14
12
14
20
20
Maximum Single-Ended I/O
850
1,200
700
600
700
600
1,000
Maximum Differential I/O Pairs
408
576
336
288
336
288
480
DSP Slices
1,260
2,160
1,120
2,160
2,800
2,880
3,600
PCIe® Gen2(2)
3
4
—
—
4
—
—
PCIe Gen3
—
—
2
2
—
2
3
Analog Mixed Signal (AMS) / XADC
1
1
1
1
1
1
1
Configuration AES / HMAC Blocks
1
1
1
1
1
1
1
GTX Transceivers (12.5 Gb/s Max Rate)(3)
36
36
—
—
56
—
—
GTH Transceivers (13.1 Gb/s Max Rate)(4)
—
—
28
48
—
80
80
GTZ Transceivers ( 28.05 Gb/s Max Rate)
—
—
—
—
—
—
—
-1, -2
-1, -2
-1, -2
-1, -2
-1, -2
-1, -2
-1, -2
Commercial Temp (C)
-2L, -3
-2L, -2G
-2L, -3
-2L, -3
-2L, -3
-2L, -3
-2L, -3
Extended Temp (E)(5)
-1, -2
-1
-1, -2
-1, -2
-1, -2
-1, -2
-1, -2
Industrial Temp (I)
Dimensions Ball Pitch
(6)
Package
Available User I/O: 3.3V HR I/O, 1.8V HP I/Os (GTX, GTH)
(mm)
(mm)
FFG1157(7)
35 x 35
1.0
0, 600 (20, 0)
0, 600 (0, 20) 0, 600 (0, 20) 0, 600 (20, 0)
0, 600 (0, 20)
FFG1761(7) 42.5 x 42.5
1.0
100, 750 (36, 0)
50, 650 (0, 28)
0, 700 (28, 0)
0, 850 (0, 36)
FHG1761
45 x 45
1.0
0, 850 (36, 0)
FLG1925
45 x 45
1.0
0, 1200 (16, 0)
FFG1158(7)
35 x 35
1.0
0, 350 (0, 48) 0, 350 (48, 0) 0, 350 (0, 48) 0, 350 (0, 48)
FFG1926
45 x 45
1.0
0, 720 (0, 64)
FLG1926
45 x 45
1.0
FFG1927(7)
45 x 45
1.0
0, 600 (0, 48) 0, 600 (56, 0) 0, 600 (0, 80) 0, 600 (0, 80)
FFG1928
45 x 45
1.0
FLG1928
45 x 45
1.0
FFG1930
45 x 45
1.0
0, 700 (24, 0)
0, 1000 (0, 24)
FLG1930
45 x 45
1.0
FLG1155
35 x 35
1.0
FLG1931
45 x 45
1.0
FLG1932
45 x 45
1.0

Notes:
1.
2.
3.
4.

XC7VX980T XC7VX1140T XC7VH580T
XCE7VX980T
—
—
153,000
178,000
90,700
979,200
1,139,200
580,480
1,224,000
1,424,000
725,600
13,838
17,700
8,850
1,500
1,880
940
54,000
67,680
33,840
18
24
12
900
1,100
600
432
528
288
3,600
3,360
1,680
—
—
—
3
4
2
1
1
1
1
1
1
—
—
—
72
96
48
—
—
8
-1, -2
-1, -2
-1, -2
-2L
-2L, -2G
-2L, -2G
-1
-1
—

XC7VH870T
—
136,900
876,160
1,095,200
13,275
1,410
50,760
18
300
144
2,520
—
3
1
1
—
72
16
-1, -2
-2L, -2G
—

1.8V HP I/O (GTH, GTZ)

0, 720 (0, 64)
0, 720 (0, 64)
0, 480 (0, 72)
0, 480 (0, 96)
0, 900 (0, 24)
0, 1100 (0, 24)
400 (24, 8)
600 (48, 8)
300 (72, 16)

5. -2G only applies to Stacked Silicon Interconnect devices and supports 12.5G GTX,
EasyPath™ solutions provide a fast and conversion-free path for cost reduction.
13.1G GTH, 28.05G GTZ with -2 fabric.
Hard block supports PCI Express Base 2.1 specification at Gen1 and Gen2 data rates. Gen3 supported with soft IP.
12.5 Gb/s support in "-3E", "-2GE" speed/temperature grade; 10.3125 Gb/s support in "2C", "-2LE", and "-2I" speed grade. 6. Leaded package options ("FFxxxx"/"FLxxxx"/"FHxxxx") available for all packages.
"HCxxxx" is not offered in a leaded option.
13.1 Gb/s support in "-3E". "-2GE" speed grade; 11.3 Gb/s support in "2C" , "-2LE" and "-2I" speed/temperature grades.
7. See DS180, 7 Series FPGAs Overview for package details.

Page 5

Device Ordering Information
XC

7

Commercial Generation
Xilinx

XC

7

Xilinx
Generation
Commercial

XC

7

Xilinx
Generation
Commercial

XC

7

Xilinx
Generation
Commercial

S

###

Family

Logic Cells
In 1K units

A

###

Family

C = Commercial (Tj = 0°C to +85°C)

###

Family

Logic Cells
in 1K Units

V

###

Family

Logic Cells
in 1K Units

Page 6

E = Extended (Tj = 0°C to +100°C)

FG

G

Speed Grade
Package Type
G: RoHS 6/6
-1 = Slowest
CP: Wire-bond (.5 mm)
-L1 = Low Power CS: Wire-bond (.8 mm)
-2 = Mid
FG: Wire-bond (1 mm)
FT: Wire-bond (1 mm)

-1

FB

A

484

C

Package
Designator

Package
Pin Count

Temperature
Grade
(C, I, Q)

484

C

Nominal
Package
Pin Count

Temperature
Grade
(C, E, I)

900

C

Nominal
Package
Pin Count

Temperature
Grade
(C, E, I)

1156

C

Nominal
Package
Pin Count

Temperature
Grade
(C, E, I)

G

Logic Cells Speed Grade
Package Type
V: RoHS 6/6
in 1K Units -1 = Slowest
CP: Wire-bond (.5 mm)
G: RoHS 6/6
-L1 = Low Power
CS: Wire-bond (.8 mm) w/Exemption 15
-L2 = Low Power FB: Bare-Die Flip-Chip (1 mm)
-2 = Mid
FF: Flip-Chip (1 mm)
-3 = Highest
FG: Wire-bond (1 mm)
FT: Wire-bond (1 mm)
SB: Bare-Die Flip-Chip (.8 mm)

K

Notes:
-L1 is the ordering code for the lower power, -1L speed grade.
-L2 is the ordering code for the lower power, -2L speed grade.

-1

-1

FF

G

Speed Grade
Package Type
V: RoHS 6/6
-1 = Slowest
FB: Bare-Die Flip-Chip (1 mm) G: RoHS 6/6
-L2 = Low Power
FF: Flip-Chip (1 mm)
w/Exemption 15
-2 = Mid
-3 = Highest

-1

FF

G

Speed Grade
Package Type
V: RoHS 6/6
-1 = Slowest
FF: Flip-Chip (1 mm)
G: RoHS 6/6
-2 = Mid
FH: Flip-Chip (1 mm)
w/Exemption 15
-L2 = Low Power
FL: Flip-Chip (1 mm)
-3 = Highest
HC: Ceramic Flip-Chip (1 mm)

I = Industrial (Tj = –40°C to +100°C)

Q = Expanded (Tj = –40°C to +125°C)

Digital Signal Processing Metrics
XC7S6
XC7S15
XC7S25
XC7S50
XC7S75
XC7S100

DSP Slice Count
10
20
80
120
140
160

XC7A12T
XC7A15T
XC7A25T
XC7A35T
XC7A50T
XC7A75T
XC7A100T
XC7A200T

40
45
80
90
120
180
240

XC7K70T
XC7K160T
XC7K325T
XC7K355T
XC7K410T
XC7K420T
XC7K480T

240

XC7V585T
XC7V2000T
XC7VX330T
XC7VX415T
XC7VX485T
XC7VX550T
XC7VX690T
XC7VX980T
XC7VX1140T
XC7VH580T
XC7VH870T

Spartan®-7 FPGAs
Speed grade
FMAX [MHz]
Max GMAC/s

-1
464
148

-2
550
176

Artix®-7 FPGAs
Speed grade
FMAX [MHz]
Max GMAC/s

-1
464
686

-2
550
814

-3
628
929

-1
464
1,781

-2
550
2,112

-3
741
2,845

-1
547
2,756

-2
650
3,276

-3
741
3,734

Kintex®-7 FPGAs
Speed grade
FMAX [MHz]
Max GMAC/s

740
600
840
1440
1540
1680

Virtex®-7 FPGAs
Speed grade
FMAX [MHz]
Max GMAC/s

1920
1260
2160
1120
2160

2800
5760
3600
3600
3360
1680
2520
For more information, refer to: UG479, 7 Series FPGAs DSP48E1 Slice User Guide
Important: Verify all data in this document with the device data sheets found at www.xilinx.com

Page 7

Block RAM Metrics
XC7S6
XC7S15
XC7S25
XC7S50
XC7S75
XC7S100
XC7A12T
XC7A15T
XC7A25T
XC7A35T
XC7A50T
XC7A75T
XC7A100T
XC7A200T
XC7K70T
XC7K160T
XC7K325T
XC7K355T
XC7K410T
XC7K420T
XC7K480T
XC7V585T
XC7V2000T
XC7VX330T
XC7VX415T
XC7VX485T
XC7VX550T
XC7VX690T
XC7VX980T
XC7VX1140T
XC7VH580T
XC7VH870T

Block RAM Capacity (Mb)
180
360
1620
2700
3240
4320

Spartan-7 FPGAs
Speed grade
True dual-port Block RAM FMAX [MHz]

-2
461

-1
388

-2
461

-3
509

-1
458

-2
544

-3
601

Artix-7 FPGAs

720
900
1620
1800
2700

Speed grade
True dual-port Block RAM FMAX [MHz]
3780
4860

Kintex-7 and Virtex-7 FPGAs
13140

Speed grade

4860

True dual-port Block RAM FMAX [MHz]

11700
16020
25740

28620
30060
34380
28620
46512
27000
31680
37080
42480
52920
54000
67680
33840
50760
For more information, refer to: UG473, 7 Series FPGAs Memory Resources User Guide
Important: Verify all data in this document with the device data sheets found at www.xilinx.com

Page 8

-1
388

High-Speed Serial Transceivers
7 series devices provide a broad portfolio of transceivers for applications ranging from low-cost consumer
products to high-end networking systems.
GTP = 6.6 Gb/s
GTP
GTX
GTH
GTZ
Total Transceiver Count
GTX = 12.5 Gb/s
XC7A12T
2
GTH = 13.1 Gb/s
XC7A15T
4
XC7A25T
4
GTZ = 28.05 Gb/s
XC7A35T
XC7A50T
XC7A75T
XC7A100T
XC7A200T

XC7K70T
XC7K160T
XC7K325T
XC7K355T
XC7K410T
XC7K420T
XC7K480T
XC7V585T
XC7V2000T
XC7VX330T
XC7VX415T
XC7VX485T
XC7VX550T
XC7VX690T
XC7VX980T
XC7VX1140T
XC7VH580T
XC7VH870T

4
4

For more information, refer to:
UG482, 7 Series FPGAs GTP Transceivers User Guide
UG476, 7 Series FPGAs GTX/GTH Transceivers User Guide

8
8
16
8
8
16
24
16
32
32
36
36
28
48

56
80
80
72
96
48

88
72

Important: Verify all data in this document with the device data sheets found at www.xilinx.com
Page 9

16

Transceiver Aggregate Bandwidth
7 series devices provide a broad portfolio of transceivers for applications ranging from low-cost consumer
products to high-end networking systems.
GTP

Transceiver Aggregate Bandwidth
XC7A12T
XC7A15T
XC7A25T
XC7A35T
XC7A50T
XC7A75T
XC7A100T
XC7A200T
XC7K70T
XC7K160T
XC7K325T
XC7K355T
XC7K410T
XC7K420T
XC7K480T
XC7V585T
XC7V2000T
XC7VX330T
XC7VX415T
XC7VX485T
XC7VX550T
XC7VX690T
XC7VX980T
XC7VX1140T
XC7VH580T
XC7VH870T

26
52
52
52
52

GTX

GTZ

Maximum Line Rates
GTP = 6.6 Gb/s
GTX = 12.5 Gb/s
GTH = 13.1 Gb/s
GTZ = 28.05 Gb/s

105
105
211

For more information, refer to:
UG482, 7 Series FPGAs GTP Transceivers User Guide
UG476, 7 Series FPGAs GTX/GTH Transceivers User Guide

106
200
400
600
400
800
800
900
900
733.6

1257.6
1400
2096
2096
1886.4
2515.2
1257.6

448.8
1886.4

Important: Verify all data in this document with the device data sheets found at www.xilinx.com
Page 10

GTH

896

I/O Count and Bandwidth
XC7S6
XC7S15
XC7S25
XC7S50
XC7S75
XC7S100
XC7A12T
XC7A15T
XC7A25T
XC7A35T
XC7A50T

100 125
100 125
150

187.5
250

150

I/O Bandwidth = Total I/O x LVDS Performance

312.5
400

500

400

500

187.5
250

150

Total I/O Count
Total Bandwidth in Gb/s

312.5

187.5
250

312.5

250

312.5

XC7A75T

300

375

XC7A100T

250

375

XC7A200T
XC7K70T

500
480

300

XC7K160T

640

400

XC7K325T
XC7K355T

625

800

500
480

300

XC7K410T

800

500

XC7K420T

400

640

XC7K480T
XC7V585T
XC7V2000T
XC7VX330T

400

650

1120

700
960

600

XC7VX485T
XC7VX550T
XC7VX690T

1120

700
960

600

1600

1000

XC7VX980T

1440

900

XC7VX1140T

Page 11

1680

1200

XC7VX415T

XC7VH580T
XC7VH870T

1360

850

1100
600
300

420

840

1760
Important: Verify all data in this document
with the device data sheets found at www.xilinx.com.

References
DS180, 7 Series FPGAs Overview
DS181, Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182, Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS183, Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics
UG470, 7 Series FPGAs Configuration User Guide
UG471, 7 Series FPGAs SelectIO Resources User Guide
UG472, 7 Series FPGAs Clocking Resources User Guide
UG473, 7 Series FPGAs Memory Resources User Guide
UG474, 7 Series FPGAs Configurable Logic Block User Guide
UG475, 7 Series FPGAs Packaging and Pinout User Guide
UG476, 7 Series FPGAs GTX/GTH Transceivers User Guide
UG479, 7 Series FPGAs DSP48E1 Slice User Guide
UG480, 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS ADC User Guide
UG482, 7 Series FPGAs GTP Transceivers User Guide
UG483, 7 Series FPGAs PCB Design Guide
Important: Verify all data in this document with the device data sheets found at www.xilinx.com

XMP101 (v1.7)

© Copyright 2014-2018 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCIe, and PCI Express are
trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.

Page 12



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Description                     : 7 Series Product Tables and Product Selection Guide
Title                           : 7 Series Product Tables and Product Selection Guide
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Subject                         : 7 Series Product Tables and Product Selection Guide

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