800106_AGC 1_Users_Manual_Aug86 800106 AGC 1 Users Manual Aug86
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GENERAL INFORMATION First Edition August 1986 PART NO. 800106 FORCE COMPUTERS Inc.lGmbH All Rights Reserved This document shall not be duplicated, nor its contents used for any purpose, unless express permission has been granted. Copyright by FORCE Computers® ROT E The information in this document has been carefully checked and is believed to be entirely reliable. FORCE COMPUTERS makes no warranty of any kind with regard to the material in this document, and assumes no responsibility for any errors that may appear in this document. FORCE COMPUTERS reserves the right to make changes without notice to this, or any of its products, to improve reliability, performance or design. FORCE COMPUTERS assumes no responsibility for the use of any circuitry other than circuitry which is part of a product of FORCE COMPUTERS GmbH/Inc. FORCE COMPUTERS does not convey to the purchaser of the product described herein any license under the patent rights of FORCE COMPUTERS GmbH/Inc. nor the rights of others. FORCE COMPUTERS Inc. FORCE COMPUTERS GmbH 727 University Avenue Los Gatos, CA 95939 U.S.A. Daimlerstrasse 9 D-89l2 Ottobrunn/Munich West Germany Phone : (498) 354 34 19 172465 Telex FAX (498) 395 77 18 Phone Telex FAX FORCE COMPUTERS FRANCE SarI FORCE Computers UK Ltd. 11, rue Casteja 92199 Boulogne France No. 1 Holly Court 3 Tring Road Wendover Buckinghamshire HP22 6NR England Phone Telex Fax (1) 4629 37 37 296 394 forc-f (1) 4621 35 19 Phone Telex Fax (989) 699 91-9 524199 forc-d (989) 699 77 93 (9296) 625456 838933 (9296) 624927 1. GENERAL INFORMATION TO THE 63484 ACRTC The ACRTC is a high performance graphics-controller, compatible to the 68000 family of microprocessors. The ACRTC concept is to incorporate major functionality with effective graphic commands. High level command language increases performance and reduces software development costs. In this way, the ACRTC converts logical x - y coordinates to physical frame buffer addresses. It supports 38 commands, including LINE, RECTANGLE, POLYLINE, POLYGON, CIRCLE, ELLIPSE, ARC, ELLIPSE ARC, FILLED RECTANGLE, PAINT, PATTERN and COPY. An on-chip 32byte pattern RAM can be used for powerful graphic environments. Conditional drawing functions are useful for drawing patterns, colour mixing and software windowing. The drawing area control supports clipping and hitting. The ACRTC is able to control four hardware windows, zooming and smooth scrolling in both vertical and horizontal directions. The capability of displaying up to 256 colours and the maximum drawing speed of 2 million Pixel per second in monochrome and colour applications allows high performance CAD terminals to be used. 1-1 Features of the 63484 ACRTC: Up to 4996 by 4996 bit map graphic display and/or 256 lines by 256 characters by 32 rasters character display. Separate bit map graphic (2Mbyte) and character (128Kbyte) address spaces with combined graphic/character display. Three horizontal split screens and one window screen. Size and position fully programmable. Independent horizontal and vertical smooth scroll for each screen. 1 to 16 zoom magnitude - independent x and y factors. Logical pixel specification as 1, 2, 4 , 8 or 16 bits for monochrome, gray scale and colour displays. Programmable address increment supports frame buffer memory width up to 128 bits for video bit rates greater than 599 MHz. Unique interleaved access mode for "flashless" displays. ACRTC provides dynamic RAM refresh. Asynchronous bus interface, optimised for the 68999 MPU family and the 68459 DMAC (16bit data bus). Separate on-chip l6byte READ and WRITE FIFOs. Maskable interrupts including FIFO status. Full programmability of CRT timing signals. - Three raster scan modes. Master or Slave synchronization to multiple ACRTCs or other video generating devices. Programmable cursor and display timing skew. Eight user definable video attributes. Light pen detection. 1-2 2. IMPLEMENTATION OF THE 63484 ACRTC ON THE AGC-l The AGC-l is a highly integrated graphic-system on two doubleeuroboards, based on the 63484 ACRTC. With the optional SYS68K/AGC-lX board, it offers two bus interfaces and allows the board set to be used in single-processor as well as in high end multi-processor applications. The board has a jumper selectable access address within the 16Mbyte address range. Also the VMEbus or VMXbus access is selectable. The on-board video RAM of 2Mbyte is dual ported and in this way directly accessible by either the processor or a DMA Controller for high speed display manipulation. The Pixel clock of 64MHz offers resolutions up to 1924 X 899 noninterlaced with 4 bits per pixel. With the on-board colour palette, the user has the choice of up to 256 colours out of 16 million. With the implementation of the dual access mode, the ACRTC display and drawing accesses are interleaved and so the ACRTC reaches the maximum drawing speed without a nflashingn display. The complex attribute logic offers a great variety of display modes, e.g. blinking, inverse video, conditional blinking. The AGC-lX board adds powerful character overlay with a separate character and attribute RAM, a software loadable character generator, the 68459 DMA Controller, which is used for VMEbus data transfers, two serial I/O interfaces for printer, mouse or digitizer and the VMXbus interface. 2-1 Figure 2-1: Block Diagram of the SYS68K/AGC-l II r:=nliI dl§ ~~ ~Il'>I ------' >' L~~~t 1 "I .J ACRTC 63484 81M 681 S3 Interface I III Converter and Control Timing Generator Colour Look-up Table Colour look-up Table Colour Look-up Table red green blue DAU DAU DAU Storage Register "1---------1 Video Memory 2-2 Features of the SYS68K/AGC-l: 63484 ACRTC with a clock frequency of 8MHz. 3 x AM8l5l graphic colour palette with 16/256 entries. 68153 Bus Interrupter Module for all local interrupts. 2Mbyte of video RAM directly accessible from the VMEbus R-, G-, B- and composite SYNC output. External synchronization input/output for other AGCs. Light pen interface. Fully buffered local address, data and control bus. VME/PlB14 interface (16 bit). Software selectable interrupt request level and programmable interrupt vector. The following SYS68K/AGC-l: table shows the general memory lay-out of the The board start address steps. Table (BBA) is jumper selectable in 256Kbyte 2-1: The Address Map Start Address End Address Memory Area BBA BBA + $33FFF Occupied for the SYS68K/AGC-IX boards BBA + $34999 BBA + $35FFF BIM 68153 BBA + $36999 BBA + $37FFF GCP 1 red BBA + $38999 BBA + $39FFF GCP 2 green BBA + $3A999 BBA + $3BFFF GCP 3 blue BBA + $3C999 BBA + $3FFFF ($3DFFF) ACRTC 63484 BBA + $3E999 BBA + $3FFFF Interrupt-Register VMX-Option BBA + $49999 BBA + $23FFFF Video-RAM ------------------------------------------------------------------ The Board Base Address is set by default during manufacturing to $C99999 (Start Address) / $E3FFFF (End Address). 2-4 INSTALLATION FORCE COMPUTERS Inc.lGmbH All Rights Reserved This document shall not be duplicated, nor Its contents used for any purpose, unless express perrrission has been granted. Copyright by FORCE CorrputersJ~ 0 J22 l:J ~ J. DO CJ 51 J70 J21 DO D6 Q: J48 o n J16 EJ CJ J66 o~ n m z~ ~~ CJ Qi B14, B15, B16 AND B17 Locations Diagram J5 J57 C3 C7 -f;l J32 ~·o ~~J31D D J1 J2 0 0 + ~ 0 J34 J47 ~ D D~~ o ~~ D DD ~ 0 Do DOO D ~ DO ~; mdO oDo Do C17 J94 J28 J30 J7 J25 JI7 ~ n~' ~ ~ Q~ ~ ~ ~[rOoOou 0 0;' J9 J6 4-51 J92 J91 J76 J26 Table 4-15: Jumper Settings of Bl~ B15, B16 AND B17 JUMPER B14 JUMPER B15 DEFAULT CONDITION DEFAULT CONDITION 1 16 1 2 3 2 15 4 5 6 3 14 7 8 9 4 13 10 11 12 5 12 13 14 15 6 11 16 17 18 7 10 19 20 21 8 9 22 23 24 JUMPER B16 JUMPER B17 DEFAULT CONDITION DEFAULT CONDITION 1 8 1 2 3 2 7 4 5 6 3 6 7 8 9 4 5 10 11 12 13 14 15 16 17 18 19 20 21 4-52 4.9 Addressing the ACRTC 63484 The ACRTC incorporates more than 200 byte of internal control registers and control RAM which is accessible by the host processor. There is a distinction between two ways of accessing these registers. At first there are the direct addressable registers, the STATUS Register, the ADDRESS Register and the FIFO ENTRY. The STATUS and the ADDRESS register are distinguished by the R/WSignal. The Status register is read-only and the Address registers are write only. The addresses of these registers are located at address BBA + $3C000 for Standard Memory access (see Chapter 4-1). The second group are the indirect addressable registers, which are partioned in two groups. a) Directly Accesible Register These registers are accessed by writing the register address into the ADDRESS register and reading and writing the data over the FIFO ENTRY. b) FIFO Accessible Register These registers are accessed by writing the FIFO address ($00) into the ADDRESS register. After operation, the READ or WRITE PARAMETER REGISTER command with the respective register address written into the FIFO. The programming model is shown in Table 4-16 and the time are listed in Table 4-16. Figure ACRTC. values 4-13 shows the access timing from the VMEbus to the For the detailed register descriptions following terminology is used. in this chapter, 63484 the For directly accessible registers, the register address is shown as 'rNN' where NN is interpreted as an 8 bit hexadecimal value. For example, the Zoom Factor register address is $EA hexadecimal, so the ZFRs register address is shown as 'rEA'. For FIFO accessible Drawing Parameter registers, the register address is shown as 'PrNN'. For example, the Colour Comparison register is addressed as parameter register $2 hex, so the CMP register address is shown as 'Pr02'. When register diagrams are shown, unused bits will be marked with x. Unless stated otherwise, unused bits may be freely written with any value, and that value will be returned on subsequent reads of the register. 4-53 Table 4-16: PROGRAMMING MODEL 7 15 I I Status Register Hardware , / Oil Access ........ I 0 ,/' .... "" ................ , .... [~~~__-_-_-___FJfQ_E~ii~=====~~ I I I o 15 Address R!:l!ister Command Control Register Write FIFO I \ \\\:'~~. . . . . .:'-L____________ I \\ ~-------------, ..J O~eration Mode Re~ister .... l Display Control Register Timing C::ontrol ~A~ Raster Counter Horizontal Sync. Horizontal Display Vertical Sync. \ \ \ \ Read FIFO \ \ \ \ \ Vertical Display -JJl Split Screen Width 1L-_~C~o~m~m~an~d~R_eg~i~st_e_r____ Blink Control Horizontal Window Display / Vertical Window Display Direct Access Control Register Graphic Cursor Display Control RAM Split Screen 0 Control (Upper Screen) Spl it Screen 1 Control (Base Screen) Pattern RAM 16 x 16 "- Split Screen 2 Control (Lower Screen) Color 0 Color 1 Color Comparison Edge_~olor Split Screen 3 Control (Window Screen) Block Cursor Mask Pattern RAM Control Drawing Parameter Register Cursor Definition Zoom Facter " FIFO Access Area Definition ReadIWrite Pointer Light Pen Address Drawing Pointer Current Pointer 4-54 1..1 Table 4-16: CS RS W Reg. No. 1 0 0 0 AR 0 1 SR I/o rOO 1.' r02 1.'0 r04 1'-0 r06 r08 (con't) Programming Model Register Name AR SR FE CCR OMR OCR Address Register Status Register FIFO Entry Command Control Oper ation Mode Display Control ABT PSE OOM COM ORC MIS STR ACP WSS CSK OSP SE 1 SEO SE2 Address CER ARO CEO LPO RFF RFR WFR WFE . FE GBM CRE ARE CEE LPE RFE RRE WRE WEE OSK RAM GAl ACM RSM SE3 AT R (undefined) rjE rOO Raster Count to r82 Horizontal Sync. r84 Horizontal Display RCR r86 Vertical Sync. Vo Va i88 VertiCal Display 1"0 rSA RC HSR HDR HC HOS VSR VDR V 0 S HSW HOW vc VSW S P 1 \,o~ Split Screen Width _S~Pcc0:C-_ _ _ _ _ _ _ _ _---i SSW to rBE S P 2 '"0 r90 Blink Control t'o r92 Horizontal Window Display BeR HWR :~:~ VWR 4 Vertical Window Display BOFFl-~-o.-'"BON~2;---'I----nB"'oF~ BONl § H WS H WW ~ r% : ; CXE ~ Graphic Cursor CXS GCR CVS Va; r9C eYE I .~ .-I :~: o 1 ~o rCO Raster Addr.O ~ rC2 Upper 1 RAROl 1/01 re6 1 ~ --t---'-:...... !. Start Addr.D 1 i I 1~ S A a L ~~ Raster Addr.2 ~Lower ~dth I 0 rD6 RAR2, 2 i,MWR2 I SAR2 Start Addr.2 I ! .. ~~ Ict!IlL~:= .. i ....... -----------1 ==r:::=~=T f----, - L R A2 F RA 2 --j I :::::r=.~W,2 ......'~ ---SA _ - 1I _ SO A 2 - ,.F R Al ...........:::r----SA1H;SFiAi~ I------~-- -~-----~rt-L~----~' SARI A.~ SAOHSRAQ-- -L,-,- IStart Addr.! ~,Screen .. · RARl ........ J:. ..R....A-L-···:,~. MWRl JC~ .....~..lM W1 rCClscreen~----r- "~~--l -SllAT 1101 F R MWO S0 A0 I SARO Raster Addr.l Memory Width 1 Base ~~. L R A 0 ~~ _ _ .... MWR~ .. ~__ Memory Width 0 1'0 rC4 Screen :1'0 rCB I I (undefined) SA2H'SRA2 2 L tS-;~~. WIndow ~::~yA~~~;~ 3 I ~~;tcHRf·~;c-=~R.A 3 - - ~~=iivi-i=L-=I~~~=_~ 10'rOC:Screen :10 rDE1 Start Addr.3 rEO, - - - - - - rE2iBlock Cursor 1 110 I 110 i I ~l.-- I SOA3---r ............ SA3H/SRA3 ,I Cursor2" ~ B C W2 BCUR2!---- ~-------'--i I---BCSRT---I-'~:-:-I---BCER2-- - - - --S-C-AY--- ----"--.-. .-. II~: ;~n~r~~:'~~=~-~ ~~~ [c ~h~Qi'-f ~}-~;1_-_-kI----:~~-;-~2;~~~F2-_ ;#1 LI~htPe~ A~dress ~.- 1 rEC I : ~} j C= -:.-=-_- -=~==-=L~Urfdundefined) _ _~__L~ Note ! I _ _ LPAR 1 ..... "High" level O. "Low" level Register No. Read! Write LP ___________ _ Name of Register Pattern RAM Control ADR RIW Area Definition •• PrOB PrOC R/W PrOD Pr10 R Pr11 Pr12 Pr13 R Read Write Pointer Drawing Pointer Current Pointer •• ...... : L P A H ~T_~===-::-"':"::::'=--- Pr07 PrOB I c----::::..=-T-~··--s·At L' ---. ------·----1 ....... IBCUR1~---~-'---'---------B C A-T~ ---- ~---------+~BIOCk I 1 SAR3 --+--~-BCWI--,-m-8CSRTu--T-:::·:~··~·:~:-T·-mBC~l--' DP CP Pr14 Pr15 II .. Always set to "0" .... Set binary complements for negative values of X and Y axis. 4-55 This page is intentionally left blank. 4-56 Figure 4-13: Access to the 63484 ACRTC READ CYCLE FOLLOWED BY WRITE CYCLE INPUTS S T •• II. . C MEMORV •• SHOWN 5······· ·t······ ·C················· .~~~~ .............. ~~~~ JI • I J I I,... ,. ,. ,.. ... MIN 4BIT II l1li ........ ," . ,..... ,... ,. . . . RES J I I I' I I I I I , 5 I I T 1 I I I I I 11 , I I 1" , I I I I I I I I , I I I C I 1.1 .. . " .. ,.. " ...... ,., .... ,.... ,',.,'" I I... , ,,,.. , ,... , CLOCK ,,,,,,,,~~~l, ,,.,,,,,,,,.,.I~~~l, ,,.,,,,,.... ,. P~~S~~T 5 T C NEXT I........... " .. IJ a. .. ... .,RDDR .~~~-'. ... ,.,,,,.,.,I"'"--"~~I, .. .. ... .. ... .. HOME DRTR DIsTRNCE TIME RDDR II. II • .. ,.,... M~RKER 51. sTRRT MRG 5 -00034 0111 1111 CURSOR C +00031 0101 1000 TRIGGER T +00000 1111 1110 -2299 5-T +000.34 US C-T +000.31 US CI c-s +000.65 US _ - - - - - - - +1791 4-57 Table 4-17: I I I ~ values Qf g VMEbus access to the 63484 ACRCT Characteristics I I min. I I max. 1---------------------------------------------------I I I AS low to DTACK low I I 31~ns I I 37~ns DS low to DTACK low 28~ns 36~ns AS low to CRTEN low 9~ns ll~ns I I I 7~ns 9~ns 66~ns I I I I I I WRITE Cycle Time I I I As low to DTACK high I I I I I DS low to CRTEN low ---------------------------------------------------READ Cycle Time AS low to DTACK high I I 69~ns 1---------------------------------------------------I I I 4-58 61~ns I I I I 69Bns 4.9.1 ADDRESS Register JARl Write Only Low-order High-order I I I I I I I 15 I 14 I 13 I 12 I 11 I I I I I I I I I X I I I X I I I X I I I X I I I X I l~ I I X I I I I I I I I I I I I 9 I 8 I 7 I 6 I 5 I 4 I 3 I 2 I 1 I I I I I I I I I I I I I I I X I X I I I I ADD RES S The AR is a write only register used to specify the address $FF) of the ACRTC control register to be accessed. AR should be loaded with ~ ($~ to access the READ and WRITE FIFO's. The Timing Control RAM and Display Control RAM occupy the register address space from r8~-r9F and rC~-rEF respectively. To support block move type initialisation/access of these registers, reads and writes to the register address space r8~-rFF results in automatic incrementing of the AR. Therefore, the programmer need not explicitly address each register for sequential access. AR is not incremented for accesses from 4-59 r0~ to r7F. ~ I I I 4.9.2 lQBl Read Only Status Register High-order Low-order 1 1 1 1 1 1 1 1 1 1 1 I 1 1 I 1 I 1 15 1 14 1 13 1 12 1 11 1 10 I 9 1 8 1 7 I 6 1 5 1 4 I 3 1 2 1 1 1 0 1 1 I 1 1 1 1 1 I 1 1 I 1 I 1 1 I 1 1---------------------------------------------------------------------1 1 1 1 1 1 1 1 I 1 I 1 1 1 1 / / / / X I / X I 1 I X / X 1 1 I X / X 1 / X / X /CERIARDICEDILPDIRFFIRFRIWFRIWFEI I 1 I 1 I 1 I 1 I I 1 The SR is a read-only register containing 8 bits which reflect the state of internal status flags. If enabled by an interrupt enable bit in the CCR, a 1 bit in the corresponding SR flag will cause an interrupt to be generated. After a hardware reset, the CED, WFE and WFR bits are set to 1 and all other bits are reset to 0 ($FF23). The status register bits are briefly described below: * Command Error Flag (CER: bit 7) CER set to 1 indicates that the ACRTC has detected undefined command or invalid parameter. CED is cleared by setting the ABT bit in the CCR = 1. * an Area Detect Flag (ARD: bit 6) ARD is set to 1 depending on the AREA mode programmed for ACRTC graphic drawing commands. The ARD flag allows the host to detect whether the ACRTC has performed clipping or hitting during graphic drawing. ARD is cleared by execution of the RPR (Read Parameter Register) command or by setting the ABT bit in the CCR = 1. * Command End (CED: bit 5) CED set to 1 indicates that the ACRTC is able to accept new command. CED is cleared by writing a command to the write FIFO. * a Light Pen Detect (LPD: bit 4) LPD set to 1 indicates that the light pen strobe occured and the Light Pen Address Register contains latched address. LPD is cleared by reading the LPAR or setting the ABT in CCR to 1. 4-60 has the bit * Read FIFO Full (RFF: bit 3) RFF set to 1 indicates that the read FIFO is full (contains 8 words of data). RFF is cleared by reading at least one word from the FIFO or setting the ABT bit in CCR to 1. * Read FIFO Ready (RFR: bit 2) RFR set to 1 indicates that the read FIFO contains one more words of data. RFR is cleared by reading all data from the read FIFO. * or Write FIFO Ready (WFR: bit 1) WFR set to 1 indicates that the write FIFO is not full, and host writes can occur. WFR is also set to 1 when the ABT bit in CCR is set to 1. WFR is cleared when the write FIFO contains 8 words of data. * Write FIFO Empty (WFE: bit B) WFE set to 1 indicates that the write FIFO is empty. WFE is also set to 1 when the ABT bit in CCR is set to 1. WFE is cleared when a 16 bit word data is written to the write FIFO. 4-61 4.9.3 FIFO Entry (FE: r00-r01) High-order Low-order 1 1 1 1 1 I 1 I I I I 1 1 1 1 1 1 I 15 1 14 1 13 I 12 1 11 I 10 I 9 I 8 I 7 I 6 I 5 I 4 1 3 I 2 I 1 1 0 I I I I 1 1 I I I I 1 I 1 1 I I 1 I 1---------------------------------------------------------------------1 1 1 F 1 E I 1 1 When the AR contains the FIFO Entry addres (r00), reads and writes to the ACRTC utilize the corresponding 8 word read or write FIFO. In DMA transfer mode, the read and write FIFO's are selected regardless of the contents of AR and AR remains unchanged. 4-62 4.9.4 Command Control Register (CCR~ r~2-r~3) High-order Low-order I I I I I I I I I I I I I I I I I I 15 I 14 I 13 I 12 I 11 I l~ I 9 I 8 I 7 I 6 I 5 I 4 I 3 I 2 I 1 I ~ I I I I I I I I I I I I I I I I I I 1---------------------------------------------------------------------1 I I I I I I I I I I I I I I I IABT IpSE IDDM I ~ IDRC 1 G B M ICREIAREICEEILPEIRFEIRREIWREIWEEI I I I I I I I I I I I I I I I CCR controls command processing and enabling and disabling of interrupt requests. The 8 interrupt enable bits in the lower byte of CCR correspond directly to the 8 status flags in the Status register. After hardware reset, the ABT bit is initialised to 1 other CCR bits are initialised to ~. • and all Abort (ABT: bit 15) ABT FUNCTION ACRTC command execution is enabled. When ABT is changed from ~ to 1, the ACRTC cannot access the FIFO's until the Host issues a com and. 1 • ACRTC command execution is aborted and the read/write FIFOs are cleared. The Status register is set to $23. Setting the ABT bit to 1 is equivalent to hardware reset assertion. Pause (PSE: bit 14) PSE FUNCTION o ACRTC command execution is resumed. 1 ACRTC command execution is halted until PSE is reset to ~. ACRTC DMA (Data and Parameter) is halted until PSE is reset to 0. 4-63 * DATA DMA Mode (DDM: bit 13) DDM * FUNCTION 8 Data DMA transfer mode is disabled. 1 Data DMA transfer mode is enabled. Whether DMA is burst or cycle steal mode is determined by DRC (bit 11). DDM must be set before DMA data transfer commands are issued. DMA Request Control (DRC: bit 11) DRC 8 1 * FUNCTION BUrst Mode: /DREQ is designated as a level signal. A maximum words data is transferred per DMA request. Cycle Steal Mode: /DREQ is designated as a pulse signal. for each word. /DREQ is of 8 output Graphic Bit Mode (GBM: bit 18 - bit 8) GBM Mode t of colours Pixel/word 888 1 bit/pixel 1 16 not supported 881 2 bit/pixel 4 8 not supported 818 4 bit/pixel 16 4 supported In1 8 bit/pixel 256 2 supported 188 16 bit/pixel 65536 1 not supported 181 I N V A LID III 4-64 Interrupt Enable Bit (IE: bit 7 - bit ~) An interrupt is generated when an event flag in the Status register and the corresponding interrupt enable bit are both set to 1. Bit Name Set to 1 enables interrupt for 7 Command Error CRE Command Error 6 Area Detect ARE Clipping and Hitting detection 5 Command End CEE Command Termination 4 Light Pen Detect LPE Light Pen Strobe asserted 3 Read FIFO Full RFE Read FIFO Full 2 Read FIFO Ready RRE Read FIFO Ready 1 Write FIFO Ready WRE Write FIFO Ready 0 Write FIFO Empty WEE Write FIFO Empty 4-65 ... 4.9.~ Operation Mod~ Register (OMR: r04-r05) Low-order High-order I I I I 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 I 4 1 3 1 2 1 1 1 0 1 1 1 1 1 1 1 I 1 1 1 1 1 1 1 1 1 1 1---------------------------------------------------------------------1 I 1 1 1 1 1 1 1 1 1 1 1 1 IM/S ISTR IACP 1 0 1 CSK 1 DSK 1 0 1 0 1 1 1 1 1 ACM 1 RSM 1 1 1 1 1 1 1 1 1 1 1 1 1 1 OMR determines major operating parameters and modes of the ACRTC. The two most significant bits (M/S and STR) are reset to 0 and all other bits are unaffected by a hardware reset. * Master/Slave (M/S: bit 15) M/S defines whether the ACRTC operates as a master or slave when combined with other ACRTCs or video generating devices. M/S * FUNCTION o Slave Mode: ACRTC internal operations are reset on the rising edge of the /EXSYNC input. 1 Master Mode: /EXSYNC is defined as an output. For non-interlace modes, the /EXSYNC output timing is the same as /VSYNC output timing. For interlace modes, the /EXSYNC output timing is generated by the /VSYNC output for the odd field. Start (STR: bit 14) The STR bit is used to start and stop ACRTC operation. Initializing of registers which control basic ACRTC operation should only be performed when STR is reset to 0. STR FUNCTION o ACRTC display and drawing operations are halted. The DRAM refresh address is output on the MAD lines and the internal time base for CRT control signals is reset. 1 ACRTC starts display and drawing operations. Drawing commands halted when STR was reset to 0 are resumed. 4-66 * Drawing Access Priority (ACP: bit 13) ACP determines whether or not the ACRTC executes drawing operations on the frame during the display refresh period. ACP * FUNCTION o Display Priority Mode: During the display period, the ACRTC halts drawing operations. Thus 'flashing' due to simultaneously display and drawing access of the video memory is eliminated. Drawing operations are performed during horizontal and vertical retrace. In Interleaved Access Mode drawing can occur simultaneously with display, without 'flashing', since display and drawing accesses to the video memory are interleaved. In Superimposed Access Mode, flashless Background screen drawing may occur during idle window display cycles. 1 Drawing Priority Mode: Drawing is performed during display period. To reduce the 'flashing' effect caused by drawing-display contention the ACRTC may be programmed to drive the /DISP signals to the inactive high level during drawing operations. Cursor Delay Skew (CSK: bit 11 - bit 19) CSK defines the delay time for /CUDI and /CUD2 in units of memory cycles independent of the video memory access mode. The /CUDI and /CUD2 skew allows compensating for delays due to the video memory, character generator or other external logic access time. CSK FUNCTION 99 No skew. /CUD2 output is always high. 91 /CUDl, /CUD2 are skewed by one memory cycle. 10 /CUDl, /CUD2 are skewed by two memory cycles. 11 /CUDl, /CUD2 are skewed by three memory cycles. 4-67 * Display Skew (DSK: bit 9 - bit 8) DSK defines the /DISPl, /DISP2 delay in units cycles independent of video memory access mode. memory FUNCTION ~K * of BB No skew. Bl /DISPl, /DISP2 are skewed by one memory cycle. IB /DISPl, /DISP2 are skewed by two memory cycles. 11 /DISPl, /DISP2 are skewed by three memory cycles. Access Mode (ACM: bit 3 - bit 2) The ACRTC provides three frame buffer access modes - Single, Interleaved and Superimposed. Only the last two are supported by the SYS68K/AGC-l. ACM FUNCTION IB Interleaved Access Mode (Double Access Mode B) : The video memory is accessed twice every display cycle. Display and Drawing cycles are interleaved during each phase of the display cycle. The window has the highest priority and overlaps the Background screens. 11 Superimposed Access Mode (Double Access Mode 1) : The video memory is accessed twice every display cycle. The first phase accesses the Background screen, the second phase accesses the Window screen. In this case Background and Window have equal priority and are superimposed. This mode is only supported with the AGC-IX-board. In Interleaved and Superimposed access modes the horizontal display width of the Background screen and the Window screen must be even. Also, for these modes, the relation between the starting position of the horizontal display on the Background screen and the starting position of the horizontal display on the window screen must be even number/even number or odd number/odd number. 4-68 * Raster Scan Mode (RSM: bit 1 - bit B) RSM selects the ACRTC raster scan mode. The Interlaced Sync Mode simply repeats each raster address for both the odd and the even field. The Interlaced Sync & Video Mode displays alternate even and odd rasters on alternate even and odd fields. Note that for Interlaced modes the refresh frequency for a given dot on the screen is one-half that of the NonInterlaced mode. Interlaced modes normally require a more persistant phosphor to avoid a flickering display. RSM FUNCTION 00 01 Non-Interlace Mode 10 Interlace Sync Mode 11 Interlace Sync & Video Mode 4-69 4.9.6 Display Control Register (DCR~ r06-r07) Low-order High-order , , , , , , , , , , , , , , , , , , 15 , 14 , 13 I 12 I 11 I 10 I 9 , 8 I 7 I 6 , 5 I 4 , 3 , 2 , 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1---------------------------------------------------------------------1 I 1 I IDSP 'SEI I I " I SE0 I I SE2 1 I I I SE3, I I A T T RIB UTE I DCR controls ACRTC screen organisation and 8 bits of user defined video attributes. Logically, the ACRTC has a Background screen (Upper, Base, Lower) and a Window screen. DCR allows the screens to be enabled, disabled and blanked. If the Upper, Lower and Window screens are disabled, they do not have to be defined. * DISP Signal Control (DSP: bit 15) o DSP defines the output mode of the /DISPI display timing signals. DSP and /DISP2 FUNCTION DSPI is driven active low during the display period of the Background screen (combined horizontal and vertical display). /DISP2 is controlled similary for the window screen. board This mode is supported with the AGC-IX (optional available). 1 /DISPI is driven active low during the horizontal of both the Background and the Window display screens. /DISP2 is driven active low during the vertical display period of both the Background and the Window screen. 4-70 1 * Split Enable 1 (SE1: bit 14) SEl allows the Base screen to be blanked. Base screen drawing can occur when the Base screen is blanked since video memory display access is suppressed. Note that the Base screen parameters must be defined, even when the Base screen is always blanked. SE1 * FUNCTION o The ACRTC inhibits the the display enable timing and the display address outputs associated with the Base screen. The area of the Base screen, though blanked, remains on the CRT screen. 1 The ACRTC outputs display enable addresses for the Base screen. timing and display Split Enable 0 (SE0: bit 13 - bit 12) SE0 allows the Upper split screen to be enabled, disabled and blanked. If always disabled, the Upper screen parameters need not be defined. FUNCTION SE0 0X The ACRTC disables the Upper screen. Therefore, the Background screen contains two parts maximum - the Base and the Lower screen. The Base screen is moved upward by the number of rasters in the disabled Upper screen. 10 The display enable timing outputs and display address outputs are inhibited for the Upper screen. The area of the Upper screen, though blanked, remains on the screen. 11 The ACRTC outputs display enable addresses for the Upper screen. 4-71 timing and display * Split Enable 2 (SE2: bit 11 - bit IS) SE2 al16ws the Lower split screen to be enabled, disabled and blanked. If always disabled, the Lower screen parameters need not be defined. SE2 * FUNCTION sx The ACRTC disables the Lower screen. Therefore, the Background screen contains two parts maximum - the Base and the Upper screen. The Base screen is extended downward by the number of rasters in the disabled Lower screen. 10 The display enable timing outputs and display address outputs are inhibited for the Lower screen. The area of the Lower screen, though blanked, remains on the screen. 11 The ACRTC outputs display enable timing addresses for the Lower screen. and display Split Enable 3 (SE3: bit 9 - bit 8) SE3 allows enabling, disabling and blanking of the Window screen. When disabled or blanked, the overlapped Background screens are displayed. SE3 FUNCTION 0X The ACRTC disables the Window screen and overlapped Background screens are displayed. If always disabled, the Window parameters need not be defined. 10 The display enable timing outputs and display address outputs are inhibited for the Window screen. The area of the Window screen, though blanked, remains on the screen. For superimposed access modes (only supported with the AGC-lX board), the overlapped Background screens are displayed. 11 The ACRTC outputs display enable addresses for the Window screen. 4-72 timing and display * Attribute Control (ATR: bit 7 - bit B) These 8 bits can be freely programmed as user defined video attributes. They are output at the beginning of each raster and so programmed dynamically, ATR allows video attributes to be controlled on a raster by raster basis. On the SYS68K/AGC-l these bits are used to control the following functions : ATT0 - ATT3 5) Colour Look-up Table Control (CTC: bit 7 - bit These bits are used for the colour look-up table switching in the 4 bit/pixel mode. CTC FUNCTION 0000 Colour look-up table 0 is used for display 0001 Colour look-up table 1 is used for display 0010 Colour look-up table 2 is used for display 0011 Colour look-up table 3 is used for display 0100 Colour look-up table 4 is uSed for display 0101 Colour look-up table 5 is used for display 0110 Colour look-up table 6 is used for display 0111 Colour look-up table 7 is used for display 1000 Colour look-up table 8 is used for display 1001 Colour look-up table 9 is used for display 1010 Colour look-up table 10 is used for display 1011 Colour look-up table 11 is used for display 1100 Colour look-up table 12 is used for display 1101 Colour look-up table 13 is used for display 1110 Colour look-up table 14 is used for display 1111 Colour look-up table 15 is used for display 4-73 ATT4 - ATT6: Display Mode Control (OMC: bit 4 - bit 6) The DMC bits control the way of displaying the pixels the screen. DMC on FUNCTION 000 8 bit/pixel mode In this mode 256 colours are displayable simultaneously. The maximum screen resolution is 800 x 600 pixel with 50 Hz noninterlaced. 001 4 bit/pixel mode 1 : In this mode 16 colours are displayed simultaneously. The maximum screen resolution is 1024 x 800 pixel with 60 Hz noninterlaced. 010 4 bit/pixel mode 2 : This mode enables the SWITCH COLOR and BLINK respectively (see Chapter 4.6) 011 SWITCH mode 8 bit/pixel mode 2 : In this mode the 8 bit video data can blanked out bit by bit and replaced through ATT0 - ATT3 or BLINK {i.e. 6 bit video data + ATT0 + ATTI for colour look-up table switching) • 100 Reserved for expansion with the SYS68K/AGC-IX III ATT7: Smooth Scroll Bit 5 (SS5: bit 7) This bit, together with the SDA bits in the Start Address Register (see Chapter 4.9.16) is used for horizontal smooth scroll in the 4 bit/pixel mode. It represents the least significant bit of the Start Dot Address. 4-74 4.9.7 Raster Count Register (RCR: rSS-rSl) Low-order High-order I I I I I I I I I 1 I I I I I I I I 15 I 14 I 13 I 12 I 11 I 10 I 9 lSI 7 I 6 I 5 I 4 I 3 1 2 I 1 I 0 I I I I I I 1 1 1 1 1 1 1 1 1 1 1 1 1---------------------------------------------------------------------1 1 1 1 1 1 1 1X 1X 1X I X 1 R A S T E R C 0 U N T 1 1 1 1 I 1 1 RCR is a read-only register which contains the number of the raster currently being scanned on the CRT. Note that the initial RCR value after hardware reset is undefined. If RCR read operation is desired, the HSW should be set greater than or equal to 3. RCR should only be read when HSYNC is high. RCR is updated depending on the ACRTC raster scan modes as shown. Non-Interlace: RCR starts counting at 0 and increments by 1 sequentially. Interlace Sync: RCR starts counting at 0 and increments by 1 sequentially in both the even and the odd fields. Because a dummy raster is added to the even field, the maximum raster number for the even field is one greater than for that for the odd field. Interlace Sync & Video: RCR starts counting at 0 in the even field and at 1 in the odd field, and incremented by 2 sequentially in both fields. The even field always has even raster numbers and the odd field always has odd raster numbers. A dummy raster is added to the even field as in Interlace Sync mode. 4-75 Low-order High-order 1 1 1 1 1 1 1 1 1 1 1 1 I I I 1 1 1 15 1 14 1 13 1 12 I 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 1 1 1 1 1 1 I I I I 1 1 1 1 1 1 1 1---------------------------------------------------------------------1 1 1 1 1 1 1 1 HC 1 I 1 1 HSW I 1 1 1 1 1 1 HSR defines Width (HSW). * the Horizontal Cycle (HC) and the Horizontal Cycle Horizontal Sync (HC: bit 15 - bit 8) HC specifies the horizontal scan time (including the horizontal retrace period) in units of memory cycles (MC) • On the SYS68K/AGC-1 one memory cycle is equivalent to 250 ns. HC is set depending on the specifications of the CRT display device. If H memory cycles are to be specified, HC should be set to H-1. When using interlaced scan modes, H should be an even number. HC Memory Cycle No. 00000000 1 0.25 usec 00000001 2 0.50 usec 11111110 255 63.75 usec 11111111 256 64.00 usec 4-76 Time * Horizontal Sync Width (HSW: bit 4 - bit B) HSW specifies teh /HSYNC active low time in units of memory cycles. HSW is set depending on the specifications of the CRT display device. Valid values for HSW are 2 - 31. When using the RCR register, HSW must be 3 or greater. HSW Memory Cycle No. Time 2 9.59 usec 3 9.75 usec 11119 39 7.59 usec 11111 31 7.75 usec 4-77 4.9.9 Horizontal Display Register (HDR:r84-r85) Horizontal Window Display Register High-order (HWR: r92 =r93) Low-order I I I I I I I I 1 I I I I 1 I I I I 15 I 14 I 13 I 12 I 11 I 19 I 9 I 8 I 7 I 6 I 5 I 4 1 3 I 2 1 1 1 9 1 I I I 1 I 1 1 1 1 I I I 1 I I I 1 1---------------------------------------------------------------------1 I 1 I H D S I 1 I H D W I High-order I I Low-order I I I 1 I I I I 1 I I I I 1 I I 1 I 15 I 14 I 13 I 12 I 11 1 19 I 9 I 8 1 7 I 6 I 5 1 4 I 3 1 2 1 1 1 9 I 1 1 1 1 1 1 I I 1 1 I 1 1 1 1 1 I 1---------------------------------------------------------------------1 1 1 I I H WS I I 1 H WW HDR - specifies the horizontal display start position and horizontal display width in units of memory cycles (1 MC = 259ns) • HWR specifies the horizontal WIndow start position and horizontal Window width in units of memory cycles. • Horizontal Display Start (HDS: r84) HDS defines the interval between the rising edge of /HSYNC and the horizontal display starting point in units of memory cycles. If the Horizontal Display Start is HS memory cycles, HDS should be set to HS-l. 4-78 1 I * Horizontal Window Start (HWS: r92) HWS defines the interval between the r~s~ng edge of /HSYNC and the horizontal Window display starting point in units of memory cycles. If the horizontal window display starting point is HS memory cycles, HWS should be set to HS-1. HDS/HWS * Memory Cycle No. Time ~"HHHHHHJ 1 13.25 usec ~H'.1 ~HHHH~ 1 2 13.513 usec 111111113 255 63.75 usec 11111111 256 64.1313 usec Horizontal Display Width (HDW: r85) HDW defines the display period for one raster in units of memory cycles. If the horizontal display width is HW memory cycles, HDW should be set to HW-l. * Horizontal Window Width (HWW: r93) HDW defines the window display period for one raster in units of memory cycles. If the horizontal window display width is HW memory cycles, HWW should be set to HW-1. HDW/HWW Memory Cycle No. Time 1313131313131313 1 0.25 usec 131313131313131 2 13.513 usec 111111113 255 63.75 usec 11111111 256 64.1313 usec 4-79 4.9.10 Vertical Sync Register (VSR: r86-r87) Low-order High-order I I I I I I I I I I I I I I I I I I 15 I 14 I 13 I 12 I 11 I 10 I 9 I 8 I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 I I I I I I I I I I I I 1 I I I I I 1---------------------------------------------------------------------1 I Ix I 1 I 1 xix I 1 I Ix I I I I vc --------------------------------------------------------------------- VSR defines rasters. • the period of the vertical scan cycle in units of Vertical Cycle (VC: bit 11 - bit 0) VC defines the vertical scan cycle period (including vertical retrace) in units of rasters. VC is set depending on the specifications of the CRT display device. The way VC is programmed depends on the ACRTC raster scan mode. VC should be programmed with a non-zero value. Non-Interlace Mode When the number of rasters is V, VC is set to V. Interlace Sync Mode When the number of rasters in one field (odd or even) is V, vc is set to V. The total rasters in one frame is 2V+1 due ,to one dummy raster operation. Interlace Sync & Video Mode When the number of rasters in one frame (even field + field + dummy raster) is V, VC is set to V. VC Number of rasters 000000000001 1 000000000010 2 111111111110 4094 111111111111 4095 4-80 odd I 1 I 4.9.11 Vertical Display Register (VDR: rSS-rS9) High-order Low-order I I I I I I I I I I I I I I I I I I 15 I 14 I 13 I 12 I 11 I 19 I 9 I S I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 9 I I I I I I I I I I I I I I I I I I 1---------------------------------------------------------------------1 1 1 I I I I I VDS 1111 vsw I I 1 I I 1 VDR defines the vertical sync width and vertical display and width in units of rasters. * Vertical Display Start start (VDS: rSS) VDS defines the period from the vertical display start position vertical display start position to VS-1. The way to program VDS modes as described for VSR (rS6 VDS 1 rising edge of /VSYNC to the in units of rasters. If the is the VS raster, VDS is set depends on ACRTC raster scan - rS7). Number of rasters 99999999 99999991 1 1 2 11111119 11111111 255 256 I I I I I 4-S1 * Vertical Sync Width (VSW: r89 bit 4 - bit 9) VSW defines the /VSYNC low pulse width in units of rasters. VSW is set depending on the CRT display device specifications. VSW should be set to a non-zero value. VSW Number of rasters 1 2 11119 11111 39 31 4-82 4.9.12 Vertical Window Display Register (VDR: r94-r97) High-order Low-order 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1---------------------------------------------------------------------1 1 1 1 1 1 1 1 1 1 1 1 V W S 1 1 1 1 1 1 1 High-order Low-order 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1---------------------------------------------------------------------1 1 1 1 1 1 I 1 1 1 1 1 V W W I 1 1 1 1 1 1 VWR is a read/write register that defines the start position and width in units of rastets. • Vertical Window Start vertical Window (VWS: r94 - r95) VWS defines the period from the rising edge of /VSYNC to the vertical Window start position in units of rasters. When the vertical window start position is the VS raster, VWS is set to VS-1. Note that VWS must be greater or equal to VDS. VC Number of rasters 1 2 111111111110 4095 111111111111 4096 4-83 * Vertical Window Width (VWW: r96 - r97) VWW defines the vertical display period of the window screen in units of rasters. When the vertical window width is vw rasters, VWW is set to VW. VC Number of rasters 1 " " " 'HHHH'J " " " 1 """"""""""1" 2 11111111111" 4"94 111111111111 4"95 4-84 4.9.13 Split Screen Width Register (VDR: r8A-r8F) High-order Low-order 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1---------------------------------------------------------------------1 1 1 I I I 1 1 1 l i s P 0 (Base Screen) I 1 1 1 1 I I High-order Low-order 1 1 1 1 1 I 1 I 1 1 1 1 1 1 1 1 I 1 15 1 14 1 13 1 12 1 11 1 10 1 9 I 8 I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 I I I I 1 I I I I 1 1 I 1 1 1 1 I I 1---------------------------------------------------------------------1 I 1 I 1 1 1 1 I 1 l i s P 1 (Upper Screen) I I I I 1 I I High-order Low-order 1 I 1 I I 1 1 1 1 1 I 1 1 I I 1 1 I 15 I 14 I 13 1 12 I 11 I 10 1 9 I 8 I 7 1 6 I 5 I 4 1 3 I 2 I 1 1 0 I I I 1 1 1 1 1 1 1 I I I 1 I I 1 I 1---------------------------------------------------------------------1 1 1 1 1 1 I 1 I 1 l i s P 2 (Lower Screen) I 1 1 1 I 1 I SSW defines the screen 0), Base screens. vertical display width of (split screen 1) and Lower 4-85 the Upper (split (split screen 2) * Split Screen Width (SPO: r8A - r8B (SPl: r8e - r8D (SP2: r8E - r8F bit 11 - bit 0) bit 11 - bit 0) bit 11 - bit 0) SPO, SPI and SP2 define the vertical display period of the Upper, Base and Lower screens respectively in units of rasters. If the vertical screen width is SW rasters, SP0/SPl/SP2 are set to SW. SPl/SP2 Number of rasters 000000000001 1 000000000010 2 111111111110 4094 111111111111 4095 For the Base screen SP0 =0 also can be used. 4-86 4.9.14 Blink Control Register (VDR: r9~-r91) High-order Low-order \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 15 \ 14 \ 13 \ 12 \ 11 \ 1~ \ 9 \ 8 \ 7 \ 6 \ 5 \ 4 \ 3 \ 2 \ 1 \ ~ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \---------------------------------------------------------------------\ \ \ \ \ \ \ BON 1 \ \ BOFF 1 \ \ BON 2 \ \ \ BOFF 2 BCR defines the blink on and blink off period for the Blink 1 Blink 2 video attributes. * Blink On (BON 1: r9~ (BON 2: r91 \ and bit 15 - bit 12) bit 7 - bit 4) BON 1/2 defines the BLINK 1/2 attribute active high (on) period. The unit is 4 field periods. BLINK 1/2 is always low (OFF) when BON 1/2 = ~ is programmed. * Blink Off (BOFF 1: r98 (BOFF 2: r91 bit 11 - bit 8) bit 3 - bit 8) BOFF 1/2 defines the BLINK 1/2 attribute active low (OFF) period. The unit is 4 field periods. BLINK 1/2 is always high (on) when BON 1/2 = ~ are programmed. BON 1/2 BOFF 1/2 Blink high/low Level No. of Fields ~ ~ ~ ~ ~ ~ ~ 1 8 ~ ~ 1 ~ 12 ~ ~ 1 1 16 ~ 6~ 1 1 1 1 64 1 1 1 BLINK 1/2 always high 4-87 \ 4.9.15 Memory Width Register (MWRe: (MWRl: (MWR2: (MWR3: rC2 rCA rD2 rDA High-order - rC3) rCB) rD3) rDB) Upper Screen Base Screen Lower Screen Window Screen Low-order 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 1 14 1 13 1 12 1 11 1 Ie 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 9 1 1 1 1 1 1 1 1 1 1 1 I I 1 I 1 1 1 1---------------------------------------------------------------------1 1 1 1 1 1 1 1e 1x I x 1x 1 MW 1 1 1 1 I 1 1 MWR defines the number of physical 16 bit frame buffer words which comprise all logical pixel X addresses for a single Y address. For example, if a screen is defined with le24 logical pixel range in the X direction (X may vary from e to 1923), and 4 bits per pixel are assumed, that screens MWR value should be 256. MWR should be greater than or equal to the Horizontal Disply Width (HDW - r85). MWR must be greater than HDW to perform horizontal smooth scroll. MWR maximum value is 4995. * Memory Width MW (MW: bit 11 - bit 9) No. of Words 9geegeeegee e eegege9ge91 1 11111111119 4e94 11111111111 4e95 4-88 4.9.16 Start Address Register (SARO: (SARI: (SAR2: (SAR3: rC4 rCC rD4 rDC - rC7) rCF) rD7) rDF) High-order Upper Screen Base Screen Lower Screen Window Screen Low-order , , , , , , , , , , , , , , , , , ,, 15 ,, 14 ,, 13 ,, 12 ,, 11 ,, 10 ,, 9 ,, 8 ,, 7 ,, 6 ,, 5 ,, 4 ,, 3 ,I 2 ,, 1 ,, 0 ,, ,---------------------------------------------------------------------, , I , , , , , , , , , ,'X ,'X ,'X ,' X ,, SDA ,' x ' X , ,X , ,X , ' S, A H High-order ,, Low-order , , , , , , , , I , , , I , , , I I 15 , 14 I 13 I 12 , 11 I 10 , 9 , 8 , 7 , 6 , 5 I 4 , 3 , 2 I 1 , 0 , , , , , , , I I , , , , , , , , , 1---------------------------------------------------------------------, , I I I I I SAL .SAR defines the first frame buffer address for each screen. SARO-3 apply to screens 0 - 3, the Upper, Base, Lower and Window screens respectively. The screens have a 1M byte by 16 bit physical address space. SAR can take on any address. The memory addresses will 'wraparound' to g when the physical address space limit is reached independent of the split screen position. * Start Address Low (SAL: bit 15 - bit 0) SAL contains the least significant 16 bits of the start address. * Start Address High 20 bit (SAH: bit 3 - bit 0) SAH provides the most significant 4 bits of the 20 bit start address. 4-89 Vertical smooth scroll is done by simply increment or decrement the start address. The number of words is the same as defined in the Memory Width Register (MWR) * Start Dot Address (SDA: bit 11 - bit 8) SDA is used to define a start dot horizontal offset for the horizontal smooth scroll circuit on the SYS68K/AGC-l. In the 8 bit/pixel mode SDA can vary between 0 and 15. This value corresponds with the number of pixels read out in one memory cycle. In the 4 bit/pixel mode, the number of pixel read out during one memory cycle is 32 and therefore the least significant bit to scroll pixel by pixel is provided by attribut bit 7 in the Display Control Register (DCR r06 r07) • Number of pixels offset SDA 8 bit/pixel 4 bit/pixel 0000 0 0 0001 1 2 0010 2 4 0011 3 6 0100 4 8 0101 5 10 0110 6 12 0111 7 14 1000 8 16 1001 9 18 1010 10 20 1011 11 22 1100 12 24 1101 13 26 1110 14 28 1111 15 30 4-90 4.9.17 Zoom Factor Register (ZFR: rEA - rEB) High-order 1 Low-order 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1---------------------------------------------------------------------1 I 1 I 1 I I I I I 1 I 1HZ F 1 V Z F I X 1X I X 1X 1X 1X 1X 1X 1 1 1 1 1 1 1 1 1 1 1 1 --------------------------------------------------------------------- I 15 ZFR determines the horizontal and vertical multipliers (1-16) for zooming up. Zooming can only applied to the Base screen. HZF and VZF should be set to 0 for no-zoom and $F for 16 times zoom. Note that zooming and scrolling horizontally together only can be done due to the following equations: No. pixel/raster ------------------4 * (HZF + 1) No. pixel/raster ------------------2 * (HZF + 1) = N (4 bit/pixel mode) = N (8 bit/pixel mode) With N must be an integer value. • Horizontal Zoom Factor (HZF: bit 15 - bit 12) HZF defines the horizontal zoom factor in units of memory cycles. The ACRTC will output a single display address HZF times. • Vertical Zoom Factor (VZF: bit 11 - bit 8) VZF defines the vertical zoom factor. The ACRTC performs the vertical zoom by modifying is video memory address so that multiples of the same raster data are displayed. VZF/HZF 0 0 o o Magnitude 0 0 0 1 1 2 1 1 I 1 1 1 1 0 1 1 1 1 15 16 4-91 = HZF + 1 4.9.18 Light Pen Address Register (LPAR: rEC - rEF) High-order 1 1 Low-order 1 1 1 1 1 I 1 1 1 1 1 1 1 1 1 1 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1---------------------------------------------------------------------1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1X 1X 1X 1 X 1 X 1X 1 X 1 X 10 1 X 1 X 1X 1 L P A H 1 1 1 1 1 1 1 1 I 1 1 1 1 1 1 15 High-order Low-order 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 I I 1 1 1 1 I 1 1 1 1 1 1 1 1 1 1 1---------------------------------------------------------------------1 1 1 L PAL 1 1 1 1 LPAR is a read only register. When the ACRTC LPSTB input is asserted, the current display address is latched into the LPAR. The value in LPAR will differ from the actual display address under the light pen depending on various hardware delay times. Thus., the LPAR value should be adjusted by host software depending on system configuration. * Light Pen Address High LPAH is only significant 4 address. * (LPAH: rED bit 3 - bit 0) valid if bit 7 = 0 and contains the most bits of the 20 bit graphic screen display Light Pen Address Low (LPAL: rEE - rEF) LPAL contains the least significant bits of graphic screen display address. 4-92 the 20 bit 4.10 Drawing Control Registers The ACRTC refers to a number of registers during graphic operations. a) Pattern RAM b) Drawing Parameter Registers drawing Colour 0 Register (CL0) Colour 1 Register (CLl) Colour Comparison Register (CMP) Edge Colour Register (EDG) Mask Register (MASK) Pattern RAM Control Regiser (PRC) Area Definition Register (ADR) Read/Write Pointer (RWP) Drawing Pointer (DP) Current Pointer (CP) The Pattern RAM is accessed using the Read and Write Pattern (RPTN, WPTN) commands (see Appendix I). The Drawing Parameter Registers are accessed using the Read and Write Parameter Register (RPR, WPR) commands. Table 4-13 shows the Drawing Parameter Register locations. 4-93 CS RS ~W Reg. No. 1 - 0 0 a AR 0 a 1 SR V6 rOO 1. ra2 1/0 r04 /0 r06 rOB ,. Abbre. ~~~~~D'-OA,,,"TA~(7H-'-,.)-=-,...-o-o--=---+-~ DATA (L) 15 I 14 I 13 I 12 I 11 I 10 I 9 I 8 7 I 6 I 5 I 4 I 3 I 2 I 1 I Register Name Address Register Status Register FIFO Entry Command Control Oper alion Mode Display Control AR SR FE CCR OMR DCR ABTIPSEIDDMICDMIDRCI M/SI STRIACPIWSSI CSK DSPI SEll SEa I SE2 a Address CERIARDJCEDjLPDjRFFLRFRjWFRJWFE FE GBM CREIAREICEEILPEIRFEIRREIWREIWEE I DSK RAMI GAl I ACM I RSM I SE3 I AT R - (undefined) rlE 1 r80 Raster Count RCR···· ...... I RC ~,.~0~r~8~2~H~o=ri~ro~n~ta·71~S~~~c~.---~H~SR~~-----~H~C~-----~-'---~"~'~"-'-"-lr---~H~S~W~----r84 Horizontal Display HDR HDS ~ r86 yertic;al_--,S+-yn_co-'______-+c'-V~S'='R-I---.-.-_._''_'._._.~~~ I Va r88 Vertical Display VDR VDS ~ Split Screen Width SSW ~--:::~~:-:--+-:! ---.- I .__~.~.____ I H~ i-;-,-"o+-'..;r9;;O+-Bc-lin-;-k---,C:;co--:n-;-tr--:col,-----hBC"'R~+------,B"'OCO-;N71-__t__-ElOFF 1 ---I-----SO~--I- 9' -ElOFF2 "'01 r92 HOrIZontal Window DISPlay,__+H"-W::..R"-+_------.:.:H~W;:_::S'---~----...J---...,~_;c__-'-H~W'-'--'W'------l1. oi r94 .......... I V WS ~ Vertical Window Display VWR .......... J V WW !l~' r98 --+-,--+-------C'X&.E,-------,I---~~~C'X S ~ L,,: r9A Graphic Cursor Vb' r9C Note; 1 I i GCR -- -- -- -- ----------- I C YS I C YE .. · .. High" level level : a .. ·"Low" Table 4-13: Drawing Parameter Registers 4-94 j HDW VSW ~ _ ~ I 4.10.1 Pattern RAM The ACRTC contains a 32 byte pattern RAM. The Pattern RAM is used for pre-defining data for the graphic drawing operations. A 16 by 16 bit pattern (or 16 sets of 16 by 1 bit) can be stored in the Pattern RAM as a binary representation of screen data. In this case, a two entry colour 'palette' corresponding to 0 and 1 data values is defined using the Colour 0 (CL0) and Colour 1 (CLl) registers. To store colour patterns in the Pattern RAM it is divided into four equal segments of either 4 by 4 bit patterns or 4 sets of 4 by 1 bit patterns. In this case, during drawing the colour coded contents of the Pattern RAM are directly written to the video memory. The particular segment used is defined by the Pattern RAM Control register (PRC). When multiple drawing commands use a common continuity can be achieved by adjusting the pointer. 4-95 pattern, pattern pattern scanning 4.1~.2 Colour ~ Register I I I I I 1 I 15 I 14 I 13 1 12 I 11 1 I I I I I I (CL~: l~ Pr~~) 1 I 1 1 1 I 1 I I 1 1 9 1 8 I 7 1 6 I 5 1 4 1 3 I 2 I 1 1 I I , , 1 , , 1 , 1 ~ I 1 , ,---------------------------------------------------------------------1 , C L 'I ,I ~ When logical drawing data =~, the contents of CL~ are stored in the video memory. The value of CL~ corresponds with the bits/pixel mode used. For example in 4 bits/pixel mode CL~ contains the colour value for 4 pixel. If all pixel should be painted in the same colour, it is necessary to store the respective colour 4 times in the Colour ~ register. 4.1~.3 Colour 1 Register I I , , , I , 15 , 14 1 13 , 12 , 11 I I , 1 I 1 1 (CLl: l~ Pr~l) , I , I I 1 , , 1 , I 9 , 8 1 7 I 6 1 5 I 4 I 3 , 2 1 1 I I 1 , 1 1 , , I 1 I ~ I , I ,---------------------------------------------------------------------1 1 , , C L 1 1 , , When logical drawing data = 1, the contents of CLI are stored in the video memory. The value of CLI corresponds with the bits/pixel mode used. For example in 4 bits/pixel mode CLI contains the colour value for 4 pixel. If all pixel should be painted in the same colour, it is necessary to store the respective colour 4 times in the Colour 1 register. 4-96 4.10.4 Colour Comparison Register ~MP: Pr02) --------------------------------------------------------------------- I I I I I I I I I I I I I I I I I I 15 I 14 I 13 I 12 I 11 I 10 I 9 I 8 I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 I I I I I I I I I I I I I I I I I I 1---------------------------------------------------------------------1 I I C C MP --------------------------------------------------------------------- I I CMP defines a comparison colour for use with conditional drawing operations. Conditional drawing applies various logical comparisons between the drawing data and CCMP to determine if drawing should occur (refer to Appendix J-3). The value of CMP corresponds with the bits/pixel mode used and has to be programmed as the Colour registers respectively. 4.10.5 Edge Colour Register n;DG: Pr03) I I I I I I I I I I I I I I I I I I 15 I 14 I 13 I 12 I 11 I 10 I 9 I 8 I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 I I I I I I I I I I I I I I I I I I 1---------------------------------------------------------------------1 I I l E D G I EDG defines the boundary edge colour for use with the PAINT command. In one mode, the edge is defined as the colour contained in the EDG. In another mode, the edge is defined as any colour except the colour contained in the EDG register. The values of EDG corresponds with the bits/pixel mode used and has to be programmed as the Colour registers respectively. 4-97 I I 4.10.6 Mask Register (MASK: Pr04) ,--------------------------------------------------------------------, , , , , , , , , , , , , , , , ,, 15 ,, 14 ,, 13 ,, 12 ,, 11 ,, 10 ,, 9 ,, 8 ,, 7 ,, 6 ,, 5 ,, 4 ,, 3 ,, 2 ,, 1 ,, 0 ,, ,------------------------------------------------------_._-------------, I, M S K --------------------------------------------------------------------When performing data transfer and drawing of the video memory, MSK is used to mask bits upon which drawing and other logical operations should not be performed. If MSK bit is 0, the corresponding video memory bit is excluded from any logical operation. The values of EDG corresponds with the bits/pixel mode used and has to be programmed as the Colour registers respectively. 4-98 ," 4.10.7 Pattern RAM Control Register (PRC: Pr05 ~ Pr07) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1---------------------------------------------------------------------1 1 1 1 1 1 1 P P Yip z C yiP P X 1 P P Y 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1---------------------------------------------------------------------1 1 1 1 1 1 1 1 1 1 1 1 1 PSY 101010101 PSX 101010101 1 1 1 1 1 1 1 1 1 1 1 --------------------------------------------------------------------1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 I 1 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1---------------------------------------------------------------------1 1 1 1 1 I 1 P E yip z yip E X 1 P Z X 1 I 1 1 I 1 - PRC specifies the size of the patterns used for drawing and the start point within the Pattern RAM for the pattern scan. The pattern size can be independently specified in X and Y dimemsions (maximum 16 by 16 bits) • * Pattern Start X Pattern Start Y (PSX: (PSY: Pr06 Pr06 bit 7 - bit 4) bit 15 - bit 12) PSX and PSY specify the pattern scan starting point horizontal and vertical addresses respectively. These should be set between 0-15 for Colour register direct drawing and between 0-3 for Pattern RAM direct drawing. 4-99 * Pattern End X Pattern End Y (PEX: (PEY: Prl7 Prl7 bit 7 - bit bit IS - bit 4) 8) PEX and PEY specify the pattern scan ending point horizontal and vertical addresses respectively. These should be set between I-IS for Colour register indirect drawing and between 8-3 for Pattern RAM direct drawing. * Pattern Zoom X Pattern Zoom Y (PZX: (PZY: Pr87 Pr87 bit 3 - bit bit 11 - bit I) 8) PZX and PZY specify the magnification coefficient applied to the contents of the Pattern RAM. PZX, PZY = 8 specifies no magnification, while PZX, PZY = $F specifies by 16 magnification. * Pattern Zoom Count X Pattern Zoom Count Y (PZCX: (PZCY: PrlS PrlS bit 3 - bit bit 11 - bit B) 8) PZCX and PZCY specify the initial magnification counter values in the horizontal and vertical dimensions respectively. Normally, PZCX and PXCY should be set to 8. * Pattern Pointer X Pattern Pointer Y (PPX: (PPY: PrlS PrlS bit 7 - bit 4) bit IS - bit 12) The current reference point within the Pattern RAM is specified by PPX and PPY. When using PSX, PSY to define a pattern scan starting point, the following relationships must be maintained: = PPX = PEX PSY = PPY = PEY PSX and 4-188 4.10.8 Area Definition Register (ADR: Pr08 ~ Pr0B) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1---------------------------------------------------------------------1 1 1 X MIN 1 1 1 1 --------------------------------------------------------------------1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 I 2 1 1 1 0 1 1 I 1 1 1 1 1 I I 1 1 I I 1 1 1 1 1---------------------------------------------------------------------1 1 I 1 Y MIN 1 1 1 1 1 I 1 1 1 1 1 I 1 1 1 1 I 1 I I 1 15 1 14 1 13 I 12 I 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 I 2 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1---------------------------------------------------------------------1 1 1 I X MA X 1 1 I 1 1 I 1 1 1 1 I 1 1 1 1 1 1 1 I 1 I 15 1 14 1 13 1 12 1 11 I 10 1 9 I 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 1 I 1 1 1 1 I 1 1 1 1 1 1 1 1 1 1 1---------------------------------------------------------------------1 1 1 1 Y MA X 1 1 1 ADR is used to define a drawing area using logical X-Y addresses relative to the origin defined with the ORG command. The ACRTC will check logical drawing addresses against ADR depending on the AREA mode specified in the graphic drawing command. 4-101 4.1~.9 Read Write Pointer (RWP: gr~C ~ Pr~D) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 1 14 1 13 1 12 1 11 1 1~ 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 ~ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 I 1 1---------------------------------------------------------------------1 I 1 1 1 I 1 1 1 1 I D Nix 1X 1X I X 1X 1X 1 R WPHI 1 I 1 1 1 1 1 1 1 --------------------------------------------------------------------- 1 1 1 1 1 1 1 I 1 1 1 1 1 1 1 1 I 1 15 1 14 1 13 1 12 1 11 1 1~ 1 9 1 8 1 7 1 6 1 5 1 4 I 3 1 2 1 1 I ~ I 1 I 1 I I 1 1 1 I 1 1 1 1 1 1 1 1 1---------------------------------------------------------------------1 1 I 1 1 1 I 1 R WP L 1X 1X 1X I X I 1 1 1 1 1 1 RWP specifies a 2~ bit physical video memory address for use with the data transfer commands. * Display Number DN specifies transferred. DN * (DN: PrBe bit 15 - bit 14) the logical screen containing the data to be Functions ~~ Upper Screen ~1 Base Screen 1~ Lower Screen 11 Window Screen Read Write Pointer High Read Write Pointer Low (RWPH: (RWPL: Pr~C PrBD bit 7 - bit 9) bit 15 - bit 4) RWPH and RWPL define the initial 2~ bit video memory address used with the data transfer commands. 4-1~2 4.10.10 Drawing Pointer (RWP: Pr0C - Pr0D) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1---------------------------------------------------------------------1 1 1 1 1 1 1 1 1 1 1 D Nix 1 X 1 X 1 X 1 X I X 1 D P A H 1 1 1 1 1 I 1 1 1 1 1 1 1 1 1 1 1 1 I 1 1 1 1 1 1 1 1 1 15 1 14 1 13 1 12 I 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 1 I 1 I 1 1 1 1 1 1 1 1 1 1 1 1 1 1---------------------------------------------------------------------1 1 1 D PAL 1 1 1 1 1 D P D The ACRTC uses DP for containing the physical drawing address calculated during drawing commands. When executing a drawing command, DP is updated as the Current Pointer (CP), specifying the current logical X-Y drawing address, is moved. * Display Number (DN: Pr10 bit 15 - bit 14) DN specifies the screen for graphic drawing. Interpretation is the same as DN in the Read Write Pointer (RWP) register. * Drawing Pointer Address High Drawing Pointer Address Low (DPAH: (DPAL: Pr10 Prll DPAH and DPAL specify the 20 bit physical address. * Drawing Pointer Dot (DPD: Prll bit 7 - bit bit 15 - bit drawing 0) 4) pointer bit 3 - bit 0) DPD specifies the physical pixel address to locate a logical pixel within the 16 bit word addressed by DPAH, DPAL. Interpretation depends on the specified reletionship between logical pixels and physical frame buffer bits as determined by the Graphics Bit Mode (GBM). In the 4 bits/pixel mode, DPD specifies 1 of 4 logical pixels using the most significant 2 bits of DPD. The 2 least significant bits are not used. In the 8 bits/pixel mode DPD specifies 1 of 2 logical pixels using the most significant bit of DPD. 4-103 1 1 4.19.11 Current Pointer (CP: Pr12 =Pr13) -------------------------------------------------------'-------------- 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 1 14 1 13 1 12 1 11 1 19 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 I---------~-----------------------------------------------------------1 1 1 1 X 1 --------------------------------------------------------------------- 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 1 14 / 13 / 12 / 11 / 19 / 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 / 1 / 9 / 1 1 1 / / / 1 1 / / 1 / 1 / / / / /-------------------------------------------------------------~-------I 1 / / y CP specifies the logical X-Y coordinates of the current drawing address. As drawing proceeds, the ACRTC calculates the physical frame buffer address for each X-Y addressed logical pixel. The physical address corresponding to CP is stored in the Drawing Pointer (DP) register. Two's-comp1ement format is used to indicate positive and negative values. 4-194 / / / ~ Command Overview The ACRTC interprets and processes commands issued by the These commands are classified into three groups. host. 1. Register Access Commands 2. Data Transfer Commands 3. Graphic Drawing Commands ACRTC commands consist of a 16 bit op-code, by lore more 16 bit parameters. Commands and parameters following ways: * Software Polling can be issued to optionally the followed ACRTC in the (WFR, WFE interrupts disabled) a) The host program checks the Status Register for Write FIFO Ready (WFR) flag = 1, and then writes one word of command or parameters. b) The host program checks the Status Register for FIFO Empty (WFE) flag = 1, and then writes one to eight words of commands or parameters. * Interrupt Driven Write (WFR, WFE interrupts enabled) a) The host WFR interrupt service routine writes one word of command or parameters. b) The host WFE interupt service routine writes one to eight words of commands or parameters. In the specific case of Register Access Commands and an initially empty write FIFO, host writes need not be sychronized to the write FIFO status. The ACRTC can fetch and execute these commands faster than the host can issue them. 5-1 5.1 Register Access Commands Registers associated with the Drawing processor (the Pattern and the Drawing Parameter Registers) are accessed through read and write FIFO's using Register Access Commands. Command RAM the Function ORG Initialize the relation between the or1g1n point in the X-y coordinates and the physical address. WPR Write into the parameter register RPR Read parameter register WPTN Write into pattern RAM RPTN Read the pattern RAM For command codes Appendix J-l. and optionally parameters 5-2 please refer to 5.2 Data Transfer Commands Data Transfer Commands are used to move blocks of data between the host system memory and the ACRTC video memory or within the video memory itself. Before issuing these commands, a physical 20 bit frame buffer address must be specified in the Read Write Pointer (RWP) register. The DMA Data Transfer Commands (DRD, DWT and DMOD) are used to send large amounts of data between system and video RAM. The programmer specifies the command and the X and Y logical pixel dimensions of the video memory data block. The ACRTC will automatically control an external DMAC (installed on the optionally available SYS68K/AGC-lX board) to request data transfers via the read and write FIFO's. Note that DMA data transfers can be performed without an external DMAC, i.e. under host program control. In this case, the data DMA handshaking (DREQ, DACK and DONE) signals are disabled by resetting the DDM bit in the CCR to 0. After issuing a DMA transfer command, the host reads or writes the appropriate data to the ACRTC FIFO's under program control. The programmer must ensure that the amount of data transferred equals the amount specified as parameters to the command. Also note that the ACRTC will go into an indefinite wait state after the last transfer of a DRD command. Then, the command should be aborted (by setting the ABT bit in the CCR to 1) and the next command issued. Command Function ORO DMA read of the video memory DWT DMA write into the video memory DMOD DMA modify of the video memory data (bit maskable) RD One word read from the video memory WT One word write into the video memory MOD One word modify of the video memory (bit maskable) CLR Clear of video memory area SCLR CLear of video memory area (bit maskable) CPY Copy of video memory area into another area SCPY Copy of video memory area into another area maskable) 5-3 (bit 5.3 Modify Mode The DMOD, MOD, SCLR and SCPY commands allow 4 types of bit level logocal operations to be applied to video memory data. The modify mode is encoded in the lower two bits (MM) of these op-codes. The bit positions within each video memory word to be modified are selectable using the MASK register (MSK). Bits masked with 1 are modifiable, those masked with 9 are not. MM Modify Mode 99 Replace video memory data with command parameter data 91 OR video memory data with command parameter rewrite to the video memory. data and 19 AND video memory data with command parameter data rewrite to the video memory. and 11 EOR video memory with command rewrite to the video memory. data and of the parameter Refer to Appendix J-2 for examples showing REPLACE, OR, AND and EOR modify modes. 5-4 the use 5.4 Graphic Drawing Commands The ACRTC has 23 separate graphic drawing commands. Graphic drawing is performed by modifying the contents of the video memory based upon microcoded drawing algorithms in the ACRTC Drawing processor. Most coordinate parameters for graphic drawing commands are specified using logical X-Y addressing. The complex task of translating a logical pixel address to a linear video memory word address, and further selecting the appropriate sub-field or the word (for example, a given logical pixel in 4 bits/pixel mode might reside in bits 8-11 of a video memory word) is performed at high speed by ACRTC hardware. Most instructions allow specification of X-Y coordinates with either absolute or relative X-Y coordinates. In both cases, two compliment numbers are used to represent positive and negative values. a) Absolute Coordinate Specification The screen address (X,Y) is specified in units of logical pixels relative to an origin point defined with the ORG command. b) Relative Coordinate Specification The screen address (dX,dY) is specified in units of logical pixels relative to the current drawing pointer (CP) position. A graphic drawing command consists of an 8 bit command code, an Area Mode specifier (3 bits), a Colour Mode specifier (2 bits) and an Operation Mode specifier (3 bits). The Area Mode allows versatile clipping and hitting detection. A drawing area can be defined, and should drawing operations attempt to enter or leave that area, a number of programmable actions can be taken by the ACRTC. The Colour Mode determines whether the Pattern RAM is used indirectly to select the Colour Registers or is directly used as the colour information. The Operation Mode defines one of eight logical operations to be ~erformed between the video memory read data and the colour data In the Pattern RAM to determine the drawing data to be rewritten to the video memory. Table 5-1 shows the Graphic Drawing Commands. Please refer to Appendix J-1 for detailed information. 5-5 Table 5-1: Command Graphic Drawing Commands Function AMOVE RMOVE Movement of current points ALINE RLINE Drawing of straight lines ARCT Drawing of rectangles RRCT APLL RPLL Drawing of polylines APLG RPLG Drawing of polygones CRCL Drawing of circles ELPS Drawing of ellipses AARC Drawing of arcs RARC AEARC REARC Drawing of ellipse arcs AFRCT Painting of rectagle areas (Tiling) RFRCT PAINT Painting of arbitrary areas DOT Making of dots PTN Drawing of basic patterns (rotation angle: 45 ) (Tiling) AGCPY RGCPY Graphic copy between video memories (rotation angle: 90 /mirror turnover) 5-6. 5.5 Operation Mode The OPM bits of the Graphic Drawing Command specify the drawing condition. OPM 000 logical Operation Mode REPLACE: Replaces data. the video memory data with the colour 001 OR: ORs the video memory data with the colour data. The result is rewritten to the video memory. 010 AND: ANDs the video memory data wit the colour data. The result is rewritten to the video memory. 011 EOR: EORs the video memory data with the colour The result is rewritten to the video memory. data. 100 CONDITIONAL REPLACE (P = CMP): When the video memory data at the drawing position (P) is equal to the comparison colour (CMP), the video memory is replaced with the colour data. 101 CONDITIONAL REPLACE (P <> CMP): When the video memory data at the drawing position (P) is not equal to the comparison colour (CMP) , the video memory data is replaced with the colour data. 110 CONDITIONAL REPLACE (P < CL): When the video memory data at the drawing position (P) is less than the colour register data (CL), the video memory data is replaced with the colour data. III CONDITIONAL REPLACE (P > CL): When the video memory data at the drawing position (P) is greater than the colour register data (CL), the video memory data is replaced with the colour data. Refer to operation assumed. Appendix J-3 to show examples of each of the eight modes. In these examples, 4 bits/logical pixel is 5-7 5.6 Colour Mode (COL) The COL bits specify the source of the drawing colour data as directly or indirectly (using the Colour Registers) determined by the contents of the Pattern RAM. COL Colour Mode 0 0 When Pattern RAM data When Pattern RAM data = = 0, Colour Register 0 is used. 1, Colour Register 1 is used. o1 When Pattern RAM data When Pattern RAM data = = 0, drawing is suppressed. 1, Colour Register 0 is used. 1 0 When Pattern RAM data When Pattern RAM data = = 0, drawing is suppressed. 1, Colour Register 1 is used. 1 1 Pattern Ram contents are directly used as colour data. The Colour Mode chooses the source for colour information based on the contents (0 or 1) of a particular bit in the 16 bit by 16 bit Pattern RAM (see Appendix J-4). A sub-pattern is specified by programming the Pattern RAM Control Register (PRC) with the start (PSX, PSY) and end (PEX, PEY) points which define the diagonal of the sub-pattern. Furthermore, a specific starting point for Pattern RAM scanning is specified by PPX and PPY. Normally, the colour registers (CL) should be loaded with one colour data based on the number of bits per pixel. For example, if 4 bits/pixel are used, the 4 bit colour pattern (e.g. 0001) should be replicated four times in the colour register, i.e. Colour Register = 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 By doing this, the colour changes due to changing dot address are avoided. 5-8 5.7 Area Mode (AREA) Prior to drawing, a drawing area may be defined (Area Definition Register). Then, during Graphics Drawing Operation the ACRTC will check if the drawing point is attempting to enter or exit the defined drawing area. Based on eight Area Modes, the ACRTC will take appropriate action for clipping and hitting. AREA Drawing Area Mode Drawing is executed without Area checking. ~ ~ 1 When attempting to exit the Area, drawing is stopped and the ARD (Area Detect) and CED (Command End) flags are set ~ 1 ~ Drawing is suppressed outside the Area - drawing operation continues and the ARD flag is not set. ~ 1 1 Drawing operation is suppressed outside the Area drawing operation continues and the ARD flag is set. Same as AREA = ~ ~ ~. ~ 1 When attempting to enter the Area, drawing operation is stopped and the ARD and CED flags are set. 1 1 ~ Drawing is suppressed inside the Area - drawing operation continues and the ARD flag is not set. 1 1 1 Drawing is suppressed inside the Area drawing operation continues and the ARD flag is set. 1 Refer to Appendix J-5 for an example of the execution of a CRCL command using various Area Modes. It is assumed, that the Area Definition Register has been loaded to define the Area bounded by Xmin, Ymin and Xmax, Ymax. 5-9 ~ Miscallaneous 6.1 Miscallaneous Jumper Settings The RAS/CAS and WRITE timing for the DRAMs of the video memory is specified through the jumper settings of B13, B14, BlS, B16 and B17. BS controls the synchronization between ACRTC and host accesses to the video RAM. Note: These jumpers have a default setting and are not definable. user Jumper B12 has a default setting for enabling horizontal smooth scroll and zooming together (Scroll Mode 1). When using large zoom factors, it could occur that the display jumps to the right side of the display monitor. This phenomen can only be suppressed when horizontal smooth scroll and zooming are not used together. This mode is selected through jumper B12 (Scroll Mode 2). In the scroll mode 2 scrolling is only possible with no magnification. Fig. 6-1 Table 6-1 shows the jumper locations of BS and B12 - B17 on the SYS68K/AGC-l. lists the default jumper settings. 6-1 Figure 6-1: Jumper Location Diagram 6-2 ~ Jumper B12 Jumper B12 Scroll Mode 1 Scroll Mode 2 1---2 3 2---3 1 Default Set-up Jumper B5 Jumper B13 HJ---1 Jumper B14 1 14 16 1 2 9 2 2 13 15 8 3 3 12 14----3 7 4 4 11 13 4 6 5 5---10 12 5 6 9 11 6 7 8 10 7 9----8 Jumper Bl5 Jumper B17 Jumper B16 1 2 3 1 2 3 8----1 4 5 6 4 5 6 7 2 7 8 9 7 8 9 6 3 10---11 12 5 4 10 11---12 13---14 15 13 14 15 16 17 18 16 17 18 19 20 21 19 20---21 22 23 24 Table 6-1: Jumper Settings of B5, B12, B13, B14, B15, B16, B17 6-3 6.2 Light Pen Interface The Light pen interface is also realized on the SYS68K/AGC-l. It can be connected via the 15 pin DSUB connector (P4) on the front panel. The light pen must generate a positive or negative TTLcompatible pulse. Jumper B9 specifies the polarity of that pulse. Jumper B9 Jumper B9 positive Pulse negative Pulse 1---2 3 I 2---3 Default Set-up A light pen strobe pulse will occur when the CRT electron beam passes under the light pen during display refresh. When these pulse occur, the contents of the ACRTC display refresh address counter which then will be latched into the Light Pen Address register along with the logical screen (character or graphics) designator. The various system and ACRTC delays will cause the latched address to differ slightly from the actual light pen position. The light pen address can be corrected using software, based on the system specific delays. Or, if the application does not require the highest light pen resolution, software can 'bound' the light pen address by specifying a range of values associated with a given area of the screen. Table 6-2 shows the pin assigments of connector P4. Figure 6-2 lists the jumper location of B9. Note: Only Pins 7 and 8 have to be connected. All other pins must not be connected. These pins are reserved for future enhancements and for usage of multiple AGC-I. Table 6-2: Pin Assignment of Connector DISPI 1 /HSYNC 2 CLK31 3 2CLK 4 /EXSYNC 5 P4 9 GND 1~ 64M 11 /64M 12 NC 13 NC 14 NC 15 NC 6 +5V 7 Light Pen 8 6-5 6.3 External Synchronisation The SYS68K/AGC-l allows the sychronization of multiple AGC's (up to 3). The ACRTC may be programmed as a single master or as one of a number of slave devices. To sychronize multiple AGC's, connect them via P4 (Pin 1 - 5), select through Jumper BIB the Board as a master or slave device, set jumper Bll for internal or external pixel clock and program the ACRTC respective (in a system with 3 AGC's there exists one master and two slaves). Jumper BIB Jumper BIB Slave Master 1---2 3 1 2---3 Default Set-up Jumper Bll Jumper Bll Slave Master internal Clock external Clock 3---4 3 4 2---1 2 1 Default Set-up Fig. 6-2 shows the jumper locations of BIB and Bll on the board. Table 6-2 lists the pin assigments of connector P4. 6-6 Figure 6-2: Jumper Location Diagram of BIB (Light Pen) and BII 6-7 6.4 Display Monitor Interface The display monitor is connected with the SYS68K/AGC-l over the BNC-connectors on the front panel. A composite Sync-signal is mixed on the RGB-outputs and easing the interfacing. The outputs are capable of driving 75 Ohm lines compatible to RS 434. Monitors with separate SYNC-input should be connected with the composite SYNC-output of the SYS68K/AGC-l. The polarity of the SYNC-signal is jumper selectable through jumper B7. B7 B7 negative polarity positive polarity 1 1---2 2 Default Set-up Fig. 6-3 shows the jumper location of B7 on the board. 6-8 Figure 6-3: (17 J94 Jumper Location Diagram of B7 (SYNCSEL) J28 J30 J7 J25 J9 6-9 ~ Calculating the Screen Parameters This chapter gives a brief explanation of parameters for a given display monitor SYS68K/AGC-l (see also Chapter 8). configuration of the timing registers, completely specify the requirements of hardware and system design. calculating the screen and initializing the Before starting the it is necessary to the display monitor Two fundamental points are : (1) (2) All horizontal values used by the ACRTC are memory cycles. in units of All vertical values are in units of scan lines (rasters) It is therefore necessary to convert all specifications for the monitor hardware from their time domain values into these units before any registers can be configured. The timing control RAM (see Chapter 4.9) holds the values time and configure the display screen. that Fig. 7-1 shows how the display screen is specified in terms of the register values. For clarification, there follows a worked example. Only the Base Screen will be implemented. To recap: SYSTEM SPEC Scan standard 1333 lines interlaced Scan rate 40 KHz Field rate 60 Hz Frame rate 30 Hz Horizontal resolution 1280 pixels Vertical resolution 1239 lines Displayed vertical resolution 1024 lines Video memory capacity 2M Byte Video memory cycle period 250 ns ACRTC clock frequency 8 MHz Pixel rate 64 Mhz 7-1 (64 of 64kx4 DRAM) Monitor parameters .. Line period 25.9 usec Horizontal Sync width 2.9 usec Horizontal back porch 2.9 usec Horizontal front porch 1.9 usec Vertical Sync width min. 299 usec 999 usec Vertical front porch Vertical back porch 1.375 msec 7-2 Display Screen Specification Figure 7-1: He , ,,, ,, I .. ,,,4 I ,,I. HSW HWS , I. .I. 'HOS' I -I , I .1-,, ,, I HWW ., I . HOW ' ,L l I ----r-- ~----~--------~---------+------- 1--------+------------ ------ --- en o"'0-- I-------J--------- --1-------+-------- -1.-_ _ _ _ _ _.1- ____________________ --- ~-- r-.J L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-L 7-3 __________ _ o< 7.1 Horizontal Timing SET VIA = HSYNC 2.8 usec = BACK PORCH FRONT PORCH = 2.8 usec = 1.8 usec ACTIVE DISPLAY PERIOD LINE PERIOD = HC 8.8 % = 8.8 % = 4.8 = 28.8 25.8 usec = HSW HDS % usec = 88.8 % HDW HC 188 % The video memory cycle time is 258 nsec (i) Line Period: This is set via HC, the Horizontal Cycle Field: 25.8 usec required: 25.8 usec = 188 cycles 258 nsec note: As this is an even number, it is suitable for interlaced operation. HC is loaded with one less than this value, thus: 188 - 1 = 99 = $63 =====> HC .:: ~ (ii) Horizontal Sync Period: This is set via HSW, the Horizontal Sync Field, 2.8 usec required: 2.8 usec ---------- = 258 nsec 8 cycles =====> Note: This is greater than 3, so it will allow the RCR to be read. 7-4 (iii) Horizontal Back Porch: Set via HDS, the Horizontal Display Start Field. 2.0 usec required: 4.0 usec ---------- 250 nsec = 8 cycles HDS is loaded with one less than this value, thus: =====) 8 - 1 (iv) Active Display Period: = 7 = $07 Set via HDW, the Horizontal Display Width Field. 20.0 usec 20 usec required: ----------- = 250 nsec 80 cycles HDW is loaded with one less than this value, thus: =====) (v) = 80 - 1 = 79 $4F Front Porch This is not specified directly as it is the remainder from othe values. Front Porch = He - the (HSW + HDS + HDW) Note: This equation uses the values calculated, because sometimes they are one less. Front Porch =====) = 25.0 usec - Front Porch - not the ones loaded (2.0 usec + 2.0 usec + 20.0 usec) 1.0 usec 7-5 Summary, the four values are therefore: HDS = = = $~7 HDW = $4F 1. HC 2. HSW 3. 4. $63 $~8 HC and HSW are combined in r82 (HSR). HDS and HDW are combined in r84 (HDR). This results in the two registers having the following values: r82 = $63~8 r84 = $~74F 7-6 7.2 Vertical Timing Normally, the vertical flyback period occupies about 7% of the vertical period. In the case of 1333 lines system example, 94 lines are lost per frame, that is 47 lines per field. So only 1239 lines can be used for displaying. As the resolution will have 1924 lines, then the front and the back porches will have 199-115 lines. This should place the displayed lines almost centrally on the display monitor tube face. (i) Frame Rasters: Set by VC, the Vertical Cycle Field; 1333 lines required: = V 1333 cycles per frame Note: V = VC for interlaced sync and video mode. =====> (ii) Vertical Back Porch: Set by VDS, the Vertical Display Start Field; 199 lines required : 199 = $64 Note: VDS should be loaded with one less than the value required: =====> 199 - 1 = 99 = $63 (using interlace sync & video mode) (iii) Vertical Sync Period: Set by VSW, the Vertical Sync Width Field: 47 lines required per display field (i.e.: frame). =====> 7-7 94 lines per display (iv) Display Period: Set by SPB, the Split Screen Width Field: Hl24 lines required: Note: (v) Only the Base Screen is in use. Front Porch: This is not specified directly, other values. Front Porch Note: = VC - as it is the remainder from the (VDS + SPB + 2 x VSW) This equation uses values calculated, loaded, as sometimes these are one specified in lines per field. Front Porch = Front Porch = 1333 - not the ones less. VSW is (lBB + 1B24 + 94) 115 lines per frame As the split screens are not in use, SP1 and SPB does not have to be defined. As the address register auto-increments, it is easier to load these registers r8C and r8E with say, $BBBB than to specifically skip them. ~his also applies to the blink control, window display and graphic cursor control registers (see Chapter 4). However, if most of these functions are not to be used, then it is better to skip a continuous group of registers by reloading the address register. The unused functions can be left undefined. The registers so far initialised, (r8B - r8A) are the minimum necessary for the timing control RAM to produce a stable raster timing. The result of the vertical timing calculations are: VC = $535 VSW = $2F VDS = $63 SPB = $4BB VDS and VSW are combined in register r88 (VDR). The result that the three register have the following values. r86 = r88 $13535 r8A = = $632F $134BB This completes the programming of the Timing Control RAM. 7-8 is, 7.3 Display Control RAM (rCe =rEB) The display format is specified through the use of this registers. In the example that follows, only the Base Screen will be used for simplicity. The other screens do not need to be defined, even it is not enabled. Configuration is further simplified as the character mode (only with the IX-option) is not used and neither are the cursors. The following therefore, represents the initialization of the Display Control RAM: minimum rCe - rC6 Upper screen - not defined rC8 - rCe Base screen - to be defined rDe - rD6 Lower screen - not defined rD8 - rOE Window screen - not defined rEe - rE8 Cursor - not defined rEA Zoom factor - to be defined rEB Light pen - read only amount of We only need to Base Screen Definition: rCA - Memory Width of the Base Screen The hardware supports 2 Mbyte of video memory. consider the Base screen. The display is 128e x le24 pixels, each of 4 bits. As the base screen occupies the whole of this, it represents 64e Kbyte of data, nearly a third of the video memory capacity. If no other screen is defined, there are many possibilities for configuring the base screen in relation to the video memory. The horizontal display width is 128e x 4 bits = 32e words Recall that HDW was set to 8e cycles and using a GAI = and Dual Access Mode e 8e x 8 HDW = --------- = 32e words 2 +8 The base screen memory width can be made greater or equal to this value. 7-9 (i) If the memory width is made equal to the dislay width MW = 320 words As the video memory capacity = 1 Mwords it will support: 1 Mword ---------- = 3.2 k or 320 3277 rasters This will allow vertical scrolling, but no horizontal scrolling. (ii) If the memory width is made twice that of the display width, MW = 2 x 320 = 640 words Frame buffer capacity = 1 Mwords, so it will support: 1 Mword --------- = 1.6 k or 1638 rasters 640 This will will allow the display to be scrolled horizontally and vertically. The offset has both horizontal (X) and vertical (Y) components. The memory width is 640 words, the display width is 320 words. = 320 words total margin 640 - 329 Equally divided between left and right margins gives: 320 X = ------ = 169 words, the horizontal offset 2 Likewise, the memory supports 1638 rasters, the display uses 1024 rasters. 1638 - 1024 = 614 rasters total margin Equally divided between top and bottom margins give: 614 Y = ----- = 307 rasters, the vertical offset 2 Choosing the latter result, means that the memory width base screen must be set to 640 words: MWB Hence rCA = $280 = $0280 7-10 of the Start Address: If the display screen is to be positioned about central to the video memory, the screen start address must be offset from that of the video memory. It is now necessary to calculate the word address of the starting point of the screen from these values if offset: The start of the 308th raster will be 640 words x 307 = 196480 words from the start of memory, adding a horizontal offset of 160 words. 196480 + 160 = 196640 words from because the memory starts at address $0. Base Screen Start Address the start of memory, $30020 This value is split between registers rCC and rCE, because no smooth horizontal scrolling can be applied, the start dot address (SDA) is $0 because it has a 20 bit range. Therefore Zoom Factor rCC - $0003 rCE - $0020 =rEA This is the only rema1n1ng part of the Display Control RAM that requires initialization for this minimum configuration example. As no zooming is to be applied, both zoom factor are zero. This completes the programming of the Display Control RAM. 7-11 7.4 Control Registers The final stage, if initialization involves the 3 control registers CCR, OMR and DCR. The address register does not autoincrement when referencing these control registers, so before each write it is necessary to point to the required control register by suitable loading of the address register. The preferred order of initialization is: (1) Command Control Register (CCR: rB2) (2) Display Control Register (DCR: rB6) (3) Operation Mode Register (OMR: rB4) Together these registers hold 3B fields of control bits and each must carefully be considered in relation to the application. Chapter 4.9 gives detailed explanation on the function of each field. The following example applies to the example system and represents a simple application for clarity. (1) Command Control Register (rB2) Reset left thi p register with the value $8BBB i.e.: ABORT set and all others cleared. Bits 7 - B : Enable/disable the interrupt sources. This example uses polled status to control transfers and so all this can be disabled. Bits 8 - IB Graphic Bit Mode, this sets the number of bits per pixel. This example uses 4 bits per pixel, and so the mode is 'BIB' i.e. $3. Bits 11 - 13 : The DMA control bits, as DMA is not used these are all B. Bit 14 PAUSE: This bit halts the command execution, permit commands to be processed later. Bit 15 it must be B in order to ABORT Reset left this bit set, it must now be cleared to enable command execution later. The above values can now be written into the CCR The resulting value is thus 7-12 - $B2BB CCR. (2) Display Control Register (r~6) The DCR controls the screen organization and provides 8 bits video attributes. Bits ~ - 3 Colour Look-up Table Control : In this example LUT set to $~. Bits 4 - 6 ~ is used for display, so this bits must be Display Mode Control : Since 4 bits per pixel are displayed, set to '~~l' i.e. $1. Bits 8 - 13 for the value of these bits is Split Enables As these screens are not used, therefore they not defined, are all cleared to disable these screens. they Bit 14 Split Enable 1 (Base) : This bit enables the base screen. must be set = $1. Bit 15 As this screen is in use, it DISP Control The DISP signals, together with the HSYNC and VSYNC signals, allow blanking of the video signals and generation of front and back porches. These can be used for driving display monitors. DISP 1 provides a combined horizontal and vertical blanking signal for both background and window screens when this bit is set. In fact, this example only uses the base screen, the bit could also be cleared, when DISPI only applies to the background screen(s) and DISP2 to the window screen. In order to allow a window screen to be used later, set to $1. Therefore the value of the DCR is 7-13 this bit is (3) Operation Mode Register (r94) Reset left the two most significant bits cleared, change any others. Bits 9 - 1 but not Raster Scan Mode : In order to operate in interlace sync & video mode, both set i.e.: $3. Bits 2 - 3 did these must Access Mode For improved drawing speed the SYS68K/AGC-l uses access mode (DA9), hence these have the value $2. interleaved Bits 4 - 6 Graphics Increment Mode Because of the hardware structure of the SYS68K/AGC-l are obtained from the video memory per display access, addressing must increment by 8 words, so set GAl = $3. 128 bits hence the Bits 7 - 12 : These bits are all set to $9 because of the hardware design the SYS68K/AGC-l. Bit 13 of Access Priority : To avoid disruption of the displayed image due to drawing operations, the display process will be given priority over drawing, hence this bit will be S9. Bit 14 START: This bit was left cleared by reset to stop all drawing and displaying. In order to activate these processes, it is necessary to set this bit = $1. Bit 15 Master/Slave : As this example system will not be sychronized from an external source, this bit will be set so as the ACRTC acts in master mode. Therefore the resulting value for the Operation Mode Register is: OMR - $C93B The initialisation of the SYS68K/AGC-l is now completed. 7-14 APPENDIX TO THE HARDWARE USER'S MANUAL FORCE COMPUTERS Inc./GmbH All Rights Reserved This document shall not be duplicated, nor its contents used for any purpose, unless express permission has been granted. Copyright by FORCE Computers® A. SPECIFICATION OF THE SYS68K/AGC-l. B. MEMORY MAP OF THE SYS68K/AGC-l •••••••••••••••••••••••••••• B-l B.l. Standard Memory Access •••••••••••••••••••••••••••••• B-l B. 2. Short I/O Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2 C. ADDRESS ASSIGNMENTS AND MEMORY LAYOUT OF THE DEVICES •••••• C-l D. CIRCUIT SCHEMATICS OF THE SYS68K/AGC-l •••••••••••••••••••• D-l E. CONNECTOR PIN ASSIGNMENTS OF THE SYS68K/AGC-l BOARDS •••••• E-l E.l. Master Board Pl ••••••••••••••••••••••••••••••••••••• E-l E.2. Master Board P2 .•..•.••.•..•••.••••••••••••••••••••• E-2 E.3. Master Board P3 ••••••••••••••••••••••••••••••••••••• E-3 E.4. Master Board P4..... • ••••••••••••••••••••••••••• E-4 E.5. Master Board P6 ••••••••.•••••••••••••••••••••••••••• E-5 E.6. Slave Board Pl •••••••••••••••••••••••••••••••••••••• E-6 E.7. Slave Board P2 •••••••••••••••••••••••••••.•.••••.••• E-7 E.8. Slave Board P3................................ • •• E-8 F. COMPONENT PART LIST OF THE SYS68K/AGC-l BOARDS •••••••••••• F-l G. LITERATURE REFERENCE ••••• H. DEFAULT JUMPER SETTINGS ••••••••••••••••••••••••••••••••••• H-l • •• A-l •• G-l APPENDIX A SPECIFICATION OF THE SYS68K/AGC-l 63484 ACRTC with 8 MHz Clock Frequency 2 Mbyte dynamic Video-RAM with l20ns access time for 2048 * 2048 pixel (in 4 bit/pixel mode) up to Direct video memory access via VMEbus during display time Zoom logic for magnifications in direction up to 16 horizontal and vertical Smooth scroll logic for vertical and horizontal direction Video interface bus for upgrading with character overlay 3 Graphic Color Palette AM8l5l with 256 entries for each color and 64 MHz Pixel clock Bus Interrupt Modul for all local Interrupt sources Interrupt handling via programmable interrupt vectors Each VMEbus IRQ level can be enabled/disabled via software Fully decoding of the address modifiers Jumper access selectable access for short I/O or standard memory RUN/LOCAL switch for complete isolation Fully VMEbus and IEEE P10l4 compatible + 5V - l2V Power Requirements per slot (max) (max) Operating Temperature (degree C) Storage Temperature (degree C) Relative Humidity (Non-condensing) Board Dimensions No. of Slots used Thickness 234x160mm (9.2x6.3°) 2 3 8mm ( 1. 39 A-I 0 ) o to 50 -40 to 85 o to 95% 4.9A 1.0A APPENDIX B MEMORY MAP OF THE SYS68K/AGC-1 STANDARD MEMORY ACCESS The Board Base Address (BBA) is jumper selectable in 256K steps Start Address End Address Memory Area -----------------------------------------------------------------C35FFF BIM 68153 13.824 times C369riH'J C37FFF GCP 1 red 16 times C38999 C39FFF GCP 2 green 16 times C3A999 C3BFFF GCP 3 blue 16 times C3C999 C3FFFF I I I ACRTC 63484 I I I Video-RAM 4996 times -----------------------------------------------------------------C49999 E3FFFF B-1 1 time APPENDIX B SHORT 1/0 MEMORY ACCESS The Board Base Address (BBA) is jumperselectable in 4K steps Start Address End Address Memory Area -----------------------------------------------------------------C995FF BIM 68153 96 times C99699 C997FF GCP 1 red 1 times C99899 C009FF I I I GCP 2 I I I GCP 3 green 1 times ------------------------------------------------------------------ C99A99 COOCOO C99BFF COODFF blue 1 times ACRTC 63484 128 times only accessible via ACRTC 63484 B-2 Video-RAM APPENDIX C ADDRESS ASSIGNMENTS AND REGISTER LAYOUT STANDARD MEMORY ACCESS ~ THE DEVICES FOR The BIM Register Layout Default Address Register Name I Reset I Value Function CfiHHHHJ CONTROL REGISTER 1 $00 C00002 CONTROL REGISTER 2 ACRTC Interrupt $00 C00004 CONTROL REGISTER 3 VSYNC Interrupt $00 C00006 CONTROL REGISTER 4 reserved $00 C00008 VECTOR REGISTER 1 reserved $0F C0000A VECTOR REGISTER 2 ACRTC $0F C0000C VECTOR REGISTER 3 VSYNC $0F C0000E VECTOR REGISTER 4 reserved $0F reserved The ACRTC Register Layout I Default I I Register Reset I 1 Address I Name 1 Value 1 1----------------------------------------------1 1 I I 1 I C3C000 1 ADDRESS REGISTER 1 1 $FF23 1 1 1 1 I I C3C002 1 FIFO ENTRY 1 $0000 1 1 1 1 1 C-l APPENDIX D CIRCUIT SCHEMATICS OF THE SYS68K/AGC-1 BOARDS D-1 I A I B ADDRESS ~~1~OIR 30 :29 Pia Pia !6 p1a9~ 1 BA1 A !5 BUS J6 ALS645-1 J1 Pia 74LS682 VMEEN/ ~G~1~9~~~~~-------~. __________~G~L&E~I~C/L-______________________-1 1 ~ 14 B 13 A J15 ~--..I?*----1 --------.!6'4(1-!- ~~:~~4~~~A~---t---;1~2 Pic 11 GNO VCC 110 \20 G~b J2 -- CONTROL 74F08 BUS VMEEN/ Pia ..22 BIAOU/ P1C~~==~A~:~==~==~ Pic r:: Pic t::::Jo;~--~A~~......,.._t_--;1~ Pia 21 BIAIN/ Pia 20 BIACKI ~G ~1~9~~V:.!i!M~EEi:!:N:LI/_I_-------1 1 A GNO VCC 110 120 rl I- lR[I/ J12 3 AM tC:: 1---*----*+-:lo'i'f A H~ I......"·.. ..j :3 '---...lo + 1 1~ vce J16 +5V 3 J9 74LS682 -~--------------"~~1--~1 P>Q P-Q~~ 1 ~1~------~ 1 1 Ii 11 '3 J14 15 vcc GND ~----III---t!l 1n~ (!I I-- P1--4-----.. . . . ~======m~111 .. 1 14 Q !2 16 'Ho 120 Gtb '+5V /12 L---,3~1( I1 DATE '-..J 74F32 NAME 21.3.86 S.E./J.B. 3.6.86 S.E. 15.9.86 S.E. REV. 3 SYS68K/AGC-1A 10 3. :3k lL-____________ ~A~____________ 1 _~ 5 74LS74 ~~-~~~------~__----~~--------------~ o GNO 4 ~ I-- A3~~~=========~...J A4r- GND D J14/15 1_______..!oY J4 6 AS/ ~ Ai A2 hl1~4-------...J ~ ... f1I.lo!.....______-, ""--!oL........_ - - I 1---_...........EB;!!o!IO!!:!;RS~~F:£' F'l1]2 ,S A :/ 1 P1a~~--~~~----~ ~~ ~ ~ ~ CO B 1 Ii C4 e-!'!.............-+-f-H---.........!:iB1 C24 GG ~1~9"""""'---IfjI~~I]ET~1T.I-------- A 74LS283 j Q 2 vce 5 74LS04 ALS641-1 P1br:: .c Ul ru 82 L.{4LS04 Q) ..., 10 2 1 13 J8 ~m-, ..,.l::..... llr..:L-....J plon R' 6 :3 CLK "'i'fIQ~-...J r--. J12 '1-- J 5 +5V 1~4f-- ~ ~~~------~+-+, +5V J13 '--.......D ....T""A.... C _1I.........__-=t1""'"' 2' \ CLK:3 ~ o ru ru A1I---4---41~ GNO VCC 114 1 I-- G.N D A2 .. __--' A3,ri'uo...... 2 ____- - 1 A4'- 2 1:: 2 J11 VMEEN/ m i1 :3I:!...-----. 4G'lA +5V Gito '+5V ~ 74LS04 1...-_ _ 116 '+5V 4 z IIIIII II; AMi m m ~U~J~ -rri 7 CO B C4 e-!'!.............-+-f-H--I-.........!:iB 1 J12 G 19 A '--____~======A~C~/~==~4Y 4A GND 1 I 7 4LS283 GND G;;O 5 12 \.41:t:==i:tl:ttt:=~ u J7 1 1Y :3 2A 1/ 83 '+5V o A 2Y ~::::::::::~Ia:A~[~~/;:::::;l1A :3Y AS/ t+5V (0 ~ ..iii '--__________~V~E~:J~1VX~:/r_---tTI~:3G +5V ALS645-1 :3 r: II III,., ~~~ ____~~~---. j..i!1il2......._ _ _ _~+-+-+4I--..., 5 ~~O~C~E~N~__~6~i~~5~ ~ 74LS04 ~--~A~:--~ J--.,{.--~~--1 A: Giio 81 3A-i- A P1c~~--~~ODR~,~--~1~ J4 ~============:jA~~~j1~5 A!3 1 74LS125 t +5V A Q .. ....1 J10 ALS645-1 ~~t:::~A~1~Bt:~==~ Q) t:=====~A~~1~1 P ~____________......,A~1_71L~3 GiiD GNO VCC 110 \20 ~--riH1 OIR Pic 2 B A 1 7 11 Pic IA18 1 Pic A :0 1 P 1c t::Jol~--~A~1---t----rn B IIII NWhl\Jl~'l' 1--.-'____........~I-+.f-+------~1 +5V 4 1 1 J3 J G~O I'lz~1~I p_Q~9 A ,B ~------------......,A7,*-9~ ALS645-1 G~b 141 +5V GNO VCC 110 120 1 2 GNO ..,. _-I---------------_t_---;ttlp>Q t +5V G 19 E D C ~B______________~____________________~ FORCE COMPUTERS __________ SHEET 1 VME BUS INTERFACE FROM 9____ SHEETS ~__________________~ ~ D J35 J29 J13 +5V c B A +5V J31 en m :J 68153 PAL20LB IRQ7~~:tttttil~~ IRQ61-i +5V S 0([ IRQ5tfl--~++~ .... IRQ3 IRQ2 IRQS U IRQ4~E~~!fI~1 az .~ J34 +5V 74LS74 en m ...J . -_ _ _ _~v~~ :J en 74LS112A ...J DO J35 a gil==Jt=j: 1---"'-.....xJ:!t:!60....-.ri ([ .... z D4 D5 U a w o J40 2 ...J a .... J1474F32 z a J30 74F16474FOB U +5V o 85 J27 J33 74LS139 -----~~----~~~SG ------SA L..-----"! SB "---~~ i8'T-------~ SYO J34 (() ~ ::::=i1;1~======::ISYS ___lI1Y2 ___--dr.!:~U___ _ _ _ _ _ SY3 OJ 74LS112A E .... en en w ([ o (\J (\J en m SW2 :J a OJ ~ Z ...J %1---- a 2 ([ .... z ... 4 _ -.... 3 > + SW1 5 6 a In ...J +' 4 i~ :J ~ 74LS85 86 en m m m m 3 J36 (() o m 3 J15 10 en :J o o < 5 -rt 0 en m ([ m < :J H > .... g~~==:tit=:1 a 2 i-----I;A!--......:J U ZI--- 74F04 2 a U DATE J12 21.3.86 S.E./J.8. 3.6.86 S.E. 15.9.86 S.E. (Y) .c. +5V 1/1 (\J , A B NAME FORCE COMPUTERS REV. 3 SYS68K/AGC-1A SHEET 3 INTERUPT LOGIC FROM 9 SHEETS B A CONTROLL 1--+---.fi2.. CaMP 1 ......- CDCO IJRWEN CDCi 2L" 92/ MA317iriQE'~-"" MA4~~;""-"" MA5&-*i--.... MA6I!M-iEIIIl'--.... MA71=-.-.'---.... ~ R3 9ND 1 : ~ IRef 23 VEE 9ND ~~~:::::t::tI _~~o VCC ~+5V VCC 1 9ND \0 \Of-- ti . ,. . CD U ~l I"- U .-BNC2 cpo 5 CDO 1 l4 CD1 ,3 CD2 ~_",*,":iJ..4L~ 2 CD3 r---~H!~9ICD4 ~-,,*,";c.. 21l . CD5 ~_,,*,"~~ 2' CD6 ~_...!t!:.L~.s5!I CD7 RW2 12 RW3 2Y 7 .Ji ::3:: :s~ PAL16R4 ~ Y7 gLI!=~~[:~::i:~C~K3~~1 fS :K' 1 19 9C I 1 t- l- 1l 1: DHS 'N[ fN[ VI C 9NO • NS , _10 VCC 120 _J...330 120 GND t+5V +5V J46 , ~'I-e;.D......._ -,-,_ 7 4F244 ~ C 1 19 ~lla~1A 111=~t;~B"~'dJ~ 5 EBI~~2A ..1.S 1Y ~ f 9 11 VVDU2 II 111:1 I DD4 DOD J51 VVD B 1.....,1 DIR _J;0 9ND VVDD7 9ND ~ 004 rn 003 11 OO~ 11 Om: 3 VV005 4111D vvon6 !'i lo::D vvon7 i:;~D VVOOS 13 CATH VVDD6 T VVDOB ~~LK m ~ 9ND '1-- t-.1_4_15_~...JV,u,IO!!iI..B ..... ATT2 g __ +I 10 o 4 BLUE 9ND ~ W ~ _e-__~.J~V~OB__Jl---~C~DC~:i~~--~2LJ 4. .... 5 O"Il CL _~ +5V ~Jl1"- 74F157 , N 12 Y4 ~~~ ::3 VCC B 113 3 74FOB J71 ~_ _~CA~T~rt~~_~4f'\ 6 CLK1 CAT44 5L/"""""--1 J41 Y1 I-- 74FOB 10 J53 r.AT2 74F257 vvnnH A/B 1A 000 1B 1Y 1! 2A om. 2B 2Y 1 J41 OCLK1 ~ orb f- CATn4 -"l t--02 1 0t:::.. 7 4F0 2 _e-_---iJI£.l'VUlfnL!.·7_.... --..Jojc~AT.!..lrO~~-.a! ~I\ 3 .JvnB I 11 J41 7 4 FOB +5V BNC3 Ql .JVDB 10 DRWEN ATTO o r-- .... S 2 9ND 91 ATTi liB 74F245 R/W/-, ~ 818 t+5V m J48 J26 .JV08 CATO i 13 I-~ (() m BNC4 SYNC BLINK2 CAT2i vcc 74F175 9ND ... .JVD7 .J.:0 120 T20 t+5V ~j 1 3 BLINK1 IfDOS OO!'i 111 1 B 9ND 2 - OD7 []J 9ND VCC N t -9 I-f19J VODe 11 nDO ~ .JVDS 74F245 ~~D .. 2Y 88 vvons J52 (\J (\J +5V I- E21 DD4 on!'> OD6 m: GREEN ....E 1 DTACKI Fro Ii ...-t----I.A:u.T..!.:T30!....-_la 1 Ql 7406 J50 C5 J43 AMB151 g: 2 YN OVER RW1 116 9 29 r-,1ll"N![K~:::t:::jt---"!=!:!!Q!L9 o~ H ~R 1 == ._ 9i~'o 1Y BLANK VEE11Ia VEE 9NDiO-C6 ~ VEE g~gl;r~~"" ~ 1!:t Ref9ND -or 9ND 2 1A is 12 ~ >-fITGND HSYNC 2 +5V tIIJ .. 19 CATO I....; :AT1 o ORef vs~~tiiWmrN-[--'"~· RED ~Jl:t;;1,_ 74F32 7 4F244 ~ 1111 ~ MAO 4 n MA1 t--*-liEIiEli--.... MA2 .......~i--.... CSYNC 11 lJ3~ J49 . t~~ - PAL16LB !oD J45 3 1 N 9ND 1~ I J40 1--+---~COMP2 CLK~,T'blcr-ILKK;-i-ir-I==:j;~il ~ LC + v 2A Eii' BNC1 J38 .,..lCt=---f-k""kJD1 AMB151 t-_4Cg;P~0~1~ CDO t::=:I:Ptli CD1 ... P: CD2 p. CD3 I:I! CD4 t--~p~liiI CD5 t::=~Hl6I CD6 .... CD7 D BUS J42 1 I C CAT2i S 1 if li, GAl 3Y 002 4 4B1fl....._ . . J .Iv 3 om- v 3B ......._ _---J DATE NAME 21.3.86 S.E./J.B. 3.6.B6 S.E. 15.9.86 S.E. REV. SYS6BK/AGC-1A 3 A CONTROL B BUS VIDEO J14 74F32 1 13~ DTAC2 t---j;i:5---ti~D5 t-~~--ti~D6 t---j;iz------il~ 07 t-~fl(_--ti~DB r-----tli'f...----!lHa 09 t---j;i~1T--~D10 t---j;i~1""--MD11 t-~~1It--~D12 J611 DTACKI 3 t::::~~::::::il11 013 .1 014 --""""-----"""1015 +5V _ ___.H1;;;j4 VCC 2 ~t~~~~~~4::~~~b:;:::;~A;1;::::: M19/R31-i6O~_-~LJ.:!~-mA~1~-1 RA4~-"'C::J--=-~A:!i:.l£.2!---- GNDI-.~1i¥1B GND • ~GND R/WI 3 BZW '--_ _....._ _~4 CS Fii4 2 e~ipi ~---r++-~---~---~~A~;~r-~8.i~K ~1tl1D1Il~" r---------~M4[~gTB +5V ~IIIIIII .. r---~2CLK +5V I ~ U -r- GND ~ COD2 VCC DIR 1~""1 2 t ~-r +5V 201 74F04 g 12A GND 1B 115 1Y 3 H- :I .!O~ +5V1G*D J71 OISP2/ J63 IV 2 ~Y4 2CLKI 2CLK t+5V -lJ Y3 SCLK Y2 r---_=>.:..-""'Iy 1 -a _ _"""A..... ·TT ....7'--"""'ri!1 S ,;oG 810 d 4 GND 74LS125A III C\I ~~ 1 A2 Ai 1 CLK211 ~g ~4D1'~~!---I rNI.i~ W4...ta 1! 3Q 4Q r=-~ GND G*D VIDEO B VCC t:v CONTROL BUS ATC 2CLK CLK1 ~ CL ..; ~K HSYNC J41 74F08 ++5V I HSYNCI 74F02 O~________________________________________~________________~____________________~____________________________~ B DATE NAME REV. 21.3.86 S.E./J.B 3.6.86 S.E. J26 ~11 13 ~..:!..:!..f 1 1'~ \... ....2__~ LC r 13 11 ( = - GND VCC _~ B ,41'~ GND A pI CLK31 --' ENP ,C B4~13 3 B3 AO 10 1Q 3 B2 CLK21 20 2Q B1ITT......,......---1'---'i~1...-;171E1/2 3D 1 OISP1 74F163 ~g 1.0 74LS375 4'4F04 J65 1 _--' P4 t::J-.... J70 74F157 7 4F04 120 GND DISP2 4 r -____________________~r---------------------~~~------------~1uy1~10 o lO 2 VAS 74F04 9 2Y .i2 J63 OJ 74LS374 1~~_ J63 ~ 10 74LS373 VCC 19 2G _J.~O lO .jJ !;uD1L 74F04 GND vcc m m C\I C\I J69 J68 _ _~V~SY~N~C~:/_--1 VAS/ 1 IS ...--II-->'tI 1.,..Iil.Q.. 2 r-+--+-+t--ir-'TIi:!4 '-il-1A 2 _---, P4 t::J-.... P4 t:::I-=4--, !O~ +5V1G*D GND 74F241 3 m o • GND JlHSYNL ~-r--~GnLU[~D2~!,/~-~ J64 E GND VCC t+5VGND 3 ~ ~ Q21-*-~~----'I Q1I-=--................--1 1 L...-_ _---f_..:!.1=-/3 1 ~1~ P4t:::1 9 GND Q51""it--tm....,;:,s----1 G4Ht--I::iifRi'i:!t--1 Q31-ii--~;;E;,1r----1 ~_ _ _~CiW!HR~_ _-t ~ OJ I- Q6~1*--+i~--1 Q7 .... 1;E---.i=I-Pi.....- - - + i4l07 Q6~ 06 Q5 13 05 Q4 ~ ~ Q3 11 03 Q2 02 Q1 01 1-i!-4---~~~~~'~e;I:W~I'/-_-1 VCC 1-*1 Z3 QB I19 Q7 ~1r---tiPf7---1 r7-3_ _~M~R[~_--1 BArr- pISP1I~ LH~----t1"'gij QB 19 .:O~ +5V1G*D GND ~ G 1EN J63 P4~ .r'! VSYNC/ 62 -.OISP1/ +5V VSYNC 1 7 4 L S6 4 5 J67 1 TC-l...rtEN .1 1 CL .1 1 DB 1 1 07 .~ 06 05 r----HT-K--iIiIID4 t--ofi'r.;r--4 71ID3 ~IO E~ HSYNC BUS 74LS374 7 4LS373 t--.fP.;A~-;;!ID2 HSYNC/ 89r---e 8 GND HSD3 t--"""",,"'---=tID1 1 11 CUD1 J66 HSO", 74F04 1 1 1 '....- 6 J63 1 19 CHRIii5~6:-----------~ o 1 ~ 4 ~ ~----~-+----r---~~~:~r--m!1;5 CONTROL DHSYN/ 74F04 tHi--1 ~VCC 74LS125A -V MADO Hl6H1-......;Il~r-J-'72--iMnA:.:r0_-1 MAD1 FA1 MAD2 HiHi-~L::Hi--in~~--1 MAD3 ~-~LFJ..4--i~-"'" MAD4 1-7ir-~l.:..J"'ii--m~'i-'--1 MAD5 ~-~LJ-+--m"'--1 MAD6 t-=rl!-OD-F---f¥i~~I-1 MAD7AI MADB 1-=l4~4-~iC:h*--mA~--1 MAD9 MAD10 n;E1~-~LJ-+--iMnA'T1T-"'" ~2 .11 MAD 11 1.:pf-1--;~o-w--¥.lrA~12itc---1 MAD 121-*-lI...&lLJ-ii'--mAT13i5-...... MAD13 ~-~Lh""'-mA7'147---1 MAD14 ~->j[EEJ.:!~-m~--1 MAD15 ~---.[!oaJ-T--n~Ti': M16/RO~-~LJ-~-mA'T/if-1--1 t-~~0---'Hd7 DO r--___;,t------'!'i!f 0 1 t---j;i~-........t;(ID2 t-~!'f---ti!¥l1 03 t---j;ir------il~ 04 BUS J63 ACRTC 63484 BUS ADDRESS VIDEO J60 DATA o C 15 9 86 3 SYSSBK/AGC-1A S E FORCE COMPUTERS ________________ SHEET 5 ACRTC INTERFACE FROM ~________________________~______~ 9 SHEETS o C B A VIDEO CONTROL BUS ZCLO! J75 B11 :3. 1 P4 .10 P4 .11 2. 1 +5V 5 ..! G 14 7 110 f,11 ~~6l9~ 1 _c T~ CLKO GNO B CLK GNO HZ:3 " VEE4 G~~ JiB 15 ~ISP1! 14 1====1 ;:s 1====1 4 - 1====1 =.Ji 5 ~- 2~4 GND :3V 11 In 10 m .... Q) E ·n :3 I- ... ~r III (() -- ~r m m .... MA ~ ~ vc~fC 'EE o .r: UJ OJ o~ ~l] l' J76 SPAEN CLKO SMCYC! ~E4 111 .....§ = = = -= VEE4 ~. :3 51 2 r 2 ACKA 74F74 SMCYC 1 2 1C1r 0 :3 Clk PR Gi-i'o N1:3 1 11:3 Clr 12 0 +5V Ii ~ VPRZ == ~~6l9~ GNO +5V 1== i== - VEE2 6 7 2 1~6 1====1 G*O- Q 9 11 Clk J82 J8t 19 1 00;:' 74F153 ZPR1! ZCL " 11 15 LI"H~ 1 14 12 ,1 B 10 1 5 f-' GNO J77 foAl 2 ~ GND VC [5V 15 B Gito SPAEN ~ Y I5LAN~ _XU VEE4 :3 CUD1/ (;UD21 Z(; .1 HZ2 VPAZO Q~ 74F74 GNO VCC 5 ~O fA 74F74 TDD4 GNDVCCVf" i== t5V J76 4 Q ...§.. .::it'11 VEE1 J79 :1\LJ 11 .;3 1..t!!4 CLK2 Q~ :3 Clk PAL16L8 ~ HZO 5 ~+5V 110 HZ1 ..! H. F 1010_5 ~l] Gi +5V J40 7oF1 B CDCO L:] 4F32 ZCLK F10125 e.&i,t OATE - 11====1 NAME 21.3.86 S.E.lJ.B. 3 6 86 S E 15 9 86 REV. ~A~ ______________ ~ ________________ __________________ ~B ~ __________________________ S E ZOOM-LOGIC FORCE ECL-INTERFACE COMPUTERS ______________L-______________________ ~~ 3 SYS68K/AGC-1A F10104 .. GNO __________________ 1 1../ III (() 7 J78 ... 4 9 _fJ1~l ~ VEE2 Q) (() 1: ~ GNO OJ OJ co F10124 4 a .jJ F10016 V~4 ~ GNO m 12 J73 PO Pi P2 P:3 ,.n CLK1 +5V J72 QO Q1 Q2 Q:3 TOIS1! 4 PR Q 5 114F08 F10125 VEE2 +5V 1 Clr ,...5 0 CLK1 J77 a CLK211 J80 9 12~ ACKAO F10125 (f) (f) Q B ZPRO/ 4 +5V 11 J77 ~ CLK21 74F74 J1174F245 2~1l F10125 1,lill, 2 Q 9 1:3 VEE1 2 1 10 PR 11 Clk +5V r G*07 J77 ZCLK ~! ZPRO! 1:3 Clr ~0 T 0 QA QB QC QO 1 QE QF 11 QG QH CLR VCC C16 L B ~ C15.lIL 64MHz GNDVCCVEE GNO +5V TOISll 101 ~O ~+5V J80 74F164 B ~ 1 J74 Q2 F10124 SHEET 6 FROM 9 ______ SHEETS ~ ~ J85 J86 74F251 1 J93 ~ 813 74F164 74£"~64 ~D,OI-~-----"'ft~IU TDOI o C B A tt nAtANt( J96 A " .. "......... 11~ RAAAIIA 2 1-.& B ::::: ~~ ~tI!:GHr.;ii--, ...- 8 1 c;ar ~ ...JI c~~LJl CL.K SND. V( :r. 1 7..,. CL.KO Ul :J ",- Ul :J m a J87 z a 74F164 u J88 J89 74F251 74F251 ~~~S HSYNC 2 7 11 w ;::~ 1 ::: VCC HSDO HSDO 1i ~ J90 u I -..§.f1~-HI' L1. ~~ QD~:)~I-..;;t.._-_-_-_-....;"fliiHI~~~~ 7 4F 164 U r- 6 DHSYNI 6 DHSYNI ~ ..-r+-r-e ~tI;BI-___~ ~tI~CI-*-----I Q? ~I ~; D5Hr.w----t1Af~Q'_F ::g::~=~t2====::t1:~I::~~:~:-::Q;::;-;SHr;t-~ ... , GND 1....1 J..," ...--"'"I~C~LRCI ivcc VCC CL.K I--IJlii.f-lSC~L.KI......o~....iCIIIloL_~K:1L..---tJl CL.K cL'P""'! GND VCC GND Cv ..:t..l ABE 17 9. +5V -AI:"' +5V SMCYCI 6 ii "J .. 2 J40 MCYC Clk !-'S _ _ _ _ _ _ _ _ _2.__CL.K:&,.:,/--1 VAS RCA ~....IC_L_Kg",ja~_.... BCl:K ,END 7 RSE ~0 J32 IU SPRCL/ -ii:"' ISr-----=-/.=.::::9.:====:M:RD::=:t---Jou;;J;!l~---------. 1 Cl~Dll1_La,,--__Jl'""1J ~ DRAWl --i1~J.r ...§ Iii Clk ... 111 ______ "-_~':3~~~~~:::~::1:1~/_·T-1_- Q) +J 4 SMCYC a _:_S_MCY"'"""-C_ _ _ _ _ _+-"'I 3 Clk 74LS21 74F74 f'. (/) (\J 10 A B a a: ~ ".!ill...B __..t;;!R__ SE--r z aU 2 J96 S :: ~!....11t.&..-__ RCK:Ial,AI'O~ ...lJlIA: ~4F86 ! S 1 816 a 1 1 t":!5 = Giro .. CLL-_,A".---. VC 14 +5V 6, SPREN SPRENI 22 DATE NAME 21.3.86 S.E./J.B. 3.6.86 S.E. 15.9.B6 S.E. FORCE COMPUTERS r:. 2 ...J J92 J4 74F74 SPRCL./ m WI 1 ~~ 74F74 m J91 +5V 12 1 1 6 f-JL ~ o Ul :J S sI !t--=-6 ___-.1'-'"fl1 Clk 74F32 CASI 4 L/' 74F74 ! ! 815 RSE J 91rm.r4.,...1r'=1 ! L----+____-+-______~...., I, +5V 8 1. tv ________________~SMCY~C 1 4F04 81 7 ~'- T GND I ! B 5 Ei IL:] 4F86 4F04 ~.j._!;r.&a!,AAiiiI!iJAIWIIIAIiiL---_+_-JlIi!.I ~~1 ~~ 1:!0t:::!iEIlM::t::::mim~o~ ~~ T ___-+-' f---4 ~-------~------------~ C2S ~I~ GiiD (\J (\J 10 RASI J97 J94 6 7 4F 164 2 J97 gl~ .WAUS \. J97 J96 .WEIN ~ m m B ~ I !6 S 4 IL:] 4F86 4F04 8 1 iI 16 ,...--...... =e. ~~ 10 51 a ~ m r.AAAlJA ...J a: (f) 41~ L-------:::8 +5V m ...J .. 10 eND 1 1~4F86l{4F04 r.AA~TN BL.ANK r--..., S J96 Q:E=~--~ CL.K21 I ! J97 REV. 3 SYS68K/AC3C-1A SHEET 7 FROM 9 SHEET A B o C 1 1 OHi 014 1 2_ 5. P3e ~- PSa RESET I 7. a_ PSa LWDRDI 6. 7. P6a OERRI a. PSa CLK3 P6a DC EN 9. iO. PSb 5_ PSe PSb DTACil S. PSe PSb DDNEI 7. PSe PSb REAOYI PSe P6b ATT3 a. 9_ PSe P6b ASil 10. PSe 11 PSe 12- PSe P3a P3b P3e OGTE1I a. P3b 06 a. P3e BOEN51 ORAW/ 05 IRQ1B/ 9_ P3a VDDB P3b D4 9. iO. P3e iO. 9. iO. P3b CHR P3e DACKOI iO. ZPR1I 11 P3a 1at::lP3a i3. P3a MA13 11 11. P3e DOIR 11. PSb OTACKI 02 Di 12. i3. P3e LAS/ CLK2 12. PSb MA20 P3e CLK:H 11 P6a 12_ PSa i3. PSa BRI MA12 MA11 P3b 12. P3b i3. P3b 03 1~PSb " b PSe i4 P3a 16_ P3a is. P3a MAiO i4 P3b DO i4 P3e UDS1I i4 ATT7 i4 PSb "4c:! PSe MA9 MAB 16. is. P3b VAS P3e P3e LDSil LD4-2 LD4-i 15. is. " b PSe RCKA "!2c::.psa is. PSa PSb P3b 16. is. " b P6e 17. P3a MU4 i7. P3b WI i7. P3e CDCO i7. 1a. P3a MU5 1a. P3b 1a. i9. P3e CDC1 P3b CASI RASI P6b 17-c:::1 P6b 1a. PSb P3b UDSI 20. P3b MA5 21. P3b P3b MA4 MA3 22. 23. P3e 2~psa P3b MA2 24 P3e 24c:!PSa P3b 25. 2S. P3e "bp3a VDD7_ VDDS 19. 20. U7 21. P3a U9 A9 22. 23. P3a A11 24 P3a 25. AU AiS 26. 2S. P3a U3 Ai!'! A2 27. P3a Ai A4 AS 2a. 29. P3a P3a A3 A!5 Aa 30. P3a A7 30. VOD4 31. 32. P3a VOD2 31. P3a VDD3 32. VDD!5 m o :::~~~ :::~~~ :::!~~ :::!~~ P3a PSa PSa 1a_ PSa CATO P3e 1~P6a ~T1 P3e 2~PSa CAT2 P3e DBEN1 P3e DIBP2 21 22_ 19. 20. P6a PSa 2~PSb 28. 27. P3b MA1 MAO P3e 2bPSa DTAC2I28_ PSa P3b MAS 27. P3e 2a. P3b 29. P3b MA7 CLK2i 2a. 29. P3b HSYNC 30. P3b -12V P3b VDDi 31. 32. CLK1 "b P6e "b P6e 2~ P6e 2 b P6e HSYNCI 2bpSb 24 P6b 2bpSb 2 b P6e 23. P6c 24c:! P6c 2 b P6c 2bp6b 2 b P6c 2~P6a 2~PSb 2~ P6c P3e 2bPSa 2bp6b 2 b P6c P3e 2~PSa 2~P6b 2~ PSc P3e 3~PSa 3~P6b 3~ P6c P3e 3bP6a 31. PSb 3 b P6c 32. P6b 3 b P6c P3e 3~PSa ISIOI IASIOI 2 1~ P6e PSb PSb 2bpSb 3 4: P1b 5 P1b t p1b P1b DATE ::P1b P1b NAME 21.3.86 S.E./J.B. 3.6.86 S.E. 15.9.86 S.E. :t:~: UI C\J o~________________________________________~________________~~__________________~____________________________~ A PSe OREQOI GNO I------~ P3a 9_ P3a MRO 24 (0 PSb D7 U2 m .c PSa OWN1I 4 GBPENI 7. 22. 23. m 5_ PSe RUNI OMAEN1' IRBil A20 AiO o P3e ARENI PSb ~ o 4 4 P6e 3. PSe P3b ua m PSa AM2 PSb 1 2_ P3b C\J .JJ 4 CAT3 AM4 R/Wi 6. 7. o C\J C\J P3e ABENI PSb MA16_ 20-c:::l P3a 21. P3a ~ P3e 2. 3. P3a GND I m m S. 7. 1. AMO AMi P3a VTDIR (0 5. COACKI P3e 1 PSa 2_ PSa 3. PSa _B. Al:lt.I~""4 3 4 IAC1BI CGENI CRENI 09 BPAENI t- 010 P3e 5. GBOEN ..... 2. 3. MU7 GNO I SMCYC E 1. 012 DU 5_ SPREN m 013 MA1B OGTEOI ZCLi C\J P3b P3b 3. P3b 4 P3b VPRZ 10 10 P3a P3a 3. P3a 4 P3a R/WI 2 1 2_ OBCLK MAi9 LOSI a FORCE COMPUTERS ________________ REV. 3 SYS68K/AGC-1A SHEET B FROM ~ ________________________~______ ~ 9 SHEETS A c B D 1 1 VEE4 .....~I-I--I----. fi GND 2 I Jii 74FOB GND J12 74LS04 Ji3 74LS74 ~ ~lr; r"r"r"T" I Ji4 Ji5 J20 J26 J4i J6i J63 J76 74LS32 74FOB 74LS112 74F02 J27 74FOB J28 J32 74F04 74LS21 J34 J35 J38 J79 J80 J91 74LS112 74LSOB 2 7406 III III 16 If) J40 o ru 74F32 E ~ 8 VEE _--""1 ~ P2b~ GND P2b P2b P2b m o ru ru 10105 VEE4 10104 74F74 , 74F74 VEE4 ----lllfVEE 8 VEE _--""1 3 P3c~~~~--~ Pia P Pia i a . Pia Pia GND Pib Pib Pic (() GND J92 J58 ~56 VEEi 3 79L05 2 in 1=--'" ---+--~out GND J57 74F74 GND J96 74F86 J97 74F04 3_-=l3 7 9L 0 5 =2_~ ..._VE~E.... out 1n'GND 1 GND CD CD 74F74 Piac:::P............ 3 m m +' 74LS125 74F04 J78 10125 VEE4 CD or! 74FOB J77 U I&. :::J 1 +T..; GND GND " J59 4 DATE o NAME REV. 3 21 . 3 . 86 S . E . / J . B. Pibc::P'i • SBYVME GND GND 3.6.86 S. E. 15.9.86 S.E. SYS68K/AGC-1A SHEET 9 m GNDE::::J 1 FORCE .c (J) POWER FROM ru COMPUTERS O~______________________________________~______________________________________~__________________________~________________~______________________~~____~ 9 SHEETS (() A 8 Date 014sh1 Time 20.09.1986 . g > I\) IS 4 'Q11l Q2 W Q3 '-.I Q4 ..... 6~fd-I 01 02 03 04 .co Gl z o 12J VOU 0 rn V }I 0 I V v n v V 0 Z -l v JJ t:!"UI W I Z 0 (l) c en ~ 0 X ..... '1J 0 C JJ -4 n PI PI JJ U1 I • 0:1 -I 01 ITI 9 1 1 ~ !~J + OJ UI ~ J eL ~ "T1 :0 en a3: m m --I en :::r: ,3 :4 0 .0 S 0 0 0 7 :8 III Gl Z 0 < g~ =-r-' 03 ~ 02 ~ 01 L8 DB 07 14 OS 13 05 BO 1 eL Ii::: o 3 4 10 B6 1/ vee '"- .co !~~ GNO .co GNO Gl z Gl z < 0 0 ::tI o ITI III GNO ~O Gl z0 n O~ 01 O! ~ I\) III UI ::tI 0 '" Gl z '>" I\) M » 9 Q4 Q3 r Q2 (f) Q1 W QB Q7 '-.I QS ~ Q5 c.. GNO .co !:o~ +~ Gl z UI < EN~ 1 eL v 0,' 0: Oi 0 01 071:-~ ;;_AM 01 O! .. 10 ve~1 c.. ~;~ + 0 UI < 0 ::tI 0 '" 0 z fdrr- vee ~ !~J + U) UI < 9 1 1 1 » eL ~ vee ~ EN Q4 Q3 r Q2 (f) Q1 W QB Q7 '-.I QS ~ Q5 GNO ~O Gl z 0 04 7 03 4 02 ~ 01 18 DB 1 07 4 06 1;:s 05 ~ ::tI 0 0 > ITI III '" III '" ~ VOBB J89 19[J 91 192 193 194 90 VOU 2 EN U eL Q1 11 01 4 Q2 W 02 Q3 '-.I 03 Q4 ~ 04 1 Q5 05 4 QS OS 1 Q7 07 QB DB vee !:J m » v 9 Q4 Q3 r Q2 (f) 1 Q1 W QB Q7 '-.I Q6 ~ Q5 '"- 10 ~ +W + UI < UI < I ~m I ~I IIlI -- + < Z 0 tt vee Vl."c ve~1 fD Gl 2 Q1 11 01 3 4 Q2 W 02 ,;:I Q3 '-.I 03 4 Q4 04 Q5 ~ 05 1 QS OS1 07 1 1 Q7 QB DB VOU :2 g~ft=-1 0: Oi O' 01 .co !:o 0 ITI v GNO + < ~ » J frti ENU 9 Q4 Q3 r Q2 (f) Q1 QB W Q7 '-.I QS ~ Q5 UI EN < » ::tI EN;:fi UI Z vee '"> ~~ vee Ole.... '" fa .co !:o GNO ~ < EN G) ~ ~ ~ ~ eL ~ ;3 UI 0 0 2 Q1 11 01 4 Q2 W 02 Q3 '-.I 03 Q4 ~ 04 1 1 Q5 05 1 1 QS OS1 is Q7 07 1 19 QB DB i~o + ~ Z 9 Q4 Q3r Q2 (f) Q1 W QB Q7 '-.I QS ~ Q5 Q1 11 01 4 Q2 W 02 Q3 '-.I 03 1:1 YU'&'w -c; Q4 ~ 04 .3 05 14 }II [6 10 Q5 OS .7 VI 7 16 QS 07 15 VI [5 18 Q7 QB DB "» m en .i::: 4 ~ vee Gl A :::r: VOU ';:S VL" 03 4 (f) 02 W 01 1 ~~I g~ 11 ..... 06 1 ~ 05 Z EN V072 g~re----' r 0 '" > I *0 !:J < ::tI 4L » GNO UI ITI 1° c.. m m n S vee ::tI Q4 ~ 04 7 Q3 03 4 Q2 (f) 0 ::I Q1 11:1 QB W DB Q7 '-.I 07 14 QS ~ OS 1;:s Q5 05 ~o Gl vee '"- ITI en -< en > --I ~-""""""-"'"""'IQB < GNO < eL r 1r----.~~41~Q4 W 1 g~ ........---.~~~1E Ir----.~~~ Q7 *0 !:J ~ 01 vee en z m >3: 0:1 > --I > '-.I 9 Q4 Q3 Q2 1 Q1 1 g~ 1 12 Q6 Q5 ENI.fI . > 1010 en 0 ........---.~r'i4r-iit Q3 ru EN Gl n 11 > ~ .co !~ ~ ~ 0 9 0 1 , Q1 t:!"UI ~ EN~ z 0 ;/ 68 ........ 1r----.~'*-~6 Q2 W J ENfrl-l g~ ::I 02 ~ 03 8 04 13 g~ 14 1 07 1B DB 0 21Q1 11 g~ Q2 W 02 4 Q3 '-.I 03 Q4 ~ 04 1 Q5 05 OS1 VDITISIQS 071 VDI891g~ DB GNO Ig~ GNO I~ I~ VDU V064 '"-ru 12 z 0 < 6~l!!J 04 1:1 03 4 02 ;:s 01 ill DB 07 i~ 06 L::I 05 ~ ~~ vee Gl EN~ ~o Gl r .co GNO eL 1 2 Q1 11 01 Q2 W 02 4 Q3 '-.I 03 1 Q4 ~ 04 1 Q5 05 1 1 QS OS1 Q7 07 QB DB GNO 0 » 9 Q4 Q3 r Q2 (f) Q1 W QB Q7 '-.I Q6 ~ Q5 '"-ru rrn < H 1 06 ~ 07 1 DB vee ~ I~ I~ Q5~05 Q6 Q7 QB IGNO III I 165: ffiffi: 38 III ~ ~ VOl-BUS VlOEO-MEMORY-OATA-BUS m < --I ~ III I\) ~ I A B I C D ID cc c RCKA1 RCKA1 GND;r. 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EC~;;tJc.Jkl-.Iu,IJ..,~ ~~~~ J34 ~~ Z...I"'(lJN~CD""1D1O UJucccccccc ALS374 co RCKC Q) E ~~~~ J32 Z...I"'(lJN~CD""1D1O UJucccccccc > ~ ~GND L..-COl~C!I~C!I~C!I~C!I~C!I!C!I!iC!l~C!I~....~---" ~ ·n I- GND1::/m",.., RCKA3 RCKA3 ALS374 J36 - g~5V > RCKC RCKC Ul :J 31 3 m g~5V I > F374 H o > F374 (0 CD OJ ~ I-- OJ o VIDEO-CONTROL-BUS Q) .j.J 10 4 DATE o 15.9.86 ru .c UJ ~ ~~ ____________________ ~A __________________ ~I __________________ ~B~ __________________ ~ ____________________________ ~ NAME S.E. J.8. FORCE COMPUTERS ________________ REV. 1 SYS68K/AGC-1B SHEET 2 DATA LATCHES 2 ~ ________________________ FROM ______ 11SHEETS ~ ~ I _A J39 1-·' if lS ~ ;--, VTD DIR if ;--, B ......., 1 GND st~O A ~ J!itl lEIS DIR GND G~O l20 +5V GND _l.~0 GND A GND _l.~0 l20 +5V GND m ~ .. - ~ rs A VTD DIR A r--. .. vee VTDIR DIR if _l.~0 GND ~ VTD: DIR if _l.~0 aND ~ ,....., '--' ..... ~ ....... vee 2 l20 +5V J53 ALS1245 645 TESI VTD: j::; DIR if .- f---, ;--., I"'""" ......., r--. r--. '£TEBL '---' ....., ......., B GND 'BBB 1 r- .- f--, ;--, ......., B 1---1 ....., l20 +5V H 17 DIR I"'""" A ....... vee II vee if '--' !--1 r--. A J51 VTE51 ~ ~ ,...... ~ ALS1245 645 ;-, !--'1 B ~ ;---; 1:3 r--. ....., l20 +5V '---' J46 ......., B B A VTESI ALS1245 645 ~IW ....., ,....., A .- f---, G*~O ~20 +I5V ;--, GND ~ ir ;--., I"'""" ......., GND l20 +I5V r--1 r--. (fJ ~.E91 vee if R ......., J44 J49 VTE41 DIR ~ ALS1245 645 r-, ....., ;--., I"'""" ......., B G*~O ALS1245 645 I !I. h GND !--1 !--1 B II vee if B r-1 J47 DIR ,....., ,....., ;--, ALS1245/645 VTD if VTD 'BBEI ll:O +I5V 1:3 r--. ....., 2 DIR ......., 17\J 17 !I. A vee ~ B VTE21 f--, ......., J42 VTD ALS1245 645 ;--, ALS1245 645 ~r/ ....., ;--, A ir '-- vee if DIR ....., J40 VTD R VTC !--1 1---1 17 ,tltlCS ALS1245 645 - VTElI ~ h B J45 ALS1245 645 ......, ,....., ,....., ~ A h 0 J43 ALS1245 645 'TEOI I e J41 ALS1245 645 VTDIR 1 B A ~ ,...... '--' ....... r--. 17 'tIt1t1 r- t--' r--. B VTE71 (0 ~ GNIl_ 110 .. VTD.CR DIR JSH if 197 Ii-;::] m m A B VTEel VTD .GND 0 N ......, !--1 h H A VTC B A J54 ......, B vee GND G~O --- vee GND ~l:O VTEEI VTC FI DIR ir ;--, ~ f--, ......., ......., ~ ....., B A ......., ....., S .- vee GND '---' ~ ,...... '--' DATE 15.9.86 I B I vee G*~O ~20 +I5V VIDEO-DATA-INTERFACE-BUS VIDEO-CONTROL-BUS VTEFI r- G*~O ~l:0 +I5V +5V VIDEO-MEMORY-DATA-BUS A . ALS1245 645 'BBEI q- ~ ir +5V ,....., J:. CD n DIR H Q) C'l Giro +5V ;--, r--. .. 4 Giro ALS 1245. 645 ~_TEDI I"'""" G*~O ~::V 0 IU if IG~j:) V( il: O 110 'BBEI m 0 DIR f--, ;--, IGND V( 1l:0 110 J52 ALS1245 645 r--. ~ +' +5V J50 ALS1245 645 S (0 Giro +5V J48 E t- END VC l:0 110 120 Giro Q) 'M vc:~ NAME S.E. J,B FORCE COMPUTERS REV. 1 SYS68K/AGC-1B SHEET 3 DRIVER FROM 11SHEETS en :J m I 1 J55 WI +5V 2 I 1 PFII 4 Clr o II: r o o I o UJ o BPA 1A .ALATC.H 6. 5 --: -; J56 H -; RCKC 2. VAS 2A GND GNb J56 1 2G AMUX ~ 2Y GBPENI AI_A ;H ~~ MA16 ..MAi7 MA1B MA19 ~~ :! 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I!::':" 1 I"';; 1 ~ol+5V1lD +5V Y3 Y2 Y1 2 74F138 yA 112 9 ~: :~ vee G*~o ~20 1 1 ~: :: J71 74F157 I :::: A J70 74F373 - 3 J60 J61 AS646 AS646 J76 3 J77 74F373 J78 74F245 74F245 ID m m • ':'':' ~ !':' ':'- m o ~':' • 1 r::'F 12: ~!f ru ~i 11 fI, ~t +l m o GND G~D2 II mmr- IGND 2 Gt +5V !~ '':' .... !':' !':' .. _K ~t mEN :: .~ fI'/W vee Ci vee [:VGt:ib r::t~ ~ GBP AI r---r---- ,,~ ~!~ 9[~1£ C;;:; ......,... I& ...~~~ _, E 4 r ~~!: _K 9[~ 1£2 Q) ,,~ IJ:4 I':'':' ,,~ rrr- ~, !! -:'"' !':' ~ 11 1 ~. !! Q8 1! Q7 Q6 Q5 Q4 Q3 Q2 Q1 GND '!O~+5V1l G DIR G DIR B A H <--" !- B A V Ivee vee GND 20~ +5V~:~ DATE 15.6.B6 +5V .N ;-' vee [:VGNb I GND ~O~ +5V~:*D NAME REV. S.E. J.B. 1 SYS6BK/AGC-1B DATA-BUS ~ .c (I) ~ ,I ~~ __________________ ~A~ ______________ ~ ________________ ~B __________________ ~ __________________________ FORCE COMPUTERS ______________ ~~ GRAPHIC-VIDEO-RAM ~ INTERFACE ______________________ SHEET 4 FROM ______ 11SHEETS ~ ~ A I B J65 J66 PAL20LB 1 OEF .RFSHE/ =81; 1 .GIIID f-- lEN _£2 GND f4 +5V 3 MGATE ..... 1 1 1 4 l::l C\J G{2 t 5M[ :AS, vcr. 124 I:. A4 11 2G 9 U4 U::I Ui:! 11 ..ETA3 I:. Ail! E. -A1 E-AI 1::1 10 2A 17 ::I m ~ lB 1 I:! 14 12 lY 9 7 2Y J~o UJ GND -A~ :::I ::I lA 11B IU' lY 114 11i1! WB W7 _wti 2G 9 W4 W::I Wi:! wl 2A I 0 2Y ::I wo GND vee ro _l~o +5V 2G 2A I' 0 2Y 1 Iif ETA7 E. -AI:! GND vee GND J74 ~~D ETA7 EIAI:! E Ao E'rA4 M61 MI:!i:! MI:!::I Mti4 ReKAi RCKA2 H[;KA::I A[;KA4 E:TA3 t=.rA2 ErA1 ErAC 1 2 Iif 4 I:! lA 11B 11:! lY 14 12 B 18 11 2G 1::1 1:::1 2A 17 G.N D TB 7 rl:! r~ T4 ::I ri:! ::I l1. IG ..E.TA3 I:. Ail! E.-A1 ..t:-AI 2lf lA 2A VB V7 VI:! 9 V4 V::I Vi:! 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FORCE COMPUTERS REV. 1 SYS6BK/AGC-1B GRAPHIC-VIDEa-RAM INTERFACE SHEET 5 FROM 11 SHEETS I A J79 VII~ V02 VII;:' 1 ~ 1 RASe r;ASI 1 1 ~we a~ ~ ,- ... MI!U !... IGND VD4 VDl:! V06 VI A A~ A~ 1 ~ LRAse r;ASI LWC A, ':'~ ~: .., 1 ve( GND A 1 ':~ A VDS VDS VOl 1 vu~~ ~ LRAse r;ASI ':~ ~~" 1 LW~ ~I!i~ .6. ~~.~~ A~ VD12 1 ~l~ :\: ... .., Y014 1 VD~l:! ~ LRAse r;ASI ~~ -;: it 1 LW~ CO! !... GI~D f~J:v :f~l:5V S4 HM50465-12 ~ ... ~I!i~ vee GND ~~ l~ VD~;:! A~ !... vee HM50465-12 1B Gt!D_ A 1 ':'~ ':'~ 1 ~, ... J vee ~ +5V ",,92 HM50465-12 /' A' HM50465-12 I-- ...~i.- VD~ V02 VD;:' 1 ~ 11=1 1461 h- ..... GI~D 1B 2 GirS '- A ':~ A: A A~ . ~:, ve( .~ e 1 +5V o - ~Q,1 A 1 'A ~~ A'... ':~ ~ 2RAse 1 11 3 Ul ..,. Ul N -.... ;aw. ro- GND ~ . ~:, VD32 VD;:!;:! Y034 11 :i vu;:,:: 2RAS~ CASU 2Wt,; Ml!i2 Ul m m - 11 ~rS 0 VD36 ~:I > A~ ~ ~~ GND B eCc o 1 ~ 2RAse 1 ~3 ."'" -.... GND YCC /1 :/i! Q! JOs ~ ~RAS~ CAS9 1 ~w~ ~:" . :J vee ~ t+5V .. A 1 ':~ A' . ':~ ~:" .. In I Ul Ul w -~I: ~:.., 1 :i 2RA's~ CAl:;U 2WC Ml!iil ve( 1 1ii. ."'..." GND ~:5V B GCc V014 1 :\~ VD~O ~ '- .......... '---i « I VD40 VD41 V042 VD4;:! a w 0 H > " ~£~ ~ Ise i3 1 vee - J :J In I Ul Ul it +5V 9 !/~~ ~ Ul vce .6. CO: -;: i.- CO! w 0 « VD44 VI 141:1 V046 VD47 Gi~_ t+5V VD40 VI 141 _V042 VU4;:' ':~ -;. :/g~ > :i 2RAS~ A ':~ CASU ~:" Ml!i2 2W~ . vee 1 ~i~ ...."'"- - GND ~:5V B GCc ~ .6. .. -; 1, Ml!i2 In I Ul Ul a: 0 « I a W 0 -;: > II.- 2 w A' I- 2W~ H I-- GND J"CC :itl +5V co: Ul :J I~ i~ ~ :A~;:s ~ .6. vee 2RASO Gtr94t+5V "" HM50465-12 ~, GI~D ~ J '- 90 ~ Q,1 GIIIDVCl: l:itl -;: HM50465-12 H ~ A -; !or "" a: W 0 A~ ':': 1, Gir9':Jt+5V a .. - .., ~. ","'- .6. IB I i1 a~ • ~1 il:l CO! HM50465-12 0 ~~ VD~;:! "~ GirDS' a: VD12 Ii ..~ liB HM50465-12 VD36 i:ii..,.... A~ GIIiD B GK .6. .- Ml!i1 Ul HM50465-12 « ~ii ~, ...'- • 1 vu~~ ~ 1B a: H ~ "'h-" w W 0 ~~ .. l~ ..A. GI~D HM50465-12 ::I ~ Ml!i1 .f~ J:v '-' 2 ~ 1 1 In I Ul Ul a VDS VDS V01 1 A 1 :J I VD32 VD;:!;:! V034 VD;:!O Ul VD4 VDl:! V06 VI " A Ii HM50465-12 m J91 HM50465-12 . !... HM50465-12 VDO ~ ~ ... ~1!i1 ~~ol:v - Ii 0 JS7 HM50465-12 A Ii I c JS3 HM50465-12 VDO I B HM50465-12 3 VD44 VII4!i Y046 VD47 1 ':'~ :\: 'Q! 1 ~ 2RAS~ :AS:L:i ..~ -;: 2W~ ':'! .11 .., Ml!i2 vce :i ~i~ .. "'" ,- II.- laND ~:5V , B GCc A 1 ':~ A' -;: ~. vee ~:5V I-- VIDEO-CONTROL-BUS OJ .&J co VIDEO-DATA-BUS 4 DATE o 15.9.86 Ul .c. ..,.OJ ~ o A I B I NAME S.E. J.B. FORCE COMPUTERS REV. 1 SYS68K/AGC-1B SHEET 6 GRAPHIC-VIDEa-RAM FROM 11SHEETS I A VII1tS ViliS 1 1 ~ M51 ~8~ V020 VI 121 VD22 ...Ci~ ~: .Ihr BI~O :us ~r9 1 1 VUi:!;:S lRASIl ..~ CAS2 ~:, lW,," MHI . vee VDtS VD17 ~~8~ VUlts VlllS 1 1RAS1 ;AS1' lWO 1 M51 4~ ,.. w-h- A t VD20 ':~ VD22 2 A V112;:! 1 1 lRASI . CAS1' 1 lW~ en MHI VD48 VD49 (Y) (Y) VllO~ VIl51 1 .SC r-~ to i4 i'-----i f'--' o ~~1~~4 ;' ..SII/O (Y) ~ 1ts 1 .6 ':'! .. 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J" :;%g!:Q.4 ., t ':': -;; !or vee A VD~B ,- .. e- ~ -;: 1 A, ~ A :1 i4 ':'~ A ;~~~ .. 1 ~SC ~, Vll5 vee .6 ':'! ., HM50465-12 H ':''!: -;! ~ Ii ~~105 J:ov en en W 0 ~ ~:U 1 IGND HM50465-12 ~ 1 lRASI :AS1' lWI MHI J102 ,t 1 :J vee ~l~ J::.. ....* .., - s~B +SV ~! , A ~~ ~~ "" 104 en ':'! HM50465-12 HM50465-12 vue:, .- .. GND ~ .. G~O ':'! vee '- 8 11B 1 ..'!: -;! .6 ':'! Vll53 VU04 Vll50 - s- J:sv ~U • ili•,GND HM50465-12 HM50465-12 E orf w II 0 H : , ':'~ tt 1 1"1 MHI ~~101 J~ en en W 0 ~: sir9, Ql t vee 1 lHAS,," GAS2 ~ BND GND I HM50465-12 . .. 1 VD27 ~'!: ~ '=- m ~r9' ~+SV ~~ ':~ .6 VI 121 -; vee V,Ui:!O Vll2H HM50465-12 :J GII/O 11t1 V024 1 -;; ~; J107 J103 J100 t+sv I'. I"S G~B i:I HM50465-12 - 1 ~8! :Q.4 ~: 0 HM50465-12 HM50465-12 A It I e J99 J95 HM50465-12 VDtS VI 117 I B ~;Is Y06Q :!:'g~ vutn VllH2 t:: VD53 ':'" .it:~ ~~ .." 1 ~SI AS12 tii: 1 ...-.- :!:'g~ S~B !:SV 3 Ii A' .:; J:' ~; -- ., GNO vee A~ ':''!: A~ vee - !:SV VIDEO-CONTROL-BUS VIDEO-DATA-BUS Ql ~ m 4 DATE o 15.9.B6 " .c UJ 'if ~ o A I B I NAME S.E. J.B. FORCE COMPUTERS REV. 1 SYS68K/AGC-1B SHEET 7 GRAPHIC-VIDEO-RAM FROM 11SHEETS I A HM50465-12 1 .5C it! 1 1 ~ I"---' ~'g~ ~J~~ - ~ A A -;: GI~O vce - I"---' GI~D .l. ~ 116 GirD +5V .~1::1 -.1 1 1;:1 ~~U ;' g,4 ,GND 116 Gtto CO" VOS7 VDSti VDSS - IA5C .-'. ~~ ~~ ;1 g,4 ,-- ,~I ~~ vce J ~ +5V 1 A A~ f=- GI~D 16 1 Gi!D b- ,- I"---' GND 11tf ':~ 1 :~ vce J ~~~ ; i4 ,.... ':': -- IGND ~ 16 Gtto +5V 11 VD7S _Y[177 V[178 V[ 's 1 lAse 155 11 i3 ~. 1 ;~8~ .' 5!=- ~~ ~ eND J.:I IUS +5V 11 A A~ 1a~ ur. vce A. A~ 1 .... vce J:I Glo! +5V ,-124 \J120 HM50465-12 I 0 vn1nn 0 VOigt VLll' VD1' H 1 VDSS _Y097 VOS8 VDSS 11 1 .51 il0 (0 m m 11 ~~~~ :!:J~4 ,- - vce GI~D .~ +5V ~ 11t1 - o :I en :J m I en en A; HM50465-12 V0100 _VD1gt VOi' VDl -;: 1 1 _4RA51 4W[ M54 ~, *~8~ ia~ vce « I 0 W 0 V010, V010!:l VLll01:l _YIJ.1 > A! ~:5V ~~~ ~4 4R ,5C ;A 4W M5 V[ J vce ~ lAS 1 A; ,~1;:1 ~, 13 en m I en en J:I G~O +5V 11tf > ;'g~ V Y01'O l i VLlll VDll i~ _4RA5C H ,.... - ~ I,;A~I 4Wl M54 ,GI~D J" 11t1 ':~ 1 ~ GND vce IGND ,- ~:5V VO. _V01' VOU VDll tf Gfo 1 1 4RAs1 ;A~lt! ;>!f- A +5V A 11 ~~ ~ UJ II 0 « I 0 W 0 H ~~ A~ 2 I-- > vce J:I +5V HM50465-12 ':~8~ !~ ~~ A' ~, .- J:I en m I en en :J '- 126 A 11 ,51 ilt! vce Gi!o +5V HM50465-12 V0104 Y010lJ VLll' VD1' ~~ A~ '- 125 ~122 A 1 A~ 1:" HM50465-12 « ~~ 11 A Gi!b UJ A vce ;>!f- ,- ,GI~O II 0 I 0 W 0 A 11 A ~~~~ :/~4 .... :J vce IGND 16 1 's -i .,... - 1 VLf/tf -.:, ;>!f- !!.... G~8 A -i HM50465-12 ~ ~- V07S _Y[177 A 11 jo121v II 0 H -;: -,- ;>!f- 11tf UJ 1 I='~4 IGND HM50465-12 A~l 1 I:~~~ ,=' " ,.... '- 118 .... tf Gfo ~~ vce 1 1 ,51 il;:1 A! Gi!o I,;A~lt! GND ;1 ....- ~, ;>!f- f=- A ", ~~U g,4 ~ il HM50465-12 3 ~~ A .5C V072 V[173 VL '4 V[ '0 i1 HM50465-12 « UJ .:' A :011i UJ II 0 '- 114 OJ ;>!f- ,- ~ en :J m I en en > ~ 14 ;~~~ '~4 .51 il;:1 HM50465-12 voss VOSS V05S VLII' V[l71 A 1 ~113 m 1 1 ,50 HM50465-12 ~ !...- 2 ~ HM50465-12 I-- IA51 I- V072 V[173 VLII4 V[ '0 11 '- 116 HM50465-12 VOS4 V055 VU!:)!:) VDlS: E ·n ,- .... ~ A '- 112 - ~ i5 J123 HM50465-12 A .se ,-f=- ,16 Giro .:' ~~~~ ~~ ~4 VOSS V05S V[17' V[l71 D J119 HM50465-12 A 1 I c J115 J111 VOS4 V05fi VU!:)!:) VDf:r 1 B 4Wl M54 ~: vce ~~~~ ~J~4 ;>!f- ,- .... - GNO A A~ 3 11 ~~ ~. A' A A~ vce I-- G~8 ~:5V ~:5V VIDEO-CONTROL-BUS VIDEO-DATA-BUS OJ .jJ ro 4 DATE o 15.9.86 m 1: III <;f ~ o A I B I NAME S.E. J.B. FORCE COMPUTERS REV. 1 SYS6BK/AGC-1B SHEET B GRAPHIC-VIDEO-RAM FROM 11SHEETS I A J127 VDao VUfl1 VDB3 :;~8~ 1 ,-~4 ;:!HA5( :ASEi 3W(l Mti;:! ~~ = ISND fI S*D ~ ;~ ';~ ~~ ';: ';~ ... ~ ~; ..., 1 ;:IHA::;( :ASEi 3WC MEi;:! 1 ;:!AASl CAS14 ;:IW," MEi3 1 1 ~~~ ~~ ~ ~- ISND S~B 2 ~~ ~. - 4HAS(] CASB 4WI,; MEi4 1 1~ ~ vee 3 I- VDU V[I11 .V01l>4 VDUl!i 0 1 1 4AAS1 CAS15 ([) 4W~ m m 1 ~~8~ i44 ~ ~ .- MEi4 ~ SND - fI S*D 3AA51.: CAS5 3W1 MEi3 ~. « VDU6 VU1l1 VOU VDU 1 4AAS(] .CASfi 4WC MEi4 1 ~~ lAs .- B S*D J:5V ~~ A~ VU~l :AS14 "Wi ':~ ~~ A~ ':~ 4W~ A! 1!~8~ 44 1 ~ 1 4AASl CAS15 ~~ 1 .- MEi4 1 ~~ A~ m SND (f) (f) S~B w A~ vee SND fI S*D l:5V ~~ ':~ 3AAS(] CAse :JW1 « I 0 W 0 VD12C VU1~ V012: VLI1i:!: > .[ 1 1 :i~~ E.£~ ~~ ~ .- MEi4 ~ vee SND S~B J:5V V[I12 VOl v Iii:!: ~~ A~ 1 IiIAAS1 :AS15 IiIW1 I4Ei4 ~~ ':~ ~- vee 1 :~~~ ia~ Ii l:5V UCo VD92 VDS3 VOS4 ViUSO :'3~ 1 ;~l~ 1 !!!- 1~ 151 i14 ~~ Ii' - ,- i=- ~- (f) vee :J m SI~D (f) (f) SirD .1B I Ii A~ ~, A~ 0 « VD124 Y012l!i VD1: 1 1 V,'-!12' 4RA~(l CASB 4W1 M54 > A.. !'~~ 1 ~~ A. J vee ~ +5V Ii co: i=ICo SI~D .1f1 J:5V r-- 1 ... ~ Ii ...~~ (f) J vee ~ +5V Ii A~ 11 A: - . !'g.4 11 !!!- vee Ii A~ HM50465-12 H ~! Ii \.141 w [[ I 0 W 0 11 co: \,.140 11 J:5V 1 Ii A~ HM50465-12 A: Ii ~ ~~ :J m I 2 (f) (f) w [[ 0 « I 0 W 0 H r-- > J:I vee sirD +5V \.142 HM50465-12 VD124 11 VO~_ VD1: VII12 A~ ~: .- B S*D I!=- SirD A~ ~~ SND ~ J:5V A~ ~.- !l?'t lt1 ~ I!=- ~~~~ ~i~ SI~D HM50465-12 vn.,;" 11 vee J138 1 1 1 MJ:i~_ A_ HM50465-12 0 ~- Ii ~ ~~ J137 [[ H ':~ ~ .- I J:5V i~ l!=- :J != ~- 1 ~t:!3. (f) HM50465-12 VDU6 VLI1. .VOll VOU 1 ~AAS1 ~ vee VD92 i1 ~~ J136 J134 1 .- Ii HM50465-12 HM50465-12 1 Ii ~ B S*D VDBS VUflS VOSC ... ia~ ~ J:5V Ii :~~~ SND != ISND 1 vee HM50465-12 - Ii 1 1 VU~l J133 [[ HM50465-12 E ·n m o S~fI J130 Q) ~ ISND > ':~ ~~ ~- w H ...~ SND S~B ..... A" ':'~ ~ (f) (f) I 0 W 0 ~~ ~ I 1 ... 1 m ~~ != 1 1 :J J:5V .- ;:!AASl .CAS14 ;:IWI,; MEi3 (f) vee VDas VUflS VOSC A 1 J132 VDS4 V,UtlO YDfl5 VOB7 J139 HM50465-12 HM50465-12 ... ~ HM50465-12 1 1 .- != S~fI A 1 Ii '!!!!i'"'~ J+5V J129 VDU VU11 V0114 VLlllC :Q.4 ISND J128 VDBO V'-!fl1 YOfl2 VUtl;:l :;~8~ 1 vee HM50465-12 r-- 1 D J135 HM50465-12 A 1 I e J131 HM50465-12 ~Ofl~ I a f! 1 4RASl I,;Atilti 4W1 M54 ~- vee 11 !~~~ t~ :~~ ~~ ~- I!=UCo SND S~B l:5V 3 !1 Ii ArCO! :~ vee - l:5V VIDEO-CONTROL-BUS Q) .jJ m VIDEO-DATA-BUS 4 DATE o 15.9.86 m c. Ul '<;f ..... o A I a I NAME S.E. J.B. FORCE COMPUTERS REV. 1 SYS6BK/AGC-1B SHEET GRAPHIC-VIDEO-RAM 9 FROM 11SHEETS A e B J3 J1 74F161 74F138 1 ZPR1 A 1 B ii! e 3 ,T.!. ~~ ~~ Y3 ... t 8 Gto e~~ :::: ~ _.11 1:1 ~6~ GND eL~------------------------~5~~~.~~------~ 5 S::»A ~A D gS ENP 1 01 ---"",",,~p'----'K::I~~~ as If ZCl 5~t ~N ~ r.:l\oIn J4RD +5V • LOt1t1 ~PR1 . In 6 +5V VOl-BUS J2 . 74F138 Y7 ~ ~! 2 i Y3 ~A 3 t :II 1:1 ~6~ B Gto 74F374 ....&. 4j GND • ~~~ GND J38 2 GND .K I: ;~ :::~ ~::: ~"! +5V :::::: ..:":' (0 (Y) 9~ eLK21 ~ -- 1 c:O!+5v Gl speLK B D~ vee GND J56 (Y) (\J 14 QB i Q7 Q6 Q5 Q4 Q3 Q2 Q1 :::::: 6 2 n 14F04 VIDEO-CONTROL-BUS Q) .,..E r 3 3 J4 J5 74F244 (0 m m ':IA~l'l\oIn n --' IG 1A m a 11B 111:1 1Y 114 n RASI 2G 9 2A / !:i 2Y G*~O ~ ~ WENi ii!RA51 3RA51 WI 4RA51 ::I !~O +5V r-' 1RAS1 GND vee 4 WENO ~ 11ii! AASENi (\J 74F244 II IU III IG 1A 1Y 2G 2A 2Y 11:1 18 14 1WO 2WO ::IWO 1ii! 4WO 9 1W1 !:i ii!W1 3W1 4W1 ::I GND vee JNt G*~O ~ +5V !20 +5V II U II IIIN2 +5V ~ DATE 15.9.86 NAME S.E. J.B. FORCE COMPUTERS A B REV. 1 SYS68K/AGC-1B SHEET 10 ACRTC INTERFACE FROM 11SHEETS I A I B I e D .. > 10 + i. (!) 1 1 .. > 10 + i. (!) - .. > 10 + i. (!) 2 J55 P1. PI • • P1. P1. P1. P1b P1b P1c 10 U) GND P2b~f ~5 , ~ - m (I) • GND • +5V E ~5~d • +5V I- 3 P1.~1 • -12V P1cc::P'1 • +12V Pibc::P'1 • +5VSTD ~ P1c CD .... ~ ~O4 J56 74F04 - GND vee r+5V 4 Gt: ~~~~I + ~ J56 74F74 2 GND GtD' vee r:v - J56 V 74F04 3 10 m m ~ m Pi.~ - Pi. 0 Pib~ ~ P1b ru .fJ 10 0 ~ 4 P1b P1b:!=J P1b BG2IN/ BG20UT/ Pib~ BG3IN/ BG30UT/ P1b - BGOIN/ BGOOUT/ BG1IN/ BG10UT/ P1b~ CD IACKIN/ IACKOUT/ DATE 15.9.B6 ~ .c OJ ~ ~ 0 A I B I NAME S.E. J.B. FORCE COMPUTERS REV. 1 SYS68K/AGC-18 CAPACTORS AND OPEN GATES SHEET 11 FROM 11SHEETS APPENDIX E CONNECTOR PIN ASSIGNMENTS OF THE SYS68K/AGC-1 MASTER BOARD PI ---------------------------------------------------------------PIN NUMBER 1 2 ROW A SIGNAL MNEMONIC ROW B SIGNAL MNEMONIC ROW C SIGNAL MNEMONIC 3 4 099 D91 D92 D93 /BG9IN D98 099 019 011 5 6 7 8 094 095 D96 097 /BG90UT /BG1IN /BG10UT /BG2IN 012 013 014 015 9 GNO /BG3IN /BG30UT GND 19 11 12 GNO /OSl /SYSRESET 13 14 15 16 /DS9 /WRITE GND /OTACK AM9 /LWORD AM5 A23 A22 17 18 19 29 GND /AS GND /IACK AMI AM2 AM3 GNO A21 A29 A19 A18 21 22 23 24 /IACKIN /IACKOUT AM4 A97 GND /IRQ7 A17 A16 A15 A14 25 26 27 28 A96 A95 A94 A93 /IRQ6 /IRQ5 /IRQ4 /IRQ3 A13 A12 All A19 29 39 31 32 A92 A91 -12V +5V /IRQ2 /IRQ1 +5VSTDBY +5V A99 A98 ---------------------------------------------------------------- E-1 +5V APPENDIX E CONNECTOR ASSIGNMENTS OF THE AGC-l MASTER BOARD P2 PIN NUMBER ROW A SIGNAL MNEMONIC ROW B SIGNAL MNEMONIC +5V 1 2 GND 3 4 5 6 7 8 9 18 11 12 GND 13 14 15 16 +5V 17 18 19 28 21 22 23 24 GND 25 26 27 28 29 38 31 GND +5V 32 E-2 ROW C SIGNAL MNEMONIC APPENDIX E CONNECTOR ASSIGMENTS OF THE AGC-l MASTER BOARD p3 ---------------------------------------------------------------PIN NUMBER ROW A SIGNAL MNEMONIC ROW B SIGNAL MNEMONIC ROW C SIGNAL MNEMONIC 4 D15 /LDS R/W/ VPRZ D14 DBCLK MA19 MA18 D13 D12 Dll DB' S 6 7 8 DTGEO/ ZCLI SPREN GND MA17 MA16 GBPEN/ DGTEI/ D09 D08 D07 D06 MRD 12 CHR ZPRI/ GND DRAW/ VDD8 MA13 MA12 D05 D04 D03 D02 13 14 15 16 SMCYC GBDEN BPAEN/ BPGENI MAll MAIO MA09 MA08 DOl DOO VAS RCKA 18 19 20 VTDIR GND MA15 VDD7 VDD6 CAS/ RAS/ UDS/ 21 23 24 A18 A20 AI0 A12 A17 A19 A09 All MAS MA4 MA3 MA2 25 26 27 28 A14 A16 A02 A04 A13 A15 AOI A03 MAl MAO MA6 MA7 29 30 31 32 A06 A08 VDD4 VDD5 A05 A07 VDD2 VDD3 CLK21 HSYNC -12V VDDI 1 2 3 9 10 11 /---------------------------------------------------------------17 BPGENO MA14 W/ 22 E-3 APPENDIX E CONNECTOR ASSIGMENTS OF THE AGC-l MASTER BOARD P4 PIN NUMBER SIGNAL MNEMONIC 3 4 DISPI /HSYNC CLK31 2CLK S /EXSYNC 1 2 6 7 8 9 HJ 11 12 +SV LIGHT PEN GND 64M /64M 13 14 IS E-4 APPENDIX E CONNECTOR ASSIGMENTS OF THE AGC-l MASTER BOARD P6 ---------------------------------------------------------------PIN NUMBER ROW A SIGNAL MNEMONIC ROW B SIGNAL MNEMONIC ROW C SIGNAL MNEMONIC 2 3 4 IACIB/ CGEN/ CREN/ ABEN/ CDACK/ AMfIJ AMI AM2 CAT3 AM4 R/Wl RUN/ 5 6 7 8 AREN/ DMAEN/ IRQl/ BDEN5/ OWN 1/ RESET/ LWORD/ DERR/ DREQfIJ/ DTACI/ DONE/ READY/ 9 IRQIB/ DACKfIJ/ DDIR LAS/ CLK3 DCEN BR/ CLK2 ATT3 ASI/ DTACK/ MA2fIJ 1 IfIJ 11 12 13 14 15 16 CLK31 UDSI/ 17 18 CDCfIJ CDCl ATT7 LD4-2 LD4-1 LDSI/ CATfIJ CAT 1 CAT 2 19 2fIJ 21 22 23 24 25 26 27 DSENI DISP2 HSYNC/ CLKI /DTAC2 28 29 3fIJ 31 32 ISIO/ IASIO/ E-5 APPENDIX E CONNECTOR ASSIGNMENTS OF THE AGC-l SLAVE BOARD PI PIN NUMBER ROW A SIGNAL MNEMONIC ROW B SIGNAL MNEMONIC 1 2 3 4 BG9IN BG90UT BGIIN BGI0UT BG2IN 5 6 7 8 9 19 11 12 ROW C SIGNAL MNEMONIC GND BG20UT BG3IN BG30UT GND GND 13 14 15 16 GND 17 GND 18 19 GND 29 21 22 GND IACKIN IACKOUT 23 GND 24 25 26 27 28 29 39 31 32 -12V +5V +5VSTDBY +5V E-6 +5V APPENDIX E CONNECTOR ASSIGNMENTS OF THE AGC-l SLAVE BOARD p2 ---------------------------------------------------------------PIN NUMBER ROW A SIGNAL MNEMONIC ROW B SIGNAL MNEMONIC 1 2 3 4 +5V GND 5 6 7 8 9 10 11 12 GND 13 14 15 16 +5V 17 18 19 20 21 22 23 24 GND 25 26 27 28 29 30 31 32 GND +5V E-7 ROW C SIGNAL MNEMONIC APPENDIX E CONNECTOR ASSIGNMENTS OF THE AGC-1 SLAVE BOARD p3 ---------------------------------------------------------------PIN NUMBER ROW A SIGNAL MNEMONIC ROW B SIGNAL MNEMONIC ROW C SIGNAL MNEMONIC D15 /LDS R/W/ VPRZ D14 DBCLK MA19 MA18 D13 D12 D11 D11lJ DTGEIlJ/ ZCL1 SPREN GND MA17 MA16 GBPEN/ DGTE1/ DIlJ9 DIlJ8 DIlJ7 DIlJ6 MRD GND DRAW/ VDD8 MA13 MA12 DIlJ5 DIlJ4 DIlJ3 DIlJ2 13 14 15 16 SMCYC GBDEN BPAEN/ BPGEN1 MAll MA11lJ MAIlJ9 MAIlJ8 DIlJ1 DIlJIlJ VAS RCKA 17 18 19 21lJ BPGENIlJ VTDIR GND MA14 MA15 VDD7 VDD6 W/ CAS/ RAS/ UDS/ 21 22 23 24 A18 A21lJ A11lJ A12 A17 A19 AIlJ9 All MA5 MA4 MA3 MA2 25 26 27 28 A14 A16 AIlJ2 AIlJ4 A13 A15 AIlJ1 AIlJ3 MAl MAIlJ MA6 MA7 29 31lJ 31 32 AIlJ6 AIlJ8 VDD4 VDD5 AIlJ5 AIlJ7 VDD2 VDD3 CLK21 HSYNC -12V VDD1 1 2 3 4 5 6 7 8 9 11lJ 11 12 CHR ZPR1/ E-8 APPENDIX F COMPONENT PART LIST SYS68K/AGC-IA I Location Type I Manufacturer 1 1 ----------------------------------------------------------------1 JI 74ALS645-I TI J2 74ALS645-I TI J3 74ALS645-I TI J4 74ALS645-I TI J5 74ALS641-I TI J6 74LS682 TI, MOT J7 74LS283 TI, MOT J8 74LS283 TI, MOT J9 74LS682 TI, MOT JI0 74LSI25A TI, MOT JII 74F08 MOT, FAIR, VALVO JI2 74LS04 TI, MOT JI3 74LS74 TI, MOT JI4 74LS32 TI, MOT JI5 74F08 MOT, FAIR, VALVO JI6 74ALS645-I TI JI7 PAL I6L8A NAT, MMI JIB PAL 20LI0CN NAT, MMI JI9 PAL 20LI0CN NAT, MMI J20 74LSI12A TI, MOT J2I 74AS646 TI J22 74AS646 TI J23 74s244 TI, MOT F-I COMPONENT PART LIST SYS68K/AGC-IA ---------------------------------------------------------------Location Type Manufacturer ---------------------------------------------------------------J24 PAL 20L8A NAT, MMI J25 74F74 MOT, FAIR, VALVO J26 74F02 MOT, FAIR, VALVO J27 74LS08 MOT, TI J28 74F04 MOT, FAIR, VALVO J29 PAL 20L8A NAT, MMI J30 74F164 MOT, FAIR, VALVO J31 68153 BIM MOT J32 74LS21 TI, MOT J33 74LS139 TI, MOT J34 74LS112A TI, MOT J35 74LS08 TI, MOT J36 74LS85 TI, MOT J37 74LS74 TI, MOT J38 7406 TI, MOT J39 74LS195A TI, MOT J40 74F32 MOT, FAIR, VALVO J41 74F08 MOT, FAIR, VALVO J42 AM 8151 GCP AMD J43 AM 8151 GCP AMD J44 AM 8151 GCP AMD J45 74F244 MOT, FAIR, VALVO F-2 COMPONENT PART LIST SYS68K/AGC-IA ---------------------------------------------------------------Location Type Manufacturer ---------------------------------------------------------------J46 74F244 MOT, FAIR, VALVO J47 74F245 MOT, FAIR, VALVO J48 74F245 MOT, FAIR, VALVO J49 PAL 16L8A NAT, MMI J50 PAL 16R4A NAT, MMI J51 74F245 MOT, FAIR, VALVO J52 74F175 MOT, FAIR, VALVO J53 74F257 MOT, FAIR, VALVO J56 MC 7905 VARIOUS J57 MC 7905 VARIOUS J58 MC 7905 VARIOUS J59 MC 7905 VARIOUS J60 HD63484 ACRTC HITACHI J61 74LS125A TI, MOT J62 74ALS645-1 TI J63 74F04 MOT, FAIR, VALVO J64 74F241 MOT, FAIR, VALVO J65 74F163 MOT, FAIR, VALVO J66 74LS373 TI, MOT J67 74ALS374 TI J68 74LS373 TI, MOT J69 74ALS374 TI F-3 COMPONENT PART LIST SYS68K/AGC-IA ---------------------------------------------------------------Location Type Manufacturer ---------------------------------------------------------------J7B 74LS375 TI, MOT J7I 74FI57 MOT, FAIR, VALVO J72 FIBBI6 FAIR J73 FIBI24 FAIR J74 74FI64 MOT, FAIR, VALVO J75 FIBI24 FAIR J76 74F74 MOT, FAIR, VALVO J77 MCIBI25 FAIR, MOT J78 MCIBIB5 FAIR, MOT J79 MCIBIB4 FAIR, MOT J8B 74F74 MOT, FAIR, VALVO J8I 74FI53 MOT, FAIR, VALVO J82 PAL I6L8A NAT, MMI J83 74F164 MOT, FAIR, VALVO J84 74F25I MOT, FAIR, VALVO J85 74F25I MOT, FAIR, VALVO J86 74FI64 MOT, FAIR, VALVO J87 74FI64 MOT, FAIR, VALVO J88 74F25I MOT, FAIR, VALVO J89 74F25I MOT, FAIR, VALVO J9B 74FI64 MOT, FAIR, VALVO J9I 74F74 MOT, FAIR, VALVO F-4 COMPONENT PART LIST SYS68K/AGC-IA Location Manufacturer Type J92 74F74 MOT, FAIR, VALVO J93 74F164 MOT, FAIR, VALVO J94 74F164 MOT, FAIR, VALVO J95 74F164 MOT, FAIR, VALVO J96 74F86 MOT, FAIR, VALVO J97 74F04 MOT, FAIR, VALVO F-5 COMPONENT PART LIST SYS68K/AGC-1A RESISTOR NETWORKS ---------------------------------------------------------------Manufacturer Location Type ---------------------------------------------------------------N1 9 * 3.3K OHM VARIOUS N2 9 * 3.3K OHM VARIOUS N3 9 * 3.3K OHM VARIOUS N4 9 * 3.3K OHM VARIOUS N5 9 * 3.3K OHM VARIOUS N6 9 * 3.3K OHM VARIOUS N7 9 * OHM VARIOUS N8 9 * 330 OHM VARIOUS N9 9 VARIOUS N18 9 * 150 OHM * 3.3K OHM NIl 9 * 150 OHM VARIOUS N12 9 * 270 OHM VARIOUS N13 9 * 278 OHM VARIOUS N14 9 VARIOUS E1 * 150 OHM 5 * 27 OHM E2 5 HHJ VARIOUS 18 PIN SLIM LINE 27 OHM 10 PIN SLIM LINE E3 * 5 * 27 OHM 10 PIN SLIM LINE E4 5 27 OHM 10 PIN SLIM LINE * F-6 COMPONENT PART LIST SYS68K/AGC-IA RESISTORS Location Manufacturer Type ---------------------------------------------------------------- Note: Rl 2.2K OHM VARIOUS R2 2.2K OHM VARIOUS R3 2.9K OHM 1% VARIOUS R4 2.9K OHM 1% VARIOUS R5 2.9K OHM 1% VARIOUS R6 27 OHM VARIOUS R7 27 OHM VARIOUS R8 339 OHM VARIOUS R9 229 OHM VARIOUS R19 689 OHM VARIOUS Rll lK OHM VARIOUS R12 lK OHM VARIOUS R13 68 OHM VARIOUS All resistors are type RGU mini 2.54 RM. F-7 COMPONENT PART LIST SYS68KiAGC-1A CAPACITORS Location :C1 - :C76 CO Type 100 nF Manufacturer KER VARIOUS VARIOUS C1 ELKO 220uF /6V 5.08mm RM. 47 pF C2 470 pF + 10% VARIOUS C3 - C14 100 nF VARIOUS C15 - C16 10 pF + 10% VARIOUS C17 VARIOUS ELKO 100uF/>12V 5.08mm RM. 10 uF 6.3 V TAN VARIOUS C22 220 pF + 19% VARIOUS C23 470 pF + 10% VARIOUS C24 1nF VARIOUS C18 - C21 VARIOUS CRYSTALS 1 Location 1 Type 1 Manufacturer 1 1----------------------------------------------------------------1 1 1 1 1 1 01 1 16.000 MHz 1 SE, JAUCH 1 1 1 1 1 02 1 64.000 MHz 1 SE, JAUCH 1 1 1 1 1 1 F-8 COMPONENT PART LIST SYS68K/AGC-IA DIODES ---------------------------------------------------------------Location Type Manufacturer ---------------------------------------------------------------LDI 559 - 2296 LED GREEN LD2 559 - 2496 LED RED LD3 559 - 2396 LED YELLOW Dl IN 4148 DIODE Tl 2N 2995 TRANSISTOR T2 2N 2222 TRANSISTOR MECHANICAL PARTS Location Manufacturer Type ---------------------------------------------------------------J17 29 PIN SOCKET VARIOUS J18 - J19 24 PIN SLIM SOCKET VARIOUS J24 24 PIN SLIM SOCKET VARIOUS J29 24 PIN SLIM SOCKET VARIOUS J31 49 PIN SLIM SOCKET VARIOUS J42 - J44 49 PIN SLIM SOCKET VARIOUS J49 - J59 J69 J82 29 PIN SOCKET 64 PIN SLIM SOCKET 29 PIN SOCKET F-9 VARIOUS VARIOUS VARIOUS COMPONENT PART LIST SYS68K/AGC-1A MECHANICAL PARTS Location Manufacturer Type PI VG MALE CONNECTOR 96 PIN 98 DEGREE 2 x SCREW 2. S/18 2 x MOTHER 2. S VARIOUS P2 VG MALE CONNECTOR 96 PIN 98 DEGREE 2 x SCREW 2.S/18 2 x MOTHER 2. S VARIOUS P3 FORCE 983848 VARIOUS P3 FORCE 983841 VARIOUS P4 D FEMALE CONNECTOR IS PIN 98 DEGREE 2 PLATED SCREW 2.9/9.Smm VARIOUS . P6 VG FEMALE CONNECTOR 96 PIN Nr 983864 2 x SCREW 2.S/18 2 x MOTHER 2.S VARIOUS (without wire wrap) B1 DW 8 VARIOUS B2 DW 8 VARIOUS B3 DW 12 VARIOUS B4 DW 16 VARIOUS BS DW 18 VARIOUS B6 DW 18 VARIOUS B7 EW 2 VARIOUS ---------------------------------------------------------------- F-18 COMPONENT PART LIST SYS68K/AGC-1A MECHANICAL PARTS Location Manufacturer Type B8 TW 15 VARIOUS B9 EW 3 VARIOUS B1ft' EW 3 VARIOUS B11 DW 4 VARIOUS B12 EW 3 VARIOUS B13 DW 14 VARIOUS B14 DW 16 VARIOUS B15 TW 24 VARIOUS B16 DW 8 VARIOUS B17 TW 21 VARIOUS B18 DW 8 VARIOUS BNC1 BNC- CONNECTOR WITH ISOLATED MOUNTING BNC2 BNC- CONNECTOR WITH ISOLATED MOUNTING BNC3 BNC- CONNECTOR WITH ISOLATED MOUNTING BNC4 BNC- CONNECTOR WITH ISOLATED MOUNTING Frontpanel FRBL AGC-1A VARIOUS PC-Board AGC-1A VARIOUS Specially designed VARIOUS SW1 Switch ATE-1D-RA KNITTER SW2 Switch ATE-1D-RA KNITTER Bx JUMPER (41) VARIOUS Cooling Panel F-11 COMPONENT PART LIST SYS68K/AGC-IB ICs ---------------------------------------------------------------Location Type Manufacturer ---------------------------------------------------------------JI 74FI38 MOT, FAIR, VALVO J2 74FI38 MOT, FAIR, VALVO J3 74FI6I MOT, FAIR, VALVO J4 74F244 MOT, FAIR, VALVO J5 74F244 MOT, FAIR, VALVO J6 74LS374 TI, MOT J7 74F373 MOT, FAIR, VALVO J8 74LS374 TI, MOT J9 74F374 MOT, FAIR, VALVO JI9 74LS374 MOT, FAIR, VALVO JII 74F374 MOT, FAIR, VALVO JI2 74LS374 TI, MOT JI3 74F374 MOT, FAIR, VALVO JI4 74LS374 MOT, FAIR, VALVO JI5 74F374 MOT, FAIR, VALVO JI6 74LS374 MOT, FAIR, VALVO JI7 74F374 MOT, FAIR, VALVO JI8 74LS374 MOT, FAIR, VALVO JI9 74F374 MOT, FAIR, VALVO J29 74LS374 MOT, FAIR, VALVO J2I 74F374 MOT, FAIR, VALVO J22 74LS374 MOT, FAIR, VALVO J23 74F374 MOT, FAIR, VALVO F-12 COMPONENT PART LIST SYS68K/AGC-IB Location Type Manufacturer 1 1 1 1---------------------------------------------------------------1 J24 TI, MOT 1 74LS374 1 J25 MOT, FAIR, VALVO 1 74F374 1 J26 MOT, FAIR, VALVO 1 74LS374 J27 74F374 MOT, FAIR, VALVO J28 74LS374 MOT, FAIR, VALVO J29 74F374 MOT, FAIR, VALVO J3r2l 74LS374 MOT, FAIR, VALVO J31 74F374 MOT, FAIR, VALVO J32 74LS374 MOT, FAIR, VALVO J33 74F374 MOT, FAIR, VALVO J34 7 4LS37 4 MOT, FAIR, VALVO J35 74F374 MOT, FAIR, VALVO J36 74LS374 MOT, FAIR, VALVO J37 74F374 MOT, FAIR, VALVO J38 74F374 MOT, FAIR, VALVO J39 74ALS645-1 TI J4r2l 74ALS645-1 TI J41 74ALS645-1 TI J42 74ALS645-1 TI J43 74ALS645-1 TI J45 74ALS645-1 TI J44 74ALS645-1 TI J46 74ALS645-1 TI J47 74ALS645-1 TI F-13 COMPONENT PART LIST SYS68KiAGC-IB ---------------------------------------------------------------Location I Type Manufacturer ---------------------------------------------------------------J48 I I I I I I 74ALS645-1 TI 74ALS645-1 TI 74ALS645-1 TI J51 74ALS645-1 TI J52 74ALS645-1 TI J53 74ALS645-1 TI J54 74ALS645-1 TI J55 74F74 MOT, FAIR, VALVO J56 74F94 MOT, FAIR, VALVO J57 74LS244 TI J58 74F245 MOT, FAIR, VALVO J59 74F245 MOT, FAIR, VALVO J69 74AS646 TI J61 74AS646 TI J62 74F373 MOT, FAIR, VALVO J63 74F157 MOT, FAIR, VALVO J64 74F138 MOT, FAIR, VALVO J65 PAL 29L8A MMI, NS J66 PAL 29L8A MMI, NS J67 AM2966 AMD J68 AM2966 AMD J69 74F373 MOT, FAIR, VALVO J49 J59 F-14 COMPONENT PART LIST SYS68KiAGC-IB ICs ---------------------------------------------------------------Location Type Manufacturer ---------------------------------------------------------------J70 74F157 MOT, FAIR, VALVO J71 74F138 MOT, FAIR, VALVO J72 PAL 20L8A MMI, NS J73 74F244 MOT, FAIR, VALVO J74 AM 2966 AMD J75 AM 2966 AMD J76 74F373 MOT, FAIR, VALVO J77 74F245 MOT, FAIR, VALVO J78 74F245 MOT, FAIR, VALVO J79 41464P-12 HIT J80 41464P-12 HIT, NEC J81 41464P-12 HIT, NEC J82 41464P-12 HIT, NEC J83 41464P-12 HIT, NEC J84 41464p-12 HIT, NEC J85 41464P-12 HIT, NEC J86 41464P-12 HIT, NEC J87 41464P-12 HIT, NEC J88 41464P-12 HIT, NEC J89 41464P-12 HIT, NEC J90 41464P-12 HIT, NEC J91 41464P-12 HIT, NEC F-15 COMPONENT PART LIST SYS68K/AGC-IB ---------------------------------------------------------------Location Type Manufacturer ---------------------------------------------------------------J92 41464P-12 HIT, NEC J93 41464P-12 HIT, NEC J94 41464P-12 HIT, NEC J95 41464P-12 HIT, NEC J96 41464P-12 HIT, NEC J97 41464P-12 HIT, NEC J98 41464P-12 HIT, NEC J98 41464P-12 HIT, NEC J99 41464P-12 HIT, NEC JHH' 41464P-12 HIT, NEC JHH 41464P-12 HIT, NEC J102 41464P-12 HIT, NEC J103 41464P-12 HIT, NEC Jl04 41464P-12 HIT, NEC Jl05 41464P-12 HIT, NEC J106 41464P-12 HIT, NEC Jl07 41464P-12 HIT, NEC Jl08 41464P-12 HIT, NEC Jl09 41464P-12 HIT, NEC Jl10 41464P-12 HIT, NEC JIll 41464P-12 HIT, NEC Jl12 41464P-12 HIT, NEC ----------------------------------------------------------------F-16 COMPONENT PART LIST SYS68K/AGC-IB Location Type Manufacturer ---------------------------------------------------------------Jl13 41464P-12 HIT, NEC Jl14 41464P-12 HIT, NEC Jl15 41464P-12 HIT, NEC Jl16 41464P-12 HIT, NEC Jl17 41464P-12 HIT, NEC Jl18 41464P-12 HIT, NEC Jl19 41464P-12 HIT, NEC J120 41464P-12 HIT, NEC J121 41464p-12 HIT, NEC J122 41464P-12 HIT, NEC J123 41464P-12 HIT, NEC J124 41464P-12 HIT, NEC J125 41464P-12 HIT, NEC J126 41464P-12 HIT, NEC J127 41464P-12 HIT, NEC J128 41464P-12 HIT, NEC J129 41464P-12 HIT, NEC J130 41464P-12 HIT, NEC J131 41464P-12 HIT, NEC J132 41464P-12 HIT, NEC J133 41464P-12 HIT, NEC J134 41464p-12 HIT, NEC ---------------------------------------------------------------- F-17 COMPONENT PART LIST SYS68K/AGC-IB Location Manufacturer Type J135 41464P-12 HIT, NEC J136 41464P-12 HIT, NEC J137 41464P-12 HIT, NEC J138 41464P-12 HIT, NEC J139 41464P-12 HIT, NEC J14riJ 41464P-12 HIT, NEC J141 41464P-12 HIT, NEC J142 41464P-12 HIT, NEC ---------------------------------------------------------------- F-18 COMPONENT .~ART LIST SYS68K/AGC-IB RESISTOR NETWORKS 1 Location 1 Type 1 Manufacturer 1 1-----------------------------------------------------------------1 1 I 1 1 Nl 1 9 * 3.3K OHM 1 VARIOUS I 1 1 1 1 1 1 N2 1 9 * 3.3K OHM 1 VARIOUS 1 I 1 1 1 1 N3 1 9 * 47a OHM 1 VARIOUS 1 1 1 1 1 CAPACITORS 1 Location 1 Type I Manufacturer 1 1----------------------------------------------------------------1 1 1 1 1 1 laa nF KER 1 VARIOUS 1 1 Cl - C69 1 1 1 1 F-19 COMPONENT PART LIST SYS68K/AGC-1B MECHANICAL PARTS ---------------------------------------------------------------Location Type Manufacturer I ---------------------------------------------------------------I I I I J1 - J3 16 PIN SOCKET J4 - J37 29 PIN STACKED DIP SOCKET J38 29 PIN SOCKET VARIOUS J39 - J54 29 PIN STACKED DIP SOCKET T &B J55 - J56 14 PIN SOCKET VARIOUS J57 - J59 29 PIN STACKED DIP SOCKET T &B J69 - J61 24 PIN SLIM SOCKET VARIOUS J62 - J63 29 PIN STACKED DIP SOCKET T &B J64 16 PIN SOCKET VARIOUS J65 - J66 24 PIN SLIM SOCKET VARIOUS J67 - J69 29 PIN STACKED DIP SOCKET T &B J79 - J71 16 PIN SOCKET VARIOUS J72 24 PIN SLIM SOCKET VARIOUS J73 - J142 29 PIN STACKED DIP SOCKET T &B 29 PIN STACKED VARIOUS T &B DIP SOCKETS TOTAL OF 64 PIECES F-29 COMPONENT PART LIST SYS68K/AGC-IB MECHANICAL PARTS Location Type Manufacturer PI VG MALE CONNECTOR 2 x SCREW 2.5/18 2 x MOTHER 2.5 FORCE 983839 P2 VG MALE CONNECTOR 2 x SCREW 2.5/18 2 x MOTHER 2.5 FORCE 983838 P3 VG FEMALE CONNECTOR 96 PIN Nr 983864 2 x SCREW 2.5/18 2 x MOTHER 2.5 VARIOUS (without wire wrap) Bl - B2 TW Frontpanel FRBL AGC-IB VARIOUS PC-Board AGC-IB VARIOUS 9 JUMPER VARIOUS 3x ---------------------------------------------------------------- F-21 APPENDIX G LITERATURE REFERENCE Please refer information. to the following books for further more detailed 1) User's manual of the 63484 ACRTC, including description the instructions - M-01-85--1.ACRTC(680-1-31) HITACHI 3) HD63484 ACRTC APPLICATION NOTE I 680-3-08 HITACHI 4) HD63484 ACRTC APPLICATION NOTE II 680-3-07 HITACHI 5) VMEbus specifications 2618 S Shannon Tempe Arizona 85282 (602) 966-5936 G-l of APPENDIX H DEFAULT JUMPER SETTINGS ON THE SYS68K/AGC-1 BOARDS Description Jumpers 1 1 Boa r d Size Selection 1 Default I Schematics 1 See Page 1-8 2-7 3 6 4-5 B1 1-C2 1-19 1 1 1 1 1 1 1 1 I---------------------------------------~----1 1 1 8 1 1 B2 1 2 7 1 1-C3 1 1-19 1 1 1 3 6 1 1 1 1 4 5 1 1 ----------------------------------------------------------------Base Address 1 1 1 1 I Selection 1 1 B3 I $C99999 1 AM-Code 1 I = 1-D1 1-9 2-C3 1-26 158 I 6 7 1 1 1 Address Modifier 1 1 Selection 1 I 1-12 2-11 3-19 4-9 B4 3D,3E I I 1 I 1-16 2-15 3-14 4 13 5 12 6-11 7 19 8-9 I I I I 1----------------------------------------------------------------1 1 1 1-19 1 1 1 Access- Synchronisation Setting 1 1 I B5 I 1 1 1 I 9 8 7 6 I 1 1 3-A3 1 I 1 1 1 B6 1-19 2-9 3-8 4-7 5 6 3-C3 1-15 B7 1-2 4-Cl 1-127 Short I/O-Access Selection CSYNC Polarity 2 3 4 5 H-l APPENDIX H Jumper Location Diagram of Jumpers Bl = B7 D 817 C17 J94 J28 J30 Jl J25 J9 H-2 APPENDIX H DEFAULT JUMPER SETTINGS ON THE SYS68K/AGC-1 Description Jumpers B8 Blink Switch Mode 1 Light Pen Strobe 1 Polarity 1 B9 1 Default 1 Schematics 1 See Page 1 1 2-3 1 4 5-6 167 8 1 9 19 11 1 1 1-2 3 1 4-D2 1-39 5-A3 1-123 ----------------------------------------------------------------Master/Slave 1 1 B19 1 1 1-2 3 1 5-A4 1 1-126 1 6-Al 1 1-126 7-C1 1 1 1 1-129 1--------------------------------------------1-2 1 1 Mode l l B11 1 1 3-4 ----------------------------------------------------------------Scroll Clock 1 1 1 B12 1 1 1-2 3 1 -------------------------------------~---------------- ----------- 1 14 2 13 3 12 1 1 1 BLANK Delay 1 1 1 1 B13 4 11 5-19 1 169 178 7-Cl 1 1 1 1 ----------------------------------------------------------------1 16 1 1 1 1 RAS - Timing 1 2 15 3 14 4 13 B14 1 1 5 6 7 8 12 11 19 9 7-C2 1 1 I 1 4 5 6 1 7 8 9 119 11-12 113-14 15 116 17 18 119 29 21 122 23 24 1 1 1 1 1 1 1 1 1 1 1 1 1 1 I I 1 1 1 1 I 1 1 CAS - Timing 1 1 1 1 1 1 1 1 1 I 1----------------------------------------------------------------1 1 1 1 2 3 1 1 B15 H-3 7-C3 I I APPENDIX H Jumper Location Diagram of Jumpers B8 ~ ~~ ~ ~'~ I ~J I z~ ~ =BIS D ~~ .liS J38 n OD~Dll ~~, , 04J U N~ Ow J75 n J57 g,mQ ~ C3 - bl C7 gJ60.[J . 0 '" Jd7 H-4 D APPENDIX H DEFAULT JnMPER SETTINGS ON THE SYS68K/AGC-l Description Jumpers I Default I Schematics I See Page 1-8 Register Timing B16 2 7 3 6 7-03 4 5 WRITE - Timing B17 I 123 I 456 I 789 I H'-11 12 7-03 1 8 2 7 4-C3 113 14 15 116 17 18 119 29-21 Switch Colour B18 3-6 4-5 Mode H-5 1-36 APPENDIX H Jumper Location Diagram of Jumpers BI6 ~ BIB ~. ~ ~~ J69 ~ ~o.--J J66 ~ 78 J67 p-'L-J r-- o~ :<;7 0 r-- 62 n J70 J19 ;;10 " ~oa -:;1 C7 "'" ] d~dO DPD in DP (4 bit/pixel mode) 0 1 1 0 1 0 01 Read data (Frame buffer data: before correction) 0 1 1 0 1 0 oj Write data (Frame buffer data: after correction) ~ 10 0 0 1 ~. :dO I 1 ~;lj:!1 J Color data lcolor register) One pixel of the frame buffer read data is ORed with the corresponding color register data and the result is rewritten to the frame buffer read data location. The dot pointer serves to extract the pixel from the frame buffer word - in this example, 4 bits/pixel. Figure 6.9(b) OR Operation Mode 140 HITACHI =010 . OPM I 010 AND 3 0 1011 1·1·1 10 0 0 1 10 Of 010 10 0 0 1 10 0 0 01 0 I ~ I 1 I) to 11 OPO in OP (4 bit/pixel model Read data 0 1 1 0 1 0 01 0 1 1 0 1 0 01 (Frame buffer data: before correction) Write data I (Frame buffer data: after correction) Color data (Color register) One pixel of the frame buffer read data is ANDed with the corresponding color register data and the result is rewritten to the frame buffer read data location. The dot pointer serves to extract the pixel from the frame buffer word - in this example, 4 bits/pixel. Figure 6.9(c) AND Operation Mode HITACHI 141 OPM = 011 ~ 011 I EOA 3 0 1011 1·1·' OPO in OP 14 bit/pi Kef model Read data (Frame buffer data: before correction) Write data (Frame buffer data: after correction) Color data (color register) One pixel of the frame buffer read data is EORed with the corresponding color register data and the result is rewritten to the frame buffer read data location. The dot pointer serves to extract the pixel from the frame buffer word - in this example, 4 bits/pixel. Figure 6.9(d) EOR Operation Mode 142 HITACHI OPM = 100 •I 1 00 Conditional Replacement (P 3 = CCMP) 0 1011 1·1·1 DPD in DP (4 bit/pixel mode) ~--~~+-~----------~ Color Comparison Register data (CCMP) Read data (Frame buffer data: before correction) Write data (Frame buffer data: aftar correction) Color data (Color registerl One pixel of the frame butTer read data is compared with the corresponding one pixel contents of the Color Comparison Register (CCMP). If equal, the read data is replaced with the color data and the result is rewritten to the read data location in the frame butTer. If not equal, the read data (unmodified) is rewritten to the read data location in the frame butTer. The dot pointer serves to extract the pixel from the frame butTer word - in this example, 4 bits/pixel. Figure 6.9(e) P= CCMP Operation Mode HITACHI 143 OPM=101 ~ Conditional Replacement (P + CCMP) 3. 0 1011 1·1·1 DPD in DP (4 bit/pixel mode) Color Comparison Register (CMP) data Read data (Frame buffer data: before correction)· Write data (Frame buffer data: after correction) Color data (Color register) One pixel of the frame buffer read data is compared with the corresponding one pixel contents of the Color Comparison Register (CCMP). If not equal, the read data is replaced with the color data and the result is rewritten to the read data location in the frame buffer. If equal, the read data (unmodified) is rewritten to the read data location in the frame buffer. The dot pointer serves to extract the pixel from the frame buffer word - in this example, 4 bits/pixel. Figure 6.9(1) P =1= CCMP Operation Mode 144 HITACHI OPM= 110 ~ Conditional Replacement IP 3 < CLI 0 10 I, 1·1·1 DPD in DP 14 bit/pixel model Read data (Frame buffer data: before correction) ,..----Jj"--....,..---...-----"----., Write data (F fame buffer data: after correct ion 1 Color data (Culor register) One pixel of the frame buffer read data is compared with the corresponding one pixel contents of the color data (CL). If the read data is LESS than the color data, the read data is replaced with the color data and the result is rewritten to the read data location in the frame buffer. If the read data is GREATER than or EQU AL to the color data, the read data (unmodified) is rewritten to the read data location in the frame buffer. The dot pointer serves to extract the pixel from the frame buffer word - in this example, 4 bits/pixel. Figure 6.9(g) P< CL Operation Mode HITACHI 145 OPM = 111 ~ 1 11 I Conditional Replacement (P 3 > eL) 0 10 11 1-1·1 OPO in OP (4 bit/pixel mode) 000 0 00110100 o 1 00110100 0 0 Read data (Frame buffer data: before correction) Write data (Frame buffer data: after correction) Color data (Color register) One pixel of the frame buffer read data is compared with the corresponding one pixel contents of the color data (CL). If the read data is GREATER than the color data, the read data is replaced with the color data and the result is rewritten to the read data location in the frame buffer. If the read data is LESS than or EQUAL to the color data, the read data (unmodified) is rewritten to the read data location in the frame buffer. The dot pointer serves to extract the pixel from the frame buffer word - in this example, 4 bits/pixel. Figure 6.9(h) P> CL Operation Mode 146 HITACHI ,--------------, 11 J7//I I I tLL1 I I I I I I I I II I I I I I I I L _ _ _ _ _ _ _ _ _ _ _ _ _ _ ...1I Drawing Pattern Picture Memory before Drawing ,---------------, r--------------, I I F7A tL:d I I I I I I I I I I I I I I I I I Replacement OR r--------------, r--------------,I I I I I I I I I I I I I I I nJ1 I I I7/l rL::l I I I I I I I I I L ______________ -.! AND EOR Figure 6.10 Operation Mode Example HITACHI 147 3. Colour Mode Examples COL =00 Graphic Pattern RAM (PEX, PEY) (PSX, PSY) If the scanned Pattern RAM bit is equal '0', Color Register 0 (CLO) determines the color information. If the scanned Pattern RAM bit is equal '1', Color Register 1 (CLl) determines the color information. Figure 6.11 (a) Color Mode = 00 HITACHI 149 COL =01 Graphic Pattern RAM (c) O""-_,...-_ _ _ ~~-___,_II (PEX, PEY) Color Register 0 x = 1 (PSX, PSY) If the scanned Pattern RAM bit is equal '0', the drawing operation is suppressed and the frame buffer is not changed. If the scanned Pattern RAM bit is equal '1', Color Register 1 (CLl) determines the color information. Figure 6.11 (b) Color Mode .:.... 01 150 HITACHI COL = 10 Color Information =r= Color Register 0 Graphic Pattern RAM (PEX, PEY) ,-------, (PPX, PPY) Color Register 1 (PSX, PSY) If the scanned Pattern RAM bit is equal '1', the drawing operation is suppressed and the frame buffer is not changed. If the scanned Pattern RAM bit is equal '0', Color Register 0 (CLO) determines the color information. Figure 6.11 (e) Color Mode = 10 HITACHI 151 ICOL=lll PPX Pattern RAM PPY 3 F 2 E 1 D 0 C 3 B 2 " 0 8 9 3 7 2 6 5 0 4 3 3 C E F 2 8 A B 4, 6 2 ~Ol D o Bit Information on Pattern RAM Figure 6.11 Cd) Color Mode = 11 In the former three color modes (Pattern RAM indirect), the actual color information is stored in the color registers (CLO, CLl) and selection is based on the 0 or 1 bit value during Pattern RAM scanning. In color mode = 11 (Pattern RAM direct), the Pattern RAM contents are directly used to generate color information. This is accomplished by remapping of the Pattern RAM so that it is interpreted as containing up to 4 by 4 logical pixel color patterns, each of which contains 16 bits of color information. 152 HITACHI 4. Area Mode Examples AREA= XOO : Area Mode (XMAX, YMAX) (XMIN, YMIN) Drawing is executed without area checking. Figure 6.12(&) Area Mode = XOO HITACHI 155 AREA I: = 001 Area Mode (XMAX, YMAX) Area Definition / / I I I I I \ \ \ I "" I I I ----"'" " (XMIN, YMIN) Drawing is executed as long as the CP (Current Pointer) resides in the defined area. When the drawing operation causes the CP to go outside the defined area, the drawing instruction is terminated and the ARD (Area Detect) and CEO (Command End) flags in the Status Register (SR) are set to '1'. Figure 6.12(b) Area Mode 156 HITACHI = 001 AREA = 010 I: Area Mode (XMAX, YMAX) (XMIN, YMIN) Wheh the CP (Current Pointer) is outside the defined area, drawing is suppressed but the drawing operation continues. When CP is inside the defined area, drawing operation is enabled. When the drawing instruction execution is completed, the CEO (Command End) bit in the Status Register (SR) is set to '1'. The ARD bit (Area Detect) bit in the Status Register is not set to '1' at any time during the drawing instruction execution regardless of whether CP goes inside or outside the defined area. Figure 6.12(c) Area Mode = 010 HITACHI 157 AREA= 011 I : Area Mode (XMAX. YMAX) I / / I I I \ \ \ \ " (XMIN, YMIN) This mode is the same as AREA MODE = 010 in that drawing is enabled when CP (Current Pointer) is inside the defined area and suppressed when CP is outside the defined area. However, if at any time during the drawing instruction execution, CP goes outside the defined area, the ARD (Area Detect) bit in the Status Register (SR) will be set to '1'. The ARD bit can be monitored to determine when the CP goes outside the defined area. Figure 6.12(d) Area Mode 158 HITACHI = 011 AREA = 101 I: Area Mode (XMAX, YMAX) Area Definition / / I I I I \ I \ , ~--------------~'---_/ I " / / (XMIN, YMIN) Drawing is executed as long as the CP (Current Pointer) resides outside the defined area. When the drawing operation causes the CP to go inside the defined area, the drawing instruction is terminated and the ARD (Area Detect) and CEO (Command End) flags in the Status Register (SR) are set to '1'. Figure 6.12(e) Area Mode = 101 HITACHI 159 AREA = 110 I: Area Mode (X MAX, YMAX) (XMIN, YMIN) When the CP (Current Pointer) is inside the defined area, drawing is suppressed but the drawing operation continues. When CP is outside the defined area, drawing operation is enabled. When the drawing instruction execution is completed, the CED (Command End) but in the Status Register (SR) is set to '1'. The ARD bit (Area Detect) bit in the Status Register is not set to '1' at any time during the drawing instruction execution regardless of whether CP goes inside or outside the defined area. Figure 6.12 (f) Area Mode = 110 160 HITACHI AREA = 111 I: Area Mode (XMAX, YMAX) Area Definition / I (XMIN, YMIN) This mode is the same as AREA MODE = llO in that drawing is enabled when CP (Current Pointer) is outside the defined area and suppressed when CP is inside the defined area. However, if at any time during the drawing instruction execution, CP goes inside the defined area, the ARD (Area Detect) bit in the Status Register (SR) will be set to '1'. The ARD bit can be monitored to determine when the CP goes inside the defined area. figure 6.12 (g) Area Mode = 111 HITACHI 161 TYPE Register Access Command MNEMONIC ORG WPR RPR WPTN RPTN DRD ~_T_ Data Transfer Command DMOD RD WT MOD CLR SCLR CPY SCPY a a a a a a a a a a a a a a a 1 1 Absolute Line 1 Relative Line 1 Absolute Rectangle 1 Relative Rectangle 1 Absolute Polyline 1 Relative Polyline 1 Absolute Polygon 1 Relative Polygon 1 Circle 1 Ellipse 1 Absolute Arc 1 Relative Arc 1 Absolute Ellipse Arc 1 Relative Ellipse Arc 1 Absolute Filled Rectangle 1 Relative Filled Rectangle 1 Paint 1 Dot 1 Pattern 1 Absolute Graphic Copy 1 Relative Graphic Copy 1 RMOVE ALINE RLiNE ARCT RRCT APLL RPLL APLG RPLC CRCL ELPS AARC RARC AEARC Relative Move AFRCT RFRc;-T PAINT DOT PTN AGCPY RGCPY a a a a a a a a 1 1 1 1 1 1 1 a a a a a a a a a a a a a a a a 1 1 1 1 1 1 1 a a a a a 1 1 1 a a 0 a a 1 1 a a a a a a a a 1 1 1 1 1 1 1 1 a a a a a 1 1 - (cycles) # (words) OPERATION CODE PARAMETER 8 a a 1 ,0 0,0 a a a '0 a a a DPH DPL 3 6 2 RN 0'1 a ,0 a ,0 a a, D 1 6 RN 0'1 1 ,0 0'0 a a, 1,1 a ,0 0'0 a a a, PRA 4n+8 n n+2 Dl,· . , Dn 1,1 1 '0 0'0 a a a, PRA 4n+l0 n 2 (4x+8)y+12[x'y/8t) +(62-68) a :0 1 i a 0:0 a a a ,a a 0 a AX AY 3 0:1 a 'a ala a a a ,a a a a AX AY 14x+8)y+16[x'y/8t) +34 3 all 1 : 0 0:0 a a a ,a O:MM AX AY 14x+8)y+16Ix'y/8t) +34 3 12 a 'a 1 '0 0'0 a a a :0 a a a 1 8 0'1 a '0 0:0 a a a 'a a a a D 2 2 8 D all 1 '0 0,0 a a a ,a 0' MM 12x+8)y+12 1 1 a : a 0,0 a a a 'a a a a D AX AY 4 AX AY 4 14x+6)y+12 1 '1 1 '0 0'0 a a a ,a O:MM D a IS : DSD ,0 a a a ,a a a a SAH SAL AX AY 16x+l0)y+12 5 1 ,5' DSD ,a a a a ,0 0: MM SAH SAL AX AY 16x+l0)y+12 5 Y 56 a a a ,0 0,0 a a a ,0 a a a X 3 a 10 1 '0 0,0 a a a ,0 a a a dX dY 56 3 0,1 a '0 0' AREA COL OPM X Y P'L+18 3 a 1 1 ,0 0' AREA COL OPM dX dY P'L+18 3 Y 2PIA+B)+54 1 :0 a ,0 a' AREA COL OPM X 3 1 :0 1 ,0 0' AREA COL OPM 2PIA+B)+54 dX dY 3 L[P'L+16)+8 1 '1 a ,0 0' AREA:COL OPM n Xl, Yl,. . Xn, Yn 2n+2 1 ,1 1 '0 0' AREA,COL OPM dXl,dYl, . dXn, dYn 2n+2 LIP'L+16)+8 n a ,0 a ,0 0' AREA:COL OPM 2n+2 L[P'L+16]+P'Lo+20 n Xl, Yl, .. Xn, Yn n dXl,dYl, .. dXn, dYn 2n+2 LIP'L+16)+P'Lo+20 a ,a 1 '0 0; AREA' COL OPM r 0'1 a 'O'C' AREA:COL:OPM 2 8d+66 dX 4 10d+90 0 1 1 I o'e; AREA:COLIOPM a b Yc Ye 1 a a 'O'C ' AREA:COL:OPM 8d+18 Xc Xe 5 1 '0 1 ,O,C' AREA'COL'OPM dXc dYe dXe dYe 5 8d+18 f---.Ye 1 '1 a 'O,C' AREA: COL'OPM- a Xc Yc Xe 10d+96 b 7 1,1 1 'o'c' AREA: COL: OPM 10d+96 b dXc dYc dXe dYe 7 a o ,0 a '0 0' A'REA:'COL: OPM Y IP'A+B)B+18 X 3 a 'a 1 ,0 0' AREA: COL: OPM IP'A+B)B+18 dX dY 3 *1) 0'1 O~ AREA: COL: OPM 118A+l02)B-58 1 0'1 1 '0 0: AREA: COL: OPM 1 8 I AREA: COL: OPM *2) 1 ISL: SD Sl IP'A+l0)B+20 2 , AREA:O 0: OPM IIP+2)A+l0)B+70 Xs Ys DX DY 0,5 : DSD 5 AREA: a O!OPM dXs dYs DX DY IIP+2)A+l0)B+70 1 '5 : DSD 5 In case of rectangular filling 15 *2) Read Parameter Register Write Pattern RAM Read Pattern RAM DMA Read DMA Write DMA Modify Read Modify Clear Selective Clear Copy Se lect ive Copy Absolute Move ~. *1) Write Parameter Register Write ~?VE Graphic Command COMMAND NAME Origin 87 0 Sl: LSly t Slx t Sly, Slx: Pattern Size L/Lo/d: sum of drawing dots AlB: drawing dots of main/sub direction C: [C~l Iciockwise),C~O Ireverse)) [t): rounding up n: number of repetition xlv: drawing words of x-direction/v-direction E: [E~O Istopat Edge color), E~l Istop at excepting Edge color)) )4' OPM·OOO - all P~16:0PM.l00-lll (') o 3: 3: » z C en IORG [1] ORG (Origin) PAGE ORG-1 Associates a logical X-Y screen origin with a physical frame buffer address. TYPE Register Access Command ORG DPH,DPL WORD NUMBER Wn=3 COMMAND CODE hexadecimal notation 15 I0 0 0 0 10 0 1 0 0 10 0 0 0 10 0 0 0 I ($ 0 4 0 0) EXECUTION CYCLES Cn=8 COMMAND PARAMETERS 15 I 0 15 I I DPH 0 DPL I < DESCRIPTION> The ORG command must be issued to the ACRTC prior to graphic drawing: ORG defines the logical X-Y coordinate origin upon which all graphic drawing addresses are based and sets the screen number in which to draw. The DPH and DPL (Drawing Pointer High, Low) parameters establish the physical address in the frame buffer at which the origin is set. This physical address is composed of the following three components - DN (Screen Number) is a screen designator, DPAH, DPAL (Drawing Pointer Address High, Low) is a 20 bit address selecting one of 1 megawords in the frame buffer and DPD (Drawing Pointer Dot) specifies the bit field associated with the addressed logical pixel. The ORG command initializes the Drawing Pointer (DP) to the origin and clears the Current Pointer (CPI. 174 HITACHI " .~ IORG ORG (Origin) PAGE ORG-2 OP: ON: 151413 oN I 87 0 OPAL (12 bits) lDPD (4 bits) 0-0 I OPAH (8 bits) ON Screen Number 00 Upper Screen 01 Base Screen OPH (16 bits) 10 Lower Screen OPL (16 bits) 11 Window Screen J • The origin address of the X-Y coordinates is set with the 20-bit linear address using to OPAH and OPAL. • OPO determines the dot position in 16-bit data addressed by OPAH/OPAL. • ON sets screen number for drawing. Figure C 1 -1 ORG HITACHI 175 IORG ORG (Origin) PAGE ORG-3 The origin for the Upper screen (screen number 0) is set to bit position 4- 7 at frame buffer word address $25. 4 bits per logical pixel and Memory Width (MW) $1 a are assumed. = COMMAND CODE a 15 100 a 010 1 0010 a a a /0 a 0a I ($ a 4 a 0) ($ a a a 0) a a aI ($ a 2 5 4) 7 9 COMMAND PARAMETERS a 15 Ia aa 010 a a 010 a a 010 a a 0/ 15 Ia a a a/a a 1 a/a 1 a 110 1 y o o 1 1 2 3 4 5 6 8 ABC D E F 1'1 II I I II 'I II , I II 1'1. I II I I II I I II I 'II I I I' I I I' , 'I" I I' , , I' I'll I' __________________ ~---------------------------------x Figure C1-2 ORG Execution Example 176 HITACHI rWPR [2] WPR (Write Parameter Register) PAGE WPR-1 Write the contents of the Drawing Parameter Registers. TYPE WPR (RN) D WORD NUMBER Wn=2 COMMAND CODE 15 1 0 0 0 011 0 0 010 0 Register Access Command hexadecimal notation 0 o!~ ==;== 5 bits ($ 0 8 0 X) EXECUTION CYCLES Cn=6 COMMAND PARAMETERS 15 0 - - - 1. I - - - -D-(Data) e- < DESCRIPTION> The Drawing Parameter Register number to be written is specified in the RN (Register Number) field of the op-code. The contents of the parameter (D) is written to the selected register. HITACHI 177 IWPR WPR (Write Parameter Register) PAGE WPR-2 The value $1111 is written to the CL 1 (Color 1) of the drawing parameter register. COMMAND CODE 15 0 1000011 000100010000 11 ($0801) COMMAND PARAMETERS 15 0 1000 11000 11000 11000 1 < Color Register> I ($1111) RN=Ol 1514131211109876543210 1000 11000 11 000 110 ~ Figure C2-1 WPR Execution Example 178 HITACHI I RPR [3] RPR (Read Parameter Register) PAGE RPR-1 Read the contents of the Drawing Parameter Registers. TYPE Register Access Command RPR (RN) WORD NUMBER Wn=1 COMMAND CODE hexadecimal notation 15 0 lii~_~~1o~E~~~ ($ 0 COX) EXECUTION CYCLES Cn=6 5 bits COMMAND PARAMETERS - NON- < DESCRIPTION> The Drawing Parameter Register number to be read is specified in the RN (Register Number) field of the command code. After execution, the contents of the specified Drawing Parameter Register is loaded into the Read FIFO. HITACHI 179 IRPR RPR (Read Parameter Register) PAGE RPR-2 < EXAMPLE> The value $1111 in the Drawing Parameter Register (Color Register 1: CL 1) is loaded into the Read FIFO. COMMAND CODE 15 I0 0 i 0 0 011 1 0 0 [0 0 0 0 0 0 0 1 I ($ 0 COl) COMMAND PARAMETER - NON< Color Register 1 > 0 15 1000 11000 11000 11 0- DO}] 15 1 000 11 0 0 0 ?_~§ ?_!Jii~iJ Figure C3-1 RPR Execution Example 180 HITACHI IWPTN [4] WPTN (Write Pattern RAM) PAGE WPTN-1 Write data to the Pattern RAM. TYPE WPTN (PRA) n, 01, 02, ... On WORD NUMBER Wn=n+2 COMMAND CODE 15 10 0 0 111 0 0 0 Register Access Command hexadecimal notation leo 0 01 PRA 0 ($ 1 80 X) I EXECUTION CYCLES Cn=4n+8 COMMAND PARAMETERS 0 15 'rl---n-(N-u-m-b-e-r-o-f-w-o-r-d-s)---I 0 15 rl---D-1-(-P-att-e-r-n-D-a-t-a)---.1 15 I--~[)-n-(Pattern Data) I 0 < DESCRIPTION> WPTN command is used to write data into the Pattem KAIVl. Pattern RAM Address (PRA) of $O-$F is allocated to the Pattern RAM and each PRA represents 1 word (1 6 bits) of pattern RAM. The PRA (Pattern RAM Address) field of the command code selects the Pattern RAM wordaddress at which writing starts. The first parameter is n, the number of words to be written. This is followed by n data words (D1-Dnl. For the 8-bit interface, 1 word is divided into high and low bytes. The pattem data is sent in the order of the high byte, then the low byte. The first parameter n must be set to (the number of words) x 2. (In this case writing in unit of byte is not allowed.) HITACHI 181 IWPTN WPTN (Write Pattern RAM) PAGE WPTN-2 Two words of data, $2314 and $5713, are written to the Pattern RAM beginning at address $B. COMMAND CODE 0 15 TTl 1000 111 0001000 011 0 COMMAND PARAMETERS 15 ($ 1 80 B) 0 I0 0 0 0 10 0 0 0 I0 0 :ii[O 0 1 0 I ($ 0 0 0 2) 0 15 liQj-.9lQij ~o=o] 110 0 0 0 15 @iiil~_l__~_-~l~_~? 1_~ 0 1 1 ($ 2 3 1 4) I ($ 5 7 1 3) bit o.------..., 15 15 Pattern RAM 0f--_ _ _ _~ LSB I I I I I I I 15 14 13 12 1 1 0 0 1 0 0 0 1 1 1 0 1 0 1 0 11 0 0 1 0 1 0 0 o 1 0 o 0 1 0 0 10 1 . Figure C4-1 WPTN Execution Example 182 HITACHI rRPTN [5] RPTN (Read Pattern RAM) PAGE RPTN-1 TYPE Register Access Command Read Data from the Pattern RAM. RPTN (PRA) n WORD NUMBER Wn=2 hexadecimal notation COMMAND CODE 15 [ 0 0 0 1 [1 1 0 0 10 0 0 01 0 PRA 1 ($ 1 COX) EXECUTION CYCLES Cn=4n+ 10 COMMAND PARAMETERS 15 o rl-------n--(N-u-m--be--r-o-f-w--or-d-)----~I < DESCRIPTION> RPTN command is used to read the data ih the Pattern RAM. Pattem RAM address (PRA) of $O-$F is allocated to the Pattern RAM and each PRA represents 1 word (1 6 bits) of Pattern RAM. The PRA (Pattern RAM Address) field of the command code select the Pattern RAM word address at which reading starts. The parameter n specifies the number of words to be read. The specified Pattern RAM contents are loaded into the Read FIFO. For the 8 bit interface, 1 word of the pattern RAM is divided into high and the low bytes. The pattern data is put into the Read FIFO in the order of the high byte, the low byte. HITACHI 183 IRPTN RPTN (Read Pattern RAM) PAGE RPTN-2 Two words of data. $2314 and $5713 from the Pattem RAM beginning from address $B is placed in the Read FIFO. COMMAND CODE 15 0 I ($ 1 COB) I ($ 0 0 0 2) oJ 1 1 1 011 0 1 0 01 1 1 0 010 1 0 0 1 0 0 0 111 1 0 010 0 0 01 1 0 1 1 COMMAND PARAMETERS 15 I0 0 0 _9l? 0 0 o.~O 0 01 0 0 0 1 0 bit o 15 15 en en ~ Pattern I RAM "0 "0 « 15 14 13 12 11 1 0 1 0 0 1 o 11 o 11 0 0 0 0 10 Read FIFO ~ ~ Figure C5-1 RPTN Execution Example 184 HITACHI lORD [6] ORO (OMA Read) PAGE ORO-1 Transfer data from the frame buffer to the MPU system memory. TYPE ORO AX, AY WORD NUMBER Wn=3 hexadecimal notation COMMAND CODE 15 oB o 15 ($ 2 4 0 0) Cn= (4x+ 8)y+ 12 [X~y rJ +(62-68) COMMAND PARAMETERS 15 EXECUTION CYCLES 0 100 1 010 1 0010000100 Ir--- Data Transfer Command AX x=IAXI+1 y=IAYI+1 0 ~I------~-A_Y_~~.~____~I < DESCRIPTION> ORO command causes the ACRTC to enter DMA Data Transfer Mode in which the ACRTC will control the external DMAC to transfer data (in unit of words) from the rectangular area in the frame buffer to the MPU memory. The frame buffer data origin must be predefined in the Read Write Pointer (RWP). The parameters of the command define the frame buffer area to be read in units of physical frame buffer words. At the end of ORO command execution, RWP will be set to RWPe. HITACHI 185 ORO ORO (DMA Read) PAGE DRD-2 Read FIFO RWP CPU Memory ACRTC Frame Buffer • If minus values are set in AX and A Y, the read direction becomes negative. The status of the ACRTC Read FIFO should be checked to insure the Read FIFO is empty before the ORO command is issued. If any data is in the Read FIFO before the ORO command issued, that data is read out incorrectly by the DMAC as the first data of the ORO command. Reading direction (1) X:+,Y:+ 186 HITACHI (2) X:+, Y:- (3) X:-, Y:+ (4) X:-, Y:- IOWT [7] OWT (OMA Write) PAGE OWT-1 < FUNCTION> Transfer data from the MPU system memory to the frame buffer. TYPE DWT AX, AY Data Transfer Command WORD NUMBER Wn=3 COMMAND CODE 15 hexadecimal notation 0 100101100010000100iiJ ($2800) EXECUTION CYCLES Cn=(4x+R)y-i- 16 [X; I] +34 COMMAND PARAMETERS 15 0 I~-------~A~X~ { I X = lAX I + 1 y=IAyl+1 ------------' < DESCRIPTION> DWT command causes the ACRTC to enter DMA Data Transfer Mode in which the ACRTC will control the external DMAC to transfer data (in unit of words) frorn the MPU memory to the rectangular area in the frame buffer. The frame buffer data origin must be predefined in the Read Write Pointer (RWP). The parameters of the command (AX, A Yl define the frame buffer area to be written in units of physical frame buffer words. At the end of DWT command execution, RWP will be set to RWPe. HITACHI 187 DWT DWT (DMA Write) PAGE DWT-2 Write FIFO AY+l AX+l RWP ACRTC Frame Buffer • For AX and A Y, negative value can also be set. After DWT is issued, no further commands should be issued until the DMA data is transferred and the DWT command terminates. Writing direction (1) X:+, Y:+ 188 HITACHI (2) X:+, Y:- (3) X:-, Y:+ (4) X:-, Y:- IOMOO [8] OMOD (OMA Modify) PAGE OMOO-1 < FUNCTION> Transfer data from the MPU system memory to the frame buffer subject to logical modification. Data Transfer Command TYPE DMOD (MM) AX. A Y COMMAND CODE 15 0 @.i 1 0l~ 1,~~~~_,O-o_oE9~~ hexadecimal notation WORD NUMBER Wn=3 EXECUTION CYCLES ($ 2 COX) Cn= (4x+ 8)y+ 16 C-, 1] +34 COMMAND PARAMETERS 15 [~ 0 -----AX-----~ { = lAX I + 1 y=IAyl+1 X < DESCRIPTION> DMOD causes the ACRTC to enter DMA Data Transfer Mode in which the ACRTC will control the external DMAC to modify data in the rectangular area in the frame buffer using data in the MPU memory (in unit of words!. The frame buffer data origin must be predefined in the Read Write Pointer (RWP!. The parameters of the command (AX. A Y) define the frame buffer area to be written in units of physical frame buffer words. At the end of DMOD command execution. RWP will be set to RWPe. The MM (Modify Mode) field of the command code specifies the DMA data transfer modify mode. Each pixel transferred from MPU system memory is logically operated on the corresponding pixel from the frame buffer. and the result is rewritten to the frame buffer. Logic operation can be enabled and disabled on a bit by bit basis based on the contents of the MASK register. HITACHI 189 OMOO OMOO (OMA Modify) PAGE OMOO-2 AY+l RWP Systp.m Mp.mory ACRTC Frame Buffer Afrer DMOD is issued, no further commands should be issued until the DMA data is transferred and the DMOD command terminates. 190 HITACHI IRD [9] RD (Read) PAGE RD-1 TYPE Data Transfer Command Read one word of data from the frame buffer and load the word into Read FIFO. RD WORD NUMBER Wn=1 COMMAND CODE 15 hexadecimal notation 0 [0100[01001~~_019_~~J ($4400) EXECUTION CYCLES Cn=12 COMMAND PARAMETER - NON- < DESCRIPTION> RD reads one word (16 bits) of data from the frame buffer. The frame buffer address to be read must be predefined in the Read Write Pointer (RWP) before the RD command is issued. The results are loaded into the Read FIFO. The result may be read from the Read FIFO by the MPU anytime after the RD command is issued. If the Read FIFO is full when the command is executed. the ACRTC will enter a wait state until space becomes available in the Read FIFO. At the end of the RD command execution, the ACRTC increments RWP by one. , HITACHI 191 IRD PAGE RD-2 RD (Read) DN: RWP: DN 1514 D N Screen Number 0 RWPH (8 bits) RWPL (12 bits) 00 Upper Screen 01 r----- .1 I~ II Base Screen DATA H (16 bits) 10 Lower Screen DATA L (16 bits) 11 Window Screen • RWPH and RWPL specifies the frame buffer address by setting the linear address of 20 bits. • DN specifies screen numbers. Figure C9-' RWP Set Read the frame buffer data, $5555, at physical address $56 in screen 0 (upper screen). For this example, Memory Width (MW) is assumed to be $10. RWP 0 15 I0 0 0 0 10 0 0 0 I0 0 0 0 10 0 0 0 I 0 15 10 0 0 0 10 1 0 1 101 1 010 0 0 0 ($ 0 0 0 0) I ($ 0 5 6 0) Figure C9-2 Example of RWP Setting COMMAND CODE 15 0 10 1 0 010 1 0 010 0 0 010 0 0 0 COMMAND PARAMETERS - NON- 192 HITACHI I ($ 4 4 0 0) IRD RD (Read) Screen: 0 PAGE RD-3 ~ 1 2 3 4 5 6 7 8 9 A B C 0 E F 0 1 2 3 4 RWP .. ~ D- RWPe (after execution) 5 6 (address $56) Frame buffer data 7 o1 8 9 0 li' 1jo 1 0 110 1 0 110 1 0 1 D A ($5555) Read FIFO 15 B_ o1 0 0 1 0 1 0 10 1 0 10 1 o1 ($5555) T_ Figure C9-3 RD Execution Example HITACHI 193 [10] WT (Write) PAGE WT-1 < FUNCTION> Write one word of data to the frame buffer. TYPE WT D WORD NUMBER Wn=2 hexadecimal notation COMMAND CODE 15 0 [0100[1 Data Transfer Command ooo[ooooIoooo I ($4800) EXECUTION CYCLES Cn=8 COMMAND PARAMETERS 15 ~-. L_~ D (16 bits) 0 ~ ____ ~_______ ,_, __ ,______________ ~ < DESCRIPTION> WT writes one word (16 bits) of data to the frame buffer. The frame buffer address to be written must be predefined in the Read Write Pointer (RWP) before the WT command is issued. The command parameter (D) is the data to be written. At the end of the WT command execution, the AeRTC increments the RWP by one. 194 HITACHI WT (Write) PAGE WT-2 ON: RWP ~~~reen Number .._ 00 ~.- ----- 01 Base Screen 10 Lower Screen 11 Window Screen rI- I 0 N r_______ J RWPH (8 bits) I Upper Screen ._.- 15 RWPL (12 bits) I I - - . - - - - -.. - - - - - - - . . , 0 I~ DATA L (16 bits) • The frame memory is a 20-bit lineflr address separated into highorder RWPH (8 bits) and loworder RWPL (12 bits). • Specify the Screen No. where drawing is executed. Figure C 10-1 RWP Set < EXAMPLE> Write the 16-bit data word $5555 to frame buffer address $56 on screen 0 (upper screen). For this example. Memory Width (MW) is assumed to be $10. RWP 15 0 I 0 o~_~_~~~~_olo 0 0 0 15 I ($ 0 0 0 0) I ($ 0560) 0 [(}-oo-~~ 0 __1E1 1 010000 Figure C10-2 Example of RWP Setting COMMAND CODE 15 100ooT'---ooo~ 0 I0 0 0 0 0 I ($ 4 8 00) COMMAND PARAMETERS 15 0 [O!-o!]01-0'-@ 101J~iJ ($ 5 5 5 5) HITACHI 195 IWT WT (Write) 0 PAGE WT-3 1 2 3 4 5 6 7 8 9 A B C 0 E F 0 1 2 3 4 5 RWP (Address 56) .. ~ D- RWPe (after execution) 6 7 8 9 1010101 01010101 o I ~, A Figure C10-3 WT Execution Example 196 HITACHI , 1 ($5555) - , IMOD [11] MOD (Modify) PAGE MOD-1 Perform logical operation on one word in the frame buffer. TYPE MOD (MM) D < FORMAT> WORD NUMBER Wn=2 COMMAND CODE 15 Data Transfer Command hexadecimal notation 21 a 1 a 1 a a 11 1 -oy]a a a a a aiM M 1 ($ 4 C a X) EXECUTION CYCLES Cn=8 COMMAND PARAMETER 15 a L'_-_--__-_-_~~~-?-_-~~-6-b-it-s-)--------~1 < DESCRIPTION> The MM (Modify Mode) field of the command code specifies the data transfer modify mode. This command performs logical operation on one word in the frame buffer with the data given the parameter and writes the result back in the frame buffer. The frame buffer word address to be modified must be predefined in the Read Write Pointer (RWP). The word is read from the frame buffer, then the logical operation defined by MM is performed between the data read from the frame buffer and the command parameter (D) for those bits not masked in the MASK register, and the result is rewritten to the frame buffer. At the end of the MOD command execution, the ACRTC increments the RWP by one. HJ-TACHI197 /MOO MOD (Modify) DN: PAGE MOO-2 RWP: DN Screen Number 00 Upper Screen 01 Base Screen 1514 I I DN 7 0 r ____ I RWPH (8 bits) RWPL (12 bits) ~ 10 Lower Screen 11 Window Screen • The frame buffer 20-bit linear address is separated into high order RWPH (8 bits) and loworder RWPL (12 bits). • Specify the Screen No. where drawing is executed. Figure C11-1 RWP Set OR all bits of the frame buffer word at physical address $56 with the 16-bit data word $AAAA. MM = 01 specifies OR modify mode. All bits are selected for logical operation byassuming the MASK register to $FFFF. For this example, Memory Width (MW) is assumed to be $10. 198 HITACHI IMOD MOD (Modify) < EXECUTION PAGE MOD-3 EXAMPLE> RWP 15 0 100001000010000100001 ($0000) 0 15 I I 10 0 0 0 0 1 0 11 0 1 1 0 0 0 0 0 I ($ 0 5 6 0) MASK 0 15 [11111111111111[11111 ($FFFF) Figure C11-2 Examples of RWP and MASK Setting COMMAND CODE 15 I 0 i . 10 1 0 0 11 1 0 0 0 0 0 0 0 0 0 1 I ($ 4 C 0 1) I ($ A A AAI COMMAND PARAMETER 15 0 ~1 011 0 1 011 0 1 011 0 1 0 HITACHI 199 IMOD MOD (Modify) 0 PAGE MOD-4 1 2 3 4 6 5 7 8 9 A B C D E F 0 1 10 1 0 110 1 2 .. ~! 3 4 o 110 1 0 110 1 0 11 ($5555) RWP 5 6 (A) MOD Command Read Cycle 0 1 2 3 4 5 6 7 8 9 A B C 1 1 '1' 1 1 '1' D E 1 2 j l' ~ 3 4 1 1 .. D- 5 '1' ($FFFF) RWPe (After execution) 6 (8) MOD Command Write Cycle Figure C11-3 MOD Execution Example '. 20(}.·HITACHI 1 1 11 F ICLR [12] CLR (Clear) PAGE CLR-1 < FUNCTION> Initialize a frame buffer area with a data in the command parameter. TYPE CLR D, AX, AY Data Transfer Command WORD NUMBER Wn=4 COMMAND CODE hexadecimal notation 15 0 [0 1 0 1 [1 000100 0 oE~ { COMMAND PARAMETERS 15 ($ 5 800) EXECUTION CYCLES Cn= (2x+ 8)y+ 12 X=\AX\+1 y=\AY\+1 0 I D (16 bits) I AX (16 bits) 15 I 0 15 I 0 [ AY (16 bits) I < DESCRIPTION> The frame buffer area defined by the physical origin (RWP) and physical frame buffer word address (AX and A Y) parameters is filled with the data parameter (D). Since the ACRTC performs the clear using 16 bit words, multiple logical pixels (if 4 bits/ pixel then 4 pixels) are cleared in one access. D is normally specified to contain multiple copies (if 4 bits/pixel then 4 copies) of the color information for a single color clear. At the end of CLR command execution, RWP will be set to RWPe. HITACHI 201 ICLR CLR (Clear) PAGE CLR-2 y AX: 2nd parameter A Y: 3rd parameter (4-bits/pixel) (AX,AY) 1\ AY+l I r----- RWP X AX+l ----------- U RWPe \ I I I I I) I RWP is set with a 2-word (32-bit) data, as shown in Fig. C12-1. RWP The RWP needs to be specified in advance as follows. 202 HITACHI ICLR CLR (Clear) PAGE CLR-3 ON: RWP: 15 14 ON Screen Number 00 Upper Screen 01 Base Screen 10 i 11 7 0 o N I ____________ JRWPH (8 bits) RWPL (12 bits) I~ Lower Screen Window Screen • The frame buffer 20-bit linear address is separated into high order RWPH (8 bits) and low order RWPL (12 bits) . • Specify the Screen No. where drawing is executed. Figure C12-l RWP Set For this example 4 bits per logical pixel is used, the Memory Width (MW) is $10 and the clear operation is to start at address $56 on screen O. RWP 15 0 10 0 0 010 0 0 010 0 0 0 0 0 0 0 I 15 ($ 0000) 0 1000010 1 0 11 0 1 1 01 0000 1 ($ 0 5 60) Figure C12-2 Example of RWP Setting COMMAND CODE 15 0 io 1011100010000100001 ($ 5 800) COMMAND PARAMETERS 15 rooo 0 ,1 0 0 0 '10 0 0 11 000 ($ 1 1 1 1) 0 '5 E-' I' 11 l-t}I11 _1 1 [ 1 1 001 15 ($ F F F C) 0 ~-----~- 1_1_~_' 1 1 1 1 1 1 11 o1 01 ($ F F FA) HITACHI 203 ICLR CLR (Clear) PAGE CLR-4 1000 11 = Clear data (pixel) o 2 3 4 5 6 7 8 9 A 8 o 1 2 3 4 5 words r,....--~A'-_ _----..\ RWP (Address $56) 5 0001000100010001~ 6 00010001000100010001 7 00010001000100010001 8 00010001000100010001 9 000100010001000100P1 A 00010001000100010001 8 ~0001000100010001 Pc (address $82) 7 words L..: I - RWPe (Address $86) Figure C12-3 CLR Execution Example 204 HITACHI C 0 E iSCLR [13] SCLR (Selective Clear) PAGE SCLR-1 TYPE Data Transfer Command Initialize a frame buffer area with a constant value subject to logical modification. SCLR (MM) D, AX, A Y WORD NUMBER Wn=4 COMMAND CODE hexadecimal notation 15 0 1 0 1 0 1 11 1 00100-00TO_~M M 1 { COMMAND PARAMETERS 15 L _._- X = lAX + 1 y=IAYI+l I. 0 -------~--. D (16 bits) 1 ---- 0 15 AX (16 bits) I ($ 5 COX) EXECUTION CYCLES Cn= (4x+ 6)y+ 1 2 1 --- 0 15 ------ 1 AY (16 bits) I < DESCRIPTION> The MM (Modify Mode) field of the command code specifies the data transfer modify mode. The frame buffer area defined by the RWP origin and the physical frame buffer word address (AX and A Y) parameters is selectively cleared. The contents of the frame buffer are read, and that data is logically operated on with the D parameter (excepts bits masked in the MASK register) using the logical operation defined by MM. The result is rewritten to the frame buffer. Since the ACRTC performs the selective clear using 16-bit words, multiple logical pixels (if 4 bits/pixel then 4 pixels) are cleared in one access. D is normally specified to contain multiple copies (if 4 bits/pixel then 4 copies) of the color information for a single color selective clear. At the end of SCLR command execution, RWP will be set to RWPe. HITACHI 205 ISCLR SCLR (Selective Clear) PAGE SCLR-2 < DESCRIPTION> 0 0000 2. 4 Rwpe-I : Modifier information : 1st parameter : 2nd parameter}. In : 3rd parameter . f d Units 0 wor s 1 00000000100001- Pc 000000000000 000000000000 000000000000 Address location - - - " 10000100000000 specified by RWP. -- '------'"' ~ ---------- Figure C13-l Command Parameter Set The operation is specified by the above operation mode, and is set with bits 1, 0 in the command code. This command can be utilized for clearing the character code, the specific attribute bits, and the specific color plane in the graphic display. The RWP needs to be specified in advance as follows. RWP DN: 15 DN Screen Number 00 Upper Screen 01 Base Screen 10 Lower Screen 11 Window Screen ,..--' 14 DN 7 J __________ J RWPH (8 bits) RWPL (12 bits) 0 I~ • The frame memory is a 20-bit linear address separated into high order RWPH (8 bits) and low order RWPL (12 bits). • Specify the Screen No. where drawing is executed. Figure C13-2 RWP Set 206 HITACHI ISCLR SCLR (Selective Clear) PAGE SCLR-3 For this example 4 bits per logical pixel is used, the Memory Width (MW) is $10, the MASK register contains $FOFO and the selective clear operation is to start at address $56 on screen O. Based on MM, a logical operation (REPLACE, OR, AND or'EOR) is defined and SCLR is executed as shown, RWP 0 15 loo:ooloooolooooloooo[ ($ 0000) [000 0[0 1 0 1 [0 1 1 0[000 0 [ ($ 05 60) MASK 15 0 111111000011111100001 ($ F 0 F 0) Figure C13-3 Examples of RWP and MASK Setting Read Data o \ Modifier Data Read Data V t:. I V I \ MM MM t • Modifier Data + A Write Data Write Data (Unit: pixel) Figure C 1 3-4 Notation of Data HITACHI 207 lSCLR SCLR (Selective Clear) PAGE SCLR-4 < EXECUTION EXAMPLE> COMMAND CODE 15 0 101011110010000100!MMJ ($5COX) COMMAND PARAMETERS 15 0 10 0 0 110 0 0 110 0 0 110 0 0 1 15 I 0 11 1 1 1 11 1 1 1 11 1 1 11 1100 1 15 0 11 1 1 111 1 1 111 1 1 111 0 1 0 208 HITACHI ($ 1 1 1 1) I ($ F F F C) ($ F F FA)· SCLR SCLR (Selective Clear) < EXECUTION PAGE SCLR-5 EXAMPLE> 1 pixel 1st I 000 1 I =" (Modifier data) o o - 4 3 2 parameter (Mod ifier Data) ($1111) 5 = I"V'''''I 6 1 1 Mask 1 2 RWP (Address $56) 3 5 4 1 words 5 oooooooooooooooc~.oo~"' 6 00000000000000000000 1 MM 1 7 8 OOOb~A~~~~~AAAA~~OOO 9 OOO~~A~AAAAAAAAAAOOO A 00000000000000000000 B Pc (Address--jO 00 0 0 0 0 00000000000 7 words 010 ($B2)· - C (A) o 2 3 4 6 5 o 1 2 3 4 5 eoeoeoeoeoeoeoeo~oeCjI4----' 6 eoeoeo.o.o.O.O.O.O.O 7 .0.b.A.~.A.~.A.~AO.0 8 .0.A.A.b.A.~.AA~.0.0 9 .O.A.AAA.~AAAA.~.O.O A .0eo.0.0.0.O.O.O.O.0 .0.0.0.0.0.0.0.0.0.0 B C 1 !-RWPe (Address $C6) (B) Figure C13-5 SCLR Execution Example HITACHI 209 ICPY [14] Cpy (Copy) PAGE CPY-1 Copy frame buffer data from one area (source area) to another area (destination area). CPY (S, OS D) SAH, SAL, AX, A Y hexadecimal notation 12111087 0 10110lsIDSDIOOOOIOOOOI COMMAND PARAMETERS 15 87 1000000001 SAH (8 bits) SAL (1 2 bits) Jx = lAX 1+ tv = IAyl+ 1 1 I 10000 1 0 I AX (16 bits) 15 I EXECUTION CYCLES Cn= (6x+ 1O)y+ 12 0 15 I ($ 6 X 0 0) 0 15 1 Data Transfer Command WORD NUMBER Wn=5 COMMAND CODE 15 TYPE 0 AY (16 bits) I < DESCRIPTION> The parameters to the command define the source area. The RWP must be predefined to point to the destination area (including screen number). The source area resides in the same screen as that of the destination area as defined in RWP. The source area is defined by the origin address (SAH/SAL) and physical frame buffer word (AX and A Y) dimensions. To allow rotation and proper operation for overlapping during copying, the command code contains fields which define the source and destination scanning direction. The S (Source Scan Direction) and DSD (Destination Scan Direction) fields of the command code define the source and destination scanning direction respectively as shown next page. At the end of the CPY command, RWP is set to RWPe. 210 HITACHI ICpy Cpy (Copy) PAGE CPY-2 Pss: 0 15 ~~-----------.----------~ ------ I SAL (12 bits) (1) SAH (8 bits) I r~1 Pss (SAH, SAL) is set to be a 20-bit linear address separated into 2 words, high order SAH (8 bits) and low order SAL (12 bits). DN: RWP: 15 DN Screen Number 00 Upper Screen 01 Base Screen 10 Lower Screen 11 Window Screen 14 I D N I r_________ 7 .1 0 RWPH (8 bits) 1 RWPL (12 bits) I~ The frame buffer 20-bit linear address is separated into high order RWPH (8 bits) and low order RWPL (12 bits). Specify the Screen No. where drawing is executed. Figure C14-1 Pss and RWP Set HITACHI 211 Icpy Cpy (CoPY) PAGE CPY-3 < CPY Command Scan Direction> As to CPY, the direction of pointer scanning is specified in command code. (The pOinter functions in the unit of word). (a) Scanning Direction of Source Area (S: Source Scan Direction) COMMAND CODE 15 11 ~~_~~_L 0 1 Talbe C14-1 Source Scan Direction s=o 8 IT) b2d [TI ill ill ill ill S = 1 - : Pss o : Pse As shown in Table C 14- 1, the scanning direction in frame buffer of the copy source area is decided by the relation between bit 11 in the command code and the Pss and the Pse. (a) Scanning Direction of Destination Area (DSD: Destination Scan Direction) COMMAND CODE 15 1098 [ ID S DI 0 1 , 212 HITACHI Icpy CPY (Copy) PAGE CPY-4 Table C14-2 Destination Scan Direction DSD = 000 DSD D DSD DSD DSD = all ld LB CJ 100 = 010 D IT] ~ DSD - = 001 0 = 101 DSD = 110 DSD = 111 ItllITElBJ _ : RWP D : RWPe As shown in Table C14-2. the scanning direction in frame buffer of the destination area is decided by the relation between bit 10 to 8 in the command code and the RWP. Upon termination of the command, RWPe, end point of the RWP moves as shown in Table C14-2. Relation to Linear Address Fig. C 14-2 provides the relation between CPY and specified value when S = 1 and DSD = 000. RWPe (Linear Address) I Pse (Linear Address) [RWPHIRWPLI-l AXxMWI-~1 ~ II SAH I SAL _~jij I For this example 4 bits per logical pixel is used, the Memory Width (MW) is $10 and the copy operation source area (SAH/SAL) start is frame buffer address $89 while the copy destination area (RWP) start is frame buffer address $BO on screen O. The source area scanning direction is specified as S = 1 and the destination area scanning direction is specified as DSD = 000. RWP 15 0 [00:0 0[0 _~~_iJ_o I ($0000) 0 1 1 [0000[0000 I ($ 0 BOO) 0 0 0[0 0 0 0 15 0 ro-o~'- Figure C14-3 Example of Read Write Pointer Setting COMMAND CODE 0 15 I0 I ($ 6 8 0 0) o-DJ ($ 0 0 00) 1 1 0 11 10 0 0 10 0 0 0 [0 0 0 0 COMMAND PARAMETERS 15 10 0 0 010 0 0 010 0 0 010 0 15 0 0 I ($ 0 8 9 0) \ 0 0 0 0 \0 0 0 010 0 0 0 \0 0 1 1 \ ($ 0 0 0 3) 10 0 0 011 0 0 011 0 0 1 [0 0 0 0 15 15 0 0 10000[000010000[01101 214 HITACHI ($0006) Cpy Cpy (Copy) 0 PAGE CPY-6 1 3 2 4 5 6 7 8 9 A B 0 1 2 3 4 5 6 • • • • • • • • 0000 • • • • • • • • 00000000 • • • • • • • • 0000 7 8 9 A (A) B 0 1 3 2 5 4 6 7 8 9 A C B 0 1 Pse (Address $2C) 2 ~ 3 Ie··· pooo •••• •••• Ie ••• 10000 Iooo~ 4 5 6 ~pe (Address $70) •••• Ie ••• Ioooc 7 8 9 A B t1 ...---- 0000 ~ t"7l / Pss (Address $89) roooo oooc 00001 I•••• •••• • •••1 RWP (Address $BO) (B) Figure C14-4 Example of CPY Execution HITACHI 215 I [15] SCPY (Selective Copy) SCpy PAGE SCPY-1 Copy frame buffer data from one area (source area) to another area (destination area) subject to logical modification. The source and destination areas must reside on the same screen. TYPE Data Transfer Command SCPY(S.DSD.MM)SAH.SAL.AX.AY COMMAND CODE 15 111087 210 10 1 1 1 IslD S Dlo 0 0 0 0 O!MM! I0 0 I 0 0 0 0 0 05>[' SAH (8 bits) WORD NUMBER Wn=5 ($7XOX) EXECUTION CYCLES Cn= (6x+ 1O)y+ 12 COMMAND PARAMETERS 15 hexadecimal notation { X=IAXI+1 y= IAYI+ 1 0 15 c==r----S-~-~_-(1-2-b-its-)--~[-0-0-0-0~! 0 15 . r - - - [- I - AX (16 bits) 15 0 1=~~~~-_-____-A==Y=(=16==b=it=S)========~1 < DESCRIPTION> The parameters to the command define the source area. The RWP must be predefined to point to the destination area (including screen numbed. The source area resides in the same screen as that of the destination area as defined in RWP. The source area is defined by the origin address (SAH/SAL) and physical frame buffer word (AX and A Y) dimensions. To allow rotation and proper operation for overlapping during copying. the command code contains fields which define the source and destination scanning direction. The S (Source Scan Direction) and DSD (Destination Scan Direction) fields of the command code define the source and destination scanning direction respectively as shown next page. The MM (Modify Mode) field of the command code specifies the data transfer modify mode. l3ased on MM. logical operation is performed (except for bits masked in the MASK register) between the source data and the destination data. and the result is written to the destination. At the end of the CPY command. RWP is set to RWPe. 216 HITACHI I SCpy SCPY (Selective Copy) PAGE SCPY-2 The source address and Read/Write Pointer need to be specified as follows prior to the execution. Pss: 15 r-=: ______ ::----_____ - - - -~TSAH o I~ SAL (12 bits) (1) (8 bits) Pss (SAH, SAL) is set to be a 20-bit linear address separated into 2 words, high order SAH (8 bits) and low order SAL (12 bits!. DN: RWP: 15 DN Screen Number 00 Upper Screen ·01 14 7 0 lD N 1 ----------- IRWPH (8 bits) I~ I RWPL (12 bits) Base Screen 10 Lower Screen 11 Window Screen The frame buffer 20-bit linear address is separated into high order RWPH (8 bits) and low order RWPL (12 bits!. Specify the Screen No. where drawing is executed. Figure C15-1 Psi; and RWP Set HITACHI 217 ISCpy PAGE SCPY-3 SCpy (Selective Copy) < SCPY Command Scan Direction> As to SCPY, the direction of pointer scanning is specified in command code. (The pointer functions in the unit of word) (a) Scanning Direction of Source Area (S: Source Scan Direction) COMMAND CODE 15 I 11 IS I 0 ~ Table C15-1 Source Scan Direction s=o 8 ETI ~ EJ ill ill EI1 EIJ S = 1 _ : Pss D : Pse As shown in Table C15-1, the scanning direction in frame buffer of the copy source area is decided by the relation between bit 11 in the command code and the Pss and the Pse. 218 HITACHI Iscpy SCpy (Selective Copy) (b) PAGE SCPY-4 Scanning Direction of Destination Area (DSD: Destination Scan Direction) COMMAND CODE 10 9 8 15 10 1 0 SOl 1 Table C15-2 Destination Scan Direction DSD - 000 DSD = 001 DSD 0 0 Lld EJ ~ D DSD = 100 DSD = = 010 101 DSD = 110 DSD = 011 Ej 0 DSD - 111 ill TEJ Ell tIT I I o : RWPe • :RWP As shown in Table C15-2, the scanning direction in frame buffer of the destination area is decided by the relation between bit 10 to 8 in the com.mand code and the RWP. Upon termination of the command, RWPe, end point of the RWP moves as shown in Table C15-2. The operation is decided by the modify mode (MM) and is specified by bit "0" or "1" in the command code. HITACHI 219 ISCPY SCPY (Selective Copy) PAGE SCPY-5 Relation to Linear Address Fig. C15-2 provides the relation between SCPY and specified value when S = 1 and DSD = 000. Pse (Linear Address) \I SAil I SAL 1+ [IK] -I f L]fAY+ll IAX+ll 1IIIr---.../"o-...-----., ,---'l , ImvPllllWPL J ~ 1 SAil 1SALI\ Pss (Linear Address) II IllY!' ( LI near Address) Read Data Modifier Data ~ ~ \ I / M M I I III Write Data RWPe (Linear Address) IIRWPIIIRWPLI-I AXx~fW 1- ~I f Figure C15-2 Relations with Linear Addresses 220 HITACHI AYXMW.II \SCpy SCpy (Selective Copy) PAGE SCPY-6 For this example 4 bits per logical pixel is used, the Memory Width (MW) is $10, the MASK register contains $FOFO and the copy operation source area (SAH/SAL) start is frame buffer address $85 while the copy destination area (RWP) start is frame buffer address $80 on screen O. The source area scanning direction is specified as S 1 and the destination area scanning direction is specified as DSD 000. = = RWP 0 15 10 010 0 0 0 0010 0 0010000 I ($ 0000) I ($ 0 BOO) 0 15 10 0 0 0 11 0 1 1 10 0 0 0 10 0 0 0 MASK 0 15 11 1 1 11000011 1 1 1100001 ($ F 0 F 0) Figure C15-3 RWP and MASK Setting Read Data Modifier Data o V' "• MM Modifier Data Read Data V' /' /' MM I Write Data A (Unit: pixel) Write Data Figure C15-4 Operation of SCPY HITACHI 221 ISCPY SCPY (Selective Copy) COMMAND CODE 15 PAGE SCPY-7 a 10 1 1 111! 0 0 0 10 0 0 0 0 0 1M COMMAND PARAMETERS 15 Mj 0 100001000010000100061 15 15 ~0 '5 10 0 0 0 222 HITACHI ($ 0000) 0 10000110001010'100001 10 0 0 0 ($ 78 OX) ~ ($ 0850) 0 0 010 0 0 010 0 0 11 ($0001) 0 0 0 010 0 0 010 1 1 01 ($ 0006) SCpy SCPY (Selective Copy) PAGE SCPY-8 o 2 5 4 3 6 7 o 1 2 3 4 VVVVVVVV 5 VVVVVVVVVVVV VVVVVVVV 6 7 8 9 A ~~~~oooo~~~~oooo~~~~oooo~~~~ B oooo~~~~oooo~~~~oooo~~~~oooo C I (A) o 2 3 4 5 0001 I II Before Execution of SCPY o 1 pixel V (modifier Data) 6 7 1st Parameter ($1111) $26) 1 II (Modifier Data) 2 3 4 5 6 7 8 RWPe (Address $90) ~ Pss (Address 9 A B C RWP (Address $BO) (B) After Execution of SCPY Figure C1S-S Example of SCPY Execution HITACHI 223 /AMOVE [16] AMOVE (Absolute Move) PAGE AMOVE-1 Move the Current Pointer (CP) to an absolute logical pixel X-Y address. TYPE AMOVE X, Y WORD NUMBER Wn=3 hexadecimal notation COMMAND CODE 15 11 Graphic Command 0 0 0 0 10 0 0 0 10 0 0 01 0 0 0 9 ($ 8 000) EXECUTION CYCLES Cn=56 COMMAND PARAMETERS 15 I 0 I X (16 bits) 15 I 0 I Y (16 bits) < DESCRIPTION> The parameters (X, y) of the AMOVE command specify the new value for the CPo The address is specified using logical pixel X-Y addresses relative to the origin defined by the ORG command. y Pe (X, Y) CP(A,It~///// /.fi~ ;y .... 1\ ORG( 0 , 0) lJB Y ) ---1E:/A:..o..=-''''''-~-x ------ X ------ Figure C16-1 Function of AMOVE Command 224 HITACHI IAMOVE AMOVE (Absolute Move) PAGE AMOVE-2 If CP (-13, -10) and AMOVE command is executed with parameters IX, Y) 2), then the CP is set to Pe as shown below. = = (10, COMMAND CODE 15 0 ($ 8 000) 11 0 0 0 10 0 0 0 10 0 0 0 10 0 0 01 COMMAND PARAMETERS 15 0 ($ 00 OA) 11 0 0 0 10 0 0 0 10 0 0 0 11 0 1 01 15 0 ($ 0002) 10 0 0 010 0 0 0100 0 010 0 1 01 y Pe(lO.2) ORG(O.O) ~2 ...... x Figure C16-2 Example of AMOVE Execution HITACHI 225 IRMOVE [17] RMOVE (Relative Move) PAGE RMOVE-1 Move the Current Pointer (CP) to a relative logical pixel X-V address. TYPE Graphic Command RMOVE dX, dY WORD NUMBER Wn=3 COMMAND CODE hexadecimal notation 0 15 ($ 8 400) 11 0 0 010 1 0 010 0 0 010 0 0 01 EXECUTION CYCLES Cn=56 COMMAND PARAMETERS 15 I 0 I dX (16 bits) 15 I 0 I dY (16 bitsl < DESCRIPTION> The parameters (dX, dY) of the RMOVE command are used to calcuiate the new value for the CP .. The address is specified using logical pixel X-Y displacements relative to CPo y Pe(A+dX, B+dY) \------- dX ~ B ORG(O,O) ".-A-.,) x Figure C17-1 Function of RMOVE 226 HITACHI IRMOVE RMOVE (Relative Move) PAGE RMOVE-2 If CP = (- 13, - 10) and RMOVE command is executed with parameters (X, Y) = (10, 2). then the CP is set to Pe as shown below. COMMAND CODE 15 0 ($ 8400) 11 0 0 0 10 1 0 0 10 0 0 0 10 0 0 01 COMMAND PARAMETERS 0 15 I0 0 0 0 10 0 0 0 10 0 0 0 11 0 1 01 dX ($ 0 0 0 A) 15 0 10 0 0 010 0 0 010 0 0 010 0 1 01 dY ($ 0 0 0 2) y ___________O_R_G_(_O_,O_)~~--------------X Pe(-3,-8) CP(-13,-lO) _~ ,,- ---.,..""'" lJ2 0<::::0= 10 ............... Figure C17-2 Example of RMOVE Execution HITACHI 227 IALINE [18] ALINE (Absolute Line) PAGE ALlNE-1 Draw a straight line from CP to a command specified end point. TYPE ALINE (AREA. COL. OPM) X. Y WORD NUMBER Wn=3 COMMAND CODE hexadecimal notation 87 15 11 0 0 0 COMM:~ND 11 54 32 I I I ($88XX) EXECUTION CYCLES Cn=P·L+ 18 PARAMETERS 0 X (16 bits) I 15 I 0 0 0 OIAREA COL OPM 15 I Graphic Command 0 I Y (16 bits) < DESCRIPTION> The parameters (X. Y) define the line end point as absolute logical pixel X-Y addresses relative to the origin defined with the ORG command. As the line is drawn. CP is moved to Pe. However. the logical pixel at position Pe is not drawn. y Pe(X. Y) Figure C18-1 Function of ALINE 228 HITACHI ALINE ALINE (Absolute Line) PAGE ALINE-2 If CP 13, - 10) and ALINE command is executed with parameters (X, Y) a line is drawn and CP is set to Pe as shown below. = (- = (10, 2), then COMMAND CODE 15 87 54 32 I I 0 ($ 8 8 XX) 11 0 0 011 0 0 01 AREA COL OPM 1 COMMAND PARAMETERS 0 15 10 0 0 010 0 0 01 0 0 0 011 0 1 01 X ($ 0 0 0 Al 15 0 10 0 0 01 0 0 0 01 0 0 0 01 0 0 1 01 Y ($ 0 0 0 2) y 2 -13 Pe(l0,2) x ORG(O,O) I I 10 1 I I I I I I I I , ep(-lB,-lO) - -10 Figure C18-2 Example of ALINE Execution HITACHI 229 IRLINE [19] RLiNE (Relative Line) PAGE RLlNE-1 Draw a straight line from CP to a command specified end point. TYPE RUNE (AREA, COL, OPM) dX, dY WORD NUMBER Wn=3 COMMAND CODE 15 Graphic Command hexadecimal notation 87 54 32 0 11 0001 1 1 0 OIAREA ICOl IOPMI ($8CXX) EXECUTION CYCLES Cn=P·l+ 18 COMMAND PARAMETERS 15.r-____________________~O I dX (16 bits) I 15 0 rl--------dY--(1-6-b--its-)------~1 < DESCRIPTION> The parameters (dX, dY) define the line end point as relative logical pixel X-Y displacements from the CPo As the line is drawn, CP is moved to Pe. However, the logical pixel at position Pe is not drawn. y Pe(A+dX. B+dY) ~~YII CP(A.~ ~B- - - - dX ------- II ORG( o. 0) --~~~~_-A~~~-----------------------x Figure C19-1 Function of RLiNE 230 HITACHI IRLINE RLiNE (Relative Line) PAGE RLlNE-2 < EXAMPLE> = (- If CP 13, - 10) and RUNE command is executed with parameters (dX, dY) then a line is drawn and CP is set to Pe as shown below. = (10, 2), COMMAND CODE 15 87 54 32 0 11000[110 O[AREAICOLI OPMI ($ 8 C XX) COMMAND PARAMETERS 0 15 1000010000100001101 01 15 ($ 00 OAI 0 1000010000100001001 01 ($ 0002) y -13 x -3 : I ORG(O,O) I .... I I I I .---.0-____ I -8 -~ ,~" Pe(-3,-S) ..:...-~-. . . _________________ -10 CP(-13.-10) Figure C19-2 Example of RUNE Execution HITACHI 231 /ARCT [20] ARCT (Absolute Rectangle) PAGE ARCT-1 < FUNCTION> Draw a rectangle defined by CP and the command specified diagonal point. TYPE Graphic Command ARCT \AREA, COL, OPM) X, Y WORD NUMBER Wn=3 COMMAND CODE 15 hexadecimal notation 8 7 5 4 3 2 11 0 0 110 0 0 olAREA 0 IcOL IOPM I ($ 9 0 X X) EXECUTION CYCLES Cn= 2p(A+ BH 54 COMMAND PARAMETERS 0 15 I I X (16 bits) 0 15 I Y (16 bits) I < DESCRIPTION> The parameters (X, Y) define the diagonal point of the rectangle as absolute logical pixel X-Y addresses relative to the origin defined by the ORG command. As the rectangle is drawn, CP is moved to Pe (which is the same as CP). However, the logical pixel at position Pe is not drawn. Drawing starts in the X direction first, and is drawn in the direction shown below. The initial X direction is determined by the relationship betwflen CP and (X, Y). Pc ~P(U) ex; Y/ 1\ Pe /i<[\'--------------1 (A,B) [\ B ORG(O,O) A )y I 1/ Figure C20-1 Function of ARCT 232 HITACHI ARCT (Absolute Polyline) PAGE ARCT-2 If CP = (6, - 6) and ACT command is executed with parameters (X, Y) = (- 16, 101. then a rectangle is drawn and CP is set to Pe as shown below. Drawing starts from the X-axis direction. COMMAND CODE 15 87 54 32 I I 0 11 0 0 11 0 0 0 01 AREA COL OPM I ($ 9 a XXI COMMAND PARAMETERS 15r-____r-____. -____~--~0 11 1 1 111 1 1 111 1 1 11 0 0 0 01 15 ($ F F Fa) 0 la a a al a a 0 al a a 0 all a 1 a\ ($ 00 OA) y Pc(-16.10) ~'f\ 10 x ORG(O,O) V PC (6.-6) ooee<~~:leE~**~~~~~P (6. -6) Figure C20-2 Example of ARCT Execution HITACHI 233 IRRCT [21] RRCT (Relative Rectangle) PAGE RRCT-1 Draw a rectangle defined by CP and the command specified diagonal point. TYPE Graphic Command RRCT (AREA. COL, OPM) dX, dY WORD NUMBER Wn=3 COMMAND CODE 15 hexadecimal notation 87 54 32 0 11 0 0 11 0 1 0 01 AREA 1COL 1 OPM 1 ($ 9 4 X X) EXECUTION CYCLES Cn=2P(A+B)+54 COMMAND PARAMETERS 15 0 1r--------d-X--(1-S-b-it-S-)-------.1 15 0 rl--------d-Y-(-1-S-b-its-)------~1 < DESCRIPTION> The parameters (dX, dY) define the diagonal point of the rectangle as relative logical pixel X-Y displacements from the CPo As the rectangle is drawn, CP is moved to Pe. However, the logical pixel at position Pe is not drawn. Drawing starts in the X direction first, and is drawn in the direction show below. The initial X direction is detennined by the relationship between CP and (dX, dYI. r -___- __ Pc_(-,;A~ dX. B + dY) 1\ CP(A,B) V (r~Bf'''''\ dY II dX B ORGCO,O) l.-- A ') Figure C21-1 Function of RRCT 234 HITACHI IRRCT RRCT (Relative Rectangular) PAGE RRCT-2 If CP = (6, - 6) and RRCT command is executed with parameters (dX, dY) then a rectangle is drawn and CP is set to Pe as shown below. = (- 16, 10). COMMAND CODE 15 8754320 ($94XX) 11 00 110 1 0 olAREA ICOl 1OPMI COMMAND PARAMETERS 0 15 11 1 1 1 11 1 1 1 11 1 1 1 10 0 0 01 dX ($ F F F 0) 0 15 10 0 0 0 I0 0 0 0 I0 0 0 011 0 1 01 dY ($ 0 0 0 A) y PC(-iO,4.) '-/<~aeee4~~ _______________-e/:___O_R_G~(O_.~O)4_----~-------------------- x 10 k~e(6.-6) \; ~'16 ~~P(6.-6) Figure C21-2 Example of RRCT HITACHI 235 lAPLL [22] APLL (Absolute Polyline) PAGE APLL-1 Draw a polyline (multiple contiguous segments) from the CP through command specified points. TYPE Graphic Command APLL (AREA. COL, OPM) n, X 1, Y 1 '" Xn, Yn WORD NUMBER Wn=2n+2 COMMAND CODE 15 hexadecimal notation 8 7 5 4 3 2 0 1100111000iAREAlcOLIopg ($ 9 8 X Xl COMMAND PARAMETERS 15 1 0 n (16 bits) 15 1 0 X1 (16 bits) 15 I I Pn-1 1 0 Xn (16 bits) 15 I P2 I 0 Yn- 1 (16 bits) 15 I I 0 Xn- 1 (16 bits) 15 1 I 0 Y2 (16 bits) 15 1 P1 0 X2 (16 bits) 15 I I 0 Y1 (16 bits) 15 1 I I 0 Yn (16 bits) Pe 1 P2n+ 1 n is specified by the absolute value of a 1 6-bits binary number. 236 HITACHI EXECUTION CYCLES Cn=1 {P'L+ 16}+8 APLL APLL (Absolute Polyline) PAGE APLL-2 < DESCRIPTION> = The first parameter (n) specifies the number of line segments, that is, n 1 specifies one line segment. The following parameters (Xn, Yn) are absolute logical pixel X-V addresses, which specify each segments end point relative to the origin defined by the ORG command. As the polyline is drawn, CP is moved to Pe. However, the logical pixel at position Pe is not drawn. y P2(X 2 , Y2 ) x ORG(O,O) Xn Figure C22-1 Function of APLL HITACHI 237 APLL APLL (Absolute Polyline) PAGE APLL-3 < EXECUTION EXAMPLE> If the CP is at (- 8, - 6) on the split screen, n is set to 3, Xl to - 4, Yl to 4, X2 to 8, Y2 to 6, X3 to 1 6 and Y3 to - 8, then the APLL command draws a poly line as shown below. COMMAND CODE 15 87 54 32 0 I 1 0 0 1I1 0 0 01 AREAl COL IOPM I COMMAND PARAMETERS 15 0 1000010000100001001 1 I 15 ($ 0003) 0 ($ F F F C) 111111111111111111001 15 0 ($ 0004) 10000100001000010 1 001 15 0 I 0 0 0 0 10 0 0 01 0 0 0 01 1 0 0 0 15 I ($ 0008) 0 ($ 00 06) 10000100001000010 1 1 01 15 0 ($ 00 1 0) 10 0 0 010 0 0 01 0 0 0 11 0 0 0 01 15 0 ($ F F F 8) 1111111,11,,1,1,0001 y P2(8.6) x Pe(16,-8) Figure C22-2 Example of APLL Execution 238 HITACHI IRPLL [23] RPLL (Relative Polyline) PAGE RPLL-1 RPLL command draws a polyline which connects the Start point, current pointer, and each relative coordinate point. TYPE Graphic Command RPLL (AREA, COL, OPM) n, dX 1, dY 1, ... dXn, dYn WORD NUMBER Wn=2n+2 COMMAND CODE 15 C hexadecimal notation 87 54 32 0 110011110olAREAjcOLloPMI ($ 98 X X) EXECUTION CYCLES Cn=l(P·L+16l+8 COMMAND PARAMETERS 15 I 0 n (16 bits) 15 I 0 dX 1 (16 bits) 15 j dY 1 (16 bits) dX2 (16 bits) dY 2 (16 bits) dXn- 1 (16 bits) dY n- 1 (16 bits) I Pn-1 I 0 dXn (16 bits) 15 L P2 I 0 15 I I 0 15 I 1 0 15 L P1· 0 15 I I 0 15 I I I 0 dYn (16 bits) Pe I P2n+ 1 Set "n" in binary absolute values of 16 bits. HITACHI 239 IRPLL RPLL (Relative Polyline) PAGE RPLL-2 < DESCRIPTION> As shown in figure below, the relative poly line command (RPLL) draws a poly line which connects the Start point CP, and each relative coordinate (P" P2, P3, ....., Pn-l, Pel. The total number of points is set in the 1st command parameter (n ,). X and Y components of each point are set in the command parameters in the order the lines are drawn. CP moves to the End point Pe as the lines are drawn. However, a dot is not drawn at Pe. (X " Y, ):(A+dX " B+dY, ) (X.,Y.):(X, +dX.,Y, +dY.) (X.,Y.):(X.+dX.,Y.+dY.) (Xn- " Yn-,):(Xn-.+dXn-"Yn-.+dYn-,) (Xn,Yn):(Xn-, +dXn,Yn- , +dYn) Y p. (x •• y.) dX. i ~~----,IddYY. PI ex•• YI ) CP(A.B;........---I dY. • dXn ..,.--~ IdYn ~--- Pn- 1 (Xn-.. Yn-I)~ p. (x •• Y.) Pe(Xn. Yn) d;'<&' ~ If the CP is at (- 8, - 6) on the split screen, dX 1 is set to - 4, dY 1 to 4, dX2 to 8, dY 2 to 6, dX3 to 16 and dY 3 to - 8, then the RPLL command draws a poly line as shown below. COMMAND CODE 8 7 15 54 32 I 0 I 11 0 0 1 11 1 0 0 IAREA COL OPM I ($ 9 C X X) COMMAND PARAMETERS 15 0 I0 0 0 0 10 0 0 0 10 0 0 0 10 0 1 1 I ($ 0003) 15 0 1 1 1 1 1 1 1 1 11 1 11 1 11 001 11 15 0 I 0 0 0 01 0 0 0 010 0 0 010 1 0 01 15 0 ($ F F F C) ($ 0004) ($ 0008) 1 0 0 0 010 0 0 010 0 0 011 0 0 01 15 0 I 0 0 0 01 0 0 0 010 0 0 010 1 1 01 15 0 ($ 0006) ($ 0 0 1 0) 1 0 0 0 01 0 0 0 010 0 0 1 10 0 0 01 15 I' 0 1 1 1 11 1 1 1 11 1 1 111 0001 ($ F F F 8) y P,(-4,4) ~- / Ii ----- ~ ~ 16 -....-.. ~ /~ ~ ~~(-"-') 1\ ~lJ X ORc} ( 0, u) P e (12, -4 ) 4 /CP(-H ,-5) Figure C23-2 Example of RPLL Execution HITACHI 241 IAPLG [24] APLG (Absolute Polygon) PAGE APLG-1 APLG draws a polygon which connects the initial point, CP, and each absolute coordinate. TYPE Graphic Command APLG (AREA, COL, OPM) n, Xl, Y 1 ••••• Xn, Yn WORD NUMBER Wn=2n+2 COMMAND CODE 15 hexadecimal notation 8 7 5 4 3 2 0 11 0 1 010 0 0 olAREAI COLI OPMI ($A 0 XX) COMMAND PARAMETERS 15 I 0 n (16 bits) 15 I 0 Xl (16 bits) 15 I Yl (16 bits) Y2 (16 bits) Yn-l (16 bits) Pn-l I I 0 Yn (16 bits) P20+1 Set "n·' in binary absolute values of 16 bits. 242 HITACHI I 0 Xn (i6 bits) 15 I P2 I 0 15 I I 0 Xn-l (16 bits) 15 [ I 0 15 I Pl 0 X2 (16 bits) 15 I I 0 15 I I I Pn EXECUTION CYCLES Cn=~ {P'L + 161+p'LO+ 20 APLG APLG (Absolute Polygon) PAGE APLG-2 < DESCRIPTION> y P2 (X2 ,Y2) Pn-, (Xn-, ' Yn-, ) x ORG(O,O) Figure C24-1 Function of APLG As shown in above figure, the APLG command draws a polygon line which connects the start point, CP, and each absolute coordinate (P1, P2 ..... , Pn-l, Pnl, then back to CPo The total number of points are set in the first command parameter. X and Y components of each point are set in the command parameters in the order the lines are drawn. CP moves to the end point CPe to draw a poly line. However a dot is not drawn at Pe. CP is the same point as Pe. HITACHI 243 APLG APLG (Absolute Polygon) PAGE APLG-3 If the CP is at (- 8, - 6) on the split screen, n is set to 3, X 1 to - 4, Y 1 to 4, X2 to 8, Y 2 to 6, X3 to 16 and Y 3 to - 8 in the command parameter. The APLG command draws a polygon line as shown below. COMMAND CODE 15 0 ($A 0 XX) 11 0 1 0100 0 olAREAI COL 1OPMI COMMAND PARAMETERS 0 15 I0 0 15 11 1 1 111 1 1 111 1 1 1 11 ($ F F F C) 0 01 0 15 I0 ($ 0003) 0 0 010 0 0 010 0 0 010 0 1 11 ($ 0004) 0 0 01 0 0 0 010 0 0 010 1 0 01 0 15 I 0 0 0 01 0 0 0 010 0 0 011 0 0 01 0 15 I0 ($ 0008) ($ 0006) 0 0 010 0 0 010 0 0 010 1 1 01 15 0 ($ 0 0 1 0) 1 0 0 0 01 0 0 0 01 0 0 0 11 0 0 0 01 15 11 0 ($ F F F 8) 1 1 111 1 1 111 1 1 111 0 0 01 y P2 ( 8 ,6) P 3 (l6,-8) Figure C24-2 Example of APLG Execution 244 HITACHI IRPLG [25] RPLG (Relative Polygon) PAGE RPLG-1 APLG draws a polygon which connects the initial point, CP, and each relative coordinate. TYPE Graphic Command RPLG (AREA, COL, OPM) n, dX 1, dY 1, ... dXn, dYn WORD NUMBER Wn=2n+2 COMMAND CODE hexadecimal notation 87 15 54 32 0 11 0 1 010 1 0 01 AREAl COLI OPMI ($ A 4 X X) COMMAND PARAMETERS 15 I 0 n (16 bits) 15 I dY 1 (16 bits) P1 I 0 dX2 (16 bits) 15 I I 0 15 I I 0 dX 1 (16 bits) 15 I EXECUTION CYCLES Cn=L{P'L + 16]+P'LO+ 20 I 0 dY 2 (16 bits) 15 P2 I 0 I dXn- 1 (16 bits) 15 I 0 I dYn- 1 (16 bits) 15 Pn-l I 0 I dXn (16 bits) 15 I Pn 0 I dYn (16 bits) I P2n+ 1 Set "n" in binary absolute values of 1 6 bits. HITACHI 245 RPLG (Relative Polygon) PAGE RPLG-2 < DESCRIPTION> (Xl, Yl): (A+dXI,B+dYI) Y (X2, Y2): (XI+dX2, YI+dY2) (X3, Y3): (X2+dX3, Y2+dY3) (Xn-l, Yn-l): (Xn-2+dXn-I, Yn-2+dYn-l) (Xn, Yn): (Xn-l+dXn, Yn-J+dYn) d~ d~ dX, ~ dY, CP (A,B ORG(O,O) 1'\ I\ B Pn-' (Xn -, ,Yn-') dXn dXs Y:s k:~ x. , " ,. . - " " , P, ( Y,) ~.dYn Ps (X s . Ys ) PoCXn, Yn) Pe (A, B) X l! Figure C25-1 Function of RPLG As shown in above figure, the RPlG command draws a polygon line which connects the start point CP, and each related coordinate (P 1, P2, P3, ..., Pn-l, Pn), then back to CPo The total number of points are set in the first command parameter. X and Y components of each point are set in the command parameters in the order the lines are drawn. CP moves to the end point Pe as the lines are drawn. However a dot is not drawn at Pe. CP is the same point as Pe. 246 HITACHI IRPLG RPLG (Relative Polygon) PAGE RPLG-3 If the CP is at (- 8, - 6) on the split screen, n is set to 3, dX 1 to - 4, dY 1 to 4, dX2 to 8, dY 2 to 6, dX3 to 1 6 and dY 3 to - 8 in the command parameter, then the RPLG command draws a polygon line as shown below. COMMAND CODE a 15 11 a 1 ala 1 a al AREA I COL I OPMI ($A 4 XX) COMMAND PARAMETERS a 15 la a a al a a a al a a a al a a a 15 11 1 1 111 1 1 111 1 1 111 1 15 15 ($ 11 a a al a a a 3) ($ F F F C) a la a a al a a a al a a a al a 1 a al ($ a a a 4) a la a a ala a a ala a a al 1 a a al ($ a a a 8) a al 1$ a a a 6) a a al ($ a a 1 a) 15 la a a ala a a alo a a ala 1 1 15 la a 0 010 0 0 ola a alia 15 lii 0 0 1 111 1 1 111 1 1 1 [ 1 a 0 al ($ F F F 8) y P2 (-4,4) ~8~~ 1--- : PI (-12,-2) 'I f ;/ 16 /~ ~ \ "'~e(-8'-5) ~4-::rcCP (-8,-6) ~ \ 8 ~l! X ORG (0,0) P a (12,-4) Figure C25-2 Example of RPLG Execution HITACHI 247 JCRCl [26] CRCl (Circle Command) PAGE CRCl-1 CRCl Command draws a circle of the rqdius R placing the CP at the center. TYPE Graphic Command CRCl (C, AREA, COL, OPM) r WORD NUMBER Wn=2 hexadecimal notation COMMAND CODE 15 987 54 32 0 11 0 1 01 1 00 lclAREA ICOl I OPMI C C = 1 : ($ A = 0 : ($ A 9 X X) 8 X X) EXECUTION CYCLES Cn=8d+ 66 COMMAND PARAMETERS 15 0 Ie-- - - - - r-(1-6-b-it-s-)------=;1 < DESCRIPTION> The Circle Command (CRCL) draws a circle placing the Current Pointer (CP) at the center. The command parameter r specifies a radius in units of pixels. First the CP moves in the X-direction from the center for the length of the radius r. Now this point is named Ps. The circle drawing starts at Ps and finishes at P 1 (= Ps). But a dot is not drawn at P 1. After the circle has been drawn, the CP moves back to the center and the command is finished. The position of the CP and Pe are the same. Bit 8 (C) of the command code specifies whether a circle is drawn clockwise or counterclockwise. When C= 1, it is drawn clockwise, when C = 0, counterclockwise as shown next page. The parameter radius r is allocated 16 bits, but only the low order 13 bits are effective. 248 HITACHI CRCL CRCL (Circle Command) PAGE CRCL-2 y y Ps(A+r,B) P\(A+r,B) ~--~Ps(A+r,B) ._------'t PI (A+r ,B) 000(0,0) ORG(O,O) x A x A (B) (A) Figure C26-1 Function of CRCL If the CP is (0, 0) on the split screen, and r is set 7 in the command parameter, then the CRCl Command draws a circle as shown in figure below. COMMAND CODE 15 li 0 0 1 01 1 0 0 iolAREA ICOl IOPMI ($A 8 XX) COMMAND PARAMETERS o ($ 0007) Ps(7,O) CP(o,o) X --~~P-e(-O~,-O)-'~~~~------~ PI (7,0) Figure C26-2 Example of CRCL Execution HITACHI 249 IELPS [27] ELPS (Ellipse Command) PAGE ELPS-1 ElPS Command draws an ellipse placing the CP at the center. TYPE Graphic Command ELPS (C, AREA. COL, OPM) a, b, OX COMMAND CODE hexadecimal notation 15 987 54 32 0 11 0 1 011 1 0 :CIAREA ICOl 10PMI = 1 : ($ A 0 X X) C C = 0 : ($ A C X X) WORD NUMBER Wn=4 EXECUTION CYCLES Cn= 10d+90 COMMAND PARAMETERS 15 0 a (16 bits) 1 15 I 0 I b (16 bits) 15 I 0 I dX (16 bits) I < DESCRIPTION> The Ellipse Command (ELPS) draws an ellipse placing the current pointer (CP) at the center. On the X-Y coordinates, if the center of an ellipse is CP (A, B). the major axis is dX, and the minor axis is dY. An ellipse is drawn according to Equation (1) as shown next page. ~_~2 ~ + ~-ru2_ (jY2 - 1 ............... (1 ) In Equation (1). letting the ratio of squared dX and dY be a, b; a : b = dX2 : dY2 ..................... , (2) Then substituting (2) for Equation (1); (X- A)2 a + 250 HITACHI (Y- B)2 = dX2 (3) b a ............ . ELPS ELPS (Ellipse Command) PAGE ELPS-2 The ELPS Command draws an ellipse according to Equation (3). The a, b, dX are specified in units of pixels. y ORG( 0,0) x Figure C27-1 Function of ELPS As shown in figure below, the CP moves in the X-direction from the center for the length of dX. This point is named Ps. The ellipse drawing starts at Ps and finishes at P 1 (= PsI. But, the dot is not drawn at P 1. After the ellipse has been drawn, the CP moves back to the center, and the command is finished. The first position of the CP and Pe are the same. y y ~:-.::.~~ PI (A+dX, B) P s (A+dX, B) ORG (0,0) ORG (0,0) x A (A) x A (6) Figure C27-2 Drawing Direction of ELPS HITACHI 251 IELPS ELPS (Ellipse Command) PAGE ELPS-3 < EXAMPLE> Bit 8 (e) of the command code specifies whether an ellipse is drawn clockwise or counterclockwise. When C = 1, it is drawn clockwise, when C 0, counterclockwise as shown in previous page. If the bit length of a, b, dX are 1.a, 1.b, 1.dX, then the bit length of these parameters must be as follows; = 1.a 1.b + + 1.dX ~ 13 1.dX ~ 13 < EXECUTION EXAMPLE> If the absolute coordinate of CP is (16, 10) on the split screen, a is set to 9, b to 4, dX to 9 in the command parameter, then the ELPS Command (C = 0) draws an ellipse as shown below. COMMAND CODE 15 G0 0 I 1 0 11 1 0 [0 IAREA I COL OPM I ($A C XX) COMMAND PARAMETERS 0 15 10 0 0 010 0 0 010 0 0 011 0 0 11 a ($ 0 0 09) 0 15 10 0 0 010 0 0 010 0 0 010 1 0 0 15 Ib ($ 0 0 04) 0 10000100001000 011 ~ dX ($ 0009) 9 ;4 = 92 ; 62 y I~ ~ . I' (16,10) (16,10)1\ . 9 .~ I's(25,10) jP]C25,10) 10/ OIW CO, 0) I; x Figure C27-3 Example of ELPS Execution 252 HITACHI IAARC [28] AARC (Absolute Arc) PAGE AARC draws an arc by current pointer (start point). end point, and center point of the absolute coordinate. TYPE AARC-1 Graphic Command AARC (C, AREA, COL, OPM) Xc, Yc, Xe, Ye WORD NUMBER Wn=5 COMMAND CODE hexadecimal notation EXECUTION CYCLES Cn=8d+ 18 COMMAND PARAMETERS a 15 I Xc (16 bits) a 15 I a , I Xe (16 bits) 15 I I Yc (16 bits) 15 I I a Ye (16 bits) I < DESCRIPTION> As shown in Fig. C28-1, the AARC command draws an arc from the current pointer, CP, to Pe of the absolute coordinate, the absolute coordinates CC (Xc, yc) being the center point. The X and Y components of the absolute coordinates CC and Pe are set in the first and second paraneters in units of pixels. After the arc drawing, current pOinter moves to Pe. However a dot is not drawn at Pe. The command code bit 8 (C) selects whether an arc is drawn clockwise or counterclockwise. When C is "1 ", the arc is drawn clockwise, and when C is "a",the arc is drawn counterclockwise as shown in Fig. C28-1. HITACHI 253 AARC AARC (Absolute Arc) PAGE AARC-2 The command parameters are allocated 16 bits, but only the low order 1 3 bits are effective. y y /,/' ----- / .......... " , / I I I I I I x ORG(O,O) (A) Xe (B) Figure C28-1 Function of AARC Command If the coordinate of CP is at (12,4) on the split screen, Xc is set to 12, Yc to 10, Xe to 6, and Ye to lOin the command parameter, then the AARC Command (C = 0) draws an arc as shown in figure next page. COMMAND CODE 15 0 Eo 1 1100 o!oIAREA ICOLIOPMI ($ 80 XX) COMMAND PARAMETERS 15 0 ~lo-o-o-o~lo--o-o-o~lo-o-o-o~l-l--o~ol ($ 000 C) 0 15 10000100001000011 o 1 01 ($ 000 A) 15 0 10 0 0 010 0 0 010 0 0 0 10 1 1 01 15 ~ 00 254 HITACHI ($ 0006) 0 010 0 0 010 0 0 011 o 1 01 ($ 00 OA) IAARC AARC (Absolute Arc) PAGE AARC-3 I C= 0 I y Pe(6,10) CC(l2,10) 1\ ,~ 10 000(0,0) ~ CP (12,4) x ~12.----/ Figure C28-2 Example of AARC Execution , HITACHI 255 IRARC [29] RARe (Relative Arc) PAGE RARC-1 RARC draws an arc by current pointer (start point). end point. and center point of the relative coordinate. TYPE Graphic Command RARC (C, AREA, COL, OPM) dXc, dYc, dXe, dYe WORD NUMBER Wn=5 COMMAND CODE 15 hexadecimal notation 987 11 0 1 1 10 1 0 54 32 0 ic IAREA ICOL IOPM I ~:: ~ ::: : ! ~ ~: EXECUTION CYCLES Cn=8d+ 18 COMMAND PARAMETERS 0 15 I dXc (1 6 bits) 15 I 0 dYc (16 bits) 15 I I 0 dXe (16 bits) 15 I I I 0 dYe (16 bits) 1 < DESCRIPTION> As shown in Fig. C29-1, the RARC command draws an arc from the current pointer, CP, to Pe (A + dXe, B+ dYe) of the relative coordinates, the relative coordinates CC (A + dXc, B+ dYc) being the center points. The X and Y components of the relative coordinates· CC and Pe are set in the first and second parameters in units of pixels. CP moves to the end point Pe when an arc is drawn. However a dot is not drawn at Pe. The command code bit 8(C) selects whether an arc is drawn clockwise or counterclockwise. When C is "1 ", the arc is drawn clockwise, and when C j~ "0", the arc is drawn counterclockwise as shown in Fig. C29-2. 256 HITACHI RARC RARC (Relative Arc) PAGE RARC-2 The command parameters are allocated 1 6 bits, but only the low order 1 3 bits are effective. Pe(A+dXe ,B+dYe) Y Y Pe(A+dXe, B+dYe) / .- ------ ....... " I / CC( A+dXc, U+dY c) \ \ I I I I \CP(A,B) \ dXc B ORG ( 0,0) A x \ Yc ORG (0,0) X A (A) (B) Figure C29-1 Function of RARC < EXAMPLE> If the coordinate of CP is at (6, 10) on the split screen, dXc is set to 6, dYc to 0, dXe to 6, and dYe to 6 in the command parameter, then the RARC command (C = 0) draws an arc as shown next page. COMMAND CODE 15 0 I, 0 1 11 0 1 0;0 IAREA ICOL IODMI ($ B 4 XX) COMMAND PARAMETERS 0 15 100001000010000101 15 01 0 100001000010000100001 15 10 0 0 15 ($ 0006) ($ 0000) 0 o@ijo 10 0 0 01 0 1 1 0 I ($ 0006) 0 10000100001000010 1 1 01 ($ 0006) HITACHI 257 IRARC PAGE RARC-3 RARC (Relative Arc) y I c=o I Pe(l2,16) \ CP(6,10) ~6 / ' ~ CC(12,10) ORG( 0,0) x Figure C29-2 Example of RARC Execution 258 HITACHI IAEARC [30] AEARC (Absolute Ellipse ARC) PAGE AEARC-l TYPE Graphic Command AEARC draws an ellipse ARC. AEARC (C, AREA, COL, OPM) a, b, Xc, Yc, Xe, Ye COMMAND CODE 15 987 54 32 hexadecimal notation WORD NUMBER Wn=7 C = 1 : ($ B 9 X X) C = 0 : ($ B 8 X X) EXECUTION CYCLES Cn= 10d+96 0 11011110oiciAREAICOLIOPMI COMMAND PARAMETERS 15 I 0 a (16 bits) 15 I 0 b (16 bits) 15 I I 0 Xe (16 bits) 15 I ~ 0 Yc (16 bits) 15 [ I 0 Xc (16 bits) 15 [ I I 0 Ye (16 bits) I < DESCRIPTION> The AEARC command draws an arc from the current pointer, CP, to Pe of the absolute coordinate, the absolute coordinates CC (Xc, Yel being the center point. the X and Y components of the absolute coordinates CC and Pe are set in the command parameters in units of pixels. CP moves to the end point Pe when an arc is drawn. However a dot is not drawn at Pe. HITACHI 259 AEARC PAGE AEARC-2 AEARC (Absolute Ellipse ARC) The command code bit 8(C) selects whether an arc is drawn clockwise or counterclockwise. When C is "1 ", the arc is drawn clockwise, and when Cis "0", the arc is drawn counterclockwise as shown in Fig. C30- 1 . Y Y Pe(Xe,Ye) .... ~ ---- Pe(Xe,Ye) /';" I ( I \ \ CP(A,B) x x DRGCO,O) (B) (A) Figure C30-1 Function of AEARC < RELATED EQUATIONS> In the X-V coordinate, let the center point of the ellipse be CC(Xc, YC), let the length of the X-axis be dX, and let the length of the Y-axis be dY. Depending on (1), an ellipse ARC is drawn as shown in Fig. C30-2. (X- Xc)2 dX2 + (Y- yc)2 dY2 = 1 ............. (1) When letting dX2 and dY2 be a and b, then a : b dX2: dY2 .................. (2) by substituting (2) for (1), the result is = (X- XC)2 a + (Y-bYC) 2 = d~2 .......... (3) The AEARC draws an ellipse ARC according to Equation (3). 260 HITACHI AEARC PAGE AEARC-3 AEARC (Absolute Ellipse ARC) y x ORG(O,O) Figure C30-2 Notation of an Ellipse (1) y ... \ \ I I --- --- / .--,--/ x Figure C30-3 Notation of an Ellipse (2) When setting CP (A, 8) and CPe (Xe, Vel as shown in Fig. C30-3 for an ellipse arc drawing, the following equations are applicable. HITACHI 261 IAEARC PAGE AEARC-4 AEARC (Absolute Ellipse ARC) A = dXdY cos I} + x c. . . . . . . . .. .J dX2 sin I} + dY2 cos2 I} 2 B = .J dX2 sin2 dXdYsinl} + Yc I} + dY2 cos2 I} ......... . Xe = .J dX2 sin2 dXdY cos a + Xc a + dY2 cos2 a ......... . Ye = .J dX2 sin2 a + dY2 cos2 a + Yc () 4 (5) (6) dXdY sin a .......... (7) a, b, Xc, Yc, Xe and Ye are given as a parameter to the AEARC command in units of pixels. When setting the command parameters, CC (Xc, Yc) of an ellipse, and CP (A, B) and Pe (Xe, Ye) and ellipse ARC must meet the above (4). (5). (6) and (7) equations. 262 HITACHI JREARC [31] REARC (Relative Ellipse ARC) PAGE REARC-1 < FUNCTION> REARC draws an ellipse ARC. TYPE REARC (C,AREA, COL, OPM) a, b, dXc,dYc, dXe, dYe WORD NUMBER Wn=7 COMMAND CODE 15 Graphic Command hexadecimal notation 987 54 0 32 C 11 0 1 111 1 0 jCIAREA 1COL IOPMI C = = 1 : ($ B D X X) 0 : ($ B C X X) EXECUTION CYCLES Cn= 10d+96 COMMAND PARAMETERS 15 1 0 II a (16 bits) 15 I 0 b (16 bits) 1 15 L ______ 0 dXc (16 bits) ~ 15 I 0 dYc (16 bits) 15 I 0 dXe (1 6 bits) 15 C I 1 0 dYe (16 bits) I < DESCRIPTION> As shown in Fig. C31-1, the REARC command draws an arc from the current pointer, CP, to Pe (dXe, dYe) of the relative coordinate, the relative coordinates CC (dXc, dYc) being the center point. The X and Y components of the relative coordinates CC and Pe are set in the command parameters in units of pixels. HITACHI 263 REARC PAGE REARC-2 REARC (Relative Ellipse ARC) The command code bit 8 (C) selects whether an arc is drawn clockwise or counterclockwise. When C is "1", the arc is drawn clockwise, and when C is "0", the arc is drawn counterclockwise as shown in Fig. C31-1. Pe(A+dXe ,B+dYe) Pe(A+dXe,B+dYe; Y Y ..., ~~ " " \ I I I :l'i;;=-:;v,=-,~-~,,,,// \ x w CC(A+dXc,B+dYc \ cP(A, B) I ORG(O,O) ",""~-:-:;-:::=,,,f-:;:;-:~ ORG(O,O) X A (B) Figure C31-1 Function of REARC 264 HITACHI --------- .... /~ JAFRCT [32] AFRCT (Absolute Filled Rectangle) PAGE AFRCT-1 AFRCT command paints the rectangular area specified with CP (Current Pointer) and the command parameter (the absolute coordinates) according to a figure pattem stored in the Pattem RAM. TYPE Graphic Command AFRC (AREA, COL, OPM) X, Y WORD NUMBER Wn=3 COMMAND CODE 15 hexadecimal notation 87 54 32 0 11 1 001 000 O/AREAICOL IOPMI ($ CO XX) EXECUTION CYCLES Cn= (P'A+ 8)8+ 18 COMMAND PARAMETERS 15 I 0 X (16 bits) I 15 I 0 I Y (16 bits) < DESCRIPTION> The Absolute Filled Rectangle Command (AFRCT) paints the rectangle area according to the color information in the pattern RAM. The sizes of the rectangle are parallel to the coordinate axis. Two comer points on the diagonal are CP and Pc (X, YI at the absolute coordinate point from the origin. Pc (X, YI expressed in the absolute X - Y coordinates from the origin are given by the command parameter in units of pixels. y OIW(O,O) Figure C32-1 Function of AFRCT HITACHI 265 IAFRCT AFRCT (Absolute Filled Recangle) PAGE AFRCT-2 Painting in a rectangular area depends on the position of CP and Pc, as shown in Fig. C32-2. In Fig. C32-2, painting between CP and Pc is performed. CP is moved to Pe at the termination of the command. The drawing at the end point Pe is not performed. CP CP (:p .... ! / .. ~ Z2?/?Z --- 0-- Pc Pc i Figure C32-2 Painting Direction of AFRCT If the absolute coordinate of CP is (A, B) on the split screen, X is set to X 1 and Y to Y 1 in the command parameter, and the drawing parameter register for the pattern RAM is set to the following, the pattern start point (PSX, PSY), the pattern end point (PEX, PEY), the graphic pattern pointer (PPX, PPY), then, the rectangular area is painted with the AFRCT command as shown next page. COMMAND CODE 15 0 11 1001000 O/AREA/COL /OPM/ ($ COX X) COMMAND PARAMETERS 1r---- 15 X- 1 15 0 -----., 0 '==--=--=-~-_--_-Y=1==--=--=--~--i 266 HITACHI ($X XXX) ($ X X XX) IAFRCT AFRCT (Absolute Filled Rectangle) PAGE AFRCT-3 y f-LLLLLLLL Pattp.rn RAM PTN 15 (PEX. PEY) ((~J r---- ....,./ -- Pc (A. Y I -- 1) PTN 0 (PSX. PSY) bitO~ ~~~~~~l~l =-~~~~l~~~ =-~~~~~~l~ =-~~~~~~~~ bit 15 x ORG(O.O) Figure C32-3 Example of AFRCT Execution HITACHI 267 /RFRCT [33] RFRCT (Relative Filled Rectangle) PAGE RFRCT-1 RFRCT command paints in the rectangular area specified with CP (Current Pointer) and the command parameter (the relative coordinates) according to a figure pattern stored in the Pattern RAM. TYPE Graphic Command RFRCT (AREA. COL.OPM) dX.dY WORD NUMBER Wn=3 COMMAND CODE 15 hexadecimal notation 87 54 32 0 11 1 0 01 0 1 0 01 AREA 1COL 1 OPM I ($ C 4 XX) EXECUTION CYCLES Cn= (P·A+ 8)B+ 18 COMMAND PARAMETERS 15 I 0 I dX (16 bits) 15 I 0 I dY (16 bits) < DESCRIPTION> The Relative Filled Rectangle Command (RFRCT) paints the rectangular area according to the color information in the pattem RAM. The sizes of the rectangle are parallel to the coordinates axis. Two corner points on the diagonal are CP and Pe (A+ dX. B+ dY) at the relative coordinate point from CPo Pe (dX. dY) expressed in the relative coordinate from CP is given by the command parameter in units of pixels. y Pe (A, B-klY, 1 ) O-JI)---- Pc (A+dX,BtdY) dY ./ ORG(O,O) CP(A, dX ---1-----------------------X Figure C33-' Function of RFRCT 268 HITACHI IRFRCT RFRCT (Relative Filled Rectangle) PAGE RFRCT-2 Painting in a rectangular area depends on the position of CP and Pe, as shown in Fig. C33-2. In Fig. C33-2, painting between CP and Pe is performed. CP is moved to Pe at the termination of the command. The drawing at the end point Pe is not performed. pc_ Pe Pe CP - CP CP ~ -------0 0----- Pc Pc Pe Pe Figure C33-2 Painting Direction of RFRCT If the absolute coordinate of CP is (A, B) on the split screen, dX is set to dX 1 and dY to dY 1 in the command parameter, and the drawing parameter register for the pattern RAM is set to the following, the pattem start point (PSX, PSY), the pattern end point (PEX, PEYl. the graphic pattern pointer (PPX, PPYl. then, the rectangular area is painted with the RFRCT command, as shown in Fig. C33-3. COMMAND CODE 15 0 11 1 0 010 1 0 olAREA ICOl IOPMI ($ C 4 XX) COMMAND PARAMETERS 15 I 0 dXl 15 I 0 ! I ($X X XX) dYl i ($X X XX) I HITACHI 269 RFRCT PAGE RFRCT-3 RFRCT (Relative Filled Rectangle) y CP(A,B) ~~l~~t=.lt=. ~~~lt=.~~~ ~ Pa t tern RAM (PEX, PEY) PTN 15 r---- ..---- (ppx~1 !: PPY): t=.l ~ ~ t=. t=. ~ dYt+1 ~t=.l~~ll~ I I I ____ .II ~ Pe (A,B-dYl-I) PTN \ -dXt+1 Pc (A+dXI,B-dYI) o (PSX, PsY) bila ~ bit 15 x Figure C33-3 Example of RFRC Execution 270 HITACHI JPAINT PAGE PAINT-1 [34] PAINT (Paint) PAINT command paints the closed area surrounded by edge color using the figure pattern stored in the pattern RAM. TYPE Graphic Command PAINT (AREA, COL, OPM) WORD NUMBER Wn=l COMMAND CODE 15 hexadecimal notation 987 54 32 0 11 1 0 all 0 OiEIAREAlcOl IOPMI COMMAND PARAMETERS - NON- ($ C X XX) Command execution cycle number Cn=(lS'A+ 102)B-58 (When painting rectangle) < DESCRIPTION> The "Paint" command (PAINT) paints the closed area surrounded by edge color defined in the parameter register (EDG: edge color). using the figure pattern stored in the pattern RAM. If the CP is inside the closed area, the paint operation is performed only inside the closed area. If the CP is outside, the paint operation is performed outside the closed area. Color code stored in color registers (ClO or Cll) are also considered to be an edge during PAINT execution. (See < Complex Figure Painting>.) When an unpaintable area is detected during this command, the coordinates are put in the Read FIFO and painting is continued. Therefore, a complex figure can be completely painted by re-issuing PAINT commands using the coordinate data put in the Read FIFO. < Definition of Edge Color> E = 0: The edge color is defined by the data in the EDG register. (See figure next page) E = 1 : The edge color is defined to be all colors except for the color in the EDG register. (See figure next page) HITACHI 271 PAINT PAINT (Paint) PAGE PAINT-2 E = 0: CP "red" is set to the EDG register. PAINT is executed at E=O. Background: Black Figure C34-1 Paint Function (E=O) Red E = 1: CP "black" is set to the EDG register. PAINT is executed at E=1. Background: Black Figure C34-2 Paint Function (E= 11 Using a Pattern > The PAINT command paints using a pattern stored in the pattern RAM. As the scan point in the pattern RAM moves corresponding to the movement of the drawing point, the figure is repeatedly drawn. < Paint Pattern RAM PTN 15 ( PE (pEX, PEYI -- ~ !, I I --4PP(PPX i ,PPYI ' )----PTN 0 \...P_S_(P_S_X_,P_S_Y_I-, bitO~bit15 CP Figure C34-3 Paint Function Using Figure Pattern 272 HITACHI IPAINT PAGE PAINT-3 PAINT (Paint) < Paint Procedure> Figure C34-4 Paint Procedure Painting is continuously performed parallel to the X axis (left to right), and in the Y direction, dot by dot. Fig. C34-2 shows an example of painting the encircled area. First, painting begins from points S on a line which is parallel to the X axis from CPo Next, painting is executed on the adjacent line which is above or below the first line. This drawing is repeated and painting proceeds. In this way, the whole encircled area is painted. The current pointer, CP, moves to the end point Pe at the finish. < Complex Figure Painting> The PAINT command checks the outlined area for any un-painted areas during painting. If there are any during painting, the coordinates of the areas are pushed into the intemal stack. Figure below shows a case of four coordinates being pushed into the stack. Figure C34-5 Paint Stack Function HITACHI 273 I PAINT PAINT (Paint) PAGE PAINT-4 The ACRTC can store four such coordinates. If the points are within four, one PAINT command can completely paint a complex figure. ~ If the points are five or more all coordinates cannot be pushed into the stack. The un-stacked coordinates are put in the Read FIFO to be read out by the MPU. the MPU reads out the coordinates and issues another PAINT command to paint the un-painted areas using these coordinates after the initial PAINT command is finished. The coordinate for one point put in the Read FIFO consists of the following 3 words. 15 0 I CPx I ·Coo"',..... Xl o 15 I CPy 15 Absolute coordinates I ;Coordinates y 0 I PPxy I ;Value of the pattern pOinter If the Read FIFO is full, the command execution remains halted until the MPU reads out the coordinates. When the Read FIFO has data before "PAINT" is instructed, only two or less coordinates can be pushed into the stack. Therefore, it is recommended that the read FIFO be empty before instructing A "PAINT" command. The following two cases are the state of termination of the command. CD Data is not written in the Read FIFO (The outlined area is completely painted.) ~ Data is written in the read FIFO (An un-paintable area exists.) In the case o@ any un-painted area should be painted by issuing the PAINT command again. 274 HITACHI PAINT PAINT (Paint) PAGE PAINT-5 WPR PS WPR PE (Specify the pattern area) WPR PP (Specify the pattern point) AMOVE X, Y (Specify the start point) PAINT YES Read FIFO (Read out the coordinate X) YES Read FIFO (Read out the coordinate Y) NO Read FIFO (Read out the pattern point) END Figure C34-6 Paint Flow of Complex Figures Using PAINT Command HITACHI 275 IPAINT PAINT (Paint) PAGE PAINT-6 < PAINT Area Detection Mode> PAINT Area Detection modes have each of the following functions. AREA 000 001 PAINT Command Execution Not check the specified area. AREA flag is set and the command execution is truncated, if CP moves outside the specified area during painting. 010 Paint only inside the specified area. AREA flag is not set. all Paint only inside the specified arera. If CP meets the edge of the specified area, AREA flag is set. 100 101 Not check the specified area. AREA flag is set and the command execution is truncated, if CP moves inside the specified area. 110 Paint only outside the specified area. AREA flag is not set. 111 Paint only outside the specified area. If CP meets the edge of the specified area, AREA flag is set. 276 HITACHI PAINT PAINT (Paint) (i) PAGE PAINT-7 AREA = a a a AREA 100 = (ii) AREA = a a 1 (AREA flag is set.) (XMAX, YMAX) ,----------. I I I I Cp I I I I I .... ----(XMIN, YMIM) (iii) AREA = a 1 a (AREA flag is not changed.) a11 AREA (AREA flag is set.) (XMAX, YMAX) r----------., I = I I I CP I I I ....I ----(XMlN,YMlN) (iv) AREA = 1 a 1 (AREA flag is set.) (XMAX, YMAX) ,----------~ I I I I I CP I I ....I ----(X~[I'J, (v) AREA = 1 1 a (AREA flag is not changed.) AREA = 1 1 1 (AREA flag is set.) nil") (X~AX, r-----------., I niAX) I : CP I I ( X~[ l~~Y~~I~~-~~~~~~~ Figure C34-6A Paint Command Example with AREA Modes HITACHI 277 IPAINT PAINT (Paint) PAGE PAINT-8 = < EXAM PLE > (In the case of E "0") If a circle of the same color as specified in the edge color register (EDG) is drawn on the split screen, the pattern shown in Fig. C34-7 fetched from the pattern RAM is used and the pattern pointer (PP) is in the position shown in Fig. C34-7. Then the PAINT command with bit"0", CP in the position shown in Fig. C34-8 is executed as shown in Fig. C34-8. 8 = COMMAND CODE 15 0 11 10 0110 O!OiAREAiCOLioPMi ($ C 8 x X) Pattern RAM "--'''--''---'--r-~-'--+- PE (P EX, PE Y) H>--+-ttcj::~t---t- PP (pPX, PPY) I / PS (PSX, PSY) Figure C34-7 Setting of Pattern RAM 278 HITACHI jPAINT PAGE PAINT-9 PAINT (Paint) < EXECUTION EXAMPLE> (In the case of E - 0 o 0 o 0 0 6 [:, o 0 0 [:, 0 0 [:, o 0 [:, [:, [:, Do [:, [:, [:, [:, [:, 0 0 "0") [:, [:, 0 0 [:, 0 [:, [:, [:, 0 0 0 0 o [:, 0 0 o [:, [:, [:, [:, [:, 0 [:, [:, [:, [:, [:, [:, 0 [:, [:, 6 [:, [:, [:, 0 [:, [:, [:, [:, 0 [:, [:, [:, [:, [:, [:, [:, 0 0 [:, [:, /EDG [:, [:, [:, 6 [:, [:, [:, [:, [:, 6 [:, [:, [:, [:, [:, [:, [:, [:, [:, 0 [:, 0 [:, 0 [:, 0 0 0 o [:, [:, [:, 0 [:, [:, 0 0 [:, o [:, [:, 0 0 0 6 [:, [:, 6 0 0 [:, 0 0 0 [:, [:, [:, [:, [:, [:, 0 [:, 0 [:, 0 [:, 0 0 [:, 0 0 0 [:, [:, [:, 0 6 [:, o [:, [:, [:, [:, 6 o [:, [:, [:, [:, . ~[:, [:, [:, [:, [:, o [:, 6 [:, [:, [:, [:, [:, [:, [:, [:, [:, 6 [:, [:, 0 [:, [:, [:, [:, 0 [:, , [:, [:, [:, [:, 0 o CP 0 0 0 0 Figure C34-8 Example of PAINT Execution (E = "0") HITACHI 279 IPAINT PAINT (Paint) PAGE PAINT-10 < EXAMPLE> On the case of E = "1") If a circle of the same color as specified in the edge color parameter register (EDG) is drawn on the split screen and the inside of the circle is also painted in the same color and the surround of the circle is not the same color as the edge, Fig. C34-1 0 (A), and the pattern shown in Fig. C34-9 is in the pattern RAM, the pattern pointer (PP) is in the position shown in Fig. C34-9. Then the PAINT command with bit 8 = "1", CP in the position shown in Fig. C34-1 0 (A) is executed as shown in Fig. C34-10 (8). Pattern RAM -+- PE r-r--1--r-..,..-r__ (PE X, PE Y) H.......t--+"4=t==t--t- PP (PPX, PPY) / / PS(PSX,PSY) Figure C34-9 Setting of Pattern RAM 280 HITACHI I PAINT PAINT (Paint) PAGE PAINT-11 ., . ••• •• exceptional edge color • 0 0 0 0 0 CP .0 0 0 0 0 00 0 00 0 .0 0 0 00 0 0 00 000 00 000 00 0 00 o 0 0 00 o 0 0 000 0 000 0 00 o 0 • • • • • • • .• • • • • • •• • • • •• •• • (; (; · • ·••• • •· • • (; {:, {:, (; (; (; (; {:, (; (; (; (; (; (; (; {:, (; {:, (; (; (; (; @ (; {:, • {:, {:, (; • (; (; (; (; (; . • {:, (; (; (; •• •• (; (; (; e:. e:. e:. e:. e:. e:. e:. (; (; ••••••• (; (; (; • • • •• • • e:. e:. • (; • • • • • (A) • • {:, (; (; •• • • (; (; (; (; e:. (; (; ~EDG 000 00 0 0 000 0 o 00. 0 00 0 0 0 0 0 0 0 0 00 00 0 0 o 0 0 0 000 00 0 0 o 0 0 0 000 o 0 0 0000 0 o • 0 0 0 0 0 0 0 0 0 0 0 O. 0 0 0 0 0 00 0 0 0 0 0 . 0 0 0000000 00. 0 000 000000 00. 00 0 0 0 0 0 0 0 0 0 O. 0000000 0 0000 0000000 o 0 00 0 0 0 0 0 00 0 0 0 0 0 0000 00 000. 00000 00 00. 0 0 0 0 00 o • • • • • • • • • . •• (8) Figure C34-1 0 Example of PAINT Execution IE = "1") HITACHI 281 lOOT [35] DOT (Dot Command) PAGE OOT-1 DOT Command marks a dot on the coordinates where the CP points. TYPE Graphic Command DOT (AREA, COL, OPM) WORD NUMBER Wn=1 COMMAND CODE 15 hexadecimal notation 87 54 32 0 ($C C XX) 111001110olAREAICOLIOPMI EXECUTION CYCLES Cn=8 COMMAND PARAMETERS - NON- < DESCRIPTION> The Dot Command (DOT) marks a dot on the coordinate where the Current Pointer (CP) indicates. After dot drawing, the CP doesn't move. So, Pe, the dotting-finishing point, is the same point as the CPo y CP (A,B) • ORG (0,0) Pe (A,B) x Figure C35-1 Function of DOT 282 HITACHI lOOT PAGE OOT-2 DOT (Dot Command) In the case of the absolute coordinate of the CP is (10, 8) on the split screen, the DOT Command marks a dot as shown in Fig. C35-2. COMMAND CODE 0 15 /1 1 0 0/' 1 0 0IAREA ICOl I OPM I ($C C XX) COMMAND PARAMETERS - NONy Pe(lO,R) • CP(IO,8) __~O~R~G~(O~,~O~)__________ X figure C35-2 Example of DOT Execution The LINE Commands and ARC Commands do not draw a dot at the finishing points, Pe. The DOT Command can be used to draw a dot at the Pe to draw a complete line or arc. COMMAND CODE 15 87 54 32 0 / 1 1 0 01 1 10 alAREA I COL I OPM I EXAMPLE End point / CP Start point ALINE X, Y Pe (X, YI End point Pe (X, YI / CP Start point ALINE X, Y DOT Figure C35-3 DOT Command for the End Point HITACHI 283 IPTN [36] PTN (Pattern) PAGE The graphic pattern defined in the pattern RAM is drawn onto the rectangular area specified by the current pointer and by the pattern size. TYPE PTN-1 Graphic Command PTN (SL, SO, AREA, COL, OPM) S WORD NUMBER Wn=2 COMMAND CODE hexadecimal notation 12111087 15 54 32 0 I I I AREA ICOL IOPM I 11 1 0 1 SL SO ($0 X XX) EXECUTION CYCLES Cn= (P'A + 1O)'B+ 20 COMMAND PARAMETERS szl15 8 7 0 r-~~-S-Z-y---Ir----S-Z-x---'I 1 . . . . .- _ _ _ _ ..L._ _ _ _ _ _.....J _ SZx, SZy Setting: 0-255 Meaning: 1-256 in units of pixels < DESCRIPTION> As shown in Fig. C36-1, the Pattern command (PTN) is used to draw the graphic pattem defined in the pattern RAM onto the rectangular area specified by the current pointer (CP) and by the parameter (SZ: SZy, SZxl. The pattern to be taken out of the pattern RAM is set by the pattern start point (PS) and pattern end point (PEl. The point at which to start pattern RAM scan to obtain color information is set by the pattern pointer (PP). The color information is set on color registers "0" and "1" for execution of pattern drawing. Parameter SZ is divided into X component (SZx) and Y component (SZy), each component being set in units of pixels. The PTN command has the CP scan direction set up in units of 45° in the operation code, together with the choice of 45° slanted pattem drawing. After pattem drawing, the CP is moved to the Pe (see Table C36-11. 284 HITACHI IPTN PTN (Pattern) PAGE PTN-2 Frame Buffer Pattern RAM y where, SL; 0 SD; 7 ~ CP \' SZy + 1 SZX+l~ ORG (0,0) --~----------------------------x Figure C36-1 Function of PTN Table C36-1 Directions of CP Scan 00 0 "I o0 1 o 1 n o 1 1 Q <)oD (7 1 0 0 1 0 1 1 10 IO"'~--,,~-+---_-=-O"---"-----f-.--. 0u 1 0 10 1 1 1 II 1 1 ~ o~ • : CP 0: PI" HITACHI 285 IPTN PTN (Pattern) PAGE PTN-3 < Example of Command Execution> From the pattern RAM, take out a pattern using the PS (PSX, PSY) and PE (PEX, PEY)' and execute the PTN command. (1) Where PP=PS, PZ=O, SZ=PE-PS, SL=O, SD=O COMMAND CODE 15 i I I 0 11 1 0 11 0 0 0 01 AREA COL OPM 1 ($DOXX) COMMAND PARAMETERS 15 8 7 0 1000001 1 11000001 011 ($ 07 05) Pattern RAM PTN15r-------------~--~ . . ... PE (PEX, PEY) PTN 0 ) 0000· • oPE-PS, SL=O, SD=O COMMAND CODE 15 0 1110110iooolAREAICOLIOPMI ($DOXX) COMMAND PARAMETERS 8 7 15 0 10000 1 1 1 110000 1 0 1 1 I ($0 F OS) Pattern RAM PTN 15 r - - - - - - - - - - , PE (PEX, PEY) ..... ~ 0000· • ® •• e(!)e (!) • • -@- 0000· • @.® ••• 0· ·0· • ffJ· • •(!) • PTN 0 Frame Buffer PS (PSX, PSY) = PP bit 0 bit 15 ye •· .• .• .• .• • . . .• . .• .• .• • • 0000· • 00c!)0 •• 0·· ·0·0·· ·0· 0 · · -@·0-· .(!J. 0000· • C!)CVCV0· • 0·0·· ·0·0··· 0· · 0 · · 0 · · 0 · · ev·· · .. . .. . . . . .. .(!).(!) • • • (!). 00c!)0· ·0000· • 0 · . -0-0 . . e(!)e ® •• e0·@e. -@0000· • 0CVCV0· • C!)-@··-0-0-· • (!). e(!)e -0- -@-. ~ •• · 0 · 0 · · ·CV· CP Figure 36-5 Example of PTN Execution (4) HITACHI 289 IPTN PTN (Pattern) (5) PAGE PTN-7 Where PP=PS, PZX=1, PZY=1, SZ>PE-PS, SL=O, SD=O COMMAND CODE 15 0 111011 0 1000lAREAICOLIOPMI ($ DO XX) COMMAND PARAMETERS 15 8 7 0 1000011111000010111 ($ 0 FOB) Pattern RAM PTN15~--------------~ .. PE (PEX, PEY) 0000· • ® •• • G). ® •• ·0 • 0000· • (!) • AGCPY command copies a rectangular area specified by the absolute coordinates to the address specified by CP (Current Pointer) Graphic Command TYPE AGCPY (S, DSD, AREA, COL, OPM) Xs, Ys, DX, DY WORD NUMBER Wn=5 COMMAND CODE 15 121110 hexadecimal notation 87 54 32 0 11110lsIDSDIAREAlooIOPMI ($ E X XX) EXECUTION CYCLES Cn= {(P+ 2)A+ 1 OJB+ 70 COMMAND PARAMETERS 15 I 0 Xs 15 I 0 Ys 15 I I 0 DX 15 I I I 0 DY I < DESCRIPTION> The Absolute Graphic Copy Command (AGCPY) copies data from an rectangular area in the frame buffer (the source area) to another location in the frame buffer (the destination area) with the initial starting point CPo The size of the source rectangular area is parallel to the coordinate axis. Two diagonal comer points are Pss (XS, Ys) at the absolute coordinate point from the origin and Pse (Xs+ DX, Ys+ DY) at the relative coordinate point from Pss. Pss (XS, Ys) expressed by absolute X- Y coordinates from the origin are set in the command parameter in units of pixels. Pse (DX, DY) expressed by relative X- Y coordinates from Pss are set in the command parameter in units of pixels. HITACHI 293 IAGCPY AGCPY (Absolute Graphic Command) PAGE AGCPY-2 y Pe (A, B + OX + 1) o Destination area Source area <=::J :. CP (A, B) ORG (0,0) • Pse (Xs+DX, Ys+DY) • • • ~DX ( Pss (Xs, Ys) ______ Ys ~ \ [J ~Y Direction of scan S=1 DSD = 000 ----~--~~--------------_7------------------------~x I~xs~ Figure C37-1 Function of AGCPY < DIRECTION OF POINTER SCAN> The direction of pointer scan is determined by S bit and DSD bit in the command code through the AGCPY command. (a) S (Source Scan Direction) COMMAND CODE 15 I 294 HITACHI 11 o lSi I IAGCPY PAGE AGCPY-3 AGCPY (Absolute Graphic Command) Table C37-1 Direction of Source Data Scan s =0 s- 1 BBBlGJ • : Pss o : Ps e The direction of scan on the frame buffer in the source area is determined with bit 11 in the command code and the position of Pss and Pse, as shown in Table C3 7 -1 . (b) DSD (Destination Scan Direction) COMMAND CODE 15 1098 0 Ir-----,.I-DS-- - 'DIr-----I HITACHI 295 IAGCPY PAGE AGCPY-4 AGCPY (Absolute Graphic Copy) Table C37-2 Direction of Destination Data Scan DSD=ooo DSD=oOl DSD=OlO DSD=o 11 DSD=lOO DSD=lOl DSD=110 DSD=lll lEI [EJ oBl °Bl .:CP o:Pe As shown Table C37-2, the direction of scan on the frame buffer in the destination area is determined with bits 10 through 8 in the command code and position of CP and Pe. After termination of the command, Pe, the end point of CP, is moved to the point shown in Table C37-2. If the absolute coordinates of CP is (4, 2) on the split screen, Xs is set to 18, Ys is set to 2, OX is set to 13 and OY is set to 7 in the command parameter. Then, the drawing is copied by the AGCPY command (S = 1, OSO = 000), as shown in Fig. C37-2 (B). 296 HITACHI AGCPY AGCPY (Absolute Graphic Copy) PAGE AGCPY-5 COMMAND CODE 15 0 ($EOXX) 11 1 1 01 0 100 OIAREAI 00 IOPMI COMMAND PARAMETERS 15 0 ($ 00 1 2) 10000100001000 11 00 1 01 15 0 ($0002) /0 0 0 0/0 0 0 0/0 0 0 0/0 0 1 0/ 0 15 /000 % 0 0 010 0 0 011 1 0 1 I ($ 000 D) 0 15 1000 % 0 0 % 0 0 010 1 1 I ($ 0007) Y (34,12) ~ (28,6) x ORG (0,0) (A) Before Execution of AGCPY Y r---'0 oPe (4,16) I (8,12) I I I I I I (11,15) : I I I r-------- - I I I I I II I •: ______ .JI Pss (18, 2) 13 _____ II / 7 ---------~ CP (4, 2) x 18 ORG (0,0) (B) After Execution of AGCPY Figure C37-2 Example of AGCPY Execution HITACHI 297 [RGCPY PAGE RGCPY-1 [38] RGCPY (Relative Graphic Copy) RGCPY command copy a rectangular area specified by the reative coordinates based on CP (Current Pointer) to an address specified by CPo TYPE Graphic Command RGCPY (S, DSD, AREA, COL, OPM) dXs, dYs, OX, DY WORD NUMBER Wn=5 hexadecimal notation COMMAND CODE 15 121110 87 54 32 0 11111lSlDSDIAREAI 00 IOPMI ($FXXX) EXECUTION CYCLES Cn= /(P+2)A+ 10}B+70 COMMAND PARAMETERS 15 I 0 dXs 15 I 0 dYs 15 I I 0 OX 15 I I I 0 DY I < DESCRIPTION> The Relative Graphic Copy Command (RGCPY) copies data from an rectangular area in the frame buffer (the source area) to another location in the frame buffer (the destination area) with the initial starting point CPo The size of the source rectangular area is parallel to the coordinate axis. Two diagonal comer pOints are Pss (A+dXs, B+dYs) at the absolute coordinate point from CP and Pse (A+dXs+DX, B+dYs+DY) at the relative coordinate point from Pss. Pss (dXs, dYs) expressed by the relative X- Y coordinates from CP are set in the command parameter in units of pixels. Pse (OX, DY) expressed by the relative X - Y coordinates from Pss are set in the command parameter in units of pixels. 298 HITACHI IRGCPY RGCPY (Relative Graphic Copy) y PAGE RGCPY-2 Pe (A, B + DX+1) 0.-_--, •• Pse (A+dXs+DX, B+dYs+DY) /'---,. f\D Y ~ • •~ DX _____ V •• • CP (A, B) • ~ dXs V ORG (0,0) .I dYs \ Pss (A+dXs, B+dYs) ------- Direction of Scan S= 1 DSD = 000 x "----A...-/ Figure C38-1 Function of RGCPY < DIRECTION OF POINTER SCAN> S-bit and OSD bit in the RGCPY command have the same function as those in the AGCPY command. Refer to the description about the AGCPY command for details. < EXECUTION EXAMPLE> If the absolute coordinate of CP is (4, 2) on the split screen, dXs is set to 18, dYs to 2, OX to 1 2 and DY to 6 in the command parameter. Then, the drawing is executed by the RGCPY com1, DSO 000), as shown in Fig. C38-2 (8). mand (S = = HITACHI 299 RGCPY RGCPY (Relative Graphic Copy) PAGE RGCPY-3 COMMAND CODE a 15 11 1 1 11010 a olAREAI a a I OPM I ($FOXX) COMMAND PARAMETERS 15 10 a a 010 a a 010 a a 110 a a a 010 15 10 a a 010 a a 010 a a 1 01 a 1 01 ($ aa ($ a a 02) 1 2) a 15 10 a a 0[0 a a 010 15 10 a a 010 a a 1 001 a 010 0'0 010 1 1 01 a a all ($ a a a C) ($ a a 06) (40,13) Y • (28,6) ORG (0,0) (A) Before execution of RGCPY x Y Pe(4,15) o r-~""' r--->OJ I I I I i (6,8) I I I ~ 18 Pss (22, 4)r-=------- ~2 12 CP (4, 2) x ORG(O,O) (B) After execution of RGCPY Figure C38-2 Example of RGCPY Execution 300 HITACHI o Use of Arcs and Ellipse Arcs Commands How to Calculate Parameters of Arc Commands AARC Xc, Yc, Xe, Ye; RARC dXc, dY c, dXe, dYe; (Command Issuing Procedure) l:P is moved to the start point (CPx, CPy) by MOVE, then (Xe, Ve) ARC is issued. I [Example 11 Given center coordinates I I (Xc, Yc), radius r, drawing start angle () 1 and drawing end angle () 2, calculate as follows (counterclockwise rotation): (Parameter calculation: / I (CPx, CPy) I I \ \ \ \ ,, (Xc, Vc) " "- ....... _---- CD absolute addressing) Calculate the start point (CPx, CPy): CPx = Xc + [r cos ()1 1] CPy = Yc + [r sin () 1 11 Calculate the end point (Xe, Ye): Xe = Xc + [R cos () 2 11 Ye = Yc + [R sin ()2 11 twhere, R = J(CPx- XC)2+ (CPy- YC)2 .. r) (Parameter calculation: (1) relative addressing) Calculate the start point (CPx, CPy): CPx = Xc + [r cos () 1 11 CPy = Yc + [r sin () 1 X] Same as in absolute addressing Calculate the cemer coordinates (dXc, dYc): dXc = - [r cos () 1 11 dYc = - [r sin ()1 11 Calculate the end point (dXe, dYe): dXe = dXc + [R cos ()2 1] dYe = dYc + [R sin ()2 11 where, (R = J(CPx- XC)2+ (CPy- YC)2 .. r) HITACHI 303 [Example 2] Given center coordinates (Xc, Yc), start point (CPx, CPy) and drawing angle 0, calculate as follows (counterclockwise rotation): (Xe, Ye) / / I I I \ (CPx, CPy) I \ \ • \ \ I I I (Xc, Yc) \ CD absolute addressing) (Parameter calculation: Calculate the end point (Xe, Ye): Xe = Xc + [R cos (0+ (1) !l Ye = Yc + [R sin (0+01) 11 where, R \ \ ,, I / " / / ............ -..----,,;/ / ~ J (C,PX:p~: ~:lC=P:;:-y~~-;;-y-:-c"")2) ( 01 = tan (bfx-"=xe) (Parameter calculation: @ relative addressing) Calculate the center coordinates (dXc, dYc): dXc = Xc - CPx dYc = Yc - CPy Calculate the end point (dXe, dYe): dXe = dXc + [R cos (0+01) 11 dYe = dYc + [R sin (0+01) !l where, R = .j(CPx- XC)2+ (CPy- YC)2) ( 01 = tan- i (CPY- Yc \ CPx- Xe) [Example 3] Calculate parameters for an Arc that passes 3 points, (CPx, CPy) , (X, Y) and (Xe, Ye). (Xel"""Y......e_)--1-_ _ (Parameter calculation: Relative addressing) { dX = X - CPx dY = Y - CPy dYe dY - - - + - - 1 - - - - - - - - , ; 1 . (CPx, CPy) { dXe = Xe - CPx dYe = Ye - CPy 304 HITACHI " Calculate the center coordinates (dXc, dY c): ~X2 + ~ y2 = r2 (~X + dX)2 + (~Y + dY)2 = r 2 (~X + dXe)2 + (~Y + dYe)2 = r 2 where, dXc = [-~Xn 1 (dX2+dY2)"dYe- (dXe 2+dYe 2)"dY' [2" dX"dYe-dXe"dY 11 1 dYc = [- ~Yn 1 (dXe 2+dYe 2)"dX- (dX2+dY2)"dXe = [2" dX"dYe-dXe"dY n HITACHI 305 o Calculating Parameters of Ellipse Arc Commands AEARC a, b, Xc, Yc, Xe, Ye; REARC a, b, dXc, dY c, dXe, dYe; (Command Issuing Procedure) [Example 1] Given center coordinates (Xc, Yc), X direction axial length A, Y direction axial length B, drawing start angle (h \ (Xc, Vcl and drawing end angle ,, B (}2, calculate as follows " ' ..... .;;.::0...--+_-::;"-_ (counterclockwise rotation): _- (Parameter calculation: --"' (CPx, CPyl I / ." CD absolute addressing) • Calculate the axial length square ratio (alb): The ratio should be an integral ratio satisfying alb = A 2/B2, • Calculate the start point (CPx, CPy): { CPx = Xc + [A cos () 1 11 CPy = Yc + [B sin () 1 11 · Calculate the end point (Xe, Ye): { Xe = Xc + [.jaR' cos (}2 U Ye = Yc + [.Jb R' sin (}2 U R ' - J(·:;-O:C=P:--x---=X::-C~)2:--+---:(=C=Py---Y=-=C""')-::-2 ~ h were a b -.(Parameter calculation: A JL .Ja or .J6 CV relative addressing) • Calculate the start point (CPx, CPy): { CPx = Xc + [A cos () 1 CPy = Yc + [B sin (J 1 1]} ¢:JSame as in absolute addressing II Calculate the center coordinates (dXc, dY c): { dXc = - [A cos (J 1 II dY c = - [B sin (J 1 II • Calculate the end point (dXe, dYe): { dXe = dXc + [.Ja R' cos (J2 11 dYe = dYc + [.J6 R' sin (J2 U where R' = 306 HITACHI J(Cpx~ Xc) 2 + (Cpy; YC)2 •. $a or ~ /1 [Example 2] Given center coordinates (Xc, Yc), axial length square ratio alb, drawing start point (CPx, CPy) and drawing angle 0, calculate as follows (counterclockwise roration): (Xe, Ye!~)~F:::r--- ,- ,. / I t----'co.£'----(Cpx, CPy) I \ \ (parameter calculation: ,- , (Xc, Yc) CD absolute addressing) ',........ / ---- / I ",/ ----~ Calculate the end point (Xe, Ye): { Xe = Xc + [-Fa R' cos (0+01)1] Ye = Yc + [.Jb R' sin (0+01)1] where R' = J(CPx- Xc) 2 + (CPy- YC)2 a b 01 = tan-I (A.b CPx-Xc CPy-Yc) (Parameter calculation: (6) relative addressing) • Calculate { dXc = dYc = Calculate { dXe = dYe = the center coordinates (dXc, dY c): Xc - CPx Yc - CPy the end point (dXe, dYe): dXc + [-Fa R' cos (0+01)1] dYc + [.Jb R' sin (O+Ol)U where R' = J !-- @-- IRS T~ T4 -:uFUFU ~~U ~ 1~ ~IR!W T) Gj Vcc. 2.OV @- r- f-- ~I.- 2.2V @ 0.7V ~Ci.§)~ Vcc 20V O:BV @ '--- @-I----' 0.7V ~- f:=@~ \?Jl I{1/II. -I 1\\\' -l -++@r-@~ -I~ ;.... Vc,c20V O.BV Vcc·2.0Vl O.BV (1Ji.....l.- ©~®j ~(" O. V Vcc-2.OV INotel @ 2.2V, 0.7V+ - 2.2V 2.2V I@)tc " ~Vcc·2.0V ro \ o 7V @. 7V - r- 0.7 V\- rG9l - rf2.2V \0.7V I---@ 2.2V J O.7V @--1 I-----@ 2.2V 2.2V 0.7V " O.7V @- -;d @ O.BV ...0 @)l Vcc· 2.OV When the MPU read cycle immediately follows the MPU write cycle execution, DTACK and the read data responses are delayed (by 3 cycles of 2CLK) even though the spec, satisfied. Figure 3A @ MPU Read/Write Cycle Timing (MPU - ACRTC) ~iS "'DONE (OUTPUT) O.BV O.BV '"DONE (INPUT) *15'5NE.needs to be asserted "Low" while'i5AC'K remains "low:' DONE "Low" width must satisfy the spec. @. Figure 4 DMA Read Cycle Timing (Memory - ACRTC) T, 2CLK DREQ .\(\-jr~\ D ~ ~@ T, T, T, JV~W o 7V Tn'2 Tn·, ~ 22 R/W I i DACK @\ O.7V •- I I DTACK (READY) i l: ~ (') l: I " I/I T, Tn-2 Tn·, Tn T, To o 7V T, T, T, @- T, T, T, 07V ~ f-- @ ~V r- -@ If I @- I///t. Vee·20V \\\\'\ O.'BV 11 ~~~@ Vrr 20V OBIIj ~11 67) i--i-,,@ @ - @ O.BV -VI/I///I//////fj 1'-\\\\\\\\\\\\\\1 It O.7V a.BV 2.2V -\- B Vee. 2 .OV @ " /I I \ DONE (OUTP UTI IIIt III' O.BV i---'- I fJ O.BV @- " iT DONE (INPUT) Vee 2.DV \\W; @~--I-I-I @ io7V O.7V ==@:~ Vee· 2.OV I O.BV VII//. I-@r-@ --@~ ~-i1 @ B Vee. 2.OV - @ 0.7V -@ I-:::-1@ \ 0.7V 2.2V 2.2V O.7V VeC"2.0V'" OBV-J 11 ®- - I - - r- -@ @ @- f-- V0.7V \ ~@~ Vee20V " fi 1/ @-+--t @- ~ O.7V 2.2V -, O.7V 0.7V1 " O.7V ~I- 22V2~~ ~-= ~I-- @- @f-- @.- r-I-@.j.f-+.-@) 2.2V 0.7V Do - OH T, !Vee 20V - / T, Pv~W Q'--jr~\J ~V0H:;prvQ\JU~ T" @I-- DBV jI ,-~ ...1/ \~J Tn O.BV"" ~'"'w @ Vee· 2.OV t=1@ ~ ON} O.BV "OONE needs to be asserted "Low" while DACK remains "Low". DON E "Low" width must satisfy the spec (Note) @. DACK {"hIgh" width must satisfy the spec @ . Unless satisfying the sPec,@, DT ACK and the read data responses to the succeeding cycle are delayed. Whe~ AeRTe an~must Figure 4A DMA Read Cycle Timing (Memory ~ is used W.lth the synchronous bus timing, the speCification@,@ be satisfied ACRTC): Burst Mode I- -® :I: o Ol I I ~ I T, T" T, T, T, , I ..J \ -' 2CLK ...., w \.... I I Tn-2 r- Tn-1 Tn .j:>. co f' !'> :I: o Ol w .j:>. co .j:>. .m :I: O.8V o Ol ~ w .j:>. 2.2V co co f' RiW @) 9 @ I } 2.2V 2.2V O.7V O.7V 2.2V O.7V O.7V O.8V __________________ ~I~----------------~ } i'i'5NE (OUTPUT) O.8V O.BV } 11 i5i'iN'E (INPUT) O.7V *5Q"N'E needs to be asserted "Low" while 'i5"'AC"K remains "Low". D'C5N'E "Low" width must satisfy the spec. Figure 5 DMA Write Cycle Timing (Memory ~ ACRTC) @. (..105) T. 2CLK DREQ O. T: T, T, Tn-2 Tn-1 T, 0.8V RiW T, T, Tn-2 Tn-l T, Tn T, Te " @-tl-- , DACK - @ T, T, (106) T, T, 2.2V 0.7V I @ J: , DTACK (READY) J: I II" .... I--@- 2.2V 2.2V 2.2V 0.7V 0.7V 0.7V @ @ @ 0.8V @Arr.2.0V 0.8V r@1 0.7V - r- 1\22V I- I-@ II ~ O.7V i--=- \ if---7- ' 0 V ~ @ @v~ .w~rw @ Vee· 2.OV 0.7V II @ II @ -l2.2V 2.2V 0.7V 0.7V @ DONE (OUTPUT) DONE (INPUT) 2.21 2.2V 2.2V l ,'/ -, t "" @-1-1-- @I-- -@- 2.2V 0.7V-I- @ "" -I- 0.7V T, rv-u ~ @~H .-' -@. T. Vee 2 OV t 2. 2V ~ l -I- 2.2V2.2V 0.7V 0.7V --I em.!.I @~H 1\22V @ =- ±®: -.= l - I- -~ 00 - DIS !'tt . 2 . 2V @ : @- HH@ 2.21 I ~ II 1/ I - T, ~ , ~ (") T•. \f\F·,-Furui.\F\"JPu~~r·up..JU ~u I •- Tn 0.8V -@O-o.7---1J °DONE needs to be asserted "Low" while DACK remains "low". DON E "low" width must satisfy the spec @ . (Note) Figure 5A DMA Write Cycle Timing (Memory - @. ctQ§). DACK "high" width must satisfy the spec, unless satisfying the spec. OTA!=K response to the succeedmg cycle is delayed. WheJ!-1b.!!. AeRTe is used with the synchronous bus timing, the specification~ and(..~must be satisfied. • ACRTC): Burst Mode HD63484-4,HD63484-6,HD63484-8----------------------------- 2CLK . MAD MA/RA MCYC MRD DRAW Figure 6 Screen Display Cycle Timing 2CLK MAD. - MAD" MA,. IRA. MA ,2 /RA, MA ,./RA 2 MA,./RA J RA. . MCYC MRD O.BV Figure 7 14 Frame Memory Read Cycle Timing (ACRTC +- Frame Memory) _HITACHI O.8V - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ HD63484-4,HD63484-6,HD63484-8 0.7V 2CLK "cc- 2.OV O.BV Data MADo - MADIS _ _ _ _ _~~--< MA,./RAo MAI7 IRA, - - - - - - - f - - - - , . ir.-v,.,...cc-.=2.-=0.,...V,..----+---------l-:--.I MA .. /RA, .BV MA,. IRA, _ _ _ _ _-I_-..J RA. MCYC MRD O.BV Figure B Frame Memory Write Cycle Timing (ACRTC - Frame Memory) Refresh Cycle Attribute Control Information Output Cycle 2CLK AS MAD----+-~ IF~-:.:.::.:;;.:..::.:~I MA/RA MCYC MRD DRAW _ _ _ __+_.!~ *When AS is "High", a "0" :>utput is given. Figure 9 Frame Memory Refresh/Attribute Control Information Output Cycle Timing $ HITACHI 15 HD63484~4,HD63484-6,HD63484-8 ----------------------------- 2CLK MCYC EXSYNC (OUTPUT) CHR Figure 10 Display Control Signal Output Timing 2CLK HSYNC (SLAVE) (Sync Cycle) T1 T2 T3 T4 T5 T6 2CLK EXSYNC MCYC MCYC (When the leading edge of EXSYNC enters this period, ACRTC shifts the internal phase according to the above sequence.) Figure 11 16 EXSYNC Input Timing ~HITACHI -----------------------------HD63484-4,HD63484-6,HD63484-8 Single Access Mode (Light Pen Rise Cycle) 2CLK M LPSTB ~L..L..I"'"'t-=-"'--------- _ _ _~ 0.7V When LPSTB rises in this period, memory address "M + 2" is set in the Light Pen Address register. Figure 1 2 LPSTB Input Timing Interleave Mode/Superimpose Mode (Dual Access Mode 0/1) t-----One Displaying Period--------<~ 2CLK M LPSTB LPSTB (2) Note 2 Note 1: When LPSTB rises in the period (1), memory address "M + 1" is set in the Light Pen Address register. Note 2: When LPSTB rises in the period (2), memory address "M + 2" is set in the "Ligyt Pen Address register. Note 3: I n the Interleave Mode, memory address "M"; "M + 1", "M + 2" denote the display address. In the Superimpose Mode, memory address "M", "M + 1", M + 2" denote the display address of the background screen. Figure 1 2A LPSTB Input Timing ~HITACHI 17 HD63484-4.HD63484-6.HD63484-8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @ ,® .\ I O.7V O.7V ® 2.2V \ Figure 13 O.7V O.7V RES Input and ~ Input Timing (System Reset and 16-bit/8-bit Selectiol)l 2ClK Figure 14 iAn Output Timing Signal 5.0V 00-015 DTACK DREQ , MAD o-MAD I5 MA1S/RAo-MAI9/RA3 RA4 'VSYNC.HSYNC EXSYNC MCYC, AS. MRD DRAW, CHR DISP l' DISP 2 CUD 1• CUD 2 Figure 15 18 Test Load Circuit A _HITACHI Load Condition RL = 1.8kfl C = 40pF R = 10kfl All diodes are 1S2074@'s or the equivalent. ------------------------------HD63484-4.HD63484-6.HD63484-8 5.0V MAD 0 1---'I1\fu-_ _ MAD 15 ...--"",,-- ACRTC IRQ. DONE O~--------~ r Figure 16 { RL = 1.8kO C 40pF = Damping Resistors (500 .....: 1000) Test Load Circuit B Figure 19 Damping Resistors (3) Power Supply Circuit NOTE FOR USE When designing Vee and Vss pattern of the circuit board, the capacitors need to be located nearest to pin 14 (Vee) and pin 16 (V ss) or pin 51 (V ss) and pin 49 (Vee) as shown in the figure 20. (1) Power-on Sequence Following condition needs to be satisfied when the power turns-on. lpF/35V Tantalum Capacitor (2 pairs) 1f1 EH lOOms Figure 20 • • Figure 1 7 Power-on Sequence' (2) Output Waveform In case that ringing noise occurs beyond tolerance on CRT data buses (MAD o - MAD I5 , MA16/RAo - MA I9 /RA a, RA 4 ), damping resistors may be required for data buses as shown in the figures below. Vout Ringing Noise I Figure 1 8 Ringing Noise Note: The ringing level depends on the load capacity. and it can be V OH + 0.1 V. Note for Designing Power Supply Circuit ACRTC INTRODUCTION HD63484 (ACRTC) FEATURES Powerful visual interfaces are a key component of advanced system architectures. A proven technique uses raster scanned CRT techI'lOlogy for the display of graphics and text information. Systems which use first generation CRT Controllers (CRTCs) are constrained by hardware/software design time, manufacturing cost, and limited MPU bandwidth. To meet the functional requirements for powerful visual interfaces, and to support their use in high volume, cost sensitive applications, advanced circuit design and VLSI CMOS manufacturing technologies have been used to create a next generation CRTC, the HD63484 ACRTC (Advanced CRT Controller). The ACRTC concept is to incorporate major functionality, formerly requiring external hardware and software, on-chip. In this way, both higher performance and reduced system cost benefits are achieved. • High Level Command Language Increases Performance and Reduces Software Development Cost. - ACRTC Converts Logical X- Y Coordinates to Physical Frame Buffer Addresses. 38 Commands including 23 Graphic Drawing Commands LINE, RECTANGLE, POLYLINE, POLYGON, CIRCLE, ELLIPSE, ARC, ELLIPSE ARC, FILLED RECTANGLE, PAINT, PATTERN and COPY. - On-chip 32 Byte Pattern RAM. - Conditional Drawing function (8 conditions) for Drawing Patterns, Color Mixing and Software Windowing. - Drawing Area Control with Hardware Clipping and Hitting. - Maximum Drawing Speed of 2 Million Logical Pixels per ~HITACHI 19 HD63484-4.HD63484-6.HD63484-8-----------------------------Second is the same for Monochrome and Color applications. • High Resolution Display with Advanced Screen Control - Up to 4096 by 4096 Bit Map GRAPHIC Display and!or 256 Line by 256 Character by 32 Raster CHARACTER Display. - Separate Bit Map GRAPHIC (2M byte) and CHARACTER (128k byte) Address Spaces with Combined GRAPHIC! CHARACTER Display. - Three Horizontal Split Screens -and One Window Screen. Size and Postition Fully Programmable. - Independent Horizontal and Vertical Smooth Scroll for each Screen. - 1 to 16 Zoom Magnitude - Independent X and Y Zoom Factors. - Logical Pixel Specification as I, 2, 4, 8 or 16 Bits for Monochrome, Gray Scale and Color Displays. Programmable Address Increment Supports Frame Buffer Memory Widths to 256 Bits for Video Bit Rates > 500 MHz. (ACRTC R MASK is limit to 128 Bits.) Unique Interleaved Access Mode for Screen Superimposition or 'Flashless' Displays. - ACRTC provides Dynamic RAM Refresh Address. • High Performance MPU Interface - Optimized Interface with the HD68000 MPU and HD68450 DMAC. 8 or 16 Bit Bus - Compatible With Other MPUs. Separate on-chip 16 Byte READ and WRITE FlFOs. Maskable Interrupts Including FIFO status. * Versatile CRT Interface - Full Programmability of CRT Timing Signals. - Three Raster Scanning Modes. - Master or Slave Synchronization to Multiple ACRTCs or Other Video Generating Devices. - Two Hardware Cursors. Three Cursor Modes. Programmable Cursor and Display Timing Skew. - Eight User Defineable Video Attributes. - Light Pen Detection. * VLSI CMOS Process OS or applcation software. At this layer, a number of popular standards have emerged including GKS, CORE, NAPLP, GSX and others. Figure 21 shows how the ACRTC performs the key functions or logical drawing algorithm and physical drawing execution. Formerly, these function were performed by external hardware and! or MPU software. As shown, the ACRTC reduces the 'gap' between device functionality and high level graphics procedures. Since the ACRTC device itself provides capabilities closely related to those of high level graphics packages, the effort (hardware and software design time and cost) required to develop a visual interface is significantly reduced. Noting the traditional and emerging applications for visual interfaces, Figure 22 shows that a single ACRTC is suitable for a broad range of products in both alphanumeric ~nd graphics areas. Multiple ACRTCs can achieve performance beyond that of any first generation CRTC configuration. • APPLICATIONS • Drawing Procedures MPU Co-ordinates Soft- conversion MPU Drawing Pre-process Soft- Drawing Process ware ware (Algorithms) Drawing Execution . ACRTC Display Control Synchronizing CRTC Signals Generation Others Figure 21 ACRTC vs. CRTC The overall function of a visual interface is logically partitioned into layers. At the lowest layer are CRT timing and control signal generation. At the top layer are general purpose drawing procedures which provide a high-level interface to the users 20 $ Flight Simulator Work Station CAD/CAM Terminal Game Machine Business Computer High-end Personal Computer Word Processor Videotex Character CRTC Dumb Terminal Applications Figure 22 • ACRTC Coverage Application Spectrum SYSTEM CONFIGURATION Existing CR TCs provide a single bus interface to the frame buffer which must be shared with the host MPU. However, the refresh of large frame buffers and the requirement to access the frame buffer for drawing operations can quickly saturate this shared bus bandwidth. As shown, the ACRTC uses separate host MPU and frame buffer bus interfaces. This allows the ACRTC full access to the frame buffer for display refresh, DRAM refresh and drawing operations while minimizing the ACRTCs usage of the MPU system bus. Thus, overall system performance is maximized. A related benefit is that a large frame buffer (2M byte for each ACR TC) is useable even if the host MPU has a smaller address space or segment size restriction. The ACRTC can utilize an external DMA Controller. This increases system throughput when large amounts of command, parameter and data information must be transferred to the ACRTC. Also, advanced DMAC features, such as the HD68450 DMACs 'chaining' modes, can be used to develop powerful graphics system architectures. However, more cost sensitive or less performance sensitive applications do not require a DMAC. The interface to the ACRTC can be handled completely under MPU software control. While both ACRTC bus interfaces (Host MPU and Frame Buffer) exploit 16 bit data paths for maximum performance, the ACRTC also offers an 8 bit MPU mode for easy connection to popular 8 bit bus structures. HITACHI -----------------------------HD63484-4,HD63484-6,HD63484-8 • INTERNAL FUNCTIONS • BLOCK DIAGRAM MA,o-MA,. CPU The ACRTC consists of five major functional blocks. These functional blocks operate in parallel to achieve maximum performance. Two of the blocks perform the external bus interface for the host MPU and CRT respectively. a MPU Interface Manages the asynchronous host MPU interface including the programmable interrupt control unit and DMA handshaking (S/16b) System Memory ACRTC Video Signal DMAC Figure 23 System Configuration RES j - - Drawing Address f- DMA Control I- Unit Register Address f-- - r- 20 Drawing Processor Data Interrupt Control Unit 16 ~ Draw Enable Write I- '-- ~ ~~ - i-.. RIW - l- - f- ' - - DRAW I- ,..- MRD ~ ~ MADo-MAD,. /RA o~ :=::::> MA'6 MA,glRA 3 Display Address f- f - - - f- - RA. I- - CHR 20 ~ ;::: f ' Display Processor ~ l- - RS f Drawing Data MPU Interface Raster Address 5 CHR m CRT Interface CCUD , I- I--- LPSTB f- ~ CUD" I- cmr; GCUD 2 HSYNC VSYNC C::: F==; L-....., EXSYNC Timing Processor DISP 2 MCLK AS 2CLK r f- f-f- I-- VSYNC f- ~ EXSYNC f- ~ f- I-- MCYC f- f - - f- I--- 2CLK f2 Vee Vss Figure 24 Block Diagram _HITACHI 21 H D 6 3 4 8 4 - 4 . H D 6 3 4 8 4 - 6 . H D 6 3 4 8 4 - 8 - - - - - - - - - - - - - - - - - - - - - - - - - -_ __ control unit. o CRT Interface Manages the frame buffer bus and CRT timing input and output control signals. Also, the selection of either display refresh address or drawing address outputs is performed. The other three blocks are separately microprogrammed processors which operate in parallel to perform the major functions of drawing, display control and timing. o Drawing Processor Interprets commands and command parameters issued by the host bus (MPU and/or DMAC) and performs the drawing operations on the frame buffer memory. This processor is responsible for the execution of ACRTC drawing algorithms and conversion of logical pixel X-V addresses to physical frame buffer addresses. Communication with the host bus is via separate 16 byte read and write FIFOs. o Display Processor Manages frame buffer refresh addressing based on the user programmed specification of display screen organization. Combines and displays as many as 4 independent screen segments (3 horizontal splits and 1 window) using an internal high speed address calculation unit. Controls display refresh address outputs based on GRAPHIC (physical frame buffer address) or CHARACTER (physical frame buffer address + row address) display modes. o Timing Processor Generates the CRT synchronization signals and other timing signals used internally by the ACRTC. The ACRTCs software visible registers are similarly partitioned and reside in the appropriate internal processor depending on function. The registers in the Display and Timing processors are loaded with basic display parameters during system initialization. During operation, the host primarily communicates with the ACRTCs Drawing processor via the on-chip FIFOs. CRT INTERFACE Following is a brief description of the ACRTC pin functions organized as MPU Interface, DMAC Interface, CRT Interface and Power Supply. 2CLK - Input Basic ACRTC operating clock derived from the dot clock. MADo - MAD I5 - Input/Output Multiplexed frame buffer address/data bus. AS - Output Address strobe for demultiplexing the frame buffer address/ data bus (MADo - MAD I5 ). MAls/RAo - MAI9/RAa - Output The high order address bits for graphic screens and the raster address outputs for character screens. RA4 - Output Provides the high order rasier address bit (up to 32 rasters) for character screens. CHR - Output Indicates whether a graphic or character screen is being accessed. MCYC - Output Frame buffer memory access timing - one half the frequency of 2CLK. MRD - Output Frame Buffer data bus direction control. DRAW - Output Differentiates between drawing cycles and CRT display refresh cycles. UlS'P'I, ~ - Output Programmable display enable timing used to selectively enable, disable and blank logical screens. CUD I, CUD2 - Output Provides cursor timing determined by ACRTC programmed parameters such as cursor definition, cursor mode, cursor address, etc. . VSYNC - Output CRT device vertical synchronization pulse. HSYNC - Output CRT device horizontal synchronization pulse. EXSYNC - Input/Output For synchronization between multiple ACRTCs and other video signal generating devices. LPSTB - Input Connection to an external light pen. MPU INTERFACE VIDEO ATTRIBUTES RES - Input Hardware reset input to the ACRTC. Do - D I5 - Input/Output The bidirectional data bus for communication with the host MPU or DMAC. In 8 bit data bus mode, Do - D7 are used. R/W - Input Controls the direction of host - ACRTC transfers. CS - Input Enables data transfers between the host and the ACRTC. RS - Input Selects the ACRTC register to be accessed and is normally connected to the least significant bit of the host address bus. DT ACK - Output Provides asynchronous bus cycle timing and is compatible with the HD68000 MPU DT ACK input. mQ - Output Generates interrupt service requests to the host MPU. The ACRTC outputs 20 bits of video attributes on MADo MAD I5 and MAI6/RAo - MAI9/RAa. These attributes are out- • SIGNAL DESCRIPTION MA'6 MAD,s BLlNK2 BLlNKl SPL2 SPL1 HZ3 MAD'2 MAD" HZO HSD3 MA'9 MA'8 MAn } Blink } Split Screen Number } H.ri••""" Z.~ } H.ri",.", "'~II D~ HSDO ATC7 DMAC INTERFACE 1'5REQ - Output Generates DMA service requests to the host DMAC. DACK - Input Receives DMA acknowledge timing from the host DMAC. DONE - Input/Output Terminates DMA transfer and is compatible with the HD68450 DMAC DONE signal. 22 _HITACHI Attribute Code ATCO Figure 25 Video Attributes ------------------------....:....----HD63484-4.HD63484-6.HD63484-8 put at the last cycle prior to the rising edge of HSYNC and should be latched externally. Thus, video attributes can be set on a raster by raster basis. accomplished by the ACRTC repeating a single display address and using the HZ outputs to control the external shift register clock. Horizontal zoom can only be applied to the Base screen. . Attribute Code (ATCO-ATC7:MAD o - MAD 7) These are user defined attributes. The programmed contents of the Attribute Control bits (ATR) of the Display Control Register (DCR) are output on these lines. Note) The data written into ATR can be externally used after the completion of.current raster scanning. Attribute Code (ATC7-ATCO) Application ATC is one of the function to provide the with application to the user and appropriate data need to be employed depending on the system requirement. Followings show some of application example. (1) Amount of horizontal dot shift for window smooth scroll. (2) Horizontal width of crosshair cursor and the amount of horizontal dot shift (including Block cursor). (3) Frame buffer specification in blocks (used for the base register). . (4) Back screen color or character color code. (5) Display screen selection during screen blink (used with SPL). (6) Interrupt vector address storage. (7) Polarity selection of horizontal/vertical synchronization signal etc. (8) Blinking signal like lamps used in the system. (9) Code storage (max. 8 bit) or selection signal etc. Split Position (SPLl-SPL2:MA16 - MA17 ) These lines present the encoded information showing the enabled background screen currently being displayed by the ACRTC. Horizontal Scroll Dot (HSDO-HSD3:MAD 8 - MAD Il ) These are used in conjunction with external circuitry to implement smooth horizontal scroll. These lines contain the encoded start dot address which is used to control the external shift register load timing and data. HSD usually corresponds to the start dot address of the background screens. However, if the window smooth scroll (SWS) bit of OMR (Operation Mode Register) is set to 1, HSD outputs the start dot address of the window screen segment. Note) HSD outputs the valid value only within the specified raster area. Changing the register contents during the scanning does not cause any external effects, because the value loaded at the beginning of the area is reserved. Horizontal Zoom Factor (HZO-HZ3:MAD12 ~ MAD 15 ) These lines output the encoded 0-16) horizontal zoom factor as stored in the Zoom Factor Register (ZFR). Horizontal zoom is SPL2 SPLl o o 1 I o 1 o 1 Background Screen not enabled or displayed Base Screen Upper Screen Lower Screen Even if the split screen display is- prohibited, SPL is output if the area is specified. Blink (BLINKI-BLINK2:MA 18 - MA19 ) The lines alternate from high to low periodically as defined in the Blink Control Register (BCR). the blink frequency is specified in units of 4 field times. A field is defined as the period between successive YSYNC pulses. These lines are used to implement character and screen blink. • ADDRESS SPACE The ACRTC allows the host to issue commands using logical X-Y coordinate addressing. The ACRTC converts these to physical linear word addresses with bit field offsets in the frame buffer. Figure 26 shows the relationship between a logical X-Y screen address and the frame buffer memory, organized as sequential 16 bit words. The host may specify that a logical pixel consists of 1, 2. 4, 8 or 16 physical bits in the frame buffer. In the example, 4 bits per logical pixel is used allowing 16 colors or tones to be selected. . Up to four logical screens (Upper, Base, Lower and Window) are mapped into the ACRTC physical address space. The host specifies a logical screen physical start address, logical screen physical memory width (number of memory words per raster), logical pixel physical memory width (number of bits per pixel) and the logical origin physical address. Then, logical pixel X-Y addresses issued by the host or by the ACRTC Drawing processor are converted to physical frame buffer addresses. The ACRTC also performs bit extraction and masking to map logical pixel operations (in the example, 4 bits) to 16 bit word frame buffer accesses. _HITACHI 23 Logical Addressing Physical Addressing (Frame Buffer) Display Screen bit o r y -~~,y) /- -V I 1 pixel data - Origin ,I x MW 'T1 ICc: • % ~ ~ - iil i') m b (Q rr til l~~ /- :::: ." J Q. Q. iil en en :r (Q MW -------------- --------- x HD63484-4,HD63484-6,HD63484-8 • REGISTERS 7 15 I} I 0 I Address R!!llister I Status Register 0 ... [~~-___-_-___-_F(9~i!ri~=====~ ~ I I I Command Control Register I 0E!eration Mode Re~ister I l Display Control Register Timing Control RAIiil Raster Counter Horizontal Sync. Horizontal Display Vertical Sync. o 15 Hardware / ' Access ........ ......."" .... ... "'," Write FIFO .... \ \~~: ,......._------------' \ \ \ Read FIFO \ \ \ \ \ Vertical Display. Split Screen Width I Blink Control Horizontal Window Display ~t Command Register J / Vertical Window Display Direct >Access Control Register Graphic Cursor Display Control RAM Split Screen 0 Control (Upper Screen) Spl it Screen 1 Control (Base Screen) Pattern RAM 16 x 16 "- Split Screen 2 Control (Lower Screen) Color 0 Color 1 Color Comparison Edge Color Mask Split Screen 3 Control (Window Screen) Pattern R AM Contra I Drawing Parameter Register Block Cu rsor Cursor Definition Zoom Facter "- FIFO Access Area Definition Read/Write Pointer Light Pen Address Drawing Pointer Current Pointer Figure 27 Programming Model _HITACHI 25 HD63484-4.HD63484-6.HD63484-8----------------------------Table 1 cs RS~W Reg. No. I - Programming Model (Hardware Access. Direct Access Registers) Abbre. Register Name AR I SR '/0 rOO v r02 1./0 r04 l~·O r06 r08 °° °° ° h-;"...-;-;-~..--rD';';AT"'AT-7(H"')'r-;,;;-r-;;-.,.,,-+~...-,,-,--.--rDA..:,.T:c.AT__';;(L"')T__;;_r_.,__...,_,,...., IS I 14 I 13 I 12 I 11 I 10 I 9 I 8 AR SR FE CCR OMR OCR Address Register Status Register FIFO ERtry Command Control Operation Mode Display Control ABT/pSEjDDMjCDMIDRCI M/SI STRIACPIWSSI CSK DSPI SE II SE~ I SE2 7 I 6 I 5 I 4 I 3 I 2 I I I ° Address CERIARDICEDILPDIRFFIRFRIWFRIWFE FE GBM CREIARE CEE LPE RFE RRE WREIWEE I DSK RAMI GAl I ACM I RSM AT R I SE3 - L (undefined) r1E I rSO Raster Count RCR .. -------I RC .... -- .. _-- I 1~ i> r82 Horizontal Sync. HSR HC HSW r84 Horizontal Di splay HDR H0 S H0 W I 1/0 r86 Vertical Sync. VSR ---------I VC r.-!."'-"'U!-·r::-;;88~-Ve.:..cr-'-ti.:..cca~1~D~iS~PI~ay======~"iV~D"'R~'---_t_---------~---------~-=V~-.!D~-;-=S".:..---------------------------------:------:.--------~~~~-------------:-----------------------.V'---;-=S~"'W.;.-~------..::__I-/ .. I .---_ .. _--- I I/O rSA ---------I S P I ~~ Split Screen Width SSW -'-::-:-::-::-:-::--f-~--.----------;~~::-i~~---.-------I r.-,-"'o!-r~9~0~BI"in7k·C'o-nt~ro~I------~~BvC~R~!-----;B~0N~1------I1!----~B~O~F~FI~:~-·~~~BO~N~2~---,I- -BOF~ r.-l/-"0!-r~9~2~Ho~ri~zo~nt~al~W~in.:..cd-ow-O~i~-I~ay--~H~W~R~!----~~~~H~W~S~~~~---+-I--~~~---~H~W~W~--=~~-----I 1"01 r94 I V WS 1/0 r96 Vertical Window Display VWR f----'-' __-----.0-.0 "-__-___-__-_----II----------+.V-7 ;.:;;,W,----------W i'~1 r98 --·-!-----!----------~C~X·E~---------,------~~~C~Xo~S----------~ ~ Graphic Cursor l~O' r9C ~ -I :;~ ° I I (undefined) 1'01 rCO Raster Addr.O Upper Memory Width Screen Start Addr.O ~ i' ~'-';&- ~. !l01 rC8 I i'01 rCA I Base 11.01 rCC Screen .10 rCE l' 0, rOO " 0' rD2 : Lower rD4 'Screen "0 ,:: ::t ---------- Raster Addr.1 Memory Width Start Addr I I 'Raster Addr.2 Memory Width ::::~.::, .0-.0.0--- GCR I C YS I C YE I I I --.0.0° I==----.o ~-:-I 1RARf": --.0-.0 RARO MWRO SARO ",,"v I I -- -. -~ -- ..... ------.----------L RA0 I --.0---.0.0- I ----=o-:-~c-----I T-_-__ F_R_A--'O'---_--I ._ _:..::Mc.:W'-O=--,-_---=c SO A -.0-.0.0.0.0 I SAOHiSRAO--SAO L ~_L R A I -m---.o.o-_L-_ F R A I I~RI ICHRI_~~:.:..._+_-----MWI_ __-_ _ _ _ __ I SARI f----.:.::.::-~-.:.......--j-- ~~.! _...l..._.:..:.::..:::..::..:.-::::::T"_ ~lt:!/SRA1..__ _ f--___=S__A-,-I_=L=--____-.-_ _--:=--::-::-:o-_ _...., RAR2~---I -'=B._~_2___..L --.0-.0.0.0F RA 2 I 21 MWR~J.C~_:=:=-=--f M W.2. . I I __ .om _ SO A 2 ~ .0-----.0.0- I SA2H.'SRA2 . ---.J o-==r '::::L. . ~- _"" -'-'L=",~c~" ~ ~!":~::: :~~;.,";-~s~:~:.:t=~~'~:'::s~~t::~-.~'"~"'~=-~----j ° i' 11 rEO ° rE2 Block Cursor I l' 0 rE4 Block Cursor-2--- BCURli--.!l...£.~~-_----B~~~--. ....:.:.:..:.-.~::.:::..:- _~ __ . BCA I BCUR2; __BC~_~ -:-:T:~---B~ ~H.l:==r:::..:_-:~~-::: _:::I__==-BIE·~ 2 _ ~: ::: ftc,."",,,,,.!"".:. :-.= oj,.. j:-'-=-T-'"ii-T:~''' ' l'---,·:::::r ",,,~,,,,;~~ Z~I11_t:a~tor _____ .o I 1\0 I ,~J Light Pen : I ~lL;j~i- 1- t 1 Address ZFR +---fil--~=_.o};~~~~Lf-LPAR f - - - - - - - - · - (undefined) _L_L~___ ! ~ ~-:-:":::+-:":'-Tp A H-..L_.____ --- .- ._ _ _ _ _ _ _ _ _ _--1 ------------------------ ___.________.____________...J Not e ; I ...... "High" level ~ 0""" "Low" level 26 CHR - ___ _ _ _ . _ - - - - t - - - - - - - - - - - - - - L - P A L _HITACHI HD63484-4,HD63484-6,HD63484-8 ABT spa, SP1, SP2 : Abort : Split Screen a Widttl, Split Screen I Width, Split Screen 2 Width ACM : Access Mode ACP : Access Priority Address: Register No. of the control register BOFF!, BOFF2 : Blink ON 1. B link ON 2 : Blink OFF 1, Blink OFF 2 BON 1, BON2 ARD : Area Detect HWS : Horizontal Window Start ARE : Area Detect Interrupt Enable HWW : Horizontal Window Width ATR : Attribute Control VWS : Vertical Window Start CDM : 'Command DMA Mode VWW : Vertical Window Width CED : Command End : Cursor X Start. Cursor V Start CEE : Commad End Interrupt Enable CXS, CVS CXE, CVE CER : Command Error FRA : First Raster Address CRE : Command Error Interrupt Enable LRA : Last Raster Address : Cursor X End, Cursor Y End CSK : Cur sor Display Skew CHR : Character DDM : Data DMA Mode MW : Memory Width DRC : DMA Request Control SDA : Start Dot Address DSK : DISP Skew SAH(SRA : Start Address DSP : DISP Signal Control SAL : Start Address "Low" "High" IStart Raster Address FE : FIFO Entry BCWI. BCW2 : Block Cursor Width 1. Block Cursor Width 2 GAl : Graphic Address Increment Mode BCSR 1, BCSR2 : Block Cursor Start Raster 1. Block Cursor Start GBM : Graphic Bit Mode HC : Horizontal Cycle BCERI. BCER2 HDS : Horizontal Display Start : Block Cursor End Raster 1, Block Cursor End Raster 2 HDW : Horizontal Display Width BCAI. BCA2 : Block Cursor Address 1. Block Cursor Address 2 HSW : Horizontal Sync. Width CM : Cursor Mode LPD : Light Pen Strobe Detect CONI. CON2 : Cursor ON 1. Cursor ON 2 LPE : Light Pen Strobe Interrupt Enable COFF!, COFF2 : Cursor OFF 1. Cursor OFF 2 MIS : Master ISlave HZF, VZF PSE : Pause LPAH : Horizontal Zoom Factor, Vertical Zoom Factor : Light Pen Address "High" RAM : RAM Mode LPAL : Light Pen Address "Low" RC : Raster Count RFE : Read FIFO Full Interrupt Enable RFF : Read FIFO Full RFR : Read FIFO Ready RRE : Read FlFO Ready Interrupt Enable RSM : Raster Scan Mode SEa : Split Enable SE I : Split Enable I Raster 2 a SE2 : Split Enable 2 SE3 : Split Enable 3 STR : Start VC : Vertical Cycle VDS : Vertical Display Start VSW : Vertical Sync. Width WEE : Write FIFO Empty Interrupt' Enable WFE : Write FIFO Empty WFR : Write FIFO Ready WRE : Write FIFO Ready Interrupt Enable WSS : Window Smooth Scroll _HITACHI 27 H D 6 3 4 8 4 - 4 , H D 6 3 4 8 4 - 6 , H D 6 3 4 8 4 - 8 - - - - - - - - - - - - - - - - - - - - - - - - - -_ _ __ Table 1 (cont.) Register No. Readl Write Programming Model (Drawing Parameter Registers) Name of Register Abbr. Data (H) Pattern RAM Control Pr07 Pr08 R/W ADR Area Definition .. PrOB PrOC R/W PrOD RWP Read Write Pointer PrOE ............ PrOF Prl0 R Prl1 Pr12 R Pr13 DP Drawing Pointer CP Current Pointer •• Pr14 Pr15 B· ... Always set to "0" . Set binary complements for negative values of X and Y axis. DRAWING PARAMETER REGISTER R : Register which can be read by Read Parameter Register Command (RPR) W : Register which can be written into by Write Parameter Register Command (WPR) : Access IS not allowed CLO : Defines the color data used for the drawing when logical drawing data =0 CLl : Defines the color data used for the drawing when logical drawing data = 1 CCMP : Defines the comparative color of the drawing operation : Defines the edge color EDG MASK 28 PSX. PSY : Defines \he bit pattern used to mask bits upon which data transfer should not be performed : Pattern Start Point PEX, PEY : Pattern End Point PPX. PPY : Pattern Scan Start Point PZX. PZY : Pattern Zoom PZcx, PZCY : Pattern Zoom Count XMIN. YMIN : Start point of Area definition XMAX. YMAX : End point of Area definition DN : Screen Number RWPH : High·order 8 bit of Read Write Pointer Address RWPL : Low-order 12 bit of Read Write Pointer Address DPAH : High·order 8 bit of Drawing Pointer Address DPAL : Low·order 12 bit of Drawing Pointer Address DPD : Drawing Pointer Dot Address X. Y : Position indicated by Current Pointer on X·Y coordinate _HITACHI Data (Ll The ACRTC has over two hundred bytes of accessible registers .. These are organized as Hardware, Directly and FIFO accessible. o Hardware Accessible The ACRTC is connected to the host MPU as a standard peripheral which occupies two word locations of the host address space. The RS (Register Select) pin selects one of these two locatio~s. When RS is low, reads access the Status Register and writes access the Address Register. The Status Register summarizes the ACRTC state and is used by the MPU to monitor the overall operation of the ACRTC. The Address Register is used to program the ACRTC with the address of the specific directly accessible register which the MPU wishes to access. o Directly Accessible These registers are accessed by prior loading of the Address Register with the chosen register address. Then, when the MPU accesses the ACRTC with RS= 1, the chosen register is accessed. T~e FIFO entry enables access to FIFO accessible registers usmg the ACRTC read and write FIFOs. The Command Control Register is used to control overall A~RTC operation such as aborting or pausing commands, definmg DMA protocols, enabling/disabling interrupt sources, etc. The Operation Mode Register defines basic parameters of ACRTC operation such as frame buffer. access mode, display or drawing priority, cursor arid display timing skew factors, raster scan mode, etc. The D.ispla~ Control Register allows the independent enabling and disabling of each of the four ACRTC logical display scree~s (Base, l!pper, Lower and Window). Also, this register con tams the 8 bits of user defineable video attributes. The Timing. Control RAM contains registers which define ACR TC . timing. This includes timing specification for CRT control signals (e.g. HSYNC, VSYNC), logical display screen size and display period, blink timing, etc. The Display Control RAM contains registers which define logical screen display parameters such as start addresses, raster addresses and memory width. Also included are the cursor(s) definition, zoom factor and light pen registers. o FIFO Accessible For high performance drawing, key Drawing Processor registers are coupled to the host via the ACRTCs separate 16 byte read and write FIFOs. . ACRTC commands are sent from the MPU via the write FIFO to the Command register. As the ACRTC completes command execution, the next command is automatically fetched from the FIFO into the Command register. The Pattern RAM is used to define drawing and painting 'patterns'. The Pattern RAM is accessed using the ACRTCs Read Pattern RAM (RPTN) and Write Pattern RAM (WPTN) register access commands. The Drawing Parameter Registers define detailed parameters of the drawing process, such as color control, area control (hitting/clipping) and Pattern RAM pointers. The Drawing Parameter Registers are accessed using the ACRTCs Read Parameter Register (RPR) and Write Parameter Register (WPR) register access commands. • COMMANDS The ACRTC has 38 commands classified into three groups REGISTER ACCESS, DATA TRANSFER and GRAPHIC DRAWING. Five REGISTER ACCESS commands allow access to Drawing processor Drawing Parameter Registers and the Pattern RAM. Ten DATA TRANSFER commands are used to move data between the host system memory and the frame buffer, or within the frame buffer. Twenty three GRAPHIC DRAWING commands cause the ACRTC to perform drawing operations. Parameters for these commands are specified using logical X- Y addressing. All the above commands, parameters and data are transferred via the ACRTC read and write FIFOs. Assuming the ACRTC has been properly initialized, the MPU must perform two steps to cause graphic drawing. First, the MPU must specify certain drawing parameters which define a number of details associated with the drawing process. For example, to draw a figure or paint an area, the MPU must specify the drawing or painting 'pattern' by initializing the ACRTC Pattern RAM and related pointers. Also, if clipping and hitting control are desired, the MPU specifies the 'area' to be monitored during drawing by initializing area definition registers. Other drawing parameters include color, edge definition, etc. After the drawing parameters have been specified, the MPU issues a graphic drawing command and any required command parameters, such as the CRCL (Circle) command with a radius parameter. The ACR TC then performs the specified drawing operation by reading, modifying and rewriting the contents of the frame buffer. _HITACHI 29 H D63484-4.H D63484-6.HD63484-8 - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ Table 2 . ACRTC Command Table TYPE MNEMONIC ORG WPR RPR Register Access Command ~-. RPTN ORO OWT ~OO RO Data Transfer ~T Command MOD CLR SCLR CPY SCPY AMOVE RMOVE ALINE RLiNE ARCT RRCT APLL RPLL APLG RPLC CRCL Graphic Command ELPS AARC RARC AEARC ~~~ AFRCT RFRCT PAINT DOT PTN AGCPY RGCPY COMMAND NAME Origin Write Parameter Register Read Parameter Register Write Pattern RAM Read Pattern RAM " OMA Read OMAWrite OMAModify Read Write Modify Clear Selective Clear COpy Se lect ive Copy Absolute Move Relative Move Absolute Line Relative Line Absolute Rectangle Relative Rectangle Absolute Polyline Relative Polyline Absolute Polygon Relative Polygon Circle Ellipse Absolute Arc Relative Arc Absolute Ellipse Arc Relative Ellipse Arc Absolute Filled Rectangle Relative Filled Rectangle Paint Dot Pattern Absolute Graphic Copy Relative Graphic Copy 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 o 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 OPERATION CODE 1 ,0 0,0 0 0 0 '0 0 0 0'1 0,0 0,0 0 0, RN RN 0'1 1 ,0 0'0 0 0" 1,1 0,0 0'0 0 0 0, PRA 1.1 1 '0 0'0 0 0 0, PRA .0 1 i 0 0:0 0 0 ,0 000 0'0 0'0 0 0 0"0 000 tl 1 :0 0:0 0 0 ,0 O:MM '0 1 '0 0:0 0 0 ,0 000 ,0 000 0'1 0'0 0:0 0 0 011 1 :0 0,0 0 0 o ,0 O'MM 1 '1 0:0 0:0 0 0 o to 000 1 '1 1 '0 0·0 0 0 o ,0 O:MM ,0 000 o 'S: OSO .0 0 0 1 ,S' 050 ,0 0 0 o ,0 O:MM o ,0 0,00,00 o 0 ,0 000 to 1 '0 0,0 0 0 0,0 0 0 0 0,1 o '0 O· AREA;COL OPM 0 1 1 ,0 0' AREA:COL OPM 1 :0 0,0 0' AREA:COL OPM 1 :0 1 ,0 O' AREA;COL OPM 1 '1 o ,0 O· AREA:COL,OPM 1,1 1 '0 0' AREA:COL:OPM o ,0 o ,0 0' AREA:CoLioPM o ,0 1 '0 0: AREA'COLioPM 0'1 o 'O'C' AREA:COL:OPM 0 1 1 'O'C: AREA;COL:OPM 10 o 'O'C' AREA:COL:OPM 1 '0 1 ,O,C' AREA: COL; OPM 1'1 o 'O,C' AREA:COL:OPM 1,1 1 'o'c' AREA: COL: OPM o ,0 0'0 0' AREA;COL:OPM o 0 1 ,0 0' AR EA: COL! OPM 0;1 O~AREA:O 0:0 0 0 0'1 1 '0 0: AREA: COL: OPM 1 ISL: SO ~ AREA: COL: OPM , "AREA: 0'0: OPM o ,5 : 050 1 'S : OSO , AREA: 0 O,OPM o o OPH o o o o o o o o 0:'· o o 2 1 n+2 2 0 n n AX AX AX 0 0 0 0 SAH SAH X dX X dX X dX n n n n r a Xc dXc a a X. dX 01 ..... On 3 3 3 AY AY AY 15 87 Sly I . Ys dXs dYs '2) OX OX OY OY 0 SZx I SZy. SZx: Pattern Size n: number of repetition X/Y: drawing words of X-direction/Y -direction LlLo/d: sum of drawing dots AlB: drawing dots of mainlsub direction E: (E=O (Stop at Edge color), E=l (Stp at excepting Edge.color)] C: (C=l (clockwise). C=O (reverse)] ( I ]: rounding up P = 4: OPM-OOO-Oll 6: OPM-l00-111 '3) cycles: 2clock cycle time 30 ·_HITACHI 3 3 3 3 3 3 b dX Yc Xe Ye dYe dXe dYe Xc Yc Xe Ye b b dXc dYe dXe dYe Y dY SZ x. 1 2 2 4 4 5 5 AX AY AX AY SAL AX AY SAL AX AY Y dY Y dY Y dY Xl. Yl •.. Xn. Yn dX1. dYl •. dXn. dYn Xl, Y1, .. Xn. Yn dXl. dYl .... dXn. dYn '1) In case of rectangular filling '2) sZ:1 # (words) 3 PARAMETER OPL 2n+2 2n+2 2n+2 2n+2 2 4 5 5 7 7 3 3 1 1 2 5 5 - '3) (cycles) 8 6 6 4n+8 4n+l0 (4x+8)y+12[x'y/8tl +(62-68) (4x+8)y+16[x'y/8tl +34 (4x+8)y+16[x'y/8t] +34 12 8 8 (2x+8)y+12 (4x+6)v+12 (6x+l0)y+12 (6x+l0)y+12 56 56 P'L+18 P'L+18 2P(A+8)+54 2P(A+8)+54 :E[P'L+16]+8 :E[P'L+16]+8 :E[P' L+16] +P'Lo+20 :E[P'L+16]+P'Lo+20 8d+66 10d+90 8d+18 8d+18 10d+96 lOd+96 (P'A+8)8+18 (P'A+B)B+18 '1 ) (18A+102)B-58 8 (P'A+10)B+20 ((P+2)A+10)B+70 ((P+2)A+10)B+70 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H 063484-4, H 063484-6,H 063484-8 REGISTER ACCESS COMMAND RN PRA DPH DPL : : : : Register Pattern Drawing Drav.;ng number of the drawing parameter register($0-$13) RAM address at which Read Write operation starts($O·$F) pointer register High word pointer register Low word t---"--'.'--_."--.' . .. 15 14 13 12 11 10 9 8 7 6 5 4 3 ~~L?j.OE?lCl..L?_L_ DPH DPL -------- ---"-- -- 0 -----T--- ---- , DPAL ---- 2 DPAH DPD - DPAH : Higher 8 bits of Drawing POinter address DPAL Lower 12 bits of Drawing POinter address DPD : Dot position In the memory address DN Screen No. 00 Upper Screen 01 Base Screen 10 i Lower Screen 11 I Window Screen Dn : Write data : Number of Read ·'Wrlte data DATA TRANSFER COMMAND MM : Modify Mode i- MM '00 ! 01 10 Functior Replace OR AND Replace drav.;ng point data with modifier Information : OR dr aWing point data" with modifier data and rewrite the result data to the tr arne buffer AND drawing point data With modlfler data and rewrite the result data to the frame buffer ~O~ __ ~~2.~ ~r_~~~~~ p?ln_t_ data With modIfier data and rewrite the result data to the frame buffer S : Source Scan Direction I ml til fIT [·lE~ : : : ::" ffi [IB I I DSD . Destination Scan Direction DSD 000 0 CId DSD 001 DSD DIO m~ DSD DSD all 100 DSD 0 0 AX AY D SAH SAL : : : : : E5J IEJo 0 ]01 DSD lID DSD III mo oBl °BJ • . Redd Write pOInter start pOint Read Write pOinter end pOint Number of word In X·axis direction ~ 1 Number of word In Y-axis direction - 1 Write data Source Start Address High word Source Start Address Low word 15 14 13 12 11 10 9 8 7 6 5 4 3 2 SAH I-OEIOJOJoIo FfOT----(SAH) .... SA.L [ (SAL) -I0 1 0 I 0 I 0 10 I (SAH) : Memory address Higher 8 bits (SAL) : Memory address Lower 12 bits x : Number of word In X-axis direction : Number of word In Y-axis direction : Rounding. up $ HITACHI 31 H D63484-4,H D63484-6, HD63484-8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GRAPHIC DRAWING COMMAND AREA : Area Mode COL Color Mode OPM : Operation Mode E : Definition of Edge color_____~___c__c_------E Definition Edge color is defined by the data in the edge color register. '-'-:'---1--.:cE:c:dC'"gc:ce_color IS defined by the data excluding the above. Direction Counterclockwise Clockwise SL : Slant SD: Scan Direction ~ 0 1 000 OlD Oil 100 101 IlO III o~ ~ ~ ~ ~o ~ 001 8 '<2) '=Jl EJ 0 oL ff p) • : current potnter start point : current pointer end pOint S : Source Scan Direction DSD . Destination Scan DirectIOn DSD 000 DSD 001 DSD OlD )SC Oil DSD 100 lSI 1 DSD I DSD II 0 0 ill ill bid ITJ lEI IET oS I] 0 X, XI, Y, Yl, dX dY dXI, dYI, a, b DX DY Xc Yc dXc dYe Xe Ye dXe dYe Xs Ys dXs dYs P L, LO d A B 32 0 Xn : Absolute X· address from the origin point Yn : Absolute y. address from the origin point : Relative X· address fr am the current pointer : Relative y. address from the current pointer : Number of nodes dXn: Relative X·address from each node dYn: Relative Y·address from each node : Dot number on radius : (DX)': (DY)'=a : b : X·direction dot number : Y·direction dot number : Absolute X· address of the center point of arc /ellipse : Absolute Y'address of the center point of arc/ellipse : Relative X·address from the current pointer to the center point of arc/ellipse : Relative Y'address from the current pointer to the center point of arc/ellipse : Absolute X'address of the end point of arc/ellipse : Absolute Y·address of the end point of arc/ellipse : Relative X-address from the current pointer to the end point of arc/ellipse : Relative ,Y'address from the current pointer to the end point of arc/ellipse : Absolute X·address of the start dot position in source area : Absolute Y-address of the start dot position in source area : Relative X-address from the current pointer to the start dot position in source area : Relative V-address from the current pointer to the start dot pOsition in source area : 4(OPM=OOO-01l)/6(OPM= 100-111) : Dot number on straight line : total dot number : Scan main direction dot number : Scan sub direction dot number _HITACHI • . current pointer start point : :urrent pointer end point - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HD63484-4,HD63484-6,HD63484-8 • COMMAND FORMAT ACRTC commands consist of a 16 bit op-code, optionally followed by 1 or more 16 bit parameters. When 8 bit MPU mode is used, commands, parameters and data are sent to and from the ACRTC in the order of high byte, low byte. (a) 16 bit interface In the case of 16 bit interface, first move the 16 bit operation code and then mo\1e necessary 16 bit parameters one by one. bit 15 bit o Operation Code p1~1____________~ . Parameter Pn~I______________~ entry address and then writes commands/parameters to the write FIFO under program control (RS = high, R/W, CS = low). The MPU writes are normally synchronized with ACRTC FIFO status by software polling or interrupts. a Software Polling (WFR, WFE interrupts disabled) MPU program checks the SR (Status Register) for a) Write FIFO Ready (WFR) flag = 1, and the writes I-word op-code/parameters. b) MPU program checks the SR (Status Register) for Write FIFO Empty (WFE) flag = 1, and then writes I to 8-word op-code/parameters. a Interrupt Driven (WFR, WFE interrupts enabled) a) MPU WFR interrupt service routine writes I-word opcode/parameters. b) MPU WFE interrupt service routine writes I to 8-word op-code/parameters. In the specific case of Register A·ccess Commands and an initially empty write FIFO, MPU writes need not be synchronized to the write FIFO status. The ACRTC can fetch and execute these commands faster than the MPU can issue them. COMMAND DMA TRANSFER (b) 8 bit interface In the case of 8-bit interface, first move the operation code's high byte followed by low byte and then move those of parameters in the same order. bit o 1 } Operation ==============1 Code Commands and parameters can be transferred from MPU system memory using in external DMAC. The MPU initiates and terminates Command DMA Transfer mode under software control (CDM bit of CCR). Command DMA can also be terminated by assertion of the ACRTC DONE signal. DONE is treated as an input in Command DMA Transfer Mode. Using Command DMA Transfer, the ACRTC will issue cycle stealing DMA requests to the DMAC when the write FIFO is empty. The DMA data is automatically sent from system memory to the ACRTC write FIFO regardless of the contents of the Address Register. Note) • Make sure that the write FIFO is empty and all the commands are terminated before starting the Command DMA Transfer. • The Data DMA Command cannot be executed in the Command DMA Transfer Mode. • In the R mask and S mask version, the Command DMA Transfer is not in use. • REGISTER ACCESS COMMANDS Parameter Registers associated with the Drawing processor (Pattern RAM and Drawing Parameter Registers) are accessed through the read and write FIFOs using the Register Access Commands . • DATA TRANSFER COMMANDS PROGRAM TRANSFER Program Transfer occurs when the MPU specifies the FIFO Table 3 Data Transfer Commands are used to move blocks of data between the MPU system me'llory and the ACRTC frame buffer or within the frame buffer itself. Before issuing these commands, a physical 20 bit frame buffer address must be specified in the RWP (Read Write Pointer) Drawing Parameter Register. Register Access Commands Function Command ORG WPR Initialize the relation between the origin point in the X-Y coordinates and the physical address. Write into the parameter register RPR WPTN RPTN Read the parameter register Write into the pattern RAM Read the pattern RAM $ HITACHI 33 HD63484-4,HD63484-6,HD63484-8 Table 4 . Data Transfer Commands Command Function ORO Transfer data, by DMA transfer, from the frame buffer to the MPU system memory. DWT Transfer data, by DMA transfer, from the MPU system memory to the frame buffer. DMOD Transfer data, by DMA transfer, from the MPU system to the frame buffer subject to logical modification. (bit maskable) RD Read one word of data from the frame buffer specified by the read/write pointer (RWPI. and load the word into Read FIFO. WT Write one word of data to the frame buffer specified by the read/write pointer (RWPI. MOD Perform logical operation on one word in the frame buffer specified by the read/write pointer (RWPI. (bit maskable) - CLR Clear a rectangular area of the frame buffer with a data in the command parameter. SCLR Initialize a rectangular area of the frame buffer with 1-word data subject to logical operation. (bit maskable) CPY Copy frame buffer data from one area (source area) to another area (destination area) specified by the read/ write pointer (RWPI. SCpy Copy frame buffer data from one area (source area) to another area (destination area) subject to logical modification by word. The source and destination areas must reside on the same screen. (bit maskable) Operation Code Parameter 8 15 I 0 2 Command Code 10 o 0 0 0 olM M 15 0 I 15 0 I Figure 28 The DMOD, MOD, SCLR and SCPY commands allow 4 types of bit level logical operations to be applied to frame butTer data. The modify mode is encoded in the lower two bits (MM) of MM these op-codes. The bit positions within each frame butTer word to be modified are selectable using the mask register (MASK). Bits set to 1 are modifiable, ones to 0 are masked and not modifiable. Modify Mode ~ommand 0 REPLACE frame buffer data with 0 1 OR frame buffer data with command parameter data and rewirte to the frame buffer. 1 0 AND frame buffer data with command parameter data and rewrite to the frame buffer. 1 1 EOR frame buffer data with command parameter data and rewrite to the frame buffer. 0 GRAPHIC DRAWING COMMANDS The ACRTC has 23 separate graphic drawing commands. Graphic drawing is performed by modifying the contents of the frame butTer based upon microcoded drawing algorithms in the ACRTC drawing processor. Most coordinate parameters for graphic drawing commands are specified using logical pixel X-V addressing. The complex task of translating a logical pixel address to a linear frame butTer word address, and further selecting the appropriate sub-field of the word (for example, a given logical pixel in 4 bits per logical pixel mode might reside in bits 8-11 of a frame butTer word) is performed at high speed by ACRTC hardware. Many instructions allow specification of X-Y coordinates with either absolute or relative X-V coordinates (e.g. ALINE and RLINE). In both cases, twos complement numbers are used to represent positive and negative values. (a) Absolute Coordinate Specification The screen address (X, Y) is specified in units of logical pixels relative to an origin point defmed with the ORG command. 34 Parameter Data Transfer Command Format MODIFY MODE • I Parameter parameter data. (b) Relative Coordinate Specification The screen address (dX,dY) is specified in units of logical pixels relative to the current drawing pointer (CP) position. A graphic drawing command consists of a 16 bit op-code and optionally 0 to 64k 16 bit parameters. The 16 bit op-code consists of an 8 bit command code, an AREA· Mode specifier (3 bits), a Color Mode specifier (2 bits) and an Operation Mode specifier (3 bits). The Area Mode allows versatile clipping and hitting detection. A drawing area can be· defined, and should drawing operations attempt to enter or leave that area, a number of programmable actions can be taken by the ACRTC. The Color Mode determines whether the Pattern RAM is used indirectly to select Color Registers or is directly used as the color information. The Operation Mode defines one of eight logical operations to be performed between the frame butTer read data and the color data in the Pattern RAM to determine the drawing data to be rewritten into the frame butTer. ~HITACHI (i) Absolute Coordinate Specification Specifies the addresses (x, y) based on the origin point set by the ORG command. y (ij) Relative Coordinate Specification Specifies the relative addresses (L::.x, L::.y) related to the current drawing point. y y/} (x, y) y -- -------, , :I (x+6x, y+6y) CP (x, y) ------!~----~X---------x ------~----~----------x Origin I x Origin Figure 29 Absolute Coordinate Specification Tal;lle 5 Command Figure 30 Relative Coordinate Specification Graphic Drawing Commands Function x-v AMOVE Move the Current Pointer (CP) to an absolute logical pixel RMOVE Move the Current Pointer (CP) to a relative logical pixel X-Y address. ALINE Draw a straight line from the Current Pointer (CP) to a command specified end point of the absolute coordinates. RLiNE Draw a straight line from the Current Pointer (CP) to a command specified end point of the relative coordinates. ARCT Draw a rectangle defined by the Current Pointer (CP) and a command specified diagonal point of the absolute coordinates. RRCT Draw a rectangle defined by the Current Pointer (CP) and a command specified diagonal point of the relative coordinates. APll Draw a polyline (multiple contiguous segments) from the Current Pointer (CP) through command specified points of the absolute coordinates. RPll Draw a polyline (multiple contiguous segments) from the Current Pointer (CP) through command specified points of the relative coordinates. APlG Draw a polygon which connects the start pointer (CP) and command specified points of the absolute coordinates. RPlG Draw a polygon which connects the start pointer (CP) and command specified points of the relative coordinates. address. CRCl Draw a circle of the radius R placing the Current Pointer (CP) at the center. ElPS Draw a ellipse whose shape is specified by command parameters, placing the Current Pointer (CP) at the center. AARC Draw an arc by using the Current Pointer (CP) as a start point with an end point and a center point of the absolute coordinates. RARC Draw an arc by using the Current Pointer (CP) as a start point with an end point and a center point of the relative coordinates. AEARC Draw an ellipse arc by using the Current Pointer (CP) as a start point with an end point and a center point of the absolute coordinates. REARC Draw an ellipse arc by using the Current Pointer (CP) as a start pOint with an end point and a center point of the relative coordinates. AFRCT Paint a rectangular area specified by the Current Pointer (CP) and command parameters (absolute coordinates) according to a figure pattern stored in the Pattern RAM. (Tiling) RFRCT Paint a rectangular area specified by the Current Point (CP) and command parameters (relative coordinates) according to a figure pattern stored in the Pattern RAM. (Tiling) PAINT Paint a closed area surrounded by edge color using a figure pattern stored in the Pattern RAM. (Tiling) DOT Mark a dot on the coordinates where the Current Point (CP) indicates. PTN Draw a graphic pattern defined in the Pattern RAM onto a rectangular area specif.ied by the Current Pointer (CP) and by the pattern size. (rotation angle: 45°) AGCPY Copy a rectangular area specified by the absolute coordinates to the address specified by the Current Pointer (CP). (rotation angle: 90° /mirror turnover) RGCPY Copy a rectangular area specified by the relative coordinates to the address specified by the Current Pointer (CP). (rotation angle: 90° /mirror turnover) ~HITACHI 35 HD63484-4.HD63484-6.HD63484-8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - Operation Code 15 Parameter 8 7 5 4 3 2 0 Command Code IAREAI COL IOPM I o 15 r------P-a-ra-m-e-t-e-r-----' o 15 Parameter Figure 31 Graphic Drawing Command Format OPERATION MODE The Operation Mode (OPM bits) of the Graphic Drawing Command specify the logical drawing condition. Figure 32 shows examples of'a drawing pattern applied with various OPM mOdes. Operation Mode OPM 0 0 0 0 0 · · REPLACE: Replaces the frame buffer data with the color data. 1 OR: ORs the frame buffer data with the color data. The result is' rewritten to the frame buffer. 0 1 0 AND: ANDs the frame buffer data with the color data. The result is rewritten to the frame buffer. 0 1 1 EOR: EORs the frame buffer data with the color data. The result is rewritten to the frame buffer. 1 0 · · 0 CONDITIONAL REPLACE (Read Data=CCMP): When the frame buffer data at the drawing position is equal to the comparison color (CCMP). the frame buffer data is replaced with the color data. 1 0 1 · CONDITIONAL REPLACE (Read Data*CCMP): When the frame buffer data at the drawing position is not equal to the comparison color (CCMP). the frame buffer data is replaced with the color data. 1 1 0 CONDITIONAL REPLACE (Read Data < CLl: When the frame buffer data at the drawing position is less than the color register data (Cl). the frame buffer data is replaced with the color data . 1 1 1 CONDITIONAL REPLACE (Read Data> CLl: When the frame buffer data at the drawing position is greater than the color register data (CLl. the frame buffer data is replaced with the color data . · ..· ..· • Normally. the color register (ClO or Cll) selected by the pattern pointer (PPX. PPY) is used for the color data. but the source area data is used in the graphic copy commands (AGCPY and RGCPY). Normally. the color register (ClO or Cll) selected by the pattern pointer (PPX. PPY) is used for the color register data· (CLl. but the source area data is used in the graphic copy command (AGCPY and RGCPY). Figure 32 shows examples of a drawing pattern applied with various OPM modes. 36 ~HITACHI HD63484-4,HD63484-6,HD63484-8 ,--------------, 11 r7/l I I tzj I I I j I I I I I i / I i I _ _ _ _ _ _ _ _ _ _ _ _ _ _ -.JI I L Drawing Pattern Frame Buffer Image before Drawing ,---------------, r---------------, I I I I I f'Zl I I I I I I : 1: I:L:LI : [2l I I I I I I I I OR Replacement r-------------t r-----------------, I I I I I I I I I I I I I I . A. " :I I I I ~DZ~ I ~ : I I ______________ I L ~ AND EOR Figure 32 Operation Mode Example ~HITACHI 37 H 063484-4,H063484-6,H 063484-8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - COLOR MODE The Color Mode (COL bits) specify the source of the drawing COL color data as directly or indirectly (using the Color Registers) determined by the contents of the Pattern RAM. Color Mode 0 0 When Pattern RAM data = 0, Color Register 0 is used. When Pattern RAM data = 1, Color Register 1 is used. 0 1 When Pattern RAM data = 0, drawing is suppressed. When Pattern RAM data = 1, Color Register 1 is used. 1 0 When Pattern RAM data = 0, Color Register 0 is used. When Pattern RAM data'= 1, drawing is suppressed. 1 1 Pattern RAM contents are directly used as color data. The Color Mode chooses the source for color information based on the contents (0 or J) of a particular bit in the 16 bit by 16 bit (32 byte) Pattern RAM. A SUb-pattern is specified by programming the Pattern RAM Control Register (PRC) with the Pattern RAM start (PSX, PSY) and end (PEX, PEY) points which define the diagonal of the sub-pattern. Furthermore, a specific starting point for Pattern RAM scanning is specified by PPX and PPY. Normally, the color registers (CL) should be loaded with one color data based on the number of bits per pixel. For example, if 4 bits/pixel are used, the 4 bit color pattern (e.g. 0001) should be replicated four times in the color register, i.e. Color Register = 1 00011000 1 10 001 100011 In this way, color changes due to changing dot address are avoided. r -_ _ _.:..(P..;;;E~X, PEY) o (PPX, PPY) AREA MODE Prior to drawing, a drawing 'area' may be defined (Area Definition Register). Then, during Graphics Drawing operation the ACRTC will check if the drawing point is attempting to enter or exit the defined drawing area. Based on eight Area Modes, the ACRTC will take appropriate action for clipping or hitting. (PSX, PSY) AREA 38 0 0 0 0 Drawing Area Mode 0 Drawing is executed without Area checking. 0 1 When attempting to exit the Area. drawing is stopped after setting ABT (Abort Bit). 1 0 Drawing suppressed outside the Area - drawing operation continues and the ARD flag is not set. 0 1 1 Drawing suppressed outside the Area - drawing operation continues and the ARD flag is set at every drawing operation. 1 0 0 Same as AREA = 0 0 O. 1 0 1 When attempting to enter the Area, drawing is stopped after setting ABT (Abort Bit). 1 1 0 Drawing suppressed inside the Area - drawing operation continues and the ARD flag is not set. 1 1 1 Drawing suppressed inside the Area - drawing operation continues and the ARD flag is set at every drawing operation. ~HITACHI - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HD63484-4.HD63484-6.HD63484-8 • SYSTEM INTERFACE • BASIC CLOCK The ACRTC basic clock is 2CLK. 2CLK controls all primary ACRTC display and logic timing parameters. 2CLK, along with the specification of number of bits pe~ logical pixel, the Graphic Address Increment mode and the Display Access mode, also determines the video data rate. The basic clock must be -input, noting its cycle, max. and min. of "High" and "Low" level width. In any case,. be careful not to stop the basic clock fixing it at "High" or "Low" or not to use 2CLK line in open state, which can destroy the LSI. • CRT INTERFACE FRAME BUFFER ACCESS (I) Access Modes The three ACRTC display memory access modes are Single, Interleaved and Superimposed. (a) Single Access Mode A display (or drawing) cycle is defined as two cycles of 2CLK. During the first 2CLK cycle, the frame buffer display or drawing address is output. During the second 2CLK cycle, the frame buffer data is read (display cycles and/or drawing cycles) or written (drawing cycles). In this mode, display and drawing cycles contend for access to the frame buffer. The ACRTC allows the priority to be defined as display priority or drawing priority. If display priority, drawing cycles are only allowed to occur during horizontal/vertical flyback period. So, a 'flash less' display is obtained at the expense of slower drawing. If drawing priority, drawing may occur during display so high speed drawing is obtained, however the display may flash. (b) Interleaved Access Mode (Dual Access Mode 0) In this mode, display cycles and drawing cycles are interleaved. A display/drawing cycle is defined as four cycles of 2CLK. During the first 2CLK cycle, the frame buffer display address is output. During the second 2CLK cycle, the display data is read from the frame buffer. During the third 2CLK cycle, the frame buffer drawing address is output. During the fourth 2CLK cycle, the drawing data is read or written. Since there is no contention between display and drawing cycles, a 'flashless' display is obtained while maintaining full drawing speed. However, for a given configuration, frame buffer memory access time must be twice as fast as an equivalent Single Access Mode configuration. (c) Superimposed Access Mode (Dual Access Mode 1) In this mode, two separate logical screens are accessed during each display cycle. The display cycle is defined as four 2CLK cycles. During the first 2CLK cycle, the Background (Upper, Base or Lower) screen frame buffer address is output. During the second 2CLK cycle, the Background screen display data is read. During the third 2CLK cycle, the window screen frame buffer address or the drawing frame buffer address is output. During the 'fourth 2CLK cycle, the window screen display or drawing data is read (display or drawing) or written (drawing). Note that the third and fourth cycles can be used for drawing (similar to Interleaved mode) when these cycles are not used for Window display. $tflTACHI 39 SA (SINGLE ACCESS MODE) Display Cycle 2CLK A A MAD MA/RA/C~H~R-+ __________ ~A~ __________ ~ __________ A ~A~ A __________-A__________ ~A~ __________ ~ ____________ ___________A___ ~A MCYC "HIGH: MRD "HIGH: .." •:J: ~ () -:J: cO" I:: DISPLAY CYCLE---..., Cil w w Display Cycle (Zoom) » (") (") ~ '"'"s: 0 ~ MAD A MCYC ~ MRD ~ '----.J A " MA/RA/CH R a. 3" ---I A A A A I A J 'H IGH' 'H IGH' :i" co ZOOMING CYCLE x 2 Drawing Cycle ~ f-..--I MAD MA/RA/CH R MCYC A A A A A 0 A A r-I A I \ 0 '-- r--- MRD r--READ WRITE INTERLEAVED ACCESS MODE Display Cycle 2CLK A MAD MA/RA/C~H~R~ o A o A A +-__________ __________~A~__________~__________~A~________~~________~A~__________ ~A~ _________+-- MCYC .,., •:I ~ (') :I MRD cO" c: iil ....----~DRAW/READ w w » » (") (") ro '"'" s: t+--------~ DISPLAY CYCLE ro -I 3" DRAw/wRrrE------~ Display Cycle (Zoom) AS MAD ---, - ~ MCYC f-X A A A A ----, 0 A A MA/RA/C HR 0 0- ----t~ ----------1 0 A A I X I \ '-r-- MRD 5" co r-- I \ ZOOMING CYCLE x 2 Drawing Cycle ~ MAD MAiRA/C HR A A A A ~ ------..J X 0 A 0 A A A A MCYC MRD DRAW WRITE~--~-_ -" READ X "I J 0 .l.. .l SUPERIMPOSED ACCESS MODE Display Cycle 2CLK A A MAD MA/RA/C~H~R~ A A __________~A~__________~____________~A~________~L-__________~A~__________A-__________~A__________~~_ MCYC MRD 'HIGH" DRAW ..:t ~ () - :t BACK GROUND ---_*'"~----WINDOW----~ " _ - - - - - - - - - DISPLAY CYCLE ---------~ "T1 to' e: iil w w Display Cycle (Zoom) ---, III » (") (") MAD MCYC s: 0 MRD CD ~ ~ 'HI DRAW ~ A A A MA/RA/C HR CD C/I C/I Co - A A I Ir-I'-- A A ---, 1 A ~ J '-- .-- \ G"H-"' 3' ZOOMING CYCLE x 2 :S' co Drawing Cycle >-----I ----------... MAD ---( MA/RA/C HR I A A MRD 0 A 1 J MCYC '-----..i A A A A '-- X 0 A J I-- r-- \ DRAW READ WRITE c:::!:): CD: u::J: Split Screen Display Cycle Refresh Address Output Cycle lin DRAM mode) 2CLK -f.../\.F MCYC -L...J" ~: Drawing-Possible Window Display Cycle c:::Q:): Cycle c:e::::::): Attribute Out· is executed the put Cycle output will be f Ixed at ""0"") In this cycle the output will be fixed at "0" (when no drawing Vv ~ J\..F ~ ~ ~ ~ Lr ~ U -~ ~ ~ ~ HSYNC DISP~ DISP2 IWSS= 0) ..:z: ~ () :z: - [SA] ..., cC" c: ~ W W AS J MAD (])--€ ~ ~ O· X~ ""HIGH" MAIRA (j MRD » DRAW 0 ~~ ~ ....r-v rn-- tD---<:D--cD--m ~ CD---G)-- ~ S S 0 S Y s s W I W W X W 5 1.. s 0 X 0 X 0 "HIGH" C"l C"l (1) DISP2 IWSS=""' "') '"'s::" [DAO] c. AS 0 (1) -I 3" :;" co I I I .J J U ~ 3)---0}- CD--CD------CD- ®--CD----G}---- CD--ill- MAD I MRD DRAW J I O· XAl "HIGH" I MA/RA I 0 S I I I I I I I I I I I [DAl] . . . 1.1 J : I "HIGH" I I I DISP2 IWSS=""' "I AS I I MAD J I O· XAT I "HIGH" I DRAW DISF2 IWSS=""' s 0 w X w 0 X 0 s X 0 ~ 0 X o ~ "\ ~l i J I -m-$- CD----tfr-- CD---CD---CD--- ~ CD--ill- ~ I MRD 0 I I MA/RA s 0 I 0 5 T I [ s X oY sY 0 s "X w X I SX w ~ I I I 0 \. s X. 0 o X o I 0 H 063484-4, H 063484-6, H 063484-8 (2) Graphic Address Increment Mode (GAl) . During display operation, the ACRTC can be programmed to control the graphic display address in seven ways including increment by 1, 2, 4, 8 and 16* words, 1 word every two display cycles and no increment. Setting GAl to increment by 2, 4, 8 or 16* words per display cycle achieves linear increases in the video data rate i.e. for a given configuration setting GAl to 2, 4, 8 or 16* words will achieve 2, 4, 8 or 16* times the video data rate corresponding to GAI= 1. This allows increasing the number of bits/logical pixel and logical pixel resolution while meeting the 2CLK maximum frequency constraint. Table 6 Graphic Address Increment Modes Dot Rate 2 4 8 16 32MHz 16MHz Access Mode Color No. (bit/pixel) Memory Cycle 1 Table 6 shows the summary relationship between 2CLK, Display Access Mode, Graphic Address Increment, # bits/logical pixel, memory access time and video data rate. The frame buffer cycle frequency (Fc) is shown by the following equation where: Fv = Dot Clock # bits/logical pixel N D Display Access Mode 1 for Single Access Mode 2 for interleaved and Superimposed Access Modes A = Graphic Address Increment (112, 1, 2, 4, 8, 16*) Fc = (Fv x N x D)/(A x 16) S 0 S 64MHz 0 S 0 S 0 +1 +2 +2 +2 +4 +4 +4 +8 250ns - + 1/2 + 1/2 +1 500ns + 1/2 +1 +1 +2 250ns + 1/2 +1 +1 +2 +2 +4 +4 +8 500ns +1 +2 +2 +4 +4 +8 +8 + 16· + 16· 250ns +1 +2 +2 +4 +4 +8 +8 500ns +2 +4 +4 +8 +8 + 16· + 16· - 250ns +2 +4 +4 +8 + 16· + 16· 500ns +4 +8 +8 + 1.6· +8 + 16· 250ns +4 + 16· +8 +8 + 16· + 16· 500ns +8 + 16· - - - - - DYNAMIC RAM REFRESH When dynamic RAMs (DRAMs) are used for the frame buffer memory, the ACRTC can automatically provide DRAM refresh addressing. The ACRTC maintains an 8 bit DRAM refresh counter which is decremented on each frame buffer access. During. HSYNC low, the ACRTC will output the sequential refresh addresses on MAD. The refresh address assignment depends on Graphic Address Increment (GAl) mode as shown in Table 7. The ACRTC provides "0" output on the remaining address line of MAD and MA/RA. DRAM refresh cycle timing must be factored into the determination of HSYNC low pulse width (HSW - specified in units of frame buffer memory cycles). If the horizontal scan rate is Fh (kHz), number of DRAM refresh cycles is N and the DRAM refresh cycle time is Tr (msec) then horizontal sync width (HSW) is specified by the following equation: Table 7 - - GAl and DRAM Refresh Addressing Address Increment Mode Refresh Address Output Terminal +0 (GAI=101) MAO o-MA0 7 + 1 (GAI= 000) MAD o-MA0 7 +2 (GAI=OOl) MAO,-MAO a +4 (GAI-Ol0) MA0 2 -MAO g + 8 (GAI=Oll) MA0 3 -MAO,o + 16 (GAI= 100)· MA0 4 -MAO" + 1/2 (GAI= 111) 110 MAO o-MA0 7 HSW ~ N I (Tr x Fh) For example, if the scan rate is 15.75 kHz and the DRAMS have 128 refresh cycles of 2 msec, HSW must be greater than or equal to 5. HSW ~ 128 I (2 x 15.75) = 4.06 (Note) •... HD63484 (R-type) does not support 1 6 words increment mode. .4.4 128MHz _HITACHI -----------------------------HD63484-4,HD63484-6,HD63484-8 DiSP HSVNC AS MAD 0 o T8 A MA/RA A A RA 4 CHR DRAW "High" MRD "High" Figure 34 DRAM Refresh Timing EXTERNAL SYNCHRONIZATION The ACRTC EXSYNC pin allows synchronization of multiple ACRTCs or other video signal generators. The ACRTC may be programmed as a single Master device, or as one of a number of Slave devices. To synchronize multiple ACRTCs, simply connect all the EXSYNC pins together. For synchronizing to other video signals, the connection scheme depends on the raster scan mode. In Non-Interlace mode, EXSYNC corresponds to VSYNC. In Interlace modes, EXSYNC corresponds to VSYNC of the odd field. Clock Signal Note) 1. The ACRTC performs the synchronization everytime it accepts the pulse input from EXSYNC in the slave mode. It is recommended that 'the synchronous pulse should be input from EXSYNC only when the synchronization gap between the synchronous signal of the master device and that of ACRTC in the slave mode (HSYNC and VSYNC are output also in the slave mode,). 2. The ACRTC needs to be controlled not to execute the drawing operation during EXSYNC input. p.-. 2CLK ACRTC (slave) L. 2CLK EXSYNC ACRTC (Master) EXSYNC ...... 2CLK ACRTC (slave) EXSYNC Figure 35 External Synchronization • MPU INTERFACE MPU BUS CYCLE The ACRTC interfaces to the MPU as a peripheral occupying two addresses in the MPU address space. The ACRTC can operate as an 8 or 16 bit peripheral as configured during ~. An MPU bus cycle is initiated when CS is asserted (following the assertion of RS and R/W). The ACRTC responds to CS low by asserting DTACK low to complete the data transfer. DTACK will be returned to the MPU in between 1 and 1.5 2CLK cycles. MPU WAIT states will be added in the following two cases. (a) If the ACRTC 2CLK input is much slower than the MPU clock, continuous ACRTC accesses may be delayed due to internal processing of the previous bus cycle. Note) Be careful for CS "High" width. (b) If an ACRTC read cycle immediately follows an ACRTC write cycle, a WAIT state may occur due to ACRTC preparation for bus 'turn-around'. However, (68000 System: eg) MPUs normally have no instructions which immediately follow a write cycle with a read cycle. For connection to synchronous bus interface MPUs, DT ACK ~HITACHI 45 can simply be left open assuming the system design guarantees that WAIT states cannot occur as described above. If WAIT states may occur, DT ACK can be used with external logic to synthesize a READY signal. DMA TRANSFER The ACRTC can interface with an external DMA controller using three handshake signals, DMA Request (DREQ), DMA Acknowledge (DACK) and DMA Done (DONE). The ACRTC uses the external DMAC for two types of transfers, Command/Parameter DMA and Data DMA. For both types, DMA transfers use the ACRTC read and write FIFOs. (I) Command/Parameter DMA The MPU initiates this mode by setting bit 12 (CDM) in the ACRTC Command Control Register to I. Then, the ACRTC will automatically request DMA transfer for commands and their associated parameters as long the write FIFO has space. Only cycle steal request mode (DREQ pulses low for each data transfer) can be used. Command/Parameter DMA is terminated when the MPU resets bit 12 in CCR to 0 or the external DONE input is asserted. Note) The R mask version and the S mask version can't perform Command/Parameter DMA transfer. So CDM (bit 12) should be set to O. (2) Data DMA Data DMA is used to move data between the MPU system memory and the ACRTC frame buffer. The MPU sets-up the transfer by specifying the frame buffer transfer address (and other parameters of the transfer, such as 'on-the fly' logical operations) to the ACRTC. Next, when the M PU issues a Data Transfer Command to the ACRTC, the ACRTC will request DMA transfer to and from system memory. The ACRTC will request DMA, automatically monitoring FIFO status, until the DMA Transfer Command is completed. Data DMA request mode can be cycle steal (as in Command/ Parameter DMA) or burst mode in which DREQ is a low level control output to the DM AC which allows multiple data transiers during each acquisition of the MPU bus. f--------.----- INTERRUPTS The ACRTC recognizes eight separate conditions which can generate an interrupt including command error detection, command end, drawing edge detection, light pen strobe and four FIFO status conditions. Each condition has an associated mask bit for enabling/disabling the associated interrupt. The ACRTC removes the interrupt request when the MPU performs appropriate interrupt service by reading or writing to the ACRTC. • • DISPLAY FUNCTION LOGICAL DISPLAY SCREENS The ACRTC allows division of the frame buffer into four separate logical screens. Screen Number o Screen Name Screen Group Name Upper screen} Base Screen Background Screens Lower Screen Window Screen I 2 3 In the simplest case, only the Base screen parameters must be defined. Other screens may be selectively enabled, disabled and blanked under software control. The Background (Upper, Base and Lower) screens partition the display into three horizontal splits whose position is fully programmable. A typical application might use the Base screen for the bulk of user interaction, using the Lower screen for a 'status line(s)' and the Upper screen for 'pull-down menu(s)'. The Window screen is unique, since the ACRTC gives the Window screen higher priority than Background screens. thus, when the Window, whose size and position is fully programmable, overlaps a Background screen, the Window screen is displayed. One exception is the ACRTC Superimposed Access Mode, in which the Window has the same display priority as Background screens. In this case, the Window and Background screen are 'superimposed' on the display. The ACRTC logical screen organization can be programmed to best suit a number of display applications. Memory Width-----~------~ Start Address ~ Display Screen Area ~ Vertical Display Width ---------- 1 : Horizontal Display Width Figure 36 46 -I Display Screen/Frame Buffer Relationship ~HITACHI HD63484-4,HD63484-6,HD63484-8 0000 Defined Frame Buffer Frame Buffer for Character ~r-~------- ·1 MWO-------~ -- - ---- - - - - - - : . - - - - - - - - - - - - - - - - - - - . ; - 4 - - r - ---- --- ---- ----- -- --, SARO f----j.~_-_- -- -~ File Name: MOS - ____ -'---_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-1 --SAR2 FFFF L-_---l --+--- -- -- - - -- ----- -------: Left : Right : Layout : Symbol 1. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Frame Buffer for Graphic r----- MW1---'--j 00000 -~-------------, SAR1 I I , L ___________ ~ I I I __ J File Name: MOS f------1-~-'____________ .... _ _ _ _..........11 .-1'-,-''----v , ,, ,, ''-,- 1--- ------------------r---------- MW3~--"---l -f----'-- -- - - -- -SAR3 : , I I . _______________ L ________ _ FFFFFL.-_ _-'-" Left Right """",- ~S~cr_e~e_n_#_ _~P7o~s-it-io-n, 0 1 2 3 Upper Base Lower Window '" Layout : Symbol V L-_ _ _ _ _ _ _ _ _ ~ " '~_.l..-- Figure 37 ___-.J Display Screen Combination _HITACHI 47 H063484-4.H063484-6.H063484-8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - He '.. :I ,. HWS HSYNC-i HWW I I HSW .:,!"iDS:. I .1., , • I i I I I a I HOW ~ L,_ _ _- - - ' , I If) Cl > ~------~--------~~-------~------- f--------+------------ ------ --~-----_4-------- --- I----------_+_ - -- - -- - - -- ' - -_ _ _ _ _ _ _ _---1.. ______________________ _ 1--_ _ _ _ _ _ _ _ _ _ _ _---1- __________ _ I~ Figure 38 48 Display Screen Specification _HITACHI o a.-If) u > Memory Cycle 2CLK MCYC Horizontal Display Width ~IHDW+1)·M-----I r---------------------~-- Horizontal Display start 1-----HDS+1). M ." Horizontal Sync I: Width cO· •- HSW.M Cil W CD ----I Horizontal Window Width Horizontal Window Start ---- 1 - - - - - - 1 HWS+1)· M - - - - - <.....O----IHWW+11· M ~------------------------IHC+11·M Horizontal Cycle % -------------------- ~ () _ _- -% Vertical Split Screen Display Start VDS·H Vertical Sync Width 0 Vertical I Display Width --t..j ....4t--~SPO·H ---~------ I-----VWS· H Vertical Window Start .. 14 Vertical Window Width VSW'H VWW· H - - - - - - - - - - t.. ~1 I-~~~~~~~---------------VC·H----------------------~ Vertical Cycle ::r: o 0) w .j>. CD .j>. .J". ::r: o 0) w .j>. CD .j>. fr> ::r: o w 0) .j>. CD T- CD HD63484-4.HD63484-6.HD63484-8----------------------------- SPO-Upper EX. 1 SP1-Base SP3- SP3Window EX . 2 SP1-Base W'Ind ow SP2-Lower SPO-Upper SPO-Upper SP1-Base EX. 3 EX. 4 SP1-Base ISP3Window SP2-Lower SP3-Window Figure 40 SP2-Lower Example Screen Combinations GRAPHIC/CHARACTER ADDRESS SPACES The ACRTC controls two separate logical address spaces. The CHR pin allows external decoding if physically separate frame buffers are desired. Each of the four logical screens (Upper, Base, Lower and Window) is programmed as residing in the Graphics address space or the Character address space. ACRTC accesses to Graphics screens are treated as bit mapped using a 20 bit frame buffer address, with an address space of one megaword OM by 16 bit). ACRTC accesses to Character screens are treated as character generator mapped. In this case, a 64k word address space is used and 5 bits of raster address are output to an external character generator. Multiple logical screens defined as Character can be externally 1F 00 --f-0+----10'-+--- 01 -+04----+04---02 ----i0~0~04f0~0~0+-- 03 -+04----+04---04 -+04----+04---05 ---jO'-+------jO'-+--- decoded to use separate character generators or different addresses within a combined character generator. Also, each Character screen may be defined with separate line spacing, separate cursors, etc. • CURSOR CONTROL The ACRTC has two Block Cursor Registers and a Graphics Cursor Register. A Block cursor is used with Character screens. The cursor start and ending raster addresses are fully programmable. Also, the cursor width can be defined as one to eight memory cycles. A Graphics cursor is defined by specifying the start/end memory in cycle the X dimension and the start/end raster in the Y dimension. The Graphic cursor can output on character screens. - - - First Raster Address (FRA) HITACHI ~ Cursor1 -~0+----10~--06 ACRT~ --------~_-07 L -----------08 I - Last Raster Address (LRA) ~ Cursor2 Raster Address Figure 42 Figure 41 50 Character Screen Raster Addressing $ HITACHI Two Separate Block Cursors - - - - - - - - - - - - - - - - - - - - - - - - - - HD63484-4,HD63484-6,HD63484-8 ------1F 000000 000000 000000 000000 000000 000000 000000 BCSR=07 BCER=07 000000 000000 000000 02 ------03 ------04 ------05 ------06 ------07 ------08 BCSR=02 BCER=07 Figure 43 00 01 BCSR=OO BCER=02 Block Cursor Examples U.---------------)7 CUD, o Figure 44 Graphic Cursor _HITACHI 51 HD63484-4,HD63484-6,HD63484-8 ------------------~---------- The ACRTC provides two separate cursor outputs, CUD I and CUD2 • These are combined with two character cursor registers and a graphics cursor register to provide three cursor modes. The Graphic cursor is output on CUDI' Using an external cursor pattern memory allows a graphic cursor of various shapes. Two Block cursors are multiplexed on CUD 2 • Block Mode Crosshair Mode Two Block cursors are output on CUDland CUD2 respectively. The horizontal and vertical components of the Graphic cursor are output on CUD I and CUD2 respectively. This allows simple generation of a crosshair cursor control signal. Graphic Mode Horizontal Cursor Signal ______~n n~ ______ < CD a: n !!!. n c: iil J~I Q en ciS' ::l !!!. Figure 45 Crosshair Cursor • SCROLLING VERTICAL SCROLL Each logical screen performs independent vertical scroll. On Character Screens, vertical smooth scroll is accomplished using the programmable Start Raster Address (SRA). Line by line scroll is accomplished by increasing or decreasing the screen start address by one unit of horizontal memory width. On Graphics screens, vertical smooth scroll is accomplished by increasing or decreasing the screen start address by one unit of horizontal memory width. HORIZONTAL SCROLL 52 Horizontal scroll can be performed in units of characters for Character screens and units of words (multi logical pixels) for Graphic screens by increasing or decreasing the screen start address by l. For smooth horizontal scroll, the ACRTC has dot shift video attributes which can be used with an external circuit which conditions shift register load/clocking. Since this dot shift information is output each raster, horizontal smooth scroll is limited to either the Background screens or the Window screen at any given time. However, horizontal smooth scroll is independent for each of the Background screens (Upper, Base, Lower). _HITACHI HD63484-4,HD63484-6,HD63484-8 Defined Frame Buffer Start Address (SAR) SAR j SAR' - --r----------- --,I on Start Address (SAR') I I I I I I I MOS I I I I ____ .,. _________ ...JI "" Scrolling I r-:---- L --------, dD on . MOG MOS ______________ .J Figure 46 DISP Scrolling By SAR (Start Address Register) Rewrite ~L_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~r-- Memory Address Figure 47 Horizontal Smooth Scroll - _HITACHI Base Screen 53 H063484-4,H063484-6,H063484-8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Background DISP,~~______________________________~r_ DISP. --------------~ 1 Displav Cvcle §:)21· f MAD B m la,.fNlIBH,!W2f-- - -- -:IIt.!Wm~+d· E- --18,,; ·1 Background Address Emptv Cvcle or Drawing Cvcle Window Address W WSS=1 Figure 48 • Horizontal Smooth Scroll - Window Screen RASTER SCAN MODES The ACRTC has three software selectable raster scan modes - Non-Interlace, Interlace Sync and Interlace Sync & Video. In Non-Interlace mode a frame consists of one field. In the Interlace modes, a frame consists of two fields, the even and odd fields. The Interlace modes allow increasing screen resolution while avoiding limits imposed by the CRT display device, such as maximum horizontal scan frequency or maximum video dot rate. Interlace Sync mode simply repeats each raster address for both the even and odd fields. This is useful for increasing the quality of a displayed figure when using an interlaced CRT device such as a Television Set with RF modulator. Interlace Sync & Video mode displays alternate even and odd rasters on alternate even and odd fields. For a given number of rasters/character, this mode allows twice as many characters to be displayed in the vertical direction as Non-Interlace mode. Note that for Interlace modes, the refresh frequency for a given dot on the screen is one-half that of the Non-Interlace mode. Interlace modes normally require the use of a CRT with a more persistent phosphor to avoid a flickering display. Even--Odd ----- 1F 00 0 01 0 0 0 cx:xxx:x:x:xxJ 0 0 0 0 0 0 02 03 04 05 06 0 0 07 1F _______________ _ 1E 00 00 01 02 04 02 03~~~~~~ 04 -01 -03 ---------- -05 06---------------------------------07 08---------OB oc-r+-----~~ 06 - -00 OE~+_---~+_- ~--------------Interlace Sync. Non-Interlace Figure 49 54 -IF OA~+_---_r+_- 05 07 08 ------------------ Raster Scan Modes _HITACHI 10--------- ---------------11 Interlace Sync. & Video H 063484-4, H 063484-6, H 063484-8 [NON-INTERLACE] HSYNC~ ,... H---; RCR~ VSYNC EXSYNC (OUTPUT) .J .J~------------------------------'~--------~~------------------------------~'----------.... fool..o----------- FRAME ---------~.I [INTERLACE SYNC] Dummy RCR~ ~~;~~C (OUTPUT) j VC2 ~ VCl =t=t= Ir------------------------------~ t=-~----- EVEN FIELD ---l-~~~-=-=--~-=-F-:E [INTERLACE-SYNC & VIDEO] VC=OOD RCR ~ VSYNC .J --=-~~_=~_~O~D~-FIELD __- - _ -__ -------- H/2 Dummy -v----~TV~C~5-v~V~C~3~~V~C~1~~~~~--v-~5~~~~v-- ~ -------4:"'j ~ --I.- L -_ _ (!:~:~~) ,r~------------E-V-E-N-F-IE-L-D-------n--~_--1-----~-~-~-_----_-__ ..... --_-_-_--_~-_-_-_-_-------~-O-D:-_-FI-EL-D-_-_-----_--.__ - __ ~~ ~ FRAME - - - - - -- -----j H/2 Figure 50 Raster Scan Timing • ZOOMING The Base screen (Screen 1) is supported by the ACR TC zooming function. Note that ACRTC zooming is performed by controlling the CRT timing signals. The contents of the frame buffer area being zoomed are not changed. The ACRTC allows specification of a zoom factor (1 to 16) independently in the X and Y directions. For horizontal zoom, the programmed zoom factor is output as video attributes. An external circuit uses this factor to condition the external shift register clock to accomplish horizontal zooming. For vertical zoom, no external circuit is required. The ACRTC will scan a single raster multiple times to accomplish vertical zooming. 3xl ... Via I FfOfft 04 14 03 13 i · · 01 -1'-- 00 1...,r-....... csJ %8 05 35 ~OZ3Z '/I I'r/r------; .. 11 iI.. tIer MOTOROLA Semiconductor Products Inc. :5 ~• FIGURE 3 - LOGICAL PIN ASSIGNMENT Data Bus 00-07 ~ <'" ,... - ~ iRQ7 IR06 iRoS iRo4 A3 A2 iR63 - A1 'iR"C2 iRcli BIM INTO INT1 iNn iiCK iAcKiN INT3 IACKOUT iNm INTALO INTAL1 CL.K -5.0 (4) GND (4) INTERRUPT ACKNOW~GE SIGNALS - iACKiN, IACKOUT iACK. DEVICE INTERRUPT REQUEST SIGNALS - iNTO- iNf.i These three pins support the interrupt aclcnowledge cycle. A low level on the iACK input indicates an interrupt acknowledge cycle has been initiated. This signal is conditioned externally with Address Strobe and the lower data strobe of an MCSBOOO type bus. After iACK is asserted the 81M compares the interrupt level presented on address lines A 1, A2.. and A3 with the current levels generated intemally and determines if a match exists. Then; if input IACKIN is asserted (driven low), the 81M will either complete the interrupt acknowledge cycle if a match exists or assert output IACKOUT if no match exists. IACK)N and ""IA""C"'K""O~U""T= form part of a prioritized interrupt acknowledge daisy chain. The daisy chain prioritizes interrupters and guarantees that two or more devices requesting an interrupt on the same level will not respond to the same cycle. The reauesting device (or interrupter) must wait until iAcKiN is asserted and not pass the signal on (assert IACKOUT) if it is to complete the interrupt acknowledge cycle. BUS INTERRUPT REQUEST SIGNALS - iiiQi - i'iffi7 These open-collector outputs are low when asserted. indicating a bus interrupt is requested at the corresponding level. An open-collector buffer is normally reQuired for sufficient drive when interfacing to a system bus. A pullup resistor is required to maintain iRQi IRQ? high between interrupt requests. ® iNTO - 1NT:3 are active low inputs used to indicate to the 81M that a device wants a bus interrupt. INTERRUPT ACKNOWLEDGE ENABLE - INTAE During an interrupt aclcnowledge cycle, this output pin is asserted low to indicate that outputs INTALO and INTAL 1 are valid. These two outputs contain an encoded number (x) corresponding to the interrupt (lNTx) beir,'lg acicnowledgec1. This feature can be used to signal interrupting devices, which supply their own vector, when to respond to the interrupt acknowledge cycle with the vector and a DTACK signal. INTERRUPT INTAL1 ACKNOW~GE LEVEL - INTALO, These active high outputs contain an encoded number co,responding to the interrupt level being acknowledged. They are valid only w~en INTAE is asserted low. CLOCK- CL.K The ClK input is used to supply the clOCK for intemal operations of the MCSS'53. as, RESET iAcK Although a reset input is not supplied. an on-board reset is performed if CS and iAEi< are asserted simultaneously. . MOTOROL.A Semiconductor Products Inc. _ _ _ _ _--J FIGURE" - ~ J!/;; ., ~~~,,~ ,,~~~ Cf~ MCaa153 REGISTER MOCEl. ~ ~~ Cf("j" ~'" ~?' ,..-- A' IR04 {> A2 A3 IRQ3 IR02 RIW IRO' """'- a: > 0 iiffi7 , 'C OTACK* 1iDTm "'5.V~ A04- A23 AMC~MX 050* AS' IACK* MCsa'53 BIM iNTo Address Decode INT, INT2 ~, INn Control Decode INTAE INTALO INTAL' SYSCLK ® iAcKiN r---" Device B } Device C Device Interrupt ReQuests Device 0 cs lACK SYSRESET' IACKIN" IACKOUT" Device A I ~ To Sis ve device for extemal Imerru pt Ackknowl edge IACKOUT CLK MOTOROLA Semiconductor Products Inc. FfGURE a- .FfGURE 9 - A3-A1 READ CYCU WRrrE CYCU Address Valid 07-00 '------® MOTOROLA Semiconductor Products Inc. INTERRUPT REQUESTS . The MCSS153 accepts device interrupt requests on inputs INTO, iNTi, INT2, and iN"T3. Each input is regulated by Bit 4 (IRE) of the associated control register (CRO controls INTO, CR1 controls INT1, etcl. If IRE (Interrupt Enable) is set and a device input is asserted, an Interrupt Request open-collector output (lRQ1-IRQ7) is asserted. The asserted i'RQX output is selected by the value programmed in Bits 0, 1, and 2 of the control register (LO, L1, and L21. This 3-bit field determines the interrupt request level as set by software. ' Two or more interrupt sources can be programmed to the same request level. That IROX output will remain asserted until multiple interrupt acknowledge cycles respond to all requests. If the interrupt request level is set to zero, the interrupt is disabled because there is no corresponding IRQ output. INTERRUPT ACKNOWLEDGE The response of an Interrupt Handler to a bus interrupt request is an interrupt acknowledge cycle. The lACK cycle is initiated in the MCSS153 by receiving lACK low. RfW, A1. A2. A3 are latched, and the intElrrupt level on line A '-A3 is compared with any interrupt requests pending in the chip. Further activity can be one of four cases: 1. No further action required - This occurs if IACKIN is not asserted. Asserting iACR only starts the BIM activity. If the daisy chain signal never reaches the MCSS153 (lACKIN is not asserted), another Interrupter has responded to the lACK Cycle. The cycle will end, the chip iACK is negated, and no additional action is required. 2. F»ass on the interrupt acknowledge daisy chain For this case, IACKIN input is asserted by the preceding daisy chain Interrupter, and IACKDUT output is in tum asserted. The daisy chain signal is passed on when no interrupts are pending on a matching level or when any possible interrupts are disabled. The Interrupt Enable (IRE) bit of a control register can disable any interrupt requests, and in turn, any possible matcHes. 3. Respond internally - For this case. IACKIN is asserted and a match is found. The MCSS'53 completes the lACK cycle by supplying an interrupt vector from the proper vector register followed by a Di'ACK signal asserted. IACKOUT is not asserted because the interrupt acknowledge cycle is completed by this oevice. For the MCSS153 to respond in this mode of operation. the EXTERNAL/INTERNAL control register bit (XiIN) must be zero. For each source of interrupt reQuest, the associated control register determines the 81M response to an lACK cycle, and the x/IN '-------® bit sets this response either internally (X/IN - 0) or externally (X/iN - 1). 4. Respond externally - For the final case, IACKIN is also asserted, a match is found and the associated control register has x/iN bit set to one. The MCSS153 does not assert IACKDUT and does assert iN'fAE low. INTAE signals th.at the requesting device must complete the lACK cycle (supplying a vector and DTACK) and that the 2-bit code contained on outputs INTALO and INTAL 1 shows which interrupt source is being acknowledged. These cases are discussed in more detail in the following paragraphs. Intemal Interrupt Acknowledge For an internal interrupt acknowledge to occur, the following conditions must be met: 1. One or more device interrupt inputs (lNTo-iN"T3) has been asserted and corresponding control bit IRE value is one. 2. lACK asserted. 3. A match exists between [A3, A2. A 1) and the [L2, L1, LO) field of an enabled, requesting control register. If two or more devices are requesting at the same interrUpt level. preference is given to the highest number requester, that is, iN"F.3 has highest priority and INTO has lowest. 4. Control register bit x/IN of matching interrupt source must be zero. 5. IACKIN asserted. The internal interrupt acknowledge cycle timing is shown in Figure 10. The 8-bit interrupt acknowledge vector is presented to the data bus and DTACK i's a.sserted. Note also that INTALO and INTAL1 are valid and INTAE is asserted during this cycle although they would normally not be used. The cycle is terminated (data and DTACK released) after lACK is negated. During the lACK cycle, the INTE~RUPT AUTO-CLEAR control bit (IRAC) comes into play. If the IRAC - one for the responding interrupt source. the INTERRUPT ENABLE (IRE) bit is ,automatically cleared during the lACK cycle. thus disabling the associated interrupt input and any i'RQX output asserted due to this interrupt input. Before another interrupt can be recuested from this source. IRE must be set to one by writing to the control register. Note that IACKDUT is not asserted because this Oevice is responding to the lACK and does not pass the daisy chain signal on. Also, neW" device interrupt requests occurring on INTo-iNT3 after lACK is asserted are locked. out to prevent any race conditions on the daisy chain. MOTOROLA Semiconductor Products inc. FtGURI10 -INTERRUPT ACKNOWLEDGE CYCU -INT!RNAL veCTOR A3-A1 07-00 INTALO.INTALl External Interrupt Acknowledge For an external interrupt aclcnowledge. the same conditions as listed above are met with one exception. Contral register bit XliN of m~tching interrupt source must besetto one. The timing is shown in Figure ". For this cycle. the interruptveclor and OTACK must be supplied by an external device. iN'rAE is asserted indicating that INTALO and INTAL1 are valid. The external device can use these signals to enable the vector and l5i"ACK. The cycle is terminated after iACK is negated. The IRAC control bit acts in the external interrupt ac· knowledge the same as described for the internal response (see above). Also. IACKOUT is not asserted and new device interrupts are disabled for reasons discussed above. '-------® Pas On lAC( Daisy Chain If the MCsa153 has no interrupt request pending at the same level as the interrupt acxnowledge. the lACK daisy chain signal is passed on to the next device if !ACKIN is asserted. The following conditions are thus met: • 1. lACK asserted. 2. No match exists between (A3. A2. A 1J and the [L2. L1, LOI field of an enabled. requesting control reg· ister• . 3. iACi > I'~ Vour 1 TCOO2371 Figure 1. * An 80·nH inductor in series with the output results in a typical tA and tF of 2.5 ns with a 5% overshoot. DAC SPECIFICATIONS Parameter Symbol Voc Izs IMax. PSS IFS± IREF ClK tR tF ts Notes: over operating range unless otherwise specified Parameter Description Test Conditions Aesolution Linearity Differential Linearity Output Compliance Voltage Zero Scale Currant Output Maximum Current Full Scale Temp. CUrrent Coefficient Power Supply Sensitivity, Full Scale Positive Glitch Energy Output CapaCitance Reference Current Gray Scale (Note 7) Gray Scale (Note 9) Gray Scale (Note 9) Clock Frequency Aisetime: 10 to 90% Falltime: 90 to 10% Settling TIme (256 level of Gray) (Note 12) lC - GND, ECl Mode lC - Vee, TTL Mode (Notes 8 & 14) (Notes 8 & 14) % Gray Scale Bits (Notes 8, 10 & 11) Accuracy ±0.2 8 ±0.4 7 ±0.8 6 ±1.6 5 ±3.2 4 Min. Typ. Max. 8 8 8 ±.5 ±.5 ±1.4 1 !'A 22 50 0.25 V ±5% VEE = -5.2 V ±5% (Notes 11 & 13) (Note 11) VCC~5 50 10 200 83 3.5 3.5 45 30 8 6 4.5 mA ppml'C % Gray Scale pV-sec pF 1.66 D.C. D.C. Unite Ms lSB lSB Volts rnA MHz ns ns ns 7. Over full current range. 8. DAC settling, tA, tF measurements are taken using Figure 1. Output loading and frequency may require capacitor addition or inductor value changes to compensate for loading effects (see Figures 2 and 3). 9. Gray scale is defined as output levels between reference white and reference black. DAC Linearity and Differential Linearity are measured at';;; 10 MHz in production over operating temperature range at nominal supply voltages. Accuracy degrades with increasing frequency. DAC output terminated into 75-ohm load. IFS = 14.28 mA. 10. These numbers are measured using Tektronix sampling unit TYPE 3S2 and sampling sweep TYPE 3T77. 11. This typical value is provided for design reference and will not be tested in production. 12. Settling time is highly sensitive to PC board layout, decoupling and termination. 13. Am8151 produces a clock-related glitch on the video output pin occuring approximately 4 ns after both the rising and falling edges of the clock. The glitch is bipolar in shape and has a duration of approximately 5 ns. Typical amplitude is ±20 mV around the DAC output level. 7 Zero Scale Current: Zero Scale Current is the current produced at a Peak White output level. EXPLANATION OF DAC SPECIFICATIONS Resolution: Resolution refers to the number of discrete steps or levels which the DAC can provide, and is expressed as a number of bits. A DAC with n bits of resolution provides 2 n discrete analog levels. Note that having n bits of resolution does not guarantee n bits of accuracy. Output Maximum Current: Full Scale Current is the current produced at a Sync output level. The Full Scale Current is determined by the relation IFS = 13.27 IREF. Linearity: Linearity is the maximum deviation of an actual output from an ideal output defined by a straight line drawn through the end points of the transfer. function. A converter must be linear to within 1/2 a step to be accurate to its full resolution. In the Am8151, linearity is expressed as a fraction of the change in output caused by a change in the LSB. Full Scale Current Temperature Coefficient: The Full Scale Current Temperature Coefficient is the effect of temperature change, within the operating range, on the Full Scale Current. For the Am8151 this is given as the change in current per degree Centigrade. Power Supply Sensitivity: The effect of the power supply voltage change on 'a full scale DAC output. In the Am8151, PSS IFS ± is expressed as a percentage of the Gray Scale Range as reference black output varies while the voltage varies in the recommended operating range. This specification assumes the reference voltage is used. Differential Linearity: Differential Linearity is the measure of the uniformity of step size. If the differential linearity is specified as 1/2 an LSB, the step size from one step to the next may be from 1/2 to 3/2 of an ideal step. In the Am8151, linearity is expressed as a fraction of the change in output caused by a change in the LSB. Glitch Energy: Glitch Energy is an indication of the magnitude and duration of glitches. For the Am8151 this is specified in picovoltseconds. Output Compliance Voltage: The Output Compliance Voltage is that voltage swing which may be impressed on the output current pin. Output Capacitance: Output Capacitance is the internal capacitance of the VIDEO pin. Settling Time: Settling Time is the time from when the output first changes until the output arrives at, and remains within, a certain error band around the final value. In the Am8151 this is specified to be the time from a 10% change in the output value, to within a certain percent of the gray scale. Reference Current: Reference Current is the range of acceptable reference currents at the IREF pin. REFERENCE VOLTAGE OVER OPERATING RANGE Parameter Symbol VREF Parameter DeSCription Test Conditions Reference Voltage IREF = 1 to 5 rnA Line Regulation VCC=5 ±5% VEE =-5.2 ±5% Min. Typ. Max. 2.127 2.152 2.174 .23 .4 % VREF .4 % VREF ppml"C Load Regulation IREF = 1 to 5 rnA .1 Voltage Temp. Coefficient (Note 11) 25 Units Volts EXPLANATION OF REFERENCE VOLTAGE SPECIFICATIONS Reference Voltage: Reference Voltage is the output voltage provided by the reference voltage source. Load Regulation: Load Regulation is the effect of a change in the current sourced by the reference voltage on the reference voltage output. For the Am8151 this is specified as the percentage change in the reference voltage for changes in current as specified. Line Regulation: Line Regulation is the effect of a change in the supply voltage on the reference voltage output. For the Am8151 this is specified as the percentage change in the reference voltage for changes in supply voltage within the Operating Range. Reference Voltage Temperature Coefficient: Reference Voltage Temperature Coefficient is the effect of temperature change on the reference voltage. For the Am8151 this is given as the change in voltage per degree Centigrade. 6 ,----------------- -----------------------------------------------, AC SWITCHING CHARACTERISTICS No. Parameter Symbol over operating range Parameter Description Test Conditions 1 !eLK Clock Period (Note 14) 2 ts Address. OVERLAY. WIB Setup before Clock r HSYNC. VSYNC. BLANK Setup before Clock r Address. OVERLAY. W/Ii. HSYNC. VSYNC. BLANK Setup before Clock r (Note 14) 3 tH 4 tpo 5 tpo 6 ts 7 8 tH tpo 9 tpo 10 ts 11 ts 12 tH Min. Typ. Max. Units lC - GND. ECl Mode lC - Vee. TIL Mode lC-GND lC-GND lC-Vcc 5 12 ns ns 1.5 3.0 2.0 ns ns ns Address. OVERLAY. W/Ii Hold alter Clock r HSYNC. VSYNC. BLANK Hold alter Clock r Address. OVERLAY. W/Ii. HSYNC. VSYNC. BLANK alter Clock r (Note 14) lC-GND lC-GND LC-Vcc 2.0 2.0 2.0 ns ns ns Clock r to 10% VIDEO change (Notes 14 & 15) lC-GND LC-VCC 3.0 4.0 Clock r to Data Valid (Read) W/R Setup before ~ I (Note 14) WIR Hold alter EN r (Nota 14) ~ I to Data Active (Read) EN r to Data Three-State (Read) Address latched (Clock r) to ~ I Setup (Write) (Note 14) Data (and Address) Setup before EN r. Write Cycle Time (Write) (Note 14) Data Hold alter EN r (Note 14) 7.1l 11.0 ns ns 40 ns 20 ns 20 ns 40 ns 60 ns 10 ns 40 ns 10 ns Note: 14. Not all tests are being performed in manufacturing. Tests are guaranteed by Engineering characterization with periodic manufacturing sampling. 15. Clock t to 10% VIDEO change for any two Am8151s at the same temperature. voltage and load conditions typically does not differ by more than 0.5 ns for the Eel mode and 0.6 ns for the TTL mode. SWITCHING WAVEFORMS VIDEO REFRESH TIMING HSYNC, VSYNC~I ______ BLANK, OVERLAY)()Q N .XXXXXX N + 1 W/B VIDEO X X XX X XX X X X XX XXXXX XX X X X XXX X XXXXXXX X N N+l WF008882 9 SWITCHING WAVEFORMS (Cont.) READ TIMING CLK .1 \ \'--- Ao-Ar will I!IiI Do-Dr WF008892 WRITE TIMING - CLK r--+-----.-:i-.~ @ WFOO8901 10 r----------·--------------------------, TYPICAL CONNECTION DIAGRAM ·+5 V DIGITAL o------4.....- -......---fTTLVcc +5 V ANAVcc I - - - e - - - + - - - - o ANALOG I 0.1 p.F TTLGND ANAGND ECLGND ECLGND ANAVE£ I - - - e - - - . - - - - - - ( ) -5.2 V ANALOG I 0.1 p.F MONITOR VIDEO 1 - - - - - - - - - - 1 1 -.....COMP:! I - - - e - - - - , 75 D ,...----iECLVEE -&,2 V DlGITALo---.----.---~ECLV~ COMP1I-......._ - - - , IREF '* VREF 1 kD DIGITAL GROUND I l. ":" ANALOG GROUND O.1 p.F I 100 pF CDOO5692 TYPICAL APPLICATION ,. ---, I @} COLOR PLANES. ~ ... ~xac~K------~-----~ nMING GENERATOR 1-_ _ _ _ _.... AF003410 11 TYPICAL PROCESSOR CONNECTION » I ECl ''WIRE OR" VIDEO SHIFT REGISTERS VIDEO TIMING CONTROllER I ~~r:\~__~8~-'~~ADDR~ \.: :.; .. EN----, PROC~R - " - ADDR~ BUS r-- .---+--t"W/R TTL TO ECl I-TRANSLATORS ------a- PROC~R VIDEO i - - R ..----I---l~~ 8 DATABUS--~-----------------+--~· DATA ~ ADDR~ VIDEO - G r-+-+-+---I~ ~ ENABlE _____________________~ LINES ...,1-+---1" W/R ....t-... DATA '---- ADDR~ VIDEO i - - B '-t-+-..... ~ PROC~R _________--1 '<)-----------<....,f--~ WI" R1WUNE" " ~DATA AF003420 GENERATING 8 COLOR TEXT OVERLAY WITH W/S AND OVERLAY INPUTS G 8 Am8151 Am8151 R Am8052 Am8151 W/I \ W18 OVERLAY OVERLAY W/I OVERLAY J ' \ . "ATTRIBUTES" CHAR. GEN. 1 SHIFT• . REG. AF003720 SINGLE Am8151 TRUTH TABLE Overlay W/B 0 X Graphics 1 Peak White 0 Ref. Black 12 Output TRUTH TABLE FOR THREE Am8151s Wit Overlay (R) (0) (8) 0 X X X Graphics 1 0 0 0 Black 1 0 0 1 Blue 1 1 0 Green 1 0 0 1 1 Cyan 1 1 0 0 Red 1 1 0 1 Magenta 1 1 1 0 Yellciw 1 1 1 1 White KEY TO SWITCHING WAVEFORMS WAVEFORM ~ .- -- H INPUTS OUTPUTS MUST BE STEADY WILL BE MAY CHANGE FROMH TOL STEADY WILL BE CHANGING FROM M TOL MAY CHANGE FROM L TOH WILL BE CHANGING FROML TOH DON'T CARE; ANY CHANGE PERMITTED CHANGING; STATE UNKNOWN DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE "OFF" STATE KSOOOO10 13 Output TYPICAL PERFORMANCE CURVES 2 n$/dht Figure 2. Video Output Falling Edge Figure 3. Video Output Rising Edge 14 PHYSICAL DIMENSIONS CD 040 15 ADVANCED MICRO DEVICES DOMESTIC SALES OFFICES ALABAMA, ...... , ...................... ARIZONA, Tempe ...... , ... , ... ,................ Tucson, ............................. , CALIFORNIA, EI Segundo ...................... , .. . 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", .. ", ... ",."", .. 612 938-0001 NEW JERSEy ....... , .... "., .. " ..... , 201) 299-0002 NEW YORK, Liverpool, ........ ,., ... " .. ,." ... ," 315j457-5400 914 471-8180 Poughkeepsie (IBM only) " ..... ""'" Woodbury ." ....... , .. ,',.".,", ... . 516 364-8020 NORTH CAROLINA, (9191847-8471 (503 245-0080 OHIO, Columbus .. ", .. ", ... , .. " " , .. ,." , (614) 891-6455 PENNSYLVANIA, Allentown (AT&T only) ,., .. " " . " , .. ,. (2151 398-8006 Willow Grove ", .. ,', .. ,', ..... ,", ... (215 657-3101 TEXAS, Austin .".""" ., .. , .,"", ... , ... ,' (512 346-7830 Dallas .... , ........................ .. 214 934-9099 Houston .. , , .. , , ....... , , , , , , ........ . 713 785-9001 WASHINGTON ." .. ,",.,", ... ,.,"',. 206 455-3600 WiSCONSiN ... " ........ ,",.,.,., ... . 414 ,782-7748 f ! O~:~~~ ::::::::: :::::::::::::: :::: ::: 1 INTERNATIONAL SALES OFFICES BELGIUM, Bruxelles ................ TEL; FAX, TLX: CANADA, Ontario, Kanata ..... , ........... TEL: Willowdale " ..... " .. , .. TEL: FAX: FRANCE, Paris ................... TEL: FAX: TLX: GERMANY, Hannover area .,.".,.,. TEL: FAX: TLX: Manchen ................ TEL: FAX: TLX: Stuttgart ................ TEL: FAX: TLX: ........ (021 771 99 93 ........ (02 762-3716 ................ 61028 ., .. , ... (613) 592-0090 ...... ,. (4161 224-5193 ........ (416 224-0056 ...... (01) 46 87 36 66 ...... (01) 46 86 21 85 .. .. .. . .. . . ... 202053F ....... ,. (05143) 50 55 ......... (05143) 55 53 ............... 925287 ......... (089) 41 14-0 .. .. . .. ... (089) 406490 ..... :......... 523883 .. . .... (0711) 62 33 77 ....... (0711) 625187 ............... 721882 HONG KONG, Kowloon, ................ TEL: FAX: TLX: ITALY, Milano, .. , .... , ... ,. TEL: FAX: TLX: JAPAN, Tokyo ............. TEL: FAX: TLX: LATIN AMERICA, Ft. Lauderdale ........... TEL: FAX: TLX: SWEDEN, Stockholm .... ,. TEL: FAX: TLX: UNITED KINGDOM, Manchester area ... , .... , TEL: FAX: TLX: London area ........ , ... TEL: FAX: TLX: ............. 3-695377 .............. 1234276 ................ 50426 .......... (021 3390541 .. .. . .. ... (02 3498000 ............... 315286 ......... (03) 345-8241 .............. 3425196 , .... J24064AMDTKOJ ........ (3051 484-8600 ........ (305 485-9736 .. 5109554261 AMDFTL ........ (08) 733 03 50 ....... , (08) 733 22 85 ................ 11602 ........ (0925) 828008 .... ,'., (0925) 827693 ............... 628524 ........ (04862) 22121 ........ (04862) 22179 ........ , .. , ... 859103 NORTH AMERICAN REPRESENTATIVES CALIFORNIA 12 INC ... , .......... ,........... OEM DISTI IDAHO INTERMOUNTAIN TECH MKGT ....... . INDIANA SAl MARKETING CORP .............. , ' IOWA LORENZ SALES ..................... , MICHIGAN SAl MARKETING CORP .............. . NEBRASKA LORENZ SALES ..................... . (408) 988-3400 (408) 496-6868 (203) 272-2963 (208) 322-5022 (317) 241-9276 (319) 377-4666 (313)227-1786 NEW JERSEY TAl CORPORATION ....... , ......... " NEW MEXICO THORSON DESERT STATES ,."...... NEW YORK NYCOM, INC . . .. .. . .. .. . .. .. .. .. .. ... OHIO Dayton OOLFUSS ROOT & CO ., ..... " .. , ... Strongsville DOLFUSS ROOT & CO ............... PENNSYLVANIA DOLFUSS ROOT & CO .... , ... , ...... UTAH R2 MARKETING ...................... (609) 933-2600 (505) 293-8555 (315) 437-8343 (513) 433-6776 (216) 238-0300 (412) 221-4420 (801) 595-0631 Advanced Micro Devices reserves the right to make changes in its product without notice in order to improve deSign or performance characteristics. The performance characteristics listed in this document are guaranteed by specific tests, guard banding, design and other practices common to the industry. For specific testing details, contact your local AMD sales representative. The company assumes no responsibility for the use of any circuits described herein. JIll ADVANCED "'CRO DEVICES 901 Thompson PI., P.O. Box 3453, Sunnyvale, CA 94088, USA "'II1II TEL: (408) 732-2400 • TWX: 910-339·9280 • TELEX: 34·6306 • TOLL FREE: (800) 5388450 © 1986 Advanced Micro Devices, Inc. Printed in U.S.A. AIS·WCP·l0M·5/86·1 INITIALIZATION WITH MONI FORCE COMPUTERS Inc.!GmbH All Rights ReseNed This document shall not be duplicated, nor its contents used for any purpose, unless express permission has been granted. Copyright by FORCE Computers® The Initialization Program MONI: The SYS68K/AGC-l manual includes a floppy disk which can be read under PDOS, the Real Time Multi-tasking Operating System. After mounting of the floppy by typing in "SY0", the program can be executed by typing in: MONI The program displays the list of screen parameters and the default setting onto the terminal. In this menu the user can input the parameters which specify the horizontal and vertical resolution of the display screen Example: To display 1024 x 800 Pixel with 50Hz non-interlaced and bit/Pixel, the following sequence has to be typed in: FR Specifies the FIELD RATE 50 Stands for 50Hz RE Specifies the RASTER SCAN MODE 1 Stands for non-interlaced GM Specifies the GRAPHICS BIT MODE 4 Stands for 4 bit/Pixel XR Specifies the horizontal resolution 1024 Stands for 1024 Pixel YR Specifies the vertical resolution 800 Stands for 800 lines 4 The menu for the horizontal display parameters can be entered if HO is typed in. This menu allows to change the Horizontal SYNC width (HS), the Horizontal Back Porch (HB) and the Horizontal Front Porch (HF) in the same way as described above. The values of these parameters depends on the timing specification of the used monitor. To adapt the monitor to the AGC-l board set the correct timing values (normally included in the User's Manual of the monitor) has to be entered. 2 The menu also shows the required Horizontal SCAN FREQUENCY, the Horizontal LINE PERIOD, the BLANK TIME and the active DISPLAY PERIOD. The number of lines displayed in this menu include the lines required for the Vertical RETRACE PERIOD. The command VT selects the third menu which displays the calculated vertical display parameters. In this menu the Vertical SYNC WIDTH and the Vertical BACK PORCH can be changed because the values of these parameters also depend on the electrical specifications of the used monitor. The procedure is the same as described for the first menu. All SCREEN PARAMETER REGISTERS of the 63484 ACRCT are shown on the terminal after typing CR . These values are the values needed for the basic initialization of the SYS68K/AGC-I. Only the BASE SCREEN is initialized but the initialization of more screens does not change any of the SCREEN DISPLAY PARAMETERS which are important for the correct VIDEO timing needed by the used monitor. To see if the monitor produces a stable picture, just type GI and the SYS68K/AGC-l will be initialized by MONI with the parameters entered before. If everything performs well, a stable frame on the monitor is shown but if the frame is not stable on the monitor, the monitor has to be adapted (modification of the horizontal oscillator) and finely tuned to the trigger frame. If this procedure is not successful or the frame does not appear in the middle of the monitor the screen parameters programmed before have to be modified. This can be done by typing in the respective mnemonic (i.e. HS for the Horizontal SYNC WIDTH), entering the changed value and verifying the new adjustment by typing GI . This procedure can be performed as long as the frame does not appear in the right way. The MONI program can be left by typing in ESC and normal PDOS commands can be typed in. 3 SCREER PARAMETERS (HZ) : FIELD RATE RASTER SCAN MODE INTERLACED = 0 / NONINTERLACED = 1 GRAPHIC BIT MODE (BIT / PER PIXEL) : X - RESOLUTION (PIXEL) : Y - RESOLUTION (LINES) : * * 16000 750 2500 1250 20500 4500 48780 812 (NSEC) (NSEC) (NSEC) (NSEC) (NSEC) (NSEC) (HERTZ) RETRACE) VERTICAL MONITOR PARAMETERS MAXIMAL LINES (INCL. VERT. VERTICAL SYNCRON WIDTH VERTICAL BACK PORCH VERTICAL FRONT PORCH VERTICAL BLANK LINES ACTIVE DISPLAY LINES A CRT C HORIZONT SYNCRON HORIZONT DISPLAY VERTICAL SYNCRON VERTICAL DISPLAY SPLIT SCREEN WIDTH COMMAND CONTROL DISPLAY CONTROL OPERATION MODE * 1 4 1024 800 HORIZONTAL MONITOR PARAMETERS ACTIVE DISPLAY PERIOD HORIZONTAL SYNCRON WIDTH HORIZONTAL BACK PORCH HORIZONTAL FRONT PORCH HORIZONTAL LINE PERIOD HORIZONTAL BLANK TIME HORIZONTAL SCAN FREQUENCY MAXIMAL LINES (INCL. VERT. * 60 RETRACE) (LINES) (LINES) (LINES) (LINES) (LINES) 812 1 10 1 12 800 INITIALISATION PARAMETERS HSR HDR VSR VDR SP1 CCR DCR OMR R82 R84 R86 R88 R8A R02 R06 R04 HEX HEX HEX HEX HEX HEX HEX HEX * $00005103 $0000093F $0000032C $00000901 $00000320 $00000200 $0000C010 $0000C038 These values correspond to the monitor : BARCO CDCT 6551 4 FIELD RATE RASTER SCAN MODE INTERLACED = 0 / GRAPHIC BIT MODE X - RESOLUTION Y - RESOLUTION * (H Z) : NONINTERLACED = 1 (BIT / PER PIXEL) : (PIXEL) : (LINES) : * 17812 750 1250 1190 21000 3190 47614 952 (NSEC) (NSEC) (NSEC) (NSEC) (NSEC) (NSEC) (HERTZ) RETRACE) VERTICAL MONITOR PARAMETERS MAXIMAL LINES (INCL. VERT. VERTICAL SYNCRON WIDTH VERTICAL BACK PORCH VERTICAL FRONT PORCH VERTICAL BLANK LINES ACTIVE DISPLAY LINES * 1 4 1140 860 HORIZONTAL MONITOR PARAMETERS ACTIVE DISPLAY PERIOD HORIZONTAL SYNCRON WIDTH HORIZONTAL BACK PORCH HORIZONTAL FRONT PORCH HORIZONTAL LINE PERIOD HORIZONTAL BLANK TIME HORIZONTAL SCAN FREQUENCY MAXIMAL LINES (INCL. VERT. * 50 A CRT C HORIZONT SYNCRON HORIZONT DISPLAY VERTICAL SYNCRON VERTICAL DISPLAY SPLIT SCREEN WIDTH COMMAND CONTROL DISPLAY CONTROL OPERATION MODE RETRACE) (LINES) (LINES) (LINES) (LINES) (LINES) 952 2 54 36 92 860 INITIALISATION PARAMETERS HSR HDR VSR VDR SPl CCR DCR OMR R82 R84 R86 R88 R8A R02 R06 R04 HEX HEX HEX HEX HEX HEX HEX HEX * These values correspond to the monitor 5 * $00005303 $00000446 $000003B8 $00003502 $0000035C $00000200 $0000C010 $0000C038 BARCO CDCT 6551 FIELD RATE (HZ): RASTER SCAN MODE INTERLACED = B / NONINTERLACED = 1 GRAPHIC BIT MODE (BIT / PER PIXEL): X - RESOLUTION (PIXEL): Y - RESOLUTION (LINES): * * 2BBBB 5BB 2BBB 15BB 24BBB 4BBB 41666 1388 (NSEC) (NSEC) (NSEC) (NSEC) (NSEC) (NSEC) (HERTZ) RETRACE) VERTICAL MONITOR PARAMETERS MAXIMAL LINES (INCL. VERT. VERTICAL SYNCRON WIDTH VERTICAL BACK PORCH VERTICAL FRONT PORCH VERTICAL BLANK LINES ACTIVE DISPLAY LINES * B 4 128B 1B24 HORIZONTAL MONITOR PARAMETERS ACTIVE DISPLAY PERIOD HORIZONTAL SYNCRON WIDTH HORIZONTAL BACK PORCH HORIZONTAL FRONT PORCH HORIZONTAL LINE PERIOD HORIZONTAL BLANK TIME HORIZONTAL SCAN FREQUENCY MAXIMAL LINES (INCL. VERT. * 6B A CRT C RETRACE) (LINES) (LINES) (LINES) (LINES) (LINES) 1388 1 3 178 182 1B24 INITIALISATION PARAMETERS * ---------------------------------------------------- HORIZONT SYNCRON HORIZONT DISPLAY VERTICAL SYNCRON VERTICAL DISPLAY SPLIT SCREEN WIDTH COMMAND CONTROL DISPLAY CONTROL . OPERATION MODE * HSR HDR VSR VDR SP1 CCR OCR OMR R82 R84 R86 R88 R8A RB2 RB6 RB4 HEX HEX HEX HEX HEX HEX HEX HEX · · These values correspond to the monitor 6 $BBBB5FB2 $BBBBB74F $BBBBB56C $BBBBB2B1 $BBBBB4BB $BBBBB2BB $BBBBCB1B $BBBBCB3B . BARCO CDCT 6551 FIELD RATE RASTER SCAN MODE INTERLACED = 0 / GRAPHIC BIT MODE X - RESOLUTION Y - RESOLUTION * (HZ) : NONINTERLACED = 1 (BIT / PER PIXEL) : (PIXEL) : (LINES): 0 4 1600 1200 HORIZONTAL MONITOR PARAMETERS ACTIVE DISPLAY PERIOD HORIZONTAL SYNCRON WIDTH HORIZONTAL BACK PORCH HORIZONTAL FRONT PORCH HORIZONTAL LINE PERIOD HORIZONTAL BLANK TIME HORIZONTAL SCAN FREQUENCY MAXIMAL LINES (INCL. VERT. * 50 * (NSEC) (NSEC) (NSEC) (NSEC) (NSEC) (NSEC) (HERTZ) RETRACE) 25000 2250 2000 750 30000 5000 33333 1332 VERTICAL MONITOR PARAMETERS MAXIMAL LINES (INCL. VERT. VERTICAL SYNCRON WIDTH VERTICAL BACK PORCH VERTICAL FRONT PORCH VERTICAL BLANK LINES ACTIVE DISPLAY LINES RETRACE) (LINES) (LINES) (LINES) (LINES) (LINES) 1332 4 60 12 66 1200 A CRT C INITIALISATION PARAMETERS * * ---------------------------------------------------- HORIZONT SYNCRON HORIZONT DISPLAY VERTICAL SYNCRON VERTICAL DISPLAY SPLIT SCREEN WIDTH COMMAND CONTROL DISPLAY CONTROL OPERATION MODE * HSR HDR VSR VDR SP1 CCR DCR OMR R82 R84 R86 R88 R8A R02 R06 R04 HEX HEX HEX HEX HEX HEX HEX HEX These values correspond to the monitor 7 $00007709 $00000763 $00000534 $00003C04 $000004B0 $00000200 $0000C010 $0000C03B CONRAC 7211 FIELD RATE (HZ) : RASTER SCAN MODE INTERLACED = 0 / NONINTERLACED = 1 GRAPHIC BIT MODE (BIT / PER PIXEL) : X - RESOLUTION (PIXEL) : Y - RESOLUTION (LINES) : 60 1 8 720 560 ---------------------------------------------------HORIZONTAL MONITOR PARAMETERS * ----------------------------------------------------* ACTIVE DISPLAY PERIOD HORIZONTAL SYNCRON WIDTH HORIZONTAL BACK PORCH HORIZONTAL FRONT PORCH HORIZONTAL LINE PERIOD HORIZONTAL BLANK TIME HORIZONTAL SCAN FREQUENCY MAXIMAL LINES (INCL. VERT. * (NSEC) (NSEC) (NSEC) (NSEC) (NSEC) (NSEC) (HERTZ) RETRACE) 22500 2500 2000 1250 28250 5750 35398 589 VERTICAL MONITOR PARAMETERS MAXIMAL LINES (INCL. VERT. VERTICAL SYNCRON WIDTH VERTICAL BACK PORCH VERTICAL FRONT PORCH VERTICAL BLANK LINES ACTIVE DISPLAY LINES RETRACE) (LINES) (LINES) (LINES) (LINES) (LINES) 589 2 21 6 29 560 A CRT C INITIALISATION PARAMETERS * * ---------------------------------------------------- HORIZONT SYNCRON HORIZONT DISPLAY VERTICAL SYNCRON VERTICAL DISPLAY SPLIT SCREEN WIDTH COMMAND CONTROL DISPLAY CONTROL OPERATION MODE * HSR HDR VSR VDR SP1 CCR DCR OMR R82 R84 R86 R88 R8A R02 R06 R04 HEX HEX HEX HEX HEX HEX HEX HEX $0000700A $00000759 $0000024D $00001402 $00000230 $00000300 $0000C000 $0000C038 These values correspond to the monitor : CONRAC 7211 8 FIELD RATE RASTER SCAN MODE INTERLACED = 0 / GRAPHIC BIT MODE X - RESOLUTION Y - RESOLUTION (HZ) : NONINTERLACED = 1 (BIT / PER PIXEL) : (PIXEL) : (LINES) : .. 50 1 8 800 600 ---------------------------------------------------HORIZONTAL MONITOR PARAMETERS * * ACTIVE DISPLAY PERIOD HORIZONTAL SYNCRON WIDTH HORIZONTAL BACK PORCH HORIZONTAL FRONT PORCH HORIZONTAL LINE PERIOD HORIZONTAL BLANK TIME HORIZONTAL SCAN FREQUENCY MAXIMAL LINES (INCL. VERT. * (NSEC) (NSEC) (NSEC) (NSEC) (NSEC) (NSEC) (HERTZ) RETRACE) 25000 2750 2500 1750 32000 7000 31250 625 VERTICAL MONITOR PARAMETERS MAXIMAL LINES (INCL. VERT. VERTICAL SYNCRON WIDTH VERTICAL BACK PORCH VERTICAL FRONT PORCH VERTICAL BLANK LINES ACTIVE DISPLAY LINES RETRACE) (LINES) (LINES) (LINES) (LINES) (LINES) 625 2 17 6 25 600 A CRT C INITIALISATION PARAMETERS * ---------------------------------------------------- * HORIZONT SYNCRON HORIZONT DISPLAY VERTICAL SYNCRON VERTICAL DISPLAY SPLIT SCREEN WIDTH COMMAND CONTROL DISPLAY CONTROL OPERATION MODE * HSR HDR VSR VDR SPI CCR DCR OMR R82 R84 R86 R88 R8A R02 R06 R04 HEX HEX HEX HEX HEX HEX HEX HEX These values correspond to the monitor 9 $00007F0B $00000963 $00000271 $00001002 $00000258 $00000300 $0000C000 $0000C038 CONRAC 7211 FIELD RATE (HZ): RASTER SCAN MODE INTERLACED = 8 / NONINTERLACED = 1 GRAPHIC BIT MODE (BIT / PER PIXEL): X - RESOLUTION (PIXEL): Y - RESOLUTION (LINES): * A CRT C HORIZONT SYNCRON HORIZONT DISPLAY VERTIGAL SYNCRON VERTICAL DISPLAY SPLIT SCREEN WIDTH COMMAND CONTROL DISPLAY CONTROL OPERATION MODE * * 32000 2000 2800 1000 37008 5000 27027 900 (NSEC) (NSEC) (NSEC) (NSEC) (NSEC) (NSEC) (HERTZ) RETRACE) VERTICAL MONITOR PARAMETERS MAXIMAL LINES (INCL. VERT. VERTICAL SYNCRON WIDTH VERTICAL BACK PORCH VERTICAL FRONT PORCH VERTICAL BLANK LINES ACTIVE DISPLAY LINES * 0 8 1024 800 HORIZONTAL MONITOR PARAMETERS ACTIVE DISPLAY PERIOD HORIZONTAL SYNCRON WIDTH HORIZONTAL BACK PORCH HORIZONTAL FRONT PORCH HORIZONTAL LINE PERIOD HORIZONTAL BLANK TIME HORIZONTAL SCAN FREQUENCY MAXIMAL LINES (INCL. VERT. * 60 RETRACE) (LINES) (LINES) (LINES) (LINES) (LINES) 900 2 33 15 58 880 INITIALISATION PARAMETERS HSR HDR VSR VDR SP1 CCR DCR OMR R82 R84 R86 R88 R8A R02 R06 R04 HEX HEX HEX HEX HEX HEX HEX HEX * $00009308 $0000077F $00000384 $00082082 $00000320 $00000300 $0000C000 $0008C03B These values correspond to the monitor : CONRAC 7211 10 FIELD RATE (HZ): RASTER SCAN MODE INTERLACED = ~ / NONINTERLACED = 1 GRAPHIC BIT MODE (BIT / PER PIXEL): X - RESOLUTION (PIXEL): Y - RESOLUTION (LINES): * ~ 8 116~ 87~ HORIZONTAL MONITOR PARAMETERS ACTIVE DISPLAY PERIOD HORIZONTAL SYNCRON WIDTH HORIZONTAL BACK PORCH HORIZONTAL FRONT PORCH HORIZONTAL LINE PERIOD HORIZONTAL BLANK TIME HORIZONTAL SCAN FREQUENCY MAXIMAL LINES (INCL. VERT. * 5~ * (NSEC) (NSEC) (NSEC) (NSEC) (NSEC) (NSEC) (HERTZ) RETRACE) 3625~ 2~~~ 2~~~ 125~ 415~~ 525~ 24~96 962 VERTICAL MONITOR PARAMETERS MAXIMAL LINES (INCL. VERT. VERTICAL SYNCRON WIDTH VERTICAL BACK PORCH VERTICAL FRONT PORCH VERTICAL BLANK LINES ACTIVE DISPLAY LINES RETRACE) (LINES) (LINES) (LINES) (LINES) (LINES) 962 2 43 1 46 87~ INITIALISATION PARAMETERS A CRT C * *---------------------------------------------------- HORIZONT SYNCRON HORIZONT DISPLAY VERTICAL SYNCRON VERTICAL DISPLAY SPLIT SCREEN WIDTH COMMAND CONTROL DISPLAY CONTROL OPERATION MODE * HfSR HDR VSR VDR SPI CCR DCR OMR R82 R84 R86 R88 R8A HEX HEX HEX HEX HEX HEX HEX HEX R~2 R~6 R~4 These values correspond to the monitor 11 $~~~~A5~8 $~~~~~79~ $~~~~~3C2 $~~~~2A~2 $~~~~~366 $~~~~~3~~ $~~~~C~~~ $~~~~C~38 CONRAC 7211 PROGRAMMING EXAMPLES FORCE COMPUTERS Inc./GmbH All Rights Reserved This document shall not be duplicated, nor Its contents used for any purpose, unless express permission has been granted. Copyright by FORCE Computers@ ****************************************************** ************ * * * * * * * The information in without notice and by FORCE Computers. * * this document is subject to change * should not be construed as a commitment * * * Neither FORCE Computers nor the authors assume any responsi- * * bility for the use or reliability of this document or the * * described software. * * * Copyright (C) 1986. FORCE Computers * * * * * * * * General permission to copy or modify. but not for profit. is hereby granted, provided that the above copyright notice is included and reference made to the fact that reproduction privileges were granted by FORCE Computers. * * * * * * * * ****************************************************************** * * * SYS68K/AGC-·1 * THIS PROGRAM INCLUDES A COMPLETE SERIES OF SUBROUTINES TO GIVE A BASIS FOR USER APPLICATIONS. * PROGRAMMING EXAMPLES ==================================== THE ROUTINES AT THE BEGINNING DEMONSTRATE HOW TO USE THESE SUBROUTINES. "* * THE DEFAULT BOARD BASE ADDRESS IS SUGGESTED TO BE $BOOOOO IN THE STANDARD MEMORY AREA OF THE VMEBUS. * * THE FOLLOW SUBROUTINES MUST BE CALLED BEFORE DRAWING OPERATIONS CAN BE STARTED BSR BSR BSR * FOR LOGICAL DRAWING OPERATIONS THE ORIGIN MUST BE SET FIRST THIS ROUTINE LOCATES THE ORIGIN IN THE LOWER LEFT EDGE OF THE VISIBLE SCREEN MOVE.W MOVE.W #l.DO #O,Dl MOVE. W 10 2 1J I D;:. bS], OPOINT }<::k SA \jOh~G COLOR MOVE. v.! #3 I)1 SCOLO MOVE.W #1.D1 SCOLI I BSF, * ;CALCULATE REGISTER ACCESS ADDRESSES ;INIT AGC-1 ;LOAD COLOR TABLES BINIT INIT COLTAB ;PUT SCREEN NUMBER ;PUT X - COORDINATE ;PUT Y - COORDINATE ;SET ORIGlN POINT ;SAVE ORIGIN ADDRESS REGlSTEf ;(SSWO) ;(SSW2) DC.W DC.W DC.W $OOCA,$0280 $00CC,$0003 $OOCE,$0020 ;(MWR1) BASE ;(SAIH) BASE ;(SAIL) BASE SCREEN MEMORY WIDTH SCREEN START ADDRESS SCREEN START ADDRESS + + + DC.W $OOEA,$OOOO ;(ZFR) ZOOM FAKTOR REGISTER + DC.W DC.W DC.W DC.W $0002,$0200 $0006,$COIO $0004,$C03B $FFFF ;(CCR) ; (DCR) ; (OMR) COMMAND CONTROL REGISTER DISPLAY CONTROL REGISTER OPERATION MODE REGISTER +) THESE REGISTER MUST BE SET FOR BASIC INITIALISATION OF THE SYS68K/AGC-1 * HORIZONTAL SYNCRON HORIZONTAL DISPLAY SYNCRON VERTIKAL VERTIKAL DISPLAY UPPER SCREEN WIDTH BASE SCREEN WIDTH LOWER SCREEN WIDTH REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER + + + + + * * * * * * * + + + ************************************************************************** * AGC-I:SR ************************************************************************** ************************************************************************** * * * * * * SYS68K/AGC-I DRIVER MODULE MAl 1986 * ************************************************************************** ************************************************************************** * * SYS68K/AGC-1 BOARD BASE ADDRESS BBADR DC.L * * * OFFSET TABLE FOR FOR BASE ADDRESS CALCULATION INDEXT DC.L DC.L De.L DC.L DC.L DC.L * MAIN ROUTINE =============================== $BOOOOO =============================== $3COOO $3C002 $36000 $38000 $3AOOO $00000 * ============ BINIT LEA LEA MOVE.W MOVE.L BSR.S ADDQ.L DBRA RTS BINIl * * * ;BOARD BASE ADDRESS BBADR(PC),AO INDEXT(PC),A2 #5,D1 (A2) ,DO BASINIT #4,A2 DI,BINII ;ACRTC ;ACRTC ;COLOR ;COLOR ;COLOR iBIM ADDRESSREGISTER DATENREGISTER TABLE RED TABLE GRUEN TABLE BLUE START ADDRESS ;GET BOARD BASE ADDRESS iGET OFFSET TABLE ADDRESS iNUMBER OF OFFSETS ;PUT OFFSET IN DO iCALCULATE ;POINT TO NEXT OFFSET iALL ? INITIALISATION TO THE BASE ADDRESS AND REPLACE THEM TO THE OFFSET TABLE ==================================== BASINIT MOVEA.L (AO),Al ADDA.L DO,AI MOVE.L AI, (A2) RTS ;ADD OFFSET TO THE BOARD BASE ADDRES ;REPLACE TO OFFSET TABLE ************************************************************************** * DEFINITION CONTROLLER REGISTER FIFO CCH OMR DCR EOU EOU EOU EOU ************************************************************************** $0000 $0002 $0004 $0006 iFIFO ;COMMAND CONTROL REGISTER ;OPERATION MODE REGISTER ;DISPLAY CONTROL REGISTER RCR HSR HDR VSR VDR SSW1 SSW2 SSW3 BCR HWR VWRS VWRW EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU * RARO MWRO SARHO SARLO UPPER SCREEN EQU $OOCO EQU $00C2 EQU $00C4 EQU $00C6 :RASTER ADDRESS UPPER SCREEN If :MEMORY WIDTH ;START ADDRESS HIGH WORD ;START ADDRESS LOW WORD * RAR1 MWRI SARHI SARLI BASE EQU EQU EQU EQU SCREEN :RASTER ADDRESS BASE If ;MEMORY WIDTH :START ADDRESS HIGH WORD :START ADDRESS LOW WORD * RAR2 MWR2 SARH2 SARL2 LOWER SCREEN EQU $OODO EQU $00D2 EQU $00D4 EQU $00D6 ;RASTER ADDRESS :MEMORY WIDTH ;START ADDRESS ;START ADDRESS * RAR3 MWR3 SARH3 SARL3 WINDOW SCREEN EQU $00D8 EQU $OODA EQU $OODC EQU $OODE ;RASTER ADDRESS WINDOW SCREEN or ;MEMORY WIDTH :START ADDRESS HIGH WORD :START ADDRESS LOW WORD * ZFR ZOOM FACTOR EQU $OOEA PAGE $0080 $0082 $0084 $0086 $0088 $008A $008C $008E $0090 $0092 $0094 $0096 SCREEN $00C8 $OOCA $OOCC $OOCE ;RASTER COUNT REGISTER ;HORZONTAL SYNC. ;HORIZONTAL DISPLAY ;VERTICAL SYNC. ;VERTICAL DISPLAY REGISTER ;SPLIT SCREEN WIDTH SPI ;SPLIT SCREEN WIDTH SP2 ;SPLIT SCREEN WIDTH SP3 ;BLINK CONTROL REGISTER ;HORIZONTAL WINDOW DISPLAY ;VERTICAL WINDOW DISPLAY START WIDTH LOWER SCREEN " HIGH WORD LOW WORD ;ZOOM FACTOR ****~*********************************************************************** CONTROLLER FUNKTIONS CODES * * **************************************************************************** *NAME CODE ;COMMENT * *--------------------------------------------------------------------------* * * * * REGISTER ACCESS COMMANDS * * ORIG WPR RPR WPTN RPTN EQU EQU EQU EQU EQU $0400 $0800 $OCOO $1800 $lCOO ;ORIGN :WRITE :READ :WRJTE ;READ POINT AND CHOOSE SCREEN PARAMETER REGISTER PARAMETER REGISTER PATTERN RAM PATTERN RAM ****************************************************************************** * * DATA TRANSFER COMMANDS * * DRD DWT DMOD RD WT MOD EQU EQU EQU EQU EQU EQU $2400 $2800 $2COO J;:4400 $4800 $4COO READ :DMA ;DMA WRITE MODIFY :DMA ;READ (ONE WORD FROM THE FRAME BUFFER) :WRITE(ONE WORD TO THE FRAME BUFFER) ;MODIFY CLR SCLR CPY SCPY EQU EQU EQU EQU $5800 $5COO $6000 $7000 ;CLEAR (INITIALIZE FRAME BUFFER AERA) ;SELECTIVE CLEAR ;COPY ;SELECTIVE COPY ***************************************************************************** * AMOVE RMOVE ALINE RLINE ARCT RRCT APLL RPLL APLG RPLG CRCL1 CRCLO ELPS1 ELPSO AARC1 AARCO RARC1 RARCO AEARC1 AEARCO REARC1 REARCO AFRCT RFRCT PAINTO PAINT1 DOT PTN AGCPY RGCPY * GRAPHIC DRAWING COMMANDS EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU PAGE $8000 $8400 $8800 $8COO $9000 $9400 $9800 $9COO $AOOO $A400 $A900 $A800 $ADOO $ACOO $B100 $BOOO $B500 $B400 $B900 $B800 $BDOO $BCOO $COOO $C400 $C800 $C900 $CCOO $DOOO $EOOO $FOOO * ;ABSOLUTE MOVE ;RELATIVE MOVE ;ABSOLUTE LINE ;RELATIVE LINE ;ABSOLUTE RECTANGLE iRELATIVE RECTANGLE iABSOLUTE POLYLINE iRELATIVE POLYLINE iABSOLUTE POLYGON ;RELATIVE POLYGON iCIRCLE CLOCKWISE iCIRCLE COUNTER CLOCKWISE iELLIPSE CLOCKWISE iELLIPSE COUNTER CLOCKWISE ;ABSOLUTE ARC CLOCKWISE ;ABSOLUTE ARC COUNTER CLOCKWISE iRELATIVE ARC CLOCKWISE iRELATIVE ARC COUNTER CLOCKWISE iABSOLUTE ELLIPSE ARC CLOCKWISE iABSOLUTE ELLIPSE ARC COUN CLOCKWISE iRELATIVE ELLIPSE ARC CLOCKWISE iRELATIVE ELLIPSE ARC COUN CLOCKWISE ;ABSOLUTE FILLED RECTANGLE ;RELATIVE FILLED RECTANGLE iPAINTO ---> E = 0 iPAINT1 ---> E = 1 ;DRAW DOT iPATTERN ;ABSOLUTE GRAPHIC COPY iRELATIVE GRAPHIC COPY ****************************************************************************** DEFINITION DRAWING PARAMETER REGISTER * * ****************************************************************************** COREGO EQU $0800 iCOLOR REGISTER 0 COREG1 EQU $0801 iCOLOR REGISTER 1 CCOREG EQU $0802 ;COLOR COMPARSION REGISTER ECOREG EQU $0803 ;EDGE COLOR REGISTER RMASK EQU $0804 ;MASK REGHISTER * PRCOS PRC06 PRC07 PATTERN EQU EQU EQU RAM CONTROL REGISTER $0805 $0806 $0807 ;PATTERN POINT REGISTER iPATTERN START POINT REGISTER ;PATTERN END POINT REGISTER DRXMIN DRYMIN DRXMAX DRYMAX * AERA EQU EQU EQU EQU DEFINITION $0808 $0809 $080A $080B iXMIN ;YMIN ;XMAX iYMAX * DRWPH DRWPL READ WRITE POINTER REGISTER EQU $080C EQU $080D * DRAWING POINTER REGISTER REGISTER ;READ WRITE POINTER HIGH WORD ;" LOW WORD PDPH PDPL EOU EOU * CURRENT POINTER REGISTER EOU $0812 EOU $0813 PAGE PCPH PCPL $0810 $0811 ;DRAWING POINTER HIGH WORD LOW WORD ;CURRENT POINTER HIGH WORD LOW WORD . ," ,• n ************************************************************************** * DEFINITION DER CONTROLLER COLOR TABELLEN COLTR COLTG COLTB EOU EOU EOU INDEXT+8 INDEXT+12 INDEXT+16 ;TABELLE ROT ;TABELLE GRUEN ;TABELLE BLAU *************************************************************************** * * * GRAPHIC FUNKTIONS ACRTC FOR ALL FUNKTIONS THE PARAMETER ADRESS MUST BE GIVEN IN A2 ** MODI DC.W COMFILL DC.W DC.W DC.W DC.W SLSD SDSD DC.W * MM PRA DC.W DC.W $0000 $0000 $0000 $0000 $0000 $0000 ;X - COORDINATE ;Y - COORDINATE ;PP - PATTERN POINTER (PROS) ;SLANT AND SOURCE DIRECTION ;SOURCE- AND DESTINATION SCAN ;DIRECTION ;MODIFY MODE ;PATTERN RAM ADDRESS $0000 $0000 * * ************************************************************************** * SUBROUTINE: * * * * * * * FUNKTION: COMMANDEXTENSION: INPUT: OUTPUT: * * INTERNAL: * * WRCOM: MOVEM LEA LEA WRC1 MOVE.W BTST BEO MOVE.W MOVE.W MOVEM RTS WRCOM WRITE COMMANDCODE TO AGC DO :COMMANDCODE COMMANDCODE TO ACRTC D1 :STATUS DO-D1/AO/A1,-(A7) INDEXT(PC),AO INDEXT+4(PC),A1 (AO),D1 #S,D1 WRC1 #FIFO,(AO) DO,CA1) CA7)+,DO-D1/AO/A1 ;STORE DO ;READ STATUSREGISTER ;FIFO READY ;FIFO IS DESTINATION ;WRITE COMMAND ;RESTORE DO ;RETURN * "" ************************************************************************** * SUBROUTINE: WRPARA WRITE COMMANDPARAMETER TO ACRTC * FUNKTION: * COMMAND* * EXTENSION: * * * INPUT: * * * * * * OUTPUT: INTERNAL: * WRPARA: MOVEM LEA LEA BRA.S WRPA1 MOVE.W BTST BEQ MOVE.W WRPA2 DBRA MOVEM RTS PAGE D1 :NUMBER OF PARAMETERS A2 :PARAMETERADRESS PARMETER TO ACRTC D2 D1-D2/AO-A2,-(A7) INDEXT(PC),AO INDEXT+4(PC),A1 WRPA2 (AO),D2 #1,D2 WRPA1 (A2)+, (Al> D1,WRPA1 ;STORE D1 AND A2 ;READ STATUSREGISTER iFIFO READY (A7)+,D1-D2/AO-A2 iWRITE PARAMETER iDEKREMT NUMBER PARAMTERS iRESTORE DATA iRETURN ******************************************************************************* SET COLORREGISTER 0 * SCOLO: D1 COLOR NUMBER * IN: SCOLO: MOVEM MOVE.W AND MOVE.W LSL.W ADD LSL.W ADD LSL ADD BSR MOVEM RTS DO-D2,-(A7) #COREGO,DO #.$OOOF,D1 D1,D2 #4,D1 D2,D1 #4,D1 D2,D1 #4,01 D2,D1 WRDPAR (A7)+,DO-D2 iSET COLOR REGISTER 0 ******~***************************************************************** •••• **. * SCOL1: * IN: SCOL1: SET COLORREGISTER 1 D1 COLOR NUMBER MOVEM MOVE.W AND MOVE.W LSL.W ADD LSL.W ADD LSL ADD BSR MOVEM RTS DO-D2,-(A7) #COREG1,DO #.$OOOF,D1 D1,D2 #4,D1 D2,D1 #4,D1 D2,D1 #4,D1 D2,D1 WRDPAR (A7)+,DO-D2 ;SET COLOR REGISTER 1 ******************************************************************************* SET EDGE COLORREGISTER * SECOL: 01 COLOR NUMBER * IN: SECOL: MOVEM OO-D2,-(A7) MOVE.W AND MOVE.W LSL.W ADD LSL.W ADD LSL ADD BSR MOVEM RTS #ECOREG,DO #$OOOF,D1 D1.D2 #4,D1 D2,D1 #4,D1 D2,D1 #4,D1 D2,D1 WRDPAR (A7)+ ,DO-D2 iSET EDGE COLOR REGISTER * ************************************************************************** * SUBROUTINE: SSLANT SET SLANT IN SLSD WORT (PATTERN) * FUNKTION: * COMMAND* EXTENSION: * :SLANT INPUT: DO * * OUTPUT: DO IN SLSD(BIT 11> * * INTERNAL: D1 A2 * * * * SSLANT: MOVEM DO/DlIA2,- (A7) iSTORE DO AND D1 CLR D1 #8,DO iSHIFT LEFT 8 BIT LSL #3,DO LSL MOVE.W #$07FF,D1 iSET MASK SLSD(PC),A2 ;LOAD SLSD ADRESS LEA D1. (A2) AND.W DO,(A2) ;SET SLANT MODE IN SLSD OR.W (A7)+,DO/D1/A2 MOVEM ;RESTORE ; RETURN RTS * * ************************************************************************** * SUBROUTINE: SESCDI SET SCAN DIRECTION IN SLSD (PATTERN) * FUNKTION: * COMMAND* EXTENSION: * INPUT: :SCAN DIRECTION DO * * DO IN SLSD IN SLSD (BIT 8 -10) OUTPUT: * * * INTERNAL: D1 A2 * '" * SESCDI: MOVEM CLR AND.W LSL MOVE.W LEA AND.W OR.W MOVEM RTS DO/D1/A2,-(A7) D1 #$0007,DO #8,DO #$0800,01 SLSD(PC),A2 D1,(A2) DO,(A2) (A7>+,DO/DI/A2 ;STORE DO AND D1 ;SHIFT LEFT 8 BIT iSET MASK iLOAD MODI ADRESS ;SET SCAN DIRECTION IN SLSD ;RESTORE ;RETURN PAGE * ************************************************************************** * SUBROUTINE: SETSSO * FUNKTION: SET SOURCE SCAN DIRECTION IN SDSD * COMMAND* EXTENSION: * * * * * * INPUT: OUTPUT: INTERNAL: * * * SETSSD: MOVEM CLR AND.W LSL LSL MOVE.W LEA AND.W OR.W MOVEM RTS DO :SOURCE SCAN DIRECTION DO IN SDSD (BIT 11) 01 A2 DO/D1/A2,-CA7) D1 #$0001,00 #8,DO #3,DO #$0700,01 SDSDCPC),A2 D1,(A2) DO,CA2) (A7)+,00/DI/A2 ;STORE DO ANO 01 iBLANKED BIT 15 - 1 iSHIFT LEFT 11 BIT ;SET MASK iLOAD SDSD ADRESS iSET SSD iRESTORE ;RETURN MODE IN SOSD * * ************************************************************************** SETDSD * SUBROUTINE: * * * * * * FUNKTION: COMMANDEXTENSION: INPUT: * OUTPUT: * * INTERNAL: * SET DESTINATION SCAN DIRECTION IN SDSD :OESTINATION SCAN DIRECTION DO DO IN SDSD (BIT 8 -10) 01 A2 * * SETDSD: MOVEM CLR AND.W LSL MOVE.W LEA AND.W OR.W MOVEM RTS PAGE DO/DlIA2, - (A7) 01 #$0007,DO #8,DO #$0800,Dl SDSD(PC),A2 Dl,(A2) 00,(A2) CA7)+,DO/DI/A2 * iSTORE DO AND Dl iBLANKED BIT 15 - 3 iSHIFT LEFT 8 BIT iSET MASK iLOAO SDSD ADRESS iSET DSD iRESTORE iRETURN MODE IN SOSD ************************************************************************** * SUBROUTINE: SETMFY FUNKTION: SET MODIFY MODE IN MM * COMMAND* * EXTENSION: * INPUT: DO :MODIFY MODE * * * * * OUTPUT: INTERNAL: DO IN MM Dl . A2 (BIT 1-0) SETMFY: MOVEM CLR AND.W M,OVE.W LEA AND.W OR.W MOVEM RTS DO/D1/A2,-(A7) 01 #$0003,00 #$FFFC,D1 MMCPC),A2 D1.(A2) DO,(A2) (A7)+,DO/DlIA2 ;STORE DO AND D1 ;BLANK OUT ;SET MASK ;LOAD MM ADRESS ;SET MODIFY MODE IN MM ; RESTORE ;RETURN * * "'***"'*****"'**********"'******"'******************************* •••• ** •••••• *. '" SUBROUTINE: SETPRA * FUNKTION: SET PATTERN RAM ADDRESS IN PRA '" COMMAND* EXTENSION: * * * * * INPUT: OUTPUT: INTERNAL: DO :PATTERN RAM ADDRESS DO IN PRA (BIT 3 - 0) D1 A2 * * SETPRA: MOVEM CLR AND.W MOVE.W LEA AND.W OR.W MOVEM RTS PAGE DO/DI/A2,-(A7) ;STORE DO AND D1 D1 #$OOOF,DO #$FFFO,Dl PRA(PC),A2 Dl,(A2) DO,(A2) ;SET MASK ;LOAD PRA ADRESS (A7)+,DO/D1/A2 ;SET PATTERN RAM ADDRESS IN PRA ;RESTORE ;RETURN * "'*******"'**"'''''''**'''*'''***''''''**'''''''''**'''.*****.***********************.********* •• * SUBROUTINE: SETAER SET AERAMODE IN MODI-BYTE '" F.uNKTION: '" COMMAND'" EXTENSION: INPUT: * * OUTPUT: '" INTERNAL: '" DO :AERA MODE DO IN MODI (BIT 7-5) D1 A2 * * * SETAER: MOVEM CLR LSL MOVE.W LEA AND.W OR.W MOVEM RTS * * DO/DI/A2,-(A7) D1 #5,DO #$001F,Dl MODI(PC),A2 D1. (A2) DO,CA2) (A7)+,DO/D1/A2 ;STORE DO AND D1 ;SHIFT LEFT 5 BIT ;SET MASK ;LOAD MODI ADRESS ;SET AERA MODE IN MODI ;RESTORE ;RETURN ************************************************************************** * SUBROUTINE: * * * * * * * * * * * FUNKTION: COMMANDEXTENSION: INPUT: OUTPUT: INTERNAL: * SETCOL: MOVEM CLR LSL MOVE.W LEA AND.W OR.W MOVEM RTS PAGE SETCOL SET COLORMODE IN MODI-BYTE DO :COLORMODE DO IN MODI (BIT 4-3) Dl DO/DI/A2,-(A7} Dl #3,DO #$00E7,Dl MODI(PC},A2 Dl,(A2) DO,(A2} (A7)+,DO/DI/A2 ;STORE DO AND Dl ;SHIFT LEFT 3 BIT iSET MASK iLOAD MODI iSET COLORMODE IN MODI iRESTORE iRETURN '" ************************************************************************ •• * SUBROUTINE: SETOPM SET OPERATIONMODE IN MODI-BYTE * FUNKTION: * COMMAND* EXTENSION: * INPUT: :OPERATIONMODE DO * * OUTPUT: DO IN MODI (BIT 0-2) * * INTERNAL: Dl * * * * DO/DI/A2,-(A7} SETOPM: MOVEM iSTORE DO AND Dl CLR D1 MOVE.W #$00F8,Dl ;SET MASK MODI(PC),A2 LEA iLOAD MODI Dl,(A2) AND.W DO,(A2) OR.W iSET OPERATIONMODE IN MODI (A7)+,DO/DI/A2 MOVEM iRESTORE RTS iRETURN '" ************************************************************************** SETMOD * SUBROUTINE: INSERTS AERA-, COLOR- AND OPERATIONMODE IN THE FUNKTION: * COMMANDCODE * COMMAND* * EXTENSION: * :COMMANDCODE INPUT: DO * * :MODIFIERED COMMANDCODE OUTPUT: DO * * INTERNAL: * * * SETMOD: MOVEM LEA OR.W MOVEM A2,-(A7) MODI(PC),A2 (A2) ,DO (A7)+,A2 iSTORE A2 ;LOAD MODI ;INSERT MODI IN COMMANDCODE ;RESTORE A2 RTS PAGE ************************************************************************** WRCONR * SUBROUTINE: FUNKTION: WRITE PARAMETER IN THE SELECTED CONTROL REGISTER * COMMAND* * EXTENSION: ... ... ... INPUT: * OUTPUT: * * ... * DO :REGISTER NUMBER Dl :PARAMTER REGISTER TO ACRTC ADRESSREGISTER PARAMETER ACRTC DATAREGISTER INTERNAL: WRCONR: MOVEM LEA LEA MOVE.W MOVE.W MOVEM RTS DO-DI/AO/A1,-(A7) INDEXT(PC),AO INDEXT+4(PC),Al DO,(AO) Dl,(Al> (A7)+,DO-DI/AO/A1 ;REGISTER IS DESTINATION ;WRITE PARAMETER ************************************************************************** * SUBROUTINE: * FUNKTION: * COMMAND* EXTENSION: * RECONR READ THE PARAMETER FROM THE SELECTED CONTROL REGISTER * INPUT: DO :REGISTER NUMBER * * OUTPUT: Dl : PARAMETER INTERNAL: D1 * * * * RECONR: MOVEM LEA LEA MOVE.W MOVE.W MOVEM RTS PAGE DO/AO-A1,-(A7) INDEXT(PC),AO INDEXT+4(PC),A1 DO,(AO) (A1),D1 (A7)+,DO/AO-Al ;DESTINATION REGISTER ;READ PARAMETER ************************************************************************** ... SUBROUTINE: * * * * * * ... FUNKTION: COMMANDEXTENSION: INPUT: * OUTPUT: * * INTERNAL: ... WRDPAR WRITE DRAWING PARAMETER INTO SELECTED DRAWING PARAMETER REGISTER DO D1 :REGISTER NUMBER :PARAMETER * WRDPAR: MOVEM DO-D2/AO-Al,-(A7) INDEXT(PC),AO LEA INDEXT+4(PC),Al LEA MOVE. W (AO) , D2 WRDP1 BTST #1,D2 ;READ STATUSREGISTER ;WRITE FIFO READY BEQ WRDP1 MOVE.W #FIFO, (AO) MOVE.W DO, CAl) MOVE.W D1, CAl) MOVEM CA7)+,DO-D2/AO-A1 RTS ;WRITE COMMAND ;WRITE PARAMETER .... ************************************************************************** REDPAR * SUBROUTINE: FUNKTION: LOAD PARAMETER FROM SELECTED DRAWING PARAMETER REGISTER * INTO THE READ FIFO * COMMAND* * EXTENSION: * INPUT: DO :REGISTER NUMBER * * OUTPUT: D1 : PARAMETER * * INTERNAL: D2 '" * * REDPAR: MOVEM LEA LEA BSR.S MOVE.W MOVE.W MOVE.W MOVEM RTS PAGE DO/D2/AO-A1,-CA7) INDEXT(PC),AO INDEXT+4CPC),A1 CLFIFO #FIFO,(AO) DO,CAl> (Al> ,D1 CA7)+,DO/D2/AO-A1 ;CLEAR READ FIFO ;FIFO IS DESTINATION ;WRITE REGISTER READ COMMAND ;READ PARAMETER FROM FIFO **************"'*********************************************************** .... SUBROUTINE: RFIPAR FUNKTION: READ PARAMETERS FROM READ FIFO * .... CBE SURE ) COMMAND* * EXTENSION: * INPUT: A2 :PARAMETER LIST * * OUTPUT: WRITE THE CONTENTS OF READ FIFO INTO THE PARAMETERLIST * * INTERNAL: D1 * '" * RFIPAR: MOVEM LEA LEA RFST MOVE.W BTST BEQ.S MOVE.W BRA RFEND MOVEM RTS D1/AO-A2,-CA7) INDEXT(PC),AO INDEXT+4CPC),Al (AO) ,D1 #2,D1 RFEND (Al>,(A2)+ RFST (A7)+,D1/AO-A2 ;READ STATUS REGISTER ;READ FIFO EMPTY .... "'************************************************************************* CLFIFO * SUBROUTINE: SET AND RESET THE ABORT-BIT IN THE COMMAND CONTROL REGISTER '" FUNKTION: AFTER EXECUTION THE READ FIFO AND THE WRITE FIFO WILL BE * CLEARED * '" COMMAND* EXTENSION: * * * * * * * INPUT: OUTPUT: INTERNAL: CLFIFO: MOVEM MOVE.W BSR MOVE.W OR.W BSR MOVE.W AND.W BSR MOVEM RTS PAGE DO D1 D2 DO-D2,-(A7) #CCR,DO RECONR #$8000,D2 D2,Dl WRCONR #$7FFF,D2 D2,D1 WRCONR (A7)+,DO-D2 ,LOAD REGISTER NUMBER ;READ CONTROL REGISTER ,LOAD MASK ,SET ABORT BIT ,WRITE CONTROLREGISTER ;LOAD MASK ;RESET THE ABORT BIT ;WRITE CONTROL REGISTER '" ************************************************************************** .. SUBROUTINE: .. FUNKTION: * COMMAND.. EXTENSION: .. .. INPUT: * * .. . .. WPARAM WRITE DATA TO THE PATTERN RAM PRA :PATTERN RAM ADDRESS DO Dl A2 :COMMAND CODE :NUMBER OF WORDS :PARAMETER ADDRESS OUTPUT: INTERNAL: .. WRPLIS DS.W WPARAM: MOVEM LEA MOVE.W OR.W MOVE.W WPRI LEA MOVEA.L MOVE.W MOVE.W BRA.S WPLP1 MOVE.W WPLP2 DBRA MOVEA.L BSR ADD.W BSR MOVEM RTS * 16 DO-D3/A2/A3/A4,-(A7) PRA(PC),A3 (A3),D2 D2,DO D1,D3 WRPLIS(PC),A3 A3,A4 D3,(A3)+ Dl,D3 WPLP2 (A2)+, (A3)+ D3,WPLP1 A4,A2 WRCOM #l,Dl WRPARA ;INSERT COMMAND EXTENSION ;SAVE NUMBER OF WORDS ;LOAD PATTERN LIST ADDRESS ,WRITE ORIGN NUMBER OF WORDS ;LOOP COUNTER TO D3 ,DEKREMENT AND JUMP ;7777777777 ;WRITE COMMAND ;WRITE PARAMETER (A7)+,DO-D3/A2/A3/A4 '" '" ************************************************************************** '" SUBROUTINE: * FUNKTION: * COMMAND-* EXTENSION: .. . INPUT: RPARAM READ DATA FROM THE PATTERN RAM PRA DO D1 :COMMAND CODE :NUMBER OF WORDS TO BE READ * * * * OUTPUT: INTERNAL: LERAM PRLIST DC.W DS.W RPARAM: MOVEM BSR LEA MOVE.W OR.W LEA MOVE.W BSR MOVE.W BSR LEA BSR MOVEM RTS PAGE A2 $0000 16 iPARAMETER ADDRESS iRESERVE 16 WORD DO-D2/A2/A3,-(A7) CLFIFO PRA(PC),A3 (A3),D2 D2,DO LERAM(PC),A2 D1,(A2) WRCOM ~n ,D1 WRPARA PRLIST(PC),A2 RFIPAR iCLEAR FIFO iLOAD COMMAND EXTENSION ADDRESS iINSERT COMMAND EXTENSION iLOAD PARAMETER ADDRESS iWRITE COMMAND iONE PARAMETER TO BE WRITTEN iWRITE PARAMETER iLOAD PARAMETERLIST ADDRESS iREAD OUT READ FIFO (A7)+,DO-D2/A2/A3 * ************************************************************************** * SUBROUTINE: CLPATT * FUNKTION: CLEARED THE PATTERN * COMMAND* EXTENSION: * * * * * * * * INPUT: OUTPUT: INTERNAL: CLPATT: MOVEM LEA MOVE.W MOVE. W BSR MOVEM RTS PAGE A2 DO D1 DO/D1/A2,-(A7) PRAMO(PC),A2 #WPTN,DO #16,D1 WPARAM (A7)+,DO/D1/A2 * ************************************************************************** * SUBROUTINE: CPMOVE * FUNKTION: MOVED CURRENTPOINTER ABSOLUT OR RELATIVE * COMMAND* EXTENSION: * * * * * * * * INPUT: OUTPUT: INTERNAL: CPMOVE: MOVEM BSR MOVE.W BSR MOVEM DO A2 COMMANDCODE --> ACRTC --> ACRTC PARAMETER D1 DO-D.1/A2,-(A7) WRCOM #2,D1 WRPARA (A7)+,DO-D1/A2 :COMMANDCODE :PARAMETERADRESS ;WRITE COMMAND ;NUMBER OF PARAMETERS iWRITE PARAMETERS RTS ************************************************************************** * SUBROUTINE: LINREC * FUNKTION: DRAW AN ABSOLUTE OR RELATIVE LINE OR RECTANGLE * COMMAND* EXTENSION: AERA - COL - OPM * INPUT: * * * OUTPUT: * * * INTERNAL: * LINREC MOVEM BSR BSR MOVE.W BSR MOVEM RTS PAGE DO :COMMANDCODE A2 :PARAMETERADRESS COMMANDCODE --> ACRTC FIFO PARAMETER --> ACRTC FIFO D1 DO-D1/A2.-(A7) SETMOD WRCOM #2.D1 WRPARA (A7>+.DO-D1/A2 ;INSERT COMMANDEXTENSION ;WRITE COMMAND ;NUMBER OF PARAMETERS ;WRITE PARAMETER ************************************************************************** * SUBROUTINE: POLYLG * FUNKTION: DRAW AN ABSOLUTE OR RELATIVE POLYLINE OR POLYGON * COMMAND* EXTENSION: AERA - COL - OPM * * * * * * * * INPUT: OUTPUT: INTERNAL: POLYLG: MOVEM BSR BSR MOVE.W MULU ADD.W BSR MOVEM RTS DO :COMMANDCODE A2 :PARAMETERADRESS COMMANDCODE --> ACRTC FIFO PARAMETER --> ACRTC FIFO D1 DO-D1/A2.-(A7) SETMOD WRCOM (A2).D1 #2.D1 #1.D1 WRPARA (A7H.DO-D1/A2 ;INSERT COMMANDEXTENSION ;WRITE COMMAND ;NUMBER OF POINTS --> D1 ;*2 --> NUMBER OF PARAMETERS ;WRITE PARAMETERS .... ************************************************************************** * SUBROUTINE: DCIRCL DRAW CIRCLE CLOCKWISE OR COUNTERCLOCKWISE * FUNKTION: * COMMAND* EXTENSION: AERA - COL - OPM * * * * * * INPUT: OUTPUT: INTERNAL: DO ;COMMANDCODE A2 ;PARAMETERADRESS COMMANDCODE --> ACRTC FIFO --> ACRTC FIFO PARAMETER D1 * * DCIRCL: MOVEM BSR BSR MOVE.W DO-D1/A2.-(A7) SETMOD WRCOM #1.D1 ; INSERT COMMANDEXTENSION ;WRITE COMMAND ;NUMBER OF PARAMETER BSR MOVEM RTS PAGE WRPARA (A7)+,DO-DlIA2 ;WRITE PARAMETER ; RESTORE '" "'***"'''''''*'''********''''''*''''''*'''*'''**'''********************************************* '" SUBROUTINE: DELLIP * FUNKTION: DRAW A ELLIPSE CLOCKWISE OR COUNTERCLOCKWISE * COMMAND* EXTENSION: AERA - COL - OPM '" '" * * * INPUT: OUTPUT: INTERNAL: DO :COMMANDCODE A2 :PARAMETERADRESS COMMANDCODE --> ACRTC FIFO PARAMETER --> ACRTC FIFO D1 * DELLIP: MOVEM BSR BSR MOVE.W BSR MOVEM RTS DO-D1/A2,-CA7) SETMOD WRCOM #3,D1 WRPARA (A7)+,DO-D1/A2 ;INSERT COMMANDEXTENSION ;WRITE COMMAND ;NUMBER OF PARAMETERS ;WRITE PARAMETER ; RESTORE '" "'******"''''*'''*'''*****'''*************************************"'*"'************"'** RLARC '" SUBROUTINE: FUNKTION: DRAW CLOCKWISE OR COUNTERCLOCKWISE AN ABSOLUTE OR RELATIVE '" ARC '" COMMAND* AERA - COL - OPM '" EXTENSION: * * INPUT: '" * * * * * OUTPUT: INTERNAL: RLARC: MOVEM BSR BSR MOVE.W BSR MOVEM RTS PAGE DO :COMMANDCODE A2 :PARAMETERADRESS COMMAND --> ACRTC FIFO PARAMETER--> ACRTC FIFO D1 DO-D1/A2,-(A7) SETMOD WRCOM #4,D1 WRPARA (A7)+,DO-D1/A2 ;INSERT COMMANDEXTENSION ;WRITE COMMAND ;NUMBER OF PARAMETERS ;WRITE PARAMETER '" ***"''''*******'''********'''***********'''*'''************************"'********"'**"'''' ELLARC * SUBROUTINE: DRAW CLOCKWISE OR COUNTERCLOCKWISE AN ABSOLUTE OR RELATIVE FUNKTION: * ELLIPSE ARC * COMMAND* AERA - COL - OPM * EXTENSION: * * * * * * * * INPUT: OUTPUT: INTERNAL: ELLARC: MOVEM BSR DO :COMMANDCODE :PARAMETERADRESS A2 COMMAND --> ACRTC FIFO PARAMETER--> ACRTC FIFO D1 DO-D1/A2,-(A7) SETMOD ;INSERT COMMANDEXTENSION BSR WRCOM MOVE.W #6,D1 BSR WRPARA MOVEM (A7)+,DO-D1/A2 RTS ;WRITE COMMAND ;NUMBER OF PARAMETERS ;WRITE PARAMETER ************************************************************************** FILREC * SUBROUTINE: FUNKTION: FILLS AN ABSOLUTE OR RELATIVE RECTANGULAR AREA SPECIFIED * WITH CP AND COMMAND PARAMETER WITH THE FIGURE PATTERN STORED * IN THE PATTERN RAM * COMMAND* AERA - COL - OPM * EXTENSION: * INPUT: DO :COMMANDCODE * A2 :PARAMETERADRESS * OUTPUT: --> ACRTC FIFO COMMAND * PARAMETER --> ACRTC FIFO * INTERNAL: D1 * * FILREC: MOVEM BSR BSR MOVE.W BSR MOVEM RTS DO-D1/A2,-(A7) SETMOD WRCOM #2,D1 WRPARA (A7)+,DO-D1/A2 ;INSERT COMMANDEXTENSION ;WRITE COMMAND ;NUMBER OF PARAMETER ;WRITE PARAMETER ************************************************************************** FILL * SUBROUTINE: FUNKTION: FILLS A CLOSED AEREA SURROUNDED BY EDGE COLOR DEFINED IN * THE PARAMETERREGISTER (EDG) USING THE FIGURE PATTERN * SPECIFIED IN THE PATTERN RAM * COMMAND* AERA (COL-MODE MUST SPECIFIED 00) * EXTENSION: (OPM-MODE MUST SPECIFIED 000) * E EGDECOLOR INCLUDED IN THE COMMANDCODE * INPUT: DO COMMANDPARATER * A2 PARAMETERADDRESS * OUTPUT: COMMAND --> ACRTC FIFO * PARAMETER --> ACRTC FIFO * INTERNAL: * * FILL: * FILSTA RAGAIN REFIFO MOVEM LEA LEA DO-D2/AO/A2,-CA7) INDEXT(PC),AO COMFILLCPC),A2 BSR MOVE.W AND.W BSR BSR CLR.L MOVE.W BTST BNE.S BTST BEQ BRA.S BSR MOVE.W MOVE.W BSR MOVE.W SETMOD #$FFEO,D1 D1,00 CLFIFO WRCOM D2 (AO),D2 #2,02 REFIFO #5,D2 RAGAIN FILEND RFIPAR 4(A2),D1 #PRC05,DO WRDPAR #AMOVE,DO ;GET ADRESSREGISTER ADDRESS ;LOAD PARAMETERLIST FOR COMPLEX ;FIGURE PAINTING ; INSERT COMMANDEXTENSION ;LOAD MASK ;MASK COMMANDCODE ;CLEAR FIFO ;WRITE COMMAND ;CLEAR D3 ;READ STATUSREGISTER ;READ FIFO READY ;YES --> READ FIFO ;COMMANO END ;NO --> READ AGAIN ;COMMAND END ;READ FIFO ;LOAD PP --> D1 ;LOAD PATTERN RAM CONTR.REG (PROS) ;SPECIFY THE PATTERN POINT ;LOAO ABSOLUTE MOVE FILEND BSR BRA MOVEM RTS PAGE CPMOVE FILSTA (A7)+,DO-D2/AO/A2 ;SPECIFY THE START POINT ;FILL THE AERA ************************************************************************** * SUBROUTINE: SETDOT * FUNKTION: MARKS A DOT ON THE COORDINATE WHERE THE CP POINTS * COMMAND* EXTENSION: AERA - COL - OPM .... * INPUT: * OUTPUT: DO :COMMAND CODE DO,-(A7) SETMOD WRCOM (A7)+,DO ;INSERT COMMAND EXTENSION ;WRITE COMMAND .... .... * INTERNAL: .... * SETDOT: MOVEM BSR BSR MOVEM RTS '" * ************************************************.***.**.********.********* * SUBROUTINE: PATDRA .... FUNKTION: DRAW PATTERN ONTO THE RECTANGULAR AERA SPECIFIED BY THE CURRENT POINTER AND BY THE PATTERN SIZE * * COMMAND* EXTENSION: AERA - COL - OPM SL :SLANT (BIT 11 ) * SD :SOURCE DIRECTION (BIT 10 - 8) * * * * * * * * * INPUT: '" :COMMAND CODE :PARAMETERADDRESS DO-DI/A2/A3,-(A7) A2,A3 SETMOD SLSD(PC),A3 (A3),Dl Dl,DO ;STORE PARAMETERADDRESS ; INSERT COMMAND EXTENSION ;LOAD SL AND SD EXTENSION ADDRESS OUTPUT: INTERNAL: PATDRA: MOVEM MOVEA.L BSR LEA MOVE.W OR.W * DO A2 BSR MOVE.W BSR MOVEM RTS PAGE WRCOM #I,Dl WRPARA (A7)+,DO-DI/AZ/A3 ;INSERT COMMAND EXTENSION EXCEPT ;AERA - COL - OPM MODE ;WRITE COMMAND ;NUMBER OF PARAMETER ;WRITE PARAMETER ************************************************************************.* GRACPY * SUBROUTINE: COPIES A RECTANGULAR AREA SPECIFIED BY THE ABSOLUTE OR * FUNKTION: RELATIVE COORDINATES TO THE ADDRESS SPECIFIED BY THE * CURRENT POINTER (CP) * • COMMANDAERA - COL - OPM • EXTENSION: S :SOURCE SCAN DIRECTION (BIT 11) • DSD :DESTINATION SCAN DIRECTION (BIT 10-8 * INPUT: :COMMAND CODE DO * * * * * * * A"- :PARAMETERADDRESS ~, OUTPUT: INTERNAL: GRACPY: MOVEM MOVEA.L BSR MOVE.W AND.W LEA MOVE.W OR.W BSR MOVE.W BSR MOVEM RTS PAGE DO-D1/A2/A3,-(A7) A2,A3 SETMOD #$FFC7,Dl D1,DO SDSD(PC),A3 (A3),D1 D1,DO WRCOM #4,D1 WRPARA ;STORE PARAMETERADDRESS ; INSERT COMMANDEXTENSION ;LOAD MASK ;MASK COMMAND CODE ;LOAD EXTENSION ADDRESS ; ;INSERT EXTENSION SAND DSD ;WRITE COMMAND ;NUMBER OF PARAMETER ;WRITE PARAMETER (A7)+,DO-D1/A2/A3 '" ***************************************************************************** * * * ASSEMBLER INTERFACE DRIVER ACRTC * * * ***************************************************************************** ************************************************************************** * SUBROUTINE: * FUNKTION: * * * * * * * * INPUT: OPOINT ASSOCIATES A LOGICAL X - Y SCREEN WITH PHYSICAL FRAME BUFFER ADDRESS :SCREEN NUMBER DO :X - COORDINATE D1 D2 :Y - COORDINATE OUTPUT: INTERNAL: ************************************************************************** OPOINT: MOVEM LEA MOVE.L DIVU MOVE.L MOVE.L MUI.U DIVU AND.I. ADD.L MOVE.L DIVU I.SR.L DO-D7/A2/A3,-(A7) BILDPACPC),A2 (A2)+,D3 #4,D3 (A2)+,D4 (A2),D5 D2,D3 #4,D1 #$0000FFFF,D1 D1,D3 D3,D6 #4,D6 #8,D6 ;LOAD DISPLAY PARAMETER ;PIXEL PER LINE (FRAME) ;IN WORD PER LINE ;NUMBER OF RASTERS (FRAME) ;DISPLAY START ADDRESS ;X COORDINATE IN WORDS ;REST AUSBLENDEN ;PHYSICAL ADDRESS LSR.L AND.L ADD.L LSL.L OR.L AND.L MOVE.L LSL.L OR.L LEA LEA MOVE.W MOVE.W SWAP MOVE.W MOVE.W MOVE.W BSR MOVEM.L RTS #8,D6 #$C,D6 D5,D3 #4,D3 D6,D3 #$00FFFFFF,D3 #30,D7 D7,DO DO,D3 ORGRWD(PC),A3 ORGPAR(PC),A2 D3,2(A3) D3,2(A2) D3 D3,(A3) D3,(A2) #ORIG,DO CPMOVE (A7)+,DO-D7/A2/A3 ;PIXEL IN WORD (DPD) ;MASKED ;PLUS DISPLAY START OFFSET ORGPAR DC.W DC.W $0000 $0000 ;DPH ;DPL ORGRWD DC.W DC.W $0000 $0000 iDGH ,DPL BILDPA DC.L DC.L DC.L 1536 1200 $12ACO ;PIXEL PER LINE iNUMBER OF RASTER ;DISPLAY START ADDRESS ;INSERT DPD ;INSERT SCREEN NUMBER ;NULL POINT ;STORE DPL ; ;STORE DPH ;SET ORIGN ************************************************************************* * SAVE ORIGN EVEN ORIGSAV DC.W DC.W SAVORG: MOVEM.L LEA LEA MOVE.W MOVE.W MOVEM.L RTS $0000 $0000 A4/A3,-(A7) ORGPAR(PC),A4 ORIGSAV(PC),A3 (A4)+, (A3)+ (A4), (A3) (A7)+,A4/A3 ************************************************************************** CLEAR SCREEN * DSCLPA DC.W $0,$FF,$320 DSCLEAR MOVEM.L MOVE.L MOVE.L MOVE.L BSR LEA MOVE.W MOVE.W BSR MOVE.W MOVE.W BSR MOVE.W BSR DO-D2/A2,-(A7) #l,DO #0,D1 #800,D2 OPOINT ORGRWD(PC),A2 #DRWPH,DO (A2)+,Dl WRDPAR #DRWPL,DO (A2),Dl WRDPAR #CLR,DO WRCOM MOVE.W LEA BSR #3,D1 DSCLPA(PC),A2 WRPARA LEA ORIGSAV(PC),A2 MOVE.W #ORIG,DO BSR CPMOVE MOVEM.L (A7)+,DO-D2/A2 RTS ************************************************************************** ABMOVE * SUBROUTINE: FUNKTION: ABSOLUT MOVE * * INPUT: A2 :PARAMETER ADDRESS * * OUTPUT: * * INTERNAL: * * ************************************************************************** ABMOVE: MOVE.W BSR RTS :JI:AMOVE,DO CPMOVE ************************************************************************** * SUBROUTINE: REMOVE RELATIVE MOVE * FUNKTION: .. INPUT: * * * . OUTPUT: .. INTERNAL: .. A2 :PARAMETER ADDRESS ************************************************************************** REMOVE: MOVE.W BSR RTS #RMOVE,DO CPMOVE ************************************************************************** ABLINE * SUBROUTINE: DRAW AN ABSOLUT LINE * FUNKTION: * * * * * .* INPUT: A2 :PARAMETER ADDRESS OUTPUT: INTERNAL: ************************************************************************** ABLINE: MOVE.W B5R #ALINE,DO LINREC RTS ************************************************************************** * SUBROUTINE: * FUNKTION: * INPUT: * * * OUTPUT: * * * INTERNAL: RELINE DRAW A RELATIVE LINE A2 :PARAMETER ADDRESS ************************************************************************** RELINE: MOVE.W BSR RTS #RLINE,DO LINREC ************************************************************************** * SUBROUTINE: * FUNKTION: * INPUT: * * * OUTPUT: * * * INTERNAL: ABRECT DRAW AN ABSOLUT RECTANGLE A2 :PARAMETER ADDRESS ************************************************************************** ABRECT: MOVE.W BSR RTS #ARCT,DO LINREC ************************************************************************** * SUBROUTINE: " * * * * * * * FUNKTION: INPUT: RERECT DRAW A RELATIVE RECTANGLE A2 :PARAMETER ADDRESS OUTPUT: INTERNAL: ************************************************************************** RERECT: MOVE.W BSR #RRCT,DO LINREC RTS ************************************************************************** * SUBROUTINE: ABPOLL * FUNKTION: ABSOLUT POLYLINE * * * * * * INPUT: A2 :PARAMETER ADDRESS OUTPUT: INTERNAL: * ************************************************************************** ABPOLL: MOVE.W BSR RTS IAPLL,DO POLYLG ************************************************************************** REPOLL * SUBROUTINE: RELATIVE POLYLINE * FUNKTION: * * * * * * INPUT: A2 :PARAMETER ADDRESS OUTPUT: INTERNAL: * ************************************************************************** REPOLL: MOVE. W IRPLL,DO BSR POLYLG RTS ************************************************************************** ABPOLG * SUBROUTINE: ABSOLUT POLYGON * FUNKTION: * * INPUT: * * OUTPUT: * A2 :PARAMETER ADDRESS INTERNAL: * ************************************************************************** ABPOLG: MOVE.W BSR IAPLG,DO POLYLG RTS ************************************************************************** * SUBROUTINE: REPOLG * FUNKTION: RELATIVE POLYGON * * INPUT: * OUTPUT: * * INTERNAL: * A2 :PARAMETER ADDRESS * ************************************************************************** REPOLG: MOVE.W BSR RTS #RPLG,DO POLYLG ************************************************************************** * SUBROUTINE: CIRCLE * FUNKTION: DRAW A CIRCLE * * INPUT: * A2 D1 * * * * * :PARAMETER ADDRESS :DRAWING DIRECTION :D1 = 1 CLOCKWISE :D1 = 0 COUNTERCLOCKWISE OUTPUT: INTERNAL: * ************************************************************************** CIRCLE: CMP BNE.S MOVE.W BRA.S CIR1 MOVE.W CIR2 BSR RTS #1,D1 CIR1 #CRCL1,DO CIR2 #CRCLO,DO DCIRCL ;COMPARE DRAWING DIRECTION ;CLOCKWISE ; COUNTERCLOCKWISE ;DRAW ************************************************************************** * SUBROUTINE: ELLIPS DRAW AN ELLIPSE CLOCKWISE OR COUNTERCLOCKWISE * FUNKTION: * INPUT: :PARAMETER ADDRESS A2 * :DRAWING DIRECTION D1 * :D1 = 1 CLOCKWISE * :D1 = 0 COUNTERCLOCKWISE * OUTPUT: * * INTERNAL: * * ************************************************************************** ELLIPS: CMP BNE.S MOVE.W BRA.S ELL1 MOVE.W ELL2 BSR RTS #1.D1 ELL1 #ELPS1,DO ELL2 #ELPSO,DO DELLIP ************************************************************************** * SUBROUTINE: * FUNKTION: * ABC ARC DRAW AN ABSOLUTE CIRCLE ARC CLOCKWISE OR COUNTERCLOCKWISE ABCARC: CMP BNE.S MOVE.W BRA.S ACARC1 MOVE.W ACARC2 BSR RTS #1,D1 ACARC1 #AARC1,DO ACARC2 #AARCO,DO RLARC INPUT: A2 :PARAMETER ADDRESS * D1 :DRAWING DIRECTION * :D1 = 1 CLOCKWISE * :D1 = 0 COUNTERCLOCKWISE * OUTPUT: * * INTERNAL: * * ************************************************************************** ************************************************************************** * SUBROUTINE: * FUNKTION: * * * * * * * * INPUT: RECARC DRAW A RELATIVE CIRCLE ARC CLOCKWISE OR COUNTERCLOCKWISE A2 D1 OUTPUT: :PARAMETER ADDRESS :DRAWING DIRECTION :D1 = 1 CLOCKWISE :D1 = 0 COUNTERCLOCKWISE INTERNAL: ************************************************************************** RECARC: CMP BNE.S MOVE.W BRA.S RCARC1 MOVE.W RCARC2 BSR RTS #1.D1 RCARC1 #RARC1,DO RCARC2 #RARCO,DO RLARC ************************************************************************** * SUBROUTINE: * FUNKTION: * INPUT: * ABEARC DRAW AN ABSOLUTE ELLIPS ARC CLOCKWISE OR COUNTERCLOCKWISE A2 :PARAMETER ADDRESS * * * * * * * D1 :DRAWING DIRECTION :D1 = 1 CLOCKWISE :D1 = 0 COUNTERCLOCKWISE OUTPUT: INTERNAL: ************************************************************************** ABEARC: CMP BNE.S MOVE.W BRA.S AECR1 MOVE.W AECR2 BSR RTS #1,D1 AECR1 #AEARC1,DO AECR2 #AEARCO,DO ELLARC ************************************************************************** * SUBROUTINE: REEARC DRAW A RELATIVE ELLIPS ARC CLOCKWISE OR COUNTERCLOCKWISE * FUNKTION: * * * * * * * * * INPUT: A2 D1 OUTPUT: :PARAMETER ADDRESS :DRAWING DIRECTION :D1 = 1 CLOCKWISE :D1 = 0 COUNTERCLOCKWISE INTERNAL: ************************************************************************** REEARC: CMP BNE.S MOVE.W BRA.S RECR1 MOVE.W RECR2 BSR RTS #1,D1 RECR1 #REARC1,DO RECR2 #REARCO,DO RLARC ************************************************************************** * SUBROUTINE: ABFRCT ABSOLUT FILLED RECTANGLE * FUNKTION: * * * * * * * INPUT: A2 :PARAMETER ADDRESS OUTPUT: INTERNAL: ************************************************************************** ABFRCT: MOVE.W BSR RTS #AFRCT,DO FILREC *"******************************************"*"**************************** REFRCT * SUBROUTINE: RELATIVE FILLED RECTANGLE " FUNKTION: * INPUT: * * * OUTPUT: * * INTERNAL: A2 :PARAMETER ADDRESS * ************************************************************************** REFRCT: MOVE.W BSR RTS #RFRCT,DO FILREC ************************************************************************** PAINT FILLED A CLOSED AERA * FUNKTION: * SUBROUTINE: * INPUT: * * * Dl :Dl = 0 :Dl = 1 EDGECOLOR MODE OUTPUT: * * INTERNAL: '* ************************************************************************** PAINT: PAINl PAIN4 CMP BNE.S MOVE.W BRA.S MOVE.W BSR RTS #l,Dl PAINl #PAINTO,DO PAIN2 #PAINT1,DO FILL **"*"***"*'*******"**"**************""****""******************************* DRADOT * SUBROUTINE: * FUNKTION: DRAW A DOT '* INPUT: * "* " " OUTPUT: INTERNAL: " """*********************************************************************** DRADOT: MOVE.W BSR RTS iDOT·, DO SETDOT ************************************************************************** * SUBROUTINE: * * * * * * * * FUNKTION: INPUT: PTTERN DRAW GRAPHIC PATTERN WHICH STORED IN PATTERN RAM A2 :PARAMETER ADDRESS : (SZ: SZY, SZX) OUTPUT: INTERNAL: ************************************************************************** PTTERN: MOVE.W BSR RTS #PTN,DO PATDRA ************************************************************************** * SUBROUTINE: * FUNKTION: * * INPUT: * * * OUTPUT: * * ABGCPY ABSOLUT GRAPHIC COPY A2 :PARAMETER ADDRESS INTERNAL: ************************************************************************** ABGCPY: MOVE.W BSR RTS #AGCPY,DO GRACPY ************************************************************************** * SUBROUTINE: * FUNKTION: REGCPY RELATIVE GRAPHIC COPY * * INPUT: A2 * * OUTPUT: * * * :PARAMETER ADDRESS INTERNAL: ************************************************************************** REGCPY: MOVE.W BSR #RGCPY,DO GRACPY RTS **************************************************************************** **************************************************************************** VERTIKAL-BLANK ABWARTEN * BLNKTST MOVE BLNKI BSR CMP BLS RTS #RCR,DO RECONR #860,Dl BLNK1 RASTER-COUNT-REGISTER LESEN **************************************************************************** * SUBROUTINE COLTAB * FUNKTION LOAD THE COLORTABLES RED GREEN BLUE * IN * OUT * INTERNAL A2 A3 DO COLTAB BUI * BU2 MOVEM MOVEA.L LEA MOVE.L MOVE.W DBRA A2/A3/DO,-CA7) #COLTR,A2 ROT(PC),A3 #15,DO (A3)+,(A2)+ DO,BUI MOVEA.L LEA MOVE.L MOVE.W DBRA #COLTG,A2 GRUEN(PC),A3 #15,DO (A3) + , (A2) + DO,BU2 MOVEA.L LEA MOVE.L MOVE.W DBRA MOVEM RTS #COLTB,A2 BLAU(PC),A3 #15,DO (A 3) + , (A2) + DO,BU3 (A7)+,A2/A3/DO DC.W EVEN DC.W EVEN DC.W EVEN 0,0,0,255,0,255,255,255,0,0,127,0,127,127,127,0 '" * BU3 BLAU ROT GRUEN 0,255,0,0,255,255,0,255,127,0,0,127,127,0,127,255 0,0,255,0,255,0,255,255,0,127,0,127,0,127,127,136 *************************************************************************** *************************************************************************** *************************************************************************** * * PATTER RAM * * PRAMO DC.W EVEN 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 '" ***************************************************************************** VERSCHIEDENE PATTERN * * SCHRAFFUR PATTER1 DC.W $8080,$4040,$2020,$1010,$0808,$0404,$0202,$0101 DC.W * SCHRAFFUR1 PATTER2 DC.W DC.W * $B005,$500B,$2424,$13C8,$0810,$0420,$0240,$0420 $0810,$1188,$1248,$1188,$0810,$6426,$1242,$0180 SYMBOL2 PATTER6 DC.W DC.W * $COOO,$7E78,$2188,$6186,$4182,$4182,$4182,$3FFC $3FFC,$4182,$4182,$4182,$6186,$1188,$lE78,$0000 SYMBOL1 PATTER5 DC.W DC.W * $0000,$7FFE,$4002,$4002,$4FF2,$4812,$4812,$4992 $4992,$4812,$4812,$4FF2,$4002,$4002,$7FFE,$0000 KLEEBLAT PATTER4 DC.W DC.W * $8888,$8888,$8888,$BBBB,$BBBB,$8888,$8888,$8888 $8888,$8888,$8888,$B88B,$8888,$8888,$8888,$8888 MOSAIK PATTER3 DC.W DC.W * $8080,$4040,$2020,$1010,$0808,$0404,$0202,$0101 $0000,$OOOO,$OOOO,$0780,$1840,$1720,$2110,$472C $4952,$C126,$7EEE,$30C4,$38E7,$38E3,$0000,$OOOO COURSOR PATTER7 DC.W DC.W EVEN END $0000,$lFEE,$OFFE,$07FE,$03FE,$01FE,$01FE,$03FE $07FE,$OFOE,$lFOE,$3E06,$7C02,$7800,$3000,$0000 LIBRARY FOR THE AGC-l FORCE COMPUTERS Inc.!GmbH All Rights Reserved This document sholl not be duplicated. nor its contents used for any purpose, unless express permission has been granted. Copyright by FORCE Computers® *~*~************************************************************** * * change * * * * * * * The information in without notice and by FORCE Computers. * * * Neither FORCE Computers nor the authors assume any responsi- ~ bility for the use or reliability of this document or the * described software. * * * * * * General permission to copy or modify. but not for profit. is * hereby granted. provided that the above copyright notice is * * * * * * * * * this document is subject to should not be construed as a commitment Copyright eC) * * * 1986. FORCE Computers included and reference made" to the fact that privileges were granted by FORCE Computers. reproduction * * * ****************************************************************** 1---------------------------------------------------------------1 This library is used as driver for the AGe. The implemented commands can be linked to a user program as follows: F77 EXAMPLE F77L EXAMPLE,AGCLIB/L,XLIB/L 1 File name: Programmed by: Date: AGCLIB:DOC K. Nguyen-Thanh 09/18/86 1 1---------------------------------------------------------------- 1-----------------------------------------1 1 1 AGe Address register: $C3COOO AGC Data register: eC3C002 1 I 1 1 1-----------------------------------------1 ******************************************************************* * * INITIALISATION COMMANDS * * * * ******************************************************************* 1---------------------------------------1 I Subroutine: RESET 1 1 Function: reset AGC I 1---------------------------------------1 call RESET 1 1---------------------------------------1 1 Subroutine: CLEARI 1 1 1 Function: clear image memory Ram Address and COOOOO - C40000 C40000 - E3FFFE 1 1---------------------------------------1 call CLEARI 1-----------------·-------------------------------------------------Subroutine: INIT1 Function: Initialize the screen Note: The Information to be used for the Initialistion of the AGe is written in the file 'SCREEN:DAT' It can be modified, when mode=1. If mode=O, the screen will be initialized automaticly. Mode=1: After the Modification the Information is saved and a ind~x > 60 must be entered to start the initialisation. 1 1------------------------------------------------------------------integer mode CALL INIT1(mode) Example: The frame for non-interlced screen and 4 bit mode(GBM) is initialized as follows: horizon~al sync(r82) horizontal dispCr84) vertical sync (r86) vertcal display(r88) #$5809 #$03BF #$0383 1$3aOl # of lines displayed # of pixel per line # memory start address # no zoom (r02) 4 bit/pixel CCR base screen enabled DCR (r06) ACRTC is master,GAI=8 (r04) -> hc=58, -> us=B , hws=09 hdw=3F -> 899 lines -> back porch 59 lines -> vsync lline 800 1024 1$12ACO #$200 I$COIO I$C038, non-interlaced 1------------------------------------------------------------------call INITI(O) 1-------------------------------------------------------------------1 1 Subroutine: GCP16 1 1 1 1 Function: load color chips 16 times Address for color rot chip = eC36000 Address for color green chip $C38000 Address for color blue chip = eC3AOOO Predefined values (in file AGDDEF:SR) 1-------------------------------------------------------------------1 call GCPl6 At first the AGC must be reset, initialized. The memory must be cleared and the color chips must be loaded in the sequence below: call call call call RESET1 CLEAR 1 INITl(O) or call INITl(l) GCP16 *********************************************************************** The following 6 routines can be used to set the graphic * * parameters: * * - source scan direction call SETSSD(ssd) * - destination scan direction call SETDSD(dsd) * * - pat.tern RAM address call SETPRA(pra) * * - graphic area call SETAER(aer) * - modify mode call SETMFY(mm) * * - operation mode call SETOPM(op) * * The defauld values of ssd,dsd,pra,aer,mm,op are O. * * * * *********************************************************************** .. .. .. .. I-----------------------------~---------------------------------------1 I Subroutine: SETSSD I I Function: set source SCAN direction in SDSD. I Note: This function set the defauld for the bit 11 for all the commands codes using the source scan direction. ssd = 0 or 1 I 1 1 I 1 1 1 1 1 1---------------------------------------------------------------------1 integer ssd call SETSSD(ssd) Example: call SETSSD(O) 1---------------------------------------------------------------------1 1 1 Subroutine: SETPRA Function: set pattern RAM address. This function sets the defauld for Bit (0-3) for all the commands codes using the pattern RAM. A pattern contains 16 words (16x16 bytes). The pattern RAM address (pra) ranges from 0 to 15. 1 1 1 1 1---------------------------------------------------------------------1 integer pra call SETPRA (pra) Example: call SETPRA(l) [--------------------------------------------------------------------1 1 Subroutine: SETAER Function: Set area-mode. Note: This function sets the defauld for Bits (5-7) for alll 1 the commands codes using the aera. 1 The aeras (aer) range from 0-7. 1 1 1--------------------------------------------------------------------1 integer aer call SETAER(aer) Example: call SETAER(l) I------------~-------------------------------------------------------1 1 Subroutine: SETOPM Function: Set operation mode. Note: Bit (0-2) in the command code, which depended to the operation mode, will be set to opm. The operation mode ranges from 0 - 7 1 1 1 1 1 1 1--------------------------------------------------------------------1 integer opm call SETOPM(opm) Example: call SETOPM(l) 1----------------------------------------------------------------------------1 1 Subroutine: SETMFY 1 1 I Function: Set modify mode. Note: This function sets the defauld for Bits (0-1) for all the commands codes using the mofify mode. mm ranges from 0 to 3. mm 0: replace frame buffer data with command parameter datal mm 1: OR frame buffer data with command parameter data. 1 mm 2: AND frame buffer data with command parameter data. 1 mm - 3: EOR frame buffer data with command parameter data. and rewrite to frame buffer. --------------------------------------------------------------------------- integer mm call SETMFY(mm) Example: call SETMFY(l) ********************************************************************** * THE FOLLOWING ARE GRAPHIC COMMANDS * * * * * ********************************************************************** 1--------------------------------------------------------------------1 1 Subrout~ne: ABMOVE 1 1 1 1 Function: Absolute move"to the position (ay,ax) 1 1 Note: 1 1--------------------------------------------------------------------1 integer ax,ay call ABMOVE(ay,ax) Example: call ABMOVE(lOO,200) 1--------------------------------------------------------------------1 1 Subrout~ne REMOVE 1 Function: Relative move to the position (ry,rx). 1 1 1 1 Note: 1 1--------------------------------------------------------------------1 integer ry,rx call REMOVE(ry,rx) Example: call REMOVE(lOO,200) t--------------------------------------------------------------------1 1 Subroutine SCOLO 1 Function The color register 0 (CLO) is set to 'col'. Note: This register defines the drawing color in addition t.o t.he color register (CLl) . If t.he Bcaned pattern RAM is equal t.o ' 0 ' the color is in CLO. If the scaned pattern RAM is equal to ' I ' the color is in CL1.(See also SCOLI) . 1 I-------------------------~------------------------------------------ integer col call SCOLO(col) Example: set color white call SCOLl< 7) 1-------------------------------------------------------------------1 Subroutine SCOL1 Funct.ion: The color register I Note: This register defines the drawing color in addition to the color register 0 (CLO). If the scaned pattern RAM is equal to '1' the color is in CLI. If the scaned pattern RAM is equal to , 0 ' the color is in CLO.(see also SCOLO). 1 1 (CLI) is set to 'col'. 1 1-------------------------------------------------------------------integer col call SCOLl(col) Example: set color white call SCOLl(7) 1--------------------------------------------------------------------1 Subroutine: SECOL Function: Set edge color register. Note: The paint command oan change the edg 1 00101'. 1--------------------------------------------------------------------1 int.egE,r edool call SECOL(edcol) Example: oal1 SECOL(S) J--------------------------------------------------------------------1 1 Subroutine: ABRECT 1 I 1 Function: Draw an absolute rectangle. The rectangle is defined by the current point (CP) and the absolute cordinate x,y. I Note: I integer x,y 1 1 1 1--------------------------------------------------------------------1 call ABRECT(y,x) Example: draw a rectangle defined by absolute cordinate (100,200) and (150,300). call ABMOVE(100,200) call ABRECT(150,300) I--------------------------------------~-----------------------------1 Subroutine: RERECT Function: I Draw a relative rectangle. The rectangle is defined by CP and the relative coordinate dx,dy. Note: 1 1 1 1 I I 1--------------------------------------------------------------------1 inteqer dx,xy call RERECT(dy,dx) Example: If the current point(CP) is at (100,200), this example will draw the rectangle between (100,200) and (150,300). call RERECT(SO.lOO) 1--------------------------------------------------------------------1 I Subroutine: Function: Note: I ABPOLL Draw an absolute polyline. Each line from polyline connects the absolute coordinate with the previous coordinate. abuf is an array of coordinates (xl,yl ... xn,yn) n is the number of the coordinates +1. 1 1--------------------------------------------------------------------1 integer abuf(512),n call ABPOLL(abuf,n) Example: draw a polyline consists of 2 lines. abuf(l)=lOO abuf' (2'):= 100 abuf(;3)=200 abuf(4)=-200 call ABMOVE(O.O) call ABPOLL(abuf,S) 1--------------------------------------------------------------------1 1 Subroutine: REPOLL 1 1 Function: Draw a relative polyline. Each line from polyline connects the relative coordinate with the previous coordinate. Note: abuf is an array of coordinates (x1,yl ... xn,yn). n is number of the coordinates +1. 1--------------------------------------------------------------------1 integer abuf(S12),n call REPOLL(abuf,n) Example: draw a polyline consists of 2 lines. abufCl)=100 abuf(2)=100 abuf(3)=lOO abuf(4)=-300 call ABMOVEEDG I already painted and as edge color 1 or COL = CLO or COL = CLl (satisfied if one of I the condition is met) 1 or COL = CLO or COL = CLl (satisfied if one of I the condition is met) I I I 1----------------------------------------------------------------------1 1 I I I Dot is redarded as unpainted COL <> and COL <> and COL <> (satisfied conditions EDG CLO CLl if ALL the are met) COL = EDG and COL <> CLO and COL <> CLI (satisfied ALL the conditions are met) 1 ------------------------------------------------------------------------ 1-------------------------------------------------------------------------integer edg call PAINT(edg) Example: fill a circle call call call call call COLNEU(7) EDGCOL(l) ABMOVE(lOO,lOO) CIRCLE(SO,l) PAINT(l) 1---------------------------------------------------------------------Subroutine: WPARAM 1 I 1 1 1 Function: Write pattern RAM Note: A pattern contains 16 words (16x16 bytes). The pattern RAM address is created by calling the routine SETPRA. Default address is O. Bevor write pattern, the pattern RAM control register (set, start- and endpointer in register $B05,$806,$B07 must be written). nr = Number of words (0 .. 15) pattrn = pattern , B x long word = 16 1---------------------------------------------------------------------integer nr,i integer pattrn(B) character*9 buffer(B) call WPARAM(pattrn,nr) Example: write pattern 'R' to pattern RAM 1 1 6 DATA buffer /'$F01C7B1C','$3CICIE1C','$OFIC079C', '$03DC3FFC','$7FFCFFFC','$E01CEOIC'.'$E01CFFFC', '$7FFC1FFC'/ do 6 i=1,B CALL XCDB(buffer(i),pattrn(1» continue 1----------------------------------------------------------------------1 1 Subroutine: RPARAM 1 1 1 1 Function: Read pattern RAM in to buffer Note: A pattern contains 16 words (16x16 bytes). The pattern RAM address is created by calling the routine SETPRA. Default address is O. nr = Number of word (0 .. 15) pattrn = pattern , B x long word = 16 1 1 1 1 1 1 1 1 1-----------------------------------------------------------------------1 int.eger nr, i integer pattrn(B) character*9 buffer(S) call RPARAM(pattrn,nr) Example: read 16 words from pattern RAM CALL RPARAM(pattrn.16) I--------~------------------------------------------------------------1 I I 1 1 1 1 Subrout_ine PTTERN 1 Function: Draw a graphic pattern which stored in pattern RAM 1 1 1 Note: The pattern is created by calling the routine WPARAM. No parameter is needed. 1 1---------------------------------------------------------------------1 1 call PTTERN 1---------------------------------------------------------------------1 Subroutine DRADOT 1 Function: Draw a dot 1 1 Note: 1 1-----------------------------------------------------------------~---I call DRADOT 1---------------------------------------------------------------------1 Subroutine ABFRCT 1 1 Function: 1 Fill the rectangle with the predifined color. 1 1 1 Note: 1---------------------------------------------------------------------1 integer ay,ax call ABFRCT(ay,ax) Example: fill the rectangle defined by CP(100,100) and <150,150) call ABMOVE(100,100) call REFRCT(150,150) 1---------------------------------------------------------------------1 1 Subroutine REFRCT 1 Function: Fill rectangle with the predefined color. 1 1 1 Note: 1--------------------------------------------------------------------1 integer ry,rx call REFRCT(ry,rx) Example: fill the rectangle defined by CP(100,100) and (150,150) call ABMOVE(100,100) call REFRCT(SO,SO) 1-------------------------------------------------------------------1 1 Sotfware-cursor as crosshair I Function: Blends a crosshair at CPo Note: The cursor step, size and color can The cursor size must be multiple of stepx,stepy are the step, which the has to move. If stepx=O and stepy=O d'ont move. I 1 be changed. 2. cursor the cursor 1 1-------------------------------------------------------------------1 integer dx,dy,step,size,coi call CURSORCstepx,stepy,size,col) Example: call CURSOR(O,O,8,4) 1-------------------------------------------------------------------1 1 Subroutine: CPXY 1 1 Function: Read current point 1 1 Note: 1 1--·-----------------------------------------------------------------1 integer apx,apy call CPXY(apy,apx) Example: call CPXYCapy,apx) write(9,*) 'absolute coordinate apy, apx ~',apy,apx 1-------------------------------------------------------------------1 1 Subroutine WRITPA Function: Write paramter register with value 1 Note: I--------------------------~----------------------------------------1 integer val, reg call WRITPA(val,reg) Example: write pattern pointer register PrOS,Pr06,Pr07 before write pattern RAM. call WRITPA(O,2053) call WRITPAC2,2054) call WRITPA(2,20SS) 1-------------------------------------------------------------------1 Subroutine READPA 1 1 Function: Read paramter register. Note: before the subroutine is called I the parameter must be written 1 1 1--------------------------------------------------------------------1 integer val call READPA (val) Example: call READPA(val) write(9,*) 'Parameter = ',val END USER NOTES FORCE COMPUTERS Inc.!GmbH All Rights ReseNed This document shall not be duplicated, nor its contents used for any purpose, unless express permission has been granted. Copyright by FORCE Computersll!> MODIFICATIONS FORCE COMPUTERS Inc.lGmbH All Rights ReseNed This document shall not be duplicated, nor lis contents used for any purpose, unless express permission has been granted. Copyright by FORCE Computersi!>
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