800_9049 0_8400_Scientific_Computing_System_Reference_Handbook 800 9049 0 8400 Scientific Computing System Reference Handbook
800_9049-0_8400_Scientific_Computing_System_Reference_Handbook 800_9049-0_8400_Scientific_Computing_System_Reference_Handbook
User Manual: 800_9049-0_8400_Scientific_Computing_System_Reference_Handbook
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SCIENTIFIC COMPUTATION
E L E C T RON IC
ASSOC IA T E S, INC. West Long Branch, New Jersey
8400 SCIENTIF1C COMPUTING SYSTEM
REFERENCE HANDBOOK
•
I
Publ. No. 00 800 9049-0
@ELECTRONIC ASSOCIATES, INC.
ALL RIGHTS RESERVED
PRINTED IN U.S.A.
CONTENTS
CHAPTER 1 - SYSTEM DESCRIPTION . • . . . . • . • . . . . . . . . . . . . . . • . . • . . . . • . . . . . . . . . • . .
1-1
1.1
INTRODUCTION . . . . . • . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-1
1. 2
EXPANSIONS . . . . . . . . . . • . . . . • . • . . . . . • • . • . • . . . . . • . . . • . . • . . . . . . . . . . .
1-1
1. 2. 1
8402 Basic Computing System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-3
1. 2. 2
8403 Basic Computing System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-3
1. 2. 3
8410 Central Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-3
1. 2.4
8420 Memory Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-4
1. 2. 5
8430 Exchange Module . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-4
1. 2. 6
8440 Desk Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . .
1-4
1. 2. 7
8490 Power Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-4
PROCESSOR......................................................
1-6
1. 3
1. 4
1. 5
1. 3. 1
Memory Word . • • . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . • . . . . • . . .
1-6
1. 3. 2
Instruction Word • . . . . . . • . • . . . . . . . . . . . . . . • . • • . • . . . . . . . . . . . . . . .
1-7
1. 3. 3
Data, Word Formats . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-7
1. 3.4
Processor Registers . . . . . . . . . . . . • . . . . • . . • . . . . . . . . . . . • . . . . . . . . .
1-10
ADDRESSING • • • . . . • . . . • . . . . • . . • . . . • . . • . . . . • . . . . . • • . . . . • . . • . . . . . . .
1-12
1. 4. 1
Direct Addressing • . • • • • . . • . . . . • . • • . • • • • . • . . • • • • • • . . • . • • . • • • . .
1-12
1. 4.2
Indexed Addressing . . • . . • . • . • • • . • . . . • . . . . . . • . • . . . . . . • . . . . . • . . .
1-13
1. 4.3
Indirect Addressing • . . • • . . . • . . . . • . . • . . . . . . . • . . . . . . • . . . . • . . . . . .
1-13
1. 4. 4
Immediate Addressing • • . • . • . • • . • . . • . • • . . . • • . • • • . • • . . . . • . • . . . . .
1-13
INTERRU PT SYSTEM • • . . . . . . . • . . . • . . . • • . . . . . . . . . • . . . . . . . . . . . . . . . . . .
1-13
CHAPTER 2 - INSTRUCTION REPERTOIRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1
2. 1
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1
2.2
EFFECTIVE ADDRESS CALCULATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1
2. 2. 1
Direct Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1
2. 2. 2
Indexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1
2. 2. 3
Indirect AddreSSing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-2
2. 2.4
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-2
2.2.5
Combinations of AddreSSing Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-4
2. 3
ARITHMETIC INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-6
2.4
NOTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-6
2.4. 1
Addressing Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-7
2.4.2
Register Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-7
THE FIXED POINT INSTRUCTION CLASS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-8
2. 5. 1
The Save Register . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . .
2-8
2. 5. 2
2. 5
The Accumulator Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-9
2. 6
THE EXTENDED PRECISION INSTRUCTION CLASS . . • . . . . . . . . . . . . . . . . . . . . . . .
2-9
2. 7
THE INDEX INSTRUCTION CLASS . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-10
2.8
FLOATING POINT INSTRUCTION CLASS • . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . .
2-11
i
CONTENTS (Cont)
2.8.1
Floating Divide. • . . • . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . .
2-12
2.8.2
Floating Multiply. . . . . . . . . . . • . . . . . . • . . . . . . . . . . . . . . . • . . • . . . . . . .
2-13
THE DOUBLE PRECISION INSTRUCTION CLASS. . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-13
2.10 THE INTEGER INSTRUCTION CLASS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-14
2.9
2.10.1
Floating...................................................
2-15
2.10.2
Integerizing . . . . . . . . • . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-15
2.11 BOOLEAN CONNECTIVE INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-16
2.11. 1
The Mnemonics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-17
2.11. 2
Addressing.................................................
2-18
2.12 CONDITIONAL INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-21
2.12.1
The Flag Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-21
2.12.2
Index Jumps XJ, XJT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-22
2.13 INSTRUCTIONS TO LOAD AND STORE SPECIAL REGISTERS. . . . . . . . . . . . . . . . . . .
2-22
2. 13. 1
Load Register or Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-22
2.13.2
Store from Register or Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-23
2.13.3
The Flag Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-23
2.13.4
Location Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-23
2. 13. 5
Timer....................................................
2-24
2. 13.6
Mask Register . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-24
2.13.7
Console Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-24
2.14 EXEC BIT INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-24
2.14.1
Exec Bit Controls . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-24
2.14.2
Accumulator Exec Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-25
2.15 INPUT/OUTPUT INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-25
2. 15. 1
SFL Instruction (Set Function Line) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-25
2.15.2
TSL Instruction (Test Status Line) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-27
2.15.3
LDCD, STCD Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-27
2.15.4
LDCC, STCC Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-28
2.15.5
LDOB, STIB Instructions.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-29
2.16 SHIFT, ROTATE AND NORMALIZE INSTRUCTIONS
..........................
2-29
2. 16. 1 Arithmetic Shift . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . . . . . . . . . . . . . . . .
2-29
2.16.2
2-30
Rotates...................................................
CHAPTER 3 - PRIORITY INTERRUPT SYSTEM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ii
3-1
3.1
INTRODUCTION...................................................
3-1
3.2
BASIC OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1
3.3
PRIORITy.......................................................
3-1
3.4
INTERRUPT CONTROL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-3
3.5
MASKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5
3.6
USER/MONITOR MODE AND THE INTERNAL INTERRUPTS. . . . . . . . . . . . . . . . . . . . .
3-6
3.6.1
3.6.2
3-6
3-7
User/Monitor Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Interrupts. . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . .
CONTENTS (Cont)
Page
3.7
EXTERNALmTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-10
3.8
CONSOLE INDICATORS
3-10
CHAPTER 4 - mpUT/OUTPUT SYSTEM
..........................................
4-1
4.1
mTRODUCTION...................................................
4-1
4.2
DATA CHANNELS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4-1
4.3
4.4
4.5
4.2.1
Function
4-1
4.2.2
Structure
4-2
4.2.3
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4
4.2.4
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6
4.2.5
Byte Assembly/Disassembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-7
4.2.6
Code Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-8
AUTOMATIC DATA CHANNEL PROCESSOR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4-8
4. 3. 1
Function..................................................
4-8
4.3.2
Structure..................................................
4-8
4.3.3
Control Words
4-8
4.3.4
Operation
..............................................
.................................................
4-10
SYSTEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-11
4.4.1
Function..................................................
4-11
4.4. 2
Structure..................................................
4-12
4.4.3
SFL/TSL Instructions
.........................................
4-13
PERIPHERAL DEVICES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4-14
4.5.1
Typewriter
................................................
4-14
4.5.2
Card Reader (Models 8452, 8453, and 8454) . . . . . . . . . . . . . . . . . . . . . . . . . ..
4-16
4. 5. 3
Paper Tape Reader .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4- 20
4.5.4
Paper Tape Punch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,
4-21
4.5.5
Line Printer (Models 8461, 8462, and 8463) . . . . . . . . . . . . . . . . . . . . . . . . . ..
4-22
4.5.6
Card Punch (Models 8455 and 8456) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-26
CHAPTER 5 - COMPUTER CONSOLE OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-1
5.1
mTRODUCTION...................................................
5-1
5.2
CONTROLS AND INDICATORS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5-2
5.2.1
Register Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-2
5.2.2
Typewriter Input Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-3
5.2.3
Exponent Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-5
5.2.4
Interrupt Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-5
5.2.5
Channel Condition Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-5
5.2.6
Parity Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-6
5.2.7
System Flag Indicators . . . . . . . . . . . . . . . .
5.2.8
Programmer Flag Controls and Indicators. . . . . . . . . . . . . . . . . . . . . . . . . . ..
5-6
5-6
5.2.9
Console Interrupt Controls and Indicators ... . . . . . . . . . . . . . . . . . . . .
5-6
5.2. 10
Configuration Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-6
5.2. 11
AUTO LOAD and AUTO DUMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-6
iii
CONTENTS (Cont)
Page
5.3
5.4
5.2. 12
Clock Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5-7
5.2. 13
System Controls and Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-7
5.2. 14
Console Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5-7
CONSOLE DISPLAY
5-7
5.3.1
Accumulator
...............................................
5-7
5.3. 2
Display Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5-7
5.3.3
Memory Data
5-8
5.3.4
Memory Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-8
5.3.5
Exchange Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-8
5-8
5.3.6
Location Counter
5.3.7
Channel Function
........................................... .
5-8
5.3.8
Channel Buffer ... . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . .. . . . . .
5-9
5.3.9
Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-9
5.3.10
Typewriter Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5-9
Maintenance Panel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5-9
5.4. 1
Lamp Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5-9
5.4.2
Keyboard
5-9
5.4.3
Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5-9
5.4.4
Mode.....................................................
5-10
5.4.5
Left Half, Right Half, Left Exec, and Right Exec .... . . . . . . . . . . . . . . . . . ..
5-10
5.4.6
PCO, PC1, PC2, and PC3
......................................
5-10
5.4.7
Data Test
.................................................
5-10
5.4.8
ERR(Error) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-10
5.4.9
BankSelect................................................
5-11
5.4.10
PatternControl..............................................
5-11
5.4.11
Memory - LD/NORM/UNLD .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5-11
5.4.12
Clock - STEP/NORM/START . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-11
5.4.13
Channel Select
5-11
5.4.14
Device Select
5-11
5.4.15
Byte 4/8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-12
5.4.16
EBITE/E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-12
5.4.17
Code-BIN/BCD..............................................
5-12
5.4. 18
DBCO, DBC 1, DBC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-12
5.4.19
DSCO, DSC1, DSC2
5-12
5.4.20
CSCO, CSC1, CSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-12
5.4.21
C1CO, C1C1 • . . . • . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . • . . • . . . . . . ..
5-12
5.4.22
CCOThroughCC4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-12
APPENDIX 1 - WORD FORMATS
iv
................................................
...............................................
A1-1
1.
INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
A1-1
2.
LOGICAL DATA .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
A1-1
3.
FIXED POINT FRACTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
A1-1
CONTENTS (Cont)
Page
4.
FLOATING POINT NUMBERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Al-2
5.
INTEGERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Al-2
6.
ALPHANUMERIC DATA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Al-2
7.
GENERALIZED DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Al-3
APPENDIX 2
8400 INSTRUCTION AND TEST MNEMONICS. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
A2-1
APPENDIX 3 - TABLE OF INTERRUPT ADDRESS CODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
A3-1
1.
ANALOG-TO-DIGITAL CONVERSIONS ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
A3-2
2.
OPERATION CODES FOR ANALOG MONITOR/CONTROL
A3-2
.......................
APPENDIX 4 - TABLE OF SFL/TSL CODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
A4-1
1.
PROCESSOR INTERRUPT SFL
A4-1
2.
PROCESSOR INTERRUPT TSL
A4-1
3.
EXCHANGE INTERRUPT SFL
A4-2
4.
EXCHANGE INTERRUPT TSL
A4-2
5.
HYBRID SFL's . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
A4-2
APPENDIX 5 - CHARACTER CODE EQUIVALENCE TABLE
.............................
A5-1
APPENDIX 6 - POWERS OF TWO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . .
A6-1
APPENDIX 7 - OCTAL-DECIMAL INTEGER CONVERSION • . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A7-1
APPENDIX 8 - HOLLERITH CARD CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A8-1
APPENDIX 9 - LINKING LOADER TEXT BINARY CARD FORMAT
..............•..........
A9-1
..........................................
AlO-1
APPENDIX 10 - PAPER TAPE FORMAT
APPENDIX 11 - TWO'S COMPLEMENT ARITHMETIC
.................................
A11-1
1.
THE TWO'S COMPLEMENTS SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
A11-1
2.
RANGE OF NUMBERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
A11-1
3.
TRUNCATION AND ROUND-OFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
A11-1
4.
SHIFTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
All-3
5.
OVERFLOWS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
All-4
6.
MULTIPLE PRECISION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Al1-4
APPENDIX 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
A12-1
v/vi
ILLUSTRATIONS
Figure
Number
Page
Title
1-2
1-1
1-2
Typical 8400 Scientific Computing System
8400 System Diagrams . ... .
1-3
Memory Word Format .... .
1-6
1-4
Instruction Word Format- . . . . . . . .
1-7
1-5
Summary of 8400 Word Format ... .
1-8
1-6
Processor Registers . . . . . . . .
1-10
1-7
Universal Accumulator Formats
1-11
2-1
8400 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-2
2-2
Effective Address Calculation . . . . . . . . . . . . . . . . . . . .
2-5
3-1
Interrupt Register Mask Enable Configuration . . . . . . . . . . . . . . . . . . . .
3-2
1-3
3-2
Interrupt States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4
3-3
Multi-Level Interrupts . . ". . . . . . . . . . .
3-4
3-4
Internal Interrupt Conditions .
3-7
3-5
Console Interrupt Buttons ...
3-9
4-1
Exchange Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-1
4-2
The Elements of a Data Channel . . . . . . . .
4-3
4-3
Data Channel SFL Instructions
4-5
4-4
4-6
4-5
Data Channel TSL Instructions
Program-Controlled Data Transfer . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6
Byte Size/Byte Count Variation . . . . . . . . . . . . . . . . . . . . . . .
4-8
4-7
Channel Control Word Format
.................. .
4-9
4-8
ADC P Action for a TCD Operation . . . . . . . . . . . . . . . . .
4-11
4-7
4-9
Typewriter Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . .
4-15
4-10
Connection of Typewriter to the Channel Buffer Register
4-15
4-11
4-12
Typewriter Character Position in Memory
.........
. ........ .
4-15
Typewriter SFL Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-15
4-13
Hollerith- BCD Code on a Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-17
4-14
Position of Binary Card Characters in an 8-bit Byte . . . . . . . . . . . . . . . . . . . . . . .
4-17
4-15
Card Reader TSL Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-18
4-16
Card Reader SFL Codes . . . . . . . . . . . . . .
4-19
4-17
Paper Tape Reader SFL Instructions . . . . . . . . . . . . . . . . . . . . . . . . .
4-21
4-18
Paper Tape Punch SFL Instructions . .... .
4-22
4-19
Vertical Format Codes . . . . . . . . . . . . . .
4-24
4-20
Line Printer TSL Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-25
4-21
Line Printer SFL Instructions . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-25
4-22
Card Punch SFL Instructions
4-28
4-23
Card Punch TSL Instructions
4-29
vii
ILLUSTRATIONS (Cont)
Figure
Number
Title
4-24
4-25
Magnetic Tape SFL Instruction
4-30
Magnetic Tape TSL [nstruction
4-31
5-1
5-2
Control Console ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-1
Control Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-2
5-3
Register Display/[nput-Output Typewriter . . . . . .
5-3
5-4
Paper Tape Reader and Maintenance Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-4
5"'-5
System Control Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-4
<
••••
5-6
System Display Panel . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-8
5-7
Maintenance Control Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-10
viii
CHAPTER 1
SYSTEM DESCRIPTION
1. 1
INTRODUCTION
terrupt lines, special control registers, location
counter, interval timer control, instruction register,
The 8400 Scientific Computing System (Figure 1-1)
flag register, high-speed save register, and seven
Organization is made up of three autonomous subsys-
index registers including the Universal Accumulator.
tems; memory, processor, and exchange, which
operate together from one control. Figure 1-2 illus-
The last subsystem, the exchange, consists of a data
trates, in block diagram form, a typical 8400 Scien-
channel control system and a system interface. The
tific Computing System.
data channel control system provides a fully buffered
interface with external input/output (I/O) devices. It
The memory consists of from one to four banks with
includes up to eight two-way data channels which can
individual controls. Each bank has four storage ac-
be controlled by either the program or one of the
cess channels for multiple access communication. In
optional Automatic Data Channel Controllers. Each
the typical configuration shown in Figure 1-2, the
first channel of each bank is connected to a bus from
external devices. The system interface includes an
the processor. Another separate bus ties together
I/O bus system that is directly addressable, as well
the second channel of each bank. This bus is con-
as provision for status control lines, function control
channel has the capability of controlling up to fifteen
nected to each optional Automatic Data Channel Con-
lines, and external interrupt lines; as required for
troller used. The banks' third and fourth channels
the integration of hybrid or other systems with the
are available for bus connection to external proces-
8400.
sors and mass memory devices. With this arrangement, the banks can be accessed in an over lapped
Two additional units, the Automatic Data Channel
fashion by the central processor and by the external
Controller and the console, are shown separately in
processors in an expanded multiprocessor system.
the diagram. The first of these, an optional expan-
Each bank can also exchange information with external mass memory devices for efficient time-sharing
sion in the exchange, provides data channel control
for data transfer (independent of processor opera-
processes. With this configuration, the processors
tion) between external devices and memory. The
may continue computation during input/output activity.
console, which is considered as part of the processor, includes: system controls, register displays,
The central processor, functioning as the heart of the
an on-line typewriter and a paper tape station.
system, has two-way communication with all subsystems and optional Automatic Data Channel Control-
1. 2
EXPANSIONS
lers. Provided with a complete capability of performing all required arithmetic and logical operations,
One important aspect of the 8400 is the versatility of
it performs the major part in control and execution
configurations. The expansions may be factory in-
of the stored program. The achievement is accom-
stalled or added in the field when the 8400 users' re-
plished by an accumulator and an extensive comple-
quirements change. A complete listing of expansions
ment of registers, control lineS, and logic circuitry.
may be found in Section 1. 1 of the 8400 Maintenance
Series - System Information manual (EAI Publication Number 00 800 9002-0). This section provides
In general, the basic items of this subsystem are:
logic signal control, status lines, function lines, in-
1-1
Figure 1-1. Typical 8400 Scientific Computing Sys tern
1-2
FUNCTION LINES
STATUS LINES
INTERRUPT
II II
~r45678
I
I
CHANNEL CONTROLLERS
DISC- PAC
CONTROLLER
MEMORY
BANK
MEMORY
BANK
MAGNETIC
TAPE
CONTROLLER
MASS
STORAGE
PROCESSOR
MEMORY
BANK
8930
Figure 1-2. 8400 System Diagrams
a brief outline of the basic systems (8402, 8403)
Three high-speed index registers and four in-
along with the standard and optional components
dex registers in coret;
available.
Figure 1-2 illustrates the various configu-
rations.
1. 2. 1 8402 Basic Computing System - Includes
the following:
Masked priority interrupt system with 16 internal. and 16 external. levels;
Power fail-safe system;
8410 Floating Point Processor;
8420 Memory Module - 8K capacity;
8430 Exchange Module;
8440 Desk Console;
Exchange module (8430) with one (8431) data
channel, one (8440) desk console with on-line
input-output typewriter and one (8490) power
system;
8490 Power Module.
Indirect, immediate and byte addressing capa-
1. 2. 2 8403 Basic Computing System - Same
as the 8402 System except that the memory module
bility; and, SAVE register with 560 nanosecond
cycle time.
has a 16K storage capacity.
t Four, high-speed index registers referred to as
1. 2. 3 8410 Central. Processor - Including:
Hardware for performing fixed and floating
pOint arithmetic;
the Quad Index Register Pak may be optionally deleted. However, the system always has seven index
registers. After the deletion is made, the system
index registers include the accumulator, two highspeed registers and four registers in core memory.
1-3
Masked priority interrupt system with 16
internal and 16 external levels; and
An availability for four channel interrupt lines
Power fail-safe system tied to the highest
A systems interface with up to 16, fully-buffered,
interrupt level.
16-bit parallel input/output busses - up to 128
when less than five 8431 data channels are used;
groups of status lines with 8 lines per group -
1. 2. 4 8420 Memory Module - Includes:
Core storage capacity of 8192 words, each containing 32 bits for information, 2 EXEC bits
for special control functions and 2 parity bits;
A 650 nanosecond access time;
A 1. 75 microsecond cycle time;
and up to 128 groups of function lines with 8
lines per group; and,
Interface terminations for optional external
priority interrupt system expansions, for up to
256 interrupt levels.
1. 2.6 8440 Desk Console - Including:
Independent read/write control enabling over-
Operator's panel with complete display and
lapped operations with other memory banks;
control facilities including console, status line
and,
control and processor access for on-line parameter changing;
The capability for handling independent busses
from up to four request sources.
A maintenance panel;
Maximum one unit to be added in field.
An on-line, Selectric Typewriter for manual and
program -controlled input/output.
1. 2.5 8430 Exchange Module - Includes:
1. 2. 7 8490 Power Module - Including:
A channel control system that can accommodate up to eight 8431 data channels;
A capability for providing the 8400 system's
full power requirements;
Two bi -directional buffered data channels each
Provisions for the manual, marginal testing of
capable of handling 16-bit parallel communication;
memory;
The capability for handling 15 device control-
Provisions for power-fail monitoring; and,
lers per channel;
Provision for over/under power protection.
The capability for controlling 16, 8 and 4-bit
byte assembly or disassembly sequences, including parity checking or generation as well
1. 2. 8 The follOWing list includes optional peripheral devices and system expansion components:
as conversion of BCD to processor collating
codes;
8441 Paper Tape Station - with a 500 cps read
and 110 cps punch capability.
(cps = Char/sec).
The capability for independent channel control
1-4
from the processor or from the optional, 8435-1
8412 Quad Index Register Pak - adds to the
Automatic Data Channel Control System (per-
processor four high-speed index registers
mitting simultaneous multi-channel operation);
(registers 4 to 7).
8417 Timer Register - provides addressable,
8439-1 through 128 Function Line Package -
real-time millisecond clock.
provides in the exchange additional function
8422 8K Memory Bank - with same features as
8422-E Memory Module.
(Maximum four banks
groups of 8 lines each (two 8-line groups per
unit). Each package provides fully buffered
flip-flop storage for function line output to ex-
per 8400.)
ternal devices.
(Maximun 64 groups.)
8423 16K Memory Bank - with a 16,384 word,
core storage capacity; other features are the
8441 Paper Tape Station - 500 character-per-
same as those for the 8420 Memory Module.
second read and 110 character-per-second
(Maximum four banks per 8400. )
punch. Mounting provisions are included in the
8431 Program Control Data Channel - provides
a data channel capability for any exchange
module channel position, from 1 to 7; handles
up to 15 peripheral device controllers.
8440 Central Console.
8452 Card Reader - 400 cards-per-minute; 12
row cards, 80 column read.
8435-1 Automatic Data Channel Processor -
8453 Card Reader - 800 cards-per-minute; 12
provides independent block data transfer con-
row cards, 80 column read.
trol for the 8431 data channel of channel position 0 in the exchange module; requires the use
of an 8420 Memory Interface Pak; independent
8454 Card Reader - 1400 cards-per-minute;
12 row cards, 80 column read.
of central llrocessor.
8455 Serial Card Punch - 100 cards-per -minute
8435-2, 3, 4 Automatic Data Channel Processor Expansions - each adds independent block
data transfer control for one 8431 data channel
occupying any channel position between 1 and 7
in the exchange module; 8435-1 Automatic Data
Channel is required in order to use the expansion.
(Maximum of three. )
to 316 cpm.
8456 Parallel Card Punch· 300 cards-per-
minute.
8461 Line Printer - 300 lines-per-minute; 132
columns-per-line, 64 characters, buffered
8420-21,22,23,24 Memory Interface Pak -
printer.
provides coupling interface between 8435-1
Automatic Data Channel Processor and Memory
8462 Line Printer - 600 lines-per-minute; 132
Banks 1, 2, 3, anli 4, respectively.
columns-per-line, 64 characters, buffered
Maximum
of four; one required per memory bank. Neces-
printer.
sary if an ADCP is to be used.
8463 Line Printer - 1000 lines-per-minute.
8437-2 through 16 External Interrupt System
Expansion Group - each group adds 16 inter-
8472 Magnetic Tape System - provides con-
rupt lines to basic external interrupt system.
troller handlin up to four transports (8473);
8438-1 through 128 Status Line Package - pro-
vides in the exchange additional status line
groups of 8 lines each (two 8-line groups per
unit). Each package provides fully buffered
one is included, maximum of four.
The
tape transport uses 7 -track, IBM compatible
tapes and operates at 45 ips and 556 and 800
bpi, respectively.
flip-flop storage for sense input from external
8474 Magnetic Tape System - provides con-
devices .. (Maximum 64 groups.)
troller handling up to four transports (8475);
1-5
one is included (maximum of four). The tape
8481 Display Monitor - provides point, line
transport uses 7 -track, IBM compatible tapes
and character plotting on a 10" x 10" display
and operates at 75 ips and 556 and 800 bpi,
of 1024 points along each axis. Light pen is
respectively.
included.
8476 Magnetic Tape System - provides con-
1. 3 PROCESSOR
troller handling up to four transports (8477);
one is included. The tape transport uses 7-
1. 3.1 Memory Word
track, IBM compatible tapes and operates at
120 ips and 556 and 800 bpi, respectively.
The 8400 Computer's memory word 'consists of 36
8478 Magnetic Tape System - provides con-
bits: 2 bits for parity check, 2 bits for program
troller handling up to four transports (8479);
control (EXEC bits), and 32 data bits. The memory
one is included. The tape transport (8479)
word format is shown in Figure 1-3.
uses 7-track, IBM compatible tapes and operates at 150 ips and 556 and 800 bpi, respec-
The parity bits are generated and stored on a half-
tively.
word basis during the write cycle. Parity is then
NDTE
checked during the read cycle. If an error is lo-
Model Numbers 8472-9, 8474-9, 8476-9, and
cated, the console indicator lights and a parity inter8478-9 are the same as the models listed above
rupt J!3 initiated. The 8400 System uses odd parity;
except that they use 9 track IBM compatible tapes.
this means that whenever the number of logic ONE's
31 32 33 3435
151 16
INFORMATION
0
16-BIT HALF-WORD
I
16-BIT HALF-WORD
E E
P P
,
32-BIT FULL -WORD
8-BIT BYTES
I·
4-BIT BYTES
SUBDIVISION OF HALF-WORDS
FOR BOOLEAN OPERATIONS
I I I I II I I I
H,T BYTES
11111111111111111,·"
T BYTES
Figure 1-3. Memory Word Format
1-6
making up a word is even, a parity bit is generated
indicates the normal program control capabilities of
so that the result is odd. (Using odd parity, the
the instruction word; for example, addressing, ad-
parity bit is always the opposite when all l's or O's
dress modification, and instruction interpretation.
are used.)
The first sixteen bits (M field) in the word format
represent the operand address during a data fetch.
The EXEC bits, in effect, expand the system's soft-
It may also signify: an instruction address during
ware capability. Used by the programmer to tag
an instruction fetch, an immediate operand, or a
selected memory words, these two bits are also
shift count. The next four bits designate any address
capable of the following:
modification required. If bit 16 (*) is a binary 1,
the M field contains the address of another location
enabling interrupt control for memory
protection,
in memory that will replace the present M field,
rather than the address of an operand. Bits 17 through
19 (X, where X = 1 to 7) specify the number of an
dynamic relocation of object programs,
Index register. Either or both may be used to change
the interpretation of the instruction address during
. .. stack or table pOinting, and so forth.
execution.
The last 12-bit (OP field) portion of the word format
EXEC bit control is discussed in Chapter 2.
denotes the operation to be performed.
The information portion of the word may contain a
full (32-bit) word, two half (16-bit) words, or por-
1. 3. 3 Data Word Formats
tions thereof (8, 4, 2, or 1-bit) for Boolean
operations.
This section describes the word formats used in the
8400 Computer. The brief descriptions refer to
Figure 1-5. Arithmetic formats are in a two's
complement notation with the + sign (binary 1) indicating a negative quantity. The instruction, memory
data and memory address word formats are included
in Figure 1-5 for comparison.
1. 3. 2 Instruction Word
Instructions are executed in sequence by the 8400
Instruction Register (I). Each instruction has a 32-bit
word format as shown in Figure 1-4. This figure
0
15
M FIELD
M
16
*
17
19
X
31
OP FIELD
16 - BIT (MEMORY) ADDRESS FIELD
*
I - BIT INDIRECT ADDRESS MODIFIER
X
3 - BIT INDEXING MODIFIER
OP
20
12 - BIT COMMAND (OPERATION CODE)
Figure 1-4. Instruction Word Format
1-7
CHARACTERISTIC
FLOATING POI NT
S
DOUBLE PRECISION
FLOATING POINT
sl
{
EXPONENT
I
lSi
23
MOST SIGNIFICANT CHARACTERISTIC
7
24EXPONENT
lsi
23
LEAST SIGNIFICANT CHARACTERISTIC
7
EXPONENT - 23
INTEGER
sl
~s...I_____
FIXED POINT
I
~s IL...------1_5------~1
,
I
=:J
-- ,-1----'....1I
~
Isl==7
1_5_ _ _ _ _---', _ _ _ _ _ -1-1 _ _ _ _
....
I
EXTENDED FIXED POINT S
I I
15
INDEX
IS I
15
LOGICAL: I, 16-BIT BYTE
I
S
I
15
I~------------------~------------------~
I~-----'
2, a-BIT
I~----------------~
BYTESI~_ _ _ _ _ _"'--_ _ _ _ _ _~
4, 4-BIT BYTESI
I~-~--~--~-~
16, 1- BIT BYTES
1
I
I I 1 1.1 I 1 I 1 1 1 I 1
6
INSTRUCTION
17 19
OPERATION
M FI ELD
MEMORY ADDRESS
MEMORY DATA
BIT SCALE
RIGHT HALF
LEFT HALF
I 7 II
a
ItlMrl~1
16
EL - LEFT EXEC BIT
ER - RIGHT EXEC BIT
PL - LEFT PARITY BIT
PR - RIGHT PARITY BIT
S" SIGN:!:
Figure 1-5. Summary of 8400 Word Format
1-8
1. 3. 3.1 Floating-Point. Floating-point num-
1. 3. 3. 2 Fixed-Point.
Formats for the stan-
bers are either single word (32-bit), or double pre-
dard (16-bit) and extended (32-bit) fixed-point quan-
cision (56-bit) quantities. The single-precision
tities are illustrated in Figure 1-5. The standard
floating-point number consists of:
fixed-point format consists of a 15-bit fraction along
.'
with a sign bit and may occupy either half-word
•.. a fractional part (23 magnitude bits),
position of the memory word. The extended fixedpoint format contains two 15-bit fractional parts
a sign bit,
and a sign bit for each. Its left half-word contains
the fifteen most significant bits and the sign of the
and an exponent part ( 7 magnitude bits)
with its own sign bit.
entire 30-bit fractional quantities, In standard
fixed-pOint arithmetic operations, the half-words
This single-precision floating-point notation provides
are addressed individually.
an accuracy of six.decimal digits.
1. 3. 3. 3 Integer.
The double-precision floating-point number occupies
Integer arithmetic instruc-
tion involve operations with two types of data words:
two consecutive memory word locations .. The word
with the lowest address contains the most significant
1. Standard, 16-bit fixed-point
and
fraction and exponent bits. The signed exponent part
of the word (eight bits) with the higher address is
. .
adJusted durmg memory store to EXP-2
23
2. Single, 32-bit floating-point.
. Double
floating-point notation provides an accuracy of thirteen decimal digits.
The data word associated with the system memory is
standard, 16-bit, fixed-point notation. The operand
in the Accumulator is in single 32-bit, floating-point
The double-precision floating-point word format has
direct correspondence with the single floating-point
format.
For example, when executing a 32-bit
floating-point multiply, the product will be in the
double-precision word format. Therefore, the results of several 32-bit floating-point multiply operations can be accumulated using double-precision
floating-point add operations. The results may be
operated on individually since the sign and exponent
for each of the most significant and least significant
portions are preserved.
notation. In the integer mode, a 16-bit, fixed-point
number is automatically converted from the halfword memory location to the floating-point format.
LikeWise, a floating-point number in the accumulator which represents the result of a series of
floating-point operations, is integerized and stored
in the designated half-word memory location. Operations in this mode may be either normalized or unnormalized by post modifying the associated instructions.
1. 3.3. 4 Index. In this operation, the contents
.of a specified index register is arithmetically combined
Floating-point operations are normalized (adjustment
with the contents of a half-word memory location.
of the mantissa and floating-point number so that the
The result, obtained in the accumulator, is automati-
mantissa lies in the prescribed normal range) auto-
cally transferred back into the specific index regi-
matically after each operation unless the instruction
ster and the previous contents of the accumulator ar!
is post-modified by the unnormalized symbol (U).
restored.
Normalization is accomplished by using left shifts
to remove all leading zeros from the number in the
1. 3. 3.5 Logical Byte. Logical Byte operations
accumulator. The shifting continues until the con-
between half-word memory locations and the accumu-
tents of the first two bit positions (0, 1) in the accu-
lator may be performed in 16, 8, 4, 2, or 1-bit bytes.
mulator differ.
A single instruction selects the desired byte size,
1-9
byte positions, logical connective and recipient (either
The first section, the 16-bit A Register, is used by
memory or accumulator) of the operation results.
itself for 16-bit fixed-point operations and as the
most significant 16 bits of all other operations. The
1. 3. 4 Processor Registers
second section, the AE Register, is used when ex-
The following registers in the 8400 Computer provide
tended fixed-point and extended shift operations are
needed. It enables the A Register to Handle 32-bit
the major portion of the Processor's capability for
fixed-point quantities such as: 32-bit, double-length
control and execution of the stored program. (See
products; and dividends of standard, 16-bit fixed-
Figure 1-6).
point multiply and divide operations. The AF Register, the third section, is a 16-bit A Register exten-
1.3.4.1 Instruction Register (l). This 32-bit
register stores each instruction as it is executed.
sion and is used for single-word (32 -bit) floating-
The register format is the same as the 8400 instruc-
point quantities. The final section, the AD Register,
provides a 24-bit extension to the AF Register. This
tion word as shown in Figure 1-4.
enables the accumulator to handle 56-bit, double1. 3. 4.2 Location Counter (L). This 16-bit
precision floating-point quantities; such as the double-
register contains the address of the next instruction
precision products and dividends of a single-word
to be loaded into the Instruction Register. Its primary
floating-point multiplication and division operations.
function is to provide system program control by sequentially directing the flow of instructions into the
The accumulator provides several special 8400 pro-
system. The contents of the Location Counter may
gramming features. It provides a single refere.nce
be stored when necessary.
location for the implicit operand and the result of all
arithmetic and logical operations. The accumulator
1. 3. 4. 3 Universal Accumulator (A).
The
is universal in that it automatically handles all inter-
Universal Accumulator as shown in Figure 1-7, con-
register transfers after each arithmetic operation.
sists of four separate registers which carry out the
Another convenience is that it may be used as an index
8400's arithmetic and data operations.
register. Finally, by virtue of its self-addressing
o
I
16
INSTRUCTION REGISTER ( r
LOCATION COUNTER (L
FLAG REGISTER ( F
I
1
15
o
32
I
INDEX REGISTERS
(X I _7) .. ·(SEVEN)*
1
1
UNIVERSAL ACCUMULATOR (A)
~
16
i
32
151--A~REG~ER--=-=:]
o
INTERNAL
MASK REGISTER (Ml
, - - - - - - - tL----_ _ _ _ _ _ _ -,
EXTERNAL
MASK REGISTER (El
0
L
A REGISTER
__
______
AF REGISTER
, - - - - - - - - - - - ---,23
INTERNAL
INTERRUPT REGISTER
L
_ _ _ _ ~D~E~~.:mR
SAVE REGISTER ($ I
INTERVAL
TIMER REGISTER (Tl
___ ~
~
EXTERNAL
INTERRUPT REGISTERS
CONSOLE REGISTER (C
L-------~
o
f
,--------,
.6
15
'-~REGI-;:;:-E_;_---I-
1
32
A E REGISTER
_ _ _ _ _ _ ---1
L- _ _ _ _ _ _ --j _ _ _ _ _ _ --,
L_~~GIST~ _ _ ..J
, - - - - - - - - - - - l23
0
L
_ _ _ ~D~~S~R_ _ _ _ ..J
'The A Register of the Uni versal Accumulator is Index Register Xl
Figure 1-6. Processor Registers
1-10
16
31
17
s I
0
I
15
r~-----------------AE REGISTER
I
MANTISSA (CONTINUED IN AF REGISTER)
..J .!..M~T.!!'!.N ~I ~~ ~R!..W!!E!! ~E~ W..!.T~ ~ ~G~T~R
~S
A REGISTER
31
23 "24
16
(CONTINUATION
_ _ _ O!,. ~N~'~A:' _
I
-1 ___ E~P~~T
____
AF REGISTER
MANTISSA (LEAST SIGNIFICANT PART)
- - - - - - - - -AD REGISTER
-
-
- - -
- - - - - -
-
Figure 1-7. Universal Accumulator Formats
capability, the accumulator enables the performance
When indexed address modification is specified, the
of doubling and squaring at high speeds. This selfaddressing capability also enables data transfer be-
effective address is formed by adding the contents of
the selected index register to the contents of the M
tween the accumulator and all index registers. The
field. This operation has no effect on index register
Universal Accumulator is addressable as memory
content.
location zero.
1. 3. 4.4 Save Register ($). The Save Register
Index arithmetic instructions allow direct operation
is a high-speed storage register similar to the
Universal Accumulator. (See Figures 1-6 and 1-7.)
between the respective contents of a specified index
This register is used to retain the entire contents of
single instruction effects the following: An automatic
the accumulator prior to the execution of any arithmetic or shift instruction. The Save option is de-
parallel transfer of the contents of the addressed
signated by the & symbol and may be used with any
arithmetic operation, as specified, combining this
'arithmetic or shift operation.
quantity with that contained in the addressed memory
register and an addressed memory location. A
index register to the Universal Accumulator; an
location; and, an automatic transfer of the result
The programmer, by using the Save Register, is able
back to the same index register. The transfer from
to store or read operands in 560 nanoseconds, less
the index register is made to the parallel A Register
time than it takes using core memory. The data is
automatically arranged in the proper format when
of the Universal Accumulator with the previous A
recalled by the Universal Accumulator. Similar to
a memory cell, this register retains data until a
register has no extension (AE Register), its use is
restricted to operations giving a half-word (16-bit)
subsequent instruction containing the $ symbol stores
results.
Register contents being stored. Since the index
new data; the data is NOT destroyed during the savewrite cycle.
1. 3.4. 6 Flag Register (F). The addressable,
1.3.4.5 Index Register (X1 - 7). Seven index
registers including the Universal Accumulator (index
register one) provide automatic address modification.
These registers retain ha:lf-word numbers that are
expressed in two's complement notation.
16-bit Flag Register continually monitors machine
conditions as well as those specified by the programmer. At the end of each instruction, the status
of these conditions is indicated by the register's
sixteen flag bits.
1-11
1. 3. 4.8 Console Register (C).
Tested by a set of transfer operations, the flags pro-
This l6-bit
vide the basis for the 8400's extensive program-
register enables monitoring, data display and data
control capability. They signify modifications of the
input while the program is in progress. It may be
normal sequential control for the program. Basic
control instructions affected include the following:
loaded by the operator or by the program..
HJf
EXf
Lf
1. 3.. 4.9 Interval Timer Register (T). Enabled
HALT if flag f set and JUMP when
execute button depressed;
by the LOAD INTERVAL TIMER (LDT) instruction,
EXECUTE instruction at specified
this l6-bit register decrements one count each millisecond t providing computer real-time control. As
location if flag f set;
the register goes through zero, an interrupt is gen-
LINK to subroutine if flag f set;
erated and the register is reset to its maximum
value. At this point, unless reloaded by the interrupt
subroutine, the register continues to decrement as
LRf
LINK to subroutine if flag f set,
before.
RESET flag; JUMP if flag f set;
With all its bit positions occupied, the Interval Timer.
Jf
JUMP if flag f set;
Register will decrement through a maximum time
range of 65,
JRf
~36-l milliseconds{~2n)InterruPts may
\\n=o
JUMP if flag f set, RESET flag;
be programmed to occur at any selected' time interval
JSf
JTf
JUMP if flag f set, SET flag;
within this range. Consequently, the register is
JUMP if flag f set, TRIGGER flag.
extremely useful for: program synchronization,
periodic output of data, time-sharing programs or
The LINK and JUMP operations are conditional; they
consoles, periodic sense line testing, and many
other purposes.
depend upon the status of the flag tested. The setting,
resetting, or triggering (complementing) of the flag,
however, is unconditional.
1. 4 ADDRESSING
The Flag Register bits indicate the status of 16 inter-
The extensive addressing capability in the 8400
nal machine conditions. Eight of the bits serve as
Scientific Computing System facilitates the handling of
programmer console flags and are set by either con-
all normally encountered address manipulations in-
sole switches or the program. Internal machine
volving core memory locations. Direct, indexed, and
status conditions can be preserved at any particular
indirect addressing have been made available to the
time by storing the entire register contents in mem-
programmer •. In addition, an immediate or literal
ory. This enables the programmer to retrieve inter-
addressing capability provides programming flexi-
nal machine status after the occurrence of subsequent
bility for fast efficient processing.
interrupt conditions.
1. 4. 1 Direct Addressing
1. 3. 4.7 Mask Registers, Internal (M) and
External (E). The Internal Mask Register and External Mask Register permit the programmer to select
the interrupts a program will respond to and, to establish a priority- among these interrupts. These
l6-bit registers are loaded and stored by the use .of
special instructions (see Chapter 2).
1-12
With direct addressing, the l6-bit address specified
by the instructions' M field referS' directly to the
memory location of the data (operand) that is to be
t Other factory-set timing intervals are also available.
used in the specified operation. In arithmetic opera-
where the address of the data may be found.
tions, either full-word or half -word operands may be
the address of the data is given indirectly.
Thus,
used. With full-word operands, the entire contents
of the specified memory location are involved. With
If both an index register and indirect addressing are
half-word operands, either the right or left half of
required by the programmer, the effective address
the full-word location is used. The half-word to be
is computed as previously discussed and then the in-
used is designated in the instruction by a / (slash)
direct address is computed.
.'
post modifier (see Chapter 2).
1. 4. 4 Immediate Addressing
For double precision arithmetic operations, the contents of both the specified memory location and the
The 16-bit address of an arithmetic or logical in-
next memory location (M + 1) are accessed. In
struction serves as the operand when immediate
Boolean operations, the specific half-word (including
addreSSing is used. This operand is a signed number
its byte size and position) is specified by using post
represented in two's complement notation. Immedi-
modifiers in the associated instruction, i. e. , AHM4/
ate addressing is specified in the 12-bit operation
SAM,,3. In this instruction: 4 specifies a four-bit
(OP) field of the instruction word and is accomplished
byte; SAM designates the memory location and, being
in symbolic notation by placing the = symbol in this
to the right of the slash, the right half-word of this
field.
full-word location is specified. The instruction
states, "where each of the four bits in the third byte
This form of addressing saves instruction time since
position are high, set the corresponding bits in the
it permits the direct use of data from the Instruction
right half-word of memory location SAM".
Register; no memory access required. This form
of addressing also saves memory space since no
1.4.2 IndexedAddressing
operand memory locations are required and; in ad-
Indexed addressing represents an important and
dition, the operand may be modified by the contents
highly useful variation of direct addressing. The
of a specifiC index register since the immediate
8400 contains seven index registers providing an
. efficient, flexible means of address modification.
operand is located in the instruction word address
field. With this modification accomplished prior 'to
using the immediate operand, the effective immediate
Indexing adds the contents of an index register to the
operand concept can be used by the programmer to
address portion of an instruction, Bits 17, 18, and
provide greater programming flexibility.
CA
store
19 of the instruction word specify which one of the
command with immediate addressing capability is
seven index registers is to be activated. If bit posi-
called an NOP.)
tions 17, 18, and 19 are zero, no indexing is specified. The contents of anyone of the computers'
The immediate operand notion extends to shifting
seven index registers are added to the 16-bit address
operations as well. In a SHIFT instruction, the
field (base part) to form the "effective address".
desired number of shifts is speCified as an arithmetic operand. Direction of shifting is determined by
the shift count sign. And, as an immediate operand,
this shift count may be modified by the contents of a
1. 4. 3 Indirect Addressing
Multi-level indirect addressing may· be used without
being restricted by any 8400 instructions. The
* bit
specified index register.
1. 5 INTERRUPT SYSTEM
(bit 16) of the instruction word is used as the indirect indicator. When indirect addressing is speci-
The true multilevel interrupt system with mask con-
fied' the 16-bit address gives the memory location
trol permits multilevel interruption to any depth
1-13
without a loss of return-continuity. When an internal
has priority over the succeeding group and each
or external interrupt condition occurs and the inter-
group level over lower levels.
rupt action is not inhibited by masks, an instruction
in a reversed interrupt location is executed (each
Basically, 16 flip-flops (each set by a particular
interrupt condition has a reversed location). The
execution of this instruction does not change Location
Counter contents. LINK, the normally executed
interrupt condition) are scanned. A scanner will
accept a flip-flop output only if the Interrupt Enable
bit in the Flag Register and the corresponding mask
instruction, transfers control to the interrupt routine
register bit are both high. The scanner begins scan-
while preserving the return address of the interrupted
ning at selected points in the instruction flow, con-
program. Once started, an interrupt action may be
tinues until an interrupt condition is detected, and
interrupted by the occurrence of a subsequent sys-
then locks onto that position. The priority of a
tem interrupt condition.
scanner is established when no "higher-priority"
scanner has locked up. Mter priority has been
The interrupt system responds to internal conditions
established, interrupt logic determines the address
of the reserved interrupt location.
and operating modes monitored by sixteen internal
interrupt lines. It is also responsive to any of up to
256 external conditions monitored by an expanded
Mter an interrupt subroutine has been given control
complement of external interrupt lines. There are
and the return address of the interrupted program
16 external interrupt lines in the first group with a
has been saved, scanning of the higher priority inter-
capability of up to 15 additional external groups. The
rupt levels resume. This insures that the operation
complete system is arranged in 17 groups containing
of the subroutine will be interrupted only when the
16 individual interrupt levels apiece. Group 0 in-
higher interrupt conditions are detected. Such in-
cludes the internal interrupt levels and groups 1
through 16, the external interrupt levels. Each group
terruption may be eliminated by using the appropriate masking.
1-14
CHAPTER 2
INSTRUCTION REPERTOIRE
2. 1 INTRODUCTION
This chapter contains a complete and precise definition of the operations performed by every 8400
instruction. Further details on input/output in-
.•• the instruction address field in the left
portion of the instruction word;
••• other special registers are a half-word in
size.
structions for peripheral devices are given in
Chapter 4. The emphasis in this chapter is on pro-
2.2 EFFECTIVE ADDRESS CALCULATIONS
gramming rules and conventions; moreover, as an
aid in learning the entire repertoire, the instruc-
2. 2. 1 Direct Addressing
tions are presented in classes and sets. The programming conventions and notation used are taken
from the 8400 Macro-Assembler manual (EAI
All instructions referencing an operand in memory
Publication Number 07 800.0001-3). The actualOP
The most basiC, direct addreSSing, uses the 16-bit
code numerical values are given in the appendix and
left hand number of the instruction word as the
in the 8400 Programmer's Card.
operand address. Other addressing modes are
specify one of several ways to address the operand.
termed: index modification, indirect addressing,
Consistent with the objective of presenting the instruction repertoire as the programmer will use it,
the view of the computer is offered as functional appropriate for the programmer. Therefore, Figure
2.1 illustrates the essential programmable elements
of the central processor. Only the 16-bit input and
output busses are missing. The registers required
and immediate addressing. Half-word addreSSing, a
variation on each of the above, is allowed when the
operand is a 16-bit word. The left or right half-word
selection is made after a memory address. This
left/right option is an integral part of the OP code
(bits 20 to 31 of the I Register as shown in Figure
2.1).
for momentary storage of data traveling to the accumulator from the memory is only one explicit
inter-register transfer and that is between the ac-
2. 2. 2 Indexing
cumulator and the Save ($) Register. The memory-
One of the primary uses of index registers arises from
their ability to modify instruction addresses. For this
to-register transfer paths are obvious; therefore,
to occur, the instruction must specify the particular
not shown. Other register transfers which are
closely related to the instruction and their options
index register that is to take part in the modifying
are developed in the text below.
activity. Indexing adds the contents of an index register to the address portion of an instruction.
Figure 2.1 illustrates the following important facts:
When indeXing is speCified, the contents of the index
• •• The Save Register can hold a copy of the
accumulator contents except for the exec
bits (shown crosshatched);
· •• the EA and AF Registers are alternative
extensions of the A Register;
· •• the A Register is also treated as Index
Register one;
registers are added algebraically, in two's complement notation, to the address portion of the
instruction. This new address, the effective address,
is then to be used as the operand.
If the index register contains a negative (two's com-
plement) value, the result of address modification
to subtract this value from the address portion of the
! instruction.
2-1
INDEX REGISTERS
o
15
X7
X6
X5
X4
X3
X2
PROCESSOR REGISTER
o
T
c
REGISTER
E
M
F
L.
o
I.
I.
52
1__m_--1.JH_x.1. ._op_-,
I ....
M
o
EI
ORY
II
IE
8400 REGISTERS
Figure 2.1
As an example of address modification, assume that
memory address 500 contains the instruction AD 124,2
and this instruction has a two in the appropriate index
register position. If the contents of the index register are 27, then the number stored in memory location 151 (124 + 27 = 151) is added into the accumulator when the add AD instruction is executed. Note
that memory location 500 still contains the instruction
AD 124,2 in its original form. Memory address 151
is called the effective address, and the process is
called address modification; that is, the address of
the instruction is modified in the central processor
for execution purposes, but is unaltered in memory.
2.2.3 Indirect Addressing
When proceSSing data is located in several different
areas of memory, it is at times convenient to operate
upon an indirect address as opposed to an actual ad-
AD 123.
However, if he wishes to add to the accumulator, not
the contents of memory location 123 but the contents
of the contents of memory locat:i.on 123, then the computer would add the contents of location 1862 to the
accumulator. This procedure is known as indirect
addressing, and occurs when a 1 is placed in bit
position 16 (*) of the instruction word. Mnemonically,
it is written as:
AD* 123
Note that if an index register and indirect addressing
are requested by the programmer, the effective address is computed as previously discussed and then
the indirect address is computed.
2.2.4 Summary
Table 2.1 lists the entire 8400 Instruction Repertoire.
dress. For example, if the programmer wishes to
perform an add instruction at memory location 3000
An instruction that has a number (m) in the left half-
(assume that memory location 123 already contains
is said to address memory core location, m, which
1862), he would write location 3000
contains the operand. If the Immediate option is
2-2
word and no address modifier in the right half-word
Table 2.1. 8400 Instruction Repertoire
8400 INSTRUCTION LIST
ARITHMETIC OPERATIONS
32·BIT FLOA TING.POINT
Subtract
Cleor Subtract
Cleor Add
Add
Com pore
Multiply
Store
Store Rounded
Divide
Clear Divide
56·BIT DOUBLE FLOATING.POINT
MNEMONIC
FSB
FCS
FCA
FAD
FCP
FMP
FST
FSR
FDV
FCD
MNEMONIC
Subtract
Clear Subtract
Clear Add
Add
Compar.
Multiply
Store
Store Rounded
Divide
Clear Divide
32·BIT EXTENDED FIXen.POINT
Subtract
C lear Subtract
C lear Add
DeS
DCA
Subtract
Clear Subtract
Cleor Add
Add
DAD
Add
Comparet
Multiply
l'
DSB
16·BIT FIXED POINT
DCP
Compore t
DMP
MultlplYf
Store
Stor. Rounded t
Store
Store Round"cI t
OST
DSR
Divide t
DOV
Clear Divide t
OeD
t denotes compatible subroutine operat;ons
16·BIT INTEGER
Subtract
Clear Subtract
Cleor Add
Add
Compare
Multiply
Store
Stor. Rounded
Divide
Clear Divide
MNEMONIC
ISB
ICS
ICA
lAD
ICP
IMP
1ST
ISR
IDV
ICD
Operation modifiers extend the basic list. The post
modifier "U" specifies unnormaHzed operation for
F,D and f Classes. The premodifier "$" specifies
a Scive Register store of the accumulator contents
prior to the execution of a modified instruction of
any class. Examples: FADUi SEAD or $FADU.
Divide t
Clear Divide t
MNEMONIC
SB
CS
CA
AD
CP
MP
ST
SR
DV
CD
MNEMONIC
ESB
ECS
ECA
EAD
ECP
EMP
EST
ESR
EDV
ECD
16·BIT INDEX
MNEMONIC
Subtract
C lear Subtract
Cleaf Add
XSB
XCS
XCA
XAD
XCP
XMP
XST
XSR
XDV
XCD
Add
Compare
Multiply
Store
Store Rounded
Divide
Clear Divide
The prefixes or suHixes in the mnemonic symbol
denote the class of operation or operation conditions. The basic symbol indicates t"'e operation
itself.
ElI:ample: In FAD, F stands for Floating.Point
Arithmetic (32·bit precision).
AD indicates
the ADO operation.
SHIFTING, ROTATION AND NORMALIZING OPERATIONS
ACCUMULATOR
Arithmetic Shift
Logical Rotate
Normalize
MNEMONIC
ASH
ROT
NRM
EXTENDED ACCUMULA TOR
Arit"'metic Shift
Logical Rotate
Normalize
MNEMONIC
EASH
EROT
ENRM
Set (A 11 Ones in A)
Reset (Ail Zeros in A)
Memory High (Load M)
Accumulator Low (Complement A)
Memory Low (Complement M)
Bot'" Hig'" (And)
Either High (Or)
Either Low (Nand)
BLAn
BDAn
BSAn
CSHAn
CEHAn
CELAn
CBLAn
BECTn
Example: ELAn specifies that the result of a NAND, with on n.. bit
byte in A and an n.blt byte in M, replace the A.byte. T"'e mnemonic:
is interprered as follows: "For corresponding bit positions in t"'e
Both Low (Nor)
Both Different (Exel Or)
Both Same (Equiv)
Complement Both High (And A)
Complement Either High (Or 'A'>
Complement -Either Low (Nand A)
Complement Both Low (Nor A)
Memory High (Set Z Flag if Byt. in M is Zero)
BLMn
BDMn
BSMn
CBHMn
CEHMn
CELMn
CBLMn
MHMn
A·byte and the _~byte,where EITHER the A.bit or the M.. bit is LOW.
set resultant A.bit. n= 1,2,4,8 or 16 bits.
CONTROL OPERATIONS
TEST BRANCH _ ON "FLAG". I
Holt - Jump
Execut.
Link (To Subroutine)
Link _ Res.t Flag
Jump _ Trigg.r Flag
Jump - Set Flog
Jump _ Reset Flag
Jump
MNEMONIC
HJI
EXI
LI
LRI
JTI
JSI
JRI
JI
MNEMONIC
INDEX JUMPS
XJ
Index Jump - Unconditional
Index Jump Test
XJT
EXEC BIT CONTROL
MNEMONIC
SEX
REX
Set EXEC Bit
Reset EXEC Bft
Test EXEC Bit
TEX
f denotes one of the 16 conditions monitored by a special flag
register. T"'ese conditions are listed below with their respective
mnemonics. Complement conditions can be specffied by prefixing
the condition mnemonics with the modifier, tiN".
Accumulator Equals Zero
Accumulator Greoter than Zero
Accumulator Less than Zero
Overflow (Cumulative)
Examples: Halt Jump on Over·
flow Is coded HJV. Holt Jump on no Overflow Is HJNV.
Unconditionally True
blank
Z
G
L
Carty (Or Borrow)
Busy Data Channel
Enabled Interrupt
C
B
E
V
Progrommer Flags
1·8
1/0 OPERATIONS
1/0 REGISTER LOAD
MNEMONIC
Load Output BU55
Load Channel Dota Register
Load Channel Control Register
LDOS
LOCD
Set Function Line
AUTOMATIC DATA CHANNEL CONTROL _
DATA BLOCK TRANSMISSION
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
on Count _ Disconnect
Until Signal _ Disconnect
on Either _ Disconnect
on Count _ Interrupt
Until Signal _ Interrupt
on Either _ Interrupt
I/O REGISTER STORE
MNEMONIC
LDCC
Store Input Buss
Storoe Channel Doto Register
Store Channel Control Register
STiB
SlCD
STCC
SFL
Test Stotus Line
TSL
MNEMONIC
TCD
TSD
TED
TCI
TSI
TEl
AUTOMATIC DATA CHANNEL CONTROL _
NO DATA BLOCK TRANSMISSION
Skip
Skip
Skip
Skip
Skip
Skip
on Count _ Disconnect
Until Signal _ Disconnect
on Either _ Disconnect
on Count _ Interrupt
Until Signol _ Interrupt
on Either _ Interrupt
MNEMONIC
SCD
SSO
SED
SCI
SSI
SEI
SPECIAL REGISTER TRANSFER OPERATIONS
LOGICAL BYTE OPERATIONS
BOOLEAN CONNECTIVES _
RESUL TS TO ACCUMULATOR
Both Low (Nor)
Both Different (Excl Or)
Both Same (Equiv)
Complement Both High (And A)
Complement Either High (Or A)
Complement Either Low (Nand A)
Complement Both Low (Nor A)
Byte Equality Test (Set Z Flag if Bytes identical)
MNEMONIC
SAn
RAn
MHAn
ALAn
MLAn
BHAn
EHAn
ELAn
BOOLEAN COt.NECTIVES _
RESULTS TO MEMORY
Set (All Ones in M)
Reset (All Zeros in M)
Accumulator High (Store A)
Accumulator Low (Complement A)
Memory Low (Complement M)
Both High (And)
Either High (Or)
Eit"'er Low (Nand)
MNEMONIC
SMn
RMn
AHMn
ALMn
MLMn
BHMn
EHMn
ELMn
REGISTER TRANSFER _ LOAD
Load A -Extended
Load Flag Register
Loai Locotion Counter
Load Timer Register
Load Mask Register Internal
Load External Mask Register
Load Console Register
MNEMONIC
LDAE
LDF
LDL
LOT
LDM
LOE
LDC
REGISTER TRANSFER _ STORE
Store
Store
Store
Store
Store
Store
Store
A Extended
Flag Register
Location Counter
Timer Register
Mask Register Internal
Externol Mask Register
Console Regi ster
MNEMONIC
STAE
STF
STL
STT
STM
STE
STC
specified, the number (m) is "immediately" treated
as data (operand) rather than as an address. If the
takes place before indirect addressing (*), and the
final option is the half-word selection of immediate,
I
Indirect option is specified, core memory address m
left, or right (= and
contains the "address" of the operand rather than the
operand itself. If the Index option is specified, a
This sequence is illustrated in Figure 2.2. The notation in this figure is that parentheses around a regis-
number is taken from one of the seven index regis-
ter name specify the register contents; the arrow
cannot appear simultaneously).
ters and added to m to produce the effective address
reads as "replaces", and subscripts indicate specific
of the operand; while the left half contents (m) re-
register bits.
main the same. Several options may be used simultaneously as described in the following section. In
The flow diagram of Figure 2.2 is interpreted as
any case, the action of address modification is often
follows:
referred to as "effective address calculation". Since
this is a common occurrence and is possible with
1.
The instruction cycle starts with an
instruction fetch, which is denoted as
«L»-
regularly throughout for the contents of the effective
(I), or "The contents of the
memory address that is the contents of
address.
L replaces the contents of the instruction
the majority of instructions, the E notation is used
register, I".
2.2. 5 Combinations of Addressing Options
2.
The various address modifiers and the legal combi-
If indexing is speCified (by 1 to 7 in
bit positions 117, 18, 19) then the sum
nations thereof are shown in Table 2.2 in the format
of the number m in the instruction
used when writing instructions for the assembler.
address field and the contents of the
specified index register forms (tenta-
The precedence of the addressing options is: X, *,
=, or I. This means that index modification (X)
tively) the effective address E.
Table 2.2
Modifier
Name
Remarks
*
Indirect Address
OPN* M
The address for the given instruction is taken from the address portion of the 32-bit word at location M. Multiple
indirect addressing is possible. All instructions may use an
indirect address.
X
Address Modification
OPN M,x
The effective address is obtained by adding the contents of
the speCified index register, X, to the address, M. That is,
M + (X) - E .A. All instructions except the Index Register
Class can have address modification. Indexing precedes indirect addressing at every level if both are specified.
I
Halfword Address
OPN /M
The operand for 16-bit operations comes from the left half
of M by using MI and the right half of M by using 1M. The
slash (/) has no effect on indexing or indirect addressing. A
16-bit operation written OPN M is interpreted by the Assembler as OPN MI.
=
Immediate Address
OPN=M
The operand for this instruction is taken from the address
field of the instruction itself. The immediate address may
not be used with I. The immediate address is applicable to
all 16-bit operations except Store and Store After Rounding.
REMARKS:
All legal combinations of the address modifiers are illustrated below:
OPNMI
OPNM
OPN/M
2-4
Format
OPN M/ ,X
OPN 1M, X
OPN* M!
OPN* 1M
OPN* M/,x
OPN* IM,X
OPN=M
OPN = M,X
OPN* = M
OPN* = M,X
FETCH
INSTRUCTION
(( L
(1)
»....
I LLEGAL
I NSTRUCTION INTERRUPT
FETCH NEW
ADDRESS AND
MODIFIERS
(E.· 19 )- (1.'19)
rSAVE ACCUMULATOR
FETCH
OPERAND
(E)
EFFECTIVE
E-+ (D)
~(O)
ADDRESS
CALCULATION
Figure 2.2
3.
If indirect addressing is specified (by
by a manual halt or an interrupt. However,
116 = 1) then a new word, located at ad-
in the normal course, indirect references
dress E, is obtained from the memory.
can be made (at the expense of time for
each memory fetch) and indexing (for dif-
Only the first 19 bits of this word are used,
ferent index registers) can be performed
and they replace the contents of bit I o:19 '
Now, the original value m has been re-
at each level of indirectness.
placed in I by (E O:15 )$ and the index and
indirect bits have also been replaced.
Steps 1, 2, and 3 are repeated until for
some indirect address, indirect addressing
4.
With a new value for E, bits 125:26 in the
original instruction are tested for immediate addressing (half-word operands only).
is not specified. It is possible, through a
programming error, for the above loop to
If immediate is specified, the value of E
be a closed path, which "hangs-up" the
register (D) before the execution of the
computer. Such a loop can be broken only
accumulator instruction. Otherwise E is
itself is placed in the intermediate data
2-5
used as the effective memory address for
operand = E = (m) (16-bit
tOPN*=m
operand only)
the final gathering of data from the memory. After this gathering, the left/right
OPN*= m, X
option selects the specified half-word for
bit operand only)
execution.
5.
operand = E = (m + (X» (16-
Note that the Save option takes place just
after the immediate address test on either
2.3 ARITHMETIC INSTRUCTIONS
path.
There are ten basic arithmetic instructions that
The different effective address calculations
occur in each of six classes of operation. The
may be specified as follows, where OPN
classes differ in the form of arithmetic, word size,
signifies any operation code for which the
and the registers affected. The resultant sixty
address options are valid.
mnemonics and their functions are readily committed
OPNm
operand = (E0:15) or (E o:31 )'
E
= 00
to memory. There are numerous variations to these
basic instructions and they follow a consistent and
logical pattern. All arithmetic instructions may
exercise the Save option prior to execution; and they
OPNm/
operand = (E0:15)' E = 00
set Z, G, and L decision flags after execution. All
OPN/m
operand = (E 16:31)' E = 00
floatillg-point operations may terminate with an unnormalized result. All multiply and divide operations
OPN m, X
operand = (E0:15) or (E o:31 )'
require double length registers, hence the double
OPN /00, X
preCision instructions are executed by subroutines.
E=m+(X)
These mnemonics (and some others in the set of
sixty basic operations) are recognized by the assem-
operand = (E 16:31)' E = m+ (X)
bler and replaced by the appropriate Link instruction.
Alternatively, the actual codes for these instructions
tOPN*m
operand = (E o:15 ) or (E o:31 )'
E= (00)
are recognized by the computer and cause an interrupt
(number 2 interrupt). Software is provided to select
the right subroutine. All compare, store, and store-
tOPN*/m
operand = (E16:31)' E = (00)
rounded instructions leave the entire accumulator
unchanged. The add, subtract, and store-rounded
tOPN*m, X
operand = (E 0:15) or (E 0:31)'
conditions generally result in bit (C) of the flag
register being set. The carry flag (C) indicates that
E = (m + (X»
an arithmetic 'carry has been produced. Divide conditions can result in setting the overflow (V) flag
tOPN*/m, X
operand = (E 16:31)' E =
(see Paragraph 2.8.1).
(m + (X»
OPN=m
operand = E = 00 (16-bit
2.4 NOTATION
operand only)
The following shorthand notation is used throughOPN= 00, X
operand = E = 00 + (X) (16-bit
operand only)
out this text.
conventions.
t one level of indirect addressing assumed for illustrations.
2-6
Some are assembly language
2. 4. 1 Addressing Conventions
($A)
contents of the 16-bit A portion
of the Save Register
E
effective adQress
($AAE)
(E)
m
IE, 1m
E,
E/, m, ml
OP= m
OPm,X
contents of the Extended FixedPoint Save Register
contents of E
contents of address field of
instruction word
specifies right half-word for
16-bit operands
($AAF)
contents of the Floating-Point
Save Register
($AAFAD)
contents of the Double PreCision Save Register
speCifies left half-word for 16bit operands
immediate address, m is a
contents of bits 0 to 7 in A
Register
(AD
0, 9:23)
contents of bits 0 and 9 to 23 in
literal, a constant
the AD Register
indexing, X is an integer 1 to 7;
E = m + (X) except Index Class
the one's complement of the
contents of 0 to 7 of A
instructions
left Exec bit at effective
OP*m
indirect addressing, E
OP* m,X
indexing plus indirect,
E = (m + (X))
(Note: the
= (m)
address
right Exec bit at effective
address
* is part of the OP
field)
2.4.2 Register Conventions
Accumulator Exec bits
int( )
the integer part of the floatingpoint operand. Note that for
(A)
contents of the 16-bit A
two's complement numbers the
Register of the Accumulator
integer part is always the most
positive integer that is more
(AAE)
(AAF)
(AAFAD)
($)
negative than the number, hence
contents of the Extended FixedPoint Accumulator
for negative numbers the magnitude of the integer part is larger
than the magnitude of the
contents of the Floating-Point
Accumulator
contents of the Double Precision Accumulator
contents of the Save Register
number.
Jrac( )
the fractional part of the
floating-point operand:
I
I
frac(m) = (m) - int(m) is
always a positive fraction
2-7
fit( )
the 16-bit operand converted
Clear, Subtract
(floated) to a floating-point
CS
number
m,X
-(E)-(A)
(E 32)- (A 32 ) for m/
sgn( )-ZGL
the Zero, Greater than, Less
.fl- (AD l:S)
than flags are set according to
value of the operand relative to
Subtract
zero
SB
nrm( )
m,X
the normalized value of the
(A) - (E)- (A)
(E 32 )XOR(A 32 ) -
(A 32 ) for m/
floating-point operand
Compare
2.5 THE FIXED POINT INSTRUCTION CLASS
m,X sgn
CP
ZGL flags
(AO:15, 32, 33) unchanged
This is the most basic class of arithmetic instructions. No prefix is used before the basic mnemonics
[(A) - (E)] -
Store
of AD, SB, etc., as in the other classes. The
operand is always a 16-bit half-word. Two's com-
ST
m,X
plement binary arithmetic is performed. The state
(A)- (E)
(A 32 ) - (E 32 ) for m/
of the Z, G, L decision flags is determined by the
resultant value of (A), "zero", "greater than" or
Store, Rounded
"less than" zero after each operation (except CP as
noted below). The addressing options
*, /,
and X
are available for all instructions; and = is available
for all but ST and SR. The Save option, $, may
precede any of the mnemonics.
SR
m,X
MultiPly
MP
m,X
(AAE)
.fl - (AEo)
(AD) destroyed
Load
CA
(A)x(E) -
m,X
(E)-(A)
Divide
(E32)-(A 32 ) for m/
.fl-(AD 1 :S )
DV
m,X
(AAE) + (E) Remainder -
Example:
(A)
(AE)
(AD) destroyed
The above reads as follows: Line 1; The contents of
Clear, Divide
E (memory) replaces the contents of the A Register
of the accumulator.
Line 2; The left Exec bit at the
CD
m,X
.fl- (AE)
effective address replaces bit 32 of the A Register
(AAE) .;... (E) -
for a left half-word.
(AD) destroyed
Line 3; bits 1 through 8 of the
AD Register are replaced by
11.
(A)
2.5.1 The Save Register
Add
The sections of the accumulator are duplicated in the
AD
2-8
m,X
(A) + (E)- (A)
Save Register. When the save option is exerCised,
(E 32)XOR(A32)- (A 32 ) for m/
the entire contents of the accumulator (except Exec
bits) are saved: (A, AE, AF, AD) -
($A, $AE,
word sign bits. Therefore, the data word consists of
$AF, $AD) prior to execution of the instruction. The
sign plus 30 bits. The instructions, EMP, EDV,
Save Register is assigned memory address number
ECD, ECP, and ESR are not executed directly, but
one. The actual core memory cell number one is not
by programmed subroutines, since more than 32 bits
accessed by arithmetic instructions (except ST and
of register are required. The subroutines may be
SR), nor by Boolean connective instructions (except
entered in two ways. If the processor attempts to
M typej see Paragraph 2.4, Boolean Connective
execute one of these instruction codes, the number
Instructions). To gather data from the Save Register,
two interrupt occurs, and either the Monitor or the
the programmer writes either 1 or $ in the address
Compat routine (EAI Publication Number
field (the assembler translates $ to 1). Thus, CAl
07 825 0046-0, see Preliminary Bulletin Program
and CA $ result in ($A) -
Information 66026) takes control and selects the
(A). Since thE;l save
operation takes place first, $AD $ doubles the con-
proper subroutine. The more common method is for
tents of Aj $SB $ clears (A)j $MP $ squares (A)j
the Macro Assembler (EAI Publication Number
and $CS $ inverts the sign of (A). In each case, the
07 800.0001-3) to recognize the mnemonic code and
original contents of A is saved in $A. It is not possi-
substitute a Link instruction to the subroutine.
ble to store in the Save Register except by the $
prefix; ST 1 and SR 1 both store in core memory
The state of the Z, G, L decision flags is determined
location number one.
by the resultant value of (AAE) after each operation.
The addressing options
2.5.2 The Accumulator Address
In the same manner as above, the accumulator itself
is assigned memory address zero for arithmetic
instructions (which cannot access core memory location zero). This results in the following operations
with the fixed point instructions: CA ~ does not
change (A) but resets Z, G, L if, for example, CP
were the previous instructionj CS
~
inverts the sign
of {A)j MP ~ squares {A)j and CD ~ overflows. ST ~
does nothing and SR ~ rounds (A). The left/right
slash option is not available for addresses zero and
one: CA/1 and CA 1 are the same, as are SB /~ and
SB ¢. Neither (AE) nor ($AE) are affected by such
operations.
2.6 THE EXTENDED PRECISION INSTRUCTION
* and X are available with all
instructions in the class. The immediate option is
available (for all but EST and ESR) indirectly through
action of the Macro Assembler. The immediate option normally means that the address field of the
instruction is treated as a literal (a 16-bit data word).
However, since the extended class instructions
operate on whole words this is not possible. The
programmer may then use the = symbol to specify
a 32-bit literal. During the assembly process, the
literal value is placed in a special data storage area
called the Literal Pool and the instruction address
field is then given the data address.
The Save option may precede any of the mnemonics.
Load
CLASS
ECA
m,X
(E)- (AAE)
For each fixed-point instruction code and mnemonic
(AD) destroyed
there is a corresponding extended precision code and
mnemonic. The former operate on 16-bit half-words
and the latter on 32-bit whole words. All operations
Add
use fixed-point, two's complement, arithmetic.
Execution of the extended preCision instructions takes
EAD
m,X
(AAE) ~ (E) -
(AAE)
place in the AAE Register. The left half bits of the
two halves of this register,
A:o and AE o, are half-
(AD) destroyed
2-9
Clear, Subtract
to CA m. Note, however, that the X field of all of
the index class instructions is used to select the
ECS
m,X
-(E)_ (AAE)
register for action and not for address modification.
(AD) destroyed
This addressing option is not available for the index
instructions; while
* and /
are available for ali, and
the immediate option (=) is available for all but XST
Subtract
and XSR. An index register must be specified.
ESB
m,X
(AAE) - (E) (AAE)
(AD) destroyed
Since index registers are restricted in size to 16
bits, operations requiring whole word registers
Compare
(XMP, XDV, XCD, XSR) are performed by subroutines. Execution of the codes for these instruc-
ECP
tions results in the number two internal interrupt.
m,X
The Macro Assembler substitutes a Link instruction
for these mnemonics.
Store
EST
m,X
(AAE)- (E)
The state of the Z, G, L decision flags is determined
by the resultant value of the specified index register,
(X), or of the comparison (X)-(E). The Save option
Multiply
$, may precede any of these instructions; and (X) is
EMP
saved in the A portion of the Save Register, rather
m,X
than (A) being saved. However, in this case the rest
of the accumulator is saved, i.
Divide
e.,
$XCA m, 3 causes
(X3, AE, AF, AD) to replace ($A, $AE, $AF, $AD)
EDV
and the accumulator is unchanged.
m,X
Load
Clear, Divide
ECD
XCA
m,X
m,X
(E)_ (X)
then sgn(X)- ZGL
Store, Rounded
Add
ESR
m,X
XAD
m,~
(X) + (E)- (X)
then sgn (X)- ZGL
Address Zero and One are special addresses for the
Accumulator and Save Register. Therefore, they are
not normally used with the Extended Precision instruc-
Clear, Subtract
tions, (AE) and ($AE) cannot be accessed in this
manner. The result of EAD
~
is to add (A) and (AE).
XCS
m,X
-(E)-(X)
then sgn (X)- ZGL
2. 7 THE INDEX INSTRUCTION CLASS
Subtract
The same 16-bit fixed-point operations that take
place in the A Register, may also be programmed
for any index register. Thus, XCA m, 1 is equivalent
2-10
XSB
m,X
(X) - (E)- (X)
then sgn (X)-ZGL
Compare
XCP
2.8 FLOATING POINT INSTRUCTION CLASS
m,X
sgn (X) - (E)- ZGL
(X) unchanged
This most important class of arithmetic instructions
operates upon 32-bit data words, in the AAF portion
of the accumulator. A floating number has a sign
Store
and a twenty-three bit mantissa, which are held in A
and in the left, eight bit positions of AF (denoted as
XST
(X)-(E)
m,X
AAF 0:23 or as A, AF 0:7'). The floating-point exponent has a sign and seven bits, held in AF 8:15. The
Multiply
range of magnitudes for floating-point numbers is
between 2 128 and 2 -128; operations that result in
XMP
m,X
larger or smaller magnitudes cause an exponent
fault interrupt. A subroutine is used to normally set
Divide
the accumulator to zero or the largest possible value.
The value of zero is represented by 32 zero bits;
XDV
m,X
however, if a word with a zero mantissa and a nonzero exponent is loaded it is treated as zero.
Clear, Divide
The basic floating-point arithmetic instructions (FAD,
XCD
m,X
FSB, FMP, FDV) perform normalized arithmetic.
Normalization means that the mantissa of the opera-
Store, Rounded
tion result is shifted to the left to eliminate any
leading zero bits. The exponent is then decremented
XSR
m,X
once for each bit position shifted. FCAand FCS also
normalize the number loaded into the accumulator.
To clear an index register, the literal constant zero
is loaded by using the Immediate option; XCA = ~,X.
ing and before storing. FST (floating store) does not
The Immediate option is also used to add or subtract
normalize.
FSR (floating store rounded) normalizes after round-
constants. The value of a variable just calculated in
the accumulator is added to index register three by
All floating instructions (except compare) may be
XAD~,
used with the Unnormalize option by appending the
3. Note that in this case the zero is the ef-
fective address (specifically the address of A). Zero
letter U to the end of the mnemonic. The effect is to
and one (or $) are used to access (A) and ($A) with all
inhibit the post-normalization operation. Unnormali-
of the index instructions (except XST 1 and XSR 1).
zed data may then be considered as 24-bit, fixed-
The Slash option has no effect with address zero· and
one. While XST
~,
5 is used to move a half-word
point data with assigned scale factors (the exponents).
When adding and subtracting, the exponents are auto-
from X5 to the A Register, other means are used to
matically adjusted to agree with the larger exponent.
move index register contents directly to other 16-bit
For multiplication and division, the exponents are
registers. For example, LDAE
=~,
5 loads AE
added or subtracted. Care must be taken to avoid
from X5, LDF
=~,
3 loads the Flag Register from
overflow on division. Note that FCAU loads a copy
X3, and LDOB
=~,
2 moves (X2) to the output bus.
of (E) without normalizing, and is therefore used
In these cases the zero is a literal constant.
with FSTU to move 32-bit words from one core
2-11
location to another.
See Paragraph 2. 7 on moving
Store
Exec bits.
FSTU
(AAF)- (E)
m,X
Multiple level indirect addressing (* option) and
(A 32 :33 ) (E 32:33)
FST = FSTU
indexing is possible with all instrUctions; and as
explained in Paragraph 2.3. 3, the Immediate (=)
option may be employed indirectly through the use of
Multiply
the Macro Assembler Literal Pool feature. The
Save option ($) may be exercised with all instructions
FMP
nrm,[, (AAF) x (E)]- (AAF AD)
m,X
(AE) destroyed
to cause (AAF) to be stored in $AAF prior to the
operation. As with all arithmetic instructions, the
FMPU
m,X
(AAF)x(E) -
(AE) destroyed
ZGL flags are set by the result of each operation.
Divide
Load AAF
FCAU
(AAF AD)
m,X
(E)- (AAF)
FDV
nrm [(AAFAD) + (E)] (AAF)
m,X
(E 32 :33 ) - (A 32 :33 )
mantissa of Rem. -
(AD)
(AE) destroyed
FDVU
Clear, Add, Normalize
(AAFAD) ..;. (E)- (AAF)
m,X
mantissa of Rem.- (AD)
FCA
m,X
(AE) destroyed
nrm(E)-(AAF)
Clear, Divide
Add
FAD
m,X
nrm [(AAF) + (E)]- (AAF)
FCD
FADU
m,X
(AAF) - (E) -
FCDU
(AAF)
m,X \
~-
(AD)
) then execute FDV or FDVU
\
Store, Rounded
Clear, Subtract
FCS
m,X
nrm [ - (E)] -
FCSU
m,X
(E 32:33) -
(AAF)
I
FSR
m,X
nrm [(AAF) + (AD 1)2- 23
(AAF) unchanged
FSRU
m,X
(AAF) + (AD 1)2-23
(A 32:33)
I
I
!]
(E)
(E)
(AAF) unchanged
Subtract
2.8.1 Floating Divide
FSB
FSBU
m,X
m,X
nrm [(AAF) - (E)] (AAF)
(AAF) - (E) (AAF)
Special characteristics of FDV, FCD must be mentioned (also true for
Compare
rov,
ICD). Overflow will occur
if the mantissa of the divisor is less than half the
mantissa of the dividend. This will not occur if the
FCP
2-12
m,X
sgn [(AAF) - (E)] -
ZGL
divisor is the result of a normalized operation.
The result of a floating divide operation is to leave
FMP
B, 3
a x b product
DAD
$
add partial sum
XJT
*-3,3,-1
index and loop
FST
y
store single preci-
the quotient in AAF and the 24-bit mantissa of the
remainder in AD. Note, however, that the 24-bit AD
cannot hold the exponent of the exponent of the
remainder. The full remainder, as a proper floating
point number, can only be recovered by deduction.
2.8. 2 Floating Multiply
sion result
The result of a floating multiply is a number with
2.9 THE DOUBLE PRECISION INSTRUCTION CLASS
sign bit, 46 mantissa bits, and an 8-bit exponent,
that is held in the AAF AD register. This number is
Double preCision floating-point instructions operate
converted into the double word format by separating
on data consisting of a Sign, 46 bits of mantissa and
the mantissa into two 23-bit segments, and adding a
an 8-bit exponent. This data is held in memory as
positive sign bit for the lower half. An exponent is
created for the lower half which is 23 less than the
two successive 32-bit words, each in proper 32-bit
floating-point format. That is, each word has a
upper half exponent (AF 8 :15)' The Universal Accu-
sign, a 23-bit mantissa, and an 8-bit exponent. Half
mulator holds the lower half mantissa in AD 1 :23 and
of the double precision mantissa magnitude bits are
provides for the extra sign bit," ADo_ The.extra
in each word. The second sign and exponent are
exponent for the lower half is not required in the
redundant from the point of view of the accumulator.
accumulator and is created only upon execution of a
However, for multiple precision calculations by
double floating store instruction. (ADo) does not
subroutine, it is convenient to have each half of the
enter into any mathematical operations except for
double word in single preCision format. Note that
holding the sign of the division remainder mantissa.
the second sign is always positive and the second
exponent is 23 less than the first. Double preCision
After the execution of FMP, the extra sign bit ADo··
operations take place in the 46-bit AAFAD register;
is reset to zero. Any two's complement fraction
AF 8: 15 hold the exponent. The second exponent is
consisting of bits truncated from a larger number
created upon execution of double store (DST).
(either sign) is itself a positive number (with an
exponent). Resetting ADo makes it possible to treat
All operations are performed in the same manner,
the lower half of the product in normal floating-point
only with the 46-bit mantissa, and with the same
format.
options and restructions as the single precision
floating-point operations. Double multiply, divide,
The double precision pr()duct is often used in an other-
compare, and store-rounded must be executed by
wise single precisioN computation. For example, in
subroutine. If the immediate addressing option is
the calculation (y = L:
used, the Literal Pool feature allocates two memory
~
b i ), it is useful to accumulate
the double precision results of each multiplication as
cells from the data specified in the address field.
illustrated in this small routine.
The instruction pair, DCAU and DST, may be used to
XCA
=N, 3
DCA
ZERO
initialize
bits from one memory location to another via the
$FCA
A, 3
save partial sum
accumulator.
move double precision data (both words) with exec
2-13
store
LoadAAFAD
DCAU
(E,E + 10 : 23 ) - (AAFAD)
m,X
DSTU
m,X
(AAFAD) -
(E, E + 1 0 :23 .)
(AF 0:15) - 23 - E + 124 : 31
(A 32 : 33 ) - (E 32 :33 )
(E 32:33) (A 32 :33 )
(AE) destroyed
DST = DSTU
Clear, Add, Normalize
Multiply
DCA
m,X
nrm (E,E + 10 :23 ) - (AAFAD)
(AE) destroyed
DMP
m,X
DMPU
m,X
Add
Divide
DAD
m,X
nrm [(AAFAD) +(E,E, + 1 0 : 23 ))
_ (AAFAD)
(AE) destroyed
DADU
m,X
(AAFAD) + (E,E + 1 0 :23 )
_ (AAFAD)
(AE) destroyed
DDV
m,X
DDVU
m,X
Clear, Divide
DCD
m,X
DCDU
m,X
Clear, Subtract
Store, Rounded
DCS
m,X
-nrm (E,E + 1 0 :23 ) (AE) destroyed
DCSU
m,X
- (E,E + 1 0 :23 ) - (AAFAD)
(AAFAD)
(E 32:33) (A 32:33)
(AE) destroyed
Subtract
DSR
m,X
DSRU
m,X
2. 10 THE INTEGER INSTRUCTION CLASS
This unique set of instructions performs floatingpoint artthmeticoperations on fixed-point and
DSB
DSBU
m,X
m,X
nrm [(AAFAD) - (E,E + 1 0 :23 )]
_(AAFAD)
floating- point data. The data operand in the accu-
(AE) destroyed
AFFAD). The data operand specified by the effective
(AAFAD) - (E, E + 10 :23 )
- (AAFAD)
(AE) destroyed
address is always a 16-bit fixed-point data word.
mulator is always a floating-point number (AAF or
Each instruction (except the store commands) first
gathers the 16-bit operand, converts it to a floatingpoint number, and then executes a normal floatingpoint operation. The conversion process is termed
Compare
floating and the reverse process, upon storing, is
DCP
2-14
m,X
called integerizing.
It is important to understand exactly what happens
part of the original contents of AAF. Then (A) is
during floating and integerizingj other features
stored at the effective address and AAF is restored
(except half-word address option) of the ten instruc-
to its original state. If the magnitude of (AAF) is
tions of this class are the same as those of the
equal to or greater than 2 16 an overflow will occur,
Floating Point Class.
and an incorrect number will be stored.
2. 10. 1 Floating
The half-word addressing options (= 1) are aVailable,
as well as indirect addressing and indeXing. Ad-
A 16-bit data word is normally thought of as a fixed-
dresses zero and one refer to (A) and ($A). The
point fraction, with the binary point adjacent to the
same rules for the unnormalize (U) option and divide
sign bit. Fixed-point multiply and divide instructions
overflow apply as for floating-point instructions.
perform fractional arithmetic. On the other hand, a
of the Save options will save (AAF).
Use
16-bit data word may be considered to be a fixedpoint integer, with the binary point to the far right-
Load, Integer
hand position. This is of course the common practice
when operating on memory address numbers.
ICAU
m,X
flt(E) -
(AAF)
which means:
No confusion occurs provided a correct scale factor
(E)- (A O: 15 )
is used when the data word enters an arithmetic
~- (AF o:17 )
operation. The floating of a 16-bit word by an
+ 15 _
(AF 8:15)
= Exponent
Integer Class Instruction causes the contents of the
half-word effective address to be loaded into A
Clear, Add, Normalize
(for Integer-clear-add, ACA), zeroes to be loaded
in AF 0:7' and exponent of + 15 to be loaded in AF 8: 15.
ICA
m,X
nrm [flt(E)] -
(AAF)
When in memory, the operand is considered an
integer, hence a scale factor of 215 is entered in AAF
Add
as the number itself becomes the mantissa (a fraction)
of a floating point number. The least Significant eight
lAD
m,X
nrm [(AAF) + flt(E)]-(AAF)
bits of the mantissa are made zero. After this con-
lADU
m,X
(AAF) + flt (E) -
(AAF)
version, the rest of ICA is simply to normalize (AAF).
In the case of lAD, ISS, IMP, etc., the above con-
Clear, Subtract
version is performed before presenting the floated
operand to the accumulator.
ICS
m,X
nrm [-flt(E)] -
ICSU
m,X
-flt(E)- (AAF)
(AAF)
2. 10.2 Integerizing
Subtract
The integer part of the result of any floating-point
calculation (by floating, double precision, or integer
ISS
m,X
nrm [(AAF) - flt(E)]- (AAF)
class instruction) can be stored as 16-bit fixed-
ISSU
m,X
(AAF) - flt(E)- (AAF)
m,X
(AAF) - flt(E)- ZGL
point integers provided the magnitude of the number
is less than 2 16 • The IST instruction (same as ISTU)
Compare
first causes the contents of AAF to be shifted left or
right as needed, bringing the exponent to + 15. When
(AF 8 :15)
ICP
= + 15, the binary point may be considered to
be to the right of A 15 , hence (A) is the 16-bit integer
(AAF) unchanged
2-15
immediate addressing. Thus, the Fortran state-
store
ment, A = 3B + I might be implemented by the code:
ISTU
m,X
int(AAF)- (E)
(AAF) unchanged
FCA
B
IST = ISTU
IMP
=3
lAD
=1
FST
A
Multiply
IMP
m,X
nrm [(AAF) x flt(E)]
_
(AAFAD)
Where A and B are floating-point numbers, and I,
a Fortran integer, is stored as a fixed-point number.
Care must be taken with IDV and lCD, for the floating
(AE) destroyed
operand (divisor) is an unnormalized number and if
IMPU
m,X
(AAF) x flt (E) -
(AAF AD)
the resultant mantissa is less than half the accumulator mantissa overflow occurs.
(AE) destroyed
A characteristic of negative twots complement num-
Divide
bers, as noted elsewhere, is that when least signifiIDV
m,X
nrm [(AAFAD) +flt(E)]
cant bits are truncated, the result is greater in
magnitude (more net negative) than the untruncated
-(AAF)
number. IST truncates the fractional part of (AAF)
(AE) destroyed
before storing and yields for negative numbers the
"next more negative integer". ISR yields the nearest
IDVU
m,X
(AAFAD)4flt(E)- (AAF)
(AE) destroyed
integer for both signs. The pairs; IST and ISTU, ISR
and ISRU, each produce identical codes, no normalization is performed.
Clear, Divide
2.11 BOOLEAN CONNECTNE INSTRUCTIONS
ICD
m,X
(0 -
ICDU
m,X
then execute FDV, FDVU
(AD»
(AE) destroyed
If an accumulator (a) bit and a memory (m) bit are
considered as arguments of a logical function to form
a resultant bit, r. Then there are sixteen possible
store, Rounded
ISRU
m,X
functions that may be performed.
int(AAF) +~ -
where
~
(E)
= ~ iffrae (AAF)<:1/2
= 1 iffrae (AAF»1/2
(AAF) unchanged
Table 2.3 gives the function as well as showing the
four possible values of r for each combination of a
and m. Basic operations used in this table is
indicated by:
ISR = ISRU
Integer arithmetic instructions may be mixed freely
1.
The over-bar: logical inversion of the
within floating computations to save execution time
logical value.
and memory space, particularly with the use of
to ONE)
2-16
(ONE to ZERO and ZERO
Table 2. 3. Boolean Connective Functions
6.
Exclusive OR: Result is ONE if the argument values are different.
a =
0 1 0 1
m=
0 0 1 1
r =
1 1 1 1
7.
Equivalence: Result is ONE if argument
values are the same.
Set r = 1 regardless of
.~ and!!!.
0 0 0 0
Reset r = 0 regardless of
~andm
The last four functions are performed by first complementing a and then executing the OR, AND, NOR
or NAND function.
0 1 0 1
r=a
1 1
r =m
1 0 1 0
r=a
listed in Table 2. 3. One instruction stores the re-
1 1 0 0
r= iii
sult r in the original location of a. The other instruc-
0 1 1 1
r = a + m OR function
0 0 0 1
r = a x m AND function
Variables a, m, and r are not restricted to single
1 0 0 0
r = a+m NOR function
bits but may be in bytes. If bytes are used, the byte
1 1 1 0
r =
These are thirty-two basic Boolean connective in0 0
structions, two for each of the sixteen functions
-
tion stores r in the memory location m.
0
1 1 0
1 0 0 1
axm NAND function
r = (a + m) (a x m)
sixteen functions are performed upon individual pairs
of bits within the bytes both simultaneously and inde-
Exclusive OR
pendently. The byte size is specified (1, 2, 4, 8 or
function
16 bits) by writing the respective digit after the in-
r = (a x m) + (a x m)
EQUIVALENCE
function
1 0 1 1
r=a+m=axm
0 0 1 0
r=axm=a+m
0 1 0 0
r=a+m=axm
1 1 0 1
sizes of the three variables are all the same. The
-
--
r=axm=a+iii
struction mnemonic in the OP code field. A byte
size of 16 is implied if no digits are specified. For
example, HAl resets a single bit in the accumulator;
HAS resets 8 bits; and HA resets aU 16 bits of the
A register.
For byte sizes of 1, 2, 4, or 8 bits, the byte position
within the half-word is speCified in the count field
(third subfield of the address field) by a decimal
number 0 to 15. For example, RM1, m, X,
2.
OR: Result is a ONE if either argument
is a ONE.
~
resets
the sign bit of (E); RM1, m, X, 15 resets (E 15)' The
positions of larger bytes are denoted by numbers 0
to 7 for two bits, by 0 to 3 for four bits and 0 to 1
3.
AND: Result is ONE only if both arguments are ONE.
4.
(E s:15 ).
NOR: Result is ONE if neither argument
is ONE.
5.
for eight bits. Therefore, RM8, m, X resets
2.11.1 The Mnemonics
NAND: Result is ONE if either argument
The thirty-two instruction mnemonics indicate the
is ZERO.
logical action performed and the designation of the
2-17
result. They do NOT indicate the name of the Boolean
function. If the mnemonic ends in "A", the result is
memory bits E 12:15 are inspected. For each ZERO bit (low)
placed in the accumulator. If the mnemonic ends in
the corresponding bit within
"M", the result is put in memory. The mnemonic
A 12 :15 is set to ONE and the
codes for the 16 pairs of instructions appear as shown
other bits of A 12 :15 are reset to
ZERO. This is a byte load in-
in Table 2.4.
struction.
Table 2. 4. Boolean Mnemonics
Conditiont
Destination
Accumulator
2.
CEHM8 m,X,fj
Complement A,
Either High to Memory; 8-bit
Memory
byte; first byte position; which
SA
SM
Set
RA
RM
Reset
AHM
Accumulator High
ALA
ALM
Accumulator Low
memory is set high, .otherwise it
MLA
MLM
Memory Low
remains low.
EHA
EHM
Either High (OR)
BHA
BHM
Both High (AND)
BLA
BLM
Both Low (NOR)
ELA
ELM
Either Low (NAND)
BDA
BDM
Both Different (XOR)
for the specified byte is simply restored (unchanged),
BSA
BSM
Both Same (EQU)
to its original location. However, MHM is a useful
CEHA
CEHM
Compo A, Either Hi
CBHA
CBHM
Compo A, Both Hi
only action of MHM is to indicate a ZE RO byte in
CBLA
CBLM
Compo A, Both Lo
memory which, if E
CELA
CELM
Compo A, Either Lo
:I:
means the complement of (A 0:7)
is compared to (E o:7 )' bit by bit.
If either bit of a pair is high, the
corresponding bit position in
2.11.1.2
AHA, MHM).
*
Special Cases (BEQT Replacing
The two codes accumulator high to
accumulator (AHA) and memory high to memory
(MHM) appear to do nothing. This is nearly true,
ZERO byte test, since the Z flag is set if the result
of the logical function is a byte of all ZEROES. The
= 0,
refers to the accumulator.
The AHA code is therefore redundant and is replaced
by the more useful Byte Equality Test (BEQT) for
which the byte size and position options are the same
t The expression in the right column describes the
condition for which a bit in the result is set to ONE;
all other conditions produce a ZERO bit in the result.
as above. Tl\e action of BEQT is to set the Z flag if
and only ifall accumulator and memory bytes are
the same.
2. 11. 1. 1 Examples
1.
2-18
Memory low to
accumulator; 4- bit byte; byte
2.11. 2 Addressing
MLA4 m,X,3
Indirect addressing and half-word addressing options
position 4; which means the
are valid for Boolean instructions, however immediate addressing is not possible with M-type
instructions. An effective address of ZERO refers to
In the following table of instructions, all of the pos-
the accumulator. This results in each A and M pair
sible combinations of byte sizes and byte positions
of instructions being equivalent.
are given by way of example. Any instruction may
An effective ad-
dress of ONE refers to core memory cell number
one for
M-typ~
instructions.
address any of the bit combinations illustrated.
It does not refer to
$A register since storing in the Save Register is
only possible by means of the $ prefix operator.
In the following examples, if the result of the logical
operations yields a byte (in the referenced position)
See Paragraph 2.3.2.
consisting of all zeroes, the Z flag is set; otherwise it
is reset.
Table 2.5. Boolean Instruction
set and reset
¢
(one bit/byte)
SAl ~,~,~
1-
(Ao) reset Z
SM1 m,X, 1
1-
(E1) reset Z
RA1 ~,~, 2
~ -
(A2) set Z
RM1 m,X,3
~
(E 3) set Z
-
byte equality test
BEQT1 m,X,4
(one bit/byte)
if (A4) = (E 4) set Z, if ",reset Z
(one bit/byte)
store and load
AHM1 m,X, 5
(A 5) -
(E 5 )
MHA1 m,X, 6
(E 6) -
(A 6 )
zero byte test
MHM1 m,X,7
(one bit/byte)
if (E7) = ~ set Z, if
",reset Z
(one bit/byte)
complement accumulator
ALA1 ~,~,8
(one bit/byte)
store and load complement
ALM1 m,X, 9
(A 9 ) -
(E 9)
MLA1 m,X, 10
(E 10) -
(A 10)
complement memory
MLM1 m,X, 11
(one bit/byte)
(E 11) -
(E 11)
2-19
Table 2.5. Boolean Instruction (Cont)
(one bit/byte)
QR, AND
EHAI m,X, 12
(A 12 ) OR (E 12)-(A 12 )
EHMI m,X, 13
(A 13 ) OR (E 13) - (E 13 )
BHAI m,X, 14
(A 14) AND (E 14) - (A 14)
BHMI m,X, 15
(A15) AND (E 15)- (E 15)
(2 bits/byte)
NOR, NAND
BLA2 m,X,~
(AO} NOR (E o:1 )-(A o:1 )
BLM2 m,X, 1
(A 2: 3) NOR (E 2:3)-(E 2:3 )
ELA2 m,X,2
(A 4:5 ) NAND (E 4:5)-{A 4:5 )
ELM2 m,X,3
(A 6 : 7) NAND (E 6 : 7)-{E 6 : 7 )
(2 bits/byte)
XOR, EQU
BDA2 m,X,4
(A S: 9 ) XOR (E s :9 ) - (A s:9 )
BDM2 m,X, 5
(A 10 : 11 ) XOR (E10:11)-(E10:11)
BSA2 m,X,6
(A 12 :13 ) EQU (E 12:13)-(A 12 :13 )
BSM2 m,X,7
(A 14: 15 ) EQU (E 14:15)-(E 14:15)
(4 bits/byte)
complement A, then OR, AND
m,X,~
(A O:3 ) OR (E o:3 ) -(AO:3)
CEHM4 m,X, 1
(A 4:7) OR (E 4:7)- (E 4:7)
CBHA4 m,X,2
(A 8:11 )
CBHM4 m,X,3
(A 12 :15 ) AND (E 12 :15 ) - (E 12 :15 )
CEHA4
AND (E 8:11) -
(8 and 16 bits/byte)
complement A, then NOR, NAND
2-20
(A 8:11 )
CBLA8 m,X,~
(A O:7)
CBLM8 m,X, 1
(A 8:15 ) NOR (E 8:15 ) - (E s:15 )
NOR (E o:7 ) -
(AO:7)
CELA m,X,~
(A o:15 ) NAND (E o:15 ) - (A o:15 )
CELM m,X,~
(A o:15 ) NAND (EO:15)-{EO:15)
2.12 CONDITIONAL INSTRUCTIONS
The condition code c, may have thirty-two values;
these are the 16 codes for the bits of the flag register
2.12.1 The Flag Operations
and the same codes prefixed by N to denote the inverse condition. They are:
The execution of each of the following instructions
Z, G, L, Y, C, B,
HJc
halt and jump to E
EXc
execute and instruction at E
Lc
link to E
LRc
reset flag, link to E
JTc
trigger (complement) flag, jump to E
1, 2, 3, 4, 5, 6, 7, 8
N, NZ, NG, NL, NY, NC, NB, NE
N1, N2, N3, N4, N5, N6, N7, N8
Normal indirect addressing is available with all
instructions.
JSc
set flag, jump to E
JRc
reset flag, jump to E
Jc
jump E
Halt
tHJc
m,X
user mode:
= 0, NOP; if (c)
is conditional upon the state of the flag indicated by
if (c)
c; c can refer to any flag of the flag register in its
interrupt no. 2
1,
set or reset state.
monitor mode:
Example:
HJ1
if (c)
START
= 0, NOP; if (c)
1,
computer halts with
(E) -
The halt will occur, with subsequent transfer to
(L)
START, only if flag 1 is set. If it is not set, no halt
occurs, and transfer to the instruction following HJ1
Execute
takes place. On the other hand, the reverse applies
EXc
m,X
to the example:
if (c) = 0, NOP; if (c) = 1,
execute the instruction located
HJN1
at E
START
that is, the halt will occur if flag 1 is not set, etc.
Link
Lc
m,X
if (c)
= 0, NOP; if (c)
LR, JT, JS, JR cause the indicated change to the
(L + 1 ) - (E),
referenced flag whether the instruction is executed
(E + 1 ) - (L)
1,
or not; the instruction is executed conditional to the
present state of the flag. If unconditional execution
of the instruction is required, c is left blank.
LRc
m,X
if (c) = 0, reset flag;
if (c) = 1, reset flag,
(L + D - (E) ),
If unconditional non-execution of the instruction is
(E + 1) -
(L)
required for creating a class of no-operations, c
could be set to N. For this purpose HJN, EXN, LN
and IN would serve. Of these the last, IN, has been
selected in the assembler as the non-operation instruction, NOP.
t Privileged instructions, see Chapter 3.
2-21
index, jump test
Jump
Jc
m,X
if (c)
=
(E) -
m,X
JRc
m,X
1,
XJT m,X,A
(L)
(X) + A - (X), -128 :s A:s 127
then if sgn (X)
if (c)
= 0, reset flag;
if (c)
=
(E) -
JSc
0, NOP; if (c)
= ~
A,
(L + 1 ) - (L); if I, E - (L)
1, reset flag,
2. 13 INSTRUCTIONS TO LOAD AND STORE
SPECIAL REGISTERS
(L)
if (c)
=
0, set flag;
if (c)
=
1, set flag,
Each of the several 16-bit registers in the 8400 and
(L)
the 16-bit input and output busses are serviced by a
(E) -
pair of instructions that gather and store a half-word
JTc
m,X
if (c) = 0, trigger (comple-
ment) flag; if (c)
flag, (E) -
=
1, trigger
(L)
from either half of the memory word. The addressing options
*, /,
and X apply in each case and the
Immediate option (=) is available for all load instructions. Exec bits are not affected or moved by these
2.12.2 Index Jumps XJ, XJT
instructions, and except for the direct effect on the
flag register with LDF, there is no associated
2.12.2.1 Unconditional Jump - XJ m,X,A.
The specified index register X is algebraically incremented by the value A, and transfer takes place to
location m (NOT to location m, c).
change to the flag register. The 32-bit data channel
control registers (CCR) are serviced by a similar
pair of instructions; however, the half-word addressing options
=
and / do not apply. In the case of
the 16-bit channel data registers (CDR), a half-word
A is accorded 8 bits (8-15) in, the instruction and is
interpreted as (-) if bit 8 is "1", or (+) if bit 8
is
"o!~
Thus, -128 :s A :s 127.
and Exec bit are moved between memory and the
registers; however, the
=
option does not apply
and the Left-Right option is determined by another
register (CFR) in the data channel. See 4. 1.
2. 12.2.2 Conditional Index Jump - XJT,
m,X,A. The contents of index register X are algebraically incremented by A, and if the sign of the
2.13.1 Load Register or Bus
resultant index register contents is found to be the
same as that of A, transfer takes place to the instruc-
LDAE
m,X
(E) -
(AE) external accu-
mulator register
tion following the XJT instruction. If these differ,
transfer takes place to m. A has the same signifi-
(AE) destroyed
cance as described above.
The speCified index register is not used in the effective address determination. If indirect addressing is
used with XJ or XJT, address modification by indexing
does not take place at any level.
LDF
m,X
(E) -
(F) flag register
LDL
m,X
(E) -
(L) location counter
LDT
m,X
(E) -
(T) timer register
LDM
m,X
(E) -
(M) interval interrupt
mask register
index, jump
XJ
m,X,A
(X) + A-(X), -128:s A:s 127
E-(L)
2-22
LDE
m,X
(E) -
(EM) external
interrupt mask register
LDC
m,X
(E) -
(C) console register
LDOB
m,X,R
(E) -
Output bus R where
There are 15 bus addresses, R, which are written
as octal numbers, and eight channel numbers, k
R:s 178
~ through 7).
When indexing is not employed, these
instructions must be written with two commas, e. g.,
"
LDCC
m,X,k
(E O: 31 ) -
(CCRk) channel
LDOB m" 1.0 loads output bus number 8. Note that
LDOB = .0, 3,.0 loads bus zero from index register
control register k
three.
LDCD
m,X,k
(Eo: 15,32)- (CDRk) or
(Fh6: 31, 3S> (CDRk) channel
data register k according to
2. 13.3 The Flag Register
the L bit of channel junction
The sixteen bits of the flag register, F, are moved
register
as a group, although they are set and reset individually by other instructions and machine functions.
2.13.2 Store from Register or Bus
The zero bit of F is not really a flag and cannot be
STAE
m,X
(AE) -
reset; it is always set. Hence, when tested by con-
(E)
ditional instructions, a positive test always results
STF
m,X
(F)
(E)
STL
m,X
(L)
(E)
STT
m,X
(T)
(E)
(see Paragraph 2.12).
Bits F 1:30 are the Z (zero), G (greater than), and
L (less than) flags that are set to the sign of A
after each arithmetic instruction, except the index
STM
m,X
(M)
(E)
STE
m,X
(EM)- (E)
class. For the index class, they are set by the
sign resulting from the index arithmetic operation.
The Boolean connective instructions also set and
reset flag Z. Bit F 4 is V (overflow flag) which
(E)
m,X
(C)
tSTIB
m,X,R
Input Bus R -
tSTCC
m,X,k
(CCRk)
tSTCD
m,X,k
(E o:15 , 32) or
(E 16:31, 33) laccording to the
L bit of channel function
when set. This flag cannot be changed in user
register
mode. (See 3.6.1.). Register bits F8:15 are eight,
STC
remains set, until reset.
(E)
Bit F5 is C (carry flag)
which indicates if a carry from the accumulator
occurred with the last arithmetic instruction.
(E 0:31)
Bit
F 6 is B (busy flag) which indicates whether or not
(CDRk)
the last
I/o instruction was
executed.
Bit F 7 is
E (enable flag), enables the entire interrupt system
general purpose flags available to the programmer
All
I/o instructions plus those that modify the
limiter,
(called flag 1, 2, ... flag 8).
These eight flags
console, mask register are privileged instructions
can be set and reset manually at the computer
and in user mode they are not executed by activate
console.
the internal interrupt number two (see 3.6.1). In a
computer lacking an automatic data channel LDCC
2.13.4 Location Counter
and STCC cause this interrupt in monitor mode as
well.
tPrivileged instructions
The LDL instruction is quite equivalent to the jump
instruction, but there are differences in addressing
2-23
options. Note the following fWlCtionally equivalent
iLDOB, LDCC, LDCD, STIB, STCC, STCD
pairs:
Instructions
LDL
LDL
=m,X
m/,X
J
J*
m,X
m, X to one level of
indirectness
There are no direct equivalents of:
LDL*
m/,X
LDL*
/m,X
LDL*
-m/,X
LDL*
=/m,X
LDL
/m,X
These instructions are treated in the Input/Output
Instructions found in Paragraph 2. 14.3.
2. 14 EXEC Brr INSTRUCTIONS
Every memory word (in core memory and on the
Rapid Access Drum) contains 32 data bits plus two
special bits that are identified as left and right Exec
bits. The left Exec bit (Ed is in position 32, and
the right Exec bit (ER) is in poSition 33, however,
Thus, LDL can jump direct or indirect to addresses
EL is always associated with the left half-word (bits
stored in right half-words. LDL*m,X reaches to one
0:15), and ERwith bits 16:31. EL is used by all sys-
more level of indirectness than does J*m,X. Note
that the Indirect-immediate option is possible (LDL* =
tem programs to designate a relocatable address in
m,X). This differs from LDLm,X only when the con-
word located in core memory. E R operates with the
tents of the effective address m, X specifies indirect
interrupt system to interrupt the computer when an
or index modification.
illegal reference is made to the memory. cell in user
the left half-word. ER is primarily used to protect a
mode. See Paragraph 3.6. 1.
2. 13. 5 Timer
The timer may be read, but not changed in user
mode. The operation is suchthat the contents of
Exec bits are set, reset, and tested respectively by
the three instructions: SEX, REX, TEX. In each
T is decremented. once every millisecond. When (T)
case, the contents, other than EL or ER, of the effective address is ignored. The slash option speci-
reaches zero, internal interrupt number six is activated (see Paragraph 3.6). This interrupt forces the
fies left or right Exec bit; for example, REX m, X
mode into monitor mode and then the T register is
struction sets the Z flag if the specified exec bit is
reloaded by the monitor program.
2. 13.6 Mask Register
resets EL and REX /m,X resets En. The test inset.
2. 14. 1 Exec Bit Controls
The internal mask register (M) and the external mask
register (EM or E) contain 16 bits each, which indi-
SEX m,X
1-
(E'30
set EL
vidually enable interrupt lines. These registers can-
SEX /m,X
1 -
(E33~
set ER
REX m,X
~ -
(E32)
reset EL
REX /m,X
~- (E 33)
reset ER
TEX m,X
(E 32) -
Z flag
test EL
TEX /m,X
(E33) -
Z flag
test ER
not be modified in user mode. See Chapter 3.
2.13.7 Console Register
Instructions LDC and STC are privileged instructions,
and can be performed only in monitor mode. The
contents of this register can be set and reset manually at the computer console.
2-24
2. 14. 2 Accumulator Exec Bits
system conventions, index registers 5, 6, and 7 are
assumed always to contain relocatable address
The accumulator is the only register that accepts
values.
Exec bits. Bit A32 is associated with the EL of a
left half-word loaded from memory. Bit A33 is
2. 15 INPUT/OUTPUT INSTRUCTIONS
associated with the E R of a whole word loaded into
AAF. A32 and A33 are addressed by the above in-
The instructions in this group are:
structions with an effective address of zero.
SFL
=M" k
Set a function line in bankok
The accumulator Exec bits each exist for a specific
purpose. A33 is used when a word is to he moved
TSL
=M, , k
Test a sense line in bank k
with its protection bit Er from one core location to
LDCD
M,X,K
Load channel data register,
channel K (output)
another. The instruction pair, FCAU, FST, moves
all 34 bits from core to core. Similarly, DCAU,
DST is used to move double precision data (and must
STCD
M,X,K
channel K (input)
not be used to move pairs of words of any other type
of data). All arithmetic instructions (except FCAU
Store channel data register,
STCC
M,X,K
and DCAU) and all Boolean instructions that change
Store channel control word,
channel K (input)
the contents of the accumulator reset A33' Any instruction that does not change the contents of the
LDOB
M,X,R
Load output bus R
STill
M,X,R
Store input bus R
accumulator does not alter (A33). Only FST and DST
store (A33) in memory.
The accumulator left Exec bit, A32' is used to preserve the relocation information throughout address
calculations, as follows. The difference of two relocatable address values must be an absolute value;
LDCC and STCC instructions are only available with
the Automatic Data Channel Processor expansion and
once initiated, govern the transfer of data without
further intervention of the central processor.
the sum of such numbers, however, is not defined in
these terms. The sum or difference between an
absolute value and a relocatable one must be relocatable. Therefore, after either of the instructions
AD m/,X and SB m/,X (note: left half option only),
the contents of A32 is the exclusive OR of (E 32) with
the initial (A32)' A32 is located from memory only
by the instructions: FCAU, FCSU, DCAU, DCSU,
CA (left half), and CS (left half). All other arithmetic
and Boolean instructions that change the contents of
Programmed half-word transfer using LDCD and
STCD are available with or without ADCP. In addition, the System Interface Instructions LDOB and
STill provide data transfer between registers of
external devices.
A more complete summary of these instructions is
given in Chapter 4, Paragraphs 4.3 to 4.5.
2.15.1 SFL Instruction (Set Function Line)
the accumulator, reset A 32' All others that do not
change (AAFAD), do not alter A32' Only the instruc-
Immediate addressing must always be used with SFL
tions FST, DST, ST (left half) store A 32 in memory.
instructions. Within this instruction indexing and
indirect addressing may also be used. The effective
A 32 and A 33 are not saved by the Save Register
address, E, is therefore always used as an im-
option. Index registers do not contain bits for holding
mediate operand, whose bit pattern determines the
relocated Exec bits; however, by programming
channel, device, and function required.
2-25
Bits 13-15
The data channel SFL's fall into two broad categories
Byte Size/Count
(1) initialize channel and connect device, or (2) chan00000
Exec bits only
00001
8/1 (i. e., signifies 8 bytes
of 1 bit each)
00002
8/2
always set
00003
16/1
bit 1-3
channel number (0-7)
00004
4/4
bit 4-7
device designation (non-zero byte,
00005
4/1
00006
4/2
00007
4/3
nel clear, disconnect, set/reset ready interrupt, and
set/reset signal interrupt. A non-zero 4-bit byte
(bits 4-7) denotes the former category, whose bit
pattern significance is as follows:
bit
,l:S
1-15)
bit 8
transfer Exec bits if set, omit Exec
bits if reset
bit 9
binary mode if set, BCD if reset
bit 10
start transfer with left half-word
In the second category of data channel functions de-
noted by a zero byte (bits 4-7), bits have the following
significance:
initially if set, right if reset
bit
,l:S
unconditional channel clear
alternate left to right, right to left,
bit 11
bit 1-3
channel number (0-7)
from word half specified by bit 10
bit 4-7
(zero byte)
transfer to memory (input) if set; if
bit 8-10
no significance
bit 11
Reset Channel signal interrupt
bit 12
Set Channel signal interrupt
bit 13
Reset Channel ready interrupt
bit 14
Set Channel ready interrupt
bit 15
Channel disconnect
if set; if reset continue transfers
bit 12
reset, transfer to device (output)
bit 13-15
code for bits per byte/number of
bytes per half-word transferred.
Bits 4-7
Device
01000
Paper Tape Reader
01400
Card Reader
02000
Paper Tape Punch
02400
Card Punch
03000
Typewriter
Each device has a set of SFL's for establishing de-
03400
Line Printer
vice dependent conditions, e. g., on the typewriter -
compatible combinations of channel data functions
may be called with one SFL instruction by setting the
corresponding bits.
type red or type black; on the paper tape reader 04000
2-26
Magnetic Tape
read forward or read reverse; on the paper tape
punch - turn power on or turn power off; and so on.
2.15.3 LDCD, STCD Instructions
Available SFL's are specified in device descriptions,
Paragraph 4. 5 in this manual.
Having connected a device for data transfer, the
The successful completion of the SFL instruction is
STCD instruction.
actual transfer of data is effected by the LDCD or
indicated by the busy (B) flag in the flag register,
which changes to a reset condition after completion.
There must be one of these instructions per halfword transferred. If bit 11 of data channel SFL
2.15.2 TSL Instruction (Test Status Line)
calling for left and right alternate transfer is set,
two instructions per memory location are required.
Immediate addressing is required with TSL instruc-
Since initial and subsequent left/right half positioning
tions; within this restriction, indexing and indirect
is implicit in the SFL call, address specification in
addressing may be used. The effective address E,
this case is identical for both instructions and refers
is therefore always used as an immediate operand,
apparently only to the left half.
whose bit pattern specifies which test is required, on
which device, on which channel. As with SFL in-
The instruction modifier X, *, may be used with both
structions, bit 1-3 specify the channel, and bits 4-7
LDCD and with STCD. The / modifier is irrelevant
the device; with the remaining bits specifying the
and should not be used with either.
test.
The accumulator cannot be accessed directly by an
For the data channel functions the following tests are
STCD or LDCD instruction. (E = 0 or 1 refer to
available.
core location 0 or 1 with LDCD and STCD.)
00001
-00001
Test channel signal
Test channel signal and clear
Example:
The following example reads paper tape, punched in
autoload format, for N words, starting the loading
00002
Test channel parity
at memory location MEMORY. The device SFL
connects the paper tape reader (PTR) to transfer
-00002
Test channel parity and clear
Exec bits, binary mode, starting with left half memory word, alternating left/right/left, etc., reading
00004
Test channel ready
from device to memory, half-words comprising four
4-bit bytes.
With peripherals, device related tests are available.
For example: for card reader, test if the reader is
SFL
=1,,1
ready; test if the reading of the previous card is
conditional disconnect
channel 0, bank 1
complete: for magnetic tape, test if tape movement
has ceased; and so on. The available tests are speci-
SFL
='-1374" 1
connect PTR
JB
*-1
wait until device
fied in device descriptions in Paragraph 4. 6 of this
manual.
connected
The Z flag is set if the result of a TSL is true, reset
is false.
XCS
-N,X
count of N in index
register X
2-27
STCD
MEMORY +
transfer first half-
N,X
word to memory
MEMORY +
transfer second
N,X
half-word to memory
Example
SCI
STCD
,!nterrupt (but do not disconnect)
TED
XJT
*-2,X,1
SFL
Transfer data until ]!ither count is zero
loop until N words
or signal is received, then Qisconnect
transferred
(and interrupt)
disconnect.
=1,,1
.§kip data until gount is zero then
These ADC OP symbols could be used as shown below
to cause the skipping of the first 500 words of a data
2.15.4 LDCC, STCC Instructions
record, then the transfer into memory of either the
remaining portion of the record if there were fewer
Available only with ADCP, these instruction govern
than 1500 words, or of the next 1000 words.
transfer of data according to a data control word of
the form
SFL
ARG(*)
connect device
for transfer to
ADDRSS,X, COUNT
memory
where ADDRSS is the starting address of a block size
given by COUNT, in a manner specified by the * and
JB
*-1
X bits (16-19).
wait until
connected
LDCC
The options implied by bits 16-19 are:
OMIT
initiate skip
action
bit 16 - Transfer data if set, skip if reset (T or S)
bit 17 - Disconnect at end if set, do not disconnect
if not set (D or I)
bit 18 - Skip or transfer until signal (S)
OMIT
bit 19 - Skip or transfer until count complete (C)
READ IN TED
and are summarized mnemonically by one of the
SCI
,,500
ADC OP symbol
START,,1000
definitions
with an interrupt routine containing
following OP symbols: LDCC
TCD, SCD, TCI, SCI, TSD, SSD, TSI, SSI, TED, SED, TEl,
READIN
initiate actual
data transfer
SEI in the formal context:
If a signal, due to the advent of a terminating charac-
OP
2-28
ADDRSS" COUNT
ter or situation (stop code on paper tape, end-of-
record gap on magnetic tape, end-of-card on card
is a request for an arithmetic shift of the A register
reader) precedes the completion of the specified
contents 4 places to the right (equivalent to a division
count, the number of words transmitted can be as-
by 24 ). The same affect is achieved by
certained by performing STCC after interrupt, and
examining the count field.
Transfer of data, one initiated, proceeds automatically under control of the ADCP without the need of
2. 15. 5 LDOB, STIB Instructions
These system interface instructions effect the transfer of 17 bit data (16 bits plus 1 exec bit) from E via
the output buss to the specified external register
4
ASH*
SAM
or by:
central processor intervention.
An interrupt is always generated on the completion
of these ADCP functions.
ASH
where the left half contents of SAM is 4. These are
examples of positive shifts.
With arithmetic shifts, the sign bit
~
is propagated
for right shifts, so that a negative number remains
negative, a positive one positive. Similarly for left
shifts (negative shifts) the sign bit does not change,
and bit 1 is lost for each left shift.
(LDOB), or from the specified external register via
the input buss to the effective address E (STm).
For extended shifts, the sign bit of the AE register
does not change. Therefore, only bits 1-15, 17-31
The X, *, =and / options are available with LDOB,
and X, * and / with STm
are involved. For example,
EASH
-15
2.16 SHIFT, ROTATE AND NORMALIZE
shifts the AE register, considered as an arithmetic
INSTRUCTIONS
quantity, to the A register.
These instructions are available in single or extended precision form. If extended preciSion, the
The Z, G, L and V flags reflect the resultant state
A-AE registers are involved; if single precision,
the A register only.
of the A, or A-AE registers.
Bits in positions 15-E to 15 for ASH right shift or
Each instruction in this group may use the Save
option.
2. 16. 1 Arithmetic Shift
31-E to 31 for EASH right shifts, where E is the
number of shifts, are permanently lost. For left
shifts, the same applies to bits in positions 1 to E
for both ASH and EASH. If a 1 bit is lost in the
latter cases for initially positive value, or a
~
bit
Although = is not written in the first character position of the address field of shifts or rotates, the
immediate mode is .assumed· by the hardware. Thus,
for an initially negative value, the overflow flag is
if N=3, and (X)=1, so that E=4
The nominal effective address is truncated by hard-
ASH
N,X
set.
ware to provide an effective immediate address E
such that -64sEs63.
2-29
The Save option prefix may be used to save (A) in ($A)
2. 16. 2 Rotates
prior to shifting. H indirect addressing is used, the
immediate operator is still implied and the value of E
The contents of the A register for single precision
is taken as the shift count. Actually E is truncated at
or of the A-AE register for extended precision, are
regarded as a bit pattern having no arithmetic signif-
7 bits, and the effective count is:
-64
$
(Eo, 10:15)
$
icance, so that bit .0 and bit 16 for extended preCi-
63.
sion are treated as any other bit.
2.16.1.1 right arithmetic shift
In contrast with arithmetic shifts, no bits are lost:
ASH
m,X
(EO, 10:15) positive
where e = (E 0,10:15) modulo 15
shift (A 1 : 15 ) right bye bits
for Single precision, right-rotation (positive E) the
(Ao> - - (AI:e)
right-most e bits are lost
extended precision rotation, the bit in position 31 is
bit in position 15 is transferred to position .0; the
reverse applies to left (negative) rotation. For
transferred to bit position
.0; the reverse
applies to
left (negative) rotation.
EASH
m,X
where e = (E 0,10:15) modulo 31
shift (AAE 1:15,17:31) right by
e bits
(Ao) -
The save prefix operator may be used, and the same
immediate addressing rules apply as above for shifts.
left most e bits
The flags are unaffected by rotates. For example,
(excluding AAE 16)
right-most e bits are lost
(AAE l d unchanged
EROT
exchanges the contents of the A and AE registers.
2. 16. 1. 2 left arithmetic shift
ASH
m,X
(E 0,10:15 ) negative
where e = (Eo, 10:15) modulo 15
shift (A l : 15 ) left by e bits
.0 -
right most e bits
(A l :e ) lost, V flag set if any
lost bits
where e
EASH
m,X
=
I
16
The rotate instructions are formally summarized as
follows:
rotate, right
(EO, 10:15) positive or negative
or left
for e = (EO, 10:15)
(Ao)
ROT
m,X
(AO: 15 ) -
EROT
m,X
(AAE O: 31 >-
(E 0,10:15) modulo 31
shift (AAE 1:15,17:31 } left by
e bits
(Ae :(15+e)
)
modulo 16
(AAEe :(1+e)
)
modulo 32
.0 -
right most e bits
(excluding AAE 16 )
Normalize
left most e bits lost (excluding
AAE 16 )
V flag set if any lost bits
(A 0)
2-30
I
The specified index register receives a count of
shifts required to normalize the contents of the A
register if single precision is required, or A-AE
registers if extended precision desired. The contents
The normalize instructions are formally summarized
of the accumulator are considered arithmetic, and
as:
the shifts follow the rules of ASH or EASH operations.
Single Precision
The count appearing'in the specified index register is
a positive quantity, so that the two instructions
NRM
~,
ASH
~, 2
NRM
~,x
for
(A)~~,
Arith.Single Prec.
left shift until [Ao] ~ [AI]'
positive count of shifts c -
2
(X).
for (A)=O, 0 - (X).
would leave the A register unchanged, but with the
number of shifts to achieve normalization in index
Extended Precision
register 2.
ENRM
NaTE
The criterion for normalization is that bits !1
and 1 of the A register must be different.
~,x
for (A)~~, Arith. Extend.
Prec. left shift until TAo] ~
[ A I], positive count of shifts
c-(X).
for (AAE)=O, O-(X)
2-31/2-32
CHAPTER 3
PRIORITY INTERRUPT SYSTEM
,searches for any interrupt signals. The order of
3.1 INTRODUCTION
scanning determines the priority of one interrupt conThe 8400 Interrupt System provides a means of inter-
dition relative to another. If an interrupt condition is
rupting a program sequence at the occurrence of some
detected by the scanner, and no higher priority Sig-
event, and executing a routine that corresponds to the
nals were detected, the interrupt logic generates an
event. Conditions both internal and external to the
unique address for that interrupt. At certain pOints
machine can cause interrupts. Hardware is provided
in the instruction cycle, the machine acknowledges
to maintain an assigned priority among the interrupt
the detected interrupt by breaking the program se-
conditions, and to maintain the priority while an inter-
quence, and executing the instruction at the location
rupt routine is in progress.
specified by the interrupt logic.
When the machine is
interrupted, the continuity of the instruction sequence
is preserved, and interrupt routines as small as one
instruction can be used.
The Enable Flag, E, can either enable or disable
all signals from the interrupt registers. When the E
flag is reset (set to zero, disabled, turned off), no
3.2 BASIC OPERATION
interrupt condition can be acknowledged, except upon
power failure, and the program, sequence cannot be
The elements of the interrupt system are as follows:
1.
A 16-bit Internal Interrupt Register with
associated decoding logic and scan circuits.
2.
3.
interrupted. Instructions pertaining to the flags are
discussed in Chapter 2.
The interrupt registers themselves cannot be disabled.
Up to sixteen 16-bit External Interrupt
.An interrupt condition will always set the correspond-
Registers with associated decoding logiC
ing bit in the interrupt register independent of the E
and scan circuits.
flag and the mask bits.
The Enable Flag in the Flag Register denoted by (E).
The interrupt registers
provide a buffer to remember the occurrence of
.~
interrupt conditions until the interrupt logic can ac,knowledge the signal. Depending on the type of inter-
4.
5.
6.
A 16-bit Internal Mask Register denoted
rupt routine used, a bit in the interrupt register is
by (IMR).
reset either automatically when the interrupt condi-
A 16-bit External Mask Register denoted
tion is acknowledged or is reset by program. Figure
by (EMR).
3-1 shows the interrupt register mask configuration.
An additional external mask bit denoted
by (EMB).
3.3
PRIORITY
When an interrupt condition occurs, a bit correspond-
There are two aspects in determining the interrupt
ing to that condition is set in one of the interrupt
priority of specific interrupt requests:
:registers. If the enable flag E and the Mask bit
corresponding to that position in the interrupt regis-
1.
When multiple interrupt conditions occur
ter are set, a signal is gated to the scan circuits. At
simultaneously, which condition will be
various points in the instruction cycle, the scanner
first acknowledged by the system?
/3-1
Table 3-1. Memory Locations (Cont)
ICO SET
Octal
Decimal
Interrupt Name,
45
37
Memory Protect
46
47
38
39
Console
50-57
40-47
Data Channels 0-7
60-77
48-63
External Group
1
100-117
64-79
External Group
2
120-137
80-95
External Group
3
140-157
96-111
External Group
4
160-177
112-127
External Group
5
200-217
128-143
External Group
6
220-237
240-257
144-159
160-175
External Group
External Group
7
8
260-277
176-191
External Group
9
300-317
192-207
External Group 10
320-337
208-223
External Group 11
RESET
ICI SET
RESET
IC2 SET
}
RESET
CONTROL
SIGNALS
ICI5 SET
1.115
L
......!ANd' GATES
FLIP FLOPS IN THE INTERRUPT
REGISTER
:~~} INTERRUPT
CONDITIONS
MO} MASK BITS
1.115
E
}
ENABLE
FLAG
Figure 3-1. Interrupt Register Mask
Enable Configuration
2.
Timer
340-357
224-239
External Group 12
Once an interrupt has been acknowledged,
360-377
240-255
External Group 13
an interrupt routine is in progress, what
400-417
256-271
External Group 14
conditions will cause that routine to be
420-437
272-287
External Group 15
interrupted?
440-457
288-303
External Group 16
Regarding the first, the scan action of the interrupt
detection logic determines which interrupts take pre-
The first 16 interrupts (highest priority) are internal.
cedence over other interrupts. That is, if conditions
All remaining interrupts are called interrupts. The
occur simultaneously, the scan determines which
first 6 interrupts refer in some way to the instruction
will be acknowledged first. This feature of the inter-
sequence. The meaning of all internal interrupts is
rupt system is referred to as hardware priority. The
explained in Paragraphs 3.7.
memory locations associated with the interrupts
Once an interrupt has been acknowledged, there are
reflect the hardware priority. The highest priority
two methods by which a given priority can be main-
interrupt has the lowest memory location as shown in
tained for the duration of the interrupt routine. One
Table 3-1.
method is through the use of the mask registers. By
manipulation of the mask registers, any priority
Table 3 -1. Memory Locations
sequence - not necessarily the same as hardware
priority - can be achieved and maintained. Pr ogrammed
Interrupt Name
Octal
Decimal
40
32
41
33
Data Exec
42
34
Illegal Instruction
43
35
Instruction Exec
44
36
Exponent Fault
. Power Failure/Memory Parity
Error
priority allocation is discussed in Paragraph 3. 5, If
the hardware priority sequence is acceptable to the
user, this priority will be maintained automatically
for the duration of an interrupt routine by the hardward. If certain programming rules are observed.
The automatic maintenance of hardward priority is
discussed in Chapter 4.
3-2
3.4 INTERRUPT CONTROL
A link instruction serves to inform the interrupt system that an interrupt route is being initiated. When
Interrupts can be acknowledged only at certain times
during the instruction sequence:
1.
After gathering of instruction,
2.
After each level of address modification,
and
3.
After the execution of an instruction.
The actual execution of an instruction can never be
interrupted. Also, interrupts can never occur at the
following times:
1.
When executing the first instruction of an
interrupt routine,
2.
3.
After the machine has been halted from
console, and
When the E flag is reset.
the link at the interrupt location is executed, the
system enters a scan-limiting state, and the interrupt condition is not reset. Once in the acknowledged,
but not reset state, the scan is limited so that only
interrupts of higher priority can be acknowledged.
The use of the link instructions, therefore, permit
the hardware priority to be maintained for the duration of an interrupt routine.
The Jump Trigger (JT) instruction is the means by
which a program informs the interrupt system that
an interrupt routine has been completed. If the system is in a scan-limiting state, and a JT instruction
is executed, the system then resets the highest priority interrupt condition that has been acknowledged
but not reset. There are three states for each type
of interrupt.
1.
Idle; no interrupt condition present.
2.
Set; an interrupt condition has set the bit in
the interrupt register, but the condition has
An exception to the above is the po~er failure interrupt which has the highest hardware priority. This
interrupt can occur, independent of its mask bit and
the E flag, during auto load or auto dump and after
the machine has been halted manually.
not yet been acknowledged.
3.
Acknowledged but not reset; a link instruction at the interrupt location was executed,
and no JT instruction has yet been executed.
When an interrupt is acknowledged, the machine is
forced to execute the instruction at the interrupt
The possible states of the interrupt system are shown
location. The interrupt location address is not placed
in Figure 3-2. While an interrupt is in the acknowl-
in the .location counter. The resulting action depends
edged state, no more interrupt of that type can be
on the type of instruction at the interrupt location.
received until the JT instruction is executed. The
The four possible cases are as follows:
bit in the interrupt register remains set until the
JT is executed. If no interrupt is in the acknowledged
1.
Link instructions (L or LR).
state, then JT instructions have no effect on the
interrupt system.
2.
Jump instructions (J, JS, JR, JT, HJ,
XJ, XJT, LDL).
The link JT technique for interrupt routines provides
Execute instruction (EX).
priority without resorting the mask manipulation. An
multi-level interrupt capability with the proper
3.
example of multi-level interrupts is shown in Figure
4.
other instructions.
3-3. For each interrupt routine, the use of the lin
3-3
Note that the resetting of the interrupt is independent
of any flags associated with the JT instruction. For
the instruction JTf, where f is some flag, the following occurs:
OCCURENCE
INTERRUPT
CONDITION
1.
The jump is performed if flag f is true.
2.
Flag f is triggered unconditionally.
3.
The highest priority acknowledged interrupt is reset unconditionally.
EXECUTING A LINK AT
THE INTERRUPT LOCATION
When the instruction executed at the interrupt location
is not a link, the interrupt conditions is automatically
Figure 3-2. Interrupt States
reset. If the instruction is not a jump type instruction
that alters the location counter, the interrupt instruction is then executed as a one-instruction interrupt
routine. The return is made to the interrupted program to insure that no instructions will have been
missed.
If the instruction at the interrupt location is a jump
instruction, the interrupt is automatically reset, and
the jump is executed. Since the location counter is
loaded with a new address, the location counter value
at the time of the interrupt is lost. In this case, it
is impossible to determine by program at which
point the program was interrupted.
INTERRUPT
ROUTINE
WITH PRIORITY
P2>PI
MAIN
PROGRAM
INTERRUPT
ROUTINE
WITH PRIORITY
P3 > P2
Should the instruction at the interrupt location be an
Execute (EX), the resulting action depends on the
object of the Execute instruction. The interrupt condition is reset automatically, independent of the object
instruction unless it is a Link. If multiple Execute
instructions are chained together, the entire chain,
including the object instruction, is non-interruptable .•
Figure 3-3. Multi-LevelInterrupts
Interrupts that refer to machine instructions (interinstruction guarantees that only higher priority inter-
rupts 0-5) are handled in a special way. If one of
rupts can occur while the routine is in progress.
these interrupts is acknowledged either after gather-
When the routine is complete, the use of the JT
ing of instruction or after address modification, the
guarantees that the status of the interrupt system
location counter is incremented by one before the
before the interrupts will be re-established.
instruction at the interrupt location is executed.
3-4
For example, if an illegal instruction at location L
instructions pertaining to the mask bits are the
causes an interrupt after gathering instruction the
following:
following occurs:
m
LDM
1.
Load the Internal Mask Register
"
with a hali-word from memory.
With a link instruction at the interrupt
location, the address L + 1 is stored at
the effective address of the instruction.
m
LDE
Load the External Mask Register
a half-word from memory.
2.
With a non-link, non-jump instruction,
Options:
*, X, /, =
Flags:
none
return would be made to L + 1, after
execution of the one instruction routine.
A personalized interrupt is one in which a transfer
STM
m
Store the contents of the Internal
of control takes place immediately, should the inter-
Mask Register into a hali-word in
rupt condition arise, where immediately means
memory.
following the execution of the instruction currently
being obeyed.
m
STE
Store the contents of the External
Mask Register into a hali-word in
memory.
This is critical for such interrupts as "unvalid
instruction".
On the other hand, other interrupts
cause the transfer of control to take place one in-
Options:
*, X, /
Flags:
none
struction later than this and this is satisfactory for
interrupts generated externally.
SFL
='60, , 0
SFL
=
However, the 8800 interfacy busy interrupt is not
personalized, and so the occurrence of an 8800
'61,,0
Set the external mask bit (EMB)
Reset the external mask bit (EMB)
instruction which causes an 8800 busy interrupt to
occur, causes the interrupt routine to save the
address of the instruction after the one that caused
the interrupt to occur. It is wise therefore for the
The B flag is set following either SFL instruction if
the EMB was set prior to the instruction.
programmer to follow every 8800 interface instruction that can result in an '8800 busy' interrupt, by a
= '60, 00
TSL
Test the external mask bit (EMB)
NOP. If the interrupt occurs the address of the NOP
will be saved, and the interrupt routine can occur
properly.
The Z flag is set following this instruction if the EMB
was set, and the flag is reset if the EMB was not set.
Dynamic priority allocation can be achieved by using
3.5 MASKING
the masks in the following way:
If some priority sequence other than the hardware
priority is needed, masking must be used.
For
1.
Determine for each interrupt condition
those interrupts with individual mask bits, any
which of the others are to have higher or
sequence of priority can be achieved.
lower priority.
The
3-5
2.
During the main program, keep all mask
The Reset Monitor mode instructiop., in addition to
bits set and all interrupts enabled, and
placing the machine in :usermode, also enables the
interrupt system. Once in user mode, the interrupts
perform a JT instruction to release the
machine from its limited-scan control
state.
cannot be disabled. The interrupts can then be disabled only after an interrupt has occurred, and the
machine has been returned to monitor mode.
3.
Store the existing mask registers; then
change the masks so that only bits for in-
Instructions that cannot be executed in user mode are
terrupts of priority greater than the given
called privileged instructions. They are:
interrupt (in the new sequence) are set.
4.
5.
1.
LDT, LDM, LDE, LDC
and execute the interrupt routine.
2.
SFL, TSL
When the interrupt routine is completed,
3.
LDOB, STm
the interrupts should be disabled, the
original masks restored, and the interrupts
4.
LDCD, STCD, LDCC, STCC
5.
HJ
Set the E flag to re-enable the interrupt
again enabled before returning to the point
that was originally interrupted.
3.6 USER/MONITOR MODE AND THE INTERNAL
INTERRUPTS
When one of these instruction is attempted in user
mode, the instruction is not executed, a privileged
instruction flip-flop is set, and an interrupt is generated. The privileged instruction flip-flop can be
3.6.1 User/Monitor Modes
Every 8400 is equipped with a feature to facilitate
tested and reset with the following instructions:
SFL
= '21,,0
Reset Privileged Instructions
TSL
= '21n 0
Test Privileged Instructions
multi-programming and time sharing. 'rhe User/
Monitor mode feature prevents a user program from
interfering with the continuous operation of the computer. In USer mode, any instruction that initiates
input/output operations or modifies the state of certain control register is not executed. In monitor
mode all instructions are permitted.
Other illegal instructions generate this interrupt as
usual, but do not set the Privileged Instruction flipflop.
Since the interrupt system cannot be disabled in user
The monitor mode flip-flop controls the mode of the
mode, instructions that refer to the E flag in the flag
computer. The machine is placed in monitor mode
register are not allowed to change its state. Instruc-
when any interrupt occurs, or by the INITIALIZE
tions of this type are executed, but do not affect the
button from the console. The flip-flop can be reset
E flag, as shown by the following:
and tested by the following instruction:
Instruction
SFL
TSL
3-6
= '65,,0
= '65,,0
Reset Monitor Mode
Test Monitor Mode
Acts Like
JSE
JE
JSNE
JNE
JRE
JE
lns true tion
Acts Like
JRNE
JNE
LRE
LE
LRNE
JTE
LNE
If the voltage level varies beyond a safe limit, a
JE
power failure interrupt is generated. Memory parity
JTNE
JNE
Interrupt Mask:
Does not affect this
interrupt.
is checked whenever the memory is accessed either for normal program execution or for the auto-
In user mode, the LDF instruction does not change
matic data channel operation. Both power failure
the E bit, and the JT instruction has no affect on the
and memory parity error are considered catastrophic.
Restart may be from the beginning of the present job
interrupt system.
or from the last SAVE point in the job. The following instructions are used to determine cause: TSL =
3. 6. 2 Internal Interrupts
'23" 0 for Test Memory Parity Failure, and SFL
Tne internal interrupts are summarized in Figure
=
'23,,0 for Reset Memory Parity Failure.
3-4. The interrupt number represents the bit number for the corresponding bit in the Mask Register.
(1) Interrupt Name:
Data Exec
The lowest number has the highest priority. Each
interrupt is discussed in detail below.
Power failure and memor:y
parity error interrupt.
(0) Interrupt Name:
Interrupt Location:
'41
Internal Mask:
'40000
The Data Exec interrupt is set for any gathering of
Interrupt Location:
o
'40
data in the monitor mode of a word with the left Exec
(POWER FAILURE)+(ANY READ)(MEMORY AIIRITY FAILURE)
(DATA FETCHi(RIGHT EXEC)(USER MODE)HLEFT EXEC)
(MONITOR MODEl]
2
UNSTRUCTION FETCHi(PRIVILEGED INST)(USER MODE)
+ULLEGAL INST)HLDCC+STCC)(NO ADCP~
3
(INSTRUCTION FETCH)(RIGHT EXEC)(USER MODE)
4
EXPONENT OVERFLOW
5
PROT
(USER MODE)(ANY WRITE)(RIGHT EXEC)(MEMORY PROTECT
ENABLE)HMEMORY ACCESS)(ADDRESS OUT OF
MEMORY)
TIMER
TIMER DECREMENTED TO ZERO
6
MEM
7
CONsa.E INTERRUPT BUTTON DEPRESSED
8
DATA
CHNO
9
DATA
CHNI
10
\I
12
OR UNDERFLOW
DATA
CHN2
DATA
CHN3
DATA CHANNEL INTERRUPTS
(SEE CHAPTER 5 FOR DEFINITION OF INTERRUPT
CONDITIONS)
13
14
15
Figure 3-4. Internal Interrupt Conditions
3-7
bit set, or in user mode of a word with the right
(4) Interrupt Name:
ExPonent Fault
Exec bit set.
Interrupt Location:
' 44
Internal Mask:
'04000
Exceptions: TEX, LDCC, LDCD, LDOB.
The cycle of instruction gathering lasts until the effective address has been fully calculated, including
This interrupt is generated by a floating-point expo-
indirect addressing and indexing. Instructions that
nent exceeding the proper range as the result of some
have operands in a memory location given by the ef-
floating-point operation. The proper range for expo-
fective address, have a data gathering cycle that fol-
nents is -128 :s Exp:s 127. Exponent overflow does
lows the instruction gathering cycle. Immediate
not inhibit a floating-point operation.
instructions do not have a data gathering cycle.
(5) Interrupt Name:
(2) Interrupt Name:
Interrupt Location:
Internal Mask:
Memory Protect
Illegal Instruction
Interrupt Location:
'45
Internal Mask:
'02000
'42
'20000
This interrupt results when an instruction tries to
In general, any instruction that is undefined or would
result in stopping machine operation will cause this
interrupt. Immediately after gathering instruction
the interrupt is generated and the instruction is not
executed. The following specific instructions cause
this interrupt:
modify any half-word, full-word, or Exec bit in a
protected area of memory. Specifically, this interrupt occurs on a store instruction, in user mode, if
and only if the right Exec bit is set at the location and
the memory protect mode has been enabled for that
memory bank. The memory protect mode can be enabled and disabled individually for up to four memory
banks. The instructions pertaining to the memory
1.
Undefined OP codes
2.
STCC or LDCC when no Automatic Data
Channel Processor is present
3.
Privileged instructions in user mode
(3) Interrupt Name:
protect mode are the following:
Test
Set
Reset
Bank 1
TSL ='40,,0
SFL = '40, ,0
SFL='41,,0
Bank 2
TSL = '42,,0
SFL ='42,,0
SFL='43,,0
Bank 3
TSL = '44, ,0
SFL = '44,,0
SFL ='45,,0
Bank 4
TSL ='46,,0
SFL = '46, ,0
SFL ='47, ,0
Instruction Exec
The SFL instructions set the B flag if the specified
Interrupt Location:
'43
mode control was set prior to the SFL action. The
TSL instructions set the Z flag if the specified mode
Internal Mask:
' 10000
control was set, and reset the Z flag if the control
was reset.
This interrupt is generated following instruction
gathering in user,. mode if the right Exec bit at the
This interrupt will also occur if memory is refer-
location of the obtained instruction is high. The
enced by an illegal address (for example, an address
instruction is not executed.
out of memory). If an instruction attempts to access
3-8
memory with an illegal address, the memory access
value in the Timer Register, and decrementing pro-
is bypassed, the instruction cycle is completed, and
ceeds from there.
the interrupt is generated.
Console
(7) Interrupt Name:
Timer
(6) Interrupt Name:
Interrupt Location:
Internal Mask:
Interrupt Location:
'47
Internal Mask:
'00400
' 46
'01000
The console interrupt is generated when anyone of
The interval timer is an optional feature on the 8400,
the four console interrupt buttons (CI1-CI4) is de-
and this interrupt cannot occur on those machines
pressed. Each button is buffered with a flip-flop as
without a timer. This interrupt occurs when the
shown in Figure 3-5. Pushing the button sets a cor-
timer is decremented to zero.
responding flip-flop, and generates the interrupt.
An indicator in the button lights when the flip-flop is
The basic element of the timer is the 16-bit Timer
set. The flip-flops can be tested and reset by pro-
Register. The following instructions pertain to the
gram to determine which of the buttons caused the
timer:
interrupt. When the flip-flop is reset, the indicator
light goes out. The instructions related to the con-
m
LDT
Load the Timer Register with a
sole interrupt are listed below:
half-word from memory
TSL
= '25" 0
Test Console - Interrupt 1
half-word in memory.
SFL
='25,,0
Reset Console - Interrupt 1
Options
*, X, /,
TSL '='27,,0
Flags:
none
SFL
~'27"O
Reset Console - Interrupt 2
TSL
='31,,0
Test Console - Interrupt 3
m
STT
Store the Timer Register into a
=
SFL
= '62,,0
Start the timer
TSL
= '62,,0
Test the timer
SFL
= '63,,0
Stop the timer
Test Console - Interrupt 2
The B flag is set following the SFL instructions if the
timer was operating prior to the SFL; the Z flag is
set follOWing the TSL if the timer was operating.
Once the timer is operating, the Timer Register is
decremented every millisecond. Decrementing continues until the timer is stopped with the appropriate
SFL instruction. Note that the timer runs while the
machine is in a manual halt condition. After zero is
reached, the next decrement produces the maximum
Figure 3-5. Console Interrupt Buttons
3-9
SFL
='31,,0
TSL
=
SFL
= '33, , 0
'33, , 0
Reset Console - Interrupt 3
Test Console - Interrupt 4
Reset Console - Interrupt 4
Interrupt
Location
External Mask
(1, 5)
'65
'02000
(1, 6)
'66
'01000
(1, 7)
'67
'00400
(1, 8)
'70
'00200
(1, 9)
'71
'00100
The TSL instructions set the Z flag if the specified
(1, 10)
'72
'00040
flip-flop was set. The SFL instructions set the B
(1, 11)
'73
'00020
flag if the specified flip-flop was set.
(1, 12)
'74
'00010
(1, 13)
(1, 14)
'75
'00004
The JT instruction that resets the bit in the interrupt
'76
register has no affect on the flur flip-flops associated
(1, 15)
'77
'00002
'00001
with the console interrupts. Following a console interrupt, both the interrupt bit and the console flip-flop
must be reset before another console interrupt can be
generated.
For those machines with no more than four data
channels, the interrupts corresponding to channels
4-7 are available as external interrupts. In this
case, lines for these interrupts are available through
(8) - (15) Interrupt Name:
Interrupt Location:
Channel Interrupt
'50 - '57
the system interface. A response line is available
tl}rough the system interface that indicates when the
interrupt has been serviced.
The interrupts are set by a positive transistion in a
Internal Mask:
'00377
Each data channel has. one interrupt. Channel 0
corresponds to location '50, channell to '51, and so
signal. Therefore, either pulse or level Signals can
be used to generate external interrupts.
When a signal on an interrupt line is set, an inter-
forth. When a device is connected to a data channel,
rupt will occur. If the external signal maintains its
interrupts can result from the channel itself, or from
position level, no more interrupts will result from
the connected device. When no device is connected
that signal until it falls and is set again. A positive
to a channel, interrupts can result from those
transition is required for both internal and external
devices on the channel which have been properly
interrupts.
enabled.
3.8 CONSOLE INDICATORS
3.7 EXTERNAL INTERRUPTS
The conditions that cause external interrupts are a.
function of the external equipment tied to the interrupt
The following items pertain to the interrupt system:
1.
The INITIALIZE button on the console sets
lines. There are up to 16 groups of 16 interrupts.
all interrupts in the interrupt registers,
The external mask register pertains only to the first
returns all inter~upts to the idle state, and
resets the console interrupt flip-flops.
external group which is shown below:
Interrupt
3-10
Location
External Mask
(1, 0)
'60
'-00000
(1, 1)
'61
'40000
(1, 2)
'62
'20000
(1, 3)
'63
'10000
(1, 4)
'64
'04000
2.
The INTERNAL INTERRUPT indicator on
the console is lit when any internal interrupt is not in the idle state.
3.
The CHANNEL INTERRUPT indicator on the
console is lit when any channel interrupt is
not in the idle state.
CHAPTER 4
INPUT/OUTPUT SYSTEM
4. 1 INTRODUCTION
The input/output of the 8400 resides in the Exchange
Module which contains the following functional units:
1.
An Exchange Module Central CC5ntroller
(EMCC) with up to 8 bi-directional data
channels for buffered data transfer to a
number of devices.
2.
An Automatic Data Channel Processor
(ADCP) which automates the data channel
operation, provides direct memory access,
EMCC= EXCHANGE MODULE CENTRAL CONTROLLER
ADCP = AUTOMATIC DATA CHANNEL PROCESSOR
5.1. = SYSTEM INTERFACE
K = CHANNEL NUMBER
D = DEVICE NUMBER
and permits simultaneous input/uutput/
compute operations.
3.
Figure 4-1.
A System Interface which permits direct
Exchange Module
data transfer with external data handling
systems.
4. 2. 1 Function
Each peripheral device is provided with a device
The purpose of an 8400 data channel is to facilitate
controller which enables all devices to use the gen-
data transfers to or from peripheral devices with a
eralized data and control interface of the exchange
minimum of programming effort. Byte assembly
module.
and disassembly is provided for handling 4 and 8-bit
bytes. All transfers between memory and a channel
The operators desk, which uses the features of the
are made as 17-bit halfwords (16 data bits and Exec
Exchange Module, is discussed in detail in Chapter 5.
bit), while transfers between the channel and a device
can be in terms of 4, 8 or 16-bit bytes and an Exec
A functional representation of the Exchange Module
bit.
is shown in Figure 4-1.
Character buffering is provided so that character
devices need not have their own external buffer register.
4.2 DATA CHANNELS
Buffering is also provided for control signals
and error indicators so that all external devices can
be programmed and operated in a generalized and
Every 8400 is equipped with at least one data channel
and may be expanded to 8.
consistent manner.
Up to 15 devices can be
connected to each channel, although only one device
Code conversion circuitry is provided so that exter-
can be selected for data transfer at a given time.
nal devices which require a binary coded decimal
4-1
(BCD) code can be IUtndled as well as those that gen-
transferred to a device. During input, this
erate or accept the 8400 internal binary code. On
register holds an assembled half-word
input, the BCD code from a device is converted to.
which is to be stored in memory.
binary code, and on output, the internal binary code
is converted to the device oriented BCD code.
3.
Channel Buffer Register (CBR)
Parity generation and checking logic is provided for
This 8-bit register is the character buffer
4 and 8-bit byte transfers. On output, the parity bit
register to which the selected device is
is generated and sent with the data; on input, a parity
connected. With either 4-bit or 8-bit data
bit is generated and checked against the parity bit
transfers, 8-bit bytes are transferred
received with the data. With binary data transfers,
between the Channel Data Register and the
odd parity is used, and with BCD transfer, even
parity is used.
Channel Buffer Register. Assembly of 4bit bytes into 8-bit bytes, or disassembly
of 8-bit bytes into 4-bit bytes is performed
4.2.2 Structure
in the Channel Buffer Register. Parity
The data channel complex includes the Exchange
checki.ng and code conversion is also done
in conjunction with the Channel Buffer Reg-
Module Central Controller (EMCC) plus up to 8 indi-
ister. With l6-bit data transfers, data is
vidual channels. Associated with the individual data
transferred directly between the Channel
channels are the followi.ng elements:
Data Register and the selected device, bypassing the Channel Buffer Register. No
1.
parity checking or code conversion is pro-
Channel Function Register (CFR)
vided for l6-bit transfers.
This 8-bit register holds a code word which
specifies the type of operation to be per-
4.
Control indicators as follows:
formed on the channel--input or output,
Channel Read'), (CDRY) indicator is true
binary or BCD, 4, 8, or l6-bit bytes, etc.
Details of the Channel Function Register
whenever the Channel Data Register is
format are discussed with the SFL instruc-
ready to transfer a half-word to memory
tions. Associated with the Channel Func-
on input, or accept a half-word from
tion Register is the channel control and
device selection logic which actively con-
memory on output.
nects one device to the channel. It also
Channel Automatic (CHA) indicator is true
prevents the Channel Function Register
from being changed while a cha.nnel opera-
whenever the channel is under control of
tion is in progress.
Details of this indicator are discussed with
the Automatic Data Channel Processor.
the ADCP.
2.
Channel Data Register (CDR)
Channel Parity (CHP) indicator is set
4-2
This l7-bit (16 data bits plus one exec bit)
when either the channel or a selected de-
register represents the interface between
vice detects a parity failure during data
the data channel and memory. For output,
transfer; the indicator is reset by a TSL
the Channel Data Register can be loaded
instruction, or when a new channel opera-
with a half-word from memory to be
tion is initiated.
Channel Signal (CBS) indicator can be set
___
by the selected device on the channel when
!!PI~!....
____
certain conditions on the device exist. The
specific conditions that set CHS are different for each device, and are described in
the section pertaining to devices.
When the Channel Ready Interrupt (CHRI)
DCHB
D
indicator is true, a channel interrupt will
CBRY
CFR
be generated whenever the CHRY indicator
i
becomes true. The CHRI indicator, which
enables the interrupt, can be set by an SFL
T
instruction, and is reset by an SFL instruction.
DEVICE
When the Channel Signal Interrupt (CBSI)
indicator is true, a channel interrupt will
be generated whenever the CBS indicator
becomes true. The CBSI indicator, which
enables the interrupt, can be set by an
SFL instruction, and is reset by an SFL
COR=CHANNEL DATA REGISTER
CBR-QlANNEL BUFFER REGISlER
CFR=CHANNEL FUNCTION REGISTER
CHRY=CHANNEL READY
CHRI = CHANNEL READY INTERRUPT
CHSI = CHANNEL SIGNAL INTERRUPT
CHA CHANNEL AUTOMATIC
CHS CHANNEL SIGNAL
CHP= CHANNEL PARITY
CHD = CHANNEL DISCONNECT
CHB= CHANNEL BUSY
CBRY= CHANNEL BUFFER REGISTER READY
=
=
instruction.
Figure 4-2. The Elements of a Data Channel
Channel Disconnect (CHD) control is used
to implement the conditional disconnect
action.
The CHD control indicator is set
EMCC is an Exchange Assembly Register (EAR)
which serves the following purposes:
by an SFL instruction and reset when a new
channel operation is initiated. Disconnect
1.
All accesses to the Channel Data Registers
procedures are discussed with the SFL
are made through the Exchange Assembly
instructions.
Register. The Exchange Assembly Register acts as an intermediate buffer on all
A block diagram of a data channel is shown in Fig-
transfers between memory and the Channel
ure 4-2.
Data Register.
The Exchange Module Central Controller (EMCC) is
2.
With 4 or 8-bit byte operations, the as-
shared by all the data channels in the Exchange
sembly or disassembly of 8-bit bytes is
Module. The EMCC is available to only one channel
performed in the Exchange Assembly
at a time. A scan mechanism searches for activity
on the channels. When a request for EMCC action is
Register. The Excha.nge Assembly Register, therefore, also acts like an inter-
detected, the scan locks on the particular channel.
mediate buffer on all transfers between
When the required transfers are complete, the EMCC
the Channel Data Register and the Channel
is released and the scan continues. Included in the
Buffer Register.
4-3
3.
During 16-bit operations, the Exchange Assembly Register also is a buffer between
The SFL i.nstructions related to the data channels are
as shown on Figure 4-3.
the Channel Data Register and the selected
device. On output, when the device is
ready, data is transferred from the Chan-
device will be executed only if the channel is idle,
nel Data Register through the Exchange
and no device is already connected to the channel. If
Assembly Register to the device. Simi-
a device is already connected, the SFL will be re-
larly, on input, data from the device goes
jected and the B flag set. When the channel is not
through the Exchange Assembly Register
busy, the SFL performs three functions:
The SFL instruction for initialize channel/connect
to the Channel Data Register.
1.
Device D is logically connected to the
4.2. 3 Instructions
channel, and is initialized for data transfer.
Instructions required to use the data channels are
2.
All channel registers and indicators (ex-
described below:
cept for CHRI and CHSI) are reset to initial
conditions.
SFL
=M"l
Set a Function Line in bank
The Channel Function Register (CFR) is
3.
1 as defined by the effective
loaded with the 8 least sig.nificant bits of
address.
SFL address which specify the operation
TSL
=M"l
Test a Sense Line in bank
to be performed. These bits in the SFL
1 as defined by the effective
address.
address have the following meaning:
Bits
Options:
*
Flags
B for SFL instructions
E
Value
Operation
1
Exec bit transfer
o
No exec bit transfer
1
Binary transfer without code con-
Z for TSL instructions
B
There are four banks associated with TSL and SFL
version
instructions. The data channels are considered
bank 1, and any SFL or TSL instructions which refer
o
BCD transfer with code conversion
to the data channels or devices connected to the
channels should use the ba.nk 1 deSignation.
L
1
Left half for half-word transfers to
or from memory
Immediate addressing always must be used with all
SFL and TSL instructions. Indirect addressing and
0
indexing may also be used if desired.
The B flag is set following an SFL instruction if the
Right half for half-word transfers to
or from memory
specified function could not be performed; the B flag
The L bit of the CFR is to be complemented after each half-word
will be reset if the specified function was performed.
The Z flag is set following a TSL instruction if the
transfer to or from memory is com-
A
1
pleted
specified sense line or indicator was true; the Z flag
will be reset if the specified sense line is not true.
4-4
0
The L bit is not to be complemented
Bits
I
N
The SFL Channel Clear instruction is an unconditional
Operation
Value
command; this instruction will disconnect the selected
1
Input operation
0
Output operation
0
Transfer E bits only
1
Transfer 8-bit bytes, one per half-
device and terminate any current operation, regardless of the state of the current operation.
devices connected to the channel will be reset.
whether or not the device was selected when the SFL
word
word
This instruction is similar to the
console initialize control, but it affects only one data
connect command is properly used, the unconditional
disconnect need not be used except in error routines.
Care should be exercised in the use of this instruc-
Transfer 4-bit bytes, four per half-
3
was executed.
channel, rather than all channels. If conditional dis-
Transfer 8-bit bytes, two per half-
2
All chan-
nel indicators will be reset, and all indicators· on
tion to avoid interfering with valid channel operations.
word
The SFL Disconnect instruction sets the CHD control
4
Transfer 4-bit bytes, four per half-
indicator in the channel.
The CHD indicator being
word
set causes a disconnect action which is conditional
on the state of the channel as follows:
Transfer 4-bit bytes, one per half-
5
word
1.
If an output operation is in progress (I
= 0),
then the device will be disconnected when
6
Transfer 4-bit bytes, two per half-
the channel is ready (CHRY = 1). This
word
feature permits the channel to complete
the transfer of. its current half-word be-
Transfer 4-bit bytes, three per half-
7
fore disconnecting the device.
word
Details of the byte assembly/disassembly are discussed later. None of the remaining SFL instructions
= 0) and
an input operation is in progress (I = 1),
are ever rejected.
then the device will be disconnected im-
2.
If the ADCP is not in control (CIlA
mediately when CHD gets set.
EFFECTIVE ADDRESS
FUNCTION
INITIALIZE CHANNELl
CONNECT DEVICE
III K I D
CHANNEL CLEAR
I
CHANNEL DISCONNECT
SET CHANNEL READY
INTERRUPT (CHRI)
RESET CHANNEL READY
INTERRUPT (CHRll
SET CHANNEL SIGNAL
INTERRUPT (CHSt)
RESET CHANNEL SIGNAL
INTERRUPT (CHSII
IEIBIYAlII :N:
I
II 10000 Ixlxl~~xI3xjxl
pi
10000Ixlxl~+0xl'l
K
101 K 10000 IxlxlXl~xl~ II~
@K 10000 Ixlxl3xIXI I Ixlxl
@ loooolxlxlifl'13x!X1
pi K 10000 ~lx~II l~xlXlXI
K
01
34
7891011121514111
WHERE' K = CHANNEL NUMBER 0-7
D
= DEVICE
NUMBER
3.
If the ADCP is in control (CIlA
K
1-15
x= cp UNLESS COMBINED
OPERATIONS NEEDED
= 1), and
= 1),
an input operation is in progress (I
then the device will be disconnected immediately after the next transfer into
memory.
This feature permits the use of
SFL disconnect to terminate an ADCP operation in the middle of a block transfer
without lOSing a completely assembled
half-word.
The data transfer operation
can be resumed and completed later. provided that the channel control word is
Figure 4-3. Data Channel SFL Instructions
saved (using an STCC instruction).
4-5
The TSL instructions related to the data channels are
shown
OQ
FUNCTION
EFFECTIVE 4DDRESS
TEST CHANNEL SIGNALlCHSllOI K foooFlxl*lxFI~11
Figure 4-4.
III
The Z flag is set following a TSL instruction if the
~1lAtN(~H~AR CHANNEL
specified indicator is true, and reset if the indicator
TEST CHANNEL
is not true.
~,.¢N~H~~EAR CHANNEL III K lOoooElxMXFlxl'l~
PARITY
K lOoooFFlflxlxlxl'l
(CHP) 101 K 10 00 oElxHX§§I, H
TEST CHANNEL REAOY(CHRYllOI K pooo\x~I+HpClXj
The instructions pertaining to the Channel Data
Register are the following:
TEST CHANNEL AUTOMATIC 101 K lOooOlXlx\XIxlllXlxlxl
(CHAI
0 I
54
71
III
LDCD
WHERE'K = CHANNEL NUMBER 0-7
X = ¢ UNLESS COMBINED OPERATIONS NEEOED
M"K
Load the Channel Data
Register in channel K with
Figure 4-4. Data Channel TSL Instructions
a half-word at the effective
address. The L bit in the
4.2.4
Programming
Channel Function Register
in the channel determines
whether the right half or
left half of the word at the
The various modes of data transfer which can be
achieved with the data channel are as follows:
1.
effective address will be
Program controlled data transfer without
interrupts.
used.
2.
STCD
M"K
Store the contents of the
Channel Data Register in
Pragram controlled data transfer using
interrupts.
3.
Autamatic data channel transfers.
4.
Auto load or auto dump operations.
channel K into the halfword at the effective address.
The L bit in the
Channel Function Register
Auto. load and auto dump operations are discussed
determines whether to
under console operatians.
store into the right half or
operatians are discussed in Paragraph 4. 3.
Automatic data channel
left half.
In program controlled operations, data is transferred
Cha.nnel:
K
Options:
*
= channel number
0-7
between memory and a data channel by executing
LDCD or STCD instructions.
The general sequence of instructions required for
Flags:
None
program controlled transfers without interrupts is the
following:
For both LDCD and STCD instructions, the computer
waits for CDRY to be true before executing the transfer.
will be executed.
Initialize the channel and connect a device
with an appropriate SFL instruction.
If a given Data Channel is under ADCP control
(CRA is true), no instruction to that Data Channel
4-6
1.
2.
Test the B flag to make sure the channel
command was nat rejected.
3.
4.
Transfer half-words to or from the data
The basic programming sequences are illustrated in
channel using LDCD or STCD instructions.
Figure 4-5.
Test channel or device conditions using
appropriate TSL instructions.
4.2.5
Byte Assembly/Disassembly
The Exchange Assembly Register (EAR) handles the
5.
Terminate the operation and disconnect
assembly of 8-bit bytes into half-words on input. and
the device with a SFL disconnect instruc-
the disassembly of half-words into 8-bit bytes on
tion.
output. When the exec bit is transferred with a halfword, it is treated like an additional 8-bit byte dur-
Since LDCD and STCD instructions are not executed
ing assembly or disassembly. The Channel Buffer
until the channel is ready (CHRY
Register handles the assembly of 4-bit bytes into
=
1), no special
timing considerations are required to transfer the
8-bit bytes on input. and the disassembly of 8-bit
data. The transfer i.nstructions will be executed at
bytes into 4-bit bytes on output.
a rate determined by the speed of the selected device.
For relatively slow peripheral devices, this method
of data transfer can be inefficient.
All possible variations for byte size/byte count are
shown in Figure 4-6. Note that bytes are right
justified and left precedent within the half-word.
The use of the channel interrupt capability frees the
processor for other tasks during the time that the
That is, the left most byte to be transferred will always be transferred first. The numbers in the
data channel is not ready for a transfer to or from
figure refer to the order of bytes transferred to or
memory. The general sequence of instructions
from the device.
required to achieve program-controlled output with
interrupts is the following:
1.
Initialize the channel and connect a device
with an appropriate SFL instruction; test
the B flag to assure that the SFL was accepted.
2.
Set C HR.I to enable a channel ready interrupt and proceed with processing task.
Note steps 1 and 2 may be inter-changed
if desired.
3.
When the channel interrupt occurs due to
the channel becomi.ng ready. transfer a
half-word to or from the channel with an
LDCD or STCD instruction. If more
transfers are needed, return to the
processing task.
4.
Repeat the interrupt procedure until all
WITHOUT INTERRUPTS
WITH INTERRUPTS
data is transferred; then execute an SFL
channel disconnect to terminate the process.
Figure 4-5. Program-Controlled Data Transfer
4-7
~
£.=..L
~J TRANSFER [I
o I
BITS
tion is completed or intervention by the processor.
Q
n
1
2
1
1
1 I
1
N=1 TRANSFER B BIT BYffs!- I PER HALFWORD
01213J
011121
N=2 TRANSFER 8 BIT BYTES -2 PER HALFWORD
8
8
0
1
2
N=3 TRANSFER 16 BIT BYTES
JRANlFEJ
When referring to separate memory banks, the ADCP
and processor operate at full speed without interaction from one another. Concurrent requests from
the ADCP and the processor to the same memory
12 1 3 1 4 1 5 1
0
11 1 2 1 3 1 4
N=4 TRANSFER 4 BIT BYTES-4 PER HALFWORD
[~lJ
8
data transfer continues autonomously until the opera-
~ LJ~~L bLJwJ~
D
1
D
bank are handled on a cycle stealing baSiS, with the
ADCP having priority. The presence of the ADCP
option does not preclude program controlled operations on a data channel.
111 2 1 3 1
111112
N=6 TRANSFER 4 BIT BYTES-2 PER HALFWORD
~N- ~
12 1 3 14
11 1 1 2 1 3
TRANSFER 4 BIT BYTES-3 PER HAL.FWORD
BYTE SIZE / BYTE COUNT VARIATION
N =BYTE SIZE / BYTE COUNT FIELD OF THE
CHANNEL FUNCTION REGISTER
Figure 4-6. Byte Size/Byte Count Variation
4. 3. 2
Structure
The ADCP involves the following elements:
1.
One 32-bit Channel Control Register (CCR)
for each channel. These registers are
arranged in a high speed integrated circuit.
All bits to the left of the first byte transferred will
be set to zero on input, and ignored on output.
2.
A 32-bit Exchange Control Register (ECR)
which holds the control word for the opera-
4.2.6 Code Conversion
tion currently in progress. All accesses to
the CCR stack are made through ECR.
The code conversion controlled by the B bit in the
Channel Function Register, converts binary to BCD
on output, and BCD to binary on input.
The charac-
3.
Direct data and control busses between
the Exchange Module and memory.
ters of the 8400 character set and the corresponding
binary and BCD codes are shown in the Appendixes.
4.
4.3
AUTOMATIC DATA CHANNEL PROCESSOR
One Channel Automatic Indicator (CHA)
for each channel. The CHA is set whenever the CCR is loaded with a new com-
4. 3. 1
Function
mand and reset whenever the channel is
cleared or disconnected.
The Automatic Data Channel Processor (ADCP) is
an optional expansion to the Exchange Module. This
feature permits automatic transfer of data blocks,
direct access to memory from the Exchange Module,
as well as simultaneous program execution and data
transfer.
4.3.3
Control Words
The contents of the Channel Control Register (CCR)
specifies the type of data transfer operation to be
performed. In general, data is transferred to or from
consecutive memory locations starting at some speci-
The ADCP, using its own set of control words, per-
fied location M. The length of the block to be transferred
mits data transfer, independent of the processor,
is controlled either by a count decrementing to zero,
between memory and an external device. Once an
or by the receipt of a signal in the data. The format
automatic data channel operation is initiated, the
of the Channel Control word is shown in Figure 4-7.
4-8
Table 4-1. OP Codes (Cont)
c
M FIELD
Mnemonic
Binary
OP-Code
OP-Code
SSD
where
0110
Function
Skip until signal is received,
then disconnect and
M
address of the first memory location involved in the transfer
OP
operation code which specifies how to
transfer the data, and how to terminate the
operation
C
count specifying the number of memory
locations involved in the transfer.
interrupt.
TSI
1010
received, then interrupt.
S81
0010
Skip until signal is received
and then interrupt.
Figure 4-7. Channel Control Word Format
For symbolic assembly purposes, the 32-bit control
Transfer until signal is
TED
1111
Tra.nsfer until either count
is zero, or signal is re-
word for the Channel Control Register is expressed
ceived, then disconnect and
as:
il!terrupt.
OP
M"C
SED
0111
Skip until either count is
zero, or signal is received,
The OP codes and their meaning are listed below:
then disconnect and interrupt
Table 4-1. OP Codes
TEl
Mnemonic
Binary
OP-Code
OP-Code
TCD
1101
1011
ceived, then interrupt.
Function
Transfer until count is
SEI
0011
zero, then disconnect and
0101
Skip until either count is
zero, or signal is received,
interrupt.
SCD
Transfer until either count
is zero, or signal is re-
then interrupt.
Skip until count is zero,
Note that an interrupt is generated following all
then disconnect and
ADCP operations.
interrupt.
TCI
1001
Transfer until count is
zero, then interrupt.
SCI
0001
The skip operation is useful for passing over a
block of data on input without tra.nsferring any information.
Skip until count is zero,
then interrupt.
The count refers to the number of memory locations
involved in the operation. If an alternate mode is
TSD
1110
Transfer until signal is
used, then two half-word transfers constitute a count
received, then disconnect
of one. If non-alternate mode is used, then each
and interrupt.
half-word transfer corresponds to a count of one.
4-9
The signal refers to those conditions appropriate to
code conversion/no code conversion
the selected device that would set the signal flip flop
left half first/right half first
(CHS) in the channel.
alternate/no alternate
to memory/from memory
The Channel Control Register is loaded with a control word using the instruction
byte size
byte count
LDCC
M"K
The Channel Control Register is loaded with an LDCC
instruction which also sets the Channel Automatic
where
Indicator. Once the channel is initialized and Channel
Automatic Indicator is set, the channel operation is
K
channel number 0-7
under ADCP control and the processor is no longer
M
location in core memory of the 32-bit control
required.
word to be loaded into the CCR.
The LDCC instruction can either precede or follow the
SFL instruction for channel initialization. Before
The contents of the Channel Control Register can be
.initiating a new ADCP operation it is important to
stored using the instruction
check that the channel is not busy on a previous ADCP
request. An appropriate instruction sequence is as
STCC
M"K
where
K
follows:
SFL
JB
=CFCODE" 1
=*-1
= channel number 0-7
LDCC =CCWORD" K
INIT CHANNEL
TEST IF CHANNEL
BUSY
LOAD CCR
location in core memory in which the 32 bits
M
of the CCR should be stored.
4.3. 4 Operation
An alternate sequence is as follows:
TSL
JZ
LDCC
Initiating an ADCP operation on a data channel in-
SFL
=CHA"l
*-1
CCWORD, , K
=CFCODE, , 1
TEST AUTOMATIC
WAIT IF CHA SET
LOAD CCR
INIT CHANNEL
volves two steps:
Once the Channel Automatic Indicator is set and the
1.
Initializing the channel and connecting a
channel is initialized, all transfers to/from memory
device
are under ADCP control. The instructions LDCD and
STCD cannot be executed by the processor when the
2.
Loading the Channel Control Register with
Channel Automatic Indicator is set.
a control word.
If the transfer is in non-alternate mode, the M field
Channel initialization is performed by the channel
is incremented and the C field decremented after
SFL instruction which specifies the following:
every transfer to/from memory. If the transfer is in
alternate mode, the M field is incremented and the C
field decremented after every second transfer to/from
memory, independent of the initial L/R bit in the
Channel Function Register.
channel number
device number
exec bits/no exec bits
4-10
The Channel Control Register is updated immediately
following the transfer to or from memory. The se-
7.
Depressing AUTO DUMP pushbutton on the
console.
quence of operations is summarized in Figure 4-8.
When an operation is terminated, the Channel Control
ADCP OPERATION INITIATED
IS C '" 0 ?
the operation was completed. The STCC instruction
YES
can be used following an ADCP operation to examine
the contents of Channel Control Register. Note that
TRANSFER HALFWORD
ALT-ERNATE MODE?
NO
~~0:J
M-M+I
C-C-I
DISCONNECT AND
GENERATE INTERRUPT
C
M
= COUNT
= MEMORY
Register is not changed; it remains as it was when
when reading, there is a half-word uncertainty--as
measured by the remaining count in Channel Control
Register--as to how many words were transferred
to memory.
On termination, if disconnect was specified, the
~
Channel Disconnect (CRD) flip-flop is set. The data
channel and device are disconnected after the current
ADDRESS
half-word transfer is complete. For details on the
disconnect action, refer to the section on operation
Figure 4-8. ADCP Action jor a TCD Operation
of the Exchange Module.
Note that if a device is selected to read or write, and
If an SFL for conditional disconnect is executed dur-
an ADCP count operation is started with the count
ing an ADCP input operation, the operation is stopped
zero, a record of information could be skipped on the
after the next complete half-word transfer. If an
external device. Care should be exercised in ini-
SFL for channel clear is executed, the ADCP opera-
tiating operations with the count zero.
tion is terminated immediately and all channel indicators are reset.
An ADCPoperation can be terminated in several ways:
1.
The count in the Channel Control Register
Note, that after reading data with a TCI and TCD
reaching zero while a count operation is in
operation, the SFL conditional disconnect waits for
progress.
the next transfer before disconnecting the device. If
no further data is to be transferred to the channel,
2.
A signal being detected in the data while a
an SFL channel clear must be used to disconnect.
signal operation is in progress.
3.
The processor executing an SFL instruc-
4.4 SYSTEM INTERFACE
tion for channel disconnect.
4.4.1 Function
4.
The processor executing an SFL instruction for channel clear.
5.
DepreSSing INITIALIZE pushbutton on
console.
The System Interface is designed for general communication to or from external devices where the
function of the data channel is not required nor appropriate. Means are provided for direct data trans-
6.
Depressing AUTO LOAD pushbutton on the
fer between the processor and the registers of ex-
console.
ternal devices. The capability for testing Signals
4-11
and setting conditions on external devices is also
and 7 are accessible through the interface. For
provided. This interface facilitates direct computer
control with a variety of system configurations.
machines with more than four data channels, these
interrupt lines are not available for use with the system interface.
4. 4. 2 Structure
All operations with the system interface operate on
The elements of the system interface are the follow-
an asynchronous request/response/release basis with
ing:
the external device. The general sequence of events
during one operation is as follows:
1.
A 17-bit data output buss
1.
2.
A 17 -bit data input buss
3.
A 4-bit address field R
4.
Up to 256 external interrupt lines
5.
Command and control lines
6.
The outputs from four system control but-
The processor generates a request signal
(input or output command) signal to the selected device, as defined by the address
steering field "R".
2.
The external device addressed by the request raises a ready signal when it is prepared to transfer or receive data.
3.
A transfer complete signal is generated by
the computer when the data is ready to
tons (SCl-SC4) on the operator's console.
transmit on output, or after the data has
been received on input.
The 17 bits (16 data plus 1 exec) of the output buss
can be directed to any of 16 external registers as defined by the address field R. The output buss also
4.
The device resets the ready signal when it
transfers the address field of SFL and TSL instruc-
has completed the transfer, and releases
tions to external devices.
the computer from the current operation.
The input buss can receive data from any of 16 ex-
The output control lines associated with the system
ternal registers as specified by the address field R.
interface are listed below. The signals on these
lines, generated by the computer, inform the exter-
Details of the external interrupts are discussed with
nal devices about the operation in progress.
the interrupt system in Chapter 3.
Table 4-2. System Interface Output Control Lines
The outputs from the system control buttons are provided to enable operator control of external devices
Output
Line
Meaning
from the console. The system control buttons are
LOOB
Load output buss operation
latching switches. When the button is depressed,
the output line is high (+ 5 volts); when the button is
STIB
SFL2
Store input buss operation
SFL3
SFL operation in bank 3
TSL2
TSL operation in bank 2
TSL3
TSL operation in bank 3
TCS
Transfer complete strobe. (This signal
is set when data is ready for output, or
has been received on input. )
released, the output line is low (ground).
Provision is also made for four internal interrupt
lines on the system interface. For those machines
with no more than four data channels, the internal
interrupt lines corresponding to channels 4, 5, 6,
4-12
SFL operation in bank 2
The input control lines are listed below. The sig-
buss and appropriate control signals
nals on these lines, generated by external devices,
are set to indicate a TSL instruction
are in response to the output control signals.
in Bank B.
Table 4-3. System Interface Input Control Lines
Banks:
B
Input
Line
Options:
*
Flags:
The Z flag is set if the selected line is
2 or 3 for the system interface
Meaning
SBY2
B flag response for bank 2 SFL's
SBY3
B flag response for bank 3 SFL's
SZE2
Z flag response for bank 2 TSL!s
SZE3
Z flag response for bank 3 TSL's
SRDY
System Ready. (This signal is set when
the device is ready to transmit or receive information, and reset when the
operation is complete. )
set (binary 1). If multiple lines are addressed, the Z flag is set if any of the
selected lines are high.
There are no restrictions on the use of address fields
for either SFL or TSL instructions in Bank 2 or 3.
External decoding logic can be added to the system
The SRDY signal must be reset by the external device before the computer will be released and allowed
to proceed. The execution time, therefore, of all
instructions pertaining to the system interface depends on the speed of the external device addressed
interface to permit selection of up to 2 16 line for
each bank. Note, however, that EAI standard System Interface Expansion codes have been allocated to
ensure satisfactory field expansion of a system and
programming compatibility.
by the instruction.
LOOB
M" R
Load external register R on the
4.4.3 SFL/TSL Instructions
Output Buss with the contents of
memory location M.
SFL = M, ,B
Set Function Line in bank B. The
effective address is transferred
over the 16 data lines of the output
STIB
M, ,R
Store the contents of external register R on the Input Buss into memory
buss, and appropriate control sig-
location M.
nals are set to indicate an SFL instruction in Bank B.
Registers: R
0, 1, 2 ...... , 15
2 or 3 for the system interface
Banks:
B
Options:
*
Flags:
The B flag is set if the selected line (or
Options:
*, =, /
Flags:
None
lines) is already set, or if some conditions prevent the setting of the selected
line (or lines).
If more than 16 external registers are to be used,
an external address buffer can be added to the interface.
TSL "" M, , B
LOOB and STIB instructions could then be
Test Sense Line in bank B. The
preceded by an SFL instruction to set up the exter-
effective address is transferred
nal address buffer. Standard EAI modules in this
over the 16 data lines of the output
area (such as I/O Buss Controllers) are available.
4-13
4. 5 PERIPHERAL DEVICES
The typewriter transmits and receives data characters in BCD mode. The data channel makes the re-
4. 5. 1 Typewriter
quired code conversion from BCD code to internal
8400 code on input, and vice versa on output. Details
The 8400 desk typewriter is a 132 column IBM Selec-
of the code conversion are also discussed in Appen-
tric. The typewriter can be connected to the data
dix 5.
channel as an input or an output device, or it can be
used for entering data directly into the computer reg-
H byte size 4 mode is used, only the 4 least signifi-
isters. Details. of the latter capability are discussed
with console operations, Chapter 5. Parity is checked
cant bits per character are transferred. In this
mode, however, parity may not be correct.
on both input and output. The maximum data rate is
15 characters per second.
4. 5. 1. 2 Programming. The general sequence
of instructions required to transfer data to or from
A Typewriter Ready indicator on the console is lit
the typewriter is the following:
when the typewriter is connected to the channel and
waiting for input.
1.
Initialize the channel and connect the device with a channel SFL instruction. The
The typewriter keyboard and the corresponding char-
SFL code should specify BCD mode to
acter octal codes are shown in Figure 4-9.
achieve proper code conversion.
4. 5. 1. 1 Data Format. The typewriter trans-
2.
Test busy to assure that the channel in-
mits and receives two types of information: data
struction was accepted by the Exchange
characters and control characters. The data char-
Module.
acters are the 64 members of the EAI 8400 character
set. Control characters on the typewriter are the
3.
following:
struction.
carriage return
4.
tab
5.
Transfer data.
Disconnect the typewriter with a channel
SFL instruction.
backspace
upper case shift
Select ribbon color with a device SFL in-
The ribbon color can be selected by an SFL instruction with the address field shown in Figure 4-12.
lower case shift
The SFL instruction for ribbon control can be issued
index
any time, where the device is active or not; these
instructions are never rejected. Black is considered
Eight lines are used to transfer information to or
from the typewriter--6 data lines, 1 control line, and
the normal color. The ribbon color will be set to
black when any of the following occur:
1 parity line. The parity bit is used by the data
.channel, and this bit never appears in core memory.
1.
Channel Clear SFL is executed
Refer to Figure 4-10. The control line is high for all
control characters, and low for all data characters.
2.
Console Initialize
The position of a typewriter character in an 8-bit byte
3.
Auto Load
in core memory is shown in Figure 4-11.
4.
Auto Dump
4-14
60
Figure 4-9. Typewriter Keyboard
o
2
3
4
5
6
1
FUNCTION
DATA
SET REO
C
K
DEV
0
I 2 3
456 1
B 9 10 II 121314 15
0
000
o
o
XXXXXXO I
SET BLACK 0 000
TYPEWRITER
P
C
X
X
= PARITY
DATA
P
BIT
L
I 10 XXXXXXIO
I I 0
K
channel number 0-7
D
device number 1-15
x
"don It care" positions
= CONTROL BIT
=0 ON INPUT
= DON'T CARE ON OUTPUT
Figure 4-10. Connection of Typewriter
to the Channel Buffer Register
Figure 4-12. Typewriter SFL Codes
No TSL instructions are associated with the typewriter.
I
x
I
c
o
Parity can be tested using the channel parity
indicator. The channel signal indicator will be set in
two situations:
1.
where:
During input when a carriage return is
typed. The occurrence of channel signal
on input will always terminate the current
D
6 data bits
word assembly permitting transfer of the
c
1 for control characters
(possibly incomplete) half-word into
c
o for data characters
o following input (forced by hardware)
memory.
x
(X is ignored on output)
2.
During output if the typewriter printing
mechanism fails to respond to an output
Figure 4-11.. Typewriter Character
Position in Memory
character within a preset amount of time
(approximately 110 msec).
4-15
4. 5.2 Card Reader (Models 8452, 8453, and
8454)
Reset
This switch, when pressed, clears
the error indicators.
The card reader is an input device which reads
punched cards. All models can handle either 51 or
start
80 column cards. In addition, some units can handle
60 and 66 column cards.
This switch, when pressed, resets
the Not Ready indicator and permits
the reader to be put on line for data
The Model 8452 Card
transfer.
Reader reads 400 cards per minute (cpm), the
Model 8453 reads 800 cpm, and the Model 8454 reads
1400 cpm. All models provide read-check circuits
and validity-checking apparatus; the models are in-
Stop
This switch, when pressed, places the
reader in a Not Ready condition.
terchangeable and can be programmed and operated
4.5.2.2 Data Format.
in the same way.
In general, cards have
80 columns and 12 rows. The card reader is capa4.5.2.1 OPerator Controls and Indicators. The
following switches and indicators are located on the
control panel of the card reader:
ble of reading two types of cards: Hollerith cards
and binary cards. Hollerith cards have one alphanumeric character per column, and each character
is expressed in a 12-bit Hollerith code. The Hollerith
Power On
This switch when pressed, applies
power to the card reader.
code for the EAr 8400 character set is shown in Figure 4-13. When reading Hollerith cards, the card
reader translates the 12-bit card code into a 6-bit
Power Off
This switch, when pressed turns
off the card reader,
BCD code. By using the BCD mode in the data channel, the BCD code is automatically converted to internal 8400 binary codes. Cards will be read as
Not Ready
This indicator is lit whenever the
reader is not ready. The ready
condition is defined under program indicators.
Hollerith cards when the data channel is selected in
BCD mode. The validity checking in the reader per-
tains to Hollerith cards only; the reader checks that
the 12-bit character punched on the card is a legal
Hollerith character.
Feed Check This indicator is lit whenever a
jam occurs in the card feeding
mechanism.
Binary cards are read as two 6-bit binary characters
per column. The card reader strobes each column
twice, reading the top 6-bits of a column first, and
Read Check This indicator is lit whenever a
fault in the read circuitry is detected.
then the lower 6-bits of the same column. Each card
contains 160 total characters. No decoding or validity checks are performed for binary cards. The correspondence between a binary card character and its
Validity On
This latching switch, when depressed, enables the validitychecking circuit, and lights the
indicator. Releasing the switch
inhibits the validity checking.
Validity Off This indicator is lit when the
4-16
image in core memory is shown in Figure 4-14.
Cards are always selected as binary cards when the
data channel is selected in binary mode.
Provision is made for reading mixed decks of binary
and Hollerith cards as follows: if the data channel is
selected in BCD. mode, and the first column of a
validity-checking circuits detect
card has the 7 and 9 holes punched, the mode will be
an invalid character.
automatically switched to binary, and that card will
(ROW
12
I
I
I
II
o
2
3
4
J
I
B
K
S
C
0
L
M
I
I
A
T
U
+
?
!
-
I
0
I
~
-6
==
I
.
)
$
•
3
*
.•
(
4
5
E
N
V
.
[
6
F
0
W
>
<
7
G
P
X
r
-t
8
H
Q
y
I I I I
9
I
R
Z
]
t:.
4
2
"...,...
5
\
6
"*
7
8
5
6
7
8
9
caR
CBR: CHANNEL BUFFER REGISTER
THE TWO MOST SIGNIFICANT BITS ARE SET TO ZERO
IN 8 BIT MODE. ONLY THE FOUR LEAST SIGNIFICANT
BITS ARE USED IN 4 BIT MODE.
9
NO PUNCH = SPACE CHARACTER
='60 INTERNAL BINARY CODE
='20 EXTERNAL BCD CODE
Figure 4-14. Position of Binary
Card Characters in an
8-bit byte
Figure 4-13. Hollerith-BCD Code on a Card
be read as a binary card. The first column will also
4.5.2.3 Program Controls and Indicators.
be strobed twice in this situation, and 160 binary
The controls and indicators accessible by program
characters will result from a binary card in mixed
are the following:
mode. At the end of the card, the mode is switched
back to the BCD state.
Reader Ready
This indicator is true when the
following conditions exist on
The 8-bit mode in the data channel normally will be
the reader:
used with the card reader. Since 6-bit characters
1. Power on
are generated by the reader, the 2 most significant
the data channel can be used in Binary mode only; in
2.
3.
4.
5.
this case, only the 4 least significant bits of each
6. No read check error
6-bit character generated by the reader are trans-
7. No validity check error
ferred to the data channel.
8. All covers in place
bits per 8-bit byte are set to zero by the data channel
prior to transfer into memory. The 4-bit mode in
Hopper not empty
Stacker not full
Start button depressed
No feed check error
4-17
Binary Status
This indicator is set when a
This indicator is set when the
Overflow
7 -9 punch is detected in the
data channel fails to accept a
first column of card and is re-
character from the reader
set by any of the following:
before another character is
read, and, reset by any of the
1. SFL instruction for channel
following:
clear
1. TSL instruction for test and
reset
2. Initiating a new card cycle,
2. SFL instruction for channel
whether by SFL instruc-
clear
tion, or by continuous card
feeding
3. SFL instruction which con-
nects the reader to the
3. Manual reset control on
channel
the reader
Card Cycle
In Progress
Start Card
Cycle
This indicator is set when a
This command starts a card on
the way to the read station, and
new card cycle is initiated-
sets the Card Cycle in Progress
either by SFL instruction, or
indicator.
by continuous card feed-and
Device
Interrupt
Enable
(DINE)
reset when all 80 columns have
been read.
This program-controlled
switch, when set, enables a
channel interrupt to occur
whenever the Reader Ready
Reader
Error
This indicator is set when one
indicator is high. This switch
of the following:
can be set only when no device
is currently connected to the
channel, and is automatically
1. A read-circuit malfunction
reset whenever a device is
is detected
connected to the channel, or a
channel clear instruction is
2. An invalid character is
executed.
detected while reading in
Hollerith mode with the
The TSL instructions associated with the card reader
Validity switch on
use the address field shown in Figure 4.15.
This indicator is reset by any
of the following:
1. SFL instruction for channel
clear
0
K
K
0
K
0
K
0
0
0
0
0
K
K
K
0
0
0
0
0
I
2. SFL instruction which con-
X XX I X X X X
XI X X X X X X
XX X X I X X X
XX X X X I X X
X XX X X x I X
XX X X xx X I
XX I X X X X X
K = channel number 0-7
channel
D = device number 1-15
reader
CARD READER ERROR
CARD READER CONTINUE LEVEL
END OF FILE
CARD CYCLE LEVEL
CARD READY LEVEL
BINARY MODE
OVERFLOW
Where
nects the reader to the
3. Manual r.eset control on the
4-18
7 8 9 10 " 12 1314 15
34
01
X = don't care
Figure 4-15. Card Reader TSL Codes
The Z flag is set in response to a TSL instruction, if
the tested indicator is true; the flag is reset if the
8. Test error conditions using channel and
device TSL instructions.
tested indicator is false.
The SFL instructions associated with the card reader
A new card cycle can be initiated either with the SFL
use the address field shown in Figure 4. 16.
for Start Card Cycle, or the SFL instruction which
connects the reader to the channel. Once a card
cycle is started, the card moves at a fixed rate
EFFECTIVE ADDRESS
FUNCTION
START CARD CYCLE
101
K
D
through the read station, and data is generated at a
Ixlxlxlxlxlxlxlll
101
II
SET DEVICE INTERRUPT
K
D
III xlxl xlxl x x x I
ENABLE (DI NE)
'-0-'-1--3-'-4---7--'-8'------'----L--'--'----'----'--'15
rate determined by the card reader. If the SFL Start
Card Cycle command is used, the reader must then
be connected to the channel within 10 milliseconds,
K
= channel number
0-7
D = device number 1-15
X
or the SFL channel command will be rejected and
one card may be skipped.
= don't care
In general, the channel SFL instruction which conFigure 4-16. Card Reader SFL Codes
nects the reader to the channel will be rejected if
either the reader is not ready, or if more than 10
The SFL for Start Card Cycle is rejected, and the B
milliseconds have elapsed since a new card cycle
flag set if a card cycle is in progress, or if the
was started.
reader is not ready.
If another device is connected to the data channel, the
When the card reader is connected to the channel,
SFL to set the DINE switch is rejected, and the B
the channel signal indicator will be set at the end of
flag set.
a card cycle (i. e., after all 80 columns are read).
4.5.2.4 Programming. The general sequence
of instructions required to use the card reader is the
following:
At the same time the channel signal indicator is set,
a 100 microsecond timing signal will be triggered.
At the end of the 100 microsecond period, if the
reader has not been disconnected from the channel,
1. Test for end of previous card cycle with a
TSL instruction.
a new card cycle will be started automatically.
Therefore, once the reader is connected to the channel, cards are read continuously until the reader is
2. Initiate a new card cycle with a device SFL
disconnected from the channel.
instruction.
3. Test busy to make sure the SFL instruction
was accepted, and take delay action if the
reader is busy.
4. Initialize the channel and connect the reader
No parity checking is performed by the data channel
with the card reader. The channel parity indicator
will be set when the reader is connected to the channel and any of the following occur:
with a channel SFL command.
5. Test busy to make sure the channel com-
1. Reader overflow
mand was accepted.
2. Read-Check error
6. Transfer data.
7. Disconnect the transfer.
3. Validity-Check error
4-19
A channel interrupt will result from the card reader
in the following two cases:
4.5.3.1 Data Format.
Paper Tapes can be
read in either forward or reverse direction using
either binary or BCD channel options. In all cases,
1. When the reader is connected to .the channel,
and the reader becomes not ready.
the most significant bit per character on the tape is
considered a parity bit. The data channel checks the
lateral parity of each character, using odd parity in
2. When no device is connected to the channel,
binary mode and even parity in BCD mode. The
the DINE switch on the reader is set, and
channel parity indicator is set when bad parity is
the reader becomes ready.
detected.
If the reader becomes not ready while connected to
Either a 4 or 8-bit mode can be used, with or without
the channel, the data continues to be transferred, and
exec bits. In the 8-bit mode, the 7 least significant
the card will continue to move until the present cycle
bits per character are transferred into the 7 least
is complete. Once disconnected, however, the
significant bits per byte, and the most significant bit
reader cannot again be connected until the not ready
is set to zero. In the 4-bit mode, only the 4 least
condition is reset (i. e., the cause of the not ready
significant bits per character plus the parity bit are
condition is removed).
transferred to the data channel. The connection of
the reader to the channel buffer register is similar
4.5.3 Paper Tape Reader
to that of the typewriter as shown in Figure 4.10.
The paper tape reader is an EAI model which can
Blank tape is always skipped automatically in both
read 5, 7, or 8 channel tapes. The device reads
binary and BCD mode.
500 characters per second in either forward or reverse direction.
Fanfold tape containers for tape
supply and take-up are provided.
4.5.3.2 Programming.
The general sequence--
of instructions required to use the paper tape reader
is the following:
Desk controls and indicators pertaining to the reader
1. Set forward or reverse direction with a
are the following:
device SFL instruction.
Power On/Off
This switch controls the power
to the reader transport and
electronics.
2. Test busy flag to see if the direction command was accepted.
3. Initialize the channel and connect the reader
Run/Load
This switch must be in load
with a channel SFL instruction.
position to insert or remove
tapes from the reader. The
switch must be in run position
4. Test busy flag to ensure that the channel
command was accepted.
for the tape to move.
5. Transfer data.
Reader
Ready
This indicator is lit when the
reader has been connected to
the data channel.
4-20
6. Disconnect the reader with a channel SFL
instruction.
The reader direction can be selected by an SFL instruction with the address field shown in Figure 4-17.
register. The channel data register is not ready when
it contains a completely assembled half-word, and is
waiting to transfer its contents to core memory.
c:
I
M FIELD
D
K
oil 2 3 : 4 5
i0
I
I
6:
I
I
,
I
L
7 : 8 9 10 II 12 13 14 15
FWD
o :0 0 0
REV
o : 0 0 0 : 0 0 1:0: x x x x x X I 0
I
I
0 I ,0 : x x x x x x 0
I
I
I
I
I
at 500 characters per second) is less thaIl 500 micro-
I
1
K = channel number 0-7
D = device number 1-15
= don't care
X
The stopping time for the tape reader (when running
seconds. When the tape motion is inhibited by the
channel, the tape stops on the character just transferred to the channel.
There are no TSL instructions associated with the
Figure 4-17. Paper Tape Reader
SFL Instructions
tape reader. Parity can be tested using the channel
The direction control instructions will be rejected if
The channel signal indicator will be set whenever a
the tape is moving in a direction contrary to that of
stop code (octal 100) is detected. The detection of a
the SFL command. This interlock prevents damage
stop code will also terminate the current word assem-
to the reader due to sudden reversal of drive power.
bly' permitting transfer of the (possibly incomplete)
The forward direction is considered normal. The
half-word into memory. stop code detection is enabled
Forward Direction is set when any of the following
even in 4-bit mode. Direction of a stop code during
occur:
an auto load operation will terminate the input and
1. SFL channel clear instruction is executed
2. Console initialize
3. Auto Load
parity indicator.
disconnect the reader.
4. 5.4 Paper Tape Punch
The paper tape punch is an EAI Model which handles
5 to a channel paper tapes. Ten characters per inch
4. Auto Dump
When reading in reverse mode, the data channel
assembled half-word has the same form as when the
tape is read in the forward direction. The half-word
are punched at 110 characters per second.
Desk controls and indicators pertaining to the punch
are the following:
Power On/Off
This switch, when on, enables
program control over the punch
transfers into memory, however, must be programmed differently in forward and reverse mode to
power. When this switch is off,
achieve identical full-word formats in memory.
the punch power remains off
unconditionally.
The SFL instruction which connects the reader to the
channel starts the tape in motion. The channel SFL
Tape Feed
command will be rejected and the B flag set if the
blank tape to be punched as
reader power is off, or if the reader is in a load (not
long as the switch is depressed.
run) condition. Tape motion will be automatically
inhibited if either the channel buffer register is not
This switch, if pushed when the
punch power is on, causes
Tape Low
This indicator is lit when only
ready to accept a character from the reader, or if
one foot or less of tape remains
the channel data register is not ready to accept a
to be punched.
character from the buffer register. The channel buf-
Punch Ready
This indicator is lit whenever
fer is not ready when it contains a completely assem-
the punch has been connected
bled a-bit byte, and is waiting to transfer its contents
to the data channel for data
through the assembly register into the channel data
transfer.
4-21
4. 5. 4. 1 Data Format.
Both binary and BCD
mode may be used for transfer of information to the
The punch power is controlled by SFL instructions
with the address field shown in Figure 4-18.
punch. A parity bit is generated in the data channel-odd parity for binary mode, and even parity for BCD
cant Qit of each character. The connection of the
punch to the Channel Buffer Register is similar to
0:
C
K
0
I 23
4 5 6:7
B 9 10 II 12 13 1415
POWER ON
0
000
0
000
o
o
XXXXXXIO
POWER OFF
mode. The parity bit is punched as the most signifiM FIELD
I
oio
L
I 0:0 ' 0 AFTER ARITH. INSTR.
RESULT NOT> 0 AFTER ARITH. INSTR.
RESULT < 0 AFTER ARITH. INSTR.
RESULT NOT < 0 AFTER ARITH. INSTR.
OVERFLOW SINCE FLAG RESET
NO OVERFLOW SINCE FLAG RESET
CARRY IN LAST ARITH. INSTR.
NO CARRY IN LAST ARITH. INSTR.
LAST 1-0 INSTR. NOT EXECUTED (BUSY)
LAST 1-0 INSTR. WAS EXECUTED
INTERRUPT SYSTEM ENABLED
INTERRUPT SYSTEM NOT ENABLED
FLAG 1 TRUE
FLAG 1 FALSE
FLAG 2 TRUE
FLAG 2 FALSE
FLAG 3 TRUE
FLAG 3 FALSE
FLAG 4 TRUE
FLAG 4 FALSE
FLAG 5 TRUE
FLAG 5 FALSE
FLAG 6 TRUE
FLAG 6 FALSE
FLAG 7 TRUE
FLAG 7 FALSE
FLAG 8 TRUE
FLAG 8 FALSE
a MNEMONIC FLAGS
0
1
2
3
4
5
6
7
X
19
25
I 26
FL
27
I
28
I
29
30
31
OP
CONDITION (1)
C
N
Z
NZ
C
NC
L
NL
V
18
TRUE
FALSE
TRIGGER
= SET
= RESET
= COMPLEMENT
OPERATION
HALT AND JUMP TO EFFECTIVE ADDRESS (EA)
EXECUTE THE INSTR AT EA
LINK TO THE SUBR. AT EA
LINK TO EA AND RESET FLAG
JUMP TO EA AND TRIGGER FLAG (2)
JUMP TO EA AND SET FLAG
JUMP TO EA AND RESET FLAG
JUMP TO EA
(1) HALT, EXECUTE, LINKS AND JUMPS ARE CONDITIONAL UPON THE STATE OF THE FLAG
TESTED WHEREAS SET, RESET AND TRIGGER ARE NOT CONDITIONAL
(2)
PERMITS LOW PRIORITY INTERRUPTS AFTER A HIGHER .'ffiIORITY INTERRUPT
HAS OCCURRED.
A2-1
APPENDIX 2
MNEMONICS
Input-Output (0400-0577)
All in this group are privileged instructions
OCTAL
0420
0440
0460
0500
0520
054k
055k
056k
057k
+R
+R
+R
+R
+R
MNEMONIC
INSTRUCTION
FLAGS
LOAD OUTPUT BUSS R WITH E. A. O:SR :S 178
STORE (INPUT BUSS R) AT E.A.
LOAD OUTPUT BUSS R WITH (E. A.)
STORE (INPUT BUSS R) AT /E.A.
LOAD OUTPUT BUSS R WITH (fE.A.)
STORE CHANNEL k's CONTROL WORD AT E.A. OS k8:S7
STORE CHANNEL k's DATA WORD AT E.A. (1)
LOAD CHANNEL k's CONTROL WORD WITH (E.A.)
LOAD CHANNEL k's DATA WORD WITH (E.A.)(1)
LDOB = m"R
STIB
m"R
LDOB m"R
STIB /m"R
LDOB /m"R
STCC m, ,k
STCD m, ,k
LDCC m"k
LDCD m, ,k
Registers, TSL's and SFL's-Exec Bits (0600-0777)
SFL, TSL, LOT, LDM, LDE and LDC are privileged instructions
IMMEDIATE
0607
0617
062k
0627
0630 + b
REX
TEX
LDs
SEX
TSL
= m,X
= m,X
= m,X
= m,X
=m, ,b
0634 + b
SFL = m"b
Z
Z
B
RESET L.H. EXEC. BIT AT INSTRUCTION ADDRESS
TEST L.H. EXEC. BIT AT INSTRUCTION ADDRESS
LOAD REGISTER s WITH E.A.
SET L.H. EXEC. BIT AT INSTRUCTION ADDRESS
TEST SENSE LINE(S) IN BASE 0 SPECIFIED BY E .A.
o :S bS :S 3
SET FUNCTION LINE(S) IN BANK b SPECIFIED BY E.A.
LEFT HALF
064s
0647
0657
066s
0667
STs
REX
TEX
LDs
SEX
m,X
m,X
m,X
m,X
m,X
STs
REX
TEX
LDs
SEX
/m,X
/m,X
/m,X
/m,X
/m,X
Z
STORE (REGISTER s) AT E.A.
RESET L.H. EXEC. BIT AT E.A.
TEST L.H. EXEC. BIT AT E.A.
. LOAD REGISTER s WITH (E.A.)
SET L.H. EXEC. BIT AT E.A.
Z
STORE (REGISTER s) AT /E.A.
RESET R.H. EXEC. BIT AT E.A.
TEST R.H. EXEC. BIT AT E.A.
LOAD REGISTER s WITH (fE.A.)
SET R.H. EXEC. BIT AT E. A.
RIGHT HALF
070s
0707
0717
072s
0727
(0') IS READ AS "THE CONTENTS OF
0::"
SPECIAL REGISTER S
o
AE
1
2
3
4
5
6
F
L
T
M
E
C
EXTENDED FIXED POINT ACCUMULATION
FLAG REGISTER
LOCATION COUNTER
TIMER REGISTER
INTERNAL INTERRUPT MASK REGISTER
EXTERNAL INTERRUPT MASK REGISTER
CONSOLE REGISTER
(1) IN STCD AND LDCD THE FORMAT OF STORAGE DEPENDS ON THE CHANNEL FUNCTION REGISTER
WmCH IS SET UP BY SPL TO DEVICE 0 ON THE CHANNEL.
A2-2
APPENDIX 2
MNEMONICS
Index Jump Test (1000-1777)
16
18
17
*
21
0
I
22
23
24
1
T
I.± I
0
FLAGS
m, X.± C
XJ
XIT
1000
1400
20
X
MNEMONIC
OCTAL
19
1
27
26
28
1
30
39
31
C
OPERATIONS
ZGL
ZGL
m, X.± C
25
INCREMENT INDEX X BY C AND JUMP TO M
INCREMENT INDEX X BY C AND JUMP TO M
IF THE RESULT IN X HAS OPPOSITE SIGN OF C. -128::::; C ::::; 127
Arithmetic (2000-3777)
16
17
*
18
19
X
20
21
0
1
22
24
1 23
I
25
27
1 26
Mode
1
$
28 1 29
31
30
!
OP
1
C
NORMALIZED 32 BIT FLOATING POINT (FL PT)
NORMALIZED 56 BIT FL PT
UNNORMALIZED 32 BIT FL PT
UNNORMALIZED 56 BIT FL PT
INTEGER EXECUTED AS FL PT IMMEDIATE
INTEGER EXECUTED AS FL PT LEFT HALF
INTEGER EXECUTED AS FL PT RIGHT HALF
UNNORMALIZED INT EXECUTED AS FL PT IMM.
UNNORMALIZED INT EXECUTED AS FL PT L.H.
UNNORMALIZED INT EXECUTED AS FL PT R. H.
INDEX ARITHMETIC IMMEDIATE
INDEX ARITHMETIC LEFT HALF
INDEX ARITHMETIC RIGHT HALF
EXTENDED FIXED POINT
FIXED POINT IMMEDIATE
FIXED POINT LEFT HALF
FIXED POINT RIGHT HALF
2000 + C
2100 + C
2200 + C
2300 + C
2400 + C
2400+ C
2440 + C
2600' + C
2640 + C
2700 + C
3400 + C
3440 + C
3500 + C
3540 + C
3600 + C
3640 + C
3700 + C
00
01
02
03
04
05
06
07
10
11
20
21
22
23
24
25
26
27
30
31
SB
CS
CA
AD
CP
CP
ST
SR
DV
CD
$SB
$CS
$CA
$AD
$CP
$MP
$ST
$SR
$DV
SCD
Shifts (3000-3377)
N - NORMALIZED
E- EXTENDED
16
L- LOGICAL
*
ASH
3000
3020
$ASH
3040
ROT
3060
$ROT
EASH
3100
3120 $EASH
EROT
3140
3160 $EROT
NRM
3200
3220 $NRM
3300 ENRM
3320 $ENRM
±
±
±
±
±
±
±
±
m,
m,
m,
m,
m,
m,
m,
m,
,
,
,
,
X
X
X
X
X
X
X
X
X
X
X
X
17
18
X
ZGLV
ZGLV
19
20
21
22
0
1
1
I 23
24
0 IN
25
J
26
L
27
l
$
28
I 29
30
31
J - UNUSED
ARITHMETIC SHIFT
LOGICAL ROTATE
ZGLV
ZGLV
EXTENDED ARITHMETIC SHIFT
EXTENDED LOGICAL ROTATE
NORMALIZE AND LOAD SHIFT COUNT IN X
EXTENDED NORMALIZE AND LD S. C. IN X
IMMEDIATE MODE IS ASSUMED
IF EA IS POSITIVE, SHIFT OR ROTATE RIGHT
IF EA IS NEGATIVE, SllFT OR ROTATE LEFT
A2-3
MNEMONICS
APPENDIX 2
Boolean Connectives (4000-7777)
16
17
*
18
X
OCTAL
4000 +
4100 +
4200 +
4300 +
4400 +
4500 +
4600 +
4700 +
5000 +
5100 +
5200 +
5300 +
5400 +
5500 +
5600 +
5700 +
19
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
FORMAT OPNn
20
21
22
I
1
I 23
25
24
27
28
OP
MNEMONIC
FLAGS
RA
BLA
CBHA
ALA
CBLA
MLA
BDA
ELA
BHA
BSA
MHA
CEHA
BEQT
CELA
EHA
SA
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
I 29
30
31
b
OPERATION
A-ZEROES
A-A NORm
A-AANDm
A-A
A-A NOR m
A-in
A-A EXCL. OR m
A-A NAND m
A-AANDm
A-A EQUIV. m
A-m
A-AORm
A-A- Z SET IF A = m
-' NAND m
A-A
A-AORm
A-ONES
m, x, BYTE
n, 1, 2, 4, 8
BYTE SIZE: UNSPECIFIED
BYTE = 0, 1, ••• ,15 BYTE POSITION
OPTIONS:
26
*
= 16 BIT BYTE
ALL BYTE SIZE/BYTE POSITIONS
IS BIT BYTE TO ACCUM. ONLY
ALL BOOLEAN CONNECTNES ONLY EFFECT A 1, 2, 4, 8, OR 16 BIT BYTE OF THE
ACCUMULATOR WHICH IS SPECIFIED BY THE b FIELD OF THE INSTRUCTION. THE
VALUE OF b MAY BE DETERMINED FROM THE TABLE OPPOSITE
IS READ
"IS REPLACED BY"
A2-4
APPENDIX 2
MNEMONICS
Boolean Connectives (4000-7777)
NAME
OCTAL
RESET
BOTH LOW
BOTH mGH
ACCUMULATION
BOTH LOW
MEMORY LOW
BOTH
EITHER LOW
BOTH HIGH
BOTH SAME
MEMORY HIGH
EITHER HIGH
BYTE EQUAL.
EITHER LOW
EITHER HIGH
SET
6000
6100
6200
6300
6400
6500
6600
6700
7000
7100
7200
7300
7400
7500
7600
7700
USING
LOW
USING
A
A
DIFFERENT
USING A
TEST
USING A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
MNEMONIC
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
FLAGS
RM
BLM
CBHM
ALM
CBLM
MLM
BDM
ELM
BHM
BSM
MHM
CEHM
AHM
CELM
EHM
SM
OPERATION
Z
Z
m - ZEROES
m-ANORm
m-AANDm
m-A
m-ANORm
m-ffi
m - A EXCL. OR m
m-ANANDm
m-AANDm
m - AEQUIV. m
m-m
m-AORm
m-A
m-ANANDm
m-AORm
m - ONES
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
TABLE FOR COMPUTING THE VALUE OF b
1
BYTE SIZE
1M
OPERAND
BYTE #
2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
01
03
05
07
11
13
15
17
21
23
25
27
31
33
35
37
4
1M
41
43
45
47
51
53
55
57
61
63
65
67
71
73
75
77
02
06
12
16
22
26
32
36
1M
42
46
52
56
62
66
72
76
04
14
24
34
16
8
1M
44
54
64
74
10
30
50
70
=
1M
00
20
60
A2-5
APPENDIX 2
MNEMONICS
Double Precision
FORMAT
OPTIONS
*
U
$
=
*
U
$
=
*
U
$
=
*
U
$
=
D
OPN
$
=
*
U
$
=
OPERATIONS
ZGL
C
A:AF:AD - m:m + 1
ZGL
-m: m + 1
A:AF:AD
A:AF:AD
TITLE
SUBTRACT
CLEAR & SUBTRACT
(5)
m: m+ 1
A:AF:AD
CLEAR & ADD
(5) (7)
ZGL
C
A:AF:AD + m: m + 1
ZGL
(2)
COMPARE
ZGL
(2)
MULTIPLY
A:AF:AD _ m: m + 1
(3) (6) (7)
STORE
(2) (4)
STORE ROUNDED
ZGL
V
(2)
DIVIDE
ZGL
V
(2)
CLEAR & DIVIDE
*
$
*
A:AF:AD
ADD
Vc
$
*
$
*
$
(1)
FLAGS
ZGL
*
m,X
=
(1)
OPTIONS
(3) DST FUNCTIONALLY EQUIVALENT TO DSTU
*
USE OF EQUAL SIGN (=) (4) DSTU FUNCTIONALLY EQUIVALENT TO DSRU
OPTION CAUSES DATA
GIVEN (56) BITS TO BE (5) DCAU, DCSU LOAD ACCUMULATOR EXEC BITS
PLACED IN LITERAL
POOL
(6) DSTU STORES ACCUMULATOR EXEC BITS
INDIRECT
/ HALF WORD
= IMMEDIATE
$ SAVE
U UNNORMALIZED.
(2) SUBROUTINE
THE $ SYMBOL IS THE
ONLY OPTION THAT
IS A PREFIX
A2-6
(7) DCAU, DSTU USED TO MOVE DOUBLE PREC. DATA
MNEMONICS
APPENDIX 2
1
INTEGER
MNEMONIC
SB
OCTAL
00
FORMAT
OPN
OPTIONS
FLAGS
01
=
02
03
* / U
04
05
=
*/U
06
-mf - A:AF
ZGL
mf - A:AF
ZGL
C
A:AF = mf - A:AF
ZGL
Z SET IF A:AF = m A:AF UNCHANGED
G SET IF A:AF >m
L SET IF A:AF m
L SET IF A:AF < m
COMPARE
ZGL
A:AF
MULTIPLY
ZGL
C
*
$
m -A:AF:AD
A:AF _ m
(1) (4) (5)
STORE
A:AF (ROUNDED) _ m, A:AF UNCHANGED
STORE ROUNDED
U
C
(2)
$
*
U
$
=
*
U
$
=
ZGL
V
A:AF:AD + m QUOTIENT A:AF
DIVIDE
ZGL
CLEAR AD THEN FLOATING DIVIDE
CLEAR & DIVIDE
V
USE OF THE EQUAL SIGN (=)
OPTION CAUSES DATA (32 BITS)
TO BE PLACED IN THE LITERAL
POOL.
(1) FST FUNCTIONALLY EQUIVALENT TO FSTN
(2) FSR DIFFERS FROM FSRU IF ROUNDING
RESULTS IN AN UNNORMALIZED NUMBER
(3) FCAl1, FCSU LOAD ACCUMULATOR EXEC BITS
(4) FSTU STORES ACCUMULATOR EXEC BITS
(5) FCAU, FSTU USED TO MOVE WHOLE WORDS
& EXEC BITS
A2-8
TITLE
U
$
*
m,X
FLAGS
ZGL
I
F
OPTIONS
*
INDIRECT
/
HALF WORD
IMMEDIATE
S SAVE
U UNNORMALIZED
APPENDIX 2
MNEMONICS
16 Bit Fixed Point
FORMAT OPN /m,X
MNEMONIC
SB
OCTAL
00
(1)
OPTIONS
*/
$
CS
01
*
CA
02
*
03
*
04
05
/
$
ST
06
(2)
(3)
ZGL
m _ A
(2)
(3)
ZGL
VC
A+ m _ A
=
*/
*
ZGL
V
-m - A
=
/
$
MP
A-m _ A
=
$
CP
ZGL
VC
/
$
AD
OPERATIONS
=
/
$
FLAGS
ZGL
=
=
ZGL
V
*/
Z SET IF A = m A UNCHANGED
G SET IF A > m
L SET IF A < m
A
m -A:AE
A-m
$
SR
07
*/
A (ROUNDED) - M
VC
$
DV
10
*
/
$
CD
11
*
$
=
ZGL
V
A:AE -;.. m QUOTIENT - A
REMAINDER - AE
ZGL
V
CLEAR AE THEN DIVIDE
=
/
(1)
USE OF THE SLASH (/)
OPTION IS REQUIRED FOR
RIGHT HALF-WORD ADDRESSING
IF THE SLASH IS OMITTED
LEFT HALF-WORD ADDRESSING
IS ASSUMED.
FLAGS
Z
G
L
V
C
= ACCUM. ZERO
= ACCUM. > ZERO
= ACCUM. < ZERO
= OVERFLOW
= CARRY
(2) 0 - AF
o - AD (1-8)
(3) CA, CS LOAD LEFT ACCUMULATOR EXEC BIT
(4) ST STORES LEFT ACCUMULATOR EXEC BIT
A2-9
APPENDIX 2
Index
MNEMONICS
X
(1, 2, 4)
FORMAT OPN/m, X
OPTIONS
FLAGS
*
$1=
ZGL
VC
X-m-X
SUBTRACT
*
$1=
ZGL
V
-m - X
CLEAR &
SUB 'IRAC T
*
$1=
ZGL
m - X
CLEAR &
ADD
*
$1=
-*1
ZGL
X+ m - X
ADD
ZGL
Z SET IF X - m X UNCHANGED
G SET IFX > m
L SET IF X < m
COMPARE
*
$1:
(3)
MULTIPLY
*$1=
X_m
STORE
$
vc
:
OPERATIONS
TITLE
*1 =
C
(3)
STORE
ROUNDED
*
$1=
AGL
V
(3)
DIVIDE
*
$1=
ZGL
V
(3)
CLEAR &
DIVIDE
$
(1)
USE OF THE SLASH (/) OPTION
IS REQUIRED FOR RIGHT HALFWORD ADDRESSING IF THE SLASH
IS OMITTED LEFT HALFWORD
ADDRESSING IS ASSUMED
(2)
AN INDEX REGISTER MUST BE
SPECIFIED
(3)
SUBROUTINE
(4)
ADDRESS m IS NON-INDEXABLE
A2-10
OPTIONS
*
INDIRECT
HALFWORD
IMMEDIATE
$ BLANK
U UNNORMALIZED
1
MNEMONICS
APPENDIX 2
Extended Precision
FORMAT OPN m, X
OPERATIONS
MNEMONIC
OCTAL
OPTIONS
FLAGS
SB
00
$=
*
ZGL
VC
A:AE -m - A:AE
CS
01
*
$=
ZGL
V
-m _ A:AE (3)
CA
02
$ =
*
ZGL
m _ A:AE (3)
AD
03
$
*
ZGL
VC
A:AE + m _ A:AE
CP
04
$ =
*
ZGL
(1)
MP
05
$ =
*
ZGL
(1)
ST
06
SR
07
DV
10
$ =
CD
11
$ =
*
A:AE _m
$
$
*
C
(1)
*
ZGL
V
(1)
*
ZGL
V
(1)
(1)
FLAGS
SUBROUTINE
(2)
USE OF THE EQUAL SIGN (=)
OPTION CAUSES DATA
(32 BITS) TO BE PLACED
IN THE LITERAL POOL
Z
G
L
V
C
ACCUM ZERO
ACCUM> ZERO
ACCUM < ZERO
OVERFLOW
CARRY
(3)
o
o-
-+
AF
AD (1-8)
A2-11/A2-12
APPENDIX 3
T ABLE OF INTERRUPT ADDRESS CODES
Interrupt Name
Octal
Priority Address
Mask (M
Internal Mask
E External
Mask)
Interrupt Name
Octal
Priority Address
Mask (M
Internal Mask
E External
Mask)
pip
1
'40
Cannot be
masked
External Interrupt
(1,7)
24
'67
E '400
Data Exec
2
'41
M '40000
25
'70
E '200
Priv. Inst.
3
'42
M '20000
External Interrupt
(1,8)
Inst. Exec
4
'43
M'10000
26
'71
E'100
Exp. Fault
5
'44
M '4000
External Interrupt
(1,9)
Mem. Protect
6
'45
M '2000
External Interrupt
(1,10)
27
'72
E '40
Timer
7
'46
M'1000
'73
E '20
8
'47
M '400
External Interrupt
(1,11)
28
Console
Data Channel 0
9
'50
M '200
29
'74
E'10
Data Channel 1
10
'51
M'100
External Interrupt
(1,12)
Data Channel 2
11
'52
M '40
External Interrupt
(1,13)
30
'75
E '4
Data Channel 3
12
'53
M '20
'76
E '2
13
'54
M'10
External Interrupt
(1,14)
31
Data Channel 4
Data Channel 5
14
'55
M '4
32
'77
E'l
Data Channel 6
15
'56
M'2
External Interrupt
(1,15)
Data Channel 7
16
'57
External Interrupt
(2,0)
33
'100
External Interrupt
(1,0) *
17
'60
M'l
E '_0
External Interrupt
(1, 1)
18
'61
E '40000
External Interrupt
(1,2)
19
'62
E '20000
External Interrupt
(1,3)
20
'63
E '10000
External Interrupt
(1,4)
21
'64
E '4000
Set by SFL =
'60,0
Reset by SFL =
'61,,0
External Interrupt
(1,5)
22
External Interrupt
(1,6)
23
'65
E '2000
External Interrupt
(16, 15)
271
'457
I
This enables
or disables
all interrupts
in banks 2-16
More than one interrupt is enabled by forming.a.composite mark code that is the arithmetic sum of the individual code; e. g. , for External Interrupts 4,5,6,
'66
E'1000
mark = E '7400.
*(b. n) Where b=Bank number
n ...Number of the interrupt in the bank.
A3-1
TABLE OF INTERRUPT ADDRESS CODES
APPENDIX 3
HYBRID OPERATIONS
Operation Codes for High-Speed Conversions
1.
ANALOG-TO-DIGITAL CONVERSIONS
Potentiometer Setting
LDOB = '15+c" 12
Single Print
LDOB = '14+c" 12
Analog Mode Selection LDOB
= '07 +c+m, , 12
Analog Time Constant
SFL = '-47 400+a, ,2
Sequential Conversion
SFL = '+47400+a" 2
Random Conversion
SFL
= '+17400+a"
2
Individual T /S : Store
Tis:
SFL = '+07400+a" 2
Individual
SFL = '+37400+a" 2
Block of T /S : Store
SFL
= '+27400+a"
2
Track
Block of T /S : Track
SFL = '+47600, ,2
ADC Control Readout
TSL = '+07400,,2
ADC Test
= '-07000+a, ,2
SFL = '-47000+a, ,2
Random Load DAC
SFL = '+27000+a" 2
Individual DAC Channel:
Transfer
SFL = '+17000+a" 2
Block of DAC Channels:
Transfer
SFL = '+47200, , 2
Clear all DAC Registers
2.
LOOB
Logic Word Input
LOOB = '02+c, , 12
Logic 16 Bit Word
Output
LDOB = '02+c, , 12
Logic B Bit Word
Output
LDOB
Status Word Readout
LDOB = '06+c, , 12
Fault Word Readout
LOOB
where
= '03+c, , 12
c = analog console number times 25 in octal
for example:
and
DAC Test
OPERATION CODES FOR ANALOG
MONITOR/ CONTROL
m follows the table below:
OD
'0400
RT
'1000
ST
'1400
OP
'2000
H
'2400
DVM Conversion
LOOB = '16+c" 12
IC
'3000
PS
'3400
DVM Readout
LDOB = 'Ol+c" 12
Analog Address
Selection
LOOB = '04+c" 12
Analog Address
Readout
LDOB = '04+c, ,12
Analog Address Step
LDOB = '17+c" 12
Analog Value Selection LOOB
= '05+c"
12
c = 40 for console 1
c = 100 for console 2
= conversion channel address or block address.
A3-2
= '13+c, , 12
Sequential Jam DAC
Random Jam DAC
a
= '12+c+d" 12
Logic Mode Selection
Monitor Word Readout STIB = M" 12
SFL = '+07000+a, , 2
= '+07000,,2
LOOB= '11+c+t2" 12
Sequential Load DAC
SFL = '+47000+a, , 2
TSL
10:1
LDOB = '10+c+t1" 12
Mask Register Loading LOOB i" 12
Digital-to-Analog Conversions
SFL
Selection, 1000: 1
and
tl follows the table below:
MSEC
'000
SEC
'400
APPENDIX 3
and
TABLE OF INTERRUPT ADDRESS CODES
t2 follows the table below:
finally i corresponds to a mask placed into the most
FAST
'0400
significant two octal digits of the address, thus vary-
MED
'1400
ing between '00000 and '77000 changing only the left-
SLO
'1000
most two digits.
3.
HYBRID SENSELINES AND FUNCTION LINES
TSL = '6000 + C + S " 2
and
d will be determined by the following table:
RUN
'0400
STOP
'1000
CLR
'1400
SFL
where
= '6000 + C + S
" 2
c is console # as defined above and
s is the address of the sense or control line
in octal.
A3-3/ A3-4
APPENDIX 4
TABLE OF SFL/TSL CODES
1.
PROCESSOR INTERRUPT SFL
SFL
Function
Flag Indication
21
Reset Privileged Instruction
Interrupt Occurred Indicator
B flag if set
23
Reset Memory Parity Error
Indicator
B flag is set
25
Reset Console Interrupt 1
Indicator
B flag if set
27
Reset Console Interrupt 2
Indicator
B flag if set
31
Reset Console Interrupt 3
Indicator
B flag if set
Reset Console Interrupt 4
Indicator
B flag if set
40
Set Memory Protect Bank 1
Indicator
B flag if set
41
Reset Memory Protect
Bank 1 Indicator
B flag if set
Set Memory Protect
Bank 2 Indicator
B flag if set
Reset Memory Protect
Bank 2 Indicator
B flag if set
Set Memory Protect Bank 3
Indicator
B flag if set
45
Reset Memory Protect
Bank 3 Indicator
B flag if set
46
Set Memory Protect Bank 4
Indicator
B flag if set
Reset Memory Protect
Bank 4 Indicator
B flag if set
Set External Interrupt
Enable Indicator
B flag if set
61
Reset External Interrupt
Enable Indicator
B flag if set
62
Set Internal Timer On-Off
Control
B flag if set
Reset Inte1'nal Timer OnOff Control
B flag if set
33
42
43
44
47
60
63
SFL
Function
Flag Indication
65
Reset Monitor Mode Indicator
B flag if set
67
Reset Memory Protect Interrupt Occurred Indicator
B flag if set
2.
PROCESSOR INTERRUPT TSL
TSL
Function
Flag Indication
21
Tested Privileged Instruction
Interrupt Occurred Indicator
Z flag if set
23
Tested Memory Parity Error
Indicator
Z flag if set
25
Tested Console Interrupt 1
Indicator
Z flag if set
27
Tested Console Interrupt 2
Indicator
Z flag if set
31
Tested Console Interrupt 3
Indicator
Z flag if set
33
Tested Console Interrupt 4
Indicator
Z flag if set
40
Tested Memory Protect
Bank 1 Indicator
Z flag if set
42
Tested Memory Protect
Bank 2 Indicator
Z flag if set
44
Tested Memory Protect
Bank 3 Indicator
Z flag if set
46
Tested Memory Protect
Bank 4 Indicator
Z flag if set
60
Tested External Interrupt
Enable Indicator
Z flag if set
62
Tested Internal Timer On-Off
Control Indicator
Z flag if set
65
Tested Monitor Mode Indicator Z flag if set
67
Tested Memory Protect
Interrupt Occurred Indicator
Z flag if set
A4-1
TABLE OF SFL/TSL CODES
APPENDIX 4
3.
5.
EXCHANGEINTERRUPTSFL
SFL
-OOOOO+K*
Function
Flag Indication
Unconditional Channel
Clean
B
00001+K
Disconnect Channel
00002+K
HYBRID SFL's
Digital-to-Analog Conversion
SFL
Function
B
0700+a**
Sequential/Normal Conversion
Enable Channel Ready
Interrupt
B
47000+a
Sequential/Jam Conversion
-07000+a
00004+K
Random/Normal Conversion
Disable Channel Ready
Interrupt
B
-47000+a
Random/Jam Conversion
00010+K
Enable Channel Signal
Interrupt
B
Disable Channel Signal
Interrupt
B
00020+K
4.
27000+a
Individual Channel Transfer
17000+a
Block Transfer
07200
Clear all DAC Registers
EXCHANGE INTERRUPT TSL
TSL
00001+K
-OOOOl+K
00002+K
-00002+K
00004+K
Function
Flag Indication
Test Channel Signal
Z
Test Channel Signal and
Clear
Z
47400+a
Sequential Conversion
-47400+a
Random Conversion
Individual T /S Store
Test Channel Parity
Z
17400+a
Test Channel Parity and
Clear
Z
07400+a
Indi vidual T /S Track
37400+a
Block T /S Store
Test Channel Ready
Z
27400+a
Block T /S Track
27600
Control Readout
*K= 00000 jor Channel 0
= 40000 jor Channel 4
= 1 0000 jor Channell
=50000 jor Channel 5
= 20000 jor Channel 2
= 60000 jor Channel 6
= 30000 jor Channel 3
= 70000 jor Channel 7
A4-2
Analog-to-Digital Conversion
**a = DAC Channel Address or Block Address.
APPENDIX 4
TABLE OF SFL/TSL CODES
SFL AND TSL CODES FOR 8400 STANDARD PERIPHERAL EQUIPMENTS
GENERAL FORMAT
(Applicable to all Data Channels and Device Controllers attached to Data Channels.)
SFL Instructions
K
D
L
Crr--~A--~I,rr----~·~--~,r,--------~·~--------~
"M" Field
Io I I I I I I I I I I I I I I I I
1
3
4
7
15
8
C :;: O-SFLC. Used for general Channel/Device control conditions.
C:;: 1-SFLF. Used to Initialize Channel and Connect Device.
Also, for Unconditional Channel/Device Disconnect if D :;: O.
K :;: Data Channel Designator, 0 to 7.
D :;: Peripheral Device Designator, 1 to 15.
L :;: M field allocated for:
1.
Setting Channel Function Register (CFR), if C :;: 1 and D :;: O.
2.
Device Control, if C :;: 0 and D f 0, (i. e., Device Control Word).
3.
Channel Control, if C :;: 0 and D :;: 0, (i. e., CHRI and CHSI).
TSL Instructions
"M" Field
K
C ~(
D
L
A
lr~--------""'''-----------~
Io " I I " I I I I I I I I I II I
1
3
4
7 8
15
C :;: O-TSLC. Intended for general Channel/Device status testing.
C :;: 1_TSLF. Intended for general Channel/Device status testing, followed by
resetting the addressed status line(s) to zero on the same instruction.
K :;: Data Channel Designator, 0 to 7.
D:;: Peripheral Device Designator, 1 to 15.
L :;: M field allocated for:
1.
Testing Channel conditions, if D :;: O.
2.
Testing Peripheral Device conditions, if. D f O.
A4-3
APPENDIX 4
TABLE OF SFL/TSL CODES
SFL/TSL INSTRUCTIONS FOR TYPEWRITER OPERATIONS
D
L
'r~--------~'rr----------~--------~,
K
C ,
SFL(C) "M"
1 0 II
I
I
I II
I~ f I I
o
II III III
15
P
N
CFR
D
K
SFL(F) "M"
i~/Ol
~,-_-...-_-,J'-.,J
o
Set Additional
Channel/Device
Control Conditions
1,.-----''-------~1/01~1-1-----'I1"'"'"---1-1-----I1
J~
\
N
Initialize Channel/
Connect Device and
Clear Channel/Device
15
p
K=Ot07
D = (N)p = (3)0
Function
"L" Code/CFR
Comments
Set Ribbon Black
SFL(C)
X X X X X X X 1
Normal state when Data
Channel is cleared or
disconnected.
Set Ribbon Red
SFL(C)
X X X X X X 1 X
Initialize Channel/
Connect Device
CFR
(Channel transfer
conditions, data format.)
Indicators
Affected
None
None
Permits input or output
to Typewriter. Unlocks
keyboard for input.
Channel Signal
Channel Parity
Channel Interrupt
TSL Instructions
There are no TSL instructions associated directly with Typewriter status signals. Parity error
and certain Signals (carriage return, illegal control character) are tested via the Channel Parity
and Channel Signal indicators, respectively.
A4-4
TABLE OF SFL/TSL CODES
APPENDIX 4
SFL/TSL INSTRUCTIONS FOR PAPER TAPE READER OPERATIONS
C
SFL(C) "M"
K
D
Io I I I I'----v---l"--'
I I !! I I I I I I I I I
0
N
K
C
SFL(F) "M"
L
A_ _ _ _ _ _ _.......,
~~f
o
K=Ot07
D = (N)p = (1)0
15
P
D
CFR
.
,---A----,~,
11 I
A
\
I I I'---v----J'-.rJ
III III III III
15
N
Set Up Channell
Device Control
Conditions
Initialize Channell
Connect Device or
Disconnect Channell
Device
P
x - Don't Care Bits
Comments
Indicators
Affected
Function
"L" Code/CFR
Set Reader Forward
SFL(C)
X X X X X X X 1
Set direction of tape
motion to Forward.
Device "Busy"
response sets
"Busy" flag if
tape in motion.
Set Reader Reverse
SFL(C)
X X X X X X 1 X
Set direction of tape
motion to Reverse.
As Above
Initialize Channel/
Connect Device
SFL(F)
CFR
Connects Reader to Data
Channel and starts tape
motion.
Channel Parity
Channel Signal
Channel Interrupt
Stop Code
Device "Busy" if
Power off or
Reader in "Load"
state.
TSL Instructions
No status lines are tested via TSL instructions directly.
A4-5
APPENDIX 4
TABLE OF SFL/TSL CODES
SFL/TSL INSTRUCTIONS FOR PAPER TAPE PUNCH OPERATIONS
C
SFL(C)
K
D
J.
~
r~
L
J._ _ _ _ _ _ _--,.
v
~(
,
"M"I I I I I"---v---'Y
I I Ii I I I I I I I I I
N
C
SFL(F) "M"
P
CFR
D
K
J.
~rr----~A~------,."
11 I
Set Additional
Channel/Device
Control Conditions
III II
111/°1
~y
N
II III III
Initialize Channel/
Connect Device or
Clear Channel/Device
P
K=Ot07
X - Don't Care Bits
D = (N)p = (2)0
Function
"L" Code/CFR
Comments
Indicators
Affected
Power On
SFL(C)
X X X X X X 1 X
None
Power Off
SFL(C)
X X X X X X X 1
None
Initialize Channel/
Connect Device
SFL(F)
CFR
(Channel data transfer conditions, format, etc.)
Set up Channel transfer
conditions, connect
Punch and start data
transfer if Channel and
Punch are ready.
"Busy" flag in
Flag Register if:
a) Power off and
b) Tape is low.
Channel Parity
Channel Signal
Channel Interrupt
TSL Instructions
There are no status levels tested by TSL instructions.
A4-6
APPENDIX 4
TABLE OF SFL/TSL CODES
SFL INSTRUCTION LIST (FUNCTIONS AND CODES)
SERIAL (COLUMN-BY-COLUMN) CARD PUNCH
C
K
D
L
~~(r_ _ _ _ _--'J.",_ _ _ _ _- "
II III III III III III
01
34
15
78
'--y----Jy
N
P
M field
C = O-SFLC - Used to Set Channel/Device Control Conditions
C ::r: 1---SFLF - Used to Initialize Channel, Connect Device,
Unconditional Channel/Device Disconnect (D = 0)
K = Data Channel Number, 0 to 7
D = Device Number; Card Punch Device No. = (N)p = (2)1
L = M Field Allocated for Setting of Data Channel Function Register,
CFR (C = 1) or Device Control Conditions (D, C = 0)
X = Don't Care
Function
Start Card
. Punch Cycle
SFLC
or
SFLF 8
CFR (for SFLF
or L (for SFLC)
9 10 11 12 13 14 15
SFLC X XX XX X X 1
Start Card
Punch Cycle
and Connect
Punch (Cont)
to Data
Channel
SFLF
Eject Card*
(Terminate
Card Cycle)
SFLC XX XX 1 X X X
Reject (Offset) Card
Set DINE
Flip-Flop
(DINE = Dev.
Interrupt
Enable)
Comments
Program
Indicators
Affected
Initiate "Card Punch "Busy" Flag. See
Cycle" w/o connect- other sections for
ing CP Controller to conditions.
Data Channel.
Initiate "Card Punch See, other sections
Cycle" and connect
for conditions.
'X XX XX XX X CP controller to
Data Channel.
CFR
A
,
I
I,
,
SFLC XX XX X X 1 X
SFLC
1 X X X X X X X
Card ejected to output hopper after
punching previous
column. Next card
brought to Reg.
Station - - waiting
for next "Start Card
Punch Cycle"
command.
Ejected mispunched
card appears offset
by 1/2 inch output
hopper.
Set Dev. Int. Enable
flip-flop to allow
Dev. Int. when Dev.
is NOT selected,
DINE flip-flop set
and Card Punch is
ready for next Card
Punch Cycle.
Non~
Uncdnditional
Command
"
"
None
Unconditional
Command
"Busy',' Flag,
if DINE flip-
flop could not be
set.
*A card is also ejected in response to "Carriage Return" character, (155)8' This character
is not punched.
A4-7
TABLE OF SFL/TSL CODES
APPENDIX 4
TSL INSTRUCTION LIST (FUNCTIONS AND CODES)
SERIAL (COLUMN-BY-COLUMN) CARD PUNCH
K
D
C ~,
L
J.
I
I II I I II I I ;;
o
= 0,
N
I
I II I I II I I I
3~~8
1
M Field
C
J.
II
15
P
Test Only, TSLC
C = 1, Test and Reset, TSLF
K
= Data Channel Number,
0 to 7
D = Device Number; Card Punch Controller Code = (N)p = (2)1
L
= Channel/Device Control Field
A4-8
= 0)
L Field
TSLC
or
TSLF
8
9 10
Test "Card
Punch Operable" Status
TSLC
X
X
X
Test "Card
Punch Cycle"
Status
TSLC
X
X
Test "Binary
Mode" Status
TSLC
X
Test "End of
Card" Status
TSLC
Test "Punch
Error" Status
TSLF
Function
(Channel Field if D
11 12
13
14
15
Comments
X
X
X
X
1
See other section for definition
when Signal is true.
X
X
X
X
1
X
This line becomes true on start
of new card cycle (in response
to SFL command) and is reset
when card is ejected.
X
1
X
X
X
X
X
This line is "true" when the card
is being punched in "Binary Mode"
and "false" when card is being
punched in "Hollerith Mode. "
X
X
X
X
X
1
X
X
This line becomes true on ejection
of card and remains true until next
card is in Register Station. Start
"Card Punch Cycle" SFL commands
will be rejected during this period.
X
X
X
X
1
X
X
X
This line becomes true when an
error ( E'Echo-check'j error or
"overflow") is detected on punching a particular column. The
Punch Controller will ej ect the
card in response to the Punch
"next column data request. "
Data Channel will be disconnected and an interrupt generated.
APPENDIX 4
TABLE OF SFL/TSL CODES
SFL INSTRUCTIONS FOR CARD READER OPERATIONS
L
D
K
C ~r.---J."'-----"H"'-----oA_------,
SFL(C) "M"
Io I I I /I I I Ii I I /I I I I I I I
0
l
T
Jl
J
-y-
N
P
D
K
C~r
SFL(F) "M"
CFR
D = (N)p =(1)1
Function
.1
H
i
,
1o I I I I I !! I I I I I " I I I
1
"
~y
N
K=Oto7
15
Set Up Additional
Channel/Device
Control Conditions
15
P
Initialize Channel/
Connect Device and
Disconnect Channel/
Device
x = Don't Care Bit Positions,
Combined Operations Possible
"V' Code/CFR
Comments
Indicators
Start Card
Cycle SFL(C)
X X X X X X X 1
A card is started on its
way to Read Station. An
SFL(F) must follow within a period of time to enable reading.
Device "Busy" setting
"Busy" Flag if Card
Cycle in Progress or
Card Reader not Ready.
Initiate
Channel/Connect Device
SFL(F) Instruction
CFR (Data Channel
Options)
Connects Card Reader
to Data Channel initiates
"Card Cycle" if not already started. Cards
are read continuously
until Data Channel is
disconnected.
Channel Signal, Channel
Interrupt, Channel
Parity
Disconnect
Power from
Card Reader
SFL(C)
X X X X X 1 0 X
Disconnect Power when
Reader not expected to
be used for some time.
No Device "Busy" Response
Set "Device
Interrupt
Enable"
(DINE) FlipFlop
1 X X X X X X X
Enables Channel Interrupt if Reader is Ready
for next card cycle, (i. e.,.
Card Reader Ready =
"Busy" response if any
device already selected
on this Data ChanneL
"1").
NOTE: The two different instructions to start a card cycle are available to permit the use
of Data Channel with other devices on the channel while a card is being moved
relatively slowly into "read station".
A4-9
APPENDIX 4
TABLE OF SFL/TSL CODES
TSL INSTRUCTIONS FOR LINE PRINTER OPERATION
K
D
C~I
TSL "M"
L
A
V
A
,
I I I I I I I ; 1/°1 I I I I I I I I
°
'---y---A-y-J
N
15
P
D = (N)p = (3)1
C = 0, Test Status Line Only
C = 1, Test Status Line, Then Clear Status Indicator
X = 0, Unless Combined Test Specified
Function
"L" Field
Status Definition and/or Comments
Test Printer Ready
X X X X X 1 X X
Printer in operable condition. Power
turned on. "Operate-Standby" switch on
Operator Panel in "operate" position, down
gate is closed. Paper is in printing position.
Next Character
Request (=Send
Data)
X X X X X X X 1
Printer available to accept next character.
The line will be false during printing or
paper spaCing operations.
Next Line Request
X X X X X X 1 X
Printing of previous line is complete. The
Printer is ready for next line.
Printer Buffer Full
X X X X 1 X X X
132 characters transmitted to Printer
Buffer without print (end of message) command.
Paper AdvanCing
X X X 1 X X X X
Paper advanCing not complete.
A4-10
TABLE OF SFL/TSL CODES
APPENDIX 4
SFL INSTRUCTIONS FOR PARALLEL (ROW-BY-ROW)
CARD PUNCH OPERATIONS
D
K
SFL(C)
I~ If I I 1"'--1--"--1
1,.--1-11-1--"--I-II-I-----I1
-----::110
o
11 I
o
CFR
D
){"
"\
I I I I I !! I I I I I I I I I
15
"'-.,-J
N
Set Channel/DeVice
Control Conditions
15
'"...._.....,..._~J'-.,-J
N
P
K
C(
SFL(F)
L
P
Initialize Channel/
Connect Device, Clear
Channel
K=Ot07
D
= (N)p = (2)1
x
= Don't Care Unless Combined Operation Desired
= Device #
Function
"L" Code/CFR
Comments
Indicators Affected
Start Card
Punch Cycle
X X X X X X X 1
Start card on its way
to Punch Station.
Stop after one card
moved unless Punch
connected to Data
Channel.
Device "Busy" response if
a) Punch not Ready
b) Power to Punch off.
Reject Card
to AUX Stacker
X X X X X X 1 X
The card being
punched to be
ejected to AUX
Stacker.
None
Initialize
Channel/
Connect
Device
CFR
Permits data transfer
and punch operation.
Allows bringing next
card into punch
station if Channel/
Device not discon..
nected.
Set "Device
Interrupt
Enable"
(DINE) FlipFlop
1 X X X X X, X X
Permits an Interrupt
when device becomes
operable again following some failure.
Device "Busy" response
if instruction is too 'late
to punch complete card.
Channel Signal, Channel
Parity, Channel Interrupt.
Channel Interrupt "Busy"
response if at least one
device already connected
to channel.
A4-11
TABLE OF SFL/TSL CODES
APPENDIX 4
TSL, INSTRUCTIONS FOR CARD READ OPERATION
K
D
C~~f
TSL "M"
L
"
Io " I I I"---v----..J
I I Ii I
'-v-'
N
P
,
I I I I I I I I
15
C = 0, Test Only
C = 1, Test and Clear
D = (N)p, K = 0 to 7
= (1)1
x = Don't Care Conditions Unless Combined Tests Requested
Function
"L" Code
Status Definition and/or Comments
Test "Card Reader
Ready" Status
X X X X X X
Test "Read Cycle in
Progress" Status
X X X X X
Test "Hopper Empty" X X X X
Status
1 X
1 X X
Response to "Start Card Cycle" command.
"True" until all 80 columns are read. New
card cycle initiated, after some delay when
this Signal goes "False" provided Data
Channel remains connected.
1 X X X
True when hopper is empty and End of File
button has been depressed.
Test "Reader Error"
Status
X X X
Test "Overflow"
Status
X X
Test "Binary Card"
Status
X X X X X X X
Test "Card Reader
Continue" Status
X
A4-12
No jams. Stacker not full. Covers in place.
Power on. Start button depressed. Feeder
ready (Model 1). Read Circuits OK. Card
line mechanism locked (Model 1). Hopper
not empty. No character validity error.
1 X X X X
1 X X X X X
1
1 X X X X X X
A photo cell malfunctioning or invalid
character detected (Hollerith Mode) - if
validity switch is on.
A character has been missed. Once a card
cycle is initiated characters are available
at fixed intervals.
The card being read is a "Binary Card".
Card Reader has been put on-line again and
the operator has depressed "Card Reader
Continue" button.
TABLE OF SFL/TSL CODES
APPENDIX 4
SFL INSTRUCTIONS FOR LINE PRINTER OPERATION
K
D
L
C ~~r'----~~'------'l
SFL( C) "M"
I 0 II
I
I
II
o
I
111/ 0 1
I
L-.,---Jy
N
I
I I
15
11
"
SFL( F) "M"
l......~v---'Jt.y-1
o
I
Set Up Channel/
Device Operating
Conditions
CFR
D
H
A
I
I
P
K
Cr
I I
I I I I I I I I
15
Initialize Channel/
Connect Device or
Clear Channel Device Conditions
P
N
K=Oto7
D = (N)p = (3)1
X = Don't Care Bit Positions
Function
"L" Code/CFR
Initialize Channell
Connect Device
SFL(F)
CFR
,
L
(
1
Set "Device Interrupt Enable" (DINE)
Flip-Flop
Advance Carriage
to Control Tape
Hole on Channell
Comments
o
,
X X X X X X
Connects Printer to
Data Channel and makes
the latter responsive to
Signals from the Printer
buffer.
Indicators
Affected
Device "Busy" response if Printer
is not ready.
Enables Channel Interrupt Device Busy if
DES=="l".
Top of Form
X
1 X X 0 0 0
2
X 1 X X 0 0 0
11
X 1 X X 0 0 1
4
X
1 X X
5
X
1 X X 0 1 0
0
6
X
1 X X 0 1 0
1
7
X
1 X X
0 1 1
0
8
X
1 X X 0 1 1
1
Adv. Carr. by 1 Line X
0 0 1
0
1 Different tapes available to suit particular
0
format requirements.
1
1 0 0 X Permit direct paper
spacing control with0 out reference to tape
1 loop.
1 X X
2
X
3
X
1 X X 1 0 1
1 X X 1 0 1
4
X
1 X X
5
X
1 X X 1 1 0
6
X 1 X X
7
X
1 1 0
1 1 1
1 X X
"1" in this Position
Specifies Paper
Space Instructions
~
Disable Auto Carriage Advance on
1st Character of a
Line
0
o
.
L
1 1 1
I
X XX X X
Device "Busy" response if a) printing cycle not complete b) previous
space operations
not complete.
Same as in previous
case.
0
1
0
1
I
The same codes are
used to obtain paper
spacing by 1st character in a line.
1 To permit overprinting
of a line if desired.
Device "Busy" response if paper
spacing taking place.
A4-13
APPENDIX 4
TABLE OF SFL/TSL CODES
TSL INSTRUCTIONS FOR PARALLEL (ROW-BY-ROW)
CARD PUNCH OPERATION
D
K
C (
11/ 0
0
•
1 I I I
\
L
A
\(
•
"
I, I
I~
N
P
::1/01
I
I
I I I
\
II I
15
K=Ot07
D = (2)1 = (N)p = Device Number
C = 0 Test Status Level Only
C = 1 Test Status and Then Reset Status Flip-Flop
X = Don't Care Bits, Unless Combined Tests Desired
Function
A4-14
"L" Code
Status Definition and Comments
Test "Punch Ready" Status
X X X X XX X 1
Cards in hopper. Die in place. Card line
mechanism locked up. Card in position to
be punched. Stacker not full. Power on.
No jam condition. Covers are in place.
No punch error.
Test "Ready to Punch Next
Row" Status
X X X X Xl X X
Punch is ready to punch next row on card.
Test "Punch Cycle" Status
X X X X XX 1 X Card is in punch cycle. Status remains
true for the duration of punching a card.
Test "Punch Error" Status
X X X X 1 X X X An invalid Hollerith character punched.
Inhibited in "BIN" mode.
APPENDIX 4
TABLE OF SFL/TSL CODES
TSL INSTRUCTION LIST AND CODES FOR MAGNETIC TAPE OPERATIONS
K
D
L
C ,---A.-----.~,.
TSL
"M"
A
,
Io I I I I I I ; I I I I I I I I I
15
D = (N)p = (4)0
K=Ot07
X = 0, Unless "Combined" Tests Preferred
If C = 0 Test Only
If C = 1 Test and Clear Status Indicator
"L" Field
Function
Test and Clear End
1
of Record Indicator
o
Status Definition and/or Comments
X X X X X
1
This indicator is needed only to enable
programmer to test whether EOR has been
reached when Data Channel is not connected
to tape unit.
Test and Clear End
of File Indicator
1 0 X X X X
Test and Clear
Overflow Indicator
1 0 X X X
Test if Tape Unit
Ready
1 0 X X
Test if Tape is at
Load Point (BOT)
1 0 X
Test if End of Tape
(EOT) has been
Reached
1 0 1 X X X X X
End of tape tab has passed the photo sense
head.
Test if File-Protect
is On
1 1 X X X X
Tape unit is loaded with reel equipped with
a file-protect ring.
Test for High Density
1 1 X X
Test for Medium
Density
1 1 X
Test if Tape Unit is
Rewinding
0 1 X X X
Unit 0
to 7
The unit addressed is in the Rewinding state.
A number of tape units can be in the Rewinding status at the same time.
Test if selected tape
unit is set for 7track mode.
1 1 X X X
1 X X
This test is relevant when both the 7 -track
and the 9-track features are available in a
particular Magnetic Tape System.
1 X
1 X X
1 X X X
1 X X X X
1 X
1 X X X
1 X X X X
Set up by EOF marker in Read or Write
(by Check head) operations.
Set up when Character is missed in Read
operation or is late (Rate check) in Write
operation.
Tape Unit is ready to accept a new instruction.
Load point tab is at photo sense head.
Tape unit selected for High Density (800 bpi)
recording.
Tape unit selected for Medium Density
(556 bpi) recording.
A4-15
APPENDIX 4
TABLE OF SFL/TSL CODES
SFL INSTRUCTION LIST AND CODES FOR MAGNETIC TAPE OPERATIONS
D
K
C~~I
SFL(C) "M"
lo~
0
C
SFL(F) "M"
I
I
II
I
~1/01
I
'---v-/'-..r'
A
I
I II
I
,
I
P
N
D
K
~~I
It/!0 I I II I I
:[1/01
'----v--''-..rJ
P
N
FWD/REV
F/R
W/R
D
L
= Forward/Reverse Motion
= File/Record
= Write/Read
=(N)p = (4)0
Set Up Channel/
I_DeVice Operating
Conditions (Other
I
than CFR)
15
CFR
A
I I I I I 1 I 15I
,
X't:: 0, Unless "Combined" Operations Required
"L" Code or CFR
Indlcators
Comments
Function
~led)
Control Fwd/Rov' F/R w/R Unit #
1. Read Record(s)
FWD
0
1
0
0
0
0107
Read record and enable data transfer if
Channel Initialized
and Device connected.
otherwise skip one
record.
Channel Parity, Channel Signal, Channel
Interrupt, EOR, EOT,
Overfiow.
2. Read Record(s)
REV
0
1
1
0
0
0107
As 1 but tape moves
in REV direction.
As in 1 but BOT instead
of EOT.
3. Search End of
FUeFWD
0
1
0
1
,0
0107
As In 1 but Channel
EOT, EOF
4. Search End of
0
1
1
1
0
Oto 7
BOT, BOF
FUeREV
5. Write Record(s)
(FWD Only)
As in 3 hut tape moves
in REV direction.
0
1
0
0
1
o to 7
Write a record after
Channe1lnltlalize/
Device Connect Instr.
and write LPC at end
of record (word. count
= 0).
Channel Parity, Channel Signal, Channel Interrupt, EOR, EOT J
Overflow
6. Write Blank
Tape (=Erase)
FWD
0
1
0
1
1
o to 7
Write as in 5 but re-
Channel Parity (H tape
not blank), EOT
7. Set Unit Field
0
o to 7
Set up the unit field of
control register, but
InltiaUze/Devtce
Connect Instr. omitted. Stop after one
record. Search for
File Mark instead of
End of Record.
cord "an zero" characters. Stop tape after 3-3/4 Inches.
0
0
0
0
do not initiate any tape
operat1on to allow testing of se1. unit status.
8. Write End of
File
1
1
0
1
1
0107
Write EOF mark and
EOF,EOT
its LPC, (17}8 in both
cases, under control of
Tape Controller.
9. Rewind 10 Load
0
0
1
1
0
0107
Initiate Rewind opera-
BOT
tlon via a trigger.
Point
Transfer to other tape
units not inhibited while
rewinding.
10. Rewlnd and Unlock
O
0
1
11. Initialize Channel Connect Deviee
1
1
0107
As in 9 but tape unit
switched to "LOCAL"
mode.
BOT
This instruction enables "Busy" flag If data
data transfer and makes transfer not possible at
that· time. "
channel responsive to
CFR
Device signals.
12. Set "Device Interrupt Enable"
(DINE) FlIpFlop
A4-16
1
0
X
Initialize Channell
Connect Device or
- - Clear Channel/Device Conditions
X
X
X
Allow channel inter"Busy" response if any
rupt when MT becomes device on this Data
operable again and this Channel already conflip-flop is set.
nected for data transfer
(DES flip-flop set).
APPENDIX 5
CHARACTER CODE EQUIVALENCE TABLE
Char.
0
1
2
3
4
5
6
7
8
9
1)
=
,
:
J+
A
B
C
D
E
F
G
H
I
?
.
)
[
<
$
Card
Punch
(Hollerith)
0
1
2
3
4
5
6
7
8
9
2-8
3-8
4-8
5-8
6-8
7-8
12
12-1
12-2
12-3
12-4
12-5
12-6
12-7
12-8
12-9
12-0-8
12-3-8
12-4-8
12-5-8
12-6-8
12-7-8
Octal
** *
00
04
10
14
20
24
30
34
40
44
50
54
60
64
70
74
100
104
110
114
120
124
130
134
140
144
150
154
160
164
170
174
00
01
02
03
04
05
06
07
10
11
12
13
14
15
16
17
20
21
22
23
24
25
26
27
30
31
32
33
34
35
36
37
Hex
00
01
02
03
04
05
06
'07
08
09
OA
OB
OC
OD
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
Char.
.
J
K
L
M
N
0
P
Q
R
!
$
*
J
;
t::.
Blank
/
S
T
U
V
W
X
y
Z
f-
,
(
n
\
~
Card
Punch
(Hollerith)
11
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
11-0-8
11-3-8
11-4-8
11-5-8
11-6-8
11-7-8
No Punch
0-1
0-2
0-3
0-4
0-5
0-6
0-7
0-8
0-9
0-2-8
0-3-8
0-4-8
0-5-8
0-6-8
0-7-8
Octal
**
*
Hex
200
204
210
214
220
224
230
234
240
244
250
254
260
264
270
274
300
304
310
314
320
324
330
334
340
344
350
354
360
364
370
374
40
41
42
43
44
45
46
47
50
51
52
53
54
55
56
57
60
61
62
63
64
65
66
67
70
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
71
72
73
74
75
76
77
,
CARRIAGE RETURN
TAB
BACKSPACE
UPPER CASE
LOWER CASE
INDEX
STOP CODE
664
764
670
470
770
764
400
155
175
156
116
136
135
100
*
= Right 8 Bit Byte in Each Half-Word
** =Left 8 Bit Byte in Each Half-Word
A5-1/A5-2
APPENDIX 6
POWERS OF TWO
2n n
1
2
4
8
0
1
2
3
1.0
0.5
0.25
0.125
16
32
64
128
4
5
6
7
'0.062
0.031
0.015
0.007
256
512
1 024
2 048
8
9
10
11
0.003
0.001
0.000
0.000
906
953
976
488
25
125
562 5
281 25
5
25
625
812 5
4
8
16
32
096
192
384
768
12
13
14
15
0.000
0.000
0.000
0.000
244
122
061
030
140
070
035
517
625
312 5
156 25
578 125
65
131
262
524
536
072
144
288
16
17
18
19
0.000
0.000
0.000
0.000
015
007
003
001
258
629
814
907
789
394
697
348
062
531
265
632
5,
25
625
812 5
1
2
4
8
048
097
194
388
576
152
304
608
20
21
22
23
0.000
0.000
0.000
0.000
000
000
000
000
953
476
238
119
674
837
418
209
316
158
579
289
406
203
101
550
25
125
562 5
781 25
16
33
67
134
777
554
108
217
216
432
864
728
24
25
26
27
0.000
0.000
0.000
0.000
000
000
000
000
.059
029
014
007
604
802
901
450
644
322
161
580
775
387
193
596
390
695
847
923
268
536
1 073
2 147
435
870
741
483
456 28
912 29
824 30
648 31
625
312 5
656 25
828 125
0.000 000 003 725
0.000 000 001 862
0.000 000 000 931
0:000000000465
290 298
645 149
322 574
661,287
461 914
230 957
615 478
307'739
062
031
515
257
5
25
625
812 5
4
8
17
34
294
589
179
359
967
934
869
738
296
592
184
368
32
33
34
35
0.000
0.000
0.000
0.000
000
000
000
000
000
000
000
000
232
116
058
029
830
415
207
103
643
321
660
830
653
826
913
456
869
934
467
733
628
814
407
703
906
453
226
613
25
125
562 5
281 25
68
137
274
549
719
438
877
755
476
953
906
813
736 36
472 37
944 38
888 39
0.000
0.000
0.000
0.000
000
000
000
000
000
000
000
000
014
007
003
001
551
275
637
818
915
957
978
989
228
614
807
403
366
183
091
545
851
425
712
856
806
903
951
475
640
320
660
830
625
312 5
156 25
078 125
TABLE POWERS OF TWO
A6-1/A6-2
APPENDIX 7
OCTAL-DECIMAL INTEGER CONVERSION
0000
0000
to
to
0777
0511
(Octal)
(Decimal)
Octal Decimal
10000 - 4096
20000 - 8192
30000 - 12288
40000 - 16384
50000 - 20480
60000 - 24576
70000 - 28672
1000
0512
to
to
1777
1023
(Octal)
(Decimal)
.0
1
2
3
4
5
6
7
0000
001.0
0020
0030
0040
0050
0060
0070
0000
0008
0016
0024
0032
0040
0048
0001
0009
0017
0025
0.033
0041
0049
0057
0002
0010
0018
0026
0034
0042
0050
0058
0003
0011
0019
0027
0035
0043
0051
0059
0004
0012
0020
0028
0036
0044
0052
0060
0005
0013
0021
0029
0037
0045
0053
0061
0006
0014
0022
0030
0036
0046
0054
0062
0015
0023
0031
0039
0047
0055
0063
0100
0110
0120
0130
.0140
0150
0160
017.0
0064
0072
0060
0088
0096
0104
0112
.0120
0066
0074
0082
0090
00~7 0098
0105 0106
0113 0114
0121 .0122
0067
0075
b083
0091
0099
0107
0115
.0123
0068
0076
0084
0092
0100
0108
0116
0124
0069
0077
0065
0093
0101
0109
0117
0125
0070
0078
0086
0094
0102
0110
0118
0126
0200
0210
0220
0230
0240
0250
0260
.0270
0128
0136
0144
0152
0160
0168
0176
0184
0129
0137
0145
0153
0161
0169
0177
0185
0130
0138
0146
0154
0162
0170
0176
0186
0131
0139
0147
0155
0163
0171
0179
0187
.0132
0140
0148
0156
0164
0172
0180
0188
0133
0141
0149
0157
0165
0173
0181
0189
0300
0310
0320
0330
0340
0350
0360
0370
0192
0200
0208
0216
0224
0232
0240
0248
0193
0201
0209
0217
0225
0233
0241
0249
0194
0202
0210
0218
0226
0234
0242
0250
.0195
0203
0211
0219
0227
0235
0243
0251
0196
0204
0212
0220
0226
0236
0244
0252
0
1
2
3
095~
0065
0073
0081
0089
0
1
2
3
4
5
6
7
0400
0410
0420
0430
0440
0450
0460
0470
0256
0264
0272
0260
0268
0296
0304
0312
0257
0265
0273
0281
0269
0297
0305
0313
.0258
0266
0274
0262
0290
0296
0306
0314
0259
0267
0275
0263
0291
0299
0307
0315
0260
0268
0276
0284
0292
0300
030Q
0316
0261
0269
0277
0285
0293
0301
0309
0317
0262
0270
0278
0286
0294
0302
0310
0318
0263
0271
0279
0267
0295
0303
0311
0319
0071
0079
0087
0095
0103
0111
0119
0127
0500
0510
0520
0530
0540
0550
0560
0570
0320
0326
0336
0344
0352
0360
0368
0376
0321
0329
0337
0345
0353
0361
0369
0377
0322
0330
0338
0346
0354
0362
0370
0376
0323
0331
0339
0347
0355
0363
0371
0379
0324
0332
0340
0346
0356
0364
0372
0380
0325
0333
0341
0349
0357
0365
0373
0361
0326
0334
0342
0350
0356
0366
0374
0382
0327
0335
0343
0351
0359
0367
0375
0383
0134
0142
0150
0158
0166
0174
0182
0190
0135
0143
0151
0159
0167
0175
0183
0191
0600
0610
0620
0630
0640
0650
0660
0670
0364
0392
0400
0408
0416
0424
0432
0440
0365
0393
0401
0409
0417
0425
0433
0441
0366
0394
0402
0410
0416
0426
0434
0442
0367
0395
0403
0411
0419
0427
0435
0443
0368
0396
0404
0412
0420
0428
0436
0444
0389
0397
0405
0413
0421
0429
0437
0445
0390
0396
0406
0414
0422
0430
0438
0446
0391
0399
0407
0415
0423
0431
0439
0447
0197
0205
0213
0221
0229
0237
0245
0253
0198
0206
0214
0222
0230
0236
0246
0254
0199
0207
0215
0223
0231
0239
0247
0255
0700
0710
0720
0730
0740
0750
0760
0770
0448
0456
0464
0472
0460
0466
0496
0504
0449
0457
0465
0473
0461
0489
0497
0505
0450
0456
0466
0474
0482
0490
0498
0506
0451
0459
0467
0475
0463
0491
0499
0507
0452
0460
0468
0476
0464
0492
0500
0508
0453
0461
0469
0477
0465
0493
0501
0509
0454
0462
0470
0478
0486
0494
0502
0510
0455
0463
0471
0479
0467
0495
0503
0511
4
5
6
7
0
1
2
3
4
5
6
7
0516
0524
0532
0540
0548
0556
0564
0572
0517
0525
0533
0541
0549
0557
0565
0573
0516
0526
0534
0542
0550
0556
0566
0574
0519
0527
0535
0543
0551
0559
0567
0575
1400
1410
1420
1430
1440
1450
1460
1470
0766
0776
0764
0792
0600
0806
0816
0624
0769
0777
0765
0793
0801
0809
0617
0625
0770
0776
0786
0794
0602
0610
0616
0826
0771
0779
0787
0795
0603
0611
0619
0627
0772
0780
0766
0796
0804
0812
.0620
0826
0773
0761
0789
0797
0605
0613
0821
0629
0774
0762
0'(90
0796
0606
0614
0622
0830
0775
0783
0791
0799
0807
0615
0823
0831
bo07
1000
10to
1020
1030
1040
1050
1060
1070
0512
0520
0526
0536
0544
0552
0560
0566
0513
0521
0529
0537
0545
0553
0561
0569
0514
0522
0530
0536
0546
0554
0562
0570
0515
0523
0531
0539
0547
0555
0563
0571
1100
1110
1120
1130
1140
1150
1160
1170
0576
0564
0592
0600
0606
0616
0624
0632
0577
0565
0593
0601
0609
0617
0625
0633
0576
0566
0594
0602
0610
0618
0626
0634
0579
0567
0595
0603
0611
0619
0627
0635
0560
0586
0596
0604
0612
0620
0628
0636
0581
.0589
0597
0605
0613
0621
0629
0637
0562
0590
0598
0606
0614
0622
0630
0638
0583
0591
0599
0607
0615
0623
0631
0639
1500
1510
1520
1530
1540
1550
1560
1570
0832
0640
0648
0656
0664
0872
0660
0886
0833
0641
0649
0657
0865
0673
0881
0889
0634
0642
0650
0656
0666
0874
0662
0690
0635
0643
0651
0659
0667
0875
0863
0691
0636
0644
0852
0660
0866
0676
0884
0692
0637
0645
0853
0861
0669
0877
0685
0693
0838
0846
0854
0662
0870
0678
0886
0694
0839
0647
0655
0663
0871
0679
0887
0895
1200
1210
1220
1230
1240
1250
1260
1270
0640
0646
0656
0664
0672
0680
0688
0696
0641
0649
0657
0665
0673
0681
0669
0697
0642
0650
0658
0666
0674
0682
0690
0698
0643
0651
0659
0667
0675
0683
0691
0699
0644
0652
0660
0668
0676
0684
0692
0700
0645
0653
0661
0669
0677
0685
0693
0701
0646
0654
0662
0670
0676
0666
0694
0702
0647
0655
0663
0671
0679
0667
0695
0703
1600
1610
1620
1630
1640
1650
1660
1670
0896
0904
0912
0920
0926
0936
0944
0952
0897
0905
0913
0921
0929
0937
0945
0953
0898
0906
0914
0922
0930
0938
0946
0954
0699
0907
0915
0923
0931
0939
0947
0955
0900
0906
0916
0924
0932
0940
0946
0956
0901
0909
0917
0925
0933
0941
0949
0957
0902
0910
0918
0926
0934
0942
0950
0956
0903
0911
0919
0927
0935
0943
0951
0959
1300
1310
1320
1330
1340
1350
1360
1370
0704
0712
0720
0728
0736
0744
0752
0760
0705
0713
0721
0729
0737
0745
0753
0761
0706
0714
0722
0730
0738
0746
0754
0762
0707
0715
0723
0731
0739
0747
0755
0763
0708
0716
0724
0732
0740
0746
0756
0764
0709
0717
0725
0733
0741
0749
0757
0765
0710
0716
0726
0734
0742
0750
0758
0766
0711
0719
0727
0735
0743
0751
0759
0767
1700
1710
1720
1730
1740
1750
1760
1770
0960
0966
0976
0984
0992
1000
1008
1016
0961
0969
0977
0965
0993
1001
1009
1017
0962
0970
0978
0966
0994
1002
1010
1018
0963
0971
0979
0987
0995
1003
1011
1019
0964
0972
0980
0988
0996
1004
1012
1020
0965
0973
0961
0989
0997
1005
1013
1021
0966
0974
0982
0990
0998
1006
1014
1022
0967
0975
0983
0991
0999
1007
1015
1023
Octal-Decimal Integer Conversion Table (Sheet 1 of 7)
A7-1
OCTAL-DECIMAL INTEGER CONVERSION
APPENDIX 7
0
1
2
3
4
5
6
7
2400
2410
2420
2430
2440
2450
2460
2470
1280
1288
1296
1304
1312
1320
1328
1336
1281
1289
1297
1305
1313
1321
1329
1337
1282
1290
1298
1306
1314
1322
1330
1338
1283
1291
1299
1307
1315
1323
1331
1339
1284
1292
1300
1308
1316
1324
1332
1340
1285
1293
1301
1309
1317
1325
1333
1341
1286
1294
1302
1310
1318
1326
1334
1342
1287'
1295
1303
1311
1319
1327
1335
1343
1095
1103
1111
1119
1127
1135
1143
1151
2500
2510
2520
2530
2540
2550
2560
2570
1344
1352
1360
1368
1376
1384
1392
1400
1345
1353
1361
1369
1377
1385
1393
1401
1346
1354
1362
1370
1378
1386
1394
1402
1347
1355
1363
1371
1379
1387
1395
1403
1348
1356
1364
1372
1380
1388
1396
1404
1349
1357
1365
1373
1381
1389
1397
1405
1350
1358·
1366
1374
1382
1390
1398
1406
1351
1359
1367
1375
1383
1391
1399
1407
1158
1166
1174
1182
1190
1198
1206
1214
1159
1167
1175
1183
1191
1199
1207
1215
2600
2610
2620
2630
2640
2650
2660
2670
1408
1416
1424
1432
1440
1448
1456
1464
1409
1417
1425
1433
1441
1449
1457
1465
1410
1418
1426
1434
1442
1450
1458
1466
1411
1419
1427
1435
1443
1451
1459
1467
1412
1420
1428
1436
1444
1452
1460
1468
1413
1421
1429
1437
1445
1453
1461
1469
1414
1422
1430
1438
1446
1454
1462
1470
1415
1423
1431
1439
1447
1455
1463
1471
1221
1229
1237
1245
1253
1261
1269
1277
1222
1230
1238
1246
1254
1262
1270
1278
1223
1231
1239
1247
1255
1263
1271
1279
2700
2710
2720
2730
2740
2750
2760
2770
1472
1480
1488
1496
1504
1512
1520
1528
1473
1481
1489
1497
1505
1513
1521
1529
1474
1482
1490
1498
1506
1514
1522
1530
1475
1483
1491
1499
1507
1515
1523
1531
1476
1484
1492
1500
1508
1516
1524
1532
1477
1485
1493
1501
1509
1517
1525
1533
1478
1486
1494
1502
1510
1518
1526
1534
1479
1487
1495
1503
1511
1519
1527
1535
4
5
6
7
0
1
2
3
4
5
6
7
1539
1547
1555
1563
1571
1579
1587
1595
1540
1548
1556
1564
1572
1580
1588
1596
1541
1549
1557
1565
1573
1581
1589
1597
1542
1550
1558
1566
1574
1582
1590
1598
1543
1551
1559
1567
1575
1583
1591
1599
3400
3410
3420
3430
3440
3450
3460
3470
1792
1800
1808
1816
1824
1832
1840
1848
1793
1801
1809
1817
1825
1833
1841
1849
1794
1802
1810
1818
1826
1834
1842
1850
1795
1803
1811
1819
1827
1835
1843
1851
1796
1804
1812
1820
1828
1836
1844
1852
1797
1805
1813
1821
1829
1837
1845
1853
1798
1806
1814
1822
1830
1838
1846
1854
1799
1807
1815
1823
1831
1839
1847
1855
1602
1610
1618
1626
1634
1642
1650
1658
1603
1611
1619
1627
1635
1643
1651
1659
1604
1612
1620
1628
1636
1644
1652
1660
1605
1613
1621
1629
1637
1645
1653
1661
1606
1614
1622
1630
1638
1646
1654
1662
1607
1615
1623
1631
1639
1647
1655
1663
3500
3510
3520
3530
3540
3550
3560
3570
1856
1864
1872
1880
1888
1896
1904
1912
1857
1865
1873
1881
1889
1897
1905
1913
1858
1866
1874
1882
1890
1898
1906
1914
1859
1867
1875
1883
1891
1899
1907
1915
1860
1868
1876
1884
1892
1900
1908'
1916
1861
1869
1877
1885
189.3
1901
1909
1917
1862
1870
1878
1886
1894
1902
1910
1918
1863
1871
1879
1887
1895
1903
1911
1919
1665
1673
1681
1689
1697
1705
1713
1721
1666
1.674
1682
1690
1698
1706
1714
1722
1667
1675
1683
1691
1699
1707
1715
1723
1668
1676
1684
1692
1700
1708
1716
1724
1669
1677
1685
1693
1701
1709
1717
1725
1670
1678
1686
1694
1702
1710
1718
1726
1671
1679
1687
1695
1703
1711
1719'
1727
3600
3610
3620
3630
3640
3650
3660
3670
1920
1928
1936
1944
1952
1960
1968
1976
1921
1929
1937
1945
1953
1961
1969
1977
1922
1930
1938
1946
1954
1962
1970
1978
1923
1931
1939
1947
1955
1963
1971
1979
1924
1932
1940
1948
1956
1964
1972
1980
1925
1933
1941
1949
1957
1965
1973
1981
1926
1934
1942
1950
1958
1966
1974
1982
1927
1935
1943
1951
1959
1967
1975
1983
1729
1737
1745
1753
1761
1769
1777
1785
1730
1738
1746
1754
1762
1770
1778
1786
1731
1739
1747
1755
1763
1771
1779
1787
1732
1740
1748
1756
1764
1772
1780
1788
1733
1741
1749
1757
1765
1773
1781
1789
1734
1742
1750
1758
1766
1774
1782
1790
1735
1743
1751
1759
1767
1775
1783
1791
3700
3710
3720
3730
3740
3750
3760
3770
1984
1992
2000
2008
2016
2024
2032
2040
1985
1993
2001
2009
2017
2025
2033
2041
1986
1994
2002
2010
2018
2026
2034
2042
1987
1995
2003
2011
2019
2027
2035
2043
1988
1996
2004
2012
2020
2028
2036
2044
1989
1997
2005
2013
2021
2029
2037
2045
1990
1998
2006
2014
2022
2030
2038
2046
1991
1999
2007
2015
2023
2031
2039
2047
0
1
2
3
4
5
6
7
2000
2010
2020
2030
2040
2050
2060
2070
1024
1032
1040
1048
1056
1064
1072
1080
1025
1033
1041
1049
1057
1065
1073
1081
1026
1034
1042
1050
1058
1066
1074
1082
1027
1035
1043
1051
1059
1067
1075
1083
1028
1036
1044
1052
1060
1068
1076
1084
1029
1037
1045
1053
1061
1069
1077
1085
1030
1038
1046
1054
1062
1070
1078
1086
1031
1039
1047
1055
1063
1071
1079
1087
2100
2110
2120
2130
2140
2150
2160
2170
1088
1096
1104
1112
1120
1128
1136
1144
1089
1097
1105
1113
1121
1129
1137
1145
1090
1098
1106
1114
1122
1130
1138
1146
1091
1099
1107
1115
1123
1131
1139
1147
1092
1100
1108
1116
1124
1132
1140
1148
1093
1101
1109
1117
1125
1133
1141
1149
1094
1102
1110
1118
1126
1134
1142
1150
2200
2210
2220
2230
2240
2250
2260
2270
1152
1160
1168
1176
1184
1192
1200
1208
1153
1161
1169
1177
1185
1193
1201
1209
1154
1162
1170
1178
1186
1194
1202
1210
1155
1163
1171
1179
1187
1195
1203
1211
1156
1164
1172
1180
1188
1196
1204
1212
1157
1165
1173
1181
1189
1197
1205
1213
2300
2310
2320
2330
2340
2350
2360
2370
1216
1224
1232
1240
1248
1256
1264
1272
1217
1225
1233
1241
1249
1257
1265
1273
1218
1226
1234
1242
1250
1258
1266
1274
1219
1227
1235
1243
1251
1259
1267
1275
1220
1228
1236
1244
1252
1260
1268
1276
0
1
2
3
3000
3010
3020
303.0
3040
3050
3060
3070
1536
1544
1552
1560
1568
1576
1584
1592
1537
1545
1553
1561
1569
1577
1585
1593
1538
1546
1554
1562
1570
1578
1586
1594
3100
3110
3120
3130
3140
3150
3160
3170
1600
1608
1616
1624
1632
1640
1648
165.6
1601
1609
1617
1625
1633
1641
1649
1657
3200
3210
3220
3230
3240
3250
3260
3270
1664
1672
1680
1688
1696
1704
1712
1720
3300
3310
3320
3330
3340
3350
3360
3370
1728
1736
1744
1752
1760
1768
1776
1784
octal-Decimal Intp.f{er Conversion Table (Sheet 2 of 7)
A7-2
2000
to
2777
(Odol)
1024
to
1535
(Decimal)
Octal Decimal
10000 - 4096
20000 - 8192
30000 - 12288
40000 - 16384
50000 - 20480
60000 - 24576
70000 - 28672
1536
to
3000
to
3777
2047
(Octo/)
(Decimal)
APPENDIX 7
to
2.5.59
(Decimol)
Octal Decimal
10000 - .4096
20000 - 8192
30000 - 12288
«1000 - 16384
50000 - 20480
60000 - 24576
70000 - 28672
OCTAL-DECIMAL INTEGER CONVERSION
2.560
to
.5777
(Octo I)
to •
3071
(Decimol)
1
2
3
4
5
6
7
4400
4410
4420
4430
4440
4450
4460
4470
2304
2312
2320
2328
2338
2344
2352
2380
2305
2313
2321
2329
2337
2345
2353
2381
2306
2314
2322
2330
2338
2348
2354
2382
2307
2315
2323
2331
2339
2347
2355
2383
2308
2316
2324
2332
2340
2348
2356
2384
2309
2317
2325
2333
2341
2349
2357
2365
2310
2318
2326
2334
2342
2350
2358
2388
2311
2319
2327
2335
2343
2351
2359
2387
2119
2127
2135
2143
2151
2159
2167
2175
4500
4510
4520
4530
4540
4550
4560
4570
2368
2378
2384
2392
2400
2408
2416
2424
2389
2377
2385
2393
2401
2409
2417
2425
2370
2378
2386
2394
2402
2410
2418
2426
2371
2379
2387
2395
2403
2411
2419
2427
2372
2380
2388
2398
2404
2412
2420
2428
2373
2381
2389
2397
2405
2413
2421
2429
2374
2382
2390
2398
2408
2414
2422
2430
2375
2383
2391
2399
2407
2415
2423
2431
2183
2191
2199
2207
2215
2223
2231
2239
4600
4610
4620
4630
4640
4650
4660
4670
2432
2440
2448
2456
2464
2472
2480
2488
2433
2441
2449
2457
2465
2473
2481
2489
2434
2442
2450
2458
2466
2474
2482
2490
2435
2443
2451
2459
2467
2475
2483
2491
2436
2444
2452
2460
2468
2476
2484
2492
2437
2445
2453
2461
2469
2477
2485
2493
2438
2446
2454
2462
2470
2478
2486
2494
2439
2447
2455
2463
2471
2479
2487
2495
2246 2247
2254 - 2255
2262 2263
2270 2271
2278 2279
2286 2287
2294 2295
2302 2303
4700
4710
4720
4730
4740
4750
4760
4770
2496
2504
2512
2520
2528
2536
2544
2552
2497
2505
2513
2521
2529
2537
2545
2553
2498
2506
2514
2522
2530
2538
2546
2554
2499
2507
2515
2523
2531
2539
2547
2555
2500
2508
2516
2524
2532
2540
2548
2556
2501
2509
2517
2525
2533
2541
2549
2557
2502
2510
2518
2526
2534
2542
2550
2558
2503
2511
2519
2527
2535
2543
2551
2559
0
1
2
3
4
5
6
7
1
·2
3
4
5
8
7
4000
4010
4020
4030
4040
4050
4060
4070
2048
2058
2084
2072
2080
2088
2098
2104
2049
2057
2085
2073
2081
2089
2097
2105
2050
2058
2088
2074
2082
2090
2098
2106
2051
2059
2087
2075
2083
2091
2099
2107
2052
2080
2088
2078
2084
2092
2100
2108
2053
2081
2089
2077
2085
2093
2101
2109
2054
2082
2070
2078
2086
2094
2102
2110
2055
2083
2071
2079
2087
2095
2103
2111
4100
4110
4120
4130
4140
4150
4160
4170
2112
2120
2128
2136
2144
2152
2160
2168
2113
2121
2129
2137
2145
2153
2161
2169
2114
2122
2130
2138
2146
2154
2162
2170
2115
2123
2131
2139
2147
2155
2163
2171
2116
2124
2132
2140
2148
2156
2164
2172
2117
2125
2133
2141
2149
2157
2165
2173
2118
2126
2134
2142
2150
2158
2166
2174
4200
4210
4220
4230
4240
4250
4260
4270
2176
2184
2192
2200
2208
2216
2224
2232
2177
2185
2193
2201
2209
2217
2225
2233
2178
2186
2194
2202
2210
2218
2226
2234
2179
2187
2195
2203
2211
2219
2227
2235
2180
2188
2196
2204
2212
2220
2228
2236
2181
2189
2197
2205
2213
2221
2229
2237
2182
2190
2198
2206
2214
2222
2230
2238
4300
4310
4320
4330
4340
4350
4360
4370
2240
2248
2256
2264
2272
2280
2288
2296
2241
2249
2257
2265
2273
2281
2289
2297
2242
2250
2258
2266
2274
2282
2290
2298
2243
2251
2259
2267
2275
2283
2291
2299
2244
2252
2260
2268
2276
2284
2292
2300
2245
2253
2261
2269
2277
2285
2293
2301
0
5000
0
0
1
2
3
4
5
6
7
---
5000
5010
5020
5030
5040
5050
5060
5070
2560
2568
2576
2584
2592
2600
2608
2616
2561
2569
2577
2585
2593
2601
2609
2617
2562
2570
2578
2586
2594
2602
2610
2618
2563
2571
2579
2587
2595
2603
2611
2619
2564
2572
2580
2588
2596
2604
2612
2620
2565
2573
2581
2589
2597
2605
2613
2621
2566
2574
2582
2590
2598
2606
2614
2622
2567
2575
2583
2591
2599
2607
2615
2623
5400
5410
5420
5430
5440
5450
5460
5470
2816
2824
2832
2840
2848
2856
2864
2872
2817
2825
2833
2841
2849
2857
2865
2873
2818
2826
2834
2842
2850
2858
2866
2874
2819
2827
2835
2843
2851
2859
2867
2875
2820
2828
2836
2844
2852
2860
2868
2876
2821
2829
2837
2845
2853
2861
2869
2877
2822
2830
2838
2846
2854
2862
2870
2878
2823
2831
2839
2847
2855
2863
2871
2879
5100
5110
5120
5130
5140
5150
5160
5170
2624
2632
2640
2648
2656
2664
2672
2680
2625
2633
2641
2649
2657
2665
26.73
2681
2626
2634
2642
2650
2658
2666
2674
2682
2627
2635
2643
2651
2659
2667
2675
2683
2628
2636
2644
2652
2660
2668
2676
2684
2629
2637
2645
2653
2661
2669
2677
2685
2630
2638
2646
2654
2662
2670
2678
2686
2631
2639
2647
2655
2663
2671
2679
2687
5500
5510
5520
5530
5540
5550
5560
5570
2880
2888
2896
2904
2912
2920
2928
2936
2881
2889
2897
2905
2913
2921
2929
2937
2882
2890
2898
2906
2914
2922
2930
2938
2883
2891
2899
2907
2915
2923
2931
2939
2884
2892
2900
2908
2916
2924
2932
2940
2885
2893
2901
2909
2917
2925
2933
2941
2886
2894
2902
2910
2918
2926
2934
2942
2887
2895
2903
2911
2919
2927
2935
2943
5200
5210
5220
5230
5240
5250
5260
5270
2688
2696
2704
2712
2720
2728
2736
2744
2689
2697
2705
2713
2721
2729
2737
2745
2690
2698
2706
2714
2722
2730
2738
2746
2691
2699
2707
2715
2723
2731
2739
2747
2692
2700
2708
2716
2724
2732
2740
2748
2693
2701
2709
2717
2725
2733
2741
2749
2694
2702
2710
2718
2726
2734
2742
2750
2695
2703
2711
2719
2727
2735
2743
2751
5600
5610
5620
5630
5640
5650
5660
5670
2944
2952
2960
2968
2976
2984
2992
3000
2945
2953
296.1
2969
2977
2985
2993
3001
2946
2954
2962
2970
2978
2986
2994
3002
2947
2955
2963
2971
2979
2987
2995
3003
2948
2956
2964
2972
2980
2988
2996
3004
2949
2957
2965
2973
2981
2989
2997
3005
2950
2958
2966
2974
2982
2990
2998
3006
2951
2959
2967
2975
2983
2991
2999
3007
5300
5310
5320
5330
5340
5350
5360
5370
2752
2760
2768
2776
2784
2792
2800
2808
2753
2761
2769
2777
2785
2793
2801
2809
2754
2762
2770
2778
2786
2794
2802
2810
2755
2763
2771
2779
2787
2795
2803
2811
2756
2764
2772
2780
2788
2796
2804
2812
2757
2765
2773
2781
2789
2797
2805
2813
2758
2766
2774
2782
2790
2798
2806
2814
2759
2767
2775
2783
2791
2799
2807
2815
5700
5710
5720
5730
5740
5750
5760
5770
3008
3016
3024
3032
3040
3048
3056
3064
3009
3017
3025
3033
3041
3049
3057
3065
3010
3018
3026
3034
3042
3050
3058
3066
3011
3019
3027
3035
3043
3051
3059
3067
3012
3020
3028
3036
3044
3052
3060
3068
3013
3021
3029
3037
3045
3053
3061
3069
3014
3022
3030
3038
3046
3054
3062
3070
3015
3023
3031
3039
3047
3055
3063
3071
Octal-Decimal Integer Conversion Table (Sheet 3 oj 7)
A7-3
OCTAL-DECIMAL INTEGER CONVERSION
APPENDIX 7
4
5
6
7
3331
3339
3347
3355
3363
3371
3379
3387
3332
3340
3348
3356
3364
3372
3380
3388
3333
3341
3349
3357
3365
3373
3381
3389
3334
3342
3350
3358
3366
3374
3382
3390
3335
3343
3351
3359
3367
3375
3383
3391
3394
3402
3410
3418
3426
3434
3442
3450
3395
3403
3411
3419
3427
3435
3443
3451
3396
3404
3412
3420
3428
3436
3444
3452
3397
3405
3413
3421
3429
3437
3445
3453
3398
3406
3414
3422
3430
3438
3446
3454
3399
3407
3415
3423
3431
3439
3447
3455
3457
3465
3473
3481
3489
3497
3505
3513
3458
3466
3474
3482
3490
3498
3506
3514
3459
3467
3475
3483
3491
3499
3507
3515
3460
3468
3476
3484
3492
3500
3508
3516
3461
3469
3477
3485
3493
3501
3509
3517
3462
3470
3478
3486
3494
3502
3510
3518
3463
3471
3479
3487
3495
3503
3511
3519
3520
3528
3536
3544
3552
3560
3568
3576
3521
3529
3537
3545
3553
3561
3569
3577
3522
3530
3538
3546
3554
3562
3570
3578
3523
3531
3539
3547
3555
3563
3571
3579
3524
3532
3540
3548
3556
3564
3572
3580
3525
3533
3541
3549
3557
3565
3573
3581
3526
3534
3542
3550
3558
3566
3574
3582
3527
3535
3543
3551
3559
3567
3575
3583
0
1
2
3
4
5
6
7
7400
7410
7420
7430
7440
7450
7460
7470
3840
3848
3858
3864
3872
3880
3888
3896
3841
3849
3857
3865
3873
3881
3889
3897
3842
3850
3858
3866
3874
3882
3890
3898
3843
3851
3859
3867
3875
3883
3891
3899
3844
3852
3860
3868
3a76
3884
3892
3900
3845
3853
3861
3869
3877
3885
3893
3901
3846
3854
3862
3870
3878
3886
3894
3902
3847
3855
3863
3871
3879
3887
3895
3903
3655
3663
3671
3679
3687
3695
3703
3711
7500
7510
7520
7530
7540
7550
7560
7570
3904
3912
3920
3928
3936
3944
3952
3960
3905
3913
3921
3929
3937
3945
3953
3961
3906
3914
3922
3930
3938
3946
3954
3962
3907
3915
3923
3931
3939
3947
3955
3963
3908
3916
3924
.i932
3940
3909
3917
3925
3933
3941
39~ 3949
3956 3957
3964 3965
3910
3918
3926
3934
3942
3950
3958
3966
3911
3919
3927
3935
3943
3951
3959
3967
3718
3726
3734
3742
3750
3758
3766
3774
3719
3727
3735
3743
3751
3759
3767
3775
7600
7610
7620
7630
7640
7650
7660
7670
3968
3976
3984
3992
4000
4008
4016
4024
3969
3977
3985
3993
4001
4009
4017
4025
3970
3978
3986
3994
4002
4010
4018
4026
3971
3979
3987
3995
4003
4011
4019
4027
3972
3980
3988
3996
4004
4012
4020
4028
3973
398r
3989
3997
4005
4013
4021
4029
3974
3982
3990
3998
4006
4014
4022
4030
3975
3983
3991
3999
4007
4015
4023
4031
3782
3790
3798
3806
3814
3822
3830
3838
3783
3791
3799
3807
3815
3823
3831
3839
7700
7710
7720
7730
7740
7750
7760
7770
4032
4040
4048
4056
4064
4072
4080
4088
4033
4041
4049
4057
4065
4073
4081
4089
4034
4042
4050
4058
4066
4074
4082
4090
4035
4043
4051
4059
4067
4075
4083
4091
4036
4044
4052
4060
4068
4076
4084
4092
4037
4045
4053
4061
4069
4077
4085
4093
4038
4046
4054
4062
4070
4078
4086
4094
4039
4047
4055
4063
4071
4079
4087
4095
0
.1
2
0
1
2
3
4
5
6
7
6000
6010
8020
6030
6040
8050
8060
6070
30n
3080
3088
3096
3104
3112
3120
3128
3073
3081
3089
3097
3105
3113
3121
3129
3074
3082
3090
3098
3106
3114
3122
3130
3075
3083
3091
3099
3107
3115
3123
3131
3076
3084
3092
3100
3108
3116
3124
3132
3077
3085
3093
3101
3109
3117
3125
3133
3078
3086
3094
3102
3110
3118
3126
3134
3079
3087
3095
3103
3111
3119
3127
3135
8400
6410
8420
8430
6440
6450
6460
6470
3328
3338
3344
3352
3360
3368
3376
3384
3329
3337
3345
3353
3381
3369
3377
3385
3330
3338
3346
3354
3362
3370
3378
3386
6100
6110
6120
8130
6140
8150
8160
8170
3138
3144
3152
3160
3168
3176
3184
3192
3137
3145
3153
3181
3189
3177
3185
3193
3138
3146
3154
3162
3170
3178
3186
3194
3139
3147
3155
3163
3171
3179
3187
3195
3140
3148
3156
3164
3172
3180
3188
3196
3141
3149
3157
3165
3173
3181
3189
3197
3142
3150
3158
3166
3174
3182
3190
3198
3143
3151
3159
3167
3175
3183
3191
3199
6500
6510
6520
6530
6540
6550
6560
6570
3392
3400
3408
3416
3424
3432
3440
3448
3393
3401
3409
3417
3425
3433
3441
3449
8200
6210
6220
6230
6240
6250
6260
6270
3200
3208
3216
3224
3232
3240
3248
3256
3201
3209
3217
3225
3233
3241
3249
3257
3202
3210
3218
3226
3234
3242
3250
3258
3203 3204 3205 3206 3207
3211
3219
3227
3235
3243
3251
3259
3212
3220
3228
3236
3244
3252
3260
3213
3221
3229
3237
3245
3253
3261
3214
3222
3230
3238
3246
3254
326a
3215
3223
3231
3239
3247
3255
3263
6600
6610
6620
6630
6640
6650
6660
6670
3456
3464
3472
3480
3488
3496
3504
3512
6300
6310
6320
6330
6340
6350
6360
6370
3264
3272
3280
3288
3296
3304
3312
3320
3265
3273
3281
3289
3297
3305
3313
3321
3266
3274
3282
3290
3298
3306
3314
3322
3267
3275
3283
3291
3299
3307
3315
3323
3268
3276
3284
3292
3300
3308
3316
3324
3269
3277
3285
3293
3301
3309
3317
3325
3270
3278
3286
3294
3302
3310
3318
3326
3271
3279
3287
3295
3303
3311
3319
3327
6700
6710
6720
6730
6740
6750
6760
6770
0
1
2
3
4
5
6
7
7000
7010
7020
7030
7040
7050
7060
7070
3584
3592
3600
3608
3616
3624
3632
3640
3585
3593
3601
3609
3617
3625
3633
3641
3586
3594
3602
3610
3618
3626
3634
3642
3587
3595
3603
3611
3619
3627
3635
3643
3588
3596
3604
3612
3620
3628
3636
3644
3589
3597
3605
3613
3621
3629
3637
3645
3590
3598
3606
3614
3622
3630
3638
3646
3591
3599
3607
3615
3623
3631
3639
3647
7100
7110
7120
7130
7140
7150
7160
7170
3648
3656
3664
3672
3680
3688
3696
3704
3649
3657
3665
3673
3681
3689
3697
3705
3650
3658
3666
3674
3682
3690
3698
3706
3651
3659
3667
3675
3683
3691
3699
3707
3652
3660
3668
3676
3684
3692
3700
3708
3653
3661
3669
3677
3685
3693
3701
3709
3654
3662
3670
3678
3686
3694
3702
3710
7200
7210
7220
7230
7240
7250
7260
7270
3712
3720
3728
3736
3744
3752
3760
3768
3713
3721
3729
3737
3745
3753
3761
3769
3714
3722
3730
3738
3746
3754
3762
3770
3715
3723
3731
3739
3747
3755
3763
3771
3716
3724
3732
3740
3748
3756
3764
3772
3717
3725
3733
3741
3749
3757
3765
3773
7300
7310
7320
7330
7340
7350
7360
7370
3776
3784
3.792
3800
38{)8
3816
3824
3832
3777
37.&5
3793
3801
3809
3817
3825
3833
3778
3786
3794
3802
3810
3818
3826
3834
3779
3787
3795
3803
3811
3819
3827
3835
3780
3788
3796
3804
3812
3820
3828
3836
3781
3789
3797
3805
3813
3821
3829
3837
3
Octal-Decimal Integer Conversion Table (Sheet 40/7)
A7-4
6000
3072
ta
ta
6777
3583
(Octal)
(Decimal)
Octal Decimal
10000· .4096
20000· 8192
30000· 12288
40000 • 16384
50000 • 20480
60000· 2.4576
70000 • 28672
7000
3584
ta
ta
7777
4095
(Octal)
(Decimal)
APPENDIX 7
OCTAL-DECIMAL INTEGER CONVERSION
OCTAL
DEC.
OCTAL
DEC.
OCTAL
DEC.
OCTAL
DEC.
.000
.001
.002
.003
.004
.005
.006
.007
.010
.011
.012
.013
.014
.015
.016
.017
.020
.021
.022
.023
.024
.025
.026
.027
.030
.031
.032
.033
.000000
.001953
.003906
.005859
.007812
.009765
;011718
.0131171
.015625
.017578
.019531
.021484
.023437
.025390
.027343
.029296
.031250
.0:i3203
.035156
.037109
.039062
.041015
.042968
.044921
.046875
.048828
.050781
.052734
.054687
.056640
.058593
.060546
.062S00
.064453
.066406
.068359
.070312
.072265
.074218
.076171
.078125
.080078
.082031
.083984
.085937
.087_
.089843
.091796
.0t3750
._703
..10ll6J
.loasl1
.100
.101
.102
.103
.104
.105
.106
.107
.110
.111
.112
.113
.114
.115
.116
.117
.120
.121
.122
.123
.124
.125
.126
.127
.130
.131
.132
,133
.134
.135
.136
.137
.140
.141
.142
.143
.144
.145
.146
.147
.156
.151
.152
.153
.154
.155
.156
.157
.160
.161
.162
.163
.184
.165
.10CS4l8
.IM
.107421
.10t3T1S
.111328
.113281
.115234
.117187
.119140
.1210t3
.123046
.167
.170
.171
.172
.173
.174
.175
.176
.1,.,
.125000
.126953
.128906
.130859
.132812
.134765
.136718
.138671
.140625
.142578
.144531
.146484
.148437
.150390
.152343
.154296
.156250
.158203
.160156
.162109
.164062
.166015
.167968
.169921
.171875
.173828
.175781
.177734
.179687
.181840
.183593
.185546
.187500
.189453
.191406
.193359
.i95312
.197265
.199218
.201171
.203125
.205078
.207031
.208984
.210937
.212890
.214843
.216796
.218750
.220703
.222656
.224609
.226562
.228511
.230468
.232421
.234375
.236328
.238281
.240234
.242187
.244140
.246093
.248046
.200
.201
.202
.203
.204
.205
.206
.207
.210
.211
.212
.213
.214
.215
.216
.217
.220
.221
.222
.223
.224
.225
.226
.227
.230
.231
.232
.233
.234
.235
.236
.237
.240
.241
.242
.243
.244
.245
.246
.247
.250
.251
.252
.253
.254
.255
.256
.257
.260
.261
.262
.283
.264
.265
.266
.267
.270
.271
.272
.273
.274
.2TS
.276
.2,.,
.250000
.251953
.253906
.255859
.257812
.259765
.261718
.263671
.265625
.267578
.269531
.271484
.273437
.275390
.277343
.279296
.281250
.283203
.285156
.287109
.289062
.291015
.292968
.294921
.296875
.298828
.300781
.302734
.304687
.306840
.308593
.310546
.312500
.314453
.318406
.318359
.320312
.322265
.324218
.326171
.328125
.330078
.332031
.333984
.335937
.337890
.339843
.341796
.343750
.345703
.347656
.349609
.351562
.353111
.355468
.357421
.359375
.361328
.363281
.365234
.367187
.369140
.371093
.373046
.300
.301
.302
.303
.304
.305
.306
.307
.310
.311
.312
.313
.314
.315
.316
.317
.320
.321
.322
.323
.324
.325
.326
.327
.330
.331
.332
.333
.334
.335
.336
.337
.340
.341
.342
.343
.344
.345
.346
.347
.350
.351
.352
.353
.354
.355
.356
.357
.360
.361
.362
.363
.364
.365
.366
.367
.370
.371
.372
.373
.374
.375
.376
.377
.375000
.376953
.378906
.380859
.382812
.384765
.386718
.388671
.390625
.392578
.394531
.396484
.398437
.400390
.402343
.404296
.406250
.408203
.410156
.412109
.414062
.416015
.417968
.419921
.421875
.423828
.426781
.427734
.429687
.431640
.433593
.435546
.437500
.439453
.441406
.443359
.445312
.447265
.449218
.451171
.453125
.455678
.457031
.458984
.460937
.462890
.464843
.466796
.468750
.470703
.472656
.474609
.476562
.478515
.480468
.482421
.484375
.486328
.488281
.490234
.492187
.494140
.496093
.498046
..034
.1135
.037
.040
.041
.042
.043
.044
.045
.046
.047
.OSO
.051
..053
.054
.055
.056
.057
••
.Ml
.062
.062
.OM
.115
....
...7
.070
.071
.012
.073
.17"
.075
• ITS
• OTT
.097U6
Octal-Decimal Integer Conversion Table (Sheet 5 oj 7)
A7-5
OCTAL-DECIMAL INTEGER CONVERSION
APPENDIX 7
OCTAL
DEC.
OCTAL
DEC.
OCTAL
DEC.
OCTAL
DEC.
.000000
.000001
.000002
.000003
.000004
.000005
.000006
.000007
.000010
.000011
.000012
.000013
.000014
.000015
.000016
.000017
.000020
.000000
.000003
.000007
.000011
.000015
.000100
.000101
.000102
.000103
.000104
.000244
.000247
.000251
.000255
.000200
.000201
.000202
.000203
.000204
.000019
.000105
.000106
.000488
.000492
.000495
.000499
.000503
.000507
.000511
.000514
.000518
.000522
.000526
.000530
.000534
.000537
.000541
.000545
.000300
.000301
.000302
.000303
.000304
.000305
.000306
.000307
.000310
.00031l
.000312
.000313
.000314
.000315
.000316
.000317
.000320
.000732
.000736
.000740
.000743
.000747
.000751
.000021
.000022
.000023
.000024
.000025
.000026
.000027
.000030
.000031
.000032
.000033
.000034
.000035
.000038
.000037
.000040
.000041
.000042
.000043
.000044
.000045
.000046
.000047
.000050
.000051
.000052
.000053
.000054
.000066
.000022
.000026
.000030
.000034
.000038
.000041
.000045
.00/)049
.000053
.000057
.000061
.000084
.000068
.000072
.000076
.000080
.000083
.000087
.000091
.000095
.000099
.000102
.000106
.000110
.000114
.000118
•. 000122
.000125
.000129
.000133
.000137
.000107
.000110
.000111
.0001l2
.000113
.000114
.000115
.000116
.000117
.000120
.000121
.000122
.000123
.000124
.000125
.000126
.000127
.000130
.000131
.000132
.000133
.000134
.000135
.000136
.000137
.000140
.000141
.000142
.000143
.000144
.000141
.000145
.000144
.000148
.000152
.000156
';000160
.000184
.000167
.000171
.000146
.000147
.000150
.000151
.000152
.000153
.0001M
.000155
.000156
.000157
.000160
.000161
.000182
.000163
.000184
.000165
.000166
.000167
.000170
.000171
.000172
.000173
.000174
.000175
.000176
.000177
.000056
.000175
.000057
.000060
.000061
.000062
.000083
.000084
.00006&
.000068
.000067
.000070
.000071
.000072
.000073
.000074
.000075
.000076
.000077
.000179
.000183
.000186
.000190
.000194
.000198
.000201
.000106
.000209
.000213
.000217
.00001
.ooom
.000228
.000232
.000236
.000240
.000259
.000263
.000267
.000270
.000274
.000278
.000282
.000286
.000289
.000293
.000297
.000301
.000305
.000308
.000312
.000318
.000320
.000324
.000328
.000331
.000335
.000339
.000343
.000347
.000350
.000354
.000358
.000362
.000386
.000370
.000373
.000377
.000381
.000385
.000389
.000392
.000396
.000400
.000404
.000408
.000411
.000415
.000419
.000423
.000427
.000431
.000434
.000438
.000442
.000446
.00Cl45O
.000453
.000457
.000461
.000465
.000469
.000473
.000476
.000480
.000484
.000205
.00020$
.000207
.000210
.000211
.000212
.000213
.000214
.000215
.000216
.000217
.000220
.000221
.000222
.000223
.000224
.000225
.000226
.000227
.000230
.000231
.000232
.000233
.000234
.'000235
.000236
.000237
.000240
.000241
.000242
.000243
.000244
.000245
.000246
.000247
.000250
.000251
.000252
.0002113
.0002&4
.000255
.000256
.000267
.000260
.000261
.000282
.000283
.000184
.000185
.000266
.000267
.000270
.000171
.000272
.000273
.000274
.000275
.000276
.000277
.000549
.000553
.000556
.00Q560
.000584
.000568
.000572
.000576
.000579
.000583
.000587
.000591
.000595
.000598
.000602
.000606
.000610
.000614
.000617
.000621
.000625
.000629
.000633
.000637
.000840
.000644
.000848
.000652
.000656
.0006&9
.000863
.000687
.000671
.000675
.000679
.000682
.000686
.000690
.000694
.000698
.000701
.000705
.000709
.000713
.000717
.000710
.000724
.000728
Octal-Decimal Integer Conversion Table (Sheet 6 oj 7)
A7-6
.000321
.000322
.000323
.000324
-.000325
.000326
.000327
.000330
.000331
.000332
.000333
.000334
.000335
.000336
.000337
.000340
.000341
.000342
.000343
.000344
.000345
.000346
.000347
.000350
.000351
.000352
.000353
.000354
.000355
.000356
,.000357
.000360
.000361
.000362
.000363
.000384
.000365
.000366
.000367
.000370
.000371
.000371
.000373
.000374
.000375
.000376
.000377
.000755
.000759
.000762
.000766
.000770
.000774
.000778
.000782
.000785
.000789
.000793
.000797
.000801
.000805
.000808
.000812
.000816
.000820
.000823
.000827
.000831
.000835
.000839
.000843
.000846
.000850
.000854
.000858
.000862
.000865
.000869
.000873
.000877
.000881
.000885
.000888
.0~892
.000896
.00C!900
.000904
.000907
.00091l
.000915
.000919
.000923
.000926
.000930
.000934
.000938
.000942
.000946
.000949
.000953
.000957
.000961
.000965
.000968
.000972
j
OCTAL-DECIMAL INTEGER CONVERSION
APPENDIX 7
OCTAL
DEC.
OCTAL
DEC.
OCTAL
DEC.
OCTAL
DEC.
.0.0.0.40.0.
.0.0.0.40.1
,.0.0.0.40.2
.0.0.0.40.3
.0.0.0.40.4
.0.0.0.40.5
.0.0.0.40.6
.0.0.0.40.7
.0.0.0.410.
.0.0.0.411
.0.0.0.412
.0.0.0.413
,0.0.0.414
.0.0.0.415
,0.0.0.416
,0.0.0.417
.0.0.0.976
.0.0.0.980.
.0.0.0.984
.0.0.0.988
.0.0.0.991
.0.0.0.995
.0.0.0.999
.0.0.10.0.3
.0.0.10.0.7
.0.0.10.10.
.0.0.10.14
.0.0.10.18
,0.0.10.22
.0.0.10.26
.0.0.10.29
,0.0.10.33
.0.0.0.50.0.
.0.0.0.50.1
.0.0.0.50.2
.0.0.0.50.3
.0.0.0.50.4
.0.0.0.50.5
.0.0.0.50.6
.0.0.0.50.7
.0.0.0.510.
.0.0.0.511
.0.0.0.512
,0.0.0.513
,0.0.0.514
.0.0.0.515
.0.0.0.516
,0.0.0.517
.0.0.1220.
.0.0.1224
.0.0.,1228
.0.0.1232
.0.0.1235
.0.0.1239
.0.0.1243
.0.0.1247
.0.0.1251
.0.0.1255
.0.0.1258
,90.1262
,0.0.1266
.0.0.1270.
.0.0.1274
,0.0.1277
.0.0.0.60.0.
.0.0.0.60.1
.0.0.0.60.2
.0.0.0.60.3
.0.0.0.60.4
.0.0.0.60.5
.0.0.0.60.6
.0.0.0.60.7
.0.0.0.610.
.0.0.0.611
,0.0.0.612
,0.0.0.613
,0.0.0.614
,0.0.0.615
,0.0.0.616
.0.0.0.617
.0.0.1464
.0.0.1468
.0.0.1472
.0.0.1476
.0.0.1480.
.0.0.1483
.0.0.1487
.0.0.1491
.0.0.1495
.0.0.1499
.0.0.150.2
.0.0.150.6
,90.1510.
,0.0.1514
,0.0.1518
,0.0.1522
.0.0.0.70.0.
.0.0.0.70.1
.0.0.0.70.2
.0.0.0.70.3
.0.0.0.70.4
.0.0.0.70.5
.0.0.0.70.6
.0.0.0.70.7
.0.0.0.710.
.0.0.0.711
.0.0.0.712
.0.0.0.713
.0.0.0.714
.0.0.0.715
,0.0.0.716
,0.0.0.717
.0.0.170.8
.0.0.1712
.0.0.1716
.0.0.1720.
.0.0.1724
.0.0.1728
.0.0.1731
.I}D1735
.0.0.1739
.0.0.1743
.0.0.1747
,0.0.1750.
,90.1754
.0.0.1758
,0.0.1762
.0.0.1766
,0.0.0.420.
.0.0.0.421
,0.0.0.422
.0.0.0.423
,0.0.0.424
.0.0.0.425
,0.0.0.426
,0.0.0.427
.0.0.0.430.
,0.0.0.431
.0.0.0.432
.0.0.0.433
,0.0.0.434
,0.0.0.435
,0.0.0.436
.0.0.0.437
,0.0.0.440.
.0.0.0.441
,0.0.0.442
.0.0.0.443
.0.0.0.444
.0.0.0.445
.0.0.0.446
.0.0.0.447
.0.0.0.450.
.0.0.0.451
.0.0.0.452
.0.0.0.453
.0.0.0.454
,0.0.0.455
.0.0.0.456
.0.0.0.457
.0.0.0.460.
.0.0.0.461
.0.00.462
.0.0.0.463
.0.0.0.464
.0.0.0.465
.0.0.0.466
.0.0.0.467
.0.0.0.470.
.0.0.0.471
.0.0.0.472
.0.0.0.473
.0.0.0.474
,0.0.0.475
.0.0.0.476
.0.0.0.477
,0.0.10.37
,0.0.10.41
.0.0.10.45
,0.0.10.49
,0.0.10.52
.0.0.10.56
.0.0.10.60.
.0.0.10.64
,0.0.10.68
.0.0.10.71
,0.0.10.75
,0.0.10.79
,0.0.10.83
.0.0.10.87
.0.0.10.91
,0.0.10.94
,0.0.0.520.
.0.0.0.521
.0.0.0.522
.0.0.0.523
,0.0.0.524
,0.0.0.525
.0.0.0.526
.0.0.0.527
,0.0.0.530.
.0.0.0.531
.0.0.0.532
.0.0.0.533
,0.0.0.534
.0.0.0.535
.0.0.0.536
.0.0.0.537
.0.0.0.540.
.0.0.0.541
.0.0.0.542
.0.0.0.543
.0.0.0.544
.0.0.0.545
.0.0.0.546
.0.0.0.547
.0.0.0.550.
.0.0.0.551
,0.0.0.552
.0.0.0.553
.0.0.0.554
.0.0.0.555
.0.0.0.556
.0.0.0.557
.0.0.0.560.
.00.0.561
,0.0.0.562
.0.0.0.563
.0.0.0.564
.0.0.0.565
,,0.0.0.566
.0.0.0.567
.0.0.0.570.
.0.0.0.571
,0.0.0.572
.0.0.0.573
,0.0.0.574
.0.0.0.575
,0.0.0.576
.0.0.0.577
,0.0.1281
,0.0.1285
,0.0.1289
.0.01293
.0.0.1296
,0.0.130.0.
.0.0.130.4
.0.0.130.8
.0.0.1312
.0.0.1316
.0.0.1319
.0.0.1323
.0.0.1327
.0.0.1331
.0.0.1335
.0.0.1338
,0.0.1342
.0.0.1346
.0.0.1350.
.0.0.1354
,0.0.1358
.0.0.1361
.0.0.1365
.0.0.1369
.0.0.1373
.0.0.1377
.0.0.1380.
.0.0.1384
.0.0.1388
.0.0.1392
.0.0.1396
.0.0.1399
.0.0.140.3
.0.0.140.7
.0.0.1411
.0.0.1415
,0.0.1419
.0.0.1422
.0.0.1426
.0.0.1430.
.0.0.1434
.0.0.1438
.0.0.1441
.0.0.1445
.0.0.1449
.0.0.1453
,0.0.1457
.0.0.1461
,0.0.0.620.
,0.0.0.621
.0.0.0.622
,0.0.0.623
.0.0.0.624
.0.0.0.625
.0.0.0.626
,0.0.0.627
,0.0.0.630.
.0.0.0.631
.0.0.0.632
.0.0.0.633
.0.0.0.634
.0.0.0.635
.0.0.0.636
.0.0.0.637
,0.0.0.640.
,0.0.0.641
.0.0.0.642
.0.0.0.643
.0.0.0.644
.0.0.0.645
.0.0.0.646
.0.0.0.647
.0.0.0.650.
.80.0.651
.0.0.0.652
.0.0.0.653
.0.0.0.654
.0.0.0.655
.0.0.0.656
.0.0.0.657
.0.0.0660.
,0.0.0.661
.0.0.0.662
.0.0.0.663
.0.0.0.664
.0.0.0.665
.0.0.0.666
.0.0.0.667
.0.0.0.670.
.0.0.0.671
.0.0.0.672
.0.0.0.673
.0.0.0.674
.0.0.0.675
.0.0.0.676
,0.0.0.677
,0.0.1525
.0.0.1529
.0.0.1533
,0.0.1537
.0.0.1541
.0.0.1544
,0.0.1548
,0.0.1552
.0.0.1556
,0.0.1560.
.0.0.1564
.0.0.1567
,0.0.1571
.0.0.1575
,0.0.1579
,0.0.1583
.0.0.1586
.0.0.1590.
.0.0.1594
.0.0.1598
.0.0.160.2
.0.0.160.5
.0.0.160.9
.0.0.1613
,0.0.1617
.0.0.1621
.0.0.1625
.0.0.1628
.0.0.1632
,0.0.1636
.0.0.1640.
.0.0.1644
.0.0.1647
.0.0.1651
.0.0.1655
.0.0.1659
.0.0.1663
.0.0.1667
.0.0.1670.
.0.0.1674
.0.0.1678
.0.0.1682
.0.0.1686
.0.0.1689
.0.0.1693
,0.0.1697
.0.0.17.01
,0.0.170.5
.0.0.0.720.
.0.0.0.721
.0.0.0.722
.0.0.0.723
,0.0.0.724
.0.0.0.725
,0.0.0.726
.0.0.0.727
.0.0.0.730.
.0.0.0.731
.0.0.0.732
,0.0.0.733
.0.0.0.734
,0.0.0.735
,0.0.0.736
.0.0.0.737
.0.0.0.740.
,0.0.0.741
.0.0.0.742
.0.0.0.743
.0.0.0.744
.0.0.0.745
.0.0.0.746
.0.0.0.747
,0.0.0.750.
.0.0.0.751
.0.0.0.752
.0.0.0.753
.0.0.0.754
.0.0.0.755
.0.00756
.0.0.0.757
.0.0.0.760.
.0.0.0.761
.00.0.762
.0.0.0.763
.0.0.0.764
,0.0.0.765
.0.0.0.766
.0.0.0.767
.0.0.0.770.
.0.00771
,0.0.0.772
.0.0.0.773
.0.0.0.774
.0.0.0.775
,0.0.0.776
,0.0.0.777
,0.0.1770.
.0.0.1773
,0.0.1777
,0.0.1781
,0.0.1785
.0.0.1789
.0.0.1792
.0.0.1796
.0.0.180.0.
.0.0.180.4
.0.0.180.8
.0.0.1811
.0.0.1815
.0.0.1819
,0.0.1823
,0.0.1827
.0.0.1831
,0.0.1834
.0.0.1838
.0.0.1842
.0.0.1846
.0.0.1850.
.0.0.1853
.0.0.1857
.0.0.1861
.0.0.1865
.0.0.1869
.0.0.1873
.0.0.1876
.0.0.1880.
.0.0.1884
.0.0.1888
.0.0.1892
.0.0.1895
,0.0.1899
.0.0.190.3
.0.0.190.7
.0.0.1911
.0.0.1914
.0.0.1918
,0.0.1922
.0.0.1926
.0.0.1930.
:0.0.1934
.0.0.1937
.0.0.1941
.0.0.1945
.0.0.1949
.0.0.10.98
.0.0.110.2
.0.0.1196
.0.0.1110.
.0.0.1113
.0.0.1117
.0.0.1121
.0.0.1125
.0.0.1129
.0.0.1132
.0.0.1136
.0.0.1140.
.0.0.1144
.0.0.1148
.0.0.1152
.0.0.1155
.0.0.1159
.0.0.1163
.0.0.1167
.0.0.1171
.0.0.1174
.0.0.1178
.0.0.1182
.0.0.1186
.0.0.1190.
.0.0.1194
.0.0.1197
,0.0.120.1
,0.0.120.5
.0.0.120.9
.0.0.1213
.0.0.1216
Octal-Decimal Integer Conversion Table (Sheet 7 of 7)
A7-7/A7-8
APPENDIX 8
HOLLERITH CARD CODES
8400
Graphics
ti
(ZERO)
1
2
3
4
5
6
7
8
9
BLANK
=
I
:
>
../
+
A
B
C
D
E
F
G
H
I
?
.
)
[
<
+
NOTES:
Standard
Hollerith
Card Codes
Internal
Binary
Code
0
1
2
3
4
5
6
7
8
9
8-2
8-3
8-4
8-5
8-6
8-7
00
01
02
03
04
05
06
07
10
11
12
13
14
15
16
17
12
12-1
12-2
12-3
12-4
12-5
12-6
12-7
12-8
12-9
12-0
12-8-3
12-8-4
12-8-5
12-8-6
12-8-7
20
21
22
23
24
25
26
27
30
31
32
33
34
35
36
37
8400
Graphics
-
J
K
L
M
N
0
P
Q
R
!
$
*
J
;
~
BLANK
/
S
T
U
V
W
X
y
Z
,+
,.,..(
\
-H+-
standard
Hollerith
Card Codes
Internal
Binary
Code
11
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
11-0
11-8-3
11-8-4
11-8-5
11-8-6
11-8-7
40
41
42
43
44
45
46
47
50
51
52
53
54
55
56
57
NO PUNCH
0-1
0-2
0-3
0-4
0-5
0-6
0-7
0-8
0-9
0-8-2
0-8-3
0-8-4
0-8-5
0-8-6
0-8-7
60
61
62
63
64
65
66
67
70
71
72
73
74
75
76
77
1.
In the binary mode do.tafrom a card reader is transferred without conversion.
Each Card column is divided into two characters. Either 4- or 6-bit characters will be transferred depending upon the format option specified.
2.
In the Hollerith mode do.ta from the card reader (assumed to be in BCD codes)
is automatically converted to collating codes.
3.
Data to a card punch is presented in collating code - character by character in the same manner as to the line printer.
4.
No parity bit is presented with do.ta to/from card equipment. Error and code
validity checks are performed at the respective card device.
A8-1/A8-2
PREPARED BY _ _ _ _ _ _ _ _ _ _ _ _ _ __
PROGRAM TITLE _ _ _ _ _
~
PHONE
_ _ __
DATE _ _ _ _ _ PROJECT _ _ __
_ _ _ _ _ _ _ _ _ _ _ _ _ _ __
PAGE _ _ _ _ _ OF _ _ _ _ __
~~116I'I.191"1111"113I14I""I"I1811YIN'"lnl"I":,,
12
11
0,
,T,T,
IT,
~,
I~,
,•
IT,
I~
T,
IT,
I.,
IT
T,
+-'-.J..-f''-H ,-+"'I.~+_'_~,j~y-~_M~IL___'___fJ.""---'--
1
~~~~~y~~~IL-y,~¥~~~~-~~~"-~~~~-~I~~,~~I~~~1mIHr~IX~",~~~-I"-~~~
~~~12~~T~IT~,~~I~T,~IT~,~~I~T~~~-~~~~~I~T~~~~~~~+~~I~T~+-'-~+ __ ~~~~1.
8~~~~
.
C,
IR, T
~,-I~,
H,
E,
0,
,0
Iw
10,
10,
Iw,
10,
Iw,
10,
Iw
10,
IRI
101
Iw,
10
10
:0,
17
!
I
L_~~~~'~~~L~~~_~~~~~~~~~~~~~~~~~~~,~~2
L
I
I
!
!
!
_~_~'~~IL_L
!
I
"~_~,~~,~,~,~,~,~,~,~~,~~,~~~_~~~~~4_~~-"-i,~~2
22~,-,~~,~~~-~,-~,~~~,~~~L.-,-~~,~-~~~,~~~~~-~~~~,~,~,~~,~~1~~~,-,~~~~~~_r~~-~~_42
23rt'-~~~~L~~L~~"-~~_~_.L.~~~J~~~,~~~~~~,~~~,~,~~~~,~_,~~~~~~,~~+~~~~"
24
f--'--~~++L.,L.!
25
,
"
l' '/'/' /' 1'1'
I
,
I
J
L~'--'--'-~L.L--..-L'
I
",
!
__
L.~L_~~~~,'~~~~~,~~~,~~_~~~~~,.L.L_L~~~'"-+~ -'-'~~-'--'--j2
,
'/"/' /"/13/14 /"/,,/,,/,/,,/20/"1,,1,,1,,1,,1,,/,,/,,/,,/,,/,,/32/33/,, /"/"/"/"/"/"/"/ ,,/,,1 ... I",I" 1,,/.++-/, 1"/"/ "/"/"/"/"/ "/"/"/
APPENDIX 10
PAPER TAPE FORMAT
Corresponding
Contents of Memory
Example
0
0
0
0
'-77777/' -77777B
0
0
0
0
0
Example
'12345/' 54321R
0
0
Stop Code
0
0
0 00
0
0 00
0
0 00
0
0 00
0
0
0
0 00
0
000
0
0 00
0
0 00
0
0
0
0
0
00
0
000
0
00
0
0
0
00
0
00
0
000
0
0
0
0
Left Exec Bit
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
}
}
Left Half Word
Right Exec Bit
Right Half Word
0
0
0
0
0
0
0
Paper Tape Format
For 4 Bit Mode with
Exec Bits
Parity
Channel
AlO-l/AlO-2
APPENDIX 11
TWO'S COMPLEMENT ARITHMETIC
1.
THE TWO'S COMPLEMENTS SYSTEM
3.
TRUNCATION AND ROUND-OFF
In the sign-magnitude system, the sign bit has a value
In the natural, real number system, a given number X
of -1 or ±1. The sign is multiplied by the value repre-
can assume any value on the continuous range -
ro :;:; x
sented by the magnitude bits to form the implied num-
Natural numbers have infinite precision (i. e., their
ber.
representation requires an infinite number of digits).
:;:;.
The numbers that the digital computer must deal with
: In two's complements, the sign bit has a variable negative weight, depending on the position of the binary
point. The weight of the sign is added to the value repre.sented by the magnitude bits to form the implied
number.
are finite-precision, quantized numbers. We shall
refer to these as "digital" or "synthetic" numbers.
Digital numbers are evidently a function of the continuous natural argument X. Two such consistent functions
are:
y=
The Representation of a 2's Complements Number
If b s is the content of the sign bit, and bj the content of
any other bit in position j, the number N represented
Y=
These functions (Figure 1) are defined as follows: In
L. I., if n is an integer, y = n-l for n-l :;:; x 0,
but y
= n-l
= n for n-l < x < n, x < o.
j
j=1
In the discussion above and in the following, we assume
y to have integer values only (binary point to the right
Note that the summation in the equation is always
of least significant bit of A register, say). This does
positive.
not detract from the generality of the results. To convert the y values to fractions, simply multiply by 2- 15 •
2.
RANGE OF NUMBERS
In the 8400, the "lease integer" functions, y
Let the binary point be immediately to the right of the
sign bit (n
1-2
-m
= 0).
Then m bits can represent -1 :;:; N :;:;
• Note that -1 is inside the range (bs = 1,
bj = 0), but +1 is not.
=
lxJ, is
used, as this is most compatible with two's complement
notation. The "a symetry" in the range of numbers,
discussed in Section 2. 1 can now be seen as a direct
consequence of the L. I. function.
AU-l
TWO'S COMPLEMENT ARITHMETIC
APPENDIX 11
y
Y
-3 -2 -I
4
4
3
2
3
2
1
-\
-----------~---------X
234
y=
I
-\
-I
-2
-3
-4
-2
2
3
4
X
-3
-4
y= rxl
lX J
--------r--+~---------X
A less-consistent scheme, often
used in sign-magnitude computers.
Here y = (sgn x) (lxl).
Figure All.l. Digital Numbers as Functions oj Continuous Natural Numbers
Yr
4
3
2
~--~~---;----~~--~------.
%%%
X
-\
-2
-3
-4
Figure All. 2. Rounded Digital Numbers as a Function oj Natural Numbers
Al1-2
TWO'S COMPLEMENT ARITHMETIC
APPENDIX 11
Truncation
It is also quite easy to get the function (sgn x)
~x~ (Fig-
ure 2) by doing:
lJ
The implication of the y = x function is that when an
(operation resulting in A:AE)
8400 number is truncated, it automatically assumes
its "least integer" value. Thus dividing 1 (bit 15 = 1,
all others zero) by 2 (ASH 1) results in the natural number O. 5., which, truncated, becomes
ze~o.
On the
EXL
ADD
ST
SAVE
other hand, the number -1 (b = b. = 1 in the first exs
J
.
ample, vis all bits high) when divided by 2 results in
ADD AD
the natural number -0. 5, which the 8400 truncates to
-1.
=1
Note, in particular, that the 1ST instruction will truncate (i. e., get the "least integer in x") a floating-point
Round-Off
number prior to storing. The schemes just discussed
To round a number, one can use the SR instruction.
For example, doing
of obtaining other types of truncation are particularly
useful here.
For example, a floating point number can
be "greatest-integer" truncated by
EASH
k
SR
o
FCA
NUMBER
lAD
=1
1ST
will divide the number in the A register by 2k and round
it. The rounded function yr appears as in Figure 2.
or "sign-magnitude" truncated by
The function yr is defined as y r
= llx I -
1/2
J.
Thus
O. 5 yields 0 for the truncated result, but 1 for the
FCA
NUMBER
EXL
ADD
1ST
rounded r-esult and -0.5 yields -1 truncated and 0
rounded. Note that the error committed in round-off is
E
r
ADD lAD
2 O. 5.
Programming for C. I. and "Sign-Magnitude"
r
If the programmer needs y = xl, he can simply do:
(operation resulting in A:AE)
AD = 1
ST = GI
4.
=1
SIDFTS
Left shifts must have zero-fill for low order bits.
Right shifts must have sign-fill for high order bits.
The need for sign fill in right shifts is that a right shift
of k is a division by 2k of the magnitude bits if they are
zero filled in the vacated high order bits. As the sign
bit is an additive value in two's complement it must also
A11-3
TWO'S COMPLEMENT ARITHMETIC
APPENDIX 11
EST and DST set to corresponding sign bit in memory
be divided by two and added to the shifted mantissa.
Note that _zn/Zk = _Zn-k which is represented in two's
to the value of the sign bit of AE(AD). All other arith-
complement as a one in the sign bit position followed
metic operations ignore this bit.
by k one's. Adding this value in gives the appearance
When X is to be treated as.two separate single preci-
of a sign fill in vacated high order bits.
sion numbers, their sum must clearly add up to X.
That is,
5.
OVERFLOWS
X
= (A)
+ (AE) • 2- 15
An overflow indicates that the result of an arithmetic
operation exceeds the permissible range of the computer. In two's complement, the overflow V is defined
It should be clear that, unless the sign of AE is zero,
the equation is not satisfied.
as the exclusive -OR of the carry C and the drop-off D:
Similar considerations show that the sign of the AD
register must be zero if the content of that register is
V=CD+CD
to be operated on by F-type instructions.
where D is a carry from bit position S.
That this defini-
tion is correct can be quickly verified by noting that,
if a number has b s = b 1 = 1, it cannot be more positive
then -0. 5, so it is well within the permissible range
Note that a single-precision number which is to become
the least-significant portion of an extended-precision
number is treated as follows
and will remain so when shifted left once (multiplied by
2). Thus, a carry accompanied by a drop-off is not an
overflow, and, of course, neither is C = D = O. A
CA
LO
EASH
15
carry without a drop-off signifies a positive overflow,
while a drop-off without a carry indicates a negative
cision you do
overflow.
6.
To convert a single preCision number to extended pre-
MULTIPLE PRECISION
CA
HO
LDAE
=0
An extended precision number X can be regarded as a
single number.
In fact, all legitimate extended (E)
and double-floating (D) instructions of the 8400 re-
Converting a single preCision floating point number to
double can be done by clearing the AD register:
gard numbers in this way; that is, the computer effectively ignores the sign of the AE (AD) registers in all
legitimate operations (including properlY,,:,programmed
FCAU
NUMBER
FMPU
= '40000/1
DST
combat subroutines).
or
MP and ASH, EASH, reset the sign of AE, ECA, ECS,
$DCAU
DCA, DCAU, DCS, and DCSU set the sign bit of the
FCAU
AE(AD) as the corresponding memory bit was set.
DST
Al1-4
=0
$
Operation
Time is in
Microseconds,
and Includes
Instruction
Fetch (1)
32 Bit
Fit. pt.
Operand
Address
(Prefix F)
56 Bit
FIt. pt.
(Prefix D)
16 32 Bit
Integer
(Prefix I)
16 Bit
Fix. Pt.
(Prefix
[Blank])
32 Bit
Fix Pt.
(Prefix E)
16 Bit
Index
(Prefix X)
Indexing
OP M, (X)
.
Indirect Addressing
OP
M
Save
--
$ OPM
Arithmetic
CA, AD
CS, SB
I!
HIGH SPEED
REGlBTERS
1$
(2)
MEMORY
MP
I!
HIGH SPEED
REGlBTERS 1 $
MEMORY
3.89
NA
3.89
3.06
NA
3.06
4.17
4.72
4.17
3.33
3.89
3.33
5.28
8.06*'
5.28
4.45
5.28*
4.45
6.67
By Sub
6.67
5.28
By Sub
By Sub
6.94
By Sub
6.94
5.56
By Sub
By Sub
8.06
By Sub
8.06
6.67
By Sub
By Sub
For each level of
indexing
For each level of indirect
addressing
For a prefiXed
Save
Add.561IH.S.
Register
Addressed
*no additional
time required.
Add 0
Add .281I MEM
addressed except . . Add • 56
Add. 28 except
it Save also
addressed
($ 01'$)
Add 2.00
Add .56
CD, DV
HIGH SPEED
REGISTERS
CP
HIGH SPEED
REGlBTERS
10.00
By Sub
10.00
7.78
By Sub
By Sub
1$
10.28
By Sub
10.28
8.06
By Sub
By Sub
11.39
By Sub
11.39
9.17
By Sub
By Sub
I~
3.89
By Sub
.3.89
3.33
By Sub
1$
4.17
By Sub
4.17
3.61
By Sub
3.61
5.28
By Sub
5.28
4.72
By Sub
4.72
MEMORY
ST
MEMORY
SR
HIGH SPEED
REGlBTERS
MEMORY
I+
EXAMPLES,
$DST Mov. X
=
5.84
DST Mov. X '" 4. 72
I~
MEMORY
1. Time shown for arithmetic
operations is minimum
execution tlme and does not
include pre- alignment or
post normalization. For
each pre-alignment or
post normalization-add
0.28 !-Lsec.
4.17
6.11
5.00
4.17
4.17
3.06
By Sub
3.33
2.78
By Sub
=
.56
.56
5.84
$CA = 3.X
CA=3
$
X
3.33
4.17
=
X
=3.90
= 3.06
= .28
=~
3.90.
Add.56
Add 2.00
Add.56
$FMP $, X
FMP$
$ (OP$)
X
= 6.94
= .56
=~
= 8.06
8.06
By Sub
2. High Speed Registers Are:
4.72
By Sub
5.00
4.45
By Sub
By Sub
+ Self addressing accumulator
Immediate addressing (16
Bit Operand field of
instruction Reg. )
Save Register
>
......
l\)
I
......
>......
l\)
I
l\)
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