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NEe

....~

Advanced
A~"'Personal
Computer
TM

APe System Reference Guide

NEe
NEe Information Systems, Inc.
819-000100-1003
4-83

LIMITED WARRANTY
AND
LIABILITY DISCLAIMER

NEC Information Systems, Inc. products are warranted in accordance with the
terms of the applicable NEC Information Systems, Inc. products specification.
Product performance is affected by system configuration, software, the application,
customer data, and operator control of the system among other factors. While NEC
Information Systems, Inc. products are considered to be compatible with most
systems, the specific functional implementation by customers of the products may
vary.
Therefore, the suitability of a product for a specific application must be determined
by the customer and is not warranted by NEC Information Systems, Inc.
This manual is as complete and factual as possible at the time of printing, however,
the information in this manual may have been updated since that time. NEC
Information Systems, Inc. reserves the right to change the functions, features, or
specifications of its products at any time, without notice.
NEC Information Systems, Inc. has prepared this document for use by NECIS
employees and customers. The information contained herein is the property of
NECIS and shall not be reproduced in whole or in part without prior written
approval from NECIS.

First Printing - September 1982
Revised - December 1982
Revised - March 1983

Copyright 1982
NEC Information Systems, Inc.
5 Militia Drive
Lexington, MA 02173
Printed in U.S.A.

FEDERAL COMMUNICATIONS COMMISSION RADIO
FREQUENCY INTERFERENCE STATEMENT

"w ARNING:

This equipment generates, uses and can radiate radio frequency
energy and if not installed and used in accordance with the instructions manual,
may cause interference to radio communications. It has been tested and found to
comply with the limits for a Class A Computing device pursuant to Subpart] of
Part 15 of FCC Rules, which are designed to provide protection against such
interference. Operation of the equipment in a residential area is likely to cause
interference in which case, the user will be required to take whatever measures may
be required to correct the interference."

Manufacturer's Instructions and User's Responsibility
to Prevent Radio Frequency Interference
Manufacturer's Instructions
The user must observe the following precautions when installing and operating this
device:
1. Operate the equipment in strict accordance with the manufacturer's
instructions for the model.
2. Ensure that the unit is plugged into a properly grounded wall outlet and
that the power cord supplied with the unit is used and not modified.
3. Ensure that the unit is always operated with the factory-installed cover set
on the unit.
4. Make no modifications to the equipment which would affect its meeting the
specified limits of the Rules.
5. Properly maintain the equipment in a satisfactory state of repair.
User's Responsibility
The user has the ultimate responsibility to correct problems arising from harmful
radio-frequency emissions from equipment under his control. If this equipment
does cause interference to radio or television reception, which can be determined by
turning the equipment off and on, the user is encouraged to try to correct the
interference by one of the following measures. All of these responsibilities and any
others not mentioned are exclusively at the expense of the user.

111

1.
2.
3.
4.

Change
Change
Change
Change

in
in
in
in

orientation of the receiving device antenna.
orientation of the equipment.
location of equipment.
equipment power source.

If these attempts are unsuccessful, install one or all of the following devices:
1. Line isolation transformers
2. Line filters
3. Electro-magnetic shielding
If necessary, the user should consult the dealer, NEC, or an experienced radioltele-

vision technician for additional suggestions. The user may find the following
booklet prepared by the Federal Communications Commission to be helpful: "How
to Identify and Resolve Radio-TV Interference Problems." This booklet is available
from the U.S. Government Printing Office, Washington, D.C. 20402, Stock No.
004-000-00345-4.
"N ote: The operator of a computing device may be required to stop operating his
device upon finding that the device is causing harmful interference and it is in the
public interest to stop operation until the interference problem is corrected."

iv

Contents
Page
PREFACE ......................................................

Xlii

CHAPTER 1 HARDWARE OVERVIEW
2 PROCESSOR PCB
MOTHER BOARD/CARD CAGE INTERFACE .........
MICROPROCESSOR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DIRECT MEMORY ACCESS ..........................
INTERVAL TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
INTERRUPT CONTROL. . . . . . . . . . . . . . . . . .. . . . . . . . . . ..
MEMORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.6.1
Main Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.6.2
Battery-Backed Memory. . . . . . . . . . . . . . . . . . . . . . ..
2.6.3
Read Only Memory ............................
2.7
PARALLEL PRINTER CONTROL ......................
2.7.1
Interface ......................................
Programming Considerations. . . . . . . . . . . . . . . . . . ..
2.7.2
2.8
KEYBOARD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.8.1
Keyboard Layout and Scan Codes. . . . . . . . . . . . . . ..
2.8.2
Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.9
CALENDAR AND CLOCK GENERATOR ..............
2.9.1
Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Programming Considerations. . . . . . . . . . . . . . . . . . ..
2.9.2
2.10 JUMPER SETTINGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

2-3
2-13
2-14
2-19
2-20
2-26
2-27
2-28
2-29
2-29
2-29
2-29
2-38
2-39
2-41
2-42
2-43
2-44
2-44

CHAPTER 3 CONTROLLER PCB
3.1
MOTHER BOARD/CARD CAGE INTERFACE .........
3.2
CRT DISPLAY CONTROL ............................
3.2.1
Display Buffer Memory. . . . . . . . . . . . . . . . . . . . . . . ..
3.2.2
Programming Considerations. . . . . . . . . . . . . . . . . . ..
3.3
CRT DISPLAY UNIT .................................
FLEXIBLE DISK DRIVE CONTROLLER. . . . . . . . . . . . . ..
3.4
3.4.1
Programming Considerations. . . . . . . . . . . . . . . . . . ..
3.4.2
Drive A and B Interface. . . . . . . . . . . . . . . . . . . . . . . ..

3-1
3-4
3-5
3-8
3-18
3-21
3-24
3-37

CHAPTER
2.1
2.2
2.3
2.4
2.5
2.6

v

Contents (cont'd)
Page
3.5

3.6

3.7
3.8
3.9

FDD UNIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.5.1
Specifications ................................. ,
3.5.2
Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.5.3
Terminations and Jumper Settings. . . . . . . . . . . . . . ..
SERIAL I/O COMMUNICATIONS CONTROLLER ..... ,
3.6.1
Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.6.2
Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.6.3
Interface ..................................... ,
3.6.4
Programming Considerations ................... ,
3.6.4.1 Asynchronous Operating Mode ..................
3.6.4.2 Synchronous Operating Mode ...................
3.6.4.3 Business Machine Operating Mode ...............
3.6.5
Status Word Format ...........................
SOUND CONTROL .................................. ,
3.7.1
Interface ......................................
3.7.2
Programming Considerations. . . . . . . . . . . . . . . . . . ..
ARITHMETIC PROCESSING UNIT. . . . . . . . . . . . . . . . . . ..
JUMPER SETTINGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

3-39
3-39
3-40
3-40
3-43
3-43
3-43
3-43
3-43
3-50
3-53
3-57
3-59
3-60
3-61
3-62
3-62
3-64

CHAPTER 4 POWER SUPPLY
APPENDIX A INTEGRATED CIRCUIT DATA SHEETS
Al
16-BIT MICROPROCESSOR ...........................
A2
PROGRAMMABLE COMMUNICATION INTERFACES ..
SINGLE/DOUBLE DENSITY FLOPPY DISK
A3
CONTROLLER .......................................
A4
GRAPHICS DISPLAY CONTROLLER ..................
APPENDIX B LOGIC AND SCHEMATIC DIAGRAMS

VI

AI-I
A2-1
A3-1
A4-1

Contents (cont'd)
APPENDIX C PROGRAMMABLE ARRAY LOGIC DECODING
SPECIFICATIONS
APPENDIX D CHARACTER CODE AND KEYBOARD
INFORMATION
APPENDIX E 110 PORT ADDRESSES AND INSTRUCTIONS
APPENDIX F HARDWARE SPECIFICATIONS

Vll

List of Illustrations
Figure
1-1
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
2-22
2-23
2-24
2-25
2-26
2-27
2-28
2-29
3-1
3-2
3-3
3-4
Vlll

Title

Page

System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Processor PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Processor PCB Block Diagram ..............................
Mother Board/Card Cage Intp.rface . . . . . . . . . . . . . . . . . . . . . . . . ..
Processor Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DMA Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
RD Y Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
RFSH Signal Timing ...................................... ,
Processor T nterface Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Device Interface Circuits ...................................
DMA Command and Mode Registers ........................
DMA Request and Mask Register. . . . . . . . . . . . . . . . . . . . . . . . . . ..
DMA Status Register ......................................
Interval Timer Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Interrupt Control Block Diagram ............................
Interrupt Initialization Command Words .....................
Interrupt Operation Command Words ............ , ...........
System Memory Map ......................................
Main Memory Block Diagram ...............................
Battery-Backed Memory Block Diagram ......................
Parallel Printer Control Block Diagram .......................
Parallel Printer Cable Connections ...........................
Parallel Printer Controller Interface Timing ...................
Parallel Printer Controller Interface at Paper Out Status ........
Keyboard Block Diagram ...................................
Keyboard Layout ..........................................
Keyboard Interface ........................................
Clock/Calendar Block Diagram .............................
Clock/Calendar Format ....................................
Proce<:sor PCB Jumper Settings ..............................
Controller PCB ..........................•................
Controller PCB Block Diagram ..............................
CRT Display Control Block Diagram ........................
Character-Code Representation in the Character Code
Buffer Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

1-2
2-1
2-2
2-3
2-8
2-9
2-10
2-10
2-11
2-12
2-16
2-17
2-19
2-19
2-21
2-24
2-25
2-26
2-27
2-28
2-30
2-32
2-36
2-37
2-38
2-39
2-41
2-43
2-45
2-46
3-2
3-3
3-5
3-5

List of Illustrations (cont' d)
Figure
3-5
3-6
3-7
3-8
3-9
3-lO
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23
3-24
3-25
3-26
3-27
3-28
3-29
4-1
4-2
D-l
D-2
D-3

Title

Page

Bit Map for Character Attribute Code ....................... .
Display Buffer Memory Map ............................... .
Relationship Between Character Code, Character-Attribute Code,
Display Position, and Video Screen ......................... .
GDC Status Register Bit Map .............................. .
Monochrome-CRT Display Interface ........................ .
Color-CRT Display Interface ............................... .
FDC Block Diagram ...................................... .
FDC Timing Diagram .................................... .
FDD Signal Connector Interface and Pin Assignments ......... .
FDD Power Connector Interfce and Pin Assignments .......... .
FDD Termination Resistor Modules, Location
and Installation .......................................... .
FDD Jumper, Location and Proper Setting .................. .
Serial I/O Communications Controller Block Diagram ........ .
Communications Controller Cable Connections ............... .
Asynchronous Mode Instruction Word ...................... .
Command Instruction Word Format ........................ .
Communications Controller, Circuit for
Asynchronous Operation .................................. .
Synchronous Mode Instruction Word ....................... .
Communications Controller, Circuit for Synchronous Operation
Using External Clock ..................................... .
Communications Controller, Circuit for Synchronous Operation
Using Internal Clock ...................................... .
Communications Controller, Circuit for
Business Machine Clock ................................... .
Communications Controller, Status Word Format ............ .
Sound Control Block Diagram ............................. .
Location of Sound Interface Connectors ..................... .
Controller PCB Jumper Settings ............................ .
System Power Supply Block Diagram .......................
Power Supply Interconnection Diagram .....................
APC GRPH 1 Characters ..................................
APC GRPH2 Characters ..................................
Keyboard Layout Showing Hex Codes
for Special Keys ..........................................

.
.
.
.

3-6
3-7
3-8
3-9
3-19
3-20
3-22
3-24
3-41
3-42
3-42
3-43
3-45
3-49
3-51
3-51
3-52
3-54
3-54
3-55
3-57
3-59
3-60
3-61
3-65
4-2
4-3
D-6
D-7

. D-8

IX

List of Tables
Table
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-lO
2-11
2-12
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-lO
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21

x

Title
Card Cage Socket Contact Assignments . . . . . . . . . . . . . . . . . . . . ..
DMA Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Timer Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Interrupt Lines ...........................................
Interrupt Control Commands Summary. . . . . . . . . . . . . . . . . . . . ..
Parallel Printer Connectors Pin Assignments. . . . . . . . . . . . . . . . ..
Parallel Printer Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Parallel Printer Controller Instruction. . . . . . . . . . . . . . . . . . . . . . ..
Parallel Printer Controller Instruction Sequence . . . . . . . . . . . . . ..
Keyboard Scan Codes .....................................
Keyboard Interface Lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Clock/Calendar Instruction Format .........................
Attribute Description for Character Attribute Code ............
GDC I/O-Address and Bit Map .............................
Contents of the GDC Status Register ........................
GOC Symbols ............................................
GOC Commands .........................................
GDC Command Constants. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Bit Description of the FDC Main Status Register ..............
FOC Symbols ............................................
FDC Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
FDC Status Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
FOC Status Register 1 .....................................
FDC Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
FDC Status Register 3 .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
FDC Register I/O Addresses and Functions ..................
Output Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Input Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
FDD Specifications .......................................
Serial I/O Communications Controller Specifications ..........
Serial I/O Commands .....................................
Serial I/O Connector Pin Assignments .................... ....
Serial I/O Device Interface Connector
Pin Descriptions ..........................................

Page
2-4
2-14
2-20
2-21
2-22
2-31
2-33
2-35
2-36
2-39
2-42
2-44
3-6
3-9
3-lO
3-11
3-14
3-18
3-23
3-24
3-27
3-33
3-34
3-35
3-36
3-36
3-37
3-38
3-39
3-44
3-46
3-47
3-48

List of Tables (cont'd)
Table
3-22
3-23
3-24
3-25
3-26
3-27
3-28
3-29
4-1
C-l
C-2
C-3
C-4
C-5
D-l
D-2
D-3
D-4
E-l
E-2
E-3
E-4
E-5
E-6
E-7

Title
8251A Instruction .........................................
Communications Controller, Baud Rate Coding During
Asynchronous Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Communications Controller, Baud Rate Coding During
Synchronous Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Communications Controller, Baud Rate Coding During
Operations with Business Machine Clocking ..................
Sound Interface Pin Assignments ............................
Sound Programming Read/Write Format. ................... ,
Sound Control Commands .................................
Sound Scale Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Power Supply Pin Command Assignments ....................
Identification and Location of PAL Device ...................
PFBOIB Inputs/Outputs ...................................
PFB02B Inputs/Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
PFCOI Inputs/Outputs ....................................
NMS02 Inputs/Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Code Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ASCII Special Characters ..................................
APC Special Characters ....................................
Quick Reference Guide for ASCII Special Character/ APC Special Character Association. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
I/O Port Address and Instructions for the DMA Controller. . . ..
I/O Port Addresses and Instructions for the Interrupt
Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
I/O Port Addresses and Instructions for the Internal Timer .....
I/O Port Addresses and Instructions for the Serial I/O Communications Controller Number 1 ...............................
I/O Port Addresses and Instructions for the Serial I/O Communications Controller Number 2 ...............................
I/O Port Addresses and Instructions for the DMA Address
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
I/O Port Addresses and Instructions for the CRT Controller ....

Page
3-50
3-53
3-56
3-58
3-61
3-62
3-62
3-63
4-4
C-l
C-2
C-3
C-4
C-5
D-2
D-3
D-4
D-5
E-2
E-4
E-5
E-6
E-6
E-7
E-7

xi

List of Tables (cont'd)
Table
E-8
E-9
E-10
E-11
E-12
E-13
E-14
E-15
E-16
E-17
E-18
E-19
E-20

xu

Title
110 Port Addresses and Instructions for the Graphics Display
Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
110 Port Addresses and Instructions for the Keyboard
Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
110 Port Addresses and Instructions for the FDD Controller. . ..
110 Port Addresses and Instructions for the Clock and
Calendar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
110 Port Address and Instruction for the BBM Enable .........
110 Port Addresses and Instructions for the APU . . . . . . . . . . . . ..
110 Port Address and Instruction for the Power Off Control ....
110 Port Addresses and Instructions for the Sound Control .....
110 Port Addresses and Instructions for the Timer. . . . . . . . . . . ..
110 Port Addresses and Instructions for the ODA Controller
Number 1 ................................................
110 Port Addresses and Instructions for the IDA Controller. . . ..
110 Port Addresses and Instructions for the Communications
Adapter .................................................
110 Port Addresses and Instructions for the ASOP Controller ...

Page
E-8
E-8
E-8
E-9
E-9
E-9
E-9
E-10
E-1O
E-ll
E-ll
E-12
E-12

Preface

This system reference guide provides hardware design and interface information for
programmers, engineers, designers, and others who need to know how the APC is
designed.
Chapter 1, Hardware Overview, familiarizes you with the Advanced Personal Computer and defines the principal components and devices.
Chapter 2, Processor PCB, includes descriptions and technical information for the
devices contained on the Processor PCB along with programming considerations
where appropriate.
Chapter 3, Controller PCB, includes information similar to that in Chapter 2 for the
devices contained on the Controller PCB.
Chapter 4, Power Supply, contains detailed specifications for the system power
source.
Appendices A to F include hardware reference information such as IC data sheets,
logic diagrams, and data summaries.

Xlll

List of Abbreviations
A
ALE
APC

Ampere
Address Latch Enable
Advanced Personal
Computer
APU
Arithmetic Processing Unit
AT
Abnormal Termination
BBM
Battery-Backed Memory
CMOS Complementary Metal
Oxide Semiconductor
CPU
Central Processing Unit
CRT
Cathode Ray Tube
CS
Code Segment
DCH
Device Control
DIP
Dual In-line Package
DMA
Direct Memory Access
DMC
Direct Memory Access
Cycle
OS
Data Segment
EPROM Erasable Programmable
Read-Only Memory
ES
Extra Segment
FDC
Flexible Disk Drive
Controller
FDD
Flexible Disk Drive
FIFO
First-In First-Out
FM
Frequency Modulation
GDC
Graphic Display Controller
HEX
Hexadecimal
Hz
Hertz
IC
Integrated Circuit,
Interrupt Code, Invalid
Command
ICW
Initialization Command
Word
I/O
Input/Output
IP
Instruction Pointer
IRR
Read Interrupt Register

xiv

ISR
KB
LED
LSB
LSI
MB
MFM

Read Inservice Register
Kilobyte
Light Emitting Diode
Least Significant Bit
Large-Scale Integration
Megabyte
Modified Frequency
Modulation
MHz
Megahertz
MOS
Metal Oxide
Semicond uctor
ms
Millisecond
MSB
Most Significant Bit
ns
Nanosecond
NT
Normal Termination
OCW
Operational Command
Word
ODA
Output Device Adapter
PAL
Programmable Array
Logic
PCB
Printed Circuit Board
POF
Power Off Control
RAM
Random Access Memory
ROM
Read-Only Memory
rpm
Revolutions Per Minute
SS
Stack Segment
SW
Switch
TTL
Transistor/Transistor
Logic
USART Universal Synchronous/
Asynchronous Receiver/
Transmitter
V
Volt
VFO
Variable Frequency
Oscillator
W
Watt
Microsecond
JlS

Chapter 1

Hardware Overview
The NEC Advanced Personal Computer (APC) has two basic components: a Main
Unit and a Keyboard. The Keyboard, which cable-connects to the Main Unit, is
common to all APC models. The Main Unit, which houses the Central Processing
Unit (CPU), memory, visual display, sound output, and peripheral controllers, is
available in three models: (I) a Monochrome Cathode Ray Tube (CRT) Display
with one 8-inch Flexible Disk Drive (FDD), (2) a Monochrome CRT Display with
two 8-inch FDDs, and (3) a Color CRT Display with two 8-inch FDDs. Several
options and accessories are available to enhance performance or to adapt the APC
for special applications.
Figure 1-1 is a block diagram of the APe. The Main Unit, the heart of the APC, has
a CRT Display, one or two 8-inch FDDs, an ON/OFF switch, and several controls
associated with the CRT Display. Three Input/Output (I/O) cable connectors are
available at the rear of the cabinet.
The CPU, memory, and basic control logic are contained in the Main Unit on two
quad-layered Printed Circuit Boards (PCB): a Processor PCB (G9PFBU) and a
Controller PCB (G9PFCU). These PCBs plug into a mother board interface bus
that has the space and power for up to three additional (optional) PCBs.
The Processor PCB contains as standard equipment:
• A 16-bit 8086 Microprocessor
• An 8288 Bus Controller with 20-bits of addressing, making one megabyte
(MB) of memory accessible
• 128 kilobytes (KB) (standard) of Random Access Memory (RAM)
• 8 KB of Read-Only Memory (ROM)
• 4 KB of CMOS Battery-Backed Memory, which remains refreshed for at
least two years without ac power
• A 4-channel Direct Memory Access (DMA) Controller
1-1

Hardware Overview

\1.'\I~

r
I
I

LJNIT

-----l

PO\\'ER Sl'PPLY
5 LPiELS

SySTEM CLOCK

(4.9152!\.UIz)

B,I"THRY-SACKED
IMEMOR\
(pPD449)

4

CHA~NEL

I

DMA

(8237)

4 KB

Rf

I

TOP VIEW

::::11~

LI

L2

I

I
I

I I:::

: : :1 I

LJUu-

moOD,

Figure 2-3 Mother Board/Card Cage Interface
Table 2-1 lists the contact assignments for each socket. All signals on these contacts
are Transistor/Transistor Logic (TTL) compatible. Time relationships between
various contacts in the card cage bus are shown in Figures 2-4 through 2-7. 110
equivalent circuits for the affected contacts and devices are shown in Figures 2-8
and 2-9.
2-3

Processor PCB

Table 2-1 Card Cage Socket Contact Assignments
PIN
NUMBER

2-4

NAME

READ/
WRITE

DESCRIPTION

Rl, RSO
LI, LSO

GND

Signal Ground

R2, R49
L2, L49

+S V

+S Vdc Supply

R3, R48
L3, L48

+12 V

+12 V Supply

R47, L47

-12 V

-12 V Supply

R46, L46

-S V

-S V Supply

R4

POF

W

Power Off Control. Goes high to command
power supply off.

RS,LS
R6,L7
R8
R9,L9
RIO, LIO
R12

IRO to
IR14

R

Interrupt Request a Through 14. These IS
lines carry interrupt requests to the processor. When an 110 device requires processor
intervention, it signals the jJPD82S9 A interrupt controller, which activates one of the IS
interrupt lines to the processor; the interruptrequest signal is maintained until acknowledgement from the processor. IRO has the
highest priority and IRIS the lowest priority.
These lines are active Low.

R13, R14
RlS, R16

DRQO to
DRQ3

R

DMA Request a Through 3. These lines transmit requests by 110 devices for DMA service.
These signals remain active until DMA
acknowledgement is active on a corresponding DACK line. Channel assignments are 0 =
CRT, 1 = FDD, 2 = Graphics, 3 = AUX.

LI3, LI4
LIS, LI6

DACKO
to DACK3

W

DMA-Request Acknowledgement a Through
3. These lines signify that the DMA controller
has acknowledged the DMA request on a
corresponding DRQ line. DACK lines are
active High.

Processor PCB
Table 2-1 Card Cage Socket Contact Assignments (cont'd)
PIN
NUMBER

NAME

READI
WRITE

DESCRIPTION

R20

TC

W

Terminal Count. This line carries to the 110
device a one-clock-duration pulse indicating
that the terminal count for the DMA channel
has been reached. This pulse is active High.

R21

PHIO

W

System Clock. The pulse of the clock is
transmitted on this line; the clock period is
about 200 nsec (4.9152 MHz) and its duty
cycle is 33 percent.

L21

IRST

W

Initial Reset. When this line goes High, every
device in the system is initialized. This line is
activated at power on.

R22

lOW

W

110 Write. A Low on this line instructs the
110 device to receive data from the data bus.
Either the DMA controller or processor can
activate the line.

L22

RDY

R

Ready. A High on this line indicates that data
has been received by an 110 device or
memory, or that preparation of data is complete. It is pulled Low by a device to lengthen
110 memory cycles, allowing slower devices
to adjust to the 110 channel.
NOTE
There is an Interval-Ready signal
within the G9PFBU PCB; it activates when memory access from
the processor or DMA controller
clashes with the memory-refresh
cycle.

2-5

Processor PCB

Table 2-1 Card Cage Socket Contact Assignments (cont'd)
PIN
NUMBER

2-6

NAME

READ/
WRITE

DESCRIPTION

R23

lOR

W

IIO Read. A Low on this line instructs the
110 device to transmit its data to the data bus.
This instruction can come from either the
DMA controller or the processor.

L23

DMC

W

DMA Cycle. A High on this line indicates the
processor has been inhibited, thus giving
system-bus control to the DMA controller.

R24

MRQ

W

Memory Request. When this line is Low, it
indicates the memory cycle is in operation.
The line is inactive (High) during memoryrefresh cycles.

L24

MR

W

Memory Read. This line instructs the additional memory to transmit its data onto the
data bus. Either the processor or DMA controller can activate this signal, which is active
Low.

R25

RFSH

W

Memory Refresh. When this line
dynamic memory is refreshed.

L25

MW

W

Memory Write. When Low, this line instructs
the selected memory to receive the data on the
data bus. It is activated by either the DMA
controller or processor.

R26

BHE

W

Bus High Enable. When Low, this line indicates that the most significant half of the data
line is ready to be read. This line is not used
during DMA cycles.

L26

ALE

W

Address Latch Enable. When activated by the
processor or DMA control, the signal on this
line latches the address on the bus.

IS

Low,

Processor PCB

Table 2-1 Card Cage Socket Contact Assignments (cont'd)
PIN
NUMBER

NAME

READ/
WRITE

DESCRIPTION

R27

DT/R

W

Data Transmit or Receive. This line indicates
data transfer direction. When High, direction
is processor to 110 or memory; when Low,
direction is 110 or memory to processor.

L27

CLKO

W

Communication Clock. This line, which is
energized by the 8253-5 Programmable Interval Timer, conveys a synchronizing variable
frequency clock to the communications
control.

R30

AO

W

Address Bit O. When this line is active (High),
the memory or 110 device associated with the
least significant half of the data is enabled to
read or transmit its data.

R31, L30
R32, L31
R33, L32
L33

Al to A7

W

Address Bits 1 Through 7. These seven lines
address the memory or 110 device. These
signals are latched.

R34,
R35,
R36,
R37,
R38,
R39,
R40,
R4I,

ADO to
AD15

W

Address and Data Lines 0 Through 15. These
16 lines are bidirectional and time multiplexed to convey address or data to the
address or data buses.

Al6 to
AI9

W

Address Lines 16 Through 19. These four lines,
used for addressing the memory, increase the
number of address lines to twenty, allowing
access to one megabyte of memory.

L34
L35
L36
L37
L38
L39
L40
L41

R42, L42
R43,L43

2-7

Processor PCB

T1

T4

T3

T2

PHIO

_1

1~

~ lIOns,

--

1_

I

,10nsMIN

'''.1

1 30 ns IOns
...
__

==x
--~~~------------V-AL-ID----------------~

AS TO A15 )...-----~(rDO:A~TrAA~INN».-----

ADS TO AD15

BHE lAO TO A7

-1

~35ns~

MRQ

10ns

\_--------------~/

MRD/IORIIOW

\\----------,
I !~ I

10 ns

---xI

ADS TO AD15

~

~

AS TO A15 Xr----D-A-T-A-O-U-T-------X

~ ~35ns
--~l--_-_--_--_-_--_~\.~

MW

l::jS5 ns

\...1330 ns MIN

________~,~-------

NOTE: WITH MEMORY IN REFRESH, MW
BECOMES ACTIVE BEFORE MRQ.

-l 2~OA~ I--

~~~__
1 _________________________I~c=

Figure 2-4 Processor Timing

2-8

H

\

ALE

DMC

~r---

Processor PCB

I

SI

S2

S4

S3

PHIO

ALE

~

~

------_/~----~\_------------------------I.. 200 ns

ADS TO AD15

.. IJOO n~I ..... 130 ns

_~X AS-AI5 X~---------

IPOns

~100ns

.. I

==x

AO TO A7

VALID

I

X. . ___
-

~

~
\. . ------------------~!~/~-----

DACK

I. . 190 ns

MRD/IOR

I. 190 ns .. I
I

... 1

\O'- _ _ _ _--J/
1..19ons

MRiIOW

.. I

----------~\

Il70 n~1

TC

DMC

~
I~-------

I. . 170 ns ..I

----------~\_------_/~-----

I. 2~~~s .1
----

1::s: I

MAX

7~----------------------~\

----

Figure 2-5 D MA Timing

2-9

Processor PCB

PHIO

lOR/lOW

-r- to.,

,'-------45 .,

MIN

RDY -----~\J

Figure 2-6 RDY Signal Timing

RFSH

*RFSH'

*RAS

\

/

\

MRQ

MW

\

NOTE: THE *RFSH' AND *RAS SIGNALS ARE GENERATED IN THE MEMORY
FROM THE RFSH SIGNAL.

Figure 2-7 RFSH Signal Timing
2-10

Processor PCB

1. AO TO A19, IRQ, lOR, lOW, BHE, IRST, PHIO

AO TO A19

LS244

vee

2. RDY

<'>
~

I

8284

"'

RDY

X111
(LOGICAL " 1" )

LSTTL

I

3. IRO TO IRll, DRQO TO DRQl

Vee

LS14
8259A
OR 8237-5

4. DACK

8237-5

p
LSTTL

<-J

Figvre 2-8 Processor Interface Circuits
2-11

Processor PCB

l.PHIO
LS14

I

1::

I>

[)o

00
,.

2. IRST
Vee

30 K
LS14

51

1

0.22"'

3. IRQ, lOR, lOW, BHE, DACK

LS14

~~~-----------------[)o~------~I>

4.;_D_Y_ _ _ _ _ _ _ _ _ _ _:

___

~~----;'""--,

LS OPEN-COLLECTOR

5. IRO TO IRll, DRQO TO DRQl (LS TTL)

Figure 2-9 Device Interface Circuits
2-12

Processor PCB

2.2

MICROPROCESSOR

The functional heart of the Processor PCB is the NEC pPD8086 Microprocessor, an
NEC-manufactured device physically and logically interchangeable with the Intel
8086.
The 8086 is a high-performance 16-bit CPU packaged in a single40-pin Dual In-line
Package (DIP) chip. It has a direct addressing capability to 1 MB of memory on a
20-bit address bus, of which bits 0 through 15 are time-multiplexed for the 16-bit
data bus. It is driven at a 4.9152 MHz clock rate and is used in maximum operating
mode (using an external 8288 bus controller).
In general, the 8086 processes a program by repeated cycling through four clock
steps, Tl through T4:
Tl fetches an instruction from memory
T2 reads in any required operand
T3 executes the instruction
T4 writes any required result.
In the 8086, two separate processors perform these steps independently and simultaneously: (1) an execution unit that executes instructions, and (2) a bus interface
unit that fetches instructions and queues them up for use by the execution unit.
All registers and data paths within the execution unit are 16 bits wide for fast
operation. A 16-bit arithmetic-logic unit manages the general registers and instruction operands and maintains status and control flags. The execution unit is a strictly
internal device and has no connection to the outside world. All instructions and
memory access operations are accomplished by the bus interface unit.
The bus interface unit functions as a good secretary by anticipating the needs of the
execution unit and lining up sequential instructions for ready access. These instructions are stored in an internal queue RAM with a capacity of six bytes. The bus
interface unit is programmed to keep this RAM filled, fetching two bytes at a time
from even addresses and one byte at a time from odd addresses. When the execution
unit requests a memory or 110 read or write, the bus interface unit discontinues
instruction fetching and responds to the execution unit request. If the instruction
executed calls for control transfer to another location, the bus interface unit empties
the queue RAM, fetches the instruction from the new location, and feeds it directly
to the execution unit. Then the bus interface unit proceeds to refill the queue RAM
from sequential instructions from the new location.

2-13

Processor PCB

The 1,048,576 bytes of available memory space are addressed as if divided into
logical segments of up to 64 KB each. The 8086 has direct access to four segments at
a time, each of which has a base address carried in one offour segment registers: the
Code Segment (CS), Data Segment (DS), Stack Segment (SS), and Extra Segment
(ES). The Instruction Pointer (IP) register contains the present offset distance in
bytes, which completes the logical address of the next address to be processed. The
result of this memory organization is that the 20-bit physical memory address can
be defined by a logical address consisting of two 16-bit bytes, the first specifying the
base address of the selected segment and the second specifying the relative address
within that segment, counting from the base address. To convert a logical address to
a physical address, first shift the base address byte 4 bits to the left by multiplying it
by sixteen, then add the result to the offset byte.
2.3

DIRECT MEMORY ACCESS

Because it bypasses processor intervention, DMA provides a much faster way of
moving data between I/O devices and memory. Supported by the NEC LSI 8237-5
DMA Controller, DMA employs 16 address lines and 4 bits of page addressing,
thus enabling it to address one megabyte of memory. Although the DMA is a
synchronous device, it can interface with low-speed memory or I/O devices by using
the external Ready line.
The four DMA channels are assigned as follows:
ChannelO

CRT

Channel 1

FD D

Channel 2

Reserved for graphic operations option

Channel 3

Future.

See Table 2-2 for a list of instructions and I/O addresses. Figures 2-10, 2-11, and
2-12 show the DMA registers.
Table 2-2 DMA Instructions
INSTRUCTION

READ/
WRITE

110
ADDRESS

Write Command

W

09

Write Mode

W

IB

7

6

K

D
S

S
M
S
1

2-14

M
S
0

DATA BUS
4
5
3
W
S

P
R

I

A
T

D

2

1

0

T
M

C

A

M

E

H

M

T
R

T
R
0

C
S

C
S
0

1

1

Processor PCB

Table 2-2 DMA Instructions (cont'd)
READI
WRITE

I/O
ADDRESS

Write RQ Register

W

Write Single Mask

INSTRUCTION

DATA BUS
4
5
3

7

6

2

I

0

19

-

-

-

-

-

R
B

C
S
I

C
S
0

W

OB

-

-

-

-

-

M
K

C
S
I

C
S
0

Write All Mask

W

IF

-

-

-

-

M
B
3

M
B
2

M
B
I

M
B
0

Read Status

R

09

R
Q
3

R
Q
2

R
Q
I

R
Q
0

T
C
3

T
C
2

T
C
I

T
C
0

CHO DMA Address

R/W

01

A7 A6 AS A4 A3 A2 Al
AI5 AI4 AI3 AI2 All AIO A9

AO
A8

CHO DMA Count

R/W

II

W7 W6 W5 W4 W3 W2 WI WO
WI5WI4WI3WI2WII WlOW9 W8

CH I DMA Address

R/W

03

A7 A6 AS A4 A3 A2 Al
AI5 AI4 AI3 AI2 All AIO A9

CHI DMA Count

R/W

13

W7 W6 W5 W4 W3 W2 WI WO
WI5WI4WI3WI2WII WIOW9 W8

CH2 DMA Address

R/W

05

A7 A6 AS A4 A3 A2 Al
AI5 AI4 AI3 AI2 All AIO A9

CH2 DMA Count

R/W

15

W7 W6 W5 W4 W3 W2 WI WO
WI5WI4WI3Wl2WII WIO\V9 W8

CH3 DMA Address

R/W

07

A7 A6 AS A4 A3 A2 Al
AI5 AI4 AI3 Al2 All AIO A9

CH3 DMA Count

R/W

17

W7 W6 W5 W4 W3 W2 WI WO
WI5WI4 WI3WI2WII WlOW9 W8

AD
A8

AO
A8

AO
A8

2-15

Processor PCB

Table 2-2 DMA Instructions (cont'd)
INSTRUCTION

READ/
WRITE

I/O
ADDRESS

7

6

DATA BUS
5
4
3

CHO Page Register

W

38

0

0

0

0

CH 1 Page Register

W

3A

0

0

0

CH2 Page Register

W

3C

0

0

CH3 Page Register

W

3E

0

0

Read Temp Register

R

ID

D
7

D
6

D
5

Master Clear

W

ID

-

-

-

2

1

0

A
19

A
18

A
17

A
16

0

A
19

A
18

A
17

A
16

0

0

A
19

.'\

18

A
17

A
16

0

0 19

A

A
18

A
17

A
16

D
4

D
3

D
2

D
1

D
0

-

-

-

-

-

COMMAND REGISTER
7

6

5

4

3

2

1

0 -

BIT NUMBER

l J1 I I I I I I

I

o

MEMORY-TO-MEMORY DISABLE

X DON'T CARE
I
(

I
(

o
1

o
o
1

o
o
o

CONTROLLER ENABLE
CONTROLLER DISABLE
NORMAL TIMING
FIXED PRIORITY
ROTATING PRIORITY
LATE WRITE SELECTION
DREQ SENSE ACTIVE HIGH
DACK SENSE ACTIVE LOW

Figure 2-10 DMA Command and Mode Registers
2-16

Processor PCB

MODE REGISTER
2

0 -

BIT NUMBER

r-~.-.-.--r-.-.-'

II

CHANNEL
CHANNEL
CHANNEL
CHANNEL

00
01
10
11

VERIFY TRANSFER
WRITE TRANSFER
READ TRANSFER
ILLEGAL

0

AUTO INITIALIZATION DISABLE
AUTO INITIALIZATION ENABLE

0

ADDRESS INCREMENT SELECT
ADDRESS DECREMENT SELECT

00
01
10
11

DEMAND MODE SELECT
SINGLE MODE SELECT
BLOCK MODE SELECT
CASCADE MODE SELECT

00
01
10

0
1
2
3

SELECT
SELECT
SELECT
SELECT

Figure 2-10 DMA Command and Mode Registers (cont'd)
REQUEST REGISTER
7

6

5

4

3

'---~V""'-_...J

DON'T CARE

2

o -

BIT NUMBER

L-y-J

L{~~

10
11

'-----{ ~

SELECT
SELECT
SELECT
SELECT

CHANNEL
CHANNEL
CHANNEL
CHANNEL

0
1
2
3

RESET REQUEST BIT
SET REQUEST BIT

SOFTW ARE REQUESTS WILL BE SERVICED ONLY IF THE CHANNEL IS IN BLOCK MODE.

Figure 2-11 DMA Request and Mask Register
2-17

Processor PCB

MASK REGISTER
7

6

5

4

3

o -

2

I I

I I

l ' - - -......V.___---'

'---y--'

BIT NUMBER

L{~!

DON'T CARE

11

<-..----{ ~

SELECT
SELECT
SELECT
SELECT

CHANNEL
CHANNEL
CHANNEL
CHANNEL

0
1
2
3

MASK
MASK
MASK
MASK

BIT
BIT
BIT
BIT

CLEAR MASK BIT
SET MASK BIT

THE INSTRUCTION, WHICH SEPARATELY SETS OR CLEARS THE MASK BITS, IS SIMILAR IN FORM TO THAT
USED WITH THE REQUEST REGISTER.

7

6

I I

5

4

3

2

o -

BIT NUMBER

I I I

L{:
~{:

I

L - - -_ _ _

L - - -_ _ _ _

{~
{~

CLEAR CHANNEL 0 MASK BIT
SET CHANNEL 0 MASK BIT
CLEAR CHANNEL 1 MASK BIT
SET CHANNEL 1 MASK BIT
CLEAR CHANNEL 2 MASK BIT
SET CHANNEL 2 MASK BIT
CLEAR CHANNEL 3 MASK BIT
SET CHANNEL 3 MASK BIT

ALL FOUR BITS OF THE MASK REGISTER MAY ALSO BE WRITTEN WITH A SINGLE COMMAND.

Figure 2-11 DMA Request and Mask Register (cont'd)

2-18

Processor PCB

STATUS REGISTER
7

6

5

4

3

2

I

0 ..

BIT NUMBER

I I I I I I I I I
I

I

CHANNEL 0 HAS REACHEDTC

I

CHANNELIHASREACHEDTC

I

CHANNEL 2 HAS REACHED TC

I

CHANNEL3HASREACHEDTC

I

CHANNEL 0 REQUEST

1

CHANNEL 1 REQUEST

1

CHANNEL 2 REQUEST

I

CHANNEL 3 REQUEST

THIS INFORMATION INCLUDES WHICH CHANNELS HAVE REACHED A TERMINAL COUNT AND WHICH
CHANNELS HAVE A PENDING DMA REQUEST. BITS 0 THROUGH 3 ARE SET EVERY TIME A TC IS REACHED BY
THAT CHANNEL OR AN EXTERNAL EOP IS APPLIED. THESE BITS ARE CLEARED UPON RESET AND ON EACH
STATUS READ.

Figure 2-12 DMA Status Register
2.4

INTERV AL TIMER

The NEC J1PD8253-5 Programmable Interval Timer has three timer counter outputs: ChannelO is attached to interrupt-request Channel 3; Channell is sent to the
synchronous/asynchronous communications controller on the Controller PCB (see
Chapter 3); Channel 2 is not used. Figure 2-13 is a block diagram of the interval
timer. Table 2-3 lists the timer commands.
(LOGIC "1")

08 TO DIS
2.4576 MHz

8

8253-5
CLKO
CLKI

- l - -___

X111
r-- 7-4
LS
TO t - - - - - - t CP FIF
...----0 MR

IRQ3

T1
Al
A2
lOW
lOR

CS

AO
Al
WR
RD
CS

BUS

IRT
RESET
COMM.

Figure 2-13 Interval Timer Block Diagram
2-19

Processor PCB

Table 2-3 Timer Commands
INSTRUCTION

DATA BUS
4 3 2

READ/
WRITE

I/O
ADDRESS

Load Counter 0

W

29

C7 C6 C5 C4 C3 C2 CI CO
Cl5 Cl4 Cl3 Cl2 CII ClO C9 C8

Load Counter I

W

2B

C7 C6 C5 C4 C3 C2 CI CO
Cl5 Cl4 Cl3 Cl2 CII ClO C9 C8

Mode Set

W

2F

Timer Reset

W

46

7

6

5

I

R
L M2 MI MO

0

R
L
I

X

X

X X

S
C
I

S
C

X

0

T
M

X

0

B
C
D
X

X: Don't care.

2.5 INTERRUPT CONTROL
This interrupt function is controlled by two 8259 Metal Oxide Semiconductor
(MOS) devices; each can handle up to eight vectored priority interrupts, as shown in
Figure 2-14. The first 8259 device (master) supports IRO through IR6, with IR7
cascaded from the second 8259 device (slave), which supports IR7 through IRI4.
These 15 available interrupt lines are assigned to service specific devices in order of
priority. Table 2-4 lists the interrupt lines.
There are two interactions between the processor and the interrupt controller. The
first is the acknowledgement process, during which the processor transmits
acknowledgement of the interrupt request to the interrupt controller. During the
second process, the interrupt controller transmits a byte of data to the processor
(see Table 2-4).
Control commands issued by the processor, consisting of Initialization Command
Words (ICW) and Operational Command Words (OCW), are summarized in Table
2-5 and shown in Figures 2-15 and 2-16. Table 2-5 also includes poll mode, read
interrupt register (IRR), read inservice register (ISR), and interrupt register words
that are read into the data bus by the interrupt controller when so commanded.

2-20

Processor PCB

00 TO 07

8

MASTER
7

IRO TO IR6

lNTA
AO
lOW
lOR
CS

--

INT

IRO TO IR6

TO THE PROCESSOR

INTA
00 TO 07
AO
WR
RO
CASO TO
CS
CAS2

8

SLAVE

8
IR7 TO lRl4

---

IR

INT

-

L., INTA

CS

-

AO
WR

00 TO 07

RO
CS

CASO TO
CAS2

Figure 2-14 Interrupt Control Block Diagram
Table 2-4 Interrupt Lines
DEVICE

INTERRUPT
REQUEST LINE

INTERRUPT
VECTOR BYTE

ASSIGNMENT

Master

IRa
IRI
IR2
IR3
IR4
IR5
IR6

Not used
Communication
Not used
Timer
Keyboard
Not used
Not used

T7
T7
T7
T7
T7
T7
T7

T6
T6
T6
T6
T6
T6
T6

T5
T5
T5
T5
T5
T5
T5

T4
T4
T4
T4
T4
T4
T4

T3 a a a
T3 a a I
T3 a I a
T3 a I I
T3 I a a
T3 I a I
T3 I I a

Slave

IR7
IR8
IR9
IRlO
IRil
IRI2
IRI3
IRI4

Printer
Not used
Not used
CRT
FDD
Not used
Not used
APU

T7
T7
T7
T7
T7
T7
T7
T7

T6
T6
T6
T6
T6
T6
T6
T6

T5
T5
T5
T5
T5
T5
T5
T5

T4
T4
T4
T4
T4
T4
T4
T4

T3
T3
T3
T3
T3
T3
T3
T3

aaa
a0 I
aIa
aI I
I aa
I a I
I I a
I I I
2-21

Processor PCB

Table 2-5 Interrupt Control Commands Summary
READ/
WRITE

I/O
ADDRESS

7

6

5

ICW I

W

20

0

0

0

I

0

ICW2

W

22

T7

T6

T5

T4

ICW 3

W

22

I

0

0

ICW4

W

22

0

0

0

OCW I

W

22

OCW2

W

20

DEVICE

INSTRUCTION

Master

DATA BUS
4
2
3

I

0

0

0

I

T3

0

0

0

0

0

0

0

0

0

0

0

0

I

M6 M5 M4 M3 M2 MI MO
R

S
L

E

0

0

L2

Ll

LO

0

I

P

P
R

R
I
S

0

I

Slave

2-22

OCW3

W

20

0

E
S
M

S
M
M

Poll Mode

R

20

I

-

-

Read IRR

R

20

-

W2 WI WO

-

I

I

I

I

I

I

I

R

R

R

R

R

R

R

6

5

4

3

2

I

0

I
S
6

I
S
5

I
S
4

I
S
3

I
S
2

I
S
I

I
S
0

Read ISR

R

20

Read Mask

R

22

ICW I

W

28

0

0

0

I

0

0

0

I

ICW2

W

2A

T7

T6

T5

T4

T3

0

0

0

ICW 3

W

2A

0

0

0

0

0

I

I

I

ICW4

W

2A

0

0

0

0

0

0

0

I

M6 M5 M4 M3 M2 MI MO

Processor PCB

Table 2-5 Interrupt Control Commands Summary (cont'd)
DEVICE

I/O

DATA BUS
4
2
3

READ/
WRITE

ADDRESS

OCW 1

W

2A

OCW2

W

28

R

S
L

E
0
I

0

0

L2

L1

LO

OCW3

W

28

0

E
S
M

S
M
M

0

1

P

R
R

R
I
S

Poll Mode

R

28

I

-

-

-

-

W2 WI WO

Read IRR

R

28

IR
14

IR
13

IR
12

IR
11

IR

IR
9

IR
8

IR
7

Read IRR

R

28

IS
14

IS
13

IS
12

IS
11

IS

IS
9

IS
8

IS
7

Read Mask

R

2A

INSTRUCTION

7

6

5

1

0

MI4 M13 M12 MIl MIO M9 M8 M7

lO

lO

M 14 M 13 M 12 MIl M 10 M9 M8 M7

2-23

rrocessor rClJ

ICWI
07 06 OS 04

03

01

02

DO

/A7/A6/AS/1 /LTIM / AD! ISNGL I IC4

L U

I

t

I: ICW4 NEEDED
0: NO ICW4 NEEDED
SET "I"
I: SINGLE
0: CASCADE
SET "0"
CALL ADDRESS INTERVAL
SET "0"
I: LEVEL TRIGGERED MODE
0: EDGE TRIGGERED MODE
SET"!"
INTERRUPT VECTOR ADDRESS
SET "0"

L-~~

_________________ INTERRUPTVECTORADDRESS
SET ALL "0"

L--L~--L--L------------------------INTERRUPTVECTORADDRESS

ICW3 (MASTER)
1 s71 s61 SSI S41 s31 s21 SI 1 SO

I

fL..--"fL-..Jt------'f------'t------'t----Lt----Lf________ l:

IR INPUT HAS A SLAVE
0: IR INPUT DOES NOT HAVE A SLA VE
SO TO S6 = 0, S7 = 1

ICW3 (SLAVE)
102

101

100

tL.._--"t'------l.t____ SLAVE ID
SET ALL TO ''I''
ICW4
I 0 I 0 I 0 I SFNM I BUF

MIS I AEOII tJ PM I

~ 1:

8086/8088 MODE
0: MCS-80/8S MODE

1: AUTO EOI
NORMALEOI
BUF MIS
L-________________ 0 X NON-BUFFERED MODE

L--------- O:

1
1
L--_______________________ I:
0:

0 BUFFERED MODE/SLA VE
1 BUFFER MODE/MASTER
SPECIAL FULLY NESTED MODE SELECTED
SPECIAL FULLY NESTED MODE NOT SELECTED

Figure 2-15 Interrupt Initialization Command Words
2-24

Processor PCB

OCWI
D7

DO

INTERRUPT MASK
I: MASK SET
0: MASK RESET
OCW2

MO TO M7 CORRESPOND TO IRO TO IR7

D7

DO

I I I I 0 I0 I
R

SL EO!

L21 Lli LO

I
IR LEVEL

f

L2
0
0
0
0

Ll
0
0

LO
0
1
0

I
0
0

0
0

OCW3
D7

MASTER
IRO
IRI
IR2
IR3
IR4
IRS
IR6

SLAVE
IR7
IR8
IR9
IRIO
IRll
IR12
IRI3
IRI4

NONSPECIFIC EO! COMMAND
SPECIFIC EO! COMMAND
ROTATE ON NONSPECIFIC EO! COMMAND
ROTATE IN AUTOMATIC EO! MODE (SET)
ROTATE IN AUTOMATIC EO! MODE (CLEAR)
ROTATE ON SPECIFIC EO! COMMAND
SET PRIORITY COMMAND
NO OPERATION
DO

RR

RIS

o

READ IRR
READISR

I: POLL COMMAND
0: NO POLL COMMAND

ESMM

SMM

o

RESET SPECIAL MASK
SET SPECIAL MASK

Figure 2-16 Interrupt Operation Command Words
2-25

Processor PCB

2.6 MEMORY
Figure 2-17 is the system memory map that shows how the memory space addresses
are allocated.
00000

'\

STANDARD
RAM

128 KB

20000
/

MAIN MEMORY
640 KB
(USER RAM)

EXPANDED
RAM

AOOOO

AI000

4KBBM
DUPLICATE
BBM
ADDRESSES

COOOO
ALPHANUMERIC
ROM

128 KB

<

BATTERY-BACKED MEMORY
(4 KB REPEATED 32 TIMES)

DOOOO
DISPLAY
MEMORY

(NOT USED)

EOOOO

FOOOO

SPECIAL
CHARACTERS
RAM
ROM DUPLICATE
ADDRESSES

FEOOO
FFFFF

8KROM

Figure 2-17 System Memory Map
2-26

11

Processor PCB

2.6.1 Main Memory
The Processor PCB contains 128 KB (64 K words: 16 bits of data, 18 bits wide, with 1
bit parity for each 8 bits)' of RAM, organized into eighteen 64K x I-bit dynamic
memory chips. Figure 2-18 is a block diagram of the circuit. The RAM is refreshed
during the non-memory-access cycle, and its access time is 200 ns. Parity check is
carried out with two additional memory chips. A detected parity error lights the D4
red Light Emitting Diode (LED), located near the top edge of the Processor PCB.
As shown in Figure 2-17, the main memory is expandable to a maximum of 640 KB,
of which 256 KB can be supported by the present APC equipment configuration.
ADDRESSES
1 TO 16
REFRESH ADDRESS
REFRESH
ADDRESS
CONNECTOR

\

ADDRESS
MUX.

t
CLOCK

MEMORY
(HIGH)

REFRESH
TIMER

MEMORY
(LOW)

REFRESH
REQUEST

MRQ

DATA
8 TO 15
DATA

REFRESH
ARBITER

o TO 7

-

DATA
8 TO 15
DATA

o TO 7

64K X 9

REFRESH

READY
CONTROL

RDY

RAS
MW
AO
BHE

MEMORY
CONTROL
LOGIC

CAS
WR

Figure 2-18 Main Memory Block Diagram
2-27

Processor PCB

2.6.2

Battery-Backed Memory

The BBM is composed of4K(two 2K X 8-bit chips) of Complementary Metal Oxide
Semiconductor (CMOS) static RAM and is addressable from AOOOO through COOOO
hexadecimal (HEX) in 32 4K visible sections of memory, each section containing
the same da ta. The APe uses partial address decoding of this 128 KB of memory,
which results in 4 KB of BBM. The BBM contains system information and is
protected from loss for at least two years by the battery that plugs into the Processor
PCB.
As shown in Figure 2-19, the BBM read/write operation is identical to that of the
main memory except for a BBM write protect circuit that safeguards the BBM from
unintentional data manipulation.

(HIGH) D8 TO DIS

--'--_...J.f______

DATA BUS _ _ _ _ _ _ _ _ _ _ _ _
(LOW) DO TO D7

~

L-.....,. 2K X 8 OUT

ADDRESS I TO 11
BHE
AO

BBM
F/F COMMAND
MW

+5 Vde

BATTERY

CMOS
STATIC
MEMORY

BBM
WRITE
PROTECT
CIRCUIT

WRT

I

CS
CONTROL
CIRCUIT

L-..,. VOLTAGE
CONTROl"
CIRCUIT

Figure 2-19 Battery-Backed Memory Block Diagram

2-28

2K X 8

.----

WR(LOW)
CS Vee

~

J

Processor PCB

The BBM write protect command 110 port address is 59(HEX). A logical" 1" on the
Least Significant Bit (LSB) position on the data bus enables writing to the BBM; a
"0" sets the BBM for write protection.
2.6.3

Read Only Memory

The Processor PCB contains 8K of ROM in tw04K x 8-bit Erasable Programmable
Read-Only Memory (EPROM) chips. The ROM has two functions: flexible disk
self-testing and bootstrap loading. As shown in Figure 2-17, the ROM occupies the
8K addresses from FEOOO through FFFFF and is visible in eight duplicate 8K
sections from FOOOO through FFFFF. At APC power-on, the 8086 code segment
and instruction-pointer registers are set to FFFF(HEX) and OOOO(HEX) addresses
respectively for loading and auto self-test, instructions for which are resident in the
ROM.
2.7

PARALLEL PRINTER CONTROL

This portion of the logic provides an 110 TTL interface with an external paralleldata-bus printer.
As shown in Figures 2-20 and 2-21, the parallel printer control consists of an NEC
pPD8255A Programmable Peripheral Controller that interfaces with connector
CN2 through LS244 drivers. A flat-type 26-conductor cable connects the CN2
board connector to a connector at the rear of the main unit that, in turn, goes to the
printer. The pin connections are listed in Table 2-6. The interface is adaptable to
either an Output Device Adapter (ODA) or Centronics-type printer by setting
appropriate jumpers on TM2, TM3, and TM4 on the Processor PCB (see Figure
2-29).
2.7.1

Interface

Table 2-7 lists the interface lines.
2.7.2

Programming Considerations

The 8255A device is operated in the APC as Mode 0 (basic 110) in the Group A
ports (Port A and upper 4 lines of Port C), and Mode 1 (strobed) in the Group B
ports (Port B and lower 4 lines of Port C). The eight lines of Port B (PBO through
PB7) carry the strobed data to the printer; 110 control line levels are from Ports A
and C.
Programming and execution of the 8255 is accomplished using the instructions
described in Tables 2-8 and 2-9. Figures 2-22 and 2-23 show interline timing under
various operating conditions.
2-29

Processor PCB

PRINTER
CABLE
CONNECTOR
PIN NUMBERS

8255A-5
8;

DBO
TO
DB7

8

PBO
TO
PB7

LS244
DRIVER

/
I

8

DATA
TO CONNECTOR
I

PBO
TO
PB7

{

11
13
15
17
19
21
23
25

PE

22

PAO
PA3
ABOI

AO

PA4

AB02

Al

PA7

IORO

lOR

PC7

IOWO

lOW

~
~

DRIVER

I

>---

CS

IRT

IRT

PC!
PAl
PC2
PC4

t--

rl

FA ULT

14

+5V

18

INPUT PR IME

10

ST ROBE

SHIFT ~

1

I }--

IRT71
RSTO
CLOCK

Figure 2-20 Parallel Printer Control Block Diagram

2-30

7

B USY

PC2
CS

SE LECT

L-

..

SG

3
5
{

1,9,20
4,12,24
6,16,26

Processor PCB

Table 2-6 Parallel Printer Connectors Pin Assignments

SIGNAL
DATA STB
DATA 1
DATA 2
DATA 3
DATA 4
DATA 5
DATA 6
DATA 7
DATA 8
ACK
Input Busy
PE
SELECT
Signal Ground
NC
Signal Ground
Chassis Ground
+5 Vdc
Twisted Pair Ground (Pin 1)
Ground (Pin 2)
Ground (Pin 3)
Ground (Pin 4)
Ground (Pin 5)
Ground (Pin 6)
Ground (Pin 7)
Ground (Pin 8)
Ground (Pin 9)
Ground (Pin 10)
Ground (Pin 11)
Ground (Pin 31)
Input Prime

"FaUIT
Signal Ground
NC
NC
Input Busy

PIN NUMBER PIN NUMBER PIN NUMBER REMARKS
AT A
ATB
ATC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

3
6
7
8
9
10
11
12
13
2
22
29
4

2
16
4
17
5
18
6
19
7
14
9
25
15

27

NC
NC
NC
NC
NC24

NC
NC
NC
NC

19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

NC
NC

35
36

NC

NC

NC
20
21
5
24
26
28
30
31

8
21
3
10
11
12
13
26

23
25

22
23

NC
NC
NC

NC
NC
18
NC
19
1

NOTE: NC means No Connection.

20
1

No siRnal
No signal
2-31

Processor PCB

25 23

CN2

1 00
o 0
II I

5 31

0001
0 00 .

7 I 7 7 2 Z I 72 2 II 7 7 Z 121 7 7 7/1//7 I I I 7 Z? 2 I Z I Z 7 I i 7 Z 1117772,",,",

C

26 24

36

6 42

18

G9PFBU PCB

PINS 14 TO 18 AND 32 TO 36 HAVE
NO CONNECTION.
MOUNTED ON THE REAR PANEL
(MARKED PTR).

B

19

1

36

18

I

n---------4;

A

Y

REAR PANEL
CONNECTOR

0

PRINTER CABLE

RIBBON-TYPE INTERCONECTING CABLE

NOTE: SEE TABLE 2-6 FOR PIN NUMBERS AT LOCATIONS A, B, AND C.
Figure 2-21 Parallel Printer Cable Connect
2-32

Processor PCB
Table 2-7 Parallel Printer Interface Signals

SIGNAL

SOURCE

DESCRIPTION

RMS

APC

Receive Machine Set.
This signal is used
with the ODA printer
interface only.

BUSY

Printer

Goes high to indicate
that the printer cannot receive data:
1. During data entry
2. During printing
operation
3. In offline state
4. During printer
error status.

APC

Strobe pulse to read
data in. The signal
level is normally
High. Read-in of data
is performed at the
Low level of this
signal.

STROBE

SG

Twisted-pair return
signal ground level.

SELECT

Printer

Goes high to indicate
that the printer is in
selected state.

ACKNLG

Printer

Acknowledge goes
Low to indicate that
data has been
received and that the
printer is ready to
accept other data.
2-33

Processor PCB

Table 2-7 Parallel Printer Interface Signals (cont'd)

SIGNAL

2-34

SOURCE

DESCRIPTION

INPUT PRIME

APC

Goes Low to initialize
the printer.

DATA 1

APC

Data lines from
8255A, PBO through
PB7. High is logic 1;
Low is logic O.

DATA 2

APC

DATA 3

APC

DATA 4

APC

DATA 5

APC

DATA 6

APC

DATA 7

APC

DATA 8

APC

FAULT

Printer

Goes Low when the
printer is in
1. Paper End state
2. Offline state
3. Error state.

+5 V

Printer

Device Control
(DCN)

PE

Printer

Goes high to indicate
that printer is out of
paper.

Processor PCB

Table 2-8 Parallel Printer Controller Instruction
INSTRUCTION
Write Signal 0

READ/
WRITE

I/O ADDRESS

W

6E

7

6

DATA BUS
5 4 3 2

1

0

I

0

0

1

0

0

1

0

Write Signal 1

W

6E

0

0

0

0

0

I

0

I
N
T
E

Write Signal 2

W

6E

0

0

0

0

0

1

I

R
M
S
M
A
S
K

Write Signal 3

W

6E

0

0

0

0

1

0

0

Write Signal 4

W

6E

0

0

0

0

I

1

I

Write Signal 5

W

6C

X

X

X

X

X

X

R
D
R
Q

P
E

D
A
T
A
2

D
A
T
A
I

I
P

M
A
S
K

5
V

0

0

F
A
U
L
T

D
A
T
A

D
A
T
A

8

7

D
A
T
A
6

D
A
T
A
5

+
Read Signal

Write Data

R

W

68

6A

S
E
L
E
C
T
D
A
T
A
4

0

D
A
T
A
3

I
R
T

2-35

rrocessor reB

Table 2-9 Parallel Printer Controller Instruction Sequence
INSTRUCTION

DESCRIPTION

Write Signal 0

Set the 8255 Mode

Write Signal 1

Interrupt Enable Flag (lNTE)

Write Signal 2
(Not used for
Centronics I1F)

Receive Machine Set (RMS)

Write Signal 3

Mask Set or Reset

Write Signal 4

Input Prime (lP) Set or Reset

Write Signal 5

IP and Mask Set or Reset

Read Signal

Read the status of the printer

Write Data

Write data to be printed

1: Flag On
0: Flag Off
1: RMS On
0: RMS Off

1: Reset
0: Set
1: Reset
0: Set

RECEIVE DATA

DATA
DATA STB
BUSY LOW
INPUT BUSY
ACK

,, I
,,

T4

I
,
I

... '......'.....

I,

+- I..,

I

TS

I

T6

:
I
I

~

T4

Figure 2-22 Parallel Printer Controller Interface Timing
2-36

Tl TO T3 = 1 iJ.s MIN
T4 =100 ns MAX
TS =0.1 TO 0.5 ms
T6 =6 TO 8 iJ.S

Processor PCB

DA T A BUFFER FULL
DATA

~

DATA STB

INPUT BUSY
ACK

"I PRINT

T7

/

BUSY

.,

------------------------~\ ~------T7 = 0.2 TO 1 ms

Figure 2-22 Parallel Printer Controller Interface Timing (cont'd)
NO DATA IS IN THE DATA BUFFER

PE
SELECT
FAULT
BUSY _ _--s
SEL SW ON
RECEIVE DATA
PRINT ONE LINE

STORED DATA IS IN THE DATA BUFFER
PE OCCURS
PE

PE
DESELECT

SELECT
~-------------------------~

FAULT
BUSY ________________~~
PRINT ONE LINE

r-J------

FAULT
BUSY

......
L _ _ _ _ __

Figure 2-23 Parallel Printer Controller Interface at Paper Out Status
2-37

Processor PCB

2.8 KEYBOARD
The Keyboard employs capacitance technology and an 8048, 8-bit microprocessor
that performs keyboard scanning and coding functions. It contains 109 keys in three
major groupings. The central area is a standard typewriter layout. Above the
central area are 22 user-definable function keys in a single row. To the right of the
central area are 25 keys that consist of a numeric entry pad and a set of cursor/
control keys.
As shown in Figure 2-24, the Keyboard is arranged as a matrix (8 x 16), with 128
possible X/Y coordinate output combinations (only 109 of which are represented
by key positions). The 8048 microprocessor, in combination with an LS74159
decoder chip, produces a scan code output function peculiar to each key position
and shift/control status. These scan codes are sent to the Processor PCB on an
eight-bit scan data bus designated SDI through SD8.

Y32

8 X 16

KEY MATRIX

Pressing a key produces a strobe that latches the corresponding scan code into a key
data register or switch (SW) register located on the Processor PCB and generates an
interrupt request. Pressing a switch key (such as FNC or SHIFT) is recorded in an
SW register on the Processor PCB, the output of which is combined with the key
data register to produce the code output.
The CPU I/O address is hexadecimal 48 for the key data register and 4C for the SW
register. The CPU can also read the keyboard status at address 4A.
2-38

Processor PCB
2.8.1 Keyboard Layout and Scan Codes
The Keyboard layout and designated key position numbers are shown in Figure
2-25. The corresponding scan codes are listed in Table 2-10. The scan codes are
usually different than the hex codes for the keys. For hex code information, see
Appendix D.
PROGRAMMABLE FUNCTION KEYS

PFI ..

(I)

I

FNC~

(2)

I

(3)

(4)

(5)

(6)

(7)

(8)

(9)

I

(10)

I

(\1)

I

(12)

I

(13)

I

(14)

•

I

(IS)

I

(16)

I

(17)

I

I

(18)

(19)

!

INS
(S5)

(S6)

.

DEL
(90)

t

I

(21)

CLEAR
HOME PRINT
(S7)
(SS)
7

I

(22)

PF22

I

(23)

I

BREAK
STOP(89)

-

(92)

S
(93)

9
(94)

(95)

(96)

4
(97)

5
(9S)

6
(99)

(100)

(102)

I
(103)

2
(104)

3
(lOS)

(lOS)

(109)

+ (107)

D
D

(20)

(91)

- (101)

I

0

+
E
N
T
E
R

(106)

(NUMBERS IN PARENTHESES DESIGNATE KEY POSITION)

NONLOCKABLE SWITCH KEYS

LOCKABLE SWITCH KEYS

Figure 2-25 Keyboard Layout
Table 2-10 Keyboard Scan Codes
KEY
POSITION

SCAN
CODE

KEY
POSITION

SCAN
CODE

KEY
POSITION

SCAN
CODE

1*
2
3
4
5
6
7
8

80
81
82
83
84
85
86

38
39
40
41
42
43
44
45

9C
98
51
57
45
52
54
59

75
76
77
78
79*
80*
81*
82

4D
2C
2E
2F
-

20

*Positions 1 (FNC), 54 (CTRL), 55 (CAPS LOCK), 68 and 79 (SHIFT), 80 (GRPH 1),81
(GRPH 2), and 83 (ALT) must be used with another key to generate a scan code.
2-39

Processor PCB

Table 2-10 Keyboard Scan Codes (cont'd)

KEY
POSITION

SCAN
CODE

KEY
POSITION

SCAN
CODE

KEY
POSITION

9
10
11
12

87
88
89
8A
8B
8C
8D
8E
8F
90
91

46
47
48
49
50
51
52
53
54*
55*
56
57
58
59
60
61
62
63

55
49
4F
50
5B
5D
5C
5E

83*
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109

13

14
15
16
17

18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37

92

93
94
95
IB
31
32
33
34
35
36
37
38
39
30
50
2D
40

64

65
66
67
68*
69
70
71
72

73
74

-

41
53
44
46
47
48
4A
4B
4C
3A
3B
97
-

5A
58
43
56
42
4E

SCAN
CODE
-

9E
FB
6F
9A
FF
96
FC
6A
77

78
79
6D
F7
74
75
76
6B
FA
F9
71
72
73
FD
F8
70
6E

*Positions 1 (FNC), 54 (CTRL), 55 (CAPS LOCK), 68 and 79 (SHIFT), 80 (GRPH
(GRPH 2), and 83 (ALT) must be used with another key to generate a scan code.

2-40

1),81

Processor PCB

2.8.2

Interface

The Keyboard connects with a coiled multiconductor cable to the rear of the Main
Unit (see Figure 2-26 and Table 2-11). The cable is a shielded 19-wire design that
includes power(+5 Vdc), grounds, and twelve signal lines. The cable is permanently
attached to the Keyboard.

1 3

23 25

1000--------0001
000---------1:] 0 C
2 4

24 26

Figure 2-26 Keyboard Interface

2-41

Processor PCB

Table 2-11 Keyboard Interface Lines
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

2.9

SIGNAL
Not used
Not used
Keyboard Data
Keyboard Data
Keyboard Data
Keyboard Data
Keyboard Data
Keyboard Data
Keyboard Data
Keyboard Data
Signal Ground
Data Strobe
Signal Ground
Not used
Not used
SWItch Strobe
Not used
Not used
Debug
Signal Ground
Signal Ground
Signal Ground
+5 Vdc
+5 Vdc
Not used
Not used

1
2
3
4
5
6
7
8

CALENDAR AND CLOCK GENERATOR

The Calendar and Clock Generator is supported by a CMOS Integrated Circuit
(IC) (NEC JlPDI990AC). This IC independently registers the month, day of the
month, day of the week, hour, minute, and second, and it can receive or send this
information from or to the microprocessor. Because this IC carries out all clock
functions, it frees the microprocessor from these duties, increasing the capabilities
of the microprocessor in other areas.
2-42

Processor PCB

2.9.1 Circuit Description
As shown in Figure 2-27, the clock generator is driven by a 32.768 kHz crystal
oscillator. Should a power break occur, system battery power prevents calendarand-clock data loss. A 14-pin IC encloses all functions.
/-1 PDl990A

co

74LS174
ADO

- - - - - ' ' '.......
~
----.v
AD7 A

TO

TO
C2
STB

6 BIT
LATCH

XL

-

XL
CLK
Dl

~

r--

.1
Cl
T

CS
CONTROL I LOGIC

II--

It----<

32.768 kHz
DO

CS
DE
VDD

G

I
7.7

+5

v'"

VDD

VDD
SUPPLY
CIRCUIT

~

.b
-

J

LED (GREEN)

BATTERY

-

BATTERY
VOLTAGE
CHECKER

~+5V

-

J

74LS367 J o - - - - - - - - - - - - I

Figure 2-27 Clock/Calendar Block Diagram
2-43

Processor PCB

2.9.2

Programming Considerations

Input and output of clock/calendar data is available on command as a 40-bit serial
word having the following format.
MSB

LSB

4 bits

4 bits

8 bits

8 bits

8 bits

8 bits

month

day of wk.

date

hour

minute

second

The writelread instruction format is shown in Table 2-12 and Figure 2-28.

Table 2-12 Clock/Calendar Instruction Format
INSTRUCTION

Set Register

Read Data

2-44

READ/
WRITE

I/O
ADDRESS

W

58

R

58

7

6

0

-

0

-

DATA BUS
5 4
3 2
D
I

-

C
L
K

-

;

DESCRIPTION
0

S
T C2 CI CO
B

-

-

B
A
T
T

D

0

See Figure
2-28(1)

See Figure
2-28 (2)

Processor PCB

COMMAND SUMMARY
(I)

SET REGISTER
6
5
4
3 2
r--r-""""T'""""'T--'---'-,

0

-r,--.,--.,

_BIT:"il'VlBER

DON'T CARE

('2 CI Co

o
o
I

0
0

o
0

o
I

L -_ _ _ _ _

0

I
I

0
I
0

STROBE

' - - - - - - - - CLOCK

REGISTER HOLD COMMAND
REGISTER SHIFT COMMAND
TIME SET/COliNTER HOLD COMMAND
TIME READ COMMAND
ILLEGAL
ILLEGAL
ILLEGAL
ILU:(;AL

COMMANDS «('2, CI, CO) ARE INDEPENDENTLY LATCHED BY
TIlE STB INPUT

DATA INPUT/OUTPUT IN SYNCHRONIZATION WITH CLK INPUT

' - - - - - - - - - - D A T A INPUT

(2)

READ DATA

DATA OUTPLT

' - - - - BATTERY VOLTM;E CIIECK

0= NORMAL (ELECTRO-CHEM>3,OV, SANYO>2..W)
I = LOW (ELECTRO-CIlEM~3.0V, SANYO~2.3V)

Figure 2-28 Clock/Calendar Format

2-45

Processor PCB

2.10

JUMPER SETTINGS

The Processor PCB has four jumpers (TMl, TM2, TM3, and TM4). TMI is not
related to system functions, but to battery replacement. To prevent harm to the
diode when replacing the battery, TM 1 must be removed.
To adapt the APC interface for a Centronics-type or aDA printer, set TM2, TM3,'
and TM4 as instructed in Figure 2-29.

FS2s9l D o g ~M! C
0
eN!
@CJD 0
c:::F
ODD 000 2
c::J
U
CJ

CJ~

c::J~
c::J D CJ-=D~c::J
DO
c::J 0 Q§J
~Doo DO
c::::J

D

D D
c=JD
0 D O D c=J

0000000

DDDDDDCJ
c::JODDDOCJ
c::J2! D

g

CJ ~

c:J

DODOO=D
c::JD 0 0 0 Cl
c::JCl 0 0 0 Cl 0
OODDDClO

G9PFBU

FOR CENTRONICS·TYPE
PRINTER INTERFACE
TM2

[J]
TM3

Q]

m

(SHORTED)

FOR ODA·TYPE
PRINTER INTERFACE
TM2

~
TM3

[D
I

2
TM4

[;]
(SHORTED)

Figure 2-29 Processor PCB Jumper Settings
2-46

Chapter 3

Controller PCB
The Controller PCB (G9PFCU) is the same size and has the same general physical
arrangement as the Processor PCB. Like the Processor PCB, it fits into the Mother
Board with a 100-pin card-edge socket. It is normally located in the first slot
position (closest to the CRT).
Installed on the Controller PCB are five cable connectors: a communications
interface connector, a CRT interface connector, an FDD interface connector, a
speaker interface connector, and a volume interface connector (see Figure 3-1).
Figure 3-2 shows the functional relationships between the five principal components that occupy the Controller PCB.
• CRT Display control for the 12.;.inch monochrome or color display -designed around the ~PD7220 graphic display controller
• An 8-inch FDD control, that can read from and drive double-sided doubledensity flexible disks or single-sided single-density disks
• Serial 110 device control, supported by the NEC 8251A controller, converts
serial data to parallel data and parallel data to serial data -- it can do so
synchronously or asynchronously, using half- or full-duplex at various
baud rates
• Sound control is supported by Large-Scale Integration (LSI) NEC
~PD 1771-006 and generates signal beeps and programmed melodies
• Arithmetic processing unit, an optional device, that provides high performance fixed-and-floating-point arithmetic operations and floating-point trigonometric operations.
3.1 MOTHER BOARD/CARD CAGE INTERFACE
For a description of this interface, see Section 2.1.

3-1

Controller PCB

ARITHMETIC
PROCESSING
LSI
(OPTIONAL)

CRT
CONTROL
CLOCK

D
D

D

D

D
D'
I
I

COMMCNICA T10N
LSI

COMMliNICA T10N
INTERFACE
CONNECTOR

1

I

D

D

0

I
I

1

D
D

1

~

CRT UNIT
INTERFACE
CONNECTOR

,
1

D

..

~

0
0
D

1 TM3
1

1

I
~::
6116
D D
1

FDD
CONTROL
CLOCK

0 0

DD

'0
I

FDD
INTERFACE
CONNECTOR

6116

1

CRT
REFRESH
MEMORY

D
,

I

ID

1

~

GJo

0
D

CRT CONTROL LSI

Figure 3-1 Controller PCB
3-2

SPEAKER
INTERFACE
CONNECTOR

VOLUME
INTERFACE
CONNECTOR

SOllND LSI

FDD
CONTROLLER

Controller PCB

7220
GRAPHIC
DISPLAY
CONTROL

OSl TO 4

LWC, D1R, FLR. STP. WOT. HOL. SSL. MFM.
WGT. VSYN
ROY. PRT. TSO. FUS. TKO. IDX.
ROT. WID
SD

D8251
SERIAL

VO

SD. RS. ER. ST I

DEVICE
CONTROL

RD. CS. DR. RT. ST2

(O.CI

8231
ARITHMETIC

INT.14

PROCESSING
UNIT

1771-006
SOUNO
CONTROL

:=3

VOLUME

Figure 3-2 Controller PCB Block Diagram
3-3

Controller PCB

3.2 CRT DISPLAY CONTROL
This adapter connects the microprocessor with a 12-inch monochrome or color
display. At the heart of this computer-graphics system is the ,uPD7220 Graphic
Display Controller (GDC), an intelligent LSI microprocessor that carries out the
high-speed and repetitive duties required to generate the raster display and manage
the display memory. The GDC duties include
• Generating the basic video raster timing (including sync and blanking
signals)
• Video-display-memory modification and data moves
• Calculating display-memory addresses.
Some characteristics of the CRT-control design are
• Display buffer is independent of system memory
• An 80-character by 25-line screen (2000 characters)
• A 26th line reserved for system status information
• Direct drive output
• An 8-dot by 19-dot character box
• A 7-dot by II-dot character
• 8-dot by 16-dot special programmable characters.
A character generator supplies the video process logic with the information necessary for displaying the characters. Additionally, a special-character generator
contains the fonts for user-programmable characters; these are 8 by 16 characters in
8 by 19 character boxes.
In the display-control adapter is a character-code buffer memory that stores character codes or special-character codes (each character has 1 of 256 codes in RAM or
250 codes in ROM, of which 6 in ROM are not assigned) and an attribute-code
buffer memory that stores character attributes (each character is associated with
one or more of eight attributes). Figure 3-3 shows the functional relationships
between the principal components of CRT control.

3-4

Controller PCB

ATTRIBITE f-------'
ME\IOR\

ATTRIBITf:
REGISTER

1----'

REFRESH
MEMOR\

16 BIT
SillFT
REGISTER

ROM
('G

(,G 81'S

('O'-.C7 C6 C5 C4 C3 C2 CI CO
CI5 CI4 CI3 CI2 CII CIO C9 C8

Writes the charactercode data into the
display memory.

C
PI

0
C7

LOW BYTE CODEW
I
I
0
0 "'MOD...
C5 C4 C3 C2 CI CO

Writes the low-order
byte of the
character-code data
into the display
memory.

C
PI

HIGH BYTE CODEW
0
0
I
I
0 ... MOD.,.
I
CI5 CI4 CI3 CI2 CII CIO C9 C8

0
C6

I
A5
AI3
SLi
SL9
A5
AI3
SLi
SL9

Al AO
A9 A8
0
0
SLS SL4
Al AO
A9 A8
0
0
SL5 SL4

Writes the high-order
byte of the
character code data
into the display
memory.

3-15

Controller PCB

Table 3-5 GDC Commands (cont'd)

3-16

COMMAND/
PARAMETER

D7

D6

DATA BUS
D5
D4
D3

D2

DI

DO

C
PI

0
P7

I
P6

0
P5

PITCH W
0
0
P4
P3

I
P2

I
PI

I
PO

REMARKS
Specifies the width
of the X dimension
of the display
memory.

C
PI
P2

MASK W
0
I
0
0
I
0
I
0
MA7 MA6 MA5 MA4 MA3 MA2 MAl MAO
MAI5 MAI4 MAI3 MAI2 MAil MAIO MA9 MA8

Sets the mask
register contents.

C
PI
P2
P3
P4
P5
P6
P7
P8
P9
PIO
PI I

VECTW
I
0
0
I
R
C
T
L
DC6 DC5 DC4 DC3
DGD DCI3 DCI2 DCII
D7
D6
D4
D3
D5
DI3 DI2 Dli
D27 D26 D25 D24 D23
D213 D212 D2II
DI7 DI6 DI5 DI4 DI3
DII3 DI12 DIll
DM7 DM6 DM5 DM4 DM3
DMI3 DMI2 DMII

Vector parameters
set: specifies the
parameters for the
drawing processor.

0
SL
DC7

I
0
0
.-DIR---..
DC2 DCl DCO
DCIO DC9 DC8
D2
DI
DO
DIO D9
D8
D22 D2I D20
D210 D29 D28
DI2 DII DIO
DIIO Dl9 DI8
DM2 DMI DMO
DMIO DM9 DM8

WORD CODER
0
0
0 ...-MOD-.

C

I

0

I

C

I

0

LOW BYTE CODER
I
I
0
0

...-MOD-.

Reads the
character-code data
from the display
memory.
Reads the loworder byte of the
character-code data
from the display
memory.

Controller PCB

Table 3-5 GDC Commands (cont'd)
COMMAND/
PARAMETER

07

06

05

C

I

a

I

I

C

I

I

I

a

C

a

a

I

WORD DREQW
a a I ~MOD . .

Requests a DMA
write transfer for the
entire word.

C

a

a

LOW BYTE DREQW
I
I
a I ~MOD~

Requests a DMA
write transfer for the
low-order byte only.

C

a

a

HIGH BYTE DREQW
I
I
I
I ~MOD'"

Requests a DMA
write transfer for the
high-order byte only.

C

I

a

I

WORD DREQR
a a I .... MOD ...

Requests a DMA
read transfer for the
entire word.

C

I

0

LOW BYTE DREQR
I
I
a I ~MOD'"

Requests a DMA
read transfer for the
low-order byte only.

C

I

0

HIGH BYTE DREQR
I
I
I
I ....MOD ...

Requests a DMA
read transfer for the
high-order byte only.

DATA BUS

04

03

02

DI

DO

HIGH BYTE CODER
I

o

~MOD~

CSR R

a

a

a

a

REMARKS
Reads the highorder byte of the
character-code data
from the display
memory.
Reads the display
position of the cursor.

3-17

comrOller rCli

Table 3-6 GDC Command Constants
COMMAND/
PARAMETER

SETTING VALUE
(HEX)

C
PI
P2
P3
P4
P5
P6
P7
P8

SYNCSET
10
4E
52
OE
06
13
EE
45

C

Master/slave

C
PI

ZOOMW
00

Zooming disabled

C
PI
P2
P3

CSR DISP
12
CI
8B

Blinking block cursor

C
PI

PITCH W
50

80 characters per row

C
PI
P2

MASKW
FF
FF

3.3

REMARKS
Character display mode '0': no
interlace, flash less drawing, static
RAM, 80 characters per row

Master versus slave video
synchronization

CRT DISPLAY UNIT

The CRT Display unit consists of a chassis-mounted circuit, a 12-inch monochrome
or color CRT Display, Controller PCB, and internal power unit.
The monochrome or color display units connect to the Controller PCB (see Figures
3-9 and 3-10).

3-18

Controller PCB
BRIGHTNESS CONTROL

CONTROLLER PCB

CRT
DISPLAY
UNIT

~

Z

U

INTERNAL
POWER
SUPPLY
GDC

PIN ASSIGNMENT

BRIGHTNESS ADJUSTMENT

1

/
/..--1

GROUND

A

1

B

2

C

3

/

D

4

10

.... _- GROUND

E

5

12

HORIZONTAL DRIVE

F

6

{r\
\

CN4

\!

./

NOT USED

16
18
20

VIDEO
VERTICAL DRIVE
GROUND

MONOCHRO ME
CRT
DISPLAY
UNIT

7

J

8

K

9

L

10

Figure 3-9 Monochrome-CRT Display Interface
3-19

Controller PCB

CONTROLLER PCB

BRIGHTNESS CONTROL

/
COLOR
CRT
DISPLAY
UNIT

.,.
Z

U

INTERNAL
POWER
SUPPLY
GDC

PIN ASSIGNMENT
1, 3, 5, 7, 9, 10, 11 GROUND
4,6,8

NOT USED

12 HORIZONTAL DRIVE
13
CN4

14, 15

VIDEO (RED)
GROUND

16

VIDEO (GREEN)

17

GROUND

18

VERTICAL DRIVE

19

VIDEO (BLUE)

20

GROUND

1, 3, 5, 7, 9, 10, 11
4,6,8
12
13
14,15
16

COLOR
CRT
DISPLAY
UNIT

17
18
19
20

Figure 3-10 Color-CRT Display Interface
Another internal cable, the power supply cable, carries 115 Vac power from the
system power supply to the internal power supply oftn:? CRT Display. This internal
power unit provides the CRT Display with +12 Vdc.
3-20

Controller PCB
The following items are the principal operating characteristics of the monochrome
CRT Display.

• Display control. A brightness control knob is available to the operator on
the front of the unit.
• Monochrome Display screen. The Monochrome CRT Display employs a
yellow-green, long-persistence phosphor (P39) and has a reduced-glare
surface. The display format is 80 characters wide by 25 lines high plus one
status line. Each standard character consists of a 7 (width)-by-ll (height)
dot matrix. Special characters can be as large as 8-by-16 dots. The screen is
composed of 475 lines of vertical resolution.
• Color Display screen. The Color Display has an 8-color, high-resolution,
reduced-glare screen.
• Horizontal drive. This positive level, TTL compatible frequency is 22.727
kHz. The minimum pulse width is 3 JiS.
• Vertical drive. This frequency is 41.5 Hz and is negative leveVTTL compatible.
• Video signal. The video signal is positive level with a 50-ns minimum pulse
width.
• CRT Display interface.
3.4

FLEXIBLE DISK DRIVE CONTROLLER

The APC has space and power for two 8-inch FDDs. The drives are soft-sectored
and two-sided, with 77 cylinders (0 to 76). They use Modified Frequency Modulation (MFM) coded in 256 byte sectors (except index track), giving an unformatted
capacity of about 1.2 MB per drive. They have a track access time of 5 ms.
The 8-inch Flexible Disk Drive Controller (FDC) on the Controller PCB attaches
to the FDD with an internal flat cable, which is daisy-chained if there are two
FDDs.
The FDC is designed for double-density MFM-coded drives, uses write precompensation, and employs the NEC JiPD765. The FDC uses DMA for record-data
transfers. An interrupt level indicates completed operation or a status condition
that requires processor attention.
Figure 3-11 is a functional block diagram of the FDe. This controller contains two
registers that can be accessed by the main processor: a status register and a data
register. The 8-bit main status register contains the status information of the FDC
and can be accessed at any time. This register facilitates the transfer of data between
the processor and FDC. It can be read only. Table 3-7 summarizes the bit functions
of the main status register.

3-21

Controller PCB

The 8-bit data register (which actually consists of several registers in a stack with
only one register presented to the data bus at a time) stores data, commands,
parameters, and FDD status information. Data bytes are written into the data
register to program the FDC and are read out of it to obtain results after a
command.
The FDC can perform 15 different commands. Each command is initiated by a
multibyte transfer from the processor, and the result after execution of the command can also be a multibyte transfer back to the processor. Because of this
multi byte interchange of information between the FDC and the processor, each
command can be considered in three phases.

• Command Phase - The FDC receives all information required to perform a
particular operation from the processor.
• Execution Phase - The FDC performs the operation.
• Result Phase - Status and other housekeeping information are made
available to the processor.

I

CLOCK &
TIMING

I ...

I------<~I WRITE

-.J PRECOMP 11---1><>-----'

CIRCUIT

I

-I CIRCUIT

....

~
I ~:;:E
VFO SYNC ...

DMA
A
REQUEST.....
DMA -C>o-"----I

FLEXIBLE
DISK
CONTROLLER
LSI

H
H

DATA WINDOW

A

RD DATA

":::!

DECODER

ACKNOWL~DGE

L

fDD

DR IV\<: A SELECT
..hl'RIVE B SELECT
...
..
....

...

.

...

INTERRUPT
REQUEST

...

STEP
DIRECTION

,

r

i

WRITE GATE
HEAD LOAD
SIDE SELECT
MFM
LOW CURRENT

..

FILE UNSAFE RESET

A

..

READY

A

......,-

... WRITE PROTECT

A

...

3-22

TRACKO

.,.. INDEX
A

Figure 3-11 FDe Block Diagram

TWO SIDED

FILE UNSAFE

Controller PCB

Table 3-7 Bit Description of the FDC Main Status Register

BIT
NUMBER

NAME

DESCRIPTION

SYMBOL

DBO

FDD A Busy

DAB

FDD A is in the Seek Mode.

DBI

FDD B Busy

DBB

FDD B is in the Seek Mode.

DB2

FDD C Busy

DCB

Not used.

DB3

FDD D Busy

DDB

Not used.

DB4

FDC Busy

CB

A read or write command is in
process.

DB5

Non-DMA
Mode

NDM

The FDC is in the Non-DMA
Mode.

DB6

Data Input/
Output

DIO

Indicates direction of data transfer
between the FDC and the processor. DIO = '1' indicates transfer is
from FDC data register to the
processor; DIO = '0' indicates
transfer is from processor to FOC
data register.

DB7

Request for
Master

RQM

Indicates Data Register is ready to
send or receive data to or from the
processor. Both bits DIO and RQM
should be used to perform the
handshaking functions of "ready"
and "direction" to the processor.

3-23

Controller PCB

Figure 3-12 is a timing diagram that defines the timing of this three-phase command
process.
r....-

DATA SEND

PROCESSOR

DlO

COMMAND
PHASE

_ _.A_ _ _,

RESULT
PHASE

EXECUTION
PHASE
~

~

DA T A RECEIVE

DATA SEND

•

+I

I

---+-----11-----'

L

I

RQM

FDC

DATA
RECEIVE

DATA
RECEIVE

DATA
SEND

Figure 3-12 FDC Timing Diagram
3.4.1

Programming Considerations

Table 3-8 defines the symbols used in the FDC command summary given in Table
3-9. Tables 3-10, 3-11, 3-12 and 3-13 define the bit functions of the command status
registers. Table 3-14 lists the 110 addresses and functions of the FDC registers.
Table 3-8 FDC Symbols
SYMBOL

3-24

NAME

DESCRIPTION

AO

Address Line 0

Controls the selection of the Main Status
Register (AO=O) or Data Register
(AO=l).

C

Cylinder Number

Specifies the selected cylinder number.

D

Data

Specifies the data pattern that is going to
be written into a sector.

D7 to DO

Data Bus

8-bit Data Bus, where D7 is the most
significant bit, and DO is the least
significant bit.

DTL

Data Length

When N is defined as 00, DTL is the
data length that users are going to read
out or write into the sector.

EOT

End of Track

Indicates the final sector number on a
cylinder.

Controller PCB
Table 3-8 FDC Symbols (cont'd)
SYMBOL

NAME

DESCRIPTION

GPL

Gap Length

Specifies length of Gap 3 (spacing
between sectors excluding VCO Sync.
Field).

H

Head Address

Specifies the head number 0 or 1, as
specified in the ID field.

HD

Head

Specifies the selected head number 0 or
1. (H = HD in all command words.)

HLT

Head Load Time

Indicates the head load time in the FDD
(2 to 256 ms in 2-ms increments).

HUT

Head Unload Time

Indicates the head unload time after a
read or write operation has occurred (0
to 240 ms in 16-ms increments).

MF

FM or MFM Mode

If MF is Low, FM Mode is selected; if
High, MFM Mode is selected only if
MFM is implemented.

MT

Multi-Track

If MT is High, a multitrack operation is
to be performed. (A cylinder under both
HDO and HDI is read or written.)

N

Number

Specifies the number of data bytes written in a sector.

NCN

New Cylinder
Number

New cylinder number, which is going to
be reached as a result of the Seek operation. Desired position of head.

ND

Non-DMA Mode

Signals that operation is Non-DMA
Mode.

PCN

Present Cylinder
Number

Designates cylinder number at the
completion of Sense Interrupt Status
Command, indicating the position of the
head at present time.
3-25

Controller PCB

Table 3-8 FDC Symbols (cont'd)
SYMBOL

NAME

DESCRIPTION

R

Record

Specifies the sector number, which is
read or written.

R/W

Read/Write

Specifies the Read (R) or Write (W)
signal.

SC

Sector

Indicates the number of sectors per
cylinder.

SK

Skip

Specifies the Skip Deleted Data Address
Mark.

SRT

Step Rate Time

Specifies the Stepping Rate for the FDD
(1 to 16 ms in I-ms increments).

°

3-26

ST
ST 1
ST 2
ST 3

Status
Status
Status
Status

0
1
2
3

STP

Scan Test

During a Scan operation, if STP = 1, the
data in contiguous sectors is compared
byte by byte with data sent from the
processor (or DMA). If STP = 2, then
alternate sectors are read and compared.

USO,
USI

Unit Select

Specifies the selected drive number.

Specifies which of four registers will
store the status information after a
command has been executed. This
information is available during the result
phase after command execution. These
registers should not be confused with the
main status register (selected by AO = 0).
ST 0 to 3 can be read only after a
command has been executed. They
contain information relevant to that
particular command.

Controller PCB

Table 3-9 FDC Commands
PHASE

Command

READ/
WRITE

W
W
W
W
W
W
W
W

D7

D6

D5

MT MF
X
X

SK
X

W

DATA BUS
D4 D3 D2
READ DATA
I
0
0
HD
X
X
C
H
R
N
EOT
GPL
DTL

DI

DO

I
USI

usa

0

Command

Data transfer between
the FDD and main
system
R
R
R
R
R
R
R

W
W

W
W
W

W
W
W
W

STO
STI
ST2
C
H
R
N

MT
X

MF
X

READ DELETED DATA
I
I
SK
0
0
X
X
X
HD USI
C
H
R
N
EOT
GPL
DTL

Execution

Result

Command Codes
Sector ID information
prior to Command
execution

Execution

Result

REMARKS

Status information after
Command execution
Sector ID information
after Command
execution

0

usa

Command Codes
Sector ID information
prior to Command
execution

Data transfer between
the FDD and main
system
R
R
R
R
R
R
R

STO
STI
ST2
C
H
R
N

Status information after
command execution
Sector ID information
after command
execution

X = Don't care.

3-27

Controller PCB
Table 3-9 FDC Commands (cont'd)
PHASE

Command

READ/
WRITE

W
W
W
W
W
W
W
W
W

D7

D6

D5

MT MF
X
X

0
X

DATA BUS
D4 D3 D2
WRITE DATA
I
0
0
X
X HD
C
H
R
N
EOT
GPL
DTL

DI

DO

0
USI

usa

I

Command

Data transfer between
the main system and
FDD
R
R
R
R
R
R
R

W
W
W
W
W
W
W
W
W

STO
STI
ST2
C
H
R
N

MT MF
X
X

WRITE DELETED DATA
I
0
0
0
0
X
X
X HD USI
C
H
R
N
EOT
GPL
DTL

Execution
Result

Status information after
command execution
Sector ID information
after command
execution

I

usa

Command Codes
Sector ID information
prior to command
execution

Data transfer between
FDD and main system
R
R
R
R
R
R
R

X = Don't care.

3-28

Command Codes
Sector ID information
to command execution

Execution

Result

REMARKS

STO
STI
ST2
C
H
R
N

Status ID information
after command
execution
Sector ID information
after command
execution

Controller PCB

Table 3-9 FDC Commands (cont'd)
PHASE

Command

READ/
WRITE

W
W
W
W
W
W
W
W
W

D7

D6

0
X

MF
X

D5

DATA BUS
D4 D3 D2

READ A TRACK
SK
0
0
0
X
X
HD
X
C
H
R
N
EOT
GPL
DTL

DI

DO

I
USI

usa

0

Command

Data transfer between
the FDD and main
system. FDD reads all
of cylinders contents
from index hole to EOT.
R
R
R
R
R
R
R

W
W

STO
STI
ST2
C
H
R
N

0
X

MF
X

0
X

READ ID
0
I
0
HD
X
X

Execution

Result

Command Codes
Sector ID information
prior to command
execution

Execution

Result

REMARKS

Status information after
command execution
Sector ID information
after command
execution

I
USI

0

usa

Command Codes
The first correct ID
information on the
cylinder is stored in data
register

R
R
R
R
R
R
R

STO
STI
ST2
C
H
R
N

Status information after
command execution
Sector ID information
during execution
phase

X = Don't care.

3-29

Controller PCB

Table 3-9 FDC Commands (cont'd)
PHASE

Command

READ/
WRITE

W
W
W
W
W
W

D7

D6

0
X

MF
X

D5

DATA BUS
D4 D3 D2

D]

FORMAT TRACK
]
]
0
0
0
X
X
HD US]
X
N
SC
GPL
D

DO

0

usa

Command

FDC formats an entire
cylinder
R
R
R
R
R
R
R

W
W
W
W
W
W
W
W
W

STO
ST]
ST2
C
H
R
N

MT MF
X
X

SCAN EQUAL
]
0
0
X
X
X HD
C
H
R
N
EOT
GPL
STP

SK

Execution

Result

Status information after
command execution
In this case, the ID
information has no
meaning

0
US]

]

usa

Command Codes
Sector ID information
prior to command
execution

Data compared between
the FDD and main
system
R
R
R
R
R
R
R

X = Don't care,

3-30

Command Codes
Bytes/Sector
Sector/Track
Gap 3
filler byte

Execution
Result

REMARKS

STO
STI
ST2
C
H
R
N

Status information after
command execution
Sector ID information

Controller PCB

Table 3-9 FDC Commands (cont'd)
PHASE

Command

READ/
WRITE

W
W
W
W
W
W
W
W
W

D7

D6

MT MF
X
X

D5

DATA BUS
D4 D3 D2

DI

SCAN LOW OR EQUAL
SK
1
1
0
0
X
X
X HD USI
C
H
R
N
EOT
GPL
STP

DO

1

usa

Command

Data compared between
the FDD and main
system
R
R
R
R
R
R
R

W
W

w
W
W
W
W
W
W

STO
STI
ST2
C
H
R
N

MT MF
X
X

SCAN HIGH OR EQUAL
SK
1
1
1
0
X
X
X HD USI
C
H
R
N
EOT
GPL
STP

Execution

Result

Command Codes
Section ID information
prior to command
execution

Execution

Result

REMARKS

Status information after
command execution
Sector ID information
after command
execution

1

usa

Command Codes
Sector ID information
prior to command
execution

Data compared between
the FDD and main
system

R
R
R
R
R
R
R

STO
STI
ST2
C
H
R
N

Status information after
command execution
Sector ID information
after command
execution

X = Don't care.

3-31

Controller l'ClJ

'{able 3-9 FDC Commands (cont'd)
PHASE

Command

READ/
WRITE

W
W

07

06

0

0

X

X

DATA BUS
04 03 02

01

DO

RECALIBRA TE
0
0
1
X
X
X
0

1
USI

usa

05

0

1

Execution
No Result
Phase

W
R
R

Command

W
W
W

No Re,ult
Phase

Result

Command

Command Codes
Head retracted to
track 0

Command
Result

Command

REMARKS

W
W
R

W
W
W

Execution

0

SENSE INTERRUPT STATUS
0
0
1
0
0
0
STO
PCN

0
0
0
.-SRT
HLT

..
0
X

0
X

..

0
X

0
X

SPECIFY
0
0
0
~

.

I
I
HUT-.. NO

SENSE DRIVE STATUS
0
0
0
1
0
X
X
X
HD USI
ST3

0
X

0
X

SEEK
1
X
NCN

I
HD

0

I
USI

0

usa

Command Code
Status information
about the FDD at the
end of seek operation

Command Codes

Command Codes
Status information
about FDD

1

usa

..

Command Codes

Head is positioned over
proper cylinder on
diskette

No Result
Phase

Command

W

INVALID
Invalid Codes

Result

R

STO

X = Don't care.

3-32

Invalid command codes
(NoOp - FDC goes into
standby state)
STO = 80

Controller PCB
Table 3-10 FDC Status Register 0
NUMBER

BIT
NAME

SYMBOL

07

DESCRIPTION
D7 = 0 and 06 = 0
Normal termination (NT) of
command. Command was completed
and properly executed.
07 = 0 and D6 = 1
Abnormal termination (AT) of
command. Execution of command
was started, but not successfully
completed.
07 = 1 and 06 = 0
Invalid command issue (IC). Command which was issued was never
started.
D7 = 1 and D6 = 1
Abnormal termination because during command execution the ready
signal from FOO changed
state.

Interrupt
Code

IC

05

Seek End

SE

When the FDC completes the Seek
command, this flag is set to 1 (High).

D4

Equipment
Check

EC

If a fault signal is received from the
FDD, or if the track 0 signal fails to
occur after 77 step pulses (recalibrate
command), then this flag is set.

D3

Not Ready

NR

When the FDD is in the not-ready
state and a read or write command is
issued, this flag is set. If a read or
write command is issued to side 1 of
a single sided drive, then this flag is
set.

02

Head
Address

HO

This flag is used to indicate the state
of the head at interrupt

Dl
DO

Unit Select 1
Unit Select 0

US 1

These flags are used to indicate a
Drive Unit number at interrupt.

06

usa

3-33

Controller PCB
Table 3-11 FDe Status Register 1
BIT
NAME

NUMBER

3-34

SYMBOL

DESCRIPTION

D7

End of
Cylinder

EN

When the FDC tries to access a
sector beyond the final sector of a
cylinder, this flag is set.

D6

-

-

Not used. This bit is always 0 (Low).

D5

Data Error

DE

When the FDC detects a CRC error
in either the ID field or the data
field, this flag is set.

D4

Over Run

OR

If the FDC is not serviced by the
main systems during data transfers
within a certain time interval, this
flag is set.

D3

-

-

Not used. This bit is always 0 (Low).

D2

No Data

ND

During execution of a Read Data,
Write Deleted Data, or Scan command, if the FDC cannot find the
sector specified in the ID register,
this flag is set. During execution of
the Read ID command, if the FDC
cannot read the ID field without an
error, then this flag is set.
During the execution of the Read-aCylinder command, if the starting
sector cannot be found, then this
flag is set.

Dl

Not
Writable

NW

During Execution of a Write Data,
Write Deleted Data, or Format a
Cylinder command, if the FDC
detects a write protect signal from
the FDD, then this flag is set.

DO

Missing
Address
Mark

MA

If the FDC cannot detect the ID
Address Mark, this flag is set. Also
at the same time, the MD Flag of
Status Register 2 is set.

Controller PCB
Table 3-12 FDC Status Register 2
BIT
NAME

NUMBER

SYMBOL

DESCRIPTION

07

-

-

Not Used. This bit is always 0
(Low).

06

Control Mark

CM

During execution of the Read
Data or Scan command, if the
FDC encounters a sector that
contains a Deleted Data
Address Mark, this flag is set.

05

Data Error in
Data Field

DO

If the FDC detects a CRC error
in the data, then this flag is set.

04

Wrong Cylinder

WC

This bit is related with the NO
bit, and when the contents of C
on the medium are different
from that stored in the 10
Register, this flag is set.

03

Scan Equal Hit

SH

During execution of the Scan
command, if the condition of
"equal" is satisfied, this flag is
set.

02

Scan Not
Satisfied

SN

During execution of the Scan
command, if the FDC cannot
find a sector on the cylinder
that meets the condition, then
this flag is set.

01

Bad Cylinder

BC

This bit is related with the NO
bit, and when the contents of C
on the medium are different
from that stored in the ID
Register and the content of C is
FF, then this flag is set.

DO

Missing
Address Mark
in Data Field

MD

When data is read from the
medium, if the FDC cannot find
a Data Address Mark or
Deleted Data Address Mark,
then this flag is set.

3-35

Controller PCB

Table 3-13 FDC Status Register 3
BIT
NAME

NUMBER

SYMBOL

DESCRIPTION

07

Fault

FT

Indicates the status of the Fault
signal from the FDD.

06

Write Protected

WP

Indicates the status of the Write
Protected signal from the FDD.

05

Ready

RY

Indicates the status of the
Ready signal from the FDD.

D4

Track 0

TO

03

Two Side

TS

Indicates the status of the Two
Side signal from the FDD.

02

Head Address

HD

Indicates the status of Side
Select signal to the FDD.

01

Unit Select 1

USI

Indicates the status of the Unit
Select 1 signal to the FDD.

DO

Unit Select 0

usa

Indicates the status of the Track
the FDD.

o signal from

Indicates the status of the Unit
Select 0 signal to the FDD.

Table 3-14 FDC Register I/O Addresses and Functions
I/O
ADDRESS

3-36

READ/
WRITE

FUNCTION

50

Read

Read-Status Register

52

Read

Read-Data Register

52

Write

Write-Data Register

Controller PCB

3.4.2

Drive A and B Interface

All signals are TTL compatible, and all outputs are driven by open-collector gates.
The drives provide termination networks; each input is terminated with a ISO-ohm
resistor. The output signals are described in Table 3-15, the input signals are
described in Table 3-16.
Table 3-15 Output Signals
SIGNAL

DRIVER

DESCRIPTION

Drive Select A
and B

7445

When the line associated with a drive is not
active, these two lines are used by Drives A and B to
degate all drivers to the adapter and all receivers
from the attachment.

Step

7406

The selected drive moves the read/write head one
cylinder in or out (according to the direction-line
signal) for each pulse present on this line.

Direction

7406

F or each recognized pulse of the step line, the
read/write head moves one cylinder toward the
spindle if this line is active, and away from the spindle if this line is inactive.

Write Data

7406

For each inactive-to-active transition of this line
(while Write Enable is active), the selected drive
causes a flux change to be stored on the
disk.

Write Gate

7406

Unless this line is active, the drive disables the write
current for the head.

Head Load

7406

While this line is active, the drive loads the read/
write ~ead.

Side Select

7406

The read/write head selects which side of the flexible
disk to read/write.
0= head 0
I = head 1

M/FM

7406

This signal selects the Code-Reading Mode, FM or
MFM.
0= FM Mode
1 = MFM Mode

3-37

Controller PCB

Table 3-15 Output Signals (cont'd)
SIGNAL

DRIVER

DESCRIPTION

VFO Sync

7406

This signal enables or disables the VFO Circuit
Mode.
0= enable
1 = disable

Low Current

7406

This line relays head-position information to the
drive.

File-Unsafe Reset

7406

This line resets a drive if it is in fault status.

Table 3-16 Input Signals
SIGNAL

3-38

DESCRIPTION

Index

The selected drive supplies one pulse per disk revolution
on this line.

Write Protect

The selected drive activates this line when a write protected diskette is mounted in the drive.

Track 0

The selected drive activates this line when the read/write
head is over Track O.

Read Data

The selected drive supplies a pulse on this line for each
flux change encountered on the disk; it relays data from
the flexible disk.

Ready

This line becomes active when the selected drive is ready.

Dual Side

When a dual-sided disk is mounted on the drive, this line
becomes active.

File Unsafe

If the drive is in a fault state, the selected drive activates
this line.

Data Window

The selected drive combines read data with clock data,
which allows the FDC to discriminate data from read
data.

Controller PCB

3.5

FDD UNIT

The 8-inch FDD is a two-sided, double-density unit that can read from and write to
one-sided and single-density flexible disks as well. The FDD can read and record
digital data using either FM or MFM. Signal transfer is in the VFO Mode.
The FDD unit attaches to the FDC with the signal cable and the flexible disk
interface connector, which is located on the Controller PCB (see Figure 3-1). A
power cable connects each FDD unit to the APC power supply.
To enable disk reading, insert a disk, and close the front latch; this causes the drive
hub to clamp the disk and turn it at 360 rpm. When an index sensor detects the index
hole, it activates a signal. The stepper motor positions the read/write heads over the
desired tracks for reading.
3.5.1 Specifications
The FDD specifications are listed in Table 3-17.

Table 3-17 FDD Specifications
CHARACTERISTIC

SPECIFICA TION

Transfer Rate
FM
MFM

31.25 KB/sec
62.5 KB/sec

Disk Speed

360 rpm

Seek Time

5 ms track to track

Seek Settling Time

15 ms

Head-Load Time

50 ms

Tracks Per Inch

48

Maximum Bits Per Inch
FM
MFM

3.408
6.816

Recording Mode

FMorMFM

3-39

Controller PCB

Table 3-17 FDD Specifications (cont'd)
CHARACTERISTIC
Dimensions
Height
Width
Depth
Weight

SPECIFICATION
8.55 in. (217.2 mm)
2.28 in. (58.0 mm)
12.73 in. (323.0 mm)
7.7 Ib (3.5 Ib)

Operating Temperature Range
Relative Humidity Tolerance Range

20 to 80%

Power

+24 Vdc ±IO% 0.75 A (starting)
0.90 A (average)
+5 Vdc ±5% 0.8 A
-5 Vdc ±5% 0.07A

Power Consumption

28 W (maximum)

Error Rate
Recoverable
Non-Recoverable
Seeks

I per 10 12
I per 106

3.5.2

I per 109

Interface

Figure 3-13 shows the signal connector interface and pin assignments; Figure 3-14
illustrates the power connector interface and pin assignments.
3.5.3 Terminations and Jumper Settings
The location and installation of the termination resistor modules are shown in
Figure 3-15, and the jumper location and jumper setting are shown in Figure 3-16.

3-40

Controller PCB

AT STANDARD TTL LEVELS

8 in. FDD

50-PIN
SIGNAL
CONNECTOR

49

LOW CURRENT

47

FILE UNSAFE RESET

45

FILE UNSAFE

41

TWO SIDED

37

SIDE SELECT

33

HEAD LOAD

31

INDEX

-

29

READY

27

VFO SYNC

25

DRIVE SELECT A

23

DRIVE SELECT B

21

--

19

2

~
3

0

0

0

0

0

0

I

I

I

I

,

49

4

FDD
CONTROL

DRIVE SELECT C
DRIVE SELECT D

17

DIRECTION SELECT

15

STEP

13

WRITE DATA

II

WRITE GATE

9

TRACK 00

7

WRITE PROTECT

5

READ DATA

3

MFM

1

WINDOW

I

0

I

I

I

I

I

0

I

I

0

-"

2-50(EVEN) GROUND

50

Figure 3-13 FDD Signal Connector Interface and Pin Assignments
3-41

Controller PCB

FDD
CONNECTOR
171826-7
(AMP)

POWER CABLE
CONNECTOR
170204-1 (AMP)
AT STANDARD TTL LEVELS

r::I~~,----+-_- 7-PIN

13

POWER CONNECTOR

8 in. FDD

Figure 3-14 FDD Power Connector Interface and Pin Assignments

o

0
D 0
t t
TERMINATION RESISTOR MODULE
15000 661-3-R150

Figure 3-15 FDD Termination Resistor Modules, Location and Installation
3-42

1

DC +24 V

2

GND

3

DC+S V

4

GND

S

DC -S V

6

GND

7

FG

POWER
UNIT

Controller PCB

XG

2

4

~@
1

DRIVE B

3

DRIVE A

Figure 3-16 FDD Jumper, Location and Proper Setting
3.6 SERIAL 1/0 COMMUNICATIONS CONTROLLER
Supported by the 8251A USART controller, this communications interface circuit
is programmed by the CPU to operate using synchronous, asynchronous, or
business-machine serial-data-transmission techniques. Basically, the serial 110
device converts parallel data of the microprocessor into serial data and vice versa
and generates appropriate supervisory lines to interface with a modem or other
external peripheral devices.
3.6.1 Specifications
Table 3-18 lists the specifications for the Serial 110 Communications Controller.
3.6.2 Circuit Description
A functional block diagram of the serial 110 device is shown in Figure 3-17. Table
3-19 lists the serial 110 commands.
3.6.3 Interface
The serial 110 connects to the APC rear panel with a 26-pin cable connector,
designated CN3 on the Controller PCB. The other end of the 26-pin cable connects
to a 36-pin D-type connector similar to the printer connector. Table 3-20 lists and
Figure 3-18 shows the pin assignments of all the cables. Table 3-21 explains the interface signals.
3.6.4 Programming Considerations
Opera tion of the 8251 A processor is programmed by two 8-bit control words:
• A mode instruction word, which is the first word written into the 8251A
after reset
• A command instruction word, which defines the operation to be performed.

3-43

COnTrOller

reB

Table 3-18 Serial 1/0 Communications Controller Specifications

Characteristics
Processor
Channel
Transmission Mode
Synchronization
Interface
Line Speed
Asynchronous Mode
Synchronous Mode
Business Machine

3-44

Specifications
NEC 8251A
1
Half-Duplex or Full-Duplex
Synchronous or Asynchronous
EIA RS-232C
50 to 19.2K Baud
50 to 19.2K Baud
1200 Baud

Controller PCB

8251A
RXR
DB 0 TO 7

PROGRAM
CONTROL

l

WR
RD
C/D
CS
RST
RXD
CTS
DSR
RXC
TXC

TXR
TXE

TRANSMIT
DATA

TXD

~---.SD

RTS

'Xl.....----.. RS

DTR

ER

~---DR

....----CS
RECEIVE
DATA
J.--::.--- RD

BMC
RT

....----RT
1-----

ST2

CLOCK
GENERATOR
~----STI
CLKO----------~----~

BUSINESS
MACHINE
CLOCK
GENERATOR

cp----------'
Figure 3-17 Serial 1/0 Communications Controller Block Diagram
3-45

Table 3-19 Serial I/O Commands

COMMAND

Read Data

Write Data

I/O
ADDRESS

READ/
WRITE

30

R

30

W

7

6

DATA BUS
5 4 3 2

R
D
7

R
D
6

R
D
5

R
D

S
D
7

S
D
6

S
D
5

S
D

S

D
Read Status

32

R
D
3

R
D
2

R
D

S
D
2

S
D

4

S
D
3

F

0

P

T

E

E

E

E

R
R
D

4

Y

R
R

N

1

0

R
D
1 0
S
D
1 0
T
R
D

Y Y
P
E L2 L, B2 B,
N

Write Mode (A)

32

W

S2 S,

E
P

Write Mode (S)

32

W

S
C
S

E
S
D

E
P

Write Command

32

W

E
H

I
R

R
S

Write Mask

34

W

Tx Rx Tx
E R R

Read Signal

34

R

C
S

Write Signal

36

W

3-46

P
E L2 L,
N

R
S
T

S
B
R

R
E
N

0

0

E
R

T
E
N

C
I

C
D
T
D
C

Table 3-20 Serial 1/0 Connectors Pin Assignments

SIGNAL

PIN NUMBER
AT A

PIN NUMBER
ATB

Frame Ground
SO
RD
RS
CS
DR
Signal Ground
CD

1
2
3
4
5
6
7
8

1
2
3
4
5
6
7
8

1
3
5
7
9
11
13
15

9
10
11
12
13
14

9
10
11
12
13
19

17
19
21
23
25
2

15

20

4

16

21

6

17

22

8

18
19

23
24

10
12

20

25

14

21
22
23

26
27
28

16
18
20

24

29

22

25

30

24

ST2

RT

ER

STI

PIN NUMBER
ATC
REMARKS

No signal

No signal

No signal

No signal

No signal

3-47

Controller PCB

Table 3-21 Serial 110 Device Interface Connector Pin Descriptions
SIGNAL
SG
SD
RD
RS
CS
DR
SG
ST2(TxC)
RT
ER
STl(RxC)

SOURCE

DESCRIPTION

Controller
Modem
Controller
Modem
Modem

Signal ground
Send data
Receive data
Request to send
Clear to send
Data set ready

Modem
Modem
Controller
Controller

Transmit Clock
Receive Clock
Data Terminal Ready
Transmit Clock

-

The processor can also read a status word from the 8251 A, or write sync characters
(in the Synchronous Mode), or specify that the data bus is to be read from or written
to and transmitted to or received from (respectively) the modem. Instruction to the
8251A is determined by the levels on IC Pins 10, 11, 12, 13 and 21 (see Table 3-22).

3-48

25 23

CN3

00
1o

5 31

0001

0

0

0

0

PI? 7 I I I Z Z i I I II I Z Z Z I ? I Z I I Z ? ? Z 12 I ? I I I 2 II II I i I Z Z Z I ? I I I

C

26 24

~

6 42

G9PFCU PCB

PINS 14 TO 18 AND 32 TO 36 HAVE
NO CONNECTION.

36

MOUNTED ON THE REAR PANEL
(MARKED COMM).

19
B

25

19

2

1

14

A

CN3
G9PFCU

u-------.----uif~G
COMMUNICATIONS CABLE

INTERCONNECTING CABLE

Figure 3-18 Communications Controller Cable Connections
3-49

controller rClJ

Table 3-22 8251A Instructions

SYMBOL
--

WR

-

CS

NAME
WRITE

--

DESCRIPTION
A Low on this line indicates
that data on the bus is to be
written into the 8251A (APC
lOW line).

CHIP
SELECT

A Low on this line selects the
8251A, enabling read or write
operations. This line must be
Low for the 8251A to
respond to or affect the data
bus (APC SIO line).

CONTROLI
DATA

A High on this line specifies
that a control word is being
written in or that a status
word read out. A Low means
that data is being written in
or read out (APC AB line).

RD

READ

A Low on this line indicates
that the data or a status word
is being read from the 8251 A
(APC lOR line).

RST

RESET

A High on this line places the
8251A in an idle mode, waiting for a new set of control
words (A PC RST line).

-

CIO

-

3.6.4.1 ASYNCHRONOUS OPERATING MODE
The mode instruction word for asynchronous operation is shown in Figure 3-19.
The format of the command instructions word is shown in Figure 3-20. Figure 3-21
shows the setup of jumper settings and the resulting circuit. Table 3-23 shows how
the Baud rate is set.
3-50

Controller PCB

I S2 I SI I EP IPEN I L2 I L1 I B2 I BI I

I

BAUD RATE
IX 16X 64X

SYNC
MODE

CHARACTER LENGTH
BITS
7

o

PARITY ENABLE
I ~ ENABLE
o ~ DISABLE
PARITY
~ EVEN

I

O~ODD

Nl'MBER OF STOP BITS

X

o
o

tYl
0

Figure 3-19 Asynchronous Mode Instruction Word
DS

I

EH

I

IR

I

RTS

D2

I

ER

DO

I SBRK I R X E I DTR I T X EN I
I

TRANSMIT ENABLE
I ~ ENABLE
DISABLE

o~

DATA TERMI~AL
READY·HIGH WILL
FORCE DTR OUTPUT
LOW
RECEIVE ENABLE
I ~ ENABLE
o ~ DISABLE
SEND BREAK
CHARACTER

I

~

o~

FORCES T X D LOW
NORMAL OPERATION

ERROR RESET
I ~ RESET ALL ERROR
FLAGS (PE. OE. FE)
REQl'EST TO SEND
HIGH FORCES RTS
Ol'TPlT TO ZERO
I'ITER:-IAL RESET
HIGH RETURNS 8251 TO
MODE I"

o-!2

RD

BIT SYNC
CLOCK GEN

r-------~---. RTI

Figure 3-21 Communications Controller, Circuit for Asynchronous Operation
3-52

STl

Controller PCB

Table 3-23 Communications Controller, Baud Rate Coding
During Asynchronous Operation

BAUD RATE
19.2K

COUNT
RATE*

COUNT REGISTER
HIGH

COUNT REGISTER
LOW

15 14 13 12 11 10 9 8

7 6 5 4 3 2 1 0

o0

0

0

o0
o0
o0
o0
o0

0

0

0 0 1

0

0

0

0 1 0

0

0

0

0

0 1 1

o0
o0
o0

0

0

0

0

0

1 1 0

2048

0

0

0

0

1

0

3072

0

0

0

0

1

1

8

0

0

0

0

0

0

9600

16

0

0

0

0

0

0

4800

32

0

0

0

0

0

0

2400

64

0

0

0

0

0

0

1200

128

0

0

0

0

600

256

0

0

0

300

512

0

0

200

768

0

100

1536

75
50

001 000

000 1 0 000

o0
o1

100 0 0 0
000 0 0 0

1 0 000 0 0 0
000 0 0 0
000 0 0 0
0 0 0 0 0 0

135

*Count Rate

o0
o0

o0 o0 0
o 0 000
o 0 000

0 0 0
0 0 0
0 0 0

= 2457600/(RxC or TxC) x 16 (Hz)

3.6.4.2 SYNCHRONOUS OPERATING MODE
The mode instruction word for synchronous operation is shown by Figure 3-22.
Figures 3-23 and 3-24 show the circuits for synchronous operation using external
(Modem) and interval clocks, respectively. Table 3-24 lists the Baud rate setting
codes in synchronous operation.

3-53

Controller PCB

07

1>6

O'i

04

D3

Is(slfSDI ,:rIN:NI,21

I

D2

LI

DI

I0

DO

10

eHA RACTER LENGTH

I

BITS
5

I

0
0
PARITY ENABI.E
1 :: PIiABtE
0 = DISABLE

P ARITV
1 = EVEN
0=000
E XTERNAI. SYNC Dt:TE('T
1 :: SYNDEr IS AN INPl:r
0 :: SYNDEr IS AN Ol'TPlTT

SINGU: CHARACTER SYNC
I:: SIN(; LE CHARACTER
au: CHARACTER
0"

DOl'

Figure 3-22 Synchronous Mode Instruction Word

8251

RT

sn

T[

8253
161
~16

p

2.4576 MHz

TI~C~lFKO~______.-~CP

0"'-+----1 ")00-----1,

RD

BIT SYNC
CI.OCK GEN

STI

.. RTI

f----------.-4~----

Figure 3-23 Communications Controller, Circuit for Synchronous Operation Using External Clock
3-54

comrOller rcn

8251

O':;".....--~RXC

RT L-.-----,

TXC

STl

TE

8153
161
+16

p

2.4576 MHz

CLKO

TL ~~-+----....-f CP
1

TM4

;>O--C:J STI

RD

c:::::r--~

BIT SYNC
CLOCK GEN

r------~---~ RTI

Figure 3-24 Communications Controller, Circuit for Synchronous Operation Using Internal Clock
3-55

Controller PCB

Table 3-24 Communications Controller, Baud Rate Coding
During Synchronous Operation

COUNT REGISTER
HIGH

BAUD RATE

COUNT
RATE* 15 14 13 12 11 10 9 8

128

0

0

0

0

0

0

9600

256

0

0

0

0

0

0

4800

512

0

0

0

0

0

0 1 0

2400

1024

0

0

0

0

0

1

1200

2048

0

0

0

0

1 0

600

4096

0

0

0

1 0

300

8192

0

0

1 0

200

12288

0

0

1

100

18204

0

1 0

75

24756

0

1

*Count Rate = 2457600/Baud (Hz)

3-56

o0
o1

19.2K

0

o0
o0
o0
o0
o0

COUNT REGISTER
LOW

7 6 5 4 3 2 1 0
1 0 0 0 0 0 0 0

o0

0 0 000 0

000 0 0 0 1 0

o0
o0
o0
o0

0 0 0 000
0 0 0 000
0 0 0 0 0 0
0 0 0 0 0 0

0

0

1 0

0

0

0

1 1 1

000 1 1 1

1 0

0

0

o0

101 1 0 1

000 00000

o0
o0

Controller rClJ

3.6.4.3

BUSINESS MACHINE OPERATING MODE

Figure 3-25 shows the circuit and Table 3-25 lists the Baud rate setting codes when
operation with business-machine timing.

8251

RTD-~

o-__._---+j

RXC
TXC

ITM2

sn

TE

8253
161
+16
p

2.4576 MHz

CLKO
TI 1--;---\----...---1 CP

STI

RD

L--r_---,

BIT SYNC
CLOCK GEN

I---------.----~

RT1

Figure 3-25 Communications Controller, Circuit for Business Machine Clock
3-57

Controller PCB

Table 3-25 Communications Controller, Baud Rate Coding During
Operations with Business Machine Clocking

BAUD RATE

3-58

RATE

COUNT REGISTER
HIGH

COUNT REGISTER
LOW

15 14 13 12 11 10 9 8

7 6 5 4 3 210

o0
o0
o0
o0
o0
o1

00001 000

19.2K

8

0

0

0

0

0

0

9600

16

0

0

0

0

0

0

4800

32

0

0

0

0

0

0

2400

64

0

0

0

0

0

0

1200

128

0

0

0

0

0

0

600

256

0

0

0

0

0

0

300

512

0

0

0

0

0

0 1 0

o0
o0

200

768

0

0

0

0

0

0 1 1

000 0 0 0 0 0

135

1138

0

0

0

0

0

1

o0

011 100 1 0

100

1536

0

0

0

0

0

1 1 0

75

2048

0

0

0

0

1 0

50

3072

0

0

0

0

1

1

o0
o0

000 1 0 0 0 0

o0
o1

1 000 0 0
0 0 0 0 0 0

100 0 0 0 0 0

o0
o0
o0

0 0 0 0 0 0
0 0 0 0 0 0

0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0

Controller PCB

3.6.5

Status Word Format

The status word format is shown by Figure 3-26.

I

D7

D6

D5

DSR

ISYNDETI

FE

D4
I

OE

D3
I

PE

D2
I

TXE

Dl

DO

I TXRDY I RXRDY

I

SAME DEFINITIONS AS I/O PINS

PARITY ERROR
PE FLAG SET WHEN PARITY ERROR IS
DETECTED. DOES NOT INHIBIT OPERATION
OF 8251. RESET BY ER BIT OF
COMMAND INSTRUCTION.
'- OVERRUN ERROR
OE FLAG IS SET WHEN THE CPU DOES
NOT READ A CHARACTER BEFORE THE
NEXT ONE BECOMES AVAILABLE. IT
IS RESET BY ER BIT OF COMMAND
INSTRUCTION. DOES NOT INHIBIT
8251 OPERATION, BUT OVERRUN
CHARACTER IS LOST.
'-----FRAMING ERROR (ASYNC ONLY)
FE FLAG SET WHEN VALID STOP BIT
IS NOT DETECTED AT THE END OF EVERY
CHARACTER. DOES NOT INHIBIT 8251
OPERATION. FE IS RESET BY THE ER
BIT OF THE COMMAND INSTRUCTION.

Figure 3-26 Communications Controller, Status Word Format

3-59

Controller PCB

3.7 SOUND CONTROL
The sound control system is supported by the NEC pPD 1771 C-006, which drives a
loudspeaker through a Y4- Watt audio amplifier. This LSI generates audio signals
and programmable music. Through music programming, the sound control system
can generate tones ranging over two octaves in frequency, at specified note lengths,
intensities, and tempos.
A functional block diagram of the sound control system is shown in Figure 3-27.
The sound system speaker is mounted near the front of the main unit. An operator's
volume control is also provided.

f-1PDl771 C-006

DB 0 TO 7
1

CN6 (VOLUME INTERFACE
CONNECTOR)

IOWO---..... WR
IORO
RD
CS

CS

4 MHz - - -.... CLK

1
Figure 3-27 Sound Control Block Diagram

3-60

CN7 (SPEAKER INTERFACE
CONNECTOR)

~unlrUller r~D

3.7.1 Interface
Figure 3-28 shows the sound control interface with the Controller PCB, and Table
3-26 describes the pin assignments.

CONTROLLER (G9PFCU) PCB

CN6 CN7

VOLUME

Figure 3-28

Location of Sound Interface Connectors
Table 3-26

Sound Interface Pin Assignments

CONNECTOR
CN6
(Volume
Interface)

CN7
(Speaker
Interface)

PIN

SIGNAL

1

Volume In

2

Volume Out

3

Ground

4

Ground

1

SP+

2

SP3-61

Controller PCB

3.7.2 Programming Considerations
Tables 3-27, 3-28 and 3-29 give format and command information for soundprogramming users.
Table 3-27

Sound Programming Read/Write Format
READ/
WRITE

110
ADDRESS

Write Command

W

60

0 FS C5 C4 C3 C2 C 1 CO

Read Status

R

60

S7 S6 S5 S4 S3 S2 Sl SO

INSTRUCTION

7

6

DATA BUS
5 4 3 2

1

0

Legend:
FS
CO to C5
SO to S7

--

First (0) or Second (1) command identification
Sound Control and Scale commands
= Status information: if HEX value is 80, all the write commands are
accepted; if HEX value is 00, only the Beep command is accepted.

=

Table 3-28

Sound Control Commands

FIRST COMMAND

SECOND COMMAND

COMMAND

DATA BUS
7 65432 1 0

MUSIC EXPRESSION

DATA BUS
7 6 5 4 3 2 1 0

Music Notes

0 0 1 1 0 0 0 1

Volume

Illegal

0 1 0 0 0 0 0 0

Beep Notes

3-62

Piano

0 1 0 0 0 0 0 1

20 ms

0 0 1 1 1 OXX

Medium

0 1 0 0 0 0 1 0

6 minutes

0 0 1 1 1 lXX

Forte

0 1 0 0 0 0 1 1

710 Hz

0 0 1 1 1 X 0 0

1202 Hz

0 0 1 1 1 X 0 1

Slow (1.0 sec)

0 1 0 1 0 0 0 0

2038 Hz

0 0 1 1 1 Xl 0

Moderately
Slow (0.87 sec)

0 1 0 1 0 0 0 1

Tempo

Controller PCB

Table 3-28

Sound Control Commands (cont'd)

FIRST COMMAND

SECOND COMMAND

COMMAND

DATA BUS
7 6 5 4 3 2 1 0

3906 Hz

0 0 1 1 1 X 1 1

MUSIC EXPRESSION

DATA BUS
7 6 5 4 3 2 1 0

Moderately
Fast (0.56 sec)

0 1 0 1 0 0 1 0

Fast (0.38 sec)

o

1 0 1 0 0 1 1

Sharp Attack (Bell-like)

o

Illegal
Piano
Medium
Forte

1 1 0
0 1 1 0
0 1 1 0
0 1 1 0

0
0
0
0

0
0
0
0

0
0
1
1

0
1
0
1

0
0
0
0

0
0
0
0

0
0
1
1

0
1
0
1

Soft Attack (Piano-like)

o 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1

Illegal
Piano
Medium
Forte

Table 3-29

Sound Scale Commands

FIRST COMMAND (NOTE TONE)
COMMAND

DATA BUS
7 6 5 4 3 2 1 0

Illegal

0 0 0 0 0 0 0 0

C

0 0 0 0 0 0 0 1

C#

SECOND COMMAND (NOTE DURA nON)
DATA BUS
COMMAND

7 6 543 2 1 0

Moderately emphatic
rhythm

0 1 0 OXXXX

0 0 0 0 0 0 1 0

Emphatic rhythm

0 1 0 IXXXX

D

0 0 0 0 0 0 1 1

Note without point

0 1 OXOXXX

D#

0 0 0 0 0 1 0 0

Note with point

0 1 OXIXXX

E

0 0 0 0 0 1 0 1

F

0 0 0 0 0 1 1 0

(Except thirty-second
note

F#

0 0 0 0 0 1 1 1

G

0 0 0 0 1 0 0 0

G#

0 0 0 0 1 0 0 1

.r)

Whole note ( 0
Half note (

)

d)

Quarter note ( ~ )
Eighth note

(J)

0 1
0 1
0 1
0 1

oX
oX
oX
oX

X 0 0 0
X 0 0 1
X 0 1 0
X 0 1 1

3-63

Controller PCB

Table 3-29
FIRST COMMAND (NOTE TONE)

3-64

COMMAND

DATA BUS
7 6 5 4 3 2 1 0

A

0 0 0 0 1 0 1 0

A#

0 0 0 0 1 0 1 1

B

0 0 0 0 1 1 0 0

C

0 0 0 0 1 1 0 1

C#

0 0 0 0 I 1 1 0

D

0 0 0 0 1 1 1 1

D#

0 0 0 1 0 0 0 0

E

0 0 0 1 0 0 0 1

F

0 0 0 1 0 0 1 0

F#

0 0 0 I 0 0 1 1

G

0 0 0 I 0 1 0 0

G#

0 0 0 1 0 I 0 I

A

0 0 0 1 0 1 I 0

A#

0 0 0 I 0 I I 1

B

0 0 0 1 1 0 0 0

C

0 0 0 I 1 0 0 1

C#

0 0 0 1 1 0 1 0

D

0 0 0 I 1 0 I 1

D#

0 0 0 1 1 1 0 0

E

0 0 0 1 1 1 0 I

Illegal

0 0 0 I I 1 I 0
Through
0 0 I 0 1 1 I I

Rest

0 0 1 I 0 0 0 0

Illegal

0 0 1 I 0 0 0 1
Through
0 0 1 1 1 I I I

Sound Scale Commands (cont'd)
SECOND COMMAND (NOTE DURATION)
DATA BUS
7 6 543 2 1 0

COMMAND
Sixteenth note

(J)

Thirty-second note
Illegal
Illegal

0 1 0 XX 1 0 0

(I)

oX

X 1 0 1
0 1 0 XX 1 I 0
0 I o X X I I I
0 1

Controller PCB

3.8

JUMPER SETTINGS

Figure 3-29 shows the Controller PCB jumper settings, which adapt the system to
various communications situations and to either monochrome or color display.

D LO[;J

D LO[;J

D LOt;]

D

D

D

D

D

D

D

D

D

D

D

D

TMID

~~D
D
D ~~

D

TM20

I

D
,

TM20

TM6 TM5

1

D

~~
TM3

: :~

~17

SYNCHRONOUS
(TMI-I, TM2-2, TM4-2)

~17

I

TM3

I,

I1

,

1

roJOI
l!.l!I

DLO~

D
D

D
D

TMID

~·~D

D
D
,

TMID

~·~D

D
D

TM6 TM5

~I

TM3

, ![;i

::

,

TM20
TM6 TM5

[I~

I

TM3

: !~

DI)

nil

MONOCHROME D1SPLA Y
(TM3-2, TM5 SHORTED, TM6-1)

D
D

TM4

rr==11~

TM20

I

17
n

D

BUSINESS MACHINE
CLOCK
(TMI-2, TM2-1, TM4-1)

DLO~

D
D

~~

,

::

ASYNCHRONOUS
(TMI-3, TM2-1, TM4-2)

rr=i1~

Figure 3-29

~·~D
D TM20

TM6 TM5

TM3

: :~

r==i1w

~·~D

TM6 TM5

I

TMID

TMID

rr==11[;l;1

rr==11rn

~17

COLOR DISPLA Y
(TM3-1, TM5 OPEN, TM6-2)

Controller PCB Jumper Settings
3-65

Chapter 4

Power Supply
The dc power supply is a 100 W, 5-voltage level, switching regula tor providing the
following dc outputs. The power supply also provides a noise-filtered switched 115
V, 60 Hz output at 1.2 A, and a single-pole, single-throw power control switch
output for external power On/Off control.
• +5 Vdc ± 5% @ 9 A
• -5 V dc ± 5% @ 0.3 A
• + 12 Vdc ± 5% @ 0.3 A
• -12 Vdc ± 5% @ 0.25 A
• +24 Vdc ± 10%

@

1.8 A

The power supply furnishes all required power to APC components in the Keyboard and terminal cabinet and is located in a removable chassis module under the
CRT Display. The power On/Off Switch is an integral part of the power supply.
All dc outputs are regulated and have overcurrent and overvoltage protection.
Ripple voltage does not exceed 50 mV at any dc output except the 24 V output,
where the ripple voltage does not exceed 100 m V. Spike noise voltage is less than 250
m Von any output. If an overload or overvoltage condition exists on any of the dc
outputs, the unit automatically shuts down until the condition is corrected and the
power is recycled off and on. The power supply is designed for continuous operation at 100 W of dc output and 130 W of ac output. The ac output is 2.5 A maximum
at 104 to 132 V, 60 ± 0.5 Hz and is fused for 5.0 A.
The APC power supply incorporates a POF circuit that enables remote On/Off
switching of both ac and dc outputs. The POF character is 5B and its address is
AD08.
A functional block diagram of the power supply is shown by Figure 4-1, which also
shows additional specifications of the POF feature.

4-1

ruwer

~upply

The input and output cable connections to and from the power supply are shown in
Figure 4-2 and listed in Table 4-1.

FUSE
NOISE
FILTER

AciN

+24 V

-5 V

+12V

-\2 V

+5 V
PCOUn

7

RELAY CONTACTS
RATED AT 0.5 ... 1A
AT 125 Vac

SG
Ac 115 V
OUT
R

L....-----------~O__() POF IN

"
-+-.

LESS THAN

1......-

10 MS

POF~~
I

OUTPUTS

~OWER
ON

Figure 4-1 System Power Supply Block Diagram

4-2

J

•:
I

~

Dc/ac

POF

-.J

I

ENABLEDJ
OUTPUT
OFF

Power Supply

SW

,

1]-< \

PC OUT ,:-;,'
(CN3)

LJ

POWER SUPPLY
UNIT

8

1

~1~1)1
16

AC
OUT

9

TO/FROM
CARD CAGE BUS

TO
CRT

+SV (PINS 2,7)
+l2V (PIN 5)
-12V (PIN 3)
-5V (PIN 4)
SG (PINS 1,8)
POF(PIN 6)

TO
FAN

TO FDD A
TO FDD B
+5V (PIN 3)
-5V (PIN 5)
+24V (PIN 1)
SG (PINS 2,4,6)
FG (PIN 7)

Figure 4-2 Power Supply Interconnection Diagram

4-3

Power Supply

Table 4-1 Power Supply Pin Command Assignments
CN2
PIN
NUMBER

4-4

DESCRIPTION

CN2
PIN
NUMBER

DESCRIPTION

1

115 Vac

9

115 Vac

2

Ground

10

Ground

3

+ 12 Vdc

11

-12 Vdc

4

-5 Vdc

12

-5 Vdc

5

POF

13

+24 Vdc

6

+5 Vdc

14

Ground

7

+5 Vdc

15

+5 Vdc

8

Ground

16

Ground

Appendix A

Integrated Circuit Data Sheets
16-BIT MICROPROCESSOR *
DESCR I PTI ON

FEATURES

PIN CONFIGURATION

The IlPD8086 is a 16-bit microprocessor that has both 8-bit and 16-bit attributes. It
has a 16-bit wide physical path to memory for high performance. Its architecture
allows higher throughput than the 5 MHz IlPD8085A-2.

• Can Directly Address 1 Megabyte of Memory
•
•
•

Fourteen 16-Bit Registers with Symmetrical Operations
Bit, Byte, Word, and Block Operations
8- and 16-Bit Signed and Unsigned Arithmetic Operations in Binary or Decimal

•
•
•
•

Multiply and Divide Instructions
24 Operand Addressing Modes
Assembly Language Compatible with the IlPD8080/8085
Complete Family of Components for Design Flexibility

GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
ADO
NMI
INTR
eLK
GND

Vee
AD15
A16/S3
A17/S4
A18/S5
A19/S6
SHE/S7
MN/MJ(

AD
HOLD
HLDA

(RO/GTO)
(Ro/GT1)

WR

(COCi<)

M/iO
DTIR

(Si)

(Si)

BEN

(wi

ALE

(OSO)
(OS1)

iN'fA
TEST
READY
RESET

*Preliminary

Reprinted through courtesy of NEe Electronics, U.S.A., Inc.

NOTE: These manufacturer's specifications are provided for reference. The APC
may not use some of the functions described here.

AI-I

PIN IDENTIFICATION

NO.
2·16.39

17

FUNCTION

NAME

SYMBOL
AOO·ADIS

Address/Data 8us

Multiplexed address (Tl) and data (T2. T3. TW. T 4) bus.
8-bit peripherals tied to the lower 8 bits, use AO to condition
chip select functions. These lines are tri·state during interrupt
acknowledge and hold states.

NMI

Non-Maskable

This is an edge triggered input causmg a type 2 interrupt, P.
look-up table is used by the processor for vectoring
information.

Interrupt
18

INTR

Interrupt Request

A level triggered input sampled on the last clock evcle of
each instruction. Vectoring is vis an interrupt look-up table.
INTR can mask in software by resetting the interrupt enable
bit.

19

CLK

Clock

The clock input is 8 1/3 duty cycle input basic timing for the
processor and bus controller.

21

RESET

Reset

This active high signal must be high for 4 clock CYcles. When
it returns low, the processor restarts execution.

22

READY

Ready

An acknowledgement from memory or I/O that data will be
transferred. Synchronization is done by the IIPD8284 clock
generator.

23

TEST

Test

This input is examined by the "WAIT" instruction, and if
low, execution continues. Otherwise the processor waits in an
"Idle" state. Synchronized by the processor on the leading
edge of ClK.

24

iN'l'A

Interrupt
Acknowledge

This is 8 read strobe for reading vectoring information.
During T2. T3. and TW of each interrupt acknowledge
cycle it is low.

25

ALE

Address Latch Enable

This is used in conjunctton with the IIPD8282/8283 latches
to latch the address, during T 1 of any bus cycle.

26

DEN

Data Enable

This is the output enable for the IIPD8282/8287 transceivers.
It is active low during each memory and I/O access and
INTA cycles.

27

DT/R

Data Transmit/Receive

Used to control the direction of data flow through the
"an"",i. . ,,~

28

MilO

Memory/IO Status

This is used to separate memory access from I/O access.

29

WR

Write

Oepending on the state of the MilO line. the processor is
either writing to I/O or memory.

30

HlDA

Hold Acknowledge

A response to the HOLD input. causing the processor to
tri-state the local bus. The bus return active one evcle after
HO LD goes back low.

31

HOLD

Hold

When another device requests the local bus. driving HOLD
high. will cause the IIPo8086 to i$$Ue a H LOA.

32

RD

Reed

Depending on the state of the M/IO line. the processor is
reading from either memory or I/O.

33

MN/MX

Minimum/Maximum

This input is to tell the processor which mode it is to be used
in. This effects lOme of the pin descriptions.

34

~/S7

Bus/High Enable

This is used in conjunction with the most significant half of
the data bus. Peripheral devices on this half of the bus use
BHE to condition chtp
functions.

A16-A19

Most Significant
Address Bits

The four most significant address bits for memory operations. low during I/O operations.

S()'S7

Status Outputs

TheM are the status outputs from the processor. They are
u.:l by the "P08288 to generate bus control stgnals.

OS1. a SO

Que Status

Ulld to tr8Ck the Internal ",P08086 instrum:ton que.

LOCK

lock

This outPut is set by the "LOCK" instructton to prevent
other system bus masters from gaining control.

~~

Request/Grant

Other 10<:111 bus masters can force the processor to rebete
the local bus at the end of the current bus cycle.

_act

35-38

26.27.28
34~38

24,25

29
30.31

RQJGTI

AI-2

BLOCK DIAGRAM

EXECUTION UNIT
REGISTER FilE
DATA,
POINTER, AND
INDEX REGS
(SWORDS)

BUS INTERFACE UNIT

I REGISTER
RELOCATION
FilE
SEGMENT
REGISTERS
AND
INSTRUCTION
POINTER
(5 WORDS)

16-BIT AlU

FLAGS

BUS
INTERFACE
UNIT

DT/R, DEN, ALE

6-BYTE
INSTRUCTION
aUEUE

TEST
INT
NMI
aSa,as,

CONTROL & TIMING

RO/GTa,1
HOLD
HlDA

ClK

RESET READY MN/MX

GND
Vee

Al-3

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . oOe to 70 0e
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 65° e to +150° e
Voltage on Any Pin with Respect to Ground .
... ... ..
-1.0 to +7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5W

ABSOLUTE MAXIMUM
RATINGS*

Ta = 25°e
'COMMENT: Stress above those listed under" Absolute Maximym Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum ...ating conditions for extended periods may affect device

reliability.

Ta = O'C to 70'C; VCC = 5V ± 10%

PARAMETER

SYMBOL

MIN

LIMITS
MAX
+O.B

V

VCC + 0.5

V

0.45

V

10l = 2.5 mA

V

10H =-400pA

Input Low Voltage

VIL

-0.5

Input High Voltage

VIH

2.0

Output Low Voltage

VOL

Output High Voltage

VOH

Power Supply Current

ICC

2.4

pPDBOB6/
pPDBOB6·2

Al-4

TEST
CONDITIONS

UNITS

340
350

mA
mA

Ta =25'C

< VIN < VCG

Input leakage Current

III

±10

pA

OV

Output leakage Current

IlO

±10

pA

0.45V " VOUT'; VCC

Clock Input low Voltage

VCl

Clock Input High Voltage

VCH.

Capacitance of Input Buffer
(All input except
ADO-ADI5. RO/GT)
Capacitance of I/O Buffer
(ADO-ADI5. RO/GT)

-0.5

+0.6

V

VCC+l.0

V

GIN

15

pF

Ie = 1 MHz

CIO

15

pF

fc = 1 MHz

3.9

DC CHARACTERISTICS

!,PD8086: Ta

AC CHARACTERISTICS

=o°c to 70°C; VCC = 5V ± 10%

TIMING REQUIREMEN TS

MINIMUM COMPLEXITY
SYSTEM

",PDlDl8-2.rellmlneryJ

.u. PDl086
PARAMETER

SYMBOL

MIN

MAX

500

elK Cycle Period -IlPD8086

releL

200

elK Low Time

reLCH

(2/3 releL) -15

(1/3 TeleLI +2

MIN

MAX

125

500

(2/3 TCLCLJ-15

TCH1CH2

10

'0

elK Fat! Time

TCL2CL1

10

10

Data In Setup Time

TOVel

30

Oa1;a In Hold Time

TelDX

10

10

35

35

TR1VCL

20

0

0

,(j)@
(2/3 TeLeLl -15

READY Setup Time into ",P08086

TRYHCH

(2/3 TCLCLl-15

READY Hold 11me into IlP08086

TCHRYX

30

20

READY Inactive to elK

TRYlCL

-8

-8

THVCH

35

20

INTR, NMI, TeST Setup TIme

TtNVCH

30

'5

From 1.0V to 3.5V
From 3,5V to 1.0V

n."'
n.
n.

@
HOLD Setup Time

"'
"'

n."'
n.
n.
n.

(j)@
TCLR1X

"'

"'

TCHCL

ROY Hold Time Into J,.CPD8284

TEST
CONDITIONS

"'

(1/3 reLeLl +2

eLK Hlg" TIme

elK Rise Time

ROY Setup Time into ",PD8284

UNITS

@
Input AiseTlme

TILIH

20

eo

From O.BV to 2.0V

input Fall Time

TIHIL

'2

eo

From 2.0V to O.BV

UNITS

TEST
CONDITIONS

TIMING RESPONSES

TIMING RESPONSES

~PDB086

PARAMETER

SYMBOL

MAX

110

Address Valid Delay

TCLAV

10

Address Hold Time

TCLAX

10

Addre~

TCLAZ

TCLAX
TCLCH-20

Float Delay

~PD8086-2

MIN

(P11IIiminary)

MIN

MAX

10

60

10
80

ALE Width

TLHLL

ALE Active Delay

TCLLH

80

ALE Inactive Delay

TCHLL

85

Address Hold Time to ALE Inactive

TLLAX

TCHCL-10

Data Valid Delay

TCLDV

10

Dat8 Hold TIme

TCHDX

10

Data Hold Time After WR

TWHDX

TCLCH-30

TCLAX

50

TCLCH-1Q

50
55
TCHCL-l0

110

10

60

10
TCLCH-JO

Con'trol Active Delay 1

TCvCTV

10

110

10

70

Control Active Delay 2

TCHCTv

10

110

10

80

Control Active Otlay

TCvCTX

10

110

10

70

Address Flolt 10 READ Active

TAlRL

0

RD Active Delay

TCLRL

10

165

10

100

RD Inactive Delay

TCLFlH

10

150

10

80

RD Inactive to Next Add11l11 Active

TRHAv

TClCL-45

HLDA Valid Deily

TCLHAv

ROWldtt'!

TRLRH

2TCLCL 75

2TCLCL-50

WRWidth

TWLWH

2TCLCL-60

2TCLCl-40

Add11l" V.lld to ALE Low

TAVAL

TCLCH-60

Output RI$e Time

TOLOH

20

Output Fall Time

TOHOl

12

NOTES:

 ROY iI ........... thtendofT2.T3.Twto . . . . . . . ifTW
mechinM . . . . . . to be iMllrted.
@1c--.add... ilWllid~firwl .........

@
@

,NTA~.

Two 'NT A eye. . run beck-to-blJck. The _
.... ADOAto.. I . II
ftoetingdurineboth 'NTA cvcteL Cofth'Ol for poiftW . . . . .
it thown tor -=ond INTA cytM.
SiIMh .182M or 8281.,.1hown for ........ ..,.

 S1"", iNlet;' in . . . juIC prior to T....

At-to

ASYNCHRONOUS SIGNAL
RECOGNITION

elK
NMI

INTR

SIGNAL "':_ _ __

i'EsT
NOTE:

CD

Setup requirements for asynchronous signals only to guarantee recognition

at next elK.

BUS LOCK SIGNAL TIMING

REQUEST/GRANT SEQUENCE
TIMING*

NOTE:

CD

The coprocessor may not drive the buses outside the region shown without
risking contention.

*for Maximum Mode only

AI-II

HOLD/HOLD ACKNOWLEDGE
TIMING*

~

,elKevelE

elK

1~

HOLO~

TCLHAV

HLDA

~,------------~~----~

....

AD1S-ADo.
Al9fSe-A S3.

uv

~/S7.M/iO.

COPRoceSSOR

·H_ _ _-J '-_ _ _ _ _.... I-_ _ _ _ _-J

1-1_ _ _ _ _ _ _

DTJR'. WR. DEN

PACKAGE OUTLINE
IlPD80860

G

F

f - - - - - - - - - E -------~

Cerdip
ITEM

MILLIMETERS

INCHES

A
B
C
D
E

51.5 MAX
1.62 MAX
2.54 ± 0.1
0.5 ± 0.1
48.26 ± 0.1
1.02 MIN
3.2MIN
1.0MIN
3.5 MAX
4.5 MAX
15.24 TYP
14.93 TYP
0.25 ± 0.05

2.03 MAX
0.06 MAX
0.1 ± 0.004
0.02 ± 0.004
1.9 ± 0.004
0.04 MIN
0.13 MIN
0.04 MIN
0.14 MAX
0.18 MAX
0.6 TYP
0.59 TYP
0.01 ± 0.0019

F
G

H
I
J

K
L
M

Al . . 12

PROGRAMMABLE COMMUNICATION INTERFACES
DESCRIPTION

F EATU R ES

The J.1PD8251 and J.1PD8251A Universal Synchronous/Asynchronous Receiver/
Transmitters (USARTs) are designed for microcomputer systems data communications.
The USART is used as a peripheral and is programmed by the 8080A or other
processor to communicate in commonly used serial data transmission techniques includ·
ing IBM Bi·Sync. The USART receives serial data streams and converts them into
parallel data characters for the processor. While receiving serial data, the USART will
also accept data characters from the processor in parallel format, convert them to serial
format and transmit. The USART will signal the processor when it has completely
received or transmitted a character and requires service. Complete USART status
including data format errors and control signals such as TxE and SYNDET, is available
to the processor at any time.

• Asynchronous or Synchronous Operation
Asynchronous:
Five 8-Bit Characters
Clock Rate - 1, 16 or 64 x Baud Rate
Break Character Generation
Select 1, 1-1/2, or 2 Stop Bits
False Start Bit Detector
Automatic Break Detect and Handling (pPD8251A)
Synchronous:
Five 8-Bit Characters
Internal or External Character Synchronization
Automatic Sync Insertion
Single or Double Sync Characters
• Baud Rate (1X Mode) - DC to 56K Baud (J.1PD8251)
- DC to 64K Baud (J.1PD8251A)
• Full Duplex, Double Buffered Transmitter and Receiver
• Parity, Overrun and Framing Flags
• Fully Compatible with 8080A/8085/J.1PD780 (Z80TM)
• All Inputs and Outputs are TTL Compatible
• Single +5 Volt Supply, ± 10% (8251 A) ± 5% (8251)
• Separate Device Receive and Transmit TTL Clocks
• 28 Pin Plastic DIP Package
• N-Channel MOS Technology
PIN NAMES

PIN CONFIGURATION

0,

D.tI BUI (8 bin)

DO

R..t oeu Comnwnd

VCC

Writ. Oe'8

ContrOl Of Oeta is to

I'r.C
5TR

RTs
5SR
RESET

Of

cs

ChipE~.

ClK

Cklek Pul ..

be

Written or R.~

ContrOl Command

(TTL I

RESET

T.C
T.D

"xC

".0

T,.,..sminef Clock (TTLI

Tr.nsminer D~e
Receive, Clock (TTLI

RIIRDY

T_ROY

ClK

ho

DT"
$VNDeT

Sync Oetect

TxE

SVNOETIBD

Sync o-tectlBr.. k o.t.ct

ffi'

ATS
CTS

T.e

Regu •• to Send 0 ...
CInr to Send Oetll
T,.,smitt... Empty

GND

Ground

SVNOET (",P08251)

~!~~;T/BD (",P08251A) f-::V~CC~_+-;;+5:-:V:..::oI::.:'..:;"':::"'::.cY'--_ _ _ _ _ _-t
TM:

Z80 is a registered trademark of Zilog, Inc.

Reprinted through courtesy of NEC Electronics, U,S,A,. Inc.

NOTE: These manufacturer's specifications are provided for reference. The APC
may not use some of the functions described here.

A2-1

The pPDS251 and pPDS251A Universal Synchronous/Asynchronous Receiver/
Transmitters are designed specifically for SOSO microcomputer systems but work with
most S-bit processors_ Operation of the pPDS251 and pPDS251A, like other I/O devices
in the SOSO family, are ,.nogrammed by system software for maximum flexibility_

FUNCTIONAL
DESCRIPTION

In the receive mode, the !-,PDS251 or !-,PDS251A converts incoming serial format data
Into parallel data and makes certain format checks. In the transmit mode, it formats
parallel data into serial form. The device also supplies or removes characte~s or bits that
are unique to the communication format in use. By performing conversion and format·
tlng services automatically, the USART appears to the processor as a Simple or "trans·
parent" input or output of byte·oriented parallel data.
The !-,PDS251A IS an advanced design of the Industry standard S251 USART. It
operates With a wide range of microprocessors, inCluding the SOSO, SOS5, and
!-,PD 7S0 (ZSOTM I. The additional features and enhancements of the !-,PDS251 A over
the !-,PDS251 are listed below.
The data paths are double· buffered With separate I/O registers for control, status,
Data In and Data Out. This feature Simplifies control programming and min·
Imlzes processor overhead.
2. The Receiver detects and handles "break" automatically in asynchronous
operations, which relieves the processor of this task.
3

The Receiver is prevented from starting when In "break" state by a reftned Rx
initialization. This also prevents a disconnected USART from causing unwanted
Interrupts.

4 When a transmission IS concluded the TxD line will always return to the marking
state unless SBRK IS programmed.
5. The Tx Dlsahle command IS prevented from halting tra!lsmlSSlon by the Tx
Enable Logic enhance.llent, until all data previously written has been trans·
mltted. The same logic also prevents the transmitter from turning off In the mid·
die of a word.
6. Internal Sync Detect IS disabled when External Sync Detect IS programmed . .An
External Sync Detect Status IS prOVided through a fl,p·flop which clears Itself
upon a status read.
7. The pOSSibility of a false sync detect IS minimized by
- ensuring that If a double sync character IS programmed, the characters be
contiguously detected.
-

clearing the Rx register to all LogiC 1s (VOHI whenever the Enter Hunt com·
mand IS issued in Sync mode.

S. The RD and WR do not affect the Internal operation of the deVice as long as the
!-,PDS251 A IS not .selected
9. The !-,PDS251A Status can be read at any time, however, the status update will
be Inhibited dUring status read.
10. The pPDS251A has enhanced AC and DC characterrstlcs and IS free from
extraneous glitChes, prOViding higher speed and Improved operating margins
11. Baud rate from DC to 64K.

A2-2

pPD8251A FEATURES AND

ENHANCEMENTS

BASIC OPERATION

c/o

RD

WR

CS

0
0
1
1
X
X

0
1
0
1
X
1

1
0
1
0
X
1

0
0
0
0
1
0

TM.

/.IPD8251//.IPD8251A - Data Bus
Data Bus - /.IPD8251//.IPD8251A
Status - Data Bus
Data Bus - Control
Data Bus - 3·St?te

Z80 is a registered trademark of Zilog, Inc.

BLOCK DIAGRAM
TRANSMIT

hO

RESET
eLK

C'D

AD
WA

T~RDY

hE

he

cTs
RTs

SVNDET (uPD8251l
SYNDET/BD (~PD8251A)

ABSOLUTE MAXIMUM
RATINGS'

Operating Temperature . . . . . .
Storage Temperature . . . . . . .
Ali Output Voltages .. .
All Input Voltages..
Supply Voltages

. . . - 0° C to + 70° C
_65°C to +150°C
-0.5 to +7 Volts
-0.5 to +7 Volts
-0.5 to +7 Volts

Ta = 25°C
·COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device

reliability.

A2-3

DC CHARACTERISTICS

Ta = oOe to 70'e; vee = 5.0V ± 10% for 8251A and ± 5% for 8251; GND = OV.
LIMITS
PD8251
PARAMETER

SYMBOL

MIN TYP

Input Low Voltage

VIL

-0.5

Input High Voltage

vlH

2.0

Ou tpu 1 Low Vol tage

Val

Output High Voltage

Data Bus Leakage
Input Load Current
Power Supply Current

VOH

MIN

MAX

O.B

0.5

O.B

Vee

2.2 vee

0.45

0.45

UNIT

TEST CONDITIONS

V
V
V

"PD8251

2.4

2.4

V

"PDB251

III

Input Capacitance

1110 Capacitance

A2-4

SYMBOL

IOH = -10C"A

"POB251A IOH = -40G"A

45

-50

-10

10

10

10

10

BO

100

VOUT = 0.45V
"A

VOUT = VCC
At 5.SV

"A
mA

"PDB251A All OutputS =
Logic 1

LIMITS
PARAMETER

IOL=1.7mA

"PDB251 A IOL = 2.2 mA

IDl

ICC

.. PD8251A

MAX

TEST
CONDITIONS

MAX

UNIT

elN

10

pF

tc

el/O

20

pF

Unmeasured
pins returned
to GND

MIN

TY'

= 1 MHz

CAPACITANCE

AC CHARACTERISTICS

Ta

O'Cw70'C VCC~50V: 10% lor 81S1A GND~OV Vee-SOY' 5'\,10,8251

LIMITS
PARAMETER

Add'en Stabl!' betotl'

l=iEAD

SYMBOL

r

MIN

T

MAX

.... PD821SA,

I

MIN

I

MAX

I

UNIT

TEST
CONDITIONS

READ

m,

,~

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Figure 1.

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C'OC_ Pulse W'dl" H'9"

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Cloc~

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RecE""E" InOul Clock
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16)( Baud Rolle
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Dt'la~ "0"'"

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TEST LOAD CIRCUIT

56
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A2-5

TIMING WAVEFORMS
CLOCK

SYSTEM CLOCK INPUT
TPW

:""'00" ~
~~
_

T~C 116~

nsTruC!S the USART
to place the data Or status ,nformation
onlO the Data Bu) tor the prOCeSSOr 10
read

12

C/D

ContrOI·Dola

I
I

10

I

accept or prOVide elth+.:!r a data charaClpr.
control word or status ,nformatlon Via the
Data Bus. 0 - Data. 1
Conlrol

I
11

CS

Chip Selecl

Modem Cant rol

l

'"' ~o"-" 0." ,""' , , , " , , " , , , " 0 . , , "
WR and RD Inputs. ,nfo,ms the USART

-1

'J

I

A "zero" on thiS Inpu! enables the uSART to
read from or wrlle to the proceSSOr
The ..... PD8251 and J,.IPD8251 A have 0 set of
control Inputs and outouts which m·ay be used to
Simplify the Interlace to a Modem

22

DSR

Data Set Ready

The Data Set Ready Input can hI' tested by the
processor via StalUs information The DSR Input
IS normally used to test Modem Dala Set Ready
condition

24

DTR

Data Terminal Ready

The Data Terminal Ready output c~n be con
trOlled vIa the Command word The 0fR output
IS normally used to drive Modem Data Terminal
Ready or Rate $elect hnes

23

RTS

Request to $end

The Request to Send output can be controlled
via the Command word The RTS output IS
normally used to dr Ive the Modem Request to
Send line

17

CTS

Clear to Send

A ··zero·· on the Clear to Send mput enables the
USART to transmIT serial data Ii the TxEN bit In
the Command Instruction register IS enabled
(one)

A2-9

The Transmit Buffer receives parallel data from the Data Bus Buffer via the internal
data bus, converts parallel to serial data, inserts the necessary characters or bits needed
for the programmed communication format and outputs composite serial data on the
TxD pin.

PIN IDENTIFICATION

PIN
No.1 SYMBOL

TxRDY

(CONT.)

FUNCTION

NAME

The Transmit Control Logic accepts and outputs
all external and internal signals necessary for
serial data transmission.
Transmitter Read'" signals the processor that the
transmitter IS ready to accept a data character.
TxADY can be used as an interrupt or may be

Transmit Control Logic

15

TRANSMIT BUFFER

Transmitter Ready

tested through the Status information for polled
operation. Loadinga character from the processor
automatically resets TxROY. on the leading edge.

18

TxE

Transmitter Empty

The Transmitter Empty output signals the
processor that the USART has no further char-

acters to transmit. TxE

IS

automatically reset

upon receiving a data character from the pro·
cessor, In half·duplex, TxE can be used to signal
end of a transmission and request the processor
to "turn the Ime around," The TxEn bit in the
command instruction does nOt effect TxE,
In the Synchronous mode, a "one" on this output Indicates that a Sync character or charac·
ters are about to be automatically transmitted
as "fillers" because the next data character has
not been loaded.

9

TxC

Transmitter Clock

The Transmitter Clock controls the serial charac
ter transmission rate. In the Asynchronous
mode, the TxC frequency is a multiple of the
actual Baud Rate. Two bitS of the Mode Instruc·
tion select the multiple to be 1x, 16x, or 64)(
!!!!..,Baud Rate. In the Synchronous mode, the
TxC frequency is automatically selected to
equal the actual ~aud Rate.
Note that for both Synchronous and Asvnchronous modes, serial data is shifted out of the
USART by lhe falling edge of TXC.

19

TxD

The Transmit Control LogiC outputs the
composite senal data stream on this pin.

Transmitter Data

\

\

ADDRESS BUS
AO

\

\

CONTROL BUS
IIOR

~

1'0 VV

RESET

<>2
(TTL!

\

DATA BUS

/').
8

V
C/O

CS

D7 - DO

RD

,.PD825118251 A

A2-10

VVR

RESET

ClK

J.lPD8251 AND J.lPD8251A
INTERFACE TO 8080
STANDARD SYSTEM BUS

RECEIVE BUFFER

The Receive Buffer accepts serial data input at the RxD pin and converts the data
from serial to parallel format, Bits or characters required for the specific communication technique In use are checked and then an eight-bit "assembled" character is
readied for the procesc:.or. For communication techniques which require less than
eight bits. the I1 PD8251 and I1PD8251 A set the extra bits to "zero,"

PIN IDENTIFICATION
(CONT)

PIN
NO.

I

SYMBOL_1

Receiver ContrOl Logic

14

FUNCTION

NAME

RxAOY

ReC€II.1er Ready

ThiS ulock manages all activities related to
mcomlng dald

The Receiver Ready output Indicate .. thaI the
Receiver Buffet IS leildv With an "assembled"

For Polled
operation, the proceSSOr can check RxRDY
Read 01 AxROY can he con

ChiHJCler for InpuT to the prOCeSSOr

uSlng.l StdluS

rlPcted to thE"

ptOCf'S~OI

rntellupt structure

\Jole lh,J1 If',Jr!lnQ the ch,p.l[!@r 10 the pro
ce~sol dU!{)ITI;tlIC,llly 1l'~t'lS

ReCt:'lvE'r ClOCk

R"ROl'

Tlw Rt'celver C10l.:k dl'TPtlT1rrlf'S the rate at which
thl' If1COtn,nq chardctt'l 15 rpCt.'IVt'(l In Iht' Asyn
chrOrlOllS rnot!.'. tht! R-;C In'llUerlfy rndy 1)1' 1 16
01

64 tl!llt''> th" d(IUdl B.llHI Rdte hut II' th,' Svn

Ulionou:. modI' th., Rxe frl'qlH.'IlCIr' must ,'qll,11

tht' B,IUd Ral.'

T~\Io 1>11\ III Ih.· Ill()(h'

l1<;fruc.:I'Orl

~t'lt'C1 AsvnchIO!lOU~

oJt lx, 16 .. ur 64 .. or S..,n
Olll'Llt.on ,II 111 Th.· Baud R,ltt'

C~1ron()1,1',111\

lhe Rec.:I'I\t!. Co'rHlol logiC

16

SYNDET

Sync Orlec!

I .... P08251I

(JI\

IS rt>O'lvt>d hv
ThiS pill

Thl' SYNC DPlf'(1 pm I~ onl.., uc.ed ,n Ttl+'
Svll(hlon()u~ mu(h.' The ... P082S1 Illd.., he p,u
q._,mmed Ih'ough Ih~' Modf' In~I'uClI()1\ III
opf'r.I!l' In l'lttle, ThF' In\t-rll.!1 tI. ell.lt>'Il,,1 Sync
mode .rnci SYNDET Then lunctlons,IS .In Outpul
or ,npul reSpecllvely In Ihe rnl.,.rn,,1 Sync nlo(l ..
lh.,. SYNDE T oulpul .\rll go 10 d "on(>" \'\hl'll
Iht> .... PD8251 h.l~ luCrler! Iht' SYNC Ch,tI,H;IPI
rll tilt' Rt>cerIH' mode II (jouillp SYNC
ChtirilC'''' Ibl sync) Oper,lllon h,IS 111.'('1\ D'U
gl,lmmed, SYN~E T ~.... !l1 go 10 "ant" In ttl+'
mldd:e at the IdSt brt of the second SYNC
ChiJlClClel SYNOE T I~ automatlC.llly 'esPt to
"zero" upon tI St.IIUS At-.ldol AESET In ,Ilt'
e:to: te' n .... 1 SYNC mf)cle," "le'o" 10 "one" Ir,I"O;I
lion un Ihe SYNDET Inpul ..vdl c.luse The

I-IPD8251 10

~i1,I" dssem!)ling ddld ch.II"CI(,"

on the nell 1 failing edge of ~ The length of

the SYNOET rnput should be elt ledst one A'II.C
period, but m,IY be removed once the
j.lPD8251 IS Ir"! SYNC
16

SYNDET

80

(.uP08251 A I

Sync Detect
Break Oetl'ct

The SYNDET/BD pm IS used In both Synchronous and Asynchronous modes. When In SYNC
mode the features for the SYNDET pin

descnbed above apply. When in Asynchronous mode, the Break Detect output will go
high which all zero word of the programmed
length is received. This word consists of: start

bit, data bit, parity bit and one stop bit. Reset
only occurs when Rx data returns to a logic

one state or upon chip reset. The state of
Break Detect can be read as a status bit.
NO'e

(j)

SInce the ,uP08251 and ,uPD8251A wrll freQuently be handling both the reception and
transmlSSron for a grven link. the Recerve and Transmit Baud Rates will be same. RxC
and TxC then reQuue the same frequency and may be tied together and connected to
a SIngle clock source or Baud Rate Generator.

Examples

If the Baud Rate equals 110 IAsync)

TxC

AxC or
equals 110 Hz (lx)
AxC or TxC eQuals 1.16 KHz (16xl
~ or i'XC equals 7,04 KHz (64xl

If the Baud Rate eQuals 300
RxC or TxC equals 200 Hz (hi A or S
RxC or TxC equals 4800 Hz 116xl A only
RiC or TxC equals 19.2 KHz 164x) A only

A2-11

A set of control words must be sent to the J.1PD8251 and J.1PD8251A to define the
desired mode and communications format. The control words will specify the BAUD
rate factor (1 x, 16x, 64x), character length (5 to 8). number of STOP bits (1, 1·1/2,
2) Asynchronous or Synchronous mode, SYNDET (IN or OUT), parity, etc.

OPERATIONAL
DESCRIPTION

After receiving the control words, the J.1PD8251 and J.1PD8251A are ready to communicate. TxRDY is raised to signal the processor that the USART is ready to receive a
character for transmission. When the processor writes a character to the USART,
TxRDY is automatically reset.
Concurrently, the J.1PD8251 and J.1PD8251A may receive serial data; and after
receiving an entire character, the RxRDY output is raised to indicate a completed
character is ready for the processor. The processor fetch will automatically reset
RxRDY.
Note:

The J.1PD8251 and /.1PD8251A may provide faulty RxRDY for the first read
after power-on or for the first read after receive is re-enabled by a command
instruction (RxE). A dummy read is recommended to clear faulty RxRDY.
But this is not the case for the first read after hardware or software reset
after the device operation has once been established.
The /.1PD8251 and J.1PD8251A cannot transmit until the TxEN (Transmitter
Enable) bit has been set by a Command Instruction and until the CTS (Clear
to Send) input is a "zero", TxD is held in the "marking" state after Reset
awaiting new control words.

The USART must be loaded with a group of two to four control words provided by
the processor before data reception and transmission can begin. A RESET (internal or
external 1 must immediately proceed the control words which are used to program the
complete operational description of the communications interface. If an external
RESET is not available, three successive 00 Hex or two successive 80 Hex command
instructions (c/5 = 11 followed by a software reset command instruction (40 Hexl
can be used to initialize the /.1PD8251 and /.1PD8251A.

USART P ROG RAMM I NG

There are two control word formats:
1. Mode Instruction
2. Command Instruction

This control word specifies the general characteristics of the interface regarding the
Synchronous or Asynchronous mode, BAUD rate factor, character length, parity, and
number of stop bits. Once the Mode Instruction has been received, SYNC characters
or Command Instructions may be inserted depending on the Mode Instruction content.

A2-12

MODE INSTRUCTION

COMMAND I NSTRUCTION

This control word will be interpreted as a SYNC character definition if immediately
preceded by a Mode Instruction which specified a Synchronous format. After the
SYNC character(s) are specified or after an Asynchronous Mode Instruction, all sub·
sequent control words will be interpreted as an update to the Command Instruction.
Command Instruction updates may occur at any time during the data block. To
modify the Mode Instruction, a bit may be set in the Command Instruction which
causes an internal Reset which allows a new Mode Instruction to be accepted.

TYPICAL DATA BLOCK

B

MODE INSTRUCTION

C (5

SYNC CHARACTER 1

C

B

SYNC CHARACTER 2

C

B

COMMAND INSTRUCTION

C

B a

C

}

C D

NOTE

CD

Th~

secono

ONLY

CD

D ATA

COMMAND INSTRUCTION

C

B a

C

B

SYNC

SYNC MODE

DATA

COMMAND INSTRUCTION

charactt'l IS sk.lpprd If

MODE

YJammed the .u PD8251 and .u P08251A to

Slf1QJp

InstruCTion hilS pro

charactf'r

SYNC Moo!' 80th SYNC characters art' sk.lpper! ,/ MODE
instruction has programmeci the .u P D8251 and ,uPD8251A

tnlern.ll

\0

ASYNC

marie

MODE INSTRUCTION
DEFINITION

The IlPD8251 and IlPD8251A can operate In either Asynchronous or Synchronous
communication modes. Understanding how the Mode Instruction controls the
functional oiJerat,on of the USART IS easiest when the deVice is conSidered to be two
separate components (one asynchronous and the other synchronous) which share the
same support circuits and package. Although the format defll1ltlon can be changed at
will or "on the fly," the tw'J modes will be explained separately for clarity.

ASYNCHRONOUS
TRANSMISSION

When a data character is written Into the IlPD8251 and IlPD8251A. the USART
automatically· acids a START bit (low level or "space") and the number of STOP bits
(high level or "mark") specified by the Mode Instruction. If Parity has been enabled,
an odd or even Parity bit is inserted just before the STOP bit(s), as specified by the
Mode Instruction. Then. depending on CTS and TxEN, the character may be trans·
mitted as a serial data stream at the TxD output. Data is shifted out by the falling
edge of TxC at TxC. TxC/16 or TxC/64, as defined by the Mode Instruction.
If no data characters have been loaded II1tO the IlPD8251 and IlPD8251A. or if all
available charact~rs hilVe been transmitted, the TxD output remains "high" (marking)
In preparation for sending the START bit of the next character provided by the
processor. TxD may be forced to send a BR EAK (continuously low) by setting the cor·
rect bit in the Command Instruction.

A2,.13

ASYI'JCH RONOUS
RECEIVE

The RxD input line is normally held "high" (marking) by the transmitting device.
A falling edge at RxD signals the possible beginning of a START bit and a new
character. The START bit is checked by testing for a "low" at its nominal center
as specified by the B4UD RATE. If a "low" is detected again, it is considered valid,
and the bit assembling counter starts counting, The bit counter locates the approxi·
mate center of the data, parity (if specified), and STOP bits. The parity error flag (PE)
is set, if a parity error occurs. Input bits are sampled at the R xD pin with the rising
edge of RxC. If a high is not detected for the STOP uit, which normally signals the end
of an input character, a framing error (FE) will be set. After a valid STOP bit, the input
character is loaded into the parallel Data Bus Buffer of the /JPD8251 and /JPD8251 A
and the RxRDY signal is raised to indicate to the processor that a character is ready to
be fetched, If the processor has failed to fetch the previbus character, the new charac·
ter replaces the old and the overrun flag (OEI is set. All the error flags can be reset
by setting a bit in the Command Instruction. Error flag conditions will not stop sub·
sequent USART operation.

l

52

J

5,

II
EP

PEN 1 L21

I

L,

B21Bl

I

L

BA UD RA TE FACTOR

0

1

0

1

0

0

1

,

11 XI

116XI

164XI

SYNC
MODE

CHARACTER LENGTH

0

1

0

0

0

1

5

6
BITS

)

BITS

PARITY ENABLE
1 ENABLE
0

BITS

1
1
B
BITS

DISABLE

EVEN PARITY GENERATION/CHEC K
1 EvEN
0 ODD

NUMBER OF STOP BITS

..

0

1

0

0

0

,

1

BIT

1
BITS

2
BITS

INVALID

TItD

,

1

ST~

MARKING

BITS

L

TRANSMITTER OUTPUT
00

0,

t t

R.D

START

BIT

I

DA T

02

~

)-BI_T_S_.l-_ _ _..J

RECEIVER INPUT

A2-14

STOt;-]
BITS

L

PROCESSOR BYTE 15-8 BITS/CHARI

DATA

C~~RACTER

ASSEMBLED SERIAL DATA OUTPUT IhDI

~S_T_:_I~_T~

D_A_T_A~CH~A_R_'A_C_T_E_R ~

_____

____

______

~ ~-4~~~
__

TRANSMISSION FORMAT
SERIAL DATA INPUT IR,D)

~ ~~
____

C_H~ARrAC_T_E_R ~

___D_A_T_A
__

____

______

PROCESSOR BYTE 15-8 BITS/CHAR)

~ ~~~~
___

G>

I, I
DATA CH;;ACTER

RECEIVE FORMAT
N011:1S

I

~
2
3

Generated by .uP08251/82;Jl A
Does not appear on the Data Bus.
If charaCter length IS defined as 5, 6, or 7 bits. the

unused bits are set to "zero,"

SYNCHRONOUS
TRANSMISSION

As in Asynchronous transmission, the TxD output remains "high" (marking)
until the ;.tPD8251 and ;.tPD8251 A receive the first character (usually a SYNC
character) from the processor. After a Command Instruction has set TxEN and
after Clear to Send (CTS) goes low, the first character is serially transmitted.
Data is shifted out on the falling edge of TxC and the same rate as TxC.
Once transmission has started, Synchronous Mode format requires that the serial data
stream at TxD continue at the TxC rate or SYNC will be lost. If a data character IS
not provided by the processor before the ;.tPD8251 and ;.tPD8251A Transmit
8uffer becomes empty, the SYNC character!s) loaded directly following the Mode
Instruction will be automatically inserted in the TxD data stream. The SYNC
character(s) are inserted to fill the line and maintain synchronization until new data
characters are available for transmission. If the f./PD8251 and f./PD8251A become
empty, and must send the SYNC character(s}, the TxEMPTY output IS raised to signal
the processor that the Transmitter 8uffer IS empty and SYNC characters are being
transmitted. TxEMPTY is automatically reset by the next character from the processor.

SYNCHRONOUS
RECEIVE

In Synchronous Receive, character synchronization can be either external or Internal.
If the internal SYNC mode has been selected, and the Enter HUNT (EH) bit
has been set by a Command Instruction, the receiver goes Into the HUNT mode.
Incoming data on the RxD Input IS sampled on the "Sing edge of RxC, and the
Reeeive 8uffer is compared with the first SYNC character after each bit has been
loaded until a match IS found. If two SYNC characters have been programmed, the
next received character IS also compared. When the SYNC character(s) programmed
have been detected, the f./PD8251 and ;.tPD8251A leave the HUNT mode and are In char·
acter synchronization. At this time, the SYNDET (output I I.S set high. SYNDET IS
automatically reset by a STATUS READ.

A2-15

If external SYNC has been specified In the Mode Instruction, a "one" applied
to the SYNDET (Input) for at least one RxC cycle will synchronize the USART.
Parity and Overrun Errors are treated the same In the Synchronous as In the
Asynchronous Mode, If not in HUNT, parity will continue to be checked even
if the receiver is not enabled. Framing errors do not apply In the Synchronous
format,
The processor may command the receiver to enter the HUNT mode with a Command
Instruction which sets Enter HUNT (EH),f synchronizatIOn IS lost.

Iscs I I I I ': I 1,1 ' I
I
I
I I
fSO

E'

'f'

MODE INSTRUCTION
FORMAT
SYNCHRONOUS MODE

I

1 ·"H-l.l

1 ~ HIE "', T H
'I

"

i

I
' - - - - - - - -__

I'

(I

"
BITS

b

T

I:\ITS

81T",

PARITY

L._ _ _ _ _ _ _ _ _ _
•

I
I

I

"

BITS

E'~AAlE

I

EII,jABlE I

'0

ll'SABl f

1

EIIE;NPARITY GEII,jERATIO'\l CHECK

,

EVEI\j

o

ODD

L._ _ _ _ _ _ _ _ _ _ _ EXTERNAL SYNC DETECT
1

o

SYNDET IS AN INPUT
SYNDEr IS AN OUTPUT

L ._ _ _ _ _ _ _ _ _ _ _ _ _ <;INGLE CHARACTER SYNC

1

o

SINGl E SYNC CHARACTER
DOUBt E SYNC CHARACTER

PROCESSOR BYTES I~O BITS CHARI

flAT ACH:\:RACHf1<;
,\SSE~,1Rl

ED SERIAL

SYNC

SYNC

CHAR 1

CHAR .'

Oi~,T,\

OlJTPtJT IT,()\

nA 1 '\

CH~R:~\_C_T_E_f_"___--,

TRANSMIT FORMAT
St:HIAl l)ATli. INPUT II,d"))

DA r.:'l. CH'\H:..\_'_:T_l_'_"___-'
PROCESSOR BYTES '5 R 81TS CHAR'

(i)

RECEIVE FORMAT
NOll'

CD

II chelr,lelt"
lllt, ,lr"

A',2-16

Ipnqth

<;','l 10

'~(it'I"wd ,1,5 G

'lPr 0

Or 7 h'I"

1'1,' unu<;"d

TRANSMIT/RECEIVE
FORMAT
SYNCHRONOUS MODE

COMMAND INSTRUCTION
FORMAT

After the functional definition of the IlPD8251 and IlPD8251A has been specified by
the Mode Instruction and the SYNC character(s) have been entered (if in SYNC mode),
the USART is ready to receive Command Instructions and begin communication. A
Command Instruction is used to control the specific operation of the format selected
by the Mode Instruction. Enable Transmit, Enable Receive, Error Reset and Modem
Controls are controlled by the Command Instruction.
After the Mode Instruction and the SYNC character(s) (as needed) are loaded, all
subsequent "control writes" (C/O = 1) will load or overwrite the Command Instruction
register. A Reset operation (Internal via CMD IR or external via the RESET Input)
will cause the IlPD8251 and IlPD8251A to interpret the next "control write", which
must Immediately follow the reset, as a Mode Instruction.

STATUS READ FORMAT

It is frequently necessary for the processor to examine the status of an active
Interface deVice to deter'1'ine if errors have occurred or if there are other conditions
which require a response from the processor. The IlPD8251 and IlPD8251 A have
features which allow the processor to read the device status at any time. A data fetch
is issued by the processor while holding the C/O input "high" to obtain device Status
Information. Many of the bits in the status register are copies of external pins. This
dual status arrangement allows the IlPD8251 and IlPD8251 A to be used in both Polled
and interrupt driven environments. Status update can have a maximum delay of 16
clock periods in the IlPD8251 and 28 clock periods in the IlPD8251 A.

PARITY ERROR

When a parity error is detected, the PE flag is set, It is cleared by setting the
ER bit in a subsequent Command Instruction, PE being set does not inhibit USART
operation.

OVERRUN ERROR

FRAMING ERROR

CD

If the processor fails to read a data character before the one following is available,
the OE flag is set, It is cleared by setting the E R bit in a subsequent Command
Instruction. Although OE being set does not inhibit USART operation, the
previously received character is overwritten and lost.
If a valid STOP bit IS not detected at the end of a character, the FE flag is set, It
is cleared by setting the E R bit in a subsequent Command Instruction. FE being set
does not inhibit USART operation.
Note

CD

ASYNC mode only.

A2-17

COMMAND INSTRUCTION
FORMAT

STATUS READ FORMAT

0)

l
T~ANSMIT

OSR

ENABLE

1 ' enable
d's.ble

o~

lSY~~ET I

I

FE

l 1

OE

0,

0,

T.E

R.ROY

I

I

I I I IL
PE

hROY

SAME DEFINITIONS AS 110 PINS

PARITY ERROR

DATA TERMINAL

let when a p.r".,.
11 ,S 'est't bv
the fA b" 01 the Command
InSTruct,on PE does nOI ..,t-I,b,!
ope_.t,on 01 the J,lPD8151 and
JjPD8151A

The PE lIag.,

error ., detect.d

output

10

lero

RECEIVE ENABLE
1 " enable

o 'dISable
OVERRUN ERROR

The DE Ilag os sel when

-

SEND BREAK

CHARACTER
I
IO'Cl'$ T"O low"
OPe.allon

o " normal

does nOI

f~ad

'''e CPU

a character btfOfe

the nelll one ~come, avaIlable
1\'$ re'!'1 bv the fR b" 01 the

Command 'nll.uel,on OE dMS
not ,ntub,t OPe,at,on 01 tne ~P08251
and ..,P08251 A, but, tne p,e,
llIOUIly ov~rrun cha,aet~. II loll

ERROR RESET
1 - reset all !'''O' ""9'
PE.OE.FE

FRAMING ERROR lAsvnc onlyl
Tne FE lIa9 " Nt wh.n • lIaltd
StOP bll II root det«:t«j at tn.

of .ve'v ena,acle' It II , . .,t
by' the ER bl! 01 th. Comm.nd
In"'uetlon, FE do.. not Inhlbtl
th. Opetll'on of th. ~P08251 and

.nd

REQuEST TO SEND
"'!I'll'! ..... 111 lorce

ITs

output TO letO

~P08251A
NOIIL!'

INTeRNAL RESET
hlllh retu.ns uSART to
Mooe Instruct.on FOlmar

CD

CV

No effect In ASVNC mode

T.RDY status bIt II not totally eQuI,...I.n, to the T.ROV au'pUt pin, Ih' ',.allO.shlp

"a,

follows

T,.RDY ,Iatu, b" • DB Buffer Emptv
hRDV Ipm lSI
ENTER HUNT MODE
,
enable sealch 10' Sync
Ch,HaCte,!.

A2-18

CD

=

08 8uff" Emptv.

CiS. T.en

APPLICATION OF THE ,uPD8251
AND ,uPD8251A

SYNCHRONOUS
TERMINAL

OR PERIPHERAL
DEvICE

ASYNCHRONOUS SERIAL INTERFACE TO CRT TERMINAL,
OC to 9600 BAUD

SYNCHRONOUS INTERFACE TO TERMINAL OR PERIPHERAL OEVICE

PHONE
llNF

PHONE

LINE
INTEA

INTER
fACE

SYNC
MODEM

TEl EPHONE
LINE

ASYNCHRONOUS INTERFACE TO TELEPHONE LINES

FACE

TELEPHONE
LINE

SYNCHRONOUS INTERFACE TO TELEPHONE LINES

A2-19

PACKAGE OUTLINES
J-IPD8251C
J.LPD8251AC

0°_15"

Plastic
ITEM

I

INCHES

380 MAX

1.96MAX

249
-----_.

0098

A
8
I

I

254

C
D

I

I

05 . 0 I

o 10
o 02

I

. 0 0()4

I J

1302

F

15

0059

G

254 MI'<

H

05 MI'<

o 10 VI'<
o J2 MI'<

.- - - . ----+--- -

I

5

n

MAX

~+--572MAX
K

15 24

J
J

I

--------1

0205 MAX
,
------<
0225 MAX

+--06--------1

L_

-

A

I

J
I

E

r----t-----

--.-

)

MILLIMETERS

K
L

'-

,

!

C

Ceramic
ITEM
A

B
C
0
E
F
G
H

I
J

K
L

M

A2-20

MILLIMETERS
362 MAX
1.59 MAX.
2.54 , 0.1
0.46,0.01
33.02 , 0.1
1.02 MIN.
3.2 MIN.
1.0MIN.
3.5 MAX.
4.5 MAX.
15.24 TYP.
14.93 TYP.

0.25, 0.05

INCHES
1.43 MAX
0.06 MAX
0.1' 0004
0.02,0.004
1.3' 0.004
0.04 MIN.
0.13 MIN.
0.04 MIN.
0.14 MAX.
0.18 MAX.
0.6 TYP.

0.59 TYP.
0.01 , 0.002

/-lPD8251D
/-lPD8251AD

~

-::::;:::::=..."

J";'-==:;:::.

---M

---<
.----.1

0 0 _100~

I--

SINGLE/DOUBLE DENSITY
FLOPPY DISK CONTROLLER
DESCRIPTION

The /JPD765 is an LSI Floppy Disk Controller (FDC) Chip, which contains the circuitry and control
functions for interfacing a processor t04 Floppy Disk Drives. It is capable of supporting either
IBM 3740 single density format (FM), or IBM System 34 Double Density format (MFM) including
double sided recording. The /JPD765 provides control signals which simplify the design of an
external phase locked loop, and write precompensation circuitry. The FDC simplifies and handles
most of the burdens associated with implementing a Floppy Disk Interface.
Hand-shaking signals are provided in the /JPD765 which make DMA operation easy to ixorporate
with the aid of an external DMA Controller chip, such as the /JPDB257. The FDC will operate in
either DMA or Non-DMA mode. In the Non-DMA mode, the FDC generates interrupts to the
processor every time a data byte is available. In the DMA mode, the processor need only load the
command into the FDC and all data transfers occur under control of the /JPD765 and DMA
controller.
There are 15 separate commands which the /JPD765 will execute. Each of these commands require
multiple B-bit bytes to fully specify the operation which the processor wishes the FDC to perform.
The following commands are available:
Read Data
Read ID
Read Deleted Data
Read a Track
Scan Equal

FE.ATURES

Scan High or Equal
Scan Low or Equa!
Specify
Write Data
Format a Track

Write Deleted Data
Seek
Recalibrate (Restore to Track 0)
Sense I nterrupt Status
Sense Drive Status

Address mark detection circuitry is internal to the FDC which simplifies the phase locked loop and
read electronics. The track stepping rate, head load time, and head unload time may be programmed
by the user. The /JPD765 offers many additional features such as multiple ,ector transfers in both
read and write with a single command, and full IBM compatibility in both single and double
density modes.
•
•
•
•
•

•
•
•
•
•
•

IBM Compatible in Both Single and Double Density Recording Formats
Programmable Data Record Lengths: 128,256,512, or 1024 Bytes/Sector
Multi-Sector and Multi-Track Transfer Capability
Drive Up to 4 Floppy Disks
Data Scan Capability - Will Scan a Single Sector or an Entire Cylinder's Worth of Data Fields,
Comparing on a Byte by Byte Basis, Data in the Processor's Mer.1ory with Data Read from the
Diskette
Data Transfers in DMA or Non-DMA Mode
Parallel Seek Dperations on Up to Four Drives
Compatible with Most Microprocessors Including 80BOA, 8085A, /JPD7BO (Z80™)
Single Ph a.. 8 MHz Clock
Single +5 Volt Power Supply
Available in 40 Pin Plastic Dual-in-Line Package

RESET

VCC
RW/SEEK

AD

LCT/oIR

WR

Cs

4

AO
DBa

5
6

DB,

7

DB2

8

oB4

ROY
WP/TS
FLT/TR(

IlPD

DB3

PIN CONFIGURATION

F"'ST?
HDL

10

'PSo

765A

DBS
oB6
DB7
ORO.
oACK
TC

TM:Z80 ... registered tndemark of Zilog. Inc.

lOX

vco

INT

Ro
ROW

CLK

Reprinted through courtesy of NEe Electronics, U.S.A" Inc.

NOTE: These manufacturer's specifications are provided for reference. The APe
may not use some of the functions described here.

GNo

~----..-

WCK

A3-1

BLOCK DIAGRAM

ORO

D'Ac"iC
INT

READY
WAITE PROTECTfTWQ SIDE

INDEX
FAULT/TRACK 0

RESET

UNIT SELECT 0
UNlTSELECT 1
MFM MODE

elK
Vee

RWISEEK
HEAD LOAD
HEADSELECT

ONo

LOW CURRENT/DIRECTION
FAULT RESET/STEP

. _10°C to +70oe
-55°eto+150oe
-0.5 to +7 Volts
-0.5 to +7 Volts
-0.5 to +7 Volts
....... 1 Watt

Operating Temperature.
Storage Temperature
All Output Voitages .
All Input Voltages ..
Supply Voltage Vee
Power Dissipation

ABSOLUTE MAXIMUM
RATINGS*
"COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stren rating onlv and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

Ta = 2SoC

Ta:: _10°C to +70°C;

Vee = +5V

±

DC CHARACTE R ISTICS

5% unless otherwise specified.
LIMITS

PARAMETER

SYMBOL
MIN

Input Low Voltage

Vil

-0.5

Input High Voltage

VIH

2.0

Output Low Voltage

VOL

Output High Voltage

VOH

Input Low Voltage
(ClK + WR Clock)

VlliCY

Clock Active (High, Low)

<1>0

Clock Aise Time

r

20

ns

Clock Fall Time

f

20

ns

'20

TRA

a
a

AD Width

TRR

250

Data Access Time from A 0

~

~

ns

40

AO. CS, DACK Hold Time from AD t

AO, CS, DACK Set Up Time to AD

TAR

ns
ns
ns

TRD

DB to Float Delay Time from AD t

TDF

20

200

ns

CL='OOpf

,00

ns

CL='OOpF

AO. CS, DACK Set Up Time to WA l

TAW

a

ns

AO. CS. DACK Hold Time to WR t

TWA

a

ns

WA Width

TWW

250

ns

Data Set Up Time to WR t

TDW

,50

ns

Data Hold Time from WR t

TWD

5

INT Delav Time from AD t

TRI

500

INT Delay Time from WA t

TWI

500

ORO Cvcle Time

TMCY

ns

,3

ns
ns
~s

,

ns

ORO Delav Time from DACK l

TAM

TC Width

TTC

Reset Width

TRST

WCK Cvcle Time

TCY

WCK Active Time (High)

TO

350

ns

WCK' Ri.. Time

Tr

20

ns

WCK Fall Time

Tf

20

ns

Pre..shift Oelay Time from WCK t

TCp

20

'00

ns

WoA Delay Time from WCK f

TCO

20

,00

n.

ROO Active Time (High)

TROO

40

200

~CY

,4

~CY

MFM =0

2 or 4(OJ
~s

1 or 2
80

250

TWCY

MFM
~.

'.0

TROW

15

n.

TUS

,2

~.

SEEK/RW Hold Time to LOW CURRENT/
DIRECTIDN 1

TSD

7

~.

LOW CURRENT/DIRECTION Hold Tim. to
FAULT RESET/STEP t

TDST

1.0

~.

USO' Hold Time from FAULT
RES'ET/STEP t

TSTU

5.0

~.

STep Acti .... Time (High)

TSTP

6.0

STEP Cvcle Time

TSC

FAULT RESET Active Time (High)

TFR

Window Hold Time to/from ROO

MFM' ,

n.
2.0

Window Cycle Time

TEST
CONOITIONS

-a

MFM' ,

TWRD
USO,1 Hold Time to Ifi'Ii/SEEK

t

Write oltl Width

33
8.0

@

~.

i3)
,0

~.
~.

n.

TWDD TO-50
,5

TSU

Seek Hold Time from OIA

TDS

30

~.

OIA Hold Time after STEP

TSTD

24

~.

Index Pul.. Width

TIDX

10

CY must be 4 mHz.

A3-4

Period

7.0

USO,' Hold Tim. After SEEK

WR

8 MHz Clock

Ta = 25°C; tc = 1 MHz; VCC = OV

CAPACITANCE

PARAMETER

SYMBOL

Clock Input Capacitance

MIN

LIMITS
TYP MAX

UNIT

CIN(ct»

20

pF

Input Capacitance

CIN

10

pF

Output Capacitance

COUT

20

pF

TEST
CONDITIONS
All Pins Except
Pin Under Test
Tied to AC
Ground

AC TEST CONDITION
INPUT/OUTPUT

CLOCK

2.4V

3.0V-----,.

O.45V

0.3V _ _ _- J

AC TESTING
Inputs are driven at 2.4V for a logic "1" and O.4SV for a logic "0." Timing measure·
ments are made at 2.QV for a logic "1" and a.BV for a logic "0."
Clocks are driven at 3,QV for a logic "1" and O.3V for a logic "0," Timing measure-

ments are made at 2.4V for a logic "1" and O.65V for a logic "0."

TIMING WAVEFORMS
PROCESSOR READ OPERATION
AO

Cs. DAcK

=x

PROCESSOR WRITE OPERATION

X\.____

TAR~

I~

-..J :~TRA

RD~TRR_t
L..----'

DATA

____

~ ~R~~

- \ '--TOF
\ )

_____ _

Io.-TRI~

INT

CLOCK
~A

I

eLK

I 00

I

l~I¢OI

OR~ ~,r--,

I

ORO

-.-l ~pF

OPERATION

J:

WRORRD

A3-5

FDD WRITE OPERATION

---!

TERMINAL COUNT

---n-

f-o-To
TC

WRITE CLOCK

~

'I
1
II~ I--TF
I--'-Tcv--l
TR __ : :_,....._ _-;'_ _
1 _ _ _ _ _ _ _.....,.
,

WRITE ENABLE

I

~:

'--

I
t--Tcp

, I
~
PR ESHIFT 0 OR

:c:

RESET

H

,--V---':li.!i"I:
'--.A
T"=1:_.;....---'X..- - ~TCO

-,

--I

I

1
WAITE DATA

PRE5HIFT 0
NORMAL

0

LATE
EARL Y

0
I

INVALID

I

RESET

'--TWOO

----l!

~

0
I

FLT RESET
1

lV

FILE UNSAFE RESET

X-------f\--+-I__
I r-% -X,.....;,..--:,...---------i t---~TU--1

STEP _ _ _ _ _nS_T_D_ _ _
tSTP---j

-II~

I--

1
1 T,DX

1

FDD READ OPERATION

~---------~~~I-------i

:--TRDD

iTWRD-j

READ DATA WINDOW

X

Note: Either polarity data windOW, is valid.

A3-6

:-TRDW-l

I

_---TWCy

1 . ..
1 .

I

TIDX

I

HI--1

~1·~------tsc-------4.~1

_ _ _- - - .

I

~

ll..1

.. ,

I
TFR---

INDEX

DIRECTION _ _ _ _ _

READ DATA

:
-

ItOSI

- ,tSOt--

'

~

FAULTRESET=

--i tsu r-

--ltu~1--

---.j

TRST

0
I

STABLE

tDST

I.-

PRESHIFT 1

---,,"~--_--Jt"'----

RWISEEK

~

--t

SEEK OPERATION
USO,'

I--T TC

TIMING WAVEFORMS
(CaNT.)

I NTE RNAL REG ISTEAS

The IlP0765 contains two registers which may be accessed by the main system processor; a Status Register and a Oata.Register. The 8-bit Main Status Register contains the
status information of the FOe, and may be accessed at any time_ The 8-bit Data
Register (actually consists of several registers in a stack with only one register presented to the data bus at a time), which stores data, commands, parameters, and FDD
status information_ Data bytes are read out of, or written into, the Data Register in
order to program or obtain the results after a particular command_ The Status
Register may only be read and is used to facilitate the transfer of data between the
processor and IlP0765_
The relationship between the Status/Data registers and the signals R D, WR, and AO
is shown below_

INTERNAL REGISTERS
(CONT_)

AO

1m

0
0
0
1
1
1

0
1
0
0
0
1

WR
1
0
0
0
1
0

FUNCTION
Read Main Status Register
Illegal
Illegal
Illegal
Read from Data Register
Write into Data Register

The bits in the Main Status Register are defined as follows'
BIT NUMBER

NAME

DESCRIPTION

SYMBOL

DBa

FOD 0 Busy

DaB

FOD number 0 is in the Seek mode. If any of the bits is set FOe will not accept
read or write command.

DB,

FDD 1 Busy

D,B

FoD number 1 is in the Seek mode. If any of
read or write command.

FOD number 2 is in the Seek mode. If any of the bits is set FOC will not accept
read or wnte command.

th~

bits is set FOe will not accept

DB2

FOD 2 Busy

D2B

DB3

FOD 3 Busy

o3B

FOD number 3 is in the Seek mode. If any of the bits is set FOC will not accept
read or write command.
A read or write command is in process. FOC will not accept any other command.

DB.
oBS

FOC Busy
Execution Mode

CB
EXM

DB6

Data Input/Output

DID

DB,

Request for Master

ROM

This bit is set only during execution phase in non-OM A mode. When DBS goes
low, execution phase has ended, and result phase was started. It operates only
during NON·OMA mode of operation.
Indicates direction of data transfer between FDC and Data Register. It 010 = "1"
then transfer is from Data Register to the Processor. If 010 = "0", then transfer
is from the Processor to Data Register.
Indicates Data Register is ready to send or receive data to or from the Processor
Both bits 010 and RaM should be used to perform the hand-shaking functions of
"ready" and "direction" to the processor.

The 010 and RaM bIts In the Status Register Indicate when Data IS ready and· In which directIon data Will be transferred on the Data
Bus. The max time between the lau AD or WA during command or result phase and 010 and RaM getting set oJr reset is 12 ~s.:£or
this reason every time Main Status Register is read the CPU should wait 12 ~s. The max time from the traiting edge cf the last RO in
the result phase to when OB4 (FOC Busy) goes low is 12 ~s.

Out FOe and Into ProceSSor

Oat a In,Out
(0101

Out Processor and

~

11110 Foci
I

R~dy

I

Request for Masler

f...........,~,_.,..-,,---t---,

(ROM I

I
I

~
Ready

~I

I

~

I

I

rI;

~I

I

I

r---!

~I

:
I

I

WR

:

R5~'
I

I

I

IA IBI

I

A

I

I

I

I

I

I I

IBI A I c I 0I C 10 IBI

I

A

I

Notes ~ - Dala ff.:glster reaC"ly 10 be written ,nto by processor

~ - Data register nOI ready 10 be wntlen mto by processor

©

DaTa reg'ster ready for ne.lo da"l byte 10 be read by the processor

(Q] -

Data ,eglster not reJdy for

n._1 dala byle to be read by processor

A3-7

The /JP0765 is capable of performing 15 different commands. Each command is initiated by a
multi-byte transfer from the processor, and the result after execution of the command may also
be a multi-byte transfer back to the processor. Because of this multi-byte interchange of informa·
tion between the /JP0765 and the processor, it is convenient to consider each command as
consisting of three phases:
Command Phase:

The FOC receives all information required to perform a particular
operatior) from the processor.

Execution Phase:

The FOC performs the operation it was instructed to do.

Result Phase:

After completion of the operation, status and other housekeeping
information are made available to the processor.

COMMAND SEQUENCE

IN ST RU CT ION SET
DATA BUS
PHASE

R/W

07

D.

05 0

DATA BUS

03 0,

0,

Do

REMARKS

PHASE

R/W

07

D.

Os

D.

SCAN LOW OR EQUAL

Command

W

MT

MF

W

SK

,

X

X

Command Codes

X

HO

US,

Command

USO

w

Command execution

X

X

C

Result

REMARKS

Command Codes

usa
Head retra<.ted to Track 0

Command Codes

W

SPECIFY
Command

SCAN HIGH OR eaUAl

SK

,

X

X

,

X

Command Codes

HUT
NO

SRT
HlT

SENSE DRIVE STATUS

Sector 10 information after

Command

HD

US,

Comma nd Codes

W
W

MF

.. • ..

W
W
W

Status information after
Command execution

Command execution

MT

Status information at the end
of seek-opefation about the FOC

STO
PCN

Result

ST 0
ST,
ST'
C

W
W
W
W
W
W
W

US,

Execution

Command

EOT
GPl
STP

FDD and main-system

W

Do

, ,

Data-compared between the

W

0,

SENSE INTERRUPT STATUS

Execution

Command

°2

W
W

Sector I D information prior

W
W
W
W
W
W

03

RECALIBRATE

X

X

Result

,

X

HO US,

usa
Status informaticn about FDD

ST3
SEEK

Command Codes

usa

Command

CommilOd Codes

W
W

Sector 10 information prior
Command execution

W

X

X

X

HD

US,

USO

NCN

Execution

Head is positioned over
propef Cylinder on
Diskette

EOT
GPl
STP

INVALID
ExecutIOn

Result

Data-compared between the
FDD and main-system
ST 0
ST'
ST'

Status information after
Command execution

Result

W

- - - I n v a l i d Codes _ _ _ _

ST

a

Invalid Command Codes
{NoOp - FDC goes lnlo
Standby State)
STO"'BO
(16)

Sector 10 informatIOn after
Command execution

A3-8

Command

INSTRUCTION SET

CD

@ (CaNT.)

J

DATA BUS
REMARKS

PHASE

RIW

0,

0

READ DATA
Command

a

SK

a

05

0

0

REMARKS

0

READ A TRACK

I

Command Codes

o

Command

MF

o

0

0
HO

:-'O~
----OTL

Sector 10 ,,,formallon prIor
to Commande~ecullon The
4bytes.recommandeda9",n.1

US1

W_'O§

h&ad.. r on FloPPV O'ik

----GPe

W

----GeL

----on

Dala transfer between the

08,a""a"de'0eIwel!n!he
FDD and rna'" 'ntern FDC
rl"',.11 datlf,.ld.

FOD sod rna,,, _vuem
StaluSlnlorma"onal!er

5n

Secto, LD,nformal,onproor
10 Command a.eCUI,on

f,om on.... hole

Commande'I!CUIIOn

5T2

",====

Result

Sector ID ,,,format,on aher

5"'-=====

CommBnde~l!cul,on

w EDT

Stalus ,nlormaIIOrl.ltfr
CommandeKecul,on

Sl!<;lOr IOu'lormaTranalte,
CommandeKeculion

READ OELETED DATA
5K

0

Command COdes
HO

US!

AEAOIO

usa
Command

W

W

~~~'OT---

HO

US!

USO
The 1",1 correcllD tnlormatlon
DalaFhg .. ter
S'llu.,,,formaIIOf1,,lIe,
Command exeCullof1

",

Data I'Bnsh!' between ,he
FDDandma,n system

----5T2

0

X

on the Cylinder I.Slofed ,n

Aelull

-5T:~
----ST'

,

See10r 10 ",formauon pflor
to Command execu"on The
4bY'e.arecommandedaga,n<1
header on Floppy Or$~

"2
C

Sector 10 Inlo,m8110n ,ead
durrng e ~ecutlon Pha~8 I,orn

Stalu"nlormatronaHe,
CommandexeculiOn

FlOPpy DIsk

Se.:lor ID,nformalion alte,
Commande.ecu.,on

FORMAT A TRACt<

W

W
W
==~;,~
W
____ 0'-==

Command

Sector 10 ,,,Io,ma.,on pfror
10Commandexeculion The
4 bylll"a'e commanded a!1C'rnl1
heade' on flOppy D'.~

Re,ull

=======~~ ~'====
=======-S~

_5TO:==
----5T2
----ST'

0

1

0
HD

SCAN EOUAL

tiO
Sector 10 >n/ormal'On ah"r
Commande.ecul,on

~

W

Sector 10 ,n/ormat,onpHor
w Command e'.CuHO" Tl'le
4 byleS are comm,nded '9I',nn
header 0" FlOPPY o .. ~

____

---_N

----Gee
----5T'

-----

Resull

Dauecul,on

Oa,a·lfans'e,belweenthe
ma,n-SYltem ~nd fOO

WAITE DELETED OATA
MT

2----

By.e.ISector
SKto"IT,ack
Gap J
Frlle r Byle

~---

-------A------------N-----

Sector 10 ,nlormal,onlh••
Command .xecut,on

Slatu"nlorfnillton aher
Command "".cu1,on

----5T2

---- C

~=~~~

CD


SeclofIO,,,lorfnill,on.lle.
Command e>KuIIO"

Symbols ulad in mil UlbI ..... ct..cr,bed.t th • •rtd of this Jll(:hon

Ao Ihould equa' b,,,-,v 1 for .U

@ )( •

OPtrallO"$

00"'1 ~., usuaU y madI 10 «Iual b,n.ary O.

A3-9

SYMBOL

DESCRIPTION

NAME

Ao controls selection

of Main Status Register (Aa

=0 1 or Data

AO

Address Line 0

C

Cylinder Number

D

Data

o stands for the data pattern which is going to be written into a
Sector.

D7·D O

Data Bus

8-bit Data Bus, where 07 stands for a most significant bit. and

DTL

Data Length

When N is defined as 00, Oll stands for the data length which
users are going to read out or write into the Sector.

EOT

End of Track

EDT stands for the final Sector number on a Cylinder. During
Read or Write operation FOe will stop date transfer after a sector
# equal to EOT.

GPL

Gap Length

GPL stands for the length of Gap 3, During Read/Write commands
this value determines the number of bytes that veos will stay low
after two eRe bytes. During Format command it determines the
size of Gap 3.

H

Head Address

H stands for head number 0 or 1, as specified in 10 field.

HD

Head

H 0 stands for a selected head number 0 or 1 and controls the
polarity of pin 27. (H = HD in all command words.)

HLT

Head Load :Time

H L T stands for the head load time in the FOD (2 to 254 ms in
2 ms increments).

HUT

Head Unload Time

HUT stands for the head unload time after a read or write opera·
tion has occurred (16 to 240 ms in 16 ms increments).

MF

FM or MFM Mode

If MF is low, FM mode is selected, and if it is high, MFM mode is
selected.

MT

Multi-Track

If MT is high, a multi-track operation is to be performed. If MT = 1
after finishing Read/Write operation on side 0 FOe will automatically start searching for sector 1 on side 1.

COMMAND SYMBOL
DESCRIPTION

Register (AO = 11

C stands for the current/selected Cylinder (track) number 0
through 76 of the medium.

DO stands for a least significant bit.

SYSTEM CONFIGURATION

oB()'7

AO

MeMR

oB()'7

iOR

AD
WFi
CS

MmW

iOW
CS

INT
RESET

HRO
HLoA

.PoB257

ORO

CoN~~;LLER om
TC
TERMINAL
COUNT

A3-10

COMMAND SYMBOL
DESCRIPTION (CONT.)

NAME

SYMBOL

DESCRIPTION

N

Number

N stands for the number of data bytes
vvrinen in a Sector.

NCN

New Cylinder Number

NCN stands for a new Cylinder number,
which is going to be reached as a result of the
Seek operation. Desired position of Head.

NO

Non·DMA Mode

NO stands for operation in the Non·DMA Mode.

PCN

Present Cylinder
Number

peN stands for the Cylinder number at the com·

pletion of SENSE INTERRUPT STATUS
Command. Position of Head at present time.

R

Record

R stands for the Sector number, which will
be read or written.

RNi

ReadNirite

RNi stands for either Read IR lor Write IWI
signal.

SC

Sector

SC indicates the number of Sectors per
Cylinder.

SK

Skip

SK stands for Skip Deleted Data Address Mark,

SRT

Step Rate Time

SAT stands for the Stepping Rate for the FOO.
(1 to 16 ms in 1 ms increments.! Stepping Aate
applies to all drives, ~F "" 1 ml, E 2 ms, etc,),

ST a
ST'
ST 2
ST 3

Status a
Status'
Status 2
Status 3

ST ()'3 stand for one of four registers which
store the status information after a command
has been executed. This information is
available during the result phase after command
execution. These registers should not be con·
fL'sed with the main status register (selected by

E

AO = 01. ST Q.3 may be read only after a com·
mand has been executed and contain informatior
relevant to that particular command.
During a Scan operation, if STP = " the data in
contiguous sectors is compared byte by byte
with data sent from the processor (or DMA);
and if STP = 2, then alternate sectors are read
and compared

STP

usa,

US,

Unit Select

US stands for a selected drive number

a or

1.

PROCESSOR I NTER FACE During Command or Result Phases the Main Status Register (described earlier) must be
read by the processor before each byte of information is written into or read from the
Data Register. After each byte of data read or written to Data Register, CPU should
wait tor 12 /.Is before reading MSR. Bits D6 and D7 in the Main Statu; Register must
be in a 0 and 1 state. respectively, before each byte of the command word may be
written into the /.IPD765. Many of the commands require multiple bytes, and as a
result the Main Status Register must be read prior to each byte transfer to the /.IPD765.
On the other hand. during the Result Phase. 06 and D7 in the Main Status Register
must both be 1's (D6 = 1 and D7 = 1) before reading each byte from the Data Register.
Note, this reading of the Main Status Register before each byte transfer to the /.IPD765
is required in only the Command and Result Phases, and NOT during the Execution
Phase.
During the Execution Phase, the Main Status Register need not be read. If the J.lPD765
is in the NON·DMA Mode, then the receipt of each data byte (if /.IPD765 is reading
data from FDD) is indicated by an Interrupt signal on pin 18 (INT = 1). The generation
of a Read signal (RD = 0) or Write signal (WR = 0) will reset the Interrupt as well as
output tne Data onto the Data Bus. If the processor cannot handle I nterrupts fast
enough (every 13 /.Is) for MFM and 27 /.Is for FM mode, then it may poll the Main
Status Register and then bit D7 (ROM) functions just like the I nterrupt signal. I fa
Write Command is in process then the WR signal performs the reset to the Interrupt
signal.

A3-11

If the pPD765 is in the DMA Mode, no Interrupts are generated during the E'(ecution
Phase. The pPD765 generates D RO's (DMA Requests) when each byte of data is avail·
able, The DMA Controller responds to this request with both a DACK ~ 0 (DMA
Acknowledge) and a RD ~ 0 (Read signal). When the DMA Acknowledge signal goes
low (DACK ~ 0) then the DMA Request is reset (DRO ~ 0). If a Write Command has
been programmed then a WR signal will appear instead of RD. After the Execution
Phase has been completed (Terminal Count has occurred) or EOT sector was read I
written, then an I nterrupt will occur (I NT ~ 1). This signifies the beginning of the
Result Phase. When the first byte of data is read during the Result Phase, the Interrupt
is automatically reset (I NT ~ 0),

POLLING FEATURE OF
THE J,lPD765

It is important to note that during the Result Phase all bytes shown in the Command
Table must oe read. The Read Data Command, for example has seven bytes of data in
the Result Phase. All seven bytes must be read in order to successfully complete the
Read Data Command. The pPD765 will not accept a new command until all seven
bytes have been read. Other commands may require fewer bytes to be read during the
Result Phase.
The pPD765 contains five Status Registers. The Main Status Register mentioned above
may be read by the processor at any time. The other four Status Registers (STO, ST1,
ST2, and ST3) are only available during the Result Phase, and may be read only after
completing a command. The particular command which has been executed determines
how many of the Status Registers will be read.
The bytes of data which are sent to the pPDY65 to form the Command Phase, and are
read out of the pPD765 in the Result Phase, must occur in the order shown in the
Command Table. That is, the Command Code must be sent first and the other bytes
sent in the prescribed sequence. No foreshortening of the Command or Result Phases
are allowed. After the last byte of data in the Command Phase is sent to the ).lPD765,
the Execution Phase automatically starts. In a similar fashion, when the last byte of
data i~ read out in the Result Phase, the command is automatically ended and the
pPD765 is ready for a new command.
After the Specify command has been sent to the pPD765, the Unit Select line USO and
US1 will automatically go into a polling mode. In between commands (and between
step pulses in the SEEK command) the ).lPD765 polls all four FDD's looking for a
change in the Ready line from any of the dri~es. If the Rea,dy line changes state (usually
due to a door opening or closing) then the pPD765 will generate an interrupt, When
Status Register 0 (STO) is read (after Sense interrupt Status is issued), Not Ready (NR)
will be indicated, The polling of the Ready line by the ).lPD765 occurs continuously
between commands, thus notifying the processor which drives are on or off line. Each
drive is polled every 1,024 ms except during the ReadlWrite commands,
READ DATA
A set of nine (9) byte words are required to place the FOe into the Read Data Mode. After the Read Data
command has been issued the FOe loads the head (if it is in the unloaded state), waits the specified head
settling time (defined in the Specify Command), and begins reading 10 Address Marks and 10 fields. When
the current sector number ("R") stored in the 10 Register (IDA) compares with the sector number read off
the diskette, then the FOe outputs data (from the data field) byte·to-byte to the main system via the data
bus.
After completion of the read operation from the current sector, the Sector Number is incremented by one,
and the data from the next sectOr is read and output on the data bus. This continuous read function is called
a "Multi-Sector Read Operation." The Read Data Command may be terminated by the receipt of a Terminal
Count signal. TC should be issued at the same time that the OACK for the last byte of data is sent. Upon
receipt of this signal, the FOe stops outputting data to the processor, but will continue to read data from the
current sector, check CRC (Cyclic Redundancy Count) bytes, and then at the end of the sector terminate
the Read Data Command.
The amount of data which can be handled with a single command to the FOe depends upon MT (multi-

track), MF (MFM/FM). and N (Number of Bytes/Sector!c Table 1 below shows the Transfer Capacity.

A3-12

FUNCTIONAL
DESCRIPTION OF
COMMANDS

Multi-Track
MT

MFM/FM
MF

Bytes/Sector
N

Maximum Transfer Capacity
(Bytes/Sector) (Number of Sectors)

0
0

0
1

00
01

(128) (26) =
(256) (26) =

1
1

0
1

00
01

(1281 (52) = 6,656
(256) (521 = 13,312

0
0

0
1

01
02

(256) (15) =
(5121(151 =

1
1

0
1

01
02

(2561 (301 - 7,680
(5121(301 = 15,360

0
0

0
1

02
03

(5121(81
(10241(81

1
1

0
1

02
03

(5121(161 = 8,192
(1024) (16) = 16,384

=

3,328
6,656

3,840
7,680

4,096
8,192

Final Sector Read
from Diskette
26 at Side 0
or 26 at Side 1
26 at Side 1
15 at Side 0
or 15 at Side 1

15 at Side 1
8 at Side 0
or 8 at Side 1

8 at Side 1

Table 1. Transfer Capacity
The "multi-track" function (MT) allows the FOG to read data from both sides of the diskette. For a
particular cylinder, data will be transferred starting at Sector 1, SIde 0 and completing at Sector L. Side 1

(Sector L = last sector on the side). Note. this function pertains to only one cylinder (the same track) on
each side of the diskette.
When N = 0, then DTL defines the data length which the FDG must treat as a sector. If DTL is smaller than
the actual data length in a Sector, the data beyond Dll in the Sector, is not sent to the Data Bus. The FOe
reads (internally) the complete Sector performing the CRC check, and depending upon the manner of command termination, may perform a Multi-Sector R~ad Operation. When N is non-zero. then OTL has no
meaning and should be set to F F HexidecimaL

At the completion of the Read Data Command. the head is not unloaded until after Head Unload Time
Interval (specified in the Specify Command) has elapsed_ If the processor issues another command before
the head unloads then the head settling time may be saved between subsequent reads_ This time out is
particularly valuable when a diskene is copied from one drive to another_
If the FOC detects the Index Hole twice without finding the right sector. (indicated in "R"l. then the FOe
sets the NO (No Data) flag in Status Register 1 to a 1 (high). and terminates the Read Data Command.
(Status Register 0 also has bits 7 and 6 set to a and 1 respectively.j
After reading the 10 and Data Fields in each sector, the FOC checks the CRe bytes. If a read error is
detected (incorrect eRe in 10 field I, the FOe sets the DE (Data Error) flag in Status Register 1 to a 1 (highl,

and if a CRC error occurs in the Data Field the FOC also sets the DO (Data Error in Data Field) flag in
Status Register 2 to a 1 (high), and terminates the Read Data Command. (Status Register 0 also has bits 7

and 0 set to 0 and 1 respectively.)
If the F DC reads a Deleted Data Address Mark off the diskette, and the SK bit (bit 05 in the first Command
Wordl is not set {SK = 01. then the FDC sets the CM (Control Mark) flag in Status Register 2 to a 1 (highl.
and terminates the Read Data Command, after reading all the data in the Sector. If SK = 1, the FOC skips
the sector with the Deleted Data Address Mark and reads the next sector. The CRe bits in the deleted data
field are not checked when SK = 1.
During disk data transfers between the FOC and the processor, via the data bus, the FOC must be serviced
by the processor every 27 IJS in the FM Mode, and every 13,us in the MFM Mode, or the FOC sets the OR
(Over Run) flag in Status Register 1 to a 1 (high), and terminates the Read Oata Command.
If the processor terminates a read (or write) operation in the FOC, then the 10 Information in the Aesult
Phase is dependent upon the state of the MT bit and EOT byte. Table 2 shows the values for C, H, A, and
N, when the processor terminates the Command.

A3-13

10 Information at Result Phase
MT

Final Sector Transferred to Processor

HD

C
NC

0

Less than EOT

0

Equal to EOT

1

Less than EOT

NC

1

Equal to EOT

C+1

NC

0

Less than EOT

NC

NC

0

Equal to EOT

NC

LSB

1

Less than EOT

NC

NC

1

Equal to EOT

C+1

LSB

0

C

+1

NC
NC
NC

1

Notes:

R

N

R+1

NC

H

R

= 01

NC

R +1

NC

R

= 01

NC

R+1

NC

R

= 01

NC

R+1

NC

R

= 01

NC

1 NC (No Change): The same value as the one at the beginning of command execution.
2

LSB (Least Significant Bit): The least significant bit of H is complemented.

WRITE DATA

A set of nine (9) bytes are required to set the FOC into the Write Data mode. After the Write Data command
has been issued the FDC loads the head (if it is in the unloaded state), walts the specified Head Settling Time
(defined in the Specify Command), and begins reading ID Fields. When all four bytes loaded during the command (C, H, R, N) match the four bytes of the ID field from the diskette, the FDC takes data from the
processor byte-by-byte via the data bus, and outputs it to the FDD.
After writing data into the current sector, the Sector Number stored in "R" is incremented by one, and the
next data field is written into. The FDC continues this "Multi·Sector Write Operation" until the issuance of
a Terminal Count signal. If a Terminal Count signal is sent to the FOC it continues writing into the current
sector to complete the data field. If the Terminal Count signal is received while a data field is being written
then the remainder of the data field is filled with 00 (zeros).
The FDC reads the 10 field of each sector and checks the CRC bytes. If the FOC detects a read error
(incorrect CRC) in one of the 10 Fields, it sets the DE (Data Error) oag of Status Register 1 to a 1 (high).
and terminates the Write Data Command. (Status Register 0 also has bits 7 and 6 set to 0 and 1 respectively.)
The Write Command operates in much the same manner as the Read Command. The following items are the
same, and one should refer to the Read Data Command for details:
• Transfer Capacity
• EN (End of Cylinder) Flag
• NO (No Data) Flag

•
•
•

Head Unload Time Interval
10 Information when the processor terminates command (see Table 2)
Definition of OTL when N '"' 0 and when N =F 0

In the Write Data mode, data transfers between the processor and FOC, via the Data Bus, must occur every
27 ~s in the FM mode, and every 131-'s in the MFM mode. If the time Interval between data transfers is
longer than this then the FDC sets the OR (Over Run) flag in Status Register 1 to a 1 (high), and terminates
the Write Data Command. (Status Register 0 also has bit 7 and 6 set to 0 and 1 respectively,)
WRITE DELETED DATA

This command is the same as the Write Data Command except a Deleted Data Address Mark is written at the
beginning of the Data Field instead of the normal Data Address Mark.
READ DELETED DATA

This command is the same as the Read Data Command except that when the F DC detects a Data Address
Mark at the beginning of a Data Field (and SK = 0 (low), it will read all the data in the sector and seT the
eM flag in Status Register 2 to a 1 (high), and then terminate the command. If SK = 1, then the FOe skips
the sector with the Data Address Mark and reads the next sector.

READ A TRACK

This command is Similar to READ DATA Command except that thiS IS a contInuous READ operation
where the entire data fiel~ from each of the sectors are read. Immediately after encountering the
INDEX HOLE, the FDC starts reading all data fields on the track, as continuous blocks of data. If the
FOC finds an error in the 10 or DATA CAC check bytes, it continues to read data from the track. The
FDC compares the 10 information read from each sector with the value stored In the IDA, and sets the
iND flag of Status Register 1 to a 1 (high) If there is no comparison. Multi·track or skip operations are not
allowed with this command.

A3-14

FUNCTIONAL
DESCRIPTION OF
COMMANDS (CONT.)

FUNCTIONAL
DESCRIPTION OF
COMMANDS (CONT.)

This command terminates when number of sectors read is equal to'EOT. If the FOe does not find
an 10 Address Mark on the diskette after it encounters the INDEX HOLE for the second time,
then it sets the MA (missing address mark) flag in Status Register 1 to a 1 (high), and terminates
the command. (Status Register 0 has bits 7 and 6 set to 0 and 1 respectively,)
READ 10
The READ ID Command is used to give the present position of the recordmg head The FOe stores the
values from the first 10 Field
before the INDEX HOLE

IS

It IS

able to read. If no proper 10 Address Mark

IS

found on the diskette,

encountered for the second time then the MA (Missing Address Mark) flag

In

Status Register 1 IS set to a 1 (high), and If no data IS found then the NO {No Data} flag IS also set In Status
Register 1 to a 1 (high). The command is then terminated with Sits 7 and 6 In Status Register 0 set to 0
and 1 respectively, DUring this command there IS no data transfer between FOC and the CPU except during
the result phase.

FORMAT A TRACK
The Format Command allows an entire track to be formatted. After the INDEX HOLE is detected, Data is
'vVI"itten on the Diskette; Gaps, Address Marks, 10 Fields and Data Fields, all per the IBM System 34 (Double
Density) or System 3740 (Single Density) Format are recorded. The particular format which will be written
is controlled by the values programmed into N (number of bytes/sector), SC (sectors/cylinder), GPL (Gap
Length), and 0 (Data Pattern) which are supplied by the processor during the Command Phase. The Data
Field is filled with the Byte of data stored in O. The 10 Field for each sector is supplied by the processor
that is, four data requests per sector are made by the FOC for C (Cylinder Number), H (Head Number\.
R (Sector Number) and N (Number of Bytes/Sector). This allows the diskette to be formatted with non,
sequential sector numbers, if desired.
The processor must send new values for C, H, R, and N to the ,uP0765 for each sector on the track, If FOC
IS set for OMA mode, it Will issue 4 DMA requests per sector. If It IS set for mterrupt mode, It will Issue tour
interrupts per sector and the processor must supply C, H, Rand N load for each sector. The r:ontents of
the R register IS Incremented by one after each sector IS formatted, thus, the R register contains a value of
R when It IS read during the Result Phase. ThiS Incrementing and formatting contmues for the whole track
until the FOC encounters the INDEX HOLE for the second time; whereupon It terminates the command
If a FAULT Signal IS received from the FOO at the end of a write operation, then the FOC sets the EC
flag of Status Register 0 to a 1 (high), and terminates the command after setting bits 7 and 6 of Status
Register

0 to 0 and 1 respectively. Also the loss of a READY Signal at the beginning of a command

execution phase causes bits 7 and 6 of Status Register 0 to be set to 0 and 1 respectively.
Table 3 shows the relationship between N, SC, and GPL for various sector Slles

514" MINI FLOPPY

8" STANDARD FLOPPY
FORMAT

FM Mode

MFM Mode

G:

GPL~

SECTOR SIZE

N

SC

GPLG)

SECTOR SIZE

N

SC

GPL

128 bytes/Sector

00

1A

07

18

128 bytes/Sector

00

12

07

256

01

OF

OE

2A

128

00

10

10

19

512

02

08

18

3A

256

01

08

18

30

GPL®

09

1024 bytes/Sector

03

04

47

8A

512

02

04

46

87

2048

04

02

C8

FF

1024

03

02

C8

FF

4096

05

01

C8

FF

2048

04

01

C8

FF
OC

256

01

1A

OE

36

256

01

12

OA

512

02

OF

18

54

256

01

10

20

32

1024

03

08

35

74

512

02

08

2A

50

2048

04

04

99

FF

1024

03

04

80

FO

4096

05

02

C8

FF

2048

04

02

C8

FF

8192

06

01

C8

FF

4096

05

01

C8

FF

Table 3
Note:

 DProcessor
DFDD < Dprocessor

a
a

1

COMMENTS

< OProcessor

DFOD> 0Processor

Table 4

If the FOC encounters a Deleted Data Addres:; Mark on one of the sectors (and SK := 0), then it regaros the
sector as the last sector on the cylinder, sets CM (Control Mark) flag of Status Register 2 to a 1 (hig'-') and
terminates the command. If SK = 1, the FOC skips the sector with the Deleted Address Mark, and reads
the next sector. In the second case (SK 1), the FOC sets the CM (Control Mark) flag of Status Register 2
to a 1 (high) in order to show that a Deleted Sector had been encountered.
:0

When either the STP (contiguous sectors = 01, or alternate sectors = 02 sectors are read) or the MT (MultiTrack) are programmed, it is necessary to remember that the last sector on the track must be read. For
example, if STP == 02, MT := 0, the sectors are numbered sequentially 1 through 26, and we start the Scan
Command at sector 21; the following will happen. Sectors 21, 23, and 25 will be read, then the next sectol
(26) ~ill be skipped and the Index Hole will be encountered before the EDT value of 26 can be read. This
will result in an abnormal termination of the command. If the EDT had been set at 25 or the scanning
started at sector 20, then the Scan Command would be completed in a normal manner.
During the Scan Command data is supplied by either the processor or DMA Controller for comparison
against the data read from the diskette. In order to avoid having the OR (Over Run) flag set in Status
Register 1, it is necessary to have the data available in less than 27 J.1s (FM Mode) or 13 J.1s (MFM Mode). If
an Overrun occurs the F DC ends the command with bits 7 and 6 of Status r.egister 0 set to 0 and 1,
respect ivel y.
SEEK

The read/write head within the FOO is moved from cylinder to cylinder under control of the Seek Command. FOe has four independent Present Cylinder Registers for each drive. They are clear only after
Recalibrate command. The FOe compares the PCN (Present Cylinder Number) which is the current head

A3-16

FUNCTIONAL
DESCRIPTION OF
COMMANDS (CONT.)

FUNCTIONAL
DESCRIPTION OF
COMMANDS (CONT.)

position with the NCN (New Cylinder Number), and If there is a difference performs the following
operation:
peN
NCN: Direction signal to FOD set to a 1 (high), and Step Pulses are issued. (Step In.!

<

peN> NCN: Direction signal to FOO set to a a (low), and Step Pulses are issued. (Step Out.)

The rate at which Step Pulses are issued is controlled by SAT (Stepping Rate Time) in the SPECIFY Command. After each Step Pulse is issued NCN is compared against peN, and when NCN : peN, then the SE
(Seek End) flag is set in Status Register 0 to a 1 (high), and the command is terminated. At this point

FOe interrupt goes high. Bits DBO~DB3 in Main Status Register are set during seek operation and
are cleared by Sense I nterrupt Status command.
During the Command Phase of the Seek operation the FOC is in the FOC BUSY state, but during the
Execution Phdse it is in the NON BUSY state. While the FDC is In the NON BUSY state, another Seek
Command may be issued, and in this manner parallel seek operations may be done on up to 4 Drives at
once. No other command could be issued for as lo.,g as FDC IS in process of sending Step Pulses to any
drive.
If an FOD is in a NOT READY state at the beginning of the command execution phase or during the seek
operation, then the NR (NOT READY) flag is set in Status Register 0 to a 1 (high), and the command is
terminated after bits 7 and 6 of Status Register 0 are set to 0 and 1 respectively.
If the time to write 3 bytes of seek command exceeds 150 .us, the timing between first two Step Pulses
may be shorter than set in the Specify command by as much as 1 ms.

RECALIBRATE
The function of this command is to retract the read/write head within the FDO to the Track 0 position.
The FOC clears the contents of the PCN counter, and checks the status of the Track 0 signal from the
FDD. ~ long as the Track 0 signal is low, the Direction signal remains 0 (low) and Step Pulses are issued.
When the Track 0 signal goes high. the SE (SEEK END) flag in Status Register 0 is set to. 1 (high) and the
command is terminated. If the Track 0 signal is still low after 77 Step Pulse have been issued, the F DC sets
the SE (SEE K END) and EC (EQUIPMENT CHECK) Ilags 01 Status Register 0 to both 1s (highs), and
term inates the command after bits 7 and 6 of Status Register 0 is set to 0 and 1 respectively.

The ability to do overlap RECALIBRATE Commands to multiple FDD. and the loss 01 the READY signal,
as described in the SEEK Command. also applies to the RECALIBRATE Command.
SENSE INTERRUPT STATUS
An Interrupt signal is generated by the FOC for one of the following reasons:
1. Upon entering the Result Phase of:

o. Read Data Command
b. Read a Track Command
c. Read 10 Command
d. Read Deleted Data Command

e.
I.
g.
h.

Write Data Command
Format aCyl inder Command
Write Deleted Data Command
Scan Commands

2. Ready Line of FDD changes state
3. End of Seek or Recalibrate Command
4. During Execution Phase in the NON-OMA Mode
Interrupts caused by reasons 1 and 4 above occur during normal command operations and are easily discernible by the processor. During an execution phase in NON·DMA Mode, 085 in Main Status Register
is htgh. Upon entering Result Phase this bit gets clear. Reason 1 and 4 does not require Sense Interrupt
Status command. The interrupt is cleared by reading/writing data to FOe. Interrupts caused by reasons
2 and 3 above may be uniquely identified with the aid of the Sense Interrupt Status Command. ThiS
command when Issued resets the Interrupt signal and via bits 5, 6, and 7 of Status Register 0 identifies
the cause of the interrupt.

SEEK END
BIT 5

INTERRUPT CODE
BIT 6

CAUSE

BIT 7

0

1

1

Ready Line changed state, either polarity

1

0

1

1

0
0

Abnormal Termination of Seek or Recalibrate Command

Normal Termination of Seek or Recalibrate Command

Tobl.5
Neither the Seek or Recalibrat. Command have a Result Phase. Therefore, it is mandatory to use the Sense
Interrupt Status Command after these commands to .ffectively terminate them and to provide verification of
where the head is positioned (PCN),
Issuing Sense InterruPt Status Command without interrupt pending is treated as an invalid commant'.!.

A3-17

SPECIFV
The Specify Command sets the initial values for each of the three internal timers. The HUT (Head Unload Time)
defines the time from the end of the Execution Phase of one of the Read/Write Commands to the head unload

state. This timer is programmable from 16 to 240 ms in increments of 16 ms (01 = 16 ms, 02 =32 ms .... OF::
240 msl. The SAT (Step Rate Time) defines the time interval between adjacent step pulses. This timer is pro·
grammable from 1 to 16 ms in increments of 1 ms IF "" 1 ms, E z 2 ms, 0 = 3 ms, etc.L The HL T (Head Load
Time) defines the time between when the Head Load signal goes high and when the ReadlWrite operation starts.
This timer is programmable from 2 to 254 ms in· increments of 2 ms (01 =2 ms, 02 "" 4 ms, 03 = 6 ms ... 7 F =

254 msl.
The time intervals mentioned above are a direct function of the clock Ie LK on pin '9)' Times indicated above
are for an 8 MHz clock, if the c~ock was reduced to 4 MHz (mini-floppy application) then all time intervals are
increased by a factor of 2.
The choice of OMA or NON-OM A operation is made by the NO (NON-OMA) bit. When this bit is high (NO = ,)
the NON·OMA mode is selected, and when NO .. 0 the OMA mode is selected.
SENSE DRIVE STATUS
This command may be used by the processor whenever it wishes to obtain the status of the FOOs. Status
Register 3 contains the Drive Status information stored internally in FOe registers.
INVALID
If an invalid command is sent to the FOe (a command not defined above), then the FOe will terminate the command after bits 7 and 6 of Status Register 0 are set to , and 0 respectively. No interrupt is generated by the
~PD765 during this condition. Bit 6 and bit 7 (010 and ROM) in the Main Status Registar are both high (",")
indicating to the processor that the jJP0765 is in the R8Sult Phase and the contents of Status Register 0 (STO)
must be reacl. When the processor reads Status Register 0 it will find a 80 hex indicating an invalid command
was received.
A Senae Interrupt StatuI Command mUlt be sent after a Seek or Recalibrate Interrupt, otherwise the FOe will
consider the next command to be an Invalid Command.

In some.pplicationl the user may wish to use this command as a No-Op command, to place the FOe in a
standby or no operation state.

A3-I8

STATUS REGISTER
IDENTIFICATION

BIT
NAME

NO.

J
SYMBOL

I

DESCRIPTION

STATUS REGISTER 0

07 = 0 and 06 = 0
Normal Termination of Command. (NT). Command was completed and properly executed.

07
Interrupt
Code

IC

07 o and 06 1
Abnormal Termination of Command. (AT).
Execution of Command was started. but was not
successfully completed.

06

07 - 1 and 06 - 0
Invalid Command issue. (IC). Command which
was issued was never started.

07 - 1 and 06 - 1
Abnormal Termination because during command
execution the ready signal from FDD changed
state.
05

Seek End

SE

When the FDC completes the SEEK Command.
this flag is set to 1 (high).

04

Equipment
Check

EC

If a fault Signal is received from the FDD. or if
the Track 0 Signal fails to occur after 77 Step
Pulses (Recalibrate Command) then this flag is
set.

03

Not Ready

NR

When the FDD,is in the not-ready state and a
read or write command is issued. th is flag is set.
If a read or write command is issued to Side 1 of
a single sided drive. then th is flag is set.

02

Head
Address

HD

This flag is used to indicate the state of the head
at Interrupt.

01

Unit Select 1
Unit Select 0

US 1

DO

'uso

These flags are used to indicate a Drive Unit.
Number at Interrupt_

07

End of

EN

When the F DC tries to access a Sector beyond
the final Sector of a Cylinder. this flag is set.
When the FDC detects a CRC error in either the
10 field or the data field. this flag is set.
If the FDC is not serviced by the main-systems
during data transfers. within a certain time
interval. this flag is set.

STATUS REGISTER 1
~ylinder

Not used. This bit is always 0 (low).

06
05

Data Error

DE

04

Over Run

OR

03
02

iNo Data

NO

Not used. This bit always 0 (low).
During execution of READ DATA. WRITE
DELETED DATA or SCAN Command. if the
FDC cannot find the Sector specified in the IDR
Register. this flag is set.
During executing the READ 10 Command. if
the FDC cannot read the ID field without an
error. then this flag is set.

I

I

During the execution of the READ A Cylinder
Command. if the starting sector cannot be
found. then this flag is set.

A3-19

BIT
NO.

I

NAME

I

SYMBOL

I
I

STATUS REGISTER
IDENTIFICATION (CONT,)

DESCRIPTION

STATUS REGISTER 1 (CONT.I
01

Not
Writable

NW

During execution of WRITE DATA, WRITE
DELETED DATA or Format A Cylinder Com·
mand, if the F DC detects a write protect signal
from the FDD, then this flag is set.

DO

Missing
Address

MA

If the FDC cannot detect the ID Address Mark
after encountering the index hole twice, then
th is flag is set.

Mark

I! the FDC cannot detect the Data Address Mark
or Deleted Data Address Mark, this flag is set.
Also at the same time, the MD (Missing Address
Mark in Data Fieldl of Status Register 2 is set.
STATUS REGISTER 2
Not used. This bit is always 0 (low).

D7
D6

Control
Mark

CM

During executing the READ DATA or SCAN
Command, if the F DC encou nters a Sector wh ich
contains a Deleted Data Address Mark, th is
flag is set.

D5

Data Error in

DO

I! the FDC detects a CRC error in the data field
then this flag is set.

Data Field
D4

Wrong
Cylinder

WC

This bit is related with the ND bit, and when the
contents of C on the medium is different from
that stored in the lOR, this flag is set.

D3

Scan Equal
Hit

SH

During execution, the SCAN Command, if the
condition of "eQual" is satisfied. this flag is set.

D2

Scan Not
Satisfied

SN

During executing the SCAN Command, if the
FOe cannot find a Sector on the cylinder which
meets the condition, then this flag is set

Dl

Bad
Cylinder

BC

This bit is related with the NO bit. and when the
content of C on the medium is different from

that stored in the lOR and the content of C

IS

FF, then this flag is iiet.

DO

Missing

MD

Address Mark
in Data Field

When data is read from the medium, if the F DC
caf1not find a Data Address Mark or Deleted
Data Address Mark, then this flag is set.
STATUS REGISTER 3

A3-20

D7

Fault

FT

This bit is used to indicate the status of the
Fault signal from the FDD.

D6

Write
Protected

WP

This bit is used to Indicate the status of the
Write Protected signal from the FDD.

D5

Ready

RY

This bit is used to indicate the status of the
Ready signal from the FDD.

D4

Track 0

TO

This bit is used to indicate the status of the
Track 0 signal from the FDO.

D3

Two Side

TS

This bit is used to indicate the status of the
Two Side signal from the FDD.

D2

Head Address

HD

This bit is used to indicate the status of Side
Select signal to the F DD.

Dl

Unit Select 1

US 1

This bit is used to indicate the status of the Unit
Select 1 signal to the FDD.

DO

Unit Select 0

USO

This bit is used to indicate the status of the Unit
Select 0 signal to the F DD.

It is suggested that you utilize the following applications notes:

CD #8 -

for an example of an actual interface. as well as a "theoretical" data
separator.

(2) #10 - for a well documented example of a working phase lock loop.

PACKAGE OUTLINE
IlPD765AD
Ceramic

G

l~:J~
0·10'

1 - - - - - - - E ------~

ITEM

MILLIMETERS

INCHES

A
B
C
0
E

51.5 MAX
1.62 MAX
2.54' 0.1
0.5,0.1
4B.26 , 0.1
'.02 MIN
3.2 MIN
1.0 MIN
3.5 MAX
4.5 MAX
15.24 TYP
14.93 TYP
0.25' 0.05

2.03 MAX
0.06 MAX
0.1 ! 0.004
0.02' 0.004
1.9,0.004
0.04 MIN
0.13MIN
0.04 MIN
0.14 MAX
0.1B MAX
0.6 TYP
0.59 TYP
0.01 , 0.0019

F

G
H

1
J
K
L

M

PACKAGE OUTLINE
IlPD765AC
Plutic
ITEM

MILLIMETERS

A

51.5 MAX

INCHES
2.028 MAX

1.62

0.064

C

2.54 • 0.1

0.10

0
E

0.5! 0.1

0.019:! 0.004

B

F

4B.26

~

0.004

1.9

1.2MIN

0.047 MIN
0.10MIN

G

2.54 MIN

H

0.5MIN

0.019 MIN

I

5.22 MAX

0.206 MAX

J

5.72 MAX

K

15.24

L

13.2

M

0.25

0.225 MAX
0.600
0.520

·0.1
0.05

0.010

·0.004
0.002

A3-21

PRELIMINARY
GRAPHICS DISPLAY CONTROLLER
Description
The fLPD7220 Graphics Display Controller (GDC) is an
intelligent microprocessor peripheral designed to be the
heart of a high-performance raster-scan computer graphics
and character display system. Positioned between the
video display memory and the microprocessor bus, the
GDC performs the tasks needed to generate the raster display and manage the display memory. Processor software
overhead IS minimized by the GDC's sophisticated instruction set, graphics figure drawing, and DMA transfer capabilities. The display memory supported by the GDC can be
configured in any number of formats and sizes up to 256K
16-bit words. The display can be zoomed and panned,
while partitioned screen areas can be independently
scrolled. With Its light pen Input and multiple controller
capability, the GDC IS ideal for advanced computer
graphics applications.
Features
D Microprocessor Interface
DMA transfers with 8257- or 8237-type controllers
FIFO Command Buffering
D Display Memory Interface
Up to 256K words of 16 bits
Read-Modlfy-Wrlte (RMW) Display Memory cycles
In under BOOns
Dynamic RAM reresh cycles for non accessed memory
D Light Pen Input
D External video synchronization mode
D Graphics Mode:
Four megabit, bit-mapped display memory
D Character Mode:
BK character code and attributes display memory
D Mixed Graphics and Characters Mode
64K if all characters
1 megapixel if all graphiCS
D Graphics Capabilities
Figure drawing of lines, arc/circles, rectangles, and
graphics char~cter in BOOns per pixel
Display 1024-by-1 024 pixels with 4 planes of color
or grayscale.
Two independently scroll able areas
Character Capabilities:
Auto cursor advance
Four independently scrollable areas
Programmable cursor height
Characters per row: up to 256
Character rows per screen: up to 100
D Video Display Format
Zoom magnification factors of 1 to 16
Panning
Command-settable video raster parameters
o Technology
Single +5 volt, NMOS, 40-pin DIP
o DMA Capability:
Bytes or word transfers
4 ciock periods per byte transferred

System Considerations
The GDC is designed to work with a general purpose
microprocessor to implement a high-performance computer graphics system. Through the division of labor
established by the GDC's design, each of the system
components is used to the maximum extent through sixlevel hierarchy of simultaneous tasks. At the lowest level,
the GDC generates the basic video raster timing, including
sync and blanking signals. Partitioned areas on the screen
and zooming are also accomplished at this level. At the
next level, video display memory is modified during the figure drawing operations and data moves. Third, display
memory addresses are calculated pixel by pixel as drawing
progresses. Outside the GDC at the next level, preliminary
calculations are done to prepare drawing parameters. At
the fifth level, the picture must be represented as a list of
graphics figures drawable by the GDC. Finally, this representation must be manipulated, stored, and communicated By handling the first three levelS, the GDC takes care
of the high-speed and repetitive tasks required to implement a graphics system.
ODe Components
The GDC block diagram illustrates how these tasks are
accomplished.

o

Microprocessor Bus Interface
Control of the GDC by the system microprocessor is
achieved through an 8-bit bidirectional interface. The
status register is readable at any time. Access to the FIFO
buffer is coordinated through flags in the status register
and operates independently of the various internal GDC
operations, due to the separate data bus connecting the
interface and the FIFO buffer.

Command Processor
The contents of the FIFO are interpreted by the command
processor. The command bytes are decoded, and the succeeding parameters are distributed to their proper destina-

Reprinted through courtesy of NEC Electronics, U_S_A., Inc.

NOTE: These manufacturer's specifications are provided for reference, The APe
may not use some of the functions described here.

A4-1

tions within the GOC. The command processor yields to the
bus Interface when both access the FIFO simultaneously.
DMAControl
The OMA control circuitry in the GOC coordinates transfers
over the microprocessor interface when using an external
OMA controller. The OMA Request and Acknowledge
handshake lines directly interface with a !,P08257 or
!,P08237 OMA controller, so that display data can be
moved between the microprocessor memory and the display memory.
Parameter RAM
The 16-byte RAM stores parameters that are used repetitively during the display and drawing processes. In character mode, this RAM holds four sets of partitioned display
area parameters: in graphics mode, the drawing pattern
and graphics character take the place of two of the sets of
parameters.
Video Sync Generator
Based on the clock input, the sync logic generates the raster timing signals for almost any interlaced, non-interlaced,
or "repeat field" interlaced video format. The generator IS
programmed during the idle period following a reset. In
video sync slave mode, it coordinates timing between multipleGOCs.
Memory Timing Generator
The memory timing circuitry provides two memory cycle
types: a two-clock peri.od refresh cycle and the readmodify-write (RMW) cycle which takes four clock penods
The memory control signals needed to drive the display
memory devices are easily generated from the GOC's ALE
and DtlTN outputs.
Zoom & Pan Controller
Based on the programmable zoom display factor and the
display area entries In the parameter RAM, the zoom and
pan controller determines when to advance to the next
memory address for display refresh and when to go on to
the next display area. A horizontal zoom is produced by
slowing down the display refresh rate while maintaining the
video sync rates. Vertical zoom is accomplished by repeatedly accessing each line a number of times equal to the
horizontal repeat. Once the line count for a display area is
exhausted, the controller accesses the starting address
and line count of the next display area from the parameter
RAM. The system microprocessor. by modifying a display
area starting address, can pan In any direction, independent of the other display areas.
Drawing Processor
The drawing processor contains the logiC necessary to
calculate the addresses and positions of the pixels of the
various graphics figures. Given a starting point and the
appropriate drawing parameters, the drawing processor
needs no further assistance to complete the figure drawing.
Display Memory Controller
The display memory controller's tasks are numerous. Its
primary purpose is to multiplex the address and data information in and out of the display memory. It also contains
the 16-bit logic unit used to modify the display memory contents during RMW cycles, the character mode line counter,
and the refresh cou'nter for dynamic RAMs. The memory
controller apportions the video field time between the various types of cycles.
Light Pen Deglitcher
Only if two rising edges on the light pen input occur at the
same point during successive video fields are the pulses

A4-2

accepted as a valid light pen detection. A status bit indicates to the system microprocessor that the light pen register contains a valid address.
Programmer's View of GDC
The GOC occupies two addresses on the system microprocessor bus through which the GOC's status register and
FIFO are accessed. Commands and parameters are written into the GOG's FIFO and are differentiated based on
address bit AG. The status register or the FIFO can be read
as selected by the address line
READ

WRITE

STATUS REOISTER

PARAMETER INTO FIFO

'0

I

I

!

I

FIFO REAO
,

!

!

!

!

!

!

I

I

I

!

COMMANO INTO FIFO
!

I

!

!

!

!

!

!

GDC Microprocessor Bus Interlace Registers

Commands to the GOC take the form of a command byte
followed by a series of parameter bytes as needed for·
specifYing the details of the command. The command processor decodes the commands. unpacts the parameters.
loads them into the appropnate registers within the GOC.
and Initiates the reqUired operations
The commands available In the GDC can be organized
Into five categories as described In the follOWing section

GDC Command Summary
Video Control Commands
1. RESET: Resets the GOC to its idle state.
2. SYNC:
Specifies the video display format.
3. VSYNC: Selects master or slave video synchronization mode.
4. CCHAR: SpeCifies the cursor and character
row heights.
Display Control Commands
1. START: Ends Idle mode and unblanks the
display.
2. BCTRL: Controls the blanking and unblanking
of the display.
Specifies zoom factors for the display
3. ZOOM:
and graphics characters writing.
4. CURS:
Sets the position of the cursor in
display memory.
5. PRAM:
Defines starting addresses and lengths
of the display areas and specifies the
eight bytes for the graphics character.
Specifies the width of the X dimen6. PITCH:
sion of display memory.
Drawing Control Commands
1. WOAT
Writes data words or bytes into display
memory.
2. MASK:
Sets the mask register contents.
Specifies the parameters for the drawing
3. FIGS:
processor.
4. FIGO:
Oraws the figure as specified above.
5. GCHRO: Oraws the graphics character into display memory.
Data Read Commands
1. RDAT:
Reads data words or bytes from display
memory.
Reads the cursor position.
2. CURD:
Reads the light pen address
3. LPRD:

DMA Control Commands
1.0MAR: Requests a OMA read transfer.
2. OMAW: Requests a OMA write transfer.

71_1

5

1_1

II I

3

1

2

1'1

0

1

1'- - - - - - ~~::;~:~:~
_

L-_ _ _ _ _ _ Drawing in Progress
DMA Execute

L------------VefticaISyncAc1lve
Horizontal Blank Active

L - - , - - - - c - - - - - - - - - - - L 1 g h l Pen Detect

Status Register (SR)

Status Register Flags
SR-7: Light Pen Detect
When this bit is set to 1, the light pen address (LAO)
register contains a deglitched value that the system microprocessor may read. This flag is reset after the 3-byte
LAO is moved Into the FIFO in response to the light pen
read command.
SR-6: Horizontal Blanking Active
A 1 value for this flag signifies that horizontal retrace blanking is currently underway.
SR-5: Vertical Sync
Vertical retrace sync occurs while thiS flag is a 1 The vertical sync flag coordinates display format modifying commands to the blanked interval surrounding vertical sync.
ThiS eliminates display disturbances.
SR-4: DMA Execute
This bit is a 1 during OMA data transfers.
SR-3: Drawing in Progress
While the GOC is drawing a graphics figure, this status bit
is a 1.
SR-2: FIFO Empty
This bit and the FIFO Full flag coordinate system microprocessor accesses with the GOC FIFO. When it is 1, the
Empty flag ensures that all the commands and parameters
previously sent to the GOC have been processed.
SR-l: FIFO Full
A 1 at this flag indicates a full FIFO in the GOC. A 0
ensures that there is room for at least one byte. This flag
needs to be checked before each write into the GOC.
SR-O: Data Ready
When this flag is aI, it indicates that a byte is available to
be read by the system microprocessor. This bit must be
tested before each read operation. It drops to a 0 while the
data is transferred from the FIFO into the microprocessor
interface data register.
FIFO Operation & Command Protocol
The first-in, first-out buffer (FIFO) in the GOC handles the
command dialogue with the system microprocessor. This
flow of information uses a half-duplex technique, in which
the single 16-location FIFO is used for both directions of
data movement, one direction at a time. The FIFO's direction is controlled by the system microprocessor through
the GOC's command set. The microprocessor coordinates
these transfers by checking the appropriate status
register bits.
The command protocol used by the GOC requires the differentiation of the first byte of a command sequence from
the succeeding bytes. This first byte contains the operation
code and the remaining bytes carry parameters. Writing

into the GOC causes the FIFO to store a flag value alongside the data byte to signify whether the byte was written
into the command or the parameter address. The command processor in the GOC tests this bit as it interprets the
entries in the FIFO.
The receipt of a command byte by the command processor
marks the end of any previous operation. The number of
parameter bytes supplied with a command is cut short by
the receipt of the next command byte. A read operation
from the GOC to the microprocessor can be terminated at
any time by the next command.
The FIFO changes direction under the control of the system microprocessor. Commands written into the GOC
always put the FIFO into write mode if it wasn't in it already_
If it was in read mode, any read data in the FIFO at the time
of the turnaround is lost. Commands which require a GOC
response, such as ROAT, CURO and LPRO, put the FIFO
into read mode after the command is interpreted by the
GOC's command processor. Any commands and parameters behind the read-evoking command are discarded
when the FIFO direction is reversed.

Read-Modify·Write Cycle
Oata transfers between the GOC and the display memory
are accomplished using a read-modify-write (RMW) memory cycle. The four clock period timing of the RMW cycle is
used to: 1) output the address, 2) read data from the memory, 3) modify the data, and 4) write the modified data back
Into the Initially selected memory address. This type of
memory cycle is used for all interactions with display memory including OMA transfers, except for the two clock
period display and RAM refresh cycles.
The operations performed during the modify portion of the
RMW cycle ment additional explanation. The circuitry in the
GOC uses three main elements: the Pattern register, the
Mask register, and the 16-bit Logic Unit. The Pattern register holds the data pattern to be moved into memory. It is
loaded by the WOAT command or, during drawing, from the
parameter RAM. The Mask register contents determine
which bits of the read data will be modified. Based on the
contents of these registers, the Logic Unit performs the
selected operations of REPLACE, COMPLEMENT, SET, or
CLEAR on the data read from display memory.
The Pattern register contents are ANOed with the Mask
register contents to enable the actual modification of the
memory read data, on a bit-by-bit basis. For graphics drawing, one bit at a time from the Pattern register is combined
with the Mask. When ANOed with the bit set to a 1 in the
Mask register, the proper single pixel is modified by the
Logic Unit. For the next pixel in the figure, the next bit in the
Pattern register is selected and the Mask register bit is
moved to identify the pixel's location within the word. The
Execution word address pointer register, EAO, is also
adjusted as required to address the word containing the
next pixel.
In character mode, all of the bits in the Pattern register are
used in parallel to form the respective bits of the modify
data word. Since the bits of the character code word are
used in parallel, unlike the one-bit-at-a-time graphics drawing process, this facility allows any or all of the bits in a
memory word to be modified in one RMW memory cycle.
The Mask register must be loaded with 1s in the positions
where modification is to be permitted.

A4-3

The Mask register can be loaded in either of two ways. In
graphics mode, the CURS command contains a four-bit
dAD field to specify the dot address. The command processor converts this parameter into the one-of-16 format used
in the Mask register for figure drawing. A full 16 bits can be
loaded into the Mask register using the MASK command.
In addition to the character mode use mentioned above,
the 16-bit MASK load is convenient in graphics mode when
all of the pixels of a word are to be set to the same value.
The Logic Unit combines the data read from display memory, the Pattern Register, and the Mask register to generate
the data to be written back into display memory. Anyone of
four operations can be selected: REPLACE, COMPLEMENT, CLEAR or SET. In each case, if the respective Mask
bit is 0, that particular bit of the read data is returned to
memory unmodified. If the Mask bit is 1, the modification IS
enabled. With the REPLACE operation, the modify data
simply takes the place of the read data for modification
enabled bits. For the other three operations, a 0 in the modify data allows the read data bit to be returned to memory.
A 1 value causes the specified operation to be performed In
the bit positions with set Mask bits.

The table below summarizes these operations for each
direction.

Figure Drawing

dAD will always be 1. so that the EAD value will be incremented or decremented for each cycle regardless of direction. One RMW cycle will be able to effect all 16 bits of the
word for any drawing type. One bit in the Pattern register is
used per RMW cycle to write all the bits of the word to the
same value. The next Pattern bit is used for the word. etc.
For the various figures. the effect of the Initial direction
upon the resulting draWing is shown below:

The GDC draws graphics figures at the rate of one pixel per
read-modify-write (RMW) display memory cycle. These
cycles take four clock periods to complete. At a clock frequency of 5MHz, this is equal to BOOns. During the RMW
cycle the GDC simultaneously calculates the address and
position of the next pixel to be drawn.
The graphics figure drawing process depends on the display memory addressing structure. Groups of 16 hOrizontally adjacent pixels form the 16-bit words which are
handled by the GDC. Display memory is organized as a linearly addressed space of these words. Addressing of individual pixels is handled by the GDGs internal RMW logic.
During the drawing process, the GDC finds the next pixel of
the figure which is one of the eight nearest neighbors of the
last pixel drawn. The GDC assigns each of these eight
directions a number from to 7, starting with straight down
and proceeding counterclockwise.

Whole word drawing is useful for filling areas in memory
with a single value. By setting the Mask register to all1s
with the MASK command, both the LSB and MSB of the
OPERATIONS TO ADDRESS THE NEXT PIXEL

DIR

EAD· P-EAD

000

P - f EAD

EAD

001

dAD (MSBI

1 EAD

1 ---0 EAD

dAD-o LA

010

dAD (MSB)

1 EAD· ! _EAD

dAD ..... LR

01 1

EAD

P ..... EAD
1 EAD

dAD IMSBI

100

EAD

P ..... EAD

10 1

EAD

P

,'0

--0

EAD

1 EAD

1 ---0 EAD

dAD _

dADILSBI

1 EAD

1 -EAD

dAD ..... RR

1

dAD ...... RR

"" " .. , ','.

ARC

000

, EAD

LCL
.

.'

,

-0

EAD

CHARACTER SLANT CHAR RECTANGLE

~""

001

,,

r'l
" "1"

r

.\.~\,.

(

~

[.-:;---

r~/A ,

-

---

"0

'/;:;/
)

Figure drawing requires the proper manipulation of the
address and the pixel bit position according to the drawing
direction to determine the next pixel 01 the figure. To move
to the word above or below the current one, it is necessary
to subtract or add the number of words per line in display
memory. This parameter is called the pitch. To move to the
word to either side, the Execute word address cursor, EAD,
must be incremented or decremented as the dot address
pointer bit reaches the LSB or the MSB of the Mask register. To move to a pixel within the same word, it is necessary
to rotate the dot address pointer register to the right or left.

A4-4

."

--'--.

°

Drawing Directions

AR

P ..... EAD

EAD

,... "., ..

dAD .... LR

dAOILSB!

dAOILSBI

.\"",.:

1 ..... EAD

-~

7'"'

~0~.. ~'\~.

~'~0

£'07

c:,'7

/1, ' /1 t/

----- -

r'

C'::-_~

?=?3 =~

--------"-

~

/'

<,/

l
('

".

,,/

Note that during line drawing, the angle of the line may be
anywhere within the shaded octant defined by the DIR
value Arc drawing starts in the direction inrtially specified
by the DIR value and veers Into an arc as drawing proceeds An arc may be up to 45 degrees in length. DMA
transfers are done on word boundaries only, and follow the
arrows indicated In the table to find successive word
addresses. The slanted paths for DMA transfers indicate
the GDC changing both the X and Y components of the
word address when moving to the next word. It does not
follow a 45 degree diagonal path by pixels.

Drawing Parameters
In preparation for graphics figure drawing, the GDC's
Drawing Processor needs the figure type, direction and
drawing parameters, the starting pixel address, and the
pattern from the microprocessor. Once these are in place
within the GDC, the Figure Draw command, FIGD, initiates
the drawing operation. From that point on, the system
microprocessor is not involved in the drawing process. The
GOC Drawing Processor coordinates the RMW circuitry
and address registers to draw the specified figure pixel by
pixel.
The algorithms used by the processor for figure drawing
are designed to optimize its drawing speed. To this end, the
specific details about the figure to be drawn are reduced by
the microprocessor to a form conducive to high-speed
address calculations within the GDC. In this way the repetitive, pixel-by-pixel calculations can be done quickly,
thereby minimizing the overall figure drawing time. The
table below summarizes the parameters.
DRAWING TYPE
Inhlal Value'

DC
D

02

01

•

-1

OM
-1

Lin.

1b.11

21401 - IAII

2(1"'01-1011)

21.1.01

Arc"

r sin Ot

,-1

2(,-1)

-1

rsin 61

A-1

.-1

-1

A-1

R.ctangla

Ar•• All

.-1

Graphic Characte,' ••

8-1

A

R.ad .. Write Data

W-1

DMAW

0-1

C 1

DMAR

0-1

C-1

(e-11/Z.-

• Initial valu •• lor the various parameter, are loaded during Ihe handling of the FIGS
op code byte .
•• eire", .r. drawn with 8 .rCI, ••ch 01 which apan 45°, 10 that lin 0
1(y"2 and
aln tl : O.
••• Graphic character. ar. a special case of blt·map area filling in which B and A .:;; 8.
If A ~ 8 there I. no n_d to load 0 and 02.
Whare:
-1 _ all ONES value.
All number. ar. ahown In ba•• 10 tor convenience. The GDC accepts base 2 numbers (2.
complement notaUon where appropriate).

=

-

&

.11

~

No parameter byte •••nt to GOC tor this parameter .
Tha larger at rut or .1y.

.10 " The smaller lit rut or .1y.
r " Radius at curvature, in plxeis.
• " Angle trom major .xls 10 end at the arc ..... 45 0 •
8 " Angle from major axis to atart at the arc. 8" 45°.
f " Round up to the next higher Integer.
• " Round down to the next lower Integer.
A '" Number of plx.ls In the Initially specified direction.
B ~ Number of pixels In the direction at right angles to the Initially apecified direction.
W = Number of worda to be accessed.
= Number of bytes to be tranalerred In the InlUally specified direction. (Two bytes
per word It word Iranafer mode Is ..Iected).
o '" Number of worda to be accessed In the direction at right angle. to the initially
apecltled direction.
DC '" Drawing count parameter which Is one less than the number of RMW cycle. to
be executed.
OM " Dots ma.ked trom drawing during arc drawing.
.. " Needed only lor word read •.

Graphics Character Drawing
Graphics characters can be drawn into display memory
pixel-by-pixel. The up to 8-by-8 character is loaded
into the GOC's parameter RAM by the system microprocessor. Consequently, there are no limitations on the
character set used. By varying the drawing parameters
and drawing direction, numerous drawing options are
available. In area fill applications, a character can be
written into display memory as many times as desired
without reloading the parameter RAM.
Once the parameter RAM has been loaded with up to
eight graphics character bytes by the appropriate
PRAM command, the GCHRD command can be used

to draw the bytes into display memory starting at the
cursor. The zoom magnification factor for writing, set by
the zoom command, controls the size of the character
written into the display memory in integer multiples of 1
through 16. The bit values in the PRAM are repeated
horizontally and vertically the number of times specified
by the zoom factor.
The movement of these PRAM bytes to the .display memory is controlled by the parameters of the FIGS command. Based on the specified height and width of the
area to be drawn, the parameter RAM is scanned to fill
the required area.
For an 8-by-e graphics character, the first pixel drawn
uses the LSB of RA-15, the second pixel uses bit 1 of
RA-15, and so on, until the MSB of RA-15 is reached.
The GOC jumps to the corresponding bit in RA-14 to
continue the drawing. The progression then advances
toward the LSB of RA-14. This snaking sequence is
continued for the other 6 PRAM bytes. This progression
matches the sequence of display memory addresses
calculated by the drawing processor as shown above. If
the area is narrower than e pixels wide, the snaking will
advance to the next PRAM byte before the MSB is
reached. If the area is less than e lines high, fewer
bytes in the parameter RAM will be scanned. If the area
is larger than e bye, the GDC will repeat the contents
of the parameter RAM in two dimensions, as required to
fill the area with the e-by-e mozaic. (Fractions of the
e-by-e pattern will be used to fill areas which are not
multiples of e bye.)

Parameter RAM Contents: RAM Addre.. RA
Oto 15
The parameters stored in the parameter RAM, PRAM,
are available for the GDC to refer to repeatedly during
figure drawing and raster-scanning. In each mode of
operation the values in the PRAM are interpreted by the
GDC in a predetermined fashion. The host microprocessor must load the appropriate parameters into the
proper PRAM locations. PRAM loading command
allows the host to write into any location of the PRAM
and transfer as many bytes as desired. In this way any
stored parameter byte or bytes may be changed without
influencing the other bytes.
The PRAM stores two types of information. For specifying the details of the display area partitions, blocks of
four bytes are used. The four parameters stored in each
block include the starting address in display memory of
each display area, and its length. In addition, there are
two mode bits for each area which specify whether the
area is a bit-mapped graphics area or a coded character area, and whether a 16-bit or a 32-bit wide display
cycle is to be used for that area.
The other use for the PRAM contents is to supply the
pattern for figure drawing when in a bit-mapped
graphics area or mode. In these situations, PRAM bytes
e through 16 are reserved for this patterning information. For line, arc, and rectangle drawing (linear figures)
locations e and 9 are loaded into the Pattern Register
to allow the GDC to draw dotted, dashed, etc. lines. For
area filling and graphics bit-mapped character drawing
locations e through 15 are referenced for the pattern or
character to be drawn.
Details of the bit assignments are shown on the following
pages for the various modes of operation.

A4-5

Character Mode

."cL::'
'I

[

0

0

0

~ l·"'lIlhofOI,pl.yP.rtltlonl

LEN1,.

(lin. count) with hlOh .nd

IiPi.\

GCHR8

GCHR7

PTN,

RA-l0

GCHR6

11

GCHRS

12

GCHR4

13

GCHR3

Poltemol,
••,,.u_l,,,
figure drawing
to pattern
dotted, ...hed, etc, lines,

10w·'enllle.ne.II,'dl.
... WIIM Ol.pl.y

c~cl.

'Of

.deI,.,.

The cll.pl.y
coun". I, Ihln
Incl'9m.nled by 2 tor ..eh dl.pI.y Kin eyel.
OIM, m.mory eye" typ. . .111 rIOt '"tlu.n~.

.".

0 01
LEN2,

WD2!

.".

t-

5A02,

o

0

I

SAD2 M

OItpl • .,. ""rtltlon 2
.tartlng!Kid,.... .nd

'"""~

15

GCHA 1

Command Bytes Summary

SYNC,

.nVlh

[ 0

D

I,

, 1DE 1

, 1,

, 1" 1

o

VSVNC:

~

CCHAR

E--;-~o

OIapl.yPJ.rtltloo :I
.t.rtlng addra.JI .nd

r-,

I0

0 0 0

START:

eCTRl:

OIspiay Partition 4

oj

lEN4l

'"""~

5A04>1

I

w"l 0 I

0

,

1

,

0

10

D

ZOOM:

' 1

'1

CURS,
PRAM,

,[

PITCH:

O! 0

LEN4,.

WOAT,

'1

01,

FIGS,

01,

FIGO,

o

...,..2
startIng IdcIreu Ind

t- Ief1gthwithllnllgeldentlty
DilaSln,rea 1

SA02 l

,I

I

0

o

I

DMAW:

A4-6

,

0

, 1

I'

, 1

TY,..

,

[

o

1

01

'I
0

MOD

0

1
0

I

01

0

SA02 H

DMAR:

"00

,

1
o

LEN2 ..

01

TYPE

I
o!

CURD,
LPRO:

SAD2 ..

1

01

ROAT,

0i~yPartition

TYP'

MASK,

GCHRO,

WD'IIM I

1

o 1DE 1

0

0 0

Graphics and Mixed Graphics and Character Modes

LEN2l

, ,I

t- starting itddress and

SA04 l

0

character drawing.

LEN3 ..

R.... '2

o

GCHR2

SA03,.

01

wei 01

14

RESET:

LEN2H

LEN3,

memory with graphiCS

)

0 0 0

I0

SAO:l c

0 0

L- ~r:';:,~\I~~~t:~~~

wldlh

ollwo word. per m.mory eyel,
I. 1.'~Md
thl. dl.pl.y
,",,1 thl. bit I. "I to. 1

I, 1
' 1

MOO

MOO

1
1

Video Control Commands
Reset

Modes of Operation Bits

~ r-o---------o~1

hnk1hldl~.m.r

-FlFO
- Commtlnd

- tnlemal

If followed by parameter bytes. this command also sets the
sync generator parameters as described below.
Idle mode is exited with the START command.
0

ole i I, I I
F

'"

0

AW

vs,

-

I

- - - - - _..

__
, ...,J}---vertlC81 Sync WI4

~___'n_~_"_d__-J)(~________

-JAA
AD:

D80~7, ---H:::,,:::h"7'm=......
==.-.---1K
I----------'ACV~------..,

Mlcroproce••or Inlerface DMA Wrlle Timing
2xWCLK:

AEa

DAEa,

~

------------------,,----------------------

'0.
I---------'E-----+----~

'.W

M:~roproce••or

'W.

Inlerface DMA Read Timing

2.WCLK:

DREQ:

t-'RE"i--/

~'OK

------'----{

~-

t---------".Q(R)---f . .

DACK:

080....7:

H.... _

--

A4-13

nmlng W.veforms (Cont.)
Display Memory Display Cycle Timing

2xWCLK:

Aoo,,-1$:

"'11, A17:

ALE:

~~~~.EF~i______xr___t_v~

>t-

~

LCO",,3

es.

CSR·IMAGE
AT BLINK - fIe

light Pen and External Sync Input Timing

2'WCLK~~PS
LPEN,
EX. SYNC:

' -_ _ __

tpW

Clock Timing

-r---",:----- VCH '" 3,'

2I1WCLK:

Vel" 0.5

Test Level (for AC Tesls)

==x

MISCELLAHEOUS'
.

A4-14

-0.'

2 . 0 _ T... Polnt- 2.0
0.'-

x=VOH . 2.
VIH '" 2.0
VOL
0.8
YIL

=

• 0.'

:::!

Video Sync Signals Timing

3

5'

II

IE

I..

2xWCLK:
H BLANK:

r1
r 1L-J
r 1L.. _______
....J1 1
L...Ir 1
LJ
L...I

lH
"I i=
J1..fUl....J1Jl ___ _..n...Il.J"-____ .JlJL ___ IL •iii

. J r - - - - - - - ------

----1' -______ ..Jr-

c;
0

~

H SYNC:
ADO-15:

LCO-4:

ADO-15:

LCO-4:

r

1H---t- __________________ - ------------------ ---::p:x==:_-_xpx~:::xra=::=:~ :-_-. ~~: :.-_ -_:=:._:. ~~_-_~~_~ ____--.JJ:Xr::~J::J:::.
J

±=.---.:t:=--.~.
I

ROW:

,X

---

-_...

- -- - - --- -- - -- - --- -- - - ~---=r:..

--

----------------------

~I

C

'
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ .J

I

-\t
ROW:

f--

~--.J\.----c:-:. ~ ~ ~ Jo._...--JX'---_ _ _ _ _ __

L

V BLANK:

--

_______-'

-------L

V SYNC:
I

1~4----------------------------------1V(FRAME)--------------------------------~..~I

nmillfll W."eform. (Cont.)

Inlerlaced Video Timing

t:::~:~~

HBLANK:
VBLANK:

l

VSYNC:
(INTERLACE)

-:-::: ::~: =t:. .~~_~:~~ iY-::--ff-:::
i'

: !

i-----ODD'FlELD

'

:L-

:1

i
i.

:

EVEN FIELD"';":- - -

______~--~__________r_~~

VSYNC:
(NO INTERLACE)

Video Sync Generalor Paramelers

~1.-------------------1H----------------~
HBLANK:

~r--------------1-

,
________________________________jr--

~~j______~------------------------------~-­

HSYNC:
I

,I

I

I

t- HBP -t----------- C/R ------------1

- j HFP . I

I

I

-lHSi~1·~------------------lV---------~.~1
VBLANK:

---:-----~-----------------J---~---~L-

VSYNC:

---fII------~-------------------------;,----~,
I
n

I

I

I

1

I

f-VBp-oo-t-1...- - - L / F

--,

-------<-1-1

I

I

,~----~-I

YFP 1-1

--iVS\---

A4-16

I

':-- YBP-1

Timing Waveforms lCont.)
DI.play and AMW Cycl•• (Ix Zoom)

bWCLK:

ALE:

D81.'~rl---------r--------+~-------+------~__~~__~---t-------t-t-------t----

A00-15:

.16,17:

VlEXT

:~:~:

HSYNe:

=tpC========!:t)C==================q:t:=====
-+________-x..
=t==J ,..------------i----'
-------================::t===x:::::=
X'-__________

Display and AMW Cycles (2x Zoom)

I

2xWCLK:

ALE,

ZooIMCl Display

I D'I D.-f-D'T D4

+

Zoomed Dlaplay

I

RMW

I DlapI.y or RMW

D', D'~ 03, D4-t-E'iE2f-E3iE4iE;CIO

~~'----rll~~-II'------------+-1
~
__~l__

_, I

-:----/---+-1---:--/----,~O-~P~J.

~15! ~-<::::::>---------------~-<::::::>---------------~-<::::::>---<:::::~~:::J')(::::::~

A1., 17:

BLANK:

~lxO~=p~=-=~-========~!x~=~=-=~u========~!x~=~=-=~-========~I::::

I

!

!,
A4-17

Zoomed Displey Operation wllh RMW Cycle (3. Zoom)
Di.pI~~FlMW

RMW
Cycle

.,

2xWCLK:

ALE:

DIDN,~--------------~-----------------------+----------'
I

I Oulput Address

Output Address

Input Oal.

Output Oat.

Output Addr •••

AD~15:~-C======r------------------------------+~====~--~~====)-<=====)-----------~<=====J-

VI.... Field nmlng

rt-

HSYNC OUTPUT

~

BLANK OUTPUT

.......-----+-----:-.=RTIC=:-:A:-L-::
.
••"::"N"C"'L...
=.:--------------k---'------

HORIZONTAL

~~E-

M

t
~

HORtZONTAL
BACK PORCH
BLANKING

~

~

HORIZONTAL
FRONT POACHBlANKING

ACTIVE
DISPLAY
UNES

~~,

A4-18

VERTlCAL BACK POACH BLANKED UNE5

.,

VERTICAL FRONT PORCH BLANKED LINES

I"
z

~

Drawing Interval.

DRAWING INTERVAL

ADDITIONAL DRAWING INTERVAL WHEN IN FLASH MODE

DYNAMIC RAM REFRESH IF ENABLED, OTHERWISE
ADDITIONAL DRAWING INTERVAL

DMA Reque.t Interval.

OMA REOUEST INTERVAL

ADDITIONAL DMA REoueST INTERVALS WHEN IN fLASH MODE

A4-19

Pin Identmcatlon

....
No.

S'-'

11

DI.-"'"

Function

'N

Clock Input

!iiiiN

OUT

Dtaplay Memory Read Input Fllg

HSYNe

OUT

Horizonta' Video Sync Output

WEXT SYNC

INIOUT

VertlCIII Video Sync Output or Extema' VSYNC Input

CRT Blinking Output

2xWCLK

,.

Pin Configuration

BLANK

OUT

ALE (A"'S)

OUT

Add,... Latch Enable Output

ORO

OUT

DMA Reque.t

DACK

'N

DMA ACknowledge Input

"0

'N

Read Strobe Input

ViA

'N

Write Strobe Inpll1 tor Mlcroproceuor Intertlle.

A.

12-11 DRO 10 7

2.

GND

21

LPEN

Outpu~

'Of Mlcroproc...or Intertace

'N

Add,... Select Input for Mlcropt'oceuor IntertKa
Bidirectional Dlta Bu. 10 HOlt Mlcropt'oceuor
Ground

Light Pen D.tect Input

22-34 ADO to 12

INIOUT

Addr... end Date Line. to Display Memory

3S-37 AD13 to 15

INIOUT

Utillution Ve,l.. with Mode ot Operation

3.

Al.

OUT

Ulillation V.rl•• witt-. Mode ot Operation

39

A17

OUT

Utilization V.rl•• with Mode of Operation

4.

Vee

+5V t 10~

Character Mode Pin Utilization
PIn

No.
35-37

N.....
A013 to 15

DltlHtlon
OUT

Function
line Counter Bit. 0 to 2 Output.

3.

Al.

OUT

Line_Counter Bit 3 Output

30

A17

OUT

Cur.or Output

Mixed Mode Pin Utilization
pt-

No.

Functton

35-37 AD13 to 15

INJOUT

Addr... and Data Btt. 13 to 15

38

A16

OUT

Attribut. Blink .nd cte.r Lin. Count.r' Output

39

A17

OUT

Cur.or .nd Bit-Map Ar •• • Flag Output

• ; Output during the HSYNC Interval. Use the trailing edge at
HSYNC to clock this value into a flop for reference during the rest of
the video line.

Graphics Mode Pin Utilization

....

No.
35-37

A4-20

N .....

DlrlHtlon

AD

Wli
AO

INIOUT

'N

2xWCLK
OBIN
HSYNC
V/EXTSYNC
BLANK
ALE
OFia
OACK

Function

A01310 15

IN/OUT

Addt... and Data IMt. 13 to 15

31

Al.

OUT

Add,... Bit 16 Output

3.

A17

OUT

Addr... Bit 17 Output

O~

0801
0802
0803
0804
0805
0806
0807
GNO

vee
1.017
1.016
A[)'15
A[)'14
A[)'13
A[).12
A[)'11
A[).10
A[).9
A[)'8
A[)'7
A[).6
A[)'5
A[).4
A[)'3
A[)'2
A[).1
A[)'O
LPEN

Block Diagram of a Graphic. Terminal

Package Outline.
I-IPD7220D

I-IPD7220C

A _ _ _ _ _ _ _ _ __

1

K

._

_.;r-~=~-~\.....

-

-- M
0° - 15°-

-

Plastic

o
~------·E

Ceramic

ITEM

MILLIMETERS

INCHES

A

51.5MAX
1.62 MAX
2.54 ' 01
0.5· 0.1
48.26 ' 0.1
1.02 MIN
3.2 MIN
1.0 MIN
3.5 MAX
4.5 MAX
15.24TYP
14.93 TYP
0.25 . 0.05

2.03 MAX
0.06 MAX
0.1 . 0.004
002 ' 0.004
1.9 . 0.004
0.04 MIN
0.13 MIN
0.04 MIN
0.14 MAX
0.18 MAX
06 TYP
0.59 TYP
0.01 ; 0.0019

B
C

D
E
F
G
H
I
J
K

L
M

ITEM

MILLIMETERS

A

515 MAX

INCHES
2.028MAX

B

1 62

0064

C

254 ' 0 1

0.10' 0.004

05'01

0019'0004

0
E
F

48.26

19

1;> MIN

0.047 MIN

G

254 MIN

0.10 MIN

H

05 MIN

0.019 MIN

r

5.22 MAX

0.206 MAX

J

572 MAX

0.225 MAX

K

15.24

L

13.2

0.600
0.520
, 0.1

M

0.25

0.05

0010

• 0.004
0.002

A4-21

Appendix B

Logic and Schematic Diagrams
The APe logic and schematic diagrams are arranged in drawing number sequence.

B-1

-:= -:--:-

,--------- ------ - ------------11- I

02:~0'
t

I
r------'A::.o1-oF1

11

T

CIT

1

====

r.LC2

______

1

f ••• '

3

-+--S>'
I
IL

I

j

2

- - -'

'----

CNI

F~ r--'-----

1i7

--

>

R,~'D.

R4

R45

-H

02~~l

T

T

V~I~

-=c::--,::+

,...1--

R12

~

!oR13

=i= ~

R14 C17

~:::'Cll

01

=O~

'II

~

+24 V

: t>3 1+12V

~

I

II

qi::.~/I+5V

7

t--------'--.~

..,

15,

,

II

8

J,

T
R2

CI6-L:,:

'

.5

'T

05...

IN

~-'-lIII...
I-----+-'"

.l
+C1D
OUTT-

I

1I
r

I

K

.2'5

Z3

",,0:,::.6.
"'J*-...~R",'",'_ . _ - - - - - .

...L.~2}

rl--.._VV'lr' R39

5. --

l~

---<

I

Z6

IL

4

T- CI8

".

R16

, . 019

-r:'-'=+,-,- - -.....- - - . .

2

.... J

I

R18 R19
,,':
-A'V'

R40

I
A

,A

~

H

".;'ll

I II

'2 V

I "

ti!,ID4 SG

161
I
I '
"5

I

L ,

~7> vv

"1-

I

81

R23, I

R2D

I - 12,

I

I

>

4/-5 V

.--cro-:-------.---PiH>V,,2 I

R43

~----+-t--+--+-+--t---.--

~ - ~~---1I

t- - -

«RI7

±

II"""..L+

I

~

r

6

"~

'N

AIM

C8

rCN2
,

I

II

I

R22

r

I
POF

Ii
I

v

1

ACOUT

r---<>"---f--l> 9 ---.J

::......-': R21

L.:. J

I
R44

I

R42

9

-H15

I' k 1

I

RVI

C26

I

I

~~

T

[lli

t,t
I
I

.!!L

R9

-D

08

T 1~9"'L..ooII~~ ,~6T~

,

!

N.....

R3

~~07

':6+

I

p .....

ACIN

C~ _

,

I,

r--

~

~C7

12

T

i ~-I:
I [~ 18.1.
~, JJI T

:

>Rl

II"""

-------~~-

r

5
~,-

Z5

- -

- l R24

t-L__\ 1
__"...1

1

I

L -+

L::J L_.

~~

'-"~J\R4J\'·{,-----.

6

l

2

~

I

R25

R28
~--,

{:..4_

07

:./"

IT'J-L

C21

02~~l T- :':

,

IZ
3

Y

I

-

16

r:::!~
C28-,

"R26
I ... I
'----+_____VRV27......~+1-<:;tf15

'

I,

>R3D

I

-L C29

--r
R29

~ _J >

R31

R32

I

----------------------------------------------~
136-100430-202-A
H Type Power Supply Circuit Diagram

B-2

Sheet 1 of 1

C1
+5V

C2

5G

5G

C20-3.3U,C21 TO C23-~

C11 9 C18-2200pF
00

a;

'"~~ '"

'"

°0

O~

a;

a;

~~

~~

'"

ON
~~

a;

'" a; '" a; '"
0",
~~

0",
~~

0",
~~

a;

~

'"~

U

1:~I ~I
U

U

o:r

2+

m-"

+5V

CN1-24

U

SG

34 P14
33 P16
32 P15
31 P14
30 P13
29 P12
28 P11

R1

000

27

27 P10
01 TO 015-15597
8048

+5V

5G

~ ;!

74159
X32

17

a;

15

A 23

14

B 22

22 P21

21 P20

INT

6

55

5

R7

+5V

OP1

1K
X31

OP2
OP3

'"

u

0.111

X30

15

13

C 2120

23 P22

X29

14

12

0 18

24 P23 P27 38

5G
R2
05TB
27
R3

X28

13

G1 19

11

P26 37

PBSTB
27

X27

1

10

G2

R4

P25 36

5G

5W5TB
27

X26

9

X25

9

X24

8

Z3

X23

X22

X1

TO

X2

T1

8

5G
39

7
L5244
17 1A1 1Y1
15 1A2 1Y2

6
6

X21

X20

4

X19

3

5

OB7 19
086 18

4

OB5 17
OB4 16
OB3 15
082 14
5G

2

507

13 1A3 1Y3
11 1A4 1Y4 9
8 2A1 2Y1 12

506
505
504

6 2A2 2Y2 14
4 2A3 2Y3 16
2 2A4 2Y4 18

OB1 13
OBO 12

+5V

508
5

CN1-5

503
502
501

Z2
X18

X17

40 VCC

2

T~FG

26 VOO

0

5G

136-100430-206-A

1U
7 EA

20 V55

5G

Keyboard Circuit Diagram
Sheet 1 of 1

B-3

I'"

,

;co-",
14 _7456Ml1Z

9

,

LS04

~
~ CP

"

5A

10

MS

13

MR

LS74
3A

1

LSOO
3G

3

1

,

LS04

CP371(2)

[::/

FO

!"

8288
(BUS c~-,

"

3

(4 )ClK02

"

RST01 (9)

":1,-

R6+~
10K
5954

C20

::::TI

I

8284
CLOCK
REs
RESET

1U

"

C6---L

",
'" ,

d" ""

22U

CS06 E1C220M8S

~"
"

(4 )ROY21
XOOO

~RSTOO(2'3'4'7'8'9'10'9)

(4)X102

I-

READY

" '"
~m
----'

F";

OSC

PCLK

CSYNC

~

ROY1

~

AEN1

,

51 - "

0$0

"

"IOWl.·

"

AMWc

xooo ....

"

."

~

'"

AEN2

G"~

MNiMx'

" '"'

II

,

30

"

INTR

2200P

"
31

l!&:!.!1-

30

2)RQG10

"i'ES'F

RQ/GTO

RQiGTi

2)STB01

OTR 01(7)

DT/R

ALE~

w,

DEN

3

3

9

9

S

C
0
3
F
F 39

ALE 01(7)

"

16

"
~~

VCC~+5V

,, lS373
,
n
"" 3M
"
~.:)..l G
P
" '"
1

TIMER

'"3

KR

I

8)IRQ61

VCC~+5V

PClK1(2,9)
82"8A
IRO INT
~=i eTR

" ,

1)INTAO

I

1 )AS011

3

,,
,
"'
""
"
3

""
,
,,

,"0

~

9

,
S

~3
, "

'" "

, "w,
r

(1 1 )CITHO

HITA

00
01

""
"05
""

,"o~

L-

CASO

"
os

CAS1

~ 7

2)IDWOO

AB 111(3,5)

OOA

8)IRQ81

8)IRQB1

AB 101(3,5)

G

L.f1G

-

8)IRQ91
8)IRQA1

3l

S

9

,
""
"

AB 161(2,5,7)

f-1L--

Fo

lS373

f--'<~
3

GND~

9)IRQ71

"

AB 081(3,5)
AB 091(3,5)

1III

AD 041(3,5,8,9)
AD 051(3,5,8,9)

~

A0081(2,3,5)

~

A0091(2,3,5)

AD 061(3,5,8,9)

~

A0101(2,3,5)

AD 071(3,5,8,9)

~

A0111(2,3,5)

~

A0121(2,3,5)

~

A0131(2,3,5)
A0141(2,3,5)

~

;." A0151(2,3,5)

136-100430-50O-A
G9PFBU PCB Circuit Diagram

Sheet 1 of 11

(1)AB001
(1)AB011
(1)AB021
(1)AB031
(1)AB041
(1)AB051
(1)AB061
(1)AB071

~

9L-

4

40

1

"

"00

'"

"
""
'"'"

.""

~

"

' "'
(1)CP371

7

!>-------,

!>---t

(11 )COMAO v
(4)ROY21

ORO'

DAC~l

ORQZ
ORQ3

OACK2

C221
==

_

DACKJ

,
'" ,

(1)A010

'"me ",

AE371(1, 7. 11 )

'"
vcc~+sv

~

GNDf1-

El
10

40

~~

(3)AOO03
(3)A0013

(1)PCLX 1

~

IIF .

elK1

CLK2
GA12

,

C21 fO.,U

(11)CTIMa

"
~ ~~

I~

(1)R5TO a

1

00

1

+5V

io,

MR

31 ~~

t:::=::D1 ~s
1

1U

11

13

--

I1R

12

vcC~+5V
GN0tl_

(11)COMRO

LSDD
3G

LS32

4P

Fa

1~ ~~
Ir=;=~r'""
4P

I

g~

A8161(1 5.7)

10

~

AB171(17,11)
AB181(1, 7,11)

4H "

\

~

'r-

__

,
,
" "

LS10

(11)CTMR1

,

~~i;':;'
lS08

, "

3

6

SP

,
,

lS08

"

,

1

Mfl

J

-v

IRQ31(1)

"

7V

>0

~,
, "

1

I~

, "
~

A8191(17.11)

"

'"

"

"

LS74

AO~

f-~
,

XNU

1217

4b'

FO

~

lRST ~

11
fiE
~\fjE

~

T5I11(7)

(1JIOWCO

I

24

10

L-

3CPlS74:[
~~S5N

R13 r'K

Til

~
L---

,

:~~l RFSH
TC ;m;

B7

~:i
" '"

GAT1

1K

L 15

1E as

2

GATO

R8

~

, 'ls67iJ
, "g;
,

-

C>-;

(3)A0023
(3)A0033

CLKO

+5V

"6

~~

g~

1

(1)A015 1

1

-1Z ... 7

OACK1
OACK2

~~DACK3~

~EO

t---c> AE373( 11.4,7)

~

~~ ~4

8!;

":~

'' ""'
"'

(1)A013
(1)A014 1

4:~

(4 )RF5H1

g~

7

MR001(5.11)

~K0.....fli3l

+5V

'82S3=5
,

WROO(7.3)

MW001(4)

'LS24O ~

10K

FDINPQ1H102K

OWOO(1, 7 ,9,11)
OROO(1,4,7,911)

MROOO(4,5,7,11)

"

:-l> AE370( 4. 11)

" RZ

L----=1000P

~~

~

5TB01(1)

(1)A008 1

(')A01' 1
(1)A012

~

t-

~,

XOOO
(1)A009

AJJ

A7

~:

10K

,,
,"

DACKa

A6

'"--

1
10K 1
10K T

2F

17
1

ROY

R7

A5

CO

~El

~

1

6

(1 )MWTCO
(1 )MROCO

'

'"
'"
'"
~

A3
A4

"il

XDOOl>--+5V
10K

~

DAOO

11

R9
R11

A1...fiTo1
A2

J

1H~

,
'" ,,
'"

19

" cs'"

,"
"

.,"

HLDA

" '"

R10

(1)AIWCO
(1)IORCO

,
,",
,

L'<'

15

3237-5

(8)OR021
(8)OR031

,

~

~

(8)OR001
(8)OR011

40

-XOOO~11
1J

~h

~
, "

ROG10(1)

136-100430-500-A
G9PFBU PCB Circuit Diagram
Sheet 2 of 11

B-5

(1.10)ADOO1

,
,"

I>

(1.10)AD011
(1 )AD031
(1)ADD41
(1)ADOS1
(1)AD061
(1 )AD071

II

LS245

""
""

(1 )AD021

(1)AB031
(1)AB011
(1)AB041
(1 )ABOS1
(1)AB061

~~~~~~~~~~]~Tr~~!!!!]' :i~ g~f*=

IJ

III

co

~

g; ~

<4:
,

'

XOOO

I

:;

,

~SO

"no 10Le-"

(1 )AB021

--(R34l

4

1:......--

JL'361

=

~

'"

!6:l~I"~~aMli
D7~17

2H

1.7

U4
R35
U5
R36

::

1

(1)AB071
(1 )AB081

A10

~~

~~1

18

C52

(1)AB091 [ > - - - - - - - - - - - - - - - - - - - - - - - - i t t t t t t r ;
(1)AB101[>------------------------itttttt~

(1)AB111 [>--------------------------rHrHrHrHrr;
(1)AB121 [ > - - - - - - - - - - - - - - - - - - - - - - - - i t t t t t t H r H h
(11)BMMSOD-------~~--~,

A0003(2. 10)

~;~32

.

I

)3
2~

rv'i2A

657"""
34"""
8

,
, ""
" '"
'"
2

,1..6

"
D4D5D3
D6D7

D2

2J

3

2

,
""

00

"

8

""
"'6

,g

~

~ r--cs244

,""

"
,""

A0033(2.10)

57

3C

"

A0013(2. 10)
A0023(2.10)
AD043( 10)
AD053(10)

3

qED
19

AD083(3.7)

E1

~

VCC~"'5V

00

CE
(1)AB001[>--------r~~-----------ittttttttHrr__t_t_rt_~~~~~
GND~

I~_'g'_/1~}28
____~~~++++++4_--~
r_+---i,,:32

'>

rz7'3'2A

~:~

•
•

6
5
4
3
2

"'2
A3
A4
A5
A6

22

A9

zi:~

g~;D

2L

02
D3
04
05
06
07

11
13
14
15
16

r-1Z---

:

~; ~~

~==~=h~=====~=~~~~~ti===l=ri,~
~
~~~

(11 )ROMSO
(7)HBNKO [:;

DE

vee

---5',1

~}2'~,----rtrt++++++4---_,

~

~
5

~~32

6

I

6,1..2
5 A3

0211
03 13

;

A4

04

22

A9

zj2:~
:~
19
21

(1 )AD081
(1 )AD101
(1)A0111
(1 )AD121

III

(10)VRAM

2M

14

g:~

07rll------

"'10
WE

~~ ~~~

(10)BMCSO

(1 )AD091

mm

.171:;010Le_~Jj"

I>----+-~------------------------+-----~.. .~

,

""
"
"""

(1)AD131
(1)A0141
(1 )AD151
(2)MWROO

"

1>-------------------------~r------'~ICS32
"
12

(11 )BMMEO
(7)X101
(1 )RSTOO

CP LS74
MS 3P
MR
FO

1
(11 )DMACO [>--------'1

2

8

8

9

LSOO
IL

LSQ2
5P

5

,

IK

8
9

136-100430-500-A

G9PFBU PCB Circuit Diagram
(11)MPROO,~13
LSOO
~'~'______~
12
IL
,....
(11 )OMECO

B-6

4
6

1: 1 - - -

1
I
g:=========~~~~~~'~2~~:::b9~--~===~
I
11
10
13

2
3

XOOO C>-__~r--;;;-'---"'9'_q1 ~g
' -_
-0,
_-

2P

I
(3)AD083

L::'''4::'

Sheet 3 of 11

...-----1> X102(1,10)
0.

DL1

4
TO
T1 5
T2 S

XOOO :>I>-----+-~----.,SHOA

O

~~:

TO
T1

LO

~~

t:::::::t 3.
9

Ho ~~

+-+~~
I

CT

XOOO .D
. . _ _ _I-+-...--'R~
OA
~~:
+ V

R30

8

OA
CS

..lL--

~~~
150

+5V

I

LS1.06661 I

1K

LS37
SW

9

T4 12
T5 11
TS 9

R32

SP

CNF

~~

-----f LS244 '~.

9

LD

T3

10

~~ SN

TO

4

T1

5

LSOO
SU

S

4
~

T31-I Sfi':i4~_ _ _ _ _ _3=4LS04
200ns T2
~ ~
~
TS 9
7W

5

f---t- ~~

10

LS1S1

CNF

~

I

+5V

L.l

~R25

9
10

O. 1U

CT

OA
1A
2'
3'
LD
EP
ET
CP
MR

LSOO

8

6U

RM9
~~_==;,

T33
I

XOOO~D------t----~--~====~------~

±

.... CASOO(S)

R1:33' SG

~

C41

ASLHO(5)

V

33

330.r.

9
(1 )AB002 I>-----------if----....!'!.I

1K

R31

4
5

NDLZOON101H2

OA

~

156M

14

DL2

~

RFA311(5) (2)MW001 "vl>--+-~--"-l4
LS37
S
2 CS
~~r-,
::: RFA211(5)
5
SW
~---~.~~~ I 330
RFA11(5)
+5 V o.,NIJ'-'4¥<-Q SG
RSO
R61
RFA01(5)

14
12

~j

OA

RFAS11(5)
RFA511(5)
RFA411(5)

. __

~

~~~~~~Is
TO~~

3A

t:::::I

~

11
12

2

~~

NDL 100N101H2 T3

100ns
SV

1 lS04
7V

LS1S1

I,.

CNF

I ~ ,.
LJ

CT

15

TO
T1
T2
T3

i~

~"i5

13
(7)HBNK1 1>----------.ll.I
...

133

6U

0.

TO
T1
T2
T3

11
12
13
14

2.
3'

9

6Q

r---+
t--+-t-.1 - - - - - - - . . . J
(6)MR04 1

11::
SA

(S)MRDS ....

17 7A

,[ > - - - - _ - - - 'I II

d

.....

(6)MR06 1~

EO

L-_ _

T214
T312

TSS

(11)MRLB
(2)MRDD

19

1W

MWOS1(6)

7

8

j

MWD71(6)

MPELO(7)

MWPL 1(6)

RM5 33

r-_ _ _.!<1~~
3R

MW081(6)

. L5244
- - 18

r -_ _ _ _ _ _~1--'2'1

1E~4

1,r---t-=13--'1N'<-=-4!-1--(> MWD91(6)
I5
S I

r
~'Sm~
~4

1R

9

~~

~

17

3

1~' ~~
(11)RAMSOI>--+-_H++-If-++I-_ _h_,;ct

(1)A0091~1>---------,

6

(6)MRPL 11>-_ _ _ _ _-"'~"ILS08

E1

11

(1)AD081;...1>----------~

j

5

TD~..!L
R _ _ _ _ _ _ _~"'R4fV_----i>

S

~----------~

MWD41(6)

I

33

~::
~--------------------------------~++~+-------~

(2)MRDOO,;:
......
(11)BE'COI>-----------,

4

I
I
1'----i--.JWv-.:...r---t>
MW061(6)

3

(6)MRD7 1
I>--------------------JI

3

~~8~~~5~--------------i>
9
10
11
12
13

1V~: ~
T7

I

---I>

RM4 33

§~@~~~L5244~~~gw~:
I

(S)MRD1 1~

j

t"1.~.'21

1

EO
E1

19

-

9
7
5
3

15

":5"""""VIr-":
6 - ! 1 - - - C > MW011(S J
MW021(S)
7
8
MWD31(6)

j

1

,.....

(1)ADOS ,;'"
(1)AD07

RM333

r----+-j3--'\N'<..:4'-+-j---OMW081(SJ

.....

j

j

8

1

2'

MWOC1(6)

641I

MWDD1(6)

13
5
j7

8' - + - j - - - I >

1
I
1'----r
'-'NY-

§~~;[~~I~~~~i~~~~I~~9

(1)A0121;...1>--------.

10

(1)A0131.....
(1)A0111 .....
(1)A0141.....

12

1T

MWDB1(6)

MWOF1(6)
MWOF1(6)

L- __ :......J RM6 33
8 ~r5--------------C>

(1)A01011>-----------.

MWOA1(6)

7

MPEHO(7)

R3

TO

6

33

~

MWPH1(6)

13

(1)AD151r-..

1~

(6)MRD81j,..~~~~~~~~~~~~~~~~~~~~~~

~

4

(S)MRPH11>-------~"l
3R

(6)MR091!::

(6)MROA1~

(4)RFA01

(6)MROB1 1>-_
.....
_ _ _ _ _--'

(4)RFA11

(6)MROC1:::.1>-_ _ _ _ _ _ _...I

(4)RFA21

(6)MR001!::1>-_ _ _ _ _ _ _---1
(4)RFA31

(6)MROE11>-_ _ _ _ _ _ _ _...J

(4)RFA41

(6)MROF1_1>-_ _ _ _ _ _ _ _ _...J

(4)RFA51

(11)MRHBO~I>--------------------...J

(1)AB011§~~~

(1)AB021

(1)AB031
(1)AB0411>---_ _ _ _....J

RM8

(4)RFA61
LS244

11

18
16
14
1
9

MMA01(6)
MMA11(6)
MMA21(6)

4M

MMA31(6)
RM7

(1)AB0511>--------..J

MMA41(6)

17
1 EO
19

(1)AB0611>-----------1
(1)AB0711>---------....J
(1)AB0811>-_ _ _ _ _ _ _ _ _...J

MMAS1(6)
MMA61(6)
MMA71(6)

(1)AB0911>----------~

RM8

(1)AB1011>---------~

(1)AB1111>--_ _ _ _ _ _---.

(1)AB121f~~~~::::~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~I~I

LS244

18
16
14

(1)AB1311>-------.

11
13

(1)AB141

4L

(1)AB151
(1.2)AB161

(4)RFSH0I>-_ _ _ _ _ _ _ _ _ _ _ _ _

~~

136-10043O-500-A

(4)RFSH11>-_ _ _ _ _ _ _ _ _ _ _ _ _-+_~
11

G9PFBU PCB Circuit Diagram
(4)ASLHOI>-------------....J

Sheet 5 of 11

B-8

(S )MW001
(S)MW011

'""101(5)
~

[> MI

(S)MW021
(S)MWD31
(S)MMA01

MR
~

(S)MMA11
(S)MMA21
(5)MMA31
(S)MMA41

~D'IOiJ~

(S)MMAS1

r===i

(S)MMA61
(S )MMA71

"

"
"'

~~

416-4

,
2

~D'IOiJ~

~ ,
"" ~ 2V
A~
2

~ 2W

" ,
BIT
,, ,
" -

~D'IOiJ~

===i

416-4

""w

"'"9 ,

6

B

BIT 1
3

RAS

"$

,
2

~ro;--;;;; ~

I

~ 2U
6

~

!

A~

416-4

,
2

"" ~
"'" ,

2T

6

9

, w
" '"

"'5

416-4

" ,
BIT 2
,, ,
",
" 'm- - - -

6

9

A~

9

BIT 3

, ,
" ""
3

OS

~

(S)MWD41
(S)MWOS1

MRD41(5)
~

(S)MW061
(S)MW071
(S)MWDL1

MRDS1(5)

I
I
~

l-'!. r::-:----=

~D'IOiJ~

!

t

""
'"n
9

A~416-4
2

3

!

I

""w
n

~ 3W

,

9

A~

,

'2

~ 3V

"w

,

A~

416-4

,
2

t

, 3U

,~
"nw

s

" ,
6

9

BIT S

9

BIT 6

,, ,
""
" ~

3

"'5

(4 )RA500

===i

6

BIT 4

, ,
" ~

(4)MMWLD

416-4

2

MRD71(S)

l-'!. ror---oo ~

l-'!. ro;--;;;;~

14

DO~

01

6

MRD61(S)

I

===t

416-4

2

,

9

, ,
m
""

3

3

14

3

35

6
2

PBL

, ,
" '""
'"- - - -

1

~

~

(S)MWOB1

MROB1(S)

(S)MW091

MR091(S)

I
I

(S)MWDA1
(S)MWOB1

i

!

A~

416-4

2
3

"" ,,
"n
9

!

I

A~

416-4

2
3

""w ,,

4W

"

6
2

9

BIT B

4V

MRDA1(S)

I

~ror---oo~

~~~

I

!

I

""

w
n

6
2

9

, ,
""
" '-----3

CAS

C MHIH1(5)

416-4
S5

6
2

PBH

BIT 1S

, ,
'"
" ~

,
""
" ~

3

3

4

I

( 4)MMWHO
(4)RA510

136-100430-500-A
G9PFBU PCB Circuit Diagram

(4)CASOO

Sheet 6 of 11

B-9

(2)AE375 1>-_ _ _--.:4~
~8~---~---------------------------------------------_i>HBNK1(4)
+5V

R14

1K
+5V

(5)MPEMOD---rr------------------------+~;

C23 IO. 1U

(5)MPELOI>--~~-----------------------+~4

(1)AB001

I>--~~----------------------_+~~

(11)MRDSO~--~----------------------_+------------~=i~~[:~rorL--~==~

4

(1)RSTOOD-~~r------------------------+------------~-+-------~-------~

1
( 11 ) RAMSO 1>-_1--+---:1-'-i

~~10-~>RAMS1(4)

'------1l>HBNKO(311 )
11

(1 )CLK01 I>--+-~----,
(2) IOWOO 1>-_+-1----,
(2)IOROO 1>-_+-1---,
(4 )MMROO
(2)MRDOO
(2)AE371
(2)MWROO

i
~~~~~~f~~~~~~~~~~I'LS~2:4"4'1~~~~~~~~~~~
;7
1

I>-~-+----,

1F

EO
E1

(1 )BHEOO I>--+---i~----,
(1 )ALE01 1>---+------,
( 1 )DTRO 1 1>-_+-----,

'~;.~~~~~~~;ff~~~~~~2r:i4I~~~~~~~~~~

(1.2)AB161 1>--1----,
(1.2)AB171 1>--1-----,
(2)TSI11 I>-~--....,
(1.2)AB181
(1.2)AB191

4

LS244

8

1G

1

EO
E1

XOOO I > - - I - - - - - - - - - - l

(11)APFOO
(3)AD083
(7)X101

B-IO

D~==j===========~~~~~~~r....!::!:!t:....l

136-100430-500-A
G9PFBU PCB Circuit Diagram
Sheet 7 of 11

+5V
(1; 10)AD011
(1)AD021
(1 ,10)AD001
(1 )A0031

t>~~~~~~~~~~~~~~~~~~~~~~~~~~IBhh
I

(1)AD041
(1)AD051
(1)AD061

~I>-

( 1 ) AD071

1>------'

_ _-J

SW
LS373

4
7

1

+5V

~

14
17

11

RM1

1
1.
1

7Q

1
R58r1K

-------11> NMI01 (1)

~---+~~~---.~IRQ01(1)

SWSTB~rcC~N'~-~16~------~~1:~~:-~====~~t+++=====i~
1 C
2200P
'---

-

.:::!::
C4°I
-=-

FDINPOIH711(

+5V
NWR1-049( 13K )

G

"X>-"'-------l> IRQ 11 ( 1)

BOOK/PAGE
2
LS373 5
6
8
1
1
14
1
17
16
7R
1

READ SIGNAL

(11)KRSGOvl>-----~R~EA~D~B~O~OK~/~P~A-G-E------J

4
7

(11 )KRBPO 1>-_----2=~~~=~_----,

•

'Xl"-----l'> IRQ21 ( 1 )

,.

CN' ,

§

r-----:t1
1

SD11
SD21

~ ~~!~
CNJ-6

~ ~~:~
(11)KRDTO

II

II

CxJ"-----I> I RQ51 ( 1 )

CP

EO

I

'----

CxJ"'----I> lAQ61 ( 1)
KEY DATA
4
7

2

LS373

5
6
9

7S

16

8
13
14
17
18

10

,.

IRQ81(1)

"

15

r-P:
1

IAQ91(1)

CP

1>---..----------------++---'<1' - - EO

+5V

IRQA1(1)
AS7 A56 ASS

~

OP01

I

10K

10K 10K

IRQB1(1)

'

g~N'~-~21g:=tjO~P~1t1~~~~;;~~~~E:====~~~~4~
6

7

LS367

IRQC1( 1)
7P
(11)KRSTOvl>-----1-----------~R~E~A~D~D~A~T~AL-------+_t+~1~____~
IRQD1(1)
+5V

PBSTBE~~N_';:-.,.14i)__+-R5-2-~+_1-1K----___"1~LS14
_ I
C38

I

8

13 LS04
6J

7J

IAQE1(1)

12

2200P

DRQ01(2)
+5V

+5V

R29~ 1K

DTSTBf<~'NN';:-::---;;12;:,--+-A-5-1+_~-1K----___"_I1~lS14
10

T

37

I

11

LS04

10

C28~ O.1U

~

7J

':)(>'-----11> DRQ 11 (2)

2200P

':)(>'-----11> DRQ21 (2)
l------~------

.-----~---,

.-+--------+---1) IRQ41(1)

2
TO~9---+LI+_~if"0'''l.,~.';.-:TcTT~5L---~
~
6 '-~"CP5KflA1ARM

R1

~
+5V

DRQ31 (2)

OA

~
5 ~08 r6------,r'i'-'~"!R...::.:.2FO~
4

(1)RSTOOI>------"l

101

II

CPLS74:
MS6H

r-

I

1

MR

r,u

ERDY1(4)

FO

Lt:::=======::::J

XOOO

1>-------.----1''"''1').

+5V~

~
25

·····31

26

................. ·42
CN3

I::::::::::::::: :1

136·100430·500·A
G9PFBU PCB Circuit Diagram

Sheet 8 of 11

B-ll

R46

~

DCN
XOOO~--~r-~C~N'~-I'>

470 _:::!::2200P
C32J;: MC01CH1H222K
R49

~

+5~V

ALM

R48

~

:::!::2200P

C34~

R47

3 ~!04X>'·--~--"'ID1
RHA

470

XOOO
(7)X101
(1)PCLK1
(1)RSTOO

~':
;;"

~~

R24 3.3K

470 _:::!:::2200P
C35J;:

,~

"

TO
7G

~I

~

~

"
llllro=t::::H:::=~===:;i---,
T6

~:===========~===========~==========:F==~===========icl'---:...o,,~,,____~5 ~!04
.:.

6

~TM2

I

-_.

IRT~

L-_--'

ROP

-!§D

~~

I' '"

(1.10)AD001
(1.10)AD011
(1)ADD21

I

~---I-'

XOOOvD--_ _ _ _ _ _ _ _-+_____

I

'
~

R26
~

13

3.3K

LS86
7H

8255A 5

"

t

+-(1)AD031!~1l!l~~~~~~~~~~~~~~~~~~~'III~ g~g~ I/O::~~'~==~+=~~
__________++__1--+______________
::!p,~=lit=j:::t-----------l
'21 -'__~'~

(1)A0041

DC

(1)ADOS1
(1)AD061
(1)AD071

~~ ~,

(1)AB01 1
(1)AB02 1

""

(2)IOROO
(2)IOWO 0
(11)CODA 0
(1)RSTO 1

PA2

eTR

"

Wi<

"

,

;A"i, ~

•

pz:==-+++____________

'co
eo, ~
eo,
4F eo,
eo,
eo,
eo,

"
'" "it--

R22

___l

R23
3.3K

2

~~08

1-"'----------------------------!>IRQ71(1)

3
3 3K

MASK

i!

Lm-

row

"",I"

'"'
:~



~

(4)RSTO 0

25

~:::::::::::

531

::: :J

IZl???Z??Z????)'?

26

642
CN2

~I
3~1
21

2~

~

~23

~

B-12

136·100430-500·A
G9PFBU PCB Circuit Diagram
Sheet 9 of 11

+~v

(3)A 0003 ...
(3)A 0013
(3)A 0023
(3)A 0033
(3)A 0043
(3)A 0053 ..

R27

I

.?

3
4

LS174

1
3
14

4C

12

LS07

40

L..2.

~~
~

5

LSD7

1

Ol
,.. ,.. ",.. ,..CO ,..

1IlU)

6

40

MR

Lf9

II: II:

II: II:

~~:

~

II~

0

C\J
II: II:

M
MM M

8

~

M
M

~

M
M

~

M
M

3

10

LSD7

4

I

TP

C1

00

C2

XTAL

9
13

9

33K

R21

1

I

LS367

..L C2511mI 22P

'fnT.

01

12

.,.

A0001(1.3.5.8.9)

~ A0011(1.3.5.8.9)

7P

XT20

6C

ClK

1S

TC2611mI 22P

32 . 768 KHz

CS

11

LS07
40

CO

33K

10

STB

~

40

11

o1990AC

3

CP

Q

(11)WTSOO ..
(1)R STOO I>--

13

+:>v

RV-38

aE
1'4

VOO

17

I

--=

40

1

2

L.SD7
40

(11)WTROO ...
+5V

470

R59
(4) X102 ::.

+5V ~ R65

OS
1

PS

2

rt:;J

+5V

I

R64
330K

7U

1

-:L-

2p1,

LSOO

R39
2.2M

100K 1 24bT<

~I::
'fM1

2
3

ICL8212
CPA

9..2
1Ss97

-==A953

+5V
3
1
R35

~~

2
[,j.RV2
20K VR

R36

R43

56K
R37 2
2:2M 31

3.3K

wf,-

4

8~

c4~1

R41

8

150K T47P

R38

3

6U

2

R40

~
fC'NM""':
R42

+5V

SG2050

8
ICL8212
CPA

C3,o1
20KT7P

?
11

R45
1.5K

~1

r

4

7rs-r

C31

T'

20PR44

I

330
R34

+
33K

...

VRAM(3)

......

BMCSO(3)

C61.C64.C95
CK010F1H104Z-C

~C506EIC220M8S

C2002
~~

5
3

I '!~

14

TO
CP 04013 ~
:70
FQ
7

1 K

C10 TO C16

1
I

l

1
,;>

XOOO

~~~04a13Tl
10

MS 70
MR

FO

136-100430-500-A
G9PFBU PCB Circuit Diagram

SG ..
FOINP01H470K

FOINP01H221K

B-13

Sheet 10 of 11

(2)AE371
(1)AB071 ::(1)AB061 ::(1)ABOS1 ::(1)AB041 "
(1)AB031 ...
(1)AB021
(1)AB011
(1)AB001
(1)BHEOO
XOOO ::.
...

:
:
:
:

'~

2

L

II

1

5
6

~
t Jill
6J

6L

16L8
PAL

PFB01A
7N

,..u-

vee

3

50

2

.1Q

1
XOOO ....
X101 ....

~~
~sv

4

~

51
52

EO
E1
E2

7M

Fa
F1
F2
F3
F4
FS
F6
F7

CDMAO(2)

I

7

: CITSO(1)
:... CTIMO(2)
CODAO(9)
"... CDMRO(2)

GNO~
-

2

~6
5

1

6L

"...

50
S1

EO

t

FO
F1
F2
F3

7L

f---l

L::;l;j~

~.

11
12
~
L532
6L

(2)IOWOO ....
....

~8
10

.14

50
51

15

EO

t

Fa
F1
F2
F3

~
~

48R
4AR
4CR
4ER

KRDTO(8)
KRSTO(8)
" KRSGO(8)
KRBPO(8)

S8W

....
.... WTSDO(10)

S9W
SBW

.... BMMEO(3)
v APFOO(7)

7L
S8R

13
12

r-U
2Q

11

~6
S

10L8
PAL
~ PFB02

III

4
5
6
7
8
9
11

I
B-14

'------{>

XOOO

v

MRDSO(7)

:::. ROMSO(3)
:::. RAMSO(S.7)
:::. BMMSO(3)
:::.
.... BEXCO(S)

III

1

..... DMACO(3)

1

1N

4

:::..... MPRDO(3)

1

vcc
GNO

(2)MRD01 "
(2)AE373 v::::.

C65 TO 94
C96 TO 99

.... MRHBO(S)

"

....
....
....
....
....
....

CKD10FIH104Z-C

C62,C63

..... MRLBO(S)

2Q

(2)AE370
(1.2)AB191
(1.2)AB181
(1.2)AB171
(2)MRDOO
(4)MR001

CSO TO 60

WTRDO(10)

6L

...

D

+SV
CS06EIC100M8S

I--,-----,--------;GNO

LS139

(7)HBNKO

CTMR1(2)

::- CITMO(1)

LS138

3

(2)IOROO

-"
....

~+sv

PJ.-

136-100430-500-A

g~

," I
11 I

L510
6K

----

8

....
.... DMECO(3)

G9PFBU PCB Circuit Diagram

Sheet 11 of 11

AB15(4)

A019

AB19(4)

A018

A013
A012

AB12(4)

A011

AB11(4)
AB10(4)
AB9(4)

AB18(4)

~~

A017
A016

1M

,

n

X111
XOOO

AB17(4)

12

""'"

AB16(4,4)
MW(4)

AB8(4)
OB15(6, 7,3)
XOOO

1>-------'

OB14(6,7,5)
OB13(6,7,5)

llim-

MRO

HRO(4)

~OB12(6.7,5)

OB11(6,7,5)
OB10(6,7,5)
(4)GCG
(4)M896

OB9(6.7,5)

[>------------4
[>-------------+-4

MW

OB8(6.7,5)
OB7(6.7,4,5)
OB6(6,7,4,5)
OB5(6,7,4,5)
OB4(6,7,4,5)
OB3(6,7,4,5)
OB2(6.7,4,5)
OB1(6.7,4,5)
OBO(6.7,4,5)

~~~~~~l ~: "'" ~~.~;!~~~ffi~~~
5 2 ,0.,

S
7

:~

SA

8 6"

2B 15

1K

!~

L06(2,8,9,10)

14
13

L05(2,8,9,4,10)

69 12

L04(2,8,9,4,10)

59
79

11

(1)IORO~================~tt==========~
(1)C50 f)
'"
19

LD7(2,8,9,10)

L03(2,8,9,4,10)
L02(2,8,9,4,9,10)

EO

L01(2,8,9,4,9,10)
LOO(2,8,9,4,9,10,2)

AB1(4,2,8,9)
AB2( 4,10)
AB3(4)
AB4(4)
AB5(4)
AB6(4)
AB7(4)
XOOO

11

LSICS
LS138

1 LSD"

LS04

'"

CRT1(2)

""n
16LB
PAL
OT/R

BHE

R2I7r-------------~~

2H

"

""
""
"

n

SNOO(10)

",

FOOO(8)
APUO( 10)

'"

"

f;'

t> 5IOO(9)

lIO SELECT
15138
R26
2

Sl
<;;,

IOR

R23

IOW

R22

OMC

R21)------~r_____'_l

IOR1(2)

3J

t> INTRO(2, 10)

""n
""",

"

~;.

IOW1(2)

IORO(1,8,9,10)

C50(1)

IOWO(8,9,10)

136-100430-501-A

G9PFCU PCB Circuit Diagram

(2 )IJACKO (>-___________--.J

Sheet 1 of 11

(8 )IlACK 1 (>-. _ _ _ _ _ _ _-.J

B-15

"" "
"" "
,"" "

WlOII
(1)lOI

!HlP]
WlD4

05

(H lOS

1220
GO<

" ""

Wl06
(I)

22
AOO
AD>
A02
AOJ
AO.
A05
A06
A"
AOI
A09
32
ADIO

D>
02

WLD2

l01

~

~

A011

DACI(

A014

AD15

VSVN

" "

.

BLNK
ATfttNK

2.CCtK

.

eSR

lPE~~4!lPGn~D ORO

GDB4IJI

G08513l
OIlB6(3)

GOB9ll)
GOB10(31

00811(31
IlO8um

·
·
*-

0814(31

--t>IISYN~ IS, 11
VSVNC (S.1)
UNKI21

M

CSR(2)

L---

.

, "
"

"

.

s

.

"

L;
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,

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,

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C6.C9
C8.C9
C11

C12 TO C27
e29
C31 TO C41
e43
C45 TO C60
C62 TO C76
C80.C82
C84.C87
e78

C515E1V6R8M 85

L-----I'> XDDO

CKD1DF1H1D4Z-C
+5V

50
R
1K 2 1 L
C61
0. 1U T

~@f-~-""f""-----------o+12V

C2
C5

Pin assignment of FDD connector

+5V

C515E1V6R8M 85

XOOO

t>----J

X111A(2.2.2)

C79
0. 1U

xooo

T

X111B(2.2.4.4.4.
5.5.5.5.5.
9.9.9.9.10)

t>----J

Pin assignment of MODEM connector

DETAIL OF ZR1
C4Z
C1DD

CKD1DF1H1D4Z-C

2

R
1K 2 2 L

,.JlllllU
R-1K

RF07Q102G

r-~--t-----------O+12V

C4

C515E1V6R8M 8C

DETAIL OF ZR4

RF07Q102G
C83

CKD1DF1H1a4Z-C

DETAIL OF ZR3

}~~~~~~~
+5vllWlU
R-150

B-24

136·100430·501·A
RF07Q151G

G9PFCU PCB Circuit Diagram

Sheet 10 of 11

(1)AD1
8

~~~~~~~~~~~~~I

(1)LD11>-1>(1)LD2
(1)LDQ
(1)LD3 1>-1>(1 )LD4

4

( 1 ) LD5 I>--+!-I+t+

3

1

13
14
15

( 1 ) LD6 [>--+++++H
( 1 ) LD7 [>--+1++1+++

21
19
20

(11)X111B
XOOO
(1)AB2
( 1)IOWO

23
22

'PU

DO
01
02
03
04
05
06
07

8531
(24 PIN)

SVACK

EACK

c/5

2F

WA

eLK

READY

( 1)IORO

-+5V

l2

(8)2MHZ

~

END

A5T
CS

11

JO

~

KO

r-4&::

CP

XOOO

AD

(2)RSTI
(1)APUO

+1711

~
2

GNO

tl-

TO 9
LS1112

11

~X,"1~0_---1 R12

FO~

IR14

1E

~"-~~_ _ _ _....J

R53

~-v~~4+----~+5V

,-

R54

1)INTR~1>--

(2)RSTO~

2

I-___________+ _________'~ L;~2 }..23_______'!.!.'-l~;04

10

Wii

O'

11
1

MA

I

+5V

CP
M5

LS74
7L

10

FO

L~~O [)-'8'--____---1

L22

8

e89~10U
,1',1 ,

e91~O.1U
XOOO t>-

e9?'~R45
~
10lUJ 10K

18

4

DO
01
02
03
04
05
06
07

8

SOUND

eH1

01771
-005
(28 PIN)

:s~

-==

WA

SOUND 1

' - -_ _ _ _-'3'<] RO

-+______-'5'<] es

( 1 ) SNDO [>-__________________

-~vA"17Y:rn--I--...l--'W'v------IeN6-,

1-"=-3

r--------"-9-l elK

~'v

3.3 K

4X

~
~:::

0 .1U

P8'

XOOO D-_ _ _ _ _ _ _ _ _ _+-_~~-"'6'_lEXINT
+5V

~'2

(8)4MHZD------"l9~1

10U
+

GND

J'

N - 1>---------,

+5V

I~--+---i
~
~
~

-3>--------~

EXT SP+

~~~~--~----~------~

EXT SP-

r---------~----------~eN7-1

1

200P

~10K

eN

? l<""
20K

150K

6800P

O.022U O.022U

N -4>-------'
10U

136-100430-501-A
G9PFCU PCB Circuit Diagram
Sheet 11 of 11

B-25

Appendix C

Programmable Array Logic
Decoding Specifications
There are four Programmable Array Logic (PAL) devices in the APC, two on the
Processor PCB and two on the Controller PCB. These devices are identified and
listed in Table C-l. Tables C-2 to C-5 describes each PAL device in terms of its
inputs and outputs.

Table C-l Identification and Location of PAL Devices
STAMPED
IDENTIFICATION

MANUF ACTURER
DATA

PCB LOCATION

PFBOIC

MMI PAL 16L8
or
Signetics N 82SI53F

G9PFBU (Processor PCB)
Location 7N

PFB02

MMI PAL lOL8

G9PFBU (Processor PCB)
Location IN

PFCOI

MMI PAL I4L4
or
Signetics N 82SI53F

G9PFCU (Controller PCB)
Location 2H

NMS02

MMI PAL I4L4

G9PFCU (Controller PCB)
Location 2N

C-I

Table C-2 PFBOIC Inputs/Outputs
INPUT
PIN NUMBER
1
2
3
4
5
6
7
8
9
11

C-2

OUTPUT

SIGNAL NAME

PIN NUMBER

SIGNAL NAME

19
18
17
16
15
14
13
12

BO
Bl
B2
KB
CO
WAT
CDMAO
MBC

A7
A6
A5
A4
A3
A2
Al
AO
BHEO
AE371

BO

=

(A7·A6·A5·BHEO·AE371) + (A7·A6·A5·A4·A2·AO·AE371) +
(A 7· A6· A5· A4· A3· A2· AI· AO· AE371)

Bl

=

(A7·A6·A5·BHEO·AE3il) + (A7·A6·A5·A4·A3·BHEO·AE371) +
(A 7·A6·A5·A4·A3·AO·AE371) +
(A 7· A6· A5· A4· A3· A2· AI· AO· AE371)

B2

=

(A 7·A6·A5·A4·A3·A2·AO·AE371) +
(A 7· A6· A5· A4· A3· BHEO· AE371 )-+-( A 7· A6· A5· A4· A3· AO· AE371)
+ (A7·A6·A5·A4·A3·A2·Al·AO·AE371)

=

(A7·A6·A5·A4·A3·AO·AE371)

=

(A 7· A6· A5· A4· A3· A2· AI· AO· AE371) +
(A7·A6·A5·A4·A3·A2·BHEO·AE371)

WAT

=

(A7·A6·A5·A4·A3·A2·Al·AO·AE371)

MBC

=

(A7·A6·A5·BHEO·AE371) + (A7·A6·A5·A4·AO·AE371) +
(A7·A6·A5·A4·A3·BHEO·AE371) + (A7·A6·A4·A3·AO·AE371) +
(A 7· A6· A5· A4· A3· AO· AE371) + (A 7· A6· A5· A4· A3· X2. BHEO·AE371) +
(A 7· A6· A5· A4· A3· A2· AI· AO· AE371)

CD MAO

=

(A 7·A6·A5·BHEO·AE371)

Table C-3 PFB02 Inputs/Outputs
OUTPUT

INPUT
PIN NUMBER

SIGNAL NAME

PIN NUMBER

1
2
3
4
5
6
7
8
9
11

MBCS
DMC
AB19
AB18
AB17
MRD
lOR
MRQ
ABO
IMM

19
18
17
16
15
14
13
12

SIGNAL NAME
ROMS
RAMS
BMMS
BEXC
MRBS
DMA
MPR
ITMM

--

ROMS

=

(ABI9'ABI8'ABI7'MRD)

RAMS

=

(ABI9' ABI8· AB17)

BMMS

=

(ABI9'ABI8'ABI7'MRQ)

BEXC

=

(DMC' MRQ' ABO)

MRBS

=

(ABI9'ABI8'ABI7'MRD)

DMA

=

(DMC'IOR) + (DMC'MRD'ABO'IMM)

MPR

=

(DMC'MBCS'IOR)+ (DMC'MRD'IMM)

ITMM

=

(ABI9'ABI8'ABI7)+ (ABI9'ABI7)

-------

--

-----------

-----

--

------

C-3

Table C-4 PFCOI Inputs/Outputs
INPUT
PIN NUMBER

SIGNAL NAME

PIN NUMBER

AO
Al
A2
A3
A4
A5
A6
DT/R
BHE
lOR
lOW

19

1
2
3
4
5
6

7
8
9

11
13

-

LSI

BI

OUTPUT
SIGNAL NAME

18
17
16

15
14

12

LSI
BO
BI
B2
10
CSO
CSI

=

(A6'A5'A4'A3'A2'AO) + (A6'A5'A4'A3'A2'AO) +
(A6'A5'A4'A3'A2'AO) + (A6·A5·A4·A3·AI·AQl.+
(A6'A5'A4'A3'A2'BHE) + (A6'A5'A4'A3'A2'AI'AO) +
(A6' A5· A4· A3· A2· BHE)

=

(A6'A5'A4'A3'A2'AO)+ (A6'A5'A4'A3'AI'AO)+
(A6'A5'A4'A3'A2'AI'AO)+ (A6'A5'A4'A3'A2'BHE)+_
__
(A6'A5'A4'A3'A2'AI'AO'DT/R) + (A6'A5'A4'A3'A2'AI'AO'DT/R)+
--(A6' A5· A4· A3· A2· AI· AO),

=

(A6'A5'A4'A3'A2'AO) + (A6'A5'A4'A3'AI'AO) +
(A6'A5'A4'A3'A2'BHE)+ (A6'A5'A4'A3'A2'BHE)+
__
(A6' A5· A4· A3· A2· AI· AO' DTIR) + (A6' A5' A4· A3· A2· A 1· AO' DTIR)+

---

--

(A6'A5'A4'A3'A2'AI'AO'DT/R)

10

=

(A6'A5'A4'A3'A2'AO) + (A6'A5'A4'A3'A2'BHE) +
(A6'A5iA4'A3'A2'AI'AO) + (A6'A5'A4'A3'A2'BHE) +
__
(A6' A5!' A4· A3· A2· AI· AO' DTIR) + (A6' A5' A4· A3· A2· AI· AO' DTIR)+
(A6'A5'A4'A3'A2'AI'AO)
I

=

(A6' A5· A4· A3· A2· AI· AO' lOW) + (A6' A5· A4' A3· A2· AI' AO' lOR) +
(A6'A5'A4'A3'A2'Al'AO'IOW) + (A6'A5'A4'A3'A2'AI'AO'IOW) +
(A6'A5'A4'A3'A2'AI'AO'IOW) + (A6'A5'A4'A3'A2'AI'AO'IOW) +
(A6'A5'A4'A3'A2'AI'AO'IOR)

=

(A6'A5'A4)
(A6'A5'A4)

C-4

Table C-5 NMS02 Inputs/Outputs
OUTPUT

INPUT
PIN NUMBER

SIGNAL NAME

PIN NUMBER

SIGNAL NAME

1
2
3
4
5
6
7
8
9
11
12
13
18
19

CC7
CC6
CC5
CC4
CC3
CC2
CC1
CCO
M8960
MRQO
MWO
XNU
XNU
XNU

17
16
15
14

ANKO
FULLl
BEO
BSO

--

--------

ANKO

=

(CC7·CC6·CC5·CC4·CC3·CC2·CC1·CCO)

FULLl

=

(CC6·CC5·CC4·CC3·CC2·CC1·CCO) +
(CC6·CC5·CC4·CC3·CC2·CC1·CCO) +
(CC6·CC5·CC4·CC3·CC2·CC1·CCO) +
(CC6·CC5·CC4·CC3·CC2·CC1·CCO)

BEO

=

(M8960· MRQO)

BSO

=

(M8960· MRQO· MWO)

-

--

---

--

C-5

Appendix D

Character Code and Keyboard
Information
This appendix gives important character code and keyboard information for the
APC. The characters that can be generated and their associated codes are shown in
Table 0-1. The meanings of the ASCII special characters are given in Table 0-2.
Table 0-3 lists the APC special characters that differ in representation from the
ASCII standard, but the generated code is the same. A quick reference quide for
easy association of the ASCII special characters and APC special characters is
provided in Table 0-4. The APC GRPHI characters are shown in Figure 0-1, the
GRPH2 characters in Figure 0-2.

0-1

Table D-l Code Table
SECOND
HEX
DIGIT
0

FIRST HEX DIGIT
0

1

NUL DLE

2

3

4

5

SP

0

32

48

@
64

80

7

96

112

P

p

00

16

SOH

DCI

!

I

A

Q

a

q

01

17

33

49

65

81

97

113

2

STX

DC2

"

2

B

R

b

r

02

18

34

50

66

82

98

114

3

ETX

DC3

#

3

C

S

c

s

03

19

35

51

67

83

99

115

D

T

d

t

I

4

EOT

DC4

$

4

04

20

36

52

68

84

100

116

5

ENQ NAK

%

5

E

U

e

u

05

21

37

53

69

85

101

117

6

ACK

SYN

&

6

F

V

f

y

06

22

38

54

70

86

102

118

BEL

ETB

7

G

W

g

w

07

23

39

55

71

87

103

119

BS

CAN

(

8

H

X

h

x

08

24

40

50

72

88

104

120

HT

EM

)

9

I

Y

i

y

09

25

41

57

73

89

105

121

LF

SUB

j

z

26

]
74

Z

10

*

:

90

106

122

K

[

k

{

59

75

91

107

123

<

L

,

60

'\

I

76

92

108

124

-

=

M

]

m

}

45

61

77

93

109

125

>

N

1\

n

7
8
9

A
B

C
0
E
F

42

+

VT

ESC

II

27

FF

FS

12

28

CR

GS

13

29

SO

RS

14

30

46

SI

US

15

31

43

44

58

62

78

/

?

0

47

63

79

ASCII Charact or
or
Graphics Character

D-2

6

94

-

95

126

0

DEL
127

A

9

-

..L.

~ 1144

B
00

1160

176

.

1162

II

1179

1164

1180

/
165

1149

.

I

€

36

lml: 16(z

(J
1184

137

Q

16J

l
llli..

~
155

117

172

158

lilll

(
173

'- I)

~
~

18l
n

.~

170

b£ +
~

7

18T
0
188

(j
189

K
190

7 E

1754

. .--r--.
Decimal Code

191

~

~~

m'7

~

J
Gt-

1212

I-

8

198

213

1199

+

1200-

V

l-

9

1--

214

1
118f

~

8
1197'YJ

181

16J

151

1196~

121Y

6

182

166

lli!J

210

~
I"~

11913

5

F

~

::::;
119fl

E

20~ m:- ~
l.w

4

<
1148

0

~

T
178

r- 1163

a
1192

193

177

*

1147

C

3

>

~~
161
~

_146

-

110

III

8

246

~

L
215

6!
=\= il 2.
~

('\

~

l216

217

201

7r
1202

1\
1203

2

r-

X

218

0

219

123'

+

1m

L250

1l.':-

-

~~
12~ r ~ @I
A
~ bX.
J1QL bt ~
204

0

220

221

[206

222

T

125?

Table D-2 ASCII Special Characters
CODE
NUL
SOH
STX
ETX
EaT
ENQ
ACK
BEL
BS
HT
LF
VT
FF
CR
SO
SI
DLE
DCI
DC2
DC3
DC4
NAK
SYN
ETB
CAN
EM
SUB
ESC
FS
GS
RS
US
SP
DEL
NOTE:

MEANING
Null
Start of Heading
Start Text
End Text
End of Transmission
Enquiry
Acknowledge
Bell
Backspace
Horizontal Tab
Line Feed
Vertical Tab
Form Feed
Carriage Return
Shift Out
Shift In
Data Link Escape
Device Control I
Device Control 2
Device Control 3
Device Control 4
Negative Acknowledge
Synchronous Idle
End Transmission Block
Cancel
End of Medium
Substitute
Escape
Form Separator
Group Separator
Record Separator
Unit Separator
Space
Delete

These codes are not displayed on the APC as shown. Some of these codes
are not used by the APC, but the unused codes can still be transmitted for
use by other devices.
D-3

Table D-3 APC Special Characters

SECOND
HEX
DIGIT

0
I

FIRST
HEX
DIGIT
0

I

00

E3
16

~
~

-

III

-

01

2

02

3

03

4

5

19

04

-+20

[2J

X

Z

21

6

OK
06

CD
22

7

~
07

23

t'
08

24

09

•

9
A

..
0
10

B

C
D

F

APC
Character

I

25

26

rn

II

27

~

El

..
13

E

D

...
12

D-4

18

05

8

NOTE:

17

"*00

28

[£J
29

0

14

30

15

c::J
31

--8-

Decimal
Code

Only characters that are not associated with a specific APe function are
displayed on the screen.

Table D-4

Quick Reference Guide for ASCII Special Character/APC Special
Character Association

ASCII
SPECIAL
CHARACTER
NUL
SOH
STX
ETX
EaT
ENQ
ACK
BEL
BS
HT
LF
VT
FF
CR
SO
SI
DLE
DCI
DC2
DC3
DC4
NAK
SYN
ETB
CAN
EM
SUB
ESC
FS
GS
RS
US
SP
DEL

NOTE:

APC
SPECIAL
CHARACTER
~
~

m
z

[2]
Ok

....
.

t;,
l'
0

~

*

00

r=:J

X

CD
0

I

CD

0
[2J
D

Ll

Characters associated with a specific APe function are not displayed.

D-5

..

OD

lA

NOTE:

Characters associated with a specific APC function are not displayed.
A.

UNSHIFTED (SHIFT KEY UP)

Graphics
Character

fi
Hex Code

B.
NOTES:

SHIFTED (SHIFT KEY DOWN)

1 GRPHI CHARACTERS ARE PRODUCED WHEN THE
GRPHI KEY IS PRESSED.
2 GRAPHICS SYMBOLS ASSOCIATED WITH A SPECIFIC
APC FUNCTION ARE NOT DISPLA YED ON THE SCREEN.
INSTEAD, THE FUNCTION IS PERFORMED.
3 THE ALPHANUMERIC SYMBOLS ASSOCIATED WITH
THE GRAPHIC SYMBOLS ARE THE HEXADECIMAL (HEX)
CODES GENERA TED BY PRESSING THE KEYS.

Figure D-l APC GRPHI Characters

D-6

C7

A. (JNSHIFTED (SHIFT KEY UP)

•

•

(
)
+
+
EB
,v
*
/
~/ ~/: ~~ ~~ ~~ ~~ "::0h ~/. ~~ ~/ ~~ ~~ ~/

6.

0

t

~

--- -

~/t ~/l ~ ~

/ irA=/'
:S

B. SHIF1ED (SHIFT KEY DOWN)

~

::I:-

~~~

GRPH2
Character

He<
Code

NOTE:

Character
on Key Cap

GRPH2 CHARACTERS ARE PRODUCED WHEN THE GRPH2
KEY [S PRESSED

Figure D-2 APC GRPH2 Characters

D-7

Controller PCB

(08)

I

INS
(IC)

(2F)

DEL
(18)

t

0

7

8

9

(37)

(38)

(39)

(OB)

(OC)

(OA)

D
D

(2D)

4

5

6

+

(34)

(35)

(36)

(2B)

I

2

3

(31)

(32)

(33)

0

(30)

(2E)

E
N
T
E
R
(OD)

NONLOCKABLE SWITCH KEYS

LOCKABLE SWITCH KEYS

NOTES:

I. HEX NUMBERS IN PARENTHESES DESIGNATE HEX CODES.

2. FOR HEX CODES OF STANDARD ALPHANUMERIC CHARACTERS, SEE TABLE D-1.
3. KEYS WITH (0) MUST BE USED WITH ANOTHER KEY TO GENERATE A CODE.
4. "SHIFT" OR "cTRL" PLUS "BREAK STOP" GENERATES HEX CODE 03.
5. KEYS WITH (00) (PFI7 TO PF22) GENERATE THE SPECIAL CODES SHOWN BELOW.

FNC
FNC
FNC
FNC
FNC
FNC

PFI7
PFI8
PFI9
PF20
PF21
PF22

ESCOO
ESCOP
ESCOQ
ESCOIR
ESCO'S
ESCO'T

PFI7
PFI8
PFI9
PF20
PF21
PF22

ESCOIU
ESCOV
ESC OW
ESC O'X
ESCOY
ESCOZ

Figure D-3 Keyboard Layout Showing Hex Codes For Special Keys

D-8

BREAK
STOP (13)

(2A)

- l(10)

LEAR PRINT
HOME
(IE)
(10)

Appendix E

110 Port Addresses and
Instructions
The I/O port addresses and instructions for all devices are listed in Tables E-l to
E-21.
Data bus bit descriptions are listed left to right as Bits 7 through 0 for low order
bytes and Bits 15 through 8 for high order bytes.

E-l

Table E-l 110 Port Address and Instructions for the DMA Controller

READ/
WRITE

ADDRESS

CHO Address Read

R

01

CHO Address Write

W

01

CHO Word Count R.

R

11

CHO Word CountW.

W

11

CH 1 Address Read

R

03

CHI Address Write

W

03

CHI Word Count R.

R

13

CHI Word Count W.

W

13

CH2 Address Read

R

05

CH2 Address Write

W

05

CH2 Word Count R.

R

15

CH2 Word CountW.

W

15

CH3 Address Read

R

07

CH3 Address Write

W

07

INSTRUCTION

B-2

110

DATA BUS
A7
AI5
A7
A15
W7
WI5
W7
WI5
A7
AI5
A7
AI5
W7
WI5
W7
WI5
A7
AI5
A7
AI5
W7
WI5
W7
WI5
A7
AI5
A7
AI5

A6
AI4
A6
AI4
W6
WI4
W6
WI4
A6
AI4
A6
AI4
W6
WI4
W6
WI4
A6
AI4
A6
AI4
W6
WI4
W6
WI4
A6
AI4
A6
AI4

A5
A13
A5
AI3
W5
W13
W5
W13
A5
A13
A5
AI3
W5
W13
W5
WI3
A5
A13
A5
A13
W5
W13
W5
W13
A5
A13
A5
A13

A4
AI2
A4
AI2
W4
WI2
W4
WI2
A4
AI2
A4
AI2
W4
WI2
W4
WI2
A4
AI2
A4
AI2
W4
WI2
W4
WI2
A4
AI2
A4
AI2

A3
All
A3
All
W3
Wll
W3
WII
A3
All
A3
All
W3
WII
W3
Wll
A3
All
A3
All
W3
Wll
W3
WII
A3
All
A3
All

A2
AlO
A2
AlO
W2
WlO
W2
WlO
A2
AlO
A2
AlO
W2
WlO
W2
WlO
A2
AlO
A2
AlO
W2
WlO
W2
WlO
A2
AlO
A2
AlO

Al
A9
Al
A9
WI
W9
WI
W9
Al
A9
Al
A9
WI
W9
WI
W9
Al
A9
Al
A9
WI
W9
WI
W9
Al
A9
Al
A9

AO
A8
AO
A8
WO
W8
WO
W8
AO
A8
AO
A8
WO
W8
WO
W8
AO
A8
AO
A8
WO
W8
WO
W8
AO
A8
AO
A8

Table E-l 1/0 Port Address and Instructions for the DMA Controller (cont'd)
READ/
WRITE

I/O
ADDRESS

CH3 Word Count

R

17

W7 W6 W5 W4 W3 W2 WI
WI5 WI4 WI3 WI2 Wll WIO W9

WO
W8

CH3 Word Count

W

17

W7 W6 W5 W4 W3 W2 WI
WI5 WI4 WI3 WI2 Wll WlO W9

WO
W8

DMA Status Read

R

09

RQ3 RQ2 RQI

DMA Command
Write

W

09

KS

DS

Illegal

R

19

-

-

Write Request
Register

W

19

-

Illegal

R

OB

Write Single Mask

W

OB

Illegal

R

IB

Write Mode

W

IB

Illegal

R

OD

-

-

Clear F/F

W

OD

-

Read Temporary
Register

R

ID

Master Clear

W

Illegal
Illegal
Illegal
Write All Mask

INSTRUCTION

DATA BUS

RQO TC3

TC2 TCI

TCO

WS

PR

TM

CE

AH

MM

-

-

-

-

-

-

-

-

-

RB

CSI

CSO

-

-

-

-

-

-

-

-

-

-

-

-

-

MK

CSI

CSO

-

-

-

-

-

-

-

MSI MSO ID

AT

TRI

TRO

CSI

CSO

-

-

-

-

-

-

-

-

-

-

D7

D6

D5

D4

D3

D2

DI

DO

ID

-

-

-

-

-

OF

-

-

-

R

-

-

-

-

-

W

OF

-

-

-

-

-

-

-

-

R

IF

-

-

-

-

-

-

IF

-

-

W

-

-

-

MB3 MB2 MBI MBO

E-3

Table E-2 liD Port Addresses and Instructions for the Interrupt Controller
INSTRUCTION

E-4

READI
WRITE

110
ADDRESS
20

D7

D6

D5

D4

D3

D2

DI

DO

EOI

DATA BUS

Read IRR/ISR/IRL

R

OCW2

W

20

R

SL

0

0

L2

LI

La

OCW3

W

20

0

ESM SMMa

I

P

PR

RIS

ICWI

W

20

a

a

a

I

a

a

a

I

Read Mask R.

R

22

-

M6

M5

M4

M3

M2

MI

MO

OCWI

W

22

-

M6

M5

M4

M3

M2

MI

Ma

ICW2

W

22

T7

T6

T5

T4

T3

a

0

a

ICW3

W

22

I

a

0

0

a

a

a

a

ICW4

W

22

0

0

0

a

a

0

a

I

R

24

W

24

R

26

W

26

Read IRR/ISR/IRL

R

28

D7

D6

D5

D4

D3

D2

DI

DO

OCW2

W

28

R

SL

EOI

0

0

L2

Ll

La

OCW3

W

28

a

ESM SMMO

I

P

PR

RIS

ICWI

W

28

0

0

I

a

a

0

I

Read Mask R.

R

2A

MI4 M13 MI2 MIl MIO M9

M8

M7

OCWI

W

2A

M14 M13 MI2 MIl

MIO M9

M8

M7

ICW2

W

2A

T7

T6

T5

T4

T3

0

0

0

ICW3

W

2A

0

0

0

0

0

I

I

I

ICW4

W

2A

0

0

0

0

a

0

a

I

a

Table E-3

va Port Addresses and Instructions for the Interval Timer
READ/
WRITE

I/O
ADDRESS

Read Counter 0

R

29

C7
CIS

C6
CI4

CS
CI3

C4
CI2

C3
CII

C2
CIO

CI
C9

CO
C8

Load Counter 0

W

29

C7
CIS

C6
CI4

CS
CI3

C4
CI2

C3
CII

C2
CIO

CI
C9

CO
C8

Read Counter I

R

2B

C7
CIS

C6
CI4

CS
Cl3

C4
CI2

C3
Cil

C2
CIO

CI
C9

CO
C8

Load Counter I

W

2B

C7
CIS

C6
CI4

CS
Cl3

C4
CI2

C3
CII

C2
CIO

CI
C9

CO
C8

Read Counter 2

R

2D

C7
CIS

C6
Cl4

CS
CI3

C4
CI2

C3
Cli

C2
ClO

CI
C9

CO
C8

Load Counter 2

W

2D

C7
CIS

C6
CI4

CS
CI3

C4
CI2

C3
CII

C2
CIO

Cl
C9

CO
C8

No Operation

R

2F

-

-

-

-

-

-

Write Mode

W

2F

SCI

SCO

RLI

RLO

INSTRUCTION

DATA BUS

-

M2

-

MI

MO

BCD

E-5

Table E-4 1/0 Port Addresses and Instructions for the Serial 1/0 Communications Controller
Number 1
READ/
WRITE

110
ADDRESS

Read Data

R

30

RD7 RD6 RD5 RD4 RD3 RD2 RDI

RDO

Write Data

W

30

SD7 SD6 SD5

SD4 SD3

SD2 SDI

SDO

Read Status

R

32

DR

SYN FE

OE

PE

TE

RR

TR

Write Mode (A)

W

32

S2

SI

EP

PEN L2

Ll

B2

Bl

Write Mode (S)

W

32

SCS

ESD EP

PEN L2

Ll

0

0

Write Command

W

32

EH

IR

RS

RST SBR REN ER

Write Mask

W

34

0

0

0

0

Read Signal

R

34

Write Signal

W

36

R

36

INSTRUCTION

DATA BUS

0

-

-

0

0

TXE RXR

0

0

-

0

TEN
TXR

CS

CI

CD

0

0

TDC

Table E-5 1/0 Port Addresses and Instructions for the Serial 110 Communications Controller
Number 2
READ/
WRITE

110
ADDRESS

Read Data

R

31

RD8 RD7 RD6 RD5 RD4 RD3 RD2

RDI

Write Data

W

31

SD8 SD7 SD6 SD5

SD4 SD3

SD2

SDI

Read Status

R

33

DR

SYN FE

OE

PE

TE

RRDY TRDY

Write Mode (A)

W

33

S2

SI

EP

PEN L2

Ll

B2

Bl

Write Mode (S)

W

33

SCS

ESD EP

PEN L2

Ll

B2

Bl

Write Command

W

33

EH

IR

RS

RST SBR REN ER

Write Mask

W

35

0

0

0

0

Read Signal

R

35

Write Signal

W

37

INSTRUCTION

E-6

DATA BUS

0

-

-

0

0

0
-

0

TXE RXR

TEN
TXR

SCA CS

CI

CD

0

0

TDC

0

Table E-6 VO Port Addresses and Instructions for the DMA Address Registers
INSTRUCTION

READ!
WRITE

110
ADDRESS

CHO Read Address R.

R

38

CHO Write Address R.

W

38

CH I Read Address

R

3A

CHI Write Address R.

W

3A

CH2 Read Address

R

3C

CH2 Write Address R.

W

3C

CH3 Read Address

R

3E

CH3 Write Address R.

W

3E

DATA BUS

0

0

0

0

AI9

AI8

AI7

AI6

0

0

0

0

AI9

AI8

AI7

AI6

0

0

0

0

AI9

AI8

AI7

AI6

0

0

0

0

AI9

AI8

AI7

A16

Table E-7 1/0 Port Addresses and Instructions for the CRT Controller
READ!
WRITE

I/O
ADDRESS

Read Status

R

40

LP

lIP

VS

DMADW

FE

FF

DR

Write Parameter

W

40

P7

P6

P5

P4

P3

P2

PI

PO

Read Data

R

42

D7

D6

D5

D4

D3

D2

DI

DO

Write Command

W

42

C7

C6

C5

C4

C3

C2

CI

CO

Reset Intr.

W

46

INSTRUCTION

DATA BUS

GDC TM

APU CRT

E-7

Table E-8 VO Port Addresses and Instructions for the Graphics Display Controller
READ/
WRITE

110
ADDRESS

Read Status

R

70

LP

HB

VS

DMADW

FE

FF

DR

Write Parameter

W

70

P7

P6

P5

P4

P3

P2

PI

PO

Read Data

R

72

D7

D6

D5

D4

D3

D2

Dl

DO

Write Command

W

72

C7

C6

C5

C4

C3

C2

Cl

CO

-

-

-

-

-

-

110

INSTRUCTION

Graph Enable
NOTE: For Graph Enable, I
Always is selected.

W

76

DATA BUS

-

= Release From Blanking Status; 0 = Blanking Always.

At power on, Blanking

Table E-9 VO Port Addresses and Instructions for the Keyboard Controller
READ/
WRITE

110
ADDRESS

Read Data

R

48

SD8

Buzzer Set

W

48

-

Read Status

R

4A

Buzzer Reset

W

4A

Read Signal

R

4C

SW8 SW7 SW6 SW5 SW4 SW3 SW2 SWI

Read Book/Page

R

4E

B4

B3

B2

Bl

P4

P3

P2

PI

Read Shift

R

4E

0

0

0

0

SF4

SF3

SF2

SFI

F2B

FIB

FOB

D3

D2

Dl

DO

C3

C2

Cl

CO

INSTRUCTION

DATA BUS
SD7 SD6 SD5 SD4 SD3
-

-

-

SD2 SDI

-

-

-

-

TP2

TPI

TPO

ALM

-

Table E-IO 1/0 Port Addresses and Instructions for the FDD Controller
READ/
WRITE

110
ADDRESS

Read Status

R

50

RQM DIO NDMFCB F3B

Read Data

R

52

D7

INSTRUCTION

Write Command

E-8

W

52

DATA BUS

C7

D6
C6

D5
C5

D4
C4

Table E-ll 1/0 Port Addresses and Instructions for the Clock and Calendar
READ/
WRITE

110
ADDRESS

Read Data

R

58

-

-

-

-

Set Register

W

58

0

0

DI

CLK STB C2

INSTRUCTION

DATA BUS

-

-

BATTDO
Cl

CO

Table E-12 I/O Port Address and Instruction for the BBM Enable

INSTRUCTION
BBM Enable

READ/
WRITE

I/O
ADDRESS

W

59

DATA BUS
ENB

Table E-13 I/O Port Addresses and Instructions for the APU
READ/
WRITE

I/O
ADDRESS

Read Data

R

5A

07

06

05

04

03

02

01

DO

Write Data

W

5A

07

06

05

04

03

02

01

DO

Read Status

R

5E

B

S

Z

E3

E2

El

EO

CRY

Write Command

W

C5

C4

C3

C2

Cl

CO

INSTRUCTION

5E

DATA BUS

C7

C6

Table E-14 I/O Port Address and Instruction for the Power Off Control

INSTRUCTION
Power Off

READ/
WRITE

I/O
ADDRESS

W

5B

DATA BUS
OFF

E-9

Table E-15 1/0 Port Addresses and Instructions for the Sound Control
READ/
WRITE

110
ADDRESS

Write Command

W

60

0

FS

C5

C4

C3

C2

CI

CO

Read Status

R

60

S7

S6

S5

S4

S3

S2

Sl

SO

INSTRUCTION

DATA BUS

Table E-16 I/O Port Addresses and Instructions for the Timer
READ/
WRITE

I/O
ADDRESS

Read Counter 0

R

61

C7
Cl5

C6
Cl4

C5
Cl3

C4
Cl2

C3
CII

C2
CIO

Cl
C9

CO
C8

Load Counter 0

W

61

C7
CI5

C6
CI4

C5
CI3

C4
CI2

C3
CII

C2
CIO

CI
C9

CO
C8

W

63
63
65
65
67
67

SCI

SCO

RLI

RLO M2

MI

MO

BCD

INSTRUCTION

Write Mode

E-lO

DATA BUS

Table E-17 1/0 Port Addresses and Instructions for the ODA Controller Number 1
READ/
WRITE

110
ADDRESS

Read Signal

R

68

DCN 0

Write Data

W

6A

RD8 RD7 RD6 RD5

Write Signal 2

W

6C

IRT

Write Signal 0

W

6E

1

0

0

1

0

1

0

0

Write Signal 1

W

6E

0

0

0

0

0

1

0

INTE

Write Signal 1

W

6E

0

0

0

0

0

1

1

RMS

Write Signal 1

W

6E

0

0

0

0

1

0

0

MASK

Write Signal 1

W

6E

0

0

0

0

1

1

1

IRT

INSTRUCTION

DATA BUS
DPQ MDL

ALM RMR 0

0

RD4 RD3 RD2 RDI

MASK

Table E-18 1/0 Port Addresses and Instructions for the IDA Controller
READ/
WRITE

110
ADDRESS

Read Signal

R

71

DCN IP3

Read Data

R

73

SD8 SD7 SD6

Write Signal 2

W

75

IRT

SDR SMS MASK

Write Signal 0

W

77

1

0

0

Write Signal 1

W

77

0

0

Write Signal 1

W

77

0

Write Signal 1

W

77

Write Signal 1

W

Write Signal 1
Write Signal 3

INSTRUCTION

DATA BUS
PSM

SMR IPI

SD5

SD4

SD3 SD2

SDI

1

0

1

1

0

0

0

0

1

0

INTE

0

0

0

1

0

0

MASK

0

0

0

0

1

0

1

SMS

77

0

0

0

0

1

1

0

SDR

W

77

0

0

0

0

1

1

1

IRT

W

79

IP2

SDRQSTT

SDA

E-11

Table E-19 I/O Port Addresses and Instructions for the Communications Adapter
READ/
WRITE

110
ADDRESS

Write BUFI

W

80

D7

D6

D5

D4

D3

D2

DI

DO

Read BUF4

R

80

D7

D6

D5

D4

D3

D2

DI

DO

Write BUF2

W

82

D7

D6

D5

D4

D3

D2

DI

DO

Read BUF5

R

82

D7

D6

D5

D4

D3

b2

DI

DO

DI

DO

DI

DO

INSTRUCTION

DATA BUS

Write BUF3

W

84

D7

D6

D5

D4

D3

D2

Read BUF6

R

84

D7

D6

D5

D4

D3

D2

Start DMA

W

86

-

-

-

-

-

-

Set INTI

W

88

-

-

-

-

-

Reset INT2

W

8A

-

-

-

-

Reset SDMA INT

W

8C

-

-

-

-

-

-

Reset RDMA INT

W

8E

-

-

-

-

-

-

Read INT

R

90

-

-

-

-

-

-

-

-

-

-

INTI INT2 MSDE MRDE

Table E-20 I/O Port Addresses and Instructions for the ASOP Controller
READ/
WRITE

110
ADDRESS

Low Address Set

W

FO

SA7 SA6 SA5

SA2 SAl

SAO

Mid Address Set

W

F2

SAl5 SAl4 SA13 SAl2 SAll SAlO SA9

SA8

High Address Set

W

F4

Mask Set

W

F6

Read Signal

l--

F6

INSTRUCTION

E-12

.-

DATA BUS
SA4 SA3

SAl9 SAl8 SAl7 SAl6
MASK
R/W INT

Appendix F

Hardware Specifications
FEATURE

cpu*
Word Length
Clock Rate

SPECIFICA nON
NEC pPD 8086
16 bits
5 MHz

ROM*

8K (bootstrap and self-test)

RAM
Standard Size*
Maximum Size

64K chips, 200 ns Access Time
128 KB
256 KB

Memory with Battery Backup*

4 K (CMOS)
Two-year life
Can be protected against accidental writing

1/0 Facilities
Standard*
Printer
RS-232C

Optional

Other Standard Features*
Music

Parallel
Asynchronous and Synchronous at speeds up
to 19,200 bps
Software Emulators for all important IBM
Workstations and Communications
subsystems
Second RS-232C Port
Pitch Range: 2 + Octaves
Number of Tempos: 4
Note Duration: thirty-second to whole
Dynamics: piano, medium, forte accent

*Standard Feature, included with Basic Unit

F-l

FEATURE
OfJter Standard Features* (cont.)
Alarm
Clock/Calendar
Automatic Power Off
Lithium Battery

Flexible Disk Drives*
Packaging
Size
Formatted Capacity (each)
Single-Sided, Single-Density
Double-Sided, Double-Density
Standard Number of Drives
Maximum Number of Drives
Maximum Disk Capacity
Disk Performance Characteristics
Rotation Rate
Head Settle Time
Track-track Time
Transfer Rate
Display Screen*
Size (Diagonal)
Lines x Columns
Character Set
Predefined*
U ser-Definable*
Monochrome* Phosphor Type
Video Interface
Color
Virtual Graphic Area Size
Real Graphic Window Size

SPECIFICA nON
Pitch: 4 selectable frequencies
Length: 20 ms or continuous
Loudness: 3 levels
Hardware (with battery backup)
Can be initiated locally or remotely
Backs up CMOS RAM and
Clock/ Calendar
Two-year life
Integrated (one* or two)
8 in.
243 KB }
1 MB

monochrome model - one
color model - two
two
2MB
360 rpm
50 ms
5 ms
62.5 KB/sec

12 in.
25 x 80 plus status line
250 Symbols (8 x 19 matrix)
256 Symbols (all displayable and printable)
Green Black
Integrated CRT Display
8-color (high res. 640 x 475 pixels)
1,024 x 1,024 pixels
640 x 475 pixels - 8-color

*Standard Feature, included with Basic Unit

F-2

Both supported

FEATURE
Display Screen* (cont.)
Character Graphics*

Line Drawing

SPECIFICATION
Overline, underline, vertical line, highlight,
inverse video, blinking, secret
Line segment, rectangle, arc, circle

Keyboard*
Number of Keys
(excluded in Programmable
Function Keys)
Number of Programmable
Function Keys
Numeric Pad

22, Dual Mode (effectively, 44)
Standard

Standard Printer
Type
Speed
Controller*

Dot Matrix
100 Characters per second
Standard

Dimensions
Main Enclosure

Keyboard

86

19.7 in. (50 cm) wide x 13.8 in. (35 cm)
high x
monochrome: 18.1 in. (46 cm) deep
color: 19.9 in. (50.5 cm) deep.
19.7 in. (50 cm) wide x 2.4 in. (6 cm) high x
9.1 in. (23 cm) deep

*Standard Feature, included with Basic Unit

F-3

Glossary
A

Abbreviation for Ampere.

ADO to AD15 Address and Data lines 0 to 15; bus interface channels. See Chapter
2 for information.
Address Bus A set of parallel conductors that carry address codes from the
microprocessor to memory and I/O devices.
ALE

Address Latch Enable.

AND A logic operator having the property that if P is a statement, Q is a
statement, R is a statement... , then the AND of P,Q,R .. .is true if and only if all
statements are true, false if any statement is false.
ANSI American National Standards Institute; an organization that develops and
publishes industry standards, including terminology and standard codes.
APC

Advanced Personal Computer.

ASCII American Standard Code for Information Interchange; this standard
defines character set codes that are used for data interchange between equipment
of different manufacturers. This code defines 96 displayed characters (64 without
lowercase) and 32 non-displayed controls in terms of 7 bits (plus an eighth bit for
parity check).
Assembler A computer program that prepares a machine-language program from
a symbolic language program.
Asynchronous

Without relation to a regular time period.

G-l

A method of transmitting data in which the timing
of character placement on connecting transmitting lines is not critical. The
transmitted characters are preceded by a start bit and followed by one or more
stop bits; this designates individual characters and allows the interval between
characters to vary.

Asynchronous Communications

In the APC, one of eight supplements that can accompany a
character on the display screen.

Attribute, Character

A16 to A19

Address bits 16 to 19; bus interface channels.

Beginner's All-purpose Symbolic Instruction Code; a common, highlevel, numerical-application-oriented, computer program language that is easily
learned.

BASIC

(l) A unit of signaling speed equal to the number of discrete conditions or
signal events per second. For example, one baud equals one-half dot cycle per
second in Morse code, one bit per second in a train of binary signals, and one
3-bit value per second in a train of signals each of which can assume one of eight
different states. (2) In asynchronous transmission, the baud is a unit of modulation rate that equals the unit intervals.

Baud

BBM

Battery-Backed Memory.

BHE

Bus High Enable; a bus-interface channel. See Chapter 2.

(1) A condition that can have exactly two values; for example, ON and
OFF, 1 and O. (2) A numbering system that includes the digits zero and one and
uses two as its base; that is, the base-2 numbering system.

Binary

Positional notation in which the individual decimal
digits are represented by a set of four binary numerals; for example, the number
twenty-three is represented by 0010 0011 in binary-coded decimal notation, and
by 10111 in binary notation.

Binary-Coded Decimal (BCD)

A technique or device designed to bring itself into a desired state by
means of its own action; for example, a machine routine whose first few instructions are sufficient to bring the rest of itself into the computer from an input
device.

Bootstrap

G-2

Buffer A temporary storage area between devices used to compensate for differences in data flow rates or in the occurrence of events; a storage area that
temporarily holds input or output data.
Bus A number of parallel conductors (usually 8 or 16, sometimes 20) used for
transmitting data signals or power; for example, address bus, data bus.
Byte A sequence of adjacent binary digits (eight digits in most machines including
the APC) operated upon as a unit and usually shorter than a computer word (a
word is composed of two bytes in the APC).
C/D (CONTROL/DATA) An input signal of the NEC 8251A Communications
Controller. See Chapter 3.
Central Processing Unit (CPU) (1) A unit of a computer that includes the circuits
controlling the interpretation and execution of instructions. (2) In the APC, the
NEC J.lPD8086 microprocessor.
Chip A tiny piece of semiconductor material on which microscopic electronic
components are photoetched to form one or more circuits. After connector leads
and a case are added, it is called an integrated circuit.
CLKO

Communications Clock; a bus-interface channel. See Chapter 2.

COBOL Common Business Oriented Language; a business data processing
language.
Clock (1) The basic source of synchronizing signals in the microcomputer; PHIO
in the APC. (2) Indata communications, the clock - CLKO in the APC - that
controls the timing of signal sending and receiving.
CMOS

Complementary Metal Oxide Semiconductor

Code (1) A system for representing data according to unambiguous rules; e.g. a
binary decimal code. (2) Within a given machine or storage location, a system of
binary digits given certain arbitrary meanings, used for transmitting information; for example, in the APC, character code, character-attribute code, command code. (3) To change the symbolic representation of data or commands in
order to make them conform to such a system.

G-3

Communications Refers to communication between computers or between computers and terminals. Information is transmitted with synchronous or asynchronous timing, and in serial-data or parallel-data form.
Computer A data processor capable of high-speed mathematical or logical calculations, able to assemble, store, and otherwise process information derived from
coded data in accordance with a predetermined program.
CP/M Control Program For Microprocessors; a registered trademark of Digital
Research, an operating system that comprises four subsystems: basic inputoutput system (BIOS), basic disk-operating system (BDOS), console command
processor (CCP), and transient program area (TPA). Programs that are created,
edited, debugged, assembled, and executed on one CP/M-based configuration
run on all CP/M-based configurations. CP/M is thus a standard interface
between user programs and system hardware. Among the high-level languages
that currently run with CP/M are BASIC, COBOL, FORTRAN, Pascal, APL,
and PL/I.
CRT Cathode Ray Tube; a vacuum tube in which electrons are accelerated to and
focused upon a fluorescent screen.
CRT Display Unit In the APC, the equipment that receives data and transforms it
into visible images on the CRT display screen. Specifically, the unit includes a
cathode ray tube, display control, display screen, horizontal driver, and vertical
driver.
CS

Code Segment

CS (Chip Select) An input signal of the Intel 8251 A Communications Controller.
See Chapter 3.
DACKO to DACK3 DMA-request Acknowledgement 0 through 3; bus-interface
channels. See Chapter 2.
Data (I) A representation of facts, concepts, or instructions in a formalized
manner suitable for communication, interpretation, or processing by humans or
automatic means. (2) Any representations such as characters or analog quantities
to which meaning is or might be assigned.

G-4

DIP Dual In-Line Package; a popular IC packaging container that has two
parallel rows (hence dual) of leads, which connect the unit to a circuit board.
They are available in a variety of configurations, from 14-pin to 40-pin
assemblies.
Disk, Flexible A type of magnetic disk, so named because it is soft and bends
easily; also called floppy disk.
Disk, Hard Conventional magnetic disk that is stiffer than a flexible disk, contains
more concentrated data, and can be read faster.
Disk, Magnetic A flat circular plate with a magnetic surface on which data can be
stored by selective magnetization of portions of the flat surface.
Display Position A unit on the video display screen capable of containing one
character; that is, each display unit holds one character box. The APC video
display has 25 lines of80 display positions; and each display position is composed
of an 8 x 19 dot matrix.
DMA Direct Memory Access; high-speed data transfer operation in which an I/O
channel transfers information directly to or from the memory. Transfers take
place with no microprocessor intervention using a "cycle-stealing" method. Also
called" data break."
DMC

DMA Cycle; a bus-interface channel. See Chapter 2.

Double Density Refers to a type of magnetic disk storage organization in which
256 characters of information are stored on each sector of a track. Compare with
single density.
DRQO to DRQ3
DS

DMA Request 0 to 3, bus interface channels. See Chapter 2.

Data Segment

DT/R

Data Transmit or Receive; a bus-interface channel. See Chapter 2.

EIA Electronics Industries Association; an electronics trade association that formulates and establishes industry standards.

G-5

EPROM Erasable Programmable Read-Only Memory. Like a PROM, it is a
programmable read-only memory, but unlike an ordinary PROM its contents
can be erased and rewritten more than once. Like any ROM device, an EPROM
retains its contents indefinitely.
FDC

Flexible Disk Controller.

FDD

Flexible Disk Drive.

FIFO

First-In First-Out.

Firmware Refers to microprocessors and other software that have been permanently written into ROM chips; for example, the bootstrap loader is a firmware
program.
Fixed-Point Arithmetic Computer calculations in which the computer does not
consider the radix point. Compare floating-point arithmetic.
Flag An indicator used to specify the status of a designated condition. A flag is
usually one or two bits and can be hardware- or software-implemented.
Floating-Point Arithmetic Arithmetic procedures in which the computer keeps
track of the radix point. Compare fixed-point arithmetic.
FM

Frequency Modulation.

Full Duplex In communications, pertains to simultaneous two-way independent
transmission in both directions; also called duplex. Compare with half duplex.
GDC

Graphic Display Controller.

Half Duplex In communications, pertains to an alternate, one-way-at-a-time
independent transmission. Compare with full duplex.
Hexadecimal (HEX)
Refers to the number system with 16 as its base. The
hexadecimal system uses 16 symbols: 0 to 9, and A to F for the base-lO numbers
lO to 15. One hexadecimal digit can be represented by four bits.
Hertz (Hz)

G-6

A unit of frequency equal to one cycle per second.

Highlighting A method used to distinguish or emphasize data on a CRT Display.
There are a number of methods: reversing the field, blinking, underlining,
changing color, changing light intensity, or some combination of these. The APC
features all of these highlighting methods.
High-Order Position In this manual (and in general), the left-most position in a
string of digits, characters, or bytes. A high-order position is more significant
than a low-order position.

lew

Initialization Command Word.

Impact Printer A printer that forms characters by physically striking the paper
through a ribbon; for example, conventional typewriters print this way.
Input/Output (I/O) Pertaining to a hardware device that can transmit data into or
receive data from a computer.
Integrated Circuit (IC) A micro unit consistmg of interconnected elements,
inseparably associated and formed on or within a single substrate to function as
an electronic circuit.

A large semiconductor designer, manufacturer, and distributor.

Intel

Interlace To assign successive storage location numbers to physically separate
storage locations; this reduces access time.
Interrupt (1) A suspension of the normal flow of a process in such a way that the
flow can be resumed. (2) A special control signal from an 110 device that diverts
the attention of the CPU from the program to a specific address.
lOR

110 Read; a bus-interface channel. See Chapter 2.

lOW

1/0 Write; a bus-interface channel. See Chapter 2.

IP

Instruction Pointer.

IRO to IR14
IRR
IRST

Interrupt Request 0 to 14; bus-interface channels. See Chapter 2.

Read Interrupt Register.
Initial Reset; a bus-interface channel. See Chapter 2.

G-7

ISR

K

Read Inservice Register.

Abbreviation for kilo. (1) Prefix meaning 1000. (2) With regard to memory
space and addressing, kilo means 1024 (2 to the 10th power); for example 2K
equals 2048.

KB

Abbreviation for kilobyte; 1024 bytes.

kHz

Abbreviation for kilohertz; a unit of frequency equal to 1000 hertz.

LAD

Light Pen Address.

Low-Order Position The left-most position in a string of digits, characters, or
bytes. A low-order position is less significant than a high-order position.

LSB

Least Significant Bit.

LSI Large Scale Integration; (1) Refers to a component density of 100 or more per
chip. (2) A chip with more than 100 components.

M

Abbreviation for mega. (1) Prefix meaning 1,000,000. (2) With regard to
memory space and addressing, mega means 1,048,576 (2 to the 20th power); for
example, one MB equals one megabyte, 1,048,576 bytes.

Machine Language Binary-coded language; the only type of language that can be
directly used by the machine.
Main Unit In the APe, the Main Unit houses all the microcomputer devices
except the Keyboard and Printer. In addition, all interfaces are in or on this unit.
Matrix Printer

MB

A printer that forms characters by printing a pattern of dots.

Megabyte; 1,048,576 bytes. The addressing power of the APe.

Memory Address (1) The unique location of a word in memory. (2) In the APe, a
20-bit value that identifies a specific portion of memory.
Memory Map A symbolic representation of memory locations that defines the
boundaries of various memory segments.
MFM Modified Frequency Modulation; a magnetic-disk coding system that uses
double-density encoding of information.

G-8

MHz

Megahertz; a unit of frequency equal to one million hertz.

Microprocessor (1) The principal component of a microcomputer, it is a semiconductor central processing unit. Usually contained on a single chip, which is
mounted on a DIP, it includes an arithmetic logic unit, control logic, and
control-memory unit. (2) In the APC, the microprocessor is the NEC J.lPD8086 ,
which is mounted on a 40-pin DIP.
Mnemonic An abbreviation of two or three letters (abbreviated in a way to aid
human memory) that is used instead of terminology.
Mode Refers to various methods of operation; for example, the synchronous
versus the asynchronous mode.
Modem MOdulator-DEModulator; a device that modulates signals transmitted
over communication facilities. This device enables computers and terminals to
communicate over telephone circuits.
Monitor (1) A device that observes and verifies the operation of a data processing
system and indicates any significant departure from the norm. (2) Software or
hardware that observes, supervises, controls, or verifies the operation of a
system. (3) A video display.
MOS

Metal Oxide Semiconductor.

Mother Board A circuit board into which various printed circuit boards (PCB) are
plugged. In the APC, the Mother Board is inside the card cage and has five PCB
slots.
MR

Memory Read; a bus-interface channel. See Chapter 2.

MRQ
ms
MSB

Memory ReQuest, a bus-interface channel. See Chapter 2.

millisecond; one-thousandth of one second, 0.001 second.
Most Significant Bit.

Multiplexer A device capable of combining several low-speed inputs into one
high-speed data stream transmitted on a single channel. A demultiplexer subsequently reconverts the single data stream into low-speed inputs for the host
computer. Two kinds of multiplexers are time-division multiplexers in which the
channel is divided into time slots and frequency-division multiplexers in which
the channel is divided into frequency bands.

0-9

MW

Memory Write; a bus-interface channel. See Chapter 2.

NAND

A logical operator that is the negation of AND.

NEC Nippon Electric Company; a large manufacturer of electronics equipment,
including semiconductors and microcomputers.
NOR
ns

A logical operator that is the negation of OR.

nanosecond; one billionth of a second, 0.000000001 second.

NT

Normal Termination.

OCW

Operational Command Word.

ODA

Output Device Adapter.

OR A logic operator having the property that ifP is a statement, Q is a statement,
R is a statement..., then the OR ofP,Q,R ... is true ifat least one statement is true,
false only if all statements are false. Often represented by +, as in P + Q.
Output Pertaining to a device, process, or channel involved in an output process,
or to the data or states involved in an output process.
Overflow That portion of the result of an operation that exceeds the capacity of
the intended unit of storage.
Parallel Data Method for representing data in which characters are transmitted
and received over separate lines, usually simultaneously. Compare serial data.
Parameter In general, a quantity used to specify 110 devices or to designate
desired routines.
PCB

Printed Circuit Board.

Personal Computer A rel'atively low-cost computer that is based on tiny microcomputer chips and is therefore portable and personally controllable. Personal
computers are often classified as home, hobbyist, professional, business, small
business, appliance, and others.
PHIO
G-IO

System Clock; a bus-interface channel. See Chapter 2.

POF Power-Off Control; (I) A bus-interface channel. See Chapter 2. (2) In the
APC, a control circuit that shuts off the system power supply by a microprocessor command.

Printed Circuit Board Also called pc board, plate, card, chassis, and - in this
manual - PCB; an insulating board with metallic wiring paths for point-topoint connections, but it can also include metallized connecting surfaces and heat
sinks or heat radiators. Printed circuit boards are single-sided, double-sided, or
multilayer; all pc boards in the APC are multilayer.
Program A series of instructions or statements, in a form acceptable to a computer, prepared in order to achieve a certain result.
Programmable Array Logic (PAL) TTL Schottky bipolar devices designed to
replace standard TTL logic. They are fully programmable to provide a high
degree of design flexibility and efficiency. The basic logic implementation is the
AND-OR array, where the AND is programmable and the OR fixed. PALs are
used to make logic modification quicker and easier than with standard devices.
PROM Programmable Read Only Memory; unprogrammed upon manufacture,
can be programmed once and only once. After programming, like ROMs, they
retain their contents indefinitely.

Protocol In data communications, a specific set of rules defining the format and
content of messages between communicating devices.
P39 Phosphor Used in both the monochrome and color displays ofthe APC, it is a
yellow-green, long-persistence phosphor that provides good luminescence, small
dot size, and good focus.
RAM

Random Access Memory. See Read/Write Memory.

Raster Scan A technique of graphics CRT displays; it operates by varying the
intensity of a beam that periodically scans left-to-right and top-to-bottom. This
CRT graphics method is the type used in the APC and conventional home TV; it
is the only method that makes full color display possible.

RD

READ; an input signal of the NEC 8251A Communications Controller. See
Chapter 3.

RDY

Ready; a bus-interface channel. See Chapter 2.
G-II

Read/Write Memory Also called random access memory or RAM. A type of
memory in which each cell can be both sensed at appropriate output terminals
and changed in response to electrical input signals.
Refreshing A process of periodically reactivating or restoring information that
decays when left idle; for example, the phosphor on a CRT must be refreshed in
order to maintain the image, and dynamic memory cells need constant refreshing
to maintain their contents.
RFSH

Refresh; a bus-interface channel. See Chapter 2.

Register
rpm
ROM

A device capable of storing a specified amount of data such as one word.

Revolutions Per Minute.
Read-Only Memory; memory that can be read but not altered.

RS-232C Interface An interface between a modem and the associated data terminal equipment that is standardized by EIA Standard 232C.
RST RESET; an input signal of the NEC 8251 A Communications Controller. See
Chapter 3.
Serial Data Method for representing data in which the data stream is transmitted
and received as a single signal by ~ single transmission path. Compare parallel
data.
Single Density Refers to a magnetic disk storage technique in which 128 characters of information are stored on each sector ofa track. Compare double density.
Software A set of programs, procedures, and possibly associated documentation
concerned with the operation of a data processing system.
Sound Generator In general, a computer device that includes a tone-generator and
speaker for outputting tones. In the APC, the sound generator is fully programmable and capable of generating user-programmed melodies and various beep
signals.
Special Character In the APC, a character that the user can create through the
ACGGEN utility program; the programmed character is stored in display RAM
(and on disk if desired) and is accesible on command. There is storage allocation
for 256 special characters, though an indefinite number can be stored on disk.
G-12

SS

Stack Segment.

Status Register
flags.
SW

A register that provides storage for arithmetic and control status

Switch.

Synchronous
or events.

Having a constant time interval between successive bits, characters,

Synchronous Communications A method oftransmitting information in which the
timing of character placement signifies the division between characters. A data
stream of an indefinite number of characters is preceded by one or two sync bits,
which indicate where the data stream begins.
Terminal Count; a bus-interface channel. See Chapter 2.

TC
TTL

Transistor/Transistor Logic.

USART

Universal Synchronous! Asynchronous Receiver/Transmitter

V Abbreviation for Volt.
VFO
W

Variable Frequency Oscillator.

Abbreviation for Watt.

Word A group of characters that occupy one storage location and are treated as a
single entity, instruction, or quantity. In the APC, two bytes (16 bits) make up a
word.
WR (WRITE) An input signal of the NEC 8251A Communications Controller.
See Chapter 3.

0-13

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