82333C_1610_1620_Mantenance_Manual_Dec78 82333C 1610 1620 Mantenance Manual Dec78
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XEROX
Diablo Systems Incorporated
A Xerox Company
HyTerm Communications Terminal
Model 1610/1620
Maintenance Manual
82333 Rev. C
December, 1978
© Copyright 1976, 1978
Diablo Systems, Inc.
Hayward, California 94545
All rights reserved
"Diablo" and "HyType" are registered trademarks of Xerox Corporation.
"Xerox" is a registered trademark of Xerox Corporation.
"HyTerm" is a trademark.
PREFACE
This manual contains only theory of operation (Section 2)
and Maintenance (Section 3) information, and schematics
and logic drawings (Section 4). Refer to the Product
Description manual, no. 82332, for operating instructions,
specifications, functional description, interface information
and installation instructions.
This revision supercedes Revision B published in December
1976. Comments on th is manual and its use are welcome.
Please address comments to Diablo Systems, Inc., 24500
Industrial Boulevard, Hayward, California 94545.
Diablo Systems, Inc., reserves the right to make
improvements to products without incurring any obligation
to incorporate such improvements in units previously sold.
WARRANTY
The Diablo Model 1610 and Model 1620 HyTerm
Communications Terminals are warranted against defects in
materials and workmanship for 90 days from the date of
shipment. Any questions with respect to the warranty
should be directed to your Diablo sales representative.
All requests for repairs should be directed to the Diablo
repair depot in your area. This will assure you of the fastest
possible service.
ii
TABLE OF CONTENTS
PAGE
PARAGRAPH
SECTION 1 - INTRODUCTION
1.1
1.2
1.3
1-1
1-1
1-1
General Description
Scope . . . .
Related Documents
SECTION 2 - THEORY OF OPERATION
2.1
2.2
2.3
Introduction . . . . . . . . . . . . . . . . . . . . . . .
HyTerm Processor (HPRO) Board, Part Nos. 23702 (HPRO 1) and 23704 (HPR02)
2.2.1
General Operation . . . . .
2.2.2
8080 Microprocessing Unit (MPU)
2.2.2.1 Architecture . . . .
2.2.2.2 Timing . . . . . .
2.2.2.3 Basic Processor Operation
2.2.3
Clock Generator (8224)
2.2.4
Bus Driver/System Controller (8228)
2.2.4.1 Bus Control
2.2.4.2 System Logic Control
2.2.4.3 Interrupt Handling
2.2.5
Memory..
2.2.5.1 Addressing.
2.2.5.2 Reading.
2.2.5.3 Writing
2.2.5.4 Timing .
2.2.6
Input/Output..
2.2.6.1 Addressing
2.2.6.2 I/O Port (8212)
2.2.6.3 Keyboard Data Input (Port 0)
2.2.6.4 Keyboard Control Switch Input (Port 1)
2.2.6.5 Control Panel Switch Inputs (Ports 2 and 3)
2.2.6.6 Baud Rate Factor (Output Port 1)
2.2.6.7 Miscellaneous Outputs (Port 0)
2.2.6.8 USART (Ports 4 and 14) . .
2.2.7
Miscellaneous Circuitry
. . . . .
2.2.7.1 3-Terminal Voltage Regulators
2.2.7.2 Level Converters. . .
2.2.7.3 Jumpers
. . . .
8080 I nterface Board, Part No. 40644-XX
2.3.1
I/O Ports 5, 6, and 7
. . . .
2.3.1.1 Transfer of Information to the Printer.
2.3.1.2 Transfer of Information from the Printer.
2.3.2
Carriage and Printwheel Position Data
2.3.2.1 Position Latches. . . .
2.3.2.2 Carriage Counter Control .
2.3.2.3 Printwheel Counter Control
2.3.3
Option Jumpers . . . . . . .
iii
2-1
2-1
2-1
2-3
2-3
2-3
2-3
2-4
2-5
2-5
2-5
2-7
2-7
2-7
2-7
2-7
2-7
2-7
2-7
2-8
2-8
2-8
2-8
2-9
2-9
2-9
2-10
2-10
2·10
2-11
2·11
2-11
2-13
2-13
2-13
2-13
2-15
2-15
2-15
SECTION 2 - THEORY OF OPERATION (Continued)
2.3.4
Oscillator.. . . .
Logic-2 Board, Part No. 40510-4X
2.4.1
Program Control Loop
2.4.2
Data Processing Loop
2.4.3
Data Output Loop
2.4.4
Basic Operation . .
2.4.5
Timing.. . . .
2.5 Servo Board, Part No. 40520-XX
2.5.1
D-A Converter Circuit .
2.5.2
Sample and Hold Circuit
2.5.3
Servo Direction Switching.
2.5.4
Servo Tachometer Circuits.
2.5.5
Servo Summation Amplifier
2.6 Transducer (XDCR) Board, Part No. 40515-03
2.6.1
Sine-Wave Drive Generator
Servo Position Transducer. . . .
2.6.2
Servo Feedback Amplifier. . . .
2.6.3
2.6.4
Servo Feedback Demodulator/Integrator/Amplifier
2.7 Carriage Power Amplifier Board, Part No. 40525-XX
2.7.1
Carriage Power Amplifier Circuit
2.7.2
Power Monitor Circuit .
2.7.3
Paper Feed Drive Circuit . . .
2.8 Printwheel Power Amplifier Board, Part No. 40530-XX
2.8.1
Printwheel Power Amplifier Circuit.
Ribbon Lift Driver Circuit. . . . . .
2.8.2
Ribbon Feed Drive Circuit. . . . . .
2.8.3
2.8.4
Hammer Energy Control and Drive Circuit
2.9 HCU R L Board (Optional) .
2.9.1
General Operation
2.9.2
Receiver Circuit .
2.9.3
Transmitter Circuit
Current Loop Operation
2.9.4
2.9.4.1 Full Duplex, Passive.
2.9.4.2 Full Duplex, Active .
2.9.4.3 Half-Duplex, Passive.
2.9.4.4 Half-Duplex, Active
2.9.5
Power Supplies . . . .
2.10 Keyboard . . . . . . . . .
2.10.1 Hall-Effect Keyboard (Schematic No. 23897)
2.10.1.1 Key Encoding . . .
2.10.1.2 Mos Decoder/Encoder
2.10.1.3 Strobe Generation
2.10.1.4 Output Drivers
2.10.1.5 Logic Levels
2.10.2 Saturable-Core Keyboard (Schematic No. 400512-01)
2.10.2.1 Basic Operation . . . .
2.10.2.2 Keyswitch . . . . . .
2.10.2.3 Encoder/Decoder/Processor
2.10.2.4 Address Logic. .
2.10.2.5 Keyswitch Matrix
2.10.2.6 Sense Amplifier .
2.10.2.7 Strobe Logic . .
2.10.2.8 Function Key Logic.
2.4
iv
2-15
2-15
2-16
2-16
2-16
2-16
2-16
2-16
2-18
2-18
2-18
2-21
2-21
2-23
2-23
2-23
2-23
2-25
2-27
2-27
2-28
2-28
2-30
2-30
2-31
2-31
2-31
2-32
2-32
2-32
2-34
2-34
2-36
2-36
2-36
2-36
2-36
2-37
2-37
2-37
2-38
2-38
2-39
2-39
2-39
2-39
2-40
2-40
2-41
2-42
2-42
2-42
2-43
SECTION 2 - THEORY OF OPERATION (Continued)
2.11 Control Panel. . . . . .
2.11.1 Switches
. . . .
2.11.2 Form Length Switch
2.11.3 Audible Alarm
2.11.4 Indicators . . . .
2.12 Power Supply. . . . . .
2.12.1 Boschert Power Supply Part No. 26021-XX
2.12.1.1
General Description .
2.12.1.2
Isolation
. . . . .
2.12.1.3
Theory of Operation
2.12.1.4
Input Current Limiting.
2.12.1.5
Input RFI Filter . . .
2.12.1.6
Full-Wave Bridge Rectifier.
2.12.1.7
Local +15 Volt Power Supply
2.12.1.8
Power Switch and Switching Regulator Amplifier
2.12.1.9
LC Smoothing Filter
2.12.1.10 Spike Catcher . .
2.12.1.11 Inverter. . . . .
2.12.1.12 DC Output Circuits .
2.12.1.13 +5 Volt Error Amplifier
2.12.1.14 Opto-Isolator. . . .
2.12.1.15 Output Current Limiting Sense Amplifier.
2.12.1.16 Overvoltage Protection. .
2.12.2 LH R Power Supply, Part No. 400062-01
2.12.2.1
Detailed Description.
2-43
2-45
2-45
2-45
2-45
2-45
2-45
2-45
2-46
2-46
2-46
2-46
2-46
2-46
2-47
2-47
2-47
2-47
2-47
2-47
2-47
2-48
2-48
2-49
2-49
SECTION 3 - MAINTENANCE
3.1
3.2
3.3
3.4
Introduction . . . .
3.1.1
General Rules.
3.1.2
Top Cover Removal
Maintenance Procedures
3.2.1
Supplies....
Cleaning and Inspection
3.2.2
Lubrication
3.2.3
Carrier System
3.2.3.1
Carriage System
3.2.3.2
3.2.3.3
Platen System .
3.2.4
Covers and Switches. . .
Module/Subassembly Removal and Replacement
3.3.1
Circuit Boards. . . . . . . . .
3.3.1.1
HCU R L Board Field Installation.
Power Supply .
3.3.2
3.3.3
Control Panel. . . . . . . .
3.3.4
Keyboard . . . . . . . . .
3.3.4.1
Keyswitch Replacement
3.3.5
Cooling Fan . . . . .
Paper Feed Motor
3.3.6
Paper Carrier Subassembly.
3.3.7
3.3.8
Carriage Subassembly
Adjustments .
3.4.1
Printer
Printer Quality Test .
3.4.1.1
v
3-1
3-1
3-1
3-2
3-2
3-3
3-3
3-3
3-5
3-5
3-5
3-6
3-6
3-6
3-9
3-10
3-11
3-11
3-12
3-12
3-13
3-15
3-18
3-18
3-18
SECTION 3 - MAINTENANCE (Continued)
3.4.1.2
3.4.1.3
3.4.1.4
3.4.1.5
3.5
Paper Carrier System
Carriage Drive Cable.
Print Quality Adjustments.
Bottom-Feed Paper Chute .
Control Panel
3.4.2
Volume Control
3.4.2.1
Power Supply.
3.4.3
Keyboard
3.4.4
3.4.4.1
Keyswitches
Cover-Open Switch
3.4.5
Paper-Out Switch.
3.4.6
3.4.6.1
Top-Feed
Bottom Feed (Optional)
3.4.6.2
Component Identification .
Reference Designator System.
3.5.1
Coordinate System
3.5.2
Pin Numbering
3.5.3
3.5.3.1
Discrete Semiconductors
3.5.3.2
Circu it Boards and Mother Board
3.5.3.3
Keyboard Cable
3.5.3.4
Control Panel .
3.5.3.5
EIA Cable
Power Supply .
3.5.3.6
3-19
3-20
3-20
3-28
3-29
3-29
3-29
3-31
3-31
3-31
3-31
3-31
3-32
3-32
3-32
3-33
3-33
3-33
3-33
3-37
3-37
3-38
3-38
SECTION 4 - SCHEMATICS AND REFERENCE INFORMATION
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4-1
4-1
4-2
4-2
4-2
4-67
4-67
Introduction
Functional Logic.
Signal Nomenclature
Logic Symbology.
Integrated Circu its
ASC II Code Chart
Schematics and Logic Drawings
vi
LIST OF ILLUSTRATIONS
FIGURE
1-1
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
2-22
2-23
2-24
2-25
2-26
2-27
2-28
2-29
2-30
2-31
2-32
2-33
2-34
2-35
2-36
2-37
2-38
2-39
2-40
2-41
2-42
2-43
2-44
2-45
2-46
2-47
2-48
2-49
PAGE
HyTerm Communications Terminal.
HyTerm Block Diagram
. . . .
HPRO Board Block Diagram . . .
Typical Instruction Cycle (Output Instruction)
MPU I nstruction Format . . . . . .
MPU Status and Resultant Control Signals
Memory Timing . . . . . . . . . .
USART Control/Status Words . . . .
Block Diagram, 8080 INTERFACE Board
Carriage Counter Decrement Control .
Block Diagram, LOGIC-2 Board. . .
Basic Operation, Printer Microprocessor
Basic Timing, Printer Microprocessor
Block Diagram, SERVO Board
D-A Converter. . . . . . . .
Typical Sample and Hold Circuit
Carriage Position Tachometer Circuit
CAR POS Tachometer Waveforms .
CAR POS F ET I nput Waveforms
Sinewave Drive Generator Waveforms
Servo Position Transducer. . . .
Servo Feedback Amplifier. . . .
Servo Feedback Amplifier Waveforms
Servo Feedback Demodulator/Integrator/Amplifier
Servo Feedback Demodulator/Integrator/Amplifier Waveforms
CAR POS SIG Development . . . . . .
Simplified Diagram, Carriage Power Amplifier
Servo Feedback Circuit. . . . . .
Power Monitor Circuit. . . . . .
Paper Feed Stepping Motor Operations
Paper Feed Drive Waveforms. . . .
Hammer Energy Control Circuit. . .
Block Diagram, Current Loop Data Flow.
Receiver Circuit . . .
Transmitter Circuit . . . . . . . .
Current Loop Operation . . . . . .
Key Positions of Hall-Effect and Saturable-Core Keyboards.
Block Diagram of Hall-Effect Keyboard .
Keyboard Strobe Generation. . . . . .
Block Diagram, Saturable-Core Keyboard
Timing Cycle, Cortron Keyboard
Sense Amplifier TPA and TPB
Block Diagram, Boschert Power Supply
Block Diagram, LH R Power Supply. .
LHR Simplified Input Rectifier/Filter/Doubler Section (115 VAC Input Strapping) .
LHR Simplified Input Rectifier/Filter/Doubler Section (230 VAC Input Strapping) .
LHR Simplified Transistor Chopper (Half-Wave)
LH R Power Supply Waveforms . . . . . .
LHR Control Module Block Diagram . . . .
LH R Control Module Timing Diagram (SG3524)
vii
1-0
2-0
2-2
2-3
2-4
2-5
2-6
2-10
2-12
2-14
2-14
2-16
2-17
2-17
2-19
2-19
2-20
2-20
2-21
2-22
2-22
2-23
2-24
2-25
2-25
2-26
2-27
2-27
2-28
2-29
2-30
2-32
2-33
2-33
2-34
2-35
2-36
2-37
2-39
2-40
2-41
2-43
2-44
2-48
2-49
2-49
2-50
2-51
2-52
2-52
LIST OF I LLUSTRATIONS (Continued)
3-35b
Carrier System Lubrication Points
Carriage System Lubrication Points.
Platen System Lubrication Points
Circuit Board Location.
Current Loop Connections
Power Supply Connections
Paper Feed Motor Removal
Carrier System Removal
Carrier System Removal
Carrier System Removal
Carrier System Replacement
Prepare Carriage Cables for Removal
Cable Clamp Removal
Disconnecting the Carriage Drive Cable
Carriage Rail Clamps
Carriage and Rail Assembly
Print Quality Standards.
Carrier Assembly Adjustment.
Paper Feed Adjustments
Paper Feed (Platen) Drive Adjustments
Platen Knob End Play Adjustment
Carriage Drive Cable Adjustment
Adjustment Tools
Printwheel Alignment
Printwheel Alignment
Platen-to-Printwheel Adjustment
Card Guide Adjustments
Ribbon Height Adjustment
Hammer Adjustments
Hammer Adjustment Tool.
Carriage Home Adjustment
Paper Chute Adjustment
Paper-Out Switch Adjustment
Circuit Board Component Location and Pin Numbering
Sem iconductor Lead Identification .
Mother Board Pin Numbering (No. 40614)
Mother Board Pin Numbering (No. 46080)
3-36
3-37
3-38
3-39
4-1
4-2
4-3
Keyboard Cable.
Control Panel Cable Pin Numbering.
EIA Cable Pin Identification
Power Supply Connections
Example of Functional Logic.
ASC II Code Chart
Logic Drawing Notation
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23
3-24a
3-24b
3-25
3-26
3-27
3-28
3-29
3-30
3-31
3-32
3-33
3-34
3-35a
viii
3-3
3-4
3-5
3-7
3-8
3-10
3-12
3-13
3-13
3-14
3-14
3-15
3-15
3-16
3-16
3-17
3-18
3-19
3-19
3-20
3-20
3-20
3-21
3-22
3-23
3-23
3-24
3-26
3-27
3-27
3-28
3-29
3-32
3-34
3-35
3-36
3-36
3-37
3-37
3-38
3-38
4-1
4-68
4-69
LIST OF TABLES
TABLE
2-1
2-2
2-3
2-4
2-5
3-1
3-2
3-3
3-4
4-1
4-2
PAGE
I/O Port Numbering.
Input Port 1
HPRO Jumpers . .
Key Position Encoding.
Voltage/Current Levels.
Major Assemblies and Modules
Current Loop Kit Parts .
Reference Designators .
Keyboard Signal Names
Integrated Circuits . .
Schematics and Logic Drawings
2-6
2-8
2-11
2-38
2-53
3-6
3-7
3-33
3-37
4-2
4-67
ix
MODEL 1610
MODEL 1620
Figure '-1. HyTerm Communications Terminal
1-0
SECTION 1
INTRODUCTION
1.1 GENERAL DESCRIPTION
1.3 RELATED DOCUMENTS
The HyTerm communications terminal, Figure 1-1,
transmits data to and receives data from a host computer or
remote terminal over a communications link via an EIA
standard RS-232 interface. I n local operation, the Model
1620 can also serve as a document writer for correspondence and other secretarial functions.
(1)
HYTERM COMMUNICATIONS TERMINAL,
PRODUCT DESCRIPTION. Diablo Systems, Inc.
Publication No. 82332.
(2)
SERIES 1300 HYTYPE II PRINTER PARTS CATALOG. Diablo Systems, Inc. Publication No. 82404.
The HyTerm consists of a Diablo HyType II printer
with microprocessor-driven electronics and an integral
power supply, all contained in an attractive table top unit.
A full complement of optional features, including keyboard, forms tractor, pin-feed platen, carbon ribbon,
interchangeable type fonts, etc., is available to adapt the
HyTerm to virtually any communications situation.
(3)
SERIES 1600 HYTERM TERMINAL PARTS CATALOG. Diablo Systems, Inc. Publication No. 82334.
(4)
INTERFACE BETWEEN DATA TERMINAL EQUIPMENT AND DATA COMMUNICATION EQUIPMENT EMPLOYING SERIAL BINARY DATA
INTERCHANGE. EIA Standard RS-232-C, August,
1969. Engineering Dept., Electronic Industries Assn.,
201 Eye St. N.W., Washington, D.C. 20006.
(5)
USA STANDARD CODE FOR INFORMATION
I NTE RCHANGE, USAS X3.4-1977. American
National Standards Institute, 1430 Broadway, New
York, N.Y. 10018.
(6)
DATA SET 103A INTERFACE SPECIFICATION,
February, 1967, Engineering Director, Data Communications, American Telephone and Telegraph Co.
Publication No. 41101.
1.2 SCOPE
This manual provides information on theory of operation, maintenance, and module/subassembly replacement.
It also includes data covering the electronic components
used and explanations of the logic symbology and drawing
conventions used. It does not include operating instructions, installation procedures, or information on the functional operation of the HyTerm; these are all contained in
the Product Description manual listed in the related
documents.
1-1
j
PRINTWHEEL
HOME
SENSOR
EIA
INTERFACE
PRINTWHEEL
POWER
AMP
RIBBON CONTROL
~
SERVO ERROR
DATA
CTRl
PRINT WHEEL POSITION
CTRl
DATA
HAMMER ..
ENERGY
READ
/' INSTRUCTIONS
WRITE
TERMINAL
STROBE
'"
FUNCTION
MICROPROCESSOR 1 - - - - - - - .
DATA
6
HPR02
IINTERFACE
SYS ClK
I !TATUS
(A)
1
CONTROL
PANEL
I
t.
&. CTRl l
CARRIAGE POSITION
DATA
COVER
OPEN
SWITCH
I
1
HAMMER
COIL
PRINTWHEEl
DRIVE
MOTOR
'--_ _ _~:
I
ROTOR
~
/
v
SERVO
XDCR
-
CLOCK A
CARRIAGE POS
STATOR
BOARD
161
ROTOR
FEEDBACK
I
(8)
DATA
RIBBON
LIFT COIL
FEEDBACK
CARRIAGE
CONTROL
t
(HI
1
PRINTWHEEL POS
PRINTWHEEL
CONTROL
SERVO DISA
.. ,
I
(CI
PAPER FEED CTRL
SWITCHES
INDICATORS
~ LOGIC 2
CLOCK A
(EI
PRINTER
MICROPROCESSOR
..
8080
I'V
I
I
\
RIBBON
DRIVE
MOTOR
SERVO ERROR
AMP
CARRIAGE
HOME
SENSOR
I
I
I
CARRIAGEp~
POWER
POWER-ON
Figure 2.. 1. HyTerm Block Diagram
i
(0)
~
CARRIAGE
DRIVE
MOTOR
PAPER FEED
DRIVE
MOTOR
SECTION 2
THEORY OF OPERATION
2.1
INTRODUCTION (Figure 2-1)
The optional HCU R L board, slot F, serves as the
interface beeween the terminal microprocessor and the
current loop network.
The HyTerm employs two separate, asynchronous,
processing systems. One, called the "printer microprocessor," is an integral part of all HyType II printers. The
other, called the "terminal microprocessor," provides the
additional fu nctions that transform a HyType II printer
into a communications terminal.
2.2 HYTERM PROCESSOR (HPRO) BOARD
(Figure 2-2), PART NOS. 23702 (HPR01) AND
23704 (HPR02)
Depending upon the optional featu res employed and
other manufacturing procedures, either of two HPRO
boards, HPR01 or HPR02, may be used. Although the two
boards appear quite different physically, the only functional difference is in the ROM integrated circuits. Both
boards contain most of the terminal microprocessor system,
including the 8080 microprocessing unit (MPU), the
memory, several Input/Output ports, and all control electronics. They also contain the Universal Synchronous/
Asynchronous Receiver/Transmitter (USART) and the
R5-232 interface components.
The terminal microprocessor, located on the HPRO
board, slot E, controls the overall terminal functions of
sending and receiving data over the EIA interface, receiving
data from the keyboard, and monitoring the control panel.
It also communicates with the printer microprocessor,
contained on the LOGI C·2 board, slot B. This second
microprocessor system initiates movement of the printer
carriage, printwheel, paper, and ribbon, and monitors
feedback from the carriage and printwheel circuits to effect
proper execution of these motion commands. It also
maintains a record of the printwheel's absolute position at
all times, it provides printer status information to the
terminal microprocessor, and it performs other "housekeepi ng" fu ncti ons.
NOTE
Throughout this manual, two terms will
be used extensively: "terminal microprocessor" refers mainly to the entire
HPRO circu it board, whereas MPU refers
to the 8080 integrated circuit.
The 8080 INTERFACE board, slot A, is located
logically between the two microprocessors. It provides
temporary storage for data and status information, and
synchronizes the transfer of data from the terminal
microprocessor to the printer microprocessor, and the
transfer of status information back. It also contains some
control logic for the servo feedback system and provides
the CLOCK A signal that drives the printer microprocessor.
2.2.1
General Operation
The terminal microprocessor is actually a miniature
computer. It receives its instructions from Read Only
Memory (ROM). These instructions are arranged to form a
"microprogram." As it executes this microprogram, the
MPU receives data from the various input ports and stores it
in memory, or reads data out of memory and sends it to the
various output ports. Between input and output instructions, the MPU may perform other operations on the data,
make logical decisions concerning the data, or "jump" to a
different portion of its program.
The SERVO board, slot C, receives printwheel and
carriage motion commands from the printer microprocessor
in digital form and converts these to analog signals
representative of the distance and direction to be moved.
These servo "error" signals are passed on to the prin twheel
and carriage power amplifiers, which drive their respective
s.ervo motors. Feedback signals, derived from the printwheel and carriage rotary transducers, are ampl ified by the
XDCR board, slot G, and passed through the SERVO board
to the 8080 I NTERFACE board. Here they are available to
the printer microprocessor, which uses them to regulate the
error signals. The SERVO board also converts digital
hammer-energy signals into their analog counterparts.
The main portion of the microprogram periodically
scans the control panel switches, performs the output
commands to the printer, control panel indicators, and the
USART, and takes care of other "housekeeping" functions.
When an input is received from either the communications
link (via the USART) or the keyboard, the MPU is
"interrupted," and it jumps out of the main program loop
into an "interrupt subroutine." During this subroutine, the
input character is received, decoded, and placed in the print
buffer and/or the transmit buffer (in memory). Then the
MPU returns to the same point in the main program at
which it was interrupted, and continues processing. Thus,
input characters are received via the interrupt subroutine,
and output characters are sent via the main program loop.
The PRINTWHEEL POWER AMPLIFIER, slot H,
provides drive for the printwheel servo motor, the ribbon
step motor, and the hammer-fire and ribbon-lift magnet
coils.
The CARRIAGE POWER AMPLIFIER, slot D, drives
the carriage servo motor and the paper feed stop motor. It
also monitors the input voltages and develops the POWER
ON signal to initiate the Restore operation.
2-1
KEYBOARD
[
}
UART
CONTROL PANEl [
USART INTERRUPT
BI-DIRECTIONAL DATA BUS
INT
I'V
N
MPU
I"
.. ADDR 4
DCDR
-CLOCK GEN
+DA ~
PORT
$1
t
t
+DA 7
PORT 4
PORT 5
PORT 6
PORT 7
/2
READ
1/0 PORT SELECTION
WRITE
~
---------v1
CONTROllER
I~-
-• : :~~ ~ J
- - - - - - - - . . - - MEM R
MEM W
Figure 2-2. HPRO Board Block Diagram
TO 8080 INTERFACE BOARD
RS-232
2.2.2
used to address memory. The stack pointer is generally used
to "remember" the address of the next sequential main
program instruction while an interrupt subroutine is being
executed. Still other elements internal to the MPU perform
the arithmetic and logic operations and control the input
and output over the data bus.
8080 Microprocessing Unit (MPU)
The 8080 is an 8-bit microprocessor contained in a single
40-pin integrated circuit (IC) package. It has an 8-bit wide
bi-directional data bus used for both input and output. It
has a 16-bit address bus, capable of addressing up to 65,536
memory locations, although the HyTerm uses substantially
less than this maximum. The MPU's instructions are located
in memory, from where they are fetched and executed
sequentially. There are over 100 separate instructions
possible, although many are similar, the difference being
only in the various MPU internal registers specified.
2.2.2.1
This is admittedly a very brief description of the MPU
architecture, but this background should be sufficient to
allow understanding of the material to follow. Further
information on the MPU can be found in the integrated
circuit information presented in Section 4.
2.2.2.2
ARCHITECTURE
To understand the operation of the terminal microprocessor, it is only necessary to know that the MPU
contains an instruction register, a program counter, a
memory address register, a stack pointer, and other registers
and logic elements. The instruction register contains the
8-bit instruction op code. The program counter contains
the 16-bi t me mo ry address of the next instruction to be
fetched. The memory address register is made up of two
8-bit registers, referred to as the Hand L register pair. It is
used to address memory for memory read and memory
write instructions. Other internal MPU registers can also be
TIMI NG
Timing is controlled by two 12V (nominal) nonoverlapping clocks, ra1 and ra2. These clocks are provided at
a frequency of 2 MHz by a Clock Generator IC.
2.2.2.3
BASIC PROCESSOR OPERATION
MPU operation is divided into time periods called
"cycles" and "states." There are two types of
cycles: instruction cycles and machine cycles. The material
that follows is summarized in the timing chart in
Figure 2-3 .
1.....
. . - - - - - - - - - - - - - INSTRUCTION
M1
.- - - I~CTL~UC~~:
CYCLE n - - - - - - - - - - - - I I..~I
M2
M3
M1
+ A15-0
+D7-0
+SYNC
+DBIN
..~..L-l_--1---JL-1.,..~~_+--_;----~--+__;~--_+-
!----L~-;
+ READY fWAIT +---!--~-.,.L-_l----l--__1-___1.,..-~-L-L-jjII-"'__1_L-_L\
-WR
STATUS
INFORMATION
*
IIf7\
- I - - - - - lII\...!..;
IXCi)
*NUMBERS IN CIRCLES REFER TO TYPES OF MACHINE CYCLES.
Figure 2-3. Typical Instruction Cycle (Output Instruction)
2-3
2.2.2.3.1
Instruction Cycle. An instruction cycle
includes both the fetching of the instruction from memory
and the execution of the instruction. Each instruction can
be either one, two, or three 8-bit bytes in length. Multiple
byte instructions must be stored in successive memory
locations. Figure 2-4 illustrates the three instruction formats. The actual bit configuration of the op code is not
important to the understanding of the terminal processor
operation.
2.2.2.3.3.1 T1. During T1 either a memory address or an
I/O port address is placed onto the memory address bus.
Also, the MPU places eight bits of status information on the
data bus which identify the type of machine cycle being
performed. Following the rising edge of ~2, the SYNC
signal is produced by the MPU, which identifies the
beginning of a machine cycle. See Figure 2-3.
2.2.2.3.3.2 T2. During T2 the MPU monitors its ROY
input. If it is high, the MPU goes on to state 3, if it is low,
the MPU goes on to the Wait state. In the HyTerm, the
WAIT output, which goes high during TW, is connected to
the ROY input. This causes TW to always follow T2.
One Byte Instructions
OPCOOE
During the machine cycles that bring data into the MPU
(Instruction Fetch, Memory Read, Stack Read, Input, and
Interrupt Acknowledge), the Data Bus In signal, OBIN, is
developed at ~2 during T2. OBIN remains high through TW
and into T3. This signal develops READ and MEMR at the
proper time to provide the input data needed by the MPU.
(This is covered more fully in Section 2.2.4.)
Two Byte Instructions
I071 061 05 1041031 021 01
1DO
I
1 071 061051 041 031 021 01
IDO I
OP CODE
OATA or
AOORESS
Three Byte Instructions
2.2.2.3.3.3 TW. The wait state provides the MPU delay
required for proper memory access. No internal processing
occurs during this state. The MPU monitors its ROY input,
and if it is low, it remains in the Wait state; if it is high, the
MPU goes on to state 3. In the HyTerm, the ROY input is
always high during TW, so the MPU always goes on to T3
after one state time (500 ns) in TW.
I OPCOOE
I071 06 1051 041 031 021 01 I00 I ) OAT A or
107106105104103102101100 I ADDRESS
107106105104103102101100
Figure 2-4. MPU Instruction Format
During machine cycles in which the MPU outputs data
(Memory Write, Stack Write, Output), it develops the WR
(Write) signal during TW and holds it low until after the end
of T3. This signal is used by other logic on the HPRO board
to strobe the output data to memory or the selected output
port.
2.2.2.3.2 Machine Cycle. A machine cycle is required
each time an I/O port or the memory is accessed. Each
instruction cycle can contain from one to five machine
cycles. There are ten different types of machine cycles
possible, as follows:
2.2.2.3.3.4 T3. During T3 the data or instruction byte is
actually transferred between the MPU and memory or an
I/O port. The source and destination of the byte is
determined by the type of machine cycle being performed.
For example, during an instruction fetch cycle, the source
of the data (instruction byte) is the memory location
addressed during state 1; the destination is the MPU. During
an Output machine cycle, the source is the MPU and the
destination is the I/O port selected (addressed) in state 1.
( 1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Instruction Fetch
Memory Read
Memory Write
Stack Read
Stack Write
Input
Output
Interrupt Acknowledge
(9) Halt Acknowledge
(10) Interrupt Acknowledge While in Halt
2.2.2.3.3.5 T4 and T5. These two states are used only
when required for manipulation of data with the MPU.
The latter two do not occur in the HyTerm since the
HALT instruction is not used in the microprogram.
2.2.3
Clock Generator (8224)
The clock generator is contained in a single integrated
circuit that provides several functions. First, it provides the
two non-overlapping 12V signals, ~1 and ~2, required by
the MPU. The frequency of these signals (2 MHz) is
controlled by an external quartz crystal. A TTL equivalent
of the ~2 signal, +~2T, is also developed for use in timing
other functions on the HPRO board.
2.2.2.3.3 States. A state is defined as the time interval
(50 ns) from leading edge to leading edge of the 9'11 clock.
There are six possible states, numbered T1 th rough T5 and
TW (representing "wait"). 1W follows T2. All machine
cycles include T1, T2, TW, and T3. T4 and T5 are omitted
during execution of instructions not requiring them.
2-4
its data inputs. The 8228 provides a minimum of +3.6 volts
on the 8080 Data Bus, which is substantially higher than
can be guaranteed by standard TTL devices. For output
data, the MPU can provide only 1.9 mA of current drive.
With many I/O ports and the memory connected to the
bi-directional data bus, this value could easily be exceeded,
so the 8228 is used to provide over 10 mA to satisfy this
requirement. The direction of data flow on the buses is
controlled internally by the same signals that furnish the
system control function performed by this IC.
Second, the 8224 converts the MPU's SYNC signal into
:he Status Strobe signal, STSTB. This signal is used to load
:he status information, put out by the MPU at the
)eginning of each machine cycle, into the Bus Driver/
iystem Controller IC. This is covered more fully in section
~.2.4.
Third, the clock generator IC develops +CLEAR, which
s used to reset and initialize the entire HPRO board. This
)ccurs both at power-on and when the RESET switch is
)perated.
2.2.4.2
The 8224 has other capabilities not utilized by the
terminal microprocessor.
2.2.4
At the beginning of each machine cycle, the MPU issues
"status" information on the 8080 data bus that indicates
the type of cycle about to be performed. At the same time,
the clock generator module develops STSTB, which loads
this status information into a status latch inside the 8228.
This status latch output is decoded [along with DBI N, WR,
and HLDA (Hold Acknowledge) from the MPU] into the
system control signals MEM R (Memory Read), MEM W
(Memory Write), I/O R (I/O Read), and I/O W (I/O Write).
The latter two are named simply -READ and -WRITE as
they leave the HPRO board. (These decoded signals also
provide the internal control of the bus driver.) Note that
these signals are not levels, but that they are gated byDBIN
or WR from the MPU at the proper time. The status
information provided by the MPU, and the system control
signals developed for each of the ten types of machine
cycles are shown in Figure 2-5.
Bus Driver/System Controller (8228)
This module is another single IC that performs three
:>asic functions: bi-directional bus control, system logic
:ontrol, and interru pt handl ing.
2.2.4.1
SYSTEM LOG IC CONTRO L
BUS CONTROL
The 8228 provides a buffer between the MPU and the
memory and I/O ports. Controll ing the two 8-bit data buses
on the HPRO board is concerned with not only switching
the data on and off in the proper di rection at the right
time, but also in providing the required voltage and current
levels. Since the MPU is an MOS device, it requires a voltage
of at least +3.3 volts for a "Iogic 1" or "true" indication on
TYPE OF MACHINE CYCLE
I
INTA
0,
WO
02
03
04
STACK
HlTA
0
OUT
0
Os
M,
1
06
07
INP
0
MEMR
0
0
Do
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
0
0
0
0
1
0
0
1
0
0
0
1
0
0
~
Ll
INTA
(NONE)
--INTA
IIOW
---I/OR
MEMW
CONTROL
StGNALS
MEMR
MEMW
MEMR
MEMR
Figure 2-5. MPU Status and Resultant Control Signals
2-5
---(ADDRESS) - - - -
+AO-A 15
+DBIN
A. READ
\
-MEM R
DATA
AVAILABLE
///////1 1//////////////1
....
+AO-A 15
/
(ADDRESS)
500ns
--
I
DATA OUT
B. WRITE
\
-WR
\
-MEM W
Figure 2-6. Memory Timing
Table 2-1. I/O Port Numbering
Input
Port No.
Output
Keyboard Data
00
Control Panel Indicators
Keyboard & M iscell aneous Controls
01
Baud Rate Factor
Control Switches
02
Not Used
Control Switches
03
Not Used
Received Data
04
Send Data
USA RT Status
14
USART Control
Printer Status
05
Printer Control & Strobe
Printer Status (Not Used)
06
Printer Low Order Data
Not Used
07
Printer High Order Data
2-6
2.2.4.3
INTERRUPT HANDLING
on the bi-di rectional data bus to be written into the
addressed RAM location. Note that both RAMs operate in
parallel, one servicing the low-order four bits of the
bi-directional bus, and the other taking care of the
high-order four bits,
The 8228 is capable of handling interrupts in either of
two different ways. Only one of these methods is used in
the HyTerm, in which the Interrupt Acknowledge pin (23)
is connected to +12V through a resistor. Connected this
way, (when the MPU is interrupted (by an input from the
keyboard or USART) and it performs an INTERRUPT
ACKNOWLEDGE machine cycle, the 8228 automatically
forces an RST 7 (Restart 7) instruction into the MPU. This
instruction causes the MPU to fetch its next instruction
from memory location 56 10, which begins the routine
needed to process the input character.
Typical idealized timing waveforms are shown in Figure
2-6. Specific timing requirements for each of the memory
IC types can be found in the IC information in Section 4.
In all cases, the timing shown in Figure 2-6 is within the
timing constraints of the invividual ICs.
2. 2.5
2.2.6
2.25.4
Memory
The HyTerm memory contains both Read-Only Memory
(ROM) and Random-Access (Read/Write) Memory (RAM)
integrated circuits. The HPR01 board contains two 1K x
8-bit erasable ROMs. The HPR02 board contains a single
2K x 8-bit mask-programmed ROM. Both boards contain
two 256 x 4-bit RAMs.
2.2.5.1
ADDRESSING
2.2.6.1
ADDRESSING
The ports are numbered 00 through 07 and 14 16, Most
port numbers can represent either an input or an output,
depending upon the operation being performed by the
MPU. For example, port 04 represents the USART. If port
04 is addressed and READ is developed, the MPU is
performing an Input machine cycle and one 8-bit data byte
will be transferred from the USART to the MPU. On the
other hand, if port 04 is addressed and WRITE is
developed, the MPU is performing an output machine cycle
and it will transfer one 8-bit data byte to the USART.
Table 2-1 lists the I/O ports and provides a brief description
of their purpose.
READI NG
All memory ICs are three-state devices. This means that
the outputs remain in the high-impedance, or "off" state, at
all times when the IC is not selected. (This allows the same
memory address bus to be used for addressing I/O devices;
the address lines can assume any configuration, but there
will be no input to or output from memory without the
proper system control signals.) ROM selection is accomplished by having address lines A 11 and A 13 low and by
having the MEM R signal from the bus driver/system
controller low. RAM selection requires A11 low and A13
high" The MEM R signal is connected to the "output
disable" input of the RAMs (pin 9). This maintains the
RAM outputs in their high-impedance state at all times
other than during a memory read.
2.2.5.3
Input/Output
The HyTerm has eight input ports and seven output
ports. Five input ports and four output ports are physically located on the HPRO board; these ports represent the
keyboard, control panel, and USART. The rest of the ports,
pertaining to the printer, are on the 8080 I NTER FACE
board. Of the ports on the HPRO board, four of the inputs
and two of the outputs are implemented by type 8212 I/O
port ICs; the others are built into the USART.
The eight low-order bits of the memory address bus are
used to directly address all memory ICs. A8, A9, and A 10
are applied to the ROM(S) to allow access to the larger
memory capacity. The A11 line is applied to the Chip
Enable or Chip Select inputs of all memory ICs; this line
must be low in order to access any memory. A 12 is not
used. A 13 selects between ROM and RAM: when A 13 is
low, ROM is accessed, and when it is high, RAM is accessed.
2.2.5.2
TIMING
The low-order four bits of the MPU's Memory Address
Bus are decoded into eight signals, -PORT 0 through
-PORT 7. One of these signals is developed during each I/O
instructi on to enable one in put port or one output port. In
the case where there is both an input port and an output
port having the same number, the state of the READ and
WRITE signals determines which will be enabled. (The use
of ports 5, 6, and 7 is covered in more detail in Section
2.3.) The +ADDR4 signal from the Memory Address Bus is
not decoded, but goes directly to the USART to determine
whether data or control/status information is to be transferred. This is covered more fully in Section 2.2.6.8.
WRITING
When memory write is performed, A 11 and A 13 still
select the RAMs, but the RAM output remains disabled
(MEM R is high), and MEM W being low allows information
2-7
2.2.6.2
I/O PORT IC (8212)
Table 2-2. Input Port 1
All of the I/O ports on the HPRO board other than the
USART use the 8212 I/O port integrated circuit. This IC
can be used as either an input port or an output port, but
not as both. It has one set of eight inputs wh ich supplies
eight D"type latches. These latches follow the inputs until
they are clocked, at which time the data is latched. The
latches' outputs go to a set of 3 .. state gates, which drive
the IC's outputs. In addition to the data inputs and out..
puts, the 8212 has four control inputs: DS1, DS2, MD, and
STBo The first two of these are used for device selection;.
when DS1 is low and DS2 is high, the port is selected. The
MD input selects the operating mode of the 8212. When
MD is low, it is an input port; when MD is high, it is an
output port. The STB (Strobe) input is used to clock the
data latches in the input mode. Further information can be
found in the integrated circuit information in Section 4.
2.2.6.3
KEYBOARD
CONTROL
SWITCH
0
-CARRIER DETECT
-ASCII KYBD
+ PAR DATA INT
+Remote/- Local
-Upper Case Only
-Shift
-Control
-Form Feed
Unlike port 0, port 1 is not directly related to an
interrupt. Instead, it is "polled" at the appropriate places in
the microprogram to determine the state of the individual
switches. For example, when an interrupt occurs, the
microprogram must determine whether the interrupt was
raised by the USART, by the keyboard, or both. (The
USART status is checked first, and the USART is serviced
if it has a character ready for the MPU.) The MPU polls
port 1 and checks the +PAR DATA INT bit to determine
the presence of a keyboard interrupt. If the keyboard has
interrupted, the MPU "looks at" the Upper Case Only,
Shift, Control, and ASCII KYBD bits to determine exactly
what character was entered. It also checks the Remote/
Local bit to determine whether or not the transmit and/or
print subroutine is to be performed.
The eight data lines from the keyboard are continuously
monitored by input port O. When +KYSTB (Key Strobe) is
received from the keyboard, it sets a D-type flip-flop. The
reset side of the flip-flop drives the STB input to port 0
low, latching the data. The set side of the flip-flop
develops +PAR(allel) DATA INTERRUPT, which interrupts the MPU. During subsequent execution of the
interrupt service routine, the MPU performs an Input
instruction from port O. When port 0 is selected, its output
drivers are turned on and the data character is placed on the
bi-directional data bus for input to the MPU. After the
MPU has received the data character, another instruction in
the same interrupt service routine outputs a 0 on the +DA2
line of the bi-directional data bus, to output port O. This
clears the KYSTB flip-flop, which removes the interrupt
from the MPU. A short time later, the MPU performs still
another output to port 0, this time putting a 1 on the
+DA2 Iine. This re-enables parallel data interrupts by
removing the clear from the KYSTB flip-flop.
2.2.6.4
(PORT 1)
Information
1
2
3
4
5
6
7
KEYBOARD DATA INPUT (PORT 0)
+BUSY is affected by +PAR DATA INTERRUPT
+EN PAR INT (Enable Parallel Interrupt). +BUSY is
used in the standard HyTerm, but is included for use
parallel 8-bit interface should the HyTerm be util ized
computer local output printer.
Bit
-ASCII KYBD refers to the type of keyboard being
used. The HyTerm microprogram is capable of handling
either an ASCII-coded keyboard or a position-encoded
keyboard, so it "Iooks at" this status bit to determine
which section of the microprogram to use. This status bit is
controlled by a jumper (see 2.2.7.3).
-CARRIER DETECT is a modem status signal. It is
included here because there was no room for it in the
USART status word (see Figure 2-7.)
-Form Feed is checked periodically during the main
program loop.
and
not
in a
as a
2.2.6.5 CONTROL PANEL SWITCH INPUTS (PORTS 2
AND 3)
INPUT
All control panel switches other than POWER and
FORM FEED are wired into input ports 2 and 3. The
BREAK switch on the keyboard is also wired to port 2. All
of these switches are monitored periodically as the microprogram goes through its main program loop. The speed of
the MPU is such that there is no noticeable delay between
operation of a switch and the resultant action. It is virtually
Input port
receives not only the keyboard control
switch inputs, but other system control functions as well.
Table 2-2 lists all information entered through port 1.
impossible to operate a switch without the MPU "seeing"
it.
2-8
2.2.6.6
BAUD RATE FACTOR (OUTPUT PORT 1)
RD is low, the USART places data or status information
(determined by the C/D input) on the bi-directional data
bus for input to the MPU. When WR is low, data or control
information from the MPU is taken off the data bus and
loaded into the USART. The RD and WR inputs are
controlled by -READ and -WRITE, respectively, from the
bus driver/system controller,
The HyTerm can transmit and receive at either 10, 15,
30, or 120 characters per second (110, 150, 300, or 1200
baud, respectively). If the 1200 baud option (see 2.2.7.3) is
not used, the microprogram "reads" the position of the
SPEED switch on the control panel and sends a corresponding 8-bit data byte to port 1 to control the USART
transmit/receive rate. If the 1200 baud option is used, the
microprogram bypasses the SPEED switch and supplies a
different 8-bit byte to port 1. The eight bits are used by the
frequency divider to develop a square wave at 64 times the
desired baud rate, which is the clock frequency used by the
USART.
Note that all information transfer between the MPU and
the USART is over the bi-directional data bus, through a
bi-directional, 3-state buffer within the USART.
Information transfer between the USART and the data
link is over individual lines for Send Data, Receive Data,
and each of the modem status and control lines, through a
voltage level converter, to (or from) the modem. (Refer to
Section 4 for information on the level converter ICs.)
Note that the -2X COMM ClK signal, shown on sheet 2
of the HPRO schematic, is not 64 times the baud rate; it is
128 times the baud rate, and is non-symmetrical. This signal
is halved in frequency and made symmetrical by the D-type
flip-flop on sheet 3 having its set output tied directly to the
USART transmit and receive clock inputs, TXC and RXC.
2.2.6.7
2.2.6.8.2.1
Read Data. When the USART receives a
character from the data link, it raises its RXROY (Receiver
Ready) line, which sends +USART INTERRUPT to the
MPU. In servicing this interrupt, the MPU performs a
sequence of instructions, one of which is an input from I/O
port 4. With CS low, RO low, and C/D low, the USART
puts an 8-bit byte of data onto the bi-directional data bus,
from where it is accepted by the MPU. The USART, having
presented the data byte to the bus, resets its R EAOY line,
until the next character is received and the entire sequence
repeats.
MISCEllANEOUS OUTPUTS (PORT 0)
Output port 0 (sheet 2) has already been mentioned in
relation to synchronizing the entry of keyboard data (see
2.2.6.3). This same port is used to drive the ERROR lamp
and the audible alarm. It also has a bit that controls the
communications +OPTION ON line, which is not used in
the standard HyTerm.
As the data is received from the data link, the USART
strips off the start and stop bits, checks the parity bit (if
parity checking is enabled - see 2.2.6.8.2.4), and checks
for framing errors (lack of a stop bit at the proper time). If
an error is detected, a bit is set in the intern al Status
Register. The USART also checks to see that the previous
character has been accepted by the MPU - if RXRDY is
still high (has not been reset by the MPU having read in the
previous character), the overrun status bit is set.
Output ports 2 and 3 do not exist.
2.2.6.8
USART (PORTS 4 AND 14)
The type 8251 USART (Universal Synchronous/
Asynchronous Receiver/Transmitter) IC accepts an 8-bit
byte of data from the MPU in parallel format and converts
it to a serial stream of data for transmission over the
communications link. Similarly, it receives data characters
from the link in serial format and converts them into
parallel data bytes for the MPU. During transmission, the
USA,RT adds start, stop, and parity bits. During reception,
it strips these bits and also checks parity, if desired. It also
checks for data framing errors and overrun errors, and can
monitor modem status. It has many capabilities that are not
used in the HyTerm (synchronous transmit/receive, character lengths down to 5 bits, etc.).
2.2.6.8.2.2 Write Data. When the MPU wishes to send
data t? the USART, it addresses port 4, places the data
character on the bi-di rectional data bus, and develops
-WRI TE. This combination (CS, WR, and C/O all low)
loads the character into the USART, which then adds the
start, stop, and parity bits, and immediately begins to shift
the character out, one bit at a ti me.
There are two status bits pertaining to data transmission: TXE (Transmitter Empty) and TXRDY (Transmitter Ready). Both of these become reset when a
character is loaded into the USART from the MPU. If a
relatively long time has passed since the previous character
was loaded, TXROY sets again almost immediately. This
allows a second character to be loaded, even though the
first has not been fully shifted out. TXRDY again resets as
the second character is loaded, but this time it remains reset
until the first character is completely shifted out. Then it
sets again, allowing another character to be loaded. When
all data characters have been fully transmitted, TXE again
sets.
2.2.6.8.1 Addressing. The CS (Chip Select) input is
driven low whenever the MPU addresses port 4. No
information can be transferred between the USART and
the MPU until the USART is selected.
The USART also has a C/D input, which is connected to
the +ADDR4 line of the Memory Address Bus. When this
line is high, control information is to be transferred; when
it is low, data is transferred.
2.2.6.8.2 Information Transfer. Two inputs, RD and
WR, determine the direction of information transfer. When
2-9
2.2.6.8.2.3 Read Status. When the MPU wishes to know
the status of the USART, it performs an I nput from port
14. This occurs after any interrupt, since the MPU needs to
know if it is the USART that is interrupting, and before
every data output to the USART, because the MPU must
check to see that the USART is able to accept the data
character.
"control writes" are accepted as Command bytes. Both of
these are shown in Figure 2-7. Further information is
contained in the IC data in Section 4.
When port 14 is addressed, the -PORT 4 signal enables
the USART by driving its CS input low, and +ADDR 4
drives the USART's C/D input high, which directs the
USART to transfer control/status information. -R EAD
again directs the USART to output information onto the
bi-directional data bus, but because the C/D input is high,
the USART outputs status information instead of data.
This status word is shown in Figure 2-7, and further
information is contained in the IC data in Section 4.
There are three 3-terminal voltage regulator ICs, shown
on sheet 1 of the HPRO logic drawings, that provide the
source of -5V, -12V, and +12V. These voltages are
derived from the ± 15V provided by the power supply,
which also provides +5V.
2.2.7
2.2.7.1
2.2.7.2
Miscellaneous Circuitry
3-TERMINAL VOLTAGE REGULATORS
LEVEL CONVERTERS
The input and output voltage level converters provide
the interface between the TTL inputs and outputs of the
USART and the 12V (nominal) requirements of RS-232-C
and the HCU R L board, if used (see 2.9).
2.2.6.8.2.4 Write Control. When the MPU outputs to
port 14, it sends control information to the USART.
However, complete control of the USART requires more
than 8 bits of information. The USART is designed to
accept two different control bytes, a "Command" byte and
a "Mode" byte. It accepts the Mode byte only as the first
control instruction following a reset. All subsequent
More information concerning these ICs (75150 and
75154) can be found in the integrated circuit information
in Section 4 and in Section 4 of the Product Description
manual.
MODE BYTE
I
D71 D6
D5
D4
D3
D2
NUMBER OF STOP BITS _ _....&....1_--,1
EVEN PARITY
D1
DO
1
....._-LI__
L . . - . - - - - - I ' - -_ _ _ _ _
BAUD RATE FACTOR
CHARACTER LENGTH
PARITY ENABLE
COMMAND BYTE
SEARCH FOR SYNC
L..-.--_
RESET
READY TO SEND
RESET ER ROR FLAGS
ENAB LE TRANSMIT
DATA TERMINAL READY
L......._ _ _ _ _ ENABLE RECEIVE
L - -_ _ _
' - - - - - - - - - - BR EAK
STATUS WORD
OAT,'\ SET READY
TRANSMITTER READY
SYNC DETECT
FRAMI[\;G ERROR
OVEFlRU~·J EP.ROf~
""'"----- RECEIVER READY
L.......-----TRANSMITTER EMPTY
L......._ _ _ _ _ _ _ PARITY ERROR
Figure 2-7. USART Control/Status Words
2-10
2.2.7.3
only. This is required when the HyTerm is used as a
computer output printer, for example, instead of a terminal.
JUMPERS
There are four jumpers on the HPRO board that provide
variations in operation" Table 2-3 lists the jumpers and their
locations on the HPRO board. Most jumper installation
requires soldering a 1/2-inch (1.2 cm) length of 26 AWG
wire to the board. Jumper removal can be accomplished by
unsoldering or simply by cutting the jumper. Later revision
boards are equipped with a miniature socket for installation
of the 1200 baud jumper; in this case a small shorting plug,
Diablo part no. 10634, is simply plugged into the board or
pulled out, instead of soldering or cutting a jumper.
2.3 8080
40644-XX
INTERFACE
BOARD,
The 8080 INTERFACE board contains I/O Ports 5,6,
and 7, which transfer data and control/status information
between the terminal microprocessor and the printer
microprocessor. It also contains logic that receives and
temporarily stores carriage and printwheel position feedback signals from the SERVO board and supplies this data
to the printer microprocessor when requested. Other
circuits provide option jumper status to the printer microprocessor and develop the CLOCK A signal used by the
printer microprocessor.
2.2.7.3.1 1200 BAUD. This option provides 1200 baud
data transmission and reception. With this jumper or plug
installed, 1200 baud is the only speed available; the SPEED
switch on the control panel is non-functional.
2.3.1
2.2.7.3.2 GND CNCT. This jumper is factory-installed.
It provides the connection between pin 1 (chassis ground)
and pin 7 (signal ground) of the EIA connector. If modem
requirements dictate separation of these two circuits,
remove this jumper.
I/O Ports 5, 6, and 7
Ports 5, 6, and 7 are used to synchronize the transfer of
information between the two processors. When the terminal
microprocessor performs an output instruction to port 5, 6,
or 7, the output information is stored on the 8080
INTERFACE board, where it is available to the printer
microprocessor. The printer microprocessor periodically
"reads" the 8080 I NTER FACE board to see if there is any
information that it should process. Similarly, as the printer
microprocessor goes through its steps of controlling the
printer, it provides status information to the 8080 I NTERFACE board. This status is monitored by the terminal
microprocessor prior to each output command.
2.2.7.3.3 ASCII KYBD. Install this jumper when an
ASCII-coded keyboard is used. When a position-encoded
keyboard is used the jumper must not be installed.
2.2.7.3.4 LOCAL. For normal HyTerm operation this
jumper is left out. When installed, it allows Local operation
Table 2-3. HPRO Jumpers
Circuit Board
Option
1200 BAUD
PART NO.
HPR01
Rev. D or
Earlier
Rev. E
Or Later
Jumper F17
Plug F23
HPR02
Rev. C
Rev. B Or
Or Later
Earlier
Jumper B2
Plug B2
GND CNCT
Jumper F3
Jumper A4
ASCII KYBD
Jumper A2
Jumper E4
LOCAL
Jumper A6
Jumper F7
Use 26 AWG wire for jumpers; use Diablo part no. 10634 for plug.
2-11
!\
A
( BI-DIRECTIONAL DATA BUS
'4
BUS
DAIJ-DA7
~
-
I--
READ
-
CONTROL
I--
CONTROL-
t.
~
lOUT
i---Y
/~
RAM
~
-
IA 1-lAB TO
LO GIC -2
I
I
I
~
-READ
R
o
k
~
H
P
v
WRITE
BUS
DIRECTION
ENA
I""
I - - - RAM
PORT 5
f - - - - WRtTE
r---- CONTROL
PORT 6
FUNCTION
1 OR 2
PORT 7
-WRITE
~
'--V
,---
16
l[
f---
f--/
f--
I
;,>
RAM
f - - - READ
eOMMANn
r-----
OPTION JUMPERS
CONTROL
DCDR
18
2
he
h.
-ENA INP
~
CARR
POSITlONfj[
POSITION DATA
F~
• LATCHESh
PW
E
t-
CARR MOTION FEEOBACK
~
V
o
f-----"
DeDR
-17
R
STATUS
RESET
G
S
IV'
BUSY
15
o
c
f\
STROBE
~ESt
-RST
L
PRI NTER
PRO CESSOR
OAT A BUS
COVER OPENPAPER OUT RIBBON OUT-
De DR
CAR
CNTR
CTRL
1L
PW MOTION FEEDBACK
",
PW
CNTR
CTRL
-:;R X
.1
1
J
:>
./
1
+PW INC
+PW DEC
ru
CLOCK A
Figure 2-8. Block Diagram, 8080 INTERFACE Board
2-12
TO LO GIC -2.
XD CR
2.3.1.1 TRANSFER
PRINTER
OF
INFORMATION
TO
Depending upon the nature of the information it
receives from the STROBE LATCHES, the printer microprocessor performs different operations. For example,
should the RC (Ribbon Control) or RSTR (Restore) latch
be set, the printer microprocessor will immediately execute
the appropriate control action. On the other hand, if either
the CAR (Carriage), PW (Printwheel), or PF (Paper Feed)
latch is set, the printer microprocessor will go through the
steps necessary to read in data from RAM storage. (The
OPT latch is not used.)
THE
The transfer of a printer command from the terminal
microprocessor to the printer microprocessor involves the
following steps (refer to Figure 2-8):
(1)
Terminal microprocessor "writes" low-order eight
bits to port 6 (stored in RAM).
(2)
Terminal microprocessor "writes" high-order bits
(and direction bit) to port 7 (stored in RAM).
(3)
Terminal microprocessor "writes" control word,
containing strobe bit, to port 5 (stored in STROBE
LATCHES), and sets BUFFER BUSY flip-flop.
(4)
Printer microprocessor "reads" ST ROB E LATCH ES
to determine nature of command.
(5)
Printer Microprocessor reads high-order bits and
direction bit from RAM.
(6)
Printer microprocessor reads low-order eights bits of
data (from RAM), resets BUFFER BUSY.
2.3.1.1.4 Read RAM Data. After sensing either a
carriage, a paper-feed, or a printwheel strobe, the printer
microprocessor is directed to the steps in its microprogram
that allow it to read the data stored in the RAM. The
storage locations read are the same in all three instances. It
reads the high -order bits first by supplying the correct
combination of signals on the 15-18 lines" It then reads the
low-order eight bits from the other RAM location, and
finally, it resets the BUFFER BUSY flip-flop.
2.3.1.2 TRANSFER OF INFORMATION FROM THE
PRINTER
The only information received from the printer is status
information. It is received by the terminal microprocessor
when it performs a READ instruction from port 5. Ports 6
and 7 are not used for input to the terminal microprocessor.
2.3.1.1.1 WRITE to Ports 6 and 7. When a write
command is executed to either port 6 or 7, the data appears
on the bi-directional data bus simultaneously with the
development of the -WRITE signal and -PORT 6 or
-PORT 7. The FUNCTION DCDR block in Figure 2-8
contains random logic which both enables (turns on) the
BUS 01 RECTION SWITCH, and addresses the RAM
according to the I/O port selected. Since -READ is high at
this time, the BUS DIRECTION switch allows data to flow
from its "bus" connection to its output, from where it is
written into the RAM.
The -PORT 5 signal, through the FUNCTION DCDR,
turns on the BUS 01 RECTION SWITCH. This time,
however, -READ, being low, guides status information on
the switch's input to the "bus" connection, where it is
placed on the bi-directional data bus and provided to the
terminal microprocessor. In addition to the contents of the
STROBE LATCHES, this status information also provides
COVER OPEN, PAPER OUT, and BUFFER BUSY status.
2.3.2
2.3.1.1.2 WRITE to Port 5. The control word, containing the strobe bit (or control bit, in the case of printer
control functions) appears on the bi-directional data bus as
-WRITE and -PORT 5 are developed. Data flow through
the BUS 01 RECTION SWITCH is again from the "bus"
connection to the output, only this time the information
on the output is not written into RAM. Instead, it is
clocked into the STROBE LATCHES. Normally, only one
of these latches is set at a time. The BUFFER BUSY
flip-flop also sets at this time.
Carriage and Printwheel Position Data
This portion of the 8080 INTERFACE logic is identical
to that found on a standard HyType " LOGIC-1 board. It
consists basically of two groups of logic, the "position
latches" and the counter control flip-flops.
2.3.2.1
POSITION LATCHES
On earl ier boards (40644-01 and -02), there are fou r
position latches, one each for the carriage and printwheel
"even" signals, and one each for the carriage and printwheel
"home" signals. These four signals occur at random in
relation to the printer microprocessor operation, so they
are synchronized to the microprocessor by clocking the
latches with +CLOCK A. On later boards (40644-03) those
latches are eliminated because other circuit changes and
printer microprocessor program alterations make them
unnecessary.
2.3.1.1.3 Read Strobe Latches. The printer microprocessor, as part of its normal processing loop, reads the
contents of the STROBE LATCHES. It provides the
conditions on the 15 through 18 lines (along with the
-ENAB LE I NP signal) to gate the contents of the latches
onto the IA 1-IA8 bus, from where the information is
received by the printer microprocessor on the LOGIC-2
board.
2-13
+CAR EVEN
+CAR X
-CAR POS A
-CAR POS B
-RST CAR X
+CAR EVEN
...,'-_ _---',...-~; ~'-_ _---'
~~
-CAR POS A
-CAR POS B
XOR-A
FF-l
..J
~
~
s~
FF-2
r--'
XOR-B
~
1\__ -.-1\_-..., ,?----------'i\ _~\ __ ~\__ _
+CAR X
I
j=-/120IN
f--
I
1/60 IN - - - -
CARRIAGE
MOTION
FORWARD
I STOPPED
REVERSE
Figure 2-9. Carriage Counter Decrement Control
i (L-------------~~---------:----------"
_.. ,' •••••••••••••• ,1, •••••• " •• " •••••••• " •••••••••• ,1, ••••••••••••••••• ,1 •••••••••••• ,11 ••• " •••••••••• 1 ••••••••••••• , ••• ,I#4!.
:~ II
,
___
__I
TABLE
~
:1
DATA FROM
(IAI
: t
8080B6~TREDRFACE)
l
UP-- ""
II :=t::.=I
~::
I
I
!:I ~
J:I
.
"
rr
,;;-;;._•• t. ____
,A
~
:-
... - - -
r:-r.---~
:1
, _____
I·
]
......... DATA OUTPUT
I:
:
REG
. _ . - PROGRAM CONTROL
:~
I
I::Ir
~---- '" ---,:
:: II
- - - DATA PROCESSING
~
::
COMPARATOR
----
• _ _ •• ,..................7"........~
~__________
lA8
"""" ':'.:":".::-:~........................................................................
!-.-.-.I
•
!I
I~
I
'REG
-·-·~l_~;----~~
'
!
I
•
PRGM
1:1
!I
PRGM
DATA &. CONTROL
SIGNALS TD OTHER
LATCHES
II.
;};
.'1 __~
1
ROM_.~.·; ~
,.~.-.~.-."......-'-""'--'-""'.-.
._.- _._.- _ ....
\
-
l!~.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-~.j .t::F~
Figure 2-10. Block Diagram, LOGIC-2 Board
2-14
PRINTER BOARDS
,\OOR
15 -,
(INSTRUCTIONS TO
8080 INTERFACE
BOARD
: I
18
CONTR:L SIGNALS
FOR THIS BOARD
2.3.2.2
CARRIAGE COUNTER CONTROL
monitors these two signals and, finding one or the other
high, it makes the appropriate change to the printwheel
absolute position counter, and outputs an instruction back
to the 8080 INTERFACE board to clear the PW INC or PN
DEC fli p-flops.
When a carriage movement command is received, the
printer microprocessor loads a value, representing the
number of 1/120-inch increments the carriage is to move,
into a "difference counter" (in RAM). It then initiates the
carriage movement, the amount of drive current fed to the
carriage motor being controlled by the printer microprocessor according to the value in the difference counter.
Signals fed back from the carriage motor's rotary transducer are used to decrement the difference cou nter for each
1/120-inch of movement. When the difference counter is
decremented to zero, the carriage movement is complete,
and the microprocessor terminates the operation.
The logic that develops +PW INC and +PvV DEC is very
similar to that which produces +CAR X, shown in Figure
2-9. The major difference is that there are six flip-flops
instead of three, because both increment and decrement
pulses must be developed. Only three flip-flops set/reset
during each printwheel movement, depending upon the
direction of rotation; the other three remain static.
2.3.3
The CAR EVEN (Carriage Even), CAR POS A, and CAR
POS B (Carriage Position A and B) signals are developed on
the SERVO board; they are de.ived from signals fed back
from the carriage motor's rotary transducer. Their timing
relationships are shown in Figure 2-9, along with waveforms
of the 8080 INTERFACE board circuitry that they drive.
These three input signals each make one full "cycle" for
each 1/60 inch of carriage movement, which results in a
single pulse on the +CAR X line for each "half cycle," or
1/120-inch increment of carriage travel.
Once it has initiated carriage movement, the printer
microprocessor "reads" the +CAR X line periodically to
monitor the carriage movement. When it finds +CAR X
high, it decrements the difference counter, and issues an
instruction to reset the counter control flip-flop. Since the
response time of the printer microprocessor will vary, the
length of the +CAR X pulse in Figure 2-9 is shown by a
dotted line.
2.3.2.3
Option Jumpers
There is provision for three jumpers to be installed on
the 8080 INTERFACE board, but two of these cannot be
used with the Model 1610/1620 HyTerm. They provide for
terminal microprocessor control of ribbon advance and
printwheel addressing/hammer energy control. Since the
terminal processor's microprogram does not have the
capability of handling these items, the corresponding
jumpers should not be installed.
The third jumper, at board coordinates J53 on older
boards and H73 on newer boards, provides for 1/2 the
normal ribbon advance. It may be installed if a carbon film
ribbon is not used.
2.3.4
Oscillator
A simple LC feedback oscillator provides the CLOCK A
signal at 5 MHz, ±1 ()oA>. This signal controls circuitry on the
8080 INTERFACE board and on the XDCR board, and
provides the basic clock for the printer microprocessor on
the LOGIC-2 board.
PRINTWHEEL COUNTER CONTROL
2.4
The printer microprocessor maintains a running log of
printwheel position in its "printwheel absolute position
counter," located in RAM. Thus, the microprocessor always
"knows" the current printwheel position, and when it
receives a command to print a new character, it calculates
the shortest direction and the distance to be moved to
access the new character. It then initiates printwheel
movement, and uses feedback signals from the printwheel
motor's transducer to update the absolute position counter.
Since the printwheel can move in either direction, the
counter can be either incremented or decremented. Each
time the microprocessor increments or decrements the
counter, it compares the counter with the desired destination; when the two are equal, it removes printwheel motor
drive current and steps to the hammer-fire sequence. (This
logic also keeps track of printwheel position should the
wheel be turned by hand.)
LOGIC-2 BOARD, PART NO. 40510-4X
The LOGI C-2 board contains the printer microprocessor.
Refer to the block diagram in Figure 2-10. The wide buses
represent 8-bit bytes of data, and the narrow buses
represent three or four bits. The Output Latches provide
over 30 separate signals to the other printer boards.
The A and B registers provide temporary storage for
data. Both are 8-bit registers with the capability of
accepting data from either of two 8-bit data sources
(although one of the B-register's sources is hard-wired to
provide all zeros). The Table ROM contains up to 512 8-bit
factors (e.g., hammer intensity values) used by the microprogram; the Program ROM provides up to 512 16-bit
instructions. The computation logic contains an adder and a
comparator. When necessary to simply pass data through
the adder to the RAM, the microprogram adds zero to the
data. RAM capacity is 32 8-bit bytes. RAM output is the
complement of its input data. The output latches store over
30 bits of output data, but a maximum of eight of them
can be changed at anyone time.
Logic on the 8080 INTERFACE board receives the three
feedback signals from the SERVO board, PW EVEN
(Printwheel Even), PN POS A and PN POS B (Printwheel
Positions A and B). Depending upon the sequence in which
the position signals appear (determined by printwheel
direction of rotation), either +PW INC (Printwheel Increment) or +PN DEC (Printwheel Decrement) will be
developed. The printer microprocessor continually
The buses are connected to form three interrelated
loops: a Program control loop, a Data Processing loop, and
a Data Output loop. The Program Control loop components
control the other two loops. Thus they control all data
movement on the LOGIC-2 board, as well as all data
movement to and from the board.
2-15
2.4.1
The 14 line is used primarily to extend the ROM
addressing capability; the 15-18 lines are used for the basic
RAM address, and the 14 line selects which of two sets of
RAMs wi II be used.
Program Control Loop
After initialization, the Program Counter is reset, and
first addresses location zero of the Program ROM. This
ROM acts as both Program Memory and Instruction
Register. That is, it contains all printer microprocessor
instructions, and, when addressed by the Program Counter,
outputs the current instruction for as long as necessary for
completion.
2.4.5
Figure 2-12 illustrates the basic timing involved in the
operation of the printer microprocessor. Two clock signals,
+8 and +C, are derived from the -CLOCK A signal (from
the 8080 INTERFACE board) once +POWER ON goes
high, The +C clock is used to divide the instruction
execution into the two phases, and the +8 clock provides
intermediate timing. The A Register is loaded at the end of
every phase 1, when -C goes low. The 8 Register is loaded
at the midpoint of every phase 2, when +8 goes low. The
final waveforms in Figure 2-12 illustrate the timing of
several important signals relative to the 8 and C clocks;
note that these final signals do not occur in every
instruction cycle, but only in those requiring them.
For sequential program execution, the complete Program Control loop is not used. Instead, the Program
Counter, the Program ROM, and the decoder are all that is
needed to control data flow in the other two loops. The A
register is still used, however, to feed "immediate" data
from the Program ROM to the Data Processing loop. The
Program Control loop is completed when it becomes
necessary for the program to "branch" or "jump" to a
non-sequential location. When this occurs, the new instruction address is first loaded into the A-register, and then
transferred to the Program Counter. The next instruction
executed is that located in the Program ROM at the new
address.
2.4.2
2.5
SERVO BOARD, PART NO. 40520-XX
As shown in Figure 2-13, this board logically follows the
8080 INTERFACE board and the LOGIC-2 board. It has
four functions. First, it receives strobed processed command data from the LOGIC-2 board, and converts this
digital data input to a voltage level representative of the
absolute value of the desired velocity at which the carriage
or printwheel is to be moved. Since incoming data is
multiplexed, this D-to-A converter part of the circuit is
common, the printwheel and carriage functions being
steered to nearly identical but separate sample-and-hold
circuits. The voltage level output from each sample-andhold circuit is then switched in polarity to control the
direction of movement, and the resultant polarized voltage
Data Processing Loop
The data processing loop receives data from one or two
of four possible sources, performs some mathematic operation on this data, and stores the result in RAM.
The sources of data are (1) the 8080 INTERFACE
board, (2) the Table ROM, (3) the RAM, and (4) the
Program ROM. The A and 8 registers are used as working
registers, to temporarily hold the two 8-bit data bytes being
manipulated. Possible operations include adding the two
bytes together, subtracting the A register byte from that in
the 8 register, comparing the two bytes to see if they are
equal, complementing the RAM data, and passing data
through unchanged.
2.4.3
Timing
Data Output Loop
f - - - - - - - 112
1 - - - - - - _ 111
HIGH 1 - - - - - - - 110
Data is read from RAM, loaded into the A register, and
then loaded into the Output Latches, where it is continually available to the rest of the printer. Note that since the
RAM output is inverted, the complement of the desired
output data must be stored in RAM by some previous
instruction.
ORDER
ONLY
ROM
CEI
CEZ
~
Th is loop is used only for pri nter control data. Output
to the 8080 INTERFACE board is in the form of
instructions (on the 15-18 lines) which are decoded on that
board to provide the desired action.
2.4.4
PHASE
1
f------_19
18
17
16
15
]
LOW
ORDER
Basic Operation
ROM
Refer to Figure 2-11. Instruction execution is divided
into two halves, called phase 1 and phase 2. The op code is
present on the 11-13 lines during both phases. The "from"
address, or data source, is on the 15-112 lines during
'phase 1, and the lito" address, or destination, is on the
15-18 lines during phase 2. The 19-112 lines are not used
during phase 2.
--____ 14
ONLY
I
. J
- - - - - 13
12
-11
PHASE
2
PHASE S
1 AND 2
Figure 2-11. Basic Operation, Printer Microprocessor
2-16
is presented to a summing amplifier as the velocity command signal. Second, dual tachometer circuits convert
incoming analog position signals to a voltage level which
represents the actual servo velocity. Three digital position
signals are derived from the analog position signals by a
series of comparators. These digital position signals represent
distance moved, and are supplied back to the 8080 INTERFACE board where they are used to generate increment
LOGIC-2 board. Third, the voltage level of velocity is
summed with the velocity command signal to generate a 0 to
7 volt maximum servo error signal used to develop the actual
servo motor drive current. Fourth, the D-to-A converter
output is used on a multiplexed basis to process print hammer energy commands, which are forwarded to the PW PWR
AMP board.
Refer to F igu re 2-13 and to the schematic diagram to aid
in understanding the following discussions.
and/or decrement counts for the position memories on the
+CLOCK A
+POWER ON
rLOAD
t
+8
+C
B REGISTER
LOAD
A REG
~+
I
LOAD
=y
A~+
2
2
Phase
2
S
PRGM CNTR
-ENA INP
-WRITE RAM
-LOAD OUTPUT
LATCHES
-RST
Figure 2-12. Basic Timing, Printer Microprocessor
r-----------------------------,
SERVO PCB
ASSEMBLY
I
I
I
f
MODE SELECT
I
I
IL
_______________________________
Figure 2-13. Block Diagram, SERVO Board
2-17
I
I
~
2.5.1
holding capacitor C in the feedback circuit of amplifier A.
Capacitor C holds this voltage until the printer microprocessor again strobes the O-A output. The microprocessor's cycle rate is such that it may update the charge
on the capacitor 100-200 times before it actually modifies
the data. The processor can modify this data only when the
associated transducer has experienced a "track crossing",
which occurs each time the carriage or printwheel has
moved one increment. Amplifier A follows and inverts the
charge on capacitor C, to produce a O-to-negative-going
voltage which represents the velocity command for the
associated servo. Transistor a buffers the ampl ifier's output, and provides drive current for the circuits following.
D-A Converter Circuit
This common input stage serves both the carriage and
printwheel channels as well as the print hammer circuit. It
consists of an 8-bit D-A converter, an operational amplifier,
a buffer/driver transistor, and associated components as
shown in Figure 2-14.
A reference current generator, consisting of resistors F9
and FlO and noise suppressing capacitors F6 and F7,
provides a reference current for the D-A Converter G12, a
monolithic 8-bit digital-to-analog converter. It supplies an
output current which is the product of the 8-bit digital
word in put and the reference current input. This output
consists of the decimal equivalent of the binary weighted
value of the digital input divided by 256 such that if ALL
inputs were high (=255), the output current would equal
255/256 or 99.6% of the reference current.
2.5.3
Refer to the schematic diagram. The carriage and
printwheel Sample and Hold circuits are nearly identical.
Each contains two paths. One path goes through a 2K
resistor to a switching FET, while the other path goes
through an inverting operational amplifier to a second
switching FET, with the output of both FETs tied together.
This means that the negative-going output of the Sample
and Hold circuit is supplied as a negative-going voltage to
one FET and as a positive-going voltage to the other FET.
The gates of these FETs are controlled by inputs from the
printer microprocessor, labeled FWD and REV, through
inverters and voltage divider networks. The microprocessor
can then select the correct polarity of signal to be presented
to the summation circuit to control ultimate direction of
servo movement.
The output of G 12 is supplied to operational amplifier
E12-6. This amplifier, with its associated components,
comprises a current-to-voltage converter. Buffer/driver
transistor E6 in its feedback loop provides a drive current
source for the stages following, through resistors D 10 and
F23. The output level from transistor E6 is 0 volts (all
inputs low) to approximately +9.95 volts (all inputs high).
During hammer-fire sequences, this circuit is utilized to
provide a time/amplitude profiled output to the hammer
drive circuits which serves to regulate the print hammer
energy synchronized with the character to be printed,
where some characters, such as periods and commas,
require much less printing energy than others, such as the
During those times in printer operation when carriage
and/or printwheel motion has stopped, and before the
hammer- fire sequence is complete, the associated servo
must be detented to hold its position. To accomplish this, a
signal called LIN EAR POS SIG is generated on the XDCR
board and presented to a third switching FET whose output
is also tied to the summation circuit. This FET is A12-7 for
the carriage circuit, and A32-15 for the printwheel circuit.
The input to the gates of these FETs comes from the
printer microprocessor through the normal inverter/divider
network, and is labeled LINEAR MODE. This associated
servo system is detented when the microprocessor gates the
LINEAR POS SIG to the summation point, while at the
same time holdi ng the two associated position switch ing
FETs in their off state.
M.
2.5.2
Servo Direction Switching
Sample and Hold Circuit
Figure 2-15 illustrates a typical Sample and Hold circuit
with the basic timing involved. As shown, the circuit
consists of an input switching FET, an operational amplifier
(A) coupled to a buffer/driver transistor (0), and associated
components.,
I n operation, the output of the D-A Converter is
presented to the switching FET through a resistor R 1
(shown as resistors D 10 and F23 on the schematic
diagram). Approximately 6 microseconds after the arrival
of data on the data bus input to the D-A Converter, the
printer microprocessor issues a 2- microsecond Velocity
Strobe pulse through an inverter and voltage divider
network to turn on the switching FET. When on, the FET
couples the output voltage from the D-A Converter to
30 ms after gating in the LINEAR POS SIG following
the last position command strobe, the printer microprocessor activates the SERVO DISABLE signal. This turns
off the power amplifier and effectively removes current
flow through the servo while it is at rest. This is called the
"Float Mode".
2-18
Carriage position information is not maintained within
the printer circuits. Any carriage drift or non-commanded
movement would desynchronize the terminal microprocessor's carriage position information. Any carriage
movement, therefore, triggers a response to remove the
"float mode" and drive the carriage back to its last
commanded position.
In the printwheel circuit, the absolute counter is
Tlaintained in synchronization with printwheel position at
:111 ti mes, even if the printwheel is manually moved or
;hould drift. In this way, printwheel movement in response
to the next command can start from wherever the
printwheel happens to be when the command is received.
+sv
TO CARRIAGE CKT
+~V
FlO
X
010
..
~
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
4
I
2
+U5S
3
4
GI2
TO HAMMER
ENERGY CKT
~
6
7
-.INPUT
-
GI6
E6
-I~S
F23
-I~S
TO P. W. CKT
Figure 2-14. O-A Converter
eUTPUT
O-A CONV.>-_____~~~~~
INPUT
O-AINPUT
-.J,..... :
C
I.. 6 JJSEC_
VELOCITY
STROBE
_.;...._ _--'.12 USEC
Q
Figure 2-15. Typical Sample and Hold Circuit
2-19
VEL. STROBE IN.
L
L
.>;;--+-~~~~~~---{) 16+/-CAR SERVO ERROR
~~1
0"
DS8
'OK
057
'0"
--_. '~--~--------D
POS SIG 3
44
+ CAR
EVEN
>--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~-o 52-CAR POS B
-~~~~~~~~~~~~~~~~~~~~~~~-o 53-CAR POS A
Figure 2-16. Carriage Position Tachometer Circuit
CAR POS SIG
1
CAR POS SIG 2
CAR POS SIG 3
-CAR
POS
B
-CAR
POS
A
Figure 2-17. CAR POS Tachometer Waveforms
2-20
2.5.4
at the capacitor-resistor ju nction in each network. Since
servo velocity is seen here as frequency, the higher or lower
the velocity, the higher or lower the level of the differentiated squarewave. The waveforms in Figure 2-18 depict
carriage motion at a constant velocity. Servo velocities of
less than that shown would produce a lower differentiated
input to the FETs, while velocities greater than this would
produce higher inputs. The control pulse to each FET will
turn on the FET to pass either the positive or negative
portion of the differentiated signal, depending on the
direction of servo movement. The FET outputs are applied
contiguously to the input (pin 1) of amplifier C60-12, with
the combined resu It representing servo velocity. Amplifier
C60-12 inverts the input and presents it to the velocity
summation junction (pin 7) of the servo summation
amplifier C24-1 0 as negative feedback.
Servo Tachometer Circuits
Figure 2-16 is a partial schematic diagram showing the
carriage position tachometer and associated circuits. Only
the carriage circuit will be discussed; the printwheel circuit
is very similar.
Figure 2-17 shows waveforms taken in these circuits.
The design of the transducer on the carriage servo motor is
such that each complete cycle of the sawtooth waveform
inputs represents 1/120 inch (.212 mm) of carriage travel.
Thus, wh ile these sawtooth inputs do not vary in amplitude, they do vary in frequency. This variation, or
modulation, follows actual servo speed, with the waveshape
itself tracking carriage position.
Three phase-modulated triangular waveshapes are generated by the XDCR board in response to movement of the
servo shaft. These signals, POS SIG 1, 2, and 3 (Figure
2-17) become the inputs to high speed comparators E48
and E72 (Figure 2-16). Their outputs are squarewaves. The
duration of these squarewaves follows the frequency of the
sawtooths inputs. They pass through inverters, whose
outputs, -CAR pas A and -CAR pas B, are sent to the
8080 INTERFACE board for use in the position counter
increment/decrement circuits. The CAR PQS SIG 3 input is
also sent through inverting amplifier C60-1 0 to develop the
+CAR EVEN signal also supplied to the 8080 INTERFACE
board.
2.5.5
Servo Summation Ampl ifier
This amplifier, C24-10 for carriage and C36-12 for
printwheel, is the output of the servo velocity command
circuit. It is an operational amplifier with a compensating
capacitor, zener clamp diodes, and a gain resistor in its
feedback loop. The back-to-back 6.2 volt zener diodes, plus
their normal voltage drop, provide a bi-directional voltage
clamp which limits the amplifier output to +7 volts. Since
each volt of signal output here produces a fixed value of
drive current later on in the servo motor, it is necessary to
establ ish this voltage limit to safeguard the servo motor.
The pas A and B squarewaves are also channeled
through a series of inverters and gates to supply waveforms
cp 1, cp2, cJ>3, and ¢4. These signals are used to control the
feedback FETs C72-15, -2, -10, and -7, respectively.
The input to this amplifier is then either the sum of
actual velocity and velocity command voltages, or the
LINEAR pas SIG input and velocity signal. The output is a
voltage which is directly proportional to the desired
amount of servo drive current. The output is labeled
+/- SERVO ER ROR.
The three POS SIG sawtooth waveforms, and pas SIG 3
inverted, are supplied to the control FETs through differentiating networks. Figure 2-18 shows the waveforms taken
CAR POS I
CAR POS 2
CAR POS 3
CAR POS 3
Figure 2-18. CAR POS FET Input Waveforms
2-21
H48-1~
H48-14
CARl PW I
J8-A J8-8
H48-13
4
7
H48-12
CAR/PW3
J8-A J8-8
7
3
H24-15
H24-14
H24-13
H24-12
a
b
Figure 2-19. Sinewave Drive Generator VVaveforms
STATOR
ROTOR
(A REPRESENTATION -WINDING DIMENSKJNS EXAGGERATED FOR CLARITY)
ROTOR SEGMENTS
STATOR SEGMENTS
NO- OFFSET STATOR
90° OFFSET STATOR
Figure 2-20. Servo Position Transducer
2-22
etched on adjacent surfaces. The rotor is mounted on the
free end of the servo motor shaft, with the stator mounted
over it and fastened to the motor case. Output signals from
the rotor are picked up by means of an axially mounted
rotary transformer.
2.6 TRANSDUCER (XDCR) BOARD, PART NO.
40515-03
This assembly contains all of the circuits necessary to
generate the sine-wave drive for the carriage and printwheel
transducer stator windings, to demodulate the resu Itant
phase-modulated carrier coming from the transducer rotor
winding, and to produce three triangu lar position signals
and one linear mode signal each for the carriage and
printwheel tachometer circuits on the SERVO board
(Figure 2-16). Where carriage circuits are discussed in the
following paragraphs, similar circuits exist for the printwheel.
2.6.1
As shown in Figure 2-20, the stator has an eight-segment
"winding," with alternate segments connected together to
form two groups of four. The four segments of one group
are displaced laterally from the other group by a distance
equal to one-half a winding width. This displacement is
equal to a 90° phase difference. The rotor has a single
symmetrical winding.
Sine-Wave Drive Generator
The two sinusoidal waveforms shown in Figure 2-19b are
applied to the transducer's stator windings. Since all the
windings in the device are nearly 1: 1, the only transformation of the inputs is phase modulation caused by rotar
movement. The phase-modulated output (Figure 2-22a) is
applied to the Servo Feedback Amplifier.
The 5 MHz -CLOCK A input from the SOSO INTERFACE board is used to clock two shift registers, H24 and
H4S. These two modules are 4-bit parallel-access shift
registers connected to form a divide-by-sixteen circuit. The
outputs, shown in Figure 2-19a, are squarewaves, where the
output of H4S-15 is followed one clock later by H48-14,
and so forth. When H24-12 goes high, feedback through
H24-11 (low) and through gate H30-S drives the output
H4S-15 low. This condition then cascades through the
registers again until H24-12 goes low, when H24-11 (high)
will drive H4S-1 5 high to start the cycle again.
2.6.3
Figure 2-21 is a partial schematic showing the Carriage
Servo Feedback Amplifier, which comprises a two-stage RF
amplifier and a squaring circuit. Since both carriage and
printwheel circuits are nearly alike, only the carriage
channel will be discussed.
These squarewave outputs are connected through
inverters, pull-up resistors, and load resistors to four output
lines-two for carriage circuit use and two for printwheel
circuit use. The inverters act as switches, allowing current
to flow through the associated load resistors whenever the
inverter output is low. Seven of the inverter outputs are
selected for summation to form each of the four output
signals, CAR 1, CAR 3, PW 1, and PW 3. The values of the
several load resistors, plus a capacitor connected from each
output line to their common return line produces a set of
two-phased sinusoidal waveforms, shown in Figure 2-19b,
for both the carriage and the printwheel circuits. These two
signals are fed to the stator "windings" on their respective
position transducer.
2.6.2
Servo Feedback Amplifier
Figure 2-22 shows waveforms appearing in this circuit.
Waveform A is the phase-modulated servo transducer
output, as seen at the input to the first video amplifier,
810-1&14. Amplifier 810 has an adjusted gain of approximately 20. It amplifes and partially filters the input, as
shown at its output, waveform B, taken at 810-7&8. The
second video amplifier, D10, also with a gain of about 20,
further filters the signal and generates a 10-volt peak-topeak output waveform (C) which displays some squaring
due to saturation limiting. This output, from 010-7&8, is
applied to a high-speed squaring comparator module F10.
This amplifier is overdriven, and produces a squarewave
output, which is passed on to the Servo Feedback
Demodu lator/! ntegrator / Ampl ifier.
Servo Position Transducer
The Servo Position Transducer consists of rotor and
stator members made up as flat disks with "windings"
CARRIAGE AI' AMPLIFIER
ROTARY;]
TRANSFORMER
(ON TRANSDUCER)
[
C~~A 6
0--------i
Ail
-6VF
910"",
Figure 2-21. Servo Feedback Amplifier
2-23
A
I st VIDEO AMPL. INPUT
810-1/14 (810-1 INVERTED)
B
I!! VIDEO AMPL. OUTPUT
B10-7/8 (810-7 INVERTED)
C
2 nd VIDEO AMPL. OUTPUT
010-7/8 (010-7 INVERTED)
Figure 2-22. Servo Feedback Amplifier Waveforms
2-24
2.6.4 Servo Feedback Demodulator/Integrator/
Amplifier
The "input" in Figure 2-23 is the phase-modulated signal
from the carriage servo transducer, after it has been squared
and inverted by the Servo Feedback Amplifier (output of
comparator F 1 0). This is also shown as waveform B in
Figure 2-24a. The "REF" inputs, one of which is shown as
waveform A in Figure 2-24a, are from the Sine-Wave
Drive Generator. These signals are exclusive-O Red to
produce a waveform such as that shown at C in Figure
2-24a. The XO R outputs are applied to integrators which
Figure 2-23 is a partial schematic of the Carriage Servo
Feedback Demodulator/Integrator/Amplifier. This circuit
receives the output of the Servo Feedback Amplifier,
synchronizes it with the Sine-Wave Drive Generator, and
develops the th ree sawtooth waveforms, CA R POS S IG 1,
2, and 3, which are then passed on to the SE RVO board.
INVERTER
A41
75pF
A42 5.IIK
CAR POS
+OVF
SIG
B42100K
#2
CAR POS
INPUT--~~
SIG
*1
G42
loOk
CAR CUSP--+----+~
REF
G40
lOOK
D42100K
--~~~---------~47 CAR~S
I~~.n
SIG #3
HIVF
C42
lOOK
~12~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~46 ;~~ ~II~EAR
Figure 2-23. Servo Feedback Demodulator/Integrator/ Amplifier
A
CAR POS SIG*1
B
CAR POS SIG*2
c
CAR POS SIG'1I3
a
b
Figure 2-24. Servo Feedback Demodulator/Integrator/Amplifier Waveforms
2-25
"average" the voltage in the pulse train. This instantaneous
average voltage is amplified to produce the carriage position
signals shown in Figure 2-24b.
causes the high/low ratio of the output (waveform C) to
vary.
Refer now to Figu re 2-25. As the carriage moves, the
varying output of the XOR gate is applied to an integrator,
which takes the average voltage value of the pulse train and
applies it to an amplifier. The output of the amplifier is one
of the sawtooth waveforms, CAR POS SIG 1,2, and 3.
If the two inputs and the output of one of the XOR
gates F48-3 or F48-11 are observed on a mu Iti-channel
oscilloscope (synchronized to the Sine-Wave Drive Generator), moving the carriage by hand will cause the input
from the Servo Feedback Amplifier (waveform B) to move
with respect to the "reference" input (waveform A). This
When the carriage is stopped, the lower circuit in Figure
2-23 develops CAR LIN POS SIG, which is used to detent
the servo.
MOTION
=O~ a.a
~
t..rUlJI.I1.TIT
~
~
Ave I.BV
=
Ave '.711 V
Avell.OV
~
_+IIV
_.n'~
~
~~
Ave O.OV
~
~
AIIW 1.IIIV
~
~
~
ITIT.D.TI.JlIJ.
DEIIOD
~
~
=
REF
DEMODULATOR
INT£ClltItTOR
~
~
~
,::!IZ
aAa
Figure 2-25. CAR POS SI G Development
2-26
-
OV
2.7 CARRIAGE POWER AMPLIFIER BOARD,
PART NO. 40525-XX
+15V
1
S2
SI
MTR
~~ T"~'V1'--=-1- - - I
NOTE
i
S3
DO NOT stand the HyType 1/ Printer on
its rear heat sink panels. The finned heat
sinks are mounted on plug-in circuit
boards which can be easily damaged by
this practice.
2.7.1
!
1
This assembly includes the Carriage Servo Power
Amplifier, the Paper Feed Drivers, and the Power Monitor
circuits. It is located in board slot 0, and has a finned heat
sink attached to it, to help cool the several driver
transistors.
FEED BACK
S4
J
T
-15V
Figure 2-26. Simplified Diagram, Carriage
Power Amplifier
Carriage Power Amplifier Circuit
Figure 2-27 is a simplified schematic diagram of the
feedback circuit. This circuit includes the 0.1 Ohm resistor
C53 located in one of the lines to the servo motor, across
which is connected a precision balanced 10K Ohm resistor
network and difference amplifier 862-10. The value of
resistor C53 is such that its voltage drop to current ratio is
1 to 10 (0.1 volt drop equals 1.0 ampere of motor current).
Difference amplifier 862-10 inverts this voltage, and
presents the result to the servo error input terminal 2 of
amplifier 855-6. The two signals are summed at a ratio of
NOTE
This circuit is nearly identical to the
Printwheel Power Amplifier Circuit described in Section 2.8. 1
This circuit supplies and controls ,current flow to the
carriage servo drive motor. It is designed as an "H" bridge,
allowing all current to flow through the motor from supply
to supply instead of through circu it ground, to avoid circuit
noise problems. Figure 2-26 illustrates the basic circuit in
simplified form, where certain transistors in the actual
circuit are represented as switches. Closing switches Sl and
S4 will cause current to flow through the motor and
resistor R right to left, while closing switches S2 and S3 will
cause current to flow left to right.
10 input to 1 feedback. As current through the drive motor
approaches the command level, the output of 855-6 wi"
diminish. When motor current matches command current,
the PU LSE REV transistor F63 will be turned off. This
removes motor current, which removes feedback voltage,
and F63 is turned back on again. The circuit will oscillate in
this manner to mai ntain motor current at the commanded
level.
Referring to the schematic diagram and Figure 2-26 will
aid in understanding the operation of the circuit itself.
Since the amplifier is composed of several similar circuits,
only one path will be discussed.
Should the Power Monitor circuit detect an input
voltage error, it will turn transistor E77 on, turn ing off
PULSE FWD and PULSE REV transistors F47 and F63 to
disable carriage servo movement.
Assume a CAR SERVO ERROR signal input of +1 volt
for a commanded motor current of 1 ampere. The output
of operational amplifier 855-6 will be low, and this will
place a low potential on the base of transistor G58 and on
the emitter of transistor G73. G73 will turn off. G73 being
off turns transistor E70 off, which turns transistor E65 on
to turn on PULSE REV transistor F63.
10K
The error signal is also supplied to amplifier A50-6, the
output of which is zero volts with a positive input. This will
turn off transistor d42, which turn 045 off and E44 on,
which turns on DR IVE REV transistor 048.
10K
ERROR
FWD/REV.
PULSE
AMPLIFIERS
OTHER
CKTS
Referring to Figure 2-26 transistor 048 is shown as
switch S2, while transistor F63 is shown as switch S3.
Turning these two transistors on establishes a current path
from the +15 volt supply through 048, resistor C53, the
drive motor, and F63 to the -15 volt supply.
Figure 2-27. Servo Feedback Circuit
2-27
2.7.2
Power Monitor Circuit (Figure 2-28)
This condition disables the printer functions as outlined
above.
The purpose of this circuit is to inhibit paper feed,
printwheel movement, and carriage movement by generating a series of disabling signals any time one or more of the
three su pply voltages drops below a level where incorrect
operation might result. These signals also reset all printer
microprocessor program and logic circuits to their initial or
zero condition.
At the end of the delay (approximately 25 ms),
transistor 822 is turned on, turning transistors A30, B23,
C36, and C34 off, allowing their outputs to all go high. This
removes the circuit disable clamps, starts the LOGIC-2
program counter, and initiates a Restore sequence.
Any subsequent interruption in, or decrease of, any of
the three input voltage levels sampled will disable the input
AND circuit leading to discharge of capacitor A22. This
clamps the output low again to disable the printer.
Complete restoration of power recycles this circuit, putting
the printer in a proper condition to resume operation.
The circuit operates as follows: as power is turned on,
the base of transistor 812 takes a negative value, and
transistors 812 and 813 are off. Three divider networks
begin to sample the voltage levels being supplied: zener
diode 85 and resistor A 11 sample the +5 volt input; zener
diode A 7 and resistor A9 sample the +15 volt input; and
zener diode 87 and resistor 86 sample the -15 volt input.
As these voltages approach their appropriate values, diodes
A 12, A8, 88, and 89 (operating as an AND gate) are
reverse-biased. The base of transistor 812 becomes sl ightly
positive, and transistors 812 and 813 turn on. Up to th is
time, transistor 816 had been on. \l\/hen transistors 812 and
813 turn on, transistor 816 tu rns off, capacitor A22 begins
to charge through resistor A24, and transistor 822 is biased
off. With transistor 822 off, transistors A30, 823, C36, and
C34 are all biased on, and their outputs are all clam ped low.
2.7.3
Paper Feed Drive Circu it
The paper feed stepping motor has two sets of windings,
referred to as Phase A and Phase B. Current can be driven
through both coils in either direction, providing four
different combinations. The sequence in which the current
0
is switched in the two windings (90 out of phase)
determines the direction of motor rotation (Figure 2-29).
When Phase A leads Phase S, the motor rotates clockwise
(viewing the shaft end), providing upward paper movement;
when Phase 8 leads Phase A, the motor rotates cou nterclockwise, moving the paper down.
E77
CARRIAGE
SERVO
DISABLE
-SERVO
DISABLE
IN
POWER MONITOR CKT
r
B2
.1
i+
+15S
5V
A26
2K
85
'JV
All
IK
AI2
PW SERVO
ENABLE
-1!lS
POWER ON
(LOGIC DISABLE)
825
PAPER FEED
DISABLE
Figure 2-28. Power Monitor Circuit
2-28
7
3
4
8
PHASE A
1
4
5
8
PHASE B
2
-A
-8
+A
+B
-B
+A
+8
1
2
3
4
-A
5
1
6
-A
-8
-A
+8
2
PHASE A
2-.....-'1
+B
+A
-B
4
3
,
3~4
3 ---..4
( }
+A
0.
(CW)
MOTOR SHAFT
2
END VIEW
T4
T7
2 --.- 1
(CCW)
MOTOR SHAFT
1
T6
{
PHASE B
T5
END VIEW
r - - - - - - - - - - - - --.,
+PFA - - - - - - ,
I
+ 15 V
--1IIIIt-------lJ._
-15V
+ PFB
L
I
I
- - -
PAPER FEED
-
- -.J
DRIVE
CIRCUIT
--------------
Figure 2-29.
.J
333 - 001
Paper Feed Stepping Motor Operations
2-29
P F B
DIFF B (G12-G17)
P F A
DIFF A (F28-F35)
~
av.
IT
av.
PHASE B
DETENT CURRENT
PHASE A
DETENT CURRENT
Figure 2-30. Paper Feed Drive Waveforms
2.8
PRINTWHEEL POWER
BOARD, PART NO. 40530-XX
The Paper Feed Drive circuit consists of two identical
channels, one for Phase A and one for Phase B. The printer
microprocessor provides pulses on +PFA and +PFB in the
correct sequence and quantity for the desired direction and
distance of paper movement. Refer to the Phase B circuit at
the bottom of schematic no. 40525. (The Phase A circuit is
the same-only the Phase 8 circuit will be covered.)
Incoming pulses (Figure 2-30) are differentiated by the
circuit comprising capacitor G12 and resistors G17 and
G20, providing a 4-5 ms pulse to the input (pin 7) of the
amplifier F18-10. This amplifier's output is coupled to
current amplifiers D22/24 and E12/21, which provide the
higher current required for stepping the motor.
AMPLIFIER
This assembly includes the Printwheel Servo Power
Amplifier, the Ribbon Lift and Ribbon Feed Drivers, the
End-of-Ribbon sensor amplifier, and the Hammer Energy
Control and Driver circuits. It is located in Printer board
slot H, and has a finned heat sink attached to it, to help
cool the several drive transisters.
NOTE
DO NOT stand the HyType /I Printer on
its rear heat sink panels. The finned heat
sinks are mounted on plug-in circuit
boards which can be easily damaged by
this practice.
The waveforms in Figure 2-30 represent one complete
line feed operation (eight 1/48 inch increments crt 6 lines
per inch). One increment is represented by each level
change in either Phase A or Phase B, and is equal to 7-1/2°
of stepping motor shaft rotation. Thus each line feed
produces 8 x 7.5° = 60° of shaft rotation at 6 lines per
inch.
2.8. 1
Printwheel Power Amplifier Circuit
NOTE
This circuit is nearly identical to the
Carriage Power Amplifier circuit described in Section 2.7.1.
The paper feed motor is detented electrically when
paper movement is complete. Again, discussing channel 8
only, a circuit comprising resistors G10, G16, and G18 (+5
volts to -15 volts) provides enough output from amplifier
F18-10 to supply about.4 amp motor current, sufficient to
hold the stepping motor in position.
This circuit supplies and controls current flow to the
printwheel servo drive motor. It is designed as an "H"
2-30
bridge, allowing all current to flow through the motor from
supply to supply instead of through circuit ground, to avoid
circuit noise problems. Figure 2-26 illustrates the basic
circuit in simplified form, where certain transistors in the
actual circuit are represented as switches. Closing switches
S1 and S4 will cause current to flow through the motor and
resistor R right to left, while closing switches S2 and S3 will
cause current to flow left to right.
2.8.2
Ribbon Lift Driver Circuit
This circuit consists of two subcircuits; one for ribbon
lift and one for ribbon hold. The ribbon lift portion
includes transistors G67 and H59. The -RIBBON LI FT
signal turns G67 on to apply a ground potential to the base
of H59. H59 turns on, applying -15 volts to one side of the
ribbon lift coil. The opposite side of the coil is connected
to +15 volts. The coil is then energized with a potential of
30 volts, to provide maximum power to rapidly lift the
ribbon. At the end of the ribbon lift sequence, the printer
microprocessor removes the -RIBBON LIFT signal and
replaces it with the -RIBBON HOLD signal. The ribbon
hold portion of the circuit includes transistors H67 and
H61. The -RIBBON HOLD signal turns on transistor H67
applying a ground potential to the base of H61. H61 turns
on, applying a ground potential to one side of the ribbon
lift coil. The coil is then maintained in its energized state
(ribbon lifted) with a potential of 15 volts.
Referring to the schematic diagram and Section 2.7.2
will aid in understanding the operation of the circuit itself.
Since the amplifier is composed of several similar circuits,
only one path will be discussed.
Assume a PW SERVO ERROR signal input of +5 volts
for a commanded motor current of 1 ampere. The output
of operational amplifier A31-6 will be low, and this will
place a low potential on the base of transistor H18 and on
the emitter of transistor H35. H35 will turn off. H35 being
off turns transistor F32 off, which turns transistor E30 on
to turn on PU LSE REV transistor G26.
2.8.3
The error signal is also supplied to amplifier A 19-7. The
output of amplifier A 19-7 will be zero volts with a positive
input, which will turn transistor C4 off. This will turn
transistor 05 off and transistor E6 on to turn on DRIVE
REV transistor C 1O.
Ribbon Feed Drive Circuit
NOTE
This circuit is nearly identical to the
Paper Feed Drive circuit described in
Section .2 7. 3.
Referring back to Figure 2-26, transistor C1 0 is shown as
switch S1, while transistor G26 is shown as switch S4.
Turning these two transistors on establishes a current path
from the -15 volt supply through G26, resistor G23, the
drive motor, and C1 0 to the +15 volt supply.
Refer to Figures 2-29, 2-30, and schematic no. 40530.
The Ribbon Feed Drive circuit consists of two identical
channels, A and B. Figure 2-30 shows typical input and
output waveforms for each channel.
The A and B inputs, 90° out of phase, are presented to
type 747 operational amplifiers E74-12/-10 where they are
squared and amplified. The output of these amplifiers is
coupled to current amplifiers of F48/D50-D43/F45 for
channel A, and F64/D64-D58/E58 for channel B, where the
drive for the ribbon feed step motor is developed.
Figure 2-27 is a simplified schematic diagram of the
feedback circuit. This circuit includes a 1.0 Ohm resistor
G 23 located in one of the lines to the servo motor, across
which is connected a precision balanced 10K Ohm resistor
network and difference amplifier A45-12. The value of
resistor G23 is such that its voltage drop to current ratio is
two-to-one (2-volt drop equals 1 ampere of motor current).
Difference amplifier A45-12 inverts this voltage and presents the result to the servo error input terminal 2 of
amplifier A31-6. The two signals are summed at a ratio of
10 input to 1.6 feedback, so that as motor current
approaches the command level, the output of A31-6 will
diminish. When motor current matches command current,
the PUl SE REV transistor G26 will be turned off. This
removes motor current, which removes feedback voltage,
and G26 is turned back on again. The circuit will oscillate
in this manner to maintain motor current at the commanded level.
The information in Figure 2-29 further illustrates the
development of the stepping motor rotation from the two
out-of-phase inputs. It should be noted, however, that
unlike the paper feed operation, ribbon feed is in one
direction only.
2.8.4
Hammer Energy Control and Drive Circuit
Figure 2-31 is a simplified schematic diagram of the
Hammer Energy Control circuit. The HAMMER ENERGY
CONTROL signal from the D-A Converter on the SERVO
board is the input to this circuit. This is a signal whose
instantaneous level depends on the character to be printed.
The norm al range of th is signal is 0 to + 10 volts.
Should the Power Monitor circuit detect an input
voltage error, it will drive the +PN SERVO ENABLE signal
low. This will turn transistor E35 on, turning off PU LSE
FWD and PULSE REV transistors G10 and G26 to disable
printwheel servo movement.
The input· is applied to board pin 50 and to the wiper
arm of the operator's Impression Control Switch. The
output of the amp I ifier A45-10 is then dependent on the
2-31
P3[:C5J~1~
IMPRESSION
CONTROL SWITCH
J3 L _____________ . __ -'
INPUT
C44
OUTPUT
4.12K
Figure 2-31. Hammer Energy Control Circuit
pass the data between the level converters and the current
loop network while providing electrical isolation between
the HyTerm and the network. (Note that the Opto Coupler
boxes in Figure 2-32 include not only the optical couplers,
but also the additional support circuitry necessary. These
circuits are explained in 2.9.2 and 2.9.3.)
position of this switch, i.e., whether a portion of the
Impression Control Switch input is added to or subtracted
from the Hammer Energy Control input.
The -HAMMER FI RE pulse from the printer microprocessor turns transistor H50 on, to drive the hammer
enabling circuits. The hammer- fire pulse from H50 is
compared with the hammer energy level in comparator
A64-7, and also enables transistor C65. The output of C65
switches driver transistor C73, and also establishes its
output level to control the amount of current flowing to
the hammer coil.
2.9.2
Refer to Figure 2-33. The receiver circu it can be thought
of as having three terminals, two of them inputs and one an
output. The two inputs are the connections to the LED in
the opto coupler. The output provides data, at E IA voltage
levels, to the HPRO board. This data is ultimately passed on
to the 8080A MPU by the USART.
2.9 HCUR L BOARD (OPTIONAL)
This section provides a brief theory of operation and
circuit description of both the HCU R L board electronics
and the current loop network.
2.9.1
Receiver Circuit
Depending upon the type of current loop network
employed, the actual connections to the LED are different.
This is discussed in 2.9.4. In any case, current flowing in
the loop represents a "Mark," or logic 1 condition. This
illuminates the LED in the opto coupler, which turns on
the phototransistor, placing a "high" at the input to the
75150 level converter. This drives -DATA RECEIVED to
approximately -7 Volts, the EIA level for a "Mark"
condition.
General Operation
The HCUR L board serves as the interface between the
terminal microprocessor (on the HPRO board) and the
current loop network. This is shown in Figure 2-32. The
HPRO board operates in the same manner regardless of the
type of network used, and the HCU R L board, through the
proper placement of the jumpers and resistors, is tailored to
adapt the HPRO board to a particular type of network.
When current flow in the loop ceases, the LED goes
dark, the phototransistor turns off, and -DATA RECEIVED
rises to about +7 Volts, the EIA level for a Space condition.
The normal use of the HPRO board I/O circuitry is to
drive an EIA RS-232-C interface. To accomplish this, it has
voltage level converters on its I/O lines to adapt the TTL
USART to the EIA interface voltage levels. The HCURL
board uses identical voltage level converters to change these
EIA levels back to TTL levels. Optical couplers are used to
The resistor between the em itter and base of the
phototransistor acts as a positive feedback to help in
speeding up the turn-off time. The phototransistor output
is fed into a 7414 Schmitt trigger inverter, which provides
noise immunity and clean edges on all signal transitions.
2-32
FULL -DUPLEX
HCURL
HPRO
....
DATA BUS
U
S
A
R
T
'\
/
V
't
~
..
LEVEL
-.. CONVERTER
LEVEl
SCONVERTER
A
NETWORK
,
OPTO
")
I
~
COUPLER "-
HOST
COMPUTER
AND/OR
LEVEl
_
CONVERTER
LEVEl
CONVERTER
OTHER
OPTO
..
--
" I TERMINALS
I'
I
~
COUPLER "-
HALF-DUPLEX
HCURL
HPRO
SCONVERTER
to..
,.,
DATA BUS
r
""/
U
S
A
R
T
rL
..
LEVEl
LEVEl
A
NETWORK
-- CONVERTER
OPIO
-
,..
COUPLER I
LEVEl
CONVERTER
--
HOST
I
: COMPUTER
+-
I
I
,
\
LEVEl
CONVERTER
"'\
OPTO
COUPLER
'-
-..
I
AND/OR
OTHER
./ TERMINALS
496-002
Figure 2-32. Block Diagram, Current Loop Data Flow
r- --(jPTO----,
I
COUPLER
I
I
~
I
I
I
I
I
L _ _ _ _ _ _ _ _ -1
-DA TA RECEIVED
TO USART
496-003
Figure 2-33. Receiver Circuit
2-33
2.9.3
Transmitter Circuit
However, the operation of the basic transm itter is the same
in all cases.
Like the receiver circuit, the transmitter circuit can be
thought of as having three terminals. Its input, at EIA
voltage levels, comes from the USART (through a level
converter) on the HPRO board. Its two outputs are
connected to the current loop network so that the
transmitter is essentially a switch, opening and closing the
current loop.
The extra transmitter on the HCUR L board, fed by
+OPTION ON from the HPRO board and having outputs
labeled DEMAND af"!d DEMAND RTN, is not used in
normal current loop operation. These components are
provided only for use in a special 1610, part no. 23940-XX.
2.9.4
Refer to Figure 2-34. EIA data to be transmitted (-XM IT
DATA) is applied to a 75154 voltage converter. A "Mark"
condition on -XM IT DATA is seen as a level of approximately -7 Volts. This is "inverted" by the 75154 to a +5
Volt level, wh ich is again inverted to light LED 1, and
double-inverted to turn off LED2. This causes phototransistor A to turn on and B to turn off, which allows
transistor C to turn on, thus "closing the switch" in the
current loop.
Current Loop Operation
There are basically four different current loop configurations in which the HCU R L board can be used. (The only
difference between the 20 mA and 60 rnA active circuits is
in the value of the resistor used in the current generator;
these two will be discussed together under the "active"
headings.) The four types are as follows:
Full-duplex, passive
Full-duplex, active
Half-duplex, passive
Half-duplex, active
When a "Space" is received from the HPRO board (+7
Volts), the 75154 inverts this to a 0 Volt level, turning off
phototransistor A and turning on phototransistor B, which
turns off transistor C, opening the current loop.
In the following paragraphs, each of these will be
discussed individually. In the accompanying illustrations,
the receiver circuit is shown as an LED, and the transmitter
circuit is shown as a transistor. Bear in mind that these
symbols represent the complete circuits, discussed in 2.9.2
and 2.9.3.
Like the receiver circuit, the transmitter's connections to
the current loop can be made in several different ways,
depending upon the type of current loop network used.
A
c
2
7404
75154
FROM USART
7405
B
-XMIT DATA
496-004
Figure 2-34. Transmitter Circuit
2-34
TRANSMITTER
RECEIVER
6
~
,,
<.
I
("~
-+J
A.
C
FULL-DUPLEX
PASSIVE
*
---.-I
----,
--=-
B.
FULL -DUPLEX
ACTIVE
r-------,
I CURRENT
SOURCE
I
I
r-------------,
r---------~v"yr_t>
y.....
I
"~__
~
I
I.....L I
I
-:- I
I
I
L---C---..J
.
I
I
I
HALF-DUPLEX
PASSIVE
I
I
*~
LI~
_ _ _ -.J
...
)
r--------------------------,
I
~~
L __ ~
D.
HALF -DUPLEX
ACTIVE
496-005
Figure 2-35. Current Loop Operation
2-35
2.9.4.1
FULL-DUPLEX, PASSIVE
Second, when a device is transmitting, its own receiver
also sees the data being transmitted. Thus, when the
HCUR L board is transmitting, the data is also being seen by
the HCU R L receiver, which echoes the data back to the
USART. This data is -automatically printed by the HyTerm
as though it were normal received data. Therefore, the
DUPLEX switch on the control panel must be in the FULL
position during current loop operation. If it is in the HALF
position, it will cause all transmitted data to be printed
twice: once as a result of normal HyTerm half-duplex
operation, in which all transmitted data is printed, and once
as a resu It of "receiving" the same data after it is
transmitted.
See Figure 2-35a. Two independent external current
sources are used. One, switched on and off by the external
transmitter, drives the HCUR L receiver circuit. The other
drives the external receiver circuit, as controlled by the
HCU R L transm itter circu it.
2.9.4.2
FULL-DUPLEX, ACTIVE
See Figure 2-35b. Again two separate current generators
are used, but this time they are located on the HCUR L
board. The external transmitter still controls current flow
through the HCUR L receiver, and the HCU R L transmitter
controls current flow through the external receiver.
HCU R L board patching is altered (from the passive
configuration) to provide a return path for the current.
2.9.4.3
2.9.4.4
HALF-DUPLEX, ACTIVE
This is similar to passive half-duplex operation, except
that the current generator is located on the HCU R L board,
and the HCU R L jumpers are changed to provide a complete
loop for the current. See Figure 2-35d.
HALF-DUPLEX, PASSIVE
In half-duplex, only one current generator is used, and
a" current flows through both the receiver and the
transmitter in series. See Figure 2-35c.
2.9.5
There are two important factors to remember in
half-duplex operation. First, when one transmitter is
transmitting, the other transmitter must remain "on" to
allow current to flow in the loop. This is easily reconcilable,
since the "idle" condition of the line is the "Mark" state
(current flowing), and whenever a transmitter stops sending, it returns to the mark condition. Thus, if neither device
is sending, current is flowing in the loop.
Power Supplies
Power is provided to the HCUR L board through the
edge connector (+5V, +15V, and -15V). A pair of 3terminal IC voltage regulators is used to convert the 15-volt
supplies to ±12 volts, needed for the level converters to
drive the E IA interface. The +12-volt supply is also used to
drive the current generator(s) when the HCU R L board is
used in the active configuration.
1. Function keys with individual signal outputs routed to
the edge con nector.
5. Key 33 is a shift lock key.
2. Alternate mounting pads allow key positions 16, 31, &
46 to be mounted as shown by dotted line.
6. Positions which may be populated with repeat type
keys_
3. Keys 32 & 47 have their outputs connected together and
routed to the connector.
7. Positions which have pads in circuit board and power/
ground traces connected, but no signal traces.
4. Keys 49 & 60 have their outputs connected together and
routed to the con nectar.
Figure 2-36. Key Positions of Hall-Effect and Saturable-Core Keyboards
2-36
2.10 KEYBOARD
Hall-effect key switches, MOS encoding, and n-key rollover.
Refer to the block diagram in Figure 2-37. Each alphameric
key depressed provides a pulse simultaneously on 2 of the
13 code Iines going into the MOS decoder/encoder. This
chip performs several functions: it transforms this 2-of-13
code into the proper 7-bit key position code, it keeps track
of the sequence in which keys are operated (n-key rollover),
it provides latches for the output data, and it develops an
output strobe signal. Each 7-bit position code is loaded into
the output latches, which develop the -DATA 0-6 signals.
+KYSTB is then developed, which is 10 to 100 microseconds (nominally 50 microseconds) in length. The
-DATA 0-6 signals are levels, which change only when
replaced by the next code.
Either of two types of keyboards may be used in the
1620, one employing Hall-effect keyswitches (M icroswitch)
and one employing saturable-core keyswitches (Cortron).
The external appearance and the interface characteristics of
both keyboards are very similar, but the internal operation
is substantially different.
The 7-bit code produced by the keyboard is the binary
representation of the relative key position. This code is
then converted to the corresponding ASCII code by the
term inal microprocessor program: it uses the position code
as part of a memory address, and reads the ASCII code
from ROM.
The 2-of-13 code and the binary position code produced
by a key in each possible keyboard position are listed in
Table 2-4. Note that the binary value of the position code is
not a direct indicator of key position; it is simply a unique
code used as an address by the terminal microprocessor.
Key positions are illustrated in Figure 2-36. Not all
positions are used. Positions used by each of the different
types of keyboards are noted in the keyboard layouts in the
Product Description manual.
Function key output is not encoded - instead, each key
has its output brought out to the connector separately. All
function keys produce low-level signals when depressed.
2.10.1 H a II-Effect
23897)
Keyboard
(Schematic
2.10.1.1
KEY ENCODING
Each individual keyswitch contains an integrated circuit
chip which is sensitive to a magnetic field set up by magnets
mounted on the keystem plunger. When the key is
actuated, the magnetic field around the chip is altered, and
the IC produces a short negative pulse.
No.
The basic construction and operation of all Hall-effect
keyboards is the same, even though the key complement
and layout may vary. The keyboard features solid-state
This pu Ise is routed, via the circuit board, to two of the
in puts of the large MOS decoder/encoder. Note that the
CONTROL
KEYS
SHIFT IlOCK
______~ ___~ -FKY 4
---------- ---- -- - - - - - - - - - - - - -FKY 5
eiRt.
,-
-
--
GEN
+KYSTB
ALPHAMERIC
KEYS
2-0F-13
KEY
ENCODING
DRIVER
2-0F-13
(13)
TO
BINARY
lATCH
ENCODER
NUMERIC
L _ _ _ _ _ _ _ _ _ _ _ _ _ _ -'
KEYS
Figure 2-37. Block Diagram Hall-Effect Keyboard
2-37
-KYDT
0-6
it into the proper 7-bit key position code. This position
code is loaded into the 7-bit output latch, and then the
strobe is developed.
2-of-13 encoding is accompl ished on the circuit board: the
position of the keyswitch on the board determ ines which
two of the 13 inputs to the MOS integrated circuit will be
activated.
The 7-bit code set into the output latches remains there
until it is replaced by another code. Thus, if no key has
been operated for quite some time, the output latches still
reflect the code corresponding to the last key actuated.
All keys in the numeric section of the keyboard and all
keys in the alphameric section except the CTR L, SH 1FT
and LOCK keys are coded in this manner. The function
keys operate in a similar manner, but their outputs are
levels, and are brought directly out to the connector. The
CTRL and SHIFT/LOCK key outputs are not encoded:
instead, they go through the interface connector to the
terminal microprocessor on the HPRO circuit board.
2.10.1.3 STROBE GENERATION
2.10.1.2 MOS DECODER/ENCODER
The +KYSTB signal is generated by a special integrated
circuit which has two modes of operation, one for normal
action and another for repeat-type keys.
The MOS chip receives the pulsed 2-of-13 codes from
the various keys, decodes the 2-of-13 code, and re-encodes
2.10.1.3.1 Normal Action. For normal operation, the
enable input (pin 5) is low, and the output appears
Table 2-4. Key Position Encoding (Half-Effectand Saturable-Core Keyboards)
Pos.
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Input
Pair*
3,6
2,8
2,9
2,10
2,11
2,12
2,13
3,4
1,3
3,5
2,7
1,4
1,5
1,6
1,7
3,8
3,9
3,10
3,11
3,12
3,13
4,5
4,6
4,7
4,8
4,9
4,10
1,2
1,8
Output
Code
6543210
Pos.
No.
Not Used
0001100
0000011
0000100
0000101
0000110
0000111
0001000
0001001
0001010
0001011
0000010
0001101
0001110
0001111
0010000
Not Used
0010010
0010011
0010100
0010101
0010110
0010111
0011000
0011001
0011010
0011011
0011100
0011101
0000001
0011111
Control
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Input
Pair
4,12
4,13
5,6
5,7
5,8
5,9
5,10
5,11
5,12
5,13
2,4
1,10
1,11
6,7
1,12
6,8
6,9
6,10
6,11
6,12
6,13
1,13
7,8
2,3
1,9
7,10
*Numbers refer to pin numbers of MOS integrated circuit.
2-38
Output
Code
6543210
Lock
0100000
0100001
0100010
0100011
01 00100
0100101
0100110
0100111
0101000
0101001
0111001
0101011
0101100
Control
Not Used
Shift
0101101
0101110
0101111
0110000
0110001
0110010
0110011
0110100
0110101
0110110
Shift
Not Used
0111000
0101010
0111010
Pos.
No.
Input
Pair
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
7,11
7,12
7,13
8,9
8,10
8,11
8,12
8,13
9,10
9,11
9,12
2,5
2,6
9,13
10,11
10,13
11,13
12,13
10,12
11,12
7,9
3,7
4,11
Output
Code
6543210
0111011
0111100
0111101
0111110
0111111
1000000
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001001
1001010
1001011
Break
1001100
1001101
Local
1001110
0110111
UC Only
Not Used
0010001
0011110
Not Used
Not Used
Not Used
Not Used
essentially the same as the strobe input. When keys are
operated in more rapid succession, the n-key rollover is
accomplished by shortening the length of +KYSTB. This
results in presenting characters to the HPRO board more
rapidly than before, but still not faster than they can be
handled by the terminal microprocessor. The speed at
which the microprocessor operates is so much faster than
the fastest possible keyboard entry that no useful data is
ever lost.
2.10.1.5
All keyboard interface signals use TTL levels. Keyboard
output signals are normally high, and go low when
activated. The +KYSTB signal latches the position code
into the input port on the HPRO board on its trailing
(positive-going) edge.
2.10.2 Saturable-Core Keyboard (Schematic No.
400512-01
2.10.1.3.2 Repeat Keys. Two qualifications are necessary to provide repeat action (repeat strobes) for a key.
First, a special keyswitch module must be installed, and,
second, the module's no. 1 output must be connected to
pin 1 or pin 2 of the MOS encoder/decoder. Also connected
to these pins is a voltage level sensing circuit, the output of
which drives the Enable input of the pulse generator IC.
The basic construction and operation of all keyboards
using the saturable-core keyswitches is the same, although
keyswitch complement and layout and key top engraving
may vary. In addition to the contactless, ferrite core
keyswitches, the keyboard features MOS encoding and
n-key rollover.
When a repeat-type key is depressed, the initial strobe is
produced in the same manner as a normal strobe. However,
if the key is held down, its output that is connected to
pin 1 or pin 2 of the MOS encoder/decoder does not return
all the way to +5 volts, but instead rises to only +4.1 volts.
This drives the enable input of the special IC high, and
allows it to generate repetitive strobe pulses at a rate of
approximately 20 per second. Representative waveforms
are shown in Figure 2-38.
2.10.2.1
The outputs of the seven latches and the strobe output
are applied to 7404 hex inverters to provide the standard
TTL drive current necessary. Function key output is direct
from the keyswitch to the terminal microprocessor input
ports, with no intermediate drivers.
KEYSWITCH
OUTPUT
REPEAT
KYSTB
lO-lOOus
BASIC OPERATION
This is a scanning keyboard. The Encoder/Decoder/
Processor electronically scans all keyswitches several times
per second to see if they are up or down. When a key's
status changes from, "up" to "down," the Encoder/
Decoder/Processor outputs a code, representing the key's
relative position, onto the data lines, and develops a strobe
pulse (+KYSTB). Function key status is loaded into a latch
so that "Ievel" signals are available at all times.
2.10.1.4 OUTPUT DRIVERS
NORMAL
LOGIC LEVELS
Refer to the block diagram in Figure 2-39. An oscillator
drives the MOS Encoder/Decoder/Processor with 12.2 IlS
square waves. This processor sends a different address to
the Addressing Logic about every 501ls.
lJ
f[j
u
lflJ
~300~50ms~
--I
U U U
~
~
Figure 2-38. Keyboard Strobe Generation
2-39
~ 50 ±10
ms
2.10.2.3 ENCODER/DECODER/PROCESSOR
The keyswitches are arranged electrically in an 8 x 16
matrix, providing up to 128 possible key positions. The
addressing logic sends a drive pulse down two wires, which
intersect at only one keyswitch. If the switch is not
depressed, noth ing else happens, but if the key is depressed,
a signal appears on the sense line. This signal is amplified to
become Shift Register IN, SR IN, which is returned to the
Encoder/Decoder/Processor to inform it that the key
addressed by its present address is down. The decoder
portion outputs the position code for this key onto the
data bus, and the Strobe Logic develops a pulse on
+KYSTB.
This integrated circuit is actually a special-purpose
microprocessor. It can be logically divided into the following sections:
(a)
(b)
(c)
2.10.2.3.1 Timing Section. The input to the timing
section is a train of 12.2/1s square waves from the
oscillator. From this, the timing section generates the main
clock signal train which drives the Count Register Section
and generates clock phases 1, 2, and 3. 1 is the
interrogation enable signal. 2 (used internally only) loads
the data into the data latch and generates the strobe. 3 is
used by the external electronics for various "housekeeping"
functions. A 4 signal is also generated externally.
On each scan the position of all function keys is set into
a latch, providing level outputs for the five FKY signals.
2.10.2.2
Tim ing Section
Count Register Section
Data and Strobe Section
KEYSWITCH
The keyswitch is a linear saturable ferrite core with two
preformed wires snapped through it. One wire, called the
2.10.2.3.2 Scanning Counter. The scanning counter is a
7-bit binary counter which provides the address for the
external pROM, part of the addressing logic.
drive wire, is periodically driven by a current pulse. The
response to the drive pulse appears, through transformer
action, on the second wire called the sense wire. This core
modu Ie assembly is snapped into the switch housing
together with. the plu nger and return spring. A pair of
magnets are located on the plu nger so that in the
undepressed position the magnets are saturating the core.
With the core satu rated, signals on the drive wire are not
coupled to the sense wire. As the plunger is depressed, the
magnets clear the core, bringing it out of saturation and
allowing the drive signals to be coupled to the sense wire.
These sense signals are amplified to become the SR I N
signal.
2.10.2.3.3 Data/Strobe Section. This section comprises a
7-bit data latch and a 128-bit shift register. After each key
is interrogated, a bit in the shift register cor.responding to
the key's position on the keyboard is either set or reset,
depending upon the keyswitch's status. As each key is
interrogated, its status in relation to its status during the
previous scan is determined by comparing it with the shift
register output. Only when a key's status changes from
"up" to "down" will the output latch be loaded (at 1) and
a strobe generated.
SRIN
KEYSWITCH
MATRIX
ENCDRI
DCORI
PROC
r---t~
ADDRESS
FUNCTION
LOGIC
KEY
LOGIC
...-----1.
- FKY 1
1
-FKY 5
STROBE
LOGIC
~--------------------------~~ +KYSTB
-BO
DATA
f
-B6
333-002
Figure 2-39. Block Diagram, Saturable-Core Keyboard
2-40
2.10.2.4 ADDRESS LOGIC
the early part of the interrogation cycle +¢4 is low,
allowing the low-order 128 bytes of the pRO~ to be
addressed. The pROM output is loaded into the 4-bit latch
when +cp3 goes low, and at the next transition of +CLK,
+cp4 goes high, allowing the high-order 128 bytes of the
pROM to be addressed.
The address logic is made up of a pROM, a 4-bit latch,
and three binary-to-decimal decoders.
The pROM is a 256 x 4-bit array, but is used as a 128 x
8-bit array. This is accomplished by addressing one of the
low-order 128 bytes (4 bits) first and storing the output in
the latch. Then the corresponding byte in the high-order
128 bytes is addressed and the output is used directly. At
the moment of key interrogation (¢1), the latch outputs are
applied to the "X" (sense line) decoder, and the pROM
outputs address the "Y" (drive line) decoders. The fourth
bit of the latch is used to select one of the two "Y"
decoders. The fourth bit of the pROM output (again, at the
moment of interrogation) is used to flag "repeat" keys.
The keyswitch matrix sense lines, also referred to as the
"X" lines, are continuously driven by the output of the
latch. However, to interrogate a particular keyswitch, one
of the drive lines, also referred to as the "Y" lines, must
also be driven low. The pROM output is applied to both
"Y" decoders, and at cp1 time one of these decoders
(determined by bit no. 1 of the latch) is enabled, causing
one of the sixteen drive lines to go low. With one sense line
(X) and one drive line (Y) low, one particular key is
interrogated.
Refer to the schematic and to Figure 2-40. Note that the
low-order seven bits of the pROM are addressed by the
Encoder/Decoder/Processor (the scanning counter). During
KEY
+
elK
+
~1
At the end of cp4 time, the Encoder/Decoder/Processor
increments the 7-bit address, thus addressing the next
INTERROGATE
NEXT KEY
INTERROGATION
+ ~2
+
~3
+ ~4
ADDRESS
PROM
-
CLOCK PROM
OUTPUT INTO
ADDR REG
ADDRESS
PROM
+ A7
A7
+
~
SRIN
+
KYSTB
-
A7
ADDRESS "X" LINES
DRIVE ONE SENSE LINE
ADDRESS "Y"
LINES ENABLE
INTRGTN
+
ADDRESS
PROM
INCREMENT ADDR
FOR NEXT KEY
J
1///
t
333-003
Figure 2-40. Timing Cycle, Cortron Keyboard
2-41
location in the pROM and enabling the interrogation of a
different key. A new key is interrogated approximately
once every 50ps.
The SRO output from the Encoder/Decoder/Processor
provides hysteresis by controlling the transistor at U2-1, 2,
and 3. For example, if a given keyswitch had been
depressed on the previous scan, +SRO would be high on the
present scan, driving U2-3 lower. This would require a
relatively lower signal on U 2-4 to provide an output at TPB
and +SR IN. On the other hand, after the key has been
released and +SRO remains low, U2-3 is slightly higher,
requ iring a relatively higher signal on U2-4 to trigger the
transistor. This hysteresis, plus the fact that the amplitude
of the signal on TPA and U2-4 is a function of how far the
key is depressed (how close the magnet is to the core),
provide effective debouncing in both directions of keyswitch travel.
When a key is detected as having been depressed, the
code placed on the output bit lines by the Encoder/
Decoder/Processor is the same as the 7-bit address used to
address the pROM (a position code).Thus encoding of keys
is accomplished in the pROM: addresses and output
codes are incremented sequentially, but keyswitches are
actually interrogated as addressed by the pROM. The
scanning sequence can jump from key to key in random
fash ion, but the codes produced by the keyboard on any
one scan will be incremental, with the lowest binary value
first.
2.10.2.5
2.10.2.7 STROBE LOGIC
KEYSWITCH MATRIX
The normal strobe logic is simple and straightforward;
the repeat strobe logic is somewhat more complex. The
Encoder/Decoder/Processor produces a low active pulse on
its STB output at <1>2 time whenever a key's status changes
from "up" to "down" (see 2.10.2.3). This signal enables
the KYSTB flip-flop, which then sets at the end of <1>1 time,
driving the +KYSTg signal low. At the end of <1>3 time, the
flip-flop is cleared and +KYSTB returns high. (The HPRO
logic uses the trailing edge of the +KYSTB pulse.)
All keyswitches are arranged electrically into an 8 x 16
matrix. There are eight sense (X) lines and 16 drive (Y)
lines. Each sense line passes through a maximum of 16
keyswitch cores, and each drive line through a maximum of
8 cores. (Not all 128 possible keyswitch locations are
populated. )
All matrix lines are driven by the same type of ICs,
74145 binary-to-decimal decoders. The X decoder is always
enabled (binary 8 input low), so one of its outputs is always
low. The Y decoder is enabled by +1, when one of the 16
lines is driven low; at -<1>1 time, all outputs are high.
The balance of the strobe logic is used for repeat key
timing. When a key is depressed and held down, the first
strobe is generated in the usual manner. Then, after an
initial delay of about .3 second, +KYSTB pulses are
generated at the rate of about 20 per second.
All sense lines are term inated in an 8-legged AN D gate.
This AN D gate is normally not satisfied, since one of its
inputs is low. Only when a Y line is driven low, and the
keyswitch at the intersection of the enabled Y line and the
enabled X line is depressed, will the signal on the Y line be
coupled to the X line, and the X line will go high to satisfy
the AN D gate.
When a repeat key is addressed, output 04 of the pROM
(pin 9) goes high, and if the key is depressed, this output
ANDed with +SRIN presets both U20 flip-flops. When
U20-9 sets, the preset clamp is removed from U 19-4, and
the clamp circuit holding the two counter ICs, U21 and
U22 clear, is disabled. Counter U22, a binary counter, is
incremented at the end of each scan, and it increments
counter U21 after every eight scans. U21 is a divide-by-six
counter, so its OD output rises after six input pulses, and
sets U 19-9. The next +<1>1 sets the KYSTB flip-flop and
generates a pulse on +KYSTB. Thus:
At first glance it might seem that this coupling would
simply drive the X line more negative. However, by passing
the X and Y lines through each keyswitch core in opposite
directions, the "low" on the X line is cancelled, instead of
being aided. This allows the large AND gate to be satisfied
momentarily, producing a positive spike at Test Point A
(TPA),
6.25 ms/scan x 8 x 6
=
300 ms
which is the initial delay after the "normal" strobe and
before the first repeat strobe. When +KYSTB is developed,
both counters are reset to 0 through gate U18-8.
2.10.2.6 SENSE AMPLIFIER
The input signal at TPA, Figure 2-41, is amplified by the
transistor at U2-3, 4, and 5 to produce a TTL compatible
After the initial strobe, with U19-9 set, a +KYSTB pulse
is generated every eight scans: the QA output of U21 is
ANDed with U19-9 to set the KYSTB flip-flop. The
+KYSTB pulse clears both counters, and the process is
repeated as long as the key is held down. Repeat strobes are
generated at the rate of approximately one every 50ms
(6.25 ms/scan x 8 scans),
signal at TPB, also shown in Figure 2-41. This signal is gated
with 1 to set the keyswitch latch and produce the Shift
Register IN signal, + SRIN. This signal is returned to the
Encoder/Decoder/Processor, where it causes the corresponding bit in the 128-bit shift register to become set.
2-42
TPA
OV.
TPB
OV.
Figure 2-41. Sense Amplifier TPA and TPB
2.10.2.8
While A6 and A7 (U5) are high, a low is applied to the
input to the Encoder/Decoder/Processor, thus disabling any
STB output.
FUNCTION KEY LOGIC
Throughout the scan cycle, the status of each key
(SR IN) is shifted into Shift Register U 11. During all but the
very end of the scan cycle, this information is not used.
However, when A6 and A7 (U5) are both high during the
later portion of the scan cycle, the decoded pROM (U 7)
outputs address the functi on keys, wh ich are the last eight
keys interrogated (five function keys and three unused
positions). At the very end of the scan cycle, when A7 goes
low, the contents of U 11 are loaded into U 12, which
provides level outputs.
2.11
CONTROL PANEL
Both the Model 1610 (RO) and 1620 (KSR) use the
same control panel assembly. However, there are different
versions of the assembly, which may be found on any
HyTerm. The major difference is in the POWER switch; it is
mounted on the control panel on some units, and it is
mounted on the bottom cover on others. The control panel
that does not include the POWER switch does include a
volume control for the audible alarm.
2-43
PRIMARY
AC
_
---I
~
/'"
V/'
REFERENCED
TO
COMMON
'r
RETURN
0
OUTPUT
CIRCUIT REFERENCED TO SIGNAL
GROUND ~
F1
INPUT,
CURRENTH
RFI
~FUll-WAVE~ ~
FI~LTER
n RECTIFIER
LIMITING
'J
1R~E
S~ITCH
EVE
LOCAL
+15V
SUPPLY
SWITCHING
REGULATOR
AMPLIFIER
BIAS
~
LC
FIL TER
K
+
+ 15V
~
FEEDBACK
.----41 RECT~FIER I
I ~ FILTER
SPIKE
CATCHER
I
/f"
- FEEDBACK -----
POWER
INVERTERH
INVE,RTER
DRIVE
SWITCH TRANS-
i
E
j
: FORMER
•
+ 5V
RECT~FIERr-1---41ep------f----
+ 15 VOL T OUTPUT
+5VOlT OUTPUT
FILTER
I'.)
~
~
e
INVERTER
I CUR RENT ...
k' ____----J
LIMITING
I
1\
I
II
-15V
~ REC~FIER
-=
FIL TER
e
.....v
1L1--_______--1 + 5V
ERROR
ISOLATOR~
AMPLIFIER
OPTO -
.I
.
I
Figure 2-42. Block Diagram, Boschert Power Supply
-15VOl T OUTPUT
2. 11.1
Switches
63 Hz. An AC line fuse is located inside the machine at the
right, and is accessible by removing the access cover. The
POWER switch is at the right side of the control panel.
There are three regulated output voltages:
The wiring of all switches except the POWER switch is
shown on the control panel schematic, no. 23708 for
control panels with the attached POWER switch, and
no. 23710 for units with the volume control. (POWER
switch wiring is shown on the power distribution schematic,
no. 23859.) The wipers of all switches are connected to
GND, and the NO/NC contacts that are used are connected
to +5 volts through a resistor on the HPRO board. Thus all
outputs appear high to the input ports on the HPRO board
until the respective switch is operated. (Note that the
CLEAR switch output, -R ESET, does not go to an input
port, but drives the 8224 Clock Generator IC directly.)
2.11.2
+5V @ 4A (8A surge)
+15V @4A (10A surge)
-15V @ 4A (10A surge)
Foldback current limiting is provided on all output
voltages (11A±2A for 5V, 13A±2A for 15V) as well as on
the inverter primary. Overvoltage protection takes over
when the +5 volt output reaches approximately 5.6 volts.
The primary circuit, which may generate switching transients, is electrically isolated from the secondary (output)
circuit.
Form Length Switch
The power supply operates on the principle of switching
regulation, using a power transistor as a pulse-widthmodulated switch, controlled by a negative feedback loop
from the output circuit. AC line voltage is rectified,
chopped, smoothed, inverted at 20 kHz, then finally
rectified for output to the term inal circuits. Operation at
this frequency, rather than at 60 Hz, perm its the use of
much smaller, lighter transformers and inductors that
dissipate far less heat.
The 12 outputs of the FORM LENGTH switch are
encoded into binary format to reduce the number of input
lines to the terminal microprocessor. A priority encoder IC
is utilized, but there is no priority involved; only one input
to the priority encoder is active at anyone time.
2. 11.3
Audi ble Alarm
The audible alarm is mounted on the control panel
circuit board. It is driven by a peripheral driver IC when the
-BELL signal is brought low by the terminal microprocessor. The other side of the audible alarm is returned to
+12 volts_ When the volume control is used, it is connected
between the audible alarm and +12 volts.
2.11.4
2.12.1.1
GENERAL DESCRIPTION
Refer to the block diagram, Figure 2-42 and the
schematic diagram, Drawing No. 26021-xx in the
Schematics/Reference Section of th is manual. A therm istor
in the power supply input line limits power-up inrush of
current to charge a large capacitor in the rectifier circuit.
An input radio frequency interference (RFI) filter prevents
switching transients generated by the power supply from
being reflected back onto the AC line. A full-wave bridge
rectifier produces approximately 100 volts DC. A portion
of the rectifier output is tapped off through a resistance
network to supply a local 15-volt regulated power supply
that furnishes power to the primary circuit. An internal
Indicators
There are two LED indicators mounted on the control
panel circuit board. The POWER indicator is lit whenever
the +5 volt supply is energized. The ERROR indicator
lights when -ERROR is driven low by the terminal
mi croprocessor.
fuse at the output of the rectifier protects it from
catastroph ic failure of circu it elements in the primary. Raw
DC from the rectifier is applied to a power transistor driven
at 20 kHz by a switching regulator amplifier. Chopped DC
from the power switch is smoothed in an L/C filter network.
A positive feedback loop from the filter to the switch driver
maintains self-oscillation. Voltage regulation is imposed by
a negative feedback loop from the output circu it. The duty
cycle of the power switch is varied in response to the
feedback signal, providing more "on" time to increase the
average voltage from the LlC filter, less "on" time to
decrease the average voltage. Current limiting signals from
both the primary circuit and the output circu it are fed back
through this same loop.
2.12 POWER SUPPLY
Either of two types of power supplies may be used on
the 1610/1620; one is the Boschert and the other is the
LHR. Both operate on the principle of switching regulation,
using a power transistor/control module assembly as a
pulse-width-modulated switch/chopper converter.
2.12.1 Boschert Power Supply Part No. 26021-XX
(See Figure 2-42)
The regu lated power supply is provided in either of two
input voltages, 115 or 220 volts. Variation of input voltage
can be ±15% for either supply. Line frequency can be 47 to
A "spike catcher" between the L/C filter and the
inverter switch suppresses large transients that may be
2-45
generated if conduction of the two transistors in the
inverter switch overlaps. The inverter switch is two power
transistors that are driven at 20 kHz, conducting alternately. The output of the inverter switch is fed to the
transformer. Current is fed to each half of the transformer
primary alternately in opposite directions. The inverter
operates on a 50% duty cycle, producing square waves.
CAUTION
When troubleshooting the primary side of
the power supply under power, do not use
test instruments having a third-wire ground,
or damage to the instrument will result.
Make measurements between circuit elements and the primary circuit common
return, NOT ground.
Each output voltage has its own full-wave rectifier and
filter circuit. A coil in the toroidal transformer of each
output is used to sense current in the circuit. This inductive
coupling to the output current limiting circuit serves to
isolate the output voltages from the primary side of the
power supply, while establishing a feedback loop to the
switch ing regu lator ampl ifier. If current in any output tends
to rise excessively, the negative feedback signal causes the
switching regulator to decrease the "on" time of the power
switch, reducing the average voltage applied to the inverter
switch, which resu Its in a reduction of the current through
the transformer. The +5 volt output is compared to a
reference Voltage, and the difference is amplified and
applied to the switching regulator amplifier via an optoisolator, which isolates the output circu it from the primary
circu it. The error signal is used to modify the duty cycle of
the switch regulator in much the same way as in the current
limiting circuit. Coupling between windings in the inverter
transformer makes it possible to regulate all outputs by
monitoring anyone.
2.1.2.1.3 THEORY OF OPERATION
The following paragraphs present a more detailed
description of the operation of the power supply. Refer to
the schematic diagram, No. 26021-xx, in the Schematics/
Reference Section.
2.12.1.4
When AC power is initially applied, electrolytic filter
capacitor C23 demands a high rate of charging current. To
protect the diodes in the rectifier, thermistor RT1 is
inserted in the line. This thermistor has a negative
coefficient of temperature, initially offering a relatively
high resistance, then lowering resistance when current
passing through it raises the temperature. The initial high
resistance limits the charging rate of C23 to a safe level.
When the temperature of RT1 rises, the resistance drops to
a very low value. The AC ripple component from the
rectifier is sufficient to keep the therm istor above the
ambient temperature and at a low resistance.
Overvoltage protection is provided by a silicon controlled rectifier connected across the +15 volt output.
Under normal operating conditions, the SCR presents a
very high resistance, but if the regulating circu it fails and a
preselected limit is exceeded (nominally 5.6 volts on the +5
volt output), the SCR is fired, placing a short across the
+15 volt output. This effectively shorts the entire transformer secondary. Current limiting then takes over automatically to protect the power supply.
2.12.1.2
INPUT CURRENT LIMITING
2.12.1.5
INPUT RFI FI LTER
Switching power supplies tend to generate sharp transients, which can be reflected onto the power line. The
purpose of the RFI filter is to suppress these switching
transients. Inductor L 1, the R F I filter, has two windings
with a common magnetic core. The two windings develop a
higher 0 and provide better filtering of both sides of the
power line than two single inductors.
ISOLATION
2.12.1.6
The primary circu its of the power su pply are electrically
isolated from the secondary, or output circu its. Note from
the schematic diagram that there is no common ground
reference between the primary and secondary circuits.
While outputs are returned to the normal signal ground,
primary circu its are retu rned to a "common return," NOT
GROUND, indicated by a diamond on the schematic (0).
The only interfaces between the primary and secondary
circuits are the inverter transformer (inductive), the output
current limiter (inductive), and the opto-isolator (optical).
FULL-WAVE BRIDGE RECTIFIER
The full-wave rectifier, consisting of diodes CR 1 through
CR4 connected in a bridge configuration, converts the
off-the-line AC directly into DC. Capacitor C23 provides
filtering and storage of the rectified voltage. The cathode of
C23 defines the primary circuit common return. Note that
the rectifier is returned to the primary circuit common
return, NOT to signal ground. Fuse F 1, at the output of the
rectifier, protects the diodes in the event of a catastrophic
failure in the primary circuit. The output of the rectifier is
then applied to the power switch, 01, and to the local +15
volt power supply via a resistor-network.
WARNING
2.12.1.7
Hazardous voltages are present in the primary circu it.
LOCAL +15 VOLT POWER SUPPLY
Transistors 05 and 06 are the basic components of the
local +15 volt regu lated power supply that powers the
2-46
switching regulator amplifier IC, Ul. Zener diode VRl and
resistors R 12, R 13, and R 14 provide a reference voltage
that is compared by 05 to the sampled voltage. The error
signal developed is used to control 06, the series-pass
element, producing the required regulation.
2.12.1.8 POWER SWITCH
LATOR AMPLIFIER
transistor. Diode CR lOis polarized to damp production of
counter emf's in L3 should transients occur in the inverter.
2.12.1.11
The smoothed DC input is chopped at 20 kHz by the
two power transistors, 010 and 011, which conduct
alternately, feeding current to the two halves of the
non-saturating output transformer T1 in opposite directions. Supporting circu itry consists of a saturating transformer, T2, diodes CRll through CR15, resistors R29
through R32, and capacitor C12. The transformer is a
self-excited type.
AND SWITCHING REGU-
Power transistor 01, the power switch, is controlled by
Type 723 switching regulator amplifier Ul, an integrated
circuit voltage regulator, through a chain of power-boosting
transistors. The switching signal generated within the IC at
approximately 20 kHz turns the power switch on and off.
Regulation is effected by modifying the duty cycle of the
switch in response to feedback signals from the +5 volt
output. Low output voltage results in increasing "on" time;
high output causes a reduction in "on" time. Modifying the
duty cyclp. raises or lowers the average voltage delivered to
the inverter.
2.12.1.12
The rectifier for the +15 volt supply is made up of
transformer T6, diodes CR17 and CR22, and capacitors
C35 and C38. Inductor L4 and capacitor C18 provide
filtering. The -15 volt supply uses transformer T5, diodes
CR18 and CR21, and capacitors C36 and C37. Filtering is
provided by inductor L6 and capacitor C20. The +5 volt
filter is a pi type consisting of inductor L5 and capacitors
C19 and C25. R54 is the +5 volt bleeder resistor. Filter
capacitors C32 and C33, and bleeder resistor R51 are
connected between the +15 and -15 volt outputs.
~.12.1.13
+5 VOLT ERROR AMPLIFIER
The +5 volt output is sampled by a voltage divider,
resistors R43 and R44, and applied to the non-inverting
input of Type 723 voltage regulator IC U2 via resistor R41.
The adjustable reference voltage is derived from potentiometer R40 and applied to the inverting input of the voltage
regulator via resistors R39 and R38. The two voltages are
compared with in U2, and the difference is applied to the
opto-isolator, U3. Only the +5 volt output is adjustable and
regulated. The close electro-magnetic coupling in the
transformer secondary makes it possible to control all
output voltages by controlling anyone.
LCSMOOTHING FILTER
The regulated, pulsed DC is applied to a filter network
made up of inductor L2 and capacitor Cl0. Diode CR6
maintains output current flow during switch "off" periods
by providing a current path to discharge the energy stored
in the magnetic field of the inductor during "on" periods.
CR6 is reverse-biased when the power switch is "on" to
prevent upsetting DC conditions. The smoothed, regulated
DC output of the filter is applied to the inverter via a
"spike catcher" network.
2.12.1.10
DCOUTPUTCIRCUITS
Each output has its own full-wave center-tap rectifier
and low-pass LC filter. In addition, there are two electrolytic filter capacitors across the entire output from +15
volts to -15 volts. There is a bleeder resistor across the
entire output, and one across the +5 volt supply to
discharge the capacitors when power is turned off. The
filters remove the high-frequency ripple com ponent, mostly
40 kHz, from the output voltages.
The output of U 1 is boosted by transistor 07 to drive
complementary Darlington stage 03. 03, a PN P transistor,
in turn drives Darlington-connected 02, the immediate
driver stage of 01, the power switch. The 20 kHz chopped
DC output from the power switch is applied to an LC filter
for smooth ing. The switch output signal is fed back to pin 4
of U 1 v ia inductor L2 and resistors R 27 and R 17 to
maintain self-oscillation. To overcome the effect of charge
storage, reverse emitter-base bias is injected into the power
switch from a secondary winding on inductor L2. The
reverse bias signal is applied v ia a network of resistors R 2,
R3, and R5, capacitor C5, and diode CR5. The phasing of
the secondary of L2 causes a pulse of turn-off bias to be
applied to both 01 and 02 at the termination of the switch
"on" period. Turnoff of the switch becomes regenerative,
and is greatly accelerated.
2.12.1.9
INVERTER
2.12.1.14
OPTO-I SO LATO R
The opto-isolator, U3, consists of a light-emitting diode
(LED) and a phototransistor. The output of the error amplifier is applied to the LED, illuminating it in proportion to
the error. The optical energy is read by the phototransistor,
SP IKE CATCH E R
The purpose of the spike catcher network, inductor L3,
diode CR 10, resistors R29 and R48, and capacitor Cl1, is
to suppress large current spikes that can be generated when
conduction of the two inverter transistors overlaps. This is
not a common occurrence, but can happen during start-up
or during recovery from an overload condition. This
suppression not only reduces RF I radiation, but also
protects the inverter transistors and the power switch
which has no electrical connection to its base. The output
of the phototransistor is fed back through resistor R33 to
the switching regulator amplifier, U1, where the signal is
used to modify the duty cycle of the power switch,
regulating the voltage. Since there is no direct electrical
connection through the Opto-Isolator, and the photo-
2-47
to reduce switch "on" time, reducing the average voltage
applied to the inverter, limiting current through the inverter
transformer. A shorted output will reduce current to a very
low level that can be tolerated indefinitely.
transistor output is returned to the primary circuit common
return, the output circuit is effectively isolated from the
primary.
2.12.1.15 OUTPUT
AMPLIFIER
CURRENT
LIMITING
SENSE
2.12.1.16
Current in a winding of a toroidal transformer in each
output is monitored and fed back to the switching regulator
amplifier to modify the switch duty cycle. Resistor R58 is
connected across a winding of transformer T4 in the +5 volt
circuit. Current through the transformer develops a voltage
drop across the resistor. Transistors 014 and 015 sense and
amplify the voltage drop. In the -15 volt supply, resistor
R59 is across the winding of T5, and transistors 016 and
Q17 are the sense amplifiers. In the +15 volt output, the
circuit elements are transformer T6, resistor R60, and
transistors 018 and 019. The collectors of all the transistors are connected to the base of transistor 013 through
resistor R70. 013 amplifies the error signal, which can
originate in any of the outputs, and applies it to the
switching regulator amplifier along with the voltage regulation feedback signal. As current increases, the duty cycle of
the switch regulator, and of the power switch, is modified
AC
SECTION
OVERVOL TAGE PROTECTION
Overvoltage protection is provided primarily to protect
the loads in the event of failure of the regulating circuit.
Silicon controlled rectifier SCR 1 is connected across the
+15 volt output. The gate circuit ofSCRl monitors the +5
volt output through zener diode VR2, which has a 5.6 volt
breakdown rating. If the +5 volt supply exceeds the zener
breakdown Voltage, the diode conducts, firing SCR2, wh ich
places a direct short across the +15 volt output. In effect,
this "crowbars" all outputs because of the close coupling of
the inverter transformer secondary. To protect the power
supply, the current limiting circuit takes over, reducing the
power switch output to a safe level. Once fired, the SCR
will continue conducting until power is turned off. When
the condition causing the overvolt condition is corrected
and power is applied, the overvolt protect circuit is
automatically restored to normal.
OIP ISOLATION
AC LINE TO DC
,----------------------,
I
TO T9
I
INPUT
AC INPUT
115 OR
230 VAC
I ;--_ _--{
II
RECTIFIE
DOUBLER/
FILTER
I
I
I
I
I
r=-J
I
I
r----==J
I
I
+
I
TO CURRENT
SENSE CKT
I
I
I
I
I
I
I
I
DRIVE
CIRCUIT
I
VDC
REG
O/P
CURRENT SENSE
SIGNAL
I
I
CONTROL
CIRCUIT
I
I
I
I
I
(PULSE WIDTH
MODULATOR)
'--------,.11
I
+5
OUTPUT
LC
FILTER
+
+ SENSE
VOLTAGE
SENSE
SIGNAL
-
24V
SENSE
:
L _____ .....1
UNDERVOL TAGE SENSE
SIGNAL
+
T2
------1
OIP
I
I
PART OF AC
SECTION
+ 15 VDC
UNREG
+ 48
VDC
UNREG
]11
OIP
I
_______ J
I
48 V SECTION ON
TM 41425 ONLY
- 15 VDC
UNREG
O/P
~
•
TO CURRENT
• SENSE CKT
(083 -013)
Figure 2-43.
Block Diagram, LHR Power Supply
2-48
limits under all conditions of the input line and the output
load. The output and all control circuitry are isolated from
the ac input line.
2.12.2 LHR Power Supply, Part No. 400062-01
(See Figure 2-43)
The main output of the Switching Power Supply is a
pUlse-width modulated chopper converter. The ac input is
rectified, doubled and filtered to 300Vdc and then
chopped and transformed to a lower voltage by a halfbridge. This transformer secondary output (consisting of a
quasi-square wave) is rectified and filtered to the final dc
output value.
This power supply has input undervoltage sense, soft
start control, output current lim iting, output overvoltage
protection and crowbar on the +5V. The unregulated ±15V
outputs have current lim iting circuits and overvoltage
clamps.
2.12.2.1 DETAILED
400062-XX)
The output is sensed and the error signal voltage is
amplified and used to control the pulse width of the
chopper, thus regulating the output voltage within narrow
+
DESCRIPTION
(See
Schematic
2.12.2.1.1 Input Filter. The input filter consists of L1,
C1, and C2, that form an R F noise suppression filter. R 1
.,
CR1
r~--
~
CR 2
C3
,.
115 VAC
IS~~A~PI~"""'_I
,
----.
IN
CR3
~-,
-
300VDC
C4
I
CR 4
~
~
~
I
I
____ ..J
I
(083 - 016)
-+I
Figure 2-44. LHR Simplified Input Rectifier/Filter Doubler Section
(115 VAC Input Strapping)
+
.... ---
r
L
CR 2
4
230V
STAPPING
-+I
CR1
---~
230 VAC
IN
-,-
..
..
AUXILIARY
TR ANSFORMER
---~
4
I
I
I
CR3
.---
~
!
,
I
I
C3
I
~
~
I
t
C4
CR4
......-
Figure 2-45. LH R Simplified Input Rectifier/Filter Doubler Section
(230 VAC Input Strapping)
2-49
300VDC
J
(083 -015)
2.12.2.1.5 Control Circuitry. The control module assembly contains a pulse-width-modulator, IC SG3524, (see
Figures 2-48 and 2-49) and provides all the basic control
functions as follows:
and R2 are thermistors with a high resistance at low
temperature. The thermistors limit the input start-up
current. The filter operation, including polarity and current
flow is described by Figures 2-44 and 2-45. The strapping
connections at T2 allow the use of the same assembly for
115 or 230Vac input. R3 and R4 are the bleeder resistors.
1.
2.
3.
2.12.2.1.2
Chopper Section (See Figures 2-46 and
2-47).
Transistors 01 and 02 are alternately turned on
and off at a 20 kHz rate. C7 is a balance capacitor and T3 is
a current sensing transformer. R5 and C8 form a primary
RC snubber to attenuate voltage overshoots. CR7 and CR8
prevent reverse conduction of 01 and 02 during transient
conditions. The switching action of 01 and 02 applies a
quasi-square voltage waveform of 300 volts peak-to-peak to
the primary of T2.
4.
5.
6.
7.
The adjustments on the control module assembly are
factory set, and it should not normally be necessary to
readjust the factory settings.
Table 2-5 defines the voltage/current levels at nominal
line and load conditions.
2.12.2.1.3 Output Rectifier and Filter (See Figure
2-47). The quasi-square voltage waveform is transformed
down by T2. The output is rectified by BR 1 and filtered by
an LC filter, consisting of L2, C15, C30, and C31. Ripple
and RFI are further reduced by C16 and C17. C9 and R25
form a secondary snu bber network.
2.12.1.1.6 Chopper Drivers. Drive to the bridge transistors 01 and 02 is provided by two pair of push-pUll
current source drivers 03, 04, 05, and 06. 04 and 05, bases
are held at a 5.1 V level. 03 and 06 are alternately turned
on by CA and C B. CA and C levels are clamped at 5.7V by
B
CR 19 and CR20 (see Figure 2-47). Transformers T4 and T5
couple drive signals to the base of Oland 04. The snubbers
2.12.2.1.4 I nternal Auxiliary Power Supply. Transformer Tl transforms the 115 or 230Vac line voltage to
supply unregulated +24Vac to the control circuit. CR13,
CR 14, CR 15, and CR 16 form a fu II bridge rectifier and C 10
fi Iters the output.
150 VDC
300 VDC
Voltage Amplifier and Reference
Overvo Itage Protection
Undervoltage Protection
Soft Start
Remote On/Off (not used)
Power Fail
Current Lim it
consists of Ql1, Cl1, R16and C13. Resistors R12and R17
control the drive current.
+
C3
L
+
C4
(083 - 014)
Figure 2-46. LHR Simplified Transistor Chopper (Half-Wave)
2-50
~
25us
~
~
50 uf (20 kHz)
i i-rs-v-I
I
I
I
__
H
J
DEAD BAND
rv 5 us
I
TO . \
I.... VARIABLE
20 uf MAX
P2-2
CB
01
r-j'""--
I f ·
I
I
I
I
I
I
,
I
I
I
I
11.8 V h
;/
1~5vTOLlY
VeE
I
I
VBE
:
I
_ _ -.J
1~
VARIABLE
,.... 20 us
I
~I
SV
~
TO
DEAD BAND
rv 5 us
I:
.
I f-
MAX
:
, I
Q2
I
I
------.v
I
I
I
----------:--I--~------~~
I
I
:~
:
I
VT2
PRIMARY
j150V
IT
I
\.
I
I
I
I
I
~: ~------
VOLTAGE
AT BR 1
CATHODE
OUTPUT
RIPPLE
20-30 MV
P-TO-P
(ON 5V O/P)
TO
(083 - 017)
Figure 2-47. LHR Power Supply Waveforms
2·51
V REF
+ 5V
":"
+5V
TO ALL INTERNAL
CIRCUITRY
OSC
OIP
OSCILLATOR
COMPARATOR
+5V
INV. INPUT
+
SENSE
N.l. INPUT
-
SENSE
9
COMPENSATION
(083 - 018)
GROUND
Figure 2-48. LH R Control Module Block Diagram
COMPARATOR
:~R::p
:_~>V
_ _..
ERROR
__
R.
AMP
OUTPUT
COMPARATOR
OUTPUT
l
_~
L.....
TO
(083 - 019)
Figure 2-49. LHR Control Module Timing Diagram (SG3524)
2-52
Table 2-5. Voltage/Current Levels
Pin
Function
Measurement
Pin
Function
Measurement
P1-1
OVP
2.3V
P2-1
C
Pl-2
Current
Limit
Square Wave,
l.4V Peak
P2-1
CB
See Fig. 2-47
P3-3
Power Fail
3.5-5V dc
Pl-3
Current
Limit
.5-.6Vdc
P2-4
-Sense
0
Pl-4
Remote
On/Off
1-4Vdc
P2-5
OSC out
See Fig. 2-47
P2-6
UVS
12-1SVdc
+Sense
Divider
2.2-2.8V dc
Pl-5
Pl-6
+24V Input
22-25Vdc
P2-7
RT
Pl-7
Current
Lim Bias
.5-.7Vdc
P2-S
Common
A
See Fig. 2-47
0
Note: All measurements are made with respect to pins P2-4 or P2-S.
overshoot. T7, R30, and CR26 through CR29 are part of
the +15V current limit circuit.
2.12.1.1.7 The +5V Main Output Crowbar. Components
CR34, R29, R28 and SCR 1 form an overvoltage crowbar
circuit. If the +5V regulated output goes above 6.3V, the
SCR 1 fires and keeps the output low. The power supply
must be tu rned off to re-start after the overvoltage
condition has been removed.
2.12.1.1.10 The ±15V Overvoltage Limit. The+15Vand
the -15V overvoltage limit circuits are identical. Only the
+15V circuit will be described. Components R36, CR35,
CR36, and R37 are a biasing network to turn on Q7, when
the output voltage is greater than 17 volts. The circuit
limits the no load output voltage to 17 volts.
2.12.1.1.8 Secondary Current L.imiting Circuitry. Transformer T6, R27, and CR22 through CR25 are part of the
secondary current limit circuit.
2.12.1.1.11
The +48V Unregulated Output. (Not used in
1610/1620.) The primary of transformer T9 is paralled
with the primary of transformer T2. The quasi-square
voltage waveform is transformed down by T9, rectified by
BR4 and filtered by L5 and C27. R 34 preloads the output
to help limit the no load voltage. The +48 volt output does
not have current I im it.
2.12.1.1.9 The ±15V Unregulated Outputs. The +15V
and the -15V unregu lated circuits are identical. Only the
+15V unregulated circuit will be described. The quasi-square
voltage waveform is transformed down by T2, rectified by
B R2 and filtered by L3 and C20. C21 is an R F I suppression
capacitor. R31 and C29 form an RC snubber to suppress
2-53
SECTION 3
MAINTENANCE
3.1
INTRODUCTION
(5)
Maintenance of the HyTerm is generally divided into
two broad categories: (1) module/subassembly removal,
replacement, and adjustments; and (2) detailed troubleshooting
shooting
before it
between
areas.
and repair of circu it boards. Since some troubleis also involved in locating the faulty module
can be replaced, there is no clear-cut dividing line
these categories, and overlap will occur in many
When tipping the HyTerm up to gain access to its
underside, first position the power cord and the E IA
cable to the sides so they wi II not be in the way.
Make sure the surface behind the HyTerm is flat and
free of any foreign objects. Then tip the HyTerm up
approximately 70 degrees so that it balances on the
rear edge of its bottom cover. Do not allow the table
surface or any objects to apply pressure to the finned
heat sinks on the rear; since these heat sinks are
mounted on the power amplifier boards, any pressure
could damage the circuit boards or the mother board
and its connectors. Also, whil..e the HyTerm is tilted
up in this manner, hold onto it with one hand to
prevent it from failing.
This section is generally divided so that those perform ing
modu Ie replacement will use the next three sub-headings,
(3.2) PREVENTIVE MAINTENANCE, (3.3) MODULE
REPLACEMENT, and (3.4) ADJUSTMENTS. The remainder of this section contains component location/
identification information that will be useful in troubleshooting.
(6)
NOTE
Preven tive Main tenance, when performed
according to the procedures listed here,
will not affect the Diablo warranty. However, any module replacemen t or adjustmen t unsuccessfully attempted will
render the warranty null and void. All
time and material required to restore the
CAUTION
F edron Platen Cleaner and similar
products are flammable, and have a very
low flash point.
(7)
HyTerm to working order will be billed at
the prevailing rates.
3.1.1
General Rules
3.1.2
There are a few general rules that should always be
observed:
(1)
Never remove or install any circuit boards, or connect
or disconnect any plugs, while power is on.
(2)
Applying power to the HyTerm initiates a printer
Restore sequence, which includes carriage movement.
Make sure the carriage is free to move to the left
before applying power.
(3)
(4)
Do not use alcohol to clean the platen, the paper feed
rollers, or any other rubber parts. Alcohol dries out
the rubber and hardens it, eventually resulting in
paper feed problems. Use "Fedron Platen Cleaner" or
its equivalent.
Take care not to touch plastic parts with platen
cleaner. These products are usually harmful to
plastics. Use alcohol to clean plastic parts.
Top Cover Removal
Removal of the top cover is a prerequisite to most
HyTerm maintenance procedures. It is relatively easy, but
slightly more difficult on HyTerms having the control panel
mounted to the top cover; on these units, have the HyTerm
adjacent to a table or other work surface on which the
cover can be placed after it is removed, since it will still be
connected to the HyTerm by its cables. Proceed as follows:
Whenever the access cover is removed, be careful not
to brush against the cover-open switch: operating this
switch could allow the carriage to move suddenly,
wh ich could cause an injury. When operating the
HyTerm with the access cover removed (and the
cover-open switch in the "override" position), keep
fingers, hair, etc., away from the printer.
Never remove the top cover without first disconnecting the power cord from the wall outlet.
3-1
(1)
Unplug the power cord from the wall.
(2)
Raise or remove the access cover. Remove the plastic
skirts over the ends of the platen shaft, if so
equipped.
(3)
Remove the platen: grasp the platen knobs in both
hands, press down the platen latches with your
thumbs, and lift the platen straight up.
(4)
Release the top cover by pulling forward on the two
latches inside the cover at the sides, just in front of
the platen. Lift thp. cover straight up.
(5)
locations required other than printwheel home sensor
tab).
If the control panel is not mounted to the cover, set
the cover aside. If the cover has the control panel
attached, hold the cover in one hand while removing
CAUTION
the ribbon cables from their cable clamps to provide
more cable length. (Note the routing of the cables for
later replacement.) Then set the cover down next to
the HyTerm. The HyTerm can be operated in this
condition, but if the power cord is plugged in with
the top cover removed, stay away from the power
switch terminals, which have line voltage present on
them.
3.2
ments. The third level, also corrective in nature, involves
(8)
for assistance with more
NOTE
(Diablo ii99009) and a long nose self-locking clamp
(Hemostat, Diablo it16424)
(12) TORX ® Driver Bit
itT15
no. 70826-01
The Diablo warranty is null and vaid when a Level 2
or 3 procedure has been unsuccessfully attempted.
All time and material required to restore the
terminal to working arder will be billed at prevailing rates. Na adjustments should be attempted
unless equipment malfunction indicates a specific
need.
Tools
Driver Bit
Screwdriver
=T9
=T15
no. 70826-02
no. 70826-03
Screwdriver
=T9
no. 70826-04
Key Wrench
.:rT15
no. 70826-05
Key Wrench
=T9
no. 70826-06
(13) Connector Extractor, 3M .=t3438, no. 70832
(14) Combination Adjustment Tools no. 40795
40795-01, and 40796
Supplies
The following supplies are necessary for proper prevenDiablo
One Carriage Drive Motor
(9) One Carriage Drive Cable assembly
(10) One Forms Tractor assembly, if appropriate
(11) Assortment of hand tools adequate for electron ie/
mechanical repair, including a T-handle spring tool
user will be lim ited to Level 1 Procedures. Diablo Customer
are
a very low flash point, so use with care.
Observe OSHA safety rules far use af
(7) One Carrier assembly, complete with paper feed
motor
the maintenance of the machine. As long as the 1610/1620
term inal's warranty remains in force, maintenance by the
(numbers
4.
(4) Control Panel assembly, no. 23710
(5) One Platen (appropriate type)
(6) One Carriage assem bly
Levels 2 and 3 are warranty and post-warranty periods in
maintenance
Platen cleaners are flammable, and have
(1) One set of circuit boards
(2) Keyboard assembly (appropriate type)
(3) Power Supply
depot and/or factory repair or refurbishment of assemblies
and printed circuit boards.
tive/corrective
numbers):
3.
Level 2:
Level 1 items, plus unit replacement, circuit
board exchange, subassembly replacement, and minor
adjustments and alignments.
The maintenance procedures described below are divided
into three levels. The first level is preventive maintenance
and may be accomplished by any user. The second level is
corrective maintenance involving on-site exchange of
printed circuit boards and subassemblies, and minor adjust-
3.2.1
Do NO T use alcohol on rubber items.
Do NO T use platen cleaners on plastic
items.
compressed air, including safety goggles.
MAINTENANCE PROCEDURES
Service shou Id be contacted
serious problems.
1.
2.
part
(15)
Tensiometer,
change;
(16)
DXX-I KD or equivalent, calibrated for Diablo cable
Cable ties, no. 10538-01
surface cleaning and lubrication; adjustment of print
impression and platen position controls; and minor assem-
(17)
Thermal compound, no. 10549
Levell:
Ribbon
cartridge
and
printwheel
Electromatic
or
Equipment Co. Model
Level 3:
Levelland 2 items, plus major disassembly
and refurbishment of subassemblies, and repair of circuit
boards.
bly exchanges of platens and paper cradle.
(1)
Fedron Platen Cleaner, or equivalent.
(2)
Diablo ::i70243 light oil, Shell Turbo 27, or equiv. (2
drops/app.)
(1)
One Circu it Board Extender assemblY', no. 40539-03
(3)
Diablo ft70364 Polyoil (light white grease)
(2)
(4)
D iablo ~70825 Mu Iti purpose grease 2 oz. tu be
One Carriage Motor Extender Cable assem bly, no.
40667
(5)
(6)
Diablo .ti99000-01
alcohol) or equiv.
Lint free wipers
(3)
(4)
(5)
One Transducer Extender Cable assembly, no. 40666
One Printwheel Motor
One Paper Feed Motor
(7)
Clean, low pressure compressed air (optional)
(6)
(8)
Diablo it70870-01 Permabond 240TM adhesive 1 oz.
Oscilloscope, vbw 15MHz, vds 100 mV /cm, sweep
speed 50ns/cm
(9)
(printwheel home sensor tab only)
Diablo #70847-01 Vibratite TM adhesive, 8cc (all
Alcohol
Pads
(91%
Isopropyl
TORX® is a registered trademark of Camcar Screw & Mfg.
3-2
3.2.2
Cleaning and Inspection
NOTE
Use of compressed air is NOT recommended
when the term inal is loca ted close to 0 ther
equipment that is sensitive to dirt and dust.
It is difficult to state specific rules concerning the
frequency of preventive maintenance inspections, because
of differences in the hou rs of usage and other environmental considerations from one machine to another. It is
recommended, therefore, that the following preventive
maintenance procedure be performed at least every 500
hours of printing time, or every six months, whichever
occurs first:
(1)
(2)
Remove power from the terminal. Raise the access
cover and remove the top cover as noted in Section
3.1.2.
Remove the platen, paper cradle, ribbon cartridge,
and printwheel. I nspect for signs of wear.
(4)
Clean the printer thoroughly, using alcohol saturated
cleaning pads, and wipers. Remove accumulations of
paper residue, ink, dust, etc., with special attention to
the carriage rails and pulley grooves. Heavy deposits
may be first removed by blowing with compressed
air. Be sure to observe all safety precautions when
using compressed air.
Clean the platen, paper bail tires, and paper feed
rollers with a good platen cleaner which is noninjurious to rubber products, such as "Fedron Platen
Cleaner." Do NOT use alcohol.
(6)*
Clean the rest of the HyTerm as required-remove all
dust and foreign material.
(7) *
Inspect the entire machine for loose hardware and
frayed wires or cables.
(8)* Check to be certain that the fan is operating.
Inspect the printer for signs of wear and loose or
broken hardware. Check carriage cable for signs of
wear, and cable pulleys for loose bearings. Check
platen for looseness or wobble. Check platen drive
gears for looseness. Check the carriage for looseness,
wobble, or accumulations of foreign material on the
rails which might cause uneven movement of the
carriage.
(3)
(5)
(9)
Check all power supply voltages (see 3.4.3).
Items above marked with an asterisk (*) should be
checked on every machine visit, not only at the P.M.
inspection.
3.2.3
Lubrication
Lubricate the various parts of the cleaned and inspected
printer according to the following schedule. DO NOT
exceed this schedule. Too much lubricant is often worse
than none at all !
(To be done every six months or if printer has not been
used for more than a week.)
3.2.3.1
(1)
CARRIER SYSTEM (Figure 3-1)
Paper Feed Roller Shaft Pins (A) - Lightly grease the
8 pressure roller shaft pins with No. 70825-01 grease.
Figure 3-1. Carrier System Lubrication Points
3-3
Figure 3-2. Carriage System Lubrication Points
3-4
(2)
(3)
(4)
Platen Position Lever Detent Plate (8) - Lightly
grease the inside of this plate with No. 70825-01
grease.
3.2.3.3
Platen Position Slide Plates (Carrier Frame) (C) Lightly grease exposed slide surfaces (lever moved
limit to limit), and all points of contact with pivots,
eccentrics, guides, etc., with No. 70825-01 grease.
Platen Position Torque Shaft Ends, Bearing Surfaces,
and Spring Loops (D) - Lightly grease these points
with No. 70825-01 grease.
(5)
Paper Release Lever Tab Ramp and Shaft Pivots (E)
- Lightly grease these points with No. 70825-01
grease.
(6)
Paper Release Torque Shaft Pivots and Arm Slots (F)
- Lightly grease these points with No. 70825-01
grease.
(7)
Paper Bail Pivots (G) - Lightly grease these two
points with No. 70825-01 grease.
3.2.3.2
PLATEN SYSTEM (Figure 3-3)
(1)
Paper Feed Idler Gear (A) - Inspect the large felt
washer behind this gear. If it is becoming white in
color, saturate with No. 70364 Polyoil.
(2)
Platen Latches (B) - Lightly grease the contact area
between these arms and the carrier side frames.
(3)
Platen Hubs (C) - Apply one drop of No. 70243 oil
to the bore of the hub at each end of the platen.
CARRIAGE SYSTEM (Figure 3-2)
(1)
Carriage Rails (A) alcohol wipers.
Clean these items only with
(2)
Carriage Rail Bearings (B) - Put 4 or 5 drops of
No. 70243 oil on each side of carriage rails and move
carriage back and forth slowly by hand, allowing oil
to saturate the felts.
(3)
Carriage Pivots (C) - Apply one drop of No. 70243
oil to the pivot on each side of the carriage frame.
Figure 3-3. Platen System Lubrication Points
3.2.4
(4)
Carriage Pivot Spring Loops (D) - Lightly grease the
end loops and posts of the pivot spring on each side
of the carriage frame with No. 70825-01 grease.
(5)
Ribbon Base Plate Pivots (E) - Saturate the felt
washer on each end of the base plate pivot shaft with
No. 70243 oi I.
(6)
Ribbon Drive System (F) - Apply one drop of
No. 70243 oil to the drive and idler gear shafts, and
to the drive key slot.
(7)
(8)
Covers and Switches
Reassemble the HyTerm and note the following items:
Hammer Armature Pivots (G) - Remove the two
rubber cups, and fi" the grease chambers with
No. 70364 Polyoil grease. Replace the rubber cups.
(1)
Replace printer top cover. Check for proper keyboard
and control panel alignment. If any keys or switches
rub against the cover, reposition the keyboard,
control panel, and/or cover.
(2)
Check for proper operation of the paper-out switch.
(3)
Check for proper operation of the cover-open switch.
If the access cover fits too loosely, adjust and/or form
its clamping springs.
(4)
Print Hammer (H) - DO NOT lubricate this item. If
cloth ri bbon is used, insure that hammer is clean.
3-5
Replace all covers and test. Operate all keys and
switches in Local mode and verify proper HyTerm
operation. If facilities are available, establish a remote
data link and test transmit/receive capabilities.
3.3 MODULE/SUBASSEMBLY REMOVAL AND
REPLACEMENT
Table 3-1.
Always make sure power is off before attempting to
replace any components, modules, or subassemblies.
Assembly No.
( Reference)
Designator)
Description
Al
A1Al
A1A2
A1A3
A1A4
A1A5
A1A7
A1A8
HyType II printer
8080 INTERFACE board
LOGIC-2 board
SERVO board
CA R PWR AMP board
HPROl or HPR02 board
XDCR board
P/W PWR AMP board
A2
Power Supp Iy
A3
Keyboard
A4
Control Panel
When module replacement is impractical, subassembly
replacement is a ready alternative.
All modules have been assigned "assembly numbers"
according to the system adopted by the American National
Standards I nstitute (ANSI) in their standard no. Y32.16,
"Reference Designations for Electrical and Electronics Parts
and Equipments". Table 3-1 lists all major assemblies, and
the smaller assemblies that are normally considered replaceable as modules, along with their reference designations.
These designators are used in the remainder of this section
and in the schematics and wiring diagrams, to identify the
various assemblies.
3.3.1
Circuit Boards
Major Assemblies and Modu les
CAUTION
(3)
Using firm, equal pressure on both upper corners of
the board, push it in so that it is fully seated into the
socket. If excessive resistance is encountered, check
first to make sure the proper board is being installed
in the socket: all boards are keyed so they will not fit
in the wrong socket. Refer to Figu re 3-4.
(4)
Reconnect any remaining cables. !\/lake sure the lower
plug (J8B) on the XDCR board is not turned over it is possible to install this plug upside down. The
control panel ribbon connectors that plug into the
HPRO board are numbered; P2 is on the left, P3 on
the right.
(5)
Replace the platen, insert a sheet of paper, and test
the HyTerm briefly.
(6)
After determining that the HyTerm is operating
properly, remove the platen, replace the circuit board
clamp, the top cover, the platen, and test again.
Never remove or insert circuit boards or
plugs with the power on.
REMOVAL
(1)
Turn off power to the HyTerm.
(2)
Remove paper or forms from the printer. Remove
tractor feed if so equipped. Raise or remove the
printer access cover. Remove the platen (refer to
Section 2.4.3 of the Product Description manual if
necessary) .
(3)
Remove the top cover (3.1.2).
(4)
Using a Ph illips screwdriver, loosen the single screw in
the center of the circuit board clamp (Figure 3-4) and
remove the clamp.
(5)
Locate the board to be removed. See Figure 3-4.
(6)
Grasp the board firmly at the two upper corners and
pull it straight up.
3.3.1.1
(7)
Disconnect any remaining cables from the board.
(1)
Remove the old (standard) interface cable, unplug the
black connector from the Jl plug in the upper
left-hand corner of the HPRO board, remove cable
clamp fastened to the left printer side frame, and
slide the cable out through the rear of the terminal.
(2)
There are six different versions of the HCU R L board;
refer to Table 3-2 for the correct board.
(3)
Install the new HCURL board in position F, just
behind the HPRO board.
REPLACEMENT
(1)
(2)
If the HPRO board is being installed, first attach the
keyboard cable to the P2 connector on the circuit
board.
Holding the board with the com ponents toward the
front of the mach ine (toward the platen), insert the
board into the guides and slide it all the way in.
3-6
HCURL BOARD FIELD INSTALLATION
(0) CAR PWR AMP
PW PWR AMP (H)
(C) SERVO
XOCR (G)
HCURL (OPIONAL) (F)
\
HPR010R
HPR02 (E)
\"'
.Figure 3-4. Circuit Board Location
Table 3-2. Current Loop Kit Parts
1.
HCURL Board
Kit Part
#
400495-01
400495-02
400495-03
400495-04
400495-05
400495-99
HCURL Part
#
23942-01
23942-02
23942-03
23942-04
23942-05
23942-99
Type of Operation
Passive, half-duplex
20 mA active, full-duplex
20 mA active, half-duplex
60 mA active, full-duplex
60 mA active, half-duplex
Passive, full-duplex
2.
Interface cable assembly, part no. 400017-01.
3.
Inform ation Packet, part no. 400496-01.
3-7
HOST
HYTERM
(ACTIVE)
CURRENT
SOURCE
~1
014
~
0
~
16
17
0
~
o
~
0
.---------------r--------H-------!--o10
140
0
16
17
0
0
0
0
o
~
~
24
013 025
0
24
250
CURRENT
SOURCE
10
0
0
0
0
0
0
0
1
0
~
130
(PASSIVE)
01
0
0
0
0
0
0
0
014
0
16
17
0
0
0
0
0'0 0
~
013
0 24
025
140
0
16
17
CURRENT
SOURCE
10
0
0
0
0
0
0
0
~
24
25 0
0
0
0
0
0
10
~
130
CURRENT
SOURCE
FULL-DUPLEX
HALF-DUPLEX
(PASSIVE)
(ACTIVE)
140
17
10
~ ~
0
o
~
~ ~
o 0
~10O+--""
o 0
250
CURRENT
13~
SOURCE
(ACTIVE)
(PASSIVE)
!
I
I'!
~
o 0
TRANSMITTER
o
I
0
0
0
0
0
0
,,7
y
I
0
17
0
0
0
0
100
0
0
o
o
CURRENT
DETECTOR
~
332-001
Figure 3-5. Current Loop Connections
3-8
(4)
CAUTION
I nstall the new interface cable
(a)
Insert the end with the two small plugs (P2 and
P3) into the left rear of the HyTerm.
(b)
Connect P2 (the 14-pin connector) to the J1
connector on the HCUR L board.
(c)
Connect P3 (the 12-pin connector) to the J1
connector on the HPRO board.
(d)
Dress the cable neatly and install the cable
clamp (removed in step 1) to hold it in place.
Whenver the HyTerm is tilted up in this
manner, hold on to it with one hand to
prevent it from falling over.
(6)
Loosen the three front screws and three rear screws
that hold on the bottom plate. Do not remove. (The
rear screws are more accessible if the HyTerm is
positioned close to the edge of its table or other
supporting surfaces.) Remove the single screw on
each side of the bottom plate. Bow the plate out in
the middle to free the top or bottom edge from the
mounting screws, and remove the plate.
(7)
Swing the power supply out to access the terminal
strip. Disconnect the wires. Set the power supply
assembly safely aside and tilt the HyTerm down onto
its feet.
NOTE
The DUPLEX switch on the control panel
must be in FU LL position.
(5)
Refer to Figure 3-5. Wire a compatible socket [25-pin
subminiature: Cannon or Cinch DB25P, or AMP
housing 205208-1 with 1-66506 pin inserts; with an
AMP 206472-1 (or equivalent) hood enclosing the
plug] to the current loop wires, and connect it to the
new HyTerm interface cable plug.
3.3.2
REPLACEMENT
Power Supply
(1)
Tilt the HyTerm up and connect the wires to the new
supply as per Figure 3-6. Observe the caution about
tilting the HyTerm noted in step (5) of the removal
procedure.
(2)
Swing the power supply into position inside the
printer casting. Make sure all wires and cables are
positioned secu rely.
(3)
Holding the power supply in position, insert the
mounting screws through the top cover screen and
the printer casting and start them into the threads in
the power supply frame. Start all five mounting
screws.
(4)
Tilt the HyTerm down onto its feet. Tighten all five
mounting screws securely.
(5)
Replace the two rear circuit boards noted in step (5)
of the removal procedures.
(6)
Refer to section 3.4.3, +5 volt adjustment, steps (1) (9), to check out the Power Supply.
(7)
Tilt the HyTerm back up.
(8)
Replace the bottom plate: sl ide it under the rear
screws first, bow it out in the center and slip it under
the front screws. Then insert the two side screws and
tighten all of the screws.
(9)
Tilt the HyTerm down onto its feet. Remove the
circuit board extender and replace the HCU R L board,
if applicable. Install the top cover, the paper cradle,
and the platen. Close the access cover, insert a sheet
of paper, apply power, and test thoroughly.
REMOVAL
(1)
Make sure the HyTerm is disconnected from its
power sou rce.
(2)
Move the HyTerm to a location where both the top
and bottom will be accessible when the machine is
tilted up.
(3)
Raise the access cover. Remove the platen, paper
crad Ie and top cover.
NOTE
If the top cover is the type having the
control panel fastened to it, unplug the
control panel cables from the HPRO board,
free the cables, and set the top cover aside.
(4)
Remove the five screws holding the power supply
assembly to its aluminum cover screen and the printer
frame. This will allow the power supply to drop
slightly, but it will still be held in place by the
bottom cover.
(5)
Remove the last two rear circuit boards wh ich have
the heat sinks mounted onto them. Tilt the HyTerm
up so it is resting on the rear edge of the bottom
cover.
3-9
TBl
1
2
POWER
3
4
SUPPLY 5
6
7
r-
AC
I 8LACK
'\
I
/
TO
FAN
WHITE
\....
8
9
®
®
®
®
®
®
®
®
®
®
®
WHITE
+ 5V
(2)
GND
(2)
(1)
RED
NOT
+15V
(2)
SROWN
(:::=~
GND
(2)
-15V
USED
FRAME GND
(NOT
SLAC]
WHITE
LJSED)
AC
FROM
POWER
SWITCH
Figure 3-6. Power Supply Connections
3.3.3
Control Panel
(5)
REMOVAL
(1)
For control panels mounted to the printer casting,
remove the three screws that fasten the control panel
mounting brackets to the printer frame, two on the
carriage motor frame and one on the right side frame.
Unplug the HyTerm from its power source.
REPLACEMENT
(2)
(3)
(4)
Raise the access cover,. Remove the platen skirts, the
platen and the top cover.
(1)
If the control panel is the type mounted to the top
cover, remove the two mounting nuts with a
5/16-inch end wrench, remove the cables from the
cable clamps, and remove the control panel from the
cover.
On control panels mounted to the top cover, position
the panel on the cover, install and tighten the two
lock nuts, and skip to step (3).
(2)
On control panels mounted to the printer casting,
place the control panel in position and insert the
three mounting screws. Tighten all screws just snug
enough to hold the panel in position, but still allow it
to be moved by hand.
(3)
Dress the cables between the keyboard and the
printer casting, around the left side of the printer,
and up to the HPRO board. Insert the cables into the
flat cable clamps. Plug the cables into the HPRO
board. The two cables have numbers stamped on
them. The one stamped "2" plugs into the left-hand
Unplug the control panel cables from the two
connectors on the HPRO board, and slide the flat
cables out of the cable clamps.
NOTE
Observe flat cable routing so the new
cables can be installed the same way.
3-10
(4)
(4)
Replace the top cover.
(5)
For panels mounted to the cover, go on to step (6).
proper clearance between the key tops and the cutout
in the top cover. Using a trial-and-error process,
reposition the keyboard unti I the top cover can be
For panels mounted to the printer casting, move the
control panel assembly right-to-Ieft until the switches
are centered in the switch openings, and tighten the
installed fully with no interference between the
key tops and the cover.
three bracket mounting screws. Test all switches for
proper operation. If the switches do not operate
(5)
properly, or if it is difficult to attach the top cover
properly, it will be necessary to adjust the control
panel up-and-down or backward-and-forward. Refer
When the correct position of the keyboard has been
obtained, again remove the printer cover, tighten all
four keyboard mounting screws fully, and reinstall
the cover.
to Section 3.4.2 for this procedure.
(6)
Turn off power and unplug the power cord. Carefully
position the top cover in place, while checking for
Replace the platen and the platen skirts, plug into a
(6)
power source, and test for proper operation.
Replace the platen and the platen skirts, Plug in the
power cord, turn on power, and test the HyTerm
again.
3.3.4
Keyboard
3.3.4.1
KEYSWITCH REPLACEMENT
REMOVAL
(1)
Unplug the power cord from the wall outlet.
(2)
Raise or remove the access cover. Remove the platen
skirts and the platen. Remove the top cover (3.1.2).
(3)
Unplug the keyboard cable from the keyboard.
(4)
Remove the four screws that mount the keyboard to
Once the keyboard has been removed, individual keyswitches can be replaced, using a soldering iron and two
special module removal tools. The special tools are available
from the Micro Switch division of Honeywell, Freeport,
Illinois. Order no. SD-1 01 01. Proceed as follows:
CAUTION
When removing the LOCA L or UC ON L Y
key tops, make sure the switch plunger is
in its upper position,' otherwise, the
module will be damaged
its mounting bracket. Lift out the keyboard and set it
aside where it will not be subject to damage.
REPLACEMENT
(1)
(1)
Position the new keyboard in place on the mounting
Remove the key tops from the modules on either side
brackets. Start all four mounting screws. Position the
keyboard in its approximate
tighten one screw on each end.
(2)
final
Remove the key top from the module being replaced,
by lifting or prying upward with a padded tool.
of the one to be replaced. It may be necessary to
remove other adjacent key tops to provide adequate
position and
work space.
Attach the keyboard cable plug to the keyboard.
A special key top puller, no. SW-1 0485, is available
from Micro Switch.
WARNING
(2)
(3)
Unsolder the four module terminals from the circuit
board. Use a solder removal tool to remove all solder
When the HyTerm is connected to a
power source, line voltage is present at
the POWER switch terminals. To avoid a
dangerous shock when power is applied
and the top cover is removed, keep
fingers away from the PO WE R switch
terminals.
from the pin holes in the circuit board.
(3)
Insert the module removal tools, one in front and one
behind the module being removed.
(4)
Grip the switch module with a pair of pliers and pull
it straight out.
(5)
I nstall the replacement module. Before snapping it
into place, make sure it is oriented properly and that
all four pins are through the circuit board.
Plug the power cord into the wall outlet, turn on
power, and test for proper keyboard operation. (Pull
the cover-open switch plunger out to its override
position to allow normal operation with the covers
off.)
3-11
(6)
Solder the new switch terminals, using 60/40 rosin
0
core solder and a 750 F soldering iron with a 1/8"
chisel tip.
REPLACEMENT
(1)
Reverse the removal steps with a new fan and/or fan
cable assembly.
CAUTION
3.3.6
Never hold the soldering iron to the
module pins for more than four seconds.
Paper Feed Motor
REMOVAL
NOTE
(7)
(8)
The solder joints may be cleaned (on the bottom of
the circuit board) with mild solvent. Be careful not to
get any solvent on the switch modules or key tops.
This procedure can be used with or without
the carrier subassembly being removed from
the printer. If the carrier subassembly is not
to be removed, then comple te Steps 1, 2, 3
and 4 of Procedure 3.3.7.
Replace all key tops. Make sure they are replaced on
the right key and that the legends are properly
oriented.
3.3.5
(1)
Using a TO RX T15 screwdriver, remove the three (3)
8-32 x 3/4" screws holding the paper feed motor to
the right-hand carrier side frame as follows: remove
the two bottom screws first, and retrieve their spacers
from between the motor flange and the carrier frame.
Remove the upper right-hand (as you view it) screw
last, and retrieve its spacer from behind the motor
flange. Note that this spacer has a shoulder which fits
into the motor flange hole to prevent side play. Refer
to Figure 3-7.
Cooling Fan
REMOVAL
(1)
Remove the printer covers and unplug the HyTerm
from its power sou rce.
(2)
Using a TORX T15 screwdriver remove the two (2)
8-32x.625 screws holding the fan to the printer frame
and retrieve the spacers.
(2)
Gently pull the fan up and away from the carriage
frame to provide enough room to disconnect the
motor leads.
Tilt the motor down and out of the carrier side
frame, and gently pull its connecting wires free from
the wire bundle inside the printer.
(3)
Using an 11/32" open end wrench and a blade
screwdriver, remove the paper feed idler gear mounting stud eccentric, nut, and washers (2) from the
paper feed motor's upper left-hand flange hole (as
you view it). Refer to Figure 3-7.
(4)
Transfer the items removed in Step (3) above to the
replacement motor exactly as they were arranged on
the removed motor (upper left-hand flange hole, nut
and washers to the rear side).
(3)
(4)
Disconnect the two motor leads from the fan cable
assembly by pulling the connectors apart.
(5)
If the fan cable assembly must be replaced, first
follow the procedures for removal of the power
supply (Section 3.3.2) to gain access to the fan cable
connectors. Then unscrew the two (2) connectors
from pins 8 and 9 of the power supply terminal strip.
(TOP P.O. SW. BAIL
~'=~~!~(.--- SHAFT HOLE)
IDLER GEAR
ECCENTRIC
Uf'PER MOUNTING SCREW
(SPECIAL SPACER)
PAPER FEED
MOTOR
LOWER MOUNTING SCREWS
(PU'IN SPACERS)
Figure 3-7. Paper Feed Motor Removal
3-12
skip to Section 3.3.7, Step (6) for the remaining steps to
reconnect the motor electrically, and for directions leading
up to its adjustment.
REPLACEMENT
(1)
(2)
(3)
Carefu lIy insert the replacement paper feed motor's
connecting wires into the opening in the right-hand
carrier side frame, and tilt the motor into position in
the frame opening.
3.3.7
Paper Carrier Subassembly
REMOVAL
Orient the paper feed motor with the idler gear
eccentric stud upper left, as shown in Figure 3-7.
Insert the special shoulder spacer [removed last in
Step (1) of the removal procedures above] behind the
motor's upper right flange, with its shoulder extending into the hole in the flange. Loosely thread one of
the 8-32 x 3/4" screws into the carrier side frame
through the motor flange and spacer.
Place spacers behind and insert 8-32 x 3/4" screws
[removed first in Step (1) of removal procedures
above] through the two bottom motor mounting
holes; then finger tighten only. Now tighten the first
screw [step (2) above] until snug, but not so tight as
to restrict lateral movement of the motor.
(1)
Remove the access cover, platen, and top cover (make
sure power is off first).
(2)
Remove and store the ribbon cartridge, printwheel,
and paper cradle.
(3)
Use the no. 99009 T-Handle Spring Hook to disengage the four (4) Carrier System load springs from
the printer's main frame (2 long springs in front, and
2 short springs in the rear). Open the wire bundle and
disconnect the four (4) paper feed motor wires from
the mother board. Refer to Figure 3-8.
(4)
Remove the 'E' ring and the paper feed idler gear.
Locate the two carrier assembly load springs, one on
each end, mounted between the inboard end of the
rear support screw on the main frame. Remove these
springs also. Store the springs, gear, and 'E' ring in a
safe place. Refer to Figures 3-8 and 3-9 .
This completes the installation of the paper feed motor
only on a carrier su bassembly. If th is was a motor
replacement only (did not involve paper carrier removal),
•
"'==------"--
LOAD SPRINGS
(L.H. END SHOWN)
Figure 3-8. Carrier System Removal
"E" RING
Figure 3-9. Carrier System Removal
3-13
(5)
(6)
Using a 1/4" wrench or nut driver, remove the leftand right-hand front carrier subassem bly height
adjustment eccentrics. Using a TO RX T15 screwdriver, remove the Ieft- and right-hand rear carrier
subassembly support shou Ider screws. Store these
items in a safe place. Refer to Figure 3-9.
(2)
Carefully lower the carrier subassembly into position
on the printer main frame. Refer to Figure 3-10.
(3)
Insert the left- and right-hand rear carrier subassembly shoulder support screws removed in Section 3.3.7
removal procedures, Step (5), using the TO RX T15
screwdriver. Make sure the screw shoulders pass into
the slots in the carrier side frame, and tighten the
screws firmly, but DO NOT overtighten and strip the
threads from the holes in the main frame casting.
(4)
Insert the left- and right-hand front carrier subassembly height adjustment eccentrics removed in Section
3.3.7 removal procedures, Step (5), using a 1/4"
wrench or nutdriver. Make sure the shoulders of the
eccentrics pass into the slots in the carrier side
frames, and thread the screws in enough to retain the
eccentrics snugly in the slots, but do not tighten. The
eccentrics should be positioned so their lobes point
toward the rear of the machine.
(5)
Use the #99009 T-Handle Spring Hook to connect
the loose ends of the four carrier subassembly load
springs to the main frame making use of the holes
provided. Section 3.3.7 removal procedures, Step (3),
detailed the unhooking of these springs for the old
subassembly just removed.
(6)
Arrange the four wires from the paper feed motor
into the wire bundle running along the edge of the
mother board, and connect them to the push-on
term inals on the mother board as follows: gray wire
to terminal T4; black wire to terminal T5; yellow
wire to terminal T6; and the red wire to terminal T7.
Secure the wire bundle with plastic cable ties or
equivalent.
Carefully lift the carrier subassembly, including the
paper feed drive motor, free of the printer main
frame, as shown in Figure 3-10. Be sure the motor
wires are free and not caught in the wire bundle.
REPLACEMENT
(1)
Clean all carrier subassembly bearing surfaces on the
printer main frame of old grease, etc. Reapply a light
coating of multipurpose grease to these points, on
both ends of the main frame. Refer to Figure 3-11.
Figure 3-10. Carrier System Removal
, - - - - - - TORQUE SHAFT BEARING NOTCH
CARRIER Slot PLATE
SLIDING BEARING SURFACES
( R. H. END SHOWN)
,
I
.'-'~'
Figure 3-11. Carrier System Replacement
3-14
3.3.8
Carriage Subassembly
REMOVAL
(1)
Remove the access cover, platen, and top cover (make
sure power is off).
(2)
Remove and store the ribbon cartridge and printwheel.
(3)
Open the left-hand (as shown in Figure 3-12) wire
bundle, and unplug the sheathed printwheel drive
cable connector P4 at mother board connector J4.
Separate this cable from the wire bundle for later
removal. Also disconnect the black ground wire,
which is a part of this cable, where it is fastened to
the main frame near the end of the cable's shield
spring.
(4)
CLAMPS
Figure 3-13. Cable Clamp Removal
Open the other wire bundle. Locate the sheathed
cable extending from connector J8B on the Transducer board (Slot G) to the carriage through the
smaller cable shield spring. Unplug this cable at the
circuit board, and prepare it for later removal from
the printer with the carriage.
NOTE
If the optional Bottom Feed Paper Chute is
instal/ed, sk ip to Step (6).
(5)
(6)
•
Use the TORX T15 screwdriver to remove the
four (4) no. 8-32 x .625" screws which fasten
the bottom plate to the printer's main frame.
•
Move this plate away from the frame far
enough to release the large spring cable shield
from the two spring clips, and to gain access to
the four (4) no. 6-32 x 1/2" screws used to
clamp the small spring cable shield to the
bottom plate. Remove these screws using the
TO R X T15 screwdriver. *
*Service Note: If the printer being worked on has other
wire bundles fastened to the bottom plate with snap-in
metal spring clips, remove these clips and replace them
with cable ties.
Refer to Figure 3-13. Using the TORX T15 screwdriver, reach down behind the left end of the rear
carriage rail and unscrew the four (4) #6-32 x 1/2"
screws holding the white plastic spring cable clamps
to the bottom plate. Retrieve and store these screws.
Reach down behind the right end of the rear rail and
remove the large spring cable shield from the two
spring clips holding it to the bottom plate.
(7)
This step applies only to those printers with the
optional bottom feed paper chute installed. Refer to
Figure 3-12.
Refer to Figure 3-14. Position the carriage slightly to
the right of center, to gain access along the right side
of the carriage servo motor to the mounting screw for
the carriage drive cable pulley. Install the hemostat
clamp on the pulley as shown (use a piece of heavy
paper between the pulley and clamp jaws to protect
the pulley flanges). This prevents the pulley from
moving or flipp ing over and releasing the drive cables.
Refer especially to Figu re 3-14b. Note that the clamp
is installed to trap the upper forward right-hand cable
;reB
GROUND
CONNECTION
BOTTOM PLATE
Figure 3-12. Prepare Carriage Cables for Removal
3-15
a
b
Figure 3-14. Disconnecting the Carriage Drive Cable
(9)
segment between its jaws as it is clamped to the
pulley. Make sure this has been done, and that the
clamp is secu re before proceeding.
Use the TO RX T15 screwdriver to reach up beside
the carriage motor and remove the pulley mounting
screw. Make sure the pulley is free from the carriage
frame, and gently move the carriage to the left to
clear the pulley. Retrieve the spacer from the top of
the pulley, and note that the spacer has a shou Ider
which extends down into the center of the pulley
when properly assembled. Store the spacer and pulley
mounting screw. DO NOT remove the hemostat
clamp from the pulley!
(8)
Lay the carriage and rail assembly on a clean flat
surface. Slide the front rail sideways out of the front
carriage bearing sleeve and put it aside in a safe place.
Slide the heavy rubber bumper washers off the ends
of the rear rai I. Note that there are two washers on
the left end, and only one on the right end. Store
these washers. Finally, slide the rear rail sideways out
of the rear carriage bearing sleeve, and place with the
front rail.
REPLACEM ENT
Replacement carriage subassemblies are complete, jig
aligned, and functionally tested at the factory. They are
ready for installation and operation as received, and usually
require only a minor readjustment or two for print quality
after installation.
Refer to Figure 3-15. Using the TORX T15 screwdriver, remove the eight (8) no. 8-32 x .625" carriage
rail clamp screws, clamps, and the impression control
switch, and store the loose items. Grasp the carriage
and rails in one hand and carefully lift the assembly
up out of the printer main frame while guiding the
two sh ielded cables and their connectors clear of the
printer structure.
(1)
Carefu IIy remove the white felt washers from their
plastic bag (shipped with each carriage subassembly),
and saturate 4 of them (there are usually 1 or 2 extra)
with light oil.
RAIL
CLAMPS
RAIL
CLAMPS
IMPRESSION
CONTROL
SWITCH
Figure 3-15. Carriage Rail Clamps
3-16
(2)
(3)
DO NO T slide the carriage to the left so as
to damage the carriage home sensor
(mounted on the main frame) with the
sensor flag (mounted on the carriage).
Retrieve the carriage rails from their storage place,
and thoroughly clean them with alcohol. After
cleaning, check both rails for straightness and surface
defects. Replace any rail which is bent or defaced.
(4)
Refer to Figure 3-16. Slide the cleaned and inspected
carriage rails through the front and rear carriage
bearing sleeves.
(5)
Gently slide an oil saturated felt washer on each rail
end, followed by a white plastic bearing wiper. Be
very careful not to stretch or break the felt washer.
Push the washers into their bearing sleeves with the
bearing wipers, and snap the wipers into position over
the ends of the bearing sleeves.
(6)
CAUTION
Unless replacement of the carriage drive cable is to be
included at this time, remove the drive pulley and
spacer from the underside of the carriage.
(9)
NOTE
If the optional bottom feed paper chute is
instal/ed, skip to Step (12).
Install the heavy rubber bumper washers on the rear
carriage rail, two on the left end, and one on the right
end.
(7)
Gently lower the carriage subassembly and rails down
onto the printer main frame, with the rail ends nested
in the frame notches. Move the rails until even on
each end, reinstall the rail clamps, and the impression
control switch. Tighten the 8 clamp screws firm Iy,
using the TORX T15 screwdriver.
(8)
Hold the two spring shielded cables up out of the
way, and gently sl ide the carriage back and forth as
far as it will go. Carriage movement must be smooth
and even, with no evidence of binding or roughness.
Place the spacer on top of the carriage drive pulley
with its shoulder extending down into the center of
the pulley. Position the carriage over the clamped
pulley, and insert the shoulder screw. The spacer and
screw were removed in Step (7), Section 3.3.8
removal procedures. Tighten the screw firm Iy with
the TORX T15 screwdriver, and remove the Hemostat Clamp.
(10)
Arrange the small (transducer) spring shielded cable
(from the right side of the carriage) down inside the
printer main frame behind the carriage drive cable,
and back to the left along the center of the bottom
plate. Extend the free end out of the bottom of the
printer to the left. Position the first plastic clamp
over the threaded screw hole farthest left in the
bottom plate, with its holes to the rear. Thread in
two (2) no. 6-32 x 1/2" screws, place the spring
shield in the clamp with about 1/8" of the spring
extending to the left beyond the clamp, and with the
loop of the spring as straight as possible vertically,
tighten the two clamp screws using a TORX T15
screwdriver. Move the second plastic clamp into
OILED FELT
WASHER
BEARING
WIPER
FRONT BEARING
SLEEVE
RAIL
Figure 3-16. Carriage and Rai I Assembly
3-17
3.4 ADJUSTMENTS
position, holes to the rear, just left of center on the
bottom plate over the two threaded holes provided;
insert two more no. 6-32 x 1/2" screws and tighten
them securely.
Any necessary tests and/or adjustments should be
performed in the sequence outlined in this section, because
some adjustments affect others. No adjustments should be
attempted unless a malfunction indicates a specific need.
{11} Arrange the large {printwheel drive} spring sh ielded
cable (from the left side of the carriage) down inside
the printer main frame behind the smaller spring
cable just installed, and along the rear edge of the
bottom plate. Extend the free end out the bottom of
the printer to the right. Position the spring as straight
as possible vertically, with the end of the shield spring
about 1/8" beyond the spring clip mounted farthest
right on the bottom plate, and push the spring back
under the clip. Push the body of the spring shield
under the second spring clip located just to the right
of the center on the bottom plate.
3.4.1
Printer
Several printer adjustments can be made using the
Combination Adjustment Tools, Diablo part no. 40795 or
40795-01, and 40796.
NOTE
In the following procedures you are often
told to tilt the carriage forward or rearward:
forward means toward the keyboard, the
operator, the front of the terminal,' rearward
means toward the platen. The carriage will
detent in either position. To move it for-
(12) This step applies only to those printers with the
optional bottom feed paper chute installed.
•
Position the bottom plate beh ind the carriage,
in the area of the platen, with its spring clips
(for the large cable) to the right on top.
•
Loop the small (transducer) spring shielded
cable (from the right side of the carriage) back
around to the left, and position its plastic
clamps over the screw holes left of center and
near the left end of the bottom plate. Thread in
the no. 6-32 x 1/2" screws to hold the clamps
in place, but do not tighten them.
•
•
ward, first remove the ribbon cartridge.
Then simply grasp it by the "ears" near the
ribbon guides and pull it away from the
platen. To move it rearward, simply push it
back up toward the platen.
3.4.1.1
PR I NT QUALITY TEST
The print quality test can provide an indication as to
possible needed adjustments. Proceed as follows:
Loop the large {printwheel driver} spring
sh ielded cable (from the left side of the carriage)
back around to the right over the smaller spring
shielded cable, and snap it into the two spring
clips right of center and near the right end of
the bottom plate.
(1)
Print a full line of capital letter "H"s.
(2)
Refer to Figure 3-17 and compare the test results
with the illustration.
(a)
Work the bottom plate, with cables attached,
back through the main frame. Move the plate
into position and fasten with the four (4) no.
8-32 x .625" screws removed in Step (6) of
Section 3.3.8 removal procedures, using the
TO RX T15 screwdriver. Secure the carriage
drive motor wire bundles to the plate with
cable ties.
{13} Arrange the two sheathed cables into the wire
bundles from which their counterparts were removed
in Steps (3) and (4), Section 3.3.8 removal procedures, and plug them in; Transducer cable to
connector J8B on the Transducer board (Slot G); and
the Printwheel Drive cable to connector J4 on the
mother board. Secure the two wire bundles with
cable ties.
Impressions similar to this with uniform density
and good edge definition indicate proper adjustment of the printer. A gradual change in
density (lighter or darker) from one end of the
line to the other indicates a Platen-toPrintwheel adjustment may be required.
H
H
(a)
(b)
I~
(c)
(d)
(e)
Figure 3-17. Print Quality Standards
3-18
(b)
Impressions similar to this indicate Platen
Height adjustment may be required for platen
too low.
(c)
Impressions similar to this indicate Platen
Height adjustment may be required for platen
too high.
(d,e) Impressions similar to this indicate that a
Printwheel-to-Hammer adjustment may be
required.
3.4.1.2
3.4.1.2.1
(1)
PAPER CARRIER SYSTEM
Carrier Assembly.
Carrier Assembly Bias Shaft, Figure 3-18, item (A).
Check for axial movement = .002 in., +.000 in., -.001
Figure 3-18. Carrier Assembly Adjustment
in. (.05mm, +.OOmm, -.03mm). Adjust the collar at
(A) as required to achieve this dimension.
(2)
Platen Position Torque Shaft, Figure 3-18, item (B).
Check that the setscrews in the eccentric collars (C),
at each end of th is shaft, are al igned vertical with
each other when the platen position lever is full
forward, and that the shaft end play = .001 in. ±
.0005 in. (.03 mm ± .01 mm). Adjust these collars as
requ ired to ach ieve these two goals.
(3)
Platen Position Lever, Figure 3-18, item (D). Move
the lever back and forth. A positive detenting force
must be felt for all positions. Adjust the detent plate
(E), as necessary to achieve an even detenting action.
The carrier assembly must move equally at both ends
in increments of .005 in. ± .002 in. (.13 mm ± .05
mm) between detent positions.
c
Figure 3-19. Paper Feed Adjustments
3.4.1.2.2 Paper Feed Rollers. Refer to Figure 3-19.
With the paper release lever (A) fully forward, the paper
feed rollers (G) must clear the platen (E) by a minimum gap
of .080 in. (2 mm). To achieve this, and other goals, adjust
the paper feed system as follows:
(1)
(2)
front paper feed rollers and the platen. Check that
both platen and rollers rotate when the strip (or
shim) is pulled free. Repeat for all rollers front and
rear. If no rotation occurs, the torque shaft arm tabs
(B) have been pushed down too low.
Insert 4 sheets of standard form paper (.012 in. or
.3 mm) and move the paper release lever fully
rearward.
3.4.1.2.3
Paper Feed (Platen) Drive. Refer to Figure
3-20. With paper feed motor drive gear (A) locked, platen
drive gear (B) must have a .002 in. (.05 mm) maximum play
[total play includes idler gear (C)] .
Ensure that the torque shaft arm tabs (B) are
touching the lower edge of the feed roller support
arm slots (C).
(1)
Loosen the paper feed motor mounting screws (D).
(3)
Ensu re that the paper release actu ator (D) is touching
the ramp on the paper release lever. Loosen the
actuator's setscrew and adjust the actuator to achieve
this condition, then retighten the set:;crew.
(2)
Rotate eccentric (E) counterclockwise ON LY (clockwise will not allow the platen to be installed
properly), until a minimum backlash is obtained with
0
no binding effect when rotating idler (C) a full 360 •
(4)
Remove the 4 sheets of paper, and insert one strip of
paper 1 in. wide (or a .004 in. shim) between the
(3)
Install the platen. Rotate the paper feed motor
clockwise about mounting screw (01) to remove
3-19
backlash between platen gear (8) and idler gear (C).
Tighten all screws.
.0020
MAX.
3.4.1.2.4 Platen Knob End Play. Refer to Figure 3-21.
End play should be .002 in. (.05 mm) maximum, as shown.
Adjust for proper clearance by loosening the setscrews in
the platen release gear hub (A) and moving the hub.
Retighten the setscrews.
3.4.1.3
(1)
CARRIAGE DRIVE CABLE (Figure 3-22)
With the carriage positioned against the left hand
mechanical stop, check the cable tension midway
along the exposed cable for a force of 16.5 ± 3.3 Ibs.
(7.5 ± 1.5kg) necessary to distort the cable as shown.
NOTE
If the Tensiometer, listed in Section
3.1.3, is not used, the dimensions
between force points must be carefully
followed.
Figure 3-20. Paper Feed (Platen) Drive Adjustments
(2)
Adjust cable tension by tightening or loosening cable
tension nut (8).
CAUTION
The square shank on the end of the cable
(A), must not rotate while adjusting nut
(8).
After adjusting the nut (8), move the carriage back
and forth several times to redistribute cable tension,
and recheck.
3.4.1.4
PRINT QUALITY ADJUSTMENTS
Certain conditions are necessary prior to making adjustments, they are:
.002·
MAXIMUM
(1)
Power
Power is to be applied to the HyTerm while making
these adjustments. It is used to electri~ally detent the
Figure 3-21. Platen Knob End Play Adjustment
3.937"
1 - - - - - - - - - (IOem) - - - - - - - - - 1
.130"
(.33 em)
1.968"
t - - - - - (~cm) - - - - J
16.5! 3.3 LBS
(7.5.! 1.5KG)
Figure 3-22. Carriage Drive Cable Adjustment
3-20
printwheel and carriage servo motors, and for cycling
the printer through a Restore sequence when
required.
(2)
(3)
(4)
Either of two alignment tools, 40795 or 40795-01, may
be used in making these adjustments. In most cases, the
procedures are the same with either tool, but in some cases
two separate procedures are listed. The following adjustments are included in this group:
Platen
Platen Carrier adjustments are to be made with a
platen installed whose su rface is in good condition
and free from wear or defects.
(1)
Printwheel-to-Hammer
(2)
Platen-to-Printwheel
Controls
(3)
Platen Height
The Platen Position (manifold) lever is to be brought
fully forward for these tests and adjustments.
(4)
Card Guide Height and Position
(5)
Ribbon
(6)
Hammer
(7)
Carriage Home
Precautions
Always remove the alignment tool from the printwheel motor shaft before initiating a Restore
sequence, to prevent damage to the printer. Also
always ensure that the tool is properly seated prior to
making any measurement. When it is necessary to
move the carriage with the alignment tool installed,
first tilt the carriage forward, away from the platen.
This will avoid possible damage to the platen.
CARD GUIDE
ALIGNMENT
TAB
1/4" 1t1880N ADJUSTMENT
FEATURES
8
SLOT
DI
_
CARRIAGE liOMf(0--- ADJUSTMENT
FI
TAB
AOJUST"ENT~)
PLATEN
Figure 3-23 identifies the several alignment/adjustment
features of the alignment tools by a number-letter designator. These designations are used in the procedures that
follow.
/
TAli
'1,
~f'B
v~
h
~
(~CAR HOME
~) "NO- 90"
CARRIAGE HOME
ADJUSTMENT
TAli
-\ '
"" O"D'
(\,~ AL~::ENT
I
.""".,"
m
"'::T
CAR HD.'
TAO
.2
333-009
RIBBON HEIGHT ~
ADJUSTMENT
E
SLOT
'
01
40795
CARD QUIDE
ALl6NMENT TAB
4079&01
Figure 3-23. Adjustment Tools
3-21
TAIl
ALIGNMENT TOOL
#: 40795-01
333-008
Figure 3-24a Printwheel Alignment
3.4.1.4.1
Printwheel-to-Hammer.
3-24a and 3-24h. Proceed as follows:
Refer
to
Figures
(1)
Apply power to the printer and verify completion of
a RESTORE sequence. Remove any paper, the ribbon
cartridge, and the printwheel.
(2)
Refer to Figure 3-24a.
Install adjustment tool
#301445-01 over the nut on the front of the
printwheel hub. Install alignment tool #40795-XX
firmly on the printwheel motor shaft hub and ensure
that it is properly seated with its alignment slot
engaged over the hub's alignment tab.
(3)
(4)
(5)
CAUTION
Carriages with the mechanical printwheel
hub DO NOT REQUIRE USE OF ANY
ADHESIVE.
3.4.1.4.2 Platen-to-Printwheel.
Proceed as follows:
(1)
Refer to Figure 3-25.
Preparation
NOTE
It will be necessary to readjust platen height
for print quality, and the card guide after
completion of this procedure.
Rotate the alignment tool to bring its hammer slot in
front of the print hammer. Block the home sensor by
inserting a piece of dark paper into its slot to detent
the printwheel motor.
Manually push the print hammer toward the platen
until its face enters the alignment tool's hammer slot.
If the hammer slides easily into the slot without
contacting the sides, printwheel-to-hammer alignment
is correct. If the hammer contacts either side of the
slot, or the hammer will not enter the slot, continue
with this procedure.
Refer to Figure 3-24b. Place a screwdriver blade at
point 1 or 2. By twisting the screwdriver you will be
moving the alignment tab in relation to the printwheel hub. Move the adjustment tool as necessary to
achieve proper alignment.
3-22
(a)
Loosen the card guide mounting screws, and
lower the gu ide as far as it will go.
(b)
Tilt the printwheel motor forward, away from
the platen, and install the Alignment Tool.
Make sure the tool is fully seated. Tilt the
motor rearward and verify that the tool clears
the card guide completely. Tilt it forward again.
(c)
Place the carriage servo switch, located near the
top edge of the CAR PWR AMP board, slot 0,
in its off position.
(d)
Loosen the front eccentric on each end of the
carrier assem bly, and set each to its mid-range
(lobe facing rearward) with a 7/16 in. open end
wrench. Retighten the eccentric lock screws.
08 ® SCREW
DRIVER ADJUSTMENT POINTS
333-00'
Figure 3-24b. Printwheel Alignment
MANIFOLD
LEVER
FORWARD---~
ADJUST REAR
ECCENTRIC
(7/16" WRENCH)
TOOL---~
FRONT ECCENTRIC
(BOTH SIDES)
IDLER GEAR MAY BE REMOVED
Figure 3-25. Platen-to-Printwheel Adjustment
3-23
A
I
I
I
I
I
___ -
__ -
-
__ -
-
-
_ _ _ ---1- -
I
----- --
---+ - -- - - - - -- - ---- - - -
SCREW
Figure 3-26. Card Guide Adjustments
3-24
(2)
Alignment Check
3.4.1.4.4 Card Guide Height and Position.
Figure 3-26. Proceed as follows:
Move the carriage as far left as it will go. Tilt the
printwheel motor rearward and verify that .0002" .003" (.005-.076 mm) clearance exists between tabs
C of the tool and the platen surface. Tilt the
printwheel motor forward (away from the platen)
and move the carriage as far right as it will go. Tilt the
printwheel motor rearward again, and check the
platen-to-tool relationship. If the platen adjustment is
within these limits, AND is equal for both ends of the
platen, no adjustment is necessary. If these criteria
are not met, continue with this procedure_
(3)
(1)
Preparation
If the card gu ide is loose from the preceding
adjustment, go on to step (3). If not, remove the
adjustment tool, install a printwheel and a sheet of
paper, and type a series of identical characters along
one line.
(2)
Alignment/Adjustment Check
The bottom edge of the triangular openings (A 1)
must be in line with the bottom lines of a series of
identical characters within .000 in. to .0058 in.
(.00 mm to .13 mm).
Platen Adjustment (Repeat for each end)
Loosen the two rear eccentric slide clamp screws
(AR) and the screw for the rear eccentric itself (AE).
Adjust the rear eccentric, using a 7/16 in. open end
wrench, to bring the platen clearance to within the
limits specified. Tighten the slide clamp screws. Move
the carriage to the opposite end of the platen and
check for proper clearance. Repeat these steps until
the clearances on each end are within the limits
specified, and are equal. Tighten the rear eccentric
slide clamp screws when this adjustment has been
completed, and then tighten eccentric screws.
(3)
Card Guide Alignment/Adjustment
Install the alignment tool on the printwheel motor
shaft, making sure it is firmly seated. The procedure
from this point is slightly different depending upon
which alignment tool is used. (See Figure 3-23.)
(a)
Refer to Figure 3-25. Proceed
(b)
(1)
Preparation
Adjustment Check
All characters should print with equal darkness on
top and bottom all across the print line. Check with a
line of capital "H"s. Refer to the print quality check
(3.4.1.1) and Figure 3-6.
(3)
Tool No. 40795-01:
Raise the card gu ide until its top edge contacts
the undersides of Adjustment Tool Tabs 01
and D2. Gently move the tool slightly from side
to side while raising the card guide until it
contacts the tabs with EQUAL pressure. Hold
the card gu ide firm Iy in th is position, and
tighten the two card guide mounting screws.
Make sure the Platen-to-Printwheel adjustment
(3.4.1.4.2) is correct. I nstall the printwheel normally
used.
(2)
Tool No. 40795:
Push the print hammer into the Hammer Slot
B2 on the tool, and hold it there. Raise the card
guide gently, until its top edge contacts the
undersides of Card Guide Alignment Tabs 01
and 02 with equal pressure. Release the
hammer and, while holding the card guide in
contact with the tool, tighten the two mounting screws.
When this adjustment has been completed, be certain
to perform the Platen Height adjustment (3.4.1.4.3)
and the Card Gu ide adjustment (3.4.1.4.4).
3.4.1.4.3 Platen Height.
as follows:
Refer to
Using a .005 in. plastic shim, check for no-drag shim
clearance between the card gu ide and the ribbon
guide posts on both sides of the carriage. Normally,
this dimension is set by the depth of the ribbon guide
post tabs. Shim drag indicates the card gu ide has
become tilted, in which case its support arms should
be gently reformed to achieve proper clearance
around the ribbon gu ide posts.
Platen Height Adjustment
Loosen the clamp screws on the front eccentric on
each end of the carrier assembly. Turn the eccentrics
as requ ired to obtain the proper print qual ity
uniformly along the length of the platen. Tighten the
clamp screws and recheck the print quality.
Using the .005 in. plastic shim, check fOI no·drag
clearance between the carel gu ide and the platen along
the fu II length of the platen.
3-25
3.4.1.4.5
Ribbon.
(b)
Refer to Figure 3-27. Proceed as
Tool no. 40795-01 :
follows:
(1)
Either 1/4 in. or 5/16 in. ribbon may be used in
making the adjustment with this tool.
Preparation
Remove the ribbon and the printwheel, and rotate
the 40795 Alignment Tool to bring Ribbon Height
Adjustment Slot E to the Top, or rotate 40795-01
Alignment Tool to bring its Slot B2 to the top with
the bottom of the slot to the bottom part of the
ribbon. Install a multistrike carbon ribbon cartridge.
(2)
1/4 in. ribbon:
The TOP EDGE of the ribbon must appear
between the high and low planes of features E 1.
5/16 in. ribbon:
Ribbon Adjustment Check
(a)
The BOTTOM EDGE of the ribbon must
appear between the high and low planes of
features E 2.
Tool. no. 40795:
(3)
The 1/4 in. ribbon can only be used in making
the adjustment with this tool.
Ribbon Adjustment
Adjust the ribbon height eccentric 1/20" as
required to achieve the proper ribbon height by
first loosening the 3/16 in. eccentric lock screw
on the inside of the carriage frame or the
locknut on the outside of the eccentric and
then moving the eccentric "20" with a blade
(a)
1/4 in. ribbon:
The TOP EDGE of the ribbon must appear
through slot E, but not above the top of the
tool.
.oo~
..
J_
.012'
t
RIBl~ON
HEIGHT ECC:ENTRIC
(3.16" WR E NCH F OR LOCK ING SCH [WS)
EI
TOP EDQE
RIBBON (CARBON)
1/4"
RISBO,,"
!VIS"
'1--~-'-
M
/
E2
BOTTOM E06E
E2
(ENLARGED FRONT VIEW)
a.
TOOL
b.
#40795
TOOL #40795 -01
333-006
Figure 3-27. Ribbon Height Adjustment
3-26
screwdriver or wrench, as required. Retighten
the eccentric lock screw.
(b)
Remove the ribbon cartridge. Place a .005 in.
plastic shim between the ribbon lift coil laminations "0" and ribbon base plate pole piece
"C2". Push up on the ribbon base plate tab
"X" so that the grommet "C1" is firmly against
the eccentric "20". Energize the ribbon lift
coils and check for an even .005 in. gap
between the lam inations "0" and the pole
piece "C2". Loosen the 3/16 in. co il mounting
screws and adjust the position of the coils with
respect to the pole piece as required to achieve
these goals. Retighten the mounting screws and
remove the shim.
Recheck the ribbon height (a) as outlined above.
Readjust as required, then recheck the coil adjustment (b) if readjustment of the ribbon height was
necessary.
Figure 3-28. Hammer Adjustments
3.4.1.4.6
Hammer. There are two hammer adjustments:
hammer coil position and armature stop eccentric. These
adjustments are simplified when tool no. 40796 is used, but
they can be performed without it if necessary. Refer to
Figures 3-28 and 3-29.
(1)
Preparation
.045DIA.
The following conditions should be present: power
off, printwheel installed, ribbon removed, and platen
position lever fully forward.
(2)
Adjustment Check (the Platen-to-Printwheel adjustment, 3.4.1.4.2, must be correct before checking
hammer adjustments).
TOOL .40796
Figure 3-29. Hammer Adjustment Tool
To check hammer coil position, first rotate the
printwheel to place one of the larger characters (M,
W, E, etc.) in front of the hammer. Then insert H2 of
tool no. 40796 (see Figure 3-29) between the
armature (A) and the anvil of the print hammer (C),
and push the armature against the hammer coils (F).
This will force the hammer (C) in to nestle the
selected printwheel petal (D) lightly against the
platen (E). Gently rock the printwheel slightly back
and forth, and verify that the petal can move with a
very sl ight drag. Repeat th is check, rotating the
platen and/or moving the carriage each time, to check
the entire printing surface.
(3)
Hammer Coil Adjustment
Loosen the hammer coil mounting screws (G) and
reposition the coils to obtain the proper relationship
between the hammer and the platen as noted above.
Retighten the screws. Recheck the armature stop
eccentric adjustment.
If tool no. 40796 is not available, hold the armature
against the hammer coils while pushing the hammer
against the printwheel to obtain the relationship
noted above, and measure the clearance between the
armature and the hammer anvil. It should be .073 in.
to .083 in. (1.85 mm to 2.10 mm).
(4)
To check the armature stop eccentric, hold the
armature (A) against the hammer coils (F), and check
the clearance between the armature and the stop (8).
There should be .042 in. to .048 in. (1.07 mm to 1.22
mm) clearance, or H3 of tool no. 40796 should fit
with very light resistance.
(5)
Armature Stop Eccentric Adjustment
Loosen the lock nut slightly, and turn the screw until
the desired clearance is obtained. Prevent the screw
from turning as the lock nut is retightened.
3-27
3.4.1.4.7
(1)
Carriage Home (Figure 3-30)
ment tool, turn off power, move the carriage to the
right, restore power, and cycle the pri nter through
the RESTORE sequence. When this adjustment is
being changed, try to ach ieve a clearance as close as
possible to tool Tabs F 1/F2 (either tool). Tighten the
eccentric clamp screw when the adjustment is complete.
Preparation
With power applied to the printer, initiate a Restore
sequence.
(2)
Adjustment Check
3.4.1.5
(a)
BOTTOM-FEED PAPER CHUTE (Figure 3-31)
Tool No. 40795:
This is an optional feature, not found on a" HyTerms.
I nsert the tool between the left side of the
printer's main frame casting and the carriage
frame, just above the carriage home sensor. The
maximum clearance between tool Tabs F1/F2
and the printer assemblies should be .017 in.
(.43 mm).
(b)
(1)
(a)
Make sure the following adjustments are correct:
Paper Feed Rollers
Platen Position
Platen Height
Card Guide
Tool No. 40795-01:
I nsert the tool between the left side of the
printer's main frame casting and the carriage
frame, just above the carriage home sensor.
Using tool tabs F1-F5, check for proper clearance as follows:
(b)
(2)
Tabs Fl/F3 should pass (go)
Tabs F4/F5 should not pass (no go)
(3)
Preparation
Turn off power. Raise or remove the access
cover, and remove the platen. Remove any
paper.
Adjustment Check
(a)
The top edge of the paper chute (B) must be in
line vertically within .030 in. (.76 mm) of the
top 45-degree bend of the card guide (C). This
must not vary more than .030 in. (.76 mm)
over the entire length of the carriage travel.
(b)
There should be .040 in. to .060 in. (1.0 mm to
1.5 mm) clearance between the paper chute and
Carriage Home Sensor Flag Adjustment
Unlock the carriage home sensor flag eccentric, and
adjust it to move the flag LEFT for "not enough"
clearance, or RIGHT for "too much" clearance. After
each movement of the eccentric, remove the align-
3.4.1.2.2
3.4.1.4.2
3.4.1.4.3
3.4.1.4.4
~CARRIAGE FRAME
FRONT BEARING
CASTING
(LEFT SIDE)
TOOL
333-007
CARRIAGE HOME SENSOR FLAG
Figure 3-30. Carriage Home Adjustment
3-28
#
40795 - 01
the front pressure rollers. Clearance should be
equal at both ends.
(c)
The paper-out bail should touch the chute at
both ends.
INUNE
(3)
-.030"
Paper Chute Adjustments
NOTE
If any of these adjustments are performed, be certain to check the bottomfeed paper-out switch adjustment
(3.4.6.2).
(a)
To adjust the height of the chute, loosen screws
(D) and (F), position the chute properly, and
tighten screws (D). Then perform adjustment
(b).
(b)
To adjust the paper chute/pressure roller clearance, loosen screws (F), position the chute
properly, and tighten screws (F).
(c)
To adjust the paper-out bail, loosen the setscrews in the hubs at both ends of the bail,
form the bail slightly, if needed, and tighten the
setscrews.
3.4.2
Figure 3-31. Paper Chute Adjustment
and any other time that power supply problems are
suspected. The tolerances given in the following procedures
are for adjustment purposes only. That is, if a voltage is
slightly outside the limits listed, but the HyTerm is
operating properly, no adjustment is required. On the other
hand, if a voltage is within the specified limits, but at the
fringe, and power supply problems are suspected, perform
the +5 voltage adjustment. The use of a digital voltmeter is
recommended because of the more precise readings obtainable. Proceed as follows:
Control Panel
The only adjustment on the control panel is a volume
control adjustment for the audible alarm.
3.4.2.1
VOLUME CONTROL
+5V Adjustment Procedures: (Both Boschert and LH R
Power Supplies)
Remove the access cover from the HyTerm. '-'\lith a small
screwdriver, turn the adjusting potentiometer until the
desired volume is obtained. The potentiometer is accessible
through a hole in the right side of the control panel near
the buzzer. To sound the audible alarm after each adjustment, operate the RESET key and then attempt to print a
character. The alarm will sound for a cover-open error.
3.4.3
(1)
Unplug the HyTerm from its power source. Raise or
remove the access cover, remove the platen, and
remove the top cover (3.1.2).
(2)
Remove the HCURL board (if installed) from slot (F)
and install a circuit board extender into slot (F).
(3)
Plug the HyTerm power cord into the wall outlet.
Power Supply
The most common adjustment procedure of the power
supply is the +5 voltage adjustment. In the Boschert power
supply, there is one additional adjustment procedure
following the replacement of the U3 opto-coupler. On the
LH R power supply, there are two additional adjustment
procedures - overvoltage protection, and current limit.
WARNING
When the HyTerm is connected to a power
source, line voltage is present at the PO WE R
switch terminals. To avoid a dangerous
shock when power is applied with top cover
removed, keep your fingers away from the
POWER switch terminals.
All voltages should be checked whenever the power
supply or one of its components is replaced, when one of
the voltage regulator ICs on the HPRO board is replaced,
3-29
Turn on the power and measure each voltage.
Spade Lugs *
T13-T14 *
T15*
T12*
T11 *
(10) Turn off the power. Replace the bottom plate. Tilt
the HyTerm back down onto its feet, remove the
board extender, replace the top cover and the platen.
Test the HyTerm for proper operation.
Extender Pins
Pins
Pins
Pins
Pins
1-2
5-6
41-42
23-24
GND
+5.0V ± .1V
+15.25V ± .75V
-15.25V ± .75V
3.4.3.1
Procedures following replacement of U30pto-coupler:
*If the machine is equipped with mother board 46080-XX,
these voltages may be measured at the dc power spade lugs
on the right side of the mother board.
(4)
(5)
Boschert Power Supply, Part No. 26021-XX
If the +5 volt supply is correct and some other supply
is not, a malfunction is present and must be corrected. If the +5 volt supply is not correct, proceed
with step (5).
(1)
Follow the procedures (1-7) for removal of power
supply (3.3.2).
(2)
Fasten one voltmeter probe on TB1-2 (GND) and the
other probe at the junction of R35, R36, and U3-2.
(See Assy. Dwg. 26021-XX for exact location.)
Turn off the power. Tilt the HyTerm up so that it is
resting on the rear edge of its bottom cover.
WARNING
CAUTION
In the following steps, be very careful not to
touch any part of the power supply, because
extremely high voltages (200-300 volts) are
present.
When tipping the HyTerm up, be certain
to use a flat surface, with no foreign
objects in the way. Any small objects
could cause pressure to be applied to the
rear heat sinks, which are mounted on the
power amplifier boards. Excess pressure
on these boards could damage the boards
and/or the mother board.
(3)
Turn on the power.
(4)
The voltage across R35 is directly proportional to the
resistance. The value of R35 may vary from 680
ohms to 2.4K ohms, 1/4 Watt 5%.
CAUTION
Whenever the HyTerm is tilted up in this
manner, hold on to it with one hand to
prevent it from falling over.
(6)
(7)
Remove the screen-I ike bottom pan from the HyTerm
by loosening the rear three screws, removing the
remaining five screws, and lifting the bottom pan off
the machine.
Fasten the voltmeter
measuring point.
(a)
Increase the resistance of R35 if the voltage
drops below 1 volt when the +5V output is ~
amps (fully loaded).
(b)
Decrease the resistance of R35 if the voltage
exceeds 2 volts when the +5V output is 2 amps
(minimum load).
probe firmly to the +5V
(5)
WARNING
3.4.3.2
In the following step, be very careful not to
touch any part of the power supply, because
extremely high voltages (200 - 300 volts) are
Turn on the power. Using a non-metallic screwdriver,
adjust the power supply potentiometer to provide +5
volts ±.1 volt.
(9)
If any 15 volt measurement is still outside its
tolerance after the +5 volt supply has been adjusted
properly, the source of the problem must be located;
either the power supply is defective, or some printer
malfunction is causing an unusual current drain. A
current foldback condition in any supply will affect
the other outputs as well.
LHR Power Supply, Part No. 400062-01
These adjustments are performed at the factory and
under normal conditions do not require field adjustment.
These adjustments may be required if a problem is
suspected or a component in the power supply has been
replaced.
present.
(8)
After resistance of R35 is corrected, proceed to steps
(1-5) of replacement of power supply (3.3.2).
Overvoltage Protection:
3-30
(1)
Disconnect the power supply outputs from the
terminal and connect a dummy load to the +5V
output which draws approximately 1 amp.
(2)
While monitoring the +5V output, adjust potentiometer R22 clockwise and note the maximum voltage
between -14mV and -22mV. Pins 1 and 2 are about 1mV
lower than the others due to the repeat circuitry tied to
these lines. A leaky keyswitch will load the encoder input
line causing a greater voltage drop. Also, the encoder line in
question will be electrically noisy if looked at with an
oscilloscope.
obtainable (after which the overvoltage circuit takes
over and causes the output to drop). This should be
between +5.5V and +6.3V, preferably around +6.0V.
(3)
Adjust potentiometer R23 on the control module
(the small circuit board attached to the power
supply's main circuit board) clockwise to trigger the
overvoltage circuit at a higher point, or counterclockwise for a lower point.
Normally, the greater voltage drop can be seen immediately after power up, but occasionally power may have to
be applied for up to an hour to exhibit the leakage
problem.
NOTE
After identifying the encode line with the defective
keyswitch, all of the keyswitches common to that line
should be replaced. See 3.3.4.1 for keyswitch removal.
If the output reaches +6.3V before triggering
the OVP circuit, the SCR "crowbar" circuit
may trigger, requiring removal of the input
power before the power supply can restart.
If this occurs, turn off power, turn pots R23
on the control module and R22 both
counterclockwise slightly, restore power,
and continue the test as described.
3.4.5
Before making any adjustment, be sure that the top
cover fits the bottom cover properly, and that the access
cover fits the top cover properly and is tight. Adjust and/or
form the access cover clamp springs (replace if necessary) to
tighten the access cover. If switch adjustment is still
necessary, loosen the cover-open switch operating bracket
(fastened to the inside lower edge of the access cover),
move the bracket up or down slightly, and retighten the
lock screw. Check the adjustment by making sure the
switch operates each time the access cover is opened or
closed.
Current Limit:
(1)
This adjustment should be made with the input
voltage at a nominal value (115V or 230V) - not at
either of its extremes.
(2)
The outputs should be loaded so that the power
supply delivers about 320 watts of total power for no
longer than 30 seconds while making this adjustment.
(3)
Adjust potentiometer R 19 unti I the output begins to
drop off at the 320 watts total power point.
3.4.4
3.4.6
Paper-Out Switch
The procedure for adjusting the paper-out switch varies,
depending upon whether the standard top-feed or the
optional bottom-feed paper supply is used.
Keyboard
The only keyboard adjustment is the positioning of the
keyboard for proper top cover fit. This is normally required
only when the keyboard has been removed or when a
different top cover is installed. This adjustment entails
trial-and-error positioning of the keyboard followed by
installation of the top cover. See 3.3.4 for details.
3.4.4.1
Cover-Open Switch
3.4.6.1
TOP-FEED
This switch is functional only when a forms tractor or
pin-feed platen is used. When a friction-feed platen is used
(without forms tractor), the switch is held in its nonoperated (paper in) position by the paper release lever's
being in its rearward position. When the paper release lever
is moved to its forward position, the switch operating
mechanism is unlocked and allowed to sense the paper-out
condition.
KEYSWITCHES
One of the failure modes of the Keyboard is a leaky
output of the keyswitches. This failure produces intermittent operation of the keyboard by holding one of the
encoder inputs (U3) low. With one input low, only the
keyswitches that have that line in common will function. In
this case, one of the functioning keyswitches is defective.
Before starting th is adjustment, be certain that the Paper
Feed Rollers adjustment (3.4.1.2.2) and the Platen Position
(3.4.1.4.2) and Platen Height (3.4.1.4.3) are correct.
Perform the adjustment with the platen installed and the
paper release lever in its rearward position (pressu re
applied). Referring to Figure 3-32, proceed as follows:
Even though this failure mode is intermittent, it may be
isolated when the keyboard is functioning. A leaky keyswitch can be identified by measuring the voltage at the
encoder inputs (pins 1 through 13 on U3) with respect to
+5V using a digital voltmeter. Typically, the meter will read
(1)
3-31
Using a .050 in. Allen setscrew wrench, loosen the
setscrew (1) in the bell crank on the end of the
paper-out bail pivot shaft (2). The front edge of the
PLATEN
Figure 3-32. Paper-Out Switch Adjustment
Before adjusting the bottom-feed paper-out switch,
make sure the Bottom-feed Paper Chute (3.4.1.6) is
adjusted properly.
bail should touch the platen surface squarely within
.003 in. (.08 mm). [A gap of .010 in. (.25 mm)
maximum due to bowed paper-out bail is permissible.J If necessary to adjust, loosen the setscrew (3)
at either end (or both), adjust, and tighten the
screw(s).
(2)
Loosen the switch mounting screws (4), and adjust
the switch to transfer when the bail is .010-.020 in.
(.2-.5mm) away from the platen. Tighten the screws.
(3)
Move the bail back away from the platen fully. The
bail legs must bottom against the printer "comb"
frame, and not against the switch. If necessary, form
the switch arm to allow the switch to transfer sooner,
and repos ition the switch to obtain the proper
adjustment as noted in step (2).
(4,
The paper-out switch should transfer when the paper-out
bail is .025-.040 in. (.63-1.0 mm) away from the front
paper chute. Loosen the switch mounting screws and
reposition the switch to obtain this adjustment. Tighten the
screws. If adjusting the switch limits the movement of the
paper-out bail to less than .100 in. (2.5 mm), form the
switch arm to allow the switch to transfer sooner, and
reposition the switch to obtain the proper adjustment.
3.5
There are two methods used to identify components
within the HyTerm. The first is an extension of the
reference designator system used to identify replaceable
modules (Section 3.3). The second is a coordinate system
used to identify components on the plug-in circuit boards.
Also, closely related to component identification is the
location of connectors and the numbering of connector
pins.
Remove the platen, and move the bail rearward until
its legs come within .030 in. (.76 mm) of the comb.
Hold the bail in this position and rotate bellcrank (5)
until its ear (6) rests against the actuator lever arm
(7). Tighten setscrew (1). After tightening the screw,
the shaft (2) should pivot freely with .005 in.
(.13 mm) maximum end play. Install the platen,
move the pressure release lever back and forth several
times, and stop with the lever in the rearward
position. There must be at least .090 in. (2.3 mm)
clearance between the bai I and the platen.
3.4.6.2
COMPONENT IDENTIFICATION
3.5.1
Reference Designator System
The reference designator system is used to identify
individual components mounted to the printer frame, as
well as components on the control panel, in the power
supply, and on the keyboard. Table 3-3 defines the class
letters used on schematics and wiring diagrams to refer to
various items. On the control panel and keyboard, the
reference designators for each component are etched on the
circuit board. To locate a particular component in the
power supply, you will first need to locate it on the power
supply assembly drawing, and then find it on the power
supply.
BOTTOM-FEED (OPTIONAL)
This switch is functional only when the enable/override
switch, mounted to the left of the front carriage rail, is in
the ON position (toward the rear). When the enable/
override switch is 0 F F, it overrides the paper-out switch,
making it non-functional.
3-32
NOTE
Table 3-3. Reference Designators
When locating components on the
HPRO 1 board, note that the alphabetic
coordinates are opposite that shown here.
"A" is at the plug end of the board.
Designator
Description
A
B
C
CR
OS
Assembly
Fan (blower)
Capacitor
Diode (including bridge rectifiers, LEOs)
Alarm (buzzer)
Pin no. 1 of each IC is easily identified from the bottom
(solder) side of the board by its square solder pad. This
lessens the chance of errors in counting pin numbers.
E
F
FL
J
L
Individual terminal
Fuse
Filter
Jack (connector, stationary portion)
Inductor (coil)
The mother board, the keyboard, and the control panel
circuit boards do not use the coordinate system because of
the small number of components involved. These boards
use standard reference designators, which are silkscreened
or etched onto the board, and referenced on the
schematics.
P
Plug (connector, movable portion)
Transistor
Resistor
Resistor, temperature-sensitive
(thermistor)
Q
R
RT
3.5.2
S
Switch
T
TB
TP
U
VR
Transformer
Terminal board
Test point
Integrated circu it
Voltage regulator (zener diode)
W
X
Cable
3.5.3
Pin Numbering
Industry standards are followed for pin numbering of
integrated circuits. Pin identification for all integrated
circuits, including metal-can ICs, can be found in Section 4.
3.5.3.1
DISCRETE SEMICONDUCTORS
Pin identification for most discrete semiconductors is
presented in Figure 3-34.
NOTE
Circuit board socket, fuseholder
Components in Figure 3-34 that are listed by
Diablo part number should not be replaced
by standard industry types. They should be
ordered by Diablo part number because in
some cases there are more stringent tolerances for the Diablo parts, and restrictions as
to approved manufacturers, due to reliability
and functional differences.
Coordinate System
Components are identified on the logic drawings as to
type and location. The location information consists of a
letter and a number, each representing coordinates on the
circuit board. Refer to Figure 3-33. Letters are printed on
the circuit board in the approximate center of the area they
refer to, whereas numbers appear at the beginning of their
respective area. As an example, to locate resistor E62,
follow the liE" row horizontally to where it intersects the
"60" column. Below the "60" and a little to the right (at
"62") you will find resistor E62. Coordinates given for IC
chips are the approximate location of pin no. 1. Coordinates for other "horizontally mounted" components (as in
Figure 3-33) refer to the location of the leftmost lead.
Letter coordinates for vertically mounted components that
overlap rows usually refer to the row in which the largest
portion of the component is located.
3.5.3.2
CIRCUIT BOARDS AND MOTHER BOARD
Pin numbering of circuit boards that plug into the
left-hand half of the HyTerm is shown in Figure 3-33.
Circu it boards on the right side are mirror images, so pin
no. 1 is on the left side; pin no. 56 on the right. This is also
shown in Figure 3-35a and b.
The numbering of all mother board pins is shown in
Figure 3-35a and b. Signal names for all points, including
power connections, are shown on schematic no. 40614 and
46080, respectively.
3-33
IC PIN NO.1
....---···-:,·~·_;i;":·~:::i
L.:i...:;;.....;;;c...;;.;.....;............
A
HPR02
ASSY
",,~\':~ "+~
.
N<22.3 7Q 4 - [ ...•:.,:'. ::.:.• J:.:
REV [_ J
~
1
B
~
o
w
W
~
~
E
E~
:;::
·+~a.IP-::::
~
. -:: : : : : : : : : F
e
"~,
' .
,.
(COMPONENT SIDE) /
PIN 55 OTHER SIDE
(SOLDER SIDE)
""
KEYBOARD CABLE
CONNECTOR
DIFFERENT FOR EACH BOARD)
\"
PIN 1 OTHER SIDE
...
,.
PRIMARY CONNECTOR (MOTHER BOARD)
Figure 3-33. Circuit Board Component Location and Pin Numbering
I
OUTLINE (BOTTOM VI EW)
DIABLO PART NUMBER
INDUSTRY TYPE NUMBER
EMITTER
180013-01
180013-01
42190-29
42190-30
USE SJ7280
USE 2N6545
USE SJ7280
42190-71
CPS1540B (Matched Pair)
SJ6211 (Matched Pair)
SJ7280
SJ7280 (Matched Pair)
2N6306 (SJ7280)
2N6308
2N6544
2N6545
42220-01
42190-72
10422-01
10443-01
10444-01
2N2219A
2N3439
2N3725
2N5320
2N5322
EMITTER¥SE
COLLECTOR
10105
42190-26
13013
42190-21
USE MPS-U60
42190-28
42190-60
2N3644
2N4126
2N4401
MPS-A43
MPS-A93
MPS5172
MPS6516
EMITTERW COLLECTOR
10105
2N3644
10445-01
10177-02
13063
13064
42190-27
42190-70
13007
2N6103
TIP31A
TIP41A
TIP42A
TIP47
TIP49
TIP125
14005-01
MV5753
42190-43
C122F (50316)
42190-25
MPS-U60
BASE
0
0
0
0
(COLLECTOR CONNECTED TO CASE)
EMITTER~E
COLLECTOR
o
o
0
0
0
B~SE:\
0:
0
COL?
~
I
EMITTER
C A T H O D E t r ANODE (+1
LED
/CATHODE
I@]~
:~ANODE
+ - - GATE
SCR
CQ[J
..,--COLLECTOR
.-BASE
·-EMITTER
Figure 3-34. Semiconductor Lead Identification
3-35
TI3 TI2 Til TlO T9 T8
IrOO 0
20
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T7 T6 T5 T4
T3 T2
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2 1 - - - - - - - - - - - - - - - - , 5 6 _ _ _ _ _ _~
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oolTI
Figure 3-35a. Mother Board Pin Numbering (No. 40614)
20
T9T8
I 3'
T7 T6 T5 T4
4
TI~
Tl4
Tl3
Tl2
Til
::8
: II
G
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COMPONENT SIDE (TOP) ~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _----,
litill
D
11
110 11
c
~ ~I
A
I
F
III
1
00
T9T8
20
I
I
II i
B
I
J4
J3
1____ lfl
E
1
II::_:~_J
III
I
I 3
I
I
J2
n
4
I~~
~---
ODD 0
I
T7 T6 T5 T4
Figure 3-35b. Mother Board Pin Numbering (No. 46080)
3-36
0
0
0
0
0
0
-15V
+15V
GND
GND
+~v
oTt
3.5.3.3
3.5.3.4
KEYBOARD CABLE
Pin numbers are shown in Figure 3-36. Pin numbers and
signal names are the same at both ends. Odd-numbered pins
are on the top (component side) of the keyboard and the
back (solder side) of the HPRO board; even-numbered pins
are on the bottom (solder side) of the keyboard and the
front (component side) of the HPRO board. Signal names
are listed in Table 3-4.
The two control panel cables are permanently mounted
to the control panel circuit board. The control panel
schematic (23708 for' HPCPL or 23710 for HPCPN) shows
the wiring of both the circuit board and the cables. Note
that cable W2 is stamped with a "2" and plugs into socket
J2 on the HPRO board, and that cable Wl is stamped with
a "3" and plugs into socket J3 on the HPRO board. The
sockets are the same as 16-pin integrated circuit sockets,
and the pins are numbered the same. Pin no. 1 is identified
in several ways: by the square solder pad on the solder side
of both the HPRO board and the HPCPL/HPCPN boards,
by the angle or dot on one corner of the sockets on the
HPRO board, and by the red-painted edge of the flat ribbon
cable. Numbers progress from 1 to 16 counterclockwise
when viewed from the component side of any circuit board;
clockwise when viewed from the solder side. Figure 3-37
shows the numbering of the pins on the end of the control
panel cables.
Table 3-4. Keyboard Signal rJames
Pin No.
I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Signal Name
+5V
SIGNAL GND
+5V
SIGNAL GND
-FKY4
-FKY5
-FKYl
-FKY2
+BUSY
-FKY3
-12V
+KYSTB
·DATAO
CONTROL PANEL
Function
Shift
Control
Upper Case Only
Local
Signal names for these cables are shown on the control
panel schematics and on the Signal Cable Interconnection
Diagram, no. 23732.
Break
-DATA7
-DATA6
-DATAl
-DATA5
-DATA2
-DATA4
-DATA3
Pl
HPRO-BOARD END
Figure 3-37. Control Panel Cable Pin l\Jumbering
P2
KEYBOARD END
COLORED STRIPE
Figure 3-36. Keyboard Cable
3-37
3.5.3.5
\
EIA CABLE
3.5.3.6
Complete information on the wiring of the EIA cable is
given in Figure 3-38. Note that the male EIA connector is
shown; the female connector on the modem or acoustic
coupler is a mirror image of this. Note also that the J1
connector on the HPRO board is a mirror image of the P1
connector shown.
POWER SUPPLY
Figure 3-39 shows the wiring of the power supply cable
and the connections to the power supply. Note that there
are some unused pins in the female connector (P1), but that
the J1 connector on the mother board that mates with it
has all pins connected in some manner. The mother board
schematic, no. 40614, lists all power connections.
POLARIZING KEY
14
0
15
0
16 0
17 0
18 0
19 0
20
21 0
22
23g
24 0
25
0
Data Terminal Read
AA
I
2
3
BA
BB
CA
CB
CC
AB
CF
4
5
6
7
0
WIRING LIST
EtA
Pl
COLOR
6
DD
DO
DO
Received Line
Signal Detector
8
90
100
110
120
130
7
DO
DO
GREEN
RED
ORANGE
YELLOW
BROWN
BLUE
PURPLE
WHITE
Pl
BLACK
I
2
:3
4
6
5
7
4
5
9
8
6
1
8
20
23
I
10
3
2
*
* NORMALLY
SPECIAL ORDER ONLY, SLATE WIRE
CUT OFF AT JACKET
SLATE
EIA
Figure 3-38. EtA Cable Pin Identification
TBl
®
®
2
POWER
3
4
SUPPLY 5
6
t
CAC
AC
TO
FAN
'
WH)TE
8
9
@
@
@
@
@
®
®
®
WHITE
BLACK
(2)
(2)
+5V l.J
GND A.B
GND C
+15V E.K
-15V P,R
NOT
USED
(NOT
BCAC}
WHITE
Pl
USED)
AC
FROM
POWER
SWITCH
A
@
C
©)B@
b~d
@
©8~
b c9
@
Figure 3-39. Power Supply Connections
3-38
SECTION 4
SCHEMATICS AND REFERENCE INFORMATION
4.1
INTRODUCTION
For example, a NAND gate may appear on a logic
diagram as either a positive logic AND function with the
output inverted (NAND), or as a negative logic OR function
with the inputs inverted (NOR). See Figure 4-1. This
practice runs contrary to some logic drawing standards,
which require the use of the NAND symbol for both
functions. But, in Diablo Systems diagrams, different
symbols are used to distinguish between the two functions
because the functional elements are considered to be more
relevant to the design theory than symbol ic representation
of the kinds of devices used.
This section contains information on logic symbology
and drawing conventions used in the HyTerm schematics
and logic diagrams, and information on the integrated
ci rcu its used.
4.2
FUNCTIONAL LOGIC
The HyTerm logic diagrams are primarily intended for
use by field service personnel as troubleshooting aids. As
such, the first responsibility of a set of logic diagrams is to
illustrate a design's principles of operation. For this reason,
Diablo Systems logic diagrams emphasize the functions
performed by the logic elements rather than the kinds of
devices used to implement the functions.
AND
A
B
C
FUNCTION
I
}
(POSITIVE LOGIC
F
C
a)
(NEGATIVE LOGIC
B
C
F
L
L
L
H
H
L
L
H
L
H
L
H
H
H
L
H
L
L
H
H
H
L
H
H
L
H
H
H
H
H
H
L
NAND)
OR FUNCTION
A
B
A
F
NOR)
H = +5V
Figure 4-1. Example of Functional Logic
4-1
L=QV
4.3
SIGNAL NOMENCLATURE
Sometimes a signal serves as the input to both positive
logic and negative logic elements. Ordinarily in such cases,
the sign preceding the signal name agrees with the active
level indicated at the output of the logic element that
produced the signal.
The active level of each logic signal is assigned a
descriptive name. A signal is considered active when it
either causes or represents some logic event that is
sign ificant to the progress of an operation. Consequently,
the name given a signal usually provides one of two kinds of
functional information:
(1)
Signal names appearing in the text are printed in all
capital letters to distinguish them from functions being
performed. For example, '-RESET' refers to an actual signal
name, whereas 'Reset' refers to the reset operation in
general.
Describes the effect that the sign ai's active level has
on the logic it feeds; for example, -ENABLE INP
allows data to be brought into the printer
microprocessor.
4.4
LOGIC SYMBOLOGY
Represents a condition or event that develops elsewhere in the logic; for example -FUN SWITCH 4 is
the name of the signal that is active whenever the
number 4 function switch (FORM FEED) is
operated.
The logic function symbols used in Diablo Systems logic
diagrams conform closely to those set forth in MI LSTD-806. Most small scale integration (SSI) circuits are
represented by function symbols. Medium scale integration
(MSI) devices, such as shift registers and counters, may be
represented by rectangles with functional labels.
A plus sign (+) or a minus sign(-) generally precedes
each signal name to identify which of the two voltage levels
used in the logic system is considered to be that signal's
active level. The + sign represents the relatively higher logic
level and the - sign, the relatively lower level. (This means
relatively higher or lower with respect to each other; the
signs do not always indicate signal polarity with respect to
ground.) For example, if -RESET is low (0 volts), it means
Reset is active; if -RESET is high (+5 volts), the Reset
function is inactive. If +USART INTER RUPT is high, it
means the USART has received a character from the data
link and is ready to forward it to the MPU; if +USART
INTERRUPT is low, it means the USART has not received
any data from the data link that has not already been
accepted by the MPU.
Generally, a circle drawn at an input to a symbol
indicates that the input is active when it is low (OV
nominal). The absence of a circle at an input means that
input is logically active when it is high (+5V nominal). The
presence or absence of a circle at a symbol output has
similar meanings for the active level of that output. Usually,
all logic symbols are drawn with inputs on the left and
outputs on the right. Symbols for all integrated circuits
used are shown in the IC data contained in this section.
(2)
4.5
INTEGRATED CIRCUITS
Table 4-1 summarizes all integrated circuits used in the
HyTerm. All of the ICs listed were used at some point in
the HyTerm manufact.uring process, but all wi II not be
found in current production machines. Further information
is contained in the following several pages. IC data on the
following pages is arranged the same order as listed in
Table 4-1, so the table can be used as an index when
looking for data on a particular IC.
The actual voltage levels represented by the signs will
depend on the logic family being used. For example, in
TTL circuits, the signal identified by -RESET is active when
it is at OV (nominal) and inactive at +5V (nominal).
Table 4-1. Integrated Circu its
Digital:
Type
833
7400
74 LSOO
7402
74LS02
Description
DTL Dual 4-lnput Expander
TTL Quad 2-lnput NAND Gate
TTL Quad 2-lnput NAND Gate, Low Power Schottky
TTL Quad 2-lnput NOR Gate
TTL Quad 2-lnput NOR Gate, Low Power Schottky
4-2
Diablo
Part No.
42191-31
10134
13077
10135
42350-01
Table 4-1. Integrated Circuits (Continued)
Type
Descri pti on
Inverter
Inverter, Low Power
Inverter, Low Power Schottky
Inverter, Open Collector
I nverter Buffer/Driver
Diablo
Part No.
7404
74L04
74LS04
7405
7406
TTL
TTL
TTL
TTL
TTL
Hex
Hex
Hex
Hex
Hex
7407
7408
74LS08
7410
74LS10
TTL
TTL
TTL
TTL
TTL
Hex Buffer/Driver
Quad 2-lnput AND Gate
Quad 2-lnput AND Gate, Low Power Schottky
Triple 3-lnput NAND Gate
Triple 3-lnput NAND Gate, Low Power Schottky
10391
10119
10210
10133
13080
7411
7414
7420
74H21
7426
TTL
TTL
TTL
TTL
TTL
Triple 3-lnput AND Gate
Hex Schmitt-trigger Inverter
Dual 4-lnput NAND Gate
Dual 4-lnput AND Gate
Quad 2-lnput NAND High-Voltage Interface Gate
10301
10299-01
10125
10319
10120
7432
7442A
74LS42
7451
7453
TTL Quad 2-lnput OR Gate
TTL BCD-To-Decimal Decoder
TTL BCD-To-Decimal Decoder, Low Power Schottky
TTL Dual AND-DR-INVERT Gate
TTL 4-wide Expandable AND-DR-INVERT Gate
7474
74LS74
7483A
74LS83
7486
TTL
TTL
TTL
TTL
TTL
3101/7489
8599/74S189
3101 A/74S289
TTL 16 x 4-Bit RAM, Open Collector
7492A
7493A
TTL Divide-by-12 Counter
TTL 4-B it Binary Counter
10193
10334
13088
10304
10141
74107
74LS107
74145
74148
74155
TTL
TTL
TTL
TTL
TTL
10305
10389
10172-29
10394
10194
74LS155
74161
74163
74LS164
74170
TTL Dual 2:4 Decoder, Low Power Schottky
TTL 4-Bit Synchronous Binary Counter
TTL 4-Bit Synchronous Binary Counter
TTL 8-Bit Shift Register, Low Power Schottky
TTL 4 x 4-Bit RAM
13090
10335
10356
42392-01
10195
74LS170
74174
74LS174
74LS175
74195
TTL
TTL
TT L
TTL
TTL
13092
10336
10393
42363-XX
10191
Dual 0 Flip-flop
Dual 0 Flip-flop, Low Power Schottky
4-Bit Binary Full Adder
4-Bit Binary Full Adder, Low Power Schottky
Quad 2-lnput Exclusive OR Gate
TTL 16 x 4-Bit RAM, Three-state
TTL 16 x 4-Bit RAM, Open Collector Schottky
Dual J-K Master-Slave Flip-flop
Dual J-K Master-Slave Flip-flop, Low Power Schottky
BCD-to-Decimal Decoder/Driver
8-Line to 3-Line Priority Encoder
Dual 2:4 Decoder
4 x 4-Bit RAM, Low Power Schottky
Hex D Latch
Hex D Latch, Low Power Schottky
Quad 0 Flip-flop, Low Power Schottky
4-Bit Parallel-Access Shift Register
4-3
10136
10389
10209
13145
10460
10302
10146
13083
10280
10192
10139
13085
10140
13086
10303
Table 4-1. Integrated Circuits (Continued)
Type
Descri pti on
8-Bit Addressable Latch
8- Bit Add ressable Latch, Low Power Schottky
Quad 2-lnput Multiplexer/Register
Quad 2-lnput Multiplexer/Register, Low Power Schottky
Hex Bus Driver, Three-State
Diablo
Part No.
9334/74259
74LS259
74298
74LS298
74367
TTL
TT L
TTL
TTL
TTL
74LS367
8080A
8205
25LS138
8212
TTL Hex Bus Driver, Three-State, Low Power Schottky
MOS 8-Bit Microprocessing Unit
TTL 3-Line to 8-Line Decoder
TTL 3-Line to 8-Line Decoder
TTL 8-Bit I/O Port, Schottky
13096
42338
42335
42403
42337
8216
8224
8228
8251
82S115
TTL 4-Bit Bi-directional Bus Driver
TTL Clock Generator/Driver, Schottky
TTL Bus Driver/System Controller, Schottky
MOS USART
TTL 512 x 8-Bit PROM, Three-State
42339
10215
42331
42336
8316A
8708
2111
SW-10667
TTL-117
TTL 2K x 8-Bit ROM, Three-State
MOS 1 K x 8-Bit E R OM, Three-State
MOS 256 x 4-Bit Static RAM, Three-State
DTL Pulse Generator
Phototransistor Opto-Isolator
42329
42334
14027
42168-XX
MCT2
MM5873
SW-20314
Phototransistor Opto-Isolator
Keyboard Encoder/Decoder/Processor
MOS Keyboard Decoder/Encoder
41290-01
42191-33
14026
Description
Diablo
Part No.
10339
13094
10196
13095
10197
Interface:
Type
75150P
75154
75451
Dual Line Driver
Quad Line Receiver
Dual AN D-Gate Peripheral Driver
10353
10354
10181
Linear:
Type
Description
Diablo
Part No.
LM319
LM310H-5
LM320H-12
LM341 P-12
LM723CD
Dual High-Speed Voltage Comparator
Voltage Regulator, 3-Terminal
Voltage Regulator, 3-Terminal
Voltage Regulator, 3-Terminal Positive
Voltage Regulator
10168
42155-05
42155-12
42154-12
10321
LM733C
MC1741SCP1
72747
72747
72748
Differential Video Amplifier
Op Amp, High Slew Rate
Dual Op Amp, General Purpose
Dual Op Amp, Selected
OpAmp
10124
10167
10165
13072
10166
4-4
Table 4-1. Integrated Circuits (Continued)
Miscellaneous Special Purpose:
Type
Diablo
Part No.
Description
42191-32
10190
13060
10239-01
10761
13044
NPN Transistor Array
Quad FET
Digital-to-Analog Converter
Resistor Network, 1 K (15 resistors)
Resistor Network, 1K (13 resistors)
Resistor Network, 10K (8 resistors)
CA3086
8041
1408L-6
Part No. 42191-31
Dual 4-lnput Expander
Type 833
Logic Symbol
9
10
12
13
This device is an expander element which allows
increased fan-in for buffer units.
11
2
3
5
4
6
VCC-14, GND-7
TTL Quad 2-1 nput NAND Gate
TTL Quad 2-1 nput NAND Gate, Low Power Schottky
Part No.1 0134
Part No. 13077
Alternate Symbol
Logic Symbol
Type 7400
Type 74LSOO
Truth Table
A
L
H
L
H
A~12
II Y
B 13
VCC-14, GND-7
Loading:
Inputs
Outputs
(083-030)
1 Unit Load (.2 for 74LSOO)
10 Unit Loads (5 for"74LSOO)
4-5
B
Y
L
L
H
H
H
H
H
L
TTL Quad 2-lnput NOR Gate
Part No. 10135
Part No. 42350-01
Logic Symbol
Type 7402
Type 74LS02
Alternate Symbol
Truth Table
8
~
A~II
13
:v-v
Y
A
L
H
L
H
B
L
L
H
H
Y
H
L
L
L
B 12
VCC-14, GND-7
Loading:
Inputs
Outputs
7402
1 Unit Load
10 Unit Loads
74LS02
0.2 Unit Load
5.0 Unit Loads
TTL Hex Inverter
TTL Hex Inverter, Low Power
TTL Hex I nverter, Low Power Schottky
Part No.1 0136
Part No.1 0389
Part No. 10209
Logic Symbol
Type 7404
Type 74L04
Type 74LS04
Alternate Symbol
A---{>-Y
VCC-14, GND-7
Loading:
Inputs
Outputs
1 Unit Load (.1 for 74L04, .2 for 74LS04)
10 Unit Loads (2 for 74L04, 5 for 74LS04)
4-6
TTL Hex Inverter, Open-Collector
Part No. 13145
Logic Symbol
Type 7405
Alternate Symbol
A-{>-Y
VCC-14, GND-7
Loading:
Inputs
Outputs
1 Unit Load
10 Unit Loads
TTL Hex Inverter Buffer/Driver
These drivers have high-voltage (up to 30V)
open-collector outputs for interfacing with high-level
circuits or for driving high current loads.
Part No. 10460
Logic Symbol
Alternate Symbol
VCC-14, GND-7
Loading:
Inputs
Outputs
Type 7406
1 Unit Load
25 Unit Loads
4-7
TTL Hex Buffer/Driver
Part No.1 0391
Type 7407
These drivers have high-voltage (up to 30V)
open-collector outputs for interfacing with high-level
circuits or for driving high current loads.
Logic Symbol
VCC-14, GND-7
Loading:
Inputs
Outputs
1 Unit Load
25 Unit Loads
Part No.1 0119
Part No. 10210
TTL Quad 2-lnput AND Gate
TTL Quad 2-lnput AND Gate, Low Power Schottky
Logic
Symbol
~
~
~
:D--v
11 Y
A~
13
8
VCC-14, GND-7
Loading:
Inputs
Outputs
1 Unit Load (.2 for 74LS08)
10 Unit Loads (5 for 74LS08)
4-8
Type 7408
Type 74LS08
Truth Table
y
A
B
L
L
L
H
L
L
H
L
L
H
H
H
TTL Triple 3-lnput NAND Gate
TTL Triple 3-lnput NAND Gate, Low Power Schottky
Type 7410
Type 74LS10
Part No. 10133
Part No. 13080
Logic Symbol
ty ty Ap
B 2
12y
13
C
11
VCC-14, GND-7
Truth Table
A
L
L
L
L
H
H
H
H
B
L
L
C
L
H
L
H
H
H
L
L
H
H
H
L
H
L
y
H
H
H
H
H
H
H
L
Alternate Symbol
,
B --<:1
A--q
C
Loading:
Inputs
Outputs
~
y
,
1 Unit Load (.2 for 74LS10)
10 Unit Loads (5 for 74LS10)
Type 7411
Part No. 10301
TTL Triple 3-lnput AND Gate
Truth Table
Logic Symbol
P P
11
~Py
C 13
B
L
L
H
H
H
H
L
L
H
H
H
L
H
H
H
H
VCC-14, GND-7
Alternate Symbol
Loading:
Inputs
Outputs
A
L
L
L
L
1 Unit Load
10 Unit Loads
4-9
C
L
H
L
L
y
L
L
L
L
L
L
L
H
TT L Hex Schmi tt-trigger Inverter
Part No.1 0299-01
Logically, these gates act like ordinary inverters
but because of the Schmitt action, each gate has
different input threshold levels for positive- and
negative-going signals. The hysteresis, which is the
difference between the two levels, is typically
800 mV.
Type 7414
Alternate Symbol
A-{>-Y
Logic Symbol
Waveforms
4
VCC-14, GND-7
Loading:
Inputs
Outputs
o
.75 Unit Load
10 Unit Loads
0.8
Part No. 10125
Logic Symbol
1.2
1.6
Type 7420
Truth Table
A
B
y
C
D
VCC-14, GND-7. Pins 3 & 11 not used.
Alternate Symbol
A
y
C
D
Loading:
Inputs
Outputs
0.4
INPUT VOLTAGE
TTL Dual 4-lnput NAND Gate
B
o
1 Unit Load
10 Unit Loads
4-10
A
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
8
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
C
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
D
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
Y
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
2
Logic Symbol
Truth Table
A
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
2
4
5
VCC-14, GND-7 Pins 3 & 11 not used
Alternate Symbol
A
B
C
y
o
Loading:
Inputs
Outputs
Type 74H21
Part No.1 0319
TTL Dual 4-lnput AND Gate
B
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
C
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
D
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
y
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
1.25 Unit Loads
12.5 Unit Loads
TTL Quad 2-lnput NAND High-Voltage Interface Gate
Part No. 10120
Type 7426
These gates have high-voltage (up to 15V) opencollector outputs for interfacing with high-level
circuits.
Logic Symbol
Alternate Symbol
Truth Table
A
L
:=D--v
A~12
II Y
8
13
VCC-14, GND-7
Loading:
Inputs
Outputs
1 Unit Load
10 Unit Loads
4-11
H
L
H
B
L
L
H
H
Y
H
H
H
L
TTL Quad 2-lnput OR Gate
TTL Quad 2-lnput OR Gate, Low Power Schottky
Type 7432
Type 74LS32
Part No. 10302
Part No. 13082
Logic Symbol
Alternate Symbol
Truth Table
9
,21Y-
B
L
H
L
H
A
L
L
H
H
:D-y
Y
L
H
H
H
VCC-14, GND-7
Loading:
Inputs
Outputs
1 Unit Load (.25 for 74LS32)
10 Unit Loads (5 for 74LS32)
TTL BCD-To-Decimal Decoder
TTL BCD-To-Decimal Decoder, Low Power Schottky
Type 7442A
Type 74LS42
Part No. 10146
Part No. 13083
Logic Symbol
1S
Truth Table
D
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
A
8
c
o
veC-16, GND-8
A 1-A8 = Binary address input
0-9 = Decimal output
Loading:
Inputs
Outputs
1 Unit Load (.25 for 74LS42)
10 Unit Loads (5 for 74LS42)
4-12
e
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
B
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
A
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
0
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
1
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
2
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
3
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
4
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
5
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
6
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
7
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
8
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
9
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
TTL Dual AND-DR-INVERT Gate
Type 7451
Part No. 10280
Logic Symbol
2
Truth Table
A
L
L
X
X
H
X
A9
B 10
3
4
C
13
o1
5
VCC - 14, G N D - 7
B
X
X
L
L
H
X
C
L
D
Y
X
X
X
L
L
L
X
X
X
H
H
H
H
H
H
L
L
Y =AB +CD
(Make no connections to pins 11 and 12.)
Loading:
Inputs
Outputs
1 Unit Load
10 Unit Loads
TTL 4-Wide Expandable AND-DR-INVERT Gate
Part No. 10192
Type 7453
Up to four type 7460 expander gates may be
connected to the expander inputs. Both expander
inputs must be used simultaneously. If the expander
inputs are not used, they should be left open.
Logic Symbol
A 13
B
1
C 2
o3
E 4""----<
y
F 5
X
12 X
Y = AB+CD+EF+GH+X
VCC-14, GND-7
Loading:
Inputs
Outputs
1 Unit Load
10 Unit Loads
4-13
Part No. 10139
Part No. 13085
TTL Dual D Flip-flop
TTL Dual D Flip-Flop, Low Power Schottky
Type 7474
Type 74LS74
The 7474 contains two D-type edge-triggered
flip-flops with direct preset and clear inputs. A low
level on the preset or clear input will set or reset the
flip-flop, respectively, regardless of other input condi-
tions. When both the preset and clear are high, the
logic level on D is transferred to a on the positivegoing edge of the clock.
Logic Symbol
Timing Waveforms
4
2
0
P Q 5
ClK
ClK
C
Q,
Q-.J
Q6
I
10
P Q 9
Truth Table
ClK
CQ
8
13
VCC-14, GND-7
Preset input
Data input
Clock input
Clear input
Data outputs
P
o
CLK
C
0,0
Function
Preset
Clear
Clear
Set
Reset
Set Up
Outputs
CLK
D
P
C
a,a
Clock
D
X
X
X
X
X
X
••
L
H
L
X
Outputs
0
H
L
H
L
H*
H
a
H
L
L
H
No Change
*This configuration is nonstable; that is, it will not
persist when preset and clear inputs return to their
inactive (high level).
Loading:
Inputs
Preset
L
H
L
H
H
H
Inputs
Clear
H
L
L
H
H
H
Unit Loads
7474
74LS74
.5
2
.25
1
1
.5
.75
2
10
5
4-14
TTL 4-Bit Binary Full Adder
TTL 4-Bit Binary Full Adder, Low Power Schottky
Part No. 10140
Part No. 13086
This device adds two 4-bit binary numbers and a
carry (C~ input). The sum (~) outputs are provided
for each bit and the carry output (C4) is obtained
Type 7483A
Type 74LS83
from the fourth bit. Note the non-standard VCC and
GND connections to this device.
Alternate Symbol
Logic Symbol
A1
10
14
C4
8
81
A2
A2
~1
A3
~1
62
NOTE: VCC-5, GND-12
~2
A3
83
A4
A1
B4
C¢
A4
~2
B1
~3
82
83
84
c¢
~4
C4
Truth Table
Outputs
~~
C~=H
C~=L
When
C2=H
When
C2=L
Inputs
x:b(,b(.b(.x:b(.~ %%%
A3
A4
83
Outputs
A3,
A4,
1-4
~4
C4
~3
~4
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
H
L
L
L
H
L
L
H
L
L
L
H
H
H
L
L
L
H
L
H
H
L
L
L
H
L
L
H
L
H
H
L
H
L
H
L
H
H
L
L
L
H
L
H
H
L
H
H
L
L
L
H
H
H
H
L
L
L
H
H
L
H
L
L
L
H
L
H
L
H
H
L
H
L
L
H
H
H
L
L
L
H
L
H
L
H
H
H
L
L
L
H
H
H
L
H
L
L
H
H
L
H
L
L
H
H
L
L
H
H
L
H
H
L
H
H
H
L
H
L
H
H
L
H
H
H
H
L
H
L
H
H
H
H
H
H
L
H
H
H
H
H
Input conditions at A 1, 81, A2, 82, and C~ are used to determine outputs
~1 and ~2 and the value of the internal carry C2. The values at C2, A3, 83,
A4, and 84 are then used to determine outputs ::!:3, ::!:4, and C4.
Loading:
Al,
A2,
Sum
C4
~3
H
NOTE:
Inputs
84
B1,
B2,
B3,
B4
C~
Unit Loads
74LS83
7483A
1 or 2*
1
1 or 2*
.25
5
10
5
5
* Depending upon manufacturer.
4-15
Part No.1 0303
TTL Quad 2-lnput Exclusive OR Gate
Type 7486
Logic Symbol
1A~1Y
1B~
Truth Table
INPUTS
2A~2Y
2B~
A
L
L
H
H
3A1~3Y 4A1~11
13
4Y
3B~
4B
B
L
H
L
H
OUTPUT
Y
L
H
H
L
VCC-14, GNO-7
Loading:
Inputs
Outputs
1 Unit Load
10 Unit Loads
TTL 16 x 4-bit Random Access Memory, Open Collector
Part No. 10193
TTL 16 x 4-bit Random Access Memory, Three-State
Part No.1 0334
TTL 16 x 4-bit Random Access Memory, Open Collector Schottky Part No. 13088
Logic Symbol
4
6
10
12
1
15
14
13
3
2
01
02
03
04
Function Table
01
02
03
04
CE
A0
A1
A2
A3
WR
VCC-16, GNO-8
Loading:
1 Unit Load
.16 Un it Load (.25 mal
10 Unit Loads
4-16
Inputs
WR
L
L
L
H
H
X
H*
CE
Inputs (7489, 8599)
Others
Outputs
Type 3101/7489
Ty pe 8599/7 4S 189
Type 3101A/74S289
Outputs
H*
Complement
of stored data
H*
Function
Write
Read
Inhibit
high
for
open-collector,
high-impedance for three state. Some
manufacturers specify this as
indeterminate.
Part No. 10304
TTL Divide-By-Twelve Counters
Each of these chips contains four master-slave
flip-flops and additional gating to provide a divid€by-two counter and a three-stage binary counter for
which the count cycle length is divide-by-six.
To use the maximum count length of the counters,
the B input is connected to the OA output. The input
count pulses are applied to input A and the outputs
are as described in the truth table.
Alternate Symbol
Logic Symbol
Truth Table
Output
QA
5
VCC
A
OA
CNTR
8
08
12
Count
INPUT A
11
9
R02
GND
Type 7492A
OC
QD 8
08
INPUT 8
10
°D
°c
°B
°A
0
L
L
L
L
1
L
L
L
H
2
L
L
H
L
3
L
L
H
H
4
L
H
L
L
5
L
H
L
H
6
H
L
L
L
7
H
L
L
H
8
H
L
H
L
9
H
L
H
H
10
H
H
L
L
11
H
H
L
H
OC
00
Output 0A is connected to input B.
H = high level, L = low level, X
Reset/Cou nt
Reset Input
Loading:
Any Reset
A
B
Output
1 Unit Load
2 Unit Loads
3 Unit Loads
10 Un it Loads
4-17
Output
R01
R02
H
H
°
L
L
X
Count
X
L
Count
= irrelevant
TTL 4-Bit Binary Counters
Part No. 10141
Each of these chips contains four master-slave
flip-flops and additional gating to provide a divide
To use the maximum count length of the counters,
the B input is connected-to the OA output. The input
count pulses are applied to input A and the outputs
are as described in the truth table.
by-two counter and a three-stage binary counter for
which the count cycle length is divide-by-eight.
Logic Symbol
A
OA
8
2
3
Output
OA
VCC
CNTR
1
Truth Table
Alternate Symbol
5
14
Type 7493A
08
OC
Rfi'1
QD
GND
10
Rfi'2
12
INPUT A
°D
°c
°B
°A
0
L
L
L
L
1
L
L
L
H
2
L
L
H
L
3
L
L
H
H
4
L
H
L
L
5
L
H
L
H
6
L
H
H
L
7
L
H
H
H
8
H
L
L
L
9
H
L
L
H
10
H
L
H
L
11
H
L
H
H
12
H
H
L
L
13
H
H
L
H
14
H
H
H
L
15
H
H
H
H
Count
9
OS
8
11
QC
00
Output OA is connected to input B.
H = high level, L = low level, X = irrelevant
Reset/Count
Loading:
Inputs
Any Reset
A
B
Outputs
Reset Inputs
1 Unit Load
2 Unit Loads
2 Unit Loads
10 Unit Loads
4-18
Output
R0 1
R0
H
H
L
L
X
Count
X
L
Count
2
°
TTL Dual J-K Master-Slave Flip-flop
TTL Dual J-K Master-Slave Flip-flop, Low Power Schottky
Part No. 10305
Part No. 13089
Logic Symbol
Timing Waveform
Q 3
HIGH
2
LOW
13
8
J
Q
1. Isolate slave from master
2. Enable entry of data from J and K
inputs to master
3. Disable entry of data from J and K
inputs
4. Transfer information from master to
slave
5
elK
11
K C
CLO C K WAVEFORM
J, K
CLK
C
0, 5 =
6
Q
10
Data inputs
Clock inputs
Clear inputs
Data outputs
VCC-7, GND-14
Truth Table
(Each Flip-Flop)
tn
tn+1
J
K
a
L
L
L
H
On
L
H
H
L
H
H
On
tn
time when clock is high (2-3)
tn+1
time after clock goes low (4)
Loading:
C,CLK
J, K
Outputs
2 Unit Loads (.5 for 74LS1 07)
1 Unit Load (.25 for 74LS107)
10 Unit Loads (5 for 74LSl 07)
4-19
Type 74107
74LS107
BCD/Decimal Decoder/Driver
Part No.1 0172-29
This BCD-to-decimal decoder/driver consists of
eight inverters and ten 4-input NAND gates. The
inverters are connected in pairs to make BCD input
data available for decoding by the NAND gates. Full
decod ing of BCD input logic ensu res that all outputs
remain off for all invalid (10-15) binary input
conditions.
Logic Symbol
15
14
13
12
A
B
Truth Table
0
1
2
3
4
e
5
6
0
7
8
9
vee -
Type 74145
16
GND - 8
No.
D C B A 0 1 2 3 4 5 6 7 8 9
0
L L L L L H H H H H H H H H
1
L L L H H L H H H H H H H H
2
L L H L H H L H H H H H H H
3
L L H H H H H L H H H H H H
4
L H L L H H H H L H H H H H
5
L H L H H H H H H L H H H H
6
L H H L H H H H H H L H H H
7
L H H H H H H H H H H L H H
8
H L L L H H H H H H H H L H
9
H L L H H H H H H H H H H L
H L H L H H H H H H H H H H
(083 - 035)
H L H H H H H H H H H H H H
H H L L H H H H H H H H H H
H H L H H H H H H H H H H H
H H H L H H H H H H H H H H
H H H H H H H H H H H H H H
H = high level (off), L = low level (on)
Loading:
Input
Output
4-20
1 Unit Load
12.5 Unit Loads
Part No.1 0394
TTL 8-Line to 3-Line Priority Encoder
This device accepts data from 8 low-active inputs
and provides a binary representation on the three
low-active outputs. A priority is assigned to each input so that when two or more inputs are active simultaneously, the input with the highest priority is represented on the output. I nput line '7' has the highest
priority; line '0', the lowest.
Type 74148
A high on the Enable Input (EI) pin forces all
outputs high, effectively blocking the encoder. The
Group Signal (GS) output goes low when any input
(in addition to EI) is low. Enable Out (EO) is low
only when all inputs (other than E I) are high.
Logic Symbol
9}
{ZJ
2
DATA
INPUTS
7
AI
6
3
4
5
Loading:
GROUP SIGNAL
6
7
ENABLE
INPUT
DATA
OUTPUTS
'0' Input
Other Inputs
Outputs
ENAB LE OUTPUT
EI
VCC-16, GND-8
Truth Table
Outputs
Inputs
EI
0
1
2
3
4
H
L
L
L
L
L
L
L
L
L
X
X
H
X
X
X
X
X
X
X
X
X
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
X
X
X
X
X
X
X
L
High
L
H
L
H
H
H
L
H
H
L
L
H
H
H
H
Low
6
7
A2
A1
AO
GS
EO
X
X
X
H
H
H
L
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
L
L
H
H
L
L
H
H
H
H
L
H
L
H
L
H
L
H
H
H
L
L
L
L
L
L
L
L
H
L
H
H
H
H
H
H
H
H
5
L
H
H
H
H
H
H
L
H
H
H
H
H
X
4-21
Irrelevant
1 Unit Load
2 Unit Loads
10 Unit Loads
Part No. 10194
Pa rt No. 1 3090
TTL Dual 2:4 Decoder
TTL Dual 2:4 Decoder, Low Power Schottky
Type 74155
Type 74LS155
Truth Table
Logic Symbol
Outputs
Inputs
1C
1G
13
A
3
B
2C
2G
1Y3
1Y2
1Yi
1YO
2Y3
2Y2 '
2Y1
2YO
VCC-16, GNO-8
Select
A
B
X
L
L
H
H
X
X
L
L
H
H
X
X
L
H
L
H
X
X
L
H
L
H
X
Loading:
Inputs
Outputs
1 Unit Load (.25 for 74LS155)
10 Unit Loads (5 for 74LS155)
4-22
Gate
1G
Data
1C
H
L
L
L
L
X
X
H
H
H
L
2G
H
L
L
L
L
X
1YO
1Y1
1Y2
1Y3
H
L
H
H
H
H
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
L
H
2C
2YO
2Y1
2Y2
2Y3
X
L
L
L
L
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
L
H
H
H
H
H
L
H
H
TTL 4-Bit Synchronous Binary Counter
TTL 4-Bit Synchronous Binary Counter, Low Power Schottky
All
f lip-flops
simultaneously, so
in this chip are clocked
all output changes occur
Type 74161
Part No.1 0335
Part No. 13091
Type 74lS161
simu Itaneously. A low on the Clear input overrides
other in puts, and drives all outputs low.
Timing Waveforms
Logic Symbol
CLEAR~
~A
OA
~B
2..
C
7
QC
QD
-
EN P
EN T
,-
l1
08
~D
iO
LOAO -~.--------------_
LOAD
Jf
J..!
ENABLE
CAR~
'
OUTPUTS
---,
{==
-
-
2 -
-
-
-
:
Unit Loads
74LS161
1
2
1
.5
.5
.25
10
5
I
L I_ _ _ _ _ _ _ _ _ _ _
r-tL__________
: 12
:13
14
I
I---
15
0
COUNT
?:
1
•
I-
H
L
X
X*
X
X*
X
X*
X
X
X
X
X
L
L
L
H
H
H
'NHIBIT
-
Lp'?ESET
3. Count to thirteen, fourteen, fifteen, zero, one, and two.
4. Inhibit
EN-P
L
r----
1. Clear outputs to zero
2. Preset to binary twelve
CLK
t
-
:
INPUTS
H
-
:
Truth Table
t
t
t
-
=~~.~---~I__________
CLEAR~
74161
_-J:I
_ _ _ :,
:
4 _ _ _ :~:
loading:
t
-
-__ ,:_----.::_~_~.
CARRY
Outputs
-
:I
---'--------'.
8
VCC-16, GND-8
lOAD
CLK, EN-T
Other
-
-~uuLl'JLJULJLJLJLJLJ-
P ___
:
EN A B LET
C
Inputs
-
,~:~~s{ ~~----.---'~-~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
~
CLOCK
.1..~CLK
-
EN-T
LOAD
C
A,B,C,D
OUTPUTS
X
l
X
X
L
H
X
X
X
DATA
H
H
H
H
H
H
H
H
X
X
No Change
No Change
All lOW
Preset to
A,B,C,D,
input data
No Change
No Change
No Change
Count Up
* Avoid changes to inputs while ClK is low.
4-23
X
X
TTL 4-Bit Synchronous Binary Counter
Part No.1 0356
All flip-flops in this chip are clocked simultaneously, so all output changes occur simultaneously.
A low on the Clear input overrides all other inputs,
Type 74163
and drives all outputs low at the next positive-going
clock.
Tim ing Waveforms
Logic Symbol
LOAD--~~r----------------------------
r-
DATA { :
INPUTS
..
8
===:~ =
=
...Jr--------.:=
...Jr-----r:_
=
CLOCK
ENABLE P - - - - - - : - '
:1
CAR 15
c
ENABLE{T,
2
OUTPUTS
..
8
VCC-16, GND-8
=== =: '
==_;
===u
~I~,~~~:
r-:-.,;..._ _ _...,L...-_ _ _ _ _ _ _ _ _ _ _ _ __
___ ~
r' - - - : - - - - - : . ._________________
CARRY _ _ _~~~---~r-I~---~--------
:1:1
: 12
CLEAR
Loading:
ClK, EN-T
All other inputs
Outputs
1.
2.
3.
4.
2 Unit Loads
1 Unit Load
10 Unit Loads
-.J
L
14
I---
I
15
0
COUNT
'l :
•
I-
Clear outputs to zero
Preset to binary twelve
Count to thirteen, fourteen, fifteen, zero, one, and two.
Inhibit
Truth Table
INPUTS
CLK
EN-P
H
L
X
X*
X
X*
t
X
t
X
l
t
t
t
H
L
t
H
EN-T
INHIBIT ~
PRESET
LOAD
C
A,8,C,D
OUTPUTS
X
X*
X
X
X
X
X
L
L
H
X
X
X
L
L
H
H
H
H
H
H
H
H
H
H
No Change
No Change
All LOW
Preset to
A,B,C,D,
input data
No Change
No Change
No Change
Count Up
* Avoid changes to inputs while CLK is low.
4-24
DATA
X
X
X
X
TTL 8-Bit Shift Register
Part No. 42325
TTL 8-Bit Sh ift Register, Low Power Schottky
Part No. 42392-01
This 8-bit shift register featu res gated serial inputs
and an asynchronous clear. The gated serial inputs (A
and B) perm it complete control over incoming data as
a low as either (or both) input(s) inhibits entry of the
new data and resets the first flip-flop to the low level
at the next clock pulse. A high-level input enables the
other input which will then determine the state of the
first flip-flop. Data at the serial inputs may be
changed while the clock is high or low, but only
information meeting the set-up requirements will be
entered. Clocking occurs on the low-to-h igh level
transition of the clock input.
Type 74164
Truth Table
Logic Symbol
Outputs
Inputs
1 A
2 B SR
8
Type 74LS164
Clear
Clock
A B
QA
QB ••• QH
L
X
X X
L
L
L
H
L
X X
X
X
X
H
t
H H
H
X
X
H
t
L X
L
X
X
H
t
X L
L
X
X
QD
QE
QF
QG
QH
CLK
C
9
H
L
X
VCC = 14 GNO = 7
t
high level (steady state)
low level (steady state)
irrelevant (any input, including transitions)
transition from low to high level
Timing Waveforms
CLEAR
:
SERIAL {
INPUTS
CLOCK
u
-u
A
~~----~----
B --;------'
:
I
OA=--~:--------~~~-----~-----OS ---1
~-----=--------
OC ===1
____
00 ===1
r--L.SIL....-..:._____
OE===l
r--L.Il_ _ _ ___
OF===1 ______________r--lL.....;:_________
_ _ __
_
OH ===,
nL..'- - - - r--L.SI~_.:..--
OUTPUTS
I
---'~
~r---i~,
QG---.!.
.
I
,--
I
CLEAR
CLEAR
Loading:
1 Unit Load (.25 For 74LS164)
Inputs
Outputs = 5 Unit Loads
4-25
Part No. 10195
Part No. 13092
TTL 4 x 4-bit RAM
TTL 4 x 4-bit RAM, Low Power Schottky
Type 74170
Type 74LS170
This RAM has independent read and write
addressing and gating, which allows simultaneous
reading and writing to/from different addresses.
Outputs are open-collector.
Alternate Symbol
Logic Symbol
14
13
15
I
2
3
01
02
03
04
5
RA
01
02
03
RA
WB
RB
GW
GR
01
Q1
02
Q2
04
2
03
Q3
7
3
04
Q4
6
10
9
6
5
WA
WA
WB
GW
4
RB
GR
VCC-16, GND-8
Write Function Table
GW
L
L
L
L
H
Write Inputs
WA
WB
L
L
H
H
L
H
L
H
X
X
Read Function Table
Function
Write Word
Write Word
Write Word
Write Word
No Change
GR
0
1
2
3
L
L
L
L
H
Loading:
Inputs
Outputs
Any D R W
GR, GW
01-04
Unit Loads
74LS170
74170
.25
1
.5
1
5
10
4-26
Read Inputs
RA
RB
L
L
H
H
L
H
L
H
X
X
Function
Read Word 0
Read Word 1
Read Word 2
Read Word 3
All Outputs
High
TTL Hex O. Latch
TTL Hex 0 Latch, Low Power Schottky
Part No. 10336
Part No. 13093
Type 74174
Type 74LS174
All flip-flops in this chip are clocked or cleared
simultaneously. A Iowan the clear input overrides all
other inputs.
Logic Symbol
3
1Q
10
I
~CLK
C
I
4
J
I
I
2Q
20
~CLK
c
I
6
y
I
~
11
13
14
~CLK
I
I
I
I
C
c
-?
50
50
~CLK
III.
C
J
60
9 I
1
4Q
40
~CLK
I
I
I
I
J
I"
I
I
3Q
3D
I
60
~CLK
c
IIIro
g
Truth Table
(Each Flip-Flop)
2
I
I
I
I
I
I
C
0
X
X
L
H
H
H
5
••
L
H
L
X
• =
7
I
I
I 10
I
I
I 12
I
I
I 15
I
I
10- 60
CLK
C
10- 60
vce-16, GNO-8
Loading:
Inputs
Outputs
INPUTS
CLK
1 Unit Load (.25 for 74LS174)
10 Unit Loads (5 for 74LS174)
4-27
Data Inputs
Clock Input
Clear
Data Outputs
H
L
X
OUTPUT
0
H
H
L
No Change
High level
Low Level
Irrelevant
Transition from low to
high level
TTL Ouad D Flip-Flop
TTL Ouad 0 Flip-Flop, Low Power Schottky
Part No.1 0337
Part No. 42363-01
This positive-edge-triggered flip-flop utilizes TTL
circu itry to implement D-type flip-flop logic, with a
direct clear input and complementary outputs from
each flip-flop.
Type 74175
Type 74LS175
positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not
directly related to the transition time of the positivegoing pulse. When the clock input is at either the high
or low level, the 0 input signal has no effect at the
output.
Data at the 0 inputs meeting set-up time requirements is transferred to the 0 outputs on the
Logic Symbol
Truth Table
(Each Flip-Flop)
C
ClK
0
0
0
L
X
X
l
H
H
H
H
L
H
t
t
L
L
H
H
L
X
No
Change
H
L
X
t
r---,
Outputs
Inputs
4
5
12
high level
low level
irrelevant
transition from low level
to high level
13
9
1
VCC = 16, GND = 8
10 - 40
ClK
C
1 Q - 40
=
10 - 40 =
Loading:
Inputs
Outputs
0.25 Unit Load
= 10 Unit Loads
4-28
Data Inputs
Clock Input
Clear
Data Outputs
Complementary
Data Outputs
TTL 4-Bit Parallel-Access Shift Register
Part No. 10191
Type 74195
Data can be loaded into this register either serially
or in parallel. When Parallel Enable (PE) is low,
parallel data is loaded into the flip-flops on every
positive-going clock. When PE is high, data is shifted
from the J and K inputs to flip-flop 0, and from 0 to
1, 1 to 2, and 2 to 3, at each positive-going clock
transition. A low on the Clear (C) input overrides all
other controls.
Logic Symbol
9
PE
2
J
K
I~
pClJ
QflJ
PI
P2
QI
Q2
P3
Q3
ClK
C
VCC-16, GND-8
Truth Table
C
PE
Inputs
CLK
J
L
X
X
H
H
H
H
H
H
L
H
H
H
H
H
H
L
X
OOn
•
•••
•
L
K
Po-P3
X
X
X
X
X
X
abcd
L
L
L
H
H
H
L
H
X
X
X
X
X
X
00
01
L
a
OOn
L
OOn
OOn
L
b
01n
OOn
OOn
OOn
OOn
H
High
Low
Irrelevant
State of 00 before positive transition of CLK
Loading:
Inputs
Outputs
1 Unit Load
10 Unit Loads
4-29
Outputs
02
L
c
02n
01n
01n
01n
01n
03
03
L
d
03n
02n
02n
02n
02n
H
-
d
03n
02n
02n
02n
02n
Clear
Parallel Load
No Change
}Shih
TTL 8-bit Addressable Latch
TTL 8-bit Addressable Latch, Low Power Schottky
Part No.1 0339
Part No. 13094
This is a multifunctional device capable of storing
single line data in eight addressable latches, and being
a one-of-eight decoder and demultiplexer with
high-active outputs. It incorporates a low-active
common clear for resetti ng all latches, as well as a
low-active enable.
remain in their previous state and are unaffected by
the data or address inputs. When operating as an
addressable latch, changing more than one bit of the
address could impose a transient wrong address.
Therefore, this should only be done while E is HIGH.
Type 9334
Type 74LS259
I n the one-of-eight decoding or demultiplexing
mode, the addressed output will follow the state of
the 0 input, with all other outputs in the LOW state.
There are two modes of operation, shown in the
Function Table. In the addressable latch mode, when
E is LOW, data on the data line (D) is written into the
addressed latch. The addressed latch will follow the
data input, with all nonaddressed latches remaining in
their previous states. When E is HIGH all latches
When E is HIGH and C is LOW all outputs are
LOW and unaffected by the address and data inputs.
Logic Diagram
Logic Symbol
ONLY ONE LATCH SHOWN FOR CLARITY
3
2
13
14
15
A2
A1
12 Q7
7
6 11 06
5 10 05
4
9 Q4
7 Q3
A0
3
0
2 6
5
1
4
0
E
C
A2
-----I
A1
Af/J
D -----\
E
02
Q1
QO
C
TO OT HER LATCHES
VCC-16, GND-8
Function Table
Inputs
Outputs
C
E
0
L
L
L
H
H
H
L
L
H
L
L
H
L
H
X
L
H
X
Loading:
Inputs
Outputs
I
I
E
Other
Unit Loads
74LS259
9334
.25
1.5
.25
1
5
6
4-30
Addressed
Latch
L
H
L
L
H
No Change
Others
L
L
L
No Change
No Change
No Change
Mode
} Demultiplexer
Clear
} Addressable
Latch
TTL Quad 2-lnput Multiplexer/Register
Part No. 10196
TTL Quad 2-input Multiplexer/Register, low Power Schottky Part No. 13095
Type 74298
Type 74LS98
Data is stored on the negative-going edge of the
elK. With WS low, word 1 (Al, Bl, el, Dl) is
stored; with WS high, word 2 is stored.
logic Symbol
QA 15
Q8
QC
Logic Diagram
Vee-16, GND-8
Al
WORD
SELECT
S
OA
°A
ClK
A2
R
B1
S
QB
QS
Oc
Qc
ClK
B2
R
C1
S
eLK
C2
R
01
S
ClK
02
R
loading:
Inputs
Outputs
CLOCK
Unit Loads
74298
74LS298
.25
10
5
4-31
Qo Qo
Part No.1 0197
Part No. 13096
TTL Hex Bus Driver, Three-State
TTL Hex Bus Driver, Three-State, Low Power Schottky
Logic Sy mbol
-I
I
12
1
3
4
5
6
7
9
12 1
11
I
I
I
,4
13
1
15
I
1_ _ VCC-16, GND-8
Loading:
Inputs (Gate enabled)
Outputs
Unit Loads
74367
74 LS367
1
.25
20
10
4-32
Type 74367
Type 74LS367
MOS 8-bit Microprocessing Unit
Part No. 42338
This is a single chip 8-bit parallel microprocessor
wh i ch forms a microcomputer system when
interfaced with any type or speed of standard
semiconductor memory up to 64K 8-bit words and an
I/O device. The MPU inputs and outputs data over an
8-bit bi-directional three-state data bus (D(}D7). It
addresses memory and I/O devices over a 16-bit
three-state memory address bus (AD-A 15). It is driven
by two 12-volt non-overlapping clocks, ~1 and ~2.
There are four input signals, INT (Interrupt), ROY
(Ready), HOLD, and RST (Reset). Output signals
include INTE (Interrupt Enable), OBI N (Data Bus
In), WR (Write), SYNC, WAIT, and HLDA (Hold
Ackn owl edge).
The 8080A uses its internal stack pointer to access
external memory, allowing it to handle multiple-level
priority interrupts. This also allows adequate
subroutine nesting.
Type 8080A
Logic Symbol
+5V
10
9
8
The 8080A contains a register array made up of
six 16-bit registers: a Program Counter, a Stack
Pointer, and four register "pairs," each made up of
two 8-bit registers. One of these is the Temporary
Register, called W/Z, which is used for the internal
execution of instructions. The other three are
working registers, called BIC, D/F, and H/L. The six
general purpose registers can be used as either single
8-bit registers or 16-bit register pairs; W/Z is not
program addressable.
7
3
4
5
6
vec
DcjJ
01
D2
03
04
05
06
D7
+12V
28
VDO
A¢
A1
A2
A3
A4
A5
A6
A7
A8
A9
22
15
The 8080A also contains an Arithmetic and Logic
Unit (ALU), containing an 8-bit accumulator (ACC),
an 8-bit temporary accumulator (ACT), an 8-bit
temporary register (TMP), and a 5-bit flag register. All
arithmetic and logic instructions are performed in this
section.
14
The third major part of the 8080A contains the
Instruction Register, Instruction Decoder, and all
ti ming and control logic. The last major portion is the
Data Bus Buffer, a 3-state bi-directional 8-bit latch
that serves to isolate the the MPU's internal data bus
from the external bus.
!l1
12
I NT
ROY
RST
HOLD
GND
The instruction set consists of over 100 different
instructions, which provide conditional and
u ncon d itional branching, decimal and binary
arithmetic, and logical, register-to-register, stack
control, memory reference, and I/O instructions. Up
to 256 input ports and 256 output ports can be
addressed. Instructions may be either one, two, or
three 8-bit bytes in length. Memory can be referenced
four ways: direct, register, register indirect, and
immediate. Non memory-reference instructions can
be executed in 2 microseconds when a 2 MHz clock is
used. The sequential program execution can be
interrupted by driving the INT input high.
INTE
DBIN
WR
SYNC
HLDA
WAIT
VSS
- 5V
Loading:
Outputs
4-33
1.2 Unit Loads
IMtruction Codel ll
Os 0 4 03 O2 0 , DO
Mnemonic
DMCfiptiGn
[ry D6
MOV ,I, r2
MOV M,r
MOVr,M
HLT
MVlr
MVIM
lNR r
OCR r
INR M
OCR M
ADD r
ADC r
Move register to register
MOlle register to memory
Move memory to register
Halt
Move immediate register
Move immediate memory
Increment register
Decrement registtf
Increment memory
Decrement memory
Add register to A
Add register to A with terry
Subtract fegister flam A
Subtract register from A
with borrow
And register with A
Exclusive Or register with A
Or register with A
Compare register with A
Add memory to A
Add memory to A with cerry
Subtract memory from A
Subtract memory from A
with borrow
And memory with A
Exclusi¥! Or memory with A
Or memory with A
Compere memory with A
Add immedjate 10 A
Add immediate to A with
carry
Subtract immediate from A
Subtrlct immedi.te from A
with borrow
And immediate with A
Exchn.ive Or immediate with
A
Or imm~diate with A
Compare immediate with A
Rotate A left
RotBte A right
Rotate A left through carry
Rotate A right through
carry
Jump unconditional
Jump on tarry
Jump on no carry
Jump on lero
Jump on no zero
Jump on positive
Jump on minus
Jump on parity even
Jump on parity odd
Call unconditional
Call on carry
Call on no carry
ell! on lelO
CIIII on no lero
Cb!l on positive
C~ll on minus
Call on lunity even
Call on parity odd
Return
Heturn on c~rry
Rfturn on no carry
o
o
o
o
o
o
o
o
o
o
o
D
0
1
1
1
0
0
0
0
1
0
1
1
0
1
o D
o o
0
0
0
1
1
0
0
sus r
S8S r
ANAr
XRA r
ORA r
CMPr
ADO M
ADC M
SUB M
S8S M
ANA M
XRA M
ORA M
CMPM
ADI
ACI
SUI
S81
ANI
XRI
ORI
CPI
RLC
RRC
RAL
RAR
JMP
JC
JNC
JZ
JNZ
JP
JM
JPE
JPO
CALL
~C
CNC
CZ
CNZ
CP
CM
CPE
CPO
RET
RC
RNt
o
1
0
0
0
0
DDS
lOS
o o
1
1
1
o
o
1
o
o
1
1
o
o
0
0
0
S
o
o
o
o
1
1
0
RM
RPE
RPO
RST
5
5
1
10
S
S
S
S
4
S
S
S
4
4
4
o
S
1
S
S S
S
RP
10
o
o
o
o
o
o
o
o
o
o
o
o o
o 1
o
o
1
1
o
o
o o
o o
1
o
o
o o o 0
o
o
o
o
o o
o
o o
o
o
o
1
o
1 o
o o
o
o
1
o
o
o
o
10
10
10
10
o
o
o
o
o
o
o
o
o
10
10
10
10
10
o
o
o
17
11/17
11/17
11/17
11/17
11/17
11/17
11/17
0
0
0
11117
10
5111
5/11
1
o
o
o
Restan (3)
Input
Output
OUT
Load immediate register
LXI 8
p.ir B & C
Load immediate fe!!ister
LXID
Pair 0 & E
Laid immediate register
LXI H
Pair H & L
Load immediate stack pointer
LXISP
Push register Pair 8 & C on
PUSH B
stack
Push register Pair D & E on
PUSH 0
stick
PUSH H
Push register Pair H & L on
stack
PUSH PSW Push A and Flags
on stack
Pop register pair S & C off
POP 8
stack
Pop register pair 0 & E off
POP 0
stack
Pop register pair H & l off
POP H
stack
Pop A Ind Flags
POP PSW
off stack
Store A direct
STA
Load A direct
LOA
Exchange D & E, H & L
XCHG
Registers
Exchange top of stick, H & l
XTHL
H & L to slilck pointer
SPHL
H & L 10 program counter
PCHL
Add 8 & C to H & L
DAD 8
Add 0 & E to H & L
OAO 0
Add H & L to H & l
DAD H
Add stack pointer to H & L
DAD SP
Store A indirect
STAX 8
Store A indirect
STAX D
Load A indirect
LOAX B
Load A indirect
LOAX 0
Increment B & C registers
INX B
Increment 0 & E registers
INX D
Increment H & L registers
INX H
Increment stack pointer
INX SP
OCX B
OeCII~ment 8 & C
OCX D
Decr~rnent 0 & E
OCX H
Decrement H & L
Decrement stack pointer
DCX SP
Complement A
CMA
Set carry
STC
CMC
Complement carry
Dec,mal adjust A
DAA
Store H & L direct
SHLO
Load K & L direct
LHLD
Enable Interrupts
EI
OiSllble
interrupt
01
No-opefation
NOP
44
Notes:
)
l
DOD or SSS
A
111
I
I
8
000
I
I
C
001
I
I
Register
0
I E
010
011
I
I
I
H
100
I
I
L
101
I
I
Mem
110
2) Two possible cycle times (11/17 or 5/11) indicate instruction cycles dependent on
condition flags.
3) After a Restart instruction, the next instruction is fetched from memory at the
address eight times AAA.
4-34
Instruction Code (1)
Os D4 D:J ~ D,
o ,
o 0
o
Ir~
o
o
1
[ry ~
Description
Return on zero
Return on no zero
Return on positive
Return on minus
Return 011 parity even
Return on parity odd
RZ
RNZ
10
S
S
S
S
1
Mnemonic
5
7
7
7
7
S
S
S
S
o
o
0
S
S
o
o o
o o
o
1
1
S
S
o o o
o o 1
o
o
o
o
o
o
o
o
o
o
0
S
Clock 12]
Cycles
S S
1
0
o o 0
o o 1
o
o o
o o
o
o
o
o
o
o
o
o
1
Type 8080A (Continued)
Part No. 42338
MOS 8-bit Microprocessing Unit
1
o
1
0
A
A
A
1
o
1
1
1
0
0
0
o
o o
0
o
o
10
0
0
o
10
0
1
o
o
10
o
o
11
o o
o
11
o
o
11
o o {) o
10
o
10
o o
10
o
10
o
o
o
1
1
0
o
0
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
1
0
o
o
0
1
0
o
o o
0
o
o
o
o
o
1
0
1
1
0
0
0
0
o
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
o
1
o
o
0
0
o
0
o
1
o
11
o
o
o
o
o o 0
1 o 0
o
o
o
o o 0
0
10
1
0
1 o
o o
o
o
o
5/11
5/11
11
o
0
0
0
0
5/11
0
o
1
0
0
10
10
o
0
0
5/11
{)
0
o
o
o
o
o
0
0
0
o
1
5/11
5111
o
0
Clock 12)
Cycles
C 0
o
o
o
0
0
0
o
1 1 0
010
o
o
o
0
0
Do
18
1
o
o
o
o
o
o
1
13
13
4
5
5
10
10
1
1
10
o
o
o
o
7
7
7
7
5
5
10
5
5
5
5
o
o
o
o
5
5
4
o
o
1
o o 0
o
o
o
1
o
o
o
4
o
o
1
1
o
4
16
16
4
4
4
NOTES FOR CHART ON FOLLOWING PAGES
1. The first memory cycle (M 1) is always an
instruction fetch; the first (or only) byte, containing
the op code, is fetched during this cycle.
13. If the condition was not met, sub-cycles M4 and
M5 are skipped; the processor instead proceeds
immediately to the instruction fetch (M 1) of the next
instruction cycle.
2. If the READY input from memory is not high
during T2 of each memory cycle, the processor will
enter a wait state (TW) until READY is sampled as
high.
14. If the condition was not met, sub-cycles M2 and
M3 are skipped; the processor instead proceeds
immediately to the instruction fetch (M 1) of the next
instruction cycle.
3. States T4 and T5 are present, as required, for
operations which are completely internal to the CPU.
The contents of the internal bus during T4 and T5 are
available at the data bus; this is designed for testing
purposes only. An "X" denotes that the state is
present, but is only used for such internal operations
as instruction decoding.
15. Stack read sub-cycle.
16. Stack write sub-cycle.
17. CONDITION
5.
These states are skipped.
6. Memory read sub-cycles; an instruction or data
word will be read.
7.
Memory write sub-cycle.
000
001
010
011
100
101
110
111
18. I/O sub-cycle: the I/O port's 8-bit select code is
duplicated on address lines 0-7 (A -7 ) and 8-15
O
(A8-15).
8. The READY signal is not required during the
second and third sutrcycles (M2 and M3). The HOLD
signal is accepted during M2 and M3. The SYNC
signal is not generated during M2 and M3. During the
execution of DAD, M2 and M3 are required for an
internal register-pair add; memory is not referenced.
19. Output sub-cycle.
20. The processor will remain idle in the halt state
until an interrupt, a reset or a hold is accepted. When
a hold request is accepted, the CPU enters the hold
mode; after the hold mode is terminated, the
processor returns to the halt state. After a reset is
accepted, the processor begins execution at memory
location zero. After an interrupt is accepted, the
processor executes the instruction forced onto the
data bus (usually a restart instruction).
9. The results of these arithmetic, logical or rotate
instructions are not moved into the accumulator (A)
until state T2 of the next instruction cycle. That is, A
is loaded while the next instruction is being fetched;
this overlapping of operations allows for faster
processing.
10. If the value of the least significant 4-bits of the
accumulator is greater than 9 £!: if the auxiliary carry
bit is set, 6 is added to the accumulator. If the value
of the most significant 4-bits of the accumu lator is
now greater than 9, ~ if the carry bit is set, 6 is
added to the most significant 4-bits of the
accumulator.
11. This represents the first sub-cycle
instruction fetch) of the next instruction cycle.
not zero (Z = 0)
zero (Z = 1)
no carry (CY = 0)
carry (CY = 1)
parity odd (P = 0)
parity even (P = 1)
plus (S = 0)
minus (S = 1)
NZ
Z
NC
C
PO
PE
P
M
4. Only register pairs rp = B (registers B and C) or
rp = D (registers D and E) may be specified.
CCC
SSS or DDD
Value
A
111
000
001
010
011
100
101
B
C
D
E
H
L
(the
12. If the condition was met, the contents of the
register pair WZ are output on the address lines
(A - 15 ) instead of the contents of the program
O
counter (PC).
4-35
rp
Value
B
00
01
10
11
D
H
SP
M1(1)
OPCOoE
MNEMONIC
o7 o S o 5 0 4
03 0 2 0 1 DO
T1
T2[2l
M2
T4
T3
T1
T5
T2[2l
T3
;,.
0
0 S S S
MOVr1,r2
0
1
i)
MOVr,M
0
1
D 0
0
1
MOVM,r
0
1
1
0
S S S
1
1
PC OUT
STATUS
PC = PC +1
INST....TMP/IR
(TMP)-+ODO
(SSS)--TMP
X(3)
0
(SSS)-TMP
(HL)
SPHL
1
1
1
1
1
0
0
1
MVI r, data
0
0
D 0
0
1
1
0
X
MVI M, data
0
0
1
1
0
1
1
0
X
LXI rp, data
0
0
R P
0
0
0
1
LOA addr
0
0
1
1
1
0
STAaddr
0
0
1
1
0
LHLOaddr
0
0
1 0
SHLOaddr
0
0
1
LOAX rp(4)
0
STAX rp(4)
i
HLOUT
STATUS[S)
DATA- f.DOO
HLOUT
STATUS(7)
(TMP)- ~DATA BUS
~P
B2 - .DODO
PC OUT
STATUS(6)
B2- .TMP
X
PC=PC+1
B2- .r1
1 0
X
PC=PC+1
B2- .. Z
0
1 0
X
PC=PC+l
B2- .Z
1
0
1 0
X
PC = PC + 1
B2- f.Z
0
0
0
1 0
X
PC OUT
STATUS(6)
PC=PC+l
B2- ~Z
0
R P
1
0
1
0
X
rpOUT
STATUS(6)
0
0
R P
0
0
1
0
X
rpOUT
STATUS(7]
XCHG
1
1
1
0
1
0
1
1
AOOr
1
0
0
0
0
S S S
ADD M
1
0
0
0
0
1
ADI data
1
1
0
0
0
1
ADCr
1
0
0
0
1
S S S
ADC M
1
0
0
0
1
1
1 0
ACI data
1
1
0
0
1
1
1
SUBr
1
0
0
1
0
S
S S
I
SUI data
SBB r
SBB M
1
1
1
1
0
0
1
1
0
1
0
0
0
0
1
1
0
1
0
1
1
1
1 0
(A)-ACT
HLOUT
STATUS[6)
1
(A)-ACT
PC OUT
STATUS[S)
PC = PC + 1
(SSS)-TMP
(AI-ACT
(9)
(ACT)+(TMP)+CY-A
(A)-ACT
HLOUT
STATUS(6)
(A)--.ACT
PCOUT
STATUS[6]
PC = PC·+ 1
(SSS)-TMP
(A)-ACT
[9]
(ACT)-(TMPI-A
(A)-ACT
HLOUT
STATUS[6]
(A)-ACT
PC OUT
STATUS[6]
PC = PC + 1
(SSS)-TMP
(A)-ACT
[9)
(ACT)-(TMP)-CY-A
(A)-ACT
HLOUT
STATUS{6]
(A)-ACT
PCOUT
STATUS{6]
0
0
I
!
1
I
T
0
1
0
S S S
i
I
I
I
I
~
1 0
I
!
I
1
1
0
1
1
1
1
0
I
INR r
INR M
0
0
0
0
0
1
D
1
D
0
1
1
0
0
0
I
0
0
D D
D
1
0
1
I
I
•
1
I
1
(DDD)-TMP
(TMP) + l-ALU
I
I
i
I
!
0
1
DCR r
!
X
I
0
0
1
1
0
1
0
(DDD)-TMP
(TMP)+1-ALU
B2- .TMP
DATA- f.- TMP
B2- f.-TMP
DATA- f.-TMP
B2- f.-TMP
DATA- f..-TMP
B2- f.- TMP
PC = PC + 1
HLOUT
STATUS{6]
DATA- .TMP
(TMP)+1- .ALU
HLOUT
STATUS{6]
DATA- -.TMP
(TMP)-l - -.ALU
ALU-+DOD
X
1
DATA- .TMP
ALU-DOD
i
I
DCR M
(ACT)+(TMPI-A
(9)
i
SBI data
(Al- .DATA BUS
(SSS)--TMP
(A)-ACT
I
1
DATA- .A
(HL)---(OE)
i
SUB M
~
[<.,
I
INX rp
0
0
R P
0
0
1
1
i
(RP) + 1 - - - - - - 4 ~RP
!
i
DCX rp
0
0
R P
1
0
1
1
I
DAD rp[8]
0
0
R P
1
0
0
1
!
DAA
0
0
1
0
1
1
1
I
0
(RP) -1 - ,
I
I
- ,
~RP
(ril-ACT
(L)--TMP.
(ACT)+(TMP)--A LU
(SSSI--TMP
(A}-+ACT
(9)
(ACT) +(TMP)--A
(A)-ACT
HLOUT
STATUS(6)
X
ALu-+L, CY
DAA-A, F LAGS[10]
I
ANAr
1
0
1
0
0
S S S
ANAM
1
0
1 0
0
1
1
0
!
PC OUT
STATUS
PC=PC+1
•
I NST--TMP/IR
4-36
DATA- -.TMP
M3
M4
T2[21
T1
T3
M5
T2[21
T1
T3
T1
T2[21
T5
T4
T3
..
.
.'
(TMP)- ~DATA BUS
HLOUT
STATUS[7]
PC OUT
STATUS[6]
.....
PC + 1
B3- ~rh
PC = PC + 1
B3- ~W
WZ OUT
STATUS[6]
DATA-
A
PC=PC+l
B3- ~W
WZOUT
STATUS17]
(A)--
DATA BUS
PC=PC+l
B3- ~W
WZOUT
STATUS[6]
DATA--WZ = WZ + 1
L
WZOUT
STAT US [6]
DATA
PC = PC + 1
B3- ~W
WZOUT
STATUS[7]
(L)
DATA BUS
WZOUT
STATUS[7]
(H)- f.oATA BUS
PC
=
....
..
"
PC OUT
STATUS[6]
..
WZ =WZ + 1
f.H
....
':,
.'
.'
..
t
[9]
(ACT)+(TMP)-A
[9]
(ACT)+(TMPI-A
[9]
(ACT)+(TMPI+CY-A
[9]
(ACTI+(TMPI+CY-A
[9]
(ACTI-(TMPI-A
[9]
( ACTI-(TMPI-A
[9]
(ACTI-(TMPI-CY-A
[9]
(ACTI-(TMPI-CY-A
..
,I>
".
"Jr<~:;~!:{\;/
.'
HLOUT
STATUS [7]
ALU- f-DATA BUS
HLOUT
STATUS[7]
ALU- f- DATA BUS
(rhl-ACT
[9]
(HI-TMP
(ACTI+(TMPI+CY-A LU
ALU·~H.
CY
(ACTI+(TMPI-A
4-37
... "
..•...
MNEMONIC
M1(1)
OPCOOE
D7 0 6 0 5 0 4
0302D1 DO
ANI data
1
1
1
0
0
1
1
0
XRAr
1
0
1
0
1
S S
S
XRAM
1
0
1
0
1
1
0
1
T1
PC OUT
STATUS
T2[21
M2
T3
PC = PC + 1 INST-TMP/IR
•
T4
1
1
1
0
1
1
1
0
ORAr
1
0
1
1
0
S S
S
i
ORAM
1
0
1
1
0
1
1
0
T3
PC OUT
STATUS(6)
PC = PC + 1
(A)-ACT
(SSS)-TMP
(9)
(ACT)+(TPM)-A
(A)-ACT
i
T2121
(A I---+A CT
"
XRI data
T1
T5
HLOUT
STATUS(6)
B2_ _TMP
DATA- f--TMP
B2- ~TMP
(A)-ACT
PC OUT
STATUS(6)
PC = PC + 1
(A)-ACT
(SSS)-TMP
[9)
(ACT)+(TMP)--+A
(A)-ACT
HLOUT
STATUS[6]
(A)-ACT
PC OUT
STATUS[6]
PC = PC + 1
(A)-ACT
(SSS)-TMP
[9]
(ACTl-(TMP), FLAGS
i
DATA- f.TMP
ORI data
1
1
1
1
0
1
CMPr
1
0
1
1
1
S S S
CMPM
1
0
1
1
1
1
1
0
(A)-ACT
HLOUT
STATUS[6]
CPI data
1
1
1
1
1
1
1
0
(A)-ACT
PC OUT
STATUS[6]
PC=PC+l
RLC
0
0
0
0
0
1
1
1
(A)-ALU
ROTATE
[9]
ALU-A, CY
RRC
0
0 0
0
1
1
1
1
(A)-ALU
ROTATE
[9]
ALU--+A, CY
RAL
0
0
0
1
0
1
1
1
(A), CY-ALU
ROTATE
[9)
ALU--+A, CY
RAR
0
0
0
1
1
1
1
1
(A), CY-ALU
ROTATE
[9)
ALU--+A,CY
PCOUT
STATUS[6]
PC = PC + 1
B2- .-Z
JUDGE CONDITION
PC OUT
STATUS[6]
PC = PC + 1
B2-
_z
SP = SP - 1
PC OUT
STATUS[6]
PC = PC + 1
B2"
-Z
JUDGE CONDITION
IF TRUE,SP=SP-1
PC OUT
STATUS[6]
PC = PC + 1
B2- f--Z
X
SP OUT
STATUS[15]
SP = SP + 1
DATA,- e-Z
JUDGE CONDITION[14]
SP OUT
STATUS[15]
SP = SP + 1
DATA- .-Z
SP OUT
STATUS[16]
SP = SP - 1
(PCHI - _DATA BUS
SP = SP - 1
SP OUT
STATUS[16]
SP = SP - 1
(rhl
SP = SP - 1
SPOUT
STATUS[16]
SP = SP - 1
(A) ,,_DATA BUS
1
0
I
CMA
0
0
1
0
1
1
1
1
i
B2- _TMP
DATA- _TMP
B2- _TMP
(A)-A
i
CMC
0
0
1
1
1
1
1
1
Cy-CY
I
i
I
STC
0
0
1
1
0
1
1
1
JMP addr
1
1
0
0
0
0
1
1
!
!
l
l--+CY
X
I
I
:
J cond addr [17]
1
1
C
C
C
0
1
0
CALLaddr
1
1
0
0
1
1 0
1
I
C cond addr[17]
1
RET
1
1
0
0
R cond addr[17]
1
1
C
C
1
C
C
1
0
1
0
0
1
C
0
0
0
C
0
I
I
i
!
I
•
I NST--+TMP/IR
I
RST n
1
1
N
N
N 1
1
1
--------------
I
HLOA
- INTA ,-IOR,-MEMR
DURING HL OA
><== -=- -= -= -=-=-== =- == =- == =- -= ~
~= == =- ==- ==== =-= ==><
-----------~\
/
,-.---------------'-
WR
\-----------1/
\ .....__-----'1
lOW OR MEM W
- - - - - - - - - - -------)('---------------------------------------------_.
-
8080 BUS DURING WRITE -
S YS TE M BUS DURING WRI TE - - - - - -
- - -
-
<=____________--'X'-__________________________
SYSTEM BUS ENABLE
SYSTEM BUS OUTPUTS - - - - - -
\'-______-',
-
- - -
-
- -
Loading:
Inputs
D2,D6
STSTB
Others
.46 Unit Load
.31 Unit Load
.16 Unit Load
Outputs
DG-D7
Others
1.25 Unit Loads
9 Unit Loads
4-45
- - <. . . _______,> - - - -
-
- - - - - -
- -
-
MOS Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
Type 8251
Part No. 42336
double buffered. Parallel words can contain up to
eight bits. Serial word length can be 5, 6,7, or 8 bits.
Parity can be even or odd, or parity checking and
generation can be inhibited. The number of stop bits
can be either one or two (or 1-1/2 when word length
= 5 bits). Transmitting and receiving can occur
simultaneously (full-duplex). Transmit and Receive
Clocks must be supplied at 1, 16, or 64 times the
desired baud rate.
The USART is used to interface the serial data
channel of a terminal or communications device to
the parallel data channel of a computer or terminal.
The transmi tter section converts parallel data into
serial words with start bits, stop bits, and (if desired)
parity bits. The receiver section converts serial data
into parallel words, while stripping off the start bits
and stop bits, checking word length, and, if desired,
checking parity. Both the receiver and transmitter are
Logic Symbol
Block Diagram
+5V
26
27 O~
vce
TRANSMIT
BUFFER
(P-S)
28 01
TxD
1 02
03
04
05
TxRDY
TRANSMIT
CONTROL
TxE
_TxC
WR
CS _ _ _---'
DSR
DTR
RxD
CTS
RTS
RxC
RxO
/
RD
TxE
WR
Tx ROY
C/O
RxROY
OSR
DTR
CTS
RTS
SYNDET
CS
GND
INTERNAL
DATA BUS
4
Loading:
Outputs
1 Unit Load
4-46
RxRDY
Rxe
CONTROL
_SVNDET
MOS Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
This is a three-state, bi-di rectional, 8-bit buffer
used to interface the 8251 to the MPU system data
bus. Data, control words, command words, and status
information are transferred through this buffer.
CTS (Clear to Send). A low on this input enables
the 8251 to transmit serial data if the TxN bit in the
command byte is set to a 1.
Read/Write Control Logic
Control inputs from the MPU system are received
and stored here. Control/command bits stored here
influence subsequent 8251 operation.
DTR (Data Terminal Ready) and RTS (Request to
Send). These two outputs can be set low by
programmi ng the appropriate bits in the command
instruction word. They are normally used for modem
control.
RST (Reset). A high on this input forces the 8251
into an "idle" condition, where it remains until a
Mode instruction is received.
Transmit Buffer
This buffer accepts parallel data from the Data Bus
Buffer, converts it to a serial bit stream, inserts the
appropriate characters or bits, and outputs a
composite serial stream of data on the TxD pin. It
consists essentially of two buffers, a transmit buffer
and a holding register.
ClK (Clock). This input is normally driven by the
02 (TTL) output of the 8224 Clock Generator, to
provide timing for internal operations. This clock
must be greater than 30 times the RxC and TxC
frequency for synchronous operation and 4.5 times
for asynchron ous operati on.
Transmit Control
WR (Write). A low on this input signals the 8251
that the MPU is writing (outputting) to the 8251.
This section controls the Transmit Buffer and
provides the signals necessary to synchronize
transmission with the MPU.
RD (Read). A low on this input signals the 8251
that the MPU is reading from the 8251.
Tx RDY (Transmit Ready). This output goes high
to inform the MPU that the transmit holding register
is ready to accept the next character. The MPU can
also check this condition by performing a status read
operation. This output goes low (at least
momentarily) when a character is received from the
MPU, and returns high when the character is
transferred from the holding register to the transmit
buffer.
C/D (Control/Data). Th is input, along with the
WR and RD inputs, informs the 8251 whether the
word on the data bus is a data, control, or status
word.
WR
RD
Function
l
H
X
X
H
l
l
Data
Status
Control
H
H
Type 8251
(Continued)
DSR (Data Set Ready). This input is normally
used to test modem conditions such as Data Set
Ready. Its condition is tested by the MPU performing
a status read operation.
Data Bus Buffer
C/D
Part No. 42336
Tx E (Transmitter Empty). This output goes high
when the transmitter has no more characters to
transmit. It goes low when a character is received
from the MPU.
CS (Chip Select). A low on this input enables the
8251. A high disables all reading and writing and
drives all outputs into the high-impedance state.
TxC (Transmit Clock). The signal applied to this
input controls the rate of data transmission. In
synchronous transmission, the baud rate is the same
as the TxC rate. I n asynchronous transmi ssion, the
TxC rate can be 1, 16, or 64 times the baud rate,
determined by the Mode instruction. The serial data
is sh ifted out of the 8251 on the fall ing edge of TxC.
Modem Control
These inputs and outputs can be used to interface
to the modem, or they can be used for other
functions as desi red.
4-47
Receive Buffer
SYNDET (SYNC Detect). This pin is used in
synchronous mode only, and it can be used as either
an input or an output, programmable through the
Control word. When used as an output, it goes high to
indicate that the 8251 has received a SYNC character.
If the 8251 is programmed to use double SYNC
characters, then SYNDET goes high in the middle of
the last bit of the second SYNC character. The
condition of this output is also available to the MPU
via a status read operation, wh ich automatically resets
the SYNOET condition.
This buffer accepts serial data from the RxD
input, converts it to parallel format, checks for bits or
characters according to the established mode and
control words, and provides this data to the MPU.
Receive Control
This section controls the Receive Buffer and
provides the signals for synchronizing it with the
IVIPU.
SYNDET may be used as an input if the check for
synchron ization is made by external logic. In th is
case, when SYNOET is driven high, the 8251 begins
assembling serial input data into characters on the
falling edge of the next RxC.
RxROY (Receiver Ready). This output goes high
to inform the MPU that the 8251 has a character
ready to be input to the MPU. This condition can also
be checked via a status read operation. The output is
driven low when the character is received by the MPU
(when RO is driven low).
Mode Instruction
RxC (Receiver Clock). The signal applied to this
input controls the rate of data reception. In
synchronous mode, the RxC rate must be the same as
the baud rate. In asynchronous mode, the RxC rate
can be 1, 16, or 64 times the baud rate, as determined
by the Mode instruction. The data on the RxO input
is sampled and shifted into the 8251 on the rising
edge of RxC.
D7
I
S2
D6
D5
D4
I S1 I EP I PEN I
D3
L2
D2
L1
D1
Type 8251
(Continued)
Part No. 42336
MOS Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
The first "control" (C/O high) write after a Reset
loads the Mode instruction into the 8251. Any
subsequent control writes load Command
instructions. The Mode instruction format is as
follows:
DO
I I B2 I B1 I
Baud Rate Farto!_
L=
L
L
Sync
Mode
H
L
LIH
H
H
1x
16x
64x
Character Length
L._________
L
L
H
L
L
H
H
H
5
6
7
8
H
~
No. of bits
Parity enabled
L = Parity disabled
H
Evenparity
parity
L == Odd
L -_ _ _ _ _ _ _ _ _ _ _ _ _
L -_ _ _ _ _ _ _ _ _ _ _ _ _- - I _
H = SYNDET is an Input
L = SYNDET is an Output
L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
H = Single SYNC character
II
I
L = Double SYNC character
I
Synchronous
4-48
Number of Stop Bits
L
H
L
H
L
L
H
H
Not
Used
1
1'12
2
Asynchronous
Part No. 42336
MOS Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
Command Instruction
Type 8251
(Continued)
After the mode instruction has been loaded,
subsequent control writes load the Command
instruction, as follows:
D6
D7
I SYN I RST I
H = Enable Search
for SYNC
L = Normal
H
D5
RTS
I
04
ERR
03
01
02
DO
I BRK I RxE I OTR I TxN I
L
J
H = Enable Transmit
L = Disable Transmit
High forces OTR
output low
= Reset 8251
H = Enable Receive
L = Disable Receive
High forces RTS
output low
H forces TxO low
L = Normal
High resets error
flags PE, FE, OE
Status Read
When a Read operation is performed with the C/O
input high, status is provided to the MPU on the
parallel data bus as follows:
I
Framing Error.
Stop bit not
detected at end
of character
(Async only).
07
DSR
I
06
SYN
OET
I
D5
FE
I
04
OE
I
03
PE
I
D2
TxE
I
I I
I
01
Rx
ROY
I
I
DO
Tx
ROY
I
I-
Same definitions
as output pins
Parity Error.
Received character had
incorrect parity
bit.
Overrun Error.
A second character was received
before the first
was read by the
MPU. First character is lost.
4-49
512 x 8-Bit Programmable Read Only Memory, Three-State
Part No. 10406
These devices are Programmable Read-Only
memories wh ich are normally programmed by the
vendor. No truth table appears here because each
program requires a separate table. Note that the part
number above is the Diablo number for the
unprogrammed pROMs: a new number is assigned
when the pROM is programmed. Part numbers for
programmed pROMs appear on the schematic. Access
time is typically 35 ns (60 ns maximum).
In the LATCHED READ mode, outputs are held
in the ir previous state (1, 0, or Hi-Z) as long as Strobe
is low, regardless of the state of address or chip
enable. A positive Strobe transition causes data from
the applied address to reach the outputs if the chip is
enabled, and causes outputs to go to the Hi-Z state if
the chip is disabled.
Type 82S115
A negative Strobe transition causes outputs to be
locked into their last Read Data condition if the chip
was enabled, or causes outputs to be locked into the
Hi-Z condition if the chip was disabled.
There are two modes of operation. In the
TRANSPARENT READ mode, stored data is
addressed by applying a binary code to the address
inputs while holding Strobe high. In this mode the bit
drivers are controlled solely by CE1 and CE2 lines.
Waveforms
(Times shown are maximum unless noted)
(Times shown are in nanoseconds)
Logic Symbol
A0
3
4
5
6
13
A1
A2
A3
A4
A5
AS
A7
AS
FE1
FE2
, ' , - - - - - - - - - - - - - - - - +3.0
STF!~~~
_____________________________ OV
01
02
03
04
05
06
07
08
r- - - - --- - - -- - - - - - - - - - - - - - - +3.0V
1.5V
~--------------OV
CE
, . . - - - - - -+ 3.0V
CHIP ENABLE
'------OV
CE 2
STR
CE1
CE2
Latched Read
,--------------""
1.5V
VCC-24, GND-12
~------
+3.0V
,__-----+3.0V
CHIP ENABLE
CE
A~-A8
FE1, FE2
STR
CE1, CE2
01-08
Address Inputs
Programming Inputs
Strobe Input
Chip Enable Inputs
Data Outputs
2
STROBE
1.5V
90
Loading:
Inputs
Outputs
OV
~------T7---VOH
.1 Unit Load
6 Unit Loads
4-50
Type 8316
MOS 2K x 8 Masked ROM
This is a Read-Only Memory that is programmed
during manufacture. No part number is given because
each program requires a separate part number. Part
numbers are given on the schematics. Outputs are
3-state, controlled by three programmable chip-select
inputs. Any combination of high- or low-active chip
select inputs can be defined, and the desired chip
select code is programmed into the chip during manufacture. Maximum access time is 1.5 J1S. Only a single
power supply voltage (+5V) is required.
Logic Symbol
5
A9J
6
AI
7
A2
8
A3
A4
A5
A6
A7
A8
A9
AIO
CS1
CS2
CS3
01
02
07
08 16
VCC-24, GN D-12
Waveforms
(All times shown are maximum)
ADDRESS
500 ns
500 ns
PROGRAMMABLE
CHIP
SELECTS
ACCESS TIME
VO H
~ 7'71 ""'
DATA OUTPUT
OUTPUT VALID
I'----------~ -
VOL
Loading:
Outputs
1.1 Unit Loads
4-51
,;;r "" - ... ,7,"
OUTPUT HIGH I
IMPEDANCE
't.:i. .... .;.-
- . . . "'"'
MOS 1024 x 8-Bit Electrically-Alterable ROM
Part No. 42329
This Read-Only Memory is programmed at the
Diablo factory. It has a transparent quartz lid which
allows exposure to ultraviolet light to erase the bit
pattern. It is electrically compatible with the type
8308 ROM. Access time is 450 ns. Outputs are
3-state, controlled by the Chip Select (CS) input.
Type 8708
Logic Symbol
+ 5V
+12V
01 9
A5
A6
A7
AS
A9
VBS =
VCC =
VDD =
VSS =
07
08
+5V
+5V
+12V
GND
PRGM
CSjWE
VSS
12
-5V
Waveforms
(All times shown are maximum)
ADDRESS
120n5
120n5
CS/WE
ACCESS TIME
450n5
~H---------------------DATA OUTPUT
OUTPUT HIGH IMPEDANCE
~L----------------------Loading:
Outputs
1 Unit Load
4-52
\,------------,
OUTPUT VALID
-- - -- -OUTPUT HIGH
IMPEDANCE
1'-------------' - - -
- - - --
MOS 256 x 4-Bit Static RAM, 3-State
Part No. 42334-11
Type 2111A-4
This is the 450 ns member of a family of
random-access memories available in several speed
ranges. The Output Disable pin (9), when high, drives
the Input/Output pins to their high-impedance state.
Logic Symbol
+5V
4
00
CE1
eE2.
R/W
GNO
Timing Waveforms
(All times are minimum unless noted)
Write Cycle
Read Cycle
450 ns
400 ns
ADDRESS
250 na
310 n.s mal(
CHIP
CHIP
ENABLES
ENABLES
(CEI CE2)
OUTPUT
OUTPUT
DISABLE
DISABLE
250 nl
DATA OUT
DATA I/O
DATA IN
STABLE
DATA I/o
VALID
250 ns
READ/
WRITE
Loading:
Outputs
1.25 Unit Loads
4-53
20 ns
Type SW-10667
DTL Pulse Generator
Part No. 14027
This is a custom Ie used in Micro Switch
keyboards to produce the keyboard Strobe pulses. It
includes a repeat circuit with an initial delay and two
independent DTL NAND gates. It requires two
external resistors and one capacitor: the resistor
connected between pins 1 and 3 determines the
length of time between repeat pulses; the resistor
between pins 3 and 4 adjusts the initial delay (the
initial delay is a function of both resistors); the
capacitor determines the length of the entire repeat
cycle ("on" time plus "off" time) and also affects the
initial delay. The repeat pulses are produced (after
the initial delay) when the Enable input is driven
high; with Enable Low, the Strobe input pulses pass
through unchanged.
Note the
connections.
Logic Sy mbol
1
5
14
2
_---I
3
4
TIME DLY
vee
E
OUT
STB
13
ADJ
GND
I
12
Loading:
Inputs
Outputs
Gate 1 (pin 8)
Other
1 Unit Load
3.75 Unit Loads
2.5 Unit Loads
4-54
non-standard
vee
and
GND
Part No. 42168-XX
Phototransistor Opto-Isolator
Th is circu it element consists of a solid-state
gallium arsenide diode lamp optically coupled to an
NPN silicon planar phototransistor. Its function is to
couple two circuits optically, while isolating them
electrically.
TypeTIL-117
Logic Symbol
Absolute Maximum Ratings
(@ 25°C)
Input Diode
Output Transistor
Forward Current 60 mA
Power Dissipation 100 mW
Reverse Voltage
3V
Power Dissipation 150 mW
VCE
30 V
VCB
70V
VEC
5V
Isolation: 42168-01
1500 volts
Type MCT2
MCT2E
Part No. 42190-01
Phototransistor Opto-Isolator
This circuit element consists of a solid-state gall ium
arsenide diode lamp optically coupled to an NPN sil icon
planar phototransistor. It is mounted in a six-lead plastic
DIP. Its function is to couple two circuits optically, while
isolating them electrically.
Circuit 1
Logic Symbol
Circuit 2
Absolute Maximum Ratings
(@ 25°C)
Forward Current 60 mA
Power Dissipation 200 mW
Reverse Voltage
3V
Isolation: 2500 volts
4-55
Power Dissipation 200 mW
VCE
30 V
VCB
70 V
7V
VEC
Part No. 42191-33
Keyboard Encoder
Type MM5873
This is a 128 key non-programmed MOS/LSI
Scanner, in a 28- Lead dual-in-line package. Used in
Cortron Up/Dn stroke keyboard. Supply Voltages:
Logic Symbol
Vss
Vdd
Vgg
5V at 40 mAo
OV at 50 mA (for TTL outputs).
-12V at 40 mAo
+5V
The device has 12 TTL/DTL outputs which are
capable of sinking 1.6 rnA. These outputs are:
Pin
12. <1>1
13.<1>3
14. Strobe
18 SRIN
28
VSS
Pin
Flag (FF)
18.
Shift Register Out
19.
21.-27. 81 through 87
A1
9
A2 8
A3
A4
A5
AS
A7
Each of these
specifications:
outputs
has
the
following
2.4V min. at 100 uA
O.4V max. at 1.6 mA
Logic "1" (high)
Logic "0" (low)
17
The device has 7 standard TTL/DTL compatible
outputs, each capable of sinking 3.2 mAo These
outputs are A 1 through A7.
Each of these
specifications:
outputs
has
the
16
NKR/2KR
following
eLK IN
2.4V min. at 200 uA.
O.4V max. at 3.2 mAo
This device has 6 logic inputs:
Pin
10. Data in (SRIN)
11. Clock in
15. Latch Inhibit
B1
B2
B3
LI
85
86
B7
,¢'1
FF
Pin
16. NKR/2KR
17. Function (FN)
20. 8ypass shift logic
8SL
VDD
1
Each input has the following specification:
SRO
¢3
STB
VGG
2
-12V
Vin (Logic 1)
Vin (Logic 0)
27
84
11
Logic "1" (high)
Logic "0" (low)
FN
Vss -2V min.
Vss +0.3V max.
Vgg min.
Vss -4.0V max.
A pull-up resistor is provided for each input on the
device.
4-56
21
12
10
MOS Decoder/Encoder
Part No. 14026
Type SW-20314
This is a custom Ie used in Micro Switch
keyboards to accomplish the keyswitch
decoding/output encoding functions. It has eight
output latches which store the decoded output data
until it is replaced by newer data. Note the
non-standard power and ground connections.
Logic Symbol
+5V
26
1
A
2
B
3
C
4
0
5
E
6
F
7
8
9
10
11
vee
G
H
STB
24
vee
VGG
B~
81
B2
~
K
83
L
M
N
85
15
14
CTRL
86
SHIFT
VGG
-12V
4-57
=
=
+5V
-12V
Part No. 10353
Dual Line Driver
This line driver is commonly used to interface data
terminal equipment to data communication equip-
Type 75150P
ment utilizing the E IA Standard RS-232-C. Input is
TTL/DTL compatible, and output is ±12V.
Logic Symbol
Truth Table
+12V
r-
21
I
I
1
STB 1
31
2A
_ f~
INPUTS
-,
17
1A
I
1
16
I
1Y
2Y
~5--~-l
L
OUTPUT
STB
A
Y
L
H
H
X
+12
+12
-12
L
H
L
OV
H
X
+5V
Irrelevant
-12V
Alternate Symbols
+12V
+12V
-_ta-
r
21
1
8
1
~
2
I
16
31
3
I
1,5- ~_I
L
4
vcc+
STB
lA
1Y
2A
2Y
GND
VCC-
-12V
5
-12V
Loading:
Inputs
Strobe
1 Unit Load
2 Unit Loads
4-58
7
6
Quadruple Line Receiver
Part No. 10354
This receiver satisfies the requirements of the
interface between data communication equipment
and data terminal equipment as defined by E IA Standard RS-232-C. Input is from +25V to -25V, and output is either OV or +5V. For normal operation, the
threshold control terminal is connected to VCC1.
This provides a wide hysteresis loop which is the difference between the positive-going and negative-going
threshold levels. In this mode of operation, if the
input voltage goes to zero (or open-circuit), the out-
Type 75154
put will remain either low (OV) or high (+5V) as
determined by the previous input. For fail-safe operation, the threshold terminal is left floating. This reduces the hysteresis loop, causing the negative-going
threshold to be above OV. The positive-going threshold is unchanged. In this mode, if the input voltage
goes to OV or is open-circuited, the output goes high
(+5V) regardless of the previous input condition.
vee can be either +5V or +12V. Pin 9 should not be
connected externally.
Logic Symbol
Alternate Symbol
vee1 VCC2
J!5J~ ~6
1A
4:
3
I
1
~13
I
1T
2A
' 12 2y
•
2T
•I 11
3A
3T
3Y
14:
'10 4y
A
y
t_
I
T
-]8 _I
VCC1
VCC2
Truth Table
(each receiver)
A
OUTPUT
Y
I
:'I ~,
L (0)
I
I
I
I
i
i
FAIL-SAFE..~
OPERATION
O~~:!'T~~~
-,
2
I
4Y
>T
I-
i,.
------if---ft---
-"
I-
"
.1.
"
o ~,
-25
I -1------ f------i
1-
-4
Loading:
10 Unit Loads
4-59
-3
-2
-I
o
2
r---
-- f--------it---
---"
1-
~f,
Outputs
3Y
~~
h
H (+5)
-12
+12
3A
2Y
Waveforms
4
INPUT
1Y
input
output
threshold
control
+5V
+12V
1
1
1A
2A
4A
8
GND
J
4A
4T
2T
3T
4T
1Y
1
I
I
---i't--I
I
3
4
,:==.
25
Dual AND-Gate Peripheral Driver
Type 75451
Part No. 10181
Logic Symbol
1
1AD-1Y
Truth Table
18 2
A
B
y
6
L
L
L
H
28 7
H
H
H
L
L
L
H
2A~2Y
L
VCC8, GND-4
Loading:
Input
Output
1 Unit Load
300ma
High-Speed Dual Comparator
Part No.1 0168
Type LM319
This device can operate on voltage supplies up to
±15V, but can also operate off of a single +5V
supply, depending upon the application. Note the
non-standard voltage connections.
Logic Symbol
+1 N 1
Alternate Symbol
12
-IN 1
OUT 1
GND1
+IN 2 9
-IN 2 10
7
OUT 2
GND 2
V+, pin 11
V-, pin 6
4-60
Part No. 42155-05
Part No. 42155-12
3- Terminal Negative Voltage Regulator, 5 Volt
3-Terminal Negative Voltage Regulator, 12 Volt
providing current
protecti on.
This series of negative regulators provides precision
regulation of output currents up to .5A, while also
Type LM320H-5
Type LM320H-12
limiting and
Logic Symbol
thermal
overload
Pinout
(Bottom View)
OUT
IN
OUT
GNO
IN
GND
Maximum Voltages
I
I
IN
OUT
-05
-7 to -25
-4.8 to -5.2
-12
-14 to -35
-11.6to-12.4
3- Terminal Positive Voltage Regulator, 12-Volt
Part No. 42154-12
This series of positive regulators provides precision
regulation of output currents up to .5A, while also
providing current
protection.
IN t
1.'
2
limiting and
thermal
overload
Pinout
(Top View)
Logic Symbol
~
Type LM341P-12
0
OUT
GND
Input (1)
Output (2)
=
+14.8 to +27V
+11.4 to +12.6V
4-61
] ~
2
3
Part No. 10321 (DIP), 10477 (TO-5)
Voltage Regulator
Th is device is used primarily in series regulator
applications. It can supply output current up to
150 mA, but larger currents can be controlled by
using the output to drive external transistors. It features extremely low standby current drain, provision
for either Iinear or foldback current limiting, up to
40V maximum input voltage, and an output voltage
Type 723
range of 2V to 37V. It contains a 7V reference
source, which can be utilized through suitable external resistors to provide any desired output voltage.
An external reference can also be used, if desired. The
Vz output is not provided in the TO-5 package: if
required, a 6.2V zener diode should be connected in
series with V -OUT.
Logic Symbols
Alternate Symbol
9
2
3
FREQ 1_3_:_+-_ __
COMP
I
j
~_=2 CURRENT
LIMIT
I
:- -li-
'--_ _3;:;..
~
- - - -
CURRENT
SENSE
v- DIP
5
TO-5
Logic Diagram
V+
ERROR
AMPLIFIER
FREQ CaMP
VC
INVERTING
INPUT
VOLTAGE
REFERENCE
AMPLIFIER
>-__---u
CURRENT
LIMITER
V - REF
NON-INVERTING
V-OUT
INPUT
VZ
VCURRENT LIMIT
NC
CURRENT
CURRENT
INV
NON-INV
LIMIT
SENSE
INPUT
2
:3
4
INPUT
5
V-REF
b
v-
7
DIP
CURRENT
SENSE
Type LM733C
Part No. 10124
Differential Video Ampl ifier
Th is d i ffere n ti a 1- in put/d iffe re nti a I-output
amplifier provides selectable gains of 10, 100, and
400.
Logic Symbol
Gain Selection
G2A G1A
IN 1
IN 2
14
1
~11
8
>7
1::
OUT 1
Gain
Connection
10
100
400
None
G 1A to G 18
G2A to G28
OUT 2
G2B G1B
V+,10
V-,5
(No connection to pins 2, 6,9, and 13)
OP Amp, High Slew Rate
Part No. 10167
Type MC1741SCPl
This device exhibits fast settling time, a high slew
rate
(10V/microsecond min.), low power
consumption, and short-circuit protection. It is
housed in an 8-pin DIP.
Logic Symbol
vec =
VEE =
4-63
+15V
-15V
Dual Op Amp, General Purpose
Dual Op Amp, Selected
Part No. 10165
Part No. 13072
Type 72747
Type 72747
Logic Sy mbol
vee +
+IN
2
12
6
OUT
10
7
- IN
3 N1
N2
VCC-4, No Connection -11
Part No. 10166
Op Amp, General Purpose
This single op amp is housed in an 8-pin DIP.
Logic Symbol
VCC+
Pin 1 = Offset null/Comp
Pin 5 = Offset null (N2)
Pin 8 = Comp
+IN
3
-IN
2
~
V
7
6
4
VCC-
4-64
OUT
Type 72748
NPN Transistor Array
Type CA3086
Part No. 42191-32
This device consists of five general-purpose silicon
NPN transistors on a common monolithic substrate.
Two of the transistors are internally connected to
form a differentially-connected pair.
Logic Symbol
4
9
3
2
6
12
(083-040)
Quad Field Effect Transistor (FET)
This
FETs.
IC contains four
Type 8041
Part No. 10190
independent p-channel
Logic Symbol
3
6
11
14
2
16
4-65
Type 1408 L-6
Digital-to-Analog Converter
Part No. 13060
This eight-bit multiplying D-to-A converter
provides a current output which is the product of a
digital word (applied to the A 1-A8 inputs) and an
analog reference voltage (applied to the VR+ and VRinputs). Digital inputs are TTL and CMOS
compatible. Output voltage swing is +0.5V to -0.6V
with the Range Control (pin 1) grounded; leaving
pin 1 open enables the negative voltage swi ng to reach
-5V when maximum power supply voltages are
applied. Frequency compensation capacitors are
connected to pin 16. Note the non-standard vce and
GND connections.
Alternate Symbol
Logic Symbol
12
MSB 5
A2
A3
A4
A5
4
1
OUT
4
15
AS
A7
2
AS
NOTE: VCC-13, GND-2
vce =
+5V
VEE = -5V to -15V (current source)
VRVR+
=
=
Loading:
Inputs (digital)
Output
1 Unit Load
2.0 mao
4-66
-15V (max.)
+5V (max.)
Resistor Network, 1 K x 15
Resistor Network, 1K x 13
Part No.1 0239-01
Pinout
Pinout
16
15
14
13
12
11
10
9
2
3
4
5
6
7
8
Resistor Network, Quad 10K x 2
Part No. 10761
14
13
12
tt
10
9
8
2
3
4
5
6
7
Table 4-2 lists the schematics and
contained in the remainder of this manual.
Part No. 13044
Pinout
logic drawings
Table 4-2. Schematics and Logic Drawings
Drawing Number
Description
2
23702-99
23704-99
40644-03
40510-XX
40520-04
40515-03
40525-06
40530-08
23940
23897
400512·01
23708
40614
46080-01
26021
400062-XX
24471
23859
23732
3
8
9
14~--
10
12
13
(Pins 4 and 11, no connection)
4.6
ASCII CODE CHART
Appendix A of the Product Description manual, the
ASCII code chart, is reproduced in Figure 4-2 for convenience.
4.7
HPR01 Board
HPR02 Board
8080 INTER FACE Board
LOGIC-2 Board
SERVO Board
XDCR Brd
CAR PWR AMP Board
PW PWR AMP Board
PW Assy. HCURL Board
Keyboard Assy. (Hall-effect)
Keyboard Assy. (Cortron)
Control Panel Assy., HPCPN
Mother Board
Mother Board
Power Supply (Boschert)
Power Supply (LHR)
Printer Cables
Power Distribution
Signal Cables
Diablo Systems can provide schematics for older un"its
and specially-built units. Contact your local Diablo representative, and provide circuit board part numbers and
revision levels for fastest service.
SCHEMATICS AND LOGIC DRAWINGS
Figure 4-3 explains the meaning of the various notations
contained on the logic drawings and schematics. For more
information on component locations and connector pin
numbers, etc., see Section 3.
4-67
Resistor Network, 1K x 15
Resistor Network, 1K x 13
Part No. 10239-01
Pinout
Pinout
16
15
14
13
12
11
10
9
2
3
4
5
6
7
8
Resistor Network, Quad 10K x 2
14
13
12
11
10
9
8
2
3
4
5
6
7
Table 4-2 lists the schematics and
contained in the remainder of this manual.
Part No. 13044
Pinout
Table 4-2.
7 ____--..1
9
23702
23704
40644-XX
40644-03
40510 Rev. L
40510 Rev. U
40520-03
40520-04
40515
40525-XX
40525-05
40530-XX
40530-07
40614
23708
23710
23897
24471
26021
26021
23836-01
23836-01
23836-02
23836-02
23859
23732
6
3
8
5
14----.. . J
10
12
13
(Pins 4 and 11, no connection)
4.6
ASCII CODE CHART
Appendix A of the Product Descri ption manual, the
ASCII code chart, is reproduced in Figure 4-2 for convenience.
4.7
SCHEMATICS AND LOGIC DRAWINGS
Figure 4-3 explains the meaning of the various notations
contained on the logic drawings and schematics. For more
information on component locations and connector pin
numbers, etc., see Section 3.
4-68
logic drawings
Schematics and Logic Drawings
Drawing Number
2
Part No. 10761
Description
HPR01 Board
HPR02 Board
8080 INTERFACE Board
8080 INTERFACE Board
LOG IC-2 Board
LOGIC-2 Board
SERVO Board
SERVO Board
XDCR Board
CAR PWR AMP Board
CAR PWR AMP Board
PW PWR AMP Board
PW PWR AMP Board
Mother Board
Control Panel Assy., HPCPN
Control Panel Assy., HPCPL
Keyboard Assy.
Printer Cables
Power Supply
Power Supply Assy.
Power Supply, 115v.
Power Supply, 115v., Assy.
Power Supply, 220v.
Power Supply, 220v., Assy.
Power Distribution
Signal Cables
+ INDICATES
ACTIVE HIGH
SIGNAL NAME
COORDINATE OF SIGNAL
INPUT ON THIS LOGIC
DRAWING (SHEET 31
COORDINATE LOCATION
OF IC ON CIRCUIT BOARD
.. AOOII"
•
lloU-.,,'
----~-:-:::~::
:~~:--i-:"::::::
NOTESI U'H.l:'& OTIoi[IIIWtft(
SPECI~IEO.
1. ALL "£SI8TANC[S 91"(Clfl[0 IN 0104M5.
:
2.ALl "ES,STOft!> "'"E ~~W,nT.'!:~""'.'
l .... lLC .. P ... CITANC(S .. tCl',[OIN ... ICIlO' ...., ... 05 •
•• +~~ TO PIN '4 OF 1!-+~t-.::.-.::.~1~
A2
17 A3
STSTB:>IRST ...,.:.ROY ~
r /0 3
I/O 4
.t---+-++---'-~~ ~:
865
7
'-H_t_rf-H---::-l
:;
2111
L--f---------------e>----+-H-t---1-+4~--~9 00
L---+---------------~
15
10
+DA3
Al
1 A2
L---+---'-i A3
~-r+H----------t_----------------~r+--+~r+---:~,~~,D2
I/O 3
~----......------'~---'~14
TL-___________
5H2 - K 16. SH3 - K16
+
T
L-__________
~
---I~~
~
658
E45
SH 2 - K16. S H3 - K 16
22
0.1
15V
12V
A22 ~ A49 A73 ~ ~
Q.1 D 19 032 041 059
m
~
U1
E75
F25
F57 F74 639
H
A65
7:~
L------------+f-:-::-=--15--=9'"'OD
21'1
R/W
116
"NO
J1
~_8
J2
DRVR DB2~~-'-'1~r+-----------------r------------------~
02
L-----~?~~~HLD~
....L."-C5USE,'
~~~~s~~+-.--------------~----------------------~
Dc 5
110
I
.:'~ ~'
lST3T8
- RE~.;;\
~ I·--------Ti -----~-W-R-IT
•
Ii
E
227
+ CLEAR
I/O W
GNC
(
'~~::~:~==--==-:~---.--__-.____ -====--=[~-_ -_~-_-_-____-- _- _- _.-----------~====~JJ
-------------------------~
7307 i
c
Z fEt,
7"':
,"H--------------,-----+_H++t-I-f>-------7
1 "-1018
A 5
DS1
13
~ ~~2
+0A 7
5B
~g ~ f.!.10"-.--------------~67 ~
DI 5
1..-------------------....--.--+---------------------t-+t-I-t....---------:2;. ;0i;-lD I 6
+OA 6
..
001
I..----------.....f---+--+---+---+---+------------------+_~>-------------__:;~~ ~~
SH 1 - G7 ::
SH1 _ G7 _~~--~+-O~A~4~----------------------~
SH1 -G7
!
..------------4.__i--_i--_i--_i---t--_i--------------------t-<1It-----------:;-,5 DIZl ° PO~T DO Z ~
+ 0 A1
-
K
!!ll~~~Q7
13K >13K >13K
10
DOS 17
Br,z
~~ ~
-----;0 EN P 74163
~ ':'CNLTK CAR ~
DO °0 67 ~
DOB~
821Z
Q
B:3 3
,-~.
C
,---
Yl
I~T~
LOAD
-#LS_T_B__,;.,C..-__-'
L-____+-+____________-t-__3~A
QA 14
L-______r_+------------+~4~8 CNTRQB~
L -_____-+__~-----------+_~: C 033 QC~
L--------t--+-------------r_~7~0 -- QD~
r------'y 14
SH3-H3
~~~-----P-O-R-T-1--------------------------------~
SH1 _ B7
_.~---'+~'~2...:T---------------------------------------------------------------------+-H++t-I-t+i-t---------------------------~---------------~-~2i>E~:K CARrl"-5---~9~A50')(~8'--~-------------2-X---C-O-M--M--C-L--K---~:SH3- j16
~ EN P 74163
J
C
7404
Yl
+ 5V
;:.
H
>~ >~~~< ~~~ >~§>AB >~
~'K ~lK
P2
$lK
<
lK <'1K
J"3
)1K <'1K '>1K
13~---D~A...:T-'A-'-~~-------------------------4.-_i---+--_i---+--_t--_t--_t------~~ Dll~OPORTOOI~:'--~+-~-+++-~-t-+--~~~D[1~0~RTD01~:~==============~===========================,----------------------------------------B-E-L_L
__~6
002
OIZ
_.-
r-~.---r_--t_--r_~r___1I____1r_----~7;..,DI2
16
r_----DA-T-A---I---------------------------'
I
_
Jr-----<....--+---t---t---t---t------C9ic1 D13
DATA 2
18 r _ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
G
8
1
r--------~--+--+--+------:-;1B~DI5
20 ~~ ~
20 l-_--=.O...:A...:TA___
3_______________________--'
r-;~~~~~~~~~~~~~~:~~~~~~"C:l-';!.62 ~~~
19~-_,-D-A-TA--4--------------------------~
A20
17~---D-A-T-A--5-------------------------------'
,2!.
STB
9 013
16 014
-
~~~ 19
008 21
INT ~
2 DS2
-=
10
8212
~IAD
~
16
r - - -__
DIS
20 ~i~
-t-++--:1c::~-{J2 ~~~
S
15
A34
821 2
STB
7
~~;
2J
008
3.!
-
INT ~
..... ~MD
~
'--________________________________
-_E_R_R__
O_R__-{
D03;Q--D04
005.",--
""-+--'-""'2::-1 05 2
C
C
14
14
- DATA
G
15~---------------------------------------'
F
DOZc
D04 15
D05 17
003
r-------~-+--+--+--+-----Cl,.::5'1D[4
7
,
14)---~DA-T~A~7--------------------------------~
SHl
-87 _-....___
+_C~L~E_A...:R______________________________________4-+-__~1~31'A~~~""~1~Z------~------~--------------~----~~~----------~-------+-+--------~,________________________________________________________-_C__L_E_A_R____.
~. SH3-B16
-SH3-H3
SH 3 -
j:3
SH1 - B7
E
-
~~~-----P~O~R~T~¢~--------------------------------~.,---------7-4-04--------t_----.--____________---'
+ READ
- WRITE
11 A50~'0'--------+_----------------------------~
~
+5V
<
~
S
7404
+5V
I~Kl0
E
lK
PULL UP 1
XIO,~+_-----------------------------------------------------+_4-----------------~~----------------____________________~~~~~~~~~~~
__~~..
+ PAR
i
~
E22-8
I~,J
~~-F~
DATA INTERRUPT
~~-+--K-Y-S-T-B---------------------------------------~------------~11 ~~
474- 8
~
C
o
. . SHl
SHl
-El7 ,SH3
,SH3-J16
-j17
-<;16
,
Qr-
r3~
_____________________________________+~B~U~S~Y~9P2
o
L'_3_________________________________________________________+_~----'1!A~50~~~L----------~1~7432
+ 1? V
7404
r ---is_ -_-,
: ~
75 1 5¢
---0.
L -________________________________3::....:..'
+sv
c
:
c.
A18
1
L'--~_v'/""v,,'V'---'-'-:.....>-(~).J
SH3-K3 4 .
~-----D-T~R---------------_---------------------------------------------------------------.
_______________________________________________'_K__~2~:---a
p
1
:,;
+ 0 P T rON 0 N J" 1
r-,=-----------------------=---~-'-~-'-~2
c
,
:7
+
DATA TERMINAL READY
r-:~--------------------------___{3
SCHEMATIC DIAGRAM
Ll---~~
~ o;.blo .,,!em, Inco'po,"'ed
-12V
B
a
PW ASSY HP ROI
1610/1G20
,-
A
4-72
.R'OC:· _0
23702-9S
I
, r·
r··
lA
IS
104
I
•
13
r
r
.I
12
( : t
'" J
R~ •
l~~~~ 76 A
11
o
(C--'
n~b~ Lit~·~~" )~'~.' r;-~~ 1./Lr.~
.. ,:
73b7
.:.
S;E~76
B
7
r;;;
12- 4
A'S
-';'5\
r~:" {~:-: t:~v~:":'~ ~'~c--1-T-"-RV--3-+C;'"2" -jYrf'fTDF'-'~:";3 702 - is --E A
I
3
,.,
I
.8
17
I
I
PRODUCT NO.
-
16
I
I
14
15
,
13
11
12
,
10
•
9
23702-99
r-----~~;_~~~+~D~A~~~----------------_,
SH1:n
:
L
:
l
-:"---'-:--'~::";::":"::~=---------------'l~---.-.-------------------------------------------~...-----...!~~~ ~~
-I• •__+_-'D'-'A-'-'4_ _ _ _ _ _. _ _
~ ~~
USART
SHI - G7
SHI - G7
--1...--+.:.--=D:.:A..:-.::5~-----------------.---.· ..- - . - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + H + + 1...
--624 OS
r -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
__
045
DA 1
~~_===
-+~~~~
-1...--+.:.--=D:.;A~6~--------------------- ('
F7
_A_ 7___________________._ .....!i'i-·-------------------------------------------+-1-++Hf-++...!~~~ RZ:K
--1.......__+__o
SHI
87
R_______________.___ .. __
-'......__+-=--_C:cl=.;E::;Ac:.:.:
-'...--+-=---'''~2..:.T------------------.-T
. ._ji
SHI -- 87
f7'.
\:..J
(;;\
-
~5V
'1519 !l6
vecI Rl veC2
~ n
-",2 2T RCVR
+ DATA SET READY
~_....;...---"'-'-'-'-'-'-...c:..=....:.-":=:.=-'---------------I
J"1
{
J
f9\
_
2X COMM ClK
SH' - 67
SHI - L 7
,
Y
2A
~
4A
4 Y f'-"-
~ [GNO
:.
..
--1-. .--+-~A-D~D~R~4-------------,1
~
r!-L
12
-n'~:;A75'54 ,y3Y~
fjf--
I
i
PULL UP 1
READ
WRITE
5HZ -
H
~~
lA U
~
~
+ CARRIER DETECT
~I-....;....:.....::..:...:...;..;..;..=-:..:.....::..::...c.=::....:..------------
'2
4
5
P4
0 Q
,,">==__+_-3:::.{>DC-LFKF
034 .... 6
7432
A8
7~4Q.!...
RxC
RxO
R
0
- 12V
J
-
+ READ
~404
l
J '
________________
~
LTs--J!
V
_ "'-
'--u""""
~-+-----------------J
+ ADDR 2
-1....--~~
+5V
j
..
~
+
+
_
...
A2 E36
I.
ADDRDATA
3
PAR
INTERRUPT
FKY 2
L -_ _ _
0 -
KEYBOARD MODE
FKY 1_~
()_3~-~
t::\
FKY 4
-
~---...:F...:U..:.N:.....S=-W-I-T-C-H-4---------------.
6
T~{ 431 ~_--'~~~~~~
______________~
FUN SWITC H 5
"
oJ
, -
11
r
E
..::x:.
----1r~
5~
il
O:3~'~z----------__,
4
H
.-~ -~-£. &
9
+5V
r4\~~ ___________ ,
+SV
II ;...!~ _________
>.>.>.:<' ><:.> >c:.> > 'K
'I
r;-+1",-;,--_.J~H++-I_-~~~ OJ, rIo
L-L-t=6+8=-j-r:,o+,,,-1r:'2=t='3t=2t-'-t=9-t7.:..-t=5+4_-_J_L-t2=-j-r:'3't'-""I
0r1;+9=-j-r:;+3::..,-
18 °01 5 ~ DOS 17
' - - - - - - - - - - - - - -...H-++-H+++---~+-H~+-H---+-H++--:2"'::-10 r 6
006 r.'' '"9+_1_++H
-
FUN SWITCH 7
' - - - - - - - - - - - - - - - - - - -__H++_H-+--__1_++_~_+++_--_+~_t_1H-~2~2 ~~~
~~~r2~1+_1_++_H+.
OSI 8212 23
,052
INT::):
~ ~~B C
13~--.:.....:F-=U~N~S~W..:..:...;IT~C..:.H~8:..:.-------------~
f?\
-
FUN SWITCH 16
(:;'I.
-
FUN SWITCH 17
f3\ -
FUN SWITCH 18
ot15' ~
•
E
~'4
L - - - - - - - - . - - - - - - - - - - - - - -...++_I--+-+-+----+-t-t-t-+-t-+-I----t-t-t-++-++7i~ OJ, 1/0 DOl ~~
'---------------------~~t-H---~--++~H+--__1H++-~H~7~~~~::~~ ~
~22
+
D
~__--,Y.'4
3
5
or1
I/O DO'
c
4
t-
I
7 or2po~D02 t-~------------__------------------------------____--------~~-+;-~-----r--~-+-+~~9 ~~~ g~~ ~
:: 015 020 005"":.;..;___--'
~1_--+_--+++_E20~ ~~~- ~~~ 1-::'~9----...J
2
1~2 DIS
FUN SWITCH 19
1J
FUN SWITCH 20
'-+--+-1,-=-f!"
':-l2
n
~ 0;001._1n_
D08 r ""_ _ _ _ _--'
~F 82~~T rF-3
-=-_~ 'r-'1'
STB
SYSTEM CLOCK
~S-C-H-E-M-A-T-m--D-I-A-G-R-A-M------__rr
PW ASSY
C
r 16 "r
15
I'
14
A
-=
L
I J==:~L
13
'-n-: 7::US
~
n
...
Jot .
i)
10
•
9
•
rVS I I
lL~(j,¥~~(··:I.IJ\~~.,rr~t ~lN;~W 12-11-'7;1
7
6
, 5
3
THRU
I
•
HP R01
1610/1620
,"DOH
~....----~C~L=E~A~R-----------------------------------------------------------------------________________________-4~--~y'4
Ahl••~:,,"!'!":.~"-2-37-0-2---99.....1
17
F
L-------------------------------------------...H+------t-+++_~~+_----_+++-1H~-+.~9 014
004r.'0:'-+-1-~
L----------------------------------------~~~--H++-rt+~~--++-H+_+~'6~or5
D05r.'~5+_~+.
'------------------------------------------...t----++_rt++_~----+_H~t-+_~'~8 Ole ~ D06~''''"7~++~
L--------------------------------------------------4~-----t-rt+-t-~+------Irt-r+-r-+_I~20~017
D07r.'~9+_~++_r.
,--++_+-+=~!:..j2 018
D08 1-"2;. l. 1~_++H+.
1200 BAUD
14t--___F_U_N_S_W_I_T_C_H__
'3___________________,
F23
'--++--t-r."3;Q Os, 8 212 23
r----, A
2 OSZ
1NT :>=
- FUN SWITC H 14
I
I L!ID
r-~~ ~~B c
\J
SHZ -n
G
--------d<
\Z)
5Hl - 87
-...:P:....O=..R:.,:.T.:....,.:5=---_<50
~
FUN SWITC H 6
~I--...;"...-=-.:....:-"-'...:.:....;"...-'-=-----------,I
•
__________
~_ _ _ _ _ _ _ _~_++_~H+~_+~+_--_++~-++~---+~_++_-~7H~:~~~~~~
'-------------t-++t-H-+t-H-+---t-+~_t_1r+++_--_+++-H--___:,~~ OJ4
004 r.~O::-5+_1_+.
5~----~F~U~N~SW~IT~C~H~1~5--------------__--~~--------~F=2~i~
c
DO I
-
11zL---:".___FU_N_S_W_IT_C~H-'-''-'O_ _ _ _ _ _ _ ___,
~
,I
10~----~F~U:.;N..:.-S=..W..:..:...;IT:..:C..:.H~I..:.'--------------_,
~2 ""
;r16
-PRINTER SELECT
r.;;...
~..------,,---,,=::..:;...;..----..,~
IK ,
I
16r-___~F~U~N_S~W~IT~C~H~9_ _ _ _ _ _ _ _ __,
o
5H Z -
P1
_ PORT 7
'--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _:...::..c.:.c~_ _<~
:,,>,>,>?>
·~?~>S<·<>C~>f22:
> >:><,
I
:~.::>.>.~.<.<:><,><~>~:
I
..
g;~~7~::::::::::::::::::t~:t~:t::::::::::::::::~:t~:t~:t~:t:::::::,-I'I~_______________________-...;"...P_0~R~T~6__~4B
I
LOCAL
~~~O~'================t~:~~~~=~------~H++_1_+_+---------------------
E' 8105
00 5 ..,
·~I-+~_-_-_-~~~~~~6~~~
- PORT 1
'-----------------------...;"...:...;,,;,..:.-.:.---II~
02
:3
{ ~f---....:....:..:c..:....-c..:....--_-------------,
- FKY 5
'" ". ".~ .,.,,,
K
3',
.1'1
TxOI'-I9~Hf---------"";""_O
DATA
16=___ _ _-_XMIT
TxE ~
,r-:
___
_ _ _--t 5
10':; WR
TxROY ~
+SV
I
I
12 C/O
RxROY ~
AIS
I
I
22,.. OSR
OTR ~ "'N'II'---'-'':'"''~
'+REQUEST TO SEND
17
17 CTS
RTS hl.Lv ~Kv
I
r_ _ _..o..._ _--'-----';.......;;'--_--t 4
"
CS
SYNOET P-6
,'--_ _ _ _ _2=-:-'-_'4'--...._ + + _ + _ - - - - - - H + + _ H + + _ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 : . .. SH2 - E16
A23
8
F
r--------+-l-l-V----------~~=----~-SH2-C16
8251
P2~~----F-K..:.Y-..:.3----------------------------------------------~~--------------------------------------~~---r--~AA~AA~
~....--+~~A~D~D~R~0~-------------------------------------------~r_r--------,~A¢
o~~,~s------------------~---+_----'-K------+_~~+_1r+~--------------------------------------_____________-__P_0_R_T-..:~____~.... SHZ-EI6
L7
SH I -
G
r-_ _ _ _ _ _ _ _ _ _ _ _+.:. . .:U:.;S:.:A..:.R. :.T.:. . .:I:..:.N.:. .;T:..:E=.:R.-.:.R. :oTR
.U=..:. P. :.T_ _ _•:~ SH' - J17
~_44
-==
5
-
-
SHI
SH1
SH'
SH2
2;'
-
t
li: ~~
CLEAR TO SEND
\.:J
..
_
5HZ - 13
E3
SHI - C7
+
J..
-
~
DATA RECEIVED
1
L
-~7~06
SHI -
!
I
VCC
___________________________________________________________+~~_+~~~~B 07
..
2
D[VELOPME",,.
SHI - :n
+
3
4
I' ~i08
::: ~::
SHI - F7
K
,
7
Loal
~
NO.
'3'TTyr'TSI6r"""UCTN023702-991E' ~
3
I
2
1
I
4-73
23702 HPR01 Processor Board
Rev. A
B
C
ECO 7367
7413
D
7424
7447
E
7487
F
G
7693
7816
H
7975
As released.
(1)
Add 1 K resistor (E22-7) from +INT (F37-14) to +5V.
(2)
Add .1 microfarad capacitor at B39 to improve noise immunity.
(3)
Change ROMs 23734 and 23735 to Rev. B; change ROM 23738 to Rev.
A, to eliminate ribbon lift problem.
Connect +12V to J3-8 to drive audible alarm.
Allow use of plastic IC packages instead of ceramic for 2111, 8205, 8212,
and 8224.
Add pullups to DATA 0-7 lines to improve noise immunity. Replace
1200-baud jumper with socket for shorting plug.
Changes some metal/ceramic IC's to plastic. (Types: 8224, 8228, 8205,
{ 8251,8212, 8080A, and 25LS138). No schematic changes.
Hardware change only. No schematic changes.
4-74
11
_
I
POOOUCToo.
17
23704- 99
I
1
14
15
16
,
,
13
,
6
7
8
+ ADDR 4
..
+ ADDR 3
:. SH3-GI6
2
3
+
-:-~"
:
SH3-616
...
5H3-H16
+ ADDR ¢
....
SH3-H16
3. ALL CAPACITANCE SPECIFIED IN MICROFARADS.
±
4. +5V TO PIN 14 OF 14-PIN Ie, GND TO PIN 7;
+SV TO PIN 16 OF lS-PIN Ie, GND TO PIN 8;
+5V TO PIN 24 OF 24-PIN Ie, GND TO PIN 12.
INSTALL JUMPER ~ IF ASCII KEYBOARD IS TO Bt USED.
WITH NO JUMPER, POSITION ENCODED KEYBOARD IS ASSUMED.
STRAP AT M PROVIDES AN OPTIONAL DISCONNECTION BETWEEN
/'>... PROTECTIVE GROUND AND SIGNAL GROUND PEl\' RS-232-C •
i l l LOCATION A22 IS FOR PROGRAM MASKED ROM •
FOR PART NUMBER REFER TO INDIVIDUAL >'ARTS LIST.
INSTALL STRAP U BETWEEN E:§ AND E.§ TO PROVIDE
LOCAL ONLY MODE.
INSTALL PLUG
B2 BETWEEN 6....1 AND ~ TO PROVIDE
1200 BAUD ONLY.
+5V
V';C
j
a·~2\
:;>U
...---------------------7:1"
.-------------------------;13 ~!
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FUN SWITCH 16
c
4
3
- FUN SWITCH 17
.
67 .r----------------------------.l
D
L-f_+-rf21=-t 01B
~~~~t_----_r--~_r-t~~59 014 l~ r~
L---------------------------------------------------------<1H_+~+_t------+_--_++_++_t_I7 g;;PORT~~~
011
00'
L I_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
004~
005r.l~5----~
L--------------------------------------------------------------~.,_t1r·---_t----~~rt~lb 015
~~~5~C-H-E-M-A-T-m---D-IA-G-R-A-M------__fr-
~~--~~F~U~N~S~W~IT~C~H~18~----------------------------------------------------------------<~~----r_-i_t_t_~~~~~ 016~ 006r.:*~----~
f2\ _- FUN SWITCH 19
~2 ~:~ ~~~ 1-'2'-'1______......
\.V
~--+_t--t-t::.u OS 1 8212
I
I
_
I
FUN SWITCH 20
I
_
SHI - 86
5H2 -E3
I
I
_
f-,
~ ,,_c-
23704 - 99
.., '" o.. ~"·".,
17
NO
~rr.J MO
+~~S~Y~ST~EM=_C~L~O~C~K~_____________________________________________________________________________________________~_~~~~
. . ._ _ _
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-
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I
15
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I
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r
13
I
I
12
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11
r
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.
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10
-.!
9
I
16 10/1620
Y.
CLEAR
16
tNT ~3
'-t-+-p13'::-10S2
15)---.......:~~~~~~'---------------------------------------------------------------~
~ ~~~,b!~_~.Y.~~~:~ Incorporated
~PW ASSY, HP R02
:
..
I"'''· L~IC.u
r:.! .v
D..1
23704-9~ C IA
SHUT :TQTAl SMEET]SIZ~I~UCT NO.
:3
THRU
I
3
i
3
11
I
2
I
1
4-77
23704 HPR02 Processor Board
Rev. A
B
C
ECO 7434
7437
7487
D
E
7605
7676
F
7683
G
H
7816
7975
J
A4015
As released.
Connect +12V to J3-8 to drive audible alarm.
Add pullups to DATA 0-7 lines to improve noise immunity. Replace
1200-baud jumper with socket for shorting plug.
New artwork. No schematic changes.
Hardware change only. No schematic changes.
Changed some metal/ceramic IC's to plastic. (Types: 8224, 8228, 8205,
{ 8251,8212, 8080A, and 25LS138). No schematic changes.
1Hardware change only. No schematic changes.
Additional solid state components used:
Ie
C8316A
A22
4·78
~DA0
3
~DAI
12
5
+DA2
+DA3 "
+ PAPER OUT 30
+PRTR READY 42
- END of RIBBON
10
+ COVER OPEN
32
g
~~==========================================================================================================================================~~3~~~2
______________________~~1~0,-----1
0(1-==============================-----------------------------------------------------------------------====-===============================~6 ~I OOI~5----------------------4_-L1
~~==========================~--------------------------------------------------------------------==========================================~IO
~
002
I
2D3
lr~
~~~~~~~~~i-~i~~?i=-_-_-_-_-_-_-_-_-_-_-_-_-_-_---1----------.-------------------------------------_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_=_=_=_=_=_=~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~]3'AIOA~
,: ~:
QB~ ~~~ D03 14
02
2
~5V~
,--________--'-l7 01
+CHECK
-SELECT
1/
cr------------------t_-i----------------------------i-i---------------=======================+====~=+=+====================1=::::j~IOD~ D~
2,:::-6----------------jf-+------------------------------------~------1__~~
~
;~ 9~I""
13
o~
or
}-_______
""'..,
5 037
10
~
C61
9
4
861
5
6
7408
.------;-
~
i
I>
~
(CMD)
~
~
9
-=-
~
fl
V
4 .......
7411
~
jf.~~.2~======t===--::::j=------rl-i--------------------------------+~~---+-+i-+---------------------------~----~-----,
~~~~-r~-P~W~5-i-------r------t-~r-------------------------------~PQ~~
*
""Jt~A6
~r-+-:P::f----+------+-+-+--------------------------------l~21I~
A~t6,61;
8-4,10,61,14;
0-4,10,61, E-4,IO,63.
f-4. \O,6~; H-4.IO,63
R
'-'
2p.2
0o----------------.-+-+-~I. B
0o---------------4-+-+-~" C
~ t:~>_':'_t_---~-I
:.~:~---r_----+-----~~[
E61
"'" 32~
~9
d~
r--;:;-- 6
nO--~----------~5:r;:;
"
"
~1'
'-----!:<
13
-0
1~---rrmffi-r---+--------1K+r~+----------~
0
-0
.....
H""""'J'v-O+5V
HII
C~+_M~
M~~~I~"
24 -CAR
22
BUSY
-PW BUSY
21 ·PF
BUSY
CLOCK A
-0
'~~~B:~.--~I--~~I----+~*~~+---+----------+~H-++~~----------------~
~-t-ti_--t_------i_-----------=====~~----------------~-~.~70~.~~13~~G~13~1~
9~~13~____+__4--+_--_+~_U~tL~
14 -CLOCK A
r--t-t--1-----------1-----------------------------------------------t--+2'~~·-~·~·~·~·-~~-+--t----+~--~~--4_+-~6..---~~
rlli---r-----------t----------------------------------------------+-~~4~'~--~~5~~f_J---~-+--~~__~4_~4~
r-t--1--------1r--i---------,-T------------------------------------t--+~~~,----~:~~---+-------+~~~~--4_+-~2 G61
~t,1
12
6
74L542
7
8
4
~+-----------+L,Sr~-6....J
•
PW
p!9
9pl.l
CAR HOME
-PW HOME
7.,. CAR EVEN
10 10CA
,~37 "32 IIJ'-{H -PW. EVEN
O--+____________-jI..q..i'l37 ."1l!l--N'7,."
7_V4 lOOn IV")I"'O---'--CA~R'--'."'PQ"'s"",A-.-_=========13~;==-::
H36
N37",. I
CAR POS.B
12>J&V-IE37
"
>:
I1~loo;;rrv,~37
1 - 13
12 100.
/0----+-1------"""'--'-"'''-''----------''=+1"
( }--+____
)::
~
H35='=
637
( } - - +_ _ _ _
g
o---+____
47W *f37
-8"+-__--=3'1>7::. •
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470'~
H37
470'~
H33=
L+Pi
5V
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II
0
3
8
6
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C
_
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I
-PW POS B
----'--1 T6:8u(J' 50V *
~-----------H--------__1f__--+----_+------f_----+_-+_l+-~RC£....--+--i--l---~
~~09
13
~
-()
~~~~+_H--!!14 R.'4LS170 r6'-t-t-H-t++-I__----------------~
DRIVER
7~ >~~~~
__3_7____~~-~~1M9'~3~t-~====~~W~RI~TE~DA~"'~A--------------------t-rlr---t---------------------------t--t---++-~-+-------=~====================~======~J
IK
+ 17
+ [AG
3~ ~ ~IO~G~7~8~c:JQ=l~I2~I~ ~- ~ ->~';j;;t:~~~~~~~~~~~l"ff~AD~rn~~~~~=t===l==~~~~~~~====~~~~~~~~tJ=t=t~~i;~~I~-~-~~~~~~~~~~~~J=tJ~~
+'~~GSO
17
19
+ lAS
45
I> (LS BYTE)03 - 4
19~
X (MS BYTE) 133\,.--';""", 10
*
+ 15
"1
-n
02~--~++~_r---------------{)
,..,
7
~~-+~+-H_+~~13
825
H-+_r+_+-~~-":q2 :; RAM 03 t-'--rH-1++t------------------{)
L--.~'5
849
10
9
QI
~~-+~~~_+~+_~'4~
'--c~
01
~~~~~,~~~~~~~
:
3 02
0A
203
f!'12'--_-+_->J'~2 013 ~:,~
aD
C2
rl-+-+-l--+--_.!.J7
3
12
"04
:~
2
D03 14
Il
OBI
13 083
5~ ~
GND lIZ
46
+DATA BIT
~~~88~~~~~~6~--------i--t-------------------------------t-t-----------------------===========4=====~=+=======------==========j::::=J
""
+5V 718
+ IA4
r -____~I
~ ~~ I;LO~c~~:~~6~-RE-S-TO-R-E-F-F-------------------------+~~---+~
31
48
~1__----------------------------~--+----~6~02 MUX
38
-PORT 6 28
• PORT 7 26
37 + IA3
r----~~~ B612~ ii61
~~~--------t---------------------~~~~----+-+--------------------------------------+-----!-._c=r-=-=-=-=-=~~10~ws~2ge
2
-'....:~
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.
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010
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'--'r:-::-, 8.04 B 4
L.,-4 Bi
OC 1f13'--_-+_~9 OJ2
-PORT 5 34
flAt
O(
2
+ I6
-()
41
40 + !A2
~
~~=========================__j--i_---------------------------i-+-------------------==============+=====+=+=+====================t==~3~
~~==========================j::::::::j==========------------------------1-+--------------------------=============t=====4=+=+====================l==J~6 DOI~5~4_~-+~+-~I__~~115~
PRTR 20
-WRITE
r-r~~-=--=-===t::::~(,4:74LSI70
.. 04 r6'------;+-HI__--------------~
~
837
•
813
13
O----------~r1-------------t_-----------------------------------------------------------------____~================~I 82
aD ~ D1'CS3 8216DlEN
,-___________________+-------------~~ ~~
0
,..,
12 WB RAM Q31-'7----------.-+-I__----------------....(;
-C
15
4
+DA 5 6
+ DA 6 16
+ DA 7
DII
.~~
~
I
~DA4
CI3
QC ~ 012 DRIVER
A2
________________________________________________________________________________.D4 BI
..J"'-..6
HI51K
-READ 23
'U
Q2
'--'
G261K
- SYSTEM CLOCK 54
,..,
QIIIO
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7«>1
13
b -~ ~
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n
12
I
j
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2
41 D25
6
H65 2'
j H68 2"
IH7I2<.T
H73=SGL STP
~~~==~~p~DV
14
I
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9
f73
LINE
DRIVER
~13~::::=-==_=__=_~+J
~
I5
II
I
'--------'
8080 INTERFACE
40644-03
REV.E
4-79
40644-03 8080 I NTE R F ACE Board
Rev. D
E
ECO 1120
A3879
Circuit board revised: all IC locations changed; 74174 eliminated; 7404,
7414, and 7432s added to CAR & PW inputs for noise immunity; CAR & PW
CNTR CTR L circuits modified to allow printwheel to turn without loss of
PW position in memory.
Documentation change only. No schematic changes.
4·80
:::
:
~:
IA_.MAIItIltlTA TRANSFEI1IlUS
,1
11\-3
IA -2
III
I
IA- I
12'
1
,---______________
~r--a.
+ i"e 00
+-IA7
+IA6
••
4 TABLE ~
,
3
~
"B-,
2 A43 f.!.'O"--_____-'
Re-4
,
1-'9'---_ _ _---'
,---________---'""'B_-'''--___+.n....,
I"~__________~
. -________"'RB=---"-2____-+-'2"'2
f.!.7____________---'
,---______"'.B=---'-'_____+_""" 825"5 ~
13
'4
"
9
+1.6.4
47
+ IA3
38
... JAe
39
+IAI
9~7..§
...
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'."'E4:
3
Kl
,---___"""":.. .-;::..8____+_--+-+_--_+-------------+-----"""A'-"-"------------------+"'I16 C2!5
RA-T
RA 7
14
~'__
.c.:;::.:_::
.--
_
~ _=1.~-8~~7,---4
o,,"t,t
lA -5
3
A
r-________~I~'2__~b
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!'l
r--
8
10
Re-'
r'2--+-~+-+_~f_+_+_~f_.
f"'3'--+-~+-+_t-I_+_+_~I_+_.
rR.~·~4____~------_+------------+_--+.~.-.~--_+_+----------._~'6
u,
~,
:
f!o2__---1H__+_H_+_++IO". RAM
6__.--f--t_ +_r+--+-+_I-'ti".
fCCI3 f'-9-'-+-H __+_HH_++,4,". AI3
,~
1'453
-
lA-2
..
L-------1----1H--+--r--=----"--!:~:'---''---4~
~
r--
'--I~~~1~~t~;~~t~~t~;1~!:t.=:,'"i'
~
"_~
'--+_t-H--+-+-H_+-"i9
•
!l
~~
+ OPTION CONTROL
013
2
PW STATUS
>:
~
-----~12~--------------------~+~B~IT~5~------~l)
",R;.A-",6+_H H---t".,'
...--Hf-+_+,'
~ - 2 G25
_
I
ti--~
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-(
LIFT
>: 10
~~
14.
~~
r"'--____________________~+~~=R~L~IN~E:AR~M~O~OC~~>:
10
+PW LINEAR MOOE
?:
9
+/-PF8
>:
+/-R'8 , B
;..
6
+/-C.... CUSP
;..
04
+OPTIO~
5
+CHEC.-
,----f.!.'2~
_____________________
CONTROL 3
>=
+:~8~1T~.~
+CJjR
>
______
4()(NOT USl01
~
27
23
30
32
36
31
~
VEl STROM
49
~_2F25
P.~3
E73 ti
4
p:-
~
-'
0En rQr
9
8
,
I
"3~ '}r-~~"
CAHRr'"
"
+ SERVO
~'~
~I-_~,
C~ - -
E61 6
~
OISA8L£
...
~~~~'----------------------~+~~"T~E.~MA~~-----(
~-~
FilA.-
f_
r4~+_+_----------------+_t-H--1_~~H_4
4
C
:2:
-+IIT;)
L.------------++++-+-I___------+-----------------:::::::-:-";~-___1H_t--+-------------------_:t: 'o",,~ ~ :::~ ~
L-___________________1-+_+_H_+--------+_---------------~R"'A~-'--'-----+++--t------------------~~"
&49 10
+.IT~
,---2P.CLK
~
'0
6
'5
::= 12
+PW REV CCW
f-'l__________________
14
~p
r"'+-+_+-----------------+_t-H-+-+-HH--"'1'
1'4298
GI3
28
19
+CARR['v'_
r4H----_+_+++-----------------H>---t_++1-------H------------------~~~R~~~--++_~
:!: t":~+-+-+----------------+-+-H--++-Hrl---'-'i'~
r--rc
13
_..l.
23
/
~--+_f_~--+_HH_+~.
OPER
~
'52
L
025
0'1- _ _
>
r--:
~I_~--+_~H_+~'~'
L-+_+-HI-----'I"'A-=-4--'i1~
"-
__
~_1--HH_+--------_+-~~~~----+----------____1----~RB~-~--H_+------------~3 ~. ~"'----~r-+_HH-+,!'2~.----b'~'H-++~
II
I~
I<"RA=--,-7+_Hr-+-+':~
I,
1
RA-.?
RA-2
110
;9
2 fi8 f",IS'-,-+---I~-+-++-+-++-+--+-r+..
~R.~--------+_----------_t--_;~.~A-'--'-----+_t_----~r+_+~
.------=---'1
r
1_
74lS283
II
to
_
~-+-+-t-+-++-+-+-++-;-+-++1--'i2
,-OMPARAroRS
13
11()I,1(
~~):)6HH-t-:-;i 12
L-_+_~H---~I~A~3~9
r--1"'2'-----------------------+~8~IT~6------~~
9
7
I
RS 2
>: 22
>< 26
>< 24 INOT US£1lI
FWO(CW)
~,
S_ 2
- ""'OON HOLD
+....
9
7
6
~
:
.---ll
f-'.'------------------------:'-':...."-'-"TION""E'-'RCOH;;:;F-'-',~"'RO<.=-c,--~><
~~ !5
II
825
14
~H_1-HH_+---------+_1~--5~C~429+---------_1----~RB~-.~--_1_+------------_YI,-L--I.
__
lA 4
3
~ G37
1
L----_+----------_++1-+-+_--_1_+--+++_H----------------'
" ill'"----H~+-+_H-+_H_1-HH_+--------_+----_:::___:_+--------____1---t_------,
L-____~IA~-9L-~9
1-7
'gSa
~~ ~ ~2'4S2,,?"---+'----",L------+-+_H_+---____1
·~_+..-->--HH_++'____________---'
~_+~~_+_+_+_+_+_r~
10
"'I'
___+_--_++----+_----------_+-----'-:;::.:-:::'----------------26'__~_+_+_HH_+-Kl~ .....
R8 6
~
0:9
~'
LATOf£O DATA OOTPl./T()IIIIVEIlS
--"t--'i,
m
Fft:G
14
~
•
9
7
0
4
r--------"9
'3 A25
~~~;~~~:~~~~~~~~~~~~~~~~~~~~:--"2_C>L'---1~=~:r-~~'9~~:~~~~~~~~~~~~~~~~~~""""RB-'":. . '-':.:. :"_- -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-___- _-
6"""-----
~====~=~:~~~=~=~~~~~~--~~
}----1>---t_+_+_+_+_++--=~:...>::1";i
42
,-------------~
RS-1
RB-6
4
3 ~'4298
=
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10
6 .....
()~(}_ _+++-+-++-H~~~8 -1"'2~_..........__________________.:.:RB:: . -. : 8___+-'---_+_+_+_+_+-+++'1" IO~C37'
8
}--_-+_+_+_+_-...._+_+_-+-~"'7-'1' 2 2
C]7' 037
,
"61
~
WORD SELECT
J,.14 ~
r--f-
L.------~--~------------------~~~--+-~H_+--------+-------+------------t_--------------_t+-----------1~_+_t~--~1___--___1--+--t---------------------___1r1_t--+------------------r_--------~:~:6~--------~<)20
L-----------r-t-----------------i-rlrt--rt-rl-t------~C:====~===========t============~lrt_--------,_Ii~_r--_1_t----t-_t--t_-------------------j-t_t--t_--------------_1----------+~1~7---------{~'6
+I8
_=_______
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1'1
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L___ ..J
RA-~
3 r - - - .--____-+____________
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I
...
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'-'
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7~
-051
1"'6'++-t':"'~-4I,....-t-<+--1.:..'+-+-1-...,9 :;:oe___+_I-f_+--+--,
-[NABLE INP
PRr)(i"-AIltl
",Fe 10E
I!rST'RUcrlOlII
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r-,
I
IH61
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9
o Gn
~8_____-6-_ _ _~"""
.9
-CLOCt< A
LOGIC-2
40510-XX
eLK B
o
eLK 8
I
-
REV. AE
Tf $T CONttofCTOA C61
4-81
REVISION HISTORY - #40510-XX LOGIC-2 BOARD
Rev. M
ECO #9988
Revise documentation and assembly to move ROM's for heat consideration;
change to axial lead bypass capacitors; revise RESET logic; and improve fan
out.
N
A1274
Revise PROM program to correct problem of failing to recognize PBV
command.
p
A1247
(1)
Change circuit to enable Table ROM (A43-19) only when it is to be
read (was previously enabled also when RAM was accessed); lengthen
Ie life.
Q
R
(2)
Add delay (via H73-12) to eliminate possible race condition on Bit 0 Bit 3 output latches.
(3)
Add delay (via C49-9) to increase RAM address hold time from;:::; 5 ns
to ~ 20 ns.
X
A1444
A1523
A1501
A1578
A1622
A1841
A1879
A1945
Y
A1977
ROM change to lower maximum carriage/paper feed velocity sl ightly, to
prevent possible missing of incr/decr pulse.
Z
A3093
Allow use of ceramic ROMs to improve reliability; ROM changes for other
HyType II models. No schematic changes.
AA
A3250
ROM changes for other HyType II models. No schematic changes.
AB
A3289
Hardware change only.
AC
AD
A3508
A3917
AE
A3929
S
T
U
V
W
ROM changes for other HyType II models; not applicable to HyTerm. No
schematic changes.
{
No schematic changes.
ROM changes for other HyType II models. No schematic changes.
PROM changes for other HyType II models. No schematic changes.
4-82
8
+155
FIG
2M
+ CAR
REV 18
+ CAR
FWD 37
-SER\IO DISABLE
CAI!RIAGf: VELOCITY COMMAND
CARRIAGE POSITION TACHOMETER
16 +/-CAR SERVO ERROR
10
STIO()8E
+CAR VEL
+
17
SERVO 20
DISABLE
+CAR
067
10K
L1: 50
DeB
10
D58
10K
D57
rot<
F72
10K
""X>-.---------------------1J
A3
249M
:=======~===E============~~~=~~~~t~=~~=~~=~~=~~===
CA~'::2 49
~1G~,48
~~~
47
+5V
EVEN
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - o 52-CARPOSB
53-C4R PaS II
")~-1:~~~-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=~~-------------------------------------------------~~====:026~R~E
L--
f9
lOOn.
___-========~
F
44 +CAR
CARRIAGE
HOME POSITlCW
REF CURRENT
.".
22 -SENSOR RETURN
SENSOR RET
34 - PW HOME
SIGNAL AMPLIFIER
flO
201<
GENERATOR
1'5V
"
14
BIT012
X
t
+ BITI
15
+ BIT2
+ BIT3
14
I
-t BIT4 19
+ BIT~
7
+ BIT6
9
+ BIT1 II
SUMMATIO!'
AMPLIFIER
29
+ PS~~~
30
L:~
46
SERVO ERROR
r ,------------:-1
032
101<
+ PW
+/- PW
'35
101<
D3I
10K
r , __________--,;-1
P~~~:.~40()--------------------~~~~M:7~---------------------------------------------------
+5V
f32
2K
45 +PW EVEN
2K
".'P~,:::, ~~=================================================================-------------------======i=====================1===t====================================
~:(;?--------------------=~=====================-=-------------------------------------------_l----------------~~~--~=======================-_________________________________________==================================0 .~W~.
045
IDK
P
~,:~
2M
F24
35
.-.-__-"1,....._
022
2K
l--~=====================--------------------_============================:o
"-PW
pas
A
25-P W HOME
PRINT WHEEL
HCME POSITION
SIGNAL AMPLIFIER
SERVO
40520-04
REV. N
4-83
REVISION HISTORY #40520-04 SERVO PCB ASSEMBLY
Rev. M
EC0#9923
N
A1504
New artwork, minor component changes; prevents possible motor burnout
following component failure.
Remove assembly number from etch; this circuit also used for other assemblies. No schematic changes.
Additional Solid State Components used:
IC's
7404
7406
7426
7415
747C
8041
319
oP, AMP
G60,E60
G24, G36
G48, G72
E12
C12,C24,C36,C48
A 12, A32, A60, C72
E24, E36, E48, E72
C60
Low Offset
Transistor 2N4401
PN3644
E6
A18, A28
Zener Diode 6.2V
1N5234B
821,822,837
Diode
1N4454
A21, A35, A41, A67, A71, 86,89,826,833,841, Dl0, D12, D16,
025,072, F14, F27, F45, F48,F51,F56,H20,H39,H68,H72.
4-84
INVERTER
"'"
1501'
A425.1IK
CARRIER
FILTER
E43
27pF
1"15VF
13
DRiVER
CARRIA9E RF AMPLIFIER
J8A
A6
4.7
r~
A43
Cl5
07
CAR~ G)~------------------------------------------------------------------------------~9\~O~~~A8~1.~J[~---~--~14~~~ ~~
~
..r
'"
B::
JaA
'¥ ri ';1'l
CAR" G)~----------------------------------------------------------------------------~I L L,.AA~
iii '-~Jf-+ 1- CAR
CUSP
CAR POS I
48
'OIO
II
I~
73~
-&IF
910~
CAR POS 2
1
I.
r~ ~
:it"
~~~
'* ~~1J4
II
II - -
~K
CIO
910~
E.IK
£5
14~ ~
!V
'O ~.r
IV
133
~
-6VF
F5
IK
~5V
II
~~~
3.31<
F9
12
~~3 I~
'¥
7
+
G31
3
L-EIIIO~~EI3~
910~
DEMODULATOR
13, _ _
H36
II
470
~J
Q
~"
~
PI/!
i..
PI
~
P2
...!-
P3
J31~
12
:3.31<
Q2
13
F
F
14
H36
H36
__
J,,!~
3.31(
22~------------------------------------------------------+-~
"42
'i"15VF
~6
.I"F
SINE WAVE
DRIVE
GENERATOR
045
t--'W'r--- +SVF
.+ T B27
F
F
"~2
J25
2.rSK
+~:,
t-__-~f'-oa----__--------------t----------------------------------------------------------------~GjG):8~A~6
J21
1.37K
i~1I
~~
03
11
03
12
r~~F1A
~~5~:
rt2
H48
5
6
HI.
....1... P3
L-4---...:'::;:0-DCLk
C
yl
1"
0" I~
HI2
+~~.30
9 HI.
12
__________
I ;o2__H_6__~.......-------.:...JI4-"'''',3'''7K~
~
w
gG
3
T F29
I~
+5v~*
D
[irF
~i
6f~
g~;
~27
+15VF
~:'"
'....F-. .-,,);.~f_"'lg'l~Ir------+------_--.:;,;E3>A2t1.:..:.:~-~.1 );:4
TI5VF
0>4
I.
A30
A3J
~.IIK
CARZ,~4
PW2.PW4
JaB
7SpF
+~
A32
I
13
5.11"
2 /41~I5VF
'36
A2S
330
d: AV 49
J
PW P[)S SlG"'2
.01
t--l'Igall\~,....------,-~V-E-RT-E-R-------------{50 == ~d~G t;;~/
10:!iJfJ..
",OPF~
~
I
F36
~5~~
QI~'4----r_------+-_+~~~~~------~~4_--~ /o~___+--~1_-4----~£~2~.I5~K
~
13 H6
Jl2
v,;..::HIIX~oH--+----------:-f3 )04-+__+-~
+-,13(;;7K~
I1
IK
2
74195
--- P2
~
-J1"5V::
)+~V
H42
Q2~'3----~--~~+--+----~------~
9
6
*
CAR 3
J8B
HI8
9
<1-___-"E4;;j0.,;2::;".7..;::.----i> i'!ivf i t
1
J8A
JI811<
1
l.~iK
2rJ---:~9~~~--_t--t_~~r_4_----+_----------_+--~~~ )/;____~-----------~~J4-2-2J-~~~~
O.IA
CARl
~J.lF
1.311<
JIO lJ5K
12
G4'
POS SIG #3
.,.-;.
13
@>Z3~_____G.J~~ I
@
CAR
100.4.
----.~~,2o-+-~--~~1I ;Hlxe~--------------4-~w,~--_t--_r-------------------------1----------------------------------------__________________________~J83B
6.8j1F-t
G472.7;
IOOPF~
J2B
2.15K
H6
6
~
1
~3
3.31<
CAR POS SIG 1f' I
~-----+~~+-----~5 )6----------~r_~--~~r__+------------------------~--------------------------------------------------------------~7
~4
CIRCUIT
G~ G»3~_____.--~~
ISVTAJ.
P
JI9
GROUNO'¥
(;)
IK
I 5~?H6~------------*-~n~15~V~,~--~~~--------------------------~----------------------------------------------------------------~7
50\1
8 PHANTOM
-15VS
D52
9
L--...:;,v...;..;..:...._..2.I.
H42
II
POWER SUPPL'I'
~
+15VF
J;:/
042 lOOK
1
10
),C3:1145
RF AMPLIFIER
o
7
r-1_-4--+-_+-----------------H4~2~, ~2---~--__~~----~.3U'3~7~K~----------------------------i-----------------------------------______________________________~J~
G9
JII~
r \3~ J6
F50
U"F
~~:
J46 J40'FJ482J5K
10
4
~VD
392K
6~.9
E371
C
B39~
043
2J~
H24
01
.....-----------------------(.5
E4J
E42 &n<
.--+-__---'-"10'-'> CL K
IOn.
IK
J301K
74185
11"2
F4:~lVF
lOOK
~.~K~3.3i<~
H36
CAR POS SIG
:t0l
- 15VF
9
10
;r'2'-'V>.........~........---{53
~1~
:!.A39
t--",a8~~
A50
13 H").02---B----------l-+----3~------~~G~4Ao~----~-------.~~7i~'P-F~~:-~9:-:-VF-*------~----------____~
TI~"
03 rlC!.I---t--------+--+-------------------------d
A48
741
-15VF
rr;nF4;Y-
IK
~9
pE
2
zoon.
G42
lOOK
,----------------------------------------------------------.\..l-'+'.--~-..,
H44
7f
5.11K
1345
+
F~~t
r:nF4~
I
+5V
:'.[2
B42100K
036
/02_ _ _-4-__________..:.J2:.;6:...,1"'.O"'7K;.+.__--JT·0022.,F
HIB
JaB
9~
AlB
C1
pw5G)~--------------------------------------------------------------------------~i~~
~820r
r
';~ 823
~ . ~"L IK
G)~----------------------------------------------------------------------~~~
J8B
9IOpF
It(
14~
1"6\IF
e30
IK
+~1'V
G3~
10
B21
II 733 5
IV
12
:i3K
~a
~'5VF
833
..
t-""~"~-------------------------<45
PW PaS SIG"'3
IZ
DEMODULATOR
-6VF
OfUVER
PRINT WHEEL R F AMPLIFIER
PRINT wHEEL FiL.TER
XDCR
40515-03
REV. A
4·85
REVISION HISTORY - #40515-01 TRANSDUCER PCB ASSEMBLY
81M and Assembly as Released.
Rev. A
EC0#9742
8
9830
Revise documentation and Assembly to change resistor type at G 1 from film
to composition. Cut "Key" pins on connectors J8A and B.
C
A1483
Change transistor at F25 from 2N5322L to 2N5322. Correct several schematic errors.
ECO#A1695
Add .01 pf capacitors from CAR pas SIG #2 (pin 53) and PW pas SIG #2
(pin 49) to GNO. Change series resistors A40 and A29 (same circuits) to
330 ohms. To increase noise immunity of op amps; eliminate printwheel
retry. Change "01 to -02; change revision level to Rev. A.
Eca#A1720
Change circuit board and artwork to accommodate changes incorporated in
-02 (ECO#A 16951. Change location of capacitor A28 to A27.
#40515-02
Rev. A
#40515-03
Rev. A
Additional Solid State Components Used:
IC's
7404
7406
7420
Transistor 2N3644
2N4401
2N4736A
2N5320
2N53
H12
H6,H18, H36,H42
H30
836, 848, 036, 048
833,845,034,045
G16, G17
F14
F25
4-86
CARRIAGE POWER AMPLIFIER
873
909n.
874
10011
850
~~~~ ~~-----------------------------------------------------------------------------------------------1r~5~.6~K~~-r--------"l
851
10K
+150
E63
CARRIAGE
DRIVE MOTOR
A59
A60
...
I
!
------- -'
10K
10K
--------------
~----~--~~~~~--------------------~~
~
=
0.1n.
-SERVO
DISABLE
E74
2K
E73
F74
2K
1"511
F73
85
511
All
II(
A7
-15S
844
IK
+5V
89
E62
88
100A
L-______________________________________________________________________________________________________________________
~~~.W~.~SE~R~VO~EN~A~6~LE~
______~18
87
-155
!-____________________________________________________________________________________________________________________________
~+~~~W~E~R~O~N
____________~16
+150
+~F
A
44~------------------------------------------------------------------------t_--+-~----~~~
S37
O.",2W
CI3
CI9
PAPER FEED
-15D€):§)--~-15D
DRIVE
A
-150
PAPER FEED
DRIVE MOTOR
PHASE A
3pF
_
1+;011_
+15000--~+150
O.1A2W
r ....
+ 5VGXV~------------_._-----t>+5V
-15S
......----...,
4)-----------+:;;.;.~----------------------
626
PAPER FEED
14
DISABLE
DRIVER RETURN
CAR
G24
14
PWR AMP
+150
+PF9
EI3
IO~----------------------------------------------------------------------------------~1r----~V-~
PAPER FEED
DRIVE
B
E20
150
., «)(=::0525- 07~?v~
\
-ISS
L-______________________________________~--------------------------------------------------------------------------------------~~
31
PHASEB
32~
4-87
REVISION HISTORY - # 40525-05 CARRIAGE POWER AMPLIFIER PCB ASSEMBLY
Rev. N
ECO#A1260
Revise schematic, documentation and assembly. Change
833 from 75K
to
15K
F32/G16 from 82K
to
62K
G 18/G 19 from 523K
to
392K
C56 from
2K
to
1K
Label G52 and G68 5.1V. Remove -5.1V line from junction G52 and G54.
Change from -XX to -05.
P
A 1260A
Correct error on B/M. No schematic or part changes.
Q
A 1565
Correct error on B/M. No schematic or part changes.
#40525-06
Rev. A
ECO#A3128
Change circuit board and artwork to accommodate changes for the other
HyType lis. Only schematic changes are in the following locators:
WAS
IS
C54
C55
C56
C67
054
056
B46
B47
B44
A44
A45
A47
#40525-07/08
A
A3278
Revise -05 PCB's to -07 configuration and revise -06 PCB's to ·08 configuration. Remove zener diode D74, replace D73 with a jumper. Change
zener diodes A7 and B7 to 11 volt devices, resistor D75 to 5.1 K and resistor
B33 to 30K.
C
A3966
Documentation change and material change of a hardware part to reduce
cost. No schematic changes.
Additional Solid State Components Used:
Diode
1 N4002
1N4454
C13, C19, E13, E20
A8,A12,A19,A20,A25,A32,A33,A37,A38,A59,A60, B8,B9,B19,
B20, B25,826, B36, B37,C54,C67, E75,E76,F72,F73, F74,G72
1 N5415
1 N5807
E53, E67
E48, E63
Zener Diode
5V
12V
1N4733
1 N5242B
B5
A7, B7
4-88
PRINT WHEEL PCM'ER AMPLIFIER
-I~D
2!5 ftwu 32
't15D 41 11r\I 47
"".
@--@~-. . O"'~i\~;.::..:.F""=--l_EI.---OO
.
-15)
E}
+1!5D
+
OJ~.c.uf'"
+5V
(ik)---------!t-J7-,-Ot>f"5V
9+
.h D33
6.BloIF
G~~
FWD/-REV
150
4}-_ _ _ _ _~~'~·V~T~.---------~~
PRINT WHEEL
DRivE MO'T(R
-
...2"
FWD/TREV
-~::T
C17
2.
RIBBON HOLD
DRIVE
+1-RlsmA
9)-------------------------------------------------------------------------------------------------------------l-~~~::::2
"'2"~ ","'
~-
t-------------------------------------------------------------------------4
+/- Rle
IJ B
12r-----------------------------------------------------------<~~~±~:...rJ
"
24
END
at
RtBBON DRI . . . E
..
859
OJ"
A11
OZZ
%0
21(
~
:~
lSI
101C
".-~~....
+P~EROh ~r-------------------------------------i_--+__1~i_----------------------------------------------~~--JCjj
C38
C37
~~~I 62V
'~.:.~"..
t~:~~,-------------~~~------------------------------------------------------------------------------- --------------C)'~
"'"
I3
+ RIBBON
SENSOR DRIvE
.C~'06
- HAMMER
~IRE
.,..IMPftESSlOft
CONlROL~
+~~~
CONTROl
.51
+c~~;~~----------------------------------------------+---------------~~~~
'56
2'4
OOn
..
,
41ZI(
10K
"
'( "~~. ,.,
~~r---1r-~C.~7~,.~----------~----------------------------------------- --------~~~ -
t--~.=~~--------------~--~~----~---------~
4T~~
C60
PW PWR AMP
40530-08
REV.C
4-89
REVISION HISTORY - #40530-06 PRINTWHEEL POWER AMPLIFIER PCB ASSEMBLY
Rev. M
ECO#A1030
N
A1050
Revise documentation and assembly to change Zener Diode C37 from a 6.8
volt "h.W to a 6.2 volt 1W device.
p
Al123
Revise documentation and assembly. Change C34 from 5.1 K to 2K. A"ow
power up sequencing when using power supplies with a low current fold back.
Q
A1230
Revise documentation and assembly. Delete C68, 068, 072, 075, E75 and
F66. Change F67 and F75 from 10K to 27.4K. Correct ribbon drive
problems. Change drawing No. from 40530-XX to 40530-06.
ECO#A1413
Remove .01 fJ. f capacitors from 846, 849 (printwheel drive motor feedback
circuit). To help eliminate printwheel retries.
Revise documentation and assembly to allow use of # 40531-06 PCB for
# 40530-02 Assembly.
#40530-07
Rev. R
#40530-08
Rev. A
ECO #A3278
Change -07 to -08 configuration. Remove C33, D33, replace 033 with a
jumper, and change resistor 034 to 5.01 K. Prevents printwheel spin on
power-down.
8
A3754
Hardware changes only. No schematic changes.
C
A3966
Documentation change and material change of a hardware part to reduce
cost. No schematic changes.
Additional Solid State Components Used:
IC's
319
747C
748
A64
A45, E74
A19,A31
Resistor Network
10K
A53
Transistor 2N3644
2N4401
2N5320
2N5322
2N6103
TIP 125
C44,D5,021,D43,050,058,064,E35,G67,H18,H35,H50,H67
C4,C19,C65, E58, F16,F45, F48, F64,G47,H61
E14, E30, H59
E6, E22
Cl0, C26, Gl0, G26
C73
Diode
D45,D61,E45,E55,E61,G61,G62
B17, B42,B50,B52,B56,C15,C39,C40,C50,C51, F40,F41,G36,
G37,G38,G39,G65,G66,H47,H53
C33, F69,F70,F72, F73,H16,H31
El0, El1,E26,E27
1N4002
1N4454
1N5231
1N5415
Zener Diode
6.2V
lM6.2Z52 e37
4-90
16
15
12
13
11
10
7
8
9
5
6
4
NOTES:
+12V
+ 12V
E32
620/200
RCV
~ill~
A
---------------0:--
r-----------------------.
&
-- 'g
8Z'~"
+ DATA
+5V
1W
r---J~---,
Q2:i
+5V
J1
SET READY
+12V
Q§Q
1K
I
825
31
~
Tl L117
I _________
OR EQUIV _
L
7515j!P
+ CLEAR
TO
SEND
+ CARRIER
I
16
I
ALL CAPACITANCE SPECIFIED IN MICROFARADS.
+5V TO PIN 14 OF 14·PIN IC, GND TO PIN 7.
~~~~:;62N~~~:f~L~R~~tt;~E~ ~ABg~~~~ltM\~DUW :~6N~~A~~ Ie
1 WATT RmSTOR; FOR A 60mA CURRENT LOOP USE A 200 OHM.
1 WATT RESISTOR.
12
- DATA RECEIVED
FOR A PASSIVE TRANSMITTER CURRENT LOOP, INSTALL JUMPER p,1fi
BETWEEN ~ AND ~. FOR AN ACTIVE TRANSMITTER IN FULLDUPL£.X CURRENT LOOP OPERATlON,INSTALL JUMPER i l l BETWEEN
All. AND A24 AND INSTALL RESISTOR ~. TO PROVIDE A 20",A
CURRENT LOOP USE A 620 OHM 1 WATT RESISTOR; FOR A 60 ",A
CURRENT LOOP USE A 200 OHM 1 WATT RESISTOR.
FOR HALF· DUPLEX CURRENT LOOP OPERATION,INSTALL JUMPER
A50 BETWEEN A49 AND AS1.
14
B
r---------------------------------------------------------------------- BI!5
RE.5IS TORS E .U ANi) E -18 (t20 tllt'Jj
m
JUMPER A23 BETWEEN At?~ A~ ~
JtJMPER tUG BETWEEN aa AND §l1
JUMPEI? 1Jf2 BETWEEN
AND -!ll.
RESISTOR E 3~ (6t?O O/IMS)
m
JUMPER
JUMPER
d.l!
BE TWUN AN AND ~
BETWEEN ~ ANO ~
RESI.5TORS fE. AND ~ (i'00 OHMS)
8~6
m
JUMPER
BETWEEN ~ AND Ai'4
JUMPER Bi'6 BETWEEN Q£l.. ANO Hi'S
JuMPER A.50 BETWEEN 1147 ANI) @
RE5ISTOR £:g (200 OHMS)
t):-+--n"--t.t:t
III II II.~"J In 1III , I
b
:1
01.'''''.,0 .. _ A.I ,''''
uI'tLI ...
INC.~I:.
OT"I["'w'.I.~.C.I"IlCl
TOLI .. • ... C . . . . . . .
I
'A4014 ,
:
I
1I"'20~"
81 .l'~'-la .82 :t'1-7 1"1
<:7
~ 7,,:~, ~
..... 0 .. 0
4·92
"-'''''''''''.
i ~ ..•• ,..
B :1l-l~157 j " .......,
23 .940
7
8
6
4
5
2
3
NOTES· UNLESS OTHERWISE SPECIFIED,
1. ALL RESISTANCES SPECIFIED IN OHMS.
2. ALL RESISTORS ARE ± 5 'ro,
WATT.
3. ALL CAPACITANCE SPECIFTED IN MICROFARADS.
4. +5V TO PIN 14 OF 14-PIN I C, GND TO PIN 7;
+5V TO PIN 16 OF 16-PIN IC, GND TO PIN 8.
5. FOR INDIVIDUAL KEY DEFINITIONS REFER TO APPLICABLE
KEYBOARD SPECIFICATION DRAWING.
I
.,.
l_i
Y4
D
U4
74 LS!I52
:3
,
REF DIABLO PiN
23962-XX
23963-XX
I REV I
CORTRON PIN
PROM PIN
55-500190
55-500221
80-551581
A
80-551660 IORIG
I
I
D
'2
U4'3
4LS!l5Z
"
~~
I
,...-_ _ _ _ _
~...:9:..;14LSIl2
1'2.2 yS
±'2 %
+eLK I
r--l
r t r t rlTPO) ~
L....J
L..J
L....J
;,~
;:h
R'S
~
4
P
O-FF
2.~Ccr,~
L-J
;4
14LS1~~
I------.L..j
+ KYSTB
- '2V
c
of-
~O
.---
+SV
'-,C,.-
,
1
c
5
,...---------+H-------':.=.t
A DCOR/ ~p.:2-----'
R16
3
.-_______-+++-_____---"-"14 B DRVR
2.2K
,3
+5V
~ B
~
+5V
U'O
vee
6
TIMER
,...---~THRES
2
OUT
1
DSCG~
5
~CV
"sv
-4:- Cj4.
2.2K
I-"-
555
GND
RST
6
U,S
6
~
74145
9
~ ~
()!l
6'2 0
'----
.---
R'3
.,r-------~-r+--+-----'~4B
2.2K
,
;~~~----------~
DRVR
~
10%
4
6
5
7
6~~--------------------------~
U23
~D
'OK
+1~ ~ 1~
...-tr+-----t"-:-4CJ>AC~~~
QA~
L.J:;C 8 U22 QB~
5
Be
~~I'--~--*--~---~r==:1~~R~'4---~
-= 'O~IO PF
5
5
.,-+-------+-r+_r-_r----~'5~ADCDR/~~2~----------~
IO·01+U4~
RI1
1 ..
4
e
5 74LS~~
R'2
3
U3
.....---::.0 TRIGGER
~D-:'4'--------'
;J.o!.!
74145
9
o
~
u,a
9 74LS0~
B
r2R~74930e8
3
R~~GND OD~
f6R~74920C~
7
R0~ GND OD~
~o
B
I
~~e~i~ QA~~4
1
2
U4
U6
, 1>8 U2' OBt!!
~
67402
74LS~4
,...-;~~~~~~~~~~~~~~~~~~~~~~~~~~~~+_t~~~_t~~~__t---------'
.---------------H----'
3~
4
+ KYSTB
~~74CL~S~~-4----~~12
'--
FK Y 1
_ _ _ _ -_'__'_'_'__'___1
7
r--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _+_~-_+-----~(~KE~Y~85~!----------------"~UI4~~o_lO~__-~F~K~Y~2~
8
(KEY 89)
'2
,...-------"=--=.;=----~U'4X)..:_-
74lSI"4
~~6~----------------------------~------------~------~
r------+++-l-+-+I~
4417
7"4~L~S~"i/J'0J)
r------oAJB
c...!.!!
SRIN
vss
A 1
,"PRoe
A2
A-'
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5
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"''''f'jU;?
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74L5114
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18
~
84 19
74LSi/J4
-
65
- 66
SCHEMATIC DIAGRAM
11
16
~~3 ~
-
~SfII4
VGS
B1
14lS/l4
9 un -",,8
. -_ _ _ _ _ _""-1
(CHIP-C)
5RO~1~9~--------------------------------------+_-----------------------------------------------------J
-
-B2
____~' un 741S~4
2
23
",12
6
80 W13
\J
~
---
13 U9
B
0
-
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6
74lS¢4
~
12
FKY 5
.
~
13~'2
5
10
U'4/~0,,6_ _-_Fc...;.;.I(..;.Y_4_'........{ 5
3~74LS4:4 - ..-~----
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11I~~:2;.:---i::::::::::::::::::t~::========~::::==::::::::~::::::::::=4::::::::======t=======~~-_________~.---------~
~
74L5j'!4
17
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1 . 78
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".DlabIO Systems Incorpond8d A
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Hayward Cailioln.a 945-45
I'
DRAWINGS FURNISHED BY CORTRON INC.
FOR MAINTENANCE PURPOSES ONLY.
SHE E 1
8
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74LS!!4
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4--------
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74LSI/I4
5
(SHIFTI
~~I-'~-+---------1--+----+-+-------'
U12
74 LSiIl4
a
:~~~~~----------------------------------_+--------__+----------------_+--_ _ _ _ _+-____+-___________+-___________~-----------------------___'_3~12
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8
7
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4
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3
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0
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84 83 82
c
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0
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0
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0
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0
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0
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03
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0
04
0
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05
0
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1
0
06
0
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1
1
D7
1
0
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1
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\.....-----.vr-------
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1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
SENSE
ADDRESS
1
1
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81 82 83 S4 85 S6 S7
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SCHEMATIC DIAGRAM
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Diablo Systems Incorporated
1"I,].,.'~..l.,j Cd"'arn.a 90;~)
•
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7
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6
-+-i-i6
W2Pl
6
9
CRI
7
4~J~ 7~8
.--_ _ _ _
GND
L
5~
6813212114105931
K
7
8
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W1P1 +SV
15
•
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9
10
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3
5
65
I..----.....-+---f-I-+-+-H++-----------....:::.OS 74148
L--_ _ _ _ _. . .-+-++++-I1-++_:--_ _ _ _ _ _ _ _~4"17
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11
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~_+---------_;12
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I 1
10
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L __ o--'-P~~~----------~-----------------------------------------------------------------------------------------------------~
1
H-+--~~~~~~~~14
I
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- SPACING
~
SPACING
AUTO LF
G
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2
12
3
I
I
610
I
I
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15
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DUPLEX
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I
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SWITCH 20
- FUN
SWITCH 17
G
~-+---------~15
7 H-+-----'------{7
-
3
FUN SWITCH 18
F
- FUN SWITCH 11
10 H-+---------~10
HALF
:3
2
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~_+------------------~6
I
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I
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____________-~S~C~R~O~L~L~_____________________________________________________________________________________________--i2~r+-------F-U-N---SW-IT-C-H--19~Z
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RESET
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- CLEAR ERROR
"--
.....
3'1
W1
,....,
,...1
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SWITCH
5
I
I
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I
I
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IK I
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1
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~I
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- FUN
3
SWITCH 4
3
SCHEMATIC
I
I
•
"0'''"., 23708
510
SET TOF
~
~I
DIAGRAM
Diablo Systems Incorporated
I
3
I
I
- SET TOF
- FUN SWITCH 6
4
--
c
CONTROL PANEL A5SY. HY TERM
4
-------- ------------
'-
SCHE .. ATIC
INCLvOlS
SHEETS
..
1
THRu
•
1
4-97
23708 HPCPN Control Panel
Rev. A
ECO 7371
B
7424
As Released.
(1)
(2)
U5 (75451) added to drive audible alarm. Return side of alarm
connected to +12V. CR3 added for noise suppression.
Schematic corrected: U1-6 was shown as U1·7.
C
7449
Hardware changes to improve ease of assembly and adjustment. No circuit
changes.
o
7507
Change height of LEOs to .650 in overall.
4-98
POWER DISTRIBUTION
CONNECTOR
VOLTAGE
J1
A,B,C
SIGNAL
GROUND
+5V
L,J
+15VS
F,K,O
XAS
XA6
XA7.
1-4
1-4
55,56
1-4
55,56
5,6
5,6
5,6
35,38
41,42
41,42
41,42
19,22
23.24
23,24
23,24
J4
XA1
XA2
XA3
11
1.2
55,56
1,2
55,56
1-4
55,56
XA4
7,8
5,6
5,6
5,6
41,42
XA8
TERM
T2, T3
T8
5,6
21
HPR01/
8080
INTFC
XAI
HPR02
XA5
-P W POS A
39
18
52
51
50
29
+PW EllEN
-CAR POS A
-CAR POS B
+ CAR EVEN
- P W POS B
14~-~C~LO~C~K~A~__________________- ,
9 r--__+....;D"-'A....:0:........_____-i 3
+DAI
+DA2
40
37
+ IA2
+IA3
39 LOGIC-2 41
38
XA2
52
+DA3
13
8
+ DA4
10 .. + DA5
14 r-__+:...:.D~A.:.::6'---_____..,
II
4
48
46
45
+ IA4
+ IA5
+ IA6
47 (SLOT B) 53
45
17
46
31
16
45 (SLOT C)
53
52
44
43
+ BIT 1
+BIT2
34
12
+ BIT7
+ P W REII (CC W)
II
33
32
22
50~__-_P_0~R_T__
5 ____~34
19~..........--+--'-'15:........--------;20
17
37
21
6
16
28
26
17
13
43
+ I6
+17
+ I8
18
16
44
15
33
II
13
+
+
+
+
37~__-~R~E~A~D~____~23
9
44
39
38
- RST
- ENABLE INP
PW STATUS
+ CHECK
8
43
40
37
22
29
27
14
+ PW FWD (CW)
+ CAR LINEAR MODE
+ PW LINEAR MODE
+ SERVO DISABLE
39
52
-WRITE
-SYSTEM CLOCK
31,32
25-32
DRIVER
RETURN
A.S,C
51-56
J5 & J6 not installed.
XOCR board.
- P W BUSY
-PFBUSY
-CAR BUSY
T9/ +PAPER OUT
T I ' +COVER OPEN
"
31
54
CARVEL STROBE
CAR FWD
CARREll
PW VEL STROBE
18
30
27
50
46
20
49~~__~C~L~0~C~K~A~~~2~2~------4¢5~P~W~PO~S~S~IG~3~__-+~35
32~____..:::C~AR:..::......;C"'U:.::S"-P_~48
XDCR 49 PIN POS SIG 2
38
1--"2 CAR 5
43
XA7
53 CAR POS SIG 2
49
22
21
24
1 J5 I I CAR 6
I
7 ~AR 3
:
4 I £AR 1
1
~! J;AR 2
30
32
53
r-----
I
r--,,",5
I J6
:
31~
PW 2
I
3' YW 3
, l PW5
-_..::..
T 12/
,
T 13)
28 .....+:..:0:.:.P..:.T..:..10::.;N~C::.;T:.:.R:..::L:.......:..1--i 4
27
+OPTIOF\J CTRL 2
3
51 (SLOT F)29
53
21.22
Pin designations start at center of motherboard, with even numbers on the
component side of the board.
-+____
________
+~L~E~D~D~R~I~V~E
CAR HOME
SOURCE/SENSOR
___________________________________________ ~~,,---2 J2
4
- LED RETURN
- SENSOR RETURN
+ CAR HOME SENSOR
L2KEY
r--
-+____________________________-~P~W~H~0~M~E~SE~N~S~0~R~R.::.E~T____------.,3J4
34~________
28
+ PW HOME SENSOR
2
-+____+~/~-~C~AR~S~E~R~V~O~E~R~R~0~R~--,
8~________-+____-~S~ER~V~O~D~IS~A~B~L~E~__,
16~________
+OPTION CTRL 3
36
39 (SLOT G) 55 CAR PaS SIG I
14
47 CAR PaS SIG 3
12
46 ,CAR LINEAR pas SIG
13
50 PW POS SIG I
II
T P W LINEAR POS SlG
48
47
51
36
40
P/W
-
(SLOT H) ;;
29 +/-PW SERVO ERROR
52
I 3 +HAMMER ENERGY CTI~L 50
21 PW6
35
37
____-~R~IB=~~~F=E=ED~X=2______________~~13
+ RIBBON FEED
21
10
36
33
13
22
7
14
12
10
6
8
491--1
~KEY
L---------l20
CAR
50 1 T4 PAPER FEED I
T4
'----------.,6 PWR AMP 33
T7 PAPER FEEDI (T7
1
30
23
10
+ RIB 0B
- RIB HOLD
- RIB LIFT
12
8
14
28
- HAMMER FIRE
38
51
34
XA4
.. P W SERVO ENA8LE 18 (SLOT 0) 36
0
./
~~A T6 PAPER FEED 2
34 ..........+:....;PO:...:..;W:.:.;E:.;.R.;.....::.ON'-=-__---i16
35r++~P~0~W~E:.:.R~O~N'---____________________________________________________________~==========~__~T
9~+~P~F'-'A~---------------------------------------------------------------------------------+~P~F~A~____-''''44
+ PFB
X3
-RIBBON FEED X4
-HAMMER COIL X5
+HAMMER COIL X6
+ RIBBON SENSOR DRIVE
+ END OF RIBBON SENSOR
IMPRESSION {
J 3 1 +IIIIPRESSION CTRL I
CONTROL
4
49
SWITCH KEY 2
3 1+IMPRESSION CTRL 2 48
71--+~R~I~B_0~A~______________________________________________________________~9
25
~O
+ RIBBON FEED XI
7~__~-r
9
8
.--'6
.J. _
+ REV/-FWD PW MOTOR
~I-W---+---+-------'''''':'':'::=--~'=''''':'''':':'''';:':''='''':-='':':'---------'''''''7
35 PWR AMP53h
+ FWD/-REV PW MOTOR
~ 18
X AS 54---+-+---..:.._..:..R-"16'-"BO:!.....!.N!!:Lo..!IF~T'-'C::..0..:.:IL=.!.~-----------RESSION CTRL 1
CONTROL
4
49
SWITCH KEY 2
3!+IMPRESSION CTRl 2 48
+.'- RI B ~A
7r-~~~--=~~~---------------------------------------------------------._19
30
23
10
+/- RIB
-
~B
RIB HOLD
RIB LIFT
POWER ON
~KEY
!
49
20
CAR
5011 T4 PAPER FEED 1 T4
L..._ _ _ _ ....-j8 PWR AMP 33
T7 PAffR F..E..E.l11 ~T7
~__
34U
51
XA4
+ P W SERVO ENABLE 18 (SLOT 0) 36
12
8
'4
28~--~-~~H~A~U~M~E~R~F~I~R=E----------------------------------------------------~-t3_B_________34~~1~+--:--:Pa~W~ER--:...:O--N~--4'6
+
~O
+ RIBBON FEED X1
7~--~-+--------R~IB~BO~N~F=E~ED~X~2----------------~~13
I
II
r-_ ......~+_---'-t .REV/-FWD PW MO_T:...:O::;Rc......________..I..1o-.--117
I--
~~-
11
ADDR 13
+ ADDR M
+ AODR 15
T14
NOTES:
:n,
f
T12
35.38
23.24
~~'~~~~~~~~~~~:~::~~~~~~:~~: LOXG~C2-2 ;~.~=~~==============+~+=:~:~~=~======================:~~~
I+COVER OPEN 32
(.~T14 (SIG GNO)
•
T15
41.42
-15VD
~~~~~~
5.6
-15VS
14~--~C~L~0~C~K~A=-----------~
9f_------------~-------- 9 1---_-+-...:D:.oA.:..:0:......------.-; 3
121----------------+--------- 12~~~+~D~A~I------~~12
.. +DA2
5
l1r-----------~------ "
131------------~------ , 3 t--'1----_+~D_A~3_ .--.---..... 11
B
+ oA4
4
8f_------------~-------10r---------------+-------- 10 ......0--_+..o.o_A..o.5 __ - - _ 6
+DA6
16
14~--------~--------- 14
+DA7
15
161----~~~~--_1------ '6
49f_--~P~0~R~T~4----~49
R
T
PO
5
50r----------------+--------- 50r--------- ------...... 34
48
48
- PORT 6
.. 26
46
46
- PORT 7
~ 26
37
101~-~E~N~D~0~F~R~'B~B_0_N
INTFC
______________________________________________________
XAI
271PW HOME
25
(SLOT A)25~~+~CA~R~H~O~M~E----------------------------....,26 SERVO
36
-PWPOSA
39
XA3
18 +PW EVEN
45 (SLOT C)
52
-CAR pos A
53
51
-CAR POS B
52
50 +CAR EVfN
._ 44
29
- P W POS B
43
TERM
T2.13
TB.T14
+-15VS
+15VD
OPT
XAB
W
~~e T6 PAPER FEED 2 ---"T6
32
47
4aW
T5 PAPER ~~T5
35~~~+~~/t-~~P~F~A~~~~~==================================================================:+7/7-~P~F~A-----1~44
+/ PFB
+1 PFB
10
2~
MOTHER BOARD 46080-01
REV.C
4-101
REVISION HISTORY -
46080-01 MOTHER BOARD
Rev. A
ECO A1759
8
A1869
Correct error in part no. on bill of material. No change to board.
C
A3603
Hardware change only. No change to board.
As released.
4-102
•
B1
Ti
L
(
~
l
0).'i
.~-
10 TO 0.2
Cl
C4
,.005;:1'0.,
4KV
SOOV
m··
I
2
1
LJI
005
(2
~
CR1
IoAR502
(MR504)
MR502
... - - -
CR2
"R502
R504)
F1
CR4
C:3
.005
1.4KV
SJ72BO\'>....JJ
I
1W
.... 'N4148
10
1W
.!,
.............
(250)
200V \400V)
I"
~-~
S_U_P_P-L-Y--~r---------:i;-1_-R-6'~r,."
.:,:",~
L_O_C__
A_L__+
__1_5_V___
R11
210K
lK
(~:~
51~2
~~~PF
fr,-;l
1KV
Q10
(39 K)
~
+---____--, ().
(T! P 49)
Q7
~-+
MPSA43
(2N 34 39)
T
-r;rM
_~------...J6
+
R30
C;~~
1/2w
I
In
'
1:;;,
I
1K,
d
,,1, H----~' ~:~,..
1.':-:~,- -4~'\:1\:6"K. -4. . . ,4R".,1/76K\rl~R",1 /:v- ~ -,: :.,.- j~ _.-_-:.r_~+
"
-;"
~~'9
RI8
~
~; 3 ~(10-
:~:,
CR1S
1N:;-48
1N:;-48
SWITCHING REGULATOR
AMPLIFIER
1KV
SMALL
I
TC17
CR20
BLK
' /2 W
L5
R54
47
1W
J
R46
-<
~
~'0
T
GND 2
1
C39 SR 3142
~3
If
o~~
100V
o~~
CR18
R51
1K
C44
C20
;~
... ,0.1
1W
100V
100V
C22
0.1
1000
35V
C37
/
I
1
.~~
L
:
L6
-15V
TO;
:
~. . . . . . . . . . . . . . . .·NC~5
"R8Z0
lCHASSI
GN
5
:
4
fm
1
H
1KV
Ii?
-
1
6
7
"'-
...
R5
e
R40
R60
R 59
R43
470
'"
t; ; <;~
MPS5172
INVERTER CURRENT LIMIT
SENSE AMPLIFIER
L-__________________~----~===========---~~~
F
;
~
,: :g;
G
WIRE
.A
-::;,
K
C25
,." ~~~o
R45
10
C36
,1
22'
1000
T~G'V
47
L. ___________
•
==
S
;::r: 35V ;:r: ~~eO
6
G"'------_.....
Cl\,Gu
1W
R32
OVER VOLTA
R63
R61
r~SI72~:
~ u,"" i:' I (~'~) 1 ' w"
(
~;~,~
R62
1~h\,,:~:;~
R1
2
--4JV,,9'\r-=--_----..
C7
D
1N~~8
Ol.~
6
---- ---y
---~--------------------------~----------------------------r-------r---------~------------t-+---.----4-t----~--~3~3~0~K---.-T~'1~K~--·TI----------------~----------~-t--+-~------+-------4-J
I
I
I
1N4~8
...:i..
>
II
C~3
CR14
5
. SJ.7.2.BO
.
. . . . .2.-jj,1 :
C~2
5
A~ P ~~:iF-1
~
:
C33
____________ ,
+
1RS~1 =1
~ :
Q1,:
:
1.0
4
1
1
35V CR 27...,....
+
sR~3.'4.2. .~. . . ._I............~~........~1~0~0~v. .~_4~~~~~~~G:E~~..~---~~..~~....+..5.v~1
1
:
~ 1000
C3Z
IN4001"'"
C~
=
-
1N:OOI
... ----·r..:-.:.'.:,'..:-.:.------------------ .----- ----------------- ..
'I
3
4
4.7
O'.~
+
C16
CR22 100V
I
• '.J::l TMR820
~~
+
[1''1'
~:
3
__~___~.__~______________--4__-:.4~
I
39K
5
~~_
R14
l50K
~REO
2
C12
I
I
=1
T.2. .
L--_ _ _ _ _ _ _
2N4126
SJ72BO
RED
• T,
2.T
.......,
~
TBl
- - -. .__. .~____. . . . . .__~,.+_1_5~V~
CR17
Pd~
• =:
=:
=.:
=,1
=1
R29
7,~ w~, .-+.._........I ..
•
CR19
4
T4
INVERTER DC/AC
1S0K
R13
0.1
100V
I..otI
11 . . 11111 . . . . . . . . . . . . . . . . . . . . . . . . . .
~PSA43
~
CR10
)
1 ;1
06
R12
L4
AC/DC
T6
2W
5W
3°/0
39K
51F2
r-r
,
'/ 2w
:7' 8
~ I
................ "".""".,, ". " .. " .. ".':
22K
'/ W
2
(560)
Q5
AND FILTER
5
P1
+ C10
!:-~.'6
L ___________________________
_
;::r=- ~OOV
r' 200V
C5
SOD
H
RECTIFIER
6
R28
100
1
<>
-=&'::--
'/ 2 W
(10K
1/zW)
OUTPUT
?6~
1W
22K
~.~6
CR6
.4~(~~~~~)
CRS
RS
y
RlO
7
8
L
Jl
•
R2
10"""'
iV;O""'"
'q:V(;i::~):
-----------------.. --------------~
r l_ _
9
SPIKE CATCHER
~2
(2N654S)'-+/ R3
•
'---.AAA~
"Q2
+
C23
~
<>
I
LC FILTER
Q1
82
R4
1.4KV
10
11
L2
~
10A
(~~~g~)
i (URS04)
4
POWER SWITCH
(~R3
&
Z
11
12
13
14
FULL WAVE BRIDGE
RECTIFIER AC/DC
·
,8
K
15
16
R6"i
R64
> 100
R66
> 100
100
R67
R6S
R69
100
100
100
C4Q
~~E---
~
0.01
100V
Q14
:
MPS15172
I
Q'5
MPSS172
I
i
1
--It-
0.01
100V
l
Q16
MPSS172
r-
<>:J..
,
E
Q17
t.4PS5172
R44
470
1 ~ !;:'
~
2N4126
R35
1K
1
OUTPUT CURRENT LIMIT SENSE
2
i-- ~-:
,tI
AMPLIFIER
I
D
+5V ERROR AMPLIFIER
I
. - - - - - - - - - _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ - - - - - - - - - - - , _ _ _ _ _ _ 1_ _ _ _ _ _ - - - - - - - - - - - - - - - - - - -
IU3
NOTES: UNLESS OTHERWISE SPECIFIED,
1. ALL RESISTANCES SPECIFIED IN OHMS.
2. ALL RESISTORS ARE 1/4 WATT, ± 5 % '
3. ALL CAPACITANCE SPECIFIED IN MICROFARADS.
4.
OEN01ES PRIMARY CIRCUIT COMMON RETURN.
C
&
&
In
!~
~.
8
10.
R33
SELECT TEST
LAST USED
C45
RESISTOR.
'6
_____ J
5
4
1K
REFERENCE DESIGNATION
<>
~A!y~
NOT USED
c
C15,16, 21,24,
26,27. 28,29
INSTALL JUMPER
FOR
INSTALL COMPONENTS
USE COMPONENT
115v
FOR
VALUES
(-all
220V:
OPERATION
02)
OPERATION
IN PARENTHESES
FOR
CR28
ONLY.
24, 25,26
ONLY.
220V (- 02)
CR23,
SCHEMATIC DIAGRAM
F1
L6
Q20
R70
OPERATION
ONLY.
USE ONLY UNGROUNDED TEST INSTRUMENTS WHEN TROUBLE-SHOOTING PRIMARY CIRCUITS
(ALL CIRCUITS OTHER THAN OUTPUT RECTIFIER AND FILTER, OVER VOLTAGE AND +5V ERRDR
ALTERNATE REFERENCE DESIGNATORS SHOWN IN PARENTHESES «CR8), (All, ETC.)
REFER TO SILKSCREENED INFORMATION ON SOME CIRCUIT BOARDS.
Diablo Systems Incorporated
Q12
R21.31,42,
50,52,53,55
AMPLIFIER).
RT1
seR1
T6
POWER SUPPLY, BOSCHERT U.L., •
115V/220V
T3
DRAW I NGS FURNISHED BY
BOSCH~:~ /SSOCIATESIJ;I~'!Z11!_'6"'l1=_'O,,/~1~6112~0Ilft'=!W-----"1
SCHEMATIC
POWER
SUPPLY
26021-XX
~--~~~~~~~~
26021- XX
17
4-103
TB1
1 [+5V]
2 [GND]
3 [GND]
4 [+15V]
5 [-15V]
6 [N.C.]
7 [CHASSIS GND]
8 [A.C. HOT]
9 [A.C. NEUT.]
115VA.C. VERSION
(26021-01)
TB1
1 [+5V]
2 [GND]
3 [GND]
'4 [+15V]
5 [-15V]
6 [N.C.]
7 [CHASSIS GND]
8 [A.C. HOT]
9 [A.C. NEUT.]
220VA.C. VERSION
(26021-02)
"DRAWINGS FURNISHED BY BOSCHERT ASSOICATES
FOR MAINTENANCE PURPOSES ONLY."
4-104
ASSEMBLY DWG.
POWER SUPPLY
26021-XX
Revision History - #26021-XX Power Supply
Rev. A
ECO#7472
As released
Rev. S
ECO#7504
Add requirement for label containing part number, serial number, and mfg.
date code.
Rev. C
ECO#7587
Add special label to 220V units.
Rev. C1
ECO#7631
Add schematic and assembly drawings to part no.
Rev. C2
ECO#7700
Correct minor schematic errors, add alternate reference designators.
Rev. C3
ECO#7758
Correct error on connection drawing, sheet 1.
Rev. C4
ECO#7899
Move cathode of diode CR27 from input to output of L4; reduces 5V ripple.
Make the following component changes:
Component
Was
Is
R3,R4,R5
01
03,04
CR19,CR20
R8
R9
R19
R22
% Watt
SJ7280(2N6308)
MPSA93
1N3889
22K
22K
160(33)
10(2.2)
1 Watt
SJ7280(2N6545)
MPSU60
SR3142
39K
22K(39K)
160(68)
10(4.7)
NOTE: Component values in parentheses are for 220V operation.
Rev. 0
ECOA#4251
Remove L3 to reduce noise
4-105
REVISION HISTORY - MISCELLANEOUS WIRE & CABLE ASSEMBLIES
(Including 24471 Rev. C)
D
A1102
Add wiring for I.h. paper feed (split platen) motor. (Not applicable to
HyTerm.)
two wires from cable spring to
E
A1244
Correct schematic error: swap wires on Tl0 & T12. (Not applicable to
HyTerm.)
Revise documentation and assembly to prevent wire breakage in cable spring.
F
A1582
Gray and green wires on P2-1&2 interchanged: gray to pin 2, green to pin 1.
As Released.
Rev. A
EC0#9684
B
9797
Revise documentation and assembly to
improve flexibility.
C
9901
remov~
P6
WHT
5~~B~~________~
2
7~~YE=L~______- - J
5
RED
3
I+.
PRINT WHEEL
TRANSDUCER
RED
BRN
YEL
2~~W~HT~______- - J
7
6~-=GR~N~______~
4~~GRA~Y________~
6
GRN
GRAY
CARRIAGE
MOTOR
a
r----...,
BLUE
P4
~>-~'--------~
•
~>--~I_R~E~D____~
(
I PWR
\ ....
AMPL
12
10
I
PCB
..... _ - -....... .J
WHT!GRN
WHT
'--______________ 111
HAMMER COIL
16
P2
BRN
17
ORG
18
19
CARRIAGE HOME
POSITION SENSOR
14
7
GRAY
2.>-ir-""---------"'"'
13
GRN
20
~431--'=BLK~___*"'"-_k__-_~
~_---~:E~H:~-----J~~----------~
IMPRESSIOH COOTIIIlL SWm:tl
4
P3
,r-----...,
!
5
(HAMMER ENERGY SELECT)
2
GRAY
, RED
T7~>-~~~-----J
\
•,
VEL
T6~'>-~I~~----~
i
T5~,>-~l~B~L~K~____J
\ MOTHER PCB
I
' ......... ----~
o
BU<
RED
OK GRN
LT
G~
' -_ _........._ _ _ _--J
I"II
RIBBON DRIVE MOTOR
RIBBON LIFT
SOLENOID
WHT!BLK
WHT!RED
T4~>--:i--.;;..;;;...---~
!\
YEL
BLUE
PRINT WHEEL
'--_ _--II--.W;.;.HT~/R~E~D_ _ HOME SENSOR
r.--------,:
PAPER FEED
MOTOR
YEL ,3
I
B~ 2
I
6
8
VIO
ORG
I
I
II REF.
ONLY
(END of RIBBON SENSOR)
l
I
II
II
r-----------~I~
I
I
_______ J
L~
PRINTER CABLES
24471
REV. F
4-106
6
7
8
!FULL-WAVE
BRI DGE
r----'
RECTIFIE R
T~l W4 : L~:"
ACHOT 8~r'n'~~. .-+......L
€R1
INPUT FILTER
D
,45210
II
lE:~1KV
i
:
I
I
I
CR4
I
'C,
I
0'
'
-
~R2)
r-'-\
ViW +
F3
......:51~
3A
3A
!
~(\
C4
!,::400
200V
R3
75~
+
'/2. W
i
C3
i
400 i
2.00V i
~
~
!....
.... _._._.,... _._._._ ..J
.A_._._._._._._._._._._._._.~~
r------ . .
R34
T;4
•
.._~~r~I~..---------------------------4~----~..__..~g:00l5
~-.~,,1
~
;
.. -' 3KV
R5
25
LZ
45246 (-01,-03)
45857 (-02,04)
f'"'\~'
T1
3
Z
4517Z
J...u..
-
S:T62"
;~OOP~1±R7f~
i?S
• :.L.u..
4-
~ 0.4KV
!
2.'0
~z ~ 200V
RG-;'"J
T4
T5
44908
44908
1
_ _-
A8
10
2
44;0~
4:- C27
I/~~~~
_3
~
~
14
~
QB.lJLE
•3
IC~'4
~N4002~
....
CR16
:CR39
I (8111)
:
I
RS
4.7
: 117'2)(
I
I
I
\lzw
I
I..
:
I
~
_·_· ••• ••••••••••••••••• •• c
P,-.
:
2.W
:
:
(B~Z)
I
~
1.4KV:
T7
z.ZK
J..A. _
L.,;J.
1N4~'
,
+
U V5
SENSE
---0--""
2" V
+
I
,
T8
P1-1
P1-4
-----0--1
REIAOTE
P2-5
---o---I--<>SC
P2-7
----0-...,
500
RN55C
VOLTAGE
1.30K
1 0/0
I
45572
:
I
:
I
I
:L- ___
...,:
.... ~
I
:2
RT
CONTROL
MODULE
R2G
_.... ...-, .... ,.,.,.,.,...,...... . .
R9
LI~IT I--r-+_ _ _
/
,--_ _ _-.-_-+-i_-".--t1'~'~ ......--T----<~-......--....:--~--+--~~---+---..-.;;..,p
±.;....,C6~:=:.t2........
~
....
*
+
Wl
~7
!lOOV CR20
1N4148
C30
;;: ... ~~~o
~
5
/1
CR34(VRZ)
r-----------------------~----~:-i~~~:J~' ~~z"
6
I
-L
I:
+5V
i
+
!:
rh
:.:::':':'::::.::,.:::.:,.::::.::::':;..:::.::.::.:.::1I ............................
.1
4561.
L.!:: __ ..J
~8
500~~
*~:~~V
o
!OVERVOLTAGE PROTECTION'
w,
r----' I""Y'Y'\
RiS
"
2.2K
~~PF
CR19 500V
'4~~Z~ IT
151~O:F!
/4
C13
,1
1 !
_~-
I,
C9
~
~4
T
r-'-'-'-'-'-~-'-'-'_'_'_I_'_'_'-'-'~-'-'-'-'"
5
CR'5
•
I
I"
~_ _ _ _ _-4C~~R7~_ _ _ _ _1t_.,!P__......~..~C~7~. ., .. .~T3~. . . .5.W. . . .~Z-J1 1'~__5+-~~T~6
RG1JC~
2.0
__
...u. iUJ..J.
~ riS362'
~ *~~iv
-02,-04 VERSIONS ONLY (+48V)
T2
~
~ RET~ 7
,11 ............................. ::'::::•••
POWER SWITCH (CHOPPER)
c
~
:
:
S
:
lOOV
E1
I
...,I····l·····
..........·..··. ···..·,···..·,·..··..•..··..··..····.......................................................................
!
OUTPUT RECTIFIER AND FILTER
I
...
i
;::r- (32
0.,
500
10W
~
R4
75K
115V·!
i
/
RT'(R')
CR2.
_
230V
+4BV
---r----"'" 6
!
I
1.4KV
TBl
-
~
7)--------.----<...- . - - . - - - . _.
.- .•.. ....•.. ..........•.. . _._._._.
115V
I
1
n.('
F2.
,
2
3
'LQ~ IAGE
DOUBLER/ FILTER
PROTECTION
9~
. .-!-...~..
L. ___~."~
-'
'-
4
'N4724(4)~. . .~.c;....~N-___. - - - - - - - - i - - - - - - - - ,
!~
:=:_21.
W5
ACNEUT
CR3
5
,]0
(~2
~?'N.7-'''~~
C~
R30
R32
130
130
C~8
REFERENCE DES",NATION
LAST USED NOT USED
05
0'
CR4Z
CRS,.6.17,18
F3
L5
F,
ALTERNATE REFERENCE DESIGNATORS SHOWN IN PARENTHESIS
(BR1, BR2,£TC.) REFER TO S[LKSCREENED INFORMATION
ON SOME CIRCUIT BOARDS.
5. USE ONLY UNGROUNDED TEST INSTRUMENTS WHEN TROUBLE-SHOOTING
PRIMARY CIRCUITS (ALL CIRCUITS OTHER THAN OUTPUT RECTIFIER
AND FILTER, AND OVER VOLTAGE).
QB
R40
IC~,~
~~·fi'4e(.) ~~41fi.'B(~ ~~N414B(4)
RT2
seR 1
T8
SCHEMATIC DIAGRAM
CURRINT
A
P1 1
CURIHNT L'IJIT BIA.,
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~~~~I~IT
(R~
t R1tj
CR?!
J-.-O-------.....---'------~!_---.....---~-----"--
CR2'5 CR27
CR29 CR31
c~a3~
PRIMARY
C,.URRENJ
LlMn.SENSE .
... _-_._.•. _._ ..
OUTPUT CU RRENT LIMIT SENSE
POWER 5UPPLY,3+4 OUTPUT, 115V/230V.
.-'-'-'-'.'-'-'-'-'-'_'_'_I_._._'-'-'~
400062-XX
7
2
1
4-107
WSCRI
DRAWING FURNISHED BY L.H. RESEARCH INC
FOR MAINTENANCE PURPOSES ONLY
ASSEMBLY DWG.
POWER SUPPLV
400062-XX
4-108
8
I
1
7
6
4
I
5
I
1
I
J
1
2
I
lOEVE~NTI
6<;8£2
01
NOTES:
0
WIPI
AC HOT
-
\
)
SAFETY GND
AC NEUT
..n.
II
11
U
WI
I--A~T-- ~
I
&
CONTROL fll r'r~" fTJ:cu..
I
I
II
I
15
rTu
I
..
NOrT~o
NC>
1- mIOOf'Tu ..
IS
rT~o
I
NO
1O
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