82720_Data_Sheet_Preliminary_Jun83 82720 Data Sheet Preliminary Jun83

User Manual: 82720_Data_Sheet_Preliminary_Jun83

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82720
GRAPHICS DISPLAY CONTROLLER
• Displays Low-to-High Resolution
Images
• Draws Characters, Points, Lines, Arcs,
and Rectangles
• Supports Monochrome, Gray Scale, or
Color Displays
• Zooms, Pans and Windows Through a
4 Mpixel Display Memory

• Extremely Flexible Programmable
Screen Display, Blanking, and Sync
Formats
• Compatible with Intel's Microprocessor
Families
• High-Level Commands Off Load Host
Processor from Bit Map Loading and
Screen Refresh Tasks
• Supports Graphics, Character, and
Mixed Display Modes

FUNCTIONAL DESCRIPTION
Introduction
The 82720 Graphics Oisplay Controller (GOC) is an intelligent microprocessor peripheral designed to drive highperformance raster-scan computer graphics and character CRT displays. Positioned between the video display
memory and Intel microprocessor bus, the GOC performs the tasks needed to generate the raster display and
manage the display memory. Processor software overhead is minimized by the GOC's sophisticated instruction
set, graphics figure drawing, and OMA transfer capabilities. The display memory directly supported by the GOC
can be configured in any number of formats and sizes up to 256K 16-bit words. The display can be zoomed and
partitioned screen areas can be independently scrolled and panned. With its light pen input and multiple controller
capability, the GOC is ideal for most computer graphics applications. Systems implemented with the GOC can
be designed to be compatible with standards such as VOl, NAPLPS, GKS, Core, or custom implementations.

eo

'" 0---<_ _ _--'

2~WClK

"IEXT:SYNC
BLANK
RAs(ALE)

PROCESSOR

WIT'"
CONTROL ROM
128 x 14

Vee
A-17

"

4
5
6

37
36

AD-14

35

AO·13

"
"

33

DACK

COMMANO

40
39

8272D

AD-"

31 ]
30

AD·9
AD-S

29
28

AD·7
AO-6

"

PARAMETER

"

2S

A[).3

24

AO·2

""

16x8

GND

0---

2xWClJ(

0----

Figure 1_ Block Diagram

Figure 2. Pin Configuration

Intel Corporation Assumed No Responsibility for the Use of Any CircUItry Other Than Circuitry Embodied in an Intel Product. No Other Clrcuil Palent licenses arc Implied. Information
contained herein supersedes previously published specifications on these devices from Intel.
@INTEL CORPORATION 1983

JUNE 1983
ORDER NUMBER: 210655-002

82720

Table 1. Pin Description
Symbol
2XWCLK

Pin No.

Type

1

I

DBIN

2

HSYNC

3

a
a

V/EXT
SYNC

4

I/O

Name and Description
Clock Input
Display Bus Input: Read strobe output used to read display memory data into the GDC.
Horizontal Sync: Output used to initiate the horizontal retrace of the CRT display.
Vertical Sync: Output used to initiate the vertical retrace of the CRT display. In slave
mode, this pin is an input used to synchronize the GDC with the master raster timing
device.

BLANK

5

RAS (ALE)

6

a
a

DRQ

7

a

DMA Request: Output used to request a DMA transfer from a DMA controller (8237) or
I/O processor (8089).

DACK

8

I

DMA Acknowledge: Input used to acknowledge a DMA transfer from a DMA controller
or I/O processor.

RD

9

I

Read: Input used to strobe GDC Data into the microprocessor.

WR

10

I

Write: Input used to strobe microprocessor data into the GDG.

Blank: Output used to suppress the video signal.
Row Address Strobe (Address Latch Enable): Output used to start the control timing
chain when used with dynamic RAMs. When used with static RAMs, this signal is used
to demultiplex the display address/data bus.

AO

11

I

Register Address: Input used to select between commands and data read or written.

DBO

12

I/O

Bidirectional Microprocessor Data Bus Line: Input enabled by WR. Output enabled
by RD.

DB1
DB2
DB3
DB4
DB5
DB6
DB7

13
14
15
16
17
18
19

GND

20

Vee

40

Ground.

A1?

39

a

Graphics Mode: Display Address Bit 17 Output
Character Mode: Cursor and Line Counter Bit 4 Output
Mixed Mode: Cursor and Image Mode Flag

A 16

38

a

Graphics Mode: Display Address Bit 16 Output
Character Mode: Line Counter Bit 3 Output
Mixed Mode: Attribute Blink and Line Counter Reset

AD 15
AD14
AD 13
AD12
AD11
AD10
AD g
ADa
AD?
AD6
AD5
AD4
AD3
AD2
AD1
ADo

37
36
35

I/O

Graphics Mode: Display Address/Data Bits 13-15
Character Mode: Line Counter Bits 0-2 Output
Mixed Mode: Display Address/Data Bits 13-15

34
33
32
31
30
29
28
27
26
25
24
23
22

I/O

Display Address/Data Bits 0-12

LPEN

21

I

+ 5V Power Supply

Light Pen Detect Input

2

210655-002

82720

FUNCTIONAL DESCRIPTION (Continued)

Zoom and Pan Controller

Microprocessor Bus Interface

The contents of the FIFO are interpreted by the command processor. The command bytes are decoded, and
the succeeding parameters are distributed to their
proper destinations within the GOC. The bus interface
has priority over the command processor when both
access the FIFO simultaneously.

Based on the programmable zoom display factor and
the display area parameters in the parameter RAM,
the zoom and pan controller determines when to
advance to the next memory address for display
refresh and when to go on to the next display area. A
horizontal zoom is produced by slowing down the
display refresh rate while maintaining the video sync
rates. Vertical zoom is accomplished by repeatedly
accessing each line a number of times equal to the
horizontal repeat. Once the line count for a display
area is exhausted, the controller accesses the starting address and line count of the next display area
from the parameter RAM. The system microprocessor, by modifying a display area starting address,
allows panning in any direction, independent of the
other display areas.

DMA Control

Drawing Processor

The OMA Control circuitry in the GOC coordinates data
transfers when using an external OMA controller. The
OMA Request and Acknowledge handshake lines interface with an 8257 or 8237 OMA controller or 8089 1/0
processor, so that display data can be moved between
the microprocessor memory and the display memory.

The drawing processor contains the logic necessary
to calculate the addresses and positions of the pixels
of the various graphics figures. Given a starting pOint
and the appropriate drawing parameters, the drawing processor needs no further assistance to complete the figure drawing.

Parameter RAM

Display Memory Controller

The 16-byte RAM stores parameters that are used
repetitively during the display and drawing processes.
In character mode, the RAM holds the partitioned display area parameters. In graphics mode, the RAM also
holds the drawing pattern and graphics character.

The display memory controller's tasks are numerous.
Its primary purpose is to multiplex the address and
data information in and out of the display memory. It
also contains the 16-bit logic units used to modify the
display memory contents during RMW cycles, the
character mode line counter, and the refresh counter
for dynamic RAMs. The memory controller apportions the video field time between the various types
of cycles.

Control of the GOC by the system microprocessor is
achieved through an 8-bit bidirectional interface.
The status register is readable at any time. Access to
the FIFO buffer is coordinated through flags in the
status register.

Command Processor

Video Sync Generator
Based on the clock input, the sync logic generates
the raster timing signals for almost any interlaced,
non-interlaced, or "repeat field" interlaced video format. The generator is programmed during the idle
period following a reset. In video sync slave mode, it
coordinates timing between the GOC and another
video source.

Light Pen Debouncer
Only if two rising edges on the light pen input occur
at the same pOint during successive video fields are
the pulses accepted as a valid light pen detection. A
status bit indicates to the system microprocessor
that the light pen register contains a valid address.

Memory Timing Generator

System Operation

The memory timing circuitry provides two memory
cycle types: a two-clock period refresh cycle and the
read-modify-write (RMW) cycle which takes four
clock periods. The memory control signals needed to
drive the display memory devices are easily
generated from the GOC's RAS(ALE) and OBIN
outputs.

The GOC is designed to work with Intel microprocessors to implement high-performance computer
graphics systems. System efficiency is maximized
through partitioning and a pipelined architecture. At
the lowest level, the GOC generates the basic video
3

210655-002

82720

many cost/performance tradeoffs for both display and
drawing are realizable.

raster timing, including sync and blanking signals.
Partitioned areas on the screen and zooming are
also accomplished at this level. At the next level,
video display memory is modified during the figure
drawing operations and data moves. Third, display
memory address are calculated pixel by pixel as
drawing progresses. Outside the GDC at the next
level, preliminary calculations are done to prepare
drawing parameters. At the fifth level, the picture
must be represented as a list of graphics figures
drawable by the GDC. Finally, this representation
must be manipulated, stored and communicated.
The GDC takes care of the high-speed and repetitive
tasks required to implement graphics systems.

The video memory can be partitioned into 4 banks,
each 1024 x 1024 bits. By selecting all 4 memory
banks during display, 4 bits/pixel can be provided by
a single 82720. Each bank of video memory contributes 1 bit to each pixel. This configuration can
support color monitors, again with a maximum dot shift
rate of 44 or 88 MHz.
Higher performance may be achieved by using multiple 82720s. Multiple 82720s can be used to support
mutliple display windows, increased drawing speed,
or increased bits per pixel. For display windows,
each 82720 controls one window of the display. For
increased drawing speed, multiple 82720s are
operated in parallel. For increased bitsipixel, each
82720 contributes a portion of the number of bits
necessary for a pixel.

GENERAL OVERVIEW
In order to minimize system bus loading, the 82720 uses
a private video memory for storage of the video image.
Up to 512K bytes of video memory can be directly supported. For example, this is sufficient capacity to store
a 2048 x 2048 pixel x 1 bit image. Images can be
_generated on the screen by:

CHARACTER DISPLAY CONFIGURATION
Although the 82720 is intended primarily for rasterscan graphics, it can be used as a character display
controller. The 82720 can support up to 8K by 13 bits
of private video memory in this configuration (1 character = 13 bits). This is sufficient memory to store 4
screens of data containing 25 rows by 80 characters.
The 82720 can display up to 256 characters per row.
Smooth vertical scrolling of each of 4 independent
display partitions is also supported.

-Drawing Commands
-Program-Controlled Transfers
-DMA Transfers from System Memory
The 82720 can be configured to support a wide variety of graphics applications. It can support:
-High Dot Rates
-Color Planes
-Horizontal Split Screen
-Character-oriented Displays
-Multiplexed Graphic and Character Display

MIXED DISPLAY CONFIGURATION
The GDC can support a mixed display system for
both graphic and character information. This capability allows the display screen to be partitioned between graphic and character data. It is possible to
switch between one graphic display window and one
character display window with raster line resolution.
A maximum of 256K bytes of video memory is supported in this mode: half is for graphic data, half is for
character data. In graphic mode, a one megapixel
image can be stored and displayed. In character mode,
64K, 16-bit characters can be stored.

GRAPHIC DISPLAY CONFIGURATIONS
The 82720 provides the flexibility to handle a wide
variety of graphic applications. This flexibility results
from having its own private video memory for storage
of the graphics image. The organization of this
memory determines the performance, the number of
bits/pixel and the size of the display. Several different
video memory organizations are examined in the following paragraphs.

DETAILED OPERATIONAL DESCRIPTION

In the simplest 82720 system, the memory can store up
to a 2048 x 2048 x 1 bit image. It can display a 1024
x 1024 x 1 bit section of the image at a maximum dot
rate of 44 MHz, or 88 MHz in wide mode. In this configuration, only 1 bit/pixel is used.

The GDC can be used in one of three basic modes
-Graphics Mode, Character Mode and Mixed Mode.
This section of the data sheet describes the following
for each mode:
1.
2.
3.
4.

By partitioning the memory into multiple banks, color,
gray scale and higher bandwidth displays can be supported. By adding various amounts of external logic,
4

Memory organ ization
Display timing
Special Display functions
Drawing and writing
210655-002

intel'

82720

Graphics Mode Memory Organization

Graphics Mode Special Display Functions:

The Display Memory is organized into 16-bit words
(32-bit words in wide mode). Since the display memory
can be larger than the GRT display itself, two width
parameters must be specified: display memory width
and display width. The Display width (in words) is
selected by a parameter of the Reset command. The
Display memory width (in words) is selected by a parameter of the Pitch command. The height of the Display
memory can be larger than the display itself. The height
of the Display is selected by a parameter of the Reset
command. The GDG can directly address up to 4Mbits
(O.5Mbytes) of display RAM in graphics mode.

WINDOWING
The GDG's Graphics Mode Display can be divided
into two windows on the screen, upper and lower.
The windows are defined by parameters written into
the GDG's parameter RAM. Each window is specified
by a starting address and a window length in lines. If
the second window is not used, the first window
parameters should be specified to be the same as the
active display length,
ZOOMING
A parameter of the GDG's zoom command allows
zooming by effectively increasing the size of the dots
on the screen. This is accomplished vertically by
repeating the same display line. The number of times
it is repeated is determined by the display zoom factor parameter. Horizontally, zoom is accomplished by
extending each display word· cycle and displaying
fewer words per line, according to the zoom factor. It
is the responsibility of the microprocessor controlling the GDG to provide the shift register clock circuitry with the zoom factor required to slow down the
shift registers to the appropriate speed. The frequency of the 2XWGLK should not be changed. The
zoom factor must be set to a known state upon
initialization.

Graphics Mode Display Timing
All raster blanking and display timings of the GDG are
a function of the input clock frequency. Sixteen or
32 bits of data are read from the RAM and loaded into
a shift register in each two clock period display cycle.
The Address and Data busses of the GDG are multiplexed. In the first part of the cycle, the address of the
word to be read is latched into an external demultiplexer.
In the second part of the cycle the data is read from
the RAM and loaded into the shift register. Since all 16
(32) bits of data are to be displayed, the dot clock is
8 x (16 x) the GDG clock or 16 x (32 x) the Read cycle
rate.

PANNING
Panning is accomplished by changing the starting
address of the display window. In this way, panning is
possible in any direction, vertically on a line by line
basis and horizontally on a word by word basis.

Parameters of the Reset or Sync command determine
the horizontal and vertical front porch, sync pulse, and
back porch timings. Horizontal parameters are specified
as multiples of the display cycle time, and vertical parameters as a multiple of the line time.

Graphics Mode Drawing and Writing

Another Reset command parameter selects interlaced
or non-interlaced mode. A bit in the parameter RAM can
define Wide Display Mode. In this mode, while data is
being sent to the screen, the display address counter
is incremented by two rather than one. This allows the
display memory to be configured to deliver 32 bits from
each display read cycle.

The GDG can draw solid or patterned lines, arcs, Circles,
rectangles, slanted rectangles, characters, slanted characters, filled rectangles. Direct access to the bit map
is also provided via the DMA Gommands and the Read
or Write data commands.
MEMORY MODIFICATION
All drawing and writing functions take place at the
location in the display RAM specified by the cursor.
The cursor is not displayed in Graphics Mode. The
cursor location is modified by the execution of drawing, reading or writing commands. The cursor will
move to the bit following the last bit accessed.

The V Sync command specifies whether the V Sync
Pin is an input or an output. If the V Sync Pin is an
output, the GDG generates the raster timing for the
display and other GRT controllers can be synchronized to it. If the V Sync pin is an input, the GDG can
be synchronized to any external vertical Sync signal.

5

210655-002

82720

READING AND DRAWING COMMANDS
After the modification mode has been set and the
parameter RAM has been loaded, the final drawing
parameters are loaded via the figure specify (FIGS)
command. The first parameter specifies the direction in which drawing will occur and the figure type to
be drawn. This parameter is followed by one to five
more parameters depending on the type of character
to be drawn.

Each bit is drawn by executing a Read-Modify-Write
cycle on the display RAM. These R/MIW cycles normally'
require four 2XWCLK cycles to execute. If the display
zoom factor is greater than two, each R/M/W cycle will
be extended to the width of a display cycle. Write Data
(WDAT), Read Data (RDAT), DMA write (DMAW) and
DMA read (DMAR) commands can be used to examine or modify one to 16 bits in each word during each
R/M/W cycle. All other graphics drawing commands
modify one bit per R/M/W cycle.

The direction parameter specifies one of eight octants in which the drawing or reading will occur. The
effect of drawing direction on the various figure
types is shown in Figure 9.

An internal 16-bit Mask register determines which bit(s)
in the accessed word are to be modified. A one in the
Mask register allows the corresPQnding bit in the display
RAM to be modified by the R/M/W cycle. A zero in the
Mask register prevents the GDC from modifying the corresponding bit in the display RAM.

RDAT, WDAT, DMAR, and DMAW Operations move
through the Display memory as shown in the "DMA"
Column.

The mask must be set by the Mask Command prior to
issuing the WDAT or DMAW command. The Mask register is automatically set by the CURS command and
manipulated by the graphics commands.

The other parameters required to set up figure reading
or drawing are shown in Figure 3.

The display RAM bits can be modified in one of four
ways. They can be set to 1, reset to 0, complemented
or replaced by a pattern.

DRAWING TYPE

DC

0

02

INITIAL VALUE'
I~II

LINE

When replace by a pattern mode is selected, lines,
arcs and rectangles will be drawn using the 16-bit
pattern in parameter RAM bytes 8 and 9.

ARC··

rsln ,pI

RECTANGLE

21~DI -I~II

2(I~DI - I~II)

01

OM

-1

-1

21~DI

'-1

2(,-1)

-1

rsln 91

A-I

B-1

-1

A-I

AREA FILL

B-1

A

A

GRAPHIC

B-1

A

A

CHARACTER"·

In set, reset, or complement mode, parameter RAM
bytes 8 and 9 act as another level of masking for line
arc and rectangle drawing. As each 16-bit segment
of the line or arc is drawn, it is checked against the
pattern in the parameter RAM. If the pattern RAM bit
is a one, the display RAM bit will be set, reset, or
complemented per the proper modes. If the pattern
RAM bit is a zero, the display RAM bit won't be
modified.

WRITE DATA

W-l

DMAW

0-1

C-l

OMAR

0-1

C-2

READ DATA

(C-2)/2t

W

'INITIAL VALUES FOR THE VARIOUS PARAMETERS ARE LOADED
WHEN THE FIGS COMMAND BYTE IS PROCESSED.

"CIRCLES ARE DRAWN WITH 8 ARCS, EACH OF WHICH SPAN 45°,
SO THAT SIN" = lIoJ2 AND SIN 8 = O.
"'GRAPHIC CHARACTERS ARE A SPECIAL CASE OF BIT·MAP

'- AREA FILLING IN WHICH B AND A so. IF A "" 8 THERE IS NO
NEED TO LOAD 0 AND 02.
WHERE:
-1 ALL ONES VALUE.
ALL NUMBERS ARE SHOWN IN BASE 10 FOR CONVENIENCE. THE GDe
ACCEPTS BASE 2 NUMBERS (25 COMPLEMENT NOTATION WHERE
APPROPRIATE).
- = NO PARAMETER BYTES SENT TO GDe FOR THIS PARAMETER.
al = THE LARGER OF .6.x OR ay.
.6.0 THE SMALLER OF ax OR !J.y.
r= RADIUS OF CURVATURE, IN PIXELS.
rp= ANGLE FROM MAJOR AXIS TO END OF THE ARC. 


~

Character Slant Char Rectangle

,,
,

L4'

r~~~,.

~

~

111

tN
~

,
•
.. ~

0

m

0

Y

0

~
2-- - .
-

~~ -,,~~'1
'

"

.'

~

I
I

~

110

1•

<>

DMA

4

r.
,
,

,

I
I

...

-~'~J

I /
~

:;

~

<>

~

Figure 9. Effect of the Direction Parameter

12

210655-002

inter

82720

Drawing Parameters

memory as many times as desired without reloading
the parameter RAM.

In preparation for graphics figure drawing, the GDC's
Drawing Processor needs the figure type, direction
and drawing parameters, the starting pixel address,
and the pattern from the microprocessor. Once these
are in place within the GDC, the Figure Draw command, FIGD, initiates the drawing operation. From
that point on, the system microprocessor is not involved in the drawing process. The GDC Drawing
Processor coordinates the RMW circuitry and address registers to draw the specified figure pixel by
pixel.

Once the parameter RAM has been loaded with up to
eight graphics character bytes by the appropriate
PRAM command, the GCHRD command can be used
to draw the bytes into display memory starting at the
cursor. The zoom magnification factor for writing,
set by the zoom command, controls the size of the
character written into the display memory in integer
multiples of 1 through 16. The bit values in the PRAM
are repeated horizontally and vertically the number
of times specified by the zoom factor.
The movement of these PRAM bytes to the display
memory is controlled by the parameters of the FIGS
command. Based on the specified height and width
of the area to be drawn, the parameter RAM is
scanned to fill the required area.

The algorithms used by the processor for figure
drawing are designed to optimize its drawing speed.
To this end, the specific details about the figure to be
drawn are reduced by the microprocessor to a form
conducive to high-speed address calculations within
the GDC. In this way the repetitive, pixel-by-pixel
calculations can be done quickly, thereby minimizing
the overall figure drawing time. Figure 3 summarizes
the parameters.

For an 8-by-8 graphics character, the first pixel drawn
uses the LSB of RA-15, the second pixel uses bit 1 of
RA-15, and so on, until the MSB of RA-15 is reached.
The GDC jumps to the corresponding bit in RA-14 to
continue the drawing. The progression then advances
toward the LSB of RA-14. This snaking sequence is continued for the other 6 PRAM bytes. This progression
matches the sequence of display memory addresses
calculated by the drawing processor as shown in
figure 9. If the area is narrower than 8 pixels wide, the
snaking will advance to the next PRAM byte before the
MSB is reached. If the area is less than 8 lines high,
fewer bytes in the parameter RAM will be scanned. If
the area is larger thaf1 8 by 8, the GDC will repeat the
contents of the parameter RAM in two dimensions.

Graphics Character Drawing
Graphics characters can be drawn into display
memory pixel-by-pixel. The up to 8-by-8 character is
loaded into the GDC's parameter RAM by the system
microprocessor. Consequently, there are no
limitations on the character set used. By varying the
drawing parameters and drawing direction,
numerous drawing options are available. In area fill
applications, a character can be written into display

13

210655-002

inter

82720

Parameter RAM Contents

In addition, there are two mode bits for each area
which specify whether the area is a bit-mapped
graphics area or a coded character area, and
whether a normal or wide display cycle is to be used
for that area.

The parameters stored in the parameter RAM,
PRAM, are available for the GOG to refer to
repeatedly during figure drawing and rasterscanning. In each mode of operation the values in the
PRAM are interpreted by the GDG in a predetermined fashion. The host microprocessor must load
the appropriate parameters into the proper PRAM
locations. PRAM loading command allows the host
to write into any location of the PRAM and transfer as
many bytes as desired. In this way any stored parameter byte or bytes may be changed without influencing the other bytes.

The other use for the PRAM contents is to supply the
pattern for figure drawing when in a bit-mapped
graphics area or mode. In these situations, PRAM
bytes 8 through 16 are reserved for this patterning
information. For line, arc, and rectangle drawing
(linear figures) locations 8 and 9 are loaded into the
Pattern register to allow the GDG to draw dotted,
dashed, etc. lines. For area filling and graphics bitmapped character drawing locations 8 through 15
are referenced for the pattern or character to be
drawn.

The PRAM stores two types of information. For
specifying the details of the display area partitions,
blocks of four bytes are used. The four parameters
stored in each block include the starting address in
display memory of each display area, and its length.

Details of the bit assignments are shown on the following pages for the various modes of operation.

14

210655-002

inter

82720

RA_10S~,

_ _ _ _S_AID_1L_ _ _ _

.

SAD1 H

~

,.1

L-~__~__~~~~I__~I~-L__~

DISPLAY PARTITION AREA 1 STARTING
ADDRESS WITH LOW AND HIGH

~~~~~~4~CEFIELDS(WORD

LENGTH OF DISPLAY PARTITION 1
(LINE COUNT) WITH LOW AND HIGH
SIGNIFICANCE FIELDS.
THE IMAGE BIT AFFECTS THE
OPERATION OF THE DISPLAY ADDRESS
COUNTER IN CHARACTER MODE. IF
'--------------

~~~~NAC~EE~I~~~ ~~~N~T AFTER
EACH READ CYCLE. IF THE IMAGE
BIT IS SET, IT WILL INCREMENT
BY ONE AFTER EVERY TWO
READ CYCLES.
A WIDE DISPLAY CYCLE WIDTH
OF TWO WORDS PER MEMORY CYCLE
IS SELECTED FOR THIS DISPLAY

'----------------

RA-4
I

o

I

I

I 0 I 0 !
I

LE~2L I

WD2!IM!
I

SA?2L

I

I

~~~~II~pl~~:~1k~~f~~~r~\~R IS
THEN INCREMENTED BY 2 FOR EACH
DISPLAY SCAN CYCLE. OTHER MEMORY
CYCLE TYPES ARE NOT INFLUENCED.

DISPLAY PARTITION 2 STARTING
. - ADDRESS AND LENGTH

I

SAD2 H

I

I
0

I

I
LEN2H
I
I
!

I
0

0

0

I

I

I

L
DISPLAY PARTITION 3 STARTING
ADDRESS AND LENGTH

RA-B

10
11

RA-12

DISPLAY PARTITION 4 STARTING
ADDRESS AND LENGTH

13
14
15

~-------------------------------------------------------------------------~
Figure 10. Parameter RAM Contents-Character Mode

15

210655-002

intel'

82720

RA-O

L-~__~__L-S_A~~_1_L~ ~ L-~I~
__

__

~_S_A..I.~_1_M-I- ~

1

1

IL__J....-I__

2

~1 ~_LE~~_1_L~ ~I O~_O~I~S_A~f_1H~1
__

__

DISPLAY PARTITION AREA 1
STARTING ADDRESS WITH LOW,
MIDDLE, AND HIGH SIGNIFICANCE
FIELDS (WORD ADDRESS).

__L-.....

__ __

'T\'----LE_~1H_t-

LENGTH OF DISPLAY PARTITION
AREA 1 WITH LOW AND HIGH
SIGNIFICANCE FIELDS (LINE COUNT)

IN MIXED MODE, A 1 INDICATES AN
IMAGE OR GRAPHICS AREA, AND A a
INDICATES A CHARACTER AREA. IN
GRAPHICS MODE THIS BIT MUST BE O.

WIDE DISPLAY CYCLE MODE BIT

7

DISPLAY PARTITION AREA 2
STARTING ADDRESS AND LENGTH WITH
IMAGE IDENTIFY BIT AS IN AREA 1.

SAD2 L

RA-4

WD2

}

RA-10

GCHR 6

11

GCHR 5

12

GCHR 4

13

GCHR 3

14

GCHR 2

PATTERN OF 16 BITS USED FOR
FIGURE DRAWING TO PERFORM
DOTTED, DASHED, ETC. LINES

GRAPHICS CHARACTER BYTES
TO BE MOVED INTO DISPLAY
MEMORY WITH GRAPHICS
CHARACTER DRAWING

15

Figure 11_ Parameter RAM Contents-Graphics and Mixed Graphics and Character Modes

16

210655-002

inter

82720

RESET:

oI

0

SYNC:

0

0

VSYNC:

0

I

I
I
I

0

I

I

0

CCHAR:

0

0

1

1

1

1

0

WDAT:

DE

MASK:

M

FIGS:

I

I
I

MOD
I

FIGD:

1

GCHRD:

START:

BCTRL:

0

ZOOM:

0

CURS:

0

PRAM:

oI

0

I

I

RDAT:

DE

I
I
SA

TyrE

0

LPRD:

0

DMAW:

PITCH:

I

CURD:

DMAR:

I

1

1

1

I
I

I
I

0

MOD

I

0

0

TYPE
I

TYPE
I

II

I I
II

MOD

I

MOD
I

Figure 12. Command Bytes Summary

VIDEO CONTROL COMMANDS

RESET:

I

0

I

0

!

0

!

0

,

0

,

0

,

0

1

0

I

BLANK THE DISPLAY, ENTER IDLE MODE.
AND INITIALIZE WITHIN THE GDC:
-FIFO
-COMMAND PROCESSOR
-INTERNAL COUNTERS

Figure 13. Reset Command

RESET COMMAND

If followed by parameter bytes. this command also
sets the sync generator parameters as described
below. Idle mode is exited with the STARTcommand.

This command can be executed at any time and does
not modify any of the parameters already loaded into
the GDC.

17

210655-002

82720

P1

0 °ICIFIIIDIGIS
AW

P2
VS L

P3

P5
P6

I

I

I

0

.,.

HFP
I
I

P8

I

i:

0 01
0 01

I

HBP

I

I

I

VFP

VBP
I
I

~

V?"

HORIZONTAL SYNC WIDTH -1
VERTICAL SYNC WIDTH, LOW BITS

I--

VERTICAL SYNC WIDTH, HIGH BITS
HORIZONTAL FRONT PORCH WIDTH -1.

_ _ HORIZONTAL BACK PORCH WIDTH -1.
_ _ VERTICAL FRONT PORCH WIDTH
ACTIVE DISPLAY LINES PER VIDEO FIELD,
- - LOW BITS

ALL

P7

MODE CONTROL BITS.
SEE FIGURE 15.
_ _ ACTIVE DISPLAY WORDS PER LINE -2. MUST
BE EVEN NUMBER WITH BIT ~ O.

HS

1

\
P4

__

I

I

I

AL
ACTIVE DISPLAY LINES PER VIDEO FIELD,
I" - - HIGH BITS
VERTICAL BACK PORCH WIDTH

Figure 14, Optional Reset Parameters

In graphics mode, a word is a group of 16 pixels. In
character mode, a word is one character code and its
attributes, if any.

HORIZONTAL BACK PORCH CONSTRAINTS
1. In general:
HBP 2:3 words
2. If interlaced display mode is used, or more than one
partition is displayed:
HBP 2:5 words

The number of active words per line must be an even
number from 2 to 256.

MODE CONTROL BITS (FIGURE 15)

An all-zero parameter value selects a count equal to
2n where n = number of bits in the parameter field for
vertical parameters.

Repeat Field Framing:

All horizontal widths are counted in display words.
All vertical intervals are counted in lines.

Interlaced Framing:

Sync Parameter Constraints
Noninterlaced Framing:

HORIZONTAL FRONT PORCH CONSTRAINTS
1. In general:
HFP 2:2 words
2. If DMA is used, or the display zoom factor is greater
than one in interlaced display mode:
HFP 2:3 words
3. If the GDC is used in slave mode:
HFP 2:4 words
4. If the light pen input is used:
HFP 2:6 words

2 Field Sequence with V2
line offset between otherwise identical fields.
2 Field Sequence with V2
line offset. Each field displays alternate lines.
1 field brings all of the information to the screen.

Total scanned lines in interlace mode is odd. The
sum of VFP + VS + VBP + AL should equal one less
than the desired odd number of lines.
Dynamic RAM refresh is important when high display
zoom factors or DMA are used in such a way that not
all of the rows in the RAMs are regularly accessed
during display raster generation and for otherwise
inactive display memory.

HORIZONTAL Sync CONSTRAINTS
1. If dynamic RAM refresh is used:
HS 2:2 words
2. If interlaced display mode is used:
HS 2:5 words

Access to display memory can be limited to retrace
blanking intervals only, so that no disruptions of the
image are seen on the screen.
18

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82720

DISPLAY MODE

CG

0 0

MIXED GRAPHICS & CHARACTER

0 1

GRAPHICS MODE

1 0

CHARACTER MODE

1 1

INVALID

VIDEO FRAMING

IS

o

0

0 1

NONINTERLACED
INVALID

1 0

INTERLACED REPEAT FIELD
FOR CHARACTER DISPLAYS

1 1

INTERLACED

D

DYNAMIC RAM REFRESH CYCLES ENABLE

0

NO REFRESH-STATIC RAM

1

REFRESH-DYNAMIC RAM

DRAWING TIME WINDOW

F

0

DRAWING DURING ACTIVE DISPLAY TIME
AND RETRACE BLANKING

1

DRAWING ONLY DURING RETRACE BLANKING

Figure 15. Mode Control Bits

SYNC: lOt 0 lOt 0 t 1 t 1 t 1 1 D L
THE DISPLAY IS ENABLEO BY
A 1, AND BLANKED BY A O.

: ~~~L7.~~~~
~oo"---+-"'--,=-,-L--I

MODE CONTROL BITS.
SEE FIGURE 15.

ACTIVE DISPLAY WORDS PER LINE -2. MUST
BE EVEN NUMBER WITH BIT 0 = o.

P3 L-J..-".L....J......J........L..J.,,-I-..l

L-.L....L.......J........L...LVS...J,c..H..lr-- VERTICAL SYNC WIDTH, HIGH BITS
' - - - - - - - HORIZONTAL FRONT PORCH WIDTH -1.
HORIZONTAL BACK PORCH WIDTH -1.
VERTICAL FRONT PORCH WIDTH
ACTIVE DISPLAY LINES PER VIDEO FIELD,
LOW BITS

L-L-L-.......L....J........LA.J~L...H.Jf.--

~~T~V:r~~SPLAY

LINES PER VIDEO FIELD,

' - - - - - - - VERTICAL BACK PORCH WIDTH

Figure 16. Sync Command
19

210655-002

intJ

82720

SYNC Format Specify Command

must be 4 or more display cycles wide. This is equivalent to eight or more clock cycles. This gives the slave
GDCs time to initialize their internal video sync
generators to the proper point in the video field to
match the incoming vertical sync pulse (VSYNC).
This resetting of the generator occurs just after the
end of the incoming VSYNC pulse, during the HFP
interval. Enough time during HFP is required to allow
the slave GOC to complete the operation before the
start of the HSYNC interval.

This command loads parameters into the sync
generator. The various parameter fields and bits are
identical to those at the RESET command. The GOC
is not reset nor does it enter idle mode.

Vertical Sync Mode Command
When using two or more GOCs to contribute to one
image, one GOC is defined as the master sync
generator, and the others operate as its slaves. The
VSYNC pins of all GOCs are connected together.

Once the GOCs are initialized and set up as Master
and Slaves, they must be given time to synchronize. It
is a good idea to watch the VSYNC status bit of the
Master GOC and wait until after one or more VSYNC
pulses have been generated before the display process is started. The START command will begin the
active display of data and will end the video
synchronization process, so be sure there has been
at least one VSYNC pulse generated for the Slaves to
synchronize to.

Slave Mode Operation
A few considerations should be observed when
synchronizing two or more GOCs to generate overlayed video via the VSYNC INPUT/OUTPUT pin. As
mentioned above, the Horizontal Front Porch (HFP)

VSYNC:

I

0 , 1 , 1 , 0

I

1

I

1

I

1

I I
M

L-

O-ACCEPT EXTERNAL VERTICAL
SYNC-SLAVE MODE
l-GENERATE & OUTPUT VERTICAL
SYNC-MASTER MODE

Figure 17. Vertical Sync Mode Command

CCHAR:

I

0, 1

I

0 , 0

I

1 ,0 ,1

!

1

I

Figure 18. Cursor & Character Characteristics Command

20

210655-002

82720

Cursor and Character Characteristics
Command

Parameter RAM Load Command
From the starting address, SA, any number of bytes
may be loaded into the parameter RAM at incrementing addresses, up to location 15. The sequence of
parameter bytes is terminated by the next command
byte entered into the FIFO. The parameter RAM
stores 16 bytes of information in predefined locations which differ for graphics and character modes.
See the parameter RAM discussion for bit
assignments.

In graphics mode, LR should be set to O. For interlaced
displays in graphics mode, BR should be set to 3. The
blink rate parameter controls both the cursor and attribute blink rates. The cursor blink-an-time = blink-oft-time
= 2 x BR (video frames). The attribute blink rate is
always '/2 the cursor rate but with a 3f4 on-V4 oft duty
cycle.

DISPLAY CONTROL COMMANDS
Zoom Factors Specify Command

Pitch Specification Command

Zoom magnification factors of 1 through 16 are available using codes 0 through 15, respectively.

This value is used during drawing by the drawing
processor to find the word directly above or below
the current word, and during display to find the start
of the next line.

Cursor Position Specify Command

The Pitch parameter (width of display memory) is set
by two different commands. In addition to the PITCH
command, the RESET (or SYNC) command also sets
the pitch value. The "active words per line" parameter, which specifies the width of the raster-scan display, also sets the Pitch of the display memory. In
situations in which these two values are equal there
is no need to execute a PITCH command.

In character mode, the third parameter byte is not
needed. The cursor is displayed for the word time in
which the display scan address (DAD) equals the
cursor address. In graphics mode, the cursor word
address specifies the word containing the starting
pixel of the drawing; the dot address value specifies
the pixel within that word.

START DISPLAY & END IDLE MODE
START:

lOt

1

!

1

!

0

!

1

0

r

r

1

!

1

I

DISPLAY BLANKING CONTROL

eCTRl:

I0 , 0 , 0

I

0

I

1

I

1 , 0

IOEI
L - ~~~ ~',S:~~YB'CA~~~~L~~
AO.

ZOOM FACTORS SPECIFY

ZOOM:

I0

I

1

r

0

!

0

r

0 , 1

a

r

1

I

0I1

J

I

CURSOR PDSITION SPECIFY
CURS:

P1
P2
P3

0

I

1

I

0 I 0

I

'

,

0

I

EAD

L

EAD

1_ EXECUTE WORD ADDRESS, MIDDLE BYTE

~~'~'~'~~

EXECUTE WORD ADDRESS, LOW BYTE

;:=':~'::::::::=:~.
dAD

:l:

T

I

1 1E~D 1_
0

I

0

L-

(GRAPHICS MODE ONLY)
WORD ADDRESS, TOP BITS
DOT ADDRESS WITHIN THE WORD

Figure 19. Display Control Commands
21

210655-002

intel'

82720

PRAM:

P,

I0

!

1 ,1 , 1

I

SA

l. . ___

..

I~~======:.
I

1 - 1 TO 16 BYTES TO BE LOADED
INTO THE PARAMETER RAM
STARTING AT THE RAM ADDRESS
SPECIFIED BY SA

,.

Po

STARTING ADDRESS IN
PARAMETER RAM

Figure 20. Parameter RAM Load Command

PITCH:

I

0

!

1

I

0 , 0

I

0

!

1

!

1

1

1

P
I

I
!-NUMBER OF WORD ADDRESSES
IN DISPLAY MEMORY IN THE
HORIZONTAL DIRECTION

Figure 21. Pitch Specification Command

WRITE DATA INTO DISPLAY MEMORY

WDAT:~I_o~ ~l~I
__

__
TYir_E__

~o~I Mi?_D~
__

tL _ _ _ _ RMW MEMORY CYCLE LOGICAL
OPERATION:

_
REPLACE WITH PATTERN
_
COMPLEMENT
RESET TO ZERO
_SETT01
' - - - - - - - - - DATA TRANSFER TYPE
1
1
o

P1

l__
_

o ~.o-------O.
l'
1

WORD, LOW THEN HIGH BYTE
LOW BYTE OF THE WORD
HIGH BYTE OF THE WORD
INVALID

W"L0_RD_L"L0_R~BY_T_E..I..
____,..,j~""- - - WORD LOW DATA BYTE OR
I
I
I
I
_
SINGLE BYTE DATA VALUE

.L.--I.__

P21L__.L.-.....__.L-W_°"Lt_D_"...I __. . I . . - - ' ' ' - , . . , j I - ~g~DD1~:~fr~R ONLY:
Figure 22. Write Data Command

DRAWING CONTROL COMMANDS

In graphics bit-map situations, only the LSB of the
WDAT parameter bytes is used as the pattern in the
RMWoperations. Therefore it is possible to have only
an all ones or all zeros pattern. In coded character
applications all the bits of the WDAT parameters are
used to establish the drawing pattern.

Write Data Command
Upon receiving a set of parameters (two bytes for a
word transfer, one for a byte transfer), one RMW
cycle into Video Memory is done at the address
pointed to by the cursor EAD. The EAD pointer is
advanced to the next word, according to the previously specified direction. More parameters can then
be accepted.

The WDAT command operates differently from the
other commands which initiate RMW cycle activity. It
requires parameters to set up the Pattern register
while the other commands use the stored values in
the parameter RAM. Like all of these commands, the

For byte writes, the unspecified byte is treated as all
zeros during the RMW memory cycle.
22

210655-002

82720

WDAT command must be preceded by a FIGS command and its parameters. Only the first three parameters need be given following the FIGS opcode, to set
up the type of drawing, the DIR direction, and the DC
value. The DC parameter + 1 will be the number of
RMW cycles done by the GDC with the first set of WDAT
parameters. Additional sets of WDAT parameters will
see a DC value of 0 which will cause only one RMW
cycle to be executed.

:=:::::::::::::::::::::::=:
P21
PI I

I1L

I_LOW SIGNIFICANCE BYTE

I1H

I_HIGH SIGNIFICANCE BYTE

Figure 23. Mask Register Load Command

FIGS:

I0

I

1

0 0

I

I

1

I

I

P11sLI R I A IGcl L I

1

I

0 0
I

I
J~ DRAWING DIRECTION BASE

IDIR I

t
f 1

1

:1 ~~

:

0

::10;01 ;

L

D:LD~H
:L

~M
D~M

:

:

FIGURE TYPE SELECT BITS:
LINE (VECTOR)
GRAPHICS CHARACTER
ARC/CIRCLE
RECTANGLE
SLANTED GRAPHICS CHARACTER
DC DRAWING PARAMETER

GRAPHICS DRAWING FLAG FOR USE IN
MIXED GRAPHICS AND CHARACTER MODE

~ 0 DRAWING PARAMETER
:

;
~ 02 .DRAWING PARAMETER

::10: 0i

: D:L

::t;oi

; D:1LDiM;

:

:
~Dl

DRAWING PARAMETER

;
~ OM DRAWING PARAMETER

pl1:o;ol D:LD~M;

P1°1

;

;

VALID FIGURE TYPE SELECT COMBINATIONS
J;!,.

R

A

GC

1,

0 0 0 0 0
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 1 0 0 0
0 0 1 0
1

OPERATION
CHARACTER DISPLAY MODE
DRAWING, INDIVIDUAL DOT
DRAWING, DMA, WDAT, AND
RDAT
STRAIGHT LINE DRAWING
GRAPHICS CHARACTER
DRAWING AND AREA FILLING
WITH GRAPHICS CHARACTER
PATTERN

[""~"" J
COMBINATIONS
ASSURE
CORRECT DRAWING
OPERATION

ARC AND CIRCLE DRAWING
RECTANGLE DRAWING

SLANTED GRAPHICS
CHARACTER DRAWING AND
SLANTED AREA FILLING

Figure 24. Figure Drawing Parameters Specify Command
23

210655-002

intJ

82720

FIGO:lo,l ,1,0,1,1 ,0,01

pixel pointed to by the cursor, EAD, and the dot
address, dAD.

Figure 25. Figure Draw Start Command

Graphics Char. Draw and Area Fill Start
Command

GCHRD:

Based on parameters loaded with the FIGS command, this command initiates the drawing of the
graphics character or area filling pattern stored in
Parameter RAM. Drawing begins at the address in
display memory pointed to by the EAD and dAD
values.

I0 , 1 , 1 , 0 , 1 , 0 , 0 , 0 I

Figure 26. Graphics Character Draw
and Area Filling Start Command

DATA READ COMMANDS
Mask Register Load Command

Read Data Command

This command sets the value of the 16-bit Mask register of the figure drawing processor. The Mask register controls which bits can be modified in the display
memory during a read-modify-write cycle.

Using the DIR and DC parameters of the FIGS command to establish direction and transfer count,
multiple RMW cycles can be executed without
specification of the cursor address after the initial
load (DC = number of words or bytes).

The Mask register is loaded both by the MASK command and the third parameter byte of the CURS
command. The MASK command accepts two parameter bytes to load a 16-bit value into the MASK
register. All 16 bits can be individually one or zero,
under program control. The CURS command on the
other hand, puts a "1 of 16" pattern into the Mask
register based on the value of the Dot Address value,
dAD. If normal single-pixel-at-a-time graphics figure
drawing is desired, there is no need to do a MASK command at all since the CURS command will set up
the proper pattern to address the proper pixels as
drawing progresses. For coded character DMA, and
screen setting and clearing operations using the
WDAT command, the MASK command should be
used after the CURS command if its third parameter
byte has been output. The Mask register should be set
to all ones for any "word-at-a-time" operation.

As this instruction begins to execute, the FIFO buffer
direction is reversed so that the data read from display memory can pass to the microprocessor. Any
commands or parameters in the FIFO at this time will
be lost. A command byte sent to the GDC will immediately reverse the buffer direction back to write
mode, and all RDAT information not yet read from the
FIFO will be lost. MOD should be set to 00.

Cursor Address Read Command
The Execute Address, EAD, points to the display
memory word containing the pixel to be addressed.
The Dot Address, dAD, within the word is represented
as a 1-of-16 code.

Figure Draw Start Command

Light Pen Address Read Command

On execution of this instruction, the GDC loads the
parameters from the parameter RAM into the drawing processor and starts the drawing process at the

The light pen address, LAD, corresponds to the display word address, DAD, at which the light pen input
signal is detected and deglitched.

RDAT:ll,O,lITYPElol M9D I

J:::-o
1
1
o

DATA TRANSFER TYPE

0 _
WORD, LOW THEN HIGH BYTE
0 _
LOW BYTE OF THE WORD ONLY
1 _
HIGH BYTE OF THE WORD ONLY
l-INVALID

Figure 27. Read Data from Display Memory Command
24

210655-002

82720

11,1

,1

,0,0,0,0,01

P'gA7 1

I

I EI\D11

P2QA'l

I

I EApM I

CURD:

LPRD" ' , , , 0 , 0 , 0 , 0 , 0 , 0

P3

i

X, X I X I X ,X IX

I

IA7,

IABIL EXECUTE ADDRESS (EADI. MIDDLE BYTE

iE~D!dL

t

!

U~PL,

,AO

1_

LIGHT PEN ADDRESS, LOW BYTE

EXECUTE ADDRESS (EADI. HIGH BITS

~IA='5:1==':;=LA:,o=M:,~=,A=B~J.- LIGHT PEN ADDRESS, MIDDLE BYTE

DDT ADDRESS (dADI. LOW BYTE

I
x

OOT ADDRESS (dAD), HIGH BYTE

x

I

THE FOLLOWING BYTES ARE RETURNED BY THE Gee:

,Aol_ EXECUTE ADDRESS (EADI. LOW BYTE

XI X I X I

x IX IX

I

LAPH I'-LIGHT PEN ADDRESS, HIGH BITS

= Undefined

= Undefined

Figure 28. Cursor Address Read Command

Figure 29. Light Pen Address Read Command

DMA READ REQUEST
DMAR:

I1

0

1

ITYPE I 1 I MOD I
-Lf------

DATA TRANSFER TYPE:

o 0~.1------ WORD, LOW THEN HIGH BYTE
0~.1------

LOW BYTE OF THE WORD

1 ~'1------ HIGH BYTE OF THE WORD
1 ~.1------ INVALID

DMA WRITE REQUEST
DMAW:

I

0I 0

I

1

IT~PE I I I
~
1

M?D

RMW MEMORY LOGICAL OPERATION:

0 _ _ REPLACE WITH PATTERN
1 _ _ COMPLEMENT
0 _ RESET TO ZERO
1 _ _ SET TO ONE

f.-------

DATA TRANSFER TYPE:

-~

o ~.1------ WORD, LOW THEN HIGH BYTE

0...1------ LOW BYTE OF THE WORD
1 ~.4----- HIGH BYTE OF THE WORD
1 ~.1------INVALID

Figure 30. DMA Control Commands

25

210655-002

82720

ABSOLUTE MAXIMUM RATINGS*

'COMMENT: Exposing the device to stresses above
those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be
operated under conditions outside the limits described in
the operational sections of this specification. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

Ambient Temperature Under Bias .......... O"C to 70"C
Storage Temperature .................. -65"C to 150"C
Voltage on any Pin with Respect
to Ground ............................ -0.5V to + 7V
Power Dissipation ............................ 1.5 Watt

DC CHARACTERISTICS
TA = O"C to 70" C; Vee = 5V ± 10%; GND =OV

Symbol

Limits

Parameter

Unit

Min.

Max.

Input Low Voltage

-0.5

0.8

V

VIH

Input High Voltage

2.0

Vee + 0.5

V

VOL

Output Low Voltage

0.45

V

VOH

Output High Voltage

IOZ

Output Leakage Current

III

Input Leakage Current

Vel

Clock Input Low Voltage

-0.5

VeH

Clock Input High Voltage

3.5

lee

Vee Supply Current

Vil

2.4

V

Conditions

IOl = 2.2 mA
IOH = -400 JkA

±10

JkA

VSS+0.45 <;;VI <;;
Vee

±10

JkA

VSS <;;VI <;;Vee

0.6

V

VCC + 0.5

V

270

mA

Typical = 150 mA

CAPACITANCE
TA = 25"C; Vee = GND = OV

Symbol

Limits

Parameter
Min.

Max.

Unit

Conditions

CIN

Input Capacitance

10

pF

CIO

1/0 Capacitance

20

pF

fc = 1 MHz

COUT

Output Capacitance

20

pF

V = 0

Co

Clock Input Capacitance

20

pF

26

210655-002

82720

A.C. CHARACTERISTICS

(TA = o·c to + 70·C, Vss = OV, vcc = + 5V ± 10%)

DATA BUS READ CYCLE
82720
Symbol

82720·1

82720·2

Parameter

Units
Min.

Max.

Min.

Max.

Min.

Max.

TAR

Ao setup to RD I

0

0

0

ns

TRA

Ao hold after RD I

0

0

0

ns

TRR

AD Pulse Width

TRO+20

TRO +20

TRo+20

TRO

AD I to Data Out Delay

TOF

AD I to Data Float Delay

TRV

AD Aecovery Time

120
120

0
4 TCY

80
100

0
4 TCY

0

Test
Conditions

ns
70

ns

90

ns

CL=50pF

ns

4 TCY

DATA BUS WRITE CYCLE
82720
Symbol

82720·1

82720·2

Parameter

Units
Min.

Max.

Min,

Max.

Min.

Max.

TWA

Ao
Ao

Tww

WA Pulse Width

120

100

90

ns

Tow

Data Setup to WA I

100

80

70

ns

TAW

Setup to WA I

0

0

0

ns

Hold after WR I

0

0

10

ns

Two

Data Hold after WA I

TRV

WR Recovery Time

Test
Conditions

0

0

10

ns

4Tev

4 TCY

4 TCY

ns

DISPLAY MEMORY TIMING
82720
Symbol

82720·1

82720·2

Parameter

Units

Test
Conditions

Min.

Max,

Min.

Max.

Min,

Max.

TCA

AddressiData Delay from 2XWCLK I

30

160

30

130

30

110

ns

CL=50pF

TAC

AddressiData Float Time

30

160

30

130

30

110

ns

CL=50pF

Toc

Data Setup to 2XWCLKI

0

Tco

Data Hold Time

TIE

2XWCLKI to DBIN

30

120

30

90

30

80

ns

CL=50pF

TCAH

2XWCLKI to ALE I

30

125

30

100

30

90

ns

CL=50pF

TCAL

2XWCLKI to ALE I

30

100

30

"BO

30

70

ns"

CL=50pF

TAL

ALE Low Time

Tev+ 3O

TAH

ALE High Time

TCH-20

Tco

Video Signal Delay from 2XWCLK I

0

TIE -20

TIE-20

ns

TCy+30

TCH-20

27

ns

TIE-20

Tev+ 3O

150

ns

0

TCH -20
120

ns
100

ns

210655-002

82720

A.C. CHARACTERISTICS (Continued)
OTHER TIMING

82720
Symbol

82720·1

82720·2

Parameter

Units
Min.

Tpc

LPEN or VSYNC Input Setup to 2XWCLK t

Tpp

LPEN or VSYNC Input Pulse Width

Max.

Min.

Max.

Min.

Test
Conditions

Max.

30

20

15

ns

TCY

TCY

TCY

ns

CLOCK TIMING

82720
Symbol

82720·1

82720·2

Parameter

Units
Min.

Max.

Min.

Max.

Min.

Max.

TCY

Clock Period

250

2000

200

2000

180

2000

TCH

Clock High Time

105

TCl

Clock Low Time

105

TR

Rise Time

20

20

20

ns

TF

Fall Time

20

20

20

ns

80

70

80

Test
Conditions

ns
ns

70

ns

DMA TIMING

82720
Symbol

82720·1

82720·2

Parameter

Units
Min.

Max.

Min.

Max.

Min.

Max.

TACC

DACK Setup to RD I or WR I

0

0

0

ns

TCAC

DACK Hold from RD t or WR t

0

0

0

ns

TRRI

RD Pulse Width

TRD1

RD I to Data Out Delay

T RD1 +20

TKO

2XWCLKt to DREO Delay

TROAK

DREO Setup to DACK I

TAKRO

DACKI to DREOI Delay

TAKH

DACK High Time

TAK1

DACK Cycle Time, Word Mode

4 TCY

TAK2

DACK Cycle Time, Byte Mode

5 TCY

TRD1 +20

ns

TRD1 +20

1.5 TCY

1.5 TCY

1.5 TCY

+120

+80

+70

150
0

120
0

TCY + 150

28

100
0

TCy+120
TCY

TCY

Test
Conditions

ns

CL=50pF

ns

CL=50pF

ns
TCY + 100

ns

TCY

ns

4 TCY

4 TCY

ns

5 TCY

5 TCY

ns

CL=50pF

2106S5-002

inter

82720

A.C. TEST CONDITIONS
Input Pulse Levels (except 2XWCLK)
................. . . .................................. 0.45V to
Input Pulse Levels (2XWCLK) . . .
. ....... .
. O.3V to
Timing Measurement Reference Levels (except 2XWCLK) ...... .
. .O.8V to
Timing Measurement Reference Levels (2XWCLK)
........ .
.O.6V to

2.4V
3.9V
2.0V
3.5V

WAVEFORMS
DATA BUS TIMING
READ CYCLE

Ao

-_-~~~---

=>it-_-

- - -_--f--I------_-_-_-T-RR-_-_-_
TA R

~TDF~

~~~~~~~ - - - - - - - 1 < > c=g~~~~~~~-D-A-TA-V-A-L-ID---.+..) - - - - - + - - - - ~--------TRv----------1

WRITE CYCLE

DATA BUS
DATA
(INPUT) _ _ _.;;;M;.:AY,-C=.:H",A",N:.::G:::.E_ _ _J

DATA
1<_ _ _
DA_I_A_VA_L_ID_-_----r ' -_ _ _...:::M:.;:AY:..;C::H"'A::.:N.::G::.E_ _ __

29

210655-002

inter

82720

WAVEFORMS (Continued)

DISPLAY MEMORY TIMING
READ/MODIFY/WRITE CYCLE
Sl

S3

S2

S4

2xWCLK

ADO-15

VALID
OUTPUT DATA

TCA

~

TCA

VALID

A16,A17

TCAL"""~TAL---.V-

~
TeAH

ALE

.-

..-

--------------------------------~

TAH .......

30

210655-002

82720

WAVEFORMS (Continued)
DISPLAY MEMORY TIMING (Continued)
READ CYCLE

Sl

S2

2xWCLK

ADo-AD15

--+---<1

A16,A17

ALE

TCO

HSYNC

~~l~~

~----------~_

LCo~3

g~~IMAGE

-----------

AT,BLANKlCLC

OTHER TIMING
2xWCLK

LPEN

1
TPC

VSYNC ---------~

\

__TPP-I'-------

CLOCK TIMING

2xWCLK

31

210655-002

intel'

82720

WAVEFORMS (Continued)
DMATIMING
READ
2XWCLK

TK0lDREQ

_ _ _ _J

rTROAK

I~'~----~KRO------'~---------

i-----TRR1-----.I ,,..--+------+--

D~7 -------------~---------_-__________+-~O~""~"'~,~,,!!:,.,~,I-

-t-_------------------------------H~O,~",~"'~,,~,,,~.,D,~--Q:E~:::>-~O~"'~'")J,,!!!
..!:,

A16'17:=4:X::::::::::::::::::::::::::::::::::::::~::::::::::::::::::::::::::::::::::::::~::::::::

Blank:

::j~~------------------------------------f-,'-------------------------------------ri::::::=

34

210655-002

inter

82720

WAVEFORMS (Continued)
VIDEO SYNC SIGNALS TIMING

I

1H

2xWCLD:

~ ____ ~ __

HBLANK:

J

HSYNC:

I
.../\.JV ___ J\..r\.. __ f\..

---"'L-__ ../

------------------~/

\~-------------------

-J'-_.J'--_,'--_---"~____''__~:=:.:x:=::x:::::
LCO-4:

x=.::::x:
:\
1

::::x

______

ADO-15:

r-~=J- __ ~=
=~_-:_-_-:_~===~~ _-_-_-_~~==~~_-_- ------_~ -- J
~--~--J()(XJ(---------------------------JCX:K)(--J()(:
=t= ::::Jt:::::.:::::x:::=:::::::::::::.::: ::::::::::.:::. =x:::::::::.:=x::

Row:

~----------------------------------------------------v-

-I,'I

'to-

_________ 1

~~~~~~---------

:::::::::::::JC:

Row:
VBLANK:

"--- - - -----~/r-----------------------------

I

~--------~

/

VSYNC:

!--------------1V (FI.,d)--------------1

INTERLACED VIDEO TIMING
HBLANK:
VBLANK:

JL __ JL1L __ JUL __ JLJL __ .JL __ JL __ JLJL __ .JLJL_
I

L

I

1

1

:
VSYNC:
(Interlace)

1 I

,

I

__ - - - . r - - - - I - - - - - - - , - - - - - L - __ ...r---,--,------,-,--I

I

II

,,
I

I

I

I

L-

I I - - - - - - - O d d F i e l d - - - : - - - - - !_ _ _ _ _ Even Fietd _ _ _--,-___

I

, I

,

VSYNC:
(No Interlace)

I

____________~I

I

Ir-----~~

35

210655-002

inter

82720

WAVEFORMS (Continued)
VIDEO HORIZONTAL SYNC GENERATOR PARAMETERS
~-----------------------lH------------------------~
I

HBLANK:

------i

~

__________________________

I
I
~r--

I
I

nL--_____.;-__________________---l._ _

HSYNC' _ _....;I'--_.....
I
I
I
I

---1

:t
I
I

~HBP--t--AW-----l

VIDEO VERTICAL SYNC GENERATOR PARAMETERS
1----------_ _ _ _ _ _ 1V ___________________

~

VBLANK' __--;_ _ _-,

I

L--

I

I

I
I

I
I

I

I

I

I
I

I
I

VSYNC, ---1"""l:-__--'-_____________~-____!n
I
I

I

I
I

I
I

I

I
iVFPrl
I
I--VBP~+-------AL.----------_I-l
tBP---j
I

i

-----1 VS
CURSOR-IMAGE BIT FLAG

36

210655-002

82720

VIDEO FIELD TIMING -----I!~----_;;H;';SY:;:;N;;_C;i;:0U:;:tP:::ut:__-----'f1__
BLANK Output
Vertical SYNC Lines

,,!-- --

Vertical Back Porch Blanked Lines

Horizontal

SYNCPulse
Horinzontal

Front Porch-

VSVNC Output

Blanking

-

Horizontal
Back Porch
Blanking

Active
Display
Lines

Vertical Front Porch Blanked Lines

DRAWING INTERVALS

~ Drawing Interval
~ Additional Drawing Interval When
~ in Flash Mode

m
wa

Dynamic RAM Refresh if Enabled, Otherwise
Additional Drawing Interval

DMA REQUEST INTERVALS
r-------------------~

DMA Request Interval
Additional DMA Request Intervals
When in Flash Mode

37

210655-002

DOMESTIC SALES OFFICES
AlABAMA

IWNOIS

Intel Corp.
303 Williams Avenue, S.W.
Suite 1422
Huntsville 35801

NEW MEXICO

TEXAS

Intel Corp,
1120 Juan Tabo N.E.
Albuquerque 87112
Tel: (505) 292·8086

Intel Corp."
12300 Ford Road
Suile 380
Dallas 75234
Tel: (214) 241·8087
TWX: 91O·86()"5617

Tel: (205) 533·9353

NEW YORK

910-651·5881

ARIZONA
Inlel Corp.
11225 N. 28th Drive

Suite 2140
Phoenix 85029
Tel: (602) 869-4980

CAUFORNIA
1010 Hurley Way
Suite 300
Sacramento 95825
Tel: (916) 929-4078
Intel Corp.

?:frrtunity

Intel Corp.
9100 Purdue Road
Suile 400
IndianapoUs 46268
Tel: (317) 875·0623

Intel Corp,
SO Washington Street
Poughkeepsie 12601
Tel: (914) 473·2303
TWX: 510-248-0060

IOWA

Intel Corp.

~~r~

Intel Corp,"
300 Vanderbilt Motor Parkway
Hauppauge 11788
Tel: (516) 231·3300
TWX: 510·227-6236

INDIANA

Road

San Diego 92111

(714) 268-3563
Intel Corp.2000 East 4th Street
Suite 100
Santa Ana 92705

~:(7Jj~5~~~~2

Intel Corp.1350 Shorebird Way
M!. Vtew 94043

Tel: (415) 968-8086
TWX: 910-339-9279

910-338-0255

Intel Corp.

fJ30An~~~nd~~~in8rive

N.E.

Cedar Rapids 52402
Tel: (319) 393·5510

IWISAS

~:{7Jr6.2~~~7W~,o

Intel Corp.
8400 W. 110th Street
Suite 170
Overland Park 66210
Tel: (913) 642-8080

TWX: 710·541·0554

LOUISIANA
Industrial Digital Systems Corp.
2332 Severn Avenue
Suile 202
Metairie 70001
Tel: (504) 831-8492

MARYLAND

Inlet Corp,5530 Corbin Avenue

Suite 120
Tarzana 91356
Tel: (213) 708-0333
TWX: 910-495-2045

COLORADO
Intel Corp.
4445 Northpark Drive

Suite 100

~,~r(:83) S~:;"~~2~0907
Intel Corp.650 S. Cherry Street
Suite 720
Denver 80222

Intel Corp.
1620 Elton Road
Silver Spring 20903
Tel: (301) 431·1200
IIASSACII~

Intel Corp,"
27 Industrial Avenue
Chelmsford 01824
Tel: (617) 256·1800
TWX: 710-343-6333

CONNECTICUT

EMC Corp.
385 Elliot Street
Newlon 02164
Tel: (617) 244-4740
TWX: 922531

Intel Corp.

IIICHIGAN

Tel: (303) 321-8086
TWX: 910-931-2289

36 Padanaram Road

~~(2b3)oe:J~-8366

TWX: 710-456-1199

EMC Corp.
393 Center Street

fe~:'i(~~Jf ~~
FLORIDA

~5'8h ~.\I;:

62nd Street
Suite 104
I
FI. Lauderdale 33309
Tel: (305) 771-0600
TWX: 510-956-9407

Intel Corp."
26500 Northwestern Hwy.
Suite 401
Southfield 48075
Tel: (313) 353-0920
TWX: 810·244·4915

MINNESOTA
Intel Corp.
3500 W. SOth Street
Suite 360
Bloomington 55431

~: (6Jf6.5~~:2~~~2

IIISSOURI

~~ ~~aldand

Intel Corp.
4203 Earth City Expressway

~: (3~,5J.s~~~9~~~3

Tel:

Suite 205
Maitland 32751

GEORGIA
Intel Corp.
3300 Holcombe Bridge Road
Suite 225
Norcross 30092
Tel: (404) 449-0541

Intel Corp,"
211 White Spruce Boulevard
Rochester 14623

~~

g'

(314~

63045
291·1990

HEW JERSEY
Intel Corp."
Raritan Plaza III
Raritan Center
Edison OSS37

~~~ua~~~ings

Road
Syracuse 13206
Tel: (315) 463·S592

~3~uap~tI~rd
Victor Road
Victor 14564
Tel: (716) 924-9101
TWX: 510-254·8542
NORTH CAROLINA
Intel Corp.
2306 W. Meadowview Road
Suite 206
Greensboro 27407
Tel: (919) 294·1541

OHIO
Inlel Corp."
6500 Poe Avenue
Dayton 45414

~:(5J~~~~~~~0

~~~gr~Ee:inard

Intel Corp,"
7322 S.W. Freeway
Suite 1490
Houston 77074
Tel: (713) 98S-8086
TWX: 910·881·2490
Industrial Digital Systems Corp.
5925 Sovereign
Suite 101
Houston 77036
Tel: (713)988·9421
Intel Corp.
313 E. Anderson Lane
Suite 314
Austin 78752
Tel: (512) 454·3628
UTAH
Intel
268
San
Tel:

Corp.
West 400 South
Lake City 84101
(801) 533·8086

VIRGINIA
Intel Corp,
1603 Santa Rosa Road
Suite 109
Richmond 2328S
Tel: (804) 282·5668

WAStftNGTON
Intel Corp.
110 110th Avenue N.E.
Sutte 510
Bellevue 98004
Tel: (206) 453·S086
TWX: 910-443·3002

WISCONSIN
Inlel Corp,
450 N. Sunnyslope Road
Suite 130
Brookfield 53005
Tel: (414) 7S4·9060

Bldg, No. 300
·28001 Chagrin Boulevard
Cleveland 44122
Tel: (216) 464·6915
TWX: 810·427·9298

CANADA

OKUHOIIA

ONTARIO

Intel Corp.
4157 S. Harvard Avenue
Suite 123
Tulsa 74135
Tel: (91S) 749-8688

Intel Semiconductor of Canada, lid.
39 Hwy. 7, Bell Mews
Nepean K2H SAl
Tel: (613) 829·9714
TELEX: 053·4115

OREGON

50 Galaxy Boulevard

Intel Corp,
10700 S.W. Beaverton
Hillsdale Highway
Suite 22
Beaverton 97005

~:(58r~~~~6
PENNSYLVANIA
Intel
510
Fort
Tel:

Corp,"
Pennsylvania Avenue
Washington 19034
(215) 641·1000
TWX: 510-661·2077
Intel Corp."
201 Penn Center Boulevard
Suile 301W
Pittsburgh 15235
Tel: ~412) 823·4970

Inlel Semiconductor of Canada, lid,
Suite 12
Rexdale M9W 4Y5
Tel: (416) 675·2105
TELEX: 06983574
Intel Semiconductor of canada, Ltd,
201 Consumers Road
Suite 200
Willowdale M2J 4GB
Tel: (416) 494·6831
TELEX: 4946831

QUEBEC
Inlel Semiconductor of canada, lid.
3860 Cote Vertu Road
Suite 210
51. Laurenl H4R lV4
Tel: (514) 334-0560
TELEX: 05·824172

Q.E.D. Electronics
300 N. York Road
Hatboro 19040
Tel: (215) 674·9600

~:(2~~6-4~~~~~~0
"Field Applicallon Location

inter
EUROPEAN SALES OFFICES
BELGIUM
Inlel Corporation SA

~~c d~cn140uhn

a Papier 51

FRANCE (ConI'd)

ISRAEL

SWEDEN

Intel Corporallon, S ARL
Immeuble OOC
4 Quai des ftrolts

Intel Semiconductor Ltd."
PO. Box 1659
Haifa
Tel. 4/524
TELEX: 46511

Intel Sweden AB."
Box 20092
Archlmedesvagen 5
S-16120 Bromma
Tel: (08) 98 53 85
TELEX: 12261

69005 Lyon
Tel: (7) 842 40 89

Bolte 1
B.1160 Brussels
Tel: (02)661 07 11
TELEX: 28414

TELEX: 305153
WEST GERMANY

D£NllARK

l?K_~~~eJ c~~n~ngdenFIEa~t

Intel Semiconductor GmbH"
Seldlslrasse 27
0-8000 Muenchen 2
Tel: (89) 53891

Tel: (01) 18 20 00

TELEX: 05-23177 INTl 0

Inlel Denmark A/S'

TELEX: 19567

Inlel Semiconductor GmbH"
Mamzer SlraS$c 75
D-6200 Wiesbaden 1
Tel: (6121) 70 08 74
TELEX. 04186163 INTW 0

FINLAND
Intel Finland OY
Hamcenlle 103

SF - 00550 Helsinki 55
Tel: 0/716 955
TELEX: 123 332

FIlAIIC<

Inlel Corporahon. S AR L."
5 Place de la Balance
Sllic 223

~(2~OI~u~1 ~~f
TELEX: 270475

ITALY
Intel Corporation !talla Spa"
Mllanoflon, Palazzo E
20094 Assago (Milano)
Tel: (02) 824 00 06
TELEX: 315183 INTMIL

SWITZERLAND

Intel Semiconductor A.G."
Forchstrasse 95
CH 8032 lunch
Tel: (01) 554502'
TELEX. 57989 ICH CH

NETHERLANDS
Intel Semiconductor Nederland B V."
Alexanderpoorl BUilding
Marlen Meesweg: 93
3068 Rotterdam
Tel. (IO) 21 23 77
TELEX: 22283

Intel Semiconductor GmbH
Brueckstrasse 61
7012 Fellbach
West Germany
Tel: (711) 58 00 82
TELEX: 7254826 INTS 0

NORWAY

Intel Semiconductor GmbH"
Hohenzollern Strasse 5"
3000 Hannover 1
Tel: (511) 34 40 81
TELEX' 923625 INTH 0

f~l:ett(~) 742 420
TELEX: 18018

Intel Norway A/S
PO. Box 92
Hvamvelen 4
N·2013

UNITED KINGDOM

Intel Corporation (U.K) Ltd.·
5 Hospital Street
Nantwlch, Cheshire CW5 5RE
Tel. (0270) 626 560
TELEX: 36620
Intel Corporation (U K.) Ltd·
Pipers Way
Swtndon, Wiltshire SN3 IRJ
Tel: (0793) 488 388
TELEX. 444447 INT SWN

Intel Semiconductor GmbH
Ober-Ratherstrasse 2
0-4000 Dusseldorf 30
Tel' (211) 6510 54
TELEX: 08-58977 INTL 0
·Fleld Application Location

EUROPEAN DISTRIBUTORS/REPRESENTATIVES
AUSTRIA

FRANCE (Conl'd)

ITALY (Conl'd)

SWEDEN (Cont'd)

Bacher Elektronlsche Geraele GmbH
Rotemuehlgasse 26
A 1120 Vienna
Tel: (222) 83 63 96
TELEX 11532 BASAT A

Tekelec Alrtronic
Cite des Bruyeres
Rue Carle Vernet
F-9231O Sevres
Tel: (OIl 534 75 35
TELEX 204552

Inlesi
Milanflori Pal E!5
20090 Assago
Milano
Tel: (02) 82470
TELEX: 311351

Nordlsk Electronlk AB
Box 27301
Sandhamnsgatan 71
S-10254 Slockholm
Tel' (8) 635 040
TELEX. 10547

WEST GERMANY

NETHERLANDS

SWITZERLAND

ElectrOniC 2000 Vertriebs A.G
Neumarl<.ter Strasse 75
[)"8oo0 Munich 80
Tel: (89) 43 40 61
TELEX 522561 EIEC D

KOning & Hartman
Koperwerf 30
P.O Box 43220
2544 EN's Gravenhage
Tel 31 (70) 210.101
TELEX: 31528

Industrade AG
Gemsenstrasse 2
Postcheck 80 - 21190
CH-8021 Zunch
Tel. (Ol) 363 23 20
TELEX: 56788 INDEL CH

NORWAY

UNITED KINGDOM

Nordisk Elektronic (Norge) A!S
PostoRice Box 122
Smedsvlngen 4
1364 Hvalstad
Tel: (2) 786 210
TELEX: 77546

~~~~7L1d.

BELGIUM

lnelco Belgium SA
Ave. des Croix de Guerre 94
B1120 Brussels
Tel: (02) 216 01 60
TELEX: 25441
DENMARK

MultiKomponent A/S
Fabnksparken 31
DK-26oo Gloskrup
Tel: (02) 45 66 45
TX: 33355
Scandinavian SemIConductor
Supply A/S

g~~2208a~eo~~hagen
Tet: (01) 83 50 90
TELEX: 19037

FINLAND
Oy Flntronic AB
Melkonkalu 24 A
SF-0021O
Helsinki 21
Tet: (0) 692 60 22
TELEX: 124 224 Ftron SF

..woe.
Genenm
Z I. de Courtaboeuf
Avenue de la Baltique
91943 Les Ulis Cedex-B.P.88
Tet: (6) 007 78 79
TELEX: F691700
Jermyn S.A
rue Jules Ferry 35
93170 Bagnolet
Tel: (I) 859 04 04
TELEX: 21810 F
Metrologle
La Tour d' Asnieres
I, Avenue Laurent Cely
92606-Asnieres
Tel: (1) 791 44 44
TELEX: 611-448

Jermyn GmbH
Postlach 1180
Schulstrasse 48
0-6277 Bad Camberg
Tel: (06434) 231
TELEX' 484426 JERM D
Celdis Enatechnlk Systems GmbH
Gutenbergstrasse 4
2359 Henstedt-Ulzburg I
Tel: (04193) 4026
TELEX: 2160260

PORTUGAL

Proelectron Vertnebs GmbH
Max Planck Strasse 1-3
6072 Orelelch bei Frankfurl
Tel (6103) 33564
TELEX' 417983

Oltram
Componentes E Electronica LOA
Av. Miguel Bombarda, 133
P1000 Llsboa
Tel: (19) 545 313
TELEX: 14182 Brieks-P

IRELAND

SPAIN

Micro Marketing
Glenageary ORice Park
Glenageary
Co. Dublin
Tel: (1) 85 62 68
TELEX: 31584

Interface S.A
Ronda San Pedro 22,3
Barcelona 10
Tel: (3) 301 78 51
TWX 51508

tsRAEL
Eastronlcs Ltd
11 Rozanls Street
P.O. Box 39300
Tel AVIV 61390
Tel: (3) 47 51 51
TELEX: 33638

ITALY
Eledra 3S S.PA
Vlale ElveZla, 18
I 20154 Milano
Tel: (2) 34 97 51
TELEX: 332332

lIT SESA
Miguel Angel 23-3
Madfld 10
Tel. (I) 419 54 00
TELEX: 27707
SWED£N

AB Gosta Backstrom
Box 12009
Aistroemergalan 22
S-10221 Siockholm 12
Tel: (8) 541 080
TELEX: 10135

London Road
Earley, Reading
Berkshire
Tel' (0734) 61031
TELEX. 848215
Comway Microsystems Ltd
Market Street
UK-Bracknell, Berkshlfe
Tei. 44 (344) 55333
TELEX 847201
Jermyn Industfles
Vestry Eslate
Sevenoaks. Kent
Tel: (0732) 450144
TELEX: 95142
M.E.DL
East Lane Road
North Wembley
Middlesex HA9 7PP
Tei. (01) 904 93 07
TELEX: 28817
Rapid Recall, Ltd
Rapid House/Denmark St

~~~s,W~~~~~

HP11 2ER
Tel (0494) 26 271
TELEX: 837931
YUGOSLAVIA

H A. Microelectronics Enterprises
PO. Box 5604
San Jose, California 95150
Tel: 408/978-8000
TELEX: 278-559

INTEL CORPORATION, 3065 Bowers Ave., Santa Clara, CA 95051; Tel. (408) 987-8080.
INTEL INTERNATIONAL, Brussels, Belgium; Tel. (02) 661 07 11.
INTEL JAPAN k.k., Ibaraki-ken; Tel. 029747-8511.

PRINTED IN USA T·1435/0683/15K/8ofors CG



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