83313200C_BR3D4_Disk_Storage_Unit_Reference_Jul75 83313200C BR3D4 Disk Storage Unit Reference Jul75
83313200C_BR3D4_Disk_Storage_Unit_Reference_Jul75 83313200C_BR3D4_Disk_Storage_Unit_Reference_Jul75
User Manual: 83313200C_BR3D4_Disk_Storage_Unit_Reference_Jul75
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,I
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COR PO R AT, I 0 ~
CONTROL DAT A®
BR3D4 DISk STORAGE UNIT
REFERENCE MANUAL
REVISION RECORD
REVISION
A
DESCRIPTION
Manual released.
Includes
pneT; nppr; neT
<
.t.
nrn<=>r
PE35604.
(2-28-75)
B
(4 -30-75)
C
(7-15-75)
Manual revised to include technical and editorial corrections affecting pages: vi, 3-36. 3-39, 3-44.
6-20. (paQ'es 6-6 thru 6-23 rearranQ'ed)
Manual revised to incorporate Enqineerinq Chanqe Order PE39280B and technical
corrections affecting pages: 1-1, 3-11, 3-13, 3-18, 3-29, 3-35, 3-36, 3-54.
Publication No.
83313200
© 1975
by Control Data Corporation
Printed in the United States of America
ii
Address comments concerning this
manual to:
Control Data Corporation
Technical Publications Dept.
7801 Computer Avenue
Minneapolis MN 55435
or use Comment Sheet in the back of
this manual.
83313200 C
PREFACE
This manual has been prepared for customer
engineers and other technical personnel .
directly involved with maintaining the Disk
Storage· Unit (drive).
Reference information is provided in six
sections in this manual. Section numbers
and a brief description of their contents
are listed below.
Section 1 - General Description. Describes
equipment functions, specifications, and equipment number
identification
Section 2 - Operation. Describes and
illustrates the location and
use of all controls and indicators, power on sequencing, and
disk pack installation and
removal.
Section 5 - Description of integrated circuits used in the drive.
Includes pin assignments along
with truth tables and/or typical
waveforms.
Section 6 - Description of discrete components and their functions.
For
ease of using the logic diagrams,
transistors and their associated
components are frequently condensed into an equivalent logic
symbol. This section, arranged
in alphabetical order of the
circuit type designator (AAAZZZ), explains these functions
and illustrates the actual discrete elements.
Manuals applicable to the BR3D4 Disk Storage
Units are as follows:
Title
Section 3 - Theory of Operation. Describes
basic logic and mechanical
functions.
Publication No.
83313100
Maintenance Manual
Section 4 - Introduction to logic symbology
and card constructions.
83313200
Reference Manual
83313300
Parts Data
83313200
A
iii/iv
"
CONTENTS
1. GENERAL DESCRIPTION
Introduction
Assembly Locations
Top Cover Assembly
Deck Assembly
AC Power Supply
Logic Chassis
Equipment Identification
2. OPERATION
Controls and Indicators
Operating Instructions
Power Application
Disk Pack Handling
Disk Pack Installation
Disk Pack Removal
.r-~
~~
CI
3. THEORY OF OPERATION
Introduction
Assemblies
Power Supply
AC/DC Distribution
Overtemperature Monitoring
Power On Sequence
Emergency Retract and Data
Protection
Loss of AC Power
Control Interlock Opening
Loss of Speed
Loss of DC Power
Power Off Sequence
Logic Chassis
Deck Assembly
Drive Motor Assembly
Hysteresis Brake Assembly
Spindle Assembly
Actuator
Transducers
First Seek Interlock Assembly
Blow~r System
Disk Pack
Logic Functions
Basic Interface Description
Unit Selection
Seek Operations
83313200
A
1-1
1-1
1-4
1-4
1-4
1-:-4
1-4
2-1
·2-4
2-4
2-4
2-4
2-5
3-1
3-1
3-1
3-1
3-6
3-6
3-7
3-7
3-7
3-9
3-9
3-10
3-11
3-11
3-11
3-11
3-13
3-13
3-17
3-17
3-17
3-19
3-19
3-19
3-19
3-19
Servo Circuit
Basic Seek Operation
Short Seeks
Track Servo Circuit
Basic Description
Circuit Description
End of Travel Detection
Cylinder Pulse Generation
First Seek
Direct (Forward/Reverse) Seek
I/O Sequencing
positioner Motion
Return to Zero Seek (RTZS)
Machine Clock Circuit
Clock Generation
Index Detection Circuit
Index Error Detection
Sector Circuit
Sense Operations
Device Check
Maintenance Monitor
Diagnostics
Static Diagnostics
Dynamic Diagnostics
Diagnostic Entry
Basic Read/Write Principles
Introduction
Writing Data
Reading Data
Track Format
Principles of MFM Recording
Read/Write Operations
Introduction
Head Selection
Write Data processing
Read Data processing
4. KEY TO LOGIC
General
Logic Chassis
Logic Cards
Physical Description
Pin Assignments
Test Points
3-32
3-36
3-38
3-39
3-39
3-39
3-45
3-46
3-46
3-51
3-51
3-55
3-56
3-59
3-59
3-60
3-60
3-60
3-64
3-64
3-64
3-64
3-64
3-66
3-66
3-66
3-66
3-66
3-66
3-71
3-71
3-72
3-72
3-72
3-74
3-74
4-1
4-1
4-1
4-1
4-1
4-1
v
Logic Symbology
4-3
Element
4-3
307
5-33
4-3
321S
5-34
4-3
339
5-35
502
5-36
Inhibit
4-3
4-4
519
5-37
Miscellaneous
4-4
5-40
5-41
Input/Output State Indicators
Dynamic Indicator
Signal Line Indicators
, Non-Standard Levels
Function Symbols
4-4
916
926
Input/Output Designators
4-5
986
Common Control Block
Wired Functions
4-5
4-6
Integrated Circuits
4-6
Operational Amplifiers
4-6
vi
DISCRETE COMPONENT CIRCUITS
Circuit
FAE
6-1
FAP
6-2
FAG
6-3
FBH
6-4
6-5
4-6
Basic Circuit Elements
4-6
Input Stage
4-6
Second stage
4-8
GJK
GKF
Basic Circuit Functions
4-8
HAQ
6-7
Schmitt Trigger Circuits
4-8
HBA
4-13
HBB
6-8
6-9
INTEGRATED CIRCUITS
Element
'~.-,
5-39
Introduction
Discrete Component Circuits
5.
6.
~,
(
6-6
HCA
6-10
HCB
6-11
140
5-1
HCE
6-12
141
5-2
HCF
6-13
143
5-3
HCK
6-14
144
5-4
HCL
6-15
6-16
145
5-6
HCP
146
5-7
HCQ
6-17
147
5-8
HCU
6-18
148
5-9
HJM
6-19
149H
5-10
ICD
6-20
158
5-11
JAG
6-21
161
5-14
JAL
6-22
6-23
162
5-15
JAM
164
5-17
LCI
6-24
166
5-19
MAF/MAH
6-25
172H
5-21
QDE
6-27
173H
5-22
QEH
6-28
175H
5-23
QEJ
6-29
176
5-24
QEK
6-30
182
5-25
QEL
6-31
191
5-27
QEM
6-32
193
5-29
QGD
6-33
195
5-30
RCB
6-34
200
5-31
SAA
6-35
202S
5-32
SCD
6-36
83313200
B
(',
('
r-")
"'--,
Circuit
SCE
TFT
UBG
UBVHI
VHJ
VHK
Circuit
6-37
VHM
6-44
6-38
VHQ
VHR
VKM
VKN
XAH
6-45
6-39
6-40
6-41
6-42
6-46
6-47
6-48
6-49
6-43
FIGURES
1-1
2-1
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23
3-24
3-25
3-26
3-27
Assembly Locations
Controls and Indicators
Simplified Logic Symbology
Power Distribution
Power Sequencing
Power Interlocks
Power Off Timing
Power Off Sequence
Deck Assembly
Spindle Assembly
Actuator Assembly Elements
Head Loading
Head/Arm Assembly Motion
Speed Detection
Velocity Detection
Blower System
Logic Block Diagram
Servo Circuit Simplified
Schematic
Servo Circuit Simplified
Signals
Track Servo Disk Layout
Track Servo Circuit
Simplified Schematic
Track Servo and Dibits Detect
Circuit Simplified Signals
Dibits Detect
Cylinder Pulses Generation
First Seek Flow Chart
First Seek Timing Diagram
Direct Seek Flow Chart
Direct Seek Timing Diagram
RTZS Flow Chart
83313200
A
1-3
3-28
2-1
3-29
3-2
3-30
3-3
3-31
3-4
3-5
3-8
3-10
3-12
3-13
3-32
3-33
3-34
3-35
3-36
3-14
3-37
3-15
3-38
3-16
3-17
3-18
3-18
3-20
3-35
3-39
3-40
3-41
3-42
3-43
3-44
3-45
3-37
4-1
3-40
4-2
3-41
4-3
4-4
3-42
3-45
3-47
3-48
3-50
3-52
4-5
4-6
4-7
4-8
4-9
4-10
RTZS Timing Diagram.
Machine Clock Circuit
Index Detection Circuit
Index Error Detection Circuit
and Timing
Sector Circuit
Device Logic Check
Static Diagnostic Entry FlCM Chart
Static Diagnostic Flow Chart
Writing Data
Reading Data
MFM Recording
Read/Write Chain Block Diagram
Head Select and Write Circuits
Write Chain Timing
AGC Amplified Stage
(Simplified Logic)
Level Detection Circuit
Time Constant Control Circuit
Data Latch Circuit
Wire Wrap Board Assembly
Logic Card Detail
Inversion Conventions
Common Control Block
Wired Functions
Integrated Circuits
Simplified Op Amp Schematic
Op Amp Circuit Functions
Op Amp Used as a Schmitt
Trigger
Discrete Component Circuit
3-58
3-59
3-61
3-62
3-63
3-65
3-67
3-68
3-70
3-70
3-71
3-72
3-73
3-75
3-76
3-77
3-78
3-80
4-2
4-3
4-4
4-5
4-6
4-7
4-7
4-9
4-12
4-13
3-54
3-57
vii
TABLES
1-1
Drive Specifications
1-1
3-2
Tag Decode and Control Bus Functions
3-23
2-1
Controls and Indicators
3-3
Servo Circuit Functions
3-32
3-1
I/O Lines
2-2
3...;21
3-4
Track Servo Circuit Functions
3-43
r--'
(
'--
c
viii
83313200
A
SECTION 1
GENERAL DESCRIPTION
c'
(':
........ --"
c
(
'-.
INTRODUCTION
ASSEMBLY LOCATIONS
The CONTROL DATA® BR3D4 Disk Storage Unit is
a high speed, random access, disk storage
device.
Data is recorded on removable disk
packs. Equipment specifications are listed
in Table 1-1.
Figure 1-1 illustrates the major drive assemblies. Detailed information on the construction and function of these assemblies
is provided in Section 3 of this manual.
....)
.../
TABLE 1-1.
Characteristics
DRIVE SPECIFICATIONS
Conditions
Specifications
PHYSICAL SPECIFICATIONS
Size
Height
39.5 in.
width
22 in.
Depth
44.5 in.
Weight
(100 cm)
(56 cm)
(176 cm)
660 lbs (300 kg)
Temperature
Operating
60 0 F (15. SOC) to 90 0 F (32 0 C)
Gradient
l2 0 F (6.6 0 C) per hour
Non-Operating
-30 0 F (-34 0 C) to +150 0 F (66 0 C)
Relative
Humidity
(no condensation)
Operating
20% to 80%
Non-Operating
5% to 95%
Altitude
Operating
-1000 ft (-305 m) to +10,000 ft (3.05 km)
mean sea level
Non-Operating
-1000 ft to +35,000 ft (10.7 km)
POWER SPECIFICATIONS (Typical Values)
Refer to Installation Manual for additional power information.
Definitions:
Standby State:
Accessing State:
AC Power Input
C
positioner continually random
seeking.
BR3D4A
208v (±10%), 60 (±0.6) Hz, 3-phase
BR3D4B
220v (±10%), 50 (±0.5) Hz, 3-phase
Phasing (60 Hz)
Two phases supplied from a three-phase Wy.e
source are used per 60 Hz drive. Three-phase
power is available at AlTBl by power cable.
During installation, two phases are connected
to internal power supply. Phases are normally
rotated from drive-to-drive so that each group
of three drives present a balanced three-phase
load. Motors are single-phase connected
phase-to-phase.
Phasing (50 Hz)
83313200
dc power on, spindle motor off.
I
I
One phase is used per 50 Hz drive. Threephase power available at AlTBl by power cable.
Power is connected phase-to-neutral with
phases rotated from drive-to-drive to present
a balanced three-phase load.
I
1-1
TABLE 1-1.
DRIVE SPECIFICATIONS (CONT'D)
Specifications
Characteristics
Conditions
Current
(208v at 60 Hz)
Standby
2 amp/phase
Starting
34 amp/phase for 7 seconds
Accessing
8 amp/phase
Power True
(208v at 60 Hz)
Power Factor
(208v at 60 Hz)
Heat Dissipation
(208v at 60 Hz)
Standby
0.4 kilowatt
Accessing
1.2 kilowatt
Standby
0.9
Accessing
0.7
Standby
1400 BTU/hr (353 Kg-cal/hr)
Accessing
4200 BTU/hr (1060
Kg~cal/hr)
DATA RECORDING SPECIFICATIONS
Disk Pack
Packs/Drive
1
Recording Surfaces/
Disk Pack
19
Usable Tracks/
Recording Surface
823 (808 plus 15 spares)
Tracks/Cylinder
19
Tracks/Inch
384
Tracks Spacing
0.0026 inch (nominal)
Rotational Speed
3600 (±2%) rpm (16.7 ms/rev)
Recommended Pack
CDC 9883-61
Access Mechanism
Voice Coil driven by servo loop
823 Tracks
55 ms (maximum)
1 Track
10 ms (maximum)
Average
30 ms
;
Seek Timing
Latency Time
Recording
Heads
Average
8.33 ms (@3600 rpm)
Maximum
17 ms (@3528 rpm)
Mode
Modified Frequency Modulation .(MFM)
Bit Density
4040 bpi (inner track nominal)
Rate
6.45 MHz (nominal)
Quantity
19 record:lng
1 servo (positioning)
Read/Write Width
0.0021 in.
Controller/Drive
Quantity
2 per channel
Interface Cables
Maximum Length
50 ft (15m)
1-2
(nominal)
Connectors
4 per drive
Pin Assignments
Refer to Installation Manual
Signal Functions
Refer to Section 3 of this manual
83313200
A
ACTUATOR ASSEMBLY
o
READ/WRITE CHASSIS
SHROUD
SPINDLE
ASSEMBLY
BLOWER
SUPPLY
eW34A
Figure 1-1.
83313200
A
Assembly Locations
1-3
TOP COVER ASSEMBLY
The top cover assembly protects the drive
assemblies during customer operations.
The pack cover is opened by means of a latch
under the cover. An electrical switch
senses the cover is opened, and disables
spindle motor power.
DECK ASSEMBLY
The deck assembly has the following major
subassemblies:
C
o
o
o
o
A spindle assembly to mount the disk
pack. Its associated drive motor
runs continuously whenever a pack is
installed, the pack cover is closed,
the START switch is on, and sequence power (either from the controller or with the LOCAL/REMOTE
switch on the power supply in the
LOCAL position) are ava.ilable.
An actuator assembly that mounts the
read/write heads for processing data.
The actuator contains a voice coil
positioner controlled by a closedloop, continuous-feedback servo
system.
A shroud to surround the disk pack.
The shroud: protects the pack, aids
in directing air from the blower to
the pack; and prevents the operator
from damaging the read/write heads
with the pack.
A read/write chassis to mount logic
cards that contain logic directly
affecting head selection and operation.
A first seek interlock assembly to
provide a heads load command delay.
AC POWER SUPPLY
The ac
quired
erated
supply
bly.
power supply provides ac power reby the drive. The ac voltages genare distributed to the dc power
located in the logic chassis assem-
The line filter filters the ac power input
to the power supply.
LOGIC CHASSIS
The logic chassis serves as the mounting
point for the main complement of the logic
cards and dc power supply. The chassis is
1-4
hinge-mounted for easy access to the cards
(which plug in at the inner side of the
chassis) or to the backpanel terminals (at
the outer side). The backpanel terminals
provide ready access to all signals entering
and leaving each card. In addition, the
cards have test points for monitoring
critical signals within the cards.
The logic chassis also contains a test point
panel that provides a location for status
monitoring of the dc voltages generated by
the dc power panel.
Located in the lower half of the logic
chassis is the dc power panel. The dc power
panel provides dc power required by the
drive. It also contains relays and solid
state logic used for power sequencing.
EQUIPMENT IDENTIFICATION
An equipment number is assigned to each
drive to identify its configuration. This
provides a systematic method of identifying,
accounting, and controlling changes that
affect drive logic and mechanical components.
The equipment configuration is identified by
a nameplate attached to the frame at the
back of the drive. The nameplate is visible
with the logic chassis open. The Equipment
Identification Number will be similar to
the following:
BR3D4
I
Equipment
Identifier
02
A
T
Lseries
Code
Type
Identifier
The Equipment Identifier indicates the basic
function of the unit. This number will be
BR3D4 on all units for which this series of
manuals have been prepared.
The Type Identifier indicates a non-interchangeable difference in equipments that
affects the interface. The term "Mod'" is
sometimes used interchangeably with "Type
Identifier". The following identifiers have
been assigned:
Engineering
Number
Channel
Configuration
Volts/
Frequency
BR3D4A
BR3D4B
Single
Single
208/60 Hz
220/50 Hz
83313200
A
The Series Code changes with each noninterchangeable change within the equipment.
Drives with different series codes are fully
interchangeable at the system level; hoWever, not all of their electrical or mechanical components may be interchangeable.
Series ~odes are changed by Engineering
Change arder (ECa) only at the factory.
ather changes are accomplished by Field
Change arder (FCa). These changes may be
installed either at the factory or by field
personnel. Fca changes are indicated by an
entry on the Fca Log that accompanies each
machine. It is important that this log be
kept current by the person installing each
Fca.
83313200
A
Unless otherwise specified, all theory,
procedures, and diagrams in these manuals
apply to all units. Exceptions are noted
where applicable.
Manuals accompanying unit shipments from
the manufacturer match the configuration of
those units. Subsequent manual changes are
controlled by the Revision Record sheet
behind the title page of every manual. This
sheet identifies the Series Code and Fca
effectivity of manual changes. If maintenance will be performed using a manual other
than the manual supplied with each drive,
verify that the manual and drive configurations match.
1-5/1-6
f
"._-
SECTION
2
OPERATION
c~
C~'
CONTROLS AND INDICATORS
The drive contains several panels and indicators. Figure 2-1 locates the panels and
indicators on a cabinet. Table 2-1 describes
the various panel controls and indicators.
OPERATOR CONTROL PANEL
D
TEST POINT PANEL
'1
0
0
+20Y
0
'2
HOY
DRIVE
MOTOR
~
(f)
DC POWER SUPPLY
(f)
+20Y
LOCAL
REMOTE
....
EB EB
UNIT
POWER
.10
-10
.10
-10
8Y20
~~)
Figure
83313200
-,"
A
a-I.
Controls and Indicators
2-1
TABLE 2-1.
CONTROLS AND INDICATORS
(...........'
\
Control or Indicator
I
Function
OPERATO~
START switch/indicator
PANEL
Switch energizes (when pressed to light) spindle drive
motor and begins the First Seek sequence provided the
following conditions are met:
1.
2.
3.
4.
Disk pack is in place and canister removed.
Pack cover is closed.
Circuit breakers are on.
Sequence power available either from control
unit (if power supply panel LOCAL/REMOTE switch
is set to REMOTE) or from power supply (if power
supply LOCAL/REMOTE switch is set to LOCAL).
Lights when switch is on and conditions 2 and 3 are met.
This allows operator to know which units will sequence
on when control unit sequence power becomes available.
Switch causes a power off sequence when pressed while
the indicator is lighted.
Physical unit Identification indicator
The lens of this indicator may be either blank or lettered A through H to physically identify the unit.
Indicator lights when read/write heads are loaded, a
Logical Address Plug is installed arrl a Seek Incomplete status
is not piesent. Half of indicator extinguishes when unit goes active.
MAINTENANCE indicator
Lights when related drive has experienced one of the
following conditions:
1.
2.
SELECT LOCK switch/
indicator
c
Either ±lOv circuit breakers on power supply
panel set to OFF.
ON LINE/OFF LINE switch on CE Tester panel set
to OFF LINE.
Lights when one or more of the following unwanted conditions occur:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Read and Write are selected at the same time.
More than one head is selected.
Voltage fault -Low voltage (±Sv, ±20v, or -16v) .
If -16v is low, heads retract.
No servo tracks - Loss of servo track for 200 ms
or more. Heads retract.
Write is selected without an On Cylinder signal.
Write gate is on but no write current (current
fault) •
Write gate is on during Index (write overrun) .
Write current present without a Write Gate
(current fault).
Write gate is on but no data transitions for 900
nsec (no write data or open coil).
Write gate is on with offset active.
c
2-2
83313200
A
TABLE 2-1.
CONTROLS AND INDICATORS (CONT'D)
Control or Indicator
Function
WRITE DISABLE switch/
indicator
Switch inhibits (when pressed to light) write gate, preventing drive from writi~g on pack.
LOGIC ADDRESS PLUG (LAP)
receptacle
A keyed LAP, when installed in this receptacle, assigns
a logical address of 0 through 7 or Service to the drive.
LOGIC CHASSIS TEST POINT PANEL
+5, -5, +20, -20, and
GND test jacks
Provide a point at which dc voltages in logic chassis
can be measured (do not use as a voltage source).
CH I DISABLE/ENABLE
switch
Enables/disables channel I transmitters and receivers.
CH II DISABLE/ENABLE
switch
Not used
AC POWER SUPPLY
(-."
Elapsed Time Meter
Indicates cumulative hours that logic dc power is on.
DRIVE MOTOR circuit
breaker
Controls application of ac voltage to spindle drive
motor.
+20Y Fuses
Protects 20 volt power supply transformer used to derive +20Y sequence and lamp voltages.
~\
DC POWER SUPPLY
+20Y indicator
Lights to indicate presence of +20Y voltage used by
lamps and power up sequence circuit.
LOCAL/REMOTE switch
Allows power up sequence to be controlled by either the
control unit (when set to REMOTE) or by +20Y-vdc from
power supply (when set to LOCAL).
±46, ±20, and flO volt
circuit breakers
Control application of related dc voltages throughout
drive.
MAIN BREAKER BOX
UNIT POWER circuit
breaker
Controls application of main ac power.
o
83313200
A
2-3
OPERATING INSTRUCTIONS
POWER APPLICATION
The following procedure prepares the drive
to go on-line.
1.
Install a disk pack (refer to Disk
Pack Installation).
2.
Set main breaker box UNIT POWER circuit to ON. Blower motor will begin
to operate.
3.
Open cabinet logic chassis gate and
position DC power supply switches
as follows:
a.
b.
LOCAL/REMOTE switch to REMOTE.
Power up sequence is then under
system control. If maintenance
is to be performed, set switch
to LOCAL.
Set all circuit breakers to ON.
4.
The power supply +20Y indicator
lights.
5.
Close cabinet logic chassis gate.
6.
Press operator panel START switch/
indicator. The switch/indicator
lights.
7.
When control unit sequence power
becomes available, or if in LOCAL
mode, the First Seek operation
begins.
8.
The First Seek operation is complete when the heads are positioned
at track 00. Operator panel Physical unit indicator lights when the
First Seek operation has been completed and a LAP has been installed.
The unit is now ready to receive a
command.
9.
To stop spindle motor, press operator
panel START switch. 'lb remJVe power to
drive, turn off UNIT POWER circuit
breaker.
2-4
d.
Determine cause of failure
(normally an open lead to voice
coil) .
To ensure maximum disk pack life and reliability, observe the following precautions:
1.
Store disk packs in a machine-room
atmosphere (GOoF to 90 o F, 10% to 80%
relative humidity).
2.
If a disk pack must be stored in a
different environment, allow two
hours for adjustment to the computer environment before use.
3.
Never store a disk pack in sunlight,
in a dirty environment, or on top of
another disk pack.
4.
Store the disk packs flat, not on
edge.
5.
Always be sure that both the top and
bottom plastic covers are on a disk
pack whenever it is not actually installed in a drive.
G.
When marking packs, use a pen or
felt-tip marker that does not produce a loose residue. Never use a
led pencil. Write on the label
before it is applied to the disk
pack.
DISK PACK INSTALLATION
Make certain that the disk pack to be installed has been properly maintained.
1.
Raise drive front cover.
2.
Lift the disk pack by the plastic
canister handle.
3.
Disengage the bottom dust cover from
the disk pack using the knob in the
center of the cover. Set the cover
aside to an uncontaminated storage
area.
CAUTION
If unit fails to power down when
START switch is pressed,the following procedure must be followed to
avoid personal injury.
Open top ~over from rear.
Disconnect yellow lead from
voice coil.
Manually retract heads.
DISK PACK HANDLING
I WARNING.
a.
b.
c.
Make certain the heads are fully
retracted.
4.
Place the disk pack onto the spindle.
83313200
A
NOTE
A spindle lock mechanism (ratchet
'brake) is actuated when the disk
pack canister cover is on the
spindle. A "click" may be heard as
the lock mechanism engages. The
mechanism holds the spindle stationary while loading or unloading a
disk pack.
5.
Twist the canister handle clockwise
until pack is locked in place.
6.
Lift the canister clear of the disk
pack and set it aside to an uncontaminated storage area.
7.
Close the front cover immediately to
prevent the entry of dust and the
contamination of the. disk surfaces.
DISK PACK REMOVAL
(~)
c··
1.
Press (to extinguish) the operator
panel START switch.
2.
Check that disk pack rotation has
stopped completely.
3.
Raise the front cover.
CAUTION
During maintenance procedures the
read/write heads are sometimes
manually positioned. Make certain
that the heads are fully retracted.
4.
Place the plastic canister over the
mounted disk pack so that the post
protruding from the center of the
disk pack is received into the
canister nandle.
5.
Twist the canister handle counterclockwise until the disk pack is
free of the spindle.
CAUTION
Avoid abusive contact between the
disk pack and the spindle assembly.
6.
Lift the canister and the disk pack
clear of the spindle.
7.
Close the front cover.
8.
Place the bottom dust cover in position on the disk pack and tighten
it.
9.
Store the disk pack in a clean
cabinet or on a clean shelf.
'I
83313200
A
2-5/2-6
...........
C~:
SECTION 3
THEORY OF OPERATION
,"-"
u
c
(-"j
"-
INTRODUCTION
3.
±9.7 vdc which, in turn, is regulated to ±S vdc at the logic chassis.
4.
±46 vdc for use by the voice coil
positioner.
S.
-16 vdc used to retract the carriage
under emergency conditions.
./
Theory of operation for the drive is orga~
nized into two parts. The first part
describes the major mechanical assemblies.
The second part describes the logical functions and the signals exchanged with the
controller.
Functional descriptions are frequently
accompanied by simplified logic diagrams.
These diagrams are useful both for instructional purposes and as an aid in troubleshooting. Figure 3-1 illustrates the logic
symbology used by the illustrations in this
manual. The diagrams have been simplified
to illustrate the principles of operation:
therfore, other elements may be omitted. The
logic diagrams in the Maintenance manual
should take precedence over the diagrams in
this section whenever there is a conflict
between the two types of diagrams.
The descriptions are limited to drive operations only. In addition, they explain
typical operations and do not list variations
or unusual conditions resulting from unique
system hardware or software environments.
Personnel using this manual should already
be familiar with principles of operation of
the computer system, the controller, programming considerations (including the correct sequencing of I/O commands and signals),
and track format (i.e., data records and
field organization).
ASSEMBLIES
Refer to Section 1 for major assembly locations.
POWER SUPPLY
Each drive cabinet has a self-contained
pm'ler supply accessible by swinging open the
logic chassis. The power supply is contained
in two locations. The ac portion of the
supply, consisting of transformers, rectifiers, triacs, and line filters, is mounted
in the lower rear of the drive cabinet. The
dc portion of the supply, consisting of
rectifiers and filters and the relays for
power sequencing, is mounted in the lower
portion of the logic chassis. Power supply
cooling is accomplished by room air for the
ac portion; for the dc portion, cooling air
is' blown over the chassis from a blower at
the front of the drive cabinet.
The power supply has the following onputs:
1.
+20Y for power sequencing control.
2.
±20 vdc used by the logic.
Power distribution and sequencing control
are illustrated in Figures 3-2 through 3-4.
AC/ DC Distri bution
Input power is made available to the power
supply via the closed contacts of the UNIT
POWER circuit breaker. With this breaker
closed, the blower motor operates. AC power
is available to the remainder of the circuit breakers.
.
The remainder of the'ac distribution occurs
when the input voltage is applied to transformer AlT3. An ac voltage of about 24
volts is picked off the secondary and
applied to the first seek interlock motor,
but application of the voltage to the motor
does not occur until the spindle motor is
started. Another T3 output is rectified to
+20Y volts, which is used as a control voltage within the power system.
With +20Y volts available, AlQl is enabled.
Solid state switches AlQl through AlQ4
effectively operate as relays.
The input applied to pin 1 of these devices
is transferred to output pin 2 only if pin 3
has +20 volts on it while pin 4 is grounded.
These enables are described in detail in the
Power Up Sequence discussion.
With AlQl enabled, ac is applied to transformers AlTl and T2. In the case of T2,
four distributative voltages developed
across the secondary windings are applied to
receifier/filter circuits. The four circuits (+9.7, -9.7, +20, and -20 vdc) are not
adjustable and incorporate no switching
device other than circuit breakers for circuit protection. Both polarities of the
9.7v circuit are voltage level regulated and
made adjustable to is vdc at the logic
chassis.
The voltages developed across AlTl are
applied to rectifier and filter circuits.
None of the voltages are adjustable. The
actuator power (±46 vdc) incorporates no
swi tching devices other than circuit'
breakers for protection. The emergency retract power (-16 vdc) uses retract relay KS
to connect or disconnect the emergency retract capacitor to the voice coil. This
function is explained further in the Emergency Retract discussion.
o
83313200
A
3-1
GENERAL INFORMATION
SIM'LIF1ED DIAGRAMS IN THIS MANUAL SHOW THE FUNCTIONAL FLOW OF SIGNALS
THROUGH THE DRIVE. THE DIAGRAMS HAVE BEEN SIMPLIFIED TO SEItyE 4S
A GUIDE IN TROUBLESHOOTING AND IN UNDERSTANDING DRIVE
Ol'EltATIONS. REFtR TO THE COMPLETE LOGIC DIAGRAMS FOR
ACTU~L
TEST POINTS AND SIGNAL LEVELS.
·ALL LOGIC " SHOWN ON POSITIVE LOGIC REPRESENTATIO ...
SIGNAL LEVELS ARE DISREGAIIDED. ALL SIGNALS ARE NAMED
WHEN THE 'UNCTION TO BE ACCOMPLISHED REQUIRES A
LOGICAL ',"EGA" DLE 51 OF ACTUAL SIGNAL VOLTAGE LEVEL.
r
~
SYMBOLS
~
-
HEAVY BAR INDICATES THAT REGISTER (OR OTHER LOGICAL 'UNCTION I
IS MOllE THAN ONE BIT. ONLY ONE BIT IS SHOW~ 'OR CLAIIITY.
REMAINING
BITS OPERATE IN A SlMILAII MANNER.
XX
ON
REG
CYLINOER~AULT
A
2
W"ITI
AS
' - - LOCATION
(I
"
LOGIC ELEMENTON LOGIC CHASSIS.
.!..
--t. . ".
"HT _
SIGNAL NAME fOR FUNCTIONAL
OLin
ACTUAL
..... AL VOLTAGIE LIVEL .
••• ,"'GA"
LOGIC
SYMBOLOGY
ACTUAL LOGIC
CONVERSION
~
IIMI'LI'IED SYMBOL
-D-
A~I
I..VUTU
i. A
=D--
C
A
=8I
. -
OR
A+I·C
=E}-
:=8-
C
A .. D
A·I·C
.~
o
E
n
:.
OR
A
n
i~'
=a:
"
CLEAR
DUAL A.. D lOR
U. I'+,C. D'aE
0'
FLIP-FLOP
OPERATION
WI"ID
,.,
"
OUTI'UTI ARE COMI'LEMENTAIIY UNLESS 10TH
INI'UTI "ECEIVE SIMULTANEOUS ENABLES. IF SO,
10TH OUTI'UTS ARE HIGH , . , . "
.I"
"
.II( "
.. INAILED 'TO CHA .. GE STATE I BY
DYNAMIC TOGGLE. JF CIRCLE IS SHOWN AT
TOIGLE, CI"CUIT IS ENABLED BY NEGATIVE-GOING
TOGGLE
I'RESETS AND I'ItECLEA"S
DO .. OT "EQUIRE TOGGLE TO CHANGE sraTE.
'·'·_·0·1.
(.
DUAL A.. D/OR
'A+II.'C + DlaE
\."
.I" nUTH
TABLE
WIUD n.p-nol'
CLEAR
."ED'LII'-'LOl'
ANDED sn IN!'UTS
OIlED CLEA" INPUTS
.I
"
0
0
0
0
I
I
0
0
I
I
0
0
I
I
IE'ORE TOGGLE
sn CLEAR
0
I
0
I
0
I
I
0
I
0
I
0
0
I
0
AFTER TOGGLE
CLEAR
SET
I
0
I
0
I
0
I
0
0
I
0
I
0
I
I
0
--L!L
I'RESET
B~.I.
ONLY
lOIS
A
.II(
Jllt[CLEA"ED
+ IV
!'Msn
SAME AS .II(, EXCEI'T THAT THE"E· IS NO
DATA INI'UT TO CL£AII .. DE. "SETS
I' D INI'UT IS ·1· WHEN TOGGLE
TO ., •• I' 0 INI'\IT IS ·0· AT
TOGGLE,
"
CLURS •
rrr·o·
I~.'
.•
FF
7"7
PftECLEARED BY ·1·
Figure 3-1.
3-2
Simplified Logic Symbology
83313200
A
C)
c=)
co
W
W
I-'
W
t\J
0
0
50HZ
220V
/ /
ROTATED
FROM DRIVE - TO - DRIVE
BE
A-B, A-C, OR
0-N
FOR 220 VAC
~~N~~CTpIOO:ER M~;
TO BALANCE
B-C.
POWER.
LOADS.
/
/
/
0A
0
>
PHASES
60HZ
208V
AITBI
()
UNIT .
POWER
~
/
08
I
0C
I
--;
N
OR IVE
MOTOR
0
c;-T-"
~
I
}
r-a
G)
TO
(SEE
OR,V'
MOTOR
SEQUENCING)
24 VAC
d\
A)
FIRST SEEK
INTERLOCK MOlOR
XMFR
HYSTERESIS
KI COIL
B)
BRAKE
SEE
SEQUENCING
1
SENSING BOARD
(SEE INTERLOCKS)
P. S.
K2
+20V
:"\.
"- -20V
XMFR
:,I
+
RECTIFIERS
AIT2
9.7V
"- - 9.7V
-
± 20
,
-..--r--..~
-
~
-10
......
ELAPSED
TIME
METER
I
I
20 Y
AITI
AIQI
lENABLE
±
TO
~}
TO
READ I WRITE LOGIC
LOGIC
LOGIC
5V REGULATORS
A2A5 AND A2A7
TO SERVO PREAMP
TO SENSI N G BOA RD A2A3
(SEE INTER LOCKS)
TO SERVO PREAMP
+ 46 V
RECTIFIERS
AND
1
DECK
:1
•
XMFR
ENABLE
r
r-----. TO
l
5 VDC
CB'S CLOSED
(FROM CONTROL INTERLOCKS)
-46 V
FILTERS
1
RECTIFIE R
-
+ 46
----46
"
1
-16 V
.
VOICE
TO
COIL POWER
AMP
A2AI
}
I
. (SEE INTERLOCKS)
EMERGENCY
-.,.
TO RETRACT CIRCUIT
(SEE INTE~LOCKS)
BY21
W
I
W
Figure 3-2.
Power Distribution
+20Y
LOGIC
CONTROL I NTERLOCK OK
MOTOR
__.~E~N_A~I~L~!________~KS ~__________________________________________________~_;:g~
~~G~R~D
NOT AIR FLOW FAULT
OR
IV
SENSING
DRIVE MO TO R
r---------,
.
I
I
!N AIL!
1(1
AICII
IDRIV! MTR I
AC IN
'FROM DIIIV!
MOTOR
STARTING
CAPACITOR
CII
I
I
GRD • ENABLE
CENTRIFUGAL
OPEN
CLOSE
!! 1000
RPM
RPM
I
I
TO -IIV SENSE
IMOTOR INTERLOCK
FOR
Kill
< 1000
I
L ________
..J
IS
SPEED
FROM SPEED
SENSING LOGIC
UP TO SPEED
KI
~--------------------------------------------------~------~
HYSTERESIS
~
~.,.------+ lOY
FIRST SEEK
INTERLOCK
MOTOR
K3
O}----r-[;----4=~n~
- ~----,~
24 V A C - - - - - - 4
~ TO~C
COMI'LETE
BY22
Figure 3-3.
3-4
Power Sequencing
83313200
A
C)
o
(\,
1\...... _I';.'
00
w
w
~
BREAKERS AUX
CONTACTS
INTERLOCK (SHOWN CLOSED)
w
~
o
o
OPEN
± 20
!t:oI
OFF
~
o
+ 46
PAC K
COVER
START
~
0
I' 'I
START
O.P.
+ 20 Y
+ 20Y
MAINTENANCE
SENSING
I
+ 9.7V
KI
AIQI
(ENABLE AC
INPUT TO DC
PWR SUPPLIES)
BOARD
(SEE SEQUENCING)
A2A3
-,
.1
CONTROL
J---- INTERLO CK
+20Y
r----....;..._.
I
LAM P
PWR
K2 COl L
+20Y
K3 COIL
KI
I
I
UNLOADED
AIQ I
..,)Y
~
....
LOADED = ENABLE
0--------
·1
HEADS
LOADED
SW
I
I
(ENABLE AC
INPUT TO DC
PWR SUPPLIES)
+20Y
< ':"16V. HDS LOADED
CR5
~
=
FLT
• -VOLT FAULT DETECT
r
I
RETRACT
r-----------------~rrK5l
I~
__ • _ _ _ _ _ J
(SPEED)
K2
I
I
I
.~
I
_...1
L
OPEN = ENABLE
MOTOR
CENTRI FUGAL
SW
(OPEN=ON)
-16V= ENABLE
K5
-1(5
EMERGENCy-G6
-16 V
+46 V
~:I~ { ::: :lpb;RI
-46V
-----I;
I
EME RGENCY
RETRACT
CAPACITO R
VOICE
COIL
"I'
eDIC
w
I
lJ1
Figure 3-4.
power Interlocks
to pick In (second drive) to
energize its Kl. In turn, Hold
In applies a holding current to
the second drive's Kl. This
process continues through the
remainder of the drives until
one is encountered with the
START switch on.
Overtemperature Monitoring
An air flow actuated switch is mounted in
the DC power supply, at the bottom of the
logic chassis. Loss of cooling air (excessive te,mperature) causes the switch to close.
This has the following effect:
1.
2.
The SELECT LOCK indicator on the
control panel lights.
b.
Air Flow Fault (Bit 5) on Bus In is
high if queried by Tag 12 BOBS
(Request Diagnostic Sense - Fault) .
A high temperature condition prevents a
power up sequence by inhibiting the energizing of K3 (Motor Start Relay). If the high
temperature (loss of cooling air condition)
is detected after power up and in a heads
loaded condition, unit operation is not
directly inhibited.
The logic temperature switch is kept open
by normal air flow from the cooling blower.
Low air flow allows the switch to close. A
low air flow condition detected before heads
are loaded, will de-energize Motor Relay K3.
2.
with the START switch on, a disk
pack installed, all interlocks
closed, and +20Y power available,
the START indicator is lighted. Now
that Kl is closed, the control
interlock signal provides the last
enable to energize motor relay K3.
3.
Closed contacts of K3 cause the
following:
a.
+20v enables solid state switch
AIQ2, AIQ3, and AIQ4. These
switches can now conduct ac
power to spindle motor.
b.
Because the motor is stopped,
centrifugal switch inside the
motor is closed. This provides
a ground enable to AIQ4 to connect the start winding and
capacitor to ac power. At 2,000
rpn the switch transfers to open,
disconnecting the start winding
and enabling run winding.
Power On Sequence
Power application to a unit is sequenced by
logic and by relays in the power supply.
Refer to Figure 3-3. Assume that all circuit breakers are closed. If so, the blower
motor is operating and the hysteresis brake
is energized by +20Y.
Power on may be controlled either by the
controller (remote) or locally for maintenance purposes (local). The Power On Sequence is as follows:
1.
+20Y is connected to relay Kl either
by placing the LOCAL/REMOTE switch
in the LOCAL position or, in the
REMOTE position, from the controller.
(Kl contacts are in the switch circuit so that, once the unit is
powered up, the LOCAL/REMOTE switch
can be switched without dropping
power, assuming ground is available
from the controller.) Other contacts of Kl enable solid state switch
AIQl to turn on the elapsed time
meter and to bring up dc power.
a.
If the START switch is not on in
the first unit, Sequence Power
Out in the second drive has a
continuous path through Sequence
Power In, Kl (first drive) START
switch, Pick out (first drive)
For the remainder of the sequence, assume that the first
drive has a disk pack installed,
that all interlocks are closed,
and that the START switch is on.
Power' cannot be sequenced to the
next drive until speed relay K2
closes.
c.
Apply GND to the frist seek
interlock motor. The first
seek interlock switch transfers
to the not complete (in progress) position.
d.
Removes power from hysteresis
brake.
4.
When the logic determines that the
spindle speed exceeds 3000 rpm, and
the first seek interlock delay is
complete, speed relay K2 energizes.
5.
With relay K2 closed:
a.
+20 vdc is distributed to the
read/write logic (Figure 3-2).
b.
Retract relay K5 is energized
(Figure 3-4).
(-\
c
3-6
83313200
A
6.
The transferring contacts of K5
cause the following:
a.
Disconnects the emergency re~
tract capacitor from the voice
coil while connecting it to the
-16v power supply to allow it
to charge to -16 volts.
b.
7.
8.
9.
Connects the power amplifier
A2Al to the positioner so that
the logic may control the positioner.
The first seek interlock switch
mechanically transfers to the complete position upon completion of
the interlock motor revolution (15
seconds for first seek delay). This
removes the remaining ground to the
interlock motor to disable it. It
also signals load heads to the logic.
Completion of the first seek delay
allows the start of the First Seek
(load heads) function. The logic
commands the positioner to move the
carriage forward. Refer to the
First Seek discussion for further
information.
When the heads move into the pack,
the heads loaded switch closes. This
causes the following:
a.
Provides a control signal to the
logic for further loading/unloading sequencing.
b.
Maintains a motor relay K3 enable
so that the motor continues to
operate if the control interlock opens. This prevents the
motor from being shut down until
the heads are unloaded.
Energizes relay K6. If any condition occurs where Retract
relay K5 opens, K6 continues to
apply -16v retract voltage to
the voice coil until the heads
unload.
c.
d.
Enables the -16v Sense circuit.
If the -16v power becomes insufficient (loss of power), the
Select Lock is set and Retract
relay K5 opens. Relay K5 connects the retract voltage to the
voice coil while removing logic
control of the voice coil.
Emergency Retract and Data Protection
Certain emergency conditions could occur
which require immediate disabling of the
write circuits and full retraction of the
heads. These conditions are:
1.
Loss of ac power, either site power
or'UNIT POWER circuit breaker.
2.
Opening of any of the control interlocks (Figure 3-4).
3.
Overheating of spindle motor. If
this occurs, the spindle motor
thermostat (Figure 3-3) opens: this
applies ac across the DRIVE MOTOR
circuit breaker coil to open the
contacts. Loss of speed (step 4)
occurs.
4.
Loss of spindle motor speed.
5.
Loss of any of the following ac
voltages: +20Y, ±9.7, or -16.
If any of these conditions occur, the read/
write logic is disabled and the heads are
unloaded. Refer to Figure 3-5 for timing
of these conditions.
Loss of AC Power
The following events occur upon catastrophic
loss of the ac power or opening of either 5v
circuit breaker.
1.
All dc power supplies drop their
outputs to zero and the logic is
disabled.
2.
All relays open.
3.
with K5 open, the normally-closed
contacts of K5 (Figure 3-4) provide
a path from the emergency retract
capacitor A2C2 to the voice coil.
This negative voltage pulls the carriage back to its retracted stop.
4.
with K2 open, +20 vdc is removed
from the read/write logic.
Control Interlock Opening
If the control interlock (Figure 3-4) opens,
the heads unload normally as explained in
Power Off Sequence. Pressing START to extinguish the indicator opens the interlock
o
83313200
A
3-7
w
I
CX)
rsvmH-;'w;';- 0;; - - - - - - - - -
I
II
~-,
I
~
I -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _I
__L
I __________ _
L
rLOCAl.
I
I
I
"SPiNDLEHOToRPOWERO"rFl
I
I
i
REMOVE AC
POWER INPUT TO
ALL DC POWER
SUPPLIES EXCEPT ..20Y
Z'
I
I
IL __________ ...JI
BLOWER
STAYS ON. IF
LOCAL POWER
OFF (Kl CLOSEI:$
ALL DC POWER
REMINING UP
ID 9A
CX)
w
w
......
W
N
o
o
Figure 3-5.
~
n
Power Off Sequence
/'-\
/
I
J
f/~
,
/
to initiate the normal unload heads sequence.
There are certain special emergency sensing
conditions:
1.
If either the +10 or -10 circuit
breaker opens, AlQl (Figure 3-2) is
disabled. The effect is the same
as if all ac power were lost. All
ac power input to the dc power supplies is opened except to +20Y.
2.
Opening a 20v circuit breaker generates an undervoltage condition to
set the Select Lock FF and light the
SELECT LOCK indicator.
3.
Opening of any other circuit breaker
or interlock breaks the control
interlock.
All of these conditions extinguish the START
indicator and unload the heads. Any undervoltage condition (±20v or ±5v) sets the
Select Lock FF, and raises bit 0 and bit 3
and/or 4 of Bus In if queried by a Request
Diagnostic Sense command bit 5.
If +9.7v is insufficient, the following
occur:
1.
Relays K2 and K3 are opened by the
+5v Sense circuit.
2.
With K2 open:
3.
4.
Loss of Speed
If the spindle motor speed drops below 2700
rpm, the following events occur:
a.
K5 opens to apply -16v retract
power.
b.
+20v power removed from read/
write chassis. With the heads
still loaded, the write circuit
gene"rates a Current Fault to set
the Select Lock FF.
With K3 open:
a.
The spindle motor is disabled.
b.
The hysteresis brake is energized.
In addition, the undervoltage condition will set the Select Lock FF
in the logic; light the SELECT LOCK
indicator and raise indicative bits
if queried by a Request Diagnostic
Sense bit. The condition must be
reset to load heads again.
If -16v power is lost, the following occur:
1.
The speed detection circuit in the
logic detects the speed loss and
opens Speed relay K~. As a backup
circuit, when the speed is less than
about 2000 rpm, the motor centrifugal
switch closes. This breaks the gate
in the -16v sense circuit (Figure
3-4)to open K5 and energizes K4 to
start a new first seek interlock
time delay.
2.
1.
The -16v Sense circuit opens KS. It
also generates an undervoltage fault
condition to set the Select Lock FF.
2.
With K5 open, retract power is
applied to the voice coil. Since
the undervoltage fault has disabled
the read/write logic, the circuit
is disabled prior to carriage retraction.
3.
Relay KS remains energized, so the
drive motor continues to run. Heads
cannot load until the SELECT LOCK
indicator is cleared.
With K2 open:
"a.
K5 opens to apply -16v retract
voltage to the voice coil.
b.
+20 vdc power is removed from
the read/write logic.
If ±20v or ±5v power becomes insufficient,
the heads do not retract. However, the
undervoltage condition sets the Select Lock
FF. This has the following effects:
3.
Relay K3 is de-energized when speed
drops below 2700 rpm.
4.
Relay K6 remains energized to continue to apply -16v retract voltage
until the heads retract sufficiently
to open the heads loaded switch.
1.
SELECT LOCK indicator lights.
2.
If heads are not loaded, loading
is inhibited.
When the heads unload, unit Ready
drops.
3.
All controller-initiated seeks are
inhibited.
4.
Read and Write gates are inhibited.
5.
During a Request Diagnostic Sense,
BOBS, the following bits are up:
5.
Loss of DC Power
If +20Y power is lost, all relays open and
the ac input to the dc power supplies is
opened. The effect is the same as if all
ac power were lost.
83313200
A
3-9
a.
Bit 0 (Select Lock) and bit 4
(+ volt) for +20v or +5v fault.
b.
Bit 0 (Select Lock) and bit 3
(- volt) for -5v or -20v fault.
2.
r----'
When the heads unload:
a.
Relay K3 de-energizes.
b.
The speed detection circuit is
disabled to de-energize relay
K2.
c.
Unit Ready drops.
d.
If power is dropped by the system (Kl opens), ac power is
removed from the dc power supplies .. If power is dropped because START was turned off, however, dc power is not dropped.
Power Off Sequence
The normal Power Off sequence begins when
the controller opens the sequence power line
to the drive. Sequencing is then as follows
(see Figures 3-5 and 3-6):
1.
Relay Kl de-energizes:
a.
b.
The control interlock opens to
raise an Unload Heads command
within the logic. This sets the
RTZ latch which, in turn, causes
the carriage to retract at 7 ips.
The carriage performs a normal
RTZS, except that the logic that
normally stops the carriage at
cylinder 000 is inhibited.
3.
With K3 open:
4.
The spindle motor is disabled.
b.
Power is applied to the hysteresis brake.
With K2 open:
a.
Power stays up within the drive
because the heads loaded sense
function of sensing board A2A3
(Figure 3-4) enables AIQl as lang
as the heads remain loaded.
+20v removed from read/write
logic.
LOSS (AND RECOVERY)
OF INPUT AC OR 5V
CIRCUIT BkEAKER
LOSS OF - 18V
RETRACT VOLTAGE
NORMAL
a.
~
CONTROL INTERLOCK
~
SPINDLE MOTOR
PO'HER RELAY K3
LJ:-
~ ~ ~
:
: r
:
r
REVERSE POSITIONER
MOTION
FORWARD POSITIONER
MOTION
II
II
I
I
II
I
I
I
I
I
R/W HEADS
I
I
I
,
I
I
CURRENT OR -16V
FAULT ENABLE
I
,
I
I
1
SPEED RELAY K2
:
I
+20V TO WRITE
CIRCUIT
I
ON
r:
r:
I
,
~
I
RETR ACT RELAY K5
----L-
I
'
i1I
:I
Jt-.-.:
I
OFF~
OFF
_____
rI
,I
::
:!~I
\l..
L-rL
y
ON----/
:
I
FIRST SEEK
INTERLOCK MOTOR
I
I
I
I
~
INTERLOCK CYCLE S'II
NOTES:
RETRACTED STOP ENCOJNTERED.
o
LOSS
VELOCITY <35 IPS. PERIOD INDETERM INATE.
FAULT DETECTED.K!I RETRACTS POSITIONER
~ CYCLES WILL REPEAT UNTIL END OF THAT
CYCLE DURING WHICH SPEF.D RECOVERS.
SPEED CAN RECOVER ONLY DURING A
FIRST SEEK CYCLE.
@)
®
I
LOSS
I
RECOVERY@
I
,
I
'I
~
....,1I ':
,
.r;LLL.sTII
I
II
I
,
I
I,
,
I
"
,
I
I'
I
,
~
I '
I
"
~
,. , 'I
~
I I
II
--11
'I
@"
:L
I
.J.ILJ"'7L
I
LOSS
I
RECOVERY
NO IIRAKING OCCURS IF INPUT AC
OR HOY IS LOST.
RECOVERY IS NORMAL
POWER UP.
Figure 3-6.
3-10
I
,
I
I
1
LOGIC/POSITION ER
DC VOLTAGES
®
®
~
:TI..l.-Jf
HEADS LOADED
SW STATE OR K8
-16 VOLTS
I
I
I
~
"'TTl ~
:1
HYSTERESIS
BRAKE POWER
EMER RETR ACT
PWR (CAP DISCH)
LOSS (AND RECOVERY)
OF SPEED
Power Off Timing
83313200
A
b.
Relay K5 opens. The emergency
retract capacitor discharges
through the voice coil to pull
it back against its retracted
stop.
Assuming Kl is open, and with the heads retracted, the +20Y enable is removed ~rom
AIQl to disable the primaries of Tl and T2.
The only dc voltage remaining on is the +20Y
required to power up again.
LOGIC CHASSIS
The logic chassis assembly consists of a
wire wrap board, logic cards, test point
panel, air plenum and dc power supply. The
entire assembly forms the rear door to the
cabinet. Flexible tubing from the blower
assembly connects to the air plenum and provides air to cool the logic cards and the
dc power supply.
The logic cards are installed on the protruding pins of one side of the wire wrap
board. Wiring between cards and to and from
the logic chassis occurs at the protruding
pins on the opposite side of the wire wrap
board. Access to this wiring is gained by
releasing two 1/4-turn fasteners at the top
of the door and removing the outer surface
of the rear door.
o
DECK ASSEMBLY
The deck assembly mechanism (Figure 3-7)
drives the disk pack and loads and positions
the read/write and servo heads. The deck
assembly consists of a drive motor, hysteresis brake,
spindle, actuator, two transducers, and a first seek interlock assembly.
Drive Motor Assembly
The drive motor drives the spindle assembly.
The motor is a 3/4-hp unit of the induction
type. The motor is secured to a mounting
plate. The motor mounting plate is secured
to the underside of the deck plate in such
a manner as to allow control of belt tension.
Power is transferred to the spindle via a
flat, smooth-surfaced belt that threads over
the pulleys of the spindle and drive motor.
Two idler springs maintain a constant tension
on the motor mounting plate to keep the belt
tight.
A second pulley on the drive motor shaft
links the motor (via a V-belt) to the hysteresis brake.
The temperature of the drive motor is monitored by an internal thermostat.
If the
motor overheats, the thermostat opens. This
applies ac across the DRIVE MOTOR circuit
breaker coil to open the contacts. The result is a speed loss (refer to Power Supplies). The DRIVE MOTOR circuit breaker
must be reset to ON to restore operation.
The logic card section contains the bulk of
the logic cards used in the cabinet (five
cards are located on the deck assembly).
The vertically mounted cards are installed
in four rows (A top row and D bottom row) at
numerically identified locations.
Hysteresis Brake Assembly
Some cards span two rows and are referred to
as full-size cards. Others span a single
row and are called half-size cards. Refer
to the Diagrams section of the Maintenance
manual for a description of the logical
functions performed by the cards. The Logic
Card manual provides a physical description
of the cards. The Wire Lists section of the
Maintenance manual contains a tabulation of
the wire wrap connections made in the
chassis.
The hysteresis brake decelerates the drive
motor during a Power-Off sequence (refer to
Power-Off sequence paragraph). The brake
is energized whenever Motor relay K3 is deenergized. On units with PE39280B the
Hysteresis Brake is attached to the drive
motor housing. On units without PE39280B
the brake mounts on a plate which, in turn,
is mounted on the motor mounting plate; and
the brake and motor shafts are linked via
a V-belt and a pulley on each shaft.
The test point panel at the top of the logic
chassis provides a convenient point to
measure the dc voltages. At the bottom of
the logic chassis assembly, and on the front
panel of the dc voltage section of the power
supply, are located the LOCAL/REMOTE switch,
the indicator for +20Y power and the circuit
breakers for ±46v, ±20v, and ±lOv. Specific
information on each control or indicator on
the test point and dc power panel is provided in the Operation section of this
manual.
The brake consists of two concentric permeable bodies. These cylinders are assembled, one inside the other, with a uniform
gap separating the outer diameter of one
from the inner diameter of the other. These
adjacent surfaces are machined to contain
a series of pole faces. A permanent magnet,
in the shape of a cup, fits in the gap to
separate the cylinders. This cup is connected to the drive motor shaft directly in
units with PE39280B and via a V-belt in
units without PE39280B. As long as drive
83313200
C
3-11
C'
DISK PACK CANNISTER
FIRST SEEK
INTERLOCK MOTOR
~
ACTUATOR
ASSEMBLY
SPINDLE
READ/WRITE
HEADS (19)
:....-- TRACK SERVO
HEAD(I)
GROUND SPRING
DRIVE MOTOR PULLEY
Figure 3-7.
3-12
8W37
Deck Assembly
83313200
A
or spindle motor power is applied, brake
power is not available, and the cup is driven
at the speed of the motor., When drive or
spindle power is removed, braking power is
applied. A flux field is created between
the inner and outer cylinder pole faces as
braking voltage (±20 volts) is applied to
the inner cylinder. The flux field sets up
what is in effect magnetic friction between
the inner cylinder and the cup, causing the
cup (and motor) to decelerate.
Spindle Assembly
The spindle assembly is the physical interface between a drive and a disk pack. The
surface of the pack mounting plate (Figure
3-8) mates directly with the center of the
disk pack.
A vertically free-floating lockshaft runs
through the center of the spindle assembly.
The upper end of the lockshaft contains
internal threads that engage the external
threads of a stud projecting from the disk
pack. When the .disk pack canister cover
handle is rotated clockwise, the springloaded lockshaftis pulled upward and the
disk pack is pulled down. As a result, the
mating surfaces of the disk pack and spindle
are engaged by a force of approximately 325
pounds. When the disk pack is fully engaged,.a release mechanism in the canister
handle frees the canister from the disk pack.
The spindle is locked by the pack canister
when installing or removing a disk pack.
This makes it easier to install or remove
a disk pack by preventing spindle rotation.
The pack on switch and ground spring (Figure
3-8) are mounted at the lower end of the
spindle assembly. The ground spring is
mounted so that it is always in contact with
the lockshaft to bleed off any accumulation
of static electricity on the spindle to the
.deck through a ground strap. The pack on
switch contacts transfer in response to the
vertical movement of the lockshaft. When
the shaft is up (disk pack mounted), the
contacts are closed. When a pack is not installed, the shaft moves downward to deflect
the switch actuator and transfer the contacts. The switch is part of the interlock
that inhibits spindle motor power to an
improperly configured unit.
Actuator
The actuator consists of the carriage, actuator housing, and magnet assembly. The
actuator (Figure 3-9) is the device that
supports and moves the read/write and track
servo heads. The forward and reverse moves
of the carriage on the carriage track are
controlled by a servo signal. Thebasic
signal is developed in the logic section and
processed by a power amplifying stage in the
power supply. The power amplifier output is
applied to the voice coil positioner (part
of carriage). The signal causes a magnetic
field about the voice coil positioner. This
magnetic field reacts with the permanent
magnetic field existing around the magnet
assembly. The reaction either draws the
voice coil into the permanent magnet field
or forces it away. Signal polarity determines the direction of motion, while signal
amplitude controls the acceleration of the
motion.
The voice coil positioner is a bobbin-wound
coil that is free to slide in and out of the
forward face of the magnet assembly. Fastened
to the positioner is a head/arm receiver
which holds the 19 read/write heads and the
single track servo head. The head/arm receiver mounts on the carriage and bearing
assembly that moves along the carriage track
on eight bearing type rollers. Movement of
the positioner in or out of the magnet causes
the same motion to be imparted to the entire
carriage assembly. This linear motion is
the basis for positioning the read/write and
track servo heads to a particular track of
data on the disk pack.
(Refer to Head Loading paragraph for detailed information on
read/write head loading and unloading.)
GROUND SPRING
BDI63A
Figure 3-8.
83313200
C
The positioning signal is derived in the
logic chassis and power supply. The signal
is applied to the voice coil positioner via
two flexible, insulated, metal straps, the
ends of which are secured to the cam mount
and the carriage and bearing assembly.
Spindle Assembly
3-13
I
•
ACTUATOR - CARRIAGE
RETRACTED
HEAD/ARM
RECEIVER
I:::::::~~~r~~~~~lL_11~~~~~~~~~~~~-_CARRIAGEASSEMBLY
AND BEARING
ACTUATOR
Pt==f:::::i""'ll==::!..._..../HOUSING
TRANSDUCER END
CAP/SPRING
'\
PARTIAL HEAD
COMPLEMENT
SHOWN
ACTUATOR - CARRIAGE
EXTENDED
I
,~
\
7JI
Figure 3-9.
Actuator Assembly Elements
During any .Seek operation, the logic must be
informed of the current location and velocity
of the carriage. This information is provided by the velocity transducer in the
magnet assembly and the lone track servo
head installed on the head/arm receiver.
The transducer is a two-piece device, one
piece stationary and the other movable. Refer
to the Transducers paragraph for a complete
description.
The actuator contains a stop mechanism to
limit extremes in forward and reverse movement. The stop assembly is a rubber cylinder sandwiched between two metal plates. If
the carriage moves too far toward the disk
pack, the stop rod heads contact the plate
on the magnet-side of the rubber cylinder.
If the carriage is retracted far enough
3-14
away from the disk pack, the rear of the
head/arm receiver contacts the stop assembly stud protruding through the stop plate.
Head Loading
The read/write heads must be loaded to the
disk surfaces before exchanging data with
the controller. The heads must be removed
(unloaded) from this position and driven
clear of the disk pack either when power is
removed from the unit or when the disk pack
velocity falls below about 2700 rpm. The
actuator components involved in these operations are identified in Figure 3-10.
Head loading amounts to allowing spring
pressure of the floating arm (part of head/
83313200
A
,-.' '
FLOATING ARM
UNFLEXED PROFILE
~::::::;::;L-_..Iiiiiii:iiiiiii:=====~=:::::::a OF HEAD ASSEMBLY
" t·
READ/WRITE
HEAD
DUAL SURFACE 0151(
(PART OF DISI( PACK)
\
111--.....
EID.
FIXED ARM
CARRIAGE
\
CAM
~(PART
OF HEAD CAM)
t;;:;;;;~i~~'::::::(.3:::;~~=::;=;L1_--lliiiiiiiiiiiiiiii;::::::=
S\
i ~;'I
/' _ .J,
\
C::::~·==~--::S~+--::::::::::r--~~~===
II
I
Ji.l
HEADS UNLOADED-CAM
SURFACE ON EACH HEAD
ASSEMBLY RI DES ON CAM
WHEN CARRIAGE IS·
RETRACTED. READ/WRITE
HEAD FACE MOVES CLEAR
OF DISK SURFACE.
:":'H:EA"!:"'D=""""'C~A~M SECUR ED TO "!:"'AC=:1:-:U~A:-::T=-=O-::::R"""!H~O=-:-U""=S~IN'=G
\ rrY--'" /
r
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I.
::, I
I
..J
I.
U.. l-_J
•
CUSHIONING LAYER OF AIR
EXISTS ON SURFACE OF
SPINNING DISK. HEAD GIMBALS
COMPENSATE FOR DISK VARIATIONS.
Figure 3-10.
arm assembly) to move the aerodynamically
shaped head face toward the related disk
surface. When the cushion of air that exists
on the surface of the spinning disk is encountered, it resists any further approach
by the head. Spring pressure is designed to
just equal the opposing cushion pressure
(function of disk pack rpm) at the required
height. As a result, the head flies. However, if the 'spring pressure exceeds the
cushion pressure (as would happen if the
disk pack lost enough speed), the head stops
flying and contacts the disk surface. This
could cause damage to the head as well as
the disk surface.
To prevent damage to the heads and/or the
disk pack during automatic operation, loading occurs only after the disk pack is up to
speed and the heads are over the disk surfaces. For the same reason, the heads unload automatically and are retracted if the
disk pack rpm drops out of tolerance. During
manual operations, heads should never be
loaded on a disk pack that is not rotating.
Head loading is part of the Power On/First
Seek function. As power to the deck is sequenced up, the drive motor starts. This
initiates disk pack rotation and a first
seek interlock delay. Actual delay is approximately 15 seconds.
83313200
A
1"""'-- HEADS LOADED - CAM SURFACE
,....~
- - '-""
ON EACH HEAD ASSEMBLY RIDES
OFF CAM AS CARrclAGE EXTENDS.
SPRING FORCE OF FLOATING ARM
MOVES READ/WRITE HEAD TOWARD
DISK SURFAr.E UNTIL OPPOSING
FORCE OF AIR LAYER CANCELS
FORCE OF FLOATING ARM.
?I'
Head Loading
When the disk pack rpm reaches 3000, the
power supply' speed relay energizes to establish the ability to continue the operation ..
Upon completion of the first seek interlock
delay, the logic specifies a forward seek
and the carriage moves forward toward track
O. Head loading occurs during this forward
motion. The carriage continues toward the
spindle until the servo detects track o.
The floating arm (Figure 3-10) is designed
to maintain a constant loading force. While
the heads are retracted, head carns on the
actuator. housing bear against the floating
arm cam surfaces. The cams support the loading force and hold the heads in unloaded
position. As the carriage moves forward, the
floating arm cam surface rides off the head
cam just after the read/write heads move out
over the disk surface. The loading force
moves the head face toward the air layer on
the surface of the spinning disk until the
opposing forces balance.
The heads loaded switch status reflects the
state of the read/write heads (loaded or
unloaded). This status is used in the logic
chassis and power supply. The switch mounts
on the carriage track and is transferred by
carriage motion. Whenever the carriage is
3-15
fully retracted, the switch st~te reflects
the unloaded status of the heads". As the
carriage moves forward during a Power On/ "
First Seek, the switch transfers at a point
within about 0.1 to 0.2 inch forward of the
retracted stop. This switch status remains
unchanged until the carriage is retracted to
the same position and, as such, does not
precisely indicate the loaded/unloaded stabm
of the heads. Precise status is determined
by the logic when the servo track head senses
dibits.
Head unloading occurs whenever power to the
unit is removed or disk pack rpm drops below
tolerance. Either event drops a speed enable
signal to the logic. This causes the voice
coil to drive the carriage in reverse from
its current location toward the retracted
stop.
(Either normal or emergency methods
can be used. Refer to Power Off Sequence
paragraph for additional information.) As
the carriage retracts, the cam surfaces encounter the head arms and each head rides
vertically away from the related di~k surface. The carriage continues back to the
retracted position and stops.
Head/Arm Assemblies
Twenty head/arm assemblies are mounted on
the carriage. A read/write head/arm assanbly
consists of a read/write head assembly
mounted at the end of a supporting arm structure. A track servo head/arm assembly consists of a read coil head assembly mounted
at the end of a supporting arm structure.
The head assembly (Figure 3-11), which includes a cable and plug, is mounted on a
gimbal ring which, in turn, is mounted on a
floating arm. This method of mounting allows
the head assembly to pivot (independent of
the arm) tangentially and radially relative
to a data track on the disk surface. Such
motion is require.d to compensate for IX>ssible
irregularities in the disk surface.
The arm structure consists of a floating arm
secured to a heavier fixed arm. The end of
the fixed arm opposite the head mounts in
the carriage receiver. The floating arm is
the mounting point for the head and is
necessarily flexible ~o that it can flex
during load and unload motions, onto and off
of the cam surfaces.
Freedom a"nd mobility of the head are necessary elements to being able to function with
interchangeable disk packs. During head
loading, each floating arm is driven off the
related cam and unflexes to force a head
toward the air cushion on the spinning disk
surface. The force applied by the floating
arm causes the heads to fly or float on the
air cushion. Vertical motion by a disk surface (due to warpage or imperfection) is
FORCE APPLIED BY
FLOATING ARM
:>(
SU~
CAM AND CAM
FACE
IS LOADED TO DISK
SURFACE
DISK
SEPARATED-";E~ ROTATION
)
/
CAM LEAVES CAM
SURFACE-HEAD
BECOMES AIRBORNE
\
CAM2."A~
CAM SURFACEHEAD IS UNLOADED
~
READ/WRITE HEAD AND
GIMBAL SPRIN8 MOTION
ABOUT THIS AXIS CREATED
BY PIVOTING ABOUT
CAMMING
SURFACE
~
~
TH8
®
Figure 3-11.
3-16
Head/Arm Assembly Motion
83313200
A
countered by a move in the opposite direction
by the gimballed head and/or floating arm.
As a result, flight height remains nearly
constant.
Velocity Transducer
The velocity transducer (Figure 3-13) is a
two-piece device consisting of a stationary
tubular coil/housing and a movable magnetic
core.
Transducers
The deck assembly contains two transducers:
speed sensing transducer and velocity transducer. These transducers provide signals
that are used by the logic chassis and the
controller to generally control the progression of most machine operations.
Speed Sensing Transducer
The speed sensor (Figure 3-7 and 3-12) generates a voltage output whenever a ferrous
material (steel pin set in spindle pulley)
enters the magnetic field surrounding the
pole piece at the pickup end of the transducer. The logic then shapes this signal
into a 55 microsecond pulse. As long as the
speed exceeds 3000 rpm, one of these pulses
will be sensed at least once each 20 ms. A
sensing circuit within the logic monitors
the pulse repetition rate and provides an
enable to Speed relay K2.
If speed is insufficient, the pulse repetition rate is reduced accordingly. This has
either of two effects:
1.
If the heads are not loaded, K2
cannot energize and the logic will
not initiate the load sequence.
2.
If the heads are already loaded, K2
opens, thereby opening the coil of
Retract relay K5. The voice coil is
disconnected from the logic power
amplifier and connected to the -16v
emergency retract capacitor. The
heads immediately are unloaded to
the retracted stop.
ctJ
l
I
£
PULLEY
The First Seek Interlock assembly provides
a fixed time delay from the completion of
the Start interlocks until heads can be
loaded during the Power On/First Seek sequence.
The assembly consists of a motor, reset
switch, cam linkage, and a mounting base.
The base mounts on the deck assembly. The
motor is energized during the Power On sequence and starts a IS-second (approximate)
first'seek interlock delay cycle. The cam
revolves until the reset switch is encountered.
The switch then transfers and removes power
to the motor and signals completion of the
delay cycle to the logic.
If power is lost or dropped during the cycle,
the cam completes the initial cycle upon reapplication of power. At this time, a new
cycle is initiated if Speed relay K2 has not
been energized.
Refer to Power On paragraph
for a complete description of conditions
that apply power to the first seek interlock motor.
BLOWER SYSTEM
SPEED
~SENSOR
7S148
Figure 3-12.
A
First Seek Interlock Assembly
~ SPINDLE
~
55 p.S PULSES
83313200
The magnetic core is connected via "the extension rod to the rear surface of the head/
"arm receiver. All motion of the carriage is
therefore duplicated by the magnetic core.
As the core moves, an emf is induced in the
coil. The amplitude of this emf is directly
related to the velocity of the core (and
carriage). The polarity of the emf is an
indication of the direction of movement by
the core (and carriage). The transducer
output drives an operational amplifier located in the logic chassis. This signal is
used by the servo logic to control acceleration/deceleration of the carriage during
Seek operations.
Speed Detection
The blower system (Figure 3-14) provides
positive pressure in the pack area. The
presence of this elevated pressure results
in an outward dispersion of air preventing
ingestion of contaminated air. This air
flow greatly reduces possible contamination
and resulting damage to the disk surfaces
and the read/write heads.
Power to the blower drive motor is available
whenever the UNIT POWER circuit breaker is
on.
3-17
I
..
I
TRANSDUCER LOGIC CHASSIS
~
VELOCITY
SIGNAL
f
VELOCITY
~
Figure 3-13.
SPINDLE AREA
1T41
Velocity Detection
ACTUATOR AREA
BLOWER
80348
Figure 3-14.
3-18
C=~
Blower System
83313200
C
DISK PACK
The disk pack is the recording medium for
the drive. The disk pack consists of 12 .
l4-inch disks, center-mounted on a hub. The
recording surface of each disk is coated
with a layer of magnetic iron oxide and related binders and adhesives. The top and
bottom disks are protective non-recording
disks.
There are 19 recording surfaces and one
track servo surface. The servo disk contains pre-recorded information that is used
by the servo logic to position the heads to
the desired track.
The 823 recording tracks (0-822) are grouped
in a 2-inch band near the outer edge of the
disk. Track 822 has a diameter of approximately 9 inches, while the diameter of track
o is about 13 inches. The tracks are spaced
about 0.0026-inch apart.
The disk pack has a two-piece container. The
bottom cover can be removed simply by grasping and rotating the center hub. The top
cover is designed so that it can be removed
only b¥ installing the disk pack on the
spindle. The disk pack can be removed from
the spindle only by using the top cover (see
Operation section). This design protects
the disk pack from physical damage and~tly
reduces the possibility of contamination of
the disk pack recording surfaces.
LOGIC FUNCTIONS
The logic functions performed by the drive
are s~bdivided as follows:
•
Basic Interface Description
•
•
•
Unit Selection
Diagnostic Operations
•
Basic Read/Write Principles
•
Write operations
•
Read Operations
Seek Operations
Most operations require the transfer of data
between the controller and the drive. Descriptions of these signal interchanges will
emphasize drive functions. Controller func-.
tions are described only where necessary to
clarify drive operations. Unless otherwise
specified, controller
illustrative purposes
applicable controller
controller operations
signal timing is for
only. Refer to the
manual for details of
and actual I/O timing.
BASIC INTERFACE DESCRIPTION
Figure 3-15 is a block diagram of the drive
and its I/O lines. The block diagram shows
only the main elements involved in the I/O
dialog. More detailed diagrams that illustrate signal interchange between drive logic
subsystems are pr.ovided in the applicable
theory portion of this manual.
Signals are exchanged between the controller
and drive by two signal cables. These cables
are the "A" (Control and power sequence)
cable and the "B" (Data and PLO signal) cable.
The· "A" cable is a twisted pair cable containing 104 lines. ·The "B" cable contains
shielded balanced lines. Dual channel units
have a pair of cables for each controller.
Definitions of the signals on the I/O lines
are provided by Table 3-1. Table 3-2 defines
the meanings of the bits on the bus lines in
accordance to the active tag.
UNIT SELECTION
The drive must be selected before it can
accept any commands from the controller.
There is one case where the drive can communicate with the controller without previous selection (Poll Devices) but the drive
must be selected before any further operation can take place.
The unit is selected when the Module Select
Gate line goes high, Tag 3 Bus Out Bits 7,
6, and 5 match the LAP decode, and parity
is odd. The unit is selected and available
for further commands from the controller as
long as Module Select Gate remains high.
While selected the drive physical address
code is transmitted to the controller on six
lines using a three of six code.
Bus In Bit 6 when active, defines the unit
as a 200 megabyte capacity unit.
SEEK OPERATIONS
Seek operations are those drive functions
that cause a repositioning of the read/write
heads. The heads are attached to the actuator which, in turn, is moved by a voice
coil positioner. The mechanical elements
involved in the mechanism are described in the assembly p:ntion of this section.
C:I
83313200 A
3-19
.....--
BUS OUT:)
~
COMMAND COMMANDS
DECODE
I--
DRIVE SELECTED BUS
3 OF 6 CODE
~
TAG 3
-
.....--
LOGICAL
ADDRESS
PLUG
SELECTION
LOGIC
,
TAG PARITY
~
.
TAG VALID
Y
TAG GATE
MOD SELECT GATE
.....---
HEAD
REGISTER
AND SELECT
~
~
WRITE READ
LOGIC LOGIC
T
f
SERVO
HEAD
R
0
L
L
E
R
TRACK
SERVO
1
t
J
•
DIFFERENCE COUNTER
N
N
S
T
M
T
R
0
L
L
E
E
R
R
PLO
CLOCK ..
L
SEEK CONTROL
ACCESS
CONTROL
8 SERVO
ERRORS~
DEVICE
CHECK
LOGIC
S
0
G
I
C
L--
-......
I
T
E
R
CYL
PULSES
C
0
L
~
DI BITS
SECTOR
AND INDEX
DETECTION
RESET
T
R
A
E
X
~
I
CLOCK
READ
DATA
r--:P
0
N
~ r----v
~
L
T
I
•
t
M
U
READ/WRITE
HEADS
.
C
-...
DEVICE
CHECK
CYLINDER
ADDRESS
REGISTER
DIAGNOSTIC
LOGIC
'"---
..
METERING IN A
METERING
IN
~
L-..-
""'--
Figure 3-15.
3-20
..
METERING IN B
Logic Block Diagram
8080
83313200
A
c.
TABLE 3-1.
Source
1
I/O LINES
Function
Signal Name
IIAII CABLE LINES
I
t"""
~)
Controller
Tag Bus Lines
Four lines plus parity that define operation
to be performed by drive. Decoded in drive to
define Tag functions.
Controller
Tag Gate
Gates Tag Bus signals into drive. Odd parity on
Tag Bus is maintained during time Tag Gate is
high.
Cont;.rpller
Bus Out. (BO)
Eight bits plus parity that supply control signals to the drive. Meaning of the signals is a
function of the active tag lines.
Controller
Module
Controller
General Reset
Clears all reserved latches of drives not
selected.
Controll,er
C<;>ntroller On
Power (COP)
Transmits a -l2v signal to drive when controller
power is on. Enables interface receivers of this
channel.
Controller
Power Up
Sequence Line
A ground on this line activates the Power Sequence in the drive.
Drive
Drive Selected Bus
Six lines which return drive units "3-of-6" code
to controller when drive is selected. Codes are
as follows:
Sel~c~
Gate
Used with Tag Decode 3 to seleot a drive when
the drive has decoded a valid logical address.
Drive
Location
Bits
2
3
4
5
6
A
B
1
1
1
0
0
0
1
1
0
0
0
1
C
1
0
1
0
1
0
D
E
F
G
1
0
0
0
1
1
0
1
1
1
0
0
0
1
0
1
0
1
0
0
1
1
1
0
H
0
0
0
1
1
1
7
Drive
Bus In (BI)
Eight lines plus parity that supply informatio~
signals to the controller. Meaning of bits is
a function of the Tag Bus lines fran the controller.
Drive
Tag Valid
This line indicates a Tag Bus signal, Tag Gate
and correct parity has been received.
Drive
Metering in A
Active when unit is on line, a seek or restore
is in process and Tag 9-BOBl was not activated
after last Seek Complete or Record Ready interrupt. This line is also active during a Record
Searcq operation until the first Record Ready
interrupt is deteoted. (This line is not used
by the controller.)
o
83313200
A
3-21
TABLE 3-1.
SOl,lrce
I/O LINES (CONTID)
Signal Name
'""
Metering in B
Active when unit is on line, a seek or restore in
process and Tag 9-BOBI was active after last Seek
Complete or Record Ready interrupt. This line is
also active during a Record Search operation until
the first Record Ready interrupt is,detected.
(This line is not used by the contr~ller.)
Drive
Device Check
Signals that a drive recognizable error has
occurred in the selected drive. Drive recognizable errors are:
1.
2.
3.
4.
5.
6.
7.
8.
9.
DIP (Device On
Power)
(Seek Incomplete) AND (Offset Reset OR Offset
Start)
Start Seek and (Offset Active OR Seek Incomplete OR Not On Cylinder)
Diagnostic 1 and (Offset Reset OR Offset
Start OR Return to Zero Seek OR Start Seek)
Operate Tag (Tag 11) and (Not On Cylinder
OR Diagnostic 1)
Select Lock latch set by:
a. Write and No write Current, or
b. Not Write and write Current, or
c. Multiple Heads Selected, or
d. Write Overrun,. or
e. Write and Offset, or
f. Read and Write, or
g. Voltage Faults, or
h. No Servo Tracks, or
i. Loss of AC Write Transitions
j. Write and Not On Cylinder
k. Write Gate and No Head Selected
.,'
(-\
Head Advance and End of Cylinder
Interface Check
Monitor Check
Test Logic
Transmits a -12v signal to the controller when
unit power is on. This signal is used in the
controller to open its interface line receivers
for this unit.
"B" CABLE LINES
Controller
Write Data
Transmits modified frequence modulation (MFM)
data to be recorded on the disk pack. Bit rate
is 6.451 MHz.
Drive
Read Data
Transmits detected digital MFM data.
Drive
PLO Clock
Transmits 806.4 kHz digital pulse train derived
from the disk pack servo track.
3-22
,
Function
Drive
Drive
..
83313200
A
TABLE 3-2.
TAG DECODE AND CONTROL BUS FUNCTIONS
Tag No. & Name
1
Transmit Sector
Notes and Function
1.
2.
3.
unit must be selected.
Sets Sector Register to a value determined by BOBI-B7.
Turns on the Record Search Latch.
4.
Causes Record Ready interrupt (see Tag 2 below) to be activated when the Sector Counter value equals the Sector register.
The Interrupt signal drops when sector count advances. It is
reactivated each disk revolution until serviced.
1.
2.
unit need not be selected.
Causes unit with interrupt condition to place its Logical
Address Plug (LAP) decode bit on BI. Interrupt 'conditions
are: attention latch on, Seek Complete Interrupt, Seek Incomplete Interrupt and Record Ready Interrupt.
3.
4.
Tag 2 BOB7 polls units 0-7.
Tag 2 BOBS polls Service unit.
1.
Selects unit by turning on Selected latch if: BOB7, B6 and
B5 match the LAP decode (BOB3 selects Service), Module Select
Gate is high.
2.
BIB6 is returned to controller if unit is a 200 megabyte unit.
1.
2.
unit must be selected.
Byte on Bus In returns status information to controller as
follows:
2
Poll Devices
3
Transmit Module
Address
u
4
Request Status
BIB
o
1
2
3
3.
o
1
2
3
4
5
6
S
1.
2.
BIB
4
5
6
7
Name
On Line
Attention
Busy
Record Search in
Progress
Bus Out Byte is not significant unless Tag 13 BOB2 (Diagnostic
Mode 2) is set. In this case, the Bus Out bits command
various drive operations as follows:
BOB
Request Address
Name
Index Error
Offset Active
Seek Incomplete
Seek Complete
Command
Simulate Even Dibit
Simulate Forward EOT Enable
Simulate Reverse EOT Enable
Simulate Velocity
Blank On Cylinder
Simulate Fine Enable
Inhibit Unload Heads and Simulate Heads Loaded
Unit must be selected.
Gates the contents of various registers to BI depending on
the BO byte present as follows:
o
83313200
A
3-23
TABLE 3-2.
TAG DECODE AND CONTROL BUS FUNCTIONS (CONT'D)
Tag No. & Name
5 (Cont'd)
\.-
Notes and Function
BOB3 - Read Difference Counter
BIB
o
1
2
3
4
5
6
7
Difference
Difference
Difference
Difference
Difference
Difference
Difference
Difference
Count
Count
Count
Count
Count
Count
Count
Count
128/0ffset Reverse
64/Sign Change
32
16/400 ~in 6ffset
8/200 ~in Offset
4/100 ~in Offset
2/50 ~in Offset
1/25 ~in Offset
BOB6 - Read High Difference
BIB
o
1
4
Diff 512
Diff 256
Reverse
BOB4 - Read Head Address Register
BIB
o
1
3
4
5
6
7
Head Address Register No.
CAR 512
CAR 256
16
8
4
2
1
BOBS - Read Cylinder Address Register
BIB
Cylinder Address Register No.
o
1
2
3
4.
128
64
32
16
8
5
4
6
2
7
1
BOB7 - Read Sector Register
BIB
o
1
2
3
4
5
6
7
3-24
High Side of Sector
Sector 64
Sector 32
Sector 16
Sector 8
Sector 4
Sector 2
Sector 1
83313200
A
.
TABLE 3-2.
TAG DECODE AND CONTROL :aUS FUNCTIOHS (CONT'D)
Notes and Function
Tag No. & Name
5 (Cont'd)
A Read Sector Register command may be used with a Save Sector
operation as follows:
Save Sector (Tag 11 BOB7) sets the Sector register to the value
in the sector counter at the time of the Save Sector command.
The Read Sector Register command then places the sector counter
value on Bus In." If the clock count within the sector has reached
23, bit 0 in the sector count byte is se~ to a "1". If the Save
Sector command does not occur before count 50 in any sector, the
sector count transfer is delayed until count 4 of the next sector
and the sector number of the next sector is transferred.
1.
6
Transmit Cylinder
Address
2.
3.
4.
5.
Unit must be selected.
Normal operation is to:
a. Set the CAR according to Bus Out Byte.
b. Reset the difference register to the highest value.
c. Reset the direction latch to forward.
d. Reset the HAR to head zero.
For normal operation to occur, the following conditions must
be met:
a. Command Valid
b. No Device Check and (Diagnostic Mode 1 latch off or
Diagnostic Mode 2 on)
c. On Cylinder or Diagnostic Mode 2 on
Regardless of whether normal operation is allowed or not,Tag
6 active causes the present value of the CAR to be placed on
the Bus In lines to the controller.
Bus In and Bus Out Byte decode is:
Bit
o
1
2
3
4
5
6
7
7
Transmit Head
Address
1.
2.
3.
Decode
CAR 128
CAR 64
CAR 32
CAR 16
CAR 8
CAR 4
CAR 2
CAR 1
Unit must be selected.
Normal operation is to set the HAR latch to the value of
" Bus Out as follows:
Decode
BOB
Decode
BOB
HAR 16
3
HAR 1
7
Not used
2.
HAR2
6
CAR 256
1
HAR 4
5
CAR 512
o
HAR 8
4
For normal operation to occur the same conditions as those
for enabling normal operation of Tag 6 and 10 must be present.
o
83313200
A
3-25
TABLE 3-2.
TAG DECODE AND CONTROL BUS FUNCTIONS (CONT'D)
Tag No. & Name
7 (Cont'd)
Notes and Function
4.
In all cases, Tag 7 causes the following bits to be gated to
Bus In.
~
7
6
5
4
8
Transmit
Difference/Offset
1.
2.
O·
1
2
3
Decode
3
2
lIAR 16
N:>t used
1
o
CAR 256
CAR 512
Qiff Coynter
128
64
32
16
BOB
4
5
6
7
Diff Counter
8
4
2
1
3.
In all cases, Tag 8 gates the difference counter output to
Bus In.
4.
Tag 8 also determines the amount of offset of the Read/Write
heads from the track center line when the Tag 8 command is
followed by an Offset Start command (Tag 9 BOB2). In this
case, offset direction and amount is set as follows:
BOB
-0
1
2
3
9
Bm
1
2
4'
8
Unit must· be selected.
Under the same conditions as required for Tags 6,7,and 8, the
difference counter is set according to the bits .on Bus Out.
.rum..
Transmit Control I
Decode
lIAR
lIAR
lIAR
lIAR
1.
2.
3.
Tag Decode
Reverse
Sign Change
Not Used
400 lJinches
BOB
-4
5
6
7
(--~
Tag Decode
200 lJinches
100 lJinches
50 lJinches
25 lJinches
Unit must be selected.
Gates the same byte to Bus In as Tag Decode 4 (Request Status) .
Performs logic control functions according to Bus Out bits
0-7 as follows:
~
1
2
Function
Enables Metering in B.
Activates Offset Start. Amount and direction of offset is specified Tag 8 BOB 0-7.
Device Check is turned on if Offset operation can not
be performed. The following conditions prevent Offset
Start.
a.
b.
c.
d.
e.
3-26
Power On Reset
Seek Incomplete
Not On Cylinder
Not On Line
Diagnostic 1 Active
83313200
A
TABLE 3-2.
TAG DECODE AND CONTROL BUS FUNCTIONS (CONT'D)
Tag No. & Name
Notes and Function
9 (Cont'd)
Function
BOB
3
Seek Start. Heads are moved the number of cylinders
specified by the value in the Difference counter.
Device Check is turned on if the operation can not be
performed.
Conditions which prevent a Seek Start are the same as
those which prevent an Offset Start plus - f. Offset
Active.
4
Rezero Start. Returns Heads to cylinder O. Device
Check is turned on if Rezero Start cannot be performed.
Not On Cylinder, Not On Line, or Diagnostic 1 active
prevent Rezero Start.
·5
Reset Head Address Register - Turns off HAR 1,2,4,8,
and 16 latches. Sets HAR to zero.
6
Control Reset. Performs same function as Power On
Reset. Resets:
a.
b.
c.
d.
7
10
Transmit Control 2
Current Fault
Write Overrun
Monitor and Mode Latches
h.
Diagnostic Mode Latches
Reset Interrupt. Resets the following interrupt circuits:
a.
b.
Sector Register Latches
Record Search Latch
c.
Attention Latch
Unit must be selected.
2.
Performs logic control functions according to BOB as follows:
BOB
Decode
0
1
2
3
Diff 512
Diff 256
Set High Diff
Reset Diff
-BOB
4
5
6
7
Decode
Reverse
Not used
Decrement Diff
Offset Reset
For normal operation to occur, the following conditions must
be met:
a.
b.
c.
A
e.
f.
g.
1.
3.
83313200
Select Lock
Device Check
Interface Check
Command Reject
Command Valid
No Device Check and (Diagnostic Mode 1 latch off or
Diagnostic Mode 2 on)
On Cylinder or Diagnostic Mode 2 on
3-27
TABLE 3-2.
Tag No..
&
TAG DECODE AND CONTROL BUS FUNCTIONS (CONT'D)
Notes and Function
Name
10 (Cont'd)
4.
Regardless of whether normal operation is allowed or not,
Tag 10 active causes the following bits to be gated to Bus In.
BIB
Decode
0
1
2,3
4
5,6
Diff 512
Diff256
Not used
Reverse
Not used
Not used
7
11
Operate
1.
unit must be selected, however odd parity is not necessary
on Bus Out with Tag 11 to activate Command Valid.
2.
Bus Out bits will be active when the Tag 11 Valid line is
activated. Tag 11 Valid is active only when all the following conditions exist:
a.
b.
No Device Check
Diagnostic 1 Latch Off
c.
Select Lock Latch Off
d.
e.
On Cylinder
Command Valid Active
f.
Tag Decode 11 Active
\ ......
3.
If Tag 11 can not be performed a Command Reject signal is
generated.
4.
A Tag 11 Valid signal allows the Bus Out bits to select the
operation as follows:
BOB
o
1
2
3
4
5
6
7
5.
Operation
Start write Address Mark
Address Mark Search
Data Enable
Select Head - according to HAR
Head Advance
Write
Read
Save Sector
The Bus Out bits may be used in combinations as follows:
Operation
Bus Out Bits
2 3 4 5 6
7
1
0
0
1
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
1
0
1
write Address Mark
Address Mark Search
1
0
0
1
0
1
1
1
0
0
write Data
0
0
0
1
Read Data
Head Advance
0
0
1
0
0
0
0
0
0
Save Sector
C
3-28
83313200
A
.
'
TABLE 3-2.
o
TAG DECODE AND CONTROL BUS FUNCTIONS (CONT'D)
Notes and Function
Tag No. & Name
11 (Cont'd)
The lines remain active until the operation is complete.
•
Write Address Mark (Tag 11 BOB 0,3,5)
Write the track for three byte times as determined by
the controller.
A 5.0
~sec
I
delay is fired which blocks Write Fault.
Bit 0 activates the Start Write Address Mark line.
Bit 3 causes a Head Select.
Bit 5 activates the Write circuit.
bits are provided to be written.
•
No clock or data
Address Mark Search (Tag 11 BOB1,2,3,6)
Operation is typically performed during an interrecord gap.
Read operation is in progress, therefore bits 2,3,and
6 are active.
Bit 1 activates the Address Mark Search. Objective is
to read until the controller senses it has not received
any clock or data pulses for three byte times.
o
•
Save Sector (Tag 11 BOB?)
Sets the Sector register to the value in the Sector
·counter. If clock count has not reached 50 when the
Save Sector signal is received, the value in the sector
counter is immediately set into the Sector register. If
a count of 50 has been reached, the Sector register is
set to the value in the sector counter at the next clock
count of 4.
The Save Sector operation allows the controller to sense
what sector the heads are in by a Tag 5 BOB? (Request
Address, Read Sector).
•
Read (Tag 11 BOB2,3,and 6)
Bit 3 allows the activation of one of the head select
lines in the same manner as in a write operation.
Bit 6 activates Read Select.
tions must be met:
a)
All the following condi-
Tag 11 Valid and Bus Out Bit 6
b)
Not Write Gate
c)
Head Select
d)
Not Diagnostic Mode 1 latch
Data Enable (Bit 2) gates the outputs of the Read detector to the controller if the following conditions are met:
a)
('-')
\......-/
83313200
C
Head Select active
b)
Read active
c)
Not Write Gate active
d)
Not Diagnostic Mode 1 Latch on
3-29
t
TABLE 3-2.
...
TAG DECODE AND CONTROL BUS FUNCTIONS (CONT'D)
Tag No. & Name
Notes and Function
•
11 (Cont'd)
Head Advance (Bit 4)
Each time bit 4 is brought up it increments the Head
Address register. The following conditions must be met:
•
a)
Not Head Select (Tag 11 BOB3)
b)
c)
Not Write (Tag 11 BOBS)
Not Read (Tag 11 BOB6)
d)
Not End of Cylinder
Write (Tag 11 BOB3 and 5)
Head Select (Bit 3) must be active to read or write.
Head Select blocks Head Advance. Head Select can not be
activated if the Diagnostic Mode 1 latch is on.
Write (Bit 5) causes the Clock and Data pulses from the
controller to be written if the following conditions
are met:
a)
Head Select (Tag 11 BOB3) active
12
Request Diagnostic
Sense
b)
Ready
c)
Not offset
Unit must be selected.
2.
Functions performed depend on which bus out lines are active.
BOB
1
2
3
4
5
6
7
2
Desired Velocity greater than 128
On Cylinder
Fine Analog
Difference Count = 0
Fine Mode
Dibits
Cylinder Pulse
EOT
Gates Status of Monitor Mode and diagnostic mode latches
to the bus in as follows:
BIBO
1
2
3
4
5
6
7
3
\,.",--,
Gates Servo Points to the Bus In as follows:
BIBO
1
3-30
('
1.
Not used
Diagnostic 4
Diagnostic 2
Diagnostic 1
Not used
Monitor Mode 4
Monitor Mode 2
Monitor Mode 1
Gates the status of Monitor State Latches 1-8 to Bus In
lines 7 through 0 respectively.
83313200
A
TABLE 3-2.
TAG DECODE AND CONTROL BUS FUNCTIONS (CONT'D)
Tag No. & Name
Notes and Function
12 (Cont'd)
BOB
4
Gates Check Status bits as follows:
BIBO
1
2
3
4
5
6
7
5
Gates fault byte bits to the bus in, as follows:
BIBO
1
2
3
4
5
6
7
C)
1.
2.
Unit must be selected.
Sets the following latches according to active bus out lines:
BOBO
1
2
3
4
5
6
7
3.
Data Fault,indicating a Select Lock condition
Servo Fault,indicating a power conflictcondition
Write Overrun
Negative Voltage Fault
Positive Voltage Fault
Air Flow Fault
Multiple Hd. Fault
Current Fault
Test Logic. This bit is used to check the Device Check
and Tag Valid circuits. Command Valid, consisting of
Valid Command decode, Tag Active and Tag Decode Odd,
'must be active to perform the Test Logic function. Test
Logic then forces a Tag Valid and turns on the Device
Check latch.
6
13
Mode/Diagnostic
Control
CE Program Stop - Switch on unit tester set
to Check Status
Motor On
Hds. Not Loaded
Even Cyl.
Interface Check
Monitor Check - set by Monitor Error
Interlocks not complete
Command reject
(Not used)
Diagnostic Mode 4
Diagnostic Mode 2
Diagnostic Mode 1
Block Parity
Monitor Mode 4
Monitor Mode 2
Monitor Mode 1
Gates the status of the Operating mode latches and the Diagnostic mode latches to the Bus In as follows:
BIBO
1
2
3
4
5
6
7
Not used
Diagnostic Mode 4
Diagnostic Mode 2
Diagnostic Mode 1
Not used
Monitor Mode 4
Monitor Mode 2
Monitor Mode 1
c)
83313200
A
3-31
Two logic circuits are used to control the
seek function:
1.
The Servo Circuit, which controls
the voice coil positioner.
2.
The Track Servo Circuit, which generates signals relating to the position of the heads over the disk pac~
Its output is also used to generate
the basic internal 806 kHz clock.
The general concepts of these two circuits
are explained to provide the general background information needed to understand the
specific types of seeks. Then more detailed
explanations are provided for the three
types of seeks: First Seek, Direct Seek,
and Return to Zero Seek.
Al though the machine clock, index, and sector
detection circuits are not directly involved
with Seek operations, their basic enable is
provided by the signals generated by the
Track Servo Circuit. These functions are,
therefore, explained following the discussion on Seek operations.
TABLE 3-3.
Circuit Element
Difference Counter
SERVO CIRCUIT
The servo circuit is a closed loop servomechanism used to position the read/write
heads. Figure 3-16 is a simplified schematic
of the servo circuit. Functions of the major
elements of the system are explained in
Table 3-3.
A servo loop sums all of the error voltages
imposed on it. The loop always attempts to
maintain itself at a null.
If not nulled,
the loop will adjust the correctabLe device
(in this case, the voice coil positioner) to
achieve this null. Signals applied to the
loop are called error voltages. Two major
error voltages are used:
1.
A position error: this is the
departure of the positioner from
the desired position.
2.
A feedback signal to modify (or
oppose) the position error to cause
a smooth motion of the positioner.
SERVO CIRCUIT FUNCTIONS
Function
Holds the complement of the number of tracks yet to be crossed
before reaching the desired track or cylinder. Counter value
is decimal 1023 (difference of zero) when on cylinder. An associated decoding network provides outputs representative of
the current general content of the counter.
In an Offset operation, the difference counter receives and
holds offset distance information.
Digital to Analog
Converter
Monitors the seven lowest order bits of difference counter to
provide an analog indication of Position Error during the last
127 tracks (except last track) of all Seek operations.
Position
Converter
Provides coarse position Error signal, the amplitude of which
is proportional to the number of tracks to go. Amplitude decreases in discrete steps (controlled by D/A converter) as last
127 tracks of a seek are crossed. Signal is inverted for reverse seeks.
Desired Velocity
Function Generator
Processes Position Error signal at gain levels that vary as
position Error decreases. The resulting output is the analog
representation of the desired velocity curve to achieve maximum control of deceleration. The parallel non-linear feedback
circuit maintains tight loop control by increasing gain as the
Position Error signal approaches zero. This gain control prevents loss of control during the critical deceleration portion
of the seek and is essential to minimize overshoot and settle
out problems.
3-32
83313200
A
TABLE 3-3.
Circuit Element
SERVO CIRCUIT FUNCTIONS (CONT'D)
Functions
Summing Amplifier
Generates a control signal to drive the power amplifier. Control
signal based on algebraic summation of position Error and Velocity
Amplifier signal causes power amplifier to accelerate carriage.
When Velocity signal exceeds position Error, carriage decelerates.
Load Gate
Provides a constant positive input to the summing amplifier.
This causes forward velocity of 7 ips.
RTZ Gate
Provides a constant negative input to the summing amplifier.
This causes reverse velocity of 7 ips.
Power Amplifier
Responds to summing amplifier perived control signal to drive
carriage mounted voice coil positioner. Current feedback is
used to stabilize the gain of the power amplifier.
Velocity Amplifier
Amplifies signal of carriage mounted linear velocity transducer
tO,provide an indication of velocity to the servo circuit. The
associated amplifier disable forces amplifier gain to zero during a Power Off sequence (unload heads). This is required so
that coupling between the positioner field and the velocity
transducer does not cause oscillation during movement to the
retracted position.
Velocity Integrator
Provides an integrated representation of velocity between each
of the last 127 track pulses of a seek. Integrator is clamped
off to gain of zero at all other times. Integrator output is a
sawtooth waveform applied to input of desired velocity function
generator between each track pulse to fill in or smooth out the
stepped signal of the D/A converter (received via the position
converter) .
Fine Enable and
Fine FF
Fine enable monitors integrated velocity. When difference
counter is 1022 (T=l) and fine enable (Velocity integrator output) exceeds 1.28v, it indicates that there is one-half track
to go. Fine FF sets to enable fine gate and clear coarse gate.
This switches Position Error input to summing amplifier from
desired velocity (coarse gate) to fine servo (fine gate). Fine
also has the following effects:
a.
b.
Turn on integrator clamp to switch off velocity
integrator.
Enables on cylinder detection.
During load or RTZ sequences, both the fine and coarse latches
are cleared. This disables both the fine and coarse gates so
that motion is under control of load gate or RTZ gate.
Bit 0 Address
Register and
Odd Cyl FF
Used to select proper track servo signal phase for use as Fine
Servo signal (signal controlling servo loop as last track is
approached and carriage is stopped). If bit 0 is not set, the
seek destination is an even numbered track and the track servo
signal will be inverted for use in stopping the carriage. If
bit 0 is set, an odd track is identified and track servo is not
inverted. Register bit content is placed in Odd Cyl FF which
performs actual gating.
o
83313200
A
3-33
TABLE 3-3.
SERVO CIRCUIT FUNCTIONS (CONT'D)
Function
.Circuit Element
Fine Servo
Amplifier
Provides the Fine Servo signal to the On Cylinder Detector and
to the fine position amplifier. This signal amplitude is proportional to distance that heads are displaced from track
centerline. Scale factor is one millivolt per microinch displacement.
If heads drift off slightly after seek is completed, track
servo signal is no longer null. This becomes fine servo signal
to drive heads back into position.
Carriage may be offset 25 to 775 microinches (in increments of
25 microinches) from nominal track centerline by application
of offset voltage to fine servo amplifier. The voltage level
is determined by Tag 8 Bits 3 through 7 when Offset Start (Tag
9 Bit 2) is received from the controller.
Provides the position Error signal, via the fine gate, to the
summing amplifier during the last one~half track of the seek.
Amplitude of this signal is proportional to distance-to-go.
Phase i i selected by Odd Cyl FF to be opposite in phase to velocity signal. The combination of the position error and
velocity signals controls voice coil current to bring positioner
into On Cylinder position.
On Cylinder
Detector
Monitors fine servo signal when T~l. When signal is less than
about 0.3v, heads are close enough to track centerline to be
assumed to be on cylinder. After 1.75 ms delay, On Cylinder
is generated.
If heads overshoot at end of seek so that voltage
exceeds 0.7v, delay is reinitiated.
Delay permits carriage to
settle out before controller may attempt any read/write operations. The On Cylinder Detector is inhibited from triggering
for 4.75 ms from the initiation of a Seek Start.
The position error signal is provided by the
position converter and its allied elements.
The amplitude of the signal is proportional
to the distance from the present position
to the desired position (tracks-to-go). The
major feedback signal is the output of the·
velocity transducer. The amplitude of this
signal is proportional to the velocity of
the positioner while the phase indicates
the direction of motion, forward or reverse.
The loop applies its position and feedback
signals to one summing point, the summing
amplifier.
If the summation of these signals
is not equal to zero, the summing amplifier
outputs a signal proportional to the amplitude of the error voltage (which signifies
3-34
the amount of displacement from the desired
position) and the phase of the error voltage (which indicates the direction of displacement) .
The error output from the summing amplifier
is applied to the actuator assembly. The
actuator contains a voice coil positioner
that supports and moves the read/write heads.
In turn, the voice coil is located within a
powerful magnet. Whenever a current passes
through the voice coil windings, the interaction of the induced emf and the magnet's
flux field cause the positioner to move.
The acceleration of the motion is proportional to the polarity and amplitude of the
voice coil current.
83313200
A
0
'-
0
(',-- ___i)
~
co
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(·8
.....
tv
0
0
DESIRED
VELOCITY
----=--I .•
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DIFF
CNTR
~.-
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DESIRED
~~~~~:~
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GENERATOR
VOICE
COIL
HEADS
LOADED
FINE
aI
ENABLE
ON
CYLINDER
DETECTION
:
BOOUSEC
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IL __ _
FINE
SERVO
AMP
-- - --,
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. . FWD SEEK
DATA. TRACK
EVEN NUMBER
DATA TRACK
I
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01 BITS I + I
r
1
NOTES'
TRACK SERVO
OFFSET FWD
(i)A..SUMMING POINT OF OPERATIONAL AMPLIFIER.
OUTPUT IS INVERSION
OF INPUT.
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FINE SERVO
(SEEK TO EVEN)
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VELOCITY
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FINE SERVO
(SEEK TO ODD)
N-CHANNEL FET TURNED ON
140 {l) BY POSITIVE INPUT.
SIGNALS NAMED WHEN INPUT
IS POSITIVE.
OFFSET GAIN/POLARITY CONTROL,
POLARITY CONTROLLED BY OFFSET
FORWARD OR OFFSET REVERSE.
OFFSET AMPLITUDE PROPORTIONAL
TO AMOUNT OF OFFSET COMMANDED.
:
ODD NUMBER
DATA TRACK
Figure 3-16.
Servo Circuit Simplified Schematic
-r-II
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DOD NUMBER
DATA TRACK
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. . . REV SEEK
EVEN NUMBER
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------
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Basic Seek Operation
Seek operations are initiated by a series of
~ontrol signals from the controller or by
lnt 7 rnally-generated signals within the drive
durlng p~w7r up ,conditions. Most long seeks
may be dlVlded lnto four phases (see Figure
3-17) :
1.
Accelerate Phase: the voice coil
receives full current to move the
positioner from the current cylinder
towards the new cylinder.
2.
Coast Phase: velocity is at its
maximum and the positioner velocity
is constant.
3.
Deceleration Phase: the positioner
is approaching the desired cylinder.
Its velocity must be reduced by
braking action to prevent overshoot.
4.
stop Phase: the positioner is almost at the desired cylinder.
It
must be stopped at the precise
centerline of the new data cylinder.
The logic is in Fine mode to stop
and hold the positioner at the new
cylinder.
Refer to the various seek descriptions for
detailed information on the exact seek sequencing.
Accelerate Phase
I
This phase is controlled largely by the position error signal. The controller loads the
difference counter with the complement of
the seek length. For example, if the heads
are,presently on cylinder 10 and must go to
cyllnder 16~, the seek length is 150 cylinders.
In blnary representation, decimal
150 is ~O 1001 0110. The complement of this
number lS 11 0110 1001, or decimal 873. At
each cylinder pulse, the counter is incremented; therefore, the greater the number
in the difference counter, the fewer tracksto-go. The counter is at its maximum value
of 1023 (11 1111 1111) when tracks to go
equal zero.
The five low-order bits of the difference
counter are applied to the position converter. The value of these bits indicates the
position error (or tracks-to-go) from 0 to
127. That is, the amplitude of the position
converter output is directly proportional to
the number of tracks remaining in the seek.
If the remaining seek length is greater than
~27 (T~128), t~e position converter output
lS clamped at ltS maximum saturated value to
cause a very large position error.
3-36
The input to the summing amplifier is now a
large signal. Since there is no velocity
yet, the current through the voice coil is
maximum, causing maximum acceleration. As
~he positioner accelerates, a velocity signal
lS generated by the velocity transducer.
This signal opposes the position error signal.
Its amplitude, however, is less. Acceleration continues.
Coast Phase
Eventually, the amplitude of the position
e:ror signal and the velocity feedback
slgnal are equal. The net error signal in
t~e loop drops to zero.
The summing amplifler output follows, so current is cut off.
Velocity is constant. Friction losses will
tend to slow the positioner but, as it does
the velocity signal decreases. This allows'
the position error signal to call for more
current.
Decelerate Phase
Braking action starts as the positioner approaches its selected cylinder.
The track servo circuit (refer to Track
~ervo C~rcuit description) has been generatlng cyllnder pulses as each cylinder is
passed. These pulses are used to increment
the difference counter. When T=64 the
position error signal from the desired velocity function generator is reduced. This
c~uses,th~ velocity signal to dominate and,
s7nce lt lS opposite in phase to the positlon error, the summing amplifier output
switches polarity. Opposing current passes
through the voice coil. The carriage decelera~es. ,Both the desired velocity and velO~lty s7gnals are decreasing simultaneously.
VOlce cOlI current decreases proportionately.
The loop maintains speed along an ideal velocity curve. This curve is the analog
version of the number of tracks-to-go. The
velocity curve is generated by the desired
velocity function generator. Its output is
compared with velocity to achieve maximum
deceleration under all conditions without
overshoot. The position signal is the sum
of the following:
1.
The position error signal from the
position converter.
Its output is
a signal whose amplitude is proportional to the number of tracks-togo.
2.
Integrated velocity from the velocity integrator. Integrating a velocity signal provides a signal
83313200 C
~ ACCELERATE+
PHASE
COAST
I
PHASE-'.~""''''--------B''AKE
I
-1
0
PHASE - - - - - - -.......t- STOP
P SE
T< 128
TRACKS
T=O
I
TO GO
I
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--l--~-~:®:
OV
VELOCITY TRANSDUCER
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-OV
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POSITION COPNERTER
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-MAX-------------------------~
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BRAKE
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- - - 1.2 BV • DE SIRED VELOC ITY
SUMMI NG AMPLI FIER.
CONTROL. ALTHOUGH
(ACCELERATE) IF
CONTINUOUS
FINE SERVO
SIGNAL.
FOR
FOR
CLARITY.
TIMING
OR
RELATI VE
SIGNAL
AMPLITUDE. XT
IS SIMPLIFIED
FU NeTIONS.
Figure 3-17.
83313200 A
SE RVO
CYLIN DER
IUUSTRATED, OUTPUT MAY
SIGt.lAL
DRAWING
LATCH SETS.
GAINS TO PERMIT
L ATCI1 SETS WH EN
T < I
NO FURTI1ER EFFECT.
BRAKING
(i)
NO
8W30
Servo Circuit Simplified Signals
3-37
proportional to distance. This signal
is a sawtooth waveform: it is pulled
back to zero by each cylinder pulse
and increases in proportion to velocity and time (distance). The
combination of the stepping-down
output from the position converter
with the ramp integrated velocity
signal results in a smooth curve of
constantly-decreasing magnitude.
3.
The function provided by the nonlinear feedback around the desired
velocity function generator.
Stop Phase
Stop phase begins when the difference counter
indicates that there is one track-to-go.
When T=l, the velocity integrator signal is
pulled back to zero by the cylinder pulse.
Its output, indicating distance, increases.
When its amplitude indicates approximately
one-half track remains, Fine Enable sets the
Fine latch.
Desired velocity is disabled
since the coarse latch is opened by Fine
being set.
The last half-track of motion is controlled
by the fine servo signal. There is a significant increase in position error gain in
switching from coarse to fine.
Fine servo
and velocity are applied to the summing
amplifier. The summation of these two
signals control the braking current.
At the start of the seek, the Odd Cylinder
FF is set if the seek is to an odd-numbered
cylinder. The odd cylinder signal controls
the phase of the track servo signal applied
to the fine servo amplifier. This adjustment is required since track servo signal
phasing is a function of the servo head
position:
the signal is negative when over
negative dibits and positive when over positive dibits. Therefore, on forward seeks,
the signal is decreasing from a negative
value toward zero when approaching a data
track with an odd number;
it is increasing
from a positive value toward zero when
approaching a data track with an even number.
The opposite is true during a reverse
seek.
Phasing of the track servo signal is selected
so that the fine servo signal opposes the
velocity signal during the last half-track
of the seek. Both signals are decreasing.
If either is greater, the summing amplifier
makes minor braking current adjustments.
When the heads are on cylinder, both signals
are zero and current is zero.
3-38
When the fine servo signal is less than about
0.3v, the positioner is, for all practical
purposes, positioned over the data track. If
the 4.75 ms delay initiated at the start of
the seek has timed out, the 1.75 ms On Cylinder Delay is initiated. After 1.75 ms, On
Cylinder is generated.
The fine servo signal remains active even
through On Cylinder is up. This is the track
following or position error operation. Since
the positioner is not mechanically locked in
place, it can drift off cylinder. As long
as it is precisely positioned, the dibits
read from the adjacent dibit tracks are equal
and opposite. Should the carriage move,one
dibit signal will increase in amplitude.
This results in a slight track servo signal
which is translated into the fine servo
signal. The summing amplifier, in turn,
senses this off-null condition and drives
the positioner back on cylinder.
If the positioner goes off cylinder sufficiently to cause the fine servo signal
greater than 0.7v for more than 800 ~sec,
the On Cylinder signal is lost. This sets
Seek Incomplete, and deselects the heads. If
the unit is reading or writing at the time
Select Lock and Device Check are also set.
Offset Head Positioning
Besides the normal seek operations, the
servo circuit positions the heads during an
Offset operation. The heads are held off
the track centerline by an amount and direction determined by a Transmit Offset command (Tag 8, Bit 0 determines direction of
offset. Bits 3-7 determine amount of offset). Heads must be On Cylinder and an
Offset Start command (Tag 9,Bit 2) must be
received before the Transmit Offset will be
acted on.
In the offset mode, the output of
the difference counter is steady and proportional to the amount of offset desired.
This raises the fine servo signal to the
fine position amplifier and causes the
heads to be driven off track centerline
until the servo loop achieves a null. Direction of offset is determined by the polarity
of the Fine Servo signal. The Offset Active
signal (Tag 11 - Bl) is set high by Offset
Start and remains high until disabled from
the controller by Offset Reset (Tag 10-B7).
Short Seeks
The preceding explanation of the basic seek
operation presumed long seeks that permitted
the positioner to attain maximum velocity.
83313200
A
\.~
"
I
",
,
C
/1
Maximum velocity of about 60 ips requires 70
tracks acceleration time. During short
seeks, gating is identical although relative
phasing of the error signals will vary. During seeks less than 128 tracks, certain
signals are available immediately: integrated
velocity, non-linear feedback to the desired velocity function generator, and a
position converter output not clamped at its
maximum value. These signals generate a
position error voltage to accelerate the
positioner.
The voice coil saturates for a shorter time
but the primary function remains unchanged:
acceleration occurs when the position error
signal exceeds the velocity signal; braking
occurs when the velocity signal exceeds the
position error signal.
TRACK SERVO CIRCUIT
Basic Description
The track servo circuit provides head positioning information. The signals generated
by this circuit:
1.
0
2.
Generate a track servo signal that
indicates the displacement of the
heads from their nominal track
centerline.
Generate indications that the heads
are positioned outside of the normal
data cylinders.
3.
Generate cylinder pulses during
seeks to indicate each cylinder
crossing.
4.
Provides signals used as the basic
806 kHz clock.
Information for this circuit is derived from
the track se~vo head (Figure 3-18). This
head is physically similar to the read/write
heads, except that it does not write. The
head reads information from the servo track
surface of the disk pack. This information
is known as dibits: dibit is a shortened
term for dipole bit. Dibits are prerecorded
on the servo surface during manufacture of
the disk pack. Do not confuse the servo
surface with the other 19 disk pack recording surfaces.
Dibits are the result of the manner in which
flux reversals are recorded on the servo
tracks. One type of track, known as the
Even track, contains negative dibits. The
other track, the Odd track, contains positive dibits.
83313200
B
There a~e 883 dibit tracks on the servo surface. At the outer edge of the surface is
a band of 24 positive dibit tracks. This
area is the Reverse End of Travel (EOT) or
outer guard band. Then, there are 823 servo
tracks alternately recorded with negative
and positive dibits. Finally, toward the
inner edge of the pack, there are 36 tracks
containing only negative dibits. This is
the Forward EOT or inner guard band.
When the read/write heads are located at the
centerline of a data track, the track servo
head is actually centered between two of the
prerecorded servo. tracks and is reading an
edge of each. The detected signal is a mixture of the two adjacent dibit signals. The
amplitude of each dibit component is proportional,to the read coil overlap of the
recorded servo tracks. with the head
centered, the amplitudes of the two types of
dibits are equal. As the head moves away
from its centered position, the amplitude of
one dibit component increases while the other
decreases. This error voltage is the track
servo signal.
Circuit Description
The basic elements of the track servo circuit are illustrated in Figure 3-19. Table
3-4 explains the track servo circuit functions.
Dibit Gating
After being differentially amplified, the
servo signal is applied to gates that separate the dibit signals by sensing the positive and negative flux reversals (Figure
3-20). A positive dibit consists of a positive-going waveform immediately followed by
a negative-going waveform. On the other
hand, a negative dibit consists of a negativegoing waveform followed immediately by a
positive-going waveform.
The dibits are analyzed by the positive and
negative gates. Each gate output switches
to the low state when it senses its respective dibit. The negative-going pulses control single-shots and JK FF's to generate
the odd/even dibits.
The even/odd dibits are used to enable the
EOT detection circuit and to generate the
basic machine clock signal.
3-39
/'
(
ODD DI BIT PULSES
EVEN DI BIT PULSES
DISK PACK
AGC
CYLINDER
PULSES
HEAD LOADING ZONE
/
OUTER GUARD BAND (REV EOT)
. /24 TRACKS OF POSITIVE DI BITS
/
/
~
# /~
T
SERVO TRACKS
INNER GUARD BAND (FWD EOT)
/ 3 6 TRACKS OF NEGATIVE 01 BITS
SERVO SURFACE
(I PER DISK PACK)
DATA SURFACES
DISK
SURFACE
N.Al8ER
HEAD/ARM
" ~:K
'-
GUARD
/
10
II
12
13
14
15
16
17
BE
18
19
GUARD DISK
~--A----'
eW21
Figure 3-18.
3-40
Track Servo Disk Layout
83313200
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REV EOT ENABLE
VELOCITY
FWD EOT ENABLE
HoSL~oED--~I-+I~~~
SEEK
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POSITIVE~
TRACK
SERVO
HEAO
0181T
-----
:
:
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......J
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+-___-oj.I ORI OOO+EVEN 0181TS
iI
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NOTES:
CD
P-CHANNEL FET TURNED ON (40 Il) 8Y NEGATIVE
INPUT. SIGNALS NAMED WHEN INPUT IS NEGATIVE.
®
POSITIVE (000) 0181TS TEND TO DRIVE TRACK
SERVO SIGNAL NEGATIVE.
@
NEGATIVE (EVEN) 0181TS TEND TO DRIVE TRACK
SERVO SIGNAL POSITIVE.
@
TRACK SERVO SIGNAL IS ZERO WHEN .... PLITUDES
OF POSITIVE AND NEGATIVE 0181TS ARE EQUAL.
5
SYMBOLOGY:
-.q- IIOUIIBIT
WHEN INPUT IS LOW.
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---~~,@
Dr/
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GATE I
SUMMING POINT OF OPERATIONAL .... PLIFER.
~ OUTPUT IS INVERSION OF INPUT.
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....
Figure 3-19 •
Track Servo Circuit Simplified Schematic
.......... ~ .. ,,~,'
..
~----LEAVING ODD (+1 DIBIT TRACK-------IIII
r--
r - O N CYLINDER-;
APPROACHING EVEN
DIBIT TRACK
(-1---1
-DIBIT
+DIBIT
NEGATIVE GATE
A251B
,,""-
\...
POSITIVE GATE
A2517
POS!TI''', DELAY
lC: _,jl
NEGATIVE DELAY
x2502
ODD DIBITS
K2500
f\lEN DIRIT5
______________~r__l~__________~r__l~___________~r__l~__________~r___
K 1000 "P")
LOAD
LATCH
--!J-r--15I
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SE-C
~I-----------------------------------------------------I
CDF~PROX 10 SEC
____---'I~
1I1917)
FORWARD CARRIAGE .. OTION
_ _ _ _---S~-11
OILAY ( X 2900 I
EVEN 01 IITS DETECTEOYlL......_.!..-_ _ _ _ _ _ __
"
~~----------I LT"ACK 0
FINE POSITION SIGNAL (A2605)
FINE
FF
ON
CVLINOE" DELAY (X3100)
ON
CVLINOER
f.- 1.711 WS -=I
NOTES:
(j)
(l)
RET"ACT RELAY K5 PICKED WHEN K2 PICKS.
LOAD ff CAUSES LOA 0 GATE ( Alt QI) TO APPLY +
(SEEK fWD) VOLTAGE TO VOICE COIL SU .... ING A.. PL.
COAIISE AND 'INE GATES INHIIITED. CYLINOE" "EGlSTE" I n TO ZE"O
AND Olf'ERENC' COUNTER lET TO MAXIMU .. (1023).
Q)
.. OTION TO 7 IPS PROVIDED IY LOAD GATE UNTL ODD
01 IITS SET "EVERSE EDT Ff. ..OTION CONTROL THEN
PROVIDED IV 'INE SERVO SIGNAL
Dt .ITS MUIT I ' DETECTED WITHIN 200 IllS 0" SElECT LOCK
IS 51 T. HEAD. UNLOAD. SELECT LOCK MUST BE CLEARED BEAlRE
ANOTH'" LOAD ATTEMPT CAN IE "ADE.
(!)
aW29B
Figure 3-24.
3-50
C~
First Seek Timing Diagram
83313200
A
When the Reverse EaT area (all odd, or positive, dibits) is sensed, the Load latch is
cleared and the Fine gate is enabled. The
carriage now servoes into cylinder 000 under
control of the fine servo signal.
When the positioner reaches cylinder 000, On
Cylinder is generated. After a 1.75 ms
delay, the On Cylinder FF sets. This has
the following effects:
1.
Unit Ready FF sets. It can be
cleared only when the heads unload.
2.
The Attention FF is set by Unit
Ready, assuming a Logical Address
Plug is in plac,e.
2.
a.
Bits 0 and 2 of the tag are
raised, transmitting a new
cylinder address of 160 10 ,
h.
The new cylinder address is
loaded into the Cylinder Address
register.
c.
Reset Head Address register to
zero.
d.
Reset difference counter to 1023.
Controller'issues a Transmit Head
Address Tag (Tag 7)
a.
If, for any reason, the dibit signals are
not detected by the track servo logic within
200 ms after the Load latch is set, the RTZ
latch will be set. The positioner will retract to the heads unloaded position. In
this case, a Pack Unsafe (Device Fault and
SELECT LOCK indicator on) condition exists
to prevent reloading until the Select Lock
FF is cleared. The same conditions exist if
the dibits are lost for 200 ms after Unit
Ready is available. Refer to Seek Status
and Error Conditions for other First Seek
Errors.
The bits of this byte are:
BOBO
1
2
3
4
5
6
7
Cylinder Address
Register 512
Cylinder Address
Register 256
Not used
Head Address 16
Head Address 8
Head Address 4
Head Address 2
Head Address 1
h.
Because the seek will be forward, less than 256 tracks, and
the head 1010' the tag byte will
be:
0000 1010.
c.
Bits 256 of Cylinder Address
register and difference counter
are loaded.
d.
The new head address is loaded
into the Head Address register.
DIRECT (FORWARD/REVERSE) SEEK
The Direct Seek function involves those
operations that must be performed to move
the read/write heads from their present track
or cylinder location to the one specified by
the controller.
The basic principles of the seek operation
are explained in the Servo Circuit discussion.
3.
Controller issues a Transmit Difference Tag (Tag 8) and Transmit Control
2 (Tag 10, BOB2).
a.
The difference between present
location and destination is
15010. Therefore, 15010 is
placed on the bus out to the
drive.
h.
The complement of 15010 enters
the lower eight bits of the difference counter. The contents
of the difference counter is now
72310' (See Figure 3-25).
I/O Sequencing
Controller/drive signal interchanges during
a seek function from cylinder 10 to cylinder
160 would be as follows (see Figures 3-25
and 3-26).
NOTE
Except as specified below, the
actual sequence may be varied without affecting drive operations.
This is a typical sequence.
1.
Controller issues a Transmit Cylinder Address Tag (Tag 6).
83313200
A
4.
Controller issues Seek Start command (Tag 9, BOB3).
5.
Drive decodes the command and, as
long as there is not a Fault, proceeds to execute the seek. The Seek
Forward FF, Forward FF and Seek FF
are set.
3-51
w
I
U1
IV
B )(SHEET 2)
OJ
W
W
I-'
W
8Y23
IV
o
o
Figure 3-25.
;x:.
()
Direct Seek Flow Chart (Sheet 1 of 2)
i
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)
c)
o
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t
....
ex>
w
w
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N
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o
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DETECTION CIRCUITS USE POSITION SIGNALS
TO DERIVE
TRACK PULSES
(AND FINE SERVO
SIGNAL, NOT
USED UNT IL
Te 112)
HEAD MOTION _ _
DATA
TRACKS
157
1~8
1~9
160
:
I
I
I
ODD : EVEN
I
SERVO
D1
BITS
TRACK
SE RVO
I
I
ODD
I
EVEN
161
I I
--t---~
---
--
I
I
I
FINE
--~~..r--
SERVO
---
-_7
--
-
---VELOCITY
XDCR
CNT R
I
SI~~ALS
THESE
SUMMED
CONTROL
MOTION
I
I
~
1022
DlfF
1---
1023
8W24-2A
w
I
111
W
Figure 3-25.
Direct Seek Flow Chart (Sheet 2 of 2)
W
I
U1
~
TAGS
TRANSMIT
CYL
ADDRESS
V
BUS OUT
l28
signal from the Difference counter.
Receipt
of the Seek Start signal also caused a Start
Seek signal to occur. Start Seek clears the
Fine FF, so the output of the desired velocity function generator is gated through
the coarse gate to the summing amplifier.
Since the carriage is stationary, no velocity
signal exists to balance the position error,
and forward motion of the positioner begins.
with the position error signal clamped at
maximum, the power amplifier output (and
voice coil positioner current) will be maximum and the positioner will continue to accelerate. As the positioner moves forward,
outputs from the track servo head are processed to derive a cylinder pulse as each
cylinder is crossed. Each pulse increases
the content of the difference counter by
one. As acceleration continues, the velocity signal opposes the position error
signal by an in~reasing amount. The input
to the summing amplifier drops off, finally
becoming zero when these opposing signals
are equal. With a nulled input to the summing amplifier, voice coil current is zero.
During this phase, the positioner coasts
along the 60 ips plateau with the power
amplifier providing only enough output voltage to compensate for the back emf of the
moving voice coil positioner.
When the tracks remaining in the seek become less than 128 tracks-to-go, the D/A
clamp is disabled for the remainder of the
seek (except the last track). As each track
is crossed, the D/A converter output steps
down by a precise and linear amount.
So
that the position error provided at the desired velocity function generator input is
not also stepped, the integrator clamp gates
the velocity integrator on between each
cylinder pulse. The resulting integrator
sawtooth output is added to the D/A converter output. This removes the step and provides a nearly smooth curve. As the fX)sition
error decreases, the summing amplifier control
signal decelerates the positioner to keep
the velocity signal/position error signal
difference to zero.
3-55
When the counter indicates one track to go
to the desired destination (counter=1022)
the integrated velocity signal is reset by
the regular cylinder pulse. The integrated'
velocity, which indicates diptance, brings
up fine ·enable when about one-half track of
travel remains. This sets the Fine FF which,
in turn, clears the Coarse FF.
Desired velocity no longer has an effect;
the position error is supplied by the fine
servo signal. This signal is the track
servo signal from the track servo circuit.
The amplitude of the signal is proportional
to the distance between the present head
position and the desired cylinder.
Since the desired destination is track 160,
bit 20 of the Cylinder Address register is
110 11 • This caused the Odd Cyl FF to be
cleared at the start of the seek. As a
result, the track servo signal is inverted
to form the fine servo signal.
In all seeks,
the fine servo signal is phased. to be opposite to the velocity signal. Since, for
forward seeks, the velocity signal is positive-going from.a negative value toward zero,
fine servo must be negative-going toward
zero so that these two signals can oppose
each other.
.
The dibit pattern causes a track servo signal to have a positive slope while approaching an even-numbered cylinder. Therefore,
the track servo signal must be inverted to
serve as a usable fine servo (position error)
signal.
If the seek had been to an odd
cylinder, Odd Cyl would have been set and
the track servo signal would not have been
inverted. As the positioner approaches
track 160, the fine servo signal approaches
Ov.
The summing amplifier responds to this
decrease in amplitude by decelerating the
positioner so that the sum of the velocity
and position error equal zero and all motion
stops with the servo circuit at null.
With the Fine FF set, the On Cylinder detection circuit is enabled. It receives the
analog signal from the fine servo amplifier.
When fine servo is less than about 0.3v, the
read/write heads are about 0.0003-inch from
nominal data track centerline and On Cylinder Enable comes up.
If the 4.75 ms delay
initiated at the start of the seek has timed
out, the 1.75 ms On Cylinder delay is triggered. When it times out, the On Cylinder
FF sets and the heads are selected again to
permit Read/Write operations.
since the positioner is not locked by a mechanical mechanism, the servo circuit continues to be enabled following the seek. If
the positioner should drift slightly, the
track servo signal increases. This signal
(fine servo), becomes a position error input
to the summing amplifier. This drives the
positioner back into place.
3-56
Reverse seeks function in an identical manner, except that all phases and polarities
are reversed. Total seek times for forward
and reverse seeks are identical for seeks of
equivalent lengths.
During a Direct Seek operation as during the
First Seek operation already considered, a
Monitor Mode FF is set.
In this case it is
the Monitor Mode 2 FF;
set by the Start
Seek pulse. As the operation continues,State
FFs associated with certain events must be
set in order.
If a State FF is not set or
is set out of order, the Device Check FF is
set.
RETURN TO ZERO SEEK (RTZS)
The RTZS function is a Seek where the heads
are repositioned at Cylinder 000. This
function is commanded when the controller
issues a Transmit Control I Tag along with
bit 4 (Rezero Start). See Figures 3-27 and
3-28 for RTZS timing.
The RTZS pulse sets the RTZ
the EaT Seek Error and Seek
This enables the RTZ gate;
age forces an average 7 ips
of the carriage.
latch and clears
Incomplete FF's.
this bias voltreverse motion
When the carriage passes cylinder 000, no
more even dibits are detected. This is the
Reverse EaT area. The lack of even dibits
inhibits cylinder pulses allowing the velocity integrator in the track servo circuit to
reach a negative output in excess of 1.28v.
This sets the Reverse EaT FF.
The integrator
is reset, but reverse motion.continues unimpeded.
After an additional reverse motion of about
two to four tracks, the velocity integrator
output again exceeds 1.28v. The RTZ latch
is cleared while the Load latch sets. The
logic now functions in a manner equivalent
to the First Seek sequence.
With the Load latch set, the Load gate supplies a voltage to command a 7 ips forward
motion. The velocity integrator, this time
indicating forward distance, clears the Load
latch to permit continued motion under control of the fine servo signal. The carriage
then servoes into cylinder 000.
On Cylinder is available 1.75 ms after the
RTZS is completed. The sequence must be
completed within 500 ms after RTZS initiation,
or else Seek Error is set.
The RTZS function is also used during normal
power off sequencing. When the operator
presses the START switch, the control interlock opens. This raises the Unload Heads
signal in the drive logic. The RTZ latch
sets to initiate a 7 ips reverse seek. This
83313200
A
n
o
(---j
\,,,___6''/
co
w
w
......
W
t\J
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BY24
W
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Figure 3-27.
RTZS Flow Chart
('
RTZ
"-_./
~~--------------------------------------
RTZ (TAG 9 ,BUSS OUT
BIT 4)
~~CD~'~------~: ~~~----------~~
'LATCH
TURN AROUND
_________________________________________
--4 I-1 1
CARRIAGE
FWD - - - ----._______________________:1
MOTION
REV
VELOCITY INTEGRATOR
~_
r----. - - - - - - - '. . .------------_____
~
I
(A2900)
I
CYLINDE R
/
~
REV -7 IPS
I
I
:
I
i
:
I
I
~
~---------------(j)
cn
o
1
I
PULSES
I
REV
FWD
J
EOT
ENABLE
(A2904)
EOT
ENABLE
(A2903)
REVERSE
EOT
FF
~~----~ur____lU~--------------------------------------------
------------~J ~~--------------~~----------------------------U
~~-------------------------
----------------~I .~p----~
I
I
REVE RSE
EOT PULSE
(X 290 I)
r
r
----------------~~ ~
40p.S~
I
1·--------------------------------------------I
--------------~J ~r----~
K 2903
1
___________________________________
I
LOAD
LATCH
________________________________________
~~---------------------~
FINE FF
FINE
1
r---1~
SERVO
SIGNAL
( A 2605 I
~"'r------
-JVV I
I
ON CYLINDER DELAY
'cn
:
®:
CYL 0
0
--------------~I j~------------------------------~r_ 175MS=j~-----------
( X 3100)
ON cYLINDER
~~------------~: 1~--------------------------------------------------4
NOTES:
CYLINDER
~
~
·REVERSE
PULSES
EOT
FF
RESTART
VELOCITY
CLEARED
BY
INTEGRATOR.
FIRST
EVEN
(1023).
(AUQ!) __ IT PROVIDES + (SEEK FWD)
MOTION CONTROL PROVIDED BY FINE
SERVO
THEY DO
NOT AFFECT
DIFFERENCE
DI BITS. (APPROACHING TRACK
SIQNAL.
COUNTER.
0).
ASSUMES 4.75 MS DELAY HAS TIMED OUT.
8YI3
Figure 3-28.
3-58
RTZS Timing Diagram
83313200
A
time however, the EaT Enable circuit is disabled so that the EaT integrator signal has
no effect.
In turn, the Load latch is disabled.
Reverse motion continues until the
heads unload. A Select Lock condition does
not inhibit the unloading; however, unloading does not clear the SELECT LOCK indicator.
The RTZS function occurs automatically in
the heads unloaded condition if dibits are
lost for more than 200 ms. The Select Lock
FF is set to prevent another First Seek until
the SELECT LOCK indicator has been cleared.
MACHINE CLOCK CIRCUIT
The machine clock
ated by the track
the basic 806 kHz
is applied to the
circuit uses dibits generservo circuit to generate
clock signal. This signal
following circuits:
1.
Index detection
2.
Write clock generator
3.
Sector counter
310 NSEC
(
, JL
",L..-__
....
"---./)
r
There are three inputs to the comparator.
One is the normal input from dibits delayed
approximately 1/4 cell and shaped to 30 nsec
(approximate) pulses. The second input is a
dub-in input. This is a 30 nsec pulse coming up at the same time as the normal input
but from the clock output. The third input
r------,
ll-----'D;;......A'-'-TA--.._ _~ Fb~~T~GI'I--...;...IN...;...P..;;..UT~_ _---, I
LOOK NETWORK
a..-.;I--!I.....C-,O_M_PA_R_A_T..,OR
AHEAD
I lOR
PULSE
I
,..----;l~ 13309/
I 'I r _____I JJ__IN:2"~R~ ~l
FIRST SEEK
I I 0...r-L
_ _ _ _-+'-A~,
REVERSE EOT
The circuits (Figure 3-29) most important
portion is a phase locked loop (PLL). The
loop compares the frequency of input data
. (dibits) with feedback data. A comparator
circuit generates a square wave input to a
GJK circuit in the voltage controlled oscillator.
(Refer to Section 6 for an explanation of the GJK circuit.) The GJK generates
a voltage proportional to the difference in
frequency between input data and feedback
data. The output of the GJK is applied to
the voltage controlled oscillator to control
its frequency. The PLL is satisfied when
the input and feedback frequencies are
identical. Note that data and feedback are
90 degrees out of phase.
NORMAL
-.l'
OOITS
Clock Generation
DUB-IN
INHIBIT PULSE
PULSE
FORMING
A
R
I
I
ON CYLINDER
AFTER FORWARD OR
REVERSE SEEK ERROR
rl
I
r,--------...J
/o~~~~G
DUB N :
I
INPUT
I
3310
-
___r-.J_I_~_ _-,~
',t--__R_E_SE_T_____....
NETWORK
-
r--
~~----4--------------._-----------,1
I
VOLTAGE CONTROLLED
OSCILLATOR
+2
ILfL
155 NSEC
J
Il
...r-L
806 K Hz
PULSES
I
~------------+-~----------------CLOCK
GJK / MAH
-----~1101~--------~--------------CLOCK
----1LSL
JLJLJUL.j
L.JL.r
I
I. 612 MHz
I
L - 806
- -K HZ- - - - - _____________________
.J
r--------,
I PHASE LOCKED I
LOOP
L-------I
8078
Figure 3-29.
83313200
A
Machine Clock Circuit
3-59
is the reset pulse.
It is the normal and
the reset input which provide the basis for
normal comparator operation.
During normal operation, a look-ahead pulse
blocks the dub-in input to the comparator.
This insures that the comparator and therefore the clock, tracks with the real input
data from dibits. However, if dibits are
missing, as they are during the Index mark
(for two cells) or during a seek (every
other cell), there must be a pseudo-dibit or
dub-in pulse to keep the clock in phase.
Therefore, the circuit is self-ringing when
data is not present at the input.
A problem with the self-ringing feature of
the circuit is that, if the first input to
the comparator is not data but a dub-in
pulse, the circuit may not be in synchronizat~on with real data when it is received.
It
would then take some time before synchronization could be attained. The 5 ms dub-in
inhibit pulse fires to block dub-in pulses
in three situations: 1) when the latch is
cleared by reverse EaT at the end tif a first
seek, or 2) and 3) when On Cylinder is received after a forward or reverse seek error.
After the heads are loaded, even/odd dibits
are available. Their nominal frequency is
806 kHz. The actual frequency is a function
of spindle motor speed. The PLL quickly
synchronizes itself to the actual dibit rate.
This permits the clock to react to variations
in spindle speed between drives. Signals
derived from this circuit, such as sectors,
are a function of actual spindle speed
rather than functions of an absolute time
base.
FF K3301 is connected as a divide-by-two
circuit. This circuit arrangement permits
the PLL feedback to be a function of negative-going edges of the PLL output. Therefore, PLL unsymetrical outputs are ignored
and the basic frequency is the controlling
factor.
The PLL output frequency is nominally 1.612 MHz.
Index Detection Circuit
The Index Detection circuit (Figure 3-30)
generates a 2-~sec pulse at the start of
each new logical track. This signal is returned to the controller as Index (BI Bit 5)
and also resets the sector counter to zero.
Prior to reaching the Index area, both even
and odd dibits are available. Dibits Present FF (K340l) is held in the preset state:
this causes the counter to be continually
loaded with zero with each clock pulse from
X3400. The counter can continue to increment only if the precise pattern continues
to be sensed. Any other combination of
missing dibits (such as when tracks are
crossed during seeks) will cause the counter
to be reset to zero.
3-60
When the counter reaches a decoded value of
550, two of the three input gates to Index
Detect FF K3402 are available. The next
even dibit triggers X3400 to set the FF. In
turn, X340l provides a 2-~sec Index pulse.
r---·
(
......./.
'\
Note that Index is inhibited while the heads
are over either a forward or reverse EOT
area.
Index Error Detection
The Index signal must appear between count
50 of the last sector (127) and count 4 of
the first sector (000).
If the Index pulse
is not detected at this time, the Index
Error FF will set. Refer to Figure 3-31.
During normal operation, the Not Index Window
FF receives gating pulses at ~ach sector
count of 4 and 50. The FF does not toggle
however, until sector 127. When sector 127
is reached, count 50 clears the FF. The
next count 4 (sector 000) sets the FF. During the time the FF is cleared, the Index
pulse will be received. The Index pulse,
combined with the clear output of the Not
Index Window FF, sets ·the Index Detected FF.
The next count 23 resets the Index Detected
FF.
If Index is received when the Not Index
Window FF is set (an error condition) it
enables a gate to the Index Error FF and
force sets it. On the other hand, if no
Index pulse is received when the Not Index
Window is cleared, the Index Error FF is set.
An Index Error raises Bus In, Bit 0 if Tags
4 or 9 are decoded.
(
'-...
Sector Circuit
The sector circuit (Figure 3-32) permits the
controller to determine the current angular
position (sector) of the read/write heads
with respect to Index. The circuit may also
be used to set up an Interrupt signal when
a sector requested by the controller is
reached. Each track may be considered as
subdivided into 128 segments. They are numbered from 000 to 127. Sector 000 is the
first sector following Index.
The circuit consists of three major elements:
1.
A Clock Counter to count even dibits.
2.
A Sector Counter that maintains a
continuous count of the current
sector.
3.
A Sector register used to supply
Record Ready Interrupt or to provide
the controller with the current
sector count.
C~
83313200
A
-l
ODD
+ EVEN
806 KHZ
CD EVEN
/--600 NS
1
t'I'------- INDEX
PATTE RN
--------1'1
DI BITS
CLOCK
01 BITS
(K3400)
01 BITS PRESENT (K3401)
RESET
COUNTER (W3400)
DE CODE
(H3400-1+3+4)
INDEX
DET (K3402)
!--0--..-l.1
2
0
3
4
5
6
®
INDEX (X3401)
r-ENABLE..j
_________________________________________________~~
~~S
NOTES:
('\
v
CD
X INDICATES
®
NEXT LEADING EDGE REQUIRED TO SET
PROPAGATION TIME THRU H3400/ K 3402
LEADI N G EDGE OF SIN GLE
SHOT X 3400
FF
BECAUSE
OF
ODD + EVEN
01 BITS
806 KHZ
A
~-------+---~
INDEX
A
4
INCREMENT
INDEX
2
REV
EOT
FWD
EOT
Figure 3-30.
80548
Index Detection Circuit
o
83313200
A
3-61
r',
I, .......
INDEX WINDOW
INDEX
WINDOW
A
INDEX
COUNT 4
INDEX
DETECTED
FF
K3403
SECT 127
A
COUNT 50
FF
K3404
COUNT 23
INDEX ERROR
INDEX---------------------4----~
I
INDEX
SECTOR 127
SECTOR 000
50
4
23
50
v
v
V
SECTOR 001
V
50/4 FF
__________~r__l~______~r__l~_________
INDEX WINDOW FF
7T//?7~ff//7/,/7/J777//T//,Q)
®
INDEX DETECTED FF
~-------I
NOTES:
IF AN INDEX PULSE OCCURS WHEN INDEX WINDOW FF IS SET,
INDEX ER ROR F F IS SET.
BOTH SIGNALS MUST BE HIGH TO PREVENT INDEX ERROR.
CD
®
8083
Figure 3-31.
Index Error Detection Circuit and Timing
The 806 kHz clock signal is used to generate
the sector count. An Index pulse sets the
Even Sector FF and partially enables the
Clock counter input. The first even clock
signal then loads the clock counter. Each
positive-going (even) clock pulse increments the clock counter. When the clock
counter counts 53 even pulses, the sector
counter is incremented by one and the clock
counter is reset. Each time the clock
counter is reset, the Even Sector FF changes
state. Note that the count loaded when an
odd sector is to be counted is one greater
than for an even sector. This is because
an odd sector has one less clock bit per
sector than does an even sector.
3-62
As the clock counter proceeds, the following
counts are important:
Count 4 - Clears the 50/4 FF and acts as a
partial enable for data input to
the Sector register.
Count 23- Sets the Hi Side Sector FF.
Count 50- Sets the 50/4 FF.
Count 53- Clears the Hi Side Sector FF,
toggles the Even Sector FF and
increments the Sector Counter.
83313200
A
,"
EVEN SECTOR
ODD SECTOR
SECTOR
PULSE
(COUNT 53)
INDEX
INDEX
RESET
OPERATE TAG
BOB7
SECTOR
COUNTER
HI SIDE
SECTOR FF
- , ~600 NSEC
CNT 50/4 FF
SAVE SECTOR(D---,L--_ _ _ _ _ _---Jr---,L--_ _ __
Lr--
~EX WINDOW
~ ___ _
B06kHz
-.j
~2 I'SEC
--r-L
INDEX
EVENCLOCK~'"L.J"f~
INDEX
DETECTED FF
~g~~T~~
K3701®
~~~~OR
FF
NOTES:
(DWHEN LOW @SETS GATE BUS FF.
@LOADS SECTOR COUNTER CONTENTS INTO SECTOR
REGISTER AT EACH COUNT 4.
COUNTER
HI SIDE
SECTOR FF
~
---.r---,
fJ--lf
--.J
fJ--l.F-'- - - - - - - - i . . .____
I
I
I
I
I
I
I
SET TO
1100 1101
CNT
2
CNT
3
CNT
4
eNT
eNT
eNT
2Fi.F-'---.:!5:..:0~_5::.:1_
------------I;~
I
I
eNT
CNT
__:5:::.2_-=;53
I
SET TO
1100 1100
L - I-
-
-
-
©ENABLES HI SIDE SECTOR REGISTER.
® ~~~i~~L~01~~N5ri: ~~yD~~A T~I~s~~~~~~ ~~E~S1i~~~ES:ViHE
SECTOR
PULSE
COUNTS OF 4 AND 50 WHEN THE SAVE SECTOR SIGNAL IS PRESENT.
BDBIA
Figure 3-32.
The Sector counter continues to count until
reset by an Index signal. When enabled, the
contents of the Sector counter is transferred
to the Sector register. To load the Sector
register from the Sector counter, the unit
must receive Tag 11 BOB7 (Save Sector). The
next count 4 of the clock counter will load
Sector counter contents into the Sector
register. From then on, the register is
continually updated by the Sector counter
until the next Tag 1.
Data may also be placed in the Sector register directly from the counter. Tag 1 BOBl-7
loads a sector count directly into the Sector
register. After the controller loads the
Sector register, a compare circuit compares
83313200
A
Sector Circuit
the output of the Sector counter and the contents of the Sector register. When a match
occurs, a Record Ready signal is generated
if the following additional conditions are
met:
1.
Record Search in Progress FF set.
2.
Tag 1 (Transmit Sector) low.
3.
On Cylinder.
4.
Neither an Index nor a Sector Pulse
may be present.
A Record Ready signal drops the Busy signal
and generates an Interrupt when the device is pJlled.
3-63
SENSE OPERATIONS
Sense operations permit the controller to
determine drive status.
Device Check
Refer to simplified logic (Figure 3-33). The
Device Check logic signals the controller by
raising the Device Check line if any of the
following error conditions occur:
1.
The controller commands a Seek op'eration when a Seek operation is
illegal.
Refer to Seek operations.
2.
The controller commands Head Advance
at end of cylinder or a Write operation during an Offset or a Not Tag
11. Valid signal is received from
the Fault Detection circuit.
3.
Any of the Monitor Check signals
(refer to Maintenance Monitor) •
4.
A Test Logic signal (Tag 12,BOB6)
forces a Device Check signal.
5.
Select Lock or Interface Check
signals besides raising their own
identifying bits, also set the
Device Check FF.
Monitor mode error detection is accomplished
in two ways. State FFs set out of sequence
or skipped in sequence are detected as state
errors and raise the Monitor Check signal
immediately. However, if the State FFs are
set in order but for some reason one or more
of the State FFs is not set, the Monitor
Check signal is not raised immediately. The
signal will be raised in the seek operations
when On Cylinder is detected.
In the Read
or write operations, Monitor Check is raised
at the end of the operation, when the Operate (Tag 11) line drops.
Clearing the
Monitor Check FF raises the Monitor Check
signal, raises the Device Check signal, and
holds the Mode and State FF's in their last
state.
A Spike Detect signal from the Desired Velocity circuit during a Direct Seek operation is immediately detected as an error.
During a Write operation, State 4 through 8
FFs are set by error conditions rather than
normal operation. The errors detected are:
1.
Write and Offset Active both
selected (State 4)
2.
An AC Write Fault (State 5)
3.
Simultaneous Read and Write (State
6)
4.
Write selected AND (Not On Cylinder
OR Not Head Selected OR EOC)
(state 7)
5.
A Multiple Head Select or Current
Fault (State 8)
One and two above also raises the Command
Reject line to the controller. '
Maintenance Monitor
Three of the seek operations we have considered, First Seek, Direct Seek, and Return
to Zero Seek, are monitored during their
normal operation by the Maintenance Monitor
circuitry.
Besides the three seek Monitor
Modes, both the Read and Write operations
are monitored.
The operation of all Monitor Modes is basically the same. At the beginning of the
monitored operation, the Mode FF or FFs are
set by the internal logic signal which begins
the operation. Mode FFs can also be set by
commands from the controller as part of a
diagnostic procedure.
Once set, the Monitor
Mode FFs act· as enables to the Monitor State
latches. Thereafter, each event during the
operation sets the appropriate State FF.
Refer to the Seek flow charts for examples.
Assuming all events progress normally, at
the end of the operation all State FFs associated with the operation mode are set.
The final event of the operation (Seek Complete for Seek operations, not read for read
operations and not write for write operations)
sets the Mode/State Reset FF and clears all
Mode and State FFs.
3-64
Five above is also detected as an error during a Read Monitor operation.
DIAGNOSTICS
The Diagnostic circuitry allows maintenance
personnel to check out key portions of the
drive logic.
State diagnostics check servo
loop operation with only simulated drive
commands and no actual carriage or disk
motion.
Dynamic diagnostics monitor drive
during normal on-line operation. The application of drive diagnostic functions is
entirely a function of microprogram firmware/software and is described by the microprogram description in the controller manual.
Static Diagnostics
Drive is powered down. The Unload Heads
signal is inhibited and a false On Cylinder
Status is set. Now either a direct or RTZ
seek may be simulated by a series of enabling
signals from the controller. These enabling
signals call for the servo loop to respond
83313200
A
c
(-'\
()
.. ,
_-,J
OJ
W
W
I-'
OFFSET
W
SEEK INC
I\J
a
o
START SEEK
FF
!l:>O
CONTROL
RESET ETC
ON CYl
( 14023)
DR
SE"Ei(INc
DEVICE CHK
SERVO
DIAG I
CMD
REJECT
ON LINE
COMMAND REJECT
C O M M A N D I t - - - - , , - - - - - - - - TO
REJECT
SEEK INC
liD
FF
TAG 10
OFFSET
RESET
OFFSET
START
A
CONTROL
RESET
BOB7
TAG 9
INTERFACE
CHECK
BOB2
DEVICE CHECK
DEVICE
CHECK
FF
TAG II VALID
(SEE SELECT lOCK)
READ/WRITE
TAG II REJECT
SELECT lOCK
TO I/O
CMD REJECT
CONTROL
RESET
ON CYLINDER
DIAG I
TAG II
SELECTED
MODE I, 2 OR 4
ON
TAG
II
VALID
MONITOR
CHECK
cn
MODE 6 OR 7
OR
MODE/STATE RESET
STATE ERROR
(STATE FF NOT
IN SEQUENCE)
DIAG 4
TAG 12
I TEST
lOGIC
• RAISE
BOB6
I
U1
TO I/O
8YI2A
W
m
TAG VALID
Figure 3-33.
Device Check Logic
to portions of the seek routines as if normal motion were taking place. The Monitor
Mode logic is operative as a normal operations and successful completion of each
portion of the simulated seek is indicated
by setting the applicable State FF.
2.
Enables Read Gate Lock up.
Normally the Read Gate is
dropped each time the Head Select
signal is dropped. Selecting
Diagnostic 4 however, holds the
Read Gate high. This lockup
mode is cleared by applying an
AM Search signal or clearing
Diagnostic Mode 4.
Dynamic Diagnostics
Dynamic diagnostics differ from Static diagnostics in that there is drive motion. By
application of pertinent commands (Request
Diagnostic Sense, Tag 12) drive status may
be monitored. Also, errors can be intentionally introduced (for example, simultaneous Read and write commands) to ensure correct response of error detection circuits.
The following flow charts (Figure 3-34 and
3-35) cover one basic diagnostic procedure.
Note their dependence on controller commands.
For this reason these flow charts should be
used as guides only. Specific information
regarding diagnostic procedures will be found
in the controller manual.
BASIC READ/WRITE PRINCIPLES
Diagnostic Entry
Introduction
The Diagnostic mode is set by Tag 13 from
the controller. One or more of three latches
can be set with this command. Each of the
latches enables or inhibits certain'events
to allow illegal commands or events to take
place. The latches and their associated
events are:
•
•
Diagnostic 1 (Tag 13 BOB3)
l.
Inhibits set input to Cylinder
Address register.
2.
Inhibits set input to Difference
counter.
3.
Inhibits the set input to the
Head Address register.
4.
Inhibits any operation prefaced
by Tag 11.
Diagnostic 2 (Tag 13 BOB2)
1.
2.
Enables Static Diagnostics by
making the Request Status bits
(Tag 4) significant.
3.
Enables a multiple head fault by
selecting two heads when a head
address greater than 18 is
selected.
4.
•
Enables a loss of dibits causing
the heads to react and setting
the Select Lock FF when combined
with Tag 4, BOB6.
Diagnostic 4
1.
3-66
Partially inhibits Servo Command Reject.
Forces an index error condition
by presetting a count of 8 into
the dibit counter. This causes
Index Window to be generated
approximately 1.4 sectors prior
to actual Index.
Information is recorded on, and read from,
the disk pack by means of 19 heads. Each
head contains a read/write coil.
Writing Data
I
Data is written by passing a current through
a read/write coil within the selected head.
This generates a flux field across the gap
in the head (Figure 3-36). The flux field
magnetizes the iron oxide particles bound to
the disk surface. Each particle is then the
equivalent of a miniature bar magnet with a
North pole and a South pole. The writing
process orients the poles to permanently
store the direction of the flux field as the
oxide passes beneath the head. The direction
of the flux field is a function of Write
current polarity while its amplitude depends
upon the amount of current: the greater the
current, the more oxide particles are
affected to the point of saturation.
(
',-.
Information (data) is written by reversing
the current through the head. This change
in current polarity switches the direction
of the flux field across the gap. The flux
change defines a data bit.
Reading Data
As the disk passes beneath the read/write
head, the stored flux intersects the gap
(Figure 3-37). Gap motion through the flux
induces a voltage in the head windings. This
voltage is analyzed by the read circuit to
define the data recorded on the disk.
Each flux reversal (caused by a current
polarity change while writing) generates a
readback voltage pulse. Each pulse,in turn,
represents a data bit.
C~
83313200
A
o
n
C)
',---/
00
w
w
.....
W
CONTROLLER
RAISES
TAG 3.
START
SWITCH
OFF
N
o
o
BUS OUT
BIT 3
SERVICE
DRIVE
SELECTED
A
~
r------,
:
I
CONTROL
RESET
L ______
I
JI
I
I
SJt~I~~
I
I _______
BITS I AND 2 OFF..JI
L
CONTROLLER
RAISES
TAG 4.
BUS OUT
BIT 6
---l
CHECK
I
DIAG
MODE
2
I
L _______ .J
CONTROLLER
RAISES TAGIO.
BUS OUT
BIT I OFF
OlffERENCE
COlJ'lTER
BITS 12B
THRU
I SET TO ZERO
INHIBIT
UNLOAD
HEADS
SIMULATE
HEADS
L040ED
SIGNAL
SIMULATE
FIRST SEEK
INTERLOCK DELAY
TO INHIBIT
LOAD FF
GENERATE
FINE
ENABLE
GENERATE
ATTENTION
i~E~-;I~~i
r-- ----I
I
!
BEJU~L;EAOS
I
L_A~E~T~~
I
I
I
I
L
~E~V~Rlf'CO:
I
FOLLOWING MODE I
______ J
GO TO
VERIFY DIFF
CNTR = 0
L _______
J
APPLICABLE
STATIC
DIAGNOSTIC
FLOW CHART
I
r-------l
~D~I~~
r -- -- ----,
I
I
I
BITS:3 AND4
L __ ..:'N___ J
I
I
\~fu';'~~
:3d~ AND 5
L ______
:
BITS
I
I
J
w
I
en
~
Figure 3-34.
Static Diagnostics Entry Flow Chart
BY25
w
I
m
co
DIFFERENCE COUNTE
r--
T~f~~~t~rE~CE
I
SET TO INOICATE
r
VERFY
BUS IN BITS
I
I
I
L _____ ...J
IS SET TO 000)
FORWARD SEEK
DIRECTION SET
I
I
r-----.I
I
VERIFY
T=I023
VERIFY BUS
IN BITS
2AN06ON
L ______
..JI
1
L_ ~A~5': _
r- I
VERIFY
I
5~~~:1;~ I
L _____ ...J
I
--l
B't~~~1IT
L__ ~O:_
I
I
--.J
r-I
I
L
SIMULATES
CONSTANT
VELOCITY
I
(~ ~C~E:'E~T~
8Y26-1
co
w
W
I-'
W
N
o
o
Figure 3-35.
:J::I
n
Static Diagnostic Flow Chart (Sheet 1 of 2)
/---)
(-\
,
)
o
r-\)
()
\
(XI
w
w
.....
W
I\J
o
o
!t>'
r----j
I
I
DECREMENT
DIFFERENCE
COUNTER
L _____
.JI
---,
---1
I
SET T= 0
L
I
_ _ _ _ _ ..J
,
VERIFY
BUS IN BITS
0-7 OFF
L ______
VERIFY
.J
---,
r -~E;;'Y_;;S_;;;: -
..,
THIS ENSURES THAT I
~ CYLINDER DELAY IS ATI
IL LEAST
_ _ 1.4MSFROMTSI
_ _ _ _ --JI
13 CFF.
I
BIT 3 ON
L ______
I
I
.J
B~s:FaIT
---,
I
I
L _____ .J
VERIFY
BUS IN
BIT4~
I
L.... _ _ _
I
I
~_...J
VERIFY
BUS IN BITS
I
I
I
1.. ~~HR~7~_J
r-I
I
BUg~~BlTS
L ______
I
J
L
BY26-2
W
I
0'1
~
Figure 3-35.
static Diagnostics Flow Chart (Sheet 2 of 2)
WRITE CURRENT
CURRENT
MAGNETIC FLUX
o/FLOW
FLOW~
MAGNETIC COATING
~RECORDING
0'
HEAD
:;::;
/~---~,g.:--"i$C~""'!N~~t
,. t
f
UU
SURFACE MOTION
NOTE: RELATIVE HEAD TO SURFACE MOTION, RECORDING (WRITE OPERATION)
Figure 3-36.
W
~ dJ
7S17A
Writing Data
- - - - - - R E A D BACK SIGNAL
~~
.tJ===~Gf:=~H::a:G~J:$=:=:SJ
~-READCURRENT
~ dJ
~~
\ ~ L.:
FLOW
\
SURFACE MOTION
NOTE: RELATIVE HEAD TO SURFACE MOTION, REPRODUCING (READ OPERATION)
7SIBA
Figure 3-37.
3-70
Reading Data
83313200
A
o
Track Format
PrinCiples of MFM Recording
Each track has Index as its starting point.
The track is further subdivided into 128
sectors. Sector 00 is the first sector
following Index. Index and On Sector signals
are available to the controller. For further
information, refer to the Direct (Forward/
Reverse) Seek theory in this section.
In order to define the binary digits stored
on the pack, the frequency of the flux reversals must be carefully controlled. Several
recording methods are available; each has
its advantages and disadvantages. This unit
uses the Modified Frequency Modulation technique.
One track is operated upon by one read/write
head. The heads are numbered from 0 to 18.
These heads are positioned vertically with
respect to each other. As a result, all 19
of the heads may be useQ without moving the
actuator. Since any of the heads may be
addressed at practically instantaneous rates,
the recording medium may be thought of as a
cylinder rather than as 19 discrete surfaces.
This is the cylinder concept. Since the
actuator may be positioned horizontally to
anyone of 823 rings or tracks, there are
823 cylinders. They are numbered from 000
(the cylinder· nearest the outside edge of
the disk) to 822 (the innermost cylinder).
Any track may be addressed by seeking to the
desired cylinder and by selecting one head.
Only one head may be selected at a time.
The length of time required to define one
bit of information is the cell. Each cell
is nominally 155 nsec in width. The data
transfer rate is, therefore, nominally 6.45
MHz.
MFM defines a "1" by writing a pulse at the
half-cell time (Figure 3-38). 'A "0" is defined by the absence of a pulse at the halfcell time. A pulse at the beginning of a
cell is Clock; however, Clock is not always
written. Clock is suppressed if there will
be a "1" in this cell or if there was a "1"
in the previous cell.
The rules for MFM recording may be surnnarized
as follows:
Track format, sector control, and data record format are functions of the operating
system. These functions are directly controlled by the controller. Refer to the
applicable controller manual for further
information.
MFM
WRITE
DATA
1+-1
~O
~p
0
1.
There is a flux transition for each
"1" bit at the time of the "1".
2.
There is a flux transition between
each pair of "0" bits.
3.
There is no flux transition between
the bits of a "10" or "01" combination.
-I"
-I
#"
O-+-I-+-
1--1
@
MFM
WRITE
®
---1
RECORDED
FLUX ~~~
..
RAW READ
DA@
· ~t .
• f~ •
·~Ii~f~~
n...___...n...____........n,"--_fL...
OUT~_ _ _ _
NOTES:
o
A.
TIMING REunVE 10 DRIVE AT
B.
SIGNAL
110
CONNECTOR.
AS IT WOULD APPEAR AT HEAD COIL.
Figure 3-38.
83313200
A
7516B
MFM Recording
3-71
The advantages and disadvantages of MFM recording are as follows:
1.
2.
3.
Fewer flux reversals are needed to
represent a given binary number be'cause there are less flux reversals
at the cell boundaries. This achieves
higher recording densities of data
without increasing the number of
flux reversals per inch.
Signal-to-noise ratio, amplitude
resolution, read chain operation,
and operation of the heads are improved by the lower recording frequency achieved because of fewer
flux reversals required for a given
binary number.
Pulse polarity has no relation to
the value of a bit without defining
the cell time along with cell polarity. This requires addxtional read/
write logic and high quality recording media to be accomplished.
READ/WRITE OPERATIONS
Introduction.
An overall block diagram of the read/write
chain is shown in Figure 3-39. More detailed
block diagrams and timing diagrams are shown
in conjunction with the discussions of the
various stages in the read/write chain.
Head Selection
The Head Selection circuit must select the
desired head before a Read or Write operation can be performed. The head selection
process is initiated by a Transmit Head Address command (Tag 7) from the controller.
This code gates the desired head address into the Head Address register (Figure 3-40).
For purposes of this discussion, assume that
head 02 is the head to be selected.
Bit 1 of the Head Address register (set by
Tag 7 BOB7) determines if the head selected
will be odd or even. Since in this example
bit 1 is off, an even head is selected. Bus
Out Bit 6 on, with BOB7 off activates Even
Heads Bit O. Assuming Head Select enable
(Tag 11, BOB3) is present, Head 02 is enabled
by applying a ground to the read/write head
center tap.
Note that if the selected head number is
decimal 19 or greater, an End of Cylinder
signal is generated. This deselects all
heads. The content of the Head Address
register can be increased by one by a Head
Advance function code (Tag 11 BOB4) from the
controller.
r-'
(
\......_ ..
READ/WRITE
HEADS
WRI TE ____
DA TA
WRITE
DRIVER
WRI TE -+
ENAB LE
4
CYL
ADDRESS
~
r-· .- 1
--.
HEAD
GATING
WRITE
CURRENT
CONTROL
~
~
AGC
PREAMPLI- f--+ AMPLIFIER
FIER
STAGE
~
~~
r-
DATA
LATCH
-
~~
-+ LEVEL
DETECTION
TO CONTROL LER
HEA D
HEAD
ADDREMS~ ADDRESS
FRO
CONTROL LER DECODING
8D77A
Figure 3-39.
3-72
Read/Write Chain Block Diagram
83313200 A
HAR
~
16
HEAD ADVANCE
HEAD SELECT
READ + WRITE
POR
19
EOC
TO I/O
HEAD
TSTR RESET HEADS
ADDRESS
CU RESET HEADS
REGISTER
SET CAR
TRANSMIT
HD ADDR TAG
ON CYL
DIAG 2. SERVO TRK
EOC
ON CYL
HEAD SELECT
AC
WRITE
FAULT
A
WRITE
SELECT LOCK
C)
®
CYL 256
CURRENT
CYL IZ8
CONTROL
CYL 512
r:------ - - - ------ ------,
IHEAD 02
I
ANALOG
C>
READ
PREAMP
I
I
EO
DATA
ENABL E
C>
®
I
:
~._G-R~O-U-N-D-=~EN-A-B-L~E--------~--r_~--~r_~~:
0
PREAMP
VHJ/VHK
14--+--+---4
I
I
I
I
I
I
I
U V
I
I _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ...l
L
HEAD 01
r - -
I HEADS
MULTIPLE
HEAD
SELECT
--I
03 - IB
I
l..r-o
.,..
L ____
READ/WRITE
I
I
SCE / SCD
I
I
.J
NOTES:
CD ~~~N~r,~~:; 51~~ ~~iA~~ A~~Tf~ ~ft~c~~Li~l· F~NfsE CiEiA~~~~VH~~ T~~ig ;it~ES~~~C~E
IS DROPPED AND AM SEARCH OR 1iiAG4 IS PRESENT.
®
G)
DECREASES WRITE CURRENT AS HEADS ARE CLOSER TO SPINDLE. CURRENT IS GREATEST AT
CYLS 0-127 AND LEAST FOR CYLS 768-822.
8W28A
EQUIVALENT CIRCUIT.
c==)
Figure 3-40.
83313200
A
Head Select and write Circuits
3-73
A multiple head select error may occur at
any time, whether reading or writing. Multiple
Head Select is sensed by the SCE/SCD circuit.
If only one ground (or no ground) is sensed,
the SCD voltage comparator output is +5v to
indicate no error. Two or more grounds
sensed through parallel dropping resistors
causes the voltage comparator circuit to
indicate the error. This generates a Current
Fault;
refer to Write Fault Detection for
further information.
Write Data Processing
A Write operation actually begins before the
voice coil positioner moves the heads to the
desired track. The Transmit Head Address
function code (Tag 7) gates the identifying
number of the head to be used into the Head
Address register (see Head Selection description). When the seek operation is completed,
the unit generates an Interrupt signal. This
places the unit logical number· on the bus in
lines when a Poll Devices tag is received.
This signal informs the controller 'that the
seek has been completed and the unit is on
cylinder and ready to receive further commands.
The controller now sends a Request Status
signal (Tag 4). After examining unit status,
the controller sends an Interrupt Reset
signal (Tag 9 BOB7) and continues its programmed operation. If conditions in the
device permit, the controller responds to an
Interrupt from the drive with an Operate
function code (Tag 11) and Head Select (Bit
3), Read Gate (Bit 6), AM Search (Bit 1) ,and
Data Enable (Bit 2). This enables the Read
circuit logic to function with the selected
head to search for an Address Mark and read
a specific record address when a write record update is desired. The address is read
from the Read Data line by the controller
and compared with the address of the desired
record.
If the address is correct, the controller drops Read and brings up Write (Tag
11 BOBS). This disables the Read circuit
and enables the Write circuit (Figure 3-41).
Timing requirements of the Bus Out lines are
a function of the controller and are specified in the controller manual.
Write data is transmitted to the unit and
applied to a differential receiver. The
write data is gated by a Write Gate signal
enabled only when the drive logic indicates
a safe write condition. The Gated write
Gate is generated when the following signals
are true: On Cylinder, Not End of Cylinder,
Write Command, Head Select and Not Write
Protect.
If Gated Write Gate is up, the
data is allowed to pass through the remainder
of the chain to the selected head and is
written on the disk.
The output of the Write Toggle FF is processed
by a symmetry restore circuit. This discrete
component circuit (QEL) restores symmetry to
the data signals that may have been lost in
the write chain. Refer to the Logic Cards
manual (see Preface) for a detailed description of this circuit.
The magnitude of the Write current flowing
in the heads is controlled as a function of
cylinder address (this is referred to as
Write Current Zoning). These zones are
divided into the following segments of tracks:
0-127, 128-255, 256-383, 384-511, 512-639,
640-767, and 768-822. Write current amplitude is reduced at each zone boundary from
outer to inner tracks.
Two fault sensing circuits have been incorporated into the write circuits. One circuit
senses the presence of any write current
flowing in the heads. The other monitors
the rate of current reversals being sent
through the head. A lack of any current reversal for 900 nsec (nominal) when Write
Gate is present, generates an AC Write Fault
status. Both fault conditions signify an
unsafe condition for writing and therefore
disable the write driver as well as set
Select Lock.
Read Data Processing
The read mode of operation is initiated by
the application of Read Gate when the desired head is selected. Any flux transitions
on the pack are then detected by the head
and converted into an analog voltage. This
analog signal (representing written data on
the pack) is amplified and applied to the
AGC Amplifier. A maximum of 30 ~sec is required from the application of read data for
the read chain to stabilize to the steady
state amplitude levels.
AGC Amplitude Stage
The analog read data is applied to a low
pass filter in the AGC amplifier stage
(Figure 3-42). This filter attenuates the
high unwanted frequencies (noise) in the
read data signal and provides a linear phase
response over the read data frequencies.
The output of the filter is applied to the
AGC amplifier (A5306). The AGC amplifier
provides a relatively constant output from
a wide amplifier range on the input. This
is accomplished by the AGC Control circuit
which varies the gain of the AGC amplifier
as the output varies.
c
3-74
83313200
A
TO CONTROLLER
DIFFRCVR
CHANNEL I
SELECT
(R7000 )
LINE t4'
DRIVER ~
(T7004) WRITE ®
- - - - - ENABLE
Q9
DIFF
RCVR
HRIT::
TOGGLE
(R52QO)
WRITE CURRENT TO
SELECTED HEAD
WRITE ENABLE
WR TE
CURRENT
CONTROL
"0"
"1"
"1"
CHANNEL I
SELECT
17005
I
T7004
®
WRITE
(®~)II
R5200
®
~JJLEE
01. . ____'
I
ENABLE~
J
J
.
_ I_ _ _ _ _ _ _ _ _ _ __
I
I ..._----.,;.--.....
J
I
VOLTAGE®,
SWITCH
I
I
~r~J:l~~----"11~
I
__________~
J
I ,....______-.
C~~~J~T @l....___'.....1
SYIS
o
Figure 3-41.
83313200
A
write Chain Timing
3-75
UAD/WRIT[
H[ADS
TO CONTROLLER
ANALOG
REA
DATA
LOW
PASS
FILTER
AGC
AM PL IFIER
t-----t~
TIME
CONSTI\NT
CONTIWL
t--.....--t~
BUFFER
DIFFERAMPLI -t---~ENTIATOR
FIER
TO
DATA
LATCH
AND
LEVEL
DETECT
A(~C
GATN
CONTIWL
8D73A
Figure 3-42.
AGC Amplified stage (Simplified Logic)
The output of the AGC amplifier is amplified
and differentiated and then applied to the
Data Latch and Level Detection circuits.
signal to reject noise and spurious pulses
in the address gap area. The only time this
output is used is during a Search Address
Mark operation.
Level Detector and Time constant Control
The Data Detector consists of a comparator
(A5404) and a retriggerab1e single shot
delay (X5402). The. reference voltage on the
comparator is a fixed dc voltage of about
-0.46v. Each time the single voltage crosses
the reference, the single shot is retriggered.
The single shot will not time out as long as
data above the fixed reference is being read.
When a gap is reached, the single shot is
retriggered by the last bit preceding the
gap, times out for 670 nsec, then changes
state to indicate an absence of data (Figure
3-43). The single shot is retriggered by
the first data bit following the gap and by
each succeeding bit, indicating that data is
again present.
The Level Detector and Time Constant Control
circuit contains an Amplitude Enable pulse
generator, a data detector to detect the
address mark gap, and a circuit to control
the time constants of the AGC amplifier and
level detector.
The output of the differentiator (Figure
3-43), is applied to a filter (A5400) which
attenuates the third harmonic of the low
frequency Read signal. This effectively
lowers the resolution of the signal.
The output of the filter is amplified and
then rectified. A capacitor is charged to
the average dc level of the rectified signal. This voltage is then applied to the
reference input of a comparator (A5402) and
the rectified signal to the other input.
When the rectified signal becomes more positive than the reference signal, the comparator switches. This produces a squarewave
output that is used as an Amplitude Enable
3-76
The Time Constant Control circuit switches
the time constants of the AGC Amplifier and
Level Detection circuits. Switching from a
short time constant to a long time constant
avoids responding to the loss of amplitude
in the address mark gap area. Figure 3-44
shows block and timing diagrams of the Time
Constant Control circuit with the address
mark gap in three different positions.
83313200
A
lIAO/'oI.1T1
HIAOS
FILTER
AND
AMPLIFIER
DATA
DETECTOR
®
RECTIFIER
@AMPLITUDE
ENABLE
PULSES
®
READ
GATE
0
TO
AGC
AMPLIFIER
25,.,.5
DELAY
(3)
OUTPUT
I~ECTI FI ER
0·
AMPLITUDE
ENABLE
PULSES _ _ _ _ _ _ _ _ _ _ _ _,
®
DATA
DETECTOR
(
--
"
~/
L -_ __
8D74A
Figure 3-43.
83313200
A
Level Detection Circuit
3-77
luo/llllT[
HUDS
\,.... ~ .. ,0
H[AD
ADORES
,,*m~LEI
FROM
670-NS
DATA--~~
DETECTOR
DELAY
CD
~----~
READ - - - 0 - - - - - 0 - - - - ; . 1 10}LS
GATE
DELAY
~==::::@
~~
25}Ls
DELAY
_ _ _ _-J
...®.;;;.9-:~ TO AMPLITUDE MONITOR
READ GATE - -.....
))
t<.
WRITE GATE-----
»)
( <.
DATA
')
CD
(.
'»)
(:»
(;0
@
leo.
U
)'}
leo.
(l)
I
10;;
n
n
10}Ls
Ll
U
~
;.1
u-
)'}
®
(1I)
LEVEL DETECT
TIME CONSTANT
0
AGC TIMECONSTANT
®
DELAYED
READ GATE
®
"c.
)'}
",c:.
~')
c.
((
U
I"
·1
25JLI
I
(SHORT)U
(LONG)
U
I
I
Ll
(SHORT)~
(LONG)
I
I
C(."l
8D75A
Figure 3-44.
3-78
("
Time Constant Control Circuit
'-
'83313200
A
The Level Detector circuit is normally in a
short time constant of 5 ~sec in order to
rapidly respond to changes in signal amplitude to maintain adequate margin in the
amplitude enable function. The 5 ~sec time
is long' enough so that the level detector
does not respond to drop outs caused by disk
surface bad spots. During the address mark
gap, the level detector is switched to a
time constant of 100 ~sec. This prevents a
shift in the comparatdr reference level so
noise in the gap area does not produce false
enable pulses.
The AGC amplifier is allowed 25 ~sec to
stabilize from the Head Select and Read Gate
transients. A head may be selected and Read
Gate can come up any time during a revolution of the disk, so it is possible that the
address mark gap could occur during the 25~sec stabilizing period.
The AGC time constant is held in the short condition for the
first 10 ~sec following Read Gate.
If a gap
occurs between 10 and 25 ~seCi the AGC amplifier is switched to a long time constant of
200 ~sec to maintain a relatively constant
gain level through the gap area.
Data Latch Circuit
(/_.•..\
.
I
'---~I
The Data Latch circuit (Figure 3-45) consists
of a low pass filter for the low resolution
channel and zero-cross detectors and pulse
generators for both the high and low resolution channels.
The Read Data from the differentiator is
applied directly to the zero-cross detector
in the high resolution channel and through
the low pass filter to the zero-cross detector in the low resolution channel. As
mentioned before, the filter lowers the
resolution of the Read signal by attenuating
the third harmonic of the signal.
83313200
A
The pulse generators (I5408 and I54l0) produce pulses for each zero-crossing of the
data. By appropriate delays, the low channel pulse (I5408) enables the K input to the
output FF (K5403) in time for the high channel pulse (I54l0) to clear it. A 50 nsec
output pulse is formed when the delayed feedback resets the FF. The leading edge of the
output pulse retains the timing of the high
resolution channel. Note that the propagation time of the various gates must be considered to enable the K input at the proper
time. Whenever the frequency of the read
back data is decreasing, there is a camels
hump in the differentiated output.
(See
Figure 3-43.) with sufficient frequency
change and high resolution heads, the differentiated signal may actually pass through
zero. The high resolution channel can react
to these extraneous zero-crossing pulses;
the low cannot because of the low pass
filter. Therefore, they are ignored by the
output FF because it cannot be cleared unless the low channel K enable is present.
The rejection of spurious pulses in the address mark gap is accomplished by ANDing the
high channel pulses with an enable pulse.
During the search mode, the Amplitude Enable
pulses are passed through and ANDed with the
high channel zero crossover pulses. When a
zero crossover pulse corresponds to an enable
pulse, it is passed through to reset the
Output FF. There are noise created zerocrossover pulses in the address mark gap
area. However, there are no enable pulses,
so the reset input to the Output FF is disabled. Noise pulses in the low resolution
channel are present at the set input of the
FF, but are ignored because the FF is not
reset during the gap period.
The Search Address Mark signal drops at the
end of the gap. This applies a constant
enable to the high resolution channel and
all zero-cross pulses get through to the FF.
This terminates the Amplitude Enable function and removes the Level Detector as a
possible source of error during the actual
reading of data.
3-79
READ/WRITE
HEADS
CYL.
ADDRESS
HEAD
ADDRESS
FROM
CONTROLLER
HEAD
ADDRESS
200na
~---'
DECODING
ANALOG
READ
DATA
ZERO
PULSE
L-..----~CROSS
GEN
DETECT
L
~
I CIII
-'
1:I:lnl----::>j
I
'----------1
L:l400Ci)
Ziro
CrOIlO.lr
K:l400
High
RIIO"'ion
ChaMII
~
K:l401
1:1410
®
Pulll
Glnlrator
ii
,
' I
,
"
:r==I:lOn.~
1:1412
.'
@ ::
@-+!
.:
~=I~!ilon
-Jr
:
i:
I - -_ _ _ _
:
.',:
'~-------~
K:l402@!!@7i.,r
.'
1:140S@
Pulll
Glnlrator
I:l403(!)
Data
LJ
I
L:l402@ t - 1 0 0 n 1 4
~~~:.ov.,
b.-.J
,j
::
i:
~
"
1klE---- 2 00
.:i'
•
n
Fl' - - - - - - -....
ftI
~Ho",
u
u
11
I I'--_ _-Jil
K:I403@1-·_ _ _ _ _ _ _ _ _ _. . . . . . J ' - -_ _ _ _....
Pull..
r
@ Prapa9ation Ollays
n _______11.-
-
DATA LATCH CIRCUIT TIMING
SYI9
Figure 3-45.
3-80
Data Latch Circuit
83313200
A
SECTION 4
KEY TO LOGIC
/~
\..J
(-
"--'
GENERAL
LOGIC CARDS
Section 4 contains information on logic symbology, operational amplifiers, integrated
circuit package configuration, discrete component 'descriptions and logic card diagrams.
PHYSICAL DESCRIPTION
The logic used in this device consists of
two styles of circuits: discrete component
and integrated circuits. Discrete component
circuits contain individually identifiable
resistors, capacitors, transistors, etc.
Standard TTL logic levels used are:
"1"'=
+3v and "0" = Ov.
Standard ECL levels rised
are:
"1" = -O.Bv and "0" = -l.Bv. All signals are named for their function when a "1".
For non-standard logic levels or analog
signal voltages, refer to applicable circuit
description.
LOGIC CHASSIS
The Logic Chassis consists of the logic
board wire wrap assembly and guiding piece
parts for the logic cards.
Logic cards are plugged into the logic board
wire wrap assembly.
Guide rails connected
to perpendicular panels guide the cards into
place and restrict horizontal or vertical
movement.
Wire wrap pins extend through the back panel.
The logic cards mate with these pins on one
side of the back panel. On the other side,
the "wire wrap" side, wiring interconnects
the logic functions between cards. This
wiring is secured to the pins by the wire
wrap technique. These pins also provide
convenient test points for monitoring logic
levels of all signals entering and leaving
each card.
The wire wrap surface of the logic board
wire wrap assembly contains wire wrap pin
identification (Figure 4-1). Logic cards
are designated by horizontal row (A) and
vertical column (1 through 16). Wire wrap
pins are then called out by pin number and
column A or B. For example, AB-12B is the
back panel pin at logic row A, position 8,
pin 12 of column B.
JAOI through JA04, PAl, PA2, PA6, PA7, P09,
and JAlO are auxiliary connectors used to
interface logic cards with maintenance panel,
I/O connectors, etc.
Pin identification is
by pin number (1 through 14) and row (A or
B).
(JAOl-5A is auxiliary connector JAOl,
pin 5, row A.)
B33l3200
A
All components of the logic cards (Figure
4-2) are mounted on one side of a printed
circuit board (PCB). Numeral designators
(1 through 99) are etched on the non-component side of the board identify each transistor. A 4-character alphanumeric designator
is etched on the non-component side of the
board to identify the card type. A matrix
code (alphanumeric) also appears on this
side. Non-amplifying components such as
integrated circuits, resistors, capacitors,
diodes, etc., are not marked.
.
PIN ASSIGNMENTS
Cards are equipped with a 62-pin (sockets)
connector. Connectors are mounted along the
shorter dimension on the component side of
the board.
The pins of each card connector are arranged
in two columns (A and B) and are numbered
from the top starting with pin 1 and continuing through pin 14 on the half-size card. ,
The pins of the full-size card are numbered
1 through 34, however, pins lBA, lBB, 19A,
19B, 20A, and 20B are omitted.
The logic chassis wire wrap surface (side
opposite surface where cards are installed)
contains wire wrap pin identification information adjacent to each chassis row. Wire
wrap pins are numbered 1 through 17 in each
chassis row. When a full-size card (spans
two logic rows) is installed in the logic
chassis, card connector pins (sockets) lA
and lB mate with wire wrap pins lA and lB of
the upper row, while card connector pins 2lA
and 2lB mate with wire wrap pins lA and lB
of the row immediately below. The logic
diagrams for this unit show connections in
terms of wire wrap pins.
TEST POINTS
Test points are located near the edge of the
card opposite the connector and in other
strategic places on the component side of
the board. Test points are identified alphanumerically starting with A on the top,outer
edge. Test points A and Z are available for
ground reference on full-size cards.
Only
test point Z is available for qround reference
on half-size cards.
4-1
I
I I
I
30 29282726252423 2221
I
I
=:
·
r-~&'O-,
c===J
20 19 18 17 16 15 14 13 12 "
I
I
'109876~
I . , JA80---,
I
A
~
............
B
1431211 10987654321
000 000000000008
000 oooooooooooA
8
8
o
o
o
o
o
o
o
o
o
o
o
___ 0
A
01
02
03
04
05
06
07
08
09
010
Oil
012
o
o
150
160
170
013
014
0
0
0
C
~
L500
VHI
A8
0
XXx....
....
I
I I
I
I
I c===J
I
I I
I
Wire WraE Pin Identification
A8
Position 8 in Chassis Raw A
l2B
Pin number 12 in Colunn B
3A
A8
Pin number 3 in Colunn A.
xxx
Special circuit characteristics.
(Oscillator frequency, delay
period, etc.).
When Chassis Raw and Position
are not listed it is identical
to the one above it.
JA80
SA
2
Input applied to transistor Q2.
Auxiliary connector used to
input or output signals tol
fran Back Panel.
4
output transistor (if applicable)
Q4.
Pin number 5 in Raw A
-f-
non Logic level
»,<
Pin connections.
lDgic ReEresentation
4-2
'.
~ Indicates direction of signal flON.
X/Y
Function symbol
LSOO
lDgic tenn or identifier
VHI
Circuit type designator. Alpha
characters indicate discrete
carp::ment circuits, nurreric
characters indicate integrated
circuits.
Figure 4-1.
i~·
Location of Logic Card. Connector
8 of Raw A. Location of full size
cards identified with top connector.
-1870
When no pin connections are indi-
cated, it is a continuous foil
going fran preceding tenn to indicated tenn.
8Y36
Wire Wrap Board Assembly
83313200
A
COMPONENT
TEST
POINT
FOIL
END
SIDE
SIDE
ETCHED MATRIX
TWO LOGIC_
CHASSIS ROWS
/
PIN IB
~ O-o.~
g
o
o
4
~ DISCRETE
-c::t
COMPONENTS
-L
_
tt
®
..1 or (>. > and
the logic negation indicator (~or
P--->.
The input polarity indicator indicates the
most negative potential is required to
satisfy the logic function represented by
the qualifying symbol. The output polarity
indicator indicates the most negative potential is present at the output when the logic
function is satisfied. The absence of the
polarity indicator indicates the most positive potential is present.
The presence or absence of the logic negation
indicator tells the conditions that are
necessary to satisfy the function of the
logic symbol. The presence of the circle
indicates a "0" logic level on that line is
needed to satisfy the function.
The absence
of the circle indicates a logical "1" is
needed to satisfy the function.
DYNAMIC INDICATOR
The presence of a dynamic indicator ( ~
just inside a symbol indicates the inputs
are gated (satisfied) with the dynamic positive-going transition of the input line to
the state shown. A logic negation indicator
(circle) accompanying the dynamic indicator
signifies that a negative-going transition
is required to gate in the inputs. Absence
of the dynamic indicator indicates the inputs
are gated (satisfied) with the static state
of the input line.
SIGNAL LINE INDICATORS
Non-Standard Levels
Some sig,nal line indicators indicate nonstandard levels on input/output lines. These
signal line indicators are as follows:
;'
The input/output state indicator depicts the
occurrence of inversion. Figure 4-3 shows
83313200
A
X
I
non-standard logic levels
analog or non-logic levels
variable control
4-3
NON -INVERTING
INVERTING
8Y32
Figure 4-3.
Inversion
Absence of "these indicators shown above
indicates a standard logic level.
Conventions
1
OR gate or inverter
a
AND gate
Inhibit
exclusive OR
The inhibit line indicates gating of the
logic function will be inhibited whenever
the line is at the level indicated by the
input state indicator. Inhibit line symbols
are as follows:
amplifier (with or without gain)
\,....
---~~~--~[
amplifier with adjustable gain
summing amplifier
integrating amplifier
with polarity indicator
differentiating amplifier·
----r---,[
without polarity indicator
)(/t>
digital to analog conversion
)(/11
digital to analog conversion
with adjustable gain
t>/V
analog to digital conversion
Miscellaneous:
Other signal line indicators are as follows:
I
~
test point
twisted pair
t>)( IV
1t>1
positive analog rectifier (symbol
preceded by a minus sign if negative
rectification is used)
analog surnnation of digital inp.lts.
Reference voltage outside box incHcates cutp.lt signal level resulting
when specified input (s) are negated
FUNCTION SYMBOLS
Circuit function symbols for discrete components and integrated circuits are as
follows:
amplifying level translator (gain
noted outside box)
t>,OV
Schmitt trigger
c~
4-4
83313200
A
\,....... ~
-
saturable ,non-linear, gain
controlled amplifier
("
,/
Ft>
function generator
nt>
active bandpass filter
.n
>
bandpass or resonant circuit
(
x/v
retriggerable multivibrator
(single shot)
tl-ll_ _ _--1tl
I
t~
2°onl
.I-I----j
1
hI~~----II.
3Onl'
35",
-I
decrease contents by one
(count down)
I
::!J
ones delay - when input changes
to a "1" a 200 nsec delay
occurs before the "1" is
passed on
zeros delay - when input
changes to a "0" a 30 nsec
delay occurs before the "0"
is passed on
both transitions are delayed
by 35 nsec
Inputs are individually identified as necessary by an input designator inside the
symbol block and adjacent to the left side
following all prefixes indicating dependency.
These input designators follow:
R
reset or clear
S
set
G
gating type input that affects
other inputs or outputs
J
J input of J-K flip-flop
K
K input of J-K flip-flop
indicates grouped inputs that rraintain a fixed relationship in states
and always change together
indicates relative
~ighting
of
inputs ·or outIXlts in codes. They
rray be' consecutive, binary ,decimal
representation of binary values, etc.
A,
a, C, ETC.
when two or nore of these are used
together in inputs to a symrol, it
in:licates individual signals or
individual groups of signals to be
identified for further operations
such as aritl1.matic functions
symmetry restoration
circuit
INPUT/OUTPUT DESIGNATORS
certain .input designators (C and G) may also
be used as prefixe·s to other input designators,
but not to each other, C and G indicate dependency of every designator, such as D,they
prefix, and are referred to as dependency
notation. For example, CD indicates that
the input 'is gated to a D-type flip-flop
only when the C input is active. Gate dependent inputs (G) may be distinguished from
each other by 1, 2, etc., following the G.
Where more than a single G term is involved,
commas are used to separate the numbers.
Clock dependent inputs for loading data are
denoted by a "C". Different C inputs are
distinguished by a number following the C.
COMMON CONTROL BLOCK
Signals entering the common control block
(Figure 4-4) are common to more than one
used to link gating (clock)
input of control block to J
and K inputs of J-K flip-flops
i!
T
toggle or complement input
o
data input of D-type flip-flops
C
a gating (clock input for Dtype flip-flops)
83313200
increase contents by one
(count up)
Level conversion - trarumdssion
line to logic level, switch state
(ground or open) to logic level,
logic level to power ou~t (to
drive laIII>, relay, solenoid, etc.)
-I1-
1
+1
,]OR[
bidirectional switch
shift left (or up)
shift right (or down)
A
CD
®
®
COMMON CONTROL BLOCK
NECK
SECTION(S) CONTROLLED BY COMMON CONTROL
BLOCK.
8Y33
Figure 4-4.
Common Control Block
4-5
section of the circuit. The neck of the
common control block abuts the top or bottom
of the sections it controls. Input desig-.
nators may include C, G, R, -+, - , +1, -1,
plus se~ect lines with or without decoding.
WIRED FUNCTIONS
OPERATIONAL AMPLIFIERS
The logic representation for wired functions
is shown in Figure 4-5. These functions are
used where circuits have the capability of
being combined as an OR function by having
the outputs connected. This is simply a .
physical connection and no electrical or
electronic components are involved. The
logical interpretation of a wired OR ~on
simply requires that one of the inputs be a
logic "0" before the output can be a logic
"0". The wired AND output will be a logic
"1" only when both inputs are logic "lis".
INTEGRATED CIRCUITS
Figure 4-6 shows the schematic version (as
shown on card schematic diagram) and the
logical representation (as shown on logic
diagrams) for the same representative integrated circuit.
Referring to Figure 4-6 it is apparent that
the two versions are essentially the same.
Both views identify pin numbers, the function symbol, and the CDC element number for
the circuit. Refer to section 5 for manufacturer's information on the various element
numbers.
The last item of information regarding these
two representations involves the location
code which borrows part of the schematic
symbols reference designator.
In the reference designator (U-A4B), the U specifies a
non-amplifying integrated circuit, the A4 is
the circuits board matrix location for the
package, and the B indicates the section of
the package.
(A 140 package is a four section package. Each section is a separate
AND
OR
INPUT
f
OUTPUT
INPUT
INPUT
a
OUTPUT
INPUT
6TIO
Figure 4-5.
circuit. Sections are identified A through
D.) The location code (on logic drawings)
borrows the matrix location and additionally
specifies the location of the card in the
logic chassis: position 5.
Wired Functions
INTRODUCTION
The operational amplifier (op amp) is a highgain integrated circuit that can amplify
signals ranging in frequency from dc to its
upper frequency limit, which may be more than
one megahertz. It is used extensively in
the drive as a linear amplifier of servo
analog signals. Because of its versatility,
however, it has multiple applications.
The op amp approaches the following characteristics of an ideal amplifier:
1.
Infinite voltage gain
2.
Infinite input resistance
3.
Zero output resistance
4.
Zero offset: output is zero when
input is zero
5.
High bandwidth frequency response
BASIC CIRCUIT ELEMENTS
Figure 4-7 is a highly simplified schematic
of a typical op amp with its basic feedback
network. Detailed circuit analysis information may be obtained by referring to the
manuals prepared by the applicable manufacturers.
INPUT STAGE
All op amps utilize a differential amplifier
in the input stage. This circuit may be
relatively simple, as shown, or may consist
of multiple circuits with FTEs or Darlingtonconnected transistors. The advantage of
this type of amplifier is that it amplifies
the difference between the two input signals.
For example, if 10 mv are applied to the
non-inverting input while 9 mv are applied
to the inverting input the extra 1 mv difference is amplified. The amplification,which
may be a voltage gain of up to 100,000 is
linear until the op amp saturates or until
increasing frequency causes rolloff.
If the same input is applied to both input
terminals, the signal is referred to as the
"common-mode" input signal.
In the preceding example, the 9 mv are the common-mode
input, while 1 mv is the differential input.
In the ideal op amp, the output is zero with
c. .·
4-6
83313200
A
C)
SCHEMATIC
INPU\
u_~ZF D/DUTP~
___
--'-I~-_-./OUTPUT
~14~
7-
I
FUNCTION SYMBOL
CDC ELEMENT NO.
CDC ELEMENT NO.
8Y34
Figure 4-6.
Integrated Circuit
CI
r--J ~:-- ..
I
1 '..
:
:
R2
:
I
I
I
I
--.
12
INllUT STAGI
2M ITAGE
OUTPUT STAGE
V2
NOTES. r:"\,
\.!.I
TO COMMON CONSTANT-CUfitRENT SCUM:[.
NOT APPLICABLE TO ALL TYPES.
REFER TO MANUFACTURER'S DATA SHEET.
FOR BALANCEO INPUT IMPEDANCE.
RS·
.!!..!....!!!.
1.113S
" •• R2
Figure 4-7.
83313200
A
Simplified Op Amp Schematic
4-7
identical inputs. Only the difference (1 mw
is amplified. Since the common-mode input
is not amplified, signals common to both,
such as noise and hum, are cancelled.
SECOND STAGE
Not all op amps have a second stage. If
used, however, it may contain additional
amplification and level shifting.
BASIC CIRCUIT FUNCTIONS
Resistors RI and R2 provide degenerative
feedback to control the overall gain of the
circuit. As long as the ratio R2/Rl is low
compared to the open loop gain at the operating frequency, circuit gain is independent
of the characteristics of the specific op
amp.
Rapid analysis of this circuit' is possible
if two basic principles of op amps are assumed:
1.
Insignificant current flows into
either input terminal; it can be
assumed to be zero.
2.
The differential voltage (V3) is
insignificant and can be assumed
to be zero.
Rule #1 may be presumed since the input
impedance is very high. As a result, all
current (II) entering the summing point must
leave it (12). These currents are:
II
vliRl
I2
-V4/R2
The minus (-V4) indicates that the output is
the inversion of the input. Since no current flows into the op amp, II must be equal
to 12. By Ohms Law:
V4/VI = -R2/Rl or V4 = -Vl(R21Rl)
Therefore, the output is simply the ratio of
R2/Rl. This linear output/input relationship holds true as long as the input (VI) is
not of sufficient amplitude to saturate the
op amp.
Resistor R2 is frequently shunted by a capacitor. This controls the roll-off characteristics of the circuit where the full op
amp bandwidth is not required. The effective
feedback to the input is the resistance of
R2 in parallel with the capacitive reactance
of Cl. Capacitive reactance decreases as
frequency increases. Therefore, a frequency
increases, the effective impedance of R2-Cl
decreases to reduce overall gain.
4-8
If Cl is large enough, its charging time becomes more of a factor. The output cannot
react as fast as the input may change. This
is the integrating or low pass function. For
example, doubling the frequency halves the
gain. The output is the mathematical integral
of the input when the effects of Cl predominate
over the effects of R2. Thus, if the input
voltage is proportional to velocity, the
output is proportional to distance.
Since there is actually a slight current
(measured in nanoamperes) entering the differential stage, "the difference or unbalance
between the two input currents would be
amplified. This results in an error known
as dc offset, that is, the output would be
non-zero with a zero common-mode input. If,
however, the currents are made to be equal,
that is, they see equal input impedances,
they are common-mode and are cancelled.
Resistor R3 is selected to balance out the
offset voltage and current by making the
impedance to ground of the two inputs equal.
Rule #2 holds true as long as feedback is
provided by R2 or its equivalent. As long
as the amplifier is not saturated, it will
adjust its output voltage to maintain the
differential voltage V3 at zero. Therefore,
the summing point is at V2.
Since V2 is
usually at ground potential, the summing
point is also at ground. This is a "virtual"
ground, that is, it is at ground potential
even though there is no connection between
this point and true ground.
If the summing
point is monitored with an oscilloscope,
little or no signal can be observed.
Typical op amp circuit functions are illustrated in Figure 4-8.
SCHMITT TRIGGER CIRCUITS
Operational amplifiers can also be connected
in the Schmitt trigger configuration (Figure
4-9). Note that the degenerative feedback
path is not provided.
It is replaced by a
regenerative feedback path. This is the
open loop configuration: if the voltage at
the non-inverting input is greater than the
voltage at the inverting input, the output
is saturated at its most positive value.
Reversing the inputs causes the circuit to
slew (change) at its maximum possible rate
to saturate negatively.
All Schmitt triggers have hysteresis.
Hysteresis is supplied by regenerative feedback from the output to the non-inverting
input.
Consider A376 o~ Figure 4-9. Assume the
voltage at A is zero. A voltage divider
network (not shown) sets point B at +1.28v.
83313200
A
I
'''~
••••
~
CIRCUIT TYPE
OUTPUT Q)
SYMBOL
INVERTING
AMP
V
OOT
R2
= - --
Y,N
RI ,
INVERTING
AMP WITH
RE'ERENCE
VOLTAGE
v::
R
-t] ~
OBSERVE ALGEBRAIC SIGNS
I F CO .. PUTING
_...o1WIMI\,3_.v'_R_
EF
VOUT=O
OR
-V
V R EF
=
IF
:t
NON
INVERTING
A.. PLIFIER
V,N=VREF
V ('
R3
)
R3
+-
R4
( R,
+
R2 )
VOUT=
SU .... ,NG
' .. PLI FIER
INVE RTI NG
A .. PLIFIER
WITH OUTPUT
Ll"'TINe
VOUT =
IF
-
± VOUT
~V
R,
IN
~ V
z
NOTE:
o ..
,NUS
SIGN (-)
Figure 4-8.
INDICATES
THAT
OUTPUT
IS
INVERTED.
Op Amp Circuit Functions (Sheet 1 of 3)
o
83313200
A
4-9
CIRCUIT TYPE
OUTPUT0
SYMBOL
INTEGRATIN G
AMPLI FIER
VOUT
VOUT
IF
= -
Y,N
IS
R: C ...
JV'N
dt
CONSTANT,
Y,N
X TIME
R, C
INTEGRATING
AMPLIFIER CONTROLLED
BY P-CHANNEL
(A) IF
R,
It>
Y,N
JFET
VOUT
V OUT
1
(B) IF
V
':"
IS
VA
VA
OV
°v
=
IS
+ 14V
I
OUT
=--R, C
IVI N
dt
DIFFERENTIAL
VOUT
AMPLIFIER
VO L TAGE
FOLLOWER
NOTES:
CD
®
M I NUS
R2
SIG N (-)
U SED
TO
SYMMETRICAL
Figure 4-8.
4-10
I NDICATES
PROVI DE
ABOUT
DC
THAT
OUTPUT
FEEDBACK
TO
IS
KEEP
INVERTED.
OUTPUT
GROUND.
T J • I -2
Op Amp Circuit Functions (Sheet 2 of 3)
83313200
A
C~,I
CIRCUIT TYPE
SYMBOL
:~
OPEN LOOP
( COM PARATOR)
:
F.UNCTION
CD
= + VSAT
VOUT = OV
Vour = -VSAT
lV-~r-VOUT
v,
V OUT
VOUT
VOUT
V2
VOUT
:::
V2
V,
=
V2
IF
V,
>
V2
IF
V,
<
V2
IF
V,
=
V2
IF
V,
>
V
IF V,
<
V2
IF V,
=
V2
IF V,
>
V2
IF V,
<
V
IF V,
=
V
2
IF
> V2
IF
V,
IF
0
SATURABLE
COMPARATOR
SATU R ABLE
COMPARATOR
<
VOUT
I 1;~PVOUT
-"
=
+vm
= OV
= V2
= V2
VOUT = OV
VOUT = -VSAT
VOUT
2
CD
Vz
r-',
~./J
= Vz
VOUT = OV
VOUT = V 2
V,
VOUT
NONL INE AR
COMPARATOR
VOUT
V2
NOTE:
CD
VOUT IS
LOOP
ACTU ALLY
VOLTAGE
EXCEED THE
2
VOLTS
Figure 4-8.
83313200
A
GAIN
(AV)'
SATURATION
LESS
OF
PRODUCT
THAN
I I- I I
VOLTAGE
THE
V,
AV ~
V
2
10,000.
(VSAT)'
SUPPLY
X
~UT
AMPLI FIER
CANNOT
WHICH
IS
V,
2
OPEN
ACTUALLY
ABOUT
VOLTAGE.
'.111-
:s
Op Amp Circuit Functions (Sheet 3 of 3)
4-11
~
<
>
I.IOV = Y
1.2IV=Y
\
A--~--~------~~------------~-
\
<
>
\
0.30V= Y
0.70V=Y
\
I>.av
A
A 33 2
\
Y
I--t....-..
VREF
+ 0.30
\
\
\
\
V
I>.av
1.10
\Y{ + 14
\
-
\
Y
A380
+
\
<-1.28V=Y
>-I.IOV =y
A
B{+ 1.28
\
14
\
\
\
<- 0.70 V= Y
>-0.3OV=Y
\
A
V REF
- 0.30 V
\
\
B
\
\
\
NOTES:
Q) Y SWITCHES WHEN
®
G>
@
=
\
\
\
\
\
+V
I
Figure 4-9.
4-12
~
{ - 0.30
B
TYPICAL DIVIDER
= +V ( R :
1.10
1.28 1 - - - - - - - - - - - - 1
14
- 14
\
WITH Y HIGH I DIODE IS ON.
FEEDBACK THRU DIODE DRIVES
VREF MORE POSITI VE,
R2
-
B •
WITH Y HIGH I DIODE IS OFF.
VREF SUPPLIED BY VOLTAGE
DIVI DER ONLY.
V REF
\{+
\
\
A
VREF SU PPLIED BY RESISTIVE
VOLTAGE DIVIDER. SEE BELOW.
RI1-
\ B{-
)
_
0.70
1------------1
\{: ::
2
7'" 'A
Op Amp used as a Schmitt Trigger
83313200
A
...... ,-"'
without feedback and, since the non-inverting
input is more positive than the inverting
input, the output is saturated positively.
amplifier, the logic function performed by
the circuit. The second line, also an alphabetic code, designates the circuit type being
used (HAB). The circuit type is a subdivision
of the function identifier (specifically a
. high level amplifier). By using the circuit
type designator, detailed information on that
particular.circuit may be obtained by referring to Section 6.
As the input A goes more positive, the output
does not'change until A equals B (+1.28v).
The differential voltage is then zero, so
the output starts to switch to a zero-volt
output. However, there is now a path from
y to B;
the B input becomes less positive
than the A input. The output very quickly
saturates negatively.
The third line within the symbol identifies
which logic card location and circuit is
located on.
with about -14v available at Y, the voltage
at B is reduced to +l.lOv. The input must
now swing to less than +l.lOv for the output
to change its state back to positive saturation.
The numbers on the input lines to the symbol
indicate which transistor is driven by that
input line. For example, the upper input
has a number 22 on its line, showing that it
drives transistor number 22 (i.e., Q22 on
the card schematic diagram) •
The remaining circuits work in a similar
manner.
The output lines also have numbers associated
with them. These numbers indicate which
transistor directly feeds the output line.
For example, the lower output line has a
number 40 above it, indi~ating that the output from transistor number 40 (Q40 on the
card schematic diagram) drives the lower
output line.
DISCRETE COMPONENT CIRCUITS.
Figure 4-10 shows a schematic (as shown on
card schematic diagram) and the logical
representation (as shown'on logic diagrams)
for the same theoretical discrete component
circuit. Three lines of information are
contained within the logic symbol. The top
line is the function symbol and designates
the board logic function of that particular
symbol.
In this case,
I> represents an
The lines on the interior of the logic block
that bracket both inputs and both outputs
+20V
+20V
R22F
.------OUT
R22C
Q41
Q22
/ 22
I
R22A
R22D
1
I
-20V
391\
t>
41
/
f
]A705 [
HAS r--..40
L
/
-=-
-=R22S
Q39
+20V
Q40
R22E
R22G
OUT
+20V
("
~)
Figure 4-10.
83313200
A
8Y35
Discrete Component Circuit
4-13
show that the input lines and the output
lines are differentials. The relative level
indicators show that the amplifier does not
invert the signal. Slashes on the inputs
and outputs show that the signal levels are
non-standard.
For schematic diagrams of discrete component
circuits used in this device see Section 6.
An analysis of circuit operation supports
each circuit diagram. The order of presentation is in accordance with the three-letter
~lphabetical circuit type designator.
\
( .-
"
4-14
83313200
A
SECTION 5
INTEGRATED CIRCUITS
DESCRIPTION
The 140 circuit is a two input-one output active low
level output AND I NAND gate.
NOTES:
1.
Symbol shown as it would appear on logic
diagrams.
2.
Sym bol repeated for each gate.
3.
Type 140 manufactured by Fairchild
A~
Semiconductors (P IN 9002) used for low
__ C
a~.
OR
A~
a----LJ
C
speed applications.
4.
Type 140S manufactured by Texas
LOGIC SYMBOL
Instruments (PIN 74S00) used for high
speed applications.
5.
Propagation delay time:
Type
6.
Delay Time (NSec)
140
18
140H
10
140S
5
+ Vee
Package pin configuration.
ID4
8
TOP
VIEW
I
7GND
A B C
0 0 J
0 J J
0 I
J
I I 0
TRUTH TABLE
(FOR ONE GATE)
PIN ASSIGNMENTS
Element 140 Sheet 1 of 1
83313200
A
5-1
Description
The 141 circuit is a three input-one output active
low level output AND/NAND gate.
NOTES:
1.
Symbol shown as it would appear on logic
diagrams.
2.
Symbol repeated for each gate.
3.
Type 141 manufactured by Farichild
~DD
Semiconductors (P /N 9003).
4.
~D-D
Type 141H manufactured by Texas
Instruments (P IN SN 74HI0).
5.
OR
LOGIC SYMBOL
Type 141S manufactured by Texas
Instruments (P IN SN 74S10).
6.
Propagation delay times:
Type
7.
Delay Time (NSec)
141
10
141H
6
141S
3
+Vcc
Package pin configuration.
ICJ48
TOP
VIEW
I
7GND
A B C 0
0
0
0
0
0
0
0
I
I
0
I
I
I
I
0
0
0
I
I
0
I
I
I
I
I
I
I
I
0
I
I
I
TRUTH TABLE
PIN ASSIGNMENTS
Element 141 Sheet 1 of 1
5-2
83313200
A
Description
(~--\
The 143 circuit is a four input-one output active low
"'---/
level output AND INAND gate.
NOTES:
1.
Symbol shown as it would appear on logic
diagrams.
2.
Symbol repeated for each gate.
3.
Type 143 manufactured by Fairchild
c
OR
C
E
0
Type 143H manufactured by Texas
LOGIC SYMBOL
Instruments (P IN SN 74H40).
5.
E
o
Semiconductors (P IN 9009).
4.
:D :D-
Type 143S manufactured by Texas
Instruments (P IN SN 74S40).
6.
Propagation delay time:
Type
7.
Delay Time (NSec)
143
10
143H
6
143S
3
+Vcc
Package pin configuration.
c::)148
-TOP
VIEW
I
A
B C 0 E
0
0
0
0
0
0
0
0
0
0
0
0
I
I
I
I
I
I
I
I
0
0
0
0
I
I
I
I
I
I
I
I
0
0
I
I
0
0
I
I
0
0
I
I
0
0
I
I
0
I
0
I
0
I
0
I
0
I
0
I
0
I
0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
0
7GND
~~ S~CT
1.----
6
PIN ASSIGNMENTS
TRUTH TABLE
(FOR ONE GATE)
Eleroent 143 Sheet 1 of 1
83313200
A
5-3
2
Description
S
5
The 144 circuit is a JK Flip-flop capable of synchronous or asynchronous input operation.
4
12
The
G'
jGJ
6
/,.--..."
",
........ /
asynchronous inputs control the state of the flip-flop
indepen~ent of static conditions of the clock and
synchronous inputs. With pin 13 or pin 2 LOW
9
one output will be high, but if opposing data is pre-
3
sent at the synchronous inputs and the flip-flop is
II
clocked, the low output may momentarily spike
10
13
HIGH synchronous with a positive transition of the
clock.
jGK
G.
R
A low level to the set input (pin 2) will set
GJ-J OUTPUT CONDITIONED BY LEADING EDGE
OF DYNAMIC TOGGLE(G)
pin 6 to high level regardless of the level at the
clock (pin 9) input.
A low level to the reset (pin 13)
input will clear pin 6 to low level regardless of the
level of the clock input.
Data is accepted by the master while the clock is in
the low state.
GK-K OUTPUT CONDITIONED BY LEADING EDGE
OF DYNAMiC TOGGLE (G)
G- GATE INPUT, HAS NO DIRECT EFFECT ON
CIRCUIT, BUT MUST PRESENT BEFORE
SIGNALS PRESENT ON INPUT(S) CAN BE
TRANSFERRED TO OUTPUT(S)
S-SET INPUT, WHEN "0", FF IS SET REGARDLESS
OF INPUTS AND GATE STATES
Transfer from the master to the
slave occurs on the LOW to HIGH transition of the
clock.
144
G
When the clock is HIGH, the J and K inputs
R-RESET (CLEAR) INPUT, WHEN "0'; FF IS CLEARED
REGARDLESS OF INPUTS AND GATE STATES
are inhibited.
LOGIC SYMBOL
NOTES:
1.
Symbol shown as it would appear on logic
diagrams.
2.
Type 144 manufactured by Fairchild
Semiconductors (p IN 9001).
3.
+VCCt:j
. con f'19urat'IOn.
P ac k age pm
.
TOP
VIEW
I
7 GND
GJ
INPUTS
GJ GK
OUTPUTS
OUTPUTS
BEFORE TOGGLE AFTER TOGGLE
GK _ _ _ _-A
SET
RESET
SET
RESET
G
SET~
0
0
0
I
0
I
0
0
I
0
I
0
0
I
0
I
0
I
0
I
I
0
0
I
I
0
0
I
I
0
I
0
I
0
I
0
I
I
0
I
I
0
I
I
I
0
0
I
~
RESET~~______~r-l~
____~
TIMING SEQUENCE
TRUTH TABLE
Element 144 Sheet 1 of 2
5-4
83313200
A
C.:
C,":'
2
PIN
4
SET
JI
PIN
5
J2
12
J3
9
Q
6
1-'"'-.........-0 Q
8
CLOCK
JK
3
KI
10
II
K3
RESET
13
FUNCTION DIAGRAM
Element 144 Sheet 2 of 2
o
83313200
A
5-5
Description
Circuit 145 is a dual expandable AND-OR-INVERT
gate.
Section B of this circuit is expandable.
If not
expanded pins 11 and 12 are open.
NOTES:
1.
Sym bol shown as it would appear on logic
diagrams.
1
2.
Type 145 manufactured by Fairchild
145
Semiconductors (P IN 9005).
3.
6(81
OR
Type 145H manufactured by Texas
n
Ilstruments (P IN 74H50).
4.
LOGIC SYMBOL
Propagation delay time:
Type
Delay Time (NSec)
145
18
145H
10
c::J
+Vee 14
5.
Package pin configuration.
8
TOP
VIEW
I
7
GND
C~
EXTENDABLE GATE
a
13
SECTION B
A
B C
D E
0 0 0 0
0 0 0 I
0 0 I 0
0 0 I I
0 I 0 0
0 I 0 I
0 I I 0
0 I I I
I 0 0 0
I 0 0 I
I 0 I 0
I 0 I I
I I 0 0
I I 0 I
I I I 0
I I I I
I
I
I
I
I
I
I
0
I
I
I
0
0
0
0
0
TRUTH TABLE
1
8
9
a
10
'----II
*EMIT
' - - - - - 1 2 *COLL
*CONNECTION FOR EXTENDER
NON-EXTENDABLE GATE
2
SECTION A
1
6
4
5
PIN ASSIGNMENTS
Element 145 Sheet 1 of 1
5-6
83313200
A
Description
(~'
,,-)
The 146 circuit is a hex inverter NAND gate.
NOTES:
1.
Symbol shown as it would appear on logic
diagrams.
2.
Symbol repeated for each gate.
3.
Type 146 manufactured by Fairchild
~ OR A-CS. I:l B
AL:J-B
Semiconductors (P IN 9016).
48
la
4.
Propagation delay time is 10 nsec.
5.
Package pin configuration.
+Vcc
LOGIC SYMBOL
TOP
VIEW
I
A~
B~
TIM lNG' SEQUENCE
7GND
J~2
3~4
5~6
9~8
JJ~JO
J3~J2
PIN ASSIGNMENTS
Element 146 Sheet 1 of 1
83313200
A
5-7
Description
r----.
The 147 circuit is a eight input-one output active
1.
\ ....... ~,,'
low level AND /NAND gate.
NOTES:
1.
Symbol shown as it would appear on logic
diagrams.
2.
"
12
13
Type 147 manufactured by Fairchild
Semiconductors (P IN 9007).
la
3.)
Propagation delay time is 18 nsec.
4.
Package pin configuration.+
Vcc
4
.
I
I
2
3
4
10
a
1
8
OR
147
147
LOGIC SYMBOL
B
TOP
VIEW
7GND
"......
INPUTS
a
I
2
H H
3
4
OUTPUT
10 II 12 13
H H H H H
H
ANY INPUT LOW
8
L
H
I
2
3---t--4
10
11---1....
__
INPUTS
1
I 121314110
LILILILIL
OUTPUT
"
L
12113
8
LIL
H
ANY INPUT HIGH
L
8
12
13
FUNCTION DIAGRAM
TRUTH TABLE
Element 147 Sheet 1 of 1
5-8
83313200
A
'
148
Information not available at time of printing.
It will be supplied at a later revision.
83313200
A
5-9
Description
The 149H circuit is a Quad 2 -input Exclusive OR
gate that performs the function: Y=
AB + AB.
When
the input states are complementary, the output goes
to the
hig~
level.
NOTES:
1.
=
A
Symbol shown as it would appear on logic
diagrams.
149H
C
OR
AE-_1
B
149H
C
B
2.
Symbol repeated for each gate.
3.
Type 149H manufactured by Motorola
LOGIC SYMBOL
Semiconductor Products, Inc., (P IN 3021).
4.
Propagation delay time is 30 nsec.
5.
Package pin COnfiguration:VCCIc:J48
.
I
TOP
VIEW
7GND
('
"- .
~JSE~~ AI
ISE~i B~6
4
A B C
0
0
0
0
1
1
1
0
1
1
1 0
TRUTH TABLE
3
5
I':JSE~~ I
8
C
12
13
ISE~; D~"
,.
PIN ASSIGNMENTS
Element 149 Sheet 1 of 1
5-10
83313200
A
('"
,---.
Description
The 158 circuit is a 4-bit synchronous binary
counter. This circuit can be preloaded with data at
the data inputs when the load input is low. This disabIes the counter and enables the data inputs. Input
data will be transferred to the outputs the next time
the clock input has a low to high transition.
6
'5
4
In order for the counter to count, the load, clear,
enable P, and enable T inputs must be high.
3
A low
When P enable is low, the clock input is disabled so
that the counter can not count when enable T is low.
Also, when P enable is low, the clock input and carry
output are disabled.
1
15
G3
-,
.,
ICD
ICD
-,
-,
ICD
ICD
1/
12
13
14
16 CNT
158
level to the clear input will clear the outputs to low
level regardless of the level to any other input.
15
X--Y
2
2,3+1
9
1
G2
NOTES:
1. Symbol shown as it would appear on logic
drawings.
2.
LOGIC SYMBOL
Type 158 manufactured by Fairchild
Semiconductors (P IN 9316).
3.
. conf·19urat·lone +Vee 16
P ac k age pm
9.
~TOP
~VIEW
8
I GND
Element 158 Sheet 1 of 3
83313200
A
5-11
PIN
I
(CLEAR)
9
(LOAD)
--U
--+Ur-.- - - - - - -
,~}NPUTS -~~---------.
2 (CLOCK)
~
7 (ENABLEP)'~
:I~}::::::S ~
Tl
12
--.J
I
I
I
I
"
---.J I
15 (TC CARRY)
:::
_ =DON'T
CARE
CONDITION
I
1-1_~_
"1-_---:-_
/01'2~31415 0 I
CLEAR
COUNT
PRESET
®
TO 12
®
1.
INHIBIT
COUNT
NOTES:
®
MODE SELECTION WITH POSITIVE-GOING CLOCK IS:
PINS
7
a 10
@
MODE
I
COUNT UP
0
I
NO CHANGE
I
©
9
I
0
®
PIN
0
0
r-'
(
\,......
PRESET
PRESET
PIN 15 IS HIGH WHEN ALL OF THE FOLLOWING
PINS ARE HIGH: 10, ", 12, 13, AND 14.
ILLUSTRATED ABOVE IS THE FOLLOWING:
I. CLEAR OUTPUTS TO ZERO
2. PRESET TO BINARY 12
3. COUNT TO 13, 14, 15, 0, I AND 2
4. INHIBIT
~
I
2
3,4,5,6
7
9
10
11,12,13,14
15
FUNCTION
MASTER RESET (ACTIVE LOW) INPUT (CLEAR)
CLOCK ACTIVE HIGH GOING EDGE INPUT
PARALLEL INPUTS
COUNT ENABLE PARALLEL INPUT
PARALLEL ENABLE (ACTIVE LOW) INPUT
COUNT ENABLE TRICKLE INPUT
PARALLEL OUTPUTS
TERMINAL COUNT OUTPUT (CARRY)
TIMING SEQUENCE
Element 158 Sheet 2-3
5-12
83313200
A
9
LOAD
I
~J
....r--
.
1a
CLEAR
CLOCK
L..-
=E}lK
3
DATA A ..,
I
QA r-~ QA
CLEAR
'(
I
~J
QB ~~ QB
"-r---
1
I
I
a
CLOCK
~
DATA B
~KCLEAR
4
'"
y-
~J
QC ~~ QC
""--
a
CLOCK
'---
DATA C ..,
CLOCK
@-K
5
~
COUNT 7
ENABLE
P
_6
DATA D ..,
CLEAR
r
r-&-J
QD
~~ QD
....:...
a
a
CLOCK
@-K.CLEAR
I
COUNT _10
ENABLE .....
T
"I
I
~
15
.....
RIPPLE
CARRY
FUNCTION DIAGRAM
o
Element 158 Sheet 3 of 3
83313200
A
5-13
Description
TIMING
NETWORK
The 161 circuit is a monostable retriggerable multivibrator that provides an output pulse whose duration
is a function of external timing components.
Input pins 3 and 4. trigger on the positive goine edge
of the input pulse and pins 1 and 2 trigger on the
negative goine input pulse. The 161 circuit will retrigger while in the pulse timing state (pin 8 high)
LOGIC SYMBOL
and the end of the last pulse will be timed from the
last input.
NOTES:
1.
Symbol shown as it would appear on logic
diagrams, except for timing network.
2.
Type 161 manufactured by Fairchild
Semiconductors (P IN 9601).
3.
Package pin configuration.
PIN
LJ
rr=r1
:
2
+Vcc
,
I
'D4
8
3-.J
4-.J
TOP
VIEW
I
RETRIGGER
7GND
I
-.I
~*
I
8
6
* PULSE
WIDTH DETERMINED
RC TIMING NETWORK
OUTPUT PINS
INPUT PINS
I
OPERATION
2
BY
3
4
8
6
U
H~L
H
H
H
TRIGGER
Jl.
H
H~L
H
H
TRIGGER
n. U
n
U
U
n..
n.
U
L
X
L-+H
H
TRIGGER
X
L
L-+H
H
TRIGGER
L
X
H
L~
TRIGGER
X
L
H
L-+H
TRIGGER
H
H
H
H
L
H
X
X
L
X
L
H
X
X
X
L
L
H
n.
TIMING SEQUENCE
U
a
4
X=DON'T CARE
TRUTH TABLE
OUTPUT PULSE WIDTH (t) IS DEFINED AS
FOLLOWS:
0.7J
t = 0.32 Rx Cx ~ + ""R";"
r.
Rx IS IN KG, ex IS IN pf, t IS IN NS
FUNCTION DIAGRAM
Element 161 Sheet 1 of 1
5-14
83313200
A
c
Description
The 162 circuit is a dual differential line receiver.
A minimum differential voltage of 25mv is required
to insure a high or low output level.
Common mode
voltages of ±3v or less will be rejected.
The maxi-
mum allowable differential input voltage is 5 volts.
+5V
C
S6
56
NOTES:
1.
TERMINATION
RESISTORS
ON CARD BUT
NOT SHOWN
ON LOGIC
DRAWINGS
Symbol shown as it would appear on logic
diagrams.
2.
Type 162 manufactured by Texas
Instruments (PIN SN 75107A).
3.
TWISTED PAIR
RECEIVER APPLICATION
Type 162C manufactured by Texas
Instruments (P IN SN 75108) .
4.
... Vee
Package pin configuration:
1~4
8
TOP
VIEW
I
7GND
8
GI
ANALOG TO DIGITAL
CONVERTER APPLICATION
+IV
4
OR
4
9
~1-8----t GI
9
162C
1...-_ _- - - '
>OV=Y
<-O.8V=Y
162 DUAL DIFFERENTIAL RECEIVER USED AS A
SCHMITT TRIGGER WITH EXTERNAL FEEDBACK
NETWORKS AND FIXED BIAS ENABLING GI AND
G2 STROBE INPUTS.
LOGIC SYMBOL
Element 162 Sheet 1 of 2
83313200
A
5-15
("
\
'
PIN
__ . J
PIN
5,6,8
I
5
+V---
~
I
I
PIN
I
5,6,8----+V----
1.12-\--A-[\-1:--
PIN 4 IS LOW ONLY IF GI AND G2 ARE
HIGH AND PIN I IS MORE NEGATIVE
THAN PIN 2. G2 IS COMMON TO BOTH
CONVERTERS.
162 DIGITAL TO ANALOG
CONVERTER APPLICATION
P
I
1
I
P
I
I
.1
P
1
1
I
ov
-O.8V
9~
162 TWISTED PAIR
RECEIVER APPLICATION
162 SCHMITT TRIGGER
TIMING SEQUENCE
r"'
\
\.....
DIFFERENTIAL
INPUTS
VIO~
25MV
-25MV
a
II
9
8--------------~
FUNCTION DIAGRAM
(RCVR APPLICATION)
Element 162 Sheet 2 of 2
5-16
83313200
A
Description
The 164 circuit is a dual JK edge-triggered flip-flop.
The 164 dual JK flip-flop triggers on the negative
going edge of the clock.
Each flip-flop is provided
with a di!,ect SET input.
These direct inputs pro-
G
6 (8)
GK
vide a means of presetting the flip-flop to initial
conditions or other asychronous operations.
LOGIC SYMBOL
Data may be applied to or changed at the clocked
inputs at any time during the clock cycle, except
during the time interval between the set-up and holdtimes.
The inputs are inhibited when the clock is
low and enabled when the clock rises.
continuously respond
clock is high.
The JK inputs
to input information when the
The data state at the inputs through-
out the interval between set-up and hold time is
INPUT
stored in the flip-flop when the clock pulse goes low.
J
OUTPUT
BEFORE G
K
SET CLEAR
OUTPUT
AFTER G
SET CLEAR
Each flip-flop may be set at any time without regard
0
0
0
I
0
I
to the clock state by applying a low level to the SET
0
0
I
0
I
0
input.
0
I
0
I
0
I
0
I
I
0
0
I
I
0
0
I
I
0
Symbol shown as it would appear on logic
I
0
I
0
I
0
diagrams.
I
I
0
I
I
0
1
1
1
0
0
1
NOTES:
1.
2.
Symbol repeated for each flip-flop.
3.
Type 164H manufactured by Motorola
TRUTH TABLE
Semiconductor Products, Inc., (P IN
3062) .
4.
Type 164S manufactured by Texas
Instruments (P IN 74S113).
5.
6.
Propagation delay time:
Type
Delay (NSec)
164H
12
164S
7
PIN
3 (12)
+Vcc
Package pin configuration.
----------------~
~148
4(10)--u
TOP
VIEW
I
7
I
I
U
1(13)
I
GND
L
I
I
2(12)_,,--~
I
5(9)-1
6( 8)
'---__--...It-
I'---__~
L
TIMING SEQUENCE
o
Element 164 Sheet 1 of 2
83313200
A
5-17
SETO---~------------~~
SET
4----
~-+-oQ
J
3
Q
5
CLOCK
K
2
J
II
6
CI:O'CK
CLOCK
K
Q
9
Q
8
13
K 12
~,.,-
~"
('-.
Q
SET
10
(REPEATED FOR EACH FLIP -FLOP)
FUNCTION DIAGRAM
Element 164 Sheet 2 of 2
5-18
83313200
A
C'
INPUT SELECT
BINARY VALU E
Description
The 166 circuit is an 8-bit multiplexer that can
select one bit of data from up to eight sources.
It
COMMON
SELECT
INPUTS
has complementary outputs, an active low enable.
and
intern~l
select decoding.
With the enable in-
active (high) the multiplexer output pin 14 is low and
the complementary multiplexer output pin 15 is high
regardless of all input conditions.
Data is routed
INHIBIT WHEN HI
from a particular multiplexer input to the outputs
o
according to the three input binary code applied to
I
the select inputs.
2
DATA
INPUTS
NOTES:
1.
15
Symbol shown as it would appear on logic
DATA INPUT
DECIMAL VALUE
diagrams.
2.
Type 166 manufactured by Fairchild
Semiconductors (P IN 9312).
3.
Package pin configuration.
TOP VIEW
'n'6+
GND
LOGIC SYMBOL
5V
aUg
COMMON SELECT PIN
13
12
II
0
0
0
0
I
I
I
I
0
0
I
I
0
0
I
I
0
I
0
I
0
I
0
I
INPUT PIN GATED TO
OUTPUT PIN 15
(PIN 10 LOW)
I
2
3
4
5
*
6
7
9
* I. OUTPUT
IS HIGH IF DATA INPUT IS LOW.
2. OUTPUT IS LOW IF DATA INPUT IS LOW.
3. PIN 14 OUTPUT IS REVERSE OF PIN 15.
4. IF PIN 10 IS HIGH, PIN 15 IS LOW AND 14
IS HIGH (REGARDLESS OF SELECT/DATA
INPUTS ).
TRUTH TABLE
o
Element 166 Sheet 1 of 2
83313200
A
5-19
(I)
o---r==::===f-;ll--__
(4)o--tmEEt3e~
r - - - - - - - o (15)
(14)
(6)
o--UfiJffi~0
(13)
(12)
(II )
(10)
FUNCTION DIAGRAM
Element 166 Sheet 2 of 2
5-20
83313200
A
Description
The 172H circuit is a Quad 2-input NOR gate.
NOTES:
1.
Symbol shown as it would appear on logic
diagrams.
2.
Symbol repeated for each gate.
3.
Type 172H manufactured by Motorola
Semiconductor Products, Inc. , (P IN 3002).
4.
Propagation delay time is 6 nsec per gate.
5.
Package pin configuration: vcc l4
8
~TOP
:lJ-c
OR
LOGIC SYMBOL
~VIEW
I
7GND
~j SEAcrr~3
A B C
0 0 I
I 0 0
0 I 0
I I 0
:--------41 SEBcr ~6
I:j SEccrr~ 8
TRUTH TABLE
:: _ _--11
SEDcr ~ I
FUNCTION DIAGRAM
o
Element 172 Sheet 1 of 1
83313200
A
5-21
Description
The 173H circuit is an Quad 2 -input NAND gate with
an open collector output.
NOTES:
1.
Symbol shown as it would appear on logic
diagrams.
2.
3.
Symbol repeated for each gate.
Type 173H manufactured by Motorola
Semiconductor Products, Inc. , (P IN 3004).
4.
The output of each gate is an open collector.
5.
Propagation delay time is 6 nsec per gate.
6.
Package pin configuration:
+Vcc
1t::)48
.
I
A
B
C
0
0
I
0
I
0
I
I
I
I
I
0
:1J-c
OR
LOGIC SYMBOL
TOP
VIEW
7GND
TRUTH TABLE
PIN ASSIGNMENTS
Element 173 Sheet 1 of 1
5-22
83313200
A
Description
The 175H circuit is a dual flip-flop which triggers
on the positive edge of the clock input pulse and performs the type D flip-flop logic function.
This
device consists of two completely independent Type
D flip-flop's, both having direct SET and RESET
PIN
inputs for asychronous operations such as parallel
u
4 (10)
data entry in shift register application.
Information at input CD is transferred to output Q
(pin 5/9) on the positive- going edge of the clock
pulse.
Clock pulse triggering occurs at a voltage
level of the pulse and is not directly related to the
transition time of the positive-going pul3e.
When
the clock is at either the high or low level, the CDinput signal has no effect.
TIMING SEQUENCE
The flip-flop can also be set or cleared directly at
any time regardless of the state of the clock by
applying a low input to the SET or RESET inputs.
NOTES:
1.
C)
Symbol shown as it would appear on logic
diagrams.
2.
3.
Symbol repeated for each flip-flop.
Type 175H manufactured by Motorola
.
Semiconductor Products, Inc .. (P IN 3060L
+Vcc
4.
Package pin configuration:
tj4
S (SET)
TOP
VIEW
I
7
GND
R
{RESEnn--4-+---~
~_--GQ
C (CLOCKD--4-~~~
( /I )
{/3}
LOGIC SYMBOL
CD (DATA) O---------~
FUNCTION DIAGRAM
(EACH FLIP-FLOP)
o
Element 175 Sheet 1 of 1
83313200
A
5-23
Des cription
10
~.
The 176 circuit is a dual differential line driver.
I
'-. .... -,
This circuit accepts a DTL or TTL logic signal and
transmits it over a differential line pair.
output current is typically 12 rna.
current is 100 rna max.
13
I
On state
2
Off state output
The output common mode
voltage range is -3v to +10v' with respect to the
3
12
5
8
6
circuit ground.
4
9
NOTES:
1.
OR
Symbol shown as it would appear on logic
diagrams.
2.
Type 176 manufactured by Texas
Instruments (P IN SN 75110).
3.
Package pin configuration:
TOP VIEW
'ft~~::
GND
7Ua
LOGIC SYMBOL
I
"-r---13
X/Y
2
(~
.."c..--12
...........
3
,------
10
PIN
5
X/Y
6
....----f~---8
....----f~---9
:3
10
FUNCTION DIAGRAM
13
12
LOGIC
INPUTS
1,5
2,6
lOR 0
lOR 0
0
lOR 0
I
I
2
4
lOR 0
lOR 0
lOR 0
0
I
INHIBIT
INPUTS
3,4
10
0
lOR 0
I
I
I
I OR 0
0
I
I
I
OUTPUTS*
9,12
8,13
I
I
0
0
I
I
I
I
I
0
OUTPUT
CONDITION
-----1
&....-_ _ _......
L
_=DON'T CARE CONDITION
TIMING SEQUENCE
INHIBITED
ACTIVE
DATA
STATE
* LOW
OUTPUT REPRESENTS THE CURRENT ON STATE.
HIGH OUTPUT REPRESENTS THE CURRENT OFF STATE.
TRUTH TABLE
5-24
Element 176 Sheet 1 of 1
83313200
A
Description
Circuit
type 182 is a 4 bit binary counter. During -
the count operation, transfer of information to the
outputs occurs pn the negative-going edge of the
clock pulse.
The direct clear (pin 13) when taken
II
low, sets all outputs low regardless of the states of
the clocks (pins 8 and 6).
3
The 182 counter is fully
2
CD
10
programmable; that is, the outputs may be preset
to any state by placing a low ("0") on the count/load
12
CO
9
CD
input (pin 1) and entering the desired data at the
inputs.
I
The outputs will change to agree with the
13
data inputs independent of the state of the clock
inputs.
4
NOTES:
1.
8
Symbol shown as it would appear on logic
diagrams.
2.
Type 182 manufactured by Texas Instruments
(P /N SN 74197) or Signetics Corporation
LOGIC SYMBOL
(P /N 8291).
VCC I4
3.
8
~TOP
Package pin configuration
~VIEW
I
7
GNO
o
COUNT
0
I
2
3
4
5
6
7
8
9
10
II
12
13
14
15
PIN
OUTPUT
Qo Qc Os OA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I
I
0
I
I
I
I
0
0
0
I
I
0
I
I
I
I
I
I
I
I
0
0
0
0
0
0
I
I
0
0
0
0
I
I
I
I
I
I
I
Ir,------------------------------------131
L
8~
5,6~
9~
2 _____---'
12 _______________________
~
I
~r_L
I
I
I
0
I
I
I
0
I
TRUTH TABLE
COUNTER
APPLICATION
I~
:
13U
8
GATE 0 INPUTS
U
I
H~SET
REG TO ZERO
I
4~
•
5~
10~
.
9~r'--~__________
3 _____________
~
2 ____~--------~r--II
---1
12----1
REGISTER
APPLICATION
TIMING SEQUENCE
(WITH PI NS 5 AND 6 WIRED TOGETHER)
Element 182 Sheet 1 of 2
83313200
A
5-25
DATA A
4
COUNT/LOAD
PRESET
QA
T
CLEAR
CLOCt< I
5 QA
CLEAR
8
DATA B 10
PRESET
ClOCt< 2
6
·Qe
T
9 Qe
CLEAR
DATA C
3
r'"""'
PRESET
Qc
"
2
"
Qc
DATA D ~I_I--------~+-~-.
b-...---+----~
PRESET
Qo
12 Qo
FUNCTION DIAGRAM
Element 182 Sheet 2 of 2
5-26
83313200
A
c:
Description
Circuit type 191 is a BCD-to-decimal (1 of 10) decoder. Four active high BCD inputs provide one of
ten mutually exclusive active low outputs. When a
binary code greater than 9 is applied, all outputs
X~Y
are high." This facilitates BCD to decimal conver-
DC9R
sions and eight channel demultiplexing and decoding.
7
6
5
4
The 191 circuit can serve as a one of eight decoder
3
with the D input acting as the active low enable.
9
Eight channel demultiplexing results when data is
addressed by inputs A, B, and C.
II
12
13
OUTPUT
DECIMAL
VALUE
NOTES:
1.
10
INPUT
BINARY
VALUE
applied to the D input and the desired output is
Symbol shown as it would appear on logic
LOGIC SYMBOL
diagrams.
2.
Type 191 manufactured by Fairchild
Semiconductors (p IN 9301).
3.
Pin
1,2,14,15
Function
Address inputs
3-7,9-13
Outputs (active low)
+Vcc
4.
Package pin configuration:
0 1 69
TOP
VIEW
I
8
GND
INPUT PIN
2
0
0
0
0
0
0
0
0
I
I
I
I
I
r
I
I
I
0
0
0
0
I
I
14
0
0
I
I
0
0
r
r
I
0
0
0
0
I
I
I
I
I
0
0
I
I
0
0
I
I
* =ALL
15
0
I
0
I
0
I
0
I
0
I
0
I
0
I
0
I
LO ("0") OUTPUT PIN
(OTHER OUTPUTS ="I"
13
,12
"
10
9
3
4
5
6
7
***
**"X
OUTPUT PINS HIGH
TRUTH
TABLE
Element 191 Sheet 1 of 2
83313200
A
5-27
OUTPUT
INPUT
PIN
15
INPUT A
i
(BINARY)
PIN
OUTPUT 0
13
OUTPUT I
12
"
3
14
10
INPUT B
B
9
C
4
INPUT C
5
2
INPUT 0
o
6
7
FUNCTION DIAGRAM
Element 191 Sheet 2 of 2
5-28
83313200
A
C~
Description
The 193 circuit is a retriggerable monostable multivibrator. Triggering the input before the output
pulse is terminated extends the output pulse duration.
The overriding clear input (pin 3 111) permits
any output pulse to be terminated at a predetermined
13
I
tim e independently of the timing network.
2
3
4
9
5
Successive triggering inputs having a period shorter
than the delay time produce a constant high output.
10
1.
Symbol shown as it would appear on logic
TIMING,
NETWORK
diagrams.
2.
Type 193 manufactured by Texas
Instruments (P IN 74123)·.
+Vcc
3.
12
II
NOTES:
Package pin configuration:
0
16
LOGIC SYMBOL
9
TOP
VIEW
I
8
GND
(--''\
~)
PIN
RETR!GGERS
(9 )
2 (10)
2------t
Q
13
Q
4
Q
5
Q
12
3 (II)
3---------------~CLEAR
13 ( 5)
4
*
(j)
®
(12)~
'----_ _ J~
PULSE DURATION IS A FUNCTION OF THE RC
TIMING NETWORK.
OUTPUT HELD HIGH DURING RETR/GGER PULSE.
OUTPUT TIMES OUT FROM EDGE OF LAST
TRIGGER PULSE.
TIMING SEQUENCE
9
IO--------~
II
--------------~
CLEAR
FUNCTION DIAGRAM
Element 193 Sheet 1 of 1
83313200
A
5-29
Description
TIMING
NETWORK
2
The 195 circuit is a dual monostable retriggerable
6
multivibrator that provides an output P?lse whose
duration is a function of external timing components.
Input pins 4 and 12 trigger on the positive going edge
of the input pulse and pins 5 and 11 trigger on the
negative going input pulse.
The 195 circuit will re-
trigger while in the pulse timing state (pin 8 high)
14
and the end of the last pulse will be timed from the
last input.
TIMING
NETWORK
A low level to the reset input (pin 3 (13)
resets pin 6 110 to low level and inhibits data inputs.
LOGIC SYMBOL
NOTES:
1.
Symbol shown as it would appear on logic
diagrams, except for timing network.
2.
Type 195 manufactured by Fairchild
Semiconductors (P IN 9602).
3.
. conf·19urat·lone+VCC
P ac k age pm
16
:t
9
~TOP
'n-nrrru.J VlEW
I
4.
H
= high
8
GND
= low
level (steady state), L
high level,
~
level
Q
t = transition from low to
(steady state),
= transition
X
r-'
('-.
from high to low
13
---------------~R
level,Sl. = one high-level pulse, l.S = one
low level pulse,
10
= irrelevant
Q
9
(any input,
including transitions).
FUNCTION DIAGRAM
5.
Output pulse width (
t = 0.32 Rx C x
t ) is
defined as follows:
[1 + ~·x7]
Rx is in Kn, C x is in pi,
t is
in ns
PIN
5
INPUTS
A
B
Q
~
H
X
L
L
L
H
X
L
-l-
t
H
_-.:.....__--In'--__. . .n=RETRIG~
OUTPUTS
Jl.
Jl.
4
I
H
3
l.S
li
6
7
TRUTH TABLE
(SEE NOTE 4)
*
PULSE DURATION IS A FUNCTION OF THE
RC TIMING NETWORK.
TIMING SEQUENCE
Element 195 Sheet 1 of 1
5-30
83313200
A
Description
"
C
/
The 200 circuit is a hex inverter buffer/driver with
x/v
an open collector output.
200
2
4
NOTES:
1.
6
Symbol shown as it would appear on logic
diagrams (symbol sections may appear
OR
8
separately).
2.
Type 200 manufactured by Texas
10
Instruments (P /N 7406).
3.
Propagation delay time 10-15 nsec typical.
4.
Package pin configuration.+vccH
12
8
~TOP
'n-nnnra1 VIEW
I
o
7GND
LOGIC SYMBOL
Element 200 Sheet 1 of 1
83313200
A
5-31
202S
Information not available at time of printing.
It will be supplied at a later revision.
5-32
83313200
A
307
Information not available at time of printing.
It will be supplied at a later revision.
o
o
83313200
A
5-33
Description
The 321S is a dual differential comparator.
Output,
pin 10, is high when either pin 2 is at a lower potential than pin 3 and pin 13 is high, or pin 6 is at a.
2
lower potential than pin 5 and pin 9 is high.
3
A low
'" ]
level to pin 9 or 13 will inhibit operation of that
13 r--...
section which it controls.
6
r>/Y
321S
1
'" ]
5
NOTES:
1 --1Q.
r>/Y
91".....J
1.
Symbol shown as it would appear on logic
diagrams.
2.
LOG IC SYMBOL
Type 321S manufactured by Transitron
Electronics (P IN TSC 5711).
Package pin r.onfiguration.
3.
GND +Vee
NC ~"
NC
E5
12341117
NC
t
NC
-Vee
2,6
3,5
13,9
_ _ _- I
I
I
I
I
I
I
I l___----'n_____
10 _ _.......
FUNCTION SEQUENCE
Element 321S Sheet 1 of 1
5-34
83313200
A
339
Information not available at time of printing.
It will be supplied at a later revision.
83313200
A
5-35
Description
The 502 circuit is a 8-bit parity generator/checker
with complementry outputs and control inputs to
8
facilitate operation in either odd-or even-parity
9
8
00
applications.
000
502
6
NOTES:
1.
9
502
Symbol shown as it would appear on logic
5
5
OR
6
diagrams.
2.
Type: 502 manufactured by Texas
Instruments (P /N SN74180).
3.
,tVCCt:j
, con f'IguratlOn.
Package pIn
TOP
VIEW
I
INPUTS
7GND
OUTPUTS
~ OF 1'5 AT PINS
I, 2, 8 THRU 13
PIN
PIN
PIN
PIN
3
4
5
6
EVEN
ODD
EVEN
ODD
I
I
0
0
I
I
I
I
0
0
0
0
X
X
LOGIC SYMBOL
I
0
0
0
I
I
0
0
0
I
I
I
X= IRRELEVANT
TRUTH TABLE
2
ODD INPUT
EVEN INPUT
4o---------------------------------------~
3o-------------------------------------------~
FUNCTION DIAGRAM
5-36
Element 502 Sheet 1 uf 1
83313200
A
Description
The 519 circuit is a register made up of hex D-type
flip-flops with clear input.
NOTES:
1.
Symbol shown as it would appear on logic
diagrams.
2.
Type 519 manufactured by Texas
Instruments (PiN SN 74174).
3.
Package pin configuration.+ Vcc I6
'9
~TOP
~VIEW
8
I GND
LOGIC SYMBOL
CLEAR
CLOCK
9.
IU
U-
n
DATA
3,4,6.
INPUT
11,13,14
DATA
2,5,7
OUTPUT 10,12,15
n
rLnJ
•
n
•
•
= DONIT CARE
FUNCTION SEQUENCE
Element 519 Sheet 1 of 2
83313200
A
5-37
('
\
' ..
4
DATA
INPUTS
6
D-----t--It----t
DATA
OUTPUTS
II
13
Q
CLOCK
~--+-+-...I...,;lC>
15
CK
CLEAR
CLEAR
I
FUNCTION DIAGRAM
Element 519 Sheet 2 of 2
r
'-....,
5-38
83313200
A
916
Information not available at time of printing.
It will be supplied at a later revision.
o
83313200
A
5-39
926
Information not available at time of printing.
It will be supplied at a later revision.
5-40
83313200
A
C",'
I
986
Information not available at time of printing.
It will be supplied at a later revision.
()
L)
"'-"',
83313200
A
5-41/5-42
SECTION 6
DISCRETE COMPONENT CIRCUITS
c·
c:
c'
GATED AMPLIFIER - FAE
The FAE circuit consists of two matched
transistors acting as low level analog gates.
Inputs A and B receive the output of differential windings of a read head. Output
points nand E drive the input of a low level
amplifier such as an FAF. The outputs are
gated by input C. When point C is at -9
volts, QN and QP turn on enabling data to
flow from points A and B to C and D respectively. At +20 volts on point C, QN and QP
turn off, inhibiting the output.
A
B
, - - - - - - - - + 20V
C
-9V
Of'
o
I.OMV
.;
'1\
tOMV
*
o
A
E
B
HRI
PR2
10K
10
c
NOTE:
83313200
A
VOLTAG E
AN 0 COM PONENT VALU ES ARE
FO R R EFEREN CE
ONLY.
701 10
6-1
AMPLIFIER - FAF
The FAF circuit is a low level amplifier
that amplifies analog read signals. Points
A and B are typically connected to Gated
.
Amplifiers which provide biasing for the
common ·base input stage.
gain of the second stage is approximately 20,
therefore, the overall amplifier gain is
approximately 180.
c
DC feedback is provided by NR9, NRlO,PR2 and
QRl to the base circuitry of the QN matched
pair. This feedback helps to stabilize the
DC operating points in the circuit. Capacitor NCl provides a lower impedance path between bases of the input transistors which
presents a low amplifier input impedance for
AC signals over the passband of the amplifier.
The amplifier consists of two stages, common base first stage (QN matched pair) and
common emitter second stage (QR matched
pair) with emitter follower outputs (QS and
QT) for low output impedance. The gain of
the first stage is dependent upon the signal
source resistance and is approximately 9·
with 9750 type heads as a signal source. The
A
B
C
D
",--------
NR9
14.7K
ON/2
t'-. -
+9V
OS
OP
SR3
22
A
C
+9V
NR4
Nel
0.033 IK
Jl-F
NR6
845
NR8
820
-=
NR5
IK
SR2
1.8K
OR/3
RCI
O.OIJl-F
NC2
3.3PF
NR3
383
RRI
681
PR2
2.15K
NR7
845
ORI
2.15K
IRR3
= IK
RR5
31.6
TRI
1.8K
TR3
22
":-
-9V
D
OT
00
B
ON/2
+ 9V
NRIO
14.7K
NOTE:
VOLTAGE AND COMPONENT VALUES ARE
FOR REFERENCE ONLY.
+9V
70111
(:
6-2
- 83313200
A
c~
CONTROLLED VOLTAGE SOURCE - FAG
The FAG circuit is a controlled voltage
source providing a controlled voltage to
Write Driver - JAG.
sistor buffer is included in the negative
feedback circuit to reduce the output voltage change due to temperature variation.
The circuit consists of an operational am~
plifier and a two transistor buffer extends
the output current capability. The tran-
The output at B (VB) is related to the two
inputs VR and A(VA) by the following expression: V = V
+
XR2 V
XRl
A
B
R ~ X~
tl
xm _
TP
A
t>
B
FAG
14.BV
14.45V
-
14.IOV
---
B
I 2. 70V - - - - - - - -
+20V
REGULATED
VOLTAGE (11.8: .2V)
+ VR
TP
PRI
NRI
270
PR3
6.2
IK
A
B
XR 2
10K
+
PCI
~I
NOTE:
VOLTAGE
83313200
A
AND COMPONENT VALUES
ARE
FOR
REFERENCE
ONLY.
701128
6-3
VOLTAGE SWITCH - FBH
The FBH is a voltage switch which transfers
a voltage at input B to output C when QP is
turned on by the proper voltage condition at
input A.
In a typical circuit the voltage at input B
is +12 volts. With 0 'volts applied to input
A, transistor QP turns on and output C goes
to +12 volts. When input B is open (as when
connected to an open collector IC that is
turned off) QP will turn off and output C
will be disconnected from input B and return
to any quiescent potential in the circuit it
is connected to.
A
,....-----......;--- + 12 V
OV
A~,
+12V
B
OV
B~C
+-12V
C
OV
c-'
C
NR 1
A
1.2K
NR2
820
B
r-------------------~--------------~----. + vR
NOTE:
VOLTAGE
6-4
AND COMPONENT VALUES ARE FOR REFERENCE ONLY.
83313200
A
LOW PASS FILTER AND AMPLIFIER - GJK
The GJK circuit consists of a bidirectional
current pump, a filter, and a level shifter.
The circuit converts TTL input signals from
a comparator circuit and integrates these
signals to produce a dc voltage level at
output B.
Because of the phase locked
oscillator closed loop, the current pump
drives the dc level at point D to reach a
steady state when the signal at input A is a
square waveform. Frequency synchronism has
been achieved at this point. A change in
data frequency (duty cycle) causes a change
in average ac voltage across NRF.
input A, NCA alternately is charged and discharged by 5 rna. The charge/discharge times
under normal operating conditions are long
compared to the input pulse times, therefore, the voltage across NCA has very little
ac component in it.
Resistor NRF generates an ac component to
ride on the dc voltage existing across NCA.
This ac component is controlled by the value
of NRF and the currents from the bidirectional pump. The net result at the base of
OR is a dc voltage which corresponds to a
particular input data frequency with a
square waveform.superimposed on it for phase
synchronism purposes.
NRC, NVRA, and NRE form a reference voltage
divider for the current pump. NRD and OP is
the negative-going current sink. This sinks
a current of approximately 2 rna continually.
NCRA, NRA, NRB, and ON form a switchable
current source of approximately 15 rna. When
a square wave TTL logic level is applied to
QR, NCRB, NCRC, and NRG form a buffer and
level shifting circuit. They shift the
waveform at the base of OR negatively to a
level appropriate for voltage control oscillator frequency.
TP
+3V
Jr>
OV
GJK
A
B
()
-3V
0.4V
NRH
280
TP
+5V
NRB
562
NRA
SEL
NCRA
NRC
178
POINT D
A
NRF
120
QN
TP
NVRA
2.7V
QP
NRG
47
B
-5V
TP
NOTE: VOLTAGE AND COMPONENT VALUES ARE FOR REFERENCE ONLY.
701170
o
83313200
A
6-5
DIGITAL TO ANALOG CONVERTER - GKF
The GKF circuit converts three digital input
signals to an analog output whose level depends upon the logical combination at the
inputs.
The element 200 is an open collector Ie.
When pin 9 of element 200 is +3 volts or a
"I", its output (pin 8) is 0 volts. When
pin 9 is 0 volts or a "0", its output (pin
8) is open and the resistor divider (XR4,
XRIO, XR13, etc.) to V determine the voltage at an identical maftner but have less
influence on the voltage at point D because
of their entry connection in the resistor
network.
When V is +12 volts the output at D corresponaing with the various combinations of
logic input is as shown in the waveform
diagram.
, - - - - - - +3V
A
OV
+3V
8
OV
+3V
C
OV
+9.BV
A~~X/~r-
B
GKF
+ B.!5V
+7.IV
+ 5.BV
0
C
+4.5V
,/ -'-
(
+ 3.IV
+
\
I. BV
"----- + .5V
+ VR
+5V
XRI
2.2K
9
C
XRIO
IK
(
8
EIE4
XR6
IK
XR2
2.2K
II
XR7
IK
XRII
IK
10
200
+5V
A
XRI4
IK
EIE4
XR9
IK
XRB
IK
XRI2
IK
12
XRI5
1.96K
200
EIE4
NOTE'
VOLTAGE
6-6
0
XRI3
IK
200
+!5V
8
XR5
IK
XR4
IK
AND COMPONENENT VALUES
ARE
FOR
REFERENCE ONLY.
7JI4
83313200 B
..
DIFFERENTIATOR/AMPLIFIER - HAQ
The HAQ circuit consists of a passive RC
network (used as a differentia tor and a differential amplifier) to boost the attenuated
signal level.
sink QQ
and QS.
emitter
capable
100 ohm
current
The HAQ, inputs A and B, are connected to
outputs D and E of circuit HAP, which supplies an amplified read head signal. NCl,
NRl, and NR2 make up the differentiator
which has a break frequency at 15 MHz.
direct coupled to second stage QR
QT, QU and QV, QW form darlington
followers for low output impedance
of driving coax lines terminated by
resistors. QX and QY are constant
sources.
NRll and NR12 provide AC/DC feedback from
the output to input emitters of the first
stage. Closed loop voltage gain is proportional to the ratio, NRll to NR4 (and
NR12 to NR7). Capacitor NC4 provides rolloff at the upper cutoff frequency.
The two stage differential amplifier consists of first stage QN and QP with current
1.6 MHZ
T100MV
A
--*-
t
100MV
B
J..
A:E:
B
] HAQ [
-,-
750MV
c
0
C
-L
0
-,
750 MV
-*+IOV
NC3
(=)
0.01
*'
NCI
100 PF
A~
NR3
1.78K
NA4
51.1
NR6
2.151<
NR7
51.1
NRI6
10
NRI8
10
NR Ii
1.7BK
NRI8
1.78K
NR23
100
NAIO
2.37K
NR5
1.7811.
NA2
2.15K
NR21
100
NRI5
1.18K
NRI
IK
NR II
2 . 15 K
o
L..-+_---'
NRI2
2.15K
NRI3
2.371<
NRZO
1.33K
- 10 V +-......-JVl"-"--..c:
-IOV
-IOV
NCRI
NRI4
2.61K
-ZOV
NOTE:
VOLTAGE
83313200
B
AND COMPONENT
VALUES ARE
FOA
REFtRENCE ONLY.
1,11010
6-7
RECTIFIER - HBA
The HBA circuit performs full wave rectification on a differential input signal.
alternating positive halves to appear at
point C (waveform C) .
The rectifier consists of QN and QP (matched
transistors in an IC array) which are base
biased at ground potential by NRl and NR2.
With no· signal input, point C rests at -.7
volts. NR6, NR8, NR9, and QS form a current
sink network which provides the collectoremitter current for QN and QP.
Network NRS, NR7, NR10, and QR set up a DC
reference voltage at point D which matches
the "no signal" DC voltage at point C (QN,
QP, and QR are an IC transistor array) .
r\.
TCRl, TVRl, TCR2, and TVR2 form a voltage
clipping network to prevent overvoltage
damage to reverse biased base-emitter junctions of QN and QP.
When a differential input signal (amplified
read head output) is present at A and B,the
rectification action of QN and QP cause the
A~---4~--~----~--~~--~----,-
B~--~----~---+----T----T----~
C
~
__
~
__
~
____
~
__
~
____L -__
~~
__
--.7V
D~------------------------------------------.7V
c
A
NR6
1.2K
TVRI
3.6V
NRI
464
NR7
464
NR3
~60
NR~
'::'
~60
-12V
+12V
TCRI
NR2
464
D
NR4
~60
NRIO
6.8K
B
- 20V
NOTE:
VOLTAGE
AND COMPONENT VALUES ARE
FOR
REFERENCE ONLY.
7.JI04A
6-8
83313200 B
RECTIFIER - HBB
The HBB circuit performs full wave rectification on a differential input signal.
alternating positive halves to appear at
point D (waveform D) .
The rectifier consists of QN and QP (matched
transistors in an IC array) which are base
biased at -5 volts by NRl and NR2. With no
signal ihput, point D rests at -5.7 volts.
NR9, NRlO, NRll, and QS form a current sink
network which provides the collector-emitter
current for QN and QP.
Network NR4, NR5, NR6, NR7, and QR set up a
DC reference voltage at point C which proportionally tracks the "no signal" DC voltage
at point D (QN, QP and QR are an IC transistor array).
When a differential input signal (amplified
read head output) is present at A and B,the
rectification action of QN and QP cause the
TCRl, TVRl, TCR2, and TVR2 form a voltage
clipping network to prevent overvoltage
damage to reverse biased base-emitter junctions of QN and QP.
If
v
A
::d]IH:a'
~
t:
If
B
v
~
C
---L
-S.7V
1/2V
-S.7V
T
D
I'r-\I
'-./
NR3
100
NCI
1200PF
A
NR4
6.19K
ON
C
0---1
NR6
4.7K
NR5
261
TCR2
TVRI
4.IV
-20V
NRI
464
NR7
464
-5V
NC2
1200PF
TVR2
4.IV
TCRI
-=
NR2
464
QP
D
Bo----1
NRIO
I.SK
-20V
-=
NOTE:
VOLTAGE AND COMPONENT
VALUES
ARE FOR
NRII
2.7K
REFERENCE ONLY.
7JI03A
83313200
B
6-9
DIFFERENTIAL AMPLIFIER - HCA
the voltage on input A is less than at B,
the current from NR2 goes through OP to output C. When input A equals input B, the
current from NR2 is split between ON and OP.
The voltage at point C is established by the
current through OP times resistor NR3. Point
C is the control voltage input for input E
on the HCU (AGC amplifier) circuit. NCl is
used as an integrator and helps stabilize
the response time.
The HCA circuit is a differential amplifier
which is used as a control element in an
AGC amplifier feedback loop.
Input B is connected to a fixed reference
voltage and input A is connected to an integrated DC voltage which is proportional to
the output amplitude of an AGC amplifier.
When the voltage on input A is greater than
that at input B, the current from emitter
resistor NR2 goes through ON to ground. When
- 5.8V
A
~--""I.-
- - --
- - ---
- 6.0V
-6.2V
B ~----~-------------------------
- 6.0V
-O.OV
I
I
-I - - - - - - - - - -O.2V
- - - - - - O.4V
NRI
IK
A
NR3
499
NCI
IOOOPF
B
C
NOTE:
VOLTAGE
AND
COMPONENT
VALUES
ARE
FOR
REFERENCE
ONLY.
7JI0I
r
"--
6-10
83313200
B
.
DIFFERENTIAL AMPLIFIER - HCB
r--,
r
"-..1
,
The HCB circuit is a single stage differential input, differential output amplifier.
QR, NR5, NR6, and NR8 are a current sink
network which provides collector current for
QN and QP.
QN and QP are the amplifying transistors.
The gain of the amplifier is largely determined by ~he ratio of NR9 to NR2 and NR7 to
NR4.
QS and QT with emitter resistors NR12 and
NR13 are emitter followers for low impedance
.outputs.
A ~--~----~--~~--~----~----~
B ~--~----~--~~--~--~~--~-
If
v
*If
~---+----~----r---~~--~----~
G(V)
D ~--~----~----~--~~--~----~
G(V)
C
J,
t
.J,
NRII
330
NRIO
100
c
NR9
1.47K
"::"
NRI
100
NR2
51.1
NRI2
J.BK
NRB
1.2K
-20V
+12V
"::"
NR4
51.1
NR6
I.BK
NRI4
100
-12V
NOTE:
VOLTAGE
AND
COMPONENT
VALUES
NRI3
I.BK
NR7
1.47K
ARE
FOR
REFERENCE
D
ONLY.
7 J97
83313200
B
6-11'
BUFFER AMPLIFIER - HCE
The HCE circuit is a differential buffer
amplifier with a gain of approximately one.
With the proper bias conditions, inputs A
and B can be connected to a circuit such as
a differential amplifier output. The effect
would be to increase its load driving capabilities'without adversely loading down the
output signal.
.
::J]:CE[t:
Emitter followers QN and QP present comparatively high input impedance at A and B, and
low output impedance at C and D. Current
sources QR and QS with NR3, NR4, NR5, and
NR6 supply constant emitter current to QN
and QP.
A
~.2V
8
~.2V
c
~.2V
0
~.2V
/".--
.........
(
"
C
A
NR3
2.2K
NR4
I.BK
NR5
IK
-IOV
+20V
-=
NR6
IK
8
o
NOTE:
VOL TAGE
A NO
COMPONENT
VALUES
ARE FOR
REFERENCE
ONLY.
7.1911
c.
6-12
83313200 B
BUFFER AMPLIFIER - HCF
"'~
C--
The HCF circuit is a differential buffer
amplifier with a gain of approximately one.
With the proper bias conditions, inputs A
and B can be connected to a circuit such as
a differential amplifier output. The effect
would be to increase its load driving capa-
bilities without adversely loading down the
output signal.
QN and QP are emitter followers which present comparatively high input impedance at
A and B, and low output impedance at C and
D.
NRI
A
C
220
NR3
2.2K
"--~+20V
NR4
NR2
2.2K
220
B
o
NOTE:
VOLTAGE
AND
COMPONENT
VALUES
ARE
FOR
REFERENCE
ONLY.
7J9!5
83313200
B
6-13
VOLTAGE FOLLOWER - HCK
The HCK circuit consists of an operational
amplifier in a voltage follower configuration. An NPN emitter follower (OP) is
enclosed in the feedback loop to provide a
voltage output at B equal to the input at A
with increased current handling capabilities.
Enclosing OP in the feedback loop also negates the change in output due to tempera-
ture related voltage variations of the baseemitter junctions of OP.
NR2 provides a minimum load current for OP
under no output load conditions. NRl is a
current limit resistor.
Resistor NR3 and
capacitor NRl stabilize the circuit.
+ 12V
+20V
NRI
560
A
NR3
220
B
NR2
4.1K
-20V
NOTE
VOLTAGE
6-14
AND
COMPONENT
VALUES
ARE
FOR
REFERENCE
ONLY.
7JI05
83313200 B
INTEGRATING AMPLIFIER - HCL
The HCL circuit converts a rectified signal
input to a DC output that is an average
value of the input signal waveform.
The integrating elements are NR2, NR3, and
NCI. The analog signal (rectified waveform)
is entered at input A. With digital voltage
control at input B, QN can be turned on
which would bypass NR2. This would leave
(NR3) X (NCl) to determine the relatively
short response time of the integrator. When
QN is turned off, NR2is included in the
integrating circuit and the (NR2 + NR3) X
(NCl) long response time results. QP (element 531) is an operational amplifier connected in a voltage follower mode of operation and acts as a buffer amplifier. NC3
is a compensation capacitor for QP.
---4V
---sv
A
........-L.....&.-.lI-L..I-.I.....I--'--'-...............a.....:L...&.-L.....&.-.l1....l - - -
5.7 V
r------- -- + 5V
B
~---------~
---------------S.5V
~------ - - -4.7V
c
- - - - - - - - - - - - - - - -5.3V
+IOV
A
NC2
*t1'~F
NR2
NRI
47K
330
033fLF
NR3
B
7
IK
C
'--~-IOV
1.
NC4
0'fLF
NOTE:
VOLTAGE
AND
COMPONENT
VALUES
ARE
FOR
REFERENCE ONLY.
7JI02
o
83313200
B
6-15
LOW PASS FILTER - HCP
QN and QP with their emitter and base resistors form the buffer amplifiers for driving
the relatively low input impedance filter.
The HCP circuit is a low pass differential
filter with a buffer amplifier input (emitter followers).
The filter provides attenuation of high unwanted frequencies (noise)
in the read back signal with a linear phase
response over the frequencies concerning
read data.
The upper cutoff frequency of the filter is
approximately 5.5 MHz (media compatible data
rate of 6.44 MHz). The signal attenuation
from inputs A, B, to outputs C, D is about
50% at 1 MHz.
NL1, NL2, NC3, NC4, NL3, and NL4 make up the
differential filter with outputs at C and D.
NR9 and NR10 are terminating (impedancematching) resistors for the filter.
NR5 and
NR6 are impedance matching resistors to the
input of the filter.
IMHZ
A ~--~----~--~~--~----~----~--
fV
J,
l'
B r---~----~---T----~--~~--~---
V
*
If'
1/2 v
C
{~..
If'
D
NCI
OILLF
A
"
{-
NRI
220
~
C>--i t--........---'V'V'v-----,
r
I
1/2v
NR5
121
NR3
1.5K
NLI
5.6f/-H
NL3
2.2f/-H
C
NR7
2.2K
NC3
180PF
NC4
240PF
+20V
-IOV
NR8
2.2K
NR4
1.5K
NC5
.01
-r
NR9
121
NRIO
121
D
NR6
121
NL2
5.6f/-H
NC2
.Olf/-F
B
C>----1
t------'lNv-----'
NOTE;
VOLTAGE
AND
COMPONENT
VALUES
ARE
FOR REFERENCE
ONLY.
7JI06
6-16
83313200
B
-----
FILTER AND AMPLIFIER - HCQ
The HCQ circuit is a differential, 2 pole
low pass filter followed by a differential
amplifier with a gain of approximately 2.5.
NL1, NC3, and NL2 make up the 2 pole low
pass filter.
The upper cutoff frequency is
approximately 2.5 MHz for media compatible
data rate (6.44 MHz). NR6, NR9, NR12, and
NR14 are impedance matching resistors for
the filter.
QN and QP are bu~fer amplifiers (emitter
followers) for driving the relatively low
impedance filter.
QR, QS, and their associated circuitry perform dual roles as differential buffer amplifiers (emitter followers) and as differential
amplifiers. Outputs C and D are the buffered
outputs that connect to level detection circuitry with further amplification. Outputs
E and F are amplified outputs which connect
to a zero cross network (low resolution
channel). This signal channel is amplified
to make up for the attenuation loss of the
filter. The gain of the amplifier is largely
determined by the ratio of RR2//RR3 to RR4
and SR2//SR4 to SR3.
DELAV
TP
/'........"
~.)
C
Jr>
A
Iv
e
Iv
C
X .2V
D
~
E
E
F
55V
F
NR6
121
NR2 +5V
IK
RRI
220
E
NC3
200PF
Rei
SR5
470
4700PF
SR4
560
-5V
NR8
470
NR9
121
83313200 B
TP
RR3
560
+5V
SR2
383
NOTE:
VOLTAGE
C
NR7
470
-=
NR4
IK
.2V
1m
1
0
HCQ
B
TP
A
F
NC6
.0 33fLF
NRI4
121
SRI
220
SR3
82
D
AND COMPONENT VALUES ARE FOR REFERENCE ONLY.
7JII28
6-17
AGC AMPLIFIER - HCU
The HCU circuit is a differential amplifier
with gain controlled by a negative voltage
at input E.
equally, causing out of phase voltage to
cancel, leaving a net output or gain of 0
volts.
Increasing the control voltage negatively starts turning off QT and QV causing
the amplifier gain to increase. Turning off
QS, QT, QU, and QV requires that the control
voltage be approximately -O.S volts, which
allows an amplifier gain of 10.
QP and QR are amplifying transistors with
their maximum gain determined by the ratio
of NRIO to NRS and NRll to NR4.
Common base amplifiers, QS, QT, QU, and QV
pass amplified current signals to resistors
NRIO and NRll. QS and QT pass out of phase
signals to collector resistor NRIO. Likewise, QU and QV pass out of phase signals
to collector resistor NRll.
Emitter followers QX and QY provide low output impedance.
QN, NR1, NR2, NR3, and TCRl make up a current sink network which controls the collector current of OP ~nd QR.
Control voltages on the bases of QT and QV
control circuit gain. With 0 volts for control voltage, QS, QT, QU, and QV turn on
NR2l and TVRI form a -IS volt regulated voltage for the current sink circuit.
--L
VI
-,---*-VI
A
B
-,-
C
B
0
E
NCI
O.OlfLF
I
AO
I
,
1
~
~
10V,
0'
'
--r
I
I
I
,
I
,
,
I
I
E,
I
:
10V,
--r
NR6
2.151<
'
I
t
'Jl
ru
--L
E
,
I
EXPANDED
WAVEFORMS
-.5V
0
I
I
Bln
-OV
C
A
AI KI . )I
;-- ........
(,
NR8
51.1
-20V
NR9
220
NR5
82.5
C
NC3
22PF
NR2
IK
TVRI
15V
NRI2
220
NR3
1.96K
0
NR4
82.5
NRI6
B
O____--;t-_ _......._"""~+_---AJ'2.""2.....K -........-~-lov
E
NOTE,
VOLTAGE AND COMPONENT
6-18
VALUES
ARE FOR
REFERENC~
ONLY.
1JIISI
83313200
B
HJM
Information not available at time of printing. It will be supplied at a later
revision.
o
o
83313200
B
6-19
IeD
l
Information not available at time of printing
It will be supplied at a later revision.
6-20
83313200
B
WRITE DRIVER - JAG
Write driver JAG is a differential voltage
switch which converts voltage (across termination resistors) to current to drive a
differential recording head.
URI) to termination resistor SR2 and current
to output E. When A is low and B is high QN
and QS turn off, QP and QT turn on applying
voltage to termination resistor TR2 and current to output F. Current sensing network
URI, UR2, UCRI and QU supply current at G
which is used for fault detection. NCRl,
NCR2, PCRl, PCR2 prevent QS and QT from
saturating when the write driver is turned
off. SCRl, SR3, TCRl, and TR3 provide back
biasing of the write matrix diodes du~ing a
write operation.
Circuit operation is dependent upon signal
level shifter QQ converting an open collector
TTL output of "0" or "1" to turning QR "off"
and "on". With QR on, -5 volts flows through
QR and NRI to supply current for the differential switches QN and QP. With input A
high and Blow, QN turns on and QP is off.
QN turning on causes QS to turn on which
applies a voltage (from D through UCRI and
+3V
A
TP
OV
+3V
TP
B
OV
+1.5V
A
C
OV
+14V
E
B
C
F
JAG
D
G
OV
+IIV
TP-A
OV
+ IIV
TP-B
OV
5MA.
0
G
o MA.
TP-A
SR2
56.2
NCRI
E
as
URI
10
A
SRI
390
UCRI
SR3
4.7K
-5V
D
Vw
TRI
TR3
4.7K
390 aT
B
G
TR 2
56.2
F
PCR2
TCRI
':'
C
NOTE:
o
83313200 B
I.
VOLTAGE
2.
WAVE FORMS ABOVE ARE FOR REFE RENCE ONLY AND VALl D ONLY
WH EN
OUTPUTS
E AND F ARE
CONNECTED TO
A READ/WRITE HEAD WITH
CENTE R TAP TO GROUND.
AND
COMPONENT
VALUES
ARE
FOR
REFERENCE
ONLY.
7J ZI
6-21
JAL
Information not available at time of printing.
It will be supplied at a later
revision.
C~
6-22
83313200 B
AUTO NULL CIRCUIT - JAM
The JAM circuit provides a DC null for the
AC signal on line AB. This circuit compensates for a fluctuation in DC reference of
the AC signal due to temperature and chipto-chip parameters.
The operational amplifier senses the DC
level on line AB and compares this voltage
level against a zero volt reference. It then
supplies the proper DC current to maintain a
DC null on line AB.
NR3
10K
J<.A A
Vyy
\1
N'dl
.01 J.LF
A ~~----+-------------~~---+----~--~~-o-B
~NRI
~IK
L-.c
-==
r----
]
,v
~NR2
~IOK
[>
306
;:~ NC2
.IJ.L F
-14
NOTES:
VOLTAGE AND COMPONENT VALUES
ARE FOR REFERENCE ONL~
VALUES CHOSEN PER CIRCUIT REQUIREMENTS.
®
7JI99
83313200
B
6-23
LeI
Information not available at time of printing.
It will be supplied at a later
revision.
\..
6-24
83313200
A
VOLTAGE CONTROLLED OSCILLATOR - MAF/MAH
The MAF/MAH circuit consists of two Schmitt
trigger circuits (QQ, QR and QS, QT) and a
differential switch/current limiter circuit
(QN, QP, NRl, and NR2). The values of capacitor PCl, resistors NRI and NR2, and the
input voltage, determines the output frequency of the circuit. Operating frequency
is listed on the Logic Diagram (see Section
5) •
For the following discussion, assume that
voltage E3 is more positive than E2, E2 is
more positive than El, and EO is the lowest
voltage (refer to Figure 1).
upper Schmitt trigger circuit. Therefore,
QN and QQ turn on and draw current from
terminal D of capacitor PCl. When the voltage at D reaches El, the upper Schmitt trigger circuit switches off. QN switches off
and point C is again raised to E3. This
completes the multivibrator cycle and brings
it back to the initial condition. The cycle
is then repeated.
As input A becomes more negative and output
frequency at B, increases linearly (refer to
Figure 2).
Assume that point C of PCl is more positive
than point D. At this time, QP and QS are
both conducting and QT is off (base-emitter
junction is reverse biased). The output
voltage at B is high. The other half of the
circuit (QN, QQ, and QR) is in the opposite
state at this time.
C)
The D terminal of capacitor PCl is held low
by the forward drop of the base-emitter
junction of QR. Therefore, current through
PCl alters its charge linearly until the
voltage at C reaches the high output voltage.
At this point, the lower Schmitt trigger
circuit (QS, QT) switches off and the out'put
voltage at B goes to ground. QP now switches
off and point C is driven rapidly positive
by the forward biased base-emitter junction
of QS.
At the instant that the lower Schmitt trigger circuit switched off, the voltage at
point D was at E3. The sudden increase of
point D to E3 potential reverse biases the
base-emitter junction of QR and triggers the
~
~
6
~
OUTPUT FREQUENCY IS
LINEAR WITH INPUT
VOLTAGE
I
--- i
1-----1
NOMINAL INPUT VOLTAGE
ri
3.2
-2V
I
I
-3V
-4V
Figure
2
Diode PCR3 prevents the emitters of QN and
QP from falling to a voltage that would
cause both transistors to conduct when power
is first applied. Such a condition would
prevent the circuit from oscillating. Diodes
QCRl, RCRl, SCRl, and TCRI prevent the
Schmitt transistors (QQ, QR,QS, and QT) from
going into full saturation. This helps the
circuit to oscillate at the higher frequencies.
_________________ f.
MIt: FORM
_ _ fa
AT POINT C
_ _ _ _ _ _ _ EI
.....-______--, _ _ _ _ _ _ EI
OUTPUT I'WAH)-'
'----- --Eo
~.~I~~--------~
o
.......---------' - - - - - - fo
Figure 1
83313200
A"
6-25
TP
-2.8V
A
-3V
-3.2V
(MAH) R
B
(MAF) B
A--r--+--'
TP
fl + f2
(WITH THE JNPUT
)
f OUT = - 2 - = 1.612 MHz \FREQUENCY= 806 KHz
TP
TP
-5V
B
PR2
470
QQ
PCRI
+5V
PCR2
-=
@
PCR3
r-'
®NRI
SEL
I:
TP
'-... ..
QP
QN
NR2
562
A
TP
NCRI
NCR2
1-....--'\/'II'v-~
NR4
470
+5 V
QT
8
-5V
TP
NOTES:
I. VOLTAGE AND COMPONENT VALUES ARE FOR REFERENCE ONLY.
®
@)
@
®
VARIES WITH DATA FREQUENCY. THESE COMPONENTS CONTROL FREQUENCY.
OUTPUT LOCATED ON MAH CIRCUIT.
OUTPUT LOCATED ON MAF CIRCUIT.
DIODE PCR3 ON MAH ONLY.
7J21A
c
6-26
83313200
A
c
SPEED DETECTOR - QDE
The QDE circuit monitors the sector pulses
to determine whether or not the spindle is
at a specified speed.
RCRI and RCR2 from ever becoming forward
biased. As a result, QT remains on and the
output at B remains low, indicating not up
to speed.
Each time a sector is sensed, a 55-11sec pulse
appears at input A. Transistors QN and QP
conduct and completely discharge capacitor
NCI to -5v. When the pulse drops, NCI begins charging through NR9. When the voltage
on the collectors of QN and QP reaches the
threshold of NCR2 and QQ, QQ turns on. This
causes transistors QR and QS to conduct and
discharge RCI.
With QR and QS on, RCRI and
RCR2 are back biased and the voltage at the
base of QT drops, turning QT on. The collector voltage of QT rises enough to turn
QU on and the output voltage at B goes low
to indicate a not up to speed condition.
If the disk pack is below speed, pulses at
input A are at low repetition rate. Capacitor NCI discharges and charges turning
transistors QQ, QR, and QS off and on, respectively. This in turn causes RCI to
charge and discharge.
Every time NCI
charges to the threshold, QQ, QR, and QS
turn on and discharge RCI.
This prevents
When the disk pack reaches the required
speed, the charging time of NCI is such that
the charging voltage on NCI remains below
the threshold of NCR2 and QQ, keeping QQ,QR,
and QS off. Now RCI has time to charge and
when RCRI and RCR2 become forward biased,the
voltage at the base of QT increases sufficiently for QT to turn off. The resulting
reverse bias on QU' turns QU off and the output at B goes high. The feedback through
RR3 reduces the charge time of RCI and the
switchover goes to completion with the high
output at B indicating an up to speed condition. The output signal at C is always
complementary and is used by a relay driver
circuit.
The voltage on the base of QQ is determined
by the voltage divider comprised of NRl,NR4,
NRll,NR12,NCR3, and NCR4.
Resistor NRI is
a test selected resistor to' fine tune the
threshold of NCR2 and QQ and to compensate
for the tolerances of NR9 and NCI.
A
C)
A--fQ5:EHZ~ :
,..---+3.5v
B
c
ov
r-------------------------~I-------+IV
........- - - - - -IV
+5V
+ 5V
+5V
RR5
27K
TRI
470
TCRI
TCR2
C
A
TR2
10K
TR4
100
B
RR3
10K
TP
TR7
2.2K
)I--~-nTP
+
-5V+---~--~~------~
o
+5V
RCI
15 fLF
NOTE:
VOLTAGE
83313200
A
AND COMPONENT VALUES
ARE
FOR
REFERENCE ONLY.
701 I I
6-27
VOLTAGE CHECKER - QEH
The QEH circuit detects decreases in power
supply voltages that are beyond a specified
level. A fault condition (output C equals
"0") occurs if:
1.
+5 volt supply becomes less positive
than +4.825 volts, or
2.
+20 volt supply becomes less positive than +18.0 volts.
of QR to drop the near zero volts switching
QS off and establishing a +3 volt level at
output C.
Transistors QN and QQ operate on each other
as a comparator. When the base voltage on
QN becomes less positive than the base voltage on QQ (+4.825 volts), QN turns on and
QQ turns off. With the base of transistor
QR at zero volts, transistor QR turns off
pulling the base of QS positive and turning
it on. As a result, output C approaches a
level near zero volts.
The base voltage at transistor QQ is determined by zener diode NVRI and a voltage
divider network (NR7, NR8, NR9, and NRl).
This base voltage is established at +4.825
volts.
If the positive supplies connected
to inputs A andB are normal, QP and QN are
off and transistor QQ is on. The resulting
positive level at the collector of QQ turns
on transistor QR. This causes the collector
Transistors QP and QQ also operate on each
other as a comparator. The voltage divider,
composed of resistors NR3 and NR4, is sized
so that when the +20 volt input at A goes
less positive than +18 volts, transistor QP
turns on and output C goes low.
TP
+20V
A
A
E>/Y
B
E>IY
a
QEH
c
_
B
I
LESS
POS + 5V
r--- ,
THAN +4.825V
(,
+ 3V
OV
C
A
+5V
NR3
8.66K
NRS
2.2K
NR9
1.54K
NRIO
4.7 K
NR7
1.54K
NRI2
2.2 K
TP
C
N RI
SEL
NR4
3.16K
NR8
3.3K
NVRI
6.2 V
NRI3
3.3K
NR"
47
+
':'
NR2
681
NCI
2.2 f'F
QR
B
NR 6
220
':'
NOTE:
VOLTAGE
6-28
AND COMPONENT VAWES
ARE FOR
REFERENCE
ONLY.
7.110
83313200
A
VOLTAGE CHECKER - QEJ
The QEJ circuit detects decreases in power
supply voltages that are beyond a specified
level. A fault condition (output C equals
"0") occurs if:
1.
-5 volt supply becomes less negabive
than -4.825 volts, or
2.
-20 volt supply becomes less negative than -18.0 volts.
The base voltage at transistor QQ is determined by zener diode NVRl and a voltage
divider network (NR7, NR8, NR9, and NRl).
This base voltage is established at -4.825
volts.
If the negative supplies connected
to inputs A and B are normal, QP and QN are
off and transistor QQ is on. The resulting
negative level at the collector of QQ turns
on transistor QR. This causes the collector
of QR to drop to near zero volts switching
QS off and developing a reverse bias across
diode NCR3. This turns off transistor QT
and sets the output at C to +3 volts.
Transistors QN and QQ operate on each other
as a comparator. When the base voltage on
QN becomes less negative than the base voltage on QQ (-4.825 volts), QN turns on and QQ
turns off. with the base of transistor QR
at zero volts, transistor QR turns off pulling the base of QS negative and turning it
on. Diodes NCRl and NCR2 raise the base
voltage of transistor QT to a point where it
turns on and causes output C to approach a
level near zero volts.
Transistors QP and QQ also operate on each
other as a comparator. The voltage divider,
composed of resistors NR3 and NR4, is sized
so that when the -20 volt input at A goes
less negative than -18 volts, transistor QP
turns on and output C goes low.
TP
A
0
A
f>/Y
1~--~~~~------2OV
a.
B
C
QEJ
B
+
C
A
3V
OV
r-------..-~
NR3
8.66K
NR5
2.2 K
NR9
1.!54K
QQ
NRIO
15K
NRI2
3.3K
NRI3
4.7K
+ 5V
NRI4
2.2 K
C
NR7
1.!54K
TP
NRI
SEL
QN
NCI
2.2,...F
B
NR6
220
':'
NOTE:
VOLTAGE
AND COM PONE NT VALu ES ARE
FOR
REFE RENCE
ONLY.
7.1' I
o
83313200
A
6-29
SWITCH RECEIVER - QEK
The QEK circuit produces a "1" (+3v) output
at B when the solid-state switch connected
to input A is closed. When the switch is
open a "0" (Ov) appears at output B.
rent through NR4 decreases due to the higher
lead resistance (NR3) of QN compared with
QP (NR5). The current drop through NR4
causes a decrease in the voltage drop across
NR4. The bias on QN is, therefore, increased. The cycle goes rapidly to completion. Transistor QP is turned off. With
QP off, the base of QQ is near ground,causing QQ to turn off. This allows the +5v
supply to flow through NR7 to output B raising the output to +3v, Hi".
A transistor switch is connected to input A.
When this switch is open, capacitor NCl approaches +5v and QN turns off. Transistor
QP is, therefore, on and conducts current to
the base of QQ through resistor NR5. Transistor QQ turns on, conducting current away
from output B, and drops the output to near
ground or a "0".
When the transistor switch driving the input
is not conducting, NCI charges slowly to +Sv
due to the long time constant of· NR2 and NCI.
Again, any preliminary switching that precedes the actual state change will hold NCI
well below the switching level of QN. As
the voltage across NCI increases, QN begins
to turn off. Transistor QP begins to conduct current away from the emitter of QN.
Transistor QP turns on rapidly because of
the positive feedback. The output then becomes "0".
When the switch is closed, the voltage flow
through NRl, the switch, and across NCI increases rapidly because of the short time
constant of NRI and NCI. Any spurious
switching that precedes the state change increases the discharge time. As the voltage
across NCI decreases, QN begins to turn on.
As QN conducts current to the base of QP,
the forward bias on QP decreases and QP begins to turn off. As QP turns off, the cur-
.. - - - - (OPEN;
....._ _ _ +1.4V
(CLOSED)
A
~,
XD"V
A
B
QEK
B
;..------ + 3V
OV
+5V
NR2
2.2K
NR7
2.2K
QN
NRI
220
A
NR4
1,5 K
B
+
NCI
1 IJ-F
NR3
3.3K
NR5
2.7K
QQ
NR6
1,5K
"::"
NOTE:
VOLTAGE
6-30
AND COMPONENT
VALUES
ARE FOR
REFERENCE
OM..Y.
ToIU
83313200
A
C:
SYMMETRY RESTORER - QEL
In a write driver chain where complementary
TTL input signals become asymmetrical by ±8
nsec, the QEL circuit is used to restore
symmetry to these signals.
duces a positive pulse at "ored" pins 8 and
11 for the duration of the delay. The negative edge of this pulse triggers pin 1 of
flip-flop l64H changing the state of outputs
D and E.
A "0" TTL level at pointC will set the flipflop ensuring the same start-up conditions
on inputs D and E when released by a "I"
level at C.
with input' A high and B low, pin 3 of l73H
goes to ground and pin 6 goes to +5v through
XRl, XR2, and XR4. The ground transition at
pin 3 is coupled through XCI and forces a
negative spike on pin 6. Starting from a
negative potential pin 6 voltage rises toward +5 volts at an RC time rate determined
by XCI and the combination of XRl, XR2, and
XR4. This causes the pulse to be delayed
in reaching the switching threshold of the
following inverter (pins 9 and 10), and pro-
The opposite conditions on inputs A and B
(A low and B high) form the positive pulse
at "ored" points 8 and 11 which is determined by the RC combination of XCI and XC3.
Thus, the negative edge which triggers the
J-K flip-flop is controlled by alternate RC
time constants, on~ of which can be adjusted
by selection of XRl with reference to the
other resistors.
Diodes XCRl, XCR2, XCR3, XCR4, and XCR5
clamp the positive excursion on pins 3 and
6 at +2.5 volts to make delays insensitive
to frequency variations up to data rates of
4 MHz.
+3V
A
OV
TP
+3V
B
A
0
B
E
+5V
TP
OV
0
+3V
D
C
OV
+3V
E
OV
a
2
A
:3
173H
EOI B2
17:3H
EOI B2
XCRI
XR3
681
XCI
100PF
+
3
4
D
5V
XR5
470
G
2
XR4
100
164 H
EOIB3
6
E
KG
':"
XRI
SEL
4
B
6
XR2
IK
9
10
173H
EOI B2
a
173H
EOIB2
C
(,
NOTE:
VOLTAGE
U
83313200
A
AND
COMPONENT VALUES
ARE FOR REFERENCE
ONLY.
7 .. "
6-31
VOLTAGE FOLLOWER - QEM
The QEM circuit consists of an operational
amplifier in a voltage follower configuration. A PNP emitter follower (QN) is enclosed in the feedback loop to provide a
voltage output at B equal to the input at A
with increased current handling capabilities.
Enclosing QN in the feedback loop also negates the change in output due to tempera-
ture related voltage variations of the baseemitter junctions of QN.
NR3 provides a minimum current to the emitter of QN under no load conditions. NR2 is
'a current limit resistor. NR1 is a buffer
resistor to eliminate possible oscillation
tendencies.
~
A~8
-20V
+12V
NR2
IK
A
NR3
4.7K
+ 20V
NOTE.
VOLTAGE
6-32
AND
COMPONENT
VALUES
ARE
FOR REFERENCE
ONLY.
7JIOO
83313200
A
C~:
FUNCTION GENERATOR - QGD
The QGD circuit is a nonlinear feedback network used as the gain determining element of
an operational amplifier.
When there are less than 64 tracks to go,
the input to the gate of QR changes from a
negative voltage to ground potential. QR
turns on, adding R2 into the feedback loop.
R2 has the same resistance as RI. This re'duces the feedback resistance to one-half
of its former value, thus reducing the gain
by 50% (output = ±s volts).
In actual circuit use, the op amp generates
a voltage proportional to the desired velocity of the read/write head positioner.
The amplitude of this signal is tpe analog
representation of the number of tracks to go
(position error) and will be compared with
velocity to achieve maximum deceleration
control without overshoot of the positioner
when on cylinder (T=O).
After T=32, input A begins to decrease in
proportion to the remaining position error.
The QGD/op amp circuit maintains an output
voltage for optimum deceleration. The optimum deceleration is obtained by taking the
square root of the position signal and comparing it with the velocity signal. The
resistor-diode circuits in the QGD supply
the position signal: as the input is reduced, the output is reduced correspondingly.
Fewer diodes conduct, removing some of the
parallel resistors in the QGD circuit from
the feedback loop. This increases the
effective feedback resistance, increasing
circuit gain. Gain is maximum (but not
greater than one) when the output is below
about ±O.S volt.
Field effect transistor QR is part of the
GJB circuit to function as a logic switch.
Prior to T=64, the input is at flO volts
with the switch open. With this input voltage, the voltage drops across all of the
forward-biased diodes are overcome so that
the equivalent resistance of the parallel
resistor network in the QGD circuit is about
equal to the input resistor Rl. The gain
is, therefore, unity (output is 10 volts,
inverted from input).
®J;-=T>64
r
oRl
I{
'.
I
1'1_.1' I
L:_:...J
1
1
r -----'
{
R2
I
GAIN
I
I
I
1
,-/
1 \ ___ _
'-.....-J /"~
I.J<,/,,/'.,.,
I
1
,r'\
X
,....
A__ J-./\/,..,_
RI
- -.
"".1-0 t>
r I
I:
301
I@
B
r - - -
~
L --'
IOK
.:C.
RA
RB
464 K
CRA
RC
46.4K
CRB
RD
562K
CRC
RE
56.2K
CRD
RF
464K
, CRE
RG
46.4K
CRF
RH
464K
CRG
RJ
4S.4K
CRH
RK
464K
CRJ
RL
464K
CRK
464K
RM
r CRL
464K
RN
CRM
RP
56.2K
~r CRN
RR
CRP
~"
CRS
~"
909K
RS
~, CRR
RT
56.2K
909 K
909 K
~C
'"""'
150 PF
'"""'
o
NOTES:
83313200
A
I
VOLTAGE AND COMPONENT VALUES ARE FOR REFERENCE ONLY
®
PART OF GJB CIRCUIT (REF ONLY)
@
SHOWN
FOR
REFERENCE ONLY.
NEG INPUT TURNS OR OFF.
6TI39A
6-33
SWITCH RECEIVER - RCB
Switch
output
nected
switch
B.
Receiver RCB produces a "1" (+3v)
at B when the grounded switch conto input A is closed. When the
is open a "0" (Ov) is felt at output
A switch to ground is connected to input A.
When this switch is open, capacitor NCI
approaches +Sv and QN is shut off. Transistor QP is, therefore, on and conducts current to the base of QQ through resistor NR6.
Transistor QQ turns on, conducting current
away from output B, and drops the output to
near ground or a "0".
When the switch is closed, the voltage across
NCI rapidly increases through NRI and the
switch to ground because of the short time
constant of NRI and NCI. Any contact bounce
on the switch will increase the discharge
time. As the voltage across NCI decreases,
QN begins to turn on. As QN conducts current to the base of QP, the forward bias on
QP is decreased and QP begins to turn off.
4-~f::BY~
As QP turns off, the current through NRS
decreases due to the higher lead resistance
(NR4) of QN compared with QP (NR6). The
current drop through NRS causes a decrease
in the voltage drop across NRS. The bias on
QN is, therefore, increased. The cycle goes
rapidly to completion. Transistor QP is
shut off. With QP off, the base of QQ is
near ground, causing QQ to shut off. This
allows the +Sv supply to flow through NR8 to
output B raising the output to +3v, "1".
When the switch is-opened again, NCI charges
slowly to +Sv due to the long time constant
of NR2 and NCI. Any contact bounce on the
switch will hold NCI well below the switching level of QN until the bouncing ceases.
As the voltage across NCI increases, QN begins to turn off. Transistor QP begins to
conduct current away from the emitter of QN.
Transistor QP turns on rapidly because of
this positive feedback.
The output then
returns to "0".
OPEN
A
(SWITCH
INPUT)
CLOSED
34fLSEC
B
~
r--
3V
".,-....
OV
(
I,
+5V
NR2
12K
NRI
NR3
560
3.3 K
A
QN
B
+
NCI
IfLF
QQ
NOTE: VOLTAGE AND COMPONENT VALUES ARE FOR REFERENCE ONLY.
c
ITI45
6-34
83313200
A
BIPOLAR CURRENT BUFFER - SAA
The SAA circuit is a power output stage for
an operational amplifier. Transistors QP
and QQ comprise a complementary output driver
and are always biased slightly on by diodes
NCRl and,NCR2.
The quiescent current in the output driver
is nominally 6.5 rna an~ the maximum signal
amplitude for the circuit is ±5 volts.
+5V
A
TP
OV
-5V
+5V
8
[>
OV
8
C
A
-5V
D
J
C
+V
7.5V
f
TP
l
7.5V
D
t
+V
-v
+V
NR3
1M
NR9
3.3K
C
QP
TP
NCRI
8
A
NRI3
220
NCR2
-
+V
NR4
1M
QQ
D
NRIO
3.3K
-V
NOTE: VOLTAGE AND COMPONENT VALUES ARE FOR REFERENCE ONLY.
6TI40A
o
83313200
A
6-35
VOLTAGE COMPARATOR - SCD
The SCD circuit compares a voltage at its
input (A) against a reference voltage and
outputs a bi-level digital signal at C.
the reference voltage at the base of QP. QN
then would be turned off and QP turned on
driving output C to +5 volts. An abnormal
or "fault" condition would be for two or
more inputs of the summing ladder (SCE) to
be grounded with the remaining inputs open.
This would cause the voltage at point A to
be lower than the reference voltage at the
base of QP. QN would then be turned on and
QP turned off. Point C would then switch
to -5 volts.
Input A.typically is connected to the output
of circuit SCE.
Input B is typically +12
volts, and normal or "no fault" condition
would be for 0 or 1 of the inputs of the
summing ladder (SCE) to be grounded and the
remaining inputs to be open. SCE would then
output a voltage (to input A) higher than
,
A
t>/Y
SeD
A
c
B
------
-IV
- - - - - - - - - VQP BASE
+IV
+!SV
c
-!SV
+12V
B
B
+ 20V
NRI
287
NR2
470
QN
PRI
287
QP
A
r""
PR3
1.47K
\ ......
':'
C
-!SV
NOTE:
VOLTAGE AND COMPONENT
6-36
VALUES
ARE FOR REFERENCE ONLY.
7JSU.
83313200
A
SUMMING LADDER - seE
f',
l
i
"-..-/
The summing ladder seE circuit is a network
of resistors with the output connected to a
voltage source through a common resistor
such as input A on the seD circuit. This
forms a ,resistor divider circuit with an
output voltage dependent upon the number of
inputs (resistors) being connected to ground
potential. One or more comparators could
be connected to the output to check for a
particular number of inputs being connected
to ground.
OUTPUT
IRI
2.15K
6RI
2.15k
"R I
2.ISK
16RI
2,15K
19
.l.N PUTS
o~-----------------------~~----~--~
t
REMAIN I NG
OUTPUT
-
INPUTS
-
~
86RI
2,15K
91RI
2.15K
NOTE:
VOLTAGE'
AND COMPONENT VALUES
ARE
FOR
REFERENCE
ONLY.
7"36A.
(j
83313200
A
6-37
TFT
Information not available at time of printing.
It will be supplied at a later
revision.
6-38
83313200
A
DELAY - UBG
The UBG circuit is used to delay application
of +5 volts during a power up sequence. Output A drives a standard TTL gate (element
number 140).
During a power off phase (to)' capacitor
A3Cl is discharged. When power is applied
(tl)' input A is still below the turn-on
threshold of the TTL gate due to the discharged state of A3Cl. However, the capacitor begins charging through A3CR1, A3R2
and the input resistance of the TTL gate. At
time t2 the capacitor voltage reaches the
turn-on threshold of the TTL gate (approximately 1.5v). The capacitor then continues
to charge to full capacity.
When the +5 voltage is removed, A3Cl discharges through A3CR2 and A3Rl returning
circuit output A to a level below the turnon threshold of the TTL gate.
ON
+5V
POWER
150 MS t2
+5V
I
I
A
t~g:
A
UBG
to
t
II
OFF
+3V
OV
I
t2
A3Rl
4.7K
A3CRI
A3CR2
+~V
A
A3RI
Ik
+
A3C I
150 JJ-F
NOTE:
VOLTAGE
AND COMPONENT VALUES ARE
FOR
REFERENCE ONLY.
7.117
o
83313200
A
6-39
I
DELAY - UBD/UBE/UBF/UBH
The capacitor delay circuits delay a "1" input at A for a specified period of time
before providing a "1" output at B. Delay
time for a "0" pulse is negligible.
Assume a "0", ground, enters at A.
If the
capacitor is discharged, it remains discharged and the output remains "0".
If the
capacitor is charged when the "0" signal
appears, the capacitor discharges almost
instantaneously, and the "0" appears with
no noticeable delay.
a "1" can appear at B. The required charge
time is the delay time of the circuit. The
charge time is dependent on the capacitor
value, the resistance between the source
voltage and the capacitor, and the minimum
. voltage required to produce a "1" output.
Delay times for capacitive delays used are
as follows:
Delay Type
t2
I
UB-
200
0.5
0.2
100
UBD
UBE
UBF
UBH
If a "1", +3 volts, enters A while the capacitor is discharged, the capacitor must
first charge to a minimum "1" voltage before
A
Time
A 1-----'
nsec
ms
ms
nsec
+3V
OV
B
+3V
OV
®
RNA
A~B
270
NOTES:
CD
®
I
-=
VARIES WITH
CNA
CD
TYPE
NOT USED ON UBF
6TI55
c
6-40
83313200
A
RELAY DRIVER - VHI
A -1 volt at input A turns off transistor QN.
(Diode CR3 limits the reverse bias on QN to
-0.7 volts.)
The collector of QN now goes
high which turns on transistor QP. This
causes output B to go low, near 0 volts,
energizing the load.
The VHI circuit drives a relay armature terminated at +V volts. Output B of the circuit functions to apply or remove ground so
that the +V source may pull or drop the relay.
An input of +1 volt at A
on. The collector of QN
transistor QP off. As a
goes to +V and the relay
turns transistor QN
goes low which turns
result, output B
is de-energized.
~
/Y
A
VHI
+ IV
A
- IV
B
+V
B
+0.2V
+5V
+V
IR 5
IK
.-.. . . .---l"
~
IR3
100
A
ICR3
NOTE:
VOLTAGE
83313200
A
AND COMPONENT
VALUES ARE FOFc
RFFE"RENCE ONLY.
7J31
6-41
LEVEL TRANSLATOR - VHJ
When a "0" (Ov to +.4v) is applied to input
A, QN turns on and applies +V (minus Vce sat)
to output B. When a "1" (+2.4v to +5v) is
applied to A, QN turns off and output B
switches to -5 volts.
The VHJ circuit converts TTL logic levels to
+V and -5 volt levels where +V = 1.4 to 2.4
volts.
,...-----+ 3V
A
A,
A~B
OV
+V
B
' - - - - - - -5V
+V
NR2
N RI
2.2 K
100
A
B
NOTE:
VOLTAGE
6-42
AND
COMPONENT
VALUES
ARE
FOR REFERENCE
ONLY.
7.1,.
83313200
A
INTEGRATING LEVEL TRANSLATOR - VHK
(~\'I
'-./
output B going to ground at a rate controlled by collector-base feedback capacitor
NC1. With an input of 0 volts to -3 volts,
QN turns off and output B is disconnected
from ground.
The VHK circuit is a voltage level shifter
that slows down and controls "turn on" and
"turn off" transition times.
with an .input to A of +.7 volts or greater
(current limited to 20 rna), QN turns on with
r
:-------.\,----_ ;.--_---- :.::
I...
l
~ +.7V
.....
GND
B
A
NOTE:
VOL.TAGE AND COMPONENT VALUES ARE FOR
83313200
A
REFERENCE
ONLY.
7.140
6-43
FAULT DETECTOR - VHM
The VHM circuit compares a voltage at its
input (A) against a reference voltage and
outputs a bi-level digital signal at C.
-S volts. With no current into A (A low)
the voltage at A is -S volts which is less
than the voltage at the base of QP. ON is
off, QP is on, and output C gets clamped at
the saturated level of about -l.S volts or
at -.7 volts if output C is connected to a
TTL gate input that has a diode clamp. When
current flow into A exceeds approximately
2.7 rna, the voltage at A becomes more positive than at the base of QP. QN turns on,
QP turns off, and output C rises to +S volts.
Input A is typically connected to output G
of a write driver (JAG) circuit.
Input B is
connected to a controlled current source
(FAG) with an output between +12 to +lS
volts, dependent upon the current drain at
QP.
The voltage level at input A is determined
by the current flow into A through NRl to.
+2V
A
-5V
B
+12V
+ 5V
c
- 1.5 V
-5V
N R2
2.2K
C
A
"--"""'-~-5V
B
NOTE:
VOLTAGE
AND
COMPONENT
VALUES
ARE
FOR
REFERENCE
ONLY.
7J42
('
6-44
83313200
A
LEVEL TRANSLATOR - VHQ
The VHQ circuit translates digital signal
levels of Ov and +5v to digital levels of
+4v and -lOv respectively.
A "I" (input op.en or +5 volts) at input A
causes QN to turn off and output B goes to
-10 volts through load resistor NR3.
A "a" (Qv to +.5v) at input A causes QN to
turn on and apply +5v minus VTCRI or about
+4 volts at output B.
An open collector IC or discrete transistor
is used to provide the described input conditions at input A.
, - - - - - - - - - , - - - - - +5V
A
'-------OV
r
, - - - - - - +4V
A-1::: B
B
'--------~
- - - - - -IOV
+5V
NR2
820
TCRI
NRI
1.21<
A
C)
B
NR3
2.2K
-IOV
NOTE:
VOLTAGE
.'---
U
AND COM PONENT VALUES ARE FOR REFERENCE ONLY.
7"94
\
83313200
A
6-45
~IME CO~TANT SWITCH - VHR
The VHR circuit converts digital signals to
integrator response times by switchin~ a
resistor in and out of an RC circuit. The
integrator is made up of NRS, NR6, and NCI
with the input at B and output at C. The
response time of this integrator can be
changed by causing QP to switch NRS in or
out of the circuit.
Full wave rectification of read head signals
is entered at B. The integrated output at
C is a DC level which is an average value of
the input signal waveform.
.
+2 volts at the base of QP. This causes QP
to turn off which inputs NRS in series with
NR6 and the time constant (response time) of
the integrator becomes (NRS + NR6) times
. (NC1) •
A "1" (input open or +S volts) at input A
causes QN to turn off. QN collector goes
toward -S volts through NR3. This causes
QP to turn on which "shorts out" NR5 leaving
NR6 and NCI to form the integrator. The
time constant (response time) then becomes
(NR6) times (NC1) . .
A "0" (Ov to +.Sv) at input A causes QN to
turn on and apply +Sv minus VTVR1 or about
A
TP
B
-.7V
X/V
A
B
('
C
VHR
\.
C
-.7V
+5V
NR2
2.7K
NRI
470
B
QN
A
NR5
10K
NR3
2.2K
-5V
NOTE:
VOLTAGE AND COMPONENT
VALUES
ARE FOR
REFERENCE ONLY.
7J99A
c
6-46
83313200
A
'
,"'---',
(,
.~
AND GATE - VKM
The VKM circuit is a two input gate with
output levels of +20 volts and -9 volts.
Diode NCRl provides breakdown protection
for the base emitter junction of QN when
inputs A and B conditions cause reverse
-bias.
Input A is typically connected to output B
of VHK circuit and input B is connected to
output C of VKN circuit through an 820 ohm
current limiting resistor.
+IOV
A
OV
8
A
B
VKM
B
+ I.~V
-IOV
C
C
+ 20V
-9V
+ 20V
C
A
("\
NR2
820
~)
B
- 9V
NOTE:
VOLTAGE
AND
COMPONENT
VALUES
ARE
FOR
REFERENCE
ONLY,
7.14 I
o
83313200
A
6-47
TWO INPUT AND GATE - VKN
The VKN circuit is a two input AND gate with
input voltage levels matched to TTL threshold
levels (approximately 1.4 volts) by NCRI.
6-48
Output voltages of +5 or -10 volts are current limited by resistors NR7 and NR6.
83313200
A
DELAY -
XAH
The XAH circuit consists of a one shot integrated circuit (with external RC network)
used in an application which results in delayed outputs rather than one shot pulse
outputs . .
and "1" respectively. The delay time is
approximatedby TD=.32 RC, where C=NCI and
R=NR3 + NR2//NR4. A return to a "0" at input A immediately resets outputs Band C to
their original states of "1" and "0" re·spectively.
A "0" (Ov to +.5v) at input A (pin 11) causes
outputs Band C to remain in an inactive
state, "1" and "0" respectively.
An open collector output integrated circuit
. such as a l73H or 200 is used to provide the
described input conditions at A.
When input A is released or open, the delay
time out begins. At the end of the delay
time, outputs Band C change state to a "0"
Resistor RNl is an input gate pullup to ensure a constant "l".condition on pins 3 and
4.
A
--125~S
I
t2tB
I
XAH
- - - - - - - - - - - - OPEN
A
B
C
C
Cl
A
NCI
2700PF
+~V
NR3
100
II
Li~~'-----~8~
NRI
______________~
B
2.2K
6
c
+~V
NOTE:
VOLTAGE
83313200
A
AND COMPONENT
VALUES
ARE FOR REFERENCE
ONLY.
7.1108
6-49/6-50
( -
COMMENT SHEET
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11
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z
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9
~
....
::J
U
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Corporation. Any errors. suggested additions or deletions. or general comments may be made above. Please include
references to fi~re number, assembly number and design configuration level.
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File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37 Producer : Adobe Acrobat 9.13 Paper Capture Plug-in Modify Date : 2009:08:27 01:31:09-07:00 Create Date : 2009:08:27 01:31:09-07:00 Metadata Date : 2009:08:27 01:31:09-07:00 Format : application/pdf Document ID : uuid:3306120d-64da-4cc1-b09e-1a5228afc4ba Instance ID : uuid:5e1e40f7-4fff-445a-b30c-2b6d6cf15a23 Page Layout : SinglePage Page Mode : UseNone Page Count : 222EXIF Metadata provided by EXIF.tools