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User Manual: 84X0873_RT_PC_Technical_Reference_Volume_3_Jun87

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----- ------ ----------_.-

IBMRTPC
Hardware Technical
Reference
Volume III

Personal Computer
Hardware Reference
Library

Second Edition (September 1986)
Changes are made periodically to the information herein; these changes will be incorporated in new editions of this publication.
References in this publication to IBM products, programs, or services do not imply the IBM intends to make these available in all
countries in which IBM operates. Any reference to an IBM program product in this publication is not intended to state or imply that
only IBM's program product may be used. Any functionally equivalent program may be used instead.
International Business Machines Corporation provides this manual "as is," without any warranty of any kind, either express or
implied, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. IBM may make
improvements and/or changes in the product(s) and/or program(s) described in this manual at any time.
Products are not stocked at the address given below. Requests for copies of this product and for technical information about the
system should be made to your authorized IBM RT PC dealer.
A reader's comment form is provided at the back of this publication. If the form has been removed, address comments to IBM
Corporation, Department 997, 11400 Burnet Road, Austin, Texas 78758. IBM may use or distribute whatever information you supply
in any way it believes appropriate without incurring any obligation to you.
© Copyright International Business Machines Corporation 1986

(

About This Book
Purpose
The options and adapters are the second part of the IBM R T PC Hardware Technical Reference
manual. They are to be used in conjunction with the IBM RT PC Hardware Technical
Reference, Volume I.

Audience
The information in this manual is for reference. It is intended for hardware and program
designers, programmers, engineers, and anyone else who needs to understand the design and
operation of the IBM RT PC Product Family.

How to Use This Book
This manual is modular in format, with each module providing information about a specific
option or adapter available for the IBM R T PC family of products. Modules having a large
amount of text contain indexes.
The modules are grouped by type of device. To find a specific module:
1.

Locate the full length hard tab with the type of device (Displays, Communications, Storage
Devices, etc.) printed on it that describes the option or adapter you need information about.

2.

Open the manual to that section.

3.

Leaf through that section to find the proper module.

iii

(

iv Reference Manual

DISPLAYS

"--

DISPLAY ADAPTERS

MEMORY EXPANSION

"--

MULTI-PURPOSE ADAPTERS
'>

----- -----

-- --_.-

- ------

IBM Advanced Color
Graphics Display

Personal Computer
Hardware Reference
Library

ii

Advanced Color Graphics Display

Contents

Description ............................................................ 1
Operating Characteristics ....................................................... 1
Connector Specifications ..................................................... ' .. 3

Contents

iii

iv

Advanced Color Graphics Display

Description

The Advanced Color Graphics Display is a high resolution color display that supports an
addressable format of 720 dots horizontally by 512 scan lines vertically. The display screen is
interlaced at a refresh rate of 46/92 Hz.
The Advanced Color Graphics Display has two attached cables. One cable provides the direct-drive
signal interface to the Advanced Color Graphics Display Adapter. The second cable provides ac
power to the display. The display operates on 120 Vac, 50/60 Hz or 220 Vac, 50/60 Hz
depending on the model.
The display uses a 14-inch (diagonal) shadow mask color cathode ray tube (CRT). The CRT and
associated analog circuits of the display are packaged in an enclosure that allows the display to sit
either on top of the mM 6151, on a nearby tabletop or desk with the IBM 6150. The display
enclosure includes a tilt and swivel base, which allows the display screen to be adjusted by the user
for the best viewing conditions. The display an operator control that provides brightness control
function and a power on and off switch.

Operating Characteristics
Operating characteristics of the display are as follows:

Screen
•

Etched surface for reduced glare

•

720 dots horizontal by 512 scan lines vertical.

Video Signal
•

Two-level (on and off) video for 6 video lines

•

Maximum bandwidth of approx. 25.7 Mhz

•

Compatible with standard TTL driver.

Advanced Color Graphics Display

1

Horizontal Drive
•

Free-running horizontal oscillator

•

Normally low, positive going TTL pulse

•

Nominal horizontal frequency of 24.68 Khz

•

Retrace blanking time of 8.0 usec.

Vertical Drive
•

Free-running vertical oscillator

•

Normally low, positive going TTL pulse

•

Nominal vertical frequency of 92 Hz

•

Nominal frame rate of 46 Hz.

•

Retrace blanking time of 527.0 usec.

Operator Control
•

Brightness control adjusts brightness of displayed image. (Clockwise rotation of control
increases brightness.)

•

Power on and off switch and light.

•

Width 372 mm (14.6 in.)

•

Depth 400 mm (15.7 in.)

•

Height 360 mm (14.2 in.)

Size

2

Advanced Color Graphics Display

Weight
13.3 Kg (29.26 pounds)

Power Cable
Length 2.8 m (9.19 ft.)

Signal Cable
Length 2.5 m (8.20 ft.)

Connector Specifications
Pin

1
2
3

4
5
6
7
8

9
10
11
12
13
14
15
16

Function
Signal ground for vertical sync
Vertical sync
R 1 signal ground
Low order red bit (R 1)
R2 signal ground
High order red bit (R2)
G 1 signal ground
Low order green bit (G 1)
G2 signal ground
High order green bit (G2)
B 1 signal ground
Low order blue bit (B 1)
B2 signal ground
High order blue bit (B2)
Signal ground for horizontal sync
Horizontal sync

1513119 7
16141210 8

Advanced Color Graphics Display

3

4

Advanced Color Graphics Display

-- --_.-

-----

. --- -- - ----

Advanced Monochrome
Graphics Display

Personal Computer
Hardware Reference
Library

ii

Advanced Monochrome Graphics Display

Contents

Description ............................................................ 1
Operating Characteristics ....................................................... 1
Connector Specifications ....................................................... 3

Contents

iii

iv

Advanced Monochrome Graphics Display

Description

The Advanced Monochrome Graphics Display is a high resolution monochrome display which
supports an addressable format of 720 dots horizontally by 512 scan lines vertically. The display
screen is interlaced at a refresh rate of 46/92 Hz.
The Advanced Monochrome Graphics Display attaches to the RT PC system unit through two
cables approximately 2.5 meters (8.25 feet) in length. One cable provides the direct-drive signal
interface to the RT PC Advanced Monochrome Graphics Display Adapter. The second cable
provides ac power to the display from the system unit. This arrangement allows the system unit
power switch to also control the power to the display and reduces the number of electrical wall
outlets required to power the system. The display operates on 120 vac, 60 Hz power line voltage.
The display uses a 12-inch (diagonal) high contrast monochrome CRT. The CRT and associated
analog circuits of the display are packaged in an enclosure that allows the display to sit either on top
of the Model 10 system unit or on a nearby tabletop or desk with other R T PC system units. The
display enclosure includes a tilt and swivel base which allows the display screen to be adjusted by
the user for the best viewing conditions. The display has only one operator control which provides
two functions: brightness control and raster switch (used only to verify operation of the display).

Operating Characteristics
Operating characteristics of the display are as follows:

Screen
Etched surface for reduced glare
720 dots horizontal by 512 scan lines vertical.

Video Signal
Two-level (on and off) video
•

Maximum bandwidth of approx. 25.7 Mhz
Compatible with standard TTL driver.

Advanced Monochrome Graphics Display

1

Horizontal Drive
Free-running horizontal oscillator
Normally low, positive going TTL pulse
Nominal horizontal frequency of 24.68 Khz
Retrace blanking time of 8.0 usec.

Vertical Drive
Free-running vertical oscillator
Normally low, positive going TTL pulse
Nominal vertical frequency of 92 Hz
Nominal frame rate of 46 Hz.

Operator Control
Brightness control adjusts brightness of displayed image. (Clockwise rotation of control
increases brightness)
Raster switch (diagnostic aid) produces visible raster independent of video input. (Raster
switch function occurs at full clockwise rotation of brightness control)

Size
Width 327 mm (12.9 in.)
Depth 331 mm (13.0 in.)
Height 266 mm (10.5 in.) without pedestal
305 mm (12.0 in.) with pedestal

2

Advanced Monochrome Graphics Display

Weight
8.5 Kg (18.74 pounds)

Power Cable
Length 2.5 m (8.25 ft.)

Signal Cable
Length 2.5 m (8.25 ft.)

Connector Specifications
Pin

1
2
3
4
5
6
7
8
9
10
11

12
13

14
15
16

Function

Signal ground for vertical sync
Vertical sync
Signal ground
Reserved
Signal ground
Reserved
Signal ground for video
Video
Signal ground
Reserved
Signal ground
Reserved
Signal ground
Reserved
Signal ground for horizontal sync
Horizontal sync

Advanced Monochrome Graphics Display

3

4

Advanced Monochrome Graphics Display

----------------

-- --_.-

Enhanced Color
Display

Personal Computer
Hardware Reference
Library

ii

Contents

Description ....................................
Operating Characteristics .........................
Specifications ..................................
Connector Information .......................

1
2
5
6

iii

iv

Description
The IBM Enhanced Color Display is an advanced color display
capable of operating in two separate modes. Mode 1 is a 16 color
640 by 200 overscan mode with a horizontal scan frequency of
15.75 kHz. Mode 2 is a 64 color 640 by 350 mode with a
horizontal scan frequency of 21.8 kHz. Both modes are
non-interlaced. The monitor determines which mode to operate in
by decoding the vertical sync polarity.
The IBM Enhanced Color Display attaches to the system unit by
a signal cable that is approximately 3.5 feet (1.07 meters) in
length. This signal cable provides a direct-drive interface from
the IBM Personal Computer.
A second cable provides ac power to the display from a standard
wall outlet. The display has its own power control and indicator.
Three models are provided. Model 001 is for northern hemisphere
operation and operates on 120 volts 50/60 Hz. Model 002 is for
northern hemisphere operation and operates on 220/240 volts
50/60 Hz. Model 003 is for southern hemisphere operation and
operates on 220/240 volts 50/60 Hz.
The display has a 13-inch, high-contrast CRT. The CRT and
analog circuits are packaged in an enclosure so the display may sit
either on top of the system unit or on a nearby tabletop or desk.
Front panel controls and indicators include: Power-On control,
Power-On indicator, Brightness and Contrast controls.
Additional controls on the rear of the display are: Vertical Size 1
and Vertical Size 2. There are two service controls on the rear of
the unit, black level adjustment and contrast default value
adjustment.

IBM Enhanced Color Display 1

Operating Characteristics
Screen
•

Etched anti-glare screen

•

O.31mm dot mask

•

Displays 16 or 64 colors depending on the mode selected

User Controls
•

Brightness control affects the contribution of all input bits by
controlling the gain of the video stages. The display contains
a protection circuit which may overide this control.

•

Contrast control affects the contribution of the least
significant bits only. When pushed in, the contrast control is
rendered inoperative and contrast is determined by the
setting of the contrast default value adjustment on the rear of
the display. Pulling the contrast control knob out engages the
front contrast control.

•

V. Size 1 control controls the vertical size of the screen in
mode 1.

•

V. Size 2 control controls the vertical size of the screen in
mode 2.

Service Controls
•

Black level adjust control is adjusted to make the raster lines
just disappear when black input signal is supplied.

•

Contrast default value control is used to set the contrast
value when the front contrast control is pushed in. Normally
adjust for best brown color.

2 IBM Enhanced Color Display

Vertical Sync
•

Uses polarity of Vertical Sync signal to automatically select
Mode 1 or Mode 2 operation. Mode 1 is selected by a
normally low positive going TTL pulse. Mode 2 is selected by
a normally high negative going TTL pulse.

•

Screen may be refreshed from 50 to 60 Hz. At 60 Hz there
are either 200 or 350 vertical lines of resolution depending
on the mode selected.

•

700 ILsec retrace time

Horizontal Sync
•

Normally low, positive going TTL pulse

•

In Mode 1, 15.75 kHz.

•

In Mode 2,21.8 kHz.

•

6 ILsec retrace time

IBM Enhanced Color Display 3

When operating in Mode 1, the display maps the 4 input bits into
16 of the possible 64 colors as shown in the following chart.

I

R

G B

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Color
Black
Blue
Green
Cvan
Red
Magenta
Brown
Grav 1
Grav 2
Light Blue
Light Green
Light Cvan
Light Red
Light Magenta
Light Yellow
White

Rr

Gg

00
00
00
00
10
10
10
10
01
01
01
01
11
11
11
11

00
00
10
10
00
00
01
10
01
01
11
11
01
01
11
11

Bb
00
10
00
10
00
10
00
10
01
11
01
11
01
11
01
11

Note: The R G and B are the most significant bits. The r g
and b are the least significant bits.

4 IBM Enhanced Color Display

Specific a tions
Size:
Length - 15.4 in (392 mm)
Depth - 15.6 in (407 mm)
Height - 11.7 in (297 mm)
Weight:

321bs
Heat Output:

300 BTU/hr
Power Cable:

Length - 6 ft (1.83 m)
Size - 18 AWG
Signal Cable:

Length - 3.5 ft (1.07 m)

IBM Enhanced Color Display 5

Connector Information
The signals that are on the pins vary with the driver card being
used and the mode in which it is operating. All signals are
expected to be TTL levels supplied by totem pole drivers.
Pin

Mode 1 (16 Color)

Mode 2 (64 Color)

1
2

Shield Gnd
Signal Gnd
Red
Green
Blue
Intensity
Unused
Horiz SYnc
Vert Sync

Ground
r

3
4
5
6
7

8
9

R
G
B

a
b
Horiz Sync
Vert SYnc

Note: The R G and B are the most significant bits. The r g
and b are the least significant bits.

6 IBM Enhanced Color Display

-- --- ---- --------_.-

Extended
Monochrome
Graphics Display

Personal Computer
Hardware Reference
Library

TNL SN20-9844 (March 1987) to 75X0235

(

ii Extended Monochrome Graphics Display

TNL SN20-9844 (March 1987) to 75X0235

Contents

Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

1

Operating Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Connector Characteristics . . : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

1
4

Contents iii

TNL SN20-9844 (March 1987) to 75X0235

iv Extended Monochrome Graphics Display

TNL SN20-9844 (March 1987) to 75X0235

Description

The Extended Monochrome Graphics Display is a high resolution monochrome display which
supports an addressable format of 1024 dots horizontally by 768 scan lines vertically. The
display screen is refreshed at a rate of 60 Hz.
The Extended Monochrome Graphics Display has two attached cables. One cable provides the
direct-drive signal interface to the Extended Monochrome Graphics Display Adapter. The
second cable provides ac power to the display. The display operates on 120 vac, 50/60 Hz or
220 vac, 50/60 Hz depending on the model.
The display uses a 15-inch (diagonal) high contrast monochrome cathode ray tube (CRT). The
CRT and associated analog circuits of the display are packaged in an enclosure that allows the
display to sit either on top of the IBM 6151 system unit or on a nearby tabletop or desk with
other R T PC system units. The display enclosure includes a tilt and swivel base which allows
the display screen to be adjusted by the user for the best viewing conditions. The display has
two operator controls. One operator control is used for contrast. The other control is used for
brightness and the power on and off switch.

Operating Characteristics
Operating characteristics of the display are as follows:

Screen
•

Etched surface for reduced glare

•

1024 dots horizontal by 768 scan lines vertical.

Extended Monochrome Graphics Display 1

TNL SN20-9844 (March 1987) to 75X0235

Video Signal
•

Two-level (on and oft) video

•

Maximum bandwidth of approx. 70 Mhz

•

Compatible with standard TTL driver.

Horizontal Drive
•

Free-running horizontal oscillator

•

Normally low, positive going TTL pulse

•

Nominal horizontal frequency of 47.52 Khz

•

Retrace blanking time of 4.21 usec.

Vertical Drive
•

Free-running vertical oscillator

•

Normally high, negative going TTL pulse

•

Nominal vertical frequency of 60 Hz

•

Retrace blanking time of 505.0 usec.

Operator Control
•

Brightness control adjusts the overall monitor screen including background raster. Adjust the
control so that the background raster disappears.

•

Contrast control adjusts the brightness of the displayed image without affecting the
background. (Clockwise rotation of control increases brightness.)

•

Power On and Off switch and light.

2 Extended Monochrome Graphics Display

TNL SN20-9844 (March 1987) to 75X0235

Size
•
•
•

Width 372 mm (14.6 in.)
Depth 400 mm (17.7 in.)
Height 360 mm (14.2 in.)

Weight
13.75 Kg (30.25 pounds)

Power Cable
Length 2.8 m (9.19 [t.)

Signal Cable
Length 2.5 m (8.2 ft.)

Extended Monochrome Graphics Display 3

TNL SN20-9844 (March 1987) to 75X0235

Connector Specifications
Pin

Function

1
2
3
4
5
6
7
8
9

Gnd - Vertical sync
Vertical sync
Fteserved
Fteserved
Gnd - Video
Video
Gnd - Video
Video
Gnd - Video
Video
Gnd - Video
Video
Gnd - Video
Video
Gnd - Horizontal sync
Horizontal sync

10
11
12
13
14
15
16

4 Extended Monochrome Graphics Display

- ---- ---------

--_.-

Monochrome
Display

Personal Computer
Hardware Reference
Library

ii

Contents

Description .................................... 1
Specifications .................................. 3
Logic Diagrams ................................. 5

iii

iv

Description
The high resolution IBM Monochrome Display connects to the
system unit through two cables. One cable is a signal cable from
the display adapter to the display, and the other provides power to
the display from the system unit. This arrangement eliminates the
need for a wall outlet and allows the system-unit Power switch to
control power to the display. The display unit has a 28.3 cm
(11.5 in.) diagonal, 90° deflection cathode ray tube (CRT). The
display may be placed on the system unit or on a nearby table or
desk. Brightness and contrast controls are on the front surface
and are easily accessible to the operator.
The characteristics of the display are as follows:
•

Screen
-

High-persistence, green phosphor (P39).
Etched surface to reduce glare.
Presentation of 80 characters wide by 25 rows deep.
Characters are defined in a 14 PEL-high by 9 PEL-wide
matrix.

•

Video Signal
-

•

Maximum bandwidth of 16.257 MHz at -3dB

Vertical Drive
Screen refreshed at 50 Hz with 350 lines of vertical
resolution and 720 lines of horizontal resolution

•

Horizontal Drive
Positive level, TTL-compatibility, at a frequency of 18.432
kHz

Monochrome Display 1

2 Monochrome Display

Specifications
Size
Height
Length
Depth

280 mm (11 in.)
380 mm (14.9 in.)
350 mm (~3.7 in.)

Weight

7.9 kg (17.3Ib)

Heat Output

325 BTU/hr

Power Cable
Length
Size

0.914 m (3 ft)
18AWG

Signal Cable
Length
Size

1.22 m (4 ft)
22AWG

Physical Specifications

Monochrome Display 3

4 Monochrome Display

Logic Diagrams
The IBM Monochrome Display has two models: a 110-Vac
model and a 220/240-Vac model. A logic diagram for each
follows.

Monochrome Display S

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NOTES,
1. RESISTOR VALUES ARE INIOHMI 0 K" 101100 M" 1.0110.01100
2. ALL RESISTOR ARE 1/4WEXCEPTWHEREoTHERWISEINOICATEO

3.ALLCAPACITORSARE50VEXCEPTWHEREOTHERWISEIN01CATEO
4. CAPACITORS VALUES ARE.F UNLESS OTHERWISE INOICATEO." ,ff" 10"
5. AC WIRING INFORMATION

PHASE" BLACK/BROWNWIRE
NEUTRAL" WHITE/BLUEWIRE
GROUND'" GREENANO YEUOW WIRE
IMPORTANT: THE PHASE WIRE MUST GO TO THE FUSED SIDE OF TRANSFORMER

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IBM 5080 Peripheral
Adapter

rersonat compurer
Hardware Reference
Library

ii

5080 Peripheral Adapter

Contents

Description ....••..••••....•••...•.••...•.......••.......•..•.......•.. 1
mM 5080 Peripheral Adapter Switch Settings .......................................
Modes of Operation ...........................................................
Interrupts ...................................................................
Serial Data Format ............................................................
External Interface Description ..................................................
Asynchronous Communications Element Pin Description .............................
Programming Considerations ...................................................
Connector Specifications ......................................................

Contents

3
5
8
9
10
12
18
32

iii

iv

5080 Peripheral Adapter

Description

The mM 5080 Peripheral Adapter provides three serial output ports on a 4.25- by 13. 12-inch board
that plugs into one I/O position. The adapter system control signals and voltage requirements are
provided throu~ a 2- by 31-position and a 2- by 18-position tab on the bottom of the adapter.
Up to four adapters may be used in one RT PC system. A DIP switch on the adapter is used to
assign the adapter I/O address range. The port I/O address assignments are contained in the
adapter's I/O address range.
The adapter is fully programmable and supports asynchronous communications only. It adds and
removes start bits, stop bits, and parity bits. A programmable baud-rate generator allows operation
from 50 bps to 19200 bps. Five-, 6-, 7- or 8-bit characters with 1, 1-1/2, or 2 stop bits are
supported. A priority interrupt system controls transmit, receive, error, line status, and data set
interrupts.
Three 10-pin male connectors on the adapter provide external access to the three ports.
The heart of the adapter is an NS 16450 LSI chip or a functional equivalent. Features in addition to
those listed above include:
Note: The NS 16450 is functionally equivalent to all INS8250.
•

Full double buffering that eliminates the need for precise synchronization

•

Independent receiver clock input

•

False start bit detection

•

Line-break generation and detection.

All communications protocol is a function of the system microcode that must be loaded before the
adapter is operational. All pacing of the interface and control signal status must be handled by the
system software. Figure 1 on page 2 is a block diagram of the IBM 5080 Peripheral Adapter.

5080 Peripheral Adapter

1

1.8432
MHZ t--OSC

1/0 R/W

---

......

Data 0-7

...

Address 0-15

.......

DATA

r----+

--....

Addr
Decode

16450

- ---

DRVRS
RCVRS

- -....

DRVRS
RCVRS

.
-- -

DRVRS
RCVRS

~

---....
=-

--~
..

16450

--

r-

Clock
__ Int Req 9
__ Int Req 10
__ Int Req 11
Reset

-..

-

Int
CnU

~
~

-

--- ~-----....
-

Figure 1.

2

mM 5080 Peripheral Adapter Block Diagram

5080 Peripheral Adapter

16450

IBM 5080 Peripheral Adapter Switch Settings
The mM 5080 Peripheral Adapter switch settings select the interrupt level and the address range of
adapters installed.

Figure 2.

~

12345678

Switch Bank One

Switch Bank Two

mM 5080 Peripheral Adapter Switches

Interrupt
Level
Selected

Switch 1

Switch 2

Switch 3

Level 9
LevellO
Levelll

On
Off
Off

Off
On
Off

Off
Off
On

Figure 3.

Switch Bank One Setting

Switch Bank One Settings

5080 Peripheral Adapter

3

Switch Bank Two Setting

Address
Range of
Adapters

Switch 1

Switch 2

Switch 3

Switch 4

1230-1247
2230-2247
3230-3247
4230-4247

On
Off
Off
Off

Off
On
Off
Off

Off
Off
On
Off

Off
Off
Off
On

Figure 4.

Switch Bank Two Settings

Note: Switches 5 through 8 are not used.

4

5080 Peripheral Adapter

Modes of Operation
The different modes of operation are selected by programming the NS 16450 asynchronous
communications element. This is done by selecting the 110 address and writing data out to the 1/0
address. Address bits AO, A1, and A2 select the different registers that define the modes of
operation. Also, the divisor latch access bit (bit 7) of the line control register is used to select
certain registers.
The address range for this adapter is X'1230' through X'4247'. Figure 5 and Figure 6 on page 6
depict a value of n, which represents a variable determined by the setting of switch bank two ..
Switches 1, 2, 3, and 4 of switch bank two allow the card to operate and select the appropriate
address range.
110 Decode (In Hex)
PortH
PortA

n238
n238
n238
n239
n239
n23A

n230
n230
n230
n231
n231
n232

n23B
n23C
n23D
n23E

n233
n234
n235
n236

Figure 5.

Register Selected

DLAB State

TX Buffer
RXBuffer
Divisor Latch LSB
Divisor Latch MSB
Interrupt Enable Register
Interrupt Identification
Register
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register

DLAB=O (Write)
DLAB=O (Read)
DLAB=1
DLAB=1
DLAB=O

II0 Decodes, Port A and Port B

Notes:
1.

n is equal to the first digit of the adapter address range

2.

DLAB means Divisor Latch Access Bit.

5080 Peripheral Adapter

5

I/O Decode (In Hex)
porte
n240
n240
n240
n241
n241
n242
n243
n244
n245
n246
Figure 6.

Register Selected

DLAB State

TX Buffer
RXBuffer
Divisor Latch LSB
Divisor Latch MSB
Interrupt Enable Register
Interrupt Identification
Register
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register

DLAB=O (Write)
DLAB=O (Read)
DLAB=l
DLAB=l
DLAB=O

I/O Decodes, Port C

Notes:

6

1.

n is equal to the first digit of the adapter address range

2.

DLAB means Divisor Latch Access Bit.

5080 Peripheral Adapter

A9->A3
Decode
A2

At

AO

See

x

x

x

Note 1

0

0

0

Figure 7.

DLAB

Register

0

0

Receive Buffer Reg. (read)
Transmit Holding Reg. (write)

0

1

0

Interrupt Enable

0

1

0

x

Interrupt Identification

0

1

1

x

Line Control

1

0

0

x

Modem Control

1

0

1

x

Line Status

1

1

0

x

Modem Status

1

1

1

x

Scratch (See note 3)

0

0

0

1

Divisor Latch (LSB)

0

0

1

1

Divisor Latch (MSB)

Address Bits

Notes:
1.

Bits A9 through A3 are used to select specific adapter an~ serial port.

2.

A2, AI, and AO bits are don't cares and are used to select the different registers of the NS 16450
chip.

3.

The Scratch Register of the NS 16450 module should be initialized to all ones and new data
should not enter afterwards. This would cause indeterminate data when read address X237
(see "Interrupts" on page 8) is executed.

5080 Peripheral Adapter

7

Interrupts
Three interrupts lines are provided to the system. The interrupt level (9, 10, or 11) is selected by
placing the appropriate switch on switch bank one to the on position. Interrupt levels 9, 10, and 11
are shared interrupts. An interrupt register (read address n237, where n is the first digit of address
range) is provided to store pending port interrupts. Interrupt register bit assignment as shown in
Figure 8.
Hex Address n237
Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1

1

0

1

0

Port 3

Port 2

Port 1

Figure 8.

Interrupt Register Read Format

The reset or enable for interrupt level 9 is hex address 02F2.
The reset or enable for interrupt level 10 is hex address 06F2.
The reset or enable for interrupt level 11 is hex address 06F3.

8

5080 Peripheral Adapter

Serial Data Format
The data format is as follows:

Transmit
Oata
Marking

Start
Bit

00

01

02

03

04

05

06

07

Parity
Bit

Stop
Bit

Data bit 0 is the first bit to be transmitted or received. The adapter automatically inserts the start
bit, the correct parity bit (if programmed to do so), and the stop bit (1, 1-1/2, or 2 depending on
the command in the line control register).

5080 Peripheral Adapter

9

External Interface Description
The adapter provides an asynchronous-like interface.
The pin functions for the 10-pin connector are shown in Figure 9.
PORT

E10

E05
4

9

3
2

8
7

1

Transmit Data

2

+12 VDC

3

+5VDC

4

Not Used

5

-12 VDC

6

Receive Data

7

Not Used

8

Not Used

4

9

Not Used

3
2

10

Ground

Figure 9.

E01

··

E06
F10

F05
4

9

3
2

8
7

F01
G05

G01

A

··
··
··

B

F06
G10
9
8

C

7

G06

to-Pin Interface Signals Connector (viewed from rear of adapter)

The adapter converts the data signals from TTL levels to EIA RS232C voltage levels, and vice
versa. These signals are sampled or generated by the communications control chip and can then be
sensed by the system software to determine the state of the interface or peripheral device. The
drivers and receivers used on the adapter are the inverting type; therefore, a 0 EIA level on the line
is received or transmitted as a 0 TTL level, and a 1 EIA level is received or transmitted as a 1 TTL
level.

Voltage Interchange Information
The signal is considered in the marking condition when the voltage on the interchange circuit,
measured at the interface point, is more negative than -3 Vdc with respect to signal ground. The
signal is considered in the spacing condition when the voltage is more positive than + 3 Vdc with
respect to signal ground. The region between +3 Vdc and -3 Vdc is the transition region and is
considered an invalid level. The voltage that is more negative than -25 Vdc or more positive than
+ 25 Vdc is also considered an invalid level.

10

5080 Peripheral Adapter

During the transmission of data, the marking condition denotes the binary state 1 and the spacing
condition denotes the binary state O.
For interface control circuits, the function is on when the voltage is more positive than + 3 V dc with
respect to signal ground and is off when the voltage is more negative than -3 V dc with respect to
signal ground.

State

Signal
Condition

Interface
Control
Function

+3Vdc to +25Vdc

Binary 0

Spacing

=On

-3Vdc to -25Vdc

Binary 1

Marking

= Off

Interchange
Voltage

Binary

Figure 10.

mM 5080 Peripheral Adapter Signal Levels

5080 Peripheral Adapter

11

Asynchronous Communications Element Pin Description
The following describes the function of all NS 16450 input/output pins. Some of these descriptions
reference internal circuits. The use of each signal as implemented on the IBM 5080 Peripheral
Adapter is described.
Note: In the following descriptions, a low represents a logic 0 (0 Vdc nominal) and a high
represents a logic 1 (+ 2.4 Vdc nominal).

Input Signals
Chip Select (CSO, CS1, -CS2), Pins 12-14: When CSO and CS1 are high and -CS2 is low, the chip
is selected. Chip selection is complete when the decoded chip select signal is latched with an active
(low) address strobe (-ADS) input. This enables communications between the NS16450 and the
processor.
Data Input Strobe (DISTR, -DISTR), Pins 22 and 21: When DISTR is high or -DISTR is low while
the chip is selected, the processor can read status information or data from a selected register of the
NS16450.
Note: Only an active DISTR or -DISTR input is required to transfer data from the NS16450
during a read operation. Therefore, tie either the DISTR input permanently low or the -DISTR line
permanently high, if not used.
Data Output Strobe (DOSTR, -DOSTR), Pins 19 and 18: When DOSTR is high or -DOSTR is low
while the chip is selected, the processor can write data or control words into a selected register of
the NS16450.
Note: Only an active DOSTR or -DOSTR input is required to transfer data to the NS16450 during
a write operation. Therefore, tie either the DOSTR input permanently low or the -DOSTR input
permanently high, if not used.
-Address Strobe (-ADS), Pin 25: When low, this signal provides latching for the register select (AO,
A1, A2) and chip select (CSO, CS1, -CS2) signals.
Note: An active -ADS input is required when the register select (AO, A1, A2) signals are not stable
for the duration of a read or write operation. If not required, tie the -ADS input permanently low.

12

5080 Peripheral Adapter

Register Select (AO, AI, A2), Pins 26-28: These three inputs are used during a read or write
operation to select an NS16450 register to read from or write into as indicated in Figure 11. Note
that the state of the divisor latch access bit (DLAB), which is the most significant bit of the line
control register, affects the selection of certain NS16450 registers. The DLAB must be set high by
the system software to access the baud-generator divisor latches.
DLAB

A2

At

AO

Register

0

0

0

0

Receiver Buffer (Read)
Transmitter Holding Register (Write)

0

0

0

1

Interrupt Enable

x

0

1

0

Interrupt Identification (Read Only)

x

0

1

1

Line Control

x

1

0

0

Modem Control

x

1

0

1

Line Status

x

1

1

0

Modem Status

x

1

1

1

Scratch

1

0

0

0

Divisor Latch (Least Significant Byte)

1

0

0

1

Divisor Latch (Most Significant Byte)

Figure 11.

NS16450 Register Selection

Master Reset (MR), Pin 35: When high, this signal clears all the registers (except the receive buffer,
transmitter holding, and divisor latches), and the control logic of the NS16450. Also, the state of
various output signals (SOUT, INTRPT, -OUT 1, -OUT 2, -RTS, -DTR) is affected by an active
MR input. Refer to the table in Figure 12 on page 14 for reset functions.

5080 Peripheral Adapter

13

Register/Signal

Reset Control

Reset State

Interrupt Enable
Register

Master Reset

All Bits Low 0-3
Forced and 4-7
Permanent

Interrupt
Identification Register

Master Reset

Bit 0 is High, Bits 1
and 2 are Low, and
Bits 3-7 are
Permanently Low

Line Control Register

Master Reset

All Bits Low

Modem Control
Register

Master Reset

All Bits Low

Line Status Register

Master Reset

All Bits Low, except
Bits 5 and 6 are High

Modem Status
Register

Master Reset

Bits 0-3 are Low
Bits 4-7 = Input Signal

SOUT

Master Reset

High

INTRPT (RCVR
Errors)

Read LSR/MR

Low

INTRPT (RCVR
Data Ready)

ReadRBR/MR

Low

INTRP (THRE)

Read UR/
Write THR/MR

Low

INTRPT (Modem
Status Changes)

Read MSR/MR

Low

Master Reset
Master Reset
Master Reset
Master Reset

High
High
High
High

•
•
•
•

OUT 2
RTS
DTR
OUTl

Figure 12.

14

NS16450 Reset Functions

5080 Peripheral Adapter

Receiver Clock (RCLK), Pin 9: This input is the 16x baud-rate clock for the receiver section of the
chip.
Serial Input (SIN), Pin 10: Serial data input from the communications link (peripheral device,
modem, or data set).
-Clear to Send (-CTS), Pin 36: The -CTS signal is a modem control function input whose condition
can be tested by the processor by reading bit 4 (CTS) of the modem status register. Bit 0 (DCTS)
of the modem status register indicates whether the -CTS input has changed state since the previous
reading of the modem status register.
Note: This pin is permanently tied low.
-Data Set Ready (-DSR), Pin 37: The -DSR signal is a modem control function input whose
condition can be tested by the processor by reading bit 5 ( DSR) of the modem status register.
When low, this signal indicates that the modem or data set is ready to establish the communications
link and transfer data with the NS 16450. Bit 1 (DDSR) of the modem status register indicates
whether the -DSR input has changed since the previous reading of the modem status register.
Note: This pin is permanently tied low.
-Received Line Signal Detect (-RLSD), Pin 38: The -RLSD signal is a modem control function
input whose condition the processor can test by reading bit 7 (RLSD) of the modem status register.
When low, this signal indicates that the data carrier had been detected by the modem or data set.
Bit 3 (RLSD) of the modem status register indicates whether the -RLSD not input has changed
state since the previous reading of the modem status register.
Notes:
1. Received Line Signal Detect is also called Data Carrier Detect (DCD), or Carrier Detect (CD).
2.

This pin is permanently tied low.

-Ring Indicator (-RI), Pin 39: The -RI signal is a modem control function input whose condition the
processor can test by reading bit 6 (RI) of the modem status register. When low, this signal
indicates that a telephone ringing signal has been received by the modem or data set. Bit 2 (TERI)
of the modem status register indicates whether the -RI input has changed from a low to high state
since the previous reading of the modem status register.

Note: This pin is permanently tied high.
VCC, Pin 40: +5 Vdc supply.
VSS, Pin 20: Ground (0 Vdc) reference.

5080 Peripheral Adapter

15

Output Signals
-Data Terminal Ready (-DTR), Pin 33: When low, this signal informs the modem or data set that
the NS 16450 is ready to communicate. The -DTR output signal can be set to an active low by
programming bit 0 (DTR) of the modem control register to a high level. The -DTR signal is set
high by a master reset operation. The -DTR signal is set high during loop mode operation.
Note: No connection, not used.
-Request to Send (-RTS), Pin 32: When low, this signal informs the modem or data set that the
NS16450 is ready to transmit data. The -RTS output signal can be set to an active low by
programming bit 1 (RTS) of the modem control register. The -RTS signal is set high by a master
reset operation. The -RTS signal is set high during loop mode operation.
Note: No connection, not used.
-Output 1 (-OUT 1), Pin 34: With this signal, user-designated output can be set to an active low by
programming bit 2 (-OUT 1) of the modem control register to a high level. The -OUT 1 signal is
set high by a master reset operation. The -OUT 1 signal is set high during the loop mode operation.
Note: No connection, not used.
-Output 2 (-OUT 2), Pin 31: With this signal, user-designated output can be set to an active low by
programming bit 3 (-OUT 2) of the modem control register to a high level. The -OUT 2 signal is
set high by a master reset operation. The -OUT 2 signal is set high during the loop mode operation.
Note: No connection, not used.
Chip Select Out (CSOUT), Pin 24: When high, this signal indicates that the chip has been selected
by active CSO, CS1, and -CS2 inputs. No data transfer can be initiated until the CSOUT signal is a
logic 1.
Note: No connection, not used.
Driver Disable (DDIS), Pin 23: This signal goes low whenever the processor is reading data from
the NS16450. A high-level DDIS output can be used to disable an external transceiver (if used
between the processor and NS 16450 on the D7 -DO data bus) at all times, except when the
processor is reading data.
Note: No connection, not used.
-Baudout (-BAUDOUT), Pin 15: This signal is a 16x clock signal for the transmitter section of the
NS16450. The clock rate is equal to the main reference oscillator frequency divided by the
specified divisor in the baud-generator division latches. The -Baudout may also be used for the
receiver section by tying this output to the RCLK input of the chip.
Note: This pin is tied to RCLK pin 9.
Interrupt (INTRPf), Pin 30: This signal goes high whenever anyone of the following interrupt
types has an active high condition and is enabled through the IER: receiver error flag, received data

16

5080 Peripheral Adapter

available, transmitter holding register empty, or modem status. The Interrupt signal is reset low on
the appropriate interrupt service or a master reset operation.

Note: Generates interrupt request.
Serial Output (SOUT), Pin 11: Composite serial data output to the communications link
(peripheral, modem or data set). The SOUT signal is set to the marking (logic 1) state on a master
reset operation.

Note: Provides data to attached device.

Input/Output Signals
Data Bus (07-00), Pins 1-8: This bus consists of eight tri-state I/O lines. The bus provides
bidirectional communications between the NS16450 and the processor. Data, control words, and
status information are transferred through the D7-DO data bus.

External Clock Input/Output (XTALl, XTAL2), Pins 16 and 17: These two pins connect the main
timing reference (crystal or signal clock) to the NS 16450.

5080 Peripheral Adapter

17

Programming Considerations
The NS16450 has several accessible registers. The system programmer may access or control any
of the NS16450 registers through the processor. These registers are used to control NS16450
operations and to transmit and receive data.
Note: The n in address is the card number (1-4).

Line Control Register
The system programmer specifies the format of the asynchronous data communications exchange
through the line control register. In addition to controlling the format, the programmer may retrieve
the contents of the line control register for inspection. This feature simplifies system programming
and eliminates the need for separate storage of the line characteristics in system memory. The
contents of the line control register are described below:

Line Control Register
(Hex Address n233, n238, n243)
Bit

7

6

5

4

3

2

a

I I I :

--...

...

-..

Word length select bit 0
Word length select bit 1
Number of stop bits
Parity enable
Even parity select
Stick parity
Set break

" - - - - - - - - - - - -. . Divisor latch access bit

18

5080 Peripheral Adapter

Bits 0, 1

These two bits specify the number of bits in each transmitted or received serial
character. The encoding of bits 0 and 1 is as follows:
Bit 1

Bit 0

Word Length

0

0

5 bits

0

1

6 bits

1

0

7 bits

1

1

8 bits

Bit 2

This bit specifies the number of stop bits in each transmitted or received serial
character. If bit 2 is a logical 0, one stop bit is generated or checked in the transmit or
receive data, respectively. If bit 2 is a logical 1 when a 5-bit word length is selected
through bits 0 and 1, 1-1/2 stop bits are generated or checked. If bit 2 is a logical 1
when either a 6-, 7-, or 8-bit word length is selected, two stop bits are generated or
checked.

Bit 3

This bit is the parity enable bit. When bit 3 is a logical 1, a parity bit is generated
(transmit data) or checked (receive data) between the last data word bit and stop bit of
the serial data. (The parity bit is used to produce an even or odd number of 1's when
the data word bits and the parity bit are summed.)

Bit 4

This bit is the even parity select bit. When bit 3 is a logical 1 and bit 4 is a logical 0, an
odd number of logical 1 is transmitted or checked in the data word bits and parity bit.
When bit 3 is a logical 1 and bit 4 is a logical 1, an even number of bits are transmitted
or checked.

BitS

This bit is the stick parity bit. When bit 3 is a logical 1 and bit 5 is a logical 1, the
parity bit is transmitted and then detected by the receiver as a logical 0 (space parity) if
bit 4 is a logical 1, or as a logical 1 (mark parity) if bit 4 is a logical O.

Bit 6

This bit is the set break control bit. When bit 6 is a logical 1, the serial output (SOUT)
is forced to the spacing (logical 0) state and remains there regardless of other
transmitter activity. The set break is disabled by setting bit 6 to a logical O. This
feature enables the processor to alert a terminal in a computer communications system.

Bit 7

This bit is the divisor latch access bit (DLAB). It must be set high (logicall) to access
the divisor latches of the baud-rate generator during a read/write operation. It must be
set low (logical 0) to access the receiver buffer, the transmitter holding register, or the
interrupt enable register.

5080 Peripheral Adapter

19

Line Status Register
This 8-bit register provides status information to the processor about the data transfer. The
contents of the line status register are described below:
Line Status Register
(Hex Address n235, n230, n245 )
Bit

7

6

I

5

4

3

lS

2

1

a

-...---

Parity error
Framing error
Break interrupt

---

Transmitter holding

-...

Tx shift register empty

..-

20

Data ready
Overrun error

register empty

=

a

Bit 0

This bit is the receiver data ready (DR) indicator. Bit 0 is set to a logicall whenever a
complete incoming character has been received and transferred into the receiver buffer
register. Bit 0 may be reset to a logical 0 either by the processor reading the data in
the receiver buffer or by writing a logical 0 into it from the processor.

Bit 1

This bit is the overrun error (OE) indicator. Bit 1 indicates that data in the receiver
buffer register was not read by the processor before the next character was transferred
into the receiver buffer register, and thereby destroyed the previous character. The OE
indicator is reset whenever the processor reads the contents of the line status register.

Bit 2

This bit is the parity error (PE) indicator. Bit 2 indicates that the received data
character does not have the correct even or odd parity as selected by the even parity
select bit. The PE bit is set to a logical 1 whenever a parity error is detected and is
reset to a logical 0 whenever the processor reads the contents of the line status register.

Bit 3

This bit is the framing error (FE) indicator. Bit 3 indicates that the received character
does not have a valid stop bit. Bit 3 is set to a logical 1 whenever the stop bit following
the last data bit or parity is detected as a zero bit (spacing level).

Bit 4

This bit is the break interrupt (BI) indicator. Bit 4 is set to a logicall whenever the
received data input is held in the spacing (logical 0) state for longer than a full word
transmission time (that is, the total time of start bit + data bits + parity + stop bits).

5080 Peripheral Adapter

Note: Bits 1 through 4 are the error conditions that produce a receiver line status
interrupt whenever any of the corresponding conditions are detected.
Bit S

This bit is the transmitter holding register empty (THRE) indicator. Bit 5 indicates
that the NS 16450 is ready to accept a new character for transmission. In addition, this
bit causes the NS16450 to issue an interrupt to the processor when the THRE interrupt
enable is set high. The THRE bit is set to a logical 1 when a character is transferred
from the transmitter holding register into the transmitter shift register. The bit is reset
to logical 0 concurrently with the loading of the transmitter holding register by the
processor.

Bit 6

This bit is the transmitter empty (TEMT) indicator. Bit 6 is set to a logical 1 whenever
the transmitter holding register (THR) and the transmitter shift register (TSR) are both
empty. It is reset to logical 0 whenever either the THR or TSR contain a data
character. Bit 6 is a read-only bit.

a

Bit 7

This bit is permanently set to logical O.

Interrupt Identification Register
The NS16450 has an on-chip interrupt capability that allows for complete flexibility in interfacing to
microprocessors. To provide minimum software overhead during data character transfers, the
NS 16450 ranks interrupts into four levels:
•

Receiver line status (priority 1)

•

Received data ready (priority 2)

•

Transmitter holding register empty (priority 3)

•

Modem status (priority 4).

Information indicating that a priority interrupt is pending and information on the type of interrupt is
stored in the interrupt identification register. Refer to the "Interrupt Control Functions" table in
Figure 13 on page 23. The interrupt identification register (IIR), when addressed during
chip-select time, freezes the highest priority interrupt pending, and no other interrupts are
acknowledged until that particular interrupt is serviced by the processor. The contents of the IIR
are described below.

5080 Peripheral Adapter

21

Interrupt Indentiflcatlon Register
(Hex Address n232, n23A, n242 )
Bit

7

6

5

4

3

2

I

1

0

~:
...

-.-..
--......

-.....

22

0 If interrupt pending
Interrupt 10 bit (0)
Interrupt 10 bit (1)
=0
=0
=0
=0
=0

Bit 0

This bit can be used in hardwired, priority, or polled environment to indicate whether
an interrupt is pending. When bit 0 is a logical 0, an interrupt is pending and the IIR
contents may be used as a pointer to the appropriate interrupt service routine. When
bit 0 is a logical 1, no interrupt is pending and polling (if used) is continued.

Bits 1, 2

These two bits of the IIR are used to identify the highest priority interrupt pending as
indicated in Figure 13 on page 23.

Bits 3-7

These five bits of the IIR are always logical o.

5080 Peripheral Adapter

Interrupt
Interrupt Set and Reset Functions

ID

Register
Bit

Bit
1

Bit

0

0

1

1

1

0

1

0

0

0

2

Interrupt
Type

Interrupt
Source

None

None

Highest

Receiver
Line
Status

Overrun Error or
Parity Error or
Framing Error or
Break Intrpt.

Reading the Line
Status Register

0

Second

Received
Data
Available

Receiver Data
Available

Reading the Receiver
Buffer Register

1

0

Third

Transmitter
Holding
Register
Empty

Transmitter Holding
Register Empty

Reading the IIR
Register or Writing
into the Transmitter
Holding Register

0

0

Fourth

Modem
Status

Clear to Send or Data
Set Ready or Ring
Indicator or Received
Line Signal Detect

Reading the Modem
Status Register

Figure 13.

0

Priority
Level

-

Interrupt
Reset Control

-

Interrupt Control Functions

5080 Peripheral Adapter

23

Interrupt Enable Register
This 8-bit register enables the four types of interrupts of the NS 16450 to separately activate the
chip interrupt (INTRPT) output signal. The interrupt system can be totally disabled by resetting
bits 0 through 3 of the interrupt enable register. Similarly, by setting the appropriate bits of this
register to a logical 1, selected interrupts can be enabled. Disabling the interrupt system inhibits the
interrupt identification register and the active (high) INTRPT output from the chip. All other
system functions operate in their normal manner, including the setting of the line status and modem
status registers. The contents of the interrupt enable register are described below:
Interrupt Enable Register
(Hex Address n231, n239, n241 )
Bit

7

6

5

4

3

2

DLAB

1

II

=0

0

I :

..---..
---

Enable data available interrupt
Enable Tx holding register
empty interrupt
Enable receive line status
interrupt
Enable modem status
interrupt

=0

-. = 0

-.

--

24

=0
=0

Bit 0

This bit enables the received data available interrupt when set to logical 1.

Bit 1

This bit enables the transmitter holding register empty interrupt when set to logical 1.

Bit 2

This bit enables the receiver line status interrupt when set to logical 1.

Bit 3

This bit enables the modem status interrupt when set to logical 1.

Bits 4-7

These four bits are always logical O.

5080 Peripheral Adapter

Modem Control Register
This 8-bit register controls the interface with the modem or data set (or other peripheral device).
The contents of the modem control register are described below:
Mode~ Control RegIster
(Hex Address n234, n23C, n244 )

Bit

7

6

5

4

3

2

a
Data terminal ready
Request to send

~--------~~~
~------------~~~
L-------------tl~~
L.....-----------tl~~

"'---------------------------e-~

Bit 0

OUT1
OUT2
LOOP

a
=a
=a
=

This bit controls the data terminal ready (-DTR) output. When bit 0 is set to a logical
1, the -DTR output is forced to a logical O. When bit 0 is reset to a logical 0, the -DTR
output is forced to a logical 1.
Note: The -DTR output of the NS16450 may be applied to an EIA inverting line
driver to obtain the proper polarity input at the modem or data set.

Bit 1

This bit controls the request to send (-RTS) output. Bit 1 affects the -RTS output in a
manner identical to that described above for bit O.
Note: The -RTS output of the NS16450 may be applied to an EIA-inverting line
driver to obtain the proper polarity input at the modem or data set.

Bit 2

This bit controls the output 1 (-OUT 1) signal, which is an auxiliary user-designated
output. Bit 2 affects the -OUT 1 output in a manner identical to that described above
for bit O.
Note: The -OUT 1 output of the NS 16450 may be applied to an EIA inverting line
driver to obtain the proper polarity input at the modem or data set.

Bit 3

This bit controls the output 2 (-OUT 2) signal, which is an auxiliary user-designated
output. Bit 3 affects the -OUT 2 output in a manner identical to that described above
for bit O.
Note: The -OUT 2 output of the NS 16450 may be applied to an EIA inverting line
driver to obtain the proper polarity input at the modem or data set.

5080 Peripheral Adapter

25

Bit 4

This bit provides a loopback feature for diagnostic testing of the NS16450. When bit 4
is set to logical 1, the following occurs:
The transmitter serial output (SOUT) is set to the marking (logical 1) state.
The receiver serial input (SIN) is disconnected.
The output of the transmitter shift register is "looped back" into the receiver shift
register input.
The four modem control inputs (-CTS, -DSR, -RLSD, and -RI) are disconnected.
The four modem control outputs (-DTR, -RTS, -OUT 1, and -OUT 2) are
internally connected to the four modem control inputs, and the modem control
output pins are forced high.
In the the diagnostic mode the receiver and transmitter interrupts are fully operational.
The modem control interrupts are also operational, but the sources of the interrupts are
now the lower 4 bits of the modem control register instead of the 4 modem control
inputs. The interrupts are still controlled by the interrupt enable register.
The NS 16450 interrupt system can be tested by writing into the lower 6 bits of the line
status register and into the lower 4 bits of the modem status register. Setting any of
these bits to a logical 1 generates the appropriate interrupt (if enabled). The resetting
of these interrupts is the same as in normal NS 16450 operation. To return to normal
operation, the registers must be reprogrammed for normal operation and then bit 4 of
the modem control register must be reset to logical O. The transmitter should be idle
when this bit changes state.

Bits 5-7

26

These bits are permanently set to logical O.

5080 Peripheral Adapter

Modem Status Register
This 8-bit register provides the current state of the control lines from the modem (or peripheral
device) to the processor. In addition to this current-state information, 4 bits of the modem status
register provide change information. These bits are set to a logical 1 whenever a control input from
the modem changes state. They are reset to logical 0 whenever the processor reads the modem
status register.
The contents of the modem status register are described below:
Modem Status Register
(Hex Address n236, n23E, n246 )
Bit

7

6

5

4

3

2

I

1

I

0

1_:
-

-..
----...
-

Delta clear to send

Delta data set ready
Trailing edge ring
indicator
Delta RX line signal
detect
Clear to send
Data set ready
Ring indicator
Receive line signal
detect

Bit 0

This bit is the delta clear-to-send (DCTS) indicator. Bit 0 indicates that the -CTS
input to the chip has changed state since the last time it was read by the processor.

Bit 1

This bit is the delta data set ready (DDSR) indicator. Bit 1 indicates that the -DSR
input to the chip has changed state since the last time it was read by the processor.

Bit 2

This bit is the trailing edge of the ring indicator (TERI) detector. Bit 2 indicates that
the -RI input to the chip has changed from an ON (logicall) to an OFF (logical 0)
condition.

Bit 3

This bit is the delta received line signal detector (DRLSD) indicator. Bit 3 indicates
that the -RLSD input to the chip has changed state since the last time it was read by
the processor.
Note: Whenever bit 0, 1, 2, or 3 is set to a logical 1, a modem status interrupt is
generated, if the appropriate interrupt enable bit is set in the IER.

5080 Peripheral Adapter

27

Bit 4

This bit is the complement of the clear to send (-CTS) input. Setting bit 4 (loop) of
the MCR to a logicall, is equivalent to RTS in the MCR.

Bit 5

This bit is the complement of the data set ready (-DSR) input. If bit 4 (loop) of the
MCR is set to a logicall, this bit is equivalent to DTR in the MCR.

Bit 6

This bit is the complement of the ring indicator (-RI) input. If bit 4 (loop) of the MCR
is set to a logical l, this bit is equivalent to -OUT 1 in the MCR.

Bit 7

This bit is the complement of the received line signal detect (-RLSD) input. If bit 4
(loop) of the MCR is set to a logicall, this bit is equivalent to -OUT 2 of the MCR.

Receiver Buffer Register
The receiver buffer register contains the received character as defined below:

Receive Buffer Register
(Hex Address n230, n238, n240)
Bit

7

6

5

4

3

2

Read Only DLAB = 0

1

a

EDatabitO

Data bit 1

...

Data bit 2

-.-.

Data bit 5

-.-.
~

Data bit 3
Data bit 4

Data bit 6
Data bit 7

Bit 0 is the least significant bit and is the first bit serially received.

28

5080 Peripheral Adapter

Transmitter Holding Register
The transmitter holding register contains the character to be serially transmitted and is defined
below:
Transmitter Holding Register
(Hex Address n230, n238, n240)
Bit

7

6

5

4

3

2

Write Only DLAB = 0

1

a

lSoatabita

Data bit 1

-....
---...
---...
-

Data bit 2
Data bit 3
Data bit 4
Data bit 5
Data bit 6
Data bit 7

Bit 0 is the least significant bit and is the first bit serially transmitted.

Programmable Baud-Rate Generator
The NS16450 contains a programmable baud-rate generator that can divide the clock input (1.8.432
MHz) by any divisor from 1 to 655,535 or 216_1. The output frequency of the baud-rate generator
is the baud rate multiplied by 16. Two 8-bit latches store the divisor in a 16-bit binary format.
These divisor latches must be loaded during initialization to insure desired operation of the
baud-rate generator. Upon loading either of the divisor latches, a 16-bit baud counter is
immediately loaded. This prevents long counts on initial load. The contents of the divisor latches
are indicated below:

5080 Peripheral Adapter

29

Divisor Latch Least Significant Byte
(Hex Address n230, n238, n240)
Bit

7

6

5

4

3

2

DLAB

1

=1

a

l§DatabitO

Data bit 1

-..-..

--....

Data bit 3

JIll"

Data bit 4

JIll"

Figure 14.

Data bit 2

Data bit 5
Data bit 6
Data bit 7

Divisor Latch Least Significant Byte

DLAB = 1

Divisor Latch Most Significant Byte
(Hex Address n231, n239, n241)
Bit

7

6

5

4

3

2

1

0

~

LS

Data bit 8

~Databit9

L...._ _ _ _ _ _.;
..

Data bit 10
Data bit 11

L....._ _ _ _ _ _ _--=~

Data bit 12

L...._ _ _ _ _ _ _ _ _:~

Data bit 13

L...._ _ _ _ _ _ _ _ _ _ _.
:..

Data bit 14

L....._ _ _ _ _ _ _ _ _ _ _ _

Figure 15.

30

Divisor Latch Most Significant Byte

5080 Peripheral Adapter

..

~~

Data bit 15

Figure 16 illustrates the use of the baud-rate generator with a frequency of 1.8432 MHz. For baud
rates of 19,200 and below, the error obtained is minimal.
Note: The maximum operating frequency of the baud generator is 3.1 MHz. The data rate should
never be greater than 19,200 baud.
Desired
Baud
Rate

Divisor Used to Generate
16x Clock
(Hex)
(Decimal)

Percent Error
Difference Between
Desired and Actual

50

2304

900

-

75

1536

600

-

110

1047

417

0.026

134.5

857

359

0.058

150

786

300

300

384

180

600

192

CO

-

1200

96

60

-

1800

64

40

-

2000

58

3A

0.69

2400

48

30

3600

32

20

4800

24

18

7200

16

10

9600

12

C

-

19200

6

6

-

Figure 16.

Baud Rates at 1.8432 MHz

5080 Peripheral Adapter

31

Connector Specifications
The adapter has a lO-pin connector at the rear of the adapter. The following figure shows the
signals and their pin assignments.

External
Device

Figure 17.

32

Connector Specifications

5080 Peripheral Adapter

Transmit Data

1

+ 12

2

+5

3

Not Used

4

-12

5

Receive Data

6

Not Used

7

Not Used

8

Not Used

9

Signal Ground

10

5080
Peripheral
Adapter

------ -- -- ------

--_.-

Advanced Color
Graphics Display
Adapter

Personal Computer
Hardware Reference
Library

ii

Advanced Color Graphics Display Adapter

Contents

Description ............................................................
Operation ...................................................................
Bit Map Memory Operations ....................................................
110 Operations ...............................................................
Connector Specifications ..... .' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

Contents

1
3
5
6
12

iii

iv

Advanced Color Graphics Display Adapter

Description

The Advanced Color Graphics Display Adapter attaches to the I/O channel and drives a 14-inch
color display at a 46 Hz (frame rate) or 92 Hz (field rate) interlace refresh rate. The adapter
provides a 256K-byte bit map that is translated to the screen as 720 pels horizontally by 512 pels
vertically, at 4 bits per pel. A 4-plane bit map (64K-byte each plane) is provided from which 16
colors are picked from a 64 color palette.
The adapter includes several hardware performance assists, including a write mask to protect bit
fields within a byte, a barrel shifter to rotate bits within a byte, and a logic unit to combine source
bytes before they are written into the bit map. In addition, a plane select register and foreground or
background register are provided as a means to select individual planes or all planes for update with
each system access using preprogrammed foreground or background color data. A 4-bit to 6-bit
video lookup Random Access Memory (RAM), writeable from the system, is also provided for the
selection of 16 usable colors from a palette of 64 available colors, and is represented to the monitor
using 2-bits per primary color (red, red intense, green, green intense, blue and blue intense).
Figure 1 on page 2 is a block diagram of the Advanced Color Graphics Display Adapter.

Advanced Color Graphics Display Adapter

1

DECODES

,..----3

""""---2

I

CLOCKS

........- - - 0
64KX8

r

MEMORY

SYNCS

4/1
SYS
- - ADDRESS-20
BUS
<8X4>

$
LOGIC
UNIT
CNTL--

FG/BG

PLNSEL

STATUS
SYS
--DATA-16
BUS

Figure 1.

2

Advanced Color Graphics Display Adapter Functional Block Diagram

Advanced Color Graphics Display Adapter

Operation
Data to be displayed is written into the 64K x 8 x 4 plane bit map memory by the system. This data
is then scanned out of the memory and sent as a serial video stream to the monitor.
The system processor can manipulate data residing in the bit map memory in several ways. The
choice of a particular,method is controlled by the type of instruction (Load or Store) and the
current value of a 2-bit mode field which resides within a 16-bit control register. The contents of
the control register must be initialized prior to the memory operation.
Hardware on the card allows data in the bit map to be manipulated without passing through a
processor. This hardware includes:
•
•
•
•
•

A 16-bit write mask that enables write operations to individual bits
A shifter that realigns bits before they are written to memory
Data registers to hold data being processed
Two 8-bit data mask registers that select bits being merged from data registers
A logic unit that does all the actual merging.

Using this hardware, source data from either the system or from the bit map may replace or be
merged with data in the bit map. Images on the screen (in the bit map) can thus be moved,
inverted, overlaid, or replaced.
The adapter occupies two address ranges on the I/O channel. Sixteen bytes of I/O address space at
X '0150' through '015F' are used to load the data mask register, and the control registers. See the
section entitled "I/O Operations" on page 6 for specific register addresses and bit assignments.
The second address range occupied by the adapter is the bit map memory that consists of
128K-bytes starting at hex address 'D20000' in memory space on the I/O channel. When
addressing the bit map memory, the low order address bit must be o. Address bits A01 through
A16 are used to access memory. Address bit AOO is not used during memory accesses. This
restriction arises because the adapter allows word accesses to the bit map to begin on either even or
odd byte boundaries. Because the system restricts half-word accesses to even bytes, address lines to
the bit map memory are offset by one bit.
The most significant data byte of the I/O channel is written into or read from the bit map memory
location specified by the shifted address lines. The least significant data byte is written into or read
from the memory location specified by the shifted address lines increased or decreased by one in the
X or Y direction. The increase and decrease bits of the control register determine whether the
address is increased or decreased. The X and Y bits of the control register determine whether the X
or Y direction is changed.
As a result of the addressing scheme described above, each physical memory location in the bit map
can be accessed at either of two addresses. Access directly through the most significant byte, or
after the address bus has been increased or decreased, through the least significant byte.

Advanced Color Graphics Display Adapter

3

r

0000
0080

0001
0081

0002
0082

0003 - 0058
0083 - 0008

0059
0009

005A
OOOA

005B - 007E
OOOB - OOFE

007F
OOFF

FF80

FF81

FF82

FF83 - FF08

FF09

FFOA

FFOB - FFFE

FFFF

512
Scan
Lines

L

90 Bytes Visible Memory

.I~

38 Bytes Hidden Memory

128 Bytes Total Bit Map Memory Width

Figure 2.

Bit Map Memory Addresses

The mapping between the physical addresses shown in Figure 2 and denoted as 'P' in the equations
and the I/O channel address denoted as 'C' in the equations is shown, as folluws, for each of the
increase and decrease bits and the X and Y status bits.

I/O Channel
Byte
MSByte
LS Byte
LS Byte
LS Byte
LS Byte

Word Storage Location
Physical to
Inc/Dec X/V
I/O Channel
either
+

+

either
X
X
Y
Y

C=2P
C=2P-2
C=2P+2
C=2P-256
C=2P+256

I/O Channel
to Physical

=>
=>
=>
=>
=>

P=C/2
P=C/2 +1
P=C/2 -1
P=C/2 +128
P=C/2 -128

Figure 2 shows how on-card physical memory byte addresses are mapped to the display screen.
The bits in each byte are shifted onto the screen with the most significant bit to the left.

4

Advanced Color Graphics Display Adapter

Bit Map Memory Operations
The following are possible memory operations and respective mode bit definitions.

System Write Operation (Mode

= 00)

This operation writes 16 bits of external data to the bit map memory at the address specified in the
system processor 'Store' instruction.

Overlay Write Operation (Mode

= 01)

This operation writes 16 bits of external data to the onboard write-mask registers (WMI and
WM2). It also initiates a write operation of the onboard system data latches to the bit map memory
at the address specified in the system processor 'Store' instruction. The new value in the write mask
controls the write to the bit map. This operation will not affect the contents of the system data
latches. Preloading the system data latches with the proper constant makes it possible to 'AND' or
'OR' system data with the bit map memory in one memory operation.

Adapter Write Operation (Mode == 10)
This operation writes data from the onboard data latches (D 1,D2,D3) to the bit map memory using
the rotate count, write mask, data mask, data bus and the logic unit. The following operations must
be completed before executing this operation:
•

Load the data latches using an adapter read operation.

•

Load the write mask using an overlay write operation.

•

Load the operation mode, rotate count and logic function using an I/O 'Store' to the adapter
control register.

Advanced Color Graphics Display Adapter

5

System Read Operation (Mode

= XX)

This operation reads 16 bits of data from the bit map memory and places it on the system data bus.
Onboard data latches D 1, D2, and D3 are updated by this operation. Data is loaded into latches
Dl, D2, and D3 regardless of the setting of the mode. However, valid data is returned to the system
processor only if the mode is '00'. Data returned to the system is from the lowest numbered plane
that is enabled for reading.

Automatic Read/Write Operation (Mode

=

11)

In this mode of operation, data is alternately read into D 1, D2 and D3 and then written to memory
with successive write operations from the microprocessor. Data read from memory is not gated
onto any busses external to the data path, but is used only to update D 1, D2, and D3. This allows
the fast 'Store' operation to be used for block transfer operations with no 'Loads' required.
To get the alternate read/write operations into phase with the source and destination addresses, the
system processor should do a 'Load' operation from the first source address. Subsequent 'Stores'
will automatically alternate between read and writes to the bit map.

110 Operations
To manipulate the various registers on the adapter, a set of I/O operations are required.

Data Mask Register (X'OI52') Write Only
Typically these two 8-bit registers (DMI and DM2) are initialized with data representing the
inverse of each other, and are used to mask the bits on or off for logical combination through the
logic unit.

6

•

An 8 bit for DMI Mask (Data Bus MS Byte, bits 0-7)

•

An 8 bit for DM2 Mask (Data Bus LS Byte, bits 0-7).

Advanced Color Graphics Display Adapter

Data Control Register (X'OlSO') Write Only
Bits 0 through 11 should not be changed for at least 1.4 microseconds after a memory operation
since the memory operation may still be in progress.
Bits 0-2

Rotate Count
The rotate count determines the number of bits that the data read from the bit
map is shifted to the left prior to being written back into the bit map. This
value has no effect during system write or overlay write modes. It has effect.
only during adapter write or automatic write modes.

Bits 3-5

Logic Unit Function Control
Bit
543
000 - Pass through B
010 - Pass through A
100 - Pass through 'Not' B
101-A 'OR'B
110 - Pass through 'Not' A
111 - A 'NOR' B
Logic unit function control bits (bits 3-5) determine how data previously read
from the bit map or written from the system are merged before being written
into the bit map. When set to '101 'B, the bit fields masked off by the data
mask register are merged with system data before being written back into the
bit map memory. This is the function normally needed during adapter write
and automatic write modes. When set to '010'B, the bit field masked off by
data mask register 1 (DMl) is written into the bit map memory. This is the
function normally needed in system write and overlay write modes. When set
to 'OOO'B, the bit field masked off by data mask register 2 (DM2) is written
into the bit map memory. This function can be used in adapter write and
automatic write modes when no bit shift is used. In each case, an inverting
form of the operation exists to allow data to be inverted as it is written to the
bit map. See "Bit Map Memory Operations" on page 5 for further
explanations.

Bits 6-7

Reserved

Advanced Color Graphics Display Adapter

7

Bits 8-9

Memory Mode
Bit

98
00 = System write operation
01 = Overlay write operation
10 = Adapter write operation
11 = Automatic read/write operation
Bit 10

Address Counter Mode

o = Increase the address counter
1 = Decrease the address counter
Bit 11

Address Counter Stepping

o = Y stepping
1

=X

stepping

Bits 10 and 11 control whether the LSB of a bit map memory operation is accessed
from the left, right, above or below the MSB. See "Bit Map Memory Operations"
on page S. for further explanation.
Bit 12

Block transfer
Bit 12 controls block transfer mode. When this bit is set from a 0 to a 1, the
address of the next memory location accessed is stored in a pointer register on
the card. This address is adjusted to point at the next memory location at the
end of each memory cycle. That is, the X or Y address is increased or
decreased. After the first block transfer memory cycle has loaded the on-card
pointer register, the memory address supplied on the data bus is ignored, and
the pointer is used to access memory. To reload the pointer register, either
clear and set the block transfer bit again or read from the block transfer reload
I/O address, X'01S2'.

Bit 13

Interrupt enable
If bit 13 is 1, an interrupt is generated at the start of vertical sync. If this bit is

0, the interrupt is not generated. See "Interrupts" on page 11.
Bit 14

Sync enable (always 1)

Bit 15

Video enable

o = Disables video to monitor
1 = Enables video to monitor

8

Advanced Color Graphics Display Adapter

Color Plane Select Register X'OlS4' Write Only
Color planes can only be written or read by the system if the corresponding plane select bit is
active.
If more than one plane is enabled during a read operation, only the lowest numbered is enabled to

the I/O channel.
Bits 0-3

Bit 4

Color plane select
Bit 0

1 = Plane select 0

Bit 1

1

Bit 2

1 = Plane select 2

Bit 3

1 = Plane select 3

1

=

=

Plane select 1

Foreground/background multi-plane write enable

If bit 4 is a 0, data bits written into a bit map plane are stored as written. If bit 4 is a 1,
data is translated to the foreground bit (data = 1) or into the background bit (data =
0). This allows all selected planes to be updated simultaneously with the selected
foreground and background colors.
Bits 5-7

Reserved

Foreground/Background Register X'lS6' Write Only
The foreground/background register is physically contained in the data path LSI modules, with a
foreground and background bit pair implemented per plane.
Bits 0-3

Bits 4-7

Foreground color
Bit 0

Foreground plane 0 - LSI module 0

Bit 1

Foreground plane 1 - LSI module 1

Bit 2

Foreground plane 2 - LSI module 2

Bit 3

Foreground plane 3 - LSI module 3

Background Color
Bit 4

Background plane 0 - LSI module 0

Bit 5

Background plane 1 - LSI module 1

Bit 6

Background plane 2 - LSI module 2

Bit 7

Background plane 3 - LSI module 3

Advanced Color Graphics Display Adapter

9

RAS Status Register (X'0150') Read Only
Bit 0

1 = Even

0 = Odd field

Bit 1

Horizontal sync toggle latch

Bit 2

0 = Vertical sync inactive

Bit 3

Reserved

Bit 4

1= X

Bit 5

1 = Interrupt pending

Bit 6

0

1= Vertical sync active

0 = Y Stepping

Bit 7

= Increase 1 = Decrease the address counter
1 = Enable load address

Bits 8-13

Serialized Color Video
Bit 8

Red (Rl)

Bit 9

Red intense (R2)

Bit 10

Green (Gl)

Bit 11

Green intense (G2)

Bit 12

Blue (Bl)

Bit 13

Blue intense (B2)

Bits 14-15 Reserved

Video Look-up Table Register X'0158' Write Only
The video look-up table is selected via the I/O channel address. The data written, specified on the
I/O channel most significant byte (bits 0 through 5), is written to the address specified on the I/O
channel least significant byte (bits 0 through 3). To avoid scintillation of the screen, this operation
should only be performed during vertical blanking.

10

Advanced Color Graphics Display Adapter

The mapping of the most significant byte, bits 0-5 to output colors, is as follows:

Pel
Low
Med
High
Low
Med
High
Low
Med
High

Color
Intense red
Intense red
Intense red
Intense green
Intense green
Intense green
Intense Blue
Intense blue
Intense blue

Most Significant Byte
0 1 2 3 4 5
1 0 0 0 0 0
0 1 0 0 0 0
1 1 0 0 0 0
0 0 1 0 0 0
0 0 0 1 0 0
0 0 1 1 0 0
0 0 0 0 1 0
0 0 0 0 0 1
0 0 0 0 1 1

Other combinations of the three basic colors described above produce alternate hues.

Block Transfer Reload (X'0152') Read Only
Reading from this I/O location loads the address of the next memory access into the on-card
address pointer register. No significant data is returned when this location is read. See "Data
Control Register (X'0150') Write Only" on page 7 for more information regarding the use of this
I/O command.

Interrupts
The adapter generates a level 11 interrupt at the start of vertical sync if bit 13 (interrupt enable) of
the control register is a 1. This interrupt will not occur if bit 13 is a O. When the adapter generates
an interrupt, bit 5 of the RAS status register is set to 1. To clear bit 5 and reenable level 11
interrupts, an output to hex 6F3 with any data value must be issued. Interrupt ·11 is a shared
interrupt.

Advanced Color Graphics Display Adapter

11

Connector Specifications
The adapter has a 16-pin connector at the rear of the adapter. The following figure shows the
signals and their pin assignments.

Advanced
Color
Graphics Display

1

Signal ground for vertical sync

2

Vertical sync

3

R1 signal ground

4

Low order red bit (R 1 )

5

R2 signal ground

6

High order red bit (R2)

7

G1 signal ground

8

Low order green bit (G1)

9

G2 signal ground

Advanced
Color
Graphics Displ ay
Adapter

10

High order green bit (G2)

11

B 1 signal ground

12

Low order blue bit (B 1 )

13

B2 skmal ~Hound

14

High order blue bit (B2)

15

Signal ground for horizontal sync

16

Horizontal sync

L,

1

3

5

7

9

11

13

2

4

6

8

10

12

14

15
16

.I

MATING FACE OF ADAPTER CONNECTOR

Figure 3.

12

Advanced Color Graphics Display Adapter Connector Specifications

Advanced Color Graphics Display Adapter

---- --- ------------_.-

Advanced Monochrome
Graphics Display
Adapter

Personal Computer
Hardware Reference
Library

ii

Advanced Monochrome Graphics Display Adapter

Contents

Description ............................................................
Operation ...................................................................
Bit Map Memory Operations ....................................................
110 Operations ...............................................................
Specifications ...............................................................
Logic Diagrams ..............................................................

Contents

1
3
5
6
10
12

iii

iv

Advanced Monochrome Graphics Display Adapter

Description

The Advanced Monochrome Graphics Display Adapter attaches to the 110 channel and drives a
12-inch monochrome display at a 46 Hz (frame rate) or 92 Hz (field rate) interlace refresh rate.
The adapter provides a 64K-byte bit map that is translated to the screen as 720 pels horizontally by
512 pels vertically, one bit per pel.
The adapter includes a number of hardware performance assists, including a write mask to protect
bit fields within a byte, a barrel shifter to rotate bits within a byte, and a logic unit to combine
source bytes before they are written into the bit map.
Figure 1 on page 2 is a block diagram of the Advanced Monochrome Graphics Display Adapter.

Advanced Monochrome Graphics Display Adapter

1

DECODE

CLOCKS

I----~

DECODES

~ SYNCS

SYS
ADDRESS - - - - 24 BUS

..........-..t

64KX8
ADR

DO I - - - - r -...

MEMORY
01

LOGIC
UNIT

CONTROL

STATUS

SYS
DATA
BUS

Figure 1.

2

Advanced Monochrome Graphics Display Adapter Functional Block Diagram

Advanced Monochrome Graphics Display Adapter

ViDEO ....

Operation
Data to be displayed is written into the 64K x 8 byte bit map memory by the system. This data is
then scanned out of the memory and sent as a serial video stream to the monitor.
The system processor can manipulate data residing in the bit map memory in several ways. The
choice of a particular method is controlled by the type of instruction (Load or Store) and the
current value of a 2-bit mode field which resides within a 16-bit control register. The contents of
the control register must be initialized prior to the memory operation.
Hardware on the card allows data in the bit map to be manipulated without passing through a
processor. This hardware includes:
A 16-bit write mask that enables write operations to individual bits
A shifter that realigns bits before they are written to memory
Data registers to hold data being processed
Two 8-bit data mask registers that select bits being merged from data registers
A logic unit that does all the actual merging.
Using this hardware, source data from either the system or from the bit map may replace or be
merged with data in the bit map. Images on the screen (in the bit map) can thus be moved,
inverted, overlaid, or replaced.
The adapter occupies two address ranges on the I/O channel. Sixteen bytes of I/O address space at
X '0160' through '016F' are used to load the data mask register, and the control registers. See the
section entitled "I/O Operations" on page 6 for specific register addresses and bit assignments.
The second address range occupied by the adapter is the bit map memory that consists of
128K-bytes starting at hex address 'DOOOOO' in memory space on the I/O channel. When
addressing the bit map memory, the low order address bit must be o. Address bits A01 through
A16 are used to access memory. Address bit AOO is not used during memory accesses. This
restriction arises because the adapter allows word accesses to the bit map to begin on either even or
odd byte boundaries. Because the system restricts half-word accesses to even bytes, address lines to
the bit map memory are offset by one bit.
The most significant data byte of the I/O channel is written into or read from the bit map memory
location specified by the shifted address lines. The least significant data byte is written into or read
from the memory location specified by the shifted address lines increased or decreased by one in the
X or Y direction. The increase and decrease bits of the control register determine whether the
address is increased or decreased. The X and Y bits of the control register determine whether the X
or Y direction is changed.
As a result of the addressing scheme described above, each physical memory location in the bit map
can be accessed at either of two addresses: either directly, through the most significant byte, or after
the address bus has been increased or decreased, through the least significant byte.

Advanced Monochrome Graphics Display Adapter

3

I

0000
0080

0001
0081

0002
0082

0003 - 0058
0083 - 0008

0059
0009

005A
OODA

005B - 007E
OODB - OOFE

007F
OOFF

FF80

FF81

FF82

FF83 - FFD8

FFD9

FFDA

FFDB - FFFE

FFFF

512
Sean
Lines

L

90 Bytes Visible Memory

... I~

38 Bytes Hidden Memory

128 Bytes Total Bit Map Memory Width

Figure 2.

Bit Map Memory Addresses

The mapping between the physical addresses shown in Figure 2 and denoted as 'P' in the equations
and the I/O channel address denoted as 'C' in the equations shown as follows for each of the
increase and decrease bits and the X and Y status bits.
Word Storage Location
I/O Channel Inc/Dec X/V
Physical to
I/O Channel to Physical
Byte
I/O Channel to Physical
MS Byte
LS Byte
LS Byte
LS Byte
LS Byte

either

+

either
X
X

+

Y

C=2P
C=2P-2
C=2P+2
C=2P-256

y

C=2P+256

=>
=>
=>
=>
=>

P=C/2
P=C/2 +1
P=C/2 -1
P=C/2
+128
P=C/2 -128

Figure 2 shows how on-card physical memory byte addresses are mapped to the display screen.
The bits in each byte are shifted onto the screen with the most significant bit to the left.

4 Advanced Monochrome Graphics Display Adapter

Bit Map Memory Operations
The possible memory operations and respective mode bit definitions are as follows:

System Write Operation (Mode = 00)
This operation writes 16 bits of external data to the bit map memory at the address specified in the
system processor 'Store' instruction.

Overlay Write Operation (Mode

= 01)

This operation writes 16 bits of external data to the on-card write mask registers (WM1 and WM2).
It also initiates a write operation of the on-card system data latches to the bit map memory at the
address specified in the system processor 'Store' instruction. The new value in the write mask is
used to control the write to the bit map. This operation will not affect the contents of the system
data latches. Preloading the system data latches with the proper constant makes it possible to
'AND' or 'OR' system data with the bit map memory in one memory operation.

Adapter Write Operation (Mode

= 10)

This operation writes data from the on-card data latches (D 1,D2,D3) to the bit map memory
making use of the rotate count, write mask, data mask, data bus and the logic unit. The following
operations must be completed prior to executing this operation:
Load the data latches using an adapter read operation.
•

Load the write mask using an overlay write operation.
Load the operation mode, rotate count and logic function using an 110 'Store' to the adapter
control register.

System Read Operation (Mode

= XX)

This operation reads 16 bits of data from the bit map memory and places it on the system data bus.
On-card data latches D 1, D2 and D3 are updated by this operation. Data is loaded into latches D 1,
D2 and D3 regardless of the setting of the mode. However, valid data is returned to the system
processor only if the mode is '00'.

Advanced Monochrome Graphics Display Adapter

5

Automatic Read/Write Operation (Mode

= 11)

In this mode of operation, data is alternately read into D 1, D2 and D3 and then written to memory
with successive write operations from the microprocessor. Data read from memory is not gated
onto any busses external to the data path, but is used only to update Dl, D2 and D3. This allows
the relatively fast 'Store' operation to be used for block transfer operations with no 'Loads'
required.
To get the alternate read/write operations into phase with the source and destination addresses, the
system processor should do a 'Load' operation from the first source address. Subsequent 'Stores'
will automatically alternate between read and writes to the bit map.

110 Operations
In order to manipulate the various registers on the adapter, a set of I/O operations are required.

Data Mask Register (X'0162')
Typically these two 8-bit registers (DMI and DM2) are initialized with data representing the
inverse of each other, and are used to mask the bits on or off for logical combination through the
logic unit.
An 8 bit for DMI Mask (Data Bus MS Byte, bits 0-7)
An 8 bit for DM2 Mask (Data Bus LS Byte, bits 0-7).

Data Control Register (X'0160') Write Only
Bits 0 through 11 should not be changed for at least 1.4 microseconds after a memory operation
since the memory operation may still be in progress.
Bits 0-2

Rotate Count
The rotate count determines the number of bits that the data read from the bit
map is shifted to the left prior to being written back into the bit map. This
value has no effect during system write or overlay write modes. It has effect
only during adapter write or automatic write modes.

6

Advanced Monochrome Graphics Display Adapter

Bits 3-5

Logic Unit Function Control
Bit
543
000 010 100 101 110 111 -

Pass through
Pass through
Pass through
A 'OR' B
Pass through
A 'NOR' B

B
A
'Not' B
'Not' A

Logic unit function control bits (bits 3-5) determine how data previously read
from the bit map or written from the system are merged before being written
into the bit map. When set to '101'B, the bit fields masked off by the data
mask register are merged with system data before being written back into the
bit map memory. This is the function normally needed during adapter write
and automatic write modes. When set to '01 O'B, the bit field masked off by
data mask register 1 (DMl) is written into the bit map memory. This is the
function normally needed in system write and overlay write modes. When set
to 'OOO'B, the bit field masked off by data mask register 2 (DM2) is written
into the bit map memory. This function can be used in adapter write and
automatic write modes when no bit shift is used. In each case, an inverting
form of the operation exists to allow data to be inverted as it is written to the
bit map. See "Bit Map Memory Operations" on page 5 for further
explanations.
Bits 6-7

Reserved

Bits 8-9

Memory Mode
Bit
98
00 = System write operation
01 = Overlay write operation
10 = Adapter write operation
11 = Automatic read/write operation

Bit 10

Address Counter Mode

o = Increase the address counter
1
Bit 11

= Decrease the address counter

Address Counter Stepping

o=

Y stepping
1 = X stepping

Advanced Monochrome Graphics Display Adapter

7

Bits 10 and 11 control whether the LSB of a bit map memory operation is accessed
from the left, right, above or below the MSB. See "Bit Map Memory Operations"
on page 5 for further explanation.
Bit 12

Block transfer
Bit 12 controls block transfer mode. When this bit is set from a 0 to ai, the
address of the next memory location accessed is stored in a pointer register on
the card. This address is adjusted to point at the next memory location at the
end of each memory cycle. That is, the X or Y address is increased or
decreased. After the first block transfer memory cycle has loaded the on-card
pointer register, the memory address supplied on the data bus is ignored, and
the pointer is used to access memory. To reload the pointer register, either
clear and set the block transfer bit again or read from the block transfer reload
I/O address, X'OI62'.

Bit 13

Interrupt enable
If bit 13 is 1, an interrupt is generated at the start of vertical sync. If this bit is
0, the interrupt is not generated. See "Interrupts" on page 9.

Bit 14

Sync enable (always 1)

Bit 15

Video enable

o=
1

Disables video to monitor

= Enables video to monitor

RAS Status Register (X'0160') Read Only

8

Bit 0

1 = Even

0 = Odd field

Bit 1

Horizontal sync toggle latch

Bit 2

o = Vertical sync inactive

Bit 3

Serialized Video

Bit 4

1= X

Bit 5

1 = Interrupt pending

Bit 6

0

Bit 7

1 = Enable load address

1 = Vertical sync active

0 = Y Stepping

= Increase

1

= Decrease the address counter

Advanced Monochrome Graphics Display Adapter

Block Transfer Reload (X'0162') Read Only
Reading from this I/O location loads the address of the next memory access into the on-card
address pointer register. No meaningful data is returned when this location is read. See "Data
Control Register (X'OI60') Write Only" on page 6 for more information regarding the use of this
I/O command.

Interrupts
The adapter generates a level 11 interrupt at the start of vertical sync if bit 13 (interrupt enable) of
the control register is a 1. This interrupt will not occur if bit 13 is a O. When the adapter generates
an interrupt, bit 5 of the RAS status register is set to 1. To clear bit 5 and reenable level 11
interrupts, an output to hex 6F3 with any data value must be issued.

Advanced Monochrome Graphics Display Adapter

9

Specifications
The adapter has a 16-pin connector at the rear of the adapter. The following figure shows the
signals and their pin assignments.

10

Advanced Monochrome Graphics Display Adapter

GNO

1

Vertical Sync

2

GNO

3

Reserved

4

-....

GNO

5

....

--

Reserved

6

....

GNO

7

-...
--

Video

8

GNO

S

~

---

~

..-

-..

Advanced
Monochrome
Graphics Display

--

--

Reserved

10

_ +Busy GNO

11

_ + PE Reserved

12

_ GNO

13

-...

Reserved

14

-

GNO

15

....

Horizontal Sync

16

-

-

Figure 3.

Advanced
Monochrom e
Graphics Oi splay
Adapter

Advanced Monochrome Graphics Display Adapter Interface Specifications

Advanced Monochrome Graphics Display Adapter

11

liD SLOT
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A2B
A29
A30
A31
CO2
C03
C04
C05
C07
C06
COB
B2B
B14
B13
C09
Cl0
All
B02
COl
A15
B20

(SHT 15) +SADDRI 5
(SHT 15) +SADDRI 4
(SHT 15) +SADDRI 3
(SHT 15) +SADDRI 2
(SHT 15) +SADDRI 1
(SHT 15) +SADDRI 0
(SHT 15) +SADDR 9
(SHT 15) +SADDR B
(SHT 16) +SADDR 7
(SHT 16) +SADDR 6
(SHT 16) +SADDR 5
(SHT 16) +SADDR 4
(SHT 16) +SADDR3
(SHT 16) +SADDR 2
(SHT 16) +SADDR 1
(SHT 16) +SADDRO
(SHT 2) +SADDR23
(SHT 2) +SADDR22
(SHT 2) +SAODR21
(SHT 2) +SADDR20
(SHT 2) +SADDRI8
(SHT 2) +SADDRI9
(SHT 2) +SADDRI7
(SHT 2) +SALE
(SHT 2) -SIOR
(SHT 3) -SlOW
(SHT 2) -SMEMR
(SHT 3) -SMEMW
(SHT 3) +SAEN
(SHT 8) +SRESET
(SHT 13) -SBHE
(SHT 13) +SADDRI6
(SHT 16) +SYSCLK

001
002
AID
A02
A03
A04
A05
A06
A07
AOB
A09
Cll
C12
C13
C14
C15
C16

(SHT 2)-MEMCSI6
(SHT 3)-I/OCSI6
(SHT 5) +1OCHRDY
(SHT 16) +SDATA7
(SHT 16) +SDATA6
(SHT 16) +SDATA5
(SHT 16) +SDATA4
(SHT 16) +SOATA3
(SHT 16) +SDATA2
(SHT 16) +SDATAI
(SHT 16) +SDATAO
(SHT 151 +SDATAB
(SHT 15) +SDATA9
(SHT 15) +SDATAlO
(SHT 15) +SoATAll
(SHT 151 +SDATAI2
(SHT 151 +SDATAI3
(SHT 151 +SDATAI4
(SHT 15) +SDATAI5
(SHT 16) +IROll

C17
CIB
004

+5

t---r-----t--.,.----o---- B03

16-PIN MOOU
CONNECTOR

t--+---f----1----+---B29
'---+---+--'---~~-DI6

lCl

13Cl

,

.. .

lC2

01

!'

JTn;~----(SHT 10) +VSOUT
r.7.<------(SHT 7, 15) +VIDEOOUT
'--_ _J"'~-----(SHT 10) +HSOUT

F

62C2
BOI
BID
831
01B

~

11

(SHT
(SHT
(SHT
(SHT

(SHT
(SHT
(SHT
(SHT

74lS244

1) +sAOOR3-----------------------:1~3i.-------lhQ~---------------------(SHT 13.16) +BAOOR3

1) +SAOOR2
1) +SAOORI
1) +SAOORO

15
7
(SHT 3.13.16) +BAOOR2
17
UQ3 5
(SHT 3.13.16) +BAOORI
1Q
3
(SHT 13. 16) +BAOORO
,---'-=< ' - - 2 74lS244
1) +SAODR7 - - - - - - - - - - - - - - - - - - - - - - t - - - - T l 4------"'-'-'1-21~8---------------------(SHT3. 13. 16) +BADDR7
1) +SAOOR6
6
16
(SHT 3.13.16) +BADDR6
1) +SADDR5
8
UQ3
14
(SHT 3.13.16) +8ADOR5
1) +SADDR4
1
12
(SHT 3.13.16) +BADOR4

t----'-< ' - 11~

(SHT 1) +SAOORll--------------------1--T.i13~
(SHT 1) +SAOOR10
15
(SHT 1) +SAODRQ
17
(SHT 1) +SADDR8
~

UQ4

I-'Q~---------------------(SHT 3.13.16) +BAOOR11
7
5
3

(SHT 3.13.16) +BAOORID
(SHT3. 13. 16) +BAODRQ
(SHT 3. 13. 16) +BAODRB

'---

(SHT
(SHT
(SHT
(SHT

2 74lS244
1) +SADDRI5------------------------lr-----i4--j-1-21~8_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - - - ( S H T 3.13) +BAOORI5
1) +SAOOR14
6
UQ4
16
(SHT 3.13) +BADDRI4
1) +SAODR13
8
14
(SHT 3.13) +BADORI3
1) +SAOORI2
1
12
(SHT 3. 13) +BAOORI2
~'-74lSD4

+5~o-J>,R.!IP.!l4,_"5~-41 U63 ~=-2_---~
(SHT 1) +SADDR23-----------,

r"HT 5. ,0'0'"

(SHT 1) +SADDR22--------,
(SHT 1) +SADDR20---------,

(SHT 1) +SADDR21

6]

2

_

UQQ

E)1FOO

~------~~+------~-~13'---~~~16--~11~32.17~

(SHT 1) +SAlE _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
i I
(SHT 5) -RDYRST -----------------jf--------~H--------t-------4

11

(mI5)~~~

(SHT 1) +SADDRI8---------------'--'--i

(SHT 1) + S A O D R 1 Q - - - - - - - - - - - - - - - - + - - ' 1

~1
~,»1:..:2_ _~~2

74S03
UQO

(SHT 1) -MEMCS16

(SHT 1) + S A D D R 1 7 - - - - - - - - - - - - - - - - + - - - - - - - - = - = j
(SHT 1) -SIOR---------~
(SHT 1) -SMEMR----------;;-t
(SHT 1) -SMEMW----------=-j

~~-------------------------------l~~~~i ~~M~5~:MEMR
f--!!~---------------------------------(SHT3)-DIOR

74ALS138

(SH~S~~+I~~~IO:~-----------------------------------..!J~

(SH~8~T+~~:~~~-----rt-------------------------.:======J![j

U78

5

~:~c-------(SHT 15) ·STATUSEN
t>7;11~-----(8HT 4) ·BLOCKRST
p-;:lO:-------(SHT 12, 16) +CNTLCLK3
I>-:-'g' - - - - - - - ( S H T 12) +MCLK
7

74FOO

r - - - - - - - - + - - - - - - - + - - - - - - - - - - - - ( S H T 16) +IORW/AEN

~-------+-------+------------(8HT 15) +IOR/AEN
74803
74LS04

p."------(SHT 1) ,l/oeSl6

(SHT 1) +SAEN---------'!..I U40
74FOO

(SHT 2) +800R15

(SHT 2) +BADDR5--------.l.I
(SHT 2) +BADDR8--------.!:..I
(SHT 2) +BADDR6--------"4...._--"

(SHT 2) + B A O O R I 4 - - - - - - - - - - - - - - - - - - - - l J
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l>-"------(SHT 15) ·IOOEC

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DATA PATH

25~2

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27
28
29
30
31
32
33
34
35
36
37
38
39
40

[SHT 61·ENSY2
[SHT 61 ·ENSYI
[SHT 141 +MDATA07
[SHT 141 +MDATA06
[SHT 141 +MDATA05
[SHT 141 +MDATA04
[SHT 141 +MDATA03
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[SHT 14) +MDATADO
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36
37
38
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[SHT 3) +MCLK
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3
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6
7
8
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18
19
20
21
22
23
24
41
42
43
44
45
46
47
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[SHT 16) +BDATA6
[SHT 15) +BDATA5
[SHT 16) +BDATA4
[SHT 15) +BDATA3
[SHT 15) +BDATA2
[SHT 15) +BDATA 1
[SHT 15) +BDATAO
[SHT 14) +MDATAID
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[SHT 14) +MDATA12
[SHT 141 +MDATA13
[SHT 14) +MDATA14

[SHT 14) +MDATA15
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[SHT 161 +BDATA12
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2600-12

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1
11
13
14
17
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18
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(SHT 61-ENWMI
(SHT 14. 151-WEO
(SHT 14. 151-WEI
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(SHT 14. 151-WE4
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(SHT 14. 151-WE6
(SHT 14. 151-WE7

28

Advanced Monochrome Graphics Display Adapter

--------------,-

-- -

Enhanced Graphics
Adapter

Personal Computer
Hardware Reference
Library

ii

Contents

Description .................................... 1
Major Components .......................... 3
Modes of Operation ......................... 5
Basic Operations ............................ 8
Registers ................................. 12
Programming Considerations ..................... 62
Programming the Registers ................... 62
RAM Loadable Character Generator ........... 69
Creating a 512 Character Set ................. 70
Creating an 80 by 43 Alphanumeric Mode ....... 71
Vertical Interrupt Feature .................... 72
Creating a Split Screen ...................... 73
Compatibility Issues ........................ 74
Interface ..................................... 76
Feature Connector ......................... 76
Specifications ................................. 79
System Board Switches ...................... 79
Configuration Switches ...................... 80
Direct Drive Connector ..................... 83
Light Pen Interface ......................... 84
Jumper Descriptions ........................ 85
Logic Diagrams ................................ 87
BIOS Listing ................................. 103
Vectors with Special Meanings ............... 103
Index ........................................ Index-l

iii

Notes:

iv

Description
The IBM Enhanced Graphics Adapter (EGA) is a graphics
controller that supports both color and monochrome direct drive
displays in a variety of modes. In addition to the direct drive port,
a light pen interface is provided. Advanced features on the
adapter include bit-mapped graphics in four planes and a RAM
(Random Access Memory) loadable character generator. Design
features in the hardware substantially reduce the software
overhead for many graphics functions.
The Enhanced Graphics Adapter provides Basic Input Output
System (BIOS) support for both alphanumeric (A/N) modes and
all-points-addressable (AP A) graphics modes, including all modes
supported by the Monochrome Display Adapter and the
Color/Graphics Monitor Adapter. Other modes provide APA
640x350 pel graphics support for the IBM Monochrome Display,
full 16 color support in both 320x200 pel and 640x200 pel
resolutions for the IBM Color Display, and both A/N and APA
support with resolution of 640x350 for the IBM Enhanced Color
Display. In alphanumeric modes, characters are formed from one
of two ROM (Read Only Memory) character generators on the
adapter. One character generator defines 7x9 characters in a
9x14 character box. For Enhanced Color Display support, the
9x 14 character set is modified to provide an 8x 14 character set.
The second character generator defines 7x7 characters in an 8x8
character box. These generators contain dot patterns for 256
different characters. The character sets are identical to those
provided by the IBM Monochrome Display Adapter and the IBM
Color / Graphics Monitor Adapter.
The adapter contains 64K bytes of storage configured as four
16K byte bit planes. Memory expansion options are available to
expand the adapter memory to 128K bytes or 256K bytes.
The adapter is packaged on a single 13-1/8 inch (333.50 mm)
card. The direct drive port is a right-angle mounted connector at
the rear of the adapter and extends through the rear panel of the
system unit. Also on the card are five large scale integration
(LSI) modules custom designed for this controller.

IBM Enhanced Graphics Adapter 1

Located on the adapter is a feature connector that provides access
to internal functions through a 32-pin berg connector. A separate
64-pin connector provides an interface for graphics memory
expansion.
The following is a block diagram of the Enhanced Graphics
Adapter:
CPU
Addr.
CPU
Data

..
r

J

rl

~

'"

....

CRTC
LSI

MUX

~

.... GRAPH .:....

4~

v

.

~~

r

LSI

..

4

r---

SEQ
LSI

r

'"

.
.

......

'--

... ,n,
.

-4

1~

.

BIT 0 I-MAP ~

~

......

0-- ~

GRAPH
... LSI

H. ..

~
r

3~.
BIT 2 MAP ~.

~,

I--

.... ATTRIB
... LSI
r

Enhanced Graphics Adapter Block Diagram

2 IBM Enhanced Graphics Adapter

01 RECT
DRIVE
OUTPUT

Major Components
CRT Controller
The CRT (Cathode Ray Tube) Controller (CRTC) generates
horizontal and vertical synchronous timings, addressing for the
regenerative buffer, cursor and underline timings, and refresh
addressing for the dynamic RAMs.

Sequencer
The Sequencer generates basic memory timings for the dynamic
RAMs and the character clock for controlling regenerative
memory fetches. It allows the processor to access memory during
active display intervals by inserting dedicated processor memory
cycles periodically between the display memory cycles. Map
mask registers are available to protect entire memory maps from
being changed.

Graphics Controller
The Graphics Controller directs the data from the memory to the
attribute controller and the processor. In graphics modes,
memory data is sent in serialized form to the attribute chip. In
alpha modes the memory data is sent in parallel form, bypassing
the graphics controller. The graphics controller formats the data
for compatible modes and provides color comparators for use in
color painting modes. Other hardware facilities allow the
processor to write 32 bits in a single memory cycle, (8 bits per
plane) for quick color presetting of the display areas, and
additional logic allows the processor to write data to the display
on non-byte boundaries.

Attribute Controller
The Attribute Controller provides a color palette of 16 colors,
each of which may be specified separately. Six color outputs are

IBM Enhanced Graphics Adapter 3

available for driving a display. Blinking and underlining are
controlled by this chip. This chip takes data from the display
memory and formats it for display on the CRT screen.

Display Buffer
The display buffer on the adapter consists of 64K bytes of
dynamic read/write memory configured as four 16K byte video
bit planes. Two options are available for expanding the graphics
memory. The Graphics Memory Expansion Card plugs into the
memory expansion connector on the adapter, and adds one bank
of 16K to each of the four bit planes, increasing the graphics
memory to 128K bytes. The expansion card also provides DIP
sockets for further memory expansion. Populating the DIP
sockets with the Graphics Memory Module Kit adds two
additional 16K banks to each bit plane, bringing the graphics
memory to its maximum of 256K bytes.
The address of the display buffer can be changed to remain
compatible with other video cards and application software. Four
locations are provided. The buffer can be configured at segment
address hex AOOOO for a length of 128K bytes, at hex AOOOO for
a length of 64K bytes, at hex BOOOO for a length of 32K bytes, or
at hex B8000 for a length of 32K bytes.

BIOS
A read-only memory (ROM) Basic Input Output System (BIOS)
module on the adapter is linked to the system BIOS. This ROM
BIOS contains character generators and control code and is
mapped into the processor address at hex COOOO for a length of
16K bytes.

Support Logic
The logic on the card surrounding the LSI modules supports the
modules and creates latch buses for the CRT controller, the

4 IBM Enhanced Graphics Adapter

processor, and character generator. Two clock sources (14 MHz
and 16 MHz) provide the dot rate. The clock is multiplexed
under processor I/O control. Four I/O registers also resident on
the card are not part of the LSI devices.

Modes of Operation
IBM Color Display
The following table describes the modes supported by BIOS on
the IBM Color Display:
BUFFER BOX MAX.
ALPHA
MODE # TYPE COLORS FORMAT START SIZE PAGES RESOLUTION

88000

8x8

8

320x200

40x25

88000

8x8

8

320x200

80x25

88000

8x8

8

640x200

80x25

88000

8x8

8

640x200

40x25

88000

8x8

1

320x200

40x25

88000

8x8

1

320x200

APA 2

80x25

88000

8x8

1

640x200

D

APA 16

40x25

A8000

8x8

2/4/8

320x200

E

APA 16

80x25

A8000

8x8

1/2/4

640x200

0

A/N

1

A/N

16
16

2

A/N

16

3

A/N

16

4

APA 4

5

APA 4

6

40x25

Modes 0 through 6 emulate the support provided by the IBM
Color/Graphics monitor Adapter.
Modes 0,2 and 5 are identical to modes 1,3 and 4 respectively at
the adapter's direct drive interface.
The Maximum Pages fields for modes D and E indicate the
number of pages supported when 64K, 128K or 256K bytes of
graphics memory is installed, respectively.

IBM Enhanced Graphics Adapter 5

IBM Monochrome Display
The following table describes the modes supported by BIOS on
the IBM Monochrome Display.
ALPHA BUFFER BOX MAX.
MODE# TYPE COLORS FORMAT START SIZE PAGES RESOLUTION
7

A/N

4

80x25

BOOOO

9x14 8

720x350

F

APA

4

80x25

AOOOO

8x14 1/2

640x350

Mode 7 emulates the support provided by the IBM Monochrome
Display Adapter.

IBM Enhanced Color Display
The Enhanced Graphics Adapter supports attachment of the IBM
Enhanced Color Display. The IBM Enhanced Color Display is
capable of running at the standard television frequency of 15.75
KHz as well as running 21.85 KHz. The table below summarizes
the characteristics of the IBM Enhanced Color Display:
Parameter
Horiz Scan Rate
Vertical Scan Rate
Video Bandwidth
Displayable Colors
Character Size
Character Box Size
Maximum Resolution
Alphanumeric Modes
Graphics Modes

TV Frequency
15.75 KHz.
60 Hz.
14.318 MHz.
16 Maximum
7 by7 Pels
8 by8 Pels
640x200 Pels
0,1,2,3
4,5,6,D,E

High Resolution
21.85 KHz.
60 Hz.
16.257 MHz.
16 or 64
7 by 9 Pels
8 by 14 Pels
640 by 350 Pels
0,1,2,3
10

In the television frequency mode, the IBM Enhanced Color
Display displays information identical in color and resolution to
the IBM Color Display.
In the high resolution mode, the adapter provides enhanced
alphanumeric character support. This enhanced alphanumeric
support consists of transforming the 8 by 8 character box into an
8 by 14 character box, and providing 16 colors out of a palette of

6 IBM Enhanced Graphics Adapter

64 possible display colors. Display colors are changed by altering
the programming of the color palette registers in the Attribute
Controller. In alphanumeric modes, any 16 of 64 colors are
displayable. the screen resolution is 320x350 for modes 0 and 1,
and 640x350 for modes 2 and 3.
The resolution displayed on the IBM Enhanced Color Display is
selected by the switch settings on the Enhanced Graphics
Adapter.
The Enhanced Color Display is compatible with all modes listed
for the IBM Color Display. the following table describes
additional modes supported by BIOS for the IBM Enhanced
Color Display:

MODE

#

ALPHA BUFFER BOX MAX.
TYPE COLORS FORMAT START SIZE PAGES RESOLUTION

0*

A/N

16/64

40x25

88000

8x14 8

320x350

1*

A/N

16/64

40x25

88000

8x14 8

320x350

2*

A/N

16/64

80x25

88000

8x14 8

640x350

88000

8x14 8

640x350

A8000

8x14 1/2

640x350

3*

A/N

16/64

80x25

10*

APA

4/16
16/64

80x25

* Note that modes 0, 1, 2, and 3, are also listed for IBM Color
Display support. BIOS provides enhanced support for these
modes when an Enhanced Color Display is attached.
The values in the "COLORS" field indicate 16 colors of a 64
color palette or 4 colors of a sixteen color palette.
In mode 10, The dual values for the "COLORS" field and the
"MAX. PAGES" field indicate the support provided when 64K
or when greater than 64K of graphics memory is installed,
respectively.

IBM Enhanced Graphics Adapter 7

Basic Operations
Alphanumeric Modes
The data format for alphanumeric modes on the Enhanced
Graphics Adapter is the same as the data format on the IBM
Color / Graphics Monitor Adapter and the IBM Monochrome
Display Adapter. As an added function, bit three of the attribute
byte may be redefined by the Character Map Select register to act
as a switch between character sets. This gives the programmer
access to 512 characters at one time. This function is valid only
when memory has been expanded to 128K bytes or more.
When an alphanumeric mode is selected, the BIOS transfers
character patterns from the ROM to bit plane 2. The processor
stores the character data in bit plane 0, and the attribute data in
bit plane 1. The programmer can view bit planes 0 and 1 as a
single buffer in alphanumeric modes. The CRTC generates
sequential addresses, and fetches one character code byte and one
attribute byte at a time. The character code and row scan count
address bit plane 2, which contains the character generators. The
appropriate dot patterns are then sent to the palette in the
attribute chip, where color is assigned according to the attribute
data.

Graphics Modes
320x200 Two and Four Color Graphics (Modes 4 and 5)
Addressing, mapping and data format are the same as the
320x200 pel mode of the Color/Graphics Monitor Adapter. The
display buffer is configured at hex B8000. Bit image data is
stored in bit planes 0 and 1.

640x200 Two Color Graphics (Mode 6)
Addressing, mapping and data format are the same as the
640x200 pel black and white mode of the Color/Graphics

8 IBM Enhanced Graphics Adapter

Monitor Adapter. The display buffer is configured at hex B8000.·
Bit image data is stored in bit plane O.

640x350 Monochrome Graphics (Mode F )
This mode supports graphics on the IBM Monochrome Display
with the following attributes: black, video, blinking video, and
intensified video. Resolution of 640x350 requires 56K bytes to
support four attributes. By chaining maps 0 and 1, then maps 2
and 3 together, two 32K bit planes can be formed. This chaining
is done only when necessary (less than 128K of graphics
memory). The first map is the video bit plane, and the second
map is the intensity bit plane. Both planes reside at hex address
AOOOO.
Two bits, one from each bit plane, define one picture element
(pel) on the screen. The bit definitions for the pels are given in
the following table. The video bit plane is denoted by CO and the
Intensity Bit Plane is denoted by C2.

C2

co

Pixel Color

0
0
1
1

0
1
0
1

Black
Video
Blinking Video
Intensified Video

Valid Attributes

0
3
C
F

The byte organization in memory is sequential. The first eight
pels on the screen are defined by the contents of memory in
location AOOO:OH, the second eight pels by location AOOO: IH,
and so on. The first pel within anyone byte is defined by bit 7 in
the byte. The last pel within the byte is defined by bit 0 in the
byte.
Monochrome graphics works in odd/even mode, which means
that even CPU addresses go into even bit planes and odd CPU
addresses go into odd bit planes. Since both bit planes reside at
address AOOOO, the user must select which plane or planes he
desires to update. This is accomplished by the map mask register
of the sequencer. (See the table above for valid attributes).

IBM Enhanced Graphics Adapter 9

16/64 Color Graphics Modes (Mode 10)
These modes support graphics in 16 colors on either a medium or
high resolution monitor. The memory in these modes consists of
using all four bit planes. Each bit plane represents a color as
shown below. The bit planes are denoted as CO,C1,C2 and C3
respectively.

co =

Blue Pels
C 1 = Green Pels
C2 = Red Pels
C3 = Intensified Pels

F our bits (one from each plane) define one pelon the screen.
The color combinations are illustrated in the following table:
I

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

R

0
0
0
0
1
1
1
1

0
0
0
0
1
1

1
1

G
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

B
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Color
Black
Blue
Green
Cyan
Red
Magenta
Brown
White
Dark Gray
Light Blue
Light Green
Light Cyan
Light Red
Light Magenta
Yellow
Intensified White

The display buffer resides at address AOOOO. The map mask
register of the sequencer is used to select any or all of the bit
planes to be updated when a memory write to the display buffer is
executed by the CPU.

Color Mapping
The Enhanced Graphics Adapter supports 640x350 Graphics for
both the IBM Monochrome and the IBM Enhanced Color

10 IBM Enhanced Graphics Adapter

Displays. Four color capability is supported on the EGA without
the Graphics Memory Expansion Card (base 64 KB), and sixteen
colors are supported when the Graphics Memory Expansion Card
is installed on the adapter (128 KB or above). This section
describes the differences in the colors displayed depending upon
the graphics memory available. Note that colors OH, IH, 4H, and
7H map directly regardless of the graphics memory available.
Character
Attribute

Monochrome

Mode 10H

Mode 10H

64KB

>64KB

OOH*

Black

Black

Black

01H*

Video

Blue

Blue

02H

Black

Black

Green

03H

Video

Blue

Cyan

04H*

Blinking

Red

Red

OSH

Intensified

White

Magenta

06H

Blinking

Red

Brown

07H*

Intensified

White

White

08H

Black

Black

Dark Gray

09H

Video

Blue

Light Blue

OAH

Black

Black

Light Green

OBH

Video

Blue

Light Cyan

OCH

Blinking

Red

Light Red

ODH

Intensified

White

Light Magenta

OEH

Blinking

Red

Yellow

OFH

Intensified

White

Intensified White

* Graphics character attributes which map directly regardless of
the graphics memory available.

IBM Enhanced Graphics Adapter 11

Registers
External Registers
This section contains descriptions of the registers of the Enhanced
Graphics Adapter that are not contained in an LSI device.

Name

Port

Miscellaneous Output Register
Feature Control Register
I nput Status Register 0
Input Status Register 1

3C2
3?A
3C2
3?2

? = B in Monochrome Modes

Index

-

-

? = Din Color Modes

Miscellaneous Output Register
This is a write-only register. The processor output port address is
hex 3C2. A hardware reset causes all bits to reset to zero.

Miscellaneous Output Register Format
Bit

7

6

5

4

3

2

1

0
I/O Address Select
Enable Ram
Clock Select 0

' - - - - - - - - - J..~

Clock Select 1
Disable Internal Video Drivers
Page Bit For Odd/Even
Horizontal Retrace Polarity

& . . . . - - -_ _ _ _ _ _ _~

Bit 0

Vertical Retrace Polarity

3BX/3DX CRTC I/O Address-This bit maps
the CRTC I/O addresses for IBM Monochrome
or Color/Graphics Monitor Adapter emulation.
A logical 0 sets CRTC addresses to 3BX and
Input Status Register 1 's address to 3BA for
Monochrome emulation. A logical 1 sets CRTC

12 IBM Enhanced Graphics Adapter

addresses to 3DX and Input Status Register l's
address to 3DA for Color/Graphics Monitor
Adapter emulation.
Bit 1

Enable RAM-A logical 0 disables RAM from
the processor; a logical 1 enables RAM to
respond at addresses designated by the Control
Data Select value programmed into the Graphics
Controllers.

Bit 2-Bit 3

Clock Select-These two bits select the clock
source according to the following table:
Bits
3 2

o 0-

Selects 14 MHz clock from the processor
I/O channel
o 1- Selects 16 MHz clock on-board oscillator
1 0- Selects external clock source from the
feature connector.
1 1- Not used
Bit 4

Disable Internal Video Drivers-A logical 0
activates internal video drivers; a logical 1
disables internal video drivers. When the internal
video drivers are disabled, the source of the direct
drive color output becomes the feature connector
direct drive outputs.

Bit 5

Page Bit For Odd/Even-Selects between two
64K pages of memory when in the Odd/Even
modes (0,1,2,3,7). A logical 0 selects the low
page of memory; a logical 1 selects the high page
of memory.

Bit 6

Horizontal Retrace Polarity-A logical 0 selects
positive horizontal retrace; a logical 1 selects
negative horizontal retrace.

Bit 7

Vertical Retrace Polarity-A logical 0 selects
positive vertical retrace; a logical 1 selects

IBM Enhanced Graphics Adapter 13

negative vertical retrace. The IBM Monochrome
display requires a negative vertical retrace
polarity.

Feature Control Register
This is a write-only register. The processor output register is hex
3BAor3DA.

Feature Control Register Format
Bit

7

6

5

4

3

2

1

0
Feature Control Bit 0
Feature Control Bit 1
Reserved
Not Used

Bits 0 and 1

Feature Control Bits-These bits are used to
convey information to the feature connector.
The output of these bits goes to the FEAT 0 (pin
19) and FEAT 1 (pin 17) of the feature
connector.

Input Status Register Zero
This is a read-only register. The processor input port address is
hex 3C2.

14 IBM Enhanced Graphics Adapter

Input Status Register Zero Format
Bit

7

6

5

4

I

3

2

1

0

I I I I

I

:

Not Used
Switch Sense
Reserved
Reserved
CRT Interrupt

Bit 4

Switch Sense-When set to 1, this bit allows the
processor to read the four configuration switches
on the board. The setting of the CLKSEL field
determines which switch is being read. The
switch configuration can be determined by
reading byte 40:88H in RAM.
Bit 3:
Bit 2:
Bit 1:
Bit 0:

Switch 4
Switch 3
Switch 2
Switch 1

; Logical 0
; Logical 0
; Logical 0
; Logical 0

= switch closed
= switch closed

= switch closed
= switch closed

Bits 5 and 6

Feature Code-These bits are input from the
Feat (0) and Feat (1) pins on the feature
connector.

Bit 7

CRT Interrupt-A logical 1 indicates video is
being displayed on the CRT screen; a logical 0
indicates that vertical retrace is occurring.

Input Status Register One
This is a read-only register. The processor port address is hex
3BA or hex 3DA.

IBM Enhanced Graphics Adapter 15

Input Status Register One Format
B~

7

6

5

4

3

2

1

0
Disptay Enable
Light Pen Strobe
Light Pen Switch

'--------i"'~

Vertical Retrace
Diagnostic 1

'--...Ii..-_ _ _ _ _ _ _-I.~

Diagnostic 0
Not Used

Bit 0

Display Enable-Logical 0 indicates the CRT
raster is in a horizontal or vertical retrace
interval. This bit is the real time status of the
display enable signal. Some programs use this
status bit to restrict screen updates to inactive
display intervals. The Enhanced Graphics
Adapter does not require the CPU to update the
screen buffer during inactive display intervals to
avoid glitches in the display image.

Bit 1

Light Pen Strobe-A logical 0 indicates that the
light pen trigger has not been set; a logical 1
indicates that the light pen trigger has been set.

Bit 2

Light Pen Switch-A logical 0 indicates that the
light pen switch is closed; a logical 1 indicates
that the light pen switch is open.

Bit 3

Vertical Retrace-A logical 0 indicates that video
information is being displayed on the CRT
screen; a logical 1 indicates the CRT is in a
vertical retrace interval. This bit can be
programmed to interrupt the processor on
interrupt level 2 at the start of the vertical
retrace. This is done through bits 4 and 5 of the
Vertical Retrace End Register of the CRTC.

Bits 4 and 5

Diagnostic Usage-These bits are selectively
connected to two of the six color outputs of the

16 IBM. Enhanced GraphiCS' Adapter

Attribute Controller. The Color Plane Enable
register controls the multiplexer for the video
wiring. The following table illustrates the
combinations available and the color output
wiring.

Color Plane
Register
BitS Bit4

0
0
1
1

0
1
0
1

Input Status
Register One
BitS

Bit4

Red
Secondary Blue
Secondary Red
Not Used

Blue
Green
Secondary Green
Not Used

IBM Enhanced Graphics Adapter 17

Sequencer Registers
Index
00
01
02
03
04

Port

Name

3C4
3C5
3C5
3C5
3C5
3C5

Address
Reset
Clocking Mode
Map Mask
Character Map Select
Memory Mode

Sequencer Address Register
The Address Register is a pointer register located at address hex
3C4. This register is loaded with a binary value that points to the
sequencer data register where data is to be written. This value is
referred to as "Index" in the table above.
Sequencer Address Register Format
Bit

7

6

5

Bit O-Bit 3

4

3

2

1

0

Sequencer Address Bits-A binary value pointing
to the register where data is to be written.

Reset Register
This is a write-only register pointed to when the value in the
address register is hex 00. The output port address for this
register is hex 3C5.

18 IBM Enhanced Graphics Adapter

Reset Register Format
Bit

7

6

5

4

3

2

1

0

IIIIIII~

Asynchronous Reset
Synchronous Res·et
Not Used

Bit 0

Asynchronous Reset-A logical 0 commands the
sequencer to asynchronous clear and halt. All
outputs are placed in the high impedance state
when this bit is a O. A logical 1 commands the
sequencer to run unless bit 1 is set to zero.
Resetting the sequencer with this bit can cause
data loss in the dynamic RAMs.

Bit 1

Synchronous Reset-A logical 0 commands the
sequencer to synchronous clear and halt. Bits 1
and 0 must both be ones to allow the sequencer
to operate. Reset the sequencer with this bit
before changing the Clocking Mode Register, if
memory contents are to be preserved.

Clocking Mode Register
This is a write-only register pointed to when the value in the
address register is hex 01. The output port address for this
register is hex 3C5.
Clocking Mode Register Format
Bit

7

6

5

4

3

2

1

0
8/9 Dot Clocks
Bandwidth
Shift Load
Dot Clock
Not Used

IBM Enhanced Graphics Adapter 19

Bit 0

8/9 Dot Clocks-A logical 0 directs the
sequencer to generate character clocks 9 dots
wide; a logical 1 directs the sequencer to generate
character clocks 8 dots wide. Monochrome
alphanumeric mode (07H) is the only mode that
uses character clocks 9 dots wide. All other
modes must use 8 dots per character clock.

Bit 1

Bandwidth-A logical 0 makes CRT memory
cycles occur on 4 out of 5 available memory
cycles; a logical 1 makes CRT memory cycles
occur on 2 out of 5 available memory cycles.
Medium resolution modes require less data to be
fetched from the display buffer during the
horizontal scan time. This allows the CPU
greater access time to the display buffer. All high
resolution modes must provide the CRTC with 4
out of 5 memory cycles in order to refresh the
display image.

Bit 2

Shift Load-When set to 0, the video serializers
are reloaded every character clock; when set to 1,
the video serializers are loaded every other
character clock. This mode is useful when 16 bits
are fetched per cycle and chained together in the
shift registers.

Bit 3

Dot Clock-A logical 0 selects normal dot clocks
derived from the sequencer master clock input.
When this bit is set to 1, the master clock will be
divided by 2 to generate the dot clock. All the
other timings will be stretched since they are
derived from the dot clock. Dot clock divided by
two is used for 320x200 modes (0, 1, 4, 5) to
provide a pixel rate of 7 MHz, (9 MHz for mode
D).

Map Mask Register
This is a write-only register pointed to when the value in the
address register is hex 02. The output port address for this
register is hex 3C5.

20 IBM Enhanced Graphics Adapter

Map Mask Register Format
Bit

7

6

5

4

3

2

1

0
1 Enables Map 0

1 Enables Map 1

1 Enables Map 2
1 Enables Map 3
Not Used

Bit O-Bit 3

Map Mask-A logical 1 in bits 3 through 0
enables the processor to write to the
corresponding maps 3 through O. If this register
is programmed with a value of OFH, the CPU can
perform a 32-bit write operation with only one
memory cycle. This substantially reduces the
overhead on the CPU during display update
cycles in graphics modes. Data scrolling
operations are also enhanced by setting this
register to a value of OFH and writing the display
buffer address with the data stored in the CPU
data latches. This is a read-modify-write
operation. When odd/even modes are selected,
maps 0 and 1 and maps 2 and 3 should have the
same map mask value.

Character Map Select Register
This is a write-only register pointed to when the value in the
address register is hex 03. The output port address for this
register is 3C5.

IBM Enhanced Graphics Adapter 21

Character Map Select Register Format
Bit

7

6

5

4

3

2

1

0

~
I I ~I: :

'

-

-

1
1 1 1 ---------l~
'--""---'---.........

Bits

Not Used

Character Map Select B-Selects the map used
to generate alpha characters when attribute bit 3
is a 0, according to the following table:

Bit O-Bit 1

1

Character Map Select B
Character Map Select A

0

Map
Selected

0
1
0
1

0
1
2
3

Table Location

Value
0
0
1
1

Character Map Select A-Selects the map used
to generate alpha characters when attribute bit 3
is a 1, according to the following table:

Bit 2-Bit 3

Bits

3

1 st 8K of Plane 2 Bank 0
2nd 8K of Plane 2 Bank 1
3rd 8K of Plane 2 Bank 2
4th 8K of Plane 2 Bank 3

2

Map
Selected

0
1
0
1

0
1
2
3

Table Location

Value
0
0
1
1

1st 8K of Plane 2 Bank 0
2nd 8K of Plane 2 Bank 1
3rd 8K of Plane 2 Bank 2
4th 8K of Plane 2 Bank 3

In alphanumeric modes, bit 3 of the attribute byte normally has
the function of turning the foreground intensity on or off. This
bit however may be redefined as a switch between character sets.
This function is enabled when there is a difference between the
value in Character Map Select A and the value in Character Map
Select B. Whenever these two values are the same, the character
select function is disabled. The memory mode register bit 1 must
be a 1 (indicates the memory extension card is installed in the
unit) to enable this function; otherwise, bank 0 is always selected.

22 IBM Enhanced Graphics Adapter

128K of graphics memory is required to support two character
sets. 256K supports four character sets. Asynchronous reset
clears this register to O. This should be done only when the
sequencer is reset.

Memory Mode Register
This is a write-only register pointed to when the value in the
address register is hex 04. The processor output port address for
this register is 3C5.

Memory Mode Register Format
Bit

7

6

5

4

3

210

E

Alpha
Extended Memory
Odd/Even
Not Used

Bit 0

Alpha-A logical 0 indicates that a non-alpha
mode is active. A logical 1 indicates that alpha
mode is active and enables the character
generator map select function.

Bit 1

Extended Memory-A logical 0 indicates that the
memory expansion card is not installed. A logical
1 indicates that the memory expansion card is
installed and enables access to the extended
memory through address bits 14 and 15.

Bit 2

Odd/Even-A logical 0 directs even processor
addresses to access maps 0 and 2, while odd
processor addresses access maps 1 and 3. A
logical 1 causes processor addresses to
sequentially access data within a bit map. The
maps are accessed according to the value in the
map mask register.

IBM Enhanced Graphics Adapter 23

CRT Controller Registers
Name

Port

Index

Address Register
Horizontal Total
Horizontal Display End
Start Horizontal Blank
End Horizontal Blank
Start Horizontal Retrace
End Horizontal Retrace
Vertical Total
Overflow
Preset Row Scan
Max Scan Line
Cursor Start
Cursor End
Start Address High
Start Address Low
Cursor Location High
Cursor Location Low
Vertical Retrace Start
Light Pen High
Vertical Retrace End
Light Pen Low
Vertical Display End
Offset
Underline Location
Start Vertical Blank
End Vertical Blank
Mode Control
Line Compare

3?4
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5

00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
10
10
11
11
12
13
14
15
16
17
18

-

? = B in Monochrome Modes and 0 in Color Modes

CRT Controller Address Register
The Address register is a pointer register located at hex 3B4 or
hex 3D4. If an IBM Monochrome Display is attached to the
adapter, address 3B4 is used. If a color display is attached to the
adapter, address 3D4 is used. This register is loaded with a binary
value that points to the CRT Controller data register where data
is to be written. This value is referred to as "Index" in the table
above.

24 IBM Enhanced Graphics Adapter

CRT Controller Address Register Format
Bit

7

6

5

Bit O-Bit 4

4

3

2

1

0

CRT Controller Address Bits-A binary value
pointing to the CRT Controller register where
data is to be written.

Horizontal Total Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex 00. The processor output port
address for this register is hex 3B5 or hex 3D5.

Horizontal Total Register Format
Bit

7

6

5

4

3

2

1

0

~I-J1L.........L.1-..L..1--,--I-&.1-..L..1--,--I~.

Horizontal Total

This register defines the total number of characters in the
horizontal scan interval including the retrace time. The value
directly controls the period of the horizontal retrace output signal.
An internal horizontal character counter counts character clock
inputs to the CRT Controller, and all horizontal and vertical
timings are based upon the horizontal register. Comparators are
used to compare register values with horizontal character values
to provide horizontal timings.
Bit O-Bit 7

Horizontal Total-The total number of
characters less 2.

IBM Enhanced Graphics Adapter 25

Horizontal Display Enable End Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex 01. The processor output port
address for this register is hex 3B5 or hex 3D5.
Horizontal Display Enable End Register Format
Bit

7

6

5

4

3

2

1

0

&.. 1---L.1---I.1---I1:""'-L..1--L..I--,-I---,I_--t.~

Horizontal Display Enable End

This register defines the length of the horizontal display enable
signal. It determines the number of displayed character positions
per horizontal line.
Horizontal display enable end -A value one less
than the total number of displayed characters.

Bit O-Bit 7

Start Horizontal Blanking Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex 02. The processor output port
address for this register is hex 3B5 or hex 3D5.
Start Horizontal Blanking Register Format
Bit

7

6

5

4

3

I

1 1 1 1

2

1

0

I I I

.,

Start Vertical Blanking

This register determines when the horizontal blanking output
signal becomes active. The row scan address and underline scan
line decode outputs are multiplexed on the memory address
outputs and cursor outputs respectively during the blanking
interval. These outputs are latched external to the CRT
Controller with the falling edge of the BLANK output signal.
The row scan address and underline signals remain on the output
signals for one character count beyond the end of the blanking
signal.

26 IBM Enhanced Graphics Adapter

Start Horizontal Blanking-The horizontal
blanking signal becomes active when the
horizontal character counter reaches this value.

Bit O-Bit 7

End Horizontal Blanking Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex 03. The processor output port
address for this register is hex 3B5 or hex 3D5.

End Horizontal Blanking Register Format
Bit

7

6

5

4

I
I
II
.

3

2

1

0

I I I I :~

.

End Blanking
Display Enable Skew Control

L...-_ _ _ _ _ _ _----'_~

Not Used

This register determines when the horizontal blanking output
signal becomes inactive. The row scan address and underline scan
line decode outputs are multiplexed on the memory address
outputs and the cursor outputs respectively during the blanking
interval. These outputs are latched external to the CRT
Controller with the falling edge of the BLANK output signal.
The row scan address and underline signals remain on the output
signals for one character count beyond the end of the blanking
signal.
Bit O-Bit 4

End Horizontal Blanking-A value equal to the
five least significant bits of the horizontal
character counter value at which time the
horizontal blanking signal becomes inactive
(logical 0). To obtain a blanking signal of width
W, the following algorithm is used: Value of
Start Blanking Register + Width of Blanking
signal in character clock units = 5-bit result to be
programmed into the End Horizontal Blanking
Register.

IBM Enhanced Graphics Adapter 27

Display Enable Skew Control-These two bits
determine the amount of display enable skew.
Display enable skew control is required to
provide sufficient time for the CRT Controller to
access the display buffer to obtain a character
and attribute code, access the character generator
font, and then go through the Horizontal Pel
Panning Register in the Attribute Controller.
Each access requires the display enable signal to
be skewed one character clock unit so that the
video output is in synchronization with the
horizontal and vertical retrace signals. The bit
values and amount of skew are shown in the
following table:

Bit 5-Bit 6

Bits

6 5

o0

Zero character clock skew
lOne character clock skew
1 0 Two character clock skew
1 1 Three character clock skew

o

Start Horizontal Retrace Pulse Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex 04. The processor output port
address for this register is hex 3B5 or hex 3D5.

Start Horizontal Retrace Pulse Register Format
Bit

7

6

5

4

3

2

1

0

I I I I I I I I

~

Start Horizontal Retrace Pulse

This register is used to center the screen horizontally, and to
specify the character position at which the Horizontal Retrace
Pulse becomes active.

28 IBM Enhanced Graphics Adapter

Start Horizontal Retrace Pulse-The value
programmed is a binary count of the character
position number at which the signal becomes
active.

Bit O-Bit 7

End Horizontal Retrace Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex 05. The processor output port
address for this register is hex 3B5 or hex 3D5.
End Horizontal Retrace Register Format
Bit

7

6

II

5

4

3

2

I I I
I

1

0
End Horizontal Retrace
Horizontal Retrace Delay
Start Odd Memory Address

This register specifies the character position at which the
Horizontal Retrace Pulse becomes inactive (logical 0).
Bit O-Bit 4

End Horizontal Retrace-A value equal to the
five least significant bits of the horizontal
character counter value at which time the
horizontal retrace signal becomes inactive (logical
0). To obtain a retrace signal of width W, the
following algorithm is used: Value of Start
Retrace Register + width of horizontal retrace
signal in character clock units = 5-bit result to be
programmed into the End Horizontal Retrace
Register.

Bit 5-Bit 6

Horizontal Retrace Delay-These bits control
the skew of the horizontal retrace signal. Binary
00 equals no Horizontal Retrace Delay. For
some modes, it is necessary to provide a
horizontal retrace signal that takes up the entire
blanking interval. Some internal timings are
generated by the falling edge of the horizontal
retrace signal. To guarantee the signals are

IBM Enhanced Graphics Adapter 29

latched properly, the retrace signal is started
before the end of the display enable signal, and
then skewed several character clock times to
provide the proper screen centering.
Start Odd/Even Memory Address-This bit
controls whether the first CRT memory address
output after a horizontal retrace begins with an
even or an odd address. A logical 0 selects even
addresses; a logical 1 selects odd addresses. This
bit is used for horizontal pel panning applications.
Generally, this bit should be set to a logical O.

Bit 7

Vertical Total Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex 06. The processor output port
address for this register is hex 3B5 or 3D5.

Vertical Total Register Format
Bit

7

6

5

4

3

2

1

0

I I I I I I I I•
Bit O-Bit 7

Vertical Total

Vertical Total-This is the low-order eight bits of
a nine-bit register. The binary value represents
the number of horizontal raster scans on the CRT
screen, including vertical retrace. The value in
this register determines the period of the vertical
retrace signal. Bit 8 of this register is contained
in the CRT Controller Overflow Register hex 07
bit O.

CRT Controller Overflow Register
This is a write-only register pointed to when the value in the CRT
Controller Address Register is hex 07. The processor output port
address for this register is hex 3B5 or hex 3D5.

30 IBM Enhanced Graphics Adapter

CRTC Overflow Register Format
Bit

7

6

5

4

3

2

1

0
Vertical Total Bit 8
Vertical Display Enable End Bit 8
Vertical Retrace Start Bit 8
Start Vertical Blank Bit 8
Line Compare Bit 8 '

L...-_ _ _ _ _~-'"~

Cursor Location Bit 8
Not Used

Bit 0

Vertical Total-Bit 8 of the Vertical Total
register (index hex 06).

Bit 1

Vertical Display Enable End-Bit 8 of the
Vertical Display Enable End register (index hex
12).

Bit 2

Vertical Retrace Start-Bit 8 of the Vertical
Retrace Start register (index hex 10).

Bit 3

Start Vertical Blank-Bit 8 of the Start Vertical
Blank register (index hex 15).

Bit 4

Line Compare-Bit 8 of the Line Compare
register (index hex 18).

Bit 5

Cursor Location-Bit 8 of the Cursor Location
register (index hex OA).

Preset Row Scan Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex 08. The processor output port
address for this register is hex 3B5 or hex 3D5.

IBM Enhanced Graphics Adapter 31

Preset Row Scan Register Format
Bit

7

6

5

III

4

3

2

1

I I I I

0

I:

Starting Row Scan Count after
a Vertical Retrace
Not Used

This register is used for pel scrolling.
Preset Row Scan (Pel Scrolling)-This register
specifies the starting row scan count after a
vertical retrace. The row scan counter
increments each horizontal retrace time until a
maximum row scan occurs. At maximum row
scan compare time the row scan is cleared (not
preset).

Bit O-Bit 4

Maximum Scan Line Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex 09. The processor output port
address for this register is hex 3B5 or hex 3D5.
Maxim um Scan Line Register Format
Bit

7

6

5

4

3

2

0

I I:

III
Bit O-Bit 4

1

Maximum Scan Line
Not Used

Maximum Scan Line-This register specifies the
number of scan lines per character row. The
number to be programmed is the maximum row
scan number minus one.

Cursor Start Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex OA. The processor output port

32 IBM Enhanced Graphics Adapter

address for this register is hex 3B5 or hex 3D5.

Cursor Start Register Format
Bit

7

6

5

4

3

2

1

0

111"111:
Bit O-Bit 4

Row Scan Cursor Begins
Not Used

Cursor Start-This register specifies the row scan
of a character line where the cursor is to begin.
The number programmed should be one less than
the starting cursor row scan.

Cursor End R~gister
This is a write-only register pointed to when the value in the CRT
Controller address register is hex OB. The processor output port
address for this register is hex 3B5 or hex 3D5.

Cursor End Register Format
Bit

7

6

5

4

3

2

1

0

IIL..-....L...I_'_'~':

Row Scan Cursor Ends
Cursor Skew Control
Not Used

Bit O-Bit 4

Cursor End-These bits specify the row scan
where the cursor is to end.

Bit 5-Bit 6

Cursor Skew-These bits control the skew of the
cursor signal.

IBM Enhanced Graphics Adapter 33

Bits

6 5

o 0 Zero character clock skew
o lOne character clock skew
1 0
1 1

Two character clock skew
Three character clock skew

Start Address High Register
This is a read/write register pointed to when the value in the CRT
Controller address register is hex OC. The processor
input/ output port address for this register is hex 3B5 or hex 3D5.

Start Address High Register Format
Bit

7

6

5

4

3

2

1

0

I I I I I I I•

High Order Start Address

Start Address High-These are the high-order
eight bits of the start address. The 16-bit value,
from the high-order and low-order start address
registers, is 'the first address after the vertical
retrace on each screen refresh.

Bit O-Bit 7

Start Address Low Register
This is a read/write register pointed to when the value in the CRT
Controller address register is hex OD. The processor
input/ output port address for this register is hex 3B5 or hex 3D5.

Start Address Low Register Format
Bit

7

6

5

4

I I I

3

2

1

0

I •

34 IBM Enhanced Graphics Adapter

Low Order Start Address

Bit O-Bit 7

Start Address Low-These are the low-order 8
bits of the start address.

Cursor Location High Register
This is a read/write register pointed to when the value in the CRT
Controller address register is hex OE. The processor input/output
port address for this register is hex 3B5 or hex 3D5.

Cursor Location High Register Format
Bit

7

6

5

4

3

2

1

0

I I I I I I •

High Order Cursor Location

Cursor Location High-These are the high-order
8 bits of the cursor location.

Bit O-Bit 7

Cursor Location Low Register
This is a read/write register pointed to when the value in the CRT
Controller address register is hex OF. The processor input/output
port address for this register is hex 3B5 or Hex 3D5.

Cursor Location Low Register Format
Bit

7

6

5

4

3

2

1

0

I I I I I I I•
Bit O-Bit 7

Low Order Cursor Location

Cursor Location Low- These are the low-order
8 bits of the cursor location.

IBM Enhanced Graphics Adapter 35

Vertical Retrace Start Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex 10. The processor output port
address for this register is hex 3B5 or hex 3D5.

Vertical Retrace Start Register Format
Bit

7

6

5

4

3

2

1

0

I I I I I I I I
Bit O-Bit 7

Low Order Vertical Retrace Pulse

Vertical Retrace Start-This is the low-order 8
bits of the vertical retrace pulse start position
programmed in horizontal scan lines. Bit 8 is in
the overflow register location hex 07.

Light Pen High Register
This is a read-only register pointed to when the value in the CRT
Controller address register is hex 10. The processor input port
address for this register is hex 3B5 or hex 3D5.

Light Pen High Register Format
Bit

7

6

5

4

3

2.

1

0

I I I I II I I
Bit O-Bit 7

~

High Order Memory Address
Counter

Light Pen High-This is the high order 8 bits of
the memory address counter at the time the light
pen was triggered.

Vertical Retrace End Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex 11. The processor output port

36 IBM Enhanced Graphics Adapter

address for this register is hex 3B5 or hex 3D5.

Vertical Retrace End Register Format
Bit

765

II

432

I
I

1

0

I II I

~

Vertical Retrace End
O=Clear Vertical Interrupt
O=Enable Vertical Interrupt
Not Used

Bit O-Bit 3

Vertical Retrace End-These bits determine the
horizontal scan count value when the vertical
retrace output signal becomes inactive. The
register is programmed in units of horizontal scan
lines. To obtain a vertical retrace signal of width
W, the following algorithm is used: Value of Start
Vertical Retrace Register + width of vertical
retrace signal in horizontal scan units = 4-bit
result to be programmed into the End Horizontal
Retrace Register.

Bit 4

Clear Vertical Interrupt-A logical 0 will clear a
vertical interrupt.

Bit 5

Enable Vertical Interrupt-A logical 0 will
enable vertical interrupt.

Light Pen Low Register
This is a read-only register pointed to when the value in the CRT
Controller address register is hex 11. The processor input port
address for this register is hex 3B5 or 3D5.

IBM Enhanced Graphics Adapter 37

Light Pen Low Register Format
Bit

7

6

5

4

3

2

1

0

I I I I I I I I

Low Order Memory Address
Counter

Light Pen Low-This is is the low-order 8 bits of
the memory address counter at the time the light
pen was triggered.

Bit O-Bit 7

Vertical Display Enable End Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex 12. The processor output port
address for this register is hex 3B5 or hex 3D5.
Vertical Display Enable End Register Format
Bit

7

6

5

4

3

2

1

0

I I I I I I I •
Bit O-Bit 7

Low Order Vertical Display
Enable End

Vertical Display Enable End-These are the
low-order 8 bits of the vertical display enable end
position. This address specifies which scan line
ends the active video area of the screen. Bit 8 is
in the overflow register location hex 07.

Offset Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex 13. The processor output port
address for this register is hex 3B5 or hex 3D5.

38 IBM Enhanced Graphics Adapter

Offset Register Format
Bit

7

6

5

4

3

I I

2

1

0

~

I I I

Bit O-Bit 7

Logical line width of the screen

Offset-This register specifies the logical line
width of the screen. The starting memory
address for the next character row is larger than
the current character row by this amount. The
Offset Register is programmed with a word
address. Depending upon the method of clocking
the CRT Controller, this word address is either a
word or double word address.

Underline Location Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex 14. The processor output port
address for this register is hex 3B5 or hex 3D5.

Underline Location Register Format
Bit

7

6

5

4

3

I I

III
Bit O-Bit 4

2

1

0

:

Horizontal row scan where
underline will occur
Not Used

Underline Location-This register specifies the
horizontal row scan on which underline will
occur. The value programmed is one less than
the scan line number desired.

Start Vertical Blanking Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex 15. The processor output port

IBM Enhanced Graphics Adapter 39

address for this register is hex 3B5 or hex 3D5.

Start Vertical Blanking Register Format

Bit

7

6

5

4

3

2

1

0

I I I I I I I •
Bit O-Bit 7

Start Vertical Blanking

Start Vertical Blank-These are the low 8 bits of
the horizontal scan line count, at which the
vertical blanking signal becomes active. Bit 8 bit
is in the overflow register hex 07.

End Vertical Blanking Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex 16. The processor output port
address for this register is hex 3B5 or hex 3D5.

End Vertical Blanking Register Format

Bit

7

6

5

III
Bit O-Bit 4

4

3

2

1

0

I I I I

:

End Vertical Blanking

Not Used

End Vertical Blank-This register specifies the
horizontal scan count value when the vertical
blank output signal becomes inactive. The
register is programmed in units of horizontal scan
lines. To obtain a vertical blank signal of width
W, the following algorithm is used: Value of Start
Vertical Blank Register + width of vertical blank
signal in horizontal scan units = 5-bit result to be
programmed into the End Vertical Blank
Register.

40 IBM Enhanced Graphics Adapter

Mode Control Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex 17. The processor output port
address for this register is hex 3B5 or hex 3D5.

Mode Control Register Format
Bit

7

6

5

4

3

2

1

a
CMSO
Select Row Scan Counter
Horizontal Retrace Select
Count by Two

'---------l~ Output Control

'--_ _ _ _ _ _~ Address Wrap
'----------i,~ Word/Byte Mode
'-------------1~~ Hardware Reset

Bit 0

Compatibility Mode Support- When this bit is
a logical 0, the row scan address bit 0 is
substituted for memory address bit 13 during
active display time. A logical 1 enables memory
address bit 13 to appear on the memory address
output bit 13 signal of the CRT Controller. The
CRT Controller used on the IBM
Color/Graphics Monitor Adapter is the 6845.
The 6845 has 128 horizontal scan line address
capability. To obtain 640 by 200 graphics
resolution, the CRTC was programmed for 100
horizontal scan lines with 2 row scan addresses
per character row. Row scan address bit 0
became the most significant address bit to the
display buffer. Successive scan lines of the
display image were displaced in memory by 8K
bytes. This bit allows compatibility with the
6845 and Color Graphics AP A modes of
operation.

IBM Enhanced Graphics Adapter 41

Bit 1

Select Row Scan Counter-A logical 0 selects
row scan counter bit 1 on MA 14 output pin. A
logical 1 selects MA 14 counter bit on MA 14
output pin.

Bit 2

Horizontal Retrace Select-This bit selects
Horizontal Retrace or Horizontal Retrace divided
by 2 as the clock that controls the vertical timing
counter. This bit can be used to effectively
double the vertical resolution capability of the
CRT Controller. The vertical counter has a
maximum resolution of 512 scan lines due to the
9-bit wide Vertical Total Register. If the vertical
counter is clocked with the horizontal retrace
divided by 2 clock, then the vertical resolution is
doubled to 1024 horizontal scan lines. A logical
o selects HRTC and a logical 1 selects HRTC
divided by 2.

Bit 3

Count By Two- When this bit is set to 0, the
memory address counter is clocked with the
character clock input. A logical 1 clocks the
memory address counter with the character clock
input divided by 2. This bit is used to create
either a byte or word refresh address for the
display buffer.

Bit 4

Output Control-A logical 0 enables the module
output drivers. A logical 1 forces all outputs into
high impedance state.

Bit 5

Address Wrap-This bit selects Memory Address
counter bit MA 13 or bit MA 15, and it appears
on the MA 0 output pin in the word address
mode. If you are not in the word address mode,
MA 0 counter output appears on the MA 0
output pin. A logical 1 selects MA 15. In
odd/ even mode, bit MA 13 should be selected
when the 64K memory is installed on the board.
Bit MA 15 should be selected when greater then
64 K memory is installed. This function is used to
implement Color Graphics Monitor Adapter
compatibility.

42 IBM Enhanced Graphics Adapter

Word Mode or Byte Mode-When this bit is a
logical 0, the Word Mode shifts all memory
address counter bits down one bit, and the most
significant bit of the counter appears on the least
significant bit of the memory address outputs.
See table below for address outPQt details. A
logical 1 selects the Byte Address mode.

Bit 6

Internal Memory Address Counter
Wiring to the Output Multiplexer
CRTC Out Pin

Byte Address
Mode

MA O/RFA 0
MA 1/RFA 1
MA 2/RFA 2
MA 3/RFA 3

MAO
MA1
MA2
MA3

*
*
*
MA 14/RS 3
MA 15/RS 4

Word Address
Mode
MA 15 or MA 13
MAO
MA1
MA2

*
*
*

*
*
*

MA14
MA15

MA13
MA14

Hardware Reset-A logical 0 forces horizontal
and vertical retrace to clear. A logical 1 forces
horizontal and vertical retrace to be enabled.

Bit 7

Line Compare Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex 18. The processor output port
address for this register is hex 3B5 or hex 3D5.

Line Compare Register Format
Bit

765

432

1

0

I I I I I I I
Bit O-Bit 7

Line Compare Target

Line Compare-This register is the low-order 8
bits of the compare target. When the vertical

IBM Enhanced Graphics Adapter 43

counter reaches this value, the internal start of
the line counter is cleared. This allows an area of
the screen to be immune to scrolling. Bit 8 of
this register is in the overflow register hex 07.

44 IBM Enhanced Graphics Adapter

Graphics Controller Registers
Name

Port

Index

Graphics 1 Position
Graphics 2 Position
Graphics 1 & 2 Address
Set/Reset
Enable Set/Reset
Color Compare
Data Rotate
Read Map Select
Mode Register
Miscellaneous
Color Don't Care
Bit Mask

3CC
3CA
3CE
3CF
3CF
3CF
3CF
3CF
3CF
3CF
3CF
3CF

-

00
01
02
03
04
05
06
07
08

Graphics 1 Position Register
This is a write-only register. The processor output port address
for this register is hex 3CC.

Graphics I Position Register Format
Bit

7

6

5

4

3

2

1

0

IIIIIII~
Bit O-Bit 1

Position 0
Position 1
Not Used

Position-These 2 bits are binary encoded
hierarchy bits for the graphics chips. The
position register controls which 2 bits of the
processor data bus each chip responds to.
Graphics 1 must be programmed with a position
register value of 0 for this card.

IBM Enhanced Graphics Adapter 45

Graphics 2 Position Register
This is a write-only register. The processor output port address
for this register is hex 3CA.
Graphics II Position Register Format
Bit

7

6

5

4

3

2

1

0

1111111~
Bit O-Bit 1

Position 0
Position 1
Not Used

Position-These 2 bits are binary encoded
hierarchy bits for the graphics chips. The
position register controls which 2 bits of the
processor data bus to which each chip responds.
Graphics 2 must be programmed with a position
register value of 1 for this card.

Graphics 1 and 2 Address Register
This is a write-only register and the processor output port address
for this register is hex 3CE.
Graphics 1 and 2 Address Register Formats
Bit

7

6

5

4

IIII
Bit O-Bit 3

3

2

1

0

:

Graphics Address
Not Used

Graphics 1 and 2 Address Bits-This output loads
the address register in both graphics chips
simultaneously. This register points to the data
register of the graphics chips.

46 IBM Enhanced Graphics Adapter

Set/Reset Register
This is a write-only register pointed to by the value in the
Graphics 1 and 2 address register. This value must be hex 00
before writing can take place. The processor output port address
for this register is hex 3CF.

Set/Reset Register Format
Bit

7

6

5

4

3

2

1

0
Set/Reset Bit 0
Set/Reset Bit 1
Set/Reset Bit 2
Set/Reset Bit 3

Not Used

Bit O-Bit 3

Set/Reset-These bits represent the value
written to the respective memory planes when the
processor does a memory write with write mode 0
selected and set/reset mode is enabled.
Set/Reset can be enabled on a plane by plane
basis with separate OUT commands to the
Set/Reset register.

Enable Set/Reset Register
This is a write-only register and is pointed to by the value in the
Graphics 1 and 2 address register. This value must be hex 01
before writing can take place. The processor output port for this
register is hex 3CF.

IBM Enhanced Graphics Adapter 47

Color Compare Register Format
Bit

7

6

5

4

3

2

1

0
Color Compare 0
Color Compare 1
Color Compare 2
Color Compare 3
Not Used

Enable Set/Reset-These bits enable the
set/ reset function. The respective memory plane
is written with the value of the Set/Reset register
provided the write mode is O. When write mode
is 0 and Set/Reset is not enabled on a plane, that
plane is written with the value of the processor
data.

Bit O-Bit 3

Color Compare Register
This is a write-only register pointed to by the value in the
Graphics 1 and 2 address register. This value must be hex 02
before writing can take place. The processor output port address
for this register is hex 3CF.

Enable Set/Reset Register Format
Bit

7

6

5

4

3

2

1

0
Enable Set/Reset Bit 0
Enable Set/Reset Bit 1
Enable Set/Reset Bit 2
Enable Set/Reset Bit 3
Not Used

Bit O-Bit 3

Color Compare-These bits represent a 4 bit
color value to be compared. If the processor sets

48 IBM Enhanced Graphics Adapter

read mode 1 on the graphics chips, and does a
memory read, the data returned from the memory
cycle will be a 1 in each bit position where the 4
bit planes equal the color compare register.

Data Rotate Register
This is a write-only register pointed to by the value in the
Graphics 1 and 2 address register. This value must be hex 03
before writing can take place. The processor output port address
for this register is hex 3CF.
Data Rotate Register Format
Bit

7

6

5

4

3

2

1

0
Rotate Count
Rotate Count 1
Rotate Count 2
Function Select
Not Used

Bit O-Bit 2

Rotate Count-These bits represent a binary
encoded value of the number of positions to
rotate the processor data bus during processor
memory writes. This operation is done when the
write mode is O. To write unrotated data the
processor must select a count of O.

Bit 3-Bit 4

Function Select-Data written to memory can
operate logically with data already in the
processor latches. The bit functions are defined
in the following table.

IBM Enhanced Graphics Adapter 49

Bits
4 3

o

0
I
I 0
I I

Data unmodified.
Data AND'ed with latched data.
Data OR'ed with latched data.
Data XOR'ed with latched data.

o

Data may be any of the choices selected by the Write Mode
Register except processor latches. If rotated data is selected, the
rotate applies before the logical function.

Read Map Select Register
This is a write-only register pointed to by the value in the
Graphics 1 and 2 address register. This value must be hex 04
before writing can take place. The processor output port address
for this register is hex 3CF.

Read Map Select Register Format
Bit

7

6

5

4

3

2

1

0

~
~

Bit O-Bit 2

Map Select 0
Map Select 1
Map Select 2
Not Used

Map Select-These bits represent a binary
encoded value of the memory plane number from
which the processor reads data. This register has
no effect on the color compare read mode
described elsewhere in this section.

Mode Register
This is a write-only register pointed to by the value in the
Graphics 1 and 2 address register. This value must be hex 05

50 IBM Enhanced Graphics Adapter

before writing can take place. The processor output port address
for this register is 3CF.

Mode Register Format

Bit

7

6

5

4

3

2

II

1

0

II :

Write Mode
Test Condition
Read Mode

'-------~

'--------~
'---..&....--------~

Bit O-Bit 1

Odd/Even
Shift Register Mode
Not Used

Write Mode
Bits

1 0

o0

o1
1 0
1 1

Each memory plane is written with the
processor data rotated by the number of
counts in the rotate register, unless
Set/Reset is enabled for the plane. Planes
for which Set/Reset is enabled are written
with 8 bits of the value contained in the
Set/Reset register for that plane.
Each memory plane is written with the
contents of the processor latches. These
latches are loaded by a processor read
operation.
Memory plane n (0 through 3) is filled
with 8 bits of the value of data bit n.
Not Valid

The logic function specified by the function select
register also applies.
Bit 2

Test Condition-A logical 1 directs graphics
controller outputs to be placed in high impedance
state for testing.

IBM Enhanced Graphics Adapter 51

Bit 3

Read Mode-When this bit is a logical 0, the
processor reads data from the memory plane
selected by the read map select register. When
this bit is a logical 1, the processor reads the
results of the comparison of the 4 memory planes
and the color compare register.

Bit 4

Odd/Even-A logical 1 selects the odd/even
addressing mode, which is useful for emulation of
the Color Graphics Monitor Adapter compatible
modes. Normally the value here follows the value
of the Memory Mode Register bit 3 of the
Sequencer.

Bit 5

Shift Register-A logical 1 directs the shift
registers on each graphics chip to format the
serial data stream with even numbered bits on the
even numbered maps and odd numbered bits on
the odd maps.

MisceUaneous Register
This is a write-only register pointed to by the value in the
Graphics 1 and 2 address register. This value must be hex 06
before writing can take place. The processor output port for this
register is hex 3CF.

Miscellaneous Register Format
Bit

7

6

5

4

3

2

1

0
Graphics Mode
Chain Odd Maps to Even
Memory Map 0
Memory Map 1
Not Used

52 IBM Enhanced Graphics Adapter

Bit 0

Graphics Mode-This bit controls alpha-mode
addressing. A logical 1 selects graphics mode.
When set to graphics mode, the character
generator address latches are disabled.

Bit 1

Chain Odd Maps To Even Maps-When set to 1,
this bit directs the processor address bit 0 to be
replaced by a higher order bit and odd/even
maps to be selected with odd/even values of the
processor AO bit, respectively.

Bit 2-Bit 3

Memory Map-These bits control the mapping of
the regenerative buffer into the processor address
space.
Bits

3 2

o0
o

1
1 0
1 1

Hex AOOO for 128K bytes.
Hex AOOO for 64K bytes.
Hex BOOO for 32K bytes
Hex B800 for 32K bytes.

If the display adapter is mapped at address hex AOOO for 128K

bytes, no other adapter can be installed in the system.

Color Don't Care Register
This is a write-only register and is pointed to by the value in the
Graphics 1 and 2 address register. This value must be hex 07
before writing can take place. The processor output port for this
register is hex 3 CF.

IBM Enhanced Graphics Adapter 53

Color Don't Care Register Format
Bit

7

6

5

4

3

2

1

0
Color Plane O=Don't Care
Color Plane 1 =Don't Care
Color Plane 2=Don't Care
Color Plane 3=Don't Care
Not Used

Color Don't Care-Color plane O=don't care
when reading color compare when this bit is set to

Bit 0

1.

Color Don't Care-Color plane 1 =don't care
when reading color compare when this bit is set to

Bit 1

1.

Color Don't Care-Color plane 2=don't care
when reading color compare when this bit is set to

Bit 2

1.

Color Don't Care-Color plane 3=don't care
when reading color compare when this bit is set to

Bit 3

1.

Bit Mask Register
This is a write-only register and is pointed to by the value in the
Graphics 1 and 2 address register. This value must be hex 08
before writing can take place. The processor output port for this
register is hex 3CF.

Bit Mask Register Format
Bit

7

6

5

4

3

2

1

0

I I I I I I I I•

O-Immune to change
1-Unimpeded Writes

54 IBM Enhanced Graphics Adapter

Bit O-Bit 7

Bit Mask-Any bit programmed to n causes the
corresponding bit nin each bit plane to be
immune to change provided that the location
being written was the last location read by the
processor. Bits programmed to a 1 allow
unimpeded writes to the corresponding bits in the
bit planes.

The bit mask applies to any data written by the processor (rotate,
AND'ed, OR'ed, XOR'ed, DX, and SIR). To preserve bits using
the bit mask, data must be latched internally by reading the
location. When data is written to preserve the bits, the most
current data in latches is written in those positions. The bit mask
applies to all bit planes simultaneously.

IBM Enhanced Graphics Adapter 55

Attribute Controller Registers
Name

Port

Index

Address Register
Palette Registers
Mode Control Register
Overscan Color Register
Color Plane Enable Register
Horizontal Pel Panning Register

3CO
3CO
3CO
3CO
3CO
3CO

OO-OF
10
11
12
13

Attribute Address Register
This is a write-only register. The processor output port is hex
3CO.

Palette Registers Hex 00 through Hex OF Format
Bit

7

6

5

4

3

2

1

0

~
Bit O-Bit 4

Blue Video
Green Video
Red Video
Secondary Blue/Mono Video

,

Secondary Green/Intensity

,

Secondary Red Video

,

Not Used

Attribute Address Bits-The Address Register is
a pointer register located at hex 3CO. This
register is loaded with a binary value that points
to the attribute data register where data is to be
written. The Attribute Controller does not have
an address bit input to control selection of the
address and data registers. An internal address
flip-flop controls selection of either the address
or data registers. To initialize the flip-flop, an
lOR instruction is issued to the Attribute
Controller at address 3BA or 3DA. This clears
the flip-flop, and selects the Address Register.
After the Address Register has been loaded, the

56 IBM Enhanced Graphics Adapter

next OUT instruction loads the data register.
The flip-flop toggles each time an OUT is issued
to the Attribute Controller.
Palette Address Source-When loading the color
palette registers, bit 5 must be cleared to O. To
enable the memory data to access the color
palette, bit 5 must be set to 1.

Bit 5

Palette Register Hex 00 through Hex OF
This is a write-only register. The processor output port is hex

3eo.

Attribute Address Register Format
Bit

7

6

5

I~ ~
l.

II
Bit O-Bit 5

-

4

I.

3

2

1

0

_I_II_I~.::
-

Attribute Address
Palette Address Source
Not Used

Palette-These 6-bit registers allow a dynamic
mapping between the text attribute or graphic
color input value and the display color in the
CRT screen. A logical 1 selects the appropriate
color. A logical 0 de-selects. The color palette
register should be modified only during the
vertical retrace interval to avoid glitches in the
displayed image. Note that some color monitors
do not have an intensity input and only a
maximum of eight colors are be available.
Monitors with four color inputs display sixteen
colors, and monitors with six color inputs display
64 colors.

IBM Enhanced Graphics Adapter 57

Mode Control Register
This is a write-only register pointed to by the value in the
Attribute address register. This value must be hex 10 before
writing can take place. The processor output port address for this
register is hex 3CO.

Mode Control Register Format
Bit

7

6

5

4

3

2

1

0
Graphics/Alphanumeric Mode
Display Type
Enable Line Graphics Character
Codes
Select Background Intensity Or
Enable Blink

'----'-...I.---'-_ _ _ _ _......~

Not Used

Bit 0

Graphics/ Alphanumeric Mode-A logical 0
selects selects alphanumeric mode. A logical 1
selects graphics mode.

Bit 1

Monochrome Display/Color Display-A logical
o selects IBM monochrome display attributes. A
logical 1 selects color Display attributes.

Bit 2

Enable Line Graphics Character Codes-When
this bit is set to 0, the ninth dot will be the same
as the background. A logical 1 enables the
special line graphics character codes for the IBM
Monochrome Display adapter. This bit when
enabled forces the ninth dot of a line graphic
character to be identical to the eighth dot of the
character. The line graphics character codes for
the Monochrome Display Adapter are Hex CO
through Hex DF.
For character fonts that do not utilize the line
graphics character codes in the range of Hex CO

58 IBM Enhanced Graphics Adapter

through Hex DF, bit 2 of this register should be a
logical O. Otherwise unwanted video information
will be displayed on the CRT screen.
Enable Blink/Select Background Intensity-A
logical 0 selects the background intensity of the
attribute input. This mode was available on the
Monochrome and Color Graphics adapters. A
logical 1 enables the blink attribute in
alphanumeric modes. This bit must also be set to
1 for blinking graphics modes.

Bit 3

Overscan Color Register
This is a write-only register pointed to by the value in the
Attribute address register. This value must be hex 11 before
writing can take place. The processor output port address for this
register is hex 3CO.

Overscan Color Register Format
Bit

7

6

5

4

3

2

1

0
Selects Blue Border Color
Selects Green Border Color
Selects Red Border Color
Selects Secondary Blue
Border Color
Selects I ntensified or
Secondary Green
Selects Secondary Red
Border Color
Not Used

Bit O-Bit 5

Overscan Color-This 6-bit register determines
the overscan (border) color displayed on the
CRT screen. For monochrome display this
register should be set to a value of O. A logical 1
selects the appropriate color.

IBM Enhanced Graphics Adapter 59

Color Plane Enable Register
This is a write-only register pointed to by the value in the
Attribute address register. This value must be hex 12 before
writing can take place. The processor output port address for this
register is 3CD.

Color Plane Enable Register Format
Bit

7

6

5

4

3

2

1

0

11a....-.....L-11_11_1~1:

Enable Color Plane
Video Status MUX
Not Used

Bit O-Bit 3

Enable Color Plane-Writing a logical 1 in any
of bits 0 through 3 enables the respective display
memory color plane.

Bit 4-Bit 5

Video Status MUX-Selects two of the six color
outputs to be available on the status port. The
following table illustrates the combinations
available and the color output wiring.

COLOR PLANE
ENABLE REGISTER

INPUT STATUS
REGISTER ONE

Bit5

Bit4

Bit5

Bit4

0
0
1
1

0
1
0
1

Red
Secondary Blue
Secondary Red
Not Used

Blue
Green
Secondary Green
Not Used

Horizontal Pel Panning Register
This is a write-only register pointed to by the value in the
Attribute address register. This value must be hex 12 before
writing can take place. The processor output port address for this
register is hex 3CO.

60 IBM Enhanced Graphics Adapter

Horizontal Pel Panning Register Format
Bit

7

6

5

4

3

2

1

I I I II'----'I--

0

~:

--1--1

Bit O-Bit 3

Horizontal Pel Panning
Not Used

Horizontal Pel Panning-This 4 bit register
selects the number of picture elements (pels) to
shift the video data horizontally to the left. Pel
panning is available in both A/N and AP A
modes. In Monochrome A/N mode, the image
can be shifted a maximum of 9 pels. In all other
A/N and AP A modes, the image can be shifted a
maximum of 8 pels. The sequence for shifting
the image is given below:
9 pels/character: 8, 0, 1, 2, 3, 4, 5, 6, 7
(Monochrome A/N mode only)
8 pels/character: 0, 1,2,3,4,5,6,7 (All other
Modes)

IBM Enhanced Graphics Adapter 61

Programming Considerations

Programming the Registers
Each of the LSI devices has an address register and a number of
data registers. The address register serves as a pointer to the
other registers on the LSI device. It is a write-only register that is
loaded by the processor by executing an 'OUT' instruction to its
I/O address with the index of the selected data register.
The data registers on each LSI device are accessed through a
common I/O address. They are distinguished by the pointer
(index) in the address register. To write to a data register, the
address register is loaded with the index of the appropriate data
register, then the selected data register is loaded by executing an
'OUT' instruction to the common I/O address.
The external registers that are not part of an LSI device and the
Graphics I and II registers are not accessed through an address
register; they are written to directly.
The following tables define the values that are loaded into the
registers by BIOS to support the different modes of operation
supported by this adapter.

62 IBM Enhanced Graphics Adapter

Rllister

Media' Operetill

Nlme

Port

Index

0

1

2

3

4

5

6

7

0

E

F 10

F:

10: 0*

1* 2* 3*

Misceilaneous

3C2

-

23 23 23 23 23 23 23 A6 23 23 A2 A7 A2 A7 A7 A7 A7 A7

Feature Cntri

3?A

-

00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Input Stat 0

3C2

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

3?2

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Input Stat 1

? = B in monochrome modes

-

-

-

-

-

? = D in color modes

'Values for these modes when the IBM Enhanced Color Display is attached
:Values for these modes when greater than 64K Graphics Memory is installed

Externa~

Registers

Register

Mode of Operation

Port

Index

0

1

2

3

4

5

6

7

0

E

F 10

F:

Seq Address

3C4

-

-

-

-

-

-

-

-

-

-

-

-

-

-

03 03 03 03 03 03 03 03 03 03 03 03 03 03 03 03 03 03

Nlme

Reset

3C5

00

Clock Mode

3C5

01

OB OB Q1

Map Mask

3C5

02

03 03 03 03 03 03 01

01

OB OB 01

00 OB 01

05 05 01

10: 0*

-

01

-

1* 2* 3*

-

-

OB OB 01

[-

01

03 OF OF OF OF OF OF 03 03 03 03

Char Gen Sel

3C5

03

00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Memory Mode

3C5

04

03 03 03 03 02 02 06 03 06 06 00 00 06 06 03 03 03 03

'Values for these modes when the IBM Enhanced Color Display is attached
:Values for these modes when greater than 64 K Graphics Memory is installed

Sequencer Registers

IBM Enhanced Graphics Adapter 63

Mode of Operllion

Hellat.r
Mill.

P,rt

Ild.1

0

1

2

3

4

5

6

7

0

E

F 10

F! 10: 0* 1* 2* 3*

-

-

-

- -

-

-

-

-

-

-

Address Reg

3?4

-

-

Horiz Total

3?5

00

37 37 70 70 37 37 70 60 37 70 60 5B 60 5B 2D 2D 5B 5B

Hrz Disp End

3?5

01

27 27 4F 4F 27 27 4F 4F 27 4F 4F 4F 4F 4F 27 27 4F 4F

Strt Hrz Blk

3?5

02

2D 2D 5C 5C 2D 2D 59 56 2D 56 56 53 56 53 2B 2B 53 53

End Hrz Blk

3?5

03

37 37 2F 2F 37 37 2D 3A 37 2D 1A 17 3A 37 2D 2D 37 37

Strt Hrz Retr

3?5

04

31

31

5F 5F 30 30 5E 51

-

-

-

-

-

30 5E 50 50 50 52 28 28 51

-

51

End Hrz Retr

3?5

05

15 15 07 07 14 14 06 60 14 06 EO BA

Vert Total

3?5

06

04 04 04 04 04 04 04 70 04 04 70 6C 70 6C 6C 6C 6C 6C

Over1low

3?5

07

11

08

00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

11

11

11

11

11

11

1F 11

11

6e 00 6D 6D 5B 5B

1F 1F 1F 1F 1F 1F 1F 1F

Preset Row SC

3?5

Max Scan Line

3?5

09

07 07 07 07 01

Cursor Start

3?5

OA

06 06 06 06 00 00 00 OB 00 00 00 00 00 00 DB DB DB OB

Cursor End

3?5

DB

07 07 07 07 00 00 00 DC 00 00 00 00 00 00 OC DC DC OC

Strt Addr Hi

3?5

OC

Strt Addr Lo

3?5

OD

-

? = B in monochrome modes

-

-

-

-

-

-

01

- - -

01

OD 00 00 00 00 00 00 OD OD OD OD

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

? = D in color modes

·Values for these modes when the IBM Enhanced Color Display is attached
:Values for these modes when greater than 64 K Graphics Memory is installed

CRT Controller Registers (1 of 2)

64 IBM Enhanced Graphics Adapter

Mode of Operation

R.gister

Nlme

Port

Index

0

1

2

3

4

5

6

7

0

E

F 10

F:

10: 0* 1* 2* 3*

Cursor LC Hi

3?5

OE

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Cursor LC Low

3?5

OF

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Vrt Retr Strt

3?5

10

E1

E1

E1

E1

E1

E1

EO 5E E1

-

-

-

-

-

-

-

EO 5E 5E 5E 5E 5E 5E 5E 5E

-

-

Light Pen Hi

3?5

10

-

Vert Retr End

3?5

11

24 24 24 24 24 24 23 2E 24 23 2E 28 2E 28 2B 2B 2B 2B

Light Pen Low

3?5

11

-

C7 C7 C7 C7 C7 C7 C7 50 C7 C7 5D 5D 50 50 50 50 5D 5D

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Vrt Oisp End

3?5

12

Offset

3?5

13

14 14 28 28 14 14 28 28 14 28 14 14 28 28 14 14 28 28

Underline Loc

3?5

14

08 08 08 08 Q{) 00 00 00 00 00 OD OF 00 OF OF OF OF OF

Strt Vert Blk

3?5

15

EO EO EO EO EO EO OF 5E EO OF 5E 5F 5E 5F 5E 5E 5E 5E

End Vert Blk

3?5

16

FO FO FO FO FO FO EF 6E FO EF 6E OA 6E OA OA OA OA OA

Mode Control

3?5

17

A3 A3 A3 A3 A2 A2 C2 A3 E3 E3 8B 8B E3 E3 A3 A3 A3 A3

Line Compare

3?5

18

FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF

? = B in monochrome modes

? = D in color modes

'Values for these modes when the IBM Enhanced Color Display is attached
:Values for these modes when greater than 64K Graphics Memory is installed

CRT Controller Registers (2 of 2)

IBM Enhanced Graphics Adapter 65

Register

Mode 01 Operation
Index

Grphx I Pos

3CC

-

00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Grphx II Pos

3CA

-

01

01

01

01

01

01

01

01

01

01

01

01

01

01

01

01

01

01

Grphx III AD

3CE

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Set Reset

3CF

00

00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Enable SIR

3CF

01

00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

0

1

F:

Port

Name

2

3

4

5

6

7

0

E

F

10

10: 0*

1* 2* 3*

Color Compare

3CF

02

00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Data Rotate

3CF

03

00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Read Map Sel

3CF

04

00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Mode Register

3CF

05

10 10 10 10 30 30 00 10 00 00 10 10 00 00 10 10 10 10

Miscellaneous

3CF

06

DE DE DE DE OF OF 00 OA 05 05 07 07 05 05 OE DE DE DE

Color No Care

3CF

07

00 00 00 00 00 00 00 00 OF OF OF ·OF OF OF 00 00 00 00

Bit Mask

3CF

08

FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF

'Values for these modes when the IBM Enhanced Color Display is attached
:Values lor these modes when greater than 64 K Graphics Memory is installed

Graphics 51 Registers

66 IBM Enhanced Graphics Adapter

Re.later

Mode a' O,eretlll

Port

Index

0

1

2

3

4

5

6

7

0

E

F 10

Address

3?A

-

-

-

-

-

-

-

-

-

-

-

-

Palette

3CO

00

00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Nlme

01

01

13 13 17 08 01 01

Ft lOt 0* 1* 2* 3*
-

-

08 01 08 01

01

-

01

-

01

-

01

Palette

3CO

01

01

Palette

3CO

02

02 02 02 02 15 15 17 08 02 02 00 00 00 02 02 02 02 02

Palette

3CO

03

03 03 03 03 17 17 17 08 03 03 00 00 00 03 03 03 03 03

Palette

3CO

04

04 04 04 04 02 02 17 08 04 04 18 04 18 04 04 04 04 04

Palette

3CO

05

05 05 05 05 04 04 17 08 05 05 18 07 18 05 05 05 05 05

Palette

3CO

06

06 06 06 06 06 06 17 08 06 06 00 00 00 06 14 14 14 14

3CO

07

07 07 07 07 07 07 17 08 07 07 00 00 00 07 07 07 07 07

Palette

01

-

Palette

3CO

08

10 10 10 10 10 10 17 10 10 10 00 00 00 38 38 38 38 38

Palette

3CO

09

11

Palette

3CO

OA

12 12 12 12 12 12 17 18 12 12 00 00 00 3A 3A 3A 3A 3A

Palette

3CO

OB

13 13 13 13 13 13 17 18 13 13 00 00 00 3B 3B 3B 3B 3B

?

= B in monochrome modes

11

11 11

11

11

17 18 11 11 08 01

08 39 39 39 39 39

? = D in color modes

'Values for these modes when the IBM Enhanced Color Display is attached
:Values for these modes when greater than 64K Graphics Memory is installed

Attribute Registers (1 of 2)

IBM Enhanced Graphics Adapter 67

Register
Name

Mode of Operation

7

F! 10: 0* 1* 2* 3*

Port

Index

Palette

3CO

OC

14 14 14 14 14 14 17 18 14 14 00 04 00 3C 3C 3C 3C 3C

Palette

3CO

OD

15 15 15 15 15 15 17 18 15 15 18 07 18 3D 3D 3D 3D 3D

Palette

3CO

OE

16 16 16 16 16 16 17 18 16 16 00 00 00 3E 3E 3E 3E 3E

Palette

3CO

OF

17 17 17 17 17 17 18 17 17 00 00 00 3F 3F 3F 3F 3F 3F

Mode Control

3CO

10

08 08 08 08 01

Overscan

3CO

11

00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Color Plane

3CO

12

OF OF OF OF 03 03 01

Hrz Panning

3CO

13

00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

0

1

2

3

4

5

01

6

0

E

01 OE 01 01

:Values for these modes when greater than 64K Graphics Memory is installed

68 IBM Enhanced Graphics Adapter

OB OB OB 01

08 08 08 08

OF OF OF 05 05 05 OF OF OF OF OF

·Values for these modes when the IBM Enhanced Color Display is attached

Attribute Registers (2 of 2)

F 10

RAM Loadable Character Generator
The character generator on the adapter is RAM loadable and can
support characters up to 32 scan lines high. Two character
generators are stored within the BIOS and one is automatically
loaded into the RAM by the BIOS when an alphanumeric mode is
selected. The Character Map Select Register can be programmed
to define the function of bit 3 of the attribute byte to be a
character generator switch. This allows the user to select between
any two character sets residing in bit plane 2. This effectively
gives the user access to 512 characters instead of 256. character
tables may be loaded off line.The adapter must have 128K bytes
of storage to support this function. Up to four tables can be
loaded can be loaded with 256K of graphics memory installed.
The structure of the character tables is described in the following
figure. The character generator is in bit plane 2 and must be
protected using the map mask function.
Bit Plane 2

+OK
Character
Generator 0

+8K

Character
Generator 1

Character
Generator 2

+48K
Character
Generator 3

+64K

~--------------------------~

The following figure illustrates the structure of each character
pattern. If the CRT controller is programmed to generate n row

IBM Enhanced Graphics Adapter 69

scans, then n bytes must be filled in for each character in the
character generator. The example assumes eight row scans per
character.
Byte Image

Address

CC * 32

+0

Data
18H
3EH

2

66H

3

66H

4

7EH

5

66H

6

66H

7

66H

CC = Value of the character code. For example, 41H in the case
of an ASCII "A".

Creating a 512 Character Set
This section describes how to create a 512 character set on the
IBM Color Display. Note that only 256 characters can be printed
on the printer. This is a special application which the Enhanced
Graphics Adapter will support. The 9 by 14 characters will be
displayed when attribute bit 3 is a logical 0, and the IBM
Color / Graphics Monitor Adapter 8 by 8 characters will be
displayed when the attribute bit 3 is a logical 1. This example is
for demonstrative purposes only. The assembly language routine
for creating 512 characters is given below. Debug 2.0 was used
for this example. The starting ,assembly address is 100 and the
character string is stored in location 200. This function requires
128K or more of graphics memory.

70 IBM Enhanced Graphics Adapter

alOO
movax,1102
mov bl,02
intlO

;load 8x8 character font in character
;generator number 2

movax,1103
mov bl,08
intlO

;select 512 character operation
;if attribute bit 3 = 1 use 8x8 font
;if attribute bit 3=0 use 9x14 font

movax,lOOO
mov bx,07l2
intlO

;set color plane enable to 7H to disable
;attribute bit 3 in the color palette
;lookup table

movax,130l
mov bx,OOOF
mov cx,003A
mov dx,1600
mov bp,0200
push cs
pop es
intlO
mov ax ,1301
mov bx,0007
mov cx,003A
mov dx,1700
mov bp,0200
push cs
pop es
intlO
int3
a200 db

;write char. string with attribute bit 3= 1
;cx = character string length
;write character on line 22 of display
;pointer to character string location

;write char. string with attribute bit 3=0
;cx = character string length
;write character on line 23 of display
;pointer to character string location

"This character string is used to show 512
characters' ,

Creating an 80 by 43 Alphanumeric Mode
The following examples show how to create 80 column by 43
row, both alphanumeric and graphics, images on the IBM
Monochrome Display. The BIOS Interface supports an 80
column by n row display by using the character generator load
routine call. The print screen routine must be revectored to

IBM Enhanced Graphics Adapter 71

handle the additional character rows on the screen. The assembly
language required for both an alphanumeric and a graphics screen
is shown below.
moval,7

intlO
movax,1112
mov bl,O

intlO
movax,1200
move bl,20

intlO
int3
movax,f

intlO
movax,1123
mov bl,O
mov dl,2B

intlO
movax,1200
mov bl,20

intlO
int3

;Monochrome alphanumeric mode
;video interrupt call
;character generator BIOS routine
;load 8 by 8 double dot character font
;video interrupt call
;alternate screen routine
;select alternate print screen routine
;video interrupt call
;Monochrome graphic mode
;video interrupt call
;character generator BIOS routine
;load 8 by 8 double dot character font
;43 character rows
;video interrupt call
;alternate screen routine
;alternate print screen routine
;video interrupt call

Vertical Interrupt Feature
The Enhanced Graphics Adapter can be programmed to create an
interrupt each time the vertical display refresh time has ended.
An interrupt handler routine must be written by the application to
take advantage of this feature. The CRT Vertical interrupt is on
IRQ2. The CPU can poll the Enhanced Graphics Adapter Input
Status Register 0 (bit 7) to determine whether the CRTC caused
the interrupt to occur.
The Vertical Retrace End Register (11 H) in the CRT controller
contains two bits which are used to control the interrupt circuitry.
The remaining bits must be output as per the value in the mode
table.

72 IBM Enhanced Graphics Adapter

Bit 5

Enable Vertical Interrupt-A logical 0 will
enable vertical interrupt.

Bit 4

Clear Vertical Interrupt-A logical 0 will clear a
vertical interrupt.

The sequence of events which occur in an interrupt handler are
outlined below.
1.
2.
3.
4.
5.
6.
7.
8.

Clear IRQ latch and enable driver
Enable IRQ latch
Wait for vertical interrupt
Poll Interrupt Status Register 0 to determine if CRTC has
caused the interrupt
If CRTC interrupt, then clear IRQ latch; if not, then branch
to next interrupt handler.
Enable IRQ latch
Update Enhanced Graphics Adapter during vertical blanking
interval
Wait for next vertical interrupt

Creating a Split Screen
The Enhanced Graphics Adapter hardware supports an
alphanumeric mode dual screen display. The top portion of the
screen is designated as screen A, and the bottom portion of the
screen is designated as screen B as per the following figure.

Screen A

Screen B

Dual Screen Definition

The following figure shows the screen mapping for a system
containing a 32K byt~ alphanumeric storage buffer. Note that the
Enhanced Graphics Adapter has a 32K byte storage buffer in
alphanumeric mode. Information displayed on screen A is

IBM Enhanced Graphics Adapter 73

defined by the start address high and low registers (OCH and
ODH) of the CRTC. Information displayed on screen B always
begins at address OOOOH.
OOOOH
Screen B
Buffer Storage Area

OFFFH
1000H

1---------\

Screen A
Buffer Storage Area

7FFFH '---_ _ _ _ _---'

Screen Mapping Within the Display Buffer Address Space

The Line Compare Register (18H) of the CRT Controller is
utilized to perform the split screen function. The CRTC has an
internal horizontal scan counter, and logic ·which compares the
horizontal scan counter value to the Line Compare Register value
and clears the memory address generator when a compare occurs.
The linear address generator then sequentially addresses the
display buffer starting at location zero, and each subsequent row
address is is determined by the 16 bit addition of the start of line
latch and the offset register.
Screen B can be smoothly scrolled onto the CRT screen by
updating the Line compare in synchronization with the vertical
retrace signal. The information on screen B is immune from
scrolling operations which utilize the Start Address High and Low
registers to scroll through the Screen A address map.

Compatibility Issues
The CRT Controller on the IBM Enhanced Graphics Adapter is a
custom design, and is different than the 6845 controller used on
the IBM Monochrome Monitor Adapter and the IBM
Color/Graphics Monitor Adapter. It should be noted that several
CRTC register addresses differ between the adapters. The
following figure illustrates the registers which do not map directly
across the two controllers.

74 IBM Enhanced Graphics Adapter

Register

6485 Function

EGA CRTC Function

02H

Start Horiz. Retrace

Start Horiz. Blanking

03H

End Horiz. Retrace

End Horiz. Blanking

04H

Vertical Total

Start Horiz. Retrace

OSH

Vertical Total Adjust

End Horiz. Retrace

06H

Vertical Displayed

Vertical Total

07H

Vertical Sync Position

Overflow

08H

Interlace Mode and Skew

Preset Row Scan

Existing applications which utilize the BIOS interface will
generally be compatible with the Enhanced Graphics Adapter.
Horizontal screen centering was required on the IBM
Color / Graphics Monitor Adapter in order to center the screen
when generating composite video. This was done through the
Horizontal Sync Position Register. Since the Enhanced Graphics
Adapter does not support a composite video monitor, programs
which do screen centering may cause loss of the screen image if
centering is attempted.
The Enhanced Graphics Adapter offers a wider variety of
displayable monochrome character attributes than the IBM
Monochrome Display Adapter. Some attribute values may
display differently between the two Adapters. The values listed in
the table below, in any combinations with the blink and intensity
attributes, will display identically.
Background
R G B
0
0
0
1

0 0
0 0
0 0
1 1

Foreground
R G B
0
0
1
0

0
0
1
0

0
1
1
0

Function
Non-Display
Underline
White Character/Black Background
Reverse Video

Software which explicitly addresses 3D8 (Mode Select Register)
or 3D9 (Color Select Register) on the Color Graphics Monitor
Adapter may produce different results on the Enhanced Graphics
Adapter. For example, blinking which is disabled by writing to
3D8 on the Color Graphics Adapter will not be disabled on the
Enhanced Graphics Adapter.

IBM Enhanced Graphics Adapter 75

Interface

Feature Connector
The following is a description of the Enhanced Graphics Adapter
feature connector. Note that signals coming from the Enhanced
Graphics Adapter are labeled "inputs" and the signals coming to
the Enhanced Graphics Adapter through the feature connector
are labeled "outputs".
Signal

Description

J2

This pin is connected to auxiliary jack 2 on the rear
panel of the adapter.

R'OUT

Secondary red output

ATRS/L

Attribute shift load. This signal controls the
serialization of the video information. The shift
register parallel loads at the dot clock leading edge
when this signal is low.

G OUT

Primary green output

R'

Secondary red input

R

Primary red input

FC1

This signal is input from bit 1 (Feature Control Bit
1) of the Feature Control Register.

FCO

This signal is input from bit 0 (Feature Control Bit
0) of the Feature control Register.

FEAT 0

This signal is output to bit 5 (Feature Code 0) of
Input Status Register O.

B' /V

Secondary blue input/Monochrome video

VIN

Vertical retrace input

76 IBM Enhanced Graphics Adapter

Internal

This signal is output to bit 4 (Disable Internal Video
Drivers) of the Miscellaneous Output Register.

V OUT

Vertical retrace output

Jl

This pin is connected to auxiliary jack 1 on the rear
panel of the adapter.

G'OUT

Secondary green output

B'OUT

Secondary blue output

B OUT

Blue output

G

Green input

B

Blue input

R OUT

Red output

BLANK

This is a composite horizontal and vertical blanking
signal from the CRTC.

FEAT 1

This signal is output to bit 6 (Feature Code 1) of
Input Status Register O.

G' /1

Secondary green/Intensity input

HIN

Horizontal retrace input from the CRTC

14MHZ

14 MHz signal from the system board

EXT OSC

External dot clock output

HOUT

Horizontal retrace output

IBM Enhanced Graphics Adapter 77

The following figure shows the layout and pin numbering of the
feature connector.
Signal Name

Signal Name

Gnd

- 1

+12V

--

J2

-

R'OUT
ATRS/L

-

GOUT

-

R'

2-

-

~

.......

J1

.-

G'OUT

-

B'OUT
BOUT

--

G
B

R
FEAT 1

-12V

ROUT

-

FEAT 0
FCO

S'N

-

BLANK
FC1

-

HIN

G'/I

VIN

-

--

14MHz

Internal

--

-

EXT OSC

-

HOUT

32 .-

+5V

VOUT

-

GND

: 31

"=

Feature Connector Diagram

"

78 IBM Enhanced Graphics Adapter

Specifica tions

System Board Switches
The following figure shows the proper system board DIP switch
settings for the IBM Enhanced Graphics Adapter when used with
the Personal Computer and the Personal Computer XT. The
switch block locations are illustrated in the Technical Reference
Manual "System Board Component Diagram". The Personal
Computer has two DIP switch blocks; the switch settings shown
pertain to DIP Switch Block 1. The Personal Computer XT has
one DIP switch block.
1

234

5

6

7

8

~DDDD~~DD
Switch Block (1 )

Note: The DIP switches must be set as shown whenever the
IBM Enhanced Graphics Adapter is installed, regardless of

display type. This is true even when a second display adapter
is installed in the system.

IBM Enhanced Graphics Adapter 79

Configuration Switches
The following diagram shows the location and orientation of the
configuration switches on the Enhanced Graphics Adapter.

Optional
Graphics Memory
Expansion Card

Off

On

80 IBM Enhanced Graphics Adapter

Configuration Switch Settings
The configuration switches on the Enhanced Graphics Adapter
determine the type of display support the adapter provides, as
follows:

Switch Settings for Enhanced Graphics Adapter
as Primary Display Adapter
Configuration
SWI SW2 SW3 SW4
On

Off

Off

On

Enhanced
Adapter
Color Display

Monochrome
Adapter

Color/Graphics
Adapter

Secondary

-

Secondary

-

40x25
Off

Off

Off

On

Color Display

80x25
On

On

On

Off

Enhanced Display
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Secondary

-

Off

On

On

Off

Enhanced Display
Hi Res Mode

Secondary

-

On

Off

On

Off

Monochrome

-

Secondary

40x25
Off

Off

On

Off

Monochrome

-

Secondary

80x25

IBM Enhanced Graphics Adapter 81

Switch Settings for Enhanced Graphics Adapter
as Secondary Display Adapter
Configuration
SWl SW2 SW3 SW4
On

On

On

On

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Adapter
Color Display

Monochrome
Adapter

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Adapter

Primary

-

Primary

-

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Off

On

On

On

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On

Off

On

On

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Primary

-

Off

Off

On

On

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Primary

-

On

On

Off

On

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-

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40x25
Off

On

Off

On

Monochrome

-

Primary

80x25

82 IBM Enhanced Graphics Adapter

Direct Drive Connector

9-Pin Direct
Drive Signal

Signal Name - Description

Direct
Drive
Display

Pin

Ground

1

Secondary Red

2

Primary Red

3

Primary Green

4

Primary Blue

5

Secondary Green/Intensity

6

Secondary Blue/Mono Video

7

Horizontal Retrace

8

Vertical Retrace

9

Enhanced
Graphics Adapter

IBM Enhanced Graphics Adapter 83

Light Pen Interface

P-2 Connector

P-2 Connector
Light Pen
Attachment .

Pin

+Light Pen Input

1

Not used

2

+Light Pen Switch

3

Ground

4

+5 Volts

5

12 Volts

6

84 IBM Enhanced Graphics Adapter

Enhanced
Graphics Adapter

Jumper Descriptions
Located on the adapter are two jumpers designated PI and P3.
Jumper P I changes the function of pin 2 on the direct drive
interface. When placed on pins 2 and 3, jumper PI selects ground
as the function of direct drive interface, pin 2. This selection is
for displays that support five color outputs, such as the IBM
Color Display. When PI is placed on pins I and 2, red prime
output is placed on pin 2 of the direct drive interface connector.
This supports the IBM Enhanced Color Display, which utilizes six
color outputs on the direct drive interface.
Jumper P3 changes the I/O address port of the Enhanced
Graphics Adapter within the system. In its normal position, (pins
1 and 2), all Enhanced Graphics Adapter addresses are in the
range 3XX. Moving jumper P3 to pins 2 and 3 changes the
addresses to 2XX. Operation of the adapter in the 2XX mode is
not supported in BIOS.
The following figure shows the location of the jumpers and
numbering of the connectors.

IBM Enhanced Graphics Adapter 85

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40

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Enhanced Graphics Adapter Sheet 11 of 11

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Graphics Memory Expansion Card Sheet 5 of 5

BIOS Listing

Vectors with Special Meanings
Interrupt Hex 42 - Reserved
When an IBM Enhanced Graphics Adapter is installed, the BIOS
routines use interrupt 42 to revector the video pointer.

Interrupt Hex 43 - IBM Enhanced Graphics Video
Parameters
When an IBM Enhanced Graphics Adapter is installed, the BIOS
routines use this vector to point to a data region containing the
parameters required for the initializing of the IBM Enhanced
Graphics Adapter. Note that the format of the table must adhere
to the BIOS conventions established in the listing. The power-on
routines initialize this vector to point to the parameters contained
in the IBM Enhanced Graphics Adapter ROM.

Interrupt Hex 44 - Graphics Character Table
When an IBM Enhanced Graphics Adapter is installed the BIOS
routines use this vector to point to a table of dot patterns that will
be used when graphics characters are to be displayed. This table
will be used for the first 128 code points in video modes 4, 5, and
6. This table will be used for 256 characters in all additional
graphics modes. See the appropriate BIOS interface for
additional information on setting and using the graphics character
table pointer.

IBM Enhanced Graphics Adapter 103

1
2

PAGE,120
TITLE
ENHA~CED GRAPH I CS ADAPTER BIOS
EXTRN
CGMN:NEAR, CGDDOT:NEAR, INT_1F_l:NEAR, CGMN_FDG:NEAR
EXTRN
END_ADDRESS: NEAR

3
4

5
6

THE
B I OS ROUT I NES ARE MEANT TO BE ACCESSED THROUGH
SOFTWARE INTERRUPTS ONLY.
ANY ADDRESSES PRESENT IN
THE LISTINGS ARE INCLUDED ONLY FOR COMPLETENESS,
NOT FOR REFERENCE.
APPL I CAT IONS WH I CH
REFERENCE
ABSOLUTE
ADDRESSES
WI TH I N
THE
CODE
SEGMENT
VIOLATE THE STRUCTURE AND DESIGN OF BIOS.

7
8

9

10
11

12
~

0000

13
14
15
16
17
18
19
20

WNR

EQU

.Iist
INCLUDE
VFRONT. INC
SUBTTl VFRONT. INC
PAGE

21
22
23
24
25
26
27
28
29
30
31
32

33
34
35
36
37
38
39
40
41
42
43

44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65

I NT 1 0 -------------.----------------------------------------------VIDEO 10
:
-THESE ROUTINES PROVIDE THE CRT INTERFACE
THE FOLLOW I NG FUNCTIONS ARE PROV IDEO:
(AH)~O
SET MODE (AL) CONTAINS MODE VALUE
AL AD

* o1
* 2

*

3
4
5
6
7

B8
B8
B8
B8
B8
B8
B8
BO

99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116

117
118
119
120
121

122
123
124
125
126

OF-DIM

DISPLAY

40X25
40X25
80X25
80X25
40X25
40X25
80X25
80X25

COLOR - BW
COLOR
COLOR - BW
COLOR
COLOR
COLOR - BW
COLOR - BW
MONOCHROME

40X25
80X25
80X25
80X25

COLOR
COLOR
MONOCHROME

MAX PGS

RESERVED

o

AO
E AO
F AO
10 AO

GRPHX
GRPHX
GRPHX
GRPHX

I NTERNAl USE
I NTERNAl USE

320X200
640X200
640X350
640X350

hi res

NOTE: HIGH BIT Al SET PREVENTS REGEN BUFFER CLEAR ON
MODES RUNN I NG ON THE COMBO V IDEO ADAPTER

***

(AH)" 1

(AH) =2

(AH)~3

(AH)~4

73
74
75
76

77

640X200
640X200
640X200
640X200
320X200
320X200
640X200
720X350

RESERVED
RESERVED

72

78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98

RES

RESERVED RESERVED -

66
67
68
69
70
71

NOTES

TYPE
ALPHA
ALPHA
ALPHA
ALPHA
GRPHX
GRPHX
GRPHX
ALPHA

(AH

)~5

(AH)~6

(AH

)~7

NOTE BW MODES OPERATE SAME AS COLOR MODES, BUT
COLOR BURST I S NOT ENABLED
SET CURSOR TYPE
(CH) ~
BITS 4-0 = START LINE FOR CURSOR
** HARDWARE WI Ll ALWAYS CAUSE Bl I NK
** SETTING BIT 5 OR 6 Will CAUSE ERRATIC
BLINKING OR NO CURSOR AT All
(Cl) "
BITS 4-0 " END LINE FOR CURSOR
SET CURSOR POS I T ION
(DH,Dl) ~ ROW,COlUMN
(0,0) IS UPPER lEFT
(BH) " PAGE NUMBER
READ CURSOR POSITION
(BH) = PAGE NUMBER
ON EX IT (DH, Dl) ~ ROW, COLUMN OF CURRENT CURSOR
(CH,Cl) " CURSOR MODE CURRENTLY SET
READ liGHT PEN POSITION
ON EXIT:
(AH) ~ 0 -- liGHT PEN SW I TCH NOT DOWN/NOT TR I GGERED
(AH) ~ 1 -- VALID LIGHT PEN VALUE IN REGISTERS
(DH,Dl) ~ ROW,COlUMN OF CHARACTER LP POSN
(CH) = RASTER LINE (0-199)
(CX) ~ RASTER LINE (O-NNN) NEW GRAPHICS MODES
(BX) ~ PIXEL COLUMN (0-319,639)
SELECT ACT I VE 0 I SPLAY PAGE
(Al) ~ NEW PAGE VALUE, SEE AH~O FOR PAGE INFO
SCROll ACTIVE PAGE UP
(AL) ~ NUMBER OF liNES, INPUT LINES BLANKED AT BOTTOM
OF WINDOW
Al ~ 0 MEANS BLANK ENTIRE WINDOW
(CH,Cl) ~ ROW,COlUMN OF UPPER lEFT CORNER OF SCROll
(DH,Dl) ~ ROW,COLUMN OF lOWER RIGHT CORNER OF SCROLL
(BH) ~ ATTRIBUTE TO BE USED ON BLANK liNE
SCROll ACT I VE PAGE DOWN
(ilL) ~ NUMBER OF liNES, INPUT LI NES BLANKED AT TOP
OF WI NDOW
Al ~ 0 MEANS BLANK ENTIRE WINDOW
(CH,Cl) ~ ROW,COlUMN OF UPPER lEFT CORNER OF SCROll
(DH,Dl) ~ ROW,COLUMN OF lOWER RIGHT CORNER OF SCROLL
(BH) ~ ATTRIBUTE TO BE USED ON BLANK LINE

CHARACTER HANDl I NG ROUT I NES
(AH) ~ 8 READ ATTR I BUTE/CHARACTER AT CURRENT CURSOR POS I T I ON
(BH) ~ DISPLAY PAGE
ON EXIT:
(AL)
CHAR READ
(AH) ~ ATTRIBUTE OF CHARACTER READ (ALPHA MODES ONLY)
(AH) = 9 WRITE ATTRIBUTE/CHARACTER AT CURRENT CURSOR POSITION
(BH) = DISPLAY PAGE
(CX) " COUNT OF CHARACTERS TO WR I TE
(Al) ~ CHAR TO WRI TE
(Bl)
ATTRIBUTE OF CHARACTER (AlPHA)/COlOR OF CHAR
(GRAPH I CS)
SEE NOTE ON WRITE DOT FOR BIT 7 OF Bl ~ 1.
(AH) = A WRITE CHARACTER ONLY AT CURRENT CURSOR POSITION
(BH) ~ DISPLAY PAGE
(CX) ~ COUNT OF CHARACTERS TO WR I TE
(AL) ~ CHAR TO WRITE
FOR READ/WR I TE CHARACTER INTERFACE WH I LE I N GRAPH I CS MODE, THE
CHARACTERS ARE FORMED FROM A CHARACTER GENERATOR IMAGE
MAINTAINED IN THE SYSTEM ROM.
ONLY THE 1ST 128 CHARS
ARE CONTAINED THERE.
TO READ/WRITE THE SECOND 128
CHARS, THE USER MUST INITIALIZE THE POINTER AT
INTERRUPT 1FH (lOCAT I ON 0007CH) TO PO I NT TO THE 1 K BYTE
TABLE CONTA I NI NG THE CODE PO I NTS FOR THE SECOND
128 CHARS (128-255).

=

=

FOR THE NEW GRAPH I CS MODES 256 GRAPH I CS CHARS ARE
SUPPl I ED I N THE SYSTEM ROM.
FOR WRITE CHARACTER INTERFACE IN GRAPHICS MODE, THE REPLICATION
FACTOR CONTAINED IN (CX) ON ENTRY WILL PROQUCE VALID
RESULTS ONLY FOR CHARACTERS CONTAINED ON THE SAME ROW.

104 IBM Enhanced Graphics Adapter

127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
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193
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230
231
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241
242
243
244
245
246
247

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

CONTINUATION TO SUCCEEDING LINES WILL NOT PRODUCE
CORRECTLY.
GRAPHICS INTERFACE
(AH) • B SET COLOR PALETTE
FOR USE IN COM PAT I Bill TY MODES
(BH) • PALETTE COLOR ID BEING SET (0-127)
(BL) • COLOR VALUE TO BE USED WITH THAT COLOR ID
NOTE: FOR THE CURRENT COLOR CARD, THIS ENTRY POINT
HAS MEANING ONLY FOR 320X200 GRAPHICS.
COLOR ID • 0 SELECTS THE BACKGROUND COLOR (0-15)
COLOR I D = 1 SELECTS THE PALETTE TO BE USED:
0 = GREEN( 1 )/RED( 2 )/BROWN( 3)
1 • CYAN( 1 )/MAGENTA( 2 )/WH I TE( 3)
IN 40X25 OR 80X25 ALPHA MODES, THE VALUE SET
FOR PALETTE COLOR 0 INDICATES THE
BORDER COLOR TO BE USED (VALUES 0-31,
WHERE 16-31 SELECT THE HIGH INTENSITY
BACKGROUND SET).
(AH) = C WRITE DOT
(BH)
PAGE
(DX)
ROW NUMBER
(CX) = COLUMN NUMBER
(AL) • COLOR VALUE
IF BIT 7 Of AL = 1, THEN THE COLOR VALUE IS
EXCLUSIVE ORoD WITH THE CURRENT CONTENTS OF
THE DOT
(AH) • D READ DOT
(BH) = PAGE
(DX)
ROW NUMBER
(ex)
COLUMN NUMBER
(AL) RETURNS THE DOT READ

=
=

=
=

ASCII

TELETYPE ROUTINE FOR OUTPUT
(AH) = E

(AH)

WRITE TELETYPE TO ACTIVE PAGE
(AL) • CHAR TO WRITE
(BL) = FOREGROUND COLOR I N GRAPH I CS MODE
NOTE -- SCREEN WIDTH I S CONTROLLED BY PREV I OUS MODE SET

=F

CURRENT VIDEO STATE
RETURNS THE CURRENT VIDEO STATE
(AL)
MODE CURRENTLY SET
(SEE AH'O FOR EXPLANATION)
(AH) • NUMBER OF CHARACTER COLUMNS ON SCREEN
(BH)
CURRENT ACTIVE DISPLAY PAGE

=
=

(AH) •

10

SET PALETTE REGISTERS

(AL) • 0
SET INDIVIDUAL PALETTE REGISTER
BL = PALETTE REG I STER TO BE SET
BH = VALUE TO SET
AL •
8H •

1
SET OVERSCAN REG I STER
VALUE TO SET

AL • 2
SET ALL PALETTE REG I STERS AND OVERSCAN
ES:DX POINTS TO A 17 BYTE TABLE
BYTES 0 - 15 ARE THE PALETTE VALUES, RESPECTIVELY
BYTE 16 I S THE OVERSCAN VALUE
AL· 3

TOGGLE INTENSIFY/BlIN·KING SIT
ENABLE I NTENS I FY
ENABLE BLINKING

BL - 0
BL - 1

(AH) • 11
CHARACTER GENERATOR ROUTINE
note: this cs II wi II initiate 8 mode set, completely
C
resetting the video environment but maintaining
C
the regen burt'e r.
C
C
AL • 00
USER ALPHA LOAD
C
ES:BP - POINTER TO USER TABLE
C
CX
- COUNT TO STORE
C
OX
- CHARACTER OFFSET I NTO TABLE
C
BL
- BLOCK TO LOAD
C
BH
- NUMBER OF BYTES PER CHARACTER
C
AL • 01
ROM MONOCHROME SET
C
BL
- BLOCK TO LOAD
C
AL • 02
ROM 8X8 DOUBLE DOT
C
BL
- BLOCK TO LOAD
C
AL = 03
SET BLOCK SPEC I F I ER
C
BL
- CHAR GEN BLOCK SPEC I F I ER
C
03-02
ATTR BIT 3 ONE,
CHAR GEN 0-3
C
Dl-DO ATTR BIT 3 ZERO, CHAR DEN 0-3
C
NOTE: WHEN USING AL = 03 A FUNCTION CALL
C
AX
1000H
C
BX
0712H
C i S RECOMMENDED ,0 SET THE COLOR PLANES
C
RESULTING IN 512 CHARACTERS AND EIGHT
C
CONSISTENT COLORS.
C
C
NOTE: THE FOLLOW·ING INTERFACE (AL.1X) IS SIMILAR IN FUNCTION
C
TO (AL'OX) EXCEPT THAT:
C
- PAGE ZERO MUST BE ACTIVE
C
- POI NTS (BYTES/CHAR) WI LL BE RECALCULATED
C
- ROWS WI LL BE CALCULATED FROM THE FOLLOW I NG:
C
INT((200 OR 350) I POINTS] - 1
C
- CRT LEN WI LL BE CALCULATED FROM:
C
(ROWS + 1) * CRT_COLS * 2
C
- THE CRTC WI LL BE REPROGRAMMED AS FOLLOWS:
C
R09H. POINTS - 1
MAX SCAN LINE
C
R09H done on t yin mode 7
C
ROAH • PO I NTS - 2
CURSOR START
C
ROBH
0
CURSOR END
C
R12H •
VERT DISP END
C
((ROWS + 1) * POINTS] - 1
C
R14H • POINTS
UNDERLINE LOC
C
C
THE ABOVE REGISTER CALCULATIONS MUST BE CLOSE TO THE
C
ORIGINAL TABLE VALUES OR UNDETERMINED RESULTS WnL
C
OCCUR.
C
C
NOTE: THE FOLLOWING INTERFACE IS DESIGNED TO BE
C
CALLED ONLY IMMEDIATELY AFTER A MODE SET HAS
C
BEEN ISSUED. FAILURE TO ADHERE TO THIS PRACTICE
C
MAY CAUSE UNDETERMINED RESULTS.
C
C
AL • 10
USER ALPHA LOAD
C
ES: BP - PO I NTER TO USER TABLE
C
CX
- COUNT TO STORE
C
OX
- CHARACTER OFFSET I NTO TABLE
C
BL
- BLOCK TO LOAD

=
=

=

248

C

249
250
251
252

C
C
C
C

BH

AL •

11

AL •

12

-

NUMBER OF BYTES PER CHARACTER

ROM MONOCHROME
- BLOCK TO
ROM 8X8 DOUBLE
BL
- BLOCK TO
BL

SET
LOAD
DOT
LOAD

IBM Enhanced Graphics Adapter 105

253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
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275
276
277
278
279
280
281
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283
284
285
286
287
288
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291
292
293
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297
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302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
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326
327
328
329
330
331
332
333
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336
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340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

NOTE: THE FOLLOWING INTERFACE IS DESIGNED TO BE
CALLED ONLY IMMEDIATELY AFTER A MODE SET HAS
BEEN ISSUED. FAILURE TO ADHERE TO THIS PRACTICE
MAY CAUSE UNDETERM I NED RESULTS.
AL = 20
AL = 21

BL = 0
BL = I
BL = 2
BL = 3
AL = 22
BL
AL = 23
BL
AL = 30

ROM 8
ROM 8
-

(AH) = I 2

USER
DL - ROWS
14 (OEH)
25 (19H)
43 (2BH)

X 14 SET
ROW SPECI FI ER
X 8 DOUBLE DOT
ROW SPECI FI ER

INFORMATION
CX
DL
- 0
ES: BP
BH
- I
ES: BP
BH
- 2
ES:BP
BH
- 3
ES: BP
BH
- 4
ES: BP
BH
- 5
ES: BP
BH

- POI NTS
- ROWS
RETURN
- PTR TO
RETURN
- PTR TO
RETURN
- PTR TO
RETURN
- PTR TO
RETURN
- PTR TO
RETURN
- PTR. TO

CURRENT I NT I FH PTR
TABLE
CURRENT I NT 44H PTR
TABLE
ROM 8 X 14 PTR
TABLE
ROM DOUBLE DOT PTR
TABLE
ROM DOUBLE DOT PTR (TOP)
TABLE
ROM ALPHA ALTERNATE 9X14
TABLE

ALTERNATE SELECT

BL = 10

RETURN EGA I NFORMAT I ON
BH = 0 - COLOR MODE I N EFFECT <3>
I - MONOC MODE I N EFFECT <3>
BL = MEMORY VALUE
00-064K
01-128K
1 0 - 192K
1 1 - 256K
CH = FEATURE BITS
CL = SWITCH SETTING

BL = 20

SELECT ALTERNATE PRINT SCREEN ROUTINE

(AH) = 13

WR I TE STR
ES:BP
CX
OX
BH

I NG
- POINTER TO STRING TO BE WRITTEN
- CHARACTER ONLY COUNT
- POS I T I ON TO BEG I N STR I NG, I N CURSOR
TERMS
- PAGE NUMBER

AL = 0
BL
- ATTRIBUTE
STRING - (CHAR, CHAR, CHAR,
CURSOR NOT MOVED

... )

BL
- ATTR I BUTE
STR I NG - (CHAR, CHAR, CHAR,
CURSOR
I S MOVED

••• )

AL = 1

AL = 2
STRING - (CHAR, ATTR, CHAR, ATTR,
CURSOR NOT MOVED

••• )

STR I NG - (CHAR, ATTR, CHAR, ATTR,
CURSOR
I S MOVED

••• )

AL = 3

NOTE : CHAR RET, LINE FEED, BACKSPACE, AND BELL ARE
TREATED AS COMMANDS RATHER THAN PRINTABLE
CHARACTERS.
--- -- -- -- - -- - -- -- - - -- - -- - -- - - - - --- - --- - - ---- - - -- - --- - --- - -- - --- - - ------SRLOAD

MACRO
SEGREG, VALUE
I FNB 
IFIDN ,
SUB
OX,DX
ELSE
MOV
OX, VALUE
ENOl F
ENOl F
IF WNR
MOV
AH,08FH
15H
I NT
ENOl F
MOV
SEGREG, OX
ENOM

WIN

MACRO
IF WNR
MOV
I NT
ENOl F
IN
ENDM

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

USER GRAPHICS CHARS
INT 01FH (8X8)
ES:BP - POINTER TO CSER TABLE
USER GRAPH I CS CHARS
ES:BP - POINTER TO USER TABLE
CX
- PO I NTS (BYTES PER CHARACTER)
BL
- ROW SPEC I F I ER

WOUT

WLXS

MACRO
IF WNR
PUSH
MOV
I NT
ENOl F
OUT
IF WNR
POP
END IF
ENDM

AH,08EH
15H
AL,DX

AX
AH,08DH
15H
OX,AL

MACRO
SEGREG, TARGREG, VALUE
IF
WNR
PUSH
OX
MOV
TARGREG, VALUE
SRLOAO SEGREG, VALUE+2
POP
OX
ELSE
L&SEGREG
TARGREG, VALUE

106 IBM Enhanced Graphics Adapter

0000
0014
0014
0040
0040
007C
007C
0108
0108
010C
010C
0410
0410
0410

0449
0449
044A
044C
044E
0450

7???

????

08 {
????

0460
0462
0463
0465
0466

....
..
....
??

0472

0472
0484
0484

0485
0487

0488

04A8
04A8

????
..
????
..

??

379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476

477
478
479
480
4'81
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
'C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

ENDIF
ENDM
; ----- LOW MEMORY SEGMENT
SEGMENT AT
ORG
005H*4
LABEL
ORG
010H*4
LABEL
VIDEO
ORG
01 FH*4
LABEL
EXT_PTR
ABSO

INT5_PTR

ORG
PLANAR_VIDEO

042H*4
LABEL

; PR I NT SCREEN VECTOR
DWORD

; REVECTORED 10H*4
DWORD
;. GRAPH I C CHARS 0-255

043H*4
LABEL

DWORD

ORG

0410H
labe I
OW

byte

equip_loW'

EQUIPJLAG

; GRAPH I C CHARS 128-255

DWORD

ORG
GRX_SET

; V IDEO I/O VECTOR

DWORD

?

;----- REUSE flAM FROM PLANAR BIOS
ORG
CRT MOOE
CRT-COLS
CRT-LEN
CRT-START
CURSOR_POSH

449H
DB
DW
DW
DW
OW

CURSOR_MODE
ACT IVE_PAGE
ADDR 6845
CRT MODE SET
CRT::PALETTE

DW
DB
DW
DB
DB

ORG
RESET FLAG
ORG
ROWS
DB
POINTS OW

0472H
DW
0484H

INFO
INFO

?
8 DUP(?)

ROWS ON THE SCREEN
BYTES PER CHARACTER

DB
D7
D6
05
D4
D3
02
Dl
DO

-

HIGH BIT OF MODE SET. CLEAR/NOT CLEAR REGEN
MEMORY D6 D5 = 0 0 - 064K
0 1 - 128K
MEMORY
1 0 - 192K
1 1 - 256K
RESERVED
ega active monitor (0), ega not active (1)
wa it fa r d i sp I ay ena b I e (1)
EGA HAS A MONOCHROME ATTACHED (1)
set c_type emulate active (0)

INFO 3
- 07-04
D3-DO

FEATURE BITS
SWI TCHES
04a8h
labe I

dword

save_ptr Is 8 pointer to a table 8S described as follows:

dword-2
dword-3
dword-4

video parameter table pointer
dynam i c save 8 rea po i nte r
a Ipha mode Buxi I isry char gen pointer
graphics mode BUX! Ilary char gan pointer

dword::5
dword 6
dword::l

reserved
reserved
reserved

dword 1

Parameter Table Pointer
Initial ized to BIOS EGA parameter table.
Th i s va I ue MUST ex 1st.

Parameter Save area pointer
Initialized to 0000:0000, this value is optional.
When non-zero, this pointer wi II be used as pointer
to a RAM area where certain dynamic values are to
be saved. When in EGA operation this RAM area wi II
hold the 16 EGA palette regist80' values plus
the overscan value in bytes 0-16d respectively.
At least 256 bytes must be allocated for this area.
Alpha Mode Auxi I iary pointer
In i t i a I i zed to 0000: 0000, th i s va I ue is opt i ana I .
When non-zero, this pointer is used as a pointer
to a tables described as follows:
byte
byte
'Word
'Word
dword
byte
byte

bytes/cha racter
block to load, should be zero for normal
ope rat ion
count to store, should be 256d for normal
operation
character offset, should be zero for normal
operat ion
pointer to a font table

1~s~};¥a~~: ~~~~mum

calculated value wi II be
used, else th i s va I ue wi I I be used
consecutive bytes of mode values for which
this font description is to be used.
The end of this stream is indicated by 8
byte code of 'FF'

Graphics Mode Auxi I iary pointer
Initialized to 0000:0000, this value is optional.
When non-zero, this pointer is used 8S a pointer
to a tables described as follo'Ws :
byte
word
dword
byte

displayable rows
bytes per character
pointer to a font table
consecutive bytes of mode values for 'Which
th i s font desc r i pt jon is to be used.
The end of this stream is indicated by a
byte code of IFF'

IBM Enhanced Graphics Adapter 107

ORG
STATUS_BYTE
ENDS
ABSO

0500H
DB

PORT B
TIMER

EQU
EQU

61H
40H

; ----- EQUATES fOR CARD PORT ADDRESSES
SEQ_ADDR
SEQ_DATA
CRTC ADDR
CRTC-ADDR B
CRTC::DATAGRAPH 1 POS
GRAPH-2-POS
GRAPH::ADDR
GRAPH DATA
M I SC OUTPUT
I N_STAT_O
I NPUT_STATUS_B
INPUT_STATUS
ATTR READ
ATTR::WRITE

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

OC4H
OC5H
OD4H
OB4H
OD5H
OCCH
OCAH
OCEH
OCfH
OC2H
OC2H
OBAH
ODAH
ODAH
OCOH

; ----- EQUATES fOR ADDRESS REGISTER VALUES
S RESET
S-CLOCK
S-MAP
S-CGEN
S::MEM

EQU
EQU
EQU
EQU
EQU

OOH
01H
02H
03H
04H

C HRZ TOT
C-HRZ-DSP
C-STRT HRZ BLK
C-END iiRZ BLK
C-STRT HRZ SYN
C-END HRZ 5YN
C-YRT-TOTC-OYERFLOW
C-PRE ROW
C-MAX-SCAN LN
C-CRSR START
C-CRSR-END
C-STRT-HGH
C-STRT-LOW
C-CRSR-LOC HGH
C-CRSR-LOC-LOW
C-YRT 5YN 5TRT
C-LGHT PEN HGH
C-YRT 5YN END
C-LGHT PEN LOW
C-YRT DSP END
C-OFF5ET C-UNDERlN lOC
C-STRT VRT BlK
C-END VRT BLK
C-MODE CNTL
C-lN caMP

EQU
EQU
EQU
EQU
[QU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
tQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

OOH
01H
02H
03H
04H
05H
06H
07H
08H
09H
OAH
OBH
OCH
ODH
OEH
OfH
10H
lOH
11H
11H
12H
13H
14H
15H
16H
17H
18H

G SET RESET
G-ENBL SET
G-ClR COMP
G::DATA_ROT
G READ MAP
G-MODC
G-M I SC
G::COLOR
G_BI T_MASK

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

OOH
01H
02H
03H
04H
05H
06H
07H
08H

P MODE
P-OYERSC
P:::CPlANE
P_HPEl

EQU
EQU
EQU
EQU

10H
l1H
12H
13H

SUBTTl
; ----- CODE SEGMENT
SEGMENT PUBL I C

CODE

YPOST. INC
INCLUDE
SUBTTl YPOST. INC
PAGE

;-- ...

--

POST
ASSUME
ORG
DB
DB
DB

CS: CODE, OS: ABSO
OH
055H
OAAH
020H

108 IBM Enhanced Graphics Adapter

0003
0003
0005
0009

0026

EB
32
36
30
4F
48
20
31
38

29
34
33
20
50
54
31
31
33

002E
002E
0030
0032
0033
0035
0036
0038
003A

B6
B2
EC
B2
EC
B2
BO
EE

03
OA

003B
0030
003F
0040
0046
004A
0050
0056
005C
0060
0066
006A
0070
0074

2B
8E
FA
C7
8C
C7
C7
C7
8C
C7
8C
C7
8C
FB

02
OA

0075
007A
0070
0081
0084
0088
008C
008F
0092
0092
0093

C6
E8
88
E8
08
8A
E8
E9

30
32
28
59
20
39
2F

30
30
43
52
49
38
30

30
29
49
42
33
33

33
43
47
40
2F

BA
CO
00

06
OE
06
06
06
DE
06
OE
06
OE

0040
0042
0108
010A
04A8
04M
007C
007E
010C
010E

06 0487
009C R
1 E 0488
0001 R
06 0488
1 E 0488
00F6 R
0247 R

CB

0093
0093
0094
0095

EE
50
58

0096
0097
0099
009B
009C

EC
24 10
DO E8
C3

009C
009C
009E
OOAO
00A2

B6
B2
B2
BO

03
C2
C2
01

00A4

EE

00A5
00A7
OOM
OOAC
OOAE
OOBO

BO
E8
DO
DO
DO
8A

00
0093 R
E8
E8
E8
08

00B2
00B4
00B7
00B9
OOBB

BO
E8
DO
DO
OA

09
0093 R
E8
E8
08

OOBD
OOBF
00C2
00C4

BO
E8
DO
OA

05
0093 R
E8
08

00C6
00C8
OOCB

BO 01
E8 0093 R
OA 08

OOCD
DODO
0001

80 E3 OF
C3

0001
0001
0003
0005

B6 03
B2 BA
BO 01

0007
0008

EE
B2 OA

OOoA
OOoB

EE
B2 C2

DODD
OOOE
OOEO

EC
24 60
DO E8

R
R
R
R
R
R
R
R
R
R

OCDA R
F065
FOOD
010F R
0000 E
0000 E

R 04
R
R
R

631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C+
C+
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C+
C
C
C
C+
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C+
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C+
C
C
C+
C
C
C+
C
C

1 1 1 0 - RESERVEO
1 1 1 1 - RESERVED
;----- SETUP ROUTINE FOR THIS MODULE
FAR
PROC
SHORT
L1
'2400'
'6320030 (C)COPVRIGHT IBM 1983'

VIDEO.SETUP
JMP
DB
DB

DB

'11/03/83'

;----- SET UP VIDEO VECTORS

L1:

dh,3
d I, Input_status

may
In

a I,dx
d I, I nput_status_b
a I,dx

in
may
may
out

dl,attr_wrlte
a 1,0
dx,al

SRLOAO
SUB
HOV
Cli
HOV
HOV
HOV
HOV
HOV
HOV
HOV
HOV
MOV
HOV
STI

05,0
OX,OX
DS,DX
WORD
WORD
WORD
WORD
WORD
WORD
WORD
WORD
WORD
WORD

PTR
PTR
PTR
PTR
PTR
PTR
PTR
PTR
PTR
PTR

VIDEO,OFFSET COHBO.VIDEO
VIDEO+2, CS
PLANAR_VIDEO,OF065H
PLANAR_VIOEO+2,OFOOOH
saYe.PTR, OFFSET saye_tb I
saye_PTR+2, CS
EXT_PTR, OFFSET INT.1F.l
EXT .PTR+2, CS
GRX.SET, OFFSET CGDDOT
GRX.SET+2, CS

; ----- POST FOR COMBO VIDEO CARD
may
CALL
MOV
CALL
OR
HOV
CALL
JMP

info, 00000 100B
RO_SWS
I NFO_3, BL
F BTS
INFO_3,AL
BL,INFO.3
HK.ENV
POST

SKI P:

RET
V IDEO_SETUP
POR.l

POR_l

ENDP

PROC
WOUT
OUT
PUSH
POP
WIN
IN
AND
SHR
RET
ENOP

NEAR
DX,AL
AX

AX
AL, OX
AL,010H
AL,l

; ----- READ THE SWI TCH SEn I NGS ON THE CARD
RO_SWS

PROC
ASSUME
may
HOV
may

NEAR
DS:ABSO
dh,3
DL,IN_STAT.O

d I, mj sc_output
81, ,

wout
OUT

DX,AL

;----- COULD BE 0,4,8,C

Ro_SWS

MOV
CALL
SHR
SHR
SHRMOVf

AL,ODH
POR 1
AL. T
AL,1
AL,l
BL,AL

MOV
CALL
SHR
SHR
OR

AL,9
POR_l
AL,l
AL,l
BL,AL

MOV
CALL
SHR
OR

Al,5
POR_l
Al,l
Bl,Al

MOV
CALL
OR

Al,l
POR 1
Bl,AL

AND
RET
ENoP

Bl,OFH

;----- OBTAIN THE FEATURE BITS FROM DAUGHTER CARD
F.BTS

PROC
may
MOV
MOV
WOUT
OUT
MOV
WOUT
OUT
MOV
WIN
IN
AND
SHR

NEAR
dh,3
Dl,OBAH
Al,l
DX,Al
Dl,OoAH

DX,AL
Dl,IN_STAT_O

READ fEATURE BITS

Al, OX
Al,060H
Al,l

IBM Enhanced Graphics Adapter 109

00E2
00E4
00E6

8A 08
B2 BA
80 02

00E8
00E9

EE
82 OA

00E8
OOEC

EE
82 C2

OOEE
OOH
OOFl
00F3
00F5
00F6

EC
24 60
DO EO
OA C3
C3

00F6
00F6
00F8
00F8
OOFD
OOFE
0100
0102
0103
0106
0108
010A

2A FF
80 E3 OF
01 E3
52
B6 03
8A E6
5A
80 E4 01
FE C4
F6 04
2E: FF A7 012B R

010F
010F
0111
0113
0115
0117
0119
011B
0110

071A R
COOO
0000
0000
0000
0000
0000
0000

011F
0121
0123
0125
0127
0129

0000
0000
0000
0000
0000
0000

012B
012B
0120
012F
0131
0133
0135
0137
0\39

0176
0181
0181
018C
0197
01A8
01BF
01CA

013B
0130
013F
0141
0143
0145
0147
0149

01CA
0105
OlEO
01 F4
0207
0207
0207
0207

014B
014B
0150
0155
0158
015A
015B

80 26 0410 R C F
80 OE 0410 R 10
B8 0001
co 10
C3

015B
015B
0160
0165
0168
016A
016B

80
80
88
CO
C3

016B
016B
0170
0173
0175
0176

80 OE 0410 R 30
B8 0007
CO 10
C3

0176
0176
017A
0170
0180
0181
0181
0181
0185
0188
0188
018C
018C
0190
0193
0196
0197
0197
0199
0198

R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R

26 0410 R C F
OE 0410 R 20
0003
10

20 26 0487 R
E8 0148 R
E8 0168 R
C3
20 26 0487 R
E8 0158 R
E8 0168 R
C3
20 26 0487 R
E8 0158 R
E8 0168 R
C3
B6 03
B2 C2
BO 00

0190
019E
01AO
01A4
01A7
01AA
01A6
01A6
01AD
OlAF

EE
F6
08
E8
E8
C3

0161

EE

04
26 0487 R
0166 R
0146 R

B6 03
62 C2
60 00

757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882

C
C
C
C
C+
C
C
C+
C
C
C+
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

F_8TS

BL,AL
OL,OBAH
AL,2
DX,AL
DL,OOAH
DX,AL
OL, I N_STAT_O

READ FEATURE 81TS

AL,OX
AL,060H
AL,l
AL,BL

;----- ESTA8L1SH THE VIDEO ENVIRONMENT, KEYED OFF OF THE SW ITCHES
MK_ENV

PROC
ASSUME
SU8
AND
SAL
PUSH
MOV
POP
AND
INC
NOT
JMP

NEAR
OS:ABSO
8H,8H
8L,OFH
8X,1
OX
dh,3
AH,DH
OX
AH,l
AH
AH
WORD PTR CS: [BX + OFFSET T5 J

d""
d""
d""
d""
d""
d""
d""
d""

offset
OcOOOh
0
0
0
0
0
0

mov

labe I

save_tb I

dW'ord
v I deD_p8 rms

parms
parms
pa I save a rea
pa I save a rea
a I pha tab les
a I pha tab les
graphics tables
graphics tables

d""
d""
d""
d""
dw
dw
T5

LABEL

ow
ow
ow

OW
OW

ow

OW

ow

c

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C+
C
C
C
C
C
C
C
C
C
C
C+

MOV
MOV
MOV
WOUT
OUT
MOV
WOUT
OUT
MOV
WIN
IN
AND
SHL
OR
RET
ENOP

ow
ow
ow
OW
OW

ow

OW
OW
ENV_X

PROC
and

or

ENV_X
ENV_O

MOV
INT
RET
ENOP
PROC
and

or

ENV_O
ENV_3

ENV_3

MOV
INT
RET
ENOP
PROC

or
MOV
INT
RET
ENOP

WORO
OFFSET
OFFSET
OFFSET
OFFSET
OFFSET
OFFSET
OFFSET
OFFSET

PST 0
PST-l
PST-2
PST-3
PST-4
PST::5
PST 6
PST::7

OFFSET
OFFSET
OFFSET
OFFSET
OFFSET
OFFSET
OFFSET
OFFSET

PST 8
PST::9
PST_A
pst B
PST-OUT
PST-OUT
PST-OUT
PST::OUT

NEAR
equip_low,Ocfh
equip_lo.... ,010h
AX,lH
10H

SET 40X25 COLOR ALPHA

NEAR
equ i p_low, Ocfh
equip_low,020h
AX,03H
10H

SET 80X25 COLOR ALPHA

NEAR
equip_lo..... ,030h
AX,07H
10H

SET MONOCHROME ALPHA

PST_O:
AND
CALL
CALL
RET

INFO,AH
ENV X
ENV::3

ANO
CALL
CALL
RET

INFO,AH
ENV 0
ENV::3

AND
CALL
CALL
RET

INFO,AH
ENV 0
ENV::3

PST 1:
PST::2:

PST_3:

PST_4:
dh,3
d I, mi sc_output
a I ,0

wout
OUT
NOT
OR
CALL
CALL
RET

OX,AL
AH
INFO,AH
ENV 3
ENV::X

PST_5:

mov
..... out
OUT

dh,3
d I. mi sc_output
a 1,0
DX,AL

110 IBM Enhanced Graphics Adapter

01B2
01B4
0188
0188
018E
018f
018f
01C3
01C6
01C9
01CA
01CA
01CA
01CE
0101
0104
0105
0105
0109
OlOC
01Df
OlEO
OlEO
01E2
01E4

f6
08
E8
E8
C3

20 26 0487 R
E8 0168 R
E8 0148 R
C3
20 26 0487 R
E8 0168 R
E8 0158 R
C3
20 26 0487 R
E8 0168 R
E8 0158 R
C3
86 03
82 C2
BO 00

OlE6
01[7
01 E9
OlEO
01 fO
01f3
01f4
01f4
OH6
OH8

EE
f6
08
E8
E8
C3

OHA
OH8
OHD
0201
0204
0207
0207
0208

EE
f6
08
E8
E8

0208
0208
0209
020C
020E
020f
0212
0214
0215
0216
0219
021A
021 B
021E
0220
0221
0223
0226
0226
0228
0229
022A
022A
0220
022E
022f

022f
022f
0230
0232
0234
0235
0236

04
26 0487 R
0168 R
0158 R

04
26 0487 R
014B R
0168 R

86 03
B2 C2
BO 00
04
26 0487 R
0158 R
0168 R

883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916

917
918
919

920
921
922

923
924
925

926

C3

927
928
929
930
931
932
933
934
935
936

937
53
88
88
50
E8
8B
58
50
E8
58
50
E8
3B
58
75
EB

007f
f8
022f R
fO
0239 R
022f R
C7
03
05 90

33 CO
5B
C3
B8 0001
58
C3

52
8B DO
BO OE
EE
42
EC

938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960

961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976

977
978
0237
0238
0239

979

5A
C3

980
981
982
983
984
985
986
987
988
989
990
991

0239
0239
023A
023B
0230
023f
0241

50
52
8B
B4
BO
E8

0244
0245
0246
0247

5A
58
C3

0247

992
00
OE
7f
0018 R

993
994
995

996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C+
C
C
C
C
C
C
C
C
C
C
C+
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

NOT
OR
CALL
CALL

AH
I NfO,AH
ENV_3
ENV_O

AND
CALL
CALL

INfO,AH
ENV_3
ENV_X

RET

PST_6:

RET

PST 7:
PST::8:
AND
CALL
CALL
RET
INfO,AH
ENV_3
ENV_O

AND
CALL
CALL
RET

dh,3

d I , mi sc_output
.1,0
"PIout

OUT
NOT
OR
CALL
CALL
RET

DX,AL
AH
INfO,AH
ENV X
ENV::3

may
may

d I • mi sc_output
.1,0

dh,3

wout
OUT
NOT
OR
CALL
CALL

DX,AL
AH
INfO,AH
ENV 0
ENV::3

PST OUT:
RET
MK_ENV ENDP

; -~ ~~ S-RO~~~ NE -~ ES~S -~~ E- eR~ -e~RD -~ N~ ERN~L -DA ~ A-~~s -AND -~ N-A -L~;:; ~ ~ED- ---~
; WAY TESTS THE CRTC V IDEO CH I P BY WR I T I NG/READ I NG fROM CURSOR REG I STER :
:
; CARRY I S SET I f AN ERROR I S fOUND
; REGISTERS BX,SI,ES,DS ARE PRESERVED.

:-~~? ~:~ ~~: -~~::~: ~~- ~~~ -~~~ ~~~~~: ---------------------------------------

CO PRESENCE TST
PUSH
MOV
mov
PUSH
CALL
MOV
POP
PUSH
CALL
POP
PUSH
CALL
CMP
POP
JNZ
JMP
NOT PRESENT:
XOR
POP
RET

PROC
NEAR
BX
BX,07fH
d j • bx
AX
RO CURSOR
SI:-AX
AX
AX
WR CURSOR
AXAX
RD CURSOR
AX:-DI
AX
NOT PRESENT
TST::EX

SAVE OR I G I NAL VALUE
RECOVER PORT ADDRESS
SAVE PORT ADDRESS
WR I TE CURSOR
RECOVER PORT ADDRESS
SAVE PORT ADDRESS
READ IT BACK
SAME?
EXIT I f NOT EQUAL
SET NOT PRESENT

AX,AX
BX

AX,l
MOV
BX
POP
RET
CD_PRESENCE_ TST ENDP

-_ -_ -_

· --

SAVE BX
INITIAL WORD PATTERN BYTE
SAVE PORT ADDRESS

SET PRESENT ON EX I T
RESTORE ax

-_ -_ -_

--_ ---_

-- - -- - - - - ... .... ...... ...... ....... ..
..
............ _.. -; MODULE NAME RD_CURSOR
;
READ CURSOR POS I T I ON I ADDRESS J (fROM CRTe J TO AX

-_

; REGISTER AX IS MODifiED.
......
.. ..............
.....
... -- --- ... -- ----flO CURSOR
PROC NEAR
PUSH
OX
MOV
DX,AX
MOV
AL, C_CRSR_LOC_HGH
OUT
DX,AL
INC
OX
IN
AL,DX

· -_ -_

-- -- --_

-_ .. --- -_ .... _..... -_ ..... ...

--_ ... ---_ ... -- -- -- -_ ........... --_ ... -- ............... -;

SAVE REGS USED

RETURN WITH CURSOR POS I N AX
RESTORE REGS USED

OX
ENDP

-_ -_

· -_

...... ........................ ..... ..............
; MODULE NAME WR_CURSOR
;
WR I TE CURSOR POS I T I ON

-_ ...... -_ ......... -_ ................................. -- -_ ...... -- -- - .. -_ ............ --- -----I ADDRESS J

(TO CRTC) WITH CONTENTS Of AX

; ALL REG I STERS PRESERVED
~R= e~RSOR

-------PRoe -NEAR----- -------------------------- ----------------:
SAVE REGS USED

PUSH
PUSH
MOV
MOV
MOV
CALL

AX
OX
DX,AX
AH, C_CRSR_LOC_HGH
AL,07fH
OUT_OX

CURSOR LOCATION HIGH
TEST VALUE

INDEX

RETURN WI TH CURSOR POS I N AX
RESTORE REGS USED
POP

POP
RET
WR_CURSOR

OX
AX
ENDP

POST:
I NIT I AL I ZE AND START CRT CONTROLLER (6845)
ON COLOR GRAPH I CS AND MONOCHROME CARDS
TEST V IDEO READ/WR I TE STORAGE.

IBM Enhanced Graphics Adapter 111

0247
024A
024F
0251
0254
0257
025A
025C
025F
025F
0261
0263
0263
0266
0269
026C
026E
0271
0271
0273
0273
0274
0277
027A
0270
027F
0282
0284
0286
0288
02BA
028C
028C

E8
F6
75
B8
E8
30
74
E9

0001 R
06 0487 R 02
12
03B4
0208 R
0001
03
031A R

B4 30
EB 10
B8
E8
30
74
E9

0304
020B R
0001
03
031A R

B4 20
50
BB
BA
B9
BO
80
74
B7
B2
B5
FE

BOOO
03B8
1000
01
FC 30
08
B8
08
40
C8

EE

0280

8B 2E 0472 R

0291
0295
0297
0299

81
8E
74
8E

029B
029E

E8 02E2 R
75 2E

02AO
02AO
02A 1
02A2
02A5
02A7
02AA

02AC
02AD
02AE
02Bl
02B4
02B6
02BB
02BB
02BA
02BA
02BC
02BC
02BD
02BF
02Cl
02C3
02C5
02C5
02C7
02C7
02CB
02CA
02CC
02CE
02CE
0201
0204
0206
0206
0208
020A
02DC
020C
0200

02DF
02DF
02E2
02E2
02[3
02E5
02EB

FD 1234
C3
07
DB

58
50
B8 7020
2B FF
B9 0028
F3/ AB

58
50
80
BA
74
B2

FC 30
03BA
02
OA

B4 08
2B C9
EC
22
75
E2
EB

C4
04
F9
09

2B C9
EC
22 C4
74 OA
E2 F9
BA 0102
E8 06CB R
EB 06
Bl 03
02 EC
75 DE
58
EB 3B

B9 4000
FC
8B 09
B8 AAAA
BA FF55

1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
lllB
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

c

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

c

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

e

C
C
C
C
C
C
C
C
C

OESCR I PT ION
RESET THE VIDEO ENABLE SIGNAL.
SELECT ALPHANUMERIC MODE, 40
25, B lie W.
READ/WRITE DATA PATTERNS TO STG. CHECK STG
AOORESSAB I L I TY.

*

OS: ABSO, ES: ABSO
ODS

ASSUME
CALL

test

Info,2

JNZ
MOV
CALL
CMP
JE
JMP

COLOR_PRESENCE_ TST
AX,03B4H
CO_PRESENCE_TST

MOV

AH,30H

jmp

short

AX,1
CONT1
POD14

CONTl :
; MONOCHROME CARD INSTALLED

eOLOR_PRESENCE_ TST:
MOV
AX,0304H
CALL
CO_PRESENCE_TST
CMP
AX,l
JE
CONT2
P0014
JMP
CONT2:
MOV
AH,20H
OVER:
PUSH
AX
MOV
BX,OBOOOH
MOV
OX,3B8H
MOV
eX,4096
AL,l
MOV
CMP
AH,30H
JE
E9
MOV
BH,OB8H
MOV
DL,ODBH
CH,40H
MOV
DEC
AL
E9:
OUT
DX,AL

COLOR GRAPHICS CARD INSTALLED
RESAVE VALUE
BEG V IDEO RAM ADDR B/W CD
MODE CONTROL B/W
RAM BYTE CNT FOR B/W CD
SET MODE FOR BW CARD
B/W VIDEO CARD ATTACHED?
YES - GO TEST V IDEO STG
BEG V IDEO RAM ADDR COLOR CO
MODE CONTROL COLOR
RAM BYTE CNT FOR COLOR CD
SET MODE TO 0 FOR COLOR CD
TEST VIDEO STG:
o I SABLE V IDEO FOR COLOR CD

MOV

BP,DS:RESETJLAG

POD INITIALIZED BY KBD RESET

CMP
MOV
JE
MOV
ASSUME
CALL
JNE

BP,1234H
ES, BX
El0
OS, BX
OS: NOTH I NG, ES: NOTH I NG
STGTST CNT
E17
-

POD INITIATED BY KBD RESET?
POINT ES TO VIDEO RAM STG
YES - SK I P V IDEO RAM TEST
POINT OS TO VIDEO RAM STG
,
;

GO TEST V IDEO R/W STG
R/W STG FAI LURE - BEEP SPK

;----- --SE;C p-v~ OEO -oA; A-oN -sCREEN -;OR -v~ OED -L~ NE-; ES;~ ---------DESCR I PT I ON
ENABLE V IDEO SIGNAL AND SET MODE.
DISPLAY A HORIZONTAL BAR ON SCREEN.

j
~ ~ ~ ~

........................

--_ ............... -- -_ ...................................................................................................... -_ ............ ...

POP
PUSH
MOV
SUB
MOV
REP

AX
AX
AX.7020H
01,01
CX,40
STOSW

,
;
;
;
;
;

GET V IDEO SENSE SWS (AH)
SAVE IT
WRT BLANKS IN REVERSE VIDEO
SETUP STARTING LOC
NO. OF BLANKS TO DISPLAY
WRITE VIDEO STORAGE

: -------CR; -~ N; ER; ACE -L~ NEs-;Es; -------------------------

; DESCR I PT I ON
;
SENSE ON/OF F TRANS I T I ON OF THE V IDEO ENABLE
;
AND HOR I ZONTAL SYNC LI NES.
:
; -- ... ..................... -......... ...... ... ...
......... ... ...............
.................. ...
POP
GET VIDEO SENSE SW INFO
AX
SAVE IT
PUSH
AX
CMP
AH,30H
B/W CARD ATTACHED?
SETUP ADDR OF BW STATUS PORT
MOV
DX,03BAH
JE
Ell
YES - GO TEST LINES
MOV
COLOR CARD I S ATTACHED
DL,ODAH
LINE_TST:
Ell:
MOV
AH,8
; OFLOOP _CNT:
E12:
SUB
CX,CX
E13:
READ CRT STATUS PORT
IN
AL,OX
AND
AL,AH
CHECK V IDEO/HaRZ LI NE
I TS ON - CHECK I FIT GOES OFF
JNZ
E14
LOOP TILL ON OR TIMEOUT
LOOP
E13
JMP
GO PR I NT ERROR MSG
SHORT E17
E14:
SUB
CX,CX
E15:
READ CRT STATUS PORT
IN
AL,OX
AL,AH
CHECK VIDEO/HORZ LINE
AND
I TS ON - CHECK NEXT LINE
JZ
E16
LOOP IF OFF TILL IT GOES ON
LOOP
E15
CRT_ERR
E17:
MOV
DX,102H
; GO BEEP SPEAKER
CALL
ERR BEEP
JMP
SHORT E18
NXT LINE
E16:
GET-NEXT BIT TO CHECK
MOV
CL,3
SHR
AH,CL
E12
GO CHECK HORIZONTAL LINE
JNZ
[18:
o I SPLAY CURSOR:
GET V IDEO SENSE SWS (AH)
POP
AX
jmp
short
pod14

-_

; ...

-_

-_ -_ -_ --_

-_ -_

-- -_

-_ ...... -_ ......................................................... -_ ... -- ............... -_ .......................................... -- ...... -_ ............ --- -- --_ ...
TH I S SUBROUT I NE PERFORMS A REAO/WR I TE STORAGE TEST ON
A 16K BLOCK OF STORAGE.
ENTRY REQU I REMENTS:
ES = ADDRESS OF STORAGE SEGMENT BE I NG TESTED
OS = ADDRESS OF STORAGE SEGMENT BE I NG TESTED
WHEN ENTERING AT STGTST_CNT, CX MUST BE LOADED WITH
THE BYTE COUNT.
EX I T PARAMETERS:
ZERO FLAG = 0 I F STORAGE ERROR (DATA COMPARE OR PAR I TY CHECK.
AL = 0 DENOTES A PARITY CHECK. ELSE AL=XOR' EO BIT
PATTERN OF THE EXPECTED DATA PATTERN VS THE
ACTUAL DATA READ.
AX.BX,CX,DX,DI, AND SI ARE ALL DESTROYED.

§;~~ ~~

...... PROC ............

MOV
STGTST CNT:
- CLO
MOV
MOV
MOV

N£~R"'''''''''''''

-- ...... -_ . . -- ............... --- -_ . . -_ . . -- ............... -_ . . ---- ............... -- .........

CX,4000H

SETUP CNT TO TEST A 16K BLK

BX,CX
AX,OAAAAH
DX,OFF55H

SET D I R FLAG TO INCREMENT
SAVE CNT (4K FOR VIDEO OR 16K)
GET DATA PATTERN TO WR I TE
SETUP OTHER DATA PATTERNS TO USE

112 IBM Enhanced Graphics Adapter

02EB
02ED
02EF
02EF
02FO
02Fl
02Fl
02F3
02F5
02F5
02F6
02F8
02FA
02FC
02FD
02FF
0301
0303
0305
0307
0309
030B
0300
030F
030F
0310
0311
0313
0314
0316
0316
0318
0318
0319
031A

2B FF
F3/ AA
4F
FD
8B F1
8B CB
AC
32 C4
75 lE
SA C2

AA
E2 F6
22 E4
74 13

SA EO
86
22
75
8A
EB

F2
E4
04
04
EO

FC
47
74 DE
4F
EB 09
BO 00
FC
C3

= AOAC
= C460
= 00C8
= 8099
= B862
= 015E
= 015E
= 0043
= 0040
031A
031A
0310

83 EC OA
8B EC

031F
0322

E8 0001 R
BO 30

0324
0326
0328
032A
032F
0331
0334
0339
033E
0343
0345
0347
0349
034C
034E
0350
0350
0353
0356
0358
035A
035C
035E
0361
0366
0369

E6
BO
E6
F6
74
E8
C7
C7
C7
B2
B4
BO
E8
B2
EB

43
00
40
06 0487 R 02
1F
016B R
46 02 015E
46 04 8D99
46 06 B862
B4
01
27
OD18 R
BA
2A

E8
E8
73
B2
B4
BO
E8
C7
EB

014B R
OE9C R
11
D4
01
14
OD18 R
46 02 015E
06 90

0369
036E
036E
0373
0378

C7 46 02 00C8
C7 46 04 AOAC
C7 46 06 C460
B2 DA

037A
037A
0370
037F

B8 0500
CD 10
2B C9

0381
0381
0382
0384
0386
0388
038A

EC
A8
75
E2
B3
E9

0380
0380

BO 00

08
07
F9
00
044B R

1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260

01 = OFFSET 0 RELAT I VE TO ES REG
01,01
SUB
C
WR I TE STORAGE LOCAT IONS
STOSB
REP
C
STGOl
C C3:
PO I NT TO LAST BYTE JUST WR I TTEN
01
DEC
C
SET 0 I R fLAG TO GO BACKWARDS
STD
C
C C4:
SI,DI
MOV
C
SETU P BYTE CNT
CX,BX
MOV
C
I NNER TEST LOOP
C C5:
READ OLD TEST BYTE lSI J+
LODSB
C
DATA READ AS EXPECTED?
AL,AH
XOR
C
NO - GO TO ERROR ROUT I NE
C7
JNE
C
GET NEXT DATA PATTERN TO WRITE
AL,DL
MOV
C
WRITE INTO LOCATION JUST READ
STOSB
C
DECREMENT COUNT AND LOOP CX
LOOP
C5
C
C
ENDING 0 PATTERN WRITTEN TO STG?
AH,AH
AND
C
YES - RETURN TO CALLER WITH AL=O
C6X
JZ
C
SETUP NEW VALUE FOR COMPARE
AH,AL
MOV
C
MOVE
NEXT DATA PATTERN TO DL
DH,DL
XCHG
C
READ I NG ZERO PATTERN TH I S PASS ?
AH,AH
AND
C
CONT
I NUE TEST SEQUENCE TILL 0
C6
JNZ
C
ELSE
SET 0 FOR END READ PATTERN
DL,AH
MOV
C
AND MAKE FINAL BACKWARDS PASS
C3
JMP
C
C C6:
SET
0
I
R
FLAG TO GO FORWARD
CLD
C
SET POI NTER TO BEG LOCAT I ON
01
INC
C
READ/WR I TE FORWARD IN SlG
C4
JZ
C
ADJUST
POI
NTER
01
DEC
C
READ/WR I TE BACKWARD IN STG
C3
JMP
C
C C6X:
; AL=O DATA COMPARE OK
AL,OOOH
MOV
C
C C7:
; SET 0 I RECT I ON FLAG BACK TO INC
CLD
C
RET
C
ENDP
C STGTST
C
C
iG~ ~~~ ~ ~~~~iNT i;~
~
C
C
:
C ~ 1. I NIT CRT TO 40X25 - Sn' ****SET TO MODE****
C ; 2. CHECK FOR VERT I CAL AND V IDEO ENABLES, AND CHECK
TIM I NG OF SAME
C
C
I
AND I NTENS I FY DOTS
C
C
C
C
C ; _____ NOM I NAL T I ME IS B286H FOR 60 HZ.
C ; _____ NOMINAL TIME IS A2FEH FOR 50 HZ.
C
MAX T I ME FOR VERT/VERT
OAOACH
C
(NOMINAL + 10%)
C
MI N TIME FOR VERT/VERT
OC460H
C
(NOMINAL - 10%)
C
NUM
OF ENABLES PER FRAME
200
C CENAB PER FRAME EQU
MAX T I ME FOR VERT /VERT
08D99H
EQU
C MAX_VERTJ10NO
( NOM I NAL + 10%)
C
MIN
TIME FOR VERT/VERT
OB862H
EQU
C
( NOM I NAL - 10%)
C
enhanced enables per frame
350
C eENAB PER FRAME equ
NUM OF ENABLES PER FRAME
350
C MENAB=PER=FRAME EQU
C
043H
8253 T I MER CONTROL PORT
EQU
C TIM CTL
8253 T I MER/CNTER 0 PORT
EQU
040H
C T I MERO
C
PROC
NEAR
C
POD14
SP,OAH
RESERVE 5 WORDS ON STACK
SUB
C
BP, SP
IN IT SCRATCH PAD POINTER
MOV
C
C
ASSUME
OS: ABSO, ES: ABSO
C
CALL
DDS
C
SET TIMER 0 TO MODE 0
MOV
AL,OOl10000B
C
C
OUT
TIM CTL,AL
C
MOV
AL, DOH
C
SEND FIRST BYTE TO T I MER
OUT
TIMERO,AL
C
test
info,2
C
COLOR EGA V
JZ
C
ENV 3SET UP I N MONOCHROME
CALL
C
NUM. OF FRAMES FOR MONO
MOV
WORD PTRI BP I I 2 J, MENAB_ PER_FRAME
C
MAX T I ME FOR VERT/VERT
MOV
WORD PTRI BP I I 4 J, MAX_ VERT_MONO
C
MIN T I ME FOR VERT/VERT
WORD PTRIBPJ(6J.MIN_VERT_MONO
MOV
C
MONO CRTC REG
DL, CRTC_ADDR_B
MOV
C
HORIZ. TOTAL 01 PLAY
AH, C HRZ DSP
MOV
C
AL,27H TO 40 COL
MOV
C
CALL
OUT OX
C
DL, INPUT STATUS B
3BA
MOV
C
sho rt
commonjmp
C
C COLOR EGA V:
CALL
SET UP IN 40X25 COLOR
ENV X
C
enhanced mode
ca I I
brst det
C
no,40x25
jne
co lor v
C
brst mode on Iy!
mov
dl,crtc addr
C
ah,l
hrz dsp end
mov
C
modify for test only
a 1,20
mov
C
ca I I
out dx
C
MOV
WORD PTRI BP J I 2 J, eENAB_PER_FRAME ; NUM. OF FRAMES FOR COLOR
C
jmp
brst_color_v
C
C color_V:
C
WORD
PTRI BPJ(2],CENAB_PER_FRAME ; NUM.OF FRAMES FOR COLOR
MOV
C
C brst color v:
MOV
MAX T I ME FOR VERT/VERT
WORD PTRI BP)( 41, MAX_VERT_COLOR
C
MIN T I ME FOR VERT /VERT
MOV
WORD PTRI BP J 161, M I N_ VERT _COLOR
C
SET ADDRESSING TO VIDEO
MOV
DL, INPUT_STATUS
C
ATTR STATUS
C
C COMMON:
SET TO V IDEO PAGE 0
MOV
AX,0500H
C
INT
10H
C
SUB
CX,CX
C
C
C
; ----- LOOK FOR VERT ICAL
C
C POD14 1:
IN
GET STATUS
AL,DX
C
VERT I CAL THERE YET?
TEST
AL, 00001 OOOB
C
CONTINUE IF IT IS
JNE
POD14 2
C
POD14-1
KEEP LOOK I NG TILL COUNT
LOOP
C
BL,OOEXHAUSTED
MOV
C
NO VERT I CAL
POD14_ERR
JMP
C
C
C ;----- GOT VERTICAL - START TIMER
C
C POD14 2:
MOV
AL,O
C

;--------------- - - TT

; ~: g~~g~ ~~~~ ~~~E ~ Nri~~~~~T

-T -----------------

~ - ~: - ~ ~: ~ - ~~ -~~~~~ -=- ~~:~~~~~~~ - :::::~~ -~? -~?~:::::-

-----

IBM Enhanced Graphics Adapter 113

038F

E6 40

0391

2B DB

0393
0395
0395
0396
0398
039A
039C
039E

EC
A8
74
E2
B3
E9

03Al
03Al
03A3
03A3
03A4
03A6
03A8
03M
03AC
03AE
03BO
03B3
03B3
03B5
03B8
03B8
03BA

33 C9
08
07
F9
01
044B R

2B C9
EC
A8
74
A8
75
E2
B3
E9

01
15
08
23
F5
02
044B R

B3 03
E9 044B R
B3 04
E9 044B R

03BD
03BD
03BF

A8 08
75 F2

03Cl
03Cl
03C2
03C4
03C6

EC
A8 01
[1 FB
E3 FO

03C8
03C8
03C9

43
74 04

03CB

A8 08

03CD

74 02

03CF
03CF
0301
0303

BO 00
E6 43
3B 5[ 02

0306
0308
030A
030C
030C
030E
03[0
03El
03E3
03E5
03E6
03E7
03EA
03EC
03EE
03FO
03FO
03F3
03F5
03F7

03F9
03F9
03FC
03FF
0402
0404
0405
0406
0408
040A
040C
040F
0412
0413
0413
0414
0415
0417
0419
041C
0410
041 E
0420
0420
0421
0423
0425
0427
0429
042B
042E
042[
0430
0430
0431
0433
0435
0437
0439

74 04
B3 05
[B 6F
E4
8A
90
[4
86
90
90
3B
70
B3
EB

40
EO

3B
7E
B3
EB

46 06
04
07
52

40
EO
46 04
04
06
5B

B8 090B
BB OOOF
B9 0050
co 10
EC
52
B2 CO
B4 OF
BO 3F
E8 0018 R
B8 OOOF
5A
50
52
B2
84
E8
5A
58
2B
[C
A8
75
E2
B3
OA
EB

CO
32
0018 R
C9

30
09
F9
10
DC
1 E 90

2B C9
[C
A8 30
74 08
[2 F9
B3 20
OA DC

1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
12BO
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

OUT

SEND 2ND BYTE TO TI MER TO
START IT
I NIT. ENABLE COUNTER

TIMERO,AL

SUB
;----- WAIT FOR
XOR
P0014_25:
IN
TEST
JZ
LOOP
MOV
JMP

BX,BX
VERTICAL TO GO AWAY
CX,CX

GET STATUS
VERT I CAL ST I LL THERE
CONTI NUE I FIT'S GONE
KEE P LOOK I NG TILL COUNT
EXHAUSTED
VERT I CAL STUCK ON

AL,OX
AL, 00001 OOOB
P0014 3
P0014-25
BL,OlH
P0014_ERR

;----- NOW START LOOKING FOR ENABLE TRANSITIONS
P0014 3:
SUB
P0014 4:
IN
TEST
JE
TEST
JNE
LOOP
MOV
JMP
P0014_4A:
MOV
JMP
P0014_4B:
MOV
JMP

CX,CX
AL,OX
AL,OOOOOOOlB
P0014 5
AL,00001000B
P0014 75
P0014-4
BL,02H
P0014_ERR

GET STATUS
ENABLE ON YET?
GOONIFITIS
VERTICAL ON AGAIN?
CONT I NU ElF IT IS
KEEP LOOK I NG I F NOT
;

ENABLE STUCK OFF

; VERT I CAL STUCK ON
;

ENABLE STUCK ON

;----- MAKE SURE VERTICAL WENT OFF WITH ENABLE GOING ON
P0014 5:
VERT I CAL OFF?
TEST
AL,00001000B
GO ON I F IT IS
JNZ
P0014 4A
(ERROR I F NOT)
; ----- NOW WA I T FOR ENABLE TO GO OFF
P0014 6:
IN
AL,OX
GET STATUS
ENABLE OFF YET?
TEST
AL,OOOOOOOlB
LOOPE
P0014_6
KEE P LOOK I NG I F NOT
JCXl
P0014 4B
,
YET LOW
; ----- ENABLE HAS TOGGLED, BUMP COUNTER AND TEST FOR NEXT VERT I CAL
P0014 7:
INC
BUMP ENABLE COUNTER
I F COUNTER WRAPS,
Jl
SOMETH I NG I S WRONG
DID ENABLE GO LOW
TEST
AL, 0000 1OOOB
BECAUSE OF VERT I CAL
I F NOT, LOOK FOR ANOTHER
Jl
ENABLE TOGGLE
; ----- HAVE HAD COMPLETE VERT I CAL-VERT I CAL CYCLE; NOW TEST RESULTS
P0014 75:
MOV
LATCH TIMERO
AL,OO
TIM CTL,AL
OUT
NUMBER OF ENABLES BETWEEN
CMP
BX,WORD PTR(BPII2]
VERT I CALS O. K.?
J[
P0014 8
MOV
BL,05il
jrnp
short pod14_err
P0014 8:
IN
GET T I MER VALUE LOW
AL, TIMERO
SAVE IT
MOV
AH,AL
NOP
GET T I MER HIGH
IN
AL, TIMERO
XCHG
AH,AL
NOP
NOP
; MAXIMUM VERTICAL TIMING
CMP
AX, WORD PTR( BP II 4]
P0014 9
JGE
MOV
BL,06il
short pod14_err
jmp
POD14_9:
MI N I MUM VERT I CAL TIM I NG
CMP
AX, WORD PTR( BP II 6]
JLE
P0014 10
MOV
BL,07H
short
pod14_err
jmp
; ----- SEE

I F RED, GREEN, BLUE AND I NT ENS I FY DOTS WORK

,
FIRST,
P0014 10:
MOV
MOV

SET A LINE OF REVERSE VIDEO,
AX,090BH
BX,OOOFH

MOV
CX,BO
I NT
lOH
IN
AL,OX
PUSH
OX
OL, A TTR_WR I TE
MOV
AH,OFH
MOV
AL,03FH
MOV
CALL
OUT OX
MOV
AX,OFH
POP
OX
P0014 13:
PUSH
AX
PUSH
OX
MOV
OL,ATTR_WRITE
MOV
AH,32H
CALL
OUT OX
POP
OX POP
AX
SUB
CX,CX
; ----- SEE I F DOT COMES ON
P0014 14:
IN
AL,DX
TEST
AL,00110000B
JNl
P0014 15
LOOP
P0014-14
MOV
BL,10il
OR
BL,AH
JMP
P0014 ERR
; ----- SEE I F DOT GOES OFF
P0014 15:
SUB
CX,CX
P0014 16:
IN
AL,OX
TEST
AL,00110000B
JE
P0014 17
LOOP
P0014::16
MOV
OR

BL,20H
BL,AH

114 IBM Enhanced Graphics Adapter

I NTENSI F I ED BLANKS I NTO BUFFER
WR I TE CHARS, BLANKS
PAGE 0, REVERSE VIDEO,
HIGH I NTENSI TY
80 CHARACTERS
SAVE I NPUT STATUS
A TTR I BUT E AOORESSS
PALETTE REG 'F'
TEST VALUE
VIDEO STATUS MUX
START WITH BLUE DOTS
SAVE
SAVE I NPUT STATUS
ATTR I BUTE AOOR[SSS
COLOR PLANE ENABLE
VIDEO STATUS MUX
RECOVER I NPUT STATUS

GET STATUS
~OT THERE?
LOOK FOR DOT TO TURN OFF
CONT I NUE TEST FOR DOT ON
OR I N DOT BE I NG TESTED
DOT NOT COM I NG ON

GET STATUS
IS DOT STILL ON?

GO ON I F DOT OF F
ELSE, KEEP WAITING FOR
DOT TO GO OFF
; OR I N DOT BE I NG TESTED

0438

0430
0430
043F
0442
0444
0447
04"9
0448
0448
04"E
0451
0454
0457
0459
045B
0450
045F
0460
0461
0463
0466

E8 OE

FE
80
74
80
8A
EB

C4
FC 30
25
CC OF
C4
C8

89
8A
E8
83
80
E6
2A
E6
90
90
E6
BD
E9

0006
0103
06CB R
C4 OA
36
43
CO
40

0469
0469
046C
046F
0471
0473
0475
0477
0479
047A
047B
0470
0480
0483

E8
B8
CD
BO
E6
2A
E6
90
90
E6
83
BD

0001 R
0500
10
36
43
CO
40

0483
0483
0484

lE
E8 0001 R

40
0001
0092 R

40
C4 OA
0000

0487
048e
048E
0493
0496
0498
049E
04AO
04AO
04A5
04AA
04AO
04AO
04AF
04B2
04B4

F6
74
80
B8
80
B8
EB

06 0487 R 02
12
OE 0410 R 30
OOOF
OE 0487 R 60
OOOF
00

CO
83
88
B8

10
EC 06
EC
AOOO

04B7
04B9
04BB
04CO
04C5
04C7
04C9
04CC
04CF
0401
0404
0407
0408
040A
040B
0400
04EO
04E3
04E6
04E9
04EB
04[(
04EE
04Fl
04F4
04F6
04F9
04F9
04FA
04FC
04FF
0502
0504
0507
05,OA
05-0B
0500
050E
0510
0513
0516
051 B
051E
0521
0523
0526
0526
0529
052C
052E
0531
0531
0532
0534
0537
053A
053B
0530
0540
0543
0545
0546

8E
8E
C7
C7
B6
B2
B8
E8
B2
B8
E8
52
B2
EC
B2
B8
E8
E8
80
74
E9

08
CO
46 02 0000
46 04 0000
03
C4
0201
0018 R
CE
0400
0018 R

E8
80
74
E9

050C R
FC 00
03
0500 R

80 26 0410 R eF
80 0 E 0410 R 20
B8 OOOE

5A
B2
B8
E8
B2
B8
E8
52
B2
EC
B2
B8
E8
C7
E8
80
74
E9
E8
80
74
E9
5A
B2
88
E8
52
82
88
E8
B2
EC
82

OA
CO
3200
0018 R
0692 R
FC 00
03
0500 R

C4
0202
0018 R
CE
0401
0018 R
oA
CO
3200
0018 R
46 04 0000
0692 R
FC 00
03
0500 R
05DC R
FC 00
03
0500 R
C4
0204
0018 R
CE
0402
0018 R
OA
CO

1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1"00
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
e
e
e
C
C
C
C
C
C
C
e
C
e
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

short pod14_err

Jmp

;----- ADJUST TO POINT TO NEXT DOT
POD14_17:
INC
CMP
JE
OR
MOV
JMP
POD14_ERR:
MOV
MOV
CALL
ADD
MOV
OUT
SUB
OUT
NOP
NOP
OUT
MOV
JMP
ASSUME
POD14_18:
CALL
MOV
INT
MOV
OUT
SUB
OUT
Nap
NOP
OUT
ADD
MOV
POD14

AH
AH,030H
POD14 18
AH,OFH
AL,AH
POD14_ 13
CX,6
DX,0103H
ERR 8EEP

SP,Osh
AL,001 101 108
T IM_CTL,AL
AL,AL
T I MERO,AL

; ALL 3 DOTS DONE?
; GO END
; MAKE OF,1F,2F
; GO LOOK FOR ANOTHER DOT
; ONE LONG AND THREE SHORT
; 8ALANCE STACK
; RE-INIT TIMER a

T I MERO,AL
BP,l
SKI P
DS:A8S0
DDS
AX,0500H
10H
AL,OOl10110B
T IM_CTL,AL
AL,AL
T IMERO ,AL
T IMERO ,AL
SP,OAH
BP,O
ENDP

; SET TO VIDEO PAGE 0
; RE-INIT TIMER 0

; REMOVE SCRATCH PAD
; MAKE BP NON ZERO

; ----- TEST STORAGE
MEM_ TEST:
PUSH
OS
CALL
DDS
ASSUME OS: ABSO
info,2
test
o COLOR M
JZ
equip_low,030h
or
may
ax,Ofh
i nfa,060h
may
aX,Ofh

short d_out_m

jmp

O_COLOR_M:
and
MOV

equip_lo'W,Ocfh
equip_loW',020h
AX,OEH

I NT
SUB
MOV
MOV
ASSUME
MOV
MOV
MOV
MOV
may
MOV
may
CALL
MOV
may
CALL
PUSH
MOV
IN
MOV
may
CALL
CALL
CMP
JZ
JMP

10H
SP,6
BP,SP
AX,OAOOOH
OS: NOTH lNG, ES: NOTH I NG
oS,AX
ES,AX
WORD PTRIBPJ(2J,0
WORD PTRI BP 114 J, 0
dh,3
oL, SEQ_ADDR
aX,0201h
OUT OX
OL, GRAPH_AoDR
aX,0400h
OUT_OX
OX
OL, A TTR_REAo
AL,oX
oL,ATTR_WRITE
aX,3200h
OUT OX
HOW-BIG
AH,O
AAl
EGA_MEM_ERROR

CALL
CMP
JZ
JMP

MEMORY_OK
AH,O
AA2
EGA_MEM_ERROR

POP
MOV
may
CALL
MOV
may
CALL
PUSH
MOV
IN
MOV
may
CALL
MOV
CALL
CMP
JZ
JMP

OX
oL, SEQ_AooR
aX,0202h
OUT OX
oL, GRAPH_AooR
aX,0401h
OUT_OX
OX
oL, A TTR_REAo
AL,OX
oL, A TTR_WR I TE
OUT OX
WORD PTR IBPII4J,0
HOW 81G
AH,D
AA3
EGA_MEM_ERROR

CALL
CMP
JZ
JMP

MEMORY_OK
AH,O
/\A4
EGA_MEM_ERROR

POP
MOV
may
CALL
PUSH

OX
DL, SEQ_AOOR
aX,0204h
OUT_OX
OX
oL,GRAPH_AooR
aX,0402h
OUT OX
OL, ATTR_REAO
AL,OX
OL, A TTR_WR I TE

or

O_OUT_M:

AAl:

I NTERNAL COLOR MODE
TEST I N COLOR
OUT 5/4/83
RESERVE 3 WOROS ON STACK
SET BP
PUT BU F FER ADDRESS I N AX
SET UP SEG REGS TO POI NT
TO BUFFER AREA
INITIALIZE
INITIALIZE

; ADDRESS READ MAP SELECT

; SET UP ATTR I BUTE
; A TTR I BUTE WR I TE ADDRESS
; GO F I NO AMOUNT' OF MEMORY

; GO TEST IT

AA2:

; ADDRESS OF READ MAP

; SET UP ATTRIBUTE
; IITTR 18UTE WR I TE ADDRESS

aX,3200h

AA3:

INITIALIZE
; GO F I NO AMOUNT OF MEMORY

; GO TEST IT

AA4:

~OV

may
CALL
MOV
IN
MOV

; ADDRESS OF READ MAP

; SET UP ATTRIBUTE
; ATTRIBUTE WRITE ADDRESS

IBM Enhanced Graphics Adapter 115

0546
054B
054E
0553
0556
0559
055B
055E
055E
0561
0564
0566
0569
0569
05611
056C
056F
0572
0574
0577
057A
057B
0570
057E
0580
0583
0586
058B
058E
0591
0593
0596
0599
0598
059C
059F
D59F
05AO
05Al

B6
E6
C7
E6
80
74
EB

3200
0016 R
46 04 0000
0692 R
FC 00
03
73 90

E8
80
74
EB

05DC R
FC 00
03
68 90

05A4
05A8
05AA
05AC
05AD
05AF
05S1

36: 8B 5C 02
Bl 06
D3 EB
4B
Bl 05
03 E3
80 E3 60

05B4

80 26 0487 R 9F

05B9

08 1 E 0487 R

05BO
05C2
05C6
OSC9
05CC
05CD
05DO
05DO
0503
0506
05D7
050A

80
8A
E8
83
1F
E9

OE 0487 R 04
1 E 0488 R
00F6 R
C4 06

BA
E8
55
BO
EB

0103
06CB R

BB
8E
8E
86
8A
2A
01
E8
8D
75

AOOO
DB
C3
46 04
E8
C9
El
05FE R
FC 00
09

05De
050C
05DF
05El
05E3
05E6
05E8
05EA
05EC
05EF
05F2
05F4
05F4
05F7
05FA
05FO
05FO
05FE

5A
B2
B8
E8
B2
B8
E8
52
B2
EC
B2
B8
E8
C7
E8
80
75
E8
80
75
55
BD

C4
0208
0018 R
CE
0403
0016 R
OA
CO
3200
0018 R
46 04 0000
0692 R
FC 00
3D
050C R
FC 00
35
0000

5E
5A
E8 0001 R

0092 R

0001
C3

8B 46 04
01 46 02
B8 0000
C3

05FE
05FE
05FF
0600

55
FC
2B FF

0602

2B CO

0604

E8 0001 R

0607
060B
060F
0611
0613

88
81
8C
8E
74

0615
0619
061B
061B
0610
061F
0621
0623
0625
0627

81 FB 4321
74 5C

0629

8B E9

88
8A
32
75
FE
8A
75

1 E 0472 R
FB 1234
C2
DA
62

05
05
C4
40
C4
C4
F2

1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621

1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638

mav
aX,3200h
C
CALL
OUT OX
C
INITIALIZE
MOV
WORD PTR[BP)(4J,0
C
GO F I NO AMOUNT OF MEMORY
CALL
HOW BIG
C
AH,O
CMP
C
JZ
AA5
C
EGA_MEM_ERROR
JMP
C
C AA5:
; GO TEST IT
CALL
MEMORY OK
C
AH,O CMP
C
JZ
AA6
C
EGA_MEM_ERROR
JMP
C
C AA6:
POP
DX
C
MOV
DL, SEQ_ADDR
C
mav
aX,0208h
C
CALL
OUT OX
C
; ADDRESS OF READ MAP
MOV
DL, GRAPH ADDR
C
ax, 0403hmav
C
CALL
OUT_OX
C
PUSH
OX
C
; SET UP ATTR I BUTE
DL, ATTR_READ
MOV
C
AL,DX
IN
C
; ATTRIBUTE WRITE ADDRESS
DL, ATTR_WR I TE
MOV
C
mav
aX,3200h
C
CALL
OUT_OX
C
INITIALIZE
WORD PTR[BP)(4J,0
MOV
C
GO FI NO AMOUNT OF MEMORY
CALL
HOW SIG
C
CMP
AH,O
C
EGA MEM ERROR
JNZ
C
GO TEST IT
CALL
MEMORY OK
C
AH,O CMP
C
EGA MEM ERROR
JNZ
C
BP SAVE SCRATCH PAD PO INTER
PUSH
C
RESET BP FOR XT
MOV
BP,O
C
C EGA MEM EXI T:
-POP
RESTORE
$1
C
POP
OX
C
SET DATA SEGMENT
CALL
DDS
C
ASSUME OS: ABSO
C
GET EGA MEMORY SIZE
BX,WORD PTR SS:[SI J[2]
MOV
C
DIVI DE BY 64 TO GET
MOV
CL,06H
C
NUMBER OF 64KB BLOCKS
SHR
BX,CL
C
dec
bx
C
MOV
CL,05H
C
SHL
BX,CL
C
ISOLATE BITS 5 AND 6
AND
BL,01100000B
C
C
info, 10011111 b
and
C
C
OR
INFO,BL
C
C
04H
SET 3XX ACT I VE
INFO,00000100B
OR
C
BL, I NFO_3
MOV
C
CALL
MK_ENV
C
RESTORE STACK
ADD
SP,6
C
POP
OS
C
GO TO END
JMP
SKI P
C
C EGA MEM ERROR:
-MOV
ONE LONG AND THREE SHORT
DX,0103H
C
CALL
ERR BEEP
C
BP SAVE SCRATCH PAD PO INTER
PUSH
C
I NO I CA TE ERROR FOR XT
MOV
BP,1
C
JMP
EGA_MEM_EX I T
C
C
C ; ----- TH I S ROUT I NE FINDS AMOUNT OF MEMORY GOOD
C
PROC
NEAR
C MEMORY OK
- MOV
SET PTR. TO BUFFER SEG
BX,OAOOOH
C
SET SEG.REG.
MOV
C
DS,BX
ES,BX
MOV
C
SET COUNT FOR 32K WORDS
AX, WORD PTR[ BP)( 4]
MOV
C
SET AMOUNT OF BUFFER
CH,AL
MOV
C
TO BE TESTED
SUB
CL,CL
C
MULTIPLY BY TWO
SHL
CX,1
C
CALL
PODSTG
C
TEST
FOR ERROR
CMP
AH,O
C
IF ERROR GO PR I NT I T
MEMORY_OK_ERR
C
JNZ
C MEMORY OK EX:
MOV
AMOUNT OF MEMORY FOUND
AX, WORD PTR[ BP II 4]
C
AMOUNT OF MEMORY GOOD
ADD
WORD PTR[BP][2],AX
C
MOV
C
AX,O
C MEMORY_OK_ERR:
RET
C
C MEMORY_OK
ENDP
C
C -; --------------------- ------- --------- ----------------------- ---C
TH I S ROUT I NE PERFORMS A READ/WR I TE TEST ON A BLOCK OF STORAGE :
C , 1MAX. SIZE = 32KW). I F "WARM START", FILL BLOCK WITH 0000 AND :
C ; RETURN.
:
:
C ; ON ENTRY:
C;
ES = ADDRESS OF STORAGE TO BE TESTED
:
C;
OS = ADDRESS OF STORAGE TO BE TESTED
C;
CX = WORD COUNT OF STORAGE BLOCK TO BE TESTED
C ;
1MAX. = 8000H 132K WORDS))
C ; ON EXIT:
C;
ZERO FLAG 0 OFF I F STORAGE ERROR
C ; AX, BX, ex, ox, 0 I, S I ARE ALL DESTROYED.
C ; ---------- -------- ---------------------------------------------C PODSTG
PROC
NEAR
C
PUSH
BP
SET 0 I R TO INCREMENT
C
CLD
SET 0 I =0000 REL TO START
01,01
SUB
C
OF SEGMENT
C
INITIAL DATA PATTERN FOR
SUB
AX,AX
C
OO-FF TEST
C
CALL
DDS
C
ASSUME
OS: ABSO
C
MOV
BX, OS: RESET FLAG
G
BX,1234H
CMP
C
OX, ES
MOV
C
RESTORE OS
MOV
DS,DX
C
GO DO FI L L WITH 0000
PODSTG_5
JE
C
I F WARM START
C
DCP WARM START?
CMP
BX, 4321 H
C
DO FI LL I F SO
JE
PODSTG_5
C
C PODSTG 1:
- MOV
WRITE TEST DATA
[01 J,AL
C
GET I T BACK
AL, [01 ]
MOV
C
COMPARE TO EXPECTED
XOR
AL,AH
C
ERROR EX I T IF M I SCOMPARE
PODSTG ERRO
JNZ
C
AH
FORM NEW DATA PATTERN
INC
C
MOV
AL,AH
C
LOOP TILL ALL 256 DATA
POQSTG_ 1
JNZ
C
PATTERNS DONE
C
SAVE WORD COUNT
MOV
BP,GX
C

116 IBM Enhanced Graphics Adapter

062B
062E
0630
0633

B8 AA55
8B 08
BA 55AA
F3/ AB

0635
0636
0637
0638
063A
063C
063C
0630
063F
0641
0643
0644
0646
0648
0649
064A
064B
0640
0640
064E
0650
0652

4F
4F
FO
8B F7
8B CO

0653

E2 F8

0655
0656

FO
4E

0657
0658
065A
065A
0658
0650
065F
0661
0663
0663
0665
0667
0669
066B
0660
0660
066F
0671
0674
0674
0675
0676
0677

AD
33
75
8B
AB
E2
8B
FC
46
46
8B

C3
22
C2
F6
CO

FE

AD
33 C2
75 11
AB

4E
8B CO
AD
OB
75
E2
EB

CO
04
F9
11

8B
32
OA
74
B4

C8
E4
EO
02
01

OA C9
74 03
80 C4 02
50
FC
C3

0677
0678
0679
067B
0670
0680
0683
0684
0685
0687

50
52
B6 03
B2 C4
B8 020F
E8 0018 R
5A
58
F3/ AB
E8 0001 R

068A
068E
0690
0692

89 lE 0472 R
8E OA
EB E2

0692
0692
0694
0696
0696
0698
069A
0690
069F
06A2
06A4
06A7
06A9
06AB
06AE
06BO
06B4
06B7
06BA
06BC
06BF
06BF
06C2
06C4
06C4
06C7
06CA
06CA
06C8

06CB
06CB
06CC
06CD
06CE
0601
06D3
0605
0605
0607

8C OA
2B DB
8E C2
2B FF
B8 AA55
8B C8
26: 89 05
BO OF
26: 8B 05
33 Cl
75 14
B9 2000
F3/ AB
81 C2 0400
83 C3 10
80 FE BO
75 OA
EB 01 90
80 FE AO
74 06
01 5E 04
B8 0000
C3

9C
FA
lE
E8 ODO 1 R
OA F6
74 OB
B3 06
E8 0023 R

1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

AX,OAA55H
BX,AX
OX,055AAH
STOSW

DEC
DEC
STO
MOV
MOV

01
01

; LOAD DATA PATTERN
LOAD OTHER DATA PATTERN
FILL WORDS FROM LOW TO
HIGH WITH MAl'.
PO I NT TO LAST WORD
WR I TTEN
SET 0 I R FLAG TO GO DOWN
SET I NDEX REGS. EQUAL
RECOVER WORD COUNT
GO FROM HIGH TO LOW
GET WORD FROM MEMORY
EQUAL WHAT SIB THERE?
GO ERROR EXI T I F NOT
GET 55 DATA PATTERN AND
STORE IN LOC JUST READ
LOOP TILL ALL BYTES DONE
RECOVER WORD COUNT
BACK TO INCREMENT
ADJUST PTRS

51,01
CX,BP

POOSTG 2:
- LOOSW
XOR
JNZ
MOV
STOSW
LOOP
MOV
CLO
INC
INC
MOV
POOSTG 3:
- LOOSW
XOR
JNZ
STOSW

AX,BX
POOSTG_ERRO
AX,DX
PODSTG 2
CX,BP SI
51
01,51

,
;
;
;
;

AX,DX
PODSTG_ERRO

LOW TO HIGH DOING WORDS
GET A WORD
SHOULD COMPARE TO OX
GO ERROR I F NOT
WR I TE 0000 BACK TO LOC
JUST READ
LOOP TILL DONE

LOOP
STD
DEC

PODSTG

BACK TO DECREMENT
ADJ UST PO I NT ER DOWN TO
LAST WORD WR I TTEN

51

DEC
MOV
POOSTG 4:
- LODSW
OR
JNZ
LOOP
jmp
POOSTG ERRO:
- MOV
XOR
OR
JZ
MOV
POOSTG ERR1:
- OR
JZ
ADD
POOSTG ERR2:
- POP
CLD
RET
PODSTG_5:

t

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

MOV
MOV
MOV
REP

PUSH
PUSH
mov
MOV
mov
CALL
POP
POP
REP
CALL
ASSUME
MOV
MOV
JMP
ENDP

51
CX,BP

; GET WORD COUNT
GET WORD
= TO 0000
ERROR I F NOT
LOOP TILL DONE

AX,AX
PODSTG ERRO
PODSTG-4

short podst9_err2
SAVE BITS I N ERROR

CX,AX
AH,AH
CH,CH
POOSTG ERRl
AH,l
-

HIGH BYTE ERROR?
SET III GH BYTE ERROR
LOW BYTE ERROR?

CL,CL
POOSTG ERR2
AH,2 BP

SET D I R FLAG BACK TO INC
RETURN TO CALLER
SIMPLE FILL WITH 0000 ON
WARM-START
SAVE
SAVE VALUE

AX
DX
dh,3
DL,SEQ_ADDR
aX,020fh
OUT DX
OX AX
STOSW
ODS
OS:ABSO
OS: RESET FLAG, BX
OS, DX
PODSTG_ERR2

SEQ_AODR

REGISTER

DO IT
RESTORE
RESTORE

RESTORE DS
AND EXIT

; ----- DETERM I NE 5 I ZE OF BUFFER
HOW_BIG
MOV
SUB
FI LL_LOOP:
MOV
SUB
MOV
MOV
MOV
MOV
MOV
XOR
JNZ
MOV
STOSW
REP
ADD
ADD
CMP
JNZ
JMP
HOW BIG END:
-CMP
jz
RESUME:
ADD
MOV
HB ERROR EXI T:

-

PROC NEAR
DX,OS
BX,BX

SET PNTR TO BUFFER LOC
BASIC COUNT OF OOK
; SET SEG. REG

ES,OX
DI,OI
AX,OAA55H
CX,AX
ES:(DI),AX
AL,OFH
AX, ES: (DII
AX,CX
HOW BIG END
CX,2000H

TEST PATTERN

j

SEND TO MEMORY
PUT SOMETH I NG IN AL
GET PATTERN FROM MEMORY
COMPARE PATTERNS
GO END I F NO COMPARE
SET COUNT FOR 8K WORDS
FILL 8K WORDS
POINT TO NEXT 16K BLOCK
BUMP COUNT BY 16KB

OX,0400H
BX,16
OH,OBOH
FI LL LOOP
HOW_B I G_ENO

; AREA VET ? (BOOOOH)
;

DH,OAOH

1ST 16KB OK

hb_error_exit
WORD PTR( BP II 4), BX
AX,O

; SAVE BUFFER FOUND

RET

ENOP

. --------------------------------------; SUBROUT I NES FOR POWER ON D I AGNOST I CS

:

; T~i ~ -;ROCEDUR E-~ iLL -i ~~u;:- oN;:- LON~ -TON;:- i ;-;ECi -~No -oN;:-oR ------;MORE SHORT TONES (1 SEC) TO INDICATE A FAILURE ON THE PLANAR
;BOARO ,A BAD RAM MOOULE,OR A PROBLEM WITH THE CRT.
; ENTRY REQU I REMENTS:
,
DH=NUMBER OF LONG TONES TO BEEP
;
DL=NUMBER OF SHORT TONES TO BEEP.
~RR- ~EE;

-

---PROC ----NE~R -------------------------------------------

PUSHF
CL I
PUSH
CALL
ASSUME
OR
JZ

DS
DDS
DS: ABSO
DH, DH
G3

SAVE FLAGS
0 I SABLE SYSTEM I NTS

MOV
CALL

BL,6
BEEP

Gl:

ANY LONG TONES TO BEEP
NO, 00 THE SHORT ONES
LONG BEEP
COUNTER FOR BEEPS
DO THE BEEP

IBM Enhanced Graphics Adapter 117

06DA
06DA
06DC
06DE
06EO
06EO
06E2
06E5
06E5
06E7
06E9
06EB
06EB
06ED
06ED
06EF
06FO
06Fl
06F2

1165
1166
1167
1168
1169
1170
1171
1172
1173
1774
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1793
1194
1795
1196
1197
1198
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827

E2 FE
FE CE
75 F5
B3 01
E8 0023 R
E2 FE
FE CA
75 F5
E2 FE
E2 FE
1F
90
C3

06F2
06F2 OEB5
10EC
06F4
1154
06F6
06F8 1183
06FA 119A
06FC 12Al
06FE 150B
15AD
0700
17CF
0702
0704
1896
0706
18DA
lA72
0708
070A lBC8
070C
lC9C
070E lCFE
1082
0710
loC2
0712
1 F95
0714
0716 20BC
0718 2115
= 0028

R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R

071A

= 0000
071A

lB28

071A
0710

=

28 18 08
0800

0005

071 F
071F OB 03 00 03
= 0004
0723

23

0724
0724 37
072A 04
0730 00
0736 C7
073C FF
= 0019
0730
0730 00
0743 06
14
0749
074F OF
= 0014

27
11
00
14

20
00
00
08

37
07
00
EO

31
06
E1
FO

15
07
24
A3

01 02 03 04 05
07 10 11 12 13
15 16 17 08 00
00

= 0037
0751
00 00 00 00 00 10
0751
0757 OE 00 FF
= 0009
= 0040
075A
0750

28 18 08
0800

075F

OB 03 00 03

0763

23

0764
076A
0770
0776
077C

37
04
00
C7
FF

27
11
00
14

0770
0783
0789
078F

00
06
14
OF

01 02 03 04 05
07 10 11 12 13
15 16 17 08 00
00

0791
0797

00 00 00 00 00 10
OE 00 FF

079A
0790

20
00
00
08

50 18 08
1000

37
07
00
EO

31
06
E1
FO

15
07
24
A3

1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
lB75
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

G2:

C

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

MOV
CALL

BL,l
BEEP

; COUNTER FOR A SHORT BEEP
; DO IT

LOOP
DEC
JNZ

G4
DL
G3

; DELAY BETWEEN BEEPS
; DONE WI TH SHORT BEEPS
; DO MORE

G5:

; DELAY BEFORE RETURN

LOOP G5
G6,
LOOP G6
POP
OS
POPF
RET
ENDP
ERR_BEEP

; RESTORE CONTENTS OF OS
; RESTORE FLAGS

SUBTTL
LABEL
OW
OW
OW
OW
OW
OW
OW
OW
OW
OW
OW
OW
OW
OW
OW
OW
OW
OW
OW
OW
EQU

T2L

C
C
C
C
C
C
C
C

; DELAY BETWEEN BEEPS
; ANY MORE TO DO
; DO IT

G4:

T2

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

G2
DH
Gl

LOOP
DEC
JNZ
G3:

WORD
OFFSET
OFFSET
OFFSET
OFFSET
OFFSET
OFFSET
OFFSET
OFFSET
OFFSET
OFFSET
OFFSET
OFFSET
OFFSET
OFFSET
OFFSET
OFFSET
OFFSET
OFFSET
OFFSET
OFFSET
$-T2

AHO
AHl
AH2
AH3
AH4
AH5
AH6
AH7
AH8
AH9
AHA
AHB
AHC
AHD
AHE
AHF
AH10
AHll
AH12
AH13

VPARMS. INC
INCLUDE
SUBTTL VPARMS. INC
PAGE
BYTE
LABEL
VIDEO_PARMS

Structure of this table
columns. rows. pe I 5 pe r cha ra c te r
page length

sequencer parameters

mi see II aneous reg i ster
CRTC pa ramete rs
Attribute parameters
Graphics parameters
base 1

equ

base-' I

S -

vi deo_pa rms
labe I
byte

; ----- defau I t modes
; --0-db
dw

40d,24d,08d
00800h

tfs_len equ

$ - base_l_1

SEQ_PARMS
DB
EQU
Ml

LABEL
BYTE
OOBH, 003H, OOOH, 003H
$ - SEQ_ PARMS

DB

023H
LABEL
BYTE
037H, 027H, 02oH, 03 7H, 031 H, 015H
004H, 0 11 H, OOOH, 007H, 006H, 007H

CRT_PARMS
DB
DB
DB
DB
DB
M4
EQU

OC7H, 0 14H, (J08H, OEOH, OFOH, oA3H
OHH
$-CRT PARMS

ATTR_PARMS
DB
DB
DB
DB
EQU
M5

BYTE
LABEL
OOOH, 001 H, 002H, 003H, 004H, 005H
006H, 007H, 0 1OH, 011 H, 012H, 013H
014H, 015H, 0 16H, 017H, 008H, OOOH
OOFH,OOOH
$-ATTR PARMS

I n_2
equ
GRAPH_PARMS
DB
DB
EQU
M6

$ - base_l_1
LABEL
BYTE
OOOH, OOOH, OOOH, OOOH, OOOH, 010H
OOEH,OOOH,OFFH
$-GRAPH_PARMS

m_tbl

equ

len

OOOH. OOOH. OOOH, OOOH, OE' H, 024H

$ - base 1 I

: --1-db
dw

40d, 24d, OBd
00800h

DB

OOBH ,003H,OOOH, 003H

DB

023H

DB
DB
DB
DB
DB

037H, 027H, 02oH, 037H, 031 H, 015H
004H, 0 11 H, OOOH, 007H, 006H, 007H
OOOH, OOOH, OOOH, OOOH, OE 1H, 024H
OC7H, 0 14H, 008H, OEOH, OFOH, OA3H
OFFH

DB
DB
DB
DB

OOOH, 001 H, 002H, 003H, 004H, 005H
006H, 007H, 0 1OH, 011 H, 0 12H, 0 1 3H
o 14H, 0 15H, 0 16H, 017H, 008H, OOOH
OOFH,OOOH

DB
DB

OOOH, OOOH, OOOH, OOOH, OOOH, 0 1OH
OOEH,OOOH,OFFH

db
dw

80d, 24d, 08d
01000h

: --2--

118 IBM Enhanced Graphics Adapter

MODE SET
SET CURSOR TYPE
SET CURSOR POS I T I ON
READ CURSOR POSI T ION
READ LIGHT PEN POS IT I ON
ACT I VE 0 I SPLAY PAGE
SCROLL DOWN
SCROLL UP
READ CHAR/ATTRIBUTE
WR I TE CHAR/ A TTR I BUTE
WR I TE CHARACTER ONLY
SET COLOR PALETTE
WRITE DOT
READ DOT
WRI TE TTY
CURRENT VIDEO STATE
SET pALETTE REGISTERS
CHAR GENERATOR ROUT I NE
ALTERNATE SELECT
WRITE STRING

079F

01 03 00 03

07A3

23

07A4
07AA
0780
07B6
07BC

70
04
00
C7
FF

4F
11
00
28

0780
07C3
07C9
07CF

00
06
14
OF

01 02 03 04 05
07 10 11 12 13
15 16 17 08 00
00

0701
0707

00 00 00 00 00 10
DE 00 FF

5C
00
00
08

2F
07
00
EO

5F
06
E1
FO

07
07
24
A3

070A
0700

50 18 08
1000

070F

01 03 00 03

07E3

23

07E4
07EA
07FO
07F6
07FC

70
04
00
C7
ff

4F
11
00
28

07fO
0803
0809
080F

00
06
14
OF

01 02 03 04 05
07 10 11 12 13
15 16 17 08 00
00

0811
0817

00 00 00 00 00 10
OE 00 FF

081A
0810

28 18 08
4000

08lf

DB 03 00 02

0823

23

0824
082A
0830
0836
083C

37
04
00
C7
Ff

27
11
00
14

0830
0843
0849
084F

00
06
14
03

1 3 15 17 02 04
07 10 11 12 13
15 16 17 01 00
00

0851
0857

00 00 00 00 00 30
OF 00 FF

085A
OB50

5C
00
00
08

20
00
00
00

2F
07
00
EO

37
01
00
EO

5F
06
E1
fO

30
00
E1
FO

07
07
24
A3

14
00
24
A2

28 18 08
4000

085f

DB 03 00 02

0863

23

0864
086A
0870
0876
087C

37
04
00
C7
fF

27
11
00
14

0870
0883
0889
088F

00
06
14
03

13 15 17 02 04
07 10 11 12 13
15 16 17 01 00
00

0891
0897

00 00 00 00 00 30
OF 00 FF

20
00
00
00

37
01
00
EO

30
00
E1
fO

14
00
24
A2

089A
0890

50 18 08
4000

089F

01 01 00 06

08A3

23

08A4
08AA
08BO
08B6
D8BC

70
04
00
C7
FF

4F
11
00
28

08BD
08C3
08C9
08Cf

00
17
17
01

17 17 17 17 17
17 17 17 17 17
17 17 17 01 00
00

0801
0807

00 00 00 00 00 00
00 00 ff

59
00
00
00

20
01
00
OF

5E
00
EO
EF

06
00
23
C2

08DA
0800

50 18 DE
1000

080F

00 03 00 03

08[3

A6

08E4
08EA
08fO
08f6
08fC

60
70
00
50
FF

4f
If
00
28

08FD
0903
0909
090f

00
08
18
Of

08 08 08 08 08
08 10 18 18 1 B
18 18 18 DE 00
08

56
00
00
00

3A
00
00
5E

51
DB
5E
6E

60
DC
2E
A3

1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

08

DOl H, 003H, OOOH, 003H

08

023H

08
08
DB
DB
DB

070H, 04FH, 05CH, 02FH, 05FH, 007H
004H, 01 1 H, OOOH, 007H, 006H, 007H
OOOH, OOOH, OOOH, OOOH, DE 1 H, 024H
OC7H, 028H, 008H, OEOH, OFOH, OA3H
OFFH

DB
DB
DB
08

OOOH, 001 H, 002H, 003H, 004H, 005H
006H, 007H, 010H, 011H, 012H, 013H
014H, 01 5H, 01 6H, 01 7H, 008H, OOOH
OOFH,OOOH

DB
DB

OOOH, OOOH, OOOH, OOOH, OOOH, 01 OH
OOEH, OOOH, OFFH

db
dw

80d, 24d, 08d
01000h

; --3--

DB

001 H, 003H, OOOH, 003H

DB

023H

DB
DB
DB
DB
DB

070H, 04 FH, 05CH, 02FH, 05FH, 007H
004H, 011 H, OOOH, 007H, 006H, 007H
OOOH, OOOH, OOOH, OOOH, DEl H, 024H
OC7H, 028H, 008H, OEOH, OfOH, OA3H
OFFH

DB
DB
DB
DB

OOOH, 00 1 H, 002H, 003H, 004H, 005H
006H, 007H, 0 1OH, 0 11 H, 012H, 013H
014H, 015H, 016H, 017H, 008H, OOOH
OOFH,OOOH

DB
DB

OOOH, OOOH, OOOH, OOOH, OOOH, 01 OH
OOEH, OOOH, OfFH

db
dw

40d, 24d, 08d
04000h

DB

OOBH, 003H, OOOH, 002H

;--4--

DB

023H

DB
DB
DB
DB
DB

037H, 027H, 02DH, 03 7H, 030H, 014H
004H, 011 H, OOOH, 001 H, OOOH, OOOH
OOOH, OOOH, OOOH, OOOH, OEl H, 024H
OC7H, 0 14H, OOOH, OEOH, OfOH, OA2H

DB
DB
DB
DB

OOOH, 013H, 015H, 017H, 002H, 004H
006H, 007H, 01 OH, 011 H, 012H, 013H
014H, 015H, 016H, 017H, 001 H, OOOH
003H,000H

DB
DB

OOOH, OOOH, OOOH, OOOH, OOOH, 030H
OOfH, OOOH, OfFH

db
dw

40d, 24d, 08d
04000h

DB

OOBH, 003H, OOOH, 002H

DB

023H

DB
DB
DB
DB
DB

037H, 027H, 020H, 03 7H, 030H, 014H
004H, 011 H, OOOH, 00 1 H, OOOH, OOOH
OOOH, OOOH, OOOH, OOOH, OEl H, 024H
OC7H, 014H, OOOH, OEOH, OFOH, OA2H
OFFH

DB
DB
DB
DB

OOOH, 0 13H, 015H, 017H, 002H, 004H
006H, 007H, 01OH, 011 H, 012H, 013H
014H, 0 15H, 016H, 017H, 001 H, OOOH
003H,000H

DB
DB

OOOH, OOOH, OOOH, OOOH, OOOH, 030H
OOFH,OOOH,OFFH

db
dw

80d, 24d, 08d
04000h

DB

001H, 001 H, 000H,006H

DB

023H

DB
DB
DB
DB
DB

070H, 04 FH, 059H, 02DH, 05EH, 006H
004H, 0 11 H, OOOH, 001 H, OOOH, OOOH
OOOH, OOOH, OOOH, OOOH, OEOH, 023H
OC7H, 028H, OOOH, ODFH, OEFH, OC2H
OFFH

DB
DB
DB
DB

OOOH, 017H, 017H, 017H, 017H, 017H
017H, 017H, 017H, 017H, 017H, 017H
01 7H, 017H, 017H, 017H, 001 H, OOOH
001H,ODOH

DB
DB

OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
OOOH,OOOH,OfFH

db
dw

80d, 24d, 14d
01000h

DB

OOOH, 003H, OOOH, 003H

DB

Oa6H

DB
DB
DB
DB
DB

060H, 04fH, 056H, 03AH, 051 H, 060H
070H, 01 fH, OOOH, OOOH, OObH, OOcH
OOOH, OOOH, OOOH, OOOH, 05EH, 02EH
050H, 028H, OOOH, 05EH, 06EH, OA3H
OFFH

DB
DB
DB
DB

OaOH. D08H, 008H, DOBH, D08H, 008H
008H, 008H, 0 1OH, 0 18H, 0 18H, 018H
018H, 0 18H, 018H, 0 18H, OOEH, OOOH
00FH,008H

OFFH

; --5--

; --6--

;--7--

IBM Enhanced Graphics Adapter 119

0911
0917
091A
0910

00 00 00 00 00 10
OA 00 FF
28 18 08
4000

091F

00 00 00 03

0923

23

0924
092A
0930
0936
093C

37
04
00
C7
FF

27
11
00
14

0930
0943
0949
094F

00
06
14
OF

01 02 03 04 05
07 10 11 12 13
15 16 17 08 00
00

0951
0957

00 00 00 00 00 10
OE 00 FF

20
00
00
08

37
07
00
EO

31
06
E1
FO

15
07
24
A3

095A
0950

28 18 08
4000

095F

00 00 00 03

0963

23

0964
096A
0970
0976
097C

3727203731
04 11 00 07 06
00 00 00 00 E 1
C7 14 08 EO FO
FF

0970
0983
0989
098F

00
06
14
OF

0991
0997

00 00 00 00 00 10
OE 00 FF

15
07
24
A3

01 02 03 04 05
07 10 11 12 13
15 16 17 08 00
00

099A
0990

28 18 08
4000

099F

00 00 00 03

09A3

23

09A4
09AA
09BO
09B6
09BC

37
04
00
C7
FF

27
11
00
14

09BD
09C3
09C9
09CF

00
06
14
OF

01 02 03 04 05
07 10 11 12 13
15 16 17 08 00
00

0901
0907

00 00 00 00 00 10
OE 00 FF

20
00
00
08

09DA
0900

50 18 08
1000

37
07
00
EO

31
06
E1
FO

15
07
24
A3

09DF

01 04 00 07

09E3

23

09E4
09EA
09FO
09F6
09FC

70
04
00
C7
FF

4F
11
00
2B

09FO
OA03
OA09
OAOF

00
00
00
Of

00 00 00 00 00
00 00 00 00 00
00 00 00 00 00
00

OAll
OA17

00 00 00 00 00 00
04 00 FF

OA1A
OA1D

50 18 OE
1000

OA1F

00 04 00 07

OA23

A6

OA24
OA2A
OA30
OA36
OA3C

60
70
00
50
FF

4F
1F
00
28

OA30
OA43
OA49
OA4F

00
00
00
OF

00 00 00 00 00
00 00 00 00 00
00 00 00 OE 00
08

OA51
OA57

00 00 00 00 00 00
04 00 FF

OA5A
OA5D

28 18 08
2000

OA5F

OB OF 00 06

OM3

23

OA64
OA6A
OA70
OA76
OA7C

37
04
00
C7
FF

OA70

00 01 02 03 04 05

27
11
00
14

5C
00
00
08

56
00
00
00

20
00
00
00

2F
07
00
EO

3A
00
00
5E

37
00
00
EO

5F
06
E1
FO

51
OB
5E
6E

30
00
E1
FO

07
07
24
A3

60
OC
2E
A3

14
00
24
E3

2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2071,
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

OB
OB

OOOH, OOOH, OOOH, OOOH, OOOH, 01 OH
OOAH,OOOH,OFFH

db
d...

40d, 24d, 08d
04000h

08

OOOH, OOOH, OOOH, 003H

;--8--

DB

023H

DB
DB
DB
DB
DB

037H, 027H, 02DH, 037H, 031 H, 015H
004H, 011 H, OOOH, 007H, 006H, 007H
DOOH, DOOH, DaOH, DOOH, DEl H, 024H

OB
OB
OB
OB

OOOH, 001 H, 002H, 003H, 004H, 005H
006H, 007H, 010H, 011 H, 012H, 013H
014H, 015H, 016H, 017H, 008H, OOOH
OOFH,OOOH

DB
DB

OOOH, OOOH, OOOH, OOOH, OOOH, 010H
OOEH,OOOH,OFFH

db
d ...

40d, 24d, 08d
04000h

DB

OOOH, OOOH, OOOH, 003H

OC7H, 014H, 008H, OEOH, OFOH, OA3H
OFFH

;--9--

DB

023H

DB
DB
DB
DB
DB

03 7H, 027H, 020H, 03 7H, 031 H, 015H
004H, 011 H, OOOH, 007H, 006H, 007H
OOOH, OOOH, OOOH, OOOH, OE 1 H, 024H
OC7H, 014H, 008H, OEOH, OFOH, OA3H
OFFH

OB
DB
DB
DB

OOOH, 00 1H, 002H, 003H, 004H, 005H
006H, 007H,010H, 011 H. 012H, 013H
014H, 015H, 0 16H, 017H, 008H, OOOH
OOFH,OOOH

DB
DB

OOOH, OOOH, OOOH, OOOH, OOOH, 0 1OH
OOEH,OOOH,OFFH

;--a-db
dw

40d, 24d, 08d
04000h

DB

OOOH, OOOH, OOOH, 003H

DB

023H

DB
DB
DB
DB
DB

037H, 027H, 02DH, 037H,
004H, 0 11 H, OOOH, 007H,
OOOH, OOOH, OOOH, OOOH,
OC7H, 01 4H, 008H, OEOH,
OFFH

DB
DB
DB
DB

OOOH, 001 H, 002H, 003H, 004H, 005H
006H, 007H, 010H, 011 H, 01 2H, 013H
o 14H, 0 15H, 016H, 017H, 008H, OOOH
OOFH,OOOH

DB
DB

OOOH, OOOH, OOOH, OOOH, OOOH, 01 OH
OOEH,OOOH,OFFH

db
d...

80d, 24d, 08d
01000h

03 1 H, 01 5H
006H, 007H
OE 1 H, 024H
OFOH, OA3H

; --b--

DB

001H, 004H, OOOH, 007H

DB

023H

DB
DB
DB
DB
DB

070H, 04FH, 05CH, 02FH, 05FH, 007H
004H, 011 H, OOOH, 007H, 006H, 007H
OOOH, OOOH, OOOH, OOOH, OEl H, 024H
OC7H, 028H, 008H, OEOH, OFOH, OA3H
OFFH

DB
DB
DB
DB

OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
OOFH,OOOH

DB
DB

OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
004H,OOOH,OFFH

;--c-db
dw

80d,24d,14d
01000h

DB

OOOH, 004H, OOOH, 007H

DB

Oa6H

DB
DB
DB
DB
DB

060H, 04FH, 056H, 03AH, 05 1 H, 060H
070H, 01 FH, OOOH, OOOH, OObH, OOcH
OOOH, OOOH, OOOH, OOOH, 05EH, 02EH
05DH, 028H, OODH, 05EH, 06EH, OA3H
OFFH

DB
OB
DB
DB

OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
OOOH, OOOH ,OOOH, OOOH, OOOH, OOOH
OOOH, OOOH, OOOH, OOOH, OOEH, OOOH
00FH,008H

DB
DB

OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
004H, OOOH, OFFH

db
d...

40d, 24d, 08d
02000h

DB

OOBH, OOFH, OOOH, 006H

DB

023H

DB
DB
DB
DB
DB

03 7H, 027H, 02DH, 03 7H, 030H, 0 14H
004H, 011 H, OOOH, OaOH, OOOH, OOOH
OOOH, OOOH, OOOH, OOOH, OE 1 H, 024H
OC7H, 01 4H, OOOH, OEOH, OFOH, OE3H
OFFH

DB

OOOH, 001 H, 002H, 003H, 004H, 005H

; --d--

120 IBM Enhanced Graphics Adapter

OAB3
OAB9
OA8F

0607 10 11 12 13
14 15 16 17 01 00
OF 00

OA91
OA97

00 00 00 00 00 00
05 OF FF

OA9A
OA90

50 18 08
4000

OA9F

01 OF 00 06

OAA3

23

OAA4
OAAA
OABO
OAB6
OABC

70
04
00
C7
FF

4F
11
00
28

OABO
OAC3
OAC9
OACF

00
06
14
OF

01 02 03 04 05
07 10 11 12 13
15 16 17 01 00
00

59
00
00
00

20
00
00
OF

5E
00
EO
EF

06
00
23
E3

OADl
OAD7

00 00 00 00 00 00
05 OF FF

OADA
OAOD

50 18 DE
8000

OADF

05 OF 00 00

OAE3

A2

OAE4
OAEA
OAFO
OAF6
OAFC

60
70
00
50
FF

4F
IF
00
14

OAFO
OB03
OB09
OBOF

00
00
00
05

08 00 00 18 18
00 00 08 00 00
18 00 00 DB 00
00

OBll
OB17

00 00 00 00 00 10
07 OF FF

OB1A
OB10

56
00
00
00

lA
00
00
5E

50
00
5E
6E

EO
00
2E
8B

50 18 DE
8000

OBlF

05 OF 00 00

OB23

A7

OB24
OB2A
OB30
OB36
OB3C

5B
6C
00
50
FF

4F
IF
00
14

OB3D
OB43
OB49
OB4F

00
00
04
05

01 00 00 04 07
00 00 01 00 00
07 00 00 01 00
00

OB51
OB57

00 00 00 00 00 10
07 OF FF

53
00
00
OF

17
00
00
5F

50
00
5E
OA

BA
00
2B
8B

= 0440

OB5A
OB50

50 18 OE
8000

OB5F

01 OF 00 06

OB63

A2

OB64
OB6A
OB70
OB76
OB7C

60
70
00
50
FF

4F
IF
00
28

OB70
OB83
OB89
OB8F

00
00
00
05

08 00 00 18 18
00 00 08 00 00
18 00 00 OB 00
00

OB91
0697

00 00 00 00 00 00
05 OF FF

56
00
00
00

3A
00
00
5E

50
00
5E
6E

60
00
2E
E3

OB9A
OB90

50 18 OE
8000

OB9F

01 OF 00 06

OBA3

A7

OBA4
OBAA
OBBO
OBB6
OBBC

5B
6C
00
50
FF

4F
IF
00
28

OBBO
OBC3
OBC9
OBCF

00
14
3C
OF

01 02 03 04 05
07 38 39 3A 3B
3D 3E 3F 01 00
00

OBDl
OBD7

00 00 00 00 00 00
05 OF FF

53
00
00
OF

= 04CO

OBDA
OBDD

28 18 OE
0800

37
00
00
5F

52
00
5E
OA

00
00
2B
E3

2143
2144
2145
2146
2147
214B
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
224B
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

; --e .....

006H, 007H, 010H, 011H,012H,013H
014H, 015H, 016H, 017H, 001 H, OOOH
OOFH,OOOH

DB
DB

OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
005H,OOFH,OFFH

db
dw

80d, 24d, 08d
04000h

DB

001 H,OOFH, 000H,006H

DB

023H

DB
DB
DB
DB
DB

070H, 04FH, 059H, 020H, 05EH, 006H
004H, 011 H, OOOH, OOOH, OOOH, OOOH
OOOH, OOOH, OOOH, OOOH, OEOH, 023H
OC7H, 028H, OOOH, OOFH, OEFH, OE3H
OFFH

DB
DB
DB
DB

OOOH, 00 1H, 002H, 003H, 004H, 005H
006H, 007H, 01 OH, 011 H, 012H, 013H
014H, 015H, 016H, 017H, 001 H, OOOH
OOFH,OOOH

DB
DB

OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
005H,OOFH,OFFH

db
dw

80d,24d,14d
08000h

DB

005H, OOFH, OOOH, OOOH

;--f--

DB

Oa2H

DB
OB
DB
OB
DB

060H, 04 FH, 056H, 01AH, 050H, OEOH
070H, 01 FH, OOOH, OOOH, OOOH, OOOH
OOOH, OOOH, OOOH, OOOH, 05EH, 02EH
05DH, 014H, OODH, 05EH, 06EH, 08BH
OFFH

DB
DB
DB
DB

OOOH, 008H, OOOH, OOOH, 0 18H, 018H
OOOH, OOOH, OOOH, 008H, OOOH, OOOH
OOOH, 0 18H, OOOH, OOOH, OOBH, OOOH
005H,OOOH

DB
DB

OOOH, OOOH, OOOH, OOOH, OOOH, 010H
007H, OOFH, OFFH

db
dw

80d,24d,14d
08000h

DB

005H, OOFH, OOOH, OOOH

DB

Oa7H

DB
DB
DB
DB
OB

05BH, 04 FH, 053H, 0 1 7H, 050h, ObaH
06CH, 01 FH, OOOH, OOOH, OOOH, OOOH
OOOH, OOOH, OOOH, OOOH, 05EH, 02BH
05DH, 0 14H, OOFH, 05 FH, OOAH, 08BH
OFFH

OB
DB
DB
DB

OOOH, 00 1h, OOOH, OOOH, 004h, 007h
OOOH, OOOH, OOOH, 001 h, OOOH, OOOH
004h, 007h, OOOH, OOOH, 00 1 H, OOOH
005H,OOOH

OB
DB

OOOH, OOOH, OOOH, OOOH, OOOH, 0 10H
007H, OOFH, OFFH

equ

$ ... vldeo_parms

;-10--

c

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

DB
DB
DB

base_2

> 16K mode values

; --f-80d,24d,14d
08000h

db
dw
DB

001 H, 00 FH, OOOH, 006H

OB

Oa2H

OB
DB
DB
DB
DB

060H, 04 FH, 056H, 03AH, 050H, 060H
070H, 01 FH, OOOH, OOOH, OOOH, OOOH
OOOH, OOOH, OOOH, OOOH, 05EH, 02EH
05DH, 028H, OOOH, 05EH, 06EH, OE3H
OFFH

DB
DB
DB
DB

OOOH, 008H, OOOH, OOOH, 018H, 018H
OOOH, OOOH, OOOH, 008H, OOOH, OOOH
OOOH, 0 18H, OOOH, OOOH, OOBH, OOOH
005H,OOOH

DB
DB

OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
005H, OOFH, OFFH

db
dw

BOd,24d,14d
08000h

DB

Oa7H

DB
DB
OB
OB
DB

05BH, 04 FH, 053H, 03 7H, 052H, OOOH
06CH, 01 FH, OOOH, OOOH, OOOH, OOOH
OOOH, OOOH, OOOH, OOOH, 05EH, 02BH
050H, 028H, OOFH, 05FH, OOAH, OE3H
OFFH

OB
OB
OB
DB

OOOH, 00 1 H, 002H, 003H, 004H, 005H
014H, 007H, 038H, 039H, 03a H, 03bH
03cH, 03dH, 03eH, 03 rH, 001 H, OOOH
OOFH,OOOH

DB
DB

OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
005H, OOFH, OFFH

;-10--

001 H, 00 FH, OOOH, 006H

base_3

equ

; ----- hi

S ...

vi deo_pa rms

res alternate values

; --0-db
dw

40d,24d,14d
00800h

IBM Enhanced Graphics Adapter 121

OBof

OB 03 00 03

OBE3

A7

OBE4
OBEA
OBfo
OBf6
oBfC

20
6C
00
50
ff

27
1f
00
14

OBrD
OC03
OC09
OCOf

00
14
3C
Of

01 02 03 04 05
07 36 39 3A 3B
3D 3E 3f 06 00
00

OC11
OC17

00 00 00 00 00 10
OE 00 ff

2B
00
00
Of

20
00
00
5E

26
06
5E
OA

60
07
2B
A3

OC1A
OC1D

28 16 OE
0600

OClf

OB 03 00 03

OC23

A7

OC24
OC2A
OC30
OC36
OC3C

20
6C
00
50
fF

27
1f
00
14

OC30
OC43
OC49
OC4f

00
14
3C
OF

01 02 03 04 05
07 36 39 3A 3B
3D 3E 3f 06 00
00

OC51
OC57

00 00 00 00 00 10
OE 00 fF

2B
00
00
Of

20
00
00
5E

28
06
5E
OA

60
07
2B
A3

OC5A
OC50

50 18 OE
1000

OC5f

01 03 00 03

OC63

A7

OC64
OC6A
OC70
OC76
OC7C

5B
6C
00
50
fF

4r
1F
00
28

OC7D
OCB3
OC89
OC8F

00
14
3C
OF

01 02 03 04 05
07 38 39 3A 3B
3D 3E 3F 08 00
00

OC91
OC97

00 00 00 00 00 10
OE 00 fF

53
00
00
OF

37
00
00
5E

51
06
5E
OA

5B
07
2B
A3

OC9A
OC9D

50 lB DE
1000

OC9f

01 03 00 03

OCA3

A7

OCA4
OCAA
OCBO
OCB6
OCBC

5B
6C
00
50
fF

4F
1F
00
28

OCBO
OCC3
OCC9
OCCf

00
14
3C
OF

01 02 03 04 05
07 38 39 3A 3B
3D 3 E 3 F 08 00
00

OCDl
OC07

00 00 00 00 00 10
OE 00 ff

OCOA
OCOA
OCOB
OCOC
OCOD
OCOE
OCDF
OCED
OCEl
OCE2
OCEl

53
00
00
Of

37
00
00
5E

51
06
5E
OA

5B
07
2B
A3

fB
fC
55
06
1E
52
51
53
56
57

OCE4
OCE5
OCE7
OCE9
OCEB
OCED
OCfO
OCf2
OCF3
OCf5
OCf8

50
8A
32
01
8B
3D
72
58
CD
E9

OCF8
OCFB
OCFC

E8 0001 R
58
2E: ff A4 06f2 R

C4
E4
ED
FO
0028
06
42
219B R

0001

0001
0002
0004

50
2B CO
BE 08

2269
2270
2271
2272
2273
2274
2275
2276
2277
2276
2279
2260
2261
2262
2263
2264
2265
2266
2267
2266
2269
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2306
2309
2310
2311
2312
2313
2314
2315
2316
2317
231B
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2336
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
235B
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

C

DB

00BH,003H,oOoH,003H

DB

Oa7H

DB
DB
DB
DB
DB

02dH, 027H, 02bH, 02dH, 026h, 06dh
06cH, 01 fH, oOOH, OOdH, 006H, 007H
OOOH, OoOH, oOoH, OOOH, 05eH, 02bH
05dH, 014H, oOfH, 05eH, OOaH, OA3H
OffH

DB
DB
DB
DB

OOOH, 001 H, 002H, 003H, 004H, 005H
01 4H, 007H, 036H, 039H, 03aH, 03bH
03cH, 03dH, 03eH, 03fH, 006H, OOOH
OOfH,OoOH

DB
DB

OOOH, OOOH, OOoH, OOoH, OOOH, 01 OH
OOEH, OOOH, OffH

db
dw

40d, 24d, 14d
00600h

DB

OOBH, 003H,OOOH, 003H

DB

Oa7H

DB
DB
DB
DB
DB

02dH, 027H, 02bH, 02dH, 028h, 06dh
06cH, 01 fH, OOOH, OOdH, 006H, 007H
OOOH, OOOH, OOOH, OOOH, 05eH, 02bH
05dH, 014H, OOfH, 05eH, OOaH, OA3H
OffH

DB
DB
DB
DB

OOOH, 001 H, 002H, 003H, 004H, 005H
014H, 007H, 038H, 039H, 03aH, 03bH
03cH, 03dH, 03eH, 03fH, OOBH, OOOH
OOFH,OOOH

DB
DB

OOOH, OOOH, OOOH, OOOH, OOOH, 01 OH
OOEH,OOOH,OFfH

db
dw

60d, 24d, 14d
01000h

DB

001 H, 003H, OOOH, 003H

DB

Oa7H

DB
DB
DB
DB
DB

05bH, 04 FH, 053H, 03 7H, 051 h, 05bh
06cH, 01 fH, OOOH, OOdH, 006H, 007H
OOOH, OOOH, OOOH, OOOH, 05eH, 02bH
05dH, 026H, OOfH, 05eH, OOaH, OA3H
OFFH

DB
DB
DB
DB

OOOH, 00 1 H, 002H, 003H, 004H, 005H
014H, 007H, 03BH, 039H, 03aH, 03bH
03cH, 03dH, 03eH, 03fH, 008H, OOOH
OOFH,OOOH

DB
DB

OOOH, OOOH, OOOH, OOOH, OOOH, 0 1 OH
OOEH,OOOH,OFFH

;--1--

; --2--

;--3--

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

db
dw

80d,24d,14d
01000h

DB

001H, 003H,OOOH, 003H

DB

Oa7H

DB
DB
DB
DB
DB

05bH, 04fH, 053H, 037H, 051 h, 05bh
06cH, 01 fH, OOOH, OOdH, 006H, 007H
OOOH, OOOH, OOOH, OOOH, 05eH, 02bH
05dH, 028H, OOfH, 05eH, OOaH, OA3H
OFFH

DB
DB
DB
DB

OOOH, 001 H, 002H, 003H, 004H, 005H
014H, 007H, D38H, 039H, 03aH, 03bH
03cH, 03dH, 03eH, 03fH, 006H, OOOH
OOFH,OOOH

DB
DB

OOOH, OOOH, OOOH, OOOH, OOOH, 01 OH
OOEH, OOOH, OFfH

SUBTTL
; ----- VECTOR INTO  SPEC I f I ED fUNCT I ON
COMBO_VIDEO
ST I
CLO
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH

PROC

NEAR

BP
ES
OS
OX
CX
BX
SI
01

PUSH
MOV
XOR
SAL
MOV
CMP
JB
POP
INT
JMP

AX
AL,AH
AH,AH
AX,l
SI,AX
AX, T2L
M2
AX
42H
V_RET

ASSUME
CALL
POP
JMP

OS: ABSO
DDS
AX
WORD PTR CS: (S I + OFfSET T2 )

I NTERRUPTS ON
SET 0 I RECT I ON fORWARD
SAVE THE REG I STER SET

SAVE AX VALUE
GET I NTO LOW BYTE
ZERO TO HIGH BYTE
• 2 FOR TABLE LOOKU P
PUT INTO S I FOR BRANCH
TEST FOR WITH I N RANGE
BRANCH AROUND BRANCH
RECOVER REG I STER
PASS UNRECOGN I ZED CALL
RETURN TO CALLER

M2:
RECOVER
; JMP TO AH=O THRU AH=XX

; ----- UT I L I TY ROUT I NES
; ----- SET OS TO THE DATA SEGMENT
PROC
PUSH
sub

NEAR
AX

ax,ax
ds,ax

122 IBM Enhanced Graphics Adapter

SAVE REG I STER

0006
0007
0008

58
C3

0008
0008
0009
OOOC
0010
0013
0016
0017
0018
0018
0018
001A
001B
001C
001 E
001 F
0020
0021

lE
E8
8B
80
80
IF
C3

0001 R
16 0463 R
E2 FO
CA OA

86 C4
EE
42
86 C4
EE
4A
C3

0021
0021
0022
0023
0023
0023
0024
0027
0029
002C
002F
0030
0033
0035
0038
003B
003C
003E
0040
0043
0045
0045
0047
0049
004B
0040
0050
0051
0052

EE
C3

52
BA
BO
E8
B8
4A
E8
8A
E8
BA
EC
8A
OC
E8
2B
E2
FE
75
8A
E8
5A
C3

0043
86
0021 R
0533
0021 R
C4
0021 R
0061
EO
03
0021 R
C9
FE
CB
FA
C4
0021 R

0052
0052

E8 0001 R

0055
0059
005C
0050

C4 1 E 04A8 R
26: C4 1F
C3

0050
0050
005E
005F
0062
0066
006B

51
52
E8
8A
F6
74

0052 R
26 0449 R
06 0487 R 60
18

0060
0070
0072
0076
0079
0079
007C
007E
0082
0085
0085
0088

80
75
81
EB

FC OF
07
C3 0440
33 90

80
75
81
EB

FC 10
07
C3 0480
27 90

008A
0080
008F
0091
0093
0095
0097

009A
009A
009E
009E
00A2
00A4

00A6
00A6
00A9
OOAB
OOAB
OOAB

80 FC 03
77 14

AO
24
3C
74
3C
74
EB

0488 R
OF
03
07
09
03
05 90

81 C3 04CO
8A OE 0449 R
2A ED
E3 05

83 C3 40
E2 FB
5A

2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520

POP

RET

AX

RESTORE REG I STER

PROC
NEAR
OS: ABSO
OS
DOS
OX, AOOR_6845
OL,OFOH
OL,OAH
OS

SAVE OATA SEGMENT
GET LOW MEMORY SEGMENT
GET CRTC AOORESS
STR I P Off LOW NIBBLE
SET TO STATUS REGISTER

ENOP

OOS

WHAT BASE
ASSUME
PUSH
CALL
MOV
ANO
OR
POP

RET

WHAT_BASE

ENOP

OUT_OX

NEAR
AL,AH

PROC
XCHG
WOUT
OUT
INC
XCHG
WOUT
OUT
OEC
RET
ENOP

OUT_OX

, AH=INOEX,AL=OATA,DX=PORT
; GET I NDEX VALUE
;' SET INDEX REG

OX,AL
OX
AL,AH
OX,AL
OX

SET OX TO DATA REG
GET DATA VALUE
SET DATA REG
;

SET OX BACK TO INDEX

; ----- ROUT I NE TO SOUNO BEEPER
BP _ 1

BP_l
BEEP

PROC
WOUT
OUT
RET
ENOP

NEAR

PROC
PUSH
MOV
MOV
CALL
MOV
OEC
CALL
MOV
CALL
MOV
WIN
IN
MOV
OR
CALL
SUB

NEAR
OX
OX, T IMER+3
AL, 101 101 lOB
BP 1
AX-;-533H
OX
BP 1
AL-;-AH
BP_l
OX, PORT_B

LOOP
DEC
JNZ
MOV
CALL
POP

G7
BL
G7
AL,AH
BP 1
OX-

OX,AL

SEL TIM 2,LSB,MSB,BINARY
WR I TE THE T I MER MOOE REG
o I VI SOR FOR 1000 HZ
; WR I TE T I MER 2 CNT -

LSB

;

MSB

GET SETT I NG OF PORT

AL,OX
AH,AL
AL,03
BP 1
CX-;-CX

SAVE THAT SETT I NG
TURN SPEAKER ON
SET CNT TO WA IT 500 MS

G7:

DELAY BEFORE TURN I NG OFF
OELAY CNT EXP I REO?
NO-CONT I NUE BEEI'I NG SPK
RECOVER VALUE {IF PORT
RETURN TO CALLER

RET

BEEP

WR I TE T I MER 2 CNT -

ENOP

find the parameter table vector in the save table
set_base assume
ca II
'w'lxs

Les
les
ret

set_base

proc
ds:absO
dds
es, bx, saVB_ptr

; get ptr to ptr table

bx, saVB_pt r
bX,dword ptr es:[bxj

; get parameter ptr

endp

;----- establ ish addressing to the correct mode table entry

proc
assume
push
push
ca II
mov

test
jz

ds:absO
ex
dx

set base

get parm tbl ptr

ah,crt mode
info,060h
b_m_l

test for base card
min memory

;----- we have a memory expansion option here
cmp
jne
add
jmp

ah,Ofh

emp
jne
add
jmp

ah,OlOh
b m 1
bx,basB_2 + m_tbl_len .. basB_'
b_m_out

b_m_2
bx, base 2 .. base 1
b_m_out -

emp
ja

skip enhanced portion

;----- check the switch setting for enhancement

a I, inf'o 3
a I ,Ofh -

mov
and
emp

a I,03h

je
emp
je
jmp

brs
a I ,09h
brs
b_m_3

seconda ry emu I a te set t i ng
primary emulate sett ing

; ----- we wi II perform enhancement
brs:

vector to enhancement tb I

add
mov
sub

jcxz

c I , c rt mode
ch, ch b_m_4

;----- this loop wi II move the ptr to the individual mode entry
add
loop

bx,m tbl len
b_m3
-

pop

dx

;

I eng th of one mode ent ry

b m 4:

b- m-out:

-

-

IBM Enhanced Graphics Adapter 123

OF32
OF32
OF35
OF37
OF3B

OF3E
OF3E
OF3F
OF40
OF42
OF44
OF49
OF40
OF4E
oF50
OF53
OF55
OF59
OF59
OF5F
OF64
OF67
OF6A
OF6B
OF6C
OF6E

A2
B2
89
EB

58
50
B6
24
80
08
58
24
A2
B2
89

0449 R
B4
16 0463 R
lC 90

03
80
26 0487 R 7F
06 0487 R
7F
0449 R
04
16 0463 R

C7 06 044E R 0000
C6 06 0462 R 00
B9 0008
BF 0450 R
lE
07
2B CO
F3/ AB

oF70

E8 0050 R

OF73
0F76
oF78

26: 8A 07
2A E4
A3 044A R

oF7F

OF7B

26: 8A 47 01
A2 0484 R

OF82
OF86
OF88

26: 8A 47 02
2A E4
A3 0485 R

OF8B
OF8F

26: 88 47 03
A3 044C R

OF92
OF94
OF96
OF9A
OF9D
OF9F
OFA2

28
80
8A
80
74
80
77

OFA4
OFA7

E8 OE9C R
72 02

OFA9
OFAB
OF AB
OFAE
OFBl
OFB5
OFB8
OFBA
OFBD
oF8D
OFCO
OFC3
OFC3
OFC4
OFC5
OFC9
OFCB
OFCO
OFDO
OFDl
OFD4
OFD7
OFD9
OFD9
OFDC
OFDF
OFE2
OFE5
OFEA
OFEC
OFF2
OFF2
OFF7
OFF9
OFFB
1000
1002
1002
1006
1009
100C
100E
1010
1012
1015
10 15
1018
lOlA
101C
1020
1022
1023
1025
1025
1026
1029
102B
102E
1032
1035
1039
103C
1040
1043
1044
1044

DB
01
26 0449 R
FC 07
OC
FC 03
35

BO 02
E8
E8
8A
80
74
EB

1 EAB R
0001 R
26 0449 R
FC 07
03
10 90

80 0000 E
BB OEOO
OE
07
26: 88 56 00
OB 02
74 OC
B9 0001
45
E8 1 EF3 R
83 C5 OE
EB EA
E8 ODAE R
E8 OE57 R
E8 OE98 R
E8
80
72
C7

0001 R
3E 0449 R OF
06
06 OlOC R 0000 E

80
77
74
80
76

3E 0449 R 07
09
4B
3E 0449 R 03
44

C4 1 E 04A8 R
83 C3 OC
26: C4 1F
8C CO
OB C3
74 32
BE 0007
26: 8A 00
3C FF
74 7A
3A 06 0449 R
74 03
46
EB FO
FA
26: 8A 07
FE C8
A2 0484 R
26: 8B 47 01
A3 0485 R
26: 8B 47 03
A3 010C R
26: 8B 47 05
A3 OlOE R
FB
EB 50

2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898

MOV
MOV
MOV
JMP

SAVE MODE VALUE
IT IS (2/3 )-B-X
SAVE CRTC ADDRESS
CONTI NUE THE MODE SET

CRT_MODE, AL
DL, CRTC_ADDR_B
ADDR_6845, OX
QQl

; ----- COLOR SETUP TO THE ADAPTER
RECOVER PARAMETER VALUE
SAVE IT

POP
PUSH
mav

AX
AX

AND
AND
OR
POP
AND
MOV
MOV
MOV

AL,080H
INFO,07FH
INFO,AL
AX
AL,07FH
CRT_MODE, AL
DL, CRTC_ADDR
ADDR_6845, OX

I SOLATE REGEN CLEAR BIT
PREPARE I NfO BYTE
SET IT, OR NOT
RECOVER TRUE MODE CALL
DONE WITH 07
SAVE TH I S MODE
(2/3 )-D-X
SAVE CRTC ADDRESS

MOV
MOV
ASSUME
MOV
MOV
PUSH
POP
SUB
REP

CRT_START, 0
ACT I VE_PAGE, 0
ES: NOTHI NG
CX,8
01, OFfSET CURSOR_POSN
OS
ES
AX, AX
STOSW

SAVE START ADDRESS
RESET PAGE VALUE TO ZERO
8 PAGES OF CURSOR VALUES
OFFSET
ESTABLI SH
ADDRESSING
o THOSE CURSOR LOCATIONS
CLEAR OUT SAVED VALUES

MOV
SUB
MOV

Al,ES:[bxl
AH,AH
CRT _ COLS, AX

GET COLUMN COUNT
ZERO HIGH BYTE
STORE COLUMN VALUE

MOV
MOV

AL,ES:[bx)[l
ROWS,AL

I

GET ROW VALUE
STORE ROW VALUE

MOY
SUB
MOV

AL, ES; [bx)[ 2
AH,AH

I

GET THE BYTES/CHAR
ZERO HIGH BYTE
STORE BYTES/CHAR

MOY
MOY

AX,ES;[bx)[31
CRT_LEN,AX

GET PAGE SIZE
STORE PAGE LENGTH

SUB
MOY
MOY
CMP
JE
cmp
ja

BX,BX
AL,l
AH , CRT_MODE
AH,7
ENTRY 2
ah,03h

ZERO
MONOCHROME ALPHA CHAR GEN
GET CURRENT MODE
I SIT MONOCHROME
9X14 FONT

dh,3

QQl :

ca II

ca II

entry_'
brst det

jc

entrY_2

MOY

AL,2

; COLOR ALPHA CHAR GEN

CH GEN

;

ENTRY 2;
CALL
CALL
MOV
CMP
JE
JMP
FDG_I T:
MOY
MOV
FDG;
PUSH
POP
MOY
OR
JZ
MOY
INC
CALL
ADD
JMP
ENTRY_l :
ca 11
CALL
CALL
ASSUME
CALL
cmp
jb
MOY
cmp
ja
je
cmp
jbe
save_9 rph:
les
add
les
or

S9- 1 ;

POINTS,AX

TABLE POINTER
14 BYTES PER CHAR

CS
ES
OX, ES; [BPI
DX,DX
ENTRY_l

GET THE ROM SEGMENT
INTO ES
GET THE CHAR HEX CODE
ZERO = NO MORE CHARS
NO MORE
DO ONE CHAR AT A TIME
MOVE TO FIRST CODE PO I NT
STORE THE CODE PO I NT
ADJUST BP TO NEXT CODE
DO ANOTHER

CX,l

BP
DO_MAP2
BP,014D
FOG

set_regs
; CLEAR OUT THE BUFFER

BLANK
PH_5
DS:ABSO
DDS

crt_mode,Ofh
ms 1
word ptr GRX_SET , OFfSET CGMN

crt_mode, 7
save_9 rph
save_a I ph
crt_mode, 3
save_a I ph

bx,save_ptr
bx,Och
bX,dword ptr es:[bxl

ax,es
ax,bx
j4j
si ,07h

mov

a I , e s: [ bx )[ s i I
a I,Offh

cmp

GET CURRENT MODE
I SIT MONOCHROME
9Xl~ FONT

BP,OFFSET CGMNJDG
BX,OEOOH

~~v
je
cmp

ahO done
a I , crt_mode

je
inc
jmp

S9_2
si
s9-1

eli

may

al,byte ptr es:[bx]

dec

aI
rO'w'S,a I

aX,word ptr es: [bxl [1

I

po ints, ax
aX,word ptr es;[bx)[31

'Word ptr grx_set,ax
aX,word ptr es;[bx)[51

'Word pt r 9 rx_set + 2, ax
sti
j4j:
jrnp

LOAD AL PHA CHAR GEN

DDS
AH,CRT_MODE
AH,7
FOG IT
ENTRY_l

short ahO_done

124 IBM Enhanced Graphics Adapter

1046
1046
104A
1040
1050
1052
1054
1056
1059
1059
105C
105E
1060
1064
1066
1067
1069
1069
106C
1070
1074
1078
107C
1080
1081
1083
1086
1088
1089
1080
108F
1091
1093

1096
1096
1099
109E
10AO
10A3
10A6
10A8
10AA
lOAD
lOBO
lOB2
lOB7
lOB9
lOBB
108B
lOBE
lOBE
10C2
10C5
10C5
10CB

C4 lE 04A8 R
83 C3 08
26: C4 1 F
8C CO
OS C3
74 40
SE OOOS
26: 8A 00
3C FF
74 36
3A 06 0449 R
74 03
46
EB FO
26: 8A 27
26: 8A 47
26: 8B 4F
26: 8B 57
26: 8B 6F
26: 8E 47
53
8B 08
B8 1110
CD 10
5B
26: SA 47
3C FF
74 05
FE C8
A2 0484 R

01
02
04
06
08

OA

E8 0001 R
80 3E 0449 R 07
77 lE
BB 10C5 R
AO 0449 R
2A E4
03 08
2E: SA 07
A2 0465 R
BO 30
80 3E 0449 R 06
75 02
BO 3F
A2 0466 R
8B OE 0460 R
EB 28 90
2C 28 20 29 2A 2E
lE 29

lOCO
lOCO
1000
1002
1004
1006
1006
1008
lODC
lODE
10EO
10EO
10El
10El
10E6
10E7
10E9
lOEB
lOEB
10EC

ro 00

80
75
FE
EB

04
Cl
OA

FE
3A
72
2A

Cl
OE 0485 R
02
C9

51
2A
80
59
75
FE

CD
F9 10
02
Cl

C3

= 0004
10EC

10EC
10EE
10F2
10F7

10F9
10FB

10ro
10FF
1101
1104

1106
1106
110B
1100
1112
1114

1117
1119
lllC
111 E
1121
1121
1124

B4
89
F6
75

8A
24
3C
75
B9
EB

OA
OE 0460 R
06 0487 R 08
33

C5
60
20
05
1 EOO
26

F6 06 0487 R 01
75 1F
80 3E 0449 R 03
77 15
E8 OE9C R
73 10
80 FD 04
76 03
80 C5 05
80 F9 04
76 03

2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
.2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024

saV8_8Iph:

bx, save_pt r

les
add
les

bX,08h
bX,dword ptr eo:(bx)

ax,es
ax,bx

or

~~y

ahO done
ol,Obh

moy
emp

al,es:(bx)(ol)
a I ,Offh
ahO_done
8 I , crt_mode
sa 2
sl-

je
emp

je
Inc
jmp

58_'

ah,es:(bx)
al ,es: (bx)( 1)
eX,es:(bx)(2)
dX,eo:(bx)(4)
bp,es:(bx)(6)
es,es:(bx)(8)
bx

moy
moy
moy
moy

~~~h

bX,8X

moy

ax,1110h
10h
bx
al,es:(bx)(Oah(
a I ,Offh
ahO done
al -

i nt

~~e

emp

je
dec

rows,81
set the loW' ram values for compatibi I ity (308 and 309 save bytes)
.shO done:

-

.ca II

dds

emp

crt_mode,1

~~v

dndos
bx,offset compat_mode
.8 I , crt_mode

mov
sub
add

ah,ah

bx,ax

a I ,cs: [bx]
crt_mode_set,a I
a I ,030h

moy
moy
emp

do_pa I:

crt_mode,6

~~~

do_pa I
a I ,03fh
crt_pa lette,a I

dndos:
moy
jrnp

ex,.cursor _mode
ahl

I abe I

campa t_mode
db
db

INCLUDE Vl-5.INC
SUBTTL Vl-5. INC
PAGE

C
C
C
C

g
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

C
C
C

byte

02eh, 028h, 02dh, 029h, 02ah, 02eh
01eh,029h

oa I c_cu r:~~ume
emp
jne
inc
jmp
inc
emp

proc
ds:absO
ch,O
ee 1
clshort

check fa r fu I I he i ght
no rrna I check
adjust end value

el
cl ,byte ptr points
ca Ic out
cl,cT

jb
sub

c,slc out:
push
sub
emp
pop

save cursor type value
end - sta rt
low nibble equal
restore

ex
ci ,ch
el,010h
ex
comp_4
el

jne
inc

adjust for ega reg I sters
it wrap
no, its ok
ega method for cursor end

.... i II

add 1 for correct cursor
back to caller

ret

os I c_cu rso r

endp

;-;£1=cT~~f:- :::~f~:C~~~~R~~rp~:::::-~:~: :--------.- ------------;
;

INPUT

;
(CX) HAS CURSOR VALUE CH-START LINE, CL-STOP LINE
; OUTPUT
;
NONE

;-------

~~;=~;;

--------- --...... 4" -------.. --------.. -----.. -------;~~

AHl :
ASSUME
MOV
MOV

OS: ABSO
AH,C_CRSR_START
CURSOR_MODE, CX

CRTC REG FOR CURSOR SET
SAVE IN DATA AREA

test
jnz

info,8
do_set

ega act i ve bit
O=ega, 1=01d cards

;--- ... - this section wi II emulate cursor off on the ega
MOV
AND
CMP
jne
MOV
jrnp

AL,CH
AL,060H
AL,020H
ahl a
CX, 01 EOOH
short do_set

GET START VALUE
TURN OFF CURSOR?
TEST THE BITS

si<.ip cursor off
EMULATE CURSOR OFF

this section: adjust the cursor and test for enhanced operation
test
jnz
emp
ja
ca II
jnc
emp
jbe
add
cmp

jbe

info,l
do set
crt mode,3
ahl-s
brst det
ahl S
ch, cut_off
ahl b

eh,5

cursor emulate bit
O=emulate, 1=value as-is
possible emulation
no, set the cu rso r type
see if emu I ate mode
not emulating
test sta rt
skip adjust
adjust
test end
sk i p adjust

IBM Enhanced Graphics Adapter 125

1126
1129
1129
112C
112C
112F

1132
1132
1136
1138
1138
1130
113F
1142

1143
1143
1144
1146
1148
114C
114E
1150
1152
1153
1154

1154
1154
1157
115A
115A
115C
115E
1160
1162
1166
116A
116C
116E
1171
1171

1172
1172
1175
1177
1178
1170
117F
1182
1183

1183
1183
1165
1167
1169
1160
1191
1192
1193
1194
1195
1196
1197
1198
1199

80 Cl 05
E8 lOCO R
E8 1132 R
E9 219B R

8B
8A
E8
FE
SA
E8
C3

53
88
SA
F6
32
03
01
5B
C3

160463 R
C5
0018 R
C4
Cl
0018 R

08
C4
26 044A R
FF
C3
EO

E8 115A R
E9 219B R
8A CF
32 ED

~~ ~1

89
38
75
88
E8

94 0450 R
3E 0462 R
05
C2
1172 R

C3

E8 1143 R
8B C8
03 OE 044E R
01 F9
B4 OE
E8 1132 R
C3

8A
32
01
88
88
5F
5E
58
56
56

OF
FF
E3
97 0450 R
OE 0460 R

1F
07
50
CF

119A
119A
1190
119F

AO 0449 R
3C 07
77 37

l1Al
l1A6

F6 06 0467 R 02
7407

l1A6
11M
1 lAC

3C 07
742C
EB 05 90

11Af
l1AF

3C 06

3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3036
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3116
3119
3120
3121
3122
3123
3124
3125
3126
3.127
3126
3129
3130
3131
3132
3133
3134
3135
3136
3137
3136
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

do_set:

add

cl,5

cs II

ca I c_cursor

; adjust end register
OUTPUT CX REG
RETURN TO CALLER

CALL
JMP

;----- THIS ROUTINE OUTPUTS THE CX REGISTER TO THE CRTC REGS NAMED IN AH
M16:
MOV
MOV
CALL
INC
MOV
CALL
RET

;

ADDRESS REG I STER
DATA
OUTPUT THE VALUE
NEXT REG I STER
SECOND DATA VALUE
OUTPUT THE VALUE
ALL DONE

OX, ADDR_6845
AL,CH
OUT_OX
AH
AL,CL
OUT_OX

.. --- --- ... -- .. ----- --------- ---- -------- -- -- --- ........ __ .. __ ..... ------- ---

;

POSITION
THIS SERVICE ROUTINE CALCULATES THE REGEN BUffER
I NPUT ADDRESS OF A CHARACTER I N THE ALPHA MODE

;
;

OUTPUT

AX = ROW, COLUMN POSITION
AX = OFFSET OF CHAR POSITION IN REGEN BUFFER

;

~osiTioN--------PROC----NEAR-------------------------------------

PUSH
MOV
MOV
MUL
XOR
ADD
SAL
POP
RET

BX
BX, AX
AL, AH
BYTE PTR CRT COLS
BH, BH
AX, BX
AX,l
BX

POS I T ION

;

SAVE REG I STER
ROWS TO AL
DETERM I NE BYTES TO ROW
ZERO OUT
ADD I N COLUMN VALUE
2 FOR ATTR I BUTE BYTES
RESTORE REG I STER

*

ENDP

; ---------------------------------------------------------------;

SET_CPOS
SET CURSOR POS I T I ON
TH I S ROUT I NE SETS THE CURRENT CURSOR POS I T I ON TO THE
I NPUT NEW X-Y VALUES PASSED

;
;
;
;

g~

:

~?~pmU~~G~F O~E~U~~~~OR

OUTPUT
CURSOR I S SET AT CRTC IF 0 I SPLAY PAGE
DISPLAY

I S CURRENT

iH2~-------------------------------------------------------------

CALL
JMP
SET CPOS:
MOV
XOR
SAL
MOV
MOV
CMP
JNZ
MOV
CALL
M17:
RET

CL, BH
CH,CH
CX,1
SI,CX
(S I +OFFSET CURSOR_POSN], OX
ACT IVE_PAGE, BH
M17
AX,DX
M18

ESTABLI SH LOOP COUNT
WORD OFFSET
USE I NO EX REG I STER
SAVE THE PO INTER
SET CPOS RETURN
GET-ROW/COLUMN TO AX
CURSOR SET
SET_CPOS_RETURN

; ----- SET CURSOR POS I T ION, AX HAS ROW/COLUMN FOR CURSOR
M18

M18

PROC
CALL
MOV
ADD

NEAR
POS I T I ON
CX,AX
CX, CRT_START

SAR
MOV
CALL
RET
ENDP

CX,l
AH, C CRSR LOC HGH
M16 -

-_

-_ -_

;

--- ---- -_

DETERMINE LOC IN REGEN
ADD I N THE START ADDR
FOR TH I S PAGE
/ 2 FOR CHAR ONLY COUNT
REGISTER NUMBER FOR CURSOR
SET VALUE TO CRTC

----

; ............................
.. -- -- -- ... .. -...................
_........
READ CURSOR
- TH I S ROUT I NE READS THE CURRENT CURSOR VALUE FROM
MEMORY AND SENDS I T BACK TO THE CALLER
;
;
;
;

---_ .. --_ ..

INPUT BH _ PAGE OF CURSOR
OUTPUT
OX - ROW, COLUMN OF THE CURRENT CURSOR POS I T I ON
CX - CURRENT CURSOR MODE

:

iH3~-------------------------------------------------------------

MOV
XOR
SAL
MOV
MOV
POP
POP
POP
POP
POP
POP
POP
POP
IRET

BL, BH
BH, BH
BX,1
OX, (BX + OFFSET CURSOR_POSN J
CX, CURSOR_MODE
01
SI
BX
AX
AX
OS
ES
BP

;----- READ LIGHT PEN POSITION
AH4;

MOV
CMP
JA

AL, CRT_MODE
AL,07H
READ_LPEN

test

info,2
CVA_I S_COLQR

JZ

;----- MONOCHROME HERE (MONOC BIT 1>
CMP
JE
JMP

AL,07H
READ LPEN
OLD_LP

; ----- CVA I S COLOR HERE (MONOC BIT 0>
CVA I S COLOR:
- CMP

AL,06H

126 IBM Enhanced Graphics Adapter

PAGE VALUE
ZERO UPPER BYTE
WORD OFFSET
GET CURSOR FOR TH I S PAGE
GET THE CURSOR MODE

DISCARD CX
DISCARD OX

llBl
llB3
llB3
llB5
llB6
11 B7
llBA
llBB
llBC
llBO

7625
CO 42
5f
5E
83 C4 06
lf
07
50
CF

l1BE
l1BE 06 06
l1C4 04 05
l1CA 00 05
I 100 04 06
11060704

07
00
06
06

07
00
0 1,
04

05
00
04
07

05
00
04
04

1108

1108
110C

86 16 0463 R
83C206

110F
11 EO
11 E2
l1E4
I I E6

EC
A8
B4
74
E9

04
00
03
128 E R

llE9
I I E9

llEB

A8 02
75 03

1 I ED

E9 1298 R

llFO
llFO

B4 10

llF2
I I F6

8B 160463 R
8A C4

11 F8
llF9
llFA

EE
42
50

l1FB
llFC
I lFE
llFF
1200
1202

EC
8A E8
58
4A
FE C4
8A C4

1204
1205

EE
42

1206
1207

EC
8A E5

1209
1200
120F
1214
1216
121A
121C
121E
1220

8A 1 E 0449 R
2A FF
2E: 8A 9F llBE R
2B C3
8B IE 044E R
01 EB
2B C3
7902
2B CO

1222
1222
1224
1229
122B
1230

Bl
80
72
80
74

03
3E 0449 R 04
40
3E 0449 R 07
46

1232
1237
1239
1236

80
77
75
01

3E 0449 R 06
28
02
E8

1230
1230
123F

B2 28
F6 F2

124 I
1243
1245
1247
1249
124E
1250

8A
02
8A
2A
80
75
Bl

E8
ED
DC
FF
3E 0449 R 06
04
04

3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C+
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C+
C
C
C
C+
C
C
C
C
C
C
C+
C
C
C+
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

JBE

READ_LPEN

INT
POP
POP
ADD
POP
POP
POP
IRET

42H
01
SI
SP,6
OS
ES
BP

OLD_LP:

; ......

,
;
;
;
;
;
;
;
;
;
; ..

; CALL EX I ST I NG CODE
;

DISCARD SAVED BX,CX,DX

-_ ............ -- -_ .... -- --_ .. -_ .. --_ .. --_ .. ------- ----_ .. ----- ---_ .. -- -- ---

LIGHT PEN
TH I S ROUT I NE TESTS THE LI GHT PEN SW I TCH AND THE LI GHT
PEN TRIGGER. IF BOTH ARE SET, THE LOCATION Of THE LIGHT
PEN IS DETERMINED. OTHERWISE, A RETURN WITH NO
INFORMATION IS MADE.
ON EXIT
(AH) = 0 IF NO LIGHT PEN INFORMATION IS AVAILABLE
BX,CX, OX ARE DESTROYED
(AH) = 1 IF LIGHT PEN IS AVAILABLE
(DH, DL) = ROW, COLUMN Of CURRENT LI GHT PEN
POSITION
(CH)
RASTER POS IT I ON (OLD MODES)
(CX)
RASTER POSITION (NEW MODES)
(BX)
BEST GUESS AT PIXEL HORIZONTAL POSITION

=
=

-_ .... - -_ ........ -_ .... -_ ...... =-_ .... -_ .......... --- ---_ ... --- .. ----- ... _-----_ ... _...... _..

ASSUME CS:CODE,DS:ABSO
;----- SUBTRACT_TABLE
VI
LABEL
BYTE
DB
006H, 006H, 007H, 007H, 005H, 005H
DB
004H, 005H, OOOH, OOOH, OOOH, OOOH
DB
OOOH, 005H, 006H, 004H, 004H, 004H
DB
004H, 006H, 006H, 004H, 007H, 004H
DB
007H,004H
PROC

0-5
6-B
C-ll
12-17
18-19

NEAR

;----- WAIT FOR LIGHT PEN TO BE DEPRESSED
MOV
ADD
WIN
IN
TEST
MOV
JZ
JMP

OX, ADDR_6845
DX,6

GET BASE AODRESS OF 6845
POINT TO STATUS REGISTER
GET STATUS REG I STER

AL,DX
AL,4
AH,O
V9
V6

TEST LIGHT PEN SW ITCH
SET NO LIGHT PEN RETURN
CODE
NOT SET, RETURN

;----- NOW TEST FOR LIGHT PEN TRIGGER
V9:
TEST
JNZ

AL,2
V7A

JMP

'V7

;----- TRIGGER HAS BEEN SET,

TEST LI GHT PEN TR I GGER
RETURN WITHOUT RESETT I NG
TR I GGER
EXIT LIGHT PEN ROUTINE
READ THE VALUE IN

V7A:
MOV

;

AH,16

INPUT REGS POINTED TO BY AH,
MOV
MOV
WOUT
OUT
INC
PUSH
WIN
IN
MOV
POP
DEC
INC
MOV
WOUT
OUT
INC
WIN
IN
MOV

LIGHT PEN REG I STERS

AND CONVERT TO ROW COLUMN

IN OX

ADDRESS REG I STER
REG I STER TO READ
SET I T UP

OX, ADDR_6845

AL,AH
DX,AL
OX
AX

DATA REGISTER
GET THE VALUE

AL,DX
CH,AL
AX
OX
AH
AL,AH

SAVE

SECOND DATA REG I STER

DX,AL
OX
AL,DX
AH,CH

IN CX

; ADDRESS REG I STER

POINT TO DATA REGISTER
GET THE 2ND DATA VALUE
;

IV(

HAS I N PUT VALUE

; ----- AX HAS THE VALUE READ I N FROM THE 6845
MOV
SUB
MOV
SUB
MOV
SHR
SUB
JNS
SUB

BL, CRT_MODE
BH, BH
BL, CS:Vl [BX]
AX, BX
BX,CRT_START
BX,l

AX,BX
V2
AX,AX

MODE VALUE TO BX
AMOUNT TO SUBTRACT
TAKE I T AWAY
SCREEN ADDRESS
DIVI DE BY 2
ADJ UST TO ZERO START
IF POSITIVE, GET MODE
<0 PLAYS AS 0

;----- DETERMINE MODE OF OPERATION
V2:
MOV
CMP
JB
CMP
JE

CL,3
CRT MODE,4
V4 CRT_MODE,7
V4

CMP
JA
JNE
SHR

CRT_MODE,06H
V8
V8X

DETERMI NE MODE
SET *8 SHIFT COUNT
GRAPH I CS OR ALPHA
ALPHA_PEN
; ALPHA_PEN

AX,l

; ----- OLD GRAPH I CS MODES
V8X:
MOV
DIV

DL,40
DL

DIVISOR FOR GRAPHICS
ROW( AL) AND COLUMN (AH)
AL RANGE 0-99,
AH RANGE 0- 39

; ----- DETERM I NE GRAPH I CROW POS I T I ON
MOV
ADD
MOV
SUB
CMP
JNE
MOV

CH, AL
CH, CH
BL,AH
BH, BH
CRT MODE,6
V3 CL,4

SAVE ROW VALUE INCH
*2 FOR EVEN/ODD FIELD
COLUMN VALUE TO BX
*8

FOR MED I UM RES

MEDIUM OR HIGH RES
NOT HIGH RES
SH 1FT VALUE FOR HIGH RES

IBM Enhanced Graphics Adapter 127

1252
1254
1254

DO E4
03 E3

1256
1258
125A
125C
125E
1261

8A
8A
DO
DO
E8

1261
1262
1266
1268
126)1
126C
1260
126E
1272
1273
1275

99
F7
8B
03
88
52
99
F7
5A
8A
EB

1278
1278
127C
127E
1280
1282
1284
1286
128A
128C
128C
128E
128E

F6
8A
8A
8A
32
03
F6
8B

04
FO
EE
EE
2C 90

36 044A R
DA
E3
C8
36 0485 R
FO
15 90

36 044A R
FO
04
DC
FF
E3
26 0485 R
C8

B4 01
52

128F
1293

8B 16 0463 R
63 C2 07

1296

EE

1297
129B
1298
1299
129A
1290
129E
129F
12AO
12Al

5A
5F
5E
83 C4 06

1F
07

~~

12Al
12Al
12A4

A2 0462 R
8B OE 044C R

12M
12A9
12M

96
50
F7 El

12AC

A3 044E R

12AF
12Bl
12B5
12B8
12BA
12BA
12BC
12BC
12BE
12Cl
12C2
12C4
12C8
12CB

BB
8A
80
17

12CE
12CE
12CF
1201
1203
1205
1207
1208
120A
120C
12DC
1200
1200
1200
12DE
12DF
12E2
12E6
12[7
12E7
12E8
12[A
12EC
12ED
12EE

C6
IE 0449 R
FB 07
02

01 H
B4
E8
5B
01
8B
E8
E9

50
8A
2A
FE
3A
58
75
2A

OC
1132 R
E3
87 0450 R
1172 R
219B R

E6
E5
C4
EO
02
CO

C3

53
IE
E8 0001 R
8B IE 044A R

1F
51
8A CA
2A ED
56
57
F3/ 1\4

3217
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297
3296
3299
HOO
3301
3302
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
3326
3329
3330
3331
3332
3333
3334
3335
3336
3337
3336
3339
3340
3341
3342
3343
3344
3345
3346
3347
3346
3349
3350
3351
3352
3353
3354
3355
3356
3357
3356
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3369
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399
3400
3401
3402

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C+
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

SAL

AH,1

SHL

BX,CL

COLUMN VALUE *2 FOR HIGH RES
NOT HIGH RES
*16-FOR HIGH RES

V3:
;----- DETERMINE ALPHA CHAR POSITION
MOV
MOV
SHR
SHR
JMP

DL,AH
DH,AL
DH,1
DH,1
V5

COLUMN VALUE FOR RETURN
; ROW VALUE
; ·DIVIDE BY 4
FOR VALUE IN 0-24 RANGE
LIGHT _PEN_RETURN_SET

V8:
NEW GRAPH I CS MODES
CWO
DIV
MOV
SAL
MOV
PUSH
CWO
DIV
POP
MOV
JMP

PREPARE TO DIVIDE
COLUMN
AX
ROW, OX
SAVE REMA I NDER
PEL COLUMN
PEL ROW
SAVE FROM DIVIDE
PREPARE TO DIVIDE
DIVIDE BY BYTES/CHAR
RECOVER
CHARACTER ROW

=

CRT_COLS
BX,DX
BX,CL
CX,AX
OX
PO I NTS
OX
DH,AL
V5

=

;----- ALPHA MODE ON LIGHT PEN
ALPHA PEN
ROW, COLUMN VALUE
ROWS TO DH
COLS TO DL
COLUMN VALUE
TO BX

V4:
DIV
MOV
MOV
MOV
XOR
SAL
MUL
MOV

BYTE PTR CRT _COLS
DH,AL
DL,AH
BL,AH
BH, BH
BX,CL
BYTE PTR PO I NTS
CX,AX

MOV

AH,1

PUSH

OX

MOV
AOD
WOUT
OUT

OX, ADDR_6645
DX,7

POP

OX

LIGHT PEN RETURN SET
I NO I CATE EVERTH ING SET
LIGHT _PEN_RETURN
SAVE RETURN VALUE
(IN CASE)
GET BASE ADDRESS
PO I NT TO RESET PARM
ADDRESS, NOT DATA,

V5:
V6:

DX,AL
IS IMPORTANT
RECOVER VALUE
RETURN_NO_RESET

V7:
POP
POP
ADD
POP
POP
POP
IRET
READJPEN

01
SI
SP,6
OS
ES
BP

; DISCARD SAVED BX, CX, OX

ENDP

;-;~T=O ~~; =;;GE ---------~E~ E~T -;~T ~ ~E -0~ ~;~; Y-;;GE ----- ---------THIS ROUTINE SETS THE ACTIVE DISPLAY PAGE,
;
FOR MULTI PLE PAGES OF DISPLAYED VIDEO.
;
; INPUT
AL HAS THE NEW ACTIVE DISPLAY PAGE
;
; OUTPUT
THE CRTC IS RESET TO DISPLAY THAT PAGE
;

; _.........

ALLOWING

-_ ... -_ ... -- -_ ...... --- --- -_ ... --- -_ ......... --- -_ ... --_ ... -- -- ......... --- ... -- -_ ......... _-:

AH5:
MOV
MOV

ACT IVE_PAGE,AL
CX,CRT_LEN

SAVE ACT I VE PAGE VALUE
GET SAVED LENGTH OF
REGEN BUFFER
CONVERT AL TO WORD
SAVE ·PAGE VALUE
Dt SPLAY PAGE TIMES
REGEN LENGTH
SAVE START ADDRESS FOR
LATER REQU I REMENTS
START ADDRESS TO CX

CBW
PUSH
MUL

AX
CX

MOV

CRT_START ,AX

MOV
MOV
CMP
ja

CX,AX
BL, CRT_MODE
BL,7

SAR

CX,1

; / 2 FOR CRTc HANOLJ NG

MOV
CALL
POP
SAL
MOV
CALL
JMP

AH, C_STRT _HGH
M16
BX
BX,1
AX, [ BX + OFFSET CURSOR_POSN I
M18
V_RET

; REG FOR START AODRESS

; DO NOT DIVIOE BY TWO FOR THE

adp_'

ADP_2:
ADP_l :

RECOVER PAGE VALUE
*2 FOR WORD OFFSET
GET CURSOR FOR TH I S PAGE
SET THE CURSOR POS IT I ON

SUBTTL
INCLUDE VSCROLL. INC
SUBTTL VSCROLl. INC
PAGE
FLTA

PROC
PUSH
MOV
SUB
INC
CMP
POP
JNE
SUB

NEAR
AX
AH,DH
AH,CH
AH
AH,AL
AX
LTA
AL,AL

; CHECK· FOR SCROLL COU·NT
LOWER ROW
UPPER ROW
NUMBER TO SCROLL
SAME AS REQUESTED

; YES, SET TO 0 FOR BLANK

LTA:
FLTA
CRANK

RET
ENDP
PROC
PUSH
ASSUME
PUSH
CALL
MOV
POP

NEAR
BX
OS: ABSO
OS
DDS
BX, CRT_COLS
OS

PUSH
MOV
SUB
PUSH
PUSH
R[P

CX
CL,DL
CH,CH
SI
01
MOVSB

CRANK_A:

128 IBM Enbanced Graphics Adapter

; MOVE ROWS OF PELS UP
SAVE DATA SEGMENT
SET DATA SEGMENT

SAVE MOVE COUNT
COLUMN COUNT
; CLEAR HIGH eYTE

; SAVE PO INTERS
; MOVE THAT ROW

12FO
12Fl
12F2
12F4
12f6
12F7
12F9
12FA
12FB
12FB
12FB
12FC
12FO
1300
1304
1305
1305
1306
1308
130A
130B
130C
130E
130F
1310
1312
1314
1315
1317
1318
1319
1319
1319
131A
131C
131E
1321
1324
1325
1327
1329
132B
132C
132E
132F
1331
1332
1334
1336
1338
133B
133C
133E
1340
1341
1343
1344
1345
1345
1345
1347
1349
134C
134F
1350

5F
5E
03 F3
03 FB
59
E2 EE
5B
C3

53
IE
E8 0001 R
BB 1 E 044A R

1F
51
8A CA
2A ED
56
57
F3/ A4
5F
5E
2B F3
2B FB
59
E2 EE
5B
C3

52
B6 03
B2 C4
B8 020F
E8 0018 R
5A
2B CO
8A CA
2A ED
57
F3/ AA
5F
8A C6
52
B6 03
B2 C4
B4 02
E8 0018 R
5A
BO FF
8A CA
57
F3/ AA
5F
C3

B6
B2
B8
E8
C3

03
C4
020F
0018 R

1350
1350

IE

1351
1354
1356
1358
1359
135A
135C
1360
1362
1363

E8
8A
2A
50
52
8B
F7
8B
5A
58

1364

1F

1365
1365

E8 1319 R

1368
1369
136C
1370
1371
1372
1374
1377
1378

0001 R
F7
FF
C3
26 0485 R
08

IE
E8 0001 R
03 3E 044A R

1f
4B
75 Fl
E8 1345 R
C3

1378
1378

IE

1379
137C
137E
1380
1381
1382
1384
1388
138A
138B

[8
8A
2A
50
52
8B
F7
8B
5A
58

138C

1F

1380
1380

E8 1319 R

1390
1391
1394
1398
1399
139A
139C

0001 R
F7
FF
C3
26 0485 R
08

IE
E8 0001 R
2B 3E 044A R

1f
4B
75 Fl
E8 1345 R

3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
31157
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
:>479
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509
3510
3511
3512
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

CRANK

POP
POP
AOO
ADD
POP
LOOP
POP
RET
ENOP

CRANK_ 4 PROC
PUSH
ASSUME
PUSH
CALL
MOV
POp
CRANK_B:
PUSH
MOV
SUB
PUSH
PUSH
REP
POP
POP
SUB
SUB
POP
LOOP
POP
RET
CRANK_ 4 ENOP
PART_l

PART_l
PART_2

PART_2
BLNK_3

01
SI
SI,BX
OI,BX
CX
CRANK_A
BX

BLNK_ 4

NEXT ROW
NEXT ROW
RECOVER ROW COUNT
DO MORE
RETURN TO CALLER

NEAR
BX
OS:ABSO
OS
DDS
BX, CRT_COLS
OS

;

MOVE ROWS 0 F PELS DOWN

;

SAVE DATA SEGMENT
SET DATA SEGMENT

SAVE MOVE COUNT
COLUMN COUNT
CLEAR HIGH BYTE
SAVE PO INTERS

CX
CL,OL
CH,CH
SI
01
MOVSB
01
SI
SI,BX
01, BX
CX
CRANK_B
BX

MOVE THAT ROW
RECOVER PO INTERS
NEXT ROW
NEXT ROW
RECOVER ROW COUNT
DO MORE
RETURN TO CALLER

PROC
PUSH
mav
MOV
MOV
CALL
POP
SUB
MOV

NEAR
OX
dh,3
OL, SEQ_AOOR
AX,020FH
OUT_OX
OX
AX,AX
CL,OL

sub

ch, ch

PUSH
REP
POP
MOV
PUSH
mav
MOV
MOV
CALL
POP
MOV
MOV
PUSH
REP

01
STOSB
01
AL,OH
OX
dh,3
OL, SEQ_AOOR
AH, 02H
OUT OX
OX AL,OFFH
CL,OL
01
STOS8

POP
RET
ENOP

01

PROC
mav
MOV
MOV
CALL
RET
ENOP

NEAR
dh,3
OL,SEQ_AOOR
AX,020FH
OUT_OX

PROC
PUSH
ASSUME
CALL
MOV
SUB
PUSH
PUSH
MOV
MUL
MOV
POP
POP

NEAR
OS
OS: ABSO
DOS
OH, BH
BH, BH
AX
OX
AX,BX
POINTS
BX,AX
OX
AX

POP
ASSUME

OS
OS: NOTH I NG

CALL
ASSUME
PUSH
CALL
ADD
POP
DEC
JNZ
CALL
RET
ENOP

PART 1
OS: ASSO
OS
DOS
OI,CRT_COLS
OS
BX
513
PART_2

S13:

BLNK_3

; RECOVER PO INTERS

FILL ROW AFTER SCROLL

;

SEQUENCER
MAP MASK
ALL MAPS ON
ZERO
COLUMN COUNT
SAVE PO INTER
CLEAR ONE ROW OF PELS
RECOVER PO INTER
GET COLOR VALUE
SEQUENCER
MAP MASK
SET THE COLOR
ALL BITS ON
COLUMN COUNT
SAVE PO INTER
TURN ON THOSE BI TS
ENABLED PLANES
RECOVER PO INTER
RETURN TO CALLER

IN

SEQUENCER
MAP MASK, ALL MAPS
ENABLE T,HE MAPS
RETURN TO CALLER
BLANK FOR SCROLL UP
SAVE DATA SEGMENT
GET LOW MEMORY SEGMENT
ATTRIBUTE FOR BLANK LINE
CLEAR HIGH BYTE
SAVE
SAVE BECAUSE OF MULT I PLY
ROW COUNT
CHARACTER HE I GHT
NET VALUE TO BX
RECOVER

BLANK OUT ROW WITH COLOR
SAVE SEGMENT
LOW MEMORY SEGMENT
NEXT ROW
RECOVER
NEXT
DO MORE
RETURN TO CALLER

PROC
PUSH
ASSUME
CALL
MOV
SUB
PUSH
PUSH
MOV
MUL
MOV
POP
POP

NEAR
OS
OS: ABSO
DOS
OH, BH
BH, BH
AX
OX
AX,BX
POI NTS
BX,AX
OX
AX

POP
ASSUME

OS
OS: NOTH I NG

CALL
ASSUME
PUSH
CALL
SUB
POP
DEC
JNZ
CALL

PART 1
OS:ASSO
OS
DDS
OI,CRTJOLS
OS
BX
S13 4
PART_2

BLANK FOR SCROLL DOWN
SAVE DATA SEGMENT
GET LOW MEMORY SEGMENT
ATTRIBUTE FOR BLANK LINE
CLEAR HIGH BYTE
SAVE
SAVE BECAUSE OF MULTIPLY
ROW COUNT
CHARACTER HE I GHT
NET VALUE TO BX
RECOVER

S13_4:
BLANK OUT ROW WITH COLOR
SAVE SEGMENT
LOW MEMORY SEGMENT
NEXT ROW
RECOVER
NEXT
DO MORE

IBM Enhanced Graphics Adapter 129

139F
13M

13AO
13M
13A2
13A5
13A6
13AA
13AO
13AF
13B2
13B2
13B3
13B5
13B8
13BA
13BC
13BE
13CO
13CO
13C3
13C5
13C7
13C9
13CB
13CB
13CC
13CE
13CE
1301
1303
1305
1307
1307
13DA
13Df
13El
13E4

C3

6A
E6
60
72
60
74
E9

06
16E6 R
FC 04
06
fC 07
03
1471 R

53
6B
E8
74
03
8A
2A

Cl
13Ef R
31
fO
E6
E3

E8
03
03
fE
75

142f R
F5
fO
CC
F5

58
BO 20
E8
03
fE
75

C6
F7

E8
80
74
AD
6A

0001 R
3E 0449 R 07
07
0465 R
0308

1438 R

fD

13E7 lEE
13E8
13E8
E9 2196 R
13EB
13E6 SA DE
13ED EB DC
13Ef

13Ef
13Ef
13f4

F6 06 0487 R 04
74 12

13F6
13F7
13F9
13fB
13FC

52
66 03
B2 DA
50

13FC
13FD
13FF
1401
1403

EC
A8
74
60
62

1405
1406
1407
1408
1408
140B
140F
1411
1413
1415
1417
1419
141B
141F
1421
1423
1427
1429
142A
142B
142E
142f

EE
58
5A

142f
142f
1431
1432
1433
1435
1436
1437
1438

1438
1438
143A
143B
1430

E8
03
86
8B
2B
fE
FE
32
8B
03
8A
F6
03
06
1F
80
C3

08
FB
25
08

1143 R
06 044E R
F8
FO
01
C6
C2

ED
2E 044A R

ED
C3
26 044A R
CO
FB 00

8A CA
56
57
f3/ A5
5F
5E
C3

8A CA
57
f3/ AB
5F

3529
3530
3531
3532
3533
3534
3535
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569
3570
3571
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583
35B4
3585
3586
3587
3588
3589
3590
3591
3592
3593
3594
3595
3596
3597
3598
3599
3600
3601
3602
3603
3604
3605
3606
3607
3608
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637
3638
3639
3640
3641
3642
3643
3644
3645
3646
3647
364B
3649
3650
3651
3652
3653
3654

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C+
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C+
C
C
C
C
C
C+
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

;

RET
ENOP

:-

~CiiOLL

;
;

RETURN TO CALLER

-ij;---------------------------------------------TH I S ROUT I NE MOVES A BLOCK OF CHARACTERS UP
ON THE SCREEN

INPUT

;

(AH)
(AL)
(CX)
(OX)
(BH)

ml

~
~

CURRENT CRT MODE
NUMBER Of ROWS TO SCROLL
ROW/COLUMN OF UPPER LEFT CORNER
ROW/COLUMN Of LOWER RIGHT CORNER
~ ATTR I BUTE TO BE USED ON BLANKED LINE
~

~

~ ~~~~NS~3~m

SEGMENT
; OUTPUT
;
NONE -- THE REGEN BUFFER I S MODI f I EO

;

-_ ... ---_ .. ---_ .............. -_ .. -_ ... --- -_ ... - ... -- -_ ... --_ ...... -_ ... ---- -_ ... -- .. _-

ASSUME
SCROLL UP
- MOV
CALL
CMP

CS: CODE, OS: ABSO, ES: NOTH I NG
PROC
NEAR
BL,AL
MK ES
AH-;-4

TEST FOR GRAPH I CS MODE

jb

nl

ha nd I e sepe ra te I y

CMP
JE
JMP

AH,7
Nl
CRAPH I CS_UP

TEST fOR BW CARD

PUSH
MOV
CAll
JZ
ADO
MOV
SUB

BX
AX,CX
SCROLL POS I T I ON
N7
SI,AX
AH,OH
AH,BL

CALL
ADO
ADO
DEC
JNZ

AH
N2

SAVE liNE COUNT IN Bl

UP CaNT I NUE
SAVE FILL ATTR IN BH
UPPER LEFT pas I T I ON
DO SETUP FOR SCROll
BLANK FIELD
FROM ADDRESS
H ROWS I N BLOCK
H ROWS TO BE MOVED
ROW_lOOP
MOVE ONE ROW

Nl:

N2:
Nl0
SI, BP

ot ,BP

NEXT liNE I N BLOCK
COUNT OF liNES TO MOVE
ROW_lOOP
CLEAR ENTRY
RECOVER A TTR I BUTE IN AH
Fill WI TH BLANKS
CLEAR lOOP
CLEAR-THE ROW
POINT TO NEXT LINE
LI NES TO SCROLL
CLEAR LOOP
SCROLL_END

N3:
POP
MOV

AX
AL,

CAll
ADD
DEC
JNZ

Nll
01, BP
BL
N4

CALL
CMP
JE
MOV
MOV
WOUT
OUT

DDS
CRT_MOOE,7
N6
AL, CRT MODE SET
OX,030SH
-

I

N4:

N5:

IS TH I S THE B/W CARD
SK I P THE MODE RESET
GET THE MODE SET
ALWAYS SET COLOR CARD

OX,AL
;

N6:
JMP

V_RET

MOV
JMP
SCROLL_UP

Bl,OH
N3
ENOP

VIDEO_RET_HERE
BLANK FIELD
GET ROW COUNT
GO CLEAR THAT AREA

N7:

; ----- HANDLE COMMON SCROLL SET UP HERE
SCROLL POS I T I ON PROC

- test

info,4

jz

NEAR

n9

; ----- 80X25 COLOR CARD SCROLL
PUSH
moy
MOV
PUSH
N8:

OX

dh,3
OL,OOAH
AX

wiN

;

COLOR CARD HERE

;

WAIT_OISP_ENABlE

AL,DX

IN
TEST
JZ
MOV
MOV
WOUT
OUT
POP
POP

WAIT FOR VERT RETRACE
WA IT _0 I SP _ENABLE

AL,8
N8
AL,25H
OL,D08H

DX~3D8

TURN OFf VIDEO
OX,AL
AX
OX

OUR I NG VERT I CAL RETRACE

N9:
CALL
ADD
MOV
MOV
SUB
INC
INC
XOR
MOV
ADO
MOV
MUL
ADO
PUSH
POP
CMP
RET
SCROLL_paS I T I ON

CONVERT TO REGEN PO INTER
OFFSET OF ACT I VE PAGE
TO ADDRESS FOR SCROLL
FROM ADDRESS FOR SCROll
OX ~ HROWS, HCOlS

POSI T I ON
AX, CRT_START
OI,AX
SI,AX
OX,CX
OH
Dl
CH,CH
BP, CRT_COLS
BP,BP
Al, BL
BYTE PTR CRT COlS

AX,AX

INCREMENT fOR a ORIGIN
ZERO HIGH BYTE OF COUNT
NUM Of COlS IN DISPLAY
TIMES 2 FOR ATTR BYTE
GET LI NE COUNT
OffSET TO FROM ADDRESS
*2 fOR A TTR I BUTE BYTE
ESTABLISH ADDRESSING
FOR BOTH PO INTERS
MEANS BLANK fiELD
RETURN WITH flAGS SET

-

ES
OS
Bl,O

a

ENOP

; ----- MOVE_ROW
Nl0

Nl0

PROC
MOV
PUSH
PUSH
REP
POP
POP
RET
ENDP

NEAR
Cl,Dl
SI
01
MOVSW
01
SI

;

GET

H

Of COlS TO MOVE

SAVE START ADDRESS
MOVE THAT LINE ON SCREEN
;

RECOVER ADDRESSES

;

GET

;

STORE THE fiLL CHARACTER

; ----- CLEAR_ROW
Nll

PROC
MOV
PUSH
REP
POP

NEAR
Cl,Dl
01
STOSW
01

130 IBM Enhanced Graphics Adapter

H

COLUMNS TO CLEAR

143E
143F

143F
143F
1440
1442
1445
1446
1448
144B

1440
144F
1451
1453
1453
1456
1458
145A
145C
145E
145E
145F
1461
1461
1464
1466
1468
146A
1460
1460
146F
1471

1471
1471
1473

C3

FD
8A
E8
53
6B
E6
74
2B
8A
2A

C2
13EF R
20
FO
E6
E3

E8
2B
2B
FE
75

142F R
F5
FD
CC
F5

08
16E6 R

56
BO 20
E8
2B
FE
75
E9

1438 R
FD
CB
F7
1307 R

8A DE
EB ED

SA 08
8B Cl

1475
1478

E8 16A4 R
8B F6

147A
147C
1480

2B 01
81 C2 0101
DO E6

1462

DO E6

1464
1469

80 3E 0449 R 06
73 04

146B
1460

148F
148F
1490
1491
1493
1495
1497
1499
149B

DO E2
01 E7

149F
14A1
14A3
14A5

06
1F
2A
DO
DO
74
8A
B4
F6
8B
03
8A
2A

ED
E3
E3
20
C3
50
E4
F7
FO
E6
E3

14A7
14A7
14AA
14AE
14B2
14B4

E8
81
81
FE
75

14CA R
EE 1FBO
EF 1FBO
CC
F1

1490

14B6
14B6
14B8

8A C7

3655
3656
3657
3656
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671
3672
3673
3674
3675
3676
3677
3676
3679
3660
3661
3682
3683
3684
3685
3686
3687
3688
3669
3690
3691
3692
3693
3694
3695
3696
3697
3696
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723
3724
3725
3726
3727
3726
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742'
3743
3744
3745
3746
3747
3748
3749
3750
3751
3752
3753
3754
3755
3756
3757
3756
3759
3760
3761
3762
3763
3764
3765
3766
3767
3768
3769
3770
3771
3772
3773
3774
3775
3776
3777
3776
3779
3760

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

RET
ENDP

NIl
;

_____ - - _ ............ -

;

- _ .. - - - _ .. - - - _ . . . . - _ .. - - - - - _ . . . . -

. . - - - - _ . . - _ .. oo - - - -

SCROLL DOWN
TH I S ROUT I NE MO'tES THE CHARACTERS WI TH I N A
DEF I NED BLOCK DOWN ON THE SCREEN, FILL I NG THE
TOP LINES WITH A DEFINED CHARACTER
INPUT
(AH) = CURRENT CRT MODE
(AL) = NUMBER OF LINES TO SCROLL
(CX) = UPPER LEFT CORNER OF REGION
(OX) = LOWER RIGHT CORNER OF REG I ON
(BH) = FILL CHARACTER

ml ~ ~~b~NS~~~~~~T

; OUTPUT
;
NONE -- SCREEN I S SCROLLED
§c~~~~-ii~iiN-----P~~C----NE~~-----------------------------

STD
MOV
CALL
PUSH
MOV
CALL
JZ

SCROLL DOWN
LINE COUNT TO BL

BL,AL
MK ES
BXAX, OX
SCROLL POS I T ION
N16-

SAVE ATTR 1BUTE IN BH
LOWER RIGHT CORN ER
GET REGEN LOCATION
, S I I S FROM ADDRESS
; GET TOTAL /I ROWS
; COUNT TO MOVE 1N SCROLL

SUB

SI,AX

MOV
SUB

AH,DH
AH, BL

CALL
SUB
SUB
DEC
JNZ

Nl0
SI, BP
01, BP
AH
N13

; MOVE ONE ROW

POP
MOV

AX
AL,

; RECOVER ATTR 1BUTE IN AH

CALL
SUB
DEC
JNZ
JMP

NIl

N13:

N14:
t

N15:

CLEAR ONE ROW
GO TO NEXT ROW

OI,BP
BL
N15
N5

N16:
MOV
JMP
SCROLL_DOWN

; ..

---_

-_

BL,DH
N14
ENDP

-_

-_

-_

-_

-_

--_

..
..........
.......... .............. ...... .................. ......
...... -- ..
SCROLL UP
THIS ROUTINE SCROLLS UP THE INFORMATION ON THE CRT
ENTRY
CH,Cl
UPPER lEFT CORNER OF REGION TO SCROLL
OH,DL = lOWER RIGHT CORNER OF REGION TO SCROLL
BOTH OF THE ABOVE ARE IN CHARACTER POSITIONS
BH = FILL VALUE FOR BLANKED LINES
Al = # LINES TO SCROLL (AL=O MEANS BLANK THE ENT I RE
FIELD)
OS = OAT A SEGMENT
ES = REGEN SEGMENT
EXIT
;
NOTH I NG, THE SCREEN I S SCROLLED
bR~P~
PR~C
NE~~

---_ ..

=

i CS -UP----MOV
MOV

----

:

-------------------------------------

BL, AL
AX,CX

SAVE LINE COUNT IN BL
GET UPPER LEFT POSITION
I NTO AX REG

; ----- USE CHARACTER SUBROUT I NE FOR POS I T I ON I NG
;----- ADDRESS RETURNED IS MULTI PLI ED BY 2 FROM CORRECT VALUE
CALL
MOV

SAVE RESULT AS
DESTINATION ADDRESS

;----- DETERMINE SIZE OF WINDOW
SUB
ADD
SAL

DX,CX
DX,101H
DH, I

SAL

DH, I

ADJUST VALUES
MULT I PLY II ROWS BY 4
SINCE B VERT DOTS/CHAR
AND EVEN/ODD ROWS

; ----- DETERM I NE CRT MODE
CMP
JNC

CRT MODE,6
R7 -

TEST FOR MED I UM RES
F I NO_SOURCE

;----- MEDIUM RES UP
SAL
SAL

Dl,l
01,1

* SINCE
2

2 BYTES/CHAR

; ----- DETERM I NE THE SOURCE ADDRESS I N THE BUFFER
R7:
PUSH
POP
SUB
SAL
SAL
JZ
MOV
MOV
MUL
MOV
ADD
MOV
SUB

ES
OS
CH,CH
BL, I
BL,1
Rl1
AL, BL
AH,80
AH
SI,DI
SI,AX
AH,OH
AH, BL

FIND SOURCE
GET SEGMENTS BOTH
PO I NT I NG TO REGEN
o TO HIGH OF COUNT REG
NUMBER OF LINES *4
I F 0, BLANK ENT 1 RE FIELD
NUMBER OF LINES IN AL
80 BYTES/ROW
OFFSET TO SOURCE
SET UP SOURCE
ADD I N OFFSET TO IT
NUMBER OF ROWS IN FIELD
DETERM I NE NUMBER TO MOVE

;----- LOOP THROUGH, MOVING ONE ROW AT A TIME, BOTH EVEN AND ODD FIELDS
R8:
CALL
SUB
SUB
DEC
JNZ

R17
S I ,2000H-60
01,2000H-60
AH
R8

ROW LOOP
MOVE ONE ROW
MOVE TO NEXT ROW
NUMBER OF ROWS TO MOVE
CONT I NUE TILL ALL MOVED

Fill IN THE VACATED LINE(S)
R9:
MOV

Al, BH

CLEAR ENTRY
ATTRIBUTE TO FILL WITH

RIO:

IBM Enhanced Graphics Adapter 131

14B8
14BB
14BF
14Cl
14C3
14C6
14C6
14C8
14CA

14CA
14CA
14CC
14CO
14CE
1400
1401
1402
1406
140A
140B
140C
140E
14£0
14El
14E2
14E3

14E3
14E3
14£5
14E6
14E8
14E9
14£0
14£E
14FO
14F2
14F3
14F4

E8
81
FE
75
E9

14E3 R
EF 1 FBO
CB
F5
219B R

8A DE
EB EC

8A CA
56
57
F3/ A4
SF
5£
81 C6 2000
81 C7 2000
56
57
8A CA
F3/ A4
5F
5E
C3

SA CA
57
F3/ AA
5F
81 C7 2000
57
8A CA
F3/ AA
5F
C3

14F4
i4F4
14F5
14F6
14F9
14FO
1500
1501
1502
1504
1505
1506
1506
1507
1508

1508
1508

50

1E
E8 0001 R
8A 26 0487 R
SO E4 60

1F
58
74 02
F9 i
C3
F8
03

E9 13AC R

150B
150B
150E
1512
1515

1517
151A

1510

[8
8A
80
76
80
73
E9

120E R
26 0449 R
FO 07
Fl
FC 00

17
219B

R

151F
151 F
1522
1525
1528
152A
1520
152F
1532
1532
1533

BA
BD
80
72
E8

ACOO
0511
FO OF
08
14F4 R
73 03
SO 0501

03

1533
1533
1534

52
E8 151 F R

1537
1539
153A
153C
153E
153F
1543
1546
1547
1549
154B
154F
1551
1553
1554
1558
155C
155E

8E
5A
8A
8B
53
SA
E8
5B
8B
2B
81
2A
8A
52

1560
1561
1562
1563
1565
1567

02
08
Cl

3£ .0462 R
1603 R
F8
01
C2 01bl
E4
C3

0 26 0485 R
F7 26 044A R

8B F7
03 FO
06

1F

156B

5A
OA
14
8A
2A
2A

1560
156E

1E
E8 0001 R

1569

DB
3F
CE
CB
EO

3781
3782
3783
3784
3785
3786
3787
3788
3789
3790
3791
3792
3793
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806
3807
3808
3809
3810
3811
3812
3813
3814
3815
3816

3817
3818
3819
3820
3821
3822
3823
3824
3825
3826
3827
3828
3829
3830
3831
3832
3833
3834
3835
3836
3837
3838
3839
3840
3841
3842
3843
3844
3845
3846
3847
3848
3849
3850
31i51
3852
3853
3854
3855
3856
3857
3858
3859
3860
3861
3862
3863
3864
3865
3866
3867
3868
3869
3870
3871
3872
3873
3874
3875
3876
3877
3878
3879
3880
3881
3882
3883
3884
3885
3886
3887
3888
3889
3890
3891
3892
3893
3894
3895
3896
3897
3898
3899
3900
3901
3902
3903
3904
3905
3906

C
C

o

C
C
C
C

o
o
o
o
o
o
C
t

MOV

BL,DH
R9
ENDP

R17

PROC
MOV
PUSH
PUSH
REP
POP
POP
ADD
ADD
PUSH
PUSH
MOV
REP
POP
POP
RET
ENDP

R18

PROC
MOV
PUSH
REP
POP
ADD
PUSH
MOV
REP
POP
RET
ENOP

mem_det

~~~~me
push
push
ca 11
may
and
pop
pop

C
C
C
C
G

o

jz
§tc

C
C
C

NEAR
CL,DL
SI
01
MOVSB
01
SI
SI,2000H
DI,2000H
SI
01
CL,OL
MOVSB
01
SI

BLANKJ I ELD
SET BLANK COUNT .TO
.EVERYTHING IN.fIELD
OLEAR THE f I ELO

;

NUM OF BYTES I N THE ROW
SAvE PO INTERS
MOVE THE EVEN F I ELO

POINT TO THE ODD FIELD
SAVE THt PO INTERs
COUNT BACK
MOVE THE ODD F I ELO
PO I NTERS BACK
RETURN TO CALLER

NEAR
CL,DL
01
STOSB
01
DI,2000H
01

NUMBER OF BYTES IN FIELD
SAVE PO INTER
STORE THE NEW VALUE
PO I NTER BACK
POINT TO ODD FIELD

CL, bL

FILL THE ODD F I LELD

STOSB
01

RETURN TO CALLER

hear
ds;absO

ax
ds
dds

ah, i f)fo
ah,060h
ds
min

ret

min:
c Ie

C
C
C
C

mem_det endp

C

; ----- SCROLL ACT IVE PAGE UP

o

,
;
;
;

;---"- CLEM A SINGLE ROW
R18

C

C
C
C
C
C
C
C
C
C
C
C
C
C
C

CLEAR THAT ROW
POINT TO NEXT LINE
NUMBER OF LI NES TO fiLL
CLEAR_LOOP

;----- ROUTINE TO MOVE ONE ROW OF INFORMATION

R17

c

C

R18
DI,2000H-80
BL
Rl0
V_RET

Rll :

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

CALL
SUB
DEC
JNZ
JMP

ret

JMP
AH6:
ASSUME
CALL
MOV
CMP
JBE
CMP
J.A£
JMP
GR ST 1 PROC
MaV

C
MOV
C
C
ClOp
G
Jb
ea II
G
jne
C
MOV
C
C VVJ:
REt
C
C GR ST 1 ENDP
C
C GRAPH I CS UP 2
ASSUME
C
PUSH
C
CALL
C
SRLOAD
C
C+
MOV
POP
C
C
MOV
MOV
C
C
PUSH
C
MOV
CALL
C
POP
C
C
MOV
C
SUB
C
ADD
SUB
C
MOV
C
PUSH
C
MUL
C
MUL
C
MOV
C
ADD
C
ASSUME
C
PUSH
C
POP
C
POP
C
OR
C
JZ
C
MDV
C
SUB
C
SUB
C
C
ASSUME
C
PUSH
C
CALL
C

DS:ABSO
FLTA
AH, CRT _MODE
AH,07H
SC 2
AH-;-ODH
GRAPH I CS_UP_2
V_RET

;

GET CURRENT MODE

;

ANY OF THE OLD MODES
NEW GRAPH I CS MODES
NOT A RECOGN I ZED MODE

NEAR
OX,OAOOOH
BP,0511H

REGEN BUFFER
GRAPH I CS WR I TE MODE

ah,.Ofh

vv1

mem det

vv'-

GRAPH I CS WR I TE MODE

BP,0501H

PROC
NEAR
OS: ABSO
OX
GR ST 1
ES- ES,DX
OX
BL,AL
AX,CX
BX
BH,ACTIVE_PAGE
ORX PSN
BX DI,AX
DX,CX
DX,OldlH
AH,AH
AL, BL
OX
POINTS
CRT COLS
SI,OI
SI,AX
OS:NOTHING
ES
OS
OX
BL, BL
AR9
CL,DH
CL, BL
CHICH
OS: ABSO
OS
DDS

132 IBM Enhanced Graphics Adapter

SET SEGMENT, WR I TE MODE
SET REGEN
NUMDER OF LI NES
UPPER LEFT CORNER
!mnS P~~E R~g~N SjROLL
SET PO I NTER
OETERM I NE WINDOW
ADJUST
ZERO HIGH BYTE
LINE COUNT

I

,

BYTES PER CHARACTER

;

COLUMNS

; SET UP SOURCE INDEX
; ADJUST

LI NE COUNT

LOW MEMORY SEGMENT

1571
1572
1573
1575
1579
157B
157C

50
52
8B Cl
F7 26 0485 R
BB C8
5A
58

157D

IF

157E
157F
1581
1583
1585
1588
158A
158D
1590
1591

52
8B
B6
B2
E8
B2
B8
E8
5A
E8

1594
1595
1596
1598
159A
159C
159F
15AO
15AO
15A3
15A6
15A6
15A8
15AA

52
40
8B
B6
B2
E8
5A

15AA
15AA

C5
03
CE
OD18 R
C4
020F
0018 R
1200 R

C5
03
CE
OD18 R

E8 1350 R
E9 219B R
8A DE
EB F6

E9 143F R

15AO
15AO
15BO
15B4
15B7
15B9
15BC

E8
8A
80
76
80
74

12CE R
26 0449 R
FC 03
Fl
FC 07
EC

15BE
15C1
15C3
15C6
15C8
15CA
15CC
15CC

80
73
80
77
B4
CO

FC 00
DC
FC 06
04
07
42

E9 219B R

15CF
15CF
1500
1502
1503

8A 08
52
E8 151 F R

1506
1508
1509
150B
1500
150E
15E2
15E5
15E6
15EA
15EC
15EE
15F2
15F4
15F6
15F7
15FB
15FF
1601

8E
5A
8B
FE
53
8A
E8
5B
2B
8B
2B
81
2A
8A
52
F7
F7
8B
2B

1603
1604
1605
1606
1608
160A
160C
160E

06

1610
1611
1614
1615
1616
1618
161C
161E
16,.

1E
E8
50
52
8B
F7
8B
5A
58

FD

C2
C2
C4
3E 0462 R
16C3 R
06 044A R
F8
Dl
C2 0101
E4
C3
26 0485 R
26 044A R
F7
FO

,.

5A
OA
74
6A
2A
2A

1620

,.

1621
1622
1624
1626
1628
162B
1620
163O
1633
1634

52
8B
B6
B2
E8
B2
B8
E8
5A
E8

1637
1638
1639
163B
163D
163F
1642
1643

52
40
8B
B6
82
E8
5A

DB
40
CE
CB
ED

0001 R
C1
26 0485 R
C8

C5
03
CE
OD18 R
C4
020F
OD18 R
12FB R

C5
03
CE
0018 II

3907
3908
3909
3910
3911
3912
3913
3914
3915
3916
3917
3918
3919
3920
3921
3922
3923
3924
3925
3926
3927
3928
3929
3930
3931
3932
3933
3?34
3935
3936
3937
3938
3939
3940
3941
3942
3943
3944
3945
3946
3947
3948
3949
3950
3951
3952
3953
3954
3955
3956
3957
3958
3959
3960
3961
3962
3963
3964
3965
3966
3967
3968
3969
3970
3971
3972
3973
3974
3975
3976
3977
3978
3979
3980
3981
3982
3983
3984
3985
3986
3987
3988
3989
3990
3991
3992
3993
3994
3995
3996
3997
3998
3999
4000
4001
4002
4003
4004
4005
4006
4007
4008
4009
4010
4011
4012
4013
4014
4015
4016
4017
4018
4019
4020
4021
4022
4023
4024
4025
4026
4027
4028
4029
4030
4031
4032

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C+
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

C

PUSH
PUSH
MOV
MUL
MOV
POP
POP
ASSUME
POP

AX
DX
AX,CX
POINTS
CX,AX
DX
AX
DS:NOTHING
DS

PUSH
HOV
mov
MOV
CALL
MOV
MOV
CALL
POP
CALL

DX
AX,BP
dh,3
DL, GRAPH_ADDR
OUT DX
DL,SEQ_ADDR
AX,020FH
OUT_OX
DX
CRANK

PUSH
DEC
MOV
mov
MOV
CALL
POP

OX
BP
AX,BP
dh,3
OL, GRAPH_ADDR
OUT_DX
OX

CALL
JMP

BLNK 3
V_RET

;
;

BYTES PER CHAR
SET THE COUNT

; GRAPHICS
SEQUENCER
ENABLE ALL MAPS
SCROLL THE SCREEN

ARlO:
AR9:
MOV
JMP
GRAPH I CS_UP_2

BLANK ENT I RE WI NOOW

BL,OH
ARlO
ENOP

;----- SCROLL ACTIVE DISPLAY PAGE DOWN
SC_3:
JMP

SCROLL_DOWN

ASSUME
CALL
MOV
CMP
JBE
CMP
JE

OS:ABSO
FLTA
AH, CRT _MODE
AH,03H
SC 3
AH~07H
SC_3

CMP
JAE
CMP
JA
MOV
I NT

AH,OOH
GRAPH I CS_DN_2
AH,06H
M_O
AH,07H
42H

JMP

V_RET

AH7:

; OLD COLOR ALPHA
; MONOCHROME ALPHA
; NEW GRAPH I CS MODES
; OLD GRAPH I CS MODES

M_O:
GRAPH I CS_ON_2
STD
MOV
PUSH
CALL
SRLOAO
MOV
POP
MOV
INC
PUSH
MOV
CALL
POP
SUB
MOV
SUB
ADD
SUB
MOV
PUSH
MUL
MUL
MOV
SUB
ASSUME
PUSH
POP
POP
OR
JZ
MOV
SUB
SUB

PROC

NEAR

BL,AL
OX
GR_ST_1
ES
ES,OX
OX
AX,OX
AH
BX
BH,ACTIVE_PAGE
GRX_PSN
BX
AX, CRT _COLS
OI,AX
DX,CX
DX,0101H
AH,AH
AL,BL
DX
POI HTS
CRT COLS
51,51
51 ,AX
OS: NOTH I NG
ES
DS
DX
BL, BL
DXR9
CL,OH
CL,BL
CH,CH

ASSUME
PUSH
CALL
PUSH
PUSH
MOV
MUL
MOV
POP
POP
ASSUME
POP

OS:ABSO
DS
DDS
AX
DX
AX,CX
PO I NTS
CX,AX
DX
AX
OS: NOTH I NG
OS

PUSH
MOV
mov
MOV
CALL
MOV
MOV
CALL
POP
CALL

dh,3
DL, GRAPH_AOOR
OUT OX
OL,SEQ_AOOR
AX,020FH
OUT_OX
OX
CRANK_4

PUSH
DEC
MOV
mov
MOV
CALL
POP

OX
BP
AX,BP
dh,3
OL, GRAPH_AOOR
OUT_OX
OX

; DIRECT i ON TO DECREMENT
; LI NE COUNT
; SAVE LOWER RIGHT
;

SET REGEN SEGMENT

; MOV CHAR ROW UP BY ONE
; ADDRESS I N REGEN
; ONE SCAN OVERSHOOT
; CALCULATE WINDOW
; ADJUST COUNT

;

BYTES PER CHAR

;

BYTES PER ROW

SET OS TO
THE REGEN SEGMENT
SCROLL COUNT
BLANK ENTIRE WINDOW

BYTES PER CHAR

OX

AX,BP
; GRAPHICS
SEQUENCER
ENABLE ALL MAPS
SCROLL THE SCREEN

OXR10:

IBM Enhanced Graphics Adapter 133

1643
1646
1647
164A
164A
164C
164E

164E
164E
1650
1652
1654
1656
165A
165C
165E
165E
1662
1664
1664
1667
1669
16M

16M
16M
1660
166F
1670
1673
1673
1675
1677
1679
1678
1670
167E
167f

i67f
167f
1680
1681
1682
1684
1687
1687
1689
168B
1680
168f
1691
1693
1695
1697

E8 1378 R
FC
E9 219B R
8A DE
EB F5

8A
32
8B
01
8B
33

CF
ED
Fl
E6
84 0450 R
DB
[3 06

03 lE 044C R
E2 FA
E8 1143 R
03 08
C3

80 [3 03
8A C3
51
B9 0003
DO EO
DO EO
OA 08
E2 f8
8A fB
59
C3

52
51
53
28 02
B9 0001
8B
23
OB
01
01
8B
23
OB
01

08
09
03
EO
E1
08
09
03
E1

1699

73 EC

169B
1690
169E
169f
16AO
16A1

8B C2
5B
59
5A
C3

16A1
16Al
16A4
16A4
16A5
16A7
16A9
16AO

16M
16B1
16B3
16B5
16B6
16B7

A1 0450 R
53
8B
8A
f6
01
01
2A
03
5B
C3

08
C4
26 044A R
EO
EO
ff
C3

16B7
16B7
16B8
16BA
16BC
16BE
16C2

53
8A
2A
01
8B
5B

Of
ff
[3

87 0450 R

4033
4034
4035
4036
4037
4038
4039
4040
4041
4042
4043
4044
4045
4046
4047
4048
4049
4050
4051
4052
4053
4054
4055
4056
4057
4058
4059
4060
4061
4062
4063
4064
4065
4066
4067
4068
4069
4070
4071
4072
4073
4074
4075
4076
4077
4078
4079
4080
4081
4082
4083
4084
4085
4086
4087
4088
4089
4090
4091
4092
4093
4094
4095
4096
4097
4098
4099
4100
4101
4102
4103
4104
4105
4106
4107
4108
4109
4110
4111
4112
4113
4114
4115
4116
4117
4118
4119
4120
4121
4122
4123
4124
4125
4126
4127
4128
4129
4130
4131
4132
4133
4134
4135
4136
4137
4138
4139
4140
4141
4142
4143
4144
4145
4146
4147
4148
4149
4150
4151
4152
4153
4154
4155
4156
4157
4158

CALL
CLO
JHP

BLNK_4
V_RET

OXR9:
HOV
JHP
GRAPH I CS_ON_2

;

BL,OH
OXR10
ENDP

BLANK ENT I RE WINDOW

SUBTTL

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

INCLUDE
VGRW. I HC
SUBTTL VGRW. INC
PAGE
ASSUME
fiNO POSITION
MOV
XOR
MOV
SAL
MOV
XOR
JCXZ
P4:
ADD
LOOP
P5:
CALL
ADO
RET
f I NO_POSIT ION

; ----- - --

OS: ABSO
PROC
NEAR
CL,BH
CH,CH
SI,CX
SI,1
AX, [S I + OffSET CURSOR_POSN J
BX,BX
P5
BX, CRT_LEN
P4
POSITION
BX,AX

;

DISPLAY PAGE TO CX
HOVE TO S I fOR INDEX
2 fOR WORD OffSET
ROW/COLUMN Of THAT PAGE
SET START ADDRESS TO 0
NO PAGE
PAGE LOOP
LENGTH Of BUffER

*

NO_PAGE
DETERM I NE LOC I N REGEN
ADD TO START Of REGEN

ENDP

--- - --- - - - ---- -- - - - - - - - - -- -- - -- -- - --- - --- - -- -- --

EXPAND MEO COLOR
THIS-ROUTINE EXPANDS THE LOW 2 BITS IN BL TO
fiLL THE ENT I RE BX REG I STER
ENTRY
BL = COLOR TO BE USED ( LOW 2 BITS)
EXI T
;
~XC~Lg~Lg~T~O)BE USED ( 8 REPLICATIONS Of THE

:

§i9-----;ROC----~[~R-------------------------------------

AND
MOV
PUSH
MOV

BL,3
AL, BL
CX
CX,3

SAL
SAL
OR

AL,1

ISOLATE THE COLOR BITS
COpy TO AL
SAVE REG I STER
NUMBER Of TIMES

S20:

AL,l
BL,AL

LOOP
S20
BH, BL
MOV
POP
CX
RET
ENOP
S19
-[~;~~~-~~T[------------------

g;

LEfT SHIfT BY 2
ANOTHER COLOR VERSION
INTO BL
fiLL ALL Of BL
fiLL UPPER PORT ION
REG I STER BACK
ALL DONE

--------------------------

c;
THIS ROUTINE TAKES THE BYTE IN AL AND DOUBLES
C;
ALL Of THE 81 TS, TURN I HG THE 8 BITS INTO
C;
16 BITS. THE RESULT '$ LEfT IN AX
:
C ; ------------------ -------------- -----------------------C S21
PROC
NEAR
; SAVE REG I STERS
C
PUSH
OX
C
PUSH
CX
C
PUSH
BX
RESULT REG I ST[R
C
SUB
OX, OX
MASK REG I STER
C
HOV
CX,1
C S22:
BASE I NTO TEMP
MOV
BX,AX
C
USE MASK TO EXTRACT BIT
BX,CX
C
AND
PUT I NTO RESULT REG I STER
OR
OX,BX
C
SHL
AX,l
C
SH I fT BASE AND MASK BY 1
CX,1
SHL
C
BASE TO TEMP
MOV
BX,AX
C
EXTRACT THE SAME BIT
AND
BX,CX
C
PUT INTO RESULT
OR
OX,BX
C
SH I fT ONLY MASK NOW,
SHL
CX,1
C
MOV I NG TO NEXT BASE
C
USE MASK BIT COM I NG OUT
C
JNC
S22
TO TERM I NATE
C
RESULT TO PARM REG I STER
AX,OX
MOV
C
POP
C
BX
; RECOVER REG I STERS
CX
POP
C
POP
OX
C
; ALL DONE
RET
C
ENDP
C S21
C
PROC
NEAR
C S26
; GET CURRENT CURSOR
AX, CURSOR_POSN
MOV
C
LABEL
NEAR
C GRAPH_POSN
SAVE REG I STER
PUSH
BX
C
SAVE A COPY Of CURSOR
MOV
BX,AX
C
GET ROWS TO AL
MOV
AL,AH
C
MULT I PLY BY BYTES/COLUMN
BYTE PTR CRT COLS
MUL
C
AX,1
*4 SINCE 4 ROWS/BYTE
SHL
C
AX,1
SHL
C
I SOLA TE COLUMN VALUE
SUB
BH, BH
C
DETERM I NE OffSET
ADO
AX,BX
C
RECOVER PO INTER
POP
BX
C
ALL DONE
RET
C
ENDP
C S26
C
C
-~R
C
C
ENTRY
C ; EXIT BH = DISPLAY PAGE
C
AX = CURSOR POS I T I ON fOR REQUESTED PAGE
C
C bR=CUR~---------------------------------------------------------C
ASSUME OS: A8S0
C
PUSH
BX
, SAVE REG I STER
C
MOV
BL, BH
; GET TO LOW BYTE
C
SUB
BH,BH
; ZERO HIGH BYTE
C
SAL
BX,1
; *2 fOR WORD COUNT
C
MOV
AX, [BX + OffSET CURSOR_POSN J
; CURSOR, REQUESTED PAGE
C
C
~~ ~
~~
~ ~~?~~~~ ~ ~~ ~:~ ~R
C
GRX PSN
C
C
ENTRY
AX = CURSOR POS I T I ON I N DES I RED PAGE
C
BH
DES I REO PAGE
C
EXIT
C
AX = BYTE OfFSET I NTO REGEN
C

;

-CUR -- -------------- -------------------------------- ---------

;_______

_____ ______________________________ _

=

134 IBM Enhanced Graphics Adapter

_

16C3
16C3
16C4
16C5
16C6
16C8
16CA
16CC
16CE

1602
1606
1608
16DA
16DE
16EO
16ED
16E2
16E4
16E4
16E5
16E6
16[7
16E8
16E8
16E8
16EB
16EF
16F3
16F6

lM8
1MB
16FB
16FO

53
51
52
2A
8A
8B
8A
F6
F7
2A
03
8B
E3

EO
CF
08
C4
26 044A R
26 0485 R
FF
C3
1 E 044C R
04

03 C3
E2 FC
5A
59
5B
C3

BE
8B
81
83
75
BE

B800
3E 0410 R
E7 0030
FF 30
03
BOOO

8E C6
C3

16FE
16FE
1701
1704

E8 16E8 R
E8 164E R
8B F3

1706
170A

8B 16 0463 R
83 C2 06

1700

F6 06 0487 R 04

1712
1713

06
1F

1714

74 OB

1716
1716
1717
1719
171B
171C

EC
A8 01
75 FB
FA

171C
1710
171F
1721
1721
1722
1725

EC
A8 01
74 FB
AD
E9 219B R

4159
4160
4161
4162
4163
4164
4165
4166
4167
4168
4169
4170
4171
4172
4173
4174
4175
4176
4177
4178
4179
4180
4181
4182
4183
4184
4185
4186
4187
4188
4189
4190
4191
4192
4193
4194
4195
4196
4197
4198
4199
4200
4201
4202
4203
4204
4205
4206
4207
4208
4209
4210
4211
4212
4213
4214
4215
4216
4217
4218
4219
4220
4221
4222
4223
4224
4225
4226
4227
4228
4229
4230
4231
4232
4233
4234
4235
4236
4237
4238
4239
4240
4241
4242
4243
4244
4245
4246
4247
4248
4249
4250
4251

4252

1725
1725
1727
172A

8A 24
8A 44 01
89 COOO

1720
172F
172F
1731

85 Cl
F8

1732
1734
1735
1735
1737
1739

B2 00

74 01
F9
00 D2
01 E9
01 E9

173B

73 F2

173D
1740
1741
1742

88 56 00
45
C3

1742
1742
1745

E8 16E8 R
E8 16Al R

4253
4254
4255
4256
4257
4258
4259
4260
4261
4262
4263
4264
4265
4266
4267
4268
4269
4270
4271
4272
4273
4274
4275
4276
4277
4278
4279
4280
4281
4282
4283
4284

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

&iix -psi; -piio~ ----i; E;ii ---------------------------------------------

C

GP _2:

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

POP
POP
POP
RET
GRX_PSN ENDP

-

g

BX
CX

SAVE
SAVE

CH,CH
CL, BH
BX, AX

ZERO
PAGE NUMBER
ROW, COLUMN

~V

~~

~W

MUL
MUL
SUB
ADO
MOV
JCXZ

BYTE PTR CRT COLS
PO I NTS
BH, BH
AX, BX
BX, CRT_LEN
GP _2

ROW
COLUMNS/ROW
BYTES PER ROW
ZERO TO LEAVE COL VALUE
ADO I N COLUMN
PAGE LENGTH
NO PAGE OFFSET

~~

~

U~

GP_3:

*

ADD I N THE PAGE LENGTH
00 FOR NUMBER OF PAGES

ADO
LOOP

RECOVER
RECOVER
RECOVER

OX
CX
BX

HK_ES:
MOV
MOV
AND
CMP
JNE
MOV

S I, OBBOOH
01, EQU I P_FLAG
0l,030H
DI,030H
P6 A
SI-;-OBOOOH

MOV
RET

ES,SI

P6_A:

;-iiEAii=A~=~uiiRE;; T---------------------------------------;

gC ; INPUT
C
C

PUSH
PUSH
SUB
MOV
MOV

TH I S ROUT I NE READS THE A TTR I BUTE AND CHARACTER
•
AT THE CURRENT CURSOR pas I T I ON AND RETURNS THEM :
TO THE CALLER

= CURRENT CRT MODE

I AH)
IBH)
(DS)
;OUTPUT I (5)

= DISPLAY PAGE I ALPHA HODES ONLY)
= DATA SEGMENT

= REGEN SEGMENT

=

C
(AL)
CHAR READ
C;
IAH) = ATTRIBUTE READ
C • ------------- ------------------------------------------C
ASSUME
CS:CODE,DS:ABSO,ES:NOTHING
C READ AC CURRENT PROC
NEAR
C
-CALL
MK ES
C
CALL
FINO POSITION
; ADDRESSING IN SI
C
MOV
SI,BX
C
GET BASE ADDRESS
OX, AODR_6845
MOV
C
POINT AT STATUS PORT
ADD
DX,6
C
C
info,4
test
C
C
PUSH
ES
C
SEGMENT FOR QU I CK ACCESS
DS
POP
C
C
jz
p3.
C
C
C ;----- WAIT FOR HORIZONTAL RETRACE
C
WA I T FOR RETRACE LOW
C P2:
GET STATUS
WIN
C
AL,OX
C+
IN
, I S HaRZ RETRACE LOW
AL,l
TEST
C
; WA I T UNT I LIT I S
P2
JNZ
C
; NO MORE I NTERRUPT5
CLI
C
; WA I T FOR RETRACE HIGH
C P3:
; GET STATUS
WIN
C
AL,DX
IN
C+
IS IT HIGH
AL,l
TEST
C
WA IT UNT I LIT I S
JZ
P3
C
C p3.:
; GET THE CHAR/ATTR
C
LODSW
C
JMP
V RET
C READ_AC_CURRENT ENDP
C
C
~Eii=REAii=ii~TE
C
THI5 ROUTINE WILL TAKE 2 BYTES FROM THE REGEN
C ,
BUFFER, COMPARE AGAI NST THE CURRENT FOREGROUND
C ;
COLOR, AND PLACE THE CORRESPOND I NG ON/OFF BIT
C ;
PATTERN INTO THE CURRENT POSITION IN THE SAVE
C ;
AREA
C ;
ENTRY
C
S I, DS = PO I NTER TO REGEN AREA OF INTEREST
C
BX = EXPANDED FOREGROUND COLOR
C
BP = PO I NTER TO SAVE AREA
C
EXI T
C
BP I S I NCREMENT AFTER SAVE
:
C ;
C ~23-----PRO~----;;EAR------------------------------------C
MOV
AH, (S I J
GET FIRST BYTE
C
MOV
AL, (S I +1 J
GET SECOND BYTE
C
MOV
CX,OCOOOH
2 BIT MASK TO TEST
C
THE ENTR I ES
C
RESULT REG I STER
DL,O
C
MOV
C 524:
IS TH I S BACKGROUND?
AX,CX
TEST
C
CLEAR CARRY I N HOPES
CLC
C
THAT IT IS
C
5
525
C
JZ
~~5~1 T: T s6 s~~C~~~~~NO
STC
C

;-

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

------------------------------------------

S25:

S23

MOVE THAT BIT I NTO THE
RESULT
MOVE THE MASK TO THE
RIGHT BY 2 BITS
DO IT AGAIN IF MA5K
DIDN'T FALL OUT
STORE RESULT I N SAVE
ADJUST PO INTER
ALL DONE

DL,l
CX,l
CX,l

RCL
5HR
SHR
JNC

524

MOV
INC
RET
ENDP

( BP],DL
BP

GRAPH I CS READ
CALL
CALL

PROC
MK ES
S26

NEAR
CONVERTED TO OFFSET

IBM Enhanced Graphics Adapter 135

1748
174...

8B fO
83 EC DB

1740

8B EC

174f
1754
1755
1756

BO 3E 0449 R 06
06
1f
72 1.0.

1758
175.0.
175.0.
175C
175f
1760
1764
1767
1768
1768
1760
176F

1772
1772
1774
1776
1776

B6 04
SA
B8
45
8.0.
88
45
83
FE
75
EB

04
46 00
84 2000
46 00
C6 50
CE
EB
17 90

01 E6
B6 04
E8 1725 R

1779
1770
1780
1784
1786

61
E6
81
FE
75

C6 2000
1725 R
EE 1 FBO
CE
EE

1788
1788
1769

IE
E8 0001

178C
1790
1791

C4 3E 010C R
1f
83 ED 08

1794
1796
1797
1799
1799
179A
179B
179E
179E
179F
17AO
17A3
17A5
17.0.6
17.0.7

8B F5
FC
BO 00
16
1f
BA 0080
56
57
B9 0006
F3/ .0.6
5F

5E
74 10

17.0.9
17AB
17AE
17AF

FE CO
63 C7 06
4A
75 ED

17Bl

3C 00

1763

74 11

17B5

E8 0001

17B6
17°C
17BE
17CO
17C2
17C4

C4
6C
DB
74
BO
EB

17C6
17C6

63 C4 06

17C9
17CC

17CC
17CC

R

R

3E 007C R
CO
C7
04
80
03

E9 219B R

E9 16FE R

17CF
17CF
1703
1706
1706
170B
1700
17EO
17E2
17E5 I
17E5 •

6.0.
80
74
80
76
60

26
FC
F4
FC
EF
FC

0449 R
07
03
06

{~ ~~42

~ml ~~ ~~F4

17ED
17EF
17Fl
17F4
17F6
17F8

R

80 FC OF
72
EB
80
73
BO
E9

R

40
0.0.
FC 00
46
00
219B R

4285
4286
4287
4288
4289
4290
4291
4292
4293
4294
4295
4296
4297
4298
4299
4300
4301
4302
4303
4304
4305
4306
4307
4308
4309
4310
4311
4312
4313
4314
4315
4316
4317
4318
4319
4320
4321
4322
4323
4324
4325
4326
4327
4326
4329
4330
4331
4332
4333
4334
4335
4336
4337
4338
4339
4340
4341
4342
4343
4344
4345
4346
4347
4348
4349
4350
4351
4352
4353
4354
4355
4356
4357
4356
4359
4360
4361
4362
4363
4364
4365
4366
4367
4366
4369
4370
4371
4372
4373
4374
4375
4376
4377
4376
4379
4380
4381
4382
4383
4384
4385
4386
4387
4368
4389
4390
4391
4392
4393
4394
4395
4396
4397
4398
4399
4400
4401
4402
4403
4404
4405
4406
4407
4408
4409
4410

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C+
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C+
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

C
C
C

MOV
SUB

SI,AX
SP,8

MOV

BP,SP

S"'VE IN SI
; ... LLOC ... TE SP ...CE TO S...VE
THE READ CODE PO I NT
PO I NTER TO SAVE AREA

; ----- DETERM I NE GRAPH I CS MODES
CMP
PUSH
POP
JC

CRT_MODE,6
ES
OS
S13P

PO I NT TO REGEN SEGMENT
MED I UM RESOLUT I ON

;----- HIGH RESOLUTION READ
;----- GET VALUES fROM REGEN BUffER AND CONVERT TO CODE POINT
MOV

OH,4

MOV
MOV
INC
MOV
MOV
INC
ADO
DEC
JNZ
JMP

AL, [SI J
I BPJ, ... L
BP
AL,I S I +2000H J
I BPJ,AL
BP
SI,80
DH
S12P
S15P

NUMBER OF PASSES

SI2P:
;

GET fiRST BYTE
SAVE I N STORAGE AREA
; NEXT LOCAT I ON
; GET LOWER REG I ON BYTE
; ADJUST AND STORE
PO I NTER I NTO REGEN
; LOOP CONTROL
; DO I T SOME MORE
; GO MATCH THE SAVED CODE
POI NTS
;

;----- MEDIUM RESOLUTION READ
S13P:
SAL
MOV

S 1,1
DH,4

MED RES READ
, OFFSET*2, 2 BYTES/CHAR
; NUMBER OF PASSES

S14P:
CALL

S23

ADD
CALL
SUB
DEC
JNZ

SI,2000H
S23
S I , 2000H -80
DH
S14P

; GET PA I R BYTES
INTO SINGLE SAVE
GO TO LOWER REG I ON
GET TH I S PA I R I NTO SAVE
ADJUST PO I NTER BACK INTO
UPPER
KEEP GOING UNTIL 8 DONE

;
;
;

; ----- SAVE AREA HAS CHARACTER IN IT, MATCH IT
F I NO_CHAR

SI5P:
PUSH
CALL
WLXS
LES
POP
SUB

OS
DDS
ES,OI,GRX_SET
01, GRX_SET
OS
BP,8

MOV
CLD
MOV

SI, BP
Al,O

PUSH
POP
MOV

SS
OS
DX,128

PUSH
PUSH
MOV
REPE
POP
POP
JZ

SI
01

INC
ADD
DEC
JNZ

AL
01,8
OX
S17P

SI6P:

EST ABL I SH ADDRESS I NG
ADJUST PO I NTER TO
BEG I NN I NG Of SAVE AREA
ENSURE DIRECTION
CURRENT CODE PO I NT BE I NG
MATCHED
, ADDRESSING TO STACK
FOR THE STR I NG COMPARE
; NUMBtR TO TEST AGA I NST

S17P:

ex,s

CMPSB
01
SI
S16P

SAVE SAVE AREA PO INTER
; SAVE CODE PO INTER
; NUMBER OF BYTES TO MATCH
; COMPARE THE 6 BYTES
; RECOVER THE PO INTERS
I F ZERO FLAG SET,
THEN MATCH OCCURRED
NO MATCH, MOVE TO NEXT
NEXT CODE PO I NT
LOOP CONTROL
DO ALL OF THEM

;----- CHAR NOT MATCHED, MIGHT BE I N USER SUPPLI ED SECOND HALF
CMP

AL,O

JE

S16P

ASSUME
CALL
WLXS
LES
MOV
OR
JZ
MOV
JMP

DS:ABSO
DDS
ES, 0 I, EXT_PTR
01, EXT_PTR
AX,ES
AX,DI
S18P
AL,128
S16P

; ----- CHARACTER

; AL <> 0 IF ONLY 1ST
HALF SCANNED
IF = 0, THEN ALL HAS
BEEN SCANNED
;

GET PO INTER
SEE I F THE PNTR EX I STS

;

I FALL 0, OOESN I T EX I sr

; NO SENSE LOOK I NG
; OR I GIN FOR SECOND HALF
; GO BACK AND TRY FOR IT

I S FOUND ( AL=O I F NOT FOUND )

S16P:
ADO
JMP
GRAPH I CS_READ

SP,6
V RET
ENDP

READJUST THE STACK,
THROW AWAY SAVE
ALL DONE

;----- READ CHARACTER/ATTRIBUTE AT CURRENT CURSOR POSITION
AH8S:
JMP

READ_AC_CURRENT

ASSUME
MOV
CMP
JE
CMP
JBE
CMP
JA
JMP

OS: ABSO

AH8:
AH,CRT_MODE

; GET THE CURRENT MODE

AH,07H
AH8S
AH,03H
AH8S
AH,06H
Z 1
GRAPH I CS_REAO

Z_l :

cmp
jb
ca II

jc
jmp
CMP
JAE
MOV
JMP

ah,Ofh
grx_rd2
mem det

grx=rd2
short grx_rd1
AH, DOH
GRX R02
AL,a
V_RET

136 IBM Enhanced Graphics Adapter

RANGE TEST
FOUR MAP READ

17FB
17FB
17FE
1800
1803
1805
1809

BA
BE
E8
8B
8B
2B

180B

6B EC

1800
180E
1810
1812
1814
1816
1818
181A
181C
181F
1822
1825
1825
1828
182A
1820
182E
1832
1833
1835
1836
1839
183C

53
24
8A
BO
02
B4
B6
B2
E8
B8
E8

AOOO
C2
16B7 R
FO
1E 0465 R
E3

01
C8
05
EO
07
03
CE
0018 R
0518
0018 R

26: 8A 04
F6 DO
88 46 00
45
03 36 044A R
4B
75 FO
5B
B6 0510
EB 32 90

183C
183C
183F
1841
18114
1846
184A

BA
8E
E8
8B
8B
2B

184C

8B EC

184E
1850
1852
1855
18J8
1859
1859
185C
185E
1861
1862
1866
1867
1869
186A
1860

AOOO
C2
16B7 R
FO
1E 0485 R
[3

B6
B2
B8
E8
53

03
CE
0508
0018 R

26:
F6
88
45
03
4B
75
5B
B8

8A 04
DO
46 00
36 044A R
FO
0500

1860

1860

E8 0018 R

1870
1874

C4 3E OlOC R
2B EB

1876
1878
1879
187B
187C
1870
1880
1880
1881
1882
1884
1886
1887
1888

8B F5
FC
Bo 00
16
IF
BA 0100

188A
188C
188E
188F
1891
1891
1893

FE CO
03 FB
4A
75 EF

56
57
8B CB
F3/ A6
5F
5E
74 07

03 E3
E9 219B R

1896
1896
1899

E8 0001 R
8A 26 0449 R

1890
18AO

80 FC 04
72 08

4411
4412
4413
4414
4415
4416
4417
4418
4419
4420
4421
4422
4423
4424
4425
4426
4427
4428
4429
4430
4431
4432
4433
4434
4435
4436
4437
4438
4439
4440
4441
4442
4443
4444
4445
4446
4447
4448
4449
4450
4451
4452
4453
4454
4455
4456
4457
4458
4459
4460
4461
4462
4463
4464
4465
4466
4467
4468
4469
4470
4471
4472
4473
4474
4475
4476
4477
4478
4479
4480
4481
4482
4483
4484
4485
4486
4487
4488
4489
4490
4491
4492
4493
4494
4495
4496
4497
4498
4499
4500
4501
4502
4503
4504
4505
4506
4507
4508
4509
4510
4511
4512
4513
4514
4515
4516
4517
4518
4519
4520
4521
4522
4523
4524
4525
4526
4527
4528
4529
4530
4531
4532
4533
4534
4535
4536

C
C
C
C+
C+
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C+
C+
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C+
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

GRX RO 1 PROC
ASSUME
SRLOAo
MOV
MOV
CALL
MOV
MOV
SUB

NEAR
OS:ABSO
ES,OAOOOH
oX,OAOOOH
ES,oX
GR CUR
SI-;-AX
BX, PO I NTS
SP,BX

;

BP, SP

MOV

REGEN SEGEMNT
BYTE OFFSET I NTO REGEN
SAVE IN SI
BYTES PER CHARACTER
ALLOCA TE SPACE TO SAVE
THE READ CODE PO I NT
POINTER TO SAVE AREA

; ----- GET VALUES FROM REGEN BUFFER AND CONVERT TO CODE POI NT
BX

PUSH
AND
MOV
MOV
SHL
MOV
mav
MOV
CALL
MOV
CALL

AL,l
CL,AL
AL,5
AL,CL
AH, G_COLOR

SAVE BYTES PER CHARACTER
000 OR EVEN BYTE
USE FOR SH 1FT
COLOR COMP VALUE (CO-C2)
(C1-C3) IF ODD BYTE
COLOR COMPARE REG I STER

dh,3
oL, GRAPH AD DR
OUT OX AX,518H
OUT_OX

S12_ 1:

AL, ES: (SI J

MOV
NOT
MOV
INC
ADD
DEC
JNl
POP
MOV
JMP
GRX_R01 ENOP

AL
SS: I BPJ.AL
BP
SI,CRT COLS
BX
S12 1
BX AX,510H
GRX_RECG

GRX RD2 PROC
ASSUME
SRLOAo
MOV
MOV
CALL
MOV
MOV
SUB

NEAR
OS: ABSO
ES,OAOOOH
DX,OAOOOH
ES,OX
GR CUR
SI-;-AX
BX,POINTS
SP, BX
BP, SP

MOV

SET GRAPH I CS CH I P
READ MODE
SET GRAPH I CS CH I P
GET FIRST BYTE
SAVE I N STORAGE AREA
NEXT LOCATION
POI NTER I NTO REGEN
LOOP CONTROL
00 I T SOME MORE
RECOVER BYTES PER CHAR
UNDO READ MODE
CHAR REGONT I ON ROUT I NE

REGEN SEGMENT
BYTE OFFSET I NTO REGEN
SAVE INS I
ByTES PER CHARACTER
ALLOCATE SPACE TO SAVE
THE READ CODE PO I NT
POI NTER TO SAVE AREA

; ----- GET VALUES FROM REGEN BUFFER AND CONVERT TO CODE POI NT

dh,3

mav
MOV
MOV
CALL
PUSH
S12:
MOV
NOT
MOV
INC
ADD
DEC
JNl
POP
MOV
GRX_RD2 ENOP

DL, GRAPH AOOR
AX,508H OUT OX
BX -

GRAPHICS CHIP
COLOR COMPARE
SET THE REG I STER
SAVE BYTES PER CHARACTER

AL, ES: I SI J
AL

GET COLOR COMPARED BYTE
ADJUST
SAVE I N STORAGE AREA
NEXT LOCAT ION
PO I NTER I NTO REGEN
LOOP CONTROL
DO I T SOME MORE
RECOVER BYTES PER CHAR
UNDO READ MODE

SS:IBPJ.AL
BP
SI,CRT_COlS
BX
S12
BX
AX,500H

GRX_RECG:
;----- SAVE AREA HAS CHARACTER IN IT, MATCH IT
CALL
WLXS
LES
SUB

OUT OX
ES,DI,GRX SET
OI,GRX_SET
BP,BX

MOV
CLO
MOV
PUSH
POP
MOV

SI, BP
AL,O
SS
OS
oX,2560

PUSH
PUSH
MOV
REPE
POP
POP
Jl

SI
01
CX,BX
CMPSB
01
SI
S18_5

INC
ADO
DEC
JNl

AL

S17_5:

ol.ax
Ox

S17_5

S18_5:
ADD
JMP

SET READ MODE BACK
GET FONT DEFINITIONS
ADJUST PO I NTER TO
BEG I NN I NG OF SAVE AREA
ENSURE 0 I RECT I ON
CODE PO I NT BE I NG MATCHED
ADDRESS I NG TO STACK
FOR THE STRING COMPARE
NUMBER TO TEST AGA I NST
SAVE SAVE AREA PO I NUR
SAVE CODE PO INTER
NUMBER OF BYTES TO MATCH
COMPARE THE 8 BYTES
RECOVER THE PO INTERS
IF lFL SET, THEN MATCH
OCCURRED
NO MATCH, ON TO NEXT
NEXT CODE PO I NT
LOOP CONTROL
DO ALL OF THEM
AL=CHAR, 0 I F NOT FOUND
READJUST THE STACK

;----- WRITE CHARACTER/ATTRIBUTE AT CURRENT CURSOR POSITION

g ;-~;;~TE=;~=~~;;;;[NT-------------- ----------------C;
C
C
C
C
C
C
C
C

THIS ROUTINE WRITES THE ATTRIBUTE
AND CHARACTER AT THE CURRENT CURSOR
POSITION
INPUT

g;

(AH)
(BH)
(CX)
(AL)
(BL)

=
=
=
=
=

CURRENT CRT MODE
DISPLAY PAGE
COUNT OF CHARACTERS TO WRITE
CHAR TO WR I TE
ATTRIBUTE OF CHAR TO WRITE

1~~ l ~ ~~6~N S~~~~~~T

C ; OUTPUT
C;
NONE

g

.i..~9 ~-

------- ------ -------------- --- ----- ---- --- --

C

CALL

C
C
C
C

MOV

OS: ABSO
ODS
AH , CRT_MODE

CMP
JC

AH,4
P6

C

ASSUME

IS TH I S GRAPH I CS

IBM Enhanced Graphics Adapter 137

18A2
18A5
18A7
18AA
18AA
18AD
18AF
18BO
18Bl
18B4
18B6
18B7
18B8
18BC

18BF
18BF
18C4
18C6
18C6
18C7
18C9
18CB
18CC
18CC
18CD
18CF
1801
1801
1803
1804
1805
1807

80 FC 07
74 03
EB 74 90
E8
8A
50
51
E8
8B
59
5B
8B
83

16E8 R
E3
164E R
FB
16 0463 R
C2 06

F6 06 0487 R 04
74 OB
EC
A8 01
75 FB
FA
EC
A8 01
74 FB
8B C3
AB
FB
E2 E8
E9 219B R

18DA
18DA
1800

E8 0001 R
8A 26 0449 R

18El
18E4
18E6
18E9

80
72
80
74

18EB
18EE
18EE
18Fl
18F2
18F3
18F6
18F8
18F9

E8 16E8 R
50
51
E8 164E R
8B FB
59
5B

FC 04
08
FC 07
03

EB 30 90

18FA
18FE
1901
1901
1906
1908

8B 16 0463 R
83 C2 06

1908
1909
190B
1900
190E

EC
A8 01
75 FB
FA

190E
190F
1911
1913
1913
1915
1916
1917
1918
191A

EC
AS 01
74 FB

F6 06 0487 R 04
74 OB

8A C3
AA
FB
47
E2 E7
E9 219B R

4537
4538
4539
4540
4541
4542
4543
4544
4545
4546
4547
4548
4549
4550
4551
4552
4553
4554
4555
4556
4557
4558
4559
4560
4561
4562
4563
4564
4565
4566
4567
4568
4569
4570
4571
4572
4573
4574
4575
4576
4577
4578
4579
4580
4581
4582
4583
45B4
4585
4586
4587
4588
4589
4590
4591
4592
4593
4594
4595
4596
4597
4598
4599
4600
4601
4602
4603
4604
4605
4606
4607
4608
4609
4610
4611
4612
4613
4614
4615
4616
4617
4618
4619
4620
4621
4622
4623
4624
4625
4626
4627
4628
4629
4630
4631
4632
4633
4634
4635
4636
4637
4638
4639
4640
4641
4642
4643
4644
4645
4646
4647
4648
4649
4650
4651
4652
4653
4654
4655
4656
4657
4658
4659
4660
4661
4662

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

C

C
C
C
C
C+
C
C
C
C
C
C+
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

CMP
JE
JMP

AH,7
P6
GRAPH I CS_WR I TE

CALL
MOV
PUSH
PUSH
CALL
MOV
POP
POP
MOV
ADD

MK ES
AH-;-BL
AX
CX
F I ND_POS I TiON
DI,BX
CX
BX
OX, ADDR_6845

;

IS THIS Bioi CARD

P6:
GET ATTRIBUTE TO AH
SAVE ON STACK
SAVE WR I TE COUNT
ADDRESS TO D I REG I STER
WR I TE COUNT
CHARACTER IN BX REG
GET BASE ADDRESS
POINT AT STATUS PORT

DX,6

;----- WAIT FOR HORIZONTAL RETRACE
p7:

info,4

test
jz

p9.

P8:
IN
TEST
JNZ
eLI

AL,DX
AL,l
P8

GET STATUS
IS IT LOW
WAIT UNTIL IT IS
NO MORE INTERRUPTS

IN
TEST
JZ

AL,DX
AL,l
P9

GET STATUS
IS IT HIGH
WAIT UNTIL IT IS

MOV
STOSW
STI
LOOP
JMP

AX,BX

RECOVER TH E CHARI A TTR
PUT THE CHAR/ATTR
I NTERRU PTS BACK ON
AS MANY TIMES

P9:

p9.:

; ----- WR I TE CHARACTER ONLY AT CURRENT CURSOR POS I T ION

; -WR 'j TE=~= ~~RRE~T -------------------------------;

THIS ROUTINE WRITES THE CHARACTER AT

;
;

THE CURRENT CURSOR POSITION, ATTRIBUTE
UNCHANGED
INPUT
(AH) = CURRENT CRT MODE
(BH)
DISPLAY PAGE
(CX)
COUNT OF CHARACTERS TO WR ITE
(AL) = CHAR TO WRITE

=
=

;

i~~ l ~

; OUTPUT
;
NONE

';'H~ ~

~~6~N S;~~~~~T

--- --- ---- --- ---- -- ---- ---- --- --- -- --- ---- --ASSUME
CALL
MOV

DS:ABSO
DDS
AH,CRT_MODE

CMP
JC
CMP
JE

AH,4
Pl0
AH,7
Pl0

IS TH I S GRAPH I CS
I S TH I S BW CARD

JMP
Pl0:
CALL
PUSH
PUSH
CALL
MOV
POP
POP

MK ES
AXCX
FIND POSITION
DI,BX
CX
BX

SAVE ON STACK
SAVE WR I TE COUNT
ADDRESS TO D I
WRITE COUNT
BL HAS CHAR TO WR I TE

;----- WAIT FOR HORIZONTAL RETRACE

ADD

MOV

OX, ADDR_6845
DX,6

test

info,4

GET BASE ADDRESS
POI NT AT STATUS PORT

pll:

jz

p13.

WI N
IN
TEST
JNZ
CLI

AL,DX
AL,l
P12

WI N
IN
TEST
JZ

AL,1

P12:
;

GET STATUS

IS IT LOW
WAIT UNTIL IT IS
NO MORE INTERRUPTS

P13:
;

GET STATUS

AL,DX
I SIT HIGH
WAIT UNTIL IT IS

P13

p13.:
MOV
STOSB
ST I
INC
LOOP
JMP

RECOVER CHAR
PUT THE CHARI A TTR
I NTERRU PTS BACK ON
BUMP PO I NTER PAST ATTR
AS REQUESTED

AL,BL

. ---- -- --- - - -- - ---- -- - -- - - - - -

;

-:..

- - - - - - -- -- - -- - - - --- - -- - _.- --- -- ---

GRAPHICS WRITE
TH I S ROUT I NE WR I TES THE ASC II CHARACTER TO THE
CURRENT POS I T I ON ON THE SCREEN.
ENTRY
AL = CHARACTER TO WR I TE
BL = COLOR ATTR I BUTE TO BE USED FOR FOREGROUND COLOR
IF BIT 7 IS SET, THE CHAR IS XOR'D INTO THE REGEN
BUFFER (0 I S USED FOR THE BACKGROUND COLOR)

ex =

;

NUMBER

or

CHARS TO WR I TE

OS = DATA SEGMENT
ES = REGEN SEGMENT
EXI T
NOTH I NG I S RETURNED
GRAPH I CS READ
TH I S ROUT I NE READS THE ASC II CHARACTER AT THE CURRENT
CURSOR POSITION ON THE SCREEN BY MATCHING THE DOTS ON
THE SCREEN TO THE CHARACTER GENERATOR CODE POINTS
ENTRY
NONE
(0 I S ASSUMED AS THE BACKGROUND COLOR)
EXIT
AL = CHARACTER READ AT THAT POS I T I ON (0 RETURNED IF
NONE FOUND)
FOR COM PAT I Bill TY ROUT I NES, THE I MAGES USED TO FORM CHARS ARE
CONTAINED IN ROM FOR THE 1ST 128 CHARS.
TO ACCESS CHARS

138 IBM Enhanced Graphics Adapter

191D
191D
1920
1922
1925
1925
1928
192A

192B
192E

1930
1931
1933

1935
1939

80 FC 07
72 03
E9 19D4 R
E8 16E8 R
B4 00
50

E8 16Al R
8B F8

58
3C 80
73 06

C5 36 OlOC R
EB 06

193B
193B

2C 80

193D

C5 36 007C R

1941
1941
1943
1945
1947
1949
194A
1940
1952
1953

D1
01
01
03
1E
E8
80
1F
72

1955
1955
1956
1957
1959
1959
195A
1950
195F
1960
1961
1961
1966
1969
196B
1960
196E
196F
1970
1972
1975
1975
1978
1979
197A
197F

1981
1981
1983
1985
1988
1988
1989
198A
198C
198C
1980
1990
1992
1995
1997
199A
199E
199E
19A1
19A5
19A6
19A9
19AB
19AE
1980
1985
19BA
19BA
198F
19C4
19C7
19C9
19CB
19CC
19CD
19CE
19CF
1901
1904

EO
EO
EO
FO
0001 R
3E 0449 R 06
2C

57
56
B6 04
AC
F6 C3 80
75 16
AA
AC
26:
83
FE
75
5E
5F
47
E2
E9

8885 1FFF
C7 4F
CE
EC

E3
219B R

26: 32 05
AA
AC
26: 3285 1FFF
EB EO

8A 03
01 E7
E8 166A R
57
56
B6 04
AC
E8 167F R
23 C3
F6 C2 80
74 07
26: 32 25
26: 32 45 01
26: 88 25
26: 88 45 01
AC
E8 167F R
23 C3
F6 C2 80
74 OA
26: 32 A5 2000
26: 32 85 2001
26: 88 A5 2000
26: 88 85 2001
83 C7 50
FE CE
75 C1
5E
5F
47
47
E2 B7
E9 2198 R

4663
4664
4665
4666
4667
4668
4669
4670
4671
4672
4673
4674
4675
4676
4677
4678
4679
4680
4681
4682
4683
4684
4685
4686
4687
4688
4689
4690
4691
4692
4693
4694
4695
4696
4697
4698
4699
4700
4701
4702
4703
4704
4705
4706
4707
4708
4709
4710
4711
4712
4713
4714
4715
4716
4717
4718
4719
4720
4721
4722
4723
4724
4725
4726
4727
4728
4729
4730
4731
4732
4733
4734
4735
4736
4737
4738
4739
4740
4741
4742
4743
4744
4745
4746
4747
4748
4749
4750
4751
4752
4753
4754
4755
4756
4757
4758
4759
4760
4761
4762
4763
4764
4765
4766
4767
4768
4769
4770
4711
4772
4713
4714
4715
4716
4771
4778
4779
4780
4781
4782
4783
4784
4785
4786
4787
4788

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C+
C
C
C
C
C
C
C
C+
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

IN THE SECOND HALF, THE USER MUST INITIALIZE THE VECTOR AT
INTERRUPT 1FH (LOCATION 0007CH) TO POINT TO THE USER
SUPPLIED TABLE OF GRAPHIC IMAGES (8X8 BOXES).
FAILURE TO DO SO WILL CAUSE IN STRANGE RESULTS
ASSUME
GRAPH I CS WR I TE
CMP
JB
JMP

CS: CODE, DS:ABSO, ES: NOTHI NG
PROC
NEAR
AH,7
51 A
GR>CWRT
MK ES

CALL
MOV
PUSH

~:-O

; 0 TO HIGH OF CODE POINT
; SAVE CODE PO I NT VALUE

;----- DETERMINE POSITION IN REGEN BUFFER TO PUT CODE POINTS
;' LOC I N REGEN BUFFER
; REGEN POINTER IN 01

526
DI,AX

CALL
MOV

; ----- DETERM I NE REG I ON TO GET CODE PO I NTS FROM
RECOVER CODE PO I NT
, IS IT IN SECOND HALF
; YES

AX
AL,80H
51

POP
CMP
JAE

IMAGE IS IN FIRST HALF, CONTAINED IN ROM
DS,SI,GRX_SET
SI,GRX_SET
SHORT S2

WLXS
LOS
JMP

I MAGE I SIN SECOND HALF,

I N USER RAM

S1:
SUB
WLXS
LOS

AL,80H
DS,SI,EXT_PTR
51, EXT_PTR

; EXTEND_CHAR
; 0 OR I GIN FOR SECOND HALF

;----- DETERMINE GRAPHICS MODE IN OPERATION
S2:
AX,1
AX,1
AX,1
SI,AX
OS
DDS
CRT_MOOE,6
OS
57

SAL
SAL
SAL
ADD
PUSH
CALL
CMP
POP
JC

; DETERM I NCMODE
; MULTIPLY CODE POINT
;
VALUE BY 8
S I HAS OFFSET OF
DES I RES CODES

TEST FOR MED I UM RES MODE

;----- HIGH RESOLUTION MODE
HIGH CHAR
SAVCREGEN PO INTER
SAVE CODE PO INTER
NUMBER OF TIMES THROUGH
LOOP
GET BYTE FROM CODE PO I NT
SHOULD WE USE THE
FUNCT I ON TO PUT CHAR IN
STORE I N REGEN BUFFER

S3:
PUSH
PUSH
MOV

01
SI
OH,4

S4:
LOOSB
TEST
JNZ
STOSB
LOOSB
S5:

BL,80H
56

MOV
ADD
DEC
JNZ
POP
POP
INC
LOOP
JMP

ES: [0 I +2000H-1 J. AL
01,79
OH
S4
SI
01
01
53
V_RET

, STORE I N SECOND HALF
; MOVE TO NEXT ROW I N REGEN
; DONE WITH LOOP

XOR
STOSB
LOOSB
XOR
JMP

AL, ES: [01]

; XOR WITH CURRENT
, STORE THE CODE PO I NT
; AGA I N FOR ODD FIE LD

S6:

AL, ES: [01 +2000H-1]
55

; RECOVER REGEN PO INTER
, PO I NT TO NEXT CHAR POS
; MORE CHARS TO WR ITE

;

BACK TO MA I NSTREAM

;----- MEDIUM RESOLUTION WRITE
S7:

MED RES WR ITE
SAVE HIGH COLOR BIT
OFFSET*2, 2 BYTES/CHAR
EXPAND BL TO FULL WORD
OF COLOR
SAVE REGEN PO INTER
SAVE THE CODE PO INTER
NUMBER OF LOOPS

MOV
SAL
CALL

OL,BL
01,1
519

PUSH
PUSH
MOV

01
51
DH,4

LOOSa
CALL
AND

AX,BX

TEST
JZ
XOR
XOR

OL,80H
S10
AH,ES:[OI]
AL,ES:[OI+1]

MOV
MOV
LODSa
CALL
AND
TEST
JZ
XOR
XOR

ES: [01 J.AH
ES: [DI+1I,AL

STORE FIRST BYTE
STORE SECOND BYTE
GET CODE PO I NT

521
AX,BX
OL,80H
511
AH, ES: [0 I +2000H I
AL, ES: [DI+2001H I

CONVER r TO COLOR
IS THIS XOR FUNCTION
NO, JUST STORE THE VALUE
FUNCTION WITH FIRST HALF
AND WI TH SECOND HALF

ES: [OI+2000HJ.AH
ES:[OI+2000H+1I,AL
01,80
OH
59
SI
01
01
01
58
V RET
ENOP

KEEP GOING
RECOVER CODE PONTER
RECOVER REGEN PO INTER
PO I NT TO NEXT CHAR

58:

S9:
521

S10:

GET CODE PO I NT
DOUBLE UP ALL THE BITS
CONVERT THEM TO FOREGROUND COLOR (0 BACK)
IS THIS XOR FUNCTION
NO, STORE IT IN AS IT IS
DO FUNCTION WITH HALF
AND WITH OTHER HALF

511:
MOV
MOV
ADO
DEC
JNZ
POP
POP
INC
INC
LOOP
JMP
GRAPHICS_WRITE
;

-

~~~~~

STORE I N SECOND PORT I ON
POINT TO NEXT LOCATION

; MORE TO WR I TE

----- - --------------- - - - -- ---------------- ---------- --- - --

IBM Enhanced Graphics Adapter 139

1904
1904
1907
1909
190C
190E
19E1
19E3
19E5
19£1
19E7
19E9
19EO
19EE
19f1
19f3

80
72
E8
72
80
8A
DO
OA

fC Of
OE
14f4 R
09
E3 85
E3
E4
DC

19f7
19fA

BA AOOO
8E C2

19fC
lAOO
lAOl
lA03
lA05
lA05
lA08
lAOA
lAOC
lAOf
lA12
lA15
lA15
lA16
lA18
lA1B
lA1E
lA20
lA21
lA23
lA24
lA27
lA27
lA28
lA2C
lA20
lA2F
lA30
lA31
lA32
lA32
lA34
lA36
lA38
lA3B
lA3C
lA30
lA3E
lA40
lA41

C5 36 010C R
58
03 fO
B6 03

B2
B4
8A
E8
57
53
51
8B
lE
E8

1 A44
lA48

8B OE 044A R
lf

lA49
lA49
lA4B
lA4[
lA51
lA52
lA54
lA55

SA 04
26: SA 25
26: 88 05
46
03 f9
48
75 f2

lA57
lA58
lA59
lA5B
lA5C
lA50

59
5B
2B.F5
5f
47
E2 A6

lA5F
lA61
lA64
lA67
lA69
lA6C
lA6f
lA72

B2
B8
E8
B2
B8
E8
E9

2A E4
f7 26 0485 R
50
E8 16B7 R
8B f8
8B 2E 0485 R

F6
74
B2
B8
E8
EB
57
B2
B8
E8
2B
51
8B
lE
E8

C3 80
OB
CE
0318
0018 R
lE 90
C4
020f
0018 R
CO
CO
0001 R

AA
03 3E 044A R
4f
E2 f8
lf
59
5f
C4
02
C3
0018 R

DO
0001 R

CE
0300
0018 R
C4
020F
0018 R
219B R

lA72

1M2
lA77
lA79
lA7E
lA80
lA82
lA82
lA85
lA85
lA87
lA89
lA80
lA90
lA93
lA95
lA97
lA99
lA9A
1A9A
lA90
lA9F

80
74
F6
74
CO

3E 0463 R B4
09
06 0487 R 02
05
42

E9 219B R
2B CO
8B E8
C4 3E 04A8 R
83 C7 04
26: C4 3D
8C CO
OB C7
74 01
45
E8 lOBO R
OA fF
75 65

4789
4790
4791
4792
4793
4794
4795
4796
4797
4798
4799
4800
4801
4802
4803
4804
.4805
4806
4807
4808
4809
4810
4811
4812
4813
4814
4815
4816
4817
4818
4819
4820
4821
4822
4823
4824
4825
4826
4827
4828
4829
4830
4831
4832
4833
4834
4835
4836
4837
4838
,,839
4840
4841
4842
4843
4844
4845
4846
4847
4848
4849
4850
4851
4852
4853
4854
4855
4856
4857
4858
4859
4860
4861
4862
4863
4864
4865
4866
4867
4868
4869
4870
4871
4872
4873
4874
4875
4876
4877
4878
4879
4880
4881
4882
4883
4884
4885
4886
4887
4888
4889
4890
4891
4892
4893
4894
4895
4896
4897
4898
4899
4900
4901
4902
4903
4904
4905
4906
4907
4908
4909
4910
4911
4912
4913
4914

AL
BH
BL
CX

C
C
C
C

=
=
=
=

CHAR TO WR ITE
01 SPLAY PAGE
ATTRIBUTE/COLOR
COUNT Of CHARS TO WRITE

g 6RX-WRT -PROC----NEAR--------------------------------------------C

-

ASSUME

OS: ABSO,

ES: NOTH I NG

C

cmp

ah,Ofh

C
C
C
C

Jb

C
C
C

mov

no:"adj 1
mem_det
no_adj 1
bl,10000101b
ah,bl

C

ca I I
jc
and

640x350 graph.lcs

; 85h, xor c2 cO mask

ah,l
bl,ah

; expand cO to c1, c2 to c3
; bui Id ?(80hl + (O,3,c,f)

SUB
MUL
PUSH
CALL
MOV
MOV
SRLOAO
MOV
MOV
WLXS
LOS
POP
ADO

AH,AH
POI NTS
AX
GR CUR
OI~AX
BP, POINTS
[S,OAOOOH
DX,OAOOOH
ES,DX
OS, S I ,GRX_SET
SI,GRX_SET
AX
SI,AX
dh,3

; ZERO
, OffSET fONT TABLE BASE
; fONT TABLE 0 I SPLACEMENT
; GET OffSET I NTO REGEN
INTO DESTINATION
BYTES PER CHAR
REGEN SEGEMNT

TEST
JZ
MOV
MOV
CALL
JMP

BL,080H
NO XOR
OL~GRAPH_AOOR
AX,0318H
OUT OX
f_2-

PUSH
MOV
MOV
CALL
SUB
PUSH
MOV
PUSH
CALL

01
OL, SEQ_AODR
AX,020fH
OUT OX
AX,AX
CX
CX,BP
OS
DOS

STOSB
ADO
DEC
LOOP
POP
POP
POP

OI,CRT_COLS
01
S13A
OS
CX
01

MOV
MOV
MOV
CALL
PUSH
PUSH
PUSH
MOV
PUSH
CALL
ASSUME
MOV
POP
ASSUME

OL, SEQ_AOOR
AH,02H
AL, BL
OUT OX
01 BX
CX
BX,BP
OS
DOS
OS:ABSO
CX,CRT_COLS
OS
OS: NOTH I NG

MOV
MOV
MOV
INC
ADD
DEC
JNZ

AL,OS:[SIJ
AH, ES: [01 )
ES: [01 J,AL
SI
OI,CX
BX
SlK

POP
POP
SUB
POP
INC
LOOP

CX
BX
SI, BP
01
01
S20A

shl

or
nO_8djl:

C
C
C
C
C
C
C
C+
C+
C
C+
C
C

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

;

; base card

;

ADDRESS I NG TO fONTS

,
;

RECOVER OffSET
CHARACTER IN TABLE

S20A:
TEST fOR XOR
NO XOR
GRAPH I CS CH I P XOR
SET REG I STER
SKI P BLANK
BLANK BOX fOR CHAR
SAVE REGEN PO INTER

NO_XOR:
;

ENABLE ALL MAPS
STORE ZERO
SAVE CHARACTER COUNT
GET BYTE COUNT

S13A:

Sl K:

MOV
MOV
CALL
MOV
MOV
CALL
JMP
GRX_WRT ENOP

OL, GRAPH_AOOR
AX,0300H
OUT OX
OL, SEQ_AOOR
AX,020FH
OUT OX
V_RET

ZERO REGEN BYTE
NEXT BYTE OF BOX
ADJUST
NEXT BYTE
RECOVER CHARACTER COUNT
RECOVER REGEN PO INTER

;
;
;

SET MAP MASK
FOR COLOR
SET THE CHIP
SAVE OFFSET IN REGEN
SAVE COLOR VALUE
SAVE CHACTER COUNT
LOOP CONTROL, BYTES/CHAR
SAVE fONT SEGMENT
SET LOW RAM SEGMENT
GET COLUMN COUNT
RESTORE FONT SEGMENT
WR I TE OUT THE CHARACTER
CODE PO I NT
LATCH DATA
WR I TE ONE BYTE OF FONT
NEXT FONT PO I NT
ONE ROW BELOW LAST PO I NT
BYTES PER CHAR COUNTER
DO NEXT ROW OF CHARACTER

, CHARACT ER COUNT
; COLOR VALUE
; ADJUST PTR TO fONT TABLE
, REGEN PO INTER
; NEXT CHAR POSN I N REGEN
; WR ITE ANOTHER CHARACTER
NORMAL WR I TE,
SET THE CH I P

NO ROTATE

ENABLE ALL MAPS
SET THE CH I P

SUBTTL
SET COLOR PALETTE
AHB:
ASSUME
CMP
JE
JZ
I NT

OS:ABSO
BYTE PTR AODR_6845, OB4H
M21 B
i nfa ~ 2
M21 A
42H-

JMP

V_RET

sub

ax,ax
bp,ax
d i, save_ptr

test

may
I es
add
les
moy
or

ca II va I id only for color
see if its the old color card
if not, handle it here
old code ca II
; back to caller

di ,4
di,dword ptr es:[di]

ax, es
ax,d i

jz
inc

not4ahb

CALL
OR
JNZ

PAL I N IT
BH, BH
M20

bp

not4ahb:

; ----- HANDLE BH = 0 HERE
ALPHA MODES => BL = OVERSCAN COLOR
GRAPH I CS
=> BL = OVERSCAN AND BACKGROUND COLOR

140 IBM Enhanced Graphics Adapter

lAAl
1AA3
lAA6
lAA8
lAAB
1AAD
lABO
lAB2
lAB5
lAB7
lAB9
lABC
lABE
lACl
lAC3
lAC5
lAC8
lACB

8A FB
AO 0466 R
24 EO
RO E3 H
OA C3
A2 0466 R
8A OF
80 E7 08
DO E7
8A E8
80 E5 EF
OA ED
80 E3 OF
8A FB
DO E3
80 E3 10
80 E7 07
OA OF

1 ACD
lADO
lAD2

AO 0449 R
3C 03
76 OE

lAD4
lAD6
lAD8

B4 00
8A C3
E8 lD9C R

lADB
lADD
lADF

OB ED
74 03
26: 88 10

lAE2
lAE2 80 3E 0449 R 03
lAE7 77 05
lAE9 E8 OE9C R
lAEC 72 07
lAEE
lAEE B4 11
lAFO 8A C3
lAr2 E8 lD9C R
lAr5
lAF5 ,OB ED
lAF7 74 04
lAF9 26: 88 50 10
lAFD
lArD 8A DO
lAFF 80 E3 20
1 B02 Bl 05
lB04 02 EB

lB06
1 B06
lBOB

80 3E 0449 R 03
76 4A

1 BOD
lBl0
lB12
lB15
lB17
lB19
1B19
lB1C
lBl E
lB20
lB22
lB24
1 B26

AO
24
80
74
OC

0466 R
OF
E3 01
02
20

A2
24
OC
OA
B4
8A
E8

0466 R
10
02
08
01
C3
lD9C R

lB29
lB2B
lB2D
lB31

OB ED
74 04
26: 88 50 01

1 B31
lB33
1 B35
lB37
lB39

FE C3
FE C3
B4 02
SA C3
E8 lD9C R

1 B3C
lB3E
lB40
lB44

OB ED
7404
26: 88 5002

lB44
lB46
lB48
lB4A
lB4C

FE
FE
B4
8A
E8

lB4F
lB51
lB53

OB ED
74 04
26: 88 50 03

lB57
1B57
lB5A

E8 lDB4 R
E9 219B R

C3
C3
03
C3
lD9C R

4915
4916
4917
4918
4919
4920
4921
4922
4923
4924
4925
4926
4927
4928
4929
4930
4931
4932
4933
4934
4935
4936
4937
4938
4939
4940
4941
4942
4943
4944
4945
4946
4947
4948
4949
4950
4951
4952
4953
4954
4955
4956
4957
4958
4959
4960
4961
4962
4963
4964
4965
4966
4967
4968
4969
4970
4971
4972
4973
4974
4975
4976
4977
4978
4979
4980
4981
4962
4983
4964
4985
4986
4987
4988
4989
4990
4991
4992
4993
4994
4995
4996
4997
4998
4999
5000
5001
5002
5003
5004
5005
5006
5007
5008
5009
5010
5011
5012
5013
5014
5015
5016
5017
5016
5019
5020
5021
5022
5023
5024
5025
5026
5027
5028
5029
5030
5031
5032
5033
5034
5035
5036
5037
5038
5039
5040

;----- MOVE INTENSITY BIT FROM 03 TO 04 FOR COMPATIBILITY

mov
mav
and
and

bh,bl

81, crt_pa lett8
81,oeOh
bl,Olfh
al,bl
crt pa 18tt8;81
bl,lih
bh,08h
bh,l

mav
mov
and
shl
mov
and

ch,al
ch,Oefh

or

ch,ch

AND
MOV
SHL
MD
AND
OR

BL,OFH
BH, BL
BL,l
BL,010H
BH,07H
BL,BH

MOV
CHP
JBE

AL, CRT_MODE
AL,3
H21

;----- GRAPHICS MODE DONE HERE (SET PALETTE 0 AND OVERSCAN)
HOV
MOV
CALL

AH,O
AL,BL
PAL_SET

or

bp,bp
m21
es: [d I I. bl

~~v

;----- ALPHA MODE DONE HERE (SET OVERSCAN REGISTER)
H21 :
ja
ca II
jc

skip::::ovrsc

set. ovrsc:
-

MOV
MOV
CALL

overscan register

AH,011H
AL,BL
PAL_SET

sk i p_ovr~~:

m21y:

check for an enhanced l1Iode
no chance
see if we 8 re enhanced
there I s no border

crt_mode, 3
set ovrsc
brst det

cmp

; set the border

bp, bp

~~v

m21y

mav
AND
MOV
SHR

bl,ch
8L.020H
CL,5
BL. CL

es:(di)[ 16dl.bl

HANDLE BH • 1 HERE
ALPHA MODES .> NO EFFECT
GRAPHICS
.> LOW BIT OF BL • 0
PALETTE 0 • BACKGROUND
PALETTE 1 • GREEN
PALETTE 2 • RED
PALETTE 3 • BROWN
.> LOW BIT 0 F BL • 1
PALETTE 0 • BACKGROUND
PALETTE 1 • CYAN
PALETTE 2 • MAGENTA
PALETTE 3 • WH I TE
H20:

H22:

m22y:

m27y:

M80:

CHP
JBE

CRT HODE,3
M80-

MOV
AND
AND
JZ
OR

AL,CRT_PALETTE
AL,ODFH
BL,l
M22
AL,020H

MOV
AND
OR
OR
MOV
MOV
CALL

CRT_PALETTE, AL
AL,010H
AL,2
BL,AL
AH,l
AL, BL
PAL_SET

or

~~v

bp, bp
m22y
es: [di)[

INC
INC
MOV
MOV
CALL

BL
BL
AH,2
AL.BL
PAL_SET

or

~~v

bp. bp
m27y
es: [d i )[21. bl

INC
INC
MOV
MOV
CALL

BL
BL
AH,3
AL.BL
PAL_SET

or

~~v

bp,bp
m80
es: [d i)[ 31, bl

CALL
JMP

PAL ON
V_RET

11, bl

INCLUDE
VOOT, INC
SUBTTL VDOT, INC
PAGE
; - -- --_ .. ..
.... -.... .......
ENTRY
OX • ROW
CX • COLUMN

-_ --_

--- -- -_

-_

-_ .. -- ............ -_ ...... _-

IBM Enhanced Graphics Adapter 141

lB50

1 B50
lB61
lB62
lB64
lB66

F7
51
01
01
01

26 044A R

lB68
IBM
lB6C
lB6E
lB70
lB74
lB76
lB76
lB78
lB7A
1 B7A
lB7B
lB70
lB80
1 B82
lB84
lB85

03
8A
2A
88
8B
E3

Cl
OF
FF
CB
IE 044C R
04

lB85
lB85
lB86

E9
E9
E9

03 C3
E2 FC
59
88
80
BO
02
C3

08
El 07
80
E8

53
50

lB87
lB89
lBBA
lB80

BO 28
52
80 E2 FE
F6 E2

lB8F
lB90
lB93
lB9~
lB98
lB98
lB9A
lB9B

5A
F6 C2 01
74 03
05 2000

1 B90
lBAO
1 BA3
lBAS
IBM
lBAO

lBBO
lBBO

88 FO
58
8B 01

B8
B9
80
72
BB
B9

02CO
0302
3E 0449 R 06
06
0180
0703

22 EA

lBB2
lBB4
lBB6

03 EA
03 F2
8A F7

lBB8
lBBA
lBBA

2A C9

lBBC
lBBE
lBCO

02 CD
FE CF
75 F8

1 BC2
lBC4
1BC6
lBC7
lBC8

8A E3
02 EC
5B
C3

DO C8

5041
5042
5043
5044
5045
5046
5047
5048
5049
5050
5051
5052
5053
5054
5055
5056
5057
5058
5059
5060
5061
5062
5063
5064
5065
5066
5067
5068
5069
5070
5071
5072
5073
5074
5075
5076
5071
5078
5079
5080
5081
5082
5083
5084
5085
5086
5087
5088
5089
5090
5091
5092
5093
5094
5095
5096
5097
5098
5099
5100
5101
5102
5103
5104
5105
5106
5107
5108
5109
5110
5111
5112
5113
5114
5115
5116
5117
5118
5119
5120
5121
5122
5123
5124
5125
5126
5127
5128
5129
5130
5131
5132
5133
5134
5135
5136
5137
5138
5139
5140
5141
5142
5143
5144
5145
5146
5147
5148
5149
5150
5151
5152
5153
5154
5155
5156
5157
5158
5159
5160
5161
5162
5163
5164
5165
5166

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

BH ;

PAGE

EXIT
BX = OFFSET I NTO REGEN
AL ; BIT MASK FOR COLUMN BYTE

6~T

=SUP=~ -------PR~C ----N~;R---------------------

; ----- OFFSET = PAGE OFFSET

+ ROW

*

BYTES/ROW

+ COLUMN/8

*

MUL
PUSH
SHR
SHR
SHR

WORD PTR CRT COLS
CX
CX,1
CX,1
CX,1

ADD
MOV
SUB
MOV
MOV
JCXZ

AX,ex
BL, BH
BH,BH
CX,BX
BX,CRT_LEN
OS_2

ROW
BYTES/ROW
SAVE COLUMN VALUE
DIVIDE BY EIGHT TO
DETERMI NE THE BYTE THAT
TH I S DOT I SIN
(8 BITS/BYTE)
BYTE OFFSET I NTO PAGE
GET PAGE INTO BL
ZERO
COUNT VALUE
LENGTH OF ONE PAGE
PAGE ZERO

ADD
LOOP

AX,BX
OS_3

BUMP TO NEXT PAGE
DO FOR THE REST

CX
BX,AX
CL,07H
AL,080H
AL,CL

RECOVER COLUMN VALUE
REGEN OFFSET
SH I FT COUNT FOR BIT MASK
MASK BI T
POSITION MASK BIT

POP
MOV
AND
MOV
SHR
RET
DOT_SUP_l

ENOP

: -T~ ~ S-SUiiROUT~ N~- ii~T~RM ~ N~S -T~E -REGEN -ii~T E-LOC;T ~ON ----;
;
;
;

OF THE INDICATED ROW COLUMN VALUE IN GRAPHICS MODE.
ENTRY -OX; ROW VALUE (0-199)
CX = COLUMN VALUE (0-639)

; EXIT -;
;
;
;

SI
AH
CL
OH

~i

= OFFSET I NTO REGEN BUFFER FOR BYTE OF INTEREST
= MASK TO STR I P OFF THE BITS OF INTEREST
= BITS TO SHIFT TO RIGHT JUSTIFY THE MASK IN AH
= # BITS I N RESULT

------PROC --- -N E;R------------------------------------PUSH
PUSH

BX
AX

SAVE BX DURING OPERATION
WILL SAVE AL DURING OPERATION

;----- DETERMINE 1ST BYTE IN IDICATED ROW BY MULTIPLYING ROW VALUE BY 40
( LOW BIT OF ROW DETERM I NES EVEN/ODD, 80 BY!ES/ROW
MOV
PUSH
MUL

AL,40
OX
DL,OFEH
DL

POP
TEST
JZ
ADD

OX
DL,l
R4
AX,2000H

MOV
POP
MOV

SI,AX
AX
OX,CX

AN~

SAVE ROW VALUE
STR I P OFF ODD/EVEN BIT
AX HAS ADDRESS OF 1 ST BYTE
OF INDICATED ROW
RECOVER IT
TEST FOR EVEN/ODD
JUMP I F EVEN ROW
OFFSET TO LOCAT I ON OF ODD ROWS
EVEN ROW
MOVCPO I NTER TO S I
RECOVER AL VALUE
COLUMN VALUE TO OX

R4:

; ----- OETERMI HE GRAPH I CS MODE CURRENTLY

I N EFFECT

;-S~ T-UP-T~E -REG ~ ST ERs- ;cCORii~ NG -TO -T~E -MoiiE ------------------ --~
;
;
;
;

; ....

CH; MASK FOR LOW OF COLUMN ADDRESS ( 7/3 FOR HI GH/MED RES)
CL = /I OF ADDRESS BITS I N COLUMN VALUE ( 3/2 FOR H/M)
BL = MASK TO SELECT BITS FROM PO I NTED BYTE (80H/COH FOR H/M)
BH = NUMBER OF VALID BITS IN POINTED BYTE ( 1/2 FOR H/M)

:
:
:
:

--_ ............ --_ .. - .... -_ .. --_ .. -- -- --_ .... -- -- -_ .. ---_ .. - .. -_ .. --_ .............. -_ ..
MOV
MOV
CMP
JC
MOV
MOV

BX,2COH
CX,302H
CRT_MODE,6
R5
BX,180H
CX,703H

SET PARMS FOR MED RES
HANDLE IF MED ARES
SET PARMS FOR HIGH RES

;----- DETERMINE BIT OFFSET IN BYTE FROM COLUMN MASK
R5:
AND

CH,DL

; ADDRESS OF PEL WITHIN BYTE TO CH

;----- DETERMINE BYTE OFFSET FOR THIS LOCATION IN COLUMN
SHR
ADD
MOV

DX,CL
SI/OX

DH, BH

SH I FT BY CORRECT AMOUNT
I NCREMENT THE PO INTER
GET THE /I OF BITS IN RESULT TO DH

;----- MULTIPLY BH (VALID BITS IN BYTE) BY CH (BIT OFFSET)
SUB

CL,CL

ZERO

ROR

AL,1

ADD
DEC
JNZ

CL,CH
BH
R6

MOV
SHR
POP
RET
ENOP

AH, BL
AH, CL
BX

LEFT JUST I FY THE VALUE
IN AL (FOR WRITE)
ADD I N THE BIT OFFSET VALUE
LOOP CONTROL
ON EX IT, CL HAS SH I FT COUNT
TO RESTORE BITS
GET MASK TO AH
MOVE THE MASK TO CORRECT LOCAT I ON
RECOVER REG
RETURN WITH EVERYTH I NG SET UP

I NTO STORAGE LOCAT I ON

R6:

R3

; ---------------------------------------------------------------READ DOT
-- WR I TE DOT
THESE ROUT I NES WILL WR I TE A DOT, OR READ THE DOT AT
THE INDICATED LOCATION
ENTRY -OX = ROW (0-199)
(THE ACTUAL VALUE DEPENDS ON THE MODE)
CX = COLUMN ( 0-639) ( THE VALUES ARE NOT RANGE CHECKED )
AL = DOT VALUE TO WRITE (1,2 OR 4 BITS DEPENDING ON MODE,
REQ'D FOR WRITE DOT ONLY, RIGHT JUSTIFIED)
BIT 7 OF AL=l INDICATES XOR THE VALUE INTO THE LOCATION
OS

=

OATA SEGMENT

ES = REGEN SEGMENT
; EXIT
;

AL = DOT VALUE READ,

RIGHT JUSTIFIED,

READ ONLY

----------------------------------------------------------------

142 IBM Enhanced Graphics Adapter

lBC8
lBC8
lBCO

80 3E 0449 R 07
77 2A

lBCf
lBCf

52

lBOO
lB03
lB05
lB06
lB07
lB08
lBOB
lBOO
lBOf
lBE2
lBE3
lBE6
lBE8
lBEA
lBEC
lBEE
lBEE
lBfl
lBf2
lBf5
lBf5
lBf7
lBf9

BA B800
8E C2
5A
50
50
E8 lB85 R
02 E8
22 C4
26: 8A OC
5B
f6 C3 80
75 00
f6 04
22 CC
OA Cl

lBF9
lBf9
lBfE
lCOO
lC03
lC05
lC07
lC09
lCOB
lCOO
lCOD
lCOE
lCl0
lC13
lC15
lC17
lC19
lC1C
lCl D
lC20
lC22
lC23
lC24
lC26
lC29
lC2B
lC2D
lC2f
lC32
lC35
lC35
lC37
lC39
lC3B
lC3E
lC41
lC43
lC46
lC46
lC48
lC4A
lC4C
lC4E
lC51
lC54
lC56

lC59
lC5C
lC5E
lC60
lC62
lC65
lC67
lC69
lC6C
lC6F

26: 88 04
58
E9 219B R
32 Cl
EB f5

80
72
E8
72
24
8A
DO
OA

3E 0449 R Of
00
14f4 R
08
85
EO
E4
C4

50
8B
EB
B6
B2
B4
E8
52

C2
lB5D R
03
CE
08
OD18 R

BA
8E
5A
58
8A
f6
74
B4
BO
E8
EB

AOOO
C2
E8
C5 80
OA
03
18
OD18 R
12 90

B2 C4
84 02
BO ff
E8 0018 R
26: 8A 07
2A CO
26: 88 07
B2 C4
B4 02
SA C5
24 Of
[8 0018 R
26: 8A 07
BO ff
26: 88 07

E8
B2
B4
2A
E8
B4
BO
E8
E9

0018
C[
03
CO
OD18
08
FF
OD18
219B

R

R
R
R

lC6F
lC6F
lC70

50
52

lC71
lC74
lC76
lC77
lC78
lC7A
lC70
lC7F
lC81
lC83
lC85
lC86

BA
8E
5A
58
8B
E8
B5
2A
2B
BO
C3

lC86
lC86
lC88
lC8A
lC8B
lC8D
lC8f
lC92
lC93
lC96
lC98

AOOO
C2
C2
lB5D R
07
E9
02
00

8A CD
B4 04
52
B6 03
B2 CE
E8 OD18 R
5A
26: SA 27
D2 EC
80 E4 01

5167
5168
5169
5170
5171
5172
5173
5174
5175
5176
5177
5178
5179
5180
5181
5182
5183
5184
5185
5186
5187
5188
5189
5190
5191
5192
5193
5194
5195
5196
5197
5198
5199
5200
5201
5202
5203
5204
5205
5206
5207
5208
5209
5210
5211
5212
5213
5214
5215
5216
5217
5218
5219
5220
5221
5222
5223
5224
5225
5226
5227
5228
5229
5230
5231
5232
5233
5234
5235
5236
5237
5238
5239
5240
5241
5242
5243
5244
5245
5246
5247
5248
5249
5250
5251
5252
5253
5254
5255
5256
5257
5258
5259
5260
5261
5262
5263
5264
5265
5266
5267
5268
5269
5270
5271
5272
5273
5274
5275
5276
5277
5278
5279
5280
5281
5282
5283
5284
5285
5286
5287
5288
5289
5290
5291
5292

C
C
C
C
C
C
C
C
C
C
C
C
C+
C+
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C+
C+
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C+
C+
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

; ----- WR I TE ~OT
AHC:
ASSUME
cmp

OS: ABSO

Ja

wrl te_dot_2

crt_mode, 7

MOV
MOV
pop
PUSH
PUSH
CALL
SHR
AND
MOV
POP
TEST
JNZ
NOT
AND
OR

NEAR
PROC
ds: absO, as: nath Ing
dx
eS,Ob800h
OX,Ob800h
es,OX
dx
AX
AX
R3
AL,CL
AL,AH
CL, ES: (SI]
BX
BL,80H
R2
AH
CL,AH
AL, CL

MOV
POP

ES:(SI],AL
AX

WR I TE_OOT

assume
push

srload

Rl :

jmp

v_ret

XOR
JMP
WRI TE_OOT

AL, CL
Rl
ENOP

XOR ~OT
EXCLUS I VE OR THE DOTS
fiNISH UP THE WRITING

R2:

PROC

WR I TE_00T_2
cmp
jb
ca II
jc
and
may
sh I
or

SAVE DOT VALUE
TWICE
OETERM I NE BYTE POS I T I ON Of THE ~OT
SH I fT TO SET UP THE BITS fOR OUTPUT
STR I P Off THE OTHER B I T5
GET THE CURRENT BYTE
RECOVER XOR fLAG
IS IT ON
YES, XOR THE DOT
SET THE MASK TO REMOVE THE
I NO I CATED BITS
OR I N THE NEW VALUE Of THOSE BITS
fiN ISH_DOT
RESTORE THE BYTE IN MEMORY

NEAR

crt_mode,Ofh
no_adj2

base card

mem det
nO_Bdj2
a 1,10000101b

85h,

ah, a I
ah,l
a I, ah

expand cO to c1, 02 to 03
bui Id ?(80h) + (0, 3,c, f)

xor c2 cO mask

no_adj2:
push
MOV
CALL
may
MOV
MOV
CALL
PUSH
SRLOAD
MOV
MOV
POP
POP
MOV
TEST
JZ
MOV
MOV
CALL
JMP

ax
AX,DX
DOT SUP 1
dh,"3
OL, GRAPH_ADDR
AH, G_B IT_MASK
OUT_DX
DX
ES,OAOOOH
DX,OAOOOH
ES, DX
DX
AX
CH,AL
CH,080H
WD A

MOV
MOV
MOV
CALL
MOV
SUB
MOV

DL, SEQ_AooR
AH, S_MAP
AL,OffH
OUT OX
AL, ES: (BX]
AL,AL
ES: (BXj,AL

MOV
MOV
MOV
AND
CALL
MOV
MOV
MOV

DL, SEQ_AOoR
AH, S_MAP
AL,CH
AL,OfH
OUT DX
AL, ES: (BX]
AL,OffH
ES: (BXj,AL

WD_A:

AH~G_DATA_ROT

AL,018H
OUT DX
WD_B

WO_B:

ROW VALUE
BX=OffSET, AL=B I T MASK
GRAPH I CS CH I P
BIT MASK REG I STER
SET BIT MASK
REGEN SEGMENT

RECOVER COLOR
SAVE COLOR
SEE If XOR
NO XOR
DO XOR
XOR fUNCT I ON
SET THE REG I STER
SK I P THE 8LANK
8LANK THE DOT
SEQUENCER
MAP MASK
ENABLE ALL MAPS
SET THE REG I STER
LATCH DATA
ZERO
BLANK THE DOT
SET THE COLOR MAP MASK
SEQUENCER
MAP MASK REGI STER
COLOR VALUE
VALUES 0-15
SET IT
LATCH DATA
WRITE VALUE
SET THE DOT

;----- NORMALIZE THE ENVIRONMENT
CALL
MOV
MOV
SUB
CALL
MOV
MOV
CALL
JMP
WR I TE_00T_2
RD_S

RD_S
RD_'S

OUT OX
OL, GRAPH_ADDR
AH, C_DATA_ROT
AL,AL
OUT OX
AH,G_BIT_MASK
Al,OFFH
OUT DX
V RET
ENDP

PROC
ASSUME
PUSH
PUSH
SRLOAD
MOV
MOV
POP
POP
MOV
CALL
MOV
SUB
SUB
MOV
RET
ENDP

NEAR
DS: ABSO
AX
DX
ES,OAOOOH
DX,OAOOOH
ES,DX
DX
AX
AX, DX
DOT SUP 1
CH,7
CH, CL
DX,OX
AL,O

PROC
MOV
MOV
PUSH
may
MOV
CALL
POP
MOV
SHR
AND

NEAR
CL,CH
AH,4
DX
dh,3
DL, GRAPH_ADDR
OUT_DX
DX
AH, ES: (BX)
AH,Cl
AH,l

ALL MAPS ON
GRAPH I CS CH I PS
XOR REG I STER
NORMAL WR ITES
SET IT
BI T MASK
ALL BITS ON
SET IT
WR I TE DOT DONE

IBM Enhanced Graphics Adapter 143

le9B
lC9C

C3

lC9C
lC9C
lCAl

60 3E 0449 R 07
77 16

lCA3
lCA3

52

1CA4
lCA7
lCA9
lCAA
lCAO
lCBO
lCB2
lCB4
lCB6
lCB8
lCBB

B.A B800
8E C2
5A
E8 1 B85 R
26: SA 04
22 C4
02 EO
8A CE
02 CO
E9 219B R

lCBB
lCBB
lCCO
lCC2
lCC5

80
72
E8
72

3E 0449 R OF
25
14F4 R
20

lCC7
lCC7
lCCA
lCCO
lCCF
lCOl
lC03
lC05
lC08
lCOA
lCOC
lCOE
lCEO
lCE2
lCE4
lCE7

E8
E8
OA
DO
OA
BO
E8
DO
DO
OA
DO
OA
8A
E9

lC6F
lC86
04
E4
04
02
lC86
E4
E4
04
E4
04
C2
219B

R
R

R

R

lCE7
lCE7
lCEA
lCEA
lCED
leFF
lCFl
lCF3
lCF5
lCF7
lCF9
lCFB
lCFE

E8 lC6F R
E8
8A
02
OA
FE
3C
76
8A
E9

lC86 R
C8
£4
04
CO
03
Fl
C2
219B R

lCFE
lCFE
lCFF
1003
1004
1006
1008
100A
100E

50
8A
53
8A
32
01
8B
5B

lDOF
lOll
1013
1015
1017
1019
101B
1010

3C 00
745C
3C OA
74 5C
3C 08
74 4C
3C 07
74 5C

3E 0462 R
OF
FF
E3
97 0450 R

10lF
11)21
1024

B4 OA
B9 0001
CD 10

1026
1028
102C
102E
1030
1034

FE
3A
75
2A
3A
75

C2
16 044A R
35
02
36'0484 R
28

5293
5294
5295
5296
5297
5298
5299
5300
5301
5302
5303
5304
5305
5306
5307
5308
5309
5310
5311
5312
5313
5314
5315
5316
5317
5318
5319
5320
5321
5322
5323
5324
5325
5326
5327
5328
5329
5330
5331
5332
5333
5334
5335
5336
5337
5338
5339
5340
5341
5342
5343
5344
5345
5346
5347
5348
5349
5350
5351
5352
5353
5354
5355
5356
5357
5358
5359
5360
5361
5362
5363
5364
5365
5366
5367
5368
5369
5370
5371
5372
5373
5374
5375
5376
5377
5378
5379
5380
5381
5382
5383
5384
5385
5386
5387
5388
5389
5390
5391
5392
5393
5394
5395
5396
5397
5398
5399
5400
5401
5402
5403
5404
5405
5406
5407
5408
5409
5410

5411
5412
5413
5414
5415
5416
5417
5418

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C+
C+
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

RO_ 1 S

RET
ENDP

: ----- READ DOT
AHO:
ASSUME
cmp

J8
READ_DOT 8 ssume
pUSh

s.rload
MOV
MOV
pop
CALL
MOV
AND
SHL
MOV
ROL
jmp

OS:ABSO

crt_mode, 7
r_l
PROC
NEAR
ds: absO, es: noth i n9
dx
es,Ob800h
OX,Ob800h
es,DX
dx
R3
AL,ES:[SI)
AL,AH
AL,CL
CL,DH
AL,CL

OETERM I NE BYTE POS I T I ON OF DOT
GET THE BYTE
MASK OFF THE OTHER BITS IN THE BYTE
LEFT JUST I FY THE VALUE
GET NUMBER OF BITS I N RESULT
RIGHT JUST I FY THE RESULT

v ret
ENDP

READ_DOT
cmp
jb
ca II
jc

crt_mode,Ofh
read_dot_2
mem det

read_dot_2

READ DOT 1
ASSUME
CALL
CALL
OR
SHL
OR
MOV
CALL
SHL
SHL
OR
SHL
OR
MOV
JMP
READ_DOT _1

PROC
NEAR
DS:ABSO, ES: NOTH I NG
RD S
RD-l S
DL~AH
AH,1
DL,AH
AL,2
RO lS
AH~1
AH,1
OL,AH
AH,1
OL,AH
AL,DL
V Rn
ENOP

2 MAPS

READ DOT 2
ASSUME
CALL

PROC
NEAR
OS:ABSO, ES:NOTHING
RO_S

4 MAPS

CALL
MOV
SHl
OR
INC
CMP
JBE
MOV
JMP
READ_00T_2

RO lS
CL~AL
AH,CL
OL,AH
AL
AL,3
RD 2A
AL~OL
V RET
ENDP

;-WR 7T[= TT~ -----WR 7T[-T[~ET~;[ -TO -ACT 7vE-;AG[ ------------------ ---------j

TH I S INTERFACE

:
:
:
:
:
:
:
:
:
:

CARD.
THE INPUT CHARACTER
IS WRITTEN TO THE
CURRENT CURSOR
POSITION, AND THE CURSOR IS MOVED TO THE NEXT POSITION. iF THE
CURSOR LEAVES THE LAST COLUMN OF THE FIELD,
THE COLUMN I S SET
TO ZERO,
AND THE ROW VALUE IS INCREMENTED.
I F THE ROW VALUE
LEAVES THE FIELD,
THE CURSOR I S PLACED ON THE LAST ROW, FIRST
COLUMN,
AND THE ENTIRE SCREEN IS SCROLLED UP ONE LINE.
WHEN
THE SCREEN I S SCROLLED UP, THE ATTR I BUTE FOR F I Lli NG THE NEWLY
BLANKED LINE I S READ FROM THE
CURSOR POS I T I ON ON THE PREV I OUS
LINE BEFORE THE SCROLL,
I N CHARACTER MODE.
I N GRAPH I CS MODE,
THE 0 COLOR I S USED.

PROV I DES A TELETYPE LIKE

I NTERfACE TO THE Y IDEO

ENTRY

;

EXIT

(AH I = CURRENT CRT MODE
(ALI = ·CHARACTER TO BE WRITTEN
NOTE THAT BACK SPACE, CAR RET, BELL AND LINE FEED ARE HANDLED
AS COMMANDS RATHER THAN AS DISPLAYABLE GRAPHICS
(BL I = FOREGROUND COLOR FOR CHAR WR I TE I F CURRENTLY I N A
GRAPHICS MODE

REG I STERS SAVED
.......... -- ...... ALL
-_ ................
-_ ..... -_ ........ --_ ........... -- --- ...... -- -_ ..... --- ---_ ... --_ .. --_ ............ -_ .. ---_ .. ...

AHE:

ASSUME
PUSH
MOV
PUSH
MOV
XOR
SAL
MOV
POP

CS: CODE, OS: ABSO
AX
BH,ACTIVE_PAGE
BX
BL,BH
BH,BH
BX,1
OX, [BX + OFFSET CURSOR_POSN I
BX

SAVE REG I STERS
GET THE ACT I VE PAGE
SAVE
GET PAGE TO BL
CLEAR HIGH BYTE
*2 FOR WORD OFFSET
CURSOR, ACTIVE PAGE
RECOVER

:----- OX NOW HAS THE CURRENT CURSOR POSITION
CMP
JE
CMP
JE
CMP
JE
CMP
JE

AL,OOH
U9
AL,OAH
Ul0
AL,08H
U8
AL,07H

U11

I SIT CARR I AGE RETURN
CAR RET
I S IT ALINE FEED
LINE HED
I S IT A BACKSPACE
BACK SPACE
IS IT A 8ELL
BELL

: ----- WR I TE THE CHAR TO THE SCREEN
MOV
MOV
I NT

AH,10

eX,l
10H

: WRITE CHAR ONLY
ONLY ONE CHAR
WR I TE THE CHAR

:----- POSITION THE CURSOR FOR NEXT CHAR
INC
CMP
JNZ
SUB
CMP
JNZ

DL
DL,BYTE PTR CRT_COLS
U7
OL,DL

DH,ROWS
U6

: ----- SCROLL REQU I RED

144 IBM Enhanced Graphics Adapter

TEST FOR COLUMN OVERFLOW
SET CURSOR
COLUMN FOR CURSOR

lD36
1036

lD39
103C
lD3E
1040
lD42
lD44
1046
lD46
lD48
lD4A
104C
lD4C
lD4f
lD51
lD55
lD59
lD5B
105B
1050
1050
lD5E
lD61
1061
lD63
1063
1 D65

lD67
1067
lD69
lD6B
lD60

E8 115A R

AO
3C
72
2A
3C
75

0449 R
04
06
ff
07
06

B4 08
CD 10
BA fC
B8
2B
BA
BA
fE

0601
C9
36 0484 R
16 044A R
CA

CD 10
58
E9 219B R
fE C6
B4 02
EB f4

OA
74
FE
EB

D2
F8
CA
F4

1D6F
106f
1071

2A D2
EB FO

lD73
1073
1077
1079

3A 36 0484 R
75 E8
EB BB

lD7B
107B
1070
1080

B3 02
E8 OD23 R
EB DB

1082
lD82
lD86
1DBA
lD80
108f
1093
1094
1095
1096
1097
1096
1099
109A
109B

109C
109C
1090
lOAO
lOAl

8A
8A
AO
24
OA
5F
5E
59
59
5A
1F
07
50
CF

26 044A R
3E 0462 R
0487 R
80
06 0449 R

50
E8 OD06 R
fA

lOA7
lDA9

EC
AS
74
58
B2
86

10AB
lOAC

EE
66 C4

1DAE
lDAF

EE
BO 20

lDBl
10B2
10B3
lOB4

EE
FB
C3

10Al
10A2
lOA4
lDA6

lDB4
lDB4
10B7
10B9
lOBB
lOBC
10BD
10BD
10BD
lOCO
lDCl
lDC2

06
FB
CO
C4

E8 lOBD R
B2 CO
BO 20
EE
C3

E8 OD08 R
EC
C3

5419
5420
5421
5422
5423
5424
5425
5426
5427
5426
5429
5430
5431
5432
5433
5434
5435
5436
5437
5438
5439
5440
5441
5442
5443
5444
5445
5446
5447
5448
5449
5450
5451
5452
5453
5454
5455
5456
5457
5458
5459
5460
5461
5462
5463
5464
5465
5466
5467
5468
5469
5470
5471
5472
5473
5474
5475
5476
5477
5478
5479
5480
5481
5482
5483
5484
5485
5486
5487
5488
5489
5490
5491
5492
5493
5494
5495
5496
5497
5498
5499
5500
5501
5502
5503

5504
5505
5506
5507
5508
5509
5510
5511
5512
5513
5514
5515
5516
5517
5518
5519
5520
5521
5522
5523
5524
5525
5526
5527
5528
5529
5530
5531
5532
5533
5534
5535
5536
5537
5538
5539
5540
5541
5542
5543
5544

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

Ul :
SET_CPOS

CALL

; SET THE CURSOR

;----- DETERMINE VALUE TO FILL WITH DURING SCROLL
MOV
CMP
JB
SUB
CMP
JNE

AL, CRT _MODE
AL,4
U2
BH,BH
AL,7
U3

MOV
I NT
MOV

AH,8
10H
BH,AH

MOV
SUB
MOV
MOV
DEC

AX,601H
CX,CX
DH, ROWS
DL, BYTE PTR CRT _COLS
DL

U2:

U3:

U4:
INT

10H

POP
JMP

AX
V_RET

U5:
U6:
INC

DH

MOV
JMP

AH,2
U4

U7:

; GET THE CURRENT MODE
;

READ-CURSOR

; fiLL WI TH BACKGROUND
;
;

SCROLL-UP
READ-CURSOR
READ CHAR/ATTR
STORE IN BH
SCROLL-UP
SCROLL ONE LI NE
UPPER LEfT CORNER
LOWER RIGHT ROW
LOWER RIGHT COLUMN
VIDEO-CALL-RETURN
SCROLL UP THE SCREEN
TTY-RETURN
RESTORE THE CHARACTER
RETURN TO CALLER
SET-CURSOR-I NC
NEXT ROW
SET-CURSOR
ESTABL I SH THE NEW CURSOR

; ----- BACK SPACE fOUND
U8:
OR
JZ
DEC
JMP

DL,DL
U7
DL
U7

ALREADY AT END Of LINE
SET CURSOR
NO -- JUST MOVE I T BACK
SET_CURSOR

; ----- CARR I AGE RETURN FOUND
U9:
DL, DL
U7

SUB
JMP

MOVE TO FIRST COLUMN
SET_CURSOR

; ----- LI NE fEED FOUND
Ul0:
CMP
JNE
JMP

DH, ROWS
u6
Ul

BOTTOM OF SCREEN
YES, SCROLL THE SCREEN
NO, JUST SET THE CURSOR

; ----- BELL FOUND
Ull :
BL,2
BEEP
U5

MOV
CALL
JMP

SET UP COUNT FOR BEEP
SOUND THE POD BELL
TTY_RETURN

;----- CURRENT VIOEO STATE
AHF:
ASSUME
MOV
MOV
MOV
AND
OR
POP
POP
POP
POP
POP
POP
POP
POP
IRET

DS: ABSO
AH, BYTE PTR CRT_COlS
BH,ACTIVE_PAGE
AL, INfO
AL,080H
AL, CRT _MODE
01
SI
CX
CX
DX
DS
ES
BP

GET NUMBER Of COLUMNS

DI SCARD BX

SUBTTL
PAL_SET PROC
PUSH
CALL
CLI
VR:
WIN
IN
TEST
JZ
POP
MOV
XCHG
WOUT
OUT
XCHG
WOUT
OUT
MOV
WOUT
OUT
ST I
RET
PAL_SET ENDP
PAL_ON

PAL_ON

PROC
CALL
MOV
MOV
WOUT
OUT
RET
ENDP

PAL_I NIT
CALL
WIN
IN
RET
PAL I NI T

NEAR
AX
WHAT_BASE

AL,DX
AL,08H
VR
AX
OL,ATTR_WRITE
AL,AH

VERT I CAL RETRACE

DX,AL
AL,AH
DX,AL
AL,020H
DX,AL

NEAR
PAL I NIT
Dl, ATTR_WR I TE
Al,020H
DX,AL

PROG
NEAR
WHAT_BASE
AL,DX
ENDP

; ----- SET PALETTE REG I STERS

IBM Enhanced Graphics Adapter 145

10C2
10C2
10C7

F6 06 0487 R 02
75 07

10C9
10CE
1000
1000
1002
1004

80 3E 0463 R B4
74 33

1006
1008
100C
100F
10E2
10E4
10E6
10E8
10E9

2B ED
C4 3E 04A8 R
83 C7 04
26: C4 3D
8C CO
OB C7
74 01
45

10E9
10EC
lOEE
10FO
10F3
10F6
10F8
10FA
10FC
10FE
lEOO
lE03
lE03

E8 lOBO R
SA E3
8A C7
E8 109C R
E8 10B4 R
OB EO
74 09
8A C7
2A FF
03 FB
26: 88 05

SA EO
OA E4
75 30

E9 219B R

lE06
lE06
lE06

FE CC
75 20

lEOA
lEOC
lEl0
lE13
lE16
lE18
lElA
lE1C
lElO

2B ED
C4 3E 04A8 R
83 C7 04
26: C4 3D
8C CO
OB C7
74 01
45

lE20
lE22
1 E24
lE27

[8
B4
8A
E8
E8

lE2A
lE2C
lE2E
lE31

OB EO
74 05
83 C7 11
26: 88 30

lE34

E9 219B R

lE37
1 E37
lE39

FE CC
75 40

lElO

lE3B
lE3C

lOBO R
11
C7
109C R
10B4 R

lE
06

1 E3D
lE41
lE44
lE47
lE49
lE4B

C4 3E 04A8 R
83 C7 04
26: C4 30
8C CO
OB C7
74 09

lE4D
lE4E
lE4F
lE51
1 E54

1F
lE
8B F2
B9 0011
F3/ A4

1 E56
lE56
lE57

07
lF
8B OA
E8 lOBO R
2A E4

lE58
lE5A
lE50
lE5F
lE5F
lE62
lE65
lE67
lE68
lE6B
lE60
lE6F
lE72
1 E75
1 E78

26: 8A 07
E8 109C R
FE C4
43
80 FC 10
72 F2
FE C4
26: SA 07
E8 lD9C R
E8 lDB4 R
E9 219B R

lE7B
1 E7B
lE7D

FE CC
75 29

lE7F
lE80
lE83
lE86
lE89

53
E8 0052 R
83 C3 47
26: SA 07
5B

lE8A
lE8C

OA DB
75 OA

5545
5546
5547
5548
5549
5550
5551
5552
5553
5554
5555
5556
5557
5558
5559
5560
5561
5562
5563
5564
5565
5566
5567
5568
5569
5570
5571
5572
5573
5574
5575
5576
5577
5578
5579
5580
5581
5582
5583
5584
5585
5586
5587
5588
5589
5590
5591
5592
5593
5594
5595
5596
5597
5598
5599
5600
5601
560?
5603
5604
5605
5606
5607
5608
5609
5610
5611
5612
5613
5614
5615
5616
5617
5618
5619
5620
5621
5622
5623
5624
5625
5626
5627
5628
5629
5630
5631
5632
5633
5634
5635
5636
5637
5638
5639
5640
5641
5642
5643
5644
5645
5646
5647
5648
5649
5650
5651
5652
5653
5654
5655
5656
5657
5658
5659
5660
5661
5662
5663
5664
5665
5666
5667
5668
5669
5670

AH10:
ASSUME

OS:ABSO

test

info,2

JNZ

BM_OK

; ----- HERE THE ega

I N MONOCHROME MODE

IS I N A COLOR MODE

CMP
JE

BYTE PTR AOOR_6845, OB4H
BM_OUT

MOV
OR
JNZ

AH,AL
AH,AH
BM_l

BM_OK:

; ----- set individual reg I star
sub
les
add
les
or

Jz

bp, bp
d i , save_pt r
d i ,4
di ,dword ptr as: (dl]
aX,es
ax,d i

tlo_'

inc

bp

CALL
MOV
MOV
CALL
CALL
or

PAL I N IT
AH, BL
AL,BH
PAL SET
PAL-ON
bp,bp
bm out
a I-;-bh
bh, bh
d i, bx
es: [di La I

tlo_' :

~~v
sub
add

BM_OUT:
JMP

V_RET

DEC
JNZ

AH
BM_2

BM_l :

sub
les
add
les

bp, bp
d i, save_ptr
d i,4

d i , dwo rd pt r es: (d i

or

ax,es
ax,d i

inc

tlo_2
bp

jz

I

t 10_2:

; --- ... - set overscan reg i ster
CALL
MOV
MOV
CALL
CALL

PAL I NIT
AH,Ql1H
AL, BH
PAL SET
PAL::ON

or

bp, bp
bm out
d i-;-011h
es:(di ],bh

jz
add
JMP

V_RET

DEC
JNZ

AH
BM_3

BM_2:

set 16 pa lette reg i ste rs and ove rscan reg i ste r
push
'push

les
add
les
or

Jz
pop

~~~h
mov
rep

ds
d i, save_ptr
d i,4

d i ,dword ptr es: (d I]
aX,es
aX,d i
tlo_3

eS:d i ptrtopal

ds
ds

parameter es

si ,dx
eX,17d

movsb

tlo_3:
pop
pop

es
ds

MOV
CALL
SUB

BX,DX
PAL I N IT
AH,AH

MOV
CALL
INC
INC
CMP
JB
INC
MOV
CALL
CALL
JMP

AL, ES: (BXI
PAL_SET
AH
BX
AH,010H
BM_2A
AH
AL, ES: (BX]
PAL SET
PAL-ON
V_RET

DEC
JNZ

AH
BM_4

BM_2A:

BM_3:

; ----- togg Ie intensify/bl inking bit
BX

PUSH
ca I I
ADO
MOV
POP

BX,Ql0H + In_2
AL, ES: (BX]
BX

OR
JNZ

BL, BL
BM_6

set base

146 IBM Enhanced Graphics Adapter

pa rameter offset

save a rea

lE8E
lE93
lE95
lE98
lE98
lE9A

lE9C
lEAl
lEA3
lEA3
lEA5
lEA8
lEA8

lEAB
lEAB
lEAC
lEAD
lEAE
lEAF
lEBO
lEBl
lEB4
lEB7
lEB8
lEBA
lEBC
lECl
lEC3
lEC3
lEC8
lEC8
lECB
lECE
lECF

80 26 0465 R Of
24 f7
EB OC 90
fE CB
07

7~

80 OE 0465 R 20
OC 08
B4 10
E8 ID9C R
E9 219B R

50
55
53
51
52
06
E8
AO
50
3C
74
C6
EB

E8 ODAE R
E8 0001 R
58
A2 0449 R
07
5A
59
5B
50
58

lED8
lEOA
lEOC
lEOD
lEOE
lEEO
lEE3
lEE5
lEE7
lEE9
lEEC
lEEE
lEEE
lEFO

OA
74
OE
07
2B
B9
FE
75
B7
BD
EB

lEF6
lEF9
lEFB
lEFC
lEFO
lEFF
lFOl
H02
1 F04
H06
H06
HOA
lFOC
lFOE
HOE
lFlO
H12
lFl4
1F16
H18
lF18
lF19
lF1B
lF1D
lFH
lF22
lF23
lF25
lF25

07
07
06 0449 R OB
05

C6 06 0449 R OC

lED2
lED3
lED4
lED5
lE06
lE07

lEF3
lEF3
lEF4
lEF5

0001 R
0449 R

CO
17
02
0100
C8
07
OE
0000 E
05

B7 08
BD 0000 E

06

1F
52
BA
8E
5A
51
Bl
03
59
OA
74

AOOO
C2
05
E2
DB
08

81 C2 4000
FE CB
75 F8
8A
2A
8B
8B
E3

C7
E4
FA
F5
00

51
8B C8
F3/ A4
2B F8
83 C7 20
59
E2 F3
C3

lF26
1F26

lF29
lF2C
lF30

E8
A3
8B
80

0001 R
0485 R
16 0463 R
3E 0449 R 07

5671
5672
5673
5674
5675
5676
5677
5678
5679
5680
5681
5682
5683
5684
5685
5686
5687
5688
5689
5690
5691
5692
5693
5694
5695
5696
5697
5698
5699
5700
5701
5702
5703
5704
5705
5706
5707
5708
5709
5710
5711
5712
5713
5714
5715
5716
5717
5718
5719
5720
5721
5722
5723
5724
5725
5726
5727
5728
5729
5730
5731
5732
5733
5734
5735
5736
5737
5738
5739
5740
5741
5742
5743
5744
5745
5746
5747
5748
5749
5750
5751
5752
5753
5754
5755
5756
5757
5758
5759
5760
5761
5762
5763
5764
5765
5766
5767
5768
5769
5770
5771
5772
5773
5774
5775
5776
5777
5778
5779
5780
5781
5782
5783
5784
5785
5786
5787
5788
5789
5790
5791
5792
5793
5794
5795
5796

;----- enable I ntens i fy
AND
JMP

c rt_mode_set, 110111 1 lb
AL,Of,7H
BM_7

DEC
JNZ

BL
BM_7

and
BM_6:

i- ........ -

enable bl ink

or

c rt_mode_set, 020h

OR

AL,08H

MOV
CALL

AH, P_MODE
PAL_SET

BM_7:
BM_4:
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C+
C+
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

;

JMP

V_RET

VCHGEN. INC
INCLUDE
VCHGEN. INC
SUBTTL
PAGE
_ _ .... _ _ .. _ _ _ _ _ _ .. w _ _ _ .. _ _ . . . . . . _ _ . . . . _ _ .. _ .. _ _ _ _ _ _ . . . . _ _ _ .. _

... _

ENTRY
AL = 0 USER SPEC I F I ED FONT
1 8 X 14 FONT
2 8 X 8 DOUBLE DOT
BL = BLOCK TO LOAD

.

-_ .. -_ .. --_ .. -- --- .. --- ---- --- --_ .... --- ---_ .. -----

........
CH_GEN:

; SAVE THE I NVOLVED REGS

PUSH
PUSH
PUSH
PUSH
PUSH
PUSH

AX
BP
BX
CX
OX
ES

ASSUME
CALL
MOV
PUSH
CMP
JE
MOV
JMP

OS:ABSO
DDS
AL, CRT _MODE
AX
AL,7
H14
CRT _MODE, OBH
SHORT H15

MOV

CRT _MODE, OCH

ca II
CALL
POP
MOV

set_regs
ODS
AX
CRT_MODE,AL

RESET THE DATA SEGMENT
RECOVER OLD MODE VALUE
RETURN TO LOW MEMORY

POP
POP
POP
POP
POP
POP

ES
OX
CX
BX
BP
AX

RESTORE REGS THAT WERE
USED BY THE MODE SET
ROUT I NES

OR
JZ
PUSH
POP
SUB
MOV
DEC
JNZ
MOV
MOV
JMP

AL,AL
00_MAP2
CS
ES
DX,OX
CX,02560
AL
H7
BH,0140
BP,OFFSET CGMN
SHORT 00_MAP2

SET FLAGS
USER SPEC I F I ED FONT
SET SEGMENT TO
TH I S MODULE
ZERO OUT START OffSET
CHAR COUNT (FULL SET)
WH I CH PARAMETER
MUST BE ONE
BYTES PER CHARACTER
8 X 14 TABLE OFfSET
STORE IT

MOV
MOV

BH,8
BP,OFFSET CGDDOT

8 X 8 FONT
ROM 8 X 8 DOUBLE DOT

H14:

SET DATA SEGMENT
GET THE CURRENT MODE
SAVE IT
IS TH I S MONOCHROME
MONOCHROME VALUES
COLOR VALUES
SKI P

; MONOCHROME VALUES

H15:

H7:

;

_ _ . . . . _ _ . . _ _ . . . . _ _ . . _ _ _ _ . . _ _ _ _ . . _ _ _ _ _ _ _ _ _ _ . . . . _ _ _ _ _ . . . . . . 00 . . . . _

ALPHA CHARACTER GENERATOR LOAD
ENTRY
ES: BP - PO I NTER TO TABLE
- COUNT OF CHARS
CX
.. CHAR COUNT OFFSET I NTO MAP 2
OX
- BYTES PER CHARACTER
BH
- MAP 2 BLOCK TO LOAD
BL
bO=MAP2~-----------------------------------------

FONT TABLE SEGMENT
ADDRESS I NG TO TABLE
SAVE REG I STER
ADDRESS I NG TO MAP 2

PUSH
POP
PUSH
SRLOAD
MOV
MOV
POP
PUSH
MOV
SHL
POP
OR
JZ

ES
OS
OX
ES,OAOOOH
DX,OAOOOH
ES,OX
DX
CX
CL,5
OX,CL
CX
BL, BL
H3

RECOVER REG I STER
MULTIPLY BY 020H SINCE
MAX I MUM BYTES PER
CHARACTER IS 32D=020H
RECOVER
WHICH 16K BLOCK TO LOAD
BLOCK ZERO

ADD
DEC
JNZ

DX,04000H
BL
H4

I NCREMENT TO NEXT BLOCK
ANY MORE
DO ANOTHER

MOV
SUB
MOV
MOV
JCXZ

AL,BH
AH,AH
DI,DX
SI,BP
LD_OVER

BYTES PER CHARACTER
ZERO
OFFSET I NTO MAP
OFFSET INTO TABLE
CHARACT ER COUNT

PUSH
MOV
REP
SUB
ADD
POP
LOOP

CX
CX,AX
MOVSB
DI,AX
DI,020H
CX
LD

SAVE CHARACTER COUNT
ONE ENT I RE CHARACTER
AT A TIME
ADJUST OFFSET
NEXT CHARACTER POSITION
RECOVER CHARACTER COUNT
DO THE REST

H4:

H3:

LD:

LO_OVER:
RET
BRK_' :
ASSUME
CALL

DS:ABSO
DDS

MOV
MOV
cmp

crt_mode,7

POINTS,AX

DX, AOOR_6845

;

SET LOW MEMORY SEGMENT

GET BYTES/CHARACTER
CRTC REG I STER

IBM Enhanced Graphics Adapter 147

1 F35
lF37
1 F39
H3C
lF3C
H3E
1 F40
lF43

75 05
B4 14
E8 0018 R
FE
B4
E8
FE

C8
09
0018 R
C8

1 FII5
1 FII7
lF49
lF4B
lF40

8A
8A
FE
B4
CD

E8
C8
Cl
01
10

1 F4 F
1 F53
lf56
1 F59
1 F5B
1 F5E
1 F60
H63
lF63
1 F64
lF68
1 F69
1 F6C
lF6E
1 F70
1 F74
1 F75
IF79
1 F7B
H7E
1 F81
1 F83
1 F87
H89
1 F8e
1 F8F
lF92

8A 1 E 0449 R
B8 015E
80 FB 03
77 08
E8 OE9C R
72 03
B8 00C8
99
F7
48
A2
FE
2A
F7
48
8B
B4
E8
AO
FE
F6
01
05
A3
E8
E9

H95
H95
H97

3C 10
73 17

36 0485 R
0484 R
CO
E4
26 0485 R
16 0463 R
12
0018 R
0484 R
CO
26 044A R
EO
0.100
044C R
OE98 R
219B R

lF99
H9B
H9D
1 FAO
HA3

3C
73
E8
E8
E8

1 FA6
1 FA9
lFAD
1 FAF
lFBl

E8 0001 R
88 OE 0460 R
B4o.l
CD 10
E9 219B R

HB4
HB4
1 f86
HB8

03
17
1 EAB R
OOAE R
OE98 R

75 17
B6 O~
B2 C4

1 FBA
1 FBO

B8 0001
E8 0018 R

1 FCO
H\:2
He4

B4 03
8A 03
E8 0018 R

1 fC7
1 fCA
HCO
1 FCO

s8 0003
E8 0018 R
E9 219B R

lFOO
lFOO
1F02

30 20
73 26

1FD4
1F06
1FD8
1 FDA
1 FOB
IFOC
HDF
1 FE2
1 FE3
1FE4
1 FE6
lFE8
1 FEA
1 FEC
lFEE
IFF1
IFF3
1 fF5
IFF5
lfF7

2C
3C
17
50
53
E8
(8
5B
56
8A
OA

19
02
F3
1 E"!I R
OQAE R
EO
E4

M P
74
BO
8Q
75
BO

09
0.8
FC 01
02
OE

U. E4
[9 lf26 R

1FFA
1FFA
1Ffc
1 FFE
2000

3C
73
2C
75

30
6A
20.
11

5797
5798
5799
5800
5801
5802
5803
5804
5805
5806
5807
5808
5809
5810
5811
5812
5813
5814
5815
5816
5811
5818
5819
5820
5821
5822
5823
5824
5825
5826
5827
5828
5829
5830
5831
5832
5833
5834
5835
5836
5.837
5838
5839
5840
5841
5842
5843
58g4
5845
5846
5847
5848
5849
5850
5851
5852
5853
5854
5855
5856
5857
5858
5859
5860
5861
5862
5863
5864
5865
5866
5867
5868
5&69
5870
5871
5872
5873
~874

5875
5876
5877
5878
5879
5880
5881
58B2
5883
5884
5885
5886
5887
5888
5889
5890
5891
5892
5893
5894
58.95
5896
5891
5898
5899
5900
5901
5902
5903
5904
5905
5906
5907
5908
5909
5910
5911
5912
5913
5914
5915
5916
5917

59 1 8
2002
2004
2006

2B 02
8E DA
FA

5919
5920
5921
5922

C
C
C
C
C
C
C
C
C
C
C
C
C
C

jne

BL, CRT_MODE
AX, 3500
BL,l
H11

CWO
DIV
DEC
MOV
INC
SU~

MUL
DEC

HQV
MOV
CALL
MOV
INC
MUL
SHL
add
MOV
CALL
JMP

;

brst det

hll AX,200D

POINTS - 1
R09H
lIET THE CHARACTER HE I GHT
PO I NTS - II

au rso r s ta rt
cursor end
adjust end

set c_type bios

<;~

set the cursQr

II

, GET THE CURRENT MO[)E
; MAX SCANS ON SCREE,,!
; 640X200 ALPHA MODES
1 H~ST BE ~50
; SET FOR 200
PREPARE TO DIVIDE
MAX I\OWS ON SCREEN
ADJUST
SAVE ROWS
READJUST
CLEAR
ROWS*BYTES/CHAR
ADJUST
CRTC ADDRESS
SCANS 0 I SPLAYED
SET IT
GET CHARACTER ROWS
ADJUST
RQWS*COLUMNS
*2 FOR ALPHA MODE

POI HTS
AX
ROWS,AL.

AL
AH,AH
POINTS
AX
OX, A[lDR_6845
AH,C_ VRT_OSP _END
OUT OX
AL, RQWS
AL
BYTE PTR CRLCOLS
AX,l
ax,2~6d

space between pages

CRLLEN,AX

BYTES PER PAGE
VIDEO ON
RETURN TO CALLER

p~-?

V_RET

; ----- LQADABLE CHi'o.RACTER GENERATOR ROUT I NES
AHll:
CMP
JAE

CHECK PARAMETER
NEXT STAGE

AL,010H
AH11_ALPHAl

; --.-- ALPHA MODE AC,T I V I TY H~RE
CMP
JAE
CALL
ca II
CALL

C
C
C
C

c

e

as,s,ume
ca I t

e

moy
moY

C

C
C
C

I

nt

JMP

RANGE CHECK
NEXT STAGE
SET THE CHAR GEN

AL,OlH
H1
CH GEN

se~_regs

PH 5

ds:~bsO

; VIDEO ON

ddS
cx,eur·sol"_mode
ah t 1
10h
V_RET

$I;lt

the da ta

s~gment

get the mode
s~t

c_type

~lJlulate

correct cursor

RETURN TO CALLER

,----- &ET THE CHARA()TER GENERATOR BLOCK SELEOT REGISTER
H1:
JNE
mov
MOV

C
C

H2

MOV
MOV
CALL

; NOT I N RANGE

dh,3
DL, SEQ_ADDR

; SEQUENCER
; ah=s_reset, a 1=1

mov
ca II

c

AH, S_CGEN
AL,BL
OUT~DX

; CHAR BLOCK REG I STER
I GET THE VALUE
; SET IT

mQV

ca II
H2:

; RETURN TO CALLER

JMP
AH11_ALPHA1 :
ASSUME
CMP
JAE

OS: ABSa
AL,020H
AH11_GRAPH lOS

; --.-. ALPHA MODE ACT IV, TY HERE
SUB
CMP
JA
PUSH
PUSH
CALL

G
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C+
C+
C

R14~

l;ET THE UNI)ERLI NE LOC

Hl1 :

C

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

MOV
MOV
CMP
JA

jc
MOV

o

C
C
C
C

int

cl,al
cl
ah,l
10h

ca"

C
C
C
C
C
C
C
C
C
C
C
C

e

AL
AH, C_MAX_SCAN_LN
OUT_OX
AL

ch,sl

C

G
C

DEC
MOV
CALL
DEC

inc

C
C
C

C
C
C
C
C
C
C
C
C

hIla
AH, C_UNDERLN_LOC
OUT_OX

moy

o
c.
C
C
C
C.
C
C
C
C.

MOV
CALL
h11a:

AL,010H
AL,02H
H2
AX
BX
CH_GEN

ca II

$~~_regs

POP
POP
MOV
OR
MOV
JZ
MOV
CMP
JNE
MOV

BX
AX
AH,AL
AH,AH
AL,BH
H13
AL,8
AH,l
H13
AL,14D

SUB
JMP

AH,AH
BRK_1

H13:

; ADJUST TO 0 - N
; RANGE CHECK
INVALID CALL
SAVE

i

; LOAD THE CHAR (lEN
RESTORE
CALL I NG PARAMETER
USER MODE
DO NOT SET BYTES/CHAR
8 X 8 FONT
I S THE CALL FOR MONOC
NO, LEAVE I T AT B
; MONQO SET
CLEAR UPPER BYTE
CaNT I NUE

;--.-- GRAPHiCS MODE ACTIVITY HERE
AH11 ORAPHICS,
ASSUME
CMP
JAE
SUB
JNZ

DS:ABSO
AL,030H
AHll INFORM
AL,020H
FlO

;----_ COMPATIB.ILITY, UPPER HALF GRAPHICS CHARACTER !>ET
ASSUME
SRLOAQ
SUB
MOV
CLI

OS: ABSQ
OS,O
DX,DX
OS,DX

148 IBM Enhanced Graphics Adapter

2007
2006
200F
2010
2010
2013

69 2E 007C R
6C 06 007E R
FB

2013

52

2014
2016
2018
2019
2018
2010
20lF
2021
2022
2023
2025
2027
202A
2020
202F
202F
2032
2035
2035
2036
203A
203E

2B
8E
5A
3C
77
FE
74
OE
07
FE
75
B9
Bo
EB

203F
2042
2046
2048
204B
2040
204F
2051
2054
2054
2056
2058
205A
205A
205C
205C
205E
2061

E8
89
SA
BB
OA
75
SA
EB

2064
2064

E9 219B R

02
DA
03
F3
C6
14
C8
08
OOOE
0000 E
06

B9 0008
Bo 0000 E
FA
89 2E 010C R
8C 06 010E R
FB
0001 R
OE 0485 R
C3
2064 R
CO
05
C2
09 90

3C 03
76 02
60 02
2E: 07
FE C8
A2 0484 R
E9 219B R
00 OE 19 2B

2068
2068
206A
206C
206C
206F
206F
2073
2077
207A
207C
207F

3C 30
74 03
E9 219B R
8B
8A
80
77
80
77

OE
16
FF
fO
ff
18

0485 R
0484 R
07
01

2081

52

2082
2084
2086
2087
2089

2B
8E
5A
OA
75

208B
208F
2092

C4 2E 007C R
EB lA 90

2092
2096

C4 2E 010C R
EB 13 90

02
oA
FF
07

2099
2099
209C
209E
20AO
20A2
20M
20A9
20AA
20AB
20AB
20AO
20Ao
20AE
20M
_ _ 20BO
20Bl
20B2
20B3

20B4
20B4
20B6
20B8
20BA

80 Ef 02
SA Of
2A FF
01 E3
81 C3 20B4 R
2E: 8B 2f
OE
07
5f
5E
5B
58
58
IF
58
58
CF

0000
0000
0000
0000

E
E
E
E

20BO
20BO

80 FB 10

5923
5924
5925
5926
5927
5928
5929
5930
5931
5932
5933
5934
5935
5936
5937
5938
5939
5940
5941
5942
5943
5944
5945
5946
5947
5948
5949
5950
5951
5952
5953
5954
5955
5956
5957
5958
5959
5960
5961
5962
5963
5964
5965
5966
5967
5968
5969
5970
5971
5972
5973
5974
5975
5976
5977
5978
5979
5980
5981
5982
5983
5984
5985
5986
5987
5988
5989
5990
5991
5992
5993
5994
5995
5996
5997
5998
5999
6000
6001
6002
6003
6004
6005
6006
6007
6008
6009
6010
6011
6012
6013
6014
6015
6016
6017
6018
6019
6020
6021
6022
6023
6024
6025
6026
6027
6028
6029
6030
6031
6032
6033
6034
6035
6036
6037
6038
6039
6040
6041
6042
6043
6044
6045
6046
6047
6048

C
C
C
C
C
C
C
C
C
C+
C+
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C+
C+
C
C
C
C
C+
C
C
C
C+
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

MOV
MOV
STI

WORD PTR EXT_PTR , BP
WORD PTR EXT_PTR + 2 , ES

JMP

V_RET

ASSUME
PUSH
SRLOAo
SUB
MOV
POP
CMP
JA
DEC
JZ
PUSH
POP
DEC
JNZ
MOV
MOV
JMP

DS:ABSO
OX
OS,O
oX,QX
OS,OX
OX
AL,03H
Fll
AL
F19
CS
ES
AL
F13
CX,14O
BP, OFFSET CGMN
SHORT F19

MOV
MOV

CX,8
BP, OFFSET CGooOT

Fll :
flO:

; RANGE CHECK

; ROM 8 X 14 CHARACTER SET

F13:
; ROM 6 X 8 DOUBLE DOT

F19:
CLI
MOV
MOV
STI
ASSUME
CALL
MOV
MOV
MOV
OR
JNZ
MOV
JMP

WORD PTR GRX_SET , BP
WORD PTR GRX_SET + 2 ,

ES

oS:ABSO
DDS
PO I NTS, CX
AL,BL
BX, OFFSET RT
AL,AL
DR 3
AL-;-oL
OR_l

OR_3:
CMP
JBE
MOV

AL,3
DR 2
AL-;-2

OR_2:
XLAT

CS: RT

DEC
MOV
JMP

AL
ROWS,AL
V_RET

LABEL
DB

BYTE
000,140,250,430

DR_I:

RT

I NFORMAT I ON RETURN DONE HERE
AH11

- INFORM:
ASSUME
CMP
JE

F5:

DS:ABSO
AL,030H
F6

JMP

V_RET

MOV
MOV
CMP
JA
CMP
JA

CX, PO I NTS
oL, ROWS
BH,7
f5
BH,1
F7

ASSUME
PUSH
SRLOAo
SUB
MOV
POP
OR
JNZ
WLXS
LES
JMP

oS:ABSO
OX
OS,O
DX,oX
OS,OX
OX
BH,BH
F9
ES,BP, EXT_PTR
BP, EXT_PTR
INFORM_OUT

WLXS
LES
JMP

ES, BP ,GRX_SET
BP,GRX_SET
INFORM_OUT

F6:

F9:

; ----- HANDLE BH

=2

THRU

BH

=5

HERE

RETURN ROM TABLE PO INTERS

f7:
ASSUME
SUB
MOV
SUB
SAL
ADD
MOV
PUSH
POP
INFORM_OUT:
POP
POP
POP
POP
POP
POP
POP
POP
I RET

oS:ABSO
BH,2
BL, BH
BH, BH
BX,1
BX, OFFSET TBL_5
BP,CS: [BX)
CS
ES
01
SI
BX
AX
AX
OS
AX
AX

; 0 I SCARD SAVED CX
; 0 I SCARo SAVED OX
; 0 I SCARo SAVED ES
; 0 I SCARD SAVED BP

; ----- TABLE OF CHARACTER GENERATOR OFFSETS
TBL_5

LABEL
OW
PW
OW
OW

WORD
OFfSET
OFFSET
OFFSET
OFFSET

CGMN
CGOOOT
INT I f 1
CGMN_FjjG

SUBTTL
; ----- ALTERNATE SELECT
AHI2:
ASSUME
CMP

DS;ABSO
BL,010H

RETURN ACT I VE CALL

IBM Enhanced Graphics Adapter 149

20BF
20Cl
20C3
20C6
20C8
20CB

72
74
80
74
E9

51
lB
FB 20
03
219B R

20CB
20CO
20CF
2000
2006
200A
200B
200E
200E
20E2
20E5

2B
8E
FA
C7
8C
FB
E9

20E7
20EA
20EC
20EE
20FO

AO
24
Bl
02
8A

0487 R
60
05
E8
08

20F2
20F6
20F8
20FB
20FO
20FF
2101
2103

8A
8A
80
DO
DO
DO
DO
80

OE 0488 R
E9
El OF
ED
ED
ED
ED
E5 OF

2106
2107
2108
2109
210A
210B
210C
2100
210E
210F
210F
2112
2112
2112

SF
5E
SA
SA
SA
1F
07
50
CF

2115
2115
2117
2119
211B
211C
211 E
2120
2123
2126
2127
2128
2129
212C
212E
212F
212F
2130
2131
2132
2134
2138
2139
213B
2130
213F
2141
2143
2145
2147
2149
214C
214F
2151
2155
2156
2156
2158
215A
215C
2160
2162
2166
2168
216B
2160
216F
216F
2171
2173
2173
2176
2178
217A
217A
217C
217E
2180
2182
2184
2188
2188
2189
218A
218B

02
OA
06 0014 R 21A4 R
OE 0016 R
219B R

8A 3E 0487 R
80 E7 02
DO EF

E9 219B R
E9 219B R

3C
73
E3
53
8A
2A
01
68
5B
56

04
F9
F7
OF
FF

E3
B7 0450 R

50
B8 0200
CD 10
58
51
53
50
86 EO
26: 8A 46 00
45
3C 00
74 3D
3C OA
74 39
3C 08
74 35
3C 07
74 31
B9 0001
80 FC 02
72 05
26: 8A 5E 00
45
B4 09
CD 10
FE C2
3A 16 044A R
72 11
3A 36 0484 R
75 07
B8 OEOA
CD 10
FE CE
FE C6
2A 02
B8 0200
CD 10
E8 OE
B4
CD
8A
2A
01
88

OE
10
OF
FF
E3
97 0450 R

58
58
59
E2 A2

2160

5A

216E
2190
2192
2194
2196
2199

3C
74
3C
74
B8
CD

01
09
03
05
0200
10

6049
6050
6051
6052
6053
6054
6055
6056
6057
6056
6059
6060
6061
6062
6063
6064
6065
6066
6067
6068
6069
6070
6071
6072
6073
6074
6075
6076
6077
6076
6079
6080
6081
6082
6063
6084
6065
6066
6067
6066
6069
6090
6091
6092
6093
6094
6095
6096
6097
6098
6099
6100
6101
6102
6103
6104
6105
6106
6107
6108
6109
6110
6111
6112
6113
6114
6115
6116
6117
6118
6119
6120
6121
6122
6123
6124
6125
6126
6127
6128
6129
6130
6131
6132
6133
6134
6135
6136
6137
6138
6139
6140
6141
6142
6143
6144
6145
6146
6147
6148
6149
6150
6151
6152
6153
6154
6155
6156
6157
6158
6159
6160
6161
6162
6163
6164
6165
6166
6167
6168
6169
6170
6171
6172
6173
6174

J8
JE
CMP
JE
JMP

ACT_l
ACT_3
BL,020H
ACT_2
V_RET

SRLOAO
SUB
MOV
CLI
MOV
MOV
STI
JMP

OS,O
OX, OX
OS,OX

mov

and
shr

; ALTERNATE PRINT SCREEN
,
;

I NVALI 0 CALL
NEW PR I NT SCREEN

WORD PTR INT5_PTR, OFFSET PRINT_SCREEN
WORD PTR I NT5_PTR+2, CS
V_RET

looking for manoe bit
isolate

bh, info
bh,2
bh,l

mav
and

81, info
al,01100000b

mav
shr
mav

cl,5
a I,e I

MOV
MOV
AND
SHR
SHR
SHR
SHR
AND

CL, I NFO_3
CH, CL
CL,OFH
CH,l
CH,l
CH,l
CH,l
CH,OFH

POP
POP
POP
POP
POP
POP
POP
POP
IRET

01
SI
OX
OX
OX
OS
ES
BP

adjust

look ing for memory
memory bits
shift count

adjust mem va I ue
return register

bl,8 I

FEATURE/SWI TCH
, ~UPLICATE IN CH
; MASK OFF SWI TCH VALUE
; MOVE FEATURE VALUE

MASK IT

DISCARD BX
01 SCARO CX

RETURN TO CALLER
ACT_' :
STR OUTZ:
JMP

RETURN TO CALLER

; ----- WR I TE STR I NG
AH13:
CMP
JAE
JCXZ
PUSH
MOV
SUB
SAL
MOV
POP
PUSH

AL,04
STR OUTZ
STR-OUTZ
BX BL, BH
BH, BH
BX,l
51, (BX + OFFSET CURSOR_POSN)
BX
SI

PUSH
MOV
I NT
POP

AX
AX,0200H
10H
AX

PUSH
PUSH
PUSH
XCHG
MOV
INC

CX
BX
AX
AH, AL
AL, ES: (BP)
BP

CMP

AL,ODH

JE
CMP
JE
CMP
JE
CMP
JE
MOV
CMP
JB
MOV
INC

STR_CR_LF
AL,OAH
STR CR LF
AL,08HSTR CR LF
AL,07HSTR_CR_LF
CX,l
AH,2
DO STR
BL-;-ES: (BP)
BP

MOV
I NT
INC
CMP
J8
CMP
JNE
MOV
I NT
DEC

AH,09H
10H
OL
OL, BYTE PTR CRT_COLS
STR 2
OH, ROWS
STR 3
AX,OEOAH
10H
OH

OO_STR:

INC
SUB
MOV
I NT
JMP
STR CR LF:
- MOV
I NT
MOV
SUB
SAL
MOV

RANGE CHECK
I NVALI 0 PARAMETER
SAVE REGI STER
GET PAGE TO LOW BYTE

*2 FOR WORD OF FSET
GET CURSOR POS I T ION
RESTORE
CURRENT VALUE ON STACK
SET THE CURSOR POS I T I ON

;

GET THE CHAR TO WR I TE

; CARR I AGE RETURN
LINE FEED
;

BACKSPACE

;

BELL

; COUNT OF CHARACTERS
; CHECK WHERE ATTR IS
; NOT IN THE STRING
; GET THE A TTR I BUTE
; NEXT ITEM IN STRING
; WR ITE THE CHAR/ATTR
NEXT CURSOR POS I T I ON
, COLUMN OVERFLOW
; NOT YET

OH
OL,OL

NEXT ROW
COLUMN ZERO

AX,0200H
10H
SHORT
STR_4

SET TH E CURSOR

AH,OEH
10H
BL,BH
BH,BH
BX,l
OX, (BX + OFFSET CURSOR_POSN)

POP
POP
POP
LOOP

AX
BX
CX
STR_'

POP

OX

CMP
JE
CMP
JE
MOV
I NT

AL,l
STR OUT
AL, "3
STR OUT
AX,0200H
10H

1 SO IBM Enhanced Graphics Adapter

; GET PAGE TO LOW BYTE

; *2 FOR WORD OF FSET
; GET CURSOR POS I T ION

RECOVER CURSOR POS I T I ON
FROM PUSH S I ABOVE

SET CURSOR POS I T I ON

219B

219B
219B
219C
2190
219E
219F
21AD
21A1
21A2
21A3
21A4

5F
5E
5B
59
5A
1F
07
50
CF

21A4

21A4
21M
21A5
21A6
21A7
21A8
21A9
21M
21AD
21B2
21B4
21B9
21BB

21BO
21 B F
21C3
21C5
21C8
21C9
21CB
21CO
21CE
21CF

2101
2101
2103
2105
2107
2109
210B
21 DO
21DF
210F
21EO
21E2
21 E4
21E6
21 E7
21EA
21EC
21EE
21FO
21F2
21F4
21F6
21F7
21FA
21FB
21F0
21FF
2201
2202
2204
2206
220B
2200
2200
220E
2210
2212
2217
2217
2218
2219
221A
221 B
221C
2210

2210
2210
221F

FB
lE
50
53
51
52
E8
80
74
C6
B4
CO

8A
8A
FE
E8
51
B4
CO
59
52
33

B4
CO
B4
CO
OA
75
BO
52
33
32
CD
5A
F6
75
FE
3A
75
32
8A
52
E8
5A
FE
3A
75
5A
B4
CD
C6
EB

0001 R
3E 0500 R 01
63
06 0500 R 01
OF
10

CC
2 E 0484 R
C5
2210 R
03
10
02

02
10
08
10
CO
02
20
02
E4
17
C4 29
21
C2
CA
OF
02
E2
2210 R
C6
EE
DO
02
10
06 0500 R 00
OA

5A
B4 02
CD 10
C6 06 0500 R FF
5A
59
5B
58
1F
CF

33 02
32 E4

6175
6176
6177
6178
6179
6180
6181
6182
6183
6184
6185
6186
6187
6188
6189
6190
6191
6192
6193
6194
6195
6196
6197
6198
6199
6200
6201
6202
6203
6204
6205
6206
6207
6208
6209
6210
6211
6212
6213
6214
6215
6216
6217
6218
6219
6220
6221
6222
6223
6224
6225
6226
6227
6228
6229
6230
6231
6232
6233
6234
6235
6236
6237
6238
6239
6240
6241
6242
6243
6244
6245
6246
6247
6248
6249
6250
6251
6252
6253
6254
6255
6256
6257
6258
6259
6260
6261
6262
6263
6264
6265
6266
6267
6268
6269
6270
6271
6272
6273
6274
6275
6276
6277
6278
6279
6280
6281
6282
6283
6284
6285
6286
6287
6288
6289
6290
6291
6292
6293
6294
6295
6296
6297
6298
6299
6300

V_RET

PROC
POP
POP
POP
POP
POP
POP
POP
POP
IRET
ENDP

V_RET

NEAR
01
SI
BX
CX
OX
OS
ES
BP

COMBO_VI OED

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

;

ALLOW FALL THROUGH

;

VIDEO BIOS RETURN

ENDP

INCLUDE
VPRSC. INC
SUBTTL VPRSC. I HC
PAGE

; - ---- - - - - - ------ - ------ --- -- --- ------ - --- - ---- -- - --- - -- ------- --- ------INTERRUPT 5
THIS LOGIC WILL BE INVOKED BY INTERRUPT 05H TO PRINT THE
SCREEN. THE CURSOR POSITION AT THE TIME THIS ROUTINE IS INVOKED
WILL BE SAVED AND RESTORED UPON COMPLETION. THE ROUTINE IS
INTENDED TO RUN WITH INTERRUPTS ENABLED. IF A SUBSEQUENT
'PRINT SCREEN' KEY IS DEPRESSED DURING THE TIME THIS ROUTINE
IS PRINTING IT WILL BE IGNORED.
ADDRESS 50:0 CONTAINS THE STATUS OF THE PRINT SCREEN:
50: 0

=0

EITHER PR I NT SCREEN HAS NOT BEEN CALLED
OR UPON RETURN FROM A CALL THIS INDICATES
A SUCCESSFUL OPERAT I ON.
PR I NT SCREEN I SIN PROGRESS
ERROR ENCOUNTERED OUR I NG PR I NT I NG

=1
=255

; - - - -- - - - - - - - -- -- - - - - - -- -- - - - - -- -- ---- - -- - - -- - - -- ----- -- - - --- - ------ - - --CS: CODE, OS: ABSO
PROC
FAR
MUST RUN WI TH I NTS ENABLED
MUST USE 50: 0 FOR DATA
OS
area storage
AX
BX
USE TH I S LATER FOR CURSOR LI M ITS
CX
WI LL HOLD CURRENT CURSOR POS
OX
DDS
, SEE IF PR I NT ALREADY I N PROGRESS
STATUS_BYTE,l
; JUMP IF PR I NT I N PROGRESS
EXIT
; INDICATE PRINT NOW IN PROGRESS
STATUS_BYTE,l
; WILL REQUEST THE CURRENT MODE
AH,15
;
I AL )=MODE (NOT USED)
10H
;
I AH )=NUMBER COLUMNS/LI NE
;
I BH )=V I SUAL PME
; _...... ...............
..................................... ............................ .. ..... ---_ ................ ...
AT THIS POINT WE KNOW THE COLUMNS/LINE ARE IN
ASSUME
PR I NT SCREEN
STI
PUSH
PUSH
PUSH
PUSH
PUSH
CALL
CMP
JZ
MOV
MOV
I NT

-

-_

-_ -_

-_

-~

-_

--

~~~)D~~~/~U~:6xl~U~m~C~m ~~SI~lb~~)M06~E STACK
; ---------------------------------------------------------------;

;

MOV
MOV
INC
CALL
PUSH
MOV
I NT
POP
PUSH
XOR

-_ ........ --_ ......... -_

CL,AH
CH, ROWS
CH
CRLF
CX
AH,3
10H
CX
OX
OX, OX

..............

,
;
;
;
;
;
;
;
;
;

WILL MAKE USE OF ICX) REG TO
CONTROL ROW & COLUMNS
A~JUST
'
CAR RETURN LINE FEED ROUT I NE
SAVE SCREEN BOUNDS
WI LL NOW READ THE CURSOR.
AND PRESERVE THE POS I T I ON
RECALL SCREEN BOUNDS
RECALL IBH)=VISUAL PAGE
SET CURSOR POSITION TO 10,0)

-_ ......... --- -_ .......................... -_ .. ---_ ... ---- -_ .. ---- ----

THE LOOP FROM PR 110 TO THE I NSTRUCT I ON. PR I OR TO PR 120
IS THE LOOP TO READ EACH CURSOR POSITION FROM THE
SCREEN AND PR I NT.
~~~~o;---------------------------------

AL,AL
PRI15

AL#

. . . . ---------.. . --------.. --TO INDICATE CURSOR SET REQUEST
NEW CURSOR POS ESTABL I SHED
TO INDICATE READ CHARACTER
CHARACTER NOW I N I AL)
SEE I F VAL I 0 CHAR
JUMP I F VAL I 0 CHAR
MAKE A BLANK

AH,2
10H
AH,8
10H

MOV
I NT
MOV
INT
OR
JNZ
MOV

I

PR115:
PUSH
XOR
XOR
INT
POP
TEST
JNZ
INC
CMP
JNZ
XOR
MOV

SAVE CURSOR POS I T I ON
INDICATE PRINTER 1
TO INDICATE PRINT CHAR IN [AL)
PR I NT THE CHARACTER
RECALL CURSOR POS I T I ON
TEST FOR PR I NTER ERROR
JUMP I F ERROR DETECTED
ADVANCE TO NEXT COLUMN
SEE IF AT END OF LINE
I F NOT PROCEED
BACK TO COLUMN 0
[AH )=0

OX

DX,DX

CALL
POP
INC
CMP
JNZ

AH,AH
17H
OX
AH,029H
ERR10
OL
CL,DL
PRll0
DL,DL
AH,Dl
OX
CRLF
OX
OH
CH,OH
PRll0

POP
MOV
INT
MOV
JMP

OX
AH,2
10H
STATUS_BYTE,O
SHORT EXIT

RECALL CURSOR POS I T I ON
TO INDICATE CURSOR SET REQUEST
CURSOR POS I T I ON RESTORED
INDICATE FINISHED
EXIT THE ROUTINE

POP
MOV
I NT
MOV

OX
AH,2
10H
STATUS_BYTE,OFFH

GET CURSOR POS I T I ON
TO REQUEST CURSOR SET
CURSOR POS I T ION RESTORED
INDICATE ERROR

OX
CX
BX
AX
OS

RESTORE ALL THE REG I STERS USED

PUSH

SAVE NEW CURSOR POS I T I ON

LINE FEED CARR I AGE RETURN
RECAll CURSOR POS I T ION
ADVANCE TO NEXT LINE
F INI SHED?
I F NOT CONT I NUE

ERR10:

EXIT:
POP
POP
POP
POP
POP
IRET
PR I NT_SCREEN

ENDP

; ------ CARR I AGE RETURN,
CRlF

PROC
XOR
XOR

NEAR
OX,DX
AH,AH

II NE FEED SUBROUT I NE
PR INTER 0
Will NOW SEND
TO PRI NTER

INITIAL CR,

LF

IBM Enhanced Grapbics Adapter 151

2221
2223
2225
2227
2229
222B
222C

BO
CO
32
BO
CO
C3

00
17
E4
OA
17

6301
6302
6303
6304
6305
6306
6307
6308
6309
6310
6311
6312

222C

CRLF

1
2

3
4

CODE

0000

5
6

CCMN

0008
OOOE
0016
001C
0024
002A
0032
0038
0040
0046
004E
0054
005C
0062
006A
0070
0078
007E
0086
008C
0094
009A
00A2
00A8
OOBO
00B6
OOBE
00C4
OOCC
0002
OODA
OOEO
00E8
OOEE
00F6
OOFC
0104
010A
0112
0118
0120
0126
012E
0134
013C
0142
014A
0150
0158
015E
0166
016C
0174
017A
0182
0188
0190
0196
019E
01A4
01AC
01B2
01BA
01CO
01 C8
01CE
0106
01DC
01E4
OlEA

00
00
00
00
81
99
00
H
£7
00
FE
7C
00
FE
38
00
E7
18
00
FF
18
00
3C
18
FF
C3
E7
00
42
66
FF
Bo
99
00
78
CC
00
3C
7E
00
30
70
00
63
67

00
00
00
00
Bo
81
00
C3
FF
00
FE
38
00
7C
10
00
E7
18
00
7E
16
00
3C
00
FF
C3
FF
00
42
3C
FF
Bo
C3
00
CC
CC
00
18
18
00
30
FO
00
63

00
FE
EO
00
FE
OE
00
18
7E
00
66
00
00
7B
lB
00
C6
6C
00
00
FE
00
18
7E
00
18
18
00
18
7E
00
FE
18
00
FE
30
00
CO
FE
00
FE
28
00
7C
FE
00
7C
38

00
F8
CO
00
3E
06
00
18
3C
00
66
66
00
lB
lB
7C
C6
38
00
00
FE
00
18
3C
00
18
18
00
18
3C
00
OC
00
00
60
00
00
CO
00
00
6C
00
00
7C
FE
00
38
10

00
00
00
00
18
00
00
00
00
00

00
00
00
00
18
18
66
00
00
00

00 00 00 00
00 00 00 00
7E 81 A5 81
7E 00 00 00
7E FF DB FF
7E 00 00 00
00 6C FE FE
10 00 00 00
00 10 38 7C
00 00 00 00
18 3C 3C E7
3C 00 00 00
18 3C 7E FF
3C 00 00 00
00 00 00 18
00 00 00 00
H FF FF E7
FF FF FF FF
00 00 3C 66
00 00 00 00
FF H C3 99
FF FF FF FF
IE OE lA 32
78 00 00 00
3C 66 66 66

7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

33
34
35
36
37
38
39
40
41
42
43

AL,OoH
17H
AH,AH
AL,OAH
17H

CR
SEND THE LINE FEED
NOW FOR THE CR
LF
SEND THE CARR I AGE RETURN

SUBTTL
CODE

0000

0000

MOV
INT
XOR
MOV
INT
RET
[NDP

ENDS
END
PAGE,120
SUBTTL MONOCHROME CHARACTER GENERATOR
SEGMENT PUBL I C
PUBLIC CGMN
LABEL
BYTE

~~P~~l~F :~6TTERN

08

OOOH,OOOH, OOOH,OOOH, OOOH, OOOH,OOOH,OOOH ;

DB
DB

OOOH,OOOH,OOOH,OOOH,OOOH,OOOH
, BOTTOM_HALF 00
000H,OOOH,07EH,081H,OA5H,081H,081H,OBDH ; TH_Ol

DB
DB

099H,08tH,07EH,OOOH,OOOH,OOOH
OoOH, 000H,07EH, OHM,ODBH, OFFH, OHH,OC3H

BT 01
TH::02

DB
DB

OE7H, OFFH, 07EH,OOOH, OOOH, OOOH
OOOH, OOOH, OOOH, 06CH, OFEH, OFEH, OFEH, OFEH

BT_02
TH_03

DB
DB

07CH, 038H, 010H, OOOH, OOOH, OOOH
OOOH, OOOH, OOOH, 010H, 038H, 07CH, OFEH, 07CH

BT_03
TH_04

DB
DB

038H, 01 OH, OOOH, OOOH, OOOH, OOOH
OOOH, OOOH, 018H, 03CH, 03CH, OE7H, OE7H, OE7H

BT 04
TH::05

DB
DB

Ot8H,018H,03CH,OOOH,OOOH,OOOH
OOOH, OOOH, 018H, 03CH, 07EH, OHH, OFFH, 07EH

BT 05
TH::06

DB
DB

018H,018H,03CH,OOOH,OOOH,OOOH
OOOH, OOOH, OOOH, OOOH, OOOH, 0 18H, 03CH, 03CH

BT_06
TH_07

08
DB

018H,OOOH,OOOH,OOOH,OOOH,OOOH
OHH, OFFH, OFFH, OFFH, OFFH, OE7H, OC3H, OC3H

BT 07
TH::08

DB
DB

OE7H,OFFH,OFFH,OFFH,OFFH,OFFH
OOOH, OOOH, OOOH, OOOH, 03CH, 066H, 042H, 042H

BT 08
TH::09

DB
DB

066H, 03CH, OOOH, OOOH, OOOH, OOOH
OFFH, OFFH, OFFH, OFFH, OC3H, 099H, OBOH, OBoH

BT 09
TH::OA

DB
DB

099H.OC3H.OFFH,OFFH,OFFH,OFFH
OOOH, OOOH, OtEH. OOEH, 01 AH, 032H, 078H, OCCH

BT OA
TH::OB

OB
DB

OCCH, OCCH, 0 78H, OOOH, OOOH, OOOH
OOOH, OOOH, 03CH. 066H, 066H, 066H, 03CH, 018H

B T OB
TH::OC

DB
DB

07EH.018H.018H.000H.000H.000H
OOOH, OOOH, 03 FH, 033H, 03 FH, 030H. 030H, 030H

BT DC
TH::OD

DB
DB

070H. OFOH, OEOH, OOOH, OOOH, OOOH
OOOH, OOOH, 07 FH, 063H, 07 FH, 063H, 063H, 063H

BT_OD
TH_OE

DB
DB

067H,OE7H,OE6H,OCOH,OOOH,ODOH
OOOH, OOOH, 018H, 018H, ODBH, 03CH, OE7H, 03CH

BT_OE
TH_OF

DB

OoBH, 018H, 0 18H, OOOH, OOOH, OOOH

44
18 00 00 00
3F 33 3F 30
EO 00 00 00
7F 63 7F 63

E7 E6 CO 00 00
00 18 18 DB 3C
E7 3C
DB 18 18 00 00 00

ou

80 CO EO F8
80 00 00 00
02 06 OE 3E
02 00 00 00
18 3C 7E 18
18 00 00 00
66 66 66 66
66 00 00 00
7F DB DB DB
lB 00 00 00
C6 60 38 6C
OC C6 7C 00
00 00 00 00
FE 00 00 00
18 3C 7E 18
18 7E 00 00
18 3C 7E 18
18 00 00 00
18 18 18 18
18 00 00 00
00 00 18 OC
00 00 00 00
00 00 30 60
00 00 00 00
00 00 00 CO
00 00 00 00
00 00 28 6C
00 00 00 00
00 10 38 38
00 00 00 00
00 FE FE 7C
00 00 00 00
00 00 00 00
00 00 00 00
18 3C 3C 3C
18 00 00 00
66 66 24 00
00 00 00 00
6C 6C FE 6C

45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71

72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114

OOOH,OOOH,060H,OCOH,OEOH,Of8H,OfEH,Of8H ; TH_10

DB
DB

OEOH, OCOH, 080H, OOOH, OOOH, OOOH
, BT 10
000H,OOOH,002H,006H,OOEH,03EH,OFEH,03EH ; TH::11

DB
DB

OOEH, 006H, 002H, OOOH, OOOH, OOOH
OOOH, OOOH, 0 18H, 03CH, 07EH, 018H, 018H, 018H

DB
DB

07EH,03CH,018H,OOOH,OOOH,OOOH
, BT 12
000H,OOOH,066H,066H,066H,066H,066H,066H ; TH=13

DB
DB

OOOH, 066H, 066H, OOOH, OOOH, OOOH
, BT _ 1 3
000H,OOOH,07FH,ODBH,ODBH,ODBH,07BH,OlBH ; TH_14

DB
DB

01BH,OlBH,OlBH,OOOH,OOOH,OOOH
OOOH, 07CH, OC6H,060H,038H,06CH,OC6H,OC6H

OB
OB

06CH, 038H, OOCH, OC6H, 07CH, OOOH
, BT 15
OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH ; TH:: 16

BT _ 11
TH_ t 2

BT_14
TH_15

DB
DB

OFEH, OFEH, OFEH, OOOH, OOOH, OOOH
OOOH, OOOH, 018H, 03CH, 07EH, 018H, 0 18H, 0 18H

BT 16
TH::17

DB
OB

07EH,03CH,018H,07EH,OOOH,OOOH
OOOH, OOOH, 018H, 03CH, 07EH, 018H, 018H, 018H

BT_17
TH_18

OB
DB

018H,018H,018H,OOOH,OOOH,OOOH
, BT_18
OOOH,OOOH,018H,016H,018H,018H,018H,018H ; TH_19

DB
DB

07EH,03CH,018H,OOOH,OOOH,OOOH
, BT_19
000H,OOOH,OOOH,OOOH,018H,OOCH,OFEH,OOCH ; TH_1A

DB
DB

018H,OOOH,OOOH,OOOH,OOOH,OOOH
OOOH, OOOH, OOOH, OOOH, 030H, 060H, 0 FEH, 060H

DB
DB

030H,OOOH,OOOH,OOOH,OOOH,OOOH
; BT_1B
OOOH, OOOH, OOOH, OOOH, OOOH, OCOH, OCOH, OCOH ; TH_l C

BT_1A
TH_ 1 B

DB
DB

OFEH, OOOH, OOOH, OOOH, OOOH, OOOH
, BT 1 C
OOOH, OOOH, OOOH, OOOH, 028H, 06CH, OFEH, 06CH ; TH::1D

DB
DB

028H, OOOH, OOOH, OOOH, OOOH, OOOH
, BT 10
000H,OOOH,OOOH,OtOH,038H,038H,07CH,07CH ; TH::1E

DB
OB

OFEH,OFEH,OOOH,OOOH,OOOH,OOOH
OOOH, OOOH, OOOH, OFEH, OFEH, 07CH, 07CH, 038H

OB

038H, 01 OH, OOOH, OOOH, OOOH, OOOH

BT_l E
TH_l F

DB

OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH ; TH_20 SP

DB
DB

OOOH,OOOH,OOOH,OOOH,OOOH,OOOH
, BT 20 SP
000H,OOOH,018H,03CH,03CH,03CH,018H,018H ; TH::21 !

DB
DB

000H,Ot8H,016H,OOOH,OOOH,OOOH
, BT 21 !
OOOH, 066H, 066H, 066H, 024H, OOOH, OOOH, OOOH ; TH::22 "

DB
DB

OOOH,OOOH,OOOH.OOOH,OOOH,OOOH
, BT_22 "
OOOH, OOOH, 06CH, 06CH, OFEH, 06CH, 06CM, 06CH ; TH_23 /I

152 IBM Enhanced Graphics Adapter

01F2
01F8
0200
0206
020E
0214
021C
0222
022A
0230
0238
023E
0246
024C
0254
025A
0262
0268
0270
0276
027E
0284
028C
0292
029A
02AO
02A8
02AE
02B6
02BC
02C4
02CA
0202
02D8
02EO
02E6
02EE
02F4
02FC
0302
030A
0310
0318
031E
0326
032C
0334
033A
0342
0348
0350
0356
035E
0364
036C
0372
037A
0380
0388
038E
0396
039C
03A4
03AA
03B2
03B8
03CO
03C6
03CE
0304
03DC
03E2
03EA
03FO
03F8
03FE
0406
040C
0414
041A
0422
0428

6C
FE
18
7C
86
00
DC
30
00
76
CC
00
00
00
00
30
30
00
DC
DC
00
FF
66
00
7E
18
00
00
18
00
FE
00
00
00
00
00
30
CO

6C
6C
18
06
C6
00
18
66
00
DC
CC
30
00
00
00
30
18
00
OC
18
00
3C
00
00
18
00
00
00
18
00
00
00
00
00
18
00
60
80

00
F6
C6
00
18
18
00
18
60
00
3C
06
00
CC
DC
00
FC
06
00
FC
C6
00
18
30
00
7C
C6
00
7E
06
00
00
18
00
00
18
00
60
18
00
00
7E
00
06
18
00
18
00

00 7C
E6
C6 7C
00 18
18
18 7E
00 7C
30
C6 FE
00 7C
06
C6 7C
00 DC
FE
DC 1 E
00 FE
06
C6 7C
00 38
C6
C6 7C
00 FE
30
30 30
ODIC
C6
C6 7C
00 7C
06
DC 78
00 00
00
18 00
00 00
00
18 30
00 06
30
DC 06
00 00
00
00 00
00 60
DC
30 60
00 7C
18
18 18

00
DE
DC
00
C6
C6
00
7C
66
00
CO
C2
00
66
66
00
78
62
00
78
60
00
CO
C6
00
FE
C6
00
18
18
00
DC
CC
00
78
6C
00
60

00 7C
DE
CO 7C
00 10
FE
C6 C6
00 FC
66
66 fC
00 3C
CO
66 3C
00 f8
66
6C F8
00 FE
68
66 FE
00 fE
68
60 fO
00 3C
DE
66 3A
00 C6
C6
C6 C6
00 3C
18
18 3C
ODIE
DC
CC 78
00 E6
6C
66 E6
00 fO
60

6C 00 0000
7C C6 C2 CO
7C 18 18 00
00 00 C2 C6
C6 00 00 00
38 6C 6C 38
76 00 00 00
30 30 60 00
00 00 00 00
DC 18 30 30
OC 00 00 00
30 18 DC OC
30 00 00 00
00 00 66 3C
00 00 00 00
00 00 18 18
00 00 00 00
00 00 00 00
18 30 00 00
00 00 00 00
00 00 00 00
00 00 00 00
18 00 00 00
02 06 DC 18
00 00 00 00
C6 CE DE
00 00 00
38 78 18
00 00 00
C6 06 DC
00 00 00
C6 06 06
00 00 00
lC 3C 6C
00 00 00
CO CO CO
00 00 00
60 CO CO
00 00 00
C6 06 DC
00 00 00
C6 C6 C6
00 00 00
C6 C6 C6
00 00 00
18 18 00
00 00 00
18 18 00
00 00 00
DC 18 30
00 00 00
00 00 7E
00 00 00
30 18 DC
00 00 00
C6 C6 DC
00 00 00
C6 C6 DE
00 00 00
38 6C C6
00 00 00
66 66 66
00 00 00
66 C2 CO
00 00 00
6C 66 66
00 00 00
66 62 68
00 00 00
66 62 68
00 00 00
66 C2 CO
00 00 00
C6 C6 C6
00 00 00
18 18 18
00 00 00
DC DC DC
00 00 00
66 6C 6C
00 00 00
60 60 60

115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240

DB
DB

m~:g1~~:g~g~:gg~~:ggg~:ggg~,07CH,006H ~ ~~:::~~ ~

DB
DB

ggg~:ggg~:g6gU6g~:m~:gg~~,00CH,018H

;

~~J~ ~%'

DB
DB

030H,066H,OC6H,000H,000H,000H
;
OOOH, 000H,038H,06CH, 06CH, 038H,076H, ODCH ;

BT_25 '%'
TH_26 Ie

DB
DB

ggg~:g~g~:g~g~:g~g~: g~g~: ggg~, OOOH, OOOH

DB
DB

OOOH,OOOH,OOOH,OOOH,OOOH,OOOH
;
000H,000H,00CH,01BH,030H,030H,030H,030H ;

BT 27
TH:::28 (

DB
DB

030H,018H,00CH,000H,000H,000H
,
000H,000H,030H,018H,00CH,00CH,00CH,00CH ;

BT_28 (
TH_29 )

DB
DB

00CH,018H,030H,000H,000H,000H
,
000H,000H,000H,000H,066H,03CH,OFFH,03CH ;

BT_29 )
TH_2A

DB
DB

066H, OOOH, OOOH, OOOH, OOOH, OOOH
,
000H,000H,000H,000H,018H,018H,07EH,018H ;

BT 2A
TH:::2B

DB
DB

018H,000H,000H,000H,000H,000H

DB
DB

018H,018H,018H,030H,000H,000H
,
OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OFEH, OOOH ;

DB
DB

OOOH,OOOH,OOOH,OOOH,OOOH,OOOH
,
OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH ;

BT 20 -

DB
DB

000H,018H,018H,000H,000H,000H
,
OOOH, OOOH, 002H, 006H, OOCH, 018H, 030H, 060H ;

BT 2E .

DB

OCOH, 080H, OOOH, OOOH, OOOH, OOOH

;

~~:::~~

,.

*
*

+

, BT 2B +
OOOH,OOOH,OOOH,OOOH,OOOH,OOOH,OOOH,OOOH ; TH=:2C I
BT_2C ,
TH_2D TH:::2E .
TH:::2f /

DB

000H,000H,07CH,OC6H,OCEH,ODEH,OF6H,OE6H ;

TH_30 0

DB
DB

OC6H, OC6H, 07CH, OOOH, OOOH, OOOH
,
000H,000H,018H,038H,076H,018H,018H,018H;

BT 30 0
TH:::31 1

DB
DB

018H,018H,07[H,000H,000H,000H
,
000H,000H,07CH,OC6H,006H,00CH,018H,030H;

BT 31 1
TH::322

DB
DB

060H,OC6H,OFEH,000H,000H,aOOH
,
000H,000H,07CH,OC6H,006H,006H,03CH,006H;

BT 32 2

DB
DB

006H,OC6H,07CH,000H,000H,000H
,
OOOH, OOOH, OOCH, 01CH, 03CH, 06CH, OCCH, OfEH ;

BT 33 3
TH:::34 4

DB
DB

00CH,OOCH.01EH.000H,OOOH,OOOH
• BT 34 4
000H,OOOH,OFEH,OCOH,OCOH,OCOH,OfCH,006H ; TH:::355

DB
DB

006H,OC6H,07CH,OOOH,OOOH,OOOH
,
000H,OOOH,038H,060H,OCOH,OCOH,OFCH,OC6H;

BT 35 5
TH:::366

DB
DB

OC6H ,OC6H, 07CH, OOOH, OOOH, OOOH
,
000H,OOOH,OfEH,OC6H,006H,OOCH,018H,030H ;

BT 36 6
TH::37 7,

DB
DB

030H,030H,030H,OOOH,OOOH,OOOH
,
000H,OOOH,07CH,OC6H,OC6H,OC6H,07CH,OC6H ;

8T 37 7
TH=38 8

DB
DB

OC6H,OC6H,07CH,OOOH,OOOH,OOOH
,
OOOH, OOOH, 07CH, OC6H, OC6H, OC6H, 07EH, 006H ;

BT 38 8

DB
DB

006H, OOCH, 078H, OOOH, OOOH, OOOH
,
000H,OOOH,OOOH,018H,018H,OOOH,000H,000H;

BT 39 9
TH:::3A:

DB
DB

018H,018H,OOOH,OOOH,000H,000H
,
000H,000H,000H,018H,018H,000H,000H,000H;

BT 3A :
TH:::3B;

DB
DB

018H,018H,030H,000H,000H,000H
,
000H,000H,006H,00CH,018H,030H,060H,030H;

BT_3B ;
TH_3C <

DB
DB

018H,00CH,006H,000H,OOOH,OOOH
,
OOOH, OOOH, OOOH, OOOH, OOOH, 07EH, OOOH, OOOH ;

BT 3C <
TH:::30:

DB
DB

07EH,OOOH,OOOH,000H,OOOH,OOOH
,
000H,000H,060H,030H,018H,00CH,006H,00CH;

BT 30 :
nC3E>

DB
DB

018H,030H,060H,000H,000H,000H
,
000H,000H,07CH,OC6H,OC6H,00CH,018H,018H ;

BT 3E >
TH:::3F ?

DB

OOOH, 018H, 01 8H, OOOH, OOOH, OOOH

TH::33 3

TH:::39 9

DB

000H,000H,07CH,OC6H,OC6H,ODEH,ODEH,ODEH ;

TH_40 @

DB
DB

ODCH,OCOH,07CH,000H,000H,000H
,
000H,000H,010H,038H,06CH,OC6H,OC6H,OfEH ;

BT '10 @
TH:::41 A

DB
DB

OC6H,OC6H,OC6H,OOOH,OOOH,OOOH
,
OOOH, OOOH, OFCH, 066H, 066H, 066H, 07CH, 066H ;

ST 41 A
TH::42 B

DB
DB

066H, 066H, OFCH, OOOH, OOOH, OOOH
;
OOOH, OOOH, 03CH, 066H, OC2H, OCOH, OCOH, OCOH ;

ST 42 B
TH:::43 C

DB
DB

OC2H, 066H, 03CH, OOOH, OOOH, OOOH
,
OOOH, OOOH, OF8H, 06CH, 066H, 066H, 066H, 066H ;

BT 43 C
TH:::44 0

DB
DB

066H,06CH,OF8H,000H,000H,000H
,
OOOH, OOOH, OFEH, 066H, 062H, 068H, 078H, 068H ;

ST 44 0
TH::45 E

DB
DB

062H, 066H, OfEH, OOOH, OOOH, OOOH
,
OOOH, OOOH, OfEH, 066H, 062H, 068H, 078H,068H ;

ST 45 E
TH::46 f

DB
DB

060H,060H,OfOH,000H,000H,000H
,
000H,000H,03CH,066H,OC2H,OCOH,OCOH,ODEH;

ST 46 f
TH::47 G

OS
DB

OC6H,066H,03AH,000H,000H,OOOH
,
OOOH, OOOH, OC6H, OC6H, OC6H, OC6H, OfEH,OC6H ;

ST 47 G
TH::48, H

DB
OS

OC6H,OC6H,OC6H,OOOH,OOOH,OOOH
,
000H,000H,03CH,018H,018H,018H,018H,018H ;

BT 48 H
TH:::49 I

DB
DB

018H,018H,03CH,000H,000H,000H
,
OOOH, OOOH, 01 EH, OOCH,OOCH, OOCH, OOCH, OOCH ;

BT 49 I
TH::4A J

OS
OS

OCCH,OCCH,078H,OOOH,OOOH,OOOH
,
OOOH, OOOH, OE6H, 066H, 06CH, 06CH, 078H, 06CH ;

BT 4A J
TH:::4B K

OS
DB

06CH, 066H, OE6H, OOOH, OOOH, OOOH
,
000H,000H,OFOH,060H,060H,060H,060H,060H ;

BT 4S K
TH::4C L

IBM Enhanced Graphics Adapter 153

0~30
0~36
0~3E

0~44
0~4C
0~52
0~5A

0~60
0~68

0~6E
0~76

0~7C
0~84
0~8A
0~92
0~98
O~AO
0~A6
O~AE

0~B4
O~BC

0~C2
O~CA
O~DO
0~D8

O~DE

04E6
O~EC
0~F4
O~FA

0502
0506
0510
0516
051E
0524
052C
0532
053A
0540
0546
054E
0556
055C
0564
056A
0572
0578
0580
0586
058E
059~

059C
05A2
05AA
05BO
05B6
05BE
05C6
05CC
0504
05DA
05E2
05E8
05FO
05F6
05FE
0604
060C
0612
061A
0620
0628
062E
0636
063C
0644
064A
0652
0658
0660
0666

62
00
06
C6
00
DE
C6
00
C6
C6

66
00
C6
C6
00
CE
C6
00
C6
6C

FE 00 00 00
C6 EE FE FE

00
7C
60
00
C6
DE
00
7C
66
00
38
C6
00
18
18
00
C6
C6
00
C6
6C
00
06
FE
00
38
6C
00
3C
16
00
30
C2
00
30
30
00
38
OE
00
DC
OC
10
00
00
00
00
00

00
60
60
00
06
7C
00
6C
66
00
OC
C6
00
18
18
00
C6
C6
00
C6
38
00
06
7C
00
38
C6
00
18
16
00
60
C6
00
30
30
00
lC
06
00
OC
OC
36
00
00
00
00
00

FC 66 66 66

30
00
00
00
OC
CC
00
6C
66
00
C6
CO
00
6C
CC
00
C6
CO
00
FO
60
00
CC
CC
00
76
66
00
16
16
00
06
06
00
6C
6C
00
16
16
00
FE
06
00
66
66
00
C6
C6

30
00
00
00
7C
CC
00
66
66
00
CO
C6
00
CC
CC
00
FE
C6
00
60
60
00
CC
7C
00
66
66
00
16
16
00
06
06
00
76
66
00
16
18
00
06
06
00
66
66
00
C6
C6

00
66
66
00
CC
CC
00
76
60
00
C6
lC
00
30
30
00
CC

00
66
7C
00
CC
7C
00
66
60
00
70
C6
00
30
36
00
CC

C6 00 00 00
C6 E6 F6 FE
C6 00 00 00
38 6C C6 C6
38 00 00 00

FO 00 00 00
7C C6 C6 C6
OC OE 00 00
FC 66 66 66
E6 00 00 00
7C C6 C6 60
7C 00 00 DO
7E 7E 5A 18
3C 00 00 00
C6 C6 C6 C6
7C 00 00 00
C6 C6 C6 C6
10 00 00 00
C6 C6 C6 C6
6C 00 00 00
C6 C6 6C 38
C6 00 00 00
66 66 66 66
3C 00 00 00
FE C6 6C 18
FE 00 00 00
3C 30 30 30
3C 00 00 00
60 CO EO 70
02 00 00 00
3C OC OC OC
3C 00 00 00
6C C6 00 00
00 00 00 00
00 00 00 00
00 00 FF 00
16 00 00 00
00 00 00 00
00 00 00 76
76 00 00 00
EO 60 60 76
7C 00 00 00
00 00 00 7C
7C 00 00 00
lC OC OC 3C
76 00 00 00
00 00 00 7C
7C 00 00 00
38 6C 64 60
FO 00 00 00
00 00 00 76
DC CC 76 00
EO 60 60 6C
E6 00 00 00
18 18 00 36
3C 00 00 00
06 06 00 OE
66 66 3C 00
EO 60 60 66
E6 00 00 00
36 18 18 18
3C 00 00 00
00 00 00 EC
C6 00 00 00
00 00 00 DC
66 00 00 00
00 00 00 7C
7C 00 00 00
00 00 00 DC
60 60 FO 00
00 00 00 76
DC OC 1 E 00
00 00 00 DC
FO 00 00 00
00 00 00 7C
7C 00 00 00
10 30 30 FC
lC 00 00 00
00 00 00 CC

241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
266
269
270
271
272
273
274
275
276
277
276
279
280
261
262
263
264
285
266
267
266
269
290
291
292
293
294
295
296
297
296
299
300
301
302
303
304
305
306
307
306
309
310
311
312
313
314
315
316
317
316
319
320
321
322
323
324
325
326
327
326
329
330
331
332

DB
DB

062H,066H,OFEH,000H,000H,000H
, BT_4C L
000H,000H,OC6H,OEEH,OFEH,OFEH,OD6H,OC6H ; TH_40 M

DB
DB

OC6H,OC6H,OC6H,000H,000H,000H
, BT_40 M
000H,000H,OC6H,OE6H,OF6H,OFEH,ODEH,OCEH ; TH_4E N

DB
DB

OC6H,OC6H,OC6H,000H,000H,000H
, BT_4E N
000H,000H,038H,06CH,OC6H,OC6H,OC6H,OC6H ; TH_4f 0

333
334
335
336

337
336
339
340
341
342
343
344
345
346
347
346
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366

DB

OC6H, 06CH, 038H, OOOH, OOOH, OOOH

DB

OOOH, OOOH, OFCH, 066H, 066H, 066H, 07CH, 060H ; TH_50 P

DB
DB

060H, 060H, OFOH,OOOH, OOOH, OOOH
; BT_50 P
000H,000H,07CH,OC6H,OC6H,OC6H,OC6H,OD6H ; TH_51 Q

DB
DB

ODEH,07CH,OOCH,OOEH,OOOH,000H
OOOH, OOOH, OFCH,066H, 066H, 066H, 07CH, 06CH

BT_51 Q
TH_52 R

DB
DB

066H,066H, OE6H,000H, OOOH, OOOH
OOOH, OOOH, 07CH,OC6H, OC6H, 060H, 036H, OOCH

BT_52 R
TH_53 S

DB
DB

OC6H,OC6H,07CH,000H,000H,000H
000H,OOOH,07EH,07EH,05AH,016H,018H,018H

TH_5~ T

DB
DB

016H,016H,03CH,000H,OOOH,000H
OOOH, OOOH, OC6H, OC6H, OC6H, OC6H, OC6H, OC6H

BT_5~ T
TH_55 U

DB
DB

OC6H,OC6H,07CH,000H,000H,000H
OOOH, OOOH, OC6H, OC6H, OC6H, OC6H, OC6H, OC6H

BT_55 U
TH_56 Y

DB
DB

06CH,036H,010H,000H,000H,000H
OOOH,OOOH, OC6H, OC6H, OC6H, OC6H, OD6H, OD6H

BT_56 Y
TH_57 W

DB
DB

OFEH,07CH,06CH,OOOH,000H,000H
OOOH, OOOH, OC6H, OC6H, 06CH, 038H, 038H, 036H

BT_57 W
TH_58 X

DB
DB

06CH,OC6H,OC6H,000H,000H,000H
, BT_58 X
000H,000H,066H,066H,066H,066H,03CH,016H ; TH_59 Y

DB
DB

018H,018H,03CH,OOOH,OOOH,OOOH
OODH, OOOH, OFEH, DC6H, 06CH', 018H, 030H, 060H

BT_59 Y

DB
DB

OC2H,OC6H,OFEH,DOOH,000H,000H
000H,000H,03CH,030H,030H,030H,030H,030H

BT_5A Z
TH_58 I

DB
DB

030H,030H,03CH,000H,000H,000H
OOOH, OOOH, 060H, OCOH, OEOH, 070H, 036H, 01 CH

BT_58
TH_5C

DB
DB

OOEH, 006H, 002H, OOOH, OOOH, OOOH
OOOH, OOOH, 03CH, OOCH, OOCH, OOCH, OOCH, OOCH

BT 5C
TH::5D J

DB
DB

00CH,00CH,03CH,000H,000H,000H
01 OH, 036H, 06CH, OC6H, OOOH, OOOH, OOOH, OOOH

BT_50 J
TH_5E

DB
DB

OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH

BT 5E
TH::5 F

DB

OOOH, OOOH, OOOH, OOOH, 0 FFH, OOOH

BT _5 F

DB

030H,030H,018H,000H,000H,000H,000H,000H ; TH_60 '

DB
DB

OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
; BT_60 '
OOOH, OOOH, OOOH, OOOH, OOOH, 078H, OOCH, 07CH ; TH_61 LOWER_CASE A

DB
DB

OCCH, OCCH, 076H, OOOH, OOOH, OOOH
000H,000H,OEOH,060H,060H,078H,06CH,066H

BT_61 LOWER_CASE A
TH_62 LoCo 8

DB
DB

066H,066H,07CH,000H,000H,000H
OOOH, OOOH, OOOH, OOOH, OOOH, 07CH, OC6H, OCOH

BT_62 LoCo 8
TH_63 Lo Co C

DB
DB

OCOH,OC6H,07CH,000H,000H,000H
OOOH, OOOH, 01CH, OOCH, OOCH, 03CH,06CH, OCCH

BT_63 LoCo C
TH_6~ Lo Co 0

DB
DB

OCCH,OCCH,076H,OOOH,OOOH,OOOH
000H,000H,000H,000H,000H,07CH,OC6H,OFEH

BT_6~ LoCo
TH_65 LoCo

DB
DB

OCOH,OC6H,07CH,000H,000H,000H
OOOH, OOOH, 038H, 06CH, 064H, 060H, OFOH, 060H

BT_65 LoCo
TH_66 Lo Co

DB
DB

060H,060H,OFOH,000H,000H,000H
OOOH, OOOH, OOOH, OOOH, OOOH, 076H, OCCH, OCCH

BT_66 LoCo F
TH_64' LoCo C

DB
DB

OCCH,07CH,00CH,OCCH,078H,000H
000H,000H,OEOH,060H,060H,06CH,076H,066H

BT_67 LoCo C
TH_68 LoCo H

DB
DB

066H,066H,OE6H,000H,000H,000H
000H,000H,018H,018H,000H,038H,018H,018H

BT_68 LoCo H
TH_69 LoCo I

DB
DB

018H,016H,03CH,000H,000H,000H
OOOH, OOOH, 006H, 006H, OOOH, OOEH, 006H, 006H

BT_69 LoCo I
TH_6A Lo Co J

DB
DB

006H,006H,066H,066H,03CH,000H
OOOH, OOOH, OEOH, 060H, 060H, 066H, 06CH, 078H

BT_6A LoCo J
TH_68 Lo C K

DB
DB

06CH,066H,OE6H,000H,000H,000H
000H,000H,038H,018H,018H,018H,018H,018H

BT_68 LoCo
TH_6C LoCo

DB
DB

018H,018H,03CH,000H,000H,000H
000H,000H,000H,000H,000H,OECH,OFEH,OD6H

BT_6C LoCo L
TH_60 LoCo M

DB
DB

OD6H,OD6H,OC6H,000H,000H,000H
OOOH, OOOH, OOOH, OOOH, OOOH, ODCH, 066H, 066H

BT_60 LoCo M
TH_6E Lo CoN

DB
DB

066H,066H,066H,000H,000H,000H
, BT_6E LoCo N
000H,000H,000H,000H,000H,07CH,OC6H,OC6H ; TH_6F LoCo 0

DB

OC6H, OC6H, 07CH, OOOH, OOOH, OOOH

DB

000H,000H,OOOH,000H,000H,ODCH,066H,066H ;

TH_7D LCo

DB
DB

066H,07CH,060H,060H,OFOH,000H
000H,000H,000H,000H,000H,076H,OCCH,OCCH

BT_70 LoCo P
TH_71 LoCo Q

DB
DB

OCCH,07CH,00CH,00CH,01EH,000H
000H,000H,000H,000H,000H,00CH,076H,066H

BT_71 LoCo Q
TH_72 LoCo R

DB
DB

060H,060H,OFOH,000H,000H,000H
000H,000H,000H,000H,000H,07CH,OC6H,070H

BT_72 LoCo
TH_73 LoCo

DB
DB

01CH,OC6H,07CH,000H,000H,000H
000H,OOOH,010H,030H,030H,OFCH,030H,030H

BT_73 LoCo
TH_7~ LoCo

DB
DB

030H,036H,01CH,000H,000H,000H
OOOH,OOOH,OOOH,OOOH,OOOH,OCCH,OCCH,OCCH

BT_7~ LoCo T
TH_75 LoCo U

154 IBM Enhanced Graphics Adapter

BT_53 S

TH_5A Z

I

0

K
L

P

066E
0674
067C
0682
068A
0690
0698
069E
06A6
06AC
06B4
06BA
06C2
06C8
06DO
06D6
06DE
06E4
06EC
06F2
06FA
0700
0708
070E
0716
071C
0724
072A
0732
0738
0740
0746
074E
0754
075C
0762
076A
0770
0778
077E
0786
078C
0794
079A
07A2
07A8
07BO
07B6
07BE
07C4
07CC
0702
070A
07EO
07E8
07EE
07F6
07FC
0804
080A
0812
0818
0820
0826
082E
0834
083C
0842
084A
0850
0858
085E
0866
086C
0874
087A
0882
0888
0890
0896
089E
08A4
08AC

CC
00
66
66
00
C6
D6
00
6C
38
00
C6
C6
00
CC
30
00
70
18
00
00
18
00
OE
18
00
00
00

CC
00
66
3C
00
D6
FE
00
38
6C
00
C6
7E
00
18
66
00
18
18
00
18
18
00
18
18
00
00
00
no 00
6C C6
C6 FE
00 00
co C2
66 3C
00 00
CC CC
CC CC
00 DC
C6 FE
CO C6
00 10
OC 7C
CC CC
00 00
OC 7C
CC CC
00 60
OC 7C
CC CC
00 38
OC 7C
CC CC
00 00
60 66
3C OC
00 10
C6 FE
co C6
00 00
C6 FE
co C6
00 60
C6 FE
CO C6
00 00
18 18
18 18
00 18
18 18
18 18
00 60
18 18
18 18
00 C6
C6 C6
FE C6
38 6C
C6 C6
FE C6
18
60
60
00
36
D8
00
FE
CC
00
C6
C6
00
C6
C6
00
C6
C6
00
CC
CC
00
CC
CC
00
C6
C6
00
C6
C6
00
C6
C6
00
60
3C
00
60
60
00
7E
7E
00
CC
CC

30
7C
66
00
7E
DB
00
CC
CC
10
C6
C6
00
C6
C6
60
C6
C6
30
CC
CC
60
CC
CC
00
C6
7E
C6
C6
6C
C6
C6
C6
18
66
18
38
60
E6
00
18
18
F8
DE
CC

76 00 00 00
00 00 00 66
18 00 00 00
00 00 00 C6
6C 00 00 00
00 00 00 C6
C6 00 00 00
00 00 00 C6
06 DC F8 00
00 00 00 FE
FE 00 00 00
OE 18 18 18
DE 00 00 00
18 18 18 18
18 00 00 00
70 18 18 18
70 00 00 00
76 DC 00 00
00 00 00 00
00 00 10 38
00 00 00 00
3C 66 C2

co

OC 06 7C 00
CC CC 00 CC
76 00 00 00
18 30 00 7C
7C 00 00 00
38 6C 00 78
76 00 00 00
CC CC 00 78
76 00 00 00
30 18 00 78
76 00 00 00
6C 38 00 78
76 00 00 00
00 00 3C 66
06 3C 00 00
38 6C 00 7C
7C 00 00 00
CC CC 00 7C
7C 00 00 00
30 18 00 7C
7C 00 00 00
66 66 00 38
3C 00 00 00
3C 66 00 38
3C 00 00 00
30 18 00 38
3C 00 00 00
C6 10 3B 6C
C6 00 00 00
38 00 38 6C
C6 00 00 00
60 00 FE 66
FE 00 00 00
00 00 CC 76
6E 00 00 00
3E 6C CC CC
CE 00 00 00
38 6C 00 7C
7C 00 00 00
C6 C6 00 7C
7C 00 00 00
30 18 00 7C
7C 00 00 00
78 CC 00 CC
76 00 00 00
30 18 00 CC
76 00 00 00
C6 C6 00 C6
06 OC 78 00
C6 38 6C C6
38 00 00 00
C6 00 C6 C6
7C 00 00 00
18 3C 66 60
18 00 00 00
6C 64 60 FO
FC 00 00 00
66 66 3C 18
18 00 00 00
CC CC F8 C4
C6 00 00 00

367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
,,03
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492

DB
DB

OCCH,OCCH,076H,OOOH,OOOH,OOOH
, BT_75 L.C. U
000H,OOOH,OOOH,OOOH,OOOH,066H,066H,066H ; TH_76 L.C. V
BT_76 L.C. V
TH_77 L.C. W

DB
DB

066H.,03CH,018H,OOOH,OOOH,OOOH
;
000H,OOOH,OOOH,OOOH,OOOH,OC6H,OC6H,OD6H ;

DB
DB

OD6H,OFEH,06CH,OOOH,OOOH,OOOH
, BT_77 L.C. W
OOOH,000H,OOOH,OOOH,OOOH,OC6H,06CH,038H ; TH_78 L.C. X

DB
DB

038H,06CH,OC6H,OOOH,OOOH,OOOH
; BT_78 L.C. X
000H,OOOH,OOOH,OOOH,OOOH,OC6H,OC6H,OC6H ; TH_79 L.C. Y

DB
DB

OC6H.07EH,006H,OOCH,Of8H,OOOH
,
OOOH,OOOH,OOOH,OOOH,000H,OFEH,OCCH,018H ;

8T_79 L.C. v
TH_7A L.C. Z

DB
DB

030H,066H,OFEH,OOOH,OOOH,000H
,
OOOH,000H,OOEH,018H,018H,018H,OrDH,018H ;

BT_7A L.C. Z
TH_7B L BRAK

DB
DB

018H,018H,OOEH,OOOH,OOOH,OOOH
,
OOOH,OOOH,018H,018H,018H,018H,000H,018H ;

BT_7B L BRAK
TH_7C I

DB
DB

018H,018H,018H,OOOH,OOOH,000H
,
OOOH,OOOH,070H,018H,018H,018H,OOEH,018H ;

BT_7C I
TH_70 R BRAK

DB
DB

018H,018H,070H,OOOH,000H,OOOH
,
OOOH, OOOH, 076H, OOCH, OOOH, OOOH, OOOH, OOOH ;

BT_70 R BRAK
TH_7E TILDE

DB
DB

OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
; BT_7E TILDE
OOOH, OOOH,OOOH, OOOH, 010H, 038H, 06CH, OC6H ; TH_7F DELTA

DB

OC6H, OFEH, OOOH, OOOH, OOOH, OOOH

DB

OOOH, 000H,03CH, 066H, OC2H, OCOH,OCOH, OC2H ;

TH_80

DB
DB

066H,03CH,OOCH,006H,07CH,OOOH
,
OOOH, OOOH, OCCH, OCCH, OOOH, OCCH, OCCH,OCCH ;

BT_80
TH_81

DB
DB

OCCH,OCCH,076H,OOOH,OOOH,OOOH
,
000H,OOCH,018H,030H,OOOH,07CH,OC6H,OFEH ;

BT_81
TH_82

DB
DB

OCOH,OC6H,07CH,OOOH,OOOH,OOOH
,
000H,010H,038H,06CH,OOOH,078H,OOCH,07CH ;

BT_82
TH_83

DB
DB

OCCH,OCCH,076H,OOOH,OOOH,OOOH
, BT_83
OOOH, OOOH, OCCH, OCCH, OOOH, 078H, OOCH, 07CH ; TH_84

DB
DB

OCCH,OCCH,076H,OOOH,OOOH,OOOH
, BT_84
000H,060H,030H,018H,OOOH,078H,OOCH,07CH ; TH_85

DB
DB

OCCH,OCCH,076H,OOOH,OOOH,OOOH
, BT 85
000H,038H,06CH,038H,OOOH,078H,OOCH,07CH ; TH:86

DB
DB

OCCH,OCCH,076H,OOOH,OOOH,OOOH

OOOH. OOOH. OOOH, OOOH, 03CH, 066H, 060H, 066H ;

TH:::::67

DB
DB

03CH,OOCH,006H,03CH,OOOH,OOOH
,
000H,010H,038H,06CH,OOOH,07CH,OC6H,OFEH ;

BT 87
TH:88

DB
DB

OCOH, OC6H, 07CH, OOOH, OOOH, OOOH
,
OOOH, OOOH, OCCH, OCCH, OOOH, 07CH, OC6H, OFEH ;

BT 88
TH:89

DB
DB

OCOH, OC6H, 07CH, OOOH, OOOH, OOOH
,
000H,060H,030H,018H,OOOH,07CH,OC6H,OFEH ;

BT _89
TH_BA

DB
DB

OCOH,OC6H,C7CH,OOOH,OOOH,OOOH
,
000H,OOOH,066H,066H,OOOH,038H,018H,018H ;

BT_8A
TH_8B

DB
DB

018H,018H,03CH,OOOH,OOOH,OOOH
, BT_8B
000H,018H,03CH,066H,OOOH,038H,018H,018H ; TH_8C

DB
DB

018H,018H,03CH,OOOH,OOOH,000H
, BT_8C
000H,060H,030H,018H,OOOH,038H,018H,018H ; TH_80

DB
DB

018H,018H,03CH,OOOH,OOOH,000H
, BT_80
000H,OC6H,OC6H,010H,038H,06CH,OC6H,OC6H ; TH_8E

,

BT 86

DB
DB

OFEH,OC6H, OC6H, OOOH, OOOH, OOOH
,
038H,06CH,038H,OOOH,038H,06CH,OC6H,OC6H ;

DB

oFEH, OC6H, OC6H, OOOH, OOOH, OOOH

BT_8E
TH_8F

DB

018H, 030H, 060H, OOOH, OFEH, 066H, 060H, 07CH ;

TH_90

DB
DB

060H, 066H, OFEH, OOOH, OOOH, OOOH
,
OOOH, OOOH, OOOH, OOOH, OCCH, 076H, 036H,07EH ;

BT_90
TH_91

DB
DB

008H, 008H, 06EH, OOOH, OOOH, OOOH
,
OOOH, OOOH, 03EH, 06CH, OCCH, OCCH, OFEH, OCCH ;

BT 91
TH:92

DB
DB

OCCH,OCCH,OCEH,OOOH,OOOH,OOOH
,
OOOH, 010H,038H,06CH, OOOH, 07CH, OC6H, OC6H ;

BT 92
TH:93

DB
DB

OC6H,OC6H,07CH,OOOH,OOOH,OOOH
,
OOOH, 000H.OC6H, OC6H, OOOH, 07CH, OC6H, OC6H ;

BT 93
TH:94

DB
DB

OC6H,OC6H,07CH,OOOH,OOOH,OOOH
,
000H,060H,030H,018H,OOOH,07CH,OC6H,OC6H ;

BT 94
TH:95

DB
DB

OC6H,OC6H,07CH,OOOH,OCOH,OOOH
,
OOOH, 030H,078H, OCCH, OOOH, OCCH, OCCH, OCCH ;

BT 95
TH:96

DB
DB

OCCH,OCCH,076H,OOOH,OOOH,OOOH
,
000H,060H,030H,018H,OOOH,OCCH,OCCH,OCCH ;

BT 96
TH:97

DB
DB

OCCH,OCCH,076H,OOOH,OOOH,OOOH
, BT 97
000H,OOOH,OC6H,OC6H,OOOH,OC6H,OC6H,OC6H; TH:98

DB
DB

OC6H,07EH,006H,OOCH,078H,OOOH
,
000H,OC6H,OC6H,038H,06CH,OC6H,OC6H,OC6H ;

BT 96
TH:99

DB
DB

OC6H,06CH,038H,OOOH,OOOH,OOOH
,
000H,OC6H,OC6H,OOOH,OC6H,OC6H,OC6H,OC6H ;

BT 99
TH:9A

DB
DB

0C6H,OC6H,07CH,OOOH,OOOH,OOOH
,
000H,018H,018H,03CH,066H,060H,060H,066H ;

BT 9A
TH:9B

DB
DB

03CH,018H,018H,OOOH,OOOH,OOOH
, BT 9B
OOOH, 038H, 06CH, 064H, 060H, 0 FOH, 060H, 060H ; TH:9C

DB
DB

060H,OE6H,OFCH,OOOH,OOOH,OOOH
,
000H,OOOH,066H,066H,03CH,018H,07EH,018H ;

BT 9C
TH:90

DB
DB

07EH,018H,018H,OOOH,OOOH,OOOH
000H,OF8H, OCCH, OCCH, OF8H, OC4H,OCCH, OOEH

BT 90
TH:9E

DB

OCCH, OCCH, OC6H, OOOH, OOOH, OOOH

BT_9E

IBM Enhanced Graphics Adapter 155

08B2
08BA
08CO
08C8
08CE
0806
08DC
08E4
08EA
08F2
08F8
0900
0906
090E
0914
091C
0922
092A
0930
0938
093E
0946
094C
0954
095A
0962
0968
0970
0976
097E
0984
098C
0992
099A
09AO
09A8
09AE
09B6
09BC
D9C4
09CA
0902
0908
09EO
09E6
09EE
09F4
09FC
OA02
DADA
OA10
OA18
DAlE
OA26
OA2C
OA34
OA3A
OA42
OA48
OA50
DA56
OA5E
OA64
OA6C
OA72
OA7A
OA80
OAS8
OA8E
OA96
OA9C
OAA4
OAAA
OAB2
OAB8
OACO
OAC6
DACE
OAD4
OADC
OAE2
OAEA

00 OE lB 18 18 18
7E 18
18 18 18 08 70 00
00
DC
CC
00
18
18
00
C6
C6
00
CC
CC
00
66
66
76
FE
CE
00
7E
00
00
7C
00
00
30
C6
00
FE
CO
00
FE
06
00
30
DC
00
30
CE
00
18
3C
00
08
36
00
36
08

18
7C
CC
OC
18
18
18
C6
C6
18
CC
CC
00
66
66
DC
DE
C6
3C
00
00
38
00
00
00
60
C6
00
CO
CO
00
06
06
CO
60
86
CO
66
9E
00
3C
3C
00
6C
00
00
6C
00

11
11
11
55
55
55
DO
DO
DO
18
18
18
18
18
18
18
18
18
36
36
36
00
00
36
00
18
18
36
06
36
36
36
36
00
06
36
36
06
00
36
36
00
18
18
00
00
00
18

44
44
44
AA
AA
AA
77
77
77
18
18
18
18
F8
18
18
F8
18
36
F6
36
00
FE
36
00
F8
18
36
f6
36
36
36
36
00
F6
36
36
FE
00
36
FE
00
18
F8
00
00
F8
18

18
18
00
18
18
00
00
00
18
18
18
18
00
00
00
18
18
18
18
18
18
36
36
36

18
1F
00
18
ff
00
00
ff
18
18
If
18
00
ff
00
18
ff
18
18
1f
18
36
37
36

30 60 00 78
76 00 00 00
18 30 00 38
3C 00 00 00
30 60 00 7C
7C 00 00 00
30 60 00 CC
76 00 00 00
76 DC 00 DC
66 00 00 00
00 C6 E6 F6
C6 00 00 00
6C 6C 3E 00
00 00 00 00
6C 6C 38 00
00 00 00 00
30 30 00 30
7C 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
C6 CC 08

co

DC 18 3E 00
CO C6 CC 08
3 E 06 06 00
18 18 00 18
18 00 00 00
00 00 36 6C
00 00 00 00
00 00 08 6C
00 00 00 00
11 44 11 44
11 44 11 44
55 AA 55 AA
55 AA 55 AA
DO 77 DO 77
DO TI DO 77
18 18 18 18
18 18 18. 18
18 18 18 18
18 18 18 18
18 18 18 F8
18 18 18 18
36 36 36 36
36 36 36 36
00 00 00 00
36 36 36 36
00 00 00 F8
18 18 18 18
36 36 36 F6
36 36 36 36
36 36 36 36
36 36 36 36
00 00 00 FE
36 36 36 36
36 36 36 f6
00 00 00 00
36 36 36 36
00 00 00 00
18 18 18 F8
00 00 00 00
00 00 00 00
18 18 18 18
18 18 18 18
00 00 00 00
18 18 18 18
00 00 00 00
00 00 00 00
18 18 18 18
18 18 18 18
18 18 18 18
00 00 00 00
00 00 00 00
18 18 18 18
18 18 18 18
18 18 18 1f
18 18 18 18
36 36 36 36
36 36 36 36

493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618

DB

000H,00EH,01BH,018H,018H,018H,07EH,018H ; TH_9F

DB

018H, 018H, 018H, OD8H, 070H, OOOH

08

OOOH, 018H, 030H, 060H, OOOH, 078H, OOCH,07GH ; TH_AO

DB
DB

OCCH,OCCH,076H,000H,000H,000H
; BT_AO
OODH,00CH,018H,030H,000H,038H,018H,018H ; TH_Al

DB
DB

018H, 018H, 03CH, OOOH, OOOH, OOOH
; BT_Al
OOOH,018H,030H,060H,000H,07CH,OC6H,OC6H ; TH_A2

DB
08

OC6H,OC6H,07CH,000H,000H,000H
; BT_A2
OOOH,018H,030H,060H,OOOH,OCCH,OCCH,OCCH ; TH_A3

DB
DB

OCCH, OCCH, 076H, OOOH, OOOH, OOOH
; BT_A3
OOOH, OOOH, 076H,ODCH, OOOH, ODCH, 066H,066H ; TH_A4

DB
DB

D66H, 066H, 066H, OOOH, OOOH, OOOH
, BT _A4
076H,ODCH,000H,OC6H,OE6H,Of6H,OFEH,ODEH ; TH_A5

DB
DB

OCEH,OC6H,OC6H,000H,000H,000H
, BT_A5
OOOH, 03CH, 06CH, 06CH, 03EH, OOOH, 07EH, OOOH ; TH_A6

DB
DB

OOOH,OOOH,OOOH,OOOH,OOOH,OOOH
, BT_A6
OOOH,038H,06CH,06CH,038H,000H,07CH,000H ; TH_A7

DB
DB

OOOH,OOOH,OOOH,OOUH,OOOH,IiOOH
;
OOOH,OOOH, 030H, 030H, OOOH,030H,030H, 060H ;

DB
DB

OC6H,OC6H,07CH,000H,000H,000H
; BT_AS
OOOH, OOOH,OOOH, OOOH, OOOH, OOOH, OfEH,OCOH ; TH_A9

BT_A7
TH_AS

DB
DB

OCOH,OCOH,OOOH,OOOH,OOOH,OOOH
, BT_A9
000H,000H,000H·,000H,000H,000H,OfEH,006H; TH_AA

DB
DB

006H, 006H, OOOH, OOUH, OOOH, OOOH
, BT_AA
OOOH, OCOH,OCOH, OC6H, OCCH, OD8H, 030H,060H ; TH_AB

DB
DB

ODCH,086H,00CH,018H,03EH,000H

OOOH, OCOH, OCOH, OC6H, aCCH, OD8H, 030H, 066H ;

TH_AC

DB
DB

OCEH, 09EH, 03 EH, 006H, 006H, OOOH
,
000H,000H,018H,018H,000H,018H,018H,03CH ;

, BT_AB
BT AC
TH::AD

DB
DB

03CH,03CH,018H,000H,000H,000H
, BT AD
OOOH, OOOH, OOOH, OOOH, 036H, 06CH, OD8H, 06CH ; TH::AE

DB
DB

036H, OOOH, OOOH, OOOH, OOOH, OOOH
, BT _AE
OOOH, OOOH, OOOH, OOOH, OD8H, 06CH, 036H, 06CH ; TH_Af

DB

008H, OOOH, OOOH, OOOH, OOOH, OOOH

DB

011H,044H,011H,044H,011H,044H,011H,044H; TH_BO

DB
DB

011H,044H,011H,044H,011H,044H
, BT_BO
055H,OAAH,055H,OAAH,055H,OAAH,055H,OAAH; TH_Bl

DB
DB

055H,OAAH,055H,OAAH,055H,OAAH
, BT B1
ODDH,077H,ODDH,077H,ODDH,077H,ODDH,077H ; TH::82

DB
DB

ODOH, 077H, OODH, 077H, ODDH, 077H
, BT B2
018H,018H,018H,018H,018H,018H,018H,018H; TH::B3

DB
DB

018H,018H,018H,018H,018H,018H
,
018H,018H,018H,018H,018H,018H,018H,Of8H ;

BT_B3
TH_B4

DB
DB

018H,018H,018H,018H,018H,018H
,
018H, 018H, 018H,018H, 018H, Of8H, 018H, OF8H ;

BT_B4
TH_B5

OB
DB

018H,018H,018H,018H,018H,018H
, BT_B5
036H, 036H,036H, 036H, 036H, 036H, 036H, OF6H ; TH_B6

DB
DB

036H, 036H, 036H, 036H, 036H,036H
,
OOOH,OOOH,OOOH,OOOH,OOOH,OOOH,OOOH,OFEH ;

DB
DB

036H, 036H, 036H, 036H, 036H, 036H
, BT _B7
OOOH,OOOH,OOOH, OOOH, OOOH, OF8H, 018H, OF8H ; TH:..B8

BT_B6
TH_B7

DB
DB

018H,018H,018H,018H,018H,018H
,
036H, 036H, 036H,036H, 036H, Of6H,006H, OF6H ;

BT_B8
TH_B9

DB
DB

036H, 036H, 036H, 036H, 036H, 036H
,
036H, 036H, 036H, 036H, 036H, 036H, 036H, 036H ;

BT B9
TH:::BA

DB
DB

036H, 036H, 036H,036H, 036H, 036H
,
OOOH, OOOH, OOOH,OOOH, OOOH, OFEH, 006H, Of6H ;

BT BA
TH:::BB

DB
OB

036H, 036H, 036H, 036H, 036H, 036H
,
036H, 036H, 036H, 036H, 036H, Of6H, 006H, OfEH ;

BT BB
TH:::BC
BT BC
TH:::BD

DB
DB

OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
,
036H,036H,036H,036H,036H,036H,036H,OfEH ;

DB
DB

OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
,
018H, 018H, 018H, 018H, 018H, Of8H, 018H, Of8H ;

BT BO
TH:::BE

DB
DB

OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
,
OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, Of8H ;

BT BE
TH:::Bf

°

DB

018H, 018H,

DB

018H,018H,018H,018H,018H,018H,018H,OlfH ;

18H, 018H, 018H, 018H
TH_CO

DB
DB

OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
,
018H,018H,018H,018H,018H,018H,018H,OffH ;

BT CO
TH:::Cl

DB
DB

OOOH,OOOH,OOOH,OOOH,OOOH,OOOH

DB
DB

018H,018H,018H,018H,018H,018H
, BT C2
018H,018H,018H,018H,018H,018H,018H,01fH; TH:::C3

DB
DB

018H,018H,018H,018H,018H,018H
,
OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, 000 H., OF fH ;

BT C3
TH:::C4

DB
DB

OOOH, OOOH, OOOH ,OOOH, OOOH, OOOH
,
018H,018H,018H,018H,018H,018H,018H,OFfH ;

8T C4
TH:::C5

DB
DB

018H,018H,018H,018H,018H,018H
,
018H,018H,018H,018H,018H,01FH,018H,OlfH ;

8T C5
TH:::C6

DB
DB

018H,018H,018H,018H,018H,018H
,
036H, 036H, 036H, 036H, 036H, 036H, 036H, 037H ;

BT C6
TH:::C7

DB

036H, 036H, 036H, 036H, 036H, 036H

, BT C1
OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OFFH ; TH:C2

156 IBM Enhanced Graphics Adapter

OAFO
OAF8
OAf[
OB06
OBOC
OB14
OBIA
OB22
OB28
OB30
OB36
OB3E
OBli4
OBliC
OB52
OB5A
OB60
OB68
OB6E
OB76
OB7C
OB84
OB8A
OB92
OB98
OBAO
OBM
DBA[
OBB4
OBBC
OBC?
OBCA
OBDO
OBD8
OBOE
OBE6
OBEC
OBF4
OBFA
OC02
OC08
OC10
OC16
OClE
OC24
OC2C
OC32
OC3A
OC40
OC48
OCliE
OC56
OC5C
OC64
OC6A
OC72
OC78
OC80
OC86

36
30
00
00
30
36
36
00
00
00
00
36
36
30
36
00
00
00
36
00
36
18
00
00

36
3F
00
00
37
36
36
FF
00
00

36
36
00
00
00
18
00
00
36
36
36
00
18
18
00
00
18
18
00
00
36
36
36
36
18
18
18
18
18
00
00
00
18
FF
FF
FF
00
00
FF
FO
FO
FO
OF
OF
OF
FF
FF
00

36
FF
00
00
FF
18
00
FF
36
36
3F
00
18
1F
00
00
1F
18
00
3F
36
36
FF
36
18
FF
18
18
F8
00
00
1F
18
FF
FF
FF
00
FF
FF
FO
FO
FO
OF
OF
OF
FF

00
DC
08
00
FC
C6
00
CO
CO
00
6C
6C
00
18
60
00

00 00 00 00 76

08
OC8E
OC94
OC9C
OCA2
OCAA
OCBO
OCB8
OCBE
OCC6
OCCC
OCD4
OCDA
OCE2
OCE8
OCFO
OCF6
OCFE
0004
OOOC
0012
001A
0020
0028

36 36 36 37
00 00 00 00
00 00 00 3 F
36 36 36 36
36 36 36 F7
00 00 00 00
00 00 00 FF

F7
36
36
37
36
00
FF
00
36
F7
36
18
FF
00

36 36 36 36
36 36 36 37
36 36 36 36
00 00 00 FF
00 00 00 00
36 36 36 F7
36 36 36 36
18 18 18 FF
00 00 00 00
36 36 36 36
00 00 00 00
00 00 00 FF
18 18 18 18
00 00 00 00
36 36 36 36
36 36 36 36
00 00 00 00
18 18 18 1F
00 00 00 00
00 00 00 1F
18 18 18 18
00 00 00 00

DB

036H,036H,036H,036H,036H,037H,030H,03FH ;

DB
DB

OOOH,OOOH,OOOH,OOOH,OOOH,OOOH
, BT_C8
000H,OOOH,OOOH,OOOH,OOOH,03FH,030H,037H ; TH_C9

DB
DB

036H,036H,036H,036H,036H,036H
,
036H, 036H, 036H, 036H, 036H, OF7H, OOOH, OFFH ;

627

DB
DB

OOOH,OOOH,OOOH,OOOH,OOOH,OOOH
, BT CA
OOOH, OOOH,OOOH,OOOH, OOOH, OFFH, OOOH, OF7H ; TH::CB

628
629
630
631
632
633
63li
635
636

637
638
639
640
641
642
643
64li
645
646
647
648
649
650
651
652
653
654
655

656
657
658
659
660
661

662
663
664

TH_C8

BT_C9
TH_CA

DB
DB

036H,036H,036H,036H,036H,036H
, BT_CB
036H,036H,036H,036H,036H,037H,030H,037H ; TH_CC

DB
DB

036H,036H,036H,036H,036H,036H
,
OOOH,OOOH,OOOH,OOOH,OOOH,OFFH,OOOH,OFFH ;

BT_CC
TH_CO

DB
DB

OOOH,OOOH,OOOH,OOOH,OOOH,OOOH
,
036H,036H,036H,036H,036H,OF7H,OOOH,0F7H ;

BT_CO
TH_CE

DB
DB

036H, 036H, 036H,036H, 036H, 036H
,
018H, 018H, 018H, 018~, 018H, OFFH,OOOH, OFFH ;

BT_CE
TH_CF

DB

OOOH, OOOH, OOOH, OOOH, OOOH, OOOH

DB

036H,036H,036H,036H,036H,036H,036H,OFFH; TH_OO

DB
DB

OOOH,OOOH,OOOH,OOOH,OOOH"OOOH
, BT_OO
OOOH, OOOH,OOOH, OOOH,OOOH, OFFH, OOOH, OFFH ; TH_Ol

DB
DB

018H,018H,018H,018H,018H,018H
, BT_Ol
OOOH, OOOH, OOOH, OOOH,OOOH, OOOH, OOOH, OFFH ; TH_D2

DB
DB

036H,036H,036H,036H,036H,036H
, BT_D2
036H, 036H, 036H', D36H, 036H, 036H, 036H, 03 FH ; TH_03

DB
DB

OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
, BT _03
018H,018H,018H,018H,018H,01FH,018H,01FH ; TH_D4

DB
DB

OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
, BT_Dli
000H,OOOH,OOOH,OOOH,OOOH,OIFH,018H,01FH ; TH_05

DB
DB

018H,018H,018H,018H,018H,018H
, BT 05
OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, 03FH ; TH::D6
036H, 036H, 036H, 036H, 036H, 036H
, BT 06
036H, 036H, 036H, 036H, 036H, 036H, 036H, OFFH ; TH::D7

36 36 36 36
36 36 36 36

665

DB
DB

36 36 36 36
18 18 18 FF

666
667
668

DB
DB

036H, 036H, 036H, 036H, 036H, 036H
, BT 07
018H,018H,018H,018H,018H,OFFH,018H,OFFH ; TH::D8

DB
DB

018H,018H,018H,018H,018H,018H
, BT 08
018H,018H,018H,018H,018H,018H,018H,OF8H ; TH::D9

DB
DB

OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
, BT 09
OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, 01 FH ; TH::DA

DB
DB

018H,018H,018H,018H,018H,018H
,
OFFH, OFFH, OF FH, OFFH, OFFH, OF FH, OF FH, OFFH ;

678
679
680
681

DB
DB

OFFH,OFFH,OFFH,OFFH,OFFH,OFFH
, BT DB
OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OFFH ; TH::OC

682

DB
DB

OFFH,OFFH,OFFH,OFFH,OFFH,OFFH
, BT DC
OFOH, OFOH, OFOH, OFOH,OFOH, OFOH, OFOH, OFOH ; TH::DD

DB
DB

OFOH,OFOH,OFOH,OFOH,OFOH,OFOH
, BT DO
OOFH# OOFH, OOFH, OOFH, OOFH, OOFH, OOFH, OOFH ; TH:OE

DB
DB

OOFH,OOFH,OOFH,OOFH,OOFH,OOFH
, BT DE
OFFH, OFFH, OFFH, OFFH, OFFH, OFFH, OFFH, OOOH ; TH::OF

DB

OOOH, OOOH, OOOH, OOOH, OOOH, OOOH

DB

OOOH, OOOH, OOOH,OOOH, OOOH, 076H, OOCH, OD8H ;

DB
DB

008H,ODCH,076H,OOOH,OOOH,OOOH
, BT_EO
OOOH, OOOH,OOOH, 000H,07CH, OC6H, OFCH, OC6H ; TH_El

DB
DB

OC6H, OFCH, OCOH, OCOH, OliOH, OOOH
,
OOOH, OOOH, OFEH, OC6H, OC6H, OCOH, OCOH, OCOH ;

BT El
TH::E2

DB
DB

OCOH, OCOH, OCOH, OOOH, OOOH, OOOH
,
OOOH, OOOH, OOOH, OOOH, OFEH, 06CH, 06CH, 06CH ;

BT_E2
TH_E3

DB
DB

06CH,06CH,06CH,OOOH,OOOH,OOOH
,
000H,OOOH,OFEH,OC6H,060H,030H,018H,030H ;

BT E3
TH::Eli

706
707
708
709

DB
DB

060H,OC6H,OFEH,OOOH,OOOH,OOOH
, BT Eli
OOOH, OOOH, OOOH, OOOH, OOOH, 07EH, OD8H, OD8H ; TH::E5

00 00 00
00 66 66

710
711

DB
DB

OD8H,008H,070H,OOOH,OOOH,OOOH
, BT E5
OOOH, OOOH, OOOH, OOOH, 066H, 066H, 066H, 066H ; TH::E6

CO 00 00
00 76 DC

712
713
714

18 18 18 18
18 18 18 18
00 00 00 00
00 00 00 00

669
670
671
672
673
674

675
18 18 18 18
FF FF FF FF
FF FF FF FF
00 00 00 00
FF FF FF FF
FO FO FO FO
FO FO FO FO
OF OF OF OF
OF OF OF OF
FF FF FF FF

00
00 00 00 00 00

08
DC
00
C6
FC
00
CO
CO
00
6C
6C
00
30
C6
00
08
08
00
66
60
00

619
620
621
622
623
624
625
626

76 00 00 00
00 00 7C C6
CO CO 40 00
FE C6 C6 CO
CO 00 00 00
00 00 FE 6C
6C 00 00 00
FE C6 60 30
FE 00 00 00
00 00 00 7E

08
70
00
00
66
7C
60
00
00
18 18
18 18 18
00 00 7E
66 66
3C 18 7E
00 00 38
FE C6
C6 6C 38
00 00 38
C6 6C
6C 6C EE
00 00 IE
3E 66
66 66 3C
00 00 00
DB DB
7 E 00 00
00 00 03
DB F3
7 E 60 CO
00 00 I C
7C 60
60 30 I C
DO 00 00
C6 C6
C6 C6 C6

676

677

683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704

705

00 00 00
6C C6 C6
00 00 00
6C C6 C6

DB
DB

07CH, 060H, 060H, OCOH, OOOH, OOOH
, BT _E6
000H,OOOH,OOOH,OOOH,076H,OOCH,018H,018H ; TH_E7

DB
DB

018H,018H,018H,OOOH,OOOH,OOOH
, BT_E7
000H,OOOH,07EH,018H,03CH,066H,066H,066H ; TH_E8

DB
DB

03CH,OI8H,07EH,OOOH,OOOH,OOOH
, BT_E8
000H,OOOH,038H,06CH,OC6H,OC6H,OFEH,OC6H; TH_E9

722

DB
DB

OC6H, 06CH, 038H, OOOH, OOOH, OOOH
, BT E9
OOOH, OOOH, 038H, 06CH, OC6H, OC6H, OC6H, 06CH ; TH::EA

DB
DB

06CH,06CH,OEEH,OOOH,OOOH,OOOH
, BT EA
000H,OOOH,01EH,030H,018H,OOCH,03EH,066H ; TH::EB

DB
DB

066H,066H,03CH,OOOH,OOOH,OOOH
, BT EB
OOOH, OOOH, OOOH, OOOH, OOOH, 07EH, ODBH, ODBH ; TH::EC

DB
DB

07EH,OOOH,OOOH,OOOH,OOOH,OOOH
, BT EC
OOOH, OOOH, 003H, 006H, 07EH, OOBH, ODBH, 0 F3H ; TH::[O

DB
DB

07EH,060H,OCOH,OOOH,OOOH,OOOH
, BT ED
OOOH, OOOH, 0 1CH, 030H, 060H, 060H, 07CH, 060H ; TH::EE

DB
DB

060H,030H,01CH,OOOH,OOOH,OOOH
, BT EE
OOOH, OOOH, OOOH, 07CH, OC6H, OC6H, OC6H, OC6H ; TH::EF

723
724

00 00 00
30 18 DC

725
726
727

00 00 00
00 00 7 E

728
729
730
731

00 00 00
06 7E DB
00 GO 00
30 60 60
00 00 00
7C C6 C6

TH_EO

716
717
718
719
720
721

715
00 00 00
18 3C 66

BT DA
TH::DB

732
733
734

735
736
737
738
739

00 00 00

740
741

DB

OC6H, OC6H, OC6H, OOOH, OOOH, OOOH

DO 00 DO FE 00 00
FE 00
00 FE 00 00 00 00

742
743
744

DB

OOOH,OOOH,OOOH,OFEH,OOOH,OOOH,OFEH,OOOH ;

THJO

DB

OOOH, OFEH, OOOH, OOOH, OOOH, OOOH

BTJO

IBM Enhanced Graphics Adapter 157

002E
0036
003C
0044
004A
0052
0058
0060
0066
006E
0074
007C
0062
DOHA
0090
0098
009E
00A6
OOAC
00B4
OOBA
00C2
00C8
0000
0006
OOOE
00E4
OOEC
00F2
00 FA
OEOO

00
18
00
00
DC
30
00
30
DC
00
18
18
18
16
06
00
7E
16
00
00
DC
00
00
00
00
18
00
00
00
00
00
DC
6C
00
6C
00
00
F6
00
00
7C
7C
00
00
00

00
18
00
00
18
00
00
18
00
00
18
18
16
18
06
00
00
16
00
76
00
36
00
00
00
18
00
00
18
00
OF
EC
3C
08
00
00
70
00
00
00
7C
7C
00
00
00

00 18 18 7E
FF 00 00 00
30 18 DC 06
7E 00 00 00
DC 18 30 60
7E 00 00 00
DE lB lB 18
18 18 18 18
16 16 16 16
70 00 00 00
00 16 16 00
00 00 00 00
00 00 76 DC
00 00 00 00
6C 6C 38 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
DC DC DC DC
lC 00 00 00
6C 6C 6C 6C
00 00 00 00
08 30 60 C8
00 00 00 00
00 00 7C 7C
00 00 00 00
00 00 00 00
00 00 00 00

745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
767
766
769
790
791
1

0000

2
3
4

0000

5

6
7
6
9

0000
0001
0009
OOOF
0010
0016
001 E
001F
0027
0020
002E
0036
003C
0030
0045
004B
004C
0054
005A
005B
0063
0069
006A
0072
0078
0079
0081
0087
0088
0090
0096
0097
009F
00A5
00A6
OOAE
OOB4
00B5
OOBD
OOC3
00C4
OOCC
0002
0003
OODB
OOEl
00E2
OOEA
OOFO
OOFl

10
00
FF
24
22
00
00
00
28
00
FF
18
20
00
FF
00
40
00
C3
C3
54
00
18
18
56
00
C3
66
57
00
DB
FF
58
00
18
66
59
00
3C
18
5A
00
18
61
60
00
FF
DB
76
00
C3
66
77
00
C3
DB
91
00
lB
08
9B
00
CO
7E
90
00

00 00 00 24 66
66
00 00 00 00 00
63 63 63 22 00
00
00 00 00 00 00

10
11
12
13
14
15
16
17
18
19
20
21

22
00 00 18 18 18
18
18 00 00 00 00
00 00 00 00 00
00
00 00 00 00 00
00 C3 E7 FF DB
C3
C3 C3 00 00 00
00 FF DB 99 18
lB
18 3C 00 00 00
00 C3 C3 C3 C3
C3
3C 18 00 00 00
00 C3 C3 C3 C3
DB
66 66 00 00 00
00 C3 C3 66 3C
3C
C3 C3 00 00 00
00 C3 C3 C3 66
18
18 3C 00 00 00
00 FF C3 86 DC
30
C3 FF 00 00 00
00 00 00 00 E6
DB
DB DB 00 00 00
00 00 00 00 C3
C3
3C 18 00 00 00
00 00 00 00 C3
DB
FF 66 00 00 00
00 DO 00 6E 3B
7E
DC 77 00 00 00
18 18 7E C3 CO
C3
18 18 00 00 00
00 C3 66 3C 18

23
24
25
26
27
28
29
30
31
32

33
34
35
36
37
38
39
40
41
42
43

44

DB

OOOH,000H,000H,018H,018H,07EH,018H,018H : TH_Fl

DB
DB

OOOH,OOOH,OFFH,OOOH,OOOH,OOOH
, ST_F1
000H,000H,030H,016H,00CH,006H,00GH,016H : TH_F2

DB
DB

030H, OOOH, 07EH, OOOH, OOOH, OOOH
, STJ2
000H,000H,00CH,018H,030H,060H,030H,018H : TH_F3

DB
DB

00CH,000H,07EH,000H,000H,000H
, ST_F3
000H,000H,00EH,01SH,01BH,016H,016H,016H : TH_F4

DB
DB

016H, 016H, 016H, 018H, 018H, 016H
, BTJ4
018H,016H,016H,018H,016H,016H,016H,C18H: THJ5

DB
DB

008H,OD8H,070H,000H,000H,000H
, BTJ5
OOOH,000H,000H,018H,018H,000H,07EH,000H : THJ6

DB
DB

018H,018H,000H,000H,000H,OOOH
, BT_F6
OOOH,000H,000H,000H,076H,00CH,000H,076H : THJ7

DB
DB

ODCH,OOOH,OOOH,OOOH,OOOH,OOOH
, BTJ7
OOOH,038H,06CH,06CH,038H,000H,000H,000H : THJ8

DB
DB

OOOH,OOOH,OOOH,OOOH,OOOH,OOOH
, BTJ8
OOOH,000H,000H,000H,000H,000H,018H,018H : TH_F9

DB
DB

OOOH,OOOH,OOOH,OOOH,OOOH,OOOH
, BTJ9
OODH,000H,000H,000H,000H,000H,000H,018H : THJA

DB
DB

OOOH, OOOH, OOOH, OOOH, OOOH,OOOH
, BT_FA
OOOH,OOFH,OOCH,OOCH,OOCH,OOCH,OOCH,OECH ; THJB

DB
DB

D6CH,03CH,01CH,000H,000H,000H
, BT_FB
OOOH, OD8H, 06CH, 06CH, 06CH, 06CH,06CH, OOOH ; THJC

DB
DB

OOOH,OOOH,OOOH,OOOH,OOOH,OOOH
, BT FC
000H,070H,OD8H,030H,060H,OC8H,OF8H,000H : TH::FD

DB
DB

OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
, BT FO
OOOH, OOOH, OOOH, OOOH, 07CH, 07CH, 07CH, 07CH ; TH::FE

DB
DB

07CH,07CH,000H,000H,000H,000H
, BT FE
OOOH,OOOH,OOOH,OOOH,OOOH,OOOH,OOOH,OOOH ; TH::FF

DB
OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
ENDS
END
PAGE,120
SUBTTL MONOCHROME CHARACTER GENERATOR
CODE
SEGMENT PUBLI C
PUBL I C CGMN FOG
CGMN_FOG
LABEL
BYTE

B TJ F

CODE

ALPHA SUPPLEMENT

STRUCTURE OF TH I S FILE
DB
XXH
WHERE XX I S THE HEX CODE FOR THE FOLLOW I NG CHAR
DB
(BYTES
13 OF THAT CHARACTER J

°-

INDICATES NO MORE REPLACEMENTS TO BE DONE

DB

OOH

DB
DB

010H
,
000H,000H,000H,000H,024H,066H,OFFH,066H ; TH_1D

DB
DB
DB

024H,000H,000H,000H,000H,000H
BT_1D
022H
,
OOOH, 063H, 063H, 063H, 022H, OOOH, OOOH, OOOH ; TH_22 "

DB
DB
DB

OOOH,OOOH,OOOH,OOOH,OOOH,OOOH
BT_22 "
02BH
,
000H,000H,000H,018H,016H,018H,OFFH,018H : TH_2B +

DB

018H,018H,000H,000H,000H,000H

,

BT_2B +

~

~~

DB

OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OFFH, OOOH ; TH_2D -

DB

OOOH, OOOH, OOOH, OOOH, OOOH, OOOH

,

BT _20 -

~

~~

DB

OOOH,000H,OC3H,OE7H,OFFH,ODBH,OC3H,OC3H; TH_4D M

DB
DB
DB

OC3H,OC3H,OC3H,000H,000H,000H
BT_4D M
054H
,
OOOH,000H,OFFH,ODBH,099H,018H,018H,018H ; TH_54 T

DB
DB
DB

018H,018H,03CII,000H,000H,000H
BT_54 T
056H
,
OOOH, OOOH, OC3H, OC3H, OC3H, OC3H, OC3H,OC3H : TH_56 V

DB
DB
DB

066H,03CH,018H,000H,000H,000H
BT_56 V
057H
,
OOOH,000H,0C3H,OC3H,OC3H,OC3H,00BH,DOBH ; TH_57 W

45
46
47
48
49
50
51
52
53
54

DB
DB
DB

OFFH,066H,066H,ODOH,000H,000H
BT_57 W
058H
,
000H,000H,OC3H,OC3H,066H,03CH,018H,03CH; TH_58 X

DB
DB
DB

066H,OC3H,0C3H,000H,000H,000H
BT_58 X
059H
,
OOOH,000H,OC3H·,OC3H,OC3H,066H,03CH,018H ; TH_59 Y

DB

018H,018H,03CH,000H,000H,000H

~

M~

55

DB

000H,000H,OFfH,OC3H,086H,00CH,018H,030H ; TH_5A Z

DB

061H,0C3H,OfFH,000H,000H,000H

56
57
56
59
60
61
62
63
64
65
66
67

66
69
70
71
72
73
74
75
76
77
76
79

BT_59 Y

,
, BT_5A Z
;

~

~~

DB

000H,000H,000H,000H,000H,OE6H,OFFH,ODBH ; TH_6D L.C. M

DB
DB
DB

OOBH,ODBH,ODBH,OOOH,OOOH,OOOH
BT_6D L.C. M
076H
,
OOOH,000H,000H,000H,000H,DC3H,OCjH,OC3H ; TH_76 L.C. V

DB
DB
DB

066H,03CH,018H,000H,000H,000H
BT_76 L.C. V
077H
,
000H,000H,000H,000H,000H,OC3H,OC3H,00BH ; TH_77 L.C. W

DB
DB
DB

ODBH,OffH,066H,000H,000H,000H
, BT_77 L.C. W
091 H
;
000H,000H,000H,000H,06EH,03BH,01BH,07EH ; TH_91

DB
DB
DB

OD8H,ODCH,077H,000H,000H,000H
BT_91
09BH
,
000H,018H,018H,07EH,OC3H,OCOH,OCOH,OC3H ; TH_9B

DB

07EH,018H,018H,000H,000H,000H

,

~

~~

DB

000H,000H,OC3H,066H,03CH,018H,OFFH,018H ;

158 IBM Enhanced Graphics Adapter

BT_9B
TH_9D

00F9
OOH
0100
0108
010E
010F
0117
0110
01l[
0126
012C
0120

FF
H
9E
00
66
66
Fl
00
18
18
F6
00
FF
00
00

18
18 18 00 00 00
FC 66 66 7C 62
6F
66 F3 00 00 00
00 18 18 18 FF
18
00 FF 00 00 00
00 18 18 00 00
00
18 18 00 00 00

0000
0000
0000
0008
0010
0018
0020
0028
0030
0038
0040
0048
0050
0058
0060
0068
0070
0078
0080
0088
0090
0098
OOAO
00A8
OOBO
00B8
OOCO
00C8
0000
0008
ODED
00E8
OOFO
00F8
0100
0108
0110
0118
0120
0128
0130
0138
0140

00
00
7E
81
7E
FF
6C
10
10
10
38
38
10
38
00
00
FF
FF
00
3C
FF
C3
OF
CC
3C
7E
3F
FO
7F
E6
99
5A

00
00
81
7E
H
7E
FE
00
38
00
7C
7C
10
7C
00
00
FF
FF
3C
00
C3
FF
07
78
66
18
33
EO
63
CO
5A
99

80
80
02
02
18
3C
66
66
7F
18
3E
CC
00
7E
18
18
18
18
18
18
00
00
00
00
00
00
00
00
00
00
00
00

EO
00
DE
00
3C
18
66
00
DB
00
63
78
00
00
3C
FF
3C
00
18
00
18
00
30
00
00
00
24
00
18
00
FF
00

00
00
30
30
6C
00
6C
6C
30
30
00
C6
38
76
60
00
18

00
00
78
00
6C
00
6C
00
7C
00
C6
00
6C
00
60
00
30

00 00 00 00
A5 81 BD 99
DB FF C3 E7
FE FE 7C 38
7C FE 7C 38
38 FE FE 7C
38 7C FE 7C
18 3C 3C 18
E7 C3 C3 E7
66 42 42 66
99 BD BD 99
OF 70 CC cc
66 66 3C 18
3F 30 30 70
7F 63 63 67
3C E7 E7 3C
F8 FE F8 EO
3E FE 3E DE
7E 18 18 7E
66 66 66 00
DB 7B 1 B 1 B
38 6C 6C 38
00 00 7 E 7E
7E 18 7E 3C
7E 18 18 18
18 18 7E 3C
OC FE DC 18
60 FE 60 30
CO CO co FE
66 FF 66 24
3C 7E FF FF
FF 7E 3C 18
00 00 00 00
78 30 30 00
6C 00 00 00
FE 6C FE 6C
CO 78 DC F8
CC 18 30 66
38 76 DC CC
CO 00 00 00
60 60 60 30

18 00

0148
0150
0158
0160
0168
0170
0178
0180
0188

60
60
00
00
00
00
00
30
00
00
00
30
06
80

30
00
66
00
30
00
00
60
00
00
00
00
DC
00

18 18 18 30

7C
7C
30
FC

C6 CE DE F6 E6
00
70 30 30 30 30
00

80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76

77
78
79
80
81
82
83
84
85
86
87
88
89
90
91

92
3C FF 3C 66
30 FC 30 30
00 00 00 30
00 FC 00 00
00 00 00 30
18 30 60 CO

93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109

CODE

CODE
CGDDOT

DB
DB
DB

OFFH, 0 18H, 018H, OOOH, OOOH, OOOH
09EH
OOOH, OFCH, 066H, 066H, 07CH, 062H, 066H, OMH ;

BT_9D

DB
DB
DB

066H, 066H, OF3H, OOOH, OOOH, OOOH
OF1H
OOOH, OOOH, 018H, 018H, 018H, OF FH, 018H, 018H ;

BT_9E

DB
DB
DB

BT_Fl
o 18H, OOOH, OFFH, OOOH, OOOH, OOOH
OF6H
OOOH,DOOH, 018H, 018H, OOOH, OOOH, OFFH, OOOH ; TH_F6

OOOH, 0 18H, 0 18H, OOOH, OOOH, OOOH
DB
OODH
DB
ENDS
END
PAGE,120
SUBTTL DOUBLE DOT CHARACTER GENERATOR
SEGMENT PUBL I C
PUBLIC CGDDOT, I NT _ H _1
LABEL
BYTE

TH_9E

TH - Fl

BT F6
NO-MORE

DB

DOUBLE DOT
OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH ; 0_00

DB

07EH, 081 H, OA5H, 081 H, OBDH, 099H, 081 H, 07EH ; 0_01

08

07EH, OF FH, ODBH, OF FH, OC3H, OE7H, OFFH, 07EH ; 0_02

DB

06CH, OFEH, OFEH, OFEH, 07CH, 038H, 010H, OOOH ; 0_03

DB

01 OH, 038H, 07CH, OFEH, 07CH, 038H, 0 1OH, OOOH ; 0_04
038H, 07CH, 038H, 0 FEH, 0 FEH, 07CH, 038H, 07CH ; 0_05

DB

01 OH, 01 OH, 038H, 07CH, OFEH, 07CH, 038H, 07CH ; 0_06

DB

OOOH, DOOH, 0 18H, 03CH, 03CH, 0 18H, OOOH, OOOH ; 0_07

DB

OFFH, OFFH, OE7H, OC3H, OC3H, OE7H, OFFH, OFFH ; 0_08

DB

OOOH, 03CH, 066H, 042H, 042H, 066H, 03CH, OOOH ; 0_09

DB

OF FH, OC3H, 099H, OBOH, OBDH, 099H, OC3H, 0 FFH ; D_OA

OB

OOFH, 007H, 00 FH, 07DH, OCCH, OCCH, OCCH, 078H ; D_OB

DB

03CH, 066H, 066H, 066H, 03CH, 018H, 07EH, 018H ; D_OC

DB

03 FH, 03 3H, 03 FH, 030H, 030H, 070H, 0 FOH, OEOH ; 0_00

DB

07FH, 063H, 07FH, 063H, 063H, 067H, OE6H, OCOH ; O_OE
099H, 05AH, 03CH, OE7H, OE7H, 03CH, 05AH, 099H ; D_OF

OB

080H, OEOH, 0 F8H, OFEH, 0 F8H, OEOH, 080H, OOOH ; 0_10

DB

002H, OOEH, 03 EH, 0 FEH, 03EH, OOEH, 002H, OOOH ; 0_11

DB

o 18H, 03CH, 07EH, 0 18H, 0 18H, 07EH, 03CH, 018H ; 0_12

DB

066H, 066H, 066H, 066H, 066H, OOOH, 066H, OOOH ; 0_13

DB

07 FH, ODBH, ODBH, 07BH, 01 BH, 0 1 BH, 01 BH, OOOH ; 0_14

DB

03EH, 063H, 038H, OoCH, 06CH, 038H, OCCH, 078H ; 0_15

DB

OOOH, OOOH, OOOH, OOOH, 07EH, 07EH, 07EH, OOOH ; 0_16
018H, 03CH, 07EH, 018H, 07EH, 03CH, 018H, OFFH ; 0_17

DB

o 18H, 03CH, 07EH, 0 18H, 0 18H, 0 18H, 0 18H, OOOH ; 0_18

DB

018H, 018H, 018H, 018H, 07EH, 03CH, 018H,000H ; 0_19

DB

OOOH, 018H, OOCH, 0 FEH, OOCH, 0 18H, OOOH, OOOH ; o_lA

DB

OOOH, 030H, 060H, OFEH, 060H, 030H, OOOH, OOOH ; o_lB

DB

OOOH, OOOH, OCOH, OCOH, OCOH, 0 FEH, OOOH, OOOH ; o_lC

DB

OOOH, 024H, 066H, 0 FFH, 066H, 024H, OOOH, OOOH ; 0_10

DB

OOOH, 018H, 03CH, 07EH, OFFH, 0 FFH, OOOH, OOOH ; o_lE

DB

OOOH, OF FH, OFFH, 07EH, 03CH, 0 18H, OOOH, OOOH ; o_lF
SP 0_20

DB

OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH ;

DB

030H, 078H, 078H, 030H, 030H, OOOH, 030H, OOOH ;

! 0_21

DB

06CH, 06CH, 06CH, OOOH, OOOH, OOOH, OOOH, OOOH ;

II

DB

06CH, 06CH, OFEH, 06CH, 0 FEH, 06CH, 06CH, OOOH ; # 0 23

DB

030H, 07CH, OCOH, 078H, OOCH, 0 F8H, 030H, OOOH ; $ 0_24

DB

OOOH, OC6H, OCCH, 018H, 030H, 066H, OC6H, OOOH ;

DB

038H, 06CH, 038H, 076H, ODCH, OCCH, 076H, OOOH ; & 0_26

D_22

PER CENT 0_25

0_27

060H, 060H, OCOH, OOOH, OOOH, OOOH, OOOH, OOOH ;

0_28

DB

018H, 030H, 060H, 060H, 060H, 030H, 0 18H, OOOH ;

(

DB

060H, 030H, 0 18H, 0 18H, 0 18H, 030H, 060H, OOOH ;

) 0_29

*

D_2A

DB

OOOH, 066H, 03CH, 0 F FH, 03CH, 066H, OOOH, OODH ;

DB

OOOH, 030H, 030H, OFCH, 030H, 030H, OOOH, OOOH ; + D_2B

DB

OOOH, OOOH, OOOH, OOOH, OOOH, 030H, 030H, 060H ;

DB

OOOH, OOOH, OOOH, 0 FCH, OOOH, OOOH, OOOH, OOOH ; -

0_20

DB

OOOH, OOOH, OOOH, OOOH, OOOH, 030H, 030H, OOOH ;

D_2E

006H, OOCH, 0 18H, 030H, 060H, OCOH, 080H, OOOH ;

D_2C

/

D_2F

DB

07CH, OC6H, OCEH, ODEH, OF6H, OE6H, 07CH, OOOH ; o 0_30

DB

030H, 070H, 030H, 030H, 030H, 030H, OFCH, OOOH ;

1 0_31

IBM Enhanced Graphics Adapter 159

0190
0198
01AO
01A8
01BO
01B8
01CO
01C6
0100
0106
OlEO
01E6
01F0
01f8
0200
0206
0210
0216
0220
0226
0230
0236
0240
0248
0250
0258
0260
0268
0270
0278
0280
0268
0290
0298
02AO
02A8
02BO
02B8
02CO
02C8
0200
0208
02EO
02E8
02fO
02f8
0300
0308
0310
0318
0320
0328
0330
0338
0340
0348
0350
0358
0360
0368
0370
0378

78
fC
78
78
lC
lE
FC
78
36
76
FC
30
76
76
76
70
00
30
00
30
16
16
00
00
60
60
76
30

CC
00
CC
00
3C
00
CO
00
60
00
CC
00
CC
00
CC
00
30
00
30
60
30
00
00
00
30
00
CC
00

OC 38 60 CC

7C
76
30
CC
FC
FC
3C
3C
F8
F8
FE
FE
FE
FO
3C
3E
CC
CC
78
78
1[
78
[6
[6
FO
FE
C6
C6
C6
C6
38
38

C6
00
76
00
66
00
66
00
6C
00
62
00
62
00
66
00
CC
00
30
00
DC
00
66
00
60
00
EE
00
E6
00
6C
00

DE DE DE CO

FC
FO
78
lC
FC
E6
78
78
FC
78
CC
FC
CC
30
C6
C6
C6
C6
CC
78
FE
FE
78
78
CO
02
78
78
10
00
00
00

66
00
CC
00
66
00
CC
00
B4
00
CC
00
CC
00
C6
00
C6
00
CC
00
C6
00
60
00
60
00
18
00
38
00
00
FF

66 7C 60 60

30
00
00
76
EO
DC
00
78
1C
76
00
78
38
FO
00
OC
EO
E6
30
78
OC
CC
EO
E6
70
78
00
C6
00
CC
00

30 18 00
00
00 78 OC
00
60 60 7C
DO
00 78 CC
00
OC OC 7C
00
00 78 CC
00
6C 60 fO
00
00 76 CC
F8
60 6C 76
00
00 70 30
00
00 OC OC
78
60 66 6C
00
30 30 30
00
00 CC FE
00
00 F8 CC
00
00 78 CC

OC 38 OC CC
6C CC FE DC
F8 DC OC CC
CO f8 CC CC
OC 18 30 30
CC 76 CC CC
CC 7C OC 18
30 00 00 30
30 00 00 30
60 CO 60 30
fC 00 00 fC
16 OC 16 30
OC 16 30 00

CC CC fC CC
66 7C 66 66

co co co

66

66 66 66 6C
66 76 66 62
68 76 68 60
CO CO CE 66
CC FC CC CC
30 30 30 30
OC DC CC CC
6C 78 6C 66
60 60 62 66
FE FE 06 C6
F6 OE CE C6
C6 C6 C6 6C

CC CC DC 78
66 7C 6C 66
EO 70 lC CC
30 30 30 30
CC CC CC CC
CC CC CC 78
C6 06 fE EE
6C 36 38 6C
CC 78 30 30
6C 18 32 66
60 60 60 60
30 18 OC 06
18 18 18 18
6C C6 00 00
00 00 00 00
00 00
7C CC
66 66
CO CC
CC CC
FC CO
60 60
CC 7C
66 66
30 30
OC CC
78 6C
30 30
FE 06
CC CC
CC CC

110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
136
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235

08

078H,OCCH,OOCH,038H, 060H, OCCH, OfCH,OOOH ; 2 0_32

DB

078H, OCCH, OOCH, 038H, OOCH, OCCH, 078H, OOOH ;

3 0_33

DB

01CH,03CH, 06CH, OCCH, OfEH, OOCH, 01 EH, OOOH ;

4 0_34

DB

OFCH, OCOH, OF8H, OOCH, 00CH,OCCH,078H, OOOH ; 5 0_35

DB

038H, 060H, OCOH, Of6H, OCCH, OCCH, 076H, OOOH ; 6 0_36

OB

OfCH, OCCH, OOCH, 016H, 030H,030H,030H, OOOH ; 7 0_37

DB

078H, OCCH, OCCH, 078H, OCCH,OCCH,078H, OOOH ; 8 0_38

OB

076H,OCCH,OCCH,07CH,OOCH,016H ,070H,OOOH ; 9 0_39

DB

OOOH, 030H, 030H, OOOH, OOOH, 030H, 030H, OOOH ;

: 0_3A

DB

OOOH, 030H, 030H, OOOH, OOOH, 030H, 030H, 060H ;

; 0_3B

DB

016H, 030H, 060H, OCOH, 060H, 030H, 016H, OOOH ;

< 0_3C

DB

OOOH, OOOH, OfCH, OOOH, OOOH, OfCH, OOOH, OOOH ; = 0_30

DB

060H, 030H, 016H, OOCH, 016H, 030H, 060H, OOOH ; > 0_3E

DB

078H, OCCH, OOCH, 018H, 030H, OOOH, 030H, OOOH ; ? 0_3f

OB

07CH,OC6H,OOEH,OOEH,OOEH,OCOH,078H,OOOH ; @ 0_40

DB

030H, 076H, OCCH, OCCH, OFCH, OCCH, OCCH, OOOH ; A 0_41

DB

OfCH, 066H, 066H, 07CH, 066H, 066H, OfCH, OOOH ; B 0_42

DB

03CH, 066H, OCOH, OCOH, OCOH, 066H, 03CH, OOOH ; C 0_43

DB

OfBH, 06CH, 066H, 066H, 066H, 06CH, Of8H, OOOH ;

°

DB

OfEH, 062H, 066H, 076H, 068H, 062H, OFEH, OOOH ;

E 0_45

DB

OFEH, 062H, 06BH, 07BH, 06BH, 060H, OFOH, OOOH ;

F 0_46

DB

03CH, 066H, OCOH, OCOH, OCEH, 066H, 03EH, OOOH ; G 0_47

0_44

OCCH, OCCH, OCCH, 0 FCH, OCCH, OCCH , OCCH, 000 H ; H 0_46
I 0_49

DB

076H, 030H, 030H, 030H, 030H, 030H, 076H, OOOH ;

DB

01 EH, OOCH, OOCH, OOCH, OCCH, OCCH, 078H, OOOH ; J 0_4A

DB

OE6H, 066H, 06CH, 07BH, 06CH, 066H, OE6H, OOOH ;

K 0_4B

DB

oFOH, 060H, 060H, 060H, 062H, 066H, OFEH, OOOH

L 0_4C

;

OC6H, OFFH, OFFH, 0 FFH, 006H, OC6H, OC6H, OOOH ; M D_40
DB

OC6H, OE6H, OF6H, OOEH. OCEH, OC6H, OC6H, OOOH ; N 0_4E

DB

038H, 06CH, OC6H, OC6H, OC6H, 06CH, 038H, OOOH ;

o

OFCH, 066H, 066H, 07CH, 060H, 060H, OFOH, OOOH ;

PO_50

0_4F

DB

076H, OCCH, OCCH, OCCH, OOCH, 078H, 01 CH, OOOH ; Q 0_51

DB

OFCH. 066H, 066H, 07CH, 06CH, 066H, OE6H, OOOH ;

R 0_52

DB

078H, OCCH, OEOH, 070H, 01 CH, OCCH, 078H, OOOH ;

SO_53

DB

OFCH, OB4H, 030H, 030H, 030H, 030H, 078H, OOOH ; TO_54

DB

OCCH, OCCH, OCCH, OCCH, OCCH, OCCH, OFCH, OOOH ;

DB

OCCH, OCCH, OCCH, OCCH, OCCH, 078H, 030H, OOOH ; V 0_56

DB

OC6H, OC6H, OC6H, 006H, OFEH, OEEH, OC6H, OOOH ; W 0_57

DB

OC6H, OC6H, 06CH, 038H, 038H, 06CH, OC6H, OOOH ;

DB

OCCH, OCCH, OCCH, 076H, 030H, 030H, 078H, OOOH ; YO_59

DB

OfEH, OC6H, 08CH, 018H, 032H, 066H, OfEH, OOOH ; Z 0_5A

DB

078H, 060H, 060H, 060H, 060H, 060H, 078H, OOOH ;

DB

OCOH, 060H, 030H, 016H, OOCH, 006H, 002H, OOOH ; BACKSLASH 0_5C

DB

078H, 018H, 018H, 018H, 018H, 0 18H, 078H, OOOH ;

DB

01 OH, 038H, 06CH, OC6H, OOOH, OOOH, OOOH, OOOH ; CIRCUMFLEX 0_5E

DB

OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OFFH ; _ 0_5F

DB

030H, 030H, 01 BH, OOOH, OOOH, OOOH, OOOH, OOOH ;

DB

OOOH, OOOH, 07BH, OOCH, 07CH, OCCH, 076H, OOOH ;

LOWER CASE A 0_61

DB

OEOH, 060H, 060H, 07CH, 066H, 066H, OOCH, OOOH ;

L.C. B 0_62

DB

OOOH, OOOH, 078H, OCCH, OCOH, OCCH, 078H, OOOH ;

L.C. C 0_63

DB

01 CH, OOCH, OOCH, 07CH, OCCH, OCCH, 076H, OOOH ;

L.C.

DB

OOOH, OOOH, 078H, OCCH, OfCH, OCOH, 078H, OOOH ;

L.C. E 0_65

DB

038H, 06CH, 060H, OFOH, 060H, 060H, OFOH, OOOH ; L.C.

DB

OOOH, OOOH, 076H, OCCH, OCCH, 07CH, OOCH, OF8H ;

L.C. G 0_67

DB

OEOH, 060H, 06CH, 076H. 066H, 066H, OE6H, OOOH ;

L.C. H 0_68

DB

030H, OOOH, 070H, 030H, 030H, 030H, 078H, OOOH ;

L.C.

DB

OOCH, OOOH, OOCH, OOCH, OOCH, OCCH, OCCH, 078H ;

L.C. J 0_6A

DB

OEOH, 060H, 066H, 06CH, 078H, 06CH, OE6H, OOOH ;

L.C. K 0_6B

DB

070H, 030H, 030H, 030H, 030H, 030H, 078H, OOOH ;

L.C. L 0_6C

DB

OOOH, OOOH, OCCH, OFEH, OFEH, 006H, OC6H, OOOH ;

L.C. M 0_60

DB

OOOH, OOOH, OF8H, OCCH, OCCH, OCCH, OCCH, OOOH ;

L.C. N 0_6E

DB

OOOH, OOOH, 078H, OCCH, OCCH, OCCH, 078H, OOOH ;

L.C.

160 IBM Enhanced Graphics Adapter

U 0_55

X 0_58

[

0_5B

) 0_50

0_60

°

0_64

F 0_66

I 0_69

o

0_6F

76 00
0360
0368
0390
0396
03AO
03A8
03BO
03B6
03CO
03C6
0300
0306
03EO
03E8
03FO
03F8

00
60
00
DC
00
FO
00
F8
10
18
00
76
00
30
00
6C
00
C6
00
DC
00
FC
1C
lC
18
18
EO
EO
76
00
00
FE

00
FO
00
1E
00
00
00
00
30
00
00
00
00
00
00
00
00
00
00
F6
00
00
30
00
18
00
30
00
DC
00
10
00

DC 66 66 7C

78
DC
00
7E
1C
78
7E
3F
CC
7E
EO
7E
30
7E
00
DC
7E
3C
CC
78
EO
78
CC
78
7C
3C
EO
78
C6
C6
30
CC

CC
78
CC
00
00
00
C3
00
00
00
00
00
30
00
00
38
C3
00
00
00
00
00
00
00
C6
00
00
00
38
00
30
00

co CC 78 18

1C
FC
00
IF
3E
CE
78
78
00
78
00
78
78
7E
00
7E
00
DC
C3
18
CC
78
18
18
38
FC
CC
30
F8
C6
DE
08

00
00
00
00
6C
00
CC
00
CC
00
EO
00
CC
00
EO
00
CC
F8
18
00
00
00
18
18
6C
00

FC 60 78 60

76 CC CC 7C
DC 76 66 60
7C CO 78 DC
7C 30 30 34
CC CC CC CC
CC CC CC 78
C6 06 FE FE
C6 6C 38 6C
CC CC CC 7C
FC 96 30 64
30 EO 30 30
18 00 18 18
30 1C 30 30
00 00 00 00
38 6C C6 C6

0400
0400
0408
0410
0418
0420
0428
0430
0438
0440
0448
0450
0458
0460
0468
0470
0478
0480
0486
0490
0498
04AO
04A8
04BO
04B8
04CO
04C8
0400
0408
04EO
04E8
04FO
04F8
0500
0508
0510
0518
0520
052B
0530
0538
0540
0548
0550
0558

cc

00 CC CC CC
78 CC FC CO
3C 06 3E 66
78 DC 7C CC
78 DC 7C CC
78 DC 7C CC
78 CO CO 78
3C 66 7E 60
78 CC FC CO
78

cc

FC CO

70 30 30 30
38 18 18 18
70 30 30 30
6C C6 FE C6
00 78 CC FC

7 F DC 7 F CC
CC FE CC CC
00 78 CC CC
00 78 CC CC
00 78 CC CC
00 CC CC CC
00 CC CC CC
00 CC CC 7C
3C 66 66 3C
CC CC CC CC
7E CO CO 7E
64 FO 60 E6
78 FC 30 FC

30
CC CC FA C6 CF
C7
18 18 3C 18 18
70

1C 00
7E 00
38 00
78 00
ODIC
78 00
ODIC
7E 00
00 F8
CC 00
FC 00
cc 00
3C 6C
00 00
38 6C
00 00
30 00
78 00
00 00
00 00
00 00
00 00
C3 C6

78 DC 7C CC
70 30 30 30
00 78 CC CC
00 CC CC CC
00 F8 CC CC
CC EC FC DC
6C 3E 00 7E
6C 38 00 7C
30 60 CO

cc

00 FC CO CO
00 FC DC DC
CC DE 33 66

236
237
236
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361

DB

OOOH, OOOH, ODCH, 066H, 066H, 07CH, 060H, OFOH ;

L.Co

DB

OOOH, OOOH, 076H, OCCH, OCCH, 07CH, OOCH, 01 EH ;

LoCo Q 0_71

DB

OOOH, OOOH, ODCH, 076H, 066H, 060H, OFOH, OOOH ;

LoCo

R 0_72

DB

OOOH, OOOH, 07CH, OCOH, 076H, OOCH, OF8H, OOOH ;

LoCo

S 0_73

DB

010H, 030H,07CH, 030H, 030H, 034H, 018H, OOOH ;

LoCo T 0_74

DB

OOOH, OOOH, OCCH, OCCH, OCCH, OCCH, 076H, OOOH ;

LoCo U 0_75

DB

DOOH, OOOH,OCCH, OCCH, OCCH, 076H, 030H, OOOH ;

LoCo V 0_76

DB

OOOH, OOOH, OC6H, OD6H, OFEH, OFEH, 06CH, OOOH ;

LoCo W 0_77

DB

OOOH, OOOH, OC6H, 06CH, 036H, 06CH, OC6H, OOOH ;

LoCo X 0_78

DB

OOOH, OOOH, OCCH, OCCH, OCCH, 07CH, OOCH, OF8H ;

LoCo V 0_79

DB

OOOH, OOOH, OFCH, 098H, 030H, 064H, 0 FeH, OOOH ;

L.C o Z D_7A

DB

01 CH, 030H, 030H, OEOH, 030H, 030H, 01 CH, OOOH ;

L BRIIK 0_7B

DB

o18H, 018H, 018H, OOOH, 0 18H, 018H, 018H, OOOH

DB

OEOH, 030H, 030H, 01 CH, 030H, 030H, OEOH, OOOH ;

DB

076H, OOCH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH ;

TILDE D_7E

DB

OOOH, 01 OH, 038H, 06CH, OC6H, OC6H, OFEH, OOOH ;

OELTII D_7F

DB

078H, OCCH, OCOH, OCCH, 078H, 018H, OOCH, 078H ;

0_80

DB

OOOH, OCCH, OOOH, OCCH, OCCH, OCCH, 07EH, OOOH ;

0_81

LIIBEL

I NT_IF _1

;

I

D_7C

R BRIIK 0_70

BYTE

01 CH, OOOH, 078H, OCCH, OFCH, OCOH, 078H, OOOH ;

0_82

DB

07 EH, OC3H, 03CH, 006H, 03 EH, 066H, 03 FH, OOOH ;

0_83

DB

OCCH, OOOH, 078H, OOCH, 07CH, OCCH, 07EH, OOOH ;

0_84

DB

OEOH, OOOH, 078H, OOCH, 07CH, OCCH, 07EH, OOOH ;

0_85

DB

030H, 030H, 078H, OOCH, 07CH, OCCH, 07EH, OOOH ;

0_86

DB

OOOH, OOOH, 078H, OCOH, OCOH, 078H, OOCH, 038H ;

0_87

DB

07EH, OC3H, 03CH, 066H, 07EH, 060H, 03CH, OOOH ;

0_88

OCCH, OOOH, 078H, OCCH, 0 FCH, OCOH, 078H, OOOH ;

0_89

OEOH, OOOH, 078H, OCCH, OFCH, OCOH, 078H, OOOH ;

O_BA

OCCH, OOOH, 070H, 030H, 030H, 030H, 078H, OOOH ;

0_8B

07CH, OC6H, 038H, 018H, 0 18H, 0 18H, 03CH, OOOH ;

0_8C

DB

OEOH, OOOH, 070H, 030H, 030H, 030H, 078H, OOOH ;

0_80

DB

OC6H, 038H, 06CH, OC6H, OFEH, OC6H, OC6H, OOOH ;

D_8E

DB

030H, 030H, OOOH, 078H, OCCH, OFCH, OCCH, OOOH ;

0_8F

DB

01 CH, OOOH, OFCH, 060H, 078H, 060H, OFCH, OOOH ;

0_90

DB

OOOH, OOOH, OlFH, OOCH, 07 FH, OCCH, 07 FH, OOOH ;

0_91

DB

03EH, 06CH, OCCH, OFEH, OCCH, OCCH, OCEH, OOOH ;

0_92

DB

078H, OCCH, OOOH, 078H, OCCH, OCCH, 078H, OOOH ;

0_93

DB

OOOH, OCCH, OOOH, 078H, OCCH, OCCH, 078H, OOOH ;

0_94

DB

OOOH, OEOH, OOOH, 078H, OCCH, OCCH, 078H, OOOH ;

0_95

DB

078H, OCCH, OOOH, OCCH, OCCH, OCCH, 07EH, OOOH ;

0_96

DB

OOOH, OEOH, OOOH, OCCH, OCCH, OCCH, 07EH, OOOH ;

0_97

DB

OOOH, OCCH, OOOH, OCCH, OCCH, 07CH, OOCH, OF8H ;

0_98

OC3H, 018H, 03CH, 066H, 066H, 03CH, 018H, OOOH ;

0_99

DB

OCCH, OOOH, oeCH, OCCH, OCCH, OCCH, 078H, OOOH ;

0_9A

DB

o18H, 018H, 07EH, OCOH, OCOH, 07EH, 018H, 018H

0_9B

DB

038H, 06CH, 064H, 0 FOH, 060H, OE6H, OFCH, OOOH ;

0_9C

DB

OCCH, OCCH, 078H, 0 FCH, 030H, 0 FCH, 030H, 030H ;

0_90

DB

oF8H, OCCH, OCCH, 0 FAH, OC6H, OCFH, OC6H, OC7H

;

0_9E

DB

OOEH, 0 1 BH, 0 18H, 03CH, 0 18H, 0 18H, 008H, 070H ;

0_9F

DB

01 CH, OOOH, 078H, OOCH, 07CH, OCCH, 07EH, OOOH ;

O_AO

DB

038H, OOOH, 070H, 030H, 030H, 030H, 078H, OOOH ;

D_Al

DB

OOOH, 01 CH, OOOH, 07BH, OCCH, OCCH, 078H, OOOH ;

0_A2

OOOH, 01 CH, OOOH, OCCH, OCCH, OCCH, 07 EH, OOOH ;

D_A3

OOOH, OF8H, OOOH, OF8H, OCCH, OCCH, OCCH, OOOH ;

0_114

oFCH, OOOH, OCCH, OECH, 0 FCH, ODCH, OCCH, OOOH

;

0_115

03CH, 06CH, 06CH, 03EH, OOOH, 07EH, OOOH, OOOH ;

0_116

DB

P 0_70

;

DB

038H, 06CH, 06CH, 038H, OOOH, 07CH, OOOH, OOOH ;

0_117

DB

030H, OOOH, 030H, 060H, OGOH, OCCH, 078H, OOOH ;

O_AS

DB

OOOH, OOOH, OOOH, 0 FCH, OCOH, OCOH, OOOH, OOOH ;

D_A9

DB

OOOH, OOOH, OOOH, 0 FCH, OOCH, OOCH, OOOH, OOOH ;

D_M

DB

OC3H, OC6H, OCCH, ODEH, 033H, 066H, OCCH, OOFH ;

D_AB

IBM EWialiced Graphlcs Adapter 161

0560
0566
0570
0578
0580
0588
0590
0598
05AO
05A8
05BO
05B8
05CO
05C6
05DO
05D6

05EO
05E8
05FO
05F6
0600
0608
0610
0616
0620
0626
0630
0638
0640
0648
0650
0658
0660
0666
0670
0676
0660
0686
0690
0696
06AO
06A6
06BO
06B8
06CO
06C8
0600
06D8
06EO
06E8
06FO
06F8
0700
0708
0710
0718
0720
0728
0730
0738
0740

CC
C3
CF
16
16
00
00
00
00

OF
C6
03
18
00
33
00
CC
00

22
22
55
55
DB
DB
18
18
16
18
16
16
36
36
00
36
00
18
36
36
36
36
00
36
36
00
36
00
16
00
00
16

88
88
AA
AA
77
EE
18
18
16
18
18
16
36
36
00
36
00
16
36
36
36
36
00
36
36
00
36
00
18
00
00
16

18
00
18
00
00
18
18
16
00
00
18
18
16
18
36
36
36
00
00
36
36
00
00
36
36
36
00
00
36
36
16
00

18
00
16
00
00
18
18
16
00
00
18
18
18
18
36
36
36
00
00
36
36
00
00
36
36
36
00
00
36
36
16
00

36
00
00
18
00
36
36
00
18
00
00
18
00
36
36
36
18
18
18
00
00
18
FF
FF
00
FF
FO
FO
OF
OF
FF
00

36
00
00
16
00
36
36
00
16
00
00
18
00
36
36
36
16
18
18
00
00
16
FF
FF
00
FF
FO
FO
OF
OF
FF
00

00
76
00
CO
00
CO
00
6C
FC
FC
00
70
00
60
00
18
FC

00
00
78
CO
FC
00
FE
00
CC
00
00
00
66
CO
76
00
30

CC DB 37 6F
00 18 16 18
66 CC 66 33
66 33 66 CC
22 88 22 88
55 AA 55 AA
DB EE DB 77
18 18 18 18
18 18 F8 18
F6 18 F6 16
36 36 F6 36
00 00 FE 36
F8 18 F8 18
F6 06 F6 36
36 36 36 36
FE 06 F6 36
F6 06 FE 00
36 36 FE 00
F8 16 F6 00
00 00 F6 18
16 16 1F 00
16 16 FF 00
00 00 FF 18
16 16 1F 18
00 00 F F 00
16 16 FF 16
1F 16 1F 18
36 36 37 36
37 30 3 F 00
3 F 30 37 36
F7 00 F F 00
FF 00 F7 36
37 30 37 36
F F 00 F F 00
F7 OD F7 36
FF 00 FF 00
36 36 FF 00
FF 00 FF 16
00 00 FF 36
36 36 3 F 00
1F 18 1 F 00
1 F 16 1F 16
00 00 3 F 36
36 36 FF 36
FF 18 FF 18
18 18 F8 00
00 00 1 F 16
FF FF FF FF
00 00 FF FF
FO FO FO FO
OF OF OF OF
FF FF 00 00
76 DC C8 DC
CC F8 CC F8
CC CO CO CO
6C 6C 6C 6C
60 30 60 CC
7E D8 D8 08
66 66 66 7C
DC 18 18 18
76 CC CC 78

362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
361
362
363
384
385
386
387
388
369
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
426
429
430
431
432
433
434
435
436
437
436
439
440
441
442
443
444
445
446
447
446
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
466
467

DB

OC3H, OC6H, OCCH,ODBH, 037H, 06FH,OCFH,003H ;

D_AC

DB

018H, 018H, OOOH, 018H, 018H, 018H, 018H, OOOH ;

D_AD

DB

OOOH, 033H, 066H, OCCH, 066H,033H,OOOH, OOOH ;

D_AE

DB

OOOH,OCCH, 066H,033H,066H, OCCH,OOOH,OOOH ;

D_AF

DB

022H, 088H, 022H, 088H, 022H, 088H, 022H, 086H ;

D_BO

DB

055H,OAAH, 055H,OAAH, 055H,OAAH,055H,OAAH ;

D_B1

DB

ODBH,077H, ODBH, OEEH, ODBH, 077H,ODBH,OEEH ;

D_B2

DB

018H, 018H, 018H, 018H, 01 8H, 018H, 018H, 018H ;

D_B3

DB

01 8H, 01 8H, 01 8H, 01 8H, OF8H, 018H ,01 8H, 016H ;

D_B4

DB

01 6H, 01 6H, OF8H, 01 6H, OF6H, 01 8H, 01 8H, 01 6H ;

D_B5

DB

036H, 036H, 036H, 036H, OF6H, 036H, 036H, 036H ;

D_B6

DB

OOOH, OOOH, OOOH, OOOH, OFEH, 036H, 036H, 036H ;

D_B7

DB

OOOH, OOOH, OF8H, 01 8H, OF8H, 01 8H, 01 8H, 01 8H ;

D_B8

DB

036H, 036H, OF6H, 006H, OF6H, 036H, 036H, 036H ;

D_B9

DB

036H, 036H, 036H, 036H, 036H, 036H, 036H, 036H ;

D_BA

DB

OOOH, OOOH, OFEH, 006H, OF6H, 036H, 036H, 036H ;

D_BB

DB

036H, 036H, 0 F6H, 006H, OFEH, OOOH, OOOH, OOOH ;

D_BC

DB

036H, 036H, 036H, 036H, OFEH, OOOH, OOOH, OOOH ;

D_BD

DB

01 6H, 01 6H, OF8H, 0 18H, OF6H, OOOH, OOOH, OOOH ;

D_BE

DB

OOOH, OOOH, OOOH, OOOH, OF6H, 01 8H, 01 8H, 0 18H ;

D_BF

DB

01 6H, 0 16H, 01 8H, 01 6H, 01 FH, OOOH, OOOH, OOOH ;

D_CO

DB

01 6H, 018H, 016H, 016H, OFFH, OOOH, OOOH, OOOH ;

D_C1

DB

OOOH, OOOH, OOOH, OOOH, OFFH, 0 18H, 01 6H, 0 18H ;

D_C2

DB

01 6H, 01 6H, 018H, 01 6H, 01 FH, 01 6H, 01 6H, 01 8H ;

D_C3

DB

OOOH, OOOH, OOOH, OOOH, OF FH, OOOH, OOOH, OOOH ;

D_C4
D_C5

DB

018H, 016H, 01 8H, 018H, OFFH, 016H, 018H, 016H ;

DB

01 6H, 01 6H, 01 FH, 01 8H, 01 FH, 01 6H, 01 6H, 01 6H ;

D_C6

DB

036H, 036H, 036H, 036H, 037H, 036H, 036H, 036H ;

D_C7

DB

036H, 036H, 03 7H, 030H, 03 FH, OOOH, OOOH, OOOH ;

0_C8

DB

OOOH, OOOH, 03 FH, 030H, 037H, 036H, 036H, 036H ;

D_C9
D_CA

DB

036H, 036H, OF7H", OOOH, OFFH, OOOH, DOOH, OOOH ;

DB

OOOH, OOOH, OFFH, OOOH, OF7H, 036H, 036H, 036H ;

O_CB

DB

036H, 036H, 037H, 030H,037H, 036H, 036H, 036H ;

D_CC

DB

OOOH, OOOH, OFFH, OOOH, 0 FFH, OOOH, OOOH, OOOH ;

D_CD

DB

036H, 036H, OF7H, OOOH, OF7H, 036H, 036H, 036H ;

O_CE

DB

01 6H, 016H,OFFH, OOOH, OFFH, OOOH, OOOH, OOOH ;

O_CF

De

036H, 036H, 036H, 036H, 0 FFH, OOOH, OOOH, OOOH ;

D_OO

DB

OOOH, OOOH,OFFH, OOOH, OFFH, 01 6H, 016H, 016H ;

D_D1

OOOH, OOOH, OOOH, OOOH, OFFH, 036H, 036H, 036H ;

D_D2

DB

036H, 036H, 036H, 036H, 03 FH, OOOH, OOOH, OOOH ;

D_D3

DB

01 6H, 01 6H, 0 1 FH, 01 6H, 01 FH, OOOH, OOOH, OOOH ;

0_04

DB

OOOH, OOOH, 01 FH, 016H, 01 FH, 01 6H, 01 6H, 01 6H ;

0_05

DB

OOOH, OOOH, OOOH, OOOH, 03 FH, 036H, 036H, 036H ;

D_D6

DB

036H, 036H, 036H, 036H, 0 FFH, 036H, 036H, 036H ;

0_07

DB

01 8H, 01 8H, 0 F FH, 01 8H, OF FH, 01 8H, 01 8H, 01 8H ;

0_08

DB

01 8H, 01 8H, 01 8H, 0 18H, 0 F8H, OOOH, OOOH, OOOH ;

D_D9

DB

OOOH, OOOH, OOOH, OOOH, 0 1 FH, 01 8H, 01 8H, 01 8H ;

O_DA

DB

OFFH, 0 FFH, 0 F FH, OFFH, OFFH, 0 FFH, OFFH, OFFH ;

O_OB

DB

OOOH, OOOH, OOOH, OOOH, 0 FFH, OFFH, OFFH, 0 F FH ;

O_DC

DB

OFOH, OFOH, OFOH, OFOH, 0 FOH, OFOH, OFOH, OFOH ;

D_DO

DB

OOFH, OOFH, OOFH, OOFH, OOFH, OOFH, OOFH, OOFH ;

D_DE

OF FH, OF FH, OFFH, 0 FFH, OOOH, OOOH, OOOH, OOOH ;

D_DF

DB

OOOH, OOOH, 076H, ODCH, OC8H, OOCH, 076H, OOOH ;

D_EO

DB

OOOH, 076H, OCCH, OF8H, OCCH, OF8H, OCOH, OCOH ;

0_E1

DB

OOOH, OFCH, OCCH, OCOH, OCOH, OCOH, OCOH, OOOH ;

D_E2

DB

OOOH, OFEH, 06CH, 06CH, 06CH, 06CH, 06CH, OOOH ;

D_E3

DB

OFCH, OCCH, 060H, 030H, 060H, OCCH, OFCH, OOOH ;

D_E4

DB

OOOH, OOOH, 07EH, OD8H, OD8H, OD8H, 070H, OOOH ;

0_E5

DB

OOOH, 066H, 066H, 066H, 066H, 07CH, 060H, OCOH ;

0_E6

DB

OOOH, 076H, ODCH, 0 18H, 0 18H, 01 8H, 01 8H, OOOH ;

DJ7

OFCH, 030H, 078H, OCCH, OCCH, 078H, 030H, OFCH ;

D_E8

162 IBM Enhanced Graphics Adapter

0748
0750
0758
0760
0768
0770
0778
0780
0788
0790
0798
07AO
07A8
07BO
07B8
07CO
07C8
0700
0708
07EO
07E8
07fO
07F8
0600

0000
0000
0000

30
38
38
38
EE
lC
78
00
00
06
60
38
38
78
CC

FC
6C
00
6C
00
30
00
00
00
OC
CO
60
00
CC
00

00
00
30
FC
60
FC
18
FC
OE
16
16
06
30
30
00
00
36
00
00
00
00
00
OF
3C
76
00
70
00
00
00
00
00

FC
00
30
00
30
00
30
00
lB
16
18
70
30
00
76
00
6C
00
00
00
00
00
OC
lC
6C
00
16
00
00
00
00
00

C6 FE C6 6C
C6 C6 6C 6C
18 7C CC CC
7E DB DB 7E
7E DB DB 7E

co

F8 CO 60

CC CC CC CC
00 FC 00 FC
FC 30 30 00
18 30 60 00
60 30 16 00
lB 16 16 18
18 16 16 06
00 FC 00 30
DC 00 76 DC
6C 36 00 00
00 16 16 00
00 00 16 00
OC OC EC 6C
6C 6C 6C 00
30 60 76 00
3C 3C 3C 3C
00 00 00 00

488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
516
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
1
2
3
4
5
6
7

D_E9

DB

038H, 06CH, OC6H, OFEH, OC6H, 06CH, 03ijH, OOOH ;

DB

038H, 06CH, OC6H, OC6H,06CH,06CH,OEEH,OOOH ;

D_EA

DB

01CH,030H,018H,07CH,OCCH,OCCH,078H,OOOH ;

D_EB

DB

OOOH, OOOH, 07EH, ODBH,ODBH,07EH,OOOH,OOOH ;

D_EC

DB

006H, OOCH, 07EH,ODBH, ODBH,07EH,060H,OCOH ;

D_ED

DB

038H, 060H, OCOH, OF8H, OCOH, 060H, 038H, OOOH ;

D_EE

DB

078H, OCCH, OCCH,OCCH, OCCH, OCCH, OCCH,OOOH ;

D_EF

DB

OOOH, OFCH, OOOH, OFCH, OOOH, OFCH, OODH, OOOH ;

DJO

DB

030H, 030H, OFCH, 030H,030H,OOOH,OFCH,OOOH ;

D_Fl

DB

060H, 030H, 018H, 030H, 060H,OOOH,OFCH,OOOH ;

D_F2

DB

018H, 030H, 060H, 030H, 016H,OOOH,OFCH,OOOH ;

D_F3

DB

OOEH, 01 BH, 01BH, 018H, 018H,018H,018H,018H ;

D_F4

DB

016H, 016H, 018H,018H, 016H, OD8H, OD8H,070H ;

DJ5

DB

030H, 030H, OOOH, OFCH, OOOH, 030H, 030H, OOOH ;

D_F6

DB

OOOH, 076H, ODCH, OOOH, 076H, ODCH, OOOH, OOOH ;

D_F7

DB

038H, 06CH, 06CH, 038H, OOOH, OOOH, OOOH, OOOH ;

D_F8

DB

OOOH, OOOH, OOOH, 018H, 016H, OOOH, OOOH, OOOH ;

DJ9

DB

OOOH, OOOH, OOOH, OOOH, 016H, OOOH, OOOH, OOOH ;

DJA

DB

OOFH, OOCH, OOCH, OOCH, OECH, 06CH, D3CH,OlCH ;

DJB

076H, 06CH, 06CH, 06CH, 06CH, OOOH, OOOH, OOOH ;

D_FC

DB

070H, 016H, 030H, 060H, 078H, OOOH, OOOH, OOOH ;

DJD

DB

OOOH, OOOH, 03CH, 03CH, 03CH, 03CH, OOOH, OOOH ;

DJE

DB

OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH ;

D_FF

ENDS
END
PAGE,120
SUBTTL END ADDRESS
SEGMENT PUBL I C
CODE
PUBL IC END_ADDRESS
BYTE
LABEL
END ADDRESS
ENDS
CODE
END
CODE

IBM Enhanced Graphics Adapter 163

164 IBM Enhanced Graphics Adapter

Index

A
Attribute Address Register 56
Attribute Controller
description 3
registers 56

B
BIOS
description 4
vectofs with special
meanings 103
BIOS listing 103
Bit Mask Register 54

c
character generator
ROM 1
Character Map Select
Register 21
Clocking Mode Register 19
Color Conlpare Register 48
Color Don't Care Register 53
color fnapping 10
Color Plane Enable
Register 60

compatibility issues 74
configuration switches 80
CRT Controller
descIiption 3
registers 24
CRT Controller Address
Register 24
CRT Controller Overflow
Register 30
Cursor End Register 33
Cursor Location High
Register 35
Cursor Location Low
Register 35
Cursor Start Register 32

D
Data Rotate Register 49
direct drive connector 83
display buffer 4

E
Enable Set/Reset Register 47
End Horizontal Blanking
Register 27
End Horizontal Retrace
Register 29

Index-l

End Vertical Blanking
Register 40

F

I
Input Status Register One 15
Input Status Register Zero 14
Interface 76
feature connector 76

feature connector 76
Feature Control Register 14

L

G
Graphics Controller
description 3
re gisters 45
Graphics 1 and 2 Address
Register 46
Graphics 1 Position
Register 45
Graphics 2 Position
Register 46

H
Horizontal Display Enable End
Register 26
Horizontal Pel Panning
Register 60
Horizontal Total Register 25

Index-2

Light Pen High Register 36
light pen interface 84
Light Pen Low Register 37
Line Compare Register 43

M
Map Mask Register 20
Maximum Scan Line
Register 32
Memory Mode Register 23
Miscellaneous Output
Register 12
Miscellaneous Register 52
Mode Control Register 41,58
Mode Register 50
modes
alphanumeric 8
graphics 8
IBM Color Display 5
IBM Enhanced Color
Display 6
IBM Monochrome
Display 6

o

Graphics Controller 45
Sequencer 18
Reset Register 18

Offset Register 38
Overscan Color Register 59

s
p
Palette Registers 57
Preset Row Scan Register 31
programming
considerations 62
compatibility issues 74
creating a split screen 73
creating a 512 character
set 70
creating an 80 by 43
alphanumeric mode 71
programming registers 62
RAM load able character
generator 69
vertical interrupt feature 72

R
RAM load able character
generator 69
Read Map Select Register 50
registers
Attribute Controller 56
CRT Controller 24
external 12

Sequencer
description 3
registers 18
Sequencer Address Register 18
Set/Reset Register 47
specifications 79
configuration switch
settings 81
configuration switches 80
direct drive connector 83
light pen interface 84
system board switches 79
Start Address High Register 34
Start Address Low Register 34
Start Horizontal Blanking
Register 26
Start Horizontal Retrace Pulse
Register 28
Start Vertical Blanking
Register 39
support logic 4

u
Underline Location
Register 39

Index-3

v
Vertical Display Enable End
Register 38
vertical inteJ.'fupt feature 72

Index-4

Vertical Retrace End
Register 36
Vertical Retrace Start
Register 36
Vertical Total Register 30

---- ---

--_.-

- -- --------~

Extended Monochrome
Graphics Adapter

Personal Computer
Hardware Reference
Library

TNL SN20-9844 (March 1987) to 75X0235

ii Extended Monochrome Graphics Adapter

TNL SN20-9844 (March 1987) to 75X0235

Contents

Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming Model ....................................................
Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Graphic Operation Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Graphic Operation Queue Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connector Specifications .................................................

1

.. 1
.. 5
"
6
.. 8
.. 30
.. 60
" 69

Contents iii

TNL SN20-9844 (March 1987) to 75X0235

iv Extended Monochrome Graphics Adapter

TNL SN20-9844 (March 1987) to 75X0235

Description

Introduction
The Extended Monochrome Graphics Display Adapter attaches to the system I/O channel and
drives a 60 Hz noninterlaced monochrome monitor (1024 X 768 picture elements-pels). The
adapter has a graphic operation processor which provides bit manipulation facilities that
enhance the management and presentation of text, graphics, and image information.
Note: Programming and addressing considerations preclude the use of an Extended
Monochrome Graphics Display Adapter in PC-AT systems.
Advanced features include:
•

A fast graphic operation processor which can do bit block transfers, line draw, image
copy/merge, and rotate

•

Graphic operation command queue with synchronization and branch control for animation

•

Hardware controlled cursor which provides instant cursor movement with no obstruction to
graphic operations

•

An I/O interface which supports direct bit addressability in both horizontal and vertical
(orthogonal) access directions

•

DMA as an alternate controller for image and character transfers from system memory.

Extended Monochrome Graphics Adapter 1

TNL SN20-9844 (March 1987) to 75X0235

Operation
The Extended Monochrome Graphics Display Adapter is characterized by the following key
functional elements.

BAMDA
The display buffer (bit map = 1024 X 1024) is a Bit Addressable Multidimensional Array
(BAMDA) which stores the picture elements (pels) for refreshing the monitor. The buffer is
arranged so that both horizontal and vertical accesses to the array are accomplished on a bit
addressable X , Y field. In addition, the bit length for write operations is variable (from 1 bit up
to 16 bits) in either the X or Y direction. Also logical operators can be specified on write
operations such as 'XOR', 'AND' and 'OR'.

Graphic Operation Processor
A graphic operation processor is used to:
•

Expedite transfers of arbitrary data block sizes from one location to another Bit wise Block
Transfer (Bit BLT) and in addition, perform Boolean operations on the data as it is being
moved

•

Draw geometric objects in the display buffer

•

Transfer image information stored in I/O channel memory.

Asynchronous Graphic Operation Queueing
A graphic operation queue mechanism is implemented in hardware and stored in the hidden
(nondisplayed) area of the bit map. Graphic operation commands are asynchronously linked to
one side of the queue list. The list acts as a first in - first out (FIFO) queue. The graphic
operation processor processes the commands one-by-one from the other side of the queue.
Interrupts, branching, and synchronization are additional control features of the command
queue.

Hardware Cursor
A 48 X 64 bit hardware cursor is combined simultaneously with the video output for each
displayed frame. There are 2 patterns which make up the cursor; the first is 'ANDed' with the
image whereas the second is 'XORed' with the image. These two images, when combined with
the video, allow for a programmable cursor pattern to appear on the screen in the cursor
position.
An X,Y pair of on-board registers enables cursor positioning at an X,Y pel location through
program control.

2 Extended Monochrome Graphics Adapter

TNL SN20-9844 (March 1987) to 75X0235

Extended Monochrome Graphics Display Adapter Diagram

1/0 CHANNEL

CRT REFRESH

...

X ADR

24 BIT ADR
-A.

.

...

~

....
"-'-

...

/

/~

/

V--v

BAMDA
ADDRESS

v
v

..oIL

1024 X 768 PELS
(BAMDA)

~

Video
~

Video Out

Syncs

32K Bytes
HIDDEN AREA

~:~

LFG

.~

/:

..

~tO

/

~

Control

VIDEO DATA

.~

..

.

...

DISPLAY BIT MAP

Y ADR'"

.. :r-:.r-:/.:/.:~

V
V
16 BIT
DATA BUS

.... -:-: .. -:.-: .. :~

-Cursor
- Raster Parameters
-Pointers
-BLT Area

GRAPHIC
OPERATION
[ 1111111111111

Instruction
ROM

Processor

Figure 1. Extended Monochrome Graphics Display Adapter Block Diagram

The Extended Monochrome Graphics Display Adapter consists of 7 major components:
1. The I/O channel interface logic which communicates with the I/O channel and allows the
system to control the display functions.
2.

The BAMDA address logic which controls access to the bit map and converts system
addresses to bit map X and Y coordinates.

3. The BAMDA bit map memory which is divided into a display bit map and a hidden area
memory.

Extended Monochrome Graphics Adapter 3

TNL SN20-9844 (March 1987) to 75X0235

4. The LFG (Logic Function Generator) which performs data conversion functions on the data
stream to and from BAMDA.
5. The video data out logic which transfers the display bit map data image from BAMDA to
the video output connectors and provides video synchronization signals for the monitor.
6. The graphic operation processor which controls all of the adapter functions.
7. The instruction ROM (Read Only Memory) which contains the microcode instructions for
the graphic operation processor.

Command Queue
The command queue is a list of graphic operation commands executed by the graphic operation
processor. The command queue is loaded by the system processor, usually in a linked list. The
processor retrieves these commands and executes them asynchronously from the system.
In its simplest form, the linked list of commands forms a FIFO buffer, with the system loading
commands at one end and the graphic processor executing them at the other end.
Additional features of the command and queue formats allow for branching and interrupting,
thus considerably increasing control flexibility over the simple FIFO approach.

Direct Memory Access (DMA)
The adapter's hardware supports DMA on system DMA channel 7. The DMA graphic
operations are performed during transfers from system memory. Two-dimensional DMA
(TDDMA) cut and paste operations are supported as graphic operations types.

Hardware Cursor
The adapter supports a 48x64 bit hardware cursor which 'AND's and 'XOR's two different
patterns simultaneously to the screen. The cursor patterns are stored in the hidden portion of
the bit map. Memory writes to the appropriate cursor X and Y positioning registers moves the
cursor display position.

4 Extended Monochrome Graphics Adapter

TNL SN20-9844 (March 1987) to 75X0235

Programming Interface
This section describes the programming interface and the key architectural features of the
Extended Monochrome Graphics Display Adapter.

Memory Map
The adapter provides the system processor with direct access to a 1M-pel bit map. A portion of
this bit map is logically dual-ported to the monitor as a video frame buffer.

Bit Addressability
Hardware assist allows the system to address down to the bit level. Bit mask logic allows
selective writing of from 1 to 16 bits automatically. Logical functions such as 'AND', 'OR' or
'XOR' are also specified during the writing of selected bits. Bit alignment, masking and rotation
(barrel shifting) are all performed by hardware within the adapter, thus freeing the system
processor and increasing I/O channel availability.

Orthogonal Access
A unique memory organization and support logic, called Bit Addressable Multidimensional
Array (BAMBA), implements the X, Y bit map. BAMBA supports a mode which directly
addresses 1 to 16 bits in the vertical and the conventional horizontal direction. The vertical
mode also supports bit addressability. All masking and rotation are performed by hardware, thus
allowing high speed graphic operations.

Extended Monochrome Graphics Adapter 5

TNL SN20-9844 (March 1987) to 75X0235

Programming Model
The Extended Monochrome Graphics Display Adapter appears as two separate memory maps to
the system:
•
•

A memory map
A I/O Map.

Memory Map
A 128K-block of memory is addressable as a part of the I/O channel memory map. A
contiguous 96K-byte segment of this block is used as the adapter video frame buffer. The
remainder is hidden memory in the sense that it is not displayable on the monitor. It is,
however, otherwise indistinguishable from the video frame buffer at the programming interface
level.

6 Extended Monochrome Graphics Adapter

TNL SN20-9844 (March 1987) to 75X0235

(1023,0)

Page 0

(0,0)

D80000

D8007E

DISPLAYABLE BIT MAP AREA

768 bits
high

1024 X 768

(0,767)
D97F80

(1023,767)
D97FFE

D98000
(0,768)

D98080
(1023,768)

256 bits
high

HIDDEN BIT MAP AREA
1024 X 256

D9FF80
(0, 1023)

D9FFFE
(1023,1023) INCLUSIVE

Figure 2. 1M-Pel Bit Map Frame Buffer

I/O Map
A small amount of read/write memory (20 bytes) is implemented in the I/O space as control
registers. The I/O registers contain various control and status bits that allow the system to
specify a variety of adapter operating modes.
While all memory implemented in the memory map can be written or read by the system, some
I/O registers and bits within those registers are read only or write only. Read-only registers (or
bits) can be set or reset by the adapter, but can only be interrogated for status by the system.
Other bits can be set or reset by the system, but cannot be directly read.

Extended Monochrome Graphics Adapter 7

TNL SN20-9844 (March 1987) to 75X0235

Addressing
The Extended Monochrome Graphics Display Adapter attaches to the system I/O channel as a
16-bit device. Therefore, the least significant bit (LSB) of the address field is assumed to be 0
and is ignored by the adapter logic. When the adapter accesses (via DMA) system memory, it
always aligns on even byte addresses (LSB is always driven zero).
The adapter is accessed via two separate address ranges. A 12SK-byte range of I/O channel
memory addresses, beginning at X'DSOOOO', implements the bit map and is accessed via I/O
channel memory read/write operations. This area is called 'memory mapped' memory. Ten
control registers are implemented within a 64-byte space called 'I/O mapped memory'. These
locations are accessed via I/O channel read/write operations.

Memory Mapped Memory Addressing
The high order seven bits of the system address select the 12SK-byte region of the I/O channel
memory map assigned to the adapter. This assigned area is X'DSOOOO' to X'D9FFFF'. The
remaining 16 bits directly address words on even byte boundaries (the LSB address bit is always
zero).
Note: The bit naming notation used in the Extended Monochrome Graphics Display Adapter
documentation follows the IBM convention of using bit 0 as the most significant bit. This
convention is used for both data and addresses.

8 Extended Monochrome Graphics Adapter

TNL SN20-9844 (March 1987) to 75X0235

DEVICE
DECODE
1 1 0 1 1

oI

I

I

I

o0
I

I

X WORD
ADDRESS
Bits 17-22

Y BIT
ADDRESS
Bits 7-16

I

718

I

I

I

I

I

I

I

Y BIT
ADDRESS
10 BITS

HORI
VER
ACCESS

1/0 CHANNEL ADDRESS

23

15116

r I

I

0

I

I

I

I

X WORD
ADDRESS
10 BITS

ARRAY X, Y ADDRESS

T
H
/
V
0
I

I

I

LOGIC
FUNCTION

WRITE
MASK
COUNT

000

I

I

I

I

71 8 I

X BIT
ADDRESS
4 BITS

MODE REGISTER

15
I

I

I

I

I

I

Bits
Bits
Bits

00
01-03

HORIZONTAL ACCESS BIT
RESERVED

04-07
08-11
12-15

WRITE MASK COUNT
LOGIC FUNCTION
START BIT DISPLACEMENT

Figure 3. I/O Channel DMA

Access to the bit map is controlled by specifying an even byte address via the I/O channel
address and the mode register contents. The mode register bits are set first via an I/O write
operation.

Extended Monochrome Graphics Adapter 9

TNL SN20-9844 (March 1987) to 75X0235

Word And Bit Addressability
There are 32 modes (16 horizontal modes and 16 vertical modes) of addressing data within the
bit map. One horizontal mode is on a conventional word (16 bit) boundary. The conventional
method accesses 16 bits beginning with bit 0 at the left to bit 15 on the right. The other 15
horizontal modes are arbitrarily bit aligned. Thus, the access overlaps into the next word as
required to reach a full 16 bit access. The addressing mode is determined by the contents of the
start bit displacement field in the mode register. These bits are set via an I/O write to the mode
register (see "Mode Register" on page 24). If this 4-bit field is equal to binary 0, then the access
is on the conventionally aligned even byte boundary. Any other binary value causes the
alignment to be otTset by that number of bits to the right within the the addressed word.
Note that with the start bit displacement field set to all zeros, that bit map access is equivalent
to conventional even word (16 bits) boundary addressing and the bit map appears to the system
as a conventional area of I/O channel memory.

Orthogonal Access
Besides the 16 horizontal addressing modes, the access direction may be specified horizontally or
vertically. The previous discussion on the addressing mode assumed horizontal access because
this is the conventional access direction in bit-mapped display adapters. Setting the mode
register horizontal access bit to otT directs the adapter to access the bit map in the vertical
orientation (down).

Masking
Since all memory accesses are I/O channel limited to 16 bit quantities, regardless of alignment,
masking is provided to allow for a variable number of bits to be written in either access
direction. The mode register contains a field called the write mask count, consisting of a 4-bit
binary value. If the mask count equals X'O', then 16 bits are written. If the mask count equals
X'I', then only one bit is written (the start X, Y bit). If the mask count equals X'2', then two
bits are written.

Logic Functions
During an I/O channel memory write operation, the incoming write data from the I/O data
channel is logically' ANDed', 'ORed' or 'XORed' with the bit map data. The logical function is
specified in the mode register. See "Mode Register" on page 24 for the logical functions
performed.

10 Extended Monochrome Graphics Adapter

TNL SN20-9844 (March 1987) to 75X0235

Memory Mapped Memory Areas
(1023, 0)

(0,0)

D8007E

080000

DISPLAYABLE BIT MAP AREA

768 bits
high

1024 X 768

(1023,767)
097FFE

(0,767)
097F80
768
SCROLL AREA
784
ACTIVE
HARDWARE
CURSOR IMAGE
"AND"I "XOR"

ADDITIONAL CURSOR PATTERNS

848
START---"

FONTS AND STACK AREA
256 bits
high
896
QUEUE LIST AREA
~START

1006
1007

HARDWARE RESERVED SCAN LINE AREA

1008

HARDWARE RESERVED SCAN LINE AREA

1009
SCROLL AREA
(1023,1023) INCLUSIVE

(0, 1023)

Figure 4. 1M-Pel Bit Map Frame Buffer (Suggested Area Usage)

Extended Monochrome Graphics Adapter 11

TNL SN20-9844 (March 1987) to 75X0235

Video Frame Buffer
A 1024 X 768 bit area is displayable from the bit map (1024 x 1024) and is located at the first
768 scan lines. The last 256 scan lines is a hidden area that contains queue lists, cursor patterns,
reserved registers, vertical scroll areas, font areas, and stack areas. The channel addresses
associated with the displayable portion of the bit map start at X'D80000' through X'D97FFF'
(96K-bytes).

Cursor Area
The cursor is 48 X 64 bits and is built from two cursor patterns (an 'AND' pattern and an
'XOR' pattern) which are stored in the hidden bit map area. A reserved cursor save area saves
the original bit map during active display of the cursor. The reserved area is located on scan line
1008 (see "Reserved Register Area" on page 13).
INCLUSIVE
(0.784)

(48, 784)

I

I

I

I

'AND'

'XOR'

PATTERN

PATTERN

48 X 64

I
(0,847)
INCLUSIVE

48

I

I
(48, 847)

Figure 5. Hidden Cursor Patterns

12 Extended Monochrome Graphics Adapter

x

I

64

I

I

TNL SN20-9844 (March 1987) to 75X0235

Reserved Register Area
X Cursor Register

I/O DATA FIELD

Bits 00-05 RESERVED
Bits 06-15 CURSOR (leftmost side of cursor box)

Figure 6. X Cursor Register (Address X'D9F800')

Note: This register is initialized to X'OOOO' with a POR or reset adapter command.
This register is loaded by the system to specify the X position in pels over which the hardware
supported cursor is positioned. The valid range is from 0 (decimal) to 1024 - 48 = 976
(decimal). Out of range values may cause distortion of the displayed image on those scan lines
overlayed by the cursor pattern.

Extended Monochrome Graphics Adapter 13

TNL SN20-9844 (March 1987) to 75X0235

Y Cursor Register

I/O DATA FIELD

Bits 00-05 RESERVED
Bits 06-15 CURSOR LINE (lowest line of cursor box)

Figure 7. Y Cursor Register (Address X'D9F802')

Note: This register is initialized to X'FFFF' with a POR or reset adapter command.
This register is loaded by the system to specify the bottom scan line for the hardware supported
cursor. When the Y cursor register equals 0, the bottom most scan line of the cursor is displayed
on the first scan line on the screen (scan line 0). When the Y cursor register equals
767 + 63 = 830, then the top most scan line of the cursor is displayed on the last displayable
scan line of the screen (scan line 767). All other values of the Y cursor register between the top
and bottom numbers, position the cursor in all the other Y bit positions on the screen. If the Y
cursor register is greater than 831 = 767 + 64, then the cursor is not displayed.

(

14 Extended Monochrome Graphics Adapter

TNL SN20-9844 (March 1987) to 75X0235

Queue Counter Register

I/O DATA FIELD

Bits 00-05 NOT USED
Bits 06-15 COUNTER VALUE (0-1023)

Figure S. Queue Counter Register (Address X'D9FS04')

Note: This register is initialized to X'OOOO' with a POR or reset adapter command.
This register contains the unexecuted 'queue loads' count. The counter is normally incremented
by the system after a new command sequence has been loaded and is ready for execution by the
adapter. It is decremented, conditionally by the adapter, at completion of a command sequence.
As a part of the memory map, it is also fully read/writable by the system. The queue counter
register should only be written when graphic operation processing is stopped (queue counter
equals 0).

Extended Monochrome Graphics Adapter 15

TNL SN20-9844 (March 1987) to 75X0235

Queue Pointer Register

liD DATA FIELD

I I I 71

8

I I I

Figure 9. Queue Pointer Register (Address X'D9F806')

Note: This register is not initialized with a POR or reset adapter command.
The next queued command word location is stored in this register and may be read or modified
via an adapter memory read/write channel operation. During normal graphic operation
processing, this register is updated and used by the graphic operations processor as a program
pointer into the graphic operations command queue. Care should be taken when updating this
pointer.

16 Extended Monochrome Graphics Adapter

TNL SN20-9844 (March 1987) to 75X0235

I/O Address to Equivalent Queue Pointer Value Conversion

DEVICE

Y BIT

X WORD

DECODE

ADDRESS

ADDRESS

Bits 7 -16

Bits 17 -22

1 1 0

1

1

o

0

0
I/O CHANNEL ADDRESS

0

:~
Y BIT

X WORD

ADDRESS

ADDRESS

4 BITS OF X ADDRESS

10 BITS

6 BITS

ARE SET TO ZEROES)

16 BIT QUEUE POINTER

(LEAST SIGNIFICANT

VALU~

o

Extended Monochrome Graphics Adapter 17

TNL SN20-9844 (March 1987) to 75X0235

Examples of queue pointer values:
I/O Channel
Address
Value

Equivalent
Queue Pointer
Value

D988AE
D9AOOO

C457
DOOO
DFE8

D9BFDO
D9COOO
D9C02A
D9EOOO

EOOO
E015

D9FOOO
D9F7FE
D9FFFE

F800
FBFF
FFFF

FOOO

(

18 Extended Monochrome Graphics Adapter

TNL SN20-9844 (March 1987) to 75X0235

Scan Line Register

I/O DATA FIELD

Bits 00-05 NOT USED
Bits 06-15 SCAN LINE (0-1023)

Figure 10. Scan Line Register (Address X'D9F808')

Note: This register is initialized to X'OOOO' with a POR or reset adapter command.
This register contains the next scan line pointer that will be serialized by the video output
circuits. The table below shows the scan line value in relation to the vertical cycle.
Scan Line Values

Relative Vertical Period

000 - 767

Active display

None

Vertical front porch

768 - 770

Vertical Sync

771 - 791

Vertical back porch

792 - 1023

Not valid

Writing the scan line register should be avoided as it causes the vertical cycle to glitch, which
may cause a vertical roll on the display.

Extended Monochrome Graphics Adapter 19

TNL SN20-9844 (March 1987) to 75X0235

Cursor Save Register

DATA FIELD

I I 71

8

I I

Figure 11. Cursor Save Registers (Address X'D9FSOA', 'D9FSOC', 'D9FSOE')

Note: These registers are not initialized with a POR or reset adapter command.
The cursor save registers are used by the graphic operation processor when the display cursor is
active. Bit map data may be lost if these registers are accidentally written.

Mode Shadow Register

DATA FIELD

I I 71

8

I I

Figure 12. Mode Shadow Register (Address X'D9FSI2')

The mode shadow register is updated each time the mode register is written (see "Mode
Register" on page 24). The programmer can read this register to determine the most recent data
written to the mode register. Since the current mode register state affects the reading of the
mode shadow register, the mode register should be set to horizontal access with start bit
displacement set to zero. The mode shadow register is only useful in determining the current
state of logic function bits and the write mask count.

20 Extended Monochrome Graphics Adapter

TNL SN20-9844 (March 1987) to 75X0235

Queue Link Pointer Register

I~--------------~------------------_I
Bits 00-15 RETURN POINTER

Figure 13. Queue Link Pointer Register (Address X'D9F814')

The graphic operations processor uses the queue link register during a branch and link queue
graphic operation. The queue return point is stored in this register. Care should be taken when
writing to this register. See graphic operation command queue for details.

Queue Mode Register

DATA FIELD
15

Bits 00-14 reserved
Bits

15 SELECT FLAG

Figure 14. Queue Mode Register (Address X'D9F816')

The graphic operations processor uses the queue mode register for temporary memory. Care
should be taken when writing to this register. See graphic operation command queue for details.

Extended Monochrome Graphics Adapter 21

TNL SN20-9844 (March 1987) to 75X0235

I/O Mapped Register Addressing
The Extended Monochrome Graphics Display Adapter responds to I/O addresses ranging from
X'ODI0' to X'OD2F' and X'06F3'.
I/O Address

Access

Function Performed

H'06F3'

Write

Interrupt Level 11 Acknowledge

H'ODI0'

Write

Write Mode Register

X'ODI2'

Write

Write Control Register

X'ODI4'

Write

Increment Queue Counter

X'ODI6'

Write

Diagnostic Promlevel Check

X'ODI8'

Write

Reserved

X'ODIA'

Write

Enable Video Data Output

X'ODIC'

Write

Reserved

X'ODIE'

Write

Reserved

X'OD20'

Write

Reset Adapter

X'OD22'

Write

Reset Frame Sync Interrupt

X'OD24'

Write

Reset Raster Operation Interrupt

X'OD26'

Write

Disable DMA Processing

X'OD28'

Write

Enable DMA Processing

X'06F3'

Read

Reserved

X'ODI0'

Read

Reserved

X'ODI2'

Read

Read Status Register

X'ODI4'

Read

Reserved

X'ODI6'

Read

Reserved

X'ODI8'

Read

Reserved

Figure 15 (Part 1 of 2). I/O Address Function Table

22 Extended Monochrome Graphics Adapter

TNL SN20-9844 (March 1987) to 75X0235

I/O Address
X'ODIA'

Access

Function Performed

X'ODIC'
X'ODIE'
X'OD20'
X'OD22'

Read
Read
Read
Read
Read

Disable Video Data Output
Reserved

X'OD24'
X'OD26'
H'OD28'

Read
Read
Read

Reserved
Reserved

Reserved
Reserved
Reserved

Reserved

Figure 15 (Part 2 of 2). I/O Address Function Table

Interrupt Acknowledge Register (Address X'06F3')
This is a write-only register and the data is of no significance. This address signals that a
pending interrupt was serviced and re-enables the adapter interrupt request pulse generating
circuit.

Reset Frame Sync Interrupt Register (Address X'OD22')
This is a write-only register and the data is of no significance. This address resets any pending
frame sync interrupt (interrupt level 11). Interrupt 11 is a shared interrupt.

Reset Graphic Operation Interrupt Register (Address X'OD24')
This is a write-only register and the data is of no significance. This address resets any pending
graphic operation interrupt (interrupt level 11). Interrupt 11 is a shared interrupt.

Extended Monochrome Graphics Adapter 23

TNL SN20-9844 (March 1987) to 75X0235

Mode Register
1/0 DATA FIELD

0

I

TI

I

I

I

II

I I

I 71

15

8

"

I

I

I

I

"

I

1 I
Bit

00

HORIZONTAL ACCESS BIT

Bits 01 03 RESERVED (000)
Bits 04 07 WRITE MASK COUNT
Bits 08 11 LOGIC FUNCTION
Bits 12 15 START BIT DISPLACEMENT

Figure 16. Mode Register (Address X'ODI0')

Note: This register is initialized to X'8090' with a paR or reset adapter command.
This is a write-only hardware register. Its shadow is stored in mode shadow register which is
described in "Mode Shadow Register" on page 20. The mode register is loaded to X'8090' when
powered on or reset. This mode permits the adapter to accept 16-bit horizontal BAMBA
accesses on a 16-bit boundary. The logic function only effects write operations and replaces the
destination data bits with the I/O channel data bits.
With the horizontal access bit in an active state, a horizontal access starting at the X, Y address
represented by the channel address and the start bit displacement (the 'start bit') occurs. The
access is a string of 1 to 16 bits to the right of the 'start bit'. With the horizontal access bit in an
inactive state, the access is a string of 1 to 16 bits down from the 'start bit'. During a write
operation, the write mask count specifies the number of bits as shown in the chart below. The
logical function, also shown below, specifies the action taken between the write data applied on
the I/O channel and the existing data in the bit map.
The write mask count and logic function bits only affect write operations. The horizontal access
and start bit displacement bits affect both read and write operations on the adapter bit map
including the reading and writing of the various control registers. The programmer must be
aware that, to correctly read the X cursor, Y cursor, queue counter, queue pointer, scan line,
and mode shadow registers, the horizontal access bit must be set to 1 and the start bit
displacement bits must all be set to O. To write the appropriate registers, the mode register
should be set to the reset state which is X'8090'.

24 Extended Monochrome Graphics Adapter

TNL SN20-9844 (March 1987) to 75X0235

Write
Count
(Hex)

Number
of Bits
Written

0

16

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

A

10

B

11

C

12

D

13

E

14

F

15

Figure 17. Write Count Mask

Extended Monochrome Graphics Adapter 25

TNL SN20-9844 (March 1987) to 75X0235

Logical
Functional
Value

Write Function Performed

0

Replace destination with zeros
I/O data 'AND' destination
, I/O data 'AND' destination
Reserved
Reserved
Reserved
Reserved
Reserved
I/O data 'AND', destination
Replace destination with I/O data
I/O data 'XOR' destination
I/O data 'OR' destination
Reserved
Reserved
,1/0 data 'OR' ,destination
Replace destination with ones

1
2
3
4
5

6
7
8
9

A
11
12
13
14
15

Note: Destination refers to the bit map data.
Figure 18. Logical Functions

26 Extended Monochrome Graphics Adapter

TNL SN20-9844 (March 1987) to 75X0235

Control/Status Register
I/O DATA FIELD

T-- -- ---

I

I

7

18 I

I

I

~

Bit 00

FRAME SYNC INT ENABLE (Read/Write)

Bit 01

GRAPHIC OP INTERRUPT ENABLE (Read/Write)

Bit 02

FRAME SYNC INTERRUPT STATUS (Ready Only)

Bit 03

GRAPHIC OP INTERRUPT STATUS (Read Only)

Bit 04

VIDEO ENABLE (Read)

Bit 05

BLACK ON WHITE BACKGROUND (Read/Write)

Bit 06

HORIZONTAL SYNC (Read Only)

Bit 07-15 RESERVED

Figure 19. Control/Status Register (Address X'ODI2')

Note: This register is initialized to X'OOXX' with a POR or reset adapter command.
This control/status register may be read or written by the system processor. The control/status
register contains the bits which enables processing, interrupts, and video. All bits in this register
are normally initialized at power on to the ofT or 0 state.
Frame Sync Int Enable (bit 0)
This bit, when active, places any frame sync interrupt on the channel interface
interrupt level 11. When inactive, no frame sync interrupts are placed on the
channel and the frame sync interrupt latch is reset.
Graphic Operation Interrupt Enable, (bit 1)
This bit, when active, places any graphic operations interrupt on the channel
interface interrupt level 11. When inactive, graphic operations interrupts are
not placed on the channel and the graphic operations interrupt latch is reset.
Status (bits 2 and 3)
The frame sync interrupt status and the graphic operations interrupt status bits
are read-only bits and indicate if these interrupts are active.

Extended Monochrome Graphics Adapter 27

TNL SN20-9844 (March 1987) to 75X0235

Video Enable (bit 4)
This bit, when active, indicates that video data from the bit map is being
supplied to the monitor. If the bit is inactive, the video data from the bit map
is not being supplied to the monitor. The video enable signal is manipulated
via graphic operation types and I/O commands. The video enable signal
should be activated after a POR or a reset adapter command.
Black on White Background (bit 5)
When active, inverts all video data going from the bit map to the video drive
circuits. This gives an effect of a white background. Thus a clear screen
operation (set bit oft) or a disable video turns the screen white. When this bit
is inactive, a white on black background is displayed. Therefore an off pel in
the bit map corresponds to an off pelon the screen and the disabled video
turns the screen black.
Horizontal Sync (bit 6)
This bit is for diagnostics and indicates the horizontal cycle is working.

Increment Queue Counter Register (Address X'OD14')
This is a write only register and the data is of no significance. A write to this register increments
the command queue counter by one. The graphic operation processor decrements the queue
counter with a flag bit in the execute command word. The graphic operation processor polls the
queue counter to see if any graphic operations are pending execution on the queue. If the queue
counter is not zero, processing of the queue begins or continues. The maximum number of
increments before a decrement occurs is 1023. If count is incremented past 1023, then 1024
graphic operations queue loads are not executed.

Disable Video Data Output (Address X'ODIA')
A read operation from this I/O address disables the adapter video data output.

Enable Video Data Output (Address X'ODIA')
A write operation to this I/O address enables the adapter video data output to the monitor. Data
written to this address is ignored.

28 Extended Monochrome Graphics Adapter

TNL SN20-9844 (March 1987) to 75X0235

Reset Adapter Register (Address X'OD20')
Note: After turning system power on, a write to this address is necessary to reset the adapter.
This is a write-only register and the data is of no significance. A write to this register resets the
adapter and acts just like the I/O channel signal 'Reset Drive'. This command initializes the
following registers:
Register Name
X cursor register
Y cursor register
Queue counter register
Scan line register
Mode shadow register
Mode register
Control/status register

Register Addr
D9F800
D9F802
D9F804
D9F808
D9F812
ODIO I/O
OD12 I/O

Register Data
0000
FFFF
0000
0000
8090
8090
0000

Graphic operation processing and command queue processing are stopped when this command
is executed. Also, the vertical and horizontal sync cycles are interrupted and video is disabled.

Disable DMA Processing (Address X'OD26')
This I/O address allows the system to disable DMA processing by the adapter. Data written to
this address is ignored.

Enable DMA Processing Register (Address X'OD28')
This I/O address allows the system to enable DMA processing by the adapter. Data written to
this address is ignored.

Extended Monochrome Graphics Adapter 29

TNL SN20-9844 (March 1987) to 75X0235

Graphic Operation Commands
Besides allowing direct bit manipulation of the video frame buffer by the system processor, the
Extended Monochrome Graphics Display Adapter can process commands which are received
from the system and stored in a command queue. These commands are loaded into the adapter
hidden bit map area as a linked-list structure. The graphic operation processor, which controls
the command list execution, recognizes three basic command word types:
•

Load register command

•

Branch command

•

Execute command.

The load register command sets values into the various graphic operation processor registers.
Normally, commands are fetched and processed from sequential 16-bit memory addresses. The
branch command allows the list to be scattered throughout memory. Notice all command words
are aligned on 16-bit word boundaries.
The execute command identifies the graphic operation type and contains flag bits that control
and synchronize the queue operation.

Graphic Operation Command Queue
Commands for the graphic operations processor are loaded into a command queue by the
system and sequentially executed (subject to branching types of commands) by the adapter. The
command queue is represented by three elements:
•

The actual memory locations used to hold the list of commands and referred as the queue

•

The queue pointer which serves to hold the address within the queue of the next command
word to be processed

•

The queue counter which provides the synchronization and interlocking between the graphic
operation processor and the system processor.

The queue consists of memory locations within the hidden bit map and is set up by the system
processor as a linked list of graphic operation commands via memory write cycles over the I/O
channel. The contents of any location within the queue may be accessed via a memory read
cycle.
The queue pointer appears as a memory location within the I/O channel memory map and may
be updated via a I/O channel memory write cycle.
The queue counter also appears as a memory location within the I/O channel memory map and
may be updated via a I/O channel memory write cycle.

30 Extended Monochrome Graphics Adapter

TNL SN20-9844 (March 1987) to 75X0235

Normal operation of the command queue begins with the system loading a command or list of
commands into the queue. This group is called a queue load. The last command is an 'Execute'
instruction which contains a bit known as the decrement queue counter flag. This flag tells the
graphic operation processor to decrement the queue counter register by one after the execution
of the queue load is complete. If this is the first or only queue load, the queue pointer points to
the first queue load command word.
Initially assume that the queue counter register is 0. Following the complete loading of the
queue load (and the queue pointer if necessary), the system processor performs an I/O Write
cycle to the increment queue counter register, causing the queue counter to be incremented by
one. Once the queue counter has incremented past 0, the graphic operation processor begins
fetching command words from the queue, starting at the address designated by the queue
pointer register. As each command is processed, the queue pointer register is either decremented
by one or loaded with a new queue location (branch address). The queue pointer always points
to the next command word in the queue.
If the processed command word is an 'execute' type and the decrement queue counter flag is set,
then the queue counter is decremented on completion of the graphic operation. If the processed
command word is either a register load or branch type, or if the decrement queue counter flag is
not set, then the queue counter is not changed by the graphic operation processor.

As queue loads are added to the queue by the system processor, the queue counter is
incremented. As queue loads are completed, the counter is decremented. When the queue
counter is decremented to zero, graphic operation processing is halted.

Extended Monochrome Graphics Adapter 31

TNL SN20-9844 (March 1987) to 75X0235

Graphic Commands
Execute Command
I/O DATA FIELD

oI

I

I

I

I

I I I
I __

I

I

718 I

15

I

I

I

I

I

I

II
Bits 00-03 EXECUTE DECODE
( 1 10 1 )
Bit 04
DECREMENT QUEUE COUNTER FLAG
Bit 05

GRAPHIC OP INTERRUPT FLAG

Bits 06-11 GRAPHIC OP TYPE
Bits 12-15 GRAPHIC OP LOGIC FUNCTION (subtype)

Figure 20. Execute Command Word (Address X'D9CXXX')

For each graphic operation there is one execute command word. It is designated via the execute
decode B'llOl '.
The execute command word contains a decrement queue counter flag. When this flag is active,
it designates queue load sequence end. If the flag is inactive, more graphic operations must
follow. Before incrementing the queue counter, a complete queue load sequence (decrement
queue counter flag) must be loaded somewhere in the queue list structure.
The graphic op interrupt flag bit, if active, sets the graphic operation interrupt latch at the
completion of the graphic operation. This action can be observed via the graphic operation
interrupt status (bit 3) in the status register. The only way to reset the graphic operation
interrupt latch is via an I/O channel write of a reset graphic operations command or a reset
adapter command. If the graphic operation interrupt enable bit (bit 1) is active in the control
register and the graphic operation interrupt latch is active, then an active interrupt is driven on
the I/O channel. Disabling graphic operation interrupts does not reset the interrupt latch.
The graphic operation type field specifies different graphic operation types. The graphic
operation logic function field specifies a subtype within a graphic operation sequence. See
graphic operations definitions for specifics about each graphic operations type and subtype.

32 Extended Monochrome Graphics Adapter

TNL SN20-9844 (March 1987) to 75X0235

Bits
12-15

Logic Function
(Subtype)

0

Set all bits to .0.

1
2

+ Operand A and + Operand B
+ Operand A and -Operand B

3

Pass through Operand A

4

All zero's

5
6

+ Operand A and + Operand B
+ Operand A and -Operand B

7

Pass through Operand A

8

-Operand A and

9
A
B

Pass through Operand B (test)

+ Operand B

C

+ Operand A xor + Operand B
+ Operand A or + Operand B
-Operand A or + Operand B

D

Pass through Operand B (test)

E

-Operand A or -Operand B

F

Set all bits to 1.

Figure 21. Graphic Operation Functions

Extended Monochrome Graphics Adapter 33

TNL SN20-9844 (March 1987) to 75X0235

Branch Command

I/O DATA FIELD

I I I 71

I

8

I I

I
Bits 00-02 BRANCH DECODE
( 1 11 )
Bit 00-15 BRANCH (Absolute) ADDRESS FIELD (16 bits)

Figure 22. Branch Command Word

The branch address is 16 bits. The 10 high order bits (including the 3 branch decode bits) of the
branch command word correspond to a Y address.
Y ADDRESS (10 bits)

X ADDRESS (10 bits)

I I 10 10 10 10

I

I

16 Bits
Branch Command Word

~

Figure 23. Branch Command Word Address Field

The other 6 (low order) bits of the branch command word form the most significant 6 bits of a
10-bit X address with the 4-least significant bits assumed to be all O's. Therefore, branching is
restricted to 16-bit word boundaries (4 LSB's of X address are all O's) and the lower 1/8 of the
bit map (Y address greater than or equal X'380', scan lines 896-1023).

34 Extended Monochrome Graphics Adapter

TNL SN20-9844 (March 1987) to 75X0235

Register Load

1/0 DATA FIELD

oI

I

I

I

I

I

I L~I

I

1

7 8
1

15
1

I

I

I

I

I

1

I

I

Bits 00-03 REGISTER DECODE
0000 = = = =>
0001 = = = =>
0010 ====>
0011 = = = =>
0100 ====>
0101 = = = =>
0110 = = = =>
0111 = = = =>
1000 = = = =>
1001 ====>
1010 = = = =>
1011 ====>

Load Graphic OP Processor Register 0
Load Graphic OP Processor Register 1
Load Graphic OP Processor Register 2
Load Graphic OP Processor Register 3
Load Graphic OP Processor Register 4
Load Graphic OP Processor Register 5
Load Graphic OP Processor Register 6
Load Graphic OP Processor Register 7
Load Graphic OP Processor Register 8
Load Graphic OP Processor Register 9
Load Graphic OP Processor Register A
Load Graphic OP Processor Register B

(RO)
(R1)
(R2)
(R3)
(R4)
(R5)
(R6)
(R7)
(R8)
(R9)
(RA)
(RB)

Bit 04,05 reserved (set to 0)
Bits 06-15 PARAMETER

Figure 24. Register Load Command Word

Bits 0-3 specify 1 of 12 graphic operation registers. Different graphic operations require different
registers to be loaded.

Extended Monochrome Graphics Adapter 35

TNL SN20-9844 (March 1987) to 75X0235

Rectangular Destination Only Graphic Operation Types
A rectangular region of pels (destination) is operated on by the graphic operation processor in
the bit map. The graphic operation either writes or read-modify-writes the destination specified.
The parameters specifying the rectangular destination are the coordinates of the lower right
corner point (X, Y exclusive) and the size (DX, DY) of the rectangular region.
Note: The microcode register ending conditions are defined for graphic operation types
X'2F','35','36','2C','2D', and '2E' only. All other graphic operation types have register ending
conditions which are not defined.

---JI}-

'--_ _ _ _ _
D_E_ST_I_N_A_TI_O_N_ _ _ _ _

DELTA Y

+1

~

IDYl

(X,Y) LOWER RIGHT CORNER

I

(exclusive)

'--------~-------~

DELTA X

+

1 = (OX)

Notes:
1. The DX & DY variables represent the actual number of pels written.
2.

The X & Y variables are the right-bottom corner pel exclusive.

36 Extended Monochrome Graphics Adapter

TNL SN20-9844 (March 1987) to 75X0235

The X, Y, DX and DY parameters are specified in the queue load. Not all parameters need be
specified for each graphic operation. Only the parameters that change from graphic operation to
the next need be specified. See register contents at completion of graphic operation. An example
of a queue load that clears a 1024 x 768 pel screen is shown below. Note that a hex value of
'000' represents a value of 1024 pels both for X and DX. The same is true for Y and DY.
Queue
Address

Queue
Data

Action By
Queue Processing

Register
Start

Register
Min Max

Reg
End

Que Ptr

X'7000'

Load X into R 7

X= 1024

1 1024

X

Que Ptr-l

X'6300'

Load Y into R6

Y=768

1 1024

Y

Que Ptr-2

X'9000'

Load DX into
R9

DX= 1024

1 DX=
X

DX

Que Ptr-3

X'8300'

Load DY into
R8

DY=768

1 DY=
Y

DY

Que Ptr-4

X'D2FO'

Execute Graphic
Operation

Note: Unpredictable results might occur if DX > X or DY > Y.

Extended Monochrome Graphics Adapter 37

TNL SN20-9844 (March 1987) to 75X0235

Write Destination (X'2F')
This graphic operation type writes a rectangular area of pels in the bit map. Three subtypes are
specified via the LF (graphic op logic function) bits as listed below.
Rectangular fill replace off:
Rectangular XOR destination:
Rectangular fill replace on:

°

LF = 0, Set destination to
LF = 9, Msk = destination (Reverse video)
LF = F, Set destination to 1

'--_ _ _C_L_E_A_R_C_H_A_R_A_C_T_ER_Ll_N_E_ _ _ _

}IOYI

= 20

(X, V) LOWER RIGHT CORNER

'--_ _ _ _ _ _~----------'I

(768,20) EXCLUSIVE

' - - - - - - - - - - - - ( D X ) =768

Figure 25. Clear Character Line (X = 768,Y = 20,DX = 768,DY = 20)

38 Extended Monochrome Graphics Adapter

TNL SN20-9844 (March 1987) to 75X0235

Read Modify Write Destination (X'2F')
This graphic operation type read-modify-writes a rectangular area of pels in the bit map. Only
one subtype is specified via the LF bits as listed below.
Rectangular XOR Destination

LF = 9,'" Destination = Result Destination

R_EV_E_R_S_E_V_I_D_EO_C_H_A_RA_C_T_E_R_L_IN_E_~}

......_ _

~

lOY) " 20

(X, Y) LOWER RIGHT CORNER
(768,20) EXCLUSIVE

_ _ _ _ _ _--,-_ _ _ _ _ _----,I

~--------(DX)=768

Figure 26. Reverse Video Character Line (X = 768,Y = 20,DX = 768,DY = 20)

Extended Monochrome Graphics Adapter 39

TNL SN20-9844 (March 1987) to 75X0235

Rectangular Source and Destination Graphic Operation Types
Two rectangular regions of pels (source-destination) are operated on by the graphic operation
processor. The graphic operation reads the source and either read-modify-writes or writes the
destination. The source data is to either replace the destination data, as in a copy operation or,
merge data as in an AND, OR or XOR merge operations.
These graphic operation types require both a source and a destination X, Y (:lddress pair. The
address pair depicts the source corner point (XS,YS) and the destination corner point (XD,YD).
The size (DX,DY) of the rectangle must also be specified.
The queue load for these graphic operation types is up to seven 16-bit words as shown below.
The queue load below represents a rectangular area of pels being moved down by one pel. The
rectangular area defined is 1024 x 767.
Queue
Address

Queue
Data

Action By
Queue Processing

Que Ptr

X'7000'

Que Ptr-l
Que Ptr-2

Register
Min Max

Load XD into R 7

Register
Start
XD= 1024

1

1024

X'A300'

Load YD into RA

YD=768

1

1024

Load XS into R5
Load YS into R4

XS = 1024

1

1024

Que Ptr-3

X'5000'
X'42FF'

YS = 767

1

1024

Que Ptr-4

X'9000'

Load DX into R9

DX= 1024

1

DX=X

Que Ptr-5

X'02FF'

Load DY into RO

DY=767

1

DY=Y

Que Ptr-6

X'D300'

Execute copy/scroll

Note: Unpredictable results might occur if DX > XD,DY > YD,DX > XS or DY > YS.

40 Extended Monochrome Graphics Adapter

TNL SN20-9844 (March 1987) to 75X0235

Rectangular Copy/Merge (X'30')
The rectangular copy/merge graphic operation reads a source rectangle defined by XS, YS, DX
and DY writes a destination rectangle defined by XD, YD, DX and DY as shown below. Any
type of overlapping source and destination combinations are allowed. The YD register is
preserved during graphic operation type X'30'.

DESTINATION RECTANGLE
exclusive (XD, YD)

] - DELTAY
SOURCE RECTANGLE

+1

~

IDYl

~----------------------------~
(XS, YS) LOWER RIGHT CORNER

I exclusive

~--------------T-------------~

DELTA X

+ 1 = (OX)

Figure 27. Copy Overlapped Character Line

To achieve a rectangular copy, the logical function (subtype) must be set to X'9'.
In consecutive repeated copy operations (graphic operations type 30) to locations with a
constant destination Y coordinate, the destination Y coordinate need only be specified in the
first queue load since its entry value is preserved. This speeds up the copy execution since only
6 parameters instead of the usual 7 need to be processed. An example of a general use for this
preservation of the destination Y value is in the copying of character images from the display
hidden area to a single horizontal character line in the active display area.

Extended Monochrome Graphics Adapter 41

TNL SN20-9844 (March 1987) to 75X0235

DESTINATION RECTANGLE

~_____________e_xc_lu_s_iV_e_(X_D_'_Y_D_)____~

l}

(DY)=20

SOURCE RECTANGLE
(XS, YS) LOWER RIGHT CORNER
I exclusive
~--------------r-------------~

(OX) = 700

Figure 28. Copy Character Line (XD = 768, YD = 20, XS = 800, YS = 30, DX = 768, YD = 16)

To achieve a merge operation while copying the source data one of these subtypes must be
specified.
Rectangular Merge And:
Rectangular Merge And.,:
Rectangular Merge., And:
Rectangular Merge XOR:
Rectangular Merge OR:
Rectangular merge .,OR:
Rectangular merge .,OR.,:

LF = 1, Source & destination = Result destination
LF = 2, Source &., destination = Result destination
LF = 8, ., Source & destination = Result destination
LF = A, Source XOR destination = Result destination
LF = B, Source OR destination = Result destination
LF = C, ., Source OR destination = Result destination
LF = E, ., Source OR ., destination = Result
destination

While copying the source, data is merged with the destination via subtype specification.

42 Extended Monochrome Graphics Adapter

TNL SN20-9844 (March 1987) to 75X0235

DESTINATION GRAPHIC WINDOW

(XD, YD) LOWER RIGHT CORNER
exclusive

S_O_U_R_C_E_T_E_X_T_W_I_N_D_O_W_ _ _ _....... }

I...-_ _ _ _

DELTA Y + 1

~

IDYl

(XS,YS) LOWER RIGHT CORNER
exclusive

I
I...---------~--------------

DELTA X

+1=

(oX)

Figure 29 . 'And' a Test Source Window to a Graphic Destination Window.

Extended Monochrome Graphics Adapter 43

TNL SN20-9844 (March 1987) to 75X0235

Rectangular Copy/Merge Rotate

+ 90 (X'31')

This graphic operation type is similar to the rectangular copy/merge graphic operation. The
destination and source rectangular areas should not overlap.

DESTINATION

(XD, YD) LOWER RIGHT CORNER
exclusive

DELTA Y

+

1 = IDY)

SOURCE

(XS, YS) LOWER RIGHT CORNER
I exclusive
~--t---~

' - - - - - - - - - - DELTA X

Figure 30. Rotate Window

+ 90 Degrees

44 Extended Monochrome Graphics Adapter

+1=

(DX)

TNL SN20-9844 (March 1987) to 75X0235

Rectangular Copy/Merge Rotate -90 (X'32')
This graphic operation type is similar to the rectangular copy/merge graphic operation. The
destination and source rectangular areas should not overlap.

DESTINATION

(XD, VD) LOWER RIGHT CORNER
exclusive

DELTA V

+ 1 = mv)

SOURCE

(XS, VS) LOWER RIGHT CORNER
L...---r---....J

exclusive

1

1...-_ _ _ _ _ _ _ _

DELTA X

+1=

(OX)

Figure 31. Rotate Window -90 Degrees

Extended Monochrome Graphics Adapter 45

TNL SN20-9844 (March 1987) to 75X0235

Rectangular Copy/Merge 180 X Axis Symmetry (X'33')
This graphic operation type is similar to the rectangular copy/merge graphic operation. The
destination and source rectangular areas should not overlap.

DESTINATION

(XD, YD) LOWER RIGHT CORNER
exclusive

----.11 ] - DELTA Y + 1

L...-_ _ _ _ _ _
S_O_U_R_C_E_ _ _ _ _

~

IDYl

(XS, YS) LOWER RIGHT CORNER
exclusive

I
L...-_ _ _ _ _ _ _~~------~

DELTA X

Figure 32. Flip Window 180 Degrees Along the X Axis

46 Extended Monochrome Graphics Adapter

+1=

(oX)

TNL SN20-9844 (March 1987) to 75X0235

Rectangular Copy/Merge 180 Y Axis Symmetry (X'34')
This graphic operation type is similar to the rectangular copy/merge graphic operation. The
destination and source rectangular areas should not overlap.

DESTINATION

(XD, YO) LOWER RIGHT CORNER
exclusive

---JI}

S_O_U_R_CE_ _ _ _ _ _

I...-_ _ _ _ _ _

DELTA Y

+1

~

IDYl

(XS, YS) LOWER RIGHT CORNER

1...-_ _ _ _ _ _- ,_ _ _ _ _ _ __

I exclusive

DELTA X

+ 1 = (OX)

Figure 33. Flip Window 180 Degrees Along the Y Axis

Extended Monochrome Graphics Adapter 47

TNL SN20-9844 (March 1987) to 75X0235

Vector Draw Graphic Operations
Vector Draw (X'35')
This graphic operation draws a straight line contained within the bit map (1024 x 1024). The
line is defined by four parameters, X from, Y from, X to, and Y to. The logical operators on the
bit map for the line draw are set line on (F), set line off(O), and 'XOR' line (A).
Example: Draw a Line From (48,256) To (16,512).

Que Ptr

Queue
Data
X'1030'

Action By
Queue Processing
Load X from R 1

Register
Start
Xl =48

Que Ptr-1

X'0100'

Load Y from RO

Que Ptr-2
Que Ptr-3
Que Ptr-8

X'5010'
X'6200'
X'D35F'

Load X to R5
LOAD Y to R6
Execute Line Draw

Y1 = 256
X2= 16
Y2 = 512
Set line on

Queue
Address

Register
Min Max

Reg
End

o 1023
o 1023
o 1023
o 1023

X to
Y to

No decrement

At the completion of the line draw, the X,Y 'to' coordinate is saved in the X,Y 'from'
coordinate registers. This permits the next graphic operation to use this saved X, Y 'to'
coordinate information for the next X,Y 'from' coordinate with out having to reload (polyline)
as shown below.
Example: Continue Drawing a New Line From (16,512) to (256,512)
Queue
Address
Que Ptr
Que Ptr-1
Que Ptr-2

Queue
Data
X'5100'
X'6200'
X'D35F'

Action By
Queue Processing

Register
Start

Register
Min Max

Load X2 into R5
Load into R6
Execute line draw

X2=256
Y2 = 512
Set line on

o 1023
o 1023

Note: X,Y 'to' coordinate is saved in the X,Y 'from' registers.

48 Extended Monochrome Graphics Adapter

No decrement

TNL SN20-9844 (March 1987) to 75X0235

Vector Draw With Ending Null (X'36')
This graphic operation functions in exactly the same way and with the same parameters as the
preceding vector draw graphic operation type X'3S'. The only exception being that the ending
pel of the line is not written to the bit map. Used for polyline XOR.

Relative Draw With Ending Null (X'2C')
The relative draw with ending null graphic operation allows the user to specify the next vector
to be drawn as a delta or increment from the last end point specified and end with a null point.
Logic functions are the same as type X'3S'.
Example: Relative Draw with Ending Null (Xl and YI values are from current contents of RI
and RO).
Queue
Address

Queue
Data

Action By
Queue Processing

Que Ptr

X'SIOO'

Load DX into RS

Que Ptr-l

X'6200'

Load DY into R6

Que Ptr-2

X'D2CO'

Execute relative draw with
ending null.

Function

RS = Xl
R6 = YI

+ DX
+ DY

Draw vector from (X I, Y I)
to (Xl + DX,YI + DY)
w/END NULL

Extended Monochrome Graphics Adapter 49

TNL SN20-9844 (March 1987) to 75X0235

Relative Draw (X'2D')
The relative draw graphic operation operates in the same manner as the graphic operation type
X'2C' above, except the drawn vector does not end with a null.
Example: Relative Draw (Xl and YI values are from the current contents of RI and RO).
Queue
Address
Que Ptr
Que Ptr-l
Que Ptr-2

Queue
Data
X'5100'
X'6200'
X'D2DO'

Action By
Queue Processing
Load DX into R5
Load DY into R6
Execute relative draw.

Function

R5
R6

=
=

Xl
YI

+
+

DX
DY

Draw vector from (XI,YI)
to (Xl + DX,YI + DY)

Relative Move to (X'2E')
The relative move to graphic operation allows the user to add a delta or increment to the last
start point coordinates specified rather than to require that new absolute coordinates to be
specified.
Example: Relative Move To (Update the contents of RI and RO for new Xl and YI).
Queue
Address
Que Ptr
Que Ptr-l
Que Ptr-2

50

Queue
Data
X'2100'
X'6200'
X'D2EO'

Action By
Queue Processing
Load DX into R2
Load DY TO > R6
Execute relative move to
No vector is drawn, only
X I and Y I are updated
for later use.

Extended Monochrome Graphics Adapter

Function
R2
R6

=
=

Xl + DX
YI + DY

TNL SN20-9844 (March 1987) to 75X0235

TDDMA I/O Copy Graphic Operation
TDDMA Cut/Paste From I/O Channel Memory (X'37')
Valid subtypes for graphic operation type X'37' are 1, 2, 8, 9, A, B, C, and E.
Example: Copy an Image From I/O Channel Memory Starting at Address X'1012'.
Bit 4 of the starting data word (X' 1012') is the upper left corner of the rectangular copied. The
image array starts at address X' 1000'and ends at X' 107E'. The destination rectangle is located at
X = 11 and Y = 12 (upper left hand corner X,Y). The width (DX) = 31 bits. The height (DY)
= 3 bits.
The skip value is the number of data words in each image array width line that are within the
height of the desired rectangle, but do not contain data within the width of the desired rectangle
and thus are skipped in the DMA transfer process.
The Skip value is calculated as follows:
In this example: AS = 128 x 8 = 1024, DW = DX = 31, and Bit Offset = 4.
Thus Skip = (Ceil( (AS - 15) - (DW - (16 - Bit Offset) ) ) /16) )-1
Skip = (Ceil( (1024 - 15) - (31 - (16 4 ») /16»- 1
Skip = (Ceil( 990
) /16) )- 1
Skip = (Ceil(
61.875
) )- 1
Skip =
62
- 1
Skip =
61 = X'3D'
AS

Array Size or DX Array x 8: the source image width in bits.

DW

Result Destination Width: the width of the unrotated destination
rectangle in bits.

Ceil

Ceiling Function: least integer greater than function.

Skip

(Ceil( (AS - 15) - (DW - (16 - Bit Offset) ) /16) ) - 1

Note: If Bit Offset = 0, the above formula simplifies to Skip = Ceil((AS - DW)/16)

Extended Monochrome Graphics Adapter 51

TNL SN20-9844 (March 1987) to 75X0235

Queue Load
Reg

Function

RA
RB
R4
R3
R2
R7
R6
R5
RO

A23-A17
Source high
A16-A9
Source mid
AS-AI
Source low
Bit offset
Skip (16 bit words)
X destination
Y destination
Delta X + 1
Delta Y + 1
Execute Command

Value of
Register
X'AOOO'
X'BOOS'
X'4009'
X'3004'
X'203D'
X'702A'
X'600F'
X'501F'
X'0003'
X'D379'

Comment
Upper left start word address
Upper left start word address
Upper left start word address
Starting bit of the starting word
Array width = X'OSO' bytes
Lower right corner exclusive
Lower right corner exclusive
Number of pels in width
Number of pels in height

Note: The registers used by the DMA graphic operations have the following ending conditions:
Reg

52

RA

Value of
Register
X'AXXX'

RB

X'BXXX'

R4

X'4XXX'

R3
R2
R7
R6
R5
RO

X'3XXX'
X'2XXX'
X'7XXX'
X'6XXX'
X'5XXX'
X'OOOO'

Change From Initial Conditions
A23-A 17 = Address of last I/O channel memory word
read
A 16-A9 = Address of last I/O channel memory word
read
AS-A 1 = Address of last I/O channel memory word
read
Unchanged
Unchanged
Unchanged
Unchanged
Unchanged
Set to zero

Extended Monochrome Graphics Adapter

TNL SN20-9844 (March 1987) to 75X0235

1/0 ADDR

LSB
D15

MSB

DO

'001012'
'001092'
'001112'

DO

xxxx------------xxxx------------xxxx-------------

- DX1=12 -

LSB
D15

MSB

'001014
'001094
'001114

-------------------------------------------------------

I

MSB

LSB

DO

'001016'
'001096'
'001116'

- - -xx
- - -xx
- - -xx

DY
+ 1 =3

I

DX2 = 19
DX +1 = 31 BITS

BAMDA IMAGE STRUCTURE

o

11

+x

41

o

12

14

: : : : : : :1

L . . . - - -_ - - - - - '

(XD YD)

1 s

+y

Figure 34. TDDMA I/O Copy Example

Extended Monochrome Graphics Adapter 53

TNL SN20-9844 (March 1987) to 75X0235

TDDMA Cut/Paste From I/O Channel Memory

+ 90 Degree Rotate (X'38')

This graphic operation performs in the same manner as graphic operation type X'37' except that
the destination is rotated 90 degrees
counterclockwise.
Note: *Notice the change in the queue load parameters.
Queue Load
Reg

Function

RA
RB
R4
R3
R2
R6 *

A23-A17 = Source high
A16-A9 = Source mid
A8-Al
= Source low
Bit offset
Skip (16 bit words)
X destination

Value of
Register
X'AOOO'
X'B008'
X'4009'
X'3004'
X'203D'
X'600A'

R7 *

Y destination

X'700F'

RO *

10 bit 2's complement of
Delta X + 1

X'03El'

R5 *

Delta Y + 1
Execute Command

X'5003'
X'D389'

54 Extended Monochrome Graphics Adapter

Comment
Upper left start word address
Upper left start word address
Upper left start word address
Starting bit of the starting word
Array width = X'080' bytes
Lower left corner exclusive
(XD-(DX + 1)-1)
Lower left corner exclusive (YD)

TNL SN20-9844 (March 1987) to 75X0235

TDDMA Cut/Paste From I/O Channel Memory 45 Degree Diag Flip (X'39')
This graphic operation performs in the same manner as graphic operation type X'37' except that
the destination is rotated 180 degrees about the 45 degree diagonal.

Note:

* Notice the change in the queue load parameters.

Queue Load

Reg

Function

RA *
RB *
R4 *
43
R2
R6
R7
RO
R5

Source high
A23-A17
A16-A9
Source mid
A8-A1
Source low
Bit offset
Skip (16 bit words)
X destination
Y destination
Delta X + 1
Delta Y + 1
Execute Command

Value of
Register
X'AOOO'
X'B008'
X'4009'
X'3004'
X'203D'
X'600F'
X'700B'
X'OOlF'
X'5003'
X'D399'

Comment
Upper left start word address
Upper left start word address
Upper left start word address
Starting bit of the starting word
Array width = X'080' bytes
Lower right corner exclusive
Lower right corner exclusive

Extended Monochrome Graphics Adapter 55

TNL SN20-9844 (March 1987) to 75X0235

TDDMA Cut/Paste From I/O Channel Memory 180 Degree X Axis Symmetry (X'3A')
This graphic operation performs in the same manner as graphic operation type X'37' except that
the destination is rotated ISO degrees about the X axis.
Note: Notice the change in the queue load parameters.
Queue Load
Reg

Function

RB *
R4 *
R3
R2
R7

A23-A17 = Source high
A16-A9 = Source mid
AS-AI
= Source low
Bit offset
Skip (16 bit words)
X destination

Value of
Register
X'AOOO'
X'BOOS'
X'4009'
X'3004'
X'203D'
X'700B'

R6

Y destination

X'600F'

Delta X + 1
10 bit 2's Complement
of Delta Y + 1

X'5013'
X'03FD'

Execute Command

X'D3A9'

RA

R5
RO

*

*

56 Extended Monochrome Graphics Adapter

Comment
Upper left start word address
Upper left start word address
Upper left start word address
Starting bit of the starting word
Array width = X'OSO' bytes
Upper right corner exclusive
(XD)
Upper right corner exclusive
(YD-(Dx + 1)-1 )

TNL SN20-9844 (March 1987) to 75X0235

Control Graphic Operation Types
Branch and Link Queue (X'3B')
The branch and link queue graphic operation allows branching to a specified queue location and
saves the queue pointer value for the next-in-line location for later use by the return queue
graphic operation.
Example: Branch and Link Queue, branch to queue address X'E015', and save the next queue
address X'EFFD' in the queue link pointer register for later use by the return queue operation.
Queue
Address

Queue
Data

Action By
Queue Processing

X'FOOO'

X'AOEO

Load RA with 8 high order bits of branch target queue pointer
value

X'EFFF'

X'B015

Load RA with 8 low order bits of branch target queue pointer
value

X'EFFE'

X'D3BO

Execute branch and link queue graphic operation

X'EFFD'

Return Queue

Link address for next operation after return queue.

(~'3C')

The return queue graphic operation returns from a branch and link queue operation to the
queue address, which was saved in the queue link pointer register. In the previous example, the
return queue graphic operation causes queue processing to return to the queue address
X'EFFD'.

Extended Monochrome Graphics Adapter 57

TNL SN20-9844 (March 1987) to 75X0235

Scan Line Sync (X'3D')
The scan line sync graphic operation provides a means of stopping queue processing until a
specified scan line number (SLN) appears in the scan line counter register. The scan line
complement (SLC) is the input data to the scan line sync graphic operation and is the 10 bit 2's
complement of the scan line number.
Note: Valid SLN values are X'OOO' and X'OOI' to X'317. The valid SLC values are X'OOO' and
X'3FF' to X'OE9'. Out of range values cause the adapter queue processing to hang in such a
manner that the adapter must be reset to restore queue processing operation.
Example: Scan Line Sync, stop queue processing until the scan line counter reaches a value of
X'IF5'.
Queue
Address

Queue
Data

Que Ptr
Que Ptr-l

X'A20B'
X'D3DO'

Action By
Queue Processing
Calculate SLC = 10 bit 2's complement of X'IF5' = X'20B'
Load RA with 10 bit scan line complement
Execute the scan line sync graphic operation

Graphic Operation Type X'3E' Set Video On
The set video on graphic operation enables the video data line to the display monitor. When the
video data line is enabled, the information contained in the displayable bit map area is displayed
on the monitor.
Example: Set Video On
Queue
Address
Que Ptr

Queue
Data
X'D3EO'

Action By
Queue Processing
Execute set video on - Enable the video data line.

58 Extended Monochrome Graphics Adapter

TNL SN20-9844 (March 1987) to 75X0235

Set Video Off (X'3F')
The set video ofT graphic operation disables the video data line to the display monitor. When
the video data line is disabled, the information contained in the displayable bit map area is not
displayed on the monitor. The monitor instead produces the background screen type, either an
all white screen or an all black screen, depending on the current setting of the black on white
background bit in the control/status register.
Example: Set Video OfT
Queue
Address

Queue
Data

Action By
Queue Processing

Que Ptr

X'D3FO'

Execute set video ofT - Disable the video data line.

Extended Monochrome Graphics Adapter 59

TNL SN20-9844 (March 1987) to 75X0235

Graphic Operation Queue Load
The queue load data example shown for each graphic operation type demonstrates what a queue
load might look like for that operation. For instance, to draw a line in BAMDA from the
decimal coordinates (X1,Y1 = 100,200) to (X2,Y2 = 512,384) with all pels on the line set to
1, you could use the graphic operation type X'35' (Vector Draw) with the following queue load
data.
System Addr.
(low 24 bits)

Queue Load
Data

Parameter
Name/Decimal Value

X'D9F7FE'

X'1064'

Xl / 100

X'D9F7FC'

X'00C8'

Y1 / 200

X'D9F7FA'

X'5200'

X2 / 512

X'D9F7F8'

X'6180'

X'D9F7F6'

X'DB5F'

Y2 / 384
Execute Vector Draw subtype F
(Replace On) with dec Q flag on

1/0 DATA FIELD

7 8

0

15

11011011101011111
I

I

I

I

I
I

I

I

I

-- I

I

I

I

I

I

I

I

I

•

GRAPHIC OP EXECUTE COMMAND WORD
FOR THIS EXAMPLE:
(X'DB5F')

II
Bits 00-03 EXECUTE DECODE
( 1 10 1 )
Bit 04
DECREMENT QUEUE COUNTER FLAG (ON)
Bit 05

GRAPHIC OP INTERRUPT FLAG (OFF)

Bits 06-11 GRAPHIC OP TYPE (X'35')
Bits 12-15 GRAPHIC OP LOGIC FUNCTION (subtype) (X'F')

To execute the graphic operation, write the queue pointer register with the queue pointer value
corresponding to the queue load starting address (X'FBFF' corresponds to X'D9F7FE') and then
increment the queue counter. Do a I/O memory write X'FBFF' to I/O channel memory address
X'D9F806' (queue pointer register location) and then a write to I/O address X'OD14' (increment
queue counter). The complete operation to write the queue load and execute it requires a total
of six memory write operations and one I/O write.

60 Extended Monochrome Graphics Adapter

TNL SN20-9844 (March 1987) to 75X0235

Graphic Operation Queue Load Format Table
Definitions of symbols used in this table are:
•

xxx = 10 bit hex data (max value = X'3FF' = 1023)

•

Oxx = 8 bit hex data (max value = X'OFF = 255)

•

s = subtype

•

Ire

•

Xl, Y 1 represent the start point coordinates of a line or the upper left corner point of a
rectangle.

•

X2, Y2 represent the end point coordinates of a line or the lower right corner point of a
rectangle.

•

DX, DY represent (X2-Xl) and (Y2-Yl) respectively.

=

lower right exclusive point

Type

Graphic Operation Name and Queue Load Data Example

2C

RELATIVE DRAW WITH ENDING NULL
Data
1xxx
Oxxx
5xxx
6xxx
D2Cs

2D

Reg Parameter
R1 Xl
RO Y1
R5 DX
R6 DY
Execute command

RELATIVE DRAW
Data
1xxx
Oxxx
5xxx
6xxx
D2Ds

Reg Parameter
R1 Xl
RO Y1
R5 DX
R6 DY
Execute command

Extended Monochrome Graphics Adapter 61

TNL SN20-9844 (March 1987) to 75X0235

Type

Graphic Operation Name and Queue Load Data Example

2E

RELATIVE MOVE TO
Data
2xxx
6xxx
D2Es

2F

RECTANGULAR FILL (HOR/VER OPTIMIZED)
Data
7xxx
6xxx
9xxx
8xxx
D2Fs

30

Reg Parameter
R2 DX
R6 DY
Execute command

Reg Parameter
R7 XD Ire
R6 YD Ire
R9 DX+ 1
R8 DY+ 1
Execute command

RECTANGULAR COPY/MERGE
Data
5xxx
4xxx
7xxx
Axxx
9xxx
Oxxx
D30s

Reg Parameter
R5 Xsource Ire
R4 Ysource Ire
R7 Xdest Ire
RA Ydest Ire
R9 DX+ 1
RO DY+ 1
Execute command

62 Extended Monochrome Graphics Adapter

TNL SN20-9844 (March 1987) to 75X0235

Type

Graphic Operation Name and Queue Load Data Example

31

RECTANGULAR COPY/MERGE + 90 DEGREE ROTATE
Data
5xxx
4xxx
Axxx
7xxx
9xxx
Oxxx
D31 s

32

RECTANGULAR COPY/MERGE -90 DEGREE ROTATE
Data
4xxx
5xxx
7xxx
Axxx
Oxxx
9xxx
D32s

33

Reg Parameter
R5 Xsource Ire
R4 Ysource Ire
RA Xdest Ire
R7 Ydest Ire
R9 DX+ 1
RO DY+ 1
Execute command

Reg Parameter
R4 Xsource Ire
R5 Ysource Ire
R7 Xdest Ire
RA Y dest Ire
RO DX+ 1
R9 DY+ 1
Execute command

RECTANGULAR COPY/MERGE 180 DEGREES X AXIS SYMMETRY
Data
5xxx
4xxx
7xxx
Axxx
9xxx
Oxxx
D33s

Reg Parameter
R5 Xsource Ire
R4 Ysource Ire
R 7 Xdest Ire
RA (Ydest-(DY + 1)-1) Ire
R9 DX+ 1
RO DY+ 1
Execute command

Extended Monochrome Graphics Adapter 63

TNL SN20-9844 (March 1987) to 75X0235

Type

Graphic Operation Name and Queue Load Data Example

34

RECTANGULAR COPY/MERGE 180 DEGREES Y AXIS SYMMETRY
Data
4xxx
5xxx
Axxx
7xxx
Oxxx
9xxx
D34s

35

VECTOR DRAW
Data
1xxx
Oxxx
5xxx
6xxx
D35s

35

Reg Parameter
R4 Xsource Ire
R5 Ysource Ire
RA (Xdest-(DX + 1)-1) Ire
R7 Ydest Ire
RO DX+ 1
R9 DY+ 1
Execute command

Reg Parameter
Rl Xl
RO Y1
R5 X2
R6 Y2
Execute command

POLYLINE DRAW (CONNECTED CONTINUATION)
Data
5xxx
6xxx
D35s

Reg Parameter
R5 X2
R6 Y2
Execute command

64 Extended Monochrome Graphics Adapter

TNL SN20-9844 (March 1987) to 75X0235

Type

Graphic Operation Name and Queue Load Data Example

36

VECTOR DRAW WITH ENDING NULL
Data
lxxx
Oxxx
5xxx
6xxx
D36s

36

. POLYLINE DRAW WITH ENDING NULL
(CONNECTED CONTINUATION)
Data
5xxx
6xxx
D36s

37

Reg Parameter
Rl Xl
RO Yl
R5 X2
R6 Y2
Execute command

Reg Parameter
R5 X2
R6 Y2
Execute command

TDDMA CUT/PASTE FROM SYSTEM MEMORY
Data
AOxx
BOxx
40xx
3xxx
2xxx
7xxx
6xxx
5xxx
Oxxx
D37s

Reg Parameter
RA DMA addr HI(O-6)
RB DMA addr MI(7-l4)
R4 DMA addr LO(l5-22)
R3 Bit offset
R2 Skip amount
R 7 Xdest Ire
R6 Ydest Ire
R5 DX+ 1
RO DY+ 1
Execute command

Extended Monochrome Graphics Adapter 65

TNL SN20-9844 (March 1987) to 75X0235

Type

Graphic Operation Name and Queue Load Data Example

38

TDDMA CUT/PASTE FROM SYSTEM MEMORY + 90 DEGREE ROTATE
Data
AOxx
BOxx
40xx
3xxx
2xxx
7xxx
6xxx
5xxx
Oxxx
D38s

39

Reg Parameter
RA DMA addr HI(0-6)
RB DMA addr MI(7-14)
R4 DMA addr LO(15-22)
R3 Bit offset
R2 Skip amount
R 7 Xdest Ire
R6 (Xdest-(DX + I)-I) Ire
R5 DX+ I
RO 2's comp of (DX + 1)
Execute command

TDDMA CUT/PASTE FROM SYSTEM MEMORY
45 DEGREES DIAGONAL FLIP
Data
AOxx
BOxx
40xx
3xxx
2xxx
7xxx
6xxx
5xxx
Oxxx
D39s

Reg Parameter
RA DMA addr HI(0-6)
RB DMA addr MI(7-14)
R4 DMA addr LO(15-22)
R3 Bit offset
R2 Skip amount
R 7 Xdest Ire
R6 Xdest Ire
R5 DY+ 1
RO DX+ 1
Execute command

66 Exten_ded Monochrome Graphics Adapter

TNL SN20-9844 (March 1987) to 75X0235

Type

Graphic Operation Name and Queue Load Data Example

3A

TDDMA CUT/PASTE FROM SYSTEM MEMORY
45 DEGREES DIAGONAL FLIP
Data
AOxx
BOxx
40xx
3xxx
2xxx
7xxx
6xxx
5xxx
Oxxx
D3As

3B

BRANCH AND LINK QUEUE (one level deep)
Data
AOxx
BOxx
D3Bs

3C

Reg Parameter
RA DMA addr HI(O-6)
RB DMA addr MI(7-14)
R4 DMA addr L0(15-22)
R3 Bit offset
R2 Skip amount
R7 Xdest Ire
R6 (Ydest-(DY + 1)-1) Ire
R5 DX+ 1
RO 2's Comp of DY + 1
Execute command

Reg Parameter
RA BR addr HI(O-7)
RB BR addr LO(8-15)
Execute command

RETURN QUEUE (one level deep)
Data
D3CO Execute command

3D

SCAN
Data
AOxx
D3DO

LINE LINK
Reg Parameter
RA Scan line complement
Execute command

Extended Monochrome Graphics Adapter 67

TNL SN20-9844 (March 1987) to 75X0235

Type

Graphic Operation Name and Queue Load Data Example

3E

SET VIDEO ON
Data
D3EO Execute command

3F

SET VIDEO OFF
Data
D3FO Execute command

68 Extended Monochrome Graphics Adapter

TNL SN20-9844 (March 1987) to 75X0235

Connector Specifications

EXTENDED M ONOCHROME
GRAPHICS DISPLAY

I

GND-VSync

1

VSync

2

RESERVED

3

RESERVED

4

RESERVED

5

RESERVED

6

GND-VIDEO

7

VIDEO

8

GND-VIDEO

9

VIDEO

10

GND-VIDEO

11

VIDEO

12

GND-VIDEO

13

VIDEO

14

GND-HSync

15

HSync

16

1

3

5

7

9

11

13

15

2

4

6

8

10

12

14

16

EXTENDED M ONOCHROME
GRAPHIC S ADAPTER

1

MATING FACE OF ADAPTER CONNECTOR

Extended Monochrome Graphics Adapter 69

TNL SN20-9844 (March 1987) to 75X0235

70 Extended Monochrome Graphics Adapter

----_.-

------- --- -- --

512 KB Memory
Expansion Option

Personal Computer
Hardware Reference
Library

ii

Contents

Description ....................................
Memory Cycles .............................
Memory Address Switches ....................
110 Channel Check .........................
Specifications ..................................
Voltage Tolerances ..........................
Power Dissipation ...........................
Temperature Variation .......................
Logic Diagrams .................................

1
1
1
3
3
3
3
3
4

iii

Notes:

iv

Description
This adapter has 36 RAM modules (128K x 1) for a total capacity
of 512Kb.

Memory Cycles
MEMR and MEMW commands require a l-wait-state, 3-clock
memory cycle. Data moves as a byte (8 data bits and 1 parity bit)
or as a word (16 data bits and 2 parity bits) and is parity-checked
on the adapter. A parity error causes an I/O channel check
(non-maskable interrupt) to the system.

Memory Address Switches
There are two banks of memory address switches on each
memory adapter. These switches are set to values for the first,
second, third, etc. memory adapter in the system. The following
figure shows the switch configuration for each adapter.
The first memory expansion adapter must start at address space
hex 100000. If more than one adapter is installed, no gaps
between memory are allowed. All expansion memory must be
one contiguous block starting at address hex 100000.

512KB Memory Expansion Option 1

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Switch Bank 0

1st512KB
Memory
Expansion
Adapter

2nd 512KB
Memory
Expansion
Adapter

3rd 512KB
Memory
Expansion
Adapter

4th 512KB
Memory
Expansion
Adapter

5th 512KB
Memory
Expansion
Adapter

2 S12KB Memory Expansion Option

Switch Bank 1

Switch Bank 1

110 Channel Check
When the I/O channel check occurs, a non-maskable interrupt
(NMI) results, and the status bits determine the source (one
status bit is I/O channel check and the other is system-board
parity check). Writing to the failing card will clear the status bit.

Specifications

Voltage Tolerances
The maximum variation of the + 5 V dc is ± 5 % at the adapter
pins.

Power Dissipation
The +5-Vdc power used by the adapter is a maximum of 5.25
watts, and the maximum current used is 1 ampere.

Temperature Variation
The adapter will operate between 10 and 50 degrees Celsius (50
and 122 degrees Farenheit).

S 12KB Memory Expansion Option 3

Notes:

4 512KB Memory Expansion Option

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----------------

-- --_.-

Monochrome Display
and Printer
Adapter

Personal Computer
Hardware Reference
Library

ii

Contents

Introduction ................................... 1
Monochrome Display Adapter Function .............. 1
Description ................................ 1
Programming Considerations .................. 5
Specifications .............................. 9
Printer Adapter Function ........................ 11
Description ............................... 11
Programming Considerations ................. 13
Specifications ............................. 17
Logic Diagrams ................................ 19

iii

iv

Introduction
The IBM Monochrome Display and Printer Adapter has two
functions. The first is to provide an interface to the IBM
Monochrome Display. The second is to provide a parallel
interface for the IBM Printers. We will discuss this adapter by
function.

Monochrome Display Adapter Function

Description
The IBM Monochrome Display and Printer Adapter is designed
around the Motorola 6845 CRT Controller module. There are
4K bytes of RAM on the adapter that are used for the display
buffer. This buffer has two ports to which the system unit's
microprocessor has direct access. No parity is provided on the
display buffer.
Two bytes are fetched from the display buffer in 553 ns,
providing a data rate of 1.8M bytes/second.
The adapter supports 256 different character codes. An 8K-byte
character generator contains the fonts for the character codes.
The characters, values, and screen characteristics are given in "Of
Characters, Keystrokes, and Colors" in your Technical Reference
system manual.
This adapter, when used with a display containing P39 phosphor,
does not support a light pen.
Where possible, only one low-power Schottky (LS) load is
present on any I/O slot. Some of the address bus lines have two
LS loads. No signal has more than two LS loads.

Monochrome Adapter 1

Characteristics of the adapter are:
•

Supports 80-character by 25-line screen

•

Has direct-drive output

•

Supports 9-PEL by 14-PEL character box

•

Supports 7-PEL by 9-PEL character

•

Has 18-kHz monitor

•

Has character attributes

2 Monochrome Adapter

The following is a block diagram of the monochrome display
adapter portion of the IBM Monochrome Display and Printer
Adapter.
Processor
Address

(12) ..

...

(1~

Memory
Address
Multiplexer

(10)

(10)

2K Memory
Character
Code

Processor
Data

..
""

Data
Bus
Gating

BOO-7

..

(8)

row

Chip

Octal
Latch

Select

Timing

""

..

1 ..

... - ...

t...

_

RA ..
(4)

...

Character
Generator

Octal
Latch

Attribute
Decode

MC6845
CRTC

DOTCLK

Shift
Register

...
'"

.....

Signals
Serial Dots

r

"

~

.....

..

Character
Clock

"

MA

AO

4~

(8)

...
row

J (8)

....

2K Memory
Attribute

.....

Video
Process
Logic

HSYNC, VSYNC, CURSOR, DISPEN ...

...

Character
Clock

I +

Monitor
Direct Drive
Outputs

IBM Monochrome Display Adapter Block Diagram

Monochrome Adapter 3

4 Monochrome Adapter

Programming Considerations
The following table summarizes the 6845 controller module's
internal data registers, their functions, and their parameters. For
the IBM Monochrome Display, the values must be programmed
into the 6845 to ensure proper initialization of the display.

Register
Number

Register
File

Program
Unit

RO
R1
R2
R3
R4
R5
R6
R7
R8
R9

Horizontal Total
Horizontal Displayed
Horizontal Sync Position
Horizontal Sync Width
Vertical Total
Vertical Total Adjust
Vertical Displayed
Vertical Sync Position
Interlace Mode
Maximum Scan Line
Address
Cursor Start
Cursor End
Start Address (H)
Start Address (L)
Cursor (H)
Cursor (L)
Reserved
Reserved

Characters
Characters
Characters
Characters
Character Rows
Scan Line
Character Row
Character Row

R10
R11
R12
R13
R14
R15
R16
R17

--------Scan Line
Scan Line
Scan Line

IBM Monochrome
Display
(Address in hex)
61
50
52
F
19
6
19
19
02
D

B

-----------------

C
00
00
00
00

---------

--

---------

--

_.... _--------------

To ensure proper initialization, the first command issued to the
IBM Monochrome Display and Printer Adapter must be sent to
the CRT control port 1 (hex 3B8), and must be a hex 01, to set
the high-resolution mode. If this bit is not set, the system unit's
microprocessor's access to the adapter must never occur. If the
high-resolution bit is not set, the system unit's microprocessor will
stop running.
System configurations that have both an IBM Monochrome
Display and Printer Adapter, and an IBM Color/Graphics
Monitor Adapter, must ensure that both adapters are properly
initialized after a power-on reset. Damage to either display may
occur if not properly initialized.

Monochrome Adapter 5

The IBM Monochrome Display and Printer Adapter supports 256
different character codes. In the character set are alphanumerics
and block graphics. Each character in the display buffer has a
corresponding character attribute. The character code must be an
even address, and the attribute code must be an odd address in
the display buffer.
7

6

5

4

2

3

0
Character Code
Even Address (M)

7
Bl

6

5

4

2

3

IR IG I I IR IG
B

I

B

Attribute Code
Odd Address (M + 1)

I

~

I I I

I

0

Foreground
Intensity
Background
Blink

The adapter decodes the character attribute byte as defined
above. The blink and intensity bits may be combined with the
foreground and background bits to further enhance the character
attribute functions listed below:
Background
R G B

0 0
0 0
0 0
1 1 1

0
0
0

Foreground
R G B

0
0
1

0

0
0
1
0

0
1
1

0

Function
Non-Display
Underline
White Character/Black Background
Reverse Video

The 4K display buffer supports one screen of the 25 rows of 80
characters, plus a character attribute for each display character.
The starting address of the buffer is hex BOOOO. The display
buffer can be read using direct memory access (DMA); however,
at least one wait state will be inserted by the system unit's
microprocessor. The duration of the wait state will vary, because
the microprocessor/monitor access is synchronized with the
character clock on this adapter.

6 Monochrome Adapter

Interrupt level 7 is used on the parallel interface. Interrupts can
be enabled or disabled through the printer control port. The
interrupt is a high-level active signal.
The following table breaks down the functions of the I/O address
decode for the adapter. The I/O address decode is from hex 3BO
through hex 3BF. The bit assignment for each I/O address
follows:
I/O Register
Address
380
381
382
383
384
385
386
387
388
389
38A
388
38C
38D
38E
38F

Function
Not Used
Not Used
Not Used
Not Used
6845 Index Register
6845 Data Register
Not Used
Not Used
CRT Control Port 1
Reserved
CRT Status Port
Reserved
Parallel Data Port
Printer Status Port
Printer Control Port
Not Used

I/O Address and Bit Map

Monochrome Adapter 7

Bit
Number

0
1
2
3
4
5
6,7

Function

+ High Resolution Mode
Not Used
Not Used
+ Video Enable
Not Use:d
+ Enable Blink
Not Used

6845 CRT Control Port 1 (Hex 3B8)
Bit
Number

Function

0

+ Horizontal Drive

1
2
3

Reserved
Reserved
+ Black/White Video

6845 CRT Status Port (Hex 3BA)

8 Monochrome Adapter

Specifications
9-Pin
Monochrome
Display
connector
o

1f:l6

9
sl0J
o

At Standard TTL Levels

IBM
Monochrome
Display

Note:

Ground

1

Ground

2

+ Intensity

Not Used

3

Not Used

4

Not Used

5

6

+ Video

7

+ Horizontal

8

- Vertical

9

IBM
Monochrome
Display and
Printer Adapter

Signal voltages are 0.0 to 0.6 Vdc at down level and + 2.4to 3.5
Vdc at high level.

Connector Specifications

Monochrome Adapter 9

10 Monochrome Adapter

Printer Adapter Function

Description
The printer adapter portion of the IBM Monochrome Display and
Printer Adapter is specifically designed to attach printers with a
parallel-port interface, but it can be used as a general
input/ output port for any device or application that matches its
input/ output capabilities. It has 12 TTL-buffer output points,
which are latched and can be written and read under program
control using the microprocessor In or Out instruction. The
adapter also has five steady-state input points that may be read
using the microprocessor's In instructions.
In addition, one input can also be used to create a microprocessor
interrupt. This interrupt can be enabled and disabled under
program control. A reset from the power-on circuit is also ORed
with a program output point, allowing a device to receive a
'power-on reset' when the system unit's microprocessor is reset.
The input/output signals are made available at the back of the
adapter through a right-angle, printed-circuit-board-mounted,
25-pin, D-shell connector. This connector protrudes through the
rear panel of the system unit or expansion unit, where a cable may
be attached.
When this adapter is used to attach a printer, data or printer
commands are loaded into an 8-bit, latched, output port, and the
strobe line is activated, writing data to the printer. The program
then may read the input ports for printer status indicating when
the next character can be written, or it may use the interrupt line
to indicate "not busy" to the software.
The output ports may also be read at the card's interface for
diagnostic loop functions. This allows faults to be isolated to the
adapter or the attaching device.

Monochrome Adapter 11

The following is a block diagram of the printer adapter portion of
the Monochrome Display and Printer Adapter.
25-Pin D-Shell
Connector

8

~

Bus BUffe-..,;r8~1---1.....
Data Latc...
h_...e-;8~-4."
~

~

r

Transceiver

~

Enable

~

Clock

.......-+____......
...

1oIIII
...~8:...

......

DIR

------...

DIR

O.C.

Read
Data

Drivers

~

Command
Decoder

Write Data

I--------+-.....J
Write Control

FDXT

Read Status

INIT

Read
Control

~

Bus
Buffers

Control
Latch

~ Enable t..2...

.....

L.....

fP""

------...

5

Clock ~

......

'----t Enable
,....... Clear

PE
ACK
Reset

Printer Adapter Block Diagram

12 Monochrome Adapter

BUSY

Programming Considerations
The printer adapter portion of the IBM Monochrome Display and
Printer Adapter responds to five I/O instructions: two output
and three input. The output instructions transfer data into 2
latches whose outputs are presented on pins of a 25-pin D-shell
connector.
Two of the three input instructions allow the system unit's
microprocessor to read back the contents of the two latches. The
third allows the system unit's microprocessor to read the real-time
status from a group of pins on the connector.
A description of each instruction follows.

IBM Monochrome Display &
Printer Adapter
Output to address hex 3BC
Bit 7

Bit 6

Bit 5

Bit4

Pin 9

Pin 8

Pin 7

Pin 6

The instruction captures data from the data bus and is present on
the respective pins. Each of these pins is capable of sourcing 2.6
rnA and sinking 24 rnA.
It is essential that the external device does not try to pull these

lines to ground.
IBM Monochrome Display &
Printer Adpater
Output to address hex 3BE
Bit4
IRQ
Enable

This instruction causes the latch to capture the five least
significant bits of the data bus. The four least significant bits
present their outputs, or inverted versions of their outputs, to the

Monochrome Adapter 13

respective pins as shown in the previous figure. If bit 4 is written
as aI, the card will interrupt the system unit's microprocessor on
the condition that pin 10 changes from high to low.
These pins are driven by open-collector drivers pulled to +5 Vdc
through 4.7 kQ resistors. They can each sink approximately 7 mA
and maintain 0.8 volts down-level.

IBM Monochrome Display &
Printer Adapter
Input from address hex 3BC

This instruction presents the system unit's Inicroprocessor with
data present on the pins associated with the output to hex 3BC.
This should normally reflect the exact value that was last written
to hex 3BC. If an external device should be driving data on these
pins at the time of an input (in violation of usage ground rules),
this data will be ORed with the latch contents.

IBM Monochrome Display &
Printer Adapter
Input from address hex 3BD

This instruction presents the real-time status to the system unit's
microprocessor from the pins as follows.

Bit 7

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

BitO

Pin 11

Pin 10

Pin 12

Pin 13

Pin 15

-

-

-

IBM Monochrome Display &
Printer Adapter
Input from address hex 3BE

14 Monochrome Adapter

This instruction causes the data present on pins 1, 14, 16, 17, and
the IRQ bit to be read by the system unit's microprocessor. In
the absence of external drive applied to these pins, data read by
the system unit's microprocessor will match data last written to
hex 3BE in the same bit positions. Notice that data bits 0-2 are
not included. If external drivers are dotted to these pins, that
data will be ORed with data applied to the pins by the hex 3BE
latch.
Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

IRQ
Enable

Pin 17

Pin 16

Par=O

Par= 1

Par=O

Bit 1

BitO

--

-

Par= 1

Par= 1

Pin 14

Pin 1

These pins assume the states shown after a reset from the system
unit's microprocessor.

Monochrome Adapter 15

16 Monochrome Adapter

Specifications

0

•
•
•
•

•
•
•
•
•
•
•
•
•

•
•
•
••

• •
•
• ••
•

14

25

0
At Standard TTL Levels

Printer

Signal

Adapter

Name

Pin Number

- Strobe

1

+ Data Bit 0
+ Data Bit 1
+ Data Bit 2
+ Data Bit 3
+ Data Bit 4
+ Data Bit 5
+ Data Bit 6
+ Data Bit 7

2
3
4
5
6
7

IBM

8

Monoch rome

9

Display a nd

- Acknowledge

10

Printer

+ Busy
+ P. End (out of paper)
+ Select

11

Adapter

12

-Auto Feed

14

- Error

15

- Initialize Printer

16

- Select Input

17

Ground

13

18-25

Connector Specifications

Monochrome Adapter 17

18 Monochrome Adapter

liD SLOT
(SHT6(

DO

A09

01
02

A08
A07

03
04

A06
A05
A04

(SHT 6)

05
06
07

(SHT3)

+(/0 READY

AID

ISHT9)

+IRQ7

B21

A03
A02

74LS244

:~

A31
A30
A29
A28

15
171

y

~

O
Ut

-=

9

r~

A

13

ISHT2.4.B)
(8HT2.4.B)
(SHT24.8)
(8HT2.4.8)

A4

(8HT2.4)
(8HT 2.4)
(8HT2.4)
(8HT2.4)
(8HT2.4)
(8HT2.4)
(8HT2)
(8HT2)
(8HT 4)
(8HT4)
(SHT4)
(SHT4)
(8HT4)
(8HT4.6)

A27
A26

A5
A6
A7
A8
A9
AID
All
AI5
AI6
A17
AI8
AI9
AEN

A25
A24
A23
A22

AI6
AI5
AI4
AI3
AI2
All
B30

1'1

B03

B03
+5V

B29
0.047"F
BOI
B31
810

B29
BOI
BID
B31
B09
BII

GROUN0--:J,.

I
I
74LSI25

BI2
12
BI3

74LSI25
9

BI4

74LSI25
5

B02

74L8125
2

II

U59

'12V
-MEMW

(8HT3.4)

-MEMR

(8HT4.6)

-lOW

(8HT2.4.B)

-lOR

(8HT4.6.8)

'RESET

(8HT2.3.5)

CI3
.".

U59

8
CIO

-=
59

6
C4

U59

-=
-=

B20

Monochrome Display Adapter (Sheet 1 of 10)

~
0

...
...~

(JQ
~

19

A21
A20

OECOUPLING CAPACITORS

BAD
BAI
BA2
BA3

3

~

74L804
12

-RE8ET

(8HT3.5.7.8)

110 CLOCK

(8HT4)

.
~

(JQ
~

a
rI1

r -____________~2~m~.lS-I-,S7

__

~ 18 IY +-RMAOr-------------+62A 2Ht--RMAI-------------------++--------------,!l-!~~: ~~ ~~=:~==

-RMAO , -S6 ~A20114l.2
u--.-

4

I,

74lSIS7~~
~

~

I~~ ~

=:=~t4:~
-RMA8~ A8

1-*

-RMA9fo

_ - -__- -____________-+-+-+-1-4--------~3 18 IY ~RMA4I"
l--'f AI
1-r------I-*l: 2A 2Y fi--RMASI"
1-4- :~
---------------------tttill.===t:::)I~1 28 3Y Tz-RMA6A4
10 3A 4y~RMA7
",-",-",-",-",-"
~--+AS UI3 UI2
- - - - - - -__-----------+-+-+-1-4--1-1--r _-___
- _-++-J.~14~~: U17
I"- ~II: A6

-------------------+++_H-+-f+----+!'13!!.1~4418ISS,EEll
GG 1

- - -__------------_+++_H-+-f+----~LI-.J

~~

I"
I"
~
I"I"-

15

,-----i
-=-

'.3 4Bl G4,lL
_ IS

_______~~,=:::.:";;_;;~~H-+t+H-+++1HT..!Jf

-

I~

jvl1 4

31 lG
IB UTm

~
26 2YI

74lS04

11

U2

~: UhP :~

10

S 74lS02

4

~---------;===--======6==U::27~
____
I,
~--------+------RAO

~--------+------:H

ISHT7.12)

1m WI

f¥.---------+------CURSOR ISHT S)

I!====t===:~m im~1

_--J----~~~~~====J-----OISPEN

·WE
18HT3)
974886
ISHT 1) +RESET-::::i)~

18HT5)

w:::+SV
RPI

Monochrome Display Adapter (Sheet 2 of 10)

~

I-l*- A9

110'12
1/0311

WE

CCS
CC6
CC7

~I/O,

~

4~

~

~I"-

11-lf
l--ft

I?
-W~I"-KJ,t---4 ~8

Ull 110: 11

A7
A8

l--]i WE
~

'"

I'

I"-

:~~;Hl~3--1------------- ATO
AT!

A41/012

I"-s:s:s.s: --t:~

1.

1

Ul0

~)I

"'-"'- "'-\ ~ "'-"'- "'- "'-"'-"'1'1'

AT2
AT3

2114l.2

~~
7 Al
- - 14

CS
~

T

~

1I0,~::~-H--I----------- CC4

I

374lS139~f'..

::

I

18HT6.10)
ISHT6.10)

UI4

I"- ,~____-+__________I--....J
I"r~~
I"AO
I"7 Al
1-- 14

74LSI39
2

~
~ cs

i=tt :~

~I~

-:_______------------I-+-+-+-I-4--1-I--I--+---~3 18 IY f4--RMA82A 2Y fl--RMA9------------------I+++-H-+-f+++-~--~11 ~: UI6
~- '"

-------------------I+++_H-+-f+++-+I~---l-!J-I:~ ~: ~ 3Y~

Va

-~=:~:t :~
~ CCO
- RMA
A3
1I0:~132 CCI
3
I~",,,,," " " " "'- "'-",-" -RMAS-+
RMA4-+ A4
I/O ~CC2
I"
AS UIS 1I0',r1L--CC3
I
2114l·2

--------------------+-+-+-------------J.!I.I14 38 UI8
4A
_ - - - - - - - - - - - - - - - -__++++-----------.-!.1;!.J48SElG
~IS

AT4
1I0'fit-- ATS
IIO,~
AT6
3
A4 U9 110
AS
110, f1-L--- AT7
17:~
UB

"4 A2
A3

-t~

r¥.---

l! ~
B

~
8]CS

ISHT6.10)

T

ISHT6.1O)

ISHTS.6)

T

ISHTS.6)

ISHTS.6)

T
ISHTS.6)

+5V
~RPI . -__~~__~~__________________________________________________________________________

J1o-..
f1_°---e.-____-'45bo-

r

6 74LS04

~T

-t=+======-__________________________________

(SHT 1) +RESET ______

~
~
<---

r

3~ 2

L.::i ~~

13 12

+5V RPI 1 2

I

II

~~tt=J

1~ 6~LK

3
4
(SHT 1) -MEMW -----+-------------!!..l,U~
(SHT4)
--;+.:;.:684..:.:5.:..:CS'--+-____________~V~
(SHT 4)
--,E,==~,-+______________~
(SHT 4)
_-"'CP-"-U""MS"'-EL'---t____________

'--~

(SHT7) -HRES

L

(SHT2)RA3

51 PI

+5V

14
7

1~~r

8

2 2 K
5
. , , : '" "'.

12 U57

..__-"

~W

4-+--+-__________...!lr7~4L"SO~
12 74LSOO
131 U25'- 11

I

I

~R

v,

~»..!!-6_ ___ ·WE

(SHT 2.6(

r--

3 74SlI
JI ~6
+CACS CCLK
74L804
U26
9 U2!>o-,,--B- - - - - i c - + - - - - - + - - - - - - - - - - +CClK
,~LV
___
-+--_ _ _ _ _ _ ___ -CClK

I
13

15~~t~

I

~74LS74

U2

11
10

74LS74

p~LK

_--+______

~l

I

2Y

I 74532

115

374LS174~

~74LS04,~B---1--~~_------------------------

ir
U43

3

/
U44

74LS04

+XACK

(SHT 6)

+10 READY

(SHT 1)

DOTCLK
ROMAlI

(SHT 7.10)
(SHT 10)

(SHT5.7.10)
__ ·CURSOR OLY (SHT 5)

(SHT 2) DlSPEN4 10
10 5
~>o'~-i'-----------------------------(SHT 2) CURSOR ---------------------I----lj....jU,f---"-I
"6 20
20 7
r--30U5530filO;;---+-+---------+--------------=::~U5~6---------------------------(SHT 2) HSYNC _ _ _ _ _ _ _ _ _ _ _-+_ _ _ _ _ _----!-;l13 ~~
:~r.~*"""2
(SHT 2) VSYNC
14 6D
60""15"--______

W

-----,f,

(SHT 5.10)
(SHT 2)

01-"--9.._+------------------- -XACK

~r_:'-"-2q:1~~LR!!...U4---.!~):>"__lalt_+_-__.___----___:"7:_-,---------I
II
~
3 7418125
1
U36
1C

2 OCLKU4 0 5
+5V 1 CLR
4 PR
06

(SHT2)

9

,

(SHT 3) + CClK

(SHT5)
(SHTIO)

1-----'vu::>u44<>'2'-----~'"""c:(3:Q.C~L~K---.....J------'1

74LS1I2A
I U2

~~gl~2n

OSCI

(SHTIO)

SI

~S04

C6

T"

~4LS04
3 J
11 74LS02

1C3
8A U24

11 2CO
+5V---+:; 2Cl

-CEROM

S/l

3

-

OSC:-----+--+----"-~ 19 lYf-'7-----i-+--~-----,,-=____+=2=U=3==-------h
l-;;:-i

(SHT7)
(SHT 4.5)

~---174--LSOO-------+--------------- 05
H------i-l"U25

----~Tt--------------74-LS-04--+++-----..!.ql~

~ 1~~LSI53

·JUMPER
+JUMPER

11 ~~ Ul ~~ 10
474LSoo
I l t 1 2A.I
~ 50 50~12C=~i=~~:jj5~~~5~6------__.:+5::-V~---1:~!(·~LR U5 Of'!g'--_____-4r'-~7:"'4L:::..:SIO

U6

74LS10

TEST

""""=-~1~3~ 11

r-r------------------.r-t-~-=-=-=-=-=-=-=-=-=-=-=-=-=_~-1-~·t_---------~~:~H'~~7~~~3JS08~1~I~fV~12-~,-U-54-~~~~~---------------------------1~ :~~~32 8

(SHT 1) -RESET

~

1

1

12 74S74
11 0
10 p~lK

JtL

---+-------------e-----------------------------------------+ _________________________________________________

4 74lS32
0 9

5 U100 6

+5V--+----Q~Clo!!.R_Ul-.Jol

Monochrome Display Adapter (Sheet 3 of 10)

·ClRVIDEO

·D1SPEN OlY

(SHT 71

+DISPEN OLY
+CURSOR Ol Y
+HSYNC OLY
+VSYNC OlY

(SHT 7)
(SHT 5)
(SHT 4.7)
(SHT5.7)

N
N

r-------------E

j ·'~1-"-9-----6845E

:::
Q

=
Q

(SHTI)

I/O CLOC K

----------r----------------------------~I~ll~LK

n

~
Q

-lOR

9~

(SHTI)
(SHT I)

-lOW
8A3

>
Q.

(SHTI)
(SHTI)

+AEN
A6

~

(SHT I)
(SHTI)
(SHT I)

A7
A5

A4

(SHT I)
(SHTI)
(SHT I)

8A2
8AI
8AO

(SHTI)

A8
A9

..""'"

~

(SHT2)

Q

1274LSOO

(SHTI)

"C

(SHT3)

174LSOO~
21 U53

Y-

3

4
U56

4
5

~
G2A

~1113~U5~3rl'-'-I-----------------+GRPOCO

r -_ _ _ _ _ _ _ _ _ _ _..

5 U4V)-l6'-----------------------_------6845CS

r6-~

~4LS04

L..J...

G28
GI
-"'1"'-5_ _ _ _ _ _ _ _ _ _ _ _-,
5
6
+6845CS
,---+_-....:4'-qG2A
YO,,"
U44
GI U52
7
C
Y7 1>'------+-+----'5<.qG28
Y-2
",1",-3
_
_
_
-"-S""TAO.!.T""US""SE"'
L--,
2
....
' - - - - - - - - - - - - - - SEL I
8
U50
I A
'----3 C
28

~
3

I

-MEMR

(SHT I)
(SHT I)
(SHTI)

(SHT I)

-MEMW
AI8
AI9
AI7
AI6
AI5

(SHT3)

+HSYNC OLY

(SHT 7)

(SHT2)

(SHT3)

(SHT 7)

----~+---------_~~~_yl~
g74LSOB

~

2
3

74LSI39
A

ro~4------~-------------------­

r--------------+~-~~I
~ U42 Y1 5

(SHT I)

(SHT8)

474L32

~
5

U46

6

5

~
G28

4 G2A
6 GI
3 C
28
I A

-

ROGATECC (SHT6)
ROGUE AT (SHT6)

U51

Yi;

9

-CPUMSEL

13 U46"
OATAGATE
~
~~1_ _ _~5 >J6L-_ _ _~---~~~-~===----------274LS02

74LS04

~

US6

fj~

!:::± j
8

+LVIOEO

"00

P

I~

Monochrome Display Adapter (Sheet 4 of 10)

12

800
801
802
803

ISHT3)
ISHT6)

ISHT61
(SHT61
ISHT61
ISHT61

ISHTII
ISHT31

74lS393
2
Tll ClR U2B 6
A
OD

+RESET
+VSYNCDlY

74lS393
12 ClR
QA 11
13 A U28

+BlINK

CURSOR BLINK
ISHT71 -ENABLE BLINK

17~B

~
10

ISHT31

+CURSDRDlY

U3

2~U46

ATO
ATl
AT2
AT3
AT4
AT5
AT6
AT7
ISHT 21
ISHT71+VIDEDENABlE
+CClK
ISHT 31

ISHTlI

-RESET

;SHT 31

-ClRVIDEO

ISHT41

+SDoTS

ISHT31

3~2

4
7
8
13
14
17
18
1
11

U31

3~
D
4
7
8
13
U30
14

AToX
ATlX
AT2X
AT3X
AT4X
AT5X
AT6X
AT7X

5
6
9
12
15
16
19

ClR

4~

+5V

ISHT71

SERDATA

>
C.

ISHT 31
ISHT 21

+JUMPER
RA3
RA2
RAI
RAo

=

..

!"1"

('D

N

~

-------J
2
3

('D

"CS

5
6

:

L9~
1 ClK

l~p3-NoDSPlY

13

~~

15

~52D2Q

7
10

1174lSD2

U29

123D

3Q

-BIOI

Gl
:
C

Y7
U48

7

-B171

_Flllr~

~G2A
~ G2B

74lSo4

Gl~
U4

1 C
Y4
2 B U47
3

~

Monochrome Display Adapter (Sheet 5 of 10)

U26

974S32
B

~
13 U43 11

'>410ClR

G2B

-

ISHT 2)

I

974lSo2
~10

I

'----

~G2AYDI5
_
-

-FIol

~
:~

I

f')

e

19

J(~

~

~
~

~

ISHT7J

I(ClR

Q

Q

9

17
18

------'1

Q

IIFJ

4JU62~

~G2Ayo15
6 G2B
Yl pi!.
+5V
~1 U49
2
B
3

=

ISHT7)

5.-'"

Q5

3:

lIBI

~S2O

(SHT 71 +ENABlE BLINK
ISHT 31 -CURSORDlY
ISHT21

3

1~

8

+RVV
+UNDERlINE

I

I

'"2,
5~

+B&WVIDEo

SERIN

ISHT7J

JSHTlOJ

ISH1)
+AEN
-JOR
ISH II
JSHIi
-MEMH
ISH 3) DATAIlAIE

iSM 21

I

ISH 21

ceo

CC I
CC2
eC3
CC4
CC5
CC6
CC7

I 74LS32

2~

3

~ ~soo
10 U53,8
~

18~2

tr

~

12
11
7
5
3

I
13
15

t7

rd2~=---

,lrr
3~2

14
I
18

ISH 3)
+XACK
ISH 4) -ROGATECC
ISH 3)
-WE
ATO

AT I

T
(SH 2)

AT2
AT3
AT4
AT5

Al6
AT7

I:

15
16
19

Ift~K

:tr
18 74L 44 2
12
9
7

8
11
13
15
17

3

~IG
I~

ti !

3.14lliL4 2

,Jt7

14

18

II CLK

15
16
19

800
801
802
803
804
805
B06
807

I

11\

800
SUI
B02
B03
B04
805
B06
B07

L
1

800
801
802
803
B04
805
806
B07

L
1

800
BOI
802
B03
B04
805
806
807

L
/

(8H 4) -ROGATEAT

Monochrome Display Adapter (Sheet 6 of 10)

l~

19 ~IR
U23

~~j
:~~----i
80!~
:~~====t
807

jE
E

~~

18H 1)

02

f-lf---- 0304
II

05
06
07

- - -800
- - -801

- - -802

-1103
804
B05

~

801i

807

1

18H I)

18H2.4.7.8.9)
18H2.4.&9)
18H 2.4.7.9)
18H2.4.8.9)
18H 2.8.9)
I8H2.1.8.9)
18H 2.8.9)
18H2.8.9)

5
.5V RPI13 U53

74lS175
ISHT 81
ISHT81
ISHT 81
ISHT 81
ISHT 41
ISHT II

13!~

-SEll
-RESET

ISHT51

...!

~2A
~2B

.HSYNC DlY

2

5

U54

0

4 74lS08

C4tl20PF

.------4..----- PIN I
1
l----PIN2

i_

74lS244
C3
120pF
,--_ _ _ _ _ _ _1~5~
.VIDEO
3
'--+--_ _ _ _ _ _-:-1:-l
I (-;7,--_ _ _ _ _ _ _ _ _ .HORIZ DRIVE

-+

PR

I
t

~ ii

UIOI

+-

,

U64

9

_

-VERT DRIVE

I
C7.i

J3
9PIN
O-SHEll
CONNECTOR

=

I

~U3
6

----PIN6

PIN7
PIN 8
- - - - PIN 9

,--------------------.lVIDEO

ISHT 4)

---lJ

0 f!5:..-1--_ _ _ _ _-!-_-=_ _
'_
- -_
-_
-__

---------~3-;D

ClK ClR
9 74lS00

~~~~

200

-HIGHLIGHT

RI

3

·5V
DOTClK

r~

~.-_ _---,
1

U45

-JUMPER

ISHT 31

8

,-----------+----------'I~I
~

ISHT31.VSYNCDly~1 74S86

·B/WVIDEO

PIN 5

12

4Y)-'=---------~

74lS74
PR

ISHT51
ISHT51

PIN 4

U64

3Y~

ISHT51

PIN 3

...!.!!

2yl

~

4

ISHT31

R2

Y~

A

-+--+---------=

I lClR

ISHT51

!..

.i..

U63

3B
IIBI -+-t--------~13 4A
IIFI
I 4B

2

ISHT 101
ISHT 101

IY

"*

1--_----;:-3-l>D ClK

ISHT 31

' - - - - - - - - - - - - - - - - - - -HRES

~

IA

~3A

·5V

ISHT 31

74lS00

~

-4 IB

-DISPEN DlY

IJ-

1-:-7--+-----'

~~ ~ ·B/II/

301:'ID:..----........- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - . V I D E D E N A B l E
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Monochrome Display Adapter (Sheet 8 of 10)

25-PINO-SHELL
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.-

Transmit Data

1

.-

Data Terminal Ready

2

-

Request to Send

3

Ring Indicate

4 ..

No Connection

5

Receive Data

6 ..

Data Set Ready

7 ...

--

......

External
Device

Clear to Send
Data Carrier
Signal Ground

28 Monochrome Adapter

...
4 Port Asynch ronous
RS232C Ada pter

...

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10

--- ------------

--_.-

Serial/Parallel
Adapter

Personal Computer
Hardware Reference
Library

ii

Contents

IBM Personal Computer AT Serial/Parallel Adapter .... 1
Serial Portion of the Adapter .................. 1
Programmable Baud-Rate Generator ........... 17
Parallel Portion of the Adapter ................ 19
Specifications ............................. 24
Logic Diagrams ................................ 26

iii

Notes:

iv

IBM Personal Computer AT
Serial/Parallel Adapter
The IBM Personal Computer AT Serial/Parallel Adapter provides
a parallel port and a serial port. It plugs into a system-board
expansion slot. All system-control signals and voltage
requirements are provided through a 2- by 31-position card edge
connector.

Serial Portion of the Adapter
The serial portion of the adapter is fully programmable and
supports asynchronous communications. It will add and remove
start, stop, and parity bits. A programmable baud-rate generator
allows operation from 50 baud to 9600 baud. Five-, six-, sevenand eight-bit characters with 1, 1.5, or 2 stop bits are supported.
A prioritized interrupt system controls transmit, receive, error,
and line status as well as data-set interrupts.
The rear of the adapter has a 9-pin D-shell connector that is
classified as an RS-232C port. When the optional IBM
Communications Cable (9-Pin), which has a 9-pin D-shell
connector on one end and a 25-pin D-shell connector on the
other end, is connected to the adapter, the 25-pin end of the cable
has all the signals of a standard EIA RS-232C interface.
The following figure is a block diagram of the serial portion of the
adapter.

Serial/ParaDel Adapter 1

Address
Decode

Address
Bus

Chip Select
Register
Select

Data Bus
Interrupt

IOscillator

1.8432 MHz

-

----

----.

...

--

--...

--

EIA
Receivers

-

Controller
Asynchronous
Communications
Chip

--...

i

OIIIIIIL

----

...lIIo.

g·Pin
Connector

-

OIIIIIIL

EIA
Drivers

---

Serial Portion Block Diagram

The serial portion of the adapter has a controller that provides the
following functions:

•

Adds or deletes standard, asynchronous-communications bits
to or from a serial data stream.

•

Provides full, double buffering, which eliminates the need for
precise synchronization.

•

Provides a programmable baud-rate generator.

•

Provides modem controls (CTS, RTS, DSR, DTR, RI, and
CD).

Communications Application
The serial output port may be addressed as either communications
port 1 or communications port 2 as defined by jumper J 1 (see the
following figure). In this section hex addresses begin with an X
which can be either a 3 for communications port 1 (interrupt level
4) or a 2 for communications port 2 (interrupt level 3).
2 Serial/Parallel Adapter

Port 2

The data format will be as follows:
DO 01 02 03 04 05 06 07

++ + + ++ + +

Marking

Is~~:t I I I I I I I I I

Parity
Bit

Stop

Bit

Data bit 0 is the first bit to be sent or received. The controller
automatically inserts the start bit, the correct parity bit (if
programmed to do so), and the stop bit (1, 1.5, or 2, depending
on the command in the line-control register).

Controller Specifications
The following describes the function of controller input/ output
signals.

Serial/Parallel Adapter 3

Input Signals
-Clear to Send: (-CTS), Pin 36-The -CTS signal is a
modem-control function input, the condition of which can be
tested by the processor by reading bit 4 (CTS) of the modem
status register. Bit 0 (DCTS) of the modem status register
indicates if the I -CTS I input has changed state since the previous
reading.
I

I

Note: Whenever the CTS bit of the modem status register
changes state, an interrupt is generated if the modem-status
interrupt is enabled.

-Data Set Ready: (-DSR), Pin 37-When low, indicates the
modem or data set is ready to establish the communications link
and transfer data with the controller. The '-DSR signal is a
modem-control function input, the condition of which can be
tested by the processor reading bit 5 (DSR) of the modem status
register. Bit 1 (DDSR) of the modem status register indicates if
the I - DSR I input has changed since the previous reading.
I

Note: Whenever the DSR bit of the modem status register
changes state, an interrupt is generated if the modem-status
interrupt is enabled.

-Data Carrier Detect: (-DCD), Pin 38-When low, indicates
the modem or data set detected a data carrier. The -DCD
signal is a modem-control function input, the condition of which
can be tested by the processor reading bit 7 (DCD) of the modem
status register. Bit 3 (DCD) of the modem status register
indicates if the DCD input has changed state since the
previous reading.
I

I -

I

I

Note: Whenever the DCD bit of the modem status register
changes state, an interrupt is generated if the modem status
interrupt is enabled.

- Ring Indicator: (- RI), Pin 39-When low, indicates the modem
or data set detected a telephone ringing signal. The I - RI I signal
is a modem-control function input, the condition of which can be

4 Serial/Parallel Adapter

tested by the processor reading bit 6 (RI) of the modem status
register. Bit 2 (TERI) of the modem status register indicates if
the I - RI I input has changed from an active to an inactive state
since the previous reading.
Note: Whenever the RI bit of the modem status register
changes from an inactive to an active state, an interrupt is
generated if the modem-status interrupt is enabled.

vee Pin 40-+5 Vdc supply
VSS

Pin 20-Ground (0 Vdc) reference

Output Signals
-Data Terminal Ready: (-DTR), Pin 33-When active, informs
the modem or data set that the controller is ready to
communicate. The DTR output signal can be set to an active
level by programming bit 0 (DTR) of the modem control register
to an active level. The I - DTR I signal is set inactive upon a
master reset operation.
I

I

-Request to Send: (-RTS), Pin 32-When active, informs the
modem or data set that the controller is ready to send data. The
I _ R TS I
output signal can be set to an active level by
programming bit 1 (RTS) of the modem control register to an
active level. The I - R TS I signal is set inactive upon a master reset
operation.
-Output 1: (-OUT 1), Pin 34-User-designated output that can
be set to an active level by programming bit 2 (-OUT 1) of the
modem control register to an inactive level. The -OUT 1 signal
is set inactive upon a master reset operation. Pin 34 is connected
to an active source.
I

I

-Output 2: (-OUT 2), Pin 31-User-designated output that can
be set to an active level by programming bit 3 (-OUT 2) of the
modem control register to an inactive level. The -OUT 2
signal is set inactive upon a master reset operation. Pin 31
controls interrupts to the system.
I

I

Serial/Parallel Adapter 5

ControUer-Accessible Registers
The controller has a number of accessible registers. The system
programmer may gain access to or control any of the controller
registers through the microprocessor. These registers are used to
control the controller's operations and to transmit and receive
data. The X in the register address determines the the port
selected; 3 is for port 1 and 2 is for port 2.
Specific registers are selected according to the following figure:
I/O Address
XF8
XF8
XF8
XF9
XF9
XFA
XFB
XFC
XFD
XFE
XFF

Register Selected
TX buffer
RX buffer
Divisor Latch LSB
Divisor Latch MSB
Interrupt Enable Register
Interrupt Identification Register
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register
Reserved

DLAB State

o (write)
o (read)
1
1
0

Controller-Accessible Registers

Transmitter Holding Register (Hex XF8): The transmitter
holding register (THR) contains the character to be sent.
TrusmlUer Holding Register (hex XF8)
Bit

7 6 543210

~>D'~B;tO
>
>
>
>
>
>
>

Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data BitS
Data Bit 6
Data Bit 7

Transmitter Holding Register

Bit 0 is the least-significant bit and the first bit sent serially.

Receiver Buffer Register (Hex XF8): The receiver buffer
register (RBR) contains the received character.

6 Serial/Parallel Adapter

Receiver Buffer Register (bex XF81
Bit

7 6 543210

~>Da~mtO
>

Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7

>
>
>
>
>
>

Receiver Buffer Register

Bit 0 is the least-significant bit and the first bit received serially.

Divisor Latch LSD (Hex XF8)
Divisor Latch leISt Slgnlflclnt Bit (blx XF81
Bit

7 6 543210

~>mtO
>
>
>
>
>
>
>

Bit 1
Bit 2
Bit3
Bit4
Bit 5
Bit6
Bit 7

Divisor Latch Least Significant Bit

Information about this register may be found under
"Programmable Baud Rate Generator" later in this section.

Divisor Latch MSD (Hex XF9)
Divisor Lltch Most SlgnlflClnt Bit (hex XF91
Bit

7 6 543210

~>.tO
>
>
>
>
>
>
>

Bit1
Bit2
Bit3
Bit4
Bit5
Bit 6
Bit 7

Divisor Latch Most Significant Bit

Serial/Parallel Adapter 7

Information about this register may be found under
"Programmable Baud Rate Generator" later in this section.

Interrupt Enable Register (Hex XF9): This 8-bit register
allows the four types of controller interrupts to separately activate
the chip-interrupt (INTRPT) output signal. The interrupt
system can be totally disabled by resetting bits 0 through 3 of the
interrupt enable register (IER). Similarly, by setting the
appropriate bits of this register to logical 1, selected interrupts can
be enabled. Disabling the interrupt system inhibits the I IER I
and the active I INTRPT I output from the chip. All other system
functions operate normally, including the setting of the line-status
and modem-status registers.
I

I

Interrupt Enlble Register (hex XF91
Bit

7 6 5 4 3 2 1 0
III

L>> ''''",
D,ta A"U .... ''''~~
Enable Tx Holding Register

Empty Interrupt
Enable Receive Line Status
Interrupt
> Enable Modem Status Interrupt
' - - - - - > =0
'------>=0
'------>=0
'------->=0

>

Interrupt Enable Register

Bit 0

When set to logical 1, enables the
received-data-available interrupt.

Bit 1

When set to logical 1, enables the
transmitter-holding-register-empty interrupt.

Bit 2

When set to logical 1, enables the receiver-line-status
interrupt.

Bit 3

When set to logical 1, enables the modem-status
interrupt.

Bits 4-7

These four bits are always logical O.

8 Serial/Parallel Adapter

Interrupt Identification Register (Hex XFA): The controller
has an on-chip interrupt capability that makes communications
possible with all of the currently popular microprocessors. In
order to minimize programming overhead during data character
transfers, the controller prioritizes interrupts into four levels:
receiver line status (priority 1), received data ready (priority 2),
transmitter holding register empty (priority 3), and modem status
(priority 4).
Information about a pending prioritized interrupt is stored in the
interrupt identification register (IIR). (See the figure "Interrupt
Control Functions," later.) The IIR, when addressed during
chip-select time, stops the pending interrupt with the highest
priority, and no other interrupts are acknowledged until the
processor services that particular interrupt.

Interrupt Identlflcltlon Register Ihex XFA)
Bit

7 6 543210

~>> """rr"~ ',"di".
>
>
>
>
>
>

0
Interrupt ID Bit 0
Interrupt ID Bit 1
=0
=0
=0
=0
=0

Interrupt Identification Register

Bit 0

This bit can be used in either hard-wired, prioritized,
or polled conditions to indicate if an interrupt is
pending. When bit 0 is logical 0, an interrupt is
pending, and the IIR contents may be used as a
pointer to the appropriate interrupt service routine.
When bit 0 is logical 1, no interrupt is pending, and
polling (if used) continues.

Bits 1-2

These two bits identify the pending interrupt that has
the highest priority interrupt pending, as shown in
the following figure.

Bits 3-7

These five bits are always logical O.

Serial/Parallel Adapter 9

Interrupt
ID
Register

Interrupt Set And Reset Functions

Bit
2

Bit
1

0

Priority
Level

Interrupt
Type

Interrupt
Source

0

0

0

-

None

None

1

1

0

Highest

Receiver
Line
Status

Overrun Error
or
Parity Error
or
Framing Error
or
Break
Interrupt

Reading the Line
Status Register

1

0

0

Second

Received
Data
Available

Receiver Data
Available

Reading the
Receiver Buffer
Register

0

1

0

Third

Transmitter
Holding
Register
Empty

Transmitter
Holding
Register
Empty

Reading the II R
(if source of interrupt) or writing
into the THR

0

0

0

Fourth

Modem
Status

Clear to Send
or
Data Set Ready
or
Ring Indicator
or
Received Line
Signal Detect

Reading the Modem
Status Register

Bit

Interrupt
Reset Control

-

Line-Control Register (Hex XFB): The system programmer
specifies the format of the asynchronous data communications
exchange through the line control register. In addition to
controlling the format, the programmer may retrieve the contents
of the line control register for inspection. This feature simplifies
system programming and eliminates the need to store line
characteristics separately in system memory.

10 Serial/Parallel Adapter

Ulle C.lllni He,lller (hex XFBI
Bit

7 6 5 4 3 2 1 0

~> Wod
"oglh S,',,' BI' 0
Word Length Select Bit 1
>
>
>
>
>
>

Number 01 Stop Bits
Parity Enable
Even Parity Select
Stuck Parity
Set Break
Divisor Latch Access Bit

Line Control Register

Bits 0, 1

These two bits specify the number of bits in each
serial character that is sent or received. The
encoding of bits 0 and 1 is as follows:
Bit 1

Bit2

0
0

0

1
1

0

7

1

8

1

Word Length (Bits)

5
6

Word length

Bit 2

This bit specifies the number of stop bits in each
serial character that is sent or received. If bit 2 is a
logical 0, one stop bit is generated or checked in the
data sent or received. If bit 2 is logical 1 when a
5-bit word length is selected through bits 0 and 1,
1-1/2 stop bits are generated or checked. If bit 2 is
logical 1 when either a 6-, 7-, or 8-bit word length
is selected, two stop bits are generated or checked.

Bit 3

This bit is the parity-enable bit. When bit 3 is
logical 1, a parity bit is generated (transmit data) or
checked (receive data) between the last data word
and stop bit of the serial data. (The parity bit is
used to produce an even or odd number of 1's when
the data-word bits and parity bit are summed.)

Bit 4

This bit is the even-parity-select bit. When bit 3 is
a logical 1 and bit 4 is a logical 0, an odd number of

Serial/Parallel Adapter 11

logical 1's is sent or checked in the data word bits
and parity bit. When both bit 3 and bit 4 are a
logical 1, an even number of bits is sent or checked.
Bit 5

This bit is the stuck-parity bit. When bit 3 is a
logical 1 and bit 5 is a logical 1, the parity bit is sent
and then detected by the receiver as a logical 0, if
bit 4 is a logical 1, or as a logical 1 if bit 4 is a
10gical0.

Bit 6

This bit is the set-break control bit. When bit 6 is
set to a logical 1, the serial output (SQUT) is forced
to the spacing (logical 0) state and remains there
regardless of other transmitter activity. The
set-break is disabled by setting bit 6 to logical O.
This feature enables the microprocessor to select a
specific terminal in a computer communications
system.

Bit 7

This bit is the divisor-latch access bit (DLAB). It
must be set high (logical 1) to gain access to the
divisor latches of the baud-rate generator during a
read or write operation. It must be set low (logical
0) to gain access to the receiver buffer, the
transmitter holding register, or the interrupt enable
register.

Modem Control Register (Hex XFC): This 8-bit register
controls the data exchange with the modem or data set (an
external device acting as a modem).
Modem Control Reglater Ihex XFCI
Bit

7 6 543210

~>> D~' '"m'",' "'''''
>
>
>
>
>
>

Request to Send
Out 1
Out 2
Loop
=0
=0
=0

Modem Control Register

12 Serial/Parallel Adapter

Bit 0

This bit controls the '-data terminal ready' ( -DTR)
output. When bit 0 is set to logical 1, the -DTR
output is forced active. When bit 0 is reset to logical
0, the '-DTR' output is forced inactive.

Bit 1

This bit controls the '-request-to-send' (-RTS)
output. Bit 1 affects the' -RTS' output in the same
way bit 0 affects the '-DTR' output.

Bit 2

This bit controls the '-Output 1 ' (-OUT 1) signal,
which is a spare the programmer can use. Bit 2
affects the '-OUT 1 ' output in the same way bit 0
affects the '-DTR' output.

Bit 3

This bit controls the '-Output 2' (-OUT 2) signal,
which is a spare the programmer can use. Bit 3
affects the '-OUT 2' output in the same way bit 0
affects the '-DTR' output.

Bit 4

This bit provides a loopback feature for diagnostic
testing of the controller. When bit 4 is set to logical
1, the following occur: the 'transmitter serial output'
(SOUT) is set to the active state; the 'receiver serial
input' (SIN) is disconnected; the output of the
transmitter shift register is "looped back" to the
receiver shift register input; the four modem-control
inputs ( '-CTS " '-DSR', '-RLSD', and '-RI') are
disconnected; and the four modem-control outputs
('-DTR', '-RTS', '-OUT l' and '-OUT 2 ') are
internally connected to the four modem control
inputs. In the diagnostic mode, data sent is
immediately received. This feature allows the
processor to verify the transmit- and receive-data
paths of the controller.
In the diagnostic mode, the receiver and transmitter
interrupts are fully operational, as are the
modem-control interrupts. But the interrupts'
sources are now the lower four bits of the modem
control register (MCR) instead of the four
modem-control inputs. The interrupts are still
controlled by the interrupt enable register.

Serial/Parallel Adapter 13

The controller's interrupt system can be tested by
writing to the lower six bits of the line status register
and the lower four bits of the modem status register.
Setting any of these bits to logical 1 generates the
appropriate interrupt (if enabled). Resetting these
interrupts is the same as for normal controller
operation. To return to normal operation, the
registers must be reprogrammed for normal
operation, and then bit 4 of the MeR must be reset
to logical O.
Bits 5-7

These bits are permanently set to logical O.

Line Status Register (Hex XFD): This 8-bit register provides
the processor with status information about the data transfer.

Line Stltus Register Ihex XFDI
Bit

7 6 5 4 3 2 1 0

~>o'm~~Y
>
>
>
>
>

Overrun Error
Parity Error
Framing Error
Break Interrupt
Transmitter Holding Register
Empty
Tx Shift Register Empty

>
> =0

Line Status Register

Bit 0

This bit is the receiver data ready (DR) indicator. It
is set to logical 1 whenever a complete incoming
character has been received and transferred into the
receiver buffer register. Bit 0 may be reset to logical
o by the processor either reading the data in the
receiver's buffer register or writing logical 0 in it.

Bit 1

This bit is the overrun error (OE) indicator. It
indicates that data in the receiver's buffer register
was not read by the processor before the next
character was transferred into the register, thereby
destroying the previous character. The OE indicator
is reset whenever the processor reads the contents of
the line status register.

14 Serial/Parallel Adapter

Bit 2

This bit is the parity error (PE) indicator and
indicates the received data character does not have
the correct even or odd parity, as selected by the
even-parity-select bit. The PE bit is set to logical 1
upon detection of a parity error, and is reset to
logical 0 whenever the processor reads the contents
of the line status register.

Bit 3

This bit is the framing error (FE) indicator. It
indicates the received character did not have a valid
stop bit. Bit 3 is set to logical 1 whenever the stop
bit following the last data bit or parity bit is detected
as a zero bit (spacing level).

Bit 4

This bit is the break interrupt (BI) indicator. It is set
to logical 1 whenever the received data input is held
in the spacing state (logical 0) for longer than a
full word transmission time (that is, the total time of
start bit + data bits + parity stop bits).
Note: Bits 1 through 4 are error conditions that
produce a receiver line-status interrupt whenever
any of the corresponding conditions are detected.

Bit 5

Bit 6

This bit is the transmitter holding register empty
(THRE) indicator. It indicates the controller is
ready to accept a new character for transmission. In
addition, this bit causes the controller to issue an
interrupt to the processor when the TRHE interrupt
enable is set active. The THRE bit is set to logical 1
when a character is transferred from the transmitter
holding register into the transmitter shift register. It
is reset to logical 0 when the processor loads the
transmitter holding register.
This bit is the transmitter empty (TEMT) indicator.
It is set to logical 1 whenever the transmitter holding

request (THR) and the transmitter shift request
(TSR) are both empty. It is reset to logical 0
whenever THR or TSR contains a data character.
Bit 7

This bit is permanently set to logical O.

Serial/ParaDel Adapter 15

Modem Status Register (Hex XFE): The 8-bit MSR provides
the current state of the control lines from the modem (or external
device) to the processor. In addition, four bits of the MSR
provide change information. These four bits are set to logical 1
whenever a control input from the modem changes state. They
are reset to logical 0 whenever the processor reads this register.

MI~lm

Bit

Stltus RIglstlr Ihlx XFEI

7 6

5 4 3 2 1 0

~>> Delta
Delta mea<" Se'"
Data Set Ready
> Trailing Edge Ring Indicator
> Delta Data Carrier Detect
> Clear to Send
> Data Set Ready
> Ring Indicator
> Data Carrier Detect

Modem Status Register

Bit 0

This bit is the delta c1ear-to-send (DCTS) indicator.
It indicates the I -CTS I input to the chip has
changed state since the last time it was read by the
processor.

Bit 1

This bit is the delta data-set-ready (DDSR)
indicator. It indicates the '-DSR input to the chip
has changed state since the last time it was read by
the processor.
I

Bit 2

This bit is the trailing-edge ring-indicator (TERI)
detector. It indicates the RI input to the chip has
changed from an active condition to an inactive
condition.
I -

Bit 3

I

This bit is the delta data-carrier-detect (DDCD)
indicator. It indicates the '-DCD input to the chip
has changed state.
I

Note: Whenever bit 0, 1, 2, or 3 is set to a logical
1, a modem status interrupt is generated.

16 Serial/Parallel Adapter

Bit 4

This bit is the opposite of the '-clear-to-send'
(-CTS) input. If bit 4 of the MCR loop is set to a
logical 1, this bit is equivalent to RTS of the MCR.

Bit 5

This bit is the opposite of the ' -data-set-ready ,
(-DSR) input. If bit 4 of the MCR is set to a logical
1, this bit is equivalent to DTR of the MCR.

Bit 6

This bit is the opposite of the '-ring-indicator'
(-RI) input. If bit 4 of the MCR is set to a logical 1,
this bit is equivalent to OUT 1 of the MCR.

Bit 7

This bit is the opposite of the '-data-carrier-detect'
(-DCD) input. If bit 4 of the MCR is set to a logical
1, this bit is equivalent to OUT 2 of the MCR.

Programmable Baud-Rate Generator
The controller has a programmable baud-rate generator that can
divide the clock input (1.8432 MHz) by any divisor from 1 to
655,535 or 2 16_1. The output frequency of the baud-rate
generator is the baud rate multiplied by 16. Two 8-bit latches
store the divisor in a 16-bit binary format. These divisor latches
must be loaded during setup to ensure desired operation of the
baud-rate generator. When either of the divisor latches is loaded,
a 16-bit baud counter is immediately loaded. This prevents long
counts on the first load.

Serial/Parallel Adapter 17

Pin Assignment for Serial Port
The following figure shows the pin assignments for the serial port
in a communications environment.

9

-

-

--

External
Device

-

Carrier Detect

1

Receive Data

2_

Transmit Data

3

Data Terminal Ready

4

Signal Ground

5

Data Set Ready

6_

Request To Send

7

Clear To Send

8_

Ring Indicator

9_

-

18 Serial/Parallel Adapter

--

Serial
Parallel
Adapter

-

-

Parallel Portion of the Adapter
The parallel portion of the adapter makes possible the attachment
of various devices that accept eight bits of parallel data at
standard TTL levels. The rear of the adapter has a 25-pin,
D-shell connector. This port may be addressed as either parallel
port 1 or 2. The port address is determined by the position of
jumper J2, as shown in the following figure.

Port 1

Serial/Parallel Adapter 19

The following figure is a block diagram of the parallel portion of
the adapter.

Address
Bus

--

Data
Bus

--. ...-

Address
Decode

--

----...
--

Buffer
Control
Signals

Interrupt

~

Data
Output
Buffer

~

Control
Output
Buffer

-..

r---

25-Pln 0
Connector

..

-

-...
...

-

Data
Wrap
Buffer

Control Wrap
and
Signal Input

..~

Parallel Portion Block Diagram

Printer Application
The following discusses the use of the parallel portion of the
adapter to connect to a parallel printer. Hexidecimal addresses in
this section begin with an X, which is replaced with a 3 to indicate
port 1, or a 2 to indicate port 2.

Data Latch (Hex X78, X7C)
Writing to this address causes data to be stored in the printer's
data buffer. Reading this address sends the contents of the
printer's data buffer to the system microprocessor.

Printer Controls (hex X7 A, X7E)
Printer control signals are stored at this address to be read by the
system microprocessor. The following are bit definitions for this
byte.

20 Serial/Parallel Adapter

Bit 7

Not used

Bit 6

Not used

Bit 5

Not used

Bit 4

+ IRQ Enable-A 1 in this position allows an interrupt
to occur when '-ACK I changes from true to false.

Bit 3

+SLCT IN-A 1 in this bit position selects the printer.

Bit 2

-INIT-A 0 starts the printer (50-microsecond pulse,
minimum).

Bit 1

+AUTO FD XT-A 1 causes the printer to line-feed
after a line is printed.

Bit 0

+STROBE-A O.S-microsecond minimum, high, active
pulse clocks data into the printer. Valid data must be
present for a minimum of 0.5 microsecond before and
after the strobe pulse.

Printer Status - Address X79, X7D
Printer status is stored at this address to be read by the
microprocessor. The following are bit definitions for this byte.
Bit 7

-BUSY-When this signal is active, the printer is busy
and cannot accept data. It may become active during
data entry, while the printer is offline, during printing,
when the print head is changing positions, or while in an
error state.

Bit 6

-ACK-This bit represents the current state of the
printer's I-ACK I signal. A 0 means the printer has
received the character and is ready to accept another.
Normally, this signal will be active for approximately 5
microseconds before I-BUSY I stops.

Bit 5

+ PE-A 1 means the printer has detected the end of
paper.

Serial/Parallel Adapter 21

Bit 4

+ SLCT-·A 1 means the printer is selected.

Bit 3

- Error-A 0 means the printer has encountered an error
condition.

Bit 2

Unused.

Bit 1

Unused.

Bit 0

Unused.

22 Serial/Parallel Adapter

Parallel Interface
The adapter has a 2S-pin, D-shell connector at the rear of the
adapter. The following figure shows the signals and their pin
assignments. Typical printer input signals also are shown.

-

- Strobe

Elt~rna I

Device

Data Bit 0

2

Data Bit 1

3

Data Bit 2

4

Data Bit 3

5

Data Bit 4

6

Data Bit 5

7

Data Bit 6

8

Data Bit 7

9

- ACK
8USY

11
12

SLCT

13 ..
14

- ERROR

15

-INIT

16

- SLCT IN
Ground

Serial
Parallel
Adapter

10

PE

- AUTO FEED XT

-

1

17
18-25

I--

Serial/ParaDel Adapter 23

Specifications
The following figures list characteristics of the output driver.
Sink current
Source current
High-level output voltage
Low-level output voltage

24 rnA
-2.6 rnA
2.4 Vdc
0.5 Vdc

Max
Max
Min
Max

Parallel Data and Processor IRQ
Sink current
Source current
High level output voltage
Low level output voltage

16 rnA
0.55 rnA
5Vdc
0.4 Vdc

Max
Max
Minus pull-up
Max

24 rnA
-15 rnA
2.0 Vdc
0.5 Vdc

Max
Max
Min
Max

Parallel Control
Sink current
Source current
High level output voltage
Low level output voltage

Parallel Processor Interface (except IRQ)

The following are the specifications for the serial interface.
Function

Condition

On

Spacing condition (binary 0, positive voltage).

Off

Marking condition (binary 1, negative voltage).

Voltage
above +15 Vdc
+3 Vdc to +15 Vdc
-3 Vdc to +3 Vdc
-3 Vdc to -15 Vdc
Below -15 Vdc

Function
Invalid
On
Invalid
Off
Invalid

Serial Port Functions

24 Serial/Parallel Adapter

(SHT2)
(SHT 3)

~

o
(JQ

RA

-----;;- AO

AO
AI
Al

AlO AI
AlO AZ

~~

A28 A~
Al7 A4
Alb A~

b IS
7

g

A2'i Ab

UI4

1'3

0"

14

1 14

01

II:)

1+

A24 A7

IBI~

AO

All

AEN

-----!"
~IOHel

P

NCZ

~BZI

:~~'

~

(SHT 2)

~B2~

Al~ NJ

BOO
BDI
BDZ

I~

07,8 A

...

rI1

Z4~

.~

~
(JQ
~

>W--

"I I"

AO~~
A04rot-

....
~
....
~

a

NO*-M:
N/C
NC4
NC~ >'-'----N/C

~ABII
DZ
gH UI7 :~

AOb~

~BZ4

(SHT3)
(SHT2)

'--LS

~BZS

- ENABLE SER I/O
PARALLEL I
NAB

17
--JIB

I

Aooi\
AOB~
A07~

(SHT31
(SHT3)
(SHT 2)

-

OZ~

~Ib

A22

(SHT 2.3)
(SHT2.3)
(SHT3)

BD~

BD4

:~

B

BD~

BOb
BD7

12

(SHT 2.3)
(SHT 2.3)
(SHT 2.3)
(SHT 2,3)
(SHT2.3)
(SHT 2.3)
(SHT 2.3)
(SHT 2.3)

~~
7J1
('D

~ UI~

Z

I UtI:)

b
LS04

LSQ4

:I.

BIOR

e.

"

814

4

, UtI:)

'i Ulb

b

BIOif

BI~ I6W
II Ute;

(SHT 2.3)
(SHT 2.3)
(SHT2)

ISHT 3)

LSQ4

lOW

B02 RESET

RESET

10

(SHT2.3)

(SHT 2)

LS04
RESET

~~

+IZ

+15

B2ol-!2---'
801
B~I

('D

N
Ul

lOR

LSD4

i-

t..

BA8

iii

-

~

GND
BIO
-IZ
R07

t f(

+

(II
KlAiF

+

el2
IO.OuF

GND

ZI

iO.DI.IF

(I

\

1'Z

J4

TO T

CB

v

.047uF

Co

T

CIO
I

(SHT3)

~~~7UF

"

.047uF

Serial/Printer Adapter (Sheet 1 of 3)

VOLTAGE AND
GND BUSES
}

'LSI'>'>

N
CtI

r----;;;~

~~~ ~

(SHT 1) - ENABLE F\\RAlLEL 110 I" 2(

~

:I.
e.
.........

(SHT
(SHT
(SHT
(SHT

1)
1)
1)
1)

~

AI
BiOR

:~ 2Gm~
3
I

~

UI2

:~~

I(

IV2

LL: IG

In

'----

I>RPB

"·RP(

~N/(

P2
Z" PIN
'0' SHal

O. (13 -(20
(9X).0022 uF

-~

(~R

.J.
(3

i..

7"

~~
~~

20
70

ri"O

V ~I>D
V BOI> 730
B07
II

~

4D
elK

BE

BQ 19
IQ 2
2Q"
7Q II>
"Q 12
I>Q '"
3Q I>
~Q 9

f-~
'---~ OATAO

II>
I.,

~

"

~

I>
B

~ OATA~

q

UIB
/

~"'
13

BOO
BOI
B02
B03

BOO
BOI
BOZ
1) B03
1) B04
1) BD"
1) BOI>
1) BD7

(SHT1)
(SHT
(SHT
(SHT
(SHT
(SHT

(SHT 1)

~

BOO

ID

~ I>D

7777-

BO~

BD.,
BOb
BD7

l

RESET

"/ am

27n

~--RNI

L

UI'>

I

qUIl

;

DATA 7

~

~~

-

:::r::
if'"

"~I>
V

12

ZV~ 3

i

a

II>

(SHT 1)

(SHT 1)
(SHT1)
(SHT 1)

IRQ"

LSO~

-INIT

II UII>

~

-SlCT IN
+Sl(T

n

i

II

:

12

10

V

,~04

I

IRQ7
BAa

J2

n....l'LJ

V

+BUSV

-

Serial/Printer Adapter (Sheet 2 of 3)

IVI
I V~

1~2AZ

~
IZ

In:~

V

•

V

I"ZAIIY2

~IG

<" "'

'---

LS04

lUll>

~10

2

q UI

a

l/{SI2.,
pvv-04.7K

---

2Y2~

17 2A4

UII>

-A(K

'5

-------

V

2V4*

I> IA3

L-~ IA~

~

+PE

4.7K

------------

~ 2G

I r----i-::~ ~~~~

8

,5

7
I>

~

"pr-'f
q U Ib

-IRQ EN

I~

2
3
4

V
V

.,

-AUTO FO XT

PARA 8

A8

BO~

-ERROR

+ IRQ EN

(SHT I)

BOZ
B03

BO.,
BOI>
B07

~SI2"
UI

LS04

4

'''~

U9

-STROBE

i

::::=::IL:
3 Ulb

BOO

IVI IB
In I~
ZB "
ZVI 9
ZVZ 7
IYZ II>
IY~ IZ

I>
2

3Qr--

I

g:i:i

~

10

a"
~'"
"~
~~c

~
+"v

A"

II UII

~4
n

2 Q .,

4.7Kn-----....

12

13

2D

\im;~~D
BD" I

IQ 2
bQ I

12

UII

~

17 2A~
2 IA I
I> IA3
I'> ZA3
II 2AI
13 ZAZ
~ IA2
B lA4

DATAl

~ g:i:~

14
10
12
II

"

19

f-~

f-~

I
Z
3
7

f-~

f-~

(IB (20

f->---#--.

~-

(SHT1)
(SHT 1)

(I~

UI9
(BX) 27n

~

~BO
~~ 10

(19 (I'> (13 (17 (II>

3

RP 1

-----

4

~

12 UI

II

lS12.,

~

1/

c

1°

IRQl

(SHT 1)

c

I"

IRQ4

(SHT 1)

o +,)V
(SHT 1)

SER A8

U2
7

(SHT 1)

'<;1

RESET

HR

IHTRPT 10

es OUT 24

Hie

0015 Z1

Hie

HIe 20

Hie

DTR 11

ml
(SHT1)

~'

BIeR

:~~~~: :~
:~~~~:
~

:So

26

U2
(SHT 1)

:~

12 eso
14

-ENABLE SER [/0

a

~
U2

SOOTI"

Hie

,

'I

m

+C;Vo

U2 II)~
Hie

!~

~

.......

SIG GND,<;

,

E[A TX DATA '1

N/e

XTAL 2

.........

i

EIA RTS '7

~

=tr=

11 eSI

+<;V

00

+W

DlSTR

~~:m

A2

12-DSR
12

+<;V
Rl

,.;on

L.....!:.l...... J

RECE[VE DATA

Serial/Printer Adapter (Sheet 3 of 3)

Notes:

28 Serial/Parallel Adapter

s : :~~~ TECHNICAL NEWSLETTER
for the

IBM RT PC
Hardware Technical Reference
©

Copyright International Business Machines Corporation 1986

-OVER-

SN20-9844
75X1073
June 1987
© Copyright IBM Corp. 1987

84X0875
Printed in U.S.A.

Update Kit Contents
This kit contains:
1. Volume III binder
2. Updates to Volumes I and II
3. Information for new RT PC adapters.

Notes
Replace the following pages in volume I with TNL pages supplied.
1. Replace pages iii through xiv with new TNL pages iii through xiv in the front of
volume 1.
2. Replace Section 2. Processor Board \vith nevI T}'JL Section 2. Processor Board
3. Replace Section 3. Memory Boards with new TNL Section 3. Memory Boards
4. Replace Section 4. Floating-Point Accelerator with new TNL Section 4. Floating-Point
Ac~elerator.

5.
6.
7.
8.
9.
10.

Replace pages 5-27 through 5-28 with new TNL pages 5-27 through 5-28.
Replace pages 5-63 through 5-64 with new TNL pages 5-63 through 5-64.
Replace pages 6-17 through 6-20 with new TNL pages 6-17 through 6-20.
Replace pages 6-47 through 6-62 with new TNL pages 6-48 through 6-64.
Replace Section 7. System IPL ROM with new TNL Section 7. System IPL ROM.
Replace Section 8. System Compatibility with new TNL Section 8. System
Compatibility.
11. Replace pages 11-13 through 11-16, 11-81 through 11-82, and 11-87 through 11-88 with
new TNL pages 11-13 through 11-16, 11-81 through 11-82 , and 11-87 through 11-88.
12. Replace Appendix A. with new TNL Appendix A.
13. Replace Glossary and Index with new TNL Glossary and Index.

Add Appendix B. Advanced Processor Board to Volume I.
Replace the following adapters in Volume II.
1. Replace ESDI Magnetic Media Adapter with new TNL ESDI Magnetic Media Adapter.
2. Replace Extended Monochrome Graphics Adapter with new TNL Extended
Monochrome Graphics Adapter.
3. Replace RS-422A Adapter with new TNL RS-422A Adapter.
4. Replace RS-232C Adapter with new TNL RS-232C Adapter.
June 1987

Add the following adapters to Volume II or Volume III.
1. Extended Enhanced Small Device Interface (HESDI) Adapter
2. Small Computer System Interface (SCSI) Adapter.
3. Extended Monochrome Graphics Display.
Replace pages 27 and 28 of the Monochrome Display and Printer Adapter in Volume II
with new TNL pages 27 and 28.
New divider tabs are provided for Volumes II and III. You may want to organize the
information using these dividers and redistribute the adapters in Volumes II and III.
Please file this cover letter at the back of the manual to provide a record of changes.

SN20-9844
75X1073
June 1987
© Copyright IBM Corp. 1987

84X0875
Printed in U.S.A.

©Copyright
International Business
Machines Corporation , 1987
All Rights Reserved
Printed in the
United States of America
References in this
publication to IBM
products or services do not
imply that IBM intends
to make them available
outside the United States .
84X0873

---- ----~
----------- -,

- -



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