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FLOATING POINT SYSTEMS, INC. Programmers Reference Manual Part Twa 860-7319-000 by FPS Technical Publications Staff Prograrntners Reference Manual PartT\No B60-7319-000 1st Edition, January 1978 Publication No. FPS-7319 NOTICE The material in this manual is for information purposes only and is subject to change without notice. Floating Point SYstemsJ Inc. assumes no responsibility for any errors which may appear in this publication. Copyright (S) 1978 by Floating Point Systems, Inc. Beaverton, Oregon 97005 All rights reserved. No part of this publication may be reproduced in any form or by any means without written permission from the publisher. Printed in U.S.A. Table of Contents AP-l20B Instruct10ns Unconditional Fields Each of the following fields may be used in any given instruction word. IField B SOP 0 NOP 1 2 3 & SOPl SPEC AOD SUB MOV AND OR . EQV I Name SOPl SH Nap WRTEXP WRTHMN . WRTLMN NOP NOP NOP NOP CLR INC DEC COM LOSPNL LOSPE LDSPI LOSPT NOP L RR . R IOctal Code • E-13 4 5 6 7 • E-23 · E-17 · £-18 · £-19 · E-20 · £-21 • E-22 10 11 12 13 14 15 16 17 Field Name Octal Code a to 17 SPS (S-Pad Source Reg.) SPO (S-Pad Oest. Reg.) (0-17) (0-17) • E-23 · E-24 · E-24 . E-14 ·E-16 . E-15 I · £-25 · E-25 · E-26 · E-26 · E-27 • E-28 · E-29 · E-30 S-Pad Timing Rules . . . • £-12 Field Name Octal Code FAOO 0 6 FADOl FSUSR fSUB FA DO FEQV FAND FOR 7 10 1 2 3 4 5 I FADOl Al A2 I · · • • · · • · £-86 £-81 £-81 E-82 E-83 £-84 £-85 £-101 NOP FIX I FIXT • E-86 • E-87 FSeLT FSM2C F2eSH FSeALE FABS · E-89 · £-90 • £-88 • E-91 · E-92 E - 1 Ne fM . DPX Opy TM . ZERO ZERO ZERO • £-93 · E-93 · £-93 · E-93 · £-94 • E-94 NC fA . OPX DPY MD ZERO MDPX £OPX ·£-95 .E-95 'E-95 -E-95 '£-96 ·E-96 ·£-96 ·E-96 Unconditional Fields Each of the following fields may be used in any given instruction word. Field Name Octal Code 0 1 2 3 4 5 6 7 10 11 12 13 14 15 16 17 Field Name Octal Code 0 1 2 3 4 5 6 7 Field Name Octal Code CONO DISP (Branch Displ acement) NOP (0-37) £-68 £-69 E-70 E-70 E-71 E-71 E-72 E-73 E-74 E-75 E-76 E-77 E-78 E-79 E-80 if BR 8INTRQ . BION BIOI BFPE RETURN BFEQ BFNE BFGE SFGT • SEQ SNE BGE BGT 0 NOP DB • FA • NOP DB . FA FM. · £-123 · £-124 · E-125 I i . £-126 i I . E-127 E-128 FM. o I I XR (DPX Read Index) YR (OPY Read Index) XW (OPX Write Index) YW (OPY Write Index) ZERO .. E-129 INBS .. E-130 VALUE* . E-131 E-132 OPX Opy E-133 MD .. . E-134 E-135 SPFN • E-136 TM .• (0-7) (0-7) (0-7) (0-7) NOP FMUL Ml M2 MI MA OPA TMA NOP INCMA •• E-140 • E-141 OECMA • E-142 SETMA NOP INCOPA • . E-143 E-144 OECOPA SETOPA . . E-145 NOP INCTMA . .E-146 OECTMA . .E-147 SETTMA . . E-148 OPBS FM ... FM •. 1 OPX Opy TM. 3 DPY I 0 2 DPX o · E-99 · E-99 • E-99 E-99 • · · FA . . • E-I00 DPX . • E-I00 Opy · •. £-100 • E-100 MO '. NOP FA • . . • E-137 FM. DB • • • E-138 E-139 o 0 o *This instruction uses a 16-bit immediate VALUE as a constant or address (in bits 48-63 of this instruction). The YW. FM. MI. M2. MI. TMA. and CPA fields are then disabled for this instruction word. SPEC Fields One of the SPEC Fields may be used per instruction word. The S-Pad Fields (B. SOP. SOPI. SH. SPS. and SPD) are then disabled for this instruction. Field Name SETPSA HOSTPNl STEST SPEC Octal Code . • •• E-31 · .. • E-39 · . · . • E-6 5 STEST · HOSTPNl SPMOA NOP NOP NOP 6 HOP 0 1 2 3 4 7 10 11 12 13 14 15 16 17 Field Name NOP SETPSA ••• · • £-45 PSEVEN • • . £-52 PSODD . . • E-55 PS •• · . • E-58 SETEXIT · E-66 NOP NOP NOP BFLT BlT BNC BZC BDBN BDBZ BIFN BIFZ NOP NOP NOP Nap BFLO BFLl BFL2 BFL3 PSEVEN PSODD ·. · · ·. ·.. · . • • E-31 · . · . • E-32 · . • • E-33 .. · . • • E-34 . · . • • £-35 • · .. • • E-36 • · . • • E-37 •. • • •••• £-37 • • • • · . · . • E-38 · .. • • E-38 · . • • E-38 · . • .• E-38 PNllIT DBELlT DBHLIT DBllIT NOP NOP NOP NOP SWDB • SweSE SwaBH SweBL Nap NOP Nap HOP ·. ·. •• • E-39 . • . £-39 . • • E-40 .• • •. E-40 ·. · • ·E-41 . •£-42 · ·£-43 • .E-44 · PS · .. • .E-45 · . · .E-46 · . • .E-47 · .. .£-47 · .. · .£-48 · . .E-48 · . · .E-49 · . ••• E-50 JMPA* JSRA* JMP* •• JSR* . JMPT • JSRT • JMPP •• JSRP • NOP NOP Nap Nap NOp Nap Nap Nap SETEXIT Octal Code 0 1 2 3 4 S 6 7 10 11 12 13 14 15 16 17 RPSOA* RPS2A* RPSO* RPS2* RPSOT RPS2T NOP NOP WPSQA* WPS2A* wpso* WPS2* WPSOT WPS2T HOP NOP · . • • E-52 · . • • E-52 · . · . • E-52 · . • •• E-52 · . • •• E-52 · .. • • E-53 • • ·. • • • E-53 •• • •• E-53 • E-54 • E-54 • . . E-54 • • E-54 · ... · .. · · · .. RPSIA* RPS3A* RPSl* RPS3* RPSlT RPS3T NOP NOP WPSIA* WPS3A* WPSl* WPSl* WPSIT WPS3T NOP Nap ·. • • • E-55 •• • •• E-55 • •••• E-55 • • E-55 • • E-56 · • E-56 · .. · .. ... . • • E-56 · . • E-56 · .. • • E-57 · .. • • E-57 · .. • • E-57 · .. • • E-57 . · •• RPSLA* RPSFA* RPSL* RPSF* RPSLT RPSFT RPSLP RPSFP LPSLA* LPSRA* LPSl* LPSR* LPSLT LPSRT LPSLP lPSRP . . · . · 'E-58 · . · ·E-59 · .. • . E-60 · . • . E-60 · . • ·E-60 • • ·E-61 · . • •• E-61 · ... · E-61 •• • . E-62 .• • . 'E-63 · 'E-64 .. · 'E-64 . 'E-64 . • • 'E-65 'E-65 'E-65 · .. · · · ·.·. ·.·. NOP SETEXA* NOP ·. . • .E-66 NOP SET EXT . · . • .E-67 Nap SETEXP ••• • .E-67 Nap HOP HOP NOP Nap NOP NOP NOP SET~X* Formats for partial words (PSEVEN. PSODD. PS Fields) • . . . E-51 *This instruction uses a 16-bit integer VALUE (in bits 48-63 of the instruction Word). The YW. FM, Ml, H3, HI, HA, THA, and DPA Fields are then disabled for this instruction word. E - 3 • .E.-66 I/O Fields One of the I/O Fields may be used per instruction word. The Floating Adder Fields· (FADO. FAODI. AI. and A2) are then disabled for this instruction word. Field Name Octal Code 0 LOR£G 1 RC~£G 2 SPt-1DAV REX IT 3 4 5 6 7 Field Name Octal Code 0 1 2 3 4 5 6 7 LOREG ROR£G NOP LDSPD LDMA . LOTMA LOOPA LOSP • LOAPS lOOA . RPSA . RSPD . I/O • £-101 · £-105 • £-7 - £-7 - £-109 - £-115 • E-121 I HOur SENSE FLAG • CONTROL -E-3 · £-101 - £-101 - £-102 · E-I02 - £-103 - £-103 RHA RTHA • ROPA _ RSPFN RAPS ROA • £-103 FLAG SENSE SNSA . SPINA SNSAOA SPNAOA SNSB . SPINS SNSSOA SPNSOA SFLO SFLl SFL2 SFL3 CFLO CFLl CFl2 CFL3 - £-115 - £-115 • E-115 • E-115 · £-118 • £-118 • E-119 • £-120 • . • . Nap INOUT OUT SPNOUT . OUTOA SPOTOA IN _ '£~105 '£-105 '£-106 '£-106 '£-107 '£-107 SPININ INOA . SPINOA . '£~108 '£-lOB CONTROL _ • • . _ HALT. IORST INl£N INTA _ REFR • WRT£X WRTMAN NOP • £-121 · £-121 · E-121 - £-121 • £-122 • E-122 • - £-122 · £-122 '£-8 -E-9 '£-9 ·£-10 ·£-10 '£-11 ·£-11 • • • • • • £-5 AP-120B Instruction Field Layout 0 1 2 alsop 3 5 4 lSH 6 I 7 8 9 10 11 12 1 I SPS 14.15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SPD I 1'.1 FADO I A2 I IsoPl l I ISPEC OPER , DISP Branch Group Adder Group S-Pad Group I COND FADDl l I/O 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 5S 56 57 58 59 60 61 62 63 DPX I Opy I Data DPBS XR YR \xw I YW Pad Group FHI H1 I H2 HI IHA IOPA Multiply Group Hemory Group I E - 4 VALUE ITHA '£-107 ·£-109 '£-110 '£-111 -E-112 -E-112 ·£-113 '£-114 o 63 "i MANDATORY FIELDS . -.-;, " OPTIONAL FIELDS DISABLED FIELDS value all zeros NOP No-operation Assembler format: NOP Effect: No operation is performed Description: The assembler recognizes this mnemonic and will insert an all zeros instruction which is a NOP. E - 5 CONTROL (from SPEC MANDATORY FIELDS OPTIONJU, FIE:LDS DISABLED FIELDS IALUE 2 SPMDA SPIN WHILE MAIN DATA BUSY Assembler Format: SPMDA Effect: "SPIN" while MAIN DATA BUSY Description: When specified, SPMDA causes the AP-l20B to suspend program execution until MAIN DATA MEMORY (MD) completes its READ or WRITE cycle a.nd becomes available for the next READ/WRITE operation. Using this op-code in an instruction immediately following one that initiates an MD READ operation, results in the data from that operation being available for use during the present instruction. It has no effect on a MD READ/WRITE operation in the same instruction. Thus: LDMA; DB=lOO SPMDA; DPX(O)(Brackets indicate optional use with S-PAD operations.) Effect: Example: Effect: BIT-REVERSE(SP ADD & 6,5 SPS )-+ SOURCE INPUT FOR CURRENT S-PAD OPERATION Description: The contents of the S-PAD SOURCE REGISTER (SP(SPS]) are BIT-REVERSED and shifted before being used as the SOURCE OPERAND in the current S-PAD operation. The number of shifts performed depends on the S1ze of the complex data array being processed. The programmer must load the applicable shift value into the BIT-REVERSE field of the APSTATUS Register before specifying the BIT-REVERSE operation. (See S-PAD SUMMARY BIT-REVERSE FIELD for more details.) (See also APSTATUS S~~Y.) E - 13 SHIFT FIELD t:-:--:r-- 5 6 7 8 9 10 11 12 13 ---r----y-------.------i SPS SOPl SPD ·i .... * MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS * MAY BE USEP WITH EITHER SOP OR SOP1 FIELDS VALUE No Operation LEFT SHIFT S-PAD OUI'PUI' (SPFN) ONCE. 1 Assembler Format: (Brackets indicate optional use with S-PAD operations) Example: Effect: ZERO FILL. SPFN~ SUBL 5,6 LEFT SHIFTED ONCE~ SPFN Description: The S-PAD RESULT (SPFN) is logically shifted left one place. The right-most bit is set to zero. The bit shifted off the left end is stored in the S-PAD CARRY BIT, (C) - overriding any carry that resulted from the specified arithmetic operation. Excepting possible OVERFLOW, the shift has the effect of a multiplication by two. The carry bit (C), bit 7 of the AP INTERNAL STATUS REGISTER (APSTATUS), may be tested during the next instruction cycle. SPFNI E - 14 ~~ SHIFT FIELD (SH) 5 --,----- 6 7 8 9 10 11 12 13 -------r------~ SPD SPS soP 1 * ..... ~ MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS * MAY BE USED WITH EITHER SOP OR sopl FIELDS VALUE RIGHT SHIFT S-PAD FUNcrION (SPFN) ONCE. ZEro FILL. 2 Assembler Format: (Brackets indicate optional use with S-PAD operations) Example: Effect: SUBR 5,6 SPFN right-shifted once+ SPFN Description: The S-PAD RESULT (SPFN) is logically shifted right one place. A zero is shifted into the left-most bit. The bit shifted off the right end is set into the S-PAD CARRY BIT. The instruction has the effect for unsigned numbers, of a division by two. Bit C of the AP INTERNAL STATUS REGISTER (bit 7, APSTATUS) reflects the condition of S-PAD CARRY and may be tested during the next instruction cycle. 15 SPFN ~G E - 15 SHIFT FIELD 5 ~~------~--~ 6 7 8 9 10 11 12 13 SPD SPS SOP 1 ....' MANDATORY FIELDS i· DISABLED FIELDS OPTIONAL FIELDS * MAY BE USED WITH EITHER SOP OR SO~1 FIELDS VALUE RIGHT SHIFT S-PAD FUNCTION (SPFN) twice. Zero fill. 3 Assembler Format: (Brackets indicate optional use with S-PAD operations) E~ample: SUBRR 5,6 SPFN -+ right shifted twice+ SPFN Effect: Description: The contents of the, S-PAD ALU RESULT are logically shifted right two times before being enabled onto the SPFN data path. Zeros are filled into 'the left-most two bits. The second bit shifted off the end is set into the S-PAD ALU CARRY BIT. The instruction has the effect for unsigned numbers of a division by four. Bit C (bit 7) of the AP INTERNAL STATUS REGISTER (APSTATUS) reflects the condition of the S-PAD CARRY BIT and may be tested during the next instruction cycle. ( 15, _ SPFN ~~ L--J • REFLECTS THE CONTENTS OF THE ~ SECOND BIT SHIFTED "OFF THE END" FIRST BIT SHIFTED nOFF ,THE END" IS LOST E ... 16 S-PAD OPERATIONS FIELD ~ SPD ... . ' MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE Y' 1 See, S-PAD OPERATIONS 1 See, SPECIAL OPERATIONS 2 ADD S-PAD SOURCE REGISTER AND S-PAD DESTINATION REGISTER Assembler Format: ADD < # > < & > SPS, SPD Effect: (SP SPS ) t SPFN+(SP Description: plus (SP SPD tt SPD )+ SPFN ) unless S-PAD NO-LOAD(#) is specified The contents of S-PAD SOURCE REGISTER (SP with the contents of S-PAD DESTINATION REGISTER (SP ) are added sPS ). The result SPD of the operation, (SPFN) is stored back into the specified S-PAD DESTINATION REGISTER unless an S-PAD NO-LOAD (#) is specified. Appropriate bits are set in the AP INTERNAL STATUS REGISTER (APSTATUS) and may be tested during the next instruction cycle. CARRY BIT EQUATION: t (SP sPS If (SP SPD) + (SP SPS) ~ 2 16 then carry=l ) may be optionally BIT-REVERSED, (see BIT-REVERSE FIELD) tt SPFN from the ADD may be optionally shifted, (see SHIFT FIELD) E - 17 S-PAD OPERATIONS FIELD ~_r-_~---::"''''''''''_''':'_r-'-6 7 8 9 l_~-.l~-.!2 SPD H Wj MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE SUBtract S-P.AD SOURCE REGISTER fran S-PAD 3 DESTINATION REGISTER Assembler Format: SUB< sh >< # > Effect: (SPSPD)minus (SP SPFN+ (SP SPD < & > sps, spd ·t sPS ) +SPFN tt ; ) unless S-PAD NO-LOAD (#) is specified Description: The contents of the S-PAD SOURCE REGISTER are subtracted from the contents of the S-PAD DESTINATION REGISTER. The result of the operation is stored back into the S-PAD DESTINATION REGISTER unless a S-PAD NO-LOAD (#) is specified. Appropriate bits (N,Z,C) are set in the AP INTERNAL STATUS REGISTER (APSTATUS) and may be tested during the next instruction cycle. 16 CARRY BIT EQUATION: If (SP[SPD])+(SPlSPS])+l ~ 2 then C=l else O. If a shift is specified, then C is set to the carry from that shift. t(SP[SPS]) may be optionally BIT-REVERSED. See BIT-REVERSE FIELD. ttSPFN from the SUB may be optionally shifted. See SHIFT FIELD. E - 18 S-PAD OPERATIONS FIELD 6 7 8 9 ~ .. ... . ' MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE mvE S-PAD SOURCE REGISTER TO 4 S-PAD DESTINATION REGISTER Assembler Format: MOV < sh > < # > Effect: (SPSPS)t+ SPFN <&> tt sps, spd ; SPFN+ (SP SPD ) unless S-PAD NO-LOAD is specified. Description: SPFN is set to the contents of the S-PAD SOURCE REGISTER (SP[SPS]); SPFN is stored into the S-PAD DESTINATION REGISTER unless an S-PAD NO-LOAD (#) is specified. Appropriate bits are set in the AP INTERNAL STATUS REGISTER and may be tested during the next instruction cycle. CARRY BIT (Sp[sPS])]~ EQUATION: If [(SP[SPD]) 2 16 then, C=l else 0 AND (APSTATUS) (Sp[SPS])] + [(SP[SPD]) OR ~SP[SPS]) may be optionally BIT-REVERSED. See BIT-REVERSE FIELD. tt SPFN from the MOV may be optionally shifted. See SHIFT FIELD. E - 19 S-PAD OPERATIONS FIELD --,-_6___ 7 _8_~ .l:_ <#> < & > sps,spd Effect: (SPSPS)t AND (SPSPD)~ SPFN tt ; SPFN ~ (SPSPD) unless S-PAO NO-LOAD is specified. Description: The contents of the S-PAO SOURCE REGISTER (SP ) are sPS logically ANDed with the contents of the S-PAD DESTINATION REGISTER ). A bit by bit comparison is made between the contents of the SPD two operands and if both respective bits are "1", a "1" is recorded (SP into the correspondi~g bit of the result (SPFN). All other combina- tions result in ".0" being recorded into the respective bit of SPFN. The result of the operation (SPFN) is stored into SPSPD"unless an S-PAD NO-LOAD (#) is specified. The appropriate bits are set in the AP INTERNAL STATUS REGISTER (APSTATUS) and may be tested during the next instruction cycle. CARRY BIT EQUATION: If [(SP SPO) AND (SP SPS) ] + (SP SPO) ~ 2 TRUTH TABLE SP • SPS .0 .0 t (SP sPS SP 1 1 .0 1 1 then CARRY=l SPFN SPD ~ .0 16 A ~ ~ -. ~ .0 .0 .0 • 1 ) mey be optionally BIT-REVERSED, See BIT-REVERSE FIELD tt SPFN from the ANO may be optionally shifted, ' See SHIFT FIELD E - 20 S-PAD OPERATIONS FIELD 5 678 9 ~ Wj MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE OR S-PAD SOURCE REGISTER to S-PAD DESTlNATION 6 Assembler Format: OR < sh > < # > < Effect: (SP SPS SPFN ~ ) t & > sps, spd OR (SPSPD)~ SPFN; (SP SPD REGIS~ tt ) unless NO-LOAD is specified. Description: The contents of the S-PAD SOURCE REGISTER (Sp[SPS]) are logically ORed with the contents of the S-PAD DESTINATION REGISTER (SP[SPD]). A bit-by-bit comparison is made between the contents of the two operands and if either one of the respective bits = "1," then a "1" is recorded in the corresponding bit of the result (SPFN). All other combinations result in a "0" being recorded into the respective SPFN bit position. The result of the operation (SPFN) is stored into SP(SPD) unless S-PAD NO-LOAD (#) is specified. Additionally, S-PAD ALU CARRY BIT is set to "0." The appropriate bits of the AP INTERNAL STATUS REGISTER (APSTATUS) are set and may be tested during the next instruction cycle. TRUTH TABLE SP SPS SP SPD Y Y ~ 1 1 ~ 1 1 ~ ~ SPFN • •• ~ ~ ~ 1 1 1 ~~SP[SPS]) may be optionally BIT-REVERSEd. See BIT-REVERSE FIELD. SPFN from the OR may be optionally shifted. See SHIFT FIELD. E - 21 S-PAD OPERATIONS FIELD ~__-:---r_6_ _ 7 ._8_9 l:.Q ..!'!'" 12 13 SPD ~ ...... ' MANDATORY FIELDS OPTIONAL FlEWS DISABLED FIELDS VALUE EQUIVALENCE S-PAD SOURCE REGISTER to S-PAD 7 DESTINATION REGISTER Assembler Format: EQV < sh > < # > < & > sps, spd Effect: (SP SPS SPFN + ) t XOR (SP SPD )+ . tt SPFN i (SP SPD) unless NO-LOAD is specified. Description: The contents of the S-PAD SOURCE REGISTER (SP[SPS]) and the S-PAD DESTINATION REGISTER (SP[SPD]) are compared on a corresponding bit position basis for equal value. If the corresponding bits both equal "0," or both equal "1," then the respective bit of the result (SPFN) is set to "l.tt All other combinations result in a "0" being set into the corresponding bit of SPFN. The result of the operation (SPFN) is then written into (SP[SPD]) unless S-PAD NO-LOAD (#) is specified. The appropriate bits are set in the AP INTERNAL STATUS REGISTER (APSTATUS) and may be tested during the next instruction cycle. CARRY BIT EQUATION: If (SP[SPD] )+(Sp[SPS]) ~ 2 16 then CARRY=l t(SP[SPS]) may be optionally BIT-REVERSED. See BIT-REVERSE FIELD. tt SPFN from the EQV may be optionally shifted. See SHIFT FIELD. E - 22 S-PAD OPERATION 1 FIELD I~ I B 1 J 2 SOP 5 4 3 I - 7 6 ~ 9 8 10 11 l4! r---'" SPD SPS SH SOP1 SPEC OPER 13 I I I ~ 19.NDATORY FIELDS ... OPTIONAL FIELDS ~ DISABLED FIELDS VALUE 1 EJ Assembler Format: RESTRIcr WRITE m EXPonent only into DPX, DPY or MI WRTEXP Example: Effect: DPX (-2) FA; WRTEXP Restricts DPX,DPY or MI field to write EXPONENT bits only. Description: WRTEXP restricts writing of the pertinent MEMORY INPUT REGISTER into EXPONENT bits 02-11 only. WRTEXP used in conjunction with a DPX, DPY or MI WRITE operation. When used in conjunction with a WRITE DPX or WRITE DPY operation, this operation has the effect of concatenating a portion of the input data with the value most recently written into DPX or DPY irrespective of XW or YW. Thus, if the last WRITE into DPX placed a floating point 1.0 into DPX(-2) and in this instruction we WRITE DPX(O) in conjunction with the WRTEXP Op-Code, the net effect is to concatenate the EXPONENT portion of the current input with the MANTISSA from the 1.0 of the preceding DPX WRITE operation and place the result in DPX(O). WRTHMN,. WRTIMN act in a similar fashion with the exception that they use different portions of the input argument. WRTEX and WRTMAN from the I/O group also work in a similar manner. E - 23 S-PAD OPERATIONS 1 FIELD 5 4 6 SH 7 B 9 10 SPS ~ SPO SOP1 ... SPEC OPER MANDATORY' FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE RESTRICT WRITE TO HIGH MANTISSA only into DPX, 2 DPY or MI Assembler Format: WRTHM.N Example: WRTHMN i DPY < FM Restricts DPX, DPY or MI fields to WRITE HIGH MANTISSA bits only (MANTISSA bits ~~-11) . Effect: Description: WRTHMN restricts the writing to the HIGH MANTISSA only, (MANTISSABITS ~~-ll) of the pertinent MEMORY INPUT REGISTER. WRTHMN is used in conjunction with a DPX, DPY or MI WRITE operation. (See example above). NOTE: DPX or See WRTEXP for a description of the effect of this operation on DPY. RESTRIC'r WRITE to I.J::1i/ MANI'ISSA only into DPX, 3 DFY Assembler Format: or MI FIELDS WRTLMN' Example: Effect: WRTLMN i SETMA; MI < MD Restricts DPX, DPY or MI fields to WRITE LOW MANTISSA only (MANTISSAbits 12-27). Description: WRTLMN restricts wr1tlng to the LOW MANTISSA only (MANTISSA[bits 12-27]) of the pertinent MEMORY INPUT REGISTER. WRTLMN is used in conjunction with a DPX, DPY or MI WRITE operation. (See example above.) NOTE: See WRTEXP for a description of the effect of this operation DPX or DPY. E - 24 on S-PAD OPERATIONS 1 FIELD 5 4 SH 9 . -7 -8- . 6 10 11 12 13 SPD SPS • ~ .. SOPI SPEC OPER MANDATORY FIElDS OPTIONAL FIELDS DISABLED FIELDS VALUE 4 through 7 10 No Operation CLEAR S-PAD DESTINATION REGISTER Assembler Format: -Effect: CLR < sh> <#> spd ~-+SPFN; ~+SPSPD unless NO-LOAD (#) is specified. Description: The S-PAD OUTPUT (SPFN) is forced to all zeros and bit "z" of the AP INTERNAL STATUS REGISTER is set to "1" (bit 5, APSTATUS). SP(SPD) is cleared unless S-PAD NO-LOAD (#) is specified. CARRY BIT EQUATION: 11 If SP(SPD) is negative then CARRY=i. INCREMENT S-PAD DESTINATION REGISTER Assembler Format: INC < sh > < # >spd Effect: (SP SPD ) + 1 -+ SPFN; and, unless NO-LOAD is specified, Description: The contents of the S-PAD DESTINATION REGISTER (SP[SPD]), plus ONE are enabled onto the S-PAD FUNCTION (SPFN). SPFN is stored into the S-PAD DESTINATION REGISTER unless S-PAD NO-LOAD IS specified. The appropriate bits of the APSTATUS Register are set and may be tested during the next instruction cycle. CARRY BIT EQUATION: If (SP[SPD]) was -1, then CARRY=i else O. E - 25 S-PAD OPERATIONS 1 FIELD 45678910 S8 ~ SPD SPS SOpl Wj SPEC OPER MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE 12 DECREMENT S-PAD DESTINATION REGISTER Assembler Format: DEC < sh> < #> spd Effect: (SP SPD) -1+ SPFN; and, unless NO-LOAD is specified, (SPFN) + SP SPD Description: Tne contents of the S-PAD DESTINATION REGISTER minus ONE is set to the S-PAD Function (SPFN). The result (SPFN) is stored into the S-PAD DESTINATION REGISTER unless S-PAD NO-LOAD (#) is specified. The appropriate bits of the AP INTERNAL STATUS REGISTER (APSTATUS) will be set and may be tested during the next instruction cycle. CARRY BIT EQUATION: 13 Unless SP SPD was ~, CARRY=l. COMPI»1ENT S-PAD DESTINATION REGISTER Assembler Format: COM < sh > <: # > spd Effect: (SP SPD )+ SPFN; unless NO-LOAD is specified, SPFN+ (SP SPD) Description: The ONE's COMPLEMENT of the contents of REGISTER are enabled onto the S-PAD Function. S-PAD DESTINATION The result (SPFN) is stored into SP unless S-PAD NO-LOAD (#) is specified in the instruction. SPD The appropriate bits of the AP INTERNAL STATUS REGISTER (APSTATUS) will be set and may be tested during the next instruction cycle. CARRY BIT EQUATION: Unless SP SPD E - was 26 ~, CARRY=l. S-PAD OPERATIONS 1 FIELD 4 5 SH - 6 7 9 8 10 11 12 13 ~ SPD SPS f4ANDA'l'OR'i FIELDS .. SOP 1 SPEC OPER OPTIONAL FIELDS DISABLED FIELDS VALUE 14 WAD S-PAD DESTINATION REGISTER frcm the PANEL BUS Assembler Format: LDSPNL spd Effect: (SP SPD) -7 SPFNi PNLBS Description: -7 SP SPD First, the S-PAD Function is set to the old contents of the S-PAD DESTINATION REGISTER. Then, whatever is enabled qnto the PANEL BUS is loaded into the S-PAD DESTINATION REGISTER. The appropriate bits of the AP INTERNAL STATUS REGISTER (APSTATUS) are set as determined by the previous contents of SP SPD S-PAD CARRY is set to one. during the next instruction. and may be tested If no S-PAD operation is done in the next instruction, then SPFN for that instruction will be the new contents of SP SPD as loaded by this instruction cycle THEN: FIRST: 15 SP PNLBS SPD ~ [ 15 ~ 15 I SPSPD SPFN E - 27 15 S-PAD OPERATIONS 1 FIELD 5 6 ~~------,----.- S8 7 8 9 10 SPS SPD SOPl Q ~ SPEC OPER MANDATORY FIElDS OPTIONAL FIELDS DISABLED FIELDS VALUE wad S-PAD DESTINATION REGIS'IER from 15 DATA PAD BUS - EXPONENT Assembler Format: LDSPE spd Effect: (SP SPD t )+ SPFNi then, (DPBS EXP ) -5l2+SP SPD Description: First, the SPFN is set to the old contents of the S-PAD DESTINATION REGISTER. Then the EXPONENT portion of the DATA PAD BUS (bits 02-11), BIAS inverted, is loaded into the S-PAD DESTINATION REGISTER (bits 06-15). The inverted EXPONENT BIAS BIT is extended into the remaining portion of SP(SPD) (bits 00-05). The appropriate bits of the AP INTERNAL STATUS REGISTER (APSTATUS) are set as determined by the previous contents of SP(SPD) and may be tested during the next instruction. S-PAD CARRY is set to one. If no S-PAD operation is done in the next instruction, then SPFN for that instruction will be the new contents of SP(SPD) as loaded by this instruction. tThis transformation converts a BIASED EXPONENT from a Floating Point word into its TWO's COMPLEMENT equivalent. E - 28 S-PAD OPERATIONS 1 FIELD I~ I I B 1 2 sOP 5 4 3 I SH 6 7 0 9 10 11 12 - SPD SPS 131 1 SOP1 I SPEC OPER H ~ MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE wad S-PAD DESTINATION REGISTER fran 16 DATA PAD BUS - INTEGER Assembler Format: LDSPI spd Effect: (SPSPD)~ SPFN, then (DPBS LOW MANTISSA)~ SP SPD Description: First, SPFN is set to the old contents of the S-PAD DESTINATION REGISTER. Then the contents of the DATA PAD BUS - LOW MANTISSA, a 16-bit integer, are loaded into the S-PAD DESTINATION REGISTER. The appropriate bits of the AP INTERNAL STATUS REGISTER (APSTATUS) are set as determined by the previous contents of SP tested during the next instruction. and may be SPD S-PAD CARRY is set to one. If no S-PAD operation is done in the next instruction, the SPFN for that instruction will be the new contents of SP E - SPD 29 as loaded by this instruction. S-PAD OPERATIONS 1 FIELD I~ I I B 1 2 5 4 3 SOP I ~ SH 6 7 8 9 10 11 -_ ... SPD SPS 12 13 I j SOPl SPEC OPER ~ ... I MANDATORY FIELDS OPTIONAL FIELDS. DISABLED FIELDS VALUE wad S-PlID DESTINATION REGISTER fran mTA PAD BUS - 17 TABLE LCOK UP BITS Assembler Format: LDSPT spd Effect: Bits (SP )+ SPFN; then (DPBS MANTISSA . SPD ~2-fJ8)+ SP SPD Description: First, the SPFN is set to the old contents of S-PAD DESTINATION REGISTER. Then the DATA PAD BUS - TABLE LOOK UP bits (MANTISSA [bits 02-08]) are loaded into bits 09-15 of the S-PAD DESTINATION REGISTER. SP(SPD) bits 00-08 are cleared to zero. LDSPT may be used to calculate memory addresses for use with a look up table. It extracts the se.ven most significant unknown bits from a positive, normalized, non-zero Floating Point number. The appropriate bits of the AP INTERNAL STATUS REGISTER (APSTATUS) are set as determined by the previous contents of SP(SPD) and may be tested during the next instruction. S-PAD CARRY is set to one. If no S-PAD operation is done in the next instruction, then SPFN for that instruction will be the new contents of SP(SPD) as loaded by this instruction. E - 30 SPECIAL TEST FIELD (STEST) H o 0 0 ~ 0 MANDATORY FIELDS OP'1':IONAL FIELDS DISABLED FIELDS VALUE BRANCH on FLOATING ADDER LESS THAN ZEID Assembler Format: BFLT targ Effect: If FA < 0; then (PSA) + (DISP t - BIAS) -+- PSA (where BIAS = 2° ). 8 Description: CONDITIONAL RELATIVE BRANCH. BFLT will cause a program branch if the FADDR Result (FA) available during the previous instruction was less than zero. This instruction tests the FA-NEGATIVE Bit (FN) of the APSTATUS Register. If FN is equal to "1" (indicating that FA was negative during the previous instruction) a program branch will occur to ,the BRANCH TARGET ADDRESS (targ) formed by adding the current contents of PSA with Biased contents of the DISP field of the current instruction word. If FN is equal to "0," this instruction will have no effect. The BRANCH TARGET ADDRESS must lie within -20(8) relative to the current PROGRAM SOURCE ADDRESS. to +17(8) locations DISP=Instruction Word (BITS 27-31) is computed as follows: DISP = targ (PSA) + BlAS. Note that if FN was altered via a LDAPS instruction, at least one cycle must intervene before testing it with this instruction. This restriction applies to all BRANCH instructions that test conditions appearing in APSTATUS. E - 31 SPECIAL TEST FIELD (STEST) H ~ o 000 MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE 1 BRANCH if S-PAD FUNCTION is LESS THAN ZERO Assembler Format: BLT targ Effect: If SPFN < 0; then (PSA) + (DISP t - BIAS) + PSA (Where BIAS = 2° ). 8 Description: CONDITIONAL RELATIVE BRANCH. BLT will cause a program branch if the result of the last S-PAD operation (SPFN) was less than zero. This instruction tests the condition of the SPFN-NEGATIVE Bit (N) of the APSTATUS Register. If "N" is equal to "1" (indicating that SPFN of the last previous instruction was negative), a program branch will occur to the BRANCH TARGET ADDRESS (targ) formed by adding the current contents of PSA with the BIASED contents of the DISP field of the current instruction word. If "N" is equal to "0," this instruction will have no effect. E - 32 SPECIAL TEST FIELD (STEST) ..... o 0 0 ~ 0 MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE 2 BRANaI if S-PAD CARRY is equal to "1" Assembler Format: BNe targ Effect: If S-PAD CARRY (Where BIAS = = 20 8 Ii then (PSA) + (OISp t - BIAS) ~ PSA >. Description: CONDITIONAL RELATIVE BRANCH. BNC will cause a program branch if the S-PAD CARRY Bit (C) of the APSTATUS Register is equal to "1." Bit "C" will be equal to "1" if either: *the S-PAD CARRY Bit was set to "1" as a result of the last S-PAD operation and no S-PAD SHIFT was specified, or *a shift occurred during the last S-PAD operation and the last bit shifted "off the end" of the S-PAD Result was equal to "1." E - 33 SPECIAL TEST FIELD (STEST) 000 ~ ~ 0 MANDATORY FIELDS OPTIONAL FIELDS CIS1\BLED FIELDS VALUE 3 BRANaI on S-PAD CARRY equal Assembler Format: BZC targ Effect: If S-PAD CARRY (Where BIAS = ~; to ZERO then (PSA) + (DISp t - BIAS) + PSA = 208). Description: CONDITIONAL RELATIVE BRANCH. BZC will cause a program branch if the S-PAD CARRY Bit (C) of the APSTATUS Register is equal to zero. E - 34 SPECIAL TEST FIELD (STEST) H o 0 0 ~ 0 MANOlo\TORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE BRANCli if DATA PAD BUS is NEG\TIVE 4 Assembler Format: BDBN targ Effect: If (DB) < 0.0; then (PSA) + (DISP t - BIAS) -+ PSA (Where BIAS = 2° ). 8 Description: CONDITIONAL RELATIVE BRANCH. The sign of the DATA PAD BUS (MANTISSA) (DB[MANT]bit 00) is tested as to its state during the preceding instruction. If DB(MANT)Bit 00 was negative, (e.g.,=l), a program branch will occur to the BRANCH TARGET ADDRESS (targ) formed by adding the current contents of PSA with the BIASED contents of the DISP field of the current instruction word. If DB(MANT)Bit 00 was "0," this instruction will have no effect. NOTE: Since any data enabled onto DB is not latched, the programmer must re-enable the particular data onto DB one instruction cycle before attempting to test it with this instruction. Note that instructions in the PS field (RPSF, LPSL, etc.) used to enable data onto Data Pad Bus for testing instruction. E - 35 cannot be with this SPECIAL TEST FIELD (STEST) ...", ~ , 000 0 MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE BRANCH if DATA PAD ,Btl:) is POSITIVE and UNNORMALIZED 5 Assembler Format: BDBZ targ Effect: If DBMANTBits ~fi1,fi1l (Where BIAS = "fi1", then (PSA) + (DISp t - BIAS)' -+ PSA = 208). Description: CONDITIONAL RELATIVE BRANCH. BDBZ will cause a program branch to occur to the BRANCH TARGET ADDRESS (targ), formed by adding the current contents of PSA with the BIASED contents of the DISP field of the current instruction word, if the sign of the DATA PAD BUS (MANTISSA) (DB [MANT]Bit 00), enabled during the preceding instruction, was positive (e.g.,=O) and DB(MANT)Bit 01 was also equal to "0," (indicating an UNNORMALIZED MANTISSA). If either or both Bits equal(s) "1," this instruction will have no effect. NOTE: Since any data enabled onto DB is not latched, the programmer must re-enabl~ the particular data onto DB one cycle before attempting to test it by this instruction. E - 36 SPECIAL TEST FIELD (STEST) ..... o 0 0 ~ 0 MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE 6~ BRANCH if INVERSE FFl' FIAG Assembler Format: BIFN targ Effect: If IFFT (APSTATUS (Where BIAS = Bit 11 =1 ) = 1; then (PSA) + (DISP t - BIAS) -+ PSA 208). Description: CONDITIONAL RELATIVE BRANCH. branch if the Inverse FFT Flag (IFFT) of the to "I." BIFN will cause a program Register is set APST~TUS IFFT is APSTATUS(bit 11) and can be set by an LDAPS instruction. (See LDREG, I/O.) It is normally set to "1," along with APSTATUS(bit 12) (FFT), only during an INVERSE FAST FOURIER TRANSFORM. 7 c::=J BRANCH if IFFT FIAG = 0 Assembler Format: BIFZ targ Effect: If IFFT (APSTATUs Bi t 12) = ¢; then (PSA) = (DISP t - BIAS) -+ PSA (Where BIAS = 208). Description: CONDITIONAL RELATIVE BRANCH. BIFZ will cause a program branch if the INVERSE FFT Flag (IFFT) of the APSTATUS Register is cleared to zero. E - 37 SPECIAL TEST FIELD (STEST) ..... o 0 0 ~ 0 MANDATORY FlEWS OPTIONAL FIELDS DISABLED FIELDS 'ALUE No Operation BRAN:li if GENERAL FIAG #~ =1 BRAN:li if BENERAL FI.AG #1 =1 BlWOi if GENERAL FI.AG #2 = 1 BlWOi if GENERAL FI.AG #3 =1 Assembler Format: BFLn targ Effect: If FLAG n=li then (PSA) + (DISp t - BIAS) + PSA (Where BIAS = 208). Description: A branch will occur to program location "targ" (assembler format) if flag "n" is set to "1." Flag "n" must have been set or cleared two cycles before the current instruction cycle in order to be tested, i.e., at least one cycle must interven~ between a set or clear flag instruction and a branch flag instruc.tion. ';;1 .. Note: The CONDITIONAL RELATIVE BRANCH instructions test the condition of either of four GENERAL FLAGS (0,1,2,3) available for use in the AP. These flags may be "set" or "cleared" by software instructions. (See FLAG, ~/ 0.) . E - 38 HOST/PANEL FIELD (HOSTPNL) ~ .. 0 0 0 1 MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE TRANSFER PANEL BUS to the LITES REGISTER Assembler Format: PNLLIT Effect: (PNLBS) Description: ~ LITES The current data enabled onto the 16-bit PANEL BUS are loaded into the 16-bit LITES REGISTER. 1 EJ TRANSFER DATA PAD BUSEXPONENT to the LITES REGISTER, via PANEL BUS Assembler Format: DBELIT Effect: (DBEXP) PNLBS Description: ~ LITES; right justified. The current data enabled onto the IO-bit DATA PAD BUSEXPONENT are loaded into the 16-bit LITES REGISTER - right justified. is via the PANEL BUS. E - 39 The transfer HOST/PANEL FIELD (HOSTPNL) o 0 0 1 ~ ~ MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS + VALUE TRANSFER DATA PAD BUS - HI<1I MANTISSA to the LITES 2 REGIS'mR, via PANEL BUS Assembler Format: DBHLIT Effect: (DBHMANT) + PNLBS + LITES; right justified Description: The current data enabled onto the DATA PAD BUS HIGH MANTISSA (MANTISSABits ~~-11) are loaded into the 12 right-most bits of the LITES REGISTER. The transfer is via PANEL BUS. TRANSFER DATA PAD BugICM MANTISSA LITES REGISTER, via to the PANEL BUS Assembler Format: DBLLIT Effect: (DBLMANT) + PNLBS + LITES Description: The current data enabled onto the DATA PAD BUS LOW MANTISSA Bits (MANTISSA 12-27) is loaded into the LITES REGISTER,via the PANEL BUS. E - 40 HOST/PANEL FIELD (HOSTPNL) H 000 1 Wj MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE +8 l~~ Assembler Format: No Operation TRANSFER SWITCHES to DA'm PAD BUS, via PANEL BUS SWDB Example: Effect: the DPX (1) < DB; SWDB Bits ~6-l5)---+ DB EXP Bits (SWR ~2-11, Bits ~4-15)---+ DBMANTBits (SWR ¢¢-11, (SWR) ) DBMANTBits 12-27. } via PNLBS Description: The current contents of the l6-bit SWITCH Register (SWR) are enabled onto the DATA PAD BUS (DB) in the following manner: SWR(bits 06-15) are enabled onto the DATA PAD BUS(EXPONENT), SWR(bits 04-15) are enabled onto the DATA PAD BUS(HIGH MANTISSA), and SWR(bits 00-15) are enabled onto the DATA PAD BUS(LOW MANTISSA) • The transfer is via PNLBS. This instruction is used concurrently with a write from DATA PAD BUS operation to transfer the contents of SWR into a designated memory location or Register. Use of this instruction disables any current DB or PNLBS source-enabling operation. E - 41 HOST/PANEL FIELD (HOSTPNL) H 000 1 WlJ MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS + VALUE TRANSFER SWITCHES to the DATA PAD BUSEXPONENT 11 via PANEL BUS Assembler Format: SWDBE Example: Effect: DPY (- 2) < DB; SWDBE (SWRBits ~6-15)---+ DB EXP Bits ~2-11, (SWRBits ~4-15)---+ DBMANTBits ~~-ll, via PNLBS; WRTEXpt is forced (SWR)------------+) DBMANTBits 12-27. Description: The current contents of the 16-bit SWITCH Register (SWR) are enabled onto the DATA PAD BUS (DB) and a WRTEXP is forced. A WRTEXP is forced as part of this instruction, restricting the writing to the EXPONENT portion of the designated memory location. t see, SOPl for a detailed description of WRTEXP E - 42 HOST/PANEL FIELD (HOSTPNL) ~ .. 0 0 0 1 MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE 12 TRANSFER SWITCHES to DATA PAD BUS HIGH MANTISSA Assembler Format: SWDBH Example: Effect: SETMA; MI < DB; SWDBH (SWRBits ~6-l5)---+ DBEXP Bits ~2-11, (SWRBits ~4-l5)---+ DBMANTBits ~~-ll, MANT . B~ ts 12-27. ( SWR ) --------+) DB 1 r + via PNLBS;WRTHMN' is forced J Description: The current contents of the 16-bit SWITCH Register are enabled onto the DATA PAD BUS (DB) in the following manner: (SWR) The transfer is via PNLBS. A WRTHMN is forced as part of this instruction, restricting the wr1t1ng to the HIGH-MANTISSA portion (MANTISSA[bits 00-11]) of the designated memory location, only. t See SOP1 for a detailed description of WRTHMN E - 43 HOST/PANEL FIELD (HOSTPNL) i .... 0 0 0 1 MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE 14 through 17 8 IDP No Operation 13~ Assembler Format: TRANSFER SWI'ICHES to DATA PAD BUP MMTISSA SWDBL Example: gffect: SWDBL; DPY (1) RY ADDRESS (ABSOWTE) Assembler Format: JSRT Example: ADD 1,2; SETTMA JSRT (SRA) + 1 -+ SRA; (PSA) + 1 Effect: Description: + SRS SRA Bits 4 15 ; (TMA .0 - )+ PSA UNCONDITIONAL ABSOLUTE SUB-ROUTINE JUMP. First, the current PROGAAM SOURCE ADDRESS plus "1" is saved by incrementing the SUB-ROUTINE ADDRESS POINTER (SRA) and storing [(PSA) + 1] into the "last-in" position of the SUB-ROUTINE ). SRA The contents of PSA are then replaced by the least-significant 12 bits RETURN STACK (SRS of the current contents of the TABLE MEMORY ADDRESS REGISTER (TMA). program then jumps to the new PROGAAM SOURCE location. BRANCH )• E - 48 The (See also, RETURN, SET PROGRAM SOURCE ADDRESS (SETPSA) H 1 0 0 MANDATORY FIELDS ~ 0 OPTIONAL FIELDS DISABLED FIELDS VALUE JUMP to location indicated by SWITCH REGISTER, 6 via PANEL BUS (ABSOLUTE) Assembler Format: JMPP Effect: (SRWBits ~4-l5) +PNLBS + PSA Description: UNCONDITIONAL ABSOLUTE JUMP. The current contents of the least-significant 12 bits of the SWITCH REGISTER (SWR) are loaded into the PROGRAM SOURCE ADDRESS REGISTER (PSA) via the PANEL BUS (PNLBS). The program then jumps to the new PROGRAM SOURCE location. WARNING: Propagation delays inherent when executing JMPP may disallow proper decoding of certain target instructions. The perferred alternative sequence is as follows: t n tn+l SWDB; LDTMA JMPT E - 49 SET PROG~~ SOURCE ADDRESS (SETPSA) 100 R Wj 0 MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE 7 JUMP to SUB-IDUTINE tx>inted by the SWITCH REGISTER Assembler Format: JSRP (SRA) + 1 + SRAi (PSA) + 1 + SRSSRAi (SWRBits ~4-l5) + PNLBS + PSA Effect: Description: UNCONDITIONAL ABSOLUTE SUB-ROUTINE JUMP. First, the current PROGRAM SOURCE ADDRESS (PSA) plus "1" is "saved" by incrementing the SUBROUTINE ADDRESS POINTER (SRA) by "1" and storing [(PSA) + 1 ] into the "last-in" position of the SUB-ROUTINE RETURN STACK (SRS ). SRA Then the contents of the PROGRAM SOURCE ADDRESS REGISTER are replaced by the current contents of the least significant 12 bits of the SWITCH REGISTER (via the PANEL BUS). SOURCE location. The program then jumps to the new PROGRAM (See also, RETURN, BRANCH WARNING: ). Propagation delays inherent when executing JSRP may disallow proper decoding of certain target instructions. The preferred alterna- tive sequence is as follows: t n tn+l SWDB i LDTMA JSRT E - 50 PSEVEN, PSODD AND PS FIELDS The following instructions available in the PSEVEN and PSODD fields involve PROGRAM SOURCE partial-word transfers via the PANEL BUS. Addressing for a given instruction may be RELATIVE or ABSOLUTE. (See SPEC SUMMARY.) All instructions within these fields require two cycles to execute and instructions from other fields which reference PNLBS for addressing or use PNLBS as a transfer-conduit should not be concurrently specified. Formats for the various PS partial-words is given below: Please note the warnings in the HALT, BDBN, BDBZ and WRT the PS, PSEVEN and PSODD instructions. JSRA descriptions for NOTES 1) When VALUE or TMA is used as an addressing subscript, the least-significant 12 bits are used. Example: PS(QO) (VALUE)=PS(QO) (VALUE) (bits 52-63) PS(QO)(TMA)=PS(QO)(TMA)(bits 04-15) TMA is TMA Register, not the Table Memory Address which may be modified by the FFT bit APSTATUS. 2) PS Quarter 0 is Bits 00 to 16 to 1 2 32 to 48 to 3 15 31 47 64 = PS(QO) = PS(Ql) = PS(Q2) = PS(Q3) E - 51 PROGRAM SOURCE - EVEN FIELD (PSEVEN) H 1 00 Wj 1 MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE ~ EJ Assembler Format: Effect: 1 c::J Assembler Format: Effect: 2 3 RPS~A ~ to LITES (ABSOLUTE) adr Q (PS ¢ VALUE ) -+ PNLBS -+ LITES READ PROGRAM SOORCEQUARI'ER 2 .from LITES (ABSOLUTE) RPS2A adr Q2 (PS VALUE) -+ PNLBS -+ LITES ~ Assembler Format: RPS~ Effect: (PsQ¢ c:=J Assembler Format: Effect: 4 READ PROGRAM SOORCEQUARI'ER c::J adr VALUE + PSA) -+ PNLBS -+ LITES READ PROGRAM SOURCEQUARI'ER 2 to LITES (REIATIVE) RPS2 adr Q2 CPS VALUE + PSA} -+ PNLBS -+ LITES READ PROGRAM SOURCEQUARI'ER ~ to LITES fran the location specified by TABLE MEM)RY ADDRESS Assembler Format: RPS¢T Effect: (PS Q¢ TMA ) -+ PNLBS -+ LITES E - 52 PROGRA.\1 SOURCE - EVEN FIELD (PSEVEN) .§ .... , 100 1 MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE 5 6 and 7 lJO 6 fran the location specified by TABLE MEMJRY ADDRESS Assembler Format: RPS2T Effect: ( Ps Q2 ~ c::J Assembler Format: Effect: 11 READ PK>GRAM SOURCEQUARI'ER 2 to LITES c::J Assembler Format: Effect: TMA ) ~ PNLBS ~ LITES No Operation WRITE PK>GRAM SOURCEQUARrER yJ from the SWITCHES (ABSOWIE) WPS¢A (SWR) adr ~ PNLBS ~ PsQ¢ VALUE WRITE PK>GRAM saJlCEQUARIER 2 fran the SWITCHES (ABSOLUTE) WPS2A (SWR) ·adr ~ PNLBS ~ PsQ2 VALUE E - 53 PROGRAM SOURCE - EVEN FIELD (PSEVEN) ~ ... ... 100 1 MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE 12 13 14 15 G WRITE PROGRAM SWI'ICHES (REIATIVE) Assembler Format: wps¢ adr Effect: (SWR) [;] SClJRCEQ~ ~ fran the + PNLBS + PsQ¢ WRITE PROGRAM SClJRCEQUARmR 2 fran the SWI'IaiES (REIATIVE) Assembler Format: WPS2 adr Effect: (SWR) + PNLBS + PS EJ Q2 VALUE + PSA WRITE PROGRAM SClJRCEQUARI'ER ~ fran the SVr.rrtllES at the location specified by TABLE MEM)RY ADDRESS Assembler Format: WPS¢T Effect: (SWR) + PNLBS + PsQ2 ~ VALUE + PSA TMA WRITE PROGRAM SClJRCEQUARrER 2 fran the SWITCHES at the location specified by TABLE MEM:>RY ADDRESS Assembler Format: WPS2T Effect: (SWR) + PNLBS + PsQ2 TMA E - 54 PROGRAM SOURCE - ODD FIELD (PSODD) ·i' ..... 1 0 1 0 MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE {I 1 2 3 G Assembler Format: RPSlA adr Effect: (opS Q1 c=J VALUE READ PROGPAM SOURCEQUARrER 3 . fran LITES (ABSOwrE) Assembler Format: RPS3A adr Effect: ( Ps Q3 c=J ) -+ PNLBS -+ LITES VALUE ) -+ PNLBS -+ LITES READ PROGPAM SOURCEQUARrER 1 to LITES (RELATIVE) Assembler Format: RPSI adr Effect: (PsQlVALUE + PSA) -+ PNLBS -+ LITES c:J Assembler Format: Effect: READ PROGPAM SOURCEQUARrER 3 to LITES (RELATIVE) RPS3 adr Q3 (PS VALUE + PSA) -+ PNLBS -+ LITES E - 55 PROGRAM SOURCE - ODD FIELD (PSODD) i " ... 1 0 1 0 MANDATORY FIElDS OPTIONAL FIELDS DISABLED FIELDS VALUE 4 5 6 and 7 1~ 11 B READ PROGRAM SOtJRCECUARI'ER 1 to LITES fran the location specified by TABLE MEM)RY AOORESS Assembler Format: RPSIT Effect: (PS ~ Ql TMA) -+ PNLBS -+ LITES READ PROGRAMSOURCEQUARl'ER 3 to LITES fran the . location specified by TABLEMEM)RY ADDRESS Assembler Format: RPS3T. Effect: ( Ps Q3 ~ ~ TMA ) -+ PNLBS -+ LITES No Operation WRITE PROGRAM SOURCECUARI'ER 1 fram the SWI'ICHES (ABSOLtJrE) Assembler Format: WPSIA adr Effect: (SWR) -+ PNLBS -+ PsQIVALUE [;J Assembler Format: WPS3A adr Effect: (SWR) -+ PNLBS -+ PsQ3 VALUE E - 56 PROGRAM SOURCE - ODD FIELD (PSODD) ·i' " ... 1 0 1 0 MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE 12 13 14 15 8 WRITE PROGRAM SOtJOCEQUARrER 1 fran the SWITCHES (RE!IATIVE) Assembler Format: WPSI adr Effect: (SWR) -+ PNLBS -+ PsQl GJ QUARrER WRITE ProGRAM SOURCE 3 fran the SWITCHES (REIATIVE) Assembler Format: WPS3 adr Effect: (SWR) -+ PNLBS -+ PS ~ Q3 VALUE + PSA WRITE PROGRAM SOURCEQUARrER 1 fran the SWITCHES at the location specified by TABLE MEMJRY ADDRESS Assembler Format: WPSIT Effect: (SWR) -+ PNLBS -+.Ps ~ VALUE + PSA Q1 TMA WRITE ProGRAM SOURCEQUARrER 3 fran the SWITCHES at the location specified by TABLE MEM:>RY .ADDRESS Assembler Format: WPS3T Effect: (SWR) -+ PNLBS -+ PSQ3 TMA E - 57 PROGRAM SOURCE FIELD CPS) ~ .. 1 0 1 1 MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE READ PRJGRAM ~ HALF to DATA PAD BUS (ABSOLUTE) Assembler Format: RPSLA adr Effect: (PSLH ) -+ DB VALUE Description: PROGRAM SOURCE(LEFT HALF) (PS LH]=PS bits 00-31]), as addressed by the least-significant 12 bits contained in the VALUE field (Instruction Word bits 48-63]), is enabled onto DATA PAD BUS (DB). The transfer is executed in the following manner: * * * ZEROS PS(Bits PS(Bits ~ DB(EXP)Bits 02-07 00-03)~DB(EXP)Bits 08-11 04-31)~ DB(MANT)Bits 00-27 This instruction requires two cycles to execute. E - 58 PROGRAM SOURCE FIELD (PS) ~ .. 1 0 1 1 MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE READ P:roGRAM ~G-POmr LITERAL to 1 Il2\TA PAD BUS (ABSOLUTE) Assembler Format: RPSFA adz FPL (PS ) ~ DB Effect: VALUE Description: PROGRAM SOURCE(FLOATING-POINT LITERAL) (PS(FPL]=PS bits as addressed by the least-significant 12 bits contained in the VALUE field (Instruction Word bits 48-63]), is enabled onto DATA PAD BUS (DB). The transfer is executed in the following manner: ~6-63]), * * PS(Bits 26-35) PS(Bits 36-63) DB(EXP)Bits 02-11 DB(MANT)Bits 00-27 This instruction requires two cycles to execute. E - 59 PROGRAM SOURCE FIELD (PS) H 1 0 1 ~ 1 MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE 2 3 GJ READ PROGFAM Assembler Format: RPSL adr Effect: (PS LH GJ VALUE ~ HALF to mTA PAD BUS (REIATIVE) + PSA) -+ DB READ PROGFAM SOURCEFIDATING-POINT LITERAL to DATA PAD BUS (REIATIVE) Assembler Format: RPSF adr Effect: (PS FPL VALUE + PSA) -+ DB This instruction requires two cycles to execute. READ PROGFAM SOUru!,EFr HALF to DATA PAD BUS fran the 4 location specified by TABLE MEM)RY ADDRESS (ABSOLU'lE) Assembler Format: RPSLT Effect: (PSLH TMA ) -+ DB This instruction requires two cycles to execute. E - . 6J) PROGRAM SOURCE FIELD (PS) ~ ' 1 0 1 1 .. MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE READ PROGRAM SOURCJ!IDATING-POlNT LITERAL to DATA PAD BUS 5 from the location specified by TABLE MEM)RY ADDRESS (ABSOLUTE) Assembler Format: RPSFT Effect: (PS FPL TMA ) -+ DB This instruction requires two cycles to execute. READ PROGRAM 6 ~ HALF to DATA PAD BUS fran the address contained. on PANEL BUS (ABSOIDrE) Assembler Format: Effect: RPSLP LH (PS PNLBS) -+ DB This instruction requires two cycles to execute. READ PROGRAM SCXJIO!IDATING-POINT LITERAL to DATA -PAD BUS fran the address contained on PANEL BUS (ABSOWTE) Assembler Format: Effect: RPSFP FPL (PS PNLBS ) -+ DB This instruction requires two cycles to execute. E - 61 PROGRAM SOURCE FIELD (PS) ~ .. 1 0 1 1 MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE l~ Assembler Format: LPSLA adr Effeci:: (DB) + PSLH VALUE Description: The right-most 32 bits of the DATA currently enab-led onto DATA PAD BUS (DB) are loaded into the PROGRAM SOURCE(LEFT HALF) (PS LH]=PS bits 00-31]). The transfer is executed 1n the following manner: * * DB(EXP) Bits 08-11---..) PS(Bits 00-03) DB(MANT) Bits 00-27 > PS(Bits 04-31) This instruction requires two cycles to execute. E - 62 PROGRAM SOURCE FIELD (PS) ~ .. 1 0 1 1 MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE !.DAD ProGRAM Assembler Format: LPSRA adr Effect: (DB) + PS RH ~GlT HALF fran DATA PAD BUS (ABSOwrE) VALUE Description: The right-most 32 bits of data currently enabled onto the DATA PAD BUS (DB) are loaded into the PROGRAM SOURCE(RIGHT HALF) (PS ~H]=PS bits ~8-63]) as addressed by the least-significant 12 bits of the VALUE field (Instruction Word bits 48-63]). The transfer is executed in the following manner: * * DB(EXP) Bits 08-11---~)o PS(Bits 32-35) DB(MANT) Bits 00-27 ~ PS(Bits 36-63) This instruction requires two cycles to execute. E - 63 PROGRAM SOURCE FIELD CPS) H 1 0 1 ~ 1 MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE 12 ~ HALF fran DATA PAD BUS (REIATIVE) I.OAD PROGPJ\M Assembler Format: LPSL adr Effect: (DB) + PS LH This VALUE + PSA requires two cycles to execute. ins~ruction LOAD pROGPJ\M 13 Assembler Format: LPSR adr Effect: (DB) RH + PS SOt.JRCE!UGHr HALF fran DATA PAD BUS (REIATIVE) VALUE + PSA This instruction requires two cycles to execute. 14 8 roAD pROGPJ\M addressed, by Assembler Format: LPSLT Effect: (DB) + PSLH ~ HALF fran DATA PAD BUS as TABLE MEM)RY AIDRESS (ABSOWI'E) TMA This instruction requires two cycles to execute. E - 64 PROGRAM SOURCE FIELD (PS) H 101 ~ 1 MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE 15 IDAD PRCX;RAM ~GlT addressed by TABIEMEM)RY ADDRESS (ABSOWTE) Assembler Format: LPSRT Effect: (DB) -+ PS RH HALF fran as DATA PAD BUS TMA This instruction requires two cycles to execute. IDAD PRCX;RAM 16 ~ HALF fran mTA PAD BUS address contained on PANEL Assembler Format: LPSLP Effect: (DB) -+ PSLHPNLBS at ~~e BUS (ABSOLUTE) This instruction requires two cycles to execute. WAD PIDGPAM ~GRl' HALF fran DATA PAD BUS address contained on PANEL BUS (ABSOWI'E) Assembler Format: LPSRP Effect: (DB) -+ PS RH PNLBS This instruction requires two cycles to execute. E - 65 at the SET EXIT FIELD (SETEXIT) q 110 ~ 0 MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE No Operation SEI' EXIT ADDRESS (ABSOLUTE) Assembler Format: SETEXA Effect: (VALUE) -+ SRS SRA Description: The contents of the current SUB-ROUTINE RETURN ADDRESS (SRS [SRA]), the "last-in" address, are replaced by the least-significant 12 bits of the VALUE field (Instruction Word[bits 48-63]). SRA not affected. No Operation SEr EXIT ADDRESS (REIATIVE) Assembler Format: SETEX adr Effect: (VALUE = PSA) -+ SRS SRA Description: The ,cont~nts of the current SUB-ROUTINE RETURN ADDRESS (SRS SRA )' the "last-in" address, are replaced with the address formed by adding the current contents of the PROGRAM SOURCE ADDRESS (PSA) to the least-significant 12 bits contained on the VALUE field. E - 66 SET EXIT FIELD (SETEXIT) q 1 1 0 ~mNDATORY OPTIONAL FIELDS ~ 0 FIELDS DISABLED FIELDS iTALUE Operation 4 No 5 SET EXIT ADDRESS Assembler Format: SETEXT Effect: (TMA) -+ SRS Description: from TABLE MEIDRY ADDRESS (ABSOI1JTE) SRA The contents of the current SUB-ROUTINE RETURN ADDRESS (SRS SRA the "last-in" address, are replaced by the least-significant 12 bits of the )' current contents of the TABLE MEMORY ADDRESS REGISTER (TMA). No Operation SET EXIT ADDRESS fran ProGRAM SOORCE ADDRESS plus ONE (ABSOllJTE) Assembler Format: SETEXP Effect: (PSA + 1) -+ SRS Description: SRA The contents of the current SUB-ROUTINE RETURN ADDRESS (SRS SRA the "last-in" address, are replaced by the current contents of the PROGRAM SOURCE ADDRESS REGISTER (PSA) plus "1" E - 67 )' BRANCH GROUP (BRANCH) 29 30 31 VALUE No 1 Operation S-PAD DESTINATION REGISTER NO-WAD Assembler Format: <#> (Example: (SPFN)~ Effect: Description: ADDL# 4,5) SPSPD is inhibited. This instruction inhibits the normal loading of the current S-PAD OPERATION result (SPFN) back into the S-PAD DESTINATION REGISTER (SP SPD NOTE: ) specified during the. S-PAD Operation. (See S-PAD summary) Brackets indicate optional use with S-PAD operations. E ... 6$ BRANCH GROUP (BRANCH) 29 30 31 OISP VALUE UNCXlIDITIONAL BRANCH (RELATIVE) 2 Assembler Format: BR disp (Examples: Effect: BR LOOP) (PSA) + (DISp t - BIAS)+ PSA (Where BIAS = 20 ), 8 Description: UNCONDITIONAL RELATIVE BRANCH The program will branch- to the target location "disp" (Assembler Format) by adding the current PSA to the BIASED value contained in the DISPlacement field of the instruction word. NOTE: The BRANCH TARGET ADDRESS must be within a range of -20(8) to +17(8) locations relative to the current PROGRAM SOURCE ADDRESS (PSA). DISP = bits 27-31 of the current instruction word and follows: t DISP = disp - PSA + BIAS. E - 69 ~s completed as BRANCH GROUP (BRANCH) 29 30 31 OISP VALUE BRANCH ON INTERRUPI' IIDJUEST FIAG NON-ZEro 3 Assembler Format: BINTRQ Effect: If INTRQ = 1, then (PSA) + (DISP disp (Where BIAS = 20 Description: - BIAS)+PSA a). CONDITIONAL RELATIVE BRANCH if Interrupt Request. If the INTERRUPT REQUEST FLAG (INTRQ) equals "1," then the program will branch to the target loc~tion "disp." This instruction can be used in conjunction with a succeeding INTA instruction (see I/O group) to identify the interrupting I/O device. 4 BRANCH ON I/O DA.TA READY FLAG NCN-ZERO Assembler Format: BION Effect: If IODRDY (DA) = = 20 disp (Where BIAS Description: 1, then (PSA) + (DISP - BIAS)+ PSA a >. CONDITIONAL RELATIVE BRANCH is I/O Device Ready_ If the I/O DATA READY FLAG (IODRDY) of the I/O device specified by the I/O DEVICE ADDRESS REGISTER (DA) is "1," then the program will branch to the target location "disp." E - 70 BRANCH GROUP (BRANCH) 29 30 31 DISP VALUE 5 BRANCH ON I/O DATA READY FIAG ZERO Assembler Format: BIOZ Effect: If (IODRDY Description: disp ) = ~, then (PSA) + (OISP OA (Where BIAS = 208) . - BIAS)+PSA CONDITIONAL RELATIVE BRANCH if I/O Device not ready. If the I/O DATA READY FLAG (IODRDY) of the I/O DEVICE specified by the I/O DEVICE ADDRESS REGISTER (DA) equals "0," then the program will branch to the target location "disp.1I BRAN::H ON FIDATING POINT ERroR 6 Assembler Format: BFPE Effect: If OVF, UNF, or OIVZ disp (Where BIAS Description: = "I", then (PSA) + (DISP - BIAS)+ PSA = 2° 8 ). CONDITIONAL RELATIVE BRANCH if Floating Point Error. The OVERFLOW (OVF), UNDERFLOW (UNF), and DIVIDE BY ZERO (DIVZ), FLAGS (bits 0, 1, 2 of the APSTATUS REGISTER) are tested. If any of the three flags = "1,11 then a branch will occur to the target location IIdisp.1I E - 71 BRANCH GROUP (BRANCH) 29 30 31 DISP VALUE RETURN FIDM SUB-ROUTINE 7 Assembler Format: RETURN Effect: (SRS Des cript ion: SRA ) -+ PSA; (SRA) -1 -+ SRA UNCONDITIONAL RETURN JUMP. The address contained in the "last-in" position of the SUB-ROUTINE RETURN STACK (SRS) is forced into the PROGRAM SOURCE ADDRESS REGISTER (PSA) and the program branches to that program location. The SUB-ROUTINE ADDRESS POINTER REGISTER (SRA) is then decremented by "1," and will point to the next "last-in" SUB-ROUTINE ADDRESS in event of another RETVRN instruction. RETURN effects a "RETURN" from the last SUB-ROUTINE call. NOTE: Two or more RETURNS may not be executed in time sequential instructions. There must be at least one instruction cycle between the last RETURN instruction and the next one, e.g., the following coding example is illegal in that it results in having the visible RETURN instruction execute immediately after the RETURN instruction in "sub" that brings the processor back to this level. illegal code: JSR sub RETURN E - 72 BRANCH GROUP (BRANCH) 29 30 31 OISP VALUE B1WOI on FLOATING ADDER EQUAL ZEro 10 Assembler Format: BFEQ disp Example: Effect: BFEQ .-3 If FA = 0.0, then (PSA) + (DISP - BIAS)~ PSA (Where BIAS ='2° 8 >. Description: CONDITIONAL RELATIVE BRANCH if FA equal to zero. BFEQ will cause a PROGRAM BRANCH if the FLOATING ADDER Result (FA) available during the previous instruction was equal to 0.0. This instruction tests the FZ FLAG' (bit 3 of APSTATUS) as set by the previous instruction. If FZ is equal to "1," (i.e., FA during the last instruction was equal to 0.0), then the program will branch to the target locat ion "disp." E - 73 BRANCH GROUP (BRANCH) 27 28 29 30 31 DISP VALUE BAANaI on FIDATING ADDER NO!' EXJUAL to ZERO 11 Assembler Format: disp BFNE Example: Effect: If FA ~ BFNE HELP+6 0.0, then (PSA) + (DISP (Where BIAS Description: - BIAS)-+ PSA = 2° 8 ). CONDITIONAL RELATIVE BRANCH if FA not equal to zero. BFNE will cause a PROGRAM BRANCH if the FLOATING ADDER Result for the previous instruction was not equal to 0.0. This instruction tests the FZ flag (bit 3 of APSTATUS) as set by the previous instruction. If FZ equals "0" (i.e., FA for the last instruction was not equal to 0.0), the branch will occur to the target location "disp." E - 74 BRANCH GROUP (BRANCH) 29 30 31 DISP VALUE BRANOI on FLOATING ADDER GREATER or EQJAL to ZERO 12 Assembler Format: BFGE Effect: If FA> 0.0, disp then (PSA) + (DISP - BIAS)~ PSA (Where BIAS = 20 ). 8 Description: to zero. CONDITIONAL RELATIVE BRANCH if FA greater than or BFGE will cause a PROGR&~ BRANCH if the FLOATING ADDER Result (FA) the previous instruction was greater than or equal to 0.0. equal for This instruction tests the condition of the FLOATING ADDER NEGATIVE (FN) FLAG (bit 4 of APSTATUS) as set by the previous instruction. If FN equals "0," (indicating that FA was not negative, i.e., greater than or equal to zero, during the last instruction tycle), a branch will occur to the TARGET ADDRESS "disp." E - 75 BRANCH GROUP (BRANCH) 29 30 31 DISP VALUE BRANCH on FIDATING ADDER GREATER THAN ZERO 13 Assembler disp Format: BFGT Effect: If FA> 0.0, then (PSA) + (DISP (Where BIAS Description: = - BIAS)-* PSA 208) CONDITIONAL RELATIVE BRANCH if FA greater than zero. BFGT will cause a PROGRAM BRANCH to occur if the last FLOATING RESULT (FA) for the previous instruction was greater than 0.0. ADDER The instruction tests the FLOATING ADDER ZERO (FZ) and FLOATING ADDER NEGATIVE (FN) flags (bits 3 and 4 of APSTATUS) as set by the previous instruction. If both flags equal "0" (indicating that FA during the last instruction was greater than zero), then the program will branch to the target location "disp." E "... 76 BRANCH GROUP (BRANCH) 29 30 31 DlSP VALUE BRANCH on S-PAD RESULT EQUALS ZERO 14 Assembler disp Format: BEQ Effect: If SPFN = ~, then (PSA) + (DISP - BIAS)+ PSA (Where BIAS = 2° ). 8 Description: CONDITIONAL RELATIVE BRANCH if SPFN equals zero. BEQ will cause a PROGRAM BRANCH if operation (SPFN) was equal to zero. the result of the last S-PAD This instruction tests the S-PAD ZERO FLAG (Z) (bit 5 of APSTATUS) as set by the previous instruction. If Z equals "1" (indicating that SPFN of the last S-PAD operation was equal to zero), then a branch will occur to the target location "disp. It E - 77 BRANCH GROUP (BRANCH) 29 30 31 DISP VALUE BRANCH 15 on S-PAD RESULT NON-ZEro Assembler Format: BNE Effect: If SPFN disp ~ ~, then (PSA) + (DISP + BIAS)~ PSA (Where BIAS = 2°8 ). Description: CONDITIONAL RELATIVE BRANCH if SPFN not equal to zero. BNE will cause a PROGRAM RELATIVE BRANCH if the previous S-PAD operation (SPFN) was not equal to result o. of the last The instruction tests the S-PAD ZERO FLAG (Z) (bit 5 of APSTATUS) as set by the previous instruction. If Z equals "0" (indicating that SPFN of the last S-PAD operation was not equal to zero), then a branch will occur to the target location "disp." E - 78 BRANCH GROUP (BRANCH) 29 30 31 DISP VALUE 16 BRAN:li on S-PAD RESULT GREA'IER Assembler Format: BGE Effect: If SPFN > ~, then (PSA) + (DISP or EQUAL to ZERO disp - BIAS) -+ PSA (Where BIAS = 2° ). 8 Description: to zero. CONDITIONAL RELATIVE BRANCH if SPFN greater than or equal BGE will cause a PROGRAM BRANCH if the result of operation (SPFN) was greater than or equal to zero. the last S-PAD The instruction tests the S-PAD NEGATIVE FLAG (N) (bit 6 of APSTATUS) as set by the previous instruction. If N is equal to "0" (indicating SPFN of the last operation was zero or greater), a branch will occur to the target location "disp." E - 79 BRANCH GROUP (BRANCH) 29 30 31 DISP VALUE 17 BRANCH on S-PAD RESULT GREATER THAN ZEID Assembler Format: BGT Effect: If SPFN > f3, then (PSA) disp (Where BIAS Description: + (DISP - BIAS) -+ PSA = 20 8 ). CONDITIONAL RELATIVE BRANCH if SPFN greater than zero. BGT will cause a PROGRAM BRANCH if the operation (SPFN) was greater than zero. result of the last S-PAD The instruction tests the S-PAD ZERO (Z) and S-PAD NEGATIVE (N) flags (bits 5, 6 or APSTATUS) as set by the previous instruction. If both flags equal "0" (indicating SPFN of last S-PAD operation was greater than zero), then a branch will occur to the target location "disp." E - 80 FLOAT1NG ADDER GROUP (FADD) 16 17 18 19 20 H Wj o MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS See FADDI field. I FLOATING-POINT SUBTRACT REVERSE; A2 minus AI. Assembler Format: FSUBR < AI, A2 > « Effect: (A2) - (AI) FSUBR TM,MD > indicates optional fields) Description: FSUBR reverses the order of operands in a FLOATING-POINT SUBTRACTION. The contents of Al REGISTER (AI) undergo a FLOATING-POINT SUBTRACTION from the contents of A2 REGISTER (A2). The NORMALIZED, CONVERGENTLY-ROUNDED RESULT is available as the FLOATING-ADDER OUTPUT (FA) one cycle after the next FADDR group instruction is initiated. (See FADDR SUMMARY.) FLOATING-POINT SUBTRACT; Al minus A2. 2 Assembler Format: FSUB < AI, A2 > Effect: (AI) - (A2) Description: The contents of A2 REGISTER (A2) undergo a FLOATING-POINT SUBTRACTION from the contents of Al REGISTER (AI). The NORMALIZED, CONVERGENTLY-ROUNDED RESULT becomes available as the FLOATING ADDER OUTPUT (FA) one cycle after the next FADDR group instruction is initiated. (See FADDR SUMMARY.) F.: - 8] LOATING ADDER GROUP (FADD) ~ Wij MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS ,DE FLOATING-POINT ADD; Al plus A2. 3 Asse.mbler Format: FADD < AI, A2 > Effect: (AI) + (A2) Description: The contents of Al REGISTER undergo a FLOATING-POINT ADDITION with the contents of A2 REGISTER. The NORMALIZED, CONVERGENTLY-ROUNDED RESULT becomes available as the FLOATING ADDER OUTPUT (FA) one cycle after the next FADDR group instruction is initiated. (See FADDR SUMMARY.) E - R? FLOATING ADDER GROUP (FADD) H Wjj MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VJ..LUE FLOATING-POINT LOGICAL EQUIVALENCE; Al with A2. 4 Assembler Format: FEQV < AI, A2 > Effect: -(AI) XOR (A2) Description: The MANTISSAS of Al and A2 in the following manner: ~re compared for EQUIVALENCE Following the arithmetic right-shift of the MANTISSA corresponding to the smaller EXPONENT, the MANTISSAS of Al and A2, including the three bits of residue, undergo a "bit by bit" comparison. When corresponding bits of Al and A2 are equal; (i.e., both "O"s or both "1"s») a "1" is written into the corresponding bit of the RESULT. All other combinations result in a "0" being written. The NORMALIZED, CONVERGENTLY-ROUNDED RESULT of this logical operation becomes available as the FLOATING ADDER OUTPUT (FA) one cycle after the np.xt FADDR group instruction is initiated. (See FADDR SUMMARY.) E - 83 JOATING ADDER GROUP (FADD) ~ Wjj MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS JE 5 FLOATING-POINT AND; AI, A2. Assembler Format: FAND < AI, A2 > Effect: (AI) and (A2) Description: The MANTISSAS of Al and A2 are following manner: logically ANDED in the Following the arithmetic right-shift of the MANTISSA corresponding to the smaller EXPONENT, the MANTISSAS of Al and A2 undergo a "bit by bit" comparison. When corresponding bits of Al and A2 both equal "1," then a "1" is written into the corresponding bit position of the RESULT. All other combinations result in a "0" being written. The NORMALIZED, CONVERGENTLY-ROUNDED RESULT of this logical operation becomes available as the FLOATING ADDER OUTPUT (FA) one cycle after the next FADDR group instruction is initiated. (See FADDR SUMMARY.) E - QA FLOATING ADDER GROUP (FADD) ·i .... MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS lALUE FLOATING-POINT OR; Al or A2. 6 Assembler Format: FOR < AI, A2 > Effect: (AI) Description: manner: OR (A2) The contents of Al and A2 are ORed ~n the following Following the arithmetic right-shift of the MANTISSA corresponding to the smaller EXPONENT, the MANTISSAS of Al and A2, including the three bits of residue, undergo a "bit by bit" comparison. When either or both corresponding bits of Al and A2 equal "1," a "1" is written into the corresponding bit position of the RESULT. When neither corresponding bit is equal to "1," a "'0" is written. The NORMALIZED and CONVERGENTLY-ROUNDED RESULT of this logical operation becomes available as the FLOATING ADDER OUTPUT (FA) one cycle after the next FADDR group instruction is initiated. (See FADDR SUMMARY. ) E - 85 FLOATING ADOER GROUP (FADD) R Wj. . . MAl-lDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS LlTE No-opera.tion~ FIX A2 to an INTEGER (result rounded) Assembler Format: FIX Effect: Example: « > indicates optional field) convert (A2) to a 28-Bit Two's Complement integer. FIX MD Description: The contents of following manner: A2 are FIXED to an integer ~n the 1) An exponent of 28 (apparent value = 1034[octal]) is forced into Al(EXPONENT). AI(MANTISSA) = O. A2 contains the selected argument to be FIXED.t 2) The EXPONENTS of the operands are compared and the MANTISSA corresponding to the smaller EXPONENT is arithmetically rightshifted the number of positions that reflect the difference in the two EXPONENTS. The aligned MANTISSAS are then algebraically added producing a PRELIMINARY-RESULT along with the larger of the two input exponents. 3) The PRELIMINARY-RESULT(EXPONENT) is decremented by "1" and the PRELIMINARY-RESULT(MANTISSA) is correspondingly left-shifted one position while preserving the MANTISSA-SIGN. 4) The PRELIMINARY-RESULT is then CONVERGENTLY-ROUNDED and becomes available as FA one cycle after the ne~t FADDR group instruction is initiated. (See FADDR SUMMARY.) If the TRUE-VALUE of A2(EXPONENT) was in a range of 1 to 27, then the TRUE-VALUE of the RESULT(EXPONENT) will be 27 (APPARENT-VALUE =1033 [octal] or 539). If RESULT(MANTISSA) i?22(-28), then a FLOATING-POINT ZERO is forced as the result. tThe TRUE-VALUE of A2(EXPONENT) must not exceed +27. (APPARENT-VALUE~1033(octal). If the TRUE-VALUE of A2(EXPONENT)~28) the following RESULT will be obtained: "I;" RESULT (MANTISSA-SIGN)=A2 01-26)=A2(MANTISSA Bits 02-27);RESULT (MANTISSA RESULT (EXPONENT)=A2 (EXPONENT)minus (MANTISSA-SIGN) , RESULT(MANTISSA Bit 27)=0. Bits FLOATING ADDER GROUP (FADD) R ~ MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALLt: FIX and TRUNCATE A2 to an INTEGER 2 Assembler Format: FIXT Effect: Convert (A2) to a 28-Bit Two's Complement INTEGER; TRUNCATE (sign magnitude) Example: FIXT DPX(3) Description: The contents of A2(MANTISSA) are FIXED to an integer the RESULT is TRUNCATED in the following manner:· and 1) Current SPFN(Bits 06-15) plus BIAS are forced into AI(EXPONENT). AI(MANTISSA)=O • A2 contains the selected argument to be FIXED.t 2) The EXPONENTS of the operands are compared and the MANTISSA corresponding to the smaller EXPONENT is arithmetically rightshifted the number of positions that reflect the difference in the two EXPONENTS. The aligned MANTISSAS are then algebraically added producing a PRELIMINARY-RESULT. 3) The PRELIMINARY-RESULT(EXPONENT) is decremented by "I" and the PRELIMINARY-RESULT(MANTISSA) is correspondingly 1eftshifted. (This operation preserves the MANTISSA-SIGN following an internal sign-extension operation). 4) The Truncation truth table logic is enabled for this operation (see Floating Point Arithmetic theory) and a TRUNCATED RESULT becomes available as FA one cycle after the next FADDR group instruction is initiated. (See FADDR SUMMARY.) If the TRUE-VALUE of A2(EXPONENT) was in a range of 1 to 27, then the TRUE-VALUE of the RESULT(EXPONENT) will be 27 (APPARENT-VALUE=I033[octa1] or 539). If RESULT(MANTISSA) is<2(-27), then a FLOAiING-POINT ZERO is forced as the result. tTRUE-VALUE of A2(EXPONENT) must not exceed +27. (APPARENT-VALUE 539). If TRUE-VALUE of A2(EXPONENT) 28, the following RESULT will be obtained: RESULT(EXPONENT)=A2(EXPONENT)minus "I"; RESULT (MANTISSA-SIGN)=A2(MANTISSA-SIGN) , RESULT(MANTISSA Bits OI-26)=A2(MANTISSA Bits 02-27);RESULT(MANTISSA Bit 27)=0. E'LOA'l')lNG ADDI:;R GROUP ~F,APD) q ~ MAtJDATORY FIEIJ)S OPTIONAL FIELDS DISABLED FIELDS VALUE FLOATING-POINT SCALE of A2; TRUNCATE 3 Assembler Format: FSCLT Effect: Shift A2MANTISSA right and increment A2 (A2EXPONENT) until A2E = (SPFN + BIAS) -1; result TRUNCATED.Converts an FPN to a 28-Bit TWo's Complement integer within a dynamic range of 2t27. Description: manner: The contents of A2(MANTISSA) are SCALED in the following 1) Current SPFN(Bits 06-15) plus BIAS(=512) are forced into Al(EXPONENT). Al(MANTISSA)-Ot. A2 contains the selected argument to be SCALED.tt 2) The EXPONENTS of the operands are compared and the MANTISSA corresponding to the smaller EXPONENT is arithmetically rightshifted the number of positions that reflect the difference in the two EXPONENTS. The aligned MANTISSAS are then algebraically added producing a PRELIMINARY-RESULT. 3) The PRELIMINARY-RESULT(EXPONENT) is decremented by "1" and the PRELIMINARY-RESULT(MANTISSA) is correspondingly leftshifted. (This operation preserves the MANTISSA-S.IGN following an internal sign-extension operation). 4) The CONVERGENT-ROUNDING logic is inhibited for this operation and a TRUNCATED RESULT becomes available as FA one cycle after the next FADDR group instruction is initiated. (See FADDR SUMMARY) • If the TRUE-VALUE OF A2(EXPONENT) was in a range of 1 to 27. then the TRUE-VALUE of the RESULT(EXPONENT) will be 27 (APPARENT-VALUE=1033[octal] or 539). If RESULT (MANTISSA) is<2( -28). then a FLOATING-POINT ZERO is forced as the result. tCurrent SPFN(Bits 06-15) must equal maximum A2 Exponent plus "I" in order to obtain a correct result from this operation. ttTRUE-VALUE of A2(EXPONENT) must not exceed the value of current SPFN minus "I." If it does, the result obtained will be the same as in the case of FIX or FIXT when A2(EXP}2 28. E ... 88 MAHDA'l'ORY FIELDS OPTIONAL FIELDS DISABLED FIELDS FORMAT-CONVERSION; A2 from SIGNEDMAGNITUDE to TtvO' S COMPLEMENT t 4 Assembler Format: Effect: FSM2C A2 Converts (A2) from SIGNED-MAGNITUDE to TWOS-COMPLEMENT. Description: The contents of A2 REGISTER are converted from SIGNED-MAGNITUDE to TWOS-COMPLEMENT format in the following manner: 1) If A2(MANTISSA) is negative, then A2(MANTISSA bit 00) (MANTISSA-SIGN) remains unchanged while A2(MANTISSA Bits 01-27) undergo a TWOS-COMPLEMENT conversion. 2) If A2(MANTISSA)is positive, A2(MANTISSA) is unchanged. The normalized RESULT becomes available as the FLOATING ADDER OUTPUT (FA) one cycle after the next FADDR group operation. This operation can result in Floating Point underflow if the exponent is large and negative and the mantissa unnormalized. (See FADDR SUMMARY). tSee FLOATING-POINT THEORY, Types of notation. This operation can result in FLOATING-POINT underflow if the exponent is large and negative and the mantissa unnormalized. E - 89 FI.DATING ADDER 1 FIEID (FADD) MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS rAL{JE [F2CSJ FORMAT CONVERSION; A2 from nvosCOMPLEMENT to SIGNED-MAGNITUDE. t Assembler Forma t: F2CSM Effect: Convert (A2) from TWOS-COMPLEMENT to SIGNED-MAGNITUDE. A2 Description: The contents of A2 REGISTER SIGN-MAGNITUDE format in the following manner: are converted to 1) If A2(MANTISSA)is positive, A2(MANTISSA)is unchanged. 2) If A2(MANTISSA)is negative, then A2(MANTISSA Bit 00) (MANTISSA-SIGN) remains unchanged while A2(MANTISSA Bits 01-27) undergo a TWOS-COMPLEMENT conversion. The normalized and convergently rounded RESULT becomes available as the FLOATING ADDER OUTPUT (FA) one cyc,le after the next FADDR group instruction is initiated. (See FADDR SUMMARY). Both underflow and overflow are possible as a result of this operation. tSee FLOATING-POINT SUMMARY, Types of Notation E - 90 FIDATING ADDER 1 FIElD (FADD) MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALL'E FLOATING-POINT SCALE of A2 (rounded result) 6 Assembler Format: Shift (A2MANTISSA) right and increment (A2EXPONENT) until (A2EXPONENT)= (SPFN) + BIAS -1 Description: The contents of A2 are SCALED in the following manner: 1) Current SPFN(Bits 06-1S)plus BIAS(=S12)are forced into Al (EXPONENT). Al(MANTISSA)=Ot. A2 contains the selected argument to be SCALED. tt 2) The EXPONENTS of the operands are compared and the MANTISSA corresponding to the smaller EXPONENT is arithmetically rightshifted the number of positions that reflect the difference in the two EXPONENTS. The aligned MANTISSAS are then algebraically added producing a PRELIMINARY-RESULT. 3) The PRELIMINARY-RESULT(EXPONENT)is decremented by "I" and the PRELIMINARY-RESULT(MANTISSA)is correspondingly leftshifted. (This operation preserves the MANTISSA-SIGN following an internal sign-extension operation). 4) The PRELIMINARY-RESULT is then CONVERGENTLY-ROUNDED and becomes available as FA one cycle after the next FADDR group instruction is initiated. (See FADDR SUMMARY.) If RESULT(MANTISSA)is~2(-28), then a FLOATING-POINT ZERO the result. 1S forced as tCurrent SPFN(Bits 06-15)must equal maximum plus "1" in order to obtain a correct result from this operation. +tTRUE-VALUE OF A2(EXPONENT)must not exceed the value of current SPFN minus "I." E - 91 FI.DATING ADDER 1 FIELD (FADD) H ... ~ MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS 'ALlTE FORMAT CONvERSION; A2 to ABSOLUTE VALUE. 7 Assembler Format: FABS Effect: (A2) A2 -+ ABSOLUTE VALUE Description: The contents of A2 are converted to ABSOLUTE VALUE format 1.n the following manner: 1) If A2(MANTISSA)is positive, A2(MANTISSA) is unchanged. A2 becomes the PRELIMINARY RESULT. 2) If A2(MANTISSA)is negative, then A2(MANTISSA Bits 00-27) undergo a TWOS-COMPLEMENT conversion. (See FLOATING-POINT SUMMARY -- Types of Notation). The PRELIMINARY RESULT is then normalized and CONVERGENTLY-ROUNDED and available as FA one cycle after the next FAD DR group becomes instruction is initiated. (See FADDR SUMMARY). Both overflow and underflow are possible as a result of this operation. E - 92' FLOATING-ADDER GROUP (AI) 14 15 FADD 16 17 18 19 20 Al 21 22 A2 FADD1 i ' MANDATORY FIELDS OPTIONAL FIELDS .. DISABLED FIELDS FLOATING ADDER REGISTER INPUT SUMMARY Al VALUE NO CHANGE: The contents of Al during the last FADDR operation are used as the Al REGISTER OPERAND. Assembler Format: FADD NC, Note: If no Al operand is specified, NC is implied. Al is unaltered from previous operation. Effect: The current FLOATING-MULTIPLIER OUTPUT (FM) is the 1 Al REGISTER OPERAND. 2 3 I Assembler Format: FSUB Effect: (FM) FM, -+ Al DPX (idx) DATA PAD X (DPA + XR -4) is the Al REGISTER OPERAND. Assembler Format: FSUBR Effect: [DPX{DPA + XR -4)] -+ Al DPY (idx) I DPX (idx) , DATA PAD Y (DPA + YR -4) is Al REGISTER OPERAND. Assembler Format: FOR DPY (idx) , FLOATING-POINT ZERO (0.0) is the Al REGISTER ZERO I OPERAND. Assembler Format: FEQV Effect: 0.0 -+ Al ZERO, E -94 FLOATING ADDER GROUP 14 15 16 17 18 19 20 FADD Al FADDI ~ ' MANDATORY FIELDS .. OPTIONAL FIELDS DISABLED FIELDS FLOATING ADDER REGISTER INPUT SUMMARY A2 OCTAL VALUE The contents of A2 during the last FADDR operation are used as the A2 REGISTER operand. Assembler Format: :FADD , NC Effect: (A2) is unaltered from previous operation. The current FLOATING ADDER OUTPUT (FA) is the A2 FA 1 REGISTER operand. Assembler Format: FIX Effect: (FA) ( 2 I DPX FA -+ A2 DATA PAD X (DPA + XR -4) is the A2 REGISTER (idx) ! operand. ! 3 Assembler Format: FSCLT Effect: [DPX(DPA + XR -4)] I DPY (idx) \ I r DPX (idx) -+ A2 DATA PAD Y (DPA + YR -4) is the A2 REGISTER operand. Assembler Format: FABS Effect: [DPX(DPA + YR -4}] DPY (idx) E - 95 -+ A2 The current contents of the MAIN DATA MEMORY OUTPUT 4 MD REGISTER (MDREG) are used as the A2 REGISTER operand. (See MEMORY GROUP SUMMARY - MD). 5 6 Assembler Format: F2CSM Effec't: (MDREG) -+ A2 ZERO MD FLOATING POINT ZERO (0.0) is the A2 REGISTER operand. Assembler Format: FADD Effect: 0.0 -+ A2 MDPX (idx) "Split-word" transfer to A2. (mantissa of DPX) (1) (AI>, ZERO The SPAD FUNCTION (SPFN) plus the BIAS-VALUE (512) forms the EXPONENT portion of the A2 OPERAND. (2) The MANTISSA portion of DATA PAD X(DPA + XR -4) forms the MANTISSA portion of the A2 OPERAND. Assembler Format: FSUB (AI), MDPX (idx) Effect: (SPFN) + 512 -+ A2EXPONENT; [DPX (DPA + XR -4)] 7 EDPX (idx) -+ A2MANTISSA " Split-word" transfer to A2. (exponent of DPX) (1) The EXPONENT of DATA PAD X(DPA + XR -4) forms the EXPONENT portion of the A2 OPERAND. (2) The 2 least-significant bits of SPAD FUNCTION (SPFN bits 14,15) are pu bits ~~, 01. zeroed. E - 96 t . t A2MANTISSA In 0 The remainder of A2MANTISSA is EDPX (idx) is used to generate either a +~ or -1 MANTISSA value. Assembler Format: FSUBR , EDPX ( idx) Effect: [ DPX (DPA + XR -4) EXPONENT ] + A2EXPONENT,. ~~, 01,· (SPFN Bi ts 14, 15 ) + A2MANTISSA bits 1-/11 ~s + A2 MANTISSA bits 01-27. E - 97 FLOATING MULTIPLIER GROUP . ...... ~ I MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE .0 No Opl?r3.tion 1 FIDATING POINT MULTIPLY Assembler Format: FMUL t Effect: (Ml) Description: * (H2) A FLOATING POINT r1ULTIPLY (FHUL) is initiated using the operands selected by the MI and M2 fields. The CONVERGENTLY-ROUNDED result becomes available as FM I cycle after it has been "pushed" through the 3 stage pipeline by two subsequent FHUL operations. (See, FMULR SUMMARy) . .:. I MI and M2 operands need not be specified if a "dummy" is desired. E - 98 Ml REGISTER SUMMARY H ~ MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE ~ 1 2 3 D FIDATING MULTIPLIER OUTPUI' is the ~U REGISTER OPERAND Assembler Format: FMUL Effect: (FM) I DPX(idx) I FM , -+ Nl DATA PAD X is the Ml REGISTER OPE:Rk'ID Assembler Format: FMUL DPX(idx) , Effect: (DPX(DPA I DPY(idx) I + idx» -+ Ml DATA PAD Y is the Ml REGISTER OPERAND Assembler Format: FMUL DPY (idx) t Effect: (DPY(DPA c:=J + idx» -+ Ml TABLE MEMORY OUTPUT REGISTER is the Ml REGISTER OPERAND Assembler Format: FMUL TM,< M2> Effect: (TMREG) -+ Ml E - 99 M2 REGISTER SUMMARY H Wt] MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE ~ 1 2 3 ~ F.1.DA.TING ADDER OurPUT is the M2 REGISTER INPUT Assembler Format: FMUL , DPX(idx) Effect: (DPX(DPA + idx») -+.M2 I DFY(idx) I DATA PAD Y is the M2 REGISTER INPUT Assembler Format: FMUL EffectE (DPY(DPA + idx)} -+ M2 c:=J , DPY ( idx) MAIN DATA MEMORY REGISTER is the M2 REGISTER INPUT Assembler Format: FMUL t MD Effect: (MDREG) -+ M2 E - 100 LOAD REGISTER FIELD (LDREG) H ~ MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE No Operation 1 LOAD S-PAD DESTINATION ADDRESS Assembler Format: LDSPD Example: Effect: LDSPDiDB=DPX(-3) (DPBSMANTISSA bits 24-27)+ SPD Description: DPBS(MANTISSA)bits 24-27 replace four-bit S-PAD DESTINATION ADDRESS REGISTER instruction cycle. the contents of the (SPD) as of the next NOTE: A current S-PAD operation is unaffected by this instruction. However, if an S-PAD operation is executed on the next instruction cycle, the assembled S-PAD DESTINATION ADDRESS (SPD) to be used in the S-PAD operation will be replaced with the contents of SPD produced as a result of this instruction. LOAD MEM)RY ADDRESS fran the DATA PAD BUS i 2 INITIATE A MEMJRY CYCLE Assembler Format: LDMA Example: Effect: LDMAiDB=DPX(-l) (DPBSMANTISSA bits 12-27) + MA Description: DPBS(LOW MANTISSA) bits 12-27 are loaded into the MAIN DATA MEMORY ADDRESS REGISTER (MA) effective as of the next instruction cycle. A MAIN DATA (MD) MEMORY cycle is initiated using the new contents of MA. (See MEMORY GROUP SUMMARY.) NOTE: This op-code supersedes INCMA and DEeMA in the same instruction. It makes SETMA redundant since it would now load from DB instead of SPFN due to the use of the LDREG field. E - 101 LOAD REGISTER FIELD (LDREG) hl ~ MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE !DAD TABLE MEM'JRY ADDRESS fran DATA PAD BUS 3 Assembler LDTMA Format: Example: LDTMAiDB=DPY(-4) (DPBSMANTISSA bits 12-27)-+ TMA Effect: Description: The DATA PAD BUS (LOW MANTISSA) (DPBS[MANTISSA]bits 12-27) is loaded into the TABLE MEMORY ADDRESS REGISTER (TMA) effective as of the next instruction cycle. Two cycles later the contents of the TABLE MEMORY location specified by the two new contents of 1}1A will become available as t~e contents of TABLE MF110RY OUTPUT REGISTER (TMREG). NOTE: This op-code supersedes INCTMA instruction. It makes SETTMA redundant. lOAD DA'l2-\. PAD ADDRESS 4 and fran DECTMA in the same DATA PAD BUS Assembler Format: LDDPA Example: Effect: LDDPA;DB=DPX(3) (DPBSMANTISSA bits 2l-27)-+DPA Description: The contents enabled onto the DATA PAD BUS (MANTISSA)bits 12-27 are loaded into the DATA PAD ADDRESS REGISTER (DPA). The change in DPA is effective as of the next instruction cycle. NOTE: LDDPA supersedes INCDPA and DECDPA. E - 102 It makes SETDPA redundant. LOAD REGISTER FIELD (LDREG) H ~ MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE IDAD S-PAD DESTINATION REGISTER fran DATA PAD BUS 5 Assembler Format: LDSP Example: Effect: LDSP; DB=VALUE (DPBSMANTISSA bits l2-27)-+SP SPD Description: The data currently enabled onto BUS(MANTISSA)bits 12-27 are loaded into SP(SPD). the SPD is selected either via current LDSPD. or S-PAD operation DATA a PAD preceding NOTE: LDSP supersedes LDSPNL, LDSPE and LDSPT. It makes LDSPI redundant. However. one of these op-codes could be used to select SPD if the immediately pre~_eding instruction was not an LDSPD. When combined with an S-PAD operation, LDSP results in the inclusive OR of SPFN and DPBS[MANTISSA](12-27) being written into SP(SPD). WAD APSTATUS REGISTER fran DATA PAD BUS 6 Assmebler Format: LDAPS Example: LDAPS;DB=DPY(2) Effect: (DPBSMANTISSA bits 12-27) APSTATUS Description: The data currently enabled onto the DATA PAD BUS(MANTISSA) bits 12-27 are loaded into the APSTATUS REGISTER (APSTATUS). The new contents of APSTATUS may be tested. Two cycles later, i.e., at least one cycle must intervene between the LDAPS and a related test. Refer to the I/O Group Summary for a complete description of the effects of LDAPS. E - 103 LOAD REGISTER FIELD (LDREG) MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS OCTAL VALUE IDAD DEVICE ADDRESS fran mTA PAD BUS. 7 Assembler Format: LDDA Example: Effect: LDDAjDB=VALUE The least significant 8 bits of the data currently en- abled onto the DATA PAD BUS (DPBS) (DATA PAD BUSMANTISSA bits 2~-27) are loaded into the 8 bit DEVICE .ADDRESS REGISTER (DA); effective as of the next instruction cycle. E - 104 READ REGISTER FIELD (RDREG) ... ... ~ MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE 8 REI\D ProGRAM S ~.,.,..-r..,....,,..,---,...:.:., /';.VALUE ~~/~~~~~~~ i~'.. ... ~ MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE 1 DPY(idx) t < DB Assembler Format: S'roRE DATA PAD BUS DPX ( idx) Example: Effect: (DB)~ into DATA PAD Y < DB DPY(+3) < DB; DB=MD DPY (DPA) + idx Description: The data currently enabled onto the DATA PAD BUS (DB) is written into DATA PAD Y (DPY) at the location specified by the current contents of the DATA PAD ADDRESS REGISTER (DPA), plus the contents of the Y WRITE FIELD (YW)tt minus 4 (the BIAS value). Normally, a DPBS enable instruction is used concurrently with this instruction. If so, the two instructions can be expressed 1n shorthand notaton (e.g., the example above can be expressed as follows: DPY [ +3] RY onto the DATA PAD BUS Assembler Format: DB=HD Effect: (MDREG)-+ DPBS Description: The contents of the MAIN DATA MEMORY (MD) location entered into the MEMORY OUTPUT REGISTER (MDREG) during this instruction cycle are enabled onto the DATA PAD BUS for the current instruction cycle. (See MEMORY GROUP SUMMARY for the set-up requirements for a MAIN DATA MEMORY (MD) READ operation.) E - 134 DATA PAD BUS (DPBS) ~ 2 33 34 3S ~~·O~X·' ·Io·~~y: • !.-._ ..•. !. - ! . . 36 37 38 :.1· --1.--.. . . OPBS - 0, 39 40 41 ° t :r:-)i 42 iR -:-: • • L!....._~· --.- 0.00 43 44 4S 46 47 48 49 50 :. :.·. . 1: ~ -. ~.:;.-~ 63 .!-!.-L!..-~...!...._!_~,_~_ -~~"Ti-."T"0"-:-L----:-r-r-:------, :. :·vAiuE .: .... .' .~,".:: : ~. ~; .;.~..~.• 0 : to .• _ .•.• •••• ~ •• _t • _I • •• ~w. 't ..'~' MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS VALUE 6 DB = SPFN ENABIE SPAD FUNCTION onto the DATA PAD BUS Assembler Format: DB = SPFN (SPFN 7-15)+ DPBSEXPONENT bits ~3-11 bits Effect: (SPFN 6) INVERTEDt+ DPBSEXPONENT bit ~2 bit MANTISSA. . -01tS 13-27 (SPFNbits ~1-15)+ DPBS (SPFN . b1t ~ .) MANTISSA (s1gn) + DPBS bits 00-12 Description: The 10 right-most bits of the S-PAD FUNCTION (SPFN bits [6-15]) plus BIAS, are enabled onto the DATA PAD BUS (EXPONENT) (DPBS [EXP] bits 02-11). The 15 right-most bits of SPFN (bits 01-15) are concurrently enabled onto the DPBS (MANTISSA bits) 13-27 and the 1eft-most remaining bit (SPFN [bit 0]) is extended and enabled onto the left-most remaining bits of the DPBS (MANTISSA) (bits 00-12). SPFN is enabled onto DPBS during the current instruction only. t BIAS: For this operation, a BIAS of 512(10) is added by inverting SPFN(bit)06. E - 135 DATA PAD BUS (DPBS) . 39 40 41 42 ~.r. "~' ',.--. .LL·'·'.·l·" ;"-. -'. ',' · :........ . 43 44 ~r 45 46 47 48 no 49 1-; ". r···. 50 "'T-' •• XR • . ' •• YR • • •• ' XW . . . . . ' .'yw •t., __!..LL'-..·· . - , - ' • •• • 'VALUE •• • t .. • 63 . . . . . . , \'.. • -!.-'-...!-!-.-. .."", .;:.. ~" Ijf" MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS lALUE 7 DB = 'IM ENABLE TABLE MEM:>RY onto the" DATA PAD BUS Assembler Format: DB=TM Effect: (TMREG)-+ DPBS Description: The contents of the TABLE MEMORY (TM) location currently entered into the TABLE MEMORY REGISTER (TM REG) is enabled onto the DATA PAD BUS (DPBS) for the current'instruction cycle. (See HEMORY GROUP SUMMARY-TM for the set-up requirements for a' TABLE MEMORY [TM] READ operation). E - 136 MEMORY INPUT GROUP (MI) H ~ MANDATORY FIELDS OPTIONAL FIELDS DISABLED FIELDS t VALUE No Operation WRITE FIDATING ADDER RESULT to MAIN DATA 1 MEM)RY; VIA MEMJRY INPUT REGISTER Assembler Format: MI RY INPUT REGISTER Assembler Format: MI RY Assembler Format: DECMA Example: Effect: (MA) -l~ DECMAiMI RY ADDRESS REGISTER 2 Assembler Format: DECTMA (See, MEMORY GROUP SUMMARY - Effect: (TMA) -1+ TMA TMA) Description: The contents of the TABLE MEMORY ADDRESS REGISTER (TMA) are decremented by one. The contents of TM (TMA) are available execution of this instruction. E - 147 in TMREG two cycles after TABLE MEMORY ADDRESS GROUP (TMA) H ~ rwIDA'l'ORY FIELDS OPTIOrlAL FIELDS DISABLED FIELDS VALUE SET TABLE MEM)RY ADDRESS REGISTER from 3 S-PAD FUNCTION Assembler Format: SETTMA Effect: (SPFN)+TMAi or, i f LDREG field is being used, then (DPBS)+ TMA, instead. Description: The contents of the result of the current S-PAD operation (SPFN) are loaded into the TABLE MEMORY ADDRESS REGISTER (TMA). However, if an LDREG field instruction is used concurrently (see I/O), th~n the data enabled onto the DATA PAD BUS (DPBS), and not SPFN, is loaded into TMA. The contents of TMA are available as TM two cycles after this instruction. E - 148 execution of INDEX &•••••••••••••• E~13 A1 ••••••••••••• E-93 A2 ••••••••••••• E-95 ADD •••••••••••• E-17 AND •••• ~ ••••••• E-20· B· ••••••••••••• E-13 BDBN ••••••••••• E-35 BDBZ ••••••••••• E-36 BEQ •••••••••••• E-77 BFEQ ••••••••••• E-73 BFGE· •••••••••• E-75 BFGT ••••••••••• E-76 BFLO ••••••••••• E-38 BFL1 ••••••••••• E-38 BFL2 ••••••••••• E-38 BFL3 ••••••••••• E-38 BFLT ••••••••••• E-31 BFNE ••••••••••• E-74 BFPE ••••••••••• E-71 BGE •••••••••••• E-79 BGT •••••••••••• E-80 BIFN ••••••••••• E-37 BIFZ ••••••••••• E-37 BINTRQ ••••••••• E-70 BION ••••••••••• E-70 BIOZ ••••••••••• E-71 BLT •••••••••••• E-32 BNC •••••••••••• E-33 BNE· ••••••••••• E-78 BR ••••••••••••• E-69 BZC •••••••••••• E-34 CFLO ••••••••••• E-122 CFL1 ••••••••••• E-122 CFL2 ••••••••••• E-122 CFL3 ••••••••••• E-122 CLR •••••••••••• E-25 COM •••••••••••• E-26 COND ••••••••••• E-68 CONTROL •••••••• E-8 DB ••••••••••••• E-123, E-129. E-139 DBELIT •••• ~ •••• E-39 DBHLIT ••••••••• E-40 DBLLIT ••••••••• E-40 DEC •••••••••••• E-26 DECDPA ••••••••• E-144 DEQlA •••••••••• E-141 DECTMA •••••••• aE-147 DISP ••••••••••• E-31, E-69 DPA •••••••••••• E-143 DPBS.$ ••••••••• E-129 DPX •••••••••••• E-93, E-95, E-99 E-100, E-123, E-132 DPY •••••••••••• E-93, E-95, E-99 E-100, E-126~ E-133 E - 149· EDPX ••••••••••• E-96 EQV·· •••••••••• E-22 F2CSM •••••••••• E-90 FA ••••••••••••• E-95, E-100, E-124 E-127, E-137 FABS ••••••••••• E-92 FADD ••••••••••• E-81 FADDl· ••••••••• E-81 FAND ••••••••••• E-84 FEQV ••••••••••• E-83 FIX·· •••••••••• E-86 FIXT· •••••••••• E-87 FLAG ••••••••••• E-121 FM ••••••••••••• E-93, E-99, E-125 E-128, E-138 TItUL ••••••••••• E-98 FOR •••••••••••• E-85 FSCALE ••••••••• E-91 FSCLT •••••••••• E-88 FSM2C •••••••••• E-89 FSUB ••••••••••• E-81 FSUBR •••••••••• E-81 HALT ............ E-8 HOSTPNL •••••••• E-39 IN ••••••••••••• E-112 INBS ••••••••••• E-130 1NC •••••••••••• E-25 1NCDPA ••••••••• E-143 1NCMA •••••••••• E-140 1NCTMA ••••••••• E-146 INDA ••••••••••• E-113 1NOUT •••••••••• E-109 1NTA ••••••••••• E-IO 1NTEN •••••••••• E-9" 10 ••••••••••••• E-7, E-101 10RST •••••••• ·•• E-9 JMP •••••••••••• E-47 JMPA ••••••••••• E-45 JMPP· •••••••••• E-49 JMPT ••••••••••• E-48 JSR· ••••••••••• E-47 JSRA ••••••••••• E-46 JSRP ••••••••••• E-50 JSRT ••••••••••• E-48 L •••••••••••••• E~14 LDAPS •••••••••• E-103 LDDA ••••••••••• E-104 LDDPA •••••••••• E-102 LDMA ••••••••••• E-101 LDREG •••••••••• E-lOl LDSP ••••••••••• E-I03 LDSPD •••••••••• E-101 LDSPE·· •••••••• E-28 LDSPI •••••••••• E-29 LDSPNL ••••••••• E-27 LDSPT •••••••••• E-30 LDTMA •••••••••• E-I02 LPSL ••••••••••• E-64 LPSLA •••••••••• E-62 LPSLP •••••••••• E-65 LPSLT •••••••••• E-64 LPSR ••••••••••• E-64 LPSRA •••••••••• E-63 LPSRP ••••• ~ •••• E-65 LPSRT •••••••••• E-65 Ml· •••••••••••• E-99 M2 ••••• ~ ••••••• E-IOO MA ••••••••••••• E-140 MD·Q ••••••••••• E-96, £-100, E-134 MDPX ••••••••••• E-96 MI· •••••••••••• E-137 MOV· ••••••••••• E-19 NC· •••••••••••• E-95 NOP •••••••••••• E-5 OR· •••••••••••• E-21 OUT •••••••••••• E-I09 OUTDA •••••••••• E-IIO PNLLIT ••••••••• E-39 PS· •••••••••••• E-58 PSEVEN ••••••••• E-52 PSODD •••••••••• E-55 R··· ••••••••••• E-15 RAPS ••••••••••• E-I08 RDA· ••••••••••• E-I08 RDPA ••••••••••• E-I07 RDREG •••••••••• E-I05 REFR ••••••••••• E-IO RETURN ••••••••• E-72 REXIT •••••••••• E-7 RMA·· •••••••••• E-I06 RPSO ••••••••••• E-652 RPSOA •••••••••• E-52 RPSOT •••••••••• E-52 RPS1 ••••••••••• E-55 RPSIA •••••••••• E-55 RPSIT •••••••••• E-56 RPS2 •••••• ~ •••• E-52 RPS2A •••••••••• E-52 RPS2T •••••••••• E-53 RPS3 ••••••••••• E-55 RPS3A •••••••••• E-55 RPS3T •••••••••• E-56 R?SA ••••••••••• E-I05 RPSF ••••••••••• E-60 RPSFA •••••••••• E-59 RPSFP •••••••••• E-61 RPSFT •••••••••• E-61 RPSL ••••••••••• E-60 RPSLA •••••••••• E-58 RPSLP •••••••••• E-61 RPSLT •••••••••• E-60 RR·· ••••••••••• E-16 RSPD ••••••••••• E-I05 RSPFN •••••••••• E-I07 RTMA· •••••••••• E-I06 SENSE •••••••••• E-115 SETDPA ••••••••• E-145 SETEX•••••••••• E-66 SETEXA ••••••••• E-66 SETEXIT •••••••• E-66 SETEXP ••••••••• E-67 SETEXT ••••••••• E-67 SETMA •••••••••• E-142 SETSPA ••••••••• E-45 SETTMA· •••••••• E-148 SFLO·· ••••••••• E-121 SFLl· •••••••••• E-121 SFL2·· •• ~ •••••• E-121 ·SFL3·· ••••••••• E-121 SH·· ••••••••••• E-14 SNSA· •••••••• _.E-115 SNSADA ••••••••• E-116 SNSB· •••••••••• E-118 SNSBDA ••••••••• E-119 SOP··· ••••••••• E-6 SOPl· •••••••••• E-23 SPD·· •••••••••• E-17 SPEC·· ••••••••• E-6 SPFN· •••••••••• E-135 SPINA •••••••••• E-115 SPINB· ••••••••• E-118 SPINDA ••••••••• E-114 SPININ ••••••••• E-112 SPMDA ••.•••••••• E-6 SPMDAV ••••••••• E-7 SPNADA· •••••••• E-117 SPNBDA ••••••••• E-120 SPNOUT ••••••••• E-I09 SPOTDA ••••••••• E-ll SPS··· ••••••••• E-17 STEST· ••••••••• E-31 SUB···· •••••••• E-18 SWDB·· ••••••••• E-41 SWDBE •••••••••• E-42 SWDBH •••••••••• E-43 SWDBL •••••••••• E-44 TM··· •••••••••• E-94, E-99, E-136 TMA···· •••••••• E-146 VALUE· ••••••••• E-121, E-131 WPSO· •••••••••• E-54 WPSOA···· •••••• E-53 WPSOT·· •••••••• E-54 WPSl· •••••••••• E-57 WPSIA· ••••••••• E-56 WPSIT •••••••••• E-57 WPS2· •••••••••• E-54 WPS2A· ••••••••• E-53 WPS2T •••••••••• E-54 WPS3· •••••••••• E-57 WPS3A •••••••••• E-56 WPS3T· ••••••••• E-57 WRTEX •••••••••• E-ll WRTEXP ••••••••• E-23 WRTHMN ••••••••• E-24 WRTLMN ••••••••• E-24 WRTI1AN ••••••••• E-ll E-132 XW ••••••••••••• E-123 YR·· ••••••••••• E-133 E-126 ZERO ••••••••••• E-94, E-96. E-129 ,···· •••••••••• E-68 XR··· .......... YW··· •....•.... E - 150 Notice to the Reader • Help us improve the quality and usefulness of thi s mam.:a 1. • Your comments and answers to the following READERS COMMENT fonn would be appreciated. To mail: fold the farm in three parts so that Floating Point Systems' mailing address ;s visible; seal. Thank you READERS COMMENT FORM Document Title _____________ Your commen~s and answers- will help us improve ~e quali~y and usefulness of our publica~ions. If your answers require qualification or addi~ional explanation, please comment in the space provided below. How did ( ( ( ( ( ( ( ) ) ) ) ) ) ) YOU use this manual? AS AN INTRODUCTION TO THE SUBJECT AS AN AID FOR ADVANCED TRAINING TO LEARN OF OPERATING PROCEDURES TO INSTRUCT A CLASS AS A STUDENT IN A CLASS AS A REFERENCE MANUAL. OTHER -------------------- Page Did YOU find this ~aterial YES • • • • • • • • USEFUL? COMPLETE? ACCURATE? WELL ORGANIZED? WELL ILLUSTRATED? WELL INDEXED? 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