88973500_1700_Enhanced_Processor_with_Core_Memory_Hardware_Reference_Sep77 88973500 1700 Enhanced Processor With Core Memory Hardware Reference Sep77

User Manual: 88973500_1700_Enhanced_Processor_with_Core_Memory_Hardware_Reference_Sep77

Open the PDF directly: View PDF .
Page Count: 94

Download
Open PDF In Browser	View PDF

88973500

&J 11:\
\::I ~

~OL DATA

CORfO~TlON

CONTROL DATA®
MICRO-PROGRAMMABLE
COMPUTER FAMILY
1700 ENHANCED PROCESSOR
WITH CORE MEMORY

HARDWARE REFERENCE MANUAL.

,---

REVISION RECORD
DESCRIPTION

REVISION
1---.J)1
(10/74)
A
(8/75)
B

1--

(9/77)

Preliminarv Release
Manual released. This manual obsoletes all previous editions.
Manual revised; includes Engineering Change Order 14967 which corrects storage reference
instructions. Page 4-16 is revised.

Publication No.
88973500
REVISION LETTERS I, 0, Q AND X ARE NOT USED

Printed in the United States of America

Address comments concerning this
manual to:
Control Data Corporation
Publications and Graphics Division
4455 Eastgate Mall
LaJol1a, Calif. 92037
or use Comment Sheet in the back of
this manual.

LIST OF EFFECTIVE PAGES

New features, as well as changes, deletions, and additions to information in this manual, are indicated by bars in the margins or by a dot
near the page number if the entire page is affected. A bar by the page number indicates pagination rather than content has changed.

PAGE
Cover
Title Page
Revision
Record
iii/iv
v thru
viii
1-1 thru
1-8
2-1 thru
2-6
3-1 thru
3-7
4-1 thru
4-15
4-16
4-17 thru
4-29
5-1 thru
5-3
6-1
6-2
7-1 thru
7-4
A-I thru
A-3
B-1 thru
B-4
C-l thru
C-8
Index-l thru
Index-6
Comment
Sheet
Envelope
Back Cover

88973500 B

REV

PAGE

REV

PAGE

REV

PAGE

REV

PAGE

REV

--B
B
A
A
A
A
A
B
A
A
A
A
A
A
A
A
A
B

---

iii/iv

PREFACE

The micro-programmable (MP) computer emulates the
1700 family of computers. Readers of this document
should be familiar with the CONTROL DATA® 1700
series computers and their associated hardware. The
MP is upward-compatible and has an enhanced instruction
capability •

Additional information on Control Data software
applicable to the MP system will be found in the
follOWing publications:

Description

88973500 A

Publication No.

1700 Computer System Codes

60163500

1700 MSOB Version 4 Reference Manual

60361500

1700 MSOB 4 MS FORTRAN Version 3A/B

60362000

Micro Processor Reference Manual

88973400

CCP Support Software 1 MICRO Assembler
Reference Manual

88988800

CCP Support Software 1 MACRO Assembler
Reference Manual

88988900

CONTENTS

SYSTEM DESCRIPTION

1-1

Introduction
Functional Characteristics
Physical Characteristics
Major System Component Description
Micro Processor
Transform
Micro Memory
Macro Memory (Core) and Memory
Interface
I/O-TTY Interface
External I/O Interface

1-1
1-1
1-1
1-5
1-5
1-5
1-5

FUNCTIONAL DESCRIPTION

2-1

General Description
Micro Processor
Transforms and the Transform
Module
Arithmetic/Logical Unit (ALU)
and Data Transfer Organization
Macro Memory
Macro Memory Configuration
I/O-TTY Module
Maintenance Interface/
Maintenance Panel

2-1
2-1

Instruction Format
Basic Instruction Set
Storage Reference
Register Reference
Inter-Register
Skip
Shift
Enhanced MP Instructions
Enhanced Storage Reference
Field Reference
Enhanced Inter-Register
Enhanced Skip
Decrement and Repeat
Miscellaneous
Auto Data Transfer

4-17
4-18
4-19
4-19
4-20
4-24

INTERRUPT SYSTEM

5-1

1-5
1-7
1-7

2-1
2-1
2-4
2-5
2-5

Interrupt Trap Locations
Mask Register
Priority
Internal In~errupts
Operation

2-6

OPERATING PROCEDURE

3-1

Startup
Emulator or Macro-Program Deadstart
Shutdown
System Failure
MSOS Autoload
Operator Interface for thc MP
Function Control Register (FCR)
Auto-Display
Panel Interface Control Commands
Panel/Program Mode Commands
I/O Operations

3-1
3-1
3-1
3-1
3-1
3-1
3-1
3-4
3-4
3-7
3-7

MP INSTRUCTION DESCRIPTION

PROGRAM PROTECT

Program Protect Violations
Storage Parity Errors as Related to
Program Protection
Set/Clear Program Protect Bit
Programming Requirements
Peripheral Equipment Protection
7.

I/O DEVICES

Panel/Program Device
Real-Time Clock

4-1
4-1
4-1
4-1
4-1
4-3
4-5
4-7
4-9
.4-9

5-1
5-1
5-1
5-2
5-2
6-1
6-1

6-1
6-1
6-1
6-2

7-1
7-1
7-3

APPENDIXES
A
B

Glossary
Instruction Summary

88973500 A

A-I

Instructi'Jn Execution Times

C-1

B-1

vii

INDEX
FIGURES

1-1
1-2
1-3
1-4
1-5
2-1

Digital Processor Organizations
MP Standard Chassis
Typical MP Circuit Card
Typical MP Chassis Layout
MP Functional Block Diagram
MP Block Diagram

1-4
1-5
1-6
1-7
1-8
2-1

2-2
2-3
2-4
4-1
4-2

Detailed Block Diagram of
1700 Enhanced Processor
Macro Memory Configuration
Major Signal Flow Paths of
I/O-TTY Module
LRG Instruction
SRG Instruction

2-2
2-5
2-5
4-23
4-23

TABLES
1-1
2-1
3-1
3-2
3-3
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8

viii

MP General Characteristics
MP Mask Register/Interrupt Addresses
Function Control Register (FCR)
Display Code Definitions
MP/1700 Register Correspondence
Storage Reference Instruction Addressing
Storage Reference Instructions
Register Reference Instructions
Inter-Register Instructions
Inter-Register Instruction Truth Table
Skip Instructions
Shift Instructions
Enhanced Storage Reference
Instruction Addresses

1-2
2-4
3-2
3-3
3-5
4-2
4-4
4-6
4-8
4-9
4-10
4-10
4-12

4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
5-1
7-1

Enhanced Storage Reference
Instructions
Field Reference Instructhns
Enhanced Skip Instructi0ns
Miscellane'lus Enhanced Instructhns
ADT Table for a Single A/Q Device
ADT Table f'1r Multiple A/Q Devices
ADT Table for the Cl0ck
ADT Table for Single or Multiple
M05 Devices
Interrupt State Definitions
Standard MP Assignment of Equipment
Codes, Macro/Micro Interrupt
Lines

4-14
4-18
4-19
4-21
4-25
4-27
4-28
4-29
5-1

7-2

88973500 A

SYSTEM DESCRIPTION

INTRODUCTION
The 1700 enhanced processor computer is a special
configuration of the CONTROL DATA® MP family of
parallel mode, stored program, digital processors.
It is dedicated to perform as a CDC® 1700-compatible
digital computer. The MP uses micro programming to
perform 1700 language programs.
This manual describes the basic as well as the optional
characteristics of the MP. It covers the hardware,
general operating procedures, and the MP instruction
repertoire.
The basic MP configuration consists of:
•

Micro processor with 1700 transform

•

Micro memory

•

Macro memory

•

I/O interface

•

Power supply

Various standard options, such as a card reader and a
line printer, are available for the MP. The user may
also use the micro memory and I/o to perform
nonstandard 1700 functions to achieve even greater
flexibility with the MP processor.
A listing of the general characteristics of the MP is
contained in table 1-1.

FUNCTIONAL CHARACTERISTICS
The micro-programmable computer is a multilevel
processor, which uses a semiconductor ROM and a
special hardware function (transform) to emulate a
CDC 1700 computer. The macro memory unit contains
1700 language programs (called macro instructions).
The multilevel processor differs from the conventional
processor, as shown in figure 1-1. The MP operation
is controlled by a program (micro program) in the
semiconductor memory (referred to as micro memory).
The micro program reads 1700 macro instructions from
macro memory and decodes them for execution in the

88973500 A

micro processor. The semiconductor memory is
several times faster than the macro memory. The
transform aids in decoding and program execution.
Therefore, the MP uses special micro-programming
techniques to emulate an enhanced CDC 1700 system
for lower cost, smaller size, and equal or better
speed.

PHYSICAL CHARACTERISTICS
The MP is modularly designed with standard TTL
MSI components and commercial construction.
The standard chassis, shown in figure 1-2, is 18.5
inches high by 17.5 inches wide by 12 inches deep.
The chassis includes cooling fans. The standard
chassis back panel has the I/O wiring for the 1700 A/Q
and 1700 A/Q-DMA. However, it may also contain
specialized I/O for the user. Wiring details are
included in the system wire list provided for the unit.
A front cover panel is provided on the chassis for
maximum cooling.
Power I1equirements for the MP vary with the uscr's
application. CDC provides power supplies of ±5, ± 12,
and ±15 volts with input power requirements of 115 vac,
50 or 60 Hz. Physical dimensions for a power supply
chassis are 8.75 inches high by 17.5 inches wide by
16.0 inches deep. Cooling fans for logic and power
supply chassis require 115 vac, 50 or 60 Hz.
A typical MP circuit card, shown in figure 1-3, is
11 by 14 inches and has 204 input/output contacts.
The MP chassis has a pre-wired location for an
optional panel interface card. The mainteIk1.nce panel
is a 16-inch by 4.5-inch printed circuit board,
connected by a flexible cable to the panel interface card.
The panel contains controls and LED indicators for
manually controlling the MP at the micro level. The
panel interface card also provides an interface to ASCII
RS232-compatible consoles (full-duplex interface). The
r.ormal configuration for the 1700 enhanced processor
uses the I/O-TTY module for manual operator interface.

1-1

TABLE 1-1. MP GENERAL CHARACTERISTICS
Basic Configuration
Processor
Type

General-purpose, micro-programmable digital processor

Organization

Word length

16 bit

Micro-instruction word

32-bit format; two micro instructions per micro-memory
address

Micro-memory type

Semiconductor read/write memory (RAM) and/or read
only memory (ROM)

Micro-memory size

512 words in 64-bit increments (on transform); maximum
of 4,096 additional words available.

Micro-memory access time

70 nanoseconds

Arithmetic

Binary with dynamic selection of ones or twos complement
mode
Up to four parallel unrelated operations are possible in
one micro instruction

Macro-instruction execution time

Approximately the same as a 1700 computer with 900 ",sec
_ memory cycle time (for detailed timing, see Appendix C).

Macro Memory
Requirement

Variable, according to application

Type

Core memory: available in 8K stacks, with a maximum of
32K; the main chassis has a 16-bit format.
Parity and protect bits are available in the standard stack.

Core speed

Read: 600 nanoseconds cycle timet
Write: 700 nanoseconds cycle time t

Direct memory access

Four I/O ports are wired for DMA devices; one can be
a CDC 1700 DSA (QSE feature).

Input/Output (l/O)
Interfaces

Teletypewriter
Display terminal (RS232-C compatible)

t The shortest possible time between successive operations.

1-2

88973500 A

TABLE 1-1. MP GENERAL CHARACTERISTICS (Contlnued)
Basic Conflguration (Continued)
Mechanical
Hardware

Modular

Construction

RETMA 19-inch, rack mountable

Dimensions

Logic Chassis:
Height - 18.5 inches (47 cm)
Width - 17.5 inches (44.5 cm)
Depth - 16.0 inches (40.64 cm)
Power Supply Chassis:
Height - 8.75 inches (22.25 cm)
Width - 17.5 inches (44.5 cm)
Depth - 16.0 inches (40.64 cm)

Weight

Logic Chassis: 40 pounds (approximately) (18 kg)
Power Supply: 50 pounds (approximately) (45 kg)

Input power

115 volts, 50/60 Hz

Miscellaneous Features
Real-tlme clock
Auto-data transfer
Enhanced 1700 Instruction repertoire
Standard Optlons
Input/Output (I/O)

Interfaces

Maintenance panel
CDC 1700 A/Q-DMA (TTL level)
RS232-C compatlble console

Operator input device

TeletypeWriter ASR/KSR 33/35
CDC conversational display terminals
(RS232-C compatible)

88973500 A

1-3

J,.
MICRO MEMORY

MULTILEVEL PROCESSOR
ORGANIZATION

CONVENTIONAL PROCESSOR
ORGANIZATION

1+-- --~

INSTRUCTION
DECODE AND
~-----~
CONTROL

~----

MEMORY

ARITHMETIC
LOGIC

MICRO CONTROL
AND TRANSFORM

MACRO MEMORY

j.. ____ ...

ARITHMETIC
LOGIC

t--+t

OPERATOR
PANEL AND
INTERFACE

t
I
1------ ....

1-------...

f
NOTES:

1.
2.

I
l __ _

DOTTED LINES ARE CONTROL SIGNALS.
SOLID LINES ARE INSTRUCTIONS AND DATA FLOW.

CD
CD

~
Co)
en

g
>

Figure 1-1. Digital Processor Organizations

----

I
I
I
I
_J

cards 1 and 2, and a 1700 transform module. The
micro-processor cards are interconnected through
the basic backpanel wiring. Special user options will
require additional wiring.

TRANSFORM

The transform hardware Is packaged as a separate
module and Is specially designed for the MP
application. The MP has a 512-word, 64-blt ROM
micro memory on the transform module.

Figure 1-2. MP Standard Chassis

The MP will operate in computer rooms, general offices,
and industrial environments. It will operate at temperatures of 40" F to 120" F (4.5° C to 48.8° C), withstand a
maximum temperature gradient of O. 20 F per minute or
at a rate that precludes condensation, and a relative
humidity of 10 to 90 percent. Non-operating environment
extends the temperature range from -30" F to 1500 F
(-35° C to 65· C) and a maximum thermal gradient not to
exceed 20· F per hour or at a rate that precludes condensation. Storage temperatures with proper packaging
protection may range from -60" F to 160· F and relative
humidity from 2 to 98 percent with temperature cycles of
not more than 60· F per hour or at a rate that will preclude condensation. The user should note that these
ranges cover only the micro processor; peripheral
equipments may require more stringent environmental
controls.

MAJOR SYSTEM COMPONENT
DESCRIPTIO N
Figure 1-4 shows the chassis layout for the MP
equlpment; figure 1-5 is the functional block diagram.

MICRO PROCESSOR

The MP enhanced processor consists of an arithmetic
card (ALU), a status mode interrupt card (SM!), control

88973500 A

Functioning as the hardware portion of the
macro-instruction decode process, the transform
causes the micro program to form program branches,
sets various parameters, and performs arithmetic
or logical operations. It provides the micro program
with the capablllty of selecting patterns of bits from
the data transmission paths to form the micro-memory
addresses that sequence the micro program.

MICRO MEMORY

The MP contains a 512-word micro memory on the
1700 transform board. It also has two card slots for
addltlonal micro-memory or special algorithms if
required by the user. The slots are interconnected
to the micro processor through the backpanel and are
accessible only by the micro processor.

MACRO MEMORY (CORE) AND MEMORY
INTERFACE

The core macro memory consists of memory stacks
and an Interface card. The memory stacks are
configured In 8K increments of 20 bits: 1 parity,
1 protect, 1 protect parity, 1 unused, and 16 data bits.
The stacks are mounted on standard 11 x 14-inch
circuit boards, with each stack requiring two card
spaces in the chassis.
Data flow is in I6-bit word format, with a maximum
of 32K possible in the basic chassis. A direct memory
access (DMA) channel is included in the memory
interface as well as the parity and program protect
generation and checking. The DMA for the MP can
provide access for four external DMA devices through
a port to the macro memory.

1-5-

Figure 1-3. Typical MP Circuit Card

1-6

88973500 A

+--

E-<

ii!
r.:I

+--

r:x:
0

+--

r:x:

><
r:x:

::sr.:I
::s

r.:I

t.::
00

r:x:
0

<
r:x:
0

::s
::s
~

8....:l

+-r.:I
C)

<
r:x:

::sr:x:

::sr.:I
::s

r...

E-<

r:x:
C)
.....

::s

r:x:

.....

::s

....:l
<

E-<

r:1>

OJ)

-'I

e..o

C1I

Figure 1-5. !\IP Functional Block Diagram

FUNCTIONAL DESCRIPTION

GENERAL DESCRIPTION
The micro-programmable computer wUl emulate a
CDC 1700 computer system. It can perform all 1700
functions, utilizing an expanded instruction set with
interfacing capablllties to 1700 Series peripherals.
Figure 2-1 shows a block diagram of the MP system.
The basic MP configuration includes the micro
processor, macro memory, I/O interface, and the
operator's interface. The flexible design of the system
permits the user to incorporate his own equipment or
to upgrade the MP with addltional micro memory, I/O
capability, or a special hardware algorithm module.

OPERATOR
INTERFACE

MACRO
MEMORY

MP
MICRO PROCESSOR

interconnected primarily by selectors. A selector is
a multiplexer that transfers one of several inputs to an
output. They are either one, eight, 12, 16, or 32 bits
wide.

TRANSFORMS AND THE TRANSFORM MODULE

Transforms enable quick and efficient decoding of an
emulated Instruction. A transform can be designed to
extract bits from a register or registers, shift the bits
to the required position, and add a base address or
constant bits. This result can then be transferred to
the micro-memory address register (transform jump)
or to the K or N register (transform register load).
For example, when a 1700 instruction is read from
macro memory, one micro-instruction transform jump
transfers control to one of 108 micro-memory locations.
Without the transform feature· the above operation would
require many micro Instructions.
The transform hardware is packaged in a separate
module and Is Implemented using three selectors. The
transform module includes 1, 024 micro instructions
(512 words) in ROM. The majority of these instructions
are used to execute the 1700 emulator. The ROM also
contains instructions for the panel Interface simulation
via the I/O-TTY board.

ARITHMETIC/ LOGICAL UNIT (ALUI AND
DATA TRANSFER ORGANIZATION

I/O

Figure 2-1. MP Block Diagram

MICRO PROCESSOR
The MP central processing unit (CPU) is a special
configuration that consists of an ALU module, an SMI
module, two control modules, and the standard MP
transform module. Detailed organization of the MP Is
shown in figure 2-2. This diagram shows MP registers

88973500 A

The ALU provides the arithmetic and logical capabilities
of the MP. This unit combines two Input words of the
system word length. These two inputs are combined
according to the function code specified in the micro
instruction. The result is immediately available at the
output of the ALU for possible shiftitlg via selector S3 and
deUvery to the destination register, memory interface,
panel interface, and 1/0. The unshifted output of the
ALU is delivered to the SM and mask registers. The
ALU output can be ignored on an operation. The results
of the ALU operation regarding sign. zero, and
magnitude (by means of carryout test) are available to
the test bit logic for instruction sequencing.
The data transfer organization of the MP provides for
storing data in one of six worldng registers and two

2-1

t-:>

J:,
I
T

55 (MAl (1")

(16 iNPl'TS)

-t

,- -

tBIT TEST

I
t tft, fftt
T

58 (KIN) (II)

57(l)

(16 lNP"TS)

ES2

DECODE /tl)

(8)

I
INTErACE

L ___

rl
r~

(8)

(32)

SPECIAL
INTEJtFACE
OPTION

MAl;": ('Pl' 'fHISTATJo:

T TF'ST (11

Ji~~~i'o:f.°M;
,1.:
______ -'

MEMORY
ADDRESS

RTJ
12

Ie ~ I ~I~C I
LJ

(16 INPUTS)

t.;

MEMOny nA TA

~J7T

!Ntn

,
,
I

00
00

ALU
TRANSFORM

fl~ij

liD
ADOO

(16)

aDd KO-1o.6

, ,

T TEST
.7

5M2 (16)

I
I.

?til (lG)

(16)

EX;:! SET

'~'-

wILl

K (Ilf

.\I.t" (lhl

IN('f~)FCH

1.8

MiellO MEMORY

]

BAND lNSFORM

01{ CUt

Sl (tGl

1.1

Ifllil

(32)

I
I

\111"

111 Ill!

2GSI

I'IIUI

S2 (161

FILE IFlLE

1.1

I,CGENERATOR
BIT'

f
N3-N'J

J
1.1

1",l(i,

-File I Is furnished ae an option.

(0)

til

g
>

fTEilFACE

INC [)£cn
oRCLR

TRA!IlSFORM+-----

53 (lG)

S:\11 (HO

5300 TO PANEL

.JI

52 RTJ)
FILE 1 AIJOH/S2 (UB)

88 (lG)

L...
I I/O
__
INTEIlFACE
_______

(!'I/3-S7I

_ _ _ JI

"'"'JI.t
I

SM'
CO'\THOL 2

lJATA

I
I

:
_

:-----------1

T[ST (87)

OPTlO"'AI THISTATE nt·s f.'n>t"T
TO SEI..ECTOIt Sl ASP S2
(VIA FI I;.IPI·TS,

S
C
A
T

__
___
____
tL. _
MACHO
MEMORY
INTERFACE

CONDITIONS

1121

(1.8B'

AU (Ui)

M!..t-.,

nrs

-----------,

TEST

INTEJUWPT AIJDRESS ClI

(12,

INTERRl'PT (321

X81

l~l~
TB

lNTERRIPTS (32,

---'

(Hi)

cL ct t

IXT

I
I
I

MlR (32)

---,

(Hi)

OF MIn

MICRO

:~~)---

f.-

MSIGJ
BITS

PANEL

MEMORY
(:J:!)

ENCODE (Iii)

- - -,

- -

,--

DELTA (lG)

~"O O:TA 8rn'8i

Figure 2-2. Detailed Block Diagram of 1700 Enhanced Processor

X .161

(J (161

MIIII'HIIIISI

provided by the F register. File 2 is
reserved for the emulator, except for registers
Rl, R2, R3, and R4, which are available to the
1700 programmer through enhanced instructions.

files, and for selecting data for processing through the
ALU. ALU results are transferred back to one of the
registers or out of the organization to control external
equipment.
The primary data registers are 1, P, A, F, X, and Q.

•

Bit Generator (BG) - The BG circuit generates
one bit at any position in a word as input to the
B side of the ALU. Control to drive the bit
generator is derived from either the mic ro
Instruction (bits 27 to 31) or the lower five bits
of the N register. Control is usually obtained
from the micro instruction. A bit setting in an
8M register determines the input that will drive
the bit generator.

•

Status/Mode Register (SM) - The SM register
allows the micro program to control the mode
of operation and also allows the micro program
to examine the status of certain internal and
external conditions. The MP can access one of
two SM registers, SMI and SM2.

The following are brief descriptions of the primary
registers. Table 3-3 contains a comparison of the
MP registers with 1700 registers.
•

•

1 Register - A word-length register whose only
Input and output is the selector S1. This
register should not be confused with the 1700
1 register (location OOFF 16).

P Register't- A word-length, general-purpose
register that receives data from the ALU and
provides output to S1. Normally it
used to
hold the software instruction counter.

•

A Register't - A word-length, general-purpose
register that receives data from the ALU and
provides output to S1. The A register is
mechanized as a shifting register, and can be
shifted left or right without using the ALU. The
A register may also be combined with the Q
register to form a double-length shifting register
that operates Independently of the ALU.
F Register - A word·length, general-purpose
register that receives data from the ALU and
provides data to 81 or S2 as ALU Input. This
register is also used as the fUe entry register
and contains Information written Into the files
when they are used as the destination of an ALU
operation.
X Register - A word-length, general-purpose

Q Register l' - A word-length, general-purpose
register that receives data from the ALU and
provides output to 82. The Q register is
mechanized as a shifting register. 'It may be
shifted left or right In conjunction with the A
register without using the ALU.

The SM register module contains 16 bits of SM1
and 16 bits of SM2. All 32 bits of an SM module
can be set or reset by the micro program by
transferring Information to the SM register
from the output of the ALU. Master clear will
also clear SMI and SM2.

•

Interrupts and Mask Register - The interrupt
system is implemented as a sampled data
system at the micro-program level, instead of
a true vectored interrupt system as used in
conventional computers.
The mask register enables the micro processor
to disable/enable interrupts. The MP can
access two mask registers, Ml or M2. For
eich mask bit there is a corresponding bit in the
inte rrupt registe r.
Ml is available to the 1700 programmer through
the DMl instruction, while M2 (referred to as "'1)
is available through the basic inter-register
instruction (see section 4).
Interrupts are identifIed by their corresponding
mask bits, which are assigned to control the
interrupt recognition. The bits in the mask
registers are identified as follows:

Other major portions of the standard MP are:
- Mask Register 1 (MI): MI00 through M115

•

File 2 - A 32-word scratchpad file that may be
used as a general-purpose, word-sized register.
It delivers its output to 81 and 82; data Input is

- Mask Rf.Jgister 2 (M2): M200 through M215

·'tAvallable to the 1700 programmer.

88973500 A

2-3

'!be Interrupt priorities correspond to the
interrupt address generated; that Is, Interrupt
address 00 is associated with the highest priority
Interrupt line and Interrupt address 311s
associated with the lowest priority Interrupt line.
For example, an Interrupt associated with M112
would have priority over an Interrupt associated
with M111, and an Interrupt address of 3
would be developed by the Interrupt address
encoder.

Interrupt addresses are generated by the Interrupt
address encoder, according to the assignments
given In table 2-1.

TABLE 2-1. MP MASK REGlSTER/lNTERRUPT
ADDRESSES
Mask
Bit

Interrupt Address
Mask Register 1

MI00
MI0l
MI02
MI03
MI04
MI05
MI06
MI07
MI08
MI09
MHO
M111
M112
M113
M114
M115

15 Lowest Priority (Ml)
14
13
12
11
10
09.08
07
06
05
04
03
02
01
00 Highest Priority (Ml)
Interrupt Address
Mask Register 2

M200
M201
M202
M203
M204
M205
M206
M207
M208
M209
M210
M211
M212
M213
M214
M215

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16

Lowest Priority (M2)

•

K Register - An eight-bit counter that can be
cleared, Incremented, or decremented. It is
used to address file 1 In addition to any program
usage as a counter.

•

N Register - An eight-bit' counter that may be
cleared, Incremented, or decremented. It is
used to address file 2, control shifts, control
the scale operations, and may be used as an
Iteration counter that controls micro-instruction
execution.

•

N/K Register - The Nand K registers may be
combined to provide operand addresses outside
the current operating micro page.

•

FUe 1 - An optional file of 256 general-purpose,
word..,sized registers that are addressed by the
contents of the K register. The output of the
addressed rue is delivered to 81 and 82 and thus
to the A and B side of theALU on demand. This
file 1 input to selectors SI and S2 is a submultiplexed input to the ALU. Thus, depending on the
state of status mode bit (SM111), either file 1 or
transform data can be selected as either an A or
B Input to the A LU.

MACRO MEMORY
Macro memory for the MP consists of 8K core memory
stacks and an interface card. The interface card provides the control and interfacing required for MP/memory
function and peripheral (DMA) equipment/memory
functions. The 8K memory stacks are In 20-bit format:
Highest Priority (M2)

1918171615
Note:

2-4

The Interrupt address generated is the
same as its priority level; i. e., the
highest priority Interrupt generates a
o interrupt address and the lowest
priority interrupt generates a 31
Interrupt address.

16-Bit Data

Memory Word Parity
Program Protect
Program Protect Parity
Unused

88973500 A

The parity and program protect bits are generated and
tested In the Interface card. One Interface card wtll
handle up to four stacks (32K) In the main MP chassis.

81M REGISTER
MPCONTROL
ALUOUTPUT

Minimum memory cycle time Is 600 ns, which is
defined as the shortest possible time between successive read operations in macro memory. Minimum
macro memory cycle time is 700 ns for write operations.

INPUT DATA
TO MAIN
TRISTATE BUS

(83)

PERIPHERAL CONTROLLER BUS IN

TTY/DISPLAY
CONTROL LINES

PERIPHERAL CON- _ _ _-'
TROLLER BUS OUT
= NUMBER OF LINES

MACRO MEMORY CONFIGURATION

The macro memory configuration is shown in figure 2-3.

,Figure 2 -4. Major Signal Flow Paths of
I/O-TTY Module

CPU}2 PORTS
DMA
.
DMA 1
DMA 2
DMA 3
DMA4

MEMORY
BANK

This module includes the following components:
5 SUBPORTS

•

Real-Time Clock - In conjunction with the
micro code it appears as a 1700 peripheral
to the macro-level programmer.

•

I/O Teletypewriter/Display Control - This
controller is an integral part of the module.
It interfaces to Teletype Corporation ASR/KSR
33/35 teletypes and to the Control Data RS232-C
compatible conversational display terminals.

•

Internal Peripheral Controller Bus - Provides
all I/O data lines, interrupts, and control signals
necessary to generate, in conjunction with the
micro code, an internal CDC 1700 A/Q
(Input/output) bus. This TTL-level bus is
intended to interface with controllers located
in the basic MP chassis.

•

Panel Interface Simulation - A logic section that
is required when a panel/program device is
used for operator input in the panel mode.

DMA5

r I

____________~y~______________- J )

INDIRECT
ADDRESS

I5-BIT ADDRESS
0000 16 to 7FFF 16 (32K SYSTEM)

Figure 2-3. Macro Memory Configuration

The core memory configuration (for 8K to 32K) is a onebank, two-port memory. One bank signifies that only
one reference may take place at one time. Two ports
provide two independent data and control paths to the
memory; either port may request memory Independent
of any operation underway on the other port. The ports
are CPU and DMA (direct memory access).

The MP is interfaced to the I/O module as follows:
•

ALU Output - All output data and address
information is provided from the output of the
ALU via S3.

•

SM Register - All commands to peripheral
controllers are generated by micro code
manipulation of the MP status mode register.

•

MP Control - Timing and control information for
controlling internal I/O module data gating is
provided from the MP control signals.

I/O. TTY MODULE

Figure 2-4 illustrates major signal flow paths to and
from the I/O-TTY module.

88973500 A

2-5

•

Interrupts - Interrupts from peripheral
controllers (within the basic chassis) are wired
directly from the peripheral controller module
to the MP.

The user may use his own design for I/O interfacing
to facllltate use of special hardware.

•

Input Data and Peripheral Response Signals All of these are provided to the MP on the main
CPU tristate bus.

MAINTENANCE INTERFACE/MAINTENANCE
PANEL

•

Real-Time Clock - An integral part of the I/O
module, the real-time clock appears as a 1700
peripheral to the macro-level software. Two
functions are available to the mac ro-level
program: Enable Limit Interrupt and Disable
Limit Interrupt. Two status bits are also
available to the macro-level program: Limit
Interrupt and Lost Count.

The maintenance panel interface is an optional circuit
module available for manual interface to the micro processor. The panel interface provides interfaces for a
maintenance panel or for an RS232-C compatible console
that has full-duplex serial ASCn characteristics. A
card slot is prewired for the panel interface card control,
and data lines tie directly into the control cards and to
the ALU.

2-6

88973500 A

OPERATING PROCEDURE

This section discusses the operating procedure for the
micro-programmable computer in general terms. Since
each user will have a different equipment application
and setup, it is recommended that the user evaluate and
develop his own operating procedure. The following
sections present a general outline for startup and
shutdown actions. Included is a description of the
normal operator's interface to the MP.

MSOS AUTOLOAD
1.

Master clear

Depress the autoload button for the mass storage
controller

Press ESCAPE on the panel/program device

Type K31002800:

Type I@

STARTUP

After the initial MSOS messages, press ESCAPE
on the panel/program device

The following startup sequence is a suggested outline:

Set the program protect by typing J28@

Input data/time on the panel/program device and
continue

Power-On Switch. Turn the MP power-on switch
to the ON position.

Peripheral Power On Sequence. Turn on all
peripherals and auxiliary power units.

OPERATOR INTERFACE FOR THE MP
EMULATOR OR MACRO-PROGRAM
DEADSTART
1.

Master clear the machine.

Place the emulator or macro-program deadstart
deck in the reader.

Press ESCAPE on the panel/program device.

Depress the deadstart switch.

SHUTDOWN
De-energize all peripherals.
switch to the OFF position.

Position the power-on

The normal MP configuration will include a CRT
display unit as the panel/program device. The paneU
program device is connected to the MP through the
I/O-TTY card. It will function as a panel interface or
a program (input/output) device.

FUNCTION CONTROL REGISTER (FCR)
The function control register (table 3-1) is the basic
means of communication between the MP and the panel/
program device in the panel interface mode. The
eight hexadecimal digits (32 bits) of the FC R can be
grouped as follows (0 is highest order):
Display:

Digits 0 and 1

Machine Modes: Digits 2 to 5
Machine Status:

SYSTEM FAILURE
After a system failure, follew the startup procedure
and deadstart/autoload for restart.

88973500 A

Digits 6, 7

The display digits determine which individual registers
of two groups of registers (identified in table 3-2) can
be displayed and/or modified. Digits 2 to 5 of the FCR
are used to set such conditions as selective stop/on/
off, step/run mode, etc.

3-1

TABLE 3-1. FUNCTION CONTROL REGISTER (FCR)
Digit

Bit

(LSB) 31
30
29
28

IF
IE

Bit Definition

Overflow
Not Protected Instruction
Protect Fault
Parity Error

Status Only -

27
26
25
24

IB
lA
19
18

23
22
21
20

17
16
15
14

19
18
17
16

13
12

15
14

OF
OE

13
12

OD
.OC

10
09
08

Enable Micro Memory Write
Multilevel Indirect Addressing Mode
Not used
Suppress Console Transmit

OB
OA
09
08

07
06
05

03
02
01
(MSB) 00

03
02
01
00

}
}

Not used
Not used
Enable Auto Display
Enable Console Echo

07
06
05
04

3-2

Interrupt System Acti ve
Auto-Restart Enabled
Micro Running
Macro Running

{

0 0 Breakpoint Off
0 1 Instruction Reference BP
1 0 Storage Operand BP
1 1 All References BP
BP Interrupt (BP Stop if Clear)
Micro BP. Step. Go. Stop (Macro if Clear)
Step
.
Selective Stop·
Selective Skip
Protect Switch
"

DISPLAY 1

DISPLAY 0

88973500 A

TABLE 3-2. DISPLAY CODE DEFINITIONS
Display 1

Code

Display 0

0 0 0 0

FCR

F2 (Addressed by N)

0 0 0 I

(MSBs)tt

0 0 1 0

(LSBs)tt

0 0 I I

0 1 0 0

0 I 0 I

MIR

0 I I 0

BP/P-MA (Display Only)

F
7

0 I I I

P-MA (Display Only)

I 0 0 0

SMI

I 0 0 1

I 0 I 0

SM2

I 0 I 1

1 I 0 0

1 1 0 I

1 I 1 0

I 1 1 1

1 { Addressed by K
Enabled by SM1l1

MEM

RTJ

)
t Used to address macro memory. Automatically incremented after each memory reference.
tt The combined contents of these two registers are used to address micro memory. The K register is
automatically incremented after each memory reference. The N register does not automatically increment.

88973500 A

3-3

The two least significant digits (6, 7) of th.e FCR are
set by the MP and indicate the machine status, such as
overflow on/off, macro storage parity error. protect
fault, etc.

PANEL INTERFACE CONTROL
COMMANDS

NOTES
1.

Bits 14 16 and 1516 of the FCR
(Enable Console Echo and
Enable Auto Display) are mutually exclusive; that is, the
operator may select one or
the.other, but not both
simultaneously.

Digit 3 of the FCR (bIts
16
to OFI6)' Breakpoint, Is
applicable only If the user
has the optional maintenance
panel and panellntertace
card.

Unassigned display codes
(table 3-2) should be
assumed to be undefined.

Selecting BP or P/MA
(table 3-2) will result IJJ ~th
BP and P-MA being dis ..
played. BP Is the leftmost
16 bits and P-MA is the
rightmost 16 bUs. BP can
be modified only If BP Is
selected; P-MA cannot be
modified in either case.

a terminator (:, G or @) with no characters preceding it
will cause a go signal.

The control commands used in the panel interface mode
include: H, I, J, K, L, @, :, G. and? Control
commands H through L identify the type of data or
operation entered or returned. The at symbol (@), the
colon (:), and G all perfonn an entry termination
function. The @ will also cause the operator's Interface
to go from the panel Interface mode to program (A/Q)
mode. The question mark, ?, generates a master clear.
A normal entry consists of one control character H
through L; two, four, or eight hexadecimal digits 0
through F; and a terminating entry (: or 0). in that order.
A normal response consists of the control character
identifying the data that follows and four or eight
hexadecimal digits. If a transmission or operator error
occ~rs on the entry, an asterisk (*) precedes the control
character and the function control register is
unconditionally displayed with the last legal control
character ~ All entries except the ? cause a response,
unless bit 1016 (Suppress Console Transmit) of the FeR
Is set. The following are examples of the control
functions. The colon (:) is used as the terminating entry.

•

Selecting N or K (table 3-2)
will result in both Nand K
being displayed. N is the left
eight bits and K Is the right
eight bits. However, when N
Is selected only the N
register can be modified;
when K is selected only the
K register can be modified.

Master Clear - A master clear can be generated
in several ways:
- A power on master clear
- The MC button on the maintenance panel
- A signal from a peripheral controller
- A question mark from a panel device

(programmers console)

NOTE
Baud rate compatlbtltty between
the panel device and the machine
must exist for? master clear.

AUTO- DISPLAY
When auto-display is enabled, the register selected by
the control code and display code will be output to the
operator's interface and continuously updated (assuming
the operator's interface contains a display and not a
teletypewriter). With auto-dlsplay enal>led, depressing

•

Stop/Go Control - The following entry wUl cause a

go:
I:

3:-4

(Initiate)

889'l3500 A

This is a micro go if bit 12 of the FCR is set. It
is both a micro and macro go if bit 12 of the FCR
is clear.

NOTE
The clear and set capabilities of
the H and I control functions are
not available in the panel simulation mode.

The I control function may also be used to set a
bit in the FCR.
The following entry will cause a stop:
H:

•

(Halt)

This is a micro stop if bit 12 of the FCR is set.
It is a macro stop if bit 12 of the FCR is Clear.

The response to a start or stop entry is a display
of the FCR.
The H control function may also be used to clear
a specific bit in the FCR. The entry
H14:

The function code

would clear bit 1416 in the FCR and the response
would be a display of the updated FCR.

TABLE 3-3.

J Control Function - The J control function is
used to replace the contents of the function control
register in a digit mode. While it may be used to
change the value of any FCR digit, it is generally
used to change digits 0 and 1. The value of Display
o and Display 1 specifies which MP parameter is
displayed on display requests, or entered on enter
requests (refer to table 3-3). J functions always
consist of J followed by two hexadecimal digits and
a terminator (:, G, or @). The first hexadeci mal
digit specifies the FCR digit 0 through 5 and the
second hexadecimal digit specifies the value the
digit is to assume, 0 through F.

J14:

MP/1700 REGISTER CORRESPONDENCE

1700

MP
P

(P) (i.e., next instruction) (display only)

F2(1)

F2(2)

F2(3)

F2(4)

F2(5)

(display only)

F2(6)

(display only)

F2(7)

(see notes 1 and 2)

(display only)

NOTE: To change I:
1. Change location OOFF 16
2. Change F2(7)

88973500 A

3-5

would set FCR digit 1 to 4 (select the A register). and
the response would be a display of the updated FCR.

NOTE
When macro memory is displayed
or entered, the register selected
in Display 1 is the macro memory
address. The Display 1 selection
must be the P or A register. This
register is incremented by 1 after
the display. In the panel Simulation mode, the Display 1 selection
must be the P register. When
micro memory is displayed or
entered, the K register is the eight
least Significant bits of the address,
and the N register provides the
remaining bits. The K register is
incremented by 1 after the display.

The J code is also used to alternately display the
upper and lower 16 bits of a 32-bit register on
the I6-bit maintenance panel display.
In the panel simulation mode, J: will result in the
display of the entire FCR register. There is no
upper/lower mode.

•

K Control Function - The K control function is
used to display or enter data into the parameter
specified by Display 1. The K function uses two
formats. The first format is a request to display
the parameter specified by Display 1:

K:
The second format is an enter data request. The
data is entered into the parameter specified by
Display 1. It consists of K followed by four or
eight hexadecimal digits, followed by a terminator
(:. G, or @). The hexadecimal digits are the data
to be entered. For example:
- To display the P register, type:
Jll:

Set Display 1 to P register (FCR
Digit 1 = 116)'

Display parameter selected in
Display 1.

- To enter 14FE 6 into the breakpoint
.
1
regIster. type:
JI6:

Set Display 1 to BP register
(FCR Digit 1 = 616),

KI4FE: Enter data into parameter
selected in Display 1.

•

3-6

•

Breakpoint (BP) - There are two types of breakpoint: micro and macro. If bit 12 of the FeR is
set, micro breakpoint is selected. If bit 12 is
clear, macro breakpoint is selected. In the panel
simulation mode there is no micro or macro breakpoint capability.
Bits 14 and 15 of the FeR are used to select three
types of macro BP:
Bit 14

Bit 15

Breakpoint not selected

Instruction reference BP

Store operand BP

All references BP

A macro breakpoint occurs if the breakpoint register

is equal to the macro memory address and the select
conditions are met. For example:
J16:

Set display 1 to breakpoint register.

L Control Function - The L function is opera-

K0050:

Set breakpoint register to 005016'

tionally the same as the K function, except that it
is associated with Display O.

J31:

Set macro mode and breakpoint on
instruction reference.

88973500 A

A stop will occur after the instruction at macro
location 5016 is executed.
If bit 13

FCR is set, an interrupt occurs
when the breakpoint conditions are met rather
than a stop.
of~he

For a micro breakpoint, P/MA is compared to the
lower 12 bits of the breakpoint register. In addition, the upper/lower selection (32-bit select) is
compared to bit 13 of the" breakpoint register. If
all bits are equal and the combination of FCR bits
14 and 15 is not zero, then a micro stop occurs.
If FCR bit 14 is set, then a comparison of FCR bit
13 and the upper/lower selector is not required.

•

Auto Display - When auto display is enabled, the
register selected by the control and display codes
will be output to the operator's interface and
continuously updated as long as the interface is a
display terminal and not a teletypewriter.
Depressing a terminator (:, G, or @) with no
characters preceding it will cause a go signal,
which is useful for stepping through a micro or
macro program.

NOTE

PANEL/PROGRAM MODE COMMANDS
Commands for use in the program mode are escape
(ESC) and manual interrupt. The ESC command will
cause the panel/program device to go from program
mode to panel interface mode. It sets the reserve status
line, which will indicate to the software that the panel/
program device is busy if the macro program would
attempt to reference it.
The manual interrupt is generated by a control G
(BELL) command. It is used instead of a console
manual interrupt button.
The command for use in panel mode is the @ symbol.
It will generate a release reserve as it causes the
panel/program device to enter into the program mode
from the panel mode. Selecting the @ during program
mode will be accepted as a normal ASCII character
with no special function.

I/O OPERATIONS
With the exceptions specified in the program mode
commands, the program mode is to be used as standard
operator data interface to the MP for I/O.

Auto-display mode and echo mode
should never be selected simultaneously. In other words, FCR
bits 20 and 21 should be mutually
exclusive.

88973500 A

3-7

MP INSTRUCTION DESCRIPTION

INSTRUCTION FORMAT

which the most significant bit is the sign bit. Storage
reference instructions have the followIng format:

The MP computer instruction word shown in the
following example consists of 16 bits, numbered
right to left as 0 to IS, with the leftmost bit, 15,
being the most significant and the rightmost bit, 0,
being the least significant.

12 11 10 9

Instruction

15 14 13 12 11 10 9

Delta (a)

Instruction Word

Most Significant Bit

Index Register 2 Flag Ql
""0
(I Register)
;::a

Index Register 1 Flag
(Q Register)

Least Significant Bit

Indirect Address Flag
Hexadecimal (base 16) notation is used in this
computer.
The MP computer is composed of a basic and an enhanced instruction set. The basic set is 1700-compatible
and is divided into storage reference, register reference,
inter-register, skip, and shift instructions. The enhanced instruction set is divided into the enhanced
storage reference, field reference, enhanced interregister, enhanced skip, decrement and repeat, and
miscellaneous instructions.

Relati ve Address Flag
Five types of addresses and/or address methods are
created by these instructions:
•

Instruction Address - The address of the
instruction being executed; also called P

•

Indirect Address - A storage address that
contains an address rather than an operand

•

Base Address - The operand address after all
indirect addressing but before modification by
the index registers. The base address is the
effective address when no indexing is specified.

•

Effective Address - The final address of the
operand. At certain times the effective address
equals the operand for read-operand type
instructions (refer to table 4-1).

•

Indexing - The computer has two index
registers. Index register 1 is the Q register;
index register 2 is storage location OOFF 16
(I register). The base address may be mO! 0) - The
base address Is equal to the instruction address
plus one, P + 1, plus the value of delta with sign
extended. The contents of index repster Ita
(when apectfled) are added to the base address
to form the effective address.

index repate.r Ra, wben apeclfled, are added to
the base address to form the effective address.
Thus, when Ra Is not specifted, the contents of
P + 2 Is the value of the operand. ,
Note that tbere is no Immediate operand condltton
(1. e., indexing Is apeclfled and tbe instruction Is
a read-operand type) as there ts for bastc storage
reference addressing.

•

16-BIt Storage (r - 0, 1" I, and A" 0) - The
base address equals the contents of P + 2. The
contents of Index register Ra, wben specified,
are added to the base address to form tbe
effectlve address.

•

16-BIt Relative (r = I, I = 0, and A = 0) - Tbe
base address equals the contents of P + 2 plus
P + 2. The contents of index register Ra, when
specified, are added to the base address to form
the effectlve address.

•

16-Bit Relative Indirect (r = 1, i = I, and
A =0) - The address of the third word of the
instruction, P + 2, plus the contents of the third
word of the instruction is an indirect address.
The content of this address is the base address.
The contents of the index register Ra, when
specified, are added to the base address to form
the effective address.

If no Indexing takes place, the addresses that can

be referenced In the elaht-bit relative mode are
restricted to the program area. Delta Is eight
bits long, thus the computer references a
location between P - 7E16 and P + 80 16 inclusive.

•

Eight-Bit Relattve tndirect (r" 1, 1" 1, and
A ~ 0) - The address of the second word of the
instruction, P + 1, plus the value of delta with
sign extended Is an indirect address. The
content of this 'address is the base address. Tbe
contents of Index register Ra, wben speCified,
are added to the base address to form the
effective address.
Absolute Constant (r • 0, 1" 0, and A· 0) - The
address of the third word of the instruction,
P + 2, Is tbe base address. The contents of tbe

The instruction deSCriptions are pven in table 4-9.

TABLE 4-9. ENHANCED STORAGE REFERENCE INSTRUCT10NS
Instruction
Subroutlne/J:ump Exit
F4 = 5
F5" 0
Rb= 0

Mnemonic
SJE

Description
Replace the contents of P with the effective address. This
instruction can be used as a Jump or subroutine exit. For
'example, If A" 1 and Ra has been set up by a previous
subroutine jump (see below), control wlll be returned following
that subroutine jump.
Note that subroutine jumps save the address of the instructlon,
rather than the next Instruction, so the subroutine jump exit
may be a two-word instruction (A ~ 0) rather than three.
For example, the following program malaes a subroutine
jump at location 1000. Register A wtU contain 1002 upon

88973500 A

TABLE 4-9. ENHANCED STORAGE REFERENCE INSTRUCTIONS (Continued)
Instruction

Mnemonic

Description
entry to the subroutine SUB. Upon completion, SUB will
exit to location 1003.
1000
1001
1002
1003

SUB

2000

2020
2021

SJA+SUB

0446
5000
2000

SJE- 1, A

0430
5001

CAUTION
Since Rb = 0, a selection of absolute (r = 0), no indirect (i = 0),
and no index register (Ra = 0) will
result in an EIN instruction.

Subroutine Jump
F4= 5
F5 = 0
Rb = 1, 2, 3, 4, 5, 6, or 7
r = 1, 2, 3, 4, Q, A, or I

SJr

Load register r with the address of the last word of this
instruction (I.e., P + 1 for A.i 0; P + 2 for A. = 0). The
contents of P are then replaced with the effective address.

Add Register
F4= 8
F5 = 0
Rb = 1, 2, 3, 4, 5, 6, or 7
r = 1, 2, 3, 4, Q, A, or I

ARr

Add (using ones complement arithmetic) the contents of the
storage location specified by the effective address to the
contents of register r. Operation on overflow is the same
as for the ADD instruction. The contents of storage are not
altered.

Subtract Register
F4= 9
F5 = 0
Rb = 1, 2, 3, 4, 5, 6, or 7
r = 1, 2, 3, 4, Q, A, or I

SBr

Subtract (using ones complement arithmetic) the contents of
the storage location specified by the effective address from
the contents of register r. Operation on overflow 1s the
same as for the ADD instruction. The contents of storage
are not altered.

AND Register
F4=A
F5 = 0
. Rb = 1, 2, 3, 4, 5, 6, or 7
r = 1, 2, 3, 4, Q, A, or I

ANr

Form the logical product (AND), blt-by-blt, of the contents
of the storage location specified by the effective address and
the contents of register r. The result replaces the contents
of register r. The contents of storage are not altered .

88973500 A

4-15

TABLE 4-9. ENHANCED STORAGE REFERENCE INSTRUCTIONS (Continued)

Description

Instruction

Mnemonic

AND Memory
F4=A
F5 = 1
Rb = 1, 2, 3, 4, 5, 6, or 7
r = 1, 2, 3, 4, Q, A, or I

AMr

Form the logical product (AND), bit-by-bit, of the contents
of the storage location specified by the effective address
and the contents of register r. The result replaces the
contents of the storage location specified by the effective
address. The original contents of the storage location
(specified by the effective address) replace the contents
of the A register. The contents of register r are not
altered unless r is the A register. Memory is locked until
completion of the instruction. This instruction is useful
for communication between MPs via memory.

Load Register
F4= C
F5 = 0
Rb = 1, 2, 3, 4, 5, 6, or 7
r = 1, 2, 3, 4, Q, A, or I

LRr

Load register r with the contents of the storage location
specified by the effective address. The contents of storage
are not altered.

Store Register
F4= C
F5 = 1
Rb = 1, 2, 3, 4, 5, 6, or 7
r = I, 2, 3, 4, Q, A, or I

SRr

Store the contents of register r in the storage location
specified by the effective address. The contents of register r
are not altered.

Load Character to A
F4= C
F5 = 2

LCA

Load bits AOO through A07 with a character from the
storage location specified by the sum of the effective address
and bits 1 to 15 of register Rb. Register Rb bit 0 set to 0
specifies the left character (hits 8 to 15) of the storage
location; bit 0 set to 1 specifies the right character (hits 0
to 7). Bits A08 through A15 are cleared to zero. The
contents of storage are not altered.

Store Character from A
F4= C
F5 = 3

SCA

Store the contents of bits AOO through A07 into a character
of the storage location specified by the sum of the effective
address and hits 1 to 15 of register Rb. If bit 0 of register Rh
is set to 0, the left character (bits 8 to 15) of the storage
location is specified; if bit 0 is set to 1 the right character
(hits 0 to 7) is specified. The contents of register A and
other storage characters are not altered.

OR Register
F4=D
F5 = 0
Rb = 1, 2, 3, 4, 5, 6, or 7
r = I, 2, 3, 4, Q, A, or I

ORr

Form the logical sum (inclusive OR), bit-by-bit, of the
contents of the storage location specified by the effective
address and the contents of register r. The result replaces
the contents of register r. The contents of storage are
not altered.

OR Memory
F4=D
F5 = 1
Rb = I, 2, 3, 4, 5, 6, or 7
r = I, 2, 3, 4, Q, A, or I

OMr

Form the logical sum (inclusive OR), bit-by-bit, of the
contents of the storage location specified by the effective
address and the contents of register r. The result replaces
the contents of the storage location specified by the effective
address. The original contents of the storage location

4-16

88973500 B

(

TABLE 4-9. ENHANCED STCRAGE REFERENCE INSTRUCTIONS (Continued)
Mnemonic

Instruction

Description
(specified by the effective address) replaces the contents of register A. The
contents of register r are not altered unless r is the A register. Memory is
locked until completion of the· instruction. This instruction is useful for
communication between MPs via memory.

Compare Register Equal
F4 = E
F5 = 0
Rb = 1,2,3,4,5,6, or 7
r = I, 2,3,4,Q,A, or I

CrE

Skip one location if the contents of register r and the contents of the storage
location specified by the effective address are equal, bit-by-bit. If they are
not, execute the next instruction. The contents of register r and storage
are not altered.

Compare Character Equal
F4 = E
F5 = 2

CCE

Skip one location if the contents of bits 0 to 7 of register A and the character
of the storage location specified by the sum of the effective address and bits
1 to 15 of register Rb are equal, bit-by-bit. If they are not, execute the next
instruction. If bit 0 of register Rb is set to 0, the left character (bits 8 to
15) of the storage location is specified; if bit 0 is set to I, the right character
(bits 0 to 7) is specified. The contents of register A and storage are not
altered.
CAUTION
Each compare instruction assumes that a oneword instruction follows it.

FIELD REFERENCE

and Ra), FLDSTR, and FLDLTH-l fields. The F3a
field determines the operation (e. g., load, store). The
addressing mode fields are defined exactly as the
enhanced storage reference instructions. Refer to
table 4-10 for descriptions of these instructions.

These instructions have the following format:

12 11

F=O

Fl = 5

FLDSTR

FLDLTH-l

....
+
Cl.

1I I
i

3 2

F3a

"":

+I
16-bit address, if l1' 0
I
Cl.L _ _ _ _ _ _ _ _ ._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ,.;

FLDSTR defines the starting bit of the field. For
example, FLDSTR = 0 indicates that the field starts
at bit O. FLDLTH-l defines the length of the field
minus one. FLDLTH-l = 0 indicates that the field is
one bit long. If FLDLTH-l = 0, the field reference
instructions become bit reference instructions.

Field reference instructions are identified when the F
field is 0, the Fl field is equal to 5, and the r, i, Ra,
and F3a fields are not all O. (If these fields are all 0,
the instruction is an lIN. )

A field starts at the bit specified by FLDSTR and
includes the contiguous FLDLTH bits to the right of
that bit. No field may cross a word boundary (i. e. ,
FLDSTR-FLDLTH-l must be greater than or equal to
0). If FLDSTR = 0, the field length must be one bit
long (FLDLTH-l = 0).

Field reference instructions contain four parts:
operation field (F3a). addressing mode fields (l1, r, i,

Note that F3a = 0, F3a = I, and FLDSTR-FLDLTH-l< 0
are reserved for future expansion.

88973500 A

4-17

TABLE 4-10. FIELD REFERENCE INSTRUCTIONS
Instruction

Mnemonic

Description

Skip If Field Zero
Faa = 2

SFZ

Skip one location If the contents of the speclfted field of the storage
location Identified In the effective address are 0 (all bits are 0).
If the contents are not 0, execute the next instruction.

Skip if Field Not Zero
F3a = 3

SFN

Skip one location If the contents of the specified field of the storage
location field Identified in the effective address are nonzero (not all
bits are 0). If the contents are zero execute the next instruction.

CAUTION
Each skip field instruction assumes

that a one-word instruction follows
it.

Load Field
F3a = 4

LFA

Load register A, right justified, with the contents of the specified
field of the storage location field Identified in the effective address.
All other bits of register A are cleared to O. The contents of
storage are not altered.

Sto-ie Field
F3a = 5

SFA

Store the contents of the field from register A, right justified, into
the speclfted field of the storage location Identified in the effective
address. All other storage bits are unchanged. Memory Is locked
until completion of the Instruction. The contents of A are not
altered.

Clear Field
F3a = R

CLF

Clear the specified field of the storage location specified by the
effective address to all Os. All other storage bits are unchanged.
Memory is locked until completion of the instruction.

Set Field
F3a = 7

SEF

Set the speclfied field of the storage location Identified in the
effective address to all Is. All other storage bits are unchanged.
Memory Is locked until completion of the instruction.

ENHANCED INTER-REGISTER

(Ra and Rb). The F2a field determines the operation
(e.g., transfer). The Ra and Rb fields specify two
operands.

These instructions have the following format:
15

12 11
F

8
F1

5
Ra

I I
F2a

Enhanced inter-register instructions are identified when
the F field is 0, the Fl field is 7, and the F2a. Ha, and
Rb fields are not all O. (If these fields are all 0, the
instruction is CPB.)
Enhanced inter-register instructions (similar to the basic)
inter-register instructions, such as TRA Q) contain
three parts: operation field (F2a) and two register fields

4-18

Note that F2a = I, F2a = 2, F2a = 3, Ra = 0, and Rb
are reserved for future expansion.
The Instruction description is:
Transfer Register
F2a = 0
Ra = I, 2, 3, 4, 5, 6, or 7
r = I, 2, 3, 4, Q, A, or 1

XFr R

Transfer the contents of register r to register R.
Note that R = I, 2, 3, 4, Q, A, or I implies that
Rb = I, 2, 3, 4, 5, 6, or 7.

88973500 A

ENHANCED SKIP

DECREMENT AND REPEAT

The skip lnstructlons have the following format:

These instructions have the following format:

12 11

F=O

8 7
Fl

3
SK

1211

F=O

Enhanced skip lnstructlons are identified when the F
and Fl fields are both 0, and the F2 and SK fields are
not both O. (If these fields are both 0, the instruction Is
an SLS.)

Decrement and repeat lnstructions are specified when
the F field Is 0, the Fl field is 6, bit 4 is 0, and the
Ra and SK fields are not both O. (If these fields are
both 0, the instruction is a SPB.)

Enhanced skip lnstructlons (similar to the basic skips;
such as SAZ) contain two parts: operation field (F2)
and skip count (SK). The F2 field determines the
operation (I.e., skip on register I, 2, 3, or 4 if zero,
nonzero, positive, or negative). The skip count
specifies. how many locations to skip if the skip
condition is met.

Decrement and repeat instructions contain two parts:
register field (ra) and skip count (SK). The register
field specifies which register is to be decremented by
one and checked for the skip condition. The skip count
specifies how many locations to repeat (go backwards)
if the skip condition is met.

When the skip condition is met, the skip count plus one
is added to the P register to obtain the address of the
next instruction (e.g., when the skip count is one, go to
P + 2). When the skip condition is not met, the address
of the next instruction is P + 1 (skip count ignored).
The skip count does not have a sign bit.
If F2 = 0 (S4Z), the skip count cannot be 0 because the

When the skip condition is met, the skip count is
subtracted from the P register to obtain the address of
the nEad; lnstructlon (e. g. , when the skip count is one,
go to P - 1). When the skip condition is not met, the
address of the next instruction is P + 1. The skip
count does not have a sign bit.
Note that Ra = 0 and bit 4 = 1 are reserved for future
expansion.

instruction would be an SLS.
The lnstruction descriptions are given In table 4-11.

TABLE 4-11. ENHANCED SKIP INSTRUCTIONS
Instruction

Mnemonic

Description

Skip if Register Zero
F2 = 0, 4, 8, or C
r = 4, I, 2, or 3

SrZ SK

Skip if Register Nonzero
F2 = I, 5, 9, or D
r = 4, I, 2, or 3

SrN SK

Skip if register r is not a positive 0 (not all bits are 0).

Skip if Register Positive
F2 = 2, 6, A, or E
r = 4, I, 2, or 3

SrP SK

Skip if register r is positive (bit 15 Is 0).

Skip if Register Negative
F2 = 3, 7, B, or F
r = 4, I, 2, or 3

SrMSK

Skip if register r is negative (bit 15 is a 1).

88973500 A

Skip if register r is a positive 0 (all bits are 0).

4-19

The miscellaneous iD8truction formats are:

The instruction description is:
Decrement and Repeat if Posltlve
Ra = I, 2, 3, 4, 5, 6, or 7

DrPSK

1. Load Micro Memory

r = I, 2, 3,4, Q, A, or I
1

Decrement the contents of register r by one.
Operation on overflow is the same as for the ADD
instruction. Repeat (go backwards) SK locations
if the contents of register r are positive (bit 15 is
0), otherwise execute the next instruction.

Micro Address

Upper (0) or _ _....J
lower (1) micro
instruction

MISCELLANEOUS

Initially, the Q register contains the number of 32-bit
micro-memory instructions to be transferred (if Q = 0,
no instructions will be transferred). Register 1
contains the starting address of micro memory.
Register 2 contains the starting address of MP macro
memory.

Miscellaneous instructions have the following format:

12 11
F' 0

8
F1= B

5
Ha

4 3

10 I

Miscellaneous instructions are specified when the F
field is 0, the F1 field is equal to a decimal 11
(hexadecimal B), bit 4 is 0, and Ra and F3 fields are
not both O. (If these fields are both 0, the instruction is
an NOP.) All of the miscellaneous Instructions are
privileged instructions; i.e. , if they are executed by an
unprotected program, they will cause a program protect
violation.

The most significant bit (15) of the contents of the
starting address will be transferred to the most
significant bit of the first micro instruction. The least
significant bit (0) of the contents of the starting address
plus one will be transferred to the least significant bit.
This instruction is Interruptible after storing each 32hit micro memory instruction, and when registers I, 2.
and Q are incremented/decremented to allow the
instruction to be restarted after any interruption. When
the instruction is completed, these registers will
contain the following rather than their original values:

Miscellaneous instructions contain two parts: operation
field (F3) and register field (Ra).
If Ra is nonzero, the F3 operation field can select up to
16 miscellaneous instructions with register Ra used to
specify an operand. If Ra is 0, the F3 operation field
can select up to 15 more miscellaneous instructions
without any explicit operand specified.

All the miscellaneous instruction descriptions are given
in table 4-12. Those instructions that require more
detail are described below.

Q -0

Rl- (R1)i+(Q)i
R2 - (R2)i+2*(Q)i
Where: i is the initial value before execution.
2. Set/Sample Output or Input

""
15
Q)

tl
·60

~L---------~-L----~----~~-r__~

Port No.
Set/Sample
condition bit

4-20

88973500 A

TABLE 4-12. MISCELLANEOUS ENHANCED INSTRUCTIONS
Instruction

Mnemonic

Description

Load Micro Memory
F3 = 1
Ra = 0

LMM

Load a 32-bit micro-memory instruction into read/write micro
memory from 16-bit MP macro memory. (For read-only micro
memory or no micro memory, no operation is executed.)

Load Registers
F3 = 2

LRG

Registers I, 2, 3, 4, Q, A, I, M, and the overflow indicator are
loaded with the contents of nine storage locations, beginning at a
storage location specified by the contents of the contents of the
next location, P + 1. The contents of the nine storage locations
will not be altered and the next instruction will be executed at
location P + 2 (i.e., the LRG instruction is a two-word
instruction). Refer to figure 4-1.

store Registers
F3 = 3
Ra = 0

SRG

Registers I, 2, 3, 4, Q, A, I, M, and the overflow indicator
are stored into nine storage locations specified by the contents
of the next location, P + I, incremented by a decimal 10. The
contents of the registers will not be altered and the next instruction will be executed at location P + 2 (i. e. , the SRG instruction
is a two-word instruction). Refer to figure 4-2.

Set/Sample Output or Input
F3 = 4

SIO

Set one word from register A for output to an external device.
The word in register Q selects the receiving device.
For input, one word from an external device is sampled (input)
to register A. The word in register Q selects the sending device.

Sample Position/status
F3 = 5
Ra = 0

SPS

Sample (input) to the A register the position and status of aMOS
device. which has caused an MP macro interrupt. The word
in the Q register selects the device. This instruction also
provides for clearing the M05-generated MP macro interrupt.

Define Micro Interrupt
F3 = 6

DMI

Define the use of one of the 12 available micro interrupts. (The
use of micro interrupts 12 through 15 is restricted for internal
use.) This instruction allows a micro interrupt to be enabled/
disabled and defined for auto-data transfer (ADT) or special
usage.

CBP

Clear the MP macro breakpoint interrupt. This interrupt
occurs when the following conditions are true: macro breakpoint
is externally selected, macro breakpoint interrupt option is
externally selected, the MP recognizes a breakpoint condition
and generates an MP macro breakpoint interrupt because of b.

Generate Character Parity
Even
F3 = 8
Ra = 0

GPE

Set or clear bit 7 of the A register so that bits 0 to 7 have an
even parity. The other bits in the A register are not altered.,

Generate Character Parity

GPO

Set or clear bit 7 of the A register so that bits 0 to 7 have an
odd parity. The other bits in the A register are not altered.

Ra = 0

Clear Breakpoint Interrupt
F3 = 7
Ra = 0

Odd
F3
Ra

=9
=0

88973500 A

4-21

TABLE 4-12. MISCELLANEOOS ENHANCED INSTRUCTIONS (Continued)
Description

Mnemonic

Instruction
Scale Accumulator
F3 =A
Ra = 0

ABC

Shift the A register left (end-around) until bits 14 and 15 of the
A register are different. Upon completion of the instruction,
register 1 will contain the number of spaces that the A register
was shifted. (This number may range from 0 to 14.) If the
A register is ±O (0000 or FFFF16)' no shift has been done and
register 1 will contain -0 (FFFF16).

Load Upper Unprotected
Bounds
F3 = 0
Ra = 1,2, 3, 4, 5, 6, or 7
R = I, 2,3,4, Q, A, or I

LUB R

Load the upper unprotected bounds register from the contents of
register R.

Load Lower Unprotected
Bounds
F3 = 1
Ra = It 2, 3,4, 5, 6, or 7
R = I, 2, 3, 4, Q, A, or I

LLBR

Load the lower unprotected bounds register from the contents of
register R.

l:xecute Micro Sequence
F3 = 2
Ra=I, 2, 3,4,5,6, or7
R = I, 2, 3,4, Q, A, or I

EMSR

Transfer machine control to the upper micro Instruction of the
'Page/micro-memory address in bits 0 to 15 of register R. A
section of micro memory is assumed to have been previously
loaded.

3. Sample Position Status

I.<

11 10 9

11
,

•

j(~
<

....III
Q)

~ 15

II
4.

12 11
0

Status

Position

LLSB

I ]
0

Auto-data
transfer

if~
~

Enable/disable
interrupt

1514

12 11

'60
Q)

Micro-Memory Address

<
transfer

Define Micro Interrupt

4-22

ADT Table Address

Port No.
I.<

Nos. 12-15 are
not used

Micro
Interrupt
No.

When bit 15 of the A register is set to a I, a jump is
made to the upper micro instruction of the page/micro
memory In bits 0 to 14. A section of micro memory is
assumed to have been previously loaded, and it must
process the micro interrupt properly and return control
to the current macro instruction address (P) by jumping
to the lower micro instruction of micro-memory
address 3E16 in micro page zero. Registers P, A, Q

88973500 A

o
1

F3=2

ADDRESS OF X

o
o
1

F3=3

~~~--~--~~

ADDRESS OF X

NOT USED
1
2
3

4
5

7
M

NOT USED
OVERFLOW

Figure 4-2. SRG IDBtrucUon

88973500 A

4-23

and all of file 2 should not be altered, and return must
be within 12.5 microseconds.

2. The macro programmer must execute a OM!

instruction. This command specifies where
the block of data is, how long it is, the direction
.(input/output), and the device's address.

CAUTION
The MP micro function, SUB-, must not be
used. Extreme caution should be exercised in
using this option, since it provides an eecape
from the 1700 emulation being performed.

3. The ADT operation is then initiated by an INP,
OUT, or SIO instruction as specified by the
particular device.

5. Execute Micro SequEllce

~ 15

8 7 0

12 11
0

Page

Micro-Memory Address

IX:

An EMS to non-existant micro memory may cause an

indeterminate result. Control should be returned to the
next macro-instruction address (P + 1) by jumping to
the lower micro instruction of micro-memory address
3E16 in micro page zero. Registers P, A, Q, and all
of file 2 should not be altered, and return must be
within 12.5 microseconds (or the micro sequence must
be interruptible).
CAUTION
Extreme caution should be exercised in using
this option, since it provides an escape from
the 1700 emulation being performed.

While the ADT operation is in progress, the emulator
is executing instructions. After each instruction is
executed, interrupts are checked. When the particular
ADT micro interrupt becomes the highest active
interrupt, the next data is input or output. After the
J.nterruption, the next instruction is executed, except
whe.'l another interrupt is active.
When the ADT operation is completed (or if there is an
error), a macro interrupt is generated. The macro
programmer may then disable the ADT micro interrupt
or initiate another ADT operation to or from the device.
For MOS devices, an SPS instruction must be
performed to clear the macro interrupt.
The following are the four types of ADT tables specified
by DMI instructions.
1. AOT Table for a Single A/Q Device:

AUTO-DATA TRANSFER
Auto-data transfer (ADT) provides for pseudo direct
memory transfers of data blocks to or from a device.
At the macro level, the transfer appears as a direct
memory access (DMA) transfer. At the micro level,
the 1700 emulator processes each data interrupt and
inputs or outputs the next data in a singular fashion.
Thus, ADT takes less time than input/output via the
INP, OUT, or SIO instructions, but more time than a
true DMA transfer.

1 0

Station/Di rector

FWA-1 and CWA

LWA

Not Used

Table 4-13 gives a detailed description of these four
words.

To accomplish an ADT for a particular device, perform
the following:
1. The device and its controller must adhere to the
auto-data transfer specifications in the Microprogrammable Computer I/o Specification.

88973500 A

TABLE 4-13. ADT TABLE FOR A SINGLE A/Q DEVICE
Bits

Word
1

15
14
12

}

Description

Must be set to O.

Word operation; data is transferred one word at a time. Normally, a
total of (CW A - FWA + 1) words will be transferred.

Character operation; data is transferred one character (eight bits) at a
time. On input, the first character will be stored in the most significant
half (bits 15 to 8) of the current words address; the second character
in the least significant half (bits 7 to 0). Subsequent pairs of characters
will be output from the most Significant half ot' the current word address;
the second character from the least Significant half. Normally a total
of 2 X (CWA - FWA + 1) characters will be transferred.

A read ADT operation

A write ADT operation

10 through 7

The equipment number of the device. This number can not conflict
with any M05 I/O port numbers.

6 through 0

The station/director bits of the device to execute the ADT operation.
These bits should specify a data (not a status/function) transfer.

Initially set to the first word address less one (FWA - 1) of the data block
to be transferred. This word is used as the current word address (CWA)
as the ADT operation is in progress and points to the last word read or
stored. Each time a word (or two characters) is transferred, CWA is
incremented. Specifically, CWA can be used to ascertain whether all the
data was transferred after the ADT operation was completed (if CWA =
LWA, all the data has been transferred).

The last word address (LWA) of the data block to be transferred

Reserved for future use; must be set to O.

88973500 A

4-25

15 14 13 12 11 10 9
1

7 6, 5

IIcl 141
0

Equipment
No.

7 •

1r6 II'5

tr4

3 1r2 1r1

Iro

Clock Counter

try. trw

Clock Limit

Not Used

h'
19 1r18

Not Used
0

11 1. 13 12 11 10

3 2

tr31 tr3) ~3l T215 h'27 tral Irz; Ira! frZ3 1r2 T21 frID

ADT Table for the Clock.

Equipment
No.

h'
iI'
2 TIE
tr14 [1'1 12 TIl trw 9 1r8 tr7
3

ADT Table for Multiple A/Q Devices:

1 1

I I I I IEqUl~:.ent I
0

Station I Director

Station/Director
Detailed descriptions of this type are given in table

FWA-1 and CWA

LWA

Not Used

4-15.

.
2

.....

't
.....

I7clC 0 Iiv:1 Equipment
No .

ADT Table for Single or Multiple M05 Devices

Station/Director

FWA-l or CWA

LWA

Not Used

FWA-1 and CWA
LWA

l'
't
.....

Not Used

o 0

~~~~~~~----~~----~~
~

This type of ADT table consists of 1*4+4 words, where
1 is the number of multiple A/Q devices (up to 32) on
one micro interrupt.

FWA-l or CWA

~~----------------------------~

LWA
Not Used

Table 4-14 provides detailed descriptions of these
words.
The ADT table for this type consists of (1-1)*4+4
words, where I is the number of M05 devices (up
to 8) on one micro interrupt. Detailed descriptions
of this type are given in table 4-16.

4-26

88973500 A

TABLE 4-14. ADT TABLE FOR MULTIPLE A/Q DEVICES

Description

Bits

Word
15

Must be 0

Must be 1

13 through 11

Must be 0

10 through 7

The equipment number of the device. This number can not conflict with any M05
I/O port numbers.

6 through 2

The maximum station (or channel) number; equivalent to the number of
multiple A/Q devices less one on a wire interrupt. Station numbers must be
contiguous. Certain peripheral devices have specifiC parameters for these
bits; refer to the peripheral controller reference manual.

Must be 1

Must be 0

2
3

Contain termination bits for the 32 devices. Initially, they must be all O.
When a macro interrupt occurs, one or more of these bits will be set to 1 to
indicate that one or more ADT operations have terminated. Thus T 7 = 1
indicates that the seventh device has terminated its ADT operation. After
receipt, the bit should be cleared via an instruction that locks memory
(e.g., a CLF instruction).

Reserved for future use; must be O.

5
6
7

Defined the same as a single A/Q device, except for bit 14 of the first word
(1*4+1), which must be 1. Refer to table 4-13.

t
tWords 1*4+1, 1*4+2, 1*4+3, and 1*4+4, where 2:5: 1:5: 32

88973500 A

4-27

TABLE 4-15. ADT TABLE FOR THE CLOCK
Bits

Word
1

Description

Must be 1

14 through 11

Must be 0

10 through 7

The equipment of the clock; must be set to 1.

6 through 0

The station/director bits of the clock, which is always equal to 70 16 , (Thus,
word 1 should equal 80F 0 16 , )

Initially set to 0; whenever the clock has been enabled, the clock counter
will be incremented every 3 1/3 milliseconds.

The clock limit, which is interpreted as a multiple of 3 1/3 milliseconds.
When the clock counter equals the clock limit and the macro-clock interrupt
is enabled, the macro-clock interrupt will occur. Thus, if the clock limit
is five, the clock interrupt is 16 2/3 milliseconds, or 60 times a second.
To continue the process, the clock counter should be reset to 0, or the limit
counter should be incremented by its original value (e. g., 5). In the latter
methOd, the clock counter can function as an elapsed time counter. Note
that if the macro-clock interrupt is not answered the clock limit will still
continue to be incremented.

Reserved for future use; must be O.

4-28

88973500 A

TABLE 4-16. ADT TABLE FOR SINGLE OR MULTIPLE M05 DEVICES
Word
1

Description

Bits
15

Must be 1

Must be 0

Defined the same as a single A/Q device.

Must be 0

o
1

A read ADT operation
A write ADT operation

10 through 7

The part number of the device. (Bit 10 is always set to 1.) Part numbers
are analogous to the A/Q I/O equipment numbers and thus cannot conflict
with them.

6, 5

Must be 0

4 through 2

The maximum position number; equivalent to the number of multiple M05
devices, less one, on a wire interrupt. Position numbers must be contiguous
(i.e.,OtoI-l).
Initially set to the first word address (FWA-l) of the data block to be
transferred; this word is used as the current word address (CWA) as the
ADT operation is in progress and points to the last data word read or stored.
Each time a word (or two characters) is transferred, CWA is incremented.
Specifically, CWA can be used to ascertain whether all the data was transferred
after the ADT operation was completed (1. e., if CWA = LWA, all data has
been transferred).
The last word address (LWA) of the data block to be transferred
Reserved for future use; must be O.

Worde(I-l)*4+1, (1-1)*4+2. (1-1)*4+3. and (1-1)*4+4. where 2::5 1 ::58. are defined in the
same manner as words 1. 2. 3. and 4. respectively.

88973500 A

4-29

INTERRUPT SYSTEM

This system enables the program to establish an
interrupt priority so that an lDterrupt of high priority
can lDterrupt the machine while it is processing an
interrupt of a lower priority. The return path to the
interrupted program is clearly established and saved.

MASK REGISTER
The mask register is the enable for each interrupt
state or line. Bit 0 of the mask register corresponds
to the lDterrupt line 0, bit 1 to line 1, etc. To enable
an interrupt line, its corresponding bit in the mask
register must be set. The mask register is set by the
lDter-register lDstruction.

INTERRUPT TRAP LOCATIONS
Trap locations are established for each interrupt line.
They are in the range of addresses 0100 through 013C •
These addresses are reserved for interrupts unless
that partiCular lDterrupt is not being used. The
assignment for each lDterrupt state or Une is shown in
table 5-1'.

PRIORITY
The computer program controls the interrupt priority
by estabUshing an interrupt mask for each interrupt
state, which enables all higher priority interrupts and

TABLE 5-1. INTERRU PT STATE DEFINITIONS

Exit State

Location of
Return Address

Location of First
Instruction after
Interrupt Occurs

0100

0101

0104

0105

0108

0109

010C

010D

0110

0111

0114

0115

0118

0119

011C

OllD

0120

0121

0124

0125

0128

0129

012C

012D

0130

0131

0134

0135

0138

0139

013C

013D

Value of 41

Interrupt
State

88973500 A

5-1

disables all lower priority interrupts. When an
interrupt state is entered, the mask for that state is
placed in the mask register. Therefore, there may be
up to 16 levels of priority. It is possible to change
priority during execution of a program.

INTERNAL INTERRUPTS
Interrupts are also generated by certain conditions
arising within the computer. These are called internal
interrupts. H such a condition occurs, it generates
interrupt 00 (interrupt mask bit 00). Normally,
internal interrupts are assigned the highest priority.
The internal interrupts are:

•

Storage Parity Error

•

Program Protect Fault

•

Power Failure

Interrupt system is de-activated and control is
transferred when the interrupt occurs. In 32K mode
the overflow is cleared, while in 65K mode the SOV or
SNO instruction must first be executed. The program
then stores all registers, including the mask register,
in addresses reserved for this interrupt state and loads
the mask register with the mask to be used in this state.
The Is in the mask indicate the interrupts that have a
higher priority than the interrupt being processed. The
mask should not have a 1 in the pOSition of the interrupt
being processed; this would lose the return link. The
program then activates the interrupt system and
processes the Interrupt.
The computer exits from an interrupt state when the
program inhibits the interrupt and restores the
registers (including the mask register). After loading
the register, the program executes the exit interrupt
command with delta equal to the lower eight bits of the
base address of the interrupt state. This command
reads the ,storage location where the return address is
stored. The overflow indicator is set or cleared as
specified by bit 16. The interrupt system is activated
and control is transferred to the return address.

OPERATION
The computer can distinguish between up to 16 (1
internal, 15 external) macro interrupts. Each of these
Interrupts has Its respective address to which control
is transferred when the interrupt is recognized.
When the computer is processing a particular interrupt,
it will be defined as being in that interrupt state (state
00 through 15). Thus, the interrupts and their
respective bits in the interrupt mask register are
numbered 00 through 15. An interrupt in bit 7 will put
the computer in interrupt state 7, etc.
Before the computer can recognize any interrupt, the
mask bit for that interrupt must be set and the interrupt
system must be activated. The mask register may be
set by an inter-register command and the interrupt
system can be activated by an enable interrupt command.
When an interrupt is recognized, the computer
automatically stores the returu address in the storage
location reserved for that interrupt state. H 32K
multilevel indirect mode has been selected, bit 15 of the
storage location is set or cleared to record the current
state of the overflow Indicator. If 65K multilevel
indirect mode has been selected, all 16 bits are required
to save the return address. Thus, the program must
check for an overflow condition with an SOV or SNO
instruction and record this condition for restoration of
the overflow indicator. In both 32K and 6!:iK modes the

5-2

EXAMPLE
The following listing and sample program steps apply
if there were five different possible interrupts and
three levels of priority:
Interrupt 01
02
05
03
04

High priority

} Mid-priority
} Low priority

543210
Mask 1

1 1 1 1·1 1 Mask used for main program

Mask 2

1 0 0 1 1 1 Mask used for state 03, 04

Mask 3

o0 0 0 1 1
o0 0 0 0 1

Mask 4

Mask used for state 02, 05
Mask used for state 01

Main Program

State 02 Program

Set mask register to Mask 1
Enable interrupt

Store registers
Set mask to Mask 3
Enable interrupt

88973500 A

Inhibit interrupt
Replace registers
Exit Interrupt 02
State 01 Program

State 03 Program

Store registers
Set mask to Mask 4
Enable interrupt

store registers
Set mask to Mask 2
Enable interrupt

Inhibit Interrupt
Exit interrupt 01

88973500 A

State 04 Program

State 05 Program

Store registers
Set mask to Mask 2
Enable Interrupt

store registers
Set mask to Mask 3
Enable interrupt

Inhibit interrupt
Replace registers
Exit interrupt 04

Inhibit interrupt
Replace registers
Exit interrupt 05

Inhibit Interrupt
Replace registers
Exit Interrupt 03

5-3

PROGRAM

The MP computer has a program protect system to
protect a program in the computer from any other
nonprotected program also in the computer. The
system is built around a program protect bit contained
in each word of storage. If the bit is set, the word is
an operand or an instruction of the protected program.
All operand and instruction locations of the protected
program must have the program protect bit set. None
of the instructions or operands of the nonprotected
program can have the program protect bit set.

PROTECT

Program protect is enabled by setting bit 8 in the function control register. If this bit is not set, then none
of the above violations are recognized, with the exception of the external storage access protect violation.

STORAGE PARITY ERRORS AS
RELATED TO PROGRAM PROTECTION
If a nonprotected instruction is attempting to write into

Whenever a violation of the program protect system,
other than a direct storage access violation, is detected,
the program protect fault flip-flop is set and an internal
interrupt is generated. A violation indicates that the
nonprotected program has attempted an operation that
could harm the protected program.

storage and a storage parity error is present or occurs,
the word in storage is not altered and a Storage Parity
Error interrupt is enabled.
If a protected instruction is attempting to write into

storage and a storage parity error occurs, the word is
written into storage and a Storage Parity Error
interrupt is enabled.

PROGRAM PROTECT VIOLATIONS

If the computer attempts to execute a SPB or CPB

The following are the program protect violations:

Instruction and a storage parity error occurs. these
become Pass instructions and a storage parity error
interrupt is enabled.

•

A nonprotected instruction attempts to write in a
protected storage location. The contents of the
storage location are not changed.

•

An attempt is made to write into a protected
storage location via external storage access when
a nonprotected instruction was the ultimate source
of the attempt. The contents of the storage
location are not changed.

•

An attempt is made to execute a protect ed
instruction following execution of a nonprotected
instruction. The protected instruction Is executed
as a nonprotected selected stop instruction.
However, it is not a violation if an interrupt
caused this sequence of instructions.
An attempt is made to execute the following
instructions when they are not protected: any
interregister instructions with bit 0 = 1, EIN, ITN,
EXI, SPB, CPB, or any miscellaneous
instructions (OBxx). Those instructions become a
nonprotected selective atop instruction under these
circumstances.

88973500 A

SET/CLEAR PROGRAM PROTECT BIT
The program protect instructions (SPB or CPB) and the
bounds instructions (LUB and LLB) are the only way in
which the program protect bit may be set or cleared in
each word d. storage.

PROGRAMMING REQUIREMENTS
The following program requirements must be met:

•

The program package that handles all interrupts
for the nonprotected program must be completely
checked out. This program must also be part of
the protected program.

•

The protected program must be a completely
checked-out program.

6-1

PERIPHERAL EQUIPMENT PROTECTION
All peripheral equipment that Is essential to the
operation of the protected program must have a bit in
the FeR to designate if the device is protected. If the
bit is set, the peripheral device responds with a reject

6-2

to aU nonprotected commands (except status request)
addressed to it. All protected commands have a
normal response. If the bit is not set, the peripheral
device responds in the normal manner to protected
and nonprotected commands.

88973500 A

I/O DEVICES

The standard assignments for MP I/O devices are
listed in table 7-1. Descriptions of the panel/program
device and clock follow.

Bit
(A Register)

End-of-Operation Send an interrupt
Interrupt Request signal when the
controller is not busy.
In the EOP state the
controller will accept a
mode change.

Alarm Interrupt
Request

Not used

ADT Mode

Not used

Select Write
Mode

An output operation;
does not clear the
alarm status.

Select Read
Mode

An input operation

Connect Printer Select a mode of
operation in which the
printer (with the paper
tape punch, when used)
and the tape reader
(when used) are both
connected to the
controller. Data read
from the paper tape in
this mode will also be
printed (and punched).

Not used

Disconnect
Printer

Computer Instruction
Q Register

Input to A

Output from A

0090

Write

Read

0091

Director Function (1)

Director Status (2)

Operation

PANEL/PROGRAM DEVICE
When referencing the panel/program devices, the Q
register should contain either 009016 or 009116
according to the following table:

Function

Send an interrupt
signal when the Lost
Data Status is active.

Auto-tructions, the first execution time is for A or Q register destinations, the second time
is for M, A and M, or Q and M registers, the third time is for A and Q, and the fourth time for A and Q
andM.

88973500 A

C-7

Deflnttton

Mnemonic
TCM

Transfer Complement M

Execution
Times (,.&sec)
1.46~ 1.62, 1. 79,

OP Code
0

8 to F

1.96
/

TCQ

Transfer Complement Q

1.18, 1.34, 1.34,
1. SIt

o to 7

TRA

Transfer A

1. 18, 1. 34, 1.34,
1.51t

o to 7

TRB

Transfer Q+M

1.46 1.62, 1. 79,
1.96

8 to F

TRM

Transfer M

1.46, 1. 62, 1. 79,
1.96 t

8 to F

TRQ

Transfer Q

1. 18, 1. 34, 1.34,
1.51t

o to 7

XFr

Transfer Register

2.47tt

0,
1 to 7
1 to 7

t For inter-register instructions, the first execution time is for A or Q register destinations, the second time

is for M, A and M, or Q and M registers, the third time is for A and Q, and the fourth time for A and Q
and M.
ttAdd .67 microseconds for XFt instruction.

C-8

88973500 A

INDEX

A register
2-3
AAB
4-8
AAM 4-8
AAQ
4-8
Absolute constsnt mode
4-2, 3, 13, 14
Absolute indirect mode, 8-bit
4-2, 3, 11, 12
Absolute mode, 8-bit
4-2, 3, 11, 12
4-4
ADD
Addresses
4-1; B-1
base
4-1
4-1, 2
effective
indexing
4-1
indirect
4-1
instruction
4-1

Bit generator
2-3
BP, see Breakpoint
Breakpoint
3-6

Address~

enhanced storage reference
4-11
storage reference instruction
4-2
ADT, see Auto data transfer
ADT tables
clock
4-26, 28
M05 devices
4-26, 29
multiple A/Q devices
4-26, 27
single A/Q device
4-24, 25
ADQ
4-5
ALS
4-10
ALU, see Arithmetic/logical unit
AMr
4-16
AND
4-5
ANr
4-15
A/Q, 1700
4-15
A/Q-DMA, 1700
I-I, 3
Arithmetic/logical unit
1-5; 2-1, 3
output
2-5
ARr
4-15
ARS
4-10
ASC
4-22
Auto-data transfer
1-3; 4-24
Auto-display
3-4, 7
Autoload
3-1

Base address
4-11
Basic configuration
1-1; 2-1
Basic instructions, see Instructions

88973500 A

CAB
4-8
CAM 4-8
CAQ
4-8
4-17
CCE
Characteristics
functional
1-1
general
I-I, 2
mechanical
1-3
physical
I-I, 3
Chassis
layout
1-7
logic
1-3
power supply
1-3
standard
I-I, 5
Circuit cards
I-I, 6
Clear breakpoint interrupt instruction
4-21
Clock, real-time
1-3; 2-5, 6; 7-3
ADT table for
4-26
CLP
4-8
Commands
@ 3-7
ESC
3-7
G (BELL)
3-7
Configuration, basic
1-1; 2-1
enhanced
1-5
Console, RS232-C compatible
1-3
Control cards, see Control 1 or Control 2
Control commands, panel interface
3-4
breakpoint
3-6
J
3-5
K 3-6
L
3-6
MC
3-4
stop/go
3-4
Control, MP
2-5
Control 1
1-5; 2-1
Control 2
1-5; 2-1
Conventional processor organization
1-4
Core memory, see Macro memory

Index-1

Correspondence, MP/1700
CPB
4-7
CPU, see Micro processor
CrE
4-17

3-5

Data flow
1-5
Data registers
2-3

Data transfer
2-1Deadstart
3-1
Decrement and repeat instructions
4-19; B-3
Define micro interrupt instruction
4-21
Digital processor organizations
1-4
Dimensions
1-3
Direct memory access
1-2
channel
1-5
Display codes
3-3
DMA, see Direct memory access
DVl
4-4

EAB
4-8
EAM 4-8
EAQ
4-8
4-2, 3, 11
Effective addresses
4-2, 3
8-bit absolute mode
8-bit absolute indirect mode
4-2, 3
8-bit relative
4-2, 3
8-bit relative indirect
4-2, 3
EIN
4-6
EMS
4-24
EMS R
4-22
Emulation
1-1; 2-1
Emulator, 1700
2-1
ENA
4-6
Enhanced
decrement and repeat instructions
4-19; B-3
field reference instructions
4-17; B-4
inter-register instructions
4-18; B-4
miscellaneous
4-20; B-4
MP instructions
4-9
processor
1-5; 2-2
1700 instruction repertoire
1-3; B-3
skip instructions
4-19; B-3
storage reference
4-9; B-3
Enhanced skip instructions
SrM SK
4-19; B-3
SrN SK
4-19; B-3
SrP SK
4-19i B-3
SrZ SK
4-19; B-3

Jndex-2

Enhanced storage reference instructions
4-14; B-3
AMr 4-16
4-15
ANr
4-15
ARr
4-17
CCE
CrE
4-17
4-16
LCA
4-16
LRr
4-16
OMr
4-16
ORr
SBr
4-15
SCA
4-16
SJE
4-14
SJr
4-15
SRr
4-16
Environment, operating
1-5
ENQ
4-6
4-5
EOR
ESC
3-7
Execute micro sequence instruction
4-22, 24
Execution times, instructions
C-l
EXI
4-7
External I/O interface
1-7

F register
2-3
FCR, see Function control register
Features
1-3
Field reference instructions
4-17; B-4
CLF
4-18
LFA
4-18
SEF
4-18
SFA
4-18
4-18
SFN
SFZ
4-18
2-4
File 1
File 2
2-3
3-1, 2
Function control register
1-8
Functional block diagram

Generate character parity even instruction
Generate character parity odd instruction
GPE
4-21
GPO 4-21

I register
lIN
4-7
INA
4-6

4-21
4-21

2-3

88973500 A

Indexing
4-1, 11
Indirect address
4-11
INP
4-6
INQ
4-6
Input data
2-6
Input/OIltput
1-2
operations
3-7
Instruction address
4-11
Instruction execution times
C-l
Instructions
address mode
B-1
decrement and repeat
4-19
enhanced inter-register
4-18
MP
4-9
skip
4-19
storage reference
4-9
field reference
4-17
format
4-1
inter-register
4-5
miscellaneOlls
4-20
register reference
B-1
set· 4-1
skip
4-7; B-2
storage reference
4-1; B-1
Interface
I/O-TTY
1-7
maintenance panel
2-6
Internal interrupts
5-2
Internal peripheral controller bus
2-5
Inter-register instructions
4-5; B-2
AAB
4-8
AAM 4-8
AAQ
4-8
EAB
4-8
EAM 4-8
EAQ
4-8
CAB
4-8
CAM 4-8
CAQ
4-8
CLP
4-8
LAB
4-8
LAM 4-8
LAQ
4-8
SET
4-8
TCA
4-8
TCB
4-8
TCM 4-8
TCQ
4-8
TRA
4-8

88973500 A

4-8
4-8
truth table
4-9
Interrupt state definitions
5-1
Interrupt system
5-1
mask register
5-1
priority
5-1
trap locations
5-1
Interrupts
2-3, 6
address
2-4
internal
5-2
I/O, see Input/output
I/o devices 7-1
panel/program
7-1
real-time clock
7-3
I/O interface
1-1; 1-7
external
1-7
I/O ports
1-2
I/O-TTY display controls
2-5
I/O-TTY module
2-5
TRB

TRQ

J control function
4-4
JMP

3-5

K control function
2-4
K register

3-6

3-6
L control function
4-8
LAB
LAM 4-8
LAQ
4-8
LCA
4-16
LDA
4-5
LDQ
4-5
LLB R 4-22
LLS
4-10
LRS
4-10
LMM 4-21
Load lower unprotected bounds instruction
Load micro memozy instruction
4-20
Load registers
4-21, 23
Load upper unprotected bounds instruction
LRG 4-21, 23
LRr
4-16
LUB R 4-22

4-22

Index-3

Macro execution time 1-2
Macro instructions
1-1
Macro interrupts
5-2
Macromemory 1-6; 2-4
configuration 2-5
speed 1-2; 2-5
t,ype
1-2
Maintenance panel 1-1; 2-6
Maintenance panel interface 1-1; 2-6
Mask registers
2-3, 4; 5-1
Master clear 3-4
Mechanical characteristics
1-3
Memory
core
1-2
cycle time
1-2
interface 1-5; 2-4
semiconductor 1-1
Micro instruction register word 1-2
Micro memory
I-I, 5
access time
1-2
addresses
1-5
size 1-2
t,ype
1-2
Micro processor, see MP processor
Micro program
1-1
Micro-programmable computer 1-1; 2-1
basic configuration
1-1
enhanced configuration 1-5
Micro programming 1-1
Miscellaneous instructions
4-20; B-4
ASC
4-22
CBP 4-21
DMZ
4-21
EMS R 4-22
GPE 4-21
GPO 4-21
LMM 4-21
LRG 4-21
SIO
4-21
SPS
4-21
SRG
4-21
Modes
absolute constant
4-2, 3, 13, 14
absolute, 8-bit
4-2, 3, 11, 12
absolute indirect, 8-bit 4-2, 3, 11, 12
auto display 3-7
echo
3-7
panel 3-7

program
3-7
relative, 8-bit 4-2, 3, 12, 14
relative, 16-bit 4-2, 3, 13, 14
relative indirect, 8-bit 4-2, 3, 12, 14
relative indirect, 16-bit 4-2, 3, 13, 14
storage, 16-bit 4-2, 3, 13, 14
MP circuit card 1-1
construction of 1-1
MP control
2-5
MP/1700 register correspondence
3-5
MSOS autoload 3-1
MUI 4-4
Multilevel processor organization
1-4

N register
2-4
N/K register
2-4
Non-operating environment
NOP 4-6

1-5

OMr 4-16
Operands
4-7
Operating environment
1-5
Operating procedure
3-1
Operator interface
3-1
Options, standard 1-1
Organization
1-4
conventional
1-4
multilevel
1-4
ORr 4-16
OUT
4-16

P register
2-3
Panel interface
control commands
3-4
simulation 2-1, 5
Panel, maintenance
2-6
Panel/program device
7-1
Parity bit 1-2, 6; 2-4
Peripheral equipment protection
6-2
P~sical characteristics
I-I, 3
Ports, I/o 1-2
Power requirements
I-I, 3
Power supplies 1-1
p~sical dimensions
I-I, 3
weight 1-3
Priority, interrupt 5-1

88973500 A

Processor
characteristics
1-2
organization
1-4
Program protect
peripheral equipment
6-2
programming requirements
system
6-1
violations
6-1
Protect bit
1-2, 6; 2-4
set/clear
6-1
Protect parity bit
1-6

6-1

Q register
2-3
QLS
4-10
QRB
4-10

Read-only memory (ROM)
I-I, 6; 2-1
Read/write memory (RAM)
1-2
Real-time clock
1-3; 2-5, 6; 7-3
Register correspondence, MP/1700
3-5
Register- reference instructions
4-3; B-1
CPB
4-7
EIN
4-6
ENA
4-6
ENQ
4-6
EXI
4-7
4-7
nN
INA
4-6
4-6
INP
INQ
4-6
NOP
4-6
OUT 4-6
SLS
4-6
SPB
4-7
2-1
Registers
2-3
A
2-3
F
I
2-3
K
2-3
mask
2-3; 5-1
N 2-4
N/K
2-4
P 2-3
R

4-11

status/mode
Q 2-3
X 2-3

88973500 A

2-3, 5

Relative indirect mode, 8-bit
enhanced storage reference
storage reference
4-2, 3
Relative indirect mode, 16-bit
enhanced storage reference
storage reference
4-2, 3
Relative mode, 8-bit
enhanced storage reference
storage reference
4-2, 3
Relative mode, 16-bit
enhanced storage reference
storage reference
4-2, 3
Requirements
environmental
1-5
power
1-3
RTJ
4-4

4-12, 14

4-13, 14

4-12, 14

4-13, 14

SAM
4-10
Sample pOSition/status instruction
4-21, 22
SAN
4-10
SAP
4-10
SAZ
4-10
SBr
4-15
SCA
4-16
Selectors
2-1
Semiconductor memory
I-I, 2
SET
4-8
Set/sample input/output instruction
4-20, 21
1700 emulation
2-1
1700 enhanced processor
2-2
1700 Series computers
emulation of
1-1
1700 transform
1-5
1700/MP register correspondence
3-5
Shift instructions
4-9; B-2
ALS
4-10
ARB
4-10
LLS
4-10
4-10
LRS
QLS
4-10
QRS
4-10
3-1
Shutdcrwn
Simulation, panel interface
2-5
16-bit relative indirect mode
enhanced storage reference instruction
4-13, 14
storage reference instruction
4-2, 3

Index-5

16-bit relative mode
enhanced storage reference instruction
storage reference instruction
4-2, 3
16-bit storage mode
enhanced storage reference instruction
storage reference instruction
4-2. 3
SJE
4-14
4-15
SJr
4-7; B-2
Skip instructions
SAM
4-10
SAN
4-10
SAP
4-10
SAZ
4-10
SNF
4-10
SNO
4-10
SNP
4-10
SOY
4-10
SPE
4-10
SPF
4-10
SQM
4-10
SQN
4-10
SQP
4-10
SQZ
4-10
SWS
4-10
4-10
SWN
Skip instructions. enhanced
SrM SK 4-19
SrN SK 4-19
SrP SK 4-19
SrZ SK 4-19
SLS
4-6
SMI. see Status mode interrupt module
SNF
4-10
4-10
SNO
SNP
4-10
SOY
4-10
SPA
4-4
SPB
4-7
SPE
4-10
SPF
4-10
SQM
4-10
SQN
4-10
SQP
4-10
SQZ
4-10
SRG
4-21. 23
4-16
SRr
STA
4-4
Standard options
1-1
Startup
3-1
Status mode interrupt module
1-5; 2-1
Status/mode register
2-3. 5
Stop/go control
3-4

Index-6

4-13. 14

Storage mode. 16-bit
enhanced storage reference instruction
storage reference instruction
4-2. 3
Storage reference instructions
4-1. 4; B-1
ADD
4-4
ADQ
4-5
AND
4-5
4-4
DVI
enhanced
4-9. 10. 14
EOR
4-5
4-4
JMP
LDA
4-5
4-5
LDQ
MUI
4-4
4-4
RTJ
4-4
SPA
STA
4-4
STQ
4-4
SUB
4-4
Store register instruction
4-21. 23
STQ
4-4
SUB
4-4
SWN
4-10
SWS
4-10
System failure
3-1

TCB
4-8
TCM 4-8
TCQ
4-8
Teletypewriter/display controller
Transform
1-1; 2-1
hardware
2-1
jump
2-1
module
2-1
1700
1-5
Transforms
2-1
TRB
4-8
TRA
TRQ

4-13. 14

2-5

4-8

4-8
Trap locations. interrupt
5-1
Truth table
inter-register instructions

Weight
logic chassis
power supply
Word length
1-2

X register

4-9

1-3
1-3

2-3

88973500 A

COMMENT SHEET

MANUAL TITLE _ _C_D_C_®
__M_ic_r_o_-_Pr_o...;gr::..-a_m_ma
__h_le_c_o_m...;p:;..u_t_e_r_F
__
a_m_i-.:ly:....-_______________

1700 Enhanced Processor with Core Memory Hardware Reference Manual
PUBLICATION NO. _ _-..,;;.8. :.8. :.97..:.3:..,.5:..,.0_0_ _ _ _ _ _ _ _ REVISION _ _ _ _B_________________

FROM

NAME: _____________________________________________

BUSINESS
ADDRESS: ____________________________________________________________

COMMENTS: This form is not intended to be used as an order blank. Your evaluation of this manual will be welcomed
by Control Data Corporation. Aslyerrors, suggested additions or deletions, or general comments may
be made below. Please include page number.

I
I
I
I

(!ll

§:
-
Source Exif Data:
File Type : PDF
File Type Extension : pdf
MIME Type : application/pdf
PDF Version : 1.3
Linearized : No
XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19
Create Date : 2016:06:19 18:52:40-08:00
Modify Date : 2016:06:19 19:38:57-07:00
Metadata Date : 2016:06:19 19:38:57-07:00
Producer : Adobe Acrobat 9.0 Paper Capture Plug-in
Format : application/pdf
Document ID : uuid:a6aade68-1e4c-9a47-961e-db035e8baa13
Instance ID : uuid:92780547-0d04-d84d-a233-fad4d0742c73
Page Layout : SinglePage
Page Mode : UseNone
Page Count : 94

EXIF Metadata provided by EXIF.tools

88973500_1700_Enhanced_Processor_with_Core_Memory_Hardware_Reference_Sep77 88973500 1700 Enhanced Processor With Core Memory Hardware Reference Sep77

Navigation menu

Versions of this User Manual:

Views

Navigation