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CQN1lJ)L DATA

'-=I ~ CORl'ORt\110N

CONTROL DATA®
CENTRAL PROCESSING UNIT
AB107-A/AB108-A,
BA201-A/B, BT148-A
BU120-A, GD811-A

ABI07-CID ABI08-C/D

BT148-C1D

GENERAL DESCRIPTION
OPERATION
INSTALLATION AND CHECKOUT
THEORY OF OPERATION
DIAGRAMS
MAINTENANCE
PARTS DATA
APPENDIX
WIRE LIST

HARDWARE MAINTENANCE MANUAL

REVISION RECORD
REVISION
02
10 Jan 74
03
. 25 Oct 74
04
20 r4ar 75

A
27 Au!) 75
B
31 Oct 75
C
12 Jan 76

1------

D

22 Jul 76
E
(July 1977)

F
(Nov 19m

DESCRIPTION
Released Class B ECO CK 456
Obsoletes all previous editions.
ECO's CK 522 and CK 748
Completely revised, obsoletes all previous editions .
Manual revised, ECO CK 1117. Pages added: 6-15.1,6-15.2.
Pages changed: iii, 1-2, 3-5, 3-7, 3-11, 4-5, 4-41, 4-43
5-4, 5-5, 5-8, 5-9/5-10, 5-20, 5-23, 5-27, 5-29, 5-32, 5-36, 5-45, 5-47, 5-48, 5-49, 5-50, 5-51, 5-52,
5-55/5-56,5-57,5-60, 5-61, 5-65, 5-66, 5-83, 5-84, 5-85, 5-86, 5-90, 5-91,5-94,5-96,5-99,5-105,
5-106,5-110,5-111,5-112,5-113,5-114,5-115,5-117,5-121, 5-122, 5-123, 5-124, 5-129, 5-130,-_ -l
5-169, 5-225, 5-248, 5-263, ~-E5/5-276, 5-281, 5-292, 5-293, 5-295, 5-297/5-298, 5-299, 5-301 ,~-:02~
5-305/5-306, 5-309, 5-313, 5-317, 5-321, 5-325/5-326, 5-329, 5-380/5-381, 5-382, 5-383, 5-387, 5-388,
5-389, 5-393, 5-395, 5-397/5-398, 5-399, 5-400, 5-401, 5-402, 5-403/5-404, 6-13, 6-14, 6-15, 6-18,
8-l.
Released Class A, ECO CK 1312.
Obsoletes all previous editions.
Manual Revised: Pages 2-5, 2-6, 3-13,3-19,5-7,9-1,9-147 and xv replaced. ECO CK 1347.
Manual Revised: Includes Field Change Order 1415, 1422, 1431 Pages revised: ii, iii, iv, v, vi, vii,
vi ii, ix, x, xi, xii, xiii, xiv, xv 3-13,4-45,4-46,4-56,5-39,5-87, 5-145/5-146, 5-151/5-152,
5-155/5-156, 5-159, 5-259, 5-379, 5-380, 5-381, 5-382, 5-383/5-384, 5-385/5-386, 5-389, 5-393,
5-397/5-398, 5-403/5-404, 5-408, 5-409, 5-414 to 5-420, 5-421, 5-430, 6-4, 8-1, 8-2, 9-2, 9-26,
9-36, 9-37, 9-40, 9-45, 9-49, 9-55, 9-57, 9-63, 9-7 , 9-80, 9-85, 9-88, 9-89, 9-90, 9-93, 9-98,
9-147/9-148.
Pages added: ..... 3e-13A, 3-13B, 5-160 through 5-166, 5-410, 5-411, 5-412, 5-413, 5-422, 9-2A/9-2B
Released by ECO CK 1421.
Manu.al Revised by ECO CK 1559. With references to ECO CK1526 and CAR's LJL 043, 158, 173 and 174.
ECO CK 1830 answered the following CAR's: LJL046/26B, LJL072/3B3, Internal CAR 406, LJLJ86/50S.
LJL199/515, LJL203-381/517, LJL206/519, LJL2071520 ,LJL211/524. _ ECO's were incorporated: CK1054,
Paoes deleted: 9-2A/9-2B
CK1436 CK1588 CK1788 and FCO CK676. PaQes added: 3-29. 3-30, 8-3.
xi i i xiv xv. xvi. xvi i, 4-5, 4-9, 5-23, 5-32,
PaQes revised: Ii i
vi i i xii
iv v vi
5-36 5-82 5-89, 5-145, 5-296, 5-371 through 5-420, 5-435, 6-4, 6-27. 8-1, 8-2, 9-1 through
9-8, 9-43, 9-61. Updated: Manual-to-Equipment Correlation sheets and Parts Oata.
ECO CK1996 Incorporated Models C and D. See ECO CK1996, CAR LJL209/522, CAR LJL216/531.

Publication No.
89633300

Page i I

©

1974, 1975, 1976, 1977

by Control Data Corporation

Printed in the United States of America

Address comments concerning this
!llanua1 to:
Control Data Corporation
Publ icatlons and Graphics Division
4455 Eastgate Mall
La Jolla, California 92037

....

or use Comment Sheet in the back of
this manual.

"'iii.

·ff

MANUAL TO EQUIPMENT LE VEL CORRELATDI SlEET
1
'''IT . ...
IMMML

RIV

02

03
04

A
C

D,E,
F

F

2
Of .......

'CfCK~CO

0573
0677
0705
0736
0840
1063
1011
0922
1241
1109
1272
1416
1415
1431
1448
1526

1491
1502
1562

19

1931

F

1909
1931

89633300 F

SERIES.
AB107-

FCO/ECO
.(CK)

A04
A05
A06
A07
A08
A09
Al0
All
A12
A13
A14
A15
A16
A17
A18
A19

0263
0677
0705
0736
0840
1063
1011
0992
1241
1109
1273
1416
1415
1431
1448
1526

SERIES
AB107COl
SIN 1501
CO2
SIN 1573
C03
SIN 1801
C01.-C03
AB107001
SIN 2001
001
SIN 2001

1491
1502
1562
1931
1909
1931

EQUIPMENTS
FCO/ECO
SERIES
AB108(CK)
A04
A05
A06
A07
A08
A09
A10
All
A12
Al3
A14
A15
A16
A17
A18
A19
SERIES
. AB108COl
SIN 1601
CO2
SIN C03
SIN 1632
COl-C03
AB108001
SIN 1701
001
SIN 1701

SERIES
BTl 48-

0668

A04

0677
1063

A05
A06

0906
1415

A07
A08

1415

A08

1491
1842

1909

SERIES
BTl 48COl
SIN 401
CG3
SIN 501

BT148-

om

SIN 601

CPU
TYPE
IDENT
IFIER
A

CPU
TYPE
IDENTIFIER
C

CPU
TYPE
IOENTIFIER
0

;iii

MANUAL TO EQUIPMENT LE VEL CORRELATION SHEET
'H&ET .. 2 .. Of .. 2...
~_L

REV

SERIES
F'C~~O . BA201-A

02

0652
0673

.A03
A04

EQUIPMENTS
FCO/ECO ; SERIES
(CK)
BA201-B FC~f~~O

.0457
0673

A03
A04

0705

SERIES
BU120-A
A03

CPU

03

0939

A04

TYPE
IDENTIFIERS

.04

0992

A05

A, C, D

1241

A06

1272

A07

1588

A08

A
C

0978

A05

I

D,E
F

0978

A05

SERIES
02,03
·04

GD6l1-~

0245

A02

~,B

~,D

E,F

89633300 F

PREFACE
This manual provides customer engineering information for the CONTROL DATA R
AB107 and AB108 with memory and supporting equipment. The AB107 and AB108
computers are physically compact and are designed for high computation and
input output speeds. They feature a semiconductor memory with a basic size
of 4096 (4K) l8-bit words which is field expandable in 4K word increments to
65K words.
NOTE:

Equipments identified without type identifier A,C,D refer to all three.

The following Control Data publications may be useful when installing and
maintaining this equipment.
Control Data Publication
1784 Computer System Reference Manual
1784 Key to logic Symbols
System Maintenance Monitor Manual (SMM17)
AB107/AB108 Execution Charts
1784 Computer Input-Output Specification Manual
CDC Mini-Computer System Site Preparation Manual, section 2

Pub. No.
89633400
89723700
60182000
89723800
89673100
60437000

1784 Computer System Peripheral Equipment Hardware Maintenance
Manuals: (HR/M means combined Hardware Reference/Maintenance Manual)
I
AF108 Paper Tape Reader/Punch Controller
HR/M 89865200
AT310 TTL A/Q DSA Bus Expander
89758600
HR/M 89600054
DJ815 Asynchronous Communications Controller
FA442 tCl Magnetic Tape Transport Controller
89637700
FA446 lCTT Magnetic Tape Transport Controller
89637700
FA716 Cartridge Disk Drive Controller
89638100
FC106 Key Entry Station Controller
89672200
GN109 Key Entry Distribution Unit
89672200
FEl19 Card Reader Controller
HR/M 89637500
FE203 Card Punch Controller
89910800
FF524 line Printer Controller
89637300
FJ505 Binary Synchronous Communication Controller
89934100
FJ606 Synchronous Communications Controller
89638500
(Continued on next page)
89633300 F

v

I

PREFACE (Continued)

Control Data Publication
Fv497 ICL Phase Encoding Formatter
FV618 LCTT Phase Encoding Formatter

I

vi

Pub. No.
89796100
89796100

896333000 F

The following list includes the documents associated with the cQnversational
display terminal:
Title
713-10
713-10
713-10
713-10

Publ ication No.

Operator1s Guide
Reference Manual
On-Site Maintenance Manual
Installation Instruction

62037900
62033400
62048500
62048700

Following is a 1 ist of documents relating to the non-impact printer
station:
Title
713-11
713-11
713-11
713-11

Pul icat ion No.

Operator's Guide
Reference Manual
Installation Instructions
On-Site Maintenance Manual

62149600
62149700
62149800
62149900

Other Publications
For 33 ASR/KSR teletypewriters:

I

Teletype Bulletin 310B, Volume
Teletype Bulletin 310B, Volume 2
Teletype Bulletin 1184B, Parts Schematic package WOP0316 includes
document Nos. 118050, 9334wo, 9335WO, 9336WD, 4970WO, 7887WD,
181821, 183079, 183087.
For 35 ASK/KSR teletypewriters:

I

Teletype Bulletin
Teletype Bulletin
Teletype Bulletin

89633300 F

281B, volume
281a, Volume 2
1201B, Parts Schematic Package.

vii

CON TEN T S
SECTION
1.

2.

Page
GENERAL DESCRIPTION
Introduction
Physical Characteristics

1-1
1-4

En v i ron men t
System Power

1-5
1-5

OPERATION AND PROGRAMMING
Programming
Ope rat i on
Swi tch i ng On
Initial Conditions and Operation
Battery Operation

I

3.

INSTALLATION AND CHECKOUT
Introduction
Uncrating
Inspection and Preparation
Mechanical Inspection
Electrical Inspection and Preparation

vii i

2-1
2-1
2-1
2-4
2-5

3-1
3-1
3-2
3-2
3-5

Installation
Initial Operation
Installation/Removal of the Battery
Installation of the Battery

3-14
3-14
3-19
3-19

Removal of the Battery
Procedure to Install External Shielded Cable Assemblies

3-21
3-22

Teletypewriter (TTY)
Models 33 ASR/KSR
~odels 35 ASR/KSR
35 ASR/KSR I/O Cable Connections
Conversational Display Terminals (COT)

3-24
3-24
3-25
3-25
3-27

89633300 F

CONTENTS (continued)

SECTION

4.

THEORY OF OPERATION
Introduction
Basic Computer
The Central Processing Unit (CPU)
Data Path
Main Registers
Control and Timing Section
Memory Sys tern
Introduction
Memory Control System
Principles of The Dynamic Semiconductor Memory Chip
Detailed Operation of The Memory Unit
Refresh Time
Chip Select
Power Supply Levels
Input Clock Ampl itudes
System Considerations
Memory Module
The Memory Module Block Diagram
Auxiliary Circuit Functions
Low Power Data Retention (LPDR) Mode
Power Back-Up
Programmer's Console
Input/Output
The Teletypewriter (TTY) Controller
Direct Storage Access (DSA)
A/Q Channel
Interrupts
Power Supply
Electrical
Mechanical
General Description and Block Diagram

89633300

Page

D

4-1
4-1
4-4
4-4
4-4
4-8
4-12
4-12
4-12
4-15
4-26
4-29
4-29
4-29
4-30
4-30
4-31
4-32
4-34
4-36
4-36
4-38
4-39
4-40
4-40
4-45
4-51
4-55
4-55
4-57
4-57
ix

CONTENTS (continued)
SECTION

5.

Page
DIAGRAMS
Introduction
Key to Logic Symbols
Signal Flow
Logic Diagram Revision Correlation Sheet
Memory System
Memory Module
Protection Against Catastrophic Failure
Memory Address
Kiloword Selector
Row Selector
Column Selector
Module Selector
Data In
Data In: Parity and Protect Bits
Memory Control
Low Power Data Retention (LPDR)
Memory Control Access Selector
Memory Control Timing
Memory Control Basic Control Signals
Basic Control Signals
Write Control Signals
Memory Control Data Output Lines
Memory Control Bank Address
The Central Processing Unit
Programmer's Console
Register Selectors
Data Bit Selectors
Control Switches and Indicators
Switches and Output Signals
Indicator Lights and Input Signals

x

5-1
5-3
5-3
5-8
5-19
5-21
5-30
5-45
5-49
5-52
5-57
5-60
5-65
5-68
5-81
5-83
5-90
5-99
5-'05
5-107
5-115
5-121
5-429
5-141
5-143
5-147
5'-151
5-155
5-155
5-156

I

89633300

F

I

CONTENTS (continued)
SECTION

5.

Page
DRAWINGS

(Cont'd.)
Arithmetic ~nd Logic Unit (ALU)
Addend Registers and Gates
Augend Registers and Gates
Arithmetic and Logic Operations
Sh i fter
Interrupt Logic
Decoder
Instruction Register and First Level Decoders
Addend Gate Controls
Augend Gate Controls
Controls for ALU and Addressing
Register Clock Controls
Timing
State Equations
Typical Timing Sequences
Oscillator and Phase Generator
Counter
..
Interrupt Timing, Y Register Control Logic
Main Sequence Flip-Flops
Auxiliary Sequence Flip-Flops
Input/Output (I/O) Interface
A/Q Channel Control
Memory Request Logic
Index (i) Address and Write Enable Controls
Decoder for Fl Field
Augend Controls and X Register Clock Control
Controls for Shifter and A/Q Channel Direction
Main Sequence Flip-Flop Controls
Overflow Logic
Enable-Interrupt Logic

89633300 0

5-168
5-178
5-182
5-190
5-193
5-202
5-211
5-215
5-220
5-225
5-228
5-232
5-241
5-242
5-245
5-249
5-258
5-265
5-270
5-277
5-291
5-294
5-299
5-302
5-307
5-310
5-314
5-318
5-322
5-327

CONTE NTS (con t i nue d)
SECTION

5.
(Cont I d)

Page
DRAWINGS
Conso 1e In te rface
Start/Stop Sequence Flip-Flops
Program Protect Logic
Test Mode and Autorestart
ALU Logi c
Enter Interrupt Logic
Skip Logic
Teletypewriter (TTY) Controller PWA 89967400
A/Q Channel Data Path
Controller/Teletype Interface
Oscillator- Baud Rate Selector
Address Decoding- Reply/Reject Logic
Control and Interrupt Logic
Breakpoint Logic
Teletypewriter (TTY) Controller PWA 89947600
A/Q Channel Data Path
Controller/Teletype Interface
Oscillator· Baud Rate Selector
Address Decoding- Reply/Reject Logic
Control and Interrupt Logic
Teletypewriter (TTY) Controller PWA 89984700
A/Q Channel Data Path
Oscillator- Baud Rate Selector
Breakpoint Logic
Teletypewriter (TTY) Controller PWA 89976400
Oscillator- Baud Rate Selector
Enclosure Power. Input
The Power Input Circuit
Power Supply Unit
Power Supply Wiring Diagrams
High Power (HP) and Control Assembly
Low Power Circuit Assembly

89633300

xi i

"

5-337
5-339
5-345
5-352
5-357
5-364
5-369
5-374
5-374
5-379
5-382
5-386
5-390
5-396
5-402
5-404
5-405
5-406
5-407
5-408
5-410
5-412
5-413
5-414
5-416
5-418
5-421
5- 422
5- 423
5-426
5-437
5-446

"

F

1.

CONTENTS (continued)
Page

SECTION

6.

MAINTENANCE
Tools and Special Equipment
Calibrate Power Supply Levels
Check Battery
Inspection or Replacement of Printed Wiring Board
Inspection or Replacement of the Power Supply Unit
Check Programmer's Console Controls and Indicators
Inspection or Replacement of Programmer's Console and

6-1
6-3
6-5
6-7
6-9
6-12
6-15

I

Components On It
Inspection or Replacement of Cooling Blowers
Power On: Procedure For Switching On Power
Power Off; Procedure For Switching Off Power
Emergency Shut-Down
Regular Shut-Down
Diagnostics and Margin Tests

7.

6-22
6-26
6-27
6-27
6-27
6-28

MAINTENANCE AIDS
TTL Ci rcu i t Ope r.a t ion
MOS Circuit Operation
The MOS Process and Silicon Gate Technology
Precautions in Handling the Memory Modules
Protection Against Catastrophic Damage

7-1
7-3
7-3
7-9
7-9

8.

PARTS DATA

8-1

9.

WIRE LISTS

9-1

89633300 F

xii i

I

LIS T 0 F TAB L E ~
Section

Table

Page

1-1

Equipment Description

1-1

4-1

Basic Computer Functional Units

4-2

4-2

Basic Timing Specifications of the Memory Units

4-25

4-3

DSA Channel Pin Assignments

4-41

4-4

A/Q Channel Pin Assignments

4-48

4-5

Interrupt Access Pin Assignments

4-52

4-6

Sunvnary of Regulated Power Supply Circuits

4- 63

1

4-63

6

6-1

Power Supply Levels and Tolerances

6-41

9

9-la

TTY Internal Cable PIN 89684200

9-2

9-lb

TTY External Shielded Cable PIN 89642300

9-2

9-2

Memory Expansion BU120-A08 External Cable Assembly 9-3
(pl) AWG 28 PIN 89658101 (3 sheets)

9-3

Memory Expansion BU120-A08 External Cable Assembly
(P2) AWG 28 PIN 89658501 (3 sheets)

xiv

9-6

9-4(a) AB107/AB108 Backplane Wiring-Signal Name Order

9-9

9-4(b) AB107/AB108 Backplane Wiring Card Slot Order

9-51

9-5

BT148 Backplane Wire List

9-138

9-6

COT External Cable Assembly Wire List

9-147

89633300F

LIST OF FIGURES
FIGURE

Page

2-1
2-2

AC Power Switch and Connection
Computer Front View

2-3
2-7

3-1
3-2
3-3
1-4
3-5
3-6
3-7
3-8
3-9
3-10

Card Placement Slot Assignment: Main Computer Enclosure
Card Placement Slot Assignment: Expansion Enclosure
Power Supply Heat Shield and Retaining Screws
Inside of Main Enclosure Front Door
Power Supply Connector Panel
AC Power Switch and Connection
Rear of Enclosures
General View and Dimensions of Main Enclosure: Type Ident. A
External Dimensions of Main Enclosure: Type Identifiers A,C,D
Rear Cover Wi th Battery
Installation Kit Part No. 89986600 For External Shielded Cable

3-3
3-4
3-6
3-8
3-8
3-9
3-12
3-15
3-16
3-20 \
3-23

Computer System Simplified Block Diagram
CPU Block Diagram
Memory Address System and Data Flow
The Memo ry Ce 11
Memory Unit (a) Block Diagram and External Connections
(b) Detailed Block Diagram
(c) Circuit Details
(d) Ci rcuit Detai ls
Memory Timing (a) CPU and DSA Cycles
(b) Refresh Cycles
Memory Module Block Diagram
DSA Channel Timing
A/Q Channel Timing
A/Q Channel Input/Output Lines
Power Supply: Simplified Block Diagram
AC-to-DC Converter and Protection Circuits: Block Diagram
Power Supply Regulator and Control Circuits: Block Diagram
Switching Regulator: Basic Circuit and Waveforms

4-3
4-5

3-11

4-1
4-2
4-3
4-4
4-5

4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14

89633300 F

I
\

4·13

4-17
4-19
4-20
4-21
4-22
4-23
4-24
4-33
4-42
4-49
4-50
4-58
4-60
·4-64
4-66

xv

LIST OF FIGURES (continued)
Page

FI GURE

6-1
6-2
6-3

6-4
6-5
6-6a.
6-6b.

6-7
6-8

7-1
7-2
7-3
7-4
7-5
7-6
7-7

xvi

Computer Backplane Showing the Power Supply Test Points
Use of Board Extractor and Board Extender
Power Supply Heat Shield and Retaining Screws
Power Supply Adjustments and Fuses
Power Supply Terminals and Retaining Screws
Inside of Computer Enclosure Front Door
Inside of Computer Enclosure Front Door
Blower Assembly in Top of Enclosure (All type identifiers)
Exposed View of Two Lower Fans and Electrical Connections

6-6
6-8
6-8
6-11
6-11
6-19
6-20
6-21
6-25

Diode AND Gates
TTL AND Gates
Typical Logic Level Margins for TTL Micrologic
Typical MOS Characteristic
MOS Inverter Circuits

7-2
7-2

MOS Inverter With Output Booster
MOS Transmission Gate

T-2

7-6
7-6
7-7
7-7

89633300 F

LIST OF FIGURES (continued)
Figure

Page

6-1

Computer Back Plane Showing the Power Supply Test Points

6-6

6-2

Use of Extractor Tool and Extension Board

6-8

6-3

Location of Power Supply Unit and Heat Shield

6-8

6-4

Power Supply Unit:

6-11

6-5

Power Supply Terminals and Retaining Screws

6-12

6-6a.

Inside of Computer Enclosure Front Door

6-19

6-6b.

Inside of Computer Enclosure Front Door

6-26

6-7

Blower Assembly

6-21

7-1

Diode AND Gates

7-2

7-2

TTL AND Gates

7-2

7-3

Typical Logic Level Margins for TTL Micrologic

7-2

7-4

Typical MOS Characteristic

7-6

7-5

MOS I nverte"r Ci rcu i ts

7-6

7-6

MOS Inverter with Output Booster

7-7

7-7

MOS Transmission Gate

7-7

89633300E·

Location of Adjustment and Fuses

xvi i Ixvi it

I

SECTION 1
GENERAL DESCRIPTION

GENERAL DESCRIPTION
INTRODUCTION
The CONTROL

DATA~AB107

and AB108 computers are small, stored program parallel

mode digital computers with semiconductor memory of a basic 4096 (4K) 18-bit
words, field expandable to 65K words in 4K word increments.

The main computer

enclosrues houses the first 32K words (32,768) memory bank, the second bank
(memory expansion) being accommodated in the BT148 Expansion Enclosure.

The

main computer and the expansion enclosures also house the peripheral controllers.
The following table 1 ists the equipment which make up the ABI07 and AB108
computers.

Equipment described in this manual (see preface for CE Manuals

of associated equipments).
TABLE 1-1.

EQUIPMENT DESCRIPTION
Descri pt ion

Equipment Number
ABI07-A

The central processing unit performs the following functions:
a.

Arithmetic and logical operations required by the stored
program.

b.

Control operations to execute and synchronize operations
within the central processor, in the memory and for
input/output.

c.

Interrupt processing for one internal and fifteen external
priority interrupts.

d.

Program protection to protect one set of programs in the
memory from the effect of other programs.

The equipment combines with ·up to eight BA201-B Memory Modules
housed in the computer enclosure to provide a bank of
32,768 (32K) words of semiconductor memory storage with a
cycle time of 900 nanoseconds.

89633300

A

1-1

EQUIPMENT DESCRIPTION (cont'd)
ABI07-A (cont'd)

The memory may be expen

a

a

~
1=

a

a

a

II
r•"':.

1=
~

.....

(-

iii

I

I

Figure 2-2.

89633300

A

a

;.

-'-,
EJ ... II

El

·m

i.

"

-

~

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iii

[±]
[±]

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a

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a

a

a

a

a

a

a

a

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a

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0 Oi 0 · 0
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0 ·0

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Oi_

Computer Front View.
(Programmer's Console, Controls and Indicators).
2-7

SECTION 3
INSTALLATION AND CHECKOUT

INSTALLATION AND CHECKOUT

INTRODUCTION
This section provides installation procedures for the AB107/AB108 computers.
To install peripheral equipments refer to the appropriate Customer Engineering
or Installation manual$.

Refer also to Control Data Mini Computer Systems,

Site Preparation Manual, publ ication No. 60437000.

UNCRATING
INSPECTION
The equipment is packed in cartons with adequate packing material in the carton
to isolate it from shocks in transit.
must be made before uncrating.

A pre! iminary inspection of the carton

Evidence of damage must be noted and reported

immediately (refer to Field Procedures Guide).

UNPACKING
To unpack the equipment lay each carton in turn on a clean smooth flat surface.
Cut the sealing tape of the carton, open out the flaps,

re~ove

the packing

material on top and sides of the equipment and 1 ift out the equipment onto the
clean surface beside the carton.

Check the contents of each carton against

packing (consignment) list and inspect each item for transit damage (dents,
scratches, signs of breakage).

Note and report damaged or missing parts

(refer to Field Procedures Guide).

CRATING INFORMATION
Consult Control Data procedure 8.504.00 in the Customer Engineering Field
Procedures Guide.

89633300

A

3-1

INSPECTION AND PREPARATION
Inspect the main computer enclosure and the expansion enclosure BT148
(if ordered) as follows:
a.

Mechanical inspection

*

Inspect the enclosure for superficial damage, loose cables and screws

*

Open the enclosure

*

Check the Identification Plates on the right hand side of the enclosure
(inside the door).
Make sure that the equipment supplied corresponds
to the Customer's order

*

Check that all the printed wiring assemblies corresponding to the
equipments shown on the Identification Plates are inserted in their
proper s lots (see Fi gures 3-1, 3-2)
I f necessary insert them and
stick the corresponding Identification Plate on the right side of
the enclosure interior.

*

Check that the computer enclosure corresponds to the Memory Modules
supplied:

I

Enclosure
main
expansion

I

3-2

AB107
AB108

BT148
BT148

Computer Cycle Time

900 nsec
600 nsec

Memory Module

BA20l-B
BA20l-A

*

Check that each printed wiring assembly is properly seated

*

Note serial number and part number of equipments supplied
for future reference.
This information is written on the
Identification Plates.

89633300 F

00
\.0
0"

DECODER

\.II,)
\.II,)
\.II,)

o

m

o

/O

."

MEMORY CONTROL
MEMORY ADDRESS

IIIIIII
EIGHT
MEMORY
MODULES

AQ BUS

TIMING

LEAST SIGNIFICANT

rL\

INTERFACE

. CONSOLE INTERFACE

I

I

IIII II I III II I I I
CENTRAL
PROCESSING
UNIT

CARTRIDGE
DISK
DRIVE
CONTROLLER

PHASE
NRZI
MAGNETIC
ENCODING
TAPE
TRANSPORT FORMAT-,
TER
CONTROLLER

:. en en 0 0 c:
% I'i'I en :.
6
:;; 0 :. en
~
I'i'I
.....
-< ::u ::u
I'i'I

.......

"

::u

i

J "
0

%

.....

:.
"V
I'i'I

0

0

ID

0

a
0

Z :.

y

-

I

~ i.....
:.

.....

36 35 34 33 32 31 30 29 2B 27 26 25 24 23 22 21 20 19 IB 17 16 15 14 13 12 II 10 9

-

AQ BUS

11 1''17

TTY CONTROLLER

i

DSA BUS

::u

r-

B

7

6

5 4

3

2

I

,

PWA's part of equipment
AB107/AB108
NOTES
11. The Memory Control board and-the Memory Address board together form the Memory Controller.
This is similar to equipment BUI20-A in the Expansion Enclosure.
2. Memory modules must be installed sequentially from slot 29. For instance, if equipment contains
16K, four modules are installed in slots 29 through 32.
~

3. See section 1 for definition of equipments.

\.II,)

-

Figure 3-1. Card Placement Slot"'Assignment: Main Computer Enclosure

........

W
I

DSA BUS

01:"

MEMORY CONTROLLER

J,
I
EIGHT
MEMORY
MODULES

A/Q BUS

DSA BUS

I

~
I I I""
'11 I'

~BUS

I

r,-, ... - "

BUS

DSA BUS

A/Q BUa

I'ln

II I

OPEN

/Q

DSA BUS

I

I
OPEN

OPEN

I
I
I
I

38

301 34 33 32 31

JO 29 28 27 28 28 24 23 22 21 20 19 18 17 18 15 14 13 12

"

10 9 8 7 8 8 4 3 2

I

NOTES
1. The Memory Control board and the Memory Address board together form the Memory Expansion Controller, equipment number BUI20-A.
~

2. Memory modules must be installed sequentially from slot 29. For instance, if equipment contains
16K, four modules are installed in slots 29 through 32.

~

~

3. See section 1 for definition of equipments.

o
o
~

Figure 3-2. Card Placement Slot Assignment: Expansion Enclosure

b.

Electrical inspection and preparation

*

Check the ac line voltage available

*

The equipment can accommodate one of the following nominal line
voltages:

Note:

*

either

110 vac,

50-60 Hz, single phase

or

220 vac,

50-60 Hz, single phase

the exact specifications are given in Section 1.

Check the enclosure Identification Plate for the line voltage of the
enclosure.
If this coincides with the one available, skip the next
paragraph and proceed to the one after; if the enclosure line voltage
is not the same as that available, proceed with the modification as
described in the next paragraph.

*

To modify the enclosure (main or expansion) to allow it to accommodate
a line voltage (110 vac or 220 vac nominal) other than it is connected
for, proceed as follows:
make sure that the enclosure is not connected to line voltage
remove the power supply heat shield by removing its retaining
screws on the inside of the enclosure front co~er (refer to
Fi gure 3-3).

89633300 f

3-5

I

r--

.........)~

II~

.-"

"

•

•

•

•

•

•

-

•

~

POWER .....V HEATJHELD

I

Figure 3-3.

3-6

Power Supply Heat Shield and Retaining Screws

89633300

F

connect the shorting links on TB2 of the power supply connection panel
according to the supply voltage available. See figures 3-4 and 3-5.
NOTE:

The view in figure 3-4 is exact for series A12 and down. Three areas,
marked PC, PS, MH in figure 3-4, were physically altered in series
A13 and up, including type identifiers C and D.

PC: The soldered connections of the programmer's console cable to
the programmer1s. console card were replaced by two horizontal
connectors, which are mounted in the same area and are marked
J20 and J21 on the nearby enclosure wall.
This change affects the procedure for removing the console card.
PS: The three soldered connections to the power supply were replaced
by a single vertical connector.
This change affects the procedure for removing the console card.
MH: The route of the main harness to the backplane under the cardfile
was shifted away from the enclosure wall towards the center.
This change does not affect the procedure for removing the card.

I

T821 1 21 31 41 51 61 71 81 91 10 1
110V

t....t J t t

tIt

t....t

SHORTING LINKS FOR 110VAC INPUT

NOMINAL INPUT
VOLTAGE
110 vac

SHORTING LINKS FOR 220VAC INPUT

St'iORTING LINKS
ON T82 TERMINALS
1-2, 3-4-5, 6-7-8,

INPUT TO
TERMI NALS

3, 7

9-10
220 vac

89633300

F

2-3,

5-6,

8-9

3, 7

3-7

I

Figure 3-4. Inside of Main Enclosure Front Door
_ (Not ~pp 1i cab le to a 11'.=eriesi. See ..!'ote ~ pag!,. 3-7. L

GND

(

o

\

(

(

I

Figure 3-5.

3-8

Power Supply Connector

Panel

89633300

F

*

As a further check inspect the power supply connections as follows:
make sure that the enclosure is not connected to line voltage
remove the power supply heat shield by removing its retaining screws
on the inside of the enclosure front cover (unless already removed).
Refer to figure 3-3 and to figure 3-4.
inspect the shorting links on TB2 of the power supply connection
panel and make sure that they are in their correct position. Refer
to figures 3-4 and 3-5.

*

Check fuses:
Fuse
des i gnat ion

Fl

Function

Current

ac power

8 A for 110 vac
4 A for 220 vac

Speed
(b low)

-

Location

Location
refer to

Figure 3-6
Input
unit

F2

battery

1 A

slow

F3
F4

dc power

5 A

fast

dc aux

100 rnA

slow

Figure 3-6.

89633300 F

}

Power

Figure

3-3

Supply

AC Power Switch and Connection

3-9

*

If the system includes the memory back up power source, battery
equipment GD611-A, check:
proper installation of the equipment in each enclosure
(refer to installation procedure)
voltage at the battery terminals (nominal 28 vdc;

for exact

specification refer to Section 1)
If the battery has to be

changed refer to battery installation

information at the end of this section.

*

Check for electrical short circuit between conductors on the equipment
power supply cable connector, also between each conductor and logic ground
(do not forget the third conductor).
Use highest resistance scale
on the multimeter and make sure that the AC POWER switch at the top

I

of the equipment rear panel is OFF (Figures 3-6 and 3-7).

*

Check all connections for tightness.

*

Reinstall the power supply heatshield by replacing its retaining
screws (refer to Figures 3-3 and 3-4).

*

If the system includes a BT148 Expansion Enclosure, check that the
equipments match by checking the identification plates on the
enclosure, on the two assemblies of the Memory Expansion Controller
and on each of the memory modules (refer to the table on page 3-13).
Make sure that the main computer and the expansion unit match.

3-10

89633300 F

12.

If the system includes memory expansion (equ,ipmentsBU120 and BA201-A or
BA201-B) in the BT148 Expansion Enclosure and therefore has more than
32K words memory, carry out the following:
Install the expansion
Switch off the dc POWER on both enclosures.
enclosure cables (refer to Figure 3-7).
Switch on the dc POWER on
both enclosures.

I

12.1

Press STOP switch on main computer.

12.2

Make sure that the main computer and expansion equipment have
the same memory cycle time (see page 3-13).

12.3

I

Perform steps 1 and 2 above for the enclosure.
NOTE
All control switches (except the dc POWER ON
swi tch of the Expans ion Enclosure) are . located
on the main computer front panel.

89633300

12.4

Press MASTER CLEAR switch.

12.5

Set Mode switch (32K/65K) to 65K.

12.6

Set ENTER/SWEEP switch to ENTER.

12.7

Set INSTRUCTION/CYCLE switch to its central (COMPUTE) position.

12.8

Set PARITY FAULT STOP switch to its central (off) position.

12.9

Set SELECTIVE STOP and SELECTIVE SKIP switches to their down
{off} positions.

12.10

If the full complement of eight memory modules is installed in
the expansion enclosure: set P register to FFFF I6 •

12.11

Press the GO pushbutton.

12.12

Press MASTER CLEAR pushbutton.

12.13

Perform steps

F

12.~,

12.5, 12.6 above.

I
3-11

\oN
I

N

@=

COMPUTER ENCLOSURE

Part
Cab) e I Number

3
4

89658)00
89658)00
89658500
89658500

5

89802800

2
00

\.D

0'

\oN
\oN
\oN

0
0

."

-------

EXPANSION
ENCLOSURE

Connections
Computer
33P)
3)P)
33P2
3)P2
23P)A07
23P) BJJ (GND)

Expansion
3)P)
33P)
3lP2
33P2
27P2A23
27P2B21 (GND)

Figure 3-7.

Rear of Enclosures

Equipment Number
Memory Cycle
nsec

I

900
600

E x p a n s ion
Me m 0 r y
Enclosure
Controller
Memory Module
BT148
BT148

BU120-A
BU120-A

Note power supply requirements:

BA201-B
BA201-A

Initial Operation paragraph 4

Insert the Memory Expansion Controller assembl ies (2) and the
memory module assembl ies in the slots of the expansion assigned
to them and make sure that they are well seated. (Figure 3-2.)
Connect the five cables of the Memory Expansion Controller (refer
to Figure 3-7 and Section 9). Note that the Memory Expansion
Controller (slots 27,28) are wired to slots 31 and 33 through
the back plane.
The flat cables plug into slots 31,33.

*

I

Connect on each enclosure a length of insulated wire of adequate
crossection to the enclosure ground and one to the Jogic ground

I

lug (refer to Figure 3-7); make sure the wire is long enough to
connect the computer (or expansion enclosure) to the nearest
logic ground outlet in the installation.
Adequate crossection for this ground-wire is considered to be

89633300 F

110 vac line voltage:

AWG 12

220 vac line voltage:

AWG 16

3-13

INSTALLATION
Ensure that there is no obstruction to free air circulation around either
enclosure and that there is enough room to insert connectors and open the
rear cover. See fi gures 3-8,3-9
for the necessary cl earance d imens ions
around the enclosure.

.

I

Ensure that the equipment "is properly grounded by performing the following
for each enclosure:

*

check that the third pin (ground) of the power cord (chassis ground)
connects to a good ground

*

connect the logic ground of each enclosure to the system logic ground
(refer to Figure 3-7 and the paragraphs on preparation of the equipment)

*

I

connect the chassis ground to the system ground.

Refer to the Mini Computer Site Preparation Manual, CDC publication
number 60437000.
Hook up the power by plugging the equipment line cord to the enclosure rear
'panel (Jl:

I

Figures 3-6 and 3-7) and then to the utf1 tty outlet.
,

INITIAL OPERATION
The equipment has been fully tested in the factory before despatch.
The
following procedure checks the equipment on first installation on site and
prepares it for operation.
It is assumed that it has been checked as
detailed in the previous paragraphs and any discrepancies corrected.
The computer main enclosure is set up first; only when that is prepared is
the expansion enclosure prepared, ifit is part of the installation.

3-14

89633300 F

~I"l
,//,,\\\

00
\.0

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! \.'\\\\

.

VJ
VJ
VJ

\

.

o
o

\.

,.

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.

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\\ \ '

\
"
~~

"

\

,

...

..

/'

--.;:eo;;;
/'

-

.-,,,,'

/

\

.!!:!!!l
I

"",-

~ .. .....~--

I
.....

-

. . . . . . . .- - t

1 - - - ' -~
......

&110

jlt==i
,..,..

==:J

1IIIiiiI

,

I

--

E:~fmM

AIR

RI_I

1
/ / ....f..L
!,I --

!

W--,

....

-.~

iH\,;;I I ' ! [ II

o

-~

'trf1L1ff
'ffi±

T~ii~--r'I~

1
1------

1

.

i

Of,·

\\\

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JQIU!I!.

,,'\.._--

~..!.TTYLL-_ _

\

1.712

VJ
I

~

---I
POIIIXlUIIAL CAa&

Figure 3-8. General View and Dimensions of Main Enclosure: Type Identifier A

\

---

~
j-_______ _ f.

I

AIR INLETS
-44-

..

1------,-I

------t

u

C!I'tI!IML - -

Type
Identifier
A

IS.750

ABI07-A
ABI08-A
BTl 48-A

.e

Type Identifier C
Type Identifier 0
AS 107-C

AB 108-c
B.1148-c
ABI07-0
ABI08-0
B1148-0

\U40;
TC) FAN:

* Type

identifiers C
and 0 have two fans
installed in the
base of the enclosure.

Ifigure 3-9. External Dimensions of Main Enclosure: Type Identifiers A,C,O
3-16

89633300 F

INITIAL OPERATION - Continued
The Programmer's Console (front panel) controls used in the following are
described in Section 6 of the 1784 Computer System Reference Manual,
publication number 89633400.
manual.
1.

The console is shown in figure 2-2 of this

Open the front cover of the enclosure and pullout all the printed
wiring assemblies from their connectors but leave them in their slots.

2.

Turn On the AC POWER switch at the top of the rear panel (see figures

I

3-6 and 3-7). Examine the enclosure to See that all blowers work.
NOTE: The number of blowers is four or six, depending on the
type identifier. Refer to Maintenance Section 6.
If there is no airflow, or some other fault is detected, switch off
the equipment immediately using the emergency shut-down procedure on
page 6-3. Location of the air inlets and outlets is shown in figures

I

3-8 and 3-9.
3.

Turn on the DC POWER switch on the operator's console (enclosure front
panel - refer to figure 2-2). The indicator above the switch should
light.
WARNING
If the indicator does not light, or if any
other fault is suspected, the equipment
must be switched off immediately by turning off the AC POWER switch at the top of
the rear panel. See page 6-3 for the emergency shut-down procedure.

4.

Check the power supply voltages (see section 6). Check that the value
of VSS is correct for the memory modules installed:

BA20~-A

or BA20l-B.

I

See table 6-1 for power supply voltages.

5.

Switch off the DC POWER switch on the Operator's Console and re-insert
the printed wiring assemblies. Make sure that they are well-seated.

6.

Repeat step 3 in this procedure.

89633300 F

3-17

INITIAL OPERATION - Continued

7.

I

If the Expansion Enclosure,equipment BT148, is part of the installation,
repeat steps 1 through 6 for it.

Set up initial conditions by the following procedure:
8.

9.

The installation has up to 32K word memory:
8.1

Press MASTER CLEAR pushbutton.

8.2

Set Mode switch (65K/32K) to 32K.

8.3

Set ENTER/SWEEP switch to ENTER.

8.4

Set INSTRUCTION/CYCLE switch to its central (COMPUTE) position.

8.5

Set PARITY FAULT STOP switch to its central (off) position.

8.6

Set SELECTIVE STOP and SELECTIVE SKIP switches to their down (off)
positions.

8.7

Press the GO pushbutton.

8.8

Press MASTER CLEAR pushbutton.

Note that this check
Check all registers by entering data in each one.
also serves as a lamp test for the indicators associated with the registers
and the data input keys.

10.

Enter a pattern into memory and correct any problems.

11.

Sweep the memory to check for parity error.
NOTE
In steps 8 and ~ refer also to
1784 Computer System Reference
Manual, publication 89633400.

3-18

89633300 F

INSTALLATION/REMOVAL OF THE BATTERY (Figure 3-10)
The optional power back-up source, rechargeable battery equipment G0611-A
is normally packed separately.
cover of the enclosure.

In operation,the battery is housed in the rear

To install the battery follow the outline procedure

given below.
Installation of the battery
1.

I

If the battery is new, install the battery, starting from step 4.
If the battery is not new, or if there is some doubt about its state of
charge, go on to the next step.

2.

Check the open circuit voltage of the battery.

2.1 Connect a voltmeter/multimeter of 20,000 ohms per volt or more across
the terminals of the battery.
2.2 Measure the open-circuit voltage to be 24.2 vdc or more.
2.3 If not, replace the battery by a fully-tested one.
I f yes, go on to the next step.
3.

Check the full load voltage of the battery.

3.1 Connect two 60 ohm, 5%,10 Watt resistors in parallel across the
terminals.
3.2 Connect the voltmeter.
3.3 Measure the full load voltage to be 24.2 vdc or more.
3.4 If not, replace the battery by a fully-tested one.
If yes, disconnect the multimeter and resistors and install the
battery, starting from step 4.

89633300 F

3-19

------,
___ -----tI

Figure 3-10.

3-20

Rear Cover With Battery

89633300 F

I

4. Remove rear cover of the enclosure by undoing the two th~mb-screws at
the top of the rear cover, tilting the cover back and sl iding it out
of its slots.

I

5. Fix the battery to the rear cover (Figure 3-10)using the four screws
and corresponding nuts and washers provided.
6. Install the battery cable provided as follows:
6.1

connect the cable shoes under the nuts on the battery terminals, the
red lead to the positive (+) terminal

6.2

slide the rear cover (with the battery fixed to it) into its slots
and support it by hand

6.3

connect the other end of the cable to connector JO on the enclosure,
inserting the red lead to the lower pin of the connector

6.4

close the rear cover onto the enclosure and tighten the two
thumbscrews

7. Check the battery fuse (refer to Figure 3-6).
If the equipment is newly installed or has not been used with a battery before
perform also the following steps:
8. Load the memory with a pattern and check the pattern under normal
operating conditions.

Record the pattern.

9. Turn off the equipment power supply (Power Off Procedure, section 6)
10. After a few minutes turn on the power again (Power On Procedure, Section 6)
and check that the pattern in the memory has been retained.
If the pattern has. been retained, proceed with normal operation.

If the

pattern has not been retained recheck the battery (see step 1 above).

If

battery is in order proceed to memory diagnostics.

Removal of the battery

89633300 F

Do steps 6, 5, 4,

in that order.

3-21

PROCEDURE TO INSTALL EXTERNAL SH I ELDED CABLE ASSEMBLI ES (Fi gure 3-11)
The ground screw to which

the~\external

shielded cable is to be attached may

or may not have a cable already attached to it.
Ground Screw Without Cable Attached
1. On the interior surface of the rear connector panel, scrape off a 0.5 inch
(12.7 mm) diameter circle of paint around each of the three lower holes.
2; Open Installation Kit Part No. 89986600 that contains all the attachment
parts needed.
3. Slide the external tooth lock washer onto the screw.

4. Insert the screw and external tooth lock washer into the hole of the rear
connector pane 1.

5. Mount the spri ng lock washer.
6. Mount the plain washer.

7. Mount one of the two hexagonal nuts.
8. S 1 ide the flat-locking terminal of the cable onto the screw.

I

. \

9. Mount the other hexagonal nut. Secure the cable into place.
Ground Screw With Cable Attached
1. Remove the securing nut and save it.
I

\

2. Slide the flat-locking terminal of the cable onto the screw.
CAUTION
Do not mount more than four external
shielded cables onto the same screw.

(

(

3. Mount again the nut that was removed in step 1.
Secure the cable into place, making sure there is proper electrical
contact with the cables already attached.

3-22

89633300 F

(

NO.8 SPRING LOCK WASHER
NO.8 PLAIN WASHER
NC8-32

HEXAGO~AL

NO.8;XT~RNAL

NUT

INTERIOR
FAC~ OF REAR

FLAT LOCKIN,G
TERMINAL
PART OF EXT. CABLE
Figure 3-ll.lnstallation Kit Part

89633300 F

iOOTH LOCK WASHER

,

CO~ECTOR
No~

PANEL

89986600 For External Shielded Cables
3-23

13.

Te I etypewr iter (TTY)
NOTE:

In the following refer to the Teletype Corportation instruction
manual for the Teletypewriter in the system. Carry out all
procedures and checks listed there. In addition, carry out
I
the procedure outlined below.

*

Inspect the teletypewriter for superficial damage, loose cables and
screws.

*

Check the teletypewriter wiring:

-

I

loop-current must be 20 milliamperes
connect for full-duplex operation
wiring changes as detailed below.

Models 33 ASR/KSR
Modifications to run full duplex with a 20 ma current loop. The changes
are noted on the diagram for the customer interface (TTY 9336WD-B2)
on terminal strip Bl (x). Also, see Note 9 on 9336WD-AI,.
Instructions for conversion:
1.

Hove the purple wire on Bl{X)-8 to Bl{X)-9.

2.

Move the White-Blue Wire on Bl{X)-4 to Bl{X)-5.

3.

Hove the Brown-Yellow wire on Bl{X)-3 to Bl{X)-5.

4.

Ref. d iag ram 9336WD-B I
Hove wire on AC{R-I) tab 3 to R-l tab 4.

Blue wire.

Facing the rear of the unit, the terminal strip Bl is located on the
lower left side near the cable entry.

3-24

89633300 F

I

I

13. Teletypewr'iter (TTY) Continued
R-l is located on the left side midway to the front, a large brown
resistor with 4 tabs.
Models 35 ASR/KSR
This type of TTY does not have the same jack/connector configuration
as the 33 KSR/ASR teletypewriter, so it does not utilize the connector on the TTY external cable assembly. The connector must be cut off
and terminal lugs should be installed on the wires.
Remove the terminal strip cover of the terminal strip located in the
place normally occupied by the I/O connectors. Remove the shorting
brackets from TB 5, 6, 7, and 8, if they exist.
Connect the TTY external cable wires to TB5, 6, 7 and 8.
the terminal strip cover and close the TTY to cover.

Then replace

35 KSR/ASR Teletypewriter I/O Cable Connections

66-PIN CONTINENTAL
CONNECTOR PIN AT
CPU END
Pin 47
Pin 43
Pin 49
Pin 45

*

TB PIN
5
6
7
8

The teletypewriter normally operates from a power line with a
nominal voltage of 110 volts. Check the teletypewriter and the
available line voltage. If they match, hook up the power to the
teletypewriter by plugging the line cord into the utility outlet.

89633300 F

3-25

I

13. Teletypewriter (TTY) Continued
If the power line voltage is 220 volts a transformer will have to be
used. To determine the power rating of the transformer, consult
the teletypewriter instruction manual.,

*

The 33 KSR/ASR TTY's come equipped as either 60 Hz or 50 Hz devices.
Both units require single phase 120 vac.

*

The 35 MSR/ASR teletypewriters are shipped with a 50 Hz mechanical
conversion kit (see Section )0.2). When installed, these TTY's
will accept 50 Hz, 120 vac. Install this kit if applicable. The
kit contains the necessaryinstructions to accomplish the change.

*

It may be necessary to replace the male connector of the TTY
primary power cord to make it compatible with the customer power
source.

*

Check the teletypewriter operation by performing the following:

I

set power switch to lOCAL ON
press a number of characters on the keyboard and check that the
printer prints them correctly.
press liNE FEED and CARRIAGE RETURN elF CR) buttons on the
keyboard.

*

Check the teletypewriter in conjunction with the computer by perforing the following:
switch off the AC POWER switch on the expansion enclosure and
on the computer rear panel.

I

connect the external data cable from the teletypewriter to the
main computer enclosure (refer to figure 3-7); check that the
internal cable (P14 to slot 20) is correctly seated.

3-26

89633300 F

13.

Teletypewriter (TTY)

Cont1d

make sure the baud select on the TTY controller is properly
installed, (Baud rate 110 is selected with Jumper on TTY
Con t ro 11 e r) •
Switch on the AC POWER switch on the computer rear panel and
the DC POWER switch on the Programmer1s Console.
Set teletypewriter power switch on ON LINE
press a character a number of times in succession:
the teletypewriter should print the character twice (and twice
only) showing presence of the TTY Controller board in the comcomputer enclosure.
press the MASTER CLEAR switch on the computer Programmer1s
Console.
press again a character on the keyboard a number of times in
succession:
twice.

the teletypewriter should again print the character

run the applicable diagnostics as detailed in the System
Maintenance Monitor (SMM) for the TTY.

14.

Conversational Display Terminal (COT)

*

Inspect the Conversational Display Terminal for superficial damage,
loose cables and screws.

*

The COT normally operates from a power 1 ine with a nominal voltage
of 110 volts.

Check the COT and the available 1 ine voltage.

If

they match, hook up the power to the teletypewriter by plugging the
line cord into the utility outlet.

If the power 1 ine voltage is

220 volts a transformer will have to be used.

To determine the

power rating of the transformer, consult the COT instruction manual.

89633300 F

3-27

14.

Conversational Display Terminal (COT)

*

Cont'd

The COT can be util ized as a 50 Hz/60 Hz 120 vac device without any
internal changes.

It may be necessary to change the connector on

the primary power cord before connecting it to the customer power
source.

*

Check the COT operation by performing the following:
set power swi tch ·to ON
ensure local switch is in the OFF position.
press a number of characters on the keyboard and check that the
printer prints them correctly.
press clear to see if screen is cleared of all characters.

*

Check the COT in conjunction with the computer by performing the
following:
switch off theAC power switch on the expansion enclosure and
on the computer rear panel.
connect the external data cable from the COT to J14 in the main

I

computer enclosure. Check that the COT/TTY internal cable (P14
to slot 20), is correctly seated.

I

If the Non-Impact Printer (NIP) is part of the system, install
cable assembly PIN 62078801 between the COT and the NIP. The
printer daisy chain output on the NIP must be terminated with
terminator assembly PIN 62078900.
make sure the baud select on the TTY controller board is properly
installed.

Baud rates are 110, 300, 1200, and 9600 only.

Maximum baud rate for NIP Printer is 300.

Use of NIP Printer

at baud rate greater than 110 will require software restrictions
to prevent lost characters after a carriage return.

3-28

89633300 F

14.

Conversational Display Terminal (COT)

Cont'd

Odd or even parity operation of the COT may be required by
specific appl ications.

In that event, changes will have to be

made on the TTY controller board.
To select even parity and seven data bits per character, add a
wire between P2-B22 and U53-7.

To select odd parity and seven

data bits per character, add another wire between P2-B28 and
U52-7.
Install wires, if required, on the component side of the TTY
controller board.
Switch on the AC POWER switch on the computer rear panel and the
DC POWER switch on the Programmer's Console.
set COT switch to ON.
Run the appl icable diagnostics as detailed in the System Maintenance Monitor (SMM) for the TTY.
15.

Install all peripheral controllers according to appropriate
Customer Engineering manual.

Refer to delivery note/equipment

order for list of peripheral controllers and to Figures 3-1,3-2. Make.
sure that the appropriate internal and external cabl~s are connected
(refer to the cable list of the peripheral Customer Engineering
manual). The preface to this manual lists the Customer Engineering

I

manuals of the peripheral controllers.
WARNING

I

Before attempting to insert any
controller make sure that the
enclosure dc POWER switch is off.
16.

Install all interconnecting cables between the main computer enclosure
and the expansion enclosure (if part of system).

89633300

F

3-29 .

I

Conversational Display Terminal (COT) Continued
17.

Make all interrupt connections according to system requirements on the
computer main enclosure back plane using the interrupt cable assembly
number 89724702.

For interrupt pin assignments on the CPU refer to

Table 4-5.
18.

Make all DSA scanner connections according to system requirements.
Refer to AB107/AB108 Computer Input/Output Specification

Manual,

publication number 89673100 as well as the CE manuals for specific

I

controllers.
19.

3-30

Run

The preface to this manual has a complete list.

diagnostics (SMM 17).

89633300 F

SECTION 4
THEORY OF OPERATION

THEORY OF OPERATION
INTRODUCTION
This section presents general and detailed functional descriptions of the
equipment, using aids such as overall and detailed block diagrams and timing
diagrams.

Descriptions are keyed to the detailed logic diagrams in the

Diagram Section (Section 5) and afford a basis to understand the detailed
description of the specific circuit in that section.
NOTE
It is assumed that the reader is familiar with Control Data equipment
and with the programming characteristics of the Computer as described
in the 1784 Computer System, Reference Manual, Publ ication No.89633400.
BASIC COMPUTER
The AB107/AB108 with the memory and other supporting equipment is a stored
program parallel mode digital computer.

The computer word contains 18 bits;

the 16 least significant bits (bits 00 through 15) contain data and instructions,
bit 16 is the parity bit, bit 17 is the program protect bit.
The simplified block diagram of the computer system is given in Figure 4-1.
It shows the principal functional units of the computer with an indication
of their equipment numbers.

The interconnection between the units is shown

both within an equipment and between the main computer enclosure (equipment
AB107
or AB108 ) and the expansion enclosure (BT148 ).
The main computer
equipment houses up to eight memory modules (equipment BA201-A/B).
It also

I

houses the optional Memory Hold Battery (equipment GD611-A) and provides slots
and wiring for peripheral equipment controllers on the A/Q and Direct Storage
Access (DSA) input/output channels.
BT148

The expansion enclosure (equipment

) similarly houses the whole of the memory expansion system and the

Memory Hold Battery and provides slots and wiring for peripheral equipment
controllers on the two input/output channels.
described in Section 1 of this manual;

The equipment is listed and

detailed circuit, logic and inter-

connection diagrams are given in Section 5.

Functional block diagrams are

given in this section.
89633300 F

4-1

I

Most of the circuitry of the computer is accommodated on 50-PAK printed
wiring boards.
The power supply forms a separate component unit within
the computer enclosure.
Table 4-1 lists the units of the basic computer,
their slot allocation within the computer enclosure is shown in Figure 3-1.

TABLE 4-1.

Subsystem
CPU

BASIC COMPUTER FUNCTIONAL UNITS

Unit designation
Timing
Decoder
Arithmetic and Logic Unit (ALU)
Console Interface
I/O Interface
Teletypewriter Controller (TTY)
Programmer's Console

I

Memory System

(900 nsec)BA201-B
Memory Module (600 nsec)BA201-A
Memory Address Assy ~Memory
Memory Control Assy ~Control1er

Power Supply

Battery
(optional)
4-2

Slot
23
24
25,26
21
22
20

29f36
28

27

Assembly/Mounting
single P.W.A.
single P.W.A.
two identical P.W.A.ls
single P.W.A.
single P.W.A.
P.W.A.
enclosure front panel
sin~le

one to eight P.W.A.'s
(BA201-A or BA201-B)
single P.W.A.
single P.W.A.

Power Supply Unit

Unit mounted on front
door of enclosure

Equipment GD611-A

Mounted on rear cover
of enclosure
89633300 F

EXPANSION
MEMORV
SVSTEM

DATA
CONTROL

MEMORY

ME»ORY EXPANSION

CONTROLLER

I

CONTROL
• DATA

CONTROu.ER BU 12O-A

DSA
CONTROL

~~~--~----------1----------------<.~TA

CPU

TTY

A/Q
CHANNEL
WIRING

L __

DSA
CHANNEL
WIRING

~/~

A/Q
CHANNEL

OSA
CHANNEL

WIRING

WIRING

l

I
I
I
I
I
I
I
~J

__ J

IWU.i

-4- LOGI C

GROUND

,h ENCLOSURE

(EQUIPMENT) GROU.. D

fiGURE

Figure 4-1.
89633300

A

4-1

COMPUTER

SYSTEM

SIMPLIFIED

BLOCK DIAGRAM

Computer System Simplified Block Diagram
4-3

THE CENTRAL PROCESSING UNIT (CPU)
DATA PATH
The block diagram of Figure 4-2(a) shows the main circuits in the arithmetic
and control portion of the 1784 computer.
The input/output (I/O) and memory
interfaces are indicated.
As shown, the CPU consists of the ALU/Shifter network, control circuits and
registers.
In general, the registers contain operators and data for some
period of time.
When the register contents require an arithmetic, logical,
or transfer operation, they are transmitted through the ALU/Shifter network.
The ALU/Shifter network combines these quantities in a logical or arithmetic
operation, operates on them independently as in a shift, or simply serves as
a path to transfer the contents of one register to another.
Thus the
ALU/Shifter serves as the main path for all arithmetic, logical or interregister transfer operations.
The AB107/AB108 instruction Execution Charts (publication number 89723800)
give details of the contents of the computer circuits at the various stages
of execution of the program commands.
MAIN REGISTERS
X Register
The 16 bit data (X) register temporarily stores all data words read from the
memory by the CPU.
This register holds one of the parameters in most
arithmetic operations.
Y Register

The 16 bit address (Y) register temporarily stores incomplete addresses during
address modification (indirect addressing).
It stores the final effective
address when modification is complete.
It is also used to store temporarily
a data word whose protect bit is being modified during set/clear protect bit
instructions; or one whose data content (16 bits) is increased by +1 during
Replace-Add-One instruction.
4-4

89633300 A

6

2

3

00

1..0

'"

\.AI
\.AI
\.AI

o
o

D

D

1'1'1
TIMING

_

.-.0,....

''IlLIES

PERIPHERALS

ALU

N'IITfRDMttmIUCTlOMlIEGISl"ER
1.DWER5111'1S(StFTCDUNT)-

c

c

0II-2T1111E5T1E~OF

:a"~rm:-~

1llU..1FU'IIWIlESlf'TOCUfT.

MEMORY ADDRESS

~

~
-,
I
--1 -...
....,
.........

II

""

F/f

""STOP

I

RNI

I

M~ 1_________

.

Ji---

I~
w:r
Flf

'i'

~-I

........

~,

---,

hnJ.""""'i
-----,

LAST

~
®LJ

: fr-~ ~ ~i I~-

B

----

I

B

."..0

'----, =:
' ",,"::: ::;.,.."""""'"
Lm_""""",,""
... ""'"'"I ____
J "' '0"'.'"
......
FRoMUr-::7'---~ ""I.-____
"'m~ EW~
:::;:;---- I
...,
I'lPlSHEOTION

I
I

RDTAIIT SW

Ii

- -33-391

I _____
L

.

L-oIENl@

~y~~cr c:J
LriJ

=
. .J
..

"',........
.....,
""'

555

.~

CONSOLE
INTERFACE

®

~---~--i~~~

i

L__________ ;;::::_:::::::::::tJ--J---L-.....t.

A

'lDTMDDE

'e""'"

TESTIIIOOE SW

II

fI

TIW'

,I.~~ .•

--Q-"-----

1714 a..oCIC DIAGRAM

MEMORY CONTROL
.~.

TTY CONTROLLER

8

-I:"

I

Errata: 1.
2.
3.
4.

7

Zone
Zone
Zone
Zone

D-7:
B-4:
D-3:
D-3:

6

5

4

3

2

input to ALU block should be "S" CONTROL (not IIS" CONTROL)
input should be liENABLE INTERRUPT" INSTRUCTION (missing quotation marks).
INTERRPUT SEQUENCE TIMING should be INTERRUPT SEQUENCE TIMING (spelling)
in block of SAVE OVERFLOW etc, INTERRUPUT should be INTERRUPT (spelling)

\T1

Figure 4-2.

CPU Block Diagram

A

A Reg i ster
This 16 bit register is the principal arithmetic register in most arithmetic and
logical operations.

The sixteenth bit in the register is the sign bit.

The

register is also used as a temporary store for data received or transmitted on
the A/Q channel.

Q Register
The 16 bit Q register serves as the auxiliary register in most arithmetic and
logical operations.

It is also used to hold address codes of peripheral devices

operating on the A/Q channel;

it also serves as index register No. 1.

P Register
The program address (p) register contains 15 bits in the 32K mode and 16 bits
in the 65K mode (operation wi th memory expans ion).

It holds the program

address of the instruction currently being executed.

In the later stages of

execution of most instructions the P register is advanced by adding +1 through
adder/shifter network for referencing the next instruction.
The P register
may be decremented by adding -1 during some interrupt sequences.
M Register
The 16 bit mask (M) register stores the interrupt mask bits.
mask register corresponds to a particular interrupt line.

Each bit in the
For the computer to

recognize an interrupt when it occurs, the corresponding bit of the mask register
must be active (high).

8 Register

The 16 bit breakpoint (8) register holds data for address comparison during
breakpoint mode of operation.

This register can be accessed only manually

through the Programmer's Console front panel controls.

4-6

89633300 A

Instruction Register
The 16 bit instruction register stores those words read from the memory which
are to be treated as instructions.

These bits, when decoded, direct the

execution of the instructions.
I Register
Storage location 00FF16 serves as index register No.2 for indirect addressing;
index register No. 1 is the Q register.
Addend/Augend Gates
These gates serve as the input gate control for the ALU/Shifter.

In most
arithmetic, logical and register transfer operations one input is selected
by the addend gates and one by the augend gates.
The gates can select signals as follows:
Gate

can select

addend

-

output of X, P, M,

augend

-

output of X,
lower 4 bits
lower 8 bits
lower 8 bits
constants fl

Q

registers

Y, A registers
of X reg i ster (other bits equal 0)
of X regi ster (other bits sign-extended)
of X register (other bits equal 0)
and fO

The constant +1 is used to increment the P register at the end of most
instructions.
The constant -1 is used during
P register.

enter interrupt

sequence to decrement the

The constants +0 and -0 are used to sign-extend the

~

field of the instruction

reg i s ter.
The lower four bits of the X register are used during skip instructions.

89633300

A

4-7

ALU/Shift~r.

The ALU/shifter is used for the following operations:
arithmetic and logical operations on the

~ontents

of registers

transfer of A/Q channel input data, Programmer's Console input data
and the Interrupt Trap Address into the CPU data path
calculation of memory address
It also serves as the transfer path for all interregister transfer operations.

CONTROL AND TIMING SECTION
This section generates the basic timing and control signals for the computer.
Figure 4-2 (b) gives its block diagram.

Programmer's Console
The equipment front panel serves as the programmer's console: it carries the
switches and indicator lights which enable the operator to control and monitor
the computer manually.
The controls and indicators are described in the 1784 Computer System Reference
Their layout is shown in Figure 2-2 of this
Manual, publication no. 89633400.
manua I.
The circuitry associated with the programmer's console consist of three
groups of circuits:
* register selectors
* data bit entry circuit

*

control switches and indicators

These circuits are described in detail in Section 5 of this manual.

They

interface with the computer control circuits through the console interface.

4-8

89633300 A

Clock
The oscillator and phase generator together form the clock.
generates crystal controlled symmetrical clock pulses.

The oscillator

Different crystals

are used to produce the frequencies needed for the two versions of the computer:
Cycle time

Osc ill ator
frequency

Phase Generator
Repetition Rate

AB107

900 nsec

12.222 MHz

81.8 nsec

AB108

600 nsec

18.333 MHz

54.5 nsec

Equipment

The phase generator converts the oscillator signal to pulse trains on five clock
lines (PHl through PHS).
Timing unit.

The timing diagram is given in Section 5 for the

The repetition rate for the pulses is given in the table above.

A CPU cycle consists of a series of five pulses, one each on the phase generator
output lines.
Main Sequence Control and Even/Odd

Cycle~

The sequence control circuit controls the mode of operation for the execution
of a given instruction.

There are four modes of operation controlled by four

state flip-flops:
Read Next Instruction (RNI)
Address (ADR)
Operand (0P)
Operand 2 (0P2)
In addition every CPU cycle is defined as either an even or an odd cycle.
even and odd flip-flops determine the state of the machine.

The

Usua 11 Y even and

odd cycles will alternate so that one flip-flop will be set and the other reset
on the first cycle, and both fl ip-flops will change state on each following cycle.
In some cases the odd state remains for two successive cycles.
~ondition

In such a

a third flip-flop, called 0002 will be set during the second odd cycle.

The 0DD2 flip-flop is set by the signal EXT from the I/O interface board and
resets itself after one cycle.

89633300 E

4-9/ 4-10

(

\.

(

The RNI state is active at the beginning of each instruction during both the
EVEN, and the

~DD

CPU cycle.

Some interregister instructions and skip

instructions are completed during RNI so that the RNI state remains active
during the whole instruction.
In memory reference instructions the RNI state is usually followed by the
(~p, ~P2)

Operand 1 or Operand 2

states.

These are also used in register

reference instructions.
The ADR state is active following RNI in memory reference instructions while
the effective address is being calculated.

The ADR state lasts from 2 to 6

CPU cycles if there is no multi-level indirect addressing (65K mode).
it remains high until addressing is completed (32K mode).
followed by

~p

or

~P2

Otherwise

The ADR state is

except in jump instructions.

The entire effective address cao be calculated during the
ADR state is not needed.

RNI·~DD

cycle and the

This is referred to as SHort ADDRessing (SHADR). Double

addressing is explained in the part of Section 5 describing the ALU circuits.
The other control signals and timing diagrams are given in Section 5 facing the
Timing circuits (sheets 2, 5).
Counter
The binary 5-bit count-down counter is used in three operations:

*

shift:

it counts the number of times a word is to be shifted
(shifting distance)

*

multiply/divide:

it counts the number of iterations necessary to complete
the operation

*

89633300

address:

A

it controls the execution of address calculations

MEMORY SYSTEM
INTRODUCTION
The AB107lAB108 equipment contains the Memory Controller of the memory system.
The Memory Controller together with the Memory Modules, equipment BA201-A/B,
constitutes the main computer memory system.

Up to eight memory modules,

equipment BA201-A/B may be accommodated in the main computer enclosure.

Each

memory module carries 4096 (4K) 18-bit words.
The Expansion Enclosure, equipment BT148, can house the memory expansion system
consisting of the Memory Expansion Controller, equipment BUI20-A and up to
eight memory modules, equipment BA201-A/B.
The memory system housed in the main computer enclosure together with the
memory expansion system form the computer memory system having up to 16 memory
modules and thus up to 65,536 (65K) 18-bit words.
The memory system will be described in the following paragraphs.
description fal1s in two parts:

The

the control and access circuits (Memory Control

System) are described briefly, followed by a description of the Memory Module,
equipment BA201-A/B and the memory unit it is based on.

As the ABI07/ABI08

uses a semiconductor memory, the theory of operation of the memory module is
explained in greater detail than that of other circuits.

A detailed circuit

description of the control circuits is given in Section 5.
The memory system
is accessed from the CPU (A/Q channel) or from peripheral devices through the
Direct Storage Access (DSA) channel.

Refer to the paragraphs on input/output

in this section.

MEMORY CONTROL SYSTEM
The memory control system is made up of two printed circuit wiring assemblies:
the Memory Address and the Memory Control.
Figure 4-3 is a block diagram showing the memory address system and data flow.

4-12

89633300

A

I
I
I

Figure 4-3.

89633300 A

Memory Address System and Data Flow

4-13

All the memory locations are defined and accessed through the memory
address assembly in the following steps:
Step

Selection of-

1•
2.

Memory bank
Memory module

3.

Ki loword

4.

I

Defines

-

main memory/expansion memory
- anyone of i nsta 11 ed modules
(up to eight in main enclosure,
up to eight in expansion enclosure)
-. one of four kilowords on selected

-

Rowand column

memory modul e
word location within the kiloword
(bit within the memory unit)

In addition to accessing operations the memory address circuits define the
origin of memory access.
The following table defines the d.ifferent
memory access cycles:
Des i gnat ion

Data flow to/from

1.

Refresh cycle

Internal to memory sys tern

2.

DSA cycle

Direct Storage Access channel (DSA)

3.

CPU cycle

Central Processing Unit
.', · ......

·.~

.. _ _

'4~

.....· _

---_. __.-

----

.. ...-.--..
~

Data input (16 bits) to the memory is through the memory address circuits,
which also generate the parity and protect bits, that make up the l8-bit
computer word.
Data output is through the memory control circuits to either the CPU or the
DSA channel. The control circuits also produce the timing and control signal
for the memory system, under command of the CPU and synchronously with the
CPU clock.

4-14

89633300 A

PRINCIPLES OF THE DYNAMIC SEMICONDUCTOR MEMORY CHIP

Introduction
The memory module (equipment BA201-A/B) of the AB107/AB108 Computer uses
dynamic 1024 bit (lione kilobit") random access memory units, built on
semiconductor chips using silicon gate MOS technology.

They are Large

Scale Integrated (LSI) networks, and perform several system functions on
the same chip.

Device Operation
The memory unit is a 1024-bit, fully decoded read-write Random Access
Memory (RAM).

Each bit of information is held in capacitive cells as

a stored charge.

Because of charge leakage, each bit must be regularly

refreshed (recharged).
by 32 cells.

The memory is organized in a matrix of 32 rows

The row and column address select one unique bit from the

1024 storage bits on the chip.

Each time a bit is read from or written

into a memory cell, all 32 bits of its particular row address are
automatically refreshed.
The circuit of each memory cell is shown in Figure 4-4.

An array of

1024 of these are mounted in an 18 lead dual in-line package.

Figure 4-5(a)

shows the block diagram of the circuit package, together with pin connections.
A more detailed logic diagram is shown in Figure 4-5(b).

The following

paragraphs describe the operation of the memory cell and the integrated
circuit package in greater detail.

89633300

A

4-15

The dynamic MOS memory cell circuit is shown in Figure 4-4.
NOTE
"H i gh" and "Low" refer to signa 1 1eve 1
change with respect to the MOS substrate.
Data is stored as charge on the parasitic capacitance Cs associated with the
gate of Q2 and the junction of Ql connected to it.
Data may be written into
this capacitance via the transmission gate formed by transistor Ql.
The data~
to be written is placed on the WDATA line and WSEL is activated (made high).
To read from the cell, the RDATA line with its associated capacitance (or
amplifier input) is initially charged high through the external gate by
activating the P (Precharge) signal.
To complete the reading operation
the RSEL line is activated and the RDATA line is recharged only if the
capacitor Cs is charged high; the RDATA line remains high only if Cs contains
a low.
Thus after the reading operation the RDATA line carries the
log i ca 1 comp 1emen t of the ce 11 .da ta •
Although the read-out operation from the cell is non-destructive, the leakage
associated with the junction of Ql eventually may result in the loss of the
charge stored in CS.
To maintain the data stored in the cell, it is
periodically refreshed through feedback of the cell content to the WDATA
line during every memory cycle. This is accomplished by reading the
contents of the cell onto the read RDATA line, inverting the resulting
signal in the refresh amplifier and applying it to the WDATA line, and
writing it back into the cell by activating the WSEL line. For the RAM of
equipment BA201-A

regeneration has to take place every 2 milliseconds,

(1 millisecond in equipment BA201-B). During normal operation of the computer

(

refresh cycles are generated automatically, interleaved with CPU and DSA
access cycles. Refresh cycles take priority.
generated when no access cycles occur.

Special refresh cycles are
(

\

4-16

89633300 A

The dynamic cells are laid out in a two dimensional array on the chip.

One

entire row of cells is refreshed (or accessed) at one time, one refresh
amplifier being provided for each column of cells in the array.
To
refresh the entire memory, each row of cells must be individually
refreshed.

WDATA

WSEL

Figure 4-4.

89633300 A

The Memo ry Ce 11

4-17

Organization
General block diagrams of the memory unit are shown in Figures 4-5 (a) to
(d).
each.

The memory is organized in a matrix of 32 rows by 32 cells
Five row address lines, AO through A4, are decoded to select one

row of cells.

When accessed, the contents of the selected row are

transferred to a row of 32 refresh amplifiers.

In the course of a

memory cycle, whether read or write, the data is regenerated and written
back into the selected row of cells.

Address bits A5 through A9 are

decoded to select one refresh amplifier for communication with the data
input and output terminals, through the Read/Write Column Gates.
Activation of the write-clock (Read/Write signal) effectively disconnects
the refresh amplifier and so causes new data to be written into the cell.
Data output is sensed as a current through the common data output gate
(DATA out gives zero current output for DATA high, about 0.9 milliamperes
for DATA low).

Figure 4-6 shows the basic timing of the chip memory cycle.
The cycle timing is established by the three clock signals:
Cenable (Chip Enable), and Write.

Precharge,

Initially (prior to execution of a

memory cycle) all clocks are at their high state, at a voltage approximately
equal to the supply voltage, VSS.
transition of Cenable.

Access begins tAC before the negative

During this period Precharge is active, and the

address becomes stable in both row and column decoders.

After the Cenable

transition the contents of the 32 cells along the selected row are written
into the 32 on-chip refresh amplifiers.

At the positive transition of the

Precharge the contents of the refresh amplifiers are written back into their
respective columns and the output appears tpo later.

A delay of tpw after

the positive edge of the Precharge,new data on the data input line may be
written into the selected cell using a read/write pulse (minimum duration
twp)·
4-18

89633300

A

IK
AO

lof 32
Row
Selector
(I per Row)

AI
A2
A3

A4

32

R8CIt/ Write
Amplifiers
(2 per Row)

Memory CeU Array
64

Ie

32 Rows
32 Columns
(1024 Bits)

64
Refresh
Amplifiers
(2 per
Column)

Control Sianals
Precharge

5

Cenable (Chip Enable)

16

Read/Write

18

32

Data Inl

ReadlWrite

Supplies
VSS ={+l9.7 volt(BA20I- A) 17
+16.7 volt (BA201-B)
Vee = VSS + 3 volt

10

VDD = ground

II

Column

2

Data In

Data Out
Circuit

Gates
(I per Column)
32
lof 32
Column
Selector
(I per
Column)

Selector Signals
Pins:

Figure 4-5.
Memory Unit.
(a) Block Diagram and External Connections.

89633300

A

4-19

Row
Selectors

Row 0

Read/Write
Ampllflera

A1
AOI
A2
A3
A4

~O

Al
Row 15 A2
A3
A4

R

I
R

Refresh
Amplifiers

To Second
Read/Write
Amplifier
In this Row

~--oR

Column Gatea

To Other Half
of MemoryUnH

{
____~~----~----{~----------_+--~~~~----~~~

Data Out

T

Column
Selectors

Data In

CE

Column 16

Column 31

Figure 4-5.
Memory Unit.
(b) Detailed Block Diagram.

4-20

89633300

.A

Balle Memory
RSEL

e.1I
RDATA

WDATA

Shown al:

WSEL

Addr...

Invert.,1
p

A P A
L
L
H
H

A: AO through

L H
H H
L L
H value

of
previous state

AS

H: High
L: Low

Figure 4-5.
Memory Unit.
(c) Circuit Details.

89633300 A

4-21

Refresh

Amplifier
Auxiliary

Gates

....-..0 pI
P

CE~P
WDATA LINE

Row Selector

RDATA LINE

and

Read / Write Amplifier

0---'1

RSEL

WSEL

NOTE:
Column Selectors
a re Identical to
Row Seleetara

VSS

Figure 4-5.
Memory Unit.
(d) Circuit Details.

4-22

89633300

A

00
\D
<7'
\At
\At
\At

g

2

3

4

5

6

7

8

9

CLOCK

>

H
Addre ..

-.

Prlohar,.

L

10

II

2

I

~

Address

~

Stable

Address
Can Change

t OVH

H
L

/

"TI

10

C
-,
~

H
Cenable

"

L

.I:"

-

I

_<7'

01 •

nx
-O~

c:a

01 -,
:::J'<

Q.
-I
0-'

(1)3

> -.
:::J

H
Read/Writ.

Data In
(Writ. Only)
Data Out
(Write,Rfad/Write )

t OVL

H

L

Data Can
Change

X
----- ro-,
-- D~ta
V~~i~
Stable Data

H
L

tpo

""" "-

= 40mV
RLOAD =lOOn.

n

VREF

~

!II

CLOAD
Data Out
( Read)

H
L

V

1'\

L

nlO
'<

.I:"
I
N
\At

/
twp

tpw

No

II

-'\0,.

Data Out
Valid

=IOOPF

--------- 1',

"

Data Out Valid

Data Can
ChanQe

Figure 4-6.
(b)

4-24

Memory Ti mi ng.
Refresh Cycles
89633300

A

The memory unit described here has two versions differing in their basic
cyc let i mes :

*

the BA201-B module allows a computer cycle time of 900 nanoseconds in
the ABI07 equipment

*

the BA201-A module allows a computer cycle time of 600 nanoseconds in
the ABI08 equipment

One type of memory module (BA201-A or BA201-B) may be accommodated in the

I

enclosures (computer enclosure and expansion enclosure, equipment BT148)
at anyone time. The memory controller and memory expansion controller are
suitable for both types and only the enclosure supply voltage (V SS ) has to
be changed. This is done at the time of installation of the first memory
module in the enclosure.
The basic timing specifications of the memory units are given in Table 4-2.
TABLE 4-2.

BASIC TIMING SPECIFICATIONS OF THE MEMORY UNITS
Chip used in
BA201-B Module
Per i od

Symbol
tREF

Time between refresh

tAC

Address to Cenable setup time

tOVL

Precharge

&

Precharge
high

MAX

115

MAX
1

UNIT
ms
nsec

30

.
nsec

-10

25
&

MIN

2

Cenable overlap,

low
tOVH

MIN

Chip used in
BA201-A Module

Cenable overlap,

tpw

Precharge to Read/Wr i te delay

twp

Read/Write pulse width

tpo

End of Precharge to

140
165

500

nsec

500

nsec
nsec

40

50

output delay

115

85

120

75

nsec

t ACCI

Address to Output Access

300

135

nsec

t ACC2

Precharge to Output Access

310

165

nsec

89633300 F

4-25

DETAILED OPERATION OF THE MEMORY UNIT
To begin a cycle, Precharge is brought low, to approximately VDO potential.
This operation activates the row and column decoders, and also charges all
read and write data lines negatively, i.e., to the equivalent of a logic
"high" state for the P-channel MOS.

(In the discussion which follows,

clocks, etc. are considered "on" at VOO level, and "off" at VSS level.
"High" and "Low" refer to the change with respect to the MOS substrate.)
The decoder circuitry is somewhat faster than the line charging circuitry,
so addresses need not be stable until somewhat after Precharge is applied.
Address data may be provided before Precharge is turned on.
After Precharge and address data have been present long enough for the data
lines to charge and the row and column decoders to stabilize (time tAC after
Precharge is low). the Cenable clock is turned on
low state.

i.e., dropped to its

At this time, the desired read-select line is activated and

the read-data line charging circuits are disabled.

This initiates the

writing of the contents of the 32 cells along the selected row into the
32 on-chip refresh amplifiers, one amplifier for each column in the array.
The data lines begin to discharge selectively, with the signals on them
approaching values corresponding to the complements of the data stored
in the selected row of cells.
As the read-data lines selectively discharge, the Precharge signal is
turned off, i.e., raised high to VSS.

Following this the contents of

the refresh amplifiers are written back into their respective columns;
and after the period tpO the output appears.

This is accomplished by

the removal of the charging signal on the write-data lines, and closing
a path to selectively discharge these lines.
The cell contents are
restored by activating the write-~elect line corresponding to the
selected read-select line.

The signal level on the write-data

line is a function of the overlap time between Precharge

4-26

89633300 A

and Cenable.

If this overlap is too short, the read-data lines will not

have discharged sufficiently when the discharge path from the refresh
amplifiers to the write-data lines is closed.

As a result, high {negative}

levels written into the cells may be reduced.
If, however, the overlap time is excessive, weak lows within the cells may
result in some discharge of the read lines before closure of the write-back
path.

Thus cells with weak lows have higher levels {even weaker lows}

written back into them, eventually resulting in lows changing to highs.
This problem is somewhat aggravated by the small but unavoidable capacitive
coupling between the data and select I ines and the cell storage capacitor.
Provision is made for controlling the overlap time in the Memory Control
and Memory Address units.
When Cenable is turned on, a current path from VSS to the output is
established, for one column decoder is enabled and all write-data lines
have been charged high {negative}.

If the selected cell {the cell at

the intersection of the selected column and selected row} contains a low,
the write-data line will discharge after Precharge is removed and the
output current will be cut off.

If, however, the selected cell has been

negatively charged {high}, the output current will continue to flow.
Cenable must remain present for a sufficient time after Precharge turn-off
to allow the contents of the selected row of cells to be refreshed.

Even

after Cenable is turned off (raised to VSS ) the addresses must remain
present for about 20 nanoseconds to allow completion of internal operations.
Precharge Will not be applied again until Cenable has been off for at
least 85 nanoseconds {see Memory Control operation}.
To write new data into the selected cell, with or without a read operation,
all sequences proceed as above.

However, the write line is activated

before Cenable is removed and tpw after the positive edge of Precharge;
this allows the write-data lines to stabilize.

89633300

A

As a result, the read

4-27

data lines are discharged, effectively disconnecting the refresh amplifiers
from the write data lines.

~

path from the data-input line is also

enables into the selected write data line.

Thus, a direct path from

the data input to the selected cell is established.

A signal on this

input will then overwrite the contents of the cell.
The timing specifications for operating the unit are shown in Table 4-2.
All the time values listed, except t po ' t ACCI are generated by the memory
system. The time designated tpo refers to the time delay observed
between the turn-off of Precharge and the availability of data at the
chip output terminals, and is a characteristic of the unit.
The two access times, t ACCI

and

t ACC2 represent a combination of system

operating parameters and characteristics of the chip.

Thus the stated

IIminimum" values represent the shortest access times which can be
guaranteed when the unit is operated within the limits specified and
with rise and fall times of 20 nanoseconds.

System access times will

exceed these values because of the additional delays and tolerances
introduced by the rest of the system.

4-28

89633300

A

REFRESH TI ME
The maximum time interval between accesses to memory cells (t REF ) is specified
as 2 milliseconds for units on the BA201-B module, 1 milliseconds for units on
the BA201-A module.

To guarantee that data is retained within the memory, at

least one read or write cycle must be executed for each row of cells within
this refresh interval.
As the rows are selected by address inputs AO
through A4 at least 32 memory cycles, one for each state of address 1 ines AO
through A4 must be executed in each refresh interval.
These cycles may
result from norl11al accessing, as in a sequential-access mode of operation of
the memory.
In other cases special refresh cycles must be executed.
In the
Memory System (AB107 equipment) the cells are refreshed every 1.5 millisecond,
in the Memory System (AB108 equipment) every 1.0 mill isecond.

CHIP SELECT
In operation, the Cenable clock also acts as a chip (memory unit) select.
That is, Precharge and write signals may be applied at their normal times
in the cycle, but if Cenable is not applied, the unit will neither deliver
current to the output terminal nor will the contents of any cell be altered;
no refreshing of memory content takes place during such a cycle.

POWER SUPPLY LEVELS
Signal and power supply levels are important to the proper operation of the
unit.

Speed is a function of both the VSS level and clock amplitudes.

general, higher amplitudes or voltages result in faster operation.
bias VBB also has an effect on performance.

In

Substrate

This bias improves noise

immunity and prevents parasitic interaction within the device.

89633300

A

4-29

INPUT CLOCK AMPLITUDES
To guarantee operation of the memory chip over the full temperature range
at the speeds specified the clock amplitudes must be maintained at the
specified values.
These are:Hi gh:

~

o

0

VSS -0.7V at 70 C to VSS-l.OV at 0 C

The value of the supply voltage (V SS ) determines that of the bias voltage
VBB (refer to Figure 4-13 of the Power Supply Regulator and Control Circuits).

SYSTEM CONSIDERATIONS
The memory units are used in a rectangular 18 x 4 array to provide storage
units of 4096 (4K) words of 18 bits each.
Such an array with its supporting
circuitry is called a Memory Module, with the main addressing and control
circuits for up to eight modules carried on the Memory Address and Memory
Con t ro 1 un i ts .
These are described in other parts of this section and in
Sect ion 5.
Maintenance and safety precautions relating to the Memory Modules and to
the memory units are given in Section 7.
The contents of the memory unit has to be refreshed periodically as it is
a basically volatile store.
The memory system, however, is made nonvolatile for at least 8 hours with the use of a battery and a special
Low Power Data Retention (LPDR) mode of operation.
This is also described
in other parts of this section.

4-30

89633300 A

MEMORY MODULE

The Memory Module is the basic unit of the AB107/AB108 memory system.

It

consists of a 4x18 array of memory units to give 4096 (4K) l8-bit words
together with immediate supporting circuitry, all accommodated on a single
50-PAK printed wiring board.
given in Figure 4-7.

The block diagram of the Memory Module is

The memory units are described in previous paragraphs.

The following paragraphs give the description of the block diagram followed
by the function of the auxil iary circuits listed in the table.

Circuit

Function

J-----------------If---------------------.--...-------.-.----Leve 1 Sh i fters

adapt TTL logic levels to MOS levels

Cenable-Precharge delay

regulates the overlap (t OVL ' t OVH )

Aux i 1 i a ry log i c

generates internal control signals
from available control signals

LPDR circuit

generates the switched supply (Vccs) used
in Low Power Data Retention operation

Data Out Sense Amplifiers

convert the signals appearing on the opencollector of the memory unit data out lines
to TTL signals (current to TTL
conversion)

,

I

109~IC

~-------------------------~------------------------

A description of these circuits is given in Section 5 (Memory Module).

89633300

A

4-31

THE MEMORY MODULE BLOCK DIAGRAM
The memory matrix provides the actual storage location within the memory system.
It is an array of four rows of 18 memory units, forming four thousand words of
18 bits each.
The data flow to and from the memory matrix is on the 18 data-in and
18 data-out lines corresponding to the 18 bits of each kiloword.
The
data-in lines of the memory units of corresponding bits in the four rows
are connected together in a wired-OR and the same is true of the data
output lines.
A level shifter is incorporated in each of the 18 data-in
lines to adapt the TTL levels from the CPU to the MOS logic levels needed
in the memory matrix.
Similarly the data out lines from the memory matrix
are buffered and level converted in the sense amplifiers.
Selection of a particular location in the matrix is achieved in two stages:
first one of the four rows of 18 memory units (one kiloword) is selected
by the corresponding kiloword selector signal (lKO through lK3).
This allows the memory control signals (Precharge, Cenable) to reach the
memory units of that word. In the second stage the row and column address
signals, through the address level shifters, select a particular 18 bit word
within the selected kiloword.
The memory control and timing signals perform functions as follows:
Se lects memo~y-~~it-·'
j

I

I

R/W

Read or Wri te

Strobe

Strobes output data

IL_.
MDX
--

4-32

Chooses memory module!
.j

89633300 A
(

\.

00
\.0

o

o

."

.

Cenable
Precharoe
Delay

'"

W
W
W

Kiloword
Select

4

4"

-

~

(IK~-IK3 )

4i

I
~,

Precharge
Level
Shifter

4

4

. of10"1I
-I Tarmln

,

~"

4

Fast Precharge (Bi t 17)

,

4

Cenable
Level
Shifter

4

Cenable

B
I--

R/W

I

,

Memory Matrix
4 x 18 Array of
Memory Units
Forming four
Kilowords
of 18 - B its Each.
(IKO through IK3)

Sepor'lte
Control
Signals
Fer Each
Kiloword

] Common

5
R/W
Levsl
Shifter

--

18

Read/Write

B

4

~--

4

,~4

....

-

Data In Level Shifters
( Y 18)

Precharge
(Bits 0-16)

4

CE

.

A1dre3~~

lines to All Units

----

5

Strobe
Row AIddress
(ARAO-ARA 4)

......

-

5

Address
Level
Sr.ifters

"
5

Column Address
(ACA5-ACA9 )
Strobe
Disable
REF
MDX

:=j

I

MD ---- Controls
VCC2

•

I-----.,.~

sfrobe

0

M0

t----•• B

I

•
YIPDRI
L

VCCS

"

eet

I.

I

I Figure 4-7.

18 Data Out Lines

MPWRo--+-~

.::W
W

"

Data - out Sense Amplifiers

St r?be ---. ] Common

Address
Level
Shifters

5
Auxi liary
I ",,;,.
LogiC

"18

Memory Module Block Diagram

--+

Data flow is shown in
thick lines.

-r::=:;:=:t-

2.

~

Transfer takes place only

when condition i. pr ... nt.

AUXILIARY CIRCUIT FUNCTIONS
Level Shifters:

TTL to MOS

TTL logic levels are 0.7 volts (low) and 2.0 volts (high).
MOS levels are
approximately zero volts to VSS (17 volts).
~ level shifter is needed to
match the two kinds of logic circuits.
The following signals use identical control signal level shifters:
Precharge
Read/Write (R/W)
Address

I

The Cenable signals use the same level shifter but with two components
added. See page 5-23.
Level shifters are also used on the 18 data-in lines to adapt the TTL logic
levels of the incoming signals to the MOS level of the memory circuits.

The Overlap Circuit (Cenable - Precharge Delay)
There is an overlap delay circuit in the precharge line of each kiloword unit
on the Memory Module.
It regulates the overlap timing tOVL and tOVH in
the memory units (see Table 4-2 and the Detailed Operation of the Memory Unit),'
and consists of a diode switching network controlling RC delay circuit.

4-34

89633300 F

Low Power Data Retention
During power failure the computer reverts to Low Power Data Retention (LPDR)
mode.
During refresh cycle bursts in this mode none of the TTL logic circuits
receive power.
This circuit controls the V 2 supply to produce the switched
cc
logic (Vees ) supply, provided the optional power back-up sources battery
equipment GD611-A is installed.
This arrangement preserves the memory
content for up to eight hours (see next subsection).

Data-Out Sense Amplifiers
The open collector outputs of the corresponding bits of the four kilowords on
the module are wire-ORed to form 18 lines.
These are ampl ified in and gated
by the sense amplifiers to form the 18 TTL-compatible output lines of the
memory module.

89633300

A

4-35

LOW POWER DATA RETENTION (LPDR) MODE
POWER BACK-UP
The memory chips are volatile: they wiJI lose their stored charges if they
are not refreshed periodically.
To make the memory system non-volatile,
it is designed to switch over to battery operation automatically in case
of power failure.
A back-up battery, optional equipment GD611-A when
installed can supply power for the retention of the full memory contents
for a period of up to ei ght hours.
When the utility power fails, the voltage on the dc power supplies
begins to drop. The power supply senses this voltage drop, and
raises the signal RGPWR to the Memory Control.
Due to large storage
capacitors in the power supply, the voltage~ remain in the
uncritical region for at least one millisecond and the memory
continues to function.
When the Memory Control receives the raised RGPWR signal, it
continues to operate normally for half a mill isecond. During this
time the CPU performs a special interrupt subroutine. At the end
of this one-half millisecond period the Memory Control switches to
the back-up mode.
To retain the memory content in the back-up mode the Memory Control
will not perform CPU or DSA cycles, but immediately performs a
burst of 32 row refresh cycles in rapid succession and so refreshes
the whole memory. The power supply switches to battery operation.
All circuits which require constant powe~ such as the memory chips,
continue to operate from the battery. All circuits that do not
require power, such as the CPU, are allowed to fail as the utility
power fails. All circuits which need power only during refresh
burst, such as address drivers, are power switched by the Memory
Control during refresh burst. Since 32 row refresh bursts require

4-36

89633300 A

(
(

\

(

only 14 microseconds to perform, and refresh bursts are performed
once every 1024 microseconds, the power switched circuits are off
for a considerable time, conserving a significant amount of power.
In the back-up mode the memory chips use most of the power.

When the power supply senses that util ity power has returned, it
switches to util ity power, and drops the RGPWR signal.
The Memory
Control performs one more refresh burst, and then switches to
normal mode operation.
During LPDR operation the Memory Hold Battery (optional equipment GD6ll-A)
supplies power.
During normal operation the battery is recharged from
the power supply.

89633300 A

4-37

PROGRAMMER'S CONSOLE
The equipment front panel serves as the Programmer's Console: it carries the
switches and indicator lights which enable the operator to control and monitor
computer operations.
The front panel controls and indicators are described in the 1784 Computer
Their layout is shown in
Reference Manual, publication number 89633400.
Figure 2-2 of this manual.
The circuits on the Programmer's Console can be grouped in three functional
areas:

*
*
*

Control switches and indicators and associated circuits;
Register selectors;
Data-bit selection circuit.

These circuits are described in Section 5 of this manual.

.

4-38

89633300 A

(

INPUT/OUTPUT
Any peripheral controller that uses the A/Q channel or the DSA channel may

I

be accommodated in the ABl07/ABl08 equipments. The following table is a
partial list. See the preface for more information.

CONTROLLER
EQUIPMENT No.

I

CONTROLLER DESIGNATION

Part of ABl07/ABl08

Teletypewriter

FA716-A
FA442-A

Cartridge Disk Drive Controller (CDDC)

FV497-A
FA446-A

ICL Phase Encoding (PE) Formatter
LCTT Magnetic Tape Transport Controller(MTTC-LCTT)

Fv6l8-A

LCTT Phase Encoding (PE) Formatter

(TTY)

ICL Magnetic Tape Transport Controller (MTTC-ICL)

The Teletypewri ter (TTY) Controller forms part of the ABl07lABl08
equipment; the other controllers are separate equipments and are
accommodated in prewired slots within the main enclosure (ABl07/ABl08
equipment).

Other controllers may be connected to the

comp~ter

through

one of the two access channels, the non-buffered AQ channel using the
A and Q registers and the Direct Storage Access (DSA) channel.
In the following a short functional description of the TTY controller is
given as well as the pin assignment and timing diagrams for the AQ and DSA
channels.

The TTY controller logic circuit diagrams are given and are

described in detail in Section 5.

Refer to the 1784 computer Input-Output

Specification Manual, publication number 89637100 and appropriate peripheral
controller manuals for further information.

89633300 F

4-39

THE TELETYPEWRITER (TTY) CONTROLLER
The TTY Controller can interface the computer CPU with a Teletypewriter
Terminal and with a Conversational Display Terminal (CDT). It provides for
communication at 9600, 1200, 300 or 110 bauds. The baud rate is selected
by inserting a jumper plug in the appropriate location on the board.
DIRECT STORAGE ACCESS (DSA)
The DSA channel provides fast external access to the computer (equipment
ABI07/ABI08).

Access connections are available on identical pins of

preassigned slots of the main enclosure (equipment ABI07/ABI08) and of the
expansion enclosure, equipment BTI48 (refer to Figures 3-1 and 3 w 2)

I

Printed wiring boards conforming to 50-PAK specifications can be
accommodated in these slots.
on the DSA channel.

Figure 4-8 shows the timing of the signals

The pin assignment for the slots allocated to

controllers using the DSA channel is given in Table 4-3.
DSA Circuit Connections
The DSA channel is designed to be used with TTL 2-input NAND buffers
(IC 7438, PN62031200).

Each DSA line is terminated by a 270 ohm pull-up

res istor (to V ) in the CPU. Each input to the CPU loads the I ine wi th up to
cc
20 TTL load units. DSA output lines should be loaded with one TTL load
unit or less.
Scanner conditions are not prewired and should be made at the time of
installation (refer to customer engineering manual for appropriate

I

controller). See the list in the preface.

4-40

89633300 F

TABLE 4-3.

OSA CHANNEL PIN ASSIGNMENTS
P2

P1
A

1

B

S005
so06
SOOO
S012
SOl1
S003
so04

1
2
3
4
5
6
7
8
9
10

SOOl
S002
so07
so08
S009
SOlO

Me

SRQ

m

S016
SFI
S017
32kW

I

I
I

I

GNO

SOJ3
S014

11

SR'SM

SAOS
SA09
SAlO
SA 11
SA12
SA13
GNO
SA14
SA15

A

I

12
55
13
SPI
14
SRI
15
16 SCRiM (sRi)
SVIO
17
18 AUTOLOAD
19 . SCFiM (SF'J)
20
SWRITE
21
22
SAvO
23
SAO 1
24
SAO 2
25
26
SA03
sA04
27
SA05
28
29
SA06
30
SA07
31

I

Vcc

I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

B

!

GNO

NOTES:
1.
Signal polarity
Address bits (SAOO~SA15) are active high.
Oata bits (SOOO~S015) are active high for OSA transfers from the computer (Write).
Oata bits (S0007S015) are active low for OSA transfers to the computer (Read).
All other signals on the OSA bus are as indicated (overlined: active low).
2.

Power Supply

~

Total usage of all controllers on A/Q and DSA buses should not exceed 30 amperes
in each enclosure.
r.ND = logic ground.

89633300 A

Vcc =+5V.

4-41

~

I

~

N

n

SRQ

I I

i

I '

I-- N......I
I.:

I

DSA ADDRESS

I

i

I

."

.,

I
I. II
I

(1)

~

I

00

I

c

~~"--

l>
n
::r

III
::::J
::::J
(1)

-.

3

::::J
\Q

~Dr-

_

~'ATA

_

IN

K

J

i

I

I

i

I

(TO COMPUTER) :.

I

I----t
~B-.I
~

I
~B~

i I

I

~D~
I

I

'. I

-

: .,

i --:

PROTECT

(J)

-t

_. J

I

C

K"

I
L.,

I

E

TAC'"
I,
.

I

I

L

I

if,

:

F:

f--C

--J

I

I

i

~.8 -I

.1

I
i

!
I

I
:

,.- G ~H-,

I

.. ----. _____Ir-- - - -

"'"'o'"""
"'o"
l>

~

I

. - . 1_ _ _- - - ,

DATA OUT
:
(FROM COMPUTEFQ
00
\.0

I

:

"I

J

i i i -r-

\Q

s

IN-I
I

I

-

I

--r· .

,I.-A-I
~=:-::-~
•. a"-;::;::_

11-----------.---------I

I

!

r-

Notes:

refer to next page.

I

J -'

I

OJ

NOTES to Figure 4-8.
1•

Signa 1 names:
TAC :
SRQ:

2.

DSA Access Time
Memory Access Request from DSA channel.

Timing

1 784 - 1

1 784 - 2
Remarks

minimum
(nsec)

typical
(nsec)

A.
B.

-

-

50

-

c.

-

D.
E.
F.
G.

390

110

605

-

655
900

190
120

-

-

-

-

10

-

10

-

0
210
0

-

-

320
470

330

-

1240

-

855

-

1455

89633300 A

110
200
245
60
705

-

-

0
150
0

-

maximum
(nsec)

-

220

-

TAC

-

-

typical
(nsec)

-

-

J.

N.
S.

440
600

minimum
(nsec)

50

215
285

70

L.

-

70
175
120
60
490

-

H.
K.

-

maximum
(nsec)

-

-

2140

at maximum
DSA access
rate
wi th DSA
Priori ty
wi thout DSA
Priority

4-43

(
NOTES to Figure 4-8 (Cont'd.):

3.

Refresh cycle time:
490 nsec once every 32 microseconds (600 nsec Memory)
735 nsec once every 48 microseconds (900 nsec Memory)

4.

Hodes of Operation
Worst Case
The maximum DSA access time (TAC ) occurs when the memory system performs
CPU access cycles and successive Refresh cycles.

DSA Priority signal active
The memory system cannot perform CPU cycles.
The DSA access time (TAC )
is minimum; it is increased by the regular occurrence of Refresh cycles.

Successive DSA requests
The memory system cannot perform CPU cycles on the memory bank addressed
by the equipment on the DSA channel. The DSA cycle time is equal to the
memory cycle time (600 nsec or 900 nsec).
The DSA cycle time will· be
Note that on single-bank operation
increased by the Refresh cycles.
no CPU access can occur if the DSA requests are generated fast enough.

4-44

89633300 A

A/Q CHANNEL
This is the non-buffered bi-directional input/output (I/O) channel for the
computer (equipment ABI07/ABI08).
of the CPU.

It utilizes the 16-bit A and Q registers

The Q register contains the address of the peripheral equipment;

the A register contains the data equipment status and director functions.

I

Access connections are available on identical pins of preassigned slots of the
main enclosure (equipment ABI07/ABI08) and of the expansion enclosure
BTl48 (refer to Figures 301a, 30Ib).

Printed wiring boards

equip~ent

confo~ming

to 50-PAK

specifications can be accommodated in these slots (refer to AB107/ABI08 Computer
Input-Output Specification Manual, publ ication number 89637100).
Output on A/Q Channel
A single word is output from the A register whenever an output instruction
is executed by the computer.

The presence of the output data is signified

by the active state of the write I ine.

The peripheral equipment whose address

is in the Q register should respond with a Reply or a Reject signal within
4 microseconds. The computer generates an internal Reject and reinitiates
execution of instructions if no response is received from the device within
12.8psec (ABI08) or, 19.2psec (ABI07). If a Reply is received by the computer,
the next instruction executed is the one following the output instruction
(P+l).

If an external Reject is received, the next instruction

execu~ed

is located at P + 1 + A, where A is the lowest eight bits of the output
instruction, the highest bit of A being a sign bit.

If an internal Reject

is generated the next instruction executed is located at P + A.

P is the

address of the output instruction.

89633300 C

4-45

Input on A/Q Channel
A single word is input to the A register whenever an input instruction
is executed by the computer.

The request for data by the computer is

signified by the active state of the read I ine.

The peripheral device

whose address is in the Q register responds with a Reply when data is
available to the A register.
If no data is available, the peripheral device responds with a Reject.
In either case, the peripheral device must respond with a Reject
Reply within 4 microseconds.

If no response is obtained in 12.8].lsec

(ABI08) or 19.2 llsec (ABI07) , the computer generates an internal Reject.
Reply causes the computer to go to address P + 1, where P is the address
of the input instruction.
to address P + 1 +

~,

the highest bit of

~

where

An external Reject causes the computer to go
~

is the lowest 8 bits of the input instruction,

being a sign bit.

computer to go to address P +

Internal Reject causes the

~.

Status on A/Q Channel
Each peripheral device must have one or more codes which can be loaded
into the Q register.

When the computer executes an input instruction the

status of that device will be loaded into the A register.

All devices

must respond to status requests wi th a Reply since the status must always
be available within 4 microseconds.

If a no response is received by the

computer, it generates an internal Reject after 6.4 ].lsec (ABI08) or
9.6 ].lsec (ABI07).

4-46

89633300

c

A/Q Channel Access
A/Q Channel accesses are available on identical backplane pins of prewired
card slots of the equipments. Table 4-4 lists pin assignments for the
va r i ous signa 1s •
A/Q Channel Timing
Figure 4-9 describes timing restrictions of the A/Q channel. In addition
to the signals shown, a timing pulse is generated 135 nsec (±40 nsec)
before a Read or Write signal can appear on the A/Q channel. The timing
pulse is active for 75 nsec (±20 nsec). For more detailed signal
description and timing, refer to I/O Specification manual number 89673100.
A/Q Channel Loading Rules
Each signal (data or control), transmitted from a peripheral controller to the
CPU .f" the A/Q. channel, must be driven by an open-collector NAND buffer
(IC Type 7438, CDC PN62031200).
Each input line is terminated at the input
to the receiver on the CPU by a 180 ohm pull-up resistor (to Vcc ) • The input
loads the line with 20 TTL loading units.
Each device on the A/Q channel is allowed to load any line from the CPU by
one TTL load unit. The data bus (A register) is bi-directional.
Fi gure 4-10 gives examples of typical i nput,output and b i-d i rect iona I lines.

89633300 A

4-47

TABLE 4-4. A/o. CHANNEL PIN ASSIGNMENTS
P2

PI

II

A

-A05

1
2
3
4

A06
AOO

m
All

X(JJ

A04
TP
AI5
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
WEZ

READ
REPLY
PRTM

GND

Notes:

1)

5

6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

o.OO~o.15

B

A

-AOI
A02
A07
AOB
A09

GND

1mT

CMI

m

m

GND
0.01
0.03
0.05
0.07
0.09
0.11
0.13
0.15

B

1
2
3
4
5
6
7
8
9
10
11

WRITE
REJECT

He

are active high;

I

Vcc

12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

GND

all other signals are active low.

2) Vcc = +5V. Total usage of all Ao. and DSA controllers should not exceed
30 amps in each enclosure.
3) GND = logic ground

4-48

89633300 A

INPUT OPERATION

____~--~II~______~

DATA

-1L

READ
REPLY OR REJECT

j 1a~ I

Alj~~
E----~~r--l~__________~r__1~____

A

=

0

14SEC MIN

(ci)

PERIPHERAL DEVICE

D

a

=

O.014SEC MIN

(ci)

COMPUTER

E

C

= O.014SEC

MIN

=
=

(ci) PERIPHERAL DEVICE

0

14SEC MIN

(q) PERIPHERAL DEVICE

4.0

14 SEC MAX

(ci) PERIPHERAL DEVICE

0.2

14 SEC MIN (Ii) PERIPHERAL DEVICE

OUTPUT OPERATION

~D~Ak-

""'AJ.-

--.-J

WRITE
REPLY OR REJECT

A

= 0.1

a

= 0.0 14 SEC
= 0.0 pSEC

C

14SEC MIN

L

U

-.J

DATA

MIN

(ci) COMPUTER

MIN

(ci) PERIPERAL

n

.Qlct-

LE

(ci) COMPUTER

I

I

-tal-

/'

DEVICE

D

=

0.1 14SEC

MIN (q) COMPUTER

E

=

4.0 14SEC

MAX (q) PERIPHERAL DEVICE

0.2 14 SEC MIN

(ci)

PERIPHERAL DEVICE

NOTE:
THE ADDRESS alTS WILL BE ON THE CHANNEL A MINIMUM OF
0.1 14 SEC BEFORE AND AFTER THE READ OR WRITE SIGNAL.

Figure 4-9.

89633300 A

A/Q Channel Timing

4-49

Vee

OUTPUT
LINE

I

~

204

1
1

180

I

146

1

204

~

Vee

INPUT
LINE

1

180

146

Vee
.,-

I
I
I

: 180
~

1

204

~

I

BI-DIRECTIONAL
LINE

I

I

i

I

I

I

.A
I

146

1
I

I

I
I
I

COMPUTER

l!..

I

I

I
I

I

8ACKPLANt

A

204

I

••
•

PERIPHERAJCONTROLLER

146 can be replaced by any TTL logic circuit gate
providing that the line is loaded by only one load unit.

Figure 4-10.
4-50

146

I

CONNECTIONS

NOTE:

I

1

A/Q. Channel Input/Output Lines
89633300 A

INTERRUPTS
There are 15 external interrupt positions provided, each brought out on an
individual backplane pin.

These are used to interrupt the computer program

on specified conditions arising in the peripheral devices. The computer
program determines the interrupt priorities, that is, the order in which
the interrupt requests are ·dealt with in the cqmputer. The program acts
th-rough the computer mask (M) register. Should two interrupts occur
simultaneously, the hard-wired order of interrupts will determine priorities
(refer to table 4-5).

Interrupt Access
The 15 external interrupts are accessible on the backplane pins of the main
enclosure. A single wire (part number 89724702) is required to connect
an interrupt source to the appropriate interrupt level.

I

Table 4-5 lists

the pin assignments for the interrupt levels. Interrupt signals are active
low.

See section 3 for the installation procedure of the interrupt cable.

For the interrupt connections for controllers installed in the BTl48 expansion enclosure, refer to Hardware Maintenance Manual publication number

I

89758600 of the AT310 TTL A/Q-DSA Bus Expander.

89633300 F

4-51

TABLE 4-5.

Line

INTERRUPT ACCESS PIN ASSIGNMENT
AB107/AB108
Card Slot

Pin

o
1
2

3
4
5
6
7
8
9
10
11
12

13
14
15

25
25
25
25
25
25
25
26
26
26
26
26
26
26
26

P1B10
P1A07
P1B07
P1A05
P1A06
P1B06
P1B05
P1A10
P1B10
P1A07
P1B07
P1A05
P1A06
PI B06 ,
P1B05

NOTE: Interrupt priority levels are in reverse
order of interrupt line numbers.

'---------_.,- -------------"

4-52

89633300 F

Timing Considerations for Two Bank Operation
The computer can have one or two memory banks (see paragraphs on Memory
System in this section), each with a maximum of 32K words. The two banks
work independently. Any memory request using an address of 7FFFl6 or less
will access the lower bank. Any memory request using an address of 8000 16
or above will access the upper bank.
logic.

The two banks have identical control

Each bank can perform three types of memory cycles: refresh cycle,
DSA cycle or CPU cycle. The DSA has priority over the CPU and refresh cycles
have priority over the other two. DSA and CPU cycles are initiated by
external signals while refresh cycles are initiated by internal timing logic.

If the CPU accesses one bank, the DSA can simultaneously access the other
bank. In this case, the CPU and DSA can work at maximum speed subject to
refresh cycle requirements.
If the CPU and DSA access the same bank, then memory cycles are shared
between them. If the CPU requests a memory access while a DSA cycle is
in progress, it must wait until the DSA cycle is fin·ished. If a refresh
cycle is pending when the DSA cycle ends, the CPU must also wait for that
refresh cycle to be completed.
Similarly, if the DSA requests access while a CPU cycle is in progress,
it must wait until the CPU cycle is finished. If a refresh cycle is
pending when the CPU cycle ends, the DSA must also wait for that refresh
cycle to be completed.

89633300 A

4-53

Successive DSA cycles: if a DSA cycle is followed by another one within the
maximum delay specified after the start of RESUME (see Figure 4-8, note 2)
and the CPU is waiting to reference the memory, then the second DSA request
will be taken and the CPU forced to wait.
gives the DSA priority over the CPU.

This is because the memory system

Thus the DSA can obtain continuous

memory cycles and block CPU memory accesses by sending memory requests at
a high enough rate.

This does not apply in two bank operation because the

CPU can access the upper bank while the DSA sends a request to the lower bank.
If the DSA then tries to access the upper bank it has to wait until the
CPU access ends.
The DSA can unconditionally block all CPU memory accesses with the signal
PRIORITY.

This allows the DSA to access both banks at maximum speed,

except when it has to wait for a refresh cycle.
Note that the speed of data transfer is a function of the computer clock in
the Timing circuits.

This clock is 1.5 times faster in the ABI07 equipment

than in the ABI08 allowing proportionally faster DSA access.

4-54

89633300

A

POWER SUPPLY
The followtng paragraphs descrfbe the functions and organization of the power
supply untt.
The power supply unit is part of the main computer enclosure
(~quipment ABI07/ABI08) and the expansion enclosure (equipment BT148)
Detailed circuit and connection diagrams are given in Section 5 of this
manual.

I

ELECTRICAL
The power supply receives the main line-voltage through the three-conductor
flexl'ble power cord which plugs in the socket at the rear of the
enclosure. The At POWER switch and input fuse are located adjacent to the
input socket (Figure 2-1). 'The power supply unit provides all the operating
supplies for the equipment within the enclosure, including the charging and
protection circuits for the backup source, Memory Hold Battery, equipment
GD61 I-A.
The supplies,with brief characteristics, are listed in Tab Ie. 6-1.
ac line specifications are as follows:
or

Note:

The input

104 - 127 vac, 49 - 60.6 Hz, single phase, up to 600 VA
198 - 264 vac, 49 - 60.6 Hz, single phase, up to 600 VA

the equipment is normally supplied for nominal Il0V operation.
It can be field converted to nominal 220V (refer to Section 3).

89633300 F

4-55/56

I

(

MECHANICAL
The power supply unit is mounted on the hinged front door of the computer and
expansion enclosures (Figure 3-2).
Access to it may be obtained by opening the
front door of the enclosure.
It is cooled by a blower mounted immediately
beneath it (in the door).
The power supply may be field calibrated (refer to
Section 6).
The memory hold battery (equipment GD611-A) when installed, is situated on the
inside of the equipment rear cover.
The battery fuse is part of the input
circuit situated at the rear of the enclosure (Figure 2-1).
WARNING
The power supply does not use a main isolating line-transformer
at its input; its circuits between the ac line input and the
isolating networks are therefore at line voltage.
Do not handle
the power supply unit while the computer line cord is connected
to the ac supply.
GENERAL DESCRIPTION AND BLOCK DIAGRAM
The power supply unit is described below, the explanation being based on the
simplified block diagram of Figure 4-11.
More detailed block diagrams follow.
Detailed circuit diagrams are given in Section 5.
The ac input power is taken to the computer enclosure through the power line
cord.
This plugs into the ac power socket of the Input Unit mounted at the
top rear of the computer enclosure (Figure 2-1,3-5).
The Input Unit contains
the computer main circuit breaker (AC POWER switch), the input fuse (FI), the
battery fuse (F3) and the line filter.
Note that the input unit is not part
of the power supply unit.
The computer chassis (frame) is connected to the third conductor of the line
cord; the conductor must be connected in turn to the ground (refer to Control
Data Mini Computer Systems, Site Preparation Manual, publication number 60437000).
The logic ground is brought out on a separate pin and should be connected to the
logic ground of the installation (refer to Section 3).
The equipment is switched on in two stages:
,
,/

first the ac line power is applied

to the power supply unit of the enclosure by switching ON the AC POWER switch on
the rear panel (part of the Input unit); in the second stage the power supply
unit is activated by turning on the dc POWER switch on the Programming Console.
89633300 A
4-57

0&:I

V'I

at

-.

AC to DC Converter
VC C R.gulotor

'"T1

IQ

.,
c:

(II

0&:I

+ 35v Prer'gulator

AC~

f'4--AC Lin.
Cord

"'0

i

(II

c:

t---

Logic

35vac

-

*

auxiliary

R•••,.,...

25vdc

"

auxiliary -7vdc

~

VCC 2
-12v

-5v

>Cha....

~

Prot.ctlon

Circulta

"C
"C

-

~

'------=---..-...-.."

Ground

VI

t:::::::~1~::::::::=:::Jr=::::::::=t1:3~:~: ~
VCC

35vdc
Input
Ciroult

r-s

L--_ _~)

.,

--

---

ov.rcurrent

Vee

+30v
Unl'8Qlllated

---r- ;'-f;;;;;'--

Referenc.

Generator

~------~---~-----------------~-------------------4~)r---~

'<

-SENSE
From back plane
grotIId t.,..lnal

(I)

:I

"C

Battery
Charg.r
and Battery
Crowbar

+ S.nse
from
VCC

"""
(II

a.

bock "one
T.rmlnal

CD

?

0

n

~

.,
10

AJ

IQ

Note:
Th. ..ain
indloat.d

[!]t

power flow ia
by t.ick lin••

at

*"

\D

~

Tile Input Clroult ia not
port of tit. Pow.r Supply
Front Panel
DC
POWER

\oil
\oil
\oil

0
0

Batt.ry
F3

Batt.ry

AJ

:I

Isolating
Diod.

'i--~
-=

I

Fus.

Equipment
GD611-A
(Optional)

'='

»
""....

.,-'--"~

~.::""

The main source of dc power is the ac-to-dc converter.

This provides the main

unregulated logic supply of the computer (V
(+35V, +25V, -7V).

) and the internal auxiliary supplies
cc
The circuit uses a high frequency switching regulator to

generate Vcc •
This circuit serves as preregulator for the other suppl ies which
are derived from the +35V supply through the regulator section.
Closely associated with the converter are the overvoltage and overcurrent
protection circuits which switch off the whole of the unit, should preset fail
conditions be exceeded on anyone of the suppl ies.

One of the auxil iary

independent suppl ies (+25V) provides the voltage for the reference generator
of the regulators to aid in operation of the circuits on switching on.
On failure of the ac line power the +35V internal supply fails and the backup power
source, optional memory hold battery equipment GD611-A (if installed), suppl ies the
regulators througn an isolating diode, connecting it to the +35V I ine.

In this case

the computer switches to Low Power Data Retention (LPDR) mode of operation and only
the memory power suppl ies are active.

The LPDR operation is described in paragraphs

on the operation of the Memory in this section and in Section 5.

Note that the

front panel DC POWER switch must remain ON during LPDR operation.
The battery charge circuit charges the memory hold battery during normal
operation of the equipment.

The battery is protected by its fuse both against

excessive charging current and against overload.

The battery fuse is blown

also through the battery crowbar (SCR) circuit when an overvoltage is detected
on anyone of the power supplies used during emergency (LPDR) operation.
The front panel dc POWER switch controls the power supply:

with the rear

panel AC power ON, the DC POWER switch disables the power supply circuits
when off and enables them when on.
The AC-to-DC Converter and Protection Circuits
Figure 4-12 shows the block diagram of the main dc generator circuits with their
controls and the power supply protection circuits.

89633300

A

4-59

.
>

r--

------1

~I--~

!I-i t
I

1

I

L________ - ____ J

i

i

£

i+
!

,..-&----""""""""

t
.- -----,,+----il--=f
Sl

III .
I~

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,
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1

I

+---+1_ - I

r-I ---- --JI

~~=I

I

~ill

I
I

I

r- ---- --i

I

1

:1;;1

~il
L _______

Figure 4-12.

4-60

I

+

J

I

,n

AC-to-DC Converter and Protection Circuits:

Block Diagram.

89633300 A

A feature of the power supply main power path is that the main isolating
transformer works at a frequency of about 20 kHz. Its bulk is therefore
drastically reduced compared to the input transformer of a more conventional
solution working at 50Hz. The line rectifier is connected directly to the ac
input line and its slightly filtered dc output taken through a voltage regulator to a 20kHz inverter. The isolating transformer can handle substantial
powers in a small volume because of its high frequency of operation.
This frequency allows also high efficiency final filtering with comparatively small components, resulting in a dc output with very small ripple-content.
The technique of employing an isolator removed from the direct input makes
it necessary to employ small isolators in the control paths. Signal transformers serve in the alternating and interrupted current paths, and an optical coupler is used where the coupling signal is dc (switching regulator curcurrent sense circuit).
The main switching regulator regulates the logic supply (V

). Its control
cc
reference voltage from the reference generator to

circuit compares the V
cc
the V voltage sensed at the computer circuits. The regulator therefore comcc
pensates both for input and for load changes on the V line. As this carries
cc
typically 35 amperes, the load regulating feature with remote sensing is
particularly important. The remote sensing points (+ SENSE, - SENSE) are at
the backplane of the enclosure.
The switching regulator serves as a preregulator for the +35V and -7V internal dc suppl ies, though load changes on the V supply will show as regulation
cc
noise on these. As th~y feed the final regulators, this noise does not appear
on the power supplies, except the +30V unregulated supply.
An auxi Ii ary supply ( +25V) is generated by a conventional line transformer
and recti fier fi 1 ter di rectly from the ac line input. This supply is used in
the reference generator and the regulators which get their supply from the
+35V line: when the ac line is applied to the computer (AC POWER swi tch on
the rear of instrument) this connection allows the regulators to stabil ize
before the front panel dc POWER switch enables the circuits in the main power
path. The auxiliary supply is protected by a separate fuse (F2: 100mA).

89633300 F

4-61

I

The Low Power Data Retention (LPDR) mode of operation is initiated when the
main logic supply (V ) fails, due to anyone of several conditions (see
cc
Protection circuits below). The failure of the V supply is sensed in the
cc
Power Failure Detector by the absence of the switching signal to the Vcc
switching regulator while the front panel dc POWER switch is ON. During LPDR
operation, only the circuits are supplied which are needed to retain the
content of the memory withi.n the enclosure, provided the power back-up
s~urce (memory hold battery, equipment GD611-A) is installed (refer to paragraphs on memory operation in this section). To avoid hunting on momentary
recovery of the ac supply, the power recovery delay allows the computer to
return to normal operation only when the ac supply has been established for
some seconds. Note that the power fail detector is actuated also by failure
of the switching regulator control circuit: when the duty cycle of the
switching regulator tends to 100% (continuous current) the power fail detector initiates an LPDR signal.
Protection Circuits
The power supply is protected against both overvoltage and excess current.
Over-current occurrring on anyone of the supplies, the whole power supply
shuts down. When an overcurrent condition occurs in the main power path, the
main voltage regulator (switching regulator for V ) is shut down. This is
cc
done by stopping its switching signal through the overcurrent protection
.circuits. Should the overcurrent condition last for more than one second,
the overcurrent latch reduces the voltage of the switching regulator and so
activates the power fail circuit. The overcurrent latch is set also if any
of the circuits in the regulator section detect an overcurrent condition.
In this case, the LPDR mode of operation is initiated.
If the overcurrent protection circuit fails to shut down the main power path,
the crowbar drive is activated directly through its isolating transformer
and so fires the SCR of the main crowbar circuit. This in turn blows the
main fuse (Fl). Each of the supply voltages is connected to the overvoltage
detector. Should a preset voltage be exceeded on anyone of the supplies,
the! detector actuates the crowbar circuits, which in turn blow both the
ma in fuse (Fl) and the battery fuse (F3).

4-62

89633300 F

Regulators and Control Circuits
The computer supplies, other than the main logic supply (V cc )' have individual
control and regulator circuits.
TABLE 4-6.
Supply
Designation

Table 4-6 summarizes these.

SUMMARY OF REGULATED POWER SUPPLY CIRCUITS
Type of
Regulator

Overcurrent
Detector

Supply
from

Vcc2

swi tch i ng

yes

+35V dc

VSS

switching

yes

+35V dc

VBB

series

no

+35V dc

-12V

series

no

35V ac

- 5V

ser i es

yes

-7V dc

+30V

none

yes

+35V dc

Figure 4-13 is a block diagram showing these circuits.

I

All regulators receive

their reference voltage from the reference generator,except the VSS supply, whose
reference is a tap of a potentiometer divider on the VBB supply.
The reason
for this arrangement is that the memory unit bias and supply voltages must be
applied together and at a definite differential between them ,to avoid possible
overheating of the unit.

Note that the +30V supply has no regulator but relies

on the regulation from the V regulator acting on the +35V internal supply.
cc
The reference generator uses the sense line (the remote computer logic ground, -SENSE)
as its reference ground, thus compensating for current in the ground circuit
between the power supply and the computer.

The reference generator is actuated

as soon as the AC power switch on the rear panel is switched on.

It is thus

stabilized whenever power is applied to the computer and is ready for operation
as soon as the front panel dc POWER switch is thrown ON.

89633300

F

4-63

..l:-

3ISvac

0'

-I'"

I

..I:-

--

+ 3!5v Lin.

(+30V)

I-...

Aaxlllary+2lSv

Front Pan.'
DC pow.r

-

L

R.f.r.no.
len.rator

~

To VCC
R.gulator

-

-!-

CompUt.r Logic Ground

.....

f-o-

--

Serlll
R.gulator
(-12v )

--

......

I
I

~

...... Swltohlng
R.gulator
...... (VCC2)

1 C....

+ 30v

Ov.rourrtnt
D.t.otor

...... VCC2
~

---. Vaa

SwitChing
R.gulator
(Vaa )

:

VSS R.f.renoe

L
~

--&
0'

IoN
IoN
IoN

o
o

."

Auxiliary -7 vdc

......

-12 v

r

"=~

Switching
R.gulator
(VSS)

Strl..
R.gulator
(-Dv)

Vss
~

-lSv

....-

...

To Curr.nt
Lllait Circuit

Figure4-l3. PoWer Supply Regulator and Control Circuits: Block Diagram (see also page 5-448)

The Switching Regulator
Figure 4-14 illustrates the basic principles of the voltage conversion circuit
which is at the heart of the switching regulator.
transistor in the main load path.

Transistor QI is a switching

It is switched on and off by a pulse wave-

form generated in the switching network.
The voltage and current waveforms are shown in part b of Figure 4-14.

This

voltage is smoothed by the LC filter to give dc output with very little ripple.
~iode

b

DI is a catching diode to complete the inductor circuit when the transistor

off.

The output voltage of this circuit is thus the average of the switched waveform
VO:
t

V

out

= Vin..2!!.
T

and it is substantially independent of the load current.

The dissipation in

the transistor is determined by the difference in input and output voltages and
the load current, as in a series regulator, but is reduced by the duty cycle
factor (t on It 0 ff) compared with the conventional series regulator.
The output
voltage can be changed for a particular input by varying the duty cycle of the
switched haveform.

89633300 A

4-65

Output
(V )
out

Input
(V

IC· - Vo

QI

)

in

L

IL

----o

r4---_ _-._--.J"'Y"V'Y'\---t..

01

Switohlng
N.twork

t

a. Switclling

regulator:

C

10

INIllc circuit

-ICI

10

Col/ector current

id d
hD t

tlml
~Iode

ourrent

time

IO~ _ _ _ _ -

Induotor curr.nt
tltne

Oiodl Voltage

time
Diode Forward

Voltagl Drop

b.

Swltoh/n, Rlgulator: Waveform.

Figure 4-14.
4-66

Switching Regulator:

Basic Circuit and Waveforms.
89633300

A

SECTION 5
DIAGRAMS

SECTION 5

INTRODUCTION
This section carries the explanation of the detailed logic and circuit diagrams
r~lating to equipments AB107/AB108 and BT148.
These equipments are described
in Section 1 Qf this manual; their theory of operation is given in Section 4.
The explanation is grouped in functional units, as follows:
Functional Group

Ci rcu it/Boa rd

5-20

Memory System
Memory Module (equipment
BA201-A or BA201-B)
Memory Controller
Memo ry Add res s
Memory Control
Central Processing
Unit (CPU)
Programmer's Console
Arithmetic and Control Unit (ALU)
Decoder
Timing
Input/Output (I/O) Interface
Console Interface
TTY Controller
Power Input Circuit
'Power Supply Unit
High Power (HP) and Control
Low Power (LP) Board

89633300 F

Page

5-21
5-45
5-81
5-141
5-143
5-167
5-211
5-241
5-291
5"337
5"373
5-424
5-427
5-436
5-461

5-1

I

Notes:
1.

All units, except the Power Supply assembly and Programmer1s Console,
are mounted in slots in the main body of the enclosure (refer to card
placement slot assignment, pages 5-6, 5-7). The order of the explanation follows the reverse order of slot assignments.

2.

The Memory Controller, (consisting of the Memory Address and Memory
Control boards) as equipment BU120-A is installed in the BT148 enclosure.

3.

The calibration of the Power Supply unit is different in the AB107 and
the AB108 equipments. The following table gives a summary:

I
I

EQUIPMENT

I
I

ABlO7 and BT148 connected to it
ABlO8 and BT148 connected to it

CAL I BRATI ON
VSS
VSS

= +16.7
= +19.7

V
V

This information is given in other parts of the manual as required. See
the Diagnostics and Margin Tests on page 6-7.
The diagrams, together with their latest revision status, are listed in
the Revision Correlation Sheet. The diagrams themselves are not bound in
this manual, but are packaged separately.
An explanation of symbols used in the diagrams is given in the Key to
Logic Symbols and Signal Flow.

5-2

89633300 F

KEY TO LOGIC SYMBOLS

Publication 89723700 (Key to Logic Symbols) or equivalent, lists the symbols
used in the logic diagrams in this manual and gives a short description of the
functions they represent.

The symbols

confo~m ~enerally

to Control Data usage

(Microcircuit Handbook, publ ication number 15006100), using the polarity logic
convention.
The following paragraphs describe the signal flow conventions used.

SIGNAL FLOW
Input signals are drawn coming from the left or above;

output signals are

drawn going to the right or down.
The signal lines are sometimes interrupted to allow logical grouping of
components and to avoi d long lines.
following indicators is used:

At each such. interrupt ion one of tne

On-Sheet Continuation

Referen~e

Symbols

These symbols when used with the logic
symbols in the following diagrams indicate
that a connection exists bet\'/een two points

~-

on a sheet.
The arrows attached to each
circle point from signal origin to signal
The letters, C, H, I, 0
destination.
and P are not used inside the circles,
since they bear special significance on
logic diagrams.

89633300 A

5-3

Off-Sheet Continuation Reference Symbols

SHEET 2 )

( ON

These symbols when used with the logic
symbols in the following diagrams
indicate two sheets in a series of
related drawings. These symbols point
from output to direction of input as
shown in the illustration. The number{s)
next to each hexagon indicate the
sheet{s) that the signal is continued
from or on. For instance, the numbers
3.6 refer to sheets 3 and 6, while 2.3
refers to sheets 2 and 3. It should be
noted that the referenced sheet number{s)
is always placed opposite the line
extending from the hexagon.

-------@3.6

(ON

23

SHEET

6)

(!)~------

SHEET
OFF-SHEET SIGNAL-'
,
REFERENCE
2 3 4
LETTER
A
BIT3 O-r
I

B

BIT2

C-r

C

BITl

B-r

0

BITO A-r

E

PTAOO 0-2 0-2

F

Q,TAOO 0-2 0-1

G

KTAOO 0-2 0-2

------ -HTAOO

5-4

A-2
--_..... --_D-2
..............

5
,
;

,
;

....

The interconnections are listed in an
Off-Sheet Reference table in the logic
diagrams. This table gives the location
of the off-sheet reference on each sheet
and generally indicates the signal on
which the signal originates (Y). The
. signal name at the interconnection is
~lso generally given in the table when
ava ilabl e.

.

89633300 A

Test Points
The test point symbol on the logic diagram
shows the connections of a test point on
the printed wiring board (PWB). The number
adjacent to the symbol refers to the test
point position on the PWB at the edge
opposite the connectors. Only test point
number one is labeled on the edge of the
PWB, the other test points are numbered
sequentially.
CONNECTING
LINES

NON -

CONNECTING
LINES

Connecting and Non-Connecting Lines
Lines eonnected to a common point or at a
junction point are shown in the upper part
of this illustration. No more than three
lines are normally connected to a common
point in the diagrams.
Lines crossing but not connected are shown
in the lower part of this illustration.

Connectors
All PWB connectors are sockets (female) and are shown as such. The name of the
signal is placed in the open end of the connector symbol (shown below), using
the full name of the signal or the common abbreviation applicable to logic
diagrams. The connector number, pin row and pin numbers are located above the
line extending from the connector symbol. Refer tQ Input/Output specification
manual publication number 89673100 for an explanation of the mechanical
location of connector pins.

r---------------- SIGNAL NAME
r-------------- CONNECTOR NUMBER
, . . - - - - - - - - - - PIN
PIN

r---------

89633300 A

ROW
NUMBER

5-5

V1
I

'"

illI

AQ BUS

TIMING,

MEMORY CONTROL
MEMORY ADDRESS
X

III

::J

n

III

Co

n

-a

a

III
0

0

."

s:

I I I 11 11

.,

EIGHT
MEMORY
MODULES

(II

., i::J
r1'

I

'O

I

,

f

I

TTY CONTROLLER

I 1111 1111 I I I I I
CENTRAL
PROCESSING
UNIT

(II

r1'
fTI

::J
0

(I)

0

r1'

en·

.,s:
(II

J:

INTERFACE
CONSOLE INTERFACE

CARTRIDGE
DISK
DRIVE
CONTROLLER

S .. .. i

0

z

~

>
en
en

iii
=-

IC

III

n

i

~

g
~

ii
-c

_ZI
PHAIE
MMNETIC
ENCOD' TAPE
'INI
TRANSPORT FORMATCONTROLLER TER

c

Ji

=- =-

0

n

z

~

g

z

~

III

~
:.-

:-t

I

DSA IUS

n

AQ IUS

'I I r

,

n

I i
~ -4
• '0,..=-

::J

i::J
r1'

56 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20

..

I. 17

•• 15

14 13 12 II Id

•• •
7

5 4 3 2 I

co

NOTES

'"

1.

The Memory Control assembly and the Memory Address assembly together form the Hemory
Controller.
This is similar to equipment BU120-A in the Expansion Enclosure.

2.

See Section 1 for definition of equipments.

\D

w
w
w
0
0

>

DSA BUS

&

MEMORY

'"
w
w

CONTROLLER

I
~
'I I I' I {'QBUI
/Q

A/Q BUS

DSA BUS

l~ TTl'
1
I

w
o
o

."

I

OPEN

EIGHT
MEMORY
MODULES

BUS

D8A BUS

I
OPEN

OPEN

I

I

I

I

ae Ia8

I NOTES

VI
I
'-J

~4

33 32

~I

30 29 28 27 2E 2!5 2"'1 23 22 21 20 19 18 17 18 16 14 13 12

-

"

10 9 8 7 8 5 4 3 2

I

1.

The Memory Control assembly and the Memory Address assembly together form the Memory

2.
3.

Controller, equipment number BU120-A.
See section 1 for defi~ition of equipments.
Slot 25 is provided with an additional connection to logic ground at 25P1A03.
Slot 26 is provided with an additional connection to logic ground at 26p2B06.

Card Placement Slot Assignment - Expansion Enclosure

DIAGRAM REVISION CORRELATION SHEET
The following is a numerical list of the logic diagrams (prefix LD) and the
wiring diagrams (prefix WD) included in section 5, with the revision status
for revision F of this manual. See the table of contents.
NUMBER-REVISION
WD 89601601 - A
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
WD
WD
WD
LD

I

5-8

89614300
89614900
89615200
89615502
89616400
89616400
89616400
89616400
89617000
89618800
89619100
89619700
89640500
89640501
89640502
89640800
89657700
89762200
89911800
89942600
89982800

...

A

A
A
E

J
H

G
F
A

B
C
A
B

A

A
D
B

05
B
A

A

NAME
Power Supply Wiring
Arithmetic Logic Unit (ALU)
Decoder
Memory Address
Memory
TTY Con t ro 11 e r
TTY Controller
TTY Controller
TTY Controller
Timing
Console Interface
Memory Control
Input/Output (I/O) Interface
Programmer1s Console
Programmer's Console
Programmer1s Console
LP Card - Power Supply
HP Control Unit
Power Supply Input-Output Wiring
Power Supply Wiring
Power Supply Input-Output Wiring
Anti-Bounce Circuit

89633300 F

I

"Pages 5-9 to 5-18 are unass i gned."

89633300 F

5-9/ 5-18

MEMORY SYSTEM
The memory system consists of the printed wiring assemblies (PWA' S) listed
in the following table:
Des i gnat ion

Slot Location

Remarks

Memory Module

29 through 36

Memory Address

28

)

Memory Control

27

)

Equipment BA201-A or BA201-B
) Memory Controller System PWA' S

Notes:

I

1.

The slot allocation is identical in equipments AB107/AB108, BT148.

2.

The Memory Controller system in the expansion enclosure is equipment
BUI20-A.

It is similar to the Memory Controller used in equipments

AB107/AB108.
The memory timing is shown in figure 4-6 and in the timing diagram associated with sheet of the Memory Control assembly.

896333QO F

5-19/ 5-20

MEMORY MODULE
The Memory Module circuits are accommodated on a single 50-PAK printed
wiring board.

The logic circuit diagrams are given in drawing number

89615502, sheets 1-8.
The equipments, BA201-A and BA201-B are both designated Memory Modules. The
difference in function between the two equipments is their speed of operation
expressed in terms of the memory read/write cycle time, as follows:
Memory Module
Equipment

Cycle Time

BA201-A

600 nsec

BA201-B

900 nsec

Accommodated in
Equipment

I

ABI08, 8T148
ABI07, BT148

The memory module,as part of the memory system is described in Section 4
of this manual.
The principles of operation and circuit configuration of the two equipments
are identical.

The component memory units they util ize are similar and

differ only in their speed of operation (refer to Section 4'of this manual
for detailed operation and timing).

Changes in the values of other components

between the two equipments are noted on sheet 1 of drawing 89615502.
The memory module block diagram is described in Section 4 of this manual.
Detailed circuit diagrams are given here.

The circuits are repetitive and

for bits I through 16 they are identical.

Only one circuit diagram is given

therefore and it is supplemented by tables defining each component.
The level shifters and other circuits which make up the memory module are
described in the following.

The memory unit is described in detail in

Section 4. Its terminal functions are summarized in the following diagram.

89633300 F

5~1

AO

ROW

AI
A2
A3

SELECTOR
SIGNALS

A4
A5
A6
A7
AI

COWMN
SELECTOR
SIGNALS

A9

RIW
·PRECHARGE(PCH)
CENAB LE (CE)

3

512 X.Y

4

2M
2 128
I
64
15
32
8
16
I
9 4
13 2
6 I
181\

.,

51\
161\

-,.
a

..

AOOOO
A 1023

G2
!II

I>MEM
DATA

IN

12_A2CD
I'

AI.2:,"14

DATA OUT

SUPPLIES
SUPPLY

VOLTAGE

TERMINAL

VIS

+19.7V(8A20I-A)
+16.7V(BA201-B)

17
17

V.

VSS +3V

10

VDD

GROUND

II

Memory Unit External Connectors

5-22

89633300 F

MEMORY MODULE

(d rawing 89615502, sheet 5)

. Level Shifters: TTL to MOS
TTL logic levels are 0.7 volts (low) and 2.0 volts (high). MOS levels are
approximately zero volts to VSS (16 volts). A level shifter is needed to
match the two kinds of logic circuits. The following signals use identical
level shifters:
Precharge, Read/Write (R/W) and Address
These level shifters are common emitter push-pull inverting amplifiers, using
four transistors. They accept TTL input and provide an output to drive MOS
circuitry, that is, they drive a 300 pf load in 45 nanoseconds. Two capaci~
tors are used to speed up the operation. The use of -5V and +z8V power suppl ies improves delay and rise-fall times. See page 4-34.

I

The Cenable 0, 1,2,3 signals use the above type of level shifter, but with
two components added: a 470-ohm resistor and a type lN4151 diode. The resistor
and diode are connected for the Cenable level shifters only. To indicate this,
they are drawn in dashed lines in the circuit diagram below.
In logic drawing 89615502 sheet 5, the 470-ohm resistor is marked RE and the
type lN4151 diode is marked CRB.
+28V

Vss

IN41D1

TTL
INPUT

,--470 ~

M.O.S LEVEL
....-~OUTPUT

I1_ _ -

-IV

TTL to MOS Logic Level Shifter Circuit Diagram

89633300

F

5-23

MEMORY MODULE

(drawing 89615502, sheet 7)

Data-In Level Shifters
The level shifters for the data input to each memory unit is an open collector
inverter with a 1 Kilohm pull-up resistor to VSS.
The DATA IN (DIN) lines are
normally low.
When a DATA-IN line becomes active (high) during a write cycle,
the information on it is immediately valid.
The outputs of the data-in level
shifters have a fast fall time, but a comparatively slow rise time, making them
suitable for this signal polarity.

Vss
IK

X-IV

Data To

Data In 0 - - - - 1 200 ....- ............- ....- -...- - 0 Memory Uritl
(Terminal 12)

I

Data-In Level Shifter and Clamp

5-21J

89633300

F

MEMORY MODULE

(drawing 89615502, sheets 5,8)

The Overlap Circuit (Cenable - Precharge Delay)
One overlap delay circuit is in the precharge line of each kiloword unit
on the Memory Module.
It regulates the overlap timing tOVL and tOVH in
the memory units (see Table 4-2 and the Detailed Operation of the Memory
Unit), and consists of a diode switching network controlling an RC
delay circuit.
The circuit is shown belo~.
In normal operation Cenable at the output of a
level shifter is high, blocking diode 01 and so allowing a voltage of about
2 volts to develop on the delay network (Cl, R2). This voltage enables the
precharge output gate.
When the Cenable line is activated (gone low), diode 01 conducts and
blocking diodes 02, 03 isolate the delay circuit.
The voltage to the
precharge unit decays with the time constant of the delay circuit so
ending the precharge signal.

vees
RI
100

01

eenable
(HIGH • -leV,

To

Preoharge

LOW =0.7V)

Output eate

el

Overlap (Cenable-Precharge Delay) Circuit:
89633300 A

Circuit Diagram
5-25

MEMORY MODULE

(Drawing 89615502, sheet 8)

Low Power Data Retention
Between refresh cycle bursts in the Low Power Data Retention (LPDR) made
during a power failure, none of the TTL logic circuits receive power.
This circuit ensures that the Precharge and Genable signals do not activate
as the Vcc is switched "on".
It achieves this by keeping the enabling
inputs of the Precharge output gates low (at U9/6).

Bllp'

1.:--T....

VCC2

IK
68nF
2N 2907
220

MPWR

Vccs

o---------------~

IOnF

1"'

f

T

LPDR
CIRCUIT
OUTPUT
U9/6

10nF

Switched Supply (V ees ) and LPDR Circuit

The circuit senses that the switched logic supply (V ees ) dropped, and,
with a short delay, holds U9/6 low; when Vees rises, the circuit releases
U9/6, after a short delay.
The attack time of the circuit (the time
allowed between Vees dropping and U9/6 being held low) is 10 mill iseconds.
The release time is determined by the Disable signal: Disable will not
go active (low) for 1.6 milliseconds after MPWR is active {that is Vees
is active, thus the circuit has 1.6 milliseconds before it must release
U9/6.
5-26

89633300 A

MEMORY MODULE

(drawing 89615502, sheet 8, cont'd)

The main logic supply (VCC ) may fail during normal operation.
This will not affect memory operation If the optional back-up source,
battery equipment GD611 is installed. In this case the computer
switches to Low-Power Data Retention (LPDR) mode and to conserve
power the following TTL circuits are connected to the switched logic
supply (V CCS ):
-

Column address (A5 - A9)
Data-in level shifters
Data-out sense amplifiers

During intercycle refresh bursts, all circuits not directly involved
are switched off by Vecs' The outputs level of the shifters to
precharge, Cenab1e and R/W continue, however, to remain high.

Address Level Shifters
To avoid long transmission paths on the memory module assembly five
of the addresses, located far from the connector, have two TTL
Inverters instead of the usual one.

89633300 A

5-27

MEMORY MODULE

(drawing 89615502, sheets 3,4)

Sense Amplifiers
The data output (terminal 14) of the memory units appears on an open collector.
The output pins of corresponding bits of the four kilowords on the module are
wire-ORed to form the 18 output 1 ines of the Memory Module.
Each wired-OR is
taken through a 330 ohm resistor to ground which converts the current source
output of the memory unit to a voltage level.
This voltage level is fed to a
differential sense amplifier (receiver unit 162C) whose output is the D~UT line.
The other input of the receiver is connected to a reference voltage.
This
reference voltage is determined by the two resistors acting as a divider on
V
using Q92.
The value of the reference voltage (VREF) differs in the
cc
high speed and low speed units:
SA201-A:
SA201-B:

VREF
VREF

= 110 mV

=

50 mV

The data output is activated by the cell enable (Cenable) signal to the memory
unit.
The output of the sense ampl ifier is not enabled unless the STROBE is low
(during clocks 5 - 10) and the module was selected (M5X low).
When the
sense amplifier is not enabled, its output is high.
Pull-up resistors
located on the Memory Control assembly pull the

5-28

D~UT

lines to Vec.

MEMORY MODULE

(drawing 89615502, sheets 3,4)

VCC

STRflJBE-............
RI61

162C

VREF
I

RI60
15.4

....-4____ D fJ UT

MDX--......

....--24fo

-TERMINAL
OF MEMORY
UNITS

-

(DATA OUTPUT)

Equipment

Note:
BA201-B

BA201-A

R161

56.2 ohms ± 2%

27.4 ohms ±2%

VREF

50 mV

110 mV

Data-Out Sense Amplifier Circuit Diagram

89633300 A

5-29

MEMORY MODULE

(drawing 89615502)

PROTECTION AGAINST CATASTROPHIC FAILURE

Capacitive coupling circuit
The MOS-level signal, after the level shifter, is fed to the precharge
line on all memory modules.
This line includes a capacitive coupling
circuit, which protects the memory chips fr?m catastrophic damage.
Power dissipation in the chip is a function of precharge duty cycle.
If a precharge driver fails or remains active (low output) for too
long, the memory units may overheat and be destroyed.
However, with
the capacitive coupl ing circuit, the precharge is pulled up even if
the level shifter output continues to remain low.
The capacitive
coupling circuit does not slow down the precharge signal in operation.
A series termination resistor (22 ohm) connects the MOS-level signals
to the memory chips, after the capacitive co~pling circuit.
The
signals run down the 18-bit kiloword bus, connecting to each memory
chip.
The address lines branch into 4 groups, each running down a
separate 18-bit kiloword line.
A clamping diode is connected at
the end of each line to Vss to prevent the signal from exceeding VSS.
There is one diode for each kiloword line, that is, a total of 4 diodes
are located on the address lines.
For bit 17 (protect bit), the one physically closest to the level
shifters, the precharge signal is connected directly after the
capacitive coupling device without series termination.
This
decreases precharge overlap time due to line reflections, and
thereby decreases data output time for bit 17.

5-30

8963330Q.03

MEMORY MODULE

(drawing 89615502)

Power supply considerations
Between VSS and VBB the memory unit presents the equivalent of a
sil icon junction diode, which is reverse biased under normal
operating conditions.

During power supply turn on, VSB should
rise at least as fast as VSS and during operation VBB should

not fall below VSS.

To insure proper VBB regulation and to
guarantee these turn-on characteristics, VBB is generated by
regulating VSS at 3-4V below VBB . Because the memory unit draws
very little current from VBB protective series resistance used;
VBB is adequately bypassed to VSS at the unit, and level
shifters connected to VBB are connected to the power supply side
of the series resistance.

89633300 A

5-31

I
SHEET REVISION STATUS

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CIRCUITS lHOWN 011 THII SHEET AIlE IlVEII III THE TAiLE.
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IIPages 5-40 to 5-44 are unassigned ll

5-40/5-44

89633300 A

MEMORY ADDRESS
The Memory Address circuits receive the address buses from the DSA channel
and from the CPU and generate the addressing signals for the whole memory
system. They also generate the data parity and protect bits. The memory
data input is routed through this assembly, it also accommodates the switching
circuit for the switched +5V supply (V CCS ) used during LPDR (Low Power
Data Retention) operation.
This page lists the principal blocks of the Memory Address.

Its block

diagram is given on the next two pages.

THE MAIN FUNCTIONAL BLOCKS

t - - - - - - - - - - - - -_________ .....' ._________. . _._ .....
Shown on sheet

Des i gna t ion
Kiloword selector

2

Row selector
Co.1 umn se 1ec to r
Module selector
Data in: 16 bit data and parity generators
Data in: parity and protect bits

2

I

3
4

5
6

----------------------------____-L______________________

•

89633300 A

5-45

V1
I

.c:O'

MEMORY ADDRESS

The Memory Address circuits are accommodated
on a single 50-PAK printed wiring board. The
logic circuit diagram is given in drawing
number 89615200, (sheets 1-5). These pages
show the principal blocks making up the Memory
Address together with the main input and output
signals. Both the circuit and the signals are
described in detail on pages ~ssociated with
corresponding sheet of the circuit diagram.

CRQ.
SRQ.
CXP
SXP
RXA
CRt

HflJLD
HflJLDW
LflJADRA
ADVANCE

Address and Control
Lines to Memory

CPU (ALU) & DSA (SA)
Address and
Data Li nes
ALUOO, ALUOI
SAOO,

Ki loword
Selector

SAO I

IIKO
KI }

I K2

Kiloword
Lines

Selects one of
four ki lowords
on a memory module.

Address

I K3

ALU02 .. ALu06 5
~

SA02 .: SA06

~
CI)

\AI
\AI

SA07

t

SAll

ARAO
ARAI
ARA2
ARA3
ARA4
BRWRA

Column.
Selector

ACA5
ACA6
ACA7
ACA8
ACA9

5

ALU07, ALU08 .. ALUII 5
~

Row
Selector

5

Descrrption

Row Address Lines
(decoded in Memory Unit)
(5 ... 32)

Selects and latches
the memory row address
for DSA, CPU and
Refresh cycles.

Column Address Lines
(decoded In Memory Unit)
(5 ... 32)

Selects and latches
the memory col umn
address to the
memory ca rd.

~
o

»

Memory Address Block Diagram

(diagram continued on next page)

QC)

\D
0'

w

MEMORY ADDRESS

g

continued from previous page

w
w

»

AlUl2 f AlOI4~ Module
SAl2 t SAl4 ~ Selector ~ MDXO
Module Presence DXI
(first module is
a I\iI9Ys present)

t

DX7 ~7,

t

PU : fAlUOO t AlUI5 /16
Data
lLAlU08 f ALUIS
From DSA: SDOO f SDI5
~ 16
)V

Protect Bit}
from Memory

Address and Control
lines to Memory
t

MDX7

f

DINI5

JrHodule Address
llines

,

I Data-Inl

l~eDINOO

I

4

I

D~UT

Decodes the memory
module address and
selects one of eight
memory modul e
assemblies.

Data to Memory

Parity Generator Output

Parity
17 _ ...... Protect
logic

Description

DINI6
DINI7

Parity Bit 1...
Protect BitJr To Memory

PAR1~IMemory

DI7Jr

Selects data from
the CPU of DSA lines
and transm its th Is
data to the memory.

controJl:tO CPU for Parity Check
MXl7 = Protect
Register Status.
Generates the parity
and protects bits for
data into the memory.

\11
I

.r::-

......

Memory Address Block Diagram

...

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TOl.[R'AfiIIClS

MEMORY ADDRESS

(Drawing number 89615200, sheet 2)

KILOWORD SELECTOR
Function
This circuit selects one of four kilowords on a memory module.

Inputs
SIGNAL
ALUOO
ALUOI
SAOO
SAOl

CiP
SXP
HIJLDW
RXA
CRl

SIGNAL SOURCE/
CONNECTOR PIN
PlB12
P1All
P2A24
P2B25
P2B26
P2B28
P2A19
P2B27
U42/12

FUNCTION

} CPU address bits

LOCATION
SHEET SQUARE
2

} DSA address bits

CPU cycle selector
DSA cycle selector
Latch hoI d (Kiloword)
Refresh cycle selector
00FF 16 Address from CPU

2
3

D4
c4
D4
c4
B4
A4
C4
D3
D3

Outputs
IKO

m
TR'2
1K3

89633300 A

P2A28
P2B30
P2A26
P2A27

2
Kiloword Selector Signals
to Memory Module

J

2

D2
D2
C2
C2

5.-49

~EMORY

ADDRESS

. (drawing number 89615200, sheet 2, cont'd)

Description
U19 and U3 select and latch the first tWo DSA or CPU address bits. This is
achieved as follows (for timing diagram - clocks - refer to Figure 4-6) and to
the timing diagram associated with sheet 4 of the Memory Control circuits.
Between clocks 1 and 2.5 either
SiP (for a DSA cycle) or CXP (for a CPU cycle)
will be active low while HeLDW remains low.
This allows SAOO, SAOl (for a DSA cycle) or ALUOO, ALUOl (for a CPU cycle) to
pass through U19 and U3. At outputs U19/8 and U3/8 the signal is Inverted.
The signals are re-inverted and fed back into U19/1 and U3/1 in separate AND
gates U34/1, 2 and U34/13, 12 forming a latch. At clock 2.5 H'LDW goes high,
allowing U19/1 and U3/1 to pass through to the output (thus, the address is
latched). After clock 2.5 SXP and CXP will be high so that their corresponding
addresses can change without affecting the address that is latched. At clock
11 H'LDW goes down, losing the address-latch. The address is no longer needed
after clock 10 because the Disable signa] blocks the kilOWord selector on the
memory module assembly. Dropping the HeLDW signal at clock 11 decreases
through-put time for a new address. The address selector must be stable by
clock 1.5 of the next cycle when the Disable signal does not blook the kilOWord
selector on the memory assembly.
The signal CRI Is inverted and ANDed into the CPU address lines (refer to sheet
3). When this signal is active (high) andCX'P is active (low) and blocked,
ALUOO and ALUOl appear low; CRl is a signal used by the CPU to automatically
address location (00FF)16 in the. memory (second Index Register).
All inputs to U19 and U3 are active high.
active high.

This implies that SAOO, SAOl are

Outputs U19/8 and U3/8 are used by the one-out-of-four decoder (U17, U50) to
select one kilOWord of the memory module (lKO through lK3). The kilOWord
selector output is active low. If the memory system is performing a refresh
cycle, all the kiloWords of the module are activated.
The following tables summarize the operation of these circuits (in tables;
H = logic high, L = logic low).
5-50

89633300 A

MEMORY ADDRESS

(drawi nq number 8961-5200, sheet 2, cont I d.)

(m low)

DSA Cycle

Input
(Active High)
SAO I
SAOO
L
L
H
H

L
H
L
H

Output
(Act i ve Low)
lKO
1KI ·)K2
L
H
H
H

lKO
H

H
H

L
L

Refresh Cycle

Input

---

RXA
H

H

H

H
L
H

H

H
L

(m low)

CPU Cycle

Input
(Active Low)
ALUOI ALUOO
L
L
H
L
H
L
H
H
CRT (High)

H
L
H
H

I K3

Output
(Act i ve Low)
1Kl
lK2
lK3
H
H
L
l
H
H
L
H
H
H
H
H
H
H
H

(RXA high)

Output
(Act i Ye Low)
1Kl
IK2
1KO
L

L

L

lK3
L

The kiloword selector must be stable at clock 1.5 so that only one kiloword
will be activated by the Disable signal on the Memory module. Note that the
critical kiloword selector circuits use super-high speed TTL circuits.

89633300 A

5-51

(Drawing number 89615200, sheet 2)

MEMORY ADDRESS
ROW SELECTOR
Function:
cycles.
Input
SIGNAL
ALU02
ALU03
ALU04
ALU05
ALU06
SA02
SA03
SAo4
SA05
SA06
CxP
SiP
HflLD

'ERf
RXA
LiJADRA
ADVANCE

To select and latch the memory row address for DSA, CPU and Refresh

LOCATION
SIGNAL SOURCEI
FUNCTION
r:ONNt.l.IUK PIN
SHEET SQUARE
h
B4
P1B10
2
B4
P1A10
D2
Memory Address lines
P2A17
'from CPU
C2
P2A15
.,
B2
P2A12
B4
Pl BOl
B4
P1A06
D2
)Memory Address lines
P1B09
from DSA
C2
P1A09
J
B2
P1A21
B4
CPU cycle selector
P2B26
A4
DSA cycle selector
P2B28
B4
Latch hold (row, column, module 2
P2A25
D4
OOFF 16 Address from CPU
P1B22
3
2
Refresh cycle selector
D3
P2B27
2
Load Refresh Address
A3
P2A29
Advance refresh address counter 2
A3
P2B14

Outeuts
ARAO
ARAI
ARA2
ARA3
ARA4
BRWRA

5-52

P2B15
P2B22
P2A23
P2A21
P2B23
P2B29

2
I-

I

) Memory Row Address
Signals
I~

32nd Refresh Address count

2

B2
B2
Dl
Cl
Bl
Al

89633300 A

MEMORY ADDRESS

(drawing number 89615200, sheet 2, contld.)

Functional Description
The row latch selects and latches the DSA or the CPU addresses.
The outputs
of this latch, through the Refresh address Selector (ARAO through ARA4) , are
sent without decoding to the memory unit row address inputs (AO through A4).
The memory address inputs are arbitrarily wired.
However CPU and DSA addresses
must correspond, i.e., the CPU address must 'select the same location in memory
as the DSA address.
That is
AlU02
AlU03
AlU04
AlU05
Alu06

must correspond to

"

"
"

SA03
SAO 4

"
"

"
"

SA05
SA06

II

"

II

"
"

SA02

The DSA addresses are active high; the CPU addresses are active low.
When
CRI is active (high) the AlU address output appears as all zeros.
Although no
decoding is performed, (the 5 to 32 conversion is performed in the memory unit)
the latch does go through a Refresh Selector.
When a refresh cycle is being
performed, it is not the latch information that goes to the memory row address
but the refresh row address from the refresh address Counter (U33).

Circuit Description
The row refresh address is stored in a five bit binary counter circuit U33.
ADVANCE (P2BI4) advances the counter just before a refresh cycle is performed.
l8ADRA (P2A29) presets the counter so that BRWRA (P2B29) goes active (low)
BRWRA remains low only during the
on the 32nd count advance after l8ADRA.
32nd count.
The outputs of the counter are arbitrarily wired with one
exception.
The memory units save power if the memory row address bit A4
goes low to high after the last Cenable was inactive.

89633300 A

5-53

MEMORY ADDRESS

(drawing number 89615200, sheet 2, cont'd.)

This is very desirable for lPDR (low Power Data Retention) operation.
Thus,
ARA4 is wired so that it will often be low on the 32nd rapid refresh cycle,
and high after the 32nd rapid refresh is completed.
The row address information is taken through the Refresh Selector gates
(AND-OR gates U36/8, U35/8, U35/6, U51/8, U51/6).
The control inputs (U36/1
and U36/10 fO,r ARAO and correspond i ng termi na 1s on the other gates) are driven
from RXA and its inverse; RXA active selects a refresh cycle row address, RXA
selects the outputs of the DSA/CPU address latches.
This arrangement avoids
spikes on the row address lines (ARAO ~ ARA4) when changing from a DSA or
CPU cycle to a refresh cycle.

Row, Column and Module Selector latching
The row, column and module selector register share a convnon latching system.
This is described here.
The signals SXP, CXP and HelD from the memory control assembly ~re designed so
that spikes will not occur on the row, column or module selectors.
By
overlapping signals so that SXP (UI/8) and HelD on a DSA cycle or CXP (U2/6,8)
and HelD on a CPU cycle are never zero at the same time, the selectors will
not generate unnecessary spikes by blocking all the information lines.
HelD
overlaps with CXP (SXP) at the beginning of the cycle so that the new address
can be fed into the latch before the old one is finished.
CXP (SXp) overlaps
with HelD at the middle of the cycle assuring that the address is latched before
it is blocked.

5-54

89633300 A

..

~

til.

00

\D

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\AI
\AI

o
o

»

.

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,
V1
I

V1
V1

......

V1
I

V1

'"

DETAILED LOIIC DlAMAM
MEMOIIY ADDltESI

(drawing number 89615200, sheet 3)

MEMORY ADDRESS
COLUMN SELECTOR
Function:
SIGNAL

To select and latch the memory column address to the memory card.
SIGNAL SOURCE/
r.nIllN!"1

11'1

PIN

FUNCTION

LOCATION
SQUARE
SHEET

Inputs:
ALU07
ALu08
ALU09
ALU10
ALUll
SA07
SA08
SA09
SA10
SAll
CRl
CXP
HfJLD

P2A09
P1A28
P1A22
P1A27
P1B28
P1B23
P1B30
P1B29
P1A26
P1B21
P1B22
~2/8]

P2A25

3
Memory Address Lines
from CPU

I

I
i

I
I
I

;

I
I

i

,
;

,
Memory Address Lines
from DSA

!

;

,

!

1

I

00FF 16 address from CPU
CPU cycle selector
Latch hold (row,column,
module)

3
2
2

04
c4
c4
B4
A4
04
C4
B4
B4
A4
04
A4
B4

Outputs:
ACA5
ACA6
ACA7
ACA8
ACA9

P2B19
P2B17
P2B24
P2A18
P2B20

3
Memory Column Address
Signa 15

I
I
I

3

01
Cl
Bl
Bl
Al

Circuit Description
Note:
This circuit is similar to the Row Selector.
The column latch selects and latches the memory address from either CPU or DSA
address.
The output of this latch is sent without decoding to the memory chip
column address inputs (A5-A9). The memory address inputs are arbitrarily wired.
89633300 A

5-57

MEMORY ADDRESS

(drawing number 89615200, sheet 3, cont'd.)

However, CPU and DSA addresses must correspond.
The CPU address must select
the same locat ion in the memory as the DSA address for that location.
Thus:
ALU07
ALU08
ALU09
ALU10
ALUll

must correspond to
II

II

II

II

II

II

II

II

II

II

II

II

The DSA address inputs are active high.

SA07
SA08
SA09
SA10
SA 11
The CPU address inputs are active

low.
When CRI is active (high) ALU07 appears as low, and ALu08-ALU11 appear as
high.
During a refresh cycle there is no special information on the column address.
However, the lines are held stable during this time to reduce system noise.
The latching circuit is similar for the row, column and module selectors.
It is described opposite sheet 2.

5-58

89633300 A

Q)

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_

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DlT~LEII
LOBIC DIAIRAIII
II'IIORY ADOREII
~----------~--~----~1

I[

MEMORY ADDRESS

(drawing number 89615200, sheet 4)

MODULE SELECTOR
Function:

SIGNAL
Ineuts
ALU12
ALU13
ALU14
ALU15
SA12
SA13
SA14
CRI
CXP
SXP
HeLD
DXl
DX2
DX3

SIGNAL SOURCE/
CONNECTOR PIN

DX7

P2A16
P2B09
P2B16
P2B13
P1B27
P1A31
P1A30
[AG]
[AF]
[AE]
[AH]
P2AOl
P2BOl
PlB3l
P2Bll
P2B06
P2B05
P2A05

Outeuts
MDXO
MDXl
MDX2
MDX3
MDX4
MDX5
MDX6
MDX7
CAAl5

P2B03
P2A02
P2A04
P2B02
P2B04
P2B07
P2A07
P2A08
PlB19

i)Xq

DX5

i5X6

5-60

To select one of eight memory module cards.

LOCATION
SHEET
SQUARE

FUNCTION

4
!Memory Module Address
(from CPU

I

)

,I

I

I

,
I

i

I

Memory Module Address
from DSA
00FF l6 address from CPU
CPU cycle selector
DSA cycle selector

i

4
3
4
..

i

f

Memory Modu 1e
Presence Indicators

!
iI

.I
I

I

•

I
4
4
Memory Module
Signals

~elector

/

4

B4
D4
c4
A4
B4
D4
c4
D4
D4
D4
c4
D3
B4
A4
A4
A4
A4
A4
Dl
Cl
Cl
Cl
Cl
Bl
Bl
Bl
Al
89633300 A

HEHORYADDRESS

(drawing number 89615200, sheet 4, cont'd.)

Description
The module selector selects the address of one of eight memory modules according
to either the DSA address or CPU address, and latches it.
The CPU lines are
active low, the DSA 1 ines are active high.
The selector outputs are active
low.

If a memory module assembly is installed in the computer, it pulls the

DX1

signal corresponding to its location to ground. Otherwise the DX1 signal
remains high.
CPU and DSA addresses must correspond to each other. That is
ALU12
ALU13
ALU14

must correspond to

"

"

"

"

"
"

SA12
SA13
SA14

DXl refers to module 1 (the second memory assembly location) and HDXl activates
memory module 1.
The sign # (DX#) represents one of the memory location
numbers (1 ~ 7).

The first memory assembly location is always occupied.

No information is on the module selector during refresh cycles.

The REF signal

activates all the memory modules during a refresh cycle, so decoding of the
module selector is not necessary.
However, the module selectors remain stable
during a refresh cycle and no spikes occur on them.
This is a safeguard and
not strictly necessary since the REF signal provides timing on the memory modules
for the module selectors.
If all eight memory modules are installed the module addressed is the one that
is used.
If less than eight memory modules are available the module that is
used is selected by the storage-wrap around table, built according to
a)
b)

how many modules are available
which module is addressed.

Formulas for this are given below: 12, 13 and 14 refer to address bits ALU12,
ALU13 and ALU14 or SA12, SA13 and SA14.
The wrap-around table resulting is
also shown.

89633300

A

5-61

(drawing number 896J5200, sheet -4, cont'd.)

MEMORY ADDRESS
MDXO =
MOXl •
MOX2 =
MDX3 -=
MoX4 =
MOX5
Mox6
MOX7

-

-

(OX 1. 12)
(
12)
(OX3.12)
(
12)
(OX5.12)
(
12)
(OX7.12)
(
12)

(OX2.13)
(OX2.13)
(
13)
(
13)
(OX6.13)
(Ox6.13)
(
13)
(
13)

(OX4.14)
(OX4.14)
(DX4.14)
(DX4.14)
(
14)
(
14)
(
14)
(
14)

Storage Addressing Wrap-Around
STORAGE SIZE
(KWORDS)

STORAGE MODULE ADDRESSED

o 12

"
8

12
16
20
81

28
32
36
"0

""

"8
52
66
60
65

3 " 5 6 7 8 9 A BODE F

000 0 o
o1 0 1 o
o1 2 2 o
o1 2 3 o
o 1 23"
o 1 23"
o 1 23"
o 1 23"
o 1 23"
o 1 23"
0 1 2 3 "
o 1 23"
0 1 23"
0 1 23"
0 1 23"
o 1 23"

0
1
1
1

000 o 0
0 1 010
22012
2 3 0 1 2

"
5
5
6
6
5
5
6
6
6
5
5

"
"
6
6
6
6
6
6
6
6
6
6

"
5
6
7
7
7
7
7
7
7
7
7

0
1
2
3
3
3
3
3

0
0
0
0

9
9
9
9
9
9
9

0
8
2
2

0
1
2
3

"" " "" "
""

0 1 2
0 1 2
012
o1 2
8 8 8 8 8
8
8
8
8
8
8
8

0
1
1
1

6
6
5 6 6
6 6 7

8 8 8
8 9 8 9 8 9
A A 8 9 A A
A B 8 9 A B
ABOOOO
ABODOD
ABODEE
ABODEF

EFFECTIVE
MODULE
ADDRESSED

For example, if the computer has 16K (16,38410) words of storage,
the highest permissible address is 3FFF16.
If the program attempts
to address location 504016 (located in a nonexistent storage module 5),
it actually references location 104016 in module 1.
I

5-62

89633300 A

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I

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IK

1114
IK

1121
IK

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IK

VI
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MEMORY ADDRESS
DATA IN:

(drawing number 89615200, sheet 5)

16 BIT DATA AND PARITY GENERATORS

Function:
To select data from the CPU or DSA lines and transmit this data to
the memory.

SIGNAL

CONNECTOR
PIN

FUNCTION

LOCATION
SHEET
SQUARE

Inputs
SDOO -: SD15
ALUOO -: ALU15
SXA

DE
CMDR

DSA bus
ALU (CPU) bus
P2A20
P2B18
P2A06

DSA cycle selector
Data Enabl e

Outputs
DINOO -: DIN15
[U45/6]
[U41/6]
[U31/6]
[U2716]

I>

5

II
5
6

Data Input to memory

5

Parity Generator
Outputs

I
I5

B3
B4
B4

C4
C3
C2
Cl

Circuit Description
The CPU data enters the memory system on the ALU (ALUOa.;ALU15) lines.
These
lines, buffered and inverted, go to the address latches.
Because their polarity
is wrong for data to the memory, they must be inverted again.
The ALU lines must be buffered because they may otherwise be overloaded,
especially if the ALU lines are connected to both the lower and upper memory banks.
The double buffered ALU lines enter data latches.
These latches are opened if
SXA (P2A20) is high and CMDR (P2A06) is low.
Thus, data can enter the data
latch during clocks 4 - 8 of a CPU or Refresh cycle.
On clock 9 the latches are

89633300 A

5-65

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MEMORY CONTROL
LOWER POWER DATA RETENTION (LPDR)

(Drawing 89619100, sheet 2)

Function:
This circuit ensures that even under power fail conditions the data stored in
the memory is retained, provided a power back-up source (battery equipment
GD611-A) is connected to the equipment.
Input
SIGNAL

SIGNAL SOURCE/
CONNECTOR PIN

BRWRA
RGPWR

P2B22
P2B29
P2A29
[U37/13]
[U36/9]
[U36/61
P2A23

AP5

-RX

JSC
JSC

FUNCTION

LOCATION
SHEET SQUARE

Active on 32nd cycle
Power fa i 1
Permanent high
Clock 2.5
Refresh cycle select

2
2
2
2

C4
B4
A4

Basic timing signal

2

D3
D4

J

3

B2

Outputs
LOADRA
P4M
NflJRMAL
N
32M
ADVANCE
RXA

MPWR
RRQ
RGPWR

89633300 A

P2A26
P2A15
P2Bll
[U3/91
P2B30
P2B25
P2A25
P2B31
[U36/15]
P2B28

Load Refresh Address
Jsc/8
} "Normal"
JSC/S12
Address register Advance
CPU cycle processed
Master Power switch
Refresh request
Regular power

2
2
2
2
2
2
2
2

B3
D2
Bl
Bl
Cl

2
2

D2
C4

Bl
Al
Al

5-83

MEMORY CONTROL

(Drawing number 89619100, sheet 2, cont'd).

Principles of Operation
Under power fail conditions the circuits essential to retaining the data stored
in the memory may be operated from a battery (optional equipment GD611-A). This
makes it essential to conserve the power used under such operation. The memory
contents is retained by refreshing it periodically. The period is different for
the 600 nanosecond cycle time and the 900 nanosecond cycle time and the 900
nanosecond cycle time memory options. To refresh the memory contents, all 32
row addresses must be refreshed within a specified period (1 millisecond for
600 nsec option, 2 milliseconds for 900 nsec option). During normal operation
this is accomplished by refreshing one row address once every 512 clock oscillator
periods.
This avoids long delays in DSA or CPU access time by performing short Refresh
cycles at given intervals. During LPDR operation all 32 rows are refreshed
sequentially every millisecond. Since it only takes 288 Oscillator periods
(15.7 ~sec for 600 nsec option, 22.0 ~sec for 900 nsec option) to refresh 32 rows
sequentially (called rapid refreshing), unnecessary control circuits can be turned
off for about 98% of the time, conserving battery power. For this reason there
are four separate supply lines on the memory control, memory address and memory
cards.
These are:

vcc

+5 volts during normal operation only.
Those I.C. packages which do not need power at all during LPDR

~peration

are

connected to Vcc
VCC3

+5 volts under all operating conditions.
Those I.C. packages which need power at all times, including LPDR operation
are connected to VCC3 . VCC3 is VCC2 less a 0.7 volt transistor drop.

VCCS

(V CCS1 ' VCCS2 ) +5 volt~ switched.
Those I.C. packages which do not need power between LPDR rapid refreshing
are connected to Vcc switched. Both VCCS
switching transistor drop.

VCC2 +5.3 volts under all operating conditions.
VeC3 and VCCS·
5-84

supplies are VCC2 less a 0.7 volt
VCC2 provides the power for

89633300 A

MEMORY CONTROL

(Drawing number 8961900, sheet 2, cont'd).

Detailed Description of LPDR Circuit
The memory system is self-starting. When the computer is first switched on, the
memory system will be in the LPDR mode.

It performs rapid refresh, tests the

power supply status and depending on this, returns to LPDR or starts normal
operation.
Transition from LPDR to Normal Operation:
Transients on the monostable MM input (U55/1,2) activate MM (U55/13 high) for a
period determined by the RC delay at U55/14,15.

After this period MM deactivates

and the rising edge on U55/14,15 activates the monostable MP (U55/5: high), for
a period determined by the RC delay at U55/6,7. Monostable MP (U55/12) clears
MM (U55/3: low) preventing MM from reactivating. Some time during the active
period of MP RXI
L0ADRA (P2A26).

(U37/2), MP (U37/1), and APS

(U37/13) go high activating

When L0ADRA is active (low), the following happen:

1. Normal register (U3/13) is cleared and put in normal operation:
2. PWRREG

(U3/4) is preset to be active (U3/5 high)

3. Refresh Access Selector (U24/2 on sheet 3) is cleared to be inactive;
4. Disable signal (U41/13 on sheet 6) is forced high preventing memory cycles
occurring in the memory.
5. The contents of the refresh address register on the memory address (MA)
assembly is loaded to a particular address.
RXI is the RX register contents delayed one clock cycle.
BRWRA is a signal from the MA assembly. It is active (low) only on the 32nd
refresh address after L0ADRA was active.
If RXI (U22/5) is low, (as it must be since L0ADRA clears RX), and Normal is
inactive (22/1 high:

it must be since L0ADRA

clears Normal at

U36/1~

is active (high).

is cleared, and RRQ (Refresh Request:

by U35/13, and requests a refresh cycle to the access selector.
monostable MP deactivates.

U3/1~;

then U36/2

RRQ is synchronized
After its period

MM cannot reactivate at this time because register N,

(U3/9 to U4/2) is. inactive, and PWRREG (U3/6 to u4/5) is also inactive. L0ADRA
deactivates when MP deactivates, and a refresh cycle is performed.
is inactive,

~22/13

Because BRWRA

high) RRQ continues requesting refresh cycles and rapid refresh

occurs, refreshing all memory locations.
One clock after RX activates, RXI activates. U36/3 is cleared (low) forcing
U36/14 high.
89633300

A

U36/14 was previously low because U36/2 was preset (low).

MEMORY CONTROL

(Drawing number 89619100, sheet 2, cont'd)

When a flip-flop is simultaneously preset and cleared, both the Q and Q outputs
will be active (high). When the refresh cycle is completed, RXl will go high,·
and U36/14 will go low. It is the negative edge of RRQ at U36/14 that advances
the row address counter on the memory address assembly. If ADVANCE (P2B2S),
goes negative and L~ADRA is inactive, the row address advances. On the 32nd row
address, BRWRA goes low. After the 32nd refresh cycle begins, RXJ activates.
Because BRWRA is low, Preset (U36/2) is not active, but Clear (U36/3) is ative,
and thus RRQ (refresh request) ceases to be active, terminating the rapid refresh.
Also on the fall ing edge of BRWRA, the s atus of the power supply RGPWR is stored
in the PWREG FF, U3/5,6.
otherwise RGPWR is low.

If there is a power-failure, RGPWR (P2B29) is high,

One clock after the 32nd refresh cycle finished, RXI inactivates, and RRQ FF
preset (U36/2) activates while clear (U36/3) deactivates. The refresh address fs
advanced once more, and BRWRA goes high. The rising edge of BRWRA has two different
conditions:
.Cond i t i on I:

Power Fa i lure

If the PWREG FF is active (U3/5 low, U3/6 high) when BRWRA rises, U55/1
falls and monostable MM is activated. The combination of MMj'(U55/4 low)
and Normal (U3/9 low) is ORed into the master power switch and MPWR rises.
When MPWR is high, VCCS
circuit on Normal (U3/9
switches off.
After the active period
The RC on U37/5 assures

is off, conserving battery power. A switching
Q2) assures that this line will remain low when VCCS
of MM, U55/4 rises, and MPWR falls, VCCS switches on.
that L0ADRA is active. The entire cycle from L0ADRA

active will repeat itself.
Condition 2:

Regular Power

If the PWREG FF is active U3/5 high, U3/9 (Normal) activatesi Because RRQ
was active before this happened one more refresh cycle is immediately
performed.

5-86

89633300 A

(Drawing number 89619100, sheet 2, cont'd.)
MEMORY CONTROL
Normal Refreshing:
A divide-by-64 counter (U20, Ul, U19) divides the 0SC frequency between P2A23 and
U19/6. A divide-by-nine counter (U35) further divides esc between U19/6 and
32M (P2B30).

The signal 32M is thus iSCdivided 576 times.

CPU as a counter for a power failure condition.

It is used by the

The fall ing edge of 32M also

,activates RRQ (U36/l5 high) and advances the refresh address (U36/14 low).

When

the refresh cycle begins, U36/3 is cleared by RX1, and the refresh request ceases
to be active.
Normal to LPDR Transition:
If during Normal operation a power failure occurs, the memory system has about one
millisecond to process CPU and DSA requests before the memory system goes into LPDR
operation.

When a power failure occurs during normal operation, RGPWR (P2B29)

rises, and U55/1 falls, activating monostable MM for 1 millisecond.

However,

because the Normal register is active (U3/9 high) MPWR remains Low, and VCCS
(switched supply) remains "on".
At the end of one millisecond monostable MM falls,
and monostable MP activates; MP clears monostable MM so that it will not reactivaLe.
If the memory system is not in the middle of a memory cycle, .. or has not finished a
refresh cycle on the previous clock, L0ADRA is activated (throughU37/3).

The

refresh cycle not being active previously is an important condition, because if
LeADRA should activate too soon, the refresh address will change too soon, and
memory unit specifications will not be met destroying the contents of the previous
refresh address.

It is permissible to activate L0ADRA before CE is active (clock 4).

The entire cycle from L0ADRA active will repeat itself.
The Refresh Request is self starting and operates as follows:
If the memory system is in normal operation, a refresh request (RRQ) must occur
every

~76

clock cycles.

If the memory system is in LPDR operation, monostables

MM and MP will eventually become inactive.
occurs unless BRWRA is low.

The RRQ must be active when this state

But BRWRA Is low only on the 32nd refresh cycle.

Because LeADRA must be activE' when the power is first initiated, BRWRA cannot then
~e

low too.

89633300 C

BRWRA can be low only during a series of rapid refresh cycles.

5-87

MEMORY CONTROL

(Drawing number n9619100, sheet 2, cont'd.)

Signal P4M, (P2A15) is the oscillator (SSC) divided 8 times.
signal to the CPU (front panel strobe).

It is a timing

Normal, (P2BII) is the status of the memory system to the CPU. It is wired-OR
(open collector) from both memory banks. If either memory bank is not in
normal operation (lPDR), this signal is low.
RXA (P2A2S)
This active high signal informs the memory address card that a REFRESH cycle is
being processed. It is active in lPDR operation, as well as from the beginning
of a refresh cycle until one clock after RX deactivates.
High (P2A29)
Used for Manufacturing Testing of Memory Control Card, synchronizes the
divide-counters. In use this line is always high and does not affect the
counters.
Timing relationship between RRQ and ADVANCE:
RRQ (U36/IS):

Clock

active high;

0

ti ...

Normal

ADVANCE (P2/25):

active high

8

2

10

~

Operation

RRQ ;: ADVAHCEJ
RX

Av
tv

'"

RXA

H
L

L

H
L
H
L

LPOR Ope ra t ion
32nd r. fr ....

H
L

ADVANCE
RRQ
8RWRA

5-88

--1

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89633300

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5-104

89633300

A

(Drawing number 89619100, sheet 3,4,6).

MEMORY CONTROL

MEMORY CONTROL BASIC CONTROL SIGNALS
Function:

To provide all control signals to the memory, memory address,
CPU and DSA devices.
Note:

The following signal lists include a number of signals
not directly connected to the circuits described here.

Inputs
SIGNAL

!SIGNAL SOURCE/
ICONNECTOR PIN:

FUNCTION

LOCATION
SHEET SQUARE
3

A-I

PlB30

3

D-2

SPI

PlB29

3

C-2

WE

P1A30

3

D-2

SWRITE

P1B31

3

C-2

(6SCA

U38/6

Oscillator buffered

CRQ

P2A09

CPU cycle Request

6

D-3

P2A08

6

0-3

P2A22

3

A-2

PRTSW

P'RTM

ICA
PBC

89633300 A

P2BOI

I

II
I

,
,

5-105

..'"

MEMORY CONTROL

(Drawing number 89619100, sheet

3~4,6,(cont'd).

Outputs
SIGNAL
GJlM1
GJlM2
DISABLE
SXA

! R/W
I

I

CXP
HfJLDW
HJlLD

. SIGNAL SOURCEJ
CONNECTOR PIN

i

P2B09

ICA·CRQ + CX·B.E

SRSM

A-2

II
:

P2A20

Read/Write

3

C-2

P2B16

CXeSX-HeLDeAP5

I!

3

C-2

P2A24

AP5

3

C-2

I

P2B14

AP5 [SX + cx]

3

B-2

I

P2Al1

SX·HOLD .AP5

3

C-2

I

P2B18

SX.[D + B]
DSA Synchronizing signal

4·

B-1

4

B-1

4

C-1

4

A-l

4

0-4

4

B-1

4

B-3

4

B-1

4

A-3

i

i
I
II
~

I
I

I

I
I

i

(m

i

I

P2A07
P2B27

RX [B + E]

-E.t

=

C + E, (Cenable)

P2B17

Data-line Enable

II

P2B12 .

Second Counter stage

P2A12

Timed by 0 (=0)

II

I

~

,,

1,

I
,
!

A~C

I

;

i

P2A17

.

!

,

i
!

I STReBE I
I

5-106

3

DSA active

DE

CVI01

B1

P2B08

II
!
I

CMDR

6

Ii

I

P2B02

i
I

:

!

I

0-1

LOADRA -Fe BUSY" IP5

.,

B

6

P2B10

IT

P16

0-1

P2B07

iI

REF

6

I

I

SXP

LOCATION
SHEET SQUARE

FUNCTION

B'E

,
I
;

,
i

P1A28

(See sheet 5)

,
I

,

89633300 A

MEMORY CONTROL

(Drawing number 89619100, sheet 4,6, contld.)

Introduction
The Control unit processes a collection of control signals and can be divided
into two parts:
1.

Basic Control Signals
Control signals necessary for all types of memory cycles,
i.e., read or write cycles in protected or unprotected
locat ions.

2.

Write Control Signals
Control signals for write memory cycles used with the
protect system.

Note:

For timing signals refer to Memory Control Timing (sheet 4).

BASIC CONTROL SIGNALS

DISABLE

(L)

P2B10

The falling edge of this signal activates the precharge signal in the memory.
The falling edge starts at clock 1.5, giving the memory system half a clock
period to select one of four kilowords on each memory card.
As each kiloword
has its own control signals (precharge, cenable, R/W) only one kiloword will
be activated.
Since the precharge signal consumes most of the memory power
delaying the disable until clock 1.5 conserves power consumption without
imposing critical set-up or hold time restrictions on other memory signals.
The rising edge of the disable signal deactivates the cenable (cell enable
signal) in the memory.
This occurs at clock 10 for DSA and CPU cycles, and
clock 8 for Refresh cycles.

89633300 A

5-107

MEMORY CONTROL
CE

(L)

(Drawing number 89619100, sheet 4,6, cont'd.)

P2B27

(Cenable)

The falling edge of this signal at clock 4 activates the cenable signal in the
memory.
Also, within the memory, the canable signal forces the precharge
signal to deactivate.
The crossover of the cenable-active precharge-inactive
is performed on the memory card (rather than the memory control card) because
of critical overlap times required by some memory chip manufacturers.
The
CE signal deactivates at clock 11 for DSA and CPU cycles, and clock 9 for
Refresh cycles.
It is important to have the CE signal deactivate one clock
after the Disable signal deactivates.
If the CE signal deactivates earl ier,
the precharge signal may reactivate at the end of a memory cycle.

REF

(L)

P2A07

The REF signal blocks the module selector (MDX#) within the memory card.
During Refresh cycles the REF signal is always activate low because a Refresh
cycle must refresh all of the memory modules.
During DSA and CPU cycles,
this is low during clock 1 to 3 because the module selector decoding is slow
The REF signal goes high between clock 3-11.
and not stable during this time.
For all unselected memory modules during this time, the precharge signal
deactivates one clock before the Cenable signal, and the cenable with the
memory card never activates.
Only in the one memory module selected by
the module selector does the precharge-cenable sequence continue.

STR0BE

(L)

P2A12

This signal is active low between clocks 5-10 for DSA and CPU cycles, and
clock 5-9 for Refresh cycles.
It enables the data out sense amplifiers
within the memory card.
It also deactivates the Read/Write (R/W) signal
(see R/W signal later in this section) slightly faster than the cenable
signal, helping meet an end of cenable - end of R/W specification for the
memory chip of some manufacturers.
during refresh cycles.

5-108

This signal performs no useful function

89633300 A

(Drawinq number 89619100, sheet 4,6, cont'd.)

MEMORY CONTROL
Ci~~~i!. __descr i pt ion:
DISABLE

(l)

P2B10

Disable activates (low) when lP5 (U41P10) ~oes high at clock 1.5.
Disable
deactivates when F (U41P12) goes low.
One clock after F goes low,
BUSY (U4lP9) goes low.
Then F goes high.
When the next access selector
activates, BUSY goes high.
If l8ADRA (U4lP13) is low, Disable is inactive.
l8ADRA is used for lPDR operation.

CE

(l)

P2B27

This signal falls at clock 4 when register
rises.

REF

(l)

C falls,

and rises when register

E

P2A07

This is a 2-2 AND-OR gate.
REF is low during refresh cycles because U61Pl,13
is connected to RX.
REF is low for DSA and CPU cycle until clock 3 when
register B (U61P10) falls, and REF remains high until clock 11 when register E
(U61P9) rises.

STROBE

(l)

P2A12

This signal is the inverse for register D.

Because Disable and CE are critical timing signals going to eight memory
modules, they employ extra powerful buffers to be less noise susceptible.
STR8BE is extra powerful because each of eight memory modules uses 2.5 TTL
logged units from this signal.

89633300 A

5-109

MEMORY CONTROL

(Drawing number 89619100, sheet 4,6 cont'd).

Basic Control signals during refresh cycles.
SXA

(l)

P2B08

This active low signal informs the Memory Address (MA) assembly that a DSA
cycle is being processed. It is the inverse of SX, active between clocks 1-11.
P16

(l)

P2A17

Active low signal opens the 16 bit parity latch on the MA assembly; activates
at clock 7 when ~ (U23/2) rises until clock 9 when C (U23/1) falls.

B

(l)

P2B12

Active low signal clocks the protect bit (bit 17) register on the MA· assembly.
Activates at clock 7.S when JSC rises. Deactivates at clock 8 when JSC falls.
B cannot activate during other time intervals.
CMDR (l)

P2B02

Active low signal provides timing to the H~CPU data in memory latch.
CMDR activates at clock 4 when E (U63/S) goes high and activates at clock 8
when B (U63/4) goes low.

S-110

89633300 A

MEMORY CONTROL
CXP

(L)

(Drawing number 89619100, sheet 4,6, cont'd.)

(P2BI6)

SXP

(L)

(P2All)

Hf/JLD

(H)

(P2BI4)

These three signals provide initiate and hold signals for the selector/latches
on the memory address assembly.
Before a memory cycle begins, Hf/JLD is High to hold the old memory address.
SXP and CXP are also high.
When the CX access selector activate at clock I;
CXP goes low, which allows a new ALU address into the MA address selectors.
The CXP signal is also fed into U23/10, so U23/8 goes high and Hf/JLD (U42/8)
goes low.
This overlap of CXP and Hf/JLD is important, because it allows the
outputs of the MA address selector/latches to change only once.
On clock 2.5
the signal AP5 (U58/4,5) goes low and Hf/JLD goes high.
This holds the address
in the MA address selector/latches.
The Hf/JLD signal and AP5 are fed into a
NAND gate whose output (U23/11) causes CXP to go high.
This overlap of Hf/JLD
and CXP prevents the MA address selector/latch from changing during this
transient period.
R-S flip-flop;

In other words, CXP and Hf/JLD behave like the Q and Q of an

except Hf/JLD is Q inverted.

For a DSA cycle, SXP behaves like the CXP signal during the CPU cycle.

During

the DSA cycle, CXP always remains high.

Hf/JLDW

(H)

(P2A24)

The MA address selector/latches for the kiloword decoder do not have the same
This decoder can have transients
requirements as the other address bits.
when the Disable signal is inactive between clocks
- 1.5.
However, it is
desirable to have the kiloword decoders completely decoded before the Disable
signal activates at clock 1.5.

For this reason, a special hold signal called

HI/JLD~[

is used for the MA kiloword decoder.
It is the signa I AP5 inverted,
and is active high between clocks 2.5 - 11.
No time is wasted in the kiloword
decoder when CXP goes low at clock I because Hf/JLDW is already low on clock 1.

89633300

A

5-111

MEMORY CONYROL

(Drawing number 89619100, sheet 4,6, cont'd).

Basic control signals to the CPU
G0Ml

(H)

P2B09

The CPU and memory are both synchronous devices using the same oscillator.
However, the memory system is not always ready for the CPU because it may be
performing DSA or Refresh cycles.
the CPU.

When this happens, it is important to stop

The CPU is a two pass machine. During pass 1 the ALU calculates address
information and holds this information at the end of pass 1. During pass 2 the
ALU calculates or receives data information and holds or accepts this information
at the end of pass 2. Both ALU passes are 5 clocks long; therefore pass 1 and
pass 2 together take 10 clocks. This causes a discrepancy, because the CPU memory
cycle is 11 clocks long. When the CPU is performing a memory request, it must
be stopped for one clock so that both the CPU and CPU memory cycle will have the
same number of clocks, namely 11.
The CPU is stopped by the memory system with the signal G0Ml. If this signal is
low at the end of CPU memory request pass 1 or pass 2, it will stop at the end
of that pass. Further, the memory system requires address information between
CPU memory cycle clocks 1-3 and data information between clocks 3-9. The three
conditions for lowering the G0Ml signal can now be defined.
1)

The memory system is busy with a DSA or Refresh cycle.

The combination of

the following three conditions define this:
if the memory is not processing a CPU cycle (CX: u60/5),
the CPU requested memory access (CRQ: U60/6),
the address is in this memory bank (ICA: U60/4).
2)

The memory system is processing the CPU request, but has not yet reached
clock 3. The combination of the following conditions define this:
the CPU requested memory CRQ (U60/l) for th i s memory bank I CA (U60/11,
12) ,
the memory cycle has not passed clock 2 because register A (U60/13) is
active.

5-112

89633300

A

~

MEMORY CONTROL
3)

(Orawing number 89619100, sheet 4,6, cont'd).

The melilory system is processing the CPU request, but has not yet reached
clock O. The combination of the following conditions define this:
the memory is processing a CPU cycle between clock 6-11{U60/10), and
has not yet passed clock 8 because register B (u60/9( is active.

Two memory systems are used in systems having more than 32K word memories.
A second signal (G/4M2: P2B07) is employed in the expansion memory system; it
is basically identical to G/4Ml in its function.
Further explanation of the CPU memory request system.
Schottky TTL circuits are employed in this system because timings must remain
synchronized with the oscillator. The CPU transmits the CPU request signal
CRQ between its clock 2-5 of pass 1 only. Also, the signal G/4Ml must be high
for one clock at the end of a CPU pass, which is why G/4Ml is released before
memory system clocks 3 and 9. The timing relationships are shown below.

~CPU

CPU Clock 0
Memory Clock 0
eRQ

a.MI

89633300 A

1

0

PASS
2
0

CPU PASS 2

-~

3

4

5

2

3

6
4

7

5

8
6

I

I

I

9
7

"I
9
8

0
9

2
10

3

11

I
I

H

L
H

L

5-113

MEMORY CONTROL

(Drawing number 89619100, sheet 4,6, cont'd).

Basic Control signals to the DSA
SRSM

(L)

P2B18

The SRSM synchronizes the DSA with the memory. Because the DSA is an
asynchronous device, the SRSM does not have to be a fast signal. The SRSM
appears at an open collector gate, and can be used as a wired-OR function.
In multibank memory operation the SRSM of both lower and upper banks are
connected together. This is an active low signal; normally the line will be
high. When one of the memory systems wants to activate the SRSM line, it
merely activates its own SRSM signal. The entire SRSM is then forced low
until this same bank deactivates its SRSM signal.
When SRSM is high, at the beginning of a DSA cycle, it informs the DSA device
that the memory has not accepted the DSA address, and that the DSA should
continue to transmit the address.
When SRSM falls, it informs the DSA device that it has accepted the DSA request
and address. The DSA should immediately clear the DSA request and address
lines, and it can send a new DSA request and address if desired.
Further, for a DSA write-into-memory cycle, the low SRSM signal informs the
DSA that the memory has not yet accepted data, and that the DSA should continue
transmitting data to the memory.
Also, for a DSA read-from memory cycle, the rising edge of the SRSM signals
informs the DSA device that data from the memory is now valid.
The SRSM is low between DSA cycle clocks 3-11.
Refer to DSA Timing Specification in Section 4 and the Input/Output
Specification Manual.

5-114

89633300 A

MEMORY CONTROL

(Drawing number 89619100, sheet 3, cont'd).

WRITE CONTROL SIGNALS
Function
The memory system includes a protect system.

The primary purpose of this

feature is to protect the program in foreground from being destroyed by
careless programming, or faulty memory operation. The protect feature is part
of the write system within the memory.
The read/write and protect status of the memory cycle is determined by
multiplexer-selector u64. The following table shows its input and output
signals.

Input Controls
RX
SX
(Pin 3) (Pin 13)
L

L
H
L
H

L
H
H

Outputs
WRITE cycle
(Pin 2)

;

;

I

SWRITE
Low
irrelevant

,
,

Selected

Unprotected Instruction
(Pin 15)

'PRTM

WE

C~cle

SPI
Low
irrelevant

CPU cycle
DSA cycle
Refresh cycle

---

I.,

I
I

I

I
I,
I

!

Signal Description
The following paragraphs describe each signal in detail: the signal name heads
each paragraph together with the integrated circuit and pin number where it
appears. The letter (H) and (L) indicate whether the signal at the corresponding
pin is active High or active Low.
WRITEREG[(H) UI2/5, (L) U12/6)
This register is positive edge triggered. On clock 6 it stores both during
a read cycle (pin 5 low) and a write cycle (pin 5 high). Pin 6 is the
inverse of pin 5. U12/4 (active low) is preset (pin 5 goes high) on clock 4.
This is to prevent unnecessary spikes on the data out 1 ines to the DSA and
CPU lines.
89633300

A

5-115

MEMORY CONTROL

(Drawing number 89619100, sheet 4, cont'd.)

PROTECTREG (H) U29/8, (l) U29/9
This register is positive-edge triggered. On clock 6 it stores whether
the cycle is a protected instruction (U29/8 high) or an unprotected
instruction (U29/8 low). P9 is the inverse of pin 8. U29/13 (active low)
is cleared (p8 goes high) when the PRTSW (Protect Switch, P2B01)" is low.
In this case (protect switch low) all instructions appear as protected
within the memory system. The protect switch is situated on the programmer's
console (front panel)
INHIBITREG

[(l) U29/5]

This register is positive edge triggered.
either one of two conditions occurred:

On clock 6 it stores provided

The first condition is that a parity error occurred on either memory bank
while the instruction was unprotected.
The second condition is that during a CPU cycle a parity error occurred in
the selected memory location and that the SPB or C'PB (Set or Clear. Protect
Bit) is activated on this memory cycle.
The two conditions may be summed up: when an attempt is made to execute
CPB or SPB instructions when a parity error exists in the selected
memory location.
The procedure for recognizing condition 2 works because before CPB or SPB,
the program must read from the location in memory, and immediately afterward
perform the CPB or SPB in that same location.
If the INHIBITREG

register recognizes either condition 1 or condition 2

or both conditions, U29/5 will go low.

Otherwise U29/5 is high.

U29/4 (active low) is preset [U29/5 goes high when the PRTSW (Protect
Switch, P2B01) is low].

When the protect switch is low, the protect

feature of the system appears to be disabled.

5-116

89633300 A

MEMORY CONTROL

(Drawing number 89619100, sheet 3, cont'd).

R/WREG [(H) u44/8]
This register provides timing to the Read/Write (R/W) signal in memory.
It also determines if the R/W signal should be activated.
This register is negative edge tirggered and is connected to the esc
(u44/13). It is activated on clock 8 (u44/8 goes high) only if one or
both of the AND-OR K inputs is active on clock 7. u44/10, 11 is active
only on clock 7. If the instruction from the PROTECTREG is protected
(u44/9 high), or if the protect bit from the memory location addressed
was inactive (U44/12 high), then u44/8 can activate on clock 8. Thus,
a write cycle will not occur if the location in memory is protected and
the instruction is unprotected. The only other condition necessary for
the R/WREG to activate is that the WRITEREG (U44/5) indicate that the
memory cycle is a write cycle. If the memory cycle is a read cycle, the
R/WREG is preset, (U44/5 is active low) and u44/8 will remain low on clock
8. If the R/WREG activated on clock 8, it will deactivate on clock 11
after 0 (U44/3, 4) activates the J input between clock 10 - 5. The J and
K inputs can never be active simultaneously because of this timing.
Read/Write: R/W [ell P2A20]
The R/W signal activates the R/W signal within the memory. If activated
the R/W signal will go high between clocks 8 - 11 (U59/10 high). The
R/W signal cannot activate if the INHIBITREG is active (U59/9 low), or
if the system is in lPDR operation (Normal, U59/13 low).

DE

[(l) U5716]

DE activates

the data-in lines on the Memory Address assembly.

These

lines transmit data to the memory on write cycles. It is desirable to
activate these lines by
clock 8 because these lines may create noise on
the data out lines from the memory and interfere with parity checking on
a Read/Write cycle. DE goes low on clock 8 when (U57/4) goes high.

DE goes

89633300 A

high on clock 12 which is approximately 50 nanoseconds after

5-117

MEMORY CONTROL

(Drawi'ng number 89619100, sheet 4, cont'd.)

register Ewent low as determined by the RC delay on US7/3.
The Of signal needs to be active until after the R/W signal within the
memory has completely deactivated. If the WRITEREG register indicates
that the memory cycle is a read cycle (U57/s is low), DEwill not activate.

5-118

89633300 A

&

'"

w
w
w
o
o

R33

270

2

,Ilo-"-'=",,-, PI'

3.5

o

II
20",
I U47-

3

vee

fREvTECO

DESCRIPTION

5017

10

.r:-

3 PIAn (MPIIY

3~

3

9

5016

12
13

SVI_

ffi,

IL
~l-------~~~~u

~-L----l-~----~==----r---~AF}6

3-=

'C7

~1-+-+-~2
t-!f-+--:-1 2~H
.... U13

P21112 (8
6

PUll?

(ffi

3( X· ~+-

"UTI)

ro~,~

II •

MUT,) ~'D"'I

I

I.
PI

. D,UT

IDY'~';

I

• I I

~I

V1
I

N

.......
"V1
I

N

00

-p" ,.

(DELE_

DETAILED LOGIC DIAGRAM
MEMORY CONTItOL

MEMORY CONTROL
MEMORY CONTROL BANK ADDRESS (Drawing number 89619100, sheet 6)
To determine which memory bank the CPU or DSA is addressing •

Function:

.I

SIGNAL SOURCE!
CONNECTOR PIN

SIGNAL
SA15
EDX

P2AOl
P2A05

CRI
CAA 15
32KW

P1B26
P1A25
P2A06

CRo.
ICA

P2A09
P2A08

Ouq~uts

I

NAME OF SIGNAL
DSA address Line 15
More than 32K of memory are
ava i 1ab 1e
CPU Index address OOFF
CPU address line ALU15
32KW Switch on Mainframe front
panel.

I

LOCATI ON
:sHEETSQ.UARE
6
6

C-3
B-3

6

C-3

6

B-3

6
6

0-3
0-3

6
6
6
6

C-l
B-1
C-l
C-l

:

Ice
ICfI
Ise

1SJ

P2B03
P2A02
P2A04
P2B04

II

I
t

Lower-bank ~~~ address correct
Lower-bank CPU address incorrect
Lower-bank DSA address correct
Lower-bank DSA address incorrect

Description of Operation
The outputs of this circuit are connected via the back-plane of the computer
enclosure to the appropriate CPU and DSA address function. The circuit
decodes the CPU and DSA address information to determine if the memory bank is
correctly addressed.

89633300 A

5-129

MEMORY CONTROL
Signal Functions
SIGNAL

(Drawing number 89619100, sheet 6, cont'd).

SIGNAL SOURCE!
CONNECTOR PIN

FUNCTION

LOCATION
SHEET SQUARE

ICIII

u66/6

Lower-bank CPU address correct
If any of u66/6 inputs are Low·,.
the CPU requests access to the
lower memory bank. Otherwi se
the memory request access to
the upper memory bank.

6

Cl

iCJ

u6/8

Lower-bank CPU address
incorrect •. The inverse of ICf.

6

Cl

ISIII

U63/3

Lower-bank DSAaddress correct.
If any of U63/3 inputs are Low,
the DSA requests access to the
lower memory bank. Otherwise
the memory requests access to
the upper memory bank.

6

Cl

ISf

U62/l0

Lower-bank CPU address
incorrect. The inverse of ISf •.

6

Cl

Interconnections:
The Bank address is connected to the Access Selector via the back-plane
wiring as follows:
Lower-memory bank:
IC'

ICA
TCJ
TCA
ISIIIISA
ISill

----

NOT CONNECTED

Upper-memory bank:
ICII

1CJ
ISill
1SJ

5-130

TEA
ICA
NOT CONNECTED
ISA

89633300 A

THE CENTRAL PROCESSING UNIT
The Central Processing Unit (CPU) consists of the printed wiring boards (PWB)
listed in the following table:
r~~s

i gnat ion··· .... -. '-' -- · .. ··..·····_·--··r-······

.~~~~.~~'~'-

..... ---.-- --'....--.--.....----.

L....... ............".,,,.... ,_-.. __ ."" ,. ............ .
I

j

Carries the front panel controls

: Programmer's Console
i

Two identical PWB's

i Ar i thme tic ,and Log i c Un i t (ALU)

i

I Decoder

I Timing

I Input/Output

I

(I/O) Interface

Console Interface

Breakpoint Logic is also
accommodated on this card.

I TTY Con t ro 11 e r

!
i

,

____

~~

••

_.,~

_____

w_ ••••

~.,

__ •

~

~~

•• _

•• _ " _ " _ " _ _ "

__

""'"""'~

.". . . . . . . . . . . . . . . . . . _

....

.

Note:
The whole of the CPU is part of the ABI07/AB108 equipment.

5-141/5- 142
89633300

A

PROGRAMMER'S CONSOLE
Controls and Indicators
The Programmer's Console circuits are on a single printed wiring board which
also carries the controls and indicators of the computer. 1n type identifiers C and D, a set of 29 pushbutton switch caps, part number 89764900, is a
spare part for the console.
Anti-Bounce Circuit
Afl PWA's require anti-bounce circuitry for the GO and MANUAL INTERRUPT
pushbutton switches. The anti-bounce circuit includes two one-shots and associated resistors, capacitors, and inverters. PWA's PIN 89985400 and
89602068 have anti-bounce in the printed circuit. See logic drawing 89640500
sheet 4, zones D-4 and C-2 on page 5-157.
PWA's PIN 89987600 and 89987700 have no anti-bounce circuit on the board.
They therefore use a separate small PWA PIN 89982800 for anti-bounce, which
is mounted piggy-back and connected to the Console by four wires. Note that
the encircled numbers 1 ~2,3,4 in the Anti-Bounce PWA on page 5-159 indicate
connections to the GO switch and to the MANUAL INTERRUPT switch in logic
drawing 89640501 sheet 4 on page 5-163 and in logic drawing 89640502 sheet 4
on page 5-167.
Cables
PWA PIN 89640300 (series A12 down) has an integral cable assembly which is
soldered to the board. This is also true of PWA PIN 89987600. All other PWA
PIN's connect to the CPU circuits through a plug-in cable assembly PIN
89893800.
TYPE IDENTIFIER
(ABI07,ABI08,BT148) CONSOLEPWA
A
PIN 89985400
A
pIN 89987600
A
PIN 89987700
pIN 89602068
C
PIN 89602068
D
The de s c rip t ion of the logic applies
89633300 F

LOGIC DRAWING

PAGE NUMBER

LD 89640500-B
LD 89640501-A
LD 89640502-A
LD 89640500-B
LD 89640500-B

5-145

5-159
5-164
5-145
5-145
to all the above PWA part numbers.
5-143

I

I The

following table gives the designation and function of the principal
blocks of the circuit. The circuit and the signals are described' in detail
on pages facing the corresponding sheet of the logic diagram. The control
switches and indicators are described in the computer reference manual_

THE MAIN CIRCUIT BLOCKS

Description

Designation

Shown
on sheet

Pushbutton switches

The seven pushbutton switches
allow the selection of one of
the six internal registers or
the Breadpoint register

2

Data-bit selectors

Allow manual data input to
each of 16 bits of the computer
from the programmer's console
when the computer is stopped

3

Control switches and These are the programmer's
Indicators
means of manual communication
with the computer. They are
described in the Reference
Manual for the Control Data 1784
Computer System, publication
number 89633400,

-

4

",

5-144

89633300

F

...
00
\D
0'

...
(IFF - SHEET REFERENCE

\N
\N
\N

111'1' SHEET
R£F£RENC£ LETTER
A
II
D

o

o
"TI

LllCATIIM
SHEET
4
3
2
A-3
A-I
II-I
A-2
'C-4
D-2.

rt"":J

P22-1

IATTtIlV)
P22-C

'II-A

<,.1. GlIlIUIID

,,/,
S 30

lIN'tlfF )

POWER

11112

®"
YCC

vee

IK
_U
vn:

"P21 -II

,

r"CV-o...

...D

,... P20-11

GIlD

,

·...D
GND

PI' -04

I
~

V1

......

V1
I

~

0'

GIlD

""

lOY

1

... P21 _II
P21_11

FOR

'21-24

GIlD

V1

CI1

~ lib'

"PlI -01

GND r

GIlD

1

P20-11

, '20-14
, '10-51

GilD

C:.-C20

NIlTES
I. CI-C7 ARE InF.
2. ALL RESIST8'RS ARE 0.2S WATT S%.
3 RI- RI7, R34.R!!O AND R97.;. RI03 ARE IBO .eHMS.
4 RIB - R33, RII4,RII3 ARE 330 rlHMS
S. RSI - R74, R 76, R77, R79, RBI-R96,RI2 ARE II( 0HMS6. RI04 - R 110 ARE !!60 IIHMS
7. R 7S AND Rill ARE 33K 0HMS .
B. cn, C24 ARE 100 nF.
9. C21, C22 ARE 0.47 MF.
10.R1B,RBO ARE !5.6K eHMS.

PZO-11

...D

GIlD

±

)P29-·c,-clll

GilD

GilD

.VCC

FOR PWA

'21 -II

"P21-17
"

PWA

".1'0; """.,""
~.,

CX)
~

o
N
o

~

~

~

.. ",.\fIt ,uu

PIN 89985400
PIN 89602068

of""':

'll JrtC ... S

1'(.: . . . . . .Cf5

DETAILED

LOGIC

DIAGRAM

PROGRAMMER'S CONSOlE
Dl'A...O NO

I

PROGRAMMER'S CONSOLE (Sheet 2)
REGISTER SELECTORS
Function
The
the
has
The

seven pushbutton switches (S1 through S7) allow the selection of one of I
six internal registers or the Breakpoint {B} register. When a register
been selected, the corresponding front panel indicator lamp lights.
circuits are actuated on pressing the pushbutton.

Pushbutton Switches

PANEL DESIGNATION

CIRCUIT DESIGNATION

M
P
V
X
A
Q
B

S1
S2
S3
S4
S5
S6
S7

FUNCTION
Selects
Selects
Selects
Selects
Selects
Selects
Selects

register
register
register
register
register
register
register

M
P
V
X
A
Q
B

Inputs
SIGNAL

ACTIVE

SEN

H

P4M
CLREG

H
H

89633300

F

FUNCTION
Active when computer stopped
(from TTV Controller)
Clock from Memory Address

LOCATION
SHEET SQUARE
2

0-2

2
3

B-2
A-4

5-147

PROGRAMMER'S CONSOLE (sheet 2, cont'd)

Output

I

SIGNAL

ACTIVE

CSM
CSJ5"
CSY
CSX
CSA
CSQ
CSB
CLRB
BCK
CSCK
CLREG
PCL

L
L
L

5-148

l

L
L
H
L
H
H
L
L

FUNCTION

Register control signals

Clears B Register
B Register clock
Clears selected register
Clears all CPU timing
flip-flops when P Register
is cleared

LOCATION
SHEET
SQUARE
2
2
2
2
2
2
2
2
2
2
2
2

B-1
B-1
B-1
B-1
C-l
C-l
0-1
A-I
A-I
B-1
C-l
C-l

89633300 F

PROGRAMMER'S CONSOLE

(sheet 2, cont'd)

Circuit Description
The switches are connected to the corresponding register control lines
through input network and gating circuits • . The input network also
ensures that only one register at a time may be selected.
The input network consists of a set-reset flip-flop in each selector
line; the set input of the flip-flop is taken from the switch through a
pull-up resistor and delay capacitor, the reset input from the inverted
output of a~ a-input NAND gate whose inputs are also taken directly from
the switches. When anyone switch is pressed, its I ine is grounded and
all the register select fl ip-flops are held reset, including the one
selected. When the pushbutton switch is released, all flip-flops remain
reset except the one selected; this is set by the signal (ground)
conserved on the delay capacitor at its set input.
The indicator lamp drivers are actuated from the selector fl ip-flop output
and cause the indicator to light when the flip-flop corresponding to it·
is set.
The register control signals are obtained by ANDing the output of the
corresponding selector flip-flop with the signal SEN in AND and NAND gates.
This prevents manual operation of the computer while it is running under
program control.

~9633300

A

5-149

I

PROGRAMMER'S CONSOLE

(sheet 2, cont'd)

The other output signals are as follows:
Signal

Equation

Funct ion/Remarks

'Ci:RB

CSB·CLREG

CLREG
PCL

CSp·CLREG

CSCK

SEN· P4M·C

Clears the B register
Clears selected internal register
Resets all CPU timing flip-flops when P register
is cleared
Clocks data into one of the six internal registers.
It is produced when anyone of the data bit or
clear pushbutton switches is pressed [condition C
(U26,10)] and is active only when the computer is
stopped (condition SEN).
The frequency of the
clock is that of P4M.

BCK

5-150

P4M·CSB·C

P4M - clock signal from Memory Control; repetition
rate approximately 0.44~sec for AB108,
0.65~sec for AB107.
Clocks the B register. It is produced when anyone
of the data bit or the clear pushbutton switches is
pressed (condition C) and has the frequency of P4M.

89633300 A

.

WI

&

(1'\

\N
\N
\N

o

o

E

o

V'I
I

V'I

DETAILED LDGIC DIAGRAM
PRDGRAMIIER'S CONSOLl

PROGRAMMER'S CONSOLE

(sheet 3)

DATA BIT SELECTORS
Funct ion
The circuit allows data input to each of 16 bits of the computer from the
programmer's console when the computer is stopped. The indicators associated
with each b.it allow monitoring the contents of each bit location, both on
manual operation and when the computer is running under program control.
The clear pushbutton and its circuitry are included here.
Pushbutton Switches
PANEL DESIGNATION

CIRCUIT DESIGNATION

0
1
2

S23
S22
S20
S21
S19
S18

3
4
5
6

S17
S16

7
8

SIS
Sl4
Sl2

9
10
11

FUNCTION

SET 00
SET. 01
SET 02

Sets data bit
in selected
regi ster;
c:orrespond i ng
indicator lights

S13
Sll
SIO

12
13
14

S9
s8
S24

15
CLEAR

ASSOCIATED
SIGNAL

Cl ears sel ected
registers (sheet 2)

SET 03
SET O~
SET 05 .
SET 06
SET 07
SET 09 .
SET 09
SET 10
.
SET 11
SET 12
SET 13
SET 1~
SET 15
CLREG

.
,
,
~

.

.!
>

..

5-152

89633300 0

PROGRAMMER'S CONSOLE
Input

See switches and notes on output signals.

Outputs
FUNCTION

LOCATION
SHEET
SQUARE

SIGNAL

ACTIVE

CNS aL
thru

L

Main data path

3

L

Main data path

3
3

eNs 7L
CNS OM
thru

eNs 7M
Notes:

!

A-2
8-2
C-2
0-2

!

a.

these signals are bidirectional when computer is operated
from the front panel.
b. these signals are inputs when computer runs under program
control.

Circuit Description
Each pushbutton switch is connected through a pull-up resistor and an
inverter to an open collector NAND gate used as an inverter. The open
coll ector outputs drive the CNS 1ines corresponding to the switch pressed.
When the computer runs under program control the main data path signals
appear at the pins carrying the CNS signals.
The indicator lights corresponding to the bit locations are lit according
to the signal on the appropriate CNS line.
Two auxiliary signals are produced as follows (these are used on sheet 2):
Condition C:

active high when anyone of the pushbuttons in this
circuit is pressed.
CLREG: Clear Register

89633300 0

5-153

U1
I
......

vee

U1

~

~

w
w
w

o':>
o

DETAILED LOGIC DIAGRAM

PROGRAMMER'S CONSOLE
CONTROL SWITCHES·· AND· I NO I CATORS .
SWITCHES AND OUTPUT SIGNALS
PANEL DESIGNATION
AUTOLOAD
MANUAL INTRPT.
STOP
MASTER CLEAR
GO
POWER
BREADPOINT STORE
BREAKPOINT
PARITY FAULT STOP
AUTORESTART
PROGRAM PROTECTS
TEST MODE
32K
65K
ENTER
SWEEP
SELECTIVE SKIP
SELECTIVE STOP
INSTRUCTION
CYCLE

CIRCUIT
S25
S26
S27
S28
S29
S30

SWITCH TYPE
Pushbutton{P)
TOClClle
(T)
P
P
P
P
P
T

S31

T

S32

T

S33

T

S34

T

S35
S36
S37

T
T
T

S38

T

SIGNAL
OUTPUT
AUTOLOAD
M.1.
sT0p CS
MCCS
G0CSW
PWR. SW

AUT0RSW
PRTSW
TM!W
32KW
(32KW)
ENTER
SWEEP
SLK
INSTEP
ST0pcs

NOTE:
The signal PRGST is transmitted to the console interface board. It is
used to stop the computer under certain conditions.
1. When the cyclic parity error signals cePE is active and the PE stop
switch is set.
2. When the BEAC signal is active and the Breakpoint stop switch is set.
BEAC is active when the contents of the Breakpoint register equals the
CPU memory address.
89633300

n

5-155

PROGRAMMER'S CONSOLE (Cont'd)
3. When the BEAC and 0PST signals are active and the Breakpoint store
switch is set.
4. When the SLSE signal is active and the selective stop switch is set.
INDICATOR LIGHTS AND INPUT SIGNALS
PANEL DESIGNATION
INTERPT ENABLED
PROG. PROTECT
OVERFLOW
PROTECT FAULT
PARITY FAULT
CPU I.NACTIVE
INSTRUCTION
INDI~ECT ADR.
INDd
OPERAND
POWER
~.

CIRCUIT
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
DS9
DS10
DS34*

-

-

INPUT SIGNAL
EINTB
PRT BIT
0VFL
PRFIND
PEIND
SEN
RNIB
ADDR
RIND
0PIND
PWRIND
CCPE
0PST
BEAC
SLSE
PWRSW

* Indicates dc power switch on.

5-156

89633300 D

...

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en
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FOR PWA PIN 89985400
FOR PWA PIN 89602068
U1

I
.....
U1

"

.........
U1

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.....
U1

00

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SIDE

.

SIIE

one••1l

\0

USED WITH PWA

PIN 89987600

AND PWA

PIN 89987700

PleirED

''.''lI0II Alltt .. ''':''

V1

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IIIINI
MJ SWITCH

UlltLIU

V1
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DETAILED LOGIC. DIAGRAM
ANTI-BOUNCE CIRCUIT
.......... 0

•

~

l~-",,~~SIOOI ~TATuM

OFF SHEET

o

DUCIIIPTION
CLMa

LOCATION
SHEET
4
3
2
A-I
A-3
II-I
A-2
D-2
I C-4

1

IIIEFEIIENCE LETTE"

0'

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11~5591A I-I ~'Hr'f1

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!!Q1!!'
I. CI-C7 ARE InF.
2. ALL RESISTORS ARE O.2t1 WATT tI...
3 RI- RI7, R34 .. RtIO AND R97+R103 ARE 180 jlHMS
4. R18-R33 ARE 330 IIHMS.
IS. Rtll-R96 ARE 1000 !tHM8.
6. R104- RIIO ARE lI60 IIHM8.
7. LD 89982800 REFERENCED ON 5.11.4 IS LOGIC DIAGRAM
FOR ANTI- BOUNCE CACUT S\B-ASSEMiIIY
B. LOGIC FIlS RlN 89640300 RE\IIQIKED TO
PIN B99B76OO BY FCO CKI'I3I

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C18
IInFC20
-

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CI7

lOY

GN~~--~--------~

~

-=-

FOR PWA

1...-----tl@NIJ-.o-

Interrupt Lines

Locat ion'
Sheet
Square

+5V

P2A31

GND

PI Bll

GND

PlA29

GND

P2A03

8

A2

GND

P2821

8

A2

Vcc

Lo~ic

Ground

89633300 D.

ALU

(drawing 89614300)

Outputs
--.,
Signal

I

.. ..
~

~.~

,. '--'

Active

'

...

- ..

Connector!
Pin
..

~,

...• -

. '-

--,~---.

~

~

".. . ..

..

-~.-.

. .. _.- ..- .......

~

Location
Square
Sheet

Function
,- ................ ," -.-." -,

..•. -.'

......., ..,........." ....,' ......

2

C2

PIB12

2

B2

H

PIAll

2

B2

Q02

H

PIA08

2

B2

Q03

H

PJB09

2

B2

Q04

H

P2A24

3

82

Q05

H

P2B28

3

B2

0.06

H

P2B25

3

B2

0.07

H

P2A28

3

B2

WEi'

L

P2B29

3

C2

XGQ.

H

P2AJ7

{X}

{Q.}

3

D2

XSQ.

H

P2B18

{X} < {Q,}

3

D2

flAOO

H

P2A05

4

B2

"AOJ

H

P1802

4

82

flA02

H

PIA30

4

B2

"A03

H

P2B04

4

A2

flA04

H

P2A23

5

B2

"A05

H

P2B24

5

82

flA06

H

P2A22

5

82

H

P2B22

5

82

Q30

H

PIB08

QOO

H

QOl

'A07

-.-- -.....

89633300 A

QOO-Q.OI-Q02

Q register bits

QO3+Q.04+Q.05+Q.06+Q.07
>

Gated
A register outputs

--

5-173

ALU (drawi.ng 89614300)
Outeuts (cont'd.)
Signal

Connector/
Pin

Act ive
--'--'
-.~.~

Function
.-~

AOo

L

P2A27

AUG07

H

P2B08

AEZ

H

PlB16

XSEL07

H

P2A19

SHA

H

A07

..........

Locat ion
Sheet Square

",

Least significant bit of
A register

5

A3

5

Dl

4

A3

5

D2

P2B26

6

C3

H

P2B23

6

C3

Q7A

H

P2BOI

6

A4

CNSOO

L

PlB31

6

B2

CNSo.l

L

PlA31

6

82

CNS.02

L

PlB29

6

82

CNS03

L

PIB2a

6

C2

CNso4

L

P2Bl2

7

C2

CFiSo5

L

P2All

7

C2

CNSO~

L

P2Bl3

7

A2

CNS07

L

P2814

7

A2

GM

H

P2803

7

83

PM

H

P2AOI

7

83

6

82

6

82

GL

H

PL

H
.....................

5-174

M""._'"

...•. ,'

AOO -m-AOf-A63-A04 -A05 -A06 -A07
X selector output bit 7

eNS data bus bits

Carry generate
>and propagate

f

I PIB21

I
...1.

PIA2)
"

• •¥ ' "

' ••••••••••••• -

. . . ~ . . . . . - . - . . .- . , . - ,. . . . . . . . . . . . . . -~, . . . - . - - " "

89633300. A

ALU

(drawing 89614300)

Outputs

(cont'd.)
.------ r-' _ ..-_..._......... ..•...

Signal

Active
--~~~---

..

-,,~

Connector/
Pin
- .... _-'-' .,-- -..

.'.-."

'".

__...... _.._._--_......._...

__

....

_

Function
. __ w_... ____ .. ,......_.
~_,

"W_ . _ . _ _ . _ ••

.,,

-._..._Location
Sheet Square I
...•.__ ...... _--.. -_ ........ -....... ~

_... ............. -- ..............

I

_._.~

__• _ _ _ _••

"",~

."

TA02

L

PI BOt,

8

Cl

TAOl

L

P1A04

8

Bl

TAOO

L

P1B02

8

Bl

GS

L

P1A02

8

Bl

EJ

L

P1BOl

8

Bl

AlUOO

H

P1B24

ALUOI

H

P1B30

7

ALU02

H

P1B27

7

ALU03

H

P1A21

7

ALU04

H

P2Bt7

ALU05

H

ALU06

'1

7

7

D4

P2A16

7

C4

H

P2A15

7

c4

ALU07

H

P2B15

7

A4

ALU07A

H

P2B02

7

A4

ALUOA

H

PIA27

89633300 A

>ALU signals to bus

.....

5-175

\J'1

•

~

/IFF SHEET
REFERENCE LETTER
A
B
C
D
E
F
G

K
L
M
N
P
R
S
T
U
V
W
X
Y
Z
0

-

AA
AB
AC
AD
AE
AF
AG
AK
AL
AM
AN
AP
AO

2
D-I
C-I
B-1
A-I
D-2
D-2
D-2
D-2
A-I
B-1
C-I
D-I
B-2
C-3
D-3
D-4
B-3
D-3
D-3
D-3
D-3
A-3
D-2
. D-2
D-2
C-4 ;
B-4
D-4
B-4
A-4
A-4
A-4
C-4

IJFF - SHEET REFERENCE
SHE! T I..8CA
3 4
5

DIN

6

7

8

B-3
B-3
8-3
B-3
D-2
D-I
D-2
D-2

D-4
C-2
B-2
D-2
D-2
B-3
B-3
B-3

A-4
C-3

2

3
B-1
A-I
A-I
B-1
C-I
D-I
A-2
A-I
A-3
A-I
SA
C'NTINUES fIN SHEET 9

B-3
D-3
D-3
D-3
B-4
C-4
C-4

B-4
D-I
C-I

8-4

~

C-4
B-4
B-4
B-4
B-4

A-4
A-4

B-4
A-I'
C-I
D-'
B-1

4

5

. AR
AS
AT
AU
AV
AW
AX
AY
AZ

C-3
C-3
D-3
D-3

D-4

--~

----

A-2
8-2
D-2
D-2

--_ .. ---

C-I
C-I
C-I
D-I

----

83
Iyee

C2-:'-CIO
88nF

CI

B-4
B-4

•

7

B-4
B-4

+ BV )UAoi!!

GND)PlBlI
GND)PIA29
'GND)P2A03
GND)P2B21

8

33~

IOnF

R53
tIC

R52

IK

H

-

"TE: ALL RESISTeRS ARE O.25WATT 5%

...............
..........

UllLUS

00
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W
W
W

o
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one--.

R.Cl'IED

LOGIC DIAGRAM

z
f1FF- SHEET REFERENCES
(C INTINUEO FRfM SHEET

00
\.D
0'

w
W

\oN
0
0

J

2

I
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88
BC
BO
BE
BF
8G
BK
BL
BM
8N
8P
8R
8S
8T
BZ
BU
BY
BV
8W
BO
CA
CB
CC
CO
CE
CF
CG
CK
CL
CM
CN
CP
CR
CS
CT
BX

,

4

0-2
0-2
0-2
0-2
0-2
A-'
0-'
0-'
0-'
0-'
C-4
0-'
C-4
B-4
C-4
0-'
C-4
0-4

6

7

8-4
B-4
B-4
B-4

T

T

I

A-I
8-1
C-I
0-1
8-2
B-2
B-2

lo""IDATiiICHG1_

8

T

1

II

T

1

~

0-1
2

C-I
CU
CW
tv
CX
CO
CY
OA
DB
DC
DO
DE
OF
DX
DY

A-I

A-I
B-1
C-I
0-1
B-4
B-'
B-'
B-'
8-'

B-'

C-4

0

II

0-1
C-I
B-1
A-I
0-2
0-2
0-2
0-2
0-2
A-'
0-3
0-'
C-'
0-'
8-4
0-'
B-4
B-4
8-4
0-'
C-4
0-4
B-2
B-2
B-2
B-2

REVISION II£COIlO

D£SCRIPTION

I.Evl ECO

,

4

II

B-2
B-'

I~

•

.L

6

7

C-'
B-'
C-'
B-'
C-I
C-2

C-4
C-4
C-4
C-4

I

I
I

.

D-2
A-I
0-2
D-2
D-2
C-4
D-I

0-2
A-'
0-2
0-'
0-2 I

I

II

I
C-'

A-'

A-'

0-'

0-1

B-1
A-I
C-'
B-4

.

I C-4
I B-1

I

I

IJ
DETAILED LOGIC DIAGRAM
ALU

V1
I

......
......

.oI!l

"&

"

ICOD. IDENT

IC I

DWG NO

AQ'::14",nn

..ISHEl"

J

n

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--"""-

~

(drawing 89614300, sheets 2,3)

ADDEND REGISTERS AND GATES
Function
This section contains the following circuits:
the addend registers Q, P, M;"
the X register which is used both as an addend and augend register;
the addend gates and the comparator for comparing the X and Q register
contents.
Description
NOTE
As in the rest of the ALU, one board accommodates the circuitry
sufficient for eight bits and therefore two boards are used. In
the following the numbers refer to the lower eight bits 00 through
07 (ALU slot location 25): for the board dealing with the upper
eight bits (08 through 15) "increment the bit number by eight.
The Q, P and M registers store the information selected by the shifter (refer to
sheets 6,7).
Each one is timed by a separate clock signal (QCK, PCK, MCK)
generated on the Timing board.
The P and M registers are reset by the Master Clear (He) signals, the Q register
by its own clear signal (CLRQ).
The Q register outputs supply the A/Q channel
bus through open collector buffers U36, u48.
The three least significant bits
of the Q register are also sent, in complement form, to a three-input AND gate
(U49/6) to produce the signal Q30 - QOO·Q01·Q02.
This signal leaves the board
through an open-collector driver.

5-178

89633300 A

ALU

(drawing 89614300) sheets 2, 3, cont'd.

The five higher bits of the Q register (the W field) are used to produce the
function WEZ = Q03oQ04oQ05oQ06oQ07 at U35/8.
The signal, from the most
significant ALU board, is sent to the A/Q channel through the console interface
board.
The WEZ and Q30 signals from both ALU boards are used to sense when
the contents of the Q register is zero (see Console Interface sheet 6).
The X register and its associated selector are described on pages facing
sheets 4, 5 of the ALU circuit.
The comparator U54, u62 compares the
outputs of the Q register with the complement of the X register.
This
comparator produces the signals XSQ and XGQ (XQ) which are sent to
the console interface card.
This comparator is used only during divide
instruction.
Because the absolute values of X and Q must be compared and
the X register content is always negative during the divide instructions,
the complement of the X register content is input to the comparator.
The addend selector gates select the outputs of one of the addend register for
transfer to the ALU under control of the signals QTADD, PTADD, MTADD and STADD.

89633300

A

5-179

...

V1

v

I

Iii:EL I

t~C.PARA~R

g>

VCC

R44
IK

4Z~ 8
4

I

4~
2

Z
4 524

II

--.:

a

~
A-aGI

GI
Aaa

~3
3 E

G2~3
~aG3Ac8~

CK

1,4,

P2AIli

I

5A8(ID

M-REGISTER

Ill!

"lit

IN. C

~RRGTR
520
U47

r--! co.

I~

r8

r;q f!---®

14 4 8
II
I
9 2 A-a G!I
I

~
~

,.."

6.3 F
OTADD" P2A2a
XTADD" PlA09

A>-t~

I

3

3 K
MTADD Plal4

>

I

~~

~]E
i:....-

3 AN
49

1
1

:~

IJ. C
-..RRGT
520
U46

~

COo

~'"&'

23

500;-- 7

.....!
4

6

co;- 10I
13
e;;- 1514
12

3 AE
PCK'" Plal3

1

-

:~
m"

4.5.6 AG

4-~
CO.

4,6 @

12CO;-~

&
0'

K

-=-

3

t~5 ~
180

2~4

II

10

U64

8

"'IV

PIB08/030

..'

~

R28
180

PlAOa 01 .010

~

II

PlB09 0,.0..

12 I - -

3

,

2-~

PIAIL,O 0

'

3 a
4 r.:!o.
5
4\:11" l!. a UI4
9
10

»

-

a
~
atr-I

a

~L

~8

Ir-r-13 a~
213 a
41-

~

~

4

00

II

P2B27

•

Ie

•

~

J

II

-

\n
I

32KW) P2A29

2

f-

ALU

(drawing 89614300, sheets 4, 5).

AUGEND REGISTERS AND GATES
Funct ion
This circuit contains the augend registers A, Y and the augend gates; as well
as the X register, which is used both as an augend and addend register.
Des c rip t i on
NOTE
As in the rest of the ALU, one board accommodates the
circuitry sufficient for eight bits and therefore two
boards are used.

In the following the numbers refer to

the lower eight bits 00 through 07 (ALU slot location 25);
for the board deal ing with the upper eight bits
08 through 15) increment the bit number by eight.
The A and Y register store the information selected by the shifter
(refer to sheets 6, 7). Each one is timed by a separate clock signal
(ACK, YCK) generated on the Timing board. The X register stores either
the shifter outputs or the MX outputs of the memory control board. The
choice between the two inputs is made in the X selector (U53, u61) under
control of the signal XEZ from the I/O interface circuit.
The MX data from the memory control board is the memory output during a
read memory reference cycle: MXOO through MX07 for the ALU board dealing with
the least significant bits, Mx08 through MX15 for the ALU board dealing with
the most significant bits.
The MX data 1 ines are terminated in 330 ohm pull-up resistors on the ALU boards
The A and Y registers are reset by Master Clear (M[) whereas the X register
has its own clear signal (CLRX).

5-182

89633300 A

ALU

(drawing number 89614300) sheets 4, 5, cont'd.

The outputs of the A, Y and X registers form some of the inputs of the
augend selector gates. The outputs of anyone register are transferred
to the augend gates under control of the signals ATAUG, YTAUG, XTAUG.
The other control inputs to the augend selector gates are SG, SI, SF and
DELTAUG.

The following figure shows the augend gate control signal connections.

Notes (to Augend Gate Control Signals):
I.

2.

89633300

A

j are bits 01 : 03

are bits 04

~

07

on the LSB,
on the LSB,

bits 09
bits 12

t
t

11 on the HSB.
15 on the MSB.

5-183

ALU (drawing 89614300) sheets 4, 5, cont'd.

SF

SI

,'"
,"

a
~

XTAUG ,'"

a

H

YTAUG

,,

ATAUG ,"

Xo

,

~

a

Yo

BIT 0

~

a

Ao

~

,

SG

I

E

,'"

a

I

~

a

H

Xj

r\.

~

BITS j

a

Yj

~

a

Aj
,

~
~

E

a

I

~

DELTAUG ,"-

a
Xi

I-

BITS i

a

Yi

a

Ai
,

5-184

,

~

E

Augend Gate Control Signals

89633300 A

(drawing 89614300) sheets 4, 5, cont'd.

ALU

The augend selector gates can, with the aid

o~

the above signals, transfer

the content of the A register, Y register, or X register to the ALU.

These

gates can also transfer part of the content of the X register with the
upper bits zero, as follows:
~

--.-,_.,,,.- ._-

Transfer Signal

I

-

-

X Register Bits
transferred

- .....-... --- ......... -.-.-~

.....

Remarks
. Rema i n i ng X-Reg i s te.~..~~~s :

~
I

DELTAUG
i

DELTAUG

I

00 f 03
00 .. 07

L- _~~~

Ii

12 bits recognized as zero

I

8 bits recogn i zed as zero

~_O_b_~_~_~_~~~n-extended acc~_~.~_I_~_9_!

+ 07_ _ _ _-A._ _

The output of the augend gates is active low.
The following table summarizes the selection of the constants:

r

•__

Con t ro 1 Signa 1

89633300 A

0-.. --_--

......._----,

Constant Selected

S I-SF

+1

S I-SG

-1

SI-SF-SG

-0

ATAUG-YTAUG-XTAUG-ST

+0

I

5-185

(drawing 89614300) sheets 4, '5, cont'd.

ALU

The following truth tables show the augend gate control signal configurations
for both ALU boards and the corresponding augend gate outputs.
AUGEND SELECTOR - MOST SIGNIFICANT BOARD (MSB)

,--- --A~~~~ 'Gate -C~'nt'~~i '~~d _..............-----.-.-.-.. ---._.,. -~U~~~d
j

'~~t~ ..~~~.~~~

;~::;H (;;:~::rr:S:~riD:~;~~ 1 (::) (::E) (~~) - (a~t1Y~_laN)
H

HL

1

L

L

I

L

I

L

L
L
L

X07
X07
X07

H

L

H

L

H

L

L

H

L

L

L

H

H

H

L

H

L

L

X07
X07

L

H

H

H

H

L

,

i

L

l,.___,. i

L

:

!

A register
Y register
X register
Extended sign bit of /}.
00 16

i

L

_!

FF16
...-."'

........

-

AUGEND SELECTOR - LEAST SIGNIFICANT BOARD (LSB)

-----.. . -.--....--... -----....---

-.---~----

Augend Gate Control and
(Corresponding Signal)

I-------o,-------r-.~-

. ATAUG
( (ATAUG)

YTAUG
(YTAUG)

.. - ... ---- -...........,..........--..

XTAUG
(XTAUGL)

. -.--.--------r--.---..-------.

f"·"" ... .

DELTAUG
SF
(DEL TAUG) (SFL)

~~~~~ff~-

H

L

L

H

H

L

H

L

H

H

L

L

H

H

H

L

L

H

L

H

L

L

L

H

H

L

L

L

L

H

L

H

, _ _ _ _--'1--. _ _...._ ....

L

I

L

~ I~

Augend Gate Output
(act ive low) . _ - - 1

A register
Y register
X register
lower 4 bits of X,
"0" extended

.... ~~ ...

--..... --.... ,
~

The signals ATAUG, XTAUGL, XTAUGM, and SIL are produced on the decoder board.
The signals YTAUG and SGL are produced on the timing board. The signals
SFL, 1M, SE, and DELTAUG are produced on the I/O interface board.

H = active high,

5-186

L = active low

89633300

A

,

I

ALU

(drawing 89614300) sheets 4,5, cont'd.

The A register outputs supply the A/Q channel bus through open-collector
NAND gates.

The outputs of these gates are controlled by the A/Q channel

control signal, AQC, from the I/O interface.
The A reg i s ter outputs are wi re.-ANDed after i nvers ion in Ul3 and U3 to
produce the signal AEZ.
A register is

This indicates whether the content of the

z~ro.

This circuit includes a fl ip-flop (U51/6) which stores the least
significant bit of the A register.

The input to the flip-flop is the

least significant bit of the shifter. It is clocked by the A register
clock and cleared by Master Clear

(MC).

Its output is used during

mUltiply instructions where this bit must be stable early in the cycle.

89633300

A

5-187

,

v

\J1
I

x

PIAI8
., .....

5

!!r

00
00

PIAU5

~

ICC

M
M
M
M
M

M

MX
MX

5

RH R6 R7 R8
330 330 330 330
PIAI6

II 0

10 I

i'

9

13 I

•

3

0

1

15

I

____

""--

5 8G

Vee

!<;!
IK

J
1iJ

I" R

1,6,8

520
12 U60
CDs

~JE
"---

L 2

~2

I

~

l...®-i

209~

~18
B

~

I

~]E

----

~I""r"'"'j"
13al~

~~7
~
,

2
G

2

=
=

2

K

2

I..

PI819

1

~

tJc
R

~~
5 CD.
7
~

feD- ~
10

ro2

13

s

21-

15
~

2T

I ~
a
2 204
'-=I U3O
4

~-

9 I-~_
121-~_

~14

L.....-

\N

\AI
\N

oo

cf

RI6
180

a
41-

3

P2A05

6

r@" P2 A~

26
10

II~~

PIA30

,fAO,,,A8

iii, JAg
"

~_6P2B04

II

131---:.~

15

~6

8

~IUI3
3
_~

1 ........

RI4 RI3
180 I f - - ®
CS I6

PISI6

~t6

5 a U28
6
BIT-I
91-·
10 a

Vee

RI5
180

I.....-

lt~
,,~

00
\D
0'\

fo--!

~2
5@-

YGTR[
520
U44
4CDo
2

12

!

fA2 ,iIAiO
(JA3, iIAii

25

SE(MI PlB22
SFL '

l

T

~I..,..!h ]E
I;:;::
13 a I
209M
2
3 a
4~

5 a UII
6
9~
I( a

AL
AM

~I
81T-0

6

~lE

~5

i....-..

~Vcc
R49
IK

l~l81T COMPUTERS l~1

• ............

DETAILED LOGIC DIAGRAM

r

OOE 'DENT

IC I

OWG NO

ALU
):0

,!

8
r=:..
BIT-2~

5 a UI2
6
9110 a

10

r!co.-~

:

I

3 a

4~

~

A

~
IIT.-3

9 I10 a

.~

~~15

v.

a
415 a U29
• 6

5~

Y-REGISTER

F'

.

5 BL

N 2

AUGEND GATES
11""r--13 a I
21- 209H

.ft>-'!

XTAUG~~
;® XTAUGM

P 2

~2
4~2

~I()- 4

PI818

~
~
~ PIA20

6 I

U45
13 CDs

;@

5 8F
5 8K

12

2

~~7

"• PIAI9
V

m

'Co';"'- ~2
10
~2
5tco;-- 7

s

~1()-12

• PIBI5

T

17

ll:~:l'

CLRX~~
MC (Ll

189
U61

'!J

.. , 2

::

J

I '..

4

89614300

J

...

JI

I GI
• ~X-SElECTfR
GO

QC)

,4 C8

\D

0'

....

\N
\N
\N

i4

~

• .':t': ..

o
o

Mli1M.MX1L,-P2..

__,....

:I>

___.......

,~~ "
II 0I '
10
I

I

l

"'aiO

S.7@

"• "
',7 IX
3,1 8W

,
I

fa

~

Ilo.-H...

4,!1
T

r=

T

153

r='
¥--@.o!'b'
~
~.
.,..
...
COl

_

41jjGL-l
P2A2i~

ATAUG ......

ECO

.,-PI811

"''''

_

.. •

(MIHIGH

.'
910 ,

,;..o.1!...J
1r:T7'1
r----T.eJ':"l
~I.I-

,,-

4~a ~I

5

l

~

a ..3
' ,..

~~

,,~.........
~.~
co;- I>L
1

.,.

ISf=--~...JQ~
l.!!r-CD.

CO, .

I

IS1146H
UI8

f

~

8

U Wi"
~

,n-o

"""

a

~U
10

111-1

~~

. 'j~I~'
.~
~~
,&/1'
I;----'~I
~a
6

1

" ,,,,,,
~.
,lA4"AI2

r-C
]
:~X-REGJSTER'

4 8T

]MUX

__"'""'"

V1

v

DA 4

al

U22

I

BIT-4

a

4ill3

'-'-----PP

_FF - SHEET REFERENCE

<7'

\oN
\oN
\oN

REV

REVISION RECORD

SIGNALS
Fo3
Fo5
Fo&
Fo7
FoB
FoB
FoO
FoE
FoF
FI .. I
FI.8
Flog
Flo2
FloO
FI-A
FI-E
F.O
Fot9
F.A
F.Y
F"5
Ftk 7
F .. C
F .. D
F"'F
RE1F
ITR
11116
RNI21
IIIPE
CSM
1,o6+7+F
RlR2.R3.~

RNI 12
RNIII
F"QFI-2:
fIIPO
RNI22
MDSE
MOSE
~

ENI2E
fIIDD 2
!liDO 2
!liDO
fIIDD

"

2
B-1
C-I
B-1
B-1
1-1
8-1
A-I
A-I
A-I
1-2
B-2
B-2

SHEET LjlCATI_N
4
3
5
B-2

A-3
A-4
A-4

I

&-3
B-3

8-3
B-3
A-3

8-3
B-3
C-2

C-I
B-4

8-4
A-2
A-3
A-2
C-I
C-I
C-I
C-I
C-I
B-1
B-1
A-I
A-I

&
0-3

0-4
C-3

fIIFF -5I£ET
REFERENCE
LETTER
DB
DO
DE
OF
OH
OG
OJ
OK
DL
OM
ON
DP
DQ
OR
OS
DT
DU

0-3
C-3
B-3
A-4

C-3
C-3

C-4
C-3
C-2

0-3
B-3
B-3
C-3
B-2
0-4
0-4
0-3
0-4
0-3
B-4
A-4
C-3
C-3
A-3
8-4
A-3
B-2
0-2
0-1
0-1
B-1
B-1
A-2
A-2
A-3
A-2

0-3
0-3

C-3
C-2
C-2
0-4
A-3

A-3

8-4
A-4
A-4
C-3
C-3
B-2

C-3
8-4
8-4
C-3
C-3
C-3
0-4

0-4
0-3
8-4

C-3

SIGNALS

2

ENt20
RE 18
MOS1
FIE23
OELTAUG
10+SHI

SIL
U+CNTE2
CSA

VIm
MIIT
CSQ
SHI

SHEET ujCATI N
3
4
5
A-I
B-2
8-4
C-4
C-3
0-3
0-3
B-4
B-4
A-4
0-3
A-4
C-4
C-2
C-I
C-2
C-4
B-1
8-1
C-I
C-I
C-4
C-4
C-4
A-2

~

&
B-3
0-4
0-1

III

8-4
8-2
0-2
B-3
C-2
B-2
A-4
A-4
B-2
8-4

I

C-4

-

0-4
0-4
C-3
A-3

C-4
C-3

~

C-2
8-2
0-4
B-3
0-4
A-3

C-4

0-4
C-3

j!L~~ ~~~~R~ l!1!

...

•

JaIl ...

DETAILED

LOGIC DIAGRAM
DECODER

CODE 'DENT

IC
.

OWG NO

89614900
SltEET

7

I

lAY

E~£~~

(drawing 89614900) sheet 2

INSTRUCTION REGISTER AND FIRST LEVEL DECODERS
Function
This circuit consists of the instruction register and the first level of decoding
logic.
Ineuts
SIGNAL
'-'--'--'HDEL
IRCK
HXOO
HXOI
HX02
HX03
Hx04
MX05
Hx06
HX07
Hx08
MX09
HXIO
MXll
HXI2
HX13
HXI4
MXI5
CLRIR
......

NOTE:

CONNECTOR
PIN

ACTIVE
H
H
H
H
H

H
H
H
H

I

H

I

H

!

,

H
H
H

I
I

I

t

I

PIA~3

I

PIB14
PIB15
P2B05
P2A08
P2B.08
P2A05
PIA31

I

H
H
!
i

j,

H

P2AI8
PIA25

I

H
H

PIB20
PIA21
PIB16
PIA16
PIAI8
PIA20
P2B19
P2B17
P2AI9

,i

I
I,.

\
....._-.........
-..

LOCATION
!
SHEET SQUA~~

FUNCTION
1:1

f ie~ 1d ze ro from memory

2

Instruction Register Clock

Ii
!

I
I

>Data read from memory

l

I

,,
!

!
i,

I

\

I
I

;
j

I,

I

I!

i

Clear Instruction Register
.___.-----l...._

2

04
04

II

c4
c4
04

,I

04
c4
B4
c4
B4
B4
B4
A4
A4
C2
C2
C2
C2
A4

An alternative notation, emphasizing the significance of the bits of data
read from memory employs the letters L (less significant) and H (more
significant).
Thus the following pairs are identical:
HXOO - HXOL, HX07 - HX7L, Hx08 ~ HXOH, HX15 - HX7H.

89633300 A

5-215

I

!
I
!

I

I
I

~

:,
;

,

i
I
\

l
I

!

I
I
I

!

1
I
1
;

;

(Drawing 89614900) sheet 2, contld.

DECODER
Outputs

ACTI~E~F. CO~~~CT.oRI"'·-·_-.-_'-_-_.-_ .--._.'-. --:~CT:------ -::~~CAT!1~ARE

1_ _

5IGNAL

1 __

1

R1

: --H

R2
R3
R4

:

I

, -.- -Pl~27

H

P1A28
P1A24
PI B28

10

H

Pi B13

11

H

12

H

PIB05
P1810

13
14

H
H

PlAIO
P2B26

15
16

H

P2B24

H

17

L

DEl

L

DEL2

H

T1

H

T2

H

T3
T4

H

Of

L

02

L

03
00

L

165

H

P2823
P2A23
PJA14
PlA 15
P2A06
P2B09
P2A09
P2B06
PIB30
PIB31
P2B01
P2AOl
P2A22

5-216

H
H

,. I

--

. --, ',' ' ,

I

Fl field of instruction

I

register

--A3--""1

2

A3
A3
A3
03

!;

~

i

03
03
c3
C3
C3
C3

Instruction Register bits

•

I
I
I

H

L

I
I

I
I
I

C3
03

A field zero (stored)
see text

02

C1
OJ

F - field outputs

01
01

F - field content is

Bl

F - field content is 2
F - field content is 3
F - field content is 0 16
16 -15'

Bl
Bl

---_._. "-

I

A1

2

B2

---"-_ __
...

89633300

...............

A

(Drawing 89614900) sheet 2, cont'd.
D~~fr i pt ion

The instructlon register is a 16 bit register.
Its input is the data read from
memory through the memory control board (signals MXOO through MX15).
The
register is clocked by the IRCK from the timing board and cleared by
CLRIR from the console interface.
The register itself uses two types of components.
The Fl field of the instruction
register are high speed dual D-type flip-flops (U45, u46).
These are
used because the Fl field must be decoded early in the execution of the instruction.
The F field and ~ field are stored in quad D-type flip-flops (U39, U41, U47) like
those used in the ALU registers.
The outputs of the F field and the Fl field are
decoded in two four-to-sixteen decoders (U57, U58) each having sixteen active low
outputs, one for each possible input code.
Four outputs from F-field decoder
(OT, 02, 03, ~ which are active when F = 1, F = 2, F = 3, and F = D respectively,
(hexadecimal notation) are outputs of the Decoder assembly.
The DEL flip-flop, (U60/8), stores the signal HDEL from the memory control assembly
This signal indicates when the delta (~) field is equal to zero.
The flip-flop
is clocked by IRCK and cleared by CLRIR.
The output of this flip-flop is an output
of the assembly, through an inverter, as DEL (~FO).
The outputs of the instruction register fields aresunvnarized in the following table:
I

FIELD

."- -_....... -....... - ... ....

OUTPUTS

BITS

~

F
Fl
~

89633300

A

Tl, T2, T3, T4
R1, R2, R3, R4
10 through 17
----

12
18
60

·· 15

·· 11
·· 7

5-217

DECODER

(Drawing 89614900) sheet 2, cont'd.

The signal DEL2 is produced by decoding MX data lines.
DEL2

= MDEL-MXlf·MXlO-MX09-MX08 •

Its equation is:

(Fl=5)-(~=0)

It is used by the interrupt logic to sense the inhibit interrupt instruction and
prevent an enter interrupt sequence under certain conditions ~ee Console
Interface sheet 5).
The signal

123 = 17·j6 is produced by U38/3

The signal

165

5-218

= 16-15 is produced by U38/8.

It is used on the I/O Interface.

89633300

A

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Vol
Vol
Vol

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DETAILED LOGIC DIAGRAM
DECODER

REV

A

DECODER (drawing '89614900) sheet 3
ADDEND GATE CONTROLS
Function
This circuit contains the logic gates which generate the signals to control the
addend gates of the ALU (refer to ALU, sheets 2, 3).

Inputs

-

SIGNAL

CO~NECTOR

IN,

ACTIVE

L
i RE1F
H
ITR
H
RNI21
L
RNI12
L
I
I
N41
H
I, H
NO
;
RE1lf
L
,
CSH
L
I
RP
I
H
L
RNI22
L
RN 111
L
L
H
HOSE
L
ADR
H
fJDD2
L
JDD
L
CSP
L
ENI2E
L
ENI20
"" I .. - - .... -

1M

I

I

I

I

m
m

I

,"

5-220

I

".

LOCATION
SHEET SQUARE

FUNCTION

P2B28
P2B15
P2At5
P2A29
P2B30
P2B14 .
P2A14
P2A27
P2A04
P1A08
P1A05
P1B08
P1A06
P2Bl6
PIBOI
P1B07
P1A02
PlB09
P1B03
P1B18
P1A07

....... "........... ·.·e .. ·· .

04
04
04
04
c4
c4
C4
c4
B4
B4
B4
A4
A4
03
02
A2
A2
A3
Bl
Bl
Al

3
I

I
,,I
t

II
i

I
I

!,

I

I
- .. -......

. --- ,..-......

~-

...................... ....... "_ .......... -.- ...
~

J

3
'

.

.. .

.

89633300 A

,
;

·
'.

~

I

l
I

•

•t

I

DECODER

(Drawing 89614900) sheet 3, cont'd.

Outputs (cont'd.)
I SIGNAL

_. ___

I . ·_-"LOCAT ION

tONNECTOiC"/

I
.,_>_~~_

ACTIVE
. .____
._

MTADD

P1A17
P2B22
P1A19
P1A09

H

I QTADD
! PTADD
i XTADD

PIN

"..L.,, ___ • _'._ ._._ .'-,.-......... __ ........ .j..-.,

H
H
H

FUNCTION

_, ,_ ...•. '._ ,~.

_',~ •. '

....'•..

... J

:1

j

!

i

(

Addend gate
gating

,j

!..

Sig:~~__

I
I

SHEET .... ~~~AR,E
C3
01

3
3

L__ ~. __;:

Description
_--..

The logic gates receive signals from the decoder, (logic shown on sheet 2)
as well as timing signals from the Timing assembly. The resulting signa,s,
QTADD, PTADD, XTADD and MTADD, determine which register, if any, is gated
through the addend gates during each CPU cycle.
The equations of these signals are as follows:
XTADD =
+
+
+
+
+
+

ENI2·~DD

+

ADR-~DD-~DD2

~P-~DD-[(F=0)-(Fl=2,3)-RP

+ (F=S)]
~P-EVEN-[(F=D) +(F=0)-(Fl=6,7)]
RNI-EVEN-(F=0)-(Fl=8)-TS-T4
RNI-EVEN-(F=0)-(Fl=9)
RNI-EVEN-(F=8,9,A,B,C,E)
RNI-~DD-(F=O)-(Fl=E)

PTADD = CSP + ENI2-EVEN + ~P·EVEN (F=S)
+ ~P-~DD-[(F=0)-(Fl=2,3)-RP + (F~O)-(F~S) + (F=0)-(Fl=6,7,F)]
+ RNI-~DD-(F~O)-[DEL + R4]
+ RNI-~DD-(F=0)-(R2.R3 + Rl-R4)

89633300 A

5-221

DECODER

(Drawing 89614900)

sheet 3, cont'd.

QTADD = CSQ + MDSoEVEN + MD21 + MDI + ADR oeDD2
+ (F ~ 0)oN41oNO + ITRo jT6015
+ RNloEVENo(F=O)·(Fl=F)·T6
+ RNI·EVEN·(F=O)o(FI=8)·14
+ ep·EvEN· (F=4)
+ RNloEVEN· (F=F)
+ RNI oEVEN·(F=O) o(FI=D)
+

RNloeDDo(F~0)·(Fl=2)oDEL

+ RNI·eDDo(F=O)·(Fl = 6,7)

MTADD = CSM + RNloEVENo(F=0)o(Fl=8)oI3
The signal .16 = EVEN·T6 (see Timing, sheet 2).

5-222

89633300 A

..
00

\D

'"

\A)
\A)
\A)

o
o

»

V'1
I

N
N
\A)

......

V'1
I

N
N

-'='"

DECODER (drawing 89614900) sheet 4
AUGEND GATE CONTROLS
Function
This circuit contains the logic gates which generate the control signals for
the augend gates of the ALU (see ALU sheets 4,5}.

Inputs

I

LOCAT ION
-,
SQUARE

J

I, SHEET
ENI
MDSl
FS
DELTAUG
CSX
PRY
MDS2
IRJ
I
EI5
I
I'
CSA
I
QSX
i

H

AO

H

I

CNTE2

I

H
L

L
L

H
H
L
L
L

H

L

P1B02
P1A13
P1A03
P2B10
P2A21
P1B06
P2B04
P1B17
P2B18
P2B20
P2B02
P2A02
P2A30

4

I

I
4

D4
D4
c4
A4
A4
B3
A3
C3
C2
C2
B2
B2
B2

Outputs

~

XTAUGM
XTAUGL
ATAUG
SI L

P2A20
P2B31
P2A24
.
P1B191

..........._ _----I"---_._~ ____ ..

89633300 A

4

_L __.. ,____"__ '._. _...... __ _

A4
A4

~l
4

Bl

5-225

DECODER

(Drawing 89614900) sheet 4, cont'd.

Des.~ription

The logic gates combine the decoded instruction with timing signals to produce
the control signals XTAUGM, XTAUGL, ATAUG, and SIL.
The equations of these
signals are as follows:
XTAUGM =
+
+
+
+
+

CSX + ENI-eDD2 + MDS1-jDD
MDS-EVEN (Tl-QSX + Tl -AO)
ep-eDD-(F=O)-(Fl=E)
RNloEVEN-(F=0)-(FI=8)-T5
RNI-EVEN-(F=F)
RNleEVEN-(F=O)-(Fl=O,A,C,D)

XTAUGL = XTAUGM + DELTAUG
+ RNI-eDD-(F~O)'DEL
+ RNI·eDD-(F=0)-(Fl=2,3)
ATAUG

where

=
+
+
+
+
+

CSA + MDS2-eDD + ITR-EIS-16
ep-EVEN-(F=6,7)
RNI-EVEN-(F=0)-(FI=F)-[IS·16·(KO + 10) + 16-(IO+SHI)]
RNI-EVEN-(F=0)'(FI=8)-IS
RNI-EVEN-T3
RNI-EVEN-(F=0)-(Fl=9)

KO = Tf-T2·TI-TZi .
SH I = KO - (TO:'"15+rn
EIS = EVEN + IS

-

see Decode rs
see Timing 2.

SIL = ENI2 + ep·EVEN-(F=S,D)
+ ep·0DD·[F~0) + (Fl=6,7,F)+(F=O)o(Fl=2,3)"IRJ]
+ RNI-EVEN-(F=7)·PRY
+ RNloeDD-(F~O)-DEL
+ RNI·eOO-(F=0)-00D2-rs·(R4+R2)
where

S-226

IRJ (Internal Rejec~ comes from the I/O interface assembly_
PRY (Parity) comes from the Console Interface assembly.
89633300 A

00
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W

93.6
3(Cx)

W
W

ENl

I
PIB02

I

a

ODD

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o

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3,!5{ eM)

I""

I I

,
16

FIE~ P2B29

.6

I +

I

I

P"

PRy)PIB06

6

LhrI8------

8

DETAILED
V'I
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'-J

LOGIC DIAGRAM
DECODER

, I'

I .."'..~

",D."

(ATAUG

(SIL

DECODER (drawing 89614900) sheet 5
CONTROLS FOR ALU AND ADDRESSING
Function
This circuit generates the following signals:
ALU control signals SO, Sl, S2, S3 and M (refer to ALU circuits,
sheets 6,7).
Counter preset signals AD1, AD2 used on the Timing assembly to preset
the counter at the beginning of the effective address calculation
(refer to timing circuit, sheet 3).
The signal SHI.

LOCATION
... _~y_~~T..:....~O::.:.N:....-_ _ _ _. . . . . . _~IiEET_ S UARE
.{

5·

Mi52f

L

MOl
CSQ

L

L

AiW

L

P2B12
P2All
P2A10
P2B07

5

04
04
c4
c4
c4
B3

Outputs

M

H

SO
Sl
S2
S3
123
SHI

H
H

H
H
H

H

P2A07
P2A12
P2A18
P2A17
P2A13
P2A25
P2Bll

ALU Controls

::~ . . _.L_~___ L...: ::::
89633300 A

DECODER

(Drawing 89614900) sheet 5, cont'd.

The signal SHI is used both on the decoder and I/O interface boards.
equation is:
SHI = KO· (1'0+15+16)
where

KO =

Its

ITo IT- 13-14

This signal is valid during shift instructions.

Its significance is as follows:

Signal KO, and therefore SHI, is active when the instruction calls for a shift of
zero or a register shift of one place.
In this case the entire shift operation
is carried out in the RNI state and the ITR state is not used.
The equations for SO, 51, 52, 53, M, ADI and A02 are as follows:
SO = W9A + CSQ + M021 + MOl + RNI-EVENo(F=0)o(Fl=8)016
+ RNloEVENo(F=0)0[(Fl~8) + 171
+ RNJoEVENo[(F=8,B)+ T3]
Sl = G0CS + RNI-EVENo(F=0)0(Fl=8)017 0T6
+ RNI-EVENo(F=9,A)
S2 = G0CS + CSQ + M021 + MOl
+ RNI-EVEN-(F=0)-(Fl=8)-17 0T6
+ RNI-EVENo(F=9,A)
S3 = W9A + RNloEVENo(F=0)-(Fl=8)017-Tb
+ RNloEVENo[(F=8,A,B)+T3]
+ RNI-EVEN-(F=0)-[(Fl~8) + T7
M = AOY + SIL + OELTAUG + MOSE
+ RNI-000-(F=O)-(Fl=2,3)
+ RNI-000-(F~0)-[(Fl=2) + R4]
+ RNI -EVEN-(F=O)o(Fl=8)0T6-T7
+ RNI-EVEN-(F=0)-(Fl=9,O)
+ RNloEVEN-(F=8,9,F)
where

89633300 A

AOY is produced on the Timing Card
W9A is produced on the Timing Card

-

see Timing sheet 3.
see Timing sheet 5.
5-229

(Drawing 89614900) sheet 5, cont'd.

DECODER

AD1 = R1

5-230

$

R3 (!) [(F1"0)' (R4.;m 'DEL]

89633300 A

"9

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00

\.D
0'
W
W
W

o
o

W9A~

P2BI3

GoeS>

P2B25

'

, 4

r;,

(j()

r

t"----:~l4~H~6

P2AI3

(S3

1'''

..c,"c

(SO

»

..

20

(

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23

6

8

I I P2A07

(M

P2

4.6

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I"

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8

DETAILED

V1
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LOGIC DIAGRAM
DECODER

...

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(AD2

DECODER (drawing 89614900) sheet 6
REG ISTER --etOCK CONTROLS
Func t i on
This circuit generates the register clock controls WP, WA, WQ, WM, WXLl;
bit bucket signal (BB) and the signal FIE23.

the

The WP, WA, WQ, WM signals are used on the Timing circuit to generate clock
pulses for their respective registers (refer to timing circuit, sheet 3). The
WXLl signal is part of the condition for writing into the X register.
It is
transmitted to the I/O interface board where it generates the signals WXL, WXM.
Inputs
FUNCTION

i.._.
I

I

(

BBCK
WRQ
WE
BX15
MOSS
Q15
CRQ
JRNI
X15

H

H
L

H
H
H
H
L
H

PIA22
PIAll
PIB12
P2A28
P2B27
I
PIB28
PIB26
PIA04
PIB22

LOCATION
SHEET SQUARE
6

•

iI
I
1

!

I

6

04
04
04
04
D4
c4
B4
A4
C2
C2
C2

Outputs
WXLl

L

BB
WP
WA
WM
WQ

H

FIE23

H

5-232

H
H
H
H

PIA12
PIB25
PIB04
P2A26
P2B03
PIB29
P2B29

6

C3
01
Cl
Bl
Bl
Bl

6

01

!

(Fl=2)+(Fl=3)

89633300 A

DECODER
Description

(Drawing 89614900) sheet 6, contld.

The BB flip-flop (U60/S) stores DBB from the console interface.
This signal
is used during multiply and divide instructions (see Console Interface. sheet 7).
The flip-flop is clocked by the signal BBCK from the Timing assembly. The output
is used on the Decoder assembly and is also transmitted to the I/O interface.
The signal FIE23 = (Fl = 2) +(Fl = 3) is produced by the AND gate U13/8.
Is used on this assembly and also transmitted to the I/O Interface.

It

The equations of the register clock control are as follows:
WP = JRNI + CSP + CRQ·SIL + RNI·SDD·(F=O)·(FI=I)
where
CRQ is generated in the timing circuit and is active during the first part
of a CPU memory cycle. This is an 000 cycle in which data is sent from the
CPU to memory.
SIL is active whenever the P register is changed (incremented
or decremented) by one.
WM = CSM + RNI·EVEN·(F=0)0(FI=8)010
WQ =
+
+
+
+
+
+

CSQ + MDloBX15 + MD21 0Ql5
HDSoEVENo(CNTE2 + TI)
ITRo0T6ol5
RNloEVENo(F=O)o(Fl=C,D)

WA =
+
+
+
+
+

CSA + HDSoSDDo(CNTE2 + Tl) + MDSloSDDoBX15
ITRoEI5 016 + SPoEVENo(F=0)0(Fl=2)
RNloEVENo(F=0)0(Fl=F)0[15 016 0(KO + 10) + 16 0(10 + SHI)]
RNloEVENo(F=0)0(FI=8)012
RNI oEVENo(F=O) o(Fl = 9,A)
RNloEVENo(F~0)0[T40T3 + (F=C) + (F=7)oPEF + (F=2,3)oBB]

89633300 A

RNloEV~No(F=E,F)

RNloEVENo(F=0)0(Fl=8)011
RNloEVENo(F=0)0(FI=F)015 0T60(SHI + ~

5-233

DECODER

(Drawing 89614900) sheet 6, cont'd.

WXLI = WRQ·WE + MDS1·8DD·{X15 + Tl)
+ RNI·'DD·{F=0)·{Fl=2,3,8)
where
- WRQ is produced on the Console Interface and is high during the
second pass (EVEN) of each CPU memory cycle
- WE is produced on the I/O interface and is high during a CPU
memory read cycle.
Thus the term WRQ·WE clocks data read from the memory into the X register.

5-234

89633300

A

-

.

-

REVISION RECORD

27

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loA)
loA)

o
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REvl

PEf" PIA27
DBa< PlB21
BBC:"-' PlA22

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3.4@--i

4 DE

6
9

3.4 CP

10

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9

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6 146 2

J.

140
2U42

2BC

5~·3@

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PlAI2

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201
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8

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UI2

3.4.5 DD

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5 UI2

OJ 4

2,5 BL

U.5 y

2 BK

8
140
9 U42

8
2~
"-'

13 U!81

2.4
2.4.5 AX

MDSII

4

5

8
140

un

N

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I
9
10 8
II
UI
12
138

I~
1~6
U43

2f
8

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2 UI4

140H
5 U29

PlB03

13.....-

I

12 I~H
9 U49
Jif'".I>lAn4 10

1

8
13 140H
U23

& r!-

8

....

PIB04

"WP

---

12

2 B

-

[!3

II

C

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9
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I
13
2
3
4
5

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P2A26

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42
39

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6

43
Tp2B03

12 13

'ell

PIB21l

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J

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3
4
58
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DESCRIPTION

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10

2.3.4.5@-~
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PIB25

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3,4,5 CG

P822 I

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28
3
4

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3,5

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P2A28

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DETAILED

Of

11'llllil'II'~1t1

-

LOGIC DIAGRAM
DECODER

CODE IDENT

IC

OWG NO

IREV

89614900
SHEET

6

I

A

"Pages 5-236 to 5-240 are unassigned."

5-236/5-240

89633300 A

TIMING

The Timing circuits are accommodated on a single 50-PAK printed
wiring board. The logic circuit diagram is given in drawing
number 89617000, sheets 1-6.
The Timing circuit provides the main timing control signals for
the CPU.

This page shows typical timing sequences, gives state

equations and I ists the functional blocks making up the Timing assembly.
The circuit and signals are described in detail on pages facing the
corresponding sheets of the circuit diagram.
MAIN FUNCTIONAL BLOCKS
De s i g na t ion
Clock (oscillator and phase generator)
Even, odd flip-flops

_ISllown ~n-She~t
!
;

~

Counter
Interrupt timing, Y register control logic

3
4

Main sequence fl ip-flops

5
6
6

Auxiliary sequence fl ip-flops
Register clocks

89633300

A

2

1

..J ...

5-241

TIMING

(drawing 89617000)

STATE EQUATIONS
The following signals are produced
signa I JKCK.

by

J-K fl ip-flops clocked

EVEN:

JEVEN = 9002 + EXT
KEVEN = I
CLEARED BY MPC

900

J9DD = I
K9DD = fjDD2 + ffi
CLEARED BY SGI AFTER DELAY OF2 CLOCK PULSES

fjDD2:

J~DD2

RNI

JRNI
KRNI

by

the

= fjDD • EXT
K9DD2 = fjDD2
CLEARED BY MPC
= fjp - fjDD + EAD-(F=l) + ENI20
= RNI-9DD-(F=0).[(FI = 2,3,6,7) + 9DD2-(FI

=

E)

+ SH I • (Fl = F)]
+ RNI -fjDD-(F ~ 0) [(F ~ 1) + SHADD + ENI3] -KENII

PRESET BY MPC

5-242

89633300 A

TIMING
ADR:

(drawing 89617000)

JADR = RNI - ~DD (F ~ 0)- SHADR
KADR = 000 - (COUNTER = 0) - [~(F::":1~=-;4-,~6,-=C-,~E)~-~3:-:::2~KW~-~X~1-5]
CLEARED BY (MPC + ENI)

~P

J~P

= RNI - ~DD ·(F = 0)·[(F1 = 2,3) + ~DD2 • (F1 = E)]
+ EAD • (F ~ t) • (F ~ D) + ~P2 - ~DD + KITR + MOl

~P

=

~P

-

~DD + ~P

- EVEN - (F = 2,3)

CLEARED BY (MPC + ENI)
~P2:

J~P2
~P2

= RNI =

~DD

(F = 0) (Fl = 6,7) + EAD - (F=D)

~DD

CLEARED BY (MPC + ENI)
ITR:

JITR = RNI -

~DD

• (F = 0) - (F1

~

F) • SHI

KITR = ITR - EVEN -[(COUNTER=2)-SHI + COUNTER

~ t]

CLEARED BY MPC
ENI

JENI = [(RNI-m + INDIND)-(GSM + GSL)-WRQ·EINT]- [RNI-MX17A-MXJ7-PRFAl-[RNI-MXl7A-MXJ7-DFEO-DEL2]
-[RNI-PRTSW-DFEO-DEL2]

KENll: ENI2 -

~DD +

ENI - RNI - GSL - GSM

CLEARED BY MPC

89633300 A

5-243

TIMI~~

ENI2:

(drawing 89617000)

JENI2 = ENI " 0002
KENI2 = EN12"0DD
CLEARED BY MPC

MD21:

NOTE: MD21

MDS 1:

This signal is produced with simple logic gates

= 000

" (F

= 2,3)

" (COUNTER

= 21)

JMDS 1 = MD21
KMDSl = MDSl " 0DD
CLEARED BY MPC

MDS:

JMDS

=

MDSl " 0DD

KMDS

= 0DD

" (COUNTER

= 2)

CLEARED BY MPC
MDl

5-244

MDl

= ADR

" (F = 2,3) " (COUNTER

= l)

89633300 A

TIMING
TYPICAL TIMING SEQUENCES

(drawing 89617000)
c.

"00

_=-----tn'--__

---L_

RNI

'P2 _--1._-'

~

CPU
ICVClE

~

I MEMORY
I CYCLE

I

Jtorage Reference Instructions

'DO

RNI

AOR

I

I/JP2

1

,P
I

89633300 A

5-245

TIMING
Timing for Shift Instructions

(drawing 89617000)

e PLACES

SHORT SHIFT -

4

3

2

0

tlDD
RNI

ITR

I
I-

I

1NOTE I

j..!...I

NOTE I

~

I
I

n

OP

SHORT SHIFT - 6 PLACES

'DD
RNI

ITR

I

I

I-

INOTEI

NOTE I

tiP

~

n

~

I
I

I
I
I

I

For notes refer to next page

5-246

89633300 A

TIMltlG

Iimi ~ for

_~!.f.~-' nst':.u..c:..t io_n_

(drawi ng 89617000)

LONG SHIFT -

5

4

4

3

2

3

5 PLACES

o

2

0

"DO

I~------

RNI

I.

ITR

,P

______________________________~INOTEl

2- I

NOTE I

~

-I

----------------------~j.l~---

NOTES:
1.

Q shifted on condition
(EVEN·IS + lb· 15)
A shifted on condition
(flJDD 16 + TS o 16)
Q shifted on condition
[15·lb. (One place or EVEN number of places)]
A shifted on condition
[15·16. (One place or EVEN number of places + 15 16. (One or more places)]
0

2.

0

Timing for Input/Output Instructions

'DO
RNI

,P
: X+-P+X SE

89633300 A

HALT FOR
REPLY OR
REJECT

NOTE
' - - - -.....v
MEMORY CYCLE

5-247

\n
I
/'oJ

..r::-

IIFf' -SHEET REFERENCE

OO

IlIFF S""t:T
~EFERENCE

~.-

'--_

--

..

SHU:

2

LETTER

A
8

---.
0
E
F
G
L

8-2
C-3

III
N

8-2

P
R
5
T ..

C-4
8-4

U_

V

"---- - W ._-_.

x

C-3
D-3

__ .

Y
Z
AI.
1.8
-AC
---..
.
._-"AD-----.- .. - .
I.E
AI'
AG
AX
AL
AM
AN
AP
AO
AR
AS
AT

00

0'\
IJ.I
IJ.I
IJ.I

o
o

»

~
f

8-3
8-2
1.-2
8-2
8-1
1.-3
C-4
C-4
8-3

6

C-3
0-2

8-2

C-2

8-3

C-3
8-4
8-3
C-2
C-3

C-4
D-4
C-3
D-2

C-2

0-3C-I
8-3
C-4
8-4
C-4

8-1
D-4

----- 1----_.- -

AV
AW
AX
AY
AZ
AH
AJ

- ..-.-

.

8-1
1--_._--- --=-.-C-3

C-"

---

0-1

D-3
0-4
C-4
0-4

C-2
8-2
8-2

C-I
8-4
0-4
8-2
8-4
8-3

8-4

C-4
C-4
C -I
C-2
D-4
C-3
8-4
A-3

8-4
C-2
C-3
0-1

C-3
0-3
C-2

D-3

8-4

~

-i.~

At

iii'

8-2

IX

-------

O-z
C-4
NfTES:
1-All ~msTfR ARE 1/4 I/!\TT. 5~
2.F,R ASSY. 'l977'l:!Of'l Yl IS 17..2222 IIIZ.

C-4
D-4
D-4
0-4
8-3

C-2
D-2

--

!~.
V",
R4

~

0-2
8 -4

, •vee

RlI

HI)

D-I

C-2

--- I--

1.-2
8-4
8-2
1.-4
C-2
1.-4
0-1
C-2
C-3
C-3
C-4

0-3

8-4

AU

\J)

!5

D-I

-_._-_.

__

r_

8-3

-------_ _-_.
-

LJIK:

4
D-3
D-3
C-I

D-I

K

__

3
C-I
C-3

LAntE

-

8977"201 Yl IS 18.3133 'til
CIRCUlT (SIICET 2. lOttE 6-7.) FOR ASSE'IBlY

'SCIll~T~

~977q7.00

HAS :

CI6 - ~_47 F IS "'T c"mECTED
~IO - 100 01.15 IS NIIT C".E

m"P2B22

VCC2) PIAOI
RI7

IK

~

:.

I

""

,n.-",

~:

!:oi

PIBl9 (CRQ
-,

MMRQ)PIB03,

""

----+I-3.-"I'~-. IL.----,I_ - ~ - - - - - ~ ".., (iiO

r r:::'
!C2

I

C3+C6
CIO-!-CI3

68ftF

V1
I

N
V1

.......

I
I
I
I

..hCI
..,.... 33,.,.
I IOV

L ____ _

DETAILED LOGIC
TIM...

4

TIMING

(Drawing number 89617000, sheet 3)

COUNTER
Function:

The 5-blt binary count down counter is used for the following:
1.

During shift instructions it is used to count the number of
times a word is shifted.

2.

During Multiply/Divide instruction it is used to count the
number of iterations necessary to complete the operation.
In this case it is loaded with the number 10110 2 •

3.

During any memory reference instruction it may be used to
count the number of memory reference cycles needed to
calculate the effective address of the operand.
In this
case it may be loaded with either 00000 2 , 00010 2 , 00100 2 , or
00110 2 •

5-258

89633300 A

TIMING

(Drawing number 89617000, sheet 3, cont'd.)

Inputs
.~

.. -.--.....

.-."...

SIGNAL
MPC
ENI
JKCK
10
11 .
12
13

i

II

I

:riTR

I,

I
I

F23
PG2
ADI
AD2
Outeuts
NO
CNTE2
N41

Jib

m
~Dl

L

~.

ACTIVE. CONNECTOR/I
PIN
;

14
15
16
PH4

.T' '" . . ...

.

~

LOCATION
. SHEET SQUARE

I

+
j

H
H
H

L
H
L
H
L

P1B28
P2A09
P2B07
P2A16
P2A17
P2BOI

.................__ .....-.

89633300 A

FUNCTION

[AS]
Master clear or clear-to-P-register.
[T]
CPU in interrupt state
[S]
Clock from phase generator(sheet 2):
P1B17
P1B18
Least significant bits of
P1A17
instruction register
i
PIBOS
P1B24
!
!
PZA10
i
P2B10
U
P2B09
Set ITR flip-flop
Clock phase generator (sheet 2)
[AV]
[AN]
Instruction register F=2 or F=3
see [V]
[w]
Second stage of phase G
P1A16
P1B20

L
L
H
H
H
H
H
H
H
H
L
H
H

,.--

I,

I

I

I

3

I
I
I

II

I

I

;

I
.... ____. ____ ... 1...

Least significant bit of counter
Counter conten.t = 00010 2
Counter content ~ 00001 2
8DD·16
EVEN-IS
~oN3of2oii otro-ADRoF23
"

--.-.-

..

--~-.--

I

c4
c4
C4
D4
D4
D3
D2
D2
A4
A4
A4
B4

D3
D4
D3

3

B3
Bl
Bl
Bl
Al
B3

5-259

(Drawing number 8,617000, sheet 3, cont'd.)

TIMING

.Descri pt ion
The counter itself is made up of five flip-flops; NO, Nl, N2, N3 and N4 (U13, U14,
U12). The most significant bit is N4 and the 1east significant is NO. All the flipf10ps are clocked by phase 5 of the clock (JKCK) and they are c1eared by either the
clock signal MPC or by signa1 ENI.
MPC is active when the CPU receives a
Master Clear signal or a Clear to the P register.
ENI is active when the
CPU goes into an interrupt state.
The counter is loaded through the set (S) input of each flip-flop, as f0110ws:For Shift instructions the counter is 10aded with the five 1east significant
bits of the instruction register, 14, 13, 12, 11, 10.
The setting of the
f1ip-f10p~ is enabled by the signal JITR'PH4 which is produced at US8/11.
For Mu1tiply/Divide instructions the counter is 10aded with the number 10110 2 ,
The f1ip-f10ps are set by the signal 0P·EVEN·PG2·F23.
The signa1s 0P·EVEN
and PG2 ~efine a specific time period whi1e F23 is active, that is, when the
F field of the instruction register is decoded as F = 2 or F = 3.
For Memory Reference instructions the counter is set by the signals ADl and AD2.
These signals are produced on the Decoder assembly. They determine whether the counter
wi11 be preset to00000 2 , 00010 2 , 00100 2 , or 00110 2 ,
The setting of the f1ip-f10ps
is enab1ed by the signa1 RNI·0DD·FEO·PH4, where RNI, 0DD and PH4 define a specific
time period and FEO is active when the F fie1d of the instruction register is not
equa 1 to zero.
Each flip-f10p changes state on JKCK when its J and K inputs are high.
This
occurs on thef-signal transmission (high-to-low) when the previous flip-flop changes
.~

state.

5-260

Thus the counter counts down.

89633300 A

TIMING

(Drawing number 89617000, sheet 3, cont'd.)

The least significant flip-flop (NO) changes state on every JKCK clock except
when one of the following conditions is true (signal at u45/6):

I.

(Counter

= 0)-RNI12-(ADI

+ AD2) at U44/8.

This function enables the counter to decrement immediately on
loading the memory reference instruction.
Note that the function N41-NO determines that the (Counter = 0)
and that this situation exists most of the time.
Here N41 = Nlj-N3-Nr-NT

2.

ADR-(Counter

= 2)[(FI = 5, 7, 0, F)-32KW-XI5

+ EVEN].

This occurs during multi-level indirect addressing, when the
counter is not decremented until the last level is reached.

3.

J ITR

This occurs when the counter is loaded at the beginning of a
shift instruction.

4.

MDS-EVEN
This occurs during multiply/divide instructions, when the
counter is decremented only on odd cycles.

5.

ITR-8DD-15-16
This occurs during Double Word Shift operations, when the
counter is decremented only on EVEN cycles.

A simplified diagram of the loading and decrementing counter is given on
page 5-264.
89633300 A

5-261

TIMING

(Drawing 89617000, sheet 3, cont'd.)

Three signals derived from the counter are also used on other assemblies of the
CPU.
These are:
------------~-------------------_r----------------------~
Counter content
Connector/pin
Signal

--------If-------------..-.-t---.-----------f
CNTE2

P2A9

N41

P2B7

NO

I'"--..---.. ......
~-

---

...

__ __
....

P1B28
..

__...._....

__.........

00010 2

I

_-_ I
.......

,,,_.,,

... -

....

i

00000 2 or 00001 2

I

odd number

I

--... -.---~

The following signals produced on the Timing assembly are used by the Decoder:

1.

MOl, (at UtO/8), is active during multiply/divide instructions
when the counter is at 00001 2

2.

m

3.

EI5 =

= Ji)'O + 11)

EVEN + 15

J]b and EI5 are used during Shift Instructions.

5-262

89633300 A

00
\.D

'"

W
W
W

o
o

»

,,-mr)
~

V'1
I

N

'"

W

' ! I:

I!!~

r~~ ....

16"

nlIQ

,..ri..p.a

DETAILED LOGIC DIMRAM
TIMING

"CA' r (EI!!

TIMING

JII·I
II

,• I

. 'II"
iU

9

i
•

!
i•
I!

II

•

I•
~

I

II
II

i+

!:

5-264

i-

10;.

II
I~I
ill

89633300 A

(Drawing number 89617000, sheet 4)

TIMING

INTERRUPT TIMING, V REGISTER CONTROL LOGIC
Function:
This circuit includes timing signals which control the transition into the
interrupt state and logic for controlling the V register in the ALU.
Inputs
t---'-- .- ..

-T----- .......

SIGNAL
INO
tN41
IN32
JENI
KENll
R2
R3
R4

! ACT IVE
H
H
H
H

L
H
H

L

32KW
N4l
MPC

H
H

L

L

H

[AC]
[AD]
[AS]
[AK]

LOCATiON '---'
FUNCT ION ___._.__. _. ____ .. SJ:iEET
S UARE
4
03
(Fl=4)+(Fl=C)
04
C4
(Fl=6)+(Fl=E)
Sets ENI
c4
Resets ENI
B4
Bit 9 of IR
c4
Bit 10 of I R
D4
Bit 11 of I R
04
Programmer's Console selects
02
V-register
See sheet 5
See sheet 3
See sheet 5
RN 112 ° (AD l+AD2) o'NO o'Nl o'ti2 oN'3 oN'4

[AP]

NOoNl oN2 oN3 oN4 = NOoN41

P1A20
P2B12
P2A28
P2B18
P1B29

H

ffi

I/JOD
NO
I/JDD02

"-CONNECTOR
.________ !'l_N_
P1A21
P1A25
P2A07
P2A13

I [K], [R]

I

H

See sheet 2
See sheet 3

[A]
[V]

N41 oNO

[AP]
GI/JCS
ADR
EAD
I/JP2
RNI
EVEN
89633300 A

H

[L]

H

[V]

L

[AV]

H

[AQ]

H;

[X]

_.__. _~. L

[~]

-. _

.

!

~

-,.-----.-..... .. -

..-.......... - -.. ..
~

See sheet 5
See sheet 5
See sheet 2
,

4

______J
5-265

TIMING

(Drawing number 89617000, Sheet 4, cont'd.)

Outputs

j_·'----'"T ""
i SIGNAL

ACTIVE

ENI
ENI03

H
H

ENI02
ENI20

H
L
L
L
H
H
L

,

-fENI2E
/JP211

I
I

:::UG

AiW

--..... ..--. ---.~

.

'.'.-'-'--'---'~"'-~~'

CONNECTOR
PIN
P2B15
P2B16
P2A06
P2A2l
P2A20
P2A24
P1A3.o
P2A14
P1A24

.-........

"'."

FUNCTION
Enter interrupt
ENIOINi2"Gf/JCS
EN I °f/JDD2
ENI2of/JDD
ENI20EVEN
, f/JP2 of/JDD

.•...- ..

i

LOCATION
SQUARE;

i SHEET

----+-,-------11

Controls output of Y register
-1 or -0 to Augend gates
Add Y register

4

4

A3
A3
B3
A2
Bl
Dl
Cl
Bl
Dl

Description
The Enter Interrupt Sequence is initiated by the signal JENI from the Console
Interface card.
This signal causes the ENI flip-flop (U7/l5) to be set.
The
flip-flop is clocked by phase 5 of the timing chain, JKCK (see Timing, sheet 2)
and is reset by MPC (see Timing,sheet 5).
The output of the flip-flop is at
u24/2.
At the end of time ENI·f/JDD2 the ENI2 flip-flop (U7/11) is set.
This
flip-flop is also clocked by JKCK and cleared by MPC.
The output of the ENI2
flip-flop is ANDed with EVEN and f/JDD (see Timing, sheet 2) to produce ENI2E and
ENI20 respectively.
ENI20 is used to reset the ENI and ENI2 flip-flops.
This
is the normal end of the enter interrupt sequence and is followed by the setting
of the RNI flip-flop (see Timing, sheet 5).
The Enter Interrupt Sequence may be aborted prematurely by the signal KENll
which resets the ENI flip-flop and prevents the RNI flip-flop from resetting.

5-266

89633300 A

(Drawing number 89617000, sheet 4, cont'd.)

TIM ING

Other signals produced by this logic circuit are:
'ENrn)= EN I-EN'im •Gee S

and

SGL = ENI02·EVEN = ENI2E (at P2A14)
SGL is an ALU control.

Timing diagram for this logic circuit is shown below.
ENI Completed

ENI Aborted

'DO

"002

____~r-l~_________

RNI

_ _ _ _ ....'10.00-._ _ _ _....

----1

____~r_l~__________
----------" - --L!>~ __

~~----

ENI

ENI02

ENI03

NOTE:

~

~~----

RNI mayor may not be active at this time.

ALU Y register control
The signal YTAUG is produced in this section.
This signal allows the output
of the Y register to be enabled through the augend gates to the adder in the
ALU circuit.
The logic equation of this signal is as follows:
YTAUG

= esy + ep20 + ADY

where
ADY
89633300 A

= ADRoGeeSoNl oRl ° (Rt+R3) oNOo INOoKtoN41 ° (IN4+IN32 32KWo X15)
0

5-267

TIMING

(Drawing number 89617000, sheet 4, cont'd.)

The first two terms of ADY are G~CS (see Timing, sheet 2) and ADR (see Timing,
sheet 5).
This restricts the YTAUG to situations where the computer is in the
addressing state, and is running.
The remaining terms of ADY define specific cycles of the addressing state where
the YTAUG signal is not active.
The signals NO, NI, and N4, are produced by
the counter (see Timing, sheet 3). The signals RI, R3 and R4 are equivalent to
bits 08, 10, and II respectively of the instruction register. Signals INO, IN32,
and IN41 are produced on the I/O Interface and are decoded from the Fl field of
the instruction register.
The signal XI5 is the most significant bit of the
X register which is stored in a flip-flop (see Timing, sheet 6); the signal
32KW is connected to the 65K/32K mode switch on the programmer's console. In
addition, the terms CSY and ~P20 produce a YTAUG signal when the Y register is
selected by pushbutton on the Programmer's Console or when the
signal is active.

~P20

timing

The signal WY at the output of u24/12 is the decoded condition for writing in
the Y register.
It is transmitted to the Timing circuit (sheet 6) where it
is ANDed with a clock signal to produce the Y register clock.
The logic
equa t i on of th iss i gna 1 is:
WY

= EAD

+ CSY + RNI·~DD + ~DDo(COUNTER ~ 0) + (COUNTER

= 1)oR2

The signal EAD (End of Address or End of effective Address) is generated in the
Timing circuit (sheet 5).
It is active on the last CPU cycle of the addressing
sequence for the memory reference instruction.
CSY is active when the computer
is stopped and the Y register is selected on the programmer's console.
The signal

RNI.~DD

is active during the first CPU cycle of each instruction.

The signal RI is active when the counter is at I and bit 9 of the instruction·
register is such that

~-268

Fl

= 2,

3, 4, 7, A, B, E, or F.

89633300

A

...
00
\.0

'"

w
w
w

R4)rf P.

»

R3) P2A28 ,

27

ffi)PIB29

o
o

IN41

PI

1.150
T~r-

-1.J2!..I

PIA24(AOY
8
P2B24

3 AD

[N32

8

P2A07

PIA30

5 AC

10

'P2f
YTAUG

- a

~"'2Hr
13 U38

3.5~III~Hl8
R2) P2BI2

JENI) P2AI3
KENII) PIA20

1-11101.

P2AZO

6

....,
6

,

I

V1
I
N

'"

\.0

~ ~1

lNI!

ENI

P2AI4

ENI2E

-'SGL

N
c
N

a..
,A..

ENIH

DIAGRAM

-

~I

__-L~__~~~~

•

TIMING (Drawing number 89617000, sheet 5)
MAIN SEQUENCE FLIP-FLOPS
Funct ion:
This section contains four of the main sequence flip-flops;

r:~I_u--- 1-!li~_~~:~~ou tP;t!!~l
I
!

i

ADR
'P2
'P

u8/l5
U41/l5
u4l/11

I

:

~-------",,--,-,,--,~,-,,---,

One of these flip-flops is usually set except during multiply/divide, shift
instructions or the enter interrupt sequence (refer to Timing, sheet 4). No
more than one of these flip-flops may be set during anyone cycle •

.. to-NNECTtfR} ........ -.
PIN
P2A24
P2B25
P1A26

··-·~----~·-···-·--···-·······-·-·····-····-----.-I-i.ocATION

FUNCT ION

i

SQUARE!
IISHEET
.. __ .. _.......
_-----+

input to RNI flip-flop
5
K input to RNI flip-flop
Master clear, clear P register!,
J

[R] , [K]

04
04

C4i

[N]

P2B08
P2B20
P2A27
[AB]
[AW]
P2B13

I.

!

Main/Expansion memory selector:

c4
A4
A4

See sheet 4
See sheet 6
Short Address =
[(Fl=0)+(Fl=2,8)·(8~0)]

03

P2B04
P2A05
[AN]
[AG]

89633300 A

TIMING

(Drawing number 89617000, sheet 5, cont'd.)

MAIN SEQUENCE FLIP-FLOPS
Outputs

r

... I
ACT IVE

SIGNAL

,'!

RNI
RN I 11

RNi12
RNm

-i
I

I

RE 1F

R'ETS"
EAO
IJp
fJPINO

iPl
"'---.~- ~ ....,

-.'

,

-- ...:.~

-

"

lCON~~~TOR T

..

H
L
L
L
L
L
H
L
L
H
H
H
H

I

P2A29
P2B27
P2B28
P2B26
P2A25
PI A31
P2AT9
P2A26
P2B14
P1A27
P1B23
P2B06
P2A04

.......

~

,~~

. - -_"'",

~"~""

~

~

Read Next Instruction

5

I

RNI·f/lOO·{F=O)
RN I ·f/lOO· (F~O)
RN I • EVEN· (F=O)
RN I ·EVEN· (F=O)
Hulticycle addressing
RNI.EVEN.(Shift)
RNI.EVEN. (F=O). (Fl=8)
tEffective Address,
End of Address
Operand 1
Operand Indicator

I

I

I,•
!I

,

!
i
I

I•,
.\

I

!

I

I
I

I

iJp·iJoo
f/lP'EVEN
•

•

o·

• "_ • • ,

__

_._

,,'

!
I

--..M._.~_"',"

LOCATION !
SHEET SQUARE
..... -"- .............. _' .....
...-._--.......,

5

_
p

89633300 A

"'~_._._~_,,_

I

FUNCTION

JI

R'N'"m
A'f>R'

fJPE

. -

.....

-

03
C2
B2
B2
B2
Cl
B2
A2
Cl
Cl
Bl
Bl
Bl

'--"""--~ ".--.-'~

5-271

TIMING

(drawing 89617000,

sheet 5, cont'd.)

Descrietion
The RNI state exists in every instruction.
Each instruction begins with
an RNI·8DD cycle and ends with an RNI·EVEN cycle (refer to Timing, sheet 2
for an explanation of the signals 8DD and EVEN).

The ADR flip-flop is active in memory reference instructions while the
effective address is being calculated.
In some cases the entire effective
address can be calculated during the RNI·8DD cycle so the ADR state is not
needed.
This is referred to as SHort ADDRessing (SHADR).

The 8P flip-flop is usually active in memory reference instructions after
addressing.
It is also used in some register reference instructions.
The ep2 flip-flop is active before the 8P flip-flop during three instructions:
RAO, SPE and CPS.

5-272

89633300 A

TIM I NG

(drawing 89617000, sheet 5, cont'd.)

Circuit Description
The RNI, AOR, SP2and SP flip-flops are all type J-K and are all clocked by
JKCK (refer to Timing, sheet 2).
AOR, SP2 and SP are reset by (MPC + EN1)
where:
MPC is active during master clear and P register clear.
ENI is active during the enter interrupt sequence.
Thus when the computer enters an interrupt, the main sequence flip-flops are
immediately cleared, except for RNI which is usually cleared later in the sequence.
RNI is set by MPC and therefore the RNI state already exists after master clear
or P register clear, when the computer is set in operation.
The inputs of the RNI flip-flop, JRNI and KRNI are produced on the I/O Interface
and the Console Interface assemblies.
The J input of the SP2 flip-flop, JSP2, is produced on the I/O Interface assembly.
The K input is connected to the signal SOD.
The J input of the ;P flip-flop,
JJ~ is also produced in the I/O Interface.
Thus the RNI, AOR and SP2 states always finish at the end of an odd cycle while
the JP state can also terminate after an even cycle during multiply/divide
instructions.
The J input of the ADR flip-flop is the signal:
RNI-'OO-{F

~

O)-SHADR

The K input is the signal:
KADR.= JDD-(Counter = 0) -[(Fl = 4,6,C,E)-32KW-XJ51
Thus the ADR state is entered after an RNI-'DD cycle for memory reference
instructions, as long as short addressing is not called for. The counter
(Timing, sheet 4) is loaded during the RNI-'DO cycle and decrements on
following cycles.
89633300 A

5-273

TIMING

(drawing

89617000~

sheet 5, cont'd,)

When the counter reaches zero and eoo is active, the AOR state will be
terminated unless the computer is performing indirect addressing,
or an interrupt sequence is entered during indirect addressing.

The signal ijU) is active during the last cycle of addressing. It is
used on Timing, sheet 4 and is also transmitted to the I/O Interface card
Its equation is:
EAO = AOR·KAOR + SHAORoRNI·eOO.(F

~

0)

The signal ePINO goes to the OPerand INDicator on the programmer1s
console. It is active during the following:
-

operand and ep2
memory reference cycles of multiply/divide instructions (M021)
enter interrupt sequence (no main sequence flip-flop active).

The remaining signals in this section are produced by combining the
main sequence signals with EVEN and eoo and with signals decoded from
the output of the instruction register.

5-274

89633300 A

co

SHAOR

\D

0'

w
w
w
0

0

J

2.M ..@---,

...

ii
~

»

I I I

32n)

(V)3

2

PIA27 (.P

6

PlB23

rrcgvp

4

RNII2

RNi22

~

4 AF

(.PINO

10 213H
U30

P2B06

RNffi

.PI

26

•

FIEF) P2B20

JNR) P2A27

P2A19 'REIF

I'D , ..".."''' (REii

VI
I

N

.......

VI

.......
VI
I
N

.......

0'

DETAILED LOGIC DIAGRAM
TIMING

P2A04 (iPE

TIMING (Drawing number 89617000, sheet 6)
AUXILIARY SEQUENCE FLIP-FLOPS
Function:
This section includes the flip-flops MOS, MOS1, ITR, XIS and FEO and generates
the corresponding signals.
Inputs
SIGNAL

".~'.. CONNECTOR
ACTIVE
PIN
...... _ ... _ _ _ _ . . . . . . . _ _..... _

WXM
WXL
WA

!

WM

H
H
H
H

WQ

H

WP

H

i

F23
CHI

H

1

H

-.3

H

'00

H

t

I

I

\

i

I

89633300 A

LOCATION
jSHEET SQUARE

. FUNCTION
••.•

,,,n,
'

P1B15
P1Bl0
P1A14
P2B23
P1B12
PlAn
P2B02
P2B31
P2A30
[K] , [R]

EVEN
H
~ [N]
i
i
H
XSEL7M
PlA02
!
H
[L]
G'CS
PG3(JKCK)
H
[E]
CLRIR
H
PlA23
H
OFEO
PIBOI
[p]
H
CNTE2
H
KITR
P2A23
H
JITR
[AL]
H
MOl
_ _--..l'--______ .[G]
__

I

I

!

....

-,"
i

-

.-- ... ..

6

I
Register clock selection

F -= 2,3
F"3
See sheet 2
See sheet 2

-_..

B4
B4
A4
A4
B3
B3
e4
A4
B4

e4
B3
B3
B3

Phase 5 of clock
Clear Index Register
(Counter = 2)

02
I

(eounter=l)-(multiply)-AOR:

6
...........

5-277

TIMING

(Drawing number 89617000, sheet 6, cont'd.)

Outputs

r----·-···-· _. -...-.. .. -.' .-.....

ACT IVE .'j". CON~~~TOR

S IG~JAL
MDS
MDSO
MDSE
MDSI
MDS2
MD21
W9A
XI5
BaCK
ITR
FEO
QCK

H
H
H
H
H
L
L
H

YCK
PCK
MCK
ALCK
AMCK
XLCK
XMCK
IRCK

H

-

,

1--

5-278

I,

H.
H

P1B14

H
H
H

H

H

P2Al1

H

PIAIO
PIB09
PlA09

H

H

FUNCTION

i)
!I

P2B30

j

PlA08
P2B03
P2A02
PIA2a
PIB31
P2AOI
PIB26
PIB30
P2B29
P2BI7
PIA II
PIAI2
PIBI3
P2A22

H

I .

j

. . . -.. . ,"'-"- """-r-

I

I
f
!

LOCATION
SHEET SQUARE
6

Cl
Cl
Cl
D3
D3

Timing during
>
multiply/divide
•
I
instructions

c4

I

A3
B3
D3
DI
Bl
BI
Al
A1
Al
Al

I,

Al

!
I.

Bucket clock
Timing for shift
F

I1
I~

=0

Register clocks

6

..

B3
B3
B3

.. -----'._----------------

- _..

89633300 A

TIMING

(drawing

89617000~

sheet 6, contI d.)

Description
Signals MDS and MOSI are active during multiply/divide instructions.
During the (tP.EVEN cycle of multiply/divide:,the counter (Timing, sheet 4)
is loaded with 10110 2 (22 10 ). On the next cycle, the 0P stat~ is not active,
the counter decrements to 21 10 and the signal M021 defines the timing.
M021 is the J-input of the MOSI flip-flop. MOSI is active for the
following two cycles and its K input is connected to the function
MOSI ·000. The MOS fl ip-flop becomes active immediately after MOSI
and remains active for 34 cycles. The K input is connected to the
function CNTE2·000 where CNTE2 means "counter equals 2 10 ".
The M021 signal is also combined with the fourth clock phase, signal PH4,
to produce BBCK which is a clock to the bit bucket on the decoder card.
The bit bucket is used to restore the sign of the result in multiply/
divide instructions.
The ITR flip-flop (U22) is active during shift instructions.
Its J and K
inputs are produced on the I/O Interface board. The fl ip-flops MOS),
MOS and ITR are all cJocked by the fifth phase clock signal JKCK and
reset by MPC.
The Xl5 fl ip-flop (U64) always holds the most significant bit of the
X register except during multiply/divide.
Its 0 input is XSEl7M which
Is the input to the X register taken from the AlU assembly. Its clock is
PG3·WXM·MOSI
The FEO flip-flop (U64) stores the signal OFEO which is active when the
F field of a word read from the memory is equal to zero. The predecoding
for OFEO is on the Memory Control assembly. The clock to this flip-flop is:
IRCK

89633300

A

= R~H·EVEN·PG3

5-279

TIMING

(drawing 89617000, sheet 6, cont'd.)

IRCK is also used to clock the instruction register. The fl ip-flop
is set by the signal CLRIR which clears the instruction register.
Thus this flip-flop indicates whether the F field of the instruction
register is zero.
Register Clocks
Clock signals for the registers in the ALU are produced in this section.
The clock signals of the various registers are produced by multiplying JKCK
~hase 5

of the clock) (Timing, sheet 2) with the appropriate signals (W):

Register

Q

p

y

M

A

Signals for
clock generation

WQ

WP

WY

WM

WA WXM

X

The signal AMCK which clocks the most significant 8 bits of the
A register can be blocked by the CHI signal. This is used by peripheral
devices which transfer only 8 bits of data on each input on the A/Q channel.
The signal W9A is transmitted to the decoder card ALU/shifter.
equation is:
W9A

5-280

= RNI·EVEN + M021 + MOl +.MDSI +

Its

G~CS

89633300 A

...

....

00
\0
0"

np"'{8ICK

\AI
\AI
\AI

KIT ..
24

PIA28(MDS2

o
o

»
TIl

I U501
PallO

PIISI

"_

PIIOS

3~.

2.s.4.'~

~S



,f'IIWZ_

T

II

DEFEO)~

vee
T
R21
470

os) P2AIO

WX_

.......,

,.

CHI

...P2B51

RI9
180

I ,

1:'

~

NI17

"m

PIA"

(OCK

_ PIII5

WXL) PIIIO

,,(i)

I
41"01_

II-U

_1'71 _

I~

1~~

,.-.

n~

1~;..,

1,.--.

~II

~~47.

.,. ""'_
:PCt
'_CK

V1
I

N

00

.!'1..~"iiA

DETAILED LOGIC DIAGRAM
TIMING

IIPages 5-282 to 5-290 are unassigned. 1I

5-282/5-290

89633300 A

INPUT/OUTPUT (I/O) INTERFACE
The I/O Interface circuits are accommodated on a single 50-PAK printed
wiring board. The logic circuit diagram of the unit is given in drawing
number 89619700, sheets 1-10.
The I/O Interface circuits generate control signals for the main inputo.utput (A/Q) channel and for the circuits commanding the peripheral controllers.
It also generates control signals for the CPU. This page lists the
functional ~locks accommodated on this board. The circuits and signals
are descr i bed in deta i1 on pages fac i ng the cor respond i n9 shee ts of the
circuit diagram.
MAIN FUNCTIONAL BLOCKS
Shown on Sheet

Des i gnat ion

-....--._--------.---.------.--......---.------------11-----_........ -.----. .---'!
A/Q channel control
Memory request logic
Index (I) address and write enable contFols

2

Decoder for Fl field
Augend controls and X register clock control

5
6

Controls for shifter and A/Q channel direction

7

Main sequence flip-flop controls

8

Overflow logic
Enable-Interrupt logic

9

3
4

10

.1 ....._

89633300 A

5-291

V1
I

I 2 I 4 5 I 7 I , I~ II REY ECO
04 04 04
04 CXlI23
If.
A A
~** ,.11 eK I...'~ A."....
It "

N

\,.0

N

{IFF

JFF SHEIT
REFERENCE LETTER
A
I
D
I
F
J

X
L

SHEET

2
C- 4
D-I
C-I
C-I

I

4
D -I

N
0
R
I
T
U

C-4
A-2

X

y

Z
AA
AI
AD
AE

..,

7

I

C-I
C-I

8 -I

8-4
D-4

A-4

D-2

c-z

"

c-z

C-2

CI(

1..11.

7400.

if.ar ~,., I~

a7*~

__ "'.

.,1../.

'111/ IU-

.....,..

ItELMWlI cutU If.

1414

1.:14'

,IIJ. ~Jn

~'"

SSWI--J

A -I
C-S

lOY

C-I
D-4

A-2

.-1

1..

1I'li

C-4

D-Z
C-I



YJJJ

A-I
C-2
N;TEI:

A:"I
(:-4
1-4

C-I

~

RI
IX

_IIYI

C -I

D-I

_

A-4

D-I

D-4

I-

CI';'C.
II"

1-4
I-I
D-2
C-4

A-I
D-I

I·yee

CI

C-4

C-4

Q ALL REII8T;n ARE 0.111 WATT II ..
II THIS SHEET IS ~TINUED

C-4
C....
C-I

C-4

tIN

II

SHEET II.

C-4
C-4
C-I
C-2
C-4
A-4
C-4

,

*
* DRAWING
~~ ;~ • DO NOT SCALE

0 0

~~
~Ol
co

.

,.." '''4

5V'·I

C-I

UNLEII OMRWIIE SPt:CIFED
DI.....Ort AItE .. INCICI
TOLEfWlct:1

o
o

CI ..1111
nA2.

PIA..
IKClCr=

~._.JO
vee

I.'
118

IK

..uu '" ..

III

yee

YOlO
r--

I~-

" .. )

PIIIO

It

I (ij}--!Si

....

T

~
1 1

R3
180

t

"2
110
.. 2102

~""""""==--_""__..l..LlI

..
•10

1.1..@

4.5,'

• :1

,

•

QCI)f!!

MII( fIEf

>PZ_

1'10

iiiiii )"104

12

IiiiIif

• @U.•
£H.'.'.IO

~

V1
I
\1.1

o

DETAILED LOGIC DIAGRAM
I/O INTERFACE

INPUT/OUTPUT {I/O} INTERFACE (drawing number 89619700, sheet 4)
INDEX (i) ADDRESS AND WRITE ENABLE CONTROLS
Funct ion
This circuit generates control signals for an index (i) address operation
and Write Enable involving:
a.

the second index register (location 00FF 16 )

b.

the memory write cycle {signals WE, SPBM, CPBM, 'PST}

(I/O) INTERFACE

(drawing number 89619700, sheet 4, cont'd.)

Descript ion
The signal CRI is defined by:

CRT = ADR·CNTE2· (Fl

=

5,7,D,F) ·X15·32KW

+ [ADR·CNTE2·DEL + RNI·eDD·(F~O}·DEL].[Fl

= 1,3,9,B]

Itis used on the Memory Address board to force the current memory reference
to be made to the second index register (memory location 00FF 16 ) rather than
the address specified by the ALU lines (indirect addressing).
The output of the index flip-flop (RIND) controls the INDEX indicator on the
Programmer1s Console. It is active during the second pass of a CPU memory
cycle in which the index location is addressed.
The signal INDIND = ADR.RTND controls the INDIRECT ADDRESS indicator on the
programmer1s console. It is also used on the Console Interface board to
determine the timing in which an interrupt is accepted (see JENI, console
interface) •
The signal WE is active when a CPU memory write cycle must be performed.
It acts on circuits on the memory control board. Its equation is:

WE =

ENTER + EtU 2· EVEN

+ 'P·(F - 4,5,6,7,D}

+ ,p·G'CS·'OO-FEO·OEL-(Fl = 6,7)

89633300 A

5-303

(I/O)

INTERFACE

(drawing number 89619700, sheet 4, cont'd.)

The signals S"PiM and C'P'BH .indicate that the computer is executing a "set
protect bit" or "clear protect bit" instruction respectively. These signals
are used on the memory address card to determine the polarity of the protect
bit written back in the specified location. Their equations are as follows:
SPBM

= ,p.G'CS·iDD·FEO.OEL.(Fl

CPiM =

,p·G'CS·'OD·FEO·DEL·(Fl

= 6)

= 7)

The signal 'PST is used by the breakpoint stop logic on the Programmer's
Console to allow the computer to be stopped when executing a memory write
cycle to a specified location. .Its equation is:
'PST

5-304

= ENTER

+ ENi2E + 'P.(F = 4,5,6,7,0)

89633300

A

&.

~

00
\.0

0'\

W
W
W

o
o

I

»
'~I""L--_ _ __

CiTii

r"'~"H

('RrND

r.~u.

(I1I;IND

PIAl2 (

>....

I!IfI

17

.pc) Paa

T4~

fD)

•
_-I

~(!'!.

EIITER) PI.

iiiii) PI.

1lI1 ••:" ....12

•
•

PIA .. (1Kr

I~

TI) PIAI4

'ill

I 'I
•

I

PillS

I '1

V1
I

W

o

V1

""

V1
I
W

o

0'\

DETAILED LOGIC DIAGRAM
I/O INTERFACE

.

(Wi

INPUT/OUTPUT (I/O) INTERFACE

(drawing number 89619700, sheet 5)

DECODER FOR Fl FIELD
Function
This circuit decodes the FI field of the instrLlctionregister on the Decoder
assembly (RI, R2, R3, R4), and generates control signals using these
decoded signals.

Ineuts
-~.

~.

'

.....-

.~-.-"

._.-

Signal

h

__

r . ....... ---Locat ion
Connector/
Sheet Square
Active
Pin
Funct ion
.... _... _. __ . --.---. -.- .. -- _._------------- .. -.- .
........ __ .. _.. _-.---- PlB22
04
H
5
H
PIBl9
04
FI field
H
P1A23
04
PIA24
04
H
B4
5
Enter Interrupt indicato
PIAIO
L
•• "

, ••• _

•• _

......

0"

.~

• • •_ _ _ ••

4~_

~

R4
R3
R2
RI

Eiii1i
Outeuts
IE
INR
INO
IN32
IN41
SLS
SHADR

W

89633300 A

H

PIA22
PIB23
PIB27
PIB29
PIA30
P1B24
P2AI6

L

PIA21

H
H
H
H
H
H

--.~

Selective Stop
Short Address
Q. channel control
(see sheet 7)

'"

"'

-'-.---.~-

5

01
01
CI
CI
BI
BI
Al

5

CI

..

5-307

(110) INTERFACE

(drawing n!,lmber 89619700, sheet 5, cont'd.)

Description
The decoder's (USR) 16 active-low outputs correspond ~o the instruction
register FI field codes (RI, R2, R3, R4). The following signals are
generated with their aid and are transmitted to other boards:
The signal SHADR is active during memory reference instructions in which one
CPU cycle (RNI-O) is enough to calculate the effective address (and therefore
the ADR timing is not needed). It Is used on this assembly as well as the
Timing assembly to produce the control signals for the RNi and ADR flip-flops.
Its equation is:
SHADR

=

(Fl

= 0)

+ DEl-(Fl

= 2,8)

The signal SLS is sent to the programmer's console and stops the computer
if the SELECTIVE STOP switch is set. Its equation is:
SLS

= RNI-EVEN-(F = 0)-(F1 = 0)- ENTq

The signal E'Ni7f is produced on the Console Interface and is used to prevent
the first cycle after an enter-interrupt from being interpreted as a
selective stop. It Is used here to generate SLS.
Other signals are:
IE - (Fl - E)
INR - FEO-(FI - 8)"
INO = (FI - 2,6,E)
IN32 = (FI = 6,E)
IN41 = (FI = 4,C)

5-308

89633300 A

..

..,
II

00
\D

Cl'
\N
\N
\N

24

1,1

0
0

[
PIAZZ

»0
114
113
III
III
I

......

Pl812

20.
21 4
222

PlAZS
4

•

•

21

IE

PI825

INR

use

I

PI827

!NO

4
4

A

U

•

PIAZI

iQc

41

•
PII29

20

INSZ

PIASO

IN41

14

I

iiiiM

PI124

12

7.10

SLS

PIAl

2
'1
PIAII SHADR

V1

DIMRAM

I

\N

o

\D

4

,1

,,

INPUT/OUTPUT (I/O) INTERFACE

(drawing number 89619700, sheet 6)

(

AUGEND CONTROLS AND X REGISTER CLOCK CONTROL
Function
This circuit generates:
a.

augend controls not Included on the Decoder assembly (DELTAUG, SE, 1M, SFL)

b.

X register clock controls (WXL, WXM)

Inputs
Signal
WRQ.
FlEl
SKT

CSx

Connector/
Pin

Active
H
H
H

mr

L
L

HDS2

H

,
.i

P2A10
P1A27
P2A30
PlA31
P1B28
PlBl3

Function

Locat ion
Sheet Square

6

04
c4
C4
B3
B3
02

6

C3
C3
01
Cl
C1
Bl
Bl
Al

6
Fl • 1
Skip conditfon

Outputs

XEZ
DELTAUG

H

C'LiiQ
WXM
WXL
SE
SIH
SFL

L

L
H
H
H
H
H

PlA05
P2B30

(X • 0)

Pl807
P2A07
P2A15
P2A04
P2A09
P2B05

Clear Q. register

}x Register clock controls
.-~--

5-310

89633300 A

(I/O) INTERFACE

(drawing number 89619700, sheet 6, cont'd.)

Description
The augend gate controls are described together with the augend gates
(ALU circuit, sheets 4,5). Their equations are as follows:
DELTAUG

= RNI·0DD·0DD2·(F = O).(FI = 1)·SKT

This function is active during skip instructions when the skip condition
(SKT) is met.
SE

= ENI2-EVEN

+ RNI -0DD-(F

= 0)·FIE23

+ RNI·0DD.(F # 0)·0E[.R4

1M = 17 + ENI2·EVEN

SF[ = ENI2·EVEN·FEQ·OEL
The X register clock control signals are used on the Timing assembly to produce
clocks for the two ALU boards (WXl is associated with the ALU LSB, WXM with
the ALU MSB). Their equations are as follows:
WXL

= CSX

+ WXLJ + EAO + ENI3

WXM

= WXl

+ RNI·000-(F

= O)·[(FI = E)

+ R4·17]

where
WXlI comes from decoder (sheet 7)
EAO is produced on the timing card (see Timing, sheet 4)
and is active during the last cycle of the address calculation.
The signal XEZ is transmitted to the ALU circuit and controls the X register
selector. When this signal is high, the X register receives memory data from
the Memory Control board; when it is low, the X register receives data from
the shifter. The equation is as follows:
XEZ

89633300 A

= WRQ

+ RNI·0DO-(F

= O)-(Fl = 0,1,4,5,8,9,A,C,O)

5-311

(I/O)

INTERFACE (drawing number 89619700, sheet 6, cont'd.)

The following signals are decoded from the FI field of the instruction
register:
F1El _=(FI = 1), used in Console Interface circuit
FIEF = RloR2oR3 oR4, used in timing circuit
The signal C1:R'il is transmitted to the ALU assemblies to clear the Q. register.
Its equation is:
CLRQ. = MC + MDS2 oMDSoEVEN o03
It is active during Master Clear and when the computer is running; it
clears the Q. register at the beginning of the mUltiply instruction
execution.

5-312

89633300 A

..

:~,

•

.;J

£

QC)

\D

0'

\III
\III
\III

0
0

,.

rJ

40

WWO)'·AIO

.{i}OJ

'r;H

7.~'

10lIl"·

......,

7....
1.I.4.7V

nvv. (

~

V1
I
W

......

DETAILED LOGIC DIAGRAM
I/O INTERFACE
4

C2

INPUT/OUTPUT (I/O) INTERFACE

(drawinQ number 89619700, sheet 8)

MAIN SEQUENCE FLIP-FLOP CONTROLS
Function
This circuit Qenerates control signals for the main sequence flip-flops
of the Timing circuit.

__

_I.....neuts._. --Signal
--.~

02

or
EAD
MiIT
SHI

Active

.--.----.L
L
l

L
H

--,-_..
Connector/
Pin
-.;...._ ...

_--_._

....... -

----.----------~--,---,-

Funct ion

_.

__ _------_ _- _---.

........

Location
Sheet Square

....

PIB03
P2Bl6
PIA26
P2A 11
PIB06

8

P2A18
P2B13
P2B12
P2B14
P2AI3
P2BI0
PIB08
P2B08,

8

8

04
c4
B4
02
C3

Outputs
JOP2
KITR
JOP
KRNII

JiTR

'JRNT
EXT
F23

5-318

H
H
H

H
L
L
H
K

Main Sequence fl ip-flop
control

(F=2)+(F=3)

8

B2
01
01
C1
C1
B1
B1
03

89633300 A

(I/O) INTERFACE
Description

(drawing number 89619700, sheet 8, cont'd.)

The control si~nals for the main sequence flip-flops determine the state of
the computer. They are described with the Timing circuits (sheets 5,6).
Other main sequence flip-flop controls are generated on the Timing and the
Console Interface assemblies. The equations of the signals generated on this
board follow:
JRNI = f/Jpof/JDD + EADo (F = 1) + ENI2 of/JDD
Jf/JP

= RNlof/JDDo(F = O)o[{Fl = 2,3) + f/JDD2o(Fl = E)]
+

EADo(F~I)o(F~O)

+ f/JP2 of/JDD

+ KITR + HDl

Jf/JP2 = RNI·f/JDDo(F = O)·(Ft = 6,7) + EADo(F = D)

JTTR = RNlof/JDDo(F

= O).(FI = F)osAi

KITR = ITRoEVENo[CNTE2·(16 o IS) + N41]
The signal KRNll is transmitted to the Console Interface to produce the
final RNI flip-flop signal, KRNI (refer to Console Interface sheet 5). Its
equation is as follows:
KRNII = RNlof/JDOo{F = O)·[(FI = 2,3,6,7) + f/JDD2o(Fl=E)] + JITR +
+ RNlof/JOOo(F ~ 0) oSHAOR·(F=l)

+ ENI3

The signal EXT is high when the f/JDD state is to be extended for double cycle
operation (f/JOOof/JD02, refer to Timing sheet 2). It is also employed during
instructions which use an immediate operand for a memory reference. In
this case the f/JOO state is extended while the f/JP state goes high, thus
avoiding the f/JpoEVEN state when this is not needed as the CPU does not have
to wait for the operand from memory.

89633300

A

5-319

(I/O) INTERFACE (drawing number 89619700, sheet 8, cont'd.)
The equation of EXT Is:
EXT -ENI3 + RNI-'OO-(F - O)-(FI - I, E)
+ RNI-'OO-(F ~ O)-(FI - A)-DE[

The signal F23 is transmitted to the timing board.

Its equation is:

F23 • (F - 2) + (F - 3)

5-320

89633300 A

....

""

&.

00
\.0
~

\N
\AI

\N

o
o

41

P21""

(F25

,1\ 4

II

P2!!1~ (KITR

42

~

Oi)"'~

,I'~

3
P2114 'KRNI 1
:l5\4110-~

F

or} PlIII

PIAI5

PUle, _ 2

I"

(.iiTii

palo (JRNI

6

no)

PlA2I

11"1 ,

T .I 0

(dIz)-6---!!.t

: -~54

PlIOI ,

6

6~

\J"I
I
\AI

N

DETAILED LOGIC DIAGRAM
I/O INTERFACE

EIIT

INPUT/OUTPUT (I/O) INTERFACE

(drawin~

number 89619700, sheet 9)

OVERFLOW LOGIC
Funct ion
This circuit generates the overflow signal (SVFL), for arithmetic
operations in the computer.

Inputs
Signal

Active

!
KSVF
BB
A7M

03
32KW
SO
A007M
AUG7M
ALU7AM
M
PTAOO

--...
H
H

,

II
I

H

L

I

H
H
H
H
H
H
H

I

P2Bl9
P2A27
P2A20
P2B07
P2A02
P2B26
P2B28
P2A28
P2A29
P2B03
P2B24

I, SheetLocatSquare
ion
!

Connector/
Pin

Function
'-""-'

...- ' ...... _., ....... _"..,...

Overflow flip-flop, K Input

.

i

9

Addition/Subtraction control

9

c4
B4
B4
B4
A4
B3
B3
B3
A3
C2
03

~

I

Outputs

5-322

BX15

H

IJVFL

H

P2827
P2A12

9

C3
01

89633300 A

(I/O) INTERFACE

(drawing number 89619700, sheet 9, cont'd.)

Description
The state of the overflow flip-flop (U39/15) determines the overflow signal.
Its output (eVFL: U41/2) is transmitted to the Programmer1s Console
(OVERFLOW indicator) and to the Console Interface.
The J input to the flip-flop is connected to the signal JeVFL (U38/8):
J~VFL = MMRQ •• DD·ADR.(F

= 2).(F = 3)·PTADD·M

• (AUG7M 
PlAIZ (JlYFL

a

KltVF) .. ,.,.

I I _-I

.."
4~

III) P2A2T~

•

P2827(

ax 15
II

"711 )

> P2II05

fI

I

II

• ~~--

67.8(iX)

141 15
II

32KW

V'I
I

>P2A02

5. 10 "'"
..D)I'IAOI
.ND) "Z121

00
\.0

0"\
W
W

W

o
o

c

Nm: ALL 1lE1I~1II AIlE O.'WATT,'.

DETAILED U»IC DlMRAM
CON~

INTE....ACE

IIt4
III

CONSOLE INTERFACE

(drawing 89618800, sheet 2)

START/STOP SEQUENCE FLI P-FLOPS
Function
This circuit works in conjunction with the Timing board. It produces the
signals for starting and stopping timing sequences under control of signals
from the Programmer's Console and from other computer control circuits •.
Inputs

r····· .- ...

.

--l·------T.-.. ---- .-

.

r

Ac t i ve

I
i

i

Connector/
Pin
I

RNI

H

!

INT·SW
STf/JPCS
PRGS'"

L
H

Mm

L

Gf/JCS

H

Nt,1RMAL
PCL

H

f/JOO.

L

JKCK·

H

P1A17
I Read Next Instruction
I
P18l6!i
P1A16
.P1AlO
P2827
P2A05
: Normal/Power fail
P2All
indicator
P2A22
Odd cycle
PlBl3
'Last phase of clock
P2Bta

CRQ

L

i MPRY

H

PtB25
P2Al2

! Gf/JCSW

L

P2A04

i

Signa 1
I

I

L

L

I

•

Function

-... t··· .-..-.. -. _.- . . . . . . .
I

.

.._._,
Locat ion
i
Sheet
Square I

.--'- .. -....... -" '-."

,... "--"1

2

04
04

I

04
04
c4

2

c4
C4
C4
B4
B4
A4
A4
A4

I

Pa r i ty signa 1

I
I
i

II
I

l._. ___ ._.. __.

89633300 A

5-339

CONSOLE INTERFACE
Outputs

(Drawing 89618800, sheet 2, cont'd.)

------ .....,- ...... - -..[ - C~~-;;-~t~~/- --.--

---------T

1

Location

~~gna_~__ __~t-'--~_ I---!-'--n------ ___ __ F~~_~i on___ . . , ___ .s~~.:_ ~

RI~T

3~ale

PIIII~

18.0 ,II
f'
..
P2828

, T.P.

~~
JKCK

CRQ

~
)

PIB25

,

P2A12

13rIll2

lurT.:l'D

.10

vee~

V1
I

W

~I

MPRY

.

56.0

PRY

G~SW

-'='"
W

"

V1
I

W

-'='"
-'='"

WRQ

DETAILED LOGIC DIAGRAM
CONtiDLE INTEftFACE

CONSOLE INTERFACE

(drawing number 89618800, sheet 3)

PROGRAM PROTECT LOGIC
Function
This circuit includes most of the logic used by the program protect system
of the computer. It detects two of the four types of program protect
violations:
a.

An attempt to execute a protected instruction after a non-protected
one.
An attempt to execute an unprotected instruction which can affect the

b.

protect system.
The other two types of violation are detected in the Memory Control.
They
are transmitted to the Console Interface by means of a single signal (CVIOl).
In~uts
_

'~"'~_'

__

~"_"

... M",

...... -.. - ..

Signal

-

'"

"~"".'

Active

~--.

'-"-'~"

Connector/
Pin
_ . _....

--.-~--.-

~_

•• _

.......

PRTSW

H

MXl7
IRCK

H
H

TEO

L

flJ002

L

INR
10
IF

H

R3
R4

H

P2A29
P2B23
P2B19
P2B06

H

PIA30

89633300 A

H
H

P2Al4
P2A19
PlA20
P2AIO
P2Bll

_.

40"

•

I

.,-~

Function

I Protect

swi tch

----I

. . - ........... -. . .
Locat ion
Sheet
Square
~-¥

3

I
~

I

II
I

I,
!

.... ......

..... _.-- --.

L_

3
.. ....
'

----

04
c4
c4
c4
B4
B4
B4
B4
B4
B4

5-345

(Drawing number 89618800, sheet 3, cont'd.)

CONSOLE INTERFACE
I nput.s (cont I d.)

/--·--1-·.· . - ·

---.-····I.----···.

E~~-n-ec to-r

._~.~g_~~.~.. __~.~~t.j_~~__

Pin

RGPWR
SWEEP
ENTER
PEL
CVIOI

I,'

H

L
L
L
L

PH3

H

PHI

H

1 '
i

Function

I

'-'" "-'.- L~~; t i~1
Sheet
Square I

. -. t-·_· ........ -..' . ::

PIB22
PIBl7
PIBIR
PIB06
P2B04

P2BOS
PIAI4

3

Clock phases

3
•.

~

--.+ "- ...

,~."-~

.... ,, . . . . . . . __ , ••• ~.,. __

" ...• c .

___

~

;

!

B4
A4
A4
C3
B3
A3
A3

I

.~._

Outputs
[Signal

I Active

Connector/

H

PlA2S

L

P2AZ8
P2B24
P2B07
P2A09
P2B15
P2B13

PRT BIT
PRTAQ
PRTM
INTOO

L

m

L

Vlf}

L

PFIND
CLREQ
CLRXM

H

L

H
H

PZBIZ
P2A29

i

Par i ty Bit

3

Dl

Dl
Cl

C1
C1
Bl

1

'------+----"--_.- --"'---

5-346

Locat ion
Sheet
Square

Function

Pin

i

rotect Fault

B1

! rid icator
(PRfl\)
l'
Clear
RQ fl ip-flup

- - - -_..

Al

3

Dl

.- ........ - - _ .

89633300

A

CONSOLE INTERFACE

(Drawing number 89618800, sheet 3~ contld.)

Desc r i pt ion
An illegal instruction sequence is detected by the fl ip-flops MXl7
(U48/S,8).

is MXI7.

The MXl7A flip-flop (u48/S) is clocked by IRCK.

Its data input

The first half of the fl ip-flop (MXl7A) stores the protect

status of the current instruction.

Its output clocks MXl7B (U48/9).

When a protected instruction follows a non-protected one, the output of
MXl7A goes high causing the Q output of MXl7B to go high.
The MXl7A flip-flop is set by the signal

MCT +ENI + PRTSW. Thus the first

instruction after a master clear or after an enter-interrupt sequence may
be protected without causing a protect violation.

When the protect switch

is NOT set, every instruction is considered protected.
flip-flop is cleared by ENTER + Slt/EEP + PRFB.

The MX17A

PRFB is active when a

protect violation caused by an illegal instruction is sensed.
instruction is executed as a non-protected selective stop.
sweep modes are also non-protected.

Such an

The enter and

The output of MX17Ais also used

on

the Memory Control assembly and by the A/Qand DSA busses.
The flip-flop MX17B is preset by:
MCI + ENI + PRTSW + ENTER + SWEEP + PRFB
This blocks a protect violation when the protect switch is not set and
allows a protect violation to be cleared by the master clear signal or by
the enter interrupt sequence.

It also causes the flip-flop to be preset

after a protect fault is detected.

The MX17B is cleared by PRFB to ensure

correct timing.
The protect bit fl ip-flop
read from the memory.
(see sheet 2).
Console.

89633300

A

(U24/6) stores the protect bit of every word

The data input is MXl7 and it is clocked by WRQ

The output, PROTECT-BIT is displayed on the Programmer's

5-347

CONSOLE INTERFACE

(Drawing number 89618800, sheet 3, cont'd.)

The flip-flops PRFA (U35/15) and PRFB (U35/11), are set when a protect
fault is detected on the console interface card.

The clock is PH3 and

data input to both fl ip-flops is the following function:
VI (I) = PRTSW· MX 17B + PRTSW· MXI7A· RtH ·1/.100· (F=O) • (I NR·IO+I E+R3°Rli)
Th iss i gna lis ac t i ve when the protect swi tch is set and an i 11 ega I
sequence is detected; or when the switch is set,. the current instruction
is not protected, and one of the following instructions has been read:
EIN, liN, SPB, CPB, EXIT, or INR (Inter Register).

Here the M register

is a destination register. The flip-flop J-input is VIO. It is also used
by the Timing assembly to block the memory request signal CRQ and to avoid the
clock JKCK when one of these violations occurs (see Timing, sheet 2).
The PRFA flip-flop may also be set, through its preset input, by the signal
CVIOI from the Memory Control assembly.

This signal becomes active when the

memory control detects protect violations during a memory cycle, caused by
the CPU.
CVIOI also sets a latch made up of two NAND gates (U8/8,11).
reset by the signal:

Th i s I a tch is

(1)00+(1)0 02+PH 3+ENTER+S\IE EP+RN I
The signal

PfF

is active when the latch is set or when the signal

PEL·MXI7A is active.

PEF is sent to the decoder and is used to avoid

changing the A register during the SPA instruction in case the memory write
cycle was aborted due to protect fault or parity error.
The PRFA flip-flop is cleared by the signal MC·PRTSW.

It may also be reset

by KPF which is produced on the Console Interface (sheet 7).

It is active

during skip-on-protect-fault or skip-on-no-protect-fault instructions.

5-348

89633300

A

CONSOLE INTERFACE

(Drawing number 89618800, sheet 3, cont'd.)

The output of the PRFA flip-flop (PFIND) is connected to the PROTECT FAULT
indicator on the Programmer1s Console.
It is also wire-ORed through open collector inverter (u47/8) to be part of
the signal INTOO which is hard-wired to the zero level interrupt on the AlU
least significant board (lSB).
The equation of INTOO is:
INTOO = PEl·RGPWR·PFIND
The PRFB flip-flop is cleared by PH1.
It produces the signal ClREQ which
is sent to the Timing assembly to clear the RQ flip-flop.
This prevents any
memory request signal even after the VIO signal has become inactive.
The
ClREQ signal also clears the instruction register so that the instruction is
executed as a non-protected selective stop (see Console Interface, sheet 5).

89633300 A

5-349

CONSOLE INTERFACE

(Drawing number 89618800, sheet 3, cont'd.)

The timing diagram for the protect fault detect sequence is shown below.

'--------- --------

t:

o

co
"0

Q)
III

:::J
IU
U

:::J
IU
I.L

..,
U

..,
Q)

o

'-

Q.

t:

'-

:::J

o

Q)

U

t:

Q)

:::J

.-E
t:

I-

!!
Go
5-350

z

o

II:

~

III

Z
II:

IS
89633300

A

...

ow

00
\0
0"\
W
W
W

7,Z(')

"I

,

1v

ren

•

(CLRlCM

o
o
~PRT8IT

>

.....-

RI5

-vee
180

PRTSW' rEO"'.

"

"I

vee
MXI7
lRCK

11""

FEO

" Izo.P'IR'

,

Ii'

PRUO

P2824

'Pii'i'i

PZIUl

(iffii

I ....... (PEF

ilJDDZ
INR

I"
IE

R5

•

R4

......

(iii

I>IF

&.P."

(PFIND

1''9

.......

(CUEO

I

Cvr;1

RGPWR

4~
.

PlB22

5

t.::.J

~

L::.J

1~8
~
I a

z~

PH5

PHI

~I

e@

Ie .~
,vee !WI

SWEEP
V1
I
W
V1

ENTER

DETAILED LOGIC DIAGRAM
CONSOLE INTERFACE

CONSOLE INTERFACE

(drawing number 89618800, sheet 4)

TEST MODE AND AUTO RESTART
Function
This is the circuit which executes the commands from the TEST MODE and
the AUTORESTART positions of toggle switches on the Programmer1s Console.
Both features cause the computer to start running after a master clear.
Inputs

r--~-igna 1

Connector/
Pin

Active

r-'--'--"--'' --" -." -.--.. . _-.,
OPST
BEA
AUTRSW
TMSW

H

P2B09

H

32M

H

P2B31
P2A08
P2A2 '•
P2B26

L
L

------,.----------" ..

--~-.---

..........

---.-..-----.--,....

Function

,

.'

-

-.-~

.. .. -. -".-'-, ..,'----".,,~-,

Locat ion
Sheet Square

._--_._----_.- .-'''''- ---4

D4
04
B4
B4

Breakpoint signal
Autorestart switch
Test Mode switch

4

B4

4

C1

Outputs
BEAC

5-352

H

t

P2A30

~EA

controlled

89633300 A

CONSOLE INTERFACE

(Drawing number 89618800, sheet 4, cont'd.)

Description
The test mode feature is activated either by the TEST MODE switch or the
AUTORESTART switch, both on the Programmer's Console.
These switches produce the
signals TMSW and AUTRSW respectively, which clock the test mode flip-flop
(TMI, TM2: U17) with the signal
32M-(TMSW + AUTRSW-AUTiRS)
where
32M is a clock of about 32 psec period generated on the memory
control board.
AUT8RS is the output of flip-flop USI8 (see below).
two-stage counter formed by TMI and TM2 are decoded as
The outputs of
MCT (U44/3) and ~ (U20/6). These signals generate a Master Clear (Me)
and then a clock pulse to the G~ flip-flop. The latter starts the computer
running (see sheet 2).
With the AUTORESTART switch set the computer is master cleared and starts
running on restoration of line power after a power failure.
When a power failure occurs, the signal

N~RMAL

from the Memory Control assembly

goes low. When power is restored, N~RMAL goes high, clocking the AUT~RS
flip-flop (USIB). If the AllTORESTART switch is set, the test mode flip-flops
are activated, causing Master Clear (Me), and clocking the G~ flip-flop.
The G~ flip-flop produces the signal SGI (see console interface sheet 2)
which resets AUT~RS thus clearing the test mode flip-flops and allowing
the computer to run.

89633300

A

5-353

CONSOLE INTERFACE

(Drawing number 89618800, sheet 4, cont'd.)

The AUT~RS flip-flop also resets a latch (U6/3, 11) which blocks the
breakpoint signal (SEA). This latch is cleared by Master Clear.
The gates U3/6 and 1J34/6 produce sync pulses when the contents of the
breakpoint register and that of the memory address register are equal.
These pulses may be, used for hardware debugging.

5-354

89633300 A

....
00
\.0
0"
\A)
\A)
\A)

0
0

-I
OPST

.... P2B

::t>
2,3.6.7 ~
61.2@-=,
•
BEA P2B31

P2A30

1

2P2A24
32M

VCCI~~------~----------J

>P2B26

\TI
I
\A)

\TI
V'I

.......

V'I
I
\A)

\TI

0"

DETAILED
CONSOLE

LOGIC DIAGRAM
INTERFACE

CONSOLE INTERFACE

(drawing number 89618800, sheet 5)

ALU LOGIC
Function
This circuit performs arithmetic and logic functions in conjunction with the
two ALU boards of the CPU.
These functions are:
carry generation
calculation of the trap address
QSX: (contents of Q register) < (contents of X register)
DBB: that bit of the bit bucket register which is used to generate
the sign bit for the result of multiply/divide operations.

NOTE
Two ALU assemblies are used to accommodate the
16 bits of the computer word (without parity or
protect bits).
One assembly designated LSB,
operates on the least significant bits (bits
00 through 07), the other assembly (HSB) operates
on the most significant bits (08 through 15).
Signals associated with the LSB are labelled
L, those associated with the HSB are labelled
H, these letters being appended to the signal
name.

89633300

A

S-357

(Drawing number 89618800,

CONSOLE INTERFACE

sheet 5, cont'd.)

Inputs
•

~... ~ ~ g~~ ~--"r-A~-t'i' :~.. I-~~~-n-~~~~-r ,p~~-T-~:~'~~ i on .--------.--. - ·

I

I·

!
I

,

j

J

i TA2M

! TA2L

,

----+------ .
i
H
P2A21
II
H

,

; TAIH

•

.

.

•

j

j

I

j

P2B26

. ..

Location
sheet squa re

.~----

04

5

04

Trap address generators

P2A17

04

P2B17

04

H

P2B16

04

TAOL

H

P2AI5

D4

GMM

H

P2B03

ALU Carry generate

PMM

H

P2A02

ALU Carry propagate (b its 12

GLM

H

P1B20

ALU Carry generate

: PLM

H

GML

; PML

H

j

; TAlL
,If
: TAOM

H

I

I
I

I

.

15

c4

T

15J

c4

(b i ts 8

T

11 '

c4

PIA21

ALU Carry propagate (bits 8

T

11 '

c4

H

P1B31

ALU Carry generate

(bits 4

T

7',

c4

H

P2BOl

ALU Carry propagate (bits 4

f

7)

c4

: GLL
I

H

P2B02

ALU Carry generate

(bits 0

T

3)

c4

i PLL

H

P2AOl

ALU Carry propagate (b i ts 0

T

3)

C4

H

PIB08

02

H

PIA08

02

j Q7M

H

P1B09

02

!

L

PIB07

j

(b its 12

j

~

l

·
I

1

; A7M
I

i X15
I

I;03
II

F ... 3

C2

{X} > {Q} on LSB

C2

{X} < {Q} on MSB

C2

,

i XGQL

H

P1A03

i XSQM

H

P1B02

XGQM

H

PIA02

I

\

I

I
5-358

. _-

.. -.

~--

." -

_.,'

••••

p. • • •

~.

",

I

j

I
:

{X} > {Q} on MSB
- -.- ...... ... -..............
... - ... ....-.. ..
'"'.~

~-.-

,

" ,..

-, ....

-.~

........ _.. - ... -.-, ...

5

...-

.....

-J

C2

-~.

--_........ ...

89633300 A

(Drawing number 89618800, sheet 5, cont'd.)

CONSOLE INTERFACE
Outputs
'~'~"-'-"--"

Signal

Active

-->.,--.... ". . -.- ..
~

~~~-'

.--~,---.

ITAliL

l

P2A26

ITA3l

l

P2A18

ITA2l

l

P2A16

MCNM

H

PIB30

LCNM

H

P1B29

MCNl

H

PlA31

H

~"

..,,--

H

P1A06

LQSX
-_____

H

PlB03

~.'-.--

.

"--,'-

.. -.' --',

•• - - - - - - "l

I

Function

-_

.. ..

"-.~,,,,---

... _.--'

.-- ....
'

Location
i
sheet square!
-~

-- - --",..,.

-'---"-'-~"'-

-" ...

5

'_·'_·_-1
!
03
03

Trap Address

03
C3

Carry output to MSB

-" -

C3
C3

Carry output to lSB
i
i

- II

{Q} < {X},
. .,..

-. .
~.--

R·_·.'_·Y _.. '" .. _.•

...

~

.. --..

~

I

B3

!

Cl

5

Cl

I

Bit bucket sign bit
"

A

., .

P1A23

DBB

89633300

--- _.... -- ..

...

Connector/Pin
- .. ,'

LCNl

--_

j

over 16 bits
........
....... ..----,....
'.
".- "'.

"'.~

"

'~

,

5-359

(Drawing number 89618800, sheet 5, contld.)

CONSOLE INTERFACE
Description

NOTE
The two AlU boards will be refered to as follows:
MSB:
lSB:

Board dealing with eight most significant bits;
Board dealing with eight least significant bits.

The carry generator of the AlU is the look-ahead microcircuit, u49.

It

accepts the carry propagate (p) and carry generate (G) outputs of the AlU
microcircuits (74181) from the AlU circuit (sheets 2,3), and returns four
carry inputs.

Each group of four bits of the AlU produces a G and a P

signal, the suffixes specify the group of bits.

The following table is a

key to these suffixes.

-.---·--1--·Group
. ---·· . -·· -· ·of· , bits
. - . ---.. .i. . ' Bit

I Board
I

Nos.

i :
1--.. _-_ ..... -·-1-..--·---- --- ....-.- ------ ..• ----.--.. _. .... .. .
LSB
lower
.
0
3
!
,.,

~

I

i;

5-360

lSB

higher

4

MSB

lower

8

MSB

higher

11

--,

Suffix

I
;

~

.

!

i

.

7

. 11
.. 15

LL

Ml
LM
MM

89633300 A

CONSOLE INTERFACE

(Drawing number 89618800, sheet 5, contld.)

The logic equat ions for the output signals are:

.

(GLL • PLL
= GMH • GML • GLM
MCNL = LCNL • GLL + GLL ·PLL
LCNL

LCNL

GML

GLL + GML

LCNM

=

MCNM

= LCNl • GML • GML • GLl

+ PML) + GMM

PLL + GML

GLL

.

(PLM • GLM + PMM)

PML

+ GlM • GMl • GlL • Pll + GlM • GML • PML +
+ GlM • PlM

The signal LCNl is generated in the super-high speed AND-OR-INVERT gates U50, U36/6.
The output signals are returned to the AlU board designated in the last letter
of the signal name:

lNCl and MCNl to the lSB, lCNM and MCNM to the MSB.

The trap address is calculated from the TAO, TAl, TA2 signals of the two AlU
boards, the corresponding signals from the two boards being ANDed together to
form the trap address signals (ITAll, ITA3l, ITA4l) which are returned to the
lSB.
Comparison of the contents of the X and Q registers is performed on each AlU
board for the bits on that board.

The following signals are generated and

sent to this circuit as inputs:
Signal

Note:

Origin

-Sig~I!2~;;~c~i

XGQl

lSB

{X}

> {Q}

XGQM

MSB

{X}

> {Q}

XSQM

MSB

. {X}

< {Q}

{X} signifies "content of register X over the eight bits of the board".

The output of this circuit is QSX which is active when the content of register
Q is smaller than the content of register X, over all 16 bits.
QSX ~ XGQM + XGQL • XSQM

89633300

A

Its equation is:

5-361

~ONSOLE

(Drawing number 89618800, sheet 5, cont1d.)

INTERFACE

The bit bucket, located on the decoder card, is used to store a bit at the
beginning of multiply and divide instructions. In multiply lnstructions
the bit stored is A7M~X15 where A7M is the sign bit of the A register and
X15 is the sign bit of the X register.
In division the bit stored is Q7MEe X15 where Q7M is the sign bit of the Q
register. Thus the bit will be set if numbers of different signs are multiplied
or divided. The bit bucket is set by the signal DBB generated at U54/8, from
signals of the A, Q and X registers on the MSB:
DBB

5-362

=

(A15~ X15) • 03 + (Q15@ X15) • 03

89633300

A

....

oJ

00

\.0
0'\
\N
\N
\N

0
0

7(B)>---.,
..III

7(A
TA2M

'" P2A21

TA2L
TAl'"
TAIL
TAOM
TAOL

l>

P6

P2A20

( ITA4L

A7M

I" B

P2AIB

(ITA3L

XI5

I" II

P2AI6

PIB07
PIAOe (D. .

.. ,

GMM
PhlM
GLM
PLM
GML
PhIL
GlL
PLL

)

P~BQ~

p:-a--

5 '-64K

I

W·_····
....
p ..
"-

'

~

XGOL

..

~.p ;;',i

,

,",'...."-

MCNM
LCNM
MCNL

P-;-:;i
~iiu,
P -g-i
P~MCi

XSOM
XGOM

PIA03
PIB02

P8

PIA02

~
205S

11
2

~U50~8

1

PlA23

 PtAI2
lei > .....0'

•

:$2KW

IT1

180

121

, 51
JI

FIEI

j!)VFL

,.

~

---,

~----~
l.i~~2.r- -6.3<.\:

, '.

SLK

>

PtA07

~
1.1

AM

>

PI426

14

AL

\lCCf--~.
~ 560

)-£!W..~~t-""I.c.I_ _-

3.2~

~K'VF

f!HL.(~

10

8

I I

51

- -

PIB04

/

'I

030" OE)-1!I2Z

wm ')

P2A07

II

>

I'tf0

11

>

I'IAO'

,

51

4

'-

c.n

A)

~
6
U43

J:"
180

1'2830

(WE2

WEZ

j

I

W
-....J

..........
W
-....J
N

DETAILED
CONSOLE

LOGIC DIAGRAM
INTERFACE

A

TELETYPEWRITER (TTY) CONTROLLER
The Teletypewriter (TTY) Controller circuits are accommodated on a single

I

50-PAK wiring board. The logic circuit diagrams and descriptions cover four
different printed wiring assemblies (PWA) in the field. The relevant pages
are indexed in the lower table on this page.
The TTY Controller interfaces the computer CPU with a Teletypewriter Terminal
or with a Console Display Terminal (COT). It provides for communication at
9600, 1200,300 or 110 bauds. The baud rate is selected by inserting a jumper plug in the appropriate location on the board (see circuit description,
sheet 4. This page lists the functional blocks accommodated on this board.
The circuits and signals are described in detail on pages facing the corresponding sheets of the circuit diagram.
This board also carries the Breakpoint Logic.
MAIN FUNCTIONAL BLOCKS
Shown on sheet

Designation
A/Q channel data path

2

Controller/Teletype interface

3
4

Oscillator - Baud rate selector
Address decoding - Reply/Reject logic
Control and interrupt logic

5
6

Breakpo i nt logic

7, 8

PWA PART NO.

PAGE

89967400

5-374
5-402

89947600
89984700
89976400

89633300 E

I

5-410
5-416

5-373

TTY CONTROLLER (PWA 89967400, Logic Diagram 89616400, Rev. J)
A/Q CHANNEL DATA PATH (sheet 2)
Function:
This circuit receives parallel data from the CPU and converts it into serial
form for transmission to the teletypewriter. It also receives serial data from
the teletypewriter, converts it into parallel form, and transmits it to the CPU.
Inputs
L(jCA liON
SIGNAL SOURCE/
SIGNAL
FUNCTION
SHEET SQUARE
CONNECTOR PIN
AOS
P2B23
2
0-4
A register bus bits
A13
P2All
0-4
RDA
[U22/18]
Reset Data Available
0-4
SDIN
[U22/20]
Serial Data Input
B-4
CP
[U22/17]
Clock Pulse
c-4
EPS
P2A28
Even Par i ty Select
0-2
PARITYSEL
P2A22
Parity Select
0-2
-12V
P2A23
,
Supply vol tage
B-4
Bi~directional Signals

}

AOO-

ACT
A02
A03
A04

A05
A06
A07
A09
A10

P2A20
P2B20
P2B19
P2A17
P2A21
P2B22
P2B18
P2A19
P2B24
P2B26

-

,
Busy Status
Interrupt Status
Data
End-of-Operation
Status
Alarm
Lost Data Status
Parity Error Status

2
or

or data
bits
to/from
A-register

'2

A-l
A-l
A-l
B-1
B-1
B-1
B-1
B-1
A-l
A-l

Outputs
All
SP0UT
TBMT
Ef/JC
f/JR
DA
PE
5-374

P2B28
[U22/25]
[U22/22]
[U22/24]
[U22/15]
[U22/19]
[U22/13]

Serial Data Output

-2

End-of-Operation Status
Data Ava i 1ab 1e
2

0-4
C-l
C-l
C-l
..A-4
A-4
A-4
89633300 E

TTY CONTROLLER

(drawing 89616400, sheet 2, cont'd)

Description
Lines AOO through A07, A09 and Ala cOll1Tlunicate with the CPU and serve both
as input and output lines. Lines Ao8 and Al3 are served as inputs to the
controller.

Signal All is an output from the controller. The input signals

are buffered and converted. They are used as director function bits and are
input to the Universal Asynchronous Receiver/Transmitter (UAR/T) U22, and
other parts of the controller.
The

circ~it

(UAR/T).

is built around the Universal Asynchronous Receiver/Transmitter

In its receive portion, this accepts serial data from the teletype-

writer (SDIN) and converts it to data on eight parallel lines (terminals

5 through 12) timed by the clock pulses (CP) from the oscillator baud rate
selector (sheet 4). In its transmit portion, the UAR!T accepts parallel data
on eight lines (terminals 26 through 33) and transmits it to the teletypewriter as SDg}UT under the action of the srtme clock (CP).
The control inputs to the UAR/T are XR,

OS, CP, RDA, PARITYSEL, and even

parity:
XR resets the internal registers of the UAR/T

OS is a strobe for parallel input (transmitter)
CP is the clock input

RDA resets the data available signal DA (receIver)
PARITYSEL is used to select the parity option,
EPS: selects whether even or odd parity is used.
The following table summarizes the action of the parity selector signals:
SIGNAL

LOGIC
LEVEL

EPS

High

EPS
PARITYSEL

Low
Low

PARITYSEL

High

89633300

E

FUNCTION
Even parity generated in UAR/T
Odd parity generated in UAR/T
Enables parity in UAR/T (7 data + parity bit)
No parity generation (8 bits from CPU)

5-375

TTY CONTROLLER (drawing 89616400, sheet 2, cont'd)
The control outputs are PE, SR, DA, TBMT and ESC signals •
. PE is active when the parity option is selected and a parity error is detected In the serial data input.
SR is active when a new character is received on the SDIN input, and the
DA output has not yet been reset.
DA is active when a character has been received on the SDIN input and is
stable on the parallel data outputs.
TBMT is active when a new character is transmitted in the SDSUT and remains
active until the start of transmissfon of the next character.
The dataflow from the CPU to the teletypewriter is thus from the common
input/output lines of the controller (AOO through A07, A09, A10) with parallel
data, to the single line serial data (SDSUT), according to the baud-rate
clock and according to the control signals.
The data flow to the CPU is selected by multiplexers U23, U37. The outputs of
these multiplexers are either the eight data bits from,U22 or the eight status
bits: Busy, Interrupt, Data EOP, Alarm, Lost Data and Pari.ty Error. One status
bit is always "1". The data selectors are controlled by signal DSEN which
comes from the address decoding and reply/reject logic. Bits AOO to A07 are
strobed by the signal (DSEN+RDA+READ) which comes from the receiver/transmitter
control logic. This signal is active when the controller sends data or status
to the CPU. The status bits are strobed by signal DSEN. They are used as fo1lows:
A09: read mode
All : manual interrupt
NOTE
Sheet 2 on page 5-378 differs from some older revisions
in the following areas:

*
*
*

5-376

zone B-4: U22/20 is not connected to U22/21 (zone C-l)
zone C-3: AND-gate type 140 is U7I9,10-8
zone A-2: AND-gate U68/1,2,13-12 is type 213S

89633300 E

SHEET REVISION STATUS .,
I 2. :3 '1 5 b '7 8 9
J

0FF SHEET REFERENCE

0::>

\..0

(J'\
VJ

OFF SHEET
REFERENCE LETTER
A
8
r---0

v.J
W

o
o

2
8-4
8-4 -

3
~--.

SHEET
4
8-1

L0CATl0N
5

7

6

A-3

. -- - -

8-4
8-1
-- - ' - -F
8-4
C-3
f---..
A-4
A-4
G
8-3
J
C -I
---K
A-4
8-4
f--L
C-3
C-I
A-4
C-3
M
C-4
C-3
N
c- "
8-3
A-3
P
Q
8-3
C-3
C-2
8-3
8-1
R
8-3
0-1
S
T
A-3
0-1
8-1
U
A-3
C-3
C-3
V
C-4
W
C-3
8-4
C-3
C-3
X
y
C 2
0-2
9-4
C-2
B-4
C-2
Z
----0-4
C-2
AA
C-2
C-2
0- 3
A8
C-2
AC
C-I
B-2
AD
C-I
8-2
8-1
8-2
AF
AG
8-1
0-2
C-2
- - - - - A : ; - - - - -~-- r-'
C-2
8-1
- ' AK
8-1
C-2
0-4
-C-I
AL
C-I
------ - - - A M - - - -C-=-' f--c--- -0-3
-'C-I
8-2
_.~N_ _
._
AP
A-4
- 8-4
_ AQ
B-4
B~
8-3
8-1
A-2
AR
--- - --- - - -f - - - - - AS
- - ----f------ C-3
A-4
-.
---- ----.-- r----AT
<:-i t---C-3
_.
- --r-- --AU
0-2
C -2
~-

IT1
I

8

~---

A A AA A A A A
C B A B B A IB A
D D D IB B .!L F IA

I

J J

JJ

R53

'"

~VCC
R.O

@

'"

----_J'ovv'v------t vee

RI2

RI9

"
0.:3~VCC
\J1
I
v.J

JVV.-------.vcc@------vvv-------4 VCC
R35
IK

RI6
IK

r---------- . _ . -

I--___BR_ _

~vcc~~vcc

:..3-

RI
IK

R68
IK

~',''-----4'VCC @-~'VCC

-.....J
-.....J

BS
BT
BU

B-1
8-1

. ..•

--

-

A -,

,

~.

0

,

,:.

~

A-3

.

. ,,','..
"

...

f

)0 NOT SCALE
... ,~ 1 I HI:,

....
'0 ...

'0 a.


'il;l .

'j

"f ~

•

A-2
0-3

A-4

ALL UNMARKED

N"TE

i
g~

6

RESISX0RS

ARE

I

DRAWING

"

flB11 COMPU[fRS lTD

I ".' N

•

.a..B

•

, •

1!§!E'lP&ill
r

,',1,-'

...
.'...
.,

~

,

AB loe-A

.. :'

':''''

,,"

Ii 1.

"

4(l~ '"

~~,

---

K

(i~

H~!~

J.

'1; iJ..y.t

8

-

-

I

~

B- 3
8-3
0-2
C-I
C-I
C-I
A-3

• C-4
B-4
0-3
8-2
A-2
A-2
A-4

I

B-3

DETAILED LOGIC DIAGRAM
T.T.r CONTROLLER

,

PIN 899,7'TOO

I' ". Ie

. -'--"---

.... c ...

-

-

5'.

0.25 WATT

7

C -I
8 -4
C -I
0-4
8-2
8-2
0-3
C-I
0- 3
9-3
0-4
0-3

f--

BW

..

"'

5
0-3
C -3
C-3
8 -2
0-2
C -3
C -2
C-I
8-1

.-

BV

•

'

T - - - - - - , --- - - --;;;:----

----

1-.-

'.,.f\<

CI1KO A ••

I

f-------- BQ
~ ..

0.',

ORFT

9

r-----Sp-~-- f------

I
I

P~6E

~

~----.

~VCC~VCC
~;6
7;<.8!

®-

SEE

4
0-1

3

--

RI.

[;l SCkJPTI(j-'

J J HAJ

2
AV
AX
AY
AZ
1---8A
--8S
1------- -80
8F
8G . - - r------,-,
f----A~4
BH
~-.
8K
8L
8M
8N

..

-----

,
fCO

E I::. ]) B B E B A E
F F DF B E F A F
G FiJ) G :it E F A G
J..\ H D!H B E J-l A iH

~-

I

.

.

REVISION RlCORO

,:

,

I

kAwrro.',

~,

89616400
<; .. ~ f

r

I

,,9

--

._.,_.......
l -

V1
tNt"' ....

""r

P2A28-

III

P2A22

1111
III

00
PARITYSEL

:; ::

AI3

~3,!I

I

::5=

HI;

.@-.-'....-:
2 204
;®-~~
~

6W
5.6 L

a

9
I

S

140

u7

5 M

36

P
~ I--

~--

-

~a

3

AIO

6

Ail

"

A9

1

I
II 146
U25

6

.e'

II5l
F

~

X·Y

3~)--ZQ
U22

__ -...I:
~

~

~
-:

rn

~I

6~~ 7

~6~~14

OUT4

,-->"----'
..
I~~.I
-,:-

7

8

'

9
10
II
12

9 ~
A-:3_ 31--

8
4

A2
A3
A4
A5
A6
A7

--

~6
19

9

I

6~1;)-

i3

~-~6

I
'

'--

1;5---

6@H
6 I

~~
:3

~

5 '~'I

7
4

5~
4
__

1

l

~

,~

U22

~

26

27

28
29
~

~
B

6

:3

F-<

"T'

3L
~

33

~

6

Ii.F 5

.AS
AG 3,5
A8@S
A4
AK 5,6

~--

~f--r--'

---

"A3

#

P2A19
P2818
P2822
P2A21

(

P2A17

(

<
<
<

A2

P2B19

Ai

<

P2820

-<

_

~&...AO

P2A20

I

"

"--

1m
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DETAILED LOGIC DIA8RAM
T. T. Y CONTROLLER

TTY CONTROLLER (drawing 89616400, sheet 6)
CONTROL AND INTERRUPT LOGIC
Function
This circuit generates an interrupt signal for the End-of-Operation (E~P),
ALARM, DATA and Manual interrupt conditions.
It also contains a number of control fl ip-flops and generates the associated
signals:
Signal

Flip-flop
READ/WRITE, MrlJDE
DATA READ, LrlJST DATA
MECH BUSY

\"'M~DE,

RMrlJDE
~, LrlJST DATA(LD)
BUSY, ErlJP, DATA,
MECH-BUSY

Inputs
SIGNAL

ACTIVE

MNL -INTRPT
MNL - I FJiRPT

CONNECTOR
PIN

L
L

P2A13
P1A05

L
L

P2B25
P2Al2

FUNCTION

LOCATION
SHEET
SQUARE

Manua I Interrupt
) from Progranvner IS
console

6
6

c-4
c-4

Character Input
Interrupt (E~P)

6

A-3
D-l

1

Outputs
...&.-

CH I"

INTIL
NOTE:

5-390

6

Sheet 6 on page 5-395 differs from some older revisions in the following areas:
* zone C-3: the Manual Interrupt flip-flop is U5/11, type 242H
* zone c-4: 68NF capacitor c16 is not connected between signal
MNL INTRPT at P2A13/P1A05 and ground.

89633300 E

(Drawing number 89616400, sheet 6, cont'd)

TTY CONTROLLER
The Interrupt Circuit

Each of the interrupt conditions (DATA, E0P, ALARM) is set by the
corresponding director function (A02, A03, A04) together with the signal DFEN,
and is latched in the corresponding D-type fl ip-flop (part of U2). The
interrupt conditions are reset by the Clear Interrupt (CLEAR).
(U2) are clocked by DF=WRITE·MC.

The latches

When the latch output (interrupt enable)

coincides with the corresponding signal, an interrupt signal is produced at
the output of u6.

The Manual Interrupt signal (from the MANUAL INTERRUPT

pushbutton on the Programmer's Console) sets the manual interrupt flip-flop
(US) and also sets the interrupt signal through u6.

The following table

summarizes the action of this circuit:

Note:

Latch
Terminals

Interrupt
Condition

Director
Function

Gate

Data

A02

U36/6

u2/4,3

EfJP

A03

U21/8

U2/12,11

ALARM

A04

U21/6

U2/s,6

Manual

---

US/II

---

ALARM INTERRUPT

=

PE·DATA·READ + LfJST DATA

that is when a parity error is detected on input data or data is lost.
The output of gate U6 is used as the interrupt status bit in the A/Q channel
data path logic circuit (sheet 2); its inverse (US6/11) is transmitted to the
CPU.
Control fl ip-flops
The Read/Write gate (U36/8) forms a latch with U2/13, 14 to produce the
clocked mode signals WM0DE and RMfJDE used in the control and teletype
interface circuit (sheet 3).

It is set by the director function A08, ANBed

with EfJP and DFEN and reset by RESET from the address decoding and
reply/reject circuit (sheet 5).

89633300 E

5

TTY CONTROLLER (drawing 89616400, sheet 6, cont'd.)
The Data Read flip-flop (U43) stores the information showing that a charactel
has been received from the peripheral device. It is preset by the function
DA·RM0DE·ID·MECHBUSY
Where
RM0DE means that the controller is in Read Mode
DA is an output of U22 in the A/Q channel data path logic
L0ST DATA,(~ is an output from flip-flop U9 and means that a
character has been received by the controller and not transferred
to the CPU
MECHBUSY (output from flip-flop U43) means that the controller is
sending a character to the peripheral device.
The data read flip-flop is cleared by the rising edge of the signal
from u28 and it is asynchronously cleared by CC0N+MC or L0STDATA atR~
The flip-flop Lost Data (U9) is clocked by the rising edge of the signal.
DATAREAD·MECHBUSY·0R
loutput ofU29), where 0R comes from the UAR/T of the A/Q channel data
path logi c.
The flip-flop is cleared asynchronously by CC0N+MC or RM0DE (u60/8).
The signal L0ST DATA (LD) is used as a status bit in the A/Q channel data
path logic.
The MechBusy flip-flop (U43) is set while data is transmitted to the
controlled peripheral and is cleared when the transmission has been
completed and the WRITE signal is no longer active.
Its actuating signals are as follows:
Set:
Preset:
Clear:
5-392

by TBMT from the UAR/T to the A/Q channel data path (sheet 2)
CC~N+MC

by rising edge of E0C·TBMT.RDEN·~
89633300

E

TTY CONTROLLER

(Drawing number 89616400, sheet 6, cont'd)

Miscellaneous output signals are produced using the signals of the above
fl ip-flops.
These are:

Equation

Signal

Description/Remarks

Origin

LOST DATA + CHI

to UAR/T of A/Q channel data
path (sheet 2)

U29/6

REAb-PAIAREAD

Character Input prevents the
most significant field of
the CPU A register from
being changed during a read
data operation

U52/8

BUSY

MECHBUSY + DA·RM0DE

Status bit

U59/11

E0P

BUSY

Status bit (End-of-Operation
interrupt)

U24/12

DATA

E0p·WMODE + DATAREAD

Status bit (data interrupt)

U42/6

PARITY ERROR

PE·DATAREAD

Status bit (data interrupt)

u8/ll

ALARM

PARITY ERROR

Status bit (alarm interrupt)

u8/6

Active after transmission of
character used in the UAR/T
of the A/Q channel data path
(sheet 2)
timed by 1.3 psec signal.

U28l6

os.·WRITEE0p·WM0DE.WDEN

NOTE:

OS=

89633300 E

E0P WMODE WDEN + DATAIN RMODE MECHBUSY (1.3 psec) at U27/8.

5-393/394

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TTY CONTROLLER

(drawing number 89616400 sheets 7,3)

BREAKPOINT LOGIC
Funct ion
The breakpoint logic generates the signal BEA when the data sent to the
memory address register is identical to the data stored in the breakpoint
register. This circuit also contains logic for buffering signals between
the CPU and the Programmer's Console.
I nputs

(sheet 7)

SIGNALS

ACTIVE

CNsoB
CNS09
CNSIO
CNS 11
CNS12

L
L
L
L
L

CNS13
CNS14
CNSI5
CSB

L
L
L
H

CRQ

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P1A1S
P1B03

0-4
0-4
0-4
0-4
B-4
B-4
A-4
B-1

P1A03
P1A04
P1B05
P1Bl6
P2B05
P1B04
P2BOI
P2B02
i

B-4
B-4
B-4
B-4

P2A07
P2B04

7

B-1
A-I
A-I

7

C-1

(sheet 7)
!

H
H
H
H

P1A02
P1Al9
P1Al7
PI B20
I

5-396

LOCATION
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P1Bl5
P.l B14

L
L

CONNECTOR
PIN
PI A14

L

Outputs
BEA
SEN
PErNO
RNIB

r

7

B-1
A-I
A-I

89633000 E

TTY CONTROLLER

(drawing number 89616400 sheets 7,8 cont'd.)

BREAKPOINT LOGIC

Inputs (sheet 8)
SIGNALS
BCK

CiJfB
CNSOO
CNSOI
CNS02
CNS03
CNs04
CNS05
CNS06
CNS07
INOINO
ilVFL
EINT

ACTIVE
H
L
L
L
L
L
L
L
L

L
L
L
H

CONNECTOR
PIN

FUNCTION

LOCATION
SHEET SQUARE

PIB02
PIA 16
PIBI7
PIBI9
PI AI8
PlA20
PlA07
PlA06
P1B13
PlAl3
P2Al8
P2AOI
P2B03

8

PIAl2
PIB21
PlBl8

8
8

0-4
0-4
B-4
B-4
B-4
B-4
0-4
0-4
0-4
0-4

8

B-1
A-I
A-I

Outputs (sheet 8)
AOOR
f)VFL
EINTB

89633300 E

H
H
H

8

B-1
A-I
A-I

5-397

TTY CONTROLLER

(drawing number 89616400 sheets 7, 8 cont'd)

BREAKPOI.NT LOGIC
Descri pt ion
The inputs CNSOO th rough CNS 15a re passed to two reg i s te rs. One is an
address register ("latches U34 and. U35).
This register is enabled by the
signal CRQ. The other one is the breakpoi~t register.
This is
made up of four-bit D type flip-flops, U50, u49, u48 and U33 clocked by
BCK and cleared by CLRB. The active high outputs of the breakpoint
regi ster are gated by CSB in open-collector NAND gate buffers (U67, u47,
u65 and U32).
The outputs of these open-collector NAND gates are fed back to the inputs
of the breakpoint register. This circuit allows the contents of the
breakpoint register to be set from the front panel switches. The contents
of the breakpoint register and the address latches (U35 and U34) are
compared by the comparators (UI6, U17, u18 and U19).
If all 16 bits of
the two registers are equal, the comparators generate the signal BEA.
NOTE
Sheet 7 on page 5-399 differs trom some older
revisions in the following area:

* zone

A-3: AND-gateU68/3,4,5-6 is type213S.
Sheet 8 on page 5-400 does not differ from older
revi s ions.

5-398

89633300 E

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89633300 E

5-401

...

TTY CONTROLLER (PWA 89947600, logic diagram 89616400, revision H)
The logic diagrams and logic descriptions for PWA 89947600, logic revision H,
pages 5-402 through 5-409, are basically the same as for PWA 89967400,
logic revision J, pages 5-374 through 5-401.
The sheets of logic revision H are located on the following pages of this
manua 1:

sheet
page

2

5-403

5-404

3
5-405

4
5-406

5
5-407

6
5-408

7
5-399

8

9

5-400

5-409

PWA 89947600, logic revision H, differs from PWA 89967400, logic reVision J
in the following areas!
Sheet 1: Revision H matches PIN 89947600
Sheet 2: *zone B-4: U22/20 is connected to U22/21 (zone C-l)
*zone C-3: AND-gate type 140 is U5/2,1-3
Sheet 3: *zone B-3: the TTS fl ip-flop is U7/11, made up of two type-140 gates.
*zone c-4: the signal at .P2AIO is not identified.
Sheet 4: *zone B-1: AND-gate type 140 is U5/5,4-6
Sheet 5: *zone c-4: U39/6 is connected to U5/9 (zone A-4)
*zone c-4: TP12 is connected to U39/6
Sheet 6: *zone C-3: the Manual Interrupt flip-flop is U5/11, made up of two
type-140 gates
*zone c-4: 68NF capacitor C16 is connected between signal MNL INTRPT
at P2A13/PIA05 and ground.
Sheet 9: revision record H
The logic descriptions for revision J also apply to revision H.

5-402

89633300 E

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4: *zone C-3: AND-gate u68 is type 213H
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sheet
page

2

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3

5-405

4
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5

5-407

6

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7

5-414

8
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Sheet 1: Revision F matches PWA 89976400.
Sheet 4: *zone c-4: The oscillator circuit contains 47 pic9farad capacitor
C20 and 180 ohm r.es"istorR62 in the path of crystal Yl, and 0.47
nanofarad capaci tor C18 to ground, on the input 1 ine to the base
Sheet 9:

of transistor Q6.
revision record F.

Except for the change in the oscillator circuit on sheet 4 described above,
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5-416

89633300 E

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89633300 E

5-419/5-420

....;.

r'II

ENCLOSURE POWER INPUT
The power supply and power input wiring of the main computer enclosure
(equipments AB107/AB108) and that of the expansion enclosure (equipment
BT148) are identical.
A Power Supply Input-Output Wiring Diagram shows the input power distributionl
in the equipment. The power. line enters the enclosure through the line filter
un-it and is taken to the power supply unit (PSU) and the blowers through the
PSU terminals. The PSU generates all internal supplies for the equipment.
The power supply wiring diagrams in this section apply to the following different equipments:
DRAWING NO.
89762200
89942600
89911800

*
*

89601601

PAGE NO.
5-429

•

EQUIPMENTS
AB107-A04 to A09
AB108-A04 to A09

Part of BT148-A06
BT148-A05 and down

5-431

ABI07-AI2 and up
ABI08-A12 and up

Part of BT148-A06

5-433

AB107-A10 to Al5
AB108-A10 to Al5

BT148-A07

5-435

AB107-A16 and up
AB107-C
AB107-D

ABI08-A16 and up
AB108-c
AB108-D

BT148-A08 up
BT148-c
BT148-D

The wire lists in section 9 give details on the interconnections.
The line filter unit and the power supply unit are described later in this
section.

*

In using wiring diagram 89911800 for the programmer's console connections
in series A12, A13, A14, A15, substitute the programmer's console connections of wiring diagram 89942600.
Note also that all series have one forced-air blower in the power supply
and three axial fans installed in the top of the enclosure. Type identifiers C and D have two more fans, installed in the bottom of the enclosure.

89633300 F

5-421

THE POWER INPUT CIRCUIT
The input circuit of the enclosure (Line Filter Unit) is mounted at the top
center of the rear panel. See figure 3-7 and the detail on this page. The
following table summarizes the components and their functions.
FUNCTION

NAME

DESIGNATION
J1

Line power socket

Accommodates the line power cord

Fl

Input fuse

Line protection

F2

Battery fuse

Battery protection

Sl

AC line switch (on/off)

Applies ac line power to the equipment
Isolate the equipment from surges
and noises on the ac line

FL1, FL2
J2

Li ne f i 1te rs

Used in the Margins test
(Refer to section 6)

Margin test socket

At Power
Switch

At Fuse
Socket for
Power Cord

Battery Fuse

OFF

JI

5-422

8A

o
J2

lASS

89633300 F

POWER SUPPLY UNIT (PSU)
. The PSU is an autonomous assembly mounted at the top of the front door of
the AB107lAB108 main computer enclosure and in the same place in the BT148
expansion enclosure. The PSU is part of the equipment which it supplies.
This sheet summarizes the circuit diagrams showing the power supply anit;
the diagrams themselves are. given in the following pages, together with a
br!ef description of the circuit functions. All connectors for connecting
the PSU to the rest of the AB107/AB108 or the BT148 equipment are brought out
on the power supply connector panel on four terminal strips: TB1,TB2,TB3,TB6.
These terminal strips are shown in a figure on one of the following pages.
The interconnection (wiring) diagrams show the interconnections between the
main units of the power supply, including terminal strips, for all series
of computers in the field.
The power supply unit receives the main line power through the input circuit
mounted at the rear of each enclosure. This input circuit, as well as the
general power input connections to the enclosure, have already been presented.
The block diagrams of the PSU and their descriptions appear in section 4 of
this manual. The diagrams are repeated in the following pages for convenience.
Most of the circuitry of the PSU is mounted on two printed
within the power supply assembly, as follows:

c~rcuit

boards

BOARD DESIGNATION
High Power (HP)
and Control

DRAWING NO.

ASSOC I ATED CI RCU ITS.

89657700

Low Power (LP)

89640800

Ac-to-dc converter, Vcc regulator,
+35V preregulator, Protection and control
circuits (except individual current limits)
Regulators, individual current limit circuits, reference voltage generator,
battery charge circuit

WARNING
The power supply does not use a main isolating line-transformer
at its input. Its circuits between the ac line input and the
isolating networks are therefore at line voltage. Do not handle
the PSU while the computer line cord is connected to the ac supply.
89633300 F

5-423

V1

•
.e:N
.e:-

VCC

AC to DC
V CC

+ 3Gv

AC~Lin
Po.... • .

R'gulator
Pr.r.gulator

~

I--

35vac
36vdc

Input
Circuit

---

*

auxiliary

,....--.

AC Lin.
Cord
Chall.1

~

Ground

2!5vdc

--

Logic
Ground

R.gulators .

auxiliary -7vdc

-------r-------'~

,.........

~--~) )

....

Conv.rt.r

Circultl

Prot.ction

----t- ;;f~;;'--

Reference

G.• nerator

~--------+-----------~------------------~~)r----~

+ Sen..
from back
V CC

Battery
Charll.r
and Battery
Crowbar

plane

T.rminal

Th.

main

indicat.d

*

pow.r
by

The Input
port of

flow il

Iiolating
Diod.

Battery
F3

Battery

thick lin. I
Circuit il not
ttl. Pow.r Supply

00

Front Pon.1

'#.

DC

\,to)
\,to)
\,to)

[fJt

1

Not.:

POWER

1--i
...

I

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o
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POW E R

VBB
VCC2

-12v
__ -6V

overcurrent

VCC

--

VSS

SUP PLY B L 0 C K 0 I A G RAM

FUle

Equipment
GD611-A
(Optional)

__ .30v
Unr.gulated

-SENSE
From back plan.
ground terminal

POWER SUPPLY UNIT

(continued)

COMPUTER DC SUPPLIES
Supply
No.

Des i !Jnat i on

Nominal voltage
volts

A

R

+5.3

3

A

R,M

VSS

+16.7

~

r:

A

ABI07/BA201-B,R,M

VSS

+19.7

5

A

ABI0S/BA201-A,R,M

4.

VSS

VSS + 3.5

40

rnA

R, t1

5.

-12V

-12

100

rnA

R,

6.

-5V

- 5

1

A

R

7.

+30V

+30

300

rnA

unregulated, M

S.

battery charger

200

rnA

current regulated

2.
3.

+5

Remarks

35

1.

Vcc
V
cc2

Nominal
Current

Internal suppl i es
9.

+35V

+35

preregulated

10.

auxi 1 iary no.

+25

unregulated

11.

auxiliary no. 2

- 7

unregulated interna
supply

NOTES:
M : supply to the memory only
R : regulated supply
The tolerance on all regulated voltages i s ~ 0.5 percent.
+
The maximum permissible ripple is - 2 percent of each regulated voltage.
See also table 6-1.

89633300 F

5-425

I

I

POWER SUPPLY WIRING DIAGRAMS

I These drawings

show the circuits of the complete power supply units for all

computer series. The circuits accommodated on the two main printed circuit
boards are shown on separate circuit diagrams. High Power and Control (HP)
drawing number 89657700 and Low Power (LP) drawing number 89640800.
Terminal connector strips TBl, TB2, TB3, and TB6 on

the power supply con-

nector panel provide the connections between the power supply unit and
the other circuits of the computer.

A following figure and figure 3-5

show the connector panel. The following table 1 ists the connections.
T

Connection
TB-l/l

Designation

Connection/Function

ON/OFF

Connection to programmer's console
dc POWER on/off switch; controls
power supply operation.

/2

+ SENSE

Sensing wire from +Vcc connection
on enclosure back-plane (Figure 3-7).

/3

RGPWR

Power fail indicator signal for
Low Power Data Retention (LPDR)
operation (to Memory Control board).

/4

-SENSE

Sensing wire from logic ground on
enclosure back-plane (Figure 3-7).

/5

-l2V

-l2V regulated supply output

/6

-5V

-5V regulated supply output

/7

+30V

+30V unregulated supply output

/8

Vee

Vee regulated supply output to
Memory system

/9

VSS

Vss regulated supply output to
Memory system

/10

VCC2

VCC2 regulated supply output to
Memory system
continued

5-426

89633300 F

I

POWER SUPPLY WIRING DIAGRAMS (continued)
TABLE OF TERMINAL STRIP CONNECTIONS (continued)
Connection

Designation

Connection/Function

TB-2/1
/2

/3

Main line voltage inputs from Input circuit:
Nominal Input to
Shorting links
voltage terminals
(terminals)

/4
/5

110V

/6

220V

3, 7
3, 7

1-2, 3-4-5, 6-7-8, 9-10
2-3,
5-6,
8-9

/7

/8
/9
/10
TB-3/1

Vcc MARG }

Connections for margin-tests on VCC
and VBB (refer to section 6)

/2

VBB MARG

/3

+ 30 V

/4

GND

Ground for margin circuits

+BAT

Battery positive terminal

TB-6/1
/2

not used

/3

not used

/4

89633300 F

TEST

5-427

POWER SUPPLY WIRING DIAGRAMS (continued)

GND

o

•

•
Power

Supply

Connector

•Panel

(See also figure 3-5)

The main logic supply (V cc ) and logic ground are brought out on two separate
terminals. A heavy gauge wire, suitable for carrying the high current of this
supply (nominal 35 amperes), connects these terminals to the backplane of the
enclosure.

The cabling of the other supplies also terminates on the back-

plane, as shown in figure 3-4.
Power supply internal connections are made on terminal strips TB4 and TB5,
mounted inside the power supply unit on the frame carrying th~ output filter
and capacitors. Other components are shown on these drawings grouped according to the mounting positions within the power supply assembly. They are
shown in their functional relation to the rest of the circuitry in circuit
diagram 89657700 for the High Power and Control Unit (HP) and in circuit
diagram 89640800 for the Low Power (LP) Card. They are described in the following pages.
For instructions and explanation of enclosure grounding, refer to the installation instructions in section 6 and to the maintenance aids in section 7
of this manual. Refer also to the Site Preparation Manual, publication number 60437000.

5-428

89633300 F

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POWER SUPPLY UNIT (cont'd)
HIGH POWER (HP) AND CONTROL ASSEMBLY (Drawing number 89657700)

WARN ING

I

The power supply does not use a main isolating
line-transformer at its input; its circuits
between the ac 1 ine input and the isolating
networks are therefore at line voltage.
Do not handle the power supply unit while the
computer line cord is connected to the ac supply.
Function
The HP assembly is part of the power supply assembly. It carries the circuits
in the main power path as well as protection and control circuits.
The circuits in the main power path are:
main line
main fuse
switching
current

rectifier and filter
(Fl) and crowbar
regulator for V with its control circuit and
cc
limit detector

inverter (chopper) and main isolating transformer (Tl)
rectifiers and output filters
The protection and control circuits are:
inverter start circuit (associated with the inverter-chopper
in the main power path)
switching control circuit, associated with the V switching
· power pat h
cc·
regu 1ator •In t h
e main
current limit, overcurrent latch and crowbar driver
power fail detector and recovery relay
These circuits are described in the following paragraphs; the block diagram
on the next page may be referred to as an aid in understanding the interrelation of the circuits.

89633300 F

:5-437

POWER SUPPLY UNIT (continued)
HIGH POWER (HP) AND CONTROL ASSEMBLY (drawing 89657700, continued)
Main Line Rectifier and Filter
The ac line voltage from the Input Circuit is applied to the rectifier
bridge CR8. When working from 220V line input, the capacitors associated
with the rectifier act as a filter, with the resistors aiding to divide the
dc voltage across them evenly. When working from llOV line input, the line
voltage is also applied to the junction between the two capacitors (refer

I

to the wiring diagrams) which now act as a voltage-doubler and filter combined. As a result of this configuration, a dc voltage of about 350V is
generated at the output of the circuit with either llOV or 220V line input.
Main Fuse and Crowbar
The power supply unit is protected by the main fuse Fl in the high voltage
dc line at the main rectifier and filter output. It is blown when the SCRtype crowbar CR7 is gated-on by the Crowbar Drive circuit (see below).
Switching Regulator For· V
cc
The main logic voltage V is regulated in the switching regulator, consistcc
ing of main switching transistor Ql, filter inductor Ll, catching diode CRl.
None are mounted on the HP board assembly. Refer to section 4 for a description of the principles of operation of switching

regula~ors.

The Ql

emitter-base feedback path through two windings of pulse transformer T3
sustains 9scillations in the circuit. The third winding of T3 is driven
from the regulator control circuit output, which both initiates and controls
the frequency of the switching.
The V Regulator Control Circuit
cc
Output circuit Q3,Q4,Q5 provides a drive pulse to pulse transformer T3 when
a negative-going pulse appears on the base of transistor Q4. It prevents oscillations by shorting the T3 winding when transistors Q5,Q6 saturate
(positive pulse at their base). Note that transistor Q3 extends the voltage

I

5-438

89633300 F

POWER SUPPLY UNIT (cont'd.)
HIGH POWER (HP) AND CONTROL ASSEMBLY (drawing 89657700, cont'd.)
range of the output circuit. Transistors Q7, Q8; Q9, drive the output
circuit, the point of control for the switching regulator being at the base
input to Q9.
This point is driven normally by controlled pulses from comparator u4 through
buffer Ql3 and oscillator QIO, QII. This circuit compares the Vcc voltage
at the enclosure backplane (+SENSE) with the V reference from the reference
cc
generator. The duty cycle of oscillations and therefore that of the switching
regulator depends on the difference between these signal levels, thus closing
the regulator feedback loop. Transistor Ql4 and associated components
control the rise and fall times at the comparator output.
The control signal at the input to the switching regulator driver (Q9 base
line) is subject to control by the overcurrent circuits actuated from the
overcurrent detectors of the various supplies, except that: in the main
power path (see below).
Note that transformer T3 provides voltage isolation between the regulator
(at high voltage) and its control circuit.
Resistor Rl (mounted outside the HP board) in the main current path is
It is also connected to the crowbar
connected to the current limit circuit.
to blow the fuse in case the current limit fails.

89633300 A

5~439

POWER SUPPLY UNIT (cont'd.)
HIGH POWER (HP) AND CONTROL ASSEMBLY (drawing 89657700, cont'd.)

Inverter and Main Isolating Transformer
The dc power from the V regulator is inverted to 20 KHz ac in the chopper
cc
circuit of transistors Q2, Q3 (mounted off the HP board).
The primary of
transformer Tl is an essential part of the chopper;

it also provides the

isolation from the line voltage in the main power path.

One pair of

windings of transformer T3 is used for current-feedback in the chopper
circuit, the other pair is for driving it.
The chopper is not self-starting.

Phase shift oscillator Ql5 is provided

to drive it through output stage Ql6, Ql7 and the driver coils of transformer
T3.

This circuit is used as a starting oscillator for the chopper on initial

switching on and during start-up after power failure.

Once the chopper gives

an output voltage the circuit provides a feedback path through transformer T2,
resistor R55 and transformer T3.

Note that the change in function of the

circuit comes about because of the low impedance of R55 aQd the path through
T2 as compared with the impedance of the resistor chain (R57 through R60) in
the phase shift circuit.
The main isolating transformer is Tl. It has three center-tapped output
windings. One winding feeds the rectifiers and filters for the main logic
supply V • Another winding provides 35 vac to the LP board and also feeds
cc
the rectifiers for the internal +35 vdc supply. The third one (shown in the
Iwiring diagrams) provides 7 vac to the LP board.
Note that the logic ground is not defined at the center tap of the winding
supplying the main logic voltage Vcc ,but is defined at the output of the
filter for this supply.
5-440

89633300

F

POWER SUPPLY
HIGH POWER (HP) AND CONTROL ASSEMBLY (drawing 89657700, cont'd.)
Rectifiers and Output Filters
The main logic supply voltage (V ) is derived from one winding of the
cc
isolating transformer (Tl) through full wave rectifier CR5, CR6 and its
output filter (C3, C14, L2, T3; all mounted on the filter chassis off the
HP board). Note that a comparatively simple filter network provides a dc
supply with very low ripple content as the frequency of the alternating
supply is high (20KHz) compared to line frequency.
Current Limit, Overcurrent Latch and Crowbar Driver Circuits
The power supply is protected against overcurrent by overcurrent detectors
in a number of circuits. These detectors act through the current limit
circuit, and the overcurrent latch, or directly on the crowbar driver circuit.
When the crowbar driver circuit is actuated, it blows the main fuse (Fl);
when the current limit circuit is activated it inhibits the Vcc regulator
control circuit and activates the power fail detector and alarm.
The various current limit modes are as follows:
if the current I imit is exceeded in anyone of the protected supplies
on the LP board, a signal appears on the overcurrent bus which is an
input to the current latch circuit;
if the current limit is exceeded in the main power path, the current
limit resistor ,associated with the Vcc regulator CRl, mounted off the
HP board) actuates the Crowbar Driver circuit;
if the current limit is exceeded in the main power path, the current
limit resistor CRI) in the V switching regulator also actuates the
cc
overcurrent circuit through optical coupler Ul.

89633300 A

5-441

POWER SUPPLY UNIT (cont'd.)
HIGH POWER (HP) AND CONTROL ASSEMBLY (drawing 89657700, cont'd.)

In addition to the overcurrent protection, the power supply is protected against
the voltage exceeding the preset maximum value on anyone of the regulated
supplies on the LP assembly.
The overvoltage detectors situated there are
ORed together and actuate the crowbar circuit through transformer Tl.
The crowbar driver consists of three firing circuits for the crowbar SCR (UR7).
When the crowbar is fired it blows the main power supply fuse (Fl).
The three
circuits are described here.
One circuit consists of transistors Ql, Q2 connected in a Silicon-ControlledRectifier (SCR) configuration.
When the voltage across the main power path
current 1 imit resistor (Rl, off the HP board) exceeds the base-emitter "on"
voltage of transistor Ql, the compound connected transistors short the crowbar
SCR (CR7) anode to its gate through resistor R7, thus firing it.
As a further precaution against a short circuit, the voltage across the main
power path current 1 imit res istor (Rl, off the HP board) is appl ied' to the
crowbar gating circuit, through diodes CR2, CR3, thus firing it almost directly.
This precaution is included in view of the high currents in the main power
circuits.
This circuit comes into operation only if other parts of the drive
fa i 1.
The overcurrent circuit receives its input from the current limit resistor in
the ma i n power path (Rl, mounted off the HP board) through opt i ca 1 coupler Ul,.
The signal from the optical coupler acts through amplifier Q18, Q19, Q20;
should the instantaneous current exceed the preset value, Q18 applies a

5-442

89633300 A

POWER SUPPLY UNIT (cont'd.)
HIGH POWER (HP) AND CONTROL ASSEMBLY (drawing 89657700, cont'd.)

positive voltage to the Vcc regulator control circuit and cuts the pulse
controlling the regulator.

The overcurrent latch consists of transistors Q22, Q23 connected as a Silicon
Controlled Rectifier (SCR) and associated components.
A signal from the
overcurrent bus from the LP card fires this and so stops the pulse train in
the Vcc regulator control circuit.
As an additional precaution this SCR
may be fired through comparator US.
The comparator is actuated when the
overcurrent signal from transistor Q19 has been present for about one second
(time-constant C33, C32, R67).
The latch is reset by the signal from the POWER on/off switch on the Programmer's
Console acting through the LP card.

The power fail detector (U2, U3), when activated, generates the power fail
signal (RGPWR).
This is transmitted to the Memory Control board and initiates
the Low Power Data Retention (LPDR) mode of operation.
This circuit is activated in the following cases:
when the V regulator control circuit is stopped
cc
when the overcurrent latch circuit has been activated.

89633300 A

5-443

POWER SUPPLY UNIT (conti d.)
HIGH POWER (HP) AND CONTROL ASSEMBLY (drawing 89657700, conti d.)

Comparators U2, U3 are connected as Schmitt-triggers and generate the output.
signal as soon as activated.
To avoid hunting, capacitors C16, C17 act to
delay the resetting of the circuit and the removal of the power fail condition.
This circuit, as the rest of the power supply protection circuits, receives
its supply from the +35 vdc internal supply bus.
also connected to the +25 vdc auxiliary supply.

Note that this bus is
Thus if the power supply

as a whole fails, these circuits remain active, provided the main line
voltage has not been removed.

5-444

89633300 A

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POWER SUPPLY UNIT (cont'd.)
LOW POWER CIRCUIT ASSEMBLY (drawing number 89640800)
Function
The Low Power circuit assembly is part of the power supply assembly and carries
the following circuits:
regulated voltage supplies and associated over-voltage detectors
(except Vcc supply)
reference voltage generator
current limit for +30V supply
battery charging circuit with battery fuse crowbar
general current limit crowbar driver
au~iliary

on/off sensor

auxiliary internal supplies:

+25V.

-7V

,L10ck diagram on
These circuits are described in thti
the next page may be referred to d H ' did in understaMln9 the i;'li:errelation

of the c i rcu its.
The +30V unregulated supplY. is derived directly from the +35 vdc internal
preregulated supply through resistors (R62, R63) of the current limit circuit.
The current 1 Imt t detector Is a convent iona 1 c i reu j t; when the current taken
from the supply causes a voltage drop across the resistors equal or greater
than the turn-on voltage of the transistor (Q29), the transistor saturates
and applies the +35V bus to the over-current bus at terminal 11, through
resistor R67.

5-446

89633300 F

POWER SUPPLY UNIT (conti d.)
LOW POWER CIRCUIT ASSEMBLY (drawing number 89640800, cont'd.)
The -12V regulated supply is derived from a half-wave rectifier on the 35 vac
winding of transformer TI.
It is regulated by a conventional series regulator
circuit working between this voltage and the +35V bus.
The two inputs of the
regulator differential amplifier are remote ground (~SENSE) and the general
voltage reference (VREF) from the reference generator.
The output voltage of
the regulator can be adjusted by means of potentiometer Rv4 in the reference
voltage divider chain.
The potentiometer is accessible through the top cover
of the power supply unit (refer to Figure 6-4).
The supply is connected to the
over-voltage detector through transistor Q23 (see below); its current is
limited by resistor R58 in the emitter circuit of the series regulating transistor
(Q28).

The -5V regulated supply is derived from the full wave rectifier (diodes CRI2,
CRI3) on the 7 vac winding of transformer TI.
It is regulated by a conventional
series regulator circuit working between this voltage and the +35V bus.
The
two inputs of the regulator differential amplifier are remote ground (-SENSE)
and the general voltage reference (VREF) from the reference generator.
The
output voltage of the regulator can be adjusted by means of potentiometer RV5
in the reference voltage divider chain.
The potentiometer is accessible
through the top cover of the power supply unit (refer to Figur~ 6-4).
The
supply is connected to the overvoltage detector through transistor Q22 (see below).
The current in this supply is limited through the general overcurrent bus; the
conventional detector (R28, Q19) saturates transistor Q29 when the supply
current exceeds a preset value; Q29 in its turn applies the +35V bus to
the overcurrent bus (terminal 11), through resistor R67.
Note that Q29
and the Q16, Ql7 pair are common to this circuit and the +30V supply.

89633300 F

5-447

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Power Supply Regulator and Control Circuits:

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Block Diagram

POWER SUPPLY UN!T(contld.)
LOW POWER CIRCUIT ASSEMBLY (drawing 89640800, contld.)
The VBB regulated supply

is derived from the +3SV internal supply.

It is

regulated by a conventional series regulator using transistor Q30 as the
series element and the differential amplifier in the reference voltage generator
package (U3) as the comparator.

The two inputs of this comparator are the

general voltage reference (VREF) through R79 and the tap on the voltage divider
chain on the output.

The output voltage of the regulator can be adjusted by

means of potentiometer RV3 in the output voltage divider chain.

The

potentiometer is accessible through the top cover of the power supply unit
(refer to Figure 6-4).

Note that this adjustment affects the value of VSS

directly
see VSS supply below.
The supply is connected to the overvoltage
detector through diode CR34; its current is limited by the conventional circuit
of Q3l, R77, which cuts off the series regulator on occurrence of overcurrent.
The regulator output voltage (and therefore VSS ) can be changed by loading the
output voltage divider chain and through it one of the comparator inputs through
the VBB MARGIN terminal (refer to Section 6 for Margin Tests).

The VSS regulated supply is derived from the +3SV internal supply, and is
regulated by a switching regulator (see Section 4 for the principles
of operation of switching regulators).

I

The switching element in this circuit is

transistor Q44 with Q9 as predriver and QS, Q33 as parallel drivers.

The main

output filter capacitors are located on the filter board in the power supply
assembly. See the relevant power supply wiring diagram.
The regulator is driven at about 22 KHz by emitter-coupled oscillator Qll, Ql3.
The duty-cycle of this oscillator (and therefore the proportional regulation of
the circuit) is determined by the ratio of emitter currents of the two transistors.
This in turn is controlled by the differential ampl ifier QlO, Ql2 sharing the
current source Q39, Q40.

One input of the differential amplifier is the VSS

reference voltage derived from the VBB supply through driver transistor Q34.
To avoid sudden changes in the inductor current (and therefore large voltage spikes
on the inductor) a rise-time limiter integrator (RlOl, C47 and Q4S) is included
in the reference line of the regulator.
89633300 F

5-449

POWER SUPPLY UNIT (conti d.)
LOW POWER CIRCUIT ASSEMBLY (drawing 89640800, cont'd.)
Overcurrent in this circuit is detected by the voltage developed on R98 acting
as the gating voltage on transistors Q14, Ql5 connected as a Silicon Controlled
Rectifier (SCR).

This is driven by the oscillator output and is therefore

reset on every cycle of·the switching inverter.

When an excess current flows

through the switching transistor, +35V is connected to the overcurrent bus
through transistor Q15.

This supply is connected to the overvoltage detector

and crowbar circuit through diode CR33.

The Vcc 2 regulated supply has a similar circuit to that of the VSS supply.
It receives its reference voltage through a reference voltage divider chain
and its output voltage can be adjusted by potentiometer RV2.

Access to

RV2 is obtained through the power supply assembly cover (refer to Figure 6-4).

The reference generator utilizes the reference portion of the voltage regulator
package U3 (see the circuit diagram below) to supply the reference voltage to
the regulated power supplies.
ground (-SENSE);

Its supply is referred to the remote enclosure

it is switched through from either the auxil iary supply or

battery by transistor Q32, under control of the dc POWER on/off switch on the
Programmer's Console.
The overvoltage detector and crowbar input circuit utilize the comparator
in the voltage regulator UI to turn on the transistors Q24, Q25 connected
in a Silicon-Controlled-Rectifier (SCR) configuration when an over-voltage
occurs on anyone of the regulated supplies (-12V, -5V, Vcc2 ' VSS ' VBB'V cc )'
The positive supplies are ORed to the inverting input through common base
level shifters Q22, Q23. The comparator thus changes state when the absolute
voltage on anyone of the suppl ies increases over the value preset by the
voltage divider on each supply. The inputs to the comparator are biased
from the reference source in Ul.
5-450

89633300 F

POWER SUPPLY UNlr (cont'd.)
LOW POWER CIRCUIT ASSEMBLY (drawing 89640800, cont'd.)
VOLTAGE REGULATOR

(~A723C)

CIRCUIT AND TERMINAL ASSIGNMENTS

NC I

14 NC
13 FREQUENCY COMPENSATION
12 V+
II Vc
10 Vout
9 Vz
8 NC

CURRENT LIMIT 2
CURRENT SENSE 3
INVERTING INPUT 4
NON -INVERTING INPUT 5
V...,

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VOLTAGE
REFERENCE
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V-

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CURRENT
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ERROR
AMPLIFIER

89633300 F

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CURRENT
SENSE
CURRENT
LIMITER

5-451

POWER SUPPLY UNIT (cont'd.)
LOW POWER CIRCUIT ASSEMBLY (drawing 89640800, cont'd.)
Thus when Ul turns on transistors Q24, Q25,they apply the switched battery or
auxiliary supply to the crowbar bus.
This signal turns on the battery
crowbar (SCR Q46) and actuates the crowbar circuit on the HP assembly
(drawing 89657700), which in turn blows the main supply fuse (Fl), and
toe battery fuse (F2).

I

The following text relies on HP assembly drawing 89657700 and on. the relevant
power supply wiring diagram.
The on/off dc POWER switch on the Programmer's Console controls the supply to
the crowbar input circuit (just as it controls the supply to the reference
generator).
When it is on, transistor Q32 switches on the battery or the
auxiliary supply through to the supply line of the crowbar circuit.

The auxiliary on/off sensor (U2) is a voltage regulator package connected as
The on/off dc POWER switch of the Programmer's Console
a Schmitt-trigger.
controls its output frequency which forms the input signal of the power fail
detector on the HP board.

Two auxiliary supplies are generated on the LP board.
The -7V supply (feeding
the -5V regulated ~upply) is generated by full-wave rectifier CRI2, CRl3 from
the 7 vac output winding of the main transformer Tl.

The +25V s·upply is generated by the rectifier bridge (CR2I, CR22, CR23, CR24)
from the separate auxiliary mains transformer T2. This supply feeds the auxiliary supply line while the main power circuit and isolating power transformer Tl do not reach their normal voltage. This may occur when the equipment
is first switched on, or when it recovers from power failure.

5-452

89633300 F

POWER SUPPLY UNIT (cont'd.)

I

LOW POWER CIRCUIT ASSEMBLY (drawing 89640800 cont'd.)

With the main power circuit supplying full voltage, the 35 vac winding on
the main transformer (T1) takes control of the auxiliary line through halfwave rectifier CR30.
The battery charging circuit charges the Memory Hold Battery (equipment
GD 611-A) from the +35V internal supply. When this supply is on, transistors Q20, Q21 form a current source which feeds the battery through current
amplifier Q43 (terminal 17).
The battery supplies power to the +35V bus and through it to the equipment
through isolating diode CR31 when the +35V supply fails (power fail condition: Low Power Data Retention (LPDR) mode of operation).

89633300 F

5-453

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89633300 F

SECTION 6
MAINTENANCE

MAINTENANCE

This section applies to the equipment listed in Section 1 of this manual.

TOOLS AND SPECIAL EQUIPMENT
The following is a 1 ist of maintenance tools for the equipment.
Part Number

•

Part Description

12210275

Tweezer Fine Point

12210314

Iron Soldering 15W Miniature

12210315

Tip Soldering Iron .046 In. Spade

12210433

Stripper Wire 20-20 Ga

12210437

Solder 60/40 24 Ga. (.022 In)

12210849

Tool Wire Removal 20-26 Gauge

12210436

Desoldering Tool

89688700

Board Extender

89980600

Board Extractor

Quant i ty

2

2

Oscilloscope (Tektronix 453 or Equivalent)
Voltmeter (20,000 ohm/V min)
Load Resistor 60 ohm, 5%, 10 watt
Isopropyl

89633300 F

2

Alcohol

6-1

The publications 1 isted below are appl icable to the equipment.

Publication Number
Mini Computer Site Preparation Manual

60437000

1784 Reference Manual

89633400

1784 1/0 Specification Manual

89673100

1700 Computer System Codes Manual

60163500

Teletypewriter C.E. Manual

60163700

System Maintenance Monitor (SMM 17)

60182000

Refer also to Preface of this Manual.

6-2

89633300

A

CALIBRATE POWER SUPPLY LEVELS
This calibration applies to both main and expansion enclosures.
Check/Condition
1.

Act i-on

System power on, system

1.

Open the enclosure rear cover.

not opera tiona 1 •

2.

Connect the vo 1 tmeter (mul t ime-ter)
to the test point (TP) for the
main logic supply (V);
cc
location of the test point is
shown in Figure 6-1.

Check the value of the V
cc
supply (see Table 6-1).
Correct?

,

a.

No

Yes

Adjust the V supply voltage
cc
by screwdriver control
located as shown in

Go to next step

Figure 6-4.
b.
3.

Repeat check.

Repeat 2 with the computer
running under test.

4.

Repeat 2 and 3 for the
following supplies: -12V,
-5V, +30V (see Table 6-1).

2.

System ac power switch OFF,
front panel de POWER switch ON,
memory hold battery installed.

89633300

A

5.

Repeat 2 above for the
following suppl ies:
V ,V ,V
(see Table 6-1).
cc2
SS
BB

6-3

TABLE 6-1

COMPUTER DC SUPPLIES

SupP.ly

Des i gnat ion

1.

Vcc
V
cC2

+ 5.0

35 A

+ 5.3

3A

R, M

VSS

+16.7

5 A

ABI07/BA201-B, R, M

VSS

+19.7

5 A

ABI08/BA201-A, R, M

4.

VBB

VSS + 3.5

40 rnA

5.

-12V

-12.0

100 rnA

R,

6.

- 5V

- 5.0

1A

R

7.

+30V

+30.0

300 rnA

unregulated, M

8.

battery charger

200 rnA

current regulated

2.
3.

Nomi na 1 voltage
vol ts

Nominal
Current

Remarks

R

R, M

Internal supplies
+35V

9.
10.

auxi 1 iary no. 1

11.

auxi 1 iary no. 2

NOTES:

1. R: regulated supply

~.

3.

4.

6-4

+35V

preregulated
unregulated

- 7

unregulated internal
supply

M: supply to the memory only

The tolerance on all regulated voltages is less than ~ 1/2%.
The maximum permissible ripple is 2 % of each regulated voltage.
All power supply levels are generated in the power supply unit
(terminal configuration shown in Figure 6-5).
All power supply levels are to be measured on the computer backplane
at the test points (TP) shown in Figure 6-1.
89633300

E

CHECK BATTERY (Optional power back-up source, equipment GD611-A)
Check/Condition

Act ion

System power off.

1.

1.

Make sure the battery is fully charged.
Note:

the battery is fully charged if it

is charged 32 hours.
fully

dis~harged

If the battery is not

a shorter period of charging

may be sufficient.
Disconnect the battery from its terminals in
the enclosure;

refer to Figure 3-7.

Connect

the voltmeter {multimeter} across the battery.
WARN ING
Do not short battery,

I

Check the battery
vol tage (~24.2V).
Correct?

No

----------~~

Yes

Change battery (refer to instructions
in Section 3).

+

Go to next step

2.

Connect two 60 ohm 5% 10 watt resistors
across the battery in parallel.
Connect the voltmeter (multimeter) across
the res i s tors.

Check the battery
voltage

(~·24.2V).

Correct?

No - - - - - -.....
~ Change battery (refer to instructions

t

in Section 3).

Yes
Reconnect battery
Go to next step.

3.

Switch off all power and close the
enclosure rear

89633300

F

cover.

6-5

P'I

IIIC

"

0-<3--00
.12

_

ConlOl.
GNO[I] • -SENSE

m

•

PWR

11t...1

c.....

••

-12V

VCC2

FAIL

Figure 6-1. Computer Backplane Showing the Power Supply Test Points

89633300 F

INSPECTION OR REPLACEMENT OF PRINTED WIRING BOARD
Should it be deemed necessary to remove or inspect any of the printed circuit
assemblies in the enclosure, proceed as follows:
NOTE
WARNING
Make sure that system
is not operational
before switching off
system power.
1.

System power off.
(Power off Procedure,
refer to page 6-27).

Do not remove any circuits with
the enclosure power on.

1.

Open enclosure front door.
NOTE
When removing a printed wiring assembly note
its slot number carefully for future reference.

2.

In a system including
the expansion enclosure
its power must be
switched off before the
main enclosure.

2.

Remove the suspected printed wiring assembly
from its place in the enclosure using the
card extractor tool (part 89670300) as
illustrated in Figure 6-2.
WARNING
Memory Module assemblies
(equipments BA201-A, BA20l-B)
require special handling:
refer to Section 7, Protection
Against Catastrophic Damage.

89633300 A

3.

Replace a suspected PWA into its slot only
if it is not faulty.
Otherwise substitute
a fully tested similar PWA.

4.

Close front door of enclosure.

6-7

EXTRACTOR

PULL TO
REMOVE I'WA

>

BOARD EXTENDER

~WA

UINIEII TEST

BOAIID EXTRACTOR

Figure 6-2.

6-8

Use of Board Extractor and Board Extender
8~633300

F

INSPECTION OR REPLACEMENT OF THE POWER SUPPLY UNIT
Should it be deemed necessary to remove or inspect the power supply unit in the
enclosure, proceed as follows:
NOTE
The power supply unit should not be repaired in the field.
In case of a fault ·the unit should be replaced as a whole.
1.

System power off.

1.

Open the enclosure front door.

(Power off procedure,
refer to page 6-27).
2.

In a system including
the expansion enclosure,
its power must be switched
off before the power of the
main enclosure.

WARNING

The power supply -does not use an input isolating transformer and
parts of its circuits are at line voltage during operation. Do
not touch the power supply unit while the line cord is plugged in.
2.

Remove the power supply heat shield by removing
its retaining screws on the inside of the
enclosure front door (refer, to Figure 6-3).

3.

Remove all connections from power supply
connector panel (refer to Figure 6-4).

4.

Remove the power supply unit by removing its
retaining screws (refer to Figure 6-5).

5.

Reconnect the power supply after repair and
testing or reconnect another one by reversing
the procedures under 3 and 4 above.

6.

Recal ibrate the power supply voltages as
described earl ier in this section.

7.

Replace the power supply heat shield by
reversing procedure in 2 above).

8.
89633300 A

Close enclosure front door.

6-9

I

r--

r--

0

•

f)

e

•
SUPPLY

FiGur-e

6-10

•

•

HEAT

6-3.

Power Supplv Heat Shield and Retaining Screws

89633300 F

(

.... .

)

~il' if

f3
SA

0

F4 @
100mA

0
0

Figure 6~4. Power Supply Adjustments and Fuses

GIlD

o

•

•
/

/

•

POWER SUPPLY
RETAINING SCREWS

figure

89633300 F

6-S.

Power Supply Terminals and Retaining Screws

6-11

CHECK PROGRAMMER'S CONSOLE CONTROLS AND INDICATORS

NOTE
Section 2 describes the controls and indicators
of the Prog'rammer' s Conso Ie.
These tes ts relate
only to the main computer enclosure after its
proper installation.
Check/Condition

Act ion

1.

1.

System power on

Check that alII ights corresponding to register positions
(except the Breakpoint register) on the front panel are
extinguished.
Yes
No ---------.~

I~----------------------~~

2.

Press MASTER CLEAR switch

a.

Take appropriate action

b. Repeat check
Press the M register selector
and the data enter pushbutton
switches (0 through 15)

Check that all indicators
corresponding to the
switches pressed 1 ight
Yes

No~--------~~~

~-----------------------t.~

3.

(1)

a.
b.

Take appropriate action
Repeat check

Pres s CLEAR but ton

Check that all data enter
indicators are extinguished
Yes

N o - - - - - - - - - -... a.
b.

Take appropriate action(2)
Repeat check

Go to next step
Note,s: re fe r to next page.
6-12

89633300 F

4. Repeat 2, 3 for registers
P, Y, X, A, Q, B

5. Actuate each of the following
switches in turn:
AUTOLOAD, MANUAL INTRPT.,
STOP, MASTER CLEAR, GO
All pushbutton switches
Check if the switches operate
correctly (refer to Section 2
and the SMM manual).
Yes

~

No ------------------~~~

a.

Take appropriate action(3)

b.

Repeat check

Go to next step

2.

Controls and Indicators
checked.

Notes:
1.

The CLEAR and MASTER CLEAR functions are defined in the Computer
System Reference Manual (publ ication number 89633400). The
signals may be traced with the aid of the Programmer's Console
basic diagram (refer to Section 5) and the back-plane wire list
(refer to Section 9).

2.

To replace an indicator lamp, carry out the appropriate procedure
outlined in the following pages.

3.

To replace a pushbutton switch, carry out the appropriate
procedure outlined in the following pages.

89633300 F

6-13

E.tECTOR PIN MARICS
(4 PLACES)

f
REMOVE MY
PRO.IECTIOH
"ROM MOUNTINe
a.SE

Bottom View of Programmer's Console Pushbutton Switch Part No. 89652300
(See also CDC Specification 89652300)

6-14

89633300 F

INSPECTION OR REPLACEMENT OF PROGRAMMER'S CONSOLE
Should it be deemed necessary
to inspect or remove the Programmer's Console printed wiring assembly;
to inspect or replace a pushbutton switch or indicator lamp,
proceed as follows:
NOTE
Make sure that system is not operational before switching off system power.
1.

Switch off system
power according to
Power Off procedure
below.

1.

Open the enclosure front door.

2.

Remove the power supply heat shield by
removing its retaining screws on the inside
of the computer enclosure front door (refer
to Figure 6-3).

3.

Remove two screws holding cover of front
panel from the rear of the front door
(refer to Figure 6-6a) •

4.

Remove two small front covers (carrying names
of switches and indicators) from the front
of the door.

5.

Remove three screws from each of the two
edges of the front panel as shown on
Figure 6-6b.

WARNING
Do not remove the other
four screws on the
{hinge side} edge of the
fro'nt door, as these
secure the door to the
enclosure.

89633300 A

.6-15

SYSTEM 17 PROGRAMMERS CONSOLE
PUSH BUTTON SWITCH INSTALLATION
1•

SCOPE
These instructions detail requirements for install ing push button
switch PIN 89652300, used on System 17 Programmer's Console
PIN 89640300.

2.

APPLICABLE DOCUMENTS
CDC SPEC 89652300 - Push Button Switch, SPST.

3.

REQUIREMENTS

4.

Premounting Preparations

5.

Switch Preparation - Switch mounting base shall be free from burrs,
as outlined in Figure 1, and other undesireable projections.

Note,

the Rohdium alloy contacts project 0.0035 inches below the mounting
base.

A smooth, projection free, mounting base is imperative for

proper switch operation.

6.

Printed Wiring Board Preparation - Cleaning
The switch is sensitive to cleaning solvents.

Safe cleaning solvents

to use are trichlorethylene, methyl denatured alcohol or isopropyl
alcohol.

PWB's shall be cleaned and dryed before mounting the switch

and not afterwards.
WARNING
Do not use Freon TMC.

It will eat away at

the plastic material.

Freon TF will distort

the silcone rubber tube.

6-15A

89633300 D

7.

Mounting Requirements

8.

Switch Placement - Switches shall be seated flat on board and held
firmly in place with a mechanical jig or other method while screws
are tightened.

9.

Mounting Torque - Switches shall be mounted with a driving torque
of 1 lb.-inch. Any higher may strip the plastic threading and cause
the swithc to loosen.
tr)

Ic

a ....

!::
CLg

g:j
OCL

t; •
.,........

...

:c

u

I-

3:
V)

LL.

e

3:
L&J

>

::E:

~
le

co

89633300 0

6-15B

2.

To replace a pushbutton
switch perform steps 6f9.

6.

Locate and remove the faulty pushbutton
switch: unscrew the two screws that
hold it to the assembly and lift it off.
(Do not lose the screws!).

7.

Prepare the assembly and replacement
switch as follows:

(Pushbutton switch:
CDC PIN 89652300)

a.

Switch preparation
Switch mounting base shall be free
from burrs and other undersireable
projections. Note, the rhodium
alloy contacts project 0.0035 inches
below the mounting base. A smooth,
projection free, mounting base is
imperative for proper switch
operation.

b.

Printed Wiring Board Preparation Cleaning
The switch is sensitive to cleaning
solvents. Safe cleaning solvents to
use are methyl denatured alcohol or
isopropyl alcohol. PWB' s shall be
cleaned and dried before mounting
the swi tch and not afterwards. .
WARNING
Do not use Freon TMC. It will eat
away at the plastic material.
Freon TF will distort the silicone
rubber tube.

8.

6-16

Mount the replacement switch on the PWB
with the aid of the two screws from step 6.
Observe the following mounting requirements:
a.

Switch Placement - Switches shall be
seated flat on board and held firmly
in place with a mechanical jig or
other method while screws are tightened.

b.

Mounting Torque - Switches shall be
mounted with a driving torque of 1 lb.inch. Any higher may strip the plastic
threading and cause the switch to loosen.
89633300

A

9.

To replace an indicator
lamp on the Programmer's
Console assembly. perform
steps 10f13.

10.

(Indicator lamp:

A

Locate and remove the faulty indicator
lamp: unsolder the two legs of the
lamp and remove it. To remove unwanted
solder use suitable copper braid.
WARNING
Do not use suction to remove
unwanted solder, suction may
lift off printed conductors
from the board.

CDC PIN 8963700)

89633300

Check the pushbutton switch (refer
to previous sUbsection).

11.

Clean the printed wiring board with
methyl denatured alcohol or isopropyl
a 1coho 1.

12.

Mount the replacement indicator lamp
by inserting its two legs in the
freed holes until the lamp is seated
flat against the board. Carefully
solder the two legs to the printed
wiring pads. Remove unwanted solder
and clean the area using the materials
of step 11.

13.

Check the Indicator lamp (refer to
previous subsection).

6-17

4.

To replace the

14.

Programmer's Console

Proceed in removing the whole' Programmer's
Console by the following procedure:

assembly
follow steps 14 through 16.

I

NOTE:
Steps noted by asterisks
apply to series A12 and down.
For other series, see the
notes at the bottom of this
page.

- * unsolder

the. power supply connection at
bottom right hand corner of the assembly

(looked at from the inside of the front
door of the enclosure: refer to Figure 6-6a)

- * open

rear cover of enclosure, remove the
connector of the assembly (refer to
Figure 6-1) and slide the cable and
connector through under the card nest
to the front of the enclosure
remove the printed wiring assembly by
removing 10 screws around its periphery.

15.

To reconnect the printed wiring assembly after
repair or with another, good one, reverse
the order of procedures I through 5 and 8.

16.

Check all Programmer's Console indicators
and switches according to the instructions
(refer to previous subsection).

I * This

step in the procedure appl ies only to series A12 and down.
For series A13 and up, including models C and D, this instruction reads:
- remove the power supply connector at bottom right hand corner of assembly {looked at from the inside of the front door of the enclosure}.
Refer to figure 6-6a.

~

This step applies only to series A12 and down. For series A13 and up, including models C and D, this instruction reads as follows:
- disconnect the two connectors on the programmer's console card which
attach the main harness. They are marked J20 and J21 on the enclosure.

6-18

89633300 F

&
0'

BLOWER WIRE SOLDERED

JOINTS

W
W
W

o
o

."

vee

BLOWER

RETAINING SCREWS
OF DISPLAY PANELS
0'
I

\.0

Figure 6-6a. Inside of Computer Enclosure Front Door

Note: This view does not apply to all
series. See the note on page 3-7.

REMOVE THESE SCR.WS

o

••

Figure 6-6b.
6-20

Inside of Computer Enclosure Front Door.
89633300 A

LOWER FAN BASE WITH FOUR RETAINING
SCREWS
(TYPE IDENTIFIERS C AND D ONLY)

Figure 6-7. Blower Assembly in
Top of Enclosure
(All Type Identifiers)

89633300 F

6-21

INSPECTION OR REPLACEMENT OF COOLING BLOWERS

I

Each enclosure of type C or D is cooled by stx centrifugal blowers'. Three
blowers are housed in the top of the enclosure (figure 6-7), two in the bottom of the enclosure(not installed in type A, see figure 6-7), and one blower is in the front door of the enclosure. (figure 6-6al. The blower in the
front door cools the power supply unit mounted above it. The blowers in the
enclosure (three on top and. two on bottom) supply cool ing air to the printed wiring assemblies in the main body of the enclosure.
Should it be deemed necessary to inspect or remove one or more of the blowers,
follow the appropriate procedure outlined below.
WARNING
The computer must not be operated or switched on with
the blowers outside the enclosure, or otherwise not
operational.
Note that free access of air around the enclosure must
be ma i ntai ned.

Inspection of the b10wer in the front door
Provided proper care is
exercised system power
need not be switched
off.

1.

Open the enclosure front door.

2.

Inspect the blower visually.

To check the
airflow a sheet of paper may be placed
momentarily on the air inlet: with proper
airflow the paperwi11 be sucked close to the
body of the blower.

3.

If the blower does not function switch off
the power to the enclosure immediately (refer
to Power Off Procedure), check wiring continuity
according to appropriate wiring diagram (see
Section 5) and if necessary, remove the blower.
Otherwise close the enclosure front door and

6-22

proceed with normal operation or further
checks.
89633300 F

Inspection of blowers in the enclosure
To inspect the three blowers in the top of the enclosure and the two blowers
in the bottom, they have to be slid out from the body of the enclosure.
1. Make sure that the system is not operational
and switch off the system power according to
Power Off Procedure.
CAUTION
In- step 2, do not let the
blower box that is mounted
in the bottom of the en'closure fall freely after
i ts fou r moun t i ng screws
have beeh removed. Support
it by hand or some other
way, to prevent strain and
possible damage to the two
connectors.

89633300 F

2.

Undo the screws holding the blower box (two
screws on either side of the enclosure:
refer to Figure 6-7). See Caution.

3.

Open the enclosure front door.

4.

Slide out the blower box carefully and inspect
the blowers and the wiring.
To check the
airflow of the blowers, prepare a sheet of
paper, switch on the power to the enclosure
for a very short time and place the sheet of
paper across the inlet of each blower momentarily; with proper airflow the paper will
be sucked close to the body of the blower.

5.

If one of the blowers does not function, check
wiring continuity according to appropriate
wiring diagram (refer to Section 5) and if
necessary, remove the blower according to
outline procedure below.
Otherwise slide
back blower box carefully, replace the four
screws holding it, close the enclosure front
door and proceed with normal operation or
further checks.

6-23

Removal and replacement of a blower
NOTE
Make sure that the
system is not operational
before switching off
sys tern power.

Before removing a blower inspect it (see two
previous subsections) and make sure that its
removal is necessary.
1.

Undo electrical connection of the blower:
a.

the wire of the blower in the front door
is part of the cable form of the door;
to remove the blower connection cut the
la~ing of this cable, cut the heatshrinkable tubing over the blower
connection and cut the wires (Figure 6~6a);

b.

the blowers in the top part of the
enclosure are wired through a terminal
block (refer to Figure 6-7); to
disconnect a blower its wire has to
be removed from this terminal block.

I ADDENDUM:
c. the blowers in the bottom
part of the enclosure are
wired to individual connectors (figure 6-8). To disconnect a blower, pullout its
plug.
2.

Remove the blower bodily by undoing the three
screws holding it (refer to Figures 6-6a, 6-7).
WARNING
Do not operate or switch
on the computer without
one of the blowers.

3.

Ensure that replacement blower is in
good working order.
Install it by reversing
the procedure of paragraphs 2 and 1 above.
After installation inspect the blowers and
close the enclosure (refer to previous
subsections).

6-24

89633300 F

____ tL ___ n. __

... ,,1

l~JI

I

(V'"

\; "I
---1J-TV--

I

REFERENCE:
MAl N HARNESS
:

89633300 F /

Figure 6-8. Exposed View
of Two Lower Fans and Electrical Connections

6-25

WARN
TURN M

-

,

POWER ON:

PROCEDURE FOR SWITCHING ON POWER

To apply power to the computer (equipment AB107lAB108) and the Expansion
Enclosure (equipment BT148), proceed as ,follows:.
NOTE
It is assumed that the equipment has been installed
and is operational.
For Power On Procedure on first
installation refer to Section 3 of this manual.
1.

Make sure all the power switches of the computer are off.
are listed in the following table:
Equipment

Switch
Designation

The switches

Location

AB107lAB108

AC POWER
DC POWER

Rear Panel
Front Panel

BTl 48

AC POWER
DC POWER

Rear Panel
Front Panel
(

\

2.

Make sure that the power cord of each enclosure is connected to a
ut i1 i ty outlet.

3.

Switch on the power to the utility outlets.

4.

Turn on the equipment switches in the following order.
On turning on the DC POWER, the associated indicator should light.

(

(

"
Step
1.

2.

3.
4.

6-26

Equipment
AB I 07lAB 108
AB107/AB108
BTl48
BTl48

Swi tch
Designation
AC
DC
AC
DC

POWER
POWER
POWER
POWER

Location
Rear
Front
Rear
Front

Panel
Panel
Panel
Panel
89633300 F

(

POWER OFF:

PROCEDURE FOR SWITCHING OFF POWER

To remove the power from the computer (equipment AB107/AB108) and associated
Expansion Enclosure (equipment BT148) proceed according to the following
instructions:
EMERGENCY SHUT-DOWN
In case of emergency (suspected burning in the computer
and associated equipment) perform anyone or all of the
following steps (the steps are given in order of preference):
Step
1.

2.

3.

REGULAR

Action
Switch off circuit breaker of
i ns ta 11 at ion
Switch off AC POWER swi tch on
each equipment
Pull power cord(s) from
.utilityoutlet

Locat ion
Depends on
installation
ABI07

AB108
BTl48

J

rear
panel

Util ity
outlet{s)

S~UT-DOWN

To shut down the computer proceed as follows:
I.
2.

Make sure that the system is not being operated.
Turn off the equipment switches in the following order:

Step

Equipment

Switch
Designation

1.

BTI48

DC POWER

Front Panel

2.

BTI48

AC POWER

Rear

3.

AB 107/ABI 08

DC POWER

Front Panel

4.

ABI07/ABI08

AC POWER

Rear

89633300 F

Location

Panel

Panel

6-27

DIAGNOSTICS AND MARGIN TESTS
TEST PROGRAMS
SMM17 Memory, Command and Random Protect Tests.
TEST CONDITIONS

(See a 1.50 tab 1e6-·1)

CONDITION

VCC

VSS

NOMINAL DC VOLTAGES

1

+5%

+5%

VCC:

2

-5%

+5%

3

-5%

-5%

4

+5%

-5%

VCC2: +5.3 VDC
VSS: tl~.7 VDC ~AB107~
VSS: +19.7 vee AB108
VBB: VSS + 3.5 VDC
-12.0 VDC
-12
- 5.0 VDC
- 5

+5.0 VDC

I

Operational Tests
At nominal voltages, run several passes of each SMM test. No
errors On any test are allowed.
Run several passes of each test at each of the 4 conditions listed above.
Return the supply to its nominal values, and re-run the tests. Shock
testing is not recommended, but very light tapping should not produce
errors.

6"'28

89633300 F

SECTION 7
~INTENANCE

AIDS

I

\

I

\,

i

\

\

MAINTENANCE AIDS
TTL CIRCUIT OPERATION
The transistor-transistor logic (TTL) is analogous to diode-transistor logic (DTL)
in certain respects.
As shown in Figure 7-1 a low voltage at inputs A or B
will allow current to flow through the diode associated with the low input, and
no drive current will pass through diode D)"
If inputs A and B are raised to
high voltage, drive current will pass through d·iode D3 •
In TTL circuitry the multiple-emitter transistor performs the same function as
the diodes in DTL (see Figure 7-2).
However the transistor action of the
multiple-emitter transistor causes transistor Ql to turn-off more rapidly thus
providing an inherent switching-time advantage over the DTL circuit.
Although one-volt dc noise margins are typical for TTL circuits, an absolute
guarantee of 400 millivolts is given for every unit by manufacturers.
Each output is tested to ensure that the logic high output voltage will not fall
below 2.4 volts.
This is done with full fan-out, lowest Vcc and 0.8 volt on the
input: 400 mV more than the logical low maximum.
Each output is tested to ensure that the logic low output voltage will not exceed
0.4 volt.
This is done with full fan-out, lowest Vcc and 2 volts on the input:
400 mV less than the logic high minimum.
In actual ~ystem operation, the majority of circuits do not experience worst-case
conditions of fan-out, supply voltage, temperature, and input voltage
simultaneously.
In addition the threshold voltage of the TTL circuits is about
1.5 volts.
These characteristics allow a larger voltage change on an input
without false triggering.
This typical noise margin is shown in Figure 7-3.
Another important feature of the design is the output configuration which both
supplies current. (In the logical high state) and sinks current (in the logical
low state) from a low impedance.
Typically logical low output impedance is
12 ohm and logical high output impedance is 70 ohm.
This low output impedance
in either state rejects capacitively coupled pulses and ensures small R-C time
constants which preserve wave-shape integrity.
89633300 A

7-1

Vc;e

Vee

03

01

Output

Input A

02
Input

Input A

8

Input 80--eround

Figure 7-1.

Diode AND Gate.

DC Level
(volta)

Figure 7-2.

2,8
Vce
4,75 V

2,0

LOllo High
..., .. Marlin

I

I

Lagle Low

Logic LO~

1- ~
No'" Mar, In 1

0,4

I

o

7-2

Lo,le High

•

V

1,2

Figure 7-3.

~

TTL AND Gate.

20

I

40

i

60

TlmfNraturl

(OC)

Typical Logic Level Margins for TTL Micrologic
89633300 A

HOS CIRCUIT OPERATION

THE HOS PROCESS AND SILICON GATE TECHNOLOGY
The memory unit is realized with silicon gate metal-oxide-silicon (HOS)
technology.
This technology offers a number of advantages over aluminum
gate HOS technology; some of these are listed:

a.

Gate oxide is protected immediately on formation in the silicon gate
process.

b.

The self-aligned gate of the silicon gate device permits the construction
of a smaller device with less gate-to-drain capacitance than is possib.le
with aluminum technology.
Faster, more compact circuits are made possible.

c.

The silicon layer can be used for interconnections, permitting reduced chip
area per function.
This is an Important factor in large scale Integrated
(LSI) circuits where interconnection area affects cost even more than
active component area.

d.

Improved reliability of the 'silicon gate devices due to the number of layers
above the gate.

e.

Lower threshold voltage due to the use of silicon rather than aluminum as
the gate material.

89633300

A

7-3

Static and Dynamic HOS Circuits

The characteristics of the HOS field-effect-transistor (HOSFET) permit the
construction of a wide variety of logic circuits with a large device and
function density while giving good reliability and yield.
An example of
the application of these circuits is ·the memory unit of the computer, a
1024-bit random access, fully decoded read-write memory unit, accommodated
on a single semiconductor chip.
In general the HOS device may be used as an active amplifier or as a load
resistor.
Typical characteristics of a MOSFET device are shown in
Figure 7-4, together with a curve corresponding to it used as a load resistor
with a 12 volt supply.
The curves show drain current (10) versus drain-tosource voltage (VDS) with gate-to-source bias voltage (V GS ) as a parameter.
The load resistor curve
The substrate is assumed to be at source potential.
is approximate as substrate bias effects have been neglected.
In the following
discussion on the various circuits high and low refer to the relative magnitude
of the voltage with respect to the substrate voltage level (VSS).
Polarities
are taken as correct for a p - channel device, i.e., all voltages negative with
respect to the substrate.
Note that the supply voltage for MOS devices is
typically -15 to -18 volts; the logic high and low signals to the memory unit
are typically as follows:·
min.

7-4

max.

input low voltage

VSS - 17

VSS - 14.5

input high voltage

VSS - 0.7

VSS + 1

89633300 A

Four types of HOSFET inverter stages are shown in Figure 7-5.
In Figure 7-5a
two HOS devices (Ql, Q2) are wired as a static inverter.
When input is
sufficiently high, Q2 turns on and the output is low.
If the input is low it
causes Q2 to be off and Ql pulls the output high.
This circuit requires that
for equivalent bias, Q2 should have much higher conductance than Ql to get
reasonable noise margins; the two devices have therefore radically different
geometries.
This is shown in Figure 7-5a by representing Ql as a resistor and
Q2 as a FET.
As a result of the low conductance of Ql, current available from
it to charge load capacitances is quite limited in this inverter and low-to-high
transitions are rather slow.
The circuit of Figure 7-5b is similar to that in Figure 7-5a when the clock is
active.
By making the clock voltage higher than V, a more consistent high
output level is established.
Once the output level is established, the clock
may be switched off to save power.
This technique is used in the low power
data retention mode of operation (LPDR) to conserve battery and may be used
also to give improved noise margins.
The circuit of Figure 7-5c behaves as an inverter when the clock is active (high).
This circuit may be used to drive relatively large capacitive loads through the
high conductance of Ql, though it may consume relatively large amount of power
while both the input and the clock are active (high).
In the circuit of Figure 7-5d the capacitive load is charged when the clock
input C is high and is discharged when C goes low, provided that the input is
high.
This circuit draws current only to charge and discharge the load and
The load capacitance is, however, reflected back
there is no dc drain.
into the clock driver.
The circuits of· Figures 7-5b, c, d make use of temporary retention of data on
the load capacitance and are therefore said to be dynamic, while that of
Figure 7-5a is dc-stable and therefore static.

89633300 A

7-5

Load

Retiator Curve

- 4,0
Yes =-IOV
Ves·- 8V

- 2.0

Yes =-6 V

,,
-e

Figure 7-4.

Yes = -4V
Yes =-2 V

-10

-Ie

Typical MOS Characteristic

V

V

V

VDS

-20

V

C
()-f

Output

Output

Output

Output
I

o-t

a.

Static

-

b. Gated

Static

Figure 7-5.

7-6

..L

o--i
Input

Input

Input

c.

I

"'T"
I

-

~

"'T"
I

Input

-!-

~

Dynamic

d.

Dynamic

I

Low Powlr

MOS Inverter Circuits

89633300

A

v

Q3
.....- 0 Output

Q4

Input

Fi gure 7-6.

MOS Inverter with Output Booster

C

0

•

1

r-r

*
I

-=

Figure 7-7.
89633300

A

•
I
I

I
I

Cs

-''1'
I

CL

-!-

MOS Transmission Gate

7-7

Larger capacitive loads may be driven by stati.c inverters only if a booster
stage is added.
A loss of high level is introduced unless bootstrap techniques
are used.
A booster stage is shown in Figure 7-6.
A transmission gate is shown in Figure 7-7.

The load capacitance CL is charged
When
towards the voltage on the input capacitor Cs when the clock C is high.
the clock input is returned low it switches off Ql and CL retains the voltage
it was charged to.

The circuit of Figure 7-7 may be driven from a number of different source
circuits.
When the source is dynamic the transmission gate clock C should
be kept high during the entire period when Cs and CL are being charged and
discharged,otherwise improper voltages may result.
For example if Cs is
initially charged and CL initially discharged,they will share their charge
when the transmission gate is opened by the clock being made active.
The
voltage on the capacitors will thus be a function of the relative values of
the two capacitors.
Unless the circuit is designed to operate with such
intermediate voltage levels incorrect operation will result.
Such circuits make up the memory unit (Section 4) which work together with
auxiliary and control circuits in the memory module, memory address and
memory control circuits.

!

\~

7-8

89633300 A

PRECAUTIONS IN HANDLING THE MEMORY MODULES
The
The
and
and

memory banks are arrays of memory units mounted on the Memory Modules.
memory units are MOSFET circuits characterized by very high impedances
some special precautions should be observed while handling them both in
out of circuit.

PROTECTION AGAINST CATASTROPHIC DAMAGE
As with any semiconductor component, the memory units can be damaged by misuse,
or misapplied voltages.
The component should be protected from such misuse
during shipment, handling, and when installed in the system.
MOS circuits are characterized by high impedances, and therefore are capable
of being charged to high voltages by static charges.
The gate circuits of
MOS transistors are subject to destructive breakdown if excessively charged.
The memory unit has an effective gate protection circuit for all input
connections, and requires no elaborate precautions in normal use.
However,
some environments are subject to extreme build up of static charge, and are
capable of releasing sufficient amounts of energy to damage any semiconductor
MOS components in particular should be protected from these static
component.
charges.
Some precautions which are easy to implement and yet which are quite
effective are:

89633300 A

a.

Carry components and memory unit cards in conductive
trays, such as metal or foil-lined pans.

b.

Personnel must touch ground, the chassis or the carrier
tray before picking up components and memory unit cards.
Avoid high static materials and fabrics in work areas.

7-9

SECTION 8
PARTS LIST

PARTS DATA (sheet 1 of 3)
The parts listed below provide the identification and ordering data for the
"field-replaceable" electri·cal and hardware parts.
PAR T

OESIGNATION/ASSEMBLY

N U MB E R

NOTES

AB 107-A/C/D AB108-A/C/D BT148-A/C/D BUI20-A
ALU
Ti mi ng
Decoder
I/O Interface
TTY Con t ro 11 e r
Console Interface
Memory Address
Memory Control
Programmer I s Console
Console Cable Assembly
Power Supply Unit
Fuse, 5A, fast blow
Fuse, 100mA,slow-blow
Fuse, 8A, slow-blow
Fuse, lA, slow-blow
Blower (in door)
Blower (in enclosure)
Lamp, indicator bulb
Switch, pushbutton
Switch, pushbutton
Connector, plug
Contact, socket
Connector
Contact, socket
Swi tch, DPDT (AC input)

J9997700
92371016
93419306
92383005
93419222
89637100
89840300
89637000

89614100
89778201
89934400
89791300
89967400
89600043
89615000
89949000
89602069
89893800
89997700
92371016
93419306
92383005
93419222
89637100
89840300
89637000

89652300
89690200

89652300
89690200

53397915
53397918
93947009
51788834
97030200

53397915
53397918
93947009
51788834
97030200

89614100
89778200
89934400
89791300
89967400
89600043
89615000
89949000
89602069

I

~9893800

I
(1)
(1)

(6)
89615000
89949000

89997700
92371016
93419306
92383005
93419222
89637100
89840300

,.

(234)
(2,5)
(7)

I

I
(3)
(4)
(5)
(5)
(2)
(2)

97030200

See sheet 2 for continuation and notes.

89633300 F

I

8-1

P'A R T S OAT A (sheet 2 of 3)
DESIGNATION/ASSEMBLY

I

PAR T
AB 107';'A/C /0

NUMBER
ABI08-A/C/D BT148-A/C/D BU120-A

Lamp,mini,6V(power on)
Switch,toggle,2 posit. 89640901
7201/J2-CB
Switch,toggle,3 posit. 89640904
7203/J2-CB
Lens,power on lamp,
red
Lens, 1amp ,wh i te
89633100

NOTES

89818700
89640901

89640901

89640904
89780201
89633100

------------~---------- -

DESIGNATION/ASSEMBLY
Equipment BA201-A (Memory 600 nsec)
Equipment BA201-B (Memory 900 nsec)
Equipment GD611-A (Memory Hold Battery)

PART NUMBER

- - - --

89876300
89876600
89650100

NOTES:
(1) The Timing pWA(897782~0 or 89778201) and the I/O Interface PWA(89791300)
must both be used at the same time. Do not replace one without replacing
the other.
(2)Programmer ' s Console PWA (89640300 and 89987600) includes an integral
cable assembly and is used on A04-A12 series. Programmer1s Console PWA
(89881800 and 89987700) does not include cable assenb1y (89893800) and
is used on A13 and higher series. Console PWA (89881800 and 89987700 and
89985400) may be installed in A04-A12 series provided cable assembly
(89893800) is installed at the same time along with using connector
(93947009) and (4) socket contacts (51788834) on the power supply wire
harness assembly (P22).
(3).Pushbutton switch (89652300) is used on A04-A12 series with Console PWA

I

89640300.
(4) Pushbutton switch (89690200) is used on A13 and higher series with
Console PWA. It uses switchcap PIN 89764900.

the

(5) Plug connector (53397915) and contact sockets (53397918) are parts of
Console Cable Assembly (89893800).
See sheet 3 for the continuation of the notes.
- .. ",.

8-2

89633300 F

PAR T S 0 A T A
(sheet 3 of 3)
NOTES (continued)

(6) TTY Controller PWA part number 89967400 is one of four valid TTY Controller part numbers in the field. See page 5-373 for the details.

(7) Four power supply wiring diagrams are provided In section 5 to cover
Power Supply Unit part number 89997700 and the other valid units in
the field.

i.

89633300

F

8-3/ 8-4

,

;1

SECTION 9

WIRE LISTS

\.

\

\

\

/

\.

(

\.

WIRE LISTS
Table 9-la gives the wire list for the TTY Internal Cable.
Table 9-lb gives the wire list for the TTY External Shielded Cable.
Tables 9-2 and 9-3 are the wire lists for the Memory Expansion Cables, which
form part of equipment BU120-A.

Refer to Figure 3-4 for placement details

of these cables.
Table 9-4(a} and 9-4(b} give the backplane wiring of the AB107/AB108 in,
respectively, signal name order and card slot order. These tables
incorporate the wiring for the CPU, Memory System, A/Q and DSA buses and
that for the slots preassigned to equipments FA716, FA442, FA446, Fv497 and
Fv618.

For slot assigned allocation refer to page 5-6.

Table 9-5 gives the backplane wiring of the BT148 Expansion Enclosure in
signal name order.

For slot ass"ignment allocation refer to page 5-7.

Table 9-6 supplies the CDT external cable assembly wire list.
Note:
The signal names shown in the wiring lists may differ slightly from those
listed in Section 5.

Equivalents of typical signal names are given below.

Signal name in Section 5
Section 9
ACA05
D(lJUT07

ACAS

ALUOO

DOUT7
ALUOL

·

····
ALU7L

···

ALU07
ALU08

···
·

ALU15
MC

89633300 E

Notes

I,

16 signals to the two ALU assemblies:
suffix L: least significant
suff i x M: most significant

ALUOM
"

.
··
·

ALU7M
MC*

Double/single digit representation
of numbers under 10

"

Inverse signal: overline/asterisk

9-1

TABLE 9-1a. TTY INTERNAL CABLE PIN 89684200
CONDUCTOR
I DENT.
1

COLOR

(1)

RED

2

3
4

5
6
7

8
9
10
11
12

13
14

ORIGIN

RED

P2AO 3
A08
A13
B21
A22
A23
A24
A25
A26
A2l
A28
A29
A30
P2A31

DESTINATION'

REMARKS/SIGNAL NAME

(2)

Pl-24
,3

GROUND
BAUD SEL

23
58
41
43
45
47
49
51
53
55
57
Pl-08

GROUND
PAR.SEL
-12V
-12V
TTY-KB
TTY-PR
CRT-TRANS
EVEN PARITY
MOTOR ON
CRT-REC
VCC

(1) Origin: 66-h61e connector ~hell plug.
(2) Destination: 62-hole connector block.

TABLE 9-lb. TTY EXTERNAL SHIELDED CABLE PIN 89642300
CONDUCTOR
I DENT.
1
2
3
4
5
6
7
8

COLOR

BlK
RED
GRN
WHT
BRN
BLU
ORN
YEL

ORIGIN
(1)

DESTI NAT ION
(2)

5
7
6
8

43
45
47
49

. REM.ARKS/ SIGNAL NAME

-12V
-12V
TTY-KB
TTY-PR
NOT USE 0
NOT USE 0
NOT USED
NOT USE 0

(1) Origin: Molex type.

(2) Destination: Continental type.

9-2

89633300 E

CONDUCTOR
IDENTITY

TABLE 911A TTY EXTERNAL CABLE (PIN 89642300 )
DESTINATION
REMARKS
ORIGIN
COLOR
MOLEX
CONTINENTAL
SIGNAL NAME

1

BLK

5

43

-12V

2

RED

7

45

-12V

3

GRN

6

47

TTY-KB

4

WHT

8

49

m-PR

5

BRN

6

BLU

7

OING

8

YEL

896333000

9-2~/9-28

\

TABLE 9-2. MEMORY EXPANSION BU120-A08 EXTERNAL CABLE ASSEMBLY (Pl) AWG 28
PART NUMBER 89658101 (sheet 1 of 3)

CONDUCTOR
IDENTITY
1
2
3
4
5
6
7
8
.9
10
11
12
13
14
15
16
17

18
19
20
21
22
23
24
25
26
27
28
29
30

COLOR
GRN-WHT
BLK
GRN-WHT
GRN-WHT
BRN
GRN-WHT
GRN-WHT
RED
GRN-WHT
GRN-WHT
ORN
GRN-WHT
GRN-WHT
YEL
GRN-WHT
GRN-WHT
GRN
GRN-WHT
GRN-WHT
BLU
GRN-WHT
GRN-WHT
VIO
GRN-WHT
GRN-WHT
GRA
GRN-WHT
GRN-WHT
WHT
GRN-WHT

ORIGIN

DESTINATION

(1)

(2)

GNO
P1BOl
GND
GND
P1B02
GND
GND
P1B04
GND
GND
P1B06
GND
GND
P1B08
GND
GND
P1B09
GND
GND
P1A10
GND
GND
P1B10
GND
GND
P1All
GND
GND
P1A12
GND

GND
P1BOl -GND
GND
P1B02
GND
GND
P1B04
GND
GND
P1B06
GND
GND
P1 B08
GND
GND
P1B09
GND
GND
P1A10
GND
GND
P1B10
GND
GND
P1All
GND
GND
P1A12
GND

t./

REMARKS/SIGNAL NAME
SLOT 31
SLOT 33
MXOL

SDl

MX1L

SA2

MX2L

SDO

MX3L

SD2

MX4L

SD3

MX5L

SD7

ALU3L

SA3

ALU2L

SD6

ALU1L

SD5

ALUOL

SD4

Numbers enclosed in parentheses indicate notes. See sheet 3.
89633300 E

9-3

TABLE 9-2. MEMORY EXPANSION BU120-A08 EXTERNAL CABLE ASSEMBLY (Pl) AWG 28
PART NUMBER 89658101 (sheet 2 of 3>"

CONDUCTOR
IDENTITY
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60

COLOR
GRN-WHT·
BLK
GRN-WHT
GRN-WHT
BRN
GRN-WHT
GRN-WHT
RED
GRN-WHT
GRN-WHT
ORN
GRN-WHT
GRN-WHT
YEL
GRN-WHT
GRN-WHT
GRN
GRN-WHT
GRN-WHT
BLU
GRN-WHT
GRN-WHT
VIO
GRN-WHT
GRN-WHT
GRA
GRN-WHT
GRN-WHT
WHT
GRN-WHT

ORIGIN
(1)

GND
P1B12
GND
GND
P1A13
GND
GND
P1B13
GND
GND
P1B14
GND
GND
P1B15
GND
GND
P1A16
GND
GND
P1B17
GND
GND
P1B18
GND
GND
P1B21
GND
GND
P1A22
GND

DESTINATION
(2)

GND
P1B12
GND
GND
P1A13
GND
GND
P1B13
GND
GND
P1B14
GND
GND
P1B15
GND
GND
P1A16
GND
GND
P1B17
GND
GND
P1B18
GND
GND
P1B21
GND
GND
P1A22
GND

REMARKS/SIGNAL NAME
SLOT 31
SLOT 33
MX6L

SA5

MX7L

SA4

MXOM

SPBM

MX1M

CPBM

MX2M

SD8

MX3M

SD11

MX7M

SD9

MX4M

SD14

MX6M

SD13

MX5M

SOlO

Numbers enclosed in parentheses indicate notes. See sheet 3.

9-4

89633300 E

TABLE 9-2. MEMORY EXPANSION BU120-A08 EXTERNAL CABLE ASSEMBLY (pJ) AWG 28
,PART NUMBER 89658101 (sheet 3 of 3)

CONDUCTOR
IDENTITY
61
62
63
64
65
66
67
68
69

COLOR

ORIGIN

DESTINfTION

GRN-WHT
BLK
GRN-WHT
GRN-WHT
BRN
GRN;"WHT
GRN-WHT
RED
GRN-WHT

GND
P1B22
GND
GND
P1A23
GND
GND
P1B23
GND

GND
P1B22
GND
GND
P1A23
GND
GND
PlB23
GND

(1)

(2

REMARKS/SIGNAL NAME
SLOT 31
SLOT 33
ALU1M

SA6

ALU2M

SA 11

ALUOM

CRI

(1) Origin: 62-contact connector
(2) Destination: 62-cQntact connector

89633300 E

9-5

TABLE'9-3.' MEMORY EXPANSION BU120-A08 EXTERNAL CABLE ASSEMBLY (P2) AWG 28
PART NUMBER 89658501 (sheet 1 of 3)

I

COLOR

CONDUCTOR
IDENTITY
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16'
17
18
19
20
21
22
23
24
25
26
27
28
29
30

GRK-WHT
BLK
GRN~WHT

GRN-WHT
BRN
GRN~WHT

..

GRN-WHT
RED
GRN-WHT
GRN-WHT
ORN
GRN-WHT
GRN-WHT
YEL
GRN-WHT
GRN-WHT
GRN
GRN...;WHT
GRN-WHT
BLU
GRN-WHT
GRN-WHT
VIO
GRN-WHT
GRN-WHT
GRA
GRN-WHT
GRN-WHT
WHT
GRN-WHT

ORIGIN

DESTINATION

(1)

(2l

GND
P2B02
GND
GND
P2B03
GND
GND
P2B04
GND
GND
P2B05
GND
GND
P2B06,
GND
GND
P2A09
GND
GND
P2B09
GND
GND
P2Al0
GND
GND
P2Bl0
GND
GND
P2All
GND

GND
P2B02 .GND
GND
P2B03/'
GND
' GND
P2B04
GND
GND
P2B05
GND
GND
P2B06 ~.
GND
GND
(~P2A09-;-')
"'--.- _--,.
GND
GND
P2B09
GND
GND
P2Al0
GND
GND
P2Bl0
GND
GND P2All -,
GND

-"'

..

REMARKS/SIGNAL NAME
SLOT 31
SLOT 33
ALU3M

SD12

MX17

SA7

MPRY

SD15

CYIOl

SAl 0

WE

SA12

PRTM

SA9

CPEC

SA14

SPI

SA8

S WRITE

SA13

CRQ

EDX

,."

Numbers inside parentheses insicate notes. See sheet 3.
9-6

89633300 E

TABLE 9-4.a

WIRE LIST AB 107/AB 108 BACKPLANE
(in signal name order)

89633300 A

9-9/9-10

PAGE

NJ

W (

1

FROM
20P2Al3
10P2A2S
lOPIA24
lOP?B07
lOP2B30
10P2A04
10Pl806
10P1826
13P2B13
14P.2812
12P1806
16P1831
14P18l7
09P2A06
10P2A06
lOP2A26
09P2A2b
10Pl A04
09PIA04
lOPl A2 8
09P1A28
lOPlAll
09PIAll
09P 2A13
lOP2A13
09PlA18
lOPIA18
10Pl B30
09P1830
09P2A22
lOP2A22
lOPlAl1
0:) PI A17
lOP2B09
09P2B09
29P28l6
34P2826
32P2B26
30P2826
35P2B26
33P2B26
31P2826
29P2826
29P2 R23
33P2&23
31P2823
35P2821
32P2823
30P2823
34P2823
29P2823

TO
20PlA24
08PlAOI
QSPl A11
caPl R 30
08P2All
ORP2811
08P2dOA
08P? Af)1
12 PI ~O(,
l3P2R13
llP1831
l'5P2AIA
13PIA13
08PIAll
OC;P2A06
09P2 A2l.
ORPIA19
(lC;P1404
08P2416
09Pl A2R
08P18l9
09Pl All
OAPIA 22
08P2R06
09P2All
08P2409
09P141A
09P1830
ORPIA 14
08PlA12
09P2A2~

09PlA17
08P1406
0C;P2809
08Pl1lI?
28P2 81 q
35P2826
33P282l.
31 P7. 826
36P2B26
34P2826
32P2826
30P2B26
30P2B23
34P2B2'~

3·2P2821
36P2B23
33P2R23
31P2B23
35P2B23
2AP28l1

89633300 A

R F

l

I

S T

SIGNAL-NAME

-12 "

A NOENV' 1)
A POSTAf!1BlE
A POS1AMBlE
A R EACY f
A REACY G
A. SKE ~CVF F
A .SKEWCVF G

AID
AID
AID
A/Q CLEAR
A=B
AB CLCCKOUT
AR CLCCKGtT
A8 DA TA
AP DATA
A8 DEN
A8 DEN
A8 DOT
A8 DOT
AB LOI
A8 lOZ
AR PAR lTV
Ai! PAPITy
AS PRESET
4B PRESET
AS PENAelE*
AB PENASLE*
AS TOG
AS TOG
ASCNE
AeCNE
4ShRES(5.
ASWREStS)
ACAS
ACAS
4(A5
ACAS
ACA5
ACA5
ACA5
ACAS
4(A6
ACA6
ACA6
4(46
ACA6
ACA6
A(A6
ACA6

A 6 1
W.L.
8981fl100
89879100
89d 19100
89879100
89879100
89879100
89879100
89879100
89a 79100
89879100
89379100
89879100
89879100
89879100
89879100
89879100
89879100
89819100
89a 19100
89879100
89819100
89819100
A9879100
89879100
89819100
89879100
89819100
89879100
89819100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89819101
89879101
89819101
89819101
89879101
89819101
89819101
89819101
89879101
89819101
89879101
89879101
B9879i01
89379101
89819100

o

118

FR .lEV TO.lEV

1
2
2
1
1
2
1
2
2

1
1
2
2

1

2
2
1
1
2
1

2
2
1
1
2

2

2
2

1
1
2
2
1
1
2
2
1
1

1
1
2
2
1
1
2
2
1
1

2

2

2

2
1

1
1
2
2
1
1

2
1.
1
2

2
2
2
1

1
1
1

1
1

1
1
2
2

1
2

2
1
1
2

2
1
2
2
2
2
1

1
1
1
1
1

1
1
2

2

2
2

2

2

·9-11

PAGE NO

2

FR1 ..
28PlB24
30P2A23
34P2A23
32P2A23
29P2A23
33P2A23
3lP2A23
35P2A23
29P2822
13P2822
31P2822
35P2B22
34P2822
32P2822
30P:! 822
29P2822
29P2A21
30P2A27
34P2A21
3lP:?A21
29PlA27
31)P2A21
33P2Al7
31P2A21
10P2R02
10P2A02
19P1809
19P1 A05
16PIBl2
19P2R25
19P28l0
19P2816
19P2817
26P2A14
22p2822
21P lA31
2ap2814
24P2B01
24P1824
24PIA26
lOP2A24
10P2A09
lOP1803
10PIA26
25Pl816
25P1819
21)P2A09
20Pl A27
28P1812
28PIA28
31PIA12

9-12

W

r

TJ
29P2A21
31P2A21
31)P2 A23
11P2 A2)
30P2A23
34P2A21
32P2 A21
36P2A21
30P2827
14P262'
32P282'
36P282'
35P282'
33P2822
31 P2 82'
28P2A 1 A
28P2820
31 P2 A27
35P2A27
33P2 A27
10P2 A27
36P2A27
34PlA27
32P2A27
08P2A17
08P2AIC)
15P2A29
11PlAIA
15P2810
16P1824
I1P2824
I 7P2 A 01)
18P1830
22P2828
23PIA31
24Pl807
27P2821)
23PIA24
23PIA16
73 PI 820
OSP 2801)
08P2AO?
08P2 A04
08P1826
21P1826
23"PIB14
25P2811
25P7 A09
25PIB24
26PIB24
28 PI B12

R

E

lIS T

A S 1

SIGNAl-NAfoIE

w.l.

A(A7
ACA1
ACA 1
ACA7
ACA7
ACA7
ACA1
ACA7
ACAa
ACA8
ACAa
ACA8
ACA8
ACA8
ACA8
ACA8
ACA9
ACA9
ACA-;
ACA9
ACA9
ACA9
A( A9
ACA9
AC1*
AC2
AOOR ERR
AOOR.CKWO=O
AOOR.ERR*
ADDRESS ECP
ACDRESS 12*
AODRESS*
AOOT I NOE)C*
AOO1M
ACR.
AOR*
ADVANce.
ADy.
ADI
A02
AENVII )
AENVC 2)
AfNVC4.
AENV(5)
Al
AlCI<
AlUOAM
_lueA ...
AlUOl
AlUOM
AlUOl

89819100
89819101
89819101
89819101
89319101
89819101
89819101
89819101
89819101
89819101
89879101
89819101
89819101
89819101
89819101
89819100
89819100
89819101
89d19101
89819101
89819101
89879101
89879101
89879101
89879100
89879100
89819100
89879100
89819100
89819100
89319100
89819100
89819100
89819100
89819100
89879100
89879100
89879100
89819100
89819100
89819100
89819100
89d79100
89819100
8913 79100
89879100
89879100
89879100
89:J 79100
89879100
89879100

o

1113

fR.lEV TO.lEV

2
2
2
2

2

1

2
2
2
1

1
1

1
1

1

1
1
1

1
1
1
1
2
2
2
2
2
2
1
2
1

1
1
2
2
2
2
2
2
1
1

1

1

1

1
1
1
1
1
2

1
1

1
1
1

1
2

1
1
2
2
1
1
2
1
2
1
2
2
1
1
1

2
1
I

2

1
1

2
1
1
1
1
1
1
1
2

2
1
1

2
1
2
1.
2
2

1
2
1
2
2
1

89633300

A

3

PAGE NO

W IRE

TO

FROM
31P1823
31PIAll
?8PIAll
28PIA22
31PIB22
31PIRIO
28P1810
2aPl A21
31PIA23
31PIAIO
'8PIAIO
28PIB28
31P2802
31P2A18
28P2A11
28P2 A16
31P2816
.31P2815
28P2A15
28P2809
31P2AI3
31P2813
28P2A12
28P2B16
31P2811
26P2A04
26P," A04
26P2R02
25P2A04
31P2812
28P2A09
28P2813
31P2B14
13P2822
13P2A21
26P1816
26P 1819
10Pl A07
IOP2AlO
lOPIA16
10PIA03
10P1825
25P2A21
10P2A2 q
10P2805
25P2A30
26P2A30
2SP2815
·33P2 A2 5
31P2A25
29P2A25

28P1A2~

28PIAll
25PIB30
26P1830
28 PI A2'l8PIBIO
25P1821
26P1821
28PIA27
28P1AIO
25PI A21
26PIA21
2ap} 828
28P2All
25P2811
26P2817
28P2A16
28P2A15
25P2 A16
26PlA16
28P2B09
28P2 All
2'lP2All)
26P2A15
28P2816
21)P2802
26P2B05
25P2A04
22P2A29
28P2 A09
25P2815
26P2811)
28P2811
12P1816
08P2A2ft.
21PIA26
23P2A 11
08P2 A12
OSPIA2]
08P1825
08P280te.
OSP1821
24P2AOl
08P2819
08P2A19
22Pl A21
25P2A30
29P2A25
34P2 A25
32P2A25
30P2A25

89633300 A

l

1ST

A B 1

SIGNAL-NAME

ill .l.

AlliOM
AlUll
AlUll
ALUIM
AlUIM
AlU2l
AlU2l
AlU2M
AlU2M
ALU3l
AlU3l
AlU3M
ALU3M
AlU4l
AlUltl
AlU4M
AlU4M
ALU5l
AlU5l
ALU5M
AlUSM
AlU6l
AlU6l
AlU6M
AlU6M
AlU1AL
AlU1 AL
ALU1AM
AltJ1AM
ALU1L
AlU1l
AlU1M
AlU1M
ALl
Al2
AM
AMCK
ANODROPOUT(
ANOEN'J (2 »
ANOENV( 3)
ANOENV(4)
ANOEN"C 5.
AO*
ACNEf*
AONEG*

89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89tJ 19100
89819100
89819100
89819100
89819100
89819100
89819100
89879100
89819100
89819100
89819100
89819100
89d19100
89819100
89819100
89879100
8c;a 79100
89879100
89819100
89819104
89819100
891179100
89819100
89819100
89819100
89819100
89819100
89819100
89879100
89819100
89819100
89819100
89879100
89819100
89879100
89619100
89319100
89819100
89819100
89879101
89819101
89879101

~CC·
~QC*

ARAO
A~AO

ARAO
ARAO

o

118

FR .lEV TO.l EV
1
1
2
2
1
1
2
2
1
1
2
2
I
1
2
2
1
1
2
2
1
I
2
2
1
1
2
1

1
I
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
1

1
2
2
1
2
2
1
2
1
1
2
1
2
2
2

1
2
2
1
2
2
1
2
1
1
2
1
2
2
2
1
2

1
2
1
2
1
1
1

1
2
1
1
1

9-13

PAGE t-.lJ

4

FROM
35P2A25
34P2A25
3.2P2Al5
30P2A25
30P2A29
.34P2A29
32PlA29
29P2A29
33PlA29
31P2A29
35P2Al9
28PZ822
29P2A28
29 P2 Al8
33PZA28
31PZA28
35PlAl8
32PlA28
30PZAl8
34PZAZ8
30P2S25
34P2BZ5
32PZS25
31P2SZ5

33PlSl5
19P2B25
35PlBZ5
28Pl All
Z8P 2823

29P28l8
]3P2B28
31P2BZ8
3SP2B28
14P2B28
32PlS28

30P2Bl8
19P1B04
lSPl807
OAPl8t]
lOP 1 A27
26PlA21
25PlA21
26P2S08
IOPl820
16P2BOA
20P lAO 1
04P1S18
03PIB18
lOPIB19
17Pl B2 9
19P2B12

9- PI

\oJ

I R E

TO
36P2A25
35P2A215
33P2 AZ15
31P2A215
31PZAZ9
35P2 AZCJ
33P2A29
30P2AZ9
34PZ AZ9
32PZAZ9
36PlA29
29PZAZCJ
28P2A23
30PZ A28
34P2A 28
3lP2 A2A
36P2 A2A
33P2A28
31P2A28
3SP2 A2A
.31P2B25
35P2825
33P2825
32P28215
34PlB25
30PlBl15
36PZB215
2 QP2 B21)
29PlB28
30P2R2A
34PZB28
.32P2B2A
36P282A
35P2R28
33P2B28
31P2BZ8
18PIA14
16P2802
I OP2 All
08P2A 13
Z5P2A21
Z4P2A24
22P2A28
05Pl8l8
10PIB20
10PIB19
05plBIS
04P1B18
OSPIBIS
16PZBO~

17PlBZ9

l

I

S T

SIGNAL-NAME
APAO
ARAC
APAO
APAO
ARAI
.RA1
APAI
ARA1
ARAI
ARA 1
ARAI
APAI
ARA2
UIAZ
ARA2
ARA2
ARA2
ARA2
ARA2
APAl
ARA3
ARA3
ARA3
ARA3
ARA3
ARA3
ARA3
ARA3
ARA4
ARA4
ARA4
ARA4
ARA4
APA4
ARA4
ARA4
ARCUR C.. A.
ARCUR-CA*
ASYNC(Z!
A5YNC (4)
ATAUG
ATAUG
AUG7M
AUTOLOAD
AUTCLCAD
AUTOLOAD
AUTOLOAD
AlJTOLOAC
AUTOLOAD
AUTOLOAC2·
AlTOLGAD2*

.:4 B 1
w.L.
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879100
89879100
89879101
89879101
89879101
89879101
89819101
89819101
89879101
89879101
89819101
89819101
89819101
89819101
89819101
89819101
89879100
89879100
89879101
89819101
89879101
89879101
89879101
89819101
89879101
89879100
89879100
89879104
89879100
89879100
89a 19100
89819100
89a 79100
89879100
89879100
89879102
89819102
891179100
89879100
89879100

o

7/8

FR .LEV TO.LEV
I
2
2
2

2
2
2

1
1
1
1
2
Z

1

1
2
2
Z
2
2
Z
1
1

1
1
Z
Z
1

1
I

1

1

1

Z
2

Z

1
1

2
2

2

1
1

2
1
1
1

1

2

1
1

1

1

1

1

1

2
1

2
1

1
1

1

1
2

1

1

1
Z
2
2
Z
1

1

1

Z
1
2
2
1
I
2
1
3
1

Z
I
2

2
2
1

Z

2
1

1
1
I

3
1
2

89633300

A

PAGE NO

WI R E

5

FR'J'4
21PlA08
10P2A05
18PIA25
11P2 A04
16P 1821
19P2B03
11P1809
I1P 2B03
19P2A10
18P1829
17P2A2l·
lSP1B20
18P1824
I1PlB20
17P2819
18PIA30
18PIA28
11P2A11
11P2A16
18P1827
ISP1B13
17P2A15
17P2802
19P1A19
l8P lA26
1~P2B28

17P2A06
18PIB26
19P2A21
11P2B12
18PIA23
18PIB18
l8P 1A24
l7P2A08
13PIA18
18PIB19
litP2B08
21PIB08
22P2A20
18P1823
l7P2814
I1P2B13
18P1A20
27P2B12
09P2A25
09P2AIO
09PlA16
09P1A03
09P2B07
09P2B30
09P2B06

TO
20P1A09
08PIA11
I1P2 A04
15P2 A14
15P2A2A
17PIBOQ
16P1821
15P2Bl'i
18P1829
17P2801
15P2A16
11 P2A21
17P2B20
15P2A13
15P2 All
11P2819
I1P2Al1
15 P2 AI;)
15P1817
I1P2A16
1 7P2 A15
15P2.B14
15P2A21
lRP1A26
11P2801
18P1B2it
1'iP2A2~

17P2A06
lSPl A21
15P2Bl7
11P2B12
17P2A10
11P2A09
15P2B16
12P2807
17P2AOR
12P2 B07
22P2A20
26P2B2~

17P2814
15P280t)
15P2A15
11P2 B11
28P2S0R
08PIA30
08P2 BOl
08P280,.
08P2 BOI
08P1831
08P2AIO
08 P2 801

89633300 A

lIS T

A 8

SIGNAL-NAME

W.l.

AUTRSW*
A\IIRES U-4)
AO
AO
AOAf+MC*
AOAf+MC.
AOAf+MC·
Al
Al
A1
A10
AIO
All
All
A12
A12
A13
A13
A14
A14
A15
A15
A2
A2
A2
A3
A3
A3
A4
A4
A4
A5
A6
A7
A7
A1
A7
A1M
A1M
A8
A8
A9
A9
B
8 NOENV(I)
B NCENV (2 »
8 NOENV( 3)
8 NCENV(4J
B POSTA8lEf
B R EADV F
B SKEWQVf F

89819100
89819100
89879100
89879100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89319100
89819100
89819100
89819100
89879100
89879100
89819100
89879100
89879100
89819100
89819100
89819100
89879100
89819100
89819100
89819100
89879100
89819100
89819100
89879100
89819100
89879100
89879100
89879100
89819100
89819100
89819100
89879100
89819100
89819100
89879100
89819100
89879100
89819100
89819100
89819100
89879100
89819100
8Q819100

89819100

1

o 1/8
FR.lEV TO.lEV
1
1
1
2
2
2
1
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
2
1
1
1
2
2
2
1
1
2
2
2
1
1
2
1
1
2
2
1
1
2
2
2
2
2
2
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1
1
1
2
2
2
1
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
2
1
1
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2
2
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1
2
2
2
1
1
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1
2
2
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1
2
2
2
2
2
2
2

9-15

PAGE NO

6

FROM
091>2AO 5
24P1825
24PIA22
13P2A14
09P2802
09P2A02
21P2831
21P2A30
18PIA13
18P1A27
18P7A07
I1PIA14
15PIA31
09P2A29
14P2S19
28P2 B29
09P2AOI
14P1814
13P1814
17P 1815
1» P2 62 3
17PIB18
12P1609
14P2 A01
13P1828
19P2A30
24P2 A28
28P 1819
19P1 A31
19P2 A04
19P 1813
19PIA12
19PIAli
19P 1 A08
19P1 A06
19P1804
19P1821
19P1820
19P1A21
19P1819
19P1A18
19P1815
I:}P1814
19P1810
17P 1810
14P1A11
19P2B05
I1P1A24
19P2 A29
18P2809
18P2811

9-16

W IRE

TO
08P1A28
22P2A27
23P1830
I1PIA17
08P2811
08P2815
20P1 A07
20P1826
I1Pl Al0
17PIB17
16Pl A23
16P1A08
16Pl A08
08P2820
13P2801
27P2821
08P2B14
13P1814
12 P1820
16PIA16
16PIA15
16Pl R15
08PIA 15
12P2810
12P2810
15P2AOl
22P2B21
21PIA25
18PIA15
18P1814
18PIA 12
18P1812
18PIA16
18P1815
18P1817
18P1A18
18P1816
18P1 All
18P lA21
18P1821
18P1 A22
18P1B27
18P1B10
18PIAI0
16P1A09
13P1817
18P2A06
16PI813
17 PI A24
16P2825
16P282 1

l

1ST

A B 1

SIGNAL-NAME

... l .

B .. RE Sf 1-4)
PB
8BCK
BCD
BC1*
8C2
BEA
BfAC
Bt-BOf(ROW*
BL-tOAO*
Bt>CYl
BL=O
Bt=O
SCNEF*
BOT
BRWRA*
SSl*
aUF 1/0*
aUF 1/0*
8UFF 1-8tiFF 2
BUFFIE!UFF2*
8UFF2 FUL L*
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8USV RR*
BX15
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CACWAO
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CAC WA 10
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CACWA12
CACwA 13
CACWA14
C AC WA1.5
CACWA2
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CACWA4
CACWA5
CACWA6
CACWA 1
CACWA8
CACWA9
CAL-SHIFT·
CARCURAO*
CAR ST*
CAU SHIFT*
CAU St-i I FT*
CAl J*
CAI2*

89819100
89879100
89379100
89819100
89979100
89819100
89879100
89819100
89819100
89919100
89879100
89819100
89819104
89379100
89819100
89819100
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89819100
89819100
89879100
89819100
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89879100
89819100
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89879100
89879100
89879100
89879100
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89819100
89879100
89879100
89819100
89819100
89819100
89819100

o

118

FR.lEV TO.l EV
2
1
2
2

2
2
1
1
1
2
2
1
2
1
1
2
1
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1
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1
2
1
2
1
2
1
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2
1
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1
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89633300

A

PAGE NJ

W IRE

7

FROM
18P2A08
18P2AIO
18P? 808
18P2AOS
18P2AOl
18P2A04
lAPlA05
18P2A22
18P2B06
18P2B06
18P2 A09
~7P2AIO

30P IB23
31P2811
35P2A26
33 P 2A26
31P2A26
29P2A26
32P2A2b
30P2A26
34P2A26
27P2827
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23P2831
2lP282S
12PIR21
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01P1807
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19P1829
19P2AOS
19P2A13
lQP280b
lAP2B17
13P2A02
26Pl A2 8
25PIA28
21P2AlS
23PIA23
21P2810
22P1801
25P lAl3
26P1820
28P2A06
25P 1831
26P1811
25PIAll
26 P IA31.
2SPIB29
26P1829

89633300

TO
16P2B20
16P2B2A
16P2B31
16P2B2Q
16P2B30
16P2814
,
16P2815
15P2A08
15P2AL7
16P2BIQ
16P2 B lA
30Pl B21
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36P2A26
34P2A26
32P2A26
30P2A26
33P2A26
31 P2 A26
35P2A2b
29PlA26
12PI B21
20P2B25
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02P1801
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20PIS17
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20P1814

A

l

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AB 1

SIGNAL-NAME

W.l.

CA13.
CAlS.
CAI6*
CA17*
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89879100
89819100
89879100
89879100
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89879100
89879100
89879100
89879100
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89819100
89879100
89879101
89879101
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89379100
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89879103
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89879100
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89819100
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89819100
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89819100
89879100

o

7/8

fR.LEV TO.lEV
1
1
1
1
1
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9-17

PAGF NO
FR1-'

8

W I
Tl

25P1828
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26PIB28
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23P2A09
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22P1817
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28PIB 13
31P2809
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12PIA31
IlP2830
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28P1822
33P1823
28PIR22
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31P2All
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24PIB26
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26PIB03
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23PlA04
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20P1829
16PIA26
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19P2A08
16PIA2"
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21Pl A2 8
21 P2 BOft
lap 1828
17PIAOA
18P1828
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22P1809
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22P1804
25P283t

9-18

~

E

liS T

A 8 1 o 7/8

SIGNAL-NAME

W.l.

CNS3l.
CNS3M*
CNS4l.
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89879100
89879100
89879100
89879100
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89819100
89819100
89319100
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89879100
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89879100
89879100
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89879100
89879100
89819100
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89879100
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89879104
89879104
89879100
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89879100
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89819100
89879100
89819100
89879100
89819100

FR.lEV TO.lEV
1
1
1
1
1
1
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1
1
1
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2
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1
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2
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1
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89633300 A

q

PAGE NO
FROM

25P2831
19P1IH 1
1RP2813
13P2B14
24-P1821
21P2Bl1
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22P'B30
24P28 1 0
24PIA15
19P2Al4
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31P2818
29PIBO::S
32P1803
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35P1803
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33PIA03
31PIA03
15PIA03
30PIA03
14PIA03
::\2PIA03
29PIA03
2qp1A28
34P1A28
32plA28
30P1A28
35PIA28
33PIA28
31PIA28
29Pl A2 9
?9P lA21
33PIA21
31PIA27
35PIA21
30Pl4.27
34P lA21
32PIA21
29PIA21
28PIB24
34-PIB25
32P1825
30P 1625
lQPl B25

89633300

W 1 R E

TO
26P28 H
I1PIAI0
17P1R14
12PIA01
21 PI A06
29P2BIA
22Pl ~l')
241>2 BIO
25P281"
21P2A26
1SP2A05
21P280R
23PIROI
21P2B19
28P1AO;»
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11PIB01
35P1801
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36P1403
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2 API BO;»
2PPI4o 11
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32PIA2R
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14P1A21
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36PIA21
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35P1A21
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35P1B2S
33P1821)
31P1625
30P1B25

A

l

I S T

SIGNAl-NA~E

C3
o .NO. (eMP •
DATA
DATA
OPB
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DEl*
DElTAUG*
DElTAUG*
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DFEO
DFEO
DFEO
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DINO
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o IN 1
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89819100
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8c;a 79100
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8<1619100
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1

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118

FR.l EV TO.L EV
2
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1
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1
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9-19

PAGE

~()

10

FROM

33P1825
31P1825
15P1825
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33P1827
31P1827
35P 1827
30P1827
34P1821
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34P1828
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33P1826
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29P1826
28P2812
34P2A04
32P2A04
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35P2A04
33P2A04
31P2A04
29P2A04
35P2A05
33P2A05
31P2A05
29P2A05
30P2A05
34P2A05
32P2A05
28P2AI0
2'JP1 A05
32PIA05
30P1405
34PIA05
2QPIA05
33P1405
31PIA05
35P lA05

9-20

W IRE
TO

34P1825
32P1821)
36P182'i
30P1827
34P1827
32P1827
36P1827
31P1821
35P1821
33P1827
28P1826
28P1A25
33P1828
31 PI 828
35P1828
30P1828
34P182A
32PIB2A
36PI828
30P1826
34P1826
32Pl826
36P1826
31P1826
35P1826
33P1826
28P1825
29P2 A0435P2A04
33P2A04
31P2A0436P2A04
34P2A04
32P2A04
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36P2 AOl)
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l. 1ST

S tGNAl-NAME
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OlN12
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DIN13
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OlN16
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OlN17
DIN17
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OlNt7
·0 IN 17
DIN17
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DIN2
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OlN2

A 8 1
ill .l.

89879101
89879101
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89879101

o 7/8
FR .lEV TO.lEV

I
1
1
1
I
.1
1
2
2
2
2
2
2
2
2
1
1
1

1
1
1
1
1
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
I
2
2
2
2
2
2
~

2
1
1
I
1

1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
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1
1
1

1
1
1
1
2
2
2
2
2
2
2
2
1
1
1
1
t
1
1
1
2
2
2
2
2
2
2
2
1
1
1
1

89633300

A

PAGE NO

11

FQ.l~

29PIR07
3.3PIB07
31PIB01
35P1807
30PIB01
34PIB01
32P1 B01
29P 1B01
2QPl AO 7
34PIA01
32PIA07
3l)PIA07
29PIA01
33P1A07
llPlA07
'35P 1 A0 7
29PIB16
33P lR 16
31P1816
:3I5P1816
30P UHf>
34PIB16
3?PIBI6
29PIB16
2C)PIA15
32PIA15
301>1AlS
34PtA15
29PIA15
33P LA 15
31PIA15
35P1A15
2yPIA18
33PIA18
31PIAIB
35P1A18
30PIA18
341>1A18
32PlA18
29PIA18
29;:11819
34PIB19
32P IS 1 <1
30 P UH 9
2:}PIB19
33PIB19
31P1B19
35P1B19
29PIB20
31PIB20
31PIB20

\oJ

1 R F

Til
30P1BOl
34P1B07
32P1B01
36Pl BOl
31PIBC1
35PIB01
33PIB]7
281>1A03
28PIAOA
35PIA01
33P1A01
31 PI A07
30PIAC1
34PIA07
32Pl A07
36PIAG1
30P181~

34Pl Bl~
32PIB16
36PIB16
3tP1B16
35PIBIn
3 3Pl BIn
2AP1A07

2RP1Aln
33Pl AI'>
31PIA15
35P1A15
30PtA15
34PIA15
32PIA15
36PIA15
30PIA18
34PIA18
32PIAIR
"i6P1AIA
31 Pt At A
3SPIA18
33Pl A18
2APIB17
2APIA14
35P1S19
33P1B19
31PlfH9
30PIB19
34PlS19
32PIA19
36Pl B19
30PIB?O
34PIBlO
32PIB20

89633300 A

l

I

S T

SIGNAl-NAfo1E
DIN3
DIN3
D IN.3
DIN3
DIN3
o IN3
DIN)
DIN3
DIN4
DIN4
OlN4
fHN4
DIN4
D IN4
DIN4
OlN4
DINS
DIN')
DINS
DIN5
DINS
DINS
DINS
DIN'>
DIN6
DIN6
DIN6
DIN6
DIN6
DIN6
o IN6
DIN6
o IN7
DIN1
DIN1
DIN 7
o IN7
UIN1
D IN1
DIN1
DIN8
I)lNA
DINS
DIN8
DIN8
DINe
o IN8
DINA
DIN9
D IN9
DIN9

A

jj

W.L.
8<:1819101
89819101
89819101
89819101
89819101
89819101
89819101
8'1879100
89819100
89819101
89819101
89879101
89.3 79101
89879101
89679101
89879101
89879101
89819101
89879101
89379101
89879101
89879101
89819101
89819100
89819100
89879101
89319101
89879101
89d 7910 1
89979101
89879101
89819101
89879101
89819101
89619101
89819101
89819101
89879101
89879101
89819100
89879100
89819101
89319101
8Q919101
89819101
89879101
89879101
89819101
89879101
89:l19101
89819101

1 0 118

FR.lEV TO.lEV
1
1

1
1
2
2
?

2
2
2
2
2
1
1
1
1

1
1
1
1
2

2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
2

2
2
2

2
2
2

2
1
1
1
1
1
1
1

1
1
1
1
2
2
2
2
2
2
2
2
1
1
1
1
1
1

1
1
2

2
2
2
2
2
2
2
1
1
1
1
1
1
1
1

2
2
2
2
2

2
2
2
1

1
1
1
1
1
1

9-21

PAGE NO

12

FROM
351)1820
30PIB20
34P1820
32PIB20
2~ Pl820
271)2810
30P2A21
34P2A21
32P 2A21
35P2 A21
33P2A21
3lPlA21
.29P2A21
19P2808
lAPIB3l
19P2A09
19P1830
21PIBOl
29PIA02
331) lA02
31 PI A02
35P1A02
34PIA02
32PIA02
30PlA02
30PIA04
34P1A04
32PIA04
29Pl A04
33PIA04
31PIA04
31)Pl A04
27PIA02
29P 1824
35P1824
33PIB24
31PIB24
29P1824
34P 1824
32P1824
30PIB24
30PIA30
34 Pl A30
32PIA30
29P 1 A30
33PlA30
31PIA30
31)PIA30
29Pl A30
29Pl A31
29Pl A31

9-22

W (

R E l

TO
36PIB20 31PIB2O
35PIB2O
33P1820
28Pl AlA
2c)P2A21
3lP2 A21
35P2A21
33P2A21
36P2A21
l4P2A 21.
32P2A21
30P2A21
lAPIR31
17PIA1"
1 1~1 Al Ii
l6PIA 2A
29PIAO'30Pl A02
l4,PIAO,32P1 AO'
36PIAO,
35PIAO?
33Pl A02
31PIA02
:JIPIA04
35PI A04
33PlA04
30PIA04
34Pl A04
32PIA04
36P1A04
29PlA04
27PlA16
36Pl824
)4P1824
32P1B24
30Pl B24
35PlB24
33P1824.
31Pl8l~

31PIA30
35PIA30
33PIA30
30PIA30
34Pl A30
32PIA30
36PIA30
2 7Pl A17
21PIA21
30Pl All

1ST

S IGNAl-NM'-E

DIN9
DIN9
DIN9
DIN9
DIN9
DISABLE
DISABLE
DISABLE
DISABLE
D ISABl E
DISABLE
DISABLE
DISABLE

OOF
OOf
OOf-LA
OOf -LA-At TO·
OOUTO
DOUTO
OOUTO
DOUTa
DOUTO
DOUlO
OOLITO

OOUlO
DOUTI
OOUTI
Doun
OOUTl
DOUTI
DOUTI
DOUTI

ooun

DOUT10
DOUTI0
Doun c
DOUlla
DOUTIO
Doun c
DOUIIO
OOuTIO
DOUTll
OOUTll
OOUTll
DOUT11
OCUlll
DOUTll
DOUTll
DGUlil
OOUTl2
DOUT12

A B 1 a 118
W.l.
89819101
89819101
89819101
89819101
89819100
89819100
89879101
89879101
89879101
89879101
89879101
89879101
8981910 I
89819100
89319100
89819100
89879100
89819100
89879101
89879101
89879101
89819101
89879101
89819101
89819101
89819101
89879101
89879101
89879101
89879101
89879101
89879101
89879100
89879100
89819101
89819101
89879101
89879101
89879101
89819101
89819101
89879101
89819101
89819101
89819101
89819101
89819101
89819101
89819100
89379100
89819101

fR.l EV TO.lEV
1
2
2
2

2
2
2
2
2
1
1
1
1
I
2
1
2
2
I
1

1
1
2
2
2
2
2
2
1
1
1
1
2
2
1
1
I
1
2
2
2
2
2
2
1
1
1
1
2
2
1

1
2
2

2
2
2
2
2
2
1
1
1
I
I
2
1
2
2
1
1
1
1
2
2
2
2
2
2
1
I
1
I

2
2
I
1
1
1
2
2
2
2
2
2
1
1
1
1
2
2
1

89633300

A

PAGE NJ

W J

13

FROM

TO

~OP2A02

34PIA31
32PIA31
36Pl A31.
35P lA 31
33PIA31
31 PI A31
31PlS29
35P1829
33Pl B29
30PIR29
l4P1829
32PIB29
36PIR29
27Pl A2~
27PIR24
30P1810
34Pl B30
32PIB30
36Pl B30
33PIB30
31PIA30
35Pl B30
31P183'
35PIB31
33Pl B31
.30P IB 31
34PIB31
32Pl A31
36PIA:H
21P1825
21P2 A16
30P2AOl
34P2 AOI
32P2AOl
36P2 AOI
33P2 AOI
31P2AOl
35P2AOl
31 P2 A07

34P2A02
32P2 A02
Z9P2A02
33P2A02
llP2 A02
35P2A02
27P2B05
28P2BlO
29P }A06
29PIA06
33PIA06
31PIA06

33P2A02
30P2 AO?
34P2A02
32P2A02
36P2.A07
28P2BIO
29P2A07
27PIB04
30PIA06
34Pl A06
32PIA Oft

33PIA31
31PIA31
35PIA31
~4PIA 31
32PIA31
30PIA31
30PIB29
3r.Pl B29
32P1829
29P 1829
33PIA29
~lPIB29

35PIB29
29P1829
29PIB30
29P1830
33PIB30
31PI830
35PIB30
32PIB30
30P 1830
34P1830
30P1831
34P1831
32Pl B31
29PIB31
33PIB31
31PIB31
35PI8.31
29P1831
29P2A01
21P2AO 1
33P~AOl

31P2A01
35P2AO 1
32P2AOI
30P2AOl
34P2AOI

89633300

15P2AO~

A

R E

l

[

S T

SIGNAL-NAME
OOUTl2
00Ul12
00UT12
00UTl2
00UT12
OOUTl2
OOtH13
OOUTl3
00UTl3
00UT13
00UT13
OCUTl3
00UT13
00UT13
00UTl4
00UT14
00UT14
DOUT14
00UT14
OOUTl4
DOUT14
DOUT14
OOUTl5
OOlJT15
00UT15
DOUT15
OOUTi5
00UT15
DOllT15
OOUT15
00UTl6
DOUT16
OOUT16
OOUTl6
00UT16
DOUTl6
DOUTl6
OOUT16
00UT17
DOllTl1
DOUT17
OOUTl 7
DOUT17
DOUT17
OOUll1
00UT17
DCUTl1
00UT2
DOUT2
DOUT2
OOUT2

A 8 1
W.L.
89879101
89879101
89819101
89879101
89879101
89879101
89879101
89879101
8C)879101
89879101
89819101
89879101
89819101
89879100
89879100
89879101
89819101
89879101
69819101
89879101
89879101
89819101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879100
89879100
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89819101
89879101
89879101
89879101
89879101
89879100
89819100
89879100
89819101
89879101
89819101

o

7/8

FR .lEV TO.LEV
1
1
1
2
2
2
2
2
2
1
1
1

1
2
2
1
1
1
1
2
2
2
2
2
2
1
1
1
1
2
2
1
1
1
1
2
2
2
2
2
2
1
1
1
1
1
2
2
1
I
1

1
1
1
2
2
2
2
2
2
1
1
1
1
2
2
1
1
1
1
2
2
2
2
2
2
1
1
1
1
2
2
1
1
1
1
2
2
2
2
2
2
1
1
1
1
1
2
2
1
1
1

9-23

P4GE NO

14

FR)M
35PIA06
32PIA06
30PIA06
34PIA06
lOPl A08

W JR E

TO
36P1406
33PIA06
31PIA06
35Pl A06
31PIAOA

~4PIA08

~5PIA08

32PL A08
29PIA08

33PIAOR
30PIAOA
34P1A08
32PIAOA
36PIAOR
21 PI ROt;
27PIB07
30PIA09
34PI AOCJ
32PIA09
36Pl A09
15Pl A09
33PIA09
31PIA09
31PIA14
31)PIA14
33PIAlt.
30PIA14
34PIA14
32PIA14
36PIA14
27Pl B09
21PIBIO
10PIA11
34Pl A17
32PIA11
36PIA11
33 PI Al1
31P1411
35P1417
31PIA19
35P1A19
33P1419
30PIA19
14P1A19
32PIA19
36PIA19
27PIB12
27 Pl All
30PLA20
34P1420
32Pl A20
36PIA20
35PIA?O
33Pl420

3~PlA08

31PIA08
35PIA08
29PIA08
29PtA09
29PIA09
3~Pl A09
31PIA09
35PIA09
34PlA09
32PIA09
30PIA09
30PIA14
34PIA14
32 PI A14
29PIA14
31PIA14
31PIA14
35PIA14
29Pl A14
29PIA11
29P1A17
31PIA17
31PIA17
35PIA17
32Pl A11
30P1A11
34PIA17
"lOPI A19
34P 1A19
32PIA19
29PIA 19
33P1A19
31PIA19
35PIA19
29PIA19
29PIA20
29PIA20
33P1A20
3lPl A20
35P 1A20
:':S4PIA20
32PIA20

9-24

LIS T
S' (GNAl-NAfolE
OOUT2
DOUT2
DOUT2
DOUT2
DOUT3
OOUT3
OOUT3
00UT3
OOUT3
DOU 13
DOllT3
DOUT3
DOU14
DOUT4
DOUT4
00U14
OOUT4
00UT4
DOUT4
00UT4
DOU15
DOUTS
00UT5
DOUTS
DOUTS
OOUTS
OOUT5
00UT5
00UT6
DOUT6
DOUT6
00UT6
00UT6
00UT6
OOUT6
DOUT6
OOUT7
00UT7
OOUT7
DOUT7
00U17
OOUT7
OOUT1
DOUT7
oeUTa
DOUTa
00UT8
DOUT8
DCUT8
OOUTS
DOUT8

A 8 1

W.l.
89879101
89879101
89879101
89879101
89879101
89879101
89379101
89879101
89979101
89879101
89879101
89379100
89879100
89379101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89819101
89879100
89879100
89879101
89879101
89879101
89879101
89819101
89879101
89879101
89879101
89819101
89879101
89879101
89879101
89879101
89879101
89879100
89379100
89879101
89879101
89879101
89879101
89879101
89879101

o

7/8

FR.LEV TO.lEV
1
2
2
2
2
2
2
1
1
1

1
2
2
2
2
2
2
1
1

1

1
2
2
1
1
1
1
2
2
2
2
2
2
1
1
1
1
2
2
1
1
1
1
2
2
2
2
2
2
1
1
1
1
2
2
1
1
1
1
2
2

2

2
1
1
1
1
2
2
2
2
2
2
1
1
1
I
2
7.
I

1
1
1
2
2
2
2
2
2
1
1
1
1
2
2
1
1
1
1
2
2

1

89633300

A

PAGE NO

W I R E

15

FROM
10PIA20
30PIA25
34PIA25
32PIA25
29P1 A2 5
l3P lA25
31PIA25
35PIA25
29P 1 A25
19P1B23
19P2A20
19P2A25
19PIA24
IlP7A20
14P2R30
t8P~B04

30P 2801
31P2B01
32P7R01
33P2BOl
34P2BOl
15P2B01
3bP2BO 1
28PlA22
2AP 2A13
23P2B14
l3PlB10
3:4P2A11
22P2818
22P7.R 18
24P2B18
13Pl620
14P2B29
21PIA15
21PIA15
22PIR15
23P2A20
2lPt B24
22plA05
21PIB24
22PIA08
22P1AIO
21PIBl8
22P2B 11
13P1A31
14PZAZ1
14P2BOl
12P2A08
lqPl A2 0
13P2A13
lQPlB31

TO
31PlA20
31 PI A20
35PIA20
33PIA20
3 oPt A20
34PIA20
32PIA20
36PlA 20
27PIB11)
16 P2 B2~
16P2Bll
16P2R24
16 Pl B.)7
12P1 A73
11P2 A21')
16PIA01
28P2AOl
28P2BOl
28PIB3l
2RP2B 11
28 P2 ROt.
?8P2B05
28P240'i
21P2 R06
211'1821
27P1A26
12 PI All
21P.7A05
20P2 BOl
21PIA19
23P2A 11
12P1628
13P2R20
24PIB02
23 P2 Btl)
24PIRt8
24PIBll1
22PtAOl)
24PIAOl
23P2AZl
23P2B 16
21P21l14
20Pl A24
2tPIBIR
lZPIA25
13PIA31
13P 24 1 ~
11P2RO':\
L6Pl B30
12P2AOR
16PIR2Q

89633300

A

L 1ST

AS 1

SIGNAL-NAME

W.l.

00UT8
OCUT9
OOUT9
00UT9
00UT9
DOUT9
DOUT9
OOUT9
00lJT9
DRIVE FAULT
DRIVE RO*
DR J VE SE *
OSA CCNNECT
OSA WREN*
DSA WREN*
DSA-BUfFl*
OX1*
OX2*
OX3*
0)(4*
OX5*
0)(6*
0)(1*
016
017
EAO*
E~RLY "OS
EDX*
E(NT
flNT
E[5*
ENA*
ENA*
EN I
ENI
ENI2E*
ENI2E*
FN120*
EN120*
EN120*
ENI3*
ENI4*
ENT ER*
ENTER*
EOG*
EGG*
EOP
FOP
FOP
EOP
EOPMCT BS\'*

89879101
89879101
89879101
89879101
89879101
89679101
89879101
89879101
89879100
89S79100
89d19100
89879100
89879100
89819100
89J19100
89319100
89819100
89819100
89819100
89819100
89819100
89819100
89d 19100
891) 79100
89879100
89319100
89819100
89819100
89879100
89819100
89819100
89819100
89879100
89819100
B9819100
89879100
89819100
89819100
89879100
89819100
89819100
8~B19100

89819100
89879100
89819100
89879100
89819100
89819100
89819100
89S191JO
89819100

o

7/8

FR.lEV TO.LEV
2
2
2
2

1
1
1
1
2
1
1

1
2
2
1
2

1
1
1
1
1
1
1
1
2
2
2
1
2
1
2
2
1
2
1
1
2
2
1
1
2
1
1
Z
2
1
1
1
2
2
2

2
2
2
2
1
1
1
1
2
1
1
1
2
2
1
2
1
1
1
1
1
1
1
1
2
2
2
1
2
1
2
2
1
2
1
1
2
2
1
1
2
1
1
2
2
1
1
1
2
2
2

9-25

PAGE

~]

16

FROM

WI R E
TO

LIS T
SIGNAL-NAME

A B 1
W.l.

o

7/8

FR .LEV TO.lEV

16PIB29
12PIA24
17P1AOb

15P2BO"J
IlP2B16
16Pl B21i

ECPMC T
EORS
EOS

B~'1*

89879100
89879100
89879100

1
1
1

1
1
1

14P2827
19PIBOl
23P1827
2lP2AlO
21P2AI0
23P2820
14P2801
IlP2B18
14P1824
14P1824
24PIA03
22PIA21
22Pl A2 0
231)2802
14P2828
14P2B26
081)1822
25PIB21
26PIR21
2e;P2803
26P2803
09PIAOl
23Pl Bll
22P2A26
20P2B02
21P2A05
22PIAli
201)2802
21 PlA04
21P2B09
31P2Bli
31P2B20
27P2B23
2'iPIA02
2lPIA24
lIP lA24
26PIA25
26P2BI0
2e;P2B06
26P2 B16
26P2All
27P2B14
21P2A24
27P2B 13
21P2 AOB
l4P2Bl4

l3P2B23
15P2A19
22PIBOB
2.3P2B17
22PIAlA
22PIBIB
11 P182A
llP2Ble;
l2P2A11
13~2 8lA
21PIA27
21PIA09
24P2 B29
22P2801J
1.3P2 B25
12P2B17
12P2B17
ZlP2B02
21PIR20
2lPIB3l
21 P2 BO~
09PIB 11
27P2 B21
23PIBl&
23PIB21
24P2 B2e;
23PIB21
21P2A oe;
20PIB2B
23PIAOR
23PIAO'i
27P2 B23
21PIB21
ZlPIAz2
25P2 Al1
26PIAO?
26Pl A24
26P2A11
26P2B16
26P2 BI0
26PIA25
28P2A2'i
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21P 2 A07
27P2B01
08Pl A2it
1.3P2B01

EOT*
E'U.NUM.MAT

89819100
89879100
89879100
89879100
89879100
89879100
89819100
89879100
89879100
89879100
89819100
89819100
89819100
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89a 19100
89879100
89879104
89819100
89819100
89819100
89819100
89819104
89879104
89879100
8S879100
89879100
89879100
89879100
89819100
89819104
89879104
89879100
89819100
89819100
89819100
89819100
89819100·
89819100
89819100
89879100
89879100
89819100
89819100
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89819100
89819100
89819100

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1
1
2
1
2
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1
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2.
1
2
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1
1
1
2
1
2
1
1
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1
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2
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1
2

2
1
1
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1
1
1
2
2
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1
1
1
2
2
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1
2
2
2
1
1
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1
2
2
2
1
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2
1
2

1
2
2
2
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1
1
1
2
2
2
1
2
2
1
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14~1B30

9-26

EXT

FEO*
FEO*
FIEF
FILL
FM/TM

FM/TM
FM/TM
F S*
FIEI
FIE23
f23
G~P ClaCK
GC128
GCIZ8
Gll
GLM
GML
GMM
GND
GND
GOAQ*
Goes
Goes
GOCS
GOCS
Goesw*
GOMI
GOMl
GPEe*
GPEe*
GSl*
GSM*
GSM*
HIGH
HIGH
HIGH
HIGH
HIGH
HOLD
HOLOW
ICA*[CO*
I(A-ICO
Ie ABORT*
IlLLSCODE

89633300 C

P~GE

NU

17

FROM
L~P1818

W I

TO

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16P1823
19P2A26
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19P2 A17
22P?AQ8

12P1 BOA
16P 18 2'4
15P2821
1 API A3 t
17P2BOI
16P2809
21P1821

22~2A08

20P2~IR

I1P2A14
19P2A21
19P1828
2.3Pl A21
19P1B23
23P2A27
23P2A27
13P 7815
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21P2A07
25:>1B10

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22 PI A21
17P lA2R
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12P2B16
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25P1AI0
20P2A17
22PIB29
22PIA30
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23 PI Bl1

2~P2A01

2.3PIA25
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23P2A05

23Pl~0C)

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21 p2 A 16
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23 PI 81A
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89633300 A

R E

l

I

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A B 1

SIGN~l-NAME

w.l.

I Nee ~*
I NCR "TA
INCR TA
I NCR TA
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INDEX GATED
INDIND*
I NO [NO.
INH IB IT NEE
INIT
[NIT 0
INO
[ NPlT CK~D
INR
INR
INT
INT.SW*
INTOl
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IN32
11'141

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89379100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
R9879100
89879100
89879100
A9879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89379100
89819100
89879100
89879100
69819100
89879100
69879100
8,)d 79100
89879100
89879100
ij9379100
89879100
89879100
89879100
89879100
89619100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89d 79100
89819100
89879100

10

10
I RC I<
IRCK
IRJ*
I SA I So
1ST 5P
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ITA4l*
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ITR
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12
13
14
14
15
15
16
16
It5
17*
17*
JENI
J HR*
JKCK
J I1815
26P1815
75PIA16
31P 1 B06
74PIA20
24PIR15
31PIA16
26PIA16
21PIB08
3lPI B08
25P2A20
26P2A20
31P1818
21P1B21
27P 1 A09
31 PI 809
21)1>2820
26P2B20
31PIA22
27PIA23
25P2A18
31P1812
74P 2A 19
31 PI B21
26P2A18
21P1A22
21P1B13
25P2B19
31 P IA13
31P1817
26P2B19
21P1B20
24P2A14
lOP 2BO 1
33P2B13
21P2B11
23P 2B07
22 Pl BO ~
02PIAO'l

9-30

RE

l

I

S T

SIGNAL-NAME

21P1 SOl
J5P1A19
27P1B01
21PIA1';
26PIA19
21PIA1')
21P1A2n
27PIA26
27PIAI)4J1PIA04
25P181'>
26Pl B 1 ')
27P IB 11
27PlfH 7
21Pl AOI)
27PIAOn
25Pl Alll
26PIA16
21PIB1Q
21 PI B19
?5P2 b.20

MXll
MX1l
MX1l
MX1M

/I.1)clM
MXIM
MX17
M Xl 7
MX2l
M)l2l
M X2l
MX2M
M >e2M

MX2M
MX3l
MX3l

MX3l
M)(3 M

1120

M)C3M
MX3M
M)(4L
M)(4l
MX4l
M)(4M
MX4M
MX4M
M)(5l
MX5l
M>cSl
/Io1)(5M
MX5M
M>eSM

2}PlA11

M)C6l

21111 AU

MX6l
M)6l
MX6M
MX6M
M)(6M
MX7l
MX1l
M)C7l
MX1M
M)1M
M)C1M
NO
NOOPOPOL;T
NORMAL
NCP"'AL
Nltl
N41
OAO*

21Pl~OR

24P2fH9
24P2BG'>
271'1821
26P2 A20
2SP2820
21 Pl A09
74P2R 17
24P2AOl-1
21P1A2~

26

25P2418
21PIA27
24-P2 BOR
26P2A1R
25 P2 B 19
24P2A16
21P1B1~

27P1B20
24P2AOl)
26P2819
23Pl !32A
10P182A
21P2B11
21 P2 A tl
241>2B14
23P2B;')1
06PIAOl

A S 1 0

W.l.
89a19100
89879100
89819100
89t119100
89819100
89d19100
89819100
89819100
89319100
89879100
89~ 79100
8981910 0
89819100
89379100
89819100
89919100
89d 19100
89819100
69819100
89819100
89319100
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89819100
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81:1819100
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89819100
89879100
89879100
89879100
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89819100
89819100
89319100
89879100
89319100
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89819100
89819100
89819100
H9819100
89879100
89879104
89;]19100
89819100
89819100
89819100
8981910]

11A
FR.LEV TO.LEV

1
1
'J.
2

1
1
1

?

2
1
1

1
1
2
2
1
1
1

1
1
2
2

1
1
1

2
2
1
1

1
1
2
2
1
1
1

1

1

2
2
1
1

2
2
1
1

1

1

1

1

2

2

2

2

1

1

1
1
1
2
2
1
1
1

1
1
1
2
2
1
1
1
1
2
2
1
1
1
1
2
2

1
2

2
1

1
1

1
2
2

1

1

2
2
1
2

2
2
1
2

89633300

A

PAGE NO

W (

21

TO

FROM

06Pl A03
01PIA03
15PlA03
17P2 B04
25P2A05
19PIA30
20P2A20
13PIB29
13PIA30
19P1826
20P2R20
21)P2 A02
1l)PlBOl
17P 2A02
06P180 1
OlPIBOl
02P 180 1
02PIB06
06P1R06
01PIB06
2bPlAl0
l5PIB06
I1P2822
lqPIA14
20PlB26
l4Pl B20
14PlA20
19PIBl2
2:lP2828
l5PlA05
17P2A20
26P2B04
06PlA05
01PIA05
02PIA05
02P1A04
06PIA04
01PlA04
15PIA04
I1P2A19
19P1B08
26PlA23
14P1819
l4PIA18
19PIA07
20P?Al1
15P 1809
17P2B17
06PIB09
OlPIBOq
02Pl R09

07PIA01
02Pl A01
13PIB2CJ
19P1 A30
20P2 A20
l5PlA01
l7P2304
07PIA01
07P1BOl
1l)PIROl
l7PlA02
20P2 B20
13Pl A30
It;PIB26
07PIBOl
02P1BOI
06P1801
06PI B06
07PIB06
02PlBO&
lOP2 A21a
14PIB20
19P1A14
l5PlBOn
17P2B21
07P1B06
07Pl AOI)
15PIAOl)
17P2 A20
14PIA 20
19P1Rl1
10P2 B2A
C1PIAOl)
02PIAOl)
06PIAOS
06PIA04
01P1A04
02 PI A04
14PlFH9
19PIBOR
15PIA04
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07PIA04
C7PIBOQ
15PlR09
l1P2 fH 1
l4PlAIA
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06PIB09

89633300

A

R f

lIS T
SIGNAl-NA~t:

OAO*
OAO*
OAO*

DAO*
OAO*
OAO*

DAO*
OAO*
OA1*

OAl*
OA1*
OA1*
OAl*
OAl*
OAl*
OA1*
OA1*
OA10*
OAIO*
OAlO*
GAIO*
OAI0*
OAI0*
OAlO*
OAI0*
OAI0*
OAII*
OA11*
OAll*
OAll*
OAll*
OAll*
OA11*
OAl1*
. nAl1*
OA12*
OA12*
OA12*
OA12*
OAl2*
OA12*
OA12*
GA12*
OA13*
OA13*
OAI3*
OAll.
OA13*
OAIl*
OAI3*
OA13*

A B 1

W.L.
89B 79103
89879103
89819100
89d 79100
89879100
8'i879100
89879100
89879100
89879100
89fJ79LOO
89879100
89879100
89879100
89819100
89879103
89879103
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89879100
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89379103
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89819103
89879103
89319100
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89819100
89879100
89d 19103
89679103
89879103

o

7/8

fR.LEV TO.lEV
1
1
1
1
1
2
2
2
2
2
2
1
1
1
1
1
2
2
1
1
I
1
1
2
1

2
2
2
2
1
1
1
I
I
2
2
1
1
1
1
2
2
2
2
2
2
1
1
1

1
2

1
1
1
1
1
2
2
2
2
2
2
1
1
1
1
I
2
2
1
1
1
1
1
2
2
2
2
2
2
1
1
1
1
1
2
2
1

1
1
1
2
2
2
2
2
2
1
1
1
1
2

9-31

PAGE

~]

2?

FROM
26P7Fi24
02P1BIO
06PIBIO
01P1810
1l)Pl810
I1P2816
19P1 AO 1
26P2A2?
l4PIBl8
14PIAl9
1QP1801
26P2822
15PIAll
I1P28l8
06P 1 A11
OlPlAll
OlPlAll
02PIB02
0()PIB02
01P180Z
1C;PIB02
17P2 AO 1
25PlA30
19P1B24
20P2819
l.~P lA21
13PIB2l
19P1 Al6
20P2A17
25P2804
15PIA06
17P2B06
O() Pl A06
01PIA06
02PIA06
02Pl AO 1
ObPIAOl
OlPl A07
1 I)Pl A07
I1P2A 11
25P2A23
19P IBI A
20P2A21
13Pl A20
13PIB19
19P1A19
20P2822
25P2B24
15PIAOl
17P2BIO
06PIA01

9-32

W I

TO
20P2A 11
06Pl R10
C1Pl AIO
02PIRIO
14P181A
1 QP1 AOI
15P1810
11P2B16
C1PIAIO
01Pl All
l5Pl AU
I1P7fHA
14PIA19
19P1 B01
01Pl ~ 11
.'l2Pl All
06Pl All
06PIB02
01PlBO?
02PIB02
13PIA21
19P1824
20P2Bl9
15PIB02
1 7P2 AOI
C1PlBO?
07P1A06
1I)PIAO"
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20P2A17
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17P2A 11
01 PI A01
C7PIAOI
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07PIAOl

RF

l

I

S T

SIGNAL-NAME
OAI3*
OAI4*
OA14*
OAI4*
OA14*
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OA14*
0.614*
OAI4*
OA lS*
0,615*
OAlS*
OA15*
OA11)*
OA15*
OAI5*
OA15*
OA2*
CA2*
OA2*
o,A2*
0,62*
OA2*
OA2*
0,62*
OA2*
OA3*
OA3*
OA3*
OA3*
0063*
OA3*

OA3*
OA3*
OA3*
OA4*
OA4*
OA4*
OA4*
OA4*
OA4*
0064*
OA4*
0064*
OA5*
OA5*
0,65*
OA5*
OA5*
OA5*
OA5*

A i3 1
W.l.
89819100
89iJ1910J
89819103
89.879103
89819100
89819100
8C3a 19100
89879100
89879100
89379100
89879100
89879100
89'379100
89819100
89319103
89879103
89819103
89819103
89319103
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89879100
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89379100
89819100
89379100
89879100
89879100
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89819100
89d19100
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89379100
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89819103

o

11B

FR .lEV TO.lEV
1
2
1
1
1
1
2
2
2
2
2
2
1
1
1
1
2
2
1
1
1
1
1
2
2
2

2
2
2
1
1
1
1
1
2
2
1
1
1
1
1
2
2
2
2
2
2
1
1
1
1

1
2
1
1
1
1
2
2
2
2
2
2
1
1
1
1
2
2
1
1
1
1
1
2
2
2
2·
2
2
1
1
1
1
1
2
2
1
1
1
1
1
2

2
2
2
2
2
1
1
1
1

89633300

A

PAGE NO

PI I

23

Til

FROM

OlPIAOl
OlPIAOI
O.2PIA02
0&P1A02
01P1AO.2
15PIA02
l1P2B09
25P.2A.22
BPI A11
20P2B18
13P1A19
IlP1B20
19PIR16
.20P2A19
25Pl82.2
15P1R03
11PlB08
OoPlB03
01PIB03
OlPlR03
02P1804
06PIB04
OlP1B04
26P2A05
I5PIB04
IlPlA13
19PIA15
20P2B23
14PI B2 q
14P1R.22
19P1A13
20P2B24
15P 1 B05
11P.2A12
26P2A02
06 P IR05
OIPl B05
02PlB05
22P1RIO
21PIR13
22PIB12
21PIB13
24P1A02
23PIB22
21PlB11
24P2R16
I1P2B05
11PlA22
l3PlA27
23P2A04
23P1Bl3

OlPl AOI
06PIAOl
06PlA02
01Pl AO'
OlP lA02
13PIA19
19PIA17
20P.2RIR
15PiA02
llP2R09
01PIA02
01PIR03
15PIBO~
I1P2~OR

lOP2 AI9
13P1B20
19PIR16
01PlR01
02PIB03
ObPIB03
ObPlB04
01PIR04
02P1B04
20PlB21
14PIBlQ
19PI A15
15PIB04
IlP2AI3
01PlB04
C7P1805
15PIBOl)
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23 Pl Bll
22PIA28
23PlBU
23P2A1f,
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17 Pl ROC;
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24PlB28
lOPl B2~

89633300

A

R E

l I S T
SIGNAL-NAME
OA5.
OA5.
OA6*
OA6*
OA6*
OA6*
OA6*
oA6*
OA6*
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OA1*
OA1*
OA1*
0~1*

OA1*
oA7*
OA1*
OA1*
OA1*
OA8*
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OA8*
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OA8*
OA8*
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OA9*
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OA9*
OA9*
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A B 1

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89819103
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89819100
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89819100
89819100
89819100
89819100
E9819100
89379100

o

7/8

fR.lEV TO.lEV
1
.2
2
1
1
1
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2
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?
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1
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1
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1
1

9-33

PAGE NO

24

FROM

231)2806
22PIA19
22PIA19
22PlA06
24PIA01
22P?Al?
22P2A12
26P2B21
lOP lA3l
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O:}P1824
lOPi. 824
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21P1828
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13P2B01
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26Pl813
25PIB13
2lP2A22
10P1801
13P1831
l4P2AOl
13P1830
llP1829
14P2823
12P1825
l3P2B06
13P2R08
13P2A29
l3P2A30
2ltPlA21
04P1A11
03PlAl1
12P1801
21PIB06
21P2826
19 tJ IAIO
20P2A07
31P2A22
21P lA14
22P2Bl9
22p2S20
21P2A05
25PIA23
26PlA23
25P2AoI

9-34

WI

(

TO
24PlAO"
20PIA22
11P2B09
l3P2824
21 P2 A2~
20P2AOl
21Pl810
21 PI B12
09P143t
08P2A22
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09P1824
09PIA30
08P2826
2RP2 All
I1P2811
1.3P2AlA
21P2 A2'
lOPIAOl
10Pl AOI
25P1813
23P1B1~

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09PIBOI
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08P2809
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l3P2 B06
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OAP2Bt2
08P2A 14
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04Pl At1
05PIA11
19PIAIO
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l?PIBOl
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21P2826
23PIAllj

R E

l

1ST

A 8 1

SIGNAl-,..AME

,. .L.

OPO*
OPST
OPST
OP20*
OSC*
OVFl*
OVFl*
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01*
01*
012
012
02*
02*
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PAR ERR.
PAR ERR.
pSC
PC 1600*
pC 1600*
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pel*
pe2
PE ENABLE
PE fOP*
PE lOST CAT
PE PARERRt
pE START
PE START
PE ST~RT
PE WOfCNING
PECHARClK
PEClOCKt
PEf*
PEl*
PEl*
PEl*
Pl;l*
PEl*
PEl*
PEl*
PElt
PHI

89319100
89819100
89819100
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89d 19100
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89d 19100
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89879102
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89a 79100
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89819100
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89819100
89379100
89879100

2~P180A

P~2

23PIA21.
22P2820
21P2AOI
2lP1A21
21P2S01

PH3
pH3
Pll
PlM
PMl

o

118

FR.lEV TO .LEV
2
1

2
1
2
1

1
2
1
2
1
2
2
1
2

1
2
2
2
1
2
1
1
2

1
2
2
1
2
2
2
2
2
2
1

2
2
2
1

1
1
2

1
I
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1

12

2
1
2
1
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1
1
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1
2
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2
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1
2
1
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2
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1
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2
1
2
2
1
2
2
2
2
2
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2
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1
1
1

2
1
1
2
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,.

1

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89633300

A

(

(

PAGE

~)

W

25

TO

FROM
?6PlAOI
19P2810
OS P2 82 it
I4P2R20
I1PlA03
IlPIAOl
llPlB06
UPl B07
llPl R03
lIP 1808
11 Pl 809
llP1BOl
21P2Rl3
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llPlB13
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1lPIA12
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11P2B04
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13P2A25
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2iP2A28
15P2B28
15P2828
IlPlA19
llPLA25
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06Pl A23
01PIA23
31P2A09
33P2B12
21P2AI4
27P2BOI
09P2A21
lOPlA21
lOPl A08
10P1Al3
lOP 1802
LOPl A25
09P2A08
09PIA13
09PIB02
2ltPlBOb

[

21P2AOl
15P2A20
12Pl A06
OAPIA21
10P2A2A
10P2Al~

09P1A 21:t
09PIA2l
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CQPlB06
10PI A21
IOPl806
20PIA2?
09Pl B27
CRPlR2~

lOPl All
1 OP2 82ft
10P2AICJ
09P2B26
OqPlA?l
09P2A19
10PlAl?
09PIA17
10PlA21
10PlAIO
12PlAO?
12p2B15
OSP2 A21
15P282R
12P1Al9
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07PIA2'l
20PIR30
2IP2824
06PIA21
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02PlA21
27PIB30
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20PIB09
21P2Allt
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08 P2 A28
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08P2A21
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89633300

A

R E

L I

S T

A t3 1

S (GNAl-NAME

W.l.

PMM
POKM
POS TAMBl E
PRBOT
PROOUl 0
PROOUT 1
PROOLT 2
PROOUl 3
PROOUT 4
PROOUT 6
PROOUT 7
PROOUT5
PRF(PfINO)
PRFB
PRFB
PRGST
PRIN 0
PRIN 1
PRIN 2
PIHN 3
PRIN 4
PRIN 5
PfCIN 6
PRIN 7
PfiINP
PROT fAULl
PRoTECTEO
PRSTRG8E
PRTAO*
PRTAO*
PRTAQ*
PRTAO*
PRTB(T
PRJM*
PRTM*
PRTM*
PRTM*
PRTM*
PRTSW
PRTSW
PRTSW
PRTY FN 81*
PRTY GN A1*
PRT'f GN /J2*
PRT'f GN A3*
PRTY GN A4*
PRTY GN A5*
PRTY GN e2*
PRTY GN B3*
PRTY (iN e4*
PRY

89879100
89879100
89879104
89819100
89879100
89879100
89379100
89879100
S9S79100
89379100
89879100
89879100
89879100
89879100
89879104
89879100
S9S79100
89879100
89879100
89879100
891) 79100
89879100
89879100
89879100
89819100
89879100
89879100
89879100
89879100
89879100
89819100
89379100
89879100
89819100
89879103
89879103
89879103
89a 19100
89979100
89379100
89879100
89879100
89819100
89879100
89819100
89819100
89879100
89819100
89d19100
8911 79100
89879100

o

7/8

FR.lEV TO.lEV
2
2

2
2

1
2

1
2
2
2
2
2
2
2
2

2
2
2
2
2
2
2

1

1

2

2

1
2
1
2
1
2
1
2

1
2
1
2
1
2

1
I

1

1
2
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1
1
2

1
I
1
1
3
3
I
2
2
1

1
1
2
3
3
1
2
2
1

1
1

1
1

1
1
2
2
2
1
2
1
2
2
2
2
1

1
1
2
2
2
1
2
1

2
2
2
1

1

9-35

PAGE NO

l6

FROM

SEE
BELOH

W IRE
TO

lIS T

A 8 1

SIGNAL-NAME

W.l.

PSFM*
PTADO
PTAOO
PTAOO
PUR*
PWOIN 0
PliO IN 1
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PWOIN 5
PWOIN 6
PWOIN 7
PwoINP
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PWOUT 0
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PWOUT 2
PWOUT 3
P~UT 4
PilOUT 5
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PIlOUTP
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PWRO
PWROSHIFlfO
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P4M
P4M
QCK
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11 Pl AOI
25PIA12
22P2B24
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19P2824
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llPIA15
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llPlA18
I1PIB18
14P2A30
llP2B09
I1P2B08
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I1p2820
I1P2818
. I1P2824
11 P2B22
11P2823
I1P2B26
12PIA28
12P1812
28P2A14
22P2 A21
21P2A15
25PIA14
23PIAli
20P2A05
25P1812
24P2B02
21P IB03
25P2A06
24P2822
25P2A26
15PIA12
19p1A28
12P1831
06PIA12
01PIA12
02PIA12
19P2802
15P 1 B12
12P2801
> 25PIAli
121)2822
20P2816

08P2A08
26PIA12
24PIA19
25PIA12
16P2B12
10PIAOt;
10PIA20
09PIAOt;
09P2B12
0'<.) PI A20
10P2A21
09P2A21
10P2B12
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09P2810
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1 OP2 823
09P2821
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08PIAI0
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21P2A17
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22P2A21
2.6Pl A14
25Pl A14
19PIA28
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25P2A06
24P2802
26P2A06
25P2A26
26P2A26
12P1831
15PIAI2
01Pl A12
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15P1812
19P2802
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15P2A10

OlAOO
OlAOO
00
00
00
00
00
00
01
01
01
01
010
010

89819100
89819100
89819100
89819100
89819100
89819100
89879100
89819100
89879100
89819100
89879100
89819100
89819100
89879100
89879100
89819100
89819100
89819100
89819100
89879100
89819100
89879100
89819100
89819100
89819100
89879100
89819100
89879100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89879103
89819103
89879103
89879100
89819100
89819100
89879100
89819100
89879100

> 02P1612
>06P1B12
>01PTB12

06P1B12
'17P1B12
02P1B12

Ql
Ql
Ql

898791(1)
8987910f)
89879100

9-36

00
00

osx
osx
osx

o

118

FR.lEV TO.lEV
1
2
2
1
1
2

2
2
2
2
2
2
2
2
1

1
1
1
1
1
1
1
1
1
1
2
2
I
1

1
2
2
1
1
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1

1
1
1
1
2

2
1
1

2

2

2
1
1
2
2

2
1

1
1
1
2
1

2
2
1
1
2
2
2

1
2
2
1
1
1

2
1
2
2
1
1
2
2
2

',....

1
1
1

1
1

1

1
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1
1

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89633300 C

.'(

!"

''.l

PAGE NO

27

FROM

W IRE
TO

lIS T
SIGNAt-NAfilE

A B 1
W.L.

o 7/8
FR.L EV TO.L EV
2
2
2
2
1
1
2
1
1
2
1
1
2
2
1
1
2
1

015
015
015
015
015
015
015
02
02
02
02
02
02
03
03
03
03
03
030
030

89819100
89879100
89879100
89819103
89879103
89879103
89879103
89819103
89819103
89819100
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89819100
89819100
89819100
89879100

06PIA14

04

89819103

2

2

07PlAl4

04

89879103

1

1

15PIAl1
15P2AI0
26PIA08
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0~P1 A17
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01PIB11
15P1811
26P1809
26P2A21t
15Pl A18
02P1418
06PIA18
01PIA18
02PIB18
06P1818
01P1818
15P1818
26P2828
26P2825
15PtAt9
02Pl A19
06P1A19
01PIA19
02P1819
06PIB19
01P1819
24Pl B28
15PIB19
26P2801
21PIB09
19P2801
15P1A13
25Pl A08
02PIA13
06Pl A13
01PIA13
06PIB13
01 PI B13
02PIB13
15P1813
25P1809
26P 1 B08
25Pla08

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12P2B22
20P2B16
06P1A17
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02P1A18
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01PIA19
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01PIA19
02PIA19
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01PIB 19
02P1819
26P2 A28
()1PIBI9
15PIB19
24Pl B28
15PIA11
07PIA13
19P2801
06PIA13
07PIA13
02PIA13
07P1813
02Pl B13
06PIB13
01P1813
15Pl B13
25PIB08
21PIB27

02PIA14
06 P IA14

010
010
010
010
010
010
011
011
011
011
011
012
012
012
012
012
013
013
013
013
013
011t
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lit

o

014
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1

2
1
1
2
2
1
1
2
1
1
1
2
1
2
1
2
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2
1
1
1
1
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2
1
2
1

2
2
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2

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1
2
1
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2
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1
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1
1
1
2
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2
2
2
1
1
1
1
2
2
1
2

1

9-37

·PAGF NO

28

W IRE

FAOM

Tl

0lPIAl4
15P1 A14
2,P2A24
20P2801
2(1)2815
.21)P2828
It;P1R14
. 06P1814
01Pl'l14
02P 1814
02PIAl5
06PIA15
01P1A15
15PIA15
25P2B25
20P2A14
12P2 A24
20P7.A06
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15P1815
15P2B09
06-P1815
01P1B15
02PIB15
02P1Alta
06PIA16
OlPlA16
15PIA16
11)P2A09
26PIB12
20P21n4
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06P1816
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19P2801
19P7.809
l8P2All
17P2A21
19P2 82 7
21P2A20
35P2821
3lP2821
31P2821
29P2827
30P2821

02 PI Al~
C7PIAl4
20P? 607
15P1A14
It;P1814
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01PIR14
02 PI 81~
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07Pl Ai';
02P1All)
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20P2A14
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15PlBl1)
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02PlAl6
01Pl A16
12P2B21
20P2814
lSP2 A09
15P lA 16
15Pl A16
15P2810
20P2A16
01P181fa
17.p2 A21
07PIB16
02P1816
06PIR16
17P2801
18P2 All
17PIAll
16P2811
I1P2 Al1
2QP2B21
36P2821
34P?R27
32P2821
30P2821
3lP2Bl1

I I ST
SIGNAL-NAME
04
04
04
04
05
Ot;
05
05
05
05
06
06
06
06
06
06
07
07
07
01
07
07
01
01
08
08
08
08
08
08
08
08
09
09
09
09
09
09
09
O~

R+C+CC
R+lIl+C
R+W+C
R "W+C+CC
R+W+C+CC
R/lR/W

R/W
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R/w
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A 8 1

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8913 79103
89d 79100
89a 79100
89819100
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89819103
89819103
89819103
89819103
89879103
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879103
89879103
89379l0,j
89879103
89819103
89879103
89879100
89879100
89819100
89879100
89879100
89879100
89819100
89879100
B9879100
89819100
89819103
89819103
89819103 .
89879100
89819100
89819100
89879100
89819100
89819100
89879101
89819101
89819101
89879101
89879101

o

7/8

FR.lEV TO.lEV
1
2
2

1
1
2
2
1
1
2
2
1
1
2
2
1
1
1
2
2
2

1
1
2
2
1

1
2
2
2
1
1
1
1
2
2
2
1
1
2
2
2
1

t

2
2
1
1
1
1
2

1
2
2
1
1
2
2
1
1
2
2
1

1
2
2
1
1
1
2
2
2
1
1
2
.2
1
1
2
2
2
1
1
1
1
2
2
2
1
1
2
2
2
1
1
2
2
1
1
1
1
2
\

9-38

89633300

A
(

\

PAGE NO

29

FR1M
l'tP2B27
3lP2Bl7
12P1A27
l~Pl A02
13PIB02
13P lA03
14PlB03
14P1R01
IlPIAOI
13PIBOI
14PIAOl
14PIA06
13P1806
13P LA01
1ltPI B07
14PIA04
13PI A04
13PIB04
14P 1804
11PIR30
19P2All
16P lA06
I~P2B20

11P28l5
15P 1A21
20P2A04
11PIB29
19PIB02
2lP2802
02PIA21
06Pl A21
01PIA21
llP2Al1
21 P2 A01
32p2A20
30P2A20
34P2A20
35P2A20
33P2A20
31P2A20
29P 2A20
15PIB22
01PIB22
06P1B22
OlPIB22
19PIBOl
22P2A24
lc)PlBl2
20P2813
2JP2B12
15PlA22

WI R E
Tl
35Pl B27
33P2B21
IlP2A2'>
13Pl BOl
11PIA04
llPIAOl
13Pl A03
13P lAOI
lipl AO'>
II PI A06
1 '3Pl BOt
13PIB06
11 PIB04
IlPIBOl
13PI A01
13PIA04
IlPl A01
II PI AOR
13Pl804
16PIAOt.
11P1830
l5Pl606
11PlA19
16P2Bl1
12PIB29
19PIBO'
C1PIA2l
15PIA21
2 OP2 AOIt
06P1A 21
01PIA21
02Pl A21
12P2Al3
29P2A20
33PlAlO
31P2A20
35P2 A20
36P2A 20
34P2A20
37P2 A20
30P?420
12P2Alit
06PIR2'
C7PIB22
02P1 R2?
1')P182'
20P26l1
01P1 B2'
19P1BOl
19P1A03
01Pl A'l2

89633300 A

l

r S T

SIGNAL-NAME

R/W
R' ..
RDS·
RDTAPE 0
RCTAPE 0
R CTAPE 1
ReT APE 1
RDTAPE 2
R[TAP E 2
ROTAPE 3
RCIAPE 3
ROTAPE 4
RCTAPE 4
RDTAPE 5
RCTAPE 5
RCTAPE 6
R OTAP E 6
RCTAPE 1
RDTAPE 1
READ
READ
READ
READ tATA
READ GATe.
REAO.
READ.
REAO*
REAO.
READ*
REAO.
READ.
REAO·
READY
REF.
REF.
REF.
REf.
REF.
REF.
REF.
REF.
REJ EC T*
REJECT·
REJECT.
REJECT·
REJECT.
REJECT.
RF.J ECl.
REJECT*
R EPl y*
REPLY'·

A B 1

W.l.
89879101
89819101
89879100
89879100
89819100
89879100
89879100
89879100
89819100
89879100
89879100
89879100
89819100
89a 79100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89879100
89819100
89819100
89819100
89819100
89819103
89879103
89819103
89819100
89879100
89819101
89879101
89819101
89819101
8~819101

89819101
89819101
89819100
89819103
89819103
89819103
89819100
89319100
89819100
89819100
89879100
89819100

o

7/8

FR.lEV TO.lEV

2
I
1
1
1
3
2
1
1
1
1
2

l
l
1
1
2
l
1
1
2
2
1
1
l
2
1
1
2
2
1
1
2
2
1
1
1
1
2
2
2
2
1
1
2
2
2
2
2
1
1
1
1
3
2
1
1
1
1
2

2

2

2
2

2
2

l
2
1
1
2
2
1
1
2
2
1
1
2
2
1
I
2
l
1
1
l
2
1
1
1
1
2
2
2
2
1
1
2
2
2

2

9-39

PAGE NO

30

FROM
22P2825
1~P1A03

SEE
BELOH

02PIA22
ObPIA22
01PIA22
15P lA22
14P2A29
·13P2B17
> lap lA11
1 5P2 B20
16P1421
I:}P2819
19P2819
17PIB01
13P2All
14P1A07
13P2A28
12P181 ~
14P2B05
08P 2810
08 P2B10
24P2B15
23P2A26
27P~828

33P2A22
22P2A11
12P2 A05
14P2A25
IJP1AOb
20P2804
21PIA17
20Pl B04
7.2P2B04
22P2804
22P? 406
2]P2828
23P2B26
22PIB26
23P2A25
24PIA08
1]P2A22
l2P2831
14P2815
13P~B26

14P2A22
21P2425
24PIB27
24P1821
24PIA28
24P 1A28
21PlBOb
>

18P2BOl
9-40

W IRE
TO
20P2812
15PIA22
06PlA2'
01PIA22
02PIA2~

12P2R14
l3P2B11
12PIA17
16PIA05
15P2B01
l5P2B20
16PIA21
16PIA21
16PIAll
12PZ818
12P1826
12P1819
11P1A3t
13P2A2A
14P2B06
11P2 B07.
23P,A19
24P2A27
21PIB2'
27P2B28
20PIA21
IIPl B30
12P2B05
12P2805
23P2429
22P1820
21P1 A17
24PIBOA
23P2R21
23P2828
24P2B30
24P2 A29
23P2826
24P1405
22P2 A2'
11P2 8 14
11P2829
13P2826
12P2831
11P2B28
28P2 B21
23P2Al'
22PIA24
22 PI A2l
2.3P281'
2.7PIB19

l8P 1A11

L

I S' T

SIGNAL-NA~E

A 8
W.l.

1

o

7/8

FR.lEV TO .lEV
1

1
1
2
1
1
3
1
2
2
2
1
2
2
2
2
2
2
1
1

1
2
2
1
1
1
1
2
2
2
1
1
2
2
1
1
2
1
2
1
1
1
2
1
2
1
2
2
1
2

1
2
2
1
1
1

Rl
Rl
R2
R2
R3

89819100
89819100
89819103
89819103
89819103
8lJ879100
898791.00
89819100
89819100
89S19100
89879100
89819100
89879100
89879100
89879100
89879100
89879100
89879100
89819100
89819104
89879104
89879100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89879100
89819100
89819100
89819100
89879100
89819100
89879100
89819100
89819100
89879100
89819100
89819100
89879100
89879100
89819100
89819100
89819100
89819100
89879100
89819100
a<;819100
89819100

REf1"EST*

89879lan

3

3

REPlY*
REPlY*
REPl V*
REPl y*
f'lEPlV*
REPl Y*
REO*
REO*
REOUE ST*
RESCTf'l8SY·
RESCTRBS~*

RESET CTR B
RESET (TR B
RESUME
RES1*
RESl,l*
RES2*
RES2*
RES2*
REV*
REV*
RElf
RE18*
~GPWR

RGPWR
R INO
RMOT
RMOT*
RMOT*
RNI
RNI
RNI
PNlll *
RNll1*
RN112*
RNIl2*
RNI21*
RN121*
RN122*
RP
RklO R.UNlD
RWlO*
RWLO*
RWlO*
RhUNlO*

RXA

1
2
1
1
3
1
2
2
2
1
2
2
2
2
2
2
1
1

I

i

2
2
2
1
1
2
2
1
1
2
1
2
1
1
1
2
1
2
1
2
2
1
2

(

\
(,

\

i

/

\
;'

\

LENf1TH 8"
89633300 C

(

\
~

\,

PAGE NO

W IRE

31

FROM
22PIBIQ
21P2ROb
21PIA30
22PIR22
21PIA30
12PIA19
27PIB31
I~Pl BOS
3lP2BIO
O,.Pl B21
OJPIB21.
11P2A26
03PIB23
04Pl B2]
l3PIROS
28P2A24
18PIA02
33P2A19
l8PIROl
33P2B19
28P2B25
I1PIA23
Oft.P1B14
OlPlB24
04PIA25
03PIA25
28PIA26
l8PIR02
33P2805
Ift-PlBOS
28PlB21
14PIA23
laPl A03
3lPlA23
03P1A26
04Pl A26
04PIA27
03PIA21
18PIBO 1
33P2R06
28Pl B2 7
14Pl A08
28P) A31
l4tPl A26
18PIA04
33P2BIO
OlPl A28
04PIA28
04PIA30
03PIA30
l8P 1804

TO
24PIA24
23P2A2~

2]P2 BIA
24PIB21
22PIR22
0'jP1821
16PIB05
1.2PIAl9
27PIB]1
O'jPIB 21
04P1B21
19PIR22
04Pl823
01) Pl821
OSPIB21
18PIAO?
13 PI ROl)
28P2A24
llPIA2]
2 8PZ 825
ISPIBOl
05P182ft.
OSP18Z4
04P1B24
OSPI A21)
04PlA2'j
18PIBO?
14Pl BOl)
28PIA26
0l)PlA25
18PI A01
05PIA26
14Pl421
.28P1821
04P1A26
OSPI A26
05PIA21
04PIA21
14P1 AOA
2APIB27
18P1801
05Pl A21
18PIA04
05PIA2A
l4PIA2~

2APIA3l
04PIA2R
05PIA2A
05PlA30
04Pl A30
14PIBOQ

89633300

A

l

I

S T

A B 1

SIGNAL-NAME

.., .l.

R3
R3
R4
R4
R4
S WRITE.
S WRI TE*
S WRITE.
S wRITE.
S WRITe.
S WRITe.
SAMPLE Cf-!EC
SAO
SAO
SAO
SAO
SAO
SAO
SAl
SAl
SAl
SAl
SAl
SAl
SA10
SAle
SAI0
SAI0
SAlO
SAI0
SAIl
SA 11
SAIl
SAIl
SAil
SAll
SA12
SA12
SA12
SA12
SA12
SAI2
SA13
SA13
SA13
SA13
SA13
SA13
SA14
SA14
SA14

89879100
89819100
89379100
89879100
89879100
89879100
89819100
89879100
89:379100
89879102
89879102
89879100
89879102
89879102
89379100
89879100
89879100
89879100
89319100
89879100
89819100
89879100
89879102
8987910,
89819102
89879102
89879100
89819100
89879100
89819100
89879100
89819100
89819100
89819100
89879102
89879102
89819102
89879102
89879100
89819100
89879100
89819100
89879100
89879100
89879100
89879100
89879102
89879102
8~819102

89879102
89819100

o 7/8
FR.lEV TO.lEV
1
1
1
1
2
2
2
1
1
.2
1
1

1
2
2
2
1
1
1
1
2
2
2
1
.2
1
2
1
1
2
2
2
1
1
1
2
2
1
1
1
2
2
2
2
1
1
I
2
2
1
1

1
1
1
I
2
2
2
1
1
1
1
1
1
1
2
2
1
1
1
1
2
2
1

1
1
I
2
1
1
2
2
2
1
1
1
1
1
1
1
1
2
2
2
2
1
1
1
1
1
1
1

9-41

PAGF NO

32

FR1N
33P2809
28PlA30
14P1809
27PlAOl
14P1B25
18P1AOI
31P2A12
01PIA31
04Pl A] 1
04P1825
03Pl825
18P1808
3.lP1B02
llPIA05
28Pl801
28PIA06
11P1823
lRPlA08
llPIAI0
03P1826
04P1R26
OlP 182 7
04Pl821
18PlA09
]lPIAIJ
Z8PlB09
13PlB08
28P1A09
13PIA26
18P1809
33P1812
04Pl828
OlP 1828
03P1830
04P1810
18j)lB06
33PIB22
28PIA21
l]P 1~09
28 P18l]
13PIB25
18PIA06
33P2B03
04P1831
OlPlB31
04P1A21
03PIA23
18P1A07
33P2AIO
28j)1B30
14P1A05

W I
Tl
l8PI A30
18PIB04
OSPI A30
18 PI AOI
OSP 1 A31
14P182,)
27P2 AOI
04Pl A31
05Pl A31
05P182,)
.04PI82')
13PI AO,)
28PIBOl
05PIB2,)
18Pl BOR
18PIAOR
05PIB2"
13Pl B21
28PIAOh
04PIB2b
05P182b
04P1821
05P1827
11PIAOR
28PIB09
18PIA09
05PIB21
18P180IJ
05PI82A
13PIA26
2API A09
05P182R
04P1B2A
04Pl830
05Pl8]0
13PIAOIJ
28PIA21
1 API B06
05PIB]O
18 PI AOit
05PIB.3t
13P182')
2AP1823
05PIB31
04PIB31
05Pl A2l
04PIA21
14Pl AO')
28P18]O
I8P1A07
05PIA2}

R F

lIS T
SIGNAl-NA.-e
SAl4
SA14
SA14
SA15
SA15
SA15
SA15
SA15
SA15
SA2
SAl
SAl
SA2
SA2
SA2
SA3
SA3
SAl
SA]
SA3
SA3
SA4
SA4
SA4
SA4
SA4
SA4
SA5
SA5
SA5
SA5
SAS
SA5
SA6
SA6
SA6
SA6
SA6
SA6
SA1
SA7
SA1
SA7

SAl
SAl
SAA
SA8
SA8
SAA
SA8
SA8

A 8 I o 7/8
W.l.
89819100
89819100
89819100
89819100
89819100
89879100
89879100
89819102
89879102
89819102
89819102
89819100
89819100
89879100
89879100
89819100
89879100
89d79100
89819100
89819102
891319102
89819102
89819102
89879100
89879100
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89879100
89819100
89819100
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89879100
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891319100
89879100
89819100
89819100
89819102
89819102
89819102
89819102
89819100
89819100
89879100
89879100

fR.lEV TO.lEV

1
2
2
2
2
1
1
1
2
2
1
1
I
2
2
2
2
1
1
1
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1
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2
2
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1
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2
1
1
2
2
2
2
1
1
1
1
2
1
1
1
2
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1
2
2
2
2
1
1
1
1
1
1
1
1
2
2
2
2
1
1
1
1
1
1
1
1
2
2
2
2
1
1
1
1
1
1
1
1
2
2
2
2
1
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1
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1
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2

I

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(

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/

\.
(

~
(

\,

~
~

.
9-42

89633300 A

~

~
i

PAGE NJ

13

W I

TO

FROM
2RPIR29
14P1A22
18PIB07
33P2A09
03PIA24
04Pl A"l.4
16P lA04
i !l!.! Ai! ~
l-9Pl R2 7
19P 7. AO 7
19PIA23
lqPIA22
16PIBOl
121'128
2RPIB03
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27PIA01
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04PIA03
03PIA03
03PlBOl
04PIBOt
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27Pt A03
33PlB01
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28PlB20
27PIR18
331>1A22
lB P2A30
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28P1A23
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33P2B02
1~P2A28

03PIA04
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04PIR09

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2RPIR29
04P1A24
as PI A2'+
12P2B2S
92f I fU!:I
15P2A24
15P2B24
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15P2B25
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A5@' 81'"
27P 1A 01
05Pl A01
13 PI A17
2RPIB01
13PIA12
05P1 AOl
04P1AO"-4
04PIBOl
05PIROt
13PIAI0
13Pl AI0
2APIAOl
"27Pl A03
05 P1801
05PIB06
21PIBIR
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28PIBlO
14Pl AI0
05PIR06
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05PlBOQ

89633300

E

R E

l

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S T

SIGNAl-N~ME

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S~9

SAC;
SA9
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SCROOI SCR [M

A B 1
\oil

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89819100
89879100
89819102
89879102
89d 19100

a

7/8

fR .lEV TO.LEV
2
2
1
1
1
2
1

2
2
1
1

1
1
1

8~ai!ila8

i!

i!

89819100
89319100
89819100
89819100
89879100

'}

1
2
1
1

2
1
2
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1

Sf8FM·'e l ."

a'tt"JAA

1

,

SOO
SOO
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500
500
SOO
SOO
501
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89879100
89879100
89879100
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89819102
89819102
89819102

2
2
1
1
3
2
1
1
2
3
1
1
2
2
2
2
1
1
3
7
1
2
1
3
1
1
2
2
2
2
1
1
3
1
2
1
2

2
2
1
1
3
1
1
1
1
3
1
1
2
2
2
2
1
1
3
1
1
1
1
3
1
1
2
2
2
2
1
1
3
1
1
1
1

SOL
501
5010
SOLO
5010
5010
5010
5010
5010
5011
5011
5011

SOLI
5011
5011
5011
S012
SD12
5012
SD12
5012
S012
5012
SC13
5013

Removed by
FCn CK676

Removed by
FCO CK676

9-43

PAGE NO

34

FR1M

18'P2B29
27P IB23
33P 1 B21
28P1A20
14PIB26
28PIA19
14Pl A15
27PIB22
33P1818
18P2A29
04P 1810
0}P1810
04PIAI1
03PIAlI
18P28}O .
27PIA19
33P2B04
28PlA24
14PIA14
27P2A21
33P2A18
03PIA18
04PIA18
04Pl A2 0
03P lA20
33P2815
27P2A18
28P1804
13P1810
2.7PIA05
33P1806
18P2826
03PI802
04PI802
04P1A06
03PIA06
18P2A25
27P1806
3.3P1808
l8Pl A05
13Pla12
28P1808
13P1815
27PIA07
33PIA12
l8P2A23
03PIA07
04PIA07
04PIA01
03PIAOl
18P2824

9-44

W I. R E
Tl
14P1826
14PIB26
28PIA2()
27P1821
05P1BO,9
27P1822
05 PI 810
14P1A15
28Pl A1q
14Pl Al'i
05P1810
04PIBl()
05P1All
04P1A 11
14Pl Al4
14PIAI4
28PIA24
21Pl A19
05PIAll
OSPIA1R
27P2A21.
04PIAIR
05PIA18
05Pl A20
04PIA20
27P2 AIR
Q5PIA20
27PIA05
05P1802
13P1810
28PIB04
13PIB10
04PIBO,
·05P1802
05Pl 'A06
04PlA06
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13P1812
28PlAOl)
27P1806
05PIA06
27PlA07
05Pl A07
l3P1815
28P1 SOR
13Pl SIS
04PIA07
OSPl A07
OSPl AOI
04PIAOl
13PIBll

t

r 5 T

SIGNAl-NAI4E
5013
50135013
SC1.3
5013
5014
5014
5014
5014
5014
5014
5014
5015
5015
5015
5015
5015
5015
5015
5016
5016
5016
5016
5017
5017
5011
5017
502
502
502
502
502
502
502
503
503
503
503
503
503
503
504
504
504
504
504
504
504
505
505
505

A B1
W.l.
89879100
89879100
8<;879100
89819100
89879100
89879100
89879100
89879100
89879100
89879100
89879102
89879102
89879102
89879102
89879100
89879100
89879100
89879100
89879100
89819100
89819100
89879102
89879102
89879102
89819102
89819100
89879100
89879100
89879100
89879100
89819100
89819100
89879102
89879102
89879102
89879102
89879100
89879100
89879100
89879100
89819100
89819100
89819100
89879100
89879100
89879100
89879102
89879102
89819102
89819102
89819100

o

118

FR.lEV TO.lEV
3
1
1

3
1
1

2

2
2

2
2
2
I
1
3

2
1
2

1
3
1
1

2
2
2
1
1
2
2
1
1
2
2
2
1
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~

1
2
2
1
3

1
1
2
2
2
2
1
1
3

1
2
2
1
3

2

2
1
1
3
1

1
1
1
3
1
1
2
2
2
1

\

1
1

1
1
1

2
2
2
1
1
3
1
1
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1
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1
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1
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89633300

A

~
r1

\i

PAGE N.1

35

FROM

SEE
BELOH

W I R E
TO

L I S T
SIGNAL-N~ME

W.L.
89879100
89819100
89879100
89819100
89879100
89879100
89879100
89879100
89879100
89879102
89819102
89879102
89819102
89819100
89879100
89819100
89879100
89819100
89819100
89819100
89879100
89879100
89879100
89879102
89879102
89819102
89879102
89879100
89819100
89819100
89879100
S9879100
89879100
89879100
89879100
89819100
89879100
89879100
89879100
89819100
89819100
89819100
89819100
89879100
89879100
89819100
89879100
89819100
89819100
89879100
89879100

28PIB07
13PIB13
21PIA08
33PIALI
21PIAI0
33P1810
28P1B06
13Pl A16
18P2A24
03P 1A02
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03P1803
04PIB03
18P2B25
28PIB05
13PIA15
21PIA12
33PIB09
27PIB14
33PlB15
28P IB14
14Pl B12
18P2B27
Oft.P 1 B04
03PIB04
03PIB05
04P1805
18P2A26
2SP IB 18
14PIBIO
21PIB16
33P1B17
l6Pl A22
22P2A04
19 P.lA16
18P2A12
> 18P2A12
Ift.PIA25
13P1A25
13PIA27
14Pl A2 7
19PIAOft.
lRPlB05
14P2B02
l6P2A06
16P2A04
16P2A02
l6P2AOl
19P2829
19P2A14

27PIAOR
05P 1 AOI
13Pl B11
28PIB07
13Pl Alb
28Pl BOft
27PlAI0
05PIA02
13Pl Alft
04PIA02
05PIAOl
04PIB03
05PIB03
13Pl Al r;
27P1A12
05PIBO}
13Pl A15
28P1805
14Pl B12
28PIBIft.
21PIB 14
05Pl B04
14PlS12
05PlS04
04PIB04
04PIB05
05PIB05
1'4PIBI0
21P IS 16
05Pl B05
14PIBIO
l8PIB 18
26Pl S2~
26PIA22
15P2A02
17PlA25
16P2BI0
13PIA25
12P2Bll
12P2All
13Pl A21
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15P2A 01
11 P2 B01
15P2A26
15P2B26
15P2A27
15P2827
16PIA25
16Pl A30

S05
S05
S05
S05
S06
SD6
S06
S06
S06
S06
S06
S07
S01
S01
S07
501
507
SOl
508
508
508
508
508
S08
S08
S09
S09
509
S09
S09
509
SD9
SE
SE
SE.U.PRT.
SECTOP G~TE
SEC TOP GAlE
SELAO
SELAO
SELA1
SELAI
SELO.UTPILO
SELO.LTPl10
SEOP.
SEOSCl*
SEO SC2*
SE05C3*
SEO 5C4*
SET ALARM*
SET CIR seE

> 19P2B15

17P1A12

G~\TE

89633300 C

A B 1

SECTOR

o

7/8

FR .LEV TO.LEV
2
2
1
1
1
1
2
2
3
1
2
1
2
3
2
2
1
1
1
1
2
2
3
2
1
1
2
3
2
2
1
1
1
2
2
2
1
1
2
2
1
1
2
I
I

2
2
1
1
1
1
2
2
3
1
1
1
1
3
2
2
1
1
1
1
2
2
3
1
1
1
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2
2
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1
1
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2
1
1
2
2
1

1

1

2
1
1
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1
1
2

1
1
2

3

3

1

LENGTH

gIL

9-45

PAGE Nil

36

FRilM

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18PIA19
2,)PlRl2
O~PlA20

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21P7Al]
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26P2B11
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22P1806
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22P2A30
11PIA01
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18P2A18
18P2819
22P2826
2'5P2'AOA
24P2A12
33P1813
2AP1A12
12p2A18
21P1829
16PlA03
31P2AIO
04PIA14
O]P 1814
04PIA15
03PIA15
16PIAO 1
31P2820
12PIA20
27P2A28
12PIA14
21P2818
16PlAI0
13P2816
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04PIA13
01P 1812
04P1812
33P2817
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12P1B22
21P2Al9

W I q F
TJ
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11 P2 810
14P281A
2'jP1A27
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24P2 iH 1
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17PIA11
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15PIA17
26PIA17
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20P1824
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16Pt1314
24P2 Al7
26P2AOA
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21P2A2A
0l)PIA15
16Pl AOt
CSPl All
16PIAIO
12PIA14
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04P1All
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12P1827
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16P1801

LIS T
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ss..

AB 1
W.l.
89879100
89879100
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o

118

FR.LEV TO.lEV
1
2
1

1
2
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1
1
2
1
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9-46

89633300

A

(

PAGE NO

11

\II

FROM

I

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14P2813
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13P2804
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24P2A13
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15 P 2A 21
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21P2B 70
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89633300

A

R E

l

1ST

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STRL'S
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51
51
511
S15
52
52
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Wi

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8981(1101
89879101
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898 7q 100
89379100
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8<;819100
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89819100
89819100
89819100
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1

o

118

FR.l EV TO.L EV
2
1
1
1
1
1
Z

2
2
1
2
2
2
2
1
1
1
1
2
1
1
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2
1
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1
2
2
2
1
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2
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1
2
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2
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1
1
2
2
2
1
1

9-47

PAGE NiJ

18

FROM

loPI 810
ISP1BI0
11PIA1O
19P2A16
19P2B14
17 P2 A2 3
lAP2802
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19P1A13
18P2R03
21P1A24
13P2814
13P?B Ib
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14P1A19
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16P2A07
21P2A31
21 P2 A30
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29 P 2A16
1~PIA11

18P2A19
17PIB19
19P1AOI
14P2Alb
19P2B12
11P1B27
09P2A07
10P2 A07
13P?B09

9-48

WI R E
T1
15P2829
17PIA1O
16P1810
16Pl B 16
lRP2B02
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21PlB16
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L I

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SIGNAL-NAME
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89-179100
8<;d 79100
89~ 79100
89879100
89879100
89879100
89819100
89879100
89879100

o

7/8

FR.lEV TO.lEV

1
1
2

1
1
1
Z
2
2
1
1
2
2
1
1
1
1

1
1
2
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1
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89633300 A

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41

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9-59

PAGE NO

6

FROM

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89633300 A

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89879100
89819100
89319102
89879103
89819103
89819103
89879103
89619103
89879103
89879103
89819103
89819103
89819103

2
1
1
3
2

?
2

FCO CK676

2
2
3

2

2

2

2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
1

2
2
2
2
2
2
2
2
2
1
2
2

'}

2
1
2
2
1
2
1

1
7
2
1
2
1

Removed by

Removed by

FCO CK676

2
2
2
2
2
2
1
2

1

9-61

P4Gf! NO

8

FROM
06PIA06
06PIA06
06PIA07
06PIA01
06PIA09
06Pt A09
06PIAll
06PIA11
ObPl A12
06PIA12
06PIA13
06PLA13
06P1A14
06Pl A14
06PIA15
06PIA15
ObPl A16
06PIA16
06PIA17
ObPl Al1
06PIA18
06PIA18
06PIAL9
06PIA19
ObPI A20
06PIA20
06P lA21
06Pl A21
06PIA22
06PIA22
ObPl A23
06PIA23
06PIBOl
06PIBOl
06PIB02
06P1802
06PIB03
06PIBO)
ObPIB04
06PIB04
06Pl B05
06Pl B05
06P1B06
ObPIB06
06Pl BO 1
06P IB01
06PIB09
06P1809
06PIBIO
Of.tP1810
06PIB12

9-62

W

IR E

TO
07PIAOb
02PIA06
07PIA07
02PIA07
C7P1A09
02PlA09
C7PIA II
02P1A 11
OiPl Al~
01PtA 12
07Pl All
02PIAH
02PIA14
01PIA14
07Pl All)
02PIA15
07PIA16
02PIAl6
02P1A17
07Pl A17
01PIA 18
02PIAIA
02 PI A19
01PIA19
02PIA20
07Pl A20
07PIA21
02P"iA2l
02P1A22
07PIA22
07Pl A23
02P1A2l
07Pl801
02PIBOl
Q2PIB07
07PlBOl
02PIBOl
o 7PIBOl
02Pl B0407PIB04
02PIBOl)
07PIBOl)
C1PIB06
02PIB06
02Pl B07
07PIB01
07Pl BOq
02Pl B09
C7PIB 10
02PIBI0
01 Pl Bl1

l

I

Sf

SIGNAL-NAME
0.43*
OA3*
OA4*
OA4*
TP
TP
OA15*
OAI5*
00
00
02
02
04
Q4
06
06
08

08
010
010
012
012
014
014
WEZ*
WEZ.
READ*
READ*
REPl v*
REPl V*
PleT"*
PRTM*
OAl*
OAl*
OA2*
OA2*
OA1*
OA7*
OA8*
OA8*
OA9*
OA9*
OAIO*
OA10*
CHI*
CHI*
OA13*
OA13*
OAI4*
OAI4*
04

A B 1
W.l.
89879103
89879103
89819103
89879103
89819103
89819103
89819103
89819103
89879103
89879103
89879103
89879103
89879103
89819103
89819103
89879103
8981910·3
89819103
89819103
89879103
89819103
89879103
89819103
89819lQ3
89879103
89819103
89819103
89879103
89819103
89819103
89879103
89819103
89879103
89879103
89819103
89879103
89819103
89879103
89879103
89879103
89819103
89879103
89879103
89819103
898191G3
89879103
89879103
89879103
89879103
89879103
89819103

o

7/8

FR.lEV TO.lEV

1
2
1
2
1
2
1
2
2
I
1
2
2
1
1
2
1
2
2
1
1
2
2
1
2

1
1
2
2
1
1
2
1
2
2
1
2
1
2
1
2
1
1
2
2
1
1
2
1
2
2

1
2
1
2
1
2
1
2
2
1
1
2
2
1
1
2
1
2
2
1
1
2
2
1
2
"1
1
2
2
1
1
2
1
2
2
1
2
1
2
1
2
1
1
2
2
1

1
2
1
2
2

89633300

A

W I

9

PAGE Nl1

FI{OM
06PIA12
06P1813
06P1813
06P1 B14
06P1B14
06P1B15
06P1 B15
06PIB16
06 P 1B16
06PIB17
06P1817
06P1B1B
06P1 B18
06P1819
06PIB19
06PIB21
06PIB21
O()PIB22
06PIB22
06P lA23
06Pls23
01PIAOl
07PIAOl
07PIA02
07P lA02
07PIA03
07PIA03
01P lA04
07 PI A04
01Pl A05
01PIA05
07P1A06
07PIA06
01PIA07
07PIA07
07PtA09
07PIA09
07PIA11
07PIA11
07 PI A12
07PIA12
01P1A13
01PIA13
01PIA14
07PIA14
07Pl A15
07PIA15
01P1A16
07P1A16
07PIA17
07PIA11

TO

C1PIAIJ
01PIRl1
02P1B1~

02P1B14
07Pl R14
02P1B15
07PIB15
07PIB16
02P181b
07Pl Bl1
02PIB11
02P181R
07P1 BIR
07PIIHQ
02PIBl9
02PIB2t
07P1B21
02P1B22
C7PIB22
02PIB23
07 P182~
06PIAOI
13PIBIQ
13Pl A1q
06PIA02
06PIA03
13P1829
14P1BIQ
06Pl A04
06PIA05
14PIA20
13PIB2t
06PIA06
06PIA07
13PIA20
15PIA09
06PIA09
06P1A 11
14PIA1Q
12P1B31
06PIAlJ
06P1A13
lSPIA13
15PIAl4
06P1A14
061>1 APi
15P1All)
15PIAlb
06P1A16
C6P1A11
15PIAl1

89633300 C

R E

l

I

S T

SIGNAl~NAME

01
03
03
05
05
01
07
0<;
09
011
011
013
013
015
015
wRITE*
wR[ TE*
REJ EeT*
R F. J EC T*
Me*
Me*
OA5*
OA5*
OA6*
OA6*
OAO*
OAO*
OA12*
OA12*
OAl1*
OAll*
OA3*
OA3*
OA4*
OA4*
T.P.
TP
OA15*
OA15*
00
00
02
02
04
04
06
Q6
08
08
010
010

A S 1

W.l.
89879103
89879103
89879103
89879103
89879103
89879103
89d 79103
B9879103
89879103
89879103
89879103
89879103
89879103
89879103
89819103
89879103
8<;879103
89879103
89879103
89819103
89879103
89879103
89879100
89879100
89879103
89819103
89879100
8<;879100
89879103
89879103
89879100
89879100
89879103
89879103
89879100
89879100
89819103
89879103
89819100
89879100
89879103
89819103
89879100
89879100
89879103
89879103
89879100
89379100
89379103
8987910.3
89879100

o

7/8

FR.LEV TO.LEV
1
1
2
2
1
2
1
1
2
1
2
2
1
1
2
2
1
2
1
2
1
1
2
2
1
1
2
2
1
1
2
2
I
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1

1
2

1
1
2
2
1
2
1
1
2
1
2
2
1
1
2
2
1
2
1
2
1
1

2
2
1
1
.2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1

1
2
2
1
1
2

9-63

PA(;E "IJ

10

FROM
07PIA18
01PIA18
C7Pl Al 9
07P1A19
07PIA20
01P1A20
01P lA21
07Pl A21
07PIA22
01P1A22
07PIA23
01P lA21
07PIBOI
C1PIBOl
07P1802
01PIB02
O'1P 1803
01P1803
01P1801t
07PIB04
01PIB05
01Pl805
01P1806
01P1806
07PlB01
07PlBOl
01P1809
01P1809
07P1810
07P1810
07P1812
07P1812
07P1813
01PIB13
07P181.4
01P1814
01P 1815
07P1815
01P1816
01P1816
07P1B17
07P1817
07P1818
07P1818
01P1B19
01PIB19
07PIB21
01P 1821
01P1822
01P1822
01P 1823

9-64

W IRE
TO
15PIA l~
06Pl A18
Ot-Pl A19
15PIAIQ
12P2A21)
Ot-Pl A20
06PIA 21
12P1B2\0(,
10P1~18

08P;'. AOQ
tlP1Alli
11 PI 8')1
1lP1B11i
10P1428
08 Pl 829
08P2826
10PIA30
10P1A:n
08P2421
10P1BOt
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I1P1B08
09Pl ADI
11 Pl R20
08P1A26
10P1 8 24
08PIA23
10P11321
08P1/H4
10PIB ~o
OSP2S14
08P2fH5
.08PIA28
10P2406
OSPI 411
o ap lAO 1
lOP2 A07
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0$JP2806
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10PlA22
oaPt AI'
08PIA30
IOP2A2()
OAP1A19
IlPlS19
UPl B06
08P2B20
10P1401
08P? 811
OAP2B07
08Pl831
OSPI1Hl
10P280'l

A

R E

l

I

S T

SIGNAL-NAME
ABCNE
A8 PRESET
AI: PRI:SET
PkOIN 4
PRDOUT 3
PPIN 3
AS DOT
AB COT
02*
02*
01*
01*
PC2
PRTV GN B4*
PROCUT 6
GND
PwOUT 4
012
012
PRF8
PRF B
AS RENAelE*
AB RENAI:UE*
BS1*
BC2
B IIRES(l-4t
AB CLOCKOUT
AS CLCCKOUT
WClK
WClK
PRTV GN 82*
B NOENV(Z)
PPOOUT 4
AS PARITY
A8 PARITY
pp, N 4
PRTY FN Bl*
AB TOG
AS TOG
B NOENV ( U
AS CA TA
AS DATA
PWOIN 6
P~DOUT 2
BCNEF*
PC 1600*
BCl*
B SKEINCVf F
R POSTABLEF
ABkRESCS)
AB~RES('j.

A 13 1
~.L

•

89819100
8'1.]19100
89879100
89,i 19100
89319100
898791UO
89979100
89879100
89879100
8~H 79100
89879100
89819100
89d 19100
89319100
89879100
89879104
89879100
89819100
89879100
89879104
89879100
89879100
89CJ79100
89;]19100
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89919100
89879100
89879100
89819100
89379100
89879100
69819100
89d 79100
89879100
89879100
89819100
89879100
89819100
8911 79100
89879100
89819100
891379100
89319100
891319100
89879100
89819104
89819100
89819100
89319100
89819100
89879100

o

118

FR .LEV TO.LEV

2

2

1

1

2

2
2

2
2
1
1
2
I

2
2
1
1
2
2

1
1
Z
2
2
1
2
2
2
1
7
1
2
2
2
2
1
2
2
2
1
2.
2
1
2

2
2

2
2
2
2
1
2.

2
1
1
2
1
2
2
1
1
2
2

1
1
2
2
2
1
2
2
2
1
2
1

2
2

2
'2
1
2
2

2
1
2
2
1
2
2
2
2
2
2
2
1
2

9-67

PI\GE

NO

14

FR1M
09Pl B10
09P?812
09P2823
09P2826
09P2830
10PIAOI
10PIAOI
10PIA02
lOPIA03
IOPIA04
10PIA05
10PIA01
10PIAIO
IOP1All
IOPIA12
10PlAl]
IOPIAI6
10PI AI1
IOPIA18
10Pl A20
10PIA21
10PlA23
lOPIA24
lOPIA25
I()PIA26
lOPlA21
10PIA28
10PIA30
10PlAli
10Pl801
lOPI.B02
IOPtB03
IOPl806
10PIBI9
lOP1819
10PIB20
10P1820
lOP1823
10PI824
lOPIB2§
lOP 1826
1()P1827
10P1828
10 P IB10
lOP2A02
10P2A04
10P2A05
lOP2A06
10P2A07
10PlAOl
IOP2A08

9-68

WI R F
TO
11 P2 All
I1P1810
IlP2B24
II PI A14
08P2A 10
09P2BOI
13p2801
IlP2B09
OAP2B04
09PIA04
11PIAI6
ORP2 A12
11P2R04
09PI A11
II PI All
08P282A
08PIB2r;
09PIA11
09PIAIA
I1PIA09
IlPIB09
11PIB14
08Pt All
OAP2821
08Pla2"
08P2 All
D9P1A2A
09Pll\30
09PIA31
09P1801
08P2A27
08P2A04
IIPIBOI
20Pl AOt
05PI81A
16P280A
05P181Q
IlP2!:lOA
09PIB24
OSPl827
OSP2A07
09PIB21
lOP2BOl
09P1830
08P2 Al r;
08P2B 11
08PIAl1
09P2 AO'IlP2821
09P2A01
C8P'- A2A

LIS T

A a 1

SIGNAL-NAME

w.l.

PWOUT 3
PhOIN 3
P~OUT 6
PPIN 2
R READY F
PC 1600*
PC 1600*
·P .. OUT 0
AftfOENV(4)
AS DEN
PWDIN 0
ANOOROPOUT(
PRINP
AS LOI
PPIN 5
PRT" GN A3*
ANDENVC 3)
ASONE
AS PRESET
PWDIN 1
PROOUT 7
PRIN 7
A PCSTAMBlE
PR1Y GN A5*
AENV( 5 J
ASYNC(4)
AS DOT
02*
01*
PC2
PRTV GN AIt*
AENV(4)
PRODUT5
AUTOLOAD
AUTOlOAO
AUTOLOAD
Al!TOLllAO
P.OLT 1
012
ANOENV(5)
A.Sl1AOI
12 PI A02
12PIA03
12P1A04
12P1A05
12P1A06
12PIA08
12P1A09
12P lA 10
12PIA11
12PIA12
12PIA13
12P1A14
12PIA14
12PIA16
12PIA17
12PIA19
12P1A19
12P1A20
12P1A20
12PIAl1
12PIA23
12PIA24
12P1A25
12PIA26
12P1A27
12 PI A28
12PIA30

II

I

Tl
1 OPt AD'
o AP2A 20
14PIB06
12PIBO'>
09P lAO?
13P2 A22
13P281A
12P1 A24
13P2 Al ~
10P2 B2 3
13P2 A06
09P1823
10P2810
10P2 BOR
09P2 q23
08P2A}1
ORPt AI!}
10P2A01
14P2 A22
12P2631
12P14 Jl
13P2At'i
1 QPl A09
05P11317
14P2413
13P2814
13P1402
13P240'
08P2B24
11p1A27
14PIBll
14P2414
13P2BIO
13 P2 B09
11P2AO'>

RE

l

I S T

SIGNAL-NAME

W.l.

p .. our 0
SFM*
TTONlINE*
ISTSP
PWnUT 2
RWl n RwUNlO
FM/TM
EDRS
PAR ERR.
PwOtJT S
WR I TE CLOCK
P~OUT 4
PLotOlJT 7
PWOUTP
P'-'OUT 6
PRSIROBE
PWRESET
WClK
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R \1B03
13Pl 60 3
llP1B04
131> 1 B04
13Pl B05
13PIBOS
13P1B06
13P1806
13P1B08
13P1 B08
13P1809
13P1809
13PIB10
13Pl 61 0
131> UHO
13P1812
13P181Z
13P1B12
13P1813
13P1813
13P1813
13P1B14
131> 1814
13P1815
13P1815
131>1815
13P1816
13P1817
13 P UH8
l3P1B19
13PIB19
I1P1820
13P1 B2 0
13P1821
13PIB21
13PIB22
IlP 1822
13 Pl 823
13P1S23
13P1824
13P1825
13P 182 5
13PIB21
13P1828
13P1B29
13P1829
IlP1 830
13P1811
13P2AO 1

TO
11PIA04
14P1 AD'
lZPl Be 1
14Pl AO~
14Pl BOft
11P1AOA
lAPI A02
C5PIB2'-l
11PIB04
14P1 AO~
18P1AOQ
05P1827
12P2B19
14PIAOQ
Z1PIA05
05p1 BO'
ISP282fl
18PZAZ'i
C5P1A06
Z1P1B06
27Pl AOR
05PIAOt
18P2B24
12Pl B20
14P1814
27PIAJ7
18P2 A23
Or;P1A07
11 PI A20
l4P1A17
lZP1BOA
07 PI ADI
l5PIAOl
15P1803
01P1801
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15Pl AOt)
12P2 A09
141> lA 21
lAPI AOA
05PIB26
12Pl A30
18PIA06
05PlB31
I1PIB26
lZ P2 B10
01PIAO'-l
15PIA03
C8P2 BOQ
OBPI A03
12P2AO~

R E

L I S T
S'GNAL-NA~E

RCTAP E
RCTAPE
TRANS*
TRANS.
R[TAPE
ROT APE
SAO
SAO
R CTAP f
~CTAPE

0
0
7
1
4
4

SA4
SA4
LCLWA*
LOlWA*
SOZ
S02
S02
S03
S03
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sos

505
505
BUF 1/0*
8UF 1/0*
S04
SD4
S04
WRT ~PE 4
CARCURAO*
(NCCA*
OA5*
OA5*
OA1*
OA1*
OA3*
OA3*
STR8Uf*
STRBUF*
SA3
SA3
9T*
SA1
SA7
WRTAP E Z
BUSY
OAO*
OAO*
PE LOST CAT
PE ENABLE
CONTACT*

A B 1
w.L.
89d 19100
89819100
aS879100
89:319100
89819100
89819100
89879100
89819100
89819100
89819100
89819100
89819100
89379100
89879100
89319100
89819100
89819100
89819100
89819100
89879100
89879100
89879100
89879100
89819100
89879100
89819100
89819100
89819100
89879100
89879100
89819100
89819100
89819100
89819100
89319100
89819100
89319100
89d 19100
8<;819100
89319100
89819100
89819100
89819100
89879100
89879100
89319100
89819100
89379100
89819100
89879100
89819100

o

118

FR.LEV TO.LEV
Z
1
Z
1
1
Z
1
Z
Z
1
1
Z
2
1
1
2
3
3
2
1
1
2
3
2
1
1
3
2
2
2
2
Z
1
1
2
2
1
2
1
1
2
Z
1
2
2

2
2
1
2
2
2

Z
1
2
I
1
Z
1
Z
Z
1
1
Z
Z
1
1
2
3
3
2
1
1
2
3
Z
1
1
3
2
2
2
2
2
1
1
2
2
1
2
1
1
2
2
1
2
2
2
2
1
2
2

2

,,~~

89633300

A

9-75

PAGE NJ

22

FROM
13P2A02
11P2A05
13P2A05
IlP2A06
13P2A06
13P2A07
13P2A07
13P2 A08
13P2A09
13P2A09
13P2 AlO
13P2A II
13P2A12
13P2A13
IjP2AI3
13P2A14
13P2A15
13P2A17
13P2A18
13PlAI8
13P1A19
13P2A20
13P2A20
13P2A21
13P2A22
13P2A23
11P2A24
13P2A25
IlP2A26
13P2 A26
13P2A21
11P2A28
13P2A28
13PlA29
13P2A30
13P2801
13P 2802
1.3P2.803
11P2B04
13P280S
13PlB06
13P2B06
13P2807
13P2808
13P?809
l3P2BLO
13P2811
IlP2812
13P2Bl1
13 P 2813
11P2814

9-76

W IRE

TO
12PIA05
OSPlalS
14P2 AI1
11P2BIQ
12PIBIO
l2P2At'S
14PIA.Ji
14Pl A30
12P2RO'
14P2A04
12P2B09
12P2RIR
12PIB04
14P2801.
12P2A08
IlPIA11
11P2 B31
12P2Al1
14P1823
I1p2811
14P2A24
12Pl A23
14P2830
ORP2A24
I1P2814
12PIA 16
ORP2 A21
l'P2Rl'S
11PIAl8
14P2Ali
14P281l
14P2BO'S
12P1819
08P2A14
OAPl813
L4P2 81 9
12P2Al'
14PIB30
12Pl1311
IlPIBO'S
14P2823
OSP1ao,
10Pl AOt
08P2812
12PIAl'
12PIAll
21 P2 Al7
IlPIA30
lZP1S0&
14Pl B1 ~
12PlAOl

lIS T

A

I}

SIGNAL-NAME

W.l.

ClR LOwER*
WREOUEST.
wREQUEST*
~RI TE CLOCK
WRITE CLOCK
STRUS
STRUS
WPfNABlE
MC*
MC*
STRINT
RFS1*
LOST tArA
fOP
EOP
BCD
MODESEl*
READY
P"R ERR.
P"R ERR.
TTDENSTAT*
CSA W~EN.
DSA WREN*
Al2
RhlC RhUNlO
lOS r DATA.
151PS
PPOTECTED
9T
9T
lJ SI
RES2*
RES2*
PECHARClK
PEClOCK.
eOT
lEGl S
IllUSCOOE
STRCC
1600
PE ST~RT
PE ST~RT
PC 1600*
PE WOJ(NING
wCS SHIFTED
EARL Y wDS

89879100
89879100
89879100
89879100
89879100
89879100
8~8 79100
89879100
89879100
89879100
898"79100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89379100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89819100
89819100
89879100
89819100
89819100
89879100
89879100
89879100
89819100
89879100
d9879100
8Q8191UO
89879100
89879100
89879100
89819100
89879100
89819100
89819100
89879100
89879100
89879100
89819100

MC*
2FWC
AID

AID
DATA

1

o

7/B

FR .lEV TO.lEV
2
2
I
1
2
2
1
2

'-

1
2
2
2
1
2
2
1
2
2
1
1
2
1

'-

1
2
2
2
2
1
1
1
2
2
2
1
2
2
2
2
1
2
2
2
2
2
3

'-

2
1
2

2
2
I
1
2
2
1
2
2
I
2
2
2
1
2
2
1
2
2
1
1
2
I
2
1
2
2
2
1
1
1
1
2
2
2
1
2
2
2
2
1
2
2
2
2
2
3
2
2
1
2

89633300

A

P4GE NO

WI R E

23

FR)1It
13P2815
13P2B16
13P2816
13P2817
13P2B17
13P281A
13P2818
13P2819
13P2820
13P2B20
13P2B22
13P2B23
1JP2B24
13P2825
13P2B26
1}P7B26
13P2B27
13P2B28
141>10401
14Pl A02
14P10403
141> 1A04
14P1A05
14P1A05
14P1A06
14Pl AO 7
141' 1408
14Pl AOA
14PIA09
14P1A10
14P1AIO
14PIAIO
141> 1 All
14PIA12
14PIA12
14PIA12
14PIA13
14PIA14
14PIA14
14PIA14
14P1A15
Ilt-Pl A15
14Pl A15
1.41> 1 A16
14P1A17
14Pl A18
14P1A18
14PIA19
14P1A19
14PIA20
14-PLA20

TO
12P?B16
12P2829
14P2A lq
14P2479
12P1417
14P1B24
11 P2 fH I)
14P2042~

12PIB2R
14P2B2Q
12Pl1316
141'2 B27
12P2A30
14P2B2R
14 P2 Bll)
12P2831
14P2 B09
14P2A2R
13P1S01
13P1 B07
13 Pl BO'l
13PIA04
lAPl407
e5PIA2}
13P1B06
12PIB26
lAP1BOI.
05Pl A27
13PIB09
lSP2A30
05P1B06
21Pl 8 18
11PIB27
27PIA1A
05PIA05
18P21331
11 PI B20
21PIo4IQ
18P2830
05Pl All
05PIB 10
1AP2 A2CJ
l7Pl B2~
I1PIB25
13Pl 811
01PIROQ
151>1809
15PIAll
C1PIA 11
01PIAOl)
15Pl AOI)

89633300 A

L 1ST
SIGNAL-N4ME
I NT
TM3
TM3
REO*
REO*
FM/TM
FM/TM
TTREAO't'*
ENA*
ENA*
ALl
EOT*
TMI
G~P CLOCK
RwLO*
R~LO*

USO
TT REAO,(
ROT APE 3
ReT ~PE 0
TRANS*
ROTAPE 6
SAA
SAa
RCTAPE 4
RES1.1*
SA12
SA 12
lOLWA*
5010
5010
SOlO
WRTApE 11
5011
5011
5011
WRT~PE 13
5015
5015
S015
5014
5014
S014
WRTAPE 14
CARCURAot
0~13*

nA13*
OA15*
OA15*
OAl1*
OAl1*

A B 1
W.L.
89379100
89879100
89379100
89879100
89879100
89a 79100
89879100
89879100
89379100
89879100
89819100
89879100
89879100
89379100
8 1 B18
15P1B18
15Pl R19
15 P IB19
15PIB2I
15PIB21
lSPIR22
15PIB22
I SP 1 B? 2
15PIB23
15PIB23
15P IB23
15P2AO 1
lSP?402
15P2A04
ISP2A05
15P2406
15P2AQ7
15 P'- Aoa
lSP2A09
15P2A09
15P2AI0
I5P 2AIO
15 P2 All
15P2A12
15P2A13

89633300

VI

,

TO
13PIB20
14P1B2Q
1 9Pl A1';
19PIA11
14P187]
14PIB20
19PIAl4
70 P2 B25
12P1821.
14PIAIR
19P1 A07
19P 1 ~ ot
14PlBIR
l2P2AOl
C7PIB17
07Pl Bl1
25P180Q
20P2Bl'i
01 PI B14
C1PIB15
12p2A24
L2P2 A;n
07Pl B 16
07PIB17
26Pl R09
26P2B2A
07PIBIA
07PIBIQ
26P2BOI
12P1830
19P2B3t
01PIB2l

R E

l

r

S T

SIGNAL-NAME
OA1*
OA8*
OA8*
OAQ*
OA9*
OA10*
OA 10*
CHI*
CHI*
OA13*
OA13*
nA14*
OA14*
01
01
03
03
05
05
07
Q1
09
Q<;

011
011
013
013
015
015
WRITE.
WR I TE*
R EJ EC T*

I2P2Al~

~fJECT*

1 Qp IBOl
16P2 B07
07P1821
25PIB20
LSPl B05
lQPIAlf,
16P2AOA
19P1 A24
16PLB04
19P2 A30
18 P2 A2'
12P2R21
20P2814
2 QPl SIS
12P2f}2'
IbP2A09
1 7P2 Al 7
17P2B20

REJECT·

A

Me.

P4C*
MC*
SElO.UTPIIO
SE.U.PRT.
US3*
Of-GATED
UlT.S~C.PFO

BUSY RR*
C 1A6
08
08
010
010
US2*
A13
All

A ti 1
.... l.
898791UO
89819100
89379100
89879100
89d79100
89879100
89979100
89319100
89879100
89879100
89819100
89379100
89819100
A9879100
89819100
89879100
89879100
8<;d79100
891379100
89379100
89819100
89879100
89879100
89d 19100
89879100
89879100
89879100
89879100
89879100
89879100
89d 79100
89819100
89879100
89879100
89819100
89879100
89879100
89879100
89879100
89879100
89d79100
89879100
89879100
89879100
89879100
89679100
89d 79100
89819100
89879100
89879100
89819100

o

7/A

FR .l EV

1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
3
1
1
2
3
2
2
1
2
1
1
2
2
1
1
2
1
2
2

TO.l EV
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1

1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
3
1
1
2
3
2
2
1
2
1

1
2
2
1
1
2
1
2
2

9-81

P4GE NO

28

FROM
lSP2A14
lSI> 2A1S
1'5P2A16
I'5P2A11
15P 2A18
15P2A19
15P2AlO
15P2A21
15P2 A2l
15P2A23
15P2A24
15 P2 A25
15P2A26
15P2A27
15P?A28
ISI>2429
15P2BO 1
ISP2B02
15P2B03
15P2B04
15P?R05
15P2B06
lSP2R01
15P2B08
15P2809
15P2B09
15P2B10
15P2BI0
11)P7.Bll
15P2R12
15P2B13
15P2B14
15P2B15
15P2B16
15P2B17
15P2B18
15P2819
ISPZ820
15P2B20
15P2B22
15P2B23
15P2B24
15P?825
15P2826
15P2B21
15P2828
15P2B28
15p2828
15P2829
15P2sJO
l'iP2B31

WI R E
TJ
1 7P2 A04I1P2Rl1
17PlA21
18P2 RO~
16PIB31
19P1 R01
19P2BIO
16PIA20
17P2802
11P2AOit
19P1827
19P1 A21
16P2AOh
16PlA02
16PIB21
19P1 A09
15P2B20
16P2 B0416P1B29
18PIA19
I1P2814
IhPIA06
19P2 A2B
16P2A01
20P2A06
12 P2 Al~

12P2Al1
20P2A16
16PZ A1417P2A lit
17 P2B19
17P2415
17P2B01
17 P2 AOA
I1P2B1?
16PIA19
16Pl A21
16P lA 77
15P2 BOt
16Pl Al416PIB21
19P2A01
1 QPl A2')
16P2A04
16P2 AOI

L I

S T

'5 (GNAL-NAME
AO
A~

AI0
C A6I)M*
A/O

ClE~R

ECU .NUM.MAT

FCKM
T.E.O ALTOL
A2
A3
scn SEO
SCOSE2
SEa SCI *
SEa SC3*
AOAF+MC*
AOOR ERR
RESCTRBSV*
LA OIFF=O*
EOPMC T B5 v*
S ET • ACDR. ER
AS
READ
LA
US4*
01
07
09
09
US1*
All,
A12
A15
Al
A1
AI,

MC
TAS EXT.
RESC TRB5Y*
R fSCTRBSY*
TDl
I NCR 1A
SCOSE 1
SCOSE3
SEa SC 2*
SEOSC4*

21P2A2~

PRT~O*

12P2A19
15Pl A2~
16PIB20
16P182,)
16Pl A2~

PRTAQ*
PRT ~O*
T02
ADOR. ERR *
CTRlR BlSY

A B 1 o 7/8
W.L.
89819100
89879100
89819100
89819100
89879100
89819100
89819100
89879100
89819100
89879100
89819100
89819100
89819100
89819100
89<319100
89819100
89819100
89819100
89819100
89819100
89319100
89819100
89819100
89819100
89819100
89a 19100
89319100
89819100
89819100
89819100
89819100
89879100
89879J.00
89819100
89879100
8C;879100
89319100
89819100
89i 19100
89879100
89879100
89879100
89819100
89819100
89319100
89819100
89879100
89819100
89879100
89819100
89819100

FR.LEV TO. LEV
2
2
2
2
2
1
1
2
2
1
2
2
1
1
2
1
2
1
1
2
2
1
2
1
1
2
2
1
1
2
2
2
1

2
2

2
1

1
2
1
1
1
1
1
1

1
2
3
1
1

1

2
2
2
2
2
1
2
2
2
1
2
2
1
1
2
1
2
1
1
2
2
2
2
1
1
2
2
1
1
2
2
2
1
2
2
2
1
1
2
1
1
1
1
1
1
1
2
3
1
1
1
~i

I

\

9-82

89633300

A

PAGE NO

29

FROM
16P lAO 1
1&PIA01
16PlA02
16PlA03
16Pl AO 1
161>1A04
16PIA05
16PIAOb
16PIAOb
16PIA07
16PIA08
16P 1 A08
16PIA09
16PIA10
16PIA10
16PIAll
16PIA12
16PIA13
16PIA14
16P lA14
16PIA15
16PIA16
IbPlAl1
16PIAl8
16PIA19
16PIA19
16PIA20
l6PIA21
16PIA22
16PIA23
161> lA25
16P1A26
16Pl 426
16P 1 A2.1
1~PIA27

l6PIA21
16PIA28
16PIA30
16PIA31
16PIB01
16PIB03
16P IB03
16PIB04
16PlB05
16PIB05
1,PIBOl
16PIB08
l6Pl B09
16PIB1O
16PIB12
16Pl8l3

89633300

W

t

R E

TO
12PIA20
27 P2 A2A
17PlfH9
17PIB2Q
12 P2 Al A
12P2B 21)
18P1All
15P2 BO"
17PIB30
18P2B04
17PIA14
15PIA 31
17Pl BI0
12PIA14
27P2BIA
11Pl B01
I1P2B 11
18P2AIA
1 7Pl B28
15P2B22
18P2 B21
1 7p 1 B 11)
17P2A21
17PlA12
11PIA?2
15P2B18
15P;JA21
15P2B19
19P2A18
18P2 A01
19P2B2Q
15P2B31
19P2 A08
19P2B19
19P2 Blq
15P2B20
19PIB30
1 QP2 A1 t.
19P2A15
12P2A27
12PIB2l
27P2A 1 q
15P2 A06
21PIB31
12PIAlQ
19PIA24
lAPlA21
17Pl A11
I1P2 A1ft
17Pl B 31
11P 1 Al4

A

l

A 8 1 07/8

I S T

SIGNAl-NA'-E
SRQ*
sa;o*
W+C

SPl*
SPJ*
SCF 00 ( SC F I M
REQUEST.
READ
READ
DSA-BUffl·
Bl=O
Bl=O
CAl-SHlfT*
SRSM*
SRSM*
RESUME
T04
SMP}(Q
TOI
TOI
BUFFIBUFF1·
BUFFI-BUFF2
T03
SET NfFO*
Me
MC
T.E.D AUTOl
TAS EXT.
LOST [ATA
Bt>CVL
SET ALARM*
CTRLR BUSV
e TRLR BUSV
RESET C TR B
RESET CTR B
RESCTRB5V*
OaF-LA-AUTO
SET eTR SEE
T01*
SCROD ( SCR 1M
SS*
S5*
ULT.SRC.PJCO
S wRITE*
S WRI TE*
nSA eeNNECT
wRITE EN.4el
SHIFT-8UUFl
I NHI BIT NEE
16B ( T 5. C 11
CAU SHIFT.

~

.l.

89d 19100
89319100
8987 17PIA24
17PlA25
11PIA27
17PIA28
17PIA30
17Pl A31
17PlA31
17PIB03
17PIS06
17P1807
lIP IB09
l l P 1809
17PlB10
17PIB14
l1PIB15
17PIBl6
17PIB17
17PIBl8
17PIBl9
1IPIB19
IIPl B22
17P 1824
17 PI B2 7
17PlB28

16Pl AOA
19P2AOq
,l8PlS31
19P1 A21
19P2A 13
19P2S20
18Pl BI0
16PIB20
18PIB2e;
16PIA19
16PlS13
19P2 A29
18P2All
19PIA21
19P1 B21
l8PIA13
16P1B09
18P2 BO,
18P2Al6
19P1 B29
16PlAll
19P2S03
16 PI B21
16PIA09
18P2B 13
16PIAl6
19P2All
18PIA27
16Pl Bl,
16PIA02
18P2A19
18P2817
19P2A Oc;
16P2B16
16PIA14

BL=O
DOf-LA
OOf
INtT
CLEAR CKWD*
READ OA TA
T02
TD2
MC
MC
CAU SHIfT*
CAU SHIFT*
SECTOR GATE
W.CKWO*
INPUT CKWD
BL-BORAOW*
SHIFT-BUUFI
SHIFT-BUUFI
515
CKWO SHIFT
RESUME
AOAf+MC*
AOAF+MC*
CAl-SHIFT*
DATA
BUffl-BUFf2
C(MPARE
Bl-LOAO.
BUFF2 fULl*
W+C
W+(
CLEAR-SHIfT
CKWOll
WRITE t~T~*
TOI

89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89819100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89a 79100
89819100
89379100
89879100

I
1
2
2
1
I
I
2
2
I
1
2
2
2
2
1
I
2
2
2
2
2
1
2
2
2

I
I
2
2
I
1
1
2
2
1
1
2
2
2
2
I
1
2
2
2
2
2
1

17P1A25

19P2B15

SECTOR GATE

89879100

3

>

16P2825
16P2B26
16P2B27
1bP2B28
16P2B29
1&P2B30
16P2B 31
17PIA04

18P2B09
19P2Bll
18P2 Bll
18P2 Al 0
IAP2Aoe;
18P2AOl
18P2BO~

89633300 C

2
2
1
I
2
1

2
1
2

2
2
2
2

2
1
1
2
1
2
1

2
3

LENGTH 99-85

PAGE NO

32

FROM
I1P1829
I1P1829
I1P1810
UP1830
17P1831
17P2401
17P2401
I1P'-A02
11P2112
I1P2404
17P~404

17P2A05
17P2·406
17P2406
I1P2407
I1P2408
I1P2408
I1P2A09
I1P2410
I1P2Ali
17P2A11
I1P2412
I1P2A12
I1P2413
I1P2411
17P2414
17P2A15
I1P2A15
I1P2A16
l1P2A16
I1P2411
17P2Al1
11P2A18
I1P2A19
11P2A19
11P2A20
I1P2A20
I1P2A21
I1P2A21
17P2A22
I1P'-A23
I1 P 2423
11P2424
I1P2425
I1P2A26
I1P2427
11P2421
I1P2428
I1P2801
17P2S02
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16PIAO'19P2Al t
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19P182'20P2820
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19P281it
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19P181A
20P2A21
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OA9*
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A14
A14
A13
A13
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A10
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89879100
89819100
89819100
89879100
89819100
89819100
89819100
89879100
89819100
89819100
89819100
89879100
89379100
89879100
89819100
89819100
89819100
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89379100
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89819100
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SAil
SA13
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SA7
SA8

89879100
89919100
89tJ19100
89819100
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89979100
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181»1A12
18PIA13
18PIA14
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l8PIA16
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18PIA18
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181»1A20
18PlA21
18PIA22
181»1423
18PIA23
18PIA24
18PIA25
18PIA26
18PIA26
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lSPIA28
181»1A30
18 PI A31
18PlA31
18PIBOl
18PIBOI
18PIB02
18PIB02
18PIB03
18PIBOl
18PIBOit
18P1B04
18P1B05
18PIBOS
18P1806
18Pl806
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18P1807
18PIB08
18P1808
18P1B09
18P1809
18PIB10
18P1812
18P1813
18 P IB14

>18P1All
9-88

W I R E
TO
14P1 A05
13PIB 23
28PIA06
28Pl B09
13PIBOA
19PIBIO
16PIA05
19PIB13
17PIAlO
19P2B04
19P1 A31
19P1 All
19PIB20
19PIB04
15P280417P2B 13
19P1 A21
19PIA 18
19P2A27
17P2B12
17P2A09
17P2A04
I1P2B02
19P2A19
I1P1817
11P2 All
I1P2B19
19P2A26
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14PIA08
28Pl B21
28PIA26
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13Pl A21
28P2B25
28P1A30
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19PIA04
13PIA09
28PIA2l
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14PIA22
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28PIA09
13P1A26
19P181419P1412
I1P2AI;
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18P2BOl

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CACWAI0
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A13
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89879100

1

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7/8

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3

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LENGTH 8"
89633300 C
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PAGE NO

W I

35

FROM

lAPIA15
18PIBI6
18PIB11
18P1818
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18P1820
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18P2A23
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18P7A26
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18P2A29
181>2A30

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14P181 c;
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18P1All

89633300 C

R E

L 1ST

A B 1

SIGNAL-NAME

W.l.

CAC wA 13
CACWA2
CAe WA14
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C "A-CGUNT.
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89819100
89879100
89879100
89879100
89879100
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89819100
89879100
89879100
89819100
89879100
89879100
89819100
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89919100
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89879100
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o

7/8

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1
2
2
1
1
1
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1
2
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2
2
1
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2
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1
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3
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3

LEKGTH 8"
9-89

PAGE

~()

36

FROM
18P2802
18P2802
18P2B03
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S (GNAl-NAME

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18P2B06
18P2B06
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18P2B08
18P2B09
IS P 2810
18P2B11
lSP2B13
18P2B16
ISP2B17
lSP2B19
18P2B20
18P2B20
18P2823
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18P2B25
18P2B26
18P2B21
18P2828
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18 P2830
18P2S31
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17P2A2'l
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21P2B30

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19PIA06
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19PIA07
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o 118
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2
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3
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TO~lEV

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2
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1
2
2
1
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2
1
1
2

LENGTH 14"

89633300 C

31

PAGE NO
FROM

19P1A16
19P lA17
19P1A17
19PIA18
19PIA19
1:}PIAI9
19PIA20
19PIA21
19PIA22
19PIA23
19PIA24
19P1 A2 S·
19P lA26
19P1 A26
19P1A~1

19PIA28
19PIA28
19PIA30
19PIA30
I~PIA31

19PIBOI
19P1801
19PIB02
19PIB02
19PIB03
19PIB04
19P lB05
19P1 BOl
19PIB07
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19PIB09
19P1S10
19P1812
19PIB12
19PIB13
19PIB14
19P1B15
19PIB16
19PIB16
19PIB17
19 P1 B18
19PIB18
19PIB19
19P1 B20
19P 1B21
19P1822
19PIB23
19P 1824
19PIB24
19PIB25

W I

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15P2 AO~
15PIA 02
17P2809
1 API A2l
15PIAOI
11P2 BI0
16Pl B 30
18P1A21
15 P2 825
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17P2B06
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1 7Pl A27
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20P2 A05
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15Pl B22
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15P2A19
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15P2A29
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89633300 A

R E

II S T

SIGNAL-NAME
SE.U.PRT.
OA6*
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CACWAA
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SAMPLE CHEC
INPUT CI379100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89379100
89879100
8Cid 79100
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89819100
89879100

o 7/8
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9-94

89633300

A

(

PAGE NO

W I R F

41

TO

FR'M
20P2 BOb
20P7B06
20P2B07
20P~R07

20P2808
20P2808
20P2B12
20P2B12
20P2Bl1
20P2813
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201>2B15
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20P2619
20P2819
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20P2B22
201>2822
20P2R2:i
20P~B23

20P2824
20P2B24
20P2825
20P 282 5
20P2626
20P2 82 6
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21P 1 AO 1
21PIA02
21PIA03
21PIA05
21PIA06
211>1A07
21PIA08
21PIAOq
21P1AI0
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71P1A14

19P2831
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89633300

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118

FR.lEV TO.LEV
1
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9-95

PAGE NO

42

FROM
21PlAl5
21PIA15
21PIA16
2lPIA17
ZlPIA17
2lPIA18
21PIA19
21PIA20
21P1AZI
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21PIB20
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21P1828
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9-96

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20P2B04
22P1820
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l

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o

118

FR.lEV TO.LEV
2

1
1
1
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89633300 A
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PAGE NO

43

FROM

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21P1631
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21P2A04
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21P2A08
21P2A09
21P2AIO
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21P2A13
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2LP?A14
2LP2A14
21P2A15
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21P2A11
21P2A18
21P2A19
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21P2A22

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89633300 A

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9-97

PAGE NO

44

FROM
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21P2B21
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21P2B25
21P2B26
21P2B27
21P2B28
21P2829
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22PIAOI
22PIA02
22PIA03
22PIA04
22PIA05
22PIA05
22PIA06
22PIA07
22PIA08
22PIAIO
22PIAll
22PIA12
22PIA14
22PIA15
22PIA17
22PlA18
22PIAI9
22PIA19
22P 1A20
22Pl A21
22PIA22
22P1A23
22PIA24
22PIA25
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22PIA28
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9-98

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TO
20P1822
22 PI AI0
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25Pl A04
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21P2814
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89819100
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o

118

FR.lEV TO.lEV
I
I
1
2
1
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1

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LENGTH 11"
LENtnH 7"

LENGTH 141l
89633300 C

PAGE 1\10

45

FROM
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22P2A15
22P2A16
22P2A 17
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22P2A1.9
22P2AlO
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W I

TO
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24PIB31
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2.3 P? 820
21P2B 06
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21PIA:JO
24PIB21
23P2A27
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89633300 A

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[

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5 (GNAl-NAME
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A 8 1 C 7/8
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89879100
89379100
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89819100
89879100
898'19100
89819100
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FR .lEV TO.lEV
2
1
1
1
1
1
1
1
2
2
1
2
1
1
2
2
2
2
1
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9-99

PAGE

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50

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55

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26P2A04
26P2A04
26P2A05
26P2A06
26P2A07
26P2A08

W IRE
TO
25PIA1A
24PIA2l
27PI At'i
25P1A20
28PIB2R
22 P2 AO~
26P1821
21PIA21
26PIA2'i
26PIA24
26P2 AI?
25PIA26
25P2A09
2C5Pl A'-R
20P282f1
20PtSl'i
21P28l,.
25Pt803
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15PIB17
20P2Bt4
25P16l3
25PIB14
24Pl Bl"
27PIB 17
21PIA2h
25PIB17
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27PIA14
23P2A 11
21P2A29
21PIB20
26PIA2~

25PIB23
2RPIA2R
25PIB 2'i
21PIB29
2 8Pl A21
20P1A1')
20P1814
2 8PI AV!
20PIA14
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26P280'i
20P2B2l
25P2A06
21PIB30
25P2ACA

89633300 A

l

I

5 T

5IGNAl-NAME
XfZ
MXIM
MXIM
yeK
ALU3M
SE
5E
PLM
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HIGH
HIGH
52
ALUOAM
CLREG*
OAI c*
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TAOM
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TA2M
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08
PCI<
MTAOO
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GLM
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eo
ALUCM
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CNS2M*
ALUlM
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QSX
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A 8

W.L.
89879100
89879100
89879100
89879100
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89819100
89819100
89819100
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89879100
89819100
89819100

1

o 118
FR .LEV TO.LEV
1

1

1

1
2
1
2
2
1
1
1

2
1
2
2
1
1
1
1
2
2
1
2
1
1
2
2
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2

1
1
1
2
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2

9-109

PAGE NU

56

'FROM
26P2A09
26P2AIO
26P2Ali
26P2A12
26P2A12
26P2A13
26P2A14
26P2A15
26P2A16
26P2A17
26P2A18
26P2A18
26P2A t"9
26P2A20
26P2A20
26P2A21
26P2A22
26P2A23
26P2A24
26P2A25
26P2A26
26P2A28
26P2A29
26P2A29
26P2A30
26P2BO 1
26P2802
26P2B03
26P2804
26P2805
26P2607
26P2808
26P2809
26P2BIO
26P2810
26P2Bli
26P2B12
26P2B13
26P2B14
26P2815
26P2B16
26P2816
26P2817
26P2818
26P2Bl9
26P2S19
26P2B20
26P2B20
26P2822
26P2823
26P2Bl4

9-110

WI
TO
22P2823
25P2AI0
20PIA03
26Pl A2'i
26P2810
25P2Al·4
22P282R
28P281h
28P2809
21PIAO'
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27P1821
24P2801)
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17P2816
17P2 Al:J
15PIAIA
24P2A20
25P2A26
24P182A
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21P2A06
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15P1819
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26P2A04
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22P2A20
2 QP2 All

R E

liS T
SIGNAL-NAME
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HIGH
MCK
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7/8

FR.LEV TO.LEV

1

1
1
2
2

1
2
1
2
1
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2
2
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89633300

A

PAGE NO

W I

57

FROM
26P2825
26P2B26
26P2821
26P2828
26PlB29
26P2B29
26P2B)O
26P2831
27P1AOI
21P1 A:> 1
21PIA02
21P1A03
27PI A03
21PIA04
21PIA04
27PIA05
21PIA05
21PIA06
21PIA06
21P lA07
27P1A01
21Pl A08
21P 1A08
27Pl A09
27PIA09
27PIAI0
27PIAIO
21PIAll
27PIAlI
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21P lA 12
27PIA13
21PIA14
27PIA14
21PIA15
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27PIA18
27PIA18
27PIA19
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21PIA20
27P1A20
27P lA2l
27PIA22
21PIA22
27PIA23
21PIA23
27PlA24
21PIA25

TO
15PIA19
25P2805
21P1812
15P181R
21 Pl All
lOP2A15
25P2830
25P2 B31
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89633300

A

R E

l

1ST

S'IGNAl-NAME
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89879100
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o

118

FR .lEV TO.lEV
1
2
1
1

1
2
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2
1
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9-111

~AGE

~O

58

FPOM
27Pl A2 6
21PIA26
21Pl A27
27PIA21
21PIA28
27PI A2 8
27P lA30
21PIA30
27PIA31
21P I BOI
21P1B02
27PIB02
27PIB03
27PIB03
21Pl804
21P1805
21PIA06
21PIR06
21PIBOl
21P1808
27P 1808
27P1809
27P1810
27P1812
21PIBI3
21PIB13
27PIB14
27P1814
27P1815
21P1816
27P18~6

271»1817
27P1811
21P181A
27P1818
21PI RI9
27PIB19
27 P IB20
27PIB20
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21P1821
21P1822
27P 1B22
21P1821
27P1823
27P1824
21P1825
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27P1826
27PIB27
27P182A

9-112

W I

T1)
31P2B03
21P2A19
21P2A12
31P2804
31P2BO'i
21 P2 BOlt
24P1812
31P2806
31 P2 B09
29PIA01
·25Pl SIA
31PIBOl
31PIAOl
25PIA19
29PIAOh
29PIAOA
28Pl A05
13PIBl'
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29PIA17
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14Pl Bl 0
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26P2819
26P2A20
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29P1S30
29Pl B31
28PIB27.
22PIA12
28P2A13
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R E

l

I

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SIGNAL-NAME
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MX17
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MPRY
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B 1 o 118

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89819100
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89819100
89819100
89819100
89819100
89819100
89879100
89879100
89819100
89879100

FA. .lEV TO.LEV
1
2
2
1
1
2
2
I
I
2
2
1

1
2
2
1
1
2
2
1
1
2
2

1

1
2
2
2
2
1
2
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1
2
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2
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1
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1
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89633300

A

PAGE NO

59

FR!]M

21P18l9
21P1B29
211»1830
21P18]0
21P1Rli
21P1831
21PlAOl
21P2A01
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21P2A06
21p·2A06
21P2A01
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21P2A09
27P2A09
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21P2A10
21P2A11
21P2A12
21P2A14
21P2 A15
21P2A16
21P2A11
21PlA18
21P2A18
l1P2A19
21P2A19
21P2A20
21P2A21
27P2A21
21P2A22
21P2A21
21P2A24
21P2A25
21P2A26
21P1A28
21P2A28
21P2A30
27P2BOt
21P2BOI
27P2B02
21P2803
27P280S
21P2806
21P2808
21P2809
27P2810
27P2811
21P281t

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31P2A10
21PlB24
31P2AOq
31P2810
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31P2A 11
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26P2 A2q
29P2A20
21P280"l
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29P2 A07
33P2814
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28P2A 14
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16P1801
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33P2AIR
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28P2A29
33P2B20
16PIAOI
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21P240R
28P2810
28P242'
28P2A20
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29P2A21
21P2Al1
33P2813

89633300 A

R E

lIS T
SIGNAL-NAME
SPI*
SPI*
PRTM*
PRTM*
S WRITE*
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SA15
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89819100
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89879100

o

118

FR.lEV TO.lEV

2

2

1
1
1
1
2
2
1
2
1
1
1
2
2
2

1
2
1
1
2
2
1
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2
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1

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1

9-113

PAGE NO

60

W

IRE

FROM

TO

21P2812
21P2813
21P2814
21P281S
21P2816
21P2811
21P2818
2.1P2818
21P2819
21P2819
21P2820
21P2820
21P2821
21P2822
21P2823
21P2823
27P2824
21P2824
21P2825
27P2826
21p2826
27P2827
27P2828
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28PIA05
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28PIA09
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27P1806
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9-114

A 8 1 o 1/8

L t S T
SIGNAL-NAME
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89633300 A

PAGE NO

61

FROM
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28PIA19
28PIA19
28PIA20
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28Pl A21
28PIA21
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89633300 A

l

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9-115

PAGE Nil

62

FROM

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89633300

A

PAGE NO

63

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9-117

P4GE NO

64

FROM
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89633300 A

'"'

.

PAGE

NO

W I

65

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89633300

A

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9-119

PAGE NO

66

FROM
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PAGE Nil

68

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PAGE NO

10

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89879101
89819101
89879101
89819101
89879101
89879101
89879101
89819101
89819101
89879100
89879100
89879100
89819100
89819100
89d 19100
89819100
89819100
89d19100
89879100
89879100

o

118

fR.LEV TO.LEV
1
2
2
1
1
2
2
1
1
2
1
2
1

1
2
2
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1

1
2
2
1
1
2
1
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1
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1

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1
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9-124

89633300

A

\4
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PAGE NO

W I R f

11

FROM

lAPlRll
l8PlA15
28Pl A16
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21P28lCJ
21P2821
30P282?
32Pl B21
30P2821
32P28l1
32P2B24
30P2824
30Pl825
32Pl R2'i
32P28l6
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32P28l8
30P2828
10P28lQ
32Pl82Q
30P2830
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33P1AO?
31PIAOl
33PIAOl
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33PIA04
31PIA05
33 PI A05
33PIA06
31PIA06
31 PI A07
33PIA01
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31 PI AOR
31PIAOQ
33PIAOQ
33PIA14
31PIA14
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33P1A17
31PIAIR
33PIAIR
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31PIA21)
~3PIA20

89633300

I S T

SIGNAL-NAME

TJ

31PlB14
31Pl815
31PlBlb
31P2Rll
11P2B18
31P28l0
31P2B22
llPl822
31P2823
31P2B23
31P2Bl4
31P2B24
31P2825
31P2825
31P2826
31P2B26
31P28l7
llPl821
31P2828
31P2828
31P2B29
31P2B29
llP2830
321»1A02
32PIAOl
32PIA03
32PIA03
32PIA04
32P1A04
32PlA05
32PIA05
32PIA06
32P1A06
32PIA07
32PIA07
32PIA08
32PIA08
32PlA09
32P1A09
32PIA14
32PIA14
32P1A15
32PIA15
32PlA11
32PlAl1
12P1Al8
32Pl Al8
32PIA19
32PIA19
3lPlA20
32P1A20

l

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00UT8

A 8 1
W.L.
89819100
89819100
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o

118

FR.lEV

1
1
1
1

1
1
2
1
2
1
1
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2
1
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1
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TO.lEV
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2
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2
2

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9-125

PAGE NO

12

F~'M

32P1A20
32P1A25
32PIA27
32Pl A21
32PIA28
32PIA28
32P1A30
32PIA30
32PIA31
32P1A31
32 0 1803
32P1803
3lP18"07
32P1801
32Pl816
32PIB16
32P1819
32P1819
32P1820
32P1820
32P1824
32P1824
32P1825
32Pl825
32P1826
32P1826
32P1821
32P1827
32P1828
32P1828
32P1829
32P1829
321»1830
32P18)O
32P1831
32P 1831
32P2AOI
32P2AOl
, 32P2A02
32P2A02
32P2A04
32P2A04
32P2A05
32P2A05
32P2A06
32P2A07
32P2A07
32P2A20
32P2A20
32P2A21
12P2A21

9-126

W fR F.

TJ
31PIA20
33PIA20
33PIA21
31PIA27
31PIA2A
33PIA28
33PI A30
31P1A30
33Pl A31
31 PI All
31P1803
33P1801
33P1807
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31P1816
33PIBIt.
33P1819
11P1819
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31P1820
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31P1831
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31P2A04
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31P2A20
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lIS T
S IGNAl-N·A ... E
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00UT13
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00UT14
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REF.
REF.
DISA8lE
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A 6 1

W.!..
89819101
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o

7/8

fR.tEV TO.lEV
1
2
2
1
1
2
2
1
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1
1
2
2
1
1
2
2
1
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1
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89633300

A

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\4

PAGE NO

W 1 R E

13

FROM

3"3P2A23
31P2A23
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31P2824
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34Pl A07
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34PlA04
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34Pl A01
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34P1 AO~
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89633300

1ST

SIGNAL-NAME

TO

321>2A23
32P7.A23
32P2A74
32P2A24
32P2 A25
32P2A25
32P7. A26
32P2A26
32P7.A27
32P2A21
32P2A28
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89819101
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o

118

FR.l EV TO .LEV
2
1
1
2

Z

1
1
2

1

1

2

2

1

1
2
1

2
1

2

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1
2
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1
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1
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1
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2
2
1
2

1
1
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1
2
2
1

1
2
1

2
2
2

2
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1
2
1
1
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2
1

2

2
1
1
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1
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1
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1
2
1
1

1
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9-127

P'GE N()

14 .

FROM
33PIAli
33PIA12
33P1A13
33PIA14
33PIA14
33PIA15
33PIA15
33PIA16
31PIA17
33PIA11
33PIA18
33PIA18
33P lA19
31PIA19
33PIA20
3.3PIA20
3)PIA20
33P1A22
33PIA23
33P1A25
31P1A27
33PIA2·7
33PIA28
33PIA28
33PIA30
33P1430
33P lA31
33PIA31
33P1801
33P1802
33P1803
33P1803
33P1804
33P1806
33P 1807
13Pl807
33P1808
33P1809
33P1810
33P1812
3JP1813
13P1814
3JP 1815
33P1816
13P1816
33P1817
33P1818
33P1819
33P 1819
3)P1820
31P1820

W IRE
TJ
28P1801
28P1808
28P1809
32PIA14
34PIA14
34PIAl'!)
32PIAl,!)
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14PIA17
32PIA 17
32P1A18
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32PIA19
34PIA19
32PIA25
32PIA20
34PIA20
28P1820
28P1821
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14PIA27
32PIA27
34Pl A2~
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34P1430
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.34PIA31
32PIA31
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32P1801
34P1801
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)

9-128

lIS T
SIGNAL-NAME
505
504
5 #\4
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5011
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500
502
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DIN3
503
507
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a

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1

o

1/8

FR.lEV TO.lEV

1
1
1
2
1
1
2
1
1
2
2
1
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2

1
1
1
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(.,
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89633300

A
~

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PAGf NO

15

FROM

W I

TO

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33PIB22
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31P1829
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33PIB31
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33P2 AO 1
33P2 A01
33P2A02
33P1A02
33P2A04
33P?A04
33P2A05
33P2A05
33P2A06
33P2A07
33P2A01
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31PlAlO
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33PlA13
33P2A18
33P2A19
3"iP2A20
33P2A20
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33P2A21
33P2A22
3-}P2A23
31P2A23
33P2A24
33P2 A24
31P2A25
33P2A25
31P2A26
3.lPlA26
33P2A21

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32PIR24
34Pl B2~
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32Pl827
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32P2A20
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o

118

FR.lEV TO.lEV
1
1
1

1

1
1

2
1
1

1

2

2

2

1

1

1

2
2
I
1
2
2
1
1
2
2
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2
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2
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1
1

2
2

1
1

1
1
1
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1
2

1
2
1
1
2
1
2

1
2

2
1
1

1

1
2
2
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2

2
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1
2
2
1
1
2
1
2
1
2
1
1
1
1
1
1
1
1
1
2
1
2
1

1
2
1
2
1
2
2
1
1

9-129

PAGE

".,~

76

F~OH

33P2A27
33P2A28
3JPl A28
33P2A29
33P2A29
33P2A30
33P2A30
33P2801
3JP2802
33P2803
33P2804
31P2805
33P2806
33P2809
33P2810
33P2811
33P2812
33P7813
33P2814
33P2815
33P2816
33P2811
33P2818
33P2819
33P2820
33P2822
33P2822
33p2823
33P2823
3)P2824
33P2824
33P2825
33P2825
33P2826
33p2826
33P2821
33P2821
33P2828
33P2828
33P2829
~3P2829

33P2830
33P2830
3~PIA02

. 34P1A02
34plAOl
34PIA03
34PIA04
34P1A04
34PIA05
34PIA05

9-130
)

W IRE

TO
32P2A21
34P2A28
32 P2 A2B
34P2A2Q
32P2A29
34P2 A30
32P2A30
28P2811
28PIA21
28P1823
28Pl A24
28PIA26
28P1821
28Pl A30
28PIA31
23PIAOl)
21P2BOl
21P2811
21P2 A14
27P2 Ala
27P2818
21P2 A19
21P2824
28P2821)
21P2 A2A
32P28Z7
34P2822
32P2823
34P2823
34P2B24
32P2824
32P2S21)
34P2821)
34P2826
32P2826
34P2827
32P2827
34P2828
32P2828
34P282CJ
32P282Q
32P2830
34P2830
33Pl A01.
35PLA01.
35PIA03
33Pl AOl
3.3PIA04
35P1404
33Pl AOI)
35Pl A05

lIS T
S (GNAL-NAME
ACA9
ARA2
ARA2
ARAI
ARA1
lKO*
lKO*
DX4*
S012
SA1
S015
SAIO
SA12
SA14
SA13
GOM2
PRTSW
NORMAL
MSXA"
S017
SRSH*
SS*
S\JIO*
SAl
S~Q*

ACA8
ACA8
ACA6
ACA6
lK2*
lK2*
ARA3
ARA3
ACA5
ACA5
R/W
R/W
ARA4
ARA4
lKl*
lKl*
MPWR*
MPWR*
DOUTO
OQUTO
OIN 1
OINl
DOUTl
DOUTI
OlN2
OlN2

A 8 1

W.l.
89879101
89819101
89819101
89819101
89819101
89819101
89819101
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819104
89819100
89819100
89819100
89879100
89819100
89879100
89879100
89819100
89819100
89819101
89879101
89879101
89819101
89879101
89819101
89819101
89d79101
89819101
89819101
89879101
89819101
89819101
89819101
89819101
89819101
89819101
89819101
89879101
89819101
89819101
89819101
89819101
89819101
89879101
89819101

o 7/8
FR .lEV TO.lEV
2

1
2
1
2
1
2
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
2
1

1
2
2
1
1
2
1
2
1
2
1
2
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1
1
2
2
1
1
2
1
2

2
1

2
1
2
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
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1
1
2
1
2
1
1
2
2
1
1
2
1
2
1
2
1
2
2
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1
2
2

1
1
2
1
2

89633300 A

P4GE NO

W I

77

fR1M

Tn

3~PlAOb

3ltPIA06
lltP1407
3ltPlA07
3ltPlA08
3ltP1A08
34PIA09
34PIA09
34P1A14
3ltPlA14
34PIA15
3ltPlA15
34P1411
34PIA17
34Pl A18
34PIA18
3ltPIA19
3ltPlA19
34PIA20
3ftPIA20
.~4PIA20

34PlA25
34Pl A21
3ltPlA21
34PIAZ8
34Pl A2 8
34PIA30
34PIA30
34P1A31
34P1A31
3~PIBO.3

34P1B03
34PIB01
3ftPIB01
34Pl816
34P1816
34Pl819
34P 1819
34Pl B20
34PIB20
34PIBZ4
34P1824
34P1B25
34P1825
34PIBZ6
34Pl826
34P1827
34Pl R2 7
34PIBZ8
34P1828
34P1829

l

t S T

SIGNAL-NAME

35Pl AOt)
33PLA06
33PIA07
35 PI A07
33PIAO~

JS;PIAOR
33PIA09
31)PIA09
35PIA14
33PIA14
33P1411)
1l)P1411)
33PIA17
35PIA17
35PIAl~

33PIAIR
33PIA19
35PIA19
35PIA20
13Pl A20
33P14ZI)
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35Pl A27
31PIA27
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33 PI AlR
33PIA1O
35PIA30
35Pl A31
3.3PIA31
33PIB03
35PIBO':\
33P1807
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35PIR16
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33 Pl 820
33PlB24
35PIB24
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35P18ZS;
33 PIB2&
35PIR26
35P1827
33Pl B27
35PIB2A
33PIB28
33 P1 B2Q

89633300

R E

A

OOUT2
DOUT2
OlN4
OlN4
DOUT3
DOUT3
DOUT4
OOUT4
OOUT5
Dour5
D(N6
O(N6
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DIN7
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DOUT8
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DOUTII
OOUTII
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DIN8
DIN9
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DOUTI0
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D[NIZ
DINII)
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DOUT13

A 8 1
W.L.
89879101
89879101
89879101
89819101
89819101
89879101
89879101
89879101
89879101
89879.101
89819101
89819101
89879101
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89819101
89819101
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89879101
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89879101
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89879101
89819101
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o

7/8

FR.lEV TO.LEV
2
1
1
2
1
2
1
2
2
1
1
2
1
2
2

2
1
1
2
1
2
1
2
2
1
1
2
1
2
2

1

1

1
2
2
1
1
2

1
1

1
2
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1
1
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1
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1
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2
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2

2

1

1
2
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1
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1
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2
1
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1
1

2
2
1
1
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1
2
2
1
2
1

2

2
1
2
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1
1

9-131

PAGE

NO

78

FROM

W IRE
TO

l

1ST

S IG.NAl-NAr-e

A 8 1
W.l.

o 7/8
FR.lEV· TO.lEV
"

34P1829
34P1830
34P1830
34P1831
34P1831
34P2AOI
. 3ftP2AOI
3~P2A02

3~P2A02

14P2A04
34P2A04
34P2A05
341»2A05
34P2A06
34P2A07
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34P2A20
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34P2A21
34P2A21
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34P2A.23
34P2A24
34P2A24
34P2A25
34P2A25
34P2426
34P2A26
34P2A27
34P2A21
34P2A28
3~PlA28

34P2A29
34P2429
34P2A30
34P2430
34P2801
34P2822
34P2822
3ltP2823
14P2823
34P2824
34P2824
.34P2825
34P2825
34P2826
34P2826
34P2827
34P2827
34P2828
34P2828

9-132

35PlBl9
35P1830
33P1B30
31P1831
35P1831
33P2A01
15P2AOI
35P2AO'
33P2A02
35P2 AOft
33P2A04
35P2AOl)
33P~ AOI)
28P2801
35P2A01
33P2A01
33P2A20
35P2A20
35P2A21
33P2A21
33P2A21
35P2A21
33P2A2~

35P2A2ft
33P2 A21)
35P2A21)
35P2A26
3.3P2426
33P2A21
35P2A21
33P2A28
35P2A2R
33P2A29
35P2A29
33P2 A30
35P2A30
28P2806
35P282'
33P2822
33P2823
35P2823
3.3P2824
35P282ft
35P282,)
33P282')
33P2826
35P2826
33P2827
15P2827
33P2B28
35P282R

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OOUT15
OOUT15
OOUT16
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DOUT17
OOUT17
OlNl6
DIN16
DIN17
DtN17
MOX5*
STR08E*
STR08E*
REF*
REF*
DISA8lE
DISABLE
A(A7
ACA7
lK3*
1K3*
ARAO
ARAO
CE*
CE*
ACA9
ACA9
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APA2
ARAI
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lKO*
lKO*
DX5*
ACA8
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lK2*
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ARAIt

89879101
89879101
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89819101
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2
2
1
1
2
1
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2
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2
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89633300 A

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NU

19

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TO

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34P2829
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14P2B30
14P 2R30
15P1A02
35PIA02
35PIAOl
35PL AO"3
35P 1A04
35PIA04
35PIA05
35P lA05
35P1A06
35PIA06
35PIA01
35P1A01
15PIA08
35 P 1A08
35PIA09
35PIA09
35PIA14
35PIA14
35PIA15
35P1 A15
35PIA17
351>1A17
35PIA18
35PIA18
35PIA19
35PLA19
35PIA20
35P1A20
15P1A20
35P 1A2 5
35Pl A21
15P1A27
351)1A28
35PIA28
35PIA30
35P1A30
35PlA31
35PIA31
35P1803
35P1803
35PIB01
35PIB01
35P IB 16
35"1816
35Pl B19
35P UH 9
35 P 1B20

33P2B29
35P2R29
33P2B30
35P2R30
34P1 AO~

R E

l

t S T

S. 'GNAl-NAME

34PIA30
36PIA30
36P1 A31
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36P1BOl
34P1 RO~
36PlB07
34P1807
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11<1 *
lKl*
MPWR*
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00U10
DOUTO
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00UT2
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DOUT8
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DIN 11
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DCU111
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36P1 B19
34P1B19
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89633300 A

A B 1
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898191u 1
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o

7/8

FR.lEV TO.LEV
1
2

1

1

1
2

2
2

1
1
2

1
2
1

2
1
2
1
2
1
2
2
1
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2
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1
2
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2
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1
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2
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2
1
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1
2
2
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1
2
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9-133

PAGE NO

80

FROM
35P1820
35P 1824
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35P 1825
35P1826
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35P1827
35PIB28
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89819100
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89879101

FR.lEV TO.lEV
2
2
1
1
2
2
1
1
2
1
2
2
1
1
2
2
1
1

2
2
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2

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1
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1
2
1
2
1
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2

2

1
2
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2
2

2
2
1
2
1
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1
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1
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9-134

89633300

A
,~
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PAGE NO

W I

81

FROM

36Pl~26

36P1827
36P1828
36P1829
36P1830
J6P1831
361>2AOI
36P2A02
36P2A04

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34P2821
36P2824
34P282434P282')
36P282')
36P2826
34P2826
36P2827
34P2 A27
36P282A
34P2828
36P2 B2q
34P2B29
34P2810
361>2830
35PIA02
35Pl A01
35PIA04
35PIAO')
35P1406
35P1407
35PIA08
35Pl AOC,
351>1414
351>1411)
351>1Al1
'351>1AIA
35PIAIQ
35PIA20
35PIA25
35Pl A27
35P1A2A
35PIA30
35Pl A31
35P1801
35P1801
35P1816
35PIB19
15Pl A20
35P1B24
35PIB21)
35P1826
351>1827
351>182R
35Pl A29
35P1830
35P1831
35P2AOI
35P2 AO?
35P2 AO~

89633300

l

1ST

SIGNAl-N~ME

Tl

31)P2823
35P2823
35P2824
35P2824
35P2825
35P2825
35P2826
35P2826
15Pl827
35P2827
35P2828
35P2828
35P2829
35;»2829
15P2830
351>2830
361>1A02
16Pl A03
36PlA04
36PIA05
36PIA06
36PIA07
36PIA08
36PIA09
36PIA14
];PIA15
"36PLAI7
36PlA18
36P1A19
36P1420
36PIA20
,36Pl A21
16PIA28
16Pl A30
36P1431
36P 1803
16PIBOl
361>1816
361>1819
36PIB20
36P1824
36P1825

R E

A

ACA6
ACA6
lK2*
lK2*
~RA3

ARA3
ACA5

ACA5
R IW
R/W
ARA4
ARA4
1 Kl*
lKl*
MPWR*
MPWR*
OOUTO
OINI
D~t) Tl
DIN 2
DOUT2
0lN4
DOUT3
00UT4
OOUT5
OlN6
DOUT6
DINl
OOUT7
DOllrS
DOUT9
o (Nil
OlNI0
OOUT11
DOUTl2
DINO
DIN3
DIN5
DIN8
DIN9
OCUTl 0
DIN 12
OlN15
DIN13
OlN14
OOUT13
OOUT14
00UT15
DOUTl6
DOUT17
OlN16

A 8 1

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89879101
89879101
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89879101
89879101
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89879101
89879101
89879101
89879101
89879101
89879101
89879101
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89879101
89879101
89879101
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89879101
89879101
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89879101
891379101
89879101
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89879101
89879101
89879101
89879101
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89879101

o

7/8

fR.lEV TO.lEV
1

1

2

2

1
2

1
2
2
1
1
2
1
2
1

2
1
1
2
1
2
1
2
1
2
2
1
1
I
1
1
1

1
1
1
1
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2
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2
2
1
1
1
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1
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1
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1

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1
1
1
1
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1
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1
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1
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1
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1
1
1
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1
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1

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1
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1

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1
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9-135

PAGf NO

82

FROM
36P2A05
36P2AOb
36P2A01
361)2A20
36P2A21
36P2A23
36P2A24
36P? A21)
36P2A26
36P2A27
36P2A28
36P2A29
16P2A10
3bP2BOI
36P2822
36P2B23
36P2B24
36P2B25
36P2826
36P2B27
36P2828
36P2829
36P2830

9-136

14 I
TO
3r;PlAOI)

l8P2 AOA
31)PlA07
3r;PlAlO
35P2A2J
35P2A21
35P2A24
35P2 A21)
3ljP2A26
35P2 A27
35P2 A2A
35P2A2Q
3ljP2A30
28P2AOS

35Pl822
35P2 B23
3r;P28l4
35P2825
35P282&
35P2827
35P282A
35Pl8lCJ
35P2830

R E

lIS T
SIGNAl-NAI'IE
DIN17
MOX1*
S TP08E*
REF*
DIS A8l E
ACA1
lK3*

ARAO
CE*
ACA9
ARA2
ARA 1
IKO*
OX1*
ACA8

AeAb
1 K2*
ARA3
AeA5
R IW
ARA4
lKl*
MPWR*

A a
\II .l.

89879101
89d 79100
89819101
89819101
89819101
89819101
89819101
89819101
89819101
89819101
89819101
89879101
89879101
89879100
89879101
89879101
89879101
89879101
89879101
89819101
89879101
89819101
89879101

1

o

7/8

FR .lEV TO .LEV
1

1
1
I

1
1
1
1
1
1
1

1
1
1
I

1
1

1
1
1
1
1

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1

1
1
1
1
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1
1
1
1
1
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1

1
1

1
1
1

1
1

89633300 A

TABLE 9-5

89633300

A

WIRE LIST BT148 EXPANSION ENCLOSURE BACKPLANE
{signal name order}

9-137/9-138

O~PIA21.06PIA21

06PIA21.14PIA21
14PIA21.22PIA21
14PIBIA.22P1818
02P181A.06PIB18
06PIB18.14PIA18
12PIB07.13PIA07
IlPIB07.12PIA07
03PIB07.0~PIB07

OSPIB07.11P1807
04PIA07.0SPIR01
OlP1807.03PIB07
19PIB07.20PIR07
13PIB07.19PIB07
20P1801.21PIR01
13P1823.19PIR23
19PIB23.20PIR23
20P1823.21PIR23
14PIA09.22PIA09
06PIA09.14FIAOS
IlPIB23.12FIR23
04P1823.0SPIR23
03P1823.04FIR23
01PIB23.03P1823
02PIA09.06PIAOQ
12PIB23.13PIA23
OSP1823.11PIB23
OlPIA03.0~PIA03

OSFlA03.11PlA03
IlPIA03.12PIA03
12PIA03.13FIA03
03PIA03.04PIA03
04PIA03.0SPlA03
13PIA03.19PIA03
19PIA03.20PIA03
20PIA03.21PIA03
20PIBOl.21PlROl
19PIAOl.20PlBOl
03PIBOt.04PIAOl
04P1801.0SPIBOl
llFlBOl.12FlBOl
13FIBOl.19PlBOl
OSPlROl.llPlBOl
01P180l.03PlAOl
l2P1801.13PlBOl
12PIB02.13PIA02
IlPIB02.1~PlB02

OSPIB02.1lPlB02
04PIB02.0SFIA02
13PIB02.19PIB02
03PIB02.04FIR02
01PIB02.03PIR02
20PIB02.21PIB02
19PIB02.20PIB02
19PIA06.20PIA06
20PIA06.21PIA06
IlPIA06.12PIA06
12PIA06.13PIA06
OSPIA06.1lPlA06
89633300 A

32KW
32KW
32KW
~UTOLO~C

WIRE liST BT148

AUTOLOAC
AUTOLOAC
CHI*
CHI*
CHI*
CHI*
CHI*
CHI*
CHI*
CHI*
CHI*
~C*

MC*
MC*
~C*

MC*
~C*

MC*
~C*
~C*
~C*
~C*
~C*

OAO*
CAO*
OAO*
CAO*
OAO*
OAO*
OAO*
CAO*
OAO*
OA1*
OAI*
C~l*

OAI*
OAl*
OAl*
OAl*
OAl*
CAl*
CA2*
OA2*
OA2*
OA2*
OA2*
OA2*
OA2OA2*
OA2*
OA3*
OA3*
OA3*
OA3*
OA3*

9-139

04PIA06.05PIA06
01PIA06.03PIA06
03P 1AOf,. 04Pl A06
13PIA06.19PIA06
13PIA07.19PIA07
03PIA01.04PIA07
12P1A01.13P1A01
01PIA01.03PIA01
05PIA01.l1PIA01
llP1A07.12PlA07
04PIA07.0~PIA07

20FIA07.21P1A07
lqPlA07.2~PlA01

20P1AOl.21PlAOl
19PIAOl.~OPlAOl

12PIAOl.13PlAOl
04PIAOl.OSPlAOl
llPlAO It 12PIAO 1
OJPIAOl.04PlAOl
OSPIAOl.llPlAOl
IJPlAOlt19PlAOl
01PlAOltOJP1AOl
OlP1A02.03PIA02
lJPlA02.19PlA02
05P1AO?.11PIA02
OJP1A02.04PIA02
llPlA02.12PIA02
04PIA02.0SPIA02
l2PlA02.13PlA02
20PIA02.21PIA02
19PIA02.20PlA02
19P180J,20PlB03
20PIB03.~lPIBOJ

lJPlB03.19PIBOJ
IIPIBOJ.12P180J
03PIB03.04PIB03
05PIB03.11PIBOJ
OlPIBOJ.03PIB03
04PlB03.0SPlBOJ
l2PlBOJ.lJP1803
12PIB04.13PIB04
04PIB04.0SPIB04
01P1B04.0JPIB04
11PIB04.1~PIB04

05PIB04.11PIB04
IJP1B04.19PIB04
OJPIB04.04PIB04
19PIB04.20PIB04
20PIB04.21P1804
20PIBOS.2iP180S
19P180S.20PIBOS
04PIBOS.OSPIBOS
IJPIBOS.19PIBOS
OSP1BOS.liP1R05
11PIBOS.12PIBOS
01P180S.0~PIBOS

OJPIBOS.04PIB05
l2PlBOS.l~PlB05

OSPIB06.11PIB06
12PIB06.13PIB06

9-140

OA3·
OA3·
OA3·
OA3·
OA4OA4·
0_4*
OA4·
OA4·
OA4*
OA4·
OA4·
OA4OASOAS·
OAS·
OASOAS·
OAS·
OAS·
OAS·
OASOA6·
OA6OA6·
OA6OA6·
OA6·
OA6·
OA6OA6·
OA1·
OA1OA1·
OA1OA7·
OA7·
OA1·
OA1·
OA1OA8OA8OAAOABOA8·
OA8·
OAS·
OASOA8·
OA9·
OA9·
OA9·
OA9OA9·
OA9·
eA9·
OA9OA9·
OAlO·
OAIO·

WI RE LI ST BT148

(j

~

I~

89633300

I~

A

r,
~

~

04P1B06.0SP1806 OA10.
01P1B06.03PIB06 OAlO.
11PIB06.12PIBO~ OAI0.
03PIB06.04PIBO~ OA10.
l3P1806.19PlRO~ OA10.
19PIB06.2QPIB06 OA10.
20PIB06.21PIB06 OA10.
20P1AOS.21PlAOS OAII •
. 01PIAOS.OlPlAOS OAII.
llP1AOS.12PlAOS OAll.
l2PlA05.13PlAOS OAII.
03PIAOS.04PlAOS OAII.
19P1AOS.2qPIAOS OAII.
05PIAOS.1IPIAOS OAll.
04PIA05.05PIA05 OAll.
13PIA05.19PIA05 OAll.
OIPIA04.03PIAO~ OA12.
IlPIA04.12PlA04 OAI2·
04PIA04.0SPIAO~ OA12.
03PIA04.04PlA04 OA12.
19P1AO~.20PlAO~ OAI2.
12PIA04.13PIA04 OAI2..
05PIA04.IIPIA04 OAI2.
l3PlA04.19PIA04 OA12.
20PIA04.2lPIA04 OAI2.
20P1B09.21P1B09 OA13.
19PIB09.20PIB09 OAI3.
IlPlB09.l2PlB09 OAI3.
03PIB09.04PIB09 OAI3.
OSPIB09.1iPI809 OA13.
01PIB09.03PIB09 OAI3·
13PIB09.19PIB09 OAI3.
04PIB09.0SP1B09 OA13.
l2P1B09.13PIB09 OA13.
l2PlBlO.13P1BIO OA14·
l3P1B10.19PlA10 OA14.
OSP1Bl0.1lPlAlO OAI4·
03P1810.04PIBlO OA14.
OlPIBIO.~3PIBIO OA14·
IIPIB10.12PI810 OAl~·
19P1810.20P1810 OA14.
04PIB10.OSPIAI0 OAI4.
20PlB10.2lPIB10 OA14.
05P1All.11PlAll OA1S84PIAll.OSPlAll OAIS.
I1PlAll.12PlAll OAIS.
12PIAll.13P1All OAI5.
13PIAll.19PlAll OA1S20PIA1I.21PIAll OA15·
19PIAll.20PlAll OAI5·
03PIAll.04PIAll OAI5.
OlPIAll.03PIAll OAI5.
02PlA17.06PIA17 FEL·
06PIA17.14PIA17 PEL·
14PIA17.22PIA17 PEL·
03PIA23.04PIA23 PRl~·
OSPIA23.1IPIA23 PRlM.
11PIA23.12PIA23 PRlM.
19P1A23.20PIA23 PRlM·
01PIA23.03PIA23 PRlM.
89633300 A

WI RE LI ST BT148

9-141

20PIA23.2iPIA23
IJPIA2J.19PIA23
12PIA23.13PIA23
04PIA23.0SP1A23
OSPIA12.11PIA12
12PIA12.13PIA12
03PIA12.04PIA12
IlPIA12.12P1A12
04PIA12.0SPIA12
01FIA12.03PIA12
IJPIA12.19PIA12
20PIA12.21PIA12
19PIA12.20PIA12
OSPIB12.11PIB12
IJPIB12.19PIBI2
04PIBI2.0SPIBI2
20PIB12.21PJ812
01F1812.0JPIB12
03P1812.04PIB12
12PIB12.13PIB12
19F1812.20PIB12
11P1812.12PIB12
04PIAI3.0SPIA13
01PIA13.03PIA13
IlPIA13.12PIA13
12PIA13.13PIA13
20PIA13.21PIA13
IJPIAIJ.19PIA13
OSPIAIJ.11PlA13
OJPIA13.04PIA13
19PIA13.20PIA13
IJPIBIJ.19P1B13
04P1813.0SPIR13
19PIB13.20PIB13
20P1B13.21P1813
01P1813.03Pla13
12PIB13.1~PIB13

OSPIB13.11P1813
03P1813.Q4P1813
IlP1813.12PIB13
12PIA14.13PIA14
IlPIA14.12PIAI4
04PIA14.0SPIA14
IJPIAI4.19PIA14
20PIA14.21PIA14
01PIA14.03PIA14
OSPIA14.11PIA14
OJPIA14.04PIA14
19PIA14.20PIA14
19P1814.20P1814
04PIB14.05P1814
20P1814.21P1814
03PIB14.04P1814
OSPIB14.11PIB14
13P1814.19P1814
01PIB14.03PIB14
12P1814.13P1814
IlP1814.12PIR14
12PIA1S.13PIA15
04PIAlS.OSP1A1S
9-142

PRlM.
PRlM.
PAlM.
PAlM00
00
00
00
00
00
GO
00
00
01
01
01
01
Cl
01
01
01
01
02
02
02
02
02
02
02
G2
02
03
03
03
03
03
03
03
03
Q3
04
04
04
04
04
04
04
04
04
05
OS
as
05
OS
OS
05
05
OS
06
06

WIRE LIST BT148

89633300

A

11P1A1S.12PIAlS
19PIA1S.20P1A1S
13PIA1S.19P1A!S
20PlAIS.21PtA1S
OlP1AIS.03PIA15
OSP1A1S.11PIA15
03P1AlS.04P1A15
20P1B1S.21P181S
04P1B1S.0SP1B1S
03P181S.04Pl81S
19P1815.20P1815
OSP181S.11P181S
l2P181S.13P18l5
1JPIB1S.19P181S
01P1R15.0JP1815
11P181S.12P181S
OSP1A16.11 P1A16
11P1A16.l2P1A16
12P1A16.13PIA16
13PIA16.i9PIA16
19P1A16.20P1A16
OlP1Al6.03P1A16
20PlA16.21P1A16
04P1A16.0SP1A16
OJP1A16.04PlA16
01P1816.03P1816
03P1Bl~.04P1Ai6

20P1816.21P1816
19PIBl6.20PIA16
OSP1816.11PIB16
13P1816.19P1816
12PIB16.13P1816
04PIB16.0SP1R16
IlP1B16.12P1B16
OJP1A17.04PIA17
OSP1A17.11PIA17
12P1A17.1JPIA17
OlPlA17.0JPlA17
IlP1A11.12PIA17
19PIA17.20P1A17
1JPlA11.19PlA17
20P1A17.2lP1A17
04PIA11.05PIA17
19P1B11.20PIB17
20P1817.21P1817
OJP1B17.04P1817
01PIB17.0JP1Bl1
IJPIB17.19P1B17
12P1811.lJP18l1
OSPIB11.l1PlBI1
04PIB11.0SP1B17
llPlB11.l2PlB17
19P1A18.20P1Al!
OSPIA18.11P1Al!
OJPlA18.04P1A18
11PIAle.12PIA1!
12P1'18.13PIA18
20PlA18.21PlA18
01P1A18.03P1A1e
04PIA18.0SP1A18
89633300 A

06
06
06
06
06
06
06
07
07
01
01
07
07
07
07
07
08
08
08
08
08
08
08
08
08
09
09
09
09
09
09
09
09
09
010
010
010
010
010
010
010
010
010
011
011
011
011
011
011
011
OIl
011
012
012
012
012
012
012
012
012

WIRE LIST BT148

13P1A18.19P1A18
OSP1818.11P1818
20P1818.21P1B18
01P1818.03P1818
13P1818.19P1818
12P1918.t3P1818
19P1818.20P1818
l1PI818.1~P1818

04P1818.0SP1818
03P1818.04P1818
04P1A19.05P1A19
OSP1A19.11P1A19
I1PIAI9.12PIAI9
12PIA19.13P1A19
01P1A19.03P1A19
20P1A19.21P1A19
13P1A19.19P1A19
19PIA19.20PIA19
03P1A19.04P1A19
OSP1819.11P1819
13P1819'19P1819
12P1819.13P1819
20P1819.21P1819
19P1819.20P1819
I1P1819.12P1819
04P1819.0SP1819
01P1819.03P1819
03P1819.04P1819
04P1A21.0SPIA21
OSP1A21.l1PIA21
12PIA21.13PIA21
l1P1A21.12P1A21
01PIA21.03P1A21
13PIA21.19P1A21
03P1A21.04PIA21
19PIA21.20PIA21
20PIA21.2ipIA21
OSP1822.11P1822
01P1822.03P1822
19P1822.20P1822
12P1822.13P1822
20P1822.2ipi822
03P1822'04P1822
13P1822.19P1822
04P1B22.0SP1822
l1P1822.12P1822
04P1A22.0SPIA22
12P1A22.13P1A22
13P1A22.19P1A22
01PIA22.03PIA22
20P1A22.2ipiA22
03P1A22.04PIA22
I1PIA22.1~P1A22

05PIA22.11P1A22
19P1A22.20P1A22
06P1812.14P1812
02P1812.06P1812
14PI812.2~PI812

06P1823.14P1823
14P1823.22P1823
9-144

012
013
013
013
0(3
013
013
013
013
013
014
014
014
014
014
014
014

WI RE LI ST

BT148

Q14

014
01S
01S
CIS
01S
01S
015
015
01S
CIS
READ*
REAO*
READ*
READ*
READ*
REAO*
READ*
READ*
READ*
REJECT*
REJECT*
REJECT*
REJECT*
REJF.CT*
REJECT*
REJECT*
REJECT*
REJECT.
REPLY*
REPLY*
REPLY*
REPLY*
REPLY*
REPLY*
REPLY*
REPLY*
REPlY*
SS*
SS*
SS*
SAO
SAO

\

89633300 A

02P1823.06P1823
06PIA03.14PIA03
14P1A03.22PIAOJ
02PIA03.06P1AOJ
06P1824.14P1824
14P1824.22P1824
02P1824.06P1824
14P1801.22P1801
02P1801.06P1801
06P1801.14P180l
06PIB2S.14P182S
14P182S.22P1825
02P182S.06P1825
l4P1802.22PIB02
02P1B02.06P1802
06PIB02.14PIB02
06PIB26.14PIB26
14PIB26.22P1826
02P1826.06PIB26
14PIA06.22PIA06
06PIA06.14PIA06
02FIA06.06PlA06
l4PlB21.22PlB27
06PlB21.14P1821
02P1821.06P1821
l4PlA01.22PIA01
02PIA01.06PIA01
06PIA01.14PlA07
l4PIB28.22PIB2B
06PIB28.14PIB28
02PIB28.06P1828
06PIAOl.14PIAOI
06PIB30.14P1830
14P1830.22P1830
02F1830.06PIA30
14PIA02.22P1A02
06PIA02.14PIA02
02P1A02.06PIA02
02P1B31.06P1831
14P1831.22PIB31
06P1831.14P1831
06P1803.14P1B03
14P1803.22PIB03
02PIB03.06P1803
06PIA23.14PIA23
02PIA23.06PIA23
14PIA23.22PIA23
14PIB04.22PIB04
02P1804.06P1804
06PIB04.14P1804
06PIA24.14PIA24
14PIA24.22P1A24
02PIA24.06PIA24
02PIBOS.06P1805
14PIBOS.22PIB05
06P1805.14P1805
06P1814.14P1814
02P1814.06P1814
14P1814.22P1814
06PlAIS.14PIAlS
89633300 A

SAO
500
500
500
SAl
SAl
SAl
SOl
SOl
501
SA2
SA2
SA2
S02
S02
S02
SA3
SA3
SA3
503
S03
503
SA4
SA4
SA4
S04
S04
504
SAS
SA5
SAS
SOS
SA6
SA6
SA6
S06
506
506
SA1
SA7
SA7
S07
507
S07
SA8
SAA
SA8
508
S08
S08
5A9
SA9
SA9
S09
S09
S09
Spy*
Spy*
SPY*
SRQ*

WIRE LIST 8T148

9-145

02PIA15.06PIA15
14PIA15.22PIA15
06PIA25.14PIA25
14PIA25.22PIA25
02PIA25.06PIA25
14PIB06.22P1806
02PIB06.06P1806
06PIB06.14PIB06
14PlA26.22PlA26
06PlA26.14PlA26
02PIA26,06PIA26
06PlA05.i4PlA05
02PlA05.06PlA05
l4PlAOS,22PIAOS
02PlA27.06PlA27
l4PlA27.22PlA27
06PlA27.14PlA27
06PIA04.l4PlA04
14PlA04.22PlA04
02PlA04.06PlA04
06PlA28.14PIA28
02PIA28.06PIA28
14PlA28.22PlA28
02PIB09.06P1809
06P1809.14PlB09
14PlB09.22PlR09
06PlA30.l4PIAJO
02PlA30.06PlA30
l4PlA30.22PIA~O

02PlBlO,06PlBlO
06PIBIO.14P1810
l4PlBlO.22P1810
02PIA31,06PlA31
06PIA31.14PlAJI
l4PlA3),22PlA31
02PIAll,06PlAll
14PIAII.22PIAI1
06PlAll,14PlAll
02PIA18,06PlA18
06PlA18.l4PIAI!
14PlA18.22PIA18
06PlA20.14PIA20
02PlA20.06PlA20
l4PlA20.22PlA20
06P182l.l4P1821
14P182l,22P182l
02PlB21,06P1821
l4PlA13.22PlA13
02PIA13.06PlA13
06PlA13.l4P1A13
02P18l7.06PlB17
06PlBI7.~4P18l7

14PIB17.22P18l7
03PIA09.04PIA09
01PIA09.03PIA09
13PIA09.19PIA09
19P1A09.20PlA09
l1PlA09.12PIA09
04PIA09.0$PIA09
20P1A09.21PIA09

9-146

SROSROSAlO
SAI0
SAI0
SOlO
SOlO
SOlO
SAil
SAIl
SAIl
5011
5011
5011
SA12
SA12
SA12
5012
5012
5012
SAI3
SA13
SA13
5013
5013
5013
SA14
SA14
SA14
5014
5014
5014
SAIS
SA15
SAlS
SOlS
5015
5015
5016
5016
5016
5017
5017
5017
SWRITf*
SWRITESWRITE*
SRSMSRSMSASMSVIO·
SVIOSVIOT.P.
T.P.
T.P.
T.P.
T.P.
T.P.
T.P.

WI RE LI ST BT148

89633300

A

WIRE LIST BT148
12P1A09,13P1A09
05P1A09,11P1A09
05P1A20,11P1A20
04P1A20,05P1A20
l1P1A20,12P1A20
12P1A20,13P1A20
20P1A20,21P1A20
13P1A20,19P1A20
03P1A20,04P1A20
01P1A20,03P1A20
19P1A20,20P1A20
19P1B21,20P1B21
01P1B21,03P1B21
13P1B21,19P1B21
05P1B21,11P1B21
12P1B21,13P1B21
20P1B21,21P1B21
03P1B21,04p1B21
04P1B21,05P1B21
-11P1B21,12P1B21

T.P.
T.P.
WEZ*
WEZ*
WEZ*
WEZ*
WEZ*
WEZ*
WEZ*
WEZ*
WEZ*
WRITE*
WRITE*
WRITE*
WRITE*
WRITE*
WRITE*
WRITE*
WRITE*
WRITE*

TABLE 9-6. COT EXTERNAL CABLE ASSEMBLY WIRE LIST (P/N 89668300)
COT
WIRE
WIRE
CPU
CONNECTOR/PIN
GAUGE
COLOR
CONNECTOR/
SIGNAL NAME
PIN
Pl-2

P14-51

CRT-TRANS

-3

RED

P14-57

CRT-REC

-7

GRN

P14-58

COMMON (GND)

WHT/BLU

Pl-5*

CLEAR TO SEND
jumpered to
REQUEST TO SEND

Pl-4

*

AWG22

BLK

-~

AWG22

Pl-5 (CLEAR TO SEND) is jumpered to Pl-4 (REQUEST TO SEND) at
assembly connector for COT.

89633300 C

9-147/148

(

(

(
(

\

COMMENT SH'EET
MANUAL TITLE CONTROL PATA R CENTRAL PROCESS I NG UN IT
BA20 1-B, BT 148, BU 120, GD611
PUBLICATION NO. _8;,.=9;..,;.6.:;.3,:;.;33::..0...,;0_ _ _ __

FROM:

AB] 07. AB] 08. BA20] -8

HARDWARE MA I NTENAN'CE MANUAL

REVISION _ _ _
F _ _ __

NAME: ______________________________________________________________________________
BUSINESS
ADDRESS: __________________________________________________________________________

COMMENTS:
This form is not intended to be used as an order blank. Your evaluation of this manual will be welcomed
by Control Data Corporation. Any errors, suggested additions or deletions, or general comments may
be made below. Please include page number references and fill in publication revision level as shown by
the last entry on the Record of Revision page at the front of the manual. Customer engineers are urged
to use the TAR.

NO POSTAGE STAMP NECESSARY IF MAILED IN U. S. A.
FOLD ON DOTTED LINES AND STAPLE

STAPLE

STAPLE

FOLD

-----------------------------------~
FIRST CLASS
PERMIT NO. 313

BUSINESS REPLY MAIL

L.A JOLLA. CA.

NO POSTAGE STAMP NECESSARY IF MAiLED !N U.S.A.

POSTAGE WIL.L. BE PAID BY

CONTROL DATA CORPORATION
PUBLICATIONS AND GRAPmCS DIVISION
4455 EASTGATE MALL
LA JOLLA, CALIFORNIA 92037

------------------------------------~
FOLD
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I
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I

I
I

I
I
I

I

STAPLE

STAPLE I



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