89633300H_AB107_AB108_Hardware_Maint_Manual_Jul80 89633300H AB107 AB108 Hardware Maint Manual Jul80
89633300H_AB107_AB108_Hardware_Maint_Manual_Jul80 manual pdf -FilePursuit
89633300H_AB107_AB108_Hardware_Maint_Manual_Jul80 89633300H_AB107_AB108_Hardware_Maint_Manual_Jul80
User Manual: 89633300H_AB107_AB108_Hardware_Maint_Manual_Jul80
Open the PDF directly: View PDF 
.
Page Count: 748
| Download | |
| Open PDF In Browser | View PDF |
89633300
CON1'R..OL DATA
CORfO~TION
CONTROL DATA®
CENTRAL PROCESSING UNIT
AB107
AB108
BA201
BU120
BT148
GD611
GENERAL DESCRIPTION
OPERATION
INSTAllATION AND CHECKOUT
THEORY OF OPERATION
DIAGRAMS
MAINTENANCE
PARTS DATA
APPENDIX
WIRE LIST
HARDWARE MAINTENANCE MANUAL
REVISION RECORD
REVISION
DESCRIPTION
a--____02_____ I __E_C_0__C::.cK.:.: 0. :.4."'5____
6 r_e_l..:..ea::..:s'-e_d_m_a::..:nc.:.u_a_l_t::..:o.--,-c_la_s_s_B.:..,_________ .____._._____ ..._._ . _... __. ____. _.... __ ._________ .___._.__.____._
(JanyarY,,197;L, I. . ,- J j ;
. 03
. '-'.
ECO ·tK'O''''''S2'''''Z--an-d--EC-0--C-KO-7-4-8-c-o-m-p-l-et·-e-l-y-re-v-i-s-ed--m-a-nu-a-l-.------------·-.. --· ....-..-..- -----.-----.-------.---.. --(October:1974) ~.I-"-'--.,,-.-------;------------~----'-------------------------------.-------.---.--------... - - '
-- - - - - - , - - - - - - - - - - - - - " - - - - i s_e_d_ma_n_u_a_I_.__~__________________.______.______________________ _
I_~~'~g_4____,__~ dCO-H!JJl.,.re._vc_
(March 1975)
I-'----=-:...::..c.----I------------·
_________________________·____·___ ---------.------------.--A
ECO CK1312 released manual to class A.
1--------------1----------.------------------- ----------------------.--(Augu st 1975)
B
ECO CKI347 affected pages: xv, 2-5, 2-6, 3-13, 3-19. 5-7. 9-1, 9-147.
-------------------------1
(October 1975)
C
ECO CK1421 incorporated Field Change Orders CK1415. CK1422. CK1431.
(January 1976)
Pages revised: ii to xv. 3-13, 4-45, 4-46, 4-56. 5-39. 5-87. 5-145, 5-151. 5-155. 5-159. 5-259
5-379. 5-380 to 5-383. 5-385. 5-389, 5-393. 5.397. 5-403, 5-408. 5-409. 5-414 to 5-421. 5-430.
6-4, 8-1, 8-2, 9-2, 9-7, 9-26, 9-36, 9-37, 9-40, 9-45, 9-49, 9-55. 9-57, 9-63, 9-80, 9-85, 9-88.
9-89, 9-90, 9-93, 9-98, 9-147
Pages added: 3-13A, 3-13B, 5-160 to 5-166, 5-410 to 5-413, 5-422, 9-2A.
-----~----.------------.----~.---------.--------
1--------1---
D
(July 1976)
E
I_ _--''--_
__
(July 1977)
ECO CK1559 incorporated ECO CKJ526 and CAR'sLJL043, 158. 173. 174.
-------------1--------
ECO CK1830. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __'___ _ _ _ _ _ _ _ _ _.._..--CAR's incorporated: LJL046/268, LJL072/383. Internal CAR 406, LJL186/505, LJLI99/515, LJL203-381/5J7
LJL206/519. LJL207/520. LJL211/524
I·--=--'--'-=-::..:~..::.c::...:...
~-----------I------
---.--~----~:--------~----~~-----------------------
ECO's incorporated: CK1054. CK1436, CK1588, CK1788, and ECO/FCO CK0676.
1-___________ ...!_<3~.~~ __':lid~~__ 3-29, 3-30, 8-3.
Pages deleted: 9-2A.
1________.____ ~Cl~.~~ ...r:~\I.i~~~: iii to vi, vi i i. xi i to xvi i, 4-5, 4-9, 5-23, 5-32, 5-36, 5-82, 5-89, 5-J45, 5-296,
1-________.______.._.5.:-171 to 5-4'0, 5-1.35, f..-h h-?7, f\-l. F\-? q-l to q-8. q-4~. 9-61.
1-________..____~_~_a.!=E!~_:.._Manual-to-Equipment Correlation sheets and Parts Data.
F
ECO CKI996 Incorporated Models C and D.
Reference CAR LJL209/522, CAR LJL216/531.
1 - - - - - - - - - - - - ------------------
1-------
(November. 1..97.11.. __ . ____________._.________________________________________________________
G
ECO CK2784 corrected the following:
1 - - ' - - - - - -.. - ...- - - - · - - - - - - - - - - - - - - - - - - - - - - - - - ' ' - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1
(July 1979)
Wrong Console PWA part number 89602068 changed to 89602069: pages 5-143. 5-145, 5-157.
,__________ ~_iJ:~hcap__.P_art number 89769400 added to Parts Data; 29 must be ordered with Console PWA 89602069
__________ I_~in~s~e~ri~e~s~~_y~~s 8-1~8-2. Pag~e~8~-_~3~de~l~e~t~e~d~b~y~ne~w~l£ay~o~u~t~.________________1
1________
-.TJ:ll::~~_ wi res_..chan~.!;L-ln-Jt{LrJng-Jj.sLdue
I _ _ _ _ _ _ _ _ ~ng
to E..c.oJ£il_CK2372: pages q-34. q-6.1.'-".~q'--"'68"".~--------.
error corrected..hy adding connection 115-11 (sheet 6) to 1152-4 (sheet 2)' page 5-395
I - - - - - - - - - I - - - - ; - - - - - - - - - -..--·:--;---;----·----;~-:_____=__;_---___;_-__:_--__;___;--------------1
H
ECO CK 3018 Incorporated changes of Series Codes, part numbers and pin numbers in the wiring list.
1--(J-u-1Y-1-9-8-0)--II-=R-ef:=-.--:'C-A-:-;R:;--;;2-=-52·~and TAR 065965. Pages to be replaced: ii, iii/iv, 5-143, 5-421, 5-425, 5-429/5=430, --5-4317S:432;--8-1~-8-2, 8-3/8-4, 9-46, 9-65, 9-66, 9-71 and Comment Sheet.
1 - - - - - - - - - 1 - - - - · - - - - - - - - - -..· - - · - - · - - - - - - - - - - - - · - - - - - - - - - - - - - - - - - - - - - - - - - - 1
Publication No.
89633300
Page ii
@ 1974 to 1980
by Control Data Corporation
Printed in the United States of America
Address comments concerning this
manual to:
Control Data Corporation
Publications and Graphics Divisio
4455 Eastgate Mall,
La Jolla, California 92037
or use Comment Sheet in the back of
this manual.
MANUAL TO EQUIPMENT LEVEL CORRELATION SHEET
This manual reflects the equipment configurations listed below.
EXPLANATION' Locate the equipment type and series number, as shown on the equipment FCO 109, in
the list below. Immediately to the right of the series number is an FCO number. If that number and all
of the numbers underneath it match all of the numbers on the equipment FCO log, then this manual
accurately reflects the equipment.
MANUAL EQUIPMENT
WITH
REVISION
TYPE
02
AB107-A04
AB108-A04
AB107/8-A05
AB107/8-A06
AB107/8-A07
BT148-A04
BA20l-A03
BA20l-B03
BA20l-A/B04
BU120-A03
GD6ll-A02
CK0573
CK0263
CK0677
CK0705
CK0736
CK0668
CK0652
CK0457
CK0673
CK0705
CK0245
03
AB 107l8-A08
BT148-A05
BU120-A04
CK0840
CK0677
CK0939
04
AB107/8-A09
AB107/8-A10
AB 107l8-A 11
AB107/8-A12
BT148-A06
BU120-A05
CK1063
CKI 0 11
CK0992
CK124l
CK1063
CK0992
A/B
AB107/8- A1 3
BT148-A07
BA20l-A/B05
BU120-A06
CKll09
CK0906
CK0978
CK124l
C
AB107-A14
AB108-A14
AB107l8-A15
AB 107l8-A 16
AB107/8-AI7
BT148-A08
BU 120-A07
CK1272
CK12 73
CK14l6
CK1415
CK1431
CK1415
CK1272
D/E
AB107/8-AI8
AB 107l8-A 19
BU120-A08
CK1448
CK1526
CK1588
F
AB107l8-COl
AB107/8-C02
AB107/8-C03
BTI48-COI
BT148-c03
AB107/8-DOl
BT148-DOl
CK1491,1931
CK1502,1931
CK1562,1931
CK1491
CK1842
CK1909,193l
CK1909
G/H
AB107/8-D02
CK2372
02/03/04
02
up
COMMENTS
ECO/FCO
,
89633300 H
...
I I 1/
I V
PREFACE
This manual provides customer engineering information for the CONTROL DATA R
AB107 and AB108 with memory and supporting equipment. The AB107 and AB108
computers are physically compact and are designed for high computation and
input output speeds. They feature a semiconductor memory with a basic size
of 4096 (4K) 18-bit words which is field expandable in 4K word increments to
65K words.
NOTE:
Equipments identified without type identifier A,C,D refer to all three.
The following Control Data publications may be useful when installing and
maintaining this equipment.
Pub. No.
Control Data Publication
1784 Computer System Reference Manual
1784 Key to Logic Symbols
System Maintenance Monitor Manual (SMM17)
AB107/AB108 Execution Charts
89633400
89723700
60182000
1784 Computer Input-Output Specification Manual
CDC Mini-Computer System Site Preparation Manual, section 2
89723800
89673100
60437000
1784 Computer System Peripheral Equipment Hardware Maintenance
Manuals: (HR/M means combined Hardware Reference/Maintenance Manual)
AF108 Paper Tape Reader/Punch Controller
HR/M 89865200
AT310
DJ815
FA442
FA446
FA716
FC106
GN109
FEl19
TTL A/Q DSA Bus Expander
Asynchronous Communications Controller
ICL Magnetic Tape Transport Controller
LCTT Magnetic Tape Transport Controller
Cartridge Disk Drive Controller
Key Entry Station Controller
Key Entry Distribution Unit
Card Reader Controller
FE203
FF524
FJ505
FJ606
Card Punch Controller
Line Printer Controller
Binary Synchronous Communication Controller
Synchronous Communications Controller
89633300 F
I
89758600
HR/M 89600054
89637700
89637700
89638100
89672200
89672200
HR/M 89637500
89910800
89637300
89934100
89638500
(Continued on next page)
v
I
PREFACE (Continued)
Control Data Publication
FV497 ICL Phase Encoding Formatter
Fv618 LCTT Phase Encoding Formatter
I
vi
Pub. No.
89796100
89796100
. 896333000 F
The following list includes the documents associated with the cQnversational
display terminal:
Publ ication No.
Ti tl e
713-10 Operator's Guide
62037900
713-10 Reference Manual
62033400
713-10 On-Site Maintenance Manual
62048500
713-10 Installation Instruction
62048700
Following is a 1 ist of documents relating to the non-impact printer
station:
Title
Pul icat ion No.
713-11 Operator's Guide
62149600
713-11 Reference Manual
713-11 Installation Instructions
62149700
62149800
713-11 On-Site Maintenance Manual
62149900
Other Publications
For 33 ASR/KSR teletypewriters:
I
Teletype Bulletin
310B, Volume
Teletype Bulletin 310B, Volume 2
Teletype Bulletin
1184B, Parts Schematic package WDP03l6 includes
document Nos. l1805D, 9334wD, 9335WD, 9336WD, 4970WD, 7887WD,
181821, 183079, 183087.
For 35 ASK/KSR teletypewriters:
I
Teletype Bulletin
281B, volume
Teletype Bulletin
281B, Volume 2
Teletype Bulletin
1201B, Parts Schematic Package.
89633300 F
vii
CON TEN T S
SECTION
1.
Page
GENERAL DESCRIPTION
Introduction
Physical Characteristics
1-1
1-4
En vi ron men t
1-5
1-5
System Power
2.
I
3.
OPERATION AND PROGRAMMING
Programming
2-1
Ope rat i on
2-1
Switching On
Initial Conditions and Operation
2-1
Battery Operation
2-5
INSTALLATION AND CHECKOUT
Introduction
3-1
Uncrat ing
Inspection and Preparation
3-1
Mechanical Inspection
Electrical Inspection and Preparation
Ins ta 11 a t ion
Initial Operation
Installation/Removal of the Battery
Installation of the Battery
Remova 1 of the Bat te ry
Procedure to Install External Shielded Cable Assemblies
Te letypewri ter (TTY)
Models 33 ASR/KSR
"odels 35 ASR/KSR
35 ASR/KSR I/O Cable Connections
Conversational Display Terminals (COT)
vi i i
2-4
3-2
3-2
3-5
3-14
3-11t
3-19
3-19
3-21
3-22
3-21t
3-21t
3-25
3-25
3-27
89633300
F
CONTENTS (continued)
SECTION
4.
THEORY OF OPERATION
I ntroduct ion
Basic Computer
The Central Processing Unit (CPU)
Data Path
Main Registers
Control and Timing Section
Memory System
Introduction
Memory Control System
Principles of The Dynamic Semiconductor Memory Chip
Detailed Operation of The Memory Unit
Refresh Time
Chip Select
Power Supply Levels
I nputC lock Amp Ii tudes
System Considerations
Memory Module
The Memory Module Block Diagram
Auxiliary Circuit Functions
Low Power Data Retention (LPDR) Mode..
Power Back-Up
Programmer1s Console
In.put!Output
The Teletyp.ewriter (TTY) Controller
Direct Storage Access (OSA)
A/Q Channel
Interrupts
Power Supply
Electrical
Mechanical
General Description and Block Diagram
89633300
Page
D
4-1
4-1
4-4
4-4
4-4
4-8
4-12
4-12
4-12
4-15
4-26
4-29
4-29
4-29
4-30
4-30
4-31
4-32
4-34
4-36
4-36
4-38
4-39
4-40
4-40
4-45
4-51
4-55
4-55
4-57
4-57
ix
CONTENTS {continued}
Page
SECTION
5.
DIAGRAMS
lntroduction
Key to Logic Symbols
Signa 1 Flow
Logic Diagram Revision Correlation Sheet
Memory Sys tem
Memory Module
Protection Against Catastrophic Failure
Memory Address
Kiloword Selector
Row Selector
Column Selector
Module Selector
Data In
Data In:
Parity and Protect Bits
Memory Control
Low Power Data Retent ion (LPDR)
Memory Control Access Selector
Memory Control Timing
Memory Control Basic Control Signals
Basic Control Signals
Write Control Signals
Memory Control Data Output Li nes
Memory Control Bank Address
The Central Processing Unit
Programmer I s Console
Register Selectors
Data Bit Selectors
Control Switches and Indicators
Switches ,and Output Signals
Indicator Lights and Input Signals
x
5-1
5-3
5-3
5-8
5-19
5-21
5-30
I
5-45
5-49
5-52
5-57
5-60
5-65
5-685-81
5-83
5-90
5-99
5-to5
5-107
5-115
5-121
5-429
5-141
5-143
5-147
5'-15t
5-155
5-155
5-156
89633300
F
I
CONTENTS (continued)
SECTION
5.
Page
DRAWINGS
(Cont I d.)
Arithmetic
~nd
Logic Unit (ALU)
Addend Registers and Gates
Augend Registers and Gates
Arithmetic and Logic Operations
Shifter
Interrupt Logic
Decoder
Instruction Register and First Level Decoders
Addend Gate Controls
Augend Gate Controls
Controls for ALU and Addressing
Register Clock Controls
Timing
State Equations
Typical Timing Sequences
Oscillator and Phase Generator
Counter
Interrupt Timing, V Register Control Logic
Main Sequence Flip-Flops
Auxiliary Sequence Flip-Flops
Input/Output (I/O) Interface
A/Q Channel Control
Memory Request Logic
Index (i) Address and Write Enable Controls
Decoder for Fl Field
Augend Controls and X Register Clock Control
Controls for Shifter and A/QChannel Direction
Main Sequence Flip-Flop Controls
,
Overflow Logic
Enable-Interrupt logic
89633300 D
5-168
5-178
5-182
5-190
5-193
5-202
5-211
5-215
5-220
5-225
5-228
5-232
5-241
5-242
5-245
5-249
5-258
5-265
5-270
5-277
5-291
5-294
5-299
5-302
5-307
5-310
5-314
5-318
5-322
5-327
xi
··CONTENTS (continue,d)
SECTION
5.
(Cont'd)
Page
DRAWINGS
Console Interface
Start/Stop Sequence Flip-Flops
Program Protect Logic
Test Mode and Autorestart
AlU Logic
Enter Interrupt Logic
Skip Logic
Te 1etypewri ter (TTY) Controller PWA 89967400
A/Q Channel Data Path
Controller/Teletype Interface
Oscillator- Baud RataSelector
Address Decoding- Reply/Reject Logic
Control and Interrupt Logic
Breakpoint Logic
Teletypewriter (TTY) Controller PWA 89947600
A/Q Channel Data Path
Controller/Teletype Interface
Osc ill ator'" Baud Rate Se lector
Address Decoding- Reply/Reject Logic
Control and Interrupt Logic
Teletypewriter (TTY) Controller PWA 89984700
A/Q Channel Data Path
Oscil1ator- Baud Rate Selectpr
Breakpoint Logic
Te 1etypewri ter (TTY) Controller PWA 89976400
Osc ill ator- Baud Rate Se 1ector
Enclosure Power Input
The Power Input Ci rcui t
Power Supply Unit
Power Supply Wiring Diagrams
High Power (HP) and Control Assembly
LoW Power Circuit Assembly
xi i
5-337
5-339
5-345
5-352
5-357
5-364
5-369
5-374
5-374
5-379
5-382
5-386
5-390
5-396
5-402
5-404
5-405
5-406
5-407
5-408
5-410
5-412
5-413
5-414
5-416
5-418
5-421
5- 4221
5- 423
5-426
5-437
5- 446
89633300 F
1
CONTENTS (continued)
SECTION
6.
Page
MAINTENANCE
Tools and Special Equipment
Calibrate Power Supply Levels
Check Battery
Inspection or Replacement of Printed Wiring Board
Inspection or Replacement of the Power Supply Unit
Check Programmer's Console Controls and Indicators
Inspection or Replacement of Programmer's Console and
6-1
6-3
6-5
6-7
6-9
6-12
6-15
I
Components On It
Inspection or Replacement of Cooling Blowers
Power On: Procedure For Switching On Power
Power Off; Procedure For Switching Off Power
Emergency Shut-Down
Regular Shut-Down
Diagnostics and Margin Tests
7.
6-22
6-26
6-27
6-27
6-27
6-28
MAINTENANCE AIDS
TTL Ci rcu it Oper.at ion
MOS Circuit Operation
The MOS Process and Silicon Gate Technology
Precautions in Handling the Memory Modules
Protection Against Catastrophic Damage
7-1
7-3
7-3
7-9
7-9
8.
PARTS DATA
8-1
9.
WI RE LISTS
9-1
89633300 F
xi i i
I
LI S T OF TABLES
Section
4
Table
Page
1-1
Equipment Description
1-1
4-1
Basic Computer Functional Units
4-2
4-2
Basic Timing Specifications of the Memory Units
4-25
4-3
DSA Channel Pin Assignments
4-41
4-4
A/Q Channel Pin Assignments
4-48
4-5
Interrupt Access Pin Assignments
4-52
4-6
Summary of Regulated Power Supply Circuits
4~63
I
4-63
6
6-1
Power Supply Levels and Tolerances
6-4
9
9-la
TTY Internal Cable PIN 89684200
9-2
9-lb
TTY External Shielded Cable PIN 89642300
9-2
9-2
Memory Expansion BU120-A08 External Cable Assembly
{pO AWG 28 PIN 89658101 (3 sheets)
9-3
9-3
Memory Expansion BU120-A08 External Cable Assembly
(P2) AWG 28 PIN 89658501 (3 sheets)
9-6
xiv
9-4{a) AB107/AB108 Backplane Wiring-Signal Name Order
9-9
9-4{b) AB107lAB108 Backplane Wiring Card Slot Order
9-51
I
9-5
BT148 Backplane Wire List
9-138
9-6
COT External Cable Assembly Wire List
9-147
89633300 F
LI ST OF FIGURES
FIGURE
Page
2-1
2-2
AC Power Switch and Connection
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-3
Card Placement Slot Assignment: Expansion Enclosure
3-4
Power Supply Heat Shield and Retainin.g Screws
3-6
Inside of Main Enclosure Front Door
3-8
Power Supply Connector Panel
3-8
AC Power Switch and Connection
3-9
Rear of Enclosures
3-12
General View and Dimensions of Main Enclosure: Type Ident. A 3-15
External Dimensions of Main Enclosure: Type Identifiers A,C,D 3-16
Rear Cover With Battery
3-20
Installation Kit Part No. 89986600 For External Shielded Cable 3-23
4-1
4-2
4-3
Computer System Simplified Block Diagram
CPU Block Diagram
4-3
4-5
Memory Address System and Data Flow
4 ... 13
4-4
The Memory Ce 11
4-5
Memory Unit (a)
(b)
(c)
(d)
4-6
Memory Timing (a) CPU and DSA Cycles
(b) Refresh Cycles
4-7
4-8
4-9
4-10
4-11
4-12
Memory Module Block Diagram
AC-to-DC Converter and Protection Circuits: Block Diagram
4-13
Power Supply Regulator and Control Circuits: Block Diagram
4-14
Switching Regulator: Basic Circuit and Waveforms
4-17
4-19
4-20
4-21
4-22
4-23
4-24
4-33
4-42
4-49
4-50
4-58
4-60
4-64
4-66
89633300
Computer Front View
2-3
2-7
Card Placement Slot Assignment: Main Computer Enclosure
Block Diagram and External Connections
Detailed Block Diagram
Circuit Details
Circuit Details
DSA Channel Timing
A/Q Channel Timing
A/Q Channel Input/Output Lines
Power Supply: Simplified Block Diagram
F
xv
I
LIST OF FtGURES (continued)
FIGURE
Page
6-1
Computer Backplane Showing the Power Supply Test Points
6-6
6-2
6-3
6-4
6-5
6-6a.
6-6b.
6-7
6-8
Use of Board Extractor and Board Extender
6-8
6-8
Exposed View of Two Lower Fans and Electrical Connections
7-1
Diode AND Gates
7-2
7-3
7-4
7-5
7-6
7-7
TTL AND Gates
xvi
Power Supply Heat Shield and Retaining Screws
Power Supply Adj us tmen ts and Fuses
6-11
Power Supply Terminals and Reta in i ng Screws
Inside of Computer Enclosure Front Door
6-11
Inside of Computer Enclosure Front Door
6-20
6-21
6-25
6-19
Blower Assembly in Top of Enclosure (All type identifiers)
MOS Inverter Circuits
7-2
7-2
7-2
7-6
7-6
MOS Inverter With Output Booster
7-7
MOS Transmission Gate
7-7
Typical Logic Level Margins for TTL Micrologic
Typical MOS Characteristic
89&33300 F
SECTION 1
GENERAL DESCRIPTION
GENERAL DESCRIPTION
INTRODUCTION
The CONTROL DATA~ABI07 and ABI08 computers are small, stored program parallel
mode digital computers with semiconductor memory of a basic 4096 (4K) 18-bit
words, field expandable to 65K words in 4K word increments.
The main computer
enclosrues houses the first 32K words {32,768} memory bank, the second bank
(memory expansion) being accommodated in the BT148 Expansion Enclosure.
The
main computer and the expansion enclosures also house the peripheral controllers.
The following table lists the equipment which make up the ABI07 and ABI08
computers.
Equipment described in this manual (see preface for CE Manuals
of associated equipments).
TABLE 1-1.
Equipment Number
ABI07-A
EQUIPMENT DESCRIPTION
Description
The central processing unit performs the following functions:
a.
Arithmetic and logical operations required by the stored
program.
b.
Control operations to execute and synchronize operations
within the central processor, in the memory and for
input/output.
c.
Interrupt processing for one internal and fifteen external
priority interrupts.
d.
Program protection to protect one set of programs in the
memory from the effect of other programs.
The equipment combines with 'up to eight BA201-B Memory Modules
housed in the computer enclosure to provide a bank of
32,768 (32K) words of semiconductor memory storage with a
cycle time of 900 nanoseconds.
89633300
A
1-1
EQUIPMENT DESCRIPTION (cont'd)
AB107-A (cont'd)
The memory Illay be expanded by up to eight BA201-B Memory
Modules to provide a second bank uf 32K words housed in the
BTI48-A Expansion Enclosure with the BUI20-A Memory Expansion
Controller to give a total of 65,536 (65K) words memory.
The memory is innerentlyvolati Ie.
I t may be made non-volati Ie
within an enclosure by install ing the optional GD611-A Memory
Hold Battery in the enclosure.
The equipment includes the following, in addition to the
central processing unit:
'a.
Front panel Programmer1s Console carrying all the system
b.
controls.
Non-buffered input/output channel based on the A and the
Q register (A/Q channel).
c.
Direct Storage Access (DSA) channel for the buffered data
transfers from peripheral control equipment housed in the
main computer enclosure or external to it.
d.
Controller for the standard input/output Teletypewriter.
The Teletypewriter to be used is the Teletype Corp.
Models ASR/KSR 33/35.
e.
Wiring, power suppl ies and enclosure for the ABI07-A
equipment circuits and in addition, for the following
circuits:
FA716-A Cartridge Disk Drive (COD) Controller
FA442-A/FV497-A Magnetic Tape Transport (MTT) Controller
it:
peripheral controllers, up to four on the A/Q channel and
I
up to three on the DSA channel
.
FA446-A/FV618-A Magnetic Tape Transport (MTT) Controller
*
GD611-A Memory Hold Battery (optional)
The equipment works from 110 vac
50/60 Hz line voltage, and
can be field converted to 220 vac, 50/60 Hz.
1-2
,
89633300
A
EQUIPMENT DESCRIPTION (cont'd)
AB108-A
Equipment identical to the AB107-A except in that it combines
with BA201-A Memory Modules to provide a memory cycle time of
600 nanoseconds.
The Input/output operations (A/Q and DSA
channels) are correspondingly faster in this computer but the
input/output equipment used is the same as in the AB107-A.
The equipment works from 110 vac 50/60 Hz line voltage, and
can be field converted to 220 vac, 50/60 Hz.
BA201-A
BA201-B
Semiconductor storage module containing 4096 (4K) 18-bit words.
The unit is designed to operate with the AB107 and AB108
computers and uses control logic provided by them to execute
read and write operations.
The storage read/write cycle
durations are:
BA201-A controlled by AB108-A:
BA201-B controlled by AB107-A:
BT148-A
600 nanoseconds
900 nanoseconds
Expansion enclosure houses (but does not include)
a) a bank of up to eight BA201-A or BA201-B Memory
Modules to provide a memory expansion of up to
32,768 18-bit words for the AB107/AB108 computers.
b) the BU120-A Memory Expansion Controller (similar
to the Memory Controller of the AB107/AB108).
c) peripheral controllers for I/O expansion.
thi~
(Note that
requires TTL A/Q-DSA Bus Expander, equipment AT310-A
in the main computer enclosure).
The equipment includes the cabinet wiring and power supplies.
It works from 110 vac 50/60 Hz line voltage and can be
field-converted to 220 vac, 50/60 Hz.
89633300 A
1-3
EQUIPMENT DESCRIPTION (cont'd)
GD611-A
The AB107/AB108 can util ize an .optional Memory
Hold Battery, equipment GD611-A,which can be housed
in the computer enclosure. On failure of the
main power the equipment switches automatically
to the battery. This wi,11 supply power for
retaining the memory content in the full memory
of 32 kilowords for at least eight hours, but will
not provide the equipment with normal operating
capabil ity. The battery is recharged automatically
during power-on periods, and is fully charged in
not more than 32 hours. The GD611-A equipment
can also be installed in the BTI48-A Expansion
Enclosure so as to preserve the contents of the
memory expansion of up to, another, 32 kilowords.
PHYSICAL CHARACTERISTICS
.
Dimensions (approximate)
each enclosure
Weight:
1-4
Width
19
inch,
433 mm
Height
15 3/4 inch,
400 mm
Depth
20
inch,
508 mm
The basic complete enclosure weighs
about 80 lbs, 36.4 kg.
89633300 A
ENVIRONMENT
Operating Temperature
40°F to 120°F (5°C to 50°C)
Operating Humidity
Storage and Shipping Temperature
Storage and Shipping Humidity
10% to 90% non-condensing
-40·F to 160°F (-40°C to 70°C)
o
to 100% RH non-condensing
NOTE
Extremes of temperature and
humidity must not occur together.
SYSTEM POWER
Power input
104 - 127 vac,
or
49 - 60.6 Hz, single phase,
600 VA
198 - 264 vac,
49 - 60.6 Hz, single phase,
600 VA
Note:
the equipment can be field-converted from one voltage range to the
other (see Section 3).
Equipment ground
The equipment chassis is connected to the third (ground) lead in
the line cord.
It must be connected to a good ground (refer to
Site Preparation Manual, publication No. 60437000).
The logic ground of the equipment is isolated from the chassis.
It should be connected to the general logic ground of the
ins ta 11 a t i on.
89633300
A
1-5
SECTION 2
OPERATION AND PROGRrut4ING
OPERATION AND PROGRAMMING
PROGRAMMING
For programming information refer to the 1784 Computer System Reference Manual,
Publication number 89633400.
OPERATION
This part describes the switching on and operation of the computer using the
controls and indicators on the Programmer's Console (front panel). The console
is illustrated in Figure 2-2, the controls and indicators are described in
section 6 of the 1784 Computer System Reference Manual, Publication number 89633400.
SWITCHING ON PROCEDURE
After the computer has been installed, checked and the initial operation procedure
carried out (Section 3), the computer may be switched on by performing the
following steps:
1.
Connect the main computer enclosure (equipment AB107/AB108) to the
power outlet by means of the power cord and apply the power by
sw i· tch i ng on the AC POWER sw itch a t the top of the enc los u re rea r
panel (Figure 2-1).
ENCLOSURE REAR PANEL
TO LINE
POWER
OUTLET
POWER SWITCH
SOCKET FOR AC LINE CORD
89633300
A
2-1
2.
Switch ON the dc POWER switch on the Programmer's Console front
panel (see Figure 2-2).
The indicator above the switch should
1 i gh t.
WARNING
If the indicator does not light or if
any other fault is suspected, the
computer must be switched off immediately
by turning off the AC POWER switch at the
top of the rear panel.
Refer to Section 6
for further procedures.
EXPANSION ENCLOSURE FRONT PANEl
DC POWER SWITCH
3.
If an expansion enclosure (equipment BT148) is connected, carry
out steps (1) and (2) above for the expans ion enclosure.
The control s
on the expansion enclosure are in the same relative positions as those
on the main computer enclosure.
WARNING
Should it become necessary to switch off
the computer always switch off the
expansion" enclosure first at the rear
panel AC POWER switch.
2-2
89633300 A
...
(I)
en
..,N
U
c
..,:
CD
• .c:u
~ OJ
-
~
c(
0:0
~~
~O
~~
0°
lH b
:::;)~
""""
0
c(
CD
•.,.
.::11
~
U
C
...
-,:a
o
u .
...
;
~
CD
..¥
u
o
U)
Figure 2-10
89633300 0
AC Power Switch and Connection
2-3
INITIAL CONDITIONS AND OPERATION
NOTE
The manual controllers and indicators on
theProgranmer's Console (front panel) are
shown in Figure 2-2 and are described in
Section 6 of the 1784 Computer System
Reference Manual, Publication number 89633400.
Set up initial conditions by the following procedure (use the controls on the
Programmer1s Console).
1.
2.
2-4
The installation has up to 32K word memory:
1.1
Press MASTER CLEAR pushbutton.
1.2
Set Mode switch (65K/32K) to 32K.
1.3
Set ENTER/SWEEP switch to ENTER.
1.4
Set INSTRUCTION/CYCLE switch to its central (COMPUTE) position.
1.5
Set PARITY FAULT STOP switch to the central (off) position.
1.6
Set SELECTIVE STOP and SELECTIVE SKIP switches to the down (off)
position.
1.7
Press the GO pushbutton.
1.8
Press MASTER CLEAR pushbutton.
The installation includes memory expansion (equipments BU120-A and
BA201-A or BA20l-B) in the expansion enclosure (equipment BT148)
and ,therefore has more than 32K (but less than 65K) words memory:
2.1
Press MASTER CLEAR pushbutton on the main computer.
2.2
Set Mode switch (65K/32K) to 65K on the main computer.
2.3
Set ENTER/SWEEP sw itch to ENTER.
2.4
Set INSTRUCTION/CYCLE switch to its central (COMPUTE) position.
89633300 A
2.5
Set PARITY FAULT STOP switch to the central (off) position.
2.6
Set SELECTIVE STOP and SELECTIVE SKIP switches to the down (off)
position.
2.7
If the full complement of eight memory modules is installed in the
2.8
expansion enclosure: set P register to FFFF 16 •
Press the GO pushbutton on the main computer.
2.9
Press the MASTER CLEAR pushbutton on the main computer.
The computer may now be operated.
NOTE
Do not switch SELECTIVE SKIP or
PROGRAM PROTECT switch when
computer is in RUN operation.
BATTERY OPERATION
Introduction
On failure of the external ac power the computer automatically switches to
the Low Power Data Retention (LPDR) mode of operation, and so connects the
optional Memory Hold Battery, equipment GD6ll-A. In this mode, the battery
(if installed) supplies the power to retain the memory content in the full
memory of 32 kilowords, but the equipment does not have normal operating
capability. The battery, when installed, provides power for'LPDR operation
for at least eight hours when fully charged. It is recharged automatically
during normal operation and reaches full
89633300 F
charge in not more than 32 hours.
I
Memory Expansion
I The
Memory Expansion Controller, equipment BU120~Af and the BT148 Expansion
Enclosure provide the same facilities for power failure to the memory expansion. Thus with a Memory Hold Battery, equipment GD611-A, installed in
the expansion enclosure, the full memory content can be retained for eight
hours after fai lure of the external ac power.
Operation
Failure of the external ac power is shown by the POWER indicator light and
all other indicators going dark during operation. If this happens, check
the external ac supply. If this failed because of no voltage or voltage
reduced under allowed tolerances (see section 1) System Power) this is indicated by "brown out II of illumination. The battery will conserve the contents of the memory for eight hours. Operation of the computer may be resumed as soon a.s ac power returns. If the ac power appears to
be in order
but the front pane 1 ind i cators are st iI' dark, swi tch off the AC POWER
switch at the top of the computer rear panel (figure 2-1) and refer to
section 6.
WARNING
Do not sw itch off the f ron t pane 1
DC POWER switch.
2-6
• IIi I: 'l
·
I-
•·
-fo-
I--
·
~~
en
I--I--
III
~_I
=I
[±l-II
I
l·t
E)-Jl
a-II, ~>:;:
sO
°i 01 O-[]
OaE)
0, 01 0-8 ID
01 oi O-I!J aD
a
'.
~
:-1
;-1
~
I
i
~
j
O~[]
~.
0 1 01 O-E] J~D
•
0'_
1
0
10
o
·EiI
0;
-,".
I
Figure 2-2.
89633300
A
Computer Front View.
(Programmer1s Console, Controls and Indicators).
2-7
SECTION 3
INSTALLATION AND CHECKOUT
INSTALLATION AND CHECKOUT
INTRODUCTION
This section provides installation procedures for the AB107/AB108 computers.
To install peripheral equipments refer to the appropriate Customer Engineering
or Installation manuals.
Refer also to Control Data Mini Computer Systems,
Site Preparation Manual, publication No. 60437000.
UNCRATING
INSPECTION
The equipment is packed in cartons with adequate packing material in the carton
to isolate it from shocks in transit.
must be made before uncrating.
A preliminary inspection of the carton
Evidence of damage must be noted and reported
immediately (refer to Field Procedures Guide).
UNPACKING
To unpack the equipment lay each carton in turn on a clean smooth flat surface.
Cut the sealing tape of the carton, open out the flaps,
re~ove
the packing
material on top and sides of the equipment and lift out the equipment onto the
clean surface beside the carton.
Check the contents of each carton against
packing (consignment) list and inspect each item for transit damage (dents,
scratches, signs of breakage).
Note and report damaged or missing parts
(refer to Field Procedures Guide).
CRATING INFORMATION
Consult Control Data procedure 8.504.00 in the Customer Engineering Field
Procedures Guide.
89633300
A
3-1
INSPECTION AND PREPARATION
Inspect the main computer enclosure and the expansion enclosure BT148
(if ordered) as follows:
a.
Mechanical inspection
*
Inspect the enclosure for superficial damage, loose cables and screws
*
Open the enclosure
*
Check the Identification Plates on the right hand side of the enclosure
(inside the door).
Make sure that the equipment supplied corresponds
to the Customer1s order
*
Check that all the printed wiring assemblies corresponding to the
equipments shown on the Identification Plates are inserted in their
proper slots (see Fi gures 3-1, 3-2)
I f necessary insert them and
stick the corresponding Identification Plate on the right side of
the enclosure interior.
*
Check that the computer enclosure corresponds to the Memory Modules
supplied:
I
Enclosure
main
expans ion
I
ABI07
AB108
BT148
BT148
Computer Cycle Time
900 nsec
600 nsec
Memory Module
BA201-B
BA20l-A
*
Check that each printed wiring assembly is properly seated
*
Note serial number and part number of equipments suppl fed
for future reference.
This information is written on the
Identification Plates.
00
\.D
(j\
DECODER
W
W
W
ALU (LEAST SIGNIFICANT
o
o
ALU (MOST SIGNIFICANT)
"
MEMORY CONTROL
MEMORY ADDRESS
1111111
EIGHT
MEMORY
MODULES
I
mI
AQ BUS
TIMING
rL
/O INTERFACE
CONSOLE INTERFACE
i
DSA BUS
AQ BUS
'11 I'fi'
TTY CONTROLLER
IIII II I III II I II
CENTRAL
PROCESSING
UNIT
CARTRIDGE
DISK
DRIVE
CONTROLLER
:.-
......
0
CIt
%
:;;
~
'"::u
CIt
'"
0
i
0
0
:.- :.CIt
CIt
PHASE
NRZI
MAGNETIC
ENCODING
TAPE
TRANSPORT FORMAT-.
TER
!coNTROLLER
c
~
6
-< ::u ~
::u
0
0
%
~
0
0
0
:.-0 ~ ~ i
~
:.- :.- ::u
CD 0
:.Z
r-
'"
~
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 II 10 9 8 7 6 5 4 3 2
I
,
PWAI S part of equipment
ABI07/ABI08
NOTES
11.
W
I
W
IIIIIIII
The Memory Control board and-the Memory Address board together form the Memory Controller.
This is similar to equipment BUI20-A in the Expansion Enclosure.
2. Memory modules must be installed sequentially from slot 29. For instance, if equipment contains
16K, four modules are installed in slots 29 through 32.
3. See section I for definition of equipments.
Figure 3-1. Card Placement Slot-Assignment: Main Computer Enclosure
-
I I
r?r
DSA BUS
\N
I
.c:-
MEMORY
CONTROLLER
J,
I
EIGHT
MEMORY
MODULES
!6 ~ 34 33 32 31 30 29 28 27 2e
DSA BUS
I
I
11-,
II I I'
I
OPEN
25
/Q BUS
A/Q BUS
DSA BUS.
A/Q BUS
I
I
OPEN
OPEN
24 23 22 21 20 19 18 17 16 15 14 13 12 II 10 9 8 7 6 5 4 3 2
I
NOTES
1. The Memory Control board and the Memory Address board together form the Memory Expansion Controller, equipment number BUI20-A.
~
2. Memory modules must be installed sequentially from slot 29. For instance, if equipment contains
16K, four modules are installed in slots 29 through 32.
~
~
Q
o
~
3. See section 1 for definition of equipments.
Figure 3-2. Card Placement Slot Assignment: Expansion Enclosure
b.
Electrical inspection and preparation
*
Check the ac line voltage available
*
The equipment can accommodate one of the following nominal line
voltages:
Note:
*
either
110 vac,
50-60 Hz, single phase
or
220 vac,
50-60 Hz, single phase
the exact specifications are given in Section l.
Check the enclosure Identification Plate for the line voltage of the
enclosure.
If this coincides with the one available, skip the next
paragraph and proceed to the one after;
if the enclosure line voltage
is not the same as that avai 1able, proceed with the modification as
described in the next paragraph.
*
To modify the enclosure (main or expansion) to allow it to accommodate
a line voltage (110 vac or 220 vac nominal) other than it is connected
for, proceed as follows:
make sure that the enclosure is not connected to line voltage
remove the power supply heat shield by removing its retaining
screws on the inside of the enclosure front cover (refer to
Figure 3-3).
89633300 F
3
I
F4
r~
~
•
•
•
-
r---
ll~
•
"
I
I
Figure 3-3.
3-6
•
•
•
Power Supply Heat Shield and Retaining Screws
8.9633300f
connect the shorting links on TB2 of the power supply connection panel
according to the supply voltage available. See figures 3-4 and 3-5.
NOTE:
The view in figure 3-4 is exact for series A12 and down. Three areas,
marked PC, PS, MH in figure 3-4, were physically altered in series
A13 and up, including type identifiers C and D.
PC: The soldered connections of the programmer's console cable to
the programmer's. console card were ~eplaced by two horizontal
connectors, which are mounted in the same area and are marked
J20 and J21 on the nearby enclosure wall.
This change affects the procedure for removing the console card.
PS: The three soldered connections to the power supply were replaced
by a single vertical connector.
This change affects the procedure for removing the console card.
MH: The route of the main harness to the backplane under the cardfile
was shifted away from the enclosure wall towards the center.
This change does not affect the procedure for removing the card.
SHORTING LINKS FOR 110VA.C INPUT
NOMINAL INPUT
VOLTAGE
110 vac
SHORTING LINKS FOR 220VAC INPUT
SHORT I NG LINKS
ON TB2 TERM INALS
1-2, 3-4-5, 6-7-8,
INPUT TO
TERMINALS
3, 7
9-10
220 vac
89633300 F
2 - 3,
5 -6 ,
8 -9
3, 7
3-7
PC
I
Figure 3-4. Inside of Main Enclosure Front Door
_(Not _app 1i ~ab le to ~ l·~eriesi. See ...!'ote on pag!.. 3-7. L
GND
o
•
•
•
I
Figure 3-5.
3-8
Power Supply Connector
Panel
8963330{) F
*
As a further check inspect the power supply connections as follows:
make sure that the enclosure is not connected to line voltage
remove the power supply heat shield by removing its retaining screws
on the inside of the enclosure front cover (unless already removed).
Refer to figure 3-3 and to figure 3-4.
inspect the shorting links on TB2 of the power supply connection
panel and make sure that they are in their correct position. Refer
to figures 3-4 and 3-5.
*
Check fuses:
Fuse
designation
Fl
Function
Current
ac power
8 A for 110 vac
4 A for 220 vac
Speed
(b low)
-
F2
battery
1 A
slow
F3
F4
dc power
5 A
fast
dc aux
100 rnA
slow
Locat i on
Location
refer to
Figure 3-6
Input
unit
}
Power
Figure
3-3
Supply
-
Figure 3-6.
89633300 F
AC Power Switch and Connection
3-9
*
If the system includes the memory back up power source, battery
equipment GD611-A, check:
proper installation of the equipment in each enclosure
(refer to installation procedure)
voltage at the battery terminals (nominal 28 vdc;
for exact
specification refer to Section 1)
If the battery has to be
changed refer to battery installatIon
information at the end of this section.
*
Check for electrical short circuit between conductors on the equipment
power supply cable connector, also between each conductor and logic ground
(do not forget the third conductor).
Use highest resistance scale
on the multimeter and make sure that the AC POWER switch at the top
of the equipment rear panel is OFF (Figures 3-6 and 3-7).
I
*
Check all connections for tightness.
*
Reinstall the power supply heatshield by replacing its retaining
screws (refer to Figures 3-3 and 3-4).
*
If the system includes a BT148 Expansion Enclosure, check that the
equipments match by checking the identification plates on the
enclosure, on the two assembl ies of the Memory Expansion Controller
,
and on each of the memory modules (refer to the table on page 3-13).
Make sure that the main computer and the expansion unit match.
3-10
89633300 F
12.
If the system includes memory expansion (equipments BUI20 and BA201-A or
BA201-B) in the BTl48 Expansion Enclosure and therefore has more than
32K words memory, carry out the following:
Switch off the dc POWER on both enclosures.
enclosure cables (refer to Figure 3-7).
Install the expansion
I
Switch on the dc POWER on
both enclosures.
12.1
Press STOP sw itch on ma i n computer.
12.2
Make sure that the main computer and expansion equipment have
I
the same memory cycle time (see page 3-13).
12.3
Perform steps 1 and 2 above for the enclosure.
NOTE
All control switches (except the dc POWER ON
switch of the Expansion Enclosure) are located
on the main computer front panel.
12.4
Press MASTER CLEAR switch.
12.5
Set Mode switch (32K/65K) to 65K.
12.6
Set ENTER/SWEEP switch to ENTER.
12.7
Set INSTRUCTION/CYCLE switch to its central (COMPUTE) position.
12.8
Set PARITY FAULT STOP switch to its central (off) position.
12.9
Set SELECTIVE STOP and SELECTIVE SKIP switches to their down
(off) positions.
12.10
If the full complement of eight memory modules is installed in
the expansion enclosure:
89633300
F
set P register to FFFF 16 .
12.11
Press the GO pushbutton.
12.12
Press MASTER CLEAR pushbutton.
12.13
Perform steps 12 .. 4, 12.5, 12.6 above.
I
3-11
W
I
..,.
N
COMPUTER ENCLOSURE
Part
Cab le I Number
EXPANSION
ENCLOSURE
Connections
Computer
Expansion
Figure 3-7.
3
4
89658100
89658100
89658500
89658500
5
89802800
2
$0"
w
w
w
0
0
.,.,
33Pl
31Pl
33P2
31P2
23P1A07
_~3Pl B11 (GND)
31Pl
33Pl
31P2
33P2
27P2A23
27P2B21 (GND)
Rear of Enclosures
Equipment Number
Memory Cycle
nsec
I
900
600
E x pan s ion
Me m 0 r y
Enclosure
Contro t 1er
Memory Module
BT148
BU120-A
BA201-B
BT148
BU120-A
BA201-A
Note power supply requirements:
Initial Operation paragraph 4
Insert the Memory Expansion Controller assembl ies (2) and the
memory module assemblies in the slots of the expansion assigned
to them and make sure that they are well seated. (Figure 3-l)
Connect the five cables of the Memory Expansion Controller (refer
to Figure 3-7 and Section 9).
I
Note that the Memory Expansion
Controller (slots 27,28) are wired to slots 31 and 33 through
the back plane.
The flat cables plug into slots 31,33.
*
Connect on each enclosure a length of insulated wire of adequate
crossection to the enclosure ground and one to the Jogic ground
I
lug (refer to Figure 3-7); make sure the wire is long enough to
connect the computer (or expansion enclosure) to the nearest
logic ground outlet in the installation.
Adequate crossection for this ground-wire is considered to be
89633300 F
110 vac line voltage:
AWG 12
llO vac line voltage:
AWG 16
3-13
INSTALLATION
Ensure that there is no obstruction to free air circulation around either
enclosure and that there is enough room to insert connectors and open the
rear cover. See figures 3-8,3-9
for the necessary clearance dimensions
around the enclosure.
I
En'sure that the equipment· is properly grounded by performing the following
for each enclosure:
*
check that the third pin (ground) of the power cord (chassis ground)
connects to a good ground
*
connect the logic ground of each enclosure to the system logic ground
(refer to Figure 3-7 and the paragraphs on preparation of the equipment)
*
I
connect the chassis ground to the system ground.
Refer to the Mini Computer Site Preparation Manual, CDC publication
number 60437000.
Hook up the power by plugging the equipment line cord to the enclosure rear
panel (Jl:
I
.
Figures 3-6 and 3-7) and then to the util ity outlet.
INITIAL OPERATION
The equipment has been fully tested in the factory before despatch.
The
following procedure checks the equipment on first installation on site and
prepares it for operation.
It is assumed that it has been checked as
detailed in the previous paragraphs and any discrepancies corrected.
The computer main enclosure is set up first; only when that is prepared is
the expansion enclosure prepared, if it is part of the installation.
3-14
89633300 F
l
00
\D
Q'\
\,\I
\,\I
\,\I
o
o
/
.
"T1
I
!
I
\(
/
....
/'
II!
I
:.
I
.,..
- t - - .. -
r.
...
I
i
1·---·_
....
\,\I
I
~
.-~
.:t
-..-.
.....
L. __._w
I
i
~'--
..
..
,/
AIR
--
+'!
I!! I
:t'·ml!:If,
~~
~·iiTTtT
y
.... -......-til.
t-.....--.....1
I
j
-, \\
'\'.. \\'L-....
'.
aJ
"
AIR INLETS
__ -4
-1_ ....
Figure 3-8. General View and Dimensions of Main Enclosure: Type Identifier A
'--\'t:-_....
...
-
Type
Identifier
A
AB107-A
AB108-A
BTl 48-A
,f
Type Identifier C
Type Identifier 0
AB107-C
AB108-c
B1148-c
AB107-D
AB 108-D
BTI48-D
* Type identifiers C
16~40
Tc) FAN:
eAst
*
,
I
I
and D have two fans
installed in the
base of the enclosure.
I Figure
3-16
3-9. External Dimensions of Main Enclosure: Type Identifiers A,C,D
89633300 F
INITIAL OPERATION - Continued
The Programmer's Console (front panel) controls used in the following are
described in Section 6 of the 1784 Computer System Reference Manual,
publication number 89633400.
The console is shown in figure 2-2 of this
manual.
1.
Open the front cover of the enclosure and pullout all the printed
wiring assemblies from their connectors but leave them in their slots.
2.
Turn on the AC POWER switch at the top of the rear panel (see figures
I
3-6 and 3-7). Examine the enclosure to see that all blowers work.
NOTE: The number of blowers is four or six, depending on the
type identifier. Refer to Maintenance Section 6.
If there is no airflow, or some other fault is detected, switch off
the equipment immediately using the emergency shut-down procedure on
page 6-3. Location of the air inlets and outlets is shown in figures
I
3-8 and 3-9.
3.
Turn on the DC POWER switch on the operator's console (enclosure front
panel - refer to flgure 2-2l. The indicator above the switch should
light.
WARNING
If the indicator does not light, or if any
other fault is suspected, the equipment
must be switched off immediately by turning off the AC POWER switch at the top of
the rear panel. See page 6-3 for the emergency shut-down procedure.
4.
Check the power supply voltages (see section 6). Check that the value
of VSS is correct for the memory modules installed: BA201-A or BA20l-B.
See table 6-1 for power supply voltages.
5.
Switch off the DC POWER switch on the Operator's Console and re-insert
the printed wiring assemblies. Make sure that they are well-seated.
6.
Repeat step 3 in this procedure.
89633300 F
3-17
I
INITIAL OPERATION - Continued
7.
I
If the Expansion Enclosure,.e.quipmentiiS;J:l;;#i"Js part of the installation,
repeat steps 1 through 6 for it.
Set up initial conditions by the following procedure:
8.
9.
The installation has up to 32K word memory:
8.1
Press MASTER CLEAR pushbutton.
8.2
Set Mode switch (65K/32K) to 32K.
8.3
Set ENTER/SWEEP switch to ENTER.
8.4
Set INSTRUCTION/CYCLE switch to its central (COMPUTE) position.
8.5
Set PARITY FAULT STOP switch to its central (off) position.
8.6
Set SELECTIVE STOP and SELECTIVE SKIP switches to their down (off)
positions.
8.7
Press the GO pushbut.to,n.·
8.8
Press MASTER CLEAR pushbutton.
Check all registers by entering data in each one.
Note that this check
also serves as a lamp test for the indicators associated with the registers
and the data input keys.
10.
Enter a pattern into memory and correct any problems.
11.
Sweep the memory to check for par i ty error.
NOTE
In steps 8 and 9 refer also to
1784 Computer System Reference
Manual, publ ication 89633400.
3-18
89633300 F
INSTALLATION/REMOVAL OF THE BATTERY (Figure 3-10)
The optional power back-up source, rechargeable battery equipment G0611-A
is normally packed separately.
cover of the enclosure.
In operation, the battery is housed in the rear
To install the battery follow the outline procedure
given below.
Installation of the battery
1.
I
If the battery is new, install the battery, starting from step 4.
If the battery is not new, or if there is some doubt about its state of
charge, go on to the next step.
2.
Check the open circuit voltage of the battery.
2.1 Connect a vol tmeter/mul timeter of 20,000 ohms per volt or more across
the terminals of the battery.
2.2 Measure the open-circuit voltage to be 24.2 vdc or more.
2.3 If not, replace the battery by a fully-tested one.
I f yes, go on to the next step.
3.
Check the full load voltage of the battery.
3.1 Connect two 60 ohm, 5%,10 Watt resistors in parallel across the
terminals.
3.2 Connect the voltmeter.
3.3 Measure the full load voltage to be 24.2 vdc or more.
3.4 If not, replace the battery by a fully-tested one.
If yes, disconnect the multimeter and resistors and install the
battery, starting from step 4.
89633300 F
3-19
-----,
___ - - -__ J
Figure 3-10.
3-20
Rear Cover With Battery
89633300 F
I
4. Remove rear cover of the enclosure by undoing the two th~mb-screws at
the top of the rear cover, tilting the cover back and sliding it out
of its slots.
I
5. Fix the battery to the rear cover (Figure 3-10)using the four screws
and corresponding nuts and washers provided.
6. Install the battery cable provided as follows:
6.1
connect the cable shoes under the nuts on the battery terminals, the
red lead to the positive (+) terminal
6.2
slide the rear cover (with the battery fixed to it) into its slots
and support it by hand
6.3
connect the other end of the cable to connector JO on the enclosure,
inserting the red lead to the lower pin of the connector
6.4
close the rear cover onto the enclosure and tighten the two
thumbscrews
7. Check the battery fuse (refer to Figure 3-6).
If the equipment is newly installed or has not been used with a battery before
perform also the following steps:
8. Load the memory with a pattern and check the pattern under normal
operating conditions.
Record the pattern.
9. Turn off the equipment power supply (Power Off Procedure, section 6)
10. After a few minutes turn on the power again (Power On Procedure, Section 6)
and check that the pattern in the memory has been retained.
If the pattern has. been retained, proceed with normal operation.
If the
pattern has not been retained recheck the battery (see step 1 above).
If
battery is in order proceed to memory diagnostics.
Removal of the battery
89633300 F
Do steps 6, 5, 4,
in that order.
3-21
PROCEDURE TO INSTALL EXTERNAL SHIELDED CABLE ASSEMBLIES (Figure 3-11)
The ground screw to which the external shielded cable is to be attached may
or may not have a cable already attached to it.
Ground Screw Without Cable Attached
1. On the interior surface of the rear connector panel, scrape off a 0.5 inch
(12.7 mm) diameter circle of paint around each of the three lower holes.
2. Open Installation Kit Part No. 89986600 that contains all the attachment
parts needed.
3. Slide the external tooth lock washer onto the screw.
4. Insert the screw and external tooth lock washer into the hole of the rear
connector pane 1•
5. Mount the spring lock washer.
6. Mount the plain washer.
7. Mount one of the two hexagonal nuts.
8. Slide the flat-locking terminal of the cable onto the screw.
9. Mount the other hexagonal nut. Secure the cable into place.
Ground Screw With Cable Attached
1. Remove the securing nut and save it.
2. Slide the flat-locking terminal of the cable onto the screw.
CAUTION
Do not mount more than four external
shielded cables onto the same screw.
3. Mount again the nut that was removed in step 1.
Secure the cable into place, making sure there is proper electrical
contact with the cables already attached.
3-22
89633300 F
H
Addr...
L
~
Add.....
~
Stabl.
Addr.ss
Can Chang.
t OVH
H
Prlohar,e
2
I
V
L
.."
\Q
..,r::
CD
H
Cenable
"
L
~
-
I
-~
III •
03:
""0 CD
c:~
III
..,
H
Read/Write
Data In
(Write Only)
t OVL
-
/ "'"
H
L
Co
-4
(/13
» -.
::::J
Data Out
(Write,Read/Write )
X
Data Can
Change
H
L
O\Q
tpo
"- ~--
~
"<
n
=40mV
RLOAD =IOOA
CLOAD =IOOPF
VREF
CD
III
Data Out
H
( Read)
L
V
~
L
::::J"<
c -.
~ twp
tpw
-
-- --- I',
~g~a
N t V~fi~
Ii
~
'.,.
-Data Out
Valid
, --------Data Out Valid
I
N
W
Data Can
Chanae
Stable Data
1\
'L
CLOCK
Addr...
( Row Only)
Precharge
H
L
H
L
H
Cenable
Read/Write
L
H
2
3
I
I
4
5
6
I
7
8
9
I
I
~
~
/'
"-
L
Figure 4-6.
Memory Timing.
(b) . Refresh Cycles
4-24
89633300 A
The memory unit described here has two versions differing in their basic
cycle times:
~':
the BA201-B module allows a computer cycle time of 900 nanoseconds in
the AB107 equipment
~~
the BA20 I-A modu 1e allows a compute r cyc 1e time of 600 nanoseconds in
the AB108 equipment
One type of memory module (BA201-A or BA201-B) may be accommodated in the
I
enclosures (computer enclosure .and expansion enclosure, equipment BT148)
at anyone time. The memory controller and memory expansion controller are
suitable for both types and only the enclosure supply voltage (V SS ) has to
be changed. This is done at the time of installation of the first memory
module in the enclosure.
The basic timing specifications of the memory units are given in Table 4-2.
TABLE 4-2.
BASIC TIMING SPECIFICATIONS OF THE MEMORY UNITS
,
Symbol
Per i od
MIN
tREF
Time between refresh
tAC
Address to Cenable setup time
tOVL
Precharge & Cenable overlap,
MAX
Chip used in
BA201-A Module
MIN
2
low
tOVH
Chip used in
BA201-B Module
115
MAX
1
UNIT
ms
nsec
30
,
25
nsec
-10
Precharge & Cenable overlap,
high
140
tpw
Precharge to Read/Wri te delay
twp
Read/Write pulse width
tpo
End of Precharge to
165
500
nsec
500
nsec
nsec
40
50
output delay
115
85
120
75
nsec
t ACCl
Address to Output Access
300
135
nsec
t ACC2
Precharge to Output
310
165
nsec
89633300 F
Ac~ess
4-25
DETAILED OPERATION OF THE MEMORY UNIT
To begin a cycle, Precharge is brought low, to approximately VDO potential.
This operation activates the row and column decoders, and also charges all
read and write data lines negatively, i.e., to the equivalent of a logic
"high" state for the P-channel MOS.
(In the discussion which follows,
clocks, etc. are considered "on" at VOO level, and "off" at VSS level.
"High" and "Low" refer to the change with respect to the MOS substrate.)
The decoder circuitry is somewhat faster than the line charging circuitry,
so addresses need not be stable until somewhat after Precharge is applied.
Address data may be provided before Precharge is turned on.
After Precharge and address data have been present long enough for the data
lines to charge and the row and column decoders to stabilize (time tAC after
Precharge is low). the Cenable clock is turned on
low state.
i.e., dropped to its
At this time, the desired read-select line is activated and
the read-data line charging circuits are disabled.
This initiates the
writing of the contents of the 32 cells along the selected row into the
32 on-chip refresh amplifiers, one amplifier for each column in the array.
The data lines begin to discharge selectively, with the signals on them
approaching values corresponding to the complements of the data stored
in the selected row of cells.
As the read-data lines selectively discharge, the Precharge signal is
turned off, i.e., raised high to VSS.
Following this the contents of
the refresh amplifiers are written back into their respective columns;
and after the period !PO the output appears.
This is accompl ished by
the removal of the charging signal on the write-data lines, and closing
a path to selectively discharge these lines.
The cell contents are
restored by activating the write-~elect line corresponding to the
selected read-select line.
The signal level on the write-data
line is a function of the overlap time between Precharge
4-26
89633300 A
and Cenable. If this overlap is too short, the read-data lines will not
have discharged sufficiently when the discharge path from the refresh
amplifiers to the write-data lines is closed.
levels written into the cells may be reduced.
As a result, high (negative)
If, however, the overlap time is excessive, weak lows within the cells may
result in some discharge of the read lines before closure of the write-back
path.
Thus cells with weak lows have higher levels (even weaker lows)
written back into them, eventually resulting in lows changing to highs.
This problem is somewhat aggravated by the small but unavoidable capacitive
coupling between the data and select lines and the cell storage capacitor.
Provision is made for controlling the overlap time in the Memory Control
and Memory Add ress un i ts.
When Cenable is turned on, a current path from VSS to the output is
established, for one column decoder is enabled and all write-data lines
have been charged high (negative).
If the selected cell (the cell at
the intersection of the selected column and selected row) contains a low,
the write-data line will discharge after Precharge is removed and the
output current will be cut off.
If, however, the selected cell has been
negatively charged (high), the output current will continue to flow.
Cenable must remain present for a sufficient time after Precharge turn-off
to allow the contents of the selected row of cells to be refreshed. Even
after Cenable is turned off (raised to VSS ) the addresses must remain
present for about 20 nanoseconds to allow completion of internal operations.
Precharge will not be applied again until Cenable has been off for at
least 85 nanoseconds (see Memory Control operation).
To write new data into the selected cell, with or without a read operation,
all sequences proceed as above.
However, the write line is activated
before Cenable is removed and tpw after the pos:tive edge of Precharge;
this allows the write-data lines to stabilize.
As a result, the read
89633300
A
4-27
data lines are discharged, effectively disconnecting the refresh amplifiers
from the write data lines.
~ path from the data-input line is also
enables into the selected write data 1 ine.
Thus., a direct path from
the data input to the selected cell is established.
A signal on this
input will then overwrite the contents of the cell.
The timing specifications for operating the unit are shown in Table 4-2.
All the time values listed, except t po ' t ACCl are generated by the memory
system. The time designated tpo refers to the time delay observed
between the turn-off of Precharge and the availability of data at the
chip output terminals, and is a characteristic of the unit.
The two access times, t ACCl and t ACC2 represent a combination of system
operating parameters and characteristics of the chip.
Thus the stated
"minimum" values represent the shortest access times which can be
guaranteed when the unit is operated within the limits specified and
with rise and fall times of 20 nanoseconds.
System access times will
exceed these values because of the additional delays and tolerances
introduced by the rest of the system.
4-28
89633300
A
REFRESH TIME
The maximum time interval between accesses to memory cells (t REF ) is specified
as 2 milliseconds for units on the BA201-B module, 1 milliseconds for units on
the BA201-A module.
To guarantee that data is retained within the memory, at
least one read or write cycle must be executed for each row of cells within
this refresh interval.
As the rows are selected by address inputs AO
through A4 at least 32 memory cycles, one for each state of address lines AO
through A4 must be executed in each refresh interval.
These cycles may
result from normal accessing, as in a sequential-access mode of operation of
the memory.
In other cases special refresh cycles must be executed.
In the
Memory System (AB107 equipment) the cells are refreshed every 1.5 millisecond,
in the Memory System (ABIOS equipment) every 1.0 millisecond.
CHIP SELECT
In operation, the Cenable clock also acts as a chip (memory unit) select.
That is, Precharge and write signals may be applied at their normal times
in the cycle, but if Cenable is not applied, the unit will neither deliver
current to the output terminal nor will the contents of any cell be altered;
no refreshing of memory content takes place during such a cycle.
POWER SUPPLY LEVELS
Signal and power supply levels are important to the proper operation of the
unit.
Speed is a function of both the VSS level and clock amplitudes.
In
general, higher amplitudes or voltages result in faster operation. Substrate
This bias improves noise
bias VBB also has an effect on performance.
immunity and prevents parasitic interaction within the device.
89633300
A
4-29
INPUT CLOCK AMPLITUDES
To guarantee operation of the memory chip over the full temperature range
at the speeds specified the clock amplitudes must be maintained at the
specified values.
These are:High:
Low:
The value of the supply voltage (VSS) determines that of the bias voltage
VBB (refer to Figure 4-13 of the Power Supply Regulator and Control Circuits).
SYSTEM CONSIDERATIONS
The memory units are used in a rectangular 18 x 4 array to provide storage
units of 4096 (4K) words of 18 bits each.
S~ch an array with its supporting
circuitry is called a Memory Module, with the main addressing and control
circuits for up to eight modules carried on the Memory Address and Memory
Control units.
These are described in other parts of this seetion and in
Section 5.
Maintenance and safety precautions relating to the Memory Modules and to
the memory units are given in Section 7.
The contents of the memory unit has to be refreshed periodically as it is
a basically volati Ie store.
The memory system, however,', is made nonvolatile for at least 8 hours with the use of a battery and a special
Low Power Data Retention (LPDR) mode of operation.
This is also described
in other parts of this section.
4-30
89633300 A
MEMORY MODULE
The Memory Module is the basic unit of the AB107/AB108 memory system.
It
consists of a 4xl8 array of memory units to give 4096 (4K) 18-bit words
together with' immediate supporting circuitry, all accommodated on a single
50-PAK printed wiring board.
given in Figure 4-7.
The block diagram of the Memory Module is
The memory units are described in previous paragraphs.
The following paragraphs give the description of the block diagram followed
by the function of the auxiliary circuits listed in the table.
Function
Circuit
Level Shifters
adapt TTL logic levels to MOS levels
Cenable-Precharge delay
regulates the overlap (t OVL ' t OVH )
Aux iIi a ry log i c
generates internal control signals
from available control signals
LPDR ci rcu i t
generates the switched supply (Vccs) used
in Low Power Data Retention operation
Data Out Sense Amplifiers
convert the signals appearing on the opencol lector of the memory uni t data out lines
to TTL signals (current to TTL logic
conversion)
i
.
I
~
A description of these circuits is given in Section 5 (Memory Module).
89633300
A
4-31
:J
THE MEMORY MODULE BLOCK DIAGRAM
-J.
:1:
The memory matrix provides the actual storage 1oca tio,,·ii th i n the memory system.
It is an array of four rows of 18 memory units, forming four thousand words of
18 'b i ts each.
The data flow to and from the IlIf;!III1Ory matrix is on the 18 data-i,n and
18 data-out lines corresponding to the 18 bits of each kiloword.
The
data-in lines of the memory units of corresponding bits in the four rows
are connected together in a wired-OR and the same is true of the data
output lines.
A level shifter is incorporated in each of the 18 data-in
lines to adapt the TTL levels from the CPU to the HOS logic levels needed
in the memory matrix.
Similarly the data out lines from the memory matrix
are buffered and level converted in the sense amplifiers.
"
Selectfbn of a particular location in the matrix is achieved In two stages:
first one of the four rows of 18 memory units (one kiloword) is selected
by the corresponding kiloword selector signal (fl<.t):::'·rough lK3).
This allows the memory control signals (Precharge, C:enable) to reach the
if
memory unit-&: of that word. In the second stage th~row and column address
signals, through the address. level shifters, select a particular 18 bit word
within the selected
kiloword •
'.
.
~
The memory control and timing signals perform functions as follows:
r--"'" .
; Cenab Ie
R/W
Read or Wri te
Strobes output data
.
Chooses memory modulei
.... J
4-32
89633300 A
00
\.0
0'
Cenable
Precharge
Delay
w
w
w
o
o
."
Kiloword
4,
Select
(IK0-IK3 )
.
4
•
I
~
4
~~
4
Precharge
Level
Shifter
4
1
T
.. I
ermlnatlon,
CE
-
-
I
I
Memory Matrix
-
4
-
( Y 18)
4
Cenable
Cenable
Level
Shifter
-
Data In Leve I Shi fte rs
Precharge
(Bits 0-16)
4
B
- --
18
Fast Precharge (Bit 17)
4
-
4 x 18 Array of
Separate
Control
Signals
For Each
Kiloword
Memory Units
Forming four
Kilowords
of 18 - Bits Each.
(IKO through IK3)
Read/Write
4
,'4
'5
B
4
R/W .....
R/W
Level
Shifter
r-----
] Common
A'idres:1
Lines to All Units
5
Strobe
Row A,ddress
(ARAO-ARA 4}
5
5
-
Address
Level
Sr.ifters
~18
,
Column Address
{ACA5-ACA9 )
Addres~
5
~ ~~~,~ary
Logic
Strobe
.....
Disable
REF
MDX
Stnbe --+ ] Common
Level
Shifters
I
MD --+ Controls
VCC2
• s(robe ';
". ..
MD
1-----.. B
0
'
I
cnJ
eet
?ILPDR
•
,
VCCS
18 Data Out Lines
MPWRO~-+---'
I.
.s::I
W
W
I Figure 4-7.
Data - out Sense Amplifiers
Memory Module Block Diagram
~
Data flow is shown in
thick lines.
--r=;:=::t..T
2.
Transfer takes place only
when condition i. pre •• nt.
AUXILIARY CIRCUIT FUNCTIONS
Leve t Sh i fters:
TTL to MOS
TTL logic levels are 0.7 volts (low) and 2.0 volts (high).
MOS levels are
A level shifter is needed to
approximately zero volts to VSS (17 volts).
match the two kinds of logic circuits.
The following signals use identical control signal level shifters:
Precharge
Read/Write (R/W)
Address
I
The Cenable signals use the same level shifter but with two components
added. See page 5-23.
Level shifters are also used on the 18 data-in lines to adapt the TTL logic
levels of the incoming signals to the MOS level of the memory circuits.
The Overlap Circuit (Cenable - Precharge Delay)
There is an overlap delay circuit in the precharge line of each kiloword unit
on the Memory Module.
It regulates the overlap timing tOVL and tOVH in
the memory units (see Table 4-2 and the Detailed Operation of the Memory Unit),
and consists of a diode switching network controlling RC delay circuit.
4-34
89633300 F
Low Power Data Retention
During power failure the computer reverts to Low Power Data Retention (LPDR)
mode.
During refresh cycle bursts in this mode none of the TTL logic circuits
receive power.
This circuit controls the V 2 supply to produce the switched
cc
logic (V CCS ) supply, provided the optional power back-up sources battery
equipment G0611-A is installed.
This arrangement preserves the memory
content for up to eight hours (see next subsection).
Data-Out Sense Amplifiers
The open collector outputs of the corresponding bits of the four kilowords on
the module are wire-ORed to form 18 lines.
These are ampl ified in and gated
by the sense amplifiers to form the 18 TTL-compatible output lines of the
memory module.
89633300 A
4-35
LOW POWER DATA RETENTION (LPDR) MODE
POWER BACK-UP
The memory chips are volatile: they will lose their stored charges if they
are not refreshed periodically.
To make the memory system non-volatile,
it is designed to switch over to battery operation automatically in case
of power failure.
A bac·k-up battery, optional equipment GD611-A when
installed can supply power for the retention of the full memory contents
for a period of up to eight hours.
When the utility power fails, the voltage on the dc power supplies
begins to drop. The power supply senses this voltage drop, and
raises the signal RGPWR to the Memory Control.
Due to large storage
capacitors in the power supply, the voltages remain in the
uncritical region for at least one millisecond and the memory
continues to function.
When the Memory Control receives the raised RGPWR signal, it
continues to operate normally for half a mil1 isecond. During this
time the CPU performs a special interrupt subroutine. At the end
of this one-half millisecond period the Memory Control switches to
the back-up mode.
To retain the memory content in the back-up mode the Me~ry Control
will not perform CPU or DSA cycles, but immediately performs a
burst of 32 row refresh cycles in rapid succession and so refreshes
the whole memory. The power supply switches to battery operation.
All circuits which require constant powe~ such as the memory chips,
continue to operate from the battery. All circuits that do not
require power, such as the CPU, are allowed to fail as the util ity
power fails. All circuits which need power only during refresh
burst, such as address drivers, are power switched by the Memory
Control during refresh burst. Since 32 row refresh bursts require
4-36
89633300 A
only 14 microseconds to perform, and refresh bursts are performed
once every 1024 microseconds, the power switched circuits are off
for a considerable time, conserving a significant amount of power.
In the back-up mode the memory chips use most of the power.
When the power supply senses that util ity power has returned, it
switches to util ity power, and drops the RGPWR signal.
The Memory
Control performs one more refresh burst, and then switches to
normal mode operation.
During LPDR operation the Memory Hold Battery (optional equipment GD611-A)
supplies power.
During normal operation the battery is recharged from
the power supply.
89633300
A
4-37
PROGRAMMER'S CONSOLE
The equipment front panel serves as the Programmer's Console: it carries the
switches and indicator lights which enable the operator to control and monitor
computer operations.
The front panel controls and indicators are described in the 1784 Computer
Their layout is shown in
Reference Manual, publication number 89633400.
Figure 2-2 of this manual.
The circuits on the Programmer's Console can be grouped in three functional
areas:
*
*
*
Control switches and indicators and associated circuits;
Register selectors;
Data-bit selection circuit.
These circuits are described in SectionS of this manual.
4-38
89633300 A
INPUT/OUTPUT
Any peripheral controller that uses the A/Q channel or the DSA channel may
I
be accommodated in the ABI07/ABI08 equipments. The following table is a
partial list. See the preface for more information.
CONTROLLER
EQUIPMENT No.
I
CONTROLLER DESIGNATION
Part of ABI07/ABI08
Teletypewriter
FA716-A
Cartridge Disk Drive Controller (CDDC)
FA442-A
ICL Magnetic Tape Transport Controller (MTTC-ICL)
Fv497-A
FA446-A
ICL Phase Encoding (PE) Formatter
LCTT Magnetic Tape Transport Controller(MTTC-LCTT)
Fv618-A
LCTT Phase Encoding (PE) Formatter
(TTY)
The Teletypewriter (TTY) Controller forms part of the ABI07/ABI08
equipment; the other controllers are separate equipments and are
accommodated in prewired slots within the main enclosure (ABI07/ABI08
equipment).
Other controllers may be connected to the compyter through
one of the two access channels, the non-buffered AQ channel using the
A and Q registers and the Direct Storage Access (DSA) channel.
In the following a short functional description of the TTY controller is
given as well as the pin assignment and timing diagrams for the AQ and DSA
channels.
The TTY controller logic circuit diagrams are given and are
described in detail in Section 5.
Refer to the 1784 computer Input-Output
Specification Manual, pub! ication number 89637100 and appropriate peripheral
controller manuals for further information.
89633300 F
4-39
THE TELETYPEWRITER (TTY) CONTROLLER
The TTY Controller can interface the computer CPU with a Teletypewriter
Terminal and with a Conversational Display Terminal (COT). It provides for
communication at 9600, 1200, 300 or 110 bauds. The baud rate is selected
by inserting a jumper pI ug in the appropriate 10cat ion on the board.
DIRECT STORAGE ACCESS (DSA)
The DSA channel provides fast external access to the computer (equipment
AB107/ABI08).
Access connections are available on identical pins of
preassigned slots of the main enclosure (equipment AB107/AB108) and of the
expansion enclosure, equipment BT148 (refer to Figures 3-1 and 3 w 2)
I
Printed wiring boards conforming to 50-PAK specifications can be
accommodated in these slots.
on the DSA channel.
Figure 4-8 shows the timing of the signals
The pin assignment for the slots allocated to
controllers using the DSA channel is given in Table 4-3.
DSA Circuit Connections
The DSA channel is designed to be used with TTL 2-input NAND buffers
(IC 7438, PN62031200).
Each DSA line is terminated by a 270 ohm pull-up
resistor (to V ) in the CPU. Each input to the CPU loads the linewithup to
cc
20 TTL load units. DSA output lines should be loaded with one TTL load
unit or less.
Scanner conditions are not prewired and should be made at the time of
installation (refer to customer engineering manual for appropriate
I
controller). See the list in the preface.
4-40
89633300 F
TABLE 4-3.
OSA CHANNEL PIN ASSIGNMENTS
P2
P1
I
A
S005
so06
5000
S012
SOll
so03
so04
Me
S'R'SM
SRQ
PIT
S016
m
SOl7
32kW
i
!I
I
SAOS
SA09
SAIO
SAlt
SA12
SA13
GNO
SA14
SA15
I
A
B
5001
1
5002
2
so07
3
so08
4
S009
5
SOlO
6
7
8
S013
9
S014
10
11
12
SS
13
SPI
14
S'iIT
15
16 SCRiM (SRi)
SVIO
17
18 AUTOLOAO
19 SC FMM (S'FJ)
20
SWRITE
21
22
SAvO
23
SAO 1
24
SA02
25
26
SA03
SA04
27
SA05
28
29
SA06
30
SA07
31
1
B
1
GNO
i
2
3
4
5
6
7
8
9
10
11
Vcc
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
GNO
--
NOTES:
1.
Signal polarity
Address bits (SAOO~SA15) are active high.
Oata bits (SOOO~S015) are active high for OSA transfers from the computer (Write).
Oata bits (SOOO~S015) are active low for OSA transfers to the computer (Read).
All other signals on the OSA bus are as indicated (overlined: active low).
Power Supply v =+5V.
2.
cc
Total usage of all controllers on A/Q and OSA buses should not exceed 30 amperes
in each enclosure.
~
GND = logic ground.
89633300 A
4-41
.
fI)
CD
en
IV
Q.
...
)(
CD
C
...0
1-
.l
-,.-
Z
J.
L.
1
CD
'+CD
U
L.
..
-- !
Q
...
In
CD
z0
.J
...~
--- --fI)
fI)
kI
a::
I~
8
c
!
-- -
5z
kI
iLl
11.1
i I
Figure 4-8.
4-42
-
----a::
kI
;~
-i
~8
-...
00
-~-
III
...~
~·ft
tC
Q~
...
-
~
I11.1
~
iE
f
DSA Channel Timing
89633300 A
NOTES to Figure 4-8.
1.
Signal names:
TAC :
SRQ:
2.
DSA Access Time
Memory Access Request from DSA channel.
Timing
1 784 - 1
1 784 - 2
Remarks
minimum
(nsec)
A.
B.
-
c.
-
D.
E.
F.
G.
H.
J.
K.
L.
N.
S.
-
TAC
50
390
-
110
70
-
0
150
0
typ i cal
(nsec)
440
600
-
-
maximum
(nsec)
-
-
-
605
-
-
655
900
10
-
-
-
-
215
285
220
-
855
1455
89633300 A
-
typical
(nsec)
70
175
120
60
490
-
minimum
(nsec)
50
-
-
maximum
(nsec)
110
200
245
60
705
-
-
-
320
470
330
-.
1240
190
120
0
210
0
10
-
2140
at maximum
DSA access
rate
wi th DSA
Pr iori ty
without" DSA
Priori ty
4-43
NOTES to Figure 4-8 (Cont'd.):
3.
Refresh cycle time:
4g0 nsec once every 32 microseconds (600 nsec Memory)
735 nsec once every 48 microseconds (gOO nsec Memory)
4.
Modes of Operation
Worst Case
·The maximum DSA access time (TAC ) oC'curs whe'n the memory system performs
CPU access cycles 'and successive Refresh cycles.
DSA Priority signal active
The memory system cannot perform CPU cycles.
The DSA access, time (TAC )
is minimum; It is increased by the regular occurrence of Refresh cycles.
Successive DSA requests
The memory system cannot perform CPU cycles on the memory bank addressed
by the equipment on the DSA channel.
The DSA cycle time Is equal to the
memory cycle time (600 nsec or, goo nsec).
The DSA cycle time will be
Increased by the Refresh cycles.
Note that on single-bank operation
no CPU access can occur if the DSA requests are generated fast enough.
4-44
8g633300 A
A/Q CHANNEL
This is the
non~buffered
bi-directional input/output (I/O) channel for the
computer (equipment ABI07/ABl08).
It util izes the 16-bit A and Q registers
of the CPU.
The Q register contains the address of the peripheral equipment;
the A register contains the data equipment status and director functions.
Access connections are available on identical pins of preassigned slots of the
main enclosure (equipment ABI07/ABI08) and of the expansion enclosure equip~ent
BTl48 (refer to Figures 301a, 30Ib).
Printed wiring boards conforming to 50-PAK
specifications can be accommodated in these slots (refer to AB107/AB108 Computer
Input-Output Specification Manual, publ ication number 89637100).
Output on A/Q Channel
A single word is output from the A register whenever an output instruction
is executed by the computer.
The presence of the output data is signified
by the active state of the write I ine.
The peripheral equipment whose address
is in the Q register should respond with a Reply or a Reject signal within
4 microseconds. The computer generates an internal Reject and reinitiates
execution of instructions if no response is received from the device within
12.8lJsec (ABI08) or, 19.2lJsec (ABI07). If a Reply is received by the computer,
the next instruction executed is the one following the output instruction
(P+l).
If an external Reject is received, the next instruction executed
is located at P + 1 + 6, where 6 is the lowest eight bits of the output
instruction, the highest bit of 6 being a sign bit.
If an internal Reject
is generated the next instruction executed is located at P + 6.
P is the
address of the output instruction.
89633300 C
4-45
Input on A/Q Channel
A single word is input to the A register whenever an input instruction
is executed by the computer. The request for data by the computer is
signified by the active state of the read 1 ine. The peripheral device
whose address is in the Q register responds with a Reply when data is
available to the A register.
If no data is available, the peripheral device responds with a Reject.
In either case, the peripheral device must respond with a Reject
Reply within 4 microseconds. If no response is obtained in 12.8psec
(AB108) or 19.2psec (AB107), the computer generates an internal Reject.
Reply causes the computer to go to address P + 1, where P is the address
of the input instruction. An external Reject causes the computer to go
to address P + 1 + 6, where 6 is the lowest 8 bits of the input instruction,
the highest bit of 6 being a sign bit. Internal Reject causes the
computer to go to address P + 6.
Status on A/Q Channel
Each peripheral device must have one or more codes which can be loaded
into the Q register. When the computer executes an input instruction the
status of that device will be loaded into the A register. All devices
must respond to status requests wi th a Reply s inee the status must always
be available within 4 microseconds. If a no response is received by the
computer, it gen~rates an internal Reject after 6.4 psec (ABI08) or
9.6 psec (ABI07).
4-46
89633300 C
A/Q Channel Access
A/Q Channel accesses are available on identical backplane pins of prewired
card slots of the equipments.
va r i ous signa 1s •
Table 4-4 lists pin assignments for the
A/Q Channel Timing
Figure 4-9 describes timing restrictions of the A/Q channel. In addition
to the signals shown, a timing pulse is generated 135 nsec (±40 nsec)
before a Read or Write signal can appear on the A/Q channel. The timing
pulse is active for 75 nsec (±20 nsec). For more detailed signal
description and timing, refer to I/O Specification manual number 89673100.
A/Q Channel Loading Rules
Each signal (data or control), transmitted from a peripheral controller to the
CPU .in the A/Q channel, must be driven by an open-collector NAND buffer
(IC Type 7438, CDC PN62031200).
Each input line is terminated at the input
to the receiver on the CPU by a 180 ohm pull-up resistor (to V ).
cc
loads the line with 20 TTL loading units.
The input
Each device on the A/Q channel is allowed to load any line from the CPU by
one TTL load unit. The data bus (A register) is bi-directional.
Figure 4-10 gives examples of typical input, output and bi-directional 1 ines.
89633300
A
4-47
TABLE 4-4. A/Q. CHANNEL PIN ASSIGNMENTS
P2.
P'I
A
A05
A06
AOO
m:
All
)ijJJ
A04
TP
A)5
0.00
0.02.
0.04
0.06
Q,08
0.10
0.12.
rui
WEZ
READ
REPLY
PRTM
GND
Notes:
I
1
2.
3
4
5
6
7
8
9
10
Jl
12.
13
14
15
16
17
18
19
2.0
2.1
2.2.
2.3
2.4
2.5
2.6
2.7
2.8
2.9
30
31
B
A
-AO)
I
m
m
I
2
3
4
5
6
7
8
9
10
Q,O)
11
12
A02.
A07
A08
A09
GND
~
CMI
GND
0.03
0.05
0.07
0.09
0.11
0.) 3
0.)5
WRITE
REJECT
RC
1) Q.OOiQ.15 are active high;
Vcc
13
14
15
16
17
18
19
2.0
21
22
2.3
2.4
2.5
2.6
2.7
28
2.9
30
31
B
GND
all other signals are active low.
2) Vcc ~ +5V. Total usage of all AQ. and DSA controllers should not exceed
30 amps in, each enclosure.
3) GND = logic ground
4-48
89633300 A
INpuT OPERATION
j At1T. b
____~--~II~______~
DATA
-,Bje-
READ
L
-.J
REPLY OR REJECT
~SEC MIN
A
=
0
B
=
0.0 ~SEC MIN (ci) COMPUTER
C
= 0.0 "SEC
(q)
E----~~________~r_l~___
PERIPHERAL DEVICE
D
=0
"SEC MIN (ci) PERIPHERAL DEVICE
E
=
"SEC MAX (ci) PERIPHERAL DEVICE
4.0
0.2 ~ SEC MIN (ci) PERIPHERAL DEVICE
MIN (ci) PERIPHERAL DEVICE
OUTPUT OPERATION
-.J
DATA
.... A
REPLY OR REJECT
L
I.
A
= 0.1
B
=
O. 0 ~ SEC MIN ~ COMPUTER
C
=
O.O.~ SEC
~SEC
I I~------~~___
~
WRITE
L
U
j-j.--------i.1 D t-I A ' -
MIN ~ COMPUTER
MIN ~ PERIPERAL
-tBI-
.mL..-..,;
______
...jCI-
E
./
DEVICE
D
= 0.1
E
=
~ SEC
4.0 ~ SEC
~!lL-.-_
MIN (ci) COMPUTER
MAX (ci) PERIPHERAL DEVICE
0.2 ~ SEC MIN ~ PERIPHERAL DEVICE
NOTE:
THE ADDRESS BITS WILL BE ON THE CHANNEL A MINIMUM OF
0.1 ~SEC BEFORE AND AFTER THE READ OR ~RITE SIGNAL.
Figure 4-9.
89633300 A
A/Q Channel Timing
4-49
Vee
OUTPUT
LINE
I
204
~
1
1
180
Vee
INPUT
LINE
1
146
I
180
~--'---~----~I~--~1L~2=~~r--
I
Vee
I
I
I
I
"'I-
I
204
....
r
:·,80
I
I
I
BI-DIRECTIONAL
LINE
146
I
I
COMPUTER
NOTE:
I
I
I
I
I
I
I
I
I
BACKPLANe:'
CONNECTIONS
.A
I
•
204
I
PERIPHERAL
CONTROLLER
~
146 can be replaced by any TTL logic circuit gate
providing that the line is loaded by only one load unit.
Figure 4-10.
4-50
1..
146,
I
I
I
.A
I
i
I
1
A/Q Channel Input/Output Lines
89633300 A
INTERRUPTS
There are 15 external interrupt positions provided, each brought out on an
individual backplane pin.
These are used to interrupt the computer program
on specified conditions arising in the peripheral devices. The computer
program determines the interrupt priorities, that is, the order in which
the interrupt requests are ~ealt with in the cQmputer. The program acts
th-rough the computer mask (M) register. Should two interrupts occur
simultaneously, the hard-wired order of interrupts will- determine priorities
(refer to table 4-5).
Interrupt Access
The 15 external interrupts are accessible on the backplane pins of the main
enclosure. A single wire (part number 89724702) is required to connect
an interrupt source to the appropriate interrupt level.
I
Table 4-5 1 ists
the pin assignments for the interrupt levels. Interrupt signals are active
low.
See section 3 for the installation procedure of the interrupt cable.
For the interrupt connections for controllers installed in the BT148 expansion enclosure, refer to Hardware Maintenance Manual publication number
I
89758600 of the AT310 TTL A/Q-DSA Bus Expander.
89633300 F
4-51
TABLE 4-5.
INTERRUPT ACCESS PIN ASSIGNMENT
ABI07lABI08
Card Slot
Line
Pin
o
25
25
25
25
25
25
25
26
26
26
26
26
26
26
26
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PI Bl 0
PIA07
P1B07
PIA05
PIA06
PIB06
PI B05
PIAIO
PIBIO
PIA07
PI B07
PlA05
PIA06
PI B06 .
PIB05
NOTE: Interrupt priority levels are in reverse
order of interrupt line numbers.
_._-_ _-
........
'---_
4-52
..
------------"
89633300 F
Timing Considerations for Two Bank Operation
The computer can have one or two memory banks (see paragraphs on Memory
System in this section), each with a maximum of 32K words. The two banks
work independently. Any memory request using an address of 7FFF16 or less
will access the lower bank. Any memory request using an address of 8000 16
or above will access the upper bank.
logic.
The two banks have identical control
Each bank can perform three types of memory cycles:
refresh cycle,
DSA cycle or CPU cycle. The DSA has priority over the CPU and refresh cycles
have priority over the other two. DSA and CPU cycles are initiated by
external signals while refresh cycles are initiated by internal timing logic.
If the CPU accesses one bank, the DSA can simultaneously access the other
bank. In this case, the CPU and DSA can work at maximum speed subject to
refresh cycle requirements.
If the CPU and DSA access the same bank, then memory cycles are shared
between them. If the CPU requests a memory access while a DSA cycle is
in progress, it must wait until the DSA cycle is finished. If a refresh
cycle is pending when the DSA cycle ends, the CPU must also wait for that
refresh cycle to be completed.
Similarly, if the DSA requests access while a CPU cycle is in progress,
it must wait until the CPU cycle is finished. If a refresh cycle is
pending when the CPU cycle ends, the DSA must also wait for that refresh
cycle to be completed.
89633300 A
4-53
Successive DSA cycles: if a DSA cycle is followed by another one within the
maximum delay specified after the start of RESUME (see Figure 4-8, note 2)
and the CPU is waiting to reference the memory, then the second DSA request
will be taken and the CPU forced to wait. This is because the memory system
gives the DSA priority over the CPU. Thus the DSA can obtain continuous
memory cycles and block CPU memory accesses by sending memory requests at
a high enough rate. This does not apply in two bank operation because the
CPU can access the upper bank while the DSA sends a request to the lower bank.
If the DSA then tries to access the upper bank it has to wait until the
CPU access ends.
The DSA can unconditionally block all CPU memory accesses with the signal
PRIORITY. This allows the DSA to access both banks at maximum speed,
except when it has to wait for a refresh cycle.
Note that the speed of data transfer is a functton of the computer clock in
the Timing circuits.
This clock is 1.5 times faster in the AB107 equipment
than in the ABl08 allowing proportionally fasterDSA access.
4-54
89633300 A
POWER SUPPLY
The following paragraphs descdbe the functions and organization of the power
supply unit.
The power supply unit is part of the main computer enclosure
(equipment ABI07/ABI08) and the expansion enclosure (equipment BT148)
I
Detailed circuit and connection diagrams are given in Section 5 of this
manual.
ELECTRICAL
The power supply receives the main line-voltage through the three-conductor
flexible power cord which plugs in the socket at the rear of the
enclosure.
The AC POWER switch and input fuse are located adjacent to the
input socket (Figure 2-1).
The power supply unit provides all the operating
supplies for the equipment within the enclosure, including the charging and
protection circuits for the backup source, Memory Hold Battery, equipment
G0611-A.
The supplies,with brief
characteristic~
are lis ted in Tab Ie. 6-1 .
The input
ac line specifications are as follows:
or
Note:
104 - 127 vac, 49 - 60.6 Hz, single phase, up to 600 VA
198 - 264 vac, 49 - 60.6 Hz, single phase, up to 600 VA
the equipment is normally suppl ied for nominal Il0V operation.
It can be field converted to nominal 220V (refer to Section 3).
89633300 F
4-55/56
I
MECHANICAL
The power supply unit is mounted on the hinged front door of the computer and
expansion enclosures (Figure 3-2).
Access to it may be obtained by opening the
front door of the enclosure.
It is cooled by a blower mounted immediately
beneath it (in the door).
The power supply may be field calibrated (refer to
Section 6).
The memory hold battery (equipment GD611-A) when installed, is situated on the
inside of the equipment rear cover.
The battery fuse is part of the input
circuit situated at the rear of the enclosure (Figure 2-1).
WARNING
The power supply does not use a main isolatin'g 1 ine-transformer
at its input; its circuits between the ac line input and the
isolating networks are therefore at line voltage.
Do not handle
the powe r supp I y un i t wh i I e the compu te r 1 i ne co rd is connec ted
to the ac supply.
GENERAL DESCRIPTION AND BLOCK DIAGRAM
The power supply unit is described below, the explanation being based on the
simpl ified block diagram of Figure 4-11.
More detailed block diagrams follow.
Detailed circuit diagrams are given in Section 5.
The ac input power is taken to the computer enclosure through the power line
cord.
This plugs into the ac power socket of the Input Unit mounted at the
top rear of the computer enclosure (Figure 2-1,3-5).
The Input Unit contains
the computer main circuit breaker (AC POWER switch), the input fuse (Fl), the
battery fuse (F3) and the line filter.
Note that the input unit is not part
of the power supply unit.
The computer chassis (frame) is connected to the third conductor of the line
cord; the conductor must be connected in turn to the ground (refer to Control
Data Mini Computer Systems, Site Preparation Manual, publication number 60437000).
The logic ground is brought out on a separate pin and should be connected to the
logic ground of the installation (refer to Section 3).
The equipment is switched on in two stages: first th..: ac line power is applied
to the power supply unit of the enclosure by switching ON the AC POWER switch on
the rear panel (part of the Input unit); in the second stage the power supply
unit is activated by turning on the dc POWER switch on the Programming Console.
89633300 A
4-57
.c:-
I
\1'1
00
VCC
AC to DC ConYerter
V~C Regulator
..,
10
.,
C
(I)
AC
Po
.c:I
~
.,z,.
+ 35v
Input
Circuit
*
~
)
.,
(I)
V)
Chall ••
Ground
-
-
.....
35vac
35vdc
auxiliary
..--.
AC Line
Cord
i"
Preregulotor
~
25vdc
auxiliary -7ydc
Circultl
Protection
f-4~
~
--
Vss
.....
-
-
Reference
-----Reference
Generator
"C
"C
-
4
~.
CI)
:I
"C
Battery
Choroer
and Battery
Crowbor
+ Sen..
-h
from
(I)
Q.
VCC
back plane
Terminal
CD
n
7:'
Q
AI
.,AI
10
No t!.:
Til t main
in IIcoted
power flow i.
by thick line.
\0
'"
\AI
\AI
\AI
0
0
»
*
Isolating
Diode
Battery
F3
Bottery
:I
00
I 1t
~~
f
0
T
The Input Circuit i. not
part of the Pow.r Supply
Front Panel
DC
POWER
}--1
~
-=
VCC2
-5"
C
-<
VBB
Regulators
-12"
overcurrent
VCC
Logie
Ground
Fu.e
Equipment
GD6J1-A
(Optional)
~30v
Unregulated
-SENSE
am back plane
ground terminal
The main source of dc power is the ac-to-dc converter.
This provides the main
unregulated logic supply of the computer (V cc ) and the internal auxiliary supplies
(+35V, +25V, -7V).
The circuit uses a high frequency switching regulator to
generate Vcc.
This circuit serves as preregulator for the other supplies which
are derived from the +35V supply through the regulator section.
Closely associated with the converter are the overvoltage and overcurrent
protection circuits which switch off the whole of the unit, should preset fail
conditions be exceeded on anyone of the supplies.
One of the auxiliary
independent supplies (+25V) provides the voltage for the reference generator
of the regulators to aid in operation of the circuits on switching on.
On failure of the ac line power the +35V internal supply fails and the backup power
source, optional memory hold battery equipment G06ll-A (if installed), suppl ies the
regulators througn an isolating diode, connecting it to the +35V line. In this case
the computer switches to Low Power Data Retention (LPDR) mode of operation and only
the memory power supplies are active.
The LPOR operation is described in paragraphs
on the operation of the Memory in this section and in Section 5.
Note that the
front panel DC POWER switch must remain ON during LPDR operation.
The battery charge circuit charges the memory hold battery during normal
operation of the equipment.
The battery is protected by its fuse both against
excessive charging current and against overload.
The battery fuse is blown
also through the battery crowbar (SCR) circuit when an overvoltage is detected
on any one of the power supplies used during emergency (LPDR) operation.
The front panel dc POWER switch controls the power supply: with the rear
panel AC power ON, the DC POWER switch disables the power supply circuits
when off and enables them when on.
The AC-to-DC Converter and Protection Circuits
Figure 4-12 shows the block diagram of the main dc generator circuits with their
controls and the power supply protection circuits.
89633300
A
4-59
I
!
•
r- -
f
•
~
I
+
- - -----,
~I--~
I
~I
I
!I: t
I
L____ -- _ ____ J
i
I
I
I
I+
111-!
I~
f
•
+
t
r---- --l
1
A---f--=t
11.
I
II
f- ------...J
I
illli
ti~1
I
I
I
I
r---- --i
I
I
;1
I!!I +
I
I
L _______ JI
!II
Figure 4-12.
4-60
AC-to-DC Converter and Protection Circuits:
Block Diagram.
89633300 A
A feature of the power supply main power path is that the main isolating
transformer works at a frequency of about 20 kHz. Its bulk is therefore
drastically reduced compared to the input transformer of a more conventional
solution working at 50Hz. The 1 ine rectifier is connected directly to the ac
input line and its sl ightly filtered dc output taken through a voltage regulator to a 20kHz inverter. The isolating transformer can handle substantial
powers in a small volume because of its high frequency of operation.
This frequency allows also high efficiency final filtering with comparatively small components, resulting in a dc output with very small ripple-content.
The technique of employing an isolator removed from the direct input makes
it necessary to employ small isolators in the control paths. Signal transformers serve in the alternating and interrupted current paths, and an optical coupler is used where the coupling signal is dc (switching regulator curcurrent·sense circuit).
The main switching regulator regulates the logic supply (V
). Its control
cc
reference voltage from the reference generator to
circuit compares the V
cc
the V voltage sensed at the computer circuits. The regulator therefore comcc
pensates both for input and for load changes on the V
I ine. As this carries
cc
typically 35 amperes, the load regulating feature with remote sensing is
particularly important. The remote sensing points (+ SENSE, - SENSE) are at
the backplane of the enclosure.
The switching regulator serves as a preregulator for the +35V and -7V internal dc suppl ies, though load changes on the V supply will show as regulation
cc
noise on these. As they feed the final regulators, this noise does not appear
on the power supplies, except the +30V unregulated supply.
An auxi I iary supply (+25V) is generated by a conventional I ine transformer
and rectifier filter directly from the ac line input. This supply is used in
the reference generator and the regulators which get their supply from the
+35V I ine: when the ac I ine is appl ied to the computer (Ae POWER switch on
the rear of instrument) this connection allows the regulators to stabi] ize
before the front panel dc POWER switch enables the circuits in the main power
path. The auxil iary supply is protected by a separate fuse (F2: 100mA).
89633300 F
4-61
I
The Low Power Data Retention (LPDR) mode of operation is initiated when the
main logic supply (Vee) fails, due to anyone of several conditions (see
Protection circuits below). The failure of the V supply is sensed in the
cc
.
Power Failure Detector by the absence of the switching signal to the V
cc
switching regulator while the front panel de POWER switch is ON. During LPDR
operation, only the circuits are supplied which are needed to retain the
content of the memory within the enclosure, provided the power back-up
source (memory hold battery, equipment GD6ll-A) is installed (refer to paragraphs on memory operation in this section). To avoid hunting on momentary
recovery of the ac supply, the power recovery delay allows the computer to
return to normal operation only when the ac supply has been established for
some seconds. Note that the power fail detector is actuated also by failure
of the switching regulator control circuit: when the duty cycle of the
switching regulator tends to 100% (continuous current) the power fail detector initiates an LPDR signal.
Protection Circuits
The power supply is protected against both overvoltage and excess current.
Over-current occurrring on anyone of the supplies, the whole power supply
shuts down. When an overcurrent condition occurs in the main power path, the
main voltage regulator (switching regulator for V ) is shut down. This is
cc
done by stopping its switching signal through the overcurrent protection
circuits. Should the overcurrent condition last for more than one second,
the overcurrent latch reduces the voltage of the switching regulator and so
activates the power fail circuit. The overcurrent latch is set also if any
of the circuits in the regulator section detect an overcurrent condition.
In this case, the LPDR mode of operation is initiated.
If the overcurrent protection circuit fails to shut down the main power path,
the crowbar
drive is activated directly through its isolating transformer
and so fires the SCR of the main crowbar circuit. This in turn blows the
main fuse (Fl). Each of the supply voltages is connected to the overvoltage
detector. Should a preset
volta~e
be exceeded on anyone of the supplies,
the detector actuates the crowbar circuits, which in turn blow both the
main fuse (Fl) and the battery fuse (F3).
4-62
89633300 F
Regulators and Control Circuits
The computer supplies, other than the main logic supply (V), have individual
cc
control and regulator circuits.
Table 4-6 summarizes these.
TABLE 4-6.
Supply
Designation
SUMMARY OF REGULATED POWER SUPPLY CIRCUITS
Type of
Regulator
Overcurrent
Detector
Supply
from
Vcc2
swi tch i ng
yes
+35V dc
VSS
switching
yes
+35V dc
VBB
series
no
+35V dc
-12V
series
no
35V ac
- 5V
seri es
yes
-7V dc
+30V
none
yes
+35V dc
Figure 4-13 is a block diagram showing these circuits.
I
All regulators receive
their reference voltage from the reference generator, except the VSS supply,whose
reference is a tap of a potentiometer divider on the VBB supply.
The reason
for this arrangement is that the memory unit bias and supply voltages must be
applied together and at a definite differential between them.to avoid possible
overheating of the unit.
Note that the +30V supply has no regulator but relies
on the regulation from the V regulator acting on the +35V internal supply.
cc
The reference generator uses the sense line (the remote computer logic ground, -SENSE)
as its reference ground, thus compensating for current in the ground circuit
between the power supply and the computer.
The reference generator is actuated
as soon as the AC power switch on the rear panel is switched on.
It is thus
stabilized whenever power is applied to the computer and is ready for operation
as soon as the front panel dc POWER switch is thrown ON.
89633300
F
4-63
,f:I
35vClc
0'\
,f:-
--
+ 3!5v Line
(+30 V )
"-
AuxlllClry+25v
Front Ponel
DC Power
Reference
aenerator
t--+
To VCC
Regulator
4
..
--
-
Sen ••
..
..
Switching
Regulator
(VCCZ)
-..
Switching
Regulator
(VBB )
L
-----
~
g
~
Auxiliary -7vdo
-
Serl ••
Regulator
(-5v)
Vaa
~
.~
f'
~
Switching
Regulator
(VSS)
VC02
~
V SS Ref.renCI
~
--llv
-'"
Computer Logic Ground
&
30v
~
Series
Regulator
(-IZv )
~-
--
1
-+
Overcurrent
Detector
- Vas
~
- -Iy
~
• re
C~".~
Lt,,'.
Circuit
Figure4-l3. Power Supply Regulator and Control Circuits: Block Diagram (see also page 5-448)
The Switching Regulator
Figure 4-14 illustrates the basic principles of the voltage conversion circuit
which is at the heart of the switching regulator.
Transistor Ql is a switching
transistor in the main load path.
It is switched on and off by a pulse waveform generated in the switching network.
The voltage and current waveforms are shown in part b of Figure 4-14.
This
voltage is smoothed by the LC filter to give dc output with very little ripple.
Diode 01 is a catching diode to complete the inductor circuit when the transistor
h. off.
The output voltage of this circuit is thus the average of the switched waveform
VO:
t
V
out
=
v.In~
T
and it is substantially independent of the load current.
The dissipation in
the transistor is determined by the difference in input and output voltages and
the load
current~,·as
in a series regulator. but is reduced by the duty cycle
factor (to/toff ) compared with the conventional series regulator.
The output
voltage can be changed for· a particular input by varying the duty cycle of the
swi tched \
i
To determine which memory bank the CPU or DSA is addressing.
SIGNAL SOURCE/
CONNECTOR PIN
SIGNAL
ffi
P2AOl
P2A05
CRI
CAA 15
32KW
P1B26
PIA25
P2A06
CRQ.
ICA
P2A09
P2A08
SA15
I
NAME OF SIGNAL
I
1::1
LOCATI ON
..
.SQUARE
.~HEET
DSA address Line 15
More than 32K of memory are
ava i 1ab 1e
CPU Index address OOFF
CPU address line ALU15
32KW Swi tch on Ma inframe front
panel.
I
I
6
6
C-3
B-3
6
C-3
6
B-3
6
6
0-3
0-3
6
C-l
B-1
C-l
C-l
Ouq~uts:
IC0
ICfI
IS0
TSJ
P2B03
P2A02
P2A04
P2B04
II
I
I
Lower-bank
Lower-bank
Lower-bank
Lower-bank
CPU
CPU
DSA
DSA
address
address
address
address
correct
incorrect
correct
incorrect
6
6
6
Description of Operation
The outputs of this circuit are connected via the back-plane of the computer
enclosure to the appropriate CPU and DSA address function. The circuit
decodes the CPU and DSA address information to determine if the memory bank is
correctly addressed.
89633300 A
5-129
MEMORY CONTROL
Signa 1 Funct ions
SIGNAL
(Drawing number 89619100, sheet 6, cont'd).
SIGNAL SOURCE/
CONNECTOR PIN
FUNCTION
LOCATION
SHEET SQUARE
IC'
u66/6
Lower-bank CPU address correct
6
If any of u66/6 inputs are Low" '
the CPU requests access to the
lower memory bank. Otherwl se
the memory reques~ access to
the upper memory bank.
Cl
iCJ
U6/8
Lower-bank CPU address
incorrect ., The inverse of IC".
6
Cl
IS'
u63/3
Lower-bank DSA address correct.
If any of U63/3 inputs are Low,
the DSA requests access to the
lower memory bank. Otherwise
the memory requests access to
the upper memory bank.
6
Cl
IS'
U62/10
Lower-bank CPU address
6
i nco rrec t. The inverse of IS'. '
Cl
Interconnections:
The Bank address is connected to the Access Selector via the back-plane
wiring as follows:
Lower-memory bank:
IC'
TCJ
I Sri
IS'
----
ICA
ICA
ISA
NOT CONNECTED
Upper-memory bank:
I Cf}
Ttl
I Sf}
TSJ
5-130
m
ICA
NOT CONNECTED
ISA
89633300 A
.
00
\0
I~
<7'
1
4 AI'
\Ill
\Ill
\Ill
o
o
I
IS
14
~
HI
)
vce
RGTR
168
Ulill
II CO
181=-2 O r o - ZI
R24
470
---
PIAlli
...---!! Ifp--
MUT9 PII15
2~ti
~ ut8
9--10
-
:~
vee
~
I
I
D,UT 10> PIAII
.•
I
vee =~~
MUTI5)-'- ~
'.
f-
a
OIUT 14
4
5
, >--
I
PI824
I
"I'
470
~~
PIA21
~
~
_
,
~
~
41
~
.....
V1
I .........
''0
I
4 AL
12
UlS
~
-
0.-
5
K
~.
'~ro "~,
5
L!2t.
I
>_!!~
DIUTI
RI5
AT 4.lI
470
vee
E
D'UT2 PII04
RI9
470
F
vee
II PIAU
U30
II--
III
3 .....
~
I
~ l--
~
tJJ
@-=! __
•
I
•
-..
1\
PIIU
e!!-
0'UT4> PlI07
_, PII12
PIAZO
PlAit
,"5014
,
HI
"SOIll
-,
".
,IIX.II
_
'"
2
4
~II
iPEc
IIX411
II PZIIID
,DF~
~OELE"
"..
D'UTI
d
I
I
T
6
IoIxaL
PlBllI
"IoIX7L
-
•
P7_
-'PEL
...... 0
Ji:ePE
a
DETAILED LOGIC DIAGRAM
MEMORY CONTROL
COO[ IDENT
IC
cw(; NO
89619100
,HUT
-.-
-
5
I
I~V
MEMORY CONTROL
(Drawing number 89619100, sheet 5,. cont'd.)
MX17 [P1A26]
This signal is connected to CXO and 017 from the Memory Address card (P1B27).
sends the status of the protect bit to the CPU on read and write cycles.
CPB signal is active, MX17 will be low.
be high.
It
If the
If the SPB signal is active, MX17 will
If the CPB and SPB signals are inactive, and the memory location is
unprotected, MX17 will be low.
If the CPB and SPB signals are inactive, and the
memory location is protected, MX17 will be high.
For MX17 truth table see table
at end of this part.
CVIOI [(U P1A28]
This signal is connected to CXO and Protect Fault.
When a protect fault occurs
during a CPU cycle, this signal is low, otherwise it is high.
The signal is high
during a read cycle because protect fault only occurs on write cycles.
SXO [U20/7]
This signal is active high for 5 clocks of a OSA cycle, beginning at clock 8.
SXRO [U21/6, 8]
This signal is active high for 5 clocks of a OSA read cycle only, beginning at
clock 8.
5000-5015 (H)
These signals are connected to SXRO and the data out latches after
O~UT
lines.
They transmit stored-buffered memory data to the OSA on read cycles only.
The
true state of this data is active high.
Data to the OSA is transmitted by powerful open collector 2-input NAND buffers.
Pull-up resistors are located on the OSA lines.
by one of two signals, SXO or SXRO.
These NAND gates are opened
All data to the OSA lasts for 4 clocks
beginning at clock 9.
5016 (odd) [P2A21]
This signal indicates the parity of data read from or written into memory of the
OSA lines.
89633300
A
It is connected to SXO and a parity selector UI4/6.
5-125
MEMORY CONTROL
(Drawing number 89619100, sheet 5, conti d.)
5016 is active such that the sum of the data on 5000-5017 (18 bits) will be
odd. During a read cycle, 5016 is determined by the parity register U15/8.
During a write cycle, 5016 is determined by 016 P2B06 from the Memory
Address card.
5017 [ell P2A18]
This signal indicates the status of the protect bit during a OSA read or
write cycle. It is connected to SXO and the protect register U1S/6. If
the location in memory is protected, 5017 is low, otherwise 5017 is high.
SVlft [ell P2B24]
This signal is connected to SXO and the Protect Fault. When a Protect Fault
occurs during a OSA cycle, this signal is low, otherwise it is high. This
signal is high during a read cycle because protect fault can only occur
during write cycles.
TRUTH TABLE FOR MX17
CPB
SPB
lOCATION
PROTECTED
MX17
H
X
l
X
H
X
X
l
H
l
H
l
NOTES:
5-126
L
L
H = High,
L
= Low,
l
H
X = irrelevant.
89633300 A
MEMORY CONTROL
(Drawing number 89619100. sheet 3, S. cont'd).
Parity error is indicated by the data registers and parity checker circuit.
Because the D0UT 1 ines are stable on clock 8, and because
D~UT
may change
after clock 8 on a write cycle, the data must be stored on clock 8.
Between clocks 6 - 8 the data latches U33. U34 are opened.
The first 16 bits
of data pass through these latches during this time. and enter the parity
checker.
The parity checker for the first 16 bits (U16, USI. U32) is
relatively slow (100 nsec).
It requires stable data to be present before
clock 8 and to continue until clock 10 in order to allow the parity checker
to be stable by clock 10.
Bit 16, (D0UT16), the Parity bit, and bit 17 (D0UT17), the Protect bit, are
stored in D-fl ip-flops (U1S) on clock 8.
The outputs from UIS/8, 9 and
UIS/S, 6 do not have to stabil ize until after clock 8 because the parity
checker is relatively fast (SO nsec) for these two bits.
The parity checker is designed so that if the binary sum of 00UTOOtD0UT17 is
even. the parity checker output U32/8 will be high indicating a parity error.
Otherwise U32/8 will be low (i .e. parity error did not occur).
The 00UT 1 ines come from the open collector sense ampl ifier outputs on the
memory modules.
MC assembly.
The pull-up resistors are located on the 00UT 1 ines in the
Only one of the possible eight memory modules sense-amplifier
outputs can be active, as determined by the module selector MOX and the signal
STR~BE.
Protect Fault [(H) U28/6] - refer to sheet 3
Protect fault [condition 1] occurs when an unprotected instruction (u28/S)
attempts to write
~28/3)
u28/6 is active high.
to deactivate u28/4.
into a protected location (u28/4).
Protect fault
The protect register is preset (UI5/4 low) on clock 5
This prevents unnecessary spikes between clocks 6 - 8
when the other two inputs are stable and CXO or SXD are stable.
prevents unnecessary spikes on 5017, the DSA protect bit.
It also
Protect fault is
val id between clocks 8 - 5 after the protect register is stable.
89633300
A
5-123
MEMORY CONTROL
(Drawing number 89619100, sheet 5, cont'd).
Note that the memory system recognizes protect fault condition 1 only.
Conditions 2 and 3 are conditions within the CPU and are not related to the
memory or DSA operations.
Both the parity fl ip-flop clock (U15/11) and the protect fl ip-flop clock U15/3)
are positive edge triggered on clock 8.
Data to the CPU (MX) and to the DSA bus (SO) is transmitted by high speed open
collector 2-input NAND gates. Pull-up resistors for these signals are located
in the CPU. These NAND gates are opened by the signals, CXD (CPU) or CSRD (DSA).
All data to the CPU is val id at clock 9.
CXD (U31/6,8) CXRD [UI3/6,8] - signal origin: sheet 4.
These signals are active high between clocks 6-10 for CPU cycles only. They
are to gate the memory data for CPU cycles.
MXOO-MX15 (H)
These signals are derived from the D0UT 1 ines gated by CXRD. They transmit
buffered memory data to the CPU during read cycles. The true state of this
data is active high.
DElE0 [ell P2B20]
This signal is sent to the CPU on a read cycle only.
MXOOtMX07 are all at logic low.
The signal is low when
DFE0 [(l) P1B20]
This signal is sent to the CPU on a read cycle only. The signal is low when
MX12-MX15 are all logic low.
MPRY [P1A27]
This signal is PAR (P1B28) from the Memory Address assembly gated by CXD.
It Is a special parity bit to the CPU on write cycles (bit 16). If the sum
of the 16-bit data sent from the CPU to the memory is even, MPRY is low.
Otherwise it is high. Information on MPRY during CPU read cycles is
meaningless and is not used by the CPU.
5-124
89633300 A
MEMORY CONTROL
MEMORY CONTROL DATA OUTPUT LINES
(Drawing number 89619100, sheet 5)
Funct ion:
To transmit data to the CPU and to the OSA
SIGNAL
E
B
CMOR
clock 6
G"PE'C
,SIGNAL SOURCEI
ICONNECTOR PIN
[Ull. 7]
LOCATION
SHEET SQUARE
Clock signals
[U10/7]
P2B02
E·B
4
Par i ty
5
5
3
4
4
[u63/11 ]
I P2B23
I
I
016
017
PAR
!
CX
RX
F
clock 7
OOUTOO+00UT17
I
P2B06
P1B27
P1B28
I
[U7/8]
I
[U45/6]
B-1 !
0-2
A-3
B-1
0-41
0-4
I
[U24/6]
End of cycle (clock signal)
[U28/2]
18 locat ions
Memory data output
I
i
,
Outputs
!
1
CCP'E
m
CPEC
OELE0
OFEO
MPRY
MX17
CV101
I
I
I
I
,
89633300 A
P2A1O
P2B26
P1A31
P2B20
P2B19
P1A27
P1A26
P1A28
,
CPU cyclic parity error
General parity error
;
i
MXOO·MX01·MX02 ••••• MX07
MX12·MX13oMX14·MX15 = 0
Parity information to CPU
Protect bit status to'CPU
Protect fault
=0
,
i
5
5
5
5
5
4
4
4
A-l!
I
I
A-l/
A-31
I
A- 4 1
A-4,,
I
0-3j
0- 3 1
A-3 i
I
I
I
5-121
MEMORY CONTROL
Outputs (cont'd)
(Drawing number 89619100, sheet 5, cont'd).
SIGNAL
ICONNECTOR
SIGNAL SOURCEI
PIN
SD16
SD17
SVlfl
MXOO-MX15
SDOO-SD15
P2A21
P2A18
P2B24
16 locations
16 locations
FUNCTION
Par i ty bit for DSA data
Protect bit for DSA data
Protect fault on DSA cycle
Data to CPU
Data to DSA on read cycles
LOCATION !
SHEET SQUAREI
4
4
4
D-2
I
D-21
D-2
I
!
Ci rcu it Descript ion
All the Data lines are open collector. Corresponding bits are connected to the
same bus line for multi-bank operation.
Parity Error Checking is performed on CPU and DSA read and write cycles. If a
parity error is detected, it is an indication that the memory is not working
correctly. Parity error is detected when the summation of DI/JUTOO-DOUT17
(data out bits 00-17) is not an odd number.
There are two types of indicators for parity error detection.
1.
PEL [P2B26]
General parity error: a parity error was detected. The J - K register
(U48) continues to be active until U48/3 is cleared by the CPU signal
GPEC(P2B23). The J input, u48/4 will detect a parity error, excluding the
refresh cycle (RX U30/9 is not low) if U32/8 is high at clock 10. The
clock (u44/l) is negative edge triggered at clock 10 by the F-register
(U45)·
2.
5-122
CCPE [P2A10]
CPU Cyclic Parity Error: a parity error was detected on the last CPU
cycle. The J - K register (u48) continues to be active until CPEC(P1A31)
(a multibank output) clears u48/8 on clock 7 on the next CPU cycle. The
J input, u48/9 will detect a parity error only on a CPU cycle (CX U30/12
is high if U32/8 is high at clock 10. The clock (u48/1) is negative edge
triggered at clock 10 by the F-reglster output.
89633300 A
00
\.0
0'.
W
W
W
....
."
o
o
204_~ 5
,
In",. <5DI7
o
J:-
s{N)
, ......& '~I
s.'.'
•
P2AOT
6
J
V1
I
\.0
"N
o
D'UTlT~
'~I
DETAILED LOGIC DIAGRAM
MEMORY CONTROL
MEMORY CONTROL
(Drawing number 89619100, sheet 3, cont'd).
R/WREG [(H) u44/8]
This register provides timing to the Read/Write (R/W) signal in memory.
It also determines if the R/W signal should be activated.
This register is negative edge tirggered and is connected to the 0SC
(u44/13).
It is activated on clock 8 (u44/8 goes high) only if one or
both of the AND-OR K inputs is active on clock 7.
only on clock 7.
U44/10, 11 is active
If the instruction from the PROTECTREG is protected
(u44/9 high), or if the protect bit from the memory location addressed
was inactive (u44/12 high), then u44/8 can activate on clock 8. Thus,
a write cycle will not occur if the location in memory is protected and
the instruction is unprotected.
The only other condition necessary for
the R/WREG to activate is that the WRITEREG (U44/5) indicate that the
memory cycle is a write cycle. If the memory cycle is a read cycle, the
R/WREG is preset, (u44/5 is active low) and u44/8 will remain low on clock
8. If the R/WREG activated on clock 8, it will deactivate on clock 11
after 0 (u44/3, 4) activates the J input between clock 10 - 5. The J and
K inputs can never be active simultaneously because of this timing.
Read/Write: R/W [ell P2A20]
The R/W signal activates the R/W signal within the memory.
If activated
the R/W signal will go high between clocks 8 - 11 (U59/10 high).
The
R/W signal cannot activate if the INHIBITREG is active (U59/9 low), or
if the system is in lPDR operation (Normal, U59/13 low).
DE
[(l) U5716]
DE activates
the data-in 1 ines on the Memory Address assembly.
These
1 ines transmit data to the memory on write cycles. It is desirable to
activate these lines by
clock 8 because these 1 ines may create noise on
the data out 1 ines from the memory and interfere with parity checking on
a Read/Write cycle. DE goes low on clock 8 when (U57/4) goes high.
DE goes
89633300
A
high on clock 12 which is approximately 50 nanoseconds after
5-117
MEMORY CONTROL
(Drawi"ng number 89619100, sheet 4, cont'd.)
register Ewent low as determined by the RC delay on U57/3.
The D£ signal needs to be active until after the R/W signal within the
memory has completely deactivated. If the WRITEREG register indicates
that the memory cycle Is a read cycle (U57/5 Is low), DEwitl not activate.
5-118
89633300 A
MEMORY CONTROL
(Drawing number 89619100, sheet 3, cont'd).
WRITE CONTROL SIGNALS
Function
The memory system includes a protect system.
The primary purpose of this
feature is to protect the program in foreground from being destroyed by
careless programming, or faulty memory operation.
of the write system within the memory.
The protect feature is part
The read/write and protect status of the memory cycle is determined by
multiplexer-selector u64.
The following table shows its input and output
signals.
Input Controls
RX
SX
(Pin 3) (Pin 13)
Outputs
WRITE cycle
I
Cycle Selected
\
Unprotected Instruction
(Pin 2)
(Pin 15)
PRTM
CPU cycle
SPl
DSA cycle
Refresh cycle
L
L
WE
L
H
SWRITE
H
L
Low
Low
H
H
irrelevant
irrelevant
I
:
---
,
Signal Description
The following paragraphs describe each signal in detail:
the signal name heads
each paragraph together with the integrated circuit and pin number where it
appears.
The letter (H) and (L) indicate whether the signal at the corresponding
pin is active High or active Low.
WRITEREG[(H) Ul2/5, (L) U12/6]
This register is positive edge triggered.
On clock 6 it stores both during
a read cycle (pin 5 low) and a write cycle (pin 5 high).
inverse of pin 5.
Pin 6 is the
U12/4 (active low) is preset (pin 5 goes high) on clock 4.
This is to prevent unnecessary spikes on the data out 1 ines to the DSA and
CPU 1 ines.
89633300
A
5-115
MEMORY CONTROL
(Drawing number 89619100, sheet 4, cont'd.)
PROTECTREG (H) U29/8, (L) U29/9
This registe~ is positive-edge triggered. On clock 6 it stores whether
the cycle is a protected instruction (U29/8 high) or an unprotected
instruction (U29/8 low). P9 is the inverse of pin 8. U29/13 (active low)
is cleared (p8 goes high) when the PRTSW (Prote.ct Switch, P2BOl)- is low.
In this case (protect switch low) all instructions appear as protected
within the memory system. The protect switch is situated on the programmer's
console (front panel)
INHIBITREG
[(L) U29/5]
This register is positive edge triggered. On clock 6 it stores provided
either one of two conditions occurred:
The first condition is that a parity error occurred on either memory bank
while the instruction was unprotected.
The second condition is that during a CPU cycle a parity error occurred in
the selected memory location and that the SPB or CPB (Set or Clear Protect
Bit) is activated on this memory cycle.
The two conditions may be summed up: when an attempt is made to execute
CPB or SPB instructions when a parity error exists in the selected
memory location.
The procedure for recognizing condition 2 works because before CPB or SPB,
the program must read from the location in memory, and immediately afterward
perform the CPB or SPB in that same location.
If the INHIBITREG register recognizes either condition 1 or condition 2
or both conditions, U29/5 will go low. Otherwise U29/5 is high.
U29/4 (active low) is preset (U29/5 goes high when the PRTSW (Protect
Switch, P280l) Is low].
When the protect switch is low, the protect
feature of the system appears to be disabled.
5-116
89633300 A
MEMORY CONTROL
3)
(Orawing number 89619100, sheet 4,6, cont'd).
The memory system is processing the CPU request, but has not yet reached
clock O. The combination of the following conditions define this:
the memory Is processing a CPU cycle between clock 6-11 (U60/10) , and
has not yet passed clock 8 because register B (u60/9( is active.
Two memory systems are used in systems having more than 32K word memories.
A second signal (G_M2: P2B07) is employed in the expansion memory system; it
is basically identical to GIJMl in its function.
Further explanation of the CPU memory request system.
Schottky TTL circuits are employed in this system because timings must remain
synchronized with the oscillator. The CPU transmits the CPU request signal
CRQ between its clock 2-5 of pass 1 only. Also, the signal G_Ml must be high
for one clock at the end of a CPU pass, which is why GIJMl is released before
memory system clocks 3 and 9. The timing relationships are shown below.
__ CPU PASS
CPU PASS 2
-f
I
i
CPU Clock 0
Memory Clock 0
CRQ
e'MI
89633300 A
1
0
2
0
I
I
3
4
2
5
3
I
6
4
7
5
8
6
I
9
7
9
0
8
9
I
2
10
3
11
I
I
H
L
H
L
5-113
MEMORY CONTROL
(Drawing number 89619100, sheet 4,6, cont'd).
Basic Control signals to the DSA
SRSM
(L)
P2Bl8
The SRSM synchronizes the DSA with the memory. Because the DSA is an
asynchronous device, the SRSM does not have to be a fast signal. The SRSM
appears at an open collector gate, and can be used as a wired-OR function.
In multibank memory operation the SRSM of both lower and upper banks are
connected together. This is an active low signal; normally the line will be
high. When one of the memory systems wants to activate the SRSM line, it
merely activates its own SRSM signal. The entire SRSM is then forced low
until this same bank deactivates its SRSM signal.
When SRSM is high, at the beginning of a DSA cycle, it informs the DSA device
that the memory has not accepted the DSA address, and that the DSA should
continue to transmit the address.
When SRSM falls, it informs the DSA device that it has accepted the DSA request
and address. The DSA should immediately clear the DSA request and address
lines, and it can send a new DSA request and address if desired.
Further, for a DSA write-into-memory cycle, the low SRSM signal informs the
DSA that the memory has not yet accepted data, and that the DSA should continue
transmitting data to the memory.
Also, for a DSA read-from memory cycle, the rising edge of the SRSM signals
informs the DSA device that data from the memory is now valid.
The SRSM is low between DSA cycle clocks 3-11.
Refer to DSA Timing Specification in Section 4 and the Input/Output
Specification Manual.
5-114
89633300 A
MEMORY CONTROL
cxp
(L)
(Drawing number 89619100, sheet 4,6, cont'd.)
(P2B16)
sxp
(l)
(P2All)
HelD
(H)
(P2B14)
These three signals provide initiate and hold signals for the selector/latches
on the memory address assembly.
Before a memory cycle begins, HelD is High to hold the old memory address.
SXP and CXP are also high.
When the ex access selector activate at clock 1;
CXP goes low, which allows a new AlU address into the MA address selectors.
The CXP signal is also fed into U23/10, so U23/8 goes high and HelD (U42/8)
goes low.
This overlap of exp and HelD is important, because it allows the
outputs of the MA address selector/latches to change only once.
On clock 2.5
the signal AP5 (U58/4,5) goes low and HelD goes high.
This holds the address
in the MA address selector/latches.
The HelD signal and AP5 are fed into a
NAND gate whose output (U23/11) causes CXP to go high.
This overlap of HelD
and CXP prevents the HA address selector/latch from changing during this
transient period.
In other words, exp and HelD behave like the Q and Q of an
R-S fl ip-flop;
except HelD is Q inverted.
For a DSA cycle, SXP behaves like the CXP signal during the CPU cycle.
the DSA cycle, exp always remains high.
HelDW
(H)
During
(P2A24)
The HA address selector/latches for the kiloword decoder do not have the same
This decoder can have transients
requirements as the other address bits.
when the Disable signal is inactive between clocks
- 1.5.
However, it is
desirable to have the kiloword decoders completely decoded before the Disable
signal activates at clock 1.5.
For this reason, a special hold signal called
HelDW is used for the MA kiloword decoder.
It is the signal AP5 inverted,
and is active high between clocks 2.5 - 11.
No time is wasted in the kiloword
decoder when exp goes low at clock 1 because H~LDW is already low on clock 1.
89633300 A
5-111
MEMORY CONYROL
(Drawing number 89619100, sheet 4,6, cont'd).
Basic control signals to the CPU
GeM 1
(H)
P2B09
The CPU and memory are both synchronous devices using the same oscillator.
However, the memory system is not always ready for the CPU because it may be
performing DSA or Refresh cycles. When this happens, it is important to stop
the CPU.
The CPU is a two pass machine. During pass 1 the ALU caloulates address
information and holds this information at the end of pass 1. During pass 2 the
ALU calculates or receives data information and holds or accepts this information
at the end of pass 2. Both ALU passes are 5 clocks long; therefore pass 1 and
pass 2 together take 10 clocks. This causes a discrepancy, because the CPU memory
cycle is 11 clocks long. When the CPU is performing a memory request, it must
be stopped for one clock so that both the CPU and CPU memory cycle will have the
same number of clocks, namely 11.
The CPU is stopped by the memory system with the signal G0Ml.
If this signal is
low at the end of CPU memory request pass 1 or pass 2, it will stop at the end
of that pass. Further, the memory system requires address information between
CPU memory cycle clocks 1-3 and data information between clocks 3-9.
conditions for lowering the G0Ml signal can now be defined.
1)
The memory system is busy with a DSA or Refresh cycle.
the following three conditions define this:
The three
The combination of
if the memory is not processing a CPU cycle (ex: u60/5),
the CPU requested memory access (CRQ: U60/6),
the address is in this memory bank (ICA: U60/4).
2)
The memory system is processing the CPU request, but has not yet reached
clock 3. The combination of the following conditions define this:
the CPU requested memory CRQ (U60/1) for this memory bank leA (U60/11,
12),
the memory cycle has not passed clock 2 because register A (U60/13) is
active.
5-112
89633300
A
(Drawin~
MEMORY CONTROL
DISABLE
number 89619100, sheet 4,6, cont'd.)
P2B10
(l)
Disable activates (low) when IPS (u41Pl0) ~oes high at clock 1.5.
Disable
deactivates when F (U41P12) goes low.
One clock after F goes low,
BUSY (U41P9) goes low.
Then F goes high.
When the next access selector
activates, BUSY goes high.
If leADRA (U41PI3) is low, Disable is inactive.
leADRA is used for lPDR operation.
CE
(l)
P2B27
This signal falls at clock 4 when register C falls, and rises when register
rises.
REF
(l)
E
P2A07
This is a 2-2 AND-OR gate.
REF is low during refresh cycles because U61Pl,13
is connected to RX.
REF is low for DSA and CPU cycle until clock 3 when
register B (U61P10) falls, and REF remains high until clock 11 when register E
(u61P9) rises.
STROBE
(l)
P2Al2
This signal is the inverse for register D.
Because Disable and CE are critical timing signals going to eight memory
modules, they employ extra powerful buffers to be less noise susceptible.
STReBE is extra powerful because each of eight memory modules uses 2.5 TTL
logged units from this signal.
89633300 A
5-109
MEMORY CONTROL
(Drawing number 89619100, sheet 4,6
cont'd).
Basic Control signals during refresh cycles.
SXA
(l)
P2B08
This active low signal informs the Memory Address (MA) assembly that a OSA
cycle is being processed.
Pl6
(l)
It is the inverse of SX, active between clocks 1-11.
P2A17
Active low signal opens the 16 bit parity latch on the MA assembly; activates
at clock 7 when A (U23/2) rises until clock 9 when C (U23/1) falls.
B
(l)
P2B12
Active low signal clocks the protect bit (bit 17) register on the MA assembly.
Activates at clock 7.5 when 0SC rises. Deactivates at clock 8 when 0SC falls.
B cannot activate during other time intervals.
CHOR (l)
P2B02
M1
Active low signal provides timing to the
CPU data in memory latch.
CHOR activates at clock 4 when E (U63/5) goes high and activates at clock 8
when B (U63/4) goes low.
5-110
89633300
A
MEMORY CONTROL
(Drawing number 89619100, sheet 4,6, cont'd.)
Introduction
The Control unit processes a collection of control signals and can be divided
into two parts:
1.
Basic Control Signals
Control signals necessary for all types of memory cycles,
i.e., read or write cycles in protected or unprotected
locati ons.
2.
Write Control Signals
Control signals for write memory cycles used with the
protect system.
For timing signals refer to Memory Control Timing (sheet 4).
Note:
BASIC CONTROL SIGNALS
DISABLE
(L)
P2B10
The falling edge of this signal activates the precharge signal in the memory.
The falling edge starts at clock 1.5, giving the memory system half a clock
period to select one of four kilowords on each memory card.
As each kiloword
has its own control signals (precharge, cenable, R/W) only one kiloword will
be activated.
Since the precharge signal consumes most of the memory power
delaying the disable until clock 1.5 conserve~ power consumption without
imposing critical set-up or hold time restrictions on other memory signals.
The rising edge of the disable signal deactivates the cenable (cell enable
signal) in the memory.
This occurs at clock 10 for DSA and CPU cycles, and
clock 8 for Refresh cycles.
89633300
A
5-107
MEMORY CONTROL
CE
(L)
(Drawing number 89619100, sheet 4,6, cont'd.)
P2B27
(Cenable)
The falling edge of this signal at clock 4 activates the cenable signal in the
memory.
Also, within the memory, the canable signal forces the precharge
signal to deactivate.
The crossover of the cenable-active precharge-inactive
is performed on the memory card (rather than the memory control card) because
of critical overlap times required by some memory chip manufacturers.
The
CE signal deactivates at clock II for DSA and CPU cycles, and clock 9 for
Refresh cycles.
It is important to have the CE signal deactivate one clock
after the Disable signal deactivates.
If the CE ~ignal deactivates earlier,
the precharge signal may reactivate at the end of a memory cycle.
REF
(L)
P2A07
The REF signal blocks the module selector (MDX#) within the memory card.
During Refresh cycles the REF signal is always activate low because a Refresh
cycle must refresh all of the memory modules.
During DSA and CPU cycles,
this is low during clock 1 to 3 because the module selector decoding is slow
The REF signal goes high between clock 3-11.
and not stable during this time.
For all unselected memory modules during this time, the precharge signal
deactivates one clock before the Cenable signal, and the cenable with the
memory card never activates.
Only in the one memory module selected by
the module selector does the precharge-cenable sequence continue.
STR0BE
(L)
P2Al2
This signal is active low between clocks 5-10 for DSA and CPU cycles, and
clock 5-9 for Refresh cycles.
It enables the data out sense amplifiers
within the memory card.
It also deactivates the Read/Write (R/W) signal
(see R/W signal later in this section) slightly faster than the cenable
signal, helping meet an end of cenable - end of R/W specification for the
memory chip of some manufacturers.
This signal performs no useful function
during refresh cycles.
5-108
89633300
A
MEMORY CONTROL
(Drawing number 89619100, sheet 3,4,6).
MEMORY CONTROL BASIC CONTROL SIGNALS
Function:
To provide all control signals to the memory, memory address,
CPU and OSA devices.
Note:
The following signal I ists include a number of signals
not directly connected to the circuits described here.
Inputs
SIGNAL
!SIGNAl SOURCE/,
ICONNECTOR PIN:
PRTSW
PRTM
P2BOI
I
FUNCTION
,
,
PI B30
LOCATION
SHEET SQUARE
3
A-I
3
0-2
3
C-2
j
SPI
PI B29
WE
P1A30
I
Ii
3
0-2
SWRITE
P1B31
!
3
C-2
6
0-3
6
0-3
3
A-2
IIISCA
U38/6
CRQ
P2A09
ICA
PBC
89633300 A
I
I
,
II
i
I
I
I
Oscillator buffered
CPU cycle Request
I
P2A08
P2A22
I
!
5-105
MEMORY CONTROL
(Drawing number 89619100, sheet
3~4,6,(cont'd).
Outputs
SIGNAL
. SIGNAL SOURCE,
CONNECTOR PIN
GriM 1
GfJM2
DISABLE
P2B07
6
0-1
6
0-1
I!
6
B1
P2B08
DSA active ('SX)
3
A-2
R/W
I,
P2A20
Read/Write
3
C-2
CXP
I
P2B16
CXeSX-HeLD-AP5
3
C-2
!
P2A24
AP5
3
C-2
3
B-2
3
C-2
4
B-1
4
B-1
4
C-I
4
A-I
4
D-4
i
H"LDW
HrlLD
SXP
S'RsM
I
I
I
REF
CE
DE
P16
B
I STReBE
CMDR
CVIOI
.
i
I
cx]
;
P2B14
AP5 [SX +
P2A11
SX·HOLD-AP5
!
P2B18
SX.[D + B]
DSA Synchronizing signal
II
P2A07
RX [B + E]
!
,i
P2B27
•
P2B17
Data-line Enable
,
i
1
P2AI7
A·C
I
i
P2B12
Second Counter stage
4
B-1
i
P2A12
Timed by D (='6)
,
4
B-3
P2B02
B'E
,
4
B-1
4
A-3
I
II
I
I
t
t
i
I
I
i
I
I
!
i
It
I
CX~B.E
LOADRA-f-BUSY .. IP5
I
I
I
ICA·CRQ +
P2BI0
ill
I
P2B09
LOCATION
SHEET SQUARE
FUNCTIGN
-[.'C
= C + E, (Cenable)
I
!
;
.,
!,
I,
i
,
I
:
I
I
;
PIA28
(See sheet 5)
I
,
5-106
89633300 A
(Drawing number 89619100, sheet 4, contld.)
MEMORY CONTROL
Detailed Circuit Description
The BUSY signal clears the five-stage ring-counter (U9,
When this signal goes high the counter is free to run.
will be the first to toggle because outputs E and
the J
E
UIO,
Ull).
Flip-flop A (U9/S)
are inversely connected to
and K terminals of the A flip-flop relative to the other J and K
connections.
The ripple-through process shifts the toggling along the counter
on the appearance of each clock pulse. The counter is clocked by the 0SC signal,
the flip-flops being triggered on the negative going edge of the signal.
The
J input activates the flip-flops, the K input and the Clear input (Busy signal)
deactivates them.
The K input activates Register F (U4S).
During DSA or CPU cycles, this register
activates after inputs U4S/11 (f), and U4SP12 (D) are activate.
However, during
Refresh cycles this register activates two clock cycles after inputs u4S/9 (RX)
and U4S/10 (A and B) are active.
The J inputs are grounded, so only the Preset
input u4S/S (BUSY) can deactivate the Register.
to the
~SC
The clock U4S/13 is connected
and is negative edge-triggered.
Half of U9 (U9/7,9) is not part of the ring counter; it generates the timing
signal APS.
It is activated on the half clock after the J input U9/11 is active.
The K. input (U9/12) is grounded, so this register can only be deactivated by
the clear input U9/14 (BUSY). This register is negative-edge triggered, but
because it is connected to ~SCA it operates between clock cycles.
The IPS register consists of two NAND gates wired as on R-S fl ip-flop.
inputs U42/1,S are high, the flip-flop holds its state.
When
Both inputs will never
be low at the same time because the BUSY signal is common to both of them but
inverted in U42 5.
After an access register activates, U42/1 (BUSY) goes high.
On the half clock after the access register went high, U42/12
and U42/13 (BUSY) is high.
(~SC)
goes high,
U42/S goes low, activating the IPS flip-flop.
At the end of the timing sequence, the BUSY signal (U42/l) goes low, deactivating
the fl ip-flop.
89633300
A
Since IPS is connected to
~SCA
and activates when 0SCA is high,
S-lC3
MEMORY CONTROL
(Drawing number 89619100, sheets 4,6)
the IP5 activates during a half-clock.
All the register, A, B, C, D, E, FI AP5 and IP5 are super high speed Schottky
TTL devices to meet specifications in the high speed (600 nsec) memory system.
Q
~~
o~
;~
0
0:
0
>CI)
X
0
;:)
ID
0
..J
"Q
:z:
Go
)(
0
I~
I~
lit
"Q
~
!e
Go
....
0::
0
0
5-104
89633300
A
MEMORY CONTROL
(Drawing number 89619100, sheet 4)
MEMORY CONTROL TIMING
Control Signal Diagram for DSA Cycles
Memory
Clock
SXA
I
2
I
I
¥
4
8
6
7
8
9
I
I
10
"
2
I
3
¥
I
I
I
4
I
n
I
I
CXP
SXP
3
H
L
H
I
I
+
I
~
:1
I
I
t
t
H~LDI
H
L.
H
L
H
SRESUME
L
Control Signal Diagram for Refresh Cycles
I
Memory
Clock
Disable
I
I
Cenable
REF
89633300 A
2
3
4
8
6
7
8
9
2
3
4
I
H
L
H
L
L
5-101
(Drawing number 89619100, sheet 4, cont'd.)
MEMORY CONTROL
The advantage of the full ring counter is that only one of the five major
timing signals (A, B, C, D, or E) can clock a cycle. Any timing sequence can be
chosen from this pattern by simply ANDing or ORing one or two timing signals
since only one timing signal can change at any time.
On
clock 10 of DSA and CPU cycles register F (End of cycle) activates.
This
deactivates the Access Selector one clock later, and the Busy signal will fall,
clearing the timing circuit.
There are two special purpose timing signals, IPS and APS. Both of these
timing signals activate on half clocks (in between usual clock edge triggering)
instead of full clocks. Both of them are cleared by the Busy signal. IPS
activates between clock I and.2{referred to as clock 1.5). APS activates during
clock 2 and 3 (referred to as clock 2.5).
.
is shorter because data
For a Refresh cycle, the timing sequence is shortened two clock cycles.
A
Refresh cycle
is neither read nor written during this
cycle, so time need not be allowed for data from the memory to stabilize. The
Refresh cycle is shortened by activating register F (End of cycle) on clock 8
instead of clock 10. When the Busy signal falls during the next clock, all·
timing signals are cleared.
The J input activates the Timing circuit registers.
deactivates them.
The K input or clear
A hazard may arise in the Refresh cycle timing sequence as registers D and E
are asynchronously cleared. Any timing function combining registers D and E
may have spikes in it. Care was taken not to use function D and E (or their
inverses or combinations) in places where spikes might impair the behavior of
the system.
5-102
89633300
A
MEMORY CONTROL
MEMORY CONTROL TIMING
Function:
(Drawing number 89619100, sheet 4)
To provide all timing signals within the memory system.
Inputs
SIGNAL
f}SC
~SCA
BUSY
RX
SIGNAL SOURCE/
CONNECTOR PIN
[U56/6,8]
[U38/6]
[U38/12]
[u24/8]
NAME OF SIGNAL
Clock
Oscillator buffered
One of access selectors active
Refresh cycle selector
LOCATI ON
SHEET SQUARE
3
3
3
3
04
Cl
Cl
03
Outputs
A
A
AP5
AP5
B
B
[U9/5]
[U9/6]
[U9/9]
[U9/7]
[UIO/9]
[UIO/7]
C
[UI0/5]
[UIO/6]
C
0
0
E
E
F
[Ull/5]
[Ull /6]
[Ull /9
[UII/7]
[U45/8]
[U45/6]
[u42/6]
F
IP5
1
Clock phase 1
>
}
Clock 2.5
}
Clock phase 2
1
Clock phase 3
1
Clock phase 4
}
Clock phase 5
}
End of cycle
Clock 1.5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
6
02
02
C2
C2
C2
B2
C2
C2
02
B2
B2
B2
B4
A4
A2
Description of Operation
The heart of the memory timing circuit is a five stage ring counter (fl ip-flops
contained in U9, UIO, Ull. This gives the main timing signals (A,B,C,D, and E).
The counter is cleared by the BUSY signal (active low). The clock cycle is
selected by the Access Selector when the BUSY signal goes high. This frees the
counter which starts generating ~he clock pulses. The pattern of pulses is
shown in the following two figures.
89633300
A
5-99
(Drawing-number 89619100, sheet 4)
MEMORY CONTROL
MEMORY CONTROL TIMING
Memory
clock
I
,
2
6
4
3
a
7
I
I
8
,
1O
9
3
2
/I
4
6
I
I
~-
Disable
H
L
L~
cenabl.
H
REF
L
L:
STROBE
H
Pia
L
H
LJ
PI7
l
H
H91LDW
L
H
R/W
(Write Cycle Only)
l
2
I
SXA
CXP
SXP
,
I
t
4
I
5
I
I
a
I
7
I
8
I
9
I
10
II
2
I
I
I
I
1
I
III
I
I
I
H9JLDI f
4
I
I
I
I
3
I
I
I
I
III
I
I
I
I
I
I
5-100
3
I
I
,
2.5
2.5
I
I
t
89633300 A
5
I
H
L
H
L
H
l
H
l
00
\D
0'
\II)
\II)
\II)
o
o
»
&.
THE
CDC TY PE DESIGNATORS "'OR
U 6, U24, U25, U56 AND UII8
VCCR'......
\TI
I
\D
......
.......
\D
00
(NOT """" ,1'2A1J I
'''1
A RE
DETAILED LOGIC DIAGRAM
MEMORY CONTROL
PENDING.
MEMORY CONTROL
(Drawing number B9619100, sheet 3, conti d.)
CX Selector Flip-flop (U7)
K inputs to CX activate CX, J inputs deactivate CX
K input to CX (U7)
This is a 2,2 AND/OR input gate.
U7/9,10 are grounded, reducing it functionally to a 2 input AND
gate.
U7/12:
U7/11:
Synchronized CPU request.
Conditional activate CX if:
1) U5/9, 10 A (Sychronized) Refresh cycle is not requested.
or
2)
or
3)
U5/2,3
a)
and
b)
4)
or
a)
The (Synchronized) DSA priority or 32KW
are not blocking the CX selector.
The CPU address is not valid and did not
address this memory bank: U5/1: CPU request delayed 2 clock cycles.
Sychronized.
U5/3: Incorrect CPU address to this memory
bank
A DSA cycle is not desired: U5/6: DSA request was activate for at least
2 clock cycles to allow time for the DSA address
lines to stabilize. Synchronized.
and
b)
U5/4: Correct DSA address to this memory bank.
J input to CX
F(U7/1,2) End of cycle
B9633300
or
U7/3,4
and
and
1.
2.
3.
A
Condi t ional
The CPU address is valid and it is found that the CPU did
not desire usage of this memory bank:
uB/l: CRQ2 CPU requests delayed two clock cycles. Synchronized.
uBI2 : CRQ CPU reques t . Synch ron i zed.
UB/13: Incorrect CPU address to this memory bank.
5-95
MEMORY CONTROL
(Drawing number 89619100, sheet 3, cont'd.)
Preset input to CX (Active Low)
U7/5: Conditional deactivate CX if:
1) U38/10:
RX is active
2) U38/11:
SX is active
3) U38/9:
LPDR operation.
Clock input to CX
U7/13: Clock fall ing edge triggered clock connected to the
oscillator.
Qoutput from CX
U7/8: CX CPU cycle
Q Output from CX
U7!6:
not a CPU cycle.
ex
Indicating output signals
BUSY
(U41/6)
One of the 3 access selectors is active
"SC
(U56/6,8):· Osci llator buffered. Usually used to clock faJ1 ingedge
triggered flip-flops.
(U38/6)
Oscillator buffered. Usually used to cl~ck rising edge
triggered flip-flops.
Because the
~SC
line is long, it is double buffered and terminated
AUXiliary Circuits
The signal at P2A29 is always high because a pull-up resistor R2 is attached to
the line and the line is never connected in the computer. This line is used
during manufacturing testing to pre-synchronize certain signals.
5-96
89633300 A
MEMORY CONTROL
Signal Functions
(Drawing number 89619100, sheet 3, cont'd.)
RX Selector Flip-flop (U24)
J
J
inputs activate RX, K input deactivate RX
inputs to RX
R'X{U24/5)
RRQl (U24/3) Synchronized refresh request.
BUSY(U24/4) The memory system is not busy with a DSA or CPU
cycle (or redundantly with a Refresh cycle). Synchronized
(with the clock).
K inputs to RX
F{U24/9, 10,11) End of cycle.
Synchronized.
Clear input to RX Active low
LOADRA{U24/2) Kaster clear signal to deacti'late RX before
going into LPDR operation.
Q output from RX
RX{U241B) Refresh cycle
Q output from RX
RX(U24/6} Not a Refresh cycle.
Clock input to RX
Clock(U24/l2) Falling edge triggered clock connected to the
Osc ill ator.
89633300
A
5"93
MEMORY CONTROL
(Drawing number 89619100, sheet 3, cont'd).
SX Selector Flip-flop (u6)
J inputs activate SX, K inputs deactivate SX
J inputs to SX
MSXA(u6/4) The other memory bank is operating on a DSA request.
Ignore DSA requests on this memory bank. Synchronized.
ISA(U6/3) Correct DSA address to this memory bank.
(u6/S) Conditional Activate SX if:
1) U40/1,2: Refresh Synchronized cycle is not requested. The double
connections ensure that the condition is held when it
occurs (RRQ) and one clock after (RRQ1).
and 2) u40/4
The memory system is not busy with a Refresh, DSA or
CPU cycle.
Synchronized.
and 3) u40/S
The DSA request was activated during the last clock
cycle. This allows the DSA address lines to stabilize
so that the SX selec.tor wi 11 act ivate only on the correct
Synchronized.
memory bank.
K inputs to SX
U6/9,lO, 11:
F End of cycle.
Synchronized.
Clear Input to SX (active Low):
u6/2 Normal: When the memory system is in LPDR operation,
the SX reg i ster is constant 1y dea.ct i vated.
Q output from SX
sx(u6/8):
DSA cycle
Q output from SX
SX(U6/6) :
Not a DSA cycle
Clock input to SX
Clock(U6/12): Falling edge triggered clock connected to the
oscillator.
89633300' A
MEMORY CONTROL
(Drawing number 89619100, sheet 3, cont'd)
Outputs
SIGNAL
RX
RX
SX
$x
CX
ex
I
i
II
esc
BUSY
0sC'A
!
HsXA
\-
R/W
I
CXP
89633300 A
SIGNAL SOURCE/
CONNECTOR PIN
u24/8
u24/6
u6/8
U6l6
U7/8
U7/6
U56/6,8
U38/12
U38/6
P2A14
P2A20
P2B16
NAME OF SIGNAL
LOCATION
SHEET SQUARE
~
Refresh cycle
3
D3
~
DSA cycle
3
C3
~ CPU cycle
3
B3
3
3
3
3
3
3
D4
Cl
Cl
A4
C2
C2
Oscillator buffered
Active of access selectors
Oscillator buffered
DSA cycle bank selector
5-91
MEMORY CONTROL
(Drawing number 89619100, sheet 3, cont'd.)
Description of Operation
The basic units of this circuit are the three cycle selectors/registers RX, SX, and
CX (U24, U6, U7). These correspond to Refresh cycle, DSA cycle, and CPU cycle
respectively. Only one may be active at any time. After the cycle is over, all of
the selectors must be inactive for at least one clock cycle.
To assure this operation,
all the registers are activated and deactivated synchronously (through their J or
K inputs).
The active low c1ear inputs of these registers are used for clearing
them during LPDR (Low Power Data Retention on power failure) operation. The active
low preset input on the CX register is used for lPDR operation and to assure that
theCX register will not activate during a Refresh or a DSA cycle.
If simultaneously more than one access cycle is initiated at the beginning of an
access cycle, only the one with the highest priority is selected.
The order of priorities for the different cycles is as follows:
Refresh has the highest priority.
DSA has the next highest priority.
CPU has the least priority.
Because there can be two 32 kiloword memory systems, one in the main and one in the
expansion enclosure, communication between these two units is essential. The signal
MSXA prevents the DSA selector from being active simultaneously on both 'banks. The
CPU selectors on both banks may be active simultaneously, but the improperly addressed
bank may not reactivate until the next CPU is sent. The signal SRQE tells the
CPU selector that the DSA request has been accepted by one of the memory banks and
that the DSA address is no longer valid due to transients.
The DSA priority signal blocks the CPU access selector.
The 32KWE signal blocks
the CPU selector only on the upper bank if the CPU is in 32KW operation (a switch
,on the AB107/AB108 front panel). When the 32KW switch is active, the CPU never
addresses the upper bank. Blocking the CPU access selector assures the DSA that
its access time to the memory will not be delayed because the CPU selector is active.
On the lower memory bank in the main computer enclosure 32KWE is not connected to the
32KW switch. Instead it is permanently wired to ground so as to make it inactive.
5-92
89633300
A
I
00
\.0
P21150
(7\
w
w
w
o
o
tTl
tYCC3
:1
RG'WII
>'ZII21
""
... "
MO
YCC3~
470
\.T1
I
00
\.0
~ ~~~~~~=-~'~U~51,
iiiWil
~
I
~
I
61
~CD
"
I 3.5-- I
GNO PIA29
\AI
I ,-:--.-.--L .
•
I ~6~t~
• 1
47
GNO
a
68nf
a
.-<
;~o r:
J
~;J.
o.
GNO
PI6)P2A14
o
p
P2812 (GNO) P2821
0110116
':'
, --- -~.;;;w;z.;-C~IT-- -----,1
I
I
+57V
!!.L...J
iJii:PIAli
CPlM PII"
:~:
1221
I
I
-M~R
P2A30
P2831
R30
330
~ L ____
146:
If
4
I
R31
LOK
.
+ C, I
-'- 33"F
iOV
T
~
~u
(+5V SWITCHED)
C5.CI2.CI3
~_~
I
c
II
___ _'
R5I
~:~
v."
19 61 13
~I-il-:lt-I
• -51.'
• ~2A2~ I 14~H ~
2
B
I
I
R35
270
R41
8 9 00
43
~
~
F 6
ibLl!--
~ 6~
~t--_ _ _.:;:I0"f~ ~ ~
9 PIBI6
R36
~ 502 S
---'!
2
3 ]
SD7,-PIB05
,L-..!!
4 PIAI7 /DINIO
,7 PIAI8
DIN9
~2~70~+-__~r+~
4 U
13 U31
s~r~~~:
r!---!
00
~
270
SD6 PlB06
SD5'PIB07
4
U47 ' 5 , ! 146
"i\>++---"'H--'-fCO
~
U46
--.:;J.1ji\.
6 ~
~
..tp\
2\J
B ~
I--
I
II 0
I
I
14 0
13
I
R34
270
vee
Br--'~
~
R47
270
R46
~
S
I
4
3~
R49
270
r
* --
'"
-
2 0
I
5 0
--.!. I
----.!
~
270
~,
K 6
502
U45 ~
-t
i,
,!t,J
......
8
2
R44
270
R50
r--
r-+-++_~I0:t
I
.
270
,---+-+-t-+~-~9:i
V1
I
I
.,~:
IU60
_
U43 ,'~ ~ 146H
16 CD
~ U44
18
~
20 ~121 , , CD
r=----'"
22 ~ p!.J ~
_
4 PIA03
APP
SD9~~~------,
~
:
~
I
I
CHKO
5011 \. PIAI5
SD8,PIBI4
RRGTR
168
14 ~
0
12 PIB02 /,
13 I
,DINI
-
R43
270
vee
W
ORFT DATE
h~O
L-----------+T+-H-4::1:5i;,GI
~ ;JC
J!I
U64
DESCRIPTION
5010 \. PIB20
. / PIBI8
I
r
15
~~I
SD2,.PIB04
~~
L...t:. RRGTR
_
.,,;.,
l'R~Rr
I
~~
~ ~ 146H
2$' .........!! CD .!!.J U48
»
L~vL £CO
SD3'--"-'''!.l''-
~ ~ ~C
)
REVISION RECORD
,,- PIB03
500
501'- PIAOI
Q)
\D
.
-
12 PIB24 DINI2
j
DWG NO
C
89615200
SHEET
~
5
I
100V
A
HEHORYADDRESS
DATA IN:
(drawing number 89615200, sheet 6)
PARITY AND PROTECT BITS
Function: This circuit generates the parity and protect bits for data into the
memory.
The Power Switch Circuit for LPDR operation is also shown here.
SIGNAL
CONNECTOR
PIN
FUNCTION
LocATION
SHEET
SQUARE
In~uts
U45/6
u41/6
U31/6
U2716
SXA
DE
P16
Df}UT17
CPBH
SPBH
CHDR
B
[K]
[H]
['F)
1
6
c4
C2
C3
Cl
B2
B4
c4
A4
c4
C4
B4
A4
6
C2
I.
A2
D2
A2
B2
B2
5
I Pari ty Generator Outputs
t
!
[L]
J
[A]
[D]
P2A14
P2B10
P1B13
PlA12
P2A06
P2B08
I
I
5
6
Protect bit output
Out~uts
DINl6
DIN17
016
D17
PAR
PBC
P2B12
P2A10
P2A22
P2A13
P2All
PlAl3
Pari ty bit
Protect bi t
j
I
6
Functional Descri~tion
DIN16 and DINl7 are the parity bit and protect bit into the memory respectively.
Their outputs "are always low if DE is high.
The purpose of DIN17 is to rewrite
the protect bit during write cycles.
The protect bit read from memory (Df}UT17 line)
is stored into register UI8/5, 6.
The negative edge of B (P2B08) clocks this
register on clock 7.5.
On clock 8 of a write cycle, DIN17 will be the same
polarity as Df}UT17 was on clock 7.5.
5-68
89633300 A
MEMORY ADDRESS
DATA IN:
(drawing number 89615200, sheet 5)
16 BIT DATA AND PARITY GENERATORS
Function:
To select data from the CPU or DSA lines and transmit this data to
the memory.
SIGNAL
CONNECTOR
PIN
FUNCTION
LOCATION
SHEET
SQUARE
Inputs
SDOO -: SOlS
ALUOO .; ALU15
SXA
DE
CMDR
DSA bus
ALU (CPU) bus
P2A20
P2Bl8
P2A06
Outputs
DINOO -: DIN15
DSA cycle selector
Data Enable
Data Input to memory
[U45/6]
[U4l/6]
[U3l/6]
[U2716]
Par i ty Generator
Outputs
5
II
5
6
B3
B4
B4
5
I
I
5
C4
C3
C2
Cl
Circuit Description
The CPU data enters the memory system on the ALU (ALUOO~AlUI5) lines.
These
lines, buffered and inverted, go to the address latches.
Because their polarity
is wrong for data to the memory, they must be inverted again.
The AlU lines must be buffered because they may otherwise be overloaded,
especially if the AlU lines are connected to both the lower and upper memory banks.
The double buffered AlU lines enter data latches.
These latches are opened jf
SXA (P2A20) is high and CHDR (P2A06) is low.
Thus. data can enter the data
latch during clocks 4 - 8 of a CPU or Refresh cycle.
On clock 9 the latches are
89633300 A
5-65
....
....
VI
I
(7\
(7\
:I{L)
•••
47
•
PI6~P2A14
r-- --POW-;.;-;W;;.;-C';;I:;-----,'
I
SP8M):P:IA:I.~_ _ _ _-=~
Cl>iiii )..-......
____ -.
I
I
1221
lIr
.4
-L
6
+!I.7V P2AaO
iiPWri
PZII3I
t
10V
-
.~--+-..
R:llI
410
I I I
. '-'X
2.4.lI
(PSC
1'- . --'-
(DINI7
IP' V
(D17
.
II~,
II
•
-_.-
QC)
\J)
'"
\oN
\oN
\oN
o
o
):0
!
..OK
CII.CI2.Clli
IP'- . --.. (PAR
1
RliO
330
CII
+as,.F
V_
(+:lV SWITCHED)
I
I
I
I
L ____ :._t ___ --1
1961 13
P2BIO
D.UT ~7~ P2808
.
R31
DETAILED LOGIC
DIAGRAM
MEMORY ADDRESS
co
..
\D
0'
w
w
w
o
o
~
I@"
5.1.I@CIIP
»
, PIlOt
I
I
...."
111
vee
PlI..
ALU811"
SAI4
U
1.1 A"
AW4'
.. J
170
II~
I
Plall
J
110
Il1O
"ILD
vee
I ~ lIT"
4.
I
,
.!l~ UI4 ~
I •
,f:j~
I-'Ii
~.
1111
ZM
J
IIZI
III
1111
III
II
r:~
~r-;-II
140M
~
.
12
....
PRIGS
, 1i1U
PIAGI..,iiiili
,
PIA041:
, iiDii
~
I.
4
,
r::i 141"
•
~ ~
~I-~
;:J~
n
I~
~..
I
PlI041 1iiim
. PlIOI;,
, iii1iiI
I~
~I
• "I
141M
~~
"'"
~
....
I
PlAG7J iiDii
pn07
iIDI
PZAoa ii6iY
~
~
~
5 - 1.8
I~ 4
,
~
T
RI2
III
iii1i"
~
~
roe
...,Jt;
: ~PZI05
m :~PU05
.. , P21 ..
"0'
~~
I
II ....Mp.!2...--
r
~I
H
I •
lUll
... 12
II
1- Z
ALU
11-
II •
I 141"
--'..!!.!!
lIB PIIII
.~
~
0'
Lr;.!!!
I
140"--r.~
4
~
~
m , PZIOI
D
Ir--
.....! . . .
I
...!l- Ull
m
W
Sf'
--' ~ 217M
4.
I
vee
11M
III
148"
~
Fl'
...I~bL
I·
~~I
1111
III
31
~r-..---l!' I
. ,,"127
1M2.,
IIZI
III
,
i~~1rL-
I .... "
UIO
"
un
I"
14'"
UI2
vee
[CO
I~
use
40
r----"I t-• II~"
4.
"ID~I
, "ASO
"[V
l.Jgr-..--
"'4~1
>"All
I
PUOI
"
URI
SAil
1127
III
vee
.1.1 lIE IIIP
ALUlIi
V1
I
~
7ii"
PUll
~
I 148H ,I
51
U5S
"""-
8
r®&
J
PIBI9 J,
ElIIT COMPUTERS LTD
• 111.5"""
••
DETAILED LOGIC DIAGRAM
ME MOllY ADDRESS
•
MEMORY ADDRESS
(drawing number 89615200, sheet 4, cont'd.)
Description
The module selector selects the address of one of eight memory modules according
to either the DSA address or CPU address, and latches it.
The CPU lines are
active low, the DSA lines are active high.
The selector outputs are active
low.
If a memory module assembly is installed in the computer, it pulls the
DX# signal corresponding to its location to ground. Otherwise the DX1 signal
remains high.
CPU and DSA addresses must correspond to each other. That is
ALU12
ALUI3
ALUI4
must correspond to
II
II
II
II
II
II
SA12
SA 13
SAI4
DXI refers to module I (the second memory assembly location) and MDXI activates
memory module I.
The sign U (DXU) represents one of the memory location
numbers (I ~ 7).
The first memory assembly location is always occupied.
No information is on the module selector during refresh cycles.
The REF signal
activates all the memory modules during a refresh cycle, so decoding of the
module selector is not necessary.
However, the module selectors remain stable
during a refresh cycle and no spikes occur on them.
This is a safeguard and
not strictly necessary since the REF signal provides timing on the memory modules
for the module selectors.
If all eight memory modules are installed the module addressed is the one that
is used.
If less than eight memory modules are available the module that is
used is selected by the storage-wrap around table, built according to
a)
b)
how many modules are available
which module is addressed.
Formulas for this are given below: 12, 13 and 14 refer to address bits ALUI2,
ALUl3 and ALUI4 or SAI2, SAI3 and SAI4.
The wrap-around table resulting is
also shown.
89633300
A
5-61
(drawing number 89615200, sheet 4, cont'd.)
MEMORY. ADDRESS
MDXO
MDXl
MDX2
MDX3
MDX4
MDX5
MDX6
MDX7
=
..
=
=
=
=
=
=
(DX 1. 12)
(
12)
(DX3.12)
(
12)
(DX5.12)
(
12)
(DX7.12)
(
12)
(DX2.13)
(DX2.13)
(
13)
(
13)
(DX6.13)
(Dx6.13)
(
13 )
(
13)
(DX4.14)
(Dx4. Pi)
(Dx4.14)
(Dx4.14)
(
14)
(
14)
(
14)
(
14)
Storage Addressing Wrap-Around
STORAGE SIZE
(KWORDS)
STORAGE MODULE ADDRESSED
o1
4
8
12
16
20
24
28
32
36
40
44
48
52
56
60
65
234 5 6 7 8 9 A B C D E F
o0 o0 o0 0 0 0 0 0
o1 o1 o1 0 1 0 1 0
0 1 2 2 o 1 2 2 0 1 2
0 1 2 3 o1 2 3 0 1 2
o 1 234444 012
o 1 234 5 4 5 0 1 2
o1 2 3 4 5 6 6 o1 2
o1 2 3 4 5 6 7 o1 2
o 1 234 5 6 7 888
0
0
0
0
0
o
o
1
1
1
1
1
1
1
234
234
234
234
234
234
234
5
5
5
5
5
5
5
0 0 000
1 o 1 G 1
2 o 1 2 2
3 0 1 2 3
3 4 4 4 4
3 4 5 4 5
3 4 5 6 6
3 4 5 6 7
8 8 8 8 8
6 7 89 898 989
6 7 8 9 A A 8 9 A A
6 7 8 9 A B 8 9 A B
6 7 8 9 ABCCCC
6 7 8 9 ABCDCD
6 7 8 9 ABCDEE
6 7 8 9 ABCDEF
EFFECTIVE
MODULE
ADDRESSED
For example, if the computer has 16K (16,38410) words of storage,
the highest permissible address is 3FFF16.
If the program attempts
to address location 504016 (located in a nonexistent storage module 5),
it actually references location 104016 in module 1.
5-62
89633300 A
00
\0
.
(7\
W
W
W
-
11'
AEVISION RECOIIO
o
o
ll2r-~
~
J>
v_
AW7L ~PIAa.
1
I
I
I
... PIIU
I
I46H
~
....... PIUO
r--
,.
..
ALII .. ,
...
,
PlAIt
I
I
y
~~
II
4
~
2
,
vee
ALII.; PI. .
4.U®"
I4IH
UI7
.r-L~
U@)-
II
I
I46H
"re
UI7
vee
II
I
~I.
III
210'
Y
I
IIZ1
110
11111
Il1O
I
-
I~
lUI
Il1O
PIli' "1.1
0
.
-
--
CODE IDENT
DETAILED LOGIC DIAIII. .
IC
1IIII000Y ADDIIES'
DWG NO
....zoo
SHEET
1
I
I
I~V
MEMORY ADDRESS
(drawing number 89615200, sheet 4)
MODULE SELECTOR
Function:
SIGNAL
Ineuts
ALU12
ALU13
ALU14
ALU15
SA12
SAt3
SA14
CRI
CXP
SXP
HflJLD
DXt
SIGNA(SOURCE/
CONNECTOR PIN
DX5
DX6
DX7
P2A16
P2B09
P2B16
P2Bl3
PtB27
PtA3t
PtA30
[AG]
[AF]
[AE]
[AH]
P2AOl
P2BOt
PtB31
P2Bll
P2B06
P2B05
P2A05
Outeuts
MDXO
MDXl
MOX2
MDX3
MDX4
MDX5
MDX6
MDX7
CAA15
P2B03
P2A02
P2A04
.P2B02
P2B04
P2B07
P2A07
P2A08
PtB19
Off
DX3
DXli"
5-60
To select one of eight memory module cards.
LOCATION
SHEET
SQUARE
FUNCTION
4
B4
D4
C4
A4
B4
D4
c4
D4
D4
04
c4
D3
B4
A4
A4
A4
A4
A4
I
IMemory Module Address
CPU
(from
I,
j
I
I
i
I
Module Address
i from DSA
~Memory
I
I
4
3
4
J
00FF 16 address from CPU
CPU cycle selector
.0SAcyctesetector
..
i
I
Memory Module
Presence Indicators
!
I
I
I
i
I,
I
4
4
Memory Module
r,ie 1ector Signa 1s.
4
-.
Dt
Cl
Cl
Cl
Cl
Bl
Bl
Bl
Al
89633300 A
(drawing number 89615200, sheet 3)
MEMORY ADDRESS
COLUMN SELECTOR
Function:
SIGNAL
To select and latch the memory column address to the memory card.
SIGNAL SOURCE/
r.ONN~"('""nR
PIN
FUNCTION
LOCATION
SQUARE
SHEET
Inputs:
ALU07
ALu08
ALU09
ALU10
ALUll
SA07
SA08
SA09
SAlO
SAll
CRl
CXP
H0LD
P2A09
P1A28
P1A22
P1A27
P1B28
P1B23
P1B30
P1B29
P1A26
P1B21
P1B22
y2/8]
P2A25
3
Memory Address Lines
\from CPU
I
I
I
I
,I
I
I
i
,
;
Memory Address Lines
from OSA
,
,I
\
I
00FF 16 address from CPU
CPU cycle selector
Latch hold (row,column,
module)
3
2
2
04
c4
C4
B4
A4
04
C4
B4
B4
A4
04
A4
B4
Outputs:
ACA5
ACA6
ACA7
ACA8
ACA9
P2B19
P2B17
P2B24
P2A18
P2B20
3
Memory Column Address
Signals
I
I
I
3
01
Cl
Bl
Bl
Al
Circuit Description
Note:
This circuit is similar to the Row Selector.
The column latch selects and latches the memory address from either CPU or DSA
address.
The output of this latch is sent without decoding to the memory chip
column address inputs (A5-A9). The memory address inputs are arbitrarily wired.
89633300 A
5-57
MEMORY ADDRESS
;
(drawing number 89615200, sheet 3, cont'd.)
However, CPU and DSA addresses must correspond.
The CPU address must select
the same locat ion in the memory as the DsA address for that location.
Thus:
ALU07 must correspond to SA07
II
II
ALU08 II
SA08
II
II
ALU09 II
SA09
II
II
II
ALU10
SA10
II
II
II
ALUll
SA 11
The DSA address inputs are active high.
Jow.
The CPU address inputs are active
When CRI is active (high) ALU07 appears as low, and ALU08-ALUJl appear as
high.
During a refresh cycle there is no special information on the coJumn address.
However, the lines are held stable during this time to reduce system noise.
The latching circuit is similar for the row, column and module selectors.
It is described opposite sheet 2.
5-58
89633300 A
..
~
"
00
\D
~
\AI
\AI
\AI
o
o
»
I - _ _....;.-.:~"""
___(
iiiiiiii
~
V'I
I
V'I
V'I
......
V'I
I
V'I
~
DlTAlLED LDeIC DI_AM
MEMOIIY ADDIIESS
4
MEMORY ADDRESS
(drawing number 89615200, sheet 2, cont'd.)
Functional Description
The row latch selects and latches the DSA or the CPU addresses.
The outputs
of this latch, through the Refresh address Selector (ARAO through ARA4) , are
sent without decoding to the memory unit row address inputs (AO through A4).
The memory address inputs are arbitrarily wired.
However CPU and DSA addresses
must correspond, i.e., the CPU address must 5elect the same location in memory
as the DSA address.
That is
ALU02
must correspond to
ALU03
ALU04
"
"
"
ALU05
ALU06
"
"
"
"
"
"
"
"
"
SA02
SA03
SA04
SA05
SAo6
The DSA addresses are active high; the CPU addresses are active low.
When
CRI is active (high) the ALU address output appears as all zeros.
Although no
decoding is performed, (the 5 to 32 conversion is performed in the memory unit)
the latch does go through a Refresh Selector.
When a refresh cycle is being
performed, it is not the latch information that goes to the memory row address
but the refresh row address from the refresh address counter (U33).
Circuit Description
The row refresh address is stored in a five bit binary counter circuit U33.
ADVANCE (P2B14) advances the counter just before a refresh cycle is performed.
L0ADRA (P2A29) presets the counter so that BRWRA (P2B29) goes active (low)
on the 32nd count advance after L0ADRA.
BRWRA remains low only during the
32nd count.
exception.
The outputs of the counter are arbitrarily wired with one
The memory units save power if the memory row address bit A4
goes low to high after the last Cenable was inactive.
89633300
A
5-53
MEMORY ADDRESS
(drawing number 89615200, sheet 2, cont'd.)
This is very desirable for lPDR (low Power Data Retention) operation.
Thus,
ARA4 is wired so that it will often be low on the 32nd rapid refresh cycle,
and high after the 32nd rapid refresh is completed.
The row address information is taken through the Refresh Selector gates
(AND-OR gates U36/8, U35/8, U35/6, U51/8, U51/6).
The control inputs (U36/1
and U36/10 fO,r ARAO and corresponding terminals on the other gates) are driven
from RXA and its inverse; RXA active selects a refresh cycle row address, RXA
selects the outputs of the DSA/CPU address latches.
This arrangement avoids
spikes on the row address lines (ARAO ~ ARA4) when changing from a DSA or
CPU cycle to a refresh cycle.
Row, Column and Module Selector latching
The row, column and module selector register share a common latching system.
This is described here.
The signals SXP, CXP and HelD from the memory control assembly ~re designed so
that spikes will not occur on the row, column or module selectors.
By
overlapping signals so that SXP (Ul/8) and HelD on a DSA cycle or CXP (U2/6,8)
and HelD on a CPU cycle are never zero at the same time, the selectors will
not generate unnecessary spikes by blocking all the information lines.
HelD
overlaps with CXP (SXp) at the beginning of the cycle so that the new address
can be fed into the latch before the old one is finished.
CXP (SXp) overlaps
with HelD at the middle of the cycle assuriilg that the address is latched before
it is blocked.
5-54
89633300 A
MEMORY ADDRESS
(drawinq number 89615200, sheet 2, cont'd.)
DSA Cycle
Input
(Active High)
SAO 1
SAOO
L
(SXP low)
Output
(Active Low)
lKO
1K1 1K2
L
L
~I
L
H
H
L
H
H
H
H
H
L
H
CRI (HiQh)
H
1KO
H
H
H
L
L
Refresh Cycle
Input
---
RXA
H
H
H
H
L
H
H
H
L
H
H
L
H
(CiP low)
CPU Cycle
Input
(Active LOw)
ALUOl ALUOO
L
L
L
H
1K3
Output
(Act i ve Low)
1K1 1K2
lK3
H
L
H
H
H
L
L
H
H
H
H
~
H
H
H
(RXA high)
Output
(Act i ve Low)
1K1 1K2
1KO
L
L
L
1K3
L
The kiloword selector must be stable at clock 1.5 so t~at only one kiloword
will be activated by the Disable signal on the Memory module. Note that the
critical kiloword selector circuits use super-high speed TTL circuits.
89633300 A
5-51
(Drawing number 89615200, sheet 2)
MEMORY ADDRESS
ROW SELECTOR
Function:
cycles.
Input
SIGNAL
ALU02
ALU03
ALU04
ALU05
ALU06
SA02
SA03
SA04
SA05
SA06
CXP
SXP
HI/JLD
CRl
RXA
L0ADRA
ADVANCE
To select and latch the memory row address for DSA, CPU and Refresh
SIGNAL SOURCE/
LOCATION
FUNCTION
PIN
SHEET S_Q.UARE
"
P1B10
B4
2
P1A10
B4
. Memory Address 1 i nes
02
P2A17
from CPU
P2A15
C2
1.1
P2A12
B2
B4
P1BOl
B4
P1A06
02
}Memory Address 1 ines
P1B09
from DSA
C2
P1A09
J
B2
P1A21
B4
CPU cycle selector
P2B26
A4
P2B28
DSA cycle selector
B4
Latch hold (row, column, module 2
P2A25
04
00FF 16 Address from CPU
P1B22
3
2
Refresh cycle selector
03
P2B27
2
load Refresh Address
A3
P2A29
Advance refresh address counter 2
P2B14
A3
~ON~TOR
Outeuts
ARAO
ARAI
ARA2
ARA3
ARA4
BRWRA
5-52
P2B15
P2B22
P2A23
P2A21
P2B23
P2B29
I'
2
I
} Memory Row Address
Signals
32nd Refresh Address count
2
B2
B2
01
Cl
Bl
Al
89633300 A
MEMORY ADDRESS
(Drawing number 89615200, sheet 2)
KILOWORD SELECTOR
Function
This circuit selects one of four kilowords on a memory module.
Inputs
SIGNAL
ALUOO
ALUOI
SAOO
SAOI
CXP
SXP
HilLDW
RXA
CR1
SIGNAL SOURCE/
CONNECTOR PIN
PI812
PIA II
P2A24
P2825
P2B26
P2828
P2AI9
P2827
U42/12
FUNCTION
1
CPU address bits
LOCATION
SHEET SQUARE
2
} DSA address bits
CPU cycle selector
DSA cycle selector
Latch hold (Kiloword)
Refresh cycle selector
00FF l6 Address from CPU
2
3
04
c4
04
c4
84 I
A4
c4
03
03
Outputs
I KO
m
1K2
I K3
89633300 A
P2A28
P2B30
P2A26
P2A27
I'
2
) Kiloword Selector Signals
to Memory Module
J
2
02
02
C2
C2
5-49
MEMORY ADDRESS
(drawing number 89615200, sheet 2, cont'd)
Description
U19 and U3 select and latch the first two DSA or CPU address bits. This is
achieved as follows (for timing diagram - clocks - refer to Figure 4-6) and to
the timing diagram associated with sheet 4 of the Memory Control circuits.
Between clocks 1 and 2.5 either
SXP
(for a DSA cycle) or CXP (for a CPU cycle)
will be active low while H~LDW remains low.
This allows SAOO, SAOl (for a DSA cycle) or ALUOO, ALUOl (for a CPU cycle) to
pass through U19 and U3. At outputs U19/8 and U3/8 the signal is inverted.
The signals are re-inverted and fed back into U19/1 and U3/1 in separate AND
gates U34/1, 2 and U34/13, 12 forming a latch. At clock 2.5 H~LDW goes high,
allowing U19/1 and U3/1 to pass through to the output (thus, the address is
latched). After clock 2.5 SXP and CXP will be high so that their corresponding
addresses can change without affecting the address that is latched. At clock
11 H~LDW goes down, losing the address-latch. The address is no longer needed
after clock 10 because the Disable signal blocks the kiloword selector on the
memory module assembly. Dropping the H~LDW signal at clock 11 decreases
through-put time for a new address. The address selector must be stable by
clock 1.5 of the next cycle when the Disable signal does not blook the kiloword
selector on the memory assembly.
The signal CRI is inverted and ANDed into the CPU address lines (refer to sheet
3). When this signal is active (high) andCXP is active (low) and blocked,
ALUOO and ALUOl appear low; CRl is a signal used by the CPU to automatically
address location (OOFF)16 in the memory (second Index Register).
All inputs to U19 and U3 are active high.
This implies that SAOO, SAOl are
active high.
Outputs U19/8 and U3/8 are used by the one-out-of-four decoder (U17, U50) to
select one kiloword of the memory module (lKO through lK3). The kiloword
selector output is active low. If the memory system is performing a refresh
cycle, all the kilowords of the module are activated.
The following tables summarize the operation of these circuits (in tables;
H = logic high,
5-50
L
= logic low).
89633300 A
co
\,0
w
MEMORY ADDRESS
~
o
continued from previous page
0\
w
>
Address and Control
Lines to Memory
ALU12 f AL014~ Module
SA12 + SA14 ~ Selector ~ MDXO + MDX7
Module Presence DXl + DX71'7
(first module is
al\iaYs present).
Data
t
,
PU : fALUOO + ALU15 # 16
lLALU08 + ALUIS
From DSA: SDOO
f
SD15
~16
)V
Protect Bit}
from Memory
JrHodule Address
Unes
L
I
I Data-Inl
l~DINOO
I
4
I
D~UT
17
f
DINI5
Decodes the memory
modul e address and·
selects one of eight
memory module
assemblies.
Data to Memory
Parity Generator Output
Pari ty BI t
IProtect BIt
Logic
Descr i pt ion
DIN16
DIN17
Selects data from
the CPU of DSA 1 ines
and transmits this
data to the memory.
Parity Bit}
Protect Bit To Memory
PAR1 .. IMemory Controll:to CPU for Pari ty Check
DI7Jr
HX17 = Protect
Register Status.
Generates the parity
and protects bits for
data into the memory.
VI
•
.t:r
.....
Memory Address Block Diagram
V'I
I
-
I
I
REVISION RECORD
SHEET REIIISlOII STATUS
~
(X)
1/1/ II£v
I 2 I 4 5 5
. , , - SHIET
llUEIlENCI LETlE II
."
-
SHEET
."'EIlEIICES
IS"
Z
S
[II ~~N
,~T
4
•
5
A
IZ
n
,
IS
14
12
14
cs
D4
II
e4
D4
L
.
el
D4
ez
D4
II
DZ
A4
I'
CZ
I
II
IZ
S
T
D4
OS
U
V
W
e4
x
M
DESCRIPTION
U'''-
To
DR_NO EIIIIOIII ON'
1HZ' T.p 54
SH 4, UZ4-J. U24-5.IIIO, ""
SH5, PlA05
SH., "","" ,!NYEIn'Eil
UI4-II,ID
01 eK7I5
eORREeT DWG EilRORS
09 CKIII
_
U: 1111 WAS "".
Sill LII:,,"_S l1li1.
liEF DESIG. DID NOT 'IT
ASSY PWG.
A4
e
A4
@
Y#
I lICe
Ivee
v.o'
IS
CS
@
es
D4
CZ
@)
-'_".
1;'"
-
1At- "~Jot. ..
~
-".~
1Wit.
.!r-+ jsor.", ~'L
$II'
4
IIU
IIICC
..0;.
es
DS
D4
14
AI
AS
es
DZ
Ae
e4
DZ
es
n
AD
AE
A4
DS
D4
AI'
A4
DS
D4
D4
IS
84
ez
es
04
l1li
N,TES'
I. ALL RESIST.IIS ARE 0.25 WATT S'I(,
es
z. THE VtfLTAGE SUPPLIED Tf ALl THE INTEGRATED
elRCUITS
14
C4
i
PUSI
IS Vee EXCEPT 1"11'
I
UI7.U". UU. U3S.USI.U50.U5I.AND USZ T' WHleH
Ve.. IS SUPPLIED
-'IICC
~
'ND~ PIAn
+
;;~
PlIII
CIO
SSpI'
IOV
pZAOI.
CI-C4
:::~C.-Ct
.IN'
'''D,
pZIZI
(X)
'''D
t
UNLESS \'''IERWlS[ sprCIFED
DltIlN51tJ11 AIitE 'N INC"S
~
\.0
~
\AI
\AI
\AI
Cl 2
...
!!
t.
2 PI.AC[
1:
ANG ... ES
t.
DO NOT SCALE DRAWING
I
FIRST USEe ON TITLE
Of
e .____:~
• >-
APPR
FI=----_---
..,,.
ZS./~-II
&~.
MATERIAL _ - - - - -
LOGIC
DETAILED
DIAGRAM
ABI01-A
'IIImjmllMbl II.'''·1f
""'U"'k~
"'
~
D4
AA
'ND,
I
til)
I va;
111
III
"if
VA
,.~
~. If"'
r=:~"!....=",:,,~~"
FtI.TEll. _ " . , ".toN
TDSMJ.
1125
III
CHICD A",
t.iif:i1i 14.:1.
DETAOIED LIST AV WAS. PI
~-.urt
DiTE
_T
<_ n ....-
07 CI< 770
A
D4
Y
AG
AH
AJ
.
A4
AS
AI
z
+ IV
1/
D
Q
ECO
OS CKJ5'
01 CII 5Z5
/
I:.NGR
MFG
Q.A
~
...
• :-t!-
A,~
1Ui1•
;11,i
[.
l'
iI
~
MEMORY
~ •. 1J
I." ....
tf/Y.
~
TOE IDENT
<·:A. E
I
~
ADDRESS
Ic I
ORAWfliG NO
89815200
-TSHE£T
...
f
01
&
MEMORY ADDRESS
The Memory Address circuits receive the address buses from the DSA channel
and from the CPU and generate the addressing signals for the whole memory
system. They also generate the data parity and protect bits. The memory
data input is routed through this assembly, it also accommodates the switching
circuit for the switched +5V supply (V CCS ) used during LPDR (Low Power
Data Retention) operation.
This page lists the principal blocks of the Memory Address.
I ts block
diagram is given on the next two pages.
THE MAIN FUNCTIONAL BLOCKS
- ......- - - - -.
",
Des i gnation
-......... ... ...--". - ..----,
- -~
Shown on sheet
Ki loword sel ector
2
Row selector
Co.1 unm se 1ec to r
Module selector
Data in: 16 bit data and parity generators
Data in: parity and protect bits
2
89633300 A
--.-,-~
3
4
5
6
5-45
V1
I
J:C7'
MEMORY ADDRESS
The Memory Address circuits are accommodated
on a single 50-PAK printed wiring board. The
logic circuit diagram is given in drawing
number 89615200, (sheets 1-5). These pages
show the pr i nc i pa 1 blocks mak i ng up the Memory
Address together with the main input and output
signals. Both the circuit and the signals are
described in detail on pages ~ssociated with
corresponding sheet of the circuit diagram.
CRQ
SRQ
CXP
SXP
RXA
CRI
HI1JLD
HI1JLDW
LI1JADRA
ADVANCE
Address and Control
Lines to Memory
CPU (ALU) & DSA (SA)
Address and
Data Li nes
ALUOO, ALUOI
SAOO,
ALU02
SAOI
ALu06 5
T
-,I-
SA02 .: SA06
ALU07, ALU08
00
\.0
C7'
'oN
'oN
'oN
T
~
SA07
T
SAIl
Ki loword
Selector
Kl }
1lKO
1K2
1K3
Kiloword
Li nes
Row
Selector
ARAO
ARAI
ARA2
ARA3
ARA4
BRWRA
Row Address Lines
(decoded in Memory Unit)
(5 .. 32)
Selects and latches
the memory row address
for DSA, CPU and
Refresh cycl es.
Column.
Selector
ACA5
ACA6
ACA7
ACA8
ACA9
Column Address Lines
(decoded in Memory Unit)
(5 .. 32)
Selects and latches
the memory column
address to the
memory ca rd.
5
ALUll 5
5
Descr i'pt ion
Selects one of
four ki lowords
on a memo ry mod uIe.
Address
o
o
»
Memory Address Block Diagram
(diagram continued on next page)
"Pages 5-40 to 5-44 are unassigned ll
5-40/5-44
89633300 A
4
VI
~
C!
1
\AI
(X)
r.:o!
o
_)r"e
'I
OINIY'-
11
=~~=
.
Iii
1":"~IM'
'1>' •
(1101
pi
~
.,)r_1W
•
1>'1111
I
I
I
1,,:, ICIIIOI
r.~? Iell"
IV..
?
.p.
.pl'
r.r lCIIII
[? [eM;
.,
1~:, Ial42
1,- tIM.
1,,:, lCll4?
"I
I
,
IT lCRM
(11)1
IV.
al
'1
,~.
,
'As
p"
I
t -rc;;
1,.111.
l'u 1M
,S
hi? lCIIS?
01')1
IT lCMI
I,,:: ICll40
I v..
21
•
p~
B
_)'I.U
_::
DlNII
~s
r
•
1Ir==J>.
,~rrI8
lun:
JO
4
rt
?
I~
,
, @I
E
:v..
I
(X)
\D
<7'
AI
U
\AI
\AI
\AI
0
0
»
..
4
~
t
64
011
\.0
!
Vol > :::::
~
w
0
0
("')
35
om
0
-
39,F - 4700F
35V -
+ 04
530F lCI
_
R2
IK
RI
100
2..
VCCI/-"W'>
V.
;;j=::IOnF ;;j=:: 10tIf'
1iJ5Wlf) P2810
iii)!&!
C69-C72,C77
CII,CI2,C84,C89,
ctI.cM,CH-C98
100nF.
1
r
.... > Plnl
•
I V.
iF i- ~ f..-t'"~'·
:e" --
W
W
Z
M
II~
M
CRI
CRS
i::
;l:
2N2_
PI811
CI
G
GIlD PZAOI
Voo >PIAOI
~
y
1: C74,c7ll,C7lI,CIO,C90,
• v..
~
EC'7,ClB,C1JR/W'I'lIUF • . ____
470.'
V.
65
GND P2821
15
..
II
GND PIA29
Ie
~QI
iii' P2121
iii >P2801
011
,!1215' 112
t
I
....
I~
l!!r-:-w
Ie
iii
!:t CIOII
• +2IV
+
+2Iv>P2AOI
67
~.,>P2AII
I
T4.7pF
.... 10V
V..
!1:C5. Vee'
'T'llpF
.... 10V
_IIV>PIAZ6
BI
CII52
IN4005
calX
470nFT
en,
C78,
CIII,
CIZ
~ CIIlI
II N
CIIS ~ R6
270
..L CII4
'1'£
~
2
xl ~
-
.-IIV
m
TC60,:7I,C95
t [ CI04
»toF
470nF
....
>P2A24
1111l...!ra1
L!!!.J
RII
v.
IB
Vo..
mIIII
)PZA07
A
A
\II
I
W
\.D
!iOX'PZ-
..
DETAILED LOGIC DIAGRAM
MEMORY
o
V1
I
r---------------------------,
\oN
0"
I
,"
+ZIV
1£
ILEV£L
'S"",TEII
11104
.
w
•
IC;IIICUITL:
I
I
II
+
II
I,
rev",.,W.IIl
c
£
(X)I ••
THE COII_UTS INCLOIID III DQHED LIIIIIS FOil II " LEVIL ."'TIIIIL.•.1
THE liEF. DESIt. t1F IT CDilPONINTS FOR THI DIFFEIIENT ..LEVIL StlFTEIl
CIRCUITS IHOWN ON Ttli lHEET MI lIVEN IN THETMLI.
DESIIl. °NColN TAILI NEANI: COIIPONENT AND LINE / I'IoT ODNNICTEO IN
THI SPECIFIIO I..'
.
(Y)4
.41
I@---
10
- II
I--.
L.S...
";---
IW
L.U
be
~v
I / ..(.1. 10 1
I~
"r FAST\;z~~Z.5,4
@S,4
'I
"""
1 jr~pc"182"
i
v,' FA!!I
'No
lliiji" .. ·~2.S.4
fiQ
.,4
':"""~2
J1
OQ
\.D
0"
\oN
\oN
\oN
o
o
l>
,
o
T
fl)
",/
//
1..1. II
1. .••
I
'ii'
CINI8
. . . . .I2
.1.4
/I
121''';;'' "''''8 2 •1 ,4
DETAILED LOGIC DIAGRAM
MEMORY
LEVEL SHIFTER CIRCUITS
'+
~
(X)
\0
0'\
\AI
\AI
\AI
o
o
I:
»
ARAO) PU25
ARAI
>P2A21
3
3
Ef}
14~H
Eft
I4~H
4
UI
4
I
8
14~S
U7
ARA2
>
P_2~A::.2,,"1_ _ _ _ _
I
~
14~S .
L.S
I
AO @Z,3,4
I
AI @2,3,4
RII2
41
RIOI
,.!.!
45
Rill
41
.!eo.
U3
I
I L.S
U3
5
"I
S
2.3,4
&.
AM3) P2125
~4
13
I
L.S
:;..,
I
~~
THE TYPICAL LEVEL SHIFTER CIRCUIT IS ON SHEET 5
@2.3.4
OUTPUT
ARA4
>_P_21_2=1_ _ _-
ACA5
>P2821
i
"I
~
14~H
13
12
L.S
.1:.....
,
I L.S
RI22
.!!
13
I
RI21
12
I
~~
@2,3,4
AS @2,3,4
UI
~
ACAI) P2823
3
14~
4
L.S
1;
I
AI@2,3,4
UI
ACAI
ACAI
>P2822
>P2AI7
I
I~:H
2
~
5 I:H
I
~
1114~H
REFERENCE
QA
QI
Qt
10
I L.S
RI23
I
RI20
L.S
I L.S
,.!.;.
!.eo,
~o,
R"I
43
I
AT
8
2,3,4
DESIGNATIONS IN LEVEL SHIFTER CIRCUITS
QO
ItA
•
IIC
au
CA
CI
CU
AO
Q80
068
014
Ql6
A90
1161
123
II4S
CI8
C40
Cltl1
Al
016
Q54
Ql0
Q32
A86
1163
RJ9
141
CI4
C36
ClII3
A2
Q19
Q57
QI3
Q3S
A89
III
122
R44
CI1
C3t
Cltll
A3
018
Q56
Q12
Q34
A88
R115
121
143
CII
C38
CltIS
~.4
Q77
Q55
QlI
Q33
AS1
RIi4
120
R42
tiS
a1
Cltl4
AS
Q90
Q68
~.
1146
Rloo
R11
R33
ASS
C2II
CSO
tRZ9
A6
QI19
067
023
Q4S
R99
R16
R32
R54
C27
C4.
CR28
A7
091
069
Q2S
041
Rl0l
R18
R4
A88
C2t
CSI
CIt:lll
AI
IJ8II
Q66
Q22
Q44
R98
A15
R3I
R53
C2t
C48
CR21
A9
081
Q6S
~1
1143
197
A1.
R30
R52
C25
C41
CR26i
I---
~
ACA7) P2AU
SIGNAL
10
I
I
A8@2,3,4
51
A9 @2,3,4
UI
~
\11
I
\AI
""-J
DETAILED LOGIC DIAGRAM
MEMORY
LEVEL SHIFTER CIRCUITS
.
,
~
~
REVISION RECORD
REVI
00
\.0
0'
3 512
4 256
2 128
I 64
15
32
--.8.. 16 AOOoo
7
»
J.
H
...i
1111'1
5®, R/WO
2,3,5 AA lSl ~HO
Y
FA T
,3,5@CENO
ORFTI DATE .ICHIMEMj
UOl7
12 A2CD AI,2~
512
256
x-v
2 128
64
~ 32
,~
7 16
9
,.
~
~
3,5
2,3,5~@R/WI
AE
:
FAST PCHI
18
LJ
'~~a
16"
,3,5@
AOooO
c
Lt.&:.
VCC
G2
I> MEMj
UII7
~A2CD
AI2
RI62
180
14
3
512
4 256
2 128
I
64
~ 32
8
16 AOOOO
Lt.
x-v
~
~
8
J
I~
~@R/W2
,2,3,S AJ FAST PCH2
8
3
RI61
I~
'2,3,S@ CEN2
.".
2,3,6
2,3,6
2,3.6
2,3,'
2,3,6"4P'
I
-!~
~2,3,6 AT
4
I
,2,3,6( AV
2.3,6 AX
2,3"
2,S
:?
'2,3,6 AR
3
4
512
256
x-v
Y
AS
AS
A7
-.9.
9
~
~
AOOOO
~
AIT
V
6 G2
RCVR
162C
UI5
2
ltJ)
1,2-
2,3,~
RI42
&,.
4
P2A02 J
oeUT 17
330
2'110
&
.".
18
2.3,5@ R/W3
FAST PCH3
. Z,3,5@C£'N3
A
"~;
16
a
G2
I>MEMI
U 317
L.J!fA2CD
V"1
I
W
V"1
2,3,8
AI.~
2 128
I 64
15 32
8 16
7
B
~2,3
G2
I> MEMJ
U217
12 A2CD
2N2222
RI60
IS
2".
~~~a
3,S
1'"
.-Lt.
&.
AI,2
p.!.!-
WBIT COMPUTERS IT!
•
IUISIDI •• '
0'
I
DETAILED LOGIC
Illml:TIImlB
.,
'"
DIAGRAM
MEMORY (BIT 17)
rODE 'DENT
1 :'1 owG NO
C B961~
.
SHEET
4
REv
A
V1
r----------------------------,
I
W
'"
I
+28V:
I&.
I
I
LEVEL
I !HlHER
I CIRCUITIL.SI
V"
&.
:
I
:
THE
I
I
RI04
I
I
I
18
34
X)2,!
FASTPCHOTD BIT
RL
""-i
~-L.S-.2-1
>= ..
.@
I
00
\.0
'"
~
>
',~
'0
L.S.4
.< 0)
L.U
I
'(11)
L.S. 10
I
.@
•
~r
17
REF. DESIG. OF IT COMPONENTS FOR THE DIFFERENT LEVEL SHIFTER
CIRCUITS SHOWN ON THIS SHEET ARE GIVEN IN THE TABLE.
OESIG 'NC'IN TABLE MEANS' COMPONENT AND LINE NOT CONNECTED
THE SPECIFIED L.S
(YH
38
!
41
'No
~
I• 1
L.S.3
>
~~3
THE COMPONENTS ENCLOSED IN DASHED LINES FORM A LEVEL SHIFTER( L.S.l
CENO 02.3,4
I '_@.",.
FAST~I PCHI
t
@'"
PCHI@2
)J
~
o
""
•@
®=2
S
I
rAt;ill"'y"y
~"T
.
11
L.S. 12
~
I
~.~
};
!
(Atj3,4
e6
CEN3@2,3,4
i ""@"'"
W
W
W
o
o
m
DETAILED LOGIC DIAGRAM
MEMORY
LEVEL SHIFTER CIRCUITS
.
IN
[
~
Cot
V1
"
I
W
~
~
~3512X_T
256
III
I 14
-=========-=11
r
:
---""2
)
1
:
I
AOOOO
iiiiii"
.IT
I&A
'H
~===ffffftmF~~
! 511 X-T
118
t~+4~~:tl:~BIH
H-+-...Jl6U~
18
4.5
-4512
.....,. 258
-i ~8
r
X-T
-'132
1'1
16
3
"
lID
I 21
I 12
PO
DOUT I TlA I IA
"51
I II
100000
I
"57
'IAO
II)
1'S'
"
1.'55
'". '21 '2 "
... ,~ '5 I"s~
I ..
'IAI7I 17
.1'5'
'IAI9I I,
11152
12. ' "
'12
,,'
'"
,,,
PI ...' 21 "'5'
.... 5' 'J ,AlSO
,. , I,
,,8 '"
'12
, ...~, 25
II
, ..
"8 '2
"
".,.1
I 12
p'..,'1 .,
1"~7
I I
Pltz,')1
JR''''
,,,
.. 1,.1
12
'In
I 17 I
13
lIP
I 17
,~
IIQ
I ,6 ' "
Ir;;-T.,
'5 I"
II
I 2
I" 12 I'
15
II
12
I.'~'
27 ,.,U
c
33 I"~s
"1)'1 10
,.,~~
, ... " "
I"~J
A
AIT :;
.!J.t~
u:n.
~R/W2
2"~8I'CHZ
I 22 I '
'". ,,' '2 "
14
PC
I,
'It
, tJ
1
Hf-+-+-.....JU:
4
"
'Zl I 2
,.. '2. '2 "
5 ::
t1+H-i--I-..J1!!I
,
I P' I ..
'.1'22111112
1
(SEE SHEET 1)-
1.& I V,
.!!.t I!JGI
T 1> MEM r
.&
B
TPA
~S£IE~
I'D
oeUT
.~O...ii1itI
4,5 @-:r.;';;\..CEN2
2.4,5®-
1IiIl!l!lIlI-! ! ! i!~!l Il!lIl1l1li!1512X-T
!!IAZCD AI,Zp..!L
":"
1128
I:: .!.2!!.22. I4:'~ 101023 &.
25&
1 18
00
\J)
~
A
W
W
W
o
o
I
tllil "'Ml'Vltn U~
, . . . . . . , . . . to
1&111::2111•
):>
.1":
DETAILED LOGIC DIAGRAM
MEMORY(BIT 1+16)
~
r:E~:]
.
.
~
00
\.0
'"
\N
\N
\N
ift'II&&
1111,
o
o
.
AOOOO
iiOii'
5
-
~
0-3
II
'-'ST
DIFFERENT VALUES IN THE
lAND 600Nsec(EOUIPMENT SA- 201A)
27DPF
4 C 55
RI61
\lOOO- UOl7
U100-U1I7
U2OO-U217
U300-U317
~
ill
1~7+
",y'
~53.
L.A'
.
cr.!4-.
#
,./
V
...~
0
PIN
NO.
10
Veel
10
V••
11
V..
II
v••
10
uNLESS
Be
,
8-1
TABLE IlN SHEET 3
.,
BB
-'J
~//
8-Z
A-3
i
.t.
&
""', '1
APP
~
II ........"5 .,,, '6,"02-
V55
8-2
C-3
UII -U23
UOOO-UOI7
UIOO -U1I7
U200-U217
U300-U317
C -I
.oS
&
&
.6\
II~T"c~~t>
It-
F~l~!t~'MP~.~~
THE
8
V'
~
\)1i .. ET£t>
(%'*&.0-3 .
8-2
SHEET CtlMPIl~ 1"'''' 89876300
(900WSI
L.·'-/
8
".N'2'
8-3
9OON"C(EQUIPME1iI'k~
8-3
AH
AM
&"imrE~TIl
/I
1-3
8-2
c ••
DEClO
AY "' ... ~ ut.s,*,,;t
CI("O l!4N0/0 INST'-'.INCoRR ..c.r
"W ""A5 C_aA...c"T
At ..,.. 5 .,~ 15"'02-
8-1
~·""'liI'TES'
C-3
AD
AL
~
0-3
Z
AG
'""",
8-2
:;
011 cti .78 • • • " ••~ " .. 7 #IIIQ .,.""
"'I".t.J'I.
C,rt •
. ,.....
fW'"".,rao rq , .•. our_ur
C-2
&
A-4
A-4
0-4
AA
AC
8-4
A-4
10 7
C-I
C-I
OIIFT DATE C_
DESCRIPTION
02 CK 364 REDRAWN PER CDC STD.
03 CK498 C 105 WAS IOpl'.35V
04 CK 621 IRa WAsno 1ltI1I•.
& 05 CllIoT!
0," CI(77C
0-3
8-4
8M
A
8
C-4
B-1
..
itA
0-2
J
8-4
PI
A II A II
a A A II
L,IIIcATlIIN
K
U
I
3
8
S
,l.r~"
SHEET
0
T
/'"
B
0-1
0
_.
7
6
0-4
~
I---
5
A
ECO
5 6 7 8 REv
0 0,01 jo2PZ
III I
SHEET LeCATI"N
P
!'-.:~
P2~
SHEET REFERENCE
'FF
2 3 4
()~"*.RWtSl
SPECIFEO
OIMEloiSION ARE IN INCHES
TOI..ERANC£S
3 PLACE
±
Z PLACE
±
ANGLES
±
00 NOT SCALE DRAWING
MA::------
FI::-------A
ElBIT COMPUTERS LTD
• su.,", •• , 'f
11'llllil'!,!
OWN
CHKO
FIRST USED ON TITLE
BAZOI-A
BA201-B
IONA
k"..
MFG
., ,', ,\.
,,()
APPR
HAIM
f.
a:;?
4A
~
DIAGRAM
J
MEMORY
DEC.
I A.b, •.
ENGR ISH'YfT
DETAILED LOGIC
'.0&-::'.11. ,
rODE IOENT
'1-'
I
Ic I
I,
.r:/.JJ"
SCALE
I
..
DRAWING NO
89615502
ISHEET I
OF8
4:
[
.CMI
&
0'
CR
59
\oN
\oN
\oN
o
o
.
~
i
'+
IREVI
~
I
AlVISION IlECORO
O"-CRI""O~ ____ .-lOI!FTJ.9~TJ JCHKOI j,j.p
ECO
I
CR
6~
.
I[
o
»
-
J~
CR
CR 74
70
l .- . .
CR
44
CR77
:.
~I
a.4~
AQ
AO
Clt79
'C1I1l!
1 1PC!I RIWI
5 A.I
iil4
•
II
• CR4I
VSS
~
~
•
~D'"
u.
2
~~I
2
,..!!,IAZCD
Ie
1£&
AI
r
1
14
512
~
X_¥II I
~
1-1
~
M
CR
51
CRee
........-
iil2 Aoooo
7
:
•
CR
Ie ~
--9!!!.
l RIW2_
81
I-
84
iil2 ~
.. A102ii1
U~
CR
CR
81
15
I>MEIII
CR8i!I
~
2 121
111'\.
CEIiII
AI
_·1
rr
•....
r-r ..2116
A102ii1
]
1£
.A.
tiD
IE
...
AS4
-
CR
CR
!112
96
CR
55
CR95
R
CR56
R9I
CR99
1
CR96
RI59
.1:IiE_ _ _
,
I-
D.UTO
i!Ii!ID
2...
CRI I
CR97
~
I'
~
..
REv
DETAILED LOGIC DIAGRAM
MEMORY ( BIT 0 )
V'I
I
\oN
\oN
~
~
1
MEMORY MODULE
(drawing 89615502)
Power supply considerations.
Setween VSS and VSS the memory unit presents the equivalent of a
silicon junction diode, which is reverse biased under normal
operating conditions.
During power supply turn on, VSS should
rise at least as fast as VSS and during operation VSS should
not fall below VSS. To insure proper VSS regulation and to
guarantee these turn-on characteristics, VSS is generated by
regulating VSS at 3-4V below VSS. Secause the memory unit draws
very little current from VSS protective series resistance used;
VSS is adequately bypassed to VSS at the unit, and level
shifters connected to VSS are connected to the power supply side
of the series resistance.
89633300 A
5-31
-
..
I
SHEfT IllEl'fMNC(
fFF
V1
I
\AI
tiff
N
SHEfT
1IJ.f'~.I'I!i~
I
1,.~T1:~'"
~
3
4
I
II
0-1
B
C-4
0-1
Q
C-4
0-2
E
C-4
0-1
BE
I'
C-4
C-2
BF
C-4
REFERENCE LETTER
2
C-I
BG
C-I
BH
L
1-4
C-I
AJ
M
1-4
C-I
BK
N
1-4
C-2
BL
P
1-4
B-1
BM
Q
1-4
B-1
BN
R
A-4
B-1
BP
&.
&.
C-3
&.
&.
&.
&.
C-2
B-2
BO
BW
U
&-4
B-1
BX
&.
&.
B-2
1-2
1-2
A-2
BY
B-2
1-2
&-2
&-3
BZ
x
1)-4
1)-4
1-2
&
,t,
Z
1)-4
1)-4
0-4
0-3
11-4
0-4
0-4
0-3
AB
C-4
SHEET ct!MP!lNENT
C-3
C-4
1-3
8
C52.C53.
C54 C 55
AE
C-4
C-4
C-4
1-3
4
AI'
B-4
RI61
UOOO- UOl7
U100-U1I7
U200-U217
U300-U317
1-3
1-3
AH
B-4
1-4
1-4
&-3
AJ
B-4
1-4
1-4
1-3
AK
A-4
2
.&.
&
&-3
lA-4
&-4
1-3
A-4
&-4
&-3
&-3
AM
A-4
AN
A-4
A-4
A-4
AP
0-4
8-4
A-4
£
AO
C-4 .A- 4
A-4
C- 3
AR
B-4
A-4
A-4
C-3
AS
8-4
A-4
A-4
C-3
AT
A-4
A-4
A-4
C- 3
AU
A-4
A-4
A-4
1-3
AV
A-4
.A-4
A-4
1-3
~
AW
.A-4
.A-4
A-4
1-3
AX
A-4
A-4
A-4
1-3
AY
A-4
.A-4
A -4
A-3
o
o
SA
0-3
A-3
/
A-3
/
C -I
\HI
.&:.
0-3
II(:
&.
I)-~
/
INTEGRATED
CIRCUITS
UI- UIO
w,,"
eft(
978
. . . c":;' R::' "'."C
~~:I ~.~~
RI!Lfl'Sfb
e
v••
C~
flU
1'("." A.1,0
cLIIH -,.
WA, ,~...,
,..• 4»8 cIS
'P'. "N.
SM .8
VSs
.0,- N"I'4-,. ('It...
....... ·fVlr ~
#Ms
Tq , .•. 04l7P"r
_"""'11
CAPIICl'IIRS SETWlU
Vee .£_f ~"'''F
&.
II..L.
"-
'·'.76
"".
D
J~~ fl.C.o.
l'
E
CK TO MATCH MFD. PWA'S:·
J~30 SH 1 , NOTE 2 :
900NS: 89876600 REPLACES 89876300
600NS: 89876300 REPLACES 89876600
ELEMENL •
IDENTIFIER
SJ.\5.
11.
~
IIjIi
~
~
39 PI'
27.4
1103
OHMS!~
1103-1
ARE
PENDING
I
"
VOLTAGE
APPLIED
Vees
Veel
V••
~
PIN
NO.
'* ~
I"t17
V..
II
VA
10
UNlESS QTHERWlSl sPECIFEO
OIM[JiSION ARE IN INCHES
TOlERANC£S
HalT COMPUTERS LTD
I
FIRST USEO ON TITLE
'IU'SIDI'.'Of~GI"~
DETAILED LOGIC
0 8
li'I:lliI'II'M~ BA2.0Ioo~~ 8 (SOOHS) MEMORY
±
.t
~ !~ e, !?:J:.
g 8
DEC.
'"~ .... Ie ...c 00 NOT SCALE DRAWING OWN A.IONA, k
J
GM~
'"iO :::
i!
rODE ID~T
c
HYtT'1-1
~
~
. .
..
. ..
5 PLACE
2 PLACE
ANGLES
l
CI)
~
CHKD
c
II
[)c:(..Il..
EHGR
CI)
>-
DIAGRAM
~
oJ
CI)
CI)
'lI
&-.1+.
,#,'+
It"'" ,,",A$ CoitA.EC,
lit
~" 15302-
/I ,""2,
B-1
~
ALL UNMARKED RESISTIIIRS ARE 0.25 WATT 5%.
~
lh
A
B-2
..,.
ALL UNMllRKED DIIIIDES ARE IN4151
UII -U23
UOOO-UOI7
UIOO -U1I7
U200-U217
U300-U317
0-3
-a,
C C.K S.Ma : VA L\JE OF
13O'" <:93 CoRR.e:CTE
B-2
56.20HMS!2%
+-
'f-
"' .......,,'50 lSI. 15502-
(2DIII 0-31.
B-2
Ino;""a~~
...., 7
Ar
l>~L£"-"1>
DI'I"'~CT.O
B-3
270 PI'
Col
C,.D
IONA DEClO
AY "'''I~ 191.5'402
CK'SO R"'O(.IM$Tj\.IMca~.c.r
B··I
122~IA;':
DOFT DATE
CK77C l)£TAC.U'lI LIST
all
THE FIlLLf/lWING CIIMPIINENTS HAVE DIFFERENT VALUES IN THE
C-4
1-4
. 01.
9OON ... IEQUIPMENT SA 201-BIAND 600NHCIEOUIPMENT SA- 20IAI
C-4
CIc; ('75
p7
B-3
/
C-4
AL
""''''
I!I 0$
Till TABLE \liN SHEET 3
C-4
DESCRIPTION
CK 364 REDRAWN PER CDC STD.
CK498 C lOS WAS IO}lF.35V
CK 621 R 3 WAS 350 "HMS.
C-2
B-2
C-3
1-4
02
·03
C-I
C-3
NIIITES'
REFER
0-3
A&
AG
A AA
0-3
0-4
~
0-3
&.
&.
B-1
~
8
C-3
&-4
V.
7
6
&
A-4
I,
A
lh
lh
&.
S
_.
. i~
ECO
A A 1\ A A II III
0-2
T
W
5
REVISION RECORD
5 6 7 8 REV
!l4
~CATI~
4
3
BD
1-4
AD
I
SHEET
1111'1' SHEET
K
AC
\AI
\AI
\AI
8
0-4
Y
00
7
A
2 34
-'
/
SMUT L'<:ATItIN
J
f'T'I
•
SHEET REVISION STATUS
-
FI:--------
MFG
t'1',
APPR
HAl., T.
QA
~
...
)
I '.'
w
I
I,
::/.7J'"
SCALE
I
DRAWfNG NO
89615502
SHEET
...
I
OF8
MEMORY MODULE
(drawing 89615502)
PROTECTION AGAINST CATASTROPHIC FAILURE
Capacitive coupling circuit
The MOS-level signal, after the level shifter, is fed to the precharge
1 ine on all memory modules.
This 1 ine includes a capacitive coupl ing
circuit, which protects the memory chips from catastrophic damage.
Power dissipation in the chip is a function of precharge duty cycle.
If a precharge driver fails or remains active (low output) for too
long, the memory units may overheat and be destroyed.
However, with
the capacitive coupling circuit, the precharge is pulled up even if
the level shifter output continues to remain low.
The capacitive
coupling circuit does not slow down the precharge signal in operation.
A series termination resistor (22 ohm) connects the MOS-level signals
to the memory chips, after the capacitive co~pling circuit.
The
signals run down the l8-bit kiloword bus, connecting to each memory
chip.
The address lines branch into 4 groups, each running down a
separate l8-bit kiloword line.
A clamping diode is connected at
the end of each line to VSS to prevent the signal from exceeding VSS.
There is one diode for each kiloword line, that is, a total of 4 diodes
are located on the address lines.
For bit 17 (protect bit), the one physically closest to the level
shifters, the precharge signal is connected directly after the
capacitive coupling device without series termination.
This
decreases precharge overlap time due to line reflections, and
thereby decreases data output time for bit 17.
5-30
89633300. 03
l/
/
MEMORY MODULE
Power su
(drawing 89615502)
con side ra t ion
/
Between VSS and VBB the me {y unit presents the ~uivalent of a
sil icon junction diode, whicH, is reverse biased nder normal
\
operating conditions. During~ower supply tur on, VBB should
rise at least as fast as VSS an~ during oper ion VBB should
not fall below VSS. To insure p\oper VBB r gulation and to
guarantee these turn-on character\s.t. i Ci:'BB is generated by
regulating VSS at 3-4Vbelow VBB • \Becau e the memory unit draws
very little current from VBB protec iv series resistance used;
VBB is adequately bypassed to VSS at ~he unit, and level
shifters connected to VBB are
d to the power supply side
of the series resistance.
89633300 A
5-31
MEMORY MODULE
(drawing 89615502, sheets 3,4)
Sense Amplifiers
The data output (terminal 14) of the memory units appears on an open collector.
The output pins of corresponding bits of the four kilowords on the module are
wire-ORed to form the 18 output lines of the Memory Module.
Each wired-OR is
taken through a 330 ohm resistor to ground which converts the current source
output of the memory unit to a voltage level.
This voltage level is fed to a
differential sense amplifier (receiver unit l62C) whose output is the D0UT line.
The other input of the receiver is connected to a reference voltage.
This
reference voltage is determined by the two resistors acting as a divider on
V
using Q92.
The value of the reference voltage (VREF) differs in the
cc
high speed and low speed units:
BA20I-A:
BA201-B:
VREF
VREF
= 110 mV
=
50 mV
The data output is activated by the cell enable (Cenable) signal to the memory
unit.
The output of the sense amplifier is not enabled unless the STROBE is low
(during clocks 5 - 10) and the module was selected (HOi low).
When the
sense amplifier is not enabled, its output is high.
Pull-up resistors
located on the Memory Control assembly pull the D0UT lines to Vee
5-28
89633300 A
MEMORY MODULE
(drawing 89615502, sheets 3,4)
VCC
STRt6BE ----.;;6...62
RCVR
RI61
162C
VREF
I
RI60
15.4
~4~-DfJUT
MDX--.....
--~2%
TERMINAL
OF MEMORY
UNITS
(DATA OUTPUT)
Equipment
Note:
BA201-B
BA201-A
R161
56.2 ohms ± 2%
27.4 ohms ±2%
VREF
50 mV
110 mV
Data-Out Sense Amplifier Circuit Diagram
89633300 A
5-29
MEMORY MODULE
(Drawing 89615502, sheet 8)
Low Power Data Retention
Between refresh cycle bursts in the Low Power Data Retention (LPDR) made
during a power failure, none of the TTL logic circuits receive power.
This circuit ensures that the Precharge and Cenable signals do not activate
as the Vcc is switched "on".
It achieves this by keeping the enabling
inputs of the Precharge output gates low (at U9/6).
VCC2
33,F
l·:---T
VCC2
68nF
1.5K
LPDR
CIRCUIT
OUTPUT
U9/6
IOnF
1"'
f
T
IOnF
Switched Supply (VCCS ) and LPDR Circuit
The circuit senses that the switched logic supply (V ees ) dropped, and,
with a short delay, holds U9/6 low; when Vees rises, the circuit releases
U9/6, after a short delay.
The attack time of the circuit (the time
allowed between Vces dropping and U9/6 being held low) is 10 milliseconds.
The release time is determined by the Disable signal: Disable will not
go active (1 ow) for 1.6 milliseconds after MPwr is active (that is Vees
is active, thus the circuit has 1.6 milliseconds before it must release
U9/6.
5-26
89633300 A
MEMORY MODULE
(drawing 89615502, sheet 8, cont'd)
The main logic supply (VCC ) may fail during normal operation.
This will not affect memory operation If the optional back-up source,
battery equipment GD611 is installed. In this case the computer
switches to Low-Power Data Retention (LPDR) mode and to conserve
power the following TTL circuits are connected to the switched logic
supply (V CCS ):
-
Column address (A5 - A9)
Data-in level shifters
Data-out sense amplifiers
During intercycle refresh bursts, all circuits not directly involved
are switched off by VCCS. The outputs level of the sh ifter.s to
precharge, Cenable and R/W continue, however, to rema.ili high.
Address Level Shifter.s
To avoid long transmission paths on the memory module assembly five
of the addresses, located far from the connector, have two TTL
inverters instead of the usual one.
89633300 A
5-27
MEMORY MODULE
89615502, sheet 7)
!
f
/
.'
Data-In Level
!
The level shifters for the data input to
\
~ch
"
memory unit is an open collector
inverter with a 1 Kiloh"\pull-u p resistor to VSS.
The DATA IN (DIN) lines are
normally low.
When a D~TA-IN line beobmes active (high) during a write cycle,
\
the information on it is i
diately valid.
The outputs of the data-in level
sh i fters have a
a comparatively slow rise time, making them
suitable
XIV
Data To
Data In 0 - - - - 1 200 . . - - - _ -.....~-----4,...--O Memory Units
(Terminal 12)
Data-in Level Shifter and Clamp
5-24
89633300
A
MEMORY MODULE
(drawing 89615502, sheets 5,8)
The Overlap Circuit (Cenable - Precharge Delay)
One overlap delay circuit is in the precharge line of each kiloword unit
on the Memory Module.
It regulates the overlap timing tOVL and tOVH in
the memory units (see Table 4-2 and the Detailed Operation of the Memory
Unit), and consists of a diode switching network controlling an RC
delay circuit.
The circuit is snown below.
In normal operation Cenable at the output of a
level shifter is high, blocking diode 01 and so allowing a voltage of about
2 volts to develop on the delay network (Cl, R2). This voltage enables the
precharge output gate.
When the Cenable line is activated (gone low), diode 01 conducts and
blocking diodes 02, D3 isolate the delay circuii.
The voltage to the
precharge unit decays with the time constant of the delay circuit so
end i ng the precha rge s i g na 1•
vees
RI
100
e.nabll
(HI8H-
-lev,
To Precltar,.
LOW-O.7V)
Output
lat.
el
Overlap (Cenable-Precharge Delay) Circuit:
89633300 A
Circuit Diagram
5-25
MEMORY MODULE
(drawing 89615502, sheet 5)
Level Shifters: TTL to MOS
TTL logic levels are 0.7 volts (low) and 2.0 volts (high). MOS levels are
approximately zero volts to VSS (16 volts).
A level shifter is needed to
match the two kinds of logic circuits. The following signals use identical
level shifters:
Precharge,
Read/Write (R/W) and Address
These level shifters are common emitter push-pull inverting amplifiers, using
four transistors.
They accept TTL input and provide an output to drive MOS
circuitry, that is, they drive a 300 pf load in 45 nanoseconds. Two capacitors are used to speed up the operation. The use of -5V and +28V power sup-
I
pl ies improves delay and rise-fall times. See page 4-34.
The Cenable 0, 1, 2, 3 signals use the above type of level shifter, but with
two components added: a 470-ohm resistor and a type lN4151 diode. The resistor
and diode are connected for the Cenable level shifters only. To indicate this,
they are drawn in dashed lines in the circuit diagram below.
In logic drawing 89615502 sheet 5, the 470-ohm resistor is marked RE and the
type lN4151 diode is marked CRB.
Vss
+28V
IN 4151
470
12K
TTL
INPUT
470
,---
i
M.O.S LEVEL
"--~OUTPUT
1N4151 :
f-
I1_ _ -
I
-5V
®
TTL to MaS Logic Level Shifter Circuit Diagram
89633300
F
5-23
MEMORY MODULE
(drawing 89615502, sheet 7)
Data-In Level Shifters
The level shifters for the data input to each memory unit is an open collector
inverter with a I Kilohm pull-up resistor to VSS.
normally low.
The DATA IN (DIN) lines are
When a DATA-IN line becomes active (high) during a write cycle,
the information on it is immediately val ide
The outputs of the data-in level
shifters have a fast fall time, but a comparatively slow rise time, making them
suitable for this signal polarity.
Vss
IK
x,/y
Data In 0 - - - - 1 200
To
...----411--.....- -.....- - 0 Data
Memory Urnts
.
(Terminal 12)
I
Data-In Level Shifter and Clamp
5-24
89633300
F
MEMORY MODULE
The Memory Module circuits are accommodated on a single 50-PAK printed
wiring board.
The logic circuit diagrams are given in drawing number
89615502, sheets 1-8.
The equipments, BA201-A and BA201-B are both designated Memory Modules. The
difference in function between the two equipments is their speed of operation
expressed in terms of the memory read/write cycle time, as follows:
Memory Module
Equipment
Cycle Time
BA201-A
600 nsec
BA201-B
900 nsec
Accommodated in
Equipment
I
ABla8, BT148
AB107, BT148
The memory module,as pa-rt of the memory system is described in Section 4
of this manual.
The principles of operation and circuit configuration of the two equipments
are identical.
The component memory units they util ize are similar and
differ only in their speed of operation (refer to Section 4'of this manual
for detailed operation and timing).
Changes in the values of other components
between the two equipments are noted on sheet 1 of drawing 89615502.
The memory module block diagram is described in Section 4 of this manual.
Detailed circuit diagrams are given here.
The circuits are repetitive and
for bits 1 through 16 they are identical.
Only one circuit diagram is given
therefore and it is supplemented by tables defining each component.
The level shifters and other circuits which make up the memory module are
described in the following.
The memory unit is described in detail in
Section 4. Its terminal functions are summarized in the following diagram.
89633300 F
5-21
AO
ROW
SELECTOR
SI GNALS
AI
A2
A3
A4
A5
COLUMN
SELECTOR
SIGNALS
A6
A7
A8
A9
RIW
PRECHARGE (PCH)
CENAB LE (CE)
3
512 X.Y
4
256
2 128
I
64
15
32
8
16
7
8
9
4
13 2
s
AOOOC
A 1023
I
181\
51\
161\
~
....a
G2
III
t>MEM
DATA
IN
I 2 {A2CD
AI.2:,'4
DATA OUT
SUPPLIES
SUPPLY
VSS
VOLTAGE
+ I9.7V(BA20I-A)
+16.7V (BA201-B)
TERMINAL
17
17
VBB
VSS +3V
10
VOD
GROUND
II
Memory Unit External Connectors
5-22
89633300 F
MEMORY SYSTEM
The memory system consists of the printed wiring assemblies (PWA's) listed
in the following table:
Designation
Slot Location
Memory Module
29 th rough 36
Memory Address
28
Remarks
Equipment BA201-A or BA201-B
)
) Memory Controller System PWA's
Memory Control
27
)
Notes:
I
1.
The slot allocation is identical in equipments AB107/AB108, BT148.
2.
The Memory Controller system in the expansion enclosure is equipment
BUI20-A.
It is similar to the Memory Controller used in equipments
ABI07/AB108.
The memory timing is shown in figure 4-6 and in the timing diagram associated with sheet of the Memory Control assembly.
89633300 F
5-19/ 5-20
"Pages 5-9 to 5-18 are unassigned."
89633300
F
I
5-91 5-18
j?r
I I
DSA BUS
ex>
\.D
MEMORY
0'
W
W
W
CONTROLLER
DSA BUS
11
o
o
."
I
I
EIGHT
MEMORY
MODULES
A/Q BUS
/Q BUS
DSA BUS
~BUS
I
TIl
DSA BUS
1m
I
1",
'I'
A/Q BUS
I
!
I
OPEN
OPEN
OPEN
,
36 35 34 33 32 31 30 29 28 27 26 25
2~
23 22 21 20 19 18 17 16 15 14 13 12 II 10 9 8 7 6
5 4 3 2
I
I
I
L..-
I
NOTES 1.
The Memory Control assembly and the Memory Address assembly together form the Memory
Controller, equipment number BUI20-A.
defi~ition
2.
See section I for
3.
Slot 25 is provided with an additional connection to logic ground at 25P1A03.
of equipments.
Slot 26 is provided with an additional connection to logic ground at 26p2B06.
\J"I
I
-....J
Card Placement Slot Assignment - Expansion Enclosure
DIAGRAM REVISION CORRELATION SHEET
The following is a numerical list of the logic diagrams (prefix LD) and the
wiring diagrams (prefix WD) included in section 5, with the revision status
for revision F of this manual. See the table of contents.
NUMBER-REVISION
WD 89601601 - A
LD 89614300 - A
fLD 89614900 - A
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
WD
WD
WD
LD
I
5-8
89615200
89615502
89616400
89616400
89616400
89616400
89617000
89618800
-
89619100 89619700 89640500 89640501 89640502 89640800 -
A
E
J
H
G
F
A
B
C
A
B
A
A
D
89657700 - B
89762200
89911800
89942600
89982800
-
05
B
A
A
NAME
Power Supply Wiring
Arithmetic Logic Unit (ALU)
Decoder
Memory Address
Memory
TTY Con t ro 11 e r
TTY Cont ro 11 er
TTY Cont ro 11er
TTY Con t ro 11 e r
Timing
Console Interface
Memory Control
Input/Output (I/O) Interface
Programmer's Console
Programmer's Console
Programmer's Console
LP Card - Power Supply
HP Control Unit
Power Supply Input-Output Wiring
Power Supply Wiring
Power Supply Input-Output Wiring
Anti-Bounce Circuit
89633300 F
Test Points
The test point symbol on the logic diagram
shows the connections of a test point on
the printed wiring board (PWB). The number
adjacent to the symbol refers to the test
point position on the PWB at the edge
opposite the connectors. Only test point
number one is labeled on the edge of the
PWB, the other test points are numbered
sequentially.
CONNECTING
LINES
Connect ing and Non-Connect i ng Lines
Lines eonnected to a common point or at a
junttion point are shown in the upper part
of this illustration. No more than three
lines are normally connected to a common
point in the diagrams.
NON -
CONNECTING
LINES
Lines crossing but not connected are shown
in the lower part of this illustration.
Connectors
All PWB connectors are sockets (female) and are shown as such. The name of the
signal is placed in the open end of the connector symbol (shown below), using
the full name of the signal or the common abbreviation applicable to logic
diagrams. The connector number, pin row and pin numbers are located above the
line extending from the connector symbol. Refer to Input/Output specification
manual publication number 89673100 for an explanation of the mechanical
location of connector pins.
, . - - - - - - - - - - - - - - - SIGNAL NAME
CONNECTOR NUMBER
PIN ROW
, . . . . - - - - - - - - PIN NUMBER
r------------r----------
READ
89633300 A
»)---------5-5
V1
I
'"
m
" I,
AO ....
TIMINI
~
Ilo' INTERFACE
MEMORY CONTROL
MEMORY ADDRESS i
l
::s
n
0
.e
C
n
.,AI
Q.
"0
I I I I' I I I
EIIHT
MEMORY
MODULES
AI
n
CD
., i::s
r1'
I
CONSOLE INTERFACE
I 1.1 II I I I II I I I I I
CENTRAL
PROCESSING
UNIT
CD
ITI
r1'
0
,...-
..,
C
»
III
CD
III
::s
n
III
en
S•t • : ;;-c Ic i
0
III
ai
5::s
r1'
36
00
'"
\At
\At
\At
0
·0
»
•
34 33 32 31 30 29 28 27 ~ 25 24 23 22 21 20
DSAIUS
AGIUS
n
'I I r
_ZI
PHAIE
CARTR IDIE
DISK
. . .ETIC ENCOD'TAPE
'ING
DRIVE
CONTROLLER TRANSPORT fORIMrI~
TER
~II
ca
::s
\D
11
TTY CONTROLLER
'1
•
0
~
=-
0
n
.z
,
n
!!
=• Ir0
III
~
~
~
~
II 17 II Ie 14 13 12 II let
•
I
7 I e 4 3 2 I
NOTES
The Memory Control assembly and ,the Memory Address assembly together form the Memory
1.
Controller. This Is similar to equipment BUI20-A in the Expansion Enclosure.
See Section I for definition of equipments.
2.
~y
TO LOGIC SYMBOLS
Publication 89723700 (Key to Logic Symbols) or equivalent, lists the symbols
used in the logic diagrams in this manual and gives a short description of the
functions they represent.
The symbols
confo~m ~enerally
to Control Data usage
(Microcircuit Handbook, publication number 15006100), using the polarity logic
convention.
The following paragraphs describe the signal flow conventions used.
SIGNAL FLOW
Input signals are drawn coming from the left or above;
drawn going to the right or down.
The signal lines are sometimes interrupted to
components and to avoid long lines.
all~1
output signals are·
logical grouping of
At each such. interruption one of th.e
following indicators is used:
On-Sheet Continuation Reference Symbo.1s
These symbols when used with the logic
symbols in the following diagrams indicate
that a connection exists betlt/een two points
on a sheet.
The arrows attached to each
circle point from signal origin to signal
destination.
The letters, C, H, I, 0
and P are not used inside the circles,
since they bear special significance on
logic diagrams.
89633300
A
5-3
( ON
SHEET
Off-Sheet Continuation Reference Symbols
2 )
These symbols when used with the logic
symbols in the following diagrams
indicate two sheets in a series of
related drawings. These symbols point
from output to direction of input as
shown in the illustration. The number(s)
--------.@3.6
(ON
23
SHEET
6)
next to each hexagon indicate the
~~-----------
sheet(s) that the signal is continued
from or on. For instance, the numbers
3.6 refer to sheets 3 and 6, while 2.3
refers to sheets 2 and 3. It should be
noted that the referenced sheet number(s)
is always placed opposite the line
extending from the hexagon.
r--'
SHEET
OFF-SHEEl SIGNAL',
REFERENCE
l
2
3 4
LETTER
A
BIT3 O-r
I
B
BIT2
C-r
C
BITl
B-r
0
BITO A-r
E
5
;
,,
PTAOO 0-2 0-2
The interconnections are listed in an
Off-Sheet Reference table in the logic
diagrams. This table gives the location
of the off-sheet reference on each sheet
and generally indicates the signal on
which the signal originates (~). The
signal name at the interconnection is
~lso generally given in the table when
avai lable.
~
F
QTAOO 0-2 0-1
G
KTAOO 0-2 0-2
- -----
MTAOO A-2 D-2
._--
5-4
'-_.-..................
...
89633300 A
SECTION 5
INTRODUCTION
This section carries the explanation of the detailed logic and circuit diagrams
r~lating to equipments AB107/AB108 and BT148.
These equipments are described
in Section 1 of this manual; their theory of operation is given in Section 4.
The explanation is grouped in functional units, as follows:
Functional Group
Circuit/Board
Memory System
'}
5-20
Memory Module (equipment
BA201-A or BA201-B)
Memory Controller
Memory Address
Memory Control
Central Processing
Unit (CPU)
Programmer1s Console
Arithmetic and Control Unit (ALU)
Decoder
Timing
Input/Output (I/O) Interface
Console Interface
TTY Contro 11 er
Power Input Circuit
Power Supply Unit
High Power (HP) and Control
Low Power (LP) Board
89633300 F
Page
5-21
5-45
5-81
5-141
5-143
5-167
5-211
5-241
5-291
5-337
5-373
5-424
5-427
5-436
5-461
5-1
I
Notes:
1.
All units, except the Power Supply assembly and Programmer1s Console,
are mounted in slots in the main body of the enclosure (refer to card
placement slot assignment, pages 5-6, 5-7). The order of the explanation follows the reverse order of slot assignments.
2.
I
I
The Memory Controller, (consisting of the Memory Address and Memory
Control boards) as equipment BU120-A is installed in the BTl48 enclosure.
3.
The calibration of the Power Supply unit is different in the AB107 and
the ABI08 equipments. The following table gives a summary:
EQUIPMENT
I
I
ABI07 and BT148 connected to it
AB108 and BT148 connected to it
CALIBRATION
VSS
VSS
= +16.7
= +19.7
V
V
This information is given in other parts of the manual as required. See
the Diagnostics and Margin Tests on page 6-7.
The diagrams, together with their latest revision status, are listed in
the Revision Correlation Sheet. The diagrams themselves are not bound in
this manual, but are packaged separately.
An explanation of symbols used in the diagrams is given in the Key to
Logic Symbols and Signal Flow.
5-2
89633300 F
SECTION
DIAGRAMS
5
...
/lfFF - SHEET REFERENCE
00
I.D
0"
W
W
W
"FF SHEET
REFERENCE LETTE R
A
8
o
o
0
SHEET
LeCATllJN
4
2
3
A-I
A-3
8 -I
A -2
C-4
0-2
C">
BATTERY)
I
f1"" ~P.S
P22-A
/
P22-B
r
P22-c
eN/tiFF
GRQJUND
.,.,...-;
S30
POWER
®H
RII2
IK
......
,YCC
P21 -19
YCC
NilTES
>P2U-II
YCC
I C8-CI6
C18-C20
,
OND
r
OND
, P20-11
OND
OND
GND
P21 -08
I
.;:V'1
"""
V'1
I
.;:-
-
.... P21 -13
,
OND
/
GNO
P20-13
)P21 -04
OND
OND
-I
, P20-34
, P20-37
OND
OND
-
I YCC
! CI7
33"F
10V
P20-27
OND
V'1
..... ........
OND
,
I CI-C7 ARE InF
2 ALL RESISTeRS ARE 0.25 WATT 5'"
3 RI- R17, R34+R50 AND R97 ... R103 ARE 180 ,sHMS
4 RI8 -R33, R1I4,R1I3 ARE 330 II)HMS
5 RSI - R74, R 76, R77, R79, RBI-R96,RI12 ARE IK 0HMS
6 R104-R110 ARE 5609lHMS
7 R 75 AND Rill ARE 33K 0HMS.
B C23, C24 ARE 100 nF
9. C21, C22 ARE 0.47 MF
10 R7B, RBO ARE 5.6 K II) HMS
P21 "II
P21-24
P21 -2'
/
-...P21-1L
,,'<", ..... "", .. , .• ,
-
'I
:111111 ...... '",- o\RI 'rr. ,.rHl
~
00
I.D
DETAILED
o
N
o
LOGIC
DIAGRAM
PROGRAMMER'S CONSOLE
I.D
0"\
00
>«
~
c;.,. ... INO NO
---'.'
0"
Logic Diagram 89640500, Sheet 1, For Programmerls Console PWA PIN 89985400 and PWA PIN 89602069
I
PROGRAMMER'S CONSOLE (Sheet 2)
REGISTER SELECTORS
Function
The
the
has
The
seven pushbutton switches (Sl through S7) allow the selection of one of I
six internal registers or the Breakpoint (B) register. When a register
been selected, the corresponding front panel indicator lamp lights.
circuits are actuated on pressing the pushbutton.
Pushbutton Switches
PANEL DESIGNATION
CIRCUIT DESIGNATION
M
P
Y
X
A
Q
B
Sl
S2
S3
S4
S5
S6
S7
FUNCTION
Selects
Selects
Selects
Selects
Selects
Selects
Selects
register
register
register
register
register
register
register
M
P
Y
X
A
Q
B
Inputs
SIGNAL
ACTIVE
SEN
H
P4M
CLREG
H
H
89633300
F
FUNCTION
Active when computer stopped
(from TTY Controller)
Clock from Memory Address
LOCATION
SHEET SQUARE
2
D-2
2
3
B-2
A-4
5-147
PROGRAMMER'S CONSOLE (sheet 2, cont'd)
Output
I
SIGNAL
ACTIVE
CSM
CSP
CSY
CSX
CSA
CSQ
CS8
CLR8
8CK
CSCK
CLREG
PCL
L
L
5-148
FUNCTION
L
l
L
L
H
L
H
H
L
L
Register control signals
LOCATION
SHEET
SQUARE
2
2
2
2
2
2
2
Clears B Register
8 Register clock
Clears selected register
Clears all CPU timing
flip-flops when P Register
is cleared
2
2
2
2
2
8-1
8-1
8-1
8-1
C-l
C-l
0-1
A-I
A-I
8-1
C-l
C-1
89633300 F
PROGRAMMER'S CONSOLE
(sheet 2, cont'd)
Circuit Description
The switches are connected to the corresponding register control lines
through input network and gating circuits.
The input network also
ensures that only one register at a time may be selected.
The input network consists of a set-reset flip-flop in each selector
line; the set input of the fl ip-flop is taken from the switch through a
pull-up resistor and delay capacitor, the reset input from the inverted
output of
a~
the switches.
8-input NAND gate whose inputs are also taken directly from
When anyone switch is pressed, its I ine is grounded and
all the register select fl ip-flops are held reset, including the one
selected.
When the pushbutton switch is released, all fl ip-flops remain
reset except the one selected; this is set by the signal (ground)
conserved on the delay capacitor at its set input.
The indicator lamp drivers are actuated from the selector fl ip-flop output
and cause the indicator to light when the flip-flop corresponding to it
is set.
The register control signals are obtained by ANDing the output of the
corresponding selector fl ip-flop with the signal SEN in AND and NAND gates.
This prevents manual operation of the computer while it is running under
program control.
89633300
A
5-149
I
PROGRAMMER'S CONSOLE
(sheet 2. cant'd)
The other output signals are as follows:
Signal
Equation
Function/Remarks
CIRB
CSB'ClREG
Clears the B register
CLREG
Clears selected internal register
PCl
CSP'ClREG
Resets all CPU timing flip-flops when P register
is cleared
CSCK
SEN· P4M·C
Clocks data into one of the six internal registers.
It is produced when anyone of the data bit or
clear pushbutton switches is pressed [condition C
(U26,10)] and is active only when the computer is
stopped (condition SEN).
The frequency of the
clock is that of P4M.
P4M - clock signal from Memory Control; repetition
rate approximately 0.44~sec for AB108,
0.65~sec for ABI07.
BCK
5-150
P4M·CSB·C
Clocks the B register. It is produced when anyone
of the data bit or the clear pushbutton switches is
pressed (condition C) and has the frequency of P4M.
89633300
A
.,
It
oJ
00
\.0
vec
'"
W
W
W
o
o
o
SEN ') r •.•-....
"
1213MI
r., .... (
Ie;
R51
IW
vee ~ -.......
R97
. • I I "I
V1
•
V1
IICC
I.....
~I
DETAILED LOGIC 04AGItA,.
PROGRAMMER'S CONSOlE
..
PROGRAMMER'S CONSOLE
(sheet 3)
DATA BIT SELECTORS
Funct ion
The circuit allows data input to each of 16 bits of the computer from the
programmer's console when the computer is stopped. The indicators associated
with each b.it allow monitoring the contents of each bit location, both on
manual operation and when the computer is running under program control.
The clear pushbutton and its circuitry are included here.
Pushbutton Switches
PANEL DESIGNAT/Oti
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLEAR
CIRCUIT DESIGNATION
S23
S22
S20
S21
S19
SI8
S17
SI6
S15
S14
SI2
S13
SI 1
SIO
S9
S8
S24
FUNCTION
ASSOCIATED
SIGNAL
SET 00
SET 01
SET 02
Se t s da ta bit
in selected
regi sterj
corresponding
indicator lights
Clears selected
registers (sheet 2)
SET 03
SET 04
SET 05
SET 06
SET 07
SET 08
SET 09
SET 10
SET 11
SET 12
SET 13
SET 14
SET 15
CLREG
..
I
5-152
89633300 D
PROGRAMMER'S CONSOLE
Input
See switches and notes on output signals.
Outputs
SIGNAL
ACTIVE
CNS aL
thru
eNS lL
CNS OM
thru
eNS 1~
Notes:
a.
b.
FUNCTION
LOCATION
SHEET
SQUARE
L
Main data path
3
L
Main data path
3
3
!
!
A-2
8-2
C-2
0-2
these signals are bidirectional when computer is operated
from the front panel.
these signals are inputs when computer runs under program
control.
Circuit Description
Each pushbutton switch is connected through a pull-up resistor and an
inverter to an open collector NAND gate used as an inverter. The open
collector outputs drive the CNS lines corresponding to the switch pressed.
When the computer runs under program control the main data path signals
appear at the pins carrying the CNS signals.
The indicator lights corresponding to the bit locations are lit according
to the signal on the appropriate CNS line.
Two auxiliary signals are produced as follows (these are used on sheet 2):
Condition C:
CLREG:
89633300 0
active high when anyone of the pushbuttons in this
circuit is pressed.
Clear Register
5-153
1
O'l
I
vee
~
O'l
~
,
§l
w
W
eN
~
o
DETAIlED LOGIC DIAGRAM
PROGRAMMER'S CONSOLE
PROGRAMMER'S CONSOLE
CONTROL SWITCHES AND·· INDICATORS
SWITCHES AND OUTPUT SIGNALS
PANEL DESIGNATION
AUTOLOAD
MANUAL INTRPT.
STOP
MASTER CLEAR
GO
POWER
BREADPOINT STORE
BREAKPOINT
PARITY FAULT STOP
AUTO RESTART
PROGRAM PROTECTS
TEST MODE
32K
65K
ENTER
SWEEP
SELECTIVE SKIP
SELECTIVE STOP
INSTRUCTION
CYCLE
CIRCUIT
S25
S26
S27
S28
S29
530
SWITCH TYPE
Pushbutton (P)
Tog~l e
iT)
P
P
P
P
P
T
S31
T
S32
T
S33
T
S34
T
S35
S36
S37
T
T
T
S38
T
SIGNAL
OUTPUT
AUTOLOAD
M.1.
ST0P CS
MCCS
G0CSW
PWR. SW
AUT0RSW
PRTSW
TMSW
32KW
(32KW)
ENTER
SWEEP
SLK
INSTEP
ST0PCS
NOTE:
The signal PRGST is transmitted to the console interface board. It;s
used to stop the computer under certain conditions.
1. When the cyclic parity error signals CCPE is active and the PE stop
switch is set.
2. When the BEAC signal is active and the Breakpoint stop switth is set.
BEAC is active when the contents of the Breakpoint register equals the
CPU memory address.
89fi33300 n
5-155
I
PROGRAMMER'S CONSOLE (C9nt'd)
3. When the BEAC and 0PST signals are active and the Breakpoint store
switch is set.
4. When the SLSE signal is active and the selective stop switch is set.
INDICATOR LIGHTS AND INPUT SIGNALS
PANEL DESIGNATION
INTERPT ENABLED
PROG. PROTECT
OVERFLOW
PROTECT FAULT
PARITY FAULT
CPU INACTIVE
INSTRUCTION
INDIRECT ADR.
INDEX
OPERAND
POWER
-
CIRCUIT
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
DS9
OSlO
DS34*
-
-
INPUT SIGNAL
EINTB
PRT BIT
0VFL
PRFIND
PEIND
SEN
RNIB
ADDR
RIND
0PIND
PWRIND
CC'J5r
0PST
BEAC
SLSE
PWRSW
* Indicates dc power switch on.
I
5-156
89633300 0
.
f
vr:r
~
r
RBI
--'oN
00
\.0
P20-01
(j\
W
W
W
0
0
-;;~
P2114
1'21-17
STIJI'CS
INITIP
1''',INO) P20-21
I
DETAILED LOGIC DIAGRAM
V1
00
-
~"I
[:
vee
C')
IOAFTloAu-
5CR1P·10~
-=B'.
r------~--
fPST~
RIO
Df
.!Co
_
3
~
I"'
"~IO
IOB
CCPE~QI - - _ .
PROGRAMMER'S CONSOLE
Logic Diagram 89640500, Sheet 4, For Programmer's Console PWA PIN 89985400 and PWA PIN 89602069
.
~
00
\.0
0'
\oN
\oN
\oN
[
o
o
"T'I
I
:1
veC' " - - - ' .
:
I
I
I
.
~IREDIVCC
.---.
I~" I..
I..
r,'
1
CI -'T'
I
t"
Ie
~:: P=+ ~'~"'...
RT.
...
5...
IWHTI'iiT
t2
~
I
.(BLKIGND
~
IORYI
00 SWITCH
SIDE
IBRNI
M.I SWITCH
SIDE
U'NLns o,.......,t:
V1
I
V1
\.D
PIN 89987600
AND PWA
PIN 89987700
~rcl,.t:o
Ot."I.OtrI .... , ... IHOCS
~
USED WITH PWA
fO!,.lltAJilClS
DETAILED LOGIC DIAGRAM
ANTI-BOUNCE CIRCUIT
J.
...
I
•
51001
'"o
OFF SHEET
IREFEIIENCE
LETTER
A
8
D
ECO
__
I
IlEVISION RECORD
I_TIDAT&
DESC...TIOfI
I~
ItltftfliA 11~5591-- A I-I ~'Hr'~
OFF - SHEET REFERENCE
\11
I
STATusl .___
l.!l!l!L4 '''h.J'hJ _I
ClAU
LOCATION
SHEET
4
2
3
A-3
A-I
A-2
8-1
D-2
I C-4
1
f-
If
~'
I. CI-C7 ARE InF.
2. ALL RESISTORS ARE 0.25 WATT 5110.
3. RI- RI7, R34.R!IO AND R97+R103 ARE ISO ,eHMS
4. RIS-R33 ARE 330 "HMS.
a. R51-R96 ARE 1000 -..MS.
~
6. RI04 - R liD ARE l560 "HMS·
7. LO 89982800 REFERENCED ON $.H.4 IS LOGIC DIAGRAM
FOR ANTI- SOlNE CR:UT SlII-ASSEMBIY
S. LOGIC FIlS AIM 8964OaOO i£WJRKED TO
PIN 89987600 8Y FeD CKI43I
Yee)
~
I
T I
...oo
II
~+5Y
CS-CI6
CI8-C20
68I1F
GN~~----~--------1
CIT
33,.F
lOY
f-
....
FOR PWA
'-----@--..oo
<"..
....... 0"".........
II. . .IION Hi!: WltICMb
o
00
~
'"
W
W
W
o
o
"
.N..11
:i
~ ....... TO~:='
05"
..
..
j;;
0"\
l!f
co l!i
~
«
DO HOI" SCALf DIIAWING
ElIIT CllIIMEIIS IJlI
,_ •••••• I l . '
•
PIN 89987600
"WST USED 0011 nTLE
f
'.Mlgi._
DETAILED
107-A
LOGIC
DIAGRAM
IJ
PROGRAMMER'S CONSOLE
FOR PIN 89987600
10NA z.
CHKO HAIM 106£f'
EN.. b#KD "'EllS
MN
OWN
A_i
! ICoILI
r;B.
IIIIA.... NO
89640501
I_TI
111'4
co
\0
m
w
w
w
o
o
o
(J'1
I
......
m
......
DETAILED LOGIC DIMIWI
PROOR_R', CONIOI.I
y
w
..
(J"I
I
1..&
0\
'"
~
m
w
w
w
o
o
o
~
DETAUD LOGIC DIAGRAM
•
..
..,
00
~
0'\
W
W
W
Cffi)r4_7_ _ __
."
.~
o
o
IIf
---
II
't:::j'
ill~
.
-
rE,
•
IIOIPIIGST
+5V
1185
49
PWR.sw) S8
I
II
"4
1178
.esUloo 699&800
!114
'il
+5V
>I
~
1117
II. .
...'"
1188
'U
IT
PROGIIAM
PROTECT
~AuTiiSw
6
!!
01-
TEST IIOOE
5SS
1189
RIO
2
'='
UK
~
534 '='
IL(PIITIW
~II2KW
1192
11.1
'PINO) 5
PWRlNO)4
r
r
I
ENTEII
"1-
SWEEP
I"u
r
I
~I 203 ~4
US.
535
'='
':iiiU
5. (
H(tNTEII
. SKIP
1193
0
4(
lSM
"8
11M
h(SUi
SE!-. STOP
0
?
1195
Vl
MIl)!!
,
ADDII)!5
,
41
'I
f
121
I
0'\
W
PRF 11'I'lN01) •
1179
:TlON
SS7
°lOCVClE
5S8
•
~+5V
FOR PWA 89987600
;!FF - SHEET REFERENCE
,
\.n
"FF SHEET
REFERENCE LETTER
A
B
D
C1'
.t:-
SHEET
L8CATIBN
3
4
2
A-I
A-3
B-1
A -2
D-2
C-4
1
P2Z-B
rr'"~P.S.
P22-A
"
p22-e
~
BATTERY)
GlltlUND
S 30
InIIIIFF )
POWER
RII2
® ..IK
'.{>,
vee
.vec
P21 -III
.~
"
NIITES'
,P20-1lII
vee ,
ce-clS
CII-C2D
liND
GND
GND
GND
GND
GND
PZD-D4
i"'-----"i"
&lNF
"
I.
2.
3.
4.
CI -C7 ARE In F.
ALL RESISTSRS ARE 0.25 WATT 5%.
RI - Rt7, R34+R50 AND R97+ R 103 ARE 180 .BHMS.
RI8 - R33 ARE 330 !l'HMS.
5. R51-R74, R 76 - 96 AND RII2 ARE IK 0HMS
6. R104-R1I0 ARE 560 !l'HMS.
7. R75ANDRIII ARE 33K 0HMS.
vee
.., +
crl'
;; j"5J"f
IDV
....
, P20-1J
r
,P2D-IB
r
,,P20-27
,P2D-54
"
, P2D-57
,PZI -04
GND r
GND
GND
GND
GND
GNO
GNO
00
1..0
,,P21
-08
, P21-15
, PZI_I'
P21-24
FOR
" P21 -29
."
PIN 89987700
UffLUS 01l£AWlS£ SPE.CII'E:O
EII.".tON .ltf IN INCHU
P21-57
"
TOl.l.RANCIEI
-
C1'
W
W
W
0
0
PWA
r
DETAILED LOGIC
DIAGRAM
DRAWING NO
:3
.,: 1213HI'c;
r~.,-",
r~, -«; (
CSB
[AJ
P2I-55 ( m
,
~
R51
iii
, I I·"
vee ~.:o.y
U'1
I
5@
CUIU
J-I
0'1
U'1
DETAILED LOGIC DIAGRAM
PROGRAMMER'S CONSOLE
,
"
.,..
rr=-
Interrupt Li nes
,.
Location
Sheet Square
+5v
P2A31
GND
PI Bll
GND
PlA29
GND
P2A03
8
A2
GND
P2821
8
A2
50::172
Vee
Logic Ground
89633300 0,
ALU
(drawing 89614300)
Outeuts
--'-""--'
Signal
"
Active
Connector/
Pin
-.-> ..-.- ..- ......
~--
~
,,""
. ',.
•
_ ••
_ • • • •4 • • , ...... '
. . . , _ .. _
' _ 0• • _ _ ,
Locat ion
Sheet
Square
Function
.......... , - ....... ,'. "'".. ,
••••••••• __•
... ;. . . . . . ~.,
f-----...
2
C2
P1B12
2
B2
H
P1All
2
B2
Q.02
H
P1A08
2
B2
Q03
H
P1809
2
82
Q.04
H
P2A24
3
82
Q.05
H
P2828
3
B2
Q06
H
P2B25
3
82
Q.07
H
P2A28
3
82
WEI
L
P2829
QO3+Q.04+Q05+Q06+Q.07
3
C2
XGQ
H
P2At7
{X} > {QJ
3
D2
XSQ.
H
P2818
{X}
3
D2
rlAOO
H
P2A05
4
82
rlA01
H
P1B02
4
82
rlA02
H
P1A30
4
82
f/JA03
H
P2804
4
A2
rlA04
H
P2A23
5
82
f/JA05
H
P2824
5
82
rlA06
H
P2A22
5
82
H
P2B22
5
82
Q30
H
PIB08
Q.OO
H
Q01
rlA07
89633300 A
- .........-
..•
QOO-Q.01-Q02
Q register bits
~
<
{Q.}
....
Gated
A register outputs
~,,-,
5-173
ALU (drawi.ng 89614300)
Outeuts (cont I d.)
Signal
Connector/
Pin
Active
i
.-._'-"'--'
-- ...
~,~-
AOO
L
P2A27
AUG07
H
AEZ
-_.'.........
Locat ion
Sheet Square
Funct ion
'"
Least significant bit of
A regi ster
5
A3
P2B08
5
Dl
H
PIBI6
AOO -A01·AOf·A03 -A04 -A05 -A06--;;;O-; 4
A3
XSElO7
H
P2A19
SHA
H
A07
5
D2
P2B26
6
C3
H
P2B23
6
C3
Q.7A
H
P2BOI
6
A4
CNSOO
L
P1B31
6
B2
CNSOI
L
P1A31
6
B2
CNS02
L
P1B29
6
B2
CNS03
L
PIB28
6
C2
CNso4
l
P2Bt2
7
C2
CNS05
L
P2Atl
7
C2
CNSO~
l
P2Bt3
7
A2
CNS07
l
P2Bl1t
...
7
A2
GH
H
P2B03
"-
7
B3
PH
H
P2AOI
7
B3
H
i
! PIB2t
6
B2
6
B2
GL
Pl
H
~
5-174
... ... ..... -..
~
,
...
I
.J
X selector output bit 7
>CNS data bus bits
Carry generate
and propagate
PIA23
. . . -'
.... ................. -.,.-" ........
,
".
-
--
....,...... ,................ ..-..... ......
~
89633300 A
ALU
(drawing 89614300)
Outputs
------.-.----.~-
Signal
..... - - t _ - - ..... - ...•......... ,
.. - .... -_ .. , .•.••. ,., ..._._ •. _ - - , .. , .., ......,.-.-_ ... - .. ' .
Connector/
Pin
Active
1------+-,--,_... _----- ..... ,.
" 0
. . . . . . . . . . _ , ' " .... ,
....
..-'.' .•.
'
'
..
~'.--'
-'-......,
..
Locat ion
I
Sheet
Square:
Function
... "'" ..... _..... _._...........
.,
. . . . . . _ _ . _. . . . .' .
,___ .. _._
..
r.'·.~
•. ' ___ .• _._ .• __ ."
~
TA02
L
PIB04
8
Cl
TAO 1
L
P1A04
8
Bl
, TAOO
L
P1B02
8
Bl
GS
L
PIA02
8
Bl
L
P1BOl
8
B1
ALUOO
H
P1B24
7
ALUOl
H
P1B30
7
ALU02
H
P1B27
7
ALU03
H
P1A21
7
ALU04
H
P2B17
ALU05
H
ALU06
7
04
P2A16
7
c4
H
P2A15
7
c4
ALU07
H
P2B15
7
A4
ALU07A
H
P2B02
7
A4
ALUOA
H
P1A27
89633300
A
»ALU signals to bus
. __
;
~
5-175
V'I
I
.~
.....
tIFF SHEET
REFERENCE LETTER
A
8
C
D
E
F
G
K
L
M
N
P
R
S
T
U
V
W
X
Y
Z
0
AA
AI
AC
AD
AE
AF
AG
AK
AL
AM
AN
AP
AO
2
D-I
C-I
8-1
A-I
D-2
D-2
D-2
D-2
A-I
8-1
C-I
D-I
8-2
C-3
D-3
D-4
8-3
0-1
D-3
D-3
D-3
A-I
0-2
. D-2
D-2 .
C-4 :
8-4
D-4
8-4
A-4
A-4
A-4
C-4
IIFF - SHEET REFERENCE
SHEI
UR:A I'IIIN
4
3
5
6
8-3
8-3
8-3
8-3
D-2
D-I
D-4
D-2
D-2
C-2
8-2
D-2
D-2
7
8
8-3
8-3
8-3
A-4
C-3
2
. AR
AS
AT
AU
AV
AW
AX
AY
AZ
C-3
C-3
D-3
D-3
8-3
D-3
D-3
D-3
8-4
C-4
C-4
8-4
D-I
C-I
8 ...
SA
C-4
8-4
8-4
8-4
8-4
A-4
A-4
8-4
A-I'
C-I
0-1
8-1
C_NTINUES
D-4
·sv )"......
I
lIN
I
.
3
8-1
A-I
A-t
8-1
C-I
0-1
A-I
A-I
A-I
A-I
SHEET.
5
6
7
8-4
8-4
A-2
8-2
0-1
D-I
C-I
c-a -'
c-a
o-a -"
t
I~
I::z
Ivee
GNO~
8-4
8-4
GND~
GNO)rsp§!
HI
'!
"TE: ALL RESISTeRS ARE 0.25 WATT 5...
0)
00
\.0
~
\oN
\oN
\oN
o
o
»
............ ,...
-
•
UJLIa 0 " ' - . .eIND
DETAD..ED LOGIC DIAGRAM
REVISION RECORD
iliFF-SHEET REFERENCES
(C "'TlNUEO FRill.. SHEET
00
\.0
a\.II)
\.II)
\.II)
0
0
J
2
I
I
L
»
...f
:1
~
II
I
I
I
L
I
I-
8B
BC
BO
BE
BF
BG
BK
BL
BM
BN
BP
BR
BS
BT
BZ
BU
BY
BV
BW
BQ
CA
CB
CC
CO
CE
CF
CG
CK
CL
CM
CN
CP
CR
CS
CT
8X
3
4
0-2
0-2
0-2
0-2
0-2
A-3
0-3
0-3
0-3
0-3
C-4
0-3
C-4
B-4
C-4
0-3
C-4
0-4
5
0
7
6
0-1
C-I
B-1
A-I
0-2
0-2
0-2
0-2
0-2
A-3
0-3
0-3
C-3
0-3
B-4
0-3
B-4
B-4
B-4
0-3
C-4
0-4
B-2
B-2
B-2
B-2
B-3
B-4
B-4
B-4
B-4
B-4
I
1I
8
"1
II
I
0-1
2
C-I
3
4
5
CU
CW
A-I
tv
CX
CQ
CY
OA
DB
DC
DO
DE
OF
OX
OY
A-I
B-1
C-I
0-1
B-4
B-3
B-3
B-3
B-3
0-1
8-1
A-I
C-3
A-I
B-1
C-I
0-1
B-2
B-2
8-2
C-4
DESCRIPTION
-----
I
I
C-4
8-1
J
B-2
B-3
.1
6
7
C-3
B-3
C-3
B-3
C-I
C-2
C-4
C-4
C-4
C-4
C-3
~
0-2
A-I
0-2
0-2
0-2
C-4
0-1
0-2
A-3
0-2
0-3
0-2
I
3
I·
8
J
j
~
A-3
A-3
I
I
II
0.,.3
I-
I
IJ
DETAILED LOGIC DIAGRAM
ALU
V1
I
-....I
-....I
A
"
p>o' ID'NT] .
C
I
DWG NO
89614300
I..·HT.
•
I~
~
ALU (drawing 89614300, sheets 2,3)
ADDEND REGISTERS AND GATES
Functlon
This section contains the following circuits:
the addend registers Q, P, M;
the X register which is used both as an addend and augend register;
the addend gates and the comparator for comparing the X and Q register
contents.
Description
NOTE
As in the rest of the ALU, one board accommodates the circuitry
sufficient for eight bits and therefore two boards are used. In
the following the numbers refer to the lower eight bits 00 through
07 (ALU slot location 25): for the board dealing with the upper
eight bits (08 through 15)· increment the bit number by eight.
The Q, P and M registers store the information selected by the shifter (refer to
sheets 6,7).
Each one is timed by a separate clock signal (QCK, PCK, MCK)
generated on the Timing board.
The P and M registers are reset by the Master Clear (Me) signals, the Q register
by its own clear signal (CLRQ).
The Q register outputs supply the A/Q channel
The three least significant bits
bus through open collector buffers U36, u48.
of the Q register are also sent, in complement form, to a three-input AND gate
(U49/6) to produce the signal Q30 = QOO-Q01·Q02. This signal leaves the board
through an open-collector driver.
5-178
89633300 A
ALU
(drawing 89614300) sheets 2, 3, cont'd.
The five higher bits of the Q register (the W field) are used to produce the
function WEZ: Q03·Q04·Q05·Q06·Q07 at U35/8.
The signal, from the most
significant ALU board, is sent to the A/Q channel through the console interface
board.
The WEZ and Q30 signals from both ALU boards are used to sense when
the contents of the Q register is zero (see Console Interface sheet 6).
The X register and its associated selector are described on pages facing
sheets 4, 5 of the ALU circuit.
The comparator U54, u62 compares the
outputs of the Q register with the complement of the X register.
This
comparator produces the signals XSQ and XGQ (XQ) which are sent to
the console interface card.
This comparator is used only during divide
instruction.
Because the absolute values of X and Q must be compared and
the X register content is always negative during the divide instructions,
the complement of the X register content is input to the comparator.
The addend selector gates select the outputs of one of the addend register for
transfer to the ALU under control of the signals QTADD, PTADD, MTADD and STADD.
89633300
A
5-179
...
\11
I
..
....
_ _ It
00
o
vee
R44
II<
C"PARA11IR
4~8 % I
4 524
4J!,!,.i)-J2 2 AM
lrxt.~
i
E$.
5U
CI<
PUllS
1
J,4, u.s@-
M-REGISTER
R
12
I '!" Ace
14 8
" 4 8
9 2 A08GI
I
r8
co;-- ~
10
5-~
6.,
AD
ICI< PIAI4
CLRO"PlAl3
I
AN"
49
I
I
1
E
......i
]
520
U46
CDo
5~
12
13
3 AE
PCI<
4.11.6 AG
00
\D
0'
PI813
I
~
.....!~
a
23
2
...! U48
4-
7
6
10
r-vr
'81
co.- "
15
14
(§f
p-REmER
I
9 C
RRGTR
520·
U63
5 COo
u9-
1JQ.
_
II
13 U64
4®-tl
I@
MTADD " PI814
3
f~5
180
8
R28
f80
I::;:;:
II .~
2~
r.:..
......
PI808 "050
,
4,6 AL
12~~
4,6 AI<
13ro-15
I
14
»
•
-
tf"
•
10 •
PI8I2/~o.0.
Ir-"~
2~
PIAII, .0 to0 •
8
UI2
4~ ~
PIA08 0 •
~
3 •
4-
.010
4@-yf
PI809
~O.,o"
9
10
-•
UI4
6
•
~~
.:--
J®8
r-"I"
I
13 • •
2~
3 •
~
4~
~
4ID-rl
7
-~
10
•
U31
9
10 •
~-
~L
----@8
\AI
\AI
\AI
o
o
•
4~
9
7
4~ ~
I
4®-rl:
V3
4',6 @
~]E
13 •
6
•
~~
I
10 U64
R27
180
UI5
10 •
vee
ft26
180
•
9 oooi
R46
2~4
2~
3 •
4~
vee
2~4
4 213H 6
3 U49
~
OTADD" P2A26
XTADD;' PlA09
~~"
:~ER
1iJ: C
Ii:\.
6.3 F
7
L-.@3
ADDEND GA'
I r-"r""j""
13 • •
,Ie
PTADD "PlA12
!.-.@ 3
R45
~
CO.
3 E
~8
~
13~~
I
14
1""1 DATI ICIII
I
3 G
7al
~
ECO
~3
~.83 !-oj-
.~
I...r. C
....RRGTR
520
U47
r-~ COo
H.
\
2 A 0 8 GI
"
. . . GI
A08 I
U62
G2
IlO£vl
DETAILED LOGIC DIAGRAM
ALU
6
•
I
I
RE1I1SION RECORD
10EvI
I
OESCRIPTION
ECO
10RFT OATEL:HKDlup
00
\.0
0'\
W
W
W
o
o
1-"--:"';='-<.JU:t\lL,
XGOM
)
I
32KW) P2A29
~VFW) P2B27
»
7
7 P2Bla
2
2,4,5.6,
,-I
AF}---.....-'''''l!'
" CO
5.7 az
5 CD4
•
5.7fiiih.
>::::/
5 7 BX
•
2
===========---:-===---==11
3
5
I
CO;--~
12
co-- ~
13
IIIII
62 AD
z@ 11111
~~
R43
IK
10
8
I
Wffi.WEzi.
P2B29
U39
C04
10
13 -
15
14
CDr
I
_
U
CD
.~12
6®--- _
a
~04
Tr
-
R31
180
3
U23
~
8
AR 7
.
BIT-5
II
~
~]
10
~ 1:....-J
I-~
I; ~ 209H
'
3 8
12
R54
180
"
yee
13 U50
5~a
U24~S}7
U
I
4 -
r®1
AZ 8
BIT-.f
>=J
I
9-
a
10
~I
8A B
::.&.,.
;J:it~
"
AX 8
-
-{ill
AY 8
~
'----~
ELBITCDMPUTlASLlD
... "., .,,"
faD'
q
P2BOI
If
5
6
9-
P2A28 07 015
~
12~CD
15
6
00
I
4 -
5 AU
~06,014
~ ~ I~I
Q7M
a
;®-rl a
R32
IBO
P2A24
,04,012
P2B25
~
-~
2_ 209H
3 a
I
P2B28 '05,013
1_
L-.
5
'3
4 I----
~~
6
"9lJQ.
- 8
1; RGTR
~
R30
180
~~
1I11Llli.~C
520
U40
R29
180
I~a II
T 13 2
~[REGISTER
AO 7
~~
yee
12 -
a
-----1l ,...
13
F::-3
c
~
U7
9110 a
9 U50
RRGT
520
~~
\J'1
I
41-
5~ a
"-'-' U
44
I"'~
i-=
2U
"f:
a
3
~iREGISTER
5 ~ 7
~CD5
6
IIIII
Zt-
I -
15
~
I
~~~4
--.JQ.
~
I~~I
yee
2 213H,lL
13 U35
9 .;;.;;;.
~
-
III !
l
!@-t,......2 V
a
r-- ~
76
TI
~
I
!lh=t
~
Ii 7 BY
)(SOM
DETAILED LOGIC DIAGRAM
ALU
1411111mlllM
I
')
...
"
I
'0"',
,
DWG NO
C
,REV
89614300
St·t t T
..
3
I
A
ALU
(drawing 89614300, sheets 4, 5).
AUGEND REGISTERS AND GATES
Function
This circuit contains the augend registers A, Y and the augend gates; as well
as the X register, which is used both as an augend and addend register.
Descri pt i on
NOTE
As in the rest of the ALU, one board accommodates the
circuitry sufficient for eight bits and therefore two
boards are used. In the following the numbers refer to
the lower eight bits 00 through 07 (ALU slot location 25);
for the board deal ing with the upper eight bits
08 through 15) increment the bit number by eight.
The A and Y register store the information selected by the shifter
(refer to sheets 6, 7). Each one is timed by a separate clock signal
(ACK, YCK) generated on the Timing board. The X register stores either
the shifter outputs or the MX outputs of the memory control board. The
choice between the two inputs is made in the X selector (US3, u61) under
control of the signal XEZ from the I/O interface circuit.
The MX data from the memory control board is the memory output
durin~
a
read memory reference cycle: MXOO through MX07 for the ALU board dealing with
the least significant bits, Mx08 through MX15 for the ALU board dealing with
the most significant bits.
The MX data lines are terminated in 330 ohm pull-up resistors on the ALU boards
The A and Y registers are reset by Master Clear (MC) whereas the X register
has its own clear signal (ClRX).
5-182
89633300
A
ALU
(drawing number 89614300) sheets 4, 5, cont'd.
The outputs of the A, Y and X registers form some of the inputs of the
augend selector gates.
The outputs of anyone register are transferred
to the augend gates under control of the signals ATAUG, YTAUG, XTAUG.
The other control inputs to the augend selector gates are SG, 51, SF and
DELTAUG.
The following figure shows the augend gate control signal connections.
Notes (to Augend Gate Control Signals):
1.
2.
89633300 A
01 : 03 on the LSB,
are bits 04 : 07 on the LSB,
j are bits
bits 09 . lIon the MSB.
bits 12
t
15 on the MSB.
5-183
AlU (drawing 89614300) sheets 4, 5, cont'd.
SF ,'"
SI
XTAUG
8
,'"
~
,'-
8
H
YTAUG
,
Xo
~
~
'-
ATAUG ,'"
I
BIT 0
8
Yo
~
8
Ao
,
SG ,'"
~
E
8
I
~
a
H
Xj
~
~
BITS j .
a
Yj
~
a
A·J
~
,"
E
a
I
~
DELTAUG
,'"
a
Xi
~
BITS i
a
y.I
~
a
Ai
,"
5-184
~
~
E
Augend Gate Control Signals
89633300 A
ALU
(drawing 89614300) sheets 4, 5, cont'd.
The augend selector gates can, with the aid 0; the above signals, transfer
the content of the A register, Y register, or X register to the ALU. These
gates can also transfer part of the content of the X register with the
upper bits zero, as follows:
Transfer Signal
DELTAUG
DELTAUG
L-
Remarks
. Remaining X-Register bits:
X Register Bits
transferred
00 T 03
00 T 07
00 .. 07
12 bits
8 bits
8 bits
to bit
recognized as zero
recognized as zero
si!=jn-extended according
X07
1
The output of the augend gates is active low.
The following table summarizes the selection of the constants:
r'Contro 1 Signa 1
SI·SF
S I·SG
SI·SF·SG
ATAUG·YTAUG·XTAUG·ST
89633300
A
.
..--- _..-...-..
.."
....... _----,
Constant Selected
I
+1
-1
-0
+0
5-185
ALU
(drawing 89614)00) sheets 4,5, cont1d.
The following truth tables show the augend gate control signal configurations
for both ALU boards and the corresponding augend gate outputs.
AUGEND SELECTOR - MOST SIGNIFICANT BOARD (MSB)
..
I
Augend Gate Control and
(Corresponding Signal)
i
I
I"'.' -_..... . .-..
!
.
YTAUG l XTAUG
(YTAUG) (XTAUG)
1-----+---
DEL TAUG' SF
(H)
(SE)
i'
SG
SI
(SSE) (I M)
"--'-'~---~---+-----il------I
l
H
l
l
l
L
H
H
L
L
l
l
L
H
H
L
L
L
H
H
L
l
xb7
X07
X07
X07
X07
l.___. . I
l
H
H
H
H
H
·
l
L
l
,
··:i
_--
.................
--
.--..... ! .
.. .-. -" .. '1"........ ........ '''.
A:rAUG
(ATAUG)
"
Augend Gate Output
(act ive low)
-"--''' ........ .... -,,-.~-----
L
.
l
L
L
H
H
I,
I
I
A register
Y register
X register
Extended sign bit of
~
00 16
FF16
-I.-_.l--.---I.._--4t__ . .___- - - - - -
...I.-_--'-_
_
!
AUGEND SELECTOR - lEAST SIGNIFICANT BOARD (lSB)
'~"-""--.~"~----"---"'~'--'-'~-''''''"'''''--
-'-.- ..
-----.~.'
.....
....----.------,--.-----.--~.-----
Augend Gate Control and
(Corresponding Signal)
... -.-.". .......... .....
I----r-----,:--~--·--··---
Augend Gate Output
(act ive low)
...- ..-.- ...- - - - - - - . _ - - 1
r-'"
ATAUG
(ATAUG)
YTAUG
(YTAUG)
XTAUG
(XTAUGl)
H
l
l
H
H
L
H
l
H
H
l
l
H
H
H
l
l
H
L
H
l
l
l
H
H
l
l
l
l
H
l
H
• _ _ _ _ _L _ . _ _ ....._
DELTAUG
SF
(DELTAUG) (SFl)
...
A register
Y reg i ster
X register
lower 4 bits of X,
11011 extended
I:
-_
The signals ATAUG, XTAUGL, XTAUGM, and SIL are produced on the decoder board.
The signals YTAUG and SGL are produced on the timing board. The signals
SFl, 1M, SE, and OELTAUG are produced on the I/O interface board.
H = active high,
5-186
l
= active
.
....... ..... _-, ........
low
89633300 A
ALU
(drawing 89614300) sheets 4,5, cont'd.
The A register outputs supply the A/Q channel bus through open-collector
NAND gates. The outputs of these gates are controlled by the A/Q channel
control signal, AQC, from the I/O interface.
The A register outputs are wire.-ANDed after inversion in Ul3 and U3 to
produce the signal AEZ. This indicates whether the content of the
A register is zero.
This circuit includes a fl ip-flop (U5l/6) which stores the least
significant bit of the A register. The input to the flip-flop is the
least significant bit of the shifter. It is clocked by the A register
clock and cleared by Master Clear (MC). Its output is used during
multiply instructions where this bit must be stable early in the cycle.
89633300
A
5-187
.r.
v
V'I
I
00
00
0'-:', '" j;;(
~
PIAI8
XEZ
..
-.X,
~hg~>
5 CB
5 au
VCC
RH R6 R7 RB
330 330 330 330
MX3L
PIAI6
M
M
MX3M'
MX2L
PIBI5
M
MX3M
M
MXIL
PIAI9
M
MXIM
M
MXOL
MX
PIBI8
MXOM,
MX
5 CA
YCK PIA20
CLRXr~
Me ILl
189
U61
9
110
10 I I
3
0
AF
~:g
U45
5 BK
15
5~76
4~~2
Ll...--
II~
I r-r--
~181~
'I~a
,
4~
'm1
5a
~60 10
I~
6
9
10
J
J!ro;-15
~
2
2
,6
AG
.r:-::>.
'~
2
AK
2
AL
.
~R
!J
C
R
I
4
YGTR(
520
U44
COo
I
~2
2;
I ~
a
2
~
2
13
6
~
reo-- ~
00
15
0'\
\N
\N
\N
o
o
»
cf
ISO
ISO
a
I
-r---
2
~ 120910
5
6
9
10
r:@" PZ AQZ.
121--
II
r@6
~14
'--
~~
3
26
10
I UI3
_~
13~~
II~~
~~
!
PIA30
a
U28
6
~
BIT-I
a
~~
P2A05 J'AO"A8
r@)6
W-
A
"j=~_6
8
II~
~
RI5
180
~9 I--
~_
I
"---
3
RI6
Vee
RI4 RI3
2 204~ U30
41-==
5
_ 6
fo:-:.-- ~
10
12 CD
6
~a
4-
5@-
5~ 1
C
~al
"--- ~
1
~.
8
BJT-2
UI2
]E
~2 .:....-..
-.!co.-~
....!:co;- 7
BII.
.CK PIBI9
A CK
~~
520
12
r!-::-;-@
1IT.-3
lOa
W 2
I....-
U29
9~
L 2
~
CDo
I
209H
5a
6
'
IK
5~
';~
W
R
2,3,5,6,8
2
,-
~a
4~
!,.QI
'Ice
a
2~
XTAUG~~
N 2
~2
13
5@ XTAUGM
P 2
I
~2
~'ir-4
j
~
T AUGEND
GATES
I r-r--
5@
5 BG
5 BF
12~10
13 I 2
r--!~7
I
~
17
IJR
13 CDI
~1i>-12
6 I
,
PIAI5
25
iii, JA9
SE(MI,PIB22
SFL
1
~]E
I~
13
a
I
2~ 209H
in ,iiAiO
a
P2804 {ii!, iJ,ijj
:a ~
Y
UII
9
II
P1816/AL
AM
29
4~
8IT-0
15
a
~JE
'---
k!ID5
~Vcc
IK
l~l'lT
tllllPlmIS,LT!I
' .........
"
nF'TAII F'n
lOGIC DIAGRAM
rOOE IDEO'
_I OWG NO
C
ALU
4
89614300
1
....
v
0)
.P2AI9
_~.9/XSEL7M
'@};~f---d ,.. '""I
;,P2A30
,/
13 iii 209H
213 8
41-
A-REGISTER
..9
JR )
3AU
59
520
)RGTRI
U37
4 CD.
2
~I--
131ci;-- 15
~I-12
II
~
~~
V'1
I
0)
\0
2,4,6
;'\
'.J
r-'j'"'
~S-~
2
5t6
~ 203M
L---.J!
If
4
~- ~
IE 7
13 iii 209H
2138
4
I
5
U22
6 8
10
9 8
4ill
IN 4
8
I1T-4
~
~L
3
I--:~
T 131--~
I
~ 11
, i6
P2A27
----.;
IHAIT rn.PIIIIA~ 11111
• ...
...
lI.eI:,'Ua'in!ih1·
7
<------...! I"" . . . .
r®r ,I
P2822, iA7,lii5
eo
~J.:..-
,
DA 4
52_
~ 2,3,4,6.~
I
'---
12
3 ~ 175H
I" R U51
-
I
BIT-5
r:::llf-
ji4 'AI2
P2124';IA5,iAi3
{---@7
,.
P2A22 iiA6, jjAj4
~-
6@-
~
~.'
CE 7
<41
12'cD;-~
13 146H
UI8
CF 7
P2A23
2 204 3
U20
5
_.6
10
5 III U21
6
9
10 iii
Vee
~~~~~
~r-;;-
~
51cD;- 7
I
Be 7
BIT-6
r;f!f-
s~
3,7
85f
'~L-
~~7
~ ~
,
BB 7
~I-
~
4
8
BIT-7
~~
IMIHIGH
III
"cii";'- ~
5f~ AUG7M
4
5 111
U4
6
9f10 III
R!IO
III i5EL'ii'OO P2B16
10
AUGEND GATES
I
I'""'j"""
13 III 209H
~III
4®--l
9j
"1iJ
Y
4@
Vee
10",.TI DATE I
DE5CRIPTION
YTAUG PI817
Y-REGISTER
4
~®--l55;4
c,
ATAUG P2A21
~~3
3 !.O....I •
I
SEIMI,SGL ,PlA22
SIM ,SIL :PIAI7
5~ 7
BQ 3
CD.
~
4~ 2
IR 3
CD.
s
,....J~4
, ... P2A20
~~
~
~~7
0
I
fr
co;--
12
13.
6
-;
I
9
t--
~
T
4 BU
IB9
~liI
U53
.
MX7M,MX71 ... P2B19
»
4
GI
IAEVI 'co
"
X-REGISTER
OF TAILF.[l lOGIC DIAGRAM
AI.l/
I"'C'"
r
c
DWG NO
89614300
I ......
1
&
I
ALU (drawing 89614300) sheets 6, 7
ARITHMETIC AND LOGIC OPERATIONS
Function
The ALU microcircuits U57, U59 form the heart of the ALU board.
the nine arithmetic and logical functions used in the computer.
Description
They perform
NOTE
As in the rest of the AlU, one card accommodates the
circuitry sufficient for eight bits and therefore two
boards are used. In the following, the numbers refer
to the lower eight bits 00 through 07 (ALU slot location 25);
for the board dealing with the upper eight bits (08 through 15),
increment the bit number by eight.
The outputs of the addend and augend gates are combined in the ALU microcircuits, the four lower bits going to U59, the four upper bits to U57. The
control inputs (SOO through S03, M) are generated in the Decoder board. The
carry look-ahead function is provided in the Console Interface circuit which
produces the four carry signals for the ALU boards.
The ALU microci rcuit outputs (ALUOO through ALUO]) form the inputs to the
shIfter and feed the ALU bus through 33 ohm series termination resistors.
The ALU bus carries CPU memory address and memory data to the memory address
card of both the internal and the optional expansion memory banks.
The CNS data gates, (U56, U58) are open collector NAND gates which transfer
ALU data to the bi-directional CNS data bus. The eNS data gates are controlled
by the signal CLREG from the programmer's console.
5-190
89633300 A
ALU (drawing 89614300)sheets 6,7, cont'd.
The ALU Microcircuit (509)
The Arithmetic Logic Unit (ALU) microcircuit is a commercial I.C. package (509 or
74181/9341
described in the Key to Logic 5ymbols, Control Data publ ication
number 89723700 (or equivalent) and in manufacturer's specifications. Its
salient features are repeated here and its specific use in the computer ALU
circuit is described.
The parallel ALU is controlled by the four Function 5elect inputs (50,51,52,53,
having binary designation 1 ,2~4,8) and the Mode Control input (M).
It can
perform all the 16 possible logic operations or 16 different arithmetic
operations on active high or active low operands.
In this computer it operates
on active low data because the addend and augend selector gates complement
the data.
When the Mode Control input (M) is high, all the internal carries are
inhibited and the device performs logic operations on the individual bits.
When the Mode Control input is low, the carries are enabled and the device
performs arithmetic operations on the two, 4-bit words.
The device incorporates
full internal look-ahead carry and provides for either ripple carry between
devices using the signals PL (carry propagate) and GL (carry generate).
PL and GL are not affected by carry in.
When speed requirements are not
stringent the 74181 can be used in a simple ripple carry mode by connecting
the carry out 16 (pin 16) signal to the carry input (C) of the next unit.
For high speed operation the 74181 is used in conjunction with the 74182
carry look-ahead circuit.
One carry look-ahead package is required for
each group of four 74181 devices.
89633300
A
5-191
ALU
(drawing 89614300) sheets 6,7, cont'd.
The computer ALU circuits utilize nine of the possible 32 functions of the
ALU microcircuit.
The functions and the control signals are shown in the
following table.
MODES OF OPERATION OF ALU MICROCIRCUIT (509)
M
INPUTS
S3 S2 Sl
FUNCTION
OESCRI PTI ON
SO
_______
1..... ·•
H
L
L
L
L
AUGEND
1.
Complements the register selected
by the Augend.
H
L
L
L
H
ADDEND-AUGEND
2.
NAND function
H
L
H
L
H
ADDEND
3.
Complements the register selected
by the Addend
H
L
H
H
L
ADDEND,AUGEND
4.
Transfers register content (except Q)
through the ALU when the computer is
stopped.
H
L
H
H
H
AUGEND -ADDEND
5.
Transfer the Q register content
through the ALU when the computer is
stopped. (In this Case Augend is zero).
H
H
L
L
H
ADDENDtAUGEND
6.
Exclusive-OR function
H
H
H
H
L
ADDEND-AUGEND
7.
AND funct ion
L
L
H
H
L
AUGEND MINUS
ADDEND
8.
Subt ract ion
L
H
L
L
H
AUGEND PLUS
ADDEND
9.
Addition
H - logic high,
5-192
I
L - logic low
89633300 A
AlU
(drawing number 896l4300) sheets 6,7
SHIFTER
Function
The shifter outputs determine which data is valid at the input of the CPU
registers at the end of a cycle.
Description
NOTE
As in the rest of the AlU, one card accommodates
the circuitry sufficient for eight bits and therefore
two boards are used. In the following the numbers
refer to the lower eight bits 00 through 07 (AlU slot
location 25); for the board dealing with the upper
eight bits (08 through 15) increment the bit number
by eight.
The circuit consists of eight-input selectors (505), one for each bit of a
computer word, and a flip-flop. Each selector is controlled by three selector
lines (three of CO through C3) which select one of the eight input signals.
The table following the next paragraph is the truth table for the shifter,
together with the operation of the ALU circuits. The circuit functions are
explained in the paragraphs following the table.
Shift Fl ip-Flop
In addition to the selectors, the AlU board carries the Shift flip-flop and
associated gating (U5l/8,9 and U26, U3/8,lO, UlS/2,4,lO, Ul9/S). The flipflop, located on each ALU board, stores information during the first step of a
double-word long shift. The information stored is from the ALU board itself or
generated in the current cycle on another board. It is stored here so that it
should not be lost at the end of the cycle, as it may be needed during the
?econd step of the long shift. During the first step of a long shift or during
a short shift the content of the flip-flop is never used. It is sometimes
used in the second step of a long shift.
89633300
A
5-193
VI
I
SHIFTER CIRCUIT OPERATION
\0
-I:"
r
Contro lSi gna 15
C3 C2 Cl
CO
Selects Input
No.
Bits j BI ts I
OUT PUT S
Bit 7
Bit 0
Bit
(15)
Input of
flip-flop
Operation
I~
~--~--.-----
L
L
L
L
L
L
o
o
L
o
H
ALtJ06
ALU06
n
ALUi-l
ALUlo-1
SHB
-.,
Short left shift
Z5
Q ..
First step of long left shift; used only
during divide Instruction. This code usedl
also during second step of any long left I
III
~
::::J
IQ
::::J
C
L
L
H
L
2
2
SHC
l
H
L
L
it
it
ALU07
6
6
ZI
ALU i+ 1 ALUOI
°
ALUi
ALUOI
ALUI_l
SHB
H
H
L
H
L
L
H
H
L
H
H
3
3
H
5
QA07
7
CNS'07i . CNS i
ALU06
ALUOO
ALUi+1
L
ITAI
A'EUOo
Second step of any long right shift
Direct transfer ALU data
..........
g.
.,CD
00
\0
0'
ALUOO
Short right shift or first step of any
long right shift
-I:"
W
Q
First ste~ of cyclic long left shift
In shift Instruction.
Transfer trap address
:r
• ITAO
o
o
I II
CD
CD
,..,.
III
0'
H
H
L
H
5
H
H
H
H
7
.• _ ,_,1
.. _,j
QAi
QAOO
-CNSOO
Transfer A/Q data
.......
Transfer CNS data
n
o::::J
,..,.
Q..
NOTES:
\0
i • 01 through 06 t j • OOt 07 for ALU board in slot 25 (LSB)
09 through 14 t j .. 08 t 15 for ALU board in slot 26 (HSB).
W
W
for
00
3.
Control Inputs are connected as follows:
r·
0'
W
o
o
»
jO.
Bits
01 t 06 t 10'; 13 connected to H.
~
High- logic high;
L=logic low
Control signals
CO Cl C2 C3
--0.' . . . . . . . . .'__ .•.. _ _ . . . . . . __
B
C
A
ALU (drawing 89614300) sheets 6,7, contld.
The connections to the shifter selectors and flip-flop are summarized in the
following figure.
CO
co
C2
z:s
SHI
ALUI
ITAO
ALUO-
liT 0
i1ii
liT?
ALUI_I
ITAI
ALUi
liTS i
OJ
CNii
SHIFTER SELECTORS
CII
CI
SHIFT FLIP-FLOP
89633300 A
5-195
ALU
(drawing 89614300}sheets 6,}, cont'd.
Shift Operations
NOTE
Timing diagrams for shift operations are given in the first sheet for
the Timing ci rcuits in section 5.
During a short left shift, each output of the shifter receives the next lowest
bit of the ALU. The lowest bit of the shifter (SHOO) receives the signal Z3.
The signal Z3 of each ALU board is wired to the most significant bit of the ALU
output on the other ALU board. Thus the shift is cyclic.
The first step of a long left shift. is similar to a short shift. During the
first step of a long left shift during divide, the SHOO bit is connected to SHB.
During this time, the signal QSX is stored in the shift flip-flop. QSX is
equivalent to the end-around-borrow resulting from substracting the X register
from the content of the Q register (X from Q). In the MSB, SHB is connected to
ALU07 of the LSB. In the LSD, SHB is connected to SHA of the MSB. During the
first step of a long left shift, the signal QTADD is high so thatSHA becomes
bit A07 of the MSB.
During the second step, QTADD is low so that SHA becomes the bit that was
previously stored in the shift flip-flop.
The first step of a cyclic long left shift differs from a long left shift in that
the bit stored in the Shifter/register is Q07 of the MSB. The execution of a long
left shift is shown below.
5-196
89633300 A
AU)
(drawi n9 89614300, sheets 6,7, cont'd.)
MSB
LSB
0
0
00
07
CONNECTION
ON COMPUTER
BACK - PLANE
A
00
07
a
L..-_-I SHIFT
~~~
}
- .....
FF
a
o
CONNECTION
ON COMPUTER
BACK - PLANE
_--'
OSX OR 007
STORED
1.
07
First step of double word left shift.
MSB
LSB
A
A
CONNECTION
ON COMPUTER
BACK -PLANE
o
SHIFT
FF
2.
89633300 A
a
CONNECTION
ON COMPUTER
BACK -PLANE
Second step of double word left shift.
5.. 197
ALU
(drawing 89614300) sheets 6,7, cont'd.
The short right shift may also be used as the first step of a long right shift.
During the operation each bit is shifted one place to the right. The least
significant bit ALUO is stored in the shift f1fp-flop. The most significant bit
of the shifter receives Zl. In the LSB Zl Is connected to ALUO of the MSB. In
the MSB Zl is connected to the function.
(ALU07 of MSB) + (F
= 2)
This causes the resulting word to be sign-extended, except during multipl ication,
when a positive sign is assumed.
The second step of a long right shift is the same as the first except that SH07
receives the input SHC. On the LSD, SHC is connected to ALUOO of the HSB while
on the MSD it is connected to SHA of the LSB.
The execution of a long right shift is shown below.
, AW07 OF MSB)
+ (F=2)
MSB
LSB
A
ZI
StlFT
FF
CONNECTION
ON COMPUTER
BACK-PLANE
1.
First step of double word right shift.
MSB
A
SHC
LSB
SHe
A
07
SHIFT
FF
SH
CONNECTION
ON COMPUTER
BACK-PLANE
SHA=SH
CONNECTION
ON COMPUTER
BACk- PLANE
2.
5-198
Second step of double word right
s~.ift.
89633300
A
ALU
(dra~ing 89614300) sheets 6~7, cont'd.
The signals which are used during double word shifts to control the end bits in
the shift flip-flop are connected as follows:
"
, _ ••••• , .
•
"'''.
~.'''''
_.
INPUT
.0
A
_ _ _ _,
SIGNAL
t40st significant
board
89633300
_~
=
(F
= 2)+(ALUOO
Least significant
board
of MSB)
ALUOO of MSB
Zl
ZJTSH
Z3
ALU07 of LSB
ALU07 of MSB
Z5
QSX
QSX
SHB
ALU07 of LSB
SHA of MSB
SHe
SHA of LSB
ALUOO of HSB
5-199
V'I
..
""
I
N
o
o
33
7
SHIFTER
po-
~._W(~
&
(7\
\N
\N
\N
o
o
;I>
DETAILED LOGIC DIAGRAM
ALU
.
_-
...1
..l.
IREvl
""
I.~
3.;"
mIo
I
I I
Eca
'!
'CtIKD' ~
.~~::~
I
SHIFTER
.oj:
I'
r
6{CY
.rB~-5 r
-
3;5
~
I~
VI
I
N
o
A
4J
Z
I-
"
I
I
I
I
-
-
AlU
(drawing number 89614300) sheet 8
INTERRUPT LOGIC
Function
This circuit accepts the signals on the interrupt lines and processes them
to produce outputs according to the content of the mask (M) register and
the predetermined interrupt priority.
Description
NOTE
As in the rest of the ALU, one card accommodates
circuitry sufficient for eight bits and therefore
two boards are used. In the following the numbers
refer to the lower eight bits 00 tnrough 07 (AlU slot
location 25): for the board dealing with the upper
eight bits (08 through 15) increment the bit number
by eight.
The interrupt signals are stored in the interrupt register (UI6, UI7).
This is clocked by the interrupt clock (INTCK) from the Timing board and
reset by Master Clear ('Me). The signals on the interrupt I ines are active
low.
5-202
89633300
A
ALU (drawing number 89614300) sheet 8, cont'd.
The outputs of the register are gated through to a priority encoder (U6S)
under control of the content of the M register. The priority signals
coinciding with a logic high in the M register are allowed to pass, and
are considered active.
The priority decoders on the two ALU boards are connected in cascade to
detect the highest priority interrupt which is active at any time. The
interrupts have ascending priority from INT1S to INT08 and from INT07 to
INTOO,the interrupts on the board dealing with the least significant data
bits (LSB) having priority.
The following table shows the operation of the priority encoder:
EI
o
o
o
o
o
o
o
o
o
INPUTS
2 . 34 S 6
OUTPUTS
TA2 TAl TAO
Ee
x X X X X X X X· H
H
H
H
H
H H
X X
X X
XX
X X
X X
X X
o
7
GS
H
L
H
H
H
H
H
H
L
L
L
L
L
L
H
L
L
L
L
H
H
H
L
L
H
H
L
H
L
H
H
H
H
H
H
H
L
L
H
L
H
H
X L H H H H H H
L H H H H H H H
L
L
H
H
H
L
H
H
H
H
H H
X X
X X
XX
X X
X L
L H
H
X
X
X
L
H
H
H
X
X
L
H
H
H
H
X
L
H
H
H
H
H = Logic High
L = Logic Low
X = irrelevant
The input EI on the LSB is connected to ground while El on the HSB is
connected to
Ee
on the LSB.
The signal GS from both ALU boards go to the console interface card.
GS
from the MSB is connected to ITAS of the LSB.
The outputs TAO, TAl, and TA2 of both ALU boards go to the console interface
and are used to produce the trap address bits (ITA2, ITA3, and ITA4) which
are connected to the LSB of the ALlI (see console interface sheet 7).
89633300
A
5-203/S-204
6
7
9
~
7
V1
I
N
o
V1
r.t"
I IS
Pla04
PIA:
Pia
~TA2L. TA2M
!AIL. TAIM
TAol. TAOM
PIA:2
~:.GSM
Pia
DETALED LOGIC DIAGRAM
ALU
"Pages 5-206 to 5-210 are unassigned".
5-206/5-210
89633300
A
.. ~ECODER
The Decoder circuits are accommodated on a single 50-PAK printed wiring
board.
The logic circuit diagram of the unit is given in drawing
number 89614900, sheets 1-6.
The Decoder circuits include the instruction register with its decoder
and other CPU control circuits.
This page lists the functional blocks
The circuits and signals are described in
accommodated on this board.
detail on pages facing the corresponding sheets of the circuit diagram.
MAIN FUNCTIONAL BLOCKS
---_..._---------
------------~------------------~
Designation
.
-.---................
..............
,..~
Shown on sheet
--------.,---
Instruction Register
2
First Level Decoders
2
Addend Gate Controls
3
Augend Gate Controls
4
Controls for ALU and Addressing
5
Register Clock Controls
6
89633300 A
5-211
,
V1
N
N
PFF - SHEET REFERENCE
reFSI£ET
EFERENCE
LETTER
A
8
0
E
F
G
J
K
L
M
N
0
R
S
T
U
V
W
X
Y
Z
AA
00
\.0
0'\
UJ
UJ
UJ
o
o
»
AB
AD
AE
AF
AG
AJ
AK
AL
AM
AN
AO
AR
AS
AT
AU
AV
AW
AX
AY
AZ
BA
BB
THIS
SIGNALS
2
0-4
"OEC
0-3
DEL
8-4
17
8- 3
17
RI
8-3
WI'
8-4
Jrr
8-4
R4
8-3
8-3
R3
A-3
R2
A-4
R3
A-4
R4
fa
C-2
8-2
TI
T4
8-2
8-3
Flo()
0-2
T3
A-3
FloA
C-I
TI
16
8-3
16
8-3
C-4
~
B-3
15
C-4
1'4
C-4
14
0-3
0-4
13
C-3
12
12
C-4
C-3
!"
C-4
11
10
0-3
10
C-3
165
B-3
B-3
123
Fl'6
B-3
Flo7
B-3
Floe
B-2
A-3
FloC
FloO
A-2
FloF
A-3
FI-O
A-2
FoO
C-I
F-2
B-1
TABLE CeNT HUES elN
n
SHEET LPCAT/~N
3
4
5
C-3
8-4
8-3
C-2
C-I
8- 2
A-4
8-1
C-2
0-4
C-4
C-2
8-2
C-4
0-4
C-I
0-4
0-4
0-4
C-4
0-4
8-4
8-2
8-4
8-4
C-I
8-3
8-3
C-4
8-2
0-3
8-3
0-2
A-3
C-3
0-3
A-3
A-3
B-3
A-4
C-3
B-3
A-4
C-4
A-3
A-4
6
0-2
0-2
0-2
C-I
0-3
0-3
63
8-4
+5V)
B-4
~el
GND ) P2A03 ,
GND ) PIB21
I
:.~J'F
I
I
vec
l' ~et
68HF
!"IAU
GND.
GNO') PIBU
C-3
A-4
0-3
A-3
B-3
B-4
B-2
RI
(ii)
0-2
)!..
Ivee
C-2
A-4
A-4
~,
A-4
C-4
C-4
A-4
B-3
B-3
A-4
0-3
C-4
0-3
SHEET 7
ALL UNMARKED RESIST""S ARE 0.25 WATT 5%
~ ELEMENT JDENTlFER IS PENDING
UNLUS Oft«'""" PlCI'EO
D._liON
-=-I
.A, ...
TOLIItMCII
OETAIL"EO LOGIC DIAGRAM
DECODER
...
•
I
00
\.0
~
\oN
\oN
\oN
o
o
»
V'I
I
N
\oN
.......
V'I
I
N
~
lRE~
(C~NTINUEO FR;M SHEET I)
~FF - SHEET REFERENCE
eFF-SHEET
REFERENCE SIGNALS
LETTER
F=3
8C
81)
F-5
F-6
r- BE
Fo7
8F
8G
FoB
FoB
8H
FoO
BJ
FoE
BK
FoF
8L
8M
FIIlI
FI.8
BN
FI=9
BP
80
FI =2
FloO
BR
8S
FI'A
FI=E
8T
F .... O
BU
F.9
8V
BW
F.... A
BX
F.. Y
F .. 5
BY
F~7
BZ
CA
FoOC
C8
F .. O
CC
F.. F
CD
RE1F
CE
ITR
CF
016
RNl21
CG
fIIPE
CH
CSM
-2J
FI,o&+7+F
CK
CL
RI.R2,R3.R4
CM
RNlI2
RNIII
CN
CP
F"QFI°2.3
ePO
CO
RNI22
CR
CS
MOSE
CT
MOSE
CU
~
CV
CW
ENl2E
CX
fIIOO 2
CY
0002
000
CZ
000
DA
.
2
8-1
C-I
8-1
8-1
8-1
8-1
A-I
A-I
A-I
8-2
B-2
8-2
SHEET L"CATIt1N
4
3
5
8-2
A-3
A-4
A-4
_I
DRFT I DATE
DESCRIPTION
CHICO " "
6
0-3
(>-3
B-3
B-3
B-3
A-3
B-3
8-3
C-2
C-I
8-4
8-4
A-2
A-3
A-2
C-I
C-I
C-I
C-I
C-I
8 -I
8-1
A-I
A-I
REVlSIOII RECORD
ECO
0-4
C-3
0FF - SHEET
REFERENCE
LETTER
08
DO
DE
OF
OH
OG
OJ
OK
OL
OM
ON
DP
OQ
DR
OS
DT
DU
0-3
C-3
B-3
A-4
C-3
C-3
C-4
C-3
C-2
0-3
8-3
8-3
C-3
8-2
0-4
0-4
0-3
0-4
0-3
8-4
A-4
C-3
C-3
A-3
8-4
A-3
8-2
0-2
0-1
0-1
8-1
8-1
A-2
A-2
A-3
A-2
0-3
0-3
C-3
C -2
C-2
0-4
A-3
A-3
8-4
A-4
A-4
C-3
C-3
8-2
C-3
8-4
8-4
C-3
C-3
C-3
0-4
0-4
0-3
8-4
C-3
SIGNALS
2
ENI20
RE 18
MDS1
FIE23
OELTAUG
IO+SHI
SIL
II'CNTE~
CSA
~
M6T
CSO
SHI
SHEET L;CATI N
3
4
5
A-I
8-2
8-4
C-4
C-3
0-3
0-3
8-4
B-4
A-4
0-3
A-4
C-4
C-2
C-I
C-2
C-4
B-1
8-1
C-I
C-I
C-4
C-4
C-4
A-2
I
6
8-3
D~4
0-1
8-4
B-2
0-2
8-3
C-2
8-2
A-4
A-4
8-2
8-4
I
C-4
0-4
0-4
C-3
A-3
C-4
C-3
j
C-2
8-2
0-4
8-3
0-4
A-3
C-4
0-4
C-3
-ft
-
-
• .... "".. ..
'I ••
DETAILED
LOGIC DIAGRAM
DECODER
COOE IDENT
IC
DWG NO
89614900
SHEET
or.
~
7
I
pr
'p.~£OD~
(drawing 89614900) sheet 2
INSTRUCTION REGISTER AND FIRST LEVEL DECODERS
Function
This circuit consists of the instruction register and the first level of decoding
logic.
.
Ineuts
.
SIGNAL
CONNECTOR
PIN
ACTIVE
-,,------- -HDEL
IRCK
HX03
HX04
HX05
Hx06
HX07
Hx08
HX09
HX10
HXll
HX12
HX13
HX14
HX15
CLRIR
.....
NOTE:
I
H
H
HXOO
HXOl
HX02
H
H
H
H
H
H
I
I
l
I
I•
H
H
H
H
H
H
H
H
H
H
!
;
LOCATION
!
SHEET
SQUA~~
FUNCTION
H
I,
!
I
I
II
I
I
I
I
I
I,
!
;
I
P1B20
P1A21
P1B16
P1A16
P1A18
P1A20
P2B19
P2B17
P2A19
P2A18
P1A25
P1A:l3
P1B14
P1B15
P2B05
P2A08
P2B.08
P2A05
P1A31
-..1.---_ ••. -_ .._-...._---._--
fl
field zero from memory
04
04
2
Instruction Register Clock
c4
C4
04
I
I
I
!
I,
I,
>Oata read from memory
i
,
!
I
!•
!
!
I
!;
I
I
j
I,
j
I
II
I
i
Clear Instruction Register
_
.___----l ...".
2
.
04
c4
B4
c4
B4
B4
B4
A4
A4
C2
C2
C2
C2
A4
An alternative notation, emphasizing the significance of the bits of data
read from memory employs the letters L (less s'gnificant) and H (more
significant).
Thus the following pairs are identical:
HXOO - HXOL, HX07 - HX7L, Hx08 ~ HXOH, HX15 - HX7H.
89633300 A
5-215
I
I
I
I•
I
!;
I
I
I
~
:
:
.,
:
\
'.
i
i
!
,!
I
!
,\
1
;
;
(Drawi ng 89614900) sheet 2, cont I d.
DECODER
Oytputs
, ::GNAL
I AC~'VEf.::I:c~or-:~=_~~.-·- FUNCT;-~--. ::~~ATf~~R~'·1
I
'
I
i
Ii
I
I
I
I
I,
i
I
I
I•
I
,I
I
R2
R3
R4
10
H
P1A28
H
I P1A24
H l p 1B28
H
I P1B13
11
12
H
13
14
15
16
H
Tf
L
L
DE[
H
H
H
H
DEL2
Tl
T2
H
T3
T4
H
Of
L
L
L
L
02
03
OD
165
H
H
H
H
I·
P1B05
P1B10
P1A10
P2B26
P2B24
P2B23
P2A23
P1A14
P1A15
P2A06
P2B09
P2A09
P2B06
P1B30
P1B31
P2BOl
P2AOl
P2A22
i
I
I
Fl field of instruction
register
A3
A3
A3
D3
.
Instruction Register bits
A field zero (stored)
see text
F - field outputs
F - field content is
F - field content is 2
F - field content is 3
F - field content is D16
16-15-
2
D3
D3
C3
C3
C3
C3
C3
D3
D2
Cl
Dl
Dl
Dl
Bl
Bl
Bl
Al
B2
-_._-_
------~~------~--------~--------------------.----,~--.----
5-216
'
...........
89633300 A
DECODER
(Drawing 89614900) sheet 2, cont'd.
The instruction register is a 16 bit register.
Its input is the data read from
memory through the memory control board (signals MXOO through MXI5).
The
register is clocked by the tRCK from the timing board and cleared by
CLRIR from the console interface.
The register itself uses two types of components.
The Fl field of the instruction
register are high speed dual D-type flip-flops (u45, U46).
These are
used because the Fl field must be decoded early in the execution of the instruction.
The F field and ~ field are stored in quad D-type flip-flops (U39, U41, U47) like
those used in the ALU registers.
The outputs of the F field and the Fl field are
decoded in two four-to-sixteen decoders (U57, U58) each having sixteen active low
outputs, one for each possible input code.
Four outputs from F-field decoder
(OT, 02, 03, OD) which are active when F = 1, F = 2, F = 3, and F = D respectively,
(hexadecimal notation) are outputs of the Decoder assembly.
The DEL flip-flop, (U60/8), stores the signal MDEL from the memory control assembly
This signal indicates when the delta (~) field is equal to zero.
The flip-flop
is clocked by tRCK and cleared by CLRIR.
The output of this flip-flop is an output
of the assembly, through an inverter, as
(~FO).
orr
The outputs of the instruction register fields are summarized in the following table:
FIELD
89633300
A
....
...............
OUTPUTS
-- ... ...-...-
BITS
~
F
TI, T2, T3, T4
FI
Rl, R2, R3, R4
to through 17
A
'---
_ - --
12
18
60
·· 15
·· II
··
7
5-217
DECODER
(Drawing 89614900) sheet 2, cont'd.
The signal DEL2 is produced by decoding MX data lines.
I ts equa t i on is:
DEL2 = MDELoMX11 MXlOoMX09-MX08 • (Fl=5)-(6=0)
0
It is used by the interrupt logic to sense the inhibit interrupt instruction and
prevent an enter interrupt sequence under certain conditions ~ee Console
Interface sheet 5).
The signal
123 = 17- ib is produced by U38/3
The signal
165 = 16 15 is produced by U38/8.
5-218
0
It is used on the I/O Interface.
89633300 A
...
00
\D
[(Fl~0).(R4.R3).DEl]
= Rl·R3
+ Rl·R3.[(Fl~0).(R4.R3).DEl]
89633300 A
...
oJ
00
U)
0'\
W
W
W
o
o
W9A) P2B13
GOeS)
P2B25
, 4
r
~I
,1'6
P2AI3
(S3
I'a
..,,,...
20
...
"
23
3.4
M
,
,
V'I
I
N
W
PIB24
I"~-T'-
(AIH
I' .. , , PIA26
(AD2
DH>4
REV
DETAILED LOGIC DIAGRAM
DECODER
A
..
DECODER (drawing 89614900) sheet 6
REGISTER CLOCK CONTROLS
Function
This circuit generates the register clock controls WP, WA, WQ, WH, WXLI;
bit bucket signal (BB) and the signal FIE23.
the
The WP, WA, WQ, WH signals are used on the Timing circuit to generate clock
pulses for their respective registers (refer to timing circuit, sheet 3). The
WXLl signal is part of the condition for writing into the X register.
It is
transmitted to the I/O interface board where it generates the signalsWXL, WXH.
r
Inl2uts
o
,
I
:::NAL ...
DBB
BBCK
WRQ
WE
BXI5
HDS'
QI5
CRQ
JiNT
XI5
r~:I ~-~. r·~C~~~:::TORT··H
H
H
L
H
H
H
H
L
H
PI B21
PIA22
PIAl I
PIBI2
P2A28
P2B27
I
PIB28
PIB26
PIA04
PIB22
L
H
H
H
H
H
H
PIAl2
PIB25
PIB04
P2A26
P2B03
P1B29
P2829
FUNCTION
...
........
--~
r
- .
"
.....
LOCATION
SQUARE
.,. -. SHEET6
!
..
~
..•
.
I
I
,•
I
It
.,
i
.
;
I
I
I
I
I
I
6
D4
D4
D4
D4
D4
c4
B4
A4
C2
C2
C2
Outeuts
wrr
BB
WP
WA
WM
WQ
F1E23
5-232
6
II
I
.
(FI-2)+(Fl=3)
I
6
C3
DI
Cl
Bl
Bl
81
Dl
89633300 A
DECODER
Description
(Drawing 89614900) sheet 6, cont'd.
The BB flip-flop (U60/5) stores DBB from the console interface.
This signal
is used during multiply and divide instructions (see Console Interface. sheet 7).
The flip-flop is clocked by the signal BBCK from the Timing assembly. The output
is used on the Decoder assembly and is also transmitted to the I/O interface.
The signal F1E23 = (Fl = 2) +(Fl = 3) is produced by the AND gate Ul3/8.
is used on this assembly and also transmitted to the I/O Interface.
It
The equations of the register clock control are as fo'llows:
WP = JRNI + CSP '+ CRQ'SIL + RNI·~DD·(F=O)·(Fl=l)
where
CRQ is generated in the timing circuit and is active during the first part
of a CPU memory cycle. This is an ~DD cycle in which data is sent from the
CPU to memory.
SIL is active whenever the P register is changed (incremented
or decremented) by one.
WH = CSH + RNI·EVEN·(F=0)·(Fl=8)·10
WQ =
+
+
+
+
+
+
CSQ + HD1·BX1S + HD21·Q1S
HDS·EVEN·(CNTE2 + Tl)
ITR·0i6·15
RNI·EVEN·(F-O)·(Fl=C,D)
RNI·EV~N·(F=E,F)
RNI·EVEN·(F=0)·(Fl=8)·ll
RNI·EVEN·(F=O).(Fl=F).IS·1b·(SHI + ~
WA = CSA + HDS·8DD·(CNTE2 + Tl) + HDS1·~DD·BX1S
+ ITR·EIS·16 + 8P·EVEN· (F=O)· (Fl=2)
+ RNI·EVEN·(F=0)·(Fl=F)·[IS·16·(KO + 10) + 16·00' + SHI)]
+RNI·EVEN·(F=0)·(Fl=8)·12
+ RNI·EVEN·(F=O)·(Fl = 9,A)
+ RNI.EVEN·(F~0)·[T4·T3 + (F=C) + (F=7)·PEF + (F=2,3)·BB]
89633300 A
5-233
DECODER
(Drawing 89614900) sheet 6, cont'd.
WXLI = WRQ·WE + MDSI·000·(X15 + Tl)
+ RNI·eoO·(F=0)·(Fl=2,3,8)
where
- WRQ is produced on the Console Interface and is high during the
second pass (EVEN) of each CPU memory cycle
- WE is produced on the I/O interface and is high during a CPU
memory read cycle.
Thus the term WRQ·WE clocks data read from the memory into the X register.
5-234
89633300
A
.
v
I
27
"
I
IREVI
'00
-'
ECO
IIEVISIOII RECORO
DESCRIPTION
IDRFTI DATE IC"ool UP
\D
'"
~BB
W
W
W
o
o
II
o
J.!!...---
»
.1 ~I 13
UI4
-
...
PIB04
CRQr=:!!--" I
(WP
~
..
~
I(
2.3,4
II
P2A26
4
0'.
2.4~N
I4t
• DU
II UI2
.
14
.'1'1 Y1 IS 12.2222 IItZ.
897711201 Y1 IS IB.3133 IIIl
baTHE ~1LL\lJIR CIRCUIT (SIIEET 2. 1IlIIE 1-2) FnR ASSEJIIlY
11!177'1?OO HAS :
C16 - ~_47 F IS NIT _EClED
P.I~ - 100 0I1'1S IS 1fT "MEnED
C15 - 47PF IS SHORT - CIRCUITED BY JIII'ER WIRE s.
AELEl1EnT IDEnT!.fIER ARE PENDlno. "I' AriD 1149 ARE 7451411.
(-2
0-2
.. I , '
• . . . . . '!>t
" . " ' •• '!a,
"M"
It ....,..
'.' r'.I. •
nIl
,
::t:o
Nil>
DETAILED LOGIC DIAGRAM
TIMING
--~
......
.t.
.a_.......,. ..
•••• , .... , t
.s
TIMING
(drawing 89617000 sheet 2)
OSCILLATOR AND PHASE GENERATOR
Function
The oscillator and phase generator form the basic clock of the CPU and therefore
of the computer.
The basic oscillator frequency is determined by crystal Vl.
This frequency differs in the two versions of the computer as shown in the
table:
,
"e,.
1.
I1._Equ.......i pment
I
AB107
AB108
.!.••. --,~ ....... ~.•• ,.- •... ,-
Memory
Cycle Time
....
..... .....
,.,
,~
...... .
,
...
900 nsec
600 nsec
'
....
.~
.....
_-----.. -_ _---:
.....
:
Basic Clock Frequency
i
.. -i·
.. .. ......
!
....---1
12.222 MHz
18.333 MHz
."
-.l
The oscillator circuit itself is a resonant circuit using the crystal Vl
as the frequency determining element in the base-collector circuit of
transistor Ql;
the simplified circuit diagram shows this clearly.
The
output of the comparator acting on the threshold of the logic circuits in
the feedback path ensure that the oscillator output signal Is a symmetrical
square wave.
Transistor Q2 and the common emitter resistor R13 stabilize
Ql of the oscillator; series stabilizing transistor Q3 isolates the VCC2
supply line from the oscillator signals.
89633300 A
5-249
TIMING
(drawing 89617000, sheet 2, cont'd.)
ISOLATED
SUPPLY
( VCC2)
CI8
C8
RII
RI3
Oscillator Simplified Circuit Diagram
5-250
89633300
A
TIMING
SIGNAL
VI0
G0AQ
i
I
G~MI
I G0M2
;, CSPR
,
-
(Drawing Number 89617000, sheet 2, cont'd.)
ACTIVE
CONNECTOR
l
L
L
PIA06
PIBI6
PI AoB
P1A05
l
P1A04
H
I
!
,
I
I
H
II STPCK
EXCK
i ClREQ
I
I
,
!.. MMRQ
~
".
89633300
P2B22
PIAI9
PI B27
l
SS I
EXT
A
lOCAT 10N·_·
_ . SU.E ~_:_
SQUARE
Program Protect Violation
2
0-4
Hold CPU during 1/0 operation
Hold CPU on busy MelOOry
(bank I)
Hold CPU on bu~y Memory
(bank 2)
2
0-2
2
0-2
2
0-2
Clocks registers to enter data Ii 2
0-2
2
0-2
Set Go
2
B-4
Set Stop
Extended odd CPU cycle
(compare 00D2)
Stop Clock
External Clod
Clear Reque~t
2
0-4
2
C-4
2
B-3
2
A-2
C-2
B-2
from Programmer IS Console
i
i
i SG-I
I
FUNCTION
H
H
i
H
i
H
I.
H
I
......4
PI B07
PlB02
P2Al5
P1B03
...
".
•
; Hem()ry rPfjUest
...............
~
•••••••••
"
."'
_. _ _ • • •
~_ _ ~
I
!,
2
li
_ _ _ _ _ _ _ _ . . . _. _ _ _ _ • _ _ • •
2
_~
__
5-251
TIMING
(drawing 89617000, sheet 2, conti d.)
outouts:
,
i
SIGNAL
ACTIVE
... ,
,
,
,
I
I
I
i
I
I
j
I
PHI
PH2
PH3
PH4
JKCK
GfJCS
EVEN
fJOO
fJ002
fJ002
H
L
I CRQ
CRQ
H
L
iSC
L
H
I
I,
5-252
H
H
H
H
H
H
H
L·
OCK
I
:
i
I
I
:
~
..
!
j
I
!
I
CONNECTOR
FUNCTION
-----.----..-.- ... ............. ....
..,
PIAI5
PIB08
PIA22
PIB25
P2B05
PlB21
P2AI8
P2BI9
PIB22
P2Bli
....- ; .. - .....
,
~~
Phase generator outputs
I
}
PIA03
PIBI9
PIA07
PIB06
TOCJJ:TION
SHEET SQUARE
Phase 5 of Phase generator
Computer running
Even CPU cycle
Odd CPU cycle
I
C-2
C-2
C-2
0-1
C-I
0-3
B-1
.B-I
2
C-3
B-3
2
2
2
2
B-1
B-1
A-I
0-1
.2
Two consecutive odd CPU cycles
CPU cycle request to Memory
Control card
I
2
2
2
2
2
2
2
2
Clock to Memory system
Not connected
I!
I
iI
I
I
I
I
I
.1!
I
j
!
!
I
I
II
,
-.--~.------.j
89633300 A
TIMING (drawing 89617000, sheet 2, cont'd.)
Description
The output at U66/6,8 provides the clock signal to the memory system (0SC);
the output at U48/8 (0SC) drives the phase generator.
The oscillator is stopped by a low on signal STPCK.
clock signal may be connected at EXCK.
In this case an external
The oscillator output drives the five-phase generator (PG).
This consists of
three-stage counter PG1, PG2, PG3 (U17, U18) and associated gates forming a fivestate machine.
The equations of the phase generator outputs are as follows:
PHl = PGl • PG2 • PG3
PH2 = PGl • PG2
PH3 = PGl • PG2
PH4 = PGl • PG2 • V10
PHS = JKCK = PG3
The output waveforms of the oscillator and phase generator are shown below.
Note that the waveforms are the same for the two equipments AB107 and AB108,
the time scale shown applies to the AB108.
To obtain the timing for the AB107
(900 nsec memory cycle), multiply the figures by 1.5.
109
,.--"""
'SC
183.5
218
272.5
TIME (nstc)
I
L~
L:
PHI
H
L
PH2
H
L
PH3
H
L
PH4
H
JICCIC
L
The fifth phase of the clock (JKCK) is the last phase of the CPU cycle.
trailing edge forms the main timing data for all state flip-flops.
89633300 A
Its
5-253
TIMING
(drawing 89617000, sheet 2, cont'd.)
The signal V10 causes the phase generator to jump directly from
PH4 to PHI, avoiding the JKCK clock.
This occurs during program
protect violation (types 2, 3) (see program protect: 1784 Reference
Manual, publication number 89633400, pages 4-9, 4-10, 5-3,6-4, 6-7).
The signal G~AQ stops the phase generator while waiting for the Reply
or Reject in an I/O operation.
The CSPR is active when the computer is not running.
It enables
D-type clocks used for setting bits in registers of Programmer's
Console, while J-K clocks are avoided.
In this circuit it gates
flip-flop PG3.
The signals G'MI and G'M2 are generated by the Memory Control (upper and
lower banks) and are used to hold the CPU on phase five; this occurs in
two cases:
1)
When a CPU Memory Request arrives while the memory is busy with
a D5A request (CPU held just before end of an odd cycle);
2}
When the CPU is wa.iting for data or sending data to the memory
(CPU held just before end of even cycle).
Computer Active/Inactive
The G'C5 flip-flop (U61) indicates whether the computer is running or not;
its output (G'CS) is connected to the CPU INACTIVE indicator on the
programmer's console (computer not running).
The G~CS signal also
stops the computer on phase 1 (PHI) of the phase generator, just after
the beginning of an odd cycle.
The G'CS flip-flop is set by signal SGI and is cleared by S51, both from
the console interface board. The flip-flop is synchronized by the clock
output (~SC); fl ip-flop U61114,15 acts as a synchronizing buffer for the
G'CS flip-flop.
5-254
89633300 A
TIMING
(drawing 89617000, sheet 2, cont'd.)
Even - Odd Circuit
Every CPU cycle is defined as either an even or an odd cycle.
The even and odd fl ip-flops (u4) determine the state of the
machine.
Usually even and odd cycles will alternate so that
one fl ip-fl~p will be set and the other reset on the first
cycle, and both flip-flops will change state on the following
cycle.
In some cases the odd state continues for two successive
cycles. In such a condition a third fl ip-flop, called 0002 (U8)
will be set during the second odd cycle. The 0002 fl ip-flop is
set by the signal EXT from the I/O Interface board and resets
itself after one cycle.
The fl ip-flops EVEN, 000 and 0002 are clocked by JKCK.
The input
equations are as follows:
SET
Fl ip-flop
,
I
EVEN
000
I
8002
I
I
RESET
MPC
i
.J
8002 + EXT
H
SGI
G0CS
H
H
MPC
800'EXT
i
K
II
H
8002 + EXT
8002
Ii
The RQ fl ip-flop (UI7) produces a timing signal for CPU memory requests.
It is set at PH3 on odd CPU cycles and cleared at the end of the cycle.
The output of this flip-flop is multiplied by VIO and by the signal MMRQ
from the I/O Interface to product CRQ which is transmitted to the
Memory Control Card.
89633300
A
5-255
TIMING (drawing 89617000, sheet 2, cont'd.)
A timing diagram for typical. CPU Memory Cycles Is shown below.
Note that the
JKCK signal is extended in the even .' part of the cycle when the CPU is stopped
by the G'MI or G'M2 signals, the timing of the CRQ signal is determined by the
RQ flip-flop.
The timing shown is for the 600 nsec memory cycle. To obtain
the timing for the 900 nsec memory cycle multiply the figures by 1.5.
0
Tim. (nllo) 8'l8
PHI
109
218
327
436
I
I
I
I
16!.8
272.5
n
Sl
548
I
496.8
381.!5
L..-_ _ _ _ _ _
(0)
109
I
I
600
n
~
5'l8
1~3.8
I
I
l
I
----~_j:~
...
I
I
I
I
'--____~n
-+----'n
I
H
L
H
L
I:
I
L--_ _ _
H
L
H
L
H
I
GOMI
I
L
I'
H
I
'DO
--1
L
H
I
EVEN
L
I
CRQ
I
:
I
200
I
I
:~::~s ________~I-~r--lL_______________I~------·r!
DATA FROM
MEMORY
I
I
V.=~=L~ID~_______Ir----------------~
I
DATA TO
MEMORY
~ST.!!~=8:::LE::""______
472.8
I
I
I
I
:
I
I
I
I
I
I
I
f-1- - - - - - - - - - - - - - - '
L
!-..~------
5-256
436
ONE MEMORY CYCLE
(600 n.. o )
J
H
L
H
L
H
L
H
L
,
89633300 A
00
1.0
Vii)
GOM2) PIA05
PIA06
Giiiil eSPR
GeAQ 9
0'\
\N
\N
\N
r
II
o
o
T
0.1
0.1
RI4
vecI ~.....-Yh~
~
r ...
~ (PH4
»
...
~
3
2 PIB22
P2811 (eD02
m"P2822
~~ I
VCC2) PIAOI
.!r:
RIT
IK
r t::'
.
MMRQ)PI803,
PI8t9 (CRQ
~I
---t-I-'\~-IL.II_ - -; - -- - - ~ '"'.,
(iii;
·C2
~I
V1
I
N
V1
......
VCC I )
P2A31
I
C3+ C6
I
I
:1CI
~v
"'" 33,.,.
I
5.6K
I'll.
L ____ _
I
II£>
DETAILED LOGIC DIAGRAM
TIMING
A
TIMING
(Drawing number 89617000, sheet 3)
COUNTER
Function:
The 5-bit binary count down counter is used for the following:
I.
During shift instructions it is used to count the number of
times a word is shifted.
2.
During Multiply/Divide instruction it is used to count the
number of iterations necessary to complete the operation.
In this case it is loaded with the number 10110 2 •
3.
During any memory reference instruction it may be used to
count the number of memory reference cycles needed to
calculate the effective address of the operand.
In this
case it may be loaded with either 00000 2 , 00010 2 , 00100 2 , or
00110 2 •
5-258
89633300 A
TI HI NG
(Drawing number 89617000, sheet 3, cont'd.)
Inputs
.T--.-. - . --; .
SIGNAL
ACTIVE: CONNECTORII
.
PIN
:
l-······· .. · ......FUNCTION
I
LOCATION
. SHEET SQUARE
-+----+----·+-I-----------~--·-·
MPC-
L
[AS]
ENT
L
[T]
Master clear or clear-to-P-reglster,
CPU in interrupt state
JKCK
H
[S]
Clock from phase generator(sheet 2):
10
II ~
12
H
PIBl7
PIB18
P1A17
P1B05
P1B24
P2A10
P2B10
P2B09
[AV]
[AN]
see [V]
H
H
13
14
15
16
H
'Ji'TR
L
PH4
H
F23
H
PG2
AOI
A02
Outputs
NO
CNTE2
N41
H
[W]
H
H
P1A16
P1B20
H
H
H
L
H
Jib
£15
to101
L
L
H
PIB28
P2A09
P2B07
P2Al6
P2Al7
I
I
Least significant bits of
instruction register
I
f
I
fJ
Set ITR flip-flop
Clock phase generator (sheet 2)
Instruction register F=2 or F=3
Second stage of phase G
c4
c4
c4
04
04
03
02
02
A4
A4
I
,
I
., I
II
Least significant bit of counter
Counter conten.t .. 00010 2
Counter content ~ 00001 2
'00'16
EVEN-IS
"' __~._._._.. _. P2B01____... L.'=~::!"'--:=N~3--=N=2"""=-N:l--:-N:O:---A~0~R~_F~2~:3 ... __.___.__ ._.__
89633300 A
3
.-
3
A4
B4
03
04
03
B3
Bl
Bl
Bl
Al
B3
5-259
TIMING
{Drawing number 89617000, sheet 3, cont'd.}
Description
The counter itself is made up of five flip-flops; NO, NI, N2, N3 and N4 (U13, U14,
U12). The most significant bit is N4 and the least significant is NO. All the flipflops are clocked by phase S of the clock (JKCK) and they are cleared by either the
clock signal MPC or by signal ENI.
MPC is active when the CPU receives a
Master Clear signal or a Clear to the P register.
ENI is active when the
CPU goes into an interrupt state.
The counter is loaded through the set (S) input of each flip-flop, as follows:For Shift instructions the counter is loaded with the five least significant
bits of the Instruction register, 14,13,12,11,10.
The setting of the
flip-flops is enabled by the signal JITR·PH4 which is produced at US8/1l.
For Multiply/Divide .instructions ·the counter is loaded with the number 10110 2 •
The flip-flops are set by the signal SP-EVEN-PG2-F23.
The signals SP-EVEN
and PG2 define a specific time period while F23 is active, that is, when the
F field of the instruction register is decoded as F = 2 or F = 3.
For Memory Reference instructions the counter is set by the signals ADI and AD2.
These signals are produced on the Decoder assembly. They determine whether the counter
will be preset to00000 2 , 00010 2 , 00100 2 , or 00110 2 • The setting of the flip-flops
is enabled by the signal RNI-SDD-FEO-PH4, where RNI, SDD and PH4 define a specific
time period and FEO is active when the F field of the instruction register is not
equa I to zero.
Eac;.h fl ip-flop changes state on JKCK when its J and K inputs are high.
This
occurs on th~signal transmission (high-to-low) when the previous flip-flop changes
state.
5-260
Thus the counter counts down.
89633300 A
TIMING
(Drawing number 896l7000, sheet 3, cont'd.)
The least significant fl ip-flop (NO) changes state on every JKCK clock except
when one of the following conditions is true (signal at u45/6):
1.
(Counter
= 0) -RN 112 - (ADl
+ AD2) at U44/8.
This function enables the counter to decrement immediately on
loading the memory reference instruction.
Note that the function N41-ml determines that the (Counter = 0)
and that this situation exists most of the time.
Here N41 = ii4-N3-N2-NT
2.
ADR-(Counter
= 2)[(Fl = 5, 7, D, F)-32KW-Xl5
+ EVEN].
This occurs during multi-level indirect addressing, when the
counter is not decremented until the last level is reached.
3.
J ITR
This occurs when the counter is loaded at the beginning of a
shift instruction.
4.
MDS-EVEN
This occurs during multiply/divide instructions, when the
counter is decremented only on odd cycles.
This occurs during Double Word Shift operations, when the
counter is decremented only on EVEN cycles.
A simplified diagram of the loading and decrementing counter is given on
page 5-264.
89633300 A
5-261
TIMING
(Drawing 89617000, sheet 3, cont'd.)
Three signals derived from the counter are also used on other assemblies of the
CPU.
These are:
Counter content
Connector/pin
Signal
-----,----+-------------" . -t---------------t
CNTE2
P2A9
N41
P2B7
NO
I
I
.....__- -...-.....--.-.-.-,---'.~--..
..
00010 2
I
00000 2 or 00001 2
lit.
-
PIB28
,
,
-. -_.... ...--- ......._--- ... ~
,
.......
....._.. ___
.o~~ n~:be~~
The following signals produced on the Timing assembly are used by the Decoder:
I.
MOl, (at UJO/8), is active during multiply/divide instructions
when the counter is at 00001 2
2.
m = iDD + 1b
iT6 and EI5 are used during Shift Instructions.
5-262
89633300
A
.
....
AD2) PIB2D
00
\.D
0'\
I
5®-:-:=
._ " PIBIT
•
11> PIBla
13) PIB05 ,
14" PlB24
\10.1
\10.1
\10.1
0
0
»
II
'" 11111
'~
II I
I I
~
22
ADI) PIAI6
15
-II
I
/1'1
1
17
21
5~J~----------~-t~===--,
pia;' ,'(
5,6(AN)
RI)
I I
...... ,..
4,5@~
8
~
.I1T1f) .
P2809
I!!~
P2AIO
pgBIO
16'
V'I
I
N
0'\
\10.1
,
!I
' I
DETAILED LOGIC DIAGRAM
TIMING
P2A17 (EI!!
TIMING
i
I
•
!
i
·
~
0;
•
I
i
i
!II
j
IfEil.
.....
..! ,
8
_
~
i. i
!I
i
5-264
89633300 A
(Drawing number 89617000, sheet 4)
TIM I NG
INTERRUPT TIMING, V REGISTER CONTROL LOGIC
Function:
This circuit includes timing signals which control the transition into the
interrupt state and logic for controlling the V register in the ALU.
Inputs
FUNCT ION _____.. _........_... .
IN32
JENI
KEN 11
R2
R3
R4
[AC]
[AD]
[AS]
[AK]
{Fl=4}+(Fl=C}
(Fl=6)+ (FI=E)
Sets ENI
Resets ENI
Bit 9 of IR
Bit 10 of I R
Bit 11 of IR
Programmer's Console selects
V-register
See sheet 5
See sheet 3
See sheet 5
RNI12 (AOI+A02) o'NO oN"loN2 o'N3 oN4
[AP]
NO oifl oN2 oN3 oN4 = NOoN41
H
L
PIA20
P2B12
P2A28
P2Bl8
PlB29
H
H
H
CSV
L
32KW
N41
MPC
H
H
L
eOD
NO
L
,: [K], [R]
H
[A]
eOO02
H
[V]
I
GeCS
I AOR
H
[L]
H
[V]
1m
l
[AY]
ep2
H
[AQ]
RNI
EVEN
H:
[xl
H
[N]
•
89633300 A
0
See sheet 2
See sheet 3
N41 oNO
[AP]
t
I
_._ ... _._...!..--. .... ....
LOCATION
S UARE
4
03
04
c4
c4
B4
C4
04
04
02
.~J:iEET
See sheet 5
See sheet 5
See sheet 2
.... .. ........._--------_ ..... ..
!
~~.,--
~
:
,
-
4
5-265
TIMING
(Drawing number 89617000, Sheet 4, cont'd.)
Outputs
r--'--------T-"
i SIGNAL
ENI
ENI03
H
ENI02
ENI20
H
L
L
L
H
H
L
~P2'
I ::~UG
I
ADY
,--,-,.,~.--,,-
P2Bl5
P2B16
P2A06
P2A21
P2A20
P2A24
P1A3.o
P2Al4
P1A24
H
ENI2E
;
·CONNECTOR
PIN
ACTIVE
-.-
• • • •_ _ , _ _ _ _ _
, ••••
~~,
• • _ . __ • • • • • •
~-
. . . . . . ._
I
FUNCTION
Enter interrupt
LOCATION
SQUARE:
i SHEET
----~----------~;
4
ENI·INf2·G~CS
EN I ·~DD2
ENI2·~DD
ENI2·EVEN
. ~P2·~DD
Controls output of Y register
-lor -0 to Augend gates
Add Y register
•
4
A3
A3
B3
A2
Bl
01
C1
B1
01
A
Descri pt ion
The Enter Interrupt Sequence is initiated by the signal JENI from the Console
Interface card.
This signal causes the ENI flip-flop (U7/15) to be set.
The
flip-flop is clocked by phase 5 of the timing chain, JKCK (see Timing, sheet 2)
and is reset by MPC (see Timing,sheet 5).
The output of the flip-flop is at
u24/2.
At the end of time ENI ·~DD2 the ENI2 flip-flop (U7/11) is set.
This
flip-flop is also clocked by JKCK and cleared by MPC.
The output of the ENI2
flip-flop is ANDed with EVEN and ~DD (see Timing, sheet 2) to produce ENI2E and
ENI20 respectively.
ENI20 is used to reset the ENI and ENI2 flip-flops.
This
is the normal end of the enter interrupt sequence and is followed by the setting
of the RNI flip-flop (see Timing, sheet 5).
The Enter Interrupt Sequence may be aborted prematurely by the signal KENII
which resets the ENI flip-flop and prevents the RNI flip-flop from resetting.
5-266
89633300 A
(Drawing number 89617000, sheet 4, cont'd.)
TIMING
Other signals produced by this logic circuit are:
ENi'tn= EN I •ENi1f1 •Gee S
and
= ENI02·EVEN = ENI2E
SGL
(at P2A14)
SGL is an ALU control.
Timing diagram for this logic circuit is shown below.
ENI Completed
ENI Aborted
"00
____~r-l~__________
'002
RNI
----1
__ _
-i'L.-.._ _ _ _.....
____~r_l~__________
-----------,.L ---NOTE __
~~----
ENI
ENr02
ENI03
~~----
~
NOTE:
RNI mayor may not be active at this time.
ALU Y register control
The signal YTAUG is produced in this section.
This signal allows the output
of the Y register to be enabled through the augend gates to the adder in the
ALU circuit.
The logic equation of this signal is as follows:
YTAUG
= CSY + f}P20 + ADY
where
ADY = ADR·Gf}CS·Nl·Rl.(R4+R3)·NO.INO·Nt·N4l·(IN4+IN32·32KW.X15)
89633300
A
5-267
TIMING
(Drawing number 89617000, sheet 4, cont'd.)
The first two terms of AOY are G(lJCS (see Timing, sheet 2) and ADR (see Timing,
sheet 5).
This restricts the YTAUG to situations where the computer is in the
addressing state, and is running.
The remaining terms of ADY define specific cycles of the addressing state where
the YTAUG signal is not active.
The signals NO, Nol, and N4, are produced by
the counter (see Timing, sheet 3). The signals Rl, R3 and R4 are equivalent to
bits 08, 10, and 11 respectively of the instruction register. Signals INO, IN32,
and IN41 are produced on the I/O Interface and are decoded from the FI field of
the instruction register.
The signal XIS is the most significant bit of the
X register which is stored in a flip-flop (see Timing, sheet 6); the signal
32KW is connected to the 65K/32K mode switch on the programmer's console. In
addition, the terms CSY and (lJP20 produce a YTAUG signal when the Y register is
selected by pushbutton on the Programmer's
signal is active.
~onsole
or when the (lJP20 timing
The signal WY at the output of U24/12 is the decoded condition for writing in
the Y register.
It is transmitted to the Timing circuit {sheet 6} where it
is ANDed with a clock signal to produce the Y register clock.
The logic
equation of this signal is:
WY
= EAO
+ CSY + RNI·(lJDO + (lJDO·(COUNTER ~ 0) + (COUNTER
= 1)·R2
The signal EAD (End of Address or End of effective Address) is generated in the
Timing circuit (sheet 5).
It is active on the last CPU cycle of the addressing
sequence for the memory reference instruction.
CSY is active when the computer
is stopped and the Y register is selected on the programmer's console.
The signal RNI.(lJDD is active during the first CPU cycle of each instruction.
The signal Rl is active when the counter is at I and bit 9 of the instruction
register is such that Fl = 2, 3, 4, 7, A, B, E, or F.
~-268
89633300 A
..
00
\0
'"
W
W
W
R4>PZBlI
,
27
__ r--:'\
-,PI12'
CSy
0
0
»
AS> PZA21
W(;;fv
~
l..!!!!.J
PIA24
PIAZO
1P:!I!.v......,.._ __
PZA20
6 P2AI4
~atI''''''"---
II)
iii
~
,
V'I
I
N
'"
\0
m!
ENI
(ENl2E
multiply/divide
•
I
ins truct ions
6
fI
I
I
~
Bucket clock
Timing for sh I ft
F =0
01
1
~
Register clocks
I
I
I
!
.)
• • • ~n~ ...... . . . . . -• •
-
Cl
Cl
Cl
03
03
c4
A3
B3
03
6
Bl
Bl
AI
AI
AI
AI
AI
B3
B3
B3
89633300 A
TIMING
(drawing 89617000, sheet 6, cont'd.)
Description
Signals MOS and MOSI are active during multiply/divide instructions.
During the
~P.EVEN
cycle of multiply/divide,the counter (Timing, sheet 4)
is loaded with 101102 (22 10 ). On the next cycle, the 0P stat~ is not active,
the counter decrements to 21 10 and the signal M021 defines the timing.
M02l is the J-input of the MOSI fl ip-flop.
MOSI is active for the
following two cycles and its K input is connected to the function
MOSI -000.
The MOS fl ip-flop becomes active immediately after MOSI
and remains active for 34 cycles.
The K input is connected to the
funct ion CNTE2 -000 where CNTE2 means "coun ter equa Is 210".
The M021 signal is also combined with the fourth clock phase, signal PH4,
to produce BBCK which is a clock to the bit bucket on the decoder card.
The bit bucket is used to restore the sign of the result in multiply/
divide instructions.
The ITR fl ip-flop (U22) is active during shift instructions.
Its J and K
inputs are produced on the I/O Interface board. The fl ip-flops MOSI,
,
MOS and ITR are all clocked by the fifth phase clock signal JKCK and
reset by MPC.
The X15 fl ip-flop (U64) always holds the most significant bIt of the
X register except during multiply/divide.
Its 0 input is XSEL7M which
is the input to the X register taken from the ALU assembly.
Its clock is
PG3-WXM-MOSI
The FEO flip-flop (U64) stores the signal OFEO which is active when the
F field of a word read from the memory is equal to zero.
The predecoding
for OFEO is on the Memory Control assembly. The clock to this fl ip-flop is:
IRCK
89633300
A
= RNI-EVEN-PG3
5-279
TIMING
(drawing 89617000, sheet 6, cont'd~)
JRCK is also used to clock the instruction register. The flip-flop
is set by the signal ClRIR which clears the instruction register.
Thus this flip-flop indicates whether the F field of the instruction
register is zero.
Register Clocks
Clock signals for the registers in the AlU are produced in this section.
The clock signals of the various registers are produced by multiplying JKCK
~hase
5 of the clock) (Timing, sheet 2) with the appropriate signals (W):
Regi ster
Q.
P
Y
M
A
Signals for
clock generation
WQ.
WP
WY
WM
WA WXM
X
The signal AMCK which clocks the roost sign i ficant 8 bits of the
_Aceg istercan bebloc-k.-ed by the CiIT' signa 1. Th i si s used by peripheral
devices which transfer only 8 bits of data on each input on the A/Q. channel.
The signal W9A is transmitted to the decoder card AlU/shifter.
equation is:
W9A
5-280
Its
= RNI·EVEN + M021 + MD1 +.MOSI + GeCS
89633300 A
V1
I
~
00
___
P_2~iiil
DETAILED LOGIC DIAGRAM
TIMING
"Pages 5-282 to 5-290 are unassigned."
5-282/5-290
89633300 A
INPUT/OUTPUT (I/O) INTERFACE
The I/O Interface circuits are accommodated on a single 50-PAK printed
wiring board. The logic circuit diagram of the unit is given in drawing
number 89619700, sheets 1-10.
The I/O Interface circuits generate control signals for the main inputo.utput (A/Q) channel and for the circuits commanding the peripheral controllers.
It also generates control signals for the CPU. This page lists the
functional "locks accommodated on this board. The circuits and signals
are described in detail on pages facing the corresponding sheets of the
circuit diagram.
MAIN FUNCTIONAL BLOCKS
Des i gnat ion
Shown on Sheet
.. - .'-"'-- -- .--------------------.--.... - - - -...- - - - - -.---.-----l....
A/Q channel control
2
Memory request logic
Index (i) address and write enable cont~ols
3
4
Decoder for FI field
Augend controls and X register clock control
5
6
Controls for shifter and A/Q channel direction
7
Main sequence flip-flop controls
8
Overflow logic
Enable-Interrupt logic
9
L_______
89633300
A
10
._---/
5-291
.
V'I
'I
N
I
\,0
N
SHEET
REFERENCE LETTER
2
A
•
C-4
0- 3
o
E
C- 3
C- 3
F
G
8-3
8-2
J
K
A-2
L
8-1
M
8-1
3
4
SHEET
II
3
4 5 6 7 8 9 I~" REV
All
8
9
C-3
C-3
0-2
8 -4
C-2
8 -3
8-4
0-4
A-4
0-2
e.
DESCRIPTION
_T illiTE
REDRAWN PER CDC ITO
R.I. Uev"
L.
~,/...(
...... 1_ <.7l
"""
12
._5
I..,~
.,,~_ N
__
••ac.,.""
_....
AIPIT. . . . P
~
oc c.oc 6ZJ; __ ..c'"- ... ,,_.
7
6
fCO
04 CK lI23
OCATION
0-1
C-4
A-2
2
04 04 04
It A It It It It It II- II It
SHEET REFERENCE
".oFF
flFF
C-2
C-2
;i ei. "';C "".-
10
0'
C-3
C-3
/I
41611 . . . . ZC
"to
~
CHIlD APP
.."
+ '....
-""I
11_
I~
_. '-..... 1".,.
1"""'•. __ ",1....
7400.
~
4DD1ID
CIOOS"
.'0. 'wI(
uf./11#
ItELlUSII]) ClASS II-
,....,
1"_
8-2
1S781~otI fttI.C/
~ ~'P ~1L
I...?"
f-
C -3
8-3
II
~ 1
C-2
8-3
C-2
8-3
N
0-4
Q
0-4
C-I
C-2
8-1
R
0-4
0-3
S
T
U
0-4
C-4
8-4
5V1
C-I
V
C-I
W
X
8-4
C-4
I
33MFW
C-I
Y
C-3
8-1
Z
0-3
0-2
AA
AI
I-I
8-3
A-3
AD
C-I
0-1
0-4
AG
AJ
C-Z
C-Z
A-Z
AK
AL
8-4
8-2
Q
C~
AN
0-2
0- 2
AQ
0-2
C-J
AR
AS
C-I
A-2
1-4
I-
'Vee
C2"C9
10V
C-3
0-4
I
C - I .
CI
A -3
68.F
:-
Lo
I"
A-4
C-4
RI
IK
""
+IIVI
0-2
®
A-3
C -2
C-Z
AE
N_TES:
II
0-5
C-4
A:'5
(:-4
1-4
C-5
C-4
C-4
II ALL RESIIT6RI AJI£ 0.25 WATT II ..
C-4
C-4
2) THIS SHEET IS C6NTINUEO
'I
SHEET II.
!I
DETAILED LOGIC DIAGRAM
1/0 INTERFACE
II
C-t
~2
C-4
C-2
C-2
C-4
0-4
D-4
C-4
A-4
C-4
UNLESS OTt£RWlSE SPECIFED
O'IIIENSIONAAEININCHtS
00
O o I!!
\,0
0'\
o
W
W
W
~
0
!
o
o
It) 0)
to
.
-
1'0
>- :it
c( c(
,.LA"
!l"
iii
~ ~ i5
.
tIlN
C~
AT
AU
»
REVISION RECORD
SH£ET RE\IISION STATUS
~
:!l
TOLE''''''''
2 PLACE
ANGLES
±
±
DDNOTSCALE DRAWING
MATERIAL
FI RST USED ON
"'mMn"
OWN
CHKD
N1 A
ENGR
NI A
A....
MFG
FINISH
-
ElIlT COMPUTERS U'D
• '.'111.""
TITLE
I'
A8107-A
Ir84I1B~A
..... IU3
RACHEL
l/j~trt;:",,, iik.t. )1
~r/o
,J>
"'."H
Il"',"
HI/litf j.
Q.A 1.1,-.- I',:
'II!J.
_
-I'CODE IDENT
DI'.O
.f""':"
3.17.75"
,.,
SCALE
1
II
C
..
I,
ORA...G NO
89619700
SHEET I
OF II
..
-
~
00
\D
OFF
.
I
111£"
IIEYIIIOfI RECORD
ECO
IDRfT DATE ICHKDI_
DESCRIPTION
SHEET REFERENCE
(T\
OFF SHEET
II £FEll ENCE LET TEll
W
W
W
o
o
AV
AW
AX
AY
AZ
BA
81
10
IE
IF
IG
»
SHEET LOCATION
Z
I
C-4
A-I
8-4
·
•
BO
III
IS
IT
8U
IV
IW
IX
IY
,
I
OH
7
•
I
C-4
10
I
8-1
0-3
C-2
0-3
A-3
C-4
C-2
0-2
C-4
C-4
A-4
C-3
1-3
0-2
O-Z
C-I
1-4
C-4
C-I
C-4
I
C-4
I-I
A-I
D-2
A-I
B-3
0-1
C-Z
8-2
0-2
C-I
C-2
1-3
C-3
1-2
B- 4
C-5
A-2
1-3
B-4
0-4
1-2
B-3
0-3
1-4
A-2
8-4
0-2
0-4
0-4
C- 2
~
1-4
C-2
I
~-4
C-3
0-2
C-2
C-3
D-I
OS
EA
•
A-3
IZ
OA
01
DO
DE
DB
·
5
C-Z
...
IK
IL
1M
4
1-4
1-4
1-4
A-4
C-4
1-4
C-4
1-3
8-2
0-3
0-3
O-Z
1-4
C-4
DP
J
IElIlT COMPUTERS l 1!1
VI
...... "."..
I
N
1.0
W
-
..
11'1111iI'II'td~ll
DETAILED LOGIC DIAGRAM
110 INTERFACE
-
CODE IDEN]
C
DWG NO
89619700
SHEET II
~
I
l~'
INPUT/OUTPUT (I/O) INTERFACE
(drawing 89619700, sheet 2)
A/Q CHANNEL CONTROL
Function
This circuit controls the A/Q data channel. The A/Q data channel is used
to transfer data, controller status, or controller instructions between a
peripheral controller in the computer and the A register. The Q register
defines the address of the peripheral controller.
This circuit transmits two control signals (READ, WRITE) to the peripheral
controllers via the A/Q channel bus and receives one' of two responses
(REPLY, REJECT) from the controller addressed.
Inputs
5i
gna~-;:t~:;l_~~~~~c~~~~
P4M
MC
REJECT
REPLY
RNI
JKCK
H
L
L
~
I
I
i
I
H
P2A21
P2A23
P2A24
C4
B4
P2B25
PtB20
P2A19
2
B4
P2A22
2
B2
Cl
Outputs
RP
TRJ
1RE"Ai>
I WRITE
L~
5-294
H
I
!
L
L
L
L
I
I'
.•.... - .. '.,-,
P2A25
1
P2B02
P2BOt
P2A26
-.-- .--_._.,._ .......
!
!
-.-.~-~,--
-- --
--.- - .•.. _............ _... ........ -..
;
2
Bl
Bl
Al
I
I
J!
------.----
---.---~....
89633300 A
(I/O) INTERFACE
(drawing number 896l9700,sheet 2 continued)
Description
The A/Q input/output sequence is initiated by the signal RNlll.FlE23·JKCK
(U2/l2).
This clears the A/Q flip-flop (Ul/10) and clears the reply latch
(U2/6 , U2/8).
The output of the A/Q flip-flop gates the signal P4M through U3/8 to the
count-up of the internal reject counter (U19).
up/down counter with a carry output.
This is a four-digit binary
P4M is a clock signal generated on
~sec
the memory control board with a repetition rate of approximately 0.88
for the ABl08, 1.30
~sec
for the AB107.
The output of the A/Q fl ip-flop is ANDed with OP·EVEN·JKCK·FEO to generate
G0AQ at U51/8.
~P·EVEN
Its function is to stop the basic timing chain in the
state, with phase 4 and JKCK of the phase generator both high
(see Timing sheet 2).
(U20/3, U20/6).
G0AQ is also used to set the READ/WRITE latch
The output of the latch gates the output buffer-gates
(U27/3, U27/ll) to generate either a READ or a WRITE signal according to
the code (Rl through R4) present on decoder U58 (refer to sheet 5).
The
READ, WRITE signals control the direction of data flow in the A/Q channel.
The read/write latch (U20/3) gates the response signal (REPLY or REJECT) from
the peripheral controller in reply to the signal READ or WRITE.
I
The timing chain remains stopped until a REPLY or REJECT is received from the
channel. If no REPLY or REJECT is received within 12.8~sec in equipment
AB108 (19.2~sec in equipment AB107) of the Read or Write signal, an Internal
Reject signal (IRJ) is generated at the carry output of the internal reject
counter (P2A25).
89633300 E
5-295
(I/O) INTERFACE
(drawing number 89619700, sheet 2, continued)
IRJ is transmitted to the Decoder and is also used to preset the A/Q flip-flop
and clear the reply latch. The signal G0AQ goes high, allowing the timing
chain to continue running. As the timing chain continues, the read/write latch
is cleared by G0CS·0DD and both READ and WRITEgo high. The computer increments
the P register ac~ording to the state of signals IRJ and RP (both sent to the
decoder). In the next CPU cycle, the internal reject counter (U19) is cleared
by RNI·WRQ. The timing diagram of the sequence is shown below.
Ilf
a REJECT signal is received before the internal reject (IRJ) is generated,
then REJECT resets reply latch U2, causing signal RP to go low. REJECT is also
gated through U3/6 to set the A/Q flip-flop, which is clocked by P4M. Therefore, the input/output sequence terminates synchronously, as described above.
Ilf a REPLY signal is received before the internal reject (IRJ) is generated,
then REPLY is gated through U3/6 to set the A/Q flip-flop. The input/output
sequence terminates as described above.
...
I
00
\D
0\.
\,Ill
W
W
0
0
1I
1'411 )
PUll
~"'.IO
):0IIC)
PZAU
146
11 U51
t'1
II~
51
tl
. .1
INTE RNAL REJECT ctlUHTER
j X·Yoj I .... t-IJ.
!
PIAU (fiiJ
CARRY
veei
,.
R4
180
PIAU
iiiTECT~
_ _... PII2I
~.
REPLY
JKCIC
... PZAIt
vee
In
55
110
f
R2
110
1'1801 (iiiiD
RNI) 1'1820
It
REPLY F.F.
5~
u
1 1
1'2101 ';iiii1i
1'113) 1'2120
PUI6 (iiii
V'1
I
N
\D
.....
.......
V'1
I
N
\D
00
\
DETAILED LOGIC DIAGRAM
110 INTERFACE
INPUT/OUTPUT (I/O) INTERFACE (drawing number 89619700, sheet 3)
MEMORY REQUEST LOGIC
Function
This circuit generates the memory request signal (MMRQ) to initiate the
CPU memory cycle by way of the signal CRQ on the Timing assembly.
C4
04
04
04
3
A4
A4
02
3
Cl
RNI·'OO· (F"O)
RN I ·eoo· (F=O)
Outputs
MMRQ
FIEF
H
H
P1A07
PI018
I
Memory Request
,_ _ _ • _ _ • • •
89633300 A
~_ ."<~ ~
• • •_ _
••
01
5,-299
(I/O) INTERFACE
(drawing number 89619700, sheet 3, cont'd.)
Oescr ipt ion'
The MMRQ signal is generated by high speed gates (series 74H) to conform
to the constraints of the memory access time. The equation of the signal
is as fo 11 ows :
MMRQ = AOR [N41-(F=2,3,8,9,A,B,C,E,F)-(Fl=1,2,3)-OEL]
+ (lJP-(lJOO
+ (lJ002
+ (lJP2-(lJOO
+ ENI2-(lJOO
+ RNI-(lJOO-(F ~ O)-(Fl=A).(~ ~ 0)
+ RNI-(lJOO-(F = O)-(FIEF)·SHI
+ (F=O)-Fl = 1,2,3,E,F-ENI3
5-300
89633300 A
00
\D
~
\oJ
\oJ
\oJ
0
0
J
iPii
.001
»
~7
PI
_
N 141H 10
iifii )"~--
1141
" )Pt8l4
II
f-!!!!-l J
\:J-'-
IIII
5.8~~
LI I
.: I
;
1.7.8 <:.:7
_PlACe
1r::El
I ••, .. 12
:1113H
•
5.1
I!
.='(-
•
8
.-.-.
II I
_>PI8I2
1.8.1~
PIEU)PtAZO
..
~
5r:r
UID
110
~
,... _,
.,1,.
•
5.7.1"'"
81C1)PIA.
~)n_A08~
iiiiiii >'1104
10
"'''~al
13
________ I
1'10
r::::J'..
"1
13
1U3D1
lol •• ;u t-..8
I I
,
Pta",
~J)4.6.'
,
(E)2,6.8.10
~
\n
I
\oJ
o
DETAILED LOGIC DIAGRAM
110 INTERFACE
f1EF
INPUT/OUTPUT (I/O) INTERFACE (drawing number 89619700, sheet 4)
INDEX (i) ADDRESS AND WRITE ENABLE CONTROLS
Funct ion
This circuit generates control signals for an index (i) address operation
and Write Enable involving:
a.
the second index register (location 00FF 16 )
b.
the memory write cycle (signals WE, SPBM, CPBM, 'PST)
(I/O) INTERFACE
(drawing number 89619700, sheet 4, cont'd.)
Descript ion
The signal CRI is defined by:
m
= ADRoCNTE2 o (Fl = 5,7,D,F)oX15
+ [ADRoCNTE2 oDEL +
0
32KW
RNlo0DDo(F~0)oDEL]o[Fl
= 1,3,9,B]
Itis used on the Memory Address board to force the current memory reference
to be made to the second index register (memory location 00FF 16 ) rather than
the address specified by the ALU lines (indirect addressing).
The output of the index flip-flop (RIND) controls the INDEX indicator on the
Programmer's Console. It is active during the second pass of a CPU memory
cycle in which the index location is addressed.
The signal INDIND = ADRoRIND controls the INDIRECT ADDRESS indicator on the
programmer's console. It is also used on the Console Interface board to
determine the timing in which an interrupt is accepted (see JENI, console
interface).
The signal WE is active when a CPU memory write cycle must be performed.
It acts on circuits on the memory control board. Its equation is:
-WE = ENTER +
+ 'P·(F
E~12oEVEN
= ~.5,6.7.D)
+ ,p·G'CSo'DDoFEOoDEL·(FI
89633300 A
= 6,7)
5-)03
(I/O)
INTERFACE
(drawing number 89619700, sheet 4, cont'd.)
The signals 'S'P'BM and C'P'iiM' .i~dicate that the computer is executing a "set
protect b'it" or "clear protect bit" instruction respectively. These signals
are used on the memory address card to determine the polarity of the protect
bit written back in the specified location. Their equations are as follows:
SPBM = SP-G0CS-000-FEO-OEL-(FI
= 6}
CPBM
= 7}
=
0P-G0CS-000-FEO-OEL-(FI
The signal 0PST is used by the breakpoint stop logic on the Programmer's
Console to allow the computer to be stopped when executing a memory write
cycle to a specified location. Its equation is:
0PST =
5-304
ENTER + ENi2E + 0P-(F = 4,5,6,7,0)
89633300 A
.
~
&.
&
0'
w
w
w
o
o
)10
,..6""
'F'...LI_ _ _ _--'-'PZAOI
(RIND
(I.IND
PIAl2 (51
CiiTi'i) ......,
.PC) .....
PIAI4
Ta)
PIAII
1.-:""'1
I
(1PsT
T4' PlIII
roo
I{!!
d ) NIO
ENTER) pt.
-)
....
,
,
"I
I "I
. """"
I
,.815
I !I
VI
I
W
o
VI
......
VI
I
W
o
0'
DETAILED LOGIC DIAGRAM
I/O INTERFACE
.
(iii
INPUT/OUTPUT (I/O) INTERFACE
(drawing number 89619700, sheet 5)
DECODER FOR Fl FIELD
Function
This circuit decodes the Fl field of the instrwction register on the Decoder
assembly (Rl, R2, R3, R4), and generates control signals using these
decoded signals.
Ineuts
.......... -....._.- ...._.....
-~
Signal
R4
R3
R2
RI
ENi1i
Outeuts
IE
INR
INO
IN32
IN41
SLS
SHAOR
X\C
89633300 A
,"'-
I ' .., ......... _...
---'-'.-
_-
Location
Connector/
Sheet Square
Active
Function
Pin
,._-_._- •.. -.... -.--. _....__... _..... - _. . _-------- -"-"---""'- - ... __ ._...
04
H
PlB22
5
H
PlBl9
04
FI field
H
PlA23
04
PlA24
04
H
'5
B4
Enter Interrupt Indicato
PlAIa
L
__
H
H
H
H
H
PIA22
PIB23
PlB27
PlB29
PlA30
PlB24
P2Al6
L
PIA21
H
H
_.
"
'"
5
Selective Stop
Short Address
Q. channel control
(see sheet 7)
5
01
01
CI
Cl
81
BI
Al
CI
5-307
(I/O)
INTERFACE
(drawing nl,lmber 89619700, sheet 5, cont'd.)
Descri pt ion
The decoder's (U5R) 16 active-low outputs correspond to the instruction
register Fl field codes (RI, R2, R3, R4). The following signals are
generated with their aid and are transmitted to other boards:
The signal SHADR is active during memory reference instructions in which one
CPU cycle (RNI-O) is enough to calculate the effective address (and therefore
the ADR timing is not needed). It is used on this assembly as well as the
Timing assembly to produce the control signals for the RNI and ADR flip-flops.
Its equation is:
SHADR = (FI = 0) + DE[-(FI = 2,8)
The signal SLS is sent to the programmer's console and stops the computer
if the SELECTIVE STOP switch is set. Its equation is:
SLS
= RN I- EVEN- (F = 0) - (Fl
= 0) -
ENi1i"
The signa I ENi1i' is produced on the Console I nterface and is used to prevent
the first cycle after an enter-interrupt from being interpreted as a
selective stop. It is used here to generate SLS.
Other signals are:
IE = (Fl = E)
INR = FEO-(Fl - 8}
INO - (Fl - 2,6,E)
IN32 = (FI = 6,E)
IN41 - (FI
5-308
= 4,c)
89633300 A
....
16
00
\.0
0\
24
\N
\N
\N
3,8
0
0
PIA22 (IE
»
PII22
114) Plllil
11:\) PlA23
8
PIB23 (INR
112~
III PI,
I {a;
PIB27 (INO
4
,..
8
PIA21
(.iQc
c
41
20. 1
ilL
PI1I29 (IN 32
'11.30 (IN41
PI824 (SLS
iii')
PIAIO
2~
51
JB
1-
PZAII(SHADR
"
\1'1
I
W
o
\.0
DETAILED LOGIC
110 INTERFACE
DIAGRAM
INPUT/OUTPUT (I/O) INTERFACE
(drawing number 89619700, sheet 6)
AUGEND CONTROLS AND X REGISTER CLOCK CONTROL
Function
This circuit generates:
a.
augend controls not included on the Decoder assembly (DELTAUG, SE, 1M, SFL)
b.
X register clock controls (WXL t WXM)
Inputs
Signal
Connector/
Pin
Active
WRQ
H
PIEI
SKT
H
ffi'
lMT
L
L
MDS2
H
H
~
j
P2Al0
PIA27
P2A30
PtA)1
PtB28
PtBl3
Function
Locat ion
Sheet Square
._-
6
04
c4
c4
B3
B3
02
6
C3
C3
01
Cl
Cl
Bl
Bl
Al
6
FI - I
Skip condition
Outputs
XEZ
DELTAUG
C'lRQ
WXH
WXL
SE
SIH
SFL
5-310
H
L
.L
H
H
H
H
H
P2A05
P2B30
(X - 0)
Pl807
P2A07
P2At5
P2A04
P2A09
P2B05 .
Clear Q register
}x Register clock controls
89633300 A
( I/O) INTERFACE
(drawing number 89619700, sheet 6, cont'd.)
Oescription
The augend gate controls are described together wi th the augend gates
(ALU circuit, sheets 4,5). Their equations are as follows:
OELTAUG
= RNI·000·0D02·(F = O)·(FI-
l)·SKT
This function is active during skip instructions when the skip condition
(S KT) i s me t •
= ENI2·EVEN
SE
+ RNI·SOO·(F
= 0)·FIE23
+ RNI·SOO.(F ~ 0).0E[.R4
1M - 17 + ENI2·EVEN
SF'[ - ENI2·EVEN·FE'O·OEL
The X register clock control signals are used on the Timing assembly to produce
clocks for the two ALU boards (WXL is associated with the ALU LSB, WXM with
the ALU MSB). Their equations are as follows:
WXL - CSX + WXLl + EAO + ENI3
WXM - WXL + RNI·SOO·(F = O)·[(FI = E) + R4·17]
where
WXLI comes from decoder (sheet 7)
EAO is produced on the timing card (see Timing, sheet 4)
and is active during the last cycle of the address calculation.
The signal XEZ is transmitted to the ALU circuit and controls the X regi.ster
selector. When this signal is high, the X register receives memory data from
the Memory Control board; when it is low, the X register receives data from
the shifter.. The equation is as follows:
XEZ
89633300 A
= WRQ
+ RNI·SOO.(F
= O).(Fl = 0,1,4,5,8,9,A,C,O)
5-311
(I/O)
INTERFACE (drawing number 89619700, sheet 6, cont'd.)
The following signals are decoded from the Fl field of the instruction
reg i s ter:
F1EI= (Fl = 1), used in Console Interface circuit
FIEF = Rl·R2·R3·R4, used in timing circuit
The signal
CIRQ
is transmitted to the ALU assemblies to clear the Q register.
Its equation is:
-
-
CLRQ = MC + MDS2·MDS·EVEN-03
It is act i ve dur i ng Master C1ea r and when the computer is runn i ng; it
clears the Q register at the beginning of the multiply instruction
execution.
5-312
89633300
A
.
,
~
00
\D
C7'
\.AI
\.AI
\.AI
o
o
40
WRQ')P2A1O
»
8
MDSI
')!!!!!
II
PII07 <: CLiiQ
5.11
'I'
'Ii'
rSRYR(
XIZ
FIEI) PlA2T
I
PZAOT( WXM
3.5~
P"
SKT,)P2AI0
P2110(GEL TAUG
,
•
PZAII( WXL
10•• I212"
I I
j,!1!-_ _ _ _ __
PlAII
,$PII2I
5.7.8
US7
36
1I{81')
,
P~"--I-
;II
~
- - - - ,'2!!Q4 4
II
'1111(.,
I
'1114 (KRIll I
•
I (lit
.~r.J UIS
J.4.6{A~
II
F
01)"'"
'PIS
(.iiii
•
PIAII ( oIOPl
6
•
filj') ....6
1.IO~
6~
V'I
I
IoN
N
10
'.10(_
12
44
1'1.01 (lIT
6
I
DETAILED LOGIC DIAGRAM
1/0 INTERFACE
..
INPUT/OUTPUT (I/O) INTERFACE
(drawin~
number 89619700, sheet 9)
OVERFLOW LOGIC
Funct ion
This circuit generates the overflow signal (eVFL), for arithmetic
operations in the computer.
Inputs
Signal
r
Connector/
Pin
Active
Function
1 - - - - - + - - -......- - - - - -... __ .
KflVF
BB
A7M
H
03
L
32KW
SO
ADD7M
AUG7M
ALU7AM
H
M
H
PTA DO
H
H
H
H
H
H
H
I
P2B19
P2A27
P2A20
P2B07
P2A02
P2B26
P2B28
P2A28
P2A29
P2B03
P2B24
. " "..-.. . .
Locat ion
Square
I Sheet
~'''--------_+_-----__f
Overflow flip-flop, K Input
9
c4
B4
B4
~
:: I
Addition/Subtraction control
9
B3
B3
B3
A3
C2
D3
Outputs
5-322
BXl5
H
'VfL
H
P2B27
P2Al2
9
C3
01
89633300 A
(I/O) INTERFACE
(drawing number 89619700, sheet 9, contld.)
Description
The state of the overflow flip-flop (U39/IS) determines the overflow signal.
Its output (fJVFL: U41/2) is transmitted to the Programmerls Console
(OVERFLOW indicator) and to the Console Interface.
The J input to the flip-flop is connected to the signal Jf)VFL (U38/8):
J~VFL
= MMRQof)OOoABRo(F = 2)o(F = 3)oPTAOOoM
° (AUG7M ~ ALU7M) (SO ~ AUG7M .~ ADD7M)
0
This restricts overflow to instructions in which arithmetic sums occur
ADD, SUB, RAQ, ADQ, INQ and INR. The signal SO controls addition (high)
and subtract (low) in the ALU. Thus during addition an overflow will occur
according to the function:
(AUG7M $ ALU7M) ° (AUG7M <.T.) A007M)
Thus on overflow the two numbers being added have the same sign while the
sum has the opposite sign.
During subtraction an overflow will occur according to the function:
(AUG7M ® ALU7M) ° (AUG7M (t) A007M)
Thus the two numbers being subtracted have opposite signs; the subtrahend
and difference also have opposite signs.
The K input, Kf)VF, is produced on the console interface card and is active
during skip-on-overflow and skip-on-no-overflow instructions. The preset
is connected to the signal (u40/6):
f)pof)OO·FEO·(FI = E)·32KW·XI5 + [f)P·f)DD + MOS·CNTE2].(F = 3)·A7MoJKCK
89633300
A
5-323
(I/O) INTERFACE
(drawing number 89619700, sheet 9, cont'd.)
Thus the overflow flip-flop is set during an exit-from-interrupt instruction
when the computer Is In 32K mode (Operator's Console switch 32K/6SK) and the
sIgn bit of the X register Is set. The flip-flop is also set during a
dIvide Instruction If the quotIent is too large for the A register.
The overflow flip-flop Is cleared by the signal (U55/12):
Thus the flip-flop is cleared under the conditions for setting it, except
that the sign bit of the X register is not set. Itis also cleared by
Master Clear '"
...
'IIU
_>PlAOI
tHO}'2"1
1I
'"
\.AI
\.AI
8
~
...... ALL . . . . , . . AM O.·WATT,'"
DeTAILED LOIIC DIAGRAM
CClNIOLE INTERFAC£
IK
CONSOLE INTERFACE
(drawing 89618800, sheet 2)
START/STOP SEQUENCE FLIP-FLOPS
Function
This circuit works in conjunction with the Timing board. It produces the
signals for starting and stopping timing sequences under control of signals
from the Programmer's Console and from other computer control circuits •.
1nputs
-T-·-·----····
f'· .
i
Signal
Active
i,
I·
Connector/ !
Pin
I,
.
Function
.. -... ··t "'--'--""'-'- ...........
.
-.. - .. - ..-- .. -..... _...
-..
locat ion
Sheet
Square
.
RNI
H
INT-SW
STfJPCS
PRGST
H
McCS
L
GSeS
H
t~(1RMAL
H
PC'[
L
l
l
L
SOD.
JKCK.
H
PlAl7
PIBl6
PlAl6
.PlAlO
P2B27
P2AOS
P2Al 1
P2A22
PlBl3
P2Bl8
CRQ
MPRY
H
PlB25
P2AI2
GfJCSW
L
P2A04
-
L
----".-,.~--
89633300
i Read Next Instruction
iI
-,
1
I
.. ·····---·1
q
I
i.
.
2
I
i
..
I
; Normal/Power fail
indicator
Odd cycle
Last phase of clock
Parity signal
2
04
04
04
04
c4
c4
C4
c4
B4
B4
I,
1
A4
A4
A4
..
A
5-339
CONSOLE INTERFACE
Outputs
(Drawing 89618800, sheet 2, conti d.)
~gn;~_. -__~-t~v~ __ ~ _ ft~::t~~~_~~ • • ~~~.~~~~~~n~~-_- ~r--_S~~!:~t~~:. re
MC
l
Me
H
SS I
H
l
l
I
P2A27
I
01
1
j
01
P2A13
Start timing chat1
el
I,
I
PIA27
P2B22
WRQ
H
;
PIAII
PRY
H
. .i
i
I
I.
I'
P2B28
i.... .... _. __
01
PIB15
I
I TP
2
I
I
I
Master Clear
!
P2B29
H
I
Master Clear
I
,I
H
MPC
I
I
l
P2B25
el
el
!
Memory Request
_...... _._'.... .
Bl
!
BI
2
.~
.•• ' •.••. ,,_.- ___ ..•••.• _..... ' ..••~._~ .. ,..,_~.~. __ .. __ •. ____ ... _ ... _ .".
I
Al
.. I
Description
The Timing chain is started by the signal SGI (see Timing sheet 2).
is generated in the GQI fl ip-flop (U22/S).
of its clock input.
This is set by the positive edge
This signal may be produced by GQlCSW from the
Programmer's Console or by the test mode logic (sheet 1.).
after the
active.
SGT signal
5-3"0
Two clock pulses
is received by the Timing assembly, the GQlCS signal becomes
This resets the GQI fl ip-flop.
also be reset by MPC
SGI
= MC
Alternatively the GQI fl ip-flop can
+ PCl.
89633300
A
CONSOLE INTERFACE
(Drawi~g
89618800, sheet 2, cant'd.)
The timing chain, and therefore the computer, is stopped by the signal
SSI produced by the stop flip-flop (U23/8). The stop flip-flop is set
by the following signals:
WRQ (RNI-INST + STOP.CS + PRGST-FS) + HCCS + HCT
where
-
WRQ is active during the second CPU memory cycle (see below).
This flip-flop is clocked by the signal PH3 from the Timing
assembly phase-generator.
According to this equation the flip-flop is set (and the computer stops)
-
-
at the beginning (Phase I of
RNI'~DO)
of the next instruction with
the instruction stop switch set
at phase I of the 0DO that follows the firstWRQ with the CYCLE
step or the STOP pushbutton set
when the PRGST signal from the Programmer's Console is active
at phase I of the first 0DO cycle after the master clear is pressed
or when a signal is received from the test mode logic.
The stop flip-flop is cleared by MPC and preset by the NORMAL signal from
the Memory Control assembly.
The First Step signal (FS: U23/5) is active high during
the first memory cycle after a master clear or P register clear
-
89633300 A
after P clear
after an abor·ted
ent~r- interrupt
sequence, (see sheet 5).
5-341
CONSOLE INTERFACE
(Drawing 89618800, sheet 2, cont'd.)
The signal is preset by MPC+ KENI1-JKCK and clocked by EVEN-PH3. This
signal causes the CPU to request the memory according to the address P
(Instead of P, + 1) in the fol1owlng cases:
-
while reading first instruction when starting to operate
program
when first enter/sweep is executed
when the ENI sequence is aborted and the CPU has to call
again on the instruction located in address P.
The Master Clear signal MC (U30/6).
Its equation is:
The Master Clear is active when
the N'RHAL signal from Memory Control Is low
the computer Is not running and the master clear button on the
Programmer's Console Is pressed
- Master Clear signal is received from the test mode logic
when the computer is running and the Master Clear button is
pressed, the computer is first stopped by the stop fl ip-flop
and then cleared. The signal N'RHAL is active high unless the
computer is in power fail mode.
The signal WRQ (U26/11) shows an EVEN cycle occurring after an 'DO
cycle in which a request to memory was made. Its data input is eRQ which
is produced on the Timing assembly. It is clocked by JKCK and is cleared by HPC.
The WRQ2 flip-flop (U26/1S)is active during the odd cycle that follows the
The parity fl ip-flop, PRY (US/S) is clocked by WRQ. I t stores the parity
of each 16 bit Word written into the memory by any store-type instruction
being executed in the CPU. PRY (Parity) is high when the nu~er of I bits
in the 16 bit word is even. The output of the flip-flop, PRY is transmitted to
the Decoder assembly and used in the execution of the SPA instruction.
The
parity of the word written into memory is generated in the Memory Address assembly.
S-342
89633300 A
00
RNI
1.0
~
vee
0"
W
W
W
0
0
J
32
PIBI6
INT.SW
8
vee
2 204
U43
P2A27
(Me
vee
~
180
3
R 22
560
PIBI5
551
PIAI6
ST¢!> CS
P2B2
CJ
MC
"'''
veel
PRGST
3~
R21
560
~-.---
40
.....
PUll
MCCS
SGI
..",n
G~CS
P2A05
>
N8'RMA~
U30
4~
IAn
II
6
r---
a L.. T
I
I I I I I
r-
, .. 1"'-
1"-
..... ..,' I
s(w}
----. ..
L.
12
CRQ
PiAI2
MPRY
i
.-,,""..
II
560
,
,,,
r
-'='"
......
I
-'='"
-'='"
T.P.
na"
( WfIQ
PRY
W
\J"I
I
10
W
W
1'2821
".
Jl'AI
efCsw)
II
P28II
JKCK
I
( MPC
3,4,6,7
4
\J"I
( FS
P
PCl
JDl)
~140~
WLJ
DETAILED LOGIC DIAGRAM
CON8oLE INTEM'ACE
CONSOLE INTERFACE
(drawing number 89618800, sheet 3)
PROGRAM PROTECT LOGIC
Function
• used by the program protect system
This circuit includes most of the logic
of the computer.
violations:
a.
It detects two of the four types of program protect
An attempt to execute a protected instruction after a non-protected
one.
b.
An attempt to execute an unprotected instruction which can affect the
protect system.
The other two types of violation
are detected in the Memory Control.
They
are transmitted to the Console Interface by means of a single signal (CVIOl).
Inputs
.. -.. ····__ ·_····Loca t ion _._-,
Signal
Shee t
. ,,"
~
Squa re I
. .... .. I
04
I
.
~
-
PRTSW
H
MX17
IRCK
H
H
P2A14
P2A19
P1A20
FEO
Ql002
L
L
P2A10
P2B11
B4
INR
H
P2A29
B4
10
IF
H
P2B23
H
R3
R4
H
P2B19
P2B06
B4
B4
B4
H
P1A30
89633300
A
3
c4
,
-~-,
I
!
c4
c4
3
B4
5-345
(Drawing number 89618800, sheet 3, cont'd.)
CONSOLE INTERFACE.
Inputs (cont I d.)
_
I~~-~f~~: I~ "~~~_-:-:ct-o-r/-~Ii[----F-~~~ti ~~=-F ~_~~h~~~~~ t~~~a re
SWEEP
ENTER
PIT
CVIOl
PH3
PHI
L
L
L
L
PIB17
P1B18
H
P2B05
PIAI4
H
Pl B06
P2B04
!
.
I
!
~
j
;
f
A4
A4
c)
I
I
I
C3
B3
.i!
,.
Clock phases
.1
...............
__......... ...
~---
...
-.~'.-
A3
A3
3
...---'".... ...- . - - ....- _..,._."
~
Outeuts
.
[ S1 9 nal
Act i ve
."
PRT BIT
PRTAQ
'P"R'TM
INToo
PEF
Vii"
PFIND
CLREQ
ClRXM
5-3"6
~_.-
.-.-.. .
Connector/
Pin
~
H
L
L
L
L
L
H
H
H
Function
"'-""",
PIA25
P2A28
P2B24
P2B07
P2A09
P2B15
P2B13
P2B12
P2A29
.,'"
.
'-~'
.....,
-.-..
".,'.-.
Par i ty Bit
"
,-
.-- .. ...
,
-~-
Locat ion
Sheet Square
..-...... _.-....... -.
-',
3
I
Protect Faul t
Indicator (PRFA)
Clear RQ flip-flop
!
L!
3
Dl
Dl
Cl
Cl
Cl
Bl
B1
Al
Dl
---' . __...
89633300 A
CONSOLE INTERFACE
(Drawing number 89618800, sheet 3, cont'd.)
Description
An illegal instruction sequence is detected by the flip-flops MXl7
(U48/s,8).
is MXI7.
The MXl7A flip-flop (U48/S) is clocked by IRCK.
Its data input
The first half of the fl ip-flop (MXI7A) stores the protect
status of the current instruction.
Its output clocks MXl7B (U48/9).
When a protected instruction follows a non-protected one, the output of
MXl7A goes high causing the Q output of MXl7B to go high.
The MXl7A flip-flop is set by the signal
MCT +ENI
+ PRTSW.
Thus the first
instruction after a master clear or after an enter-interrupt sequence may
be protected without causing a protect violation.
When the protect switch
is NOT set, every instruction is considered protected.
flip-flop is cleared by ENTER + S\/EEP + PRFB.
The MXl7A
PRFB is active when a
protect violation caused by an illegal instruction is
sensed~
instruction is executed as a non-protected selective stop.
sweep modes are also non-protected.
Such an
The enter and
The output of MXl7Ais also used
on
the Memory Control assembly and by the A/Q and DSA busses.
The flip-flop MXl7B is preset by:
MCT +
ENI + PRTSW + ENTER + SWEEP +
PRfB
This blocks a protect violation when the protect switch is not set and
allows a protect violation to be cleared by the master clear signal or by
the enter interrupt sequence.
It also causes the fl ip-flop to be preset
after a protect fault is detected.
The MXl7B is cleared by
PRfB
to ensure
correct t imi ng.
The protect bit flip-flop
read from the memory.
(see sheet 2).
Console.
89633300 A
(u24/6) stores the protect bit of every word
The data input is MX17 and it is clocked by WRQ
The output, PROTFCT-BIT is displayed on the Programmer1s
5-347
CONSOLE INTERFACE
(Drawing number 89618800, sheet 3, cont'd.)
The flip-flops PRFA (U35/15) and PRFB (U35/11), are set when a protect
fault is detected on the console interface card. The clock is PH3 and
data input to both flip-flops is the following function:
VI0
= PRTSW·MX17B + PRTSW.MX17A.RNI·0DD.(F=0).(INR.,0+IE+R3·R1D
This signal is active when the protect switch is set and an illegal
sequence is detected; or when the switch is set,. the current instruction
is not protected, and one of the following instructions has been read:
EIN, liN, SPB, CPB, EXIT, or INR (Inter Register). Here the M register
is a destination register. The flip-flop J-input is VIO. It is also used
by the Timing assembly to block the memory request signal CRQ and to avoid the
clock JKCK when one of these violations occurs (see Timing, sheet 2).
The PRFA flip-flop may also be set, through its preset input, by the signal
CVIOI from the Memory Control assembly. This signal becomes active when the
memory control detects protect violations during a memory cycle, caused by
the CPU.
CVIOI also sets a latch made up of two NAND gates (U8/8,11).
reset by the signal:
This latch is
0DD+0DD2+PH3+ENTER+SWEEP+RNI
The signal PEF is active when the latch is set or when the signal
PEL·MXI7A is active. PEF is sent to the decoder and is used to avoid
changing the A register during the SPA instruction in case the memory write
cycle was aborted due to protect fault or parity error.
The PRFA flip-flop is cleared by the signal MC·PRTSW. It may also be reset
by KPF which is produced on the Console Interface (sheet 7). It is active
during skip-on-protect-fault or skip-on-no-protect-fault instructions.
5-348
89633300 A
CONSOLE INTERFACE
(Drawing number 89618800, sheet 3, cont'd.)
The output of the PRFA flip-flop (PFIND) is connected to the PROTECT FAULT
indicator on the Programmer's Console.
It is also wire-ORed through open collector inverter (U47/8) to be part of
the signal INTOO which is hard-wired to the zero level interrupt on the ALU
least significant board (LSB).
The equation 6f INTOO is:
INTOO
= PEL·RGPWR·PFIND
The PRFB flip-flop is cleared by PHI.
It produces the signal CLREQ which
is sent to the Timing assembly to clear the RQ fl ip-flop.
This prevents any
memory request signal even after the VIO signal has become inactive.
The
CLREQ signal also clears the instruction register so that the instruction is
executed as a non-protected selective stop (see Console Interface, sheet 5).
89633300
A
5-349
Timing Sequence During Protect Fault Caused By Illegal Instruction
\on
I
W
\on
o
-I
INSTRUCTION
..----,
PHI
ILLEGAL INSTRUCTION
CLOCKED INTO
INSTRUCTION REGISTER
I
REGISTE~R
CPU EXECUTES
CLEARED ________________
SELECTIVE STOP
__________________;
~-,
J;7
...----.
A~
:::r
CD
rT
3
::J
IQ
-.
.,
~
III
IQ
PH2
-I
m
::xJ
~
.......
.,c
III
rT
~
CD
::J
IQ
.,
"0
0
rT
CD
0
rT
""'h
::J
c:
3
CT
.,CD
0)
III
\..0
0'\
rT
0)
0)
~
0
0
c:
RQ
Z
""'h
3
:::r
JKa<
0
m
n
m
.,
PH4
en
r
III
0
PH3
n
0
z
CD
rT
CD
0
EVEN
rT
III
III
:::r
CD
CD
CD
rT
c:
W
.0
RNI
CD
::J
0
CD
0
0
::J
rT
VIO
III
III
:::r
0
0)
\0
0'\
w
W
w
0
0
l>
CLREQ
~
::J
CT
CD
cr:rmr
0
~
-.
~
....
....
00
~
I"
0'\
,
...;..n
(
CLRXM
co"§>'
(
PRT BIT
W
W
W
o
o
pv
»
PRTSW) '7"'"
,
1"-
,"I
. - (PRTAQ
IF'''
MlCI7
JRCK
'ffi)
..
~ -~
1f'12,
~~I"""'~
AG 8
U:53
~&I~J
11002
"12Ci3lf'1O
,
(Pii'fii
P2IOl (INTOL
PEF
U8
~
l_
INR
IE
RlI
R4
) PlMQ
I
I ~@I
Il6
I
7
.~
1 cM
RGPWR ) _Pl_822;;:;""..L1~w I
,
SWEEP
U1
•
"'"
U1
00iii
DETAILED LOGIC DIAGRAM
CONSOLE INTERFACE
nlla
(VIJ
1'1"
"""o;!
(PFIND
II'''
.........
(elMO
CONSOLE INTERFACE
(drawing number 89618800, sheet 4)
TEST MODE AND AUTORESTART
Funct ion
This is the circuit which executes the commands from the TEST MODE and
the AUTORESTART positions of toggle switches on the Programmer1s Console.
Both features cause the computer to start running after a master clear.
Inputs
r--'~-igna 1
........ ..... ---...-......-----.----,.---,.. - .....-.. ........
Connector/
Pin
Function
."~'
Act i ve
r-i~~:~ "--i-
~--.~
'
-,.~--
......
-,....._,..
~
T'MSW
L
32M
H
H
P2A30
..
~,.
--- ..'- .... ..._.,._-Location
Sheet Square
~.---
..,'
..
4
P2B09
P2B31
P2A08
P2A2 1•
P2B26
.,'
Breakpoint signal
Autorestart switch
Test Mode switch
04
04
B4
B4
B4
Outputs
BEAC
5-352
controlled
.........1IBEA
___________
_
4
CI
-----.-1
89633300 A
CONSOLE INTERFACE
(Drawing number 89618800, sheet 4, cont'd.)
Oescr i pt ion
The test mode feature is activated either by the TEST MODE switch or the
AUTORESTART switch, both on the Programmer's Console.
These switches produce the
signals TMSW and AUTRSW respectively, which clock the test mode fl ip-flop
(TM1, TM2: U17) with the signal
32M-(TMSW + AUTRSW-AUTiRS}
where
32M is a clock of about 32 psec period generated on the memory
control board.
-
AUT'RS is the output of flip-flop U5/8 (see below).
The
outputs of
two-stage counter formed by TM1 and TM2 are decoded as
H"CT (U44/3) and Gif (U20/6). These signals generate a Master Clear (Me)
and then a clock pulse to the G' flip-flop. The latter starts the computer
running (see sheet 2).
With the AUTORESTART switch set the computer is master cleared and starts
running on restoration of line power after a power failure.
When a power failure occurs, the signal N'RMAL from the Memory Control assembly
goes low. When power is restored, NIRMAL goes high, clocking the AUTIRS
flip-flop (U5/8). If the AUTORESTART switch is set, the test mode flip-flops
are activated, causing Master Clear (MC), and clocking the GI flip-flop.
The GI flip-flop produces the signal SGT (see console interface sheet 2)
which resets AUTIRS thus clearing the test mode flip-flops and allowing
the computer to run.
89633300 A
5-353
CONSOLE INTERFACE
(Drawing number 89618800, sheet 4, cont'd.)
The AUTiRS flip-flop also resets a latch (U6/3, II) which blocks the
breakpoint signal (BEA). This latch is cleared by Master Clear.
The gates U3/6 and 1J34/6 produce sync pulses when the contents of the
breakpoint register and that of the memory address register are equal.
These pulses may be. used for hardware debugging.
5-354
89633300 A
..
v
00
\D
0'
W
W
W
o
o
OPST) riEpY!
»
:1
2.56.7@
e?.!@
l
_ ............
IlEA) 1"2'11
,
~
2@
'I
IS
P2A!O
<8EAC
1201111>6
(AD) 2
PO'
CAl> 2
vee
AUTRSW) pc"...".
iiiii> P2AU
52M >P2826
,
VCCI'
I
I
,
V'I
I
W
V'I
V'I
........
V'I
I
W
V'I
0'
DETAILED LDGIC ·DIAGRAM
CONSOLE INTERFACE
.
CONSOLE INTERFACE
(drawing number 89618800, sheet 5)
ALU LOGIC
Funct ion
This circuit performs arithmetic and logic functions in conjunction with the
two ALU boards of the CPU.
These functions are:
-
carry generation
calculation of the trap address
QSX: (contents of Q register) < (contents of X register)
DBB: that bit of the bit bucket register which is used to generate
the sign bit for the result of multiply/divide operations.
NOTE
Two ALU assemblies are used to accommodate the
16 bits of the computer word (without parity or
protect bits).
One assembly designated LSB,
operates on the least significant bits (bits
00 through 07), the other assembly (MSB) operates
on the most significant bits (08 through 15).
Signals associated with the LSB are labelled
L, those associated with the MSB are labelled
M, these letters being appended to the signal
name.
89633300 A
S-357
(Orawing number 89618800,
CONSOLE INTERFACE
sheet 5, cont'd.)
Inputs
r"'" ....
'-"--"'r-'-' .-........... '1' .-.·..--.. . -.....·.-----..
-T---.~····-·-------·-····
: Signal I Active
!
I
--:
l TA2H
1
! TA2l
H
J
Connector/Pin!
f
'
j.
i
I
H
Function
.
......
...-
•
Location
sheet square
__._._-
5
P2A21
04
P2B26
Trap address generators
•
! TA1H
H
TAll
H
: TAOH
04
P2A17
04
P2B17
04
H
P2B16
D4
TAOl
H
P2A15
GHH
H
P2B03
ALU Carry generate
(b i ts 12
T
15
04
c4
PHH
H
P2A02
ALU Carry propagate (b its 12
.
15~
c4
GlH
H
P1B20
ALU Carry generate
T
11'J
c4
; PlH
H
PIA21
ALU Carry propagate (b i ts 8
T
11'
c4
i
GHL
H
PI B31
ALU Carry generate
(bits 4
T
t
c4
i
PHL
H
P2BOI
ALU Carry propagate (bits 4
T
7
c4
.: GLL
I
H
P2B02
ALU Carry generate
(bits 0
T
3'
c4
i PLL
i
H
P2AOI
ALUCarry propagate (bits 0
T
3)
c4
; A7H
H
P1B08
D2
H
P1A08
D2
j Q.7M
I1 ! 03
H
P1B09
D2
i
XGQ.L
H
i XSQ.M
H
i
1
!,
I
I
i
(b i ts 8
1
i
I
i XI5
I
I
II XGQ.M
. -_....
5-358
L
H
I
1
I
I
P1B07
F - 3
C2
P1A03
{X} > {Q.} on LSB
C2
P1B02
{X} < {Q.} on MSB
C2
P1A02
0'
•
.....
._.
{X} > {Q.} on MSB
...
~'"
._
.....
~
.!_---- -.~. ~- j
89633300 A
I
(DrawIng number 89618800, sheet 5, cont'd.)
CONSOLE INTERFACE
Outputs
r - - - - - - r -...- - - - .
Signal
_ ..... _ ....... _ ...._. _.-.. __. '-"' ........ - .......... - ..... -- ........ - ....... "
Active
Connector/Pin
Function
locat i o~""'-sheet
ITA4l
l
P2A26
ITA3l
l
P2A18
ITA2l
l
P2A16
MCNM
H
P1B30
lCNM
H
P1 B29
MCNl
H
P1A31
LCNL
H
PIA2)
DBB
H
P1A06
QSX
.
_ _ _ _ _ _ _ _ . . . . . . . . . _.
89633300 A
H
___
.p'
h_ ..
5
Trap Address
•
__
.~
••.
~,
.....
,
D3 !
II
C3
-
C3
Carry output to lSB
_
It
_
Bit bucket sIgn bit
{Q} < {X}, over 16 bits
~_,
••. , ...... _..
_ _ .. _ .. _ •••.•.•• _
. . . . . . . ·._·· ....... _ · _ _ ._'· ••
I
C3
Ca r ry output to MSB
P1B03
'h'_'~'
squa re 1
. . .... ··_····_·1
D3 I
D3
-
'!
I
J
5
B3
Cl
Cl
P.__ .. _· . ...... _. __ ... __._., . . .,. ..
~
5-359
CONSOLE INTERFACE
(Drawing number 89618800, sheet 5, cont'd.)
Description
NOTE
The two ALU boards will be refered to as follows:
MSB: Board dealing with eight most significant bits;
LSB: Board dealing with eight least significant bits.
The carry generator of the ALU is the look-ahead microcircuit, U49. It
accepts the carry propagate (p) and carry generate (G) outputs of the ALU
microcircuits (74181) from the ALU circuit (sheets 2,3), and returns four
carry inputs. Each group of four bits of the ALU produces a G and a P
signal, the suffixes specify the group of bits. The following table is a
key to these suffixes.
I
Board -p;:;;-;;;-~f bi"~;-i h8j~ -N;;'~.Sufflxl
_ LS;-..-.·.-I.----~::~·-----:·-·
I
higher
MSB
i
lower
H58
i._.... ...... . .. ,".
5-360
j
LSB
,
i
higher
. •...•..•... ___ ..... ' .. ~._ .•
II
I
I
I
t
i
-io
~
. . . . . . --,
-;.-~.;
4
"LL .. -.-
7
HL
8 t 11
LM
11
............
_~
T
f
15
.
HM
.............._ _ _ _ _+_ - _ .. _ ...- ............ _.
89633300 A
CONSOLE ItITERFACE
(Drawing number 89618800, sheet 5, cont'd.)
The logic equations for the output signals are:
LCNL = GMM· GML • GLM • (GLL • PLL + PML) + GMM • (PLM • GLM + PMM)
MCNiL = LCNL. GLL + GLL.PLL
LeNM = LCNL
GML
GLL + GML • GLL
PLL + GML
PML
MCNM = LCNL • GML • GML • GlL + GLM • GML • GLL • PLL + GLM • GML • PML +
+ GLM • PLM
The signal LCNL is generated in the super-high speed AND-OR-INVERT gates U50, U36/6.
The output signals are returned to the ALU board designated in the last letter
of the signal name: LNCL and MCNL to the LSB, LCNM and MCNM to the MSB.
The trap address is calculated from the TAO, TAl, TA2 signals of the two ALU
boards, the corresponding signals from the two boards being ANDed together to
form the trap address signals (ITA2L, ITA3L, ITA4L) which are returned to the
lSB.
Comparison of the contents of the X and Q registers is performed on each ALU
board for the bits on that board. The following signals are generated and
sent to this circuit as inputs:
Signal
Origin
Significance
o
XGQl
XGQH
XSQH
Note:
V(}
lSB
MSB
fo1SB
00 -- _._ O-----t
{X} > {Q}
o
{)(}
{X}
> {Q}
CO
{Q}
signifies "content of register X over the eight bits of the board".
The output of this circuit is QSX which is active when the content of register
Q is smaller than the content of register X, over all 16 bits. Its equation Is:
QSX = XGQM + XGQL • XSQH
89633300 A
5-361
(Drawing number 89618800, sheet 5, cont'd.)
CONSOLE INTERFACE
The bit bucket, located on the decoder card, is used to store a bit at the
beginning of multiply and divide instructions.
In mUltiply instructions
the bit stored is A7M{jjXI5 where A7M is the sign bit of the A register and
XI5 is the sign bit of the X register.
In division the bit stored is Q7MEB XI5 where Q7M is the sign bit of the Q
register.
or divided.
Thus the bit will be set if numbers of different signs are multiplied
The bit bucket is set by the signal DBB generated at U54/8, from
signals of the A, Q and X registers on the MSB:
DBB
5-362
=
(AI5E9xI5)
·03+
(QI5¢ixI5) ·03
89633300 A
.
~
00
1.0
'"
\oN
\oN
\oN
0
0
TA2M
TA2L
TAIM
TAIL
TAOM
TAO!..
>
I"v
"'qI~'"
(iii4L
A7M
til
r~"'D
~ miL
XIS
P2A18
iTiiL.
v
rf!1OI
rf!
015) Pl801
Os
>PlB07
'lII04I (D.
GMM
PMM
GLM
PLM
...
GMt..
PML
GLL
PLL
?
:!~!?~
5n. a 4K
AW
p.'
5-:.'
(
~
P-":~'
(
xeOL
>PlA03
XSO.
~
xaQ.
'- PlA02
SID
~";--:;;:;u.~
P
CF
,L.-:_ _ _ _ "'
Me...
LCN.
MCNt.
GIl
~
..ri1r.1205S
II
111111
t--iU50 M
~
LeNt.
!
91-
II~
I
~
V'1
I
\oN
'"
\oN
DETAILED LOGIC DIAGRAM
CONSOLE INTERFACE
CONSOLE INTERFACE
(drawing number 89618800, sheet 6)
ENTER INTERRUPT LOGIC
Function
This logic circuit controls the initiation of the enter interrupt sequence.
(see Timing, sheet 4).
Ineuts
---...--.- ... ... r ..... Signal
Act ive
r
. ..... _...- - - --. ·······1·--- -.----. -_ ..-
' . ' _ •.
Connector/ Pin
_,_.,..~
_ _ _'
• __ 0_." _ _ _ _
Locat ion
Sheet
Square
Function
..
ENI
H
ENI20
KRN 11
GSL
GSM
INO INO
EINT
DEL2
DFEO
L
P1A1S
P1B24
P1B28
P1A22
P1A24
P1B23
P1A19
P2A20
P2B08
H
L
L
H
H
H
6
03
C3
C3
B3
B3
B3
B3
B3
A3
6
Dl
6
I
I
Masked Interrupt detected
_----
I
I
Indirect Address i nd i catal
i
Interrupt System Enabled
.
Outeuts
'VFW
L
ENi'4
L
CLRIR
KRNI
H
KEN I I
H
JENI
H
.
I
--_'_"'_'",._----.,.-
5-364
H
.....
"-
ENI ·fJVFL
P1B12
P2B14
P2Bl0
P2A06
P1A28
Clear Instruction Regist
P2A25
... ..................
'
-~
-- ............... _ ,. - .....- .. '.
...
Cl
Cl
Bl
Bl
. ..
.-
...,
..............
6
At
89633300 A
CONSOLE INTERFACE
(Orawing number 89618800, sheet 6, contld.)
Description
The ENI f1 ip-flop on the timing card is set by the signal JENI.
is:
JENI
= [(RNI·IPS + INOINO)·(GSM
This signal
+ GSL)·WRQ·EINT]·
[RNI.MX17A.MXl7·~
• [RNI.MXl7A·MXI7·OFEO·OEL2]· [RNI·PRTSW·DFEO.OEL2]
where
EPS is active during enter of sweep mode EPS = ENTER + SWEEP
- GSM and GSL are generated by the ALU boards and are active when any
interrupt line is active and its corresponding bit in the M register
is set
INOINO is generated by the I/O interface and is active when the
computer is doing indirect addressing
EINT is produced by the I/O interface and is active when the interrupt
system is enabled.
The JENI signal becomes active during RNI or in indirect addressing in the
CPU cycle following a memory request if the interrupts are enabled and a
masked interrupt is detected. However the JENI signal will be blocked if
one of the following conditions exists:
a.
b.
The next instruction is liN and the protect switch is OFF.
The next instruction is a protected liN and the present instruction
is protected.
The next instruction will cause an illegal instruction sequence
(because of a protected instruction following a non-protected one) and
a protect fault does not already exist.
c.
89633300
A
5-365
CONSOLE INTERFACE
(Drawing number 89618800, sheet 6, cont'd.)
The signal KENII is used to abort the enter interrupt sequence when the
H register is changed just before the sequence has begun and the Interrupt
is therefore no longer masked. The equation of KEN I I is:
KEN I I = Gsii·GSt·RNI·ENI
KENII is used to block the KRNI signal which allows the RNI state to
remain active. It is also used to preset the FS flip-flop (see Console
Interface sheet 2).
The signal CLRIR Is used to clear the Instruction register.
during:
It is active
- RNI·ENI which is the first CPU cycle of the enter interrupt
sequence (at U20/13);
- ENI2._DD (timed by PH3 during sweep or enter) at the end
of the sequence;
- CLREQ (see Console Interface sheet 3) at U20/9 and Master
Clear at U20/12.
The signal ENI2·_DD sets the ENI4 flip-flop (U24/9). The output of this
fl ip-flop prevents the fi rst RNI cycle after the enter inte.rrupt sequence
from being interpreted as a selective stop. This is necessary as the
instruction register is cleared at the time of that sequence.
The signal _VFW = ENI·'VFL is used to set bit 15 of the P register with the
status of the everflow bit during enter-Interrupt when the computer is in
32K mode (32K/65K mode switch on Programmer1s Console).
5-366
8g633300 A
.
....
00
\0
'"
IoN
IoN
IoN
o
o
I'"
(OVFW
»
iTiiO > r'8.~ i!1
(\8
P2814
(EHI4
P2"",
(CLAIR
ICMII -
KRNI
iii.
EINT
PIA
DEL2
P2AN
DFEO~
~ ..
,
""......'",
, rrU\R (JENI
V1
IoN
V1
IoN
'"
00
DETAILED LOGIC DIAGRAM
CONSOLE
INTERFACE
1
CONSOLE INTERFACE
(drawing number 89618800, sheet 7)
SKIP LOGIC
Funct ion
This circuit carries the logic used i'n executing the skip instruction.
lnputs
Signal
32KW
15
FIEI
IJVFL
14
Act ive
H
H
H
L
H
SLK
AM
AL
L
Wffi'
L
QEZI
H
mr
L
16
H
IT
L
H
H
Computerl
Pin
PlAl2
P1AOl
PlA09
P1B10
PlBOl
P1A07
PlA26
P1B26
P1At3
I
I
P1B27
P2A07
P1B05
P1A05
Locat ion
Sheet Square
Funct ion
.-.
7
Bit 5 of Instruction Register
Bit 4 of Instruction Register
I
~ontents of A register 200
I
~ field of Q-register equals zero
Bit 6 of Instruction Register
Bf t 7 of Instruction Register
7
04
04
04
c4
c4
c4
c4
c4
B4
B4
B4
B4
B4
:
Outputs
~VF
H
rnr
L
SKT
WEZ
H
89633300 A
L
PIAlO
P1B21
P1B04
P2B30
7
Skip Condition
~EZ - WEZM (logically)
7
01
Cl
Cl
Al
5-369
CONSOLE INTERFACE
Description
(Drawing number 89618800, sheet 7, cont/d.)
The signal SKT is active when the conditions for a skip exist.
Its equation is:
SKT
=
15·16·17· (TIiE9AL
AM) + T7.lb.IS· (T4$A7M)
+T7.16.TS". (fli"Qi)WEZM·WEZL·QEZ ) + T7.16.IS· Cf4 $Q7M)
+ 17·1b·T5· (".{~ SLK) + 17·lb. IS· (l¥(i)i\iF[)
+17016.T;.(TZi'$PEL) + 17. 16• IS·Cfli'$PFIND)
where
- 14, IS, 16, 17 are bits 4 T 7 of the instruction register,
- AL and AM are produced by the ALU boards and are active when
the contents of the A register is zero
- A7M and Q7M are the sign bits of the A and Q registers
- the signal WEZM·WEZL·QEZ) is hiqh when the Q register is zero
- SLK is low when the selective skip switch is set
- the signals ~VFL, PEL and PFIND are active during overflow,
parity error, and protect fault, respectively.
The signal CGPE is used by the Memory Control assembly to clear the general
parity error flip-flop.
It is active during skip-on-parity-error and
skip-on-no-parity error instructions and also during master clear.
The signal K0VF is used by the I/O Interface assembly to clear the overflow.
fl ip-flop.
It is active during skip-on-overflow and skip-on-no-overflow
instructions and also when the computer enters an interrupt while in 32K
mode (programmer's console switch 32K/6SK).
The skip logic also produces a signal (U27/8) which clears the protect fault
indicator during a skip-on-protect-fault or skip-on-no-protect-fault
instruction.
S-370
89633300
A
.
,
~
00
\0
0'\
eN
eN
eN
a
a
32KW)
ptAI2
1&)
... AO,
~
12r
I'T1
T &1
-
T
ptA'
FIEI
I,,§L _ _ _ _ _ _P_'_A'O
( KtlVF
PIB21
(em
I~
~FL)
pt_B='O"--_~
J 4 ).----f!IQ!
ilK)
I
4
b~_______~P~IB~0__
~
PlA07
AM)
PIAU
"'I
AL)
ptp, ..
'" I
",,,,,
'I
WEIM)
I
(SKT
Q30·QE~
WIn.)
P2A07
'"
I
E
1.
>
I'!IOO
,
11
>
!'1M
1""1
&
I
CJ'1
~
a
~
6
~
4
'-
1:"
180
P2B30
(WEZ
~
I
eN
-....J
--'
.........
W
-....J
N
A
DETAILED LOGIC DIAGRAM
CONSOLE
INTERFACE
...
TELETYPEWRITER (TTY) CONTROLLER
The Teletypewriter (TTY) Controller circuits are accommodated on a single
I
50-PAK wiring board. The logic circuit diagrams and descriptions cover four
different printed wiring assemblies (PWA) in the field. The relevant pages
are indexed in the lower table on this page.
The TTY Controller interfaces the computer CPU with a Teletypewriter Terminal
or with a Console Display Terminal (COT). It provides for communication at
9600, 1200, 300 or 110 bauds. The baud rate is selected by inserting a jumper plug in the appropriate location on the board (see circuit description,
sheet 4. This page lists the functional blocks accommodated on this board.
The circuits and signals are described in detail on pages facing the corresponding sheets of the circuit diagram.
This board also carries the Breakpoint Logic.
MAIN FUNCTIONAL BLOCKS
Shown on sheet
Designation
A/Q channel data path
2
Controller/Teletype interface
3
4
Oscillator - Baud rate selector
Address decoding - Reply/Reject logic
Control and i nte rrupt logic
5
6
Breakpoint logic
7, 8
PWA PART NO.
PAGE
89967400
5-374
5-402
89947600
89984700
89976400
89633300 E
I
5-410
5-416
5-373
I
TTY CONTROllER (PWA 89967400, logic Diagram 89616400, Rev. J)
A/Q CHANNEL DATA PATH
I
(sheet 2)
Function:
This circuit receives parallel data from the CPU and converts it into serial
form for transmission to the teletypewriter. It also receives serial data from
the teletypewriter, converts it into parallel form, and transmits it to the CPU.
Inputs
LOCATION
SIGNAL SOURCE/
SiGNAL
FUNCTION
SHEET SQUARE
CONNECTOR PIN
AOS
P2B23
0-4
A register bus bits
-2
A13
P2A I I
0-4
RDA
[U22/181
Reset Data Available
D-4
}
SDIN
CP
EPS
[U22/20]
[U22/l71
P2A28
Ser i a I Data Input
Clock Pu I se
PARITYSEL
P2A22
Even Parity Select
Pa r i ty Select
-12V
P2A23
Supply vo I tage
B-4
c-4
D-2
D-2
l.
B-4
2
.....
I
A- I
Bi-directional Signals
AOO
P2A20
A5T
A62
P2B20
Busy Status
P2BI9
Interrupt Status
Data
AD3
A04
P2AI7
P2A21
,
AOS
AOi5
P2B22
End-of-Operation
Status
Alarm
P2BI8
lost Data Status
A07
P2AI9
Parity Error Status
A09
AIO
P2B24
A-I
A-I
or data
B-1
bits
B-1
to/from
A-register
B-1
B-1
B-1
-...I
P2B26
A-I
2
A-I
-2
D-4
Outputs
m
P2B28
SPIaUT
[U22/2S1
TBMT
[U22/221
E0C
[U22/241
0R
DA
PE
[U22/IS]
[U22/19]
[U22/ 131
S-374
Serial Data Output
C- I
C- I
End-of-Operation Status
C-I
Data Available
.A-4
A-4
A-4
2
89633300 E
TTV CONTROLLER
(drawing 89616400, sheet 2, cont'd)
Description
Lines AOO through A07, A09 and A10 communicate with the CPU and serve both
as input and output lines. Lines A08 and A13 are served as inputs to the
contro 11 er.
Signal All is an output from the controller. The input signals
are buffered and converted. They are used as director function bits and are
input to the Universal Asynchronous Receiver/Transmitter (UAR/T) U22, and
other parts of the controller.
The cirCUit is built around the Universal Asynchronous Receiver/Transmitter
(UAR/T).
In its receive portion, this accepts serial data from the teletype-
writer (SDIN) and converts it to data on eight parallel 1 ines (terminals
5 through 12) timed by the clock pulses (Cp) from the oscillator baud rate
selector (sheet 4). In its transmit portion, the UAR/T accepts parallel data
on eight lines (terminals 26 through 33) and transmits it to the teletypewriter as SDeUT under the action of the same clock (cpl.
The control inputs to the UAR/T are XR, OS, CP, RDA, PARITVSEL, and even
parity:
XR resets the internal registers of the UAR/T
OS is a strobe for parallel input (transmitter)
CP is the clock input
RCA
resets the data available signal DA (receiver)
PARITVSEL is used to select the parity option,
EPS: selects whether even or odd parity is used.
The following table summarizes the action of the parity selector signals:
SIGNAL
LOGIC
LEVEL
EPS
High
Even parity generated in UAR/T
EPS
Odd parity generated in UAR/T.
PARITVSEL
Low
Low
PARITVSEL
High
89633300
E
FUNCTION
Enables parity in UAR/T (7 data + parity bit)
No parity generation (8 bits from CPU)
5-375
I
TTY CONTROLLER (drawing 89616400, sheet 2, cont'd)
The control outputs are PE, SR, DA, TBMT and ESC signals.
PE is active when the parity option is selected and a parity error is detected in the serial data input.
SR is active when a new character is received on the SDIN input, and the
DA output has not yet been reset.
DA is active when a character has been received on the SDIN input and is
stable on the parallel data outputs.
TBMT is active when a new character is transmitted in the SDSUT and remains
active until the start of transmisston of the next character.
The data flow from the CPU to the teletypewriter is thus from the common
input/output lines of the controller (AOO through A07, A09, A10) with parallel
data, to the single line serial data (SDSUT), according to the baud-rate
clock and according to the control signals.
The data flow to the CPU is selected by multiplexers U23, U37. The outputs of
these multiplexers are either the eight data bits from,U22 or the eight status
bits: Busy, Interrupt, Data EOP, Alarm, Lost Data and Pari,ty Error. One status
bit is always "1". The data selectors are controlled by signal DSEN which
comes from the address decoding and reply/reject logic. BitsAOO to A07 are
strobed by the signal (DSEN+RDA+READ) which comes from the receiver/transmitter
control logic. This signal is active when the controller sends data or status
to the CPU. The status bits are strobed by signal DSEN. They are used as follows:
A09:
read mode
All :
manual interrupt
NOTE
I
Sheet 2 on page 5-378 differs from some older revisions
in the following areas:
*
*
*
5-376
zone B-4: U22/20 is not connected to U22/21(zone C-l)
zone C-3: AND-gate type 140 is U7/9,10-8
zone A-2: AND-gate U68/1,2,13-11 is type 213S
89633300 E
00
1..0
_0'
v.>
v.>
v.>
o
o
rr1
fFF SHEET REFERENCE
OFF SH[ET
""'EII£NCE LETTER
4
8
______ 0
__
F
G
J
K
L
M
N
P
8-4
- --- -B-4
B-4
8-4
C-3
A-4
C -I
,1.-4
C-3
5
T
U
V
W
)(
Y
-
C-I
C-3
C-2
.
@ -----"IIV'tr--4 vee
~:n--~vcc
v.>
C-4
,1.-3
C-3
B-1
0-1
0-1
B-1
2
AV
AX
AY
AZ
BA
BB - BO
BF
BG
IfH"-- -A-4
BK
BL
BM
BN
C-3
C-3
0-2
0-4
0- 3
- - ---iii>--
0-4
C-I
4
0-1
5
6
0-3
C -3
C-3
B-2
0-2
C -3
C-2
C-I
B-1
C -I
B -4
C -I
0-4
B-2
B-2
0-3
C-I
0-3
B-3
0-4
D-3
B-1
8-1
as
B-2
B-4
----
B-2
B-1
-~~
---
--- -- -
--------
BU
BV
,1.-2
---,1.-4
-
"'Z
t-- - - i
N(lTE
--
----
A:J
RESISTeRS
I.
8
B-3
8- 3
0-2
C-I
C-I
C-I
A-3
,1.-2
0-3
B-3
A-3
ALL UNMARKED
ARE
025 WATT
5"4
--.J
R,.
®
a..
,vcc~vcc
R3S
R8
IK
If<
®- ~vcc ®-~---.3
P2A:29
(CRT-REC
-12V
:;:;:s
38
TTS FF
lis
-- I
S
QJ Z".z.H
G
GK
R33
+19V
)r_P~2=B2=7'----'l;..~?':;.___..,.______J~..J1.12Y
CII2
I .. 759A
US
R
61
•••
~A!I
G;3"
CI
C4
C!I
68.'
C6
- - C7
61.,
1 ..
C9
cta
CII
CI2
CI5
.1.'
68 .,
.1.,
61.,
.1.'
\11
CI!I
.8.'
CI4
00
- - - - . ...........".-.
:z
*
1I Ic!
T.
-=-
f
DETAILED LOGIC DIAGRAM
I
W
I
-12V) P2!2 4
I I I I I ..Lc.~
1 r I I I I I I I\U
T~ 1-T I - 1 1. T 1 I I T 'Ft7
:
-
.
TTY
CONTROLUR
.t
55Y
-:
611."
1-!2V
TTY CONTROLLER
(Drawing number 89616400, sheet 4)
OSCILLATOR - BAUD RATE SELECTOR
Function:
The Oscillator-Baud Rate Selector Circuit generates the clock signals
required to oper.ate the controller at four different rates: 9600, 1200, 300
and 110 baud.
The three higher rates are used only with the COT.
The circuit consists of a clock section and a group of programmable counters
forming the rate selector.
SIGNAL
SIGNAL SOURCE/
CONNECTOR PIN
FUNCTION
LOCATION
SHEET SQUARE
EXTCLI<
P2A09
External Clock
STPCLK
P2B09
Clock Stop Enabl e
0-4
BAUD SEL
P2A08
Programmed Selector Enable
8-4
4
D-4
,
Outputs
I
CP
[U7/l1]
Clock pulses
4
8-1
1 .3].ls
[U15/3]
].3 J.lsec clock
4
0"1
5-382
89633300 E
TTY CONTROLLER (drawing 89616400, sheet 4, cont'd.)
The Clock Section
The main oscillator consists of U45, U68, Q5, Q6 and a 12.2222 MHz crystal.
The output of this oscillator is divided by 10 (programmable counter U31
and flip-flop U14).
I
The resulting signal of 1.2222 MHz goes to
divide-by-16 counter (U15).
One output of U15 (Pin 3), is a clock with
a 1.3 microsecond period used in other parts of the control logic.
The
output at U15 (Pin 6) is a 152.8 kHz clock which goes to the Baud Rate
Selection Circuit.
The Rate Selector
Baud rate selection is accomplished by changing the preset inputs to
programmable counters UIO and Ull.
These process the 152.8 kHz clock
signal according to the preset input lines coming from multiplexor U12.
This chooses between two groups of four signal lines:
BAUDSEL active
selects four hard-wired logic levels as inputs to the selector, setting
the programmable counter to the 1200 baud rate;
BAUDSEL inactive selects
four programmable lines from location U13 as inputs to the selector.
A removable jumper plug at this location selects one of the baud rates
as follows:
Baud rate
Jumper plug in position
U13 terminals
110
89633300 E
JO
- 7
300
1200
11 - 6
12 - 5
9600
13 - 4
5-383
I
TTY CONTROLLER (drawing 89616400, sheet 4, cont'd.)
The action of this circuit Is now described.
When the 9600 baud is selected, the jumper plug at U13/10 -7 forces
U12/4 to logic low while the other outputs remain high.
This clears
flip-flop U9, blocking the output from counter UIO, and gates the
152.8 kHz clock through u8/3 and U5/6.
The resulting clock pulse (Cp)
goes to the clock input of U22 in the A/Q channel data path logic.
When 1200 baud is selected, pin U12/12 becomes low while the other
outputs are high.
This causes the data inputs of programmable
counter Ull to be 1011 2 and the data inputs of programmable counter
UIO to be 0000 2 , The circuit composed of U9, UIO and Ull thus
behaves as a divide-by-8 counter and the clock frequency signal (Cp)
becomes 19.1 kHz.
Similarly, when 300 baud is selected, the counter divides by 32 to
produce a frequency of 4.77 kHz.
When 110 baud is selected the
counter divides by 87 to produce a frequency of 1.76 kHz.
Note that the jumper plug for baud rate selection in location Ul3 has
to be inserted at the time of installation.
I
NOTE
Sheet 4 on page 5-385 differs from some
older revisions in the following areas:
*
*
*
5-384
zone c-4: two capacitors (CI8, 0.47NF
and C20, 47PF) and 180-ohm resistor R62
are not moUnted in the oscillator circuit.
zone C-3: AND-gate u68/11,9,10-8 is
type 2l3S.
zone B-1: AND-gate type 140 is U7/12,13-1l.
89633300 E
00
1..0
0"
Vol
Vol
Vol
£lCTCL.
o
o
_ _ _ _ _ _ _ _ _~
>~..:.P=.;ilA::::ot~
~ ~~~,---~
ITI
vec
~
R!I!I
R!l6
!!.
4vcc
IK
........
hlCc
.,
......... ......
...
yr .L
~T4'"
CIII
12~~22
MHZ
"'---,11
11115
a.1.
r
111Uf
I.
'\
12
.~
\1'1
I
Vol
00
\1'1
OSCILLATOR -BAUD RATE
SELECTOR
DETALED L08IC DlAIRAIl
T.T.Y CONTROLLER
TTY CONTROLLER (drawi ng 89616400, sheet 5)
ADD~ESS
DECODING
~
REPLY/REJECT LOGIC
Function
This circuit decodes the A/Q channel address bits from the
the CPU as well as the RE'Ai) and WRITE signals. It decides
(REPLY or REJECT) to the CPU based on these signals and on
the controller itself. The circuit also generates control
other parts of the controller.
Q register of
on the response
the status of
signals used in
Inputs
SIGNAL
ACTIVE
WIT
L
QOO
Q04
Q05
Q06
Q07
Q08
H
H
H
H
H
H
H
H
Q09
QIO
RfAi)
WRITE
Me
L
L
L
I
CONNECTOR
PIN
FUNCTION
LOCATION
SHEET
SQUARE
P2A15
P2A05
P2B07
P2B15
P2A14
P2A06
P2BI4
P2AI6
P2BI6
P2A04
P2B06
P2B08
5
P2B13
P2BI2
5
5
5
c-4
B-4
C-4
c-4
c-4
c-4
c-4
c-4
c-4
B-4
B-4
A-4
Outputs
REJECT
REPLY
I
5-386
L
L
89633300
0-1
0-1
E
TTY CONTROLLER (drawing 89616400, sheet 5, cont'd)
Description
The CPU addresses the TTY controller through the signals WEZ. Q04 through
Q10. When WEZ, Q10, Q09, Q08, Q06, Q05 are at logic low and Q04. Q07 are at
logic high, the TTY controller is selected and the logic high at the output
of the address decoder (u44/12: TADR) opens the decoder gates (U30, u44/6).
The decoder gates produce four signals, which are active according to the
information and data flow (under CPU command):
Note:
TADR is active high at u44/12 when the TTY controller is addressed.
Termi na 1 Signal
Equation
Information/ Data Flow
U30/12
RDEN
TADR. READ. QOO
Data from TTY to CPU (Read Data Enable)
U30/6
WDEN
TADR.WRITE.QOO
Data from CPU to TTY (Write Data Enab le)
U30/8
DSEN
TADR.READ.QOO
Status of controller to CPU
(Director Status)
u44/6
DFEN
TADR. WRI TE .QOO
Director function from CPU to controller
The strobe flip-flops provide the timing for the controller outputs
(REPLY. REJECT). They are clocked by the 1.3 microsecond pulse train from
the oscillator/baud selector circuit (sheet 4) and cleared (stopped) unless
either the "R'E"AD or WRI TE command is act i ve.
The controller gives a REPLY or REJECT output to the CPU during strobe
pulses. The REPLY signal is active when the output control gate (U39/6) is
high. This occurs when anyone of its inputs is low. The following table
summarizes the input conditions to the output control gate.
89633300 E
5-387
I
TTY CONTROLLER (drawing 89616400, sheet 5, cont'd.)
Input Signal
REPLY Active
U39/1
i5'S"EN
Read Status, Reply always
U39/2
OS·WRITE
Transmission of character
f rom con t ro 11 e r to TTY complete
U39/4
RBA. READ
Character from TTY i n con t ro 11 e r
and ready for transmission to CPU
U39/5
Decoder output
(U58/8)
Director function sent from CPU to
controller when exp ress ion in note
i.s high
Te·rmi na 1
I
NOTE
Sheet 5 on page 5-389 differs from some older
revi"s ions in the following areas:
*zone 0-2: U57/9, R/R CLOCK, is connected to
U5/9 (zone A-4)
*zone 0-2: TPl2 is connected to U57/9.
5-388
89633300 E
...
0.1
,,~
00
\.0
a-
IoN
IoN
IoN
o
o
R/R CLOCK
IT1
,i'
IOm-·
o
o9
,
Q.
Q •
.-
o•
Q4~imi
1111 I 21
o7
. . ) PZIlaIl
I
'r
lOll.,!)-"
l
-- (iIu)4
~
ADDRESS DECODING - REPLY/REJECT LOGIC
V1
I
\,oJ
00
\.0
" '~ ..AlII
4ocK ro---qUM'
DETAILED LOalC DIMRAMI
T.T. Y CONTROLLER
I \,; I .....400 I'd I
=
i
\It
TTY CONTROLLER (drawing 89616400, sheet 6)
CONTROL AND INTERRUPT LOGIC
Function
This circuit generates an interrupt signal for the End-of-Operation (E~P),
ALARM, DATA and Manual interrupt conditions.
It also contains a number of control fl ip-flops and generates the associated
signals:
Signal
Fl i p-flop
READ/WRITE, M0DE
DATA READ, L~ST DATA
MECH BUSY
WM0DE,
RM~DE
~, L~ST
DATA(LD)
BUSY, E~P, DATA,
MECH-BUSY
Inputs
SIGNAL
ACTIVE
MNL -INTRPT
MNL - IR:T~~T
CONNECTOR
PIN
FUNCTION
P2A13
PIA05
) Manua 1 Interrupt
J from Progral1ll\er I s
console
6
6
c-4
c-4
P2B25
P2A12
Character Input
Interrupt (E~P)
6
6
A-3
0-1
L
L
LOCATION
SHEET
SQUARE
Outputs
..&.-
CHI'
INTIL
NOTE:
, 15-'390
L
L
,
Sheet 6 on page 5-395 differs from some older revisions in the following areas:
* zone C-3: the Manual Interrupt flip-flop is U5/11, type 242H
* zone c-4: 6.8NF capacitor C16 is not connected between signal
MNL INTRPT at P2A13/PIA05 and ground.
89633300 E
(Drawing number 89616400, sheet 6, cont'd)
TTY CONTROLLER
The Interrupt Circuit
Each of the interrupt conditions (DATA,
E~P,
ALARM) is set by the
corresponding director functJon (A02, A03, A04) together with the signal DFEN,
and is latched in the corresponding D-type fl ip-flop (part of U2). The
interrupt conditions are reset by the Clear Interrupt (CLEAR).
(U2) are clocked by DF=WRITE·MC.
The latches
When the latch output (interrupt enable)
coincides with the corresponding signal, an interrupt signal is produced at
the output of U6.
The Manual Interrupt signal (from the MANUAL INTERRUPT
pushbutton on the Programmer's Console) sets the manual interrupt fl ip-flop
(U5) and also sets the interrupt signal through u6.
The following table
summarizes the action of this circuit:
Note:
Interrupt
Condition
Director
Function
Gate
Data
A02
U36/6
U2/4,3
E0P
A03
U21/8
U2/ 12, 11
ALARM
A04
U21/6
U2/5,6
Manual
---
U5/11
---
ALARM INTERRUPT = PE·DATA·READ +
L~ST
Latch
Terminals
I
I
DATA
that is when a parity error is detected on input data or data is lost.
The output of gate u6 is used as the interrupt status bit in the A/Q channel
data path logic circuit (sheet 2); its inverse (U56/1l) is transmitted to the
CPU.
Control flip-flops
The Read/Write gate (U36/8) forms a latch with U2/13, 14 to produce the
clocked mode signals
WM~DE
and RM0DE used in the control and teletype
interface circuit (sheet 3).
It is set by the director function A08, ANDed
with E0P and DFEN and reset by RESET from the address decoding and
reply/reject circuit (sheet 5).
89633300 E
5-391
TTY CONTROLLER (drawing 89616400, sheet 6, cont'd.)
The Data Read flip-flop (U43) stores the information showing that a character
has been received from the periphe~al device. It is preset by the function
DA·RM~DE·ID·MECH8USV
Where
RM0DE means that the controller is in Read Mode
DA is an output of U22 in the A/Q channel data path logic
L0ST DATA,(~ is an output from flip-flop U9 and means that a
character has been received by the controller and not transferred
to the CPU
MECHBUSV (output from flip-flop U43) means that the controller is
sending a character to the peripheral device.
The data read flip-flop is cleared by the rising edge of the signal
from u28 and it is asynchronously cleared by CC0N+MC or L0STDATA atR.
The flip-flop Lost Data (U9) is clocked by the rising edge of the signal.
DATAREAD·MECHBUSY·0R
toutput of U29) , where 0R comes from the UAR/T of the A/Q channel data
path logic.
The flip-flop is cleared asynchronously by CC0N+MC or RM0DE (u60/8).
The signal
L~ST
DATA (LD) is used as a status bit in the A/Q channel data
path logic.
The MechBusy flip-flop (u43) is set while data is transmitted to the
controlled peripheral and is cleared when the transmission has been
completed and the WRITE signal is no longer active.
Its actuating signals are as follows:
Set:
Preset:
Clear:
I
5-392
by TBMT from the UAR/T to the A/Q channel data path (sheet 2)
CC0N+MC
by rising edge of E0C·TBMT.RDEN·WQEN
89633300
E
TTY CONTROLLER
(Drawing number 89616400, sheet 6, cont'd)
Miscellaneous output signals are produced using the signals of the above
fl ip-flops.
These are:
Signal
BUSY
Equation
Description/Remarks
Origin
LOST DATA + CHI
to UAR/T of A/Q channel data
path (sheet 2)
U29/6
READ'DATAREAO
Character Input prevents the
most significant field of
the CPU A register from
being changed during a read
data operation
U52/8
MECHBUSY + DA'RMeDE
Status bit
U59/11
Status bit (End-of-Operation
interrupt)
U24/12
DATA
Eep·WMODE + DATAREAD
Status bit (data interrupt)
U42/6
PARITY ERROR
PE·DATAREAD
Status bit (data interrupt)
u8/11
ALARM
PARITY ERROR
Status bit (alarm interrupt)
u8/6
Active after transmission of
u28/6
D$.·WR ITE
character used in the UAR/T
of the A/Q channel data path
(sheet 2)
timed by 1.3 psec signal.
NOTE:
OS = E'P
89633300 E
WMODE WDEN + DATAIN RMODE MECHBUSY (1.3 psec) at U27/8.
5-3931394
I
II (AZ)
,
48
_PF~'~NL--r-_ _ _ _ __
ex>
I.D
I "'I
2.5fAB'
~ AZ
""'
w
w
w
~ .. '..
o
o
R[II.S.Of< RECORD
0, .
• ':> -
,to'. ,
Iv .. ,.r I 0 ... ·
ICHICD •
.,.~
'-@2
100 ENABLE
"NL
G>
I INT
1''' "P'"
+5V~
24 2H
r'r~~~NA~~~~~t~~~-fT--1T~M~N~l.~1N;T;===:::l;±f11 1t - ~O:~E
10.
FF
(~
EOP
rOEOP ENABLE
31
~
2
'.
iiNl
R"'DE
~~
144
iiiii.
iffiiji'J
49
I
.0'
U43M
"ECH BUSY
LOST DATA
l
1~5 .-+
,.30
47
I
LOST DATA
0') 2
2(Gr--+=---'-I
305 )
I
•
-----------.
~I
~
, "I
V1
I
W
I.D
V1
"U
~
L ____________~=~=_
I
(~"\35
P2b~'l
- ,.UIe
""
srJsl>
146
.f/VFL )-f2&'l.
~
EtlT)~UII!I
0"
~
1154
00
\,0
voc
ItO
W
W
W
"
,8
•
PINe
<'JIIDt
P!J2I (.e om ~
....
~
Ij
aREAl( PflINT LfGJC
o
o
!ICy
DETAILED LOGIC DIAGRAM
T.T.Y CONTROLLER
I'T1
"
A
REV
O~
C'l
09
ECO
C.K4-IO
I
REVISION RECORD
I DRFTT DATE I CHKD lAPP
DESCRIPTION
tlEOftAWN PElt CoDe. STDS
CK~J2
c.\<.~3a
07 CK'7co5"
03 CK"'~'t
10 CK795
~
~~
s \
v-. ,
\.~
CK8Se
A CK \, 79 P.ELEASED CLASS A. ALL +5V R.EPL. BY vee..
Il
s",
B
CK.\2.'2.~ O~F-S\-\EET
C
cKI241 CK\229 CANCt:.LLE"D. COMBINED
J)
cK928
E
CKI2~8' 'U22 -19!U'-C)-4 fEL~TEJ).
CODE 'DENT
C
REV
DWG NO
89616400
SHEET
J
9
.A.
89633300 E
5-401
TTY CONTROLLER (PWA 89947600, logic diagram 89616400, revision H)
The logic diagrams and logic descriptions for PWA 89947600, logic revision H,
pages 5-402 through 5- 40 9, are basically the same as for PWA 89967400,
logic revision J, pages 5-374 through 5-401.
The sheets of logic revision H are located on the following pages of this
manua 1 :
sheet
page
2
5-403
5-404
3
5-405
5-406
5
5-407
6
5-408
7
5-399
8
9
5-400
5-409
PWA 89947600, logic revision H, differs from PWA 89967400, logic revision J
in the following areas;
Sheet 1: Revision H matches PIN 89947600
Sheet 2: *zone B-4: U22/20 is connected to U22/2l (zone C-l)
*zone C-3: AND-gate type 140 is U5/2,1-3
Sheet 3: ,'tzone B-3: the TTS fl ip-flop is U7/11, made up of two type-140 gates.
*zone c-4: the signal atP2A10 is not identified.
Sheet 4: *zone B-1: AND-gate type 140 is U5/5,4-6
Sheet 5: *zone c-4: U39/6 is connected to U5/9 (zone A-4)
*zone c-4: TP12 is connected to U39/6
Sheet 6: *zone C-3: the Manual Interrupt flip-flop is U5/ll, made up of two
type-140 gates
'~zone
c-4: 68NF capacitor C16 is connected between srgnal MNL INTRPT
at P2A13/P1A05 and ground.
Sheet 9: revision record H
The logic descriptions for revision J also apply to revision H.
I
5-402
89633300 E
00
~
0FF SHEET REFERENCE
0'
\oN
\oN
\oN
o
o
J"T1
OFF
SHEET
~.~.
~.
o
8-4
8-4
A-4
F
G
J
K
I
L
loll
N
I
o
I
I
R
5
I
I
T
I
p
.
A-4
I
I
C-I
I
I
C-3
8-3
8-3
8-3
A-3
e-2
W
)(
Y
I
I C-3 I C-3
I 0-2 I 8-4 I
I I
I
C-2
8-2
8-2
8-2
8-1
I
I
I
I
I
I
C-2
I
C-2
0-4
0- 3
I- -_.,•. BH'-~
A-4
1---.
8K
~.~N_~
BP
0-4
-.--.-
8-2
8-4
f
f
I
I
B-2
=~ == f~lf:l+=~t~1itt~- 13
~
~!'A~
~.
.;~~
.vee
"40
lK
@~.vee
RI'
I~
V1
I
~
o
-
@:J~vee
®H4
RI2
IK
.....
R3S
6
C I
B-4
C -I
0-4
C -3
C-3
8 -2
0-2
C -3
C-2
C-I
8-1
--
BO
f:: .-.
NIITE
8-1
8-1
-
A-4
A-3
RESIST0RS
& -..
II<
IK
RIS
II<
II<
A •.,--
8
'--- - A-2
B-3
B-3
0-2
C-I
C-I
C-I
A- 3
0-3
I
ARE
025 WATT
8-3
5%
PIN 89947600
RI4
,~ee riil\...~~'L.
~vee
R8
R35
0-3
B-2
A-2
A-2
A-4
-
--
T
0-3
• C-4
B-4
8W
U~MARKED
7
C-I
0-3
B-3
0-4
r---
BU
BV
ALL
T
B-2
B-2
0-3
Bioi
0-3
B-4
5
0-3
BL
C - I . - l .. _ _ ~
C-I
A-4
4
0-1
3
AX
AY
AZ
IBA
- ---- -----f--_ 8. 8 _
BO
BF
8G
0-2.
C-2
I
AL _ _ _ C.:I
AM
C-I
AN
A,.
AQ
2
AV
C-2
C-2
C-2
I
C-3
8-1
0-1
0-1
C-4
C-2
C-I
C-I
8-1
AK
f
8-4
C-2
8-<1
C-2'
8-1
8-1
f
C-3
A8
AC
I
f
8-1
A-3
C-3
C-3
Z
AA
AF
I
8-3
8-4
A-4
C-4
A-3
I
I
I
---I--- -
C-3
I
AD
8
A-3
U
AJ
f- -
C-4
C-3
8-3
7
6
8-1
v
~ ___AG
t..=-·
C-I
A-4
C-3
. L~CATIIIIN
5
SHEET
4
8- I
2
3
8-4
8-4---'
REFERENCE LETTER
A
8
DETAILED LOGIC DIAGRAM
T.T.Y CONTROLLER
®-~vee~.~---ovcc
~'lCC ~ ..... vce
RI
IK
~ ~-'----"WJ
IIi
X.Y]
~
3
)iGI
~'?/
~..
U~3
I ~
9 I--
:~
AA~
~ 146·R
I
-
@r~
I
":~~ ~~~
lVCC
~.
,I
~'
DATA PATH
PIN 89947600
~~_____~~I~r------~6
DETAILED LOGIC DIAGRAM
TTY CONTROLLER
00
\..0
'"
W
W
W
o
P2B30
o
(
.----_----'t-4Ivcc
ITI
R26
/
1.211
Q4
R25
4,7K
TTY-KT.) r'MW
R32
~~.oP2AZ6 TTYPR
......
-
P
..c:.*
..
:1
2N2901
••
CII5
.41111
1"9
"'''0
(MOTOR ON
~3
P2A3p
(CRT-REC
.i
I~
13
L -_ _
-12V
,
~
'19V ) P2B27
E
R33
150
YoI'.
1,12V
CR2
IN
~~
'If
r- .
I I C4 I I I
'T I
~
-
lC~
'In'
r
I "oF I Ice
C6
C1
6Bn'
68nl
1
I
-12V) P2A24
I
I I I 1 I~
,~C9
1 IC~
61nF.
68nF
I I
ell
6BnF
CI~
68nF
CI2
V"I
I
-
CONTROLLER/ TELETYPE
V"I
---,_., '-A'
INTERFACE
I
-:-
6BnF ICl3
68nF ,,",C14
!'t68rr
"!.
O
I
63
c2
.t:-
1~9A
I
T.
1.+
61
1
1-!2V
C3
4i8~F
55Y
~
j
OETAILED LOGIC DIAGRAM
TTY
CONTROLLER
-
•
-'
b=:
•
~IIECOM)
:t " ..
.,.~
.,'1. ..
' .......1_
V1
I
'5
0'
EKTCl.K
:l
>.P2Aot
II
~ ~~~------R56
IK
vee
........
~~~A'
~VCC
..
It
.....
,..
11M
T.
...L CI9
471'1'
I~
,
YI
~
12.2222
MHZ
'I'~
lin
I. ••
~
t
/.~
It'3
Ie
A
~
110
I-
CD
I.
1.0
0'
\N
\N
\AI
o
o
IT!
OSCILLATOR/ BAUD
RATE SELECTOR
DETALED LoeIC DlAIIIAIl
T. T. Y CONTROLLEIt
00
\.0
(j'\
Vol
Vol
Vol
o
o
R/R CLOCK
ITI
.=I'
'\
"I
11: ) roo.....
Me
PIN 89947600
PIN
~
V"1
I
g
......
ADDRESS
DECODING
- REPLY/ REJECT LOGIC
DETAILED LOGIC DiAl RAM
T.T. Y CONTROLLER
I
I "I
•••••00
i
1,» I
--
-
•
11£1115'0lIl RECOIID
• (41
\.11
) on!!
I
I &~
't.
2.S~~)
~
':> ... If'
• ,.- '"
(.... ,.tIOA·
ICHlCD • •"
I .. ,
r&;;' ... 2
4&
.J:-
t
o
ex>
VA'A
,
--@2
10D ENABLE
MNL
lINT
1'(1 .., ..,'
Ciiii
lOEOP [!!ABLE
-:l\....
,
...
~
_
ell
....
nr
I
~
w
( iiiTit
EOP
EDP
WMIDE
MANuAL.
I NTEflR,.\lPT
..L -
FF
f
MNllNT
~ PIAl.
IIM'OE
144
. .".,
I
I
MECH 8USY
-.30
CONTROL AND
INTER RUPT LOGIC
1
CCON + Me
•
<~ R )
35
ex>
1..0
0"
W
W
W
o
o
I'TI
.~
.
"t.AU
rwt."'~
S
I
..,.
146
"--,
2.
L
lOBs
. p2e<,_~
U52
204
8__
.__
~Oii
f!!m
CO"PUHR~ lT~
DETAILED LOGIC DIAGRAM
TTY CONTROLLER
mTIl1Ulli1M.J
~
PIN 89947600
PIN 89984700
PIN 89976400
J
..
REVI
O~
C'
Oa
REVISION RECORD
ECO
CK4-IO
1DRFT1 DATE I CHKD lAPP
DESCRIPTION
~e:DftAWN
PEr(
c:.oc. STpS
cK'12
C.K"38
07 CK7foS
09 c.K.. 7<8Lf10
CK7~5
II
cK8Se
A
CK 1'79
S\
t-\
\,.~
'< 'rc..
B
RELEASED CLASS A, ALL +5V R.EPL. BY vee.
CK\2.2~ O~F-S~EET REF "BV" ADDE D. SJ.\2. AP REPL B'( V"S
C
CKI2.41
U~8 WAS 2.J3H. FITS ASS,(
8994-2.700.
CK\2.2e CANCELLED. COMBINED WITH CKIZLtI.SAM!:
APPEAR 1N CK 12.28 APPEAR IN cl(
C~ANGES THAT
\,2. Lj. , •
D cKca2.8
E
F
G
'l4
f<.EVERSE
cHANGES To
us
I, U7 IN ECo ~12.
U22 -19!U'-O-4 .e.EPLACES UZ~-J~7U~S-~ 2 j u2.!:) -8/
U("'8-1)2 f<.ePLAe'ES U2S-VU 4-b:-.9 j U"'~-/2./U4-'-.9
REPLACES u~e-12/u~O -4-.
CK 142.2 FITS PWA ~99'7<;'!fOO.INcoRPoRATES REWO~.K OF
CKI2.~8l.pEL.ETES OSCILLATo/'Z P-EWCRK 01= eK.eS's.
u~e IS 7'HH I .
C.KI2.~8
CKI'+If~
FITS PWA 8998Lf-700. INcoRPoRATES REWoRK
15 7'+ H II .
~
OF
ct<.I2.~e. U~8
CK
\'+ 4-7
"eVISION
R.ECORD: U"8 WAS 213 H.
FITS
PWA
GM .
of
T.T.Y. CONTROLLER
I
CO()£ IO£NT
C
'OwG NO
REV
896' 64-00
SHEET
H
9
A
89633.300 E
5-409
I
TTY CONTROLLER (PWA 89984700, 1ogi c
~ i agram
89616400, rev i s ion G)
The logic diagrams and logic descriptions for PWA 89984700, logic revision G,
pages 5-410 through 5-415, are basical1~ the same as for PWA 89947600,
logic revision H, pages 5-402 through 5-409.
The sheets of logic revision G are located on the following pages of this
manual:
sheet
page
1
5-411
2
5-412
3
5-405
4
5-413
5
5-407
6
5-408
7
5-414
8
5-400
9
5-415
PWA 89984700, logic revision G, differs from PWA 89947600, logic revi s ion H,
in the following areas;
Sheet
Sheet
Sheet
Sheet
Sheet
1 : Revision G matches PWA 89984700.
2: *zone A-3: AND-gate u68 is type 213H
4: *zone C-3: AND-gate u68 is type 213H
7: *zone A-3: AND-gate u68 is type 213H
9: revision record G
The logic descriptions for revisions J and H also apply to-revision G.
I
5-410
89633300 E
'IF
ex>
1.0
OFF
W
a
a
IT1
SHEET
SHEET
REFERENCE LETTER
2
A
B
B 4
B-4
I __
r-.
f--..
D
3
L0CATI0N
4
5
. 6
F
A-4
A-4
J
K
C-I
A-4
B-3
B-4
L
C-3
C-I
C-4
C-3
B-3
C-3
I
I
I
P
o
"
s
I
9-3
B-3
A-3
T
I
I
U
v
w
)(
I
I
y
I
C-3
0-2
C -2
AA
C-2
I
I
~- :~
I
_
C-3
--- ---
A-4
C-2·
C-I
C-I
B-1
Rf_y':_ ~- ~
2.1 ~ Iif .f). G: 7 81"9
J
AA A A A AA A
"
B B A B AI
I...... B A
~ .D D B p, DBA
C-2
C-4
I
I
I
C-3
B-4
B- 4
f--
B-4
I
I C-2
I
I
C- 2
C 2
I
I
I C-2
I B-2
I
I
0-4
B-2
BK
BL
C-I
~_
I
1--.!,,_-..:2=---1-_ _+
B-1
------f----~-:::~f___
R40
IK
~.vee
~3~vee
R36
®--
IK
RJ
IK
R68
BV
BW
~
--.t'..
NflTE
·.----tvcc @
""..,
I
vee
I . ., 1 H
'l'
0-3
1
C-4
I
B-3
B-4
0-3
B-3
0-2
B-2
C-I
1 ::: 1 ::; 1
ARE
025 WATT
5%
PIN 89984700
JO NOT SCALE
DRAWING
I
:4'\j
¥Al! RIA
.... c:.,.
..
I
,~,
> .',' N '
. . ~'
1;-":._
IU.
'.0 en
,n
..
I~i~.:
0-4
I
B-3
RESiST0RS
... , T TLE
IS.TiLl.lda itS.
1~lhlli\lJli1J1lI
:
:~,-~
gl§.
~~
~
0-3
A-3
ALL UNMARKED
~
0-3
B-3
B-1
A-4
mIT COMPUTfRS lTD'
II<
B. t.
Ed ¥:- =- ¥ ~
vee ~~---
DETAILED LOGIC DIAGRAM
T.T.Y CONTROLLER
I" ,"' Ic I 896~~:~~
5'1~fr
I ()~
E
I
V1
I
J::-
r'
_·-· .." ....t) P2AZ2
:~ i:
-> :::::
... >
'.
H6
-r_T+-____...uJ·
~ ~____
__
, ,.
Z 3.5
.
~
AA5.6
6~
ABS.
~
AO
AC S
I
lvee
IiI
~
"~
."
b
.IS
E.VEN PARr-f'2A28
N
U22
j--@3
·T"
~6
. ,. x.vu
4~
6(8)"""",' "
-,
UNlIT
s@..ti-~~
3/"
\!~
6
LtftttE-
I~
l
l
&
0"
~
.:
W
W
W
o
o
IT!
t
!i
A/Q CHA NNEL
TlW"
~
e
DATA
P2BI9
(m
~~
PIBIS
50> P2800
L® .
B
f
8
"
w
\AI
m
32KW >PIIO
•
I
~
fi
I
~:::
~
o
S1ii
p.LI::I!!IlL..<'SEN
GfilCS>".Idill""'-'''I
C..
-~.
~
vee
~2:*"m
"
203
I"
'EL)P2A07
RNI P2804
I
I'-
II!& ~
II
'j
8REAKPfilINT Lfil61C
DETAILED LOGIC DIAGRAM
TTY CONTROLLER
.,
..
PIN 89984700
PIN 89976400
..
ECO
REVI
O~
C.K4-IO
O~
cK'12
CK"3S
C'
REVISION RECORD
1DRFT1 DATE 1 CHKD lAPP
DESCRIPTION
REDf'tAWN PE~ CDC. S"'OS
07 CK7C.S
09 CK....,~~
10 CK795
1 I cK8Se
~~~S
\
'"
\..~
\
CK l \'79 "ELEASED CLASS A, ALL +5V REPL. SY vee..
B CK\2.2«e O~F-S~EET ~EF' "BV" ADDED. SJ.\2. AP RePL B'{ v,s
A
U~8 WAS
J)
2.J '3 H. FITS ASS,! 9994-2.700.
cKI2Lf-\ CK \229 CANCeLLED. COMB)NED WI"'H CKIZ4-I,SAMe
C"ANGES. THAT APPEAR IN CK 12.28 APPE.AR IN cK
\ 2.Lf. \.
cKca2.8 /tEVe.RSE cHANGES To us £. U7 IN Eco "2..
,
E
C.KI2.~8
F
rt-EPLAC.ES u~e-J 2/u~O -4-..
.....
FITS
PWA S997"Lfoo.INcoRPo·RATES REWO~K OF r'III
CKI~2.2
C\<.I2.~8l.pELETES OSCILLATo1Z "ewoRK O~ CKtl5"a
C
U22 -19!U'-O-Lf f<.EPLACES UZ~-J9/u"e-~ 2 j u2.3-8/
U'=oS-I)2. REPLAcES u2.S-&/U4-b-.9; U"~-/2./U4-'-.9
LJ~e IS
G
7'+,", II.
CKI'+'+(;:. FITS PWA 8998lf700. INcoRpoRATES REWORK OF
c.KI2."e, U"8 IS 7", H I I .
,
I
.
PIN 89984700
LTD
oF
I
DETA'LED LOGI C
T.T.Y.
I> GM.
CONTROLLER
CODE IDENT
C
REV
DWG NO
896164-00
SHEET
G
9
.A.
89633300 E
5-415
I
TTY CONTROLLER (PWA 89976400, logic diagram 89616400, revision F)
The logic diagrams and logic descriptions for PWA 89976400, logic revision F,
pages 5-416 through 5-419, are basically the same as for PWA 89984700,
logic 'revision G, pages 5-410 through 5-415.
The sheets of logic revision F are located on the following pages of this
manua 1 :
sheet
page
2
5-417
5-412
3
5-405
4
5-418
5
5-407
6
5~408
7
5-414
8
5-400
9
5-419
PWA 89976400, logic revision F, differs from PWA 89984700, logic revision G,
in the following areas:
Sheet 1: Revision F matches PWA 89976400.
Sheet 4:
>'~zone
c-4: The oscillator circuit contains 47 picofarad capacitor
C20 and 180 ohm resistor R62 in the path of crystal VI, and 0.47
nanofarad capacitor Cl8 to ground, on the input line to the base
Sheet 9:
of transistor Q6.
revision record F.
Except for the change in the oscillator circuit on sheet 4 described above,
the logic descriptions for revisions J, H, and G also apply to revision F.
I 5-416
89633300 E
...
00
eFF SHEET REFERENCE
U)
(J'\
IoN
IoN
IoN
OFF SHEET
REFERENCE LETTER
o
&
o
I
L__ ~~O
1-4
A-4
J
C-I
A,-4
G
I(
L
N
I
I
,
I
o
I
I
I
i
I
I
I
I
"
•
T
U
v
W
It
Y
I
1--_ Z
AC
AD
AF
SHEET
4
I
A-3
A-3
C-3
C-3
C-3
0-2
I
I
C-2
C-I
C-I
I-I
B-1
B-1
AJ
I
8-1
L!lCAT~
5
I
B-1.
6
I
7
8
8AIBSIA 13IA
D D D BlB I'D BIA
-f- _
E E DIBIB E
&-4
C-2
B-1
0-1
0-1
B-1
2
I
C-3
I
1-4
I
1-4
I
I
I
C-2
I
I
I
I
I
I
C-2
I
AZ
B-4
B~
C-2
8-2
B-2
B-2
I
0-4
I
0- 3
I
L=:~
BL
I
C-2
I
A-4
~~
It<
-
--,
®
~12
c~
B 2
BW
NIHE
ALL UNMARKED
RESIST0RS
~r
~
0
~~
~~8
~
~
~vcc ~ ..... vcc
@
v.*
Ivee
;
~I!i
0-3
C- I
I
IE: I I
I
~
0-3
C-I
H
0- 3
8-3
ARE
025 WATT
5%
pIN 89976400
"
t
)Q
.... A1
JO"
Iiij;l:iji~'~j I:: :o,-~
NOT SCALE DRAWING
I ,., I
H~II\
"I
T TLE
DETAILED LOGIC DIAGRAM
T.T.Y CONTROLLER
I "C'
1:""1._ "'~_1~·.!..._
;.i>~
I~I·
B-2
C-2
C -I
8- I
I
HBIT COMPUTfRS lTD I ••• '
IK
C -3
*
I,,~__
IK
a
7
I I I r~=:
~8-2 IE: I
IA-,~ IA-2: I:=~ I,-.~~~ I
RI.
1M,......,...
...
•
""
IVCC~VV~VCC
R~
R8
--v¥'----oIVCC
I
I A-4 I
I A-3
BV
~
®-~VCC®--~---P2Aot
I
ma:;~
II
15
~::t.
Hl>J'
R56
•
II(
...... lvee
-
to
._H07..t - -..
~
~
5~.K
.,
lIZ
c.e
"2,-
I
/
Hlr~ czo
V ....,pF
0.£+'7 NF
•
~
1~222
IllS
~'K
:T\
T..
~
I(
.
10
A
~
113r.r;l'2
Ii![
110
I-
' 'Il00
00
~~c
\,0
'"
w
w
w
R
o
o
f"I'1
OSCILLATOR -
BAUD RATE SE LECTOR
~
l
DETALED LOItC DlA.AII
T.T.Y COIITROUD
PIN 89976400
,.
REVISION RECORD
REVI
ECO
Ob CK4-IO
Ott3
07
C'
CK7~S
09
cl<..7C8lf
I
RE:Df<.AWN PE~
c.oc.
STDS
cK'12
cl<~3a
~ ~c,
10 CK 7<65
I
I DRFT I DATE I CHKO lAPP
DESCRIPTION
S,,,,
,\..~
I CK8S6
A CK l 1'79 "ELEASED CLASS A. ALL +5V REPL. BY vee.
REF "BV" ADDE D. s~2. AP REPL B'( v,s
B CK\2.2.'2I 01=F-S,l-'IEET
u~a WAS 2.J3H. FITS ASS,( 9994-2.700.
C CKI2.Lf-1 CK\229 CANCelLED. COMBINED WITH CKI2lfl,SAME
C\-\ANGES THAT APPEAR I N
\ 2.4}'
etc:: 12.28
APPEAR IN
cK
"'2..
D
cKca28
f<..EVE.«..SE CHANGE s To u5 I, U7 IN ECo
E
CK12~8
U2.2 -19(U'-O-Lf t<.EPLACES U2.2-19/u~e-I.l2 j U2.3-8/
lJ~ca-IJ2 «.EPLAcES U2S-&/LJ4-b-:.9 j U"~-I2./U4-'-.9
F
REPLACES UbB-12/u~O-4-.
CKILf2.2 FITS PWA a99'7"lfoo.INcoRPoRATES
CKI2.~8
u~e IS
& DEL.ETES
7*J..l/1 •
REwo~K
OSCILLATo1Z P-EWC~K 01=
.....
OF
eK.ess.
~
r-
PIN 89976400
LTD
oF
I
CODE IDENT
DETAILED LOGIC DGM.
T.T.Y.
CONTROLLER
'REV
DwG NO
C
896\6LtOO
SHEET
F
9
A
89633300 E
5-419/5-420
I
ENCLOSURE POWER INPUT
The power supply and power input wiring of the main computer enclosure
(equipments AB107/AB108) and that of the expansion enclosure (equipment
BT148) are identical.
A Power Supply Input-Output Wiring Diagram shows the input power distribution
in the equipment. The power line enters the enclosure through the line filter
unit and is taken to the power supply unit (PSU) and the blowers through
the PSU terminals. The PSU generates all internal suppl ies for the equipment.
The power supply wiring diagrams in this section apply to the fol lowing
different equipments:
DRAWING NO.
89762200
PAGE NO.
EQUIPMENTS
5-429
AB107-A04 to A12
AB108-A04 to A12
Part of BT148-A06
BT148-A05 and down
89942600
..},
5-431
AB107-A13 to A19
AB108-A13 to A19
Part of BT148-A06
89911800
"k
5-433
AB107-A10 to A15
AB108-AlO to A15
BT148-A07
5-435
AB107-A16 and up
AB107-C
AB107-D
ABlo8-A16 and up
AB108-c
AB108-D
89601601
BT148-A08 up
BT148-c
BT148-D
The wire I ists in section 9 give details on the interconnections.
Tr.e I ine filter unit and the power supply unit are described later in this
section.
*In using WI ring diagram 89911800 for the programmeris console connections
in series A13, A14, A15, substitute the progr3rlmer i s console connections
of wiring diagram 89942600.
Note also that al I series have one forced-air blower in the power supply
and three axial fans installed in the top of the enclosure. Type identifiers C and D have two more fans, installed in the bottom of the enclosure.
9633300 H
5-421
I
THE POWER INPUT CIRCUIT
The input circuit of the enclosure (Line Filter Unit) is mounted at the top
center of the rear panel. See figure 3-7 and the detail on this page. The
following table summarizes the components and their functions.
FUNCTION
NAME
DESIGNATION
J1
Line power socket
Accommodates the 1 ine power cord
Fl
Input fuse
Line protection
F2
Battery fuse
Battery protection
S1
AC line switch (on/off)
Appl ies ac 1 ine power to the equipment
Line filters
Isolate the equipment from surges
and noises on the ac line
Margin test socket
Used in the Margins test
(Refer to section 6)
FLl, FL2
J2
AC Power
AC Fuse
SIr"witch
Socket for
Power Cord
Battery Fuse
OFF
JI
5-422
eA
o
J2
IAS8
89633300 F
POWER SUPPLY UNIT (PSU)
. The PSU is an autonomous assembly mounted at the top of the front door of
the AB107/AB108 main computer enclosure and in the same place in the BT148
expansion enclosure. The PSU is part of the equipment which it supplies.
This sheet summarizes the circuit diagrams showing the power supply
~nit;
the diagrams themselves are. given in the following pages, together with a
brief description of the circuit functions. All connectors for connecting
the PSU to the rest of the AB107/AB108 or the BTl48 equipment are brought out
on the power supply connector panel on four terminal strips: TB1,TB2,TB3,TB6.
These terminal strips are shown in a figure on one of the following pages.
The interconnection (wiring) diagrams show the interconnections between the
main units of the power supply, including terminal strips, for all series
of computers in the field.
The power supply unit receives the main line power through the input circuit
mounted at the rear of each enclosure. This input circuit, as well as the
general power input connections to the enclosure, have already been presented.
The block diagrams of the PSU and their descriptions appear in section 4 of
this manual. The diagrams are repeated in the following pages for convenience.
Most of the circuitry of the PSU is mounted on two printed
c~rcuit
boards
within the power supply assembly, as follows:
BOARD DESIGNATION
DRAWING NO.
ASSOCIATED CIRCUITS
High Power (HP)
and Control
89657700
Ac-to-dc converter, V regulator,
cc
+35V preregulator, Protection and control
circuits (except individual current limits)
Low Power (LP)
89640800
Regulators, individual current limit circuits, reference voltage generator,
battery charge circuit
WARNING
The power supply does not use a main isolating line-transformer
at its input. Its circuits between the ac I ine input and the
isolating networks are therefore at line voltage. Do not handle
the PSU while the computer line cord is connected to the ac supply.
89633300 F
5-423
V1
I
.l:N
VCC
.I:-
AC
to DC
VG C
+
AC~Line
Pow.r
~
Regulator
Pr.regulator
to--
~
*
AC Line
Cord
auxiliary
----
'--------'~
~
25 vdc
---
Regulator.
auxiliary -7vdc
r-"
r'-'I
Cha ....
Ground
Logic
--- Ground
--.
35vac
35vdc
Input
Circuit
»
35v
Converter
Circuit.
Protection
overcurrent
VCC
--t- ;;;f~;;;'--
Reference
G.enerator
+ Sense
Battery
from
bock
V CC
Terminal
Charger
and Batte ry
Crowbor
plane
main
indicated
*
00
'-D
C7'
W
W
W
power
by
The Input
port of
t
f
Note:
The
w
flow i.
Isolating
Diode
Bott.ry
F3
Battery
thick line.
Circuit i. not
the Power Supply
Front Panel
DC
POWER
I--~
":"
I
-=
o
o
.."
POW E R
5 U P PLY
B L 0 C K 0 I A G RAM
FUI.
Equipment
GD611-A
( Optional)
VBB
VCC2
-12v
-5v
~30V
Un regulat.d
...
I........t - -
L -____________~------------------_+-------------------------~~)~----~
~.--------.
VSS
-SENSE
From bock plan.
ground terminal
POWER SUPPLY UNIT (continued)
COMPUTER DC SUPPLIES
Supply
No.
Designation
Nominal voltage
volts
Nominal
Current
Remarks
1.
V
cc
+5
35A
R
2.
V
cc2
+5.3
3A
R,M
3.
VSS
+16.7
5A
AB107/BA20l-B,R,M
VSS
+19.7
5A
AB108/BA20l-A,R,M
4.
VBB
VSS + 3.5
40mA
R, M
5.
-12V
-12
100mA
R,
6.
-5V
-5
lA
R
7.
+30V
+30
300mA
unregulated, M
8.
battery
cha rge r
200mA
cur rent regulated
Internal suppl ies
+35V
+35
preregulated
10.
auxiliary
no. 1
+25
unregulated
11.
auxi I iary
no. 2
-7
unregulated internal
supply
9.
NOTES:
R:
regulated supply
M:
supply to the memory only
The tolerance on all regulated voltages is
The maximum permissible ripple is
~
~
0.5 percent.
2 percent of each regulated voltage.
See also table 6-1.
I
Use adjustment VBB to adjust VSS'
89633300 H
5:-425
POWER SUPPLY WIRING DIAGRAMS
I
These drawings show the circuits of the complete power supply units for all
computer series. The circuits accommodated on the two main printed circuit
boards are shown on separate circuit diagrams. High Power and Control (HP)
drawing number 89657700 and Low Power (LP) drawing number 89640800.
Terminal connector strips TBI, TB2, TB3, and TB6 on
the power supply con-
nector panel provide the connections between the power supply unit and
the other circuits of the computer.
A following figure and figure 3-5
show the connector panel. The following table lists the connections.
T
Connection
TB-l/J
Designation
Connection/Function
ON/OFF
Connection to programmer1s console
dc POWER on/off switch; controls
power supply operation.
/2
+ SENSE
Sensing wire from +Vcc connection
on enclosure back-plane (Figure 3-7).
/3
RGPWR
Power fail indicator signal for
Low Power Data Retention (LPDR)
operation (to Memory Control board).
/4
-SENSE
Sensing wire from logic ground on
enclosure back-plane (Figure 3- 7).
/5
-12V
-12V regulated supply output
/6
-5V
-5V regulated supply output
/7
+30V
+30V unregulated supply output
/8
VBB
VBB regulated supply output to
Memory system
/9
VSS
Vss regulated supply output to
Memory system
/10
VCC2
VCC2 regulated supply output to
Memory system
continued
5-426
89633300 F
I
POWER SUPPLY WIRING DIAGRAMS (continued)
TABLE OF TERMINAL STRIP CONNECTIONS (continued)
Connection
Designation
Connection/Function
TB-2/1
/2
/3
Main line voltage inputs from Input circuit:
Nominal Input to
Shorting 1 inks
voltage terminals
(terminals)
/4
/5
110V
/6
220V
3, 7
3, 7
1-2, 3-4-5, 6-7-8, 9-10
2-3,
5-6,
8-9
/7
/8
/9
/10
1
TB-3/1
Vcc MARG
/2
VBB MARG
/3
+ 30 V
/4
GND
Ground for margin circuits
+BAT
Battery positive terminal
TB-6/1
J
Connections for margin-tests on VCC
and VBB (refer to section 6)
/2
not used
/3
not used
/4
89633300 F
TEST
5-427
POWER SUPPLY WIRING DIAGRAMS (continued)
•
GND
o
•
•
Power
Supply
Connector
•
Panel (See also figure 3-5)
The main logic supply (V ) and logic ground are brought out on two separate
cc
terminals. A heavy gauge wire, suitable for carrying the high current of this
supply (nominal 35 amperes), connects these terminals to the backplane of the
enclosure.
The cabling of the other supplies also terminates on the back-
plane, as shown in figure 3-4.
Power supply internal connections are made on terminal strips TB4 and TB5,
mounted inside the power supply unit on the frame carrying
th~
output filter
and capacitors. Other components are shown on these drawings grouped according to the mounting positions within the power supply assembly. They are
shown in their functional relation to the rest of the circuitry in circuit
diagram 89657700 for the High Power and Control Unit (HP) and in circuit
diagram 89640800 for the Low Power (LP) Card. They are described in the following pages.
For instructions and explanation of enclosure grounding, refer to the installation instructions in section 6 and to the maintenance aids in section 7
of this manual. Refer also to the Site Preparation Manual, publication number 60437000.
5-428
89633300 F
4
3
00
I..D
0'
. USED ON
\.N
\.N
\.N
AB107-A04 to A12
o
o
AB108-A04 to A12
:c
PART OF BT148-A06
CABINET ASSY
BT148-A05 DOWN
CiND
UNIT
i"iRT-OFLINEFILTER UNITASiliiiL'i
I
I
~
PO
-"-':!:LI.lo...----i1 I
k 0 11£0- WHT
1I
I. . E_VU-WHT
__________
~2
[pAiiT
GND PLANE
Of (iiiOUNDPL ... NEA'Ssi1
I
IIIIUOOO
::~-WHT
~
1-.. ·
~wn'-
m.
. . u.
<6,),
!
)
~
I
!
V1
I
~
\.N
o
I.
•
GND
BLOWERS
fPAiiTOFTOPASSY -
I
I
I
I
I
.. I
L~!....J
&
-
,
ILK
I~f
:~: I'
L
_________
~
•
,
,
UM.U, OTl1E,""," .t:CIt"IED
1lI_IiIIION Aft' IN INCHLS
TOLlR"NeiU
I
"-
I
I
I
PROO. CONSL.61
A~
)E6
~
N
ClND
~
'-,---tl-):~O
I
t ------ -.J
.,I
.
I
0 IIWHT• PIIOG. CONSL
GND
vee ( :ILU
f(_If-!'!!::L~U_ _ _.-J
£5
r - - - - - i - - 4 ) [I
V1
I..D
BRAID
LJ__ _
[I
~ ::
I
I
-.J
WIRE
I
000
I
r~ ~- -:- t -BRN~ --I~-+--'
I IICC
0
I
'='
~...!.
~
Mil
i1:-1I£0
ii'1
I_JIO
LL~J
VEL-GRN
~V"A
J(BLK
rm~ ~-~ .~':
+~
II-~~.--~~
I~I
~~SI.!..._ J
LINE FILTER
BATTERY
PART NUIII8ER
I
r89773800-,I
Aee,It, _ _
ARI 'OlOEII POINTS ON THE _AIIIIIIIR'S CONSOLE PW
ASSY
TO
OW lID. 89780800 fOil
SUPPLY
DIAGRAM
......aoo.
~.nll
POWER
COMf'LETI: WIIIlNt Of
r.I .... ND
TN.
00
I.D
'"
W
W
W
o
o
USED ON AB107-A13 to A19
AB108-A13 to A19
PART OF BT148-A06
r----1I
PARTOFREAR~NECT.PANEl..
C,A8INET
r - - - - -I WIRE
I
1
:::z::
EI2
IBRAID
JT
:
A., ....
E II
II
'T)7.
lStLAS~!§. 2~.J
lEt~SI~G~J
LINE FILTER UNIT
rtAii"T-OFLINEFILTER UNITASSEMBLY - - ,
89880100
r"-- ------':
BATTERY
89650100
PI
250V/8A
I, JIL( ILK
_14
r
I!:!~'"
'_
L_ _
I I!!!
r-"""""",
LZ
~
powEll
ASSY
=
I"
y
~
.
-
-i-"---"?i,
.c:-
\.AI
V'1
-.I.
-.-
~~
H-iu-
~~
1..
1-
,I
,
I
I
~o
Ll
_I_
.. ~t
rc--,
L .........., .
r·-:; ....... •
'
I
i:a.!.,
lb~""~~"t:'
~
,or-,I
CIO,
. . 'u........
~~. ~
TI'UT
. eee··
e ....
~
eel v.
----l:!! e e
+...
Vd
I
(lltA
1
ee.-$V
OL
""ee,-tlY
""'-m....,....
m
fliED
·:=.
e ii
:;5
ee
&'CS.MIfTf11P.S.IIOUNTtIFIWIIE
Am. ALL OTHER. MItTS SMOWN
._ II
IrNI"UTi
v.!v...:'':'.
~OII'
T
-1
"'"!
.SlNS£~
2
MN e e l Qt
VCC2
(See also
page 4-64)
Power Supply Regulator and Control Circuits:
Vss
~
-5v
I--
.
To Current
Lllllit Circuit
Block Diagram
POWER SUPPLY UNIT (contld.)
LOW POWER CIRCUIT ASSEMBLY (draw.jng 89640800, contld.)
The VBS regulated supply
is derived from the +35V internal supply.
It is
regulated by a conventional series regulator using transistor Q30 as the
series element and the differential amplifier in the reference voltage generator
package (U3) as the comparator.
The two inputs of this comparator are the
general voltage reference (VREF) through R79 and the tap on the voltage divider
chain on the output.
The output voltage of the regulator can be adjusted by
means of potentiometer RV3 in the output voltage divider chain.
The
potentiometer is accessible through the top cover of the power supply unit
(refer to Figure 6-4).
Note that this adjustment affects the value of VSS
directly
see VSS supply below.
The supply is connected to the overvoltage
detector through diode CR34; its current is limited by the conventional circuit
of Q31, R77, which cuts off the series regulator on occurrence of overcurrent.
The regulator output voltage (and therefore VSS ) can be changed by loading the
output voltage divider chain and through it one of the comparator inputs through
the VBB MARGIN terminal (refer to Section 6 for Margin Tests).
The VSS regulated supply is derived from the +35V internal supply, and is
regulated by a switching regulator (see Section 4 for the principles
of operation of switching regulators).
I
The switching element in this circuit is
transistor Q44 with Q9 as predriver and Q8, Q33 as parallel drivers.
The main
output filter capacitors are located on the filter board in the power supply
assembly. See the relevant power supply wiring diagram.
The regulator is driven at about 22 KHz by emitter-coupled oscillator QlI, Ql3.
The duty-cycle of this oscillator (and therefore the proportional regulation of
the circuit) is determined by the ratio of emitter currents of the two transistors.
This in turn is controlled by the differential amplifier QlO, Ql2 sharing the
current source Q39, Q40.
One input of the differential amplifier is the VSS
reference voltage derived from the VBB supply through driver transistor Q34.
To avoid sudden changes in the inductor current (and therefore large voltage spikes
on the inductor) a rise-time limiter integrator (RIOl, C47 and Q45) is included
in the reference line of the regulator.
89633300 F
5-449
POWER SUPPLY UNIT (cont'd.)
LOW POWER CIRCUIT ASSEMBLY (drawing 89640800, cont'd.)
Overcurrent in this circuit is
detecte~
by the voltage developed on R98 acting
as the gating voltage on transistors Q14, Ql5 cO'nnected as a Silicon Controlled
Rectifier (SCR).
This is driven by the oscillator output and is therefore
reset on every cycle of·the switching inverter.
When an excess current flows
through the switching transistor, +35V is connected to the overcurrent bus
through transistor Q15.
This supply is connected to the overvoltage detector
and crowbar circuit through diodeCR33.
The Vcc2 regulated supply has a similar circuit to that of the VSS supply.
It receives its reference voltage through a reference voltage divider chain
and its output voltage can be adjusted by potentiometer RV2.
Access to
RV2 is obtained through the power supply assembly cover (refer to Figure 6-4).
The reference generator utilizes the reference portion of the voltage regulator
package U3 (see the circuit diagram below) to supply the reference voltage to
the regulated power supplies.
ground (-SENSE);
Its supply is referred to the remote enclosure
it is switched through from either the auxiliary supply or
battery by transistor Q32, under control of the dc POWER on/off switch on the
Programmer's Console.
The overvoltage detector and crowbar input circuit utilize the comparator
in the voltage regulator Ul to turn on the transistors Q24, Q25 connected
in a Silicon-Controlled-Rectifier (SCR) configuration when an over-voltage
occurs on anyone of the regulated supplies (-12V, -5V, Vcc2' VSS ' vBB,V cc )'
The positive supplies are ORed to the inverting input through common base
level shifters Q22, Q23. The comparator thus changes state when the absolute
voltage on anyone of the suppl ies increases over the value preset by the
voltage divider on each supply. The inputs to the comparator are biased
from the reference source in Ul.
5-450
89633300 F
LOW POWER CIRCUIT ASSEMBLY (drawing 89640800, cont'd.)
VOLTAGE REGULATOR
(~A723C)
CIRCUIT AND TERMINAL ASSIGNMENTS
14 NC
NC
CURRENT LIMIT 2
13 FREQUENCY COMPENSATION
CURRENT SENSE 3
INVERTING INPUT 4
NON -INVERTING INPUT 5
12 V+
II Vc
10 Vout
VR1'
6
9 Vz
V-
7
8 NC
V+
FREQUENCY
COMPENSATION
TEMPERATURECOMPENSATED
ZENER
INVERTING
INPUT
.>-....-0 REF
NON-INVERTING
INPUT
VOLTAGE
REFERENCE
AMPLIFIER
V-
t----o OUT
CURRENT
LIMIT
ERROR
AMPLIFIER
89633300 F
'---OVz
CURRENT
SENSE
CURRENT
LIMITER
5-451
LOW POWER CIRCUIT ASSEMBLY (drawing 89640800, cont'd.)
Thus when Ul turns on transistors Q24, Q25,they apply the switched battery or
auxiliary supply to the crowbar bus.
This signal turns on the battery
crowbar (SCR Q46) and actuates the crowbar circuit on the HP assembly
(drawing 89657700), which in turn blows the main supply fuse (Fl), and
the battery fuse (F2).
I
The following text relies on HP assembly drawing 89657700 and on· the relevant
power supply wiring diagram.
The on/off dc POWER switch on the Programmer1s Console controls the supply to
the crowbar input circuit (just as it controls the supply to the reference
generator).
When it is on, transistor Q32 switches on the battery or the
auxiliary supply through to the supply line of the crowbar circuit.
The auxi I iary on/off sensor (U2) is a vol tage regulator package connected as
a Schmitt-trigger.
The on/off dc POWER switch of the Programmer1s Console
controls its output frequency which forms the input signal of the power fail
detector on the HP board.
Two auxiliary supplies are generated on the LP board.
The -7V supply (feeding
the -5V regulated supply) is generated by full-wave rectifier CRI2, CRl3 from
the 7 vac output winding of the main transformer TI.
The +25V supply is generated by the rectifier bridge (CR21, CR22, CR23, CR24)
from the separate auxiliary mains transformer T2. This supply feeds the auxiliary supply line while the main power circuit and isolating power transformer TI do not reach their normal voltage. This may occur when the equipment
is first switched on, or when it recovers from power failure.
5-45a
89633300 F
POWER SUPPLY UNIT (cont'd.)
I
LOW POWER CIRCUIT ASSEMBLY (drawing 89640800 cont'd.)
With the main power circuit supplying full voltage, the 35 vac winding on
the main transformer (T1) takes control of the auxiliary line through halfwave rectifier CR30.
The battery charging circuit charges the Memory Hold Battery (equipment
GO 611-A) from the +35V internal supply. When this supply is on, transistors Q20, Q21 form a current source which feeds the battery through current
amplifier Q43 (terminal 17).
The battery supplies power to the +35V bus and through it to the equipment
through isolating diode CR31 when the +35V supply fails (power fail condition: Low Power Data Retention (LPDR) mode of operation).
89633300 F
5-453
...
070
5.' •
11~-----------+-----+--~--+-----l------------------4--------------------------
"::N
____~~_IEN'E
GO
Ni)-.______..;m;.;.;.....__________________..J
n
u
89633300 F
.,.
...
I.t •
-
.__
------------4-< _.....
~,-
______
Q
89633300
A
~~
ID
__________________..J
(,)
ID
5-469
SECTION 6
MAINTENANCE
MAINTENANCE
This section appl ies to the equipment listed in Section 1 of this manual.
TOOLS AND SPECIAL EQUIPMENT
The following is a 1 ist of maintenance tools for the equipment.
Part Number
•
Part Description
12210275
Tweezer Fine Point
12210314
Iron Soldering 15W Miniature
12210315
Tip Soldering Iron .046 In. Spade
12210433
Stripper Wire 20-20 Ga
12210437
Solder 60/40 24 Ga. (.022 In)
12210849
Tool Wire Removal 20-26 Gauge
12210436
Desoldering Tool
89688700
Board Extender
89980600
Board Extractor
Quantity
2
2
Oscilloscope (Tektronix 453 or Equivalent)
Voltmeter (20,000 ohm/V min)
Load Resistor 60 ohm, 5%, 10 watt
Isopropyl
89633300 F
2
Alcohol
6-1
The pubJications Jisted beJow are appJ icabJe to the equipment.
PubJication Number
Mini Computer Site Preparation ManuaJ
60437000
J784 Reference ManuaJ
89633400
J784 I/O Specification ManuaJ
89673JOO
J700 Computer System Codes ManuaJ
60J63500
TeJetypewriter C.E. ManuaJ
60J63700
System Maintenance Monitor (SMM J7)
60J82000
Refer aJso to Preface of this ManuaJ.
6-2
89633300 A
CALIBRATE POWER SUPPLY LEVELS
This calibration appl ies to both main and expansion enclosures.
Check/Condition
1.
Action
System power on, system
1.
Open the enclosure rear cover.
not opera tiona 1 •
2.
Connect the voltmeter (multimeter)
to the test point (TP) for the
main logic supply (Vee);
location of the test point is
shown in Figure 6-1.
Check the value of the V
cc
supply (see Table 6-1).
Correct?
a.
No
Yes
+
Adjust the V supply voltage
cc
by screwdriver control
located as shown in
Go to next step
Figure
b.
3.
6-4.
Repeat check.
Repeat 2 with the computer
running under test.
11.
Repeat 2 and 3 for the
following suppl ies: -12V,
-5V, +30V (see Table 6-1).
2.
System ac power switch OFF,
front panel dc POWER switch ON,
memory hold battery installed.
89633300 A
5.
Repeat 2 above for the
following suppl ies:
V
V (see Table 6-1).
V
cc2' SS' BB
6-3
TABLE 6-1
Supply
No.
- COMPUTER DC SUPPLIES
Designation
Nominal vo I tage
volts
Remarks
Nominal
Current
1.
V
cc
+ 5.0
35A
R
2.
V
cc2
+ 5.3
3A
R,M
3.
VSS
+16.7
5A
AB107/BA201-B, R, M
VSS
+19.7
5A
AB108/BA201-A, R, M
4.
VBB
VSS + 3.5
40mA
5.
-12V
-12.0
100mA
R,
6.
- 5V
- 5.0
lA
R
7.
+30V
+30.0
300mA
unregulated, M
8.
battery
cha rger
200mA
current regulated
R, M
Internal suppl ies
+35V
9.
10.
auxiliary nol
11.
auxi I iary no2
NOTES:
1. R: regulated supply
2.
preregulated
+35
un reg u I ated
unregulated i nterna I
supply
- 7
M: supply to the memory only
The tolerance on all regulated voltages is less than + 1/2 %.
The maximum permissible ripple is 2% of each regulated voltage.
3.
All power supply levels are generated in the power supply unit
(terminal configuration shown in Figure 6-5).
4.
All power supply levels are to be measured on the computer backplane
at the test points (TP) shown in Figure 6-1.
I
5.
6-4
Memory supply voltage (V SS ) is varied by VBB adjustment.
89633300 H
CHECK BATTERY (Optional power back-up source, equipment GD611-A)
Check/Condition
Action
System power off.
1.
1.
Make sure the battery is fully charged.
Note:
the battery is fully charged if it
is charged 32 hours.
fully
dis~harged
If the battery is not
a shorter period of charging
may be sufficient.
Disconnect the battery from its terminals in
the enclosure; refer to Figure 3-7. Connect
the voltmeter {multimeter} across the battery.
WARNING
Do not short battery,
I
Check the battery
vol tage () 24.2V).
Cor rec t?
,
-----~.
No
Yes
Change battery (refer to instructions
in Section 3).
Go to next step
2.
Connect two 60 ohm 5% 10 watt resistors
across the battery in parallel.
Connect the voltmeter (multimeter) across
the resistors.
Check the battery
voltage
(~24.2V).
Correct?
No
-----------------~~
t
Change battery (refer to instructions
in Section 3).
Yes
Reconnect battery
Go to next step.
3.
Switch off all power and close the
enclosure rear
89633300
F
cover.
6-5
1'1
AC
F2
OOFFGeONO 0
.J2
_
VBB.
Console
GNO[l] • -SENSE
TTY Internal Cable
.SENSE.
•
PWR
••
-12V
VCC2
FAIL
Figure 6-1. Computer Backplane Showing the Power Supply Test Points
89633300 F
INSPECTION OR REPLACEMENT OF PRINTED WIRING BOARD
Should it be deemed necessary to remove or inspect any of the printed circuit
assemblies in the enclosure, proceed as follows:
NOTE
WARNING
Make sure that system
Do not remove any circuits with
the enclosure power on.
is not operational
before switching off
system power.
1.
System power off.
(Power off Procedure,
1.
Open enclosure front door.
NOTE
refer to page 6-27).
When removing a printed wiring assembly note
its slot number carefully for future reference.
In a system including
2.
2.
Remove the suspected printed wiring assembly
the expansion enclosure
from its place in the enclosure using the
its power must be
card extractor tool (part 89670300) as
switched off before the
illustrated in Figure 6-2.
main enclosure.
WARNING
Memory Module assembl ies
(equipments BA20l-A, BA20l-B)
require special handl ing:
refer to Section 7, Protection
Against Catastrophic Damage.
3.
Replace a suspected PWA into its slot only
if it is not faulty.
Otherwise substitute
a fully tested similar PWA.
4.
89633300
A
Close front door of enclosure.
6-7
BOARD EXTRACTOR
PUlL TO
IIfMOVE I'WA
>
BOARD EXTENDER
I'WA
W_R TEST
IIOAIID EXTRACTOR
Figure 6-2.
6-8
Use of Board Extractor and Board Extender
89633300 F
INSPECTION OR REPLACEMENT OF THE POWER SUPPLY UNIT
Should it be deemed necessary to remove or inspect the power supply unit in the
enclosure, proceed as follows:
NOTE
The power supply unit should not be repaired in the field.
In case of a fault the unit should be replaced as a whole.
1.
System power off.
1.
Open the enclosure front door.
(Power off procedure,
refer to page 6-27).
2.
I n a sys tem inc 1ud i ng
the expansion enclosure,
its power must be switched
off before the power of the
main enclosure.
WARNING
The power supply -does not use an input isolating transformer and
parts of its circuits are at line voltage during operation. Do
not touch the power supply unit while the line cord is plugged in.
2.
Remove the power supply heat shield by removing
its retaining screws on the inside of the
enclosure front door (refer to Figure 6-3).
3.
Remove all connections from power supply
connector panel (refer to Figure 6-4).
4.
Remove the power supply unit by removing its
retaining screws (refer to Figure 6-5).
5.
Reconnect the power supply after repair and
testing or reconnect another one by reversing
the procedures under 3 and 4 above.
6.
Recalibrate the power supply voltages as
described earl ier in this section.
7.
Replace the power supply heat shield by
reversing procedure in 2 above).
8.
" 89633300
A
Close enclosure front door.
6-9
I
-
..--
e
•
•
•
•
•
•
Fisrure 6-3. Power Su?plv Heat Shield and Retaining Screws
6-10
89633300 F
(
(
....
~ti==
»>";'
.)
~
f3
5A
0
F4
0
lOOmA
()
0
Figure 6~4. Power Supply Adjustments and Fuses
GIlD
o
•
•
/
/
•
POWER SUPPLY
RETAINING SCREWS
figure 6-5.
89633300 F
Power Supply Terminals and Retaining Screws
6-11
CHECK PROGRAMMER'S CONSOLE CONTROLS AND INDICATORS
NOTE
Section 2 describes the controls and indicators
of the Prog'ranvn~r's Console.
These tests relate
only to the main computer enclosure after its
proper installation.
Action
Check/Condition
1.
I. System power on
Check that all I ights corresponding to regist~r positions
(except the Breakpoint register) on the front panel are
extinguished.
Yes
No - - - - - - - -.......
I~-----------~.
2.
Press MASTER CLEAR switch
a.
Take appropriate action
b. Repeat check
Press the M register selector
and the data enter pushbutton
switches (0 through 15)
Check that all indicators
corresponding to the
switches pressed light
(1)
Yes
No.,;;..··-----------1... a. Take appropriate action
b. Repeat check
__________________..... 3. Press CLEAR button
l
~
~
Check that all data enter
indicators are extinguished
Yes
No ----------------.. a.
b.
Go to next step
6-12
Take appropr iate act ion(2)
Repeat check
Note,s: refer to next page.
89633300 F
4.
Repeat 2, 3 for registers
P, Y, X, A, Q, B
5.
Actuate each of the following
switches in turn:
AUTOLOAD, MANUAL INTRPT.,
STOP, MASTER CLEAR, GO
All pushbutton switches
Check if the switches operate
correctly (refer to Section 2
and the SMM manual).
No __________________
Yes
t
Go
2.
~..
a.
.
. (3)
Take appropriate
action
b.
Repeat check
to next step
Controls and Indicators
checked.
Notes:
1.
The CLEAR and MASTER CLEAR functions are defined in the Computer
System Reference Manual (publication number 89633400).
The
signals may be traced with the aid of the Programmer's Console
basic diagram (refer to Section 5) and the back-plane wire list
(refer to Section 9).
2.
To replace an indicator lamp, carry out the appropriate procedure
outlined in the following pages.
3.
89633300 F
To replace a pushbutton switch, carry out the appropriate
procedure outlined in the following pages.
6-13
E"ECTOR PIN MARKS
(4 PLACES)
l
f
REMOVE AMY
PRO"ECTION
FROM MOUNTING
BASE
Bottom View of Programmer's Console Pushbutton Switch Part No. 89652300
(See also CDC Specification 89652300)
6-14
89633300 F
INSPECTION OR REPLACEMENT OF PROGRAMMER'S CONSOLE
Should it be deemed necessary
to inspect or remove the Programmer's Console printed wiring assembly;
to inspect or replace a pushbutton switch or indicator lamp,
proceed as follows:
NOTE
Make sure that system is not operational before switching off system power.
Switch off system
power according to
Power Off procedure
below.
1.
1.
Open the enclosure front door.
2.
Remove the power supply heat shield by
removing its retaining screws on the inside
of the computer enclosure front door (refer
to Figure 6-3).
3 •.. Remove two screws hold i ng cover of front
panel from the rear of the front door
(refer to Figure 6-6a).
;
4.
Remove two small front covers (carrying names
of switches and indicators) from the front
of the door.
5.
Remove three screws from each of the two
edges of the front panel as shown on
Figure 6-6b.
WARNING
Do not remove the other
four screws on the
(hinge side) edge of the
front door, as these
secure the door to the
enclosure.
89633300
A
6-15
SYSTEM 17 PROGRAMMERS CONSOLE
PUSH BUTTON SWITCH INSTALLATION
1.
SCOPE
These instnic,tions detail requirements
switch PIN 896S~300, used on System 17
PIN 89640300.
2.
installing push button
rogrammer's Console
APPL I CABLE DOCUMENTS \,\.
"',,-
\t,
CDC SPEC 89652300 -
3.
REQUIREMENTS
4.
Premounting
5.
pus~~ttqil Switch,
X
1\
preparatiO?~
.
/
/
SPST.
'\
\,
" ''\.
Switch Preparation ,f Switch mounting b . .e shall be free from burrs,
as outlined in Fi~re 1, and other undes eable projections. Note,
the Rohdium all0.'; contacts project 0.0035
,ttes below the mounting
base. A smoot/, projection free, mounting ba~\~ is imperative for
proper sWitcfoperat ion.
6.
/
\
\
Printed WVring Board Preparat ion - Cleaning
/
I
\
\
\
The sW~Ch is sensitive to cleaning solvents. Safe ~Jeaning solvents
to usr are trichlorethylene, methyl denatured alcohol r isopropyl
alcoiol. PWB's shall be cleaned and dryed before mountl
i
and/not afterwards.
WARNING
I
Do not use Freon TMC. It will eat away at
/
/
~
the plastic material.
Freon TF will distort
I
\
6-15A
'Jl'.~'
\S ~
~
I
D
9.
3.
To replace an indicator
10.
Check the pushbutton switch (refer
to previous subsection).
Locate and remove the faulty indicator
lamp on the Programmer's
lamp:
Console assembly, perform
lamp and remove it.
steps.
10~ 13.
unsolder the two legs of the
To remove unwanted
solder use suitable copper braid.
(Indicator lamp:
WARNING
Do not use suction to remove
unwanted solder, suction may
lift off printed conductors
from the board.
CDC PIN 8963700)
11.
Clean the printed wiring board with
methyl denatured alcohol or isopropyl
alcohol.
12.
Mount the replacement indicator lamp
by inserting its two legs in the
freed holes until the lamp is seated
flat against the board.
Carefully
solder the two legs to the printed
wiring pads.
Remove unwanted solder
and clean the area using the materials
of step 11.
13.
Check the indicator lamp (refer to
previous subsection).
89633300
A
6-17
4.
To replace the
14.
Programmer's Console
Proceed in removing the whole'Programmer's
Console by the following procedure:
assembly
follow steps 14 through 16.
- * unsolder
the. power supply connection at
bottom right hand corner of the assembly
I
NOTE:
Steps noted by asterisks
apply to series A12 and down.
For other series, see the
notes at the bottom of this
page.
(looked at from the inside of the front
door of the enclosure: refer to Figure 6-6a)
- * open
rear cover of enclosure, remove the
connector of the assembly (refer to
Figure 6-1)
and slide the cable and
connector through under the card nest
to the front of the enclosure
remove the printed wiring assembly by
removing 10 screws around its periphery.
15.
To reconnect the printed wiring assembly after
repair or with another, good one, reverse
the order of procedures 1 through 5 and 8.
16.
Check all Programmer's Console indicators
and switches according to the instructions
(refer to previous subsection).
I * This
step in the procedure appl ies only to series Al2 and down.
For series AI3 and up, including models C and D, this instruction reads:
- remove the power supply connector at bottom right hand corner of assembly (looked at from the inside of the front door of the enclosure}.
Refer to figure 6-6a.
~
This step applies only to series A12 and down. For series AI3 and up, including models Cand D, this instruction reads as follows:
- disconnect the two connectors on the programmer's console card which
attach the main harness. They are marked J20 and J21 on the enclosure.
6-18
89633300 F
00
I.D
~
BLOWER WIRE SOLDERED
JOINTS
W
W
W
o
o
."
GND
vee
BLOWER
RETAINING SCREWS
OF DISPLAY PANelS
~
I
I.D
Figure 6-6a. Inside of Computer Enclosure Front Door
Note: This view does not apply to all
series. See the note on page 3-7.
REMOVE THESE SCREWS
o
••
Figure 6-6b.
6-20
Inside of Computer Enclosure Front Door.
89633300 A
LOWER FAN BASE WITH FOUR RETAINING
SCREWS
(TYPE IDENTIFIERS C AND D ONLY)
Figure
6-7. Blower Assembly in
Top of Enclosure
(All Type Identifiers)
89633300 F
6-21
INSPECTION OR REPLACEMENT OF COOLING BLOWERS
I
Each enclosure of type C or D is cooled by sLx centrifugal blowers'. Three
blowers are housed in the top of the enclosure (figure 6-7), two in the bottom of the enclosure(not installed in type A, see figure 6-7), and one blower is in the front door of the enclosure. (figure 6-6a). The blower in the
front door cools the power supply unit mounted above it. The blowers in the
enclosure (three on top and two on bottom) supply cooling air to the printed wiring assemblies in the main body of the enclosure.
Should it be deemed necessary to inspect or remove one or more of the blowers,
follow the appropriate procedure outl ined below.
WARNING
The computer must not be operated or switched on with
the blowers outside the enclosure, or otherwise not
operational.
Note that free access of air around the enclosure must
be maintained.
Inspection of the b10wer in the front door
Provided proper care is
1.
Open the enclosure front door.
2.
Inspect the blower visually.
exercised system power
need not be switched
To check the
airflow a sheet of paper may be placed
off.
momentarily on the air inlet:
with proper
airflow the paper will be sucked close to the
body of the blower.
3.
If the blower does not function switch off
the power to the enclosure immediately (refer
to Power Off Procedure), check wiring continuity
according to appropriate wiring diagram (see
Section 5) and if necessary, remove the blower.
Otherwise close the enclosure front door and
6-22
proceed with normal operation or further
checks.
89633300 F
Inspection of blowers in the enclosure
To inspect the three blowers in the top of the enclosure and the two blowers
in the bottom, they have to be slid out from the body of the enclosure.
1. Make sure that the system is not operational
and switch off
th~
system power according to
Power Off Procedure.
CAUTION
In step 2, do not let the
blower box that is mounted
in the bottom of the enclosure fall freely after
its four mounting screws
have been removed. Support
it by hand or some other
way, to prevent strain and
possible damage to the two
connectors.
2.
Undo the screws holding the blower box (two
screws on either side of the enclosure:
refer to Figure 6-7). See Caution.
3.
Open the enclosure front door.
4.
51 ide out the blower box carefully and inspect
the blowers and the wiring.
To check the
airflow of the blowers, prepare a sheet of
paper, switch on the power to the enclosure
for a very short time and place the sheet of
paper across the inlet of each blower momentarily;
with proper airflow the paper will
be sucked close to the body of the blower.
5.
If one of the blowers does not function, check
wiring continuity according to
appropriat~
wiring diagram (refer to Section 5) and if
necessary, remove the blower according to
outline procedure below.
Otherwise sl ide
back blower box carefully, replace the four
screws holding it, close the enclosure front
door and proceed with normal operation or
further checks.
89633300 F
6-23
Removal and replacement of a blower
NOTE
Make sure that the
system is not operational
before switching off
system power.
Before removing a blower inspect it (see two
previous subsections) and make sure that its
removal is necessary.
I.
Undo electrical connection of the blower:
a.
the wire of the blower in the front door
is part of the cable form of the door;
to remove the blower connection cut the
ta~ing of this cable, cut the heatshrinkable tubing over the blower
connection and cut the wires (Figure 6-6a);
b.
the blowers in the top part of the
enclosure are wired through a terminal
I ADDENDUM:
c. the blowers in the bottom
part of the enclosure are
block (refer to Figure 6-7); to
disconnect a blower its wire has to
be removed from this terminal block.
wired to individual connectors (figure 6-8). To disconnect a blower, pullout its
plug.
2.
Remove the blower bodily by undoing the three
screws holding it (refer to Figures 6-6a, 6-7).
WARNING
Do not operate or switch
on the computer without
one of the blowers.
3.
Ensure that replacement blower is in
good working order.
Install it by reversing
the procedure of paragraphs 2 and I above.
After installation inspect the blowers and
close the enclosure (refer to previous
subsections).
6-24
89633300 F
___ tL. ___ l1.. __
... ,1
{~/I
1
(V'-I
" ~I
---1J-YV--
I
REFERENCE:
MAl N HARNESS
89633300 F /
Figure 6-8. Exposed View
of Two Lower fans and Electrical Connections
6-25
WARN
TURN M
-
,
POWER ON:
PROCEDURE FOR SWITCHING ON POWER
To apply power to the computer (equipment AB107lAB108) and the Expansion
Enclosure (equi pment 8T148), proceed as follows:·
NOTE
It is assumed that the equipment has been installed
and is operational.
For Power On Procedure on first
installation refer to Section 3 of this manual.
1.
Make sure all the power switches of the computer are off.
are listed in the following table:
Equipment
Swi tch
Des i gnat ion
The sw itches
Location
ABl07/AB108
AC POWER
DC POWER
Rear Panel
Front Panel
BT148
AC POWER
Rear
DC POWER
Panel
Front Panel
2.
Make sure that the power cord of each enclosure is connected to a
utility outlet.
3.
Switch on the power to the utility outlets.
4.
Turn on the equipment switches in the following order.
On turning on the DC POWER, the associated indicator should light.
Step
Sw itch
Designation
Location
Panel
1.
ABl07lABl08
AC POWER
Rear
2.
AB107/ABl08
BTl48
BT148
DC POWER
AC POWER
DC POWER
Front Panel
Rear Panel
Front Panel
3.
4.
6-26
Equipment
89633300 F
POWER OFF:
PROCEDURE FOR SWITCHING OFF POWER
To remove the power from the computer (equipment ABI07/ABI08) and associated
Expansion Enclosure (equipment BT148) proceed according to the following
instructions:
EMERGENCY SHUT-DOWN
In case of emergency (suspected burning in the computer
and associated equipment) perform anyone or all of the
following steps (the steps are given in order of preference):
Step
Action
Locat ion
1.
Swi tch off circuit breaker of
ins ta II at ion
Depends on
installation
2.
Switch off AC POWER switch on
each equipment
AB! 07
Pull power cord(s) from
.uti I ity outlet
Utility
outleds)
3.
ABI08
BT148
J
rear
panel
REGULAR SHUT-DOWN
To shut down the computer proceed as follows:
1.
Make sure that the system is not being operated.
2.
Turn off the equipment switches in the following order:
Step
Equipment
Swi tch
Designation
1.
BTI48
DC POWER
Front Panel
2.
BTI48
AC POWER
Rear
3.
ABI 07/ABI 08
DC POWER
Front Panel
4.
ASI 07/AB 108
AC POWER
Rear
89633300 F
Locat i on
Panel
Panel
6-27
DIAGNOSTICS AND MARGIN TESTS
TEST PROGRAMS
SMM17 Memory, Command and Random Protect Tests.
TEST CONDITIONS (See alJo table 6-1)
CONDITION
VCC
VSS
NOMINAL DC VOLTAGES
1
+5%
+5%
VCC:
2
-5%
+5%
3
-5%
-5%
4
+5%
-5%
+5.3 VDC
VCC2:
VSS: +1~.7 VDC (AB107)
VSS: +19.7 VDC (AB108)
VBB: VSS + 3.5 VDC
-12.0 VDC
-12
- 5.0 VDC
- 5
+5.0 VDC
I
Operational Tests
At nominal voltages, run several passes of each SMM test.
errors on any test are allowed.
No
Run several passes of each test at each of the 4 conditions listed above.
Return the supply to its nominal values, and re-run the tests. Shock
testing is not recommended, but very light tapping should not produce
errors.
6-28
89633300 F
SECTION
MAINTENANCE
7
AIDS
MAINTENANCE AIDS
TTL CIRCUIT OPERATION
The transistor-transistor logic (TTL) is analogous to diode-transistor logic (OTL)
in certain respects.
As shown in Figure 7-1 a low voltage at inputs A or B
will allow current to flow through the diode associated with the low input, and
no drive current will pass through diode 0 3,
If inputs A and B are raised to
high voltage, drive current will pass through d10de 0 3 ,
In TTL circuitry the multiple-emitter transistor performs the same function as
the diodes in OTL (see Figure 7-2).
However the transistor action of the
multiple-emitter transistor causes transistor Ql to turn-off more rapidly thus
providing an inherent .switching-time advantage over the OTL circuit.
Although one-volt dc noise margins are typical for TTL circuits, an absolute
guarantee of 400 millivolts is given for every unit by manufacturers.
Each output is tested to ensure that the logic high output voltage will not fall
below 2.4 volts.
This is done with full fan-out, lowest Vcc and 0.8 volt on the
input: 400 mV more than the logical low maximum.
Each output is tested to ensure that the logic low output voltage will not exceed
0.4 volt. This is done with full fan-out, lowest Vec and 2 volts on the input:
400 mV less than the logic high minimum.
In actual system operation, the majority of circuits do not experience worst-case
conditions of fan-out, supply voltage, temperature, and input voltage
simultaneously.
In addition the threshold voltage of the TTL circuits is about
1.5 volts.
These characteristics allow a larger voltage change on an input
without false triggering.
This typical noise margin is shown in Figure 7-3.
Another important feature of the design is the output configuration which both
supplies current (in the logical high state) and sinks current (in the logical
low state) from a low impedance.
Typically logical low output impedance is
12 ohm and logical high output impedance is 70 ohm.
This low output impedance
in either state rejects capacitively coupled pulses and ensures small R-C time
constants which preserve wave-shape integrity.
89633300
A
7-1
Vee
Vee
01
Input A
03
Output
o-~I--I--II~o
Output
02
Input
Input A
B
Inpllt B o----J
"='
Figure 7-1.
Diode AND Gate.
OC Leve'
Figure 7-2.
2,8
Vee
4,715 V
(volta)
2,0
V
',2
- . ,a.
Figure 7-3.
7-2
r ..
Not.. " ..gift
I
I
40
I
80
Logio Hi,h
Logio Low
1
Logic LoW
•
20
I
TTL AND Gate.
IT
Lotic High
"argin
0,4
o
-
~
eround
III'
T.,..,.rotur. (Oe)
Typical Logic Level Margins for TTL Micrologic
89633300 A
MOS CIRCUIT OPERATION
THE MOS PROCESS AND SILICON GATE TECHNOLOGY
The memory unit is realized with silicon gate metal-oxide-silicon (MOS)
technology.
This technology offers a number of advantages over aluminum
gate MOS technology; some of these are listed:
a.
Gate oxide is protected immediately on formation in the silicon gate
process.
b.
The self-aligned gate of the silicon gate device permits the construction
of a smaller device with less gate-to-drain capacitance than is possib.le
with aluminum technology.
Faster, more compact circuits are made possible.
c.
The silicon layer can be used for interconnections, permitting reduced chip
area per function.
This is an important factor in large scale integrated
(LSI) circuits where interconnection area affects cost even more than
active component area.
d.
Improved reliability of the 'silicon gate devices due to the number of layers
above the gate.
e.
Lower threshold voltage due to the use of silicon rather than aluminum as
the gate material.
89633300 A
7-3
Static and Dynamic HOS Circuits
The characteristics of the HOS field-effect-transistor (HOSFET) permit the
construction of a wide variety of logic circuits with a large device and
function density while giving good reliability and yield.
An example of
the application of these circuits is the memory unit of the computer, a
1024-bit random access, fully decoded read-write memory unit, accommodated
on a single semiconductor chip.
In general the HOS device may be used as an active amplifier or as a load
Typical characteristi.cs of a HOSFET device are shown in
resistor.
Figure 7-4, together with a curve corresponding to it used as a load resistor
with a 12 volt supply.
The curves show drain current (IO) versus drain-tosource voltage (VOS) with gate-to-source bias voltage (V GS ) as a parameter.
The substrate is assumed to be at source potential.
The load resistor curve
In the following
is approximate as substrate bias effects have been neglected.
discussion on the various circuits high and low refer to the relative magnitude
of the voltage with respect to the substrate voltage level (VSS).
Polarities
are taken as correct for a p - channel device, i.e., all voltages negative with
respect to the substrate.
Note that the supply voltage for MOS devices is
typically -15 to -18 volts; the logic high and low signals to the memory unit
are typically as follows:·
min.
7-4
max.
input low voltage
VSS - 17
VSS - 14.5
input high vo ltage
VSS - 0.7
VSS + I
89633300 A
Four types of MOSFET inverter stages are shown in Figure 7-5.
In Figure 7-5a
two MOS devices (Ql, Q2) are wired as a static inverter.
When input is
sufficiently hi.gh, Q2 turns on and the output is low.
If the input is low it
causes Q2 to be off and Ql pulls the output high.
This circuit requires that
for equivalent bias, Q2 should have much higher conductance than Ql to get
reasonable noise margins; the two devices have therefore radically different
geometries.
This is shown in Figure 7-5a by representing Ql as a resistor and
Q2 as a FET.
As a result of the low conductance of Ql, current available from
it to charge load capacitances is quite limited in this inverter and low-to-high
transitions are rather slow.
The circuit of Figure 7-5b is similar to that in Figure 7-5a when the clock is
active.
By making the clock voltage higher than V, a more consistent high
output level is established.
Once the output level is established, the clock
may be switched off to save power.
This technique is used in the low power
data retention mode of operation (lPDR) to conserve battery and may be used
also to give improved noise margins.
The circuit of Figure 7-5c behaves as an inverter when the clock is active (high).
This circuit may be used to drive relatively large capacitive loads through the
high conductance of Q1, though it may consume relatively large amount of power
while both the input and the clock are active (high).
In the circuit of Figure 7-5d the capacitive load is charged when the clock
input C is high and is discharged when C goes low, provided that the input is
high.
This circuit draws current only to charge and discharge the load and
there is no dc drain.
The load capacitance is, however, reflected back
into the clock driver.
The circuits of Figures 7-5b, c, d make use of temporary retention of data on
the load capacitance and are therefore said to be dynamic, while that of
Figure 7-5a is dc-stable and therefore static.
89633300
A
7-5
" •• idor C ...v.
Load
- 4.0
Ves =-IOV
Vas·- IV
. - 2.0
Ves =-IV
Vas =-4V
Vas =-2 V
-8
Figure 7-4.
-10
-18
Typical HOS Characteristic
V
V
V
C
o--t
VDS
-20
V
C
01
o--t
Output
Output
o--t
C>-i
Input
tftput
-
a. Statio
Input
-
It. Gated Static
Figure 7-5.
7-6
Output
Output
I
c.
I
Input
,.,....
I
-!-
d.
Dynamic. Low Power
....L
'"
- -:Dynamio
I
-L-
HOS Inverter Circuits
89633300
A
v
Q3
_-0
Output
Q4
Input
Figure 7-6.
MOS Inverter with Output Booster
C
0
•
I
I
I
rt
*cs
I
~
Figure 7-7.
89633300 A
•
I
I
...L.
..,...
CL
I
+
MOS Transmission Gate
7-7·
Larger capacitive loads may be driven by static inverters only if a booster
stage is added.
A loss of high level is introduced unless bootstrap techniques
are used.
A booster stage is shown in Figure 7-6.
A transmission gate is shown in Figure 7-7.
The load capacitance CL is charged
When
towards the voltage on the input capacitor Cs when the clock C is high.
the clock input is returned low it switches off Ql and CL retains the voltage
it was charged to.
The circuit of Figure 7-7 may be driven from a number of different source
circuits.
When the source is dynamic the transmission gate clock C should
be kept high during the entire period when Cs and CL are being charged and
discharged,otherwise improper voltages may result.
For example if Cs is
initially charged and CL initially discharged, they will share their charge
when the transmission gate is opened by the clock being made active.
The
voltage on the capacitors will thus be a function of the relative values of
the two capacitors.
Unless the circuit is designed to operate with such
intermediate voltage levels incorrect operation will result.
Such circuits make up the memory unit (Section 4) which work together with
auxiliary and control circuits in the memory module, memory address and
memory control circuits.
7-8
89633300 A
PRECAUTIONS IN HANDLING THE MEMORY MODULES
The
The
and
and
memory banks are arrays of memory units mounted on the Memory Modules.
memory units are MOSFET circuits characterized by very high impedances
some special precautions should be observed while handling them both in
out of circuit.
PROTECTION AGAINST CATASTROPHIC DAMAGE
As with any semiconductor component, the memory units can be damaged by misuse,
or misapplied voltages.
The component should be protected from such misuse
during shipment, handl ing, and when installed in the system.
MOS circuits are characterized by high impedances, and therefore are capable
of being charged to high voltages by static charges.
The gate circuits of
MOS transistors are subject to destructive breakdown if excessively charged.
The memory unit has an effective gate protection circuit for all input
connections, and requires no elaborate precautions in normal use.
However,
some environments are subject to extreme build up of static charge, and are
capable of releasing sufficient amounts of energy to damage any semiconductor
MOS components in particular should be protected from these static
component.
charges.
Some precautions which are easy to implement and yet which are quite
effective are:
89633300
A
a.
Carry components and memory unit cards in conductive
trays, such as metal or foil-lined pans.
b.
Personnel must touch ground, the chassis or the carrier
tray before picking up components and memory unit cards.
Avoid high static materials and fabrics in work areas.
7-9
SECTIor~
8
PARTS LIST
-~
PARTS DATA (Sheet 1)
Use the parts listed below to maintain the equipments listed on page iii.
Numbers enclosed in parentheses indicate notes.
PART NAME
PART NUMBER IN EQUIPMENT
AB107-A/C/D AB108-A/C/D BT148-A/C/D BU120-A
ALU PWA
Timing PWA (1)
Decoder PWA
I/O Interface PWA (1)
TTY Controller PWA (6)
Console Interface PWA
Memory Address PWA
89614100
89614100
89778200
89934400
89791300
89967400
89600043
89615000
89778201
89934400
89791300
89967400
89600043
89615000
89949000
89602069
89893800
89637000
89652300
89690200
89764900
89949000
89602069
89893800
89997700
92371016
93419306
92383005
9341922r
~637100
89637100
89637000
89652300
89690200
89764900
53397915
53397918
93947009
51788834
97030200
53397915
53397918
93947009
51788834
97030200
Memory Control PWA
Programmer's Console PWA (2,3,4)
Console Cable Assembly (2,5)
Power Supply Unit (7)
Fuse, 5A, fast blow
Fuse, 100 rnA, slow blow
Fuse, 8A, slow blow
Fuse, lA, slow blow
Blower (mounted in door)
Blower (mounted in enclosure)
Lamp, indicator bulb
Switch, pushbutton (3)
Switch, pushbutton (4)
Switch, pushbutton (4)
Connector, Rlug
.. (5)
Contact, socket (5)
Connector (2)
Contact, socket (2)
Switch, DPDT (AC input)
Lamp, miniature, 6v (power on)
89633300 H
89997700
92371016
93419306
92383005
93419222
89637100
89637100
89615000
89949000
89997700
92371016
93419306
92383005
93419222
896371 00
I
89637100
97030200
89818700
8-1
PAR T S
DAT A
(Sheet 2)
PART NUMBER IN EQUIPMENT
PART NAME
AB107/8-A/C/D AB108-A/C/D BT148-A/C/D BU120-A
Switch,toggle, 2P, 7201/Jl-CB
89640901
89640901
Switch,toggle, 3P, 7203/J2-CB
Lens, lamp red (power on)
89640904
89640904
Lens, lamp, white
89633100
89640901
89780201
89633100
Equipment BA201-A, 600 nanosecond Memory, Part Number 89876300
Equipment BA201-B, 900 nanosecond Memory, Part Number 89876600
Equipment GD611-A, Memory Hold Battery,
Part Number 89650100
NOTES:
(1) Timing PWA 89778200 (or 89778201) and I/O Interface PWA 89791300 must
both be used at the same time. If you replace one, you must also replace
the other.
(2a) The PIN for the programmer's Console PWA with its related series code
is as follows:
PWA
SERIES
89987600
A04-A12
89987700
A13-A16
89985400
A17-A19
89602068
88602669
C01-C03
D01-
(2b) Programmer's Console PWA PINs 89640300 and 89987600 include an integral
cable assembly PIN 89893800, used in series A04 to A12. Programmer's
Console PWA PINs 89881800 and 89987700, used in series A13 up, do not
include the cable assembly. To install PIN 89881800 or 89987700 (more
lately 89985400 and 89602069) into series A04 to A12, make sure of
the following:
* Install cable assembly 89893800 at the same time.
*
Use connector 93947009 and four socket contacts 51788834 on the
power supply wire harness assembly (P22).
I
8-2
89633300 H
PAR T S
DAT A
(sheet 3 of 3)
NOTES (continued)
(3) Pushbutton switch 89652300 is used with Console PWA 89640300 in A04 to A12.
(4) Pushbutton switch 89690200 is used with Console PWA 89602069 in A13 up.
Twenty-nine switchcaps PIN 89764900 must be ordered together with
Console PWA 89602069.
(5) Plug connector 53397915 and contact sockets 53397918 are parts of
Console Cable Assembly 89893800.
(6) TTY Controller PWA 89967400 is one of four valid TTY Controller part
numbers in the field. See page 5-373 for details.
(7a)The PIN for the power supply PWA and its related series code is as
follows:
PWA
SERIES
89964700
A04-A09
89983000
Al0-A19
DOl
89997700
(7b) Two power supply wiring diagrams and two power supply I/O wiring
harnesses are provided in section 5 to cover Power Supply Unit part
number 89997700 and the other valid units in the field.
89633300 H
8-3/8-4
I
SECTION 9
WIRE LISTS
WIRE LISTS
Table 9-la gives the wire list for the TTY Internal Cable.
I
Table 9-lb gives the wire list for the TTY External Shielded Cable.
I
Tables 9-2 and 9-3 are the wire 1 ists for the Memory Expansion Cables, which
form part of equipment BU120-A.
Refer to Figure 3-4 for placement details
of these cables.
Table 9-4(a) and 9-4(b) give the backplane wiring of the AB107/AB108 in,
respectively, signal name order and card slot order.
These tables
incorporate the wiring for the CPU, Memory System, A/Q and DSA buses and
that for the slots preassigned to equipments FA716, FA442, FA446 , Fv497 and
Fv618.
For slot assigned allocation refer to page 5-6.
Table 9-5 gives the backplane wiring of the BT148 Expansion Enclosure in
signal name order.
For slot assignment allocation refer to page 5-7.
Table 9-6 supplies the COT external cable assembly wire list.
Note:
The signal names shown in the wiring 1 ists may differ slightly from those
listed in Section 5.
Equivalents of typical signal names are given below.
Signal name in Section 5
Section 9
ACA05
ACAS
D~UT07
ALUOO
DOUT7
ALUOL
··
·
ALU07
··
··
ALU7L
ALU08
ALUOM
··
··
···
·
ALU7M
ALU15
MC
89633300 E
MC* ,
Notes
I"
Double/single digit representation
of numbers under 10
16 signals to 'the two ALU assemblies:
suffix L:
least significant
suffix M:
most significant
Inverse signal: over1 ine/asterisk
9-1
TABLE 9-1 a. TTY INTERNAL CABLE PIN 89681,200
CONDUCTOR
I DENT.
COLOR
RED
1
2
ORIGIN
DESTI NAT ION
(1)
(2)
P2A03
A08
A 13
3
4
B21
A22
5
6
7
8
9
10
11
12
13
11,
RED
A23
A24
A25
A26
A27
A28
A29
A30
P2A31
I
Pl-24
13
23
58
41
43
45
1,7
49
51
53
55
57
PI-08
REMARKS/ SIGNAL NAME
GRO UN D
BAUD SEL
M. I •
GROUND
PAR.SEL
-12V
-12V
TTY-KB
TTY-PR
CRT-TRANS
EVEN PARITY
MOTOR ON
CRT-REC
VCC
(1) Origin: 66-h61e connector shell plug.
(2) Destination: 62-hole connector block.
_ _ _ _ " _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-1
TABLE 9-1b. TTY EXTERNAL SHIELDED CABLE PIN 89642300
--'--r--COLOR
CONDUCTOR
I DENT.
1
2
3
It
5
6
7
8
I,
BlK
RED
GRN
WHT
BRN
BLU
ORN
YEL
ORIGIN
REMARKS/ SIGNAL NAME
(1)
DESTI NAT ION
(2)
5
43
-12V
7
6
8
45
-12V
TTY-KB
TTY-PR
NOT US ED
NOT US ED
NOT USED
NOT US ED
47
49
(1) Origin: Molex type.
(2) Destination: Continental type.
I
9-2
89633300 E
I
TABLE 9-2. MEMORY EXPANSION BU120-A08 EXTERNAL CABLE ASSEMBLY (PI) AWG 28
PART NUMBER 89658101 (sheet 1 of 3)
-------
CONDUCTOR
IDENTITY
1
2
3
4
5
6
7
8
9
10
i1
-12
13
14
1'J
16
17
18
;q
J;
?;
n
23
:~4
25
26
27
28
29
30
COLOR
GRN-WHT
BLK
GRN-WHT
GRN-WHT
BRN
GRN-WHT
GRN-WHT
I
RED
GRN-WHT
i
GRN-WHT
ORN
GRN-WHT
I
I,I GRN-WHT
VEL
I
I GRN-WHT
GRN-WHT
i
GRN
GRN-WHT
, GRN-WHT
I! BLU
,
GRN-WHT
! GRN-WHT
I! VIO
f GRN-WHT
I
GRN-WHT
GRA
GRN-WHT
GRN-WHT
WHT
GRN-WHT
I
I
I
i
I
I
I
I
I
ORIGIN
DESTINATION
(I)
(2)
GND
P1BOl
GND
GND
P1B02
GND
GND
P1B04
GNO
GND
P1B06
GND
GND
P1B08
GND
GND
P1B09
GND
GND
P1A10
GND
GND
P1B10
GND
GND
P1All
GND
GND
P1A12
GND
GND
Pl BOl
GND
GND
P1B02
GND
GND
P1B04
GND
GND
P1B06
GND
GNO
P1B08
GNO
GND
P1B09
GND
GND
P1A1O
GND
GNO
P1B1O
GND
GND
I
P1All
I
GND
GNO
P1A12
GND
I
--
!,
-~I
REMARKS/SIGNAL NAME
SLOT 31
SLOT 33
MXOL
---I
-"'-1
i
SOl
I
Ij
,
!
I
MX1L
SA2
MX2L
SOO
,I
I
I
MX3L
S02
,
,
I
MX4L
I
SD3
I
I
,!
I
MX5L
SD7
I
I
I
ALU3L
I
SA3
i
I
I
ALU2L
SD6
ALU1L
SOS
ALUOL
504
--
Numbers enclosed in parentheses indicate notes. See sheet 3.
89633300 E
9-3
I
TABLE 9-2. MEMORY EXPANSION BU120-A08 EXTERNAL CABLE ASSEMBLY (pl) AWG 28
PART NUMBER 89658101 (sheet 2 of 3)"
CONDUCTOR
IDENTITY
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
COLOR
GRN-WHT
BLK
GRN-WHT
GRN-WHT
BRN
GRN-WHT
GRN-WHT
RED
GRN-WHT
GRN-WHT
ORN
GRN-WHT
GRN-WHT
YEL
GRN-WHT
GRN-WHT
GRN
GRN-WHT
GRN-WHT
BLU
GRN':'WHT
GRN-WHT
VIO
GRN-WHT
GRN-WHT
GRA
GRN-WHT
GRN-WHT
WHT
GRN-WHT
ORIGIN
(1)
GND
P1B12
GND
GND
P1A13
GND
GND
P1B13
GND
GND
P1B14
GND
GND
P1B15
GND
GND
P1A16
GND
GND
P1B17
GND
GND
P1B18
GND
GND
P1B21
.
GND
GND
P1A22
GND
DESTINATION
(2)
GND
P1B12
GND
GND
P1A13
GND
GND
P1B13
GND
GND
P1B14
GND
GND
P1B15
GND
GND
P1A16
GND
GND
P1B17
GND
GND
P1B18
GND
GND
Pl B21
GND
GND
P1A22
GND
Numbers enclosed in parentheses indicate
9-4
REMARKS/SIGNAL NAME
SLOT 31
SLOT 33
MX6L
SA5
MX71
SA4
MXOM
SPBM
MX1M
CPBM
MX2M
SD8
MX3M
SDll
MX7M
SD9
MX4M
SD14
MX6M
SDl3
MX5M
SOlO
notes. See sheet
3.
89633300 E
I
TABLE 9-2. MEMORY EXPANSION BU120-A08 EXTERNAL CABLE ASSEMBLY (Pl) AWG 28
PART NUMBER 89658101 (sheet 3 of 3)
CONDUCTOR
IDENTITY
61
62
63
64
65
66
67
68
69
COLOR
ORIGIN
DESTINATION
GRN-WHT
BLK
GRN-WHT
GRN-WHT
BRN
GRN:"'WHT
GRN-WHT
RED
GRN-WHT
GND
P1B22
GND
GND
P1A23
GND
GND
P1B23
GND
GND
P1B22
GND
GND
P1A23
GND
GND
P1B23
GND
(1)
(2)
REMARKS/SIGNAL NAME
SLOT 31
SLOT 33
ALU1M
SA6
ALU2M
SAll
ALUOM
CRI
(1) Origin: 62-contact connector
I
(.2) Destination: 62-cQntact connector
89633300 E
9-5
TABLE 9-3. MEMORY EXPANSION BU120-A08 EXTERNAL CABLE ASSEMBLY (P2) AWG 28
PART NUMBER 89658501 (sheet 1 of 3)
I
CONDUCTOR
IDENTITY
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
COLOR
GRN-WHT
BLK
GRN~WHT
GRN-WHT
BRN
GRN~WHT
GRN-WHT
RED
GRN-WHT
GRN-WHT
ORN
GRN-WHT
GRN-WHT
YEL
GRN-WHT
GRN-WHT
GRN
GRN-WHT
GRN-WHT
BLU
GRN-WHT
GRN-WHT
VIO
GRN-WHT
GRN-WHT
GRA
GRN-WHT
GRN-WHT
WHT
GRN-WHT
ORIGIN
DESTINATION
(1)
(2)
GND
P2B02
GND
GND
P2B03
GND
. GND
P2B04
GND
GND
P2B05
GND
GOO
P2B06
GND
GND
P2A09
GND
GND
P2B09
GND
GND
P2A10
GND
GND
P2B10
GND
GND
P2All
GND
GND
P2B02
GND
GND
P2B03
GND
GND
P2B04
GND
GND
P2B05
GND
GND
P2B06
GND
GND
P2A09
GND
GND
P2B09
GND
GND
P2A10
GND
GND
P2B10
GND
GND
P2A11
GND
REMARKS/SIGNAL NAME
SLOT 33
SLOT 31
ALU3M
SD12
MX17
SA7
MPRY
SD15
CVIOl
SAlO
WE
SA12
PRTM
SA9
CPEC
SA14
SPI
SA8
S WRITE
SAl3
CRQ
EDX
Numbers inside parentheses insicate notes. See sheet 3.
9-6
89633300 E
I
TABLE 9-3. MEMORY EXPANSION BU120-A08 EXTERNAL CABLE ASSEMBLY (P2) AWG 28
PART NUMBER 89658501 (sheet 2 of 3)
CONDUCTOR
IDENTITY
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
. 55
56
57
58
59
60
COLOR
GRN-WHT
BLK
GRN-WHT
GRN-WHT
BRN
GRN-WHT
GRN-WHT
RED
GRN-WHT
GRN-WHT
ORN
GRN-WHT
GRN-WHT
YEL
GRN-WHT
GRN-WHT
GRN
GRN-WHT
GRN-WHT
BLU
GRN-WHT
GRN-WHT
VIO
GRN-WHT
GRN-WHT
GRA
GRN-WHT
GRN-WHT
WHT
GRN-WHT
ORIGIN
DESTINATION
(1)
(2)
GND
P2Bll
GND
GND
P2A12
GND
GND
P2B12
GND
GND
P2A13
GND
GNO
P2B13
GND
GND
P2B14
GND
GND
P2B15
GND
GND
P2B16
GND
GND
P2B17
GNO
GND
P2A18
GND
GND
P2Bll
GND
GND
P2A12
GND
GND
P2B12
GND
GND
P2A13
GND
GND
P2B13
GND
GND
P2B14
GND
GND
P2B15
GND
GND
P2B16
GND
GND
P2B17
GND
GND
P2A18
GND
REMARKS/SIGNAL NAME
SLOT 31
SLOT 33
CCPE
---
--~
GOM2
SA15
ALU7L
PRTSW
ALU5M
32KW
ALU6L
NORMAL
ALU7M
MSXA
ALU5L
SDl7
ALU4M
SRSM
ALU6M
SS
ALU4L
SD16
-
Numbers inside parentheses indicate notes. See sheet 3.
89633300 E
9-7
I
TABLE 9-3. MEMORY EXPANSION BUI20-A08 EXTERNAL CABLE ASSEMBLY (P2) AWG 28
PART NUMBER 89658501 (sheet 3 of 3)
CONDUCTOR
IDENTITY
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
I
COLOR
ORIGIN
(1)
GRN-WHT
BlK
GRN-WHT
GRN-WHT
BRN
GRN-WHT
GRN-WHT
RED
GRN-WHT
GRN-WHT
ORN
GRN-WHT
GRN-WHT
VEL
GRN-WHT
DESTINATION
(2)
GND
P2B18
GND
GND
P2A19
GND
GND
P2B19
GND
GND
P2B20
GND
GND
P2A22
GND
GND
P2B18
GND
GND
P2A19
GND
GND
P2B19
GND
GND
P2B20
GND
GND
P2A22
GND
REMARKS/SIGNAL NAME
SLOT 31
SLOT 33
DFEO
SVIO
MDEL
SAO
SAl
GPEC
SRQ
PEL
RGPWR
Origin: 62-contact connector
(2) Destination: 62-contact connector
(1)
9-8
89633300 E
TABLE 9-4.a
WIRE LIST AB 107/AB 108 BACKPLANE
(in signal name order)
89633300 A
9-9/9-10
PAGE
N)
~
1
I
TO
R F
l
I
A 8 1 0 118
S T
SIGNAL-NAME
w.l.
20P2A24
08PlAOl
QAP1 AH
C8PIR30
08P2A 11
08P2 Bll
08P2dOA
08P? AJ1
12 PI ~Ofl
-12V
A NOENV ( 1)
A POST MII8lE
A POS1AMBlE
A REACY f
A REACV G
A.SKEINCVF F
A .SKEwCVF G
13P2Rl~
AID
AID
O~P2A06
11 PI R31
1'5P2AIA
13P1Al3
08 Pl All
lOP2AOt)
lOP2A26
09P2A2b
lOPl A04
09I Pl A04
lOPl A2 8
09P1A28
lOP! All
09PIAll
09P2A!3
lOP2A13
09PIAl8
10PIA18
LOP 1 B30
09PIB30
OQP2 A2 2
10P2A22
10PIA11
O:)PIA11
lOP2B09
09P2B09
29PlB26
34P2B26
32P2Bl6
30P2B26
35P2826
33P2R26
31P2B26
29P 2826
2~ P2 B23
33Pl8l3
31P2B23
3t;P2R23
32P28l'3
30P2B23
34P2 B2 3
29P2R23
09P2 A2l.
08PLA19
O<;PIA04
08P2A16
09PIA2R
08PIB29
09Pl All
ORP1A12
D8P2R06
09P2 All
08P2A09
09PIA18
09P1830
ORP lA 14
OBPIAll
09P2 A2")
09PIA17
08PIA06
OC;P2B09
08PIIlI?
28Pl B19
35P2B26
33PlB2n
31P7.B26
36P2B26
34P2826
32P2B26
30P2B26
30P2 B23
34P2B2'3
32P2B23
36P2BZ3
33P2B23
31P2B23
3t;P2823
2AP2B 11
89879100
8<1879100
89319100
89879100
89819100
89879100
8<1819100
89819100
89319100
8<1819100
89319100
89879100
89819100
89879100
89879100
89879100
89979100
89819100
89819100
89879100
89819100
89819100
89879100
89819100
89819100
89879100
89819100
89819100
89819100
89879100
89819100
89819100
89819100
89879100
89879100
89879100
89819101
89819101
89a 19101
89819101
89879101
89879101
89819101
89819101
89819101
89879101
89819101
89879101
89879101
89879101
89819100
FROM
20P2A23
lOP2A25
10PlA24
lOP?B07
10P2B30
10P2 A04
10P2A06
lOP1B26
13P2B 11
14P2812
12Pl B06
16P1831
14PIB17
O~P2A06
89633300 A
AID
A/Q CLEAR
A=B
AS CLOCKOUT
AB CLCCKCLT
AB DA TA
Ae DATA
AB OEN
A8 DEN
AB DOT
AB DOT
AB LOl
AS lOl
AS PARITV
Ai! PA~ITV
AS PR ESE T
AB PRESET
Ae PENAPlE*
AS RENABlE*
AB TOG
AS TOG
ABCNE
A erNE
AB~RES(5
t
AB~RES(5)
A(A5
ACA5
ACA5
A(A5
ACA5
ACAt;
ACA5
ACA5
ACA6
ACA6
ACA6
ACA6
ACA6
ACA6
A(A6
ACA6
fR .lEV TO.lEV
1
2
2
1
1
2
1
2
2
1
1
2
2
1
1
2
1
2
2
1
1
1
2
2
2
2
1
1
2
2
1
1
2
1
1
1
2
2
1
1
2
2
1
1
2
2
1
1
l
2
2
I
1
2
1
2
Z
2
1
1
1
2
2
1
1
1
2
7.
1
2
7.
2
2
1
1
2
1
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
1
1
2
2
2
2
'9-11
PAGE NO
2
FR1~
28 P2 B24
30P2A23
34P2A23
32P2A23
29P2A23
33P2A23
31P2A23
31)P2A23
29P2822
33P2822
3lP2822
35P2B22
34P2812
32P2B22
30P~ 822·
29P2B12
29P1A21
30P2A27
3ltP 2A2 7
32P~A27
29PlA27
31)P 2A27
33P2A27
31p2A27
IOP2A02
10P2A02
19PIB09
19P1 A05
16P1822
19P2A25
19P2830
19P2816
19P 2611
26P2A14
22p2B22
21P 1A31
28 P2 814
24P2B01
24P1B24
24Pl A26
lOP2A24
10P2A09
10PIB03
lOP lA26
21)PIB16
25PIB19
ZI)P2A09
2bPIA21
28PIB12
28P1A28
31PIA12
9-12
W I
R E
Tl
29 P2 A21'
31P2A21
31)P2 A23
11 Pl All
30P2A23
34P2A23
32P2A23
36P2A23
30P2827
14P282'
31P282'
36P182'
35P282'
33P2822
31 P2 82'
28P2A 1 A
28P2810
31 PZ A27
35P2A21
33P2A27
30P2A21
36P2A21
34P2 A27
32P2A27
08P2A17
08P2A1C)
15P2A29
I1P1AIA
15P2B30
16PIB24
17P2B24
1 7P2 Aot;
18P1B 30
22P2Bl8
23PIA31
24P1B01
21 P2 8lt;
23PIA24
2.3PIAln
l3PIB20
oap2BO,)
08P2 AO,
08P2 A04
CAPl626
2191626
23'Pl814
25P2B 11
25Pl A09
25PIB24
26PIB24
28 PI fH2
l
( S T
A B 1
SIGNAL-NAfole
w. L.
A(A7
ACA7
ACA 7
A(A1
ACA7
ACA7
ACA7
ACA1
ACA8
ACA8
ACA8
ACA8
ACA8
ACA8
A(A8
ACA8
ACA9
ACA9
ACAC;
ACA9
ACA9
ACA9
A( A9
ACA9
AC1·
AC2
AODR ERR
ADOR.CKWO=O
AOOR.ERR*
AOORESS ECP
ACORESS 12*
ADORESS·
AOOT I NOE X.
AD01M
ACR*
AOR*
ADVANCe.
ADV*
ADI
A02
AENV(l )
AENV(2)
AfNV(4)
AENV(5)
Al
ALCK
AlUOAM
AlUCA"AlUOl
AlUOM
ALUOl
89879100
89879101
89819101
89819101
89879101
89879101
89879101
89819101
89879101
89819101
89879101
,89879101
89879101
8987(jl01
89819101
89819100
89879100
89879101
891179101
89819101
89819101
89819101
89879101
89879101
89819100
89819100
89A 79100
89319100
89879100
89879100
89d 79100
89819100
89819100
89879100
89879100
89979100
89819100
89879100
H9879100
89879100
89879100
89879100
89d79100
89879100
89679100
89879100
89879100
89879100
89319100
89879100
89879100
o
7/e
fR.lEV TO.lEV
2
2
2
2
1
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
1
1
1
1
2
2
2
2
2
2
2
2
1
1
2
1
1
1
1
2
1
1
2
2
1
1
2
1
2
1
2
2
1
2
1
2
2
1
1
1
1
1
2
1
1
2,
1
1
1
1
2
1
1
2
2
1
1
2
1
2
1
2
2
1
2
1
2
2
1
89633300 A
3
PAGE NO
~
TO
FROM
31PIB23
3IPIAl!
l8P lA 11
28PIA22
31PIB22
31PIRIO
28P1810
28Pl A2 7
3lP 1 A23
31PIAI0
?8PIAIO
lap L828
31P2802
~lP2A18
28P 2Al7
2AP2A16
3lP2816
3lP2815
28P2A15
28P2B09
31P2Al3
31P2B13
28P2All
28 P2816
31P2817
26P2A04
26P~ A04
26P2802
25P2A04
31P2B12
28P2A09
28P2811
31P2B14
13P 2B22
13P2A21
26P1Bl6
26PIB19
lOPl A07
10P2AIO
IOPIA16
10PIA03
10PIB25
25P2A21
10P2A29
10P2805
25P2A30
26P2A30
2SP2B15
"33P2A25
31P2A25
29P2A25
IRE
2APIA2~
28PIAll
25PlR30
!.!6PIB30
28Pl A2?
2SPIBIO
25P1827
i6Pl B27
28P1A27
28PIAIO
25PIA21
26PIA21
28 Pl. B2A
28P2Al1
25P2Bl1
26P2817
28P2A16
28P2Al,)
25P2 A16
26PlA16
28P2B09
2AP2 A12
2'5P2A11)
26P2A15
2AP2816
21)P2B02
26P2B05
25P2A04
27P2A29
28P2 A09
25P2Bl'5
26P2815
28P2Bl1
12PIB16
08P2A2421PIA26
23P2A 11
08P2A12
OSPIA2)
08Pl825
08P2 B0408PIB27
24P2A02
08P2B 19
08P2A19
22PIA21
25P2A 30
29P2A25
34P2 All)
32P2A25
30P2A25
89633300 A
l
1ST
A B 1
SIGNAL-NAME
W.l.
AlllOM
ALUIL
AlUll
AlUIM
AlUIM
AlU2L
AlU2l
AlU2M
AlU2M
AlU3L
AlU3l
AlU3M
AlU3M
AlU4l
AlU4L
ALU4M
ALU4M
AlU5l
AlU5l
AlU5M
ALU5M
AlU6l
AlU6L
ALU6M
AlU6M
AlU1Al
ALU7AL
ALU7AM
AUJ7AM
ALU1l
AlUll
AlU7M
AlU7M
All
Al2
AM
AMCI<
ANOOROPOUTt
ANOEN~ (2 J
ANOENV( 3»
ANOENV (4 J
ANOENV,5J
AD*
ACNEf*
AONEG*
89819100
89879100
89879100
89S19100
89819100
89879100
89879100
89879100
89819100
89a 79100
89879100
89819100
89879100
89879100
89879100
89879100
89879100
89879100
89819100
89879100
89819100
89879100
89879100
89879100
89819100
89819100
89879100
aCJ819l00
89819104
89819100
89tl19100
89819100
89819100
89819100
89819100
89879100
89879100
89879100
89819100
89879100
89879100
89879100
89879100
89879100
89679100
89379100
89879100
89879100
89879101
89879101
89879101
~CC*
~QC*
ARAO
A~AO
ARAO
ARAO
o
1/8
FR .LEV TO.L EV
1
I
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
1
1
2
2
1
2
2
1
2
1
1
1
1
2
2
I
1
2
2
I
I
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
1
1
2
2
1
2
2
1
2
1
1
2
2
1
1
2
2
2
1
2
1
2
2
2
1
2
I
2
2
1
1
1
1
1
1
9-13
PAGE I\IJ
4
FROM
35P2A25
34P2A25
32P2A25
30P2A25
30P2A29
.14P2A?9
3ZP2AZ9
Z9P2AZ9
33P2A29
31P2AZ9
35P2A19
28PZR?2
29P2A28
Z9 P2 A28
33P1A28
31P2AZ8
35PZA28
32PZA28
30P2Al8
·34P2AZ8
30P2S25
34P2825
32pZSZ5
31P Z825
33P2825
29PZ825
35P2825
28P2A21
Z8P2823
29P2828
33P2828
31P2B28
35P2828
34P2828
32PZ8Z8
30P2828
19P2804
18P2807
OAP28t3
lOP 1 AZ7
26P2A21
25P2A21
26P2B08
10P1820
16P2B08
20P lAO 1
04P1818
03PlB 18
lOPIB19
17Pl B2 9
19P2B12
9-14
W IRE
TO
~6P2A2t;
31)P2Alt;
33P2 A2t;
31PZA2t;
31PZAZ9
35P2AZCJ
33PZAZ9
JOP2AZ9
34P2A1Q
3ZPZA29
36P2AZ9
29P2A2Q
28PZAZ3
30P2A28
34PZA2A
32P2AZA
36P2 AlA
33PZAZA
31PZAZA
31)P2 A2A
31P28Zt;
35P2825
33P18Zt;
32P2821)
34P28?t;
30P282t;
36P1B2t;
2 qP2 a21)
29PZ81A
30PZ8Z8
34P2B28
3ZPZBZ8
36PZ8Z9
35PZ8ZA
33PZ828
31P282A
18P lA 14
16P280Z
1 OPZ All
08PZA13
2t;P2AZl
14P2A24
2ZP2A28
05Pi8lA
10P18Z0
10P1819
05P1818
04PIB18
05P1818
16P2 BOS
17P182Q
L I S T
SIGNAL-NAME
APAO
ARAC
,\R,\O
ARAO
ARA1
_RAI
ARAI
ARAI
'\RAI
ARAI
,\.Ul
'\PAI
ARA2
_RAZ
ARA2
ARA2
ARA2
ARAZ
ARA2
ARA2
ARA3
AR,\3
ARA3
ARA3
ARA3
ARA3
ARA3
ARA3
APA4
ARA4
ARA4
ARA4
,\RA4
APA4
ARA4
'\RA4
ARCUR C .. A.
ARCUR-CA.
ASYNC 12.
A5VNC(4.
ATAUG
ATAUG
AUG7M
AUTOLOAD
AUTCLCAO
AUTOLOAD
AUTOLOAD
Al:TOLOAD
AUTOLOAD
AUTOlO,\CZt
Al.TOLGA02*
AB 1
W.L.
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879100
89879100
89819101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89819101
89879101
89819101
89819101
89879101
89879100
89879100
89879101
89879101
89879101
89879101
89879101
89819101
89879101
89879100
89879100
89879104
89879100
89879100
89319100
89819100
89379100
89879100
89879100
8987910Z
8987910Z
8911 79100
89879100
89879100
o 7/8
FR .• LEV TO.LEV
1
Z
2
Z
2
Z
Z
1
1
2
Z
2
Z
Z
Z
1·
1
1
1
1
1
1
Z
2
1
1
1
1
2
2
2
2
2
2
2
1
1
1
1
2
2
2
2
Z
2.
1
1
1
1
Z
Z
1
1
1
1
Z
2
2
2
1
2
1
1
1
1
2
2
1
1
1
1
2
Z
2
2
1
1
2
1
Z
2
1
2
1
2
2
1
1
1
1
2
1
3
i
1
1
3
1
Z
Z
89633300
A
PAGE NJ
WI R E
5
FRJ.,.
21 p~ A08
IOP2A05
18PIA25
17P2 A04
16P1821
1Qp2B03
11Pt 809
111» 2803
19P2AIO
l8P1829
I1P2A21
19,,1820
lap 1824
17PlB20
17P2819
lAPlA30
18PIA28
17P2A17
17P 214 16
18Pl827
laPIS13
17P2Al5
11P2B02
19P7A19
18PIA2b
1~Pl828
I1P2AOb
18P1B26
19P2A27
17P 2812
18PIA21
ISPIB18
lap 11424
17P2A08
13PIA18
18PIBl9
IltP'-B08
2lP180a
22P2A20
l8Pl R2 3
17P7R14
17P2B13
18PIA20
27P2B12
09 P2 1425
09P2AIO
09PLA16
09PIA03
09P2801
09P2830
09P2BOb
89633300
TO
20Pl A09
08PlAl7
17P2 A04
l5P2 A1415P2A2R
17PIB09
16PIB21
15P2B IS;
18PlB29
17P2R01
15P2Alft
17 P2 A21
11P2820
15P2A13
1 S;P2 811
11P2819
17P2A17
15P2 Al~
15P7817
17P2A16
1 7P2 141 Ii
15P?8l4
l5P2A27
1AP1A26
17P2807
18Pl B26
15P2A2~
17P2A06
laplA21
15P2817
17P2812
11P2A10
17P2AOQ
15P2816
12p2a07
11P2AOA
12P2 B07
22P2A20
26P2821
17 Pl 81,.
lSP2ROS;
1l)P2A15
17P2 B11
28P2S0A
oaPIA30
08P2 BO~
08P2B07
08P2 Bot
O~PIB31
08P2AIO
08 P2 S01
A
l
1ST
SIGNAL-NAME
AUTRSW*
A\lRES U -It)
AO
AO
AOAF+MC*
AOAF+MC*
AOAF+MC*
Al
Al
Al
AID
Ala
All
ALI
Al2
Al2
Al3
A13
Alit
Al4
A15
A15
A2
A2
A2
A3
A3
143
A4
144
144
A5
146
A7
A1
141
A7
141M
147M
A8
A8
49
149
8
8 NOE~V( 1)
8 NCENV (2 »
B NOENY(3)
B NGENV(4)
B POST~BteF
B READY F
B SKEWOYF F
A B 1 o 7/8
W.l.
89879100
89879100
89819100
89819100
89819100
89319100
89879100
89819100
89879100
89819100
89819100
89319100
89819100
89819100
89819100
89879100
89819100
89819100
89819100
89879100
89819100
89879100
89879100
89819100
89819100
89879100
89879100
89879100
89819100
89879100
89819100
89819100
89819100
89879100
89879100
89819100
89879100
89879100
89819100
89879100
89879100
89879100
89819100
89879100
89879100
89879100
89879100
89879100
89879100
8<;879100
89879100
FR.• lEV TO.lEY
1
1
1
2
2
2
1
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
2
1
1
1
2
2
2
1
1
2
2
2
1
1
2
1
1
2
2
1
1
2
2
2
2
2
2
2
1
I
1
2
2
2
1
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
2
1
1
1
2
2
2
1
1
2
2
2
1
1
2
1
1
2
2
1
1
2
2
2
2
2
2
2
9-15
PAGE NO
6
FROM
091>2A05
24Pl B2.5
24PIA22
l3P2A14
09P2B02
09P2A02
21P2831
21P2A30
18PtA13
18PlA27
IBP'A01
17PIA14
15?lA]1
09P2A29
14P2S19
28P2829
09P2AOI
14P1814
13P1814
17P 1815
l')P7B23
I1PlBl8
12PIB09
14-P2A07
13PIB28
19P2A30
24P7 Al8
28PIB19
19PIA31
19P2 AOIt
19P 1813
19P1A12
19PIAll
19P I A08
l~Pl A06
19PIBOit
19PIB21
19PIB20
19PIA21
19P1819
19PIA18
19PIB15
I:}P1814
19PIBI0
I1PIBIO
14PlAl1
19P2B05
11PIA24
19P2 A29
lSP2809
18P2811
9-16
\oJ
I
TO
08PlA28
22P2 A27
23PIB30
IIPIA17
OA P2 817
OAP2Blt;
20PlA07
2 OPt B2f»
l7Pl A30
17PIB17
16PIA2l
16PIAOA
t6Pl A08
08P2820
13P2801
27P2 B27
OAP2814
t3PIB14
12 PIB20
t6PIA16
16PIAlt;
16Pl t:ll,)
08P1Al')
12P2BIO
12P2BIO
15P2A07
22 P21321
27PIA2t;
IBPIA1')
18Pl Bllt
18PlA12
18PIBI2
18PIA16
lSP 181 ')
IBPl B17
lAPlAlR
18PIB16
laPl A17
1 BP lA21
18P1821
1SPIA22
1 BPI B27
lS1>1810
18PIAI0
16PIAOQ
13PIBl1
IAP2A06
16PIB13
11Pl A24
16P2B2t;
16P2B2 7
R E
l
[ S T
SIGNAL-NAME
B
Be
~RES(
1-4.
BBCK
BCD
BCI*
BC2
BEA
BEAC
Bl-BOIHCYl
Bl,=O
BL=O
SCNEF*
SOT
BRWRA*
SSI*
BUF 1/0*
8UF 1/0*
8UF F 1- BlJF F 2
8UFFlBUFF2*
BUFF2 FUll*
BUFF2FL*kMO
BUSY
BUSV
BUSY RR*
BXl5
CAA15
CAC WAO
CAC WAI
CACkAIO
CACWAII
C AC WA12
C ACWA 13
CACWA14
CAChA1S
CACWA2
CACWA3
CACWA4
CACWA5
CACWA6
CAC kA 7
CACWA8
CACkA9
CAL -SH IFT*
(ARCURAD*
C ARST*
CAU SHIFT*
CAU S~IFT*
CAL J*
CA12*
A B 1 a 1/B
w.L.
89819100
89319100
89379100
89819100
89319100
89319100
89819100
89819100
89819100
89819100
898'19100
89819100
89879104
89319100
89879100
89819100
89819100
89d 19100
89819100
89819100
89819100
89879100
89819100
89819100
89879100
89819100
89819100
89819100
89a 79100
89a 19100
B9879100
B9819100
89819100
89619100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
B9819100
89879100
89819100
89819100
89d 19100
89819100
89879100
89879100
89819100
89819100
fR.lEV TO.L EV
2
I
2
2
2
2
1
1
1
2
2
1
2
1
1
2
1
2
·2
1
1
1
1
2
2
I
2
2
2
2
1
1
1
2
2
1
2
1
1
2
1
2
2
1
I
1
1
2
1
1
2
1
2
1
2
1
2
2
1
1
2
1
2
1
2
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
2
1
1
2
1
2
2
1
1
2
1
1
1
89633300
A
PAGE N1
W I
1
FROM
1ap2AOa
18P2AIO
18P2 B08
18P2A05
18P2AO 1
18P2A04
lRPlA05
18P2A22
18P2B06
lRP2B06
l8P2 A09
~1P2AIO
30PIB23
31P2Bli
35P2A26
331>2A26
3lP2A26
29P2A26
32P2A2b
30P2A26
34P 2A26
27P2827
l'iP1807
23P2831
2lP2B25
12PIB21
02PIB07
06Pl B07
OlPIB01
26PIA03
19P1B29
19P2A05
19P2A13
lQP2BOb
lRP2817
13P2 A02
26Pl 1428
25PlA28
23P2A15
23PIA23
21P2BIO
22PIB01
25P lA13
26PIB20
28P2AOb
25P 1831
26P1811
25PIA31
26P 1 A3l.
25Pls29
26PIB29
89633300
TO
16P2B20
16P2B2R
16P2B31
16P2B2<}
16P2 B30
16P2Blit
16P2BlS
lSP2AOB
15P2Al1
16P2BIQ
16P2B18
30Pl B2l
20PIA28
21P2AlO
36P2A26
34P2A26
32P2A26
30P2A26
33P2A26
31 P2 A26
35P2A26
29P2 A26
12Pl B21
20P2B25
15PIB07
C7PIB01
06PIB07
01Pl B07
02PIB07
25PIBOl
17PL B06
17PIB24
11Pl A18
16P2 BOli
11PIB22
12PIA05
25Pl A28
20PIB01
2lP2B12
24PIA31
23PIA23
25PlA11
26PIA13
21P2A29
27P'l. B01
20PIB11
20PIA14
20PIBIQ
20PIB15
20Pl ALB
20PIB14
A
R E
l
r S T
A B 1
SIGNAL-NAME
W.L.
CA13.
CA15.
CA16*
CAll*
CA18*
CAI9*
CA20*
CAl.
CA65M*
CA65M*
CA7*
CCPE*
cePE.
CCPE*
CE*
CE*
eE*
CE*
CE*
eE*
CE*
ce*
CHI.
CHI*
CHI*
CHI*
CHI.
CHI.
CHI.
C(
CKWO SHIFT
CKWOL 1
CLEAR CKWO*
CLEAR CCNTR
CLE AR-SHI FT
ClR LOWER.
CLREG*
ClREG.
CLREQ
ClRIR
ClRIR
CLRQ*
ClRO*
ClRXM
CMOR*
CNSOL*
CNS(M*
CNSIL*
CNSIM*
CNS2L*
CNS2M*
89879100
89879100
89819100
89879100
89819100
89319100
89819100
89879100
89879100
89819100
89819100
89319100
89819100
891319100
89819101
89879101
89879101
89819101
89879101
89879101
89879101
89819100
89879100
89819100
89819100
89879100
89819103
89819103
89879103
89819100
89879100
89879100
89879100
89819100
89819100
89879100
89879100
89879100
89819100
89879100
89819100
89819100
89879100
89819100
89879100
89819100
89819100
89879100
89819100
89819100
89879100
o
7/8
FR .LEV TO.LEV
1
1
1
1
1
1
1
2
2
1
1
2
1
1
1
1
I
1
2
2
2
2
1
1
2
2
2
1
1
2
72
1
1
1
2
2
1
2
2
1
1
2
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
2
1
1
1
1
I
1
2
2
2
2
1
1
2
2
2
1
1
2
2
2
1
1
1
2
2
1
2
2
1
1
2
1
2
1
1
1
1
1
1
9-17
PAGF NO
8
W I
R E
l
1ST
A B 1 o 1/8
FR)~
TJ
SIGNAL-NAME
W.L.
25PIB28
26P1B28
25P2B12
26P2Bl2
25P2A 11
26P2Ali
25P2B13
26P2B 13
25P2B14
26P2B14
22PIA17
23P2A09
25PIB21
26PIB23
19P2 A12
14PIA28
I1P2AO 1
28PIBl3
3]P1B14
3lP2809
12PIA3l
27P 1826
33P1823
22PlA12
21P lAO]
31P2All
24P1B26
25PIR03
21P1825
26PIB03
21PIB19
24P2820
24P2A04
: 2ltP1803
23PIA04
24P 2A10
22P1A31
24P2A21
23P1829
16PIA26
19P2A08
3lP2B05
27Pl A2 8
18Pl828
18PIB28
21P2B16
22PIB09
25P2AIO
2'5PIAOl
26PIAOI
22P1804
20PIA20
20Pl A15
20PIA01
20PIBO]
20PlA06
20PIA03
20P181l
20PIA04
20PIAll
2 OPl B05
. 23P2AOQ
24P2A30
22PlAOlt
25PIB23
11P1B16
12P2A06
12P2A02
22P1811
28PIBl3
27PIA31
11 P2 B30
28P 1822
28PIR22
27PIB26
24P1826
21P2 A09
21P2AOQ
23PIB19
20P2 B05
25P1801
21P1825
2 OPl B21
20Pt81'
20PIA25
20P18l0
20PIA21
20PlS31
22PIAll
20Pl829
15P2831
16PIA26
21PIA28
21P2804
I1PIAOA
19PIB25
CNS3l*
CNS3,..*
CNS4l*
CNS4,..*
CNS5l*
CNS5M*
CNS6l*
CNS6M*
CNS7l*
CNS1M*
CNTE2*
CNTE2*
CO
CO
CCMPARE
ceN TAC T
CONTACT*
CP8M*
CP8M*
CPEC*
CRCC STATE*
CRI *
CRI*
CRI*
CICO
CRO
CfCO
CRO*
CfCO*
CRO*
CRO*
(SA*
CSM*
CSP*
CSPR
CSo*
csx*
89819100
89879100
89879100
89879100
89879100
89819100
89879100
89319100
89a 19100
89819100
89819100
89319100
89819100
69819100
89819100
89319100
89879100
89819100
89819100
89879100
89819100
89819100
89819100
89879100
89879104
89819104
89879104
89879100
89379100
89819100
89819100
89819100
89879100
89879100
89819100
89879100
89879100
89819100
89879100
89919100
89819100
89819100
89819100
89819100
89879100
89819100
89819100
89819100
89879100
89879100
89819100
9-18
28P2B7.~
2'5P2AIO
26P2AlO
22P1801
25Pl A01
25P2 83 t
C~X*
CSy*
CTRLR BUSY
C TRlR 8l ~ \'
CVIOl*
C ~ I 01*
C"A-C(UNT*
CW~-COUNT*
cxp*
Cl
Cl
C2
C2
C3
FR.LEV TO.lEV
1
I
1
1
I
1
1
1
I
1
1
2
2
1
2
2
2
2
I
1
1
2
1
1
1
1
2
2
1
1
1
1
1
1
2
1
1
2
1
2
2
1
1
1
2
2
1
1
1
1
1
1
I
1
1
1
1
I
I
2
2
1
2
2
2
2
1
1
1
2
1
1
1
1
2
2
1
1
1
1
1
1
2
1
1
2
1
2
2
1
1
1
2
2
1
1
89633300 A
q
PAGE NO
FROM
25P7.Bl1
19 PlIH 7
18P2R13
13P2B14
24-1>1B21
27P2B17
24P1A14
22P~B30
241>?810
24P1A15
lc}1>2Al4
211>2fH9
21 P~ B08
~lP2B18
29P1803
321>1B03
30P1803
34P1803
31)1'1B03
33P 1803
311'1803
7.91>1803
2Ql>lA03
331>1A03
31P1A03
15P1A03
30PIA03
~41>1A03
32PIA03
29PIA03
2ql>1A28
34P1 A28
321>1A28
301>1A28
35PlA28
33PIA28
311>1A28
29Pl A2 8
79P lA21
33P1A27
31P1A27
351>1A27
30 PI A27
34PIA27
32PIA27
29Pl A27
l8PIB24
341>1825
32Pl B2 5
30PIB25
291'187.5
89633300
W 1 R E
TO
26P2B 31
11P1Al()
1 7P18 14
121>1A01
.21 P1 AOI)
2AP2BIA
22P1411)
? 4- P2 B 1 0
?5P2R 1'"
21 P2 A2h
I1)P2AOl)
21P2808
23PIR01
27P2BIC}
28P1AO?
33 1>1 ~04
11P1801
31)P1801
36P180l
14P1803
32 PI 801
10P1801
30P1A03
14P1401
32P1A03
36P1403
31 PI A03
35P1AOl
331>1~O3
2 APl 80'
2 8P1A 11
31) 1>1 A28
33PIA2 A
31PIAl8
16P1478
34P1A2A
321>1A28
) OPI Al8
30PIA27
14P1A27
32P1427
361>1A27
31 PI A27
351>1A21
33P1A27
7.8 PI 816
2ql>lB 25
35P1B2')
331>1821)
311>1621)
30P1821)
A
l
IS T
SIGNAl-NAt-E
C3
f).No.teMP.
DATA
DATA
DPR
DE*
DEL*
DElTAUG*
DEL TAUG*
DEl2
OF-GATED
OFEO
DFEO
OFEO
DINa
DINO
DINe
o INO
DINO
DINO
DINO
OINO
DIN 1
OlN1
DINl
. DIN 1
DINl
DINl
DIN 1
DINl
OlN10
OINIO
OlNI0
DINIO
DINIO
DI~10
DIN 10
DINIO
DINll
DIN 11
OlN11
OINtl
OINll
DINll
OIN 11
OINll
OlN12
DIN 12
O(N12
OINt2
DIN 12
A i3
~
.L.
89879100
89879100
89879100
8'1879100
89a 79100
89879100
898791JO
89879100
89819100
89d19100
89319100
8981"9100
89879100
89879100
89d19100
89819101
89819101
89d79101
89879101
89879101
89d79101
89819101
89819101
89879101
89879101
89819101
89879101
A9d 19101
89879101
89879100
89:319100
89819101
89879101
89819101
89879101
89819101
89879101
89879101
89819101
89879101
89879101
89879101
89379101
89879101
89819101
89;:J 79100
89819100
89879101
89B 79101
89819101
89879101
1
o
7/8
fR.l EV TO.l EV
2
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
2
2
1
1
1
1
1
1
1
1
2
2
2
7.
2
2
2
2
1
1
1
1
1
1
1
1
2
2
2
7.
7.
7.
2
2
1
2
1
2
2
1
1
2
2
1
1
2
2
1
1
2"
2
2
2
1
1
1
1
1
1
1
1
2
2
2
2
2
7.
2
2
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
1
9-19
PAGE N()
10
FROM
33PlB25
31P1825
35PIR25
29PIB21
33PIRZ'1
31P1827
351> 1827
30P1821
34P1827
32PIB27
2CJPIB21
29PIBZ8
32P1828
30Pl R28
34PIR28
29PIBZ8
33P1628
3lP 1628
35PIBl8
29P 1 B26
331>1826
31PIB26
35P1826
30P 1826
34P1826
321>1B26
29P1826
28P281Z
341>2A04
32P2A04
30P2A04
35P2A04
, 33P2A04
31P2A04
29P2A04
35P2A05
33P2A05
llP2A05
29P2A05
301>2A05
34P2A05
3lP2A05
28P2AI0
2'JPl A05
32PIA05
30PIA05
34Pl A05
29PIA05
33PIA05
31PIA05
35PIA05
9-20
W J R E
TO
34P182S
32PIB2C)
36PIB2S
30PIB21
34Pl821
32 PI 821
36P1821
31P1821
35Pl B21
33P1821
28P1826
28PlA 25
33PIB28
31 PI B2R
35PIB28
30PIB28
34Pl B28
32PI828
J6PIB28
30P1826
34P1826
32PIR26
36PIB26
31P1826
35P1826
33P1826
28P1825
2 QP2 AO.
35P2A04
33P2A04
31 P2 AO.
36P2A04
34P2A04
32P2A04
30P2A04
36Pl AOt)
14P2A05
32P2AOt)
3 OP2 AOI)
31P2AOC)
35P2A05
33P2 AOt)
29P2AO'i
28PtA04
33PIAO'i
31PIAOli
35Pl AOt)
30PIAO'i
34PIA05
32 PI AOt)
36PIA05
l
I S T
S IGNAt-NAME
OlN12
DINt2
DIN12
DINt3
o INI3
OlN13
DIN1)
DIN 13
DINl3
DIN13
DINl3
DIN14
DIN14
OlN14
OINi4
DIN14
DIN14
DIN14
DIN14
DIN15
DINt5
DIN15
DINt5
DINl5
DINlS
DINt5
DINl5
DINl6
DIN16
DIN16
OlN16
OIN16
DIN16
DINt6
OlN16
DINl1
DINt7
DINt1
OlNl1
DINl7
DIN 17
DIN11
DIN11
DIN2
DIN2
DIN2
OlN2,
DIN2
DIN2
DIN2
OlN2
A B 1
W.t.
89879101
89879101
89819101
89879101
89879101
89879101
89819101
89879101
89879101
89879101
89iJ 79100
89819100
89879101
89879101
89819101
89879101
89819101
89819101
898'79101
89ff19101
89819101
89879101
89879101
89879101
8981910 1
89819101
89819100
89a19100
89819101
89819101
89819101
89879101
89819101
89819101
89819101
89819101
89819101
89d 19101
89819101
89879101
89819101
89879101
89819100
89819100
89879101
89879101
89879101
89819101
89879101
89879101
89879101
o
7/8
FR .lEV TO.lEV
t
1
1
1
1
.1
t
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
1
t
1
1
1
1
1
1
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
89633300 A
PAGE NO
W I
11
FQ.l~
29PIA01
331'1801
31P1B07
15P1807
101'1801
34Pl801
321'1801
29P 1801
Z9P1 A07
34PIA01
32PIA07
3JPIA07
29PIA01
33PiA07
llPIA07
15Pl A07
291'1816
33PIR16
:'UPlfHb
:i5PIBI6
30P UHI>
34P lR 16
3?PIBI6
Z<)PIIH6
ZC}PlAI5
32PIA15
3()PIA15
34P1A15
29PIA15
33PIA15
31Pl.A15
35PIA15
29P1Al8
33P1A18
31PlA18
35P1A18
30PlAlA
341> 1 A 1 8
32PLA1B
29Pl A1 A
29::>1819
34P1619
32PIB lq
30»> 1 B 19
2:JP1B19
33P1619
31P1B19
35PIB19
29PIB20
33P1820
31PIB20
89633300
T1
30 Pl BOl
34P1B01
32PIB01
36P1801
31PIBC7
35P1801
33 PI B'J1
28PIA03
28Pl AOA
35PIA01
33PIA01
31 PI A01
30P1AC1
~4PIA07
32 PI A07
36PIAG1
30PIB16
34Pl Bl~
32PIB16
16PIB16
31PIBlh
35PIBlh
3 31>1 B1 h
2SP}A07
2BPIAlh
33PIA15
31PIA15
3SPIA15
30PIA15
34PIA11)
32PlAl5
36PIA15
30PIA18
34P1418
32PIAIR
.16P1 A18
31 P1 Al 8
15PIAl8
33P1A18
2AP1B11
28PIA14
35 P1 B19
33P1B19
31PIB19
30PIB19
34PIB19
32PIRl9
36P1 B19
30P1B7.0
34PIB20
32PI1320
A
R F
l
I S T
SIGNAl-NA~E
DIN3
DIN3
DIN .3
DIN3
DIN3
D IN3
DIN3
DIN3
DIN4
DIN4
DIN4
DIN4
DIN4
D IN4
OlN4
OIN4
DIN5
DIN5
DINS
DIN5
DIN5
DIN5
DINS
DIN5
OIN6
DIN6
DIN6
DIN6
OlN6
OlN6
DIN6
DIN6
OlN7
DIN7
OlN7
DIN7
D(N1
OlN7
DIN1
OlN1
D[N8
DIN8
DINS
-DIN8
DIN8
DINS
DIN8
DINA
OlN9
DIN9
OlN9
A
jj
W.L.
89819101
89879101
8<1819101
89819101
89819101
89819101
891319101
alia 79100
89879100
89879101
89879101
89879101
tVld79101
89819101
89d79101
89879101
89879101
89879101
89879101
89:379101
89819101
89879101
89879101
89819100
89879100
89879101
89d 7910 1
89d 7910 1
89d 79101
89979101
89819101
8987910L
89879101
89879101
89879101
89819101
89819101
89819101
89879101
89879100
89d79100
89879101
89819101
89B79101
89819101
89879101
89879101
89879101
a~a 79101
89179101
89819101
1
o
118
FR.LEV TO.LEV
1
1
1
1
2
2
?
2
2
2
2
2
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
9-21
PAGE NO
12
FROM
35PIB20
30PIB2O
34Pl820
32P1820
2~ PI 820
27P2RIO
30P2A21
34P2A21
32P 2A 21
35P2A21
33P2A21
31P2A21
29P2 A21
19P2B08
IRPIB31
19P2A09
19P1830
21P1801
29PIA02
33P lA02
31 PI A02
35PlA02
34PIA02
32Pl A02
30PIA02
30PIA04
34PIA04
32PIA04
29Pl A04
33Pl·A04
31PIA04
31)PIA04
27PIA02
29P1824
31)P1824
33P1824
31PL824
29P1824
34Pt824
32P1824
30P1824
30P 1A30
34Pl A30
32PIA30
29PIA30
33PlA30
31PIA30
31)PIA30
29Pl A30
29PIA31
29PIAll
9-22
\II
( R E l
Tn
36PIB1O
31P1820
35PIR20
33P1820
28Pl A18
29PlA 21
31P2 A21
35P2A2t
33P2A21.
36P2A21
·l4P2A21.
32P2A21
30P2A2t
lRP181l
l1PIAIft
11t»IAll)
16PIA 28
29Pl AO'30Pl A02
34,PIAO'
32PIA01
36PIAO,
35PIA02
33Pl A02
31PIA02
:JIPIA04
35Pl A04
33PIA04
30PIA04
34Pl A04
32PIA04
36PIA04
Z9PIA04
21PIA16
36P1824
14P1824
32P1824
30P1824
35P1824
3.3PI824.
31 P18?r.
31PIA30
35P1A30
33PIA30
30P1A30
34Pl A30.
32P1A30
. 36PIA30
21Pl Al1
21P lA 21
lOPl A31
1ST
SIGNAl-NA,,-e
0lN9
DIN9
DINg
0lN9
DIN9
DISABLE
DISABLE
DISABLE
DISABLE
o ISABl E
DISA8lE
DISABLE
o ISABl E
oOF
OOf
OOF-LA
OOF-lA-AlTO·
OOU10
00U10
00U10
00U10
oOUTo
00U10
OOllTO
OOUTO
DOUTI
OOUTI
Doun
OOUTI
oOUTI
OOUTI
oOUTI
Doun
00UT10
00UTI0
ooun c
oOUllO
naUllO
ooun c
DOU1I0
DOU110
OQUTl1
OOUTll
oOUTll
OOUTll
OCUTtl
oOUTll
00UT11
OGUll1
OOUTl2
00UT12
A B 1
\II .l.
89819101
89819101
89819101
89819101
89919100
89819100
89819101
89819101
89879101
89819101
89819101
89819101
89819101
89819100
89319100
89819100
89819100
89819100
69819101
89879101
89819101
89819101
89819101
89819101
89819101
89819101
89819101
89819101
89819101
89819101
89879101
89819101
89819100
89879100
89879101
89879101
89819101
89879101
89879101
89819101
89879101
89819101
89879101
89819101
89879101
89879101
89819101
89819101
89879100
89319100
89979101
a
118
fR.L EV TO .lEV
1
2
2
2
2
2
2
2
2
1
1
1
1
2
2
2
2
2
2
2
2
1·
1
1
1
1
2
1
2
2
2
1
2
2
1
1
1
1
1
1
1
2
2
2
2
2
2
1
1
1
1
2
2
1
1
1
1
2
2
2
2
2
2
1
1
1
L
2
2
1
1
1
1
2
2
2
2
2
2
1
1
1
1
2
2
1
1
1
1
2
2
2
2
2
2
1
1
1
1
2
2
1
89633300 A
PA(;E N)
13
FRUM
33PIA31
31PIA31
35PIA31
':l4PIA31
32PIA31
30PLA31
30Pl829
3~PIR29
32PIR29
Z9Pl829
33PIRl9
':\lPlB29
35PIBl9
29PIB29
29P1830
29Pl B30
33PlB30
31PlB30
35P1830
32PlB30
30P IB30
34P1830
30P IB 31
34PlBli
32PIB31
29PIB31
33PIB31
3lPl B31
35PIB11
?9P1831
29P2AOI
21P2AOI
33P~AO 1
31P2AOl
3SP2AOI
3lP2AOI
10P2AOl
34PlAOl
':lOP2A02
34P2A02
32P2 A02
2t}P2A02
33P2A02
3lP2 A02
35P2A02
27P2B05
28 PlBIO
Zt}P lA06
29PIA06
33PIA06
31PtA06
W J
TO
34P LA .31
32PIA31
36Pl A3'.
35PlA31
33PIA31
31PIA31
31PIBZ9
35P1S29
33PIRl9
30PLB29
14P18l9
32P18l9
36P1829
21PIA2lt
27PIR24
30PIB30
34P1830
32PlB30
36PL 830
33PIB30
31PIB30
35P1830
31PIB.31
3SPIB3l
33Pl B31
.30PlS.3l
34PlBll
32Pl Rli
36PIR31
27PIB2S
27P2 A16
30P2AOl
34P2 AOt
32P2AOl
36P2AOl
33P2AOt
31P2AOI
3'5PlAOl
31 P2 AO?
l5P2A 01.
3 3P2 AO?
30P2 AO?
34P2A02
32P2A02
36P2A02
lAP2810
29Pl AO?
21P1804
30PIAO&
34Pt AO£»
32PIA 0&
89633300 A
R E
L I
S T
SIGNAL-NAME
OOUTl2
OOUT12
DOUT12
OOUH2
DOUT12
OOUT12
DotHl3
DOUTI3
DOUTt 3
00UTt3
00UT13
OCUTl3
OOUTt3
00UT13
OOUTl4
00UT14
00UT14
00UT14
00UT14
OOUT14
00UT14
00UT14
OOU11 5
OOlJ TIS
00UT15
OOUTlS
DOUT15
DOUTl5
OOlJTlS
00UT15
OOUT16
OOUT16
00UT16
OOUTl6
00UT16
00UT16
00UTl6
OOUT16
OOUT17
00UT11
00UTl1
OOUTl1
00UT11
00UT11
OOU111
00UT11
OCUTl1
00UT2
00UT2
00UT2
00UT2
A B 1
W.L.
89879101
89819101
89879101
89879101
89879101
89819101
89819101
89879101
8987910 I
89819101
89819101
89879101
89819101
89819100
89819100
89819101
89819101
89879101
69819101
89819101
89819101
89819101
89819101
89819101
89819101
89819101
89819101
89879101
89819101
89819100
89819100
89819101
89819101
89879101
89819101
89819101
89819101
89819101
89819101
89879101
89819101
89819101
89879101
89319101
89819101
89819100
89819100
89819100
89879101
89819101
89819101
o
7/8
FR .lEV TO.LEV
1
1
1
2
2
2
2
2
2
1
1
1
1
2
2
1
1
1
1
2
2
2
2
2
2
1
1
1
1
2
2
1
1
1
1
2
2
2
2
2
2
1
1
1
1
1
2
2
1
1
1
1
1
1
2
Z
2
Z
2
2
1
1
1
1
2
2
1
1
1
1
2
2
2
2
2
2
1
1
1
1
2
2
1
1
1
1
2
2
2
2
2
2
1
1
1
1
1
2
2
1
1
1
9-23
Pt\GE NO
14
FR]M
35PIA06
32PIA06
30PIA06
34PIA06
]OPI A08
~4PIA08
32PIA08
29PIA08
3~PIA08
31PIA08
35PIA08
29PIA08
29PIA09
29PlA09
3~Pl A09
31PIA09
35PlA09
34PIA09
32PIA09
30P1 A09
30PIA14
34PIA14
32PIA14
29PIAl4
33PIA14
31P1A14
35PIAl4
29Pl A14
29PlA17
29PIA17
3JPIA11
3lPIA17
35P1A11
32PIA11
30P1A11
34PIA11
30PIA19
34PIA19
32PIA19
29PIA19
33PIA19
31PIA19
35PIA19
29PIA19
2~PIA20
29PIA20
33PIA20
31P1A20
35PIA20
34PIA20
32PIA20
9-24
W
r RE
TO
36Pl AO~
33PIA06
3lPlA06
35Pl AO~
31PlAOR
'35Pl AOA
33 PI ADA
30PIAOR
34P1 AOA
32PIAOR
36P1AOA
27PIRO~
21PIB01
30PlA09
14Pl AQq
3?PIAOC)
16Pl A09
15Pl AOC)
33PlA09
3lPl A09
31PIA14
15PIA14
33PIA14
30PIA14
34PIA14
3?PlA14
36PIA14
27PIB09
21PIBIO
lOPlA 11
34P1 A17
3lPIA17
36PIA17
33 PI A17
1IPIA17
15PI411
31 PI A19
35P1419
33PIAl9
30PIA19
~4PIA19
32PIA19
36PlAIQ
21PIB12
21 PI All
30PIAlO
34PI4.20
32Pl A20
36PlA20
35PlA70
33PIA20
l
r
S T
S(GNAl-NA~E
DOUT2
DOUT?
DOUT2
OOUT2
DOUT]
DOUT3
DOUT3
DOUT3
DOUT3
DOUn
DOllT3
DOUT3
DOUT4
DOUT4
DOUT4
DOUT4
DOUT4
DOUT4
DOUT4
DOUT4
DOl) T5
DOUT5
OOUT5
OOUT5
DOUT5
DOUT5
DOl!T5
DOUT5
DOUT6
DOUT6
DOUT6
DOUT6
DOUT6
DOUT6
nOUT6
DOUT6
OOUT1
OOUT7
DOUT1
DOUT1
DOUT7
DOUT1
DOUT1
DOUT7
DClJ Ta
DOLTS
DOUT8
DOUT8
DCUT8
DGUT8
onUT8
A B 1
W.t.
89879101
89879101
89879101
89879101
89819101
89a79101
89319101
89819101
89979101
89879101
89879101
89379100
89879100
89979101
89819101
89879101
89819101
89879101
89879101
89819101
89879101
89879101
89819101
89819101
89819101
89819101
89879101
89819100
89879100
89879101
89319101
89879101
89879101
89879101
89879101
89819101
89879101
89879101
82829
14P2A04
18P7.B20
15P IB23
25PIB20
19P2826
13P2A09
20P2B08
151>1B23
01PIA09
OlPIB23
06P IB23
01PIB23
9-28
W
r
TO
23P2 A24
22 P2 BI0
21PIA28
22P2Bl1
21PIAI0
21P2A06
21P182A
15P2B01
16P2BOI
16P2826
15P2802
12PIA09
11Pl A09
21P1A21
21P1B2COl
MXOM
MXCM
M)lOM
A B 1
W.l.
89879100
89819100
89879102
89879102
89879100
89879100
89a 79100
89819100
89879100
89819100
89879100
89879100
89a 19100
89879100
89879100
89879100
89879100
89879100
89879100
89819100
89819100
89879100
89819100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89379100
89819100
89879100
89819100
89979100
89879101
89879101
89819101
89819101
89819101
89879101
89879100
89879100
89819100
89819100
89879100
89879100
8913 79100
89819100
89819100
89819100
o
118
FR.lEV TO.lEV
3
3
3
3
1
1
2
1
1
2
1
1
2
2
1
1
1
1
1
2
2
1
2
1
1
2
2
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
2
2
1
1
2
2
2
1
1
2
2
1
1
2
1
2
2
2
2
2
1
1
1
1
1
2
1
2
1
1
1
2
2
2
2
1
1
1
1
2
1
1
1
1
1
2
1
9-29
PAGE NO
20
fROM
W I
T1
31P1602
24P1A16
25PIA19
26PIA19
2lt-PIAl3
llPl811t31PlR03
11P2A19
27Pl BO~
25PIAlPIA02
11P2B09
25P2A22
UPIA11
2\)I>2R18
1jPIA19
UP1/:i20
1~Pl11I6
20P2A19
25P2H72
l')PIROl
17P2B08
06PIH03
alP 1/:i0:1
02 PI RO 3
02Pl H04
OoP 11:)04
01 P I Ru 4
26P?AO'5
15PIR04
17P'!A13
l'JPIA15
?OP?B23
14"lBZQ
14P 1 1122
19PIA13
?OP2R24
15P1805
17 P2 A12
26P7A02
06 P IROl)
01 PI80 ')
02PIAO')
22PIBlo
21PlRl'3
22:> UH 2
21PIA13
24P1AO.?
23P1B22.
2lP2Bl1
24P7R16
17P7B05
UPlA22
23.,lA27
23PzA04
21PIB23
89633300 A
..,
I
T1
R F
l
I S T
S IGNAl-NA~E
O?Pl AOl
06PIAOl
06P 1 ALP
C7Pl AD'
OA5*
OA5*
OA6*
02Pl~O?
OA6*
OA6*
OA6*
OA6*
OA6*
OA6*
OAA*
flA7*
pA7*
OA7*
Oll7*
OA7*
OA7*
OA7*
OA7*
OA7
OAR*
OAA*
CA8*
OA8*
OAH*
CA8*
OA8*
OA8*
IlAR*
OA9*
OA9*
0119*
OA9*
OA9*
OA<;*
OA9*
OAg*
OA9*
00*
oCO*
000*
nco*
OCD2
0002
1 Wl A19
1 QPl Al 7
20P2RIA
ItjPl~()?
17P2H09
07P1AO]
07 PI ~O~
lSPIRal
17PZ'10R
?OP2 Al 'I
1 ~PIR?()
19P1f11A
07Pl~Ol
J?Plf10l
06PIBtH
0f1PIR04
C7PIR04
02PlB04
20P21:Pl
14Plf3?9
19PIA1'>
I,)P 1 B04
17P241'.:\
07PIA04C7PIBO'5
l'5PIRO'>
17P2,U]
14P 1 B 2;>
19P1 All
201>2824
07PIBO,>
()7 PI BO'>
C6PIB05
24f>? :\01
2'3 P2 B19
24Pl RD'I
2?PIBP
23PIRl7
22PlA2R
23PlBl1
23P7A16
L6P2ROl
17P2f\O'i
??PIBl4
?4PZB2Q
?()PIB2~
OA6*
*
0002*
016*
eN C Vl
eN
CYl
OP
OPE*
OPINO
A B 1 0 1/8
w.l.
89879103
89379103
d9319103
89319103
8'H19103
89319100
89'J19100
89979100
89819100
89379100
8987:H00
89819100
89-379100
89d19100
89-119100
89819100
893 7'J 100
89 i 7910 3
8':7379103
89879103
69819103
89a 19103
89379t()3
89819100
8<;819100
89319100
89879100
89'379100
89619100
A9 P2 A1ft
OAPIA2h
(;9 PI R24
(;t)Pl A30
OBP2R2,h
OPST
OP20*
OSC*
nVFL*
OVfl*
D'IIFW*
01*
01*
01*
012
012
02*
02*
PAR
PAR ERR.
PAR ERR.
PP.C
PC 16CO*
10PIA~1
09 PI A:H
24PIB,0
O~PIB24
IJPIB24
10PIA 30
09PIA30
27PIB28
13P2A18
14PIR2j
28PIAlj
13P2801
09P21301
26PIR13
2SP 1 B 13
21P2A22
10PIB01
13P1RJi
14P2 AUI
13PIB'~0
11PIB29
14P2R23
12P 11375
13P2B06
1~P7ROR
13P2A29
11P7A30
24PIA27
04P1Al1
O~PIAI7
12P1801
21PIR06
27P2R2b
19:>IAI0
20P2 A07
31P2A?7
21PIA14
22PlBl9
22p2R20
21P2R05
25P1A23
26PIA23
25P2A01
~qP2All
I1P2R17
13P2AIA
~ 7P2 A2:>
10pl1\01
10P2AOI
?5Pl!:Hl
23P1811
20PIA2h
CC;PIBOI
ORP 1 AlB
OAP2AIQ
08P2BOQ
08P2 AOI)
1 ~ P7 B01,
OAPiB02
oaP1807
08P2817
aQp2A14
08PIB1~
71il?AOQ
05PIA17
(14Pl A17
05Pl1\17
19PIAI0
2 OP2 A17
l?PIBOl
21 P IR06
27P2 B7ft
23PIA1'l
21P1B08
23PIA27
22P2R20
21P2AOI
?lPIA21
21p2ROl
A
S T
2P~B06
22P2A12
26P2B27
9-34
I
22PIA19
22PIAIQ
22PIA()6
2lPIAO-'
22P2412
)
Vi
OPO*
AS 1*/8S0 *
PCK
PCK
PCl*
pe2
PE
PE
PE
PE
ENABLE
fOP*
LOST C,dT
PAR ERR
pE ST,dRT
PE: ST,dRT
pE STtRT
PE WOI 25P lA 11
12 P 2B22
20P2B16
26PIAl2
24PIA19
25Pl A12
16P2B12
10PIAOl)
10Pl A20
09P1AOl)
09P2Bl2
09PIA20
10P2A21
09P2A27
lOP2B12
lOP2B03
08Pl A07
10PlA02
10PIB21
O<)Pl AO?
O<)P2810
09P1821
1 OP2 821
09P2821
lOP2BI0
10P2B08
08PIAIO
08Pl A02
OSPIA1)
21P2Al1
20Pl821)
22P2A21
2.6Pl A14
25Pl AI419PIA28
20P2 AOI)
25P2A06
24P2802
26P2A06
25P2A26
26P2A26
12P1831
15PIA12
01PIA12
01Pl A12
02PIA12
06PIA12
12P2BOI
01P1B 12 .
15P1812
19P2802
15PIA11
15P2 AIO
PSFM*
PTAOO
PlAOO
PlADO
PUR*
PWOIN 0
PwOIN 1
PWOIN 2
PWOIN 3
PWOIN It
PWOIN 5
PWOIN 6
PWOIN7
PWOINP
PWIO
PWOUT 0
PWOUT 1
PWOUT 2
PWOUT 3
PWOUT It
Pt-OUT 5
P"'OUT 6
PWOUT 7
Pt.OUTP
PWRESET
PWRO
PWROSHI F TEO
P16
P4H
PitH
OCK
OCK
00
00
OSX
OSX
OSX
OlAOD
OTAOO
00
00
00
00
00
00
01
01
01
01
010
010
89879100
69879100
89879100
89819100
89879100
89819100
89819100
89819100
89879100
89819100
89819100
89819100
89879100
89879100
89619100
89819100
89819100
89879100
89819100
89819100
89819100
89879100
89819100
89879100
89819100
89879100
89879100
89819100
89819100
89879100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89879100
89819100
89819103
8981910.3
89819103
89879100
89819100
89819100
89879100
89879100
89819100
>02P1612
>06P1B12
>01P1B12
06P1B12
f)7P1B12
02P1B12
Ql
Q1
Q1
89879100
89879100
89B79100
9-36
o
7/8
FR.lEV TO.lEV
1
2
2
1
1
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
2
2
1
2
2
1
1
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
2
2
1
1
2
2
1
1
1
2
1
2
2
1
1
2
2
1
1
1
2
1
1
2
2
1
2
1
1
2
2
2
2
2
2
1
1
1
1
2
1
1
1
1
2
1
1
1
2
1
1
89633300 C
PAGE NO
W IRE
21
FROM
TO
15P 1A11
15P2AIO
26PIA08
02P1All
0!»PIAI7
0lPIAl1
02PIBl1
06Pl811
0lP1811
15PlB17
26P1809
26P2A24
15PIA18
02PIA18
06PIA18
01PIA18
02PIBl8
06PIB18
01P1818
15PIB18
26P2B28
26P2825
15PIA19
02Pl A19
06PlAl9
OlPIA19
02PIB19
06PIB19
0lPIBl9
24PIB28
15PIBl9
26P2BOI
21PIB09
19P2801
15PIAl3
2SPl A08
02PlAl3
06Pl A13
OlPIAl3
06P1813
OlPIBl3
02PIBl3
15PIB13
25PIB09
26P 1 B08
25Pla08
C1PlA11
12P2B22
20P2Bl6
06PIAl1
07PI All
02PlA11
06PIBl1
01P1811
02PlB11
07PIBl1
15Pl Bll
15PIA18
01PIA18
06PIA18
01PIA18
02P1A18
06PlB18
01PlB18
02'Pl B18
01PIB18
15P1818
l5Pl A19
01PIA19
06PIA19
01Pl A19
02PIA19
06P1 B19
01PIB19
02PIB19
26P2A28
01PIBl9
15PlB19
24Pl B28
l5plA l'l
07PIA1)
19P2BOt
06PlA13
07PIA13
02PlAl)
07PIB13
02Pl B11
06P1B13
01PIB13
15Pl B13
25PIBOA
21PIB21
02PLAl4
06PlA14
06 P IA14
07PlAl4
89633300 C
lIS T
SIGNAL-NAME
A B 1
\II .L.
o
118
FR.L EV TO .LEV
89379100
89879100
89879100
89819103
89879103
89819103
89879103
89819103
89819103
89879100
89819100
89819100
89879100
89879103
89819103
89879103
89819103
89819103
89819103
89879100
89879100
89819100
89819100
89879103
89879103
89879103
89879103
89879103
89879103
89879100
89879100
89819100
89879100
89879100
89879100
89879100
89879103
89879103
89819103
89819103
89819103
89819103
89819100
89879100
89879100
89819100
2
2
2
2
1
1
2
1
1
2
1
1
2
2
1
1
2
1
"1
2
1
·04
04
010
010
010
010
010
010
Oil
011
011
011
011
012
012
012
012
012
013
013
013
013
013
014
014
014
014
014
015
015
015
015
015
015
015
02
02
02
02
02
02
03
03
03
03
03
030
030
1
2
2
I
1
2
1
1
2
2
2
2
1
1
2
1
1
2
1
1
2
2
1
1
2
1
1
2
1
1
2
2·
I
1
2
1
1
1
1
2
1
2
1
2
2
2
1
1
1
1
2
2
1
2
1
2
1
2
1
2
2
2
1
1
1
1
2
2
1
2
1
89879103
2
2
89879103
1
1
9-37
P4GF NO
28
F~OM
OlPlA14
15P 1 A14
25P2A24
20P2801
2(1)2811j
- 21SP2828
I1)P1814
06PIB14
01Pl1l4
02PIB14
02PIAllj
06Pl A15
01PIA15
1SPIAlS
2CjP282 S
20P2A14
12P2 A24
20P?A06
2ljP2A28
l5PIR15
15P2809
06P1815
01P1B15
02P1815
02P1Alo
06PlA16
OlP1A16
15P1A16
I1)P2A09
26P1Bl2
20P2S14 _
12P2R23
12p2A2.j
20P1A16
26P lAll
15 Pl8l6
15P2810
06P1816
01P1816
02Pl816
19P280l
19P?B09
18P2Ali
11P2A21
19P2821
21P2A20
lSP2821
3)P2R27
31P282l
29P282l
30P2827
9-38
W I R E
T1 .
l
I
ST
SIGNAL-NAME
02 PI A14
C1P1A14
20P? 1307
15P1A14
1l)P1814
20P2.BllS
C1PIR14
01P1814
02P1814
06P1814
06Pl A.l1)
07P141'i
02PIAll)
01PI Al 'i
20P2A}4
lISPIAlt)
15P181 IS
15P2BOCJ
20P2 A06
C1PIBll)
12P2A 24
C1PlBl'i
02 PI 81 IS
C6PIB1'i
06PIAlb
01PIA16
O?PIA16
01Pl A16
12P2821
20P2.B14
15P2. A09
1 CjP LA 16
15Pl R16
15P2 BI0
20P2A16
01P18lf,
17.p2 A21
01P1B!"6
02P1816
06P1816
11P2B07
18P2 All
I1PIAlI
16P2Bl1
17P2 A'l1
04
04
04
04
05
(1)
05
05
Olj
05
06
06 .
06
06
06
06
01
01
01
01
01
07
01
01
08
08
08
08
08
08
08
08
09
09
09
09
09
09
09
041
R+C+CC
R+W+C
RHIi+C
R "W+C+CC
R+W+C+CC
2~P2R21
R/h
R/W
36P2827
34P?821
32P282l
30P2821
31P2827
R/W
R I ..
R/W
R/W
A 8
1
W.L.
89319103
89d 19100
89819100
89819100
89819100
89819100
89819100
89819103
89819103
8981~10l
89819103
89819103
89879103
89879100
89879100
89819100
89879100
89819100
89879100
89879100
89819100
89819103
89819103
8931910.J
89819103
89819103
89879103
89819100
89819100
89879100
89879100
89819100
89879100
89819100
89819100
89819100
89819100
89819103
89879103
89879103 .
89819100
89879100
89879100
89319100
89819100
89819100
89819101
89879101
89819101
89819101
89819101
o
7/8
FR.LEV TO. LEV
1
2
1
2
2
2
1
1
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
1
2
2
2
1
1
2.
2
2
2
1
1
2
2
1
1
1
2
2
2
1
1
2
.2
1
1
1
2
2
2
1
1
2
2
2
1
1
1
1
1
1
1
2
2
2
2
2
2
1
1
2
2
2
1
1
2
2
1
1
1
2.
2
2
1
1
2
2
1
1
1
1
1
2
1
1
2
89633300 A
PAGE NO
WI R E
29
Tl
FR'1M
14P2827
32P2B27
12PIA27
l~Pl A02
13PIB02
13P lA03
IitPIB03
14PIROI
13plAOI
13P1801
14P lAO 1
14PIA06
13PIB06
l3P LA01
IitPIB07
14PIA04
13Pl A04
13PIS04
14P LB04
l1P1R30
19P2Ali
16P lA06
le}P2820
17P2815
15P lA21
20P2A04
12PlB29
19PIB02
22P2802
02PlA21
06P1A21
01PIA21
13P2Al1
21 P2 A01
32p2A20
30P2A20
34P2A20
31)P2A20
33P2A20
31P2A20
29P2A20
15P1822
02P1822
06P1822
01P1822
19P1801
22P2A24
1,)PIB22
20P2813
20P2B12
15PIA22
35P2 B27
33P2B27
11P2A21)
13Pl BO?
IlPIA04
llPIAO?
13Pl A03
13PIAOl
liPI A05
11 PI AOft
I1PIBOl
13PIB06
11 P1804
l1P180?
13Pl A07
13PIA04
I1PIAOl
It PI AOR
13PIB04
16Pl AOt.
17P1830
15P2B06
11Pl Ale}
16P281l
12PIB29
19PIBO?
C7PIA21
15PIA21
20P2 A0406PIA 21
07PIA21
02PIA21
12P2A13
29P2A20
33P2A20
31P2A20
35P2 A20
36P2A20
34P2A20
3?PZ A20
30P2A20
12P2A14
06PIR2?
C1P1822
02Pl R7.?
1')P182?
20P2B13
Q7P182;J
19PIBOt
19PIA03
01Pl A72
89633300
A
l
r
S T
SIGNAl-NA .. E
R/W
R/ ..
RDS·
RCTAPE 0
RCTAPE 0
R [TAP E 1
RCT APE 1
RDTAPE 2
RCTAPE 2
ROTAPE 3
RCTAPE 3
ROTApE 4
RCTAPE 4
RDTAPE 5
R[TAPE 5
RCTAPE 6
R CTAPE 6
R[TAPE 7
ROT APE 1
READ
RfAD
READ
READ tATA
READ GATEREADREAD.
READ.
REAO.
RfAO.
READ.
READ.
READ·
READY
REF·
REF.
REF.
REF.
REF.
REf.
REf.
REF.
R EJ EC ,REJECT.
.REJECT*
REJ ECT.
REJECT.
REJECTREJ ECTREJECT.
R EPl Y.
REPLY'.
A 8 1
MI.l.
89879101
89879101
B9819100
89879100
89879100
89879100
89379100
89d19100
89819100
89879100
89879100
89819100
89879100
89!179100
89819100
89819100
89819100
89879100
89819100
89819100
89879100
89819100
89819100
89819100
89819100
89819100
89879100
89819100
89819100
89819103
89879103
89819103
89879100
89a 19100
89819101
89819101
89819101
89819101
8987CJI01
89819101
89819101
89819100
89819103
89879103
89879103
89819100
89819100
8987CJI00
89879100
89819100
89819100
o
7/8
FR.lEV TO.LEV
2
2
1
1
2
2
1
1
2
2
1
1
2
2
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
1
1
2
2
2
2
1
1
2
2
2
2
2
1
1
1
1
'3
2
1
1
1
1
2
2
2
2
1
1
1
2
2
2
2
1
1
2
2
2
2
2
1
1
1
1
3
2
1
1
1
1
2
2
2
2
9-39
PAGE NO
30
FRUM
SEE
BELOH
22P2825·
1:}Pl.A03
02PIA22
06PIA22
01PIA22
1l)P 1A 22
14P2 A2 9
·13P2B11
> 18P 1Al1
15P2B20
16P1421
BP2B19
BP2819
I1PIB01
13P2A11
14PIA01
13P2A28
12PIB19
14P2805
08P2B10
08P2BI0
24P2B15
23P2A26
21P2828
33P2Al2
22P2A17
12P2 A05
14P2A25
llPIA06
20P2B04
2lP1A17
20P2 B04
?2P2B04
22P2B04
22P? A06
23P2828
23P2B26
2lPl82b
23P2A25
24PIA08
134>2422
12P2B31
14P2B15
13P~B2b
14P2A22
27P2A25
24P1827
24PIB21
24PIA28
24PIA28
21P780b
>18P2BOl
9-40
·vI
I
TO
20P2B 12
15PIA22
06PIA27
01PIA22
02 PIA2~
12P2R14
13P2B11
12Pl Al1
16P lA 01)
15P2R01
15P2B20
16P1A21
16Pl A21
16P1 A11
12P2818
12PIB26
12PIBIQ
11PIA31
13P2A28
14P2B06
IlP2 BO?
23P?AIQ
24P2427
21PIB27
21P2B28
20PIA21
11 PI B30
l2P2B05
12P2801)
23P2 A2Q
22PIB20
21Pl A17
24PlB08
23P2821
23P2 B2B
24P2B30
24P2 A29
23P2826
24P1401)
22P2 A2"l
11P2B14
IlP28Z9
13P2 B26
12P2831
IlP2B2R
28P2821
23PZA I?
22PIA24
Z2PIA2~
23PZB 17
27PIBIQ
1 8P 1 A11
R E
l
1ST
A B 1 0118
SIGNAL-NAME
i4 • L.
REPLY*
REPLY.
REPLY.
R EPl Y.
REPLY.
REPlY*
REO*
REQ*
REQUEST·
RESCTRBSY·
RES(TRBS't.
RESET eTR R
RESET eTR B
RESUME
RESl*
ReSl,l*
RES2*
R ES2*
RES2*
REV*
REV*
RElf
RE18*
RGPWR
RGPWR
R INO
RMOT
RMOT*
RMOT*
RNI
RNI
RNI
RNIll*
RN111*
RN112*
RNIl2*
RN121*
RNI21*
RN122*
RP
RklD fHtUNlD
RwlO*
RWLO*
RkLD*
RklJNlO*
RXA
Rl
RI
R2
R2
R3
89819100
89819100
89819103
89879103
89879103
89819100
89819100
89819100
89819100
89819100
89819100
89879100
89819100
89819100
89879100
89819100
89879100
89879100
89819100
89819104
89879104
89879100
89819100
89819100
89819100
89879100
89879100
89819100
89879100
89819100
89819100
89879100
89819100
89879100
89879100
89819100
89819100
89879100
89819100
89819100
89819100
89879100
89879100
89879100
89879100
89819100
89819100
89819100
89819100
89879100
89819100
898791f)()
REfl"EST*
fR .lEV TO .LEV
1
1
2
1
1
3
1
2
2
2
1
2
2
2
2
2
2
1
1
1
1
2
1
1
3
1
2
2
2
1
2
2
2
2
2
2
1
1
1
2
2
1
1
I
1
2
2
2
1
1
2
2
1
1
2
1
2
1
1
1
2
1
2
1
2
2
1
2
1
2
2
1
1
1
3
3
I
i
2
2
2
1
1
2
2
1
1
2
1
2
1
1
1
2
1
2
1
2
2
1
2
LEN 11TH 8"
89633300 C
PAGE NO
11
FROM
22P181<}
21P2R06
21PIA30
22PIR22
21PIA30
12PIA19
27P1831
l~Pl 805
31P2810
0.P1821
OJP1821.
I1P2A26
03P1823
04P1823
13P1805
28P2A24
18PIA02
33P2Al9
18 PI R03
33P2819
28P2825
I)Pl A2l
04P18,4
01PIR24
04PIA25
03PIA25
28PIA26
18P1802
33P2805
14P1805
28P1821
14P lA2)
18P1 A03
33P1A23
03PIA26
04PIA26
04P1A27
03PIA21
18P1801
33P2806
28P1827
14P1 A08
28Pl A31
1.P1A26
18PIA04
33P2810
01PIA28
04P1A28
04P1A30
OlPl A30
18P 1804
W t
TO
24PIA24
23P2A2A
2.3P28lR
24P1821
22P1822
05P1821
16P1805
12P1A19
21PIB31
0l)P1821
04PIB21
19P1822
04P1823
0l)P1821
05PIB2'J
18PIAO'
13Pl BOI)
28P2A24
13P1 A23
28P2825
18P1801
05P1824
05P1824
04P1824
05Pl A21)
04PIA25
18PIBO?
14P1805
28PIA26
0'5P1A21)
18Pl AO\
05P1A26
14P142\
28P1821
04PIA26
05Pl A26
05PIA21
04PIA27
14Pl A08
28P1827
18P1801
05Pl A21
18P1A04
05PIA28
14PIA2ft
28PIAJI
04P1A2R
05P1A2R
05PIA30
04Pl A30
14P1809
89633300 A
R E
lIS T
SIGNAl-N'ME
R3
R3
R4
R4
R4
S WRITE.
S WRITE.
S WRITE*
S lIfR I TE.
S WRITE.
5 WRITE*
SAMPLE thEt
SAO
SAO
SAO
SAO
SAO
SAO
SAl
SAl
SAL
SAl
SAL
SAl
SAI0
SAI0
SAIO
SA10
SAIO
SA10
SAIl
SAIl
SAil
SAil
SAIl
SAIl
SA12
SA12
SA12
SA12
SA12
SAl2
SAl3
S~13
SA13
SA1l
SA13
SA13
SA14
SA14
SA14
A a 1
"'.L.
89879100
89879100
89879100
89879100
89679100
89879100
89879100
89879100
89:1 79100
89879102
89879102
89879100
89819102
89879102
89a79100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879102
8987910~
89879102
89879102
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879102
89879102
89879102
898'79102
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89819100
89819102
89879102
89819102
89879102
89879100
o
7/R
FR .LEV TO.LEV
1
1
1
1
2
2
2
1
1
2
1
1
1
2
2
2
1
1
1
1
2
2
2
1
2
1
2
1
1
2
2
2
1
1
1
2
2
1
1
1
2
2
2
2
1
1
1
2
2
1
1
1
1
1
.1
2
2
2
1
1
1
1
1
1
1
2
2
1
1
1
1
2
2
1
1
1
1
2
1
1
2
2
2
1
1
1
1
1
1
1
1
2
2
2
2
I
1
1
1
1
1
1
9-41
PAGF NO
32
FinN
33P2809
28P lA30
1lt-P1809
27P2AOl
14P1825
18PIA01
31P2A12
03PIA31
04P1 A31
0lt-P1825
03P 1825
18P1808
33PIB02
13PIA05
28Pl B01
28P1A06
13P1823
18PIA08
33P1AIO
03PIB26
04P1826
O·JP 182 7
04P1B27
18PIA09
31P lAll
28PIB09
13PIB08
18PIA09
13PIA26
l8PIB09
31P1812
04Pl828
03P 1828
03PlB30
OltP1830
18i»1806
33PIB22
28PIA21
13P lAO 9
28PIBl3
13PIB25
18P1A06
33P2803
04P1B31
03PlB31
04PIA23
03P1A23
18PIAOl
33P2A1O
29i»1830
llt-PIAOS
9-42
WI R
T3
28Pl A30
l8P1B04
05P1430
18Pl AOI
05P143l
14Pl82'i
27P2 AOI
04Pl A31
05Pl A31
OI)P182r;
.04PU12'i
11PIAor;
28P1801
05PIB2'i
18Pl BOR
18P1AOR
OSPla2#)
13P1823
28P1A06
04P1826
OSP1826
04P1B27
OSPIA27
13PIROR
28PIB09
18Pl A09
05PlB21
18P1809
05P1828
13PIA26
28P1 A09
05P182R
04PlB2R
04PIB30
05Pl830
13PlA09
28P1A21
lAPl B06
05P1830
18 PI A06
05P18.3t
13P182')
2RP1B23
OSPl831
04PIB3t
05P1 A2l
04PIA2'4
IltPl AO,)
2AP1830
18P1A07
05PIA2l
f
lIS T
SIGNAl-NAfiE
SA14
SA14
SA14
SA15
SA15
SA15
SA15
SA15
SA15
SA2
SA2
SA2
SA2
SA2
SA2
SA3
SA3
SAl
SA3
SA3
SA3
SA4
SA4
SA4
SA4
SA4
SA4
SA5
SA5
SA5
SAS
SAS
SA5
SA6
SA6
SA6
SA6
SA6
SA6
SA7
SA7
SAl
SA7
SAl
SAl
SA8
SA8
SA8
SA8
SA8
SA8
A B 1
W.l.
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879102
89879102
89879.102
89879102
89879100
89879100
89879100
89879100
89879100
89879100
89d79l00
89879100
89879102
89379102
89879102
89879102
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89819100
89879102
89879102
89879102
89819102
89819100
89:3 79.100
89879100
89879100
89879100
89819100
89819100
89879100
89879102
89819102
89879102
89819102
89879100
89819100
89879100
89879100
o
7/8
fR.lEV TO.lEV
1
2
2
2
2
1
1
1
2
2
1
I
1
2
2
2
2
1
1
1
1
1
2
1
1
2
2
2
2
1
1
2
1
1
2
1
1
2
2
2
2
1
1
2
1
2
1
1
1
2
2
1
2
2
2
2
1
1
1
1
I
1
1
1
2
2
2
2
I
I
1
1
1
1
1
1
2
2
2
2
1
I
1
1
1
I
1
1
2
2
2
2
1
1
1
1
1
1
1
1
2
2
89633300 A
PAGE NJ
W I
33
R E
TO
FROM
2RP1829
14PIA22
18PUW7
33P2A09
03PIA24
04PtA?4
16P 1 A04
t Z!-Z! "~I!I
19P1821
19P?A01
19PIA23
19PIA77
L6P1801
l~a~fSZ8
?BPIB03
l3PIA12
27PIAOl
"1'1PIB04
IB P2 828
04PIA03
03PIA03
0~P180L
04PlijOl
IBP2A27
27PlA03
".:\lPlFW 1
Z8P1AOI
13PlA10
14P 1 A10
28P18Z0
?7P lRl8
33PIA22
l>~PZA30
04PI806
t)3°1B06
04PIA05
03PIA05
IA P21H 1
27 Pl ALA
33PIA16
ZAPlAL5
14PIA12
ZAPiA23
14PIB15
27PIA;JU
3 jP 2 1302
lQPZA28
OjPIA04
04PIA04
0:3PIB09
04P1R09
lAPIB07
05PIA24
14Pl A2')
~HPIB29
04PIA~4
0") Pl A241?P2B?'l
B5el
EH~
15P2A?4
15P2824
15P2A2')
15P2B2'i
12P2A27
B!i I!~ eat !Ii
27Pll\01
15PIAOl
11PlAl')
2BPIBO":\
13PIA12
05 PI A0':\
04PIAOi
04Pl801
05PIBOI
13PIA10
13 PI Al 0
2RPIAOl
27PIA03
05 P1 Rot
o 5P 1 R 06
27PIBlR
14PIAlO
2RPIB20
14PIAI0
05Plf10ft
04PIB06
05 PI AO'i
C4Pl Ao'':i
14 D 1.'\P
14Pl AP
2 RP 1 A1 'i
2 7Pl A1 A
05 Pi AOI)
27PIA2 0
05PIA14
14PlR15
2SPIA2i
l'tPlI-H I.)
04PIA04
05PIA04
04P180Q
05PIROQ
89633300
E
l
I
S T
A 13
SIGNAL-NAt-It::
w .L •
SAg
SA9
S /l9
SA9
SA9
SAg
SCF(O( SCF[M
5 CEf '! II~ t I ~i I
5COSEO
SCQ Sf 1
scnSE2
SeQ SE3
S(ROO{S(RIM
89879100
8987910C
89379100
89879100
8937-1102
5f~ft~ff!1 ~
sao
SOO
SOO
SOO
seQ
SOD
SOD
501
SOl
SOL
SCI
501
SOL
501
SOLO
S CIO
5010
SOLO
SOLO
SOlC
SOLO
SCII
sell
sell
SCI 1
SI1Il
SCll
SOIl
So 1 Z
5012
se12
S012
SrI2
S012
SCl2
5C13
S013
t
1 0 7/8
F~
.L EV
TO.LEV
8Cjj 19100
?
2
1
1
1
2
1
a:2 f~ :l'i i Ii a
2
2 Removed by
89'179100
89379100
3937'1100
8:J819100
t!9879100
?
1
2
I
1
2
1
2
1
1
8~-:Sf!:llfjl~
~
~
89879100
89379100
898791.tJO
89319100
8987'1100
398791JZ
69879102
8987<1102
398791J2
898N100
B9179100
89B7JI00
89d7'1100
89819100
89879100
09<379100
89i79100
89379100
89879100
8987HJ2
8 t H791Ji
898 -7910 2.
2
'2
1
1
'3
2
2
I
I
3
1
1
I
1
3
I
1
2
2
2
2
I
I
3
1
1
1
1
3
1
1
2
Z
2
2
1
1
89~19102
8J879102
8 18P2A12
14P1A25
llPIA25
13PiA27
14PIA27
19P1A04
lAP1805
14P2B02
16P2AOb
16P2A04
1bP2A02
16P2AO 1
19P2B29
19P2A14
27PlAOA
05P 1 AOl
BPI Bll
28PIB07
13Pl Alb
28Pl BOft
27P1AI0
05PIA02
13P1Alb
04PIA02
05PIA02
04Pl803
05P1803
13P1 APi
27PIA12
05P1803
13 PI APi
28PIB05
14Pl Bll
28P1 B1'+
27PIB14
05P1804
14PlfH2
05PIB04
04Pl B04
04PIB05
05PIB05
14P1810
27P1816
05Pl B05
14PIB10
28PIB 1 R
26Pl822
26P1 AU
15P2A07
l1Pl A2'5
16P2BIO
13P1A25
12P2Bll
l2P2A II
13PIA27
18Pl B05
15P2A 01
11P2B07
15P2A26
15P2B26
l5P2A27
15P2B21
16P1A2'5
16Pl A30
506
S06
S06
506
S06
507
S07
SOl
507
507
507
S07
508
SOB
S08
S08
508
508
S08
509
509
S09
S09
S09
509
509
SE
SE
SE.U.PRT.
SECTOR GHe
SEe TOR GAlE
SElAO
SEL AO
SELAI
SEtAl
SElD.UTP I 10
SElD.UTPl.l0
SEDP.
SEDsel*
SED SC2*
SEOSC3.
SEOSC4*
SET ALARM*
SET erR SEE
19P2B15
17P1A12
SECTOR GillE
>
89633300 C
S05
505
505
505
S06
506
AB 1
lotI.L.
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879102
89879102
89879102
89819102
89879100
89879100
89879100
89879100
89879100
89879100
89a 79100
89819100
89879100
89819100
89879102
89879102
89879102
89879102
89879100
89879100
89879100
89879100
E9379100
89879100
89819100
89879100
89879100
89819100
89819100
89879100
89879100
89819100
89879100
89879100
89819100
89879100
89819100
89819100
89819100
89819100
89819100
89819100
o
7/8
FR .LEV TO.LEV
2
2
1
1
1
1
2
2
3
1
2
1
2
3
2
2
1
1
1
1
2
2
3
2
1
1
2
3
2
2
1
1
1
2
2
2
1
1
2
2
1
1
2
1
1
1
2
2
1
1
1
1
2
2
3
1
1
1
1
3
2
2
1
1
1
1
2
2
.3
1
1
1
1
3
2
2
1
1
1
2
2
2
1
1
2
2
1
1
2
1
1
1
1
1
1
1
2
1
1
2
3
3
LENGTH g"
9-45
I
PAGE NO
36
fROM
17PIA12
18PIAU~
I
25P1B22
08PIA20
08P1A20
23P2A14
21P2A13
20P 280 1
21P2813
26P2811
2&P 2826
22P1806
18P2816
18P2B05
17P1A31
24P1819
22P2A09
22P2A30
21PIA01
22P1824
18P2A 18
18P2819
22P2B26
25P2A08
24P2A12
33P1B13
28PIA12
12P2A18
21P1829
16P lA03
31P2AIO
04P1814
03PIB14
04P1A15
03P 1 A15
16PIA01
33P2B20
12PIA20
21P2A28
12PIA14
21P2B18
16PIAI0
33P2816
03P1A13
04PIA13
03PIB12
04PIB12
33P2811
16P1B03
12PIB22
21P2ALQ
9. . 46
W I
TO
16P1 A18
15P2804
22P2801)
11 P2 BID
14P2B1A
25P1 A22
23P2 B22
21P2A13
22P2A16
25P2826
25P2805
24P2 Bll
17P2A22
17P 1 A31
16P1 BOq
25PIA11
26P1 A17
21P1804
20P1AI0
20P1824
16P1A1'4
16PIB14
24P2 A12
26P2A08
25P2 AOA
28 PI A12
2 2P lA25
0l)PIB14
16P1 AO~
12P2A1A
21P1829
05Pl B14
04PIB14
05Pl A15
04PIA15
12P1420
21 P2 A2A
05PIA15
16Pl AOI
05Pl Al1
16Pl A10
12PIA14
21P2BIA
04PIAl1
05 PI A11
04P1Bl?
0I)PIB1?
21P2A19
12P1B2;>
05P1 Bl?
16Pl B01
R E
l
I
S T
S tGNAL-NAr-E
SET NEEO*
SET.ADO~.ER
SFL
SFM*
SFM*
SGL
SG1*
SG1*
SJ-!ADR
SHAL
SHAM
SHI
SHIFT CLeCK
StH FT-BUUFI
S H I FT-BUU F1
SIL
S 1M
SKT
SLK*
5LS
SMPXO
SMPX1
SO
SO
SO
SF8M*
SPBM*
5P 1*
SPI*
SPI*
S PI*
SPI*
SPI*
Sf; 0*
S~O*
SRO*
Sf/O*
SRO*
SRO*
SPSM*
SRSM*
Sf/SM*
SRSM*
SRSM*
SJ.lSM*
S $*
SS*
SS*
ss*
SS*
SS*
A B 1
W.l.
89819100
89879100
89819100
89819104
89819104
89879100
89819100
89879100
89879100
89819100
89879100
89879100
89819100
89879100
89819100
89819100
89879100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89879100
89819100
89319100
89819100
89819100
89879100
89879100
89819102
89879102
89819102
89819102
89879100
89819100
89819100
89819100
89819100
89879100
89819100
89819100
89919102
89819102
89879102
89819102
89819100
89819100
89819100
89819100
o
7/8
FR.LEV TO.LEV
1
2
1
1
2
1
1
1
2
1
1
2
1
2
2
1
2
1
1
1
1
1
1
2
1
1
2
:>
2
2
2
2
2
1
1
2
2
2
2
2
1
1
1
1
2
2
2
1
1
1
1
2
1
2
1
1
1
2
2
2
2
1
1
1
2
1
2
1
1
2
2
1
2
2
1
2
1
1
1
1
1
1
1
1
2
2
2
2
1
1
1
1
1
1
1
1
2
2
89633300 H
PAGE NO
17
FROM
W (
TO
2.1P 1A19
14P2B13
14P2B31
14P2816
21PtA16
14PIA21
13PIB22
13P2804
13P2AIO
14P2801
29P2A07
30P2A07
34P2 A07
32P2A07
35P2A07
33P2A01
llP2A07
29P2A07
13P2A01
14PtA31
12PIA13
04Pl Bll
03P1817
21P28?4
12PIAOl
33P2B18
19PIA09
21P1811
28P2A20
28P2828
26P2B09
25P2809
18P2ALl
18P2A16
2&Pl AZb
25PIA26
25P1825
26PIB25
16P1A20
15PLA09
21P2B28
25PIB02
26P1802
16 P 1A21
25P1A04
26PL A04
25P1B04
26PIB04
17P1828
16PtA 14
19P2A15
21P1BPi
12P1B07
12PIA21
12PIB21
20PlA31
13Pl822
12P2 A09
12P2 Bil
12P2BOQ
12P2 AOt
27P2 A12
31P2A07
35P2 A07
3.3P2A01
36P2A07
34P2A07
32P2A07
30P2A01
12P2 A15
13P2AOl
11P2 A05
05Pl Bl1
04PIB11
19P1 A09
C5P1817
27P2824
12Pl A01
20PIA23
21P280A
27P2A11
25P2809
24P2AIA
11Pl AO~
11PIBOl
2SP1426
24P2A17
24P2A13
25PIB2'i
15P2A2\
01PIA09
15Pl A09
21P2Al'i
21P2B16
15P2819
21P2817
21P2A17
21P2B20
21P2A21
16 PI A14
15P2B21
16PIA31
89633300 A
R E
lIS T
A 8
SIGNAL-NA~E
WI . l .
SS1
STO.P'R.ERR
STOP 01S1.
STOP*
STOPCS.
STRBUF*
STRBUf*
STRCC
SnHNT
STRMF
STROBESTROBE.
STROBE·
STROBE.
STROBESTPOBE.
STROBE.
STROBE.
STRUS
SlRVS
STWCRC*
SVIO*
SVIO*
SVIO*
SVIO*
SVIO·
SVIO*
SWEEP.
SXA.
5XP*
51
SI
SII
S15
52
S2
S3
S3
T.E.D AlHOl
T.P.
T.P.
TAOl
TADM
TAS EXT.
TAll
TAU4
TA2l
TA2M
TOI
TDI
TOl*
89819100
89879100
89819100
89819100
89879100
89879100
89819100
89819100
89819100
89819100
89879100
89879101
89819101
89819101
89879101
89879101
89879101
89819101
89819100
89879100
89819100
89879102
89819102
89819100
89819100·
89819100
89819100
89879100
89819100
89879100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89879100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89879100
1
o
118
FR.lEV TO.LEV
2
1
2
1
1
1
1
1
1
1
2
2
2
I
2
2
2
2
1
1
1
1
2
1
1
2
1
2
2
1
1
1
2
2
2
1
2
2
2
1
1
2
2
2
1
2
2
1
1
1
2
1
1
2
2
2
1
2
2
2
2
1
1
1
1
2
1
1
1
1
2
2
1
1
1
2
2
2
1
2
2
.2
1
1
2
2
2
1
2
2
1
1
1
2
2
2
2
1
1
2
1
1
PAGE
"iA
Ni)
FROM
It-PIA20
18P2BI0
I1PIA20
19P2A16
19P2B14
17 P2 A2 3
lAP2602
17P2Bll
19P2A23
lAP 2AO 3
21PZA24
13P28Z4
13P]Blb
12P2B29
14P2A19
06PIA09
OlPIA09
02PIA09
14PIA03
13PIBO 3
14P2A28
14P2811
14P2A24
11P2Bli
14P2A23
24P2A09
24P2806
HaPl804
lZPlA08
l4PIB02
14P2 A09
14P2R09
14P2Bll
16P2A14
16P 21\09
16P2 A08
1bP2A07
21P2A31
27 P2 A30
23P1406
29 P 2A16
l~PIAZ7
lRP2A19
17PIR19
19P2AOl
Z4P2426
19P2R22
11PZR27
09P2A07
10P2A07
13P?A09
9-48
W I
R E
T1
15P2829
17PIA20·
16PIA20
16PIA26
18P2A02
16 PI A17
17PZA23
16PIAll
IRPZ803
11P2B 11
ZOPl AOa
I? P2 A30
12PZBZ9
OR P2 82':\
13PZIH6
01PIA09
02Pl A09
06P1A09
13PIBOl
I.? PI 807
I1P7.828
lZPl Bl1
13P2 Alq
t4P1806
13P2819
22Pl A14
2ZPIA16
·1';P2 AQ6
IlPIA27
12PIAOl
12P2 A03
13P2B27
13PZ A27
l5P2BU
15P2A 1\
15P2 A04
15P2BOR
2CPIBOI
Z·3PIAOl
21P2B15
ZOP28Z7
11PIA27
17PIB19
16PIAO~
1 AP2 Ai q
23PIA 14
I1P2 A2R
1 OP2 407
OAPIAOl
09PZA01
12PIAl~
L I S T
SIGNAL-NAME
T02
T02
T02
T02*
A B 1
W.l.
89879100
8~8 79100
89879100
89879100
lD3
8~819100
T03
T03
T04
TC4
T04
TMSW.
TMI
T"'3
89819100
89819100
89879100
89819100
89tJ 79100
89819100
89879100
89819100
89d 79100
89879100
89819103
89819103
89819103
TM3
T"'3
·TP
TP
TP
TRANS*
TfCANS*
TT READY
TTBUSY*
TTDENSTAT*
T10Nli NE*
TTREAOY*
T3
T4
ULT.S~C.PRO
UPPER
UPP XI*
USA
lJ~O
USl
US1*
US2*
US.3*
U54*
VCC
V((Z
VIO*
'ISS
W.CKWO*
WtC
WtC
W+C
WA
WA-ADR
",eLK
WCLK
weLK
~OS SHIfTED
89~19100
89819100
8':J819100
89379100
89879100
89879104
89879100
89819100
89879100
89,;) 79100
89819100
89879100
89879100
89819100
89879100
89819100
89879100
89879100
89879100
89879104
89819100
89879100
89819100
89879100
89,179100
8C;a 79100
89879100
89879100
89819100
89879100
89879100
89879100
89879100
o
7/8
FR.lEV TO.LEV
1
1
2
1
1
1
2
2
7.
1
1
Z
2
1
1
1
1
?
1
Z
1
1
1
2
1
1
1
2
2
2
1
1
Z
2.
1
1
1
1
Z
1
Z
1
1
1
1
1
1
1
1
1
Z
1
2
1
Z
Z
2
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
Z
1
1
1
Z
1
2
1
1
1
Z
2
1
1
1
2
Z
89633300 A
PAGE NO
W I R F
39
FROM
TO
LIS T
SIGNAL-NA~E
21PIA30
24PLB12
311>2806
02PIA20
OoPI A20
0lPIA20
IlP2A25
21P2B30
21P2B30
24PIB12
22 PI B21)
27PIA30
Q6PIA20
07PIA20
02P lA20
07Pl A20
15plA20
12P2A25
WE*
wE*
WE*
WEI*
wEZ*
WEZ*
WEZ*
wEZ*
WEZ*
21P2B30
19P1AO?
tJEZ*
25P2B29
2&P2B29
26P2B29
08P lA21
12PIR24
14P2825
10P2816
24P2803
12P2804
14P2824
2ftPIR04
24PIB29
14PIA30
13P2A05
t4P2A17
19P2B13
13PlA06
13P2"A06
17 PI B21
18P2A21
17P2B23
15PIB21
20P2B06
12PIB30
19P2B31
22P 2BO 1
OlP1821
06PI821
01PIR21
21PIAll
21P1All
13P lA08
13PIAl2
14PIB21
14PIA11
14PIB16
14PIA13
14PIA16
14Pl A24
13PIB27
13PIAll
21P2A07
21PIA13
2 OP2 All)
lZPIB24
10P2816
12PI82ft
I1P2BOl
23P2 B21
11PIAI0
12P2B06
23PIAI3
23PIBI2
13P2AOR
08Pt BIA
13P2A05
17P2B2A
IlPIBIO
I1P2B19
loPlBlo
16PIBOA
16P2B22
l2PIB30
19P2831
07PIB21
15P1821
20P2B06
06PIB21
07P18ll
02PIB21
24Pl All
2lP2AIO
11PIA22
IlPl A21
IlPIAl6
I1Pl8l7
11 PI B21
IlPIB20
IlP182t;
I1P1824
IlPIBZ6
IlPIAZI)
WEZL*
WElM*
WEZM*
WFM
WFM/TM*
WFH/TM*
WFM/TM*
WM
WHOT
WHOT*
89633300 t
WP
WO
WRENABlE
wRECUEST*
WRECUE 51*
WRITE
WRITE CLOCK
WRITE CLOCK
WRITE [AT~*
WRITE ENABl
WRITE GATE*
WRITE*
WRITE*
WRITE·
WRITE*
WR( TE*
WRITE.
WRITE·
WRI TE*
WPQ
WPC
WRTAPE 0
WRT 'PE 1
WRT~PE 10
WRTAPE 11
WRT'PE 12
WRTAPE 13
WflTAP E 14
WflTAPE 15
WRTAPE 2
WflT~pE 3
A B 1 01/8
W.l.
89879100
89879100
89819100
89879103
89819103
89879103
89319100
. 89819100
89819100
89819100
89819100
89879100
89819100
89819104
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89879100
89819100
89819100
89819100
·89819100
89819100
89819100
89879100
89879100
89879100
89879103
89819103
89819103
89879100
89819100
8Q819100
89879100
89879100
FR.LEV TO.lEV
2
1
1
2
1
1
2
2
2
1
1
2
1
1
2
2
3
3
1
1
1
1
2
1
1
2
2
1
1
1
2
I
1
I
2
2
1
2
2
1
1
2
1
1
2
1
1
1
2
1
1
1
1
2
8~819100
2
2
1
1
1
2
2
2
Z
2
2
2
2
2
1
1
1
2
2
2
2
2
89819100
89819100
89879100
89879100
89819100
89819100
2
2
2
2
2
2
2
2
2
2
2
2
LENGTH 1011
LENGTH 1111
LENGTH 7 11
LENGTH 1411
1
2
2
1
2
2
1
1
2
1
1
2
9-49
PAGf
"'4)
40
FROM.
IlP1816
13P1A14
11PIA17
IlP lA24
14PIB08
14PIB21
2JPIBIO
24PIAl2
23P1B15
24P2813
22P2A05
2l)PIA18
21)P2A17
26P2A17
25P1A15
26PIA15
76P2A19
26P2B18
26PIA09
l'jPl A09
24Pl831
24P~A20
24P1R22
23P1826
24P18'22
2]Pl~12
Z,Pl A20
2l)P1Bl1
21PIA30
26P2A09
19P1805
17P2A25
22PIBO]
2)P2A10
21PIB01
22P280 1
2lP lA22
28PlA28
34P2A30
32P2A30
lOP2A30
29P'A30
31P2A30
35P2A30
33P2A30
35P2B29
3,lP2829
31P2829
29P2829
30P2R29
34P2829
9-50
vi
t
RE
TO
11P1A20
11PlA19
II PI Alft
11PIA2l
I1P1B2l
11 P182?
22P2A15
22PIB28
22PlAOl
23P2AOJ
25Pl A18
26PIAIA
21PIAOl
21 PI AO'
l~PIA 10
23 P IB09
21P.1 AO'
21P180'
25PIA09
2/tP1A09
25P2A2l)
26P2 A2l)
23PIB26
?2P21H 1
21 PI AOA
2ljP1AZO
26PIA20
. 26PIB11
25P1811
22P287.1 .
I1P2AOl
16P181ft
24PI811
24P2BOl
22P2R01
24P2 BOI
21P28 l'J
29P2A30
35Pl A30
33P2AJO
31P2A30
30P2A30
32P2A]O
36P2 A30
3/tP2A30
36P2829
34P2B29
.32P282Q
30P2829
31 P2 87.CJ
]l)P2B29
liS T
SIGf'Al-NAME
wrHAPE
WRTAP E
"RTAPE
WRTAPE
WRTAPE
WRTAPE
WXl
WXLI.
WXM
W9A*
XfZ
XEl
XGOl
XGOM
XlCK
X,,-CK
XSEl7fo1
XSOM
XTAOO
XlADO
XTAUGl
XTAUGM
X15
X15
X15
YCK
yCK
YTAUG
YTAUG
11TSH
010
011
02*
0303·
03*
IE
1KO.
11(0*
lKO*·
11(0*
11(0·
IKO*
lKO*
lKO*
lK 1*
lKl*
lK1*
lKl*
1 Kl*
11(1*
'+
5
6
7
8
9
A Ii 1
W.l.
89879100
89879100
89879100
89879100
89819100
89879100
89879100
89879100
89879100
89819l()0
89879100
89879100
89379100
89879100
89819100
89819100
89819100
89879100
89819100
89379100
89879100
89819100
89879100
898191()0
89319100
89879100
89879100
89879100
89879100
89819100
89379100
89819100
89879100
89879100
89819100
89879100
89819100
89819100
89819101
891379101
89819101
89879101
89819101
89879101
89879101
89819101
89879101
89819101
89:) 7910 1
89819101
89819101
o
118
FR .lEV TO.lEV
2
2
2
2
2
2
2
2
1
2
2
1
1
1
2
1
2
2
2
1
1
2
1
2
2
2
1
2
2
2
2
2
2
2
2
1
2
2
1
1
1
2
1
2
2
2
1
1
2
1
2
2
2
I
1
1
2
1
2
2
t
2
1
1
2
2
2
2
2
2
1
1
1
2
2
1
I
1
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
2
2
89633300 A
PAGE I\J'J
41
W I
TO
FROM
32P2R29
78i»7R30
7RP2A26
3lP;?B24
JOP2R24
34P2B24
3 ')P 2 i3? 4 .
31P 2B24
31P2B24
29P2R7.4
3SP2A24
33P2A?4
':\lP2A24
29P2A24
3QP2 A24
14P2A24
32P2A24
28P2A77
17P IB31
11P2B05
llP1A05
13P2A12
27P2 A06
2'lp2B08
21PlAl2
OlPIAll
04PIA21
72P2AOl
21PIA12
26PlA29
31P2A13
2l P 2B26
12PlA29
1.3PlA24
13P2A26
t4 P 24l1
131>l824
33P2B2Q
19P1B 29
2Qp2Bl4
~'lP2B24
~lP2B24
35P2A24
36P2A24
34PZ624
32P2B24
3CP2Bl4
36P2 A24i4P2 A24
32P2A 24
30P2A24
11 P7. A24
35PlA7.4
33P2 A24
19P2 A2ft.
16P1AI7.
11 P1 BOS
12P1R1R
11PIA30
26P2A2Q
22P2A02
OSPIA2l
04Pl All
OSPIA21
71PIA17
20P1804
23P7f\CR
27P2 AOt:.
27P2B]O
tlP2BOC;
08P2421
1 t PI A2A
13 P 2A26
lZP1430
89633300
A
R F
l
1 S T
SIGNAL-NAME
lKl*
1K1*
lK2*
1 K2*
1K2*
1K2*
11<2*
lK2*
1K2*
11<2*
1K3*
lK3*
11<3*
lK3*
11<3*
1 K3*
lK3*
1 K3*
16RITS.Oll
1600
1600
2FWC
32Kw
.32KW
32KW
32KW
32KW
32KW·
32KW
32KW
32KW
32M
4MHl
1t;IPS
9T
'IT
9T·
A 8 1 0 7/8
w.l.
89879101
89879100
t398 7910 0
89819101
eC;819101
8'J3 7910 1
89879101
8987Q101
8r~8 79101
89879101
89879101
89879101
89879101
89819101
89879101
39879101
891379101
89879100
89819100
89879100
89879100
89319100
89619100
89879100
8<;819100
89879102
89879102
89819100
89879100
89379100
89d 19100
89879100
893191IJ 0
89379100
89879100
89d 19100
89319100
FR.LEV TO.LEV
2
1
2
2
2
2
1
1
1
1
1
1
1
1
2
2
2
2
2
2
1
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
2
2
1
2
2
2
1
2
2
2
1
2
3
1
1
1
1
1
2
2
1
1
3
1
1
1
1
1
2
Z
2
2
1
1
2
2
9-51/9-52
TABLE 9-4.b
89633300 A
WIRE LIST AB 107/AB 108 BACKPLANE
(in card slot order)
9-53/9-54
PAGE NO
W I
1
TI)
FROM
OlPlAOl
OlPIA02
OlPIA03
01Pl A04
OlPIA05
01PIAOb
01 PI AO 1
0IP1AOC;
OIPl All
01P1A12
0lPIA13
01PLA14
01PIA15
01PIA16
01PIA11
01PlA18
01PIA19
01PIA20
01PIA21
0lPIA22
01PlA2]
OlPIBOl
01PIB02
0 1P.l803
01PlB04
OlP1805
01PIB06
01PIB01
OlPIB09
01PIBI0
01PIB12
OlP11H3
01PIAl4
01PIB15
01PIB16
01PIS11
01PIBl8
01P1819
01Pl821
01PIR22
01PIB23
01PIB23
02PIAOl
02PIAOl
02Pl A02
02PIA02
02PIA03
02PIA03
OlPIA04
02PIA04
OlPl A05
02PIAOl
02PIAO~
02PIAO~
02 PI A04
02PIAO'i
02PIA06
02 PI A07
OZPIAOQ
02PIAll
OZPIAL2
OlPIA11
02P1A14
02PIA1,)
OlP1A16
OZPl All
02P1A1R
02PIA19
02 Pl A20
02PIA21
02PIA2?
02P1 A2l
02PIBOl
02PIBO?
02PIBOl
02PIB04
02Pl BOI)
02P1B06
02PIB01
02P180Q
02PIBIO
02PIRIl
02PIBll
02PiB14
02PIB11)
02PIBIt.
02PIB17
02Pls1A
02PIBIQ
02P1821
OlP1822
02PIB21
OlPIA09
01 Pl AOI
C6PIAOl
06P1AOl
01PIA01
OlPIAOl
06PIA03
OlPIA04
06PIA04
OlPIAO'i
89633300 C
R E
l
1ST
S IGNAl-NAP-IE
OAS*
OAb*
OAO*
CA12*
nAll*
GA3*
OA4*
TP
OAI5.
CO
02
04
06
08
010
012
014
wEI*
READ·
REPLY.
PPTM.
OA1·
OA2*
OA7*
OA8*
OA9*
OAI0*
CHI*
O~13*
OAI4*
01
03
05
01
09
011
C13
(a5
WRITE.
REJ ECT*
Me·
Me.
OA5*
OA5*
CA6*
OA6*
OAO*
OAO*
GAI2*
OAI2*
GAll.
AB 1 o
W. L.
89879103
89879103
89819103
89879103
89819103
89879103
89879103
89819103
89819103
89819103
89879103
89819103
89879103
89819103
89879103
89319103
89819103
89819103
89819103
89819103
89819103
89819103
89819103
89819103
89819103
89819103
89879103
89819103
89819103
89819103
89819103
89819103
S9819103
8(j819103
89819103
89819103
89819103
89819103
89819103
89879103
89879103
89819100
89819103
89819103
89819103
89819103
89819103
89819103
89819103
89819103
89819103
7/8
FR. lEV TO.LEV
1
1
1
1
1
1
1
1
I
1
1
I
1
1
1
1
1
1
1
I
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
2
2
I
1
2
1
2
1
1
1
1
1
1
1
1
1
1
1
1
I
1
1
1
1
1
1
1
I
1
1
1
1
1
1
.1
1
1
I
1
1
1
1
1
1
1
1
1
1
1
2
1
2
2
1
1
2
1
2
1
9-55
PAGF
Nt)
l
FROM
02P 1 A05
02Pl A06
02PIA06
02P1A01
OlPIA07
02PlA09
02PlA09
02PlAlI
02PIAli
02Pl A12
OlPIA12
OlP1Al.~
02Pl A13
OlPIA14
02P1A14
02PIA15
02PIA15
02PIA16
OlPI A16
OlP lAl 7
02Pl Al 7
02PIA18
02PIA18
02P1A19
02P-) A19
02PIA20
02PIA20
02P lA? 1
02PIA21
02PIA22
02P IA22
02PlA23
02PIA23
02PI801
07.P1801
02P1B02
02P1802
02P1803
02P1803
02P1804
02Pt804
02P1805
02P1805
02P1806
OlP 1806
02P1807
.·02PIB01
02P1809
02P1809
02P1810
02PIBI0
9-56
"'
I R E
TO
C6PlAOl)
OlPlAOh
06PIACh
06PIAOI
01 PI A07
06PIAOQ
01PIA09
01Pl All
C6P1All
0IPIAl?
06Pl AI?
C6PIA13
OlPIAll
01PIA14
06PIA14
06PIA1'»
OlPIAll)
06PIA16
01 PI A16
01PIA17
06Pl A17
01 PI A lA
06PIAlII
06Pl A19
01PIAIQ
06P1A20
OIPI A20
06P lA 21
QIPIA2)
01P1A2'C6PIA2?
06Pl A21
01 PI A2l
01PIAOt
06PIAOI
O)PIBO'06PIB02
06PIBOl
01PI801
OlPIB04
06Pl BOlt
OlP1801)
06P1805
C6PIB06
OlPIB06
ot P1 B01
06PIBC7
01P1809
06Pl BOCJ
06PIB1O
OlPIBIO
l
( S T
S IGNAl.-f'179103
89879103
8<;879103
89879103
89879103
89;)79101
89979103
8~879103
8<;879103
89879103
89879103
89379103
89879103
8<;879101
89379103
89879103
8981910~
89819103
89819103
89879103
8987910.3
89879103
89879103
89879103
89879103
1
o 7/8
FR .lEV TO.l EV
2
1
2
2
1
2
I
1
2
2
1
2
2
I
2
1
I
1
1
2
'l
2
1
1
2
2
1
2
2
1
1
2
2
1
2
2
1
I
2
1
2
2
1
2
1
2
1
1
2
1
I
2
1
1
2
1
2
2
1
2
2
1
2
1
2
1
1
2
2
1
1
2
1
2
'-
2
1
1
2
1
1
2
1
2
1
89a79~03
2
89879103
89879103
891319103
89879103
8987910.:J
89879103
89879103
89819103
2
2
1
1
1
2
1
1
2
1
2
2
.1
2
2
1
89633300 A
:>.\G E 'IlJ
W I
3
FROM
02PL812
02P1B12
02PIB13
02P1813
02PIB14
02PL814
02P 1 B 15
02PIB15
02PIB16
02P1B16
02P1817
02PIB11
02PIB18
02PIB18
02P1B19
OlPlfH9
02P1821
a2P 1B21
02PIBl2
02PlI:~2l
02PIB23
02P1823
03PIAOI
03PIA02
0)PlA03
O:lPIA04
03PIA05
03Pl A06
03PIA07
OlPl AQ9
0~PIA09
03PIA11
O~PIAI3
03PIA15
O_~P 1 Al 7
03PIA18
OlPIA20
03P1A21
03PIA23
O~PIA24
03PIA25
03PIA26
03PIA27
03 PI A28
03PIA30
O'~PIA31
OlPIBOl
C3PIB02
03PIB03
01PIR04
03PIB05
TO
01P1B17
06PIB12
06P1811
01P1B13
ObP1B14
01PIB14
C6PIB15
01PIB15
01PIB1fJ
06P1Bln
01P1811
06PIB11
ObPIBIA
01PIB18
C6P1819
01P1B19
QbP1821
OlPlall
OlP1 B22
ObPl B2')
06P1B2-4
01PIB21
04Pl AOt
04PIA02
04PIA03
04PIA04
04PIAO')
04Pl AOfJ
04Pl AC7
04P1 A09
01 PI B21
04PIA 11
04PIAll
04Pl Al t;
04PIA11
04P1AIR
04PIA20
04PIA21
04Pl A2l
04PIA24
04PIA2')
04Pl A7.()
C4PIA27
04PIA2R
Q4Pl A30
04PIA31
04PIBOl
04PIB02
04PIB03
()4P1804
04P1BOS
89633300 C
R E
l
I
S T
SIGNAL-NAME
04
01
03
03
0!5
05
01
01
09
09
011
Oll
013
013
015
015
W~ITE*
WRIIE*
R fJfC T*
REJECT*
~C*
MC*
S05
506
seo
S012
5011
503
504
Me*
Me*
S015
SRSM*
5,"0*
PEL*
S016
5011
32KW
S~8
SA9
SA10
SA11
SA12
SAl3
SA14
SALe;
SCI
S02
S07
SOB
SOq
A B 1
w.L.
89819103
B9679103
89879103
89819103
89379103
89819103
89879103
89d 79103
89819103
89819103
89819103
89879103
89879103
89879103
89879103
B9819103
89819103
89819103
89819103
89879103
89819103
89879103
89819102
89879102
89819102
89819102
89879102
89819102
89819102
89819102
89819100
89879102
89819102
"89819102
89879102
89819102
89879102
89879102
89879102
89879102
89879102
89879102
89879102
89819102
89879102
89879102
89819102
89819102
89819102
89879102
89879102
o
118
FR .LEV TO.LEV
1
2
2
1
2
1
2
1
1
1
I
2
1
1
2
1
2
1
1
2
2
1
I
1
1
1
1
1
1
1
2
1
2
2
1
2
1
2
1
I
1
1
2
1
1
2
1
2
1
1
2
1
I
1
I
1
1
1
1
1
1
2
I
1
1
1
I
1
1
1
I
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I
1
1
1
1
1
1
I
1
1
1
1
1
I
1
9-57
PAGE NO
4
fRr:lM
03P1806
0~PIB09
03P 1610
01P1812
03PlB14
03P1817
- 0]P1818
03PIB21
01PIB~3
03P1824
OJP182S
03P187.6
03PIB21
OlP 1828
03PI830
03P1631
04PIAOl
O~PIAOI
OltP1A02
04PIA02
O~Pl A03
0itPIA03
04PIAOit
OItPiAOIt
.0lt-PIA05
04Pl A05
04PIA06
0itPIA06
04Pl A01
04PIA01
04PIA09
04PIA09
OltPtA11
OItPIAll
04Pl A13
04PIAl3
04P1A15
04PIAl5
O~PIAll
04PIA17
04PIA 18
OltPlA18
0~PIA20
04PIA20
04PIA21
04PIA21
04 P IA23
OltP1A23
04PlA24
04PIA21t
04Pl A25
9-58
W IRE
TO
04P1806
C4Pl BOq
04PIIHO
04PIB12
04PIB14
04PIB17
04PIBIA
04PIB2t
04PIA21
OltPl B2~
04PIA2S
04PIA2t.
C4PIB21
OltP1B2A
OltPl A30
OItPIB 31
03PIAOl
05PIAOl
03PIAO~
OSP1 A02
05Pl AO)
03PIAOl
0.3Pl A04
OSPI A04
03PIA05
05PIAor;
05PI AOft
03PIA06
03Pl A01
OSPIA01
03PIAOq
05P1 AOq
O~PIA 11
05Pl All
05PIAl1
03PIA13
03P1 All)
or;PlA15
03PIA17
or;PlA11
C5PIAIA
03PIAIA
05Pl A20
03PIA20
03PIA2t
or; PI A21
O13PIA21
03PIA23
013 PI A24
03PIA24
or; Pl A25
l
1ST
S"lGNAl- NAME:
SOlO
S013
S014
5S*
SPI*
SVIO*
AUTOLOAD
S wRITF*
SAO
SAl
SA2
SAl
SA4
SA5
SA6
SA7
SOt)
505
S06
S06
seo
SOC
SOl2
S012
5011
SOli
S03
S03
SOIt
SOIt
Me*
Me*
S015
S015
SPSM*
SPSM*
SRO*
SPQ*
PEl*
PEL*
S016
5016
5011
SCll
32KW
32KW
SAA
SA8
SA9
SA9
SA10
A
~
".l.
89379102
89819102
89819102
89819102
89879102
89819102
89819102
89819102
89879102
89d 19102
89879102
89879102
89819102
89819102
89879102
89819102
89a 19102
89a19102
89819102
89819102
89819102
891319102
89.') 19102
89819102
89879102
89819102
89d1910l
S9819102
89379102
89819102
89879102
89819102
89819102
89819102
89819102
89819102
891;1 19102
89879102
89819102
89879102
89819102
89d 79102
89819102
89879102
89819102
89879102
89819102
89819102
89879102
89819102
89819102
1 o 7/8
FR.lEV TO.LEV
1
1
1
1
1
1
1
1
1
1
1·
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
I
1
1
1
1
1
1
1
1
1
2
2
1
1
2
1
1
2
2
1
1
2
1
2
1
2
2
1
1
2
1
2
2
1
2
1
1
2
2
1
2
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
89633300
A
PAGE
5
til]
\of
I
RE
TO
FROM
04PIB2~
03P1A2C;
05PIA2£.
03PI A26
05P1Al7
03PIA27
OlPl A2A
o5P 1 A2 R
0C;PlA30
031>1 A30
03PIA31
05Pl A31
03PIBOl
05PIBOl
05Pl RO~
03PIBO?
05PIROl
03P1BOl
03PIB04
05PIR04
05P1 BOI)
03P1SOC;
05PIR06
03P1 R06
05P1809
03P1809
OlPIBI0
05PIBIO
05Pl B12
03PIS12
03P1814
05P1814
05PIBl1
03PlfH1
OC;Pl BIA
O.3PIBIR
05Pl8l1
03P1821
03P1Sl1
05Pl B21
OC;P 18 24
01PIBl4
05Pl825
04PIB25
04P182b
04P18?b
04P1821
0ltP1627
04PIB28
04P1B28
OftP1830
04P 1B 10
03Pl8l6
05PIR26
0.3PIBl1
OSP1B27
05PIB2R
03PIB2R
OSPl830
OJPIB )0
04PIA25
04PIA2b
04PIA2b
04P lA2 7
04Pl A27
04Pl A2 8
04PIA28
O'tPl A30
04Pl A3 0
04PIA31
Oft-PLA)1
0'tP1R01
04PIBOl
04Pl B02
04PIR02
04PIR03
04P1803
04P IR04
04P1804
04PIB05
04P 1805
0ltPI80b
04PlS06
04P1B09
OftPIB09
04PIRI0
04PIBI0
04P18l2
04PIB12
04PIB14
04P1S14
04P 1811
Olt-Pl tH 1
04P1818
04Pt818
OftP1821
04P1821
04P1823
04PIR23
04PIB24
04P1824
01p182~
89633300
A
l
I 5 T
SIGNAL-NAME
SAL 0
SAil
S~lI
SAI2
SA12
SA13
SA13
SA14
SAl4
SAl5
SA15
501
SOL
S02
S02
S07
S07
SDB
S08
S09
SD9
SOLO
SOLO
5013
SC13
S014
S014
SS*
SS*
SPI.
SPI*
SVIO.
SVIO·
AUTOLOAD
AUTOLOAD
S WRITE.
S WRITE.
SAO
S_O
SAl
SAl
SA2
SA2
SA3
SA3
SA4
S_4
SA5
SA5
S~6
SA6
A B 1 C 1/8
W.L.
89879102
89819102
89819102
89879102
89879102
89819102
89819102
89879102
89879102
89819102
898'79102
89819102
89819102
89819102
d9879102
8<;819102
89879102
89819102
89879102
89819102
89879102
89879102
89879102
89819102
89819102
89879102
69819102
89879102
89879102
89819102
89879102
89819102
89879102
89819102
89879102
89319102
89819102
89819102
89819102
89879102
89819102
89a19102
8981910l
89819102
tt9d1910l
89819102
89819102
89819102
89819102
89879102
89819102
FRo .LEV TO.LEV
1
2
I
2
1
1
1
1
1
2
2
1
1
2
I
2
2
1
'1
1
1
2
2
1
2
1
2
1
1
2
2
1
1
2
2
1
2
1
1
1
1
2
2
1
2
1
1
1
1
l
2
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
9-59
PAGE NO
6
FROM
04P1831
04P18:31
05PIAOI
05Pl AOI
0.,PIA02
0.,P1A02
05PIA03
05PlA03
05PIA04
05PIA04
05P lAOS
05PIA05
05PIA06
05PIA06
05P1A07
05P1A07
05PIA09
05PIAli
05PIAll
05PIA13
05Pl AI3
05PIA15
05PIA15
05PIA17
05PIA17
05 Pl A18
05PlAl8
05PIA20
05 PI A20
05PlA21
05PIA21
05PIA23
05PIA23
05PIA24
05PIAl4
05P lA25
05PIA25
05P1 A2 6
-05PIA26
05 PI A21
05plA27
05PIA28
OSPIA28
05PIA30
05PIA30
05P1A31
05PIA31
05P1801
05PI801
05P180l
05P1802
9-60
W (
TO
05P1831
03Pl Rn
04PIAOI
13P181)
1JPIA1"
04PIA02
04PIA03
13PIA12
14P1815
04Pl A04
04PIA05
14PIA12
13P1812
04PIA06
04PIAJ7
13P1815
04PIA09
04PIA11
14PIA14
12PIA14
04PIAIJ
04PIA15
12PIA20
12PI801
04PIA17
04PIAIA
27P2A2t
27P2A18
04P1A20
04P1A21
21PIA12
14Pl A05
04P1A21
04PIA24
14P1 A2'
14P1805
04PIA25
04PIA2f1
14PIAZl
14P1 AOA
04PIA27
04PIA28
14Pl A26
14PI80Q
04P1A30
04P1 All
14P1B25
13Pl AI0
04PI801
04P 18 02
13P1810
R E
l
I S T
SIGNAL-NAME
SA7
SA7
S05
505
506
506
SCO
SOO
5012
S012
5011
5011
503
503
504
504
Me.
5015
SD15
SRSH.
StcSM.
S~Q*
SRO·
PEl*
PEL.
5016
S016
5017
SC17
_32K"
32KW
5,\8
SA8
5,\9
5'\9
SA10
SAIO
SAil
SA II
SAi2
SAI2
SA13 SA13
SA14
SA14
S'\15
SA15
SOl
SOl
S02
S02
A 8 1
W.l.
89879102
89879102
89879102 _
89879100
89819100
89819102
89879102
89879100
89879100
8987-9102
89879102
89879100
89879100
89879102
89879102
89879100
89879102
89379102
89879100
89879100
89879102
89879102
89819100
89879100
89879102
89879102
89819100
89819100
89879102
89879102
89879100
89819100
89879102
89879102
89879100
89879100
89879102
89819102
89819100
89879100
89879102
89819102
89879100
89879100
89879102
89879102
89819100
8Q879100
89879102
8987910Z
89879100.
o
7/8
FR.lEV TO.lEV
2
1
I
2
2
1
1
2
2
1
1
2
2
1
1
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
. -2
1
-1
2
2
I
1
2
2
I
1
2
2
1
1
2
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
22
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
89633300 A
I>AGE Nt]
7
W I
TO
FROM
05P1B03
0'>P1B03
05P1B04
05P 1 804
05 PI B05
05P1B05
051>1806
05P1B06
05P1809
05P1809
0'> PI RIO
05 PIB 10
05PIB12
0,>1>1B12
05PIB14
05Pl B14
6 5@ 18) /,
05PIB17
05 P 1 B17
05P1818
05PlIH8
05i>IB18
R E
L I
S T
SIGNAL-NAME
131>1Al'>
04P11303
041>1 B04
14P1B17
141>1 RIO
C4P1RO'>
04P1806
14P1A10
14P1R76
041>U\OQ
04P1810
14PIA1'>
12P1R2?
041>1R1?
04PIB14
pP2A1A
S01
S01
508
S08
S09
509
5010
5010
5013
SC13
SC14
S014
SS*
SS*
SPI*
S P 1*
J 2 P? B2A
5 OW ttl
12P1AOI
041>1B17
04P181A
10P1B19
1 OPI B20
SVIO*
SVIC*
ALTOLC.AD
AUTOLOAD
ALTCLGAO
A 8
1 0 7/8
N .L.
89879100
89819102
89819102
89879100
89879100
89819102
89879102
89:-379100
89879100
89819102
89819102
89379100
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
SQf)79 J flO
?
esa 79100
?
89819102
89379102
89879100
89819100
2
1
1
3
2
~
2
2
2
3
2 Removed by
f FCD CK676
2
2
2
2
2
2
2
2
2
1
2
2
2
2
2
2
2
2
1
2
1
2
1
2
21
2
1
89879102
89879100
89879100
89819102
All S •
~!i2I!H !!j
l?f?"?fI
5eEf~UBt51
B9fH~
OSP1821
05P1821
051>1823
05 PI 873
05PIB24
05P1B24
05PIB25
05PIB25
05PIB26
05P1B?6
05PIR21
05PIB21
05PIB28
05P 1 B2 8
05Pl830
05P1B30
05PIB31
05PIB31
06PIAOl
06PIA01
06PIA02
06PIA07
06PIA03
06PIA03
06PIA04
06PIA04
06PIA05
06P lAO 5
121>1A19
04Pl B21
04P1823
13P1BO'>
S WRITE*
89379100
89879102
89879102
89879100
89879100
89879102
89879102
89819100
89879100
89879102
89879102
A9879100·
89d79100
89879102
89379102
89879100
89879100
89379102
89379103
8<;879103
89879103
89879103
89879103
89879103
89379103
89879103
898791)3
898791J3
13PIA2~
04P1R24
04PIB2';
13PIACS
13PIB23
04Pl B26
04P1B77
1 3P1 BOA
13P1 Alb
04P182A
04PIB30
13P1 AOq
13PIB2';
04P1831
01PIAOI
02PIAOI
07 PI AD?
OZP1AO?
07P1A03
02 PI AO'"
021' lA 04
07P1A04
02 PI AQ';
C1P1AO';
89633300
E
S ~RITE*
SAO
SAO
SAL
SAL
SA2
SA2
SA3
S~3
SA4
SA4
SA5
SA5
SA6
SA6
SA7
SA7
OA5*
OA5*
O/J6*
OA6*
OAO*
OAO*
OA12*
11 A12*
OA11*
OA 11*
FR.LEV TO.LEV
hHi
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
1
?
1
7
2
1
?
1
Removed by
I
FCD CK676
I
9-61
Pf4GF NQ
8
FROM
06Pt A06
OOP lA06
06PIA07
06Pl A07
06PIA09
06 PI A09
06PIA11
06PIAll
0l)PIA12
00PIA12
06PIA13
06PIA13
06P lA14
06Pl A14
06PIA15
06PIA15
06Pl A16
06PIA16
06PIA17
00 PI A17
06PIA18
06PIA18
06PIA19
061>1A19
06Pl A20
06PIA20
06PIA21
06PIA21
06PlA22
06PIA22
06PIA23
06PIA2:3
06PIR01
06P1801
06P 1 B02
OhP1R02
06P1803
06P IB03
06Pl B04
OhPIB04
OoP 1 BO 5
06P1 B05
06PIB06
06P1B06
06Pt sO 7
06P 1 R07
06P1809
06PIB09
OoP 1 B 10
Oft PI Al 0
OnPIB12
9-62
W I
R F
TO
07PIA06
02P lAC6
07Pl A07
02PIA01
C 7Pl A09
O?PIAQ9
C7PlA 11
02P1411
02PIAl'
C1P lA 12
07P1Al".\
02Pl An
02P1414
071>1A14
C7PIAl'i
02PIA15
07PIA16
02PIA16
02PIA17
01PIA11
o 1P tAl R
02PIA18
02 PI AIQ
01Pl Al Q
02PIA20
07Pl A20
07PIA21
02PIA21
02PIA22
C1PIA2?
07Pl A2~
02 P IA2i
01PlROl
02PIBOl
02P1807
07 P IB07
02PIBOl
01P1R01
02Pl B04
07 PI B04
07PIBO'>
01PIBO'>
C1PIRCh
02PIROA
02 PI 801
07P1R07
C7 PI B09
01 PI B09
C7p 1 B 10
02P1BI0
O?PIBl?
l
I
S T
SICNAl-NAME
OA3*
OA3*
OA4*
OA4*
TP
TP
OAI5*
OAI5*
00
QC
02
02
04
04
06
06
08
08
010
010
012
012
014
014
WEl*
WEZ*
REAO*
READ*
REP l v*
REPl v*
Pf379103
89879103
89a 79103
89879103
89879103
89819103
89879103
8987~103
89879103
89819103
89819103
89;319103
89819103
89879103
89d7Q103
89879103
FR.lEV TO.LEV
1
2
1
2
1
2
1
2
2
1
1
2
2
1
1
2
1
2
1
2
1
2
2
1
1
2
2
1
1
2
1
2
2
1
2
2
1
1
2
2
1
2
1
1
2
2
1
1
2
1
2
2
1
2
1
2
1
2
1
1
2
2
1
1
2
1
2
2
1
2
1
1
2
2
1
2
I
1
2
2
1
1
2
1
2
2
1
2
1
2
1
2
1
1
2
2
1
1
2
1
2
2
89633300
A
PAGE NJ
WI R E
9
F~OM
06PIR12
06P1813
06PlS13
OoPlSl4
ObPISl4
ObPlBlS
ObPlB15
ObPIB1b
ObPIBl6
OoPl Bll
ObPIB17
OoPIB18
ObPI B18
06P1B19
06PIA19
06Pl B21
06P1B21
Ob Pl B22
ObP1822
ObPlB23
ObPls23
01PIAOl
07PlAOI
01PIA02
01P lA02
01PIA03
01PIA03
01P lA04
07PIA04
01PIA05
01PlA05
01PlA06
07PIA06
07PIA07
01PIA07
01Pl'A09
07PIA09
01P1All
01PIAll
01PIA12
07PIA12
07PIAl}
01P1A13
07PIA14·
01PIA14
07Pl A15
07PIA15
01PIAlb
07PIAlb
01PIA17
01PIAll
TO
C1PIBl'
01Pl Bl1
02PIBl'3
02P1814
07PIB14
02PIBIl)
01PIB15
07PIB16
02PIB16
01PIBl1
02PIBl1
02PlB18
07Pl BIR
C1PIB19
02PLB19
02Pl B21 ..
01Pl821
02Pl B22
C1PIB22
02PIB23
LIS T
SIGNAL-NAME
01
03
03
05
05
01
01
oc;
09
011
011
013
013
015
015
WRITE*
WRl TE*
REJECT*
REJECT*
MC*
07Pl82~
Me.
06PlAOl
13PIB19
13P1Al9
06PIA02
06P1AOl
L3P1829
14Pl819
06P1A04
06PIA05
14PIAZO
13Pl82t
06PlA06'
06PIA01
13P1 A20
15PIA09
06PIA09
06PlAll
14PIA19
12Pl831
ObPIA11
06PIA13
15P1A13
15P1A14
06PIAl4
06P1 Al~
15PIA 11)
15PIA16
06PIA16
C6P1A 11
15P1A11
01'5*
OA5*
OAb*
OA6*
OAO*
OAO*
OAI2*
OA12*
01'11*
OA11*
01'3*
01'3*
OA4*
OA4*
T.P.
TP
OA15*
OA15*
gO
go
02
02
04
04
06
06
08
08
010
C10
89633300 C
AB 1
W.L.
89a 19103
89879103
89879103
89819103
89819103
89819103
89d 1910.3
89879103
89819103
89819103
89879103
89819103
89819103
89879103
89879103
89879103
89819103
89879103
89879103
89879103
89879103
89819103
89819100
898.,9100
89879103
89819103
89819100
89a 79100
89879103
89879101
89819100
89819100
89879101
89879103
89879100
89879100
89819103
89819103
89819100
·89819100
89879103
89879103
89879100
89819100
89879103
89819103
89879100
. 89819100
89d19103
89879103
89819100
o
7/8
FR.LEV TO.LEV
1
1
2
2
1
2
1
1
1
2
2
1
2
1
1
1
2
1
2
2
1
1
2
2
1
2
2
1
1
2
2
1
2
1
2
1
1
2
2
2
1
2
1
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
1
1
.2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
9-63
PAc;E NJ
10
FAOM
07PIA18
07'1A18
C7Pl Al q
01PIA19
01'1A20
07P1420
01P lA21
07Pl A21
07PIA22
01P1A22
01PIA23
07PIA23
07P1801
C1P1801
07P1802
07P1802
0'1P1A03
07P1803
07P1801t
07P1804
07Pl&05
07P1805
07P1806
07P1806
01P1807
07P1807
07P1809
07P180~
07'1810
07'181.0
.07P1812
07'1812
01P1813
07PIA13
01PL81.4
07P1814
07P1815
07P1815
07P1816
07'1816
07P1817
07P1817
07P1818
01P1818
07P1819
07P1819
07P1821
07P 1821
01P1822
07P1822
01P1823
9-64
VII IR t:
TO
15PIAl~
06'1 A18
06PIA19
15PIA1<"1
12P2A21i
06P1A20
06P1421
12P1829
. 15P142'
06PIA2'
06P1 A2l
12P2AIQ
.06P1801
1 1Pl A30
13PIA21
06P1802
06P1801
13P1820
14PIB2Q
06P1804
C6PIROli
14P1821
14P lA20
06P1806
06P1 B')7
12P1821
14P141"
06P180eJ
06P1810
·14PI8111
15P1811
06PIA12
06Pl Al1
15P1811
15P1814
06P1814
C6PIA1'i
15P1811i
15P181"
06P1811.
06P1811
15PIA11
15P18111
06Plalf1
06PIA1Q
15P\ 819
12P1830
06P1821
06P182'15P1821
15P1821
liS T
SIGtfAl-NAME
012
012
014
014
WEZ*
WfZ*
READ*
RFAO*
AEPl V*
REPl v*
P~TM*
PRTAO*
OA1*
OA1*
OA2*
OA2*
OA7*
.OA7*
OA8*
. OA8*
OA9*
OA9*
OAIO*
OAI0*
CHI*
CHI*
OAI3*
OAI3*
OAI4*
OAI4*
01
04
03
03
05
05
01
07
Oq
09
011
011
013
013
015
015
WRITE*
WRI TE*
REJECT*
REJECT·
MC·
A B 1
" .l.
89879100
89879103
89879101
89819100
89879100
89879103
8987910J
89879100
89879100
89879103
89879103
89879100
8987910J
89879100
8<;879100
89879103
89879103
8<;879100
89~79100
89879103
89d7910;)
89879100
89879100
89879103
89879103
89879100
89«179100
89879103
89819103
89879100
89879100
89819103
o 7/8
FR.lEV TO.lEV
2
1
1
2
2
1
1
2
1
1
1
3
1
2
2
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
3
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
?
1
1
1
1
1
2
2·
2
2
1
8987~10l
'I
89879100
89979100
89879103
8'-)879103
89/379100
89879100
89879103
89879103
89879100
89879100
89i179103
89879103
89819100
89879100
89879103
8987910J
89879100
8~8 791{;O
2
2
1
1
2
2
1
1
2·
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
.2
89633300 A
I\GE NO
WIRE
11
FROM
TO
01P1823
08PIA01
08PIA02
08PIAO 3
08PIA06
OBPIA01
08P1AI0
08PiA11
08PIA12
08PIA13
08P1A14
03 PI A15
08PIAl1
08P1A19
06Pl B23
09P2AC1
12PIA28
13Pl B31
09PIA11
14P2A30
I1P2 B26
09P 2A On
091>2A22
12PIB12
09PIB30
12P1S0Q
10P2AOl)
09P2A26
11P2BI0
14P2B18
12PIB24
09P 1 A it
1 OP2 Al 0
14P2B14
09Pl B24
14P2 B20
09P2AOl)
091>2A25
10P1A24
12P1B21)
13P2 B06
09P2B09
13P2A30
13P2A05
12P2Bl1
09P1821
10PIA16
10PIA26
10Pl a2e;
OqPIA28
10P2B07
09P2 B07
10P2A25
10P2 A09
1 OPI B03
11P1B29
10P1826
I1P2AOI
09PIA18
09P2 B30
10P2B 30
10P1A07
I OPI A21
13P2A 29
10P2A02
DqPl A04
08PIA20
08Pl A20
08PIA21
08P1A22
08PIA23
081> lA24
08 PI A26
08PIA27
08PIA28
08 PI A30
08PIA.31
08PIB02
08P1802
08PIB12
08PIB13
08PUH 8
08P 1822
08 PI B23
08Pl a2 5
08PIB26
08 PI B21
08P1829
08P1B30
08P1831
08PlAOI
08P2A02
081>2A04
08P2A05
08 P2 A01
08P2A08
08P2A09
031>2AI0
08P2A11
08P2A12
08P2A13
08P2A14
08P2A15
08P2A16
89633300 H
i
LIST
S IG NAl-NAME
MC*
WClK
PWRQ
I>E FNABL E
ABONE
P WI 0
PwRESET
AB ClGCKOUT
AB TOG
P WI< QS... IF rED
AB RENABL E*
BUFF2Fl*WMO
AwRES(l-41
AS DATA
SfM*
SFM*
WFM
AS lOZ
ANOENV(2)
10 ABGR T*
012
PRBOT
B WRES(1-4~
R NCENV(I)
A PCSIAMBlE
PE START
PE ST~RT
ABWRES(5)
P EClOCK *
WPEQUEST*
GC128
PRFB
ANOENV (3)
AENVlS)
ANOENV (5)
AB DOT
A POSTAMBlE
e POSTABU:F
A NOENVtl)
A EN VI 2)
AENV(4)
PE PARERR*
A.SKEWOVF G
PSfM*
AB PRESET
BREADY F
A READy F
ANODROPOUH
ASYNC(4)
PECHARClK
AC2
AB DEN
A B 1 0 7/8
w.t.
89819103
89a 79100
89879100
89819100
89879100
89819100
89879100
8987'HOG
89819100
89819100
89879100
89819100
89819100
89879100
8903 19104
89879104
89879104
89819100
89879100
89879100
89819100
89879100
FR.lEV TO.lEV
1
1
2
'2
2
1
1
2
2
2
2
1
1
2
1
1
2
2
2
1
1
2
2
2
2
1
1
2
I
1
1
1
1
1
8q819100
2
89819100
8'J819100
89879104
89819100
89879100
89819100
89819100
89819104
2
2
1
1
1
1
1
2
2
2
2
2
1
1
2
2
2
2
89379104
89319100
89879100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89879100
89819100
89819100
89819100
89819100
89819100
B9819100
89879100
89819100
89819100
2
2
2
2
1
2
2
2
2
2
2
2
1
2
2
2
1
1
2
2
2
2
1
1
2
2
2
2
1
1
1
1
1
2
2
1
1
1
1
1
9-65
PAGE NO
12
FROM
08P2All
OBP2A18
08P2A19
OAP2A21
08P2A22
oap2A23
08P2A24
OBP2A26
08 P2 A27
08P2A28
OBP2A30
08P2BOl
OAP2B02
08P2a03
OAP2B04
OSP2BOS
08P2B06
OSP2B07
OSP2B08
OBP? B09
08P2B10
08P2BIO
OR p2 Bl1
08P2tH2
08P2a13
ORP2814
08P2B15
08P2B16,
08P2Bl7
08P2R19
08P2R20
08P;>B23
08P2B24
08P2B26
ORP2B27
08P2B28
ORP2 B2 9
QRP2B3Q
09P 1 AO 1
09P1A07
09P lAO 3
09PIA04
09PIA04
09PIA05
09PIAll
09PIAll
09PIA12
09PlA13
09P lA 16
09PIA17
9-66
W I
TO
lOP2B02
14P2 AOt
lOP2BC5
13P2 A240C;PIA31
11P2825
13P2 A21
09P2A21
lOPIBO?
lOP2AOA
09PIA13
09Pl A01
o 9P LA 16
09P2AIO
1 OPl AO~
lOP2A24
OQP2Al1
09P2B06
10P2B06
1]PIB30
IlP2BO;>
14P2B06
1 OP2 A0413P2BOR
10P2 All
011P2 AOI
0C;P2AOl
09Pl BO;>
09P2AO?
10P2A29
09P2A29
12P2B29
12PIA06
09Pl A30
lOP IA 25
LOPIA11
10P2A21
C9P?AOQ
09PIBll
IlPlfH 1
081'2801
10PiA04OAP2Alit
1lPlBl6
oaPl A2"
lOP 1 A 11
IIPl A12
08P2 A30
08P2130;>
lOPIA17
R E
L I
S T
SIGNAL-NAME
AC1*
PE EOP.
ACNEG*
7'5IPS
01*
PRSTROBE
Al2
PRTY FN 81*
PRTY GN A4*
PRTY GN A2*
PRTV GN B3*
8 NCE~V(4)
B NOENVn)
B NOENV(2)
ANOENV(4)
AFNV( U
AB PAR lTV
B SKEwCVF F
A.SKEWOVF F
PE lOST C .&T
REV*
REV*
,A REACY G
PE wORNING
A5YNC(2)
AS1*
Be2
PRTY GN 84*
BC1*
AONEF*
BCNEF*
T~3
POSTAMBLE
02*
PRJ ... GN A5*
PRTY GN A3*
PRTV GN Al*
PRT\, GN 132*
Gt\D
PMOUT 2
A NOENV(4)
AS DE/\;
AS OEN
PwOIN 2
AS LGl
AS LOl
PRIN 6
PRTY GN 83*
B NOENV(],
AACNE
A B 1 0 7/8
w.L.
89879100
89879100
89379100
89379100
a9a 79100
89879100
89879100
89879100
89879100
89879100
89879100
89379100
89879100
89f:i 79100
89879100
89879100
89879100
8'1879100
B9879100
89:i79100
89879104
89879104
89879100
89879100
89879104
89879100
89'379100
89879100
89879100
89879100
89879100
89879100
FR.lEV TO.LEV
2.
2
1
1
1
2
1
2
2
1
1
2
1
1
.2
2
1
1
1
2
2
2
2
1
7
2
2
1
L
1
2
.1
1
2
1
2
1
2
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
89879104
8913 79100
1
89879100
2
89879100
89879100
89879100
89879104
89879100
8'7879100
89a 79100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
1
2
2
2
2
2
2
2
1
2
2
1
2
1
1
2
2
1
2
1
2
2
2
2
2
I
2
2
2
1
896~3300
H
PAGF Nl
13
FR;J M
09P1A17
09PIA18
OQPl Al R
09PIA20
0<)PIA21
09Pl
A2~
09PIA?H
\)9 PI
A~ tl
OtJPl A j lJ
09PLA30
{HPIA;il
09PI.Ail
OJPl AO 1
nqpIH02
WIP 1 H06
09PIRlI
09Pl Al j
01PIB24
09 PI R24
09PLA77
09P1B27
WIRE
LIST
A B 1 0 7/A
SIGNAL-NAME
TU
AH( NE
Ae PRESET
8'B79100
10Pl~lR
CRP7 A09
AE PRtSFT
89319100
11PIAl'>
11PlfD7
llPlfH'>
lOPIA2Q
PIII.OI N 4
a937~100
CQPl\CI,
08P1829
C8P2B2f:t
10Plt\ sO
a~179100
8 'Ii 79100
89879100
:J
PRDOUT
PPIN ~
AR OOT
89i7~100
CUT
AB
n2*
fJ 2*
10PI Ail
01*
CAP2A?'
01*
10PIR:11
PCl
Of\P;UH~
PRTY (.N 134*
IIPIBOR
09Pl A())
PRUrl.lT b
GND
11;>7~?O
P~OUT
ORPIA2h
1112
012
LOPI R24
08P1821
lOP 1'327
4
PR~fl
PRF !:3
1\8 f A07
wet K
09P;?A08
C3P2 R10
O<)P2AI0
08P280l
PRTV GN 82*
Ii NCENV(2)
09P7A12
09P2Al3
11PI110l
PFDOUT
CRP280A
toR PARITY
10P2 A l-i
11 PI R1 "1
AR PAR.ITY
PI< T N 4
08P2A2h
lOP? A22
AS
CqPIA17
AB
OQP2A13
09 P2 Al Q
01A28
PWOUT 3
I1Pl B 10
P~OIN3
J IP2824
11 PI A14
C BI> 2410
09P? AOI
13P2811
11fl?809
PwOUT 6
PPIN2
8 RfAOY F
AS1*
08P2B04
09P1404
Af\OENV(4)
A8 DEN
P WOI N 0
I1PIAI"
OAP2 A12
I1P2A04
0<;P1411
11 PI All
08P2B28
08PIB25
(;9P1 A17
091>1A18
11PIA09
11P1809
11P11114
08Pl A31
DRP2A?7
OAPIB2"
OBP?A11
o 9P 1 A? R
PC 1600*
P~OLT
a
ANOORCFOUTf
PRINP
AB LOl
PRIN 5
PRTY GN A3*
AND ENV( 3)
ABCNE
AB PRE SE T
PWOIN 1
PRDOUT 7
PRIN 7
/':. PCSTAMBlE
PRT\' GN A5*
A EN
V( 5 )
ASYNC(4)
A8 001
07*
01*
09PIA30
09P1A31
09PIBOI
03 P2A27
10PlfH)6
11P1801
20PIAOI
o5P 1 91 ~
16P2 BOA
05PIBUl
11P2"lOA
OQp1B24
OBPI '327
PROOUT5
AUTOLOAD
ALTOLCALJ
ALTOLOAD
10PIB26
13P1827
10P1828
lOPIB30
08P2A07
09PIB27
A.SKElI\CVF G
10P2A02
08 P2 AI')
oap 2811
10P11319
10Pld20
10P18?}
10PI824
10Pli125
10P2A04
10P2 A05
10P2A06
10 P 2A07
9-68
I 1 P1 Al '3
101>1A31
101>1B01
101>1802
101>1B03
10P1820
A07
10P2A08
10P~
08P2A04
10P2B01
09PIB30
OQP1A17
09P2 AO~
IlP2B?7
OQP2A07
C8
P~
FR.LEV TO.LEV
SIGNAL-NAME
10PIA30
1 OPlfH 9
I
Til
A B 1 0 7/8
lIST
A2q
pe2
PRTY GN A4*
AENV(4)
ALTOLUAO
P~OLT
1
D12
ANCFNV(5)
PRFB
NCDPOFClT
RENABLE*
he
AC2
A READY G
A ~R ES ( 1- 4 )
AS CLUCKOUT
wCLK
WCLK
PRTY GN A2*
89879100
89879100
89d79100
89879100
89,')19100
89879100
89879100
89379100
89"179100
89819100
89879100
89879100
89379100
89879100
81B29
llP1830
11plS31
IlP2AOl
IlP2A05
11PlA13
IlP2A18
11P2A25
11P2R01
Ilp2B02
llP2803
11P2B04
IlP2805
llP2R07
11P2808
9-70
W I
TO
13PIA24
13PIAl1
13PlAlI
14PIB21
12PIAOFt
IJP2A26
13P2B 12
12PIB19
lOPIB06
13PIA07
09P7. Al ~
t3P IB 06
13P2BO,)
12PIBIA
09P2A2R
09PIA21
09PIB06
IOPlA2.
09P2Bll
lOP2AIQ
09P2A19
1 oPt A23
09PIA2J
09PIAor;
1 OP2 A27
10P2B03
09PZA27
14PIAIJ
14PIB16
14PI B21
14PIBQ A
14PIAZ4
14PI A16
13PIB27
14Pl All
14P2 B01
oap2AO')
12PZA05
12P1S06
08P2AOfJ
17.PIAl~
09P7.BIO
12PIA26
12Pl A27
lOP2B16
08P2Sl0
IlP~ AOA
lOPIAIO
lZP2 A2q
14P2BO?
lOPIS2}
R E
l
I
S T
SIGNAL-NAME
kRTAPE
WRTAPE
WRTAPE
WRTAPE
UPPER
7
6
:i
10
9T
2FkC
RFS2*
PROCUT5
RCTAPE 5
PRDOUT 4
ROTAPE 4
1600
.1600
PRDOUT 2
PROOUT .3
PRDOUT 6
PRDOUT 7
PWDIN 3
PR IN 1
PRIN 4
PRIN 7
PR[N 3
PWDIN 2
PhOIN 5
P wO I NP
PWDIN 6
WRT APE 13
WRTAPE lZ
w~T ~PE
q
hPTAPE
WRTAPE
hRTAPE
WRTAPE
WRTAPE
8
15
14
2
11
FIll
PE PARERR.
RMOT
AID
PSFM*
STWCRC*
PhOUT 3
LRCC STATE
ROS·
WFM1TM*
R EV*
EOP
PRINP
4MHl
SEOP*
PhOUT 1
A B 1 07/8
W.l.
89379100
89d 79100
89879100
89879100
89879100
89879100
S9879100
89879100
89879100
8llS 79100
89819100
89879100
89879100
89879100
6987910C
89879100
89879100
89879100
89879100
89879100
89379100
89S 79100
89879100
89879100
89879100
8C;879100
89879100
89879100
89879100
89879100
89879100
89tj 79100
89879100
89879100
89879100
89819100
89879100
89879100
89879100
89819100
89879100
89,:179100
89879100
8987910·0
89879100
89d 79104
89879100
89879100
89879100
89879100
89819100
FR .lEV TU.L EV
2
2
2
2
2
2
2
1
2
2
7.
2
2
2
2
2
2
2
2
2
1
2
2
2
2
2
1
1
2
2
7.
2
2
1
Z
1
1
Z
Z
Z
2
7.
Z
7.
Z
2
2
2
2
2
2
2
1
Z
·2
2
2
2
2
2
2
2
7.
1
2
1
Z
1
7.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
Z
7.
7.
1
1
1
1
1
1
1
89633300
A
PAGE NO
11
FROM
11P?B09
11P2B10
11P2Bli
IlP2EH2
11P2B13
IlP2B14
I1p2815
UPl816
Ilp2S11
IlP2BIR
llP2819
11P2B20
11P2B22
11P2 82 3
11P7B24
11P2825
11P2826
11P2B21
IlP2B28
llP2B29
I1P2B30
11P2B3l
l2PlA01
12PlA01
IlPIA02
12PIA03
12PIA04
12PIA05
12PIA06
12PIA08
12PIA09
12P lA 10
12PIAll
12PIA12
12PIA13
12PIA14
12P1A14
12PIA16
12PIA17
12PIA19
12PIA19
12PIA20
12P 1 A20
12PIAli
12PIA23
12PIA24
12PIAl5
12PIA26
12PIA27
12Pl A28
12PIA30
89633300 H
W I
R E
l
I
S T
A B 1 07/8
TJ
SIGNAL-NAME
W.L.
1 OP1 AO'
Pl
13P2 AOb
0~PIAI3
14P2B17
13P2B2?
I1PIB05
IlPIA31
IJP2A2R
IJPIB14
07P1807
15PIBC7
16P 1 B03
05Pl Bl?
10P2B16
14P282'>
08Pl A21
08PIBO?
14PIA01
14P2B16
13P2B20
01PIA21
15PIA21
15PIBll
C1PIB21
C7PIA12
15PIA12
14P2 B01
l.3P 2A 01
14P2B2l
IlPIB30
14PIA28
14 P2 Bl 0
13P2Al1
11P2B03
13Pl B2l
13PIA21
13P2B02
13P2A11
15P IB22
13P2A07
R E
l
1ST
A 8
S IG NAL-NAME
W.l.
CRce STATE*
PEl*
PEl*
89879100
89879100
8<.i879100
89879100
89379100
89879100
89819100
89819100
89819100
89879100
89879100
89879100
89879100
89819100
89819100
89879100
89819100
89879100
89879100
89879-100
89879100
89879100
89819100
89879100
89819100
89819100
89819104
89879104
89879100
89879100
89819100
89819100
89879100
89819100
89a 19100
8CJ879100
89379100
89879100
89879100
89819100
8'1879100
89819100
89819100
89819100
89819100
89819100
89819100
89879100
89819100
89819100
89819100
STO.P~R.ERR
UPPX1*
LOST DATA
ISTSP
AID
AID·
T~ANS.
I NCCA*
BUfF2Fl*WMO
WRITE CLOCK
P ~R Q SH 1FT EO
TTBUS\,·
ALl
1600
RESZ*
RES2*
BUf 1/0*
CHI*
CHI*
ss.
ss*
WFM/TM*
wfM/TM*
WfM
PE START
RESt. 1*
STOP*
ENA*
READ*
READ*
WRI TE*
WRITE*
00
00
STRMF
CONTACT*
lEGMF
RMOT
CONTAC T
lEGCf
EOP
EOP
STR8UF*
SElAl
lEGUS
READY
REJECT*
STRUS
1
o
7/8
FR.lEV TO.LEV
1
1
.2
1
1
2
2
Z
1
1
2
2
2
1
1
2
2
1
1
2
2
2
1
1
2
2
1
2
1
1
2
2
2
1
1
.2
2
2
2
1
2
1
2
1
2
2
1
1
2
2
1
1
1
2
2
2
1
1
2
2
1
2
1
2
2
1
1
2
2
1
1
1
2
1
2
1
1
1
2
1
2
1
2
2
2
2
3
2
2
1
2
1
2
2
2
2
3
2
89633300
A
P Ar.E NO
~
19
TO
FROM
12P2A17
12PlA18
12P2A18
12P2A19
12P2A19
12P2A23
12P2A23
12P2A24
12P2A24
12P2A25
12P2A25
12P 2A26
12P2A17
11P1A19
11P2A30
IlP2801
12P2ROl
12P2B02
12PlB03
12PlB04
12P2 BO 5
12Pl805
12P2B06
12P1B07
llP1R07
12P2809
IlP1BIO
12P2BI0
IlPlBll
12P2Bll
IlP2B13
IlPlB14
llP2815
12P2816
IlP1B17
12P2817
12P?B18
l2P2B19
12Pl82l
12P2B22
12Pl813
12P2823
12PlB25
12P1628
IlP2Rl9
12P2Bl9
l2P2B31
12P 2B31
13PIAOl
13PIA01
13P I AD 2
I
14PIB24
05PIBl,.
16PIA01
C7PIA21
1l)P2B2A
l5P2BI0
15PIB16
15PIBll)
15P2BOQ
07PIA20
21 P2 R30
05PIR19
16Pl BOI
1lP2 B05
1 lP2B 14
19P2 R02
15PIBl2
13P2AOQ
14P2 A09
IlPIAIO
14P2A15
13Pl A06
14P2R24
13PIA18
1,.P2B08
13P2AI0
13 PI B2A
14P2 A01
13PIAl5
14P1831
13P2B04
15PIAl2
l3P2A21j
13PlBl5
14P2826
08Pl B22
l3P2A 11
13PlB09
l5P2 A 10
15PIAl1
l5PIAl6
11)P2A 09
16PIA04
05P1 B16
13P28lb
08Pl B21
13P2826
11P2B lq
14P1BOl
llPlAOe;
IlPlA04
89633300 C
R E
l
I
A B 1 C 7/8
S T
SIGNAL-NAME
FfI./TM
SPI*
SPI*
PRTAO*
PRT~O*
OS
09
07
07
WEZ*
WFZ*
S.
SCFOM{ BU
SCROD ( SCR 1M
,.MHZ
TM1
01
01
MC*
USA
WMOT
RMOT*
RMOT*
WMOT*
A7
A7 .
S TR (NT
RUSY
RlSY
SElAO
LEGCC
StRCC
R EPL y*
PICOTECTEC
tNT
GC128
GC128
RESt*
LDlWA*
010
010
08
08
SCfOO( SCf 1M
SCRCMleUS)
TM3
TM3
RwlD*
RIIrolD*
ROTAPE 1
RCTAPE 2
L O.,.Xl*
W.l.
89879100
89379100
89879 LOO
89879100
89879100
89879100
89379100
89879100
89879100
89879100
89~ 79100
89879100
89879100
89879100
8987910C
89879100
89879100
89879100
89879100
89879100
89879100
8911 79100
89819100
89879100
89879100
89879100
89879100
89819100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89819104
8'i819100
89819100
89819100
89879100
89819100
89819100
89819100
89879100
89879100
89879100
89819100
89879100
89879100
89879100
89a 79100
FR.LEV TO.LEV
1
2
1
2
1
1
3
2
2
1
1
2
2
3
2
2
1
1
2
2
3
2
1
1
2
2
1
2
1
2
1
2
1
2
1
2
2
1
2
2
'l
v
1
2
1
2
2
1
2
1
2
2
2
2
2
1
2
2
1
1
2
1
2
2
1
2
1
1
2
2
LENGTH 10"
LENGTH 7"
2
1
1
2
2
1
2
1
2
1
2
2
2
3
2
2
1
2
3
2
.
1
2
1
2
2
1
2
1
t
2
2
9-73
P4GE NO
20
FROM
13PIA03
13P lA03
11P1404
13PIA04
13P LA05
13Pl AO'.)
11PIA06
1.~PIAOl
11Pl,..01
13PIA08
13PIA09
13Pl A09
13PIAI0
L3PIAIO
I1PIAIO
13P lAll
13PIA12
13PIAl2
13PIA12
13PIA13
13PIA14
13PIAlS
13PIA15
IlPIA15
13PIA16
13PIA16
13PIA16
13 Pl All
13PIA18
13PIA19
13PIA19
13PIA20
13PIA20
13PIA21
13PIA21
13PIA22
I1PIA23
IlP lA23
13Pl A24
11PIA25
IJP1A25
13PIA26
13PIA26
IlPIA21
13PIA21
13PIA30
13PIA30
13PIA31
I1PIA31
13PIBOI
IlP1801
9-74
W I R E
T1
11 PI AO~
14P1801
IlPIA01
IltP1404
l8P180A
05P182'i
12P280'i
IlP180'
IltPl R01
IlPIA2'
05P1830
18P1806
27PIAOl
05PIROl
1 AP2A21
IlPl42'i
18P282A
0l)PIA01
27PIAOI
14P1811
IlP1AIQ
21Pl A12
OSPI BOl
18P282'i
18PiA21t
05PI AO'
21PIAI0
I1PIA24
12P'-801
07PIA02
15PIA02
15PIAC7
01PIAOl
01P1802
15P180'IIPl A21
0'iPIB2~
l8Pl801
IIPl A21
12p2811
14PIA2'i
l8Pl R09
05PIR 2A
12P2AlI
14Pl A21
C1P1801
15P1801
IltP2A21
12PIA2'i
IlPIA()6
14Pl Aot
lIS T
SIGNAL-NAME
RCTAPE
ROT APE
R CTAP E
ROTAPE
SA2
SA2
RMOT*
RDTAPE
1
1
6
6
5
5
tfRTAPE 0
SA6
SA6
501
RCT~PE
SOl
501
WRTAPE 3
SOO
500
SOO
A=-8
~RTAPE
5
501
507.
507
506
506
S06
WRTAPE 6
A1
OA6*
OA6*
OA4*
OA4*
OA2*
OA2*
hRTAPE 1
SAl
SAl
WRT,6PE 1
SElAO
SElAO
5A5
SA5
SElAl
SEl Al
OA1*
OAI.
fOC*
ECG*
ROT APE 3
RCTAPE 3
A 8 1
W.l.
89879100
89879100
89819100
89819100
'89819100
89819100
89819100
69819100
89879100
89879100
89ii79100
89d19100
89879100
89819100
89319100
89879100
89819100
89879100
89819100
89879100
89879100
89819100
89879100
89879100
89879100
89879100,
89tl79100
89819100
89819100
89819100
89819100
89879100
89879100
89879100
89879100
89819100
89879100
89819100
8913 19100
89879100
89819100
89879100
89819100
89819100
89a 19100
89819100
89819100
89819100
89819100
89679100
89819100
o
7/8
FR. lEV TO.lEV
2
1
2
1
1
2
2
2
1
2
2
1
1
2
3
2
3
2
1
2
2
1
2
3
3
2
1
2
2
2
1
'1
2
2
1
2
2
1
2
2
1
1
2
2
1
2
1
1
2
2
1
2
1
2
1
1
2
2
2
1
2
2
1
1
2
3
2
"3
2
1
Z
2
1
2
3
3
2
1
2
2
2
1
1
2
2
1
2
2
1.
2
2
1
1
2
2
1
2
1
1·
2
2
1
89633300 A
PAGf NO
w I RE
21
FROM
13P1B02
LlPIB02
131>1803
13P1BO]
13P1804
131>1804
I]P1805
13P 180S
13PIB06
13P1806
11P180a
13P1806
13P1809
13P1809
13P1BI0
13P1 81 0
13PUHO
13P1B12
13P1812
13P1812
13Pll:H3
13P1813
13PIB13
13P1814
13P 1814
13Pl81S
13P1 R15
13P1815
l3Pl816
13P1811
13 P 1816
13P1819
13P1B19
I1P1820
13P1820
13P1821
13P1 A21
13P1822
11P 1822
l1P1B23
13Pls23
13P 1824
13P1825
13P182S
13P1B27
13Pl B28
13P182Q
13p1829
IlP1830
13Pl Bl1
13P2AO 1
TO
11P1A04
14P1 AD'
12PIBC7
14PIAO~
14Pl60ft
11P1AOA
laPI A02
CSP1B2~
I1PIB04
14Pl AO~
18PIAOQ
OSPIB21
12P21H9
14P1AOQ
21P1AOl)
05plS0'
lSP2R2lt
16P2A21)
05P1A06
21P1806
27Pl AOA
05PIAOt
18P2824
l2PIR20
l4P1814
21Pl A,)1
18P2 A23
0t;P1A07
IlPl A20
14PIA17
I2P1808
01P1 AOI
15P1AOl
15P1803
01P180l
07PlA06
15Pl AOe.
l2P2 A09
141>1A21
1RPI AOA
0'5P1826
12P1A30
18P1A06
05PIB3t
IlP1B26
12P2 R10
01PlAOl
15PIAOl
C8P280q
08Pl A03
12P2AO~
89633300 A
l
( S T
S tGNAl-NA~E
RCTAPE
RCTAPE
TRANS*
TRANS.
R[TAPE
ROTAPE
SAO
0
0
'1
1
SAO
R CTAP f 4
RCTAPE 4
SA4
SA4
lCLWA*
lOlWA*
S02
S02
S02
S03
503
S03
S05
S05
S05
8UF 1/0*
aUF 1/0.
S04
S04
S04
WRT'PE 4
CARCURAO*
INCC4*
OAS*
OA5*
OA1*
OA1*
OA3*
OA3*
STRBUF*
STRBUF*
SA3
SA3
9T*
SAl
SAl
WRTAPE 2
8USY
OAO*
OAO*
PE lOST CAT
PE ENABLE
CONTACT*
A B 1
w.L.
89!:) 79100
89879100
8S819100
89319100
89879100
89819100
89819100
89879100
89919100
69879100
89619100
89679100
89:119100
89879100
89879100
81879100
89679100
89679100
69619100
89819100
69679100
89819100
89879100
69879100
89819100
69619100
89879100
89819100
89879100
89819100
89879100
89819100
89879100
69619100
891319100
89819100
89919100
89d79100
eC;81910 0
89819100
89819100
89819100
89879100
89819100
89879100
89a19100
89819100
89319100
89879100
89819100
89819100
o
118
FR.lEV T D.l EV
2
1
2
1
1
2
1
2
2
1
1
2
2
1
1
2
3
3
2
1
1
2
3
2
1
1
3
2
2
2
2
2
1
1
2
2
1
2
1
1
2
2
1
2
2
2
2
1
2
2
2
'
2
1
2
I
1
2
1
2
2
1
1
2
2
1
1
2
3
3
2
1
1
2
3
2
1
1
.
3
2
2
2
2
2
1
1
2
2
1
2
1
1
2
2
,1
2
2
2
2
1
2
2
2
9-75
I)
AGE NJ
22
FROM
13P2A02
13P2A05
13P2A05
111)2A06
13P2A06
13P2A01
13P2A01
13P2A08
13P2A09
13P2A09
13P2AlO
13P2A 11
13P2A12
13P2A13
13P2A13
13P2A14
13P2A15
13P2Al1
13P2A18
13P2A18
13P1A19
13P2A20
13P2A20
13P2A21
13P2A22
13P2A23
13P2A24
13P2A25
13P2A26
13P2A26
13P2A27
13P2A28
13P2 A28
13P2A29
13P2A30
13P2BOI
13P2801
13P2.B03
13P2804
IlP280S
13P2806
13P2B06
13P2B01
11P2B08
13P2809
13P2BIO
13P2Bli
IlP2B12
13P2B13
13PlB13
11P2B14
9-76
W ( R E
TO
12PIA05
08P1818
14P2A17
11P281Q
12P1810
12P2A15
14PIAJl
14Pl A30
12P2AO'
14P2A04
12P2B09.
12P2818
12P1804
14P2801.
12P2A08
11PIA17
II P2 B31
12P2A 13
14P1823
11p2817
14P2A24
12Pl A23
14P2830
OAP2A24
11P2814
12PIA 16
08P2A21
I?P2 A15
I1PIA28
14P2Alt
14P28lt
14P2B05
12P1819
Oap2A14
08P1813
14P2819
12P2Al?
14P1B30
12P2S13
I1P18011)
14P2823
OSPi80'
10Pl AOt
08P2812
12PIAl'
12P1Ali
21 P2 A27
11PIA 30
12P180&
14Pl 81 'IlPIA03
L [ S T
A 6 1
SIGNAL-NAME
W.l.
ClR LOwER*
WREQUEST.
.. REQUEST*
~RI TE CLOCK
WRITE CLOCK
STRUS
STRUS
WPENABlE
MC*
MC*
STRINT
RFS1*
LOST CATA
EOP
EOP
BCD
MODE5El·
READY
P'R ERR.
P"~ ERR.
TTDENSTAT*
C5A WPEN.
OSA WREN*
Al2
R~LC R.. UNLO
LOS r" OA TA*
151PS
PPOTECTEO
9'
9T
li 51
RES2*
RES2*
PECHARClK
P EClOCK.
BOT
LEGLS
IllUSCODE
SlRCC
1600
PE ST'RT
PE Sr'RT
PC 1600*
PE WOPNING
hOS SHIFTED
EARl Y .. OS
Me*
lFWC
AID
AID
DATA
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
898'19100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89379100
89819100
89879100
89819100
89879100
89879100
89819100
89819100
89879100
89819100
89819100
89819100
89879100
89819100
89819100
89819100
89879100
89819100
d9879100
89819100
89819100
89879100
89819100
89819100
89879100
89819100
89819100
89879100
89819100
89819100
89819100
o
118
FR .lEV TO.LEV
2
2
1
1
2
2
1
2
2
1
'2
.2
2
1
2
2
1
2
2
1
1
2
1
2
1
2
2
2
2
1
1
1
2
2
2
1
2
2
2
2
1
2
2
2
2
l
3
2
2
1
2
2
2
1
1
2
2
1
2
2
1
2
2
2
1
2
2
1
2
2
1
1
2
1
2
1
2
2
2
2
1
1
1
2
2
2
1
2
2
2
2
1
2
2
2
2
2
.3
2
2
1
2
89633300 A
PAGE N1
WI R E
23
FR)f14
13P2SIS
I3P2B 16
13P2BI6
13P2R11
13P2817
IlP2B18
13P2B18
13PlB19
13P2820
13P28l0
13Pl822
13P2823
111'2824
13P28lS
13P2826
I1P?826
13P2821
13P2B28
14P LAO 1
14Pl A02
14PIA03
14PIA04
14P1 AOS
l4PIA05
14P1A06
14PI AO 7
14P lA08
14Pl A08
14PIA09
14P lA10
14PIAIO
l4PlAlO
l4PlAl1
14P1A12
l4PlA12
1le-PIA1Z
14PIA13
14PIAl4
14PlAl4
14PIA14
lle-PlA1S
Ift.PlA1S
14PlA1S
14PIA16
14PIAl7
14PIA18
14PlA18
Ift.P1A19
14PIA19
14PIA20
14P1A20
89633300
TO
I2P? Bt&
llP2B2C}
l4P2A lC}
14P2 A?q
IlPIAI1
14P1B24
11 P2 B11)
14P2A2~
12PIB2R
I4P2829
12PIB16
14P2827
I2P2Al0
14P282R
14P1Bl'i
12P2831
14P2B09
14P2A1R
l3P1BOl
13Pl BO'
l1PIBOl
13PIA04
18Pl A07
eSPIA21
13P1B06
12P181.6
1APlBOI
05Pl A27
13PlB09
19P2A30
05P1806
27PIBIR
llP1827
27Pl AIR
OSPlA05
18P2831
11 PI 820
27PIAIQ
18P2830
05Pl All
05P1810
18P2A2Q
l7Pl82'
llPl~ 25
13Pl B17
07PlR09
15P1809
15PIAll
C7PIAl1
07PIAOl)
15P1 AOI)
A
LIS T
SIGNAL-NAME
INT
TM3
TM3
REO*
REO*
fM/TM
fM/TM
TfREAOV*
ENA*
ENA*
ALI
EOT*
TM1
G~P CLOCK
R~LO*
R~LO*
usa
TT REAO,{
ROT APE 3
ReT .PE 0
TRANS*
ROTAPE 6
SA8
SA8
RCTAPE 4
RESl,1·
SA12
SA12
LOLWA*
5010
SOLO
SOLO
WRTAPE 11
SOLI
SOLI
SDll
WRT.PE 13
S015
S015
S015
S014
S014
S014
WIHAPE 14
CARCURAO·
O~13*
OA13*
OAlS*
OAlS.
OAl1·
O~ll*
A
~
W.L.
89879100
89879100
89979100
89819100
89819100
89;319100
89819100
89879100
89379100
89879100
89819100
89879100
89879100
89879100
89319100
89879100
89879100
89il19100
89819100
89879100
89819100
89879100
89879100
89879100
89d 79100
89819100
89819100
89879100
89879100
89879100
89879100
89879100
89879100
89819100
89879100
89819100
891) 79100
89879100
89879100
89879100
89879100
89879100
89379100
8C;S 79100
89879100
89879100
8913 79100
89879100
89879100
89379100
89879100
1
o
118
fR.LEV TO.LEV
2
2
1
1
1
2
I
1
2
1
2
L
2
1
1
2
1
1
1
1
1
1
1
2
1
2
1
2
I
3
2
1
2
1
2
3
2
1
3
2
2
3
1
2
2
2
1
1
2
2
1
2
2
1
1
2
1
1
1
2
I
2
1
2
1
I
2
1
I
I
1
1
1
I
t
1
2
1
2
1
3
2
1
2
1
2
3
2
1
3
2
2
3
1
2
Z
2
1
1
2
2
1
9-77
PAGf NO
24
FROM
14PIA21
lltPI A22
14P1422
14PIA23
14PIA2]
14P1424
14PIA25
14PIA26
14P lA26
14Pl A21
14Pl A2 8
14PIA30
14Pl A31
14PIBOI
14PIB02
1ft-PI 803
14PIR04
14Pl805
14P180.5
14PIB06
14Pl807
14P180A
14PIB09
14Pl B09
14PIBIO
14Pl810
Ift-PIBIO
14PIB12
14P1812
14PIB12
14Pl813
IltPIB14
14PIBl5
14PIBI5
IltPIB15
14Pl816
IltPIR11
IltPIBl8
14P1818
14PlfH9
14PIB19
14P1820
14PIB20
14PIB2l
14P IB22
14PIB22
14PIBl3
14PIB24
14Pl824
14PIB25
14PIB25
9-78
W I
TO
13PIR2?
18PIA07
05PIA24
OSP 1 A21.
lapl A01
11PIB24
13Pl A25
laP1404
05P lA 28
13PI A21
12 P2 AOft
1:3P2AC8
13P2A07
13PIAOl
12 P 1BOl
13Pl A01
13PIB04
18PIBO?
OS PI A25
I1P2Bll
13PIA07
11 PI Bll
lapIB04
OSPIA30
18P2A26
05PIB05
27PlS16
27P1814
05PIR04
18 P2 B21
12PIAOQ
13PIB14
21Pl A20
lAP2A2A
05Pl A04
11PIB21
13PIA13
07Pl BI0
l5PIRIO
l5PIA04
07 PI AO~
01PIROI.
ISPIROI.
11 PI B2~
C1PIROS
15PIB05
13P2AIA
13P2BIA
12P2A17
1APlAOt
OSPIA31
R f
l
1ST
SIGNAl-NAfilE
STRBUF*
SA9
SA9
SA 11
5 All
WRTAPE 15
SElAO
SA13
SA13
SElAl
CONTACT
WRENABlE
STRUS
RCTAPE 2
UPP)(I*
ROT APE 1
RCTAPE 7
SAI0
SAIO
TTONlINE*
RCTAPf 5
WRT4PE 8
S414
5414
509
509
S09
S08
508
508
LAST WORD
BUf 1/0.
5012
·S012
5012
WRTAPE 12
A=R
OAI4*
OAI4*
OAI2*
0,\12*
OAlO*
OA"10*
WRT4PE 9
OA9*
OA9*
P~R ERR.
FM/TM
FM/TM
SA15
SA 1 c;
.
4 B 1
W.l.
89d 79100
89819100
89879100
89879100
89819100
89879100
89879100
89d 79100
89879100
89879100
89819100
89879100
89d79100
89879100
89879100
89879100
89879100
89879100
89879100
89879104
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89819100
89879100
89879100
898791.00
89879100.
89879100
89879100
89879100
89879100
89879100
89879100
89819100
89879100
89879100
89879100
89879100
89879100
89819100
89879100
89879100
89879100
89879100
89879100
o
118
FR .lEV TO.l EV
1
1
2
2
1
2
1
1
'2
1
2
2
1
1
2
1
1
1
2
1
2
.1
2
3
2
1
1
2
3
2
1
1
3
2
2
2
2
'I
1
2
2
1
2
2
1
2
2
1
1
2
1
1
2
2
1
2
1
1
2
1
2
2
1
1
2
1
1
1
2
1
2
1
2
3
2
1
1
2
3
2
1
1
3
2
2
2
2
1
1
2
2
1
2
2
1
2
2
1
1
2
89633300 A
PAGF NO
w I R E
25
FROM
14PI 826
14P 1 826
14Pl B2b
14PIB?1
14P 1 B29
14PIB29
14PIB30
14PIB31
14P~ AOI
14P2A04
14P2 A01
14P~ A09
14P2Al3
14PZAt4
14P1Al1
14P2Al9
14P2 A21
14P2A22
14PlAl3
14P2A24
14PZA25
14Pl A21
14P2A28
14P2A29
14PlA30
14P~ROl
14P2802
IltP2803
Ilt-Pl805
Ilt-P2806
14P7.807
14Pl808
llt-Pl B09
14Pl810
Ilt-P281l
Ilt-P28l2
14P~8l3
14P2811tllt-p2815
14P2816
1lt-PZS17
l4P2618
Ilt-P28l9
llt-Pl820
14P2822
14P2823
Ilt-PlB24
14P2825
l4P?826
14PZ827
l4P1828
89633300
Tl
18P2BZQ
OC;PIBOQ
21PIBll
11PIAlh
01PIR04
15PIB04
13PlB01
IlPlBll
08Pl AIR
13PlA09
12P2810
12 P2 BO~
tlPIAO?
11PIAI0
13PlAOC;
13P2Blh
llPl Al6
I1Pl82R
13P2R19
13PlA19
12p2BOt;
13PIA1t
13Pl8lR
13P2Bl1
08PIA01
13P2All
11P2801
11 Pl8ZR
13P2A28
08P21ll0
12P2 AOI
l2PlB01
l3P28l1
12P2407
13P2A21
13P2813
12P1802,
08P1AZIt11P2 Blf»
12Pl821
l2PIAl1
08Pl A20
13P2801
08P1AZ1
12 P' A0"
l3P2R06
lZP2806
12P1824
12P28l1
13P2871
13PZAl'»
A
t
I S T
SIGNAL-NAME
S013
S013
SD13
~RT~PE
1C
OA8*
OA8.
I tLl SCODE
l EGCC
PE EOP*
MC·
BUSY
USA
PROT FAUt T
LCCKOUT*
WFECUEST*
TM3
'IT
R .. UNLO*
TTR EAOY* .
TTOENSTAr*
RMOT.
EOG*
TT READV
REO*
PWID
EOP
SEOP*
Fill
RES2*
REV.
STRMF
A7
USO
lEGCF
USl
AID
STO.P~R.ERR
[e ABORT*
RWLO*
STOP*
TTBUSY.
SFM*
801
PRP.OT
LEGMF
PE START
WMOT*
"FM/T~*
GC128
EOr.
GAP CtCCK
A B 1
lII.l.
o
118
FR.LEV TO.lEV
89819100
3
89819100
2
1
2
2
1
1
1
1
1
1
I
1
1
I
1
1
1
1
1
1
1
1
1
1
1
1
1
1
89819100
89819100
89879UiO
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89879100
89819100
89819100
89819100
89819100
89819100
891319100
89819100
89819100
89:1 79100
89819100
89819100
89819100
89879100
89879100·
89819100
89879100
89679104
89819100
89679100
89879100
89819100
89819100
89879100
89819100
89879100
89879100
89879100
89879100.
89879104
89879100
89379100
89879100
8C;S 79100
89879100
89879100
89819100
89879100
89879100
3
2
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
t
1
I
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I
1
1
1
9-79
PAGE NO
26
FR()N
14P2829
14P2830
14P2831
15Pl AOI
ISPIAOl
15PIA02
15PIA02
15PIA03
15PIA03
15PIA04
15PIA04
lSPIA05
15PIA05
15PIA06
15Pl A06
15PIA07
15PIA07
15PIA09
15PIA09
15PIAll
15PIAlI
ISPIA12
15Pl A12
15Pl A13
15P lA13
l5PIAl4
15PIA14
15PIA15
15PIA15
lSPIA16
ISPIA16
15PIA17
15PIAl7
ISPIA18
15PI~18
ISPIA19
lSPIA19
IljPlA20
15PIA21
ISPIA21
lS~IA22
.15PIA22
15PIA22
15P1A23
15PIA31
15P1801
15P1801
15P1802
ISP 1802
ISP1803
9-80
W I
TJ
R E
liS T
SIGNAL-NAME
A B 1
W.L.
o
7/8
fR.lEV TO.lEV
13P2820
13P2A20
12PIA21
19PIA19
13P1819
13PIA19
19PIA11
19PIA30
13P1829
14P1819
19PISOA
19P1812
14Pl A20
13P 18 21
19PIA26
19PIB18
13Pt.A20
21P2828
07PIA09
19P1801
14Pl A19
12P1831
19P1 A2B
01PI All
19P2801
20P2801
C1PIA14
07PlAl,)
20P2A14
12P2823
01PIA16
07.pl Al1
12P282'26P2A24
01Pl AIR
C7PIA19
26P2825
ENA*
DSA WREN*
STOP OIST.
OA5*
OA5*
OA6*
OA6*
OAO*
OAO*
OAI2*
OA12*
OAl1·
OAll*
OA3*
OA3*
OA4*
OA4*
T.P.
T.P.
OA15*
OA15*
00
00
02
02
04
04
06
06
08
08
010
010
012
012
014
014
89819100
89879100.
89879100
89819100
89879100
89819100
89819100
89879100
89879100
89879100
89879100
89879100
89879100
89819100
89879100
89879100
89879100
89879100
89819100
89819100
89879100
39879100
89819100
89879100
89819100
89879100
89879100
89879100
89819100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89819100
1
1
1
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
I
1
2
2
1
1
2
2
1
1
2
2
1
1
2
1
1
1
1
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
I
1
2
2
1
1
·2
2
1
1
2
2
1
1
2
2
1
21P2830
19P1802
.12P1829
19PIA03
07PIA2?
12P2814
15P2828
16Pl A08
19PIB26
13PIA30
13PIA21
19P1824
19P1816
WEI*
READ*
READ*
REPlY*
REPlY*
REPl y*
PRTAO.
8l=0
OAl*
OAl*
OA2*
OA2*
OA7*
89819100
89879100
89819100
89819100'
89879100
89879100
89879100
89879104
89879100
89819100
89879100
89879100
89819100
2
2
1
1
2
3
3
2
2
1
1
2
3
3
2
1
1
2
2
2
1
1
2
2
~
.
89633300 C
PAGE- NO
27
VI
T(l
FROM
15PIB03
15P1804
15PIB04
15PIB05
1 'i Pl B05
l5PIBOb
15PIBOb
l'iPlB07
15PIB07
15PIB09
15PIBOq
15PIBI0
1'j PI B10
15Pl fH2
15p 1 B12
15PIB13
15PIA13
15PIB14
15PIB14
15PIBl5
15PIB15
15PIB16
15PIB16
lSP1R11
15PIB11
15p 1 B18
15PIB18
15Pl B19
15 P IB19
15PIB21
15P1B21
1,)PlS22
15Pl B22
15P1B7.2
lSP1823
15PIB23
1 ,)P 1 ~2 3
15PlAO 1
lSP7.402
l5P2A04
15 P2 A05
1SP2406
15PlA01
15P~ AOS
15P2A09
15P2A09
15P7AI0
15P 2AIO
15 Pl All
15P2A12
15P 2A13
,RE
LlPl B;>O
14PIB2Q
1 qPl A1 c; .
'I qp 1 A11
14P1 B7J
14P1B20
19P1A14
20P2 Bl5
12PIB21
14P1A1A
1 qPl A07
19P1 ~ 01
14P1BIA
12P2BOl
C7PUH2
07Pl Bl1
25PIBOq
20P2Bl'i
01 P1 Bl4C7P1B15
12p2 A24
12PZ A2l
07PIB16
01P1B17
2bPl BOq
26P2B2A
01P1BIA
o1PlI:nq
26P2BOl
12PIB30
19P2B 31
01Pl!}2?
12P2 Al41 qPIBOl
16PZ B07
07Pl B21
25PIB20
18Pl B05
1 qPl Al~
16PZAOA
19PJ.A24
16P1J:\04
19P2 A30
18 P2 A2'
lZP2!i21
lOP2 B14
2 OP2 SIS
17P2fJ27
16P2 A09
1 7P2 Al 7
17P2820
89633300
A
L I
S T
SIGNAL-NAME
OA7*
nA8*
OA8*
OAQ*
OA9*
OA10*
OAIO*
CHI*
CHI*
OA13*
OA1.3*
OA14*
OA14*
01
01
03
03
05
e5
07
07
09
09
011
011
013
, 013
015
015
WRITE.
WRITE.
REJ EC T*
RfJ ECT*
REJECT*
Me*
~C·
MC*
SElO.UTPI1O
SE.U.PRT.
US).
' Of-GATED
UlT.S~C.PPO
BUSY RR*
C /J6
08
08
010
010
US2*
A13
All
A 8
tJ.L.
893791()O
89879100
89819100
89819100
891179100
tl9879100
89919100
89379100
89819100
89819100
89819100
89819100
89879100
89d 79100
89879100
89879100
89879100
89879100
89819100
89319100
89879100
89879100
89819100
89319100
89819100
89819100
89819100
89819100
89879100
89819100
89d19100
89819100
89819100
8~819100
89679100
89819100
89879100
89819100
89879100
8<;819100
89819100
89819100
89819100
89879100
89819100
89~ 19100
89319100
89819100
89819100
89879100
8'1819100
1
o
7/A
FR .L EV TO. L EV
1
1
1
1
2
2
2
2
1
1
2
2
1
1
2
Z
1
1
2
2
1
1
2
2
1
1
Z
2
1
1
2
2
1
1
2
1
3
1
1
2
3
2
1
1
Z
1
1
2
Z
1
1
Z
I
Z
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
Z
2
1
1
2
2
1
1
2
2
3
1
I
1
)
2
Z
1
2
1
1
Z
2
1
1
2
1
Z
2
9-81
P~GE
NO
,28
FROM
15P2A14
151>2A15
I'5P2AI6
15P2Al7
15P 2A18
l5P2A19
15P7.A20
15P2A21
15P2 A22
1 5PlA2 3
15PlA24
15 P2A25
15P2A26
15P2A21
15P7A28
151>2A29
15PlBO 1
15P2B02
151>2803
15P2B04
15P7A05
15P2B06
15P2B01
15P2B08
15P2B09
15P2809
15P2BI0
15P2810
15P?8l1
15P2B12
ISP2813
15PlB14
15P2815
15P2816
15P2811
15P2818
15P2819
15P2820
15P2B20
15P2822
151>282'j
15P2824
15P7.B25
15P2826
15P2B21
15P2B28
15P2B28
15P2B28
15P2B29
15P2S10
l'iP2831
9-82
WI R E
fJ
1 7P2 A0417P2Bll
17PlA21
18P~ BO~
16PIB31
19P1 BOl
19P2810
16PIA20
17P2802
I1P2A06
19P1827
19P1 A21
16P2406
16P2402
l6PIB21
19P1 AOq
15P2820
16P280416P1829
18PIA19
I1P2B14
16PIA06
19P2 A28
16P2A01
20P2A06
12P2 AZ\12P2A21
20P2Alf.
16P2 AI4I1P2A16
11P2819
I1P2A15
11P2BOl
11 P2A08
17P2Bl'
16PIA19
16Pl A21
16P lA 7.7
15P2 BOl
16PIAI416PIB23
19P2 A07
1 QPl A27.
16P2404
16P2AOI
21P2A2R
12P2A19
15Pl A23
16PIB20
16PIB27.
16Pl A2~
l
I
S T
A B 1 o 1/8
SIGNAL-NAME
W.l.
AO
At;
AI0
CA6SM*
A /0 CLE~R
ECU .NUM.MAT
89879100
89879100
89819100
89819100
89819100
89819100
89819100
89879100
89819100
89819100
89'S 79100
89819100
89879100
89819100
89d79100
89819100
89819100
89819100
89879100
89819100
89a 19100
89819100
89819100
89819100
89879100
89a19100
89319100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
eC;819100
89319.100
89819100
89819100
89819100
89879100
89819100
89819100
89819100
89379100
89819100
89879100
89819100
89819100
89819100
89819100
PCKM
T.E.O ALTOl
A2
A3
SCOSEO
SCOSE2
SEO SCI lit
SEO SC3*
AOAF+MC*
AODR ERR
RESCTRBSY.
LA OIFF=O*
EOPMC T 8SV*
S ET • AC() R • ER
A8
READ
LA
US4*
07
01
09
09
USl*
A14
A12
A15
Al
A1
AA
MC
T AS EX T •
RESC TRBSV*
R fSeTRBSV.
TDl
I NCR 1A
seOSE 1
SCOSE3
SEOSC2*
SEOSC4*
PRT~Q*
PRTAO*
PRT ~O*
TD2
ADOR. ERR.
CTRLR BlSV
FR. LEV fO.LEV
2
Z
2
2
2
1
2
2
2
Z
Z
2
Z
1
2
2
2
1
2
1
2
2
2
1
1
2
1
2
1
1
2
2
2
2
1
1
7.
2
1
1
2
2
7.
1
2
2
2
1
1
2
1
1
1
1
1
1
1
2
3
1
1
1
2
1
1
2
1
2
1
1
2
2
2
2
1
1
2
2
1
1
2
2
2
"
,
1
2
2
2
1
1
2
1
1
1
1
1
1
1
2
3
1
1
1
89633300 A
PAGf NO
W I
29
FROM
16PIAOl
1&P1A01
t6P lA02
16PIA03
IbPIAO'l
16P1A04
16PIA05
16PIAOb
16PIA06
IbPIA01
16PIA08
16PIA08
16Pl A09
16PIAIO
16PIAI0
16Pl All
16PIA12
16Pl Al 3
16P1A14
16PIA14
16 P 1A15
16PIA16
16PIA17
16PIA18
16PIA19
16PIA19
IbPIA20
16P lA21
16PIA22
16PIA23
16P lA25
16PIA26
16PlA26
16PIA21
l~Pl A21
l6PIA27
16PIA28
16Pl A30
I6PIA31
16PIBOl
16PIB03
16P1803
16P1B04
16PLB05
16P1805
1~PIB01
16PIR08
16P1809
16Pl Bt 0
l6PIB12
16PlB13
TO
12PIAlO
27 P2 A2R
17PlfHQ
27PIB2Q
12 P2 Al R
12P2B2l)
laPl All
15P2 BO'17PIR30
18P2B04
17PIA14
15PIA .31
11P1810
12PIA14
21P28lR
I1Pl B01
17P2B 1l
18P2AIA
1 7Pl B28
15P2B22
l8P2B2'
I1PIBlr;
11PlA21
17Pl A12
I1PIA22
15P2B18
15P7. A21
15P2BIQ
19P2A18
18P2 A01
19P2B2Q
15P28.11
19P2 AOR
L9P2B19
19P2 BIC)
15P2B20
19PIB30
L9P2 414
19P1A15
12P2Al1
12Pl B2l
21P2A 19
15P2 A06
21PIB31
12PIAL9
19PIA24
lR P 2A.21
11PIAli
11P2 Alft.
I1Pl R 11
11Pl A24
89633300 A
R E
L 1ST
SfGNAl-NAP'E
SRQ*
S .. O*
W+C
SPI*
SPJ*
SCF 00 ( SC F I M
REOUEST.
REAO
READ
OSA-BUfFl·
BL=O
Bl=O
CAl-StHFT*
S~SM*
SRSM*
RESUME
TD4
SMP )CO
TOI
TOI
BuFF1SUfF2·
BUFFI-BUFF2
T03
SET NEfO*
Me
MC
T .E.C AUTOl
TAS EXT.
LOST [ATA
Bl>CYL
SET ALARM.
C TRLR BUSY
C TRlR BUSY
RESET CTR B
RESET eTR B
RESCTRB5Y.
OOF-LA-AlHO
SET CTR SEE
T01·
SCRODe SCR 1M
ss*
S5*
UlT.SAC.PfOO
S WRITE*
S WRf TE*
OS#\ ceNNECT
WRITE ENABL
SHI.FT-BUUfl
I NH IB IT NEE
168 [ T 5. ell
CAU SHIFT.
AB 1
vi.l.
89d79100
89379100
89879100
8<;81<;;100
89819100
89d79100
89879100
89819100
89879100
898.79100
898191uO
89879104
89819100
89819100
89d 19100
89819100
89819100
89819100
89!J 19100
89619100
89819100
89819100
89a 19100
89819100
89819100·
89619100
89819100
89d 19100
89819100
89819100
89819100
89819100
.89819100
89819100
89819100
89819100
89819100
89819100
89319100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89619100
89819100
89819100
89819100
89819100
o
7/8
FR.l EV TO.l EV
1
2
1
2
1
1
2
2
1
2
1
2
1
2
2
2
1
1
1
1
2
1
1
1
1
2
1
1
2
1
1
2
2
2
1
2
2
1
I
1
2
1
2
1
2
2
1
1
2
1
1
2
1
2
1
1
2
2
1
2
1
2
1
2
2
1
1
1
1
1
1
1
1
1
2
2
1
1
2
1
1
1
2
2
1
2
2
1
1
1
2
1
2
1
2
2
1
1
1
1
9-83
PAGF
~O
30
FROM
16PIB14
16P1815
16P1816
16P 1819
16Pl B20
16Pl820
16P 1821
16P1811
16P1822
16P1823
16P182)
16P1824
16Pi825
16P1826
16PIB27
16P1828
16P1829
16P 1829
16P1830
16P1831
16PlAOl
16P1A02
16P2A04
16P2A06
16P2A07
16P2A08
16P2 A09
16P2A14
16P2801
.~P1802
...16p2S03
loP 2804
16Pl805
16P?806
16P2807
16P2808
16P2809
16P2810
16P2811
16P2812
16PZB13
16P2814
16P2815
16P2816
l6P?817
16P2818
16P28L9
16P2820
16P2822
16P2823
16P2824
9-84
W [
R t:
L 1ST
TO
SIGNAL-NAME
lRP2819
17P181A
1 7P2 All)
18P2A 11)
17PIAlO
15P2829
17P1809
15P2 A2B
15P2R30
1l)P2R21
18PI A31
19P2821)
17PIA06
19P2 A16
19PIB2A
18P2820
1l)P2 BOl
19P 18 31
19PIA20
1l)P1AIA
1l)P2B21
15P2 A21
15P2B26
15P2A16
15P280A
15P2A04
1l)P2Ali
15P2BlI
19P2A2A
18 P2 807
.17P2lJOI)
15P2BO?
19P2S06
17P1829
15PIR21
10P182()
1 QP2A 17
lAP2A12
19P2 A20
1 QP2824
17P2A27
1 AP2A04
18P 1 AOI)
17PIB27
17PZR11)
18P2 A09
18P2 BOt.
SMP Xl
BUfF2 fULL*
011
LOAD SH(f T*
T02
T02
AOAF+MC*
AOAf+f4C*
AODR.ERR*
(NCR lA·
I NCR lA
ADDRESS ECP
EOS
T02*
I HI T Q
MC*
EOPMCT BSY*
EOPMCl BS.,*
EOP
A/Q CLEAR
SEOSC4*
SEOSC3*
SEOSC2*
SE~ SC ••
US4*
US3*
US2*
US1*
LA
ARCUR-CA·
eN
LA DIFF=O*
CLf'R CONTR
AUTOLOAD2*
18P2AO~
CA13*
WR ITE GATE·
DRIVE fAULT
DRI VE SE*
17P2B21
19P2 B2l
19P2Al'i
e'fa.
~C*
AUTOLOAD
INDEX GATEIl
SECTOR GA Tt:
DRIVE RIl.
PUR*
R+W+C+CC
CAl c;*
CA20*
WRITE C,T,*
READ GAlE.
CA1*
CA65~*
A B 1
w.L.
89879100
89879100
89879100
89879100
89819100
89879100
89819100
89d79100
89879100
8981.9100
89879100·
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89819100
89879100
89879100
89879100
89879100
89879100
89879100
89819100
89819100
89819100
89879100
898"19100 .
89879100
89879100
89879100
89819100
89819100 •
89879100
89379100
89a 79100
89879100
89819100
89879100
89819100
89379100
89879100
89d 79100
89319100
89879100
89819100
89819100
SC;819l00
o
7/8
fR .LEV TO.LEV
2
1
2
2
2
1
1
2
L
1
2
1
1
1
2
1
1
2
2
2
1
1
1
1
1
1
1
2
1
2
2
2
1
1
' 2
1
1
2
1
1
1
1
1
1
1 ..
1
1
1
1
1
1
1
1
1
1
1
1
1
·1
1
1
1
1
1
1
'I
2
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
L
89633300
A
P4.GE "'40
31
\of
FROM
R r
L I S T
SIGNAL-NAME
TCl
W.L.
FR.LEV TO. LEV
18P2A17
89819100
89819100
89819100
89819100
S9B 79100
89.3 19100
89319100
89879100
1
1
I
1
1
1
1
2
1
1
1
1
1
1
1
2
11PlA06
·11PIA08
17P1A09
17iJIAI0
l1PIAll
I1PIA 12
16PIB25
18PIB2A
19P2 AO&
19P 1817·
18P2 All
16Pl AlR
EOS
CWA-COUNT.
leL*
D.NO.CCMP.
R+W+C
SET NEED.
89819100
89879100
89819100
89879100
89819100
89379iOO
1
2
2
1
1
1
1
2
2
1
1
1
I1PIA14
11P.lA15
I1PIA16
I1P1A17
17PIAIA
11PIA19
11Pl A20
17PIA20
I1PIA22
11P1A22
I1P1A24
> 17PIA24
17PiA25
17PIA21
17PlA28
11PIA30
17Pl A31
11PIA31
I1P1803
I1P1S06
17PIB07
17P 1809
l l P IB09
17PlslO
17P IB14
I1P1815
17PIB16
11PIB11
17PIB18
I1PIB19
17P1819
11PIB22
17i)lB24
I1PIB27
11Pls28
16Pl A08
19P2AOq
,l8PIB31
19P2 A2l
19P2A13
19P2B20
18P2810
16Pl820
18Pl B2')
16Pl Al 9
16PIB11
19P2 A29
l8P2A12
19PIA21
19P182l
18PIA13
16PlB09
18P2 BOli
18P2A16
19PIB29
16PIAll
19P2B03
16 Pl B21
16PIA09
18P2B13
16PlA16
19P2A12
lapl A'27
16Pl 81 ')
16PIA02
18P2A19
18P2S17
19P2Aor;
16P2816
16PIA14
8L=0
DOf-LA
.DOF
IN(T
CLEAR CKWO*
READ OATA
T02
T02
MC
MC
CAU SHIfT.
CAU SHIFT.
SECTOR GATE
W.CKWO·
INPUT CKWO
Bl-BORAO"·
SHlfT-BUUFI
SHlfT-BuUFI
S15
CKWO SHIfT
RESUME
AOAf+MC·
AOAF+MC*
CAL-StilfT*
DATA
8UFf1-BUFf2
(CMPARE
BL-LOAO.
BUFF2 FUll*
W+C
1
1
2
2
1
1
1
2
2
1
1
2
1
1
2
2
2
2
1
1
2
2
2
2
2
1
2
2
1
1
2
2
TOI
89879100
89879100
89819100
89879100
89819100
89879100
89819100
89879100
89819100
89879100
89879100
89879100
89819100
89819100
89819100
89879100
89879100
89879100
89879100
89819100
89879100
89819100
89819100
89819100
89819100
89879100
89819100
89819100
89879100
89819100
89819100
89379100
89819100
89819100
89879100
2
1
1
2
1
2
1
2
1
2
1
2
17P 1A25
19P2B15
SECTOR GATE
89879100
3
3
>
18P280Q
19P2Bll
18P2811
18P2AIO
lAP2AO,)
"18P2AOl
A 8 1 o 7/P,
CA1J*
LA CLEAR*
CA12*
CA15*
CA11*
CAI8*
CA16*
511
16P2B25
16P2826
16P2821
IbP2828
IbP1B29
1&P2B30
IbP2831
17PIA04
SEE
BElOH
I
18P2BO~
89633300 c
.
W+C
CLEAR-SHIfT
CKWDll
w~ITE tATA.
2
2
2
2
2
2
1
1
1
2
2
1
1
2
2
2
2
1
2
2
2
2
2
1
1
2
LENGTH 99-85
P&\GE NO
32
FROM
I1P1829
I1P1829
11P1830
17 P1830
17P1831
I1P2AOI
17P2AOl
11P'A02
I1P2t,)2
I1P2 AOft
17P'A04
17P2A05
17P2·A06
17P2A06
11P2A01
17P2A08
I1P2A08
11P2A09
17P2A 1'0
I1P2Ali
17PlAll
11P2A12
17P2Al2
17P2A13
17P2A13
17PlA14
17P2A15
I1P2A15
17PlA16
17P2A16
17P2Al1
17P2A17
17P2A 18
17P2A19
17P2A19
11PlA20
17P2A20
I1P2A21
17P2A21
17PlA22
I1P2A23
17 P lA23
17PlA24
17P2A25
17P2A26
17P2A21
17P2A21
17PzA28
17P2801
11P2S02
I1P?' 802
9-86
W .1
TO
19P2812
16 P2 80r.
16PIAO~
19P2All
l6PlR12
20P2819
19P1824
19P18~~
20P2820
15P2 Al~
l8PIA2'i
19P281~
15P2A21
18P1826
19P1801)
15PlRl&
lAP1819
lAPIA24
18P1R1"
19P181A
20P2A21
20P2824
19PIAll
19P1 All)
20P2821
16P1810
18P1811
15P2814
15Pl812
18PIR21
lAPIA2B
1 C)P2A11
1qP1AO'i
26P2A2l
19P1 ROA
19P181'
20P2 !32A
15P2Al"
18P1820
18P2816
IBP280'
16PIA17
19PIA2C)
16P1816
19P1822
1 9P2 827
16P2811
19P2822
lAP'- AO'
15P2A22
18Pl A26
R f
l
1ST
S·IGNAl-NAME
AUTOlOA02*
A1JTOlOA02*
REAO
READ
168ITS.OII
OA2·
OA2*
O.Al*
OA1*
AO
AO
AODRESS*
A3
A3
010
Al
A1
A6
. A5
OA4*
OA4.
OA9*
OA9*
OA8*
OA8*
IN~ 181T NEE
All)
A15
A14
Al4
A13
A13'
ADOR.CKWO=O
OA12.
OA12.
OA11*
OA11·
A10
A10
stHFT CLOCK
T03
T03
LOAD CKWC I
011
SAMPLE CHEC
A+W.C+CC
R +W+C+CC
WA-AOR
(NCR.SECTeR
A2
A2
A is 1
W.l.
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89879100
89879100
89819100
89819100
89819100
89879100
89a 79100
89879100
89819100
89819100
89879100
89879100
89819100
89(119100
89879100
89819100
89879100
89879100
89819100
89879100
89819100
89a19100
89819100
89a19100
89819100
89819100
89819100
8«;879100
89319100
89879100
89979100
89679100
89879100
8C;d 79100
89879100
89819100
89819100
89819100
89879100
89879100
o
118
FR.lEV TO.lEV
2
1
1
2
2
2
1
1
2
2
1
1
1
2
2
2
1
2
1
1
2
2
1
1
2
1
1
2
2
1
1
2
2
2
1
1
2
2
1
2
2
1
1
2
1
2
1
1
2
2
1
2
1
1
2
2
2
1
1
2
2
1
1
1
2
2
2
1
2
1
1
2
2
1
1
2
1
1·
2
2
1
1
2
2
2
1
1
2
2
1
2
2
1
1
2
1
2
1
1
2
2
1
89633300 A
PAGf NJ
,.
33
fRUM
l7P 2803
17P2R03
17P? B04
17P 7.804
17P2805
17P2R05
17P2806
17P' 806
11P2R01
I1P28l18
l7P2ROa
I1P2B09
11P2809
I1P2810
I1P2810
11P2811
I1P2811
I1P281l
11P2812
11P2R13
11P2B13
11P2814
11P2814
17P2815
I1P2816
17P2816
I1P1.817
11P2811
17P 2818
11P2818
11P2819
17P2R19
I1P2820
I1P2820
I1P2822
17P2822
llP2823
17Pl824
11P2828
18PIAOl
laPl AO 1
18P1A02
18P1A02
lAPl A03
lSPtA03
18Pl A04
18PIA04
18P lA05
lAPlA06
18P1A06
18P1A01
I
R F
TO
15P2B Pi
18PIB2Q
20P'-A20
1 C;P 1 A lO
16P260':\
19P2 A2'
20P2A17
19PIA26
19P1B07
20P2Al9
19P18lft
19PIA17
20PlBIA.
20P2821.
19PIA19
19P2B01
16Pl AI'
Il)PlBl1
18P1 A21
18PIA20
1 t;p 2 All)
1l)P2 BOI)
18PIR 1.1
16P2811
19P1 AOI
26P2A22
20P2All
19P1 A01
19P1801
26P2R22
15P2811
18P1A)0
18PIRZ,.
15P2Al1
20P282ft
.1 9Pl AI,.
16P282' .
19P2830
lQP2f.H\
14P1821)
21P2AOI
28P2A24
13P1805
l4Pl A2\
28PIR21
28P1A1l
14Pl A2"
16P2811)
lJP1825
28P1821
28Pl831)
89633300
A
L [ S T
SIG~AL-NAME
Al
Al
OAO*
OAO*
Ct\ CYl
ON CYL
OA3*
OA3*
R+C+CC
OA1*
OA1*
OA6*
OA6*
OA5*
OA5*
T04
J04
A·4
A4
At;
A9
·A8
A8
READ GATE.
OAI4*
OA14*
OA13*
OAI3*
OA15*
OA15*
A12
A12
All
All
OA10.
OAI0*
WRI TE GA TE*
ADDRESS 12·
WRITE
5A15
5A15
SAO
SAO
5 All
SAil
SA13
SA13
CA20.
SAl
SAl
SA8
A 8
W.L.
89819100
81}S19100
89619100
89819100
8'1819100
89819100
89319100
89819100
89819100
89d19100
89819100
89319100
89819100
891)19100
89819100
89cJ 19100
89819'100
89819100
89819100
89819100
89819100
89'319100
89819100
89819100
89819100
89819100
89319100
89819100
89879100
89819100
89879100
89819100
89879100
89819100
89819100
89879100
89cJ 79100
89819100
8-1819100
89819100
89819100
89819100
89:1 7910·0
89879100
8')819100
89/J 19100
89819100
89819100
89819100
89879100
8«;879100
1
o
71P"
FR .LI:V TO.LEV
1
2
2
1
1
2
2
·1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
1
2
2
1
1
2
2
1
1
2
2
.1
1
1
2
1
2
2
1
1
2
2
1
1
1
2
2
1
2
2
1
1
2
2
1
2
2
1
1
2
2
1
I
2
2
1
1
2
2
1
1
1
2
2
1
1
2
2
1
1
2
2
1
1
1
2
1
2
2
1
1
2
2
1
I
1
2
2
9-87
PAGE ·NO
SEE
BELOW
14
W [ R E
FROM
TO
18PIA07
18PIA08
18PIA08
18P1A09
18P1A09
18PIAIO
> 18P1All
18PlA12
18PIAl3
18P1A14
18PIAlS
18PIAl6
18PtAl7
18PIA18
18P1A19
18P1A20
18PIA2J,
18PIA22
18P1A23
18PIA23
18PIA24
18PIA25
18PIA26
18PIA26
18P1A27
18P1A28
t81ltA30
18PIA31
18PlA31
18PIBO 1
18PIBOI
18PlB02
18PIB02
18PlB03
18PIB03
18PIB04
18PIB04
18PIBOS
18P180S
18P1806
l4PI AO;
13P1823
28PIA06
28P1809
13Pl808
19P18l0
16PIAO;
19P1813
17PIA30
19P2B04
19P1A31
19PI All
19P1820
lCJP1804
15P2804
I1P2813
19P1 A21
. 19PIA18
19P2A27
17P2Bl2
17P2A09
17P2A04
11P2802
19P2A19
17P1817
17P2A11
17P2B19
19P2A26
16P1821
14PiA08
28PIB21
28P1A26
14PIB05
13Pl A21
28P2B25
28PIA30
14P180c)
lSP2AOl
·19PIA04
13P1A09
28PIA21
28P182c)
14P1A22
13PIA05
28plBOl
28PIA09
13PIA26
19P1811t
19PIA12
17P2A15
19P2A04
18PU~06
18P1807
18P1807·
18PlB08
18P1808
18P1809
lBP1809
IBP1810
18P1812
18Pl813
Pl8
>1 P1A f4
1
18
9-8.8
18P2B01
lIS T
SIGNAL-NAME
SA8
SA3
SA3
SA4
SAlt
CACWA9
REQUEST.
CACWAI0
8l-BO~POW*
ARCUR CWA*
CACWAO
CACWA12
CACWA3
CACWA15
SET.AOOR.ER
A9
CACWA4
CACWA6
A4
A4
A6
AO
A2
A2
8l-LOAD.
A13
A12
INCA TA
INCR TA
SA12
SA12
SA10
SA10
SAl
SAl
SA14
SA14
SElD.UTPII0
SEL D.UTP 110
SA6
SA6
SA9
SA9
SA2
SA2
SA5
SA5
·CACWA8
CACWAl1
A1S
CACWAI
REQUEST*
A 8 1
W.l.
89819100
89879100
89879100
89819100
89879100
89819100
89879100
89879100
89879100
89819100
89819100
89879100
89819100
89879100
89"819100
89879100
89819100
89879100
89879100
89819100
89879100
89879100
89819100
89819100
89879100·
89819100
89879100
89879100
89819100
89879100
89819100
89879100
89819100
89879100
89879100
89879100
89819100
89879100
89879100
89879100
89879100
89879100
89819100
89879100
89879100
89879100
89879100
89879100
89879100
89819100
89879100
89879100
o
7/8
FR.lEV TO.lEV
1
1
2
2
1
1
2
2
1
2
2
2
1
I
2
1
2
2
2
1
2
1
I
2
2
1
1
1
2
1
2
2
1
I
2
2
1
2
1
1
2
2
1
1
2
2
1
2
1
1
1
3
1
1
2'
2
1
1
2
2
I
2
2
2
1
1
2
1
2
2
2
1
2
1
1
2
2
1
1
1
2
1
2
2
1
1
2
2
1
2
1
1
2
2
1
1
2
2
1
2
1
1
1
3
LENGTH 8"
89633300C
PAGE NO
W I
35
Fi{OM
l8PlFH5
1~PIBI6
18P1B11
18P1818
18PIB19
18P1B20
18P1821
18P1B22
18 P IB23
l'iP1 B24
18P IB 25
18P1826
IBPIB26
18PI827
18P1828
TO
19P1A08
19PIB21
19P IA 06
1 7P2 AID
17P2 AD8
11P7.A21
19P1Blg
19PIBI~
18PIB29
18P1829
18PIB30
18111831
18PIB31
18P2AO I
18P2A02
18P7A04
lRP7A05
18P2A06
18P~ A07
18P2A08
18P7 A09
18P2A 1 0
18P2All
BP~ All
18P2AI2
18P2A12
18P2A15
181) 2A16
1HPl A17
18P2A18
IRP? A).9
IsP2A19
IRP;tA21
l!:JPlA22
181>2 A2 3
lAP2A24
laPlA25
18P7A26
18P2A27
18P2 Al8
18P2A2Q
18PlA30
11P281411P2820
1 7Pl A2l
I1P2A06
19P2 B28
I1P2A16
19PIB2S
17Pl AOR
17P2B03
19P2AIO
19P2B 11
17PIA16
19P2B08
16P2830
171>2801
16P'!. 81416P2B29
19P2 B05
16 PI A2~
16P2B20
16P2 B18
16P2B28
11PIAll
19P2B09
11PIA2'i
16P2/l10
16PIBIQ
17PIB03
17P1A0416Pl All
17P1819
19PZ AOI
16PIBOA
15P2A08
13Pl fU5
13PIA16
13p1311.
14Pl RIO
1:3PIAIO
14P1815
14Pl Al 'i
1-4PIAI0
18P2:l01
l8P 1 ~.11
18PIB~8
89633300 C
KE
l
A B 1
I S T
o
7/8
FR .LEV TO.LEV
SIGNAl-NA~E
W.L.
CAC~A 13
C ACWA2
CAC wAl4
AI)
A7
AIO
CACWA5
C AC wA 1
AS
All
MC
A3
A.3
Al-4
(liliA-COUNT.
C kA-CGUNT
At
Al
ADOT INDE)C*
OOF
DOF
CA18*
I NC R • SEC TOR
CA19*
CAL 7*
CAR ST*
Bl>CYl
CA13*
CA7*
CAIS*
R+k+C
R+W+C
SEC TOR GAlE
SEClOR GAlE
LOAn SHIFT*
515
Sl1
89319100
89879100
89879100
89::179100
89879100
89879100
89819100
89819100
8987
18PIB30
16Pl A27
16P1A27
I1PIA19
17P2 A2A
16P2821
16P2817
16Pl B2418P2820
I1P2A27
18P182&
16PIA25
ACORESS*
ADOT (NDt:)(*
RESET eTR B
RESET CTR B
READ CArA
I1P28Z4
ZOP2806
15PIB21
10P1819
ZlP2B31
26PZAll
Z6PZ Al1
25P2All
25P2B12
21 pl A2421P2A08
21PIA01
21PIA18
25P2814
26P1831
26P1828
25P1829
25P1828
22P2A17
22PIA19
21 Pl817
21PIBIR
24PIB01
21P2A2?
24P2AIO
30Pl821
21P1816
21PIA16
21P2A3I
26P2Bll
21PIA1?
26P2814
2SPIA2R
21 P2 82 7
2lP2A14
23PIA04
89633300 C
W~-ADR
DRIVE fAULT
PUR.
ADDRESS EOP
MC*
R+W+C+CC
A3
SET ALARM.
ADtRESS 12*
wRI TE.
WRITE*
AUTOLOAD
8EA
CNS5M*
CNS6M*
CNS5l*
CNS4l*
TMSW.
AUTRSW*
SlK*
PRGST
CNS1l.*
CNSCM*
CNS3M*
CNS2l*
CNS3l*
RIND
OPST·
SWEEP*
ENTER*
csp*
PCL*
CSO.
cePE*
I NT. SW.
STopes·
vee
CNS4M*
32KW
eNS 7M*
ClR EG*
MCCS*
PRTSW
CSPR
A 8
W.L.
8'1B19100
89 R7Cll 00
89879100
89819100
89819100
89819100
89819100
89879100
89879100
89819100
89879100
89879100
89879100
89819100
89879100
89879100
89879100
89879100
89879100
89819100
89879100
89819100
89819100
89879100
89819100
a'7a 79100
89819100
89879100
89879100
89879100
89819100
89819100
89819100
8-;879100
89879100
89879100
8987910.0
89819·100
8987.9100
89819100
89819100
89879100
89879100
89879104
89879100
89819100
89819100
89879100
89819100
89879100
89879100
1
o
7/8
FR .LEV TO.L EV
1
1
3
~
1
2
2
2
1
1
1
1
1
2
2
1
1
1
1
Z
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
1
1
1
1
1
2
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
LENGTH 9"
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
9-93
PAGE
"'i)
40
FROM
20P1812
20P1813
2~P1811t
20P18l5
20Pt811
20P1819
20P1822
'20P1823
20P'824
'-OP 1825
20P1826
20P18l7
20P1828
20P1829
20P1830
20P1831
20P2AO 1
20P2A04
20P2A04
20P2A05
20P2A05
20P2A06
20P'-A06
20P2-A01
20P2A07
ZOPZAll
ZOPZA 11
2C)p,- A12
20P2Al4
ZOP2A14
20P2AIS
?OP2A16
20P2A16
20P'-A17
20P2A17
20P2A18
?OP2A19
20P2A19
20P2A20
?OP2A20
20P2A21
20P2A21
ZOP2A23
20P2A24
20P2801
20P2802
20P2802
20P2803
20P2804
20Pl804
70P?805
9-94
WI R F
T!J
24P2~04
25P2S13
26P182Q
26PIA11
2ljP1831
2ljPl A11
21P2811
23P1821
22P18'4
2. lP2A21
21P2A30
24P2820
21P2A04
23P1829
21PIA21j
22PIA31
27P2 All
22P2802
19P1802
19P1 A28
25Pl812
Z5P2A28
15P280Q
27P282"
21P1806
17P2817
26P2824
2SP181!)
15PIA11j
lljP2821)
26P2829
26PtAll
ISP2810
25P2804
17P2806
22PlA08
t7P280A
ZI)P282'
25P2 AOIj
17PZR04
17P2Al1
25PZ All
20P2A24
20 P ZA21
21P2Al1
21P2AOl)
23P18l1
22P2RIA
23P2A29
21Pl A17
2lPIA25
l I S T
S (GNAl-NAME
CSM.
CNS6l·
CNS2M.
ehS1M.
eNSOl·
eNSlL.
PRF(PFIND'
OPINO
SlS
P4M
REAe
eSA.
GOeSW.
esv*
PRl81T
e5)(*
OVFL.
RfAO*
RfAO*
CO
QO
07
07
PEL·
PEL.
OA1.3.
OAI3*
INTll.
06
.06
vElM*
o~
09
OA3.
OA3.
INOINO.
OA7.
OA7·
OAO*
OAO*
flA4.
OA4.
-12V
-12V
SGl*
Goes
Gees
FINT
RNI
IHH
CRO*
A8 1 C 7/8
w.l.
89879100
. 89819100
89819100
89879100
89879100
89879100
89879100
89879100
89819100
89879100
89i:l79100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89819100
89879100
89879100
, 8987910"
8981910'"'
89879100
89379100
89879100
89879100
89879100
89879100
89879100
89·:179100
89879100
89879100
89879100
89879100
89879100
89879100
89819100
89879100
89879100
89:1 79100
89879100
8c;a79100
89879100
89879100
89879100
89879100
89879100
89879100
89819100
119879100
FR .lEV TO.lEV
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
2
2
1
2
1
2
I
1
1
2
2
2
1
1
2
2
2
1
1
Z
2
1
1
1
2
2
1
2
Z
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1 .
1
2
2
1
Z
1
2
1
1
1
2
2
2
1
1
2
2
2
1
1
2
2
1
1
1
2
2
1
2
2
1
1
89633300 A
PAGF NO
41
W I R F
TJ
FR1P<4
20P2 BOb
20P7.BOb
20P2B01
lOP2 R01
20P2808
20P2B08
20P2B12
20P2BIZ
20P2811
10P2813
20P2814
20P2B14
20P1B15
20P281S
lOP2alb
ZOP281b
20P2818
20P1818
ZOPZB19
20P2819
20P2820
20P2820
20P28ZZ
20P2B12
ZOP281J
ZOPlB23
20P2824
ZOP2814
ZOP2825
lOP181'S
ZOP2B26
20P2826
ZOP2827
ZOP2828
20P28Z8
2LP lAO 1
21PIA02
21P1A03
ZIPIAOS
21PIA06
21PIA07
2IPl A08
21PIAOfl
21PIAI0
21PIAll
21plAll
21PIA12
21P1A12
ZlPlAl2
21PIAl3
21PIA14
19P2831
22P1ROl
25P2A24
1SP1 A1ft.
25Pl R20
21P2A21
1 qPl AO'.l
llP182'»
22P2A24
1 QPl ROI
26P1812
15P2 AOq
ISP1814
ZI)P28Z8
26P1AOR
15PlAI0
ZSPZA21
11Pl RQ9
I1P1AOl
ZSP1A3n
2'SP2A02
17P2AO'
I1P281n
2SP2824
26P1AO'S
I1P2 All
11PZA 12
26P1AOl
23P2831
15PIB07
17PZ82,
Z6PIA30
29P2Alft
26P2 BOft.
17PZAZO
23P2A10
26P2Al1
2SP2All
22PIAOt
24PI B2t
20P1410
24PIB22
22PIA27
22P2Bl9
24PI All
22P2AIO
OIjPlA 21
22P2 A01.
20P1804
26P2829
23Pl AIS
89633300
A
lIS T
SIGNAl-NA~E
W~ITE.
WRITE*
04
04
Me* .
Me.
RFPLV*
REPLY*
R EJ ECl*
REJECT.
08
08
OS
OS
010
010
OA6*
obb.
OA2*
OA1*
OA1*
OA1·
OA5·
OAS.
OA8*
OA8*
OA9.
OA9*
CHI.
CHI.
OA10*
OAI0·
" SS
OAl1*
OAl1·
15
XGCM
XGOl
17DBB
SlK.
XIS
FIEI
KOVf
WIlO
WfCO
32KW
32KW
32KW
WEZM.
Pt41
A B 1
W.L.
89319100
89879100
89819100
89819100
89879100
89879100
89879100
89819100
89819100
89879100
89819100
89<:179100
89819100
89879100
89879100
89879100
89879100
89319100
89819100
89819100
89819100
89819100
89819100
89879100
89819100
89819100
89819100
89819100
89879100
89879100
89819100
89819100
89879100
89879100
89879100
89819100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89819100
89879100
89879100
89879100
o
7/8
FR.lEV TO.LEV
1
2
1
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
Z
1
1
2
2
1
1
1
2
2
1
1
1
1
I
2
2
1
1
2
2
3
1
1
2
1
1
2
1
1
2
1
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
1.
1
1
2
2
1
I
1
2
2
1
1
1
1
I
2
2
1
1
2
2
3
I
1
2
9-95
PAGE NO
ft2
~
IRE
FROM
TO
2lPlA15
21Pl.A15
21PIA16
2lPlA17
ZlPIA17
2lPIAl8
21PIA19
21P1A20
21P lA21
ZlPIA22
21P1A23
21P tA2ft
2lPIA24
ZIPIA25
21PIA26
21PIA21
21P1A28
21PIA30
llPIA30
21P1A3l
llPIBOl
21P1B02
'21P1803
21 PI B04
llplS05
21P1806
21 PI BO.6
21P1807
21PIB08
21PlS09
21P1810
l1PIBll
21P18l3
llP1813
2lPIBlS
2lPlB16
21PIB17
21PIB18
21P1818
2IP1820
21PIB2I
21Pl822
21PIB23
21P1B24
21PlB24
2IPIB25
21PIB25
21Pl826
21 PI B21
21P1828
2iP 1B29
24P IB 02
23P2811)
20PIA3l
20P2B04
22 Pl 820
20P1Al1
2 2P2 BIR
23Pl A09
26PIA21
21)PIA02
25PI82'»
25P2Al'
26Pl A02
20P1830
26PIBI6
24PI AO~
23PIA20
23P2BIR
22PIB22
25P2AOl
23PIB2ft.
26P281R
24PlBO,
22Pl430
23P2810
lOP2401
19PIAIf)
22P2807
22PlA20
9-96
24PIB2~
22P2A l '
26PZB21
22P1 Bl'
'3P2Bl9
23Pl A19
20Pl A.30
20PIA21
20PIA24
22P2RlI
26P1821
21 P2B21
21P282R
2 2P2 AOR
22PlA05
23P2A21
2·3PIB19
20P2805
21)P1B1Ft
25Pl BOR
22P2alft
26PIB2Ft
l
r S T
S·IGNAl-NAME
ENI
ENI
STOPCS*
RNI
RNI
PRGST
E (NT
(RC I<
PLM
GSL*
LeNl
GSM*
GSM*
PRT81T
AM
FS*
KENIl*
R4
R4
MCNl
14
XSQM
oSx
SKT
16
PEl*
PEl*
03*
A1M
015
QVFl*
OVfW*
noo*
000*
SSI
INT.SW*
SWEEP*
ENT ER*
ENT ER*
GlM
GPEC*
RGPWR
INOIND*
EN120*
EN120*
eRO*
c .. o*
Al
030
KPNIl
lCNM
A 8 1
ill
.l.
89819100
89379100
89i:J 19100
89819100
·89879100
89879100
89819100
89879100
89879100
89879100
89819100
89819100
89819100
89879100
89819100
89819100
89819100
89879100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89879100
891179100
89819100
89879100
89819100
89819100
89879100
89819100
89IJ 79100
89819100
89819100
89879100
89819100
89819100
89819100
89819100
89819100
89d 1.9100
89819100
89379100
89819100
89819100
89819100
89819100
89819100
89819100
o
118
FR.l EV TO.LEV
2
1
1
1
2
I
1
2
1
2
2
2
I
1
I
1
1
1
2
I
1
2
1
1
2
1
2
1
2
2
1
I
1
2
2
1
1
1
2
I
2
2
1
2
1
1
1
·2
1
2
2
2
1
1
1
2
1
1
2
1
2
2
2
1
1
1
1
1
1
2
1
1
2
1
1
2
1
2
1
2
2
1
1
1
1
2
1
1
1
2
1
1
2
1
2
1
2
1
2
1
2
2
89633300
A
)AGE NO
W I
43
TO
FROM
21PIB30
21PIB31
21 P2 AO 1
21P2A02
21P2A04
21 P~ A05
21P2A05
21 P 2A06
21 P2 A01
21P2A08
21P2A09
21P2AlO
21P 2AI0
21P2Ali
21P2A12
21P2A13
21P2A13
21PlA14
21P2A14
21P2A15
21P2416
21P2411
21P2A18
21P 2A19
21P2A20
21P2A21
21P2A22
21P2A23
21p2A24
21P2A25
21P2426
21P2A21
21P2A21
21P2428
21P2A29
21P2A30
21P2A]1
21P2801
21P2802
21P2B03
21P2804
21Pl805
21P2806
21P2806
21P2801
21P2808
21P28u8
21 P2 809
21P2810
21P2811
21P2812
26 P2 407
25P2B03
25PIA2l
26P2401
20PIB28
24P2 B21)
20P2B02
23P2821)
25P2 B2~
20PIAOQ
24P147..7
23P2B17
22PIAIR
27P2811
21P1427
20P2BOl
21P21322
ZOPI BOq
21P280t
25Pl BO?
25P1425
26P1404
25Pl A2ft
21PIA26
25P281n
26Pl R04
20P1A2"
23PZ A27
20PIAOR
2.3P2413
24Pl Al I)
20P280R
13P2fHl
15P2 B2R
26P1820
20P182"
20P1801
25P2AOI
25Pl B2l
26P280l
21P1428
22P2820
22P1819
23P2 A2A
25Pl AI0
21P1801
21P2 81 Q
22P1 Al q
23PIA21
23P2811
23P2A1r;
89633300
A
R E
L
J S T
SIGNAL-NAME
MCNM
GML
PLL
PMM
GOC SW*
Goes
GOCS
KRNI
WEll*
AUTRS"*
PEf*
FEO·
fEO*
NORMAL
MPRY
SGI.
SG1*
PRT SW
PRTSW
TAOtI TA2l*
TA1M
[ TA3l
M)ll1
ITA4l*
TA2M
PCL*
[NR
TMSW*
JENI
DEL2
MC*
MC*
PRTAO*
CLPXM
BEAC
VCC
PML
GLl
GMM
C VI 01*
PH3
R3
R3
[NTOl
DfEO
DFEO
OPST
ClRIR
0002*
Cl~fQ
AB 1
W.L.
89d19100
89819100
89319100
89d 19100
89819100
89819100
69819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89d79100
898191UO
89819100
89819100
89819100
89819100
8,}819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
8981910<\
89819100
89619100
89819100
89819100
89819100
89819100
8981~100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
o
7/fJ
fR.LEV TO.lEV
2
1
1
2
1
1
2
2
1
1
2
2
1
2
2
2
1
2
1
1
2
2
2
1
1 .
2
2
1
2
1
1
1
1
1
2
3
1
1
1
2
2
2
2
2
2
1
1
1
2
2
1
1
2
1
2
1
1
2
2
1
1
2
2
1
2
2
1
1
2
.2
1
1
2
2
1
2
1
1
1
1
1
2
1
1
1
1
2
2
2
2
2
2
1
1
1
2
2
1
1
2
9-97
PAGE NO
4-4
FROM
SEE
BELOW
WI R E
TO
l
1ST
SIGNAL-NAME
PRFCPFIND)
ENI4*
VIO*
TAOH
TAll
JKCK
21P2813
21P2814
2lP2815
21P2 R16
21P2R17
2lP2R18
21P2819
21P7820
21P2822
21P2B23
21P2R24
21P2B25
21P2B26
21P2821
21 P2B28
21P2829
21P2830
> 21P2830
21P2B31
22PIAOI
22PIAOl
22PlA02
22Pl A03
22PIA04
22PIA05
22PIA05
22PIA06
22PIA07
22P1A08
22PIAI0
22P1411
22P1A12
22PIA14
22PIA15
22 PI A17
22PIA18
22PIA19
22PIA19
221>1A20
22Pl A21
22PIA22
22PIA23
22PIA24
- 22PIA25
22PIA26
22·Pl A21
22PIAZ8
22PIA30
22PIA31
22P lA31
22P1801
20PlS2?
22Pl AI0
2 3Pl AOft
26P1802
25Pl A04
22P2A19
22PIA27
25P1804
22P2B15
21PIB17
27P1830
24P1BOh
27P2 B30
20PIBOA
15Pl A09
22P2A2'J
15PIA20
12P2 A25
20P1A07
21PIA05
24P2 A23
24P2A 15
2_3P2B30
25P182l
21PIB 24
24PIA07
23P2824
23PIR03
23P2 B16
21P2R14
23PIB21
27 PI 826
24P2A09
24PIA14
23 P2 A()9
21P2AI0
20Pl A27
21 P2 B09
24P2B29
25P2A30
21P2B19
24P1A28
24PlB27
28PlA12
23P2 B14
21 PI A09
23PIB2?
23PIAzr;
20Pl B3l
24P2A21
25PIAOl
ENI3*
ENI4*
GOCS
CRI*
T3
OEt*
CNT f2*
FEO*
OPST
OPST
F IE23
AQC*
IE
R2
RI
SPBM.
EAO*
FIEI
0002
IN4I
csx*
C sx*
C2
> 21P2B31)
19P1A'.l2
~IEZ*
9-98
iE
TA2l
MPC
10
PRTM*
PRY
32M
MCCS*
T.P.
MC
WEZ*
WEZ*
BfA
17*
11*
I TR
MOS
CO
E N120*
ENI20*
OP20*
MMPC
A B 1 o 1/8
W.l.
89079100
89879100
89a 19100
89879100
89a 19100
89879100
89879100
89879100
89819100
89819100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
, 89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89819100
89879100
89879100
89819100
89819100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89819100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
FR. lEV TO.lEV
1
1
1
2
1
2
2
2
1
1
2
1
1
1
1
2
2
1
1
1
2
1
2
2
2
1
1
2
1
1
1
1
2
2
3
3_
1
1
1
1
2
2
1
2
2
1
2
2
2
2
2
2
1
1
2
2
2
1
1
2
2
1
2
1
1
2
1
1
1
2
1
2
2
2
2
2
2
2
2
1
1
2
2
1
1
1
1
2
2
1
2
1
1
2
I
1
1
2
1
2
2.
2
2.
2
LENGTH 1111
LENr,TH 7"
LENGTH 1411
89633300 C
)AGf NO
45
FROM
72PIB02
22PIB03
22PIB()4
22PIB05
22PIA06
22PIR01
22P 1808
22Pl B09
22PIA10
22PIB12
22PIR12
22PlR13
22PlB14
22Pl B15
22PIR16
22PlB17
22PIB18
22PIB19
22P1819
22P1B20
22P 1B22
22Pl822
22Pla2J
22P1824
22P1B25
22P IB26
22P1827
22Pl828
22Pl.B29
22P2A02
22P2A02
22P2A04
22PZA05
22P2A06
22P2A01
22P2A08
22P2A08
22P2A09
22PlAIO
22P2A11
22P2 A12
l2P~A12
22PZA13
22P2A15
22P2A 16
22P2A11
22P~ Al8
22P2A19
22P2A19
21P2A10
22P2A20
W I
TO
24P2A22
24P1B31
25P2 BJ 1
23P2RC7
24Pl Bll
25Pl All
23PIB21
25P2A10
24P2AOI
24P1B09
21PIBl~
24PlA13
23PIA,27
24P1 B18
24P7BOb
28PIBl)
23P7. R20
21P2B06
24Pl A,24
21PIA 1·1
21PlA]O
24P1823
23P2A27
20P1824
24P1 Bll
23P2B2b
21P1A2l
24Pl All
23P2A01
21 PI A12
23P2R08
26PIA22
25PIA18
RE
l
I
S T
SIGNAL-NAME
Il:5
02*
C3
N41
Sl-il
CLPC*
EXT
C1
00*
000*
000*
MOSl
OP
FNI2E*
T4
CPSM*
FIEF
R3
R3
PNI
R4
R4
(NR
SLS
WE*
RN[ 21 *
INO
WXLl*
IN32
32KW
32KW
SE
XFl
2~P2828
RN112*
2.3P181'i
21PIB23
20P2AIR
26PI411
21 PI All
23P2801
21P1810
20P2AOl
23P2809
13P1810
WXM
23P281~
20PIA,21
23P2 AOS
21P2818
23P2BOS
llP180A
26P2B23
89633300 A
(NOINC*
INOINO*
S 1M
WPO
MOl*
OVFl*
O"Fl*
JITR*
WXl
SHADR
RIND
JOP2
JKCK
JKCK
A1M
A1M
A B 1 C 7/8
w.L.
89819100
89;]79100
89319100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
898'19100
89879100
89879100
89819100
39879100
89879100
89819100
89819100
89879100
89879100
89819100
89879100
89879100
89819100
89879100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89379100
89819100
89919100
89819100
89819100
89819100
89819100
89819100
89879100
89819100
89879100
FR .LEV TO.LEV
2
1
1
1
1
1
1
1
2
2
1
2
1
1
2
2
2
2
1
2
2
1
2
1
1
2
1
2
2
3
2
2
2
2
1
1
2
1
2
1
1
2
2
2
1
1
2
2
1
2
1
2
1
1
1
1
1
1
1
2
2
1
2
1
1
2
2
2
2
1
2
2
1
2
1
1
2
1
2
2
3
2
2
2
2
1
I
2
1
2
1
1
2
2
2
1
1
2
2
1
2
1
9-99
PAGE NO
46
FR'lM
22PlA21
22P2A21
21P2A22
21P2A23
21P2A23
22P2A24
22P~A25
21P2A26
22P2 Al7
22P1A28
22PlA29
22P2A30
22P2ROl
22P2S02
22P2803
22P2B04
22P?R04
22P2B05
22P2B07
22P2 BOl
22P2R08
22P2BI0
22P2Bli
22P2812
22P2B13
12P2B14
22P2B15
22P2B15
22P2B16
22P2817
22P2B18
22P2818
22P2B19
22P2820
22P1R20
22P2B22
22P2823
22P2B24
22P2B25
22P2826
22P2827
22P2828
22P2829
22P2830
23Pt AO 1
13PIA02
23PIA03
23P1A04
23PIA05
23Pl A06
23PIA07
9-100
W I
TO
20P1825
27P2Al')
24PIA08
21P2829
25P2B 30
lOP2Bl1
24PIB17
23PIB16
24Pl B25
26P2ROA
. ,2')P2 A04
21 PI 804
20P2B06
20P2A04
24P2 A07
24PIBOA
21P2 B27
25PIB22
21PIBOl
24P2 BOI
2~P2B02
23P2A24
2lPl R18
23P2804
23P2A23
21P1828
23PIA26
21P2822
24P1830
2'3P1826
20P2803
21PIA19
21PIAI0
21 P2 Bor;
23PIA22
23Pl A31.
26P2 A09
24P lA 19
20P2Bl1
24P2 A12
24P2A28
26P2 A14
23P1BOA
24P2B10
27P2 A30
26P2A19
24P1826
20P1BI0
33P281l
21P2Bl')
27P2 A2'J
RE
l
1ST
SlGNAl-NAME
P4M
P4M
RP
Me
MC
REJ ECl.
IRJ*
GOAO*
BS
AUG1M
AlU1AM
SKT
WIH lE*
REAO*
M
R NII1.
RN (11*
SFl
03*
03*
F23
JRNI*
ENTER*
JOP
K ITR
KPNIl
MPC
MPC
01*
X15
EINT
EINl
KOVF
PH]
PH)
ACR*
ZI TSH
PlAOO
R EPl y*
so
RX15
AC07M
PH2
OEl TAUG*
"CC2
XSEl7M
CRO
CSPR
GCM2
VIO*
OSC*
A B 1 o 7/8
W.l.
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89d 79100
89879100
89879.100
89879104
89879100
89879100
89879100
89819100
89879100
89879100
89879100
89819100
89879100
B9819100
89879100
89879100
89879100
89879100
89879100
89819100
89879100
89879100
89879100
89819100
89879100
89819100
89819100
89879100
89879100
89879100
89819100
89879100
89819100
89d 19100
898'79100
89879100
89819100
89879100
89879100
89879104
89879100
89879104
89819100
89879104
FR.lEV TO.lEV
1
2
2
2
1
2
2
1
2
2
1
1
2
1
1
2
1
2
2
1
2
2
1
1
2
1
1
1
1
2
1
1
2
1
1
2
1
1
2
2
1
2
.2
2
1
1
2
1
1
1
2
1
2
2
1
1
2
1
1
2
1
1
2
1
1
2
1
1
2
2
1
2
2
2
1
1
2
1
1
1
2
1
2
2
1
1
2
2
1
2
1
1
1
1
89633300
A
'AGE NO
WI R F
41
TO
FROM
21Pl AO 8
23PIA09
23PIA09
23PIAIO
2lPl All
21Pl Al2
23PIA13
l.lPIA14
23P1A15
?3PIAlb
21PIAl1
23PIA19
21PIA20
2l P IA21
l.lPIA22
23PIA23
23PIA23
23PIA24
23Pl A2 5
23P lA26
2JPI. A2 7
23PIA28
23P 1 A30
·23PIA31
23PIA31
7.1PIBOl
2JP1801
21PIB05
23P1B08
23P180CJ
23P18l0
23P18l1
23PIB12
231»1813
21PI8L4
23P1815
2)P1616
23P1Bl1
231)1817
23P1818
23P1819
21P 1819
21P1820
23P1821
23P 1621
2JP1822
23PIB22
23P1823
23PLB24
21P1B24
23P182b
l1P2BOq
24Pl A2l
21PlA20
25P1 Ale;
2 5Pl A14
25PIA20
24Pl ~t)4
24P2A2~
21PlAI4
24PIB24
24PUHO
21PIB15
21 PI A2R
22PIB21
22P2B20
7.4Pl A31
21P2B 10
24P2B07
22Pl A30
22P2B15
22Pl B14
24P2R04
25P18I7
24P1807
22P282'
21P2B08
2lP1A07
24PIA 10
22P2829
26Pl A15
22P2A15
21P2821
'4plB2CJ
25P1Bl"1
25P181CJ
22P2AC1
22P2A26
21 P2 823
24P1811
24PI801)
25P1803
21P1B21)
24PIA26
22PIAll
20P2R02
24Pl AO'22PIA2A
20P1823
21 PL 801
2ltP2826
22P28L7
89633300
A
l
1ST
SIGNAL-NAME
GOM I
JRCK
( RCK
XlCK
CCK
YCK
WP
.A
PHI
A01
12
SSl
KENn*
INO
PH}
ClRIR
ClRIR
ADY.
IN4l
MPC
OP
MDS2
YTAUG
ACR.
ACR*
OFEO
MMIHl
13
PH2
x,,-eK
WXl
GND
WQ
PCK
AlCK
W)eM
GOAQ.
10
10
11
CPO·
C~O.
AD2
Goes
GOCS
0002
0002
OPIND
14
14
Xl5
A B 1
W.L.
89819104
89319100
89879100
89819100
8913 19100
89819100
89819100
89879100
8Cid 79100
89879100
89819100
89879100
89819100
89819100
89879100
89879100
89879100
89819100
89819100
89819100
89S19100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89879100
89819100
89819100
89879104
89879100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89d79100
89819100
89819100
8CJ819100
89819100
89819100
89819100
89819100
89819100
o
118
FR.lEV TO.lEV
1
2
2
1
2
1
2
2
1
2
2
1
1
1
2
1
1
1
2
1
2
2
2
1
1
2
1
1
1
2
2
1
2
1
2
Z
1
2
2
1
1
1
2
1
1
1
2
1
2
2
2
1
1
2
1
1
1
1
2
2
1
1
2
1
2
1
1
1
1
1
1
1
2
1
1
2
1
1
2
2
2
2
1
1
2
1
1
2
2
2
2
1
1
2
1
1
2
2
9-101
PAGf
~]
4A
FROM
23P1S26
23P1827
23P1828
21P1829
23P1830
23PIB31 .
21P2AOI
23P2A02
23P2A04
23P2AOS
23P2A01
23P2A08
23P2A09
23P2A09
23P2AI0
23P2AI0
23P2 All
21P2A12
23P2A13
23P2A14
23P2A1S
21P2A16
2'JP2A11
23P2A19
23P2A20
23P2A21
21P2A22
23P2A23
23P?A24
23P2A24
23P2A25
23P2A26
21P2A27
21P2A27
23P2A28
23P2A29
23P2A30
23p2BO 1
23P2801
23P2802
21P2B03
23P2804
23P2805
21Pl806
23P2B07
23P2R01
2'JP2B08
21P2B08
23P2B09
23P2810
23P2BIO
9-102
W I
TO
24P182i'
22PIBOA
24P2 AI420PIB29
24PIA22
24P2 B12
24P2B1.3
24P1Al1
24-P2 B2A
22P2AIB
22PIR29
24P2827
24P2A30
22Pl All
21PIAOl
24P2 B2426P1819
~24PIR21
2lP2 A2~
.25Pl A22
21P2B12
24P2 B16
24P2BIA
24P2811)
24PIBIA
21PIB24
2SP2All
22P2811
22P2BI0
24PIA0424PIAOf)
24P2A27
22PIR2!t
21P2A2~
21P2BOb
lOP2 B0414P2BOl
22P2All
24P2 All
22p2BOA
24PIROl
22P2B12
22P2A19
24P1 A06
24P2.B 14
R E
l
1 S T
SIGNAl-N'ME
XIS
EXT
NO
CSv*
B8CK
M021*
WC;A*
MOSI
OPE.
JOP2
IN32
MOSO
CNTE2*
CNTE2*
IS
15
A"'CK
Rl
JENI
SGl
ClREQ
016*
EIS*
RE1F
ENI2E*
fNI20*
MCK
KITR
JRNI*
JANI*
RN122*
REl8*
INR
INR
R3
RNI
03*
M01*
MD1*
F23
MOSE
JOP
JKCK
OPO.
N41
22PIBO~
N~l
26P2 A2Q
22P240?
22P2A13
32KW
32KW
J HR*
16
16
21PIBO~
24P2B21
A 8 1
W.L.
89B 79100
89819100
89879100
89879100
89879100
89879100
8~8 79100
89879100
89819100
8981~100
89819100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89819100
89B 79100
898 7~100
89879100
89819100
89879100
89819100
89819100
.89879100
89879100
89819100
89819100
89879100
89819100
89879100
89319100
89819100
89879100
89819100
89819100
89819100
89819100
89819100
89819100
89879100
89819100
89879100
89319100
89819100
89819100
89819100
89819100
o
7/B
FR .lEV TO.lEV
1
1
2
1
2
2
2
1
1
2
2
1 .
2
1
2
I
2
1
1
1
2
1
2
1
1
2
1
2
2
l
1
1
2
2
1
2
1
l
1
2
1
1
1
2
1
2
1
1
2
1
2
I
1
2
1
2
2
1
2
2
1
1
2
1
1
2
1
1
1
1
2
2
1
1
2
2
2
1
1
1
2
1
2
2
1
1
2
1
1
2
1
1
1
1
2
2
1
1
2
2
2
1
89633300 A
AGE NO
ft9
F~1M
21P2Bll
23PZB1Z
23P2B1.3
23P2B14
21P2815
21P2816
23P2B 1 7
23P2B18
23P2819
21P~820
23P2822
23P2B23
23P2B24
23P2825
23P2B26
21P2626
23P2821
23P2828
23P 2828
23P2829
71P2830
23P2831
24Pl AOZ
24P1A03
24PIA04
24PIA05
24PIA06
2ftPI A01
24PlA08
24PIA09
24P1AI0
24PIAli
24PIAIZ
24PlA13
24PIA13
24PIA14
24PIA15
24PIA16
2ltPIA17
24PIA18
24PIA19
24PIA19
24PIA20
24P1A21
24PIA22
24P lA23
2ftPIA24
2~PIA25
2~P
lA26
2ltPlA27
2lt-PIA28
WI R E
TO
21 P2 Bll
24PIA2~
2lP2A1n
22Pl Alb
21P1Al1)
22P1AOA
ZlP2 AI0
21PIA30
21PIBll
22PIBIR
21PlAll
24P2801
22P1A06
21P2A06
2 2P1 B2"
24P2A29
22P280ft
22P2A06
24P2830
24P2Alr;
22P1AOl
20P2 B21)
21P1822
21PIA21
23P2 A2ft
23P2A21)
23P2BOt.
22PIAOr;
22P2A2?
25PIA09
23P1801)
21P1Al1
22P182R
22 Pl811
23P2A02
22P1Al1)
21 P2 A26
25PIA19
25P1811t
25PIBl1)
25PIA12
22P2824
25PIA16
21PIA09
23P1830
26PIAIQ
22P1819
26Pl B18
23PIB20
21 P2 A09
2?PIA2'l
89633300 A
t
1ST
SIGNAL-NAME
0002*
R2
SHAOR
EAO*
ENI
ENI3*
FEO*
R4
000*
FIEF
SG1·
WM
OP20*
KRNI
RN121*
RN121*
RN111*
RNII2*
RNI1Z*
ITR
MOS
CHI*
0002
F S*
JRNI*
RN122*
OPO*
EN120*
RP
XTAOD
. 11
WRQ
WXll*
MOSI
MOSI
DEl*
OEl2
MXll
MTAOO
M)e2l"
PTAOO
PlAOO
M)ell
IRCK
seCK
MXIM
R3
"XO"
AD2
PEF*
R2
A B 1
W.L.
89879100
89879100
89879100
89879100
89819100
8913 19100
89879100
89879100
89879100
89879100
89819100
8913 79100
89879100
89879100
89879100
SC;679100
89879100
89819100
89619100
89819100
89879100
89819100
89819100
89879100
89879100
89879100
89819100
89879100
89879100
89819100
89819100
89819100
89879100
89819100
89819100
89819100
89819100
89819100
89319100
89819100
89819100
89819100
89819100
89879100 .
89879100
89819100
89819100
89879100
89819100
89819100
89879100
o
11 P,
FR.LEV TO.lEV
1
1
1
1
1
1
2
1
2
2
1
2
2
1
1
1
2
2
2
1
2
2
1
2
2
1
1
1
2
2
1
2
2
1
1
1
1
1
1
2
1
2
1
2
1
1
1
1
2
2
1
1
1
1
1
1 .
2
1
2
1
2
1
1
1
2
2
1
2
1
1
2
1
1
2
1
1
2
1
1
1
2
2
1
2
1
1
2
1
1
2
1
1
2
1
1
1
2
2
2
2
2
2
.9-103
PAGE NO
50
FROM
24PIA28
24PIA31
24P1601
2ftP1802
24PIR03
24P1804
24Pl805
24Pl806
24PIB07
24PIB08
24P1809
24PIBIO
24P1812
24P 1612
24PIB13
24P1814
24Pl B15
24PLBL6
24PIR17
24PIB18
24PIBl8
24PIR19
24PIB20
24PIBll
24P 1622
24P1622
24PIBZ3
24P18Z4
Z4P16Z5
24P1826
24P1626
24PI821
24P1621
24P1628
24Pl 82 8
2ft.P I B29
24PIB30
24P1831
2ft.P2 AO 1
24P~A02
24P2A04
24PZA05
24P2A01
24P2A01
24P2A08
24P2A09
24PZAIO
24P2A11
24P2A12
.24P2A12
2ltP2A13
9-104
W I
TO
2.3P2Bll
23Pl A23
23P2B03
21 PI A1 ')
20plA2')
23PIAIl
23PIB18
21P2B25
23PIA31
22P2804
22PIBl?
23PIA11
21Pl A30
22PIB25
21PIBl1
26PIBl')
26PIA16
25P1818
2 2P2A 2'i
23P2A20
22 PI 81 'i
25PIAl1
27P2BlO
21 PI A06
23P1826
21 PI AOR
22PIB22
23PIA16
22 P2 A27
23PIAOl
27P2A09
23P2 A12
22PIA24
21P1809
l6P2 AlA
23PIRIl
22P2Bl6
22PI BOl
22P1BIO
25P2A27
20P181Z
26P2819
22 P2 BOl
25P28C1
26P2B20
22Pl Alit
20P1A21
23P2BOl
2?P2B26
2SP2AC8
25PIB25
R E
l
1ST
S IGNAL-NAJ4E
R2
ClRIR
MOSE
ENI
CSP*
WP
11
PRY
AOR*
RNI11·
000*
12
we·
we.
fa
MX2M
MX3M
MXOl
IRJ*
ENI2E*
ENI2E*
Sll
MOEl
088
XIS
XIS
R4
AOI
ee
eRO
eRO
Rl
Rl
015
015
WO
01*
02·
00*
AO*
CSM*
MX1M
M
M .
MX5M
T3
eso*
MOI*
SO
SO
S3
A
a
W.l.
89879100
89379100
89879100
89879100
89879100
89879100
89879100
89979100
89819100
89379100
89819100
89879100
89879100
89879100
89379100
89819100
89819100
89819100
89819100
89879100
89879100
89879100
89819100
89879100
89879100
89819100
89879100
89319100
89819100
89819104
89819104
89819100
89819100
89319100
89819100
89819100
89819100
89819100
89879100
8981910-0
89819100
89819100
89819100
89319100
89819100
89819100
89879100
89879100
89819100
89879100
89819100
I
o
7/8
FR.lEV TO.lEV
I
2
I
2
I
I
1
1
2
1
2
2
2
1
2
I
1
1
2
2
1
2
2
1
1
2
I
1
1
1
2
I
2
1
1
1
1
2
1
2
2
2
1
2
1
1
1
2
2
1
2
2
1
. 1
2
2
1
1
2
1
2
2
1
1
1
2
I
1
2
2
1
1
2
1
2
2
1
1
1
2
1
1
1
2
1
2
1
1
2
1
2
1
1
1
1
2
1
1
89633300 A
AGE
NO
51
FROM
24P2A14
24P~A15
2lt-P2 A 15
24 D 2A16
2lt-PlAl7
24P2A18
24P2A19
24P2A20
24P2A21
24P2A12
24P2A23
24P2A24
24Pl A26
24P2A27
24P 2A28
24P2 A29
24P2A30
2lt-P2aOl
24P2BOl
2ft.P2B02
24P2802
24P2803
24P2B04
24P2805
14P2806
241»2807
2lt-P2808
24P28LO
241»2.110
24P28l1
24P28 L 2
24P2813
24P2814
241»2815
2lt-P2816
24P2817
l4P 2818
24P2B19
24P2R20
l4P2B22
24P2823
24Pl824
24PlB25
24P26lb
24P28l7
24P2828
24P28~9
24P2830
24P2B31
25P1AOl
25 P IAOl
W I R E
TO
"23P182A
22PIAO'
23P282CJ
25P2819
2SPl A26
25P2809
2SP2AIA
26P2 A25
22Pl A 31
22PIBO,
22Pl AOl
25P2A21
23PIA14
23P2 A2b
22P2821
23P2 B2~
23P2A09
22P2R01
23P1A30
21PIBOl
2SP2AQ6
23P282l
23PIA28
26P1A10
llPl81f.
23P1A24
26P2 ALA
25P2Bl6
22P2830
22 PI 80~
13Pl831
23P2AOl
l3P2801
23P2AlQ
23P2Al&
25P2820
23P2Al1
25P2 A20
20Pl821
25P2A26
23P2810
23P2AIO
llP2Aor;
23Pl B2~
23P2AOA
23Pl AOft
22Pl A2Cl
23P2B2A
21)P2 A25
26Pl AOt
22PIBOt
89633300 A
l
I S
r
SIGNAl-NA~E
NO
ITR
I TR
M)c7l
52
SI
M)l6L
XTAUG.-.
C 5)(*
165
17*
ATAUG
WA
RElS*
8X15
RN[Z1*
CNTE2*
03*
03*
05)(
QSX
WM
MDSl
MX4M
T4
AOY*
M)c6M
OElTAUG.
DEL TAUG*
SHI
M021*
W9A*
Nlt1
REIF
016*
MX5l
E[S*
MX4l
eSA*
OTAOO
16
15
Goes
14
MOSO
OPE*
FIE23
RN112*
XTAUGL
C2
C2
A B 1
W.l.
89879100
89879100
89B 79100
89879100
89879100
89879100
89819100
89879100
89879100
89879100
89879100
89879100
89379100
89879100
e9a 79100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
8987.9100
89879100
89879100
89879100
89879100
89879100
89d 79100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
o
7/8
FR.lEV TO.LEV
2
2
1
2
2
1
1
1
1
1
1
2
2
2
2
1
2
2
2
1
2
2
1
1
2
1
2
1
2
1
1
1
1
1
2
2
2
2
1
2
2
2
1
2
2
1
1
2
1
2
1
2
1
1
1
1
Z
2
1
2
1
2
2
2
I
1
1
2
1
1
1
1
1
1
2
1
1
1
1
2
2
1
1
1
2
1
1
1
1
1
1
2
1
1
1
1
1
1
1
2
1
2
9-105
P4GE NO
52
FROM
25PIA02
25PIA04
25PIA08
25Pl A09
25PIA09
25PIAIO
25Pl A11
25PIA12
25PIA12
25P1413
25PIA13
25PIA14
25Pl A14
25P1415
25Pl Al 6
25P1416
25PIAll
25PlA18
25P lA18
25PIA19
25PIA 19
25PIA20
25PIA20
25PIA21
25P1422
25PIA23
25PIA24
25Pl A25
25PIA26
25PIA26
25P1428
25P1428
25PIA30
25PIA31
'5P IBOI
25P1802
25P1803
25PIB03
25Pl B04
25P1808
25P1808
2,P1809
25PIBIO
25P1812
25PIB13
25P IB13
25P1B14
25P1814
25PIB15
25P1BL5
25P1816
9-106
WI R E
T1.
ZlPl A22
21P2B17
19P2BOI
26Pl AOCJ
24PIA 09
21 P2B07
19P2B02
24P1419
26P141'l
26P1411
22PIR07
26Pl A14
23P1411
23P1410
27Pl AO"
24PlA20
24PIB19
22P2A05
26P1A18
24Pl A16
21PIB01
23P141'
26Pl AlO
281>L410
23P2 A14
21P2 AOI
21P2AIA
21P2Al~
24P2Al1
26PIA2b
26PI A2B
20PIB07
20P2RIQ
20Pl BIQ
26P1401
21P2A15
26P1803
23P1819
21P2B20
26PIROA
21PIB27
15P1811
lOP2A12
20P2405
23P181 ~
26P1B11
26PIR14
24Pl A17
21P1404
24PIA1B
2lP1826
l
IS T
SIGNAL-NAME
GSL*
TAll
02
XTADD
XTADD
(NTOL
01
PTADO
PTADO
CU~O*
ClRO*
OCK
QCK
XlCK
MX3l
MX3l
51l
XEZ
XEZ
MXll
M)(1 L
YCK
VCK
AlU3L
5Gl
PLl
I TA3L
ITA2l*
52
52
ClREG*
ClRfG*
OA2*
CNSIl*
CI
TAOl
CRO*
CRO*
TAll
030
030
03
INTll*
00
pel<
PCK
MTADD
MTAOD
M)e2l
MX2l
Al
A 6 1
W.l.
89819100
89819100
89879100
89819100
89819100
89879100
89819100
89819100
89819100
89819100
89819100
89819100
89879100
89819100
89819100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89819100
89819100
8987'9100
89879100
89879100
89879100
89879100
89879100
89819100
89819100
89879100
89879100
89819100
89879100
89a 19100
89819100
89879100
89819100
89819100
89819100
89819100
89879100
89619100
89819100
89879100
89819100
89879100
o
7/8
FR.lEV TO. LEV
2
1
2
2
1
1
2
1
2
2
1
1
1
1
1
2
2
1
2
1
2
2
1
2
2
1
1
2
2
1
2
1
2
2
1
2
1
2
2
1
1
2
1
1
2
1I
1
1
2
2
2
1
2
2
1
1
1
2
2
1
1
2
2
1
2
2
1
1
2
2
1
2
1
1
2
1
1
2
2
1
1
1
2
2
2
1
2
2
1
1
1
2
2
1
1
1
2
2
1
2
2
89633300
A
·AGE NO
W IRE
53
FROM
2,PIB17
25Pl811
25P1818
25P1818
25PIB19
25P1820
25P1820
25P1B2l
25P1822
25P1823
25P1823
25P1824
25P1825
25PIB25
25P1826
25PIR21
25P1828
25P1829
25P1830
25P1831
2Cj P2A01
25P2A02
25P2A04
25P2A04
25P2A05
25P2A06
25P2A06
2ljP2AOl
25P2A08
25P2A08
25P2A09
25P2A09
25P2A10
25P2AI0
25P2411
25P2A12
25P2A13
25P2A13
25P2A15
25P2Al&
25P2Al1
21)P2A18
25P2A18
25P2A20
25P2A20
25P2A21
25P2A21
25P2A22
25P2A23
25P2A24
2SP2A25
TO
23PIA30
26P1811
74P1816
21P1802
23P1814
20P2B08
15P1 R2l
21P280'
22P2805
26P1821
22PIA04
28P1812
26PIB25
24P2A13
21PIA23
2AP1810
20PIA20
20Pl A18
28PIA 11
20P1811
21P2801
20P2820
26P280?
22P2 A2q
20P2A20
26P2A06
24P280'
l1PIA31
24P2 AI?
26P2AOR
25P2811
26Pl A21
26P2A10
22P1809
20P1 Aor.
21P1A24
23P2A2?
26P2A1J
28P2A12
28P2 All)
21PIA03
24P2A19
27P1 All
27PIBOR
24~2819
24P2A24
26P2A21
20P2819
20P2A21
20P2B01
24P2831
89633300
A
l
J 5 T
S IGNAl-NA .. e
YTAUG
YTAUG
M)COl
MXOl
AlCK
MC.
Me*
Gll
SFL
CO
CO
AlUOl
53
S3
lCNl
AlU2l
CNS3l*
C~52l*
AlUll
CNSOl*
FMl
OA1*
ALU7AN·
ALU1AM
OAO*
QSX
05X
NCNL
SO
50
ALUOAN
AlUOA,.
Cl
C1
CNS5L*
GSM*
MCK
MCK
AlU6l
AlU5L
XGOl
MX6l
MX6l
MX4l
MX4l
ATAUG
AfAUG
OA6*
OA4*
04
XTAUGl
A 8 1
W.L.
89819100
89819100
89819100
89879100
89879100
89879100
89819100
89879100
89819100
89879100
89879100
89819100
89819100
89879100
89819100
89819100
89879100
89819100
89879100
89819100
89819100
89819100
89819100·
89879104
89819100
89d 19100
89879100
89879100
89879100
89879100
89879100
89879100
89819100
89879100
89879100
89819100
89879100
89879100
89879100
89819100
89819100
89819100
89879100
89919100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
o
7/8
FR.lEV TO.lEV
2
1
1
2
1
1
3
2
1
1
2
2
2
1
2
2
1
1
2
1
2
1
t
1
1
2
1
1
2
2
1
2
1
1
2
2
1
2
2
i
1
2
Z
1
1
2
1
1
2
J
2
1
1
2
1
1
3
2
1
1
2
2
2
1
2
2
1
1
2
1
2
1
i
1
1
2·
1
1
2
2
1
2
1
1
2
2
1
2
2
1
1
2
Z
1
1
Z
1
1
2
1
9-107
PAGF NO
54
FROM
251)2A26
25P2A26
25P2A27
25P2A28
25P2A30
25P2A30
25P2802
25P2803
2SP2804
25P280S
25P2806
25P2807
2SP2801·
25P2809
25P'809
2SP28l0
25P2811
2SP2B12
25P2tU 3
25P2814
2SP2 B1S'
25P2816
211)P28l7
25P2619
25P2B19
25P2820
25P2820
25P2822
25P2824
25P2825
25P2826
25P2B28
25P2B29
211)P2830
25P28'30
25P2B31
25P28.31
26Pl AOI
2&PlA02
26P1A03
26PIA04
26PlA08
26PIA09
26PIA11
26P1A12
26PIAl]
26PIA14
26PlA15
26PIA16
26PIA16
26PIA17
9-108
W ( R E
TO
24P282'
26P2A26
24P2AO,
20P2A06
22Pl A21
26P2A30
26P2A04
21P1831
20P2A17
26P2826
.26P28U't
24P2A07
26P2807
l4P2AIA
26P2809
21P2 A20
2SP2AOQ
20PIA07
20Pl Bl1
20P1Al1
28P2A09
24P2810
28P2Al7
?7PIBl1
24P2A16
24P2817
27 PI A09
20P2Al9
20P2822
20P2A14
?6P28 11
20P2B11)
21P2A07
26P2830
22P2A21
26P283t
22P1804
25Pl AOI
2lP1A24
25P180l
ZiP2A17,
'OP2816
25Pl A09
20P2 A16
25PIA 12
2SPIA11
25PIA14
23P1809
24Pl BPi
21P1R 19
22 P 2A09
liS T
S IGNAl-.NAME
OlADD
OTADD
AO*
07
Aoe.
Aoe*
AlU7Al
GMl
OA3*
SHAM
HIGH
M
M
51
51
(TA4L*
AlUCAM
CN54l*
eNS6l*
eNS7l·
AlU7l
OElTAUG*
ALU4l
M)e7l
M)e7L
")cSl
MX5l
OA7*
OA5*
06
SHAL
05
WEZL·
Me
~c
C3
C3
C2
GSM*
CI
TAIM
010
XTADO
09
PTADO
ClPC*
OCK
XMCK
MX3M
MX3M
S 1M
A 8 1
W.l.
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89819100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89i79100
89879100
89879100
89879100
89879100
89879100
89819100
89d79100
89879100
89879100
89879100
89879100
89a 79100
89879100
89819100
89879100
89879100
89879100
89879100
89879100
89879100
o
7/8
FR .lEV TO.lEV
1
2
2
2
2
1
1
1
1
2
1
2
1
1
2
1
2
1
1
1
2
1
2
2
1
1
2
1
1
.2
1
2
1
2
1
2
1
1
1
2
1
2
2
'-
2
2·
2
1
1
2
1
1
2
2
2
2
1
1
1
1
2
1
2
1
1
2
1
2
1
1
1
2
1
2
2
1
1
2
1
1
2
1
2
1
2
1
2
1
1
1
2
1
2
'-
2
2
2
2
1
1
2
1
89633300 A
55
'AGE "'0
W IRE
FROM
TO
26PIA18
26PIAl9
26PIAl9
26P 1 A20
26Pl A21
26PIA22
26P 11422
26PIA23
26PIA24
26PIA25
26Pl A25
26PIA26
26PIA21
26Pl A28
26PIA30
26Pl A31
26P1802
26P1803
2&P1804
26Pl808
26PIB09
26P1812
?6PlR13
26P1814
26P1815
26P1815
26P1816
26P1811
2£tP1818
26P1818
26PIBl9
261)1820
26P1821
26P1822
261)1823
26P1824
26P1825
2£tP1826
26P1821
26P1828
2&PIR29
26P1830
261)1831
26P2AOl
26P2A02
26P2A04
2ltP2A04
2-6P2A05
26P2A06
26P2A01
26P2A08
25PIAIR
7.4PIA21
21Pl Alii
25PIA20
28PIB2R
22 P2 AO~
26P182'
21PIA21
26PIA25
26PIA24
26P2 All
25PIA26
25P2A09
25Pl A~a
20P2826
20PIBl5
21P2816
7.5PIB 03
21P2A7.t
25P1808
15P1817
20P2B14
25PIBl1
25PIB14
24P1811t
27PlBl7
21PlA26
25P18l1
24PIA7.5
21Pl A14
23P2All
21P2A29
21P1820
26PIA22
25P1823
28PlA2R
25P1825
2lP1829
2 8Pl A21
20PlAl5
20P1814
28Pl A22
20P1A14
21P2A02
20PlB24
25P2BOl
26P2801)
20P2821
25P2A06
21 Pl830
25PlACR
89633300
A
l
[ S T
S .(GNAt-NAME
XfZ
MXIM
MXIM
yeK
ALU3M
SE
SE
PlM
HIGH
HIGH
HIGH
S2
ALUOAM
ClREG*
OAle·
CNSIM*
TAOM
CRO.
TA2M
030
011
08
PCI<
MTAOO
MX2M
MX2M
AM
YTAUG
"XOM
"XO"
AMCK
CtRXM
GlM
SE
CO
ALUCM
S3
LCNM
AtU2M
CNS3M·
CNS7.M*
AlUl"
CNSCM*
PMM
OA9*
AlU1AL
AlU1At
nA8*
QSX
MCNM
SO
AB 1
W.L.
a
118
fR .LEV TO.LEV
89879100
89879100
89819100
89819100
89879100·
89819100
89879100
89879100
89879100
89879100
89879100
89879100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
. 89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89879100
89879100
89819100
89879100
89819100
89879100
89879100
1
1
7.
1
2
2
1
1
1
1
2
2
1
2
1
1
2
7.
2
2
1
2
1
89879100
89819100
89879100
89879100
89879100
89819100
89819100
89819100
89879100
89819100
89879100
89819100
1
1
2
1
1
1
2
2
1
1
1
1
2
1
7.
2
1
1
1
1
2
2
1
2
1
1
2
2
7.
2
1
2
1
1
1
7.
1
1
1
1
2
2
1
1
1
1
2
1
2
2
2
2
2
.2
2
1
1
2
1
1
1
2
1
2
2
1
1
2
1
1
2
2
1
1
2
1
1
2
2
9-109
PAGE NO
56
FROM
26P2 A09
26P2AIO
26P2All
26P2A12
26P2A 12
26P2A13
26P2A14
26P2A15
26P2A16
26P2A17
26P2A18
2C.P2A18
26P2A t"9
26P2A20
26P2A20
26P 2A21
26P2A22
26P2A23
26P2A24
26PlA25
26P2A26
26P2A28
l6P2 A29
26P2A29
26P2A30
26P'-801
26P2A02
26P2803
26P2804
26P2R05
26P2B07
26P2B08
26P2809
26P2810
26P2810
26P2811
26P2812
26P2B13
26P2B14
26P2815
26P2816
26P2816
26P2811
26P2B18
26P2819
26P2B19
26P2B20
26P2B20
26P2B22
26P2B23
2bPlBl4
9-110
W I
TO
22P2823
25P2A10
20PIA03
26Pl A21)
26P1810
25P2Al"4
22P282A
28P281h
28P2809
21PIAO,
24P280A
2iPIA2l
23PIAO'
27P1821
24P2801)
25P2A21
17P2816
17P2Al~
15PIAIB
24P2A20
25P2 A26
24P182B
23P2 B08
21P2A06
25P2A30
15Pl Bl9
25P2A04
21P2801
?OP2 B2B
26P2A04
25P1801
22P2A28
25P2809
26P281ft
26P2Al,
25P2826
lOPl B01
20PIA04
20P1801)
28P2811
26P2810
25P2BOft
28P2A16
21P180'
21P1820
2ltP2AOl)
24P2AOB
21Pl A21
17P2BIR
22P2A20
20P2A11
R E
lIS T
S {GNAl-NAME
llTSH
C1
CNS5M*
HIGH
HIGH
MCK
A007H
AlU6M
AlU5M
XGQM
M)l6M
.. X6M
XSEl7M
MX4M
NX4M
A TAUG
OA14*
OAI2*
012
XTAUGM
OTAOO
015
32KW
32KW
AOC*
CJlS
ALU7AN
GMM
OA11*
AlU7Al
M
AUG7M
SI
HIGH
HIGH
SHAl
CNSftM*
CNS6M*
CNS7M*
ALU7M
HIGH
HIGH
AlUftM
XSQM
MX1M
M)1'"
MX5M
MX5M
oAt5*
A7M
OAl3*
A B 1
W.l.
89879100
89819100
89819100
89819100
89819100
89819100
89879100
89819100
89879100
8987910.0
89879100
89879100
89819100
89979100
89879100
89819100
89819100
89d19100
89879100
89819100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89819100
89819100
89819100
89879100
89879100
89879100
89879100
89819100
89879100
89879100
89879100
89819100
89879100
89819100
89879100
89879100
89819100
89819100
8(1) 79100
89819100
89319100
89g 19100
o
7/8
FR.lEV TO.lEV
I.
I
2
1
2
2
1
2
1
I
1
1
2
2
1
1
2
2
2
1
2
2
2
1
2
2
1
1
2
1
.1
1
2
1
2
1
2
2
2
1
1
r
1
2
2
1
1
2
2
2
1
2
2
2
1
2
2
1
1
2
1
1
1
2
1
2
1
2
2
2
1
1
1
1
1
1
2
1
1
2
2
2
1
1
1
2
2
1
1
1
2
2
1
2
2
2
1
1
2
2
1
1
89633300
A
PAGE NO
51
FROM
26P2B25
26P2B26
26P2B21
26PZB28
26P2829
26P2829
Z6P2Bl0
26P2 B31
21P lAOI
21Pl AD 1
21P1A02
21Pl A03
21PIA03
27PlA04
21PIA04
21Pl A05
27PIA05
27PIA06
27PlA06
27P 1A01
21PIA07
21Pl A08
27PIA08
21Pl A09
27PIA09
21PIAI0
21P1A10
27PIAll
21PIAll
21Pl A12
27P lA 12
21PIA13
21PlA14
27PIA14
21PIA15
27P1A15
21PIA16
21PIA17
21PIA18
21PIA18
21PIA19
21PIA19
21P1A20
21PIA20
21P lA21
21PIA22
21P1A22
·21PIA23
21PIA23
27PLA24
27PIA25
W I
TO
15P 1A 19
25P2B05
21PIB11
l5PLBIA
21 Pl All
ZOP2415
25P2B30
25P2B31
28P1B03
13PIA1?
29Pl AOft.
13P1AIO
28Pl AOI
25PlB15
3lPlB04
28Pl R04
13P1810
25PIAlb
31P180f)
13PIBll)
28PIBOR
28PIB07
13PIB11
25P282l)
31PIBOq
13PIA16
2AP180~
25P2AIA
31PIBll
28PlB05
13PIA15
29PIA20
26Pl BIR
31PIBl1
31PlB14
26PIA19
29PIB24
29PlA30
14PIA1'28PIA15
2 8Pl A2~
14PIA14
. 14Pll\15
28P1 A21
2QPl431
26P2 A18
31P1821
31PIA2l
26P28Z0
29P1829
28P181Q
89633300 A
R E
l
I 5 T
SlGNAl-NAME
014
SHAM
OVFW*
013
WElM*
WEZM*
Me
C.3
soo
500
Doun
501
501
M)(2 L
MX2L
502
SD2
MX3l
MX3L
504
504
505
505
MX5l
M)5L
506
506
M)c6L
MX6l
507
501
OOUT8
MXOM
M)COM
,",X1M
MXIM
DQUTIO
DOUTll
5011
5011
SOlS
5015
5012
5012
OOUT12
,",X6M
MX6M
M)l5M
MX5M
Doun3
CAA15
A B 1
w.L.
89819100
89879100
89319100
89819100
89819100
89819100
89819100
89819100
89819100
8981.9100
89819100.
89819100
89819100
89879100
89319100
89819100
89879100
89819100
89879100
89819100
89879100
89819100
89879100
89819100
89819100
89819100
89819100
89879100
89819100
89879100
89819100
89819100
89879100
89819100
89879100
89819100
89819100
89819100
89819100
89819100
89819100
89879100
89819100
89379100
89879100
89879100
89819100
89879100
89819100
89819100
89879100
o
118
FR .lEV TO .LEV
1
2
1
1
1
2
2
2
2
1 .
2
1
2
2
1
2
1
2
1
1
2
2
1
2
1
1
1
2
2
2
2
1
2
1
2
2
1
2
1
2
1
1
2
2
1
1
2
1
I
2
2
1
2
I
2
2
1
1
2
2
2
I
2
2
1
I
2
2
1
2
1
2
2
1
l
2
2
2
2
1
1
2
2
2
1
1
2
2
1
2
1
1
1
2
2
2
2
1
1
2
2
1
9-111
PAGE
~O
58
FROM
27PIA26
21P lA26
27Pl A27
21P1A21
21PIA28
27Pl A28
21PIA30
21PIA30
21PIA31
21P1801
21P1802
21P1802
21P1B03
27P1803
"21PIB04
21PIB05
27PIB06
21PIB06
21P1807
21P1808
21P 1808
21PIB09
21PIB10
21P 1812
21P1813
21P IB13
21P1814
21P1814
27P1S15
21P1S16
21P18~o
21P1817
27PIBll
21P1818
21P 1818
27P1819
27PIB19
27P1820
21P1820
?1P1821
21P1821
21P1822
27P 1822
21P1S23
21P1823
21P1824
21P1825
27P1826
21P1826
" 21P1827
21P182B
. 9-112
W I R E
TO
3lP2B03
2lP2A19
21P2A12
31P2B04
31P280r;
21P2804
24PIB12
31P2B06
31 P? B09
29PIAO'
"25P18UI
31P1801
31PIB02
25PIA19
2qPIAOh
29PIAOA
28Pl"A05
13P1B l '
29PIAOq
25 P2 A20
31P1BOA
29Pl A14
29PIA11
29PIA19
25P2819
31PIA1"l
14PIBl'
28Pl B14
29PIA21j
28P1S1A
14P1810
26PIB15
31P1815
I~Pl AI0
2AP1820
26PIAlh
31PIA1£»
3.1PIB11
26P281 ~
26P2A20
31P181A
28Pl A19
14P1A15
14PIB26
2BPIA20
29P1830
29P1831
28P182'22PIA12
28P2A13
26P2Ali
l
I
S T
SIGNAL-NAME
MXl7
MX17
MPRY
MPRV
CVI01.
C~101·
WE·
WOE.
ePEC·
OOUIQ
MXOl
MXOl
M)CIl
MXll
DOt; T2
DOUT3
S03
503
OOUT4
MX4l
M)c4l
OOUT5
OOUT6
OOUT1
H)c7l
M)e1l
508
508
DOUT9
soq
509
MX2M
HX2M
SOlO
SOlO
MX3M
M)l3M
M)llM
MX1M
M)(4M
MX4M
5014
5014
SOl3
S013
OOUT14
OOUT15
CRI*
CRI*
011
P~R
AB 1
W.l.
89819100
89879100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819"100
89819100
89879100
8<;819100
89819100
89819100
89819100
89819100
89819100
89B19100
89819100
89819100
89819100
891)19100
89819100
89819100
89879100
89819100
89a 19100
89879100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89879100
89879100
89819100
89819100
89819100
89819100
89879100
89819100
89819100
89819100
89819100
898"19100
89819100
89879100
89819100
o 118
FR .lEV TO.lEV
1
2
2
1
1
2
2
1
1
2
2
1
1
1
2
2
1
1
2
2
1
1
2
2
2
2
2
2
2
1
2
2
1
2
2
"2
2
2
2
2
1
2
2
1
2
2
2
2
1
1
2
2
2
1
2
1
1
7.
2
1
1
2
"2
1
2
1
1
2
2
2
2
1
17.
1
1
1
1
2
2
2
1
2
1
1
2
2
1
1
2
2
1
2
1
1
2
2
2
2
1
2
2
89633300
A
AGE NO
W t
59
TJ
FR!)M
21P1B29
21P1829
271)1830
21P18'30
27PIR31
21P1831
27P2AOl
27P2AO 1
27P2A02
21P2A04
21P1AOS
27P2A06
21P2A06
21P2A07
21P2A08
?lP2A09
21P2A09
21P2A10
21P2AIO
21P2A11
27P2A12
27P?A14
21P2A15
27P2A16
21P2Al1
27P2A18
21P2418
27P2A19
21PlA19
27P2A20
27P2A21
27P2A21
27P2A22
27P2A21
21P2A24
27P2A25
27P2A26
27P2A28
27P2A28
21P2A30
21P2801
21P2BOl
27P2602
21P2BOl
21P280S
21P2B06
27P2808
2·1Pl809
27P2BIO
27P2B11
27P2811
16P1AOl
31 P2AIO
21P2~24
31P2AOq
31P2810
16PIBOf)
L8 Pl AOt
33P2A 11
27P2811
21 P2 B1 f)
31P2A 11
33P2All
26P2A29
29P2A20
21P2801
31P2A 11
24P1826
' 31P2811
30P1821
28P2B28
ZQP2 A01
33P2f.H4
22P2621
29P2AOt
28P2A14
33P2815
05P1A20
33P2811
16P1 BOl
29P2B21
OSPl AIR
33P2 At R
28PlAtl
23Pl A01
28P2At9
28P2821
28P2A29
33P2820
16P1AOI
23Pl AOt
33P2B12
21P2A14
28P2 AO~
27P2AOR
28P2BlO
28P2A2?
28P2A20
23Pl Aoa
29P2A2t
21P2Al1
33P2813
89633300
A
R E
L [ S T
SIGNAL-NAME
SPI*
SPI*
PRTM*
PRTH*
S WRITE*
S WRI Te*
SA15
SA15
ICA*'CO*
[SAlSa
EOX*
32KW
32KW
REF*
ICA-ICO
CRO
CRO
cePE·
cepe*
SXP.
STROBE*
M5XA*
PltM
DOUT16
P 16
SOIl
SOIl
SS*
'SS*
R/W
S016
5016
P8C
OSC*
HOLDW
RXA
LOAORA*
SRO.
SRO*
vce2
PRTSW
PRTSW
eMOR.
leA-ICO
00UT11
016
SXA*
GeMl
DISABLE
NORMAL
NCR,..AL
A 8 1 o 7/8
W.l.
89879100
89879100
89879100
89819100
89879100
89819100
89879100
89819100
89879100
89819100
89819100
89819100
89879100
89879100
89819100
89879104
8981910,.
89879100
89879100
89879100
89879100
89879100
89819100
89879100
89879100
89879100
89879100
89879100
89879100
8'l879100
89879100
89879100
89879100
89879104
89879100
89879100
89879100
89879100
89819100
89879100
89879100
89819100
89879100
89879100
89879100
89879100
89879100
89879104
89879100
89879100
89879100
FR .LEV TO.lEV
2
1
2
1
1
2
2
1
2
1
1
1
2
2
2
2
1
2
1
1
2
2
1
2
1
1
1
2
2
2
1
2
2
2
1
2
'1
1
1
2
1
2
2
2
1
2
1
2
2
2
1
2
2
1
1
Z
1
2
2
2
1
2
1
2
1
1
2
1
1
.2
2
2
1
1
2
1
2
2
·2
1
2
2
1
1
1
2
1
1
2
2
2
1
1
2
9-113
PAGE NO
60
FROM
27P2812
27P2813
27P2814
21P2815
21P2816
21P2811
27P2818
21P2818
21P2819
27P2819
27P2820
21P2820
21P2821
21P2822
27P2823
27P2821
21P2824
27P2824
21P2825
27P2826
21P2826
27P2821
21P2828
21P2828
21P2830
271»2831
28P1AOI
2APIAOI
28PIA02
28P1 A03
281»1A04
28Pl A05
28 P IA05
28PIA06
28PI A06
28PIA07
28PIA08
28PlA09
28PIA09
28PIAI0
2.8 PI A10
28PlAll
28Pl All
28PIA12
28P1A12
2SP1A13
28P1A14
28P1A15
28PIA15
28PIA16
28P1411
9-114
W
1 R E
TO
28P280A
21P2AO'2AP2A21)
21P2A04
28P2826'
28P2818
16PIAI0
33P28lf_
21P2S0A
31P2818
31P2 Al<1
'-4P1620
23P1811
28P2829
31P2820
21P1821 '
lQPlAOq
33P281A
28P2 81~
31P'-A 2'
20P2407
2QP2 A26
21P182'
33P2A2'
21p282&
28P2831
21P1A01
33P1801
29P1801
29Pl BOl
29PIA05
33P1808
21P1806
18PIAOR
33P1410
29P1816
29PIA'Ol
13P1812
18PIRO<1
25PIA21
31 PI Al 0
31P1411
25P1830
22 PI A21) ,
33P1813
21P2422
2QPIB 1<1
21PIA18
13PIAIt.
29PIA1'>
ZQPIA2A
l
J S T
SIGNAL-NAME
8
ICA.ICO·
HOLD
I SA J SO
exp*
OE*
SRSH*
SRSH*
OFEO
OFEO
MOEL
MDEl
GND
BRWRA*
GPEC*
GPEC*
SVIO*
SVIO*
AeVANCE.
PEL·
PEl*
ee*
RGPWR
RGPWR
32M
MPWR*
SOl
SOl
DINO
DIN3
DIN2
S03
S03
SA3
SA3
DIN5
OlN4
SA5
SA5
AlU3l
AlU3l
AlUll
AlUll
SP8M*
SPBM*
PRe
DIN8
SDll
SOlI
OlN6
OINlO
A 8 1
~
.l.
89819100
89879100
89819100
89879100
89819100
89879100
89819100
89819100
89879100
89819100
89819100
89879100
89879104
89819100
89879100
89819100
89819100
89819100
89879100
89879100
89819100
89819100
89879100
89879100
89879100
89819100
89879100
89879100
89879100
89879100
89879100
89819100
89879100
89879100
89879100
89879100
89879100
89819100
89879100
89819100
89819100
89879100
89379100
89879100
89a 19100
89879100
89879100
89a79100
89819100
89819100
89819100
o
118
FR.l EV TO.LEV
1
2
2
1
1
1
2
1
2
1
1
2
1
2
2
1
1
1
2
1
2
1
1
2
1
1
2
2
1
1
2
2
1
2
1
2
2
2
1
I
1
2
1
2
1
2
2
2
1
1
1
2
1
2
2
2
1
2
2
1
2
2
1
2
2
1
1
2
2
1
2
2
2
1
2
2
1
2
2
2
1
2
2
1
2
2
1
2
2
1
1
2
2
1
2
2
2
1
2
2
89633300 A
·AGf NO
61
FROM
?APIA18
28P 1A19
28PIA19
28PIA20
28PIA20
2apl A21
28PIA2l
28PlA22
28PIA22
28P 1A23
2aPl A23
2aPl A24
28PIA24
28P1A25
28PIA26
28P 1A26
28PIA27
28PIA27
28PIA28
28PIA28
28PIA30
28PIA30
28PlA31
28P lAll
2aPl60 1
28PIBOI
28PIB02
28P1603
28PIB03
2APIB04
2AP1804
2aPIB05
28P1B05
28Pl806
28P IB06
28PIB07
2AP1807
2ap 1808
28 PI B08
2AP1809
28P1609
28PIBI0
28P1810
28PIB12
28P1812
28P 1813
28PIB13
28PIB14
28P1B14
28PlBl6
28P1S17
W1 R E
Tl
2 9Pl 820
33PIBIR
27P1B22
27P1B21
33PIB2t
33Pl B2'
lAPIB06
26PIB30
31 PI 822
27PLA20
33P2B02
33P2 BOft
2.7P1AIQ
29PlB2A
18PIRO'
33P2BO'>
26Pl B27
31PIA23
31PIB23
26P182ft
33P2BOQ
lAPl BO,.
lAPl A04
33P2AIO
33PIBO'
lRPI B08
29PIA03
27Pl AOt
33PIB04
33PIB06
27Pl AO!)
27PIA12
33PIB09
33Pl BI0
27PIA 1 0
27PlAOR
33Pl All
33PIA12
27Pl A07
18PIA09
33PIA13
25P182l
31PIBIO
31PIA12
2') PUl2,.
22P"lB17
33PIB14
33PlBl't
27PIB14
29Pl A2l
29Pl~lA
89633300 A
l
I S T
SIGNAL-NAME
DIN9
5014
5014
5013
5013
SA6
SA6
ALUIM
AlUIM
5012
5012
5015
5015
OIN14
SAlO
SAI0
ALU2M
AlU2M
AlUOM
AlUCM
SAt4
SA14
SA13
SA13
SA2
SA2
OINl
500
500
S02
SC2
S07
507
506
506
505
505
SOIt
SD4
SA4
SAlt
AlU2l
ALU2l
AlUOl
AluOL
CPBM.
CPBM.
S08
508
olNtl
0lN7
A B 1
W.L.
89879100
89879100
89879100
R9879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89819100
89879100
89879100
89d79100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89819100
89879100
89819100
89819100
89879100
89879100
89819100
89819100
89879100
89819100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89819100
89879100
89819100
89879100
89879100
89879100
89879100
89819100
89879100
o
7/8
fR.lEV TO.LEV
2
1
2
?
I
1
2
2
1
2
I
1
2
2
2
1
2
1
1
2.
1
2
2
1
1
2
2
2
1
1
2.
2
1
1
2
2
1
1
2
11
2
1
1
2
2
1
2
1
2
2
1
1
2
2
1
2
1
1
2
2
2
1
2
1
1
2
1
2
2
1
1
2
2
2
1
1
2.
2.
1
1
2.
2
1
1
2
2
1
2
1
1
2
2.
1
1
1
2
2
2
2
2
2.
9-115
PAGE Nil
62
FROM
28PIB18
2APl B18
28P1B19
29 Pl 820
28Pl 82 0
2AP1821
28P1821
2AP1822
28P 1822
28P1823
28PIB23
29P1B24
28P1825
28P1826
28PlB27
28PIB27
28P1B28
28PIB28
28PIB29
2SP1829
28P1B30
28PIB30
28PtS)1
28P2 AOI
28P2A02
28P2A04
28P2A05
28P2A06
28PlA()7
2ap2A08
28P2A09
28P2A09
28P2AIO
28P2All
28P2A12
28P2A 12
28P2A13
2AP2A14
28P2A15
28 P2A1S
28P2A16
28P2A16
28P2A11
28PlAl1
2AP2A18
28P2A19
28P2A20
28P2A21
28PZA22·
28P2A23
28 Pz A24
9-116
W I
TO
27PIRIt.
33PlRl1
21P1A21)
33PIA2?
2 7Pl 81R
18PIAO"J
33PIA23
27P182h
33PIB2"j
33P2BO~
lRPlAOh
29PIB2')
29PI B2~
29P1B27
18P1801
33P2R06
26PIAli
31 P2 BO?
33P2AOQ
t8PIR07
l8PIA07
3 ~P2A 10
32P2BOl
3 OP2 BOI
30P2AC6
31P2 A06
36P2BOl
27P280?
3t;P2 A06
16P2A06
31P2fHZ
25P2 B15
2<;P2AOI)
27P182R
25P2 All)
31P2Bl~
21P187.7
21P2A17
31P2Bl1)
2SP2A16
26P2B11
31P2B16
31p2A18
25P.7.B11
29P28l1
21P2 A2427P?ROR
29P2 B21)
27Pl806
2QP2A2A
33P2 A19
R E
l
1ST
5 IGNAl-N"~E
509
5D9
CAA15
5010
5010
SAil
SAIl
CRI*
CRI*·
SA1
SA1
DIN12
0lN15
OlNl3
SA12
SA12
ALU3M
ALU3M
SA9
SA9
SA8
SA8
OX3*
OXl"
MOXl*
MOX2*
OX7*
CMDR*
MOX6*
MOX7*
ALU7l
ALU7l
0lN17
PAR
AlU6l
AlU6l
017
P16
AlU5l
ALU5L
AlU4M
AlU4M
AlU4L
ALU4L
ACA8
HCLOw
SXA*
ARA3
016
ARA2
SAO
A ti 1 o 7/8
w.L.
89879100
89819100
89819100
89819100
89879100
89879100
89379100
89879100
89879100
89819100
89879100
89819100
89879100
89819100
89879100
89879100
8<1879100
89819100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89879100
89819100
89879100
89879100
89879100
89879100
89879100
89879100
89819100
B9879100
89879100
89679100
89879100
89879100
89879100
89819100
89879100
89819100
89879100
89879100
8ii379100
89879100
FR.LEV TO.lEV
2
1
1
1
2
2
1
2
1
1
2
2
2
2
2
1
2
1
1
2
2
1
1
1
1
i
1
2
1
1
1
2
2
2
2
1
2
1
1
2
2
1
1
2
2
1
2
2
1
2
1
2
1
1
1
2
2
1
2
1
1
2
2
2
2
2
1
2
1
I
2
2
1
1
1
1
1
1
2
1
1
1
2
2
2
2
1
2
1
1
2
2
1
1
2
2
1
2
2
1
2
1
89633300
A
'AGE Nt1
63
"
I
Tn
FROM
78P2A24
28P2A25
28PlA26
7. 6P 7. A 2 7
28P2A28
28P2A29
281l2B01
28P2B02
28P2803
28P2804
28PlB05
28P2B06
28P2801
28P2808
28P2809
28 P2 B09
28P2B10
28P2B10
28P2B11
28P2812
28P2813
28P2813
28P2814
28P2815
28P2816
28P2816
28P2811
28P2818
28P 2B19
28P2B20
28P2B22
28P 282·3
28PlB24
28P2.825
28P2825
2AP2B26
28P2B27
28Pl828
28P2B29
281)2B30
2'1P2831
2RP2831
29P 1A02
29Pl A02
29P1403
29PIA03
29PIA04
29PIA04
29PIA05
29PIA05
29PIA06
1AP1A07
271>2814
2QP282lt
29P2A24
29P2A30
27P2A2ft
31Pl!30l
32P2 AOft
Z9P2AOh
33P2A06
35P2 BOl
34P2BOl
34P2 AOn
21P2 B1'
31p7A11
26P2A1&
29P2 A02
21P2805
33P2801
29P2404
26P2815
31 P2 B14
27P2825
29P2425
26P2A15
31p2817
29P2823
27P2811
29P2R26
29P2427
29P2A29
29P2B28
29P2A21
18P180::l
33P2819
27P2 B13
21P2A2')
21P2411
21P7. 82'
2.9P282.9
29P2830
21P2831
21P1801
30P1 A01
28P1802
30P1A01
21Pl AOZ
30PIA04
28PIA0430P1 AD')
30P1406
89633300 A
R F
l
I
S T
SIGNAl-N~ME
SAO
HOLD
1 K2*
1K3*
1KO*
LOAORA*
DX2*
MDX3*
MDxn*
MOX4*
0)(6*
0)(5*
MDX5*
B
ALU5M
AlU5M
OOUT11
DOUT17
OX4*
0lN16
AlU7M
AUnM
ADVANCE*
ARAO
AlU6,.,
AlU6,.,
A(A6
OE*
A(A5
4(A9
ARAI
ARA4
A(A1
SAl
SAl
cxp*
R )CA
SXP*
BRWRA*
1K1*
MPWR*
MPWR*
DOUTO
oeUTO
DINI
DINl
OOUTI
DOUTl
DIN2
0lN2
00UT2
A B 1
W.L.
89879100
89879100
69879100
89879100
89379100
89879100
89879100
89d 79100
69879100
89879100
89879100
89879100
89319100
89819100
89619100
89819100
89879100
89879100
89819100
89819100
89819100
89819100
89879100
89879100
89879100
89379100
89879100
89879100
89819100
89819100
89879100
89879100
89879100
89879100
89879100
89879100
a9a 79100
89879100
89879100
89879100
89879100
89879100
89iJ 79100
89879101
89879100
89879101
89879100
89879101
89879100
8987910 1
89879101
o
7/8
FR..LEV· TO.LEV
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
2
2
1
2
2
2
1
2
1
1
1
2
2
1
1
2
2
1
2
2
2
1
2
1
1
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
2
2
1
2
2
1
2
1
2
1
2
1
2
1
1
I
2
2
1
2
2
1
2
1
2
1
2
1
2
1
1
9-117
P4GE NO
64
FROM
2~PIA06
29P 1 A07
29PIA01
29Pl A08
29PlA08
29P1A09
29Pl A09
29 P IA14
29PIA14
29PIAlS'
29Pl A1 5
29PIA11
29P lAl1
29PIA18
29PIA18
29P 1A19
2~P1A19
19PIA20
29PIA20
29PlA25
29PIA25
29PIA21
29PIA21
29P lA28
29PIA28
29P1A30
29P lA30
29PIA31
29PIA31
29PIA03
29P180 3
29P IB07
29P1807
29P1816
29P 1816
2~P1819
29Pl B19
29PIB20
2~P1820
, 29P1824
29P1824
29Pl 82 5
29P IB25
29P1826
29Pl B26
29P1821
29P1821
29P1828
29P1828
29P1829
29P1829
9-118
W1 R f
Tl,
27P1804
28P140A
30PIA01
27Pl ROI)
30PlAOA
30PIA09
27PlB07
21P1809
30PIA14
28PIA16
30PIAll)
lOP1411
27PIA 10
2APlSl1
lOPl AlA
27PIBl'
30PIA19
21PIA13
30PIA20
27 PI Bll)
30PIA20
28P1B16
30PlA27
10PlA2A
l8P!A17
27Pl A17
30PIA]0
21PIA21
30PIA31
28PIA02.
30P180l
28PIA03
30PIB07
30Pl Bl"
28PIAOl
28PIA14
30PIB19
28PIAIA
30Pl820
21PIA16
30PIB24
30Pl B21)
28PIB24
30Pl B2l.
28Pl821)
30PIB21
28PIB26
28PI A21)
30P1828
21Pl A24
JOP1829
l
I
S T
S JGNAt-NAME
00UT2
OIN't
0lN4
DOUT3
QOUT3
00UT4
00UT4
00UT5
OC-UT5
DIN6
o IN6
00UT6'
00UT6
0lN7
OIN7
00UT1
DOUTl
00UT8
00UT8
oeuT9
00UT9
DIN 11
DINII
DINIO
OINIO
OOUTll
OOUTll
OOUT12
DOUll2
DINO
OINO
DIN3
DIN3
DINS
0lN5
0lN8
0lN8
0lN9
0lN9
OOUll 0
OOUTlO
OlNI2
0lNl2
OlN15
olN15
OINll
0lN13
DIN14
0lN14
OOUT13
OOUTl3
A B 1
W.L.
89B79100
89879100
89879101
89819100
89879101
89879101
89819100
89819100
89819101
89819100
89879101
89879101
89819100
89819100
89879101
89819100
89819101
89819100 .
89819101
89819100
89879101
89879100
89879101
89379101
89819100
89819100
89819101
89879100
89819101
89819100
89819101
89819100
89879101
89819101
89819100
89819100
89879101
89819100
89879101
89819100
89819101
89819101
89819100
89819101
89879100
89879101
89819100
89819100
89819101
89819100
89819101
o
11A
FR.lEV TO.lEV
2
2
1
2
1
1
2
2
1
2
1
1
2
2
1
2
1
2.
1
2
1
2
I
1
2
7.
1
2
1
2
1
2
1
1
2
2
2
2
1
2
1
1
2
2
1
2
1
1
2
2
1
2
1
2
1
2
I
2
1
1
2
2
1
2
1
2
1
2
1
1
2
2
1
1
2
1
2
1
1
2
1
2
1
2
2
1
2
1
2
1
2
1
I
2
1
2
1
2
2
1
2
1
89633300
A
'AGE NO
65
W IRE
TO
F.R)"
29P1830
29PIB30
29P 1831
Z9P1831
29P2A01
29PZAOl
29P2A02
29P2A02
29PZA04
29P2A04
29PZA05
29P2A05
29P2A06 .
29P2A07
29P2A07
29P2A16
29PZA20
29P2A20
29P2A21
29PlAl1
29P2Al3
19P2A23
29PlAZ4
29PlAZ4
29P2A25
2~PlA2S
19P'-A26
2CJP2A26
29P2A27
Z9PZA27
29PZAl8
29PlAl8
lCJPlA29
29P2A29
29P2A'J0
211PlA30
2~P28l2
29P2Rl2
2CJP2823
29P2823
29P2B24
29PlBl4
29P282S
Z9PZB2S
19PZ8l6
29Pl826
29P2B21
29P2827
29P2B28
29P2828
2CJP2B29
Z1P18Z4
lOPl B 30
30P1831
21P1825
27P2A 16
30P2AOl
Z8P2810
30P2A02
30P2A04
28P2812
28P2AI0
30P2 AOli
28P280]
30P2AOl
21PZA12
20P28Z7
10P2A20
Z7PZ A07
21P2BI0
30PZ All
10P2A21
28P2824
28PZA21
30P2 Al4
30PlAl'i
lRP2R1'i
21Pl8l7
30P2A26
28P28Z0
30PlA27
28P2Al3
10P2 AlA
l8P2821
30Pl A29
28P2A2R
30P2Al0
30Pl822
28P2AIR
28P28l7
lOP2821
28P2A26
30P2824
10Pl821i
28P2A21
28 Pl 81CJ
10P2826
JOPl821
21P2A20
28P2B23
10P282R
l8P2 830
89633300 A
liS T
S (GNAt-NAME
00UT14
00UT14
00UT15
OOUT15
OOUTl6
00UT16
OCUT11
ooun 7
0lN16
0lN16
DINl1
DIN11
MOXO.
STR08E.
STROBE •.
"5S
REF·
REF*
DISABLE
OISASlE
ACAl
ACAl
1K3*
lK3*
ARAO
ARAO
CE.
CE*
ACA9
ACA9
ARA2
ARA2
ARAI
ARA1
1KO·
lKO*
ACA8
ACAR
ACA6
ACA6
lK2*
lK2*
ARA3
ARA3
ACA5
ACAS
R/W
R/W
ARA4
ARA4
11<1 *
A B 1 0 7/8
w.t.
89819100
89819101
89819101
89819100
89819100
89819101
89819100
89tl79101
89819101
89819100
898i9100
89819101
89819100
89819101
89a79100
89819100
89819101
89879100
89819100
89819101
89819101
89819100
89819100
89879101
89819101.
89879100
89879100
89879101
89879100
89879101
89879100
89879101
89919100
89819101
89819100
89879101
89819101
89819100
89879100
89879101
89879100
89819101
89879101
89819100
89879100
89879101
89879101
89879100
89819100
898,79101
89819100
FR.LEV TO.l.EV
2
1
1
2
2
1
2
1
1.
2
2
1
1
1
2
1
1
2
2
1
1
2
2
1
2
1
1
2
2
1
1
1
2
1
1
I
2
2
I1
2
2
1
2
2
2
1
1
2
Z
I
1
2
2
1
2
1
1
2
1
2
2
1
2
1
2
1
2
.1
1
1
I
1
2
2
1
2
1
1
2
2
1
1
2
2
1
2
1
2
2
1
2
1
1
2
2
1
1
2
2
1
2
9-119
PAGE NO
66
FROM
291»2829
29P2830
29P2830
30P1402
30P1402
30P1403
30PIA03
30P1404
30P1404
30PIA05
30P1405
30P1406
)OPIA06
30P1407
30P1407
30PIA08
30P1408
30PIA09
30PIA09
10PIA14
·30PIA14
30P1415
30P1415
30P1Al1
30P1417
10P1A18
3OP1418
30P1419
30P1419
30P1420
301»1A20
30P1420
30P1425
30P1427
30P1421
10P1428
30PIA28
3OP1A30
30P1430
)OPI A31
10PIA31
30P180]
30P1803
30P1801
30P1801
10P1816
30P1816
30P1819
30P1819
30P1820
30P1820
9-120
W I A E
m
.30P282Q
28P2831
30P2830
29P140'31 PI 40'"
29PIAO~
31PIA01
29Pl AOft
31P1404
29P140ai
11P1401)
29P1AOft
31Pl A06
29PIACl
31P1401
31Pl AOA
29PIAOA
29PIA09
31 PI 409
19P1414
31P1414
29Pl All)
31P1415
31Pl A17
29P1417
29PIA18
31Pl AlA
29P1419
31P1419
29P1420
31P1A20
'29P1421)
31P1420
29PIA27
31 PI A21
29PIA2A
31P1428
29Pl A30
31PIA30
29PIA31
31PIA31
31P180~
29P1801
2QP1801
':JIP1801
31P1816
29P181'6
31P1819
29P1819
31P1820
29P1820
l
J S T
S IGNAl-N·AME
lKl·
MPWR.
MPWR*
OOUTO
OOUTO
OINt
OIN.l
OOUTI
DOUTI
0lN2
DIN2
DOUT2
00UT2
OIN4
DIN4
DOUT3
DOUTl
00UT4
00UT4
DOUT5
00UT5
DIN6
0lN6
000T6
00UT6
DIN7
DIN7
00UT7
00UT7
00UT8
00UT8
00U19
00UT9
olNtl
OINll
0lNI0
OINIO
OOUT11
OOUTll
00UT12
00UT12
OINO
OINO
0lN3
DIN3
DINS
0lN5
OlN8
0lN8
DIN9
0lN9
A 8 1
~.l •
89879101
89879100
89879101
89819101
89879101
89879101
89879101
89879101
89879101
89879101
89879iol
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89819101
89819101
89879101
89879101
89819101
89879101
89879101
89879101
89879101
89819101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89819101
89879101
89819101
89879101
89879101
89879101
89819101
89819101
o
7/8
fA.lEV TO.lEY
1
2
1
1
2
1
2
1
2
1
2
1
2
1
2
2
1
1 .
2
1
2
1
2
2
1
1
2
1
2
t
2
1
2
1
2
1
2
1
2
1
2
2
1
1
2
2
1
2
1
2
1
1
2
1
1
2
1
2
1
2
1
2
1
2
1
2
2
1
1
2
1
2
1
2
2
1
I
2
1
2
I
2
1
2
1
2
1
2
1
2
1
2
2
1
1
2
2
1
2
1
2
1
89633300 A
)AGE
~O
&7
W I R E
TO
FROM
30PIR23
30P1823
30Pl8Z4
lOP18?4
30P18Z5
30P1825
30PIB26
30P1826
30P1827
101)1B27
30P1828
10P.l828
30P1829
30P1829
lJPlB30
lOPIB30
30PIB]l
lOP 1831
10P2AOl
30P~AOI
30P2A02
30PZA01
30P2A04
30P2A04
30P2AOlj
30P2A05
30P2AOb
30Pl A07
30P2A07
lOP2A20
10P2A20
30P2A21
10P2 A21
30P.?A?3
3JP2A23
10P2A24
3()P2A14
30P2A25
30P2A15
30P1A26
30P2A2b
30P2A21
lOPZA27
10P2A28
10P2A28
lOP2A29
30P2A29
10P2A30
30P2A30
30,.2BOI
30P2822
27P2AIO
20PIA2A
31 P18Zft.
29P1824
31Pl811)
29Pl821j
29P182la
11 P182£.
3tPl827
29PIB21
31Pl81R
29P182R
29Pl819
3lPIB29
31P1830
29PI BlB
29P18'U
31Pt831
29P2AOl
31P2AOl
.llP2AO?
29P2AO'
2C;P2A04
31P2 A04
31 P2 A05
2C;P7AOI)
28P2A02
29P2 A07
31P2A07
29P2 A20
31P2A20
29P2A21
3lP2 A21
29P2A21
31P2A23
29P1A24
31P1A11t
29P2AZI)
31P2A21)
31P2416
29P2426
29P2A21
3lP2A21
29P2 A2A
31PZA2R
29P2A29
31 P2 A29
31P2A30
29P2A1O
28P2AOl
19P2817
89633300
A
l
I
S T
S·IGNAl-N~ME
CCPE*
cePE.
oOUTIO
oOlll10
DIN12
OlN12
DIN15
DINl5
DIN13
OlN13
OINIIt
0lN14
00UT13
00UT13
00UT14
oOUT14
00UT15
00UT15
00UT16
oOUT16
00UT17
OOUll1
OlN16
0lN16
olNll
OlNl1
MDXl.
STPOBE.
STROBE*
REF*
REF*
DISABLE
DISABLE
ACA7
AeAl
lK3*
lK3*
ARAO
ARAO
ce*
CE*
ACA9
ACA9
ARA2
ARAZ
ARAI
ARAI
lKO.
lKO*
OXl*
AeA8
A 8 1
w.L.
o 118
FR.lEV TO.LEV
89879100
89879100
89879101
89819101
89879101
89879101
89879101
89879101
89879101
89879101
89819101
89819101
89879101
89879101
89879101
89819101
89819101
89819101
89819101
89879101
89819101
89819101
89819101
89819101
89819101
89879101
89819100
89819101
89819101
89819101
89819101
89879101
89879101
2
1
2
1
2
1
1
2
1
2
2
2
1
2
1
1
2
2
1
1
1
8~879101
1
89819101
89879101
89879101
89879101
89819101
89879101
89879101
8'J87910 1
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879100
89819101
2
2
1
2
2
1
1
2
2
1
2
1
1
2
2
1
1
2
2
1
1
2
1
2
2
1
1
2
2
2
1
1
1
1
1
1
2
2
1
2
2
1
2
1
Z
1
2
2
1
1
Z
1
2
1
2
2
1
1
1
1
1
2
1
2
1
2
1
2
Z
1
1
Z
1
2
1
Z
2
1
1
1
9 -121
P4GE Nil
68
FROM
3OP2822
30P2823
30P2823
30P2824
30P2824
30P2825
30P2825
30P2826
30P2826
30P2821
30P2827
30P2828
30P2828
30P2629
30P2829
30P2830
30P2830·
31PIA02
31P1402
31PIA03
31PIA03
31P1404
11PIA04
31P1405
31PIA05
31P1406
31PIA06
31P1401
31P1401
31P 1A08
31PIA08
31PIA09
.31P1409
31PIAI0
31P1411
31p1412
31P1413
31PIA14
31P1414
31P1415
31PIA15.
31P1416
31PIA11
31PIA11
31PIA18
31P1418
31P1419
31P1419
31P lA20
31PIA20
31P1A20
9-122
W I
T1
31 P282:?
29P2B2~
31P2823
29P2 B2~
31P2824
29P282'S
31 P2 82'S
29P282f»
31P2826
31P2827
29P2827
31P282A
29P2R2A
29P2829
31P2829
31p2830
29P2830
32P1401
30PIA02
32PIA01
30P1401
30P1404
32P1404
:l2P1405
30PIAO,)
32Pl A06
30PIA06
30P1407
~2Pl 407
32P1A08
30P1408
30PIA09
32P1409
28Pl AI0
2APIA 11
28P1812
21P1811
30P1414
32PIA14
32plAl1)
30P1411)
21P1819
32P1417
30P1Al1
10Pl A.1A
32P141A
32P1419
30P1 A1 q
30PIA21)
32PIA20
30P1420
R E
l I S T
SIGNAL-NAMe
ACA8
ACA6
ACA6
1 K2*
lK2*
ARA3
ARA3
ACA5
ACA5
R/W
R/W
ARA4
4RA4
lKl*
lKl*
MPWR*
MPWR*
OOUTO
OOUTO
o INI
OINI
DOUT1
OOUT1
DIN2
0lN2
OOUT2
DOUT2
0lN4
DIN4
DOUT3
OOUTl
00UT4
OOUT"
AlU3l
AlUll
AlUOl
M)ell
DOUT5
DOUT5
0lN6
0lN6
MX3M
00UI6
DOUT6
DIN7
DIN1
OOUT1
OOUT1
DOUT9
OOUT8·
00UT8
A 6 1
W.l.
89879101
89879101
89819101
89879101
89819101
89819101
89819101
89879101
89819101
·89819101
89819101
89879101
89819101
89819101
89819101
89819101
89819101
89819101
89819101
89819101
89819101
89819101
89819101
89819101
89819101
89819101
89819101
89819101
89819101
89879101
89879101
89879101
89879101
89819100
89879100
89819100
89819100
89819101
89819101
89819101
89819101
89819100
89819101
89819101
89819101·
89819101
89819101
89819101
89879101
89819101
89879101
o
7/8
FR.lEV TO.l:eV
2
1
2
1
2
1
2
1
2
2
1
2
1
1
2
2
1
1
2
1
2
2
1
1
2
1
2
2
1
1
2
2
1
1
1
1
1
2
1
1
2
1
1
2
2
1
1
2
2
1
2
2
1
2
1
2
1
2
1
2
2
1
2
1
1
2
2
1
1
2
1
2
2
1
1
2
1
2
2
1
1
2
2
1
1
1
1
1
2
1
1
2
1
1
2
2
1
1
2
2
1
2
89633300 A
~
AGE NO
~9
FR)M
W (
TO
31P1A22
31P1A23
31PIA25
3lPIA27
31PIA27
31PIA28
31PIA28
3LPIA30
31PlA30
l1PIA31
31P1A31
31P1BOI
.31PIB02
31PIB03
31PIB03
31Pt804
liP 1806
31P1807
31PIB07
31P1808
l1P1SOq
31P1810
31P1812
31P1813
31P1814
31P1815
31P1816
31'1816
31P1817
31P1818
31P1B19
31P1B19
31PIB20
31P1820
31P1821
31P1822
31P1823
31P1824
31P 1~24
31P1825
31P1825
.31P1826
31P1826
31P1B27
31P1827
31Pl828
31P1828
31P1829
31PIR29
31P1830
31P1830
21PIA23
28Pl A27
32PIA20
30Pll27
32 PI A21
32PIAlR
30P1 A2q
32P1 A.30
30PIA10
30Pl An
32PIA3t
21P1802
27PIB01
30PIB03
32P1803
27P1A04
21P1A06
30P1B07
32P1807
27PIBOA
21Pl AO
33PIA01
33PIA01
]3Pl~08
33P1A08
33 PI A09
33PIA09
33P1A1O
3'3P2A23
31P2 A23
31P2A24
33P2A24
31P2 A25
33P2A2c)
31P2A26
33P2 A26'
31P2A27
33P2 A21
33P2 A2,.
'3lP2A2A
13P2 A29
31PlA2Q
33P2A30
31 P2 A30
2APIBn
31P2B27
33P252?
33P2823
3lP2 B21
33P282431P2824
31P2B21)
33P2 8 21)
31P2B26
33P2B26
33P2827
31P2B21
31 P2 R2A
33P282A
31P2829
33 PZ B2q
33P2830
32PIA02
34Pl A02
32PIAOl
34Pl A03
34PIA04
32PIA04
34Pl AOI)
32PIA05
32PIA06
34Pl AO&
34Pl,A07
32PIA01
34Pl AOA
32PIAO~
34Pl A09
32P1A09
28PIA06
89633300 A
l
1ST
SIGNAl-NAf4E
ACA1
ACA1
11<3*
lK3*
ARAO
ARAO
CE*
CE*
ACA9
ACA9
ARA2
ARA2
ARAI
ARAI
lKO*
lKO*
0)(3*
ACA8
ACA8
ACA6
ACA6
lK2*
lK2*
ARA3
ARA3
ACAI)
ACA5
R/W
R/W
ARA4
ARA4
1Kl*
lKl*
MPWR*
OOUTO
OnUTO
OINl
OINI
DOUTI
DOUTl
DIN2
OIN2
00UT2
OOUT2
DIN4
0lN4
OOUT3
00UT3
OOUT4
OOUT4
SA3
A B 1
\tI.l.
o 7/8
FR.l EV TO.LEV
89~ 19101
89819101
89879101
89879101
89819101
89879101
89879101
89819101
89819101
8987?101
89819101
89819101
89819101
89819101
89819101
89819101
89819100
89819101
89879101
89819101
89879101
89879101
89819101
89819101
89819101
89819101
89819101
89879101
89819101
89819101
89819101
89819101
89819101
2
1
1
2
89~19101
2
2
1
1
1
89819101
89a19101
89819101
89819101
89819101
89819101
89879101
89819101
89819101
89879101
89819101
89819101
89819101
89819101
89819101
89879101
89819100
2
1
1
2
1
1
2
1
2
2
1
2
1
2
2
1
2
2
1
2
1
2
1
1
1
2
2
1
2
1
2
1
1
1
2
2
2
1
2
1
1
1
1
2
1
2
1
1
2
2
1
1
2
1
1
1
2
1
2
2
2
2
1
Z
1
2
1
2
2
1
1
2
1
2
2
Z
2
1
2
1
2
2
1
1
2
1
2
1
1
2
1
2
1
9-127
P.GE
NO
74
FROM
33P1Ali
33PIA12
33P1A13
3.3PIA14
33P1A14
33PIA15
33PIA1S
33PIA16
33PIA17
33PIA17
31PIA18
33PIA18
33PIA19
1'4P1419
33PIA20
33P1420
3)PIA20
33P1422
33PIA23
33P1425
31PIA27
33P1427
33PIA28
33PIA28
33PIA30
33P1A30
33P lA31
13P1A31
33PIBOI
33P1802
33P1803
33P1803
33P1804
33P1806
33P 1807
13P1807
33P1808
33P1809
33P1810
33P1812
])P1813
13P1814
33PIB15
31P1816
33P1816
33P1817
33P1818
33P1819
33P 1819
3JP1820
3~P1820
9-128
W· IRE
.T)
28P1807
28PIB08
28Pl B09
32PIA14
34PIA14
34PIA15
32PIA15
28PIA15
34PIA17
32PIA17
32PIA18
14P1418
32P1A19
34PIA19
32PIA25
32PIA20
34PIA20
28P1820
28P1B21
~4P1 A20
14P1427
32P1427
34Pl A2~
32P1A2A
34Pl A30
32PIA30
34P1431
32P1431
28P1401
iSPIBOl
32P180'
34PIBOl
28P1801
28P180~
34Pl807
32P1807
28Pl A05
28P1805
28 PI BO"
2SP140CJ
2SPIA12
28P1811
28P1814
34P1816
32P1816
' 28P1819
28P1AIQ
34PIRICJ
32PIB1Q
32P182()
)4P1820
.,
liS T
S IGN4l-N·4ME
SOS
S04
S~4
OOUTS
DOUT5
0lN6
DIN6
SOli
OOUT6
OOUT6
DIN7
0lN7
DOUT1
DOUT7
OOUT9·
DOUT8
OOUT8
SOlO
SAIl
OOUT9
DINll
DINtl
OlNI0
DINI0
OOUT11
DOUlll
DOUT12
OOUT12
SOl
SA2
DINO
DINO
500
502
OIN3
DIN3
503
S07
SC6
SA5
SP8N*
CP8M*
508
DINS
DIN5
S~q
5014
DIN8
DIN8
0lN9
OlN9
AB 1
W.l.
89879100
89879100
89879100
89879101
89879101
89879101
89879101
89879100
89879101
89879101
89879101
89819101
89879101
89879101
89879101
89879101
89819101
89879100
89879100
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879100
89879100
89879101
89879101
89879100 .
89879100
89879101
89879101
89879100
89879100
89879100
SQ879100
89879100
89879100
89879100
89819101
89879101
89879100
89879100
89879101
89819101
89879101
89879101
o
1/8
FR.lEV TO.lEV
1
1
1
2
1
1
2
1
'I
2
2
1
2
1
2
2
1
1
1
1
1
2
1
2
1
2
1
2
1
1
2
1
1
1
1
2
I
1
1
1
1
1
1
1
2
1
1
1
2
2
1
1
1
1
2
1
1
2
1
1
2
2
1
2
1
2
2
1
1
1
1
1
2
1
2
1
2
1
2
1
1
2
1
1
1 '
1
2
1
1
1
1
1
1
1
1
2
1
1
1
2
2
1
89633300
A
PAGf NO
75
FROM
W I
TO
33PIB21
33PIB22
~3PIB23
33PIB24
33PIB24
33P lB25
33PIBl5
33PIB26
33P IB26
3lPIB27
31PIB21
33PIB28
33PIB28
31PIB29
3::iPIBl9
31PIB30
311»1830
3~PIB31
33Pl B31
33P2A01
33P2 AOl
33P2A02
3]P1A02
33P2A04
33P?A04
33P2A05
31P2A05
33P2A06
33P2A07
33P2A07
33:l2A09
33PZAIO
33PlA 11
33P2A12
33P2A13
33P2A18
31PZAL9
33P2A20
33P2A20
33P~ A21
33P2A21
33P2 A22
3"JP2A23
3.3P2A23
3·:lP2A24
33P2A24
3~P2A25
33P2A25
33P2A26
31P 2A26
33P2A21
28Pl A20
2 8Pl A21
lRPlB27
32PlB24
34Pl B2~
34PlB 21)
32Pl B2"i
34Pl B 2f1
32PlB2f1
32PIB27
l4PIB27
34PIB28
32PlBlR
3lPIB7Q
34PIBl9
34PIB10
32PIB 30
32PIB31
34PIB 3(
34P2AOI
32P2 A01
37P2A02.
l4P2A07
34P2 AO\.
32P2A04
34P2AOl)
32 P2 AO"i
?AP2B04
32P2 A07
34P2 A07
l8PIBZCJ
Z8Pl B30
2TP2AOl)
Z1PlAOI
27 P2 AOIt
27PZA21
28PlAZ4
34PZ A20
32P2AZO
34P2 A21
32P2 A21
27P2B2A
34P2 A23
32P1A23
34P2 AZ4
~Z P2 A2it
34P2A21)
32P2 A25
32P2 A2b
34P2A26
34P2 A21
89633300 A
R E
l
I S T
SIGNAL-NAME
S013
SA6
CRt*
00U110
00U110
OlN12
OINl2
OINlS
DIN 15
OINl]
OINl]
DIN 14
OlN14
DOUTt3
00UT13
00UT14
00UT14
OOUT15
OOUTlS
OOUT16
00UT16
nOUTl1
00UT11
0lN16
OlN16
DIN 17
OlN17
MOX4*
STROBE*
STROBE*
SA9
S~8
EOX*
SA 15
~lKW
S016
SAO
REf*
REf*
DISABLE
OISABlE
RGPWR
ACA7
ACA 7
lK3*
lK3*
APAO
ARAO
Cf*
CE*
ACA9
A B 1
.... L.
89819100
89d 19100
89819100
89879101
89879101
89819101
89819101
89819101
89819101
89819101
80}8 79101
69819101
89819101
89879101
89819101
8'1819101
89819101
89<:1 19101
89879101
891319101
89879101
89879101
89819101
89819101
89819101
89819101
89819101
89819100
89819101
89819101
89819100
89319100
89819100
89a19100
89379100
89819100
89819100
89a 1910 1
89619101
89879101
89819101
89819100
89819101
89819101
89879101
89819101
89819101
89819101
89879101
89819101
89;)79101
o
118
FR.lEV TO.lEV
1
1
1
2
1
1
2
1
1
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
1
2
1
2
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
2
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
1
2
1
2
1
1
1
1
1
1
1
1
2
1
2
1
2
1
2
1
1
1
2
1
1
2
1
2
1
2
2
1
2
1
1
1
2
1
2
9-129
PAGE
~1
16
FROM
33P2A21
33P2A28
3JPlA28
33P2A29
33P2A29
31P2A30
33'2A30
33P2801
31P2802
331»2803
33P2804
33P2805
33P2806
33P2809
33P2810
33P2811
33P2812
33Pl813
33P2814
33P2815
33P2816
33P2811
33P2818
33P2819
33P2820
33P2822
33P2822
33P2823
33P2823
3)P2824
33P2824·
33P2825
33P2825
33P2826
))P2826
33Pl821
33P2821
33P2828
33P2828
33P2829
~3P2829
31'2830
33P2830
3~Pl A02
14PIA02
34PIA03
)~PIA03
34PIA04
34PIA04
34PIAOS
34PIA05
9-130
W f R E
TO
32P2A21
34P2A29
32 P2 A2J1
34P2A29
32P2A29
34P2 A30
32P2A30
28P2811
28P1A21
28P1821
28Pl A24
28PIA26
28P1821
28P1 A30
28PIA31
23P1AOli
27P2801
21P2811
21P2A14
27P2 A1J1
21P2818
27P2 A19
21P2824
28P282'i
21P2 A2A
32P282'34P2822
32P2821
34P2821
34P2824
32P2824
32P2S2~
34P2821i
34P2826
32P2826
34P2827
32P2827
34P2828
32P282A
34P2829
'32P2829
32P2830
:)4P2830
33PIA02
35PIA02
15Pl A03
33 PI AO=l
33PIA04
35PIA04
33 PI AOli
35P1 A05
lIS T
SIGNAL-NAME
ACA9
ARA2
ARA2
ARAl
ARAI
1KO*
lKO*
OX4*
5012
SA1
5015
SAI0
SA12
SA14
SA13
GOM2
PRTSW
NORMAL
ft4SXA*
5011
SRSM*
SS*
5'110*
SAl
SflQ*
ACA8
ACA8
ACA6
ACA6
lK2*
lK2*
ARA3
ARA3
ACA5
ACA5
R/W
R/W
ARA4
ARA4
1Kl*
1Kl*
MPWR*
MPWR*
OOUTO
DOUlO
DINt
OINI
Doun
OOUTI
DIN2
OlN2
A 8 1
o
118
W.l.
FR .lEV
89879101
89879101
89819101
89819101
89819101
89819101
89819101
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819104
89879100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819100
89819101
89819101
89819101
89819101
89819101
89819101
89819101
89a19101
89879101
89819101
89819101
89819101
89879101
89819101
89819101
89819101
89819101
89819101
89819101
89819101
89819101
89819101
89819101
89819101
89879101
89819101
2
1
2
1
,2
1
2
1
TO.lEV
2
1
2
1
2
1
1
·1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
.1
1
1
2
1
2
1
1
2
2
1
1
2
1
2
1
2
1
2
2
1
1
2
2
1
1
2
1
2
1
1
1
2
1
2
1
1
2
2
1
1
2
1
2
1
2
1
2
2
1
1
2
2
.1
1
2
1
2
89633300 A·
PAGE NO
W I
77
R E
Tn
fRlf14
"3~PIAOb
~4PIA06
14PIA07
34P1A07
34PIAOS
lft-PlA08
34PIA09
34PIA09
3ft-P1Al4
34PIA14
l4PIA15
34PlA15
34P1A17
34PIA17
l4Pl A18
14PIA18
14PIA19
34PIA19
14P lA20
3ft-PIA20
l4PIA20
l4PlA25
]4Pl A27
34PIA21
34PIA28
34PI A2 8
34PIA30
3ft-P1A30
]4PIA31
34PIAl1
3ft.P180]
34P180]
3ft-PIB07
3ft.Pl B07
34Pl616
34PIB16
34P1819
34P 1819
14PIB20
3ft-P1820
34P1824
14P1824
34P1B25
34PIB25
14P1B26
34PIB26
14P1821
34P1 1'2 7
34P lB28
34Pl828
14P1829
1ST
SIGNAL-NAME
35Pl AOE»
33PLAOb
33PlA07
35 Pl A07
33PIAO~
.11)Pl AOA
33Pl AOq
31)P 1A 09
35PlAl4
33PlA14
33PIAl1)
11)P1UI)
33PlA17
35PIA17
35Pl Al ~
3'P1A1A
33PIA19
35Pl Al q
31)P1A20
13P1 A2()
33PIA21)
11)P1A20
35PIA27
31PIA21
'J5PIA2A
33Pl A?A
33PIA 10
35PIA30
35Pl A31
3.3PlA31
33PIB03
35PlBO':\
33Pl807
15Pl B07
35PIBl6
33P1816
35Pl BIC,
3]PIB 1 q
31)P1B20
33PIB2n
33P1824
35P1B24
33P1821)
35PlB21)
3.3P1826
35PIB26.
35P1B27
33P1827
35PIB2A
33P1828
33PIB2Q
89633300
t
A
OOUT2
DOUT2
OIN4
DIN4
00UT3
DOUT3
DOUT4
OOUT4
OOUT5
DOUT5
DIN6
OlN6
00UT6
00UT6
OlN1
DIN7
DOUT1
DOUT1
DOUT8
DOUT8
OOli19
00U19
OINll
OINtl
OlNI0
DINIO
00UT11
OOUTll
OCUTll
00UT12
DINO
OINO
DIN3
DIN]
DINS
DIN5
DIN8
DIN8
DINq
DIN9
DOUTI0
DOUTI0
DIN12
D[N12
DINl5
DIN15
OlNl3
OINl]
DIN14
DIN14
DOUTl3
A 8 1
W.L.
89879101
89879101
89879101
89819101
89819101
89879101
89879101
89879101
89819101
89879.101
89879101
89819101
89879101
8913 19101
89819101
89879101
89879101
89819101
89819101
89819101
89879101
89879101
89879101
89819101
89879101
89879101
89879101
89879101
89819101
89879101
89879101
89819101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89a19101
89879101
89819101
89819101
89819101
89879101
89819101
89879101
89879101
89879101
89879101
89819101
o
7/8
FR.lEV TO.lEV
2
1
1
2
1
2
1
2
2
1
1
2
1
2
2
1
1
2
1
1
2
1
2
1
2
2
1
1
2
1
2
2
2
1
1
2
2
1
1
2
2
1
2
1
1
2
2
1
1
2
1
2
1
1
2
2
2
1
2
1
1
2
1
2
2
1
2
1
1
2
1
2
2
1
2
1
2
2
1
1
1
1
2
2
1
2
1
2
1
2
2
1
2
1
1
1
2
2
1
2
1
1
9-131
18
P4Ge NO
FRON
34P1829
34P1830
34PIB30
34P1831
34P1831
34P2AOI
3ftP2401
3,.P2A02
34P2A02
34P2A04
34P2404
34P2A05
34P2A05
34P2A06
34P2A07
34P2407
34P2A20
3ftP2A20
34P2A21
34P2421
3ftP2A23
34P2A,23
34P2424
34P2A24
34P2A25
34P2A25
34P2426
34P2A26
34P2A27
~4P2A27
34P2A28
34PlA28
34P2429
34P2429
34P2A30
34P2A30
14P2801
34P2822
34P2822
34P2823
14P2823
34P2824
34P2824
34P2825
3ltP2B2S
34P2826
34P2826
34P2827
34P2821
34P2828
14P2828
9-132
W IRE
TO
35P1829
35PIB30
33P1830
33P1831
35P1831
33P2AOI
35P2AOI
35P2AO'
33P2A02
35P2 AOft
33P2A04
35P2AOt)
33P2 AOS
29P2807
35P2401
33P2401
33P2A20
35P2420
35P2A21
33P2421
33P2A23
35P2A2"4
33P2A2,.
35P2 A2ft
33P242')
35P2421)
35P2426
33P2A26
33P2421
35P2A27
33P2A29
35P2A2R
33P2429
35P2429
33P2 A30
35p2430
28P280&
35P282'
33P2822
33P2823
35P2823
3,3P2824
35P2824
35P2821)
33P282,)
33P282&
35P2826
33P2827
35P2827
33P282R
35P282R
lIS T
S IG.NAl-NA.-e
OOUT13
OCUT14
OOUTlIt
OOUT15
00UT15
00UT16
OooT16
00UT17
00UT17
0lN16
0lN16
OINll
OtN17
MOX5*
STROBE*
STROBE*
REF*
REF*
DISA8LE
DISABLE
' A(A7
4CA7
lK3*
1 K3.
ARAO
ARAO
ce*
CE.
AeA9
ACA9
ARA2
APA2
ARAI
4RAI
1 KO.
lKO*
OX5*
ACA8
ACA8
A(A6
ACA6
lK2·
1 K2.
ARA3
ARA3
ACA5
4CA5
R/W
R/W
ARAIt
ARAIt
A 8 1
W.l.
89879101
89879101
89879101
' 89879101
89879101
89819101
89879101
89879101
89879·101
89879101
89879101
89879101
89879101
89819100
89879101
89879101
,89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89819101
89819101
89819101
89879101
89879101
89819101
89819101
89879101
89879100
,89819101
89819101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
o
7/8
FR .lEV' TO.lEV
2
2
1
1
2
1
2
2
1
2
1
2
1
1
2
1
1
2
2
1
1
2
1
2
1
2
2
1
1
2
1
2
1
2
2
2
1
1
2
1
2
2
1
2
1
2
1
1
2
1
1
2
2
1
1
2
1
2
1
2
2
1
1
2
1
2
1
2
1
1
2
1
2
1
1
2
2
1
1
1
2
2
1
1
2
1
2
2
2
1
1
2
1
2
1
2
2
1
1
2
1
2
89633300 A
PAGE NO
79
FROM
WI R E
Tll
34P2829
~4PlB29
~4P2B30
14P 2830
35P1A02
35PIA02
35P1A03
35PlA03
35P1A04
35PlA04
35Pl A05
'35P lA05
35P1A06
35PIAOb
35PIA01
3SPl A07
~5P1A08
31)P1A08
35Pl A09
35PIA09
35P1A14
35P1A14
35P1A15
15P1A15
35PIA17
351> 1Al1
35P1A18
35PIA18
35P1A19
35PlA19
3,P1A20
35P1A20
15P1A20
35P 1A25
35Pl A27
35PIA27
35P1A28
15P1A28
35PIA30
35PIA)0
35Pl A31
35PIA31
35PIB03
35Pl803
35P1801
15P1801
3SP1816
351)1816
15P1819
35P1819
35P1820
33P2Bl9
35P2R29
33P2B30
35P2R30
34Pl AO?
~6P1AO?
.~6P1A03
34Pl AO~
36PIA04
34PIA04
36 Pl AOI)
. 34Pl AOI)
36PIA06
34P1 A06
16P1AQ7
34P1 A07
16P1AOR
34PIAOA
34Pl A09
36P1Aoq
34P1414
16P1Alft.
34P1A15
36P1A11)
36P1A17
34P1A17
36P1 ALB
34P1A1R
34PIA19
36Pl A19
34PIA20
36P1A20
34Pl All)
36P1A20
36P1A21
14Pl A27
36P1A2A
34P1 A2R
34P1A30
36P1A30
36Pl A3l
34PIA 31
36P1BOl
34P1801
36PIB01
34P1B07
34P1816
36PIB16
36P1819
34P1819
36P1820
89633300 A
l
r S T
$,IGNAl-NAME
11<1 *
lKl*
MPWR*
MPWR*
OOUTO
OOUTO
OINl
OIN1·
DOUT1
DOUTI
OlN2
DIN2
DOUT2
OOUT2
OlN4
DIN4
OOUT3
DOUT3
OOUT4
00UT4
OOUT5
DOUT5
OlN6
OIN6
00UT6
OOUT6
OlN7
OIN7
00UT7
DOUT1
00UT8
DOUT8
DOUT9
00U19
D INll
DIN11
DINI0
DINlO
DOUTll
OOUTll
OOUT12
OOUTl2
DINO
OINO
DIN3
DIN3
OlN5
OINS
DIN8
DIN8
DIN9
A B 1
~.L.
898791ul
89379101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89819101
89319101
89879101
89a79101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89879101
89819101
89879101
89819101
89879101
89819101
89819101
89819101
89879101
89879101
89919101
89819101
89819101
89879101
89879101
89819101
89879101
89879101
89819101
89879101
,89«179101
8987910l
89819101
89819111
89819101
89879101
89879101
89879101
o
7/8
fR.lEV TO.LEV
1
1
2
2
1
2
2
1
2
2
1
1
2
1
2
1
2
1
1
1
2
1
2
2
1
2
1
1
2
1
2
1
2
1
2
1
2
1
2
2
1
2
1
2
2
2
1 .
1
2
1
1
2
1
1
2
2
2
2
1
1
2
2
1
2
1
1
2
1
1
2
1
1
2
2
1
1
2
1
2
1
2
2
1
1
2
1
2
1
2
2
1
1
2
1
2
1
2
2
1
1
2
1
9-133
P4GE NO
80
FROM
35P1820
35P IB24
35P1824
35P 1825
3ljP 1825
35P1826
35P1826
35Pl821
35Pl827
35P,1828
3ljP1828
35P1829
35P1829
35P1830
35PIB30
35P1831
35Pl B31
35P2AOl
35P2AOI
3ljP2A02
15P2A02
3ljP2AOit
35P2AOit
35P2A05
3ljP2A05
35P2A06
35P2A07
35PlA07
35P2A20
3ljP2 A20
35P2A21
35P2A21
3ljP2A21
35P2A23
35P2A21t
31j P2 A24
35P2A25
35P2A25
35P2A26
35P2A26
35P2427
35P2A21
35P2A28
35P2A28
35P2A29
35P2A29
35P2A30
35P2A30
15P2801
35P2822
35P2B22
9-134
W IRE
TJ
34Pl B20
34PIB24
36P1824
36PIB25
34PIB21j
34Pl B26
36P1826
36PIB27
34PI B27
36P182A
34P1828
34P1829
36PIB29
36P1830
34P1830
34PIB31
36Pl B3l
36P2AOl
34P2AOl
3ltP2 AO,36P2AO?
34P2A04
36P2404
34P2AO'i
36P2 AOIj
28P2A07
36P2A01
34P2A01
34P?A20
36P2A20
36P2 A21
34P2A21
36P2A23
34P2A21
36P2A24
34P2A24
36P2A21j
34P2A21j
36P2A26
34 P 2A26
36P2A27
J4Pl A27
34P2A2A
36P2A2A
34P2 A29
36P2A29
36P2A30
34P2A30
28P2BOl)
34P2821
36P282l.
l
I
S T
SIGNAL-NAME
DINq
DOUTIO
DOUTI0
DINl2
DINll
DIN15
DINl5
DINl)
DINl3
OINllt
OlN14
OOUT13
DOUTl3
DOUTl4
OOUTl4
DOUT15
DOUTIS
DOL116
DOUT16
OCUT11
OOUll 7
DIN16
DIN16
DINI7
DINl1
MOX6*
STROBE*
STROBE.
REF.
RfF*
DISABLE
DISABLE
AeA1
ACA7
lK3*
11<3*
ARAO
ARAO
Cf*
CE*
ACA9
ACA9
ARA2
ARA2
ARAI
ARA 1
IKO.
lKO*
0)(6*
ACA8
ACA8
A 6 1
W.l.
8981910 1
89819101
89879101
89879101
89879101
8981910 1
89879101
89879101
89819101
89879101
89819101
89819101
89819101
89819101
89879101
89879101
-89819101
89879101
89879101
89879101
89879101
89819101
89819101
89879101
89879101
89879100
89879101
89879101
89819101
89819101
89879101
89879101
89879101
89819101
89879101
89879101
89879101
89819101
89879101
89879101
89879101
89819101
89819101
8~819101
89819101
89819101
89819101
89879101
89819100
89819101
89819101
o
7/8
FR.lEV TO.lEV
2
2
1
1
2
2
1
1
2
1
2
2
I
1
2
2
1
1
2
2
1
2
1
2
1
1
'I
2
2
1
1
2
1
2
1
2
1
2
1
2
_1
2
2
I
2
1
1
2
1
2
1
l
2
1
1
2
2
1
1
2
1
2
2
1
1
2
2
1
1
2
2
1
2
1
2
1
1
1
2
2
1
1
2
1
2
1
2
1
2
1
2
1
2
2
1
21
1
2
1
2
1
89633300 A
)AGf NO
B1
FROM
W I
T1
31)P2R23
35P2823
35P2824
35P2B24
35P2825
35P2825
35P2626
3SP2826
15Pl621
35P2821
35P2828
35P2828
35P2829
3S;»2829
lSP28}0
3SP2B30
3&P1A02
3&PIA03
36PIA04
36P1AOS
36P1A06
36P1A07
36PtA08
36P1A09
36P1A14
3!tP1A15
36PIAl1
36PIA18
36PIA19
36PtAlO
3&plA20
"36PIA27
'36PIA28
16Pt A30
36PlA31
36P1803
l6P1807
36P1816
36P18L9
3bP1820
36P1824
36P1825
36Pl~26
36P1821
36P1828
36P1829
36P1830
16Pt 831
36P2A01
36P2A02
36Pl A04
l
1ST
S IGNAl-NbME
36P2 B21
34P2B21
36P2B24
34P282434P2821)
36P2821)
36P2626
34P2826
36P2821
34P2821
36P282R
34P2828
36P282Q
34P2829
34P2B10
36P2830
35P1A02
35Pl AOl
lSPIA04
3SP1401)
3SPl A06
3SPIA01
35PIAOR
3') PI AOq
3SPIA 14
35PIAll)
35P1A11
35PLAIA
3SPI Al Q
3SPIA20
35PIA25
35Pl A21
3Sp1A28
35PIA30
35PIA31
35P1801
35P1807
35P1816
35P1819
15P1820
35P1824
35P1821)
35Pl B26
35P1821
35P182R
35Pl"829
35P1830
35PIB31
35P2AOI
35P2 AOl
·35P2 AOft
89633300
RE
A
AeA6
AeA6
1K2*
lK2*
bRA3
ARA3
bCA5
AeA5
R IW
R/W
ARA4
ARA4
lK1*
11<1*
MPWR*
MPWR*
00010
OINl
Doun
o IN2
00UT2
DIN't
DOUT3
DOUT4
-oOU1S
0lN6
00U16
0lN1
00UT1
00UT8
00UT9
OINll
OlNI0
OOUTII
OOUT12
OINO
DIN3
DIN5
0lN8
DIN9
DCUTlO
OlN12
DIN15
DINl3
DIN14
DOUT13
OOUT14
DOUT1S
00OTl6
DOUT11
DIN16
A 8 1
W.l.
89879101
89819101
89879101
89879101
89819101
89B 19101
89819101
89819101
89819101
89819101
89819101
89819101
89819101
89879101
89879101
89819101
89879101
89819101
89819101
89819101
89819101
89819101
89819101
89819101
89879101
89a 19101
89879101
89819101
89819101
89879101
89879101
89819101
89819101
89879101
89819101
89879101
89819101
89879101
89819101
89819101
89819101
89879101
89819101
89879101
89879101
89819101
89879101
89879101
89819101
89819101
89819101
o
118
FR.lEV TO.lEV
1
2
1
2
2
1
1
2
1
2
1
2
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
2
2
1
1
2
1
2
1
2
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
9-135
PAGE NO
82
FROM
36P2A05
36P2AOb
36P2AOl
3(1)2A20
36P2A21
36P24l3
36P24l4
36Pl A2'i
36P2A26
36P2A21
36P2A28
36P2A29
36P2A10
36P2BOl
36P2822
36P2823
36P2824
36P2B25
36P2826
36P2B21
36P2828
36P2829
16P2830
14 r R E
TO
35P2A 01)
l8PlA08
35Pl A01
35P2AlO
35Pl A21
35P2All
3SP2A24
3 5P2 A21)
35Pl426
3SP2 Al7
35P2A2A
35P2AlQ
35P2A30
l8P2AOl)
35PlRl2
35P28l1
ViP2-82ft
35P2825
35P2826
35Pl827
35P2828
35P28l9
3SP2830
l
1ST
SrGNAL-NA~E
OlNl1
MOX1*
ST~06E*
REF*
DISABLE
ACAl
11<3*
ARAO
CE*
ACA9
ARAl
ARAI
11<0*
OX1*
ACA8
ACA6
11<2*
ARA3
ACAS
R IW
ARA4
l1C1*
MPWR*
A a
14 .l.
89819101
89819100
89819101
89819101
89819101
89819101
89819101
89819101
89819101
89819101
89819101
89879101
89819101
89379100
89879101
89819101
89819101
89879101
89819101
89819101
89819101
89819101
89819101
I
o
118
FR.lEV TO.l EV
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
:;
9-136
89633300 A
TABLE 9-5
89633300
A
WIRE LIST BT148 EXPANSION ENCLOSURE BACKPLANE
(signal name order)
9-137/9-138
OlPIA21.06PIA21
06PIA21.14PIA21
14PIA21.22PIA21
14P181A.22P1818
02P18lA.06P1818
06P181A.14PlAlB
12PIB01.13PIA01
IlPIB07.12PlA01
03PIB01.0~PlB01
32KW
32KW
32KW
AUTOL06C
AUTOLOAC
AUTOLOac
CHI*
CHI*
CHI*
CHI*
CHI*
CHI*
CHI*
CHI*
CHI*
WIRE LIST BT148
OSPIB01.1lPlB01
04PIR07.0SPIA01
01P1801.03P1801
19PIB07.20PIA01
13PIB01.19P1801
20PIB01.2lPlA07
13PIB23.19P1823 ~C*
19PIB23.20PIR23 MC*
20PIB23.21PIR23 MC*
14PIA09.22PIA09 ~C*
06PlA09.l4PlAO~ MC*
IlP1823.12PIB23 MC*
04P1823.0SPIR23 MC*
03P1823.04PlR23 ~C*
OlP1823.03PIA23 ~C*
02PIA09.06PlA09 ~C*
lZPlBZ3.13PlR2J ~C*
OSP1823.l1P1823 ~C*
OlPIA03.0~PlA03 OAO*
05PIAO).11PIA03 CAO*
IlPlA03.12PlAOJ CAO*
lZPlA03.13FIA03 CAO*
03PIA03.04PlA03 CAO*
04PIA03.05PIA03 CAO*
l3PlA03.l9PlA03 OAO*
19PIA03.20PIA03 CAO*
20PIA03.21PIA03 OAO*
20PlBOI.2IPIROl OAl*
19PIAOl.20PIBOl OA1*
03PIBOI.04PIROI CAl*
04P1801.05PIBOl OAI*
IlPlB01.12PlBOl OAl*
13F1801.19PlROl OAl*
OSPIAOl.llPlBOl OAl*
OlP180l.03P180l OAl*
l2PlBOl.13PlBOl CAl*
l2PlB02.13PlA02 CA2*
IlP1802.12PIB02 OA2*
05P1802.11PIB02 OA2*
04PIB02.05FIA02 OA2*
13P1802.19PIR02 OA2*
03PIB02.04FIB02 OA2*
OlP1802.03PIR02 OA2*
20P1802.21P1802 OA2*
19P1B02.20PlR02 OA2*
19P1A06.20PlA06 OA3*
20PIA06.21PIA06 CA3*
IlPIA06.12PlA06 OA3*
12PIA06.l3PlA06 OA3*
05PIA06.11PIA06 OA3*
8963331)0
A
9-139
04P1A06.0SP1A06
OlP1A06.03P1A06
03P1A06.04P1A06
13PIA06.19P1A06
lJPlA07.19PlA07
03PIA07.04P1A07
12PIA07.1JPIA07
OlPIA07.0~PIA07
OSPIA07.11PIA07
lIP1A07.12PlA07
04P1A07.0SP1A07
20F1A07.21P1A07
19PIA07.2~P1A07
20P1AOl.21P1AOl
19PIA01.20P1AOl
12PIAOl.lJPIAOl
04P1AOl.OSP1AOl
IIPIAOl.12P1AOl
03PIA01.04PIAOl
OSPIAOl.liplAOl
IJPIAOl.19P1AOl
OlPIAOl.OJPlAOl
OlPIA02.0JPIA02
IJPIA02.19P1A02
OSPIAO?.1IP1A02
03P1A02.04P1A02
IlP1A02.12P1A02
04P1A02.0SPIA02
12PIA02.IJPIA02
20PIA02.2ipIA02
19F1A02.20PIA02
19P180J.20P1803
20PIBOJ.~iplBOJ
13PIBOJ.19P1BOJ
llP1BOJ.12PlB03
03PIB03.04PIBOJ
OSP1803.11P1803
01P1803.03P1903
04PIB03.0SPIB03
12P1B03.1JP1B03
12PIB04.1JP1B04
04P1B04.0SP1804
OlP1B04.03P1804
llP1B04.1~P1B04
OSPIB04.11PIB04
13P1B04.19P1804
OJPIB04.04P1804
19PIB04.2~PIB04
20PIB04.21P1904
20PIBOS.21PIBOS
19P180S.20P190S
04P1BOS.OSPIBOS
13PIBOS.19P190S
OSP1BOS'liP1ROS
llP1BOS.12P1BOS
01P180S.03P190S
03P1BOS.04PIBOS
12PIB05.1~P190S
OSP1B06.11PIB06
12PIB06.1JPIB06
9-140
OA3OA3OA3OA3OA4OA4OA4OA4OA4OA4OA4OA4OA4OASOASOASOASOAS*
OAS*
OAS*
OASOASOA6OA6OA6OA6OA6OA6OA6OA6OA6OA7OA7OA7OA7OA7OA7OA7OA7OA7OA8OA8OA8OA8OA8OA8OA8OA8OA8OA9OA9OA9OA9OA9*
OA9*
OA9OA9OA9OAI00.10-
WIRE LIST 8T148
89633300 A
04PlB06.0SPlR06 OAlO*
01PlB06.03P1B06 OA10*
IlP1B06.l2PlBO~ OA10*
03PIB06.04PIBO~ OAI0*
13PIB06.19PIBO~ OAlO*
19P1B06.2~PlB06 OA10*
20PIB06.2lPlB06 OAI0*
20PIAOS.21PIA05 OAll*
01PlA05.03PlA05 OAll*
llPlAOS.12PlA05 OAll*
12PIA05.l3PlAOS OAll*
03PlAOS.04PlAOS OAl1*
19PIA05.2qPIA05 OA1l*
05PIAOS.llPlA05 OAll*
04PlA05.0SPlA05 OAl1*
13PIA05.19PIA05 OAll*
OlPlA04.03PlA04 OA12*
IlPIA04.12PlA04 OA12*
04PlA04.0SPlA04 OA12*
03PlA04.04PlA04 OA12*
19P1A04.20PIA04 OA12*
12PIA04.l3PIA04 OA12*
OSPlA04.liP1A04 OAI2*
l3PlA04.19P1A04 OA12*
20PIA04.2lP1A04 OAI2*
20PlB09.2iplB09 OA13*
19P1B09.20PlB09 OA13*
l1PlB09.12PlB09 OA13*
03PlB09.04PlB09 OA13.
05P1B09.1iP1B09 OA13*
01P1B09.03PIB09 OA13*
13PIB09.19P1B09 OA13*
04PIB09.0SPlB09 OA13.
12P1B09.13P1B09 OA13*
l2PlB10.l3PlBlO OA14*
l3PlBlO.19P1A10 OA14*
OSPlBlO.llPlRlO OAI4*
03PIB10.04PIBIO OA14*
OlPIBIO.~3PIBIO OA14*
IlPlBlO.12PlBlO OA14*
19P1810.20PIBlO OA14*
04PIBIO.OSPlRI0 OAI4*
20PlBlO.21P1BlO OA14*
OSPIAll.llPlAll OAlS*
04P1All.OSPlAll OAlS*
11P1All.12PlAll OAlS*
l2PlAll.13PlAl1 OAlS*
13PIA11.19PIAll OAlS.
20PIA11.21PIAll OAlS*
19P1All.20P1All OA15*
03PlAll.04PlAll OAI5*
OlPIAll.03PlAI1 OAlS*
02PlA17.06PlA17 PEL·
06PlA17.14PlA17 PEL*
14PIA17.22PIA11 PEL03PIA23.04PIA23 PRl~*
OSPIA23.11P1A23 PRlM*
11PIA23.12PIA23 PRlM.
19PIA23.20PIA23 PRlM*
OlPlA23.03PlA23 PRlM*
89633300 A
WIRE LIST BT148
9-141
20PIA23.2ipIA23
IJPIA2J.19PIA23
12PIA23.13PIA2J
04PIA23.0SP1A23
OSP1A12.11 P IAI2
12PIA12.13P1A12
03P1A12.04PIA12
11PIA12.12P1A12
04PIA12.0SP1A12
01F1A12.03PIA12
13PIA12.19PIA12
20P1A12.21PlA12
19P1A12.20PIA12
OSP1812.11PIB12
13PIB12.19P1B12
04PIB12.0SP1812
20P1812.21P1B12
01F1812.03P1812
03P1812.04P1812
12P1812.13P1812
19F1B12.20P1912
11P1812.12PlB12
04PIA13.0SPlA13
OlPIA13.03PlA13
11PlA13.l2PIAIJ
12PIA13.l3PIAi3
20PIA13.21PlA1J
13P1A13.19P1A13
OSP1A13.11PlA13
03PIA1J.04P1AIJ
19PIA1J.20PlAiJ
IJP1813.19PIB13
04PIB1J.OSPl913
19PIB13.20P1813
20P1813.21P1BlJ
OlPl813.~3Pl~13
12P1813.1JP1813
OSP181J.liPl813
OJPIB13.04PIB13
11PIB13.i2P1813
12PIA14.13PIA14
11PIA14.12PIA14
04PIA14.0SPIA14
13PIA14.19PlA14
20PIA14.21PIA14
OlPIA14.03PIA14
OSPIA14.11PIA14
03PIA14.04PIA14
19PIA14.20PIA14
19P1814.20P1814
04PIB14.05P1814
20PIB14.21P1814
03PIB14.04P1814
OSP1814.11PIB14
13P1814.19Pl814
01PIB14.03P1814
12PIB14.13PIB14
IlP1814.12PIR14
12PIAlS'13PIA15
04PIAIS.OSPIAIS
9-142
PRlM.
PRlM.
PRTM.
PRlMCO
00
00
CO
00
00
CO
CO
00
01
01
Cl
01
Cl
01
Cl
01
Cl
C2
C2
C2
C2
02
C2
C2
02
C2
OJ
C3
C3
03
C3
03
03
03
OJ
04
a4
04
a4
a4
C4
a4
a4
a4
as
os
as
as
as
as
as
as
CS
06
a6
WIRE LIST 8T148
89633300
A
llP1A15.12PlA15
19P1A15.20PlA15
IJPIA15.19PJAlS
20PlA15.21PlA1S
01PIA15.0JPIA15
OSPIA15.11Pl~15
OJPlA15.04P1A15
20P1B15.21PIB15
04PIB1S.0SP1B1S
03P1815.04PIB15
19P1BlS.20P181S
OSPlBlS.llPi815
12P1815.13P18l5
l3P18l5.19PlBlS
01PIRlS.03 PlB15
IlP1815.l2PlB15
OSPIA16.11PlA16
IlP1A16.l2PlA16
12PIA16.i3PIA16
IJPIA16.i9PIA16
19P1A16.20PlA16
01P1A16.0JPlA16
20PIA16.2lPlA16
04PlA16.0SPlA16
OJPIA16.04PIA16
01PIB16.03PIB16
03PIBlf.04PlR16
20PlB16.2lPlB16
19P1B16.20PlA16
OSP1B16.l1PlB16
IJP1B16.19PIB16
12PIB16.13PIB16
04PIB16.0SPIA16
IlPIB16.lZPlB16
03PIA11.04PlA11
OSP1A11.1lPlA17
12PlA11.13PlA11
OlP1A11.03P1A17
IIPlA11.12PlA11
19PIA17.?OPlA11
lJPlA17.l9PlA17
20PlA17.21PIA11
04PlA17.0SPlA11
19P1B17.20PIB17
ZOP1811.21P18l7
03PIB11.04PIB11
OIPlB11.03PlB17
l3PlB17.l9PIB17
l2PlR17.13P18l7
OSPIB11.1lP1817
04P1B11.0SP1811
IlP1811.12P1817
19P1A18.20PlA18
OSPIA18.11PlA18
03P1A18.04PlA18
llP1A18.l2PlA18
l2PlA18.13PlA18
20PIA18.21PlA18
OlPlA18.03PlA18
04PlA18.0SPlA18
89633300 A
06
06
06
06
06
06
06
01
01
01
01
01
01
01
01
Q1
08
08
08
08
WIRE LIST BT148
as
08
08
08
08
09
09
09
09
09
Q9
09
Q9
09
010
010
010
010
010
010
010
010
010
Oil
011
Oil
011
011
Gil
Oil
011
Oil
012
Q12
012
012
012
012
012
012
9-143
IJPIAI8.19P1AI8
05P1818.11P1818
20PI818.21PIBl@
0IPI818.03P181@
13P1818.19P1818
12P1818.i3P1818
19P1818.20P1818
I1P1818.12P1818
04P1818.05P1818
03P1818.04P1818
04PIAI9.0SPIAI9
05PIA19.11PIA19
IIPIAI9.12PIAI9
12P1A19.13P1A19
01PIA19.03PIA19
20PIA19.21PiA19
13PIA19.19PIA19
19PIA19.20PIA19
03Pl&19.04PIAI9
05P1819.11P1819
13P1819.19P1819
12P1819.13P1819
20P1819.21P1819
19P1819.20P1819
11P1819.12P1819
04P1819.05P1819
01P1819.03P1819
OJP1819.04P1819
04PIA21.05Pl&21
OSPIA21.11PIA21
12PIA21.13PIA21
I1PIA21.12PIA21
01PIA21.03PIA21
IJPIA21.19PIA21
03PIA21.04PIA21
19P1&21.20PIA21
20PIA21.2ipIA21
OSP1822.11P1822
01P1822.03P1822
19PI822.?OP1822
12P1822.13P1822
20P1822.21Pi822
OJP1822'04P1822
IJP1822.19P1822
04P1822.0SPIB22
I1P1822.12P1822
04PIA22.0SPIA22
12PIA22.13PIA22
IJPIA22.19PIA22
01PIA22.03PIA22
20PIA22.2iPIA22
03PIA22.04PIA22
11PIA22.12PIA22
OSPIA22.1iP1A22
19P1A22.20PIA22
06P1812.14P1812
02P1812.06PIB12
14P1812.22P1812
06P1823.14P1823
14P1823.22PIB23
9-144
012
01J
013
01J
0(3
013
013
013
013
013
Q14
Q14
014
014
014
Q14
014
014
Q14
Q15
Q15
Q15
QlS
Q15
QIS
Cl5
015
015
REAO*
REAO*
READ*
READ*
READ*
READ*
READ*
READ*
READ*
REJFCT*
REJECT*
REJECT*
REJECT*
REJF.CT*
REJECT*
REJECT*
REJECT*
REJECT*
REPLY*
REPLY*
REPLY*
REPLY*
REPLY*
REPLY*
REPLY*
REPLY*
REPlY*
Ss*
SS*
SS*
SAO
SAO
WIRE LIST BT148
89633300 A
02PIB23.06PIB23
06PIA03.14P1A03
14PIA03.22PIAOJ
02PIAOJ.06PIA03
06PIB24.14PIB24
14P1B24.22PIB24
02P1B24.06PIB24
14PIBOl.22PlBOl
02PIBOl.06PlBOl
06PIB01.14P1AOl
06P182S.14PIB2S
14PIB2S.22P182S
02P182S.06P182S
14P1802.22P1802
02P1802.06P1802
06P1802.14P1802
06P1826.14P1826
14PIB26.22P1826
02PIB26.06P1826
14PIA06.22PIA06
06PIA06.14PIA06
02PIA06.06PIA06
14P1821.22P1821
06P1821.14P1821
02P1821.06P1821
14PIA01.22PIA01
02PIA01.06PIA01
06PIA01.14PIA01
14P1828.22P182B
06PIB28.14P1B28
02P1B28.06PIB2e
06PIAOI.14P1AOl
06P1830.14P1830
14PIBlO.22P1830
02P1830.06P1830
14PIA02.~2PIA02
06PIA02.14PIA02
02PIA02.06PIA02
02P18l1.06P1831
14PIB31.22P1831
06P1831.14PIB31
06P1803.14P1803
14P180l.22PIB03
02PIB03.06P1B03
06PIA23.14PIA23
02PIA23.06PIA2l
14PIA23.22PIA23
14P1804.22PIB04
02PIB04.06P1804
06PIB04.14PIB04
06PIA24.14PIA24
14PIA24.22PIA24
02PIA24.06PIA24
02PIBOS.06P180S
14PIBOS.22PIBOS
06PIB05.14P180S
06PIB14.14PIB14
02P1814.06PIB14
14PIB14.22PIB14
06PIA15.14PIA15
89633300 A
SAO
500
500
500
SAl
SAl
SAl
501
501
501
SA2
SA2
SA2
502
502
502
SA3
SA3
SAl
SOl
503
503
SA4
SA4
SA4
504
S04
504
SAS
SAS
SAS
50S
SA6
5A6
5A6
506
506
506
SA1
SA1
SA1
507
507
507
SA8
SAA
SA8
508
508
508
SA9
SA9
SA9
509
509
509
SPI*
SPI*
SPt*
SRC*
WIRE LIST BT148
9-145
02PIAI5.06PIAIS
14PIA15.22P1AlS
06PIA25.14PIA25
14PIA25.22PIA2S
02PIA25.06PIA2S
14PIB06.22PIB06
02PIB06.06P1806
06P1806.14PIB06
14PIA26.22PIA26
06PIA26.14PIA26
02PIA26.06PIA26
06PIA05.14PIAOS
02PIA05.06PIA05
14PIA05.22PIA05
02PIA27.06PIA27
14PIA27.22P1A27
06PIA27.14P1A27
06P1A04.14P1A04
14PIA04.22PIA04
02PlA04.06PIA04
06PIA28.14PIA28
02PIA28.06PIA28
14P1A28.22P1A28
02P1809.06P1B09
06PIB09'14PIB09
14P1809.22PIR09
06PIA30.l4PIA30
02P1A30.06PIA30
14PIA30.22PIA30
02PIB10.06P1810
06PlB10.14PIBlO
14P1810.22P1810
02PlA31.06PlA31
06PIA31.14PIA31
14P1A31.22PIA31
02PIAll.06PlA11
14PIA11.22PIAll
06PIAl1.14PlAII
02PIA18.06PIA18
06PIA18.14PlA18
14PIA18.22PIA18
06PIA20.14PIA20
02PIA20.06PIA20
l4PlA20.22P1A20
06PIB21.14PlR21
14P1B21.22PlB21
02P1821.06P1821
14PIA13.22PIA13
02PIAIJ.06PIAI3
06PIAIJ.14PIA13
02P1817.06P1817
06PIB17.14PIB17
14PIB17.22PIB17
03PIA09.04PIA09
01PIA09.0JPIA09
13P1A09.19PlA09
19PIA09.20PIA09
IlPIA09.12PIA09
04P1A09.05PIA09
20PIA09.2ipIA09
9-146
SROSROSAI0
5AI0
5AI0
5010
5010
SOlO
SAIl
SAIl
SAil
5011
5011
5011
5A12
5A12
5A12
5012
5012
5012
5A13
5A13
5AI3
5013
5013
5013
5A14
5AI4
5AI4
5014
5014
5014
5AI5
5A15
5AI5
5015
SOlS
5015
5016
5016
5016
5017
5017
5017
SWRITf*
5WRITE*
5WRITE*
SR5MSRSMSA5MSVIO5VIO5VIOT.P.
T.P.
T.P.
T.P.
T.P.
T.P.
T.P.
WIRE LIST 8T148
89633300 A
WIRE LIST BT148
12P1A09,13P1A09
05P1A09,IIP1A09
05P1A20,11P1A20
04P1A20,05P1A20
l1P1A20,12P1A20
12P1A20,13P1A20
20P1A20,21P1A20
13P1A20,19P1A20
03P1A20,04P1A20
01P1A20,03P1A20
19P1A20,20P1A20
19P1B21,20P1B21
01P1B21,03P1B21
13P1B21,19P1B21
05P1B21,11P1B21
12P1B21,13P1B21
20P1B21,21P1B21
03P1B21,04P1B21
04P1B21,05P1B21
-11P1B21,12P1B21
T.P.
T.P.
WEZ*
WEZ*
WEZ*
WEZ*
WEZ*
WEZ*
WEZ*
WEZ*
WEZ*
WRITE*
WRITE*
WRITE*
WRITE*
WRITE*
WRITE*
WRITE*
WRITE*
WRITE*
TABLE 9-6. COT EXTERNAL CABLE ASSEMBLY WIRE LIST (P/N 89668300)
COT
WIRE
WIRE
CPU
CONNECTOR/PIN
GAUGE
COLOR
CONNECTOR/
SIGNAL NAME
PIN
AWG22
BLK
P14-51
CRT-TRANS
-3
RED
Pllt-57
CRT-REC
-7
GRN
P14-58
COMMON (GND)
WHT/BLU
Pl-5*
CLEAR TO SEND
jumpered to
REQ~EST TO SEND
f!-2
Pl-4
AWG22
* Pl-5 (CLEAR TO SEND) is jumpered to
assembly connector for COT.
89633300 C
pl~4
(REQUEST TO SEND) at
9-147/148
COMMENT SHEET
MANUALTITLE CONTROL OATA R CENTRAL PROCESSING UNIT
8A201-8, 8T148, 8U120, G0611
0 _ _ _ __
0_
PUBLICATION NO. _8-=9:.....6-=3;,.::;3..::;.3_
FROM:
ABl07, ABl08, BA20l-A
HARDWARE MAINTENANCE MANUAL
REVISION _ _ _~H_ __
NAME: ____________________________________
BUSINESS
ADDRESS: _____________________________________________________
COMMENTS:
This form is not intended to be used as an order blank. Your evaluation of this manual will be welcomed
by Control Data Corporation.
Any errors, suggested additions or deletions, or general comments may
be made below. Please include page number references and fill in publication revision level as shown by
the last entry on the Record of Revision page at the front of the manual.
Customer engineers are urged
to use the TAR.
NO POSTAGE STAMP NECESSARY IF MAILED IN U. S. A.
FOLD ON DOTTED LINES AND STAPLE
STAPLE
STAPLE
mw
mw
---------------------------------------------------------------------------------------------------------------~1I
111111
I
NO POSTAGE
NECESSARY
IF MAILED
IN THE
UNITED STATES
I
I
I
I
I
I
1
BUSINESS REPLY MAIL
FIRST CLASS
PERMIT NO. 8241
w
MINNEAPOLIS, MINN.
Z
:;:;
POST AGE WILL BE PAID BY
CONTROL DATA CORPORATION
PUBLICATIONS ANO GRAPHICS DIVISION
4455 EASTGATE MAll
LA JOllA, CALIFORNIA 92037
l-
I:::>
:u
I
I
I
I
I
I
I
I
I
I
I
I
I
1
1
1
1
1
I
1
I
---------------------------------------------------------------------------------------------------------------~
~w
mw
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.6 Linearized : No Create Date : 2016:06:17 10:45:10-08:00 Modify Date : 2016:06:17 11:32:22-07:00 XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19 Metadata Date : 2016:06:17 11:32:22-07:00 Producer : Adobe Acrobat 9.0 Paper Capture Plug-in Format : application/pdf Document ID : uuid:c34422a9-9f7f-684b-9623-5213d8d20273 Instance ID : uuid:5e280238-38ea-a64b-824c-fa1cc3a9c818 Page Layout : SinglePage Page Mode : UseNone Page Count : 748EXIF Metadata provided by EXIF.tools