901565A 1_Extended_Performance_RAD_Tech_Jun70 1 Extended Performance RAD Tech Jun70
901565A-1_Extended_Performance_RAD_Tech_Jun70 901565A-1_Extended_Performance_RAD_Tech_Jun70
User Manual: 901565A-1_Extended_Performance_RAD_Tech_Jun70
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XDS 901 565A-l
$11.75
TECHNiCAL MANUAL
EXTENDED- PERFORMANCE
RAPID ACCESS DATA FILE
MOD ELS 7231/7232
,I
I
October 1969
(Revised June 19!O)
Xerox Data Systems 701 South Aviation Blvd., EI Segundo, California 90245 (213) 772-4511, 579-4511
© 1969, Xerox Doto Systems, Inc.
-
XDS 901565
.ective Poges
LIST OF EFFECTIVE PAGES
Total number of pages is 356, as follows:
Page No.
Title •••••.••••• 0•• 0••••• 0••••••••
A •••
Foreword •••••••••••••••••••••••••
i thru x •••••••••••••••••••••.••••
1-1 thru 1-6.".0 ••••••••.••••••••••
2-1 thru 2-4 •••••••••••.••••••••••
3-1 thru 3-14 ••• ~ .•.•••.••••••••••
4-1 thru 4-152 •••.••••••.••.•••••••
5-1 thru 5-24 ••••••••••.•••.•.••••
6-1 thru 6-30 •••••••••.•••••••••••
7-1 thru 7-14~ ••••••••••••••••••••
8-1 thru 8-26 •••••••.•..••••••••••
8-27 thru 8-28 ••••••••••••••••••••
8-29 thru 8-32 •••••••••• '" •••••••
9-1 thru 9-66 •••••••••••••••••••••
0
A
•••••••••••••••••••••••••••
Issue
Original
Original I
Original I
Orrginal
Original
Original .
Original Original
Original
Original
Original
Original
Revised June 1970
Original
Original
Pcge No~
Issue
XDS 901565
FOREWORD
This publication supersedes XDS publication Nc,. 901565A and
incorporates the information previously supplied by PDQ No. 70-018.
Contents
Xb5901565
TABLE OF CONTENTS
Section
Title
Page
INTRO'DUCTION .......•.•..••.•..••••••••.•••••.•••.••.•.•.•••••••••••.•••••••••••
!~
Desc~itt~~; Fi l·e· : : : :.: : : : : :.: : : : : : : : ::': : : : : : : : ': :': : : : : : : : : : : : : : : ~. : :. : ; : : :.,: : : : !:-: : : : : :< ~:: :
1-5
1-6
1-7
1-8
1-9
1-10
II. .
•••.•••••
Scope ofWlanuo! .•......•••.•.•.•..•....•••••••••.••. ~ •••• ~ ••
'Organiz'otion 'of Manua! .•.......••..•.•.•.••••••••••.•• ~ ......
0 .•••••••
0• • • • • • • •
'~
~~
0
1-1
1-2
:
••••••••.••••
••••••••••••
:
~
••••
EP RA D Contro'! ler ............................................'~': •• '..•.•• '...•••••••••••
RAD Selection Unit· ...•. :-••...••..••..••••.•..• '.......... :~ ..................... .
Di~c File ................": ••••.. : •....•.•...••.. ~ •••••••.• ~ •• '••...••.•.•••••..••.•
't\Aot~r Control Assernbl y •••••••••••
~
~
P~w~.r [)istributi~n P0i1~1 ••.••••••• : .........
~
Power Supp I y fy'\odel PT20.· •.•••• :' .............. ,; .•...•• ' .•• ~ ••.•••••.••.•...••.•••••..••
[P-
0
••••••••••••••
• • • • • • • • • • '.
< •••••••••••••.••
:
•••••••••••••••
.' • • • •
• • • .- • • • • • • • • • • • • • • • • • • • • •
OPERATION AND PROGRAMMING.: ....•.-•..•.•.•.. ~ •••.• ~.: •...•.•.• ~.: ••••..••.••••••••••••...•.
. 2-1
2-2
2-3
"2-4
2-5
2-6
4-:7 .
2-8
2--9
2-10
General ........................ .- ••.•.••.•••• ~
! • . • •~
Controls .....•...• , •....•.••.•.•.•.
~
! ••••••••••••••••••••••••••
EP PJ\D Controller Address Switches .........
EP RA.D Sto~age Unit A.ddress Swikhes .....•.• : •••..••••..••.•••••• ~: .•.••.•••..-:..•.•
. Onli ~z/Offijne Switch' ••.•.•.••••-.••..•••..•.••..•.••••.•••• : .•..•....•••.• : ..... 0.'
MF;.;~or}· Protecti~n Sv.'itches ...: ........•.••.•••.•....•...•.• ~'..•..•......•
Po·uer Distribution Ponel •....•.•.•.•. :' •••.•... '..•...•...•. :.- ....................... .
Motor Cont'fo! .h.:-sembl y .•••.. .- ••••' ••.••••••• ! •• '• • • • • • • .- •• -.- • • • • • • • • • • • • • • • • • • • ~ - ••
Povnr Supply Model PT20 •...•.•........•..• ~.~. :' .•.•. : •. ~: •••.•.•.••••.••...•..••
Opero~ing Procedure's ...••..•..•.•.•• ~ ...••• : ..•..•.••.•..•.• ~ •.•••••.•...•..•••.•••....•.
c ••.
0
. : '• • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •
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••••••••• ' •••••••••••••••••••••••••
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•••••••••
~= g -ProgrI~l::~~:~~~~: : : : : : : : : : : : : : :: : :: :.~: : : :: :: ::': : : :-: : :: : ~ : : : :-::.: : : : :: : : : : : : :: : :: : : :-: : : :
2-13
•......•.•.••.... '.' : .•...•.•• -........ '~ • : .• '•.' •..•.•.•.•..••..••.' ..•
. San.ple Progrcnl
.
.
.
.
.
.
- .
.
.' Iii
.'
;.
FUNCTIONAL OPERA nON .•....•.•. : .................................. -~ . ~ ...•..•••••.• : ..•.•.
Generci ...................• , ...•.•....•... ~ ................... ~ •...•.••....•........•
3-2
Data Org'Jniza.tion .........•.• : ~' .•.............•.. : ..... '. ~'.•.... : •. ~ .....•...•.•. ~ , •.•
3-3
. Mecha!1ic-al Functions .........• ~ .............•... : .•.....•••••. :.:. ~ .•••.••.•.•.. ~' •...•
3-4
Power r;;~tr:bution ..............•.•.•......... : ...•.•..••••••..•.......•..•.....••...
3-5
EP RAD Centrol !er •...••.•••.... ~ .•.•.....•• , ..•••..... '..' -~ . .- .•. ~ •.........••.•••.••...•
3-6
. IOF Interfo·ct. ... : ....•..•..•....•....••..••.......•...••. .- ••.•.•....•...•.••....
3-7
- Ala Command ....•.••..............•.••...•.•..•. ~.' ...
3-8
HIO Command ......•.•.••.• ~ .•• ~ •....•.•... ' ....•... ~ .. '.....•....•...• ',' ...• '.
3-9
TDV Con1mand' .........• ~ .......... - • , .....•..•....••.' , .•......•.•....... '.' ,.
3-10
. TIO Co~mand ....•.•..•.•........•.• - •....•.•. ' ............................. .
3-11
SiOCommand ............ : ...•.... - .. ~ ... ~ .•...•..... : .............••.. .- •...•
3-12
Inie,!'nal Operations .•.. : •.• : ............ ~ ...•........•.' ••.•.....•....•.••..•...•
3-:-13
..
Seek Order •......•......•.. : ~ . : ...... : •......•.••..•.•....•.•.•..•.•.•• : ..•
3-14
Sense Order .•......•..••...••••.• : ....••••..••. ~ .• ~ ........................... -. .•
3-15
vy'rite Order ......•.•.•..•.. .- ... ~'.' ••.•...• : ..•....••.•••........••••.•.•.•.•..
3-16
Read Order •...... : ..••...•...•.... : ••.....••.•..••• : ..•....•...•..•...•...•
3~ 17
Check\'vri t~ Order .•.•....•.•. ~ . '. ~ ...' • ~.•
3-·18
. . Selection Unit il1t~rface •.•. ~ •.•••. : .•.. ~'.'. ~ ~ '.' • :."'.•.••.•.•.......•• '....•.•....•••
3-19
EP ~AD Seiection Unit .....•.•.•••..•.•••.•.: ...••... ' . : .••.•••••..•..•.••.•••. : .•...•
/0
.....................
1-1
1-1
1-1
i -1
1-5
1-5
1-5
1-5
1-5
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-3
2-3
2-3
2-3
2-3
2-3
2-3
.:
3- i
0
1-1
1-1
"
••••••••••••••• :
••••
••••••••••••••••••••
3-1
3-1
3-1
3-1
3-4
3-4
3-4
3-4
3-4
3-4
3-6
3-6
3-6
3-6
3-7
3-7
3-11
3-13
3-13
3-13
Contents
XDS 901565
TABLE OF CONTENTS (Cont.)
Section
IV
TitlePage
PRINCIPLES OF OPERATION ..••••••.••••••••.•.••••••.•.••
o ••
Scope and. Organization of Section •..••• ."••••.•.
~
Electromecha,'lical Operation .•••••.••••••
Pneurr.atic System .•• • • • • . • • • • • • • • • • • • • • • • • • • • • . • • • • • • • • • • • • • • • • • • • . • • • •• • • • • • • • •
.MotOI Control Assembl y •••.••••••.• ~ ••••.•••.•••••••
Power Oi stri b·... ti on •............•.•••••.••••••.•.••••••••••.•.••••••••••••••.••••••••
Power Di strihuti on Pane I ...................•.....•......•..• ~ • . . . . • . . . • . . . . . . . . . .
Power Fail-Sofe Circuits ••••• o .
4-8.
EP RAD Controller
Subcontroll er • . . . . . • . • • • • . • . • . • .• • •.•.••••.•••••••.••..•••.••••••••••
4-9
4-10
Fun::tion Strobe and Function Indicators ........................................ .
4-11
lOP Data Line Signals .•..•••••.••.••••.•..••••••••.....••.....••••.•.••••••••
4-12
Priority Signals ............................................................. .
4-13
Subcontroller Response ................................... '.' •••••.•••••.•••.•••
4-14
TDV Function Indicator .•••.••••••..•.•••.•.•••..•••.•.•..•••••••.••.•••.•
4-15
TIO Function In~icator •••.•.•.•.•..•.••••.•••••.•.•••••••••••••••.•••••••
4-16
HIO Function Indicator.•••.•...•••.•.• , ••.•••••••••••••••••••••••••••••.•
4-17
S10 Functj Oil Indi cator •....•••.••.••...•••.••.•.•••.•••••••••••••
4-18
AIO Function Indicator. o • • • • • • •
o •••••••••••••••
4-19
ASC Function Indicator
o ••••
4-20
Phase Control Circuits ••..••.•........•••.••••••.••••••••••••. e • • • • • • • • • • • • • • • • • •
4-21
Tel Delay line •••••..• e • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • o • • • • • • • • • • •
P;,use Flip-Flops •••..••••...•.•••••
4-22
Response to lOP Commands ...
4-23
Order Out' Sequence ...••...•.••..
o ••••••
4-24
Seek Order Sequence •. ~ ••... , •.•.•...•••..•••...••. o • • •
o ••••••••
4-25
Sense Order SeqlJence. ',' .....••.•.. _. , ..•..•••.. ~ ••.••.•.••.••.•.•..•.•.•
4-26
VIrile Order or Checkwrite 8rder SeqU€.lc~ ...••••.•.•..•
4-·27
Read Order Sec:~·~nce .....•...•••..••.. ~ ....
4-28
O{der In Sequence •.•..••••....••.•.•.•.•..•.•...•..•••.••.•
4-29
S.;.~vice Cycle Identification logic •..•••.•.••...•••.•.....••.•••.••••••••••••.•
4-30
Qider ~eg i ster ••..••.••.••••.•••••....•...•.•.••.•..•.•••.••••.
4-31
S~rvice Call Logic. ' •.
4-32
By ~: Counter ...................................... .; •..•••
4-33
Terminal Order Operations .•....•••••..•..•.••..••
4-34
End Data and End Service logic ••..•.•.••••.•.••
4-35
Input./0utput Data Buffer ..•...•...•....•••.•••.•••••••.•...••.
4-36
I -Regi ster •......•••.••••.•.•..••...•.•. , - •••••••••...••••..••.•.• '•••.•...••
4-37
O-Register .
4-38
J-Regi ster ............•...••••.•.•....•....•••••••.•.••••••••...••.
4-39
Fast Access Memory (FAM) Circuits ..•.....•.•...•...••••.••.•••..•.••••.•.••...•.•
4-40
I~L Delay Line.•.•.•••....•..••••.••..•.•...•.••••.•..•••...••..•••••.••••.•
4-41
t<.K-Counter .......•.•.........••••...•....•••••.•..•.•.••.•..•
4-42
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4-2
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Op~ration of FAM Circuits During the Write ~equence •..••••••.•...••.•.••••••••
O,le-Byte Interface .•.•••.•.••..... ', .•..' ..•.••••
Multiple-Byte Interface .•...•..•..•• , .•..•••.•....•.••.•.•.•.•. _..•••.•.•
Operation of FAM Circui ts During the Read Sequence •..
One-Byte Interface .....•..••..•..•.•••••.•••....•••...•...••••••••..•.•
/v\ultipic .. Byte Interface ............•...•....•••......•.•.•...•••..••.•.••
Operation of the TRl Delay Line for a Seek Order •••..••••.
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4-1
4-1
4-1
4-1
4-1
4-3
4-3
4-3
4-3
4-3
4-8
4-8
4-8
4-9
4-9
4-9
A-TO
4-10
4-11
4-11
4-12
4-13
4-'13
4-13
4-22
04-23
4-24
4-25
4-26
4-27
4":28
4-29
~,-30
~~-32
4-33
4~34
4-37
~-37
4-39
4-40
4-41
4-41
4-45
4--48
4-48
4-51
4-52
4-52
4-54
4-55
~-55
4-56
4-57
Contents
XDS 901565
TABLE OF CO NTENTS (Cont.)
Section
Page
.Title
4-53
4-54
4-55
4-56
4-57
4-58
4-59
4-60
4-61
4-62
4-63
4-64
4-65
4-66
4-67
4-68
4·-69 --
4-70
4-71
4-72
4-73
4-74
4-75
4-76
4-77
4-78
4-79
- 4-80
4-81
4-82
4-83
4-84
4-85
4-86
4-87
4-88
4-89
4-90
4-91
4-·92
·4-93
4-94
4-95
4-96
4-97
4-98
4-99
4-100
4-101
4-102
4-103
4-104
4-105
4--106
Selection Unit Interface Circuits ••••••.••••.
TDL Delay Line ..•.
~
-Interface Clocking .•.••
B-Counter ••.•.•..
o.
K-Register ......•.••••••.•.•••••
D-Register •..•...
Interface Contrcl Circuits •.....•••.•..••••.•.....••••••....•.•.
. Track Shift Sequence •••
·Wri te Order· Sequence
Read Order Sequence ...•.•.•.•....•
Checkwrite Order Sequence •..••...•.•.••...••
Sense Order Sequence
Addressi ng Circui ts .....•....•.•.••.••••••.••••••
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Byte Width Logi c .•......••....•...•.••....••.••
RAD Type Logic.
Of;line Operation .•.
Online/Offline Control ••.
Reset Control ........................ , ..................•.... ~ . ~ ......... ; .•
PET Operations ......................................... -..............•..•.....
lOP Simulat;on ...........................•.............•.••.. ~ ...•....
Si ngl e Phase Mode .................•..........•.•........•.•
Alternate Orders Mode ...........................•........•...•.•.........
Count Done Sim'Jlation .•...........•...•..••..•••.••.......••....•.......
Sin~:e Track Mode ...................................................... .
Error Stop Mode .•..........•.....•..•............•.............•.......•
Phllse S~quence Charts ...... - .....•...•............•....•..........•...•.........
lOP Cornmand Sequences • ~ .................
Order Out Sequence ...•..•..........•...•......••.•••••••.......•...........
Sense Order Seguence ................ - ...•....••....••.......................
Seek Order Sequence .....................•....•...••...........•............
Write Order Sequence .....•.•....•... . .•. , .•.•..•.•.....•....•......•.....•
Read Order Sequence ..................•..•....••..••..•.•......•...••...
Checkwri te Order Sequence •...........•..•........•••.•.•..•.•.••.....•.....
Order In Service Cycle .......•.....
Termina; Order Operations ................................................... .
EP RAD Selection Unit •.................••........•. o • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •
Address Circu! ts ...•.................•.......•.....•••••...•...•..••.....•.•..•.
Track Register .................................. ; .....•.•...................•....
Memory Protec t Circuits .•...
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iii
Contents
XDS 901565
TABLE OF CONTENTS (Cont.)
Section
4-107
4-1Da
4-109
4-110
4-111
4-112
v
Angle Regi ster ...•••••••••.•••••••••••••.•.•••••.••••.•.••••••••••••..•.•.•.•..•
Head Selection Matrix •••••.••.••.. "••••..•••••••••••••••••••••••••••.•.•••.••..•
Write Channel •. '.•..••.•..•.•••.•.••••.••••••.•••..•..•.• ~ •••••..•..•••••••.....•
Read Channel •.•.•••••••••••••••••••••.••..••••••.•••.••••.••••••.•••••.•••••..•
logic,,! Sparing Circuits ••••••••••.•.•••.•..••••.•.•••.••.•••••••..•.•••.•.•••.••
Typical Operation ••.••..••••..•.•.••. '.' ••••••••.• '••.•.•••••••••••••••••••.•••.••••.•
DRAWINGS ••....•.•...•.••••••.•.•..••••-•.•.•.••••.•••••.••.•••••••••.••••••....•.•.•.••.•
Scope of Sec tion ••......••••••••••••..•••.•....•.••••..
Location of Related Text .•••••••.••.••...•••..••.••.••..••..•
6-1
6-1
6-1
. SPECIFICA.TIONS AI'ID INSTALLATION DATA •..•••...•••.••.•..•••.•••.•.•
7-1
Specifications ••..•••.••.•.•.••.••.••
7-2
InstallatiCJo .•...•....•..••••..•.•.••..•.•••..•.•.••.•.••..•••...•..•........•......•
7-3
Instaliation Requirements ••.••••.....•......•.•....••...••.••..••..•.•...••..•..•
7-4
Installation Procedure ••.•...•••••••••••.•.•••.••.•.••...•••..•..••.....•.•......•
7-1
7-1
7-1
7-1
/-1
MAINTENANCE •.........•...••••••...••••.•.•••••......•..•..•..••••.....•........•.•••..•
Scope of Sec tion •..•....••••..••••.••••...... : ...................................... .
General \I\ai ntenance ......•..••••.•..•.•..... , •.•..••.••.•••••••....•......•.. , ...•
Diagnosti r.. ; .:st Programs •...••.•....•..••..••••.•••.•..••..•
Basic Checv.s and Adjustments •..•••••••.••••..••.••...•..•...•..••.•....•••.•.•.
Prel:~ilinary Operations •.••••••...•...••.•..
Powel" "fest .......•...••.•...•......•.•.••..••.••..•....••.....•.....••...•.•.••
Adjusfnle;Jt of Timing Signals .••..•..•...••.•••.••••.•••..•.............•..•..•••. ~
Powe. :ail-Safe Test ..• " ••.•.••.••...•......••••.•..••. ·.•
Adjdimen;- of AT41 Write Clock Driver ••.•..•.••.••...••..••.•....•••.••.•••.•.•..
Data P'Jth Timing Adjustment ••••.•.•....•...••••...••....•..•.•.•.......•.•...•.
.Offli ne T-::sts •..•....•...•.••.•.•........•...........••••..••..•
Prelim;.,ar)' Operations.
Si ngle :--!'Iase Sequences ••.••...•...•..•.•......•....•...•••......••••••......•.•.
I1legai Order Sequence •...•.••.••.......•.•.••.•.••••.•.••.•..........•.•.......
Singie Phase Seek Order •..•.•...•.•.••....•.•••.•.•••.•••.••....
Singie Phase Sense Order •...•....•.....••••••.•.•..••..••••.•...••.•.•...•......•
Repeat Mode Seek Order •..•.••.•...••••...••.•.•••.•...•..•••.••.•.•..•.....•.••
Single Phase Write Order •..•••.....•••••.•.•.•..••..•.....•....••.....•. , •.•.•..•
Sector Counter Test ..••.•....•.•...•.•.••...•...••.••••..•••.•...•.......••...•••
Extended Interface Test (Two-Byte Option) •..•.•.•••...••..•..•...•.•.• ~ •.•.••.•.•.•
Extended Interface Test (Four-Byte Option) •...•........•...•.••.•.....•..•...••••..•
Repeat Mode V/rite Order •..•........•.•.•...•..•.•••
y-Se.;~':tTest ...•.•.••.•....••..•.••..•..•..•...•.•••. : •...•....•......•..•..•..•
Tel Delay Line Test •..••••.•.••......••..•...•.•....•.••.•.•...•..•......••..•.•.
TRL Delay Line Test ..•..•............•.....••.•.•...••..•••.•.•...•......•...•..•
Writ-e Amplifier Test •.•••......•...• : •..••..• " .•••.•••..••..••. '" ..•....•.......
Checkwrite Test .....•••••.•.•.•........•..•... ~ .•..•...•' ......•.•.•••......•....
Alternde Orders Mode, Repea ted Operati on .....•...•••..••.......•.•••..•.•......•
Alter:1ute Orders Mode, Si ngle Track Operati on ••••••••••••••••••••••••••••••..•••••
CPU Mode Tests ••.......••••......................•...••..•.••.•..•........••..•...•
Si gma 5 or S; gma 7 Mac hi ne Language TE:!> t Program ..............•...........
Sigma 2 Machine Language Test Program •••.•.••.•.•...••.•.••......• · •.. · ..•..•.•••
8-1
8-1
8-1
8-1
8-1
8-1
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8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
8-11
8-12
8-13
8-14
8-15
8-16
8-17
8-18
8-19
8-20
8-21
8-22
8-23
8-24
8-25
8-26
8-27
8-28
8-29
8-30
8-31
8-32
iv
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VIII
~·-138
4-141
4-141
5-1
5-1
5-1
0
6-1
6-2
VII
4-i34
4-i36
4-138
LOGIC EQUATIONS AND GLOSSARIES ••.••••.••.•••.....•.•.•.•••••••••••••.•.•..•..•••••..•
Glossaries
logic Equ'ltions ••.•...•.••••.••••.•..••••••••••.••••..•.•.
5-1
5-2
VI
Page
Title
.................
.
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•••••••••••••••••••
8-7
•••••••••••••••••••••••••••••••••••••••••••••••••••••••••
3-7
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8·-2
8-2
8-2
3--4
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8-9
8-10
~-10
8-11
8-12
R-12
8-13
8-13
8-15
8-15
8-15
8-16
8-17
8-17
8-20
8-21
8-22
8-22
8-22
8-22
XDS 901565
Contents-Illustrations
TABLE OF CONTENTS (Cont.)
Section
8-33
8-34
8-35
8-36
8-37
8-38
8-39
8-40
8-41
IX
Page
Title
Repairs, Replacements, and Adjustments •••.•.•..•.•••.•••.••.•••.....•••.••••...•••...•
Replacement of the Drive Motor Stator ••..•.•.••.•.•.•.•••....•...••.••..••••...•.•
Adjustment of the Disc File Brake ..•••••.....•..•.•..••..•.•.•...••••....••......•
Replacement of the Disc File Brake Linings •.•.•••.••.•.•.•.••.....•••...•.•.•••••••
RAD Filter Replacement .••..••••......•..•...•.•.•....•..•.....•.••.•.•.•..••..••
RAD Interface Connector Cleaning Procedure .••.•.•.•..••.•••.•.•.•.•.•..••.•.•.•.••
Selection of a Spare Write Clock ••....•......•..•.•••.•.••••.••.•.•..•••.••....•.•
Logical Sparing of Read/Write Head •.......•....•....••....•.....•.••••.....••...•
Selection of Spare Read/Write Heads •..•...•........•.•.•.••.•...•..•.••..•....•.•
ILLUSTRATED PARTS BREAKDOWN ........................................................... .
9-1
Group Assembly Parts List •... ~ .••••.......•..• '" ••..•..••••••........•..•••.••....••
9-2
Numerical Index ••......••••••.•••..•••••...••••.•.••.••••.•••...•..••••••••.•.•..•
8-22
8-22
8-26
8-27
8-27
8-28
8-28
8-30
8-30
9-1
9-1
9-1
LIST OF ILLUSTRATiONS
Figure
1-1
1-2
1-3
2-1
2-2
3-~
3-2
3-3
3-4
3-5
3-6
3-7
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
~·-12
4-13
4-14
4-15
4-i6
4-17
Title
Page
EP RAD Storage Unit, Front Vie'wv •..••••••••••.•.•.••••.•..•.••....•.••••••....•.••••.•.•..••.•
EP RAD Storage; Urit, Rear View.. . .• ..• . •. .. •.. .•• •• • .. .•• •. ••. •. • •• ••. .• . . . •• . . ..• . . . • •••. ••
EP RA:> Storage Unit with EP RAD Controller, Frcnt View ••..•.•...••••••.••..••.••.•.••......... ,.
LT26 Switch Co~t>arator Module .....•••••••....••••............•.•••....••.......•••••••...••
LTL5 Special Pt..q:ose Logic fv~odule •.•••..••....•..•••........•.•......•.•.•...•••••••.•.•.....•
E? RAD Fi Ie, Bi.:;ck Diagram .........•••.••.•.•.•.••....•.•.•.•..•••.•••......•.•.••.••••.....
EP RAD Disc File i)ata Organization •..••••.••....•.•• , ...•••••.•..•.....•..•....•.••...•... '. •
Response to lOP Commands, Flow Diagram •.••.........•.•..•.. . .....•••.•.....•..•.••••••...••
Seek Order Dato Path, Block Diagram •••..••.•.••.. " , .... '•..•....•......•...••..••.•.••.•..
Sense Order [)coto Pcth, Block Diagram .•.........•.••... ' ....••.•.••••••........••...•......•.•
Wri te Order or Checkwri te Order Data Path, Block Diagrarrl ..•...•.....•••....... , •.•..•.•...... , •
Read Order Data P::lth, Block Diagram ..•....•••.•...•..•........ " .•••••......••.•••.•...•..
Pneumatic System, Simplified Block Diagram •....•...••.....•..••..•••..••.•....•.•..•......•..•
Motor Control Assembly Start Sequence, Flow Diagram •.•....••.••.•.•••••••... ,. ................ ' .•
Motor Control A!::;~mbl y Start Sequence, Timing Diagram ....•...•• : ...•••.•.. ~ ......•••...•••..
Motor Control Assembl y Stop Sequence, Flow Diagram ••.•....•.•.....•.••••..•.•.••..••.•.•..
WT29 Power Menifor Module, Typical Wavehrrn ...•.•....•.••.•...•.••.•.•....•.•.•....•. ~ ..•..•
Typical I/O Operations, Ti ming Diagram •.•.•....•••.......•••.....•.••.•.•.....•••••.•.•.....•.
TCl Dela)' Line, Timing and logic Diagram ••...•.•....•.•..•.•.•••.••..•.•..............•....•.
Simpli fied Phase Sequence, Flow Diagram ...•..........•.••.•.•..•.•••..••......•.••....•... ' .••
Serv:ce Call Fli!"-Flop SCN, logic Diagram ................................................. ..
End Data and End Servi ce logic, logic Diagram .•..•.••••.....••.••...•.......•.......•.•...•..•
FAM Circuits, Simplified logic Diagram .••.•...••.....•....•••.•.••• ••••·•·•···••••···•·••·•··•
FAM Module, Blork Diagram ..•.•..•..••......•••..•••...•....•....•.•.•......•.•.•••.......•.
TRl De lay Li ne, logic and Timi ng Diagram •.........•...•.•..•..•.....•......•.. ~ .....•....•..•
Sequence of FAM Write Cycles, Timing Diagram .....•.•....•..•........••••.....•.••.•.........•
Sequence of FAM Read Cycles, Timing Diagram ..•......•.•.•...•.•....•..•.......••.•....•.....•
TDL Delay Line, logic and Timing Diagram ..•.....•.••..•.....•.....•••.........•.••........••
Track Shift Sequence, Timing Diagrarn •.•.......•......•.•••....•••.•...•.•..•.••....•......•.••
Revised June 1970
c
.-2
1-3
~
-4-
2-2
2-2
3-2
3-3
3-5
3-7
3-8
3-9
3-12
4-2
4-4
> ••
4-5
•••
4-6
4-7
4-12
4-144-15
4-31
4--35
4-42
4-43
4-44
4-49
4-50
4-5~}
4-·66
v
I
XDS 901565
I1lustrotions
LIST OFILLUSTRA nONS (Cont.)
Figure
4-18
4-19
2
4-
°.
4-21
4-22
4-23
4-24
4-25
4-26
4-27
4-28
4-29
4-30
•
4-33
4-34
4-35
4---36
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
•
6-14
6-17
6-18
6-19
6-20
6-21
6-22
7-1
7-2
7-3
7-4
7-5
8-1
8-2
8-3
8-4
8:5
vi
Page
Title
Interface Control Circuits, Timi ng Diagram •••••••••••.•.•••••••••••••••••••••••••••
Address Incrementetion, Simplified Logic Diagram •••
Checksum Generation, Simplified Logic Diagram ••••• - •.••••••••••.•••••••••••••••••••••••••••.•
Byte Width Circuits, Logic Diagram ••••
Connect-Disconnect Timi ng Diagram.
. Reset Control, Simplified Logic Diagram
PET Interfa=e Circuits, Simplified Logic Diagram
Data Transfer During Sense Order, Timing Diagram ••.••••••••••••••••••••••••••••••.•••••••••••••
Data Transfer During See'< Order, Timing Diagram •••.••••••.•••.•••••.••••••••.••••••••••••••••••
Head Seledion Iv\atrix, Simplified Block Diagram •••.••••••.•
Write Channel, Schematic Diagram ••..•.• ',"
Part of Head Selection Matrix (Track 221), Schematic Diagram •••
Write Signals, Timing Diagram ••••
Read C ha nne I, Schema ti c Oi agram •.••..••••••••.•.••.••.•••••••• ~ ••.••.•••••••.••.••••••••••••
Read Signals, Timing Diagram ••••.
Logical Sparing Circuit,;, Block Diagram •••••.•••••••.
LTl05 Spares Selector /\t\odule, Simplified Logic Diagram
Logical Sporing Circuits for Track 221 (Octal 335), Simplified Logic Diagram ••..
EP RAD Controller, Det::Ji led Block Diagram ••
o.
o.
o.
Power Distribution Peilel, Schematic Diagram
EP RAD Selection Unit; Power Distribution, Chassis Wiring Diagram
EP RAD Sei~ction Unit, Power Fail-Safe Circuits, Logic Diagram •••
N\oi'or Control Assembl}' (146485), Schematic Diagram •••.
EP RAD Selection Uni I, Address Circuits, Logic Diagram •.
o. ~
EP RAD Selection Unit, Track Register (Without Logical Spaiing), Logic Diag'"am .••• , o.
EP RAD Selection Unit, Input/Output Circuits, Logic DiC"grarn •
EP RAD Selection Uni~, Memory PiOtect Circuits, Logic Diagram ••••••••••...•••
EP RAD Selection Unit. Angle Register, Logic Diagrom' ••••••.
Head Loecti on Chart •••.•••••••••••
Head Cenlertap Chart ••.••.••.•.••.
Y-Select Location Chart (Without Logical 5paring). ~ •••
Input/Output and Start/Finish Location Chart (Without Logical Spo .. ;ng) •
Motor Control Assembl> (152692), Schematic Diagram •..•.•..•••.•.
o.
EP RAD Selection Uni·,. Write Channei (Without Logical Sparing), S~hematic Diagram ••••.••
EP RAD Selection Unit, Read Channel, Schematic Diagram •••• o • • • • • o • • • • • •
o ••••••••
o.
EP RAD Selection Unit, Write Channel (With Logical Sparing), Scr."'i'latic Diagram •••••••••
EP RAD Selection Unit, hack Register (V'lith Logical Sparing), Sch::matic DioClram •••••••••••.
Input/Output and Start/Finish Location Chart (With Logicul Spari.i9,' • o • • • • • • • • " • •
o.
Y-Select Location Chart (With Logical Spa;-ing) ••
LTlOS Spares Selector fv\odule, Logic Diagram ••••••••••.
EP RAD Selection Unit, Spares Select Circuits, Logic Diagram •••.••..•••••••••••••.•••••
o.
EP RAD Storage Unit, Illstailafion Drawing
EP RAD file, Cabling Diagram ••••••••••••
EP RAD Controller, Cab,~ Connections ••.••••••..•••••••.••••
EP RAD Selection Uni t, Module Location Chart
EP RAD Controller, Modvle location Chart • ~ .•••••••••••.••••••••. , •••
Signal CLK3MH, Tim; ng l):agram
Signal SECT, Timing Diagram ••••.
o •••
Signals SP and IP, Timing Diagram •••••••
PET Pane! Overlay
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[)ata CJ,ock Signals, Timi ng Diagrarn •••••
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4-67
4-73
4-75
4-81
4-82
4-83
4-87
4-1 )0
4-114
4··137
4-139
4-140
4-141
t! -143
4-145
':;-148
4-149
4-i50
4-·151
6-2
6-3
6-5
6--6
6-7
6-';
6-10
6-! 1
6-13
(\- -:4
f,-17
6-18
6-19
6-n
6-22
6-23
0·24
l~,-?5
6-26
0··L7
6-28
v-2')
7-7
7-3
7-11
7- 12
7-13
8-3
8-3
8-+
8-5
8-6
XDS
901565
Illustrations-Tables
LIST OF ILLUSTRATIONS (Cont.)
Figure
8-6
8-7
8-8
8-9
8-10
8-11
8-12
8-13
8-14
8-15
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
Title
Page
Data Synchronizotion Signals, Timing Diagram •••
o ••••••
o.' • • • • • • • • • •
Sector Identification Signals, Timing Dicigram •••••••••••••••••••••••••••••••••••••••••••••••••••
TDL Delay Line Signals, Timing Diagram ••••
Head Select Signals, Timing Diagram ••••••••••••••••••.•••••••••
TCl Delay Line Signals, Timing Diagram
o.
TRl Delay Li ne Signals; Timing Diagram .................... o. • • . o. • • • • • • • • • • • • • • • • • • • • • •
Write Amplifier Output Signcls, Tiffling Diagram o • • • • • • • • • •
Data Path Timing Signals, Timing Diagram •••
Write Clock Trccks, Schematic Diagram •••••••••••
H~ad Wiring Connection Chart •••••••••••
e ••••••••••••••
Extended Performance RA D Storage Uni t and RAD Contro lIer
RAD Storage Un i t Cab i ne t Assembl y ••.••••.••
Select.ion Unit P\55emhly •••••••••
Module Location (Selection Unit Assembly) •••••••••••••• " ......." •••••• "." ." ••••••••
Spindle and Drive Assembly
~
w.
Motor Control lJr:it Assembly
o.
o ••••
Printed Wiring Boord (TB 1) •••
o ••
Power Distri buti on Panel Assembl y • o • • • • • • • • • • • • • • • • • • • • • • • • o • • • • • • • • • • • • • • • •
Extended Perforl"1c:1ce RAD Controller •••••••••
Iv\odule location (RAD Controller) ••••••
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8-7
8-13
8-14
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8-18
8-19
8-20
8-21
8-29
8-31
9-3
9-5
9-14
9-22
9-24
9-29
9-40
9-43
~-48
9-54
LIST OF TABLf5
Table
Title
Page
2-1
EP RAD Control lei Address Switcn Positions ~LocationC24) ••••
2-2
EP RAD Storage Unit Address Switch Posi tions (Location A7) ••••••••••••••
2-3
Portion of Machine Language Progr~m Controlling EP RAD F:le ••••••
Service Cycle Op~rations •. o • • • • • • • • • • • • • • • • • • • • • • • •
Information in Fup-:tion Respons~ Signals for TIO, HIO, or SIO Commands •••••
Order Si gnal s •••••••••.••••••••
o ••••••••.••••
o.
~
Operation of H"e i< K-Counter •••••.•.•
o ••••
o •••••••• v ••••
Relation Betwe~p State ana Output of the l-Register .•• • ••
Summllry of Error t=lip-Flops and Signals •••••••••••••
PET Inh:rface Contro! Signals
PET Interface Indication Signals ........
AIO Command, Phase Sequence Chart •••.•••
~HO Command, Phase Sequence Chart
SIO Command, Phas~ Sequence Chart
o •••••••
TDV Command, Phase Sequence Chart ••
TIO Command, Phase Sequence Chort •••••
o ••••••••••••••
o.
Order Out Service Cycle, Phase Sequence Chart ••••••••••••••••••••••
Sense Order, Phc5e Sequence Chart ••••••••••••.••••..•••••••••• o • • • • • • • • • • • • • • • • • • • • • •
Seek. Order, Phase Sequence Chart .••••••••••••••••••••.••
Write Order or Cl-teckwri te Order, Phase Sequence Chart •••
Read Order, Phase Sequence Chart ••••••.•
Ordei In Service Cycle, Phase Sequence Chart.
3-1
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
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0 • • • • • • • • • • • 0.00
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0
000
'0'
00
••
••••• 0.,
0
••••••••••••
•• 00'
••
00
0
•
0
•••••• 0
•••• 0
•••• 00.
••
•••••••••
0
0
•••
••••••••
0 ' • • • • • • • • • • • • • • .0
0
0
0.0 • • • • • • • • 0
0' •••••••••••• 0
0
•••••••
•• 0
•••••••••••
••••••••• 0
.0 •••• 0'
••••
0
00 • • • • • • • • • • 00
•••••••••••••••••
•••••••••••
••
0
• • • • • • • • • • • 0.0 • • • • • • • • • • • • • •
•••••••••••••• 0
•••••••••••••••••
••••••••••••• 0
••
•••••••••••••
•••••••••••
••••••••••••••••••••••• 0
2-1
2-4
••• 0
••.•••••••••
2-1
3-6
0
,.0
00
• • • 0 0 • • • • • • • • • • • • •· 0
••••.••••••••• 0
0.0.· ••••••••••••••••••••••••••••••••
0
0
0
0
•••••••••••••••
0.
•••••••••• 0
0'
0
0
o ••••••••••••••••••••
••••••••••
••••••• 0
0
•••••
•••••
•••••
00
••••••••••••••••••• 0
•••••••••••••
0
•• 0
0
•
0'
0
•
••
•••••
0
••••
••••••••••
4-10
4-23
4-46
4-51
4-76
4-84
4-86
4-91
4-93
4-95
4-98
4-100
4-102
4-106
4-111
4-115
4-122
4-129
vii
XDS 901565
Tables
LIST OF TABLES (Cont.)
..
,
Title
Table
4-19
4-20
4-21
4C22
5-1
5-2
5-3
6-1
7-1
7-2
7-3
8-1
8-2
t
I
8-6
8-7
8-?A
8-7B
8-8
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
viii
Page
Terminal Order Operations, Phase Sequence Chart ••••••••••
EP RAD Selection Unit Interface Signals •••••
Memory Protect Signa Is •••••••••••••• " ••••••••
Typical Operations,of th9 EP RAD File ••••••••••••••••••••••••••••••••••••••••••••••• -•••••••••••
Glossary of EP RAD File Terms ......................
Glossary of EP RA D Contro lIer Si gna Is ••••••••••
Glossary of EP RAD Se!ectron Unit Signals
List of Related Engineering Data •••••••••••••••••••••••••••••••••••••••••••••••
EP RAD Storage Unit Srecific~tions, •••••••••••••••••••••••••
eo • •
Connections Between EP ftA.D Controller and lOP
Installation Procedure Checkoff List • ••••••••••••••••••••••
0 •••••• o ••• 0'.
Functions of PET Panel Overloy Switch Designations ••••••••••••
Test Equi pment Requ i red for Offl i ne Test •
o.
Dato ,in Bytes of Seek Order •••••••••••••••••••••••••••••••••••••••' ......................,••• 0'.
Location~ of Y-Select VL'tput Signals ••••••••••••••••••••••• '•••
EP RAD File Program fer Continuous Test (Sigma 50r Sigma 7) •• < • • • • • • • • • ~ ~
Sigma 2 Machine Langl~~ge Test Program for EP RAD File •••••••••.••••
Ins.tructions Used in Sigma 2 Test Program ....................................
Replacemer,t Filter Pert Numbers for Motor Control Unit, Part Numheo" 146485 .................. ~ ••
Replacement Filter Part Numbers for Motor Control lh itT Part Number 152692 •••••
Summary of logical Sparing Si gnals •••••••••••••••••••
Ext'ended Performance RAD Storage Unit •••••.••••
RAD Storag0 Unit Cabine" Assembly ••
Se lection IJnit AssembJy ••••••••••
~
Module locations (Sel?(;tion Unit Assembly) ............................
Spindle and [)rive Asser.1bly ••.•••••••
Motor Control Unit Assarnbl:t •••••
Printed Wi,.ing ,Board T~l ••••••••••••••••••••••••••••
Pow'er Distribution Par:1"1 ,~.ssembly •• '••••••••••••
Extended Performance RAJ) Controller ••••••••••••••
o •••
o ••••
Module Locations (!
.9·23
•••
')·25
•••••••••••••••••••••••••••••
9-,0
• • • • • • • • • • • • • • • • • • • • • • ·' • • 0
. . . . . . . . . . . . . . . . . . . . . . '.0 • • • • • • • • • • • • • • • • 0
••••••••••••••••••••••• ' ••••••• ,
•••••••••••••••••••••
00 • • • • • • • • • • • • • • • • • • • 0
0
••••••• 0
4-133
4-135
_ 0
• • 00
0' ••••••
,
•
"
9-4
••
O-?9
• • • • • • • • • • • • • • • • • • 0.'.0 •••
••••••••••••••••••••••• 0
• • • • ,'
9,-4-1
•••••••
• • • • • • • • • • • ." • • • • •
7-:)5
'1··57
Revised June 1970
Related PuSlications
XDS 901565
LIST OF RELATED PUBLICA nON S
The following publications contain information not included in this manual but necessary
for Q complete understanding of the Extended Performance Rapid Access Data (EP RAD)
File when used with related XDS equipment.
Publication Title
Publication No.
Extended Performance RAD Storage System,
Models 7231/7232, Reference Manual
901557
S:gma Computer Systems Interface Design
',"anual
900973
Power Supply Mode! PT20, Technical Manual
901157
Sigma 5 and 7 Extended Performance Rapid
Access Data (RAD) File, Program No. 704978B,
- Di~gnostic Program Manual
901540
Periphera I Equipment Tester Model 7901,
Technic,,1 Manuel
901004
S~gma
2 Computer, Techt,ical Manual
900630
Sigma 2 Computer, Reference Manual
900964
5iJma 5 Computer, Technica: Manual
901172
Manual
9009j9
S!gma 7 Computer, Technical Manual
901060
Sinma 7 Computer, Reference Manual
900950
lv'.uitiplexing hput/OlJtput Processor, Modp.ls
ts271/8471 and 8272/8472, Technical /W:Jnu~1
<;01515
$elector Input/Output Processor (SlOP), Maciel
R2H5 and 8485, Technical M""nual
901195
Diagnostic Control Program for Sigma 5 and
Sigma 7 Computer Peripheral Devices, Reference Manua!
900712
Sigma 2 Systems Test Monitor, Diagnostic
Prl)gram Manuol
900841
Slgma 5 and 7 Systems Test Monitor,
Diagnostic Program Manual
901076
Sigma 2 High Capacity Rapid Access Data (RAD)
file Test, Diagnostic Program IIAanual
901538
Sigma 5 and 7 Relocatable Diagn,,:)5tic Program
Loader, Diagnostic Program Manual
900972
Sigma 2 Relocatable Diagnostic Program Loader,
Diagnostic Program Manual
901128
Sigma 5 Computer,
~eference
ix/x
XDS 901565
Paragraphs 1 -1 to 1-5
SECTION I
INTRODUCTION
1-1 SCOPE OF ""-ANUAL
and other engineering drawings and provides a list of engineering drawings required to supplement this ~a:oual.
This manua I provides technic'.:! I information pertaining to the
Extended Performance Rapid Access Data Fi Ie (E P RAD fi Ie),
which consists of the EP RAD Controller Model 7231 and
from one to eight EP RAD Storage Units Model 7232. An
EP RAD fi Ie is an item of peripheral equipment which car.
be used with any of the Sigma series computers (Sigma 2,
Sigma 5, or Sigma 7). The EP RAD file is manufactured by
Xerox Data Systems, EI Se8undo, California.
The documents in the list of related publicGtions should be
consulted to sUF;:>lement the information in th::; manual. A
complete set of documents for this equipment consists of
this manual, related publications, engineering drawings,
wire list", diagnostic progroMS; and other data supplied
with "the equipment.
1-2 ORGANIZA lION OF
JvV~NUAL
The information contained ir. +his manual is organized as
fonows:
o. Section I outlines ~:le content and organization of
thE: manua i end piovides a .Srief description ot the EP RAG
fi and its function.
Ie
n
b. Section describ\O.:. the location and function of
ea-:h switch end indicator (.jnel provides simple machine
language progmms which ii lust rate the relation of the
EP RAD Hie to the compute •..:,peration.
c. SecHon III describes the operation of the EP RAD
fi Ie in term$ of data flow tb;-ough registers in response to
signals generated by the C0111puter. No reference is made
to signa Is or logic equations, and block diagrams and flow
diagrams support the text.
.
g. Section VII contains cable diagrams; modu Ie location charts; power, cooling, and space requirements; and
othe~ elate required for installation, including preoperationa I check procedures.
h. Section VIII provides lists of specia! tools and test
eqlJipment; schedu les and procedures for cleaning, lubricating, and preventive maintenance testing; and procedures
for performance testing, trouble analysis, and cdiustment.
i. Section IX contains an illustrated parts oi-e-:lkdown
and parts list.
1-3 DESCRIPTION
1-J! EP RAD FilE
An EP RAD file consists of from one to eight EP RAD storage
uniis (Jnd associated interconnecting cables. E"cn EP R.A.D
stc.mge unit consists of a cabinet that contains 0 disc fi Ie,
ail '::' RAD selection unit, a power distributior. p;.mel, a
moiO:- control assembly .. a Power Supply Model PT20, and
ini~rconnecting cables, wiring harnesses, and pressure iines.
(See figures 1-1 and 1-2.) An EP RAD control !?,. is collocat~cl w:th one of the EP RAD storage un fts. (See figure;
1-3. )
Eo-:h EP RAO storage unit can accommodate m':)re than 6
miilioil bytes of daTa. An EP RAD file with the maximum
eight EP ~D storage u.1its can sbre more thar; 50 mi Ilion
byte5 of data. Data byt~s may be re:ld from; or written
into, the EP RAD storage unit at an average rate of more
than 350,000 bytes per second.
1-5 EP RAD CONTROLLER
d. Section IV contain:; a detai led description of the
operation of all circuits of the EP RAD file. The purpose of
.each signa I, the logic equl..tions which control the signal
!eve I, and the re lations between signa Is are described;
supp':Jrting logic diagrams, timing diagrams, and flow diagrams are included.
e. Section V lists all s:gnals of the EP RAD file, describes the function of each signal, and contains phase
sequence charts for each EP RAD fi Ie operation.
f. Section VI inc ludes schematic diagrams for control
pane Is, power distribution, termina I boards, log ic diagrams,
An ::P RAD controller consists of three 32-moculc chmsis
and the 74 modules required for operation with an eightbit ':':.::Ita path. For the optional 16-bii data puth, five additional modules are needed for a total of 79 mo.:lules; for
the ::ptional 32-bit data path, eight additional modu les are
needed for a tota I of 82 modu les.
The EP RAD controller, which is the interface be·tween the
lOP and the EP RAD storage units, responds to command
signals from the lOP. Signais returned from the EP RAD
control !er to the 10 P indicate the status of an E P R.6.D
storage unit and the status of the control timing of data
transfers between an EP RAD storage unit and the lOP.
1-1
XDS 901565
r
DISC FILE
._--_.i
901 565A. 101
------,
Figure 1-1.
1-2
EP RAD Storage Unlt, Front View
XDS 901565
1
MOTOR
CONTROL
ASSEMBLY
POWER
DISTRIBUTION
PANEL
\v'
'i;:'~
X:
.,r
,I
'4
"1.
',',:,'1'·':,',
:~
LINE
'''l
5'"
FILTERS
,
~~""".
1iIiI!i.iSi. . . ..
"",,,,,,,,,,.,.,,,"",,,,,,,,,
PT20
POWER SUPPLY
'.1#
i
~ ,.~1
.",••
90J565A.l~
Figure 1-2.
EP RA.D Storage Unit, Rear View
1-3
XDS 901565
EP RAD CONTROLLER
DISC
FILE
901565A. 103
Figure 1-3. EP RAD Storage Unit with EP RAD Controller r Front View
1-4
XDS 901565
1-6 EP RAD SELECTION UNIT
An EP RAD selection unit consists of two 32-module chassis
and the 36 modules required for operation. If the logical
sparing option is selected, a maximum of 13 additio~al
modules may be used, fora total of 49 modules. The EP RAD
selection unit responds to signals received from the EP RAD
controller and writes data on the disc fi Ie or reads data from
the disc file, as required.
1-7 DISC FILE
The disc file contains four rotating magnetic surfaces for
recording digital data on 512 tracks. A separate read/write
head is provided for each of the 512 tracks, and 64 spare
read/write heads and tracks are available. One of the
magnetic surfaces has on active sector timing track and read
head. (A timing track is written on each surface of the
disc, so that three spare timing tracks are avai lable.) The
magnetic surfaces are sealed in a pressurized bu lkhead
which is maintained at 0 p{~ssure higher than standard atmospheric pres~ure.
1-8 MOTOR CONTROL ASSEMBLY
The motor control assembly r.ontro!s the sequence of operations for stc.rtin3 and stopping the disc fi Ie motor and monitors
the status of the disc file motor during operation. During
Paragraphs i -6 to 1 -10
the start sequence, the motor control assembly aborts operation if the disc file does not reach 300 rpm within a preset
time delay. When power is removed for shutdown or if a
power failure is sensed, the motor controlassembly controls
both .dynamic and mechanica I braki ng.
1-9 POWER DISTRIBUTION PANEL
The power distribution panel controls power from either the
control console of the computer installation or the EP RAD
storage unit.
1-10 POWER·SUPPlY MODEL PT20
Pov/er Supply Model PT20 (also referred to in this mtlIVJO!
as the PT20 power supply) is a stand::.rd XDSpcwer supply
and is described in detail in XDS publication No. 901157.
The power input required is approximately 9A from a singlephase 117V, 60Hz source. The power supply provides outputs of +4V, +8V, -8V, +25V, -25V, and +45V, with current capability sufficient for on EP RAD selection unit and
all EP RAD controller if both items are insta: ied in the EP
RAD skI/age unit. When an EP RAD fife con~ains more than
or,e EP RAD storage unit, connections from PT20 power
supplies should be distdbuted among a II phasc~of the threepho!ie source. Overvoltage and short circuit ;':>fotection for
the::PT20 power supplyis providedbf modules cndbya resettC'ble circuit breaker.
1-5/1-6
XDS 901565
Paragraph!> 2-1 to 2-6
SECTION II
OPERATION AND PROGRAMMING
2-1 GENERAL
2-4 EP RAD STOPAGE UNIT ADDRESS SWITCtiES
The EP RAD file is controlled by programmed instructions
processed by the CPU and responds to commands and orders
from the lOP. Controls of the EP RAD file establish its
address, indicate whether an F.!' RAD storage unit is on line
or offline, prov!de for write protection of selected groups
of tracks, and provide for turn-on and shutdown of E P RAD
fj Ie operations. Controls of the EP RAD fi Ie are described
in this section. A portion of a program, in machine lon~ 9. uage, is provided to illustrate the relation between the
, programs and the tP RAD fi Ie operations.
Three switches on an LT26 Switch Comparator mooule (location A7, figure 7-4) establi::;h a three-bit address for each
EP R.ft...D storage unit. (See table 2-2 and figure 2-1.)
2-5 ONLINE/OFFLINE SWITCH
A switch on the LT25 Special Purpose modu Ie {ioc'ation C23}
transfers the EP RAD file from online to offline '")peration.
When the switch is in the 0 po~ition, the EP PAD fi Ie is
ofFlir.e; when the switch is in the 1 position, the EP RAD
file ;5 on line. (See figure 2-2. )
2 -2 CO NTRO LS
2-6 MEMORY PROTECTION SWiTCHES
2-3 EP RAD CONTROLLER ADDRESS SWITCHES
Four switches on an LT26 S.','itch Comparator module (location C24, figurE'! 7 -5) estobiish the four-bit address of the
EP RAD controller. (See toble 2-1 and figure 2-1.)
Table 2-1.
54-2*
S2-2
51-2
Address
DoVinl
Down'
1000
Up
-1001
Down
1010
Positions (Locat:on A7)
t
53-1
'---
Up ,
,
I Down'
Up
Do\:\'n
Up
Down
Up
Down
. Do"m
Up
Up
EP RAO Storage L!nit Address 5''''itch
Table 2-2.
EP RAD Controller Address Switch
Positions (~ocation C24)
S3-2
Sixteen switches on the front panel of the EP RAD selection
unit (figure 1-1) may be used to ;,xevent any C Plj program
from writingcm selected groups or track~ on the disc fi Ie.
The toggle switches are labeled MEMORY PROT!:CTION
lJown
S2-1
0
Dowr.
I
01-
S ~ -1
Address*
Down D
000
[)OW:1
Down
Up
001
C''';NI1
Up
Down
010
Up
Down
Down
100
Up
DO\'/'1
Up
101
1011
Up
Up
Up
Down
Down
1100
Up
Up
Down
Up
1101
Up
Up
Up
Down
1110
Up
Up
110
Up,
Up
Up
Up
~ 1111
Up
Up
111
II
-"~"':e-- -
*Switch 54-2 position cannot be changed while
the LT26 rnodu Ie is in place
O. Switch pcsition designations
connot be read wh de the l T26 module IS In place
t Up is 1; down is
I
'Up is
~~wn
~nnot
~J
is O. S\:itch POSiti::eSignoti:ns
be reed while the LT26 rr>oduleis in pioce
2-1
XDS 901565
~'VCcJ,~ t
2'+
~---------------------------------~~~~~~--~--~-~----~--~~~----------------------------------------
11
N~8
0
.
I
.
~
__________._________________.____________________________________________ um and
a one-byte postamb!e... The check;;m is generr:ted by controllel" circuits during the write ~~quence, ana :s ...... ritten
after all data bytes hove been stored. Jhe postamble is a
string of eight zelos~!2. iden~:fies the end ct ~he sector ......
A gIJP containing no data of any L:ind separate~ T·1e sectors.
DuriLg the time that t~is gap is und~r the reaCl/"'rite heads,
prepOl.:ttory operations .:.Ire perfor ..ned by the con'roller.
3-3 MFCHANICAL
FUNCTIO~S
Dudn£"' operation of the EP RAD fi Ie, the read/write heads
whi-:'; write on (or read from) the magnetic surf.:::t:es of the
disc: fiie are held from contact With the magne;';c surfaces
by c ·j:,in film L-f air .. This technique, called floating head
or fiying head, pemlits each head to be very c:o:;e te a
surfuce without contact and eliminates design p·oblems
associated with fixed heads. For example, if th~ ~osition
of a lead/write head is fixed, the C:!sto.nce betv.:~en the
head and the m'Jving surface vcries sl ightly bf'cQuse of
irretju!orities of surface flatness or because of q slight eccentricity of the disc axis of rotation. The vor:c.tion in
flux strength introcllJcec by this variation in distance causes
variation in signal !eveh. In tJddition, because the distance
must be relatively k:rge to preverit the possioiiit:r of contact, much of the strength of the magnetic field is used in
the resu hant air gap. However, with the flying head system of the EP RAD file, the design distance betwt:'en head
and surface is maintained only whi Ie the disc is spinning
fmter than 300 rpm. Therefore, contoct between the flying heads and the disc surfaces must be reliev~d unti I the
3--1
,- -
-- -
I
TO/FROM
lOP
-E'P RADCONTROLLER
--j
-
.
I
I
I
I
I
I
I
DATA BUFFER
I
TpCET/FROM
'"T1
tOO
{jjll
I
I
I1-----
T----
I
11
PET
INTERFACE
:
I, - -
-:--
, - i_ _
@
w
!..
, --
I
'
I
TO/FROM
lOP
:
I
--- -
-
~E;N-;; ~---- - : - - - - - ,
r -- - ---,
I
I.
I
I
I
I
I
TO/FROM
O-;HER
I
~---~~----~------------r---+sTORAGe
_ _ . _. _____ ,'JF.VI':ES
I
I
I."
I
I
UNIT
I
I./I~ EPL,)
I" S~LEC;[ON
,
I
I
CABINET
~_~o~ _ _ _ _ _
I
,
I
I
I
I I
,
I
I
I
I
ENABLING
SIGNAL
,
I
I
I
I
'I
I
REAO,tWRtTE
COUPLER CIRCUITS
I
I
I
I
I
I I
L __._-.J
T
'-:0: __C~()~ ---i,
DATA
____J
L ______ - -
e
~~:
TO/FROM
ADDITIONAL
} STORAGE
---t----:--..,.----t----t--;-..
DEVICE$
I
I
r
,
I
I
I
I
I
I
I
L ___ J
CABINET
64
L __ 1_ - --- I
-
...!, ~ ~C.!!?N~'L. -
8
~-
4
- - - - -
,
~-----------------------~----------------~
TO I 'FROM DISC FILE
I
-~.
XDS 901565
SELECTION
UNIT
SECTOR
901565,6.. 30~
Figure 3-2. EP RAD Disc Fi Ie, Data O rganization
3-3
Paragraphs 3-4 to 3-9
XDS 901565
300 rpm rote is attained. During a start sequence, the
motor control assembly relieves the pressure holding the
heads against the disc surface. During a stop sequence,
the motor control assembly controls dynamic and mechanical braking of the disc. During a start sequence or a stop
sequence, the motor control assembly monitors a signal
which indicates the speed of the disc file motor.
During each phose of the sequence, the phase control
circuits respond to lOP signals, selection unit signals, and
internally generated signals to determine when to go from
one phase to another. During this sequence of phases, data
is transferred between the selection unit and the lOP through
the data buffer, the selection unit interface, and the subcontroller and expanded interface circuits.
3-4 POWER DISTRIBUTION
3-6 lOP INTERFACE
Externa I three-phase ac power is applied to the power
distribution panel through an rf filter assembly. The ac
pOVle; passes directly from the power distribution panel to
the motor control assembly. Application of ac power for
the controller, selection unit, or fans may be controlled
either from the operator panel of the computer or from the
EP RAD storage IJnit. When the LOCAL/REMOTE switch
on the power distribution panel is in the LOCAL position,
power is applied directly to the PT20 power supply and
he fans. When the LOCAL/REMOTE switch is in the
MOTE position, ac power is controlled from the operator
control panel of the computer. A delay circuit in the power
distribution panel prevents application of ac power to more
than one EP RAD stcrage unit ut a tim~ when ac power is
first applied. This delay cause:; a sequential application of
ac power to each EP RAD storage unit, thereby min!mizing
starting surges. A power fail-safe circuit senses two signals
derived from the ac power source and one dc si gna I from the
PT20 power supply. Powerfailure causesa controlled shutdown of the EP RAD storage unit. If the EP RADstorage unit
is in communication with the lOP at the time of .. hutdown, a
signal is sent to tj,~ lOP to ind:cate the unusual end.
The response of the subcontroller to lOP commands is summariz.ed in figure 3-3. The five commands associated with
CPU instructions are as follows:
4
3-5 EP RAD CONTROLLER
In a computer instClllation, the CP RAD controller is only
one of several de~ice controller:; exchangi ng data with the
computer memory through the iOP. Two techniques are
used to limit communication wi'-h the iOP to only one conJer at any time: For some !')P commands, only one
• ... troller is addressed, and on!y the addressed controller
can respond. For other 10 P commands, a priority chain
established by cable routing Iimits response to the highest
priority controller that is awaiHng that command.
The subcontro!!er portion of the EP RAD controller (figure
3-1) monitors signals from the Iep and determines if and
how the EP RAD fi Ie responds to commands. The subcontroller responds to all control signals, either by passing
the signals to other controllers as:cciCited with the computer
installation or by returning signc.ds to the lOP. The subcontroller controls exchange of data on the eight-bit data
path. The expanded interface ciicuits provide up to 24
additional data lines when a 16-bit or a 32-bit data path
is used. When the EP RAD fi Ie is operating off! ine, signals are received from the Peripheral Equipment Tester
'~(PET) Model 7901 through the PET interface.
Commands from the lOP cause phose control circuits of the
buffer to cycle through a definite sequence of phases.
_
3-4
function
Mnemonic
Ala
Acknowledge input/output interrupt
HIO
Halt input/output cperaHon
TDV
Test device
TIO
Test input/output
SIO
Start input/output
The ackriowledge service co II (ASC) cOIT/mond is g€neroted
by the lOP in response to a service call from the su!;::cntroller.
3-7 Ala Command
The AIO command, which is generatf'd by the lOP ,\,llen
an interrupt is detected, is not oddltnsed to any device or
device controller. Only th2 highest priority devi-::<=> '.;ontroller wirh an interrupt pe:nding can respond to th~ hIO
command. Any device controller witnout an interp>pt
pending !,'lsses the signals to the next device controller in
the prier:!y 3equence. If the EP RAD controller is the
highest V:ority device controller with all interrupt rending,
it responds to the AIO command by tr,:msmitting Hs o:!dress
and the COlltents of its device address register (U-r8?is~er)
to the lOP and by transmitting signals that indicatf; t~e
cause of t!1e interrupt. When an AIO command is accepted,
the interrupt condition is cleared.
.
3-8 HIC'.:.. Command
The HIO command, which is addressed to a spec:fil.. device
controller .• hoits an input/output operation being processed
by the EP PAD controller and returns function response signals and condition code signals to the lOP. These signals
indicate the status of the EP RAD controller to the !OPand
the CPU.
3-9 TDY Command
The TDV command, which is fJdd,essed to a specific device
controller, returns functicn response signals and t::ondition
code signals to the lOP. These signuls indicate any errors
XDS 901565
START
NO
WAIT FOR
FUNCTION STROBE
AND FUNCTION
INDICATOR
REQUEST ORDER
OUT SERVICE
CYCLE
YES
NO
WAIT FOR ASC
YES
RETURN ADiJRESSES
AND STATUS OF
DEVICE AND l1EVICE
CONTROLLER TO lOP
HALT I/O
OPERATION~
I
ORDE~-]
STORE
CODE
~-----------~
--A
PASS SIGNp. LS TO
NEXT DEVICE
YES
CONTRO!.LER
IN PRIORITY SFCHJENCE
RETURN FUNCTION
RESPONSE SIGNALS
AND CONDiTION
CODES Te lOP
-'T----,
:
I
SIO
I
~~
A
RETURN FUNCTiON
RESPONSE SIGNALS
AND CONDITiON
CODES TO lOP
901565A. 303
Figure 3-3.
Response to lOP Commands, Fluw Diagram
3-5
Paragraphs 3-10 to 3-13
XDS 901565
that occur during an input/output operation and the nature
of any detected .errors.
3-10 TIO Command
The TIO command, which is addressed to a specific device
controller, returns function response .signa Is and condition
code signa Is to the lOP. These signals indicate the status
of the EP RAD controller to the lOP and the cpu. The
TIO command performs a function simi lar to that of the
HIO command, without causing (] halt.
3-11 SIO Command
The SIO command, which is addressed to a specific device
controller, returns function response signa Is and condition
code signals to the lOP. These signals indicate the status
of the EP RAD controller tc the lOP and the CPU. In addi)on, the SIO command starts an input/output operation if
e EP RAD file is ready. The first response is to request
an order out service cycle fr(j:n the lOP. During this service cyc Ie, a code for one of f;ve orders {seek, sense,
read, write, or checkwrite} is stored in the order register
of the EP RAD controller. A :zyuence of ASCcommands
in response to service calls from the EP RAD controller
then causes the ord~r to be executed.
e
Table 3-1. Service Cycle Operations
Operation
Service Cycle
Order out
Control information is transmitted from
the lOP to the controller. First service
eyc Ie of any input/output opewtion
Order in
Control information is transmitted from
the controller to the lOP. Last service
cycle of any input/output operation
Data out
Data is transmitted from the computer
memory through the lOP to t!'e disc file.
Four bytes of data are transmitted during
each service cycle; therefore, a rapid
sequence of service cycles is required
during execution of a write order or a
eheckwri te order. For a seek order I
two data out service cyc les ar~ iequired
Dato in
,
3-12 INTERNAL OPERA TIOl'!S
Data i: tmnsmitted from the di:~ fi Ie
through the lOP to the ccmput~r memory. Four bytes of data are tr(l'1smitted
during each service cycle;, therefore, a
rapid sequence of service cycles is required during execution of a rt..ad order.
For a sense order, three data i'l service
cycles are required
~--.----~--~-------------------------------~
•
In response to an AIO, HIO, TIO, TDV, or SIO command
from the JOP, the EP RAD cO:1ii'oller gathers data avai lab:e
in registers and flip-flops of the controller, or from signals
available at the selection unit interface, and transmits
the data to the lOP as function response signals or condit:on
code· s;gnals. If an SIO comrri~ ..\d is accepted, the I/O
operation that resL'lts depends on the order reCEived during
the order out service cycle. For each order, the lOP responds to a sequence of service calls from the EP HAD conroHer hy generating ASC cO::lmands. Each service coli
.) identified by a two-bit code as requesting one of the
four types of service cycles list3d in table 3-1.
Regardless of the order receivecl, 0 spec Fic number of
bytes ore exchanged as the p~ar~ controi circuits of the
data buffer cycle through a definite sequence of phases.
If a seek order is stored, subsequent data out service co lis
cause two bytes of data to be sf 0red in controller registers.
If a sense order is stored, sub~equent data in service co lis
cause three bytes of data to t-A transmitted to the lOP. If
a write order is stored, subseqt;entdata out service cal;s
cause data bytes in memory to be stored in the disc fi Ie.
lf a read order is stored, subsequent data in service co lis
cause data from the disc fi Ie 10 be stored in memory. If
a checkwrite order is stored, d:.tta accepted from memory
is compared with data read from the disc file. During or
following execution of any of these orders, termina I order
data moy be received from the lOP or on order in service
cat! may cause data to be sent to the lOP.
3-6
3-13 .:jeek Order
A diagi.:tm that summarizes the transfer of data :0+::' the
EP RAD controller during the execution of a seek crder is
preser.:~d in ·figure 3-4. During eAecution of a :..:ek order,
two Lyi'C3 of data are stored in the track addiess I egi~ter
(T -reg;eter) and the sector register (S-iegister). Execution
of a slJb~cquent read order, write order, or checlwrite order
begin: "t this location in the disc file, (When r.o seek
order is used, operations begin at the location sto:-cd in
the T-register and S-register at the time that the order is
received. )
.
A byb of data is first accepted from the lOP and is stored
in th(; i-register.As this byte is transferred to thf.~ Jregister, an additional byte is requested from the lOP.
Bits 1 ihrough 7 of the first byte are stored in the higher
order ;I:r:··ftops of the T-register. After the seco~d byte
is mc\'eJ from the I-register to the J-register,· thE; four
highe~ order bits (bits 0 through 3) of the second byi'e are
placed :., the lower order fl ip-flops of the T -regiSitr, and
the fou:- lower order bits (bits 4 through 7) are placed in
the S-register.
The byte counter of the controller identifies the bytes
received and generates timing signal<; which control the
transfer of data from the J -register. An incorrect length
sigl!al is generated by the controller if a byte count other
than two is specified in the I/O doubleword associated
with the seek order.
XDS 901565
FROM---:::.,.8---... I-REGISTER t---ij81'-1111-t$
J1 H'Ii--r-i.--..".
REGISTER
lOP
~El
~
o
1
i
"I-
T~CK
2 3 4 5,6 7';0
!
I·
TO \
T-REGISTER
Paragraphs 3-14 to 3-15
S
BYTE 2
~
I SECTO~]
T-REGISTER
TC ---;r--'--_---'
BYTE 2
(BITS 0-3)
2 3· 4 5 6 7
..;I~Il-~~~
- - - l..
S-REGlSTER
REGISTER
BYTE 2
NOTES:,
(~ITS
4-7)
1. INDICATED TIMING CONTROL SIGNALS (Te)
ARE NOT IDENTICAl.
2. IF BITS 0-2 OF BYi= 1 ARE ONES, TRACK DOES NOT EXIST
901565A.304
Figure 3-4.
Seek Order Data Path, Clock Diagram
3-14 Sense Order
---Fipure 3-5 summarizes the i,ansfer of data from the EP RAD
controller dut'lng execution of a sense order. Three bytes
of Jato are transferred from the EP RAD controller to the
computer memory through The IOP. The sense order is used
to speed up input/output operations by permitt:ng the CPU
program to determine fhe locat;on avallable before starting
a t:ansfer of datt]o The a'"erage waiting time of he If a disc
revolution can thereby be rfS:duced to one sector time.
The first byte of data to be stored in the O-register consists of bits 0 through 6 from the track address register (Tregister) and one bit from the selection unit. The bit from
the selection unit indicates whether the addressed track is
write-protected. The sec.ond byte of data consists of b;ts
7 through 10 from the T -re~ister and four bits from the sector register (S-register). The bits from the T-register are
stored in bits a through 3 of the K-register; the bits from
the S-register are stored in r' t'i 4 through 7 of the K -register.
This byte is transferred to the O-register after the first byte
is accepted from the O-register by the lOP. The third
byte of data consists of four ~Jnused bits and four bits which
indicate the address of the sector currently under the read/
write heads of the disc fi Ie. (The bits in the S-register
indicate the sector addressed by the EP RAD controller.)
The third byte, in its turn, is transferred to the 0 -register,
then to the lOP.
The byte counter of the controller identifies the bytes received and generates timing signa Is wh ich control transfer
of data from one regisier to anothel. Transfei vf data from
the O-register to the lOP is coMroll"'!d by th~ !",hase contrcl circuits. An incorrect leng~h signai is ge,l.:!rated by
the controller if a byte count ot!1er than three is sj)ecified
in the I/O doubleword associated with the ser.~: order. A
seC~f):- unavailable sis:Jnal is gen~rc;ted if the ;- -r~gh.ter and
S-register huve incr~mented beyo(ld the last a\'~ilable sector.
3~
15 Write Order
A di'1!=}ram that summarizes data transfers within the EP RAD
controller during execution of c: write order jc: ~}resented in
figurp. 3-6. D .'ring execution of a write ordel, defa bytes
for on integra! number of sectors are transferred from the
computer memory to the disc file through the lOP, the controller, and the selection unit. (If less than 10:=4 datci
byt~r are transferred for a sector, hytes consistir.g of eight
zeros (0000 0000) 0re written unti I the sector is complete.)
All 1024 data byres for each 5ector are writterl the first
tim(> the addressed sector passes under the read/write heads.
If a write operation is attempted in a write-protected track,
the write order is not executed and the write-protect violai'i.:>n is reported to the lOP.
FOUi bytes of data are accepted by the I-regist~r during
each data out service cyc Ie. For an eight-bit data poth
from the lOP, one do~a byte is accepted and transferred
to the J -register before the next data byte is requested.
For a 16-bit or 32-bit data path from the lOP, two or four
bytes are accepted sirr.ultaneously. Each byte is moved to
3-7
XDS 901565
FROM
W(NOTE 4' 1SELECTION ---.:.::...:..::...:.:....'+-.-r---""
UNIT
TC~
7
~.O-REGISTER II}' ~ TO lOP
.;
TREGISTER
TC
BYTE 2
(BITS 7-10)
SREGISTER 11
TC
FROM
SELECTION
UNIT
Te-
~
I
)
:I
)
K-
4£
}
S REGISTER 1
BYTE 2
(BITS 0-3)
BYTE 3
~...
BYTE l - - - - +
.......
-:----BYfE 2
txJXl
I-
[W
T~C K
012345670
FRO/v\
T-REG~STER
"'1 ~
SY TE 3--~
1__
SECTO r [XJ)?L0i?TE 3)
23456/01234567
I
-I S-R~~~~ER I--
NOTES:
1. INDICA. TED TIMING CONTROL SIGNALS (Te) ARE NOT IDEhlTICAL
2. IF BITS 1 ANL; 2 OF BYTE 1 ARE ONES, SECTOR IS UNAVAILAEtL!:
3. SELECTION UNIT PROVIDES 4 BITS, WHICH INDICA TE CURR::~H
SECTOR AT READ/WRITE HEADS
4. SELECTION UNIT PROVIDES W BIT, WHICH INDICATES IF Tfv:..CK IS
WRITE-PROTECTED(W := 1 IF WRITE-PROTECTED)
90156SA.305
figure 3-5. Sense Order Data Path, Block Diagram
3-8
:!1
(Q
c
ro
w
\
FROM
lOP
I
?~
r0O
cL
~
S
g
I
()
:r
1
FAST
ACCESS
DATA
f"EMORY
A
~.
r0O
FWA (NOTE 4)
OR
~Rt. (NOTE 5)
a..
~
0
L
41
Q
0
""C
0
fr
CP
0
()
A"
0
Q'
CO
a
3
TC4--]-
r1~K-P--R-E-G-!S-T-ER""~.~
I
I
I
41
NOTES:
1. lOP DATA PATH MAY BE 8, 16 OR 32 BITS WIDE
2. P-R;:;GI~TER, ;:P-REGI~-:-cR N-D I.-REC-'IS', c:I; COI'-lT::OL ACtF.SS
TO ;6 :~lGiST:R~ 11 ; f"ST A(C~~~ MEt-~0~Y
3. INDICATED Tl~. . . ll ~G C()~ JTROL (Te) SIGNALS ARE NO~ IDENTICAL
4. FWAIS 4-BIT FAST MEMORY WKlTE ADDRESS
5. FRA IS 4-BlT FAST MEMORY READ ADDRESS
W
I
'<>
~
I
L_r----I T~
(\)
()
CHECKSUM
D-REGISTER
~ ~~i;nON
XDS 901565
the higher orde.r byte of the I -register and is transferred to
the J -register before additional data bytes are requested.
Data bytes in the J-register a!"e transferred to the fast access memory (FAM) module under control of the J -pointer
register (JP-register) and timing circuits. The FAM module contains 16 addressable eight-;';it registers. The JPregister stores a four-bit code wh ich addresses one of the
16 registers. A byte transferred from the J-register to the
FAM module is c.tored in the location addressed by the lregister. After a byte is stored in the FAM module, the
number in the J P-register is incremented. The incrementing
process is accompiished by causing the outputs of the lregister to generate a code next in binary sequence to the
code stored in the JP-register. In the FAM write cycle,
a data byte is transferred from the J -register to an addressed
regist~r in the FAM module, ana the incremented address
. .transferred from the L-regist~r to the J P-reg ister.
~ta
bytes in the FAM module are read into the K-register
under control of the K-pointer register (KP-register) and
timing circuits. The KP-register is incremented by reading
,the outputs of the L-register during a FAM read cycle in
"which data is read from the addressed register iil the FAM
module into the K-register. 'Ihe L-register stores a fourbit code wh ich addresses one of t!le 16 reg isters in the FAM
module.
Data stored in the K-regi5.i"er is transferred to the D-registejO
onE, byte ,.It Ci time. Data stored in the D-reglster is transferred seria Ily through the selccr!cn unit to the addressed
track and sector of the disc fi Ie. Th is data transfer takes
place at a clock rate established by timing circuits in the
controller. Execution of a write order requires control of
independently timE:d data transfers, Tral1~fer of dqta from
the lOP to the I-register is deF'e~aent on the spee0 of response of the lOP to a service c;:.:il from the controller.
lnce transfer of data from the ~-register to the di::c fiie
st keep pace with the cleek s;9na I:; generated in the
vntroller, the FAM mod'J Ie mu~f- :lave data avoi laDle for
O
the K -register in time for tramfer to the D -register. Adc.1itional circuits associated with :h0 data path monitor and
control the process so a continuo! flow of data takes place.
The phase control circuits ano associated timing circuits
regu late the process of rlota transfer rromlhc 10 P to the
I-registN into the J -register.
e
The RK-counlc;- keeps count of the number of active bytes
in the FAM rno.--Iule. Each time a byte is wrilten into the
FAM modu Ie, the count is decrea~ed by one; each ti me a
byte is read from the FAM modu ie, the count is increased
-by one. Signals controlled by t~e RK-counter request a
FAM write cyc Ie whenever the number of active bytes is
8 or less. Signals general-ed within the controller indicate
whether the J -register or K-register is fi lied. The K.~ register tak.es priority when the K-register is not fi I led
(thereby cau!>ing a request for reading dal-o from the FAM
modu Ie to the K-register), and the J -reg ister is fi lied
~reby causing a request for writing dato from the Jister into the FAM module). This priority assures that
•
a byte is always avai lable for the D-register. The FAM
module is kept filled by storing a large number of bytes
initially and by retaining service connect status with the
lOP for a period long enough to store 8 to 12 bytes or to
fill the FAM module, whichever is required.
The writing process inc ludes writing a preamble and postamble ;" addition to the 1024 data bytes (figure 3-L). This
sequer:ce is controlled by timing circuits associated with
the selection unit interface. After a write order is stored,
a search is conducted for the addressed track and sector.
The bit end byte counter (B-counter) then controls the sequenCE: of storing the preamble codes in the K-reg;ste:-,
counting the 1024 dato bytes, and storing the checksl;m in
the K--register following the last dat~ byte. The checksum
is deve loped in the P-reg ister wh i Ie the data bytes are
being transferred from the D-register to the select;on unit.
Wh ile ine gap separating each sector on the disc fi ie is
under the read/write heads, an incrementing procf'SS takes
place b~tween the T-register and S-register, and ihf' pregister. If data is to be written into the next sector, the
numbe~ in the S-register must be increased by one ~o that
a match between the S-register code and the sele-:.:tion unit
sector signal code is po:;sible. If the S-register c,. . r:toins
the code lOll, which identifies sector 11, the neyt code
in sequenc~ must be 0000 and the track address in the Tregister rr'Ic;t be increased by one. Therefore, the contents
of the T --register and the S-reg ister are temporari i t ~t:)Ted
in the 0 regisrer. This value is incremeded by 0 •• (" in the
process~f return to the S-rp.gister end the T -regi;t~., so
that the~e two registers cor.tain the COITeet codes ~efore
the nex'" "ector is availabl:-. The contents of the -; -register
are al~~.) iran:.;mitted to the selection unit by way of t:l€: Pregistel.
The tech"ique used for encoding the sequence of b:t:; 0:1
the magr, o~;c surface of the disc is known by varic'J$ names
(such a~ f../lOnchester, modified nonreturn-to-zero, heq;Jency
modulation, and Ferranti). The technique (cal!ed Nonchester t"i!coding in this mcmual) has the advantage that a
separate .:.lock track is not required on thE magnetic 5urface
and that a c lock signa I can be extracted from the data signalas data is read from the mag:1etjc surface. (The ::eporate
sector pu I:;e track and index pu Ise track do not provide (J
c lock for each bit.) In summary, during errorless execution'
of a write order, the following operations take place:
a. I71mediately following storage of the write order,
at least eight data bytes are accepted from the lOP ;nto
the I-regist~r and are transferred through the J -register
into the FAM modu Ie.
b. A seorch for the addressed sector is conduc.:ted •
Aftsr the addressed location is found, the B-counter isused
to control storage of the preamble in the K-Iegisrer. This
preamble is transferred in parallel to the D-orcgi.;ter eight
bits at a time and is transmitted from the D-register to the
selection unit in serial format.
XDS 901565
c. After the preamble code has been transferred from
the K-register, data bytes are read from the FAM module
into the K-register and are transferred from the K-register
to the D-register for transmission to the selection unit.
Data bytes are continualiy accepted from the lOP throl,;gh
the I-register and the J -register and are stored in the FAM
modu Ie. The RK-counter keeps trock of the number of
active bytes in the FAM modu Ie. The B-counter keeps
track of the number of data bytes which have been written.
If less than 1024 data byt'3s ere received from the lOP,
data bytes of all zeros are written until a total of 1024
bytes is stored.
d. A checksum deveioped in the P-register is transferred to the K-register following the last data byte. After
the checkslJnl is transferred, the P-register is used to increment the track address and sector address to prepare for
"'riting in the next sector, if necessary. (If the write order
is ended, the track address and sedor Clddres5 are retained
unti I a new order is executed or unti I a seek order is used
to store a new track addr'S::;s and sector address. )
3-16 Read Order
A summary of data transfers within the EP KAD contra! ler
during exec.utio.'l of a read order is presented in figure 3-7.
Duri ng a read order, date bytes fo~ an integrcl number of
sectors are transferred frorr. the disc file to the computer
memory through the select;on unit, controller, and lOP.
A II 1024 data bytes for eat:h sector are read lhe first time
the addressed sector passes 0:tder the read/write heads.
Two types of read orders ere possible: a sector read orc!er
and a record read order. for a sector read order, a po..;ty
error is reported to the lOP ot the end of a l'ector in which
the error occurred; for a rcrord read order, a par ity er.ol
is reported to t!1e lOP aft€r n couni dof"l€ te~mina I order is
~ec;e ived by the control !~, .
After the read order is storzd, a search for the addressed
sector is conducted. When the addressed sector is found,
the timing circuits of the cC'ntroller must by synchronized
with clock signals transmitted from the selection unit.
'These c lock signa Is are derived from I~p Manch~ster encoded data. The prcambl~, ·",hich is initially a sequence
of ones end zeros ( ... 0101 01 O••• ), develops an easi Iy
identifiable clock :;ignal to indicate the start of data
written in a sector. A sync~ronizati on patiern of 1100
ends the preamble and ider.tifies the cl0ck immediately
preceding the 1024 doia hytes.
Bits are read serially from the selection unit into the 0register. Only data bytes are transferred to the J-register,
ope byte at a time, in the interval between the last bit of
one byte and the fiIsi bit of the succeeding byte.
Dota bytes in the J-register are transferred to the fast
access memory (F/.. M) modu Ie under control of the Jpointer register (JP--register) and timing circuits. The
FAM module contains i6 addressable eight-bit registers.
Paragraph 3 --16
The J P-registerstores a four-bit code wh ich addresses one
of the 16 registers. A byte transferred from the J-register
to the FAM module is stored in the location addressed by
the L-register. After a byte is stored in the FAM module,
the number in the J P-register is incremented by causing
the outputs of the l-register to generate a code next in
binary sequence to the code stored in the J P-register. In
the FAM write cycle, during wh ich a byte is transferred
from the J -register to an addressed register in the FP,M
module, the incremented address :s transferred from the
L-re::;ister to the J P-register.
Data bytes are read from the FAM module under control of
the K-pointer register (KP-register) and timing C:rcuit$.
The KP-register is incremented b), reading the outputs of
the ~-register during a FAM read cycle in which data is
read from the addressed FAM module location. The LreGister stores a four-bit code which address€5 one of the
16 registers in the FAM module. The procedlJre is similar
to t:. . .:::t for a FAM write cycle. The RK-counter keeps
count of the number c~ ~ctive bytes in the FAM modu Ie.
Ea.:;h time a byte is written into the FAM mODule the count
is increased by one; each time a byte is read from the FAM
m.).:h.de, the count is decreased by one. Sign:: 15 generated
withi'1 the controller indicate whether the J-register or the
K-register is filled. If the K-register is nOT n!led (thereby
cC'using a request for reading datc from the FA/~. module)
arc! the J -reg ister is fi lied (thereby causi ng co request for
wra:'-:3 data from the J -register into the FA,v,. mrxlule), the
J -register takes priority. This priority assure;;., a-.at a byte
a-'uilable in the D-register is acceF-tp.d by th''': FAM module
befure the selection unit trammits the first !:-ir d tne next
byre.
E"r:il time that the FAM module stores four data b{tes, an
oro ~r in service cycle is requested by the cc,ntr~lIer. If
morA than eight data bytes are stored in the FAM ~odule,
th~ contra! ler request!; two successiv~ order :;: ~ervice
cyc:.:s without relinquishing control of the I/O chwmel.
The ITleans for transfer of data from the FAM modu Ie tv the
a-register depends on the path width or the I/o d-:')nnel.
The phase control circuits and the associated timing cirCl,;is regulate the process of data transfer from ~he 0resister to the lOP.
For c.n eight-bit data path, bytes are read from the FAM
mo,::h;le to the K-register, then to the higher-order byte of
the O-register. The lOP accepts the data from the 0reg::ter. For a 16-·bif data path, the first byt~ is read from
the fAM module to the K-register, and the sccono byte is
read from the FAM module into the next-to-higher order
byte of the I-register. After two bytes have been counted t
they are transferred simultaneously to the O-registei. For
a 32-bit data path, the first byte is read from the FAM
meou Ie to the K -register, and the second byte is read from
the FAM module to 1he next-to-higher order byte of the
I-register, as for the 16-bit data path. The next two bytes
are read into successively lower order bytes of the 1register. After four bytes have been c0unted, they are
3-11
XDS 901565
FROM
SELECTION
UNIT
K-REGISTER
TC
S
D-REGISTER
8
1
O-REGISTER
rj
FAST
ACCESS
MEMORY
i-REGISTER
FWA (NOTE 4)
OR
4 FRA (NOTE 5)
Tc4 -----
a-REGISTER
4·->
L-REGISTER
JP-REGISTER
r----r--L_ __"
~------------------~
4
4
i-REGISTER
J
TO lOr
TC
KP-REGISTER t---r--L---"
I-REGISTER
TC
NOTES:
1. lOP DATA PATH MAY BE 8,16, OR 32 BITS WIDE
2. JP-REGiSTER, KP-REGISTER.. AND l-REGISTER CONTROL
ACCESS TO 16 REGISTERS !N FAST ACCESS MEMORY
3. INDICATED TIMING COt~TROl SIGNALS (Te) ARE
NOT IDENTICAL
4. FWA IS 4-BIT FAST MEMOR\' WRITE ADDRESS
5. FRA IS 4-SlT FAST MEMORY READ ADDRESS
O-REGISTER 8
901565A. 307
Figure 3-7. Read Order Data Path, Block Diagram
3-12
XDS 901565
transferred simultaneously from the I-register and K-register
into the a-register.
After all data bytes have been counted, stored in the Dregister, and transferred, the checksum written during the
write order is read from the se !ection unit. This checksum
is compared with a checksum developed in the P-register
during the read operation. If the two are not identical,
an error has occurred. For a sector read order, the error
is reported immediate IYi for a record read order, the error
is reported at the end of lhe record. The checksum is not
transferred to the FAM moduie.
Whi Ie the gap separating ench sector on the disc file is
under the read/write heads, en incrementing process takes
place between the T-register and S-rcgister, and the Pregister. If data is to be read from the next sector, the
number in the S-register must be increased by one so that
a match between the S-register code and the selection u.,it
sector signa I code is possible. if the S-register contains
the code 1011, which identifies sector 11, the next code
in sequence must be 0000, alld the track address in the Tregister must be increased by one. Therefore, after the
checksum stored in the P-reJi~ter is compared with the
checksum reod from the selection unit, the contents of the
T-register ar.d S-register are stored in the P-register. This
varue is incremented by one it"! the process of return to the
S-register and T -register so that these two registers contain
the correct codes before the next sector is avai fable. The
contents of the T-register are 0150 transmitted "0 the selection unit by way of the P-re:;isfer.
In summary, during errorless execution of a read order, the
following operations take place:
o. Immediate!y following storc3e of a read order, a
search for the addressed sedor is conducted. '''Ihen the
oddressed sector is found, !iii: i ng signa Is from the se lection
unit control the B-counter if) synchroni ze the sp.lection unit
circuits. The preamble codt; stored during the write ope!"ation identifies the beginning of data bytes.
b. Bits are received from the se Iretion unit in seriai
form, stored in the D-register, a~d transferred in eightbit bytes to the J -register. Dai'a from the J -register is
written into the FA:A module. Service calls are requested
by Ihe controller whenever four or more active bytes are'
in the FAM modu Ie.
c. For an eight-bit data pcth I/O channel, bytes are
read from the FAM module into the K-register, tl-ten to the
a-register, and are accepted by the lOP from the 0register. For the 16-bit or 32-bit data paths, bytes are
read from the FAM module ir.to the K-register and 1register, transferred to the a-register, then accepted by
the lOP.
d. After all data bytes have been read, a checksum
developed during the read operation is compared with a
Paragraphs 3-17 to 3-19
checksum developed and written during the write operation.
After comparison of the checksums, the P-register is used
to increment the track address and sector address to prepare
for reading the next sector, if necessary. (If the read order
is ended, the track address and sector address are retained
unti I a new order is executed or unti I a seek order is used
to store a new track address and sector address. )
3-17 Checkwrite Order
Data transfer during a checkwrite order is simi lor to that
for a write order (figure 3-6). However, data is not rransferred from the D-register to the selection unit. Instead,
the data that would normally be serially shiftee! out of the
D-register to the se lection unit is compared, b:t-by-bit,
with data read from the se lection unit. The two sets of
data shou Id be identical, because the checkwrite order is
used to compare data previously written and sti 1\ in computer me":l0ry with data reaa from the same sector in wh i ch
it W'-Ji> written.
3-1i) SELECTION UNIT INTERFACE
The primary function o~ selection unit interface circuits is
to re..:eive signals from and to generate and tmnsmit signals
to ~hE:: selection units. Signals passing between the EP RAD
controller andan EP RAD selection unit are exd",anged on
lineS common to all selection units in the EP RAC' file.
These signa Is perform the following functions:
.... Address one of eight posslb!-:- selectior, units.
b. Identify the sector under :-he read/wri~e '''leads of
the ~rldressed se lection unit.
Transmit data and track address codes and assoliming signals between the controller and the selection unit.
c.
ciat~d
d. Transmit status of the disc fi Ie to the .:ontroller for
use in response to iOP commands.
"
Transmit sector and index identification signals.
f. Transmit signals which identify the ty!)e of order
(write or read) to be executed.
3-i 9 EP RAD SELECTION UNIT
An E~ RAD selection unit writes data on, or rea.::!:; duta
from, the magnetic surface of the disc fi Ie in response to
orders from the EP Rh.D controller. For each order, the
controller addresses a selection unit, transmits c.. track
address to it, and controls the process of writing or reading. (See figure 3-1. )
The controller stores a three-bit address and transmits
three signals to device address circuits of ail selection
units. The device address circuits of the addres~ed selection
3-13
XDS 901565
unit generate on enabling signal which allows that selection
unit to make use of the common transmission lines.
The controller transmits an l1-bit cede, of which 9 bits are
a track address and 2 bits are not used, to the selection unit.
The write-protect logic reads the code stored in the track
register and generates a signal that indicates whether the
addressed track is write-protected. During execution of a
read order, write order, or checkwrite order, the co'ntroller transmits this 11-bit code at the start of each sector.
Signals from the trock register permit only one of the 512
read/write heads of the disc fi ie to be active. Three bits
select one of eight read/write coupler circuits; six bits
select the center tap of one of the 64 read/write heads
associated with the selected read/write coupler circuit.
A four-bit counter in tne EP RAD storage unit contains the
address of the sector under the read/write heads. This
a,)unter is cleared to 0000 by the index pu Ise read from the
3-14
sector timing track. As each sector pulse .is read at the
start of a new sector,the counter is incremented. After
the counter has advanced from 0000 to 101 i, it is cleared
b), the index pulse. Output signals of this counter are
compared with the contents of the sector register in the
EP RAD controller to determine when the addressed sector
is avai lab Ie.
When the controller is processing a write order, ittransmits
a clo,:;!{ signal and a data signal to the write circuits. The
write circuits use the tv\anchester encoding technique to
store the data on the disc file through the selected read/
write head.
When the controller is processing a read order, the read
extract a data signa I and a clock signa I from the
signal originating at the selected read/write head. The
data 5!Cnol and the clocK signal are transmitted to The
controiier. Additional signals from the selection unit
indicate the status of the device.
circuit~
XDS 901565
Paragraphs 4-1 to 4-4
SECTION IV
PRINCIPLES OF OPERA nON
4-1 SCOPE AND ORGAhlIZA nON OF SECTION
This section describes the operation of all circuits of the
EP PAD file, including power distribution ane! control,
electronic control of mechanical functions, EP RAo controller circuits, and EP RAD selection unit circuits. Descriptions of circuit operation and function are supported
by logic equations, logic diagrams, flow diagrams, timing
diagrams, and schematic diagrams. Individual circuits
re!Clted to the transfer of data through the EP RAO fi Ie are
described in a sequence t!1at proceeds from circuits functiona"y close to the lOP interface to circuits functionally
close to the disc file. Cross-references relate the circuit
bein~1 described to circuiis that provide inputs or accept
outputs.
The phose sequence charts described in paragraph 4-93
indude the controlling equations for changes of state, dot::!
transfers, and timing, with !1rimary emphasis on the lOP
interface. Operations related to a typica I sequence of
orders are described in parograph 4-112. References to
detailed descriptions of inc!ividua! circuits ere included.
Paragraphs 4-112 and 4 -98 may be u-;cd fer a rev iew of
the detai led principles of cj:"eration or as a guide to th~
relation of the del-aiied c;rcuit descriptions to the overa!1
sequence of events during operation.
The description of offline- operation in para~raph 4-83 is
reiated to the effline tests provided in paragraph 8-11.
However, only the manually controlled signais are desctibed because operation~ following manual generatio!'l of
control signa Is are identic(d to re lated on line operation.
operation. During the start sequence, the pneumatic system
re lieves the force hold ing the read/write heads against the
disc fi Ie surfaces. The compressor operates whenever ac
power is applied through the circuit breaker on the motor
control assembly. If tr.e POWER ON-OFF switch is OFF,
re-Iays K12 and K14 are energized and relay K13 is deen:::!rgized, so that the air in the head retracti()rt mechanism
is ',!ented to the atmosphere and the compreS50r maintains
the pressure in the disc fi Ie bulkhead. After the POWER
Ol'! -OFF switch is sel' to ON, K12 and K 14 are deenergizc:J and K13 is energized. This forces air into the head
retrocticn mechanism to reduce the pressure of the read/
wr;te heads against the disc surfaces before the disc file
, m... ;or is started. Low-pressure switch S3 clos('s when pressure reaches 5 psi; high-pressure switch SL closes when
prE':..:.ure reaches 27 p::i. At this time, powe;- isopp!:ed to
th£. disc file motor, and a timing circuit is started. if the
d is:: iii e motor reaches 300 rpm 'tV i th i n 4. 5 seconds, K 13 is
deenergized and K12 and K14 are energized! venting the
hpc:d retraction mechanism to atmospheric preSSL're. The
retld/write heads then ride on a thin film of air. If the
4. '1-second period ends before the disc fi Ie motor reaches
30V rpm, a mechanical brake is opplied, the Jisc file
rr.o!m is stopped, 'and the pneurr,otic system rp.rlJrns to its
initbl state. If the rOWER Ot'-l-OFF switch is set to OFF
du;-ing norma! operati::m, the disc file motor is stopped rmd
thE:; ::>neumatic system returns to its initial state.
4-!' MOTOR CONTROL ASSEMBLY
Circuit e lement5 of the motor control assemL!t ~figure 6-4)
sen!>~ phase connectio:1s of the ac power sour-,e; S?ee0 of
t~E' disc fi Ie motor, pressure, and temperatu";.
The cirof the motor contro I assemb Iy contro I trc compressor,
thE' d1sc file motor, and the mechanical brake of the disc
file and provide voltage for dynamic braking. The circuit
t~l~t includes transistors Q7, Q8, 011, and T2 senses all
tbee phoses of the ac power source and connects relay K4
to ground through 011 if the sou;-ce is improperly wired or
if p0\Ver on any phc:se is lost. The circuit th:::;t includes
Q 1, Q2, 03, Q4., and Q9 senses the speed of the disc
fl'c! motor and provides a signai to other circuits when the
spe~d reaches 300 rpm (nominal). The circuitihat includes
Q5, Q6, and QI0 is a timing circuit that co~mects K4 to
ground 4.5 seconds aftBr c trigger signal is re~cived. The
circuit that includes SCR1, SCR2, and SCR3 provides dc
v\)!toge for dynamic braking. This voltage is applied to
the .:lise fi Ie motor through contacts T1 and L j of K6. Th~
mechanical broke is controlled by +50V power applied
through contacts of re lay K4. Low-piessure switch 53
cleses at 5 psi; high-pressure switch 52 CIa:8S at 27 psi.
o
If the disc fi 10 becomes o-,'erheated (greater than 130 F,
nomina I), the thermostat closes, connecting K4 to ground.
CIJ its
,4-2 ElECTROMECHANIC~~ OPERA nON
The read/write heads of 11.e EP RAO storage U!'lit are contained in a pressurized section of the disc file not normally
serviced in the fiE' Id. Spacing between the read/write
heads during normal oper('l~!on and start sequences is governed by the motor controi assembly and the pneumatic
system. !)uring normal operation, spacing between read/
write heads and a magnetic SUi face of the disc file is maintained by a thin film of air. During a start sequence, the
read/write head~ are held from the surface by a pneumatically-centrol jed head retraction mechanism. The pneumatic system (figure 4-1) is operated through the motor
control assembly.
4-3 PNEUIv\A 1 IC SYSTEM
The pneumatic system of the EP RAD storage unit maintains
the disc fi Ie bu Ikhead at a positive pressure during norma I
4-1
COMPRESSOR
..
ATfAOSPI&RJ:
WATER FILTER
K14
HEAD
RETRACTION
MECHANISM
~CHARCOAL
rr
FILTER
ABSOLUTE
FILTER
NOTES:
1. PATH TO HEAD RETRACTION MECHANISM CLOSED WHEN K12 AND K14 DEENERGIZED
2. PATH TO DISC FILE BULKHEAD CLOSED WHEN K12 AND K14 ENERGIZED
DISC FILE
BULKHEAD
XDS 901565
Circuits of the motor control assembly control the appl ication
of ac power to the disc fi Ie motor, prevent the operation of
the disc file motor if it does not reach 300 r9m within 4.5
seconds after application of power, control the pneumatic
system to prevent damage to the read/write heads or to the
magnetic surfaces, monitor !>peed and temperature during
normal operation, and control the stop sequence. The order
of events during a start sequence is indicated in figure 4-2;
timing diagrams are provided in figure 4-3. The order of
events during a stop seque'1ce is indi cated in figure 4-4.
Paragraphs 4-5 to 4-9
module sense ac outputs of the power distribution panel
(ACSENSE1 and ACSENSE2) and the +25V output of the
PT20 power supply (POS25SENSE). When these signa Is
indicate normal operation, signal AOK enables a gate controlling a one-shot. If these signals indicate abnormal
operation, the one-shot is triggered and remains on for 10
seconds (nominal) after normal operation has resumed. This
operation causes writing to be inhibited, the selection unit
to be disconnected, and any operation in proc(:ss to halt.
Signal AOK controls the PWERMON signal to the controller
(figur~ 6-7).
4-5 POWER DISTRIBUTION
The primary power source is connected to each EP RAD
storage unit. Power can be controlled from the power distribution panel or from a remote location and is provided to
the motor control assembly, the PT20 power supply, the
fans, and the WT29 Power Monitor module. Power from the
PT20 power supply is provided to the EP RAD controller and
to the EP RAD selection unif. (figure 6-2).
The siow ac sensor circuit of the power monitor reads the
average value of the a::: signal but is insensitive t.::> noise
spikes. The fast oc sensor circuit ·')f the power monitor
respcnds within a fraction of a cyc Ie to rapid changes in
tIH:~ ac signa I. The dc sensor is triggered when the dc voltage falls below a preset level. A delay built into the circuit prevents operation during a start sequence. Waveforms
for t:":;: circuit are illustrated in figure 4-5.
4-6 POWER DISTRIBUTION PANEL
4-6 EP RAD CONTROLLER
The power distribution pane! of each EP RAD stora:~ unit
controls the distriLution of ~rimary ac power to components
within the EP RAD storage unit as well as to 01her EP RAD
storage units. (See figure 6-1.) T:1ree-phase 60-Hz power
is always available at TB1 of an EP RAD storage unit. Application of th is ac power ·0 the disc file motor is under
the control of the motor cO:1trol assembly. Application of
ac power to the PT20 powt::.r ~upplYf the fans, and the pOWel
fail-safe circuit is under t:,e control of the REiV\OTE-OrFON switch Sl of the powei distribution pane I.
4-9 SUBCONTROLLER
When 5 i is in the ON p05itio". K 1 is energi zed and oc power
from phase C is arrli-=d through Fl io the pr;mary of Tl, 10
the PT20 power supply, ad to all fans. The vutput of the
secondary of T1 is applied to the power fail-safe circuits.
(See paragraph 4-7.) />.ft~r the +25V power sU,Jpl y of the
PT20 power supply is operating, relay K3 is energized and
a circuit is completed to grc-und through contacts K3-2,
K3-3 r Kl-6, and Kl-3. T~1is circuit controls online/off!ine
operations in the EP RAD cor+roller. (':ee paragraph 4-83. )
When 51 is in the REMOTE position, ap?licationofacpower
is controlled hom rhe computer. When ac power from t~e
remote source appears at thE contacts of J1, t;roe delayrelay K5 is ener'gized through J1 -X, the heating element of
K5, contacts K4-5 and K~ ~-4t resistor Rl, and J 1 -W. After
the contacts of K5 close, rE-lay K4 is energized and latched
and ac power goes from J1-X to J2-X through K4-6 and
K4-5. The output of J2 goes to the nex t EP RAD storage
unit in the EP RAD fi Ie. Ti) is ac power elso goes through
the contacts of S1 to relay !<1, causing the same sequence
of events iniliuted wh~n Sl is in the ON position.
4-7 POWER FAIL-SAFE CIRCUITS
Euch EP RAD selection unit i:lcludes a 'NT29 Power Monitor
module in location 4B. (See figure 6-3.) Circuits of this
Each device controller (DC) communicating wi;·h an lOP
con~loller) inc lL·dE:5 (J subco:)~roller which provides the following circuits:
(as, for example, the EP RAD
o.
Relay logic and switches for placing I:I~ DC online
or ~)ifli ne
b. Loglc elements to determine priority 1.>£ .he DC
c. Cable drivers and cable receivers to (;0:1r.3ct the
eig;,<-bit data path interface
d. Switches for establishing the addre5s of a DC and
for ~)ro'lidir,g a means of comparing the DC ad-Jress genere ted by the 10 P wi th the address of the DC
e. A flip-flop that, when set, indicates that the deVi::-F. is connected for service through the DC
NG: all possible functions of the subcontrolier ore used in
ea.:h DC. Sutcontroller function used by the E? RAD controlier are described in paragraphs 4-10 through 4-19.
The subcontroller consists of the following modules incorporated in the EP RAD controller to interface with the lOP:
Location
Module Type
C23
C24
C26
C27
C28
C29
C30
C31
C32
LT25 Special Purpose Logic Mvdu Ie
LT26 Switch Comparator Module
An? Special Purpose Logic M0dule
LT24 Spec ia I Purpose Logic Moclu Ie
AnO Cable Receiver Module
LT41 Special Purpose Logic Module
An 1 Cable Receiver/Driver Module
LT 43 Special Purpose Logic Modu Ie
A T12 Cable Driver Module
4-3
XDS 901565
START
START 4.5-SECOND TIME DELAY
8Y APPLYING +25V THROUGH
(K7-6 TO K7-n AND 53 !O Q5
I
I
PHASE />..: ENERGIZE K5 THROUGH
(!<2-2 TO K2-31 AND (Kl(}"4 TO
KI(}"5) AND (K7-10 TO K7-9) AND
(K4-14 TO K4-15) TO K_5_-7_ _-",
-~-~
PHASE A:
Kl
ENERGIZE
SI-A TO 51-5
ILAFTER K2 ENERCIZE!.I, +50V
ENERGIZES SOLENOID AND
D~SENGAGES DISC FILE 8RAKE
(K,;-S TO K4-6)
--
YES
II
ENERGIZE 1(4 ..... ND K8 BY
GROUNDiNG ~4-4 THROUGH 010
_____ J__
f
APPLY DI~~: &kAKE BY OPENiNG
+50'1 TO 50LENOID (K4-5 TO
K4-6)
REMOVE P0W::R F~OM DISC
FILE MOTC-, BY OPENING
HEADS RETRACT
ASAiR\
TACHO.METER CIRCUIT (Ql, Q2, Q3'11
Q4, Q9) TRIGGERED. ENERGILf 1<3
BY GROUNDli-lG K3-4 THRC':)CH ·1
04. ~25V LATCHiNG VOL V' GI'
K.1J6)
AP.PLlED THROUGH (KI-5 TO
AND (K7-15 TO K7-16) AND
(K4-12 TO K4-ilj TO 04 (HOLD
TACHOMETER CIRCUIT)
DE ENERGIZE Kl3 BY OPENi.;Z]
(K3-14 TO K3-15)
(K4-14 TO :~{--15), DEENERGIZING
K5
PRESSURE BUILO~~
C
S2
CtO~E~=:=J
901 565A-1. 413
Figure 4-2. Motor Control P,ssemb!y Start Sequence, Flow Diagram
4-4
XDS 901565
,-.
CSt
--
K12, K14
Sl
$1
K2
K2
----1
----..r-L
- '~
Kl
r
K13
K13
r
K3
K3
Kl
S3
_ _~
J
L
S2
CD
53
1--
S2
K7
_ _ _I
K7
K5
_ _ -----1
KS
K4
K4
A. TIME DELAY NOT EXCEEDED
J
J
L
CD
J
n~_.
J
B. TIME DE LAY EXCEEDED
NOTES:
1. START OF 4.5-SECOND TIME DELAY
2. NO TIME SCALE; SEQUENCE OF EVENTS ONLY
~
______________________________
Figure 4-3.
~~
901565A. 4i4
_____________________________________
,.__J
Motor Control Assembly Sfart S~quence, Timing Diagram
4-5
XDS 901565
START
ENERGIZE K4 BY GROUNDING
IT THROUGH THERMOSTAT
LATCH K9 {K9-3 TO K9-2j
DEENERGIZE Kl
APPLY DYNAMIC BRAKING \'OLT-
AGE THROUGH (Tl TO L1) O~ ,,6:
DEENERGIZE K7 BY OPENING
PATH THROUGH (Kl-5 TO Kl-6)
AND (K7-15 TO K7-16) AND
(K8-6 TO K8-5) TO K10-1
ENERGIZE KIO BY APPLYING
+2.5V THROUGH (Kl-5 TO Kl-6)
AND (K8-6 TO K8-7)
DEENERGIZE K5 BY OPENING ~
PA TH THROUGH (K7-9 TO K7 ·10) ,
AND (K4-14 TO K4-15)
PHASE A: ENERGIZE K15
THROUGH (K10-3 TO K10-4) AND
(K2-3 TO K2-2)
DEVELOP 140 VDC FOR
DYNA~iiJ
BRAKING
PHASE A: (KI0-7 TO K10-6)
PHASE 8: (KIO-l0 TO K10-9)
PHASE C: (K10-13 TO K10-12)
NERG!ZE K4 AND K8 BY ,- ---,
ROUND INC THEM THROU(;o1
~ Q~
APPLY DISC FILE BRAKFB~'
OPENING (K4-6 TO K4-f'l"
REMOVl:--.iG +50V FROM
SOLEN0ID
--------~--------~
DEE~ERG!ZE K2,
OPENIl'-'[]''';'
LATCH n:::OUGH (K8-IS 1")
K8-14} AND {K2-5 TO K2-6~
DEENERGIZE K9 BY O?ENit..JG
PATH THROUGH (K?-2 TO r-:9-3)
AND (KI0-3 TO K10-4) AND
(K2·-3 TO K2-2)
PHASE A: ENERGIZE K9 THROUGH
PATH (K2-2 TO K2-3) AND(KI0-4
TO KI0-3 AND (KI5-2 TO KI5-1)
DEENERG!ZE K6 BY OPENING
(K9-6 TO K9-5)
~OVE AC
POWER FROM
L~RYOFT1
'1
±25V OUTPUT OF POWER SUPPLY
FALLS, CAUSING K4, K8, Kl 0, AND
K15 TO BE DEENERGIZED
901565/1.• 415
Figure 4-4. Motor Control Assembly Stop Sequence, FloVi Diagram
4-6
A. RAPID AC LINE CHANGE
B. GRADUAL AC LINE CHANGE
TIME AT WHICH
LINE DROPS
BELOW SLOW
SENSOR
THRF.SHOLD
~~~~~
TIME AT WHICH
LINE RETURNS
---,
r-ABOVE SLOW
"SENSOR
I I
THRESHOLD
~
x
o
.
+25V
t
I
POS25SENSEY--..··----- ---·~f
I
/ .. ---------~.
1
~
AOK
<
ct:
Q
+ 8V
---
I
~1~r----J~I~T2
"
I
I
I
r
--11--___
T3-I-~T4--jr I-----h
I
I
TIME AT WHICH
+25V LEVEL DROPS
BELOW SENSOR
THRESHOLD
~f=r;
3
NOTES:
1. Tl = T4
=300 :~OO MS
= TURN ON DELAY
2. T2 = 1 MS MAX :-: FAST AC SENSOR AND DC SENSOR RESPONSE
3. T3 = 5 ± 1 MS == SLOW AC SENSOR RESPONSE
-0
~
01
0-
I~
t l~~______________________________________________________________~
Vl
...0
~
t!'1
o·
ttl
XDS 901565
Paragraphs 4-10 to 4-12
4-10 Function Strobe and Function Indicators
4-11
The subcontroller con respond to a function strobe signal
/FS/ accornpanied by one of the following function indicator signa Is:
The lOP data line signals consist of DAOR through DA7R,
which may contain en address or terminal order information.
(During execution of orders, these lines transmit data b),tes. )
Function Indicator
Function
AlaR
Acknowledge interrupt call
ASCR
Acknowledge service call
HIOR
Halt input/output
StOR
StOtt input/output
TDVR
Test device
liaR
Test input/output
lOP Data Line Signals
Signals DAOR throughDA3R ore compared with the settings
of the switches on the LT26 Switch Compmator module to
generate device controller addressed signal DCA.
DCA
=
N(DA3R NSWA3 + NDA3R SWA3
+ NDA2R SWA2 + DA2R NSWA2
+ DA1R NSWAl + NDAIR SWAl
+ DAOR NSWAO + NDAOR SWAO)
"'he HIO, SIO, TDV, and TIO functions are always addressed to a specific DC, and nnly the subcontroller associated with the addressed DC can respond. The Ala and
,ASC functions (lie nOI' addressE'd to a specific DC, and each
i, subcontroller associated with an iO P receives the function
strobe and function indicator in a priority sequence established by cabie comlcctions. If a ::ubcontroller in a DC
does not respond, the AIOR or ;\SCR function indicator
enable!> the subcontroller of the next DC in the priority
sequenre to respo~d. If the suL:ontroller does respond, it
a(,.~nov/lcdges the function strc''''~ cnd generates function
respons~ signals, condi:'ion codE' signals, and other signals
related to the function.
The tiIOR, SIOR, TDVR, and nOR function indicator signals are generat~d when the C!'lj processes an instruction.
The AIOR function indicator slsnal is generated in response
to an interrupt call by a DC (as, for example, the ,EP RAD
.ntrol!er).
•
ICD
LIl
LIL
NAIOR INC elL (True when CIl set)
+ AIOR INI i.iL NRSTR (Latched until
AIOR false)
The condition:; for which flip-fiop CIl is set are described
in paragraph 4-34.
The ASC function indicator signa i is generated in response
to a servir.e call by a DC.
seD
LSL
LSl
NASCR INC
seN
(True when SCN set)
+ ASCRINI LSL NRSTR SCN (Latched
, ~
until ASCR
false)
The conditions for which flip-flop SCN is set are described
e\Qragraph 4-32.
4-8
If any pair of corresponding bit~ of the DAnR inputs and the
SWAn inputs (where n represents any integ<::'r frem 0 to 3)
are di~ferent, signa I DCA is fa ISei therefore, signa I DCA
is true when the JOP data line code is identical to the address code set in the switches, indicating that the device
controller is addressed.
Signals DA5R through DA7R contain the devicE., oddre~s
code c!"d control signals SUOD through SU2D.
SUOD
DA5R IOP-I-
SlJ1D
DA6R lOP +
Sl:2L'
DA7R lOP +
For tcrl""1:nai orders, signals DAOR through DA3R it:dicate
interrut-'t, count done, command chaining, or IOP ho It, as
descric.;d in detai I in paragraph 4-34.
4-12 Priority Signals
Signole; HPI, HPS, LIL, LSL, AVI, and AVO contr,.)l pric;rity
when ti,e EP RAD control Ie. is online. The lOP ~r'i1erates
an AV1;( s:gnal that is always true. This si:-Jnal goes to the
highest !Jriority device con~rolier at all times. Whe" the
lOP generates a true function strobe signal (FSR)! ~c,:h
DC, bes.lnning with the highest priority DC, responrl'i to
the AVIK signa I in priority seC!uence. If a DC dof'~ ~o~
genera~8 a function strobe acknowlejge signal, the DC
passes j he: A VIR si gna I on to the next DC in sequence in
the form of a true AVOD signal.
In the EP RAD controller, a true J.VOD signal is generated
in one ot three WO}'S.
AVCD
= AVIR FSR AIOR NAIOM (AlO function)
+ A VIR FSR ASCR NASCA.'I (ASC function)
+ AVIR FSR NDCA TTSH (TDV, TIO,
SIO, or HIO
function)
TTSH = TDVR + nOR + SIOR + HIOR
For cn AIOR function indicator, a tple AVOD signal is
generated if eifher interrupt flip-flop ell is reset or if
high priority interrupt bus H PI is at the true leve I.
XDS 901565
AVIR FSR AIOR NAIOM + •••
AVOD
AIOM
NHPIL LIL + LIH
HPIL
NAIOR HPiR + AIOR HPIL
LIl
NAIOR INC CIl
+ AIOR INI LIl NRSTR
LIH
NAIOR INC ell GND} .
+ AIOR !NI NRSTR LIH Always false
Paragraphs 4-13 to 4-15
signals, and service cycle identification signa Is. These
signals are used by the 10 P to determine the type ot response required. Paragraphs 4-14 through 4-19 group these
signals for each type of function indicator.
4-14 TDV FUNCTION INDICATOR. For a TDV function
indicator, function response signals FROD, FR2D, and FR3D
contain information, and other function response signals
are always false.
FROD= (TDVR DCA FSD) RER
+ •.. (True if rate error detected)
For a service call function indicator (ASCR), a true AVOD
signal is generated if service call fiip-flop SCN is in the
reset state or if high priority service signal HPSR is at the
true level.
FR2D
FR3D
AVOD
.A. VIR FSR ASCR NASCM + •••
ASCM
NHPSL LSL + LSH
HPSl
NASC~
lSL
NASCR INC SeN
+ ASCR 1N! LSL NRSTR seN
lSH
NAseR INC SCN GND
JAIWCYS
+ ASCR INI LSH NRSTR seN false
(TDVR DCA FSD) WPV
+ •.• (True if write protection violation)
The conditions for which f!ip-flops RER, SUN, and WPV
aa'" ~d are described in paragraph 4-72.
H PSR + ASCR H PSL
Condition code !-ignals {lORD, DORD) are cont.·olled by
error fli!J-flops RER, SU N, and WPV and by device operation",1 flip-flop OPER.
IORDEN
NIORDENl + •••
NIORDENl
TDVU NFAULT + •••
NFAULT
NRER NSUN NWPv
A VIR FSR NDCA TTSH + •••
TTSH
TDVR + nOR + SIOR + H10R
DCA
Device control !er addresseo
DORD
4-i3 Subcontroller
Respor.s~
When the subcontroller doee: not generate Q true AVOD
signal, it generates a true fuilction strobe acki'lOwledge
signal, regardless of the typ:; of func~ on indicator. The
conditions which control P:i:-SL are described in paragraphs
4-20 througn 4-29.
FSlD
BSYC
PHFSL IORDEN
+ ••• (TruE: if no c,rors have
occurred)
lORD
For all other function indir:ators (TDVR, TIOR, SIOR, cr
HIOR), a true AVOD signcl is generated if the device controller is not addressed~
AVOD
(TDVR DCA FSD) SUN
+ .... {True if sector unavaiiabL."?j
PHF~l-l TTSH DCA
(TDVR, TIOR, SIOR, HIOR)
+ PHFSL-l BSYC (ASCR or AIOR)
AVIR FSR ASCR ASCf..A (ASCR)
DORDEN PHFSl
+ .•• (Tru~ if devit.:;~ "pE::rotiona!)
OPER + •••
DORDEN
Th~
conditions for which flip-flop OPER is set are C:escribed
ir. r.-oragraph 4-23.
4-15 TIO FUNCTIOI'J INDICATOR. For a TI0 function
in:licator, FROD through FR6D contain information as listed
in taole 4-1. Function response signal FR7D isalwaysfalse.
Th .... function rt."!sponse signal equations ore:
FROD
BFSD TSH CIl + ....
+ AVIR AlaR ,.,\IOM PHFSL-l (AIOR)
BFSD
FSLD
TSH
DCA (TIOR + HIOR + SIOR)
PHFSL-l = PHFS:"
After generating the function strobe acknowledge signal,
the subconlroller generates additional signals that depend
on the function indicator signal. ThE: signals include function response signals, condition cooe signals, request strobe
FR1D
DVBSY
BFSD TSH DYBSY + •••
DCB DVSEl
4-9
XDS 901565
Paragraphs 4-16 to 4-17
Table 4-1. Information in Function Response Signals for TIO, HIO, or SIO Commands
FUNCTION RESPONSE SIGNAL*
INFORMA nON
1
FROD FR1D FR2D FR3D FR4D FR5D FR6D FR7D
Interrupt pending
\1.
X
X
X
X
X
X
0
Device automatic
X
X
X
1
X
X
X
0
Unusual end
X
X
X
X
1
X
X
0
EP RAD ready
X
0
0
X
X
X
X
0
EP RAD busy
X
1
1
X
X
X
X
0
EP,RAD not operational
X
0
1
X
X
X
X
0
Controller ready
X
X
X
X
X
0
0
0
X
X
X
X
X
1
1'
0
Controller busy
I
.-
*An X indicates that the si9:1(:1 1 is not related to that information
'r
BFSD l$H S"fSH02 +
FR2D
(.
lORD
IORDEN PHFSL + •••
[)VBSY + NOPER
JORDEN
NIORDENl + •..
FR3D
BFSD TSH DVTR +
NIORDENl
NDVBSY HIOU + ••.
FR4D
BFSD TSH UNE +
. FRSD
BFSD TSH DC;) +
FR6D
BFSD TSH [1«':3 +
STSH02
FRlD
.- BFSD TSH G h!e
+
DOP'I)
D0RDEN
=
OPER + •••
~I 'NCIlON INDICAlOR. For an SIO f~ .. r:tion
indicator.- function response signals FROD I-hrough FR7D
contain jnformution as listed in tabie 4-1. FunctioL :-esponse signal FR7D is alw:lys false. The equations fOi function response signals are the same as those for the TiOfunction ind •.::ct')r.
4-17 S!O
...
adot%rder signal equation, or.'
lORD
DORDEN PHFSl + •.•
PHFSL IORDEN + •••
The condiiion code signals (lORD, DORD) are:
IORDEN
NIORCENl + .••
NIORDEN1
TIOU 0 PtR NCIl NDeS + •••
lORD
DORD
DORDEN
OPER
DCBSET + •••
~CBSET
OPER SIOPOSS PHFSl
S!GPOSS
NCIl t..JDCB SIOU
t .•••
The condition code signals (lORD, DORD) are controlled
by device busy signal DVBSY and device"operational flip-
4-10
JORDEN
DORDEN r'HFSl + •••
4-16 HIO FUNCTION INDICATOR. For an HIO function
indicator, function response signa Is FROD through FR6D
contain information as listed in table 4-1. Function
response signa I FRlD is a lways fa Ise. The eqlJations for
function response signa Is are the s(.me as those for the TIO
function indicator.
.OPER.
PHFSL IORDEN + ••.
DORlJ
DORDEN
PHFSl DORDEN +
OPER + •.•
Flip-flop Cll is the interrupt pending flip-flop, which is
set by a terminal order as described in paragraph 4-34.
Flip-fiop DCB is the device busy flip-flop; which is set
when an SiO is accepted by the device controller. This
flip-flop prevents eny nelfv SIO from being accepted unti I
XDS 901565
processing is completed. The possible condition codes and
their meaning are:
lORD
DORD
o
o
A condition code (lORD, DORD) of (0, 1) indicates a fault
condition (RER, SUN, or WPV) in the controller responding
to the AlO command.
Meaning
Device not operational
o
Paragraphs 4-18 to 4-19
Interrupt pending, device busy,.
or cor.troller busy
In addition to function response signals and condition code
signcds, status signals are generated and transmitted through
signals /DAO/, /DA2/, and /DA3/.
SIO accepted
4-18 Ala FUNCTION INPICATOR. For an AIO function
indicator, the EP RAD conirnller places its address on function response Pnes FROD through FR3D and places the unit
address stored in the unit register (UO through U2) 011 function response lines FR5D through FR7D. Function response
signal FR4D is alwoys false.
000 + •.•
/DAO/
000
OXAIOST RER + ••.
OXAIOST
AlOe FSU
002 +
/DA2/
...
OXAIOST SUN + ..•
002
003 + •••
/DA3/The logic equations for the function response signals are:
OXAIOST WPV +
003
fROD
BSYC
AIOM AIOR AVIR PHFSl-l + •••
fR1D
BSYC S\VA 1 +
FR2D
BSYC SWA2 +
FR3D
BSYC
fR4D
BSYC (; ND +
FR5D
BSYC UO +
FR6D
BSYC Ul +
FR7D
BSYC 1J2 +
4-19 ASC FUNCTION INDICATOR. The AS( flJnction
indi :::;tor is a response of the lOP to IJ servicp: call from the
EP RAD controller end can occur only after an SIO command
has been accepted, causing service call flip-flop SCN to
be di.ect set and servit:e call signa: SeD to b.~ raised.
SCD
~·Np.3
lSl
+
lSl
The condition code (lORD .. DORD) is (1, 1) only for the
subcontroller having the highest priority and a pending interrupt (Cll set).
lORD
PHFSl JORDEN + •••
10RDEN
N!ORDEN1 + .••
NIORDENl
AIOC NFAUlT + •••
NFAUlT
NRER NSUN NWPV
AIOC
AIOM AIOR AVIR
+ AIOC PHFSL-l INI NRSTR
DORD
DORDEN
...
BSYC S'dAO + •••
;":ASCR INC SeN + .••
Service calls are a part of the execution of thp !.t?ek order,
seme order, write order, read order, and checkwrite order.
For an ASC function indicator, tne function rf",;pome signal contain!' the some address information as dp.scribed for
an P. 10 function indicl"ltor (pamgraph 4-18), but ~h~ BSYC
sigr..:d is controlled by different signa Is.
nsyc
= ASCM ASCR A VIR FSR
+
The ASC function indicator causes service connec.t flip-flop
FSC 1'0 be set.
S/FSC
ASCB
C/Fse
ASCB
(deiayed NFSC) ASCM AS·':R AVIR FSR
NFSCFSR + ••.
Service connect flip-flop FSC is normally set during the
order out service cycle that starts an input/output sequence
and is not reset untj I the lOP generates end service signul ESR.
DORDEN PHFSl + •••
R/FSC
FSC ESR
AlOC + •••
C/FSC
FSC RSD + •••
4-11
XDS 901565
the timing of signals controlling typica I input/ouTput operations.
Paragraphs 4-21 to 4-23
NDCB-l
E/PHRSA
NDCBIOP + •••
NDCB-l
4-21 TCL Delay line (See figure 4-7)
E/PHRS
NDCB-1
E/PHTO
NDCB-l
The TCl delay line, v/hich provides timing signats for
changes of phase, is controlled by lOP signals and by signals originating in the controller.
For online operations, signal CYCLE/C remoins true after
each cycle of the TeL delay line, because CYCSET latches
when TC5300 is true.
CYCLE/C
CYCSET
=
MA.NRST -1
NTCLOSO (TCS300 + CYCSET + .•. )
After a 50-03 delay, sigr.cl CYCSET goes false as TCL050
goes true. However, the c.:~lay line pu Ise is stretched to
80 ns by a gaie which is held true whi Ie signa I NTCS080
is true.
1CSOOO-2 NiCS080 + •••
n~e Tel deiay lin~ providt-'~ an 80-nspulse at delays of O{
50, 801' 100, 180, and 300 ;1S. When the 3CJ-ns signa I is
twe, CYCSET becomes true and is latched as before.
MANR5T -1
E/NPHFS
CyeSET 10 P + •••
Signal CYCLE/C is an inpl;t to start gates of the TCldelay
line. Other signal inputs :0 these gates come true for various conditions of the pho~e flip-flop:; arad subcontroller
signals, as described in parf'lgraphs 4-22 through 4-29.
When all inputs to one of :;,e start gates are true, signal
DCl is true und the TCl delay line is started.
DC l
Areset signal received from the computer through the lOP
direct resets fl~p-fl TC1l80
-~--- TCll 00
_ _ _ _
0
TCloao
DCLSTARTl
~-l
V
TCl1('()-.- 47 5B
29
4Q,.~~1
TCL050-':"~.
~..!::.25~_ _
~----~.
TC5000-1
TCLOOO--l/'
CYCSET
CYClE/C
DCl
TC50oo-1 ~
TC5000-2~
I
TClOSO
NTC5080 ---~.--.-l
TC5300
40
80
280
r
---,320
360
400
901565A.402
••
an d Lc.gic Diagram
.
Figure 4-7. Tel DeJay L'Ine, Tlmlrg
4-14
XDS 901565
FROM SHEET 7
C(
~J
START
- - ~_---_-
...1-..---.
WAIT FOR FUNCTION STROBE
ANDFUNCTIONINDKATOR
START Tel DELAY LINE
[_-_-_-_-_R-E~S_E-T~-O--P-E~R~~~~~-·---'
SET DCB
I
START TCl DELAY LINE
,
[
SAMPLE DVTR
]
TO SHEET 2
---~
l-..jABlE FUNCTION RESPONSE
IGNALS (FROD- FR7D) AND
ONDITlON CODE SIGNALS
ORD, lORD) AND FSLD
r
~CL DELAY LINE
-
J
IL.....--_.
NOTES:
1. NO ERRORS OCCUR DURING OPERATIOi--l
2.
COUNT DOhiE TERMINAL Of"{DER ENDS
EXECUTION OF READ ORDER, WRiTE ORDER!
OR CHECKWRlTE ORDER, At'\lD CAUSES
TRANSFER TO ORDER IN SERVICE CYCLE
3. t;ND SERVICE SIGNAL RECEIVED DUR!t~C
GKDER IN SERVICE CYCLE
4. CONTROLLER OPERATING IN EXTENDED
PERFORMANCE MODE (EXT TRUE)
901565A.418/1
L
Figure 4-8.
Simplified Phase Sequence, Flow Diagram (Sheet 1 of 7)
4-15
XDS 901565
t.
MARK seN: RAISE seD
r - - - S E T DATA
I
t-----T FSLJ
L---=-_~~T IN_ ---~-
L---._
TO SHEET 4
-----[RSA
l
REGt~~~O-ORD4)1
lOAD ORDER--(DA3R-DA7R)
I
tl
__
SET DATA
SET~ __~_~_
I
I
-.-----r
*
~
C
RAISE RSD
I
~
}-~
-_JI
E
TO SHEET \.;
RS
1
.
- - - - I --l
TO
NO
[
SET DATA
cb
TO SHE[T 3
-
ER:O~~
--r
L_
SHIN
TO
h
SHEET7~
.------=-~
CV
SETDA1A
~
TO SHEET 5
901565A.418/2
Figure 4-8.
4· 16
!.""
d Phase Sequence, Flow Diagram
.
'Sheet
2 of 7)
Simplltl€
\
XDS 901565
FROM SHEET 2
DATA OUT
SERVICE
CYCLE
MAR.K seN :RAISE seD
YES
RAISE RSD
RESET seN
NO
[~A-T-----
ERROR
i
I
L.
(DACR-DA7R) - - - (100-107)
---.I
' - - -_ _ _ _ _ _ ,.c •.
,....--...I-N-C-RE-.Iv-~E-N-IT-B.J..YT--E-C-O-U-N-T-ER--":II
LOAD I-REGISTER
-I
r
I
---r-
RESET DA_T_A_ _, ]
SET IN
I
I
I
,I
ev
TO SHEET 7
LOAD J-REGISTER
~tO(}"I07)-.--(JOO-J07~
NO
901565A.41aj3
Figure 4-8.
Simplified Phase Sequence, Flow Diagram (Sheet 3 of 7)
4-17
XDS 901565
FROM SHEET 2 . C
DATA IN
SERVICE
CYCLE
LOAD a-REGISTER
(KOO-KOl) - - - (OOO-OOl)
[Fs.-F~T - r------_-----1-_ __
MARK seN: RAISE SCD
RAISE RSD
RESET SCN
NO
[-;;-r -,. -----_L
~_
-_.----1
RAISE RSD
LOAD C-REGISTER (BYTE 1)
I
(TRPR) - - - (000)
(TOO- T(6)----(OCl-007)
[~A-r----
3:_.
IINCRE~:~T BYTE COUNTfR
It
-----E.l
I
.
II
I
TO
.--J
NO
L
RESETDATA
TO SHEET 7
NO
ERROR
LOAD K-REGISTER
{T07- T1 O} - - - (KO()'· K03)
(SOO-S03) - - (K04- K07)
(ANOR-AN3R)--(K04- K07)
901565A.418/4
Figure 4-8.
4-W
Simplified Phase Sequence, Flow Diagram (Sheet 4 of 7)
XDS 901565
D
FROM SHEET 2
DATA OUT
SERVICE
CYCl~
..L _ _ _ ._ _
r-------~-------___.- - TF~ ;z]
M.A.RK SCN: RAISE SCD
-----~----~---I~~J
r
_
RAISE RSD
r--------~((t,
~ - - - - ~-T -~<:-l
L~
It OAD I-REGISTER
L_~DAOR-DA7R)-- (100-107)
------T~R~]
!lOAD J-REGISTER
L~?-I07)---( JOO- J07)
RAISE RSD
[
...
_---,---
i~o
r--
J
I
I
NO
_ _ -I- - - - - - - - - D o < "
RESET DATA
SET IN
]
~·--------~~F---TO--S-H-EET7
901 565A. 418/5
Figure 4-8.
Simplified Phase Sequencer Flow Diagram (Sheet 5 of 7)
4-19
XDS 901565
I
fROM SHEET 2
DATA IN
SERVICE
CYCLE
___-----L----------= -1F~~l
MARK SCN: RAISE SCD
,...--__---'--_-_-_-_"-l-;S~J
RESET seN
RAISE RSD
r------"----------_-
-1" -;5-1
LOAD O-REGISTER
(KOO- K07) - - - (000-007)
------r--]
RSA
'----
DATA TO lOP
-- -- -1 a'-R;-]
I~D
O-REGISTER
~- K07)--- (000-007)
RAISE RSD
NO
R_E,SET DATA
L . . -_ _ _
YES_ _
' __ _
l __
TO ]
~
~HEET7
901 565 A. 418/6
Figure 4-8.
4-20
Simplified Phase Sequence, Flow Diaglorn (Sheet 6 of 1)
XDS 901565
FROM
ORDER IN
SERVICE
CYCLE
L- - -
SHEETS 2,3,4;5 AND 6
------
r-----.l.....-----~---~--__.-- -[ FSL
J
RESET SCN
LOAD O-REGISTE!(
BITS!
0, 1, 3, 4 (ORDER CO~~
I
-= ---1-;;; J
r----
ORDER CODE
ro~
I
__--"------ - - --1-R-; I
RAISERSD
~
RE_S....,ET_F~S_C ~
"---_ _ _
------TroJ
~-------"-RE-S-E~T-D-C-B ~
I"
RESET IN
901565A.418/7
Figure 4-8.
Simplified Phose Sequence, Flow Diagram (Sheet 7 of 7)
4-21
XDS 901565
.graph 4-24
Before PHFSZ is reset, OPER samples device test signal
DVTR.
SlOPER
DVTR OPERSET
OPERSET
~fter
DCBRST·
R/DeB
NTCS080
C/OPER
t
TTSHU PHFSZ
The phase control circuits wait for an acknowledgement of
a service call. Flip-flop DCB can be reset only during
phase TO of an order in service cycle (except for manual
reset).
a 10O-ns delay, PHFSZ is reset and PHFSL is set.
DeBRST
DCBRSTl + ...
DeBRSTl
DCBRSTEN ORDIN PHTO
R/PHFSZ DCBRSTEN
S/pHFSL
While PHFSL is set, function response signals and condition
code signals are enabled in the subcontrollerand transmitted
to the lOP as described in para~raphs 4-13 through 4-19.
The TeL delay line is started as fl'"ction strobe signal FSU
.
' es false.
CYCLE/C DCLSTART3 + •••
DCL
•
=
NCCH + ES + UNE
PHFSZ
PHFSL NFSU + ...
DCLSTART3
After a 10C>-ns delay, NPHFS and PIiFSl are reset. (Scrv'ice connect flip-flop FSC isset only after an SIO command
is accepted. )
During phase TO, DCB is reset if an end service signal is
received (ES), if an unusual end occur~ (UNE), or if command Cha;f)lhg is not ordered (NCCH). Therefore, once en
SIO has been accepted and DCBhas been set, an I/o operation tak~s place .
4-24 QRQER OUT SEQUENCE. An order out service cycle
immediately follows acceptance of an SIO command from
the lOP. When function strobe FSR coincides with ~n acknowledge service call addressed to the EP RAD controller
(ASCM ASCR), the Tel deiay I ine is started.
CYClE/C DCLSTARTl +
DCl
R/PHFSL
R/NPHFS
PHFSET
NFSCU PHFSL +
FSCU
lOP FSC + ..•
For all lOP commands but an accepted SIO, the phase flipflops wait for a new cC'rnmand. (f an SIO is accepted,
device c0ntrollerbusyflip-flop DCBisset during phaseFSL.
S/DCB
OPER PHJ-'Sl SIOPOSS
SIOPOSS
NCIl NDCS SIOU
NTCS080
An SIO is accepted if thf' controller is not busy with a previous I/o operation (NDCB), no il"terrupt is pending (Nell),
and the device is operable (OPER). If DCB is set, service
call flip-flop SeN is direct set after a return to phase FS,
and the service call line is raised. (See paragraph 4-32.)
M/SCN
DCB PHFS N(NSCNMEN)
N(NSCNMEN)
(ND/\TA SCNMEN2
+ ..• ) NUNE
nsyCU
BSYC lOP + •.•
3SYC
ASCM ASCR AViR FSR
Phases F', FSZ, and FSL 0:"-; control~ed by the san,: equations de;cllbed in paragraph 4-23. However, servk:e connect flip ..tlop FSC is set during phase FSL as the function
s trobe goc~ ta Ise.
NRWE (NWCHW + ... )
S/FSL
ASCB
C/f~C
LSL
NASeR INC SCN + ••.
ASCB
(NFSC delayed) ASCM ASCR AVIR FSR
NFSC FSR + •••
Therefore, after a 100 ns delay, PHFSl is reset, PHRSA is
set, anrt reCjuest strobe signal RSD is raised.
R;r,~fSl
S/PHRSA
PHRSASET FSCU
FSCli
FSC lOP +
eHRSASET
PHFSL NIN + •.•
RSD
FSC NRSAR (FSCU RSD
+ RSET NPHRSA + ... )
lSL
SCD
4-22
CYCLE/C SCNMEN
SCNMEN
SCNMEN2
PHFS FS U BSYCU + ••.
DCBSET
DCBSET
C/DCB
OCLSTARTl
PHFSET
RSET
PHFSL NIN
XDS 901565
Paragraph 4-25
Service connect flip-flop FSC remains in the set state until
end service signal ES is true. Signal ES, which is generated by the lOP, causes a reset as req\Jest strobe signal RSD
goes false in response to a true request strobe acknowledge
signal RSAR.
R/FSC
ESR FSC
C/FSC
FSC RSD + •..
FSC NRSAR (FSCU RSD + ..• )
FSCU
FSC lOP + .•.
When the lOP acknowledges the request strobe, signal RSAR
is true, signal RSD goes false, and the TCl delay line is
started.
DCl = CYClE/C PHRSA RSAU + ...
During phase RSA of an order out service cycle, the ordE:r
code is stored in the order register as described in paragraph
4-31. After a 100-ns delay, PHRSA is reset and PHRS is
set.
R/pHRSA
PHRSA + ...
Request strobe line RSD is
RSD
=
:-aj:;~d
when phase RS is enteled.
FSC NRSAR(FSCU RSD
+ PHRS TCSOOO-2 + .•. )
The TCl deJay line is started ofter request strobe acknowledge signal RSAU is false. (Signal NDATA is true because
an order out service cycle h in process. )
CYC:'E/C DClSTART3 +
DCl
DClSTART3
PHFSET
PHFSET = PHTO +
Table 4-2.
Order Signals
Seek
SIGNALS
~
AlwaysTrue t TrueWhen t~PHRSAOO
r
SEEK
X XXll
SEKSEND
Sense:
X 0100
SENSE
SEKSEND
Read
X XX10
READ
RCHW, WRCH
Write
X XOOl
WRITE
WCHW, WRCH
CODE*
ORDER
I
I
i
I
ChecKwrite X X10l
CHWR
RCHW, WCiiW, WRCH
r---'
,
--1-*OrC:er register bits 0, 1, 2, 3, 4; lOP data \i;"le bit~ 3, 4,
5, 0, 7
FSCU PHR3ET
PHRSET
R/NPHFS
Subsequer.t operations depend upon the order code stored.
(See table 4-2 for order codes. )
RSD
S/PHRS
R/PHTO
tExc6pt during order register load, 'Nhen all sigrals are
false, and after which one signal becomes ta'ue
-- --------------------_._._-4-25 SEEK ORDER SEQUENCE. If a seek orGU code is
stored during the order out service cycle, the (iJp.T A, IN)
flip -flops request a data out service cycle (1, 0) as descriL(.d in paragraph 4-30. While signal PHF~ ;$ true, a
servi.,:e cycle is requested by setting SCN. Tn'; TCl de lay
line .s ~,tarted when the function strobe signal ,"lOa The acknov:iedge service call signal are re~eived.
bit/seN
N(NSCNMEN)
PftRS NDATA NRSAU +
After a 100-"'Is delay, phase TO js entered, and the TCl
delay line is stadec.' when the request strobe is acknowledged.
C,(ClE/C PHFS DC5
N(NSCNMEN)
DCl
NCDN DATAOUT SCR + •..
CYCLE/C DCLS1ARTl ;. ••.
DClSTARTl
PHFS FSU BSYCU +
'0'
R/PHI\S
S/PHTO
PHRS ED
DCl
CYClE/C DCLSTARTl + ...
DCLSTARTl
PHTO RSAU + ...
After a 100-ns de lay! phase FS is entered.
(Flip-flop SCR is set during the order out service cycle.)
Phase:; FS, FSZ, and FSL are controlled by the same equatio;1s described in paragraph 4-23. However, at the end
of pl.jose FSL, PHRSA is set, the request strobe s;gna I RSD
is raised, and the byte counter is decremented. (See paragraph 4-33 for a description of the byte counter.)
4-23
XDS 901565
Paragraph 4-26
= EDISETl
EDI
R/PHFSl
PHRSASET FSCU
S/PHRSA
EDISETl
PHRSASET
PHFSl NIN + •..
FSCU
lOP FSC +
FSC NRSAR (FSCU RSD
+ PHRSA RSET + ... )
RSD
= SEEK
NPHRSA + FSCU EDI + ..•
BKZW + ...
Thus the flip-flops cycle between phase RSA and phase RS
untii the end data signal enables transfer to phase TO. The
TCl delay line may be started in either of two ways in phase
TO.
.
DCl
CYClE/C DClSTARTl
+ CYClE/C DClSTART2 NRSAU
+ ...
RSET
PHFSl NIN
DClSTARTl
PHTO RSAU +
DCLSTART2
PHTO ES +
PHRSA SEKSEND TC5000-3 + ...
NBKCK
SEEK r-JPHRSAOO + ...
SEKSEND
When the request strobe is ackno ...... ledged, the TCl delay
.'"Ie is started and 10 P data is stored in the I-register.
DCl
CYClE/r.: PHRSA RSAU
lOP RSAR + ...
RSAU
IXD
PHRSADC TCSOOO-3
PHRSADO
Therefore, if the lOP has generated an end service signal,
the Tel delay line is started after phase TO is entpredwithout waiting foracknowledgementofthe requeststrohe raised
at the start of phase RS. Otherwise, the TCl delay line is
not started until RSAR is true. In either case, phase FS is
entered from phase TO. After 100 ns, the (DATA, !N)
flip-flops are placed in the (0, 1) state to reque:;t an a.-del'
in service cye l e, as described in paragraph 4-30.
R/PHTO
R/NPHFS
PHRSA DATAOUT
PHFSET
~eset
After a 100-ns de lay, PHRSA h
SjPHRS
and PHRS is set.
FSCU PHR<;;ET
PHRSA + .. '
Once PHRS is set, the TCl del"y line is started when RSAR
is false and RSD IS raised once more.
DClSTART2
PHRS
RSD
S~K5END
+ .•.
FSC i'ID.SAR (FSCU RSD
+ PHRS TC5000-2 + ... )
Transfer from phase RS is to phase RSA or to phase TO, depending upon the end data signed. (See figure 4-8. )
PHRSNED
PHRS
N~D
PHRS ED
r
PHFS FSU BSYCU + ••.
Phase FS, FSZ, and FSL are controlled by the sarr.e equations described in paragraph 4-23. Howev~r, at the end of
phase F~L, PHRS is set and the first byte of sense dt"1ta is
stored i,". the 0 -register.
S/PHRS
Signal ED comes true after the second byte has been cccepted from the lOP, as indicated by the byte counter.
(See paragraph 4-35. )
4-24
DClSTARTl
PHRSNED +
-
NCDN SEN NTSE ;CYCLE/C DClST ART i
Del
PHRSASET
S/PHTO
o~
N(NSCNMEN)
R/PHFSl
o
PHFS DCB N(NSCNlv'\EN)
M/SCN
PH RSA:~- i FSCU
S/PHRSA
PI-fTO +
4-26 S':NSE ORDER SEQUENCE. If a sense order code is
stored jJri ng the order out service cye Ie, the (DATA, IN)
flip-tiops request a data in service cycle (1, 1) as described
in paragraph 4-30. Whi Ie signa I PHFS is true, 0 service
cycle is requested by s-=tting SCN. The TCl dele:y line is
started '.vhen a function strobe sOignal is received.
CYCLE iC DClSTART2 NRSAU + ..•
DCl
PHFSET
FSCU PHRSET
FSCU
FSC lOP + ••.
PHRSET.
PHFSl IN + •••
OXSENSEl
OXKEN
SENSE OXKEN BKZZ
DATAIN NED PHRS
XDS 901565
After PHRS is set, the TCl delay line is started and request
strobe signal RSD is raised.
DCl
Puragraph 4-27
EDI
EDISETl = SENSE BKWZ + •••
CYC lE/C DC lS TART2 N RSA U
+ •..
DClSTART2
PHRS SEKSEND + .•.
SEKSEND
SENSE NPHRSAOO +
PHRSAOO
PHRSA ORDOUT
EDlSETl TSCOOO-2
+ EDI FSCU + •••
After ED is true, PHTO is set, as described in paragraph
4-25. The (DATA, IN) fI ip-flops are set to (0, 1) to request an order in service cycle, and phase FS is entered.
R/pHTO
R/NPHFS
RSD
FSC NRSAR (FSCU RSD
... PHRS TC5000-2 + ... )
After a 100-ns de lay, PHRS is reset and PH RSA is set.
R/PHRS
S/PHRSA
PHRSASET FSCU
PHRSASET
Pr:I~SNED
PHR5NED
PHRS NED
+
PHFSET
CYClE/C PHRSA RSAU + ..•
PH~5.\
NBKCK
SEKSEND TCSOOO-3 + ••.
SENSE NPHRSAOO + •.•
SEKSEND
After a 100-ns delay,
PH~SA
CYClE/C PHFS DeB
N(NSCNMEN)
M/SCN
N(NSCNMEN)
DCl
RS/.\,R + •.•
RSAU
PHTO +
4-27 WRITE ORDER OR CHE:Cl(WRlTE ORDEf: 3EQUENCE.
If either a write order code or 0 checkwri te order code is
stored during the order out service cycle, the (DATA, IN)
flip-flops request a dataoutservicecycle (l, O)asdescribed
in pa:-agraph 4-30. Whi Ie signal PHFS is true, q service
cyr:le is requested by setting SC1'J. The TCl dc:lay line is
start~d when a function strobe signal is received.
When the request strobe i:; ocknowledged, the Tel delay
line is started and the byte counter is decremented.
DCl
PHFSET
NCD!'J DATAOUT SCR + .••
CYClE/C DClSTARTl + •••
DClSThRTl
PHFS FSU BSY(
(I
+ •••
Phazes FS, FSZ, and FSL are c:)ntrolled by the: \ome equatio"s described in parcgraph 4-23. However! !"It the end
of phase FSl, PHRSA ;s set end re'luest strob"! :,:gnc..,1 RSD
is raised.
is reset and PHRS is set.
R/PHFSl
R/pHRSA
S/pHRSA
S/pHRS
PHRSET
FSCU
FSC lOP +
PHRSASEr
PHFSl NIN + •••
PHRSA ;. •••
The request strobe is raise~ as in the previous RS phase,
and data is tiOnsferred through the K-register to the 0register. (For this operation, the K-register functions as
a gate. )
FSC NRSAR (FSCU RSr+ PHRSA RSET + ••• )
-RSD
RSET
OXK
OXKEN
PHRSASET FSCU
FSCU PHR5ET
PHFSL NIN
OXKEN TC5000-2
DATA~N
PHRS NED
(During the previous R5 phase, nodato was in the K-register.)
When the req:.:est strobe is acknow ledged, PHRSA is
set as before. Transfer between phase RS and phase RSA
continues unti I a II sense data has been transmitted to the
lOP, as indicated by the end data signal through the byte
counter wh ich is incremented during phase RSA. (See
figure 4-8. )
When the request shobe is acknowledged, thea"CL delay
line is storied and lOP dara is stored in the I-register.
CYClE/C PHRSA RSAU + •..
DCl
RSAU
IXD
lOP RSAR + ...
PHRSADO TCSOOO-3
PHRSADO
PHRSA DA T/\OUT
4-25
Paragraph 4-28
XDS 901565
After a 100-ns delay, PHRSA is reset and PH~S is set.
R/pHRSA
R/PH10
R/NPHFS
S/PHRS
PHFSET
FSCU PHRSET
PHRSA + ••.
PHRSET
PHFSET
,Once PHRS is set, the TCl de lay line cannot be started
·until RSAR is false and the J-register is empty (NJFI true).
When these conditions are true, request strobe signal RSD
is raised as the TCl delay line is !;tarted.
PHTO
4-28 READ ORDER SEQUENCE. If a read order code is
stored during the order out service cycle, the (DATA, IN)
flip-flops are set in state (1, 1) to request a data inseivice
cycle, as described in paragraph 4-30. While signoi PHFS
is true, a service cycle is requested by setting SCN. The
TCL delay line is started when a function strobe signal is
received.
CYClE/C DClSTART2 NRSAU
DCl
+
DClSTART2
RSD
PHFS DCB N(NSCNMEN)
M/SCN
'0'
PHRS WCHW NJFI + •.
N(NSCNMEN)
0
At the same time, the J-register is filled from the I-register
(for operation with a one-byte interface).
lOP Byn ID PHR5DO TCSOOO-2
PHRS DATA0UT
PHRSDO
Transfer from phase RS is to phase RSA or to phase TO, depending upon the end data signal ED. (See figure 4-8.)
PHRSASE-I FSCU
S/PHRSA
PHR5ASET
PHRSNFD +
PHRSNED
PHRS NCD
NeDN READ KFID BYT 4ID
+ NCDN READ KFID NSCR
+ NeDN READ KFID POST
FSC NRSAR (FSCU RSD
+ PH RS TC5000-2 + ... )
JXIlB
+
+ ...
The initial ser'.'ice cycle is requested under control of the
RK-counter through flip-flop SCR. When at least £Our data
bytes are· stored in the FAM module, r:ip-fiop SCR is reset
and SCN is t:Jirect set when KFID is 1rue. Subsequent service cycles are requested as a true NSCR signal indicates
that there are sufficient data b}·tes in the FAM mod·J:':~. A
service cyc!e may be requested any timf.:'Jfter postarnble
flip-flop POST is set. This condition can occur if t:1a!a
bItes rem~in in the rAM modu Ie after the postamble ;s detected. 'the date bytes arc transferred e·. .·cn if fewer than
four bytes remain. For.::: four-byte lOP interface (~Yr4ID
true)t all :>~rvice cycles are controlled by signal K~lD.
Phases FS, FSZ, and FSl are controllf'd by the same equations desc..ribed in paragraph 4-23. H0wever, ot th,- .:..nd of
phase FSL, PHRS is set.
R/PHF~L
PHRS ED
S/PHTO
Aal ED comes true under con:ro! of flip-flop EDISET3,
S/P:-:~S
FSCU PHRSET
~escribed
FSC Iep + •.•
in paragraph 4-35. (The lOP may terminate
the operation by causing signa I ESET to be true. )
PHRSET
EDISETl TCSOOO-2 + FSCU EDI
+ •
EDI
00
EDISETl
=
EDISET3 +
.0.
Thus the fI ip-flops cycle between phase RSA and phase RS
until an end data signal enables tr0:1sfer to phase TO. After
. ED is true, PHTO is set, as described in paragraph 4-25.
If the lOP does not signal count Clone or lOP hult during
phase TO, the (DATA, IN) flip-flops remain in state (l, 0)
and the sequence of data out service cycles continues. If
the IOPdoessignal countdone during phase TO, the (DATA,
IN) flip-flops are placed in stote (0, 1) to request an order
'~n service cycle. In either easel phase FS is entered from
phase TO.
4-26
PHFSl IN + •••
After PW~~ is set, the TCl delay line is slarted. Afc the
TCl dela,. line is sta;-ted, the request :;trobe signal :5 raised
and dota is stored in the O-registe:'_ These operations cannot take p;ace unti I the K-register is filled (KFID twt-».
= CYClE/C DClSTART2 N
DCl
DClST ART2
OXK
OXK£N
RSD
=
R: \\.) + ...
PHRS READ KFID +
= OXKEN TCSOOO-2
DATAIN PHRS NED
FSC NRSAR (FSCU RSD
+ PHRS TCSOOO-2 + ... )
XDS 901565
After a 100-ns delay, PHRSA is set and PHRS is reset.
Pcragraph 4-29
R/PHRS
PHRSASET FSCU
PHRSASET
PHRSNED +
PHRSNED
PHRS NED
When the request strobe is acknowledged, the TCl delay
line is started.
CYClE/C PHRSA RSAU + •..
RSAU
PHRS ED READ NRSAU + •••
DClSTART3
S/PHRSA
DCl
CYClE/C DClSTART3 + •••
DCl
RSAR + •.•
After ED is true, PHTO is set as described in paragraph
4-25.
If the lOP does not signal count done or lOP error halt during phase TO, the (DATA, IN) flip-flops remain in state
(1, 1) and the sequence of data in service cye les continues.
If the lOP does signal count done during phase TO, the
(DATA, IN) flip-flops are placed in state to, 1) to request
an order in service cycle. In either case, phose FS is entered from phase TO.
R/PHTO
After a 100-ns delay, PHPS is set and PHRSA is reset.
R/NPHFS
PHFSET
R/PHRSA
S/PHRS
PHRSfT
FSCU PHRSET
PHRSA + .•.
The request strobe is raised os in the previous RS phase.
When the K-register is fi! ied, the TCl delay line is started
and data is stored in the 0 -reg ister as before.
Transfer from phase RS is ;0 j:hase RSA or to phase TO, depending on end data signcl ED. (See figure 4-8. )
S/PHRSA
PHFSET
Pt;R~ASET
PHTO +
4-29 ORDER IN SEQUENCE. An order in s(:. vice cycle
follows execution of a completeJ order (seek, sense, read,
wri·e. or checkwrite) or an unu::.ual end indicC1t8d by flipflop UNE. In either case, the (DATA, IN) fnp-flops are
placed in the (0, 1) state as descriLedin para8i-aph 4-30.
Whi I~ signal PHFS is true, a servic.= cycle is r2quested by
setting SeN. The TCl delay line is started \\'her. a function
strc·oe signal is received.
CYClE/C PHFS DeB
NtNSCNMEN)
M/SCN
FSCU
N(NSCNMEN)
PHRSASET
PHR:;t'!ED +
PHRSNED
P~RS
S/PHTO
NED
DCl
PHRS ED
Signal ED comes true under control of the RK·-counter in
the FAM circuits when signa! KA8 indicales that the FAM
module is empty. Signal ED is normally controlled by the
lOP, and signal KA8 controls operation only if the lOP is
offline or if the last datCl byte is transferred from the FAM
module before the lOP generates an end data signal.
NRWE
~~WCHW
•••
CYClE/C DClST ART] + ...
DClSTARTl
PHFS FSU BSYCL
-l-
•••
Phast..s FS, FSZ, and FSl are cO:'"ltrolled by the same equations described in paragraph 4-23. However, ut the end
of phose FSl, PHRS is set.
R/PHFSl
FSCU PHRSET
S/PHRS
EDI
~~j)ATA
-+-
EDISET2 NPHRSA + FSCU EDI
+ •.•
FSCU
PHRSET
EDISET2 = KA8 OXKEN
Thus the flip-flops cycle between phase RSA and phase RS
until an end data signal enables transfer to phase TO. For
transfer from phase RS to phase TO, the TCl delay line is
started when ED is true and before a request strobe acknowledge is received.
FSC lOP + .••
=
PHFSL IN + ..•
The TCl delay line is started immediately, since the DATA
flip-flop is in the reset state.
DCl
= CYClE/C
DClSTART2 + ...
DClSTART3 = PHRS NDATA NRSAU + ..•
4-27
XDS 901565
41agrOPh 4-30
As the Tel delay line is started, request strobe signal RSD
is raised and order dota is stored in O-register bits 0, 1, 3,
and 4, as described in paragraph 4-38.
PHRSNED OROIN
OXORDIN
PHRS NED
PHRSNED
FSC NRS.A.R (FSCU RSD
RSD
+ PHR5 TCSOOO-2 + ..• )
After a 100-ns delay, PHRS is res~t and PHRSA is set.
R/PHRS
PHRSAS~T
S/PHRSA
PHRSASET
FSCU
EDI
=
NDATA + ...
The TCl delay line is started whe!" the request strobe is
acknowledged.
CYClE/C PHRSA RSAU + ..•
DCL
RSAR + ...
RSAU
Af:er a 100-ns delay, PHRSA i:. reset ':lnd PHRS is set.
R/PHRSA
DCBRsn
DCBRSTEN ORDIN PHTO
DCBRSTEN
ES + .•.
NTCS080
The TCl delay I ine may be started in eiiher of two ways in
phase 10.
DCl
CYCLE/C DCLSTARTl
+ CYCLE/C DCLSTART2 NRSAU
+ ...
DClSTARTl
PHTO RSAU + •.•
DClSTART2
PHTO ES +
Therefore, if the lOP has generated on end service signal,
the TeL delay Iine is stcrted after phase TO is entered
without waiting for acknowledgement of the requc"r strobe
wised at the start of phase RS. OtherwisE, the TeL delay
line is r.o~ started unti I RSAR is true. ,After a 100-ns delay,
the (Df.TA, IN) flip-flops are placed in a state ccrresponding to ~he manner in which the order in service cycle is
terminated. In either case, phase FS is entered from phase TO.
R/PHTO
PHFSET
R/f'.!f'HFS
S/PHRS
FSCU PHI\SrT
PHRSET
FSC lOP + •..
The TCl delay Ihe is started whr>n RSA~ is false. As the
~R si~nal goes false, a signal :~JD ciocks FSC, and FSC
."eset if the IOF drives ESR tftJe.
t'HFSET
PHTO +
4-30 :;eivice Cyc Ie Identification logic
The ty~e of service cycle is identified .by flip-flops DATA
and I1"-l, and associated output signa Is, as follows:
CYCLE/C DCLSTART3 +
DATA
IN
Service Cycle
PHRS NDATA NRSAU +
o
o
Order out
ORDOUT
R/FSC
ESR FSC
o
Order in
uRDIN
C/FSC
FSC RSD + ...
Data out
DATAOUi
Data in
DATp.If'~
DCL
DCLSTART3
If the lOP does not drive ESR true, the contrail er remains
service-connected to request a terminal order.
After a 100-05 delay, PHRS is rp-ser a:1d PHTO is set.
'~
DCBRSTl + •••
PHRSNED + ..•
EDISETl ,'CSOOO-2
+ FSCU [DI +
EDISEn
DCBRST
C/DCB
While PHRSA is set, signal ED ~omes true as described in
'ograph 4-35.
•
DCBRST
R/DCB
R/PHRS
=
S/PHTO
=
PHRS ED
o
When on input/output sequence is completed, DATA and
IN are direct reset afterfi ip-flop DCB is reset.
E/DATA
Terminal order operations are described in paragraph 4-34.
NDCB-l
NDCB-l
NDeB lOP + NDCS PET
If the lOP has driven ESR true, DCB is reset 80 ns after
•
Tel delay line is started.
4-28
Output Si::Jnal
E/IN
NDCB-l
Pnragroph 4-31
XDS 901565
Therefore, DATA and IN are both in the reset state {order
out} when an S10 command is accepted from the lOP. The
fl ip-flops are c locked only during phase FS or phase TO.
C/DATA
PHFSTOD TCS100-3
PHFSTOD
PHFSDAT + PHTO
PHFSDAT
PHFS OAT
C/IN
PHFSTOD TCS100-3
When the (DATA, IN) flip-flops detect a PET count done
signal (CDNPET), an online C0unt done signal (CDN), or
an unusual end signal (UNE), the flip-flops are placed in
the (0,. 1) state to request an order in service eye Ie. (Signal N$KSBK is true when nei ther a seek order nor a sense
order is being executed.)
S/DATA
DATASET NORDIN
S/DATA
DATASET
NCDN NCDNPET NUNE
SKSBK
SENSE BKWW +
NSKSBK
INSET NORDI N
S/IN
NORD4 + ...
INSET
If 0 write order or checkwrite order is stored during the
order out service cycle, DATASET is true and ORD4 is true,
. so that the (DATA, IN) flip-flops are placed in the (1, 0)
state to request a data out service cycle similar to a seek
order. For errorless operation, DATASET remains true unti I
phase TO of the servi ce cyc Ie is reached. If C0unt done
flip-flop CDN is set duri ng phase TOT DATASET becomes
faise, and the (DATA, IN) flip-Hops are placeJ in the (0,
1) state.
DATASET NORDIN
If a read order is stored during the order out service cycle,
DATASET
NeON NCDNPET NUNE NSKSBK
INSET NORDIN
DATASET is true and ORD4 is false, so that th.:. (DATA, IN)
flip-flops are placed in the (1, 1) state to request a data
in s'3rvic.e cycle similar to the s::nse 'Jrder. For errorless
operation, DATASET remains true untj I phase TO is reached.
If count done flip-flop CDN is set during pho::.e TO, DATASET becomes fa Ise and the (OAT A, IN) flip-flops are placed
in the (0, 1) state.
SKSBK
SEEK BKWZ + SENSE BKWW
NCAfASET +
If an invalid order is detected, both DATA and IN are set.
R/DATA
S/IN
INSET
R/IN
D/l,TASEi NORDIN
S/DATA
D;.;ring the execution of (.I;. order, the (DATA, IN) f1ipflops assume a sequence of s:a~es determined by the order
in which they are stored durin!] the order out service cycle.
If a seekorder is stored, signal DATASET is true until SKSBK
indicates that all bytes hrwp- been rransferred. Therefore
the (DATA, IN) flip-flops are placed in the (1, 0) state
during phase TO of the order out service cyc Ie.
After all bytes have been tr:msferred, S KSBK is true and
the (DATA, IN) flip-flops are placed in the (0, 1) state.
R/OATA
S/IN
INSET NORDIN
INSET
NDATASET + •••
NDATASET
SEEK BKWZ + ...
If a sense order is stored, C RD4 is fa Ise and DATASET is
true until SKSBK indicates that all bytes have been transferred. Therefore the (DATA, IN) flip-flop!> are placed in
the (1, 1) state during phose TO of the order out service
cycle. After all bytes have been transferred, SKSBK is
true and ORD4 remains false, so that the (DATA, IN) flipflops are placed in the (a, 1) state.
DATASET
~~CNE
NCDN h!CDNPET
NSKSBK
INSET NORDIt--J
S/IN
N(DATASET ORD4)
INSET
A s0ivice call for a data in service cycle be~ins. However,
unusual end flip-flop UNE is cli~ect set during !1hase FS,
and an unusual end takes place. (See paragrl..)ph 4-73.)
4-31 Order kegister
The order register consists of flip-flop ORDO, buffered
latches ORDl through ORD4, and associated IcSic elements.
The vrder register stores an order code durinCJ j~,e order out
sep,;ce cycle which occurs as the first step of ..::n input/output siZquence. The order code is retained duiin~ execution
of the order and controls the following signa!s (a Iso see
table 4-2):
(
0
3)
SEEK
CRD3 ORD4
SENSE
ORD2 NORD3 NORD4(04)
READ
ORD3 NORD4
WRITE
NORD2 NORD3 ORD4
(0 2)
(0/1)
4-29
XDS 901565
· r o p h 4-32
CHWR
SEKSEND
RCHW
ORD2 NORD3 ORD4
(05"j
NPHRSAOO SEEK
+ NPHRSAOO SENSE
4-32 Service Call Logic
NPHRSAOO READ
Signal SCD, wh ich requests a service call from the lOP, is
controlled by service call flip-flop SCN. (See figure 4-9.)
Service call signal SeD is raised to the true level when SCN
is set and (emains at the true level until SCN is reset.
+ NPHRSAOO CHWR
WCHW
The order code is retained during execution of orders while
the DATA flip-flop is in the set state (data in or dota out).
NPHRSAOO WRITE
- + NPHRSAOO CHWR
SCD
WRCH
NPHRSAOO WRITE
+ NPHRSAOO RCHW
lSl
LSL
NASCR INC SCN
+ ASCR INI lSL NRSTR SCN
For online operation (lOP true), the order code is stored
during phase RSA of the order out service cycle.
DA3R lOP
S/ORDO
Service coil flip-flop SCN is direct reset when the controller
is not bl'Sy and can be placed in the set state only by the
direct set i"put. The direct set input can be true enly during phose FS after DCB has been set by an SIO com'Tland.
R/ORDO
E/seN
NDca
M/SCN
CYClE/C SCNMEN
ORDXIOP
C/ORDO
ORDXIOP
lOP PHP-SAOO TC5000-3
PHRSAOO
PH RSA ORDOUT
SCNMEI'J
ORDl
DA4R ORDXIOP +
ORD2
DA5R ORDXIOP +
ORD3
DA6R CRDXIOP +
ORD4
.DA7R ORDXIOP +
After SeN has been set, it may be retained in the :.ct state
for cer~oi:: conditions if the controller is operating ;~ the
extended pel formance mode (EXT true) and is execuri ng a
read orck:r, write order/or checkwrite order. S,snal
SCNEN I;> true when additional servicf' colis ore re.:pired
to maintain the data transfe~ rate during extended performance eperotion and prevents reset of SeN during ph~se
FSL.
The order code bits aie retained i,l buffered lotches ORDl
through ORD4 whi Ie ORDXO is fflJe.
ORDl
ORDl ORDXO +
ORD2
ORD2 ORDXO +
ORD3
ORD3 ORDXO +
PHFS DCB N(NSCNMEN)
S/SC.\l
SCNEN
~~NEN
SCN DATA EXT SCSET
SCSET
READ NRKl + WCHW RKl SCR
RKl SCR
C/SCN
TCS100-3
ORD4 = ORD4 ORr)XO + ...
If SCN is
After an input/output operation is completed, flip-flop DCB
is reset and the order register is cll'}ared. (For command
chaining, DCB is not reset. )
NORDXO = PHFS NDCB + ...
NORDXO
PHRSAO~D
4-20
PHRSAORD TCSOOO-1
PHRSA NDATA
during phose FS, SCN is reset during rl,ase
R/seN
SCNRST
A new order code is stored as sign'J! ORDXO goes true during
phase RSA of an order out service cycle.
.~
5et
FSL.
+ •••
C/SCN
SCNRST
PHFSl +
TCS100-3
Preventing reset of SeN allows the FAM module to be fi lied
during write or checkwrite operations and to be emptied
during read operations without requiring the controller to
wait for priority on the data lines from the lOP.
XDS 901565
34
NRWE
NDATA
SCNMEN2
CDN
NJFI
15
4
NSCNMEN2
NKFID
REMPTY
NCDN
8
WCHW
SCNMENl
,.--i>-
2
NSCNMEN
NUNE~6
21
5C
DCB
CYClE/C
39~_._
PHFS
READ=E"4
lOA \
NRKl
33
WCHW~
~
I
RiC1 1T ~J
'rr-
43
OA
/ , ' -_ __
,
~~44...:....---..;..;...;;...:
-L:./1
)
-
DATA
EXT
RK1 SCR
11
FF
31
5C
. . _8_C_)~a~.--
PHFS]20
"
NSCNMEN
NBYT4ID
NPOST
SCR
M
NPHFSL-9---~
15A
SCR
SCNEN
19,
_
NDCS
6'~
7.
5
8:)12
SCNREN~21
.READ
20
KFID
29
88
)r-14~_ _
NSCNMEN126
SCNMENl
37
----
--D-A-TA-O-UT-J~44~-9-C-).:::.:36~_~
SEN
44
NTSE]
88 )
__
36::....-_......
901565A. 404
Figure 4-9. Service Coil Flip-Flop SeN, logic Diogram
4-31
Paragraph 4-33
XDS 901565
After a service call involving data transfer is processed,
additional service calls wi! I be necessary unless all bytes
requiredby the order have been transferred. However, if
no additional service calls are necessary and SCN has been
prevented from resetting on the previous service call, an
additional service call wi II be requested unless SC N is reset
in phase FS. (This condition can occur only for read orders,
write orders, or checkwrite orders when the controller is
operating in the extended perf0rmance mode.) If all bytes
have not been transferred, SC N wi II be he Id in the set state
after phase FS is entered; if a II bytes have been transferred,
SCN wi II be reset after phase FSL is entered.
M/SCN
CYCLE/C DCB PHFS N(NSCNMEN)
R/SCN
SCNRST
BKO
BKl
Output Signal
o
o
BKWW
o
BKWZ
o
BKZZ
When on I/O sequence is completed, BKO and BK 1 -:lre
direct reset after device controller busy flip-flop DCB is
reset.
NDCB-l
E/BKO
NDCB-l
SCNR5T
C/SCN
TC5100-3 + ..•
CI
true N(NSCNMEN) signal
UNE (Unusual End)
+ NDl·TA NRWE CDN NJFI
NKFI[) REMPTY
NDATA NRWE NWCHW
NeDN DATAOUT SCR
NC;)I'~ SEN NTSE
NCDi'J READ KFI[) BYT 410
NCi)N READ KFID POST
NCL)N READ KFID NSCR
NC:)N CDNPET
+
+
+
+
+
+
+
NDCB-l
E/BKl
C ...)i" •
Therefore, the byte counter (BKO, BK1) is in the (0, 0)
state (BKWW true) when an SIO command is accef.'ted from
the lOP.
The byte counter is direct set to state (1, 1) when slenal
BKXl is true. Signal BKXl is true .:Iuri'lg phase KSA of cn
order C\ut service cycle, when the J -regis;er is fi i ied during
execution of a write order or checkwrite order anrl when
the O-register is cleared during execution of a read -:--rder.
BKXl
M/BKO
BKXl
PHRSAOO + NBKXl EN
PHRSAOO
PHRSA ORDOUT (PhaSE: ;(5,\ of
order our service cycle)
NBKX1EN
WCHW JFIXl (J-registe:- filled in
write or checkwrite)
+ READ KXOEI"
O-reg;ster
1
OXKEN TCS 00-3
in
reu':;
PHRS DATAIN NED
4-33 Byte Counter
•
The byte counter is used durir~£ ,~xE:cution of seek orders
d sense orders and during e)'ecution of read orders, write
.:leI's, or checkwrite orders for a multiple-byte lOP interface. For a sense order, the byte ccunter controls the transfer of data bytes info the K-regic;ter and a-register and
raises the end data signal.
Fur a seek order, the byte
counter controls the transfer of data bytes from the Jregister to the T -register and raises the end data signa L
For read orders on a multipit:::-Lyte interface, the byte
counter controls the trunsfer of data from the FAM module
to the K-register or I-register. For write orders or checkwrite orders on a multiple-byte interface, the byte counter
controls the transfer of data from the extended I -register
to the lower order byte of the I-register.
The byte counter consists of flip-flops BKO and BKl and
associated logic elements. Each byte of a service cyc!e
is identified by sta!es of the byte counter as follows:
.~
4-32
NDCB lOP + NDCB PET-I
PHFS NSCNMEN + ...
The conditions that generate
are:
N(NSCNMEN)
BKZW
1
KXOEN
OXKEN
J
c'~(~(ed
BKXl
M/SKl
The byte counter is clocked on the falling edge of ~!gnal
BKCK (which is equivalent to the rising edge of o:;gool
NBKCK).
S/BKO
R/BKO
NBKO
XDS 901565
C/BKO
NBKl
S/BKl
NBKl
Paragraph 4-34
The command chaining signal, which is sampled cnly at the
end of an order in service cycle, is valid only if no unusual
end condition exists. The command chaining signal is equivalent to:
R/BKl
CCH == lOP DA2R NDA3R
C/BKl
BKCK
As the byte counter (BKO, BK1) is clocked, it passes from
state (1, 1) to state (1,0), then state (0, 1), then state
(0, 0) un less cleared or di rect set.
If the lOP orders command chaining, DCB is not reset at
thp end of an order in service cycle; if command chaining
i~ "lot requested, DCB is reset.
DCBRST
R/DCB
When a seek order or sense order is to be executed, the
byte counter is initially placed in stote (1, 1) during phase
RSA of the order out service cycle, then is counted down
to control transfer of data.
NBKCK = PHRSA $[i-flops CIl, CDN, and UNE are controllf;::J by signal
TORD, which is true only when terminal crde. data is to be
ac.cepted.
iORD
=
lOP NES ED PHTO
+ BI-/ED/
38
ED!
M
R
RSD
4
FT2l
19C
LT41
C 29C
FSC
EDr
EDD
18
2
CYCLE/C
FSR
3
7
BT16
12B
30
SEEK
NFSC
20
5
9
FT29
19C
E5
NPHRSA
13
~
FT27
19C
21
ED
19
5
FT27
19C
46
ESR
---4>--/E5/
Figure
4-10.
End Data and End
Service Logic, Logic Diagram
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ...JL-._ _ __
90156)A.419
4-35/4-36
Paragraphs 4-36 to 4-37
XOS 901565
EDI
EOISEn NPHRSA
+ FSCU EDI
+ •••
=
EDISET1
SENSE BKWZ
For a two-byte interfac~, EDISET3 is set when bytes 13 and
14 are received, and /ED/ is driven true when bytes 15and
16 are requested.
+ .••
SjEDISET3
For a read order, signal EDIis driven true when the FAM
module is empty (KA8 true) and the last byte is being transferred to the O-register.
NEDIS3
C/EDISET3
NEDIS3 NSCR
PHRSADO NBYTl ID + •••
TCS100-3
EDISET2 TCSOOO-2 + FSCU ED
EDI
+ •••
Flip-flop EDISET3 is direct reset when the con:rol :er is not
busy.
EDISET2
KA8 OXKEN + ..•
OXKEf\.J
DATA!N PHRS NED
E/EDISET3 = NDCSl
4-36 INPUT/OUTPUT DATA BUFFER
Sigl)al KA8 can be tn'e only after SCR has been set and the
FAM module is empty. (See paragraph 4-42.) As the last
data byte is read from the F,'\M modu Ie, a true KFISET signa allows KFI to latch truE'. If signal REMPTY is true,
signal KA8 is true.
KA8
The registers of the input/output data buffer s'ior~ data accepted from the lOP for trcnsfer to the FAM module and
store data accepl'ed from the FAM module for transfer to
the lOP.
N(t'-!KA8) SCR
4-37 I-Register
N(NKA8)
KAg KfID + KFIDXl REMPTY
KF!D
KXO (KFID + KFIDXl)
KFIDXl
KFl TRS270
KFI
KXG (KFIXl
KFIXl
KFISET RREAD-2 TRS 130
The I-register consists of buffered letches IOO rnrough 131
arid associated logic elements. During exccuti()n of awrite
order or checkwrite order, data bytes are:acccpted from the
lOP ol'\d are transferred from the higher oider byte of the
I-rc}:lister (100 through I07) to the J-register. If the controiler is operating with 0 two- or four-byte jj'1·crfoce, Jato
must be transferred from iower order bytes of th~ I-register
to i"1.E: higher order byte for transfer to the J -register. Dming eXecution of a read order, the lower order bytcs of thc
I-register are used if the controller is operating with a twoor four-byte interface. In these cases, the I -register accepts
dCit:. from the FAM module for transfer to the G- ,esister.
Du, ing execution of a seek order, tV/o consecutive data
b)'t~s are transferred from the lOP to the l-reg;s;er, then
fro,." the I-register to the J-register.
+ KFI t'-lPHRSAOO)
For a write order or a checkv:rite order, signal EDI iscriven
true when fi ip-fiop EDISE-.·3 is set.
EDISETI NPHRSA + FSCU EDl
EDI
+ •.•
EDISET'i
=
EDISET3 +
If the controller is operati:1g with a four-byte interface,
all four data bytes are tra ...·~ferred at once so that data
input er.ds in one data ou t serv; ce eye Ie. There fore, EDISET3
is direct set for operation with a four-byte interface.
During phase RSA of a data out service cycle (write order,
checkwrite order, or seek order), lOP data is st.\red in the
I-register. For a write order or checkwrite order t the data
path may be 8 bits, 16 bits, or 32 bits wide.
DAOR IXD-1 + •••
100
M/EDISET3 == BYT 4!D
IXD
(IXD-l through IXD-4)
For a one- or a two-byte intorface, flip-flop EDISET3 is
IXD
PHRSADO TC5000-3
set after all four data bytes have been accepted. For a onebyte interface, EDISET3 i:. set when byte 15 is received, and
PHRSADO
PHRSA DATAOUT
/ED/ is driven true when byte 16 is requested. Refer to
paragraph 4-42 fOi operatlon of the RK-counter.
S/EDlSET3
NEDIS3
C/EDISET3
101
DAl R IXD-1 + ...
107
DA7R IXD-l
I
"\
I
~ Syte I
NEDIS3 NSCR
PHRSADO NRK3 + •••
TCS100-3
+ ..•
4-37
XDS 901565
108
124 IXI-3 + •••
100
DBORIXD-2 + ••.
IXI-3
Byte 2
115
DB7R IXD-2 + •.. "
116
DCOR IXD-3 + ...
Byte 3
123
DC7R IXD-3 +
124
DDOR IXD-4 +
RWRITEDO IXEN BKWZ
101
124 IXI-3 + •••
107
= 131 IXI-3 + •••
DD7R IXD-4
+ ...
For a controller operating with r: two- or four-byte interface, data bytes ('Iccepl"ed from rhe lOP are transferred to
the higher order byte under contr,)1 cf the byte -cOllnter
Z(BKO, BK1). Refer to paragrap~ 4-33 for a description of
the byte counter.
109
Transfer from (lOB through 115) to (100 through 107) takes
place after the first data tra;"lsfc:" from (100 through 107) to
the J -register.
!15
IXR-l ROO + ..•
IXI-l
RWRITFDO IXEN BKZZ
RvVRITEuO
RWRn~·2
IXEN
NBYTl ID NTRL240 TRL 180
IXR-l
READRR BKZW IXEN
IXEN
NBYTlID NTRL240 TRL180
READRR
READ RREAD-2
IXR-l
=
109 IXl-1 + •••
107
= 115 IX 1-1 + ...
R01 + .•.
IXR-l R07 + ••.
ROO IXR-2 + •••
DATAOUT
101
Byte 2
Signals f RL240, TRL180, and RRE.A.D-2 are control !cd by
the TRL j~lay line, Signal BKZW is centrolled by fne byte
counter. (This transfer takE's place at the same tir.·e that
data tronsfers are mcde between bytes of the I-reg ister. )
108 1),1-"1 + ...
100
J
During execution of 0 read order for a controller using a
two- or a four-byte interface, data bytes are transferred
from the FAM module (ROO through R07) to the I-register.
108
131
Byte 4
'XR-2
Byte
2
READRR IXEN BKWZ + •••
ROl IXR-2 + •••
Signals TRL240, TRl180, and RW!atlse order)
DATAIN
PHRS NED
PHRSA NIN
KOl OXK
001
108
lOS IXO-2 +
115
I1f\ IXO-3 +
116
116 IXO-3 +
+ •..
007
008
123 IXO-3 + ••.
124
124 IXO-4
131
i31 IXO-4 + •..
(IXO-?
-0
IXO-4)
NIXO
-1- •••
lYO
tH~SAOUT
TCSOOO-l + KXOEN
PHRSAOUT
PH;(SA NIN
KXOEN
OXKEN TCS100-3
=
···1
131 OXK + ...
031
l
Store contents
cf (108-131)
in (008-03i)
(Reed order
only)
Signal OXO is used to clear the O-register before storage
of new data and to retain the stored data. Hie O-register
is r:leared when signal axo is false and ratain;; data \vhile
signal OXO is true. S!gnal OXO is equivalent to request
strebe signal RSD.
(OXO-l - OXO-4)
OXO
aoo
000
axo
+ •.•
RSD
OXO
{C lear after data
lTansfer from lOP
001 OXO +
001
OXKEN
108 OXK +
•
{Clear after
data transfer
Dt\ TAIN PHRS NED
to lOP
4-38 O-Register
The O-register, which con~i(ts of buffered latches 000
through 031 and associate0 logic elements, stores data fOj"
transfer to the lOP. During phase RS of a data in service
cycle, the contents of the K-register are transferred to bits
o through 7 of the a -registt::r, and the contents of the 1register bits 8 through 31 are transferred to bits 8 through 31
of the a-register. (If the controller is operating with a
one-byte interface, only the K-register contains data; if
the controller is operating 'Nith a two-byte interface, only
the K-register and bits 8 through 15 of the I-register contain data. For a four-byte interface, all signals contain
data.) Since a dota in service cycle is part of a read order
and a sense order, the O--registcr is loaded from the Kregister or I-register for execution of these orders.
=
031
031
axo + •••
During execution of orders, signal RS[; becomes true when
a s~robe is requested from the lOP and is lotcheJ until the
request strobe is acknowledged.
-,
- RSD
FSC NRSAR (PHRS TCSOOO-2
+ RSET NPHRSA + FSCU RSD)
FSCU
FSC lOP +
RSET
PHFSL NIN
After RSD is true, data is stored in the 0 -register. After the
data is read by the lOP, RSAR becomes true and RSD is false.
4-39
XDS 901565
4IJ9raph 4-39
During execution of a sense order, the track protect bit
from the selection unit (TRPR) and bits 0 through 6 of the
track address are stored in the O-register while the byte
counter indicates byte zero (BKZZ).
OXSENSEl TRPR + •••
000
OXSENSEl
SENSE OXKEN BKZZ
001
OXSENSEl TOO + •••
007
OXSENSEl T06 + •••
order or checkwrite order, the J-register accepts data from
the I-register for transfer to the FAM module. During execution of a read order, the J-register accepts data from the
D-register for transfer to the FAM mcdule. During execution
of a seek order, the J -register accepts two bytes of data
from the i-register to the T-register and S-register.
During execution of a write order or checkwrite order, data
from the higher order byte of the I-register (100 through 107)
is transferred to the J-register. If the controller is operating with an 8-bit interface (BYTlID), the transfer takes
place during phase RS under control of the TCl delay line.
100 JXl1 B + ••.
JOO
(Additional bytes of the sense order are transferred to the
a-register from the K-register.)
. i n g phase RS of an order in se.-vice cycle, 'four bits of
control information a:-e sent to the lOP from the O-register.
000
OXORDIN TER
+ •••
(Control error,
parity error, or
rate error)
JXI1B
lOP BYTlID PHRSDO TCSOOO-2
PHRSDO
PHRS DATAOUT
JOl
101 JXI1 B + •••
JO?
107 JXIl B + .•.
TER
CER + FER + RER
If the !"ontroller is operating with a 16- or 32-bit
OXORDIN
ORDI!'.. PHRSNED
PHRSNED
PHRS
interface (NBYT1ID), transfer of data from the I-register
to the J-register must allow time for transfer from higher to
lower c;d~:- bytes of the I-register (refer to paragraph 4-37
for a de:;cription of the I-register). Therefore, for 1A- 01
32-bit ;r~erface operations, the transfer b control :ed by
the TRl delay line.
f'.,;~D
OXORGIN INl
001
(Incorrect length)
+ •••
003
OXORC'I'l + ..• (Alwa}.'i true)
004
OXORC'N UNE (Unusual end)
100 JXINl B + .••
JOO
JXJNl B
+ •.•
e
n th,~ controller responds to c.:; AlO signal, three bits
nformation are sent to the lOP from the O-register.
OXAI0~T
000
+
OXAIOST
002
...
AIOC
RER
~SU
OXAIOST SUN (Sector unavailable)
OXAIOSl WPV (Write protect
violation)
+
JOi
JOl JXINl B + .•.
J07
107 JXINl B + .••
(Rate error)
+ •.•
003
lOP NBYTl ID DATAOUT
RWRITE-2 TRS060
. ..
During execution of a read order, data bytes are trl.Apsferred
from the D-register to the J-register. This transfer takes
place af'er the preamble has been detected (NPRE) under
control of the TDl delay i ine (TOT2).
000 JXD + •..
JOO
The conditions Vv-hich control flip-flops TER, INl, UNE,
RER, SUN, and WPV are describt::d in paragraph 4··72.
JXD
READ NPRE TDT2
J01
001 JXD + ...
J07
D07 JXD + •••
'1,4-39 J-Register
The J-register consists of buffered latches JOO through J07
Du6ng execution of a write
~ associated logic elements.
4-40
XDS 901565
If the controller is operating offline, the J-register accepts
PET -generated signals under control of the TRL delay line.
JOO
OPOD JXOP + •••
JXOP
PET -1 RWRITE-2 TRS060 DATAOUT
DPOl JXDP + •••
JOl
DP07 JXDP + .•.
J07
Signal JXO is used to clear the J-register before storage of
new data and to retain the sTored dal·o. The J -register is
cleared when signal JXO is false and retains thp. stored data
wh i Ie signal JXO is true.
JOO
JOO JXO + ..•
J07
J07 JXO + ...
During execution of a read
just before data is stored.
t-4JXO
=
READ TDTl
order~
the -' -register is cleared
+ ••.
ing execution of a wri te order or a checkwrite order,
the J-register is cleared by a signal related to thesigncl
which causes data transfer. F::>r a one-byte interface tb;
J -register is always cleared during phase RS of a data OU+
service cycle.
DUi
NJXO = PHRSDO TC3000-1 + ..•
For a two- or four-byte interface, the J-registcr is cleared
during each F.h.,M write cycle.
NJXO
=
RWRITE-2 TR.S270 NTRSOOO NBYT11D + •.•
Paragraphs 4-40 to 4-41
a-register, to the lOP. For a two- or four-byte interface
width between the controller and the lOP, data bytes pass
from the FAM module to the K-register and the I-register,
then through the a-register to the lOP. (See figure 3-7. )
Thus, dota bytes pass from the J -reg ister to the FAM modu Ie,
and from the FAM module to the K-register {or the I-register}
regardless of the direction of data flow between the IOPand
a selection unit •
The TRL delay line is started each time a data byte is to be
written into the FAM module (FAM write cycle) or read from
the FAM. module (FAM read cycle). The RK-cCJul1ter keeps
track of the number of active bytes in the FAM moou Ie
(byte~ written into, but not yet read from, the fAM modu Ie).
The L-register addresses a location in the FAM rr•.x.!ule into
which 0 byte is written, or from which a byte is read, and
generates outputs that indicate the next FAM rnoduie location addressed. During a fAM write cycle, the JP-register
accepts from the L-register the address of tht> next FAM
module location into which a byte is written. DUi"ing 0 FAM
read ~icle, the KP-register accepts from the L-register the
addreJs of the next FAM iiiodule location from which a byte
is re0d.
The FAI\A, module (figure 4-12) contains 16 addrt'.'ssabl'? eightbit ;-;~q:sters. The four-bit address determines which of ~he
16 registers is available for input or output. A data byte is
stor~d in the cddressed register m the input ..::iock signal
goe.> +~Ise. Data may be read from the address2d location
at on, iime.
4-4-; TRL Delay Line
The: TRL delay line (figure 4-13), which consiSTS of a 300-ns
deley line and associar~d gates i controls data transfer into
one C'Jt of the FAM module, increment and de(''-ement of
the k;(-counter, and transfer of addresses from rhe :"-register
to thE; KP-register or the JP-regcster. During the execution
of a !.~ek orJer, the TRL delay line controls sto(uge of data
into be T-register and the S-register.
Vvh:!;> device controller busy flip-flop DCB is in the ;eset
staTt, CYCLER is true and remai ns latched after DCB is set
by at. accepted SIO command.
4-40 FAST ACCESS MEMOR"y' (FAM) CIRCUITS
CYCLER = NTRS030 (NDCB + CYCLER + •.. )
FAM circuits consist of the TRL delay line, the RK-counter,
the J-poinier register (JP-register), the K-pointer register
(KP-registPr), one FT25 Fast Access Memor)1 modu Ie (FT25
FAM modu Ie), and interconnect ing logic elements. (See
figure 4-11. )
FAM circuits are used only during execution of a read order,
a write order, or a checkwrite order. During execution of
a write order or a checkwrite order, data bytes pass from
the lOP through the I-register, the J -register, the FAM
module, the K-register, and the D-register to the selection
unit. (See figure 3-6.) During execution of a read order,
data bytes pass from the selection unit through the D--register!
the J-register, the FAM module, the K-register, and the
14cot
Vvher- SREAD (or SWRITE) comes true during exrcution of an
order: the TRL delay line is started. After a 30-ns delay,
a fn:e TRS030 signal inhibits the inputs, the siS"ol CYCLER
goes false, and the SREAD (or SWRITE) signal does fiot control the delay line. After a 130-ns delay, a tnll': TRS130
sigllal inhibits the SKEAD (or SWRITE) 5ignal.
SREAD
NTRS130 NREMPTY (DCB SREAD + ..• )
5WRITE
NTKS130 RKO (DeB SWRITE + .•. )
Because the CYCLER signa I is an input to starting gates for
SREAD and SWRITE, the SREAD ond SWRlTE signal cannot
4-41
XDS 901565
NBKZZ
KOO
THROUGH
K07
READ
(ROO-ROJ)
RREAD-2-
{DOO-D07)~"
FAST ACCESS
(JJO-J07)
8
JXD~
.no
THROUGH
.n7
(IOO_I07)~
CLOCK
8
_
TRS180
~O
THROUGH
007
_
1_________ ___P_H_RS_'~O 4f
I
:
----r---'\~PXL
2
(LEO, LE1, LE2, NL03)
-l
THROUGH
TRS270,
NTRSOOO----L--./
I ]
KP3
RREAD-2-~,
4
TRSl80
L_
/r(PXO
.-------------l
Kro
Ill-o .
RREAD-
r
{RWRlTE-2~D-. I
rAIlBfl
JY'N1B
MEMORY FT25
I
L_-.1.:._ _- - r
1 - 1_ __
NTRS030
PHRSA(,C;
lOO
THROUGH
l03, NL03
I
(lOO:L03~-.J
4.
RWRITE-l-~-
4
JPO
THROUGH
JP3
(Jro-JP3)
4
RKQ
ORDour
PHRSAOO---o--
TCSOOO-3----~
THROUGH
RK4
REMPTY
PHRSAOO - - - - - - - - . . ,
~
TRSl3)
901 565A. 4 i 0
Figure 4-11.
4-42
FAM Circuits, Simp I'f'
t leo'L 0,gic Diagram
XDS 901565
--,
1-
I
P19B
"..-
13 I - - -
TRS180
INPUT
CLOCK { f{lNRfTE-2 - - 31
ADDRESS
INPUTS
lr
lOO
L
LOl
}-
p.-
REG!STEI~
I·
,I
,I
30
--
29
L02
18
~B
L03
25
43
NL03
23
4-1
16
ADDRESSABLE
8-BIT
REGISTERS
JOO --- 35
34
JOl
INPUTS TO
ADDRESSED
I
9
---
2
J02
- - 19
J03
12
J04
33
f---.oI
28
I
j05
'----
45
46
4
1
R01
l
R02
R03
~
ROO
R04
-
R05
i----
R07
J
OUTPUTS
FROM
ADDRESSEt)
REGISTEP.
R06
I
17
J06
J07 -J~
I
--
I
L_
I
I
_______ J
90l565A. "10
L--_ _._ _ _ _ _ _ _ _ • _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Figure 4-12. FAM Modu ie, B!ock Di'.:lgram
start a new TRL delay line r.ycle until the previous cycle
is complete.
SWRITE
NTRS 130 RKO (CYCLER JFI NTRSOOO
+ .•• )
SREAD
NTRS 130 0l REMPTY (CYCLER NTRSOOO
N KFI SREAOE N
+ CYCLI:t\ NTRSOOO NFKI READ + ... )
Af~E:f a 300-ns delay, CYCLER becomes true and is latched,
allowing the SREAD (or SWkITE) signal to ::.tart the delay
I be if requi red.
been sto~ed in the J-n:gister. Vv'hen the FAM I"l"",odule is
full, flip-flop RKO is set end the SWRITE signal is inhibited,
pre ... enting any additional FAM write cycles. The SREAf'
signal cannot be true unless the K-register-fil!erl s:~nal
KrI is false. Signal KFI is true. after data has been ~tored
in the K-register and is not false until the data has been
transferred from the K-register during exec uti (;n of an order.
When the RK-counter indicates that 01 i activE' byles have
be;n read from the FAM module, a true REMPiY signal inhibits the SREAD signal, preventing any addithllal fAM
read eyc les.
During execution of a read order, write order, or checkorder, FAM write cyc les and FAM read cycles moy
occllr in any sequence, under control of signals KFI and
JFl. Vvhen signal JFI is true andsignal KFI i:; false .. signal
SWRITE and signal SREAD are both true. When CYCLER
comes true at the end of a FAM write cycle or FAM rccld
wr;h~
CYCLER = NTRS03G (TRS300 + CYCLER + .•. )
The SWRITE signal cannet be true unless the J-registerfiilcd signal JFI is true. Signal JFI is true after data has
4-43
XDS 901565
TRSl30
2
47
REMPTY
~'-------"" TRS 180
TRL180
Cf\~llB-'-'19:-_ _ _ _ _ _ _ __
TRll vv-~
..
NTRS120
TRLOOO
TRL060
TRL130
9
23
31
300 NS
TRS300~31
NDCB- 33
148
2
_
_ _---I
TR~130~5
9B
NRKO
.- - - - ,
40 '--
CYClE'~8rn
JFl
.9
~OB
NTRSOOO
).
17
TRl300
ill
2
[
.,. TRL240
bo
SWRITE
lOB
TRl27~
!Ruse
;II
.. TRlO9C
~TRL030
TRLO~U--~~~----38&_
~-
DC'~-
12C
35
NTRS030
43
-~-----I
CYCL;:R-~_
SKEAD OR
r---,
SWRITE
----1
TRLOOO
~L-_~.
~
______
n,. . ___
TRL030
--Fl _______
TRL130
~
TRlJOO
U
NTRS030
TRSl80
_ _ _ _ _ __
____________
o
90
Jl~
180
TIME IN NS
________
270
360
NOTES:
ONr Of TWO DUPLICATE FAM READ GATES
ONE OF TWO DUPLICATE FAM WRITE GATES
IJ]
rn
901565A.403
Figure 4-13.
4-44
TRL Delay Line, Logic and Timing Diagram
XDS 901565
cycle, the TRL delay line is started by both signals. However, either a FAM write cycle or a FAM read cycle can
occur, but not both. Priority is established by signals
which detect the type of order being executed. Ifa write
order or checkwrite order is being executed, signal WCHW
is true and data transfers from the FAM modu Ie to the Kregister have priority; therefore, a FAM read cyc Ie must
take precedence over a FAM write cycle. ·If a read order
is being executed, signal READ is true and data transfers
from the J -register to the FAM modu Ie have prioritYi therefore,a FAM write eye le!TIust take precedence overa FAM
read cycle.
Paragraph 4-42
(S/RKO-S/RK3)
ORDOUT
(C/RKO-C/RK3 )
RKCK
N(PHRSAOO TC5000-3 + .•• )
RKCK
Fer service cycles other than order out, clocking for all
flip-flops takes place at the rising edge of TRL delay line
signal TRS130.
{C/RKO;"(/RK4)
RKCK
The following signals control operations during a FAM
write cycle.
RWRITE-l
N(SREAD WCH\V) (SWRITE TRS030
+ RWRITE-l NTRSOOO) NTRS130
N(SRb~D
RvVRITE-2
RWRITE-N4
=
WCHW) (SWRlTETRS030
+ RWRITE-2 NTRSOOO)
S/RK4
RWRiTE-2 NRK4
R/RK4
N(READ SWRITE) (SREAD TRS030
+ RREAr)-l NT RSOOO) NTRS130
RREAD-2
N(TRS130 + .•• )
Flip-flops RKO through RK3 form or. up/down counter clocked
by s:gnal RKCK and control!ed by flip-flop RK4. Flip-flop
RK4 changes state at each clock and controls all read count
ga:es through signai RREAD-4 and controls all write count
gates through signal RWRITE-N4.
The following signals control operations during a FAM iead
cycle.
RREAD-l
RKCK
N(REt,D SWRITE) (SREAD TRS030
!,·!RK4
~READ-4
RREAD-2 RK4
RWRITE-N4
RWRITE-2 NRK4
Ther.::.~ore, read count 9'Jtes are enabled duri!'",g a FAM read
cycle, and write count gates are enabled duo ;;-'G a FAM
v..;;re cyCle.
+ RRE,A.D-2 NTRSOOO)
RREAD-4
=
RREAD-2 RK4
If both SWRiT[ and SREAD (;re true, only one of these two
sets of signa Is are val id. If signal WCH'N is true, c
FAM read cycle occurs because the factor N(SREAD WCHW)
is false. If signal READ is true, a FAM write cycle occurs
because the factor N(READ SWRITE) is false.
4-42 RK-Counter
During executi0n of a re~d 0rder, write order, or checkwrite order, a data byte !~ transferred from the J-register
into an addressed location in the FAM module· during a.
FAM write cycle, or read from the FA.M module into the
K-register (or the I-register) during a FAM read cycie.
. The RK-counter, which consists of flip-flops RKO through
RK4 and associated logic t:lements, keeps track or the number of active bytes in the FAM module.
During phase RSA of an order out service cycle, RKO
through RK3 are set and R~(4 is direct set. Clocking takes
place at the rising edge of TCL delay line signal TC5000-3.
M/RK4
PHRSAOO
If signa I RREAD-4 is true when the fI ip-flops a:-c cloc-ked,
flip-flops count ~I)' as indicated in tablt.4-3.
th~
SIRKO
RREAD-4 NRKO RKl RK2 RK3 + •••
R/RKO
RREAD-4 RKi RK2 RK3 + ...
S/RK)
RREAD-4 NRKl RK2 RK3 + •.•
R/RKl
RREAD-4 RK2 RK3 + •••
S/RK2
RREAD-4 NRK2 RK3 +
R/RK2
RREAD-4 RK3 + •.•
5/RK3
RREAD-4 NRK3 + •.•
R/RK3
RREAD-4 + .••
If signal RWRITE-N4 is true when the f1ip-f10psareclocked,
the flip-flops count down l as indicated in tabb 4-3.
SiRKO
RWRITE-N4 NRKC NRK 1 NRK2 NRK3 + ••.
PHR5AOO
R/RKO
RWRITE-N4 NRKl NRK2 NRK3 +
PHRSA ORDOUT
S/RKl
RWRITE-N4 NRKl NRK2 NRK3 +
4-45
XDS 901565
R/RKl
RWRITE-N4 NRK2 NRK3 +
S/RK2
RWRITE-N4 NRK2 NRK3 +
R/RK2
RWRITE-N4 NRK3 +
S/RK3
RWRITE-N4 NRK3 +
R/RK3
RWRITE-N4 + •••
call logic (paragraph 4-32), and the end data and end service logic (paragraph 4-35). At the start of a date out or
a data in service cyc Ie, the RK-counter (RKO RKl RK2 RK3
RK4) is in state (1 1111). For either type of service cycle,
dota bytes are first written into the FAM modu Ie, causing
a countdown for each byte written. As a byte is read from
the FAM module, a countup occurs. If the RK-counter
reaches state (0 1111), 16 active bytes are stored in the
FAM modu Ie and ~he SWRITE signal is inhibited, preventing
any additional FAM write cycles until an active byte is
read from the FAM module.
Signals indicating the state of the RK-counter provide inputs to the TRL delay line (paragraph 4-41), the service
Table 4-3.
SWRITE
NTRS130 RKO (DeB SWRITE + ••. )
Operation of the RK-Counter
,-
NEXT STATE
PRESENT STATE
---
-
I
[~
=
If RREAD-4 Is True
If RWRITE-N4 Is True
RKO
RKl
RK2
RK3
RK4
RKO
RKl
RK2
RK3
RK-1
RKO
RKl
RK2
RK3
RK4
1
0
0
0
Q
0
1
1
1
1
1
0
0
0
1
0
0
0
1
1
0
0
0
0
1
0
0
1
0
1
0
0
1
0
1
0
0
0
1
1
0
0
1
1
1
0
0
1
1
1
0
0
1
0
1
0
1
0
0
1
0
1
0
l)
1
0
0
1
1
1
0
1
0
1
1
0
1
0
1
1
0
1
0
a
1
0
i
1
0
1
0
1
1
0
1
0
1
0
I
1
0
I
1
1
1
0
1
1
1
1
0
1
1
0
1
1
0
0
C
1
1
0
0
0
1
0
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
0
0
0
1
1
0
1
0
1
1
0
1
0
1
1
0
0
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
0
)
1
1
0
0
1
1
1
0
0
1
1
0
1
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
0
1
1
1
1
0
1
1
1
1
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
'.
I
,
I
(Inhibit-ed)
0
-
Notes
1. The number of active bytes in the FAM module is indicated by the ones complement of the RK-counter
state (1 1111 indicates 0 active bytes; 0 1111 indicates 16 active bytes)
2.
4-46
Initial state (l 1111) con be followed only by a FAM write cycle; a subsequent state (1 11 1"1) inhibits
the FAM read eye Ie
XDS 901565
If the RK-counter reaches state (1 1111) after bytes have
been written into the FAM module, all active bytes have
been read. Therefore, signal REMPTY becomes true, inhibiting the SREAD signal and preventing any additional
FAM read cycles until a byte is written into the FAM module.
SREAD
NTRS130 NREMPTY (DCB SREAD
-+ ••• )
REMPTY = RKO RKl
RK2 RK3 RK4
At the start of a data out service cyc Ie following an order
out service cycle, SCN is direct set. This action is caused
by SCR1 which is direct set during phase FS of the order out
service cycle.
NSCNMENl
=
S/SCR
RREAD-2 SCRSET
SCR5ET
NSCSI: r RK2 NRK3 NRK4
SCSET
WCHW RKl SCR + READ NRKl
RKl SCR
RKl SCR
SCRSET
c/sek
S/SCN
PH RSAOO
During a data out or a datI'} in servi ce cycle, SCR is clocked
by RKCK and changes stOlE" under control of RK -counter
signals.
RKCK
If the controller is exec~'h;1g a write order or a checkwrite
order (WCHW true), SCSE r is true unti! RK1 is reset, so
that SCRSET is false unti I RKl is reset. Therefore, SCR
\Ii II remain in the set state unti I the RK-counter is in state
(l 0100), indicating thc t 11 active bytes are in the FAM
module. If a FAM read c~'cle occurs at this time, RREAD...,2
wi \I come true and SCR v'; II remain in the set state as the
RK-c.ounter goes to stott;. (1 0101) to indicate that there
are 10 active bytes in t:"1C FAM module. If a FAM write
cycle occurs at this timE:, KREAD-2 wi II be false and SCR
will be reset as the RK-col.'nter goes to state (1 0011) to
ii1dicate that there are 12 acflve bytes in the FAM module.
If the controller is exec-'~;ng a read order (READ true),
SCSET is false until RKl i~ reset, so thatSCRSET becomes
true when the RK-counter is in state (1 1100), indicating
that there are three active bytes in the FAM module. If
a FAM read cycle occurs a~ this time, RREAD-2 wiil come
true and SCR will remair. i.1 the set state CIS the RK-counter
goes to state (l 1101) to indicate that there are two active
bytes in the FAM moduie. If a FAM write cycle occurs at
this time, RREAD-2 will be false and SCR will be reset as
the RK-counter goes to state (1 1011) to indicate that
there are four active bytes in the FAM module.
DATAOUT SCR + ••.
The input/output operation begins with at least three servic<:! cycles, causi~g 12 bytes to be written into the FAM
moclule before SCR is reset. Signal SCSET prevents reset of
SCt..~ during phase FSL, so that SCN is not reset until at
least seven active bytes are in the FAM module.
Flip-flop SCR is controlled by RK-counter signals, and in
turn controls service call flip-flop SC N and end data f! ipflop EDISET3. SCR is dirE:ct set during phase RSA of an
order out service cycle.
M/SCR
=
SCNEN
SCNEN
SCt..J DATA EXT SCSET
SCSET
WCHW RKl SCR + ...
Since SCN is not reset until phase FSL, an additional service cycle of four byl-es is in process and 12 bItes are writ-
te,.
After th~ initial service cycles, SCR is set whenever there
a:-e 11 active bytes in the FAM modu Ie (1 OJ Ou), and a
fAlv\ read cycle occurs. After SCR is set, SeN is set ago in
to request a service cycle. At the start of c data in service
cycle following an order out service cycle, SeN is in the
r(:set state. After four bytes have been writtt:!!1 into the
FAM module, SCR is reset and SCN is direct set.
NSCNMENl
SCNREN
READ RKID SCNREN
T
•••
NSCR + ...
Signal SCSET prevents reset of SCN during piuse FSL, so
tnot ~CN is not reset if there are eight or mOiE. active b},tes
La ~he FAM module.
S/SCN
SCNEN
SCNEN
SCN DATA EXT SCSET
SCSET
READ NRKl + ...
After the initia I service calls, additional by~es are written
into the FAM module. If a FAM read cycle takes place
\"Vh i1e there are three active bytes in the f/',M modu Ie
(1 1100), SCR is set, thereby inhibiting any service call
when there are less than four bytes in the F,t\M modu Ie.
For any other condition, SCR is reset and a sdvice call
rr•..:.y be requested.
An end service signa I is generated during phase RSA of a
data out service cyc leif SCR is reset (12 or more active
bytes in the FAM module).
S/EDISET3
NEDIS3
NSCR NEDIS3 +
PHRSADO (NRK3 ~- NBYTlID)
4-47
XDS 901565
Paragraphs 4-43 to 4-44
For a multiple-byte interface, this flip-flop is set after 12
active bytes are in the FAM module (i 0011)i for a singlebyte interface, this flip-flop is set after 14 active bytes
are in the FAM module (1 0001).
Signal JPXO goes false during a FAM write cycle just before
the new address is transferred from the l-register. Consequently,. the contents of the JP-register are 0000 before a
new address is stored.
4-43 J P-Reg ister
4-44 KP-Register
The J-pointer register (JP-register), which consists of buflered latches JPO through JP3, stores the address of the next
FAM location t9 be selected for writing data from the Jregister. During a FAM write c}'cle, the address stored in
the JP-register is placed in the L-register for addrefsing a
location in the FAM module and a new address is accepted
from outputs of the L-register. (See figure 4-14.)
The K-pointer register (KP-register), which consists of buffered latches KPO through KP3, stores the address of the
next FAM location to be selected for reading data into the
K-register (or I-register). During a FAM read cycle, the
address stored in the KP-register is placed in the l-register
for addressing a location in theFAM module, and Q new
address is accepted from outputs of the L-register. (See
figure 4-
During phase RSA of an order out service cycle, the address
1111 is stored in the JP-register. Therefore, the first FAM
location addressed for writing is <1 I ways location 1111.
is. )
During phase RSA of an order out service cycle, the address
11 i 1 is stvred in the KP-register. Therefore, the first FAM
location ~ddressed for writing is always location 1111.
PHRSAOO + ..•
JPO
PHRSAOO + .••
KPO
PHRSAOO
PHRSA ORDOUT
PHRSAOO
JP1
PHRSAOO +
JP2
PHRSAOO +
JP3
PHRSAOO +
During a FAM write cyc Ie, thelr.cremented value from the
L-re:gister output signnls is stored in the JP-'ie8ister. Refer
to paragraph 4-4.5 for .-:>pemtior; oT ~he L-register.
KPl
PHRSAOO +
KP2
PHRSAOO +
KP3
PHRSAOO +
During rt FAM read cycle,' the incrementp.d value from the
l-regislp.r output signals are stored in The KP-regis~er. Refer
to paragrotlh 4·-45 for operation of the L-register.
JPXL LEO + .••
JPO
KPXL LEO + •••
KPO
JPXL
RWRITE-2 TRSL70 NTRSOOO
"PXL
JPl
JPXL LEl +
JP2
JPXL LE2 +
JP3
JPXL NL03 + •••
An address stored in the JP-register during a FAM write
cycle is retained whi Ie signal JPXO is true.
JPO JPXO +
JPO
JPXO
RWRITE-2
.••
RREAD-2 TRS270 NTRSOOO
KP1
KPXL LEI +
KP2
KPXL LE2 +
KP3
KPXL NL03 + ••.
An address stored in the KP-register during a FAM read
cycle is retained while signal KPXO is true.
KPO KPXO + ..•
KPO
N(RWRITE-2 TR180)
KPXO
N(SREAD WCHW) (SWRITE TRS030
~READ-2
N(RREAD-2 TRS180)
N(READ SWRITE) (SREAD TRS030
+ RREAD-2 NTRSOOO)
+ R\VRITE-2 NTRSOOO)
4-48
PHRSA ORDOUT
JPl
JPl JPXO +
KPl
KPl KPXO +
JP2
JP2 JPXO +
KP2
KP2 KPXO +
JP3
JP3 JPXO +
KP3
KP3 KPXO +
XDS 901565
L
_ _ _JL
U--
,__---.In. . .___
600
I
!
NOTES:
1. CONTENTS OF L02 AND L03 CLEARED BY NTRS030
2. RK-COUNTER INCREMENTED BY TPS 130
3. DATA TRANSFERRED FROM J-REGISTER TO ADDRESSED LOCATION
IN FAM MODULE BY FAM \fv'RITE CLOCK
4. JFl LATCHED UNTIL JflRESET TRUE
901641A.304
Figure 4-14.
Sequence of FAM Write Cycles, Timing Diagram
4-47
XDS 901565
KFI
I~----------_--~I
CYCLER
Jl"---____-----In'--_____-II
SREAD
-.l
RREAD-l
~
RREAD-2
--.l
L
~--------~~~--------
L
r
l02
l03
I
!
CD~
KP2
KP3
KPXl
------u--
u
KPXO
KXR
JL
________~L__
_ _ _1L-___---'nL-_.
0
200
~____~I,_____
I
.t!OO
600
J,____~I_
TiME IN NS
NOTES:
i. CONTENTS OF L02 AND L03 CLEARED BY NTRS030
2. RK-COUNTER INCREMENTED BY TRS13C'
3. DATA TRANSFERRED FROM ADDRESSEC' LOCATION IN
FAM MODULE TO K-REGISTER (OR
I-R~GISTER)
BY KXR
4. KFI FALSE UNTIL KFISET TRUE, GENERATING KFIXl
90l641A_ 305
Figure 4-15.
4-50
Sequence of FAM Read Cycles, Timing Diagram
XDS 901565
Signal KPXO goes false during a FAM read cycle just before
the new address is transferred from the L-register, so that
the contents of the KP-registerare 0000 before a new address is stored.
Signal RWRITE-l is latched until a data byte is stored in
the addressed FAM location, and an incremented address
is stored in the JP-register. (See figure 4-13.)
JPO RWRITE-l + ••.
lOO
4-45 L-Register
During a FAM write cycle, the contents of the JP-register
are stored in the l-register whi Ie signal RWRITE-l is true.
Table 4-4.
N(READ WCHW) (SWRITE TRS030
+ RWRITE-l NTRSCOO) NTRS130
RWRITE-l
The L-register consists of b'Jffered latches LOO through L03
and buffered latch Nl03 whi~h stores the bit complementary
to the bit stored in L03. The L-register provides a fourbit address input to the FAM module during either a FAM
read cycle or a FAM write eyde. Outputs of the L-register
provide inputs to the KP-register or to the JP-register and
store an incremented address in these registers, as summarized in table 4-4. Refei to paragraph 4-43 for operation
of the JP-register and to paragraph 4-44 for operation of
the KP-register.
LOl
JPl RWRITE-l +
L02
JP2 RWRITE-l +
L03
JP3 R\VRITE-l +
NL03
NJP3 RWRITE-l + •..
During a FAM read cyele, the contents of the KP-register
arz stored in the L-register while signal RREAD-l is true.
Relation Between State ane..: Output of the L-Register
-
STATE
SIGNALS
OUTPUT TO JP-REG ISTER
OR KP-REGISTER
LOO
LOl
L02
L03
LEO
L;:1
lE2
L23
L123
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
1 0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
0
1 0
v
0
1
0
0
0
1
0
0
0
0
1
0
1
0
1
0
1
0
1
1
0
0
0
1
1 0
0
1
1
0
0
1
1
0
0
0
1
1
1
0
1
1
1
1
0
0
1
1
1
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
1
0
0
1
0
1 0
1
0
1
0
1
0
1
0
0
1
0
1
1
.1
0
1
1
1
1
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
1
0
l
1
1
0
1
1
1
1
0
0
1
1
1 0
1
1
1
0
1
1
1
0
0
1
1
1 1
1
1
1
1
0
0
0
1
1
0
0
0
1
0
4-51
Paragraphs 4-46 to 4-47
XDS 901565
Signal RREAD-l is latched unti I a data byte is read from
the addressed FAM location and an incremented address is
stored in the KP-register. (See figure 4-14.)
KPO RREAD-l + •••
lOO
RREAD-l
N(READ SWRITE) (SREAD TRS030
+ RREAD-2 NTRSOOO) NTRS130
the J-register, the FAM modu Ie, the K .;.register, and the
D-register to the addressed selection unit. For a write
sequence, data transfers from the FAM module to the Kregister have priority over data transfers from the J -register
to the FAM modu Ie. This priority assures that the D-register
will have data for transfer to the seledion unit.
Data transfer from the lOP is controlled by the phase control circuit as described in paragraph 4-20. Data from the
lOP is requested curing phase RSA. As the lOP responds,
the TCL delay line is starteQ, lOP data is stored in the 1register, and phase RS is entered.
lO1
KPl RREAD-l +
l02
KP2 RREAD-l +
l03
KP3 RREAD-l +
DCl
CYCLE/C PHRSA RSAU + .••
Nl03
NKP3 RREAD-l + •••
IXD
PHRSADO TC5000-3
The incremented value of the input to the l-register is
,..,pnerated by a set of exclusive ORgates for the most signiflt bits of the address.
.
•
New data cannot be requested unti I phase RSA. is entered
from phase RS. Th is change of phase cannot occur ul1 t j I a II
previously accepted data has been transferred to the FAM
module and 1·he J-register is empty (JFI false).
l E C ( l O O + 1123) N(LOO L123)
DCL
1123
lO1 L23
l23
l02 L03
lEl
(lOl + l23) N(L01 l23)
lE2
(L02 + L03) N(L02 L03)
CYCLE/C DCL5TART2 NRSAU
+ ...
OClSTART2
=
WCHW PHR5 NJFI +
The J-register is cleared after its contents have beeil transferred to th~ FAM module.
NJXa = PHRSDO TC5000-1
Ouring a FAM wri te cycle, the incremented address is
placed in the J P-register; durinu a FAM read cyc Ie, the
incremented address is placed in the KP·-register.
The L-register is cleared 30 ns ofter starting the TRL delay
line, so the address from the KP~register or JP-register can
be read at address outputs LOO tr.rough L03 and NL03.
lOO
LOO NTRS030 +
L01
L01 NT RS030 +
l02
L02 NT RS030 +
l03
l03 NTRS030 +
NL03
NL03 NTRS030 + •••
After the L-register is cleared b} dgnal NTRS030 and is
loaded as previously described, signal NTRS030 acts as a
latch control until a new value i~ loaded.
Data tralisfers from the FAM circuits to the selection unit
are controlled by the selection unit ;:1terface circuits as
described in paragraph 4-53. Data !rc!Osfers from the FAM
moclu Ie toihe K-register are controll~d by the TRL dr lay
line. Data transfers from rhe K-register to the D-reg-ster
take pic..:e: 01- eight-bit interva Is uni-j I the postamb!c is
written (POST true).
DXK -
WRITE NPU5T SIT7RWE + ••.
The fundion of the FAMcircuits is to process data tror.sfers
between the lOP and the addressed se lection unit, providing
data to the se lectio'1 unit at the requ ired rate for on IOPte-controller interface of one byte, two bytes, or four ~'ytes.
4-47 ONE:BYTE INTERFACE. For a one-byte interface
with the lOP, signal BYTl 1D is true, the byte counte:- is
4-46 Operotion ofFAM Circuits During the Write Sequence
not used, und the data path from the lOP is through the
most significant byte of the I-register (IDO-I07) to the Jregister, then to the addressed location in the FAM module.
(See figurE' 4-11. )
Wli Ie the controller is executing a write order ora checkr.write order, data is transferred from the I-register to the
'D-register through the FAM circuits. (See figure 4-11.)
Data accepted from the lOP passes through the I-register,
When lOP data is first stored in the I-register, signal JFI
is false. Therefore, the data is transferred to the J-register
as the Tel de lay line is started during phase RS, and JFI
is raised and latched at the true level.
4-52
XDS 901565
JXIl B
lOP BYTlID PHRSDO TCSOOO-2
SREAD
(CYCLER NTRSOOO NKFI SREADEN
+ •.. ) NTRS130 NREMPTY
JFI
N(JFIRESET RWRITE-2 TRS180)(JFlXl
+ JFI NPHRSAOO + •.• )
JFIXl
=
PHRSDO TCSOOO-2
The controller can accept data from the lOP but cannot
start the TCl delay line during phase RS until JFI is false.
The TRl delay line is started by JFI through signal SWRITE.
SREADEN
=
NPOST NRWE NRWP NWPRE
When data is first stored in the FAM module, signal KFI is
false. Therefore, the data is transferr,ed to the K-register
as soon as the preamble has been written because FAMread
cycles have priority over FAM write cycies.
KXO
KFI
(KFIXl + KFI NPHRSAOO)
KFIX 1 = KFISET RREAD-2 TRS 180
SWRITE = (CYCLER JFI NTRSOOO
+ ••. ) NTRS130 RKO
During the FAM write cycle that is started by this signal,
the following events take place:
a.
The l-register is cleared.
b. The contents of the jP-register are read through
outputs of the l-register tu tl,e FAM module.
c. The contents of thO:' J-register are transferred in
parallel to the FAM moduic location addressed by the L~
register outputs.
During the FAM read cycle that is started by thb signal,
the following events toke place:
The L -register is cleared.
a.
b. The contents of the KP-register are read through
outputs of the L-register to the FAM module.
c.The contents of the FAM module location addressed
by the L-register outputs are transferred to the ;~-register
(or the I-register).
d. The incremented value of the contents of the KPre9:st:)r is read from the L-regisier outpul-s into the KPregister.
~.
The RK-counter is incicme:lted.
d. The decremer,ted value of the contents of the JPregister is reaa from the L-register outputs into the JPregister.
e.
The RK-counter
jc:
These events are controlled by the following cquations:
LOO
KPO RREAD-l +
KPXL
RREAD-2 T~~S270 NTRSGOC
KPXO
i'J(RREAD-~
KXR
KXREN RREAD-2 TRS180
decremented.
T~:!se events are control kJ by the following equations:
LOO
LOO NT RS030 + •.•
JPXO
N(RWRITE-2 TRS180)
(FAM write Clock)
RWRITE-2 TRS180
JPXL
RWRITE-2 TRS270 NTRSOOO
RKCK
N (TRS 130 + ..• )
RWRITE-N4
RVVRITE-2 NRK4
KXREN
Signal JFI goes false as thc contents of the J-register are
stored in the FAM module and a transfer from phase RS to
phase RSA is enabled.
JFI = N(JFIRESET RWRITE-2 TRS180)
(JFI NPHRSAOO + ••. )
Data may be accepted from the lOP until the FAM modu Ie
is filled. FAM read cycles transfer data from the FAM
module to the K-register after the preamble has been written, enabling the T RL de lay line to be started by an SREAD
signal.
TRS180)
eKZZ + .••
~KCK
N(TRS130
RREAD-4
RREAD-2 RK4
1-
••• )
Signal KFI is raised and latched as the contents of the FAM
module are transferred to the K-register. Signal KFI remGins true until the K-regis~er is cleared fol:0wing transfer
of its contents to the D-register.
NKXO
= WCHW
TDT2 + •.•
This sequence of acceptance of data from the iOP, transfer
of data to the FAM module, and. reading data from the Fl~.M
modlJle to the selection unit continues under mutual conirol
of phase control circuits, FAM circuits, and s€'lection unit
inte.face circuits. When the FAM module is filied, requests
for lOP data are inhibited because flip-flops RKO is reset,
inhibiting FAM write cycles, and JfI is held true, inhibiting
transfer from phase RS to phase RSA. When the FAM module
4-53
Paragraph 4-48
XDS 901565
is empty, FAM read cycles are inhibited because signal
REMPTY is true. Anyattempt to write into the FAM module
when it is full or to read from the FAM module when it is
empty causes a rate eriOr, as described in paragraph 4-78.
4-48 MULTIPLE-BYTE INTERFACE. For a two- orfour-byte
j"nterface with the lOP, signal NBYT1ID is true, the byte
counter is used to control data transfer from the I-register
( to the J-register, and the data path from the lOP is to the
I-register, to the most significant byte of the I-register
(100-107), to the J -regi ster, then to the addressed location
in the FAM module. (See figure 4-11.) The rest of the
paragraph emphasizes the differences between write operations for a one-by"te interface and for a multiple-byte interface.
When lOP data is stored in the i-register, signal JFIXl
comes true and causes JFI to bp. ioised and latched similar
" a one-byte sequence. Howe\-er, JFI remains latched
il all bytes accepted from th~ lOP have been transferred
•
to the J -reg ister. Data transfer I rom the I -reg ister is controlled by timing signals of the ~ RL delay line (instead of
the TCl delay lir.c). Data tran::;fers take place within the
,I-register so that a II transfers frc:il the J -register are from
the P10st significant larches of the I-register (100-107). The
mu Itiple-byte interface dota pa+-h from the J -register through
the FAM circuits tG the D-regi~ter is identical to the onebyte interface data path.
Signal JFI remair.s latched at th"~ true level following aco:e?tance of lOP data because u false JFIRESET signal takes
control from signal JFIX1. Oncp. JFI is raised by JFIX1,
JFI remains latched until JFIRESET is true during a FAM
write cyc Ie.
JrI
N(JFIkCET RWRITE-2 TRS180)
(JFIXl T JFI NPHRSAOO
For a two-byte interface, two FAM write cycles take place
before signal JFI goes false to enable a tran5fer to phase
RSA to request additional data from the lOP. During the
first FAM write cycle, data is transferred from latches (100107) of the !-register to the J -register, the contents of (108115) are transferred to (100-107), and the byte counter goes
to state (1, 0) so that signa I BKZ W is true.
JXINl B
NBYTl ID lOP DAT AOUT RWRITE-2
TRS060
IX~-l
IXEN RYIRITEDO BKZZ
IXEN
hlBYTl ID TRL180 NTRL240
During the second FAM write cycle, data is transferred
from latches (100-107) of the I-register to the J-register as
before. However, since JFIRESET is now tme, JF! goes
false during the FAM write cycle .
For a four-byte interface, fOUl FAM write cycles take place
before s:9nal JFI goes false to enable a transfer to phase
RSA to request additional data from the lOP. Duri ng the
first FAM write cye! e, data is transferred as for the twobyte interface. During the second FAM write cycle, data
is tram;ferred from latches (100-107) of the I-registe.- to the
J -register, the contents of (116-123) are transferred to (l00107), and the byte counter goes from state (1, 0) to state
(0, 1) so that signal BKVVZ is true.
IXI-2 = IXEN R\'v'RITEDO BKZW
During thE'! third FAM write cycle t data is transfen ed from
latche~ (100-107) of the I-register to the J -registef, the
contents 0f (124-131) are transferred to (IOO-107), end the
byte counter goes from state (Of 1) to state (0, 0) so that
signal &KWW is true.
+ .•. )
IX:-3
JFIX1
PHRSDO TCSOOO-2
NJFIRESET
\VCHVv NSYTl ID BKl (T wo- and
four-byte
interface)
+ WCHW BYT4ID BKO (Four-byte
interface)
The byte counter (SKO, BK1) js direct set to state (1, 1)
each time JFIXl is true and ck-:ked during each FAMwrite
cycle. (Sec paragraph 4-33. )
BKXl
NBKXl EN
NBKCK
BKCKEN
4-54
NBKX1EN + ...
WCHW JFIXl +
BKC KEN TRS270
=-=
IXEN RWRITEDO BK\VZ
During The fourth FAM writp. cycle, data is transfelr(d from
latches (100-107) of the I-register to the J-regisrer w. before.
However. since JFIRESET is now true, JFI goes faLe during
the FAM write cycle. Therefore, for Q multiple-byte interface, the phase control circuits cannot request additional
data from the lOP until previously accepter' dato has been
written into the FAM module. However, FAM reo0 cycles
may occ:.Jr during this interval to maintain the data rate to
the addressed selection unit. For u multiple-bytei:ilerface,
data tran:fer from the FAM module to the K-registcr is enabled by a false READRR signal (instead of a true BKZZ
signa I).
KXR
+ .••
NBYTl ID(WCHW RWRITE-l + .•. )
KXREN RREAD-2 TRS180
KXREN
NREADRR + BKZZ
READRR
READ RREAD-2
Paragraphs 4-49 to 4-50
XDS 901565
4-49 Operation of FAM Circuits During the Read Sequence
DCl
CYClE/C DClSTART2 NRSAU
+ •••
While the controller is ~xecuting a read order, data is
transferred from the D-register to the O-register through
the FAM circuits. (See figure 4-11.) Data accepted from
the selection unit passes through the D-register, the Jregister, the fAM module, the K-register (or the 1register), and the a-register, to the lOP. For a read
sequence, data transfers from the J -register to the FAM
module have piiority over dat~ transfers from the FAM
module to the K -register (or to the I-register). This priority
order assures that a data in the D-register wi II be stored in
the FAM module as it comes from the selection unit.
Data transfer from the selection unit is controlled by the
selection unit interface circ~its as described in paragraph
4 -53. Fo Iiowl ng detect i on of the preamb Ie, data bytes
ore transferred from the D-register to the J-register ateightbit intervals a::; described ir. paragraph 4-54.
JXD = READ NPRE j DT2
A FAM wr!~e cycle is encbled each time signal JXD comes
true.
SWRlTE
{CYCLE? iFI N'fRSOOO + ... }
NTRS130 NRKO
DCLSTART2
=
PHRS READ KFID + ...
The function of the FAM circuits during a read sequence is
to control data transfers from the FAM module to the Kregister {or K-register and I-register} so that data may bf!
stored in the a-register for transfer to the lOP on a one-,
two-, or four-byte interface.
4-50 ONE-BYTE INTERFACE. For a one-byte interface
vlith the lOP, signa I BYTl ID is true, the byte counter is
flot used, and the data path from the addressed location in
tht.: fAM moou Ie is first to i"he K-register then to the most
~:gnificant latches of the 0 -register (OOO-OO?). (See
figure 4-11.)
tach time selection unit data is transferred from the Dregister to the J -register, signa I JFI is raised end latched.
The TRL delay ,line is started, and since a FAM write cycle
h'Js priority over a FAM read cycle, a FAM write cycle
takes place.
[Juring the FAM write cycle that is stmted by this signal,
the following events take piece:
o. The l-register is cleared.
JFI
N(JFIRES[T RWRITE-2 TRS180)(JXD
+ JFI t~PriRSAOO + .•• )
FP-.M read .::ycles are ali()wed after read/write enable flipflop RWE is set, as descrlbp.d in paragraph 4-62.
SREAD
(~k'::ADEN NKFI CYCLER
,\,FRSOOO + READ f'~KFI CYCLER
N :'RSOOO + .•. ) NREMPTY
N-:-RS 180
b. The contents of the jP-r€.gister are read through
outputs of the L-register to the FAM module.
c. The contents of the j -register are t. ar!sferred in
pa:-allel to the FAM module location addres~ed by the Lregister outputs.
d. The decremented value vf the conf"ent: of the J Pr8gister is read from the l-register outpur:> into the JPr~gister •
SREADEN = Nr05T RWE NRWP NWPRE
e.
While the phase control .:1rcuits are in phase R5A, the lOP
accepts data stored in tl->E: 0 ~register and enables a transfer
to phase RS.
The RK-counter is decremented.
These events are controlled by the following equations:
lOO
lOO NT RS030 + ...
JPXO
N(RWRITi:-2 TRS180)
(FAM write clock)
RWRITE-2 TRS180
JPXl
RWRITE-2 TRS270 NTRSOOO
RKCK
N(TRS130 ;- .•• )
RWRITE-N4
RWRITE-2 NRK4
DCl = CYClE/C PHR5A RSAU + •••
Un less end data signa I ED is true, new data is transferred from
the K-register (or from t~c K-register and the I-register)
into the a-register whi:e the phase control circuits ar~ in
phase RS.
OXK
OXKEN
OXKEN TC5000-2
PHR5 DATAIN NED
However, the Tel delay line cannot be started to permit
this data until additional data has been stored in the Kregister (or K -register and I -register) as indicated by a
true KFID signal.
Signa I JFI goes fa Ise as the contents of the J -register are
stored in the FAM modu Ie. When data is first stored in the
FAM module, signal KFI is folse. iherefore, the aata can
4-55
Paragraph 4-51
XDS 901565
be transferred to the K-register any time after a false REMPTY
signal indicates that data is available, provided that no
FAM write cycle takes priority.
SREAD
(CYCLER NTRSOOO NFKI READ
+ ••. ) NTRS130 NREMPTY
KFI
KXO (KFIXl + KFI NPHRSAOO)
KFIX1
KFISET RREAD-2 TRS180
During the FAM read cycle that is started by this si~nal,
the following events take place:
o. The L-register is clearccl.
b. The contents of the KP-register are read thiOugh
outputs of the L-register to the FAM module.
_
c. The contents of the FAM module location addressed
""the L-register outputs are transferred to the K-register
(or the I-register).
d. The incremented value of the contents of the KPregister is read from the L~register outputs into the KPregister.
e.
The RK-counter is incremented.
These events are controlled by the following equations:
LOO
LOO NTRS03C +
lOO
KPO RREAD-l +
KPXL
RREAD-2 TR3270 NTRSOOO
KPXO
N(RREAD-z TRS180)
RKCK
N (T RS 130
RREAD-4
RREAD-2 RK4
KXR
KXREN RRU\.D-2 TRS J 80
KXREN
J.-
••• )
BK1Z + ..•
Signal KFIisraised and latched as the contents of the FAM
module are tran::Jerred to the K-re8ister and KFI remains
true until the K-register is cleared following the transfer
of its contents to the O-register.
NKXO
KXOEN + ..•
4-51 MULTIPLE-BYTE INTERFACE. For a two- or fourbyte interface with the lOP, signal NBYTl ID is true, the
byte cou:,ter is used to control data transfer from the ~d
dressed kcution in the FAM module to the K-register and
I-register, and the data path from the FAM module to the
o -regisi£( is through the K -register and lower-order iatches
of the I-register. (See figure 4-11.) This paragraph emphasizes the differences between a rend $;quence f0;- :l onebyte inteitace and for u multiple-byte interface.
'lvhen seiection unit data is stored in the J-register .. signal
JXD cornes true and causes JFI to be raised ar.d latched as
for a one--byte sequence. Dolo transfers from the j --register
to the FA."", modu Ie take place under control of signal JXD.
FAM write cycles and FAM read cycles cause the saii.e se..;.
quence of events as for a one-byte interface. However,
signa I KFiD cannot come true unti I sufficient data b~,tes
have bee:' stored in the K-register and I-registero
The byte r.~unier (SKO, BKl) is direct set to state (!, 1) by
sjgnal BKXl ear:h time signt:1 K.XOEN j<: true. At i~is time,
data is tH.'lrt:;ferred to the O--regist'.;r from the K-rec:isterand
I-register; both of which are then cleared. Refer to paragraphs 4-:3, 4-37, 4-38, and 4-57 for detai Is.
KXOEN +
BKX1
NBKXl EN + .•.
READ KXOEN + •.•
Once si~l)al SREADEN is true, FAlV\ reatl cycles, cO:1trolled
primarily by signal KFI, may take place whenever the FAM
module contains data bytes. Signals RREAD-l and RREAD-2,
wh ich c0n;r01 the priority of FAM read eyc les over'; AM
write c),.:;ies, become true during a FAM read cycie. Data
transfers ')ccur as described for a one-b}'te interface. As
the byte c~unter is clocked, it passes from state (1, !) to
(1, 0) to (a, 1) to (0, 0), as required.
NBKCK
BKCKEN TRS270 + .••
KXOEN
OXKEN TCS100-3
PKCKEN
NBYT1ID (READRR RREAD-l + ..• )
OXKEN
PHRS DATAIN NED
READRR
READ RREAD-2
This sequence of accepting data from the addressed selection
unit, transfe~ring data to the FAM module, and reading
4-56
data from the FAM module into the O-register for transfer
to the lOP continues under mutual control of phase control
circuits, FAM circuits, and selection unit interface circuits.
Data transfer to the lOP must continue at a high enough
rate so that there is always space in the FA/v\ modu Ie for
new dote; which is accepted at a constant rate. Request
strobes for the 10 P cannot be generated un less there is data
avai lable for transfer. Any attempt to vvrite into a full
FAM modu!e or to read from the FAM modu Ie when H has
insufficient data causes a rate error as described in paragraph 4-78.
For a two-byte interface, two FAM read cycles must take
place before signal KFID goes true. 'M1en true, KFID
XD5901565
enables a transfer to phase RSA and enables a request for
the lOP to accept data that has been stored in the a-register. During the first FAM read cycle, data is transferred
from the addressed location in the FAM module to the Kregister, and the byte counter goes to state (1, 0) so that
signal BKZW becomes true.
KXR
KXREN RREAD-2 TRS180
SKZZ + •••
KXREN
Signal KFi does not latch true because signal KFIXl is held
false by a false KFI5ET signal.
KXO (K!=IXl + KFI NPHRSAOO)
KFI
KFIXl
KFISET RREAD-2 TRS180
NKFISET
READRR NBYTl ID BKl
+ READRR BYT4ID BKO
During the second FAM reae! cycle, data is transferred from
the addressed location in the rAM module to the I-register
latc!1es 107 throt:gh 115, and the bite counter goes to state
(0, 1).
IXR-l
IXEN REAORR BKZW
NBYTi n; TRU80 NTRl240
IXEN
Signal KFI latches during th(~ second FAM read cycle because KFISET is true. (BK1 is fv.lse, and BYT 41D is false. )
Beccuse KFI latches, KFID 0.oes true and is latched unti I
the data transfer is made to the a-register.
During this FP.M read cycle', KFISET is true, KFI latches,
and KFID is latched until the data transfer to the 0 -reg ister
is made. When the data transfer is made, the byte counter
is -set to state (1, 1).
4-52 Operation of the TRL Delay Line for a Seek Order
During execution of a seek order, the contents of th~ 1register must be transferred to the J -register, and the contents of the J -register must be transferred to the T -register
or 5-fegister in two suc.;essive data out service cycles.
Data transfer from the lOP is controlled by the phose control
circuits as described in paragraph 4-20. Data from the lOP
is requested during phase RSA. As the lOP responds, the
TCldelay line is started, lOP data is stored in the I-register,
the byte counter goes from state (1, 1) to state (l, 0), and
phasp. RS is entered.
Del
CYClE/C PHRSA RSAU + .• ,
NBKCK
PHRSA 5EKSEND TC5000-3
IX!)
PHRSADO TCSOOO-3
New data is accepted after phaSE> RSA is enterc.d from phase
RS. T:lis chC1nge of phase is enabied ;mmediate I, after phase
RS is entered, if the request strobe cckr.owled~e signal is
false.
PCl
CYClF./C [)ClSTP.Ri·2 NRSAU
+ .••
DCl5TART2
PHR5 SFKSEND +
SEKSEND
SEEK f'IPHRSAOO + ' ••
KXO (rU
SEEK
SXJ
SEEK RWRITEOO .BKWZ TRS130
.53"
BKWZ TRS130
SELECTION UNIT INTERFACE CIRCUITS
" The selection unit interface cirr.uits control exchange of
signals between the controller (md the selection units. \\hen
the coptrol/er is executing an order, en 11 -bit track address
lis sent to the addressed selectk:n unit during intersector gap
time. (Two bits of the 11 -bit address should always be zeros. )
Angular position signals from the selection unit identify the
sector under the read/write heads. When the angu lar position signals match the sector address register signals, data
transfer can begin. Data is writhn on the addressed track
for a valid write c:"d€r; data is rCGd from the ar/dressed track
for a valid read order or checkv,.rite order.
Ouring execution of a write orde ..; bits me written on the
track by the Mcnchester encodir,g method, using the cbck
signals of (j 3-MHL oscillator k, the controller. A counter
controls the shifting of the treci-: address and the writing
of the five --byte preOinble, the i 024 dota bytes, the twobyte checksum, and the single '"lyte of zeros. Thefivete preamble is generpted at ~nputs to the K-register. The
• _:fa bytes are accepted from the FAM circuits into the Kregister. Data from the K-register is transferred to the 0register in parallel and is shifted in series from the D-register
to the selection unit. After all data bytes have been written, zeros are stored in the K-reg ister (i f necessary) to
complete 1024 data bytes per sector, then the two-byte"
checksum is transferred from the P-register to the K-register.
After the checksum is written, \.A byte of zeros is writter.
before the read/write heads are disabled.
During execution of a read order, clocking is initiallycontrolled bytheoscil!atorinthecola:roller. Duringthis initial
period, the addressed selection unit deve lops a clock signal from the Manchester-encoded data. After an interval
established by logic circuits, cicek control is transfened
to a data strobe clock signal developed in the addressed
"t selection unit. When the preamble synchronization pattern
is detected, the data is accepted serially in eight-bit bytes
into the 0 -register and is transferred in para lie I to the
4-58
J-register.From the J-register, the data passes to the FAM
circuits. After the 1024 data bytes have been read, the twobyte checksum read from the addressed selection unit is compared with a checksum developed during execution or the
reed order. After the checksum comparison is made, no
additional data is accepted from the addressed selection unit.
During execution of a checkwrite order, clocking is initially
controlled by the esc i lIator in the controller, then by the
data strobe clock. The preamble synchronization pattern
indicate;; the start of data, as for a read order. Data from
the lOP is moved as for as the D-register. "As lOP dota is
shifted serially from the D-register, the data is compared
with data accepted from the addressed selection unit. This
comparison is made for 1024 data bytes and for the twobyte checksum developed by controller logic. Tlws, the
checkwrite order involves operations simi lar to tho~e for
execution of Q write order (but does not include wri~ing
date) and inciudes operations simi lar to those for ex~(:ution
of a read order (but does not include transferring data to
the IO?).
4-54 TDL Delay Line
The TDL delay line, which inciudes control flip-fiop TDT
and Qsso.::ated logic el~ments, generates tiniingsig"als to
enable data transfer in the se lection un it interface circuits.
(See figure 4-16.)
Whenever flip-flop TOT is set t t-he TOt delay line :;;started.
After 40 ns, TDT is direct reset. After 60 ns,. the ir.put to
the delay line is inhibited, so a new cycle cannot be started
until th~ previous pulse has passed.
TOLOOO
TDTSET NTDL060
TDL040
The defey line provides pu Ises of nOlalinal 40-n5 durc:ion at
intervals cf 20, 40, 60, 80, and 100 ns. Signa I 10Tl is
equivalent to TDL020; signal TDT2 is eqt;ivalent to TOL080.
Fi ip-flop TDT, which is clocked by read/write c IC'{.!.: signal
RWCK, i:. set wherl..;ver TDTSET is true and is rese~ whenever
TOTSET is false.
S/fDT
TDT$ET
R/TDT
C/TDr
ROCK
Signal TDTSET is controlled by signal~ generated b}' the Bcounter and by the selection unit interface logic. [\Jring
execution of a write order, signal TDTSET comes true at
eight-bit interva Is to enable the transfer from the K-register
to the O-register of the five-byte prearr.b!e, the 1024 data
bytes, and the two-byte postamble.
BlT7RWE _f_6
NPOST 27
NPRE 25
8A
STXPEN
NTDTSETl
44-
17C
TXP
BIT7RWE
SXP
BIT7RWE
NPOST
WRITE
"T1
c.::;'
c""I
(I)
~
TDT2
~
?'
TDL060
BIT7RWE
-I
0
CHWR
0
NPOST
NPRE
r
CD
C
"'<
r
TDL040
TDL.020
:J
CHWR
10
PSPR
11
-0
3
6A
r
0
(Q
o·
01
001
0
::J
0-
TDT
~
3
::l
<.0
TDLOOO
0
o·
<.0
n
TD:"020
""I
0
3
I
I
n
I,
TDL040
TDL060
,
J
I
I
TDL080
TDLlOO ....: _ _ _ _ _ _
-0
8
v.
u,
0
40
..-:-1-;
80
0-
~
I
U't
"-0
x
CJ
VI
!!
~
Ton
t'-J
TIME IN NS
120
XDS 901565
Paragraphs 4-55 to 4-56
DXK + •..
4-55 Interface Clocking
DXK
WRITE NPOST BIT7RWE + .•.
BIT7RWE
Bl0 Bl1 B12 R'A-1:
The clock signals controlling the se lection unit interface
circuits ore controlled by an internal 3-MHz osci Ilator having an output signal designated ClK3MH, flip-flops DSE
and ClK, and control signals EXT and DSR. The read/write
clock signal, which is designated RVvCK, is generated by
four identical circuits.
TDTSET
During execution of a read order, no transfer of data from
the K-register to the D-register takes place, and the preamble synchronization pattern is used to identify the start
lof the dota bytes. Once the data bytes are available, the
TDl delay line is started at eight-bit intervals to enable a
transferof data from thc D-register to thE: J-regis1-er.
= ClK3MH
RWCK
BIT7RVv'E NPOST NPRE -I- •••
TDTSETl
clock, not extended performance)
+ClK3MH
EXT NDSE
(3.0 MHz write
clock, extel'"lded
performance)
;:::: NPRE READ TDT2
-I-
·n g execution of a checkwrite ordert transfer of data
•
the K-register to the D-register takes place, and the
preamble synchronization patten'\ is used to identify the
start of the data bytes. When the preamble synchronization
pattcrn is recognized (PSPR true), the ~ext bit received
from the seleciion unit will be the first data bit. Therefore,
the TDl delay line is started to enable the first data byte
received from the lOP {and in the K-register}to be transferred to the D-regi5~er and compared bit by bit with the
first data byte received from the selection unit.
DXK + .••
TDTSET
DXK
CHWR fSPR -I- •••
PSPR
NDAR NDOO 001 D02 PSPBREND
PSPBREND
PSPB R[ND
PSPB
B07 B08 PRt RvVE
REND
RWE RCHW
(1.5 MHz wrae
NEXT ClK
TDTSETl + ••.
TDTSET
JXD
(RWCK-l -RWCK-4) = RWCK
DSE DSR
(Read clock)
Durinc! execution of any order, i-he read/write clOCK is
generated by rhe interna I clock of the stort of a sectvr.
During th:s period, the controller is either writing the preamble or counting locally generated clocks in a search for
the prear:-;b!e synchronization patl-em.
RWCK
=
CLK3MH EXT NDSE -I-
For a wri!-~ order, thh: equation generates the read/.;dte
clock thloughout the sector. For a read order, the read/
write clock is controllpd by the selection unit date. .)t~obe
after DSE ;s set, as described in paragraph 4-59.
DSE DSR + •••
R'NCK
IDS/
liSR
Vvhen signal EXT i!; false (as described in paragraph 4-82),
the read/write clock frequency is reouced by a factC'_ c f
two, USi,lg flip-flop ClK as a frequency divider.
C LK3MH NEXT ClK + •..
Subsequent data bytes from the lOP are transferred from the
K-register to the D-register at eight-bit intervals.
TDTSET
DXK
DXK
+ ..•
CHWR NPOST NPRE BIT7RWC -I- •••
For either read orders t write orclc"s, or checkwrite orders,
the Tul delay line is started at eight-bit !nter\!als while
flip-flops RWP and RWE are in the set state.
TDTSETl
4-60
TDTSETl -I- •••
RWP BIT7RWE
NC.. K NDSE
RjCLK
Data bytes are received until po.. ~amble time (POST false).
TDTSET
S/CL;~
-I-
CjClK
CLK3MH
Vvhen control of the read/write clock is transferred ~o the
data strobe, the reduced frequenc)' c lock is iead from the
signal as for an EP RAD selection unit.
4-56 B-Counter
The bit and byte counter {B-counter} cons.ists of flip-flops
BOO through B12 and associated logic elements. These f1ipflops, which have no reset inputs, ore set by c clock signal
XDS 901565
if the set input is Irue and are reset by a clock signal ifthe
set input is false. All logic equations for the B-counter
are written v/ith the following simpl ificaticns:
The next read/write clock sets TSf and generates a true
BXO signal that resets fI ip-flops B06 through B12 because
set inputs to each of these flip-flops are folse.
BXO RWCK + ..•
(RWCK-l - RWCK-4)
RVvCK
PRE-1
FRE
BXO
PXS + •.•
BXO-1
BXO
PXS
NRWP TSE
NBXO-l
NBXO
C/B12
RWCK + •••
(1:-.073)
B05
S/B06
NB06 NBXO +
(1:-.075)
B03 B04 B05
(1:-.077)
B12
(~O79)
B10 Bll B12
The functions or the B-coun~er are:
o. To count bits transmitted to the addressed selection
unit or received from the addressed selection unit, in serial
order
b. To con';ro! data trar~sfers within the controller so
that eight-bil' bytes are tr(Jr.sf~rred between registers
c. To control writing of the five-byte preamble dur;ng
execution of a write orde~
d. To enable search fo. t~e four-bit preamble synchonization pattern during expc:ution of a read order or ch~ck
write order
e. To Identify the po·;tar.,hle during execution of a
read order, write order, Oi checkwrite order.
Bits are counted by flip-f!ops B10, B11, and B12i bytesare
counted by flip-flops BOO though B09. The description of
the B-counteroperation is r31ated to the sequences described
in paragraph 4-59.
At the beginning of each intersector gap, fl ip-flop PRE,
RWP, and BCE are in the re$~t state, and signals BXO and
SEep are false. Read/write clock signal RWCK is generated from a source internul to the controller. When a sector
pulse or index pulse is de ..xted, a true SECP signal clears
flip-flops BOO through B05.
(C/B06-C/B 11)
NB12 NBXO + •..
During execution of a write order, flip-flops B06 through
B1: count subsequent read/write c locks in binmy sequence
from 0 000000 to 1 110 111 (decimal 119). flip-flop PRE
is set when the B-counter is in state 1 001 000 {decimal 72}.
Flip-flop RWE is set when the B-counter is in state 1 001 100
{decimal 76), provided the sector compare signal is true and
nc e.rrors are detected. Flip-flop RV';P is re~et when the
B-ccunter is in state 1 010 000 (decirnal 80). ;:Iip-flop
BCE is set when the B-counter is in si"c:te 1 11 0000 (decimal
1 i ?). When the B-counter reaches a count of 1 110 111
(decimal 119), sif:lnal BXO is true, resetting flip-flops B06
thl'ough B12 as before '=lnd causing PI{E to be res.:.:·t.
PSP WRITE BIT7RWE -{- •••
BXO
PSPB
B07 B08 PRE RYVE
BlT7RWE
1)10 B11 B12 RWE
R/PRE
BXO
C/pRE
RWCK
Flip-flop BCE is reset one clock time later wh~n PSPB is
false.
S/BCE
PSPB
R/BCE
C/BCE
(E/BOO-E/B05)
=
S/B12.
RWCK
Step
SECP
SFR + IPR
SPR
/SP/
IPR
lip/
While PRE is set and BCE is reset, signal WPRE causes the
five-·byte preamble to be stored in the K-register for transfer
to the D-register. At counts 79, 87, 95, and 103, the
pattern 0101 0101 is stored in the K-register. At count
111, the pattern 0011 0101 is stored in the K-register.
(See paragraph 4-57. )
4-61
XDS 901565
KXPRE
VVPRE BIT7RWE (Counts 79, 87, 95,
103, 111)
WPRE
PSPWEN
PRE WRITE NBCE (Counts 73 through
112)
=
W:'1en the B-counter reaches its maximum count, it is cleared
by the next clock signal and POST is set.
ShOST
NPOST NPRE
C/pOST
BOO BO 1 802 B03 B04 B05 B05C K + •••
B07 B09 (Counts 104 through 111)
lAs BCE is reset, the B-counter is placed in state 0 000 000
The B-counter then counts 32 bits (count 0 000 000 011 111)
and causes RWE to be reset, disabling the read/write heads.
001 000 and begins a binary count to state 1 111 111 111
111.
R/R\\'E
5/B00
NBOO NPRE + .••
5/B06
NB06 NPRE + •••
C/BOO
B05C K B05 1104 B03 B02 BOl + •••
B05CK
B06 NBCE
C/B01
B05C K B05 B04 B03 B02 +
C/B02
BOSC K B05 B04 B03 +
C/B03
B05e K B05
C/804
BoseK B05 + ..•
C/B05
B05CK
C/006
RWCK B12 Rll Bl0 B09 B08 807+ ...
S/B07
NB07 NBXO +
S/B08
NB08 NBX0 +
S/B09
B09Xl NBXO + •..
RWERST
POSTB89 BIT7RWE
rOSTB89
POST B08 B09
BIT7RWE
810 Bl1 B12 RVVE
C/R'vVE
M/OSE
B06 B08 + ...
DSHA
DSEM
NRWP REND
~END
RVv'E RCHW
Preamble flip-flop PRE may be reset during any of ihe 16
clock times from count 112 fo count 127 jf the prer,rr.ble
synchronization pattern is recognized (PSPR true).
R/FR~
BXO
WCHW RWE
S/Bl0
NB10 NBXO +
S/Bl1
NBll NBXO +
S/B12
NB12 NBXO +
C/B07
RWCK B12 B11 BlO B09 B08 +
C/B08
RWCK B12 Bll Bl0 B09 +
C/B09
RVvCK 812 Bl1 Bl0 +
C/Bl0
ROCK B12 Bll +
C/Bl1
RWCK B12 + ...
C/B12
Rv'v"'':K
BXO
PSPR + •.•
PSPR
NDAR NDOO DOl 002 PSPBRE ND
f'SPBREND
PSPB REND
?:>PB
S07 B08 PRE RWE
C/PRE
4-62
RWPRST
+
J{WPRST
B09X1
ROCK
The B-col'nter is cleared at the starr of the new sector, as
describe"; above. During execuiion of a read order:, the
B-count~r is cleared by a sector pulse or index pulse and
counts in Dinary sequence. At a count of 76, RWP is resE;i
and DSE: is direct set to transfer clock control to the data
strobe C'f the addressed selection unit.
R/RWP
~04
RWERST
RVvCK
\Vhen PSpr, is true, BCE is set. While PSPB is true, BeE
remains jr: the set state; after PRE is reset, BCE remains in
the set state for one clock time and clears the B-counter,
as for the wri te order.
During execution of a read order, the B-counte! is preset
to 0 000 000 000 000 {instead of 0 000 000 001 000, as for
XDS 901565
a write order). The B-counter then advances to state 1 111
111 111 111, is cleared, and counts to 0 000 000 011 111,
simi lor to a write order.
Paragraphs 4-5?to 4-58
For byte 3 of a sense order (BKWZ true), the address for
the sector currently under the read/write heads of the disc
fi Ie (angu lar position) passes through K04, K05, K06, and
K07 of the K-register.
During execution of a checkwrite order, the B-counter
operates as it does for a read order, first transferring clock
control to the addressed selection unit, then searching for
the preambie synchronization pattern, counting data bytes,
and counting preamble bits.
ANOR KXSENSE2 + •••
K04
SENSE BKWZ
KXSENSE2
K05
ANl R KXSENSE2 +
K06
AN2R KXSENSE2 +
KO?
AN3R KXSENSE2 +
4-5? K-Register
The K-register, which con:;ists of bufferp.d latches KOO
through KO?, stores data during execution of read orders,
write orders, or checkwrH~ orders. Data stored in the Kregister while signal KXO is true is retained until KXD is
false.
KOD
KOO KXO + ...
KC'7
KO? KXO
+ ..•
The K-register is cleared during phase RSA of an order out
service cycle when a sens~ order is executed, when data ;s
trcnsferred rrom the K-re8;~ter to the O-register, and after
the TDT delay line is start . '!:..; Juring execution of a write
order or chec!ns depends on the type or order being executed.
4-61 WRITE ORDER SEQUENCE. If a write order is being
executed, the B-collnter is c lemed, the track address is
shifted, and RWP is set as described in paragraph 4-60.
After the B-counter is ..::.Ieared, it counts read/writp. clocks
in binoiY sequence, as described in paragraph 4-56.
Vvhen the B-counter reaches a count of 72, PRE is sd. (See
figure 4-18. )
S/PRE
PRESET
PRESET WRCH
RWP B06 B09 NB10 NB11 (NPET
+ •.• )
"
C/pRE
i,
ROCK
Whi Ie PRE is set (B-counter states 73 through 119), the five_ e preamble is written. (See paragraph 4-56.)
4-66
PRE RVv'ESET
RWESET
B10 SECOMPR NUNE NFAULT
NFAULT
NRER NSEN NWPV
C/RWE
RWCK
Aftei P-'.VE has been set, the read/write heads in the addressed selection unit are enabled by signa I /WEN/, so
that daio signal /DAT/ and clock signal /5C2/ orr validated.
/WEN/
WEND
/SC2/
SC2D
/OAT/
WEND
WRITE RWE
SC2D
\VRITE CLK3MH
D07
aI1JO,-!_72-!-~+-7_4--!-.;..;75;.....L.._'/.:;6.-+I.....;77T..:..7-,-.;..;:78TI?18o
8-COUNTER
I
RWCK
WRITE,
RE . . . D.AND
CHECKWRITE
I
I
iY0
1
RWP
~:
RWE
POST
I:::,
s--
I BeE
;~
n
WRITE
I
..,
o
KXPRE
()
SREADEN
I
i
I I
r'S-COUNTER---'-i
I
-I
~.
:::s
<0
52
READ AND
CHECKWRITE
o
<0
o
PRE
1
PSPB
I
3
SREADEN
DSE
,
,
t-lJ'
I
1
I I
1
I
:1
0-
-41
1
!I "' I
I"
I
/f-I
'I
-,1--- I
!
,
,
::
I
I
fl,
__________1"
0 \I
31 1 32
U
P
I
!
'
:'I--I--~===::~--":"'~:;I--- -
'/-I- - - - - - - I { , I - '_-;.-_--(/-,_.....;...._ _
l...{ I
~,
Il
r-l
I
,',"1--
,',~__~_r,r;-
L_
!l
I
11---'---11-----
I
;~
-u--
([2ITolJl
I 1~1i-LL
~f
rTL''-+11-1---4: II
I
h'
I
If--'-
"~~.--:.-i-
I I
1-
,~
TNTOJl
'1
I
',.
I
'----I
tLJ-----,:..-----I(11-----.:--
;,
I,.
~I-J------------.;.1---1/..
I'r----/I,I
-
f
I I Lt r I
I
I
~:
,
//1----:...(I-:--:"'--
-{~rfl_____t~:1----..:......"
1.
,~I
- - { ',
,
---------------~1~:--------------------------~
I
~I---~~
--l~I-----I1
II
_ _ _ _- - I I - -_ _ _ _ _ _ _ _ _ _ _
i,
I
~0T·-~!-..J~/~----Ir- i
_ _ _ _ _,_.1.
---:-'---:-I--1I1I.-------------Ifl---.J
.
i
I
I
I
0
'~~rLr0-l1s-Lrl.
Ir-l-.--LJ'
i l l
I
2. IF PREAMBLE SYNCHRONIZATION PATTERN IS MISSED DURING EXECUTION OF READ ORDi:R
OR CH':CKWRITE ORDER, FlIP-F' OP PrE I\FSET AT COU~IT 17.0
IN
010231
:W:
'I
NOTES:
1. FOR WRITE ORDER, FLIP-FLOP PRE RESET AT COUNT 119. FOR REAl') ORDER ORCHECKWRITE
ORDER, FllP.. FLOP PRE RESET WHEN PREAMBLE SYNCI-!RONIZATION PATTERN RECOGNIZED,
WHICH MAY TAKE PLACE WHILE COUNT (N) IS BETWEEN 112 AND 127
o
I]
!
1
BCE
BXO
I
i
_~~_-I/~
WPRE
o
:::s
.....
I
~f-
oxo
()
(Ill! 1112
--':'--':"'---I'/----
-t
CD
,
----...:..-.;...-:~I, ---~
r
I!
I11-1-'i
-i~I it
~~I--I-r:-~:
,
I
'-COUNTER
I 81
/1
i
i
NOTE 1
NOTE 2
:~
•
Paragraph 4-62
XOS 901565
Flip-flop RWP is reset when the B-counter reaches 80.
R/RWP
R'A'PRST
C/RWP
RWPRST
B06 B08 + •.•
RWCK
After the preamble is written, PRE is reset, BCE remains in
r the set state for one clock time, and the B-counter is pre-
described in paragraph 4-61, and the read order sequence.
If a read order is being executed, the B-counter is c ieared,
the track address is shifted, and RWP is set as described in
paragraph 4-60. After the B-counter is cleared, it counts
read/write c locks in binary sequence, as described in paragraph 4-56. w.'1en the B-counter reaches a count of 72,
PRE is set, simi lar to a ....'rite order sequence. When the
B-counter reaches a count of 76, RWE is set, simi lor to a
write order sequence.
set to (0 000 000 001 000).
R/pRE
BXO
BXO
PSPB WRITe BIT7RWE
PSPB
B07 B08 PRE RWE
BIT7RVv'E
B10 Bll 312 RWE
C/PRE
RWCK
S/BCE
PSPB
R/BCE
C/BCE
RWCK
S/B09
B09Xi BXO +
For a read order, the interface control circuits must search
for the preamble synchronization pattern (0011), rather
than write the preamble. The state of the B-counter when
the pati"ern is detected may not be the seme as jhe S~Qte of
the B-counter when the pattern was written. Theref.xe, a
search is conducted for the synchronization pattern for two
byte time$ (16 bits). Furthermore, since data must be read
from the selection unit, the data strobe signa I must be a! lowed
to control the read/write clock at some time during execution of the read order.
When the B-counter reaches a count :.::;f 80, RWP is ,t!set as
for a write order, end DSE is direct ~Gt, el"abling re r..1.J/w.ite
clock signal RvVCK to be controiied by the data strcb£ signal.
OSEM
M/l)SE
B09Xl
V;lCHW RV·/E
When' th:: B-counter reaches a maximum count (1 111 111
'111 111), POST is sei" to identify the time for writing the
postamble.
OSEM
NRWP REND
REND
RWE RCHW
DSR
t-,!POST NPRE
C/POST
300 BOl BO"~ B04 B05 BOSCK +
S/DSE
B06 NBCE + •.•
R/DSE
After the postamble has been writ:-en (32 bits), RWE is reset.
C/DSE
R/RWE
RWERST
RWERST
POSTB89 BIT7RWE
POSTB89
POST B08 B09
BIT7RWE
BI0 Bll B12 RWE
C/RWE
RWCK
The interface control circuits are rlow in the initial states,
ready for sector pulse or index pulse and trock addrcssshHt:ing, as before.
4-62 READ ORDER SEQUENCE. Th is paragraph emphasizes
_ _ i Herence in operoti on between the w,; te ordersequence
4-68
/OS/
Once set, DSE remains in ~he set state until RWE !s l,-'set
at the end of the postamblc.
S!pOST
saseK
DSR OS:: +
RWCi(
DSE RWE
RWCK
Preamble f!ip-f1op PRE may be reset during any of the 16
clock times frem count 112 of the B-c~unter to counl 128
of the B-c:ounter (PSPB true).
R/PRE
BXO
BXO
PSPR + ...
PSPR
NDAR NDOO.D01 D02 PSP3REND
PSPBREND
PSPB REND
PSPB
B07 B08 PRE RWE
C/PRE
RWCK
XDS 901565
Signal PSPR is true when the preamble synchronization pattern (0011) has three bits in the D-register and one bit in
data flip-flop DAR. If the preamble is missed, PSPB is true
at count 127 and error flip-flop CER is set. (See paragraph
4-76. )
B09 BIT7RWE NRWP PSPBREND
PSPM
Paragraph 4-63
The least significant bits of the B-counter count the eight
bits of each byte. During execution of a write order, the
B-counter is cleared just before the last data byte is to be
written.
Data accepted from the addressed selection unit is read by
data flip-flop DAR after read/write enable flip-flop RVVE
is set.
B10 fH 1 B12 RWE
BIT7RWE
S/DAR
DAIR REND
For the read order, flip-flop BCE is set at count 112 to pre-
vent a search for the preamble beyond count 127. If the
preamble synchronization paHern is recognized, PRE is reset, and BeE is reset on the following clock, similar to a
write operation.
DAIR
IDAI/
REND
RWE RCHW
RibAR
S/BCE
PSPB
C/DAR
RWCK
R/BCE
C/BCE
~\AlCK
If the preamble synchronization pattern is not recognized,
BCE remains in the set stct9, and a true BXO signal is generated after B06 is reset ot count 127.
BXO = PRe NB06 ••••
After BXO is true, PRE is resr>+f then BCE is reset.
While BeE is set, the mo<~ .;;ignificant flip-flops of the BCOJnter car.not be c lockee!,
(C/BOO-C/B04 )
PP: BOSeK
B05CK
BC5 NBCE
B05CK
C/B05
After BeE is reset, the B-ccunl"er is c leored.
4-63 CHECKWRITE ORDER SEQUENCE. Thi:; paragraph
emphasizes the differences in operation betwE'e!1 the write
or6er sequence described in pcrcgraph 4-61, tbe read order
se~uence described in paragraph 4-62, and the cneckwrite
on-fer sequence. If a checkwrite order is beiP3 :::xecuted,
the 8-counter is cleared, the track address i$ shifted, and
RWP is set as described in paragraph 4-60. AHer the Bct):jnter is cleared, it counts read/write clocks ;n binClry
sequence, as described in paragraph 4-56. vvhen the BC0:Jnter reaches a count of 72, PRE is set, as for a write
o~.:!:::r sequence. For a checkwrite order, the interface contr':.>! circuits must search for the pre~rnbie syncP'"onizotiooi
pntfc;;rn (0011), as in the read order, rather thcp wr:te the
pr ';(1mble. Since data must be recid from the selection unit,
tl:~ data strobe signal must be allowed to control reed/write
cloc~ ~WCK at some time during execution of the checkwrit~ corder. Therefore, data strobe enable flip·-flop ic 5et,
PRE is reset when the preamble synchronizatic-." pattern is
rpc:ognized, and data fl ip-flop D/~R reads date from the
selection unit, simi lor to a read operation.
M/DSE
For the reae order sequenct"', signal B09Xl is not true, and
the B-counter begins counting data bytes with a count of
(0 000 000 000 000). Thus the count of the B-counter is
one less than the data byte being read, as in the following
examples:
DSEM
NRWP REND
REND
RWE RCHW
ROCK
DSR
Data Byte
Write Order State
a 000 000 001
XXX
Read Order State
R/PRE
DSR DSE +
IDS/
BXO
a 000 000 000 xxx
BXO
PSPR + •••
a 000
PSPR
NDAR NDOa DOl D02 PSPBREND
2
a 000
000 010 XXX
27
0 000
all all xxx a 000 011
000 001 XXX
010
xxx
S/DAR
DAIR
1023
1 111 111 111 XXX
1 111 111 11 0 XXX
1024
a 000
1 111 111 111 XXX
000 000 XXX
DSEM
DAIR REND
/DAI/
R/DAR
C/DAR
RWCK
4--69
XDS 901565
4i5ographs4-64 to 4-66
4-64 SENSE ORDER SEQUENCE. During execution of.a
sense order, the interface control logic inhibits data transfer unti I the period of the intersector gap time following
the transfer of the track address. This restriction guarantees
that data accumulated for the sense order (figure 3-5) identifies the next sector for which a full 1024 data bytes can
be processed. During the order out service cycle and after
the sense order code is stored, service call signal SCD canznot be raised until flip-flop SE~! is set and flip-flop TSE is
reset.
DeB PHFS CYCLE!C
N(NSCNMEN}
M/5CN
N(NSCNMEN)
NCDN SCNMENl + ••.
SCNMENl
SEN NTSE + •••
.,-flop SEN is not set until the previously incremented
" c k address and sector address Love been transferred from
the T -register and the S-registe:- i"o the P-register. (See
paragraph 4-70.)
PX5R:"1
PX5R-2 = PXSR (P-register
shift right)
PRST -1
PRST -2 = PRST
(Preset Pregister)
(RWCK-l-RWCK-4)
RWCK
(Read/wri te
clock)
Reset inputs to the P-register are true when aD-register
shift left is enabled (OSl true) and during the intersector
gap time when data cannot be read from, or transmitted to,
the addressed selection unit (NRWP tr.Je).
(R/i'OO-R/P15)
DSl + NRWP
PRST
For one clock time during the intersector gap time, signal
PXT is true, causing the track overflow bit TOF cnd the
contents of the T-register to be transferred to the P-~egister.
(See figure 4-17. )
5/1'00
PXT TOF +
PXS SENSE
S/SEN
PXT
PXS
TSE NRWP
TSE NRWP
5/P0l
PXT TOG +
5/"-11
PXT
RWCK
C/5EN
Flip-flop TSE is reset by the fO!lowing read/write clock.
(See paragraph 4-60.) Once SEN :s set, it cannot Le reset
until the order in service cycle i:. entered, causing NDATA
to be true. (See p.:lragraph 4-29. )
R/S!:N
PRST
=
no
At the sume time, a sector address is stored in flip-f!C'ps
P12 through 015.
Nl)ATA
SjP12
~efort;;, for a sense order, th~ data in service cycle for
•
•. .;;) first byte cannot begin until SEN is set, after which a
transfer from phas~ FS to phase FSZ is possible. Flip-flop
SCN is direct set during phase t~. When CDN is set, the
direct set equation is inhibited aad the order in service
cycle follows.
+ •••
P~'S
S/P13
PX5
sao
+
TSE NRWP
PX5 P13LD + •••
P13lD
P13lDEN + SOl
P13lDEN
S03 S02 SOO EXT
4-65 ADDRESSING CIRCUITS
4-66 P-Register
The P-register, which consists of flip-flops poa through P15
and associated logic elements, is clocked by read/write
clock signal ROCK. Refer to paragraph 4-55 for a description of the read/write dock A flip-flop of the P-register
is reset if the reset input is true and if the set input is false.
tIf the set input is true, the flip-flop is set regardless of the
level of the reset input. Equations for the P-register are
written with the f?llowing simplifications.
4-70
S/P14
PXS S02 +
5/P15
PXS 503 +
...
For all sector addresses from 0000 through 1010, the contents of the S-register are transferred unchanged. Tnerefore, during the incrementing process described in pa;agraph
4-70, the normal binary sequence will be followed until a
count of 1011 is reached. For this count, a volue of 1111
will be transferred to the P-register if an EP RAD storage
unit is connected (signal EXT true). In this case, the incrementing process generates an address of 0000, so that a
XDS 901565
sector match occurs for sector 0000 of the next track. (The
track address is incremented in normal binary sequence each
time that the sector address changes from 1111 to 0000. )
Just before preamble time, the incremented track address
is returned to the T -register and the incremented sector
address is returned to the S-register. During preamble time
(PRE true), the P-register is preset to all ones in preparation
for generation of the checksum. When signal PXSR is true,
the contents of the P-register ore shifted right, while new
data is stored in flip-flop POD.
SjPOO
Paragraphs 4-67 to 4-68
At the beginning of each sector, the S-register is cleared
just before the incremented value is transferred from the Pregister if a read order, write order, or checkwrite order is
being executed.
NSXO
RWP TDL020 +
500
SXP P12 + •••
"SXP
STXPEN TDLl 00
STXPEN
SXPEN RWP
SXPEN
NPET +
PXSR PooSET
PXSR
PRST NPXS
SOl
SXP P13 +
502
SXP P14 +
S03
SXP P15 +
PXSR POO +
S/POl
PXSR P14 + .••
S/P15
The new information is used f'o generate the checksurr.while
data is processed, as described in paragraph 4-7 J.
!;",ctor compare signal SECOMPR is controll~_d by a" comparison between the contents of the S-regis~er and the ang'.Jlar fJosition signa!s from the addressed selection unit.
SECOMPR
4-67 S-Register
The S-regist~r, ,:vhich ccnsists of buffered latches sao
through S03 and associored logic elements, stores the
address of the sector at wh ich a rend s~quence or write
sequence will hegin whp.n ;:xe'cuted. Durin£! execution of
a seek order, the S-reghter is loaded from the J-register
under control of the byte counter and the TRL delay; ine,
as described in paragraph 4-97.
J04 SXJ + •••
SOO
=
(ANOR
(ANl R
(AN2R
(AN3R
ANOR
/ANO/
AN1R
iAN1/
AN2R
/AN2/
AN3R
/AN3/
+ NSOO) N(ANOR NSOO)
+ NS01) N(ANl R NSOl)
+ NS02) N(AN2R NS02)
+ NS03) N(AN3R NS03)
SEEK R'NRITEDO BKWZ TRS130
4-68 T-Register
SOl
J05 SXJ +
S02
J06 SXJ +
S03
J07 SXJ +
Th~ T -register, which consists of buffered latches TOO
tr.rough no and associated logic elements, s~ores the ad~rp<;s of the track from which data will be rec1(-I or into which
dl.lta will be written. During execution of Q seek order, the
T -register is loaded from the J -register under control of the
byte counter and the TRL delay line, as described in paragropn 4-97. The 11 bits (two of which shou;J always be
zeros) are stored in two consecutive bytes.
SXJ
Signal SXO is used to clear the S-register before storag,e of
new data and to retain the stored data.
SOc
sao
SXO + ...
JOl TXJ + •.•
TOO
TXJ
S03
S03 SXO + ...
SEEK RWRITEDO BKZW TRS130
T01
J02 TXJ + •••
T06
J07 TXJ + •••
During phase RS of an order out service cycle, the Sregister is cleared if a seek order is to be executed, so that
a new address can be stored.
NSXO = PHRS ORDOUT SEEK + •••
4-71
Paragraphs 4-69 to 4-70
XDS 901565
The bits of the second byte are transferred from the Jregister to both the T-register and the S-register.
JOO SXJ
T07
+ •••
SEEK RWRITEDO BKVIZ TRS130
SXJ
the EP RAD storage unit addressed for an input/output operation. The set input signals to the U-register come true
and are latched during phase FSL of a response to an lOP
command. Data is clocked into the U-register only when
device controller busy fl i p-f1op DCB is set when a new
input/output operation is started.
T08
= JOl SXJ +
T09
J02 SXJ +
DCBSET
PHFSL SIOPOSS OPER
T10
J03 SXJ +
SIOPOSS
SIOU NDCB NCIl
(C/UO-C/U2)
Signa I TXO is used to c lear the T-reg ister before storage of
new data end to retain the stored data.
DCBSET
(R/UO-R/U2)
SUOD
S/UO
TOO = TOO TXO + ••.
DA5R lOP + PHFSL SUOD +
SUOD
SUID
S/Ul
TlO
110 TXO + ...
Quring phase RS of an order oUT service cycle, t~e Tregister is cleared if a seek order is to be executed, so
that a new address cal) be stor-ee.
TXO
SXO
NSXO
PHRS ORDOl'f SEEK + •.•
At the beginning of each sector, the T -register is cleared
just before the incremented value 13 transferred frorr. the
P-register if a re~ci order, writa urder, or checkwrite order
is being executed.
TXO
S/U2
SU2D
DA7R lOP + PHFSL SU2D ;
SU2D
.••
During pno'ie FSL of any input/output sequence, the corltents of the U-register are compared with the content:; of
lOP dot" i:nes /DA5/ through IOA7/. Signal DVSEL is
true if the two sets of sisnals arc identicaL
DVSEL = (SUOD + NUO) N(SUOD r"-lUO) (SUI D
+ NUl) N(SUl D NUl) (SU2D + NU2)
N(SU2D NU2)
The contents of the U-regbter control address signa Is to the
EP RAD ~(orage units.
SXO
NSXO
DA6R lOP + PHFSL SUl D + ..•
SU1D
RWP TDL020 +
/UYJ/
=
SUOD
TXP POl + ..•
TOO
/101/ = SUID
TXP
STXPEN Tut 100
STXPEN
SXPEN RWP
SXPEN
NPET +
/102/ = SU2D
4-70 Address Incrementation
T01
TXP P02
110
TXP Pll + •••
L
4-69 U-Register
,
The U-register, which consists of f1ip-·flops UO, Ul, and
U2 and associated logic elements, stores the address of
4-72
The initiC'lI track address and sector address are loaded by a
seek order, as descri bed in paragraph 4-97. Duri ng execution of a r4->l]d order I write order, or checkwii te order, t'NO
operations must take place during the intersector gap time.
First, the .. ector address must be incremented so that a true
sector compare signa I SECOMPR can be generated for the
next sectoi in sequence. Second r if the sector add~ess
changes from 1011 (binary 11) to 0000, the track address
must be incremented, so that the next track address in sequence can be selected. These operations are controlled
by the P-register and flip-flop 007 of the D-register. (See
figure 4-19.)
(FALSE DURIN G
TRACK
It..JCREMENT)
(FALS~ OURJNG-{>ONLd..JE
-l
OPERATION)
---,
i
>----~S
DSL
1---.....
007
FF
007
D07SET
R\'VCK
P15
(TRUE)
Ot---"ND07
o
..::;;
Pl1
(FALSE DURING
TRACK
INCREMENT)
3
-0
(1)
0..
POOSET
S
r
o
(Q
POOSETEN
007
n
M
FF It---1~P15
POO-P15
C
o
C'
o
PXSR
3
DSLI>-.
NRWP
-0
3
JI
o·
Ul
'?~
1
.....J
W
.z,...
I'V
W
R
NP)~S--
NREADRWE
(0
~PR~S~T
_____
~
______________________________
~
01-"'-" NP15
XDS 901565
Paragraph 4-71
During the intersector gap time, the contents of the T register end S-register are transferred to the P-register
when PXS and PXT are true. (See figure 4-17.) Flip-flop
007 is set at the same time.
D07SET DSl + .•.
5/007
D07SET
BXO +
For the next 16 clock times, the contents of the P-register
are shifted right (from POO toward P15) while new data is
stored in POO. For 11 of the 16 clock times, the 11-bit
track address is transmitted to the addressed selection unit.
/SC1/
=
/TRK/ =
(Clock)
Pl1
(T rack address bits)
Flip-flop 007 acts os the carr)' flip-flop for a
~n of one of the contents of the P-register.
eset in 007 is added to the least significant
the P-rcgister, 007 remains in the set state if
generated.
•
D07SET
D~l
The checksum is generated in the P-register during the
execution of a write order, read order, or checkwrite order.
In all cases, the 16-bit checksum is transferred to the Dregister one byte a1 a ti me after the 1024 bytes of the sector
have been processed. For a write order, the checksum is
written on the disc file in the sector for which the checksum was generated. For a read order or checkwrite order,
the checksum ge~erated during executicn of the order is
compared bit-for-bit with ;he checksum read from the disc
fi Ie. (See figure 4-20. )
After fI ip-flop PRE is set and R'vVP is reset (figure 4-18),
the P-register is loaded with all ones.
SCl D
S/D07
. 4-71 Checksum Generation
S!pOO
serial addiAfter the one
bit (P15) of
a carry is
=
After the preamble has been written during execution of a
write order or detected during execution of a read order or
checkwrite order, PRE is reset and the process of gp.~:roting
the chc.::ksum begins. Because signal PRST is true. thecontents of the P-register are continually shifted right (from
P~Q toward P15) and ne'N data is ent~red in POD.
+ •••
S/POO
D07SET
PXSR POOSET
POOSET
(POOSE1HJ + P15)
N(PCOSETEN P15)
POOSETEN
D07, NREADRWE +
Therefore, as a track address is transnlitted to the addressed
selection unit, a new track address is generated and stored
in the P-register. Just before flip-flop RWP is reset, the
new track address and sector address are transferred to the
T -register and the S-register.
STXPEN TDllOO
TXP
SXP
STXPEN
SXPEN RV/P
SXPEN
NPET +
STXPEN TDL 100
Circuits of the P-register store a code of j 111 in fI ip-flops
P12 through P15 if the code in the S-register is 1011. Thus,
, when the address incrementation process takes place, the
new sector address is 0000 and the track address is incre.mented in normal binary sequence.
.1
4-74
PXSR POOSET + ••.
007 P15
As the serial addition proces!1 continues, the incremented
address is shifted into POD, and the more significant bits of
the previous address are shifteo in~o P15. When no carry
is generated, 007 is le5et and rh ..'! bits of the previous address arc shifted unchanged.
S/~'OO
PRE NRWP + ..•
~XSR
PRST NPXS
PRST
NRWP + .••
During execution of a write order or che"kwrite o. C!er
(NREADRWE true), P15 anci DO? generate th("~ new oata;
during 6xecuti~n of a read order (READRWE true), 1'15 and
DAR genelote the new data.
(PJOSETEN + P15)
N(POOSETEN Pi5)
peOSET
REl.DRWE DAR
+ N READ RWE D07
POOSETEN
i\EADRWE
=
READ RWE
In either :::-ase, an ~ xcfusive OR operation is perforfiied on
the conte~t of the P-register and the new data, as indicated
in figurl" 4-20, for execution of a write order or c!"lf-;ckwrite
order. Data bytes are stored in the D-register an!.i read
serially as data is circulated in the P-rcgister. b the
example of figure 4~·20, a byte of 1011 0010 in i"he D·register, when processed with the 1111 1111 initiC"'ll, in
the P-re!::ister, produces a byte of 0100 1101, which is
stored in the P-register. The second data byte. of the
example, when processed with the 1111 1111 initial~ystored
in the second half of the P-register,· produces a byte of
1010 110G. In a similar manner, after these D>-tes are processed with additional data bytes, the P-register contains
(from P15 to POD) the bits 0000 1111 0101 1010, which will
be processed with the n€;d data bytes received. The 16
bits stored in the P-register after 1024 data bytes are processed (including any bytes of all zeros) become the
WRITE OR
CHEC KVVRITE
D07~
NREAD~WE~._)
L-;--.. . "
POOScTEN
~------------~~----/
DAR
READRWE
NPXS
S
PRE
FF
1
P15
POO-P15
X
C.
RWCK
0
(..1\
NRWP
PREAMBLE
DSL3>-~.
~______
_ __
PRST
o
..
::J
(,/')
NRWP
0
<..n
<..n
~
~
(';)
r
2
3
007- 000
007 - 000
BYTE NO.
o
9.
D-REGISTER
o
D07-DOO
4
I
007 -
6
5
007 -
000
000
007 -
000
~--------+-------.--.-~-.---------~-----------~---------~~---,.----
<.a
o3
(READ FROM 007)
'.1 011
001 0 'x
P-REGISTER
(READ FROM P15)
·1111
1111
,,~1 01
Q~O~
0010
1111
0110
iYn-llrl'i1~ 0100
1101
(f010
11~
00l}.. I
P15 - - - - - - - POO
P15 -----·-----POO
0000
I
1111
01 01
101 0
P15 - - - - - - - - P O O
~-----------~---------------------~------.~.------------~--------------------~
NOTES:
1. BYTES,l .AND? PEPR2SENT INITI/\;,. (Or--.;T!:i"TS c')F
g
3;
"J>
-I'....,
./>.
S
0-
"<.a
n
NP15
'Cl
P-:U:G;STE~
2. P-REGISTER BYTES 3-6 ARE GENERATED FROM. CONTENTS OF
D-REGISTER AND P-REGISTER
Paragraphs 4-72 to 4-73
XDS 901565
9.cksum stored on the discfi Ie. 'MIen data isread serially
from the disc file atthe output offlip-flop DAR, the check-
UNEM
M/uNE
sum generated should be identical to the checksum read from
the disc fi Ie following the 1024 data bytes. The process is
identical whether POOSETEN is controlled by 007 or DAR.
UN EM
CYCLE/C DCB NORDOUT PHFS
(CER + UNEMl + DRESET)
RER + SUN + WPV
UNEMl
+ NFKI ORDO PER REMPT'{
4-72 ERROR CIRCUITS
+ NORD2 NORD3 NORD4
+ ORDIN PER + ORDl SENSE
{The error circuits of the controllE'f consist of the flip-flops
listed in table 4-5 and of the a~wciated logic elements.
These flip-flops and the signais controlled by them provide
information to the lOP concerning error conditions that
occur during execution of orders or as a result of power
failure or from programming errors. Error signals are provided during the order in service cycle of an input/output
operation. ProgrC!m response to j'hese error conditions may
• cause data to be provided by execution of additional commands (TDV, Ala, TIO, HIO, or SIO), as summarized in
+ NDVOR
(,
Unusual end f1ip-f:op UNE may be direct set during phase
FS of ony zervice cycle other thllil an order out service
cycle.
FLIP-FLOP
I
I
INL
~ER
RER
PWRMONR
P\VRM~NR
/PW,RlV\O!'J/
V,ullvtlO?l
lOP INTERFACE SIGNALS CONTROLLED
- -*- - " " - - - 1 S Ht
AIO*
I'--O-r!-T--~ *
TDV
-+-_ _ _ _ _ _+ _ r . . er .n
I - - --
- ---------1--------;--- _____
I
Check...rite error
I
IDAOI
Incorrt: c t iength
I
/DA1/
I
Parity error (checksum)
Rate erro.
/FRO/
IDA 0/
/IORI
/IOR/
/FR21
/DA2/
/lOR!
IIOR/
I
SUN
=:=
Summary of Error Flip-Flap.; and Signals
F:";!~CTION
+I
CER
DRESET
\ Direct set of/UNE takes place if error flip-flop CER, RER,
SUN, or W~V is set. Signai /DVOI is controlled bj the
addressed selection unit and is true if the aqdressed devir,e
is not operal'ional, as described in paragraph 4-104. Signal /PW~MON/ is controlied by circuits which detect
power failure, as described in paragraph 4-7. Of the 32
possible order codes, eight are interpreted as seek orders
(X XX 1i), eight as read orders (X XX 10), four as write
orders (X X001), and four c!s checkwrite orders (X XiOl).
4-73 Unusual End Logic
II
-
/DVol
~v~ ~ ~~((/.
_.4-5.
TlJble 4-5.
~I~~
DVOR
Sector t;navai lable
UNE
Unusua I 13r1d
WPV
Write protect violation
IDA!)/
/DA4/
/FR4/
/FR3/
/DA3/
/IOR/
/IOR/
r-------------~------------------------.--~----------~-----------~---------.--~~----------~
* /lORI controiled by FAULT
t TSH
=
.=
REf< + SUN + WPV
TIO + S10 + HIO
• **/DAO/ controlled by TER
= CER + PER + RER
L.______,___________________________
4-76
~
XDS 901565
Of the remaining eight, four are illegal (X XOOQ). Of the
possible forms of the sense order (X X100), two are illegal
(X 1100). Anyone of thesb: illegal order codes causes
UNE to be direct set.
NORD2 NORD3 NORD4
UNEMl
Paragraphs 4-74 to 4-76
during execution of the read order and read from P15.
the two checksums are not identical, PER is set.
S/pER
If
PEREN POOSET
PEREN
READRWE POST NB08
POOSET
(POOSETEN + P15) N(POOSETEN P15)
+ OROl SENSE + •••
SENSE
=
OR02 NORD3 NORD4
POOSETEN = READRWE DAR + ...
Parity error flip-flop PER, which can be set only during
execution of a read order; causes UNE to be ~et for two
different conditions. For a read record order (0 XX] 0),
UNE is set during the order in service cycle, after Q count
done terminal order has indicated that the entire record has
been read.
UNEMl
=
=
ORDO PER NKFI REMPTY + •••
If UNE is direct set for an~' reason, flip-flops (DATA, II'!)
wi II be placed in the (0, 1) stL,te, as described in paragraph
4-32, because sigr.al DATt.SET will be false.
NDATASET
=
Once set, PER causes UNE to be direct set and con be reset
only by a RESET signai.
R/pER
GND
E/PER
RESET
R/UNE
RESEr
ClUNE
NTC~OOO
E/UNE
MANRST
MANRST
4-7;:; Write Protect Violation Logic
Wr:te protect violation flip-flop WPV is set if a write order
is a:temj.>ted on a write protected track. TrccK-protpcted
sigOiol /fRP/is generated within the address'9d seltction
unit as described in paragraph 4-106.
PRE WPVSET
S/WPV
WPYSET
WRITE TRPR
TRPR
/fRP/
UNE + ...
Therefore, an order in service cycle will occur if UN[ is
. set during any input/output ()peration. The order in s;)rvice
cycle is begun after phase FS is entered. Flip-Flop UNE
may be set by the lOP during terminal order operations, as
described in paragraph 4-34. If UNE is set bv a termir.al
order, the sequence of operations is ide:1ticalto that caused
by a direct set signal. Or.:.e set, UNE must ~e reset by .
either a RESET signal or a .V.ANRST signal.
. RSTR
RWCK
ORDIN PER + •••
For a read sector order (1 XX10), UNE is set .if an error
occurs while data is read from any sector. End of sector is
indicated by an empty K-..egister (NKFI true) and an empty
FAM modu Ie (REMPTY true).
UNEMl
=
C/PER
NPET RSTR
/RST/
RWCK
. c/WPY
If V:PV is set during the preamble time, it CO'_;S€s UNE to
be Lir';ct set and can be reset only by a REser signal.
R/WPV
GND
E/WPV
RESET
4-76 Checkwrite Error Logic
Chcckwrite error flip-flop CER can be directsct if an index
puls-= or sector pulse is received while RVVE is set. This
condition wou ld occur if data strobes are missed during exec'..~tio 1 of a read order or checkwrite order. In that case,
t"'e B-counter value would be incorrect.
;-A/CER
CERM
4-74 Parity Error Logic
CERM
RW'E SECP
Parity error flip-flop PER can be set only during execution
of a read order and then only while the checksum is being
read from the addressed sele::::tion unit. The checksum read
from the addressed selection unit through signal DAR is
compared with the checksum generated in the P-register
SECP
IPR + SPR
SPR
/sP/
IPR
IIP/
4-77
XDS901565
Paragraph 4-77
Flip-flop CER is set during execution of a checkwrite order
if the checksum bits read from the disc file through flipflop DAR do not match the checksum bits generated during
execution of the checkwrite order. The checksum bits are
read from 007 after transfer from the P-register. An exclusive OR gate is enabled by signal CHWEREN to make
the comparison.
CERSET
S/CER
CERSET
CHWER +
CHWER
CHWEREN (DAR + D07)
N(DAR D07)
CHWEREN
CHWR NPOST NPRE RWE
R/SUN
GND
CiS UN
RWCK
This interval follows the transfer of the incremented address
from the P-register to the T -register and S-register, as described in paragraph 4-70. Therefore, SUN is set if a st:ctor address stored in the S-register, or a track address stored
in the T -register, represents a location which does no~ exist
in the RAD storage unit. (Signals TYPOR, TYPl R, and EXT
indicate the type of RAD storage unit, 05 described in paragraph 4-82. )
During execution of a seek order, the T -register is cieared
and a new track address is stored. If the most significant
bit of the new track address is a one, track overflow signal
TOF comes true and is latched.
RWCK
C/eER
JOO TXJ + TOF
TOF
;n 9 execution .:>f a read order or a checkwrite order, a
•
rch is conducted for the preamble synchronization pattern r as described in paragrap~' 4-56. If the preamble
synchronization pattern is not detected, signal PSPM is
t-rue and CER is set.
S/CER
CERSET
PSPM +
SEEK RVv'RITEDO BKZW TRS13C
TXO
SXO
NSXO
SEEK PHRS \) RDOUT +
PSPM
PSPBREN[) NRWP BIT7RWE B09
PSPBREND
PSPB R~i'lD
PSPB
PRE RWE B07 B08
REND
RCHW ::\VE
Because IJ track address with a most significant bit of one
is inval id fo;- any RAD storage unitt a true TOF signcl causes
direct set of SUN during ph':lse TO of the data out sdvice
cycle.
M/SUN
RWCK
ER is set, it remains in the ',et state lInti I signal RESET
,rue. Before RESET is true, eEl< causes UNE to be direct
set.
RICER
GND
E/CER
RESET
4-77 Sector Unavai table Logic
Sector unavai lable fl ip-flop SUN may be set in the preamble
time interval during which PRE is set and RWE is reset. (See
figure 4-18. )
S/SUN
PRENRWE
SUNSET
PRENRWE SUNSET
PRE NRWE
SOO SOl EXT + TOO + TOl
+ T02 NTYPOR
+ T03 NTYPOR NTYPl R + .••
4-78
TXJ
CERSET
C/CER
•
TXO, + •••
SUNM
SUNM
NDATASET (PHTO TeS10r' ,1)
(SEKSEN D SUNSET)
NDATASET
CL'N + •••
SEKSEND
SEEK NPHRSAOO +
SUNSET
TOF + TOO + T01
+ T02 NTY~OR
+ T03 NTYPOR NTYP1R
+ sao SOl EXT
Signal TOF becomes true and is latched if address bercmentation causes the most significant bit of the track tiddress
to be true.
POO TXP + TOF TXO + .•.
TOF
TXP
TDLlOO STXPEN
A true TOF signal is not on error unless an attempt is made
to read from, or to write into, the nonexistent addressed
track. Therefor'e, for a sense order, a true TOF signal
direct sets SUN to provide the unusual end data. The rop
is able to test for causes of unusual end.
Paragraphs 4-78 to 4-79
XDS 901565
M/SUN
SUNM
SUNM
KFID
S/KFICK
NDATASET (PHTO TCS100-3)
(SEKSEND SUNSET)
+ KFIDX1)
KFID
KXO (KFID
KFIDX1
KFI TRS270
NKXO
WCHW TDT2 + ..•
SEKSEND = SENSE NPHRSAOO +
If SUN is set, it remains in the set state until signal RESET
is true. Before RESET is true, SUN causes UNE to be direct
set.
R/KFICK
RVVCK
C/KFICK
E/SUN
=
RESET
4-78 Rate Error Logic
During execution of a write order or checkwrite order, data
from the lOP must be provided in time for a transfer of data
from the K-register to the D-register at the rate estabiished
by read/write clock signal RWCK. During execution of a
read order, data must be accepted by the lOP before the
FAM modu Ie is fi lIed, and additional data must be stored
in The FAM modu Ie at thE" rate established by read/write
clock signal RWCK. Rate error flip-flop RER is set ifeither
kind of rate is detected.
During execution of a read order, a rate error is detected
if on attempt is made to transfer data from the D-register
to the J-register (JXD true) when the FAM module is filled
(NRKO true) and the lOP has not signalled count done
(!'4CDN true). When 01 i these conditions exist simu Itaneously, RER is direct set.
M/RER
RERM
jFI
=
N(JFIRESET RWRITE-2 TRS180) U;:IXl + ••• )
Once RER is set, it <-an 1:,,:.; reset only by signal RESET. Befcre signal RESET is true l RER causes an unLosIJul end condition.
R/RER
GND
E/RER
RESEl
-79 Incorreci" Length Log i c
4
JXD I'!RKO NeDN
Incorrect length flip-flop INL is set for any '.)lle of three
co.-lditions:
REREN RERSET
REREN
DATA + JFI
RERSET
NV-lPRE DXK NKFICK
DXK
CHWR NPOST 8IT7RWE NPRE
+ VvRITE NP OST BIT7R WE + ...
C/RER
A true JFI signal enables KFICK to set after the order in
service cycle is in process. This signal is reC!uired for the
rn:Jltiple-byte interface, for which valid datC" may still be
in the I-register after exit from the data out service cycle.
(See paragraph 4-48. )
RER/I/\
During execution of a write order or a checkwrite order, a
rate error is dejected after the preamble has been wri tten
(i'-lWPRE true) ; f an aHe"""pt is made to transfer data from
the K-register to the D-"'egister (DXK true) before the Kregister has been fi lied (!'~ KFIC K true).
S/RER
Therefore, if a K-register to D-register transfer is attempted
when KFICK is in the reset statal the K-regif>ter contains no
neVi data.
RWC:~
Wnen the K-register is filled from the FAM module, KFlD
comes true and is latched. Flip-flop KFICK is set by the
following read/write c lock and remains in the set state until
the K-register is clearec.l following a k-register to 0register data transfer.
o. The number of data bytes transferred Juring execution of a read order, write orc.ler, or checkwr::e ord(;;!r is not
an lntegral multiple 0f 1024.
b. The number of data bytes transferreJ ,-juring execution of a seck order is not 2.
c. Thenumber of data bytes transferrec; curing execution of a sense order is not 3.
AlttlOugh these conditions are not necessari Iy 3rrors, the
information that INL was set may be required by a program.
Therefore, although UNE is not set, a signal is returned to
the lOP through signal /DA1/ during the order in service
cycle.
/DA1/
001
001
OXORDIN INL + ..•
Flip-flop INL is reset during any order out service cycle and
is cleared follo\'l/ing completion of any input/output operation.
4-79
•
Paragraphs 4-80 to 4-83
R/lNL
OROOUT
CjINL
TCS100-3
E/INL
NOCB
XOS 901565
Count done flip-flop CDN, which should be set after all
data bytes have been transferred following execution of
any order, controls signals related b setting flip-flop INL.
During execution of a seek order or sense order, INL is set
during the order· in service cycle if CDN is not set.
INLSET OROIN
S/INL
INLSET
INLEN SEKSEND +
SEKSEND
SEEK NPHRSAOO
+ SENSE I'~PHRSAOO
INLEN
NCDN +
During execution of a read order, INL is set during the
order in service cyde if CDN is set and the K-register is
st!!1 fi lied (KFI true). In th is ease, the byte tronsfe~red to
the K-register IS 0 byte of zeros which follows removal of
all voiid dora bytes frcm the FAM module.
S/INL
INLSET ORDIN
INlSET
CDN RE.ArKFI +
READKFI
READ KFI
During execution vT a write ordei or checkwrite order, INL
is direct set if an at iempt is made:: t.') transfer data from the
K-registcr to the D-register (DXi< ~rue) after CDN has been
set, the FAM modu:e has been e:'P.!Jtif!d (REMPTYtrue), and
the preamble has be-en written (NWPRE true). These con·tio. ns exist cfter the last data bY:t: has been stored in the
·giste. followin~ the removal o~ 011 valid data bytes
m the FAM module and after a count done terminal order
has been received from the lOP.
i
M/INL
INLM
INLM
CYCLER REMFTY CDN NWPRE
DXK NKFID
4-80 INTERFACE TYPE LOGIC
4-81
Byte Width logic
The data path between the lOP and the EP RAD controller
may be one, two, or four bytes wide. For any byte width,
data bytes are exchanged on a one -byte interface during
execution of seek orders and sense orders. Durin"g execution of read orders, ",'rite orders, or checkwrite orders,
data bytes may be transferred one, two, or f00r bytes at a
time, depending on the states of signals /EDX2/ and /EDX4/
4-80
from the lOP. (See figure 4-21.) 'v'vhen the controller is
service-connected (FSC true), signals /DX2/ and /DX4/
are sent to the lOP to indicate byte width, under control
of signa I WIDE which is true during execution ofY/rite orders,
read orders, and checkwrite orders (VYRCH true). Signals
BYTl ID, BYT2ID, and BYT 410 are used internally during
data transfers to control operations of the a-register, 1register, and related registers.
4-82 FAO Type Logic
Signals /TYPO/ and /TYP1/, which are accepted from the
addressed RAD storage unit, indicate the storage capacity
of the addressed RAD. For an EP RAD storage unit, both
signals are rrue and signal EXT is true.
EXT
TYPOR TYP1R
TYPOR
/TYPol
TYPl R
/TYP1/
Signet EXT controls operations within the controller. if
EXT is truo?, rea:!/write clock signal RWCK is nominally
3 MHz; if EXT is false, read/write clock signal RWCK is
nominal!y 1.5 MHz. (See paragraph 4-55. )
For an EP RAD storage unit, the B-counter counts 1024bytes per sector. (See" paragraph 4-56.) For other ty:,es of
RP-.D storage units, the B-·counter is preset with a '.I0iJe of
1 010 011 GOO XXX (decimal 664) and counts 360 bytes per
sector.
S/BOO
~X1MED
S/BD2
PRE BXl MED + •..
RWE NEXT
PRE BX1MED +
PRE BX1MED +
S!B06
PRE BX1MED +
For an EP RAD storage unit, there are 12 sectors per !"E:>'Olution; for other RAD storage units, there ere 16 secrOI~ per
revolution. Therefore, signal LASTSECT is erode true: fore
count of ~ 011, if EXT is true.
LASTSECT
AN10TYP2
ANOR AN10TYP2 AN2R AN3R
AN1R+ EXT
(Signal LASTSECT is used only by PET logic.)
4-83 OFFUI'JE OPERATION
Peripheral Eguipment Tester Model 7901 (PET) can be used
either to monitor operation of the EP RAD controller or to
simulate rop inputs to the EP RAD cordroller. In either
XDS 901565
Paragraph 4-84
;tDX2/~
17
GND~
BYT2lDD
/Dx21
EDX2
EDX4~
25B
14
DATA
12
DATA~ 15
25B
J..,/-
WRCH~
NWIDE
23
~~BYT1ID
GND~44
GND~
16B
EDX4
37
I
;tDX4/~
B'(T!:IDD
--~-
EDX2
I
ED XLi
~c
1
0
0
1
1
BYTlID
I
I
1
0
0
J
BYT21D
(NOTE)
0
1
0
1----
BYT410
(NOTE~ _
rl
-t>- ID)~41
DATA 5'GNAlS
_.
IDAO/ - IDA7/
IDAO/ - /DA7/
/DBO/
/DAO/
/D~O/
/DCO/
- /DB7/
- /DA7/
- /DB7/
- /DC7/
/000/ - /Du7/
NOTE: BYT2lD OR BYT HI) TRUE ONLY WHEN WIDE IS TRUE
~f)1 ~65A.
Figure 4-21.
425
Byte Wi:lth Circuits, Logic Diagram
case, the PET mlJst be connected to the EP RAe controller
through two cable connectors, as indicated in figure 7-5.
VVhen the PET is used to moy,itor operation of the controller,
indicators on the PET pane: read selected signals of the controller during online operation. \. ./hen PET is used to simI.) late lOP inputs, no RAD stcrage unit attached to the controller is accessible to the lOP.
4-84 Online/Offl ine Control (See figure 4-22)
The EP RAD controller is placed in the online state bysetting the switch on the LT25 module (location C23 in figure
7-5) to the 1 position. This action connects the PT18S
sigr,(]1 to ground and energizes relays in the A-117 module
(location C26 in figure 7-5). After these relo)'s are energized, signal NINI is connected to ground an": ~ignal INI
is dic:con:1ected from ground and allowed to go llJe. After
signalINI is hue, signal INC becomes true and signa! NINC
becomes false.
When the switch is placed in the 0 position, si:Jnal PT18S
is open and two reiays in the AT17 mooule are ceenergized
in sequence, causing signals INC and INI to go false in
sequence and shortingsignal AVI rosignal AVOto complete
the priority circuit to the :lcxt controller in ~equencc. When
signal INl becomes false, the controller is effectively
4-81
XDS 901565
Paragraphs 4-85 to 4-86
START OF
START OF
CONNECT SEQUENCE
DISCONNECT SEQUENCE
PT18*
INl
-1
r-
-III
',I----'r- 5 . 8 MS--t
________~.J~----------Ill
I
1_________
5 MS
--11--0.5
I
MS
--11-- 120 l!S
----~III
1--1
MS
'I
I
1
I
____~i______
III--~-
---------,W
----ur-----I;fI
AVO
J--
I
_____--1--. P-50-I-l-S----I:~
AVl
4.2 MS
II~--~b-.--I--1.6MS--
NINe
1!--0.5
I'-:-I-----~ir~-------.....,I
I'iINI
INC
(J.r-----------
(
L--________
--11--
500 I-lS
---l
l--700 pS
*CONTROLL~[)
BY TOGGLE SWITCH
IN MODULi: L. T25
90:n7 IJA.331
~------.------------------.-------------------------------------------------------------------.-----
Figure 4-22.
Connect-Disconnect Ti:r.lng Diagram
disconnected from the lOP interface because signal INi
grounds the following signals: A\lOD, DCA, DORD, EDD,
FROD through FR7D, FSLD, HIPD, HPSD, lCD, lORD, 000
through 007, RSAR, RSD, NRSTR, and SCD.
Signal NINI, which is true, direct resets service connect
flip-flop FSC.
E/FSC = NINI + ...
4-85 Reset Control (See figure 4-23)
Control flip-flops of the EP RAD controller may be reset by
manually-controlled signals or by computer-controlled signals. The error flip-flops (CER, PER, RER, SUN, and WPV)
,and SCR are reset by a halt inpl't/output signal (tHOU),
"whether the HIO is controlled by the computer program or
by an offline test. These flip-flops are also reset by
4-82
DCBSET d the start of an input/output operation. At the
end of a, input/output operation, D~B is reset ar.:! ~auses
one group of flip-fops to be reset. Computer-controlled
signa I RS'!"R, which can also be generated at a pushbutton
on the computer control panel, generates a true l\AP..NRST
signal. This signal resets the error flip-flops, flip-flop SCR,
and a grc,Jp of fI ip-f1ops that inc I udes DeB. Therf'fore,
signal RSTR resets all control flip-flops of the EP RAD contro!ler. Signal MANRST is also contiol!ed by the FET
through P::T reset signal RSTP. When the EP RAD controller is operating off! ine (PET irue), MANRST is tnre whenever RSTP is true.
4-86 PET Operations
When the PET is connected to the controller, the signals
listed in table 4-6 are available at the PET connectors. If
the PET is used to monitor online operation of the controller,
CYCLE/e
"
c
NPHFSCYC
-.
PHFS
FNTP
(Q
ro
HIOU
~
FLIP-FLOPS
I
N
t.,,)
;;0
..,.
(1)
('I)
IH I
0/-[::>
,DVSEL
RESET
-+
DCBSET
n
0
~
MANRST
2-
CER
PER
, RER
SCR
SUN
WPV
~
~
3
('1)
-,
lOP
FLIP-FLOPS
FLIP-FLOPS
D-
r-
0
co
0
0
0"
-.0
0
01
"'0
:!':
X
0
VI
RSTP
MANRST
'.0
a
3
/RST/
RSTR
ALT
CON
elL
eLK
DCB
OPER
NPHFS
PHFSZ
PHFSL
SECPD
SPE
UO
Ul
U2
UNE
NDCB
ORDO
BCE
PHRS,
BKO
PHTO
BKl
' PRE
DAR
RK4
DATA
RWE
DSE
RWP
DSL
EDISET3 SCN
' SEN
IN
:, TSE
INL
XDS 901565
Table 4-6.
Signal
,
PET Interface Control Signals
Source
Descri pti on
AlTP
32A-21
Alternate order control
CNTRClKP
30A-14
Clock signal to the PET internal counter
DPOO
30A-8
OPOl
30A-7
DP02
30A-6
OP03
30A-5
DP04
30A-4
[)P05
30A-3
DP06
30A-2
DP07
30A-l
Simulated data byte stored in the J·-register
!
~
32A-20
Error s;op signal that enables ~:-;It if error is detected
32A-39
Function strobe sirnu laHon
32A-26
Halt input/output function indicato!" simulation
32A-l9
Indicator signal control
32A-36
Onlint-/offl ine control
ORur-l
32A-22
Order
ORDP2
32A-23
Order bit 2 simulation
ORDP3
32A-24
Order bit 3 simulation
'ORDP4
32A-25
Order bit 4 simulation
REPEAT
32A-42
ContinL,OlJS cyc Ie control
RSTP
32A-40
Reset :;191101 simulation
SGlPH
32A-18
Single--phase operation control
SGlPHCK
32A-43
Sinsle-pnase operation clock
SGlTRKP
32A-41
Single-Hack operation control
SlOP
32A-29
Start input/output function indicator simulation
TOVP
32A-27
Test de" ice function indicator simulation
TIOP
32A-28
Test input/output function indicator simulation
ERSTOP
I
FSPS
HIOP
INDUP
lOP
i
I
II
oil
1 simulation
f
I
(Continued)
4-84·
I
Paragraph 4-87
XDS 901565
Table 4-6.
PET Interface Control Signals (Cont. )
Description
Signal
Source
TRKRST
30A-15
True when PET interno I counter equa Is counter reset
switch settings of PET pane I
UASO
30A-12
Storage unit address bit 0 simuiation
UASl
30A-ll
Storage unit address bit 1 simulation
UAS2
30A-1O
Storage unit address bit 2 simulation
--
signal lOP is true and signal INDUP, controlled from the
PET panel, causes the signcds listed in table 4-7 to be read.
If the PET is used to controi offlin~ operation, signal lOP
is false and signal PEl is trlJe, uniess the PET reset signal
RSTP is generoted to reset the controller.
Signals DPOO through DP07 :;irnu late data bytes and provide
inputs to the J-register during data out service cycles
(DATAOUT true).
DPOO
JOO
Ji~[)P
+ ...
= FNTP HIOP
+ HIOU NPHFSCYC + .•.
HIOU
FNTP
FSP PET
NPHFSCYC
N(CYCLE/C PHFS)
TIOU -
FNTP TIOP
+ TIOU NPHFSCYC +
FNTP TDVP
TDVU
+ TDVU NPHFSCYC + ...
JXl)P
DATAOUT RWRITE-2 TRS060 PET
FNTP SlOP
SIOU
JOl
J07
+ SIOU NPHFSCYC +
DPOl JXDP + .••
DP07 JXDP + .••
These signals replace JOP Juta for simulated ./rite orders,
checkwrite orders, and seek orders. For simu lated sense
orders and rpad orders, datt i~ accepted from the disc fi Ie
sir.'li lor to Olai ine operation.
4-87 iOP SIMULATION. Vvl1en the PET simu lates lOP
signa Is, the controller responds as if the lOP were providing
the inputs. Inputs from the PET start the TCl rlela}' line.
(S.;~ figure 4-24.) Other operations follow ii: liormal sequence, as described in paragraph 4-20.
When signal PET is true, device controller cd~~res5 signal
DCAU is true to simulate a match of controlle:- ,:,ddress and
lOP acidress signa Is.
DCAU = PET +
Signals ORDPl through OR[)P4 sirP.u late bits of the order
code and are accepted by t!le order register under control
of alternate order signal A~ TP and the alternote order circuits.
Signal UASO through UAS:? simulate storage unit address
bits and are accepted by the U-register at the start of a
simulated input/output ooe:-ation.
SUOD
UAS0 PET +
SU1D
UAS2 PET +
(C/UO-C/U2)
DC3SET
Signals HlOU, TIOU, TDVU, and SIOU can be controlled
by signals HIOP, TIOP, TDVP, and SlOP to simuiate commands from the lOP. The simulated function strobe signal
from the PET is used to control operations.
The function strobe which starts execution of orders is controlled tLrcugh signal FSUi the request strobe ar-knowledge
signIJI from the lOP is simulated through signa' RSAUi service connection is controlled through signal FSC:U by service call flip-flop SCN. Function strobe sigr.(11 FSU can
be controlled by a pLI:;hbuiton on the PET pane I through
si£lI1al FSPS or by a combination of PET ~igna Is and controller
siS:lals.
PET NPHFSL (SCN + FSP)
FSU
FSP
FSPS + ..•
The fu~ction strobe is inhibited while the phase control
logi..; is in phase FSL since signai NPHFSL bec8mes false.
Additional service calls depend on the state of service call
flip-flop SeN, which is controlled through signal CDNPET.
CDNPET = PET LASTSECT POSTBS9 (TRKRST
+ SGLTRK) (EXT + .•• )
4-85
Pqragraphs 4-88 to 4-89
XDS 901565
Table 4-7. PET Interface Indication Signals
SIGNAL
--
SOURCE
DATA
If INDUP false
If INDUP true
INDOl
19A-02
DCB
DCB
IND02
19A-01
READ
CIL
IND03
19A-39
WRITE
DVOR
IND04
19A-42
CHWR
RER
IND05
25A-42
UNE
PER
IND06
25A-39
TOO
CER
IND07
25A-01
TOl
WPV
IND08
25A-02
T02
SUN
IND09
25A-07
T03
DATA
IN010
25A-09
T04
iN
IND11
25A-46
T05
PHTO
IND12
25A-21
T06
PHRSA
IND13
25A-14
T07
PHRS
IND14
25A-12
TOS
PHFSL
It-II) 15
25A-27
T09
PHFSZ
IND16
25A-26
T10
J
"
'Ahen the service call line is rai<"ed by SCN, the d~ta in
signals DPOD through DP07 '1rc accepted for data out
• ,dee cycles. For either data out or data in service
cycles, request strobe acknowledge signal RSA.U is simulated by signal RSAUEN.
RSAU = PET (BYTlID + NJFI + NDATAOUT)
4-88 SINGLE PHASE MOE?E. The phase flip-flops described in paragraph 4-22 can bc cycled through normal
phase sequences one phase at a time if signal SGlPH is
true. (See figure 4-24.) In this ~ase, signal CYClE/C,
which controls start of the Tel deloy line, is controlled
through signal CYCEN (refer to p.:.ragraph 4-21 for a
description of TCl delay line operation). Single phase
enable fI ip-flop SPE is direct set whenever a TCl delay
line cycle occurs. If signal SGlPli is true, CYClE/C is
inhibited by a false CYCEN signai until SPE is reset. There-~fore, the Tel delay line cannot oe started until SPE is reset.
A true single phase c lock signa I SGlPHC K is generated by
a PET panel pushbutton. As this signal goes false, SPE is
4-86
I
PHFS
,--
reset and CYCLE/C is enabled. In tLis manner, the r·hases
associatp.n \'v'ith any lOP command or ony service cvc!e can
be enabl?d one at a time.
4-89 ALTERNATE ORDERS ,~1I0DE. I he PET can couse the
controller .0 either ~xecute the order encoded by ~jGnals
ORDPl ii'lrough ORDP4 Qr alternate execution of thut order
with executior. of a write order. For execution of i+.e order
encoded i"l signals ORDP1 through ORDP4, signol AU 0 b
false and the PET order code is stored during phase R~A of
the order out service cycle as for online operation.
M/ORDO
ORDXPET
ORDXPET
PHRSAOO PET lCSOOO-3
ORDl
ORDPl ORDXPET + •••
ORD2
ORDP2A ORDXPET + ..•
ORDP2A
ORDP2 AlTORD
All0RD
NAlTP + •••
XDS 901565
TC51OO-3
SGLPH
M
GND
S
SGLPHCK
C
(TRUE)
R
CYCEN
SPE
FF
CYCLE/C
0
N5PE
E
lOP
MANRST
~T22
~
CYCSET
IOP~CL050
DCAI)
~::~
~[~~_____________PE~T__ ~~
SCN-L,/
BSYCU
PHrSLT
c=
F S P D -_ _ _ _ _ _ _F_N_T_P_
CYCL~~:~.
O /~_.,......-l.;..;-T.;;..S;.;.HU:::....-_-_~
PET-
PHFS~·----N-P_HF:....;S-C;yCI
[
LOGIC
)-~
FSCU
PHFSL~ _ _ _--=...:..:.:..:::..::.:...
SCN----t___~/~
l - -_ _. .;R.;,: S.:.-;A.; :;. U
_ _ _~
PET--r~
DATAOUT
JFI
NBYTl ID
Dtll~LUNE
RSAUEN
,
J
90i565A.427/1
Figure 4--24.
PET Interface Circuits, Simplified Logic Diagram (Sheet 1 of 2)
4-87
XDS 901565
NSCNMENl
LASTSECTD
PET
----.
POSTB89
CD~:~==1~[____~--N_C_D_N_P_E~T--_~___~
SGLTRK
TRKRST
Bl0
NCDN
I - - + - - - -......NSCNMEN
EXT
NUNE--~----~
SCNMEN2NDATA- '---_
I--+-----....;."'..;.:~r...:::.s~p--C>o - - , - - - - - - - - I 1 J I t 1 > - FSP
FSPS
NSct~
PHF:;l-V----~
__----~r~S,POCSL~------~
SG LTR KP---I
I
""\.'--...----I~
'l-
~ SGLTRK
PET
>---i~FSU
PET--L../
FSR---r--'
I O P - L.........·
LASTSECT
NSGLTRK
RWE
RWP
REPEAT
TRKRST
~SXPEN
ORDXPET-
PET
901565A.427;2
Figure 4-24.
4-88
r-...-------.ChiTRCLKP
TRKRST
PET Interface Circuits; Simplified Logic Diagram (Sheet 2 of 2)
XDS 901565
ORDP3A ORDXPET + •••
ORD3
Paragraphs 4-90 to 4-92
NCNTRCLKP
LASTSECT RWE RWP NSGLTRK
+ ORDXPET TRKRST
ORDP3A
ORDP3 ALTORD
ORDP4A ORDXPET +
ORD4
ORDP4A
N(ALTORD NORDP4)
NORDP4
N(ORDP4 PET)
For the alternate orqer mode of opera.ti~n, signal AL TP is
true and the PET order code is stored only when flip-flop
ALTP is set.
ALTORD = ALT
+ ••.
When ALT is in the reset state, a write order (1 XOOl) is
stored. Flip-flop ALT changes state each time alternate
order clock signal ALTCK goes false.
S/ALT
4-91 SINGLE TRACK ~AODE. When the PET commands
the single track mode of operation, an order is executed
continually on a 12-sector track. For this mode of operation, the sequence of events which couse incrementation
of the track address must be inhibited, but increrl1entation
of the sector address muse be allowed. (See paragraph 4-70.)
Incrementation of the S-register is enabled through D07SET,
as i;, normal operation, but incrementation of tl-te T -register
is inhibited by a true SGLTRKP signal.
ND07SET
SGLTRK
NALT
611 B12 SGLTRK NBXO
+ ND7P15 NBXO
SGLTRKP PET
Thot :s, after four bi ts have been processed (B 11, B12), the
incrementing process is inh ibited by forcing D07SET fa Ise.
R/ALT
C/ALT
Thus, the counter is incremented as the last sector of a track
is processed and is cleared when a new order is stored after
T RKRST is true.
ALTCK
Clock signal ALTCK is true during phase RSA of each
order in service; cycle if PeT panel signal TRKRSTis true.
ALTCK
ALTCKEN
A~TCKEN ALTP
+ ...
Signa I SXPEN, which enables a transfer of data hom the
P-register to the T -register and S-registerl is inhibited by
signa I SGL TRK. (See figure 4-24. )
A count done signal is generated each time the Irtc;t sector
is detecled.
OKDIN PHRSA TRKRST
CDNPET = LASTSECT ·PET POSTB89 (SC'.TRK
Signal TRKRST is true whel' the PET internal counter state
mc;~hes the track address und the sector address switch
settings on the PET panel. Tile:refore, after each input/
output operation, Al T changes state and alternates a write
order with the order encoded or. the PET panel switches
after all data ha~ been prccf;ssed.
w'en signal ALTPis false, ALT is set by the first index
pulse and remains in the set state.
ALTCK = NALTP IPR + ...
4-90 COUNT DONE Slfv'\ULATION. The address at w:lich
an input/output operation begins is established by a single
phase seek order, during which a track address and a sector
address are loaded. A read order, write order, or checkwrite order is terminated urrler control of signal TRKRST,
which is generated by a counter in the controller.
CDNPET = LASTSECT PET POSTB89 (TRKRST
+ .•• ) (EXT + .•. )
Signal TRKRST is true when the state of a PET counter
matches a value set in PET panel switches. The counter is
incremented by signal CNTRCLKP, which is sent to the PET.
+ ..• )
Signal PRESET is inhibited if a write order is beir.;:: ::>x~cuted
so that writing is not ai lowed OP alternate rc\::'~utions,
thereby mee~;ng read/write head duty cycle sf.,,""cifications.
f'RESET = RWP NB 11 B10 B09 B06
N{AlTVP2 PET SGLTRK WRITE'
4-92 ERROR STOP MODE. When signal REPEAT from the
PET is true, the command chaini'lg signal is truro; causing
repetition of the order set into PET switches.
CCH
=
N(IOP DA3R) (REPEAT PET + •.. )
The funct i on strobe is genel ated under contre! of signa I
ERSTOP from the PET. (See figure 4-24.) Afrer the first
function strobe is generated by a true FSPS sig'ocl, no function ':lrobe is needed to continue service cycle~, provided
no unusua I end occurs.
FSU == PET NPHFSL (REPEAT NDCB UNE NERSTOP
+ FSPS)
If signal ERSTOP from the PET is false, signal NERSTOP is
true and an unusual end generates a new function strobe.
4-89
Paragraphs 4-93 to 4-95
XDS 901565
If signal ERSTOP from the PET is true, signal NERSTOP is
false. When on unusual end oc:curs, DCB is reset as for
online operation, and lack of a function strobe causes operation to stop. (The track address has been incremented.)
4-93 PHASE SEQUENCE CHARTS
The phase sequence charts describe the operation of the
controller for normal onJine response to signals from the
lOP. The emphasis is on the phase control circuits described in detai I in (Xlragraphs 4-20 through 4-35. Information is exchanged between the lOP and the controller as
these circuits cycle through a sequence of six phases (FS,
FSl, FSZ, RS, RSA, and TO), each of which is defined by
a flip-flop.
•
At certain times during a sequence of the phase control
circuit operations, signals are required from circuits asynhronous with tht phase controi circuits. The three asynronous timing circuits of the controller are:
a. The Tel delay line, which controls transfer of information between the rop and the controller
b. The TRL delay line, ..vhich controls transfer of data
bytes to and from the FAM module
c. The TDT dela)' line, which controls transfer of data
between the controller und the addressed storage unit
Data passing betweer. the lOP a'"ld the ac.iaressed storage
unit is c.ontroljed by vII three timing circuits during the
transfer process. Therefore r although detai Is of operation
of asynchronous circuits are not defined in the phase sequence charts, their relation to the operation of the phase
control circuits cannot be ignored. Sigr:.:tls originating
outside the phase control circuits, either in the 10 0 or in
asynchronous circuits of the con!roller, are identified in
•
e phase sequence charts.
the ready automatic state or may start a new order in service cycle, as determined by terminal order information.
Each of the four service cycles (order out, data out, data
in, and order in) is identified by the states of two flip-flops.
For any service cycle, the controller passes through phases
FS, FSZ, and FSL, fo! lowed by some sequence of phases RS
and RSA, followed by phase TO. During any TO phase,
the con~roller may receive information from the lOP wh ich
indica!cs than on interrupt has occurred, that all data has
been transferred, or that the lOP has commanded an unusual
end. If an error is detected by circuits of the controller,
an order in service cycle wi II be requested during the next
TO phose in sequence. During phose TO of or. orr!cr in
service cycle, the controi ler may reee ive a command chai ning sigi1aL This signal causes the controller to start a new
order out service cycle, rather than return to the reody
automc.tic state .
Therefore, operation of the controller consists of passing
from the ready automatic ~tf']te to the busy automatic state
in respcnse to lOP signals, processing data, and r~krning
to the ready automatic state. For execution of se€~ orders,
write o:-ders, and checkwri te orders, data is transfer:-ed from
the lOP in a succession of data out service cycie:;. For
execution of sense orders or read orders, data is trl...mferred
to the lOP in a succession of data in service cycles. Each
complete input/output operation begins with on or':Jer out
service c~'r!e and ends with an order in service cy~ic.
4-94
!..C P Command
Sequences
In response to or. lOP command, the control ler provides
informC!~·hr. on function rer~onse lines /FRO/ throu~h /FR7/
and or. Jato or order lines /DOR/ and IIOR. The infurmotion p:-I')vided and the operations which take place within
the contiOlle: depend upon the type of lOP commG.,d, as
indicatp.d in tables 4-8 through 4-12 .
4-95 Order Oul Sequence
. r normal online operation, the (.ontroller is initially in
the ready automatic state. When in this state, the controller responds to any lOP command (AIO. HIO, SIO,
TIO, or TDV) by passing through phases FS, FSZ, and FS l,
and then returnif'l~ i·o phose FS. If the command is on SIO
and if the SIO is acceptzd, the controller enters the busy
automat:c state Cind remains in this state until completion
of one or more input/output operations or. until an error
occurs. Upon entering the busy automatic state, the controller requests an order out servic:;; cycle, during wh ich
the controller stores the order transmitted from the ~OP.
After the order is stored, the controller wi II request a
·sequence of data out serv ice cycles or a sequence of data
in service cycles. If no error occurs during these service
cycles, a signal from the lOP indicates a count done after
all data has been transferred, after which the controller
:, requests on order in service cycle. During the order in
service cycle, information issent to the lOP. Following
the order in service cycle, the controller may return to
4-90
Each inp'Jt/output operation begins with an order out service cyde. An order cut service cycle fo! lows an ac.:.epted
SIO command or an order in service cycle during which a
command chaining signal is accepted from the lOP. During
an order C:Jt service cycle, an order is read from lor data
lines /U.". . 3/ through /DA7/ and stored in the order register
(ORDO through ORD4), as indicated in table 4-13. If the
order in~i::ates seek, write, or checkwrite, subseqtJ ·!nt s~r
vice cycies will be data out service cycles; if the orcier is .
sense or read, subsequent service cycles will be data in
service cycles. Thus, crder out service cycles nOr-!lally
begin with the (DATA, IN) flip-flops in state (0, 0) and
end with these fl ip-flops in state (1, 0) or (l, i). If the
order is one of the il legal codes or if it is a write order
which addresses a write-protected track, an error wili be
detected. The (DATA, IN) flip-flops wil·1 be placed in
the (0, 1) state, and the error wi II be reported during the
order in service cycle which fo! lows.
XDS 901565
Table 4-8. AIO Command, Phq5e Sequence Chart
Phase
Function Performed
Interrupt
Pending
Raise interrupt call line ICD
when CIl set
ICD
= LIl
Enable TCl delay line
NAIO R CIL INC
+ AIOR INI Ul NRSTR
=
CYClE/C DClSTARTl
+
CYClE/C
=
lOP CYCSET +
DClSTARTl
=
FSU PHFS AIOC +
. AIOC
=
AIOM AIOR AVIR + .••
AIOM
=
NHPIL LIl +
=
CILRST
=
AIOC +
C/CIl
=
NTCSOOO
S/NPHFS
=
~'HFS
C/NPHfS
=
TCS100-3
S/PHFSZ
=
PHFS
C/PHFSL
=
fCS100-3
DCl
-- CYC:"E/C PHFSZ + •••
R/PHFSZ
=
...
C/PHF5Z
=
rC51 00-3
S/PHFSl
=
PHFSZ
Enter phase FSL
C/PHFSl
=
TCS100-3
OPJ:R may bG s",t, but
no significance for AIO
DCl
=
CYClE/C DCLSTART3
TCl delay line enabled
when functio:1 strobe
false
DCl
f
R~set
CIL
R/CIl
I
CIlRST
I
I
Set NPHFS
Sei PHFSZ
I
I!
CIL set by terminal order
and remains in set state
until AIO response received from lOP
=
Ul
FS
Comments
Signals Involved
...
...
...
CyeSET latched true.
Delay line input when
AIOR signal received
from lOP (on~y for device controller with
LIL true)
...
...
End phase FS
I
Enter phase FSZ
--
I
FSZ
I Enable TCl ci ·Iay line
Ii
Reset PHF5Z
II
f---"
I
FSL
End phase FSZ
-
Enable TCl d81ay line
-.
DCLSTART3
FROD
Enable function response
signals
I
. ..
=
NFSU PHFSl + •.•
=
BSYC SWAO +
...
(FROD-FR3D) (.ontain
device controller address
I
(Continued)
4-91
XDS 901565
Figure 4-8. AIO Command, Phase Sequence Chart (Cont.)
Phose
Signa Is lnvo Ived
Function Perfonned
FSL
(Cont. )
BSYC
= AVIR AIOR AIOM PHFSL-1
+
Enable status signals
...
FR1D
= BSYC SWA1 +
...
FR2D
= BSYC
SVVA2 +
...
FR3D
= BSYC SWA3 +
...
FR4D.
= BSYC GND +
...
FR5D
= BSYC UO +
...
FR6D
= BSYC Ul +
...
FR7D
= . BSYC U2 +
...
DAD
- 000
+
= OXAIOST RER +
OXAIOST
= ,6.IOC FSU
= 002 +
002
003
lORD
IORDEN
(FR5D-FR7D) contain
device address
...
...
...
= PHFSL !ORDEN +
...
NIORD::~~l
+
...
NIORDENl = AIOC NFAULT +
NFAULT
DORD
DORDEN
Reset PHFSL
Reset NPHFS
"
4-92
lORD true if all status
signals false. Defi '''~S
normal I/o interrupi"
...
= NRER NSUN NWPV
= DORDEN PHFSL +
_. AlOe +
R/PHFSL
=
...
C/PHFSL
=
TCS100-3
R/NPHFS
= PHFSET
DORD always true
End phase FSL
= NFSCU PHFSL-l
FSCU
=
FSC lOP +
= TCS100-3
...
. ..
PHFSEl
C!NPHFS
...
= OXAIOST WPV +
:=
RER, SUN, WPY
indicate cause of
interrupt
...
= OXAIC.:)1 SUN +
= 003 .:.
DA3
FR4D always false
...
000
DA2
Enable condition coo . .
signals (lORD, DOP-j))
Comments
...
Enter phase FS (servi ce
connect fI ip-fiop FSC
not in set state)
j
XDS 901565
Table 4-9. HIO Command, Phase Sequence Chart
Phase
FS
Function Performed
Signa Is Involved
Comments
Enable TCl delay line
DCl
= CYClE/C DCLST ARTl
. '.
+
CYCLE/C
=
CYCSET lOP +
...
CYCSET latt::ned true.
lOP true unles!:: DC
is offl ine
DClSTARTl = FSU PHFS TTSH U DCAU
...
+
. FSU
...
+ ...
=
FSR lOP +
TTSHU
=
TTSH lOP
TTSH
=
HIOR +
DCAU
=
DC.A lOP +
...
...
I
R/OPER
=
PHt=S
C/OPER
=
NTCS080
S/NPHFS
= P~:FS
C/NPHFS
=
:C5100-3
S/PHFSZ
=
P!-ifS
C/PHFSZ
=
orCS 100-3
Enable TCL delay Ii.le
DCL
=
C ,(CLE/C PHFSZ + .•.
Sample DVTR signal from
addressed sel~ction unit
SlOPER
=
DVTR OPERSET
Reset
Set NPHFS
Set PHFSZ
FSZ
OPERSET
Reset PHFSZ
Set PHFSL
FSL
--
CPU processes HIO instruction,
and lOP generates true HIOR
function indicator signa I and
true FSR function strobe
Enable TCl delay line
Prepare to sample signai DVTR du-ing phuse
FSZ
End. phase
I
=
NTCS080
R/PHFSZ
=
...
C/PHFSZ
=
TCS100-3
S/PHFSl
=
PHFSZ
C/PHFSl
=
TCS100-3
DeL
=
CYCLE/C DCLSTART3
+
...
F~
Enter phase
~sz
Set OPER if CVl R true,
indicating RAD is operoting
= TT"HU PHFSZ
C/OPER
DCA true if (S'ilACSWA3) malch-:;:s (DAOR0".3 R)
End phase F)Z
I
Enter phase FSL
TCL deloy line enabled
at end of function strobe
I
(Continued)
4-93
XDS 901565
Figure 4-9. HIO Command, Phase Sequence Chart (Cont.)
Function Performed
Phase
FSl
(Cont. )
Enable function response
signals
FR1D
FR2D
0
0
Device ready
1
1
Device busy
0
1
Devic.c not
operational
. Comments
Signals Involved
FROD
...
-- BFSD TSH CIl +
FROD true if interrupt
pending (CIl)
BFSD
= FSLD
FSlD
= TTSH DCA PHFSl-l
PHFSL-l
=
PHfSL
=
BFSD TSH DVBSY +
=
DCB DVSEL
-
BFSD rSH STSH02 + .•.
FR1D
DVBSY
FR2D
...
DVSEL true if (UO-U2)
matches (DA5R-DA.7R),
indicating device
selected
-
STSH02
FR5D
FR6D
0
0
Device con~
troller ready
1
1
DevicE:: contro! br busy
Enable condition corie
signals (lORD, DURO)
= DVeSY + NOPER
FR3D
= BFSD TSH DVTR +
FR4D
=
BFSD TSH UNE +
...
...
FR5D
=
BFSD TSH DCI) +
...
FR6D
= BFSD TSH DCB +
...
FR7D
=
BFSD TSH GND +
lORD
=
IORDEN PHFSL +
IORDEN
= NIORDEi"l +
NIORDENl
=
DORD
DORDEN
Clear flip-flops CER, PER,
RER, SeR, SUI"-J, a~d WPV
E/CER
RESET
HIOU
= OPER +
RESET
=
DVSEL HrOU PHFSl
+
-4-94
...
= HIOR lOP + ...
E/PER
= RESET
E/RER
=
E/SCR
= RESET
E/WPV
RESET
RESET
=
RESET
FR7D always false
I
I,
...
=
E/SUN
Reset DCB
...
+ ...
NDVB:;Y HIOU +
~
Unusual end (UNE)
...
...
...
= DORDEN PHFSL
Device test (OVT)
I
I
IOR~) true if addressed
device is not busy
(ND-/BSY)
DORD true if addres~ed
device is operating
(OPER)
DVSEL true if (UO- U2)
matches {DA5R-DA7R}
XDS 901565
Table 4-9. HIO Command, Phose Sequence Chart (Cont.)
Signals Involved
Function Performed
Phose
Reset DCB
FSL
(Cont. )
R/DCB
DCBRST
C/DCB
=
=
=
Comments
DCBRST
RESET +
...
NTCS080
Flip-flops are direct
reset by equation of
form E/XXXX == NDCB
Clear flip-flops DCE, BKO,
BK1, DAR, DATA, DSE,
DSl, EDISET3, IN, INL,
ORDO, PHRS, PHRSA,
PHTO, PRE, RWE, RWP,
SCN, SEN, TSE
Reset PHFSL
R/PHFSL
=
...
C/PHFSL
=
TCS100-3
R/NPHFS
=
PHFSET
PHFSET
=
NFSCU PHFSL-1
FSCU
=
FSC lOP +
C/NPHFS
=
TCS100-2
End phase FSL
Enter phase FS (flipflop FSC can be set
only by SIO ccmmand)
...
I
I
-.I.-
Table 4-10. SIO Command, Phase Sequence Chart
Function Performed
Phase
CPU process~s SIO
instruction, and lOP
3enerates tn 'e function indica~or signal
SIOR and func+ion
strobe signai FSR.....:;::>
FS
A1:tZ 0
~
lyelZ=
DCL
Enable TCL de lav line
CYCLE/C DCLSTART1
+
...
CYCLE/C
-- Cyr:SET lOP +
DCLSTARTl
=
I
Reset OPER
-
...
CYCSET latci-1E;d true.
DCA true if (~'NAOSWA3) matc~es (DAORDA3R). lOP true unless DC is off!ine
FSU PHFS TTSHU DCAU
t
~
Commer.rs
Signals Involved
...
FSU
=
FSR lOP +
DCAU
=
DCA lOP +
TTSHU
= lTSH
TTSH
-- SiOR
...
...
JOP + ...
+ ...
R/OPER
=
PHFS
C/OPER
=
NTCS080
Prepare to semple
signa! DVTR d'!ring
phase FSZ
I
(Continued)
4-95
XDS 90i565
Table 4-10. SIO Command, Phase Sequence Chart (Cont.)
Function Performed
~hase
FS
(Cont. )
Set NPHFS
Set PHFSZ
FSZ
Enable TCl delay lif'e
I
Signals Involved
S/NPHFS
= PHFS
C/NPHFS
= TCS100-3
SjPHFSZ
= PHFS
C/PHFSZ
= TCS100-3
DCl
= CYClE/t PHFSZ
Comments
End phase FS
Enter phase FSZ
+ •.•
-
Sample DVTR signal from
se lection unit
= DVTR OPERSET
SlOPER
OPERSET
~
Reset PHFSZ
Set PHFSl
Enable Tel de lay
ljtie
Set OPER if DVTR true,
indicating RAD is operating
= TTSHU PHFSZ
C/OPER
= NTCSOSC
R/PHFSZ
=
C/PHFSZ
= TCS·'OO-3
S/PHFSl
= PHFSZ
C/PHFSl
= TCS100-3
DCl
= CYCLE/C DCLSTART3
...
End phase FSZ
Enter phase FSl
+ ••.
,"
DCLSTART3
= PHFSL NFSU +
I
...
TCl de!e}' line enc:,:ed
at enG of function si:0be
FSR
---.
FSl
Enable function re.:;ponse
signals
= BFSD TSH Cll +
FROD
BFSD
•
FSlD
= FSlD
= TTSH DCA PHFSl-l
+
TTSH
TSH
FR1 D FR2D
FR1D
0
0
Device ready
1
1
Device busy
0
1
Devic(.; not
operaHonal
...
= SIOR -;- ...
= DCA (SIOR +
:::
... )
BFSD TSH DVBSY
+ •••
DVBSY
= DeB DVSEl
= BFSD
FR2D
iSH ST5H02
+ .••
.~
STSH02
= DVBSY + NOPER
(Continued)
4-96
...
FROD hue if interrupt
pending (ell)
XDS 901565
Table 4-10.
Phase
SIO Command, Phase Sequence Chart (Cont.)
Function Performed
Signals Involved
FSL
Comments
FR3D
=
BFSD TSH DVTR
FR4D
=
BFSD TSH UNE +
FR5D
=
BFSD TSH DCB +
FR6D
=
BFSD TSH
FR7D
=
BFSD TSH
lORD
= PHFSl IORDEN
(Cont. )
FR..5D
FR6D
0
0
Device cont.oller ready
1
1
Davice controller busy
Enable condition code
signals (lORD, DORD)
!
lORD DORD
;
+
...
--
DCBSET
= OPER SIOPOSS PHFSL
Not operational
0
1
SIOPOSS = NCIL NDCB SIOU
Interrupt pending
or busy
DORD
= PHFSL DORDEN +
1
SIO accepted
DORDEN = OPtR +
SIO aeeepiod, set DCB
I
Ilf
S/DCB
IC/DCB
I E/CER
I
DCBSET, deor flip-flops
CER, PER, RE 1\( SCR, SUN,
and 'h?V
I
I
I
I
DC5SET
=
NTCS080
...
...
II
= REStT
RESET
--
DCBSET +
t
E/PER
= RESET
I
E/RER
=
RES~T
E/SCR
--
RESET
~
I
=
FR7D a Iways fa ise
...
IORDEN
0
1
...
...
DCB + ...
GND + ...
C
I
IIf
DCBSET +
FR3D true if device
test (DVfR) true;
FR4D true if unusual
end (UNE) true
...
I
I
I
I
!
I
I
IE/SUN
= RESEl
E/WPV
RESET
Sluo
SUO!)
Device address retained
in (UO-U2) dL·ring I/O
DA5R lOP + •••
operation
I
If DeBSET,
~~crE-
device
address in (UO-U2) at end
of phase FSL
SUOD
SU1D
SUl
SU1D
DA6R lOP +
s/u2
DA7R lOP +
(C/UO -C/U2)
DCBSET
(Coni inued)
4-97
XDS 901565
Table 4-10. SIO Cc-mmond, Phase Sequence Chart (Cont.)
Phase
Function Performed
FSl
(Cont. )
Reset PHFSL
Signals Involved
Reset I'-JPHFS
R/PHFSl
=
...
C/PHFSl
=
1CS100-3
R/NPHFS
=
PHfSET
=
NFSCU PHFSl-l +
=
1CS100-3
PHFSET
C/NPHFS
-Comments
End phaseFSl
Enter phase FS
...
Table 4-11. TDV Command, Phase Sequence Chart
Phase
FS
Function Performed
Signals In vohed
"-
CPU processes TDV instruction,
and lOP generates true TDVR
function indicator signa I and
trve FSR functior. s~robe.
Enable TCl delay I ;ile
= CY Cu::/c DCl STARTl
Del
+
CYCLE/C
-==
CYC~ET lOP" ...
DCLSTARTl
=
FS U PHfS 1TSH U DCAU
+
FSU
=
FS R Ie? + •.•
DCAU
=
DC A :OP +
TTSHU
= 10 P
TTSH
= 1D VR
C/OPER
=
S/NPHFS
= PH FS
C/NPHFS
= TC S100-3
S/PHFSZ
= PH FS
C/PHFSZ
=
TC S100-3
Enable TCl delay line
DCl
-
CY ClE/C PHFSZ + .••
Sample DV1R signal from
selection unit
SlOPER
=
DV TR OPERSET
=.
TTS HU PHFSZ
Set PHFSZ
O?ERSET
Prepare to sample ~ ignal
DVTR during phase FSZ
NT
(Continued)
4-98
+
= PH FS
Set NPHFS
CYCSET latched hue.
lOP true unless DC is
offl jne. DCA true if
(SWAO-SWA3) mc.tches
(DAOR-DA3R)
·i75H +
R/OPER
Reset OPER
FS7.
Comments
End phase FS
Enter phase FSZ
Set OPER if DVTR true,
indicating RAD is operating
XDS 901565
.
Table 4-11. TDV Command, Phase Seauence Chart (Cont.)
Function Performed
Phase
FSZ
(Cont. )
Reset PHFSZ
Set PHFSl
FSl
Enable TCL
d~lay
Comments
Signals Involved
line
elOPER
=
NTCS080
R/PHFSZ
=
...
C/PHFSZ
=
TCS100-3
S/PHFSl
=
PHFSZ
C/PHFSL
=
TCS100-3
DCl
=
CYClE/C
DClSTART3 +
=
PHFSl NFSU +
=
(TDVR DCA FSD) RER
+
DClSTART3
I
FROD
Enable funcl:v", response
signals
I
End phase FSZ
Enter phase FSL
...
De lay line enabled at
end of functior. strobe
...
...
FROD true for rate
error
(TDVR DCA FSD) -- DCA FSlD TDVR
I
I
I
I
Enable condiLon code signals
(lORD, DORD)
I
I
I
FSLD
-
PHFSl-l TTSH DCA
+
PHFSl-l
=
PHFSL
FR2D
=
(TDVR DCA FSD)
SUN + •••
FR2D trve if sector
unavai lable
FR3D
-
(TDVR DCA FSD)
WPV+
FR3D true if write protection violation
lORD
=
PHFSL IORDEN
+
lORD true if r.cne of
the error flip -flops in
set state
JORDEN
=
NIORDEN1 + •••
NIORDEN1
=
rDVU NFAULT
NFAULT
=
NRER NSUN NWPV
=
DORDEN PHFSL
+
=
OPER +
R/PHFSL
=
...
C/PHFSL
=
=
TCS100-3
PHFSET
=
NFSCU PHFSL-1
FSCU
=
FSC lOP +
=
TCS100-3
DORD
DORDEN
Reset PHFSL
Reset NPHFS
R/NPHFS
C/NPHFS
...
...
...
...
DORD true if devir;e
is operating
...
End phase PHFSL
PHFSET
...
En~er phase PHFS if
service connect flipflop FSC not ir. set
state
4-99
XDS 901565
Tobie 4-12. TIO Command, Phase Sequence Chart
Phase
FS
Function Performed
Signals Involved
Comments
CPU processes TIO instruc:tion,
and lOP generates true nOR
signal and FSR signal
Enable TCl delay line
= CYClE/C
Del
CYCSET latched true,
JOP true unless DC :5
offline. DCA true if
(SWAO-SWA3) matches
(DAOR-DA3R)
DClSTARTl
+ .. ,
CYCLE/C
= CyeSET
DCLSTARTl
=
FSU
TTSHU
= FSR lOP + . . .
= TT51-1 10? + . . .
DeAU
= DCA IO?
TT5H
RlOPER
= nOR + ..•
= PHFS
elOPER
= NTCS()80
S/NPHFS
=-
C/NPHFS
= TCS100-3
S/PHFSZ
= PHFS
C/PHFSZ
=
TCS10C,-3
Enable TCl de lay ;ine
DCl
=
CYCLE/C PrlFSZ +
Sample DVTR signe:! from
addressed se lection unit
SlOPER
=
DVTR 0;"cR5ET
Reset OPER
Set NPHFS
Set PHFSL
FSZ
OPERSET
Reset PHFSZ
Set PHFSl
FSU PHFS TTSHU DCAU
+ ...
= NTCSODQ
R/PHFSZ
=
C/PHFSZ
= TCS100<1
S/PHFSl
=
PHFSZ
=
TC5100-3
End phase FS
Enter phase FSZ
Set OPER if DVTR ;-r:;e,
indicating RAD is operating
...
End phase FSZ
Enter phase FSl
CYClE/C DClSTART3
+ ••.
DCLSTART3
:;::-
(Continued)
4-100
...
-
=
DCL
Prepare to sample signa I DVTR duri ng pk:se
FSZ
= TT5HU PHFSZ
... -
Enable TCl de lay Iii-Ie
+ ...
PHFS
C/OPER
C/pHFSL
FSL
lOP + , , •
PHFSl NFSU +
I
...
Tel delay line enablc,j
at end oi function strobe
XDS 901565
Table 4-12. lIO Command, Phase Sequence Chart (Cont.)
Function Performed
Phase
Signals Involved
=
BFSD TSH Cll + ••.
BFSD
-
FSLD
FSlD
=
TTSH DCA PHFSL-1
PHFSL-I
=
PHfSl
=
BFSD TSH DVBSY + •.•
=
DCB DVSEl
=
BFSD TSM STSH02 + •••
=
DVBSY + NOPER
FR3D
=
BFSD TSH DVTR + ...
Device test (DVTR)
FR4D
=
BFSD TSH UNE + •••
Unusua' end (UN E)
FR5D
-- BFSD TSH DeB
FR6D
-
BFSD TSH DCB + •••
FR7D
=
BFSD TSH GND + .•.
lORD
=
PHFSl 10RDEN + ••.
FROD
Enable function response
signals
FSL
(Cont.)
FRID FR2D
- -0
0
Device ready
1
1
Device busy
0
1
Device not
operational
FR1D
DVBSY
FR2D
STSH02
FR:;O
FR6D
0
0
Device conHuller ready
1
1
Device confro Iler bus)1 i
-- --
I
I
II
I
I
Enable condHion code
Comments
+ •••
I
lORD
I
DORD
-1
Ready for
SIO
0
0
Device not
operational
0
1
!nterrupt
pending or
DC busy
1
Reset PHFSL
Reset NPHFS
10 R0 true if i'.v ; nternot bus)" and
device operotlng
rup~,
signals
I
FROD true if interrupt
pending (CIl)
10RDEN
=
NIORDENl
=
NIORDENl + • . .
Nell NDCB OPER
nou
+ •••
=
=
lIOR lOP + .••
=
OPER + •••
DORD true if de\,ice
operating
R/PHFSl
=
...
End phase FSL
C/PHFSl
-
TCS10O-3
R/NPHFS
=
=
=
=
PHFSET
TIOU
DORD
DORDEN
PHFSET
FSCU
C/NPHFS
DORDEN PHFSl + •••
Enter phase FS
NFSCU PHFSL-I
fSC lOP + •••
TCS100-3
4-101
XDS 901565
Table 4-13. Order Out Service Cycle, Phas"e S"equence Chart
Phase
Function Performed
Signals Involved
Flip-flop NPHFS is
reset following SIO
or order in service
cycle
Device controller busy flipflop DCB has been set by
previously accepfed SIO.
Phose FS is entered following
SIO or following order inservice cycle in whkh command
chaining signa! was received
from lOP
FS
Comments
Direct set service call flipflop SeN
ORDOUT
=
NDATA NIN
M/SCN
=
PHFS DCB CYClE/C
N{I\t$CNMEN)
=
CyeSET lOP +
CYClE/C
...
CYCSETlatched true
lOP true when
is online
co~troller
N{NSCNMEN) = NDATA NRWE
NWCHW +
...
=
lSl
=
NASCR SeN INC
+
=
CYClE!C DClSTARTl
+
DClSTARTl
=
PHFS DeB BSYCU
+ ·
BSYCU
=
BSYC lOP +
BSYC
=
ASCM ASCR AVIR FSR
+
=
ORDOUT
=
N~ATA
C/CDN
=
NTCSOOO
FROD
=
BSYC SWAO +
FR1D
=
BSYC
FR2D
=
BSYC
FR3D
=
BSYC
FR4D
=
BSYc
FR5D
=
BSYC UO +
FR6D
=
BSYC Ul + •.•
I FR7D
=
BSYC U2 +
Raise service call line SCD
SCD
lSl
~
DCl
Start Tel delay line when
ASCR and FSR trup.
Reset flip-flop CDI',j
R/CDN
ORDOUT
Enable function wsponse
signals FROD through FR7D
I
(Conti nued)
4-102
·..
Service call line he id
true until lOP responds
with ASCR and FSR
...
..
...
·..
CDN set during pho<;p.
TO of last data trar.:;fel
of previous order
NIN
...
SWAl + ...
SWA2 + ...
SWA3 + ...
GRD . . ..
+
...
...
(FROD-FR3D) encoJe device controller address
FR4D always false
(FRSD-FR7D) encode
device address
XDS 901565
Table 4-13. Order Out Service Cycle, Phase Sequence Chart (Cont.)
Phase
FS
(Cont. )
Function Performed
ASCB
=
ASCM ASCR AVIR FSR
(delayed NFSC)
C/FSC
=
NFSC FSR +
S/NPHFS
=
PHFS
C/NPHFS
=
TCS100-3
S/PHFSZ
=
PHFS
C/PHFSZ
=
TCS100-3
Enable TCl de lay line
DCl
=
CYClE/C PHFSZ +
Reset PHFSZ
R/PHFSZ
=
...
End phase FSZ
Set PHFSl
S/PHFSl
-- PHFSZ
Enter phase FS:'"
C/PHF~L
=
RSD
=
Set PHFSZ
-
FSL
Comments
=
Set service connect flip-flop
FSC as function strobe FSR
goes false
Set NPHFS
FSZ
Signals Involved
Raise request
RSD
~trobe
signal
Enable data or order signals,
request 0rdE'~ out service
cycle
Start TCl delay line
S/FSC
ASCB
End phase FS
Enter phase FSZ
RSET
=
PHFSl NIN +
FSCU
=
f~C
lORD
=
j:SC NIN +
DORD
=
F!:C NDATA +
DCl
=
Phase FSZ functions
not significa:.; for
order out s€";ice cycle
...
...
RSD latche:: uqtil request strobe acknowledge signal KSAR is
true
...
lOP +
...
(DATA, IN) f:ip-flops
in (0, 0) stat~_ at sto,-t
of I/O or at end of
order in service cyc Ie
...
C.'ClE/C i.JClSTART3
...
DClSTART3
=
PHFSl NFSU +
FSU
=
FSR lOP +
=
SCNRST
=
PHFSL +
C/SCN
=
TeS 100-3
R/pHFSL
=
...
R/SCN
...
FSC NRSAR ~FSCU RSD
)
+ NPHRSA RSET +
SCNRST
Reset PHFSl
...
TCS100-3
+
Reset service call flip-flop
SCN
FSC must be set before
RSD raised in phase FSl
TCl delay line started
...
...
...
SCN reset to ;,xevent
serv ice co I! un less required
End phase FSL
(Continued)
4-103
XDS 901565
Table 4-13. Order Out Service Cycle, Phase Sequence Chart (Cont.)
Function Performed
Phase
FSl
(Cont. )
Signals Invo!ved
Set PHRSA
=
PHRSASET FSCU
=
PHFSl NiN +
C/PHRSA
=
TCS100-3
DCl
=
CYCLE/C PHRSA RSAU
+
=
RSAR lOP +
S/PHRSA
PHRSASET
,.
RSA
Comments
Enter phase RSA
...
Wait for request strobe
acknowledge signal RSAR
from lOP
Start TCl delay line
RSAU
...
·..
I
I
Direct set SCR
M/SCR
=
PHRSAOO
Pre~et for control of
FAM circuits
Store order code
S/ORDO
=
DA3R lOP
Order code retained ~mti I
.... (der has been executed
(DA3 R-DA7 R)-{O RDO-O RD4)
C/ORDO
=
ORDXIOP
Z
(Order register bih) 0 1 2 3 4
(lOP data lines)
Writ.:: order
Read sector order
Seek
Checkwrite
!X X 0 0 1
ORDOUT
=
NDATA l'-iIN
0 ORDl
=
DA4R ORDXIOP +
...
0 ORD2
=
DA5R OKDXIOP +
...
ORD3
=
DA6R CRDXIOP +
0 1 0 0 ORD4
=
DA7R ORDXIOP +
!o XXl
h XXl
I
IX
Sense order
I
orde~X X
i
...
...
1 0 1
Preset byte counter to (1, 1)
= BKXl
M/BKO
BKXl
=
PHRSAOO +
Direct set flip-flop SCR
M/SCR
= BKXl
= PHRSAOC
Preset RK -counler
(S/RKOc·S/RK3)
=
M/RK4
= PHRSAOO
Preset JP-register to 1111
(JPO-JP3)
= PHRSAOO +
Preset KP--register to 1111
(KPO-KP3)
=
M/BKl
·..
PHRSAOO +
(Continuedj
Preset requ i red for
multiple-byte lOP
in~erface operations
SCR and RK-::ountc.
preset for control of
FAM circu its
ORDOUT
I,
4-104
TCSOOO-3
PHRSAOO - ORDOUT PHRSA
IxI X Xl
ord~r
PH~SA00
3 4 5 6 7
---r:-:---
Read record order
ORDXIOP -- lOP
·..
...
Presets determine FAM
location for first FAM
read cycle and first
FAt\'\ write cycle
--
XDS 901565
Table 4-13. Order Out Service Cycle, Phase Sequence Chart (Cont.)
Phase
Function Performed
RSA
(Cont. )
Signals Involved
...
Reset PHRSA
RjPHRSA
=
Set PHRS
SjPHRS
= PHRSET FSCU
PHRSET
Start TCl delay line as RSAR
goes false
RS
Comments
Enter phose RS
...
= PHRSA ;-
C/PHRS
= TCS100-3
DCl
= CYCLE/C DClSTART3
+
...
DClSTART3
=
PHR5 NDATA NRSAU
+
...
= FSc.. NRSAR (FSCU RSD
RSD
Raise request strobe line RSD
End phose RSA
+ PHRS TCSOOO-2 + ••• )
I
...
End phase RS
Reset PHRS
RjPHRS
=
Set PHTO
S/PHTO
= PHRS EO
Enter phase TO
ED
= EDSET TCSOOO-2
+ ED FSCU +
EDJ
= EDI
~5CU
I~PHRSA
+ ':DSETl
EDISETl
i
:
--+
TO
I
=
N~.u.TA
+
...
...
+
= TC5100-3
C/PHTO
--
I Start TCl dcklY line when
I request strobe acknowledge
signal RSAR
End data signel set
internally and bkhed
...
= CYCI.E/C DCLSTARTl
DCl
+
...
~rue
DClSTARTl
II
I
PHTO RSAU +
...
= DATASET NORDIN
SjDAT.A.
Set DATA
=
DATASET
= NSKSBK NCDN
NCDNPET NUNE
Ii
ORDIN
I
DA TA set regard less
of order code s~ored
=
I
ND/\TA IN
I
I
I
II If read order or sense order,
i
I
set IN
I
PHFSTOD
S/IN
I
I
I
I
= Ph~STOD
C/DATA
I
INSET
C/IN
--
= PHTO +
TCS 100-3
...
=
INSET ''-'ORDIN
=
NCJRD4 +
IN set for orders requi ring data transfer
to computer through
lOP
...
= PHFSTOD TCS 100-3
I
I
I
(Continued)
4-105
XDS 901565
Paragraph 4-96
Table 4-13. Order Out Service Cycle, Phase Sequence Chart (Cont.)
Signals Involved
Function Performed
Phase
TO
(Cont. )
Reset PHTO
R/PHTO
=
...
Reset NPHFS
R/NPHFS
=
PHFSET
PHFSET = PHTO +
C/NPHFS
=
Comments
-
End phose TO
Enter phose FS
...
TCS100 ..3
Terminal order operations
Refer to table 4-19
for terminal order
operations resultillg
i r. c rher than e}:~cution of order
I
4-96 Sense Order Sequence
are lis~(::d in table 4-14; a timing diagram is provided in
figure 4-25.
The sense order is executed if i-he sense order code
(00100) is stored in the order n~gister during an order out
service cycle. During execufion of a sense order, three
bytes of data are transferred to ti:e O-register for transfer
:: to the lOP. The first byte contains seven bils from the
selection unit of the track address from the T ;..register and
the track protect bit. The secor.d byte contains four bits
of the track address, and the four-bit sector address from
the S-register. The third byte contains the four-bit addn:ss
of the sector currently under the reGd/write head~ of the
selection unit. Equntions contrnlli ng eXE:;cutlon of the ordu
-.--..----r----------
Table 4-14.
Function Perfurmed
Phase
Sense order data is transl,1;tted one byte at a time regardless of the bytc width of the lOP interface. The fj rst byte
is stored in the a -register as request strobe signai RSD i!:
raised. The lOP delays, reads the datu from the O-register,
then delf"'!ys before raising request strobe acknowiedge signal RSAR. The second and third bytes are transferred
throu£)h the K-register to the 0 -register. Trarl,ifer from
the T -;-egi!:ter and S-regisler to the K-register an.:! from the
K-regi:;t~: to the a-register is controlled by signals generatcd within j'he controller as the order is executed. The
lOP a,.: ... ~pts data from the 0 -register whi ie signal P..~ D is true.
Sense Order, Phase S-:-q'Jence Chart
Signa Is Invo Ivnd ---------r----C-o-m-m-e-n-ts-------,I
For SIO sequence',
refer to table 4-10
Order out servict; cycle
follo'Ns accepted SIO or
command chainir:::; termina I order, aftei 'Nh kh:
a. (DATA, il~) in
state (1, 1)
b. (BKO, BK1) i:1
state (1 f ' )
DATAIN
DATA IN
BKZZ
BKO BK1
SENSE
ORD2 NORD3 NORD4
l
For order out service
cycle sequence, r-=:fer
to table 4-13
c. (ORDO-ORD4)
$tore (00100)
d. DeB in set :;tate
e.
.~
FSC in set slate
I
___f_•.__S_C__N
__i_n_s_e_t__st_a_te____
~
_____________________________________
(ConHnued)
4-106
~
__________________________
XDS 901565
Table 4-14. Sense Order, Phase Sequence Chart (Cont.)
Phose
Function Performed
lORD
=
FSC NIN +
DORD
=
FSC NDATA +
SjSEN
=
SENSE PXS
PXS
=
TSE NRWP
At end of pre:im:nary
operations, enter phase RS
R/pHFSl
=
...
Exit phase FSl
SjPHRS
=
FSCU PHRSET
Enter phase RS
=
PHfSl IN +
=
S;..t--lSE OXKEN BKZZ
=
DHTAiN NED PHRS
=
CYClEjC DCl5TART2
I'!RSAU +
DCLSTART2
=
PrlRS SEKSEND +
SF-KSEND
=
:,Ef.JSE NPHRSAOO
+ ...
PHRSAOO
=
f'HRSA ORDOUT
RjPHRS
=
...
SjPHRSA
= FSCU
(TRPR)--(OOO)
OXSENSEl
(TOO-T06) --(001-007)
OXKEt'-!
Start TCl delay line
DCl
Reset fl ip-flop PHRS
Set fl ip-flop
RSA
...
During pre liminary phases
(F5, FSZ, FSL) of data in
service cycle, SEN is set;
EP RAD controller address
and EP RAD storage unit
address are placed on function response Hnes (FRODFR7D), and (DORD, lORD)
signals indicate data in
service eye Ie request
PHRSET
RS
Comments
Signals Involved
P~RSA
...
PH RSASET
= ?HRSNED
PHRSNED
=
R!;
Enter phase RSA
t'HRS NED
RSD
= r:SC
Decrement byl-e counter
(BKO, BK1) io (l, 0)
NBKCK
=
NRSAR (PHRS
TC5000-2 + •••
=
...
Exit phase
PHRSASET
SEKSEND
TRPR is track protect
bit from se le·.:tion unit
...
Ra ise request strobe
signal RSD
Contents of O-register
read into memory while
R5D true
?riRSA SEKSEND
TC5000-3 + ...
SENSE NPHRSAOO
-{-
I
...
...
PHRSAOO
=
P!iRSA ORDOUT
BKZW
=
BKO NBKl
(Cant i nued)
4-107
XDS 901565
Tobie 4-14. Sense Order r Phase Sequence Chart (Cont.)
Phase
RSA
(Cont. )
I
Function Performed
(T07 -T1 O)--(KOO-K03)
Signals Involved
Comments
KXSENSEl
= SENSE BKZW
DCl
= .CYClE/C PHRSA RSAU
Prepare for transfer to
. O-register in phcse RS
(SOO-S03)-'-(K04-K07)
Start TCl delay line
+ •••
(
Reset flip-flop PHRSA
R/PHRSA
=
...
Exit phase RSA
Set flip-flop PHRS
S/PHRS
=
FSCU PHRSET
Enter phase RS
PHRSET
RS
(KOO-K07) --(000-007)
OXKEN
.,
RSD
Start TCl delay line
DCl
+
...
= OXKEN TCSOOO-2
OXK
Raise request strobe
signal RSD
= PHRSA
= DATAIN NED. PHRS
= FSC NRSAR
(PHR5 TCSOOO-2 +
SEKSEND
=
SEN~!=
+
PHRSAOO
...
. ..
NPHRSAOO
-
PHRSA. QRDOUT
...
Reset fl ip-f!op PHR5
R/PHRS
=
Set flip-flop PHI\SA
S/PHRSA
= FSCU PHRSASET
PHRS;,JED +
PHRSASET
=
PHRSNED
= PHRS NED
Exit phase RS
Start TCl delay line
Enter phase RSA
...
.-
RSA
Contents o(O-register
read into memorywhile
RSD true
-- CYCLE/C DClSTART2
NRSAU + •••
DClSTARi2 _. PHRS S!:KSEND +
I
... )
= CYClc/C PHRSA RSAU
DCl
+ •..
Decrement byte t.:our.ter
(BKO, BK1) to (C r i)
(ANOR-AN3R)--(K04-K07)
_.
PHRSA SEKSEND
TCSOC()-3
SEKSEND
=
SENSE NPHRSAOO
+ ..•
PHRSAOO
=
PHRSA ORDOUT
BKWZ
=
NBKO BKl
KXSENSE2
= SENSE BKWZ
NBKCK·
(Continued)
4-108
Prepare for transfer to
O-register in phase RS
XDS 901565
Table 4-14.
Phase
Sense Order, Phase Sequence Chart (Cont.)
Function Performed
RSA
(Cont. )
Signals Involved
R/PHRSA
= ...
Exit phase RSA
Set fI ip-flop PHRS
S/PHRS
=
FSCU PHRSET
Enter phose RS
=
PHRSA +
RSD
=
FSC NRSAR
(PHRS TCSOOO-2 + ... )
(KOO-K07)-- (000-007)
OXK
=
OXKEN TCSOOO-2
=
DATAIN NED PHRS
=
EDI FSC .
EDI
=
EDiSETl NPHRSA
+ fDI FSCU +
EDJSET 1
= SENSE
Raise end data signal ED
internally
EDD
Stort TCl delay line
I
Set fl ip-flop fJHIO
-
Termino I order operations
I
I
I
...
DCLSTART2
=
PI1P' SEKSEND +
SEKSEI'~D
=
PHRSAOO
Reset flip-flop PHRS
BKWZ +
CYClE/C DCLSTART2
NRSAU +
...
~E~-JSE
+
I
=
...
PL~~SA
R/pHRS
= ...
S/PHTO
=
I
I
4-97 Seek Order Sequen<..,:
The seek order is e:'.'ecuted if thE: seek order code (0 0011 )
is stored in the order register during an order out service'
cycle. During execution of a seek order, two bytes of data
are accep:ed on the lOP dat.:l lines and are stored in registers of the controller.
The first byte contains eight
bits of the track address, whkh are stored in the T -register
(three bits are not used). The second byte contains four
additional bits of the track address, which are stored in
the T -register, and the four-bit sector address, which is
stored in the S-register. Equations controlling execution
of the order are listed in tob!e A-15; a timing diagram is
provided in figure 4-26.
Seek order data is transmi tted one byte at 0 ti me, regardless of the byte width of the lOP interface. After the
Contents of C -register
read into memory while
RSD true
...
=
DCl
I
TO
...
Raise request strobe
signal RSD
.OXKEN
I
Comments
Reset fl ip-f1op PHRSA
PHRSET
RS
Paragraphs 4-97 to 4-98
...
NPHRSAOO
ORDOUT
PHRS ED
I
II
I
I
Ex it phase RS
__ ~ter
I
phas~O
See table 4-i 9
-'
cC':1troller raises the request strobe signal RSD, the lOP
de!a}s, places output data on the .:::lata I ines, then delays
aga;n before raising the request strobe acknowledge signal
RS/\R.The first byte is accepted into the I-re:Jister and is
tfClnsferred to the j-register before the second S}'te is reqU~$ted from the lOP. Transfer from the J-register toeither
the T -register or the S-register is controlled by :;ignals generated within the controller as the order is executed.
4-98 Write Order Sequence
If a write order .(X X001) is stored in the order rl..;gister during an order out service cycle, the sequence outlined in
table 4-16 follows. During execution of a write order, a
sequence of data out service cyc les is reguested by the controller. During each data out service cycle, data bytes are
accepted from the lOP, stored temporari Iy in registers of
4-109
XDS 901565
~0J-aRSD
,.,.J
0
I
I
0
I
n
RSAR
f "
I
0
L_
n
IL
CD
.--
Del
BKO
BKl
BKCK
L
---/
,
J
I
CD
U
: I
0)
PHRS
PH~SA
U
0
I
0
__I~-
L-.I~
I I
~
FHTO
---II
NOTES:
1. NO TIME SCALE; SEQUENCE OF EVENTS ONLY
2. PRELIMINARY OPERA nONS: ORDER OUT SERVICE CYCLE AND FHASES
FS, FSZ, FSL, OF DATA IN SERVICE CYCLE
3. (TRPR)-- (000)
_ }
T
(TOO- T06)---(001-007) FIRS. BYTE
4.
(T07- TlO)--(KOO- K03)} SECOND BYTE
(SOO- S03)--(K04- K07)
5.
(ANOR-AN3R) - - (K04 - KOn THIRD BYTE
6.
(KOO- K07)--(OOO-007)
7.
0- REGISTER READ WHILE RSD TRUE
901 565A. 412
Figure 4-25.
4-110
Data Transfer DlJring Sense Order, Timing Diagram
XDS 901565
Table 4-15.
Phase
Seek Order, Phase Sequence Chart
Function Performed
Comments
Signals Involved
For SIO sequence,
refer to table 4-10.
For order out service
cycle sequence, refer
to table 4-13
Order out service cycle
follows accepted S10 or
command chaining terminal order, after which:
a. (DATA, IN);n
state (1, 0)
DATAOUT
=
b. (SKO, BK 1) in
state (\, 1)
BKZZ
=
BKO BK1
SEEK
=
ORD3 ORD4
lORD
= r:;c
NIN +
DORD
=
NDATA + ...
DCl
= CYCLE/C DCLSTART3
DATA NIN
c. (ORDO-ORD4)
store (0 0011)
d.
DCB in set state
e. FSC in set state
f.
SCN in set state
g.
RSD true
During prelim:nmy p:1ases
(FS, FSZ, FSL) of data
out service cycle, EP RAD
co;,troller ad~ress and unit
address on fundion response
lines (FROD- FR7D) and
(DORD, lORD) signals indicate data uut service cyc Ie
Start dela}' lin~ at end of
function strc-b~
I'
I
I
I
I
II
I
Ii
;-
DClSTART3
I
,I
...
=
p; :r:SL NFSU +
...
Reset fl ip- fl0j' PHFSl
R/PHFSL
=
...
Exit phase F5l
Set flip-flop PHRSA
S/PHRSA
=
F)CU PHRSASET
Enter phase RSA
--
PHFSL NIN +
PHRSASET
R5A
:-~C
...
(DAOR-DA7K)·--(100-107)
I
= PHR5ADO TC5000-3
IXD-l
PHRSADO
Decrement byf€ counter
(BKO, BKl) to (1, 0)
...
Byte 1 (track No.
bits 0-6)
= t'HR5A DATAOUT
=
PHR5A SEKSEND TC5000-3
SEKSEND
=
SEEK NPHR5AOO +
PHRSAOO
=
PHRSA ORDOUT
NBKCK
BKZW
- BKO NBKl
...
BKZW signal enables
data transfer in phase RS
(Cont i nued)
4-111
XDS 901565
TobIe 4-15. Seek Order, Phase Sequence Chart (Cont.)
Phase
RSA
(Cont. )
Function Performed
Start TCl delay line
Signals Involved
= CYCLE/C PHRSA RSAU
DCL
+ •••
Reset flip-flop PHRSA
R/PHRSA
Set flip-flop PHRS
S/PHRS
Exit phase RSA
= FSCU PHRSET
PHRSET
RS
Comments
(IOO-I07)--- (JOO-J07)
=
Enter phase RS
PHRSA + ...
If one-byte interface:
= lOP PHRSDO TCSOOO-2
JXI1B
BYTl ID
PHRSDO
=
PHRS DATAOUT
If r.ct one-byte interface:
(JOl -JOJ}--(TOO-T06)
JXINl B
=
lOP D/\TAOUT TRS060
RWRIT::--2 hJBYil ID
TXJ
=
SEEK KV/RITEDO BKZW
TRS130
=
RWRITE-2 DATAOUT
RWRITEDO
Rais3 reql'est
signa! RSD
strob~
Raise end data sigr:!
ED htemally
RSD
- FSC Ni
KXO (KFI D
+ KFIDX1)
KFIDXl
SCD
Raise service call iine SCD
KFJ TRS270
=
lSl
= l"-Jf.SCR SCN INC
+
lSL
·..
=
DCl
Start TCl delay line when
ASCR and FSR trut;
=
CYCLE/C DCLSTARTl
+
DCLSTARTl
=
PHFS DeB BSYCU
+
BSYCU
=
BSYC
=
(Continued)
4-122
· ..
BSYC lOP
1-
...
ASCM ASCR AVIR FSR
+
I
...
...
-_.
Service call line ht:':ld
true untj I lOP responds
with ASCR and FSR
XDS 901565
Table 4-17.
~'gnals
Function Performed
Phase
FS
(Cont. )
Read Order, Phase Sequence Chart (Cont.)
Enable function response
signals FROD through FR7D
Set service connect flip-flop
FSC as FSR goe~ false if FSC
was previously reset by end
service signal
Set NPHFS
Set PHFSZ
Comments
Involved
(FROD-FR3D) encode
device controller
address
FROD
= BSYC SWAO + •••
FR1D
FR2D
=
=
FR3D
= BSYC SWA3 + ..•
FR4D
= BSYC GRD
FR5D
= BSYC UO + ...
FR6D
=
BSYC U1 + .•.
FR7D
=
BSYC U2 + .••
S!FSC
=
ASCB
=
ASCM ASCR AVIR FSR
(delayed NFSC)
ASCB
BSYC SWA1 +
BSYC SWA2 +
FR4D always false
+ ...
(FR5D-FR7D) ~ncode
device address
FSC must be s:::~; before
RSD can be mLed
C/FSC
= NFSC FSR + ...
S/NPHFS
=
PHFS
C/NPHFS
=
TC3100-3
S/pHFSZ
= PHF~
End phase FS
Enter phase t- ~Z
= TCS100-3
b--------r--------------------+------------------------------------r----------------------C/PHFSZ
FSZ
FSl
I
=
Start TCl delay line
DCl
Reset PHFSZ
R/PHFSZ
Set PHFSl
S/PHFSl
= PHFSZ
C/PHFSl
= TCS 100-3
DORD
=
FSC NDATA + ..•
lORD
=
FSC NIN + ..•
DCl
=
CYClE/C DClSTART3
+ ...
DClSTART3
=
PHFSl NFSU + .••
FSU
= FSR lOP
Enable data or ::>rder signals
to request data in service
cycle
Start TCl delay line
CYCLE/C PHFSZ
-t
•••
Phase r-SZ fL'ndi')Os
not significant for
read order
End phase FSZ
(DORD, IORC) are
(0, 0)
Tel delay line started
'when FSR goes false
+ ..•
(Continued)
4-123
XDS 901565
Table 4-17.
Phase
FSL
(Cont. )
Read Order, Phase Sequence Chart (Cont.)
Signals Involved
Function Performed
If enough data bytes are
avai lable for transfer to
lOP, hold SCN in set
state; if additional data
bytes are requ i red for
data in service cycle,
reset SCN
Comments
=
SCNEN
SCNEN
=
DAT.A. SCN EXT SCSET
SCSET
= READ NRKI + ...
S/SCN
=
R/SCN
SCNRST
C/SCN
Reset PHFSl
R/PHFSl
Set PHRS
S/PHRS
SCNRST
= PHFSl
=
If SCN not in set state
upon return to phase FS,
service calls inhibited
unti I SCR is reset
+
TC5100-3
End phase FSl
=
Enter phase RS
PHRSET F5CU
PHRSET
= PHFSL
F5CU
=
FSC lOr' +
C/PHRS
=
TCS100-;J
DCl
=
CYClE/C DClS.ART2
NRSAU -1 •••
DCLSTART2
=
PHRS READ KFID
+ ..•
RSAU
=
RSAR ICP + •••
I~!
+ ...
I
I
~-~---+--------------------~-------------------------------------+I--------------------RS
Start TCLdelay line when
RSAR faise
Raise request strobe
signal RSD
+ PHRS ;CSOOO-2
+ ..• )
i
Transfer data from add .. essed
location in FAM modlJle to
K-register
(ROO-R07)~(KOO-K07)
KXR
KXREN
=
KXREN RP.=AD-2
=
BKZZ + ...
=
OXKEN TCSOOO-2
=
PHRS DATAIN NED
T~S180
Transfer data from K-register
to O-register
(KOO-K07)--(OOO-007)
OXK
OXKEN
I
I
I
I
TCl delay line starter:!
when RSAU false, bc~'
cause KFID at true level
I
= FSC NRSAR (FSCU RSD
RSD
II
Signed RSD first rais'::'0
in phe-se rSl, but n,'J .. t
be raised each time
phase RS is entered
Transfer of data from
addressed location i:1
FAM module to K-:register takes place
under control of FA ,v,
circuits. This transfer
must occur before e/{it
from phase FSl to phasE'
RS, and before Tel
delay line is storied i-1
phase RS (KFID true)
r....-_ _ _---'-_ _ _ _ _ _ _ _ _ _ _ _- . l_ _ _ _ _ _ _ _ ._ _ _ _ _ _ _ _ _ _ _ _ _ _ _-LI_ _ _ _ _ _ _ _ _ _ _-'
(Continued)
4-124
XDS 901565
Tobie 4-17.
Comments
Signals Involved
Function Performed
Phose
RS
(Cant. )
Read Order, Phose Sequence Char't ((Cant.)
= BKXl
, M/BKO
Mark byte COljnter
BKX'j
=
NBKX1EN
, NBKXl EN = KXOEN READ +
I
C Ic,:::k byte cOunter
For multiple-byte lOP
interface, additional
bytes are taken from
the FAM module to the
I-register for transfer
to a-register. Dato
transfer is controlled
by the byte counter
If multiple-byte lOP interface
Transfer data from addressed
location in FAM module to
I-register, clock byte counter.
Raise end dato signal if sufficient databyte5 are not stored
in FAM module, preset KFI
when K-register and I-register
filled with data for a-register
KXOEN
= OXKEN TCS100-3
M/BKl
= BKXl
NBKCK
= BKCKEN TRS27ID
-+-
BKCKEN
...
...
= NBYTi ID
(READ··' READRR
+ BKCKEN NU5030
+
)
...
If
Byte counter direct set
to (1, 1) dur:ng order
out service cycle, but
must be preset each
time dato is trcnsferred
from K-register ond 1register to O-register
For multiple-byte lOP
interface, bytE: counter
is incremente0 as the
byte is transferred
from the FAM module
to the K-register or
I-register
two-by~e lOP inte.r_f~~:
First data byte transferred
as for one-bvte lOP interface
I
(ROO-R07)--(KOO-K07)
Decrement ~)yte counter,
causing sigtjol BKZW to
be true
=
KXREN RREAD-2 TRS 180
KXRE~!
=-
R~ADRR
READRR
=
READ RREAD-2
BKZW
=
BKO NBKl
IXR-l
=
IXEN READRR B't08-0 15)
OXK
= OXK~N TCSOOO-2
(116-123 )---(01'6-023)
OXK
=
(124-131 )----(024-031)
OXK
= OXKEt-J
Mark byte cour.ter
KXOEN
.-
End data signal raised and
latched internally to control phase sequence
EDJ
= EDrSET2 NPHRSA
OXKEN TCSOOO-2
TCSOOO-2
OXKfN TCS1OO-3
+ EDI FSCU + ...
OXKEN KA8
EDISET2
::::
KA8
= SCR REMPTY KFIDXl
REMPTY
=
+ SCR KA8 KFID
RKO RKl RK2 RK3 RK4
KFID enables TCl delay
line to start ;n phase RS
(next RSAR sIgna I)
Transfer of d·... tc from
K-register c.ld I-register
to O-registe;- takes place
at start of phase RS.
Transfer of data from FAM
module to K~'register and
I-register is ir.dependent
of phase control timing,
but data must Se avai 1able before tr'::rlsfer to
phase RS is allowed
Prepare for next phase RS
Signal KA8 rai:.ed and
latched if FAM module
empty when KF fDX 1
true. If so, EDiSET2
raised and latched
(Continued)
4-127
XDS 901565
Table 4-17.
Phase
RS
(Cont. )
Read Order, Phase Sequence Chart (Cont.)
Function Performed
Signals Involv.ed
Comments
Reset PHRS
R/PHRS
=
...
End phase RS
If end data, set PHTO
S/PHTO
=
PHRS ED
Enter phase TO
C/PHTO
= TCS100-3
S/PHRSA
=
PHRSASET FSCU
PHRSASET
=
PHRSNED
PHRSNED
= PHRS NED
l
If not end data, set
Enter phase RSA
PHRSA
RSA
Start Tel delay line
when lOP raises RSAR
C/PHRSA
=
TCS100-3
DCl
=
CYClE/C PHRSA RSAU
+ •••
RSAU
I,
= RSAR lOP +
R/PHRSA
=
Set PHRS
S/pHRS
= PHRSET FSCU
= PHRSA
o -register data accepted by lOP
...
...
Reset PHRSA
PHRSET
I
End phase RSA
-t-
Enter phase RS
•••
-.-TO
Start TCL delay linE:
when RSAR true
DCL
= CYCU:/C DCLSTARTl
+
...
I
DClSTARTl = PHTO R'JAlI +
If lOP transmits count done
...
=
DAl R TurD
=
lOP NL, ED PHTO
C/CDN
=
NTCSOOO
S/DATA
_. DATA:;!:T NORDIN
S/CDN
terminal order, set CDN
TORD
If CON, place (D,\TA, IN)
flip-flops to (0, 1) state to
requesj· an order in service
cycle durif\g next phase FS
NDATASET = CND +
=
NDATA IN
R/DATA
=
...
C/DATA
=
PHFSTO:> TCS100-3
=
PHTO +
=
INSET "·JORDIN
=
NDATASET + ..•
=
PHFSTOD TCS 100-3
ORDIN
PHFSTOD
S/IN
f
INSET
C/IN
(Continued)
4-1?8
...
...
I
I
I,
Refer to table 4-1 Y
for terminal order
operations other th..lr.
count done
If lOP does not transmit
terminal order, da;a in
service cycles continue
following return to phose
FS
XDS 901565
Table 4-17. Read Order, Phase Sequence Chart (Cont.)
Phose
Signals Involved
Function Performed
TO
(Cont. )
Comments
Whether or not terminal order
received from lOP:
Reset PHTO
R/pHTO
=
...
End phose TO
Reset NPHFS
R/NPHFS
=
PHFSET
Enter phase FS
=
PHTO +
PHFSET
...
Table 4-18. Order In Service Cycle, Phase Sequence Chart
Phase
Function Performed
FS
If phase FS fo! lows count
done terminal crder or lOP
unusual end, (DATA, IN)
flip-flops are F-klced in
state (0, 1) dL·r~ng previous
phase TO:
I
Raise service
,~ai
I line SCD
------~---------------------
Comments
Signals Involved
Service call line he Id
true until lOP responds
with ASCR and FSR
I
=
=
SeD
lSl
lS!..
t'IASCR SCN I1'-1C
+
...
PHFS DCB CYCLE Ie
N(NSCNMEN)
NDATA
NRWE NWCHW
N(NSCNt'.AEN) ==
=
M/SCN
I Start TCl deiuy line when
+ ..•
== CYClEjC DClSTA RTl
+
DCl
...
ASCR and FSR hue
DCLSTARTl
== PHFS DCB BSYCU
-{
Enable func!ion response
signals FROD through FR7D
If DATA is not 1n reset
state, previouslyexisting conditions hold
N(NSCNMEI'!) .::t true
level
...
...
BSYCU
== BSYC lOP +
BSYC
=
ASCM ASCR AVIR FSR
+
FROD
=
BSYC SWAO +
FR1D
=
BSYC SWAl +
FR2D
=
B~YC
SWA2. +
...
...
FR3D
=
B::'YC SWA3 +
...
FR4D
=
BS~C
FR5D
== BSYC· UO +
FR6D
= BSYC Ul
FR7D
== BSYC U2 +
!
...
...
...
...
GRD +
+
...
(FROD--FR3D) encode
device contro'lpf
address
FR4D always faise
(FR5D-FR7Dj ,:mcode
device address
...
---------------------~
(Continued)
4-129
XDS 901565
Table 4-18. Order In Service eyc Ie, Phase Sequence Chart (Cont.)
Function Performed
Phase
If phase FS follows
detection of controller
error, place (DATA, IN)
flip-flops to (0, 1)
FS
(Cont. )
=
DATASET NORDIN
DATASET
=
NeDN NCDNPET
NUNE NSKSBK
ORDIN
=
NDATA IN
=
PHFSTOD TCS 100-3
S/DATA
C/DATA
PHFSTOD
I
(DATA, IN) flip-flops
must be in state (0, 1)
to request order in service cycle
= PHFS DATA
R/DATA
= ...
S/IN
-- INSEl NORDIN
...
=
NDAiASET +
C/IN
=
PHFS10D TCS 100-3
S/NPHFS
=
PHFS
C/NPHFS
=
TCS 100-3
S/PHFSZ
=
PHFS
C/PHFSZ
=
TCS10v-3
DCl
=
CYCI~/t
I Reset PHFSZ
R/PHFSZ
= ...
End p!lose FSZ
Set PHFS l
S/PHFSL
=
Enter phase FSl
C/PHFSl
-- TCS1 GO-:;
INSET
Set NPHFS
Set PHFSZ
FSZ
Comments
Signa is Involved
Siart TCl delay line
End phase FS
Enter phase FSZ
PHFSZ +
...
PHFS?
--
FSl
Start TC l de lay lint
Reset service call
SCN
f!j~-flop
=
CYClE/C DClS TART3
+ ..•
DClSTART3
=
PHFSL NFSU
FSU
-
FSR -lOP + ...
DCl
- SCNI,ST
R/SCN
SCNRST
Reset PHFSL
-- PHFSl +
C/SCN
=
TCS100-3
R/PHFSl
=
...
(Continued)
4-130
-t
TCl delay line sr..:rted
when FSR goes false
...
SCN reset to prevent
additional service calls
...
End phase FSl
XDS 901565
Tobie 4-18. Order In Service Cycle, Phase Sequence Chart (Cont.)
Phase
FSl
(Cont. )
RS
Function Performed
Set PHRS
=
FSCU PHRSET
PHRSET
=
PHFSL IN + .••
FSCU
=
FSC lOP +
=
CYCLE/C DCLSTART3
+
S/PHRS
Start TCL delay line
Comments
Signals Involved
DCL
Enter phase RS
...
.0.
DCLSTART3
=
PHRS NDATA NRSAU
+
0"
=
RSAR lOP +
RSD
=
FSC NRSAR (FSCU RSD
+ PHRS TCSOOO-2 + ... )
RSD remains high until
request strobe acknowledge signal received
from lOP
000
=
OXORDIN TER +
OXORDIN
=
PH~SNED
Contents of O-register
on lOP data jines contains
(XXOl XOOO), depending on state of flip-flops
PHRSI"-lED
=
PHRS NED
001
=
OY-ORDIN INl +
003
=
QXORDIN +
004
=
OXORDIN UNE +
Reset PHRS
RjPHRS
=
Set PHRSA
SjPHRSA
=
PHRSASET FSCU
=
?HRSNED +
C/PHRSA
=
TeS100-3
DCl
=
CYClEjC PHRSA RSAU
+ ..
RSAU
Raise request
RSD
~trobe
line
Load data into O-register
(TER, INl; 1, UNE)--(OOO,
001, 003, 004)
PHRSASET
RSA
Start TCl delay line when
request strobe rlcknowledge
signal received from lOP
••
o ••
0
•
ORDIN
o ••
000
...
End phase RS
"!'
=
~SAR
Enter phase f\SA
...
0
RSAU
•
lOP accepts ciuia ill
O-renister
lOP + ...
Reset PHRSA
RjPHRSA
-
...
End phase RSA
Set PHRS
S/PHRS
=
PHRSET FSCU
Enter phase RS
=
PHRSA +
PHRSET
C/PHRS
00'
= TCS100-3
(Continued)
4-131
XDS 901565
Table 4-18. Order In Service Cyc Ie, Phase Sequence Chart (Cont. )
Phase
Function Performed
RS
Start TCl delay line when
request strobe acknowledge
signal RSAR goes false
DCl
DClSTART3
Raise request strobe line
RSD
Comments'
Signals Involved
RSD
=
CYClE/C DClSTART3
+ •.•
=
PHRS NDATA NRSAU
+ ·
=
FSC NRSAR (FSCU RSD
+ PHRS TC5000-3
..
+
RSD remains high llr.til
RSAR received from iOP
· .. )
Reset PHR5
R/PHRS
=
...
End phase R5
Set PHrO
S/PHTO
=
PHRS ED
Enter phase TO
EDSET 1CSOOO-2
End data signal set
internally and latched
ED
=
+ ED FSCU + .•.•
EDI
~
EDISET1
C/PHTO
=
EDI FSCU
+ EDISETl NPHRSA
+ ..•
=
NDATA +
=
TCS100-3
...
I
-----
TO
Start Tel delay
RSAR tru~
Iir:~
when
=
CYCLE/C DClSTARTl
+
=
PHTO RSAU + ..•
R/FSC
=
ESR FSC
C/FSC
=
FSC RSD 4- •••
R/DCB
=
DCBRST
DeBRST
=
DCBRSTl + •••
DCBRSTl
=
PHTO ORDIN DCBRSTEN
DCBRSTfN
=
N(CCH NES NUNE)
eCI-!
=
lOP DA2R NDA3R
DCl
DClSTARTl
If end service, reset
f~C
If end service, reset DCB.
·..
If not end service, not
unusua I end, and <.;ommand
chaining is ordered by lOP,
inhibit reset of DCB
C/DCB
= t'HCS080
Reset PHTO
R/PHTO
=
...
End phase TO
Reset NPHFS
R/NPHFS
=
PHFSET
Enter phase FS
PHFS-ET
C/NPHFS
4-132
= PHTO ;-
...
= TCSiOO-3
XDS 901565
4-102 Terminal Order Operations
Every service cycle ends with a terminal order phase during
which a terminal order may be received from the lOP, as
indicated in table 4-19. If no terminal order is received
and no errors have occurred during data processing, the order
in process continues. The count done terminal order that
ends every errorless input/output operation is followed by
Table 4-19.
Phase
TO
an order in service cyc Ie. Interrupt terminal orders and
unusual end terminal orders are commanded by the lOP and
may cause the data processing to stop. A command chaining terminol order can occur only during an order in service
cycle and causes on order O!Jt service cyc Ie to follow the
order in service cycle. Controller errors are acted upon
during the teiminal order phase, regardless of when they
occur.
Terminal Order Operatior.s: Phase Sequence Chart
Function Performed
Start TCl delay line
Paragraph 4-102
Signals Involved
=
DCl
Comments
CYClE/C DClSTARTl
+ CYClE/C DCLSTART2
+
...
DClSTARTl =- ?MTO RSAU + .••
DClSTART2 = FHTO ES +
...
lOP Signals
If count
done"~
set CDN
=- DA1R TORD
S/CDN
TORD
C/CDN
If interrupt,
~ct
ell
If unusual l':nci, set UNE
If UNE or CDN set, reset
DATA and set IN to request
order in servke cyc Ie ~ pon
return to phusc FS
=
lOP NES ED PHTO
=
hlfCSOOO
Reset by AlO command.
New SIO CC:1r.ot be acr:epted untii CIt is reset.
The order i j\ process goes
to completion
S/CIL
CjCIl
=
S/UNE
= DA3R TORD
ClUNE
=
S/DATA
-- DATASET NORDIN
!':TeSaOa
=
NCDN NCDNPET NUNE
NSKSBK
ORDIN
=
N9ATA IN
=
PHFSTOD TCS100-3
=
PrlTO + •••
CjDATA
PHFSTOD
S/IN
Reset b), new 510
NTCSOOO
DATASET
= INSET NORDIN
INSET
C/IN
!rldicates al: data h.:.Js
been transfer:-ed for
read, write, or checkwrite operati()~. Reset
d:.Jring next or.:J~H out
service cycle
=
NDATASET + •.•
=
PHFSTOD TeS 100-3
(Continued)
4·-133
XDS 901565
Paragraphs 4-103 to 4-107
Table 4-19.
Phose
TO
(Cont. )
Terminal Order Operations l Phose Sequence Chart (Cont.)
Function Performed
Reset PHTO
Reset NPHFS
Signals Involved
Comments
R/PHTO
=
...
C/PHTO
=
TC5100-3
R/NPHFS
=
PHFSET
=
PHTO +
=
TC5100-3
PHFSET
C/NPHFS
4-103 EP RAD SELECTION UNIT
The EP RAD selection unit either accepts data signals and
control signals from the EP RAD controller and writes Man~ster-encoded data on the magnetic surfaces of the disc
. . . or reads Manchester-encoced data from the disc fi Ie
ana transmits data signals and con~rol signals to the EP RAD
controller. A maximum of eight ~p RAD selection units
may interface with one EP RAD controller. Each EP RAD
s.e1ection unit interfaces with one disc file •
End phase TO
Enter phose FS
...
selection unit is addressed, the track register is loaded with
on 11-bit track address during each intersector gap time.
Signal SCl R is true 11 l"imes, and the track address bits are
accepted from the controller through signa' TRKR. (The
two most significant bits shou Id always be zeros. )
S/TRO
TRKR USLA
S/iRl
TRO
S/fRl0
TR9
(C/TRo-C/TR10)
SCl R
.
All EP RAD selection units of
or. [P RAD fi Ie are connected
to the associated EP RAD control IN by a common cable assembly, as indicated in figure 3-1. Interface signals common to the EP RAD controller and to all EP RAD se lection
units of 01"' EP RAD fi Ie are Iisted in table 4-20. Signals
gcneluted by an EP RAD selecth!1 unit or received by an
EP RAD selection unit arc valid o'1ly if the EP RAD selection unit if, addressed by the EP RA~ controller.
4-104 ADDRESS CIRCUITS (SeE' figure 6-5)
Signals IDOR, ID1 R, and 102 R, wh ic.h are transmitted from
the U-register of the controller, p:-ovide inputs to all selection units. For one selection unit, the address encoded
he signal levels matches the cddress encoded by switch
•
.• ngs of the LT26 Switch Compcrator modu Ie, causi ng
signal SEL for the addressed seleciiGn unit to be true. If
no power fa: lure has occurred (NPDL Y true), signa I DVT
is true, generating a true device test signal DVTD. In
response to an accepted SIO cornmand, the controller generates a true SLNR signal. As signal SLNR goes false t flipflop USLA of the addressed seledioll unit (SEL true) is set.
Once signal USLA is true, signu Is IJSLB, TYPO, TYP1, and
DVOD are true, and interface s:,:mals for the addressed selection unit are va lid.
4-105 TRACK REGISTER (See figure 6-6)
The trock register t which consists of flip-flops TRO through
TR10, is cleared by a true PDLY s:gnal.
(E/TRO-E/fR10) = PDL Y
The track register is a serial register c locked by signal
s.c.1R, which is generated by the controller. While the
4-134
Outputs of the track register address one cf the 512 ~ead/
write heeds and permit reading from or writing into tf,<:;
track o"!:>ocioted with the addressed read/write head. Signals from TR2 through TR5 are used in the memory piOtect
circuits.
4-106 MEMORY PROTECT CIRCUITS (See figure 6-8)
The men.olY proted circuits accept output signals fr(":;l the
four mo~t significant bits of the track register (TR2, ;-P3,
TR4, and TRS) and generate 16 output signals, as surMr.::ri zed
in table 4-21. For any possible combination of the fOur inputs, one of signals NGTOl through NGT16 is false. Iflhe
switch as.:;ociated with the signal is dosed, signal T~f' is
driven folse. If the selection unit is acJJressed, signai USLA
is true and a true TRPD signal is generated t:, indicate that
the addressed track is write-protected. If on order ,:,.iher
than Wril"3 is bei ng executed, signa I TRPD does not affec t
operation of the control ier. Tracks must be protected in
groups of 22, as indicated in table 4-21 since the four most
significant bits of any address cause all tracks in that lange
to be protected.
4-107 ANGLE REGISTER (See figure 6-9)
The angle register, which consists of flip-flops ANa through
AN3, is cleared to 0000 by index pu Ise IP.
(E/AND-E/AN3)
= IP
XDS 901565
Table 4-20. EP RAD Selection Unit Interface Signals
Function
Signal
/ ANO/-/AN3/
Sector address (angle) data to controller. A four-bit code which indicates the
address of the sector currentiy under the reocl/write heads
/DAV
Data signal to controller. Developed from Manchester-encoded data written on
disc file
/DAT/
Data output to storage unit from D07 of comoller
/DS/
Data ~trobe to controller. Deve-Ioped from Manchester-encoded data. Provides
the clock signal associated with /DAV
/DVT/
Device test signal to controller
/DVO/
Device operational signal to controller
/100/-/102/
Device address signals from controller. The selection unit controls signul !evels
on t~e common cable assembly onll' if the d;vice address signals match the address
set in the module
/IP/
Index pulse to controller.
/NMNRST/
Manual reset signal flom controller.
/PWRMON/
Signal to controller.
/SAI/
Sector amplified enabft:: siqtlai from controUer. True after track addre~s !-:'Js been
shifted from cor'troller to addmssed selection unit during intersector gap time
/SC1/
Tra..;:~ and sector shift clock. True 11 times during intersector gap time to permit
output of TRKR to be stored in track register
/SC2/
Data clock from controller. Tru~ during execution of write order to enable
Manchester-encoded data to he stored on disc
/SlN/
Select now signal from controller. True when an SIO command is accept':
t
TRACK
rCODE
9 I .
SIGNALS / I ~
R53
I
USLB
3
AOK
4
C MC3
NTR2
7
12A
WENR
8
~------------~S
111
MC3
FF
01-014
v
NSC:2~.
TRACK
CODE"
SIGNALS 9;
26 WRTAMPl
NWRTAMPI
WENR
8 MC6
I
.~
r-------I~·
-
".
-
READ;WRITE COUPLERS
IN LOCA nONS
17B, 18B, 19B
,
'?/ I
24
- -- - - - - --
,'",
READ/vvRlTE COUPLERS
IN LpCA nONS
138, 14B, 15B
I
~
I
--l
32 PAIRS OF
SIGNALS TO
124
READ/WRITE
HEADS
-:1:--+/-4.~
~
L ____ ~d ).-'\'~:J
18
- ,----.
I
I
(TRACKS 0-255)
E
I,"
-
L _____ -V~1'-{c)S
10
7
. K:; JC:':-'lQ S
3
KDX :::-',:: G
='
4
:~~~.; ~:~~:
J
rzJl:::~ ',,::G 24
Ql-Q9
---- -
- -
-
i
I23 ICLOCK~EG
~.
-
9
l~
~U
t--
I
I
Q5r - - Qy 012,f---
L ___~
I
I
021
I--
27
:c: L KU r~ D LY
23
013.014
--
I
018021
I
I
I
I
I
015-017
Al
I
NOALD- 25
13A
SA
,,-- ~
r-- 01,021
03
014
04- Q13
r---
':':"!...
3
r--
DSD .--.-'--
80
5A
---.,
3P2
, 91
-
3 ~-----t- >---/OS/
II
i
..
'
..
Q 17, Q 18, 01 9
.
TO DEVICE
.
COt~TROLL[
20 f---+- us L B fLH'..JIT St LE C1 ED i ~,l rUT)
. - 30
74
DAID
12
015,016,Al
r---
.l-l..
R
SP2
~ ,~' >--/DAI/
71) ~t'-JDAID
3)
'-- ~
I.
014
DATA DECODER LT77
"1'
I
t - 01 - 01 3 1 - - - - - - y - - - I
Q20
21
___
~t----
I
12
------~
1-
..-
t-----'----i
~ ___~______~~~:===~-~~~_ _ _L______-~-.~_~ ~-:-._- _=~- =-~ ~ =~ .~L =l~I-,iI,_tv~':':"~. :c. ;I T':"':'T~;~. : :.-~:~:~ ~ ~ ~ =~ ~=~ ~- .J~ ~ ~D~A~I-O_~:;:
-)~
---
-
12
41
Ql-Q4
39 RDAfv',PPOS 39
'--I'""-'"
"----;
CLOCf.;POS
Ql-Ql0
H
RDXJ:~-':~G 27
5
t---
r--
017-
r--------
35 RDMv',PNEG 35
~~~~:::~ ~ nV-~-----'~
-
015,
016
---- 4
RDXS1
PULSE PAC Kl NG COMP[t-J',/I TOR LT85
......
~
i--
'--- f-'
Figure 4-31.
L_
---_._-_._--_ _--_
.•.
..
I\l'ud Channel, Schematic Diagram
_--------- --- ------------------
~-----
_.
---._-----_ .._-------------
4 - 143/4 - 144
XOS 901565
ROX
UMlTPOS
ClOCKOlY
(DATA)
(1 )
(1)
(1 )
(0)
(1 )
(1)
(0)
(1)
901565A.431
Figure 4-32.
Read Signals, Timing Diagram
under the icad/write heads of the EP RAD storage unit.
The seek aider provides a track number and sector number
at which execution of the following order is to begin. (A
program using this seque:1<.;e assures minimum delay while
waiting for an addressed st.!t:tor because the avai lable sector
is addressed in constructins the seek order.) The write order
Table 4-22.
follows the order which stored the addressed location. The
table provides references to paragraphs, pho"= ::;equence
chorts, and illustrations which provide detoilsofthe ope~a
~;ons outlined. figure 4-36 shows maior elements of the
EP RAD controller and can be used with other referp.nce
ma~erial to review operation.
Typical Operations of the EP RAD file
-------------------------------------Referer.ces
The lOP address an ~!O command to th<=> EP RAD
control !er and one '"'~ cigH (maximum) EP RAD
storage units. The 5TO command is accepted if:
I
Function strobe arid function indicators (p<1r. 4-10
and table 4-:-1)
'1
SIO function indicator (par. 4-17)
a.
The EP RAD controller has priority
b.
T"'e EP RAD controller and EP RAO
storage unit are ready
Ph'lse sequence chart (table 4-10)
No interrupt ;:; pending
F low diagram (fig. 4-8)
Phase control circuits (par. 4-22)
c.
Phase sequence chart (table 4-1:";)
Ouri ng the order out se:-vi ce cyc Ie, the sense
order code is stored h the order register
Order register (par. 4-31)
Order signals (table 4-2)
F low diagram (fig. 4-8)
Phase control circuits (par. 4-24)
Data path (fig. 3-5)
During th(~ following three dato in service cycles,
data is transferred to the lOP
Timing diagram (fig. 4-25)
____________________________ .__________________________- k____________________________________________________~
(Continued)
4-145
XDS 901565
Table 4-22. Typical Operations of the EP RAD Fi Ie (Cont.)
r------------------------------------------------r-------------------------------------------~-----.----.-
References
Operation
a.
Phose sequence chart (table 4-14)
Write protect bit from se lection unit and
five track address bits from T-register
Flow diagram (fig. 4-8)
b. Four track address bits from T-register and
four sector address bi ts from S-reg ister
Byte cO'Jnter (par. 4-33)
c. Four current sector bits from selection unit
O-raghter (par. 4-38)
K-register (par. 4-57)
T -register (par. 4-68)
S-register (par. 4-67)
Address circuits (por. 4-104)
Memory protect circuits (par. 4-106)
During the order in service cycle, command chaining
permits the order out service cyc Ie to follow
Phase circuits (par. 4-29)
Phase sequence chart (table 4-18)
Flow diC'gram (fig. 4-8)
Phasc sequence chart (table 4-13)
During the order out service eyc Ie, the seek order
cede is stored h the order rc~:ster
Ord,,=,r register (par. 4-31)
Order signals (table 4-2)
Phase (.ontroi circuits (par. 4-24)
Flow diagram (fig. 4-8)
Dato ;-'I1th (fig. 3-4)
During the following two data out service cycles,
data is transferred from the lOP
Timl'18 diagram (fig. 4-26)
a.
Five bits of track address
Phase con+rol circuits (par. 4-26)
b. Four bits of track
sector address
a~rJress
and four-bit
Flow (jiagram (fig. 4-8)
Phase sequence chart (table 4-15)
Byte counter (par. 4-33)
I-register (par. 4-37)
J -register (par. 4-39)
T -register (par. 4-68)
S-register (par. 4-67)
(Continued)
4-146
XDS 901565
Table 4-22. Typical Operations of the EP RAD File (Cont.)
Operation
During the order in service cycle, command chaining
permits the order out service cycle to follow
References
Phase circui ts (par. 4-29)
Phase seqlJence chart (table 4-18)
Flow diagram (fig. 4-8)
During the order out service cycle, the write order
code is stored in the order register
Phase sequence chart (table 4-13)
Order register (par. 4-31)
Order signals (table 4-2)
Pnase controi circu its (par. 4--24)
Flow diagram (fig. 4-8)
During execution of a write order, the number of
data out service cycles depends upon the number of
data bytes to be transmitted and the byte width of .
the lOP interface. After all data bytes have been
transferred, the lOP transmits a count done terminal
order
Jato path (fig. 3-6)
Phase control circuits (par. 4-27)
Flow diagram (fig. 4-8)
Phase sequence chart (table 4-16)
I-register (par. 4-37)
.J F-register (par. 4-43)
j
-register (par. 4-39)
f ...i.M cirt;uits (par. 4-46)
L·-register (par. 4-45)
~,P -register
r -register
(par. 4-44)
(par. 4-57)
i)-register (par_ 4-58)
~ -register
(par. 4-66)
Preamble (par. 4-61)
Checksum (par. 4-71)
Address increment (par. 4-70)
Terminal order (table 4-19)
During the order in service cycle, the EP RAD
controller disconnects from the lOP
Phase circuits (par. 4-29)
Phase sequence chart (table 4-18)
Terminal order (table 4-19)
Flow diagram (fig. 4-8)
4-147
XDS 901565
XN
-
YMN YLN -
A
(ALL)
YMN -
s)-
XN
YLN -
N MODn
>-
-
XN
YMN
YLN - .
-
-
XN
YMN
YLN XN YMN YLN
XN
YMN
YLN
XN
YMN
YLN
NSPEL~
~NSPEL
;
C
/7
I
___ (8,0, F, H)
NSPO
0
t---+----t~
N SPO
(C,D,G,H)
NSPl
E
-
-----... NSPl
(E, F, G, H)
=rJ-
=)-NSP2
I---t----ili!l>-
j G)
N SP2
-
~
MODULE
SIGNAL
XN
= N X 64
YMN=NX8
YLN = N X 1
NMODl
NMOD2
NMOD3
NMOD4
NMOD5
NMOD6
NMOD7
NMOD8
Figure 4-34.
-NXSP2 NXSP3 NXSP4
0
G
0
0
1
1
1
1
0
0
1
1
0
0
1
1
INPUT
GATE
0
A
1
8
C
I
0
1
0
1
f'.ISPO
D
E
F
1
0
1
0
1
.0
0
G
1
1
H
0
NSPl , NSP2
i
1
1
0
0
I
I
1
1
1
1
1
1
0
0
0
C
0
0
i
LTl 05 Spares Selector Module, Simplified Logic Diagram
4-149
xes 901565
YSP3
(Y-VAlUE
OF SPARE
READ;\iI.lRITE
HEAD)
RTla
MODULE
268
NSPSEl- 31
--,
'\
'i~NTR5BG
NTR5~
17A
SPSEl
NSPSEl I : ) - 3 4
17A 38
TR5AG
TR5 35
~
NXSP2
NSPSEl
~I)
TR2
NSPSELB
19A
47
39
.. TRM1X2
NXSP"B39
r. TRM1X3
NTR2G
NTR3G
34
X-VALUE
or TRACK
ADDRESS
TR3 44
NXSP4
NSPSEl
26
40
NTR4G
~
TRMIX4
TR4
901565A.434
Figure 4-35.
4-150
Logical Sparing Circuits for Track 221 (Octal 335), Simplified Logic Diagram
X DS 901565
~--------------------------------------------------------------------------------------------------------I
M 1,.,1'
/r/----~·LI_E_0_X_2~
".
!----~
____/_D_A~O-L___ ,
ORDPI-ORDP4/
=: :::--"1:/,n(~-tr-c-7-/----1-'l_lDOF'
---/
EDX4
f--------1L._B_Y_T_21_0_0~
\),R-I
I
'---~
IX0-2
1"0-2
1)(~-2
1><0-3
IX0-3
IXR-3
~
B
f - - - -1L_B_f_T_41_0_0.....
!-FR)0-FR70-
/
f--
lOP
_~_SE_-,--_C_H_'N_R_L-_v\_R_I_T[_-,--_R_E_I'_O_1
SE_E_K_-L_S_E
LI_ _
f-s ::
f--
Li L
SLN
I---
~
SCI
f---.
-~NC~l D~I--l ,_ DC~ ~
OS
~-----TS[
---1L_C_I_L_~
-1~_S_C'_'
SI0P0S)-1L-_S_L_N_0~~
100-107
I \0- I
---11,-_F_S_'J_~
,~ FSL~ --1,-_P_h_FS_L~
--I
B,,2L
=
IXI- i,
6~,Z\'
~~
Tx), IXI-2, I,\R-I, >-XS[NSEI
~XR,
RWP
---1
selD
ex)! c-XSE NS[2
g,v. ,\
=
JXII B
JXINIB
f--
EXT Clk_d. ~h :)Sf
_
JXD
PHRSDC TCSOOO
=3
l
, DPOO-OP07,'
L\R-J
I
(
JXDP
J\D
SECP
8XO
EXT Cl
---4.>{'----,
I
J>'C
l;~DELAYLlNE
J07
:~~:~
PhRSA0J
J
I!
TCL)BO
'---1
CLK
~IP
TRl090
ICL130------
TRL 130
TCLJ)O ------~
TRL 180
TRU40
I
J
I
-------:.,J
R'y,E READ
TRL270 - - - - - - TRUDO
-1
REND
~
EXT
r--I
SXP
P'"RSAOO
~y
l
ii'"
FAM (FT25' 8,16
f---.
TYPO
lI--
TYPI
I
- - - ( M,,)-AN3 j -
l--f
D\ T
f--
f--;
J\'O
I--
- - - - - ------/
1 RK
;--.
OPE R
RO
REN
---------~
~----------~-i---------r--------SXJ
JPXO
f--
I
I
TCL100-----
/
rT'
;:~~:~
TR OELAv LINE
,",o,"_J
~_'MH
~JI5P f--
I
JFI
)fl,[5[T R"\RIT[ j'SISC~L_ _- - '
P7
I
.)t,[
-"-','A
I--
,-----1/ 100- 1021---
DCBSlT
IXO-I
ORDXO
IDS
IXO-4 1>.0-4
r-';RS 1
1,,_D_K_'_ \---I
PHf SL
IXO-~
I'IIRS
LI~~~:;"·····
>-00-07
--------. _ _
!
,~
!
I
l_____ __ L_
t----------~
(-.j
I
_
r---
Dr
r
__________ _____1
T
PVI MONR
------I
r
',\N~ST ; - - .
I
__D_OO-D_07_ _ _ _ _ _ _? - _ 1--------
1- L-,-J_----
j[_-
--------(
DAT
f----- lJ
DAI
/
;;:[I,<[)
G~--I
S
us
I
I
I
C'X K-I
TR(\ 1 IG ,
PtjJ~j/... l JU
"I!eT (, HP,
'eR, '3f t.:J,
',,', RI Tl
r-'-------r=
_________________________'__ J
elf
T~ __
]'_[~L--...
I (ll(,/,n ______
c=Y~Ht15
~
.
[)B(~
7
[)r-()
~
-,-
7/
.
D[)O·//
(1'1,,)
Figure 4-36. EP I\AD Controller,
Detui IcJ Block [)i(l~Jrorn
901 'J65A. 435
--------------------------'--- -----,--,-------------, ---'-------,--
t-151/4-152
XDS 901565
Paragraphs 5-1 to 5-2
SECTION V
LOGIC EQUATIONS AND GLOSSARIES
5-1
GLOSSARIES
Definitions of EP RAD file terms are contained in table
5-1. Table 5-2 contains a glossary of EP RAD controller
signals and table 5-3 contains a glossary of EP RAD
Table 5-1.
selection unit signals.
sequence.
5-2
All glossaries are in alphanumeric
LOGIC EQUATIONS
(See tables 4-8 through 4-19.)
Glossar}' of EP RAD File Terms
------------------------------------~---,
Definition
Term
B-counter
Flip-flops BOO through B12. Counts bits and bytes during exe~
cution of read order, write order, or checkwrite order
Byte cC:Jnter
Flip-flops BKO ar.dBK1. Used during execution of all order"
to count bytes of a service cycle
Condition code
A two-bit code tr.,nsmitted from the EP RAD file which indic0t-;s
the status of the EP RAD file to the lOP
Data in service cycle
A service cycle ciuring which data bytes are transferred from the
EP RAD file to the lOP
Data out s~rvice cycle
A service cycle J..,r:ng which data bytes are transferred from the
lOP to the EP RI.D file
D-r-egi~ter
Flip-flops 000 ti.rough 007. Used during execution of write
order or checkwi ae order to tramform data format from parallei
to serial. Used uu&ir.g execution of read order to transform ~'.ita
format from serial to ~arallel
Ene' data signal
Signal ED, which mal be generated by either the lOP or the
EP RAD control hr and which causes an end to data transfer
End service signel
Signal ES, which is ge:1erated only bi the lOP and which causes
an end of the input/output operation
Fast access memory (FAM)
module
FT25 module which stores a maximum of 16 addressable byte!:.
Receives data inputs from J-reglster and addrcss inputs from Lregister. Outputs of addressed register are dcsigr.a~(;;d RCO
through R07
FAM read cyc Ie
A cycle of opera~ion of the fast access memory (FAM) circuit,
during wh ich a byte is transferred from the addressed locatio!'l
in the FAM module to the K-register or the I-register
FAM write cycle
A cycle of opc:ration of the fast access memory (FAM) circui~
during which a byte is trar,sferred from the J-register to the 0-::1dressed location in the FAM module
Function indicator
A signal that indicates the t}/pe of function (AIO, ASC, HIO,
TIO, TDV, or 510)
(Continued)
5-1
XDS 901565
Table 5-1.
Glossary of EP R.A.D File Terms (Cont.)
Term
Definition
Function response signals
Signals FROD through FR7D. Signals transmitted to the lOP in
response to a function strobe (FSR) and a function indicator signal
(AlaR, ASC, SIOR, TDVR, TIOR, HIOR)
Function strobe
A signal /FS/ generated by the lOP to indicate that a response is
required of a controller
Indicator signals
Signals INDOl through IND16. Signals sent to the PET to indicate state of EP FAD controller during test
lOP byte signals
y
Signals DAOR through DA7R, DSOR through DB7R, DCOR through
DC7R, and DDOR through DD7R. Transfer data between the
controller and lOP. Signals DAOR through DA7R are also used
for exchange of orders
I-register
Consists of basic I-register (100 through 107) and extended 1register (J08 through 131). Stores data from either the FAM
circuit or the lOP
JP-register
Buffered latches JPO through JP3. J-pointer register establishes
the FAM module loco~ion for input
J-registe~
Buffered latches JOO through J07. Accepts data from the 1register or D-register fer transfer to the FAM circuit
KP-registp.r
Buffered latches K PO through KP3. K-pointer register, which
establ ishes the FAM .i":odule location for output
(
K-register
r-
Buffered latches K00 through K07. Accepts data from the FAM
module fOf transfer tu O-register, I-register, or D-register.
During execution of ;.=nse order, accepts data from S-register
and T-register for transfer to a-register
'--register
Buffered latches LOO through L03, and N L03. Addresses the
FAM circuit and Cal'se3 ir.crementing of KP-register or JPregister
Order code
A five-bit code indicating the type of orJer to be executed by
the controller (read, write, checkwrite, seek, or sense)
Order in service cycle
A service cycle during which order information is transm itied
from the controller te the lOP
Order out service cycle 'i.
A service cycle durinn which an order code is accepted from
the lOP
Order reg istei
Flip-flop ORDO and t;uTfered latches ORDl through ORD4.
Stores order code (seek, sense, read, write, or checkwrite)
during execution of order
a-register
Consists of basic a-register (000 through 007) and extended
a-register (008 through 031). Stores data for transfer to computer memory under control of lOP
PET
Peripheral Equipment Tester Model 7901
(Continued)
5-2
XDS 901565
Table 5-1.
Glossary of EP RAD File Terms (Cont.)
Term
Definition
PET data signa Is
Signals DPaO through DP07. Signals received from the PET to
simulate signals DAOR through DA7R during offline test
Phase control circuits
Flip-flops NPHFS, PHFSZ, PHFSl, PHRS, PHRSA, and PHTO
and associated circuits. Establish phase of controller and respond to subcontroller outputs and internal timing and control
signals
.
P-reg ister
y
Flip-fiops POO through P15. Used to generate checksum during
execution of read o~der, write order, or checkwrite order, and
to increment track address and sector address during intersec~vr
gap
Read sequence
Tha sequence of operations (service cycles, data transfers) that
takes place during execution of a read order
Request strobe acknowledge
signal
RSAR signal which ;s generated by the lOP to indicate that a
data e;~change ha$ taken place in f;3;;ponse to an RSD signa I
Request strobe dgnal
RSD signal wh ich is generated within the controller to request
dafa strobe from the lOP, causing a data transfer betweei-,
the lOP and the codro/lei
C!
RK-counter
Flip-fiops RKO through RK4. Indicates the number of acti':e
bytes in the FAfv~ module during execution of read order.. write
ordp.rr or checkwrik order
Sector address
A four-Lit code .vI, ich addresses one of the 12 sectors of ea,:h
track
Service call sigr,a!
SCD signal wh iel, i.; generated by tile controller when servIce is
re'luired for date transfer
Service conned
A state of the cOilh)IIer in which data transfers between t;~e
lOP end the con1 rc liAr may occur
Service cyc Ie code
A two-bit code indicating the type of service cyc Ie requested
by the control fer
S-register
Buffered latches
address
Subcontroller
A .standard set of modules which form part of every device controller and which ~)onitor and respond to lOP signals
Terminal order
An optional ordf;>r following execution of a seek order, sem,~
order, write order, read order, or checkwrite order, wh ich indicates count done interrupt, channel end, unusual end r or
command chaining
suo
through 503, and NS03.
Stores seelor
j
Track address
An l1-bit code which addresses one of 512 tracks on the surfcces
of the disc file. (Only 9 of the 11 bits are· used)
T-register
Buffered latches TOO through T1 O.
Stores track address
~------------------------------.~--------------------------------------------------------------____~I
(Continued)
5-3,
XDS 901565
Table 5- i.
Glossary of EP RAD File Terms (Cont.)
Definition
Term
Un it address
A three-bit code which addresses one of the eight {maximum}
EP RAD storage units inan EP RAD file
U-register
Flip-flops UO through U2.
unit
Write sequence
The sequence of operations (service cycles, data transfers) that
takes place during execution of a write order
Stores address of EP RAD storage
"
TobIe 5-2.
Glossary of EP RAD Contmller Signals
r-----------------------------~------------------------------------------------------------------
Odin Ition/Funct ion
Signal
/AIOI
Acknowledge input/output function line. Causes highest priority device with
interrupt calf line raised to send stat'JS and address data. Transmitted from
lOP to device controller
AIOC
Acknowledge I/o control
Enables gl.!ting of status for Ala if controller is
the highest priority device with interrupt call line raised
AIOM
Acknowledge I/o monitor. Indicat~s that controller has raised interrupt cail
line. Enables BSYC and AiOC if true! enables lAVal if false
AIOR
Acknowledge
ALT
Flip-flop which a Iternates a write orOE"1" with the ordei encoded in the PET
panel switches, and provides for skipl"'ing revolutions when writing in sing(e
track mode
ALTCK
ALT clock
ALTCKEN
ALT clock enable
ALTORD
PET-generate:! simulation of AL T
ALTYP2
ALT signal fo~ extended performance C·YP2) use
/ANO/-/AN3/
Sector address (angle) dato from selecTion unit
(ANOR-AN3R)
Sector !lddress receivers
AN10TY:'2
Equiva!ent to AN 1R or EXT
lASe!
Acknowledge service call funcfior, li;:c. Causes highest priority device with
service call I ine raised to send addres5 data
ASCB
Acknowledge service call buffer, Erables setting FSC if the controller is the
highest priorit}" device with service call line raised
f.SCM
Acknowledge service call monitor. Indicates that the controller has raised
a service call. Enables ASCB and BS':'C if truei enabics AVO if false
ASCR
Acknowledge service call receiver
IAVI/
Available input priority line. Driven by the lOP to the highest priority controller. Passed on by inactivf' control !ers as signe! AVO
I/o
receivt:r
(Continued)
5-4
XDS 901565
Table 5-2.
Glossary of EP RAD Controller Signals (Cont. )
Signal
Definition/Function
AVIR
Available input receiver
lAVal
Available output line
AVOD
Available output driver. Driven by any controller that is not addressed or
that does not have priority for an interrupt or service call
(BOO-B12)
B-counter: (BOO-B09) for byte count, (B 1O-B 12) for bit count
B05CK
B05 clock
B09Xl
Store a one in B09
BCE
B-counter count enable.
signals
BFSD
Buffered function strobe delayed.
through FR70
BIT?RWE
Read/write enable and bit number 7 (bhary 111). Times parallel transfer of
(OOO-D07)-- (JOO-J07) or (K:OO-K07) ---{DOO-DO?)
Gates TIO, SIO, and HIO status to FROD
~yte counter for seek, sense, and expanded interface byte hand I ing
BKO-BK1
BKWW
BKVvZ
BKZW
BKZZ
Permits (BOO-B05) to be incremented by clock
}
Byte counter decodes: ZZ
=
(0, 0); ZW
=
(0, 1); WZ - (1, 0); WW -- (1, 1)
BSYC
Busy control. Gates the address data to F ROD through FR7D for an ASC or
AIO wh~n priority recognized, thus defining the busy device for the lOP
BSYCU
Busy clamp latched from PHFSL to PHFS
BXO
Clear B'-counter
BXIMED
Preset term for B-counter (used on 360-byte sector medium speed controller)
BYTlID
BYT2ID
BYT4ID
}
Identify width of lOP interface (one, two, or four bytes)
CCH
Command chaining bit in terminoi order from lOP
CON
Count done flip-flop.
data transfer
CONPET
PET simulation of CON flip-flop
CER
Flip-flop set if checkwrite error or if preamble synchro~ization pattern
mis-sed
CERM
Mark fl ip-f1op CER
CERSET
i
Causes order in when set by lOP to indicate end of
Set fi ip-flop CER
(Continued)
5-5
XDS 901565
TobIe 5-2. Glossary ~f EP RAD Controller Signals (Cont.)
Defi nition/Function
Signal
I
I~
CHWER
Checkwrite error; set CER on noncomparison of disc file data and D-register
output during checkwrite operation
CHWEREN
Checkwrite error enable
CIl
Inte:-rupt call flip-flop may be set by lOP during terminal order
CIlRST
Reset CIl, true for Ala function indkator
ICLlI
Clock 1 MHz.
CUR
Clock 1 MHz receiver
CLIR
Clock signal from lOP
ClK
Clock divider flip-flop; creates a 1. 5 MHz clock when controller is used
as medium speed controller
ClK3MH
3 MHz clock
CNTRCI.KP
Clock sent to PET :" increment its internal counter
CSLI
Service call inhibit. A dt::lay of 100 to 350 ns to allow control logic to
settle between disconnecting a service cycle end raising a new service call
CYCEN
Control cycle enable term used in :.ing:e-phase mode (PET)
CYClE/C
Control cycle enable; lndicates when a phase cycle is possible {TCl cielai'
line)
CYCLER
FAM cycle enable;
(DOO-D07)
D-register; the register which shifts Jata between storage unit and controller
D07SET
Set 007; presets 007 when the T-rE:"~;ster and the S-register are to be incremented
1. 024 MHz signal from the CPU via the lOP
ind~cates when
fAM cycle is possible (TRL delay line)
lOA 0/-/DA7/
Bidirectional communication lines. Signals between the lOP and controller
are tr-.;nsferred via these I ines. The information carried includes dt:!vice address, AIO status, orders, terminal orders, operationa: status bytes during
order in, and data byti;' 1
{DAOD-DA7D}
Data I ioe drivers
(DAOR-OA7R)
Data line receivers
/DAL!
Data signal from storage unit to ccntroller
DAIR
Data rece iver
IDAWV
Manchester-encoded data to medium speed RAD storage unit
OAMD
Medium-speed RAD data driver
DAR
Synchronized data flip-flop; set bi' DAIR und DSR
(Continued)
'I.
L
5-6
---------------------------.------
XOS 901565
Table 5-2. Glossary of EP RAO Controller Signals (Cont.)
-----------------------------~--------------------------------------------------------------------------
Defi nition/Func tion
Signal
/OAT/
Data output to storage unit from 007
DATA
Data/order flip-flop; set for data, reset for order
OATAIN
Data in signal; true when data sent to lOP (read or sense)
DATA OUT
Data out signal; true when data accepted from lOP (seek, write, or checkwrite)
DATASET
Set flip-flop DATA
/OBO/-/DB7/
Oata byte 2 lines (B-lines).
four-byte interfac·;
(OBOO- OB7D)
Data line 'drivers
(DBOR- DB7R)
Data line receivers
/DCO/-/DC7/
Data byte 3 lines (C-I ines).
interface
Bidirectional lines that carry dota for two- or
Bidirectional lines carrying data f.:>r four-byf p
(DCOO-DC7D)
Data I ine drivers
(DCOR-OC7R)
Oata I ine receivers
OCA
Device controller address recognition.
(SWAO-SWA3) for address recognition
DCA47
Part of DCA controlled by bits 4 Through 7 for single byte contr0~lers.
used by EP RAD file)
DCB
Device controller busy fl ip-flop.,
DCBRST
Reset fl ip-flop DeB
DCBSET
Set fl ip-flop DeB
DCl
Start term for Tel delay line
!>et
Compares (DAOR-DA3R) with
(;"ot
by successful SIO
four-bi'~a
/000/-/OD7/
Oata byte 4 lines {D-lines}.
interface
(DDOO-OD70)
Oata I ine drivers
(OOOR-DD7R)
Data I ine receivers
/OOR!
Data or order indicator line. If false during service cycle, indicates that
A-lines contain data; if true during service cycle, indicates that A-lines
contain ord(:rs. Indicates address recognition for all instructions
OORO
Data or 0rder Ii i1e driver
DaRDEN
DORD enable
(DPOD-OPO?)
Data lines from PET
DRESET
Device reset, true when a power
failure
._
_occurs
_ _ _ _ _ _ _ _-----1I
Bidirectional lines carrying do;'o for
I
(Continued)
5-7
XDS 901565
Table 5-2.
Glossary of EP RAD Controller Signals (Cont. )
Definition/Function
Signal
IDs/
Dota strobe from selection unit
DSE
Data strobe enable.
ation
DSEM
Mark flip-flop DSE
DSL
D-register shift left.
DSR
Data strobe received
DVBSY
Device busy
IDvol
Selected device operational signal from selection unit
DVOR
Selected device operational signal receiver
DVSEL
Device selected
IOVTI
De'/ice test signal from selection unit
DVTR
Device test signal recE:iver
IDx2/
Request for two-byte interface (transfer 16 birs in parall~I).
or four-byte interface
False for one-
IDx4/
Request for four-byte interface (transfer 32 bits in parallel).
or two-byte interface
False for one-
DXK
Transfer contents of K-register to O-register; (KOO-K07) ---- ([,UO-DO?)
OXP
'''ransfer contents of P-register to D-reg:ster; (P07-P14j - - - (000-007)
OXSR
Shift contents of O-register 10 right
IE 0/
End data line.
line
EDD
End data driver
EDJ
EOO gating term, combines all conditions for end data
ED15ET3
End data flip-flop
EDR
End data receiver
EDU
End data from lOP or PET
ERSTOP
Error stop switch signal from PET, hairs operation on error
EXT
Extended performance operation
FAULT
A fault condition cous~d by SUN, WPV, or RER
Gates DSR into RWCK during a read or checkwrite oper-
,
Used when incrementing T-register and S-register
Bidirectional Iine true ",hen the lost elata byte is on the
(Continued)
5-8
XDS 901565
Table 5-2.
Glossary of EP RAD Controller Signals (Cont.}
Signal
Definition/Function
FNTP
Simulated function strobe enabled by PET
/F RO/-/F R7/
Function response lines from lOP
(FROD-FR7D)
Function response line drivers
(FROR-FR7R)
Function response line receivers
/FS/
Function strobe line. The /FS/ signal from the lOP defines period during
which the controller should re~pond to function indicator or acknowledge
service call indicator if it recognizes its address or priority. Used as a
clock term for setting or resetting device controller busy flip-flop DCB or
for setting FSC _
FSC
Service connect flip-flop. Defines the period during which data or ordei'~
may be requested and transferred
FSCU
FSC for lOP or PET
FSLD
Function strobe driver
FSP
Offline simulation of function strobe
FSPOCSL
Simulated CSL signal for offline "peration
FSPS
Simulated function strobe from pET
FSR
Function strobe rece:ver
FSU
Function strobe, lOP or PET
GNDxxx
Ground connection (false levei)
/HIO/
Halt Va function line. CallSE":s the controller to ~erminate the
sequence and to return to ready :.tate
HIOP
PET simulation of HIO function indicator
HIOR
Halt
HIOU
HIO function indicator, PET or lOP
/HPV
High priority interrupt fine. When raised, overrides a higher priority
device interrupt call. Not pr€;~E'nl'ly used in Sigma peripherals
HPID
High priority interrupt driver
HPIL
High priority interrupt latch. Inhibits AIOM, thus preventing a low
priority interrupt from respondirg to an AIO instruction
HPIR
High priority interrupt rece ived
/HPS/
High priority service call line. When raised, overrides any higher
priority with a service call raised. Not presently u5ed on Sigma peripherals
HPSD
High priority 5ervice cell driver
Va
I/o
receiver
~--------------------~~------~~--~~----------~-------------------------------------------~
(Continued)
5-9
XDS 901565
Table 5-2. Glossary of EP RAD Controller Signals (Cont.)
Signal
Definition/Function
HPSl
High priority service latch. Inhibits ASCM, thus preventing a low priority
service call from responding to ASC
HPSR
HIgh priority service receiver
(IOO-·I31)
Incoming data storage buffer (I-register)
lIe!
Interrupt call. Raised by the controller in response to on order modifier or
a terminal order (zero byte count, channel end, or unusual end)
ICD
Interrupt call driver
IIDO/-/ID2/
Device address signals from controller to storage units
IN
Input/output control flip-floPi set for input, reset for output·
INC
Inhibit calls. Prevents interrupt call or service call when the controller is
offline or when controller de power fails
(IND01-iND16)
Indicator drivers to PET
INDUP
PET indicator select switch signal. Sclects upper or lower set of functions
to be displayed by (IND01-IND16)
INI
I~hibit input. Permits signal /Avol to go true when required, but forces
all other signals between lOP and controller false when the controller is
offline or when the controller de pO'_VI'~r fails
INl
Incorrect length flip-flop. Set if hyTt-! count is not a multiple of sector
storage, if seek byte cOl,;nt is not tWJ{ or if sense byte count is not three
INlEN
Enable set of flip-flop INL
INlM
Mark flip-flop INl
INLSET
Set flip-flop INL
INSET
Set flip-flop IN
lOP
PET signal. True for online, false for offline (during test, lOP true enables
monitor mode of PET)
II oR!
Input/output request. Definc·s direction for communications on the dai-.l lines
for service cycie. Defines siatus for instructions
lORD
Input/output request driver
IORDEN
Enable lORD
IIP/
1ndex pulse from storage unit
IPR
Index pulse receiver
(IXO-l - IXO-4)
Clear I--register
IXD-l
Enable transfer of (DAOR-DA7R) - - (I00-107)
(Continued)
5-10
XDS 901565
Table 5-2. Glossary of EP RAD Controller Signals (Cont. )
Signal
Defjnition/Function
IXD-2
Enable transfer of (DBOR-DB7R) -----(108-115)
IXD-3
Enable transfer of (DCOR-DC7R) ---- (116-123)
IXD-4
Enable transfer of (DDOR-DD7R) - - - (124-131)
IXEN
Extended interface option
IX1-1
Enable transfer of (108-115) ---- (100-107)
IXI-2
Enable transfer of (116-123) -
IXI-3
Enable transfer of (124-131) ---(100-1O7}
IXR-l
Enable transfer of (ROO-R07) - - - (108-115)
IXR-2
Enable transfer of (ROO-R07) - - - (116-123)
IXR-3
Enable transfer of (ROO-R07) - - (124-131)
(JOO-J07)
J-register (input buffer for FAlv', module)
JFI
J-register filled latch
JFIRESET
Force JFI false
JFIXl
Force JFI true
(jPO-JP3)
J-pointer register (JP-register). Address register for data written intoth~
FAM
jPXO
Clear the
JPXL
Load the incremented JP address infO the JP-register (LOO-L03)--(JPOO':" .I P03)
JXO
Clear the J-register
-(100-107)
JP-regi~ter
Load the contents of the D-regisi"er into the J-register:
(DOO- D07) ~ (JOO- J07)
JXDP
Load PET data into the J-register
JXI1B
Load contents of I-register intc J-register (one-byte interface only)
JXIN1B
Load contents of I-register intc .I-register (not one-byte interface)
(KOO-K07)
K-register. Provides sense date storage, preamble synchronization pattern
generation, and functions as FAM module output buffer
.
KA8
Control latch indicating that FAt.\ module is empty and last byte is in
K-register
KFI
K-register fi lied latch
KFICK
KFI delay flip-flop used for setting rate error flip-flop RER
~-------------------------~-----------------------------~
(Continued)
5-11
XDS 901565
Table 5-2.
Glossary of EP RAD Controller Signals (Cont.)
Signal
Definition/Function
~----.-----------------+------------------------------------
t
5-12
KFID
Latch signal that sets KFICK
KFIDXl
Force KFID true
KFISET
Selects condition for forcing KFI true
KFIXl
Force KFI true
(KPO-KP3)
KP-register (K-pointer register).
FAM module
KPXO
Clear the KP-register
KPXL
Load the incremented KP address into the KP-register; (LOO-L03)--(KPOO-KP03)
KXO
Clear the K-register
KXOEN
Enable KXO
KXPRE
Load the preamble synchronization pat4-.arn into the K -register
KXR
Load the addressed FAM byte into thE: K-register; (ROO-R07)-KOO-K07)
KXREN
Enable KXR
KXSENSEl
Load second sense byte into the K-res!ster; (T07-T10) - - (KOO-K03),
(SOO- SO~) - - - (K04-K07)
KXSENSE2
load third sense byte if"lto the K-regjs~er; (ANOR-AN3R) - - - (KC1-K07)
(LOO-L03)
L-register; address regis~er for FAM modulE'!
LJ~STSEC
PET decode of sector preceding index mmk
(LEO-LE2)
Excl usive OR adder used to incrementiP-register and KP-register
LIH
Latch inteirupt high. Retains thE'! fact "hat a high priority interrupt has been
raised. Enables AIOM
LIL
Latch interrupt low. Retains the faci that a low priority interrupt has been
raised. Enables AIOM
LSH
Latch service high. Refains the fact ;hu,' a high priority service call has
been issued. Enables ASCM
LSL
Latch service low. Retains the fact thc:~ a loVi priority service call has
been issued. Enables ASCM
MANRST
Manual reset from RSTR (lOP) or from RSTP (PET)
/NMANRST/
Manual reset signal from controller to fi'orage unit
(000-031)
a-register; data drivers to lOP
OPER
Device operational flip-flop
--,-------------------------------------------~
(Continued)
Address register for data read from the
XDS 901565
Table 5-2. Glossary of EP RAD Controller Signal (Cont.)
Signal
Definition/Function
(ORDO-ORD4)
Order register flip-flop and order register buffered latches
ORDIN
Order in signal
ORDOUT
Order out signal
(ORDP1-ORDP4)
PET order switch signals used to load order register
ORDXO
Clear the order register
ORDXIOP
Load the data line (lOP) info the order register; (DA3R-DA7R}--(ORDO-ORD4)
ORDXPET
Load the PET data lines into the order register latches; (ORDP1-ORDP4)
- - - (ORD1-ORD4)
OSCJ
(OXO-l - OXO-4)
I
I
Oscillator jumper for 3 MHz operation
I
Clear the O-register
:)XAIOST
I
Enable status response to Ala; (RER, SUN, WPV) - - (000, 002, 00.3)
(OXK-l - OXK-4)
I
j
Load contents of K-register into O-register (KOO-K07)-(000-007) and contents of I··re:gister into O-register. (I08-I31)--(008-031)
OXKEN
Enable OXK
OXORDIN
Enable status signals for order in; (TER, INL, 1, UNE)-(ODD, OU1, 003, 004)
OXSF:NSEl
Load first sense byte into O-register; (TRPRO) - - (000); (T00- T06)
- - - (001-007)
(POO- P15)
P-register; a two-byte parity register used to generate parity for the storage
unit and to increment the T-regi:ter and the S-register
POOSET
Set fI ip-flop POD
POOSETEN
Enable set flip-flop POD
P13LD
Increment sector number from 1011 to 0000
P13LDEN
Enable increment sector number
Ipcl
Parity check. Bidirectional line which is raised whenever byte 0 parity
(A-line parity) should be checkej (not used by EP RAD file)
PCD
Parity check driver
PER
Parity error flip-flop (read operation)
PEREN
Enable set PER
PET
Inverted lOP signal; indicates offline operation
(Continued)
5--13
XDS 901565
Table 5-2. Gloss~ry of EP RAD Controller Signals (Cont.)
Signal
~
Defi n i ri on/Functi on
PHFS
NPHFS flip-flop in reset st9te; idle phase, indicates function strobe can be
accepted
PHFSl
PHFSL f1ip-fioPi indicates function strobe acknowledge sent to lOP
PHFSCYC
PHFS and CYCLE/C signal true
PHFSDAT
PHFS and DATA signal true
PHFSET
Set flip-flop NPHFS
PHFSLNFN
PHFSL and SCN true (service call)
PHFSTOD
Phase FS of data transfer (PHFSDA T) or phase TO (PHTO)
PHFSZ
PHFSZ flip-floPi delay
PHRS
PHRS flip-flop; RSD is seilt to lOP, Clnd FAM cycle is ~!.::rted for previously
processed bytes
PHRSA
PHRSA flip-floPi
PHRSADO
PHRSA and data out; (DATA, IN)
PHRSAOO
PHRSA and order out; (DATA, IN)
PHRSAORD
PHRSA and order (DATA = 0)
PHRSASET
Set phase flip-flop PHRSA
PHRSDO
Phase PHRS and data out; (DATA, J;{,
PHRSET
Set flip-flop PHRS
PHRSNED
Phase RS and not end data
PHTO
PHTO flip-flop; termination phase used to return to PHFS
POST
Control fl ip-flop tha t indicates par:tl check portion of sector
POSTB89
POST andB08 and B09
PRE
Control flip-flop that identifies preamole pornon of sector
PRESET
Set fI ip-flop PRE
PRST -1,
PRST-2
Reset term for P-register
phas~
;eque~t
for gathering status of storage unit
strobe acknowledge
(1, O)
:-=
(O, 0)
=
(1, 0)
rSPB
Preamble synchronization bytes; true for two byl"e times during search for
preamble synchronization pattern
PSPM
Preamble synchronization pattern missed
PSPR
Preamble synchronizotion pattern recognized
_ _- - -_ _ _ _ _ _ _---1._ _ _ _ _ _ _ _ _ ..•.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
(Continued)
5-14
:=
XDS 901565
Table 5-2.
Glossary of EP PAD Controller Signals (Cont.)
Signal
.Defi n i f-jon/Function
PSPWEN
Preamble synchronization pattern write enable; generates the four-bit
preamble synchronization pattern (1100)
PT18S
PT18 switched. Ground for Kl and K2 (INi and INC) on the All 7 module.
This term is normally from the PT18 power supply, but may be chassis ground.
It is fed via switch S 1 (onl ine/offl ine) on module LT25
/PWRMON/
Power monitor line from selection units
PWRMONR
Power monitor signal from selection unit; true when addressed storage unit
power fails
PXS
Load contents of S~register into P-register; (SOO-S03) - - - (P12-P15)
PXSR-l,
PXSR-2
Sh iff contents of P-register to the right
PXT
Load contents of T-register into P-register; (TOF) - - - (POO); (TOO- T1 0)
- - (POI-Pll)
(ROO-R07)
Output of addressed location i:-. fast access memory (FAM) mcdule
RCHW
Read order or checkwrite order
READ
Read order
READRR
Clock signal for FAM read cycle
REMPTY
FAM module (R-register) empt~'
REND
Read or checkwrite cperation end read/write enable
REPEAT
PET continuous eye Ie switch signal
RER
Rate error fl ip-fioPi indicates srurage un it pracessed inform':ltion faster thur'
lOP
REREN
Enable set fl ip-flop RER
RERM
Mark flip-flop RER
RERSET
Set flip-flop RER
RESET
Reset EP RAD controller circui15
(RKO-RK4)
RK-counter; indicates number of active bytes in FAM module. Counts do ....·n
from 1 1111 when data is written into FAM module; counts up when data IS
read from FAM module
RKCK
R-counter clock
RREAD-l }
RREAD-2
RREAD-4
Control terms true when FAM read cycle has started
(Continued)
5-15
XDS 901565
Table 5-2.
Glossary of EP RAD Controller SignalS (Cont.)
Signal
l
Definition/Function
/RS/
Request strobe. Requests the transfer of data or orders while service connected. One byte, halfword, or word is transferred following each RS.
May be used as a clock for gating data or orders into the controller or for
changing state of control logic circuits
/RSA/
Request strobe acknowledge. Raised Ly the lOP to indicate that the data
or order transfer is complete. Causes RS to go low
RSAR
Request strobe acknowledge receiver
RSARC
Request strobe acknowiedge latch
RSAU
Request strobe acknowledge from lOP or PET
RSAUEN
Enable RSAU for PET
RSD
Request strobe driver
RSET
Request strobe in phase RS
/RST/
Va
RSTP
PET reset pushbutton signoi
RWCK
Read/write clock (3 Mi-:z oscillator
RWE
Read/write enable flip-flop; allows c!"'~::J transfer operat;~>ns to begin
RWERST
Reset fl ip-Hop RWE
RWP
Read/wdte possible flir-flop; it1dicate-: that co data transfer order call be
accepted
RWPRST
Reset fl ip-flop RWP
reset. Norm(1l1y rf!sets 01/ contl"jl logic in the controller and device.
RST is generated by VA RESET or SYSTFM RESET switches, by a programmable reset for the Sigloa 5 or Sigma 7, by the RESET position of the
INITIALIZE switch for the Sigma 2, N by the start term as power is applied
to the Sigma 2, 5, or 7
I
RWRITE-l
RWRITE-2
RWRITE-4
:
1
0."
data strobe bit ratp. clock)
Control terms true when FAN. write cycle has started
J
(500-S03)
S-register; contains address of next sedor to be operated on by read order
or checkwrite order
/sc/
Service call.
cycle
/5C1/
Track and sector shift clock to storage ~nit
SC1D
Shift clock driver
Raised by the controller to start a data or order service
~~------------------~--------------------------------------------------------------------------~~
(Continued)
5-16
XDS 901565
Table 5-2.
Glossary of EP RAD Controller Signals (Cont.)
Signal
Definition/Function
/SC2/
Data clock to storage unit
SC2D
Data clock driver
SCD
Service call driver
SCN
I
SCNMEN
I
I
Service call flip-floPi marked on when service is required and kept in set
state when additiona I service required
Enable mark flip-flop SCN
I
Enable reset fl ip-flop seN
SCNREN
SCR
SCRSET
SCSET
SECOMPR
I
I
I
I
I
Read/write service flip-floPi set or reset when additional bytes can be stored
in FAM module during execution of write order or checkwrite order, or read
from FAM module during execution of read order
Set flip-flop SCR
Inhibits SCRSET if true
Sector comparei (ANOR-AN3 R) matches (500-503)
SECP
!
j
Sector pulse or index pulse
SECPD
I,
Sector pulse disable flip-flop
SFCPDM
I
I
j
I
I
I
Mark flip-flop SECPD
SEEK
II
Seek or0er in procec::s
SEKSEND
I
End signal for seek order or sense ,.,rder
I
I
SEhl
I
Sense fI ip-fioPi indicates sense operation possible
I
SENSE
SGLPH
I
Sense order in process
iI
PET single-phase switch signal
I
PET singie-phase clock signal
I
SGLPHCK
PET single-track mode switch signal
SGLTRKP
/SIO/
I
Start I/o function indicator.
accepted
I
PET S10 function indicator switd-, signal
II
SlOP
I
SIO possible
SIOPOSS
SIOR
Causes the device controller to go busy when
I
Start input/output receiver
SIOU
SlOP or SIOR
SKSBK
Seck order or sense order with final byte count
(Continued)
5-17
XDS 901565
Table 5-2.
Glossary of EP RAD Controller Signals (Cont.)
Signal
Definition/Function
ISLN/
Select now line to selection units
SLND
Strobe sent to storage unit to connect the storage unit addressed by
(SUOD-SU2D)
/SP/
Sector pulse line to selection units
SPE
PET single~phase enable flip-flop
SPR
Sector pulse from storage unit
SREAD
Read cycle from FAM F!odule is pending
SREADEN
Enable SREAD
STSH02
SIO, TIO, HIO status device not busy and operational
STXPEN
Enable SXP tJnd TXP .
(SUOD-~U2D)
Storage unit address signals
SUN
Sector unavailable flip-flop (error)
SUNM
Mark fl ip-flop SUN
SUNSET
Set fI ip-flop 5UN
(SWAO-SWA.3)
Device controller addres:. !:witches bcated on LT2~ module
SWRITE
Write cycle into FAM ,nodule is p€.l1ding
sxo
Clear 5-register
SXJ
Load contents of J-reg ister into S-register: (JOO- J03) ----- (T07- T1 0),
(j04-J07) ---- (SOO-503)
SXP
Load contents of P-register into 5-f€gister: (P12-P15) - - - (500-503)
SXPEN
Enable 5XP for PET
(TOO- T1 0)
T-register; stores track address
TCLxyz
Phase delay I ine outputs (xyz = c.lel\JY in nanoseconds)
TC5xyz
Phose delay I ine sensor outputs (xyz
TDLxyz
D-register delay line outputs {xyz
TDT
TDL delGy line fI ip-flop
TDTl, TDT2
Buffered outputs of TDL delay line
TDT5ET
Set fI ip-flop TDT
ITDVI
Test device function indicator line
(Continued)
5-18
=
=:
delay in nanoseconds)
delay in nanoseconds}
XDS 901565
Table 5-2.
Glossary of EP RAD Controller Signals {Cont.}
De fi nit ion/F un ction
Signal
TDVP
PET simulation of TDVR signal
TDVR
Test device receiver
TDVU
TDVR or TDVP
TER
Transmission error signal (CER, PER or RER)
In 01
Test I/o function indicator. Tests the I/O system.
same as for the HIO and SIO commands
TIOP
PET simulation of TIOR signal
TIOR
Test
TIOU
nOR or TIOP
TOF
Track overflow bit
TORD
Terminal order
/TRK/
Track address line to sdecticn units
TRKRST
True when PET interval counter equals counter reset switch setting
TRLxyz
TRL delay line outputs (xyz ::::: delay in nanoseconds)
/TRP/
Track protect switch signal from selection unit
TRPR
Track protect swiich signal re.:.:eiver
TRSxyz
TRS delay line sensor outputs (xyz. ::::: delay in nanosecond5)
TSE
Track shift enable fl ip-flop
TSH
Gating term that indicates no! SIO, or HIO is for this controller becav:;e
of address recognized. Used io enable gating of status to (FROD-FRlD)
nSH
Gating term that defines the instruction being performed is a TIO, TDV,
SIO, or HIO
TXO
Clear the T-register
TXJ
Transfer contents of J-register to T-register: (JOI-J07)--(TOO-T06)
TXP
Transfer contents of P-register to T-register: (POl- P07) ---:-(TOO-T06)
/TYPO/,
/TYP1/
TYPO~
TYP1R
(UO-U2)
Status returned is the
I/o receiver
Storage unit type signals from seiection unit
Storage un it type
rec~ ivers
Storage unit address loaded by an SIO operation
(Continued)
~--------------------~--------~-------------
J
5-19
XDS 901565
Table 5-2. Glossary of EP RAD Controller Signals (Cont.)
Definition/Function
Signal
(UASO-UAS2)
PET switch signa Is for storage unit address
UNE
Unusual end flip-flop
WCHW
Write order or checkwrite order in process
/WEN!
Write enable signal to storage unit
WEND
Write enable driver
WIDE
True when wide interface option (32 bits) is used and a write, read, or
checkwrite operation is performed
WPRE
Write preamble
WPV
Write protection violatior. flip-flop (error),
WPVSET
Set fI ip-flop WPV
WRCH
Write, read, or checkwrite operation in process
WRITE
Write order in process
l
II
Table 5-3.
Glossary of EP RAD Selection Unit Signals
Defin ition/F~,:.,ction
Signal
......
5-20
O~t::>uts
of 2C''1 transformer in power distribution
ACSENSE1,
ACSENSE2
Powei monitor ac inputs.
panel
/ANO/-/AN3/
Sector address signals to EP RAD contrc~hr
(ANOD-AN3D)
Sector address signal drivers
AOK
Output of Fower monitor.
is on
CLKUNDLY
undelayed clock discriminator output
CLOCKDLY
Delayed dock discriminator output.
DAID
When true, indicates that ac and dc power
CLOCKNEG,
CLOCKPOS
Inputs to clock discriminator
/DAI!
Data signal to controller
DAID
Read data flip-flo?
IDATI
Dcta signal from controller
DATR
Data rece iver
IDSI
Data strobe to controller
DSD
I
Data strobe driver
(Continued)
U<;ed to clock read data flip-flop
XDS 901565
Table 5-3.
Glossary of EP RAD Selection Unit Signals (Cont.)
~------------------------~-------------------
Signal
Defin irion/Function
IDvol
Device operational signal to control-ler
DVOD
Device operational driver
/DVlI
Device test signal to controller
DVTD
Device test driver
/IDO/-/ID2/
Storage unit address signals from controller
(IDOR-ID2R)
Storage unit address signal receivers
IIP/
Index pulse signal to controller
IPD
Index pulse driver
LIMITNEG,
LlMITPOS
Inputs to data decoder
If true, extends duration of
LONGSTROB
Strobe output of pulse packing compensator.
signal CLOCKDL Y
IMANRSTI
Manual reset signal from controller
MANRSlR
Manual reset signal receiver
MC3
3 MHz signal divided down from frequency doubler.
Manchester-encoded dora
MC6
6 MHz signal output of frequency doubler
(NMOD 1- NMOOS)
Module iocation signals for LTl 05 Spares Selector modules
PDLY
Power or signal delayed 10 sec(\nds
POS25SENSE
Sense +25V input
POWERON
Power OUi indicates that all conditions necessary for operation are
present
RDAMPNEG,
RDAMPPOS
Used to create
Outputs of read amplifier
Inputs to read amplifier from read/writ"e couplers.
(d
= 0, 1,
2, 3,
RDXOdNEG,
RDXOdPOS
46 5, 6, 7)
SAE
Sector amplifier enable
/SC1/
Track address shift strobe. Consists of 11 pulses from controller during
intersector gap time
/SC2/
Data strobe from controller
~------------------------~----------------~~~--~--------------------------------------"----~
(Continued)
5-21
XDS 901565
Table 5-3.
Glossary of EP RAD Selection Unit Signals (Cont. )
Signal
Definition/Function
SC1R
Track address shift strobe receiver
SC2R
Data strobe receiver
SECT
Sector amplifier output
SECTNEG,
SECTPOS
Sector track signals
SEl
Unit selected.
/SLN/
Select now strobe from controller.
SLNR
Select strobe receiver
/SP/
Sector pulse signal to controller
(SPO-SP2)
Three-bit code that enables read/wri t \.! head selection signals (YSPo-YSP7)
for spare Y-select value
SPD
Sector pulse driver
SPSEL
Spare select signal, true when spare :eud/write head :s addressed
TGn
Outputs of track protect matrix (n = UO, 01 1
(TRO- TR10)
Tra(;k address register
TR5AG, TR5BG
Track address register bit 5.
when SPSEL is true
/TRK/
Track address bits from ccmtroller; read while SCl R is true
TRKR
Track address rece iver
(TRM 1X2- TRM 1X4)
Track address register bits 2, 3, and ~.. Represents X-value for selection of
normal read/write head or spare read/write head
/TRP/
Track protect signal to controller
TRPD
Track protected signal driver
/TYPO/,
!TYP1/
Storage unit type signals to controller
TYPOD,
TYP1D
Storage unit type drivers
True when (lDO-ID2) compare with address switch signals
•••
15, 16)
Control=: rE..'Od/write head selection.
Disabled
USLA
Unit select flip-flop. Set if storage unit has been addressed by (IDO-ID2)
signals, and SLNR is true
USLB
USLA buffered
WDM1,
WDM2
Write data fl ip-flops.
Used to encode data in Manchester form
(Continued)
5-22
Used to set unit select flip-flop USLA
XDS 901565
Table 5-3. Glossary of EP RAD Selection Unit Signals (Cont.)
Signal
Defini tion/Function
WDS
Synchronized write data fI ip-flops
/WEN/
Write enable signal from controller
WENR
Write enable signal receiver
WRTAMP1,
WRTAMP2
I
Write ampl ifier outputs
(XO-Xl)
Represents X-vaiue (most significant actual digit of track address) of spared
address
(XOB··X7S)
Buffered (XC-X7) signals
(NXSP2-NXSP4)
Represents X-value of selected spare read/write head.
(TRM1X2-TRM1X4) if SPSEL is true
(YOO-Y63)
Outputs of Y-select matrix
(YLO-YL7)
Represents least significant octal digit of spared track address (least
significant octal digit of Y-vaiue)
(YLOB- YL7B)
Buffered (YLO-Yl7) signals
(YMO-YM7)
Represer.ts middle octal digit of spared track address (most significant
octal digit of Y-value)
(YMOB- YM7B)
Buffered (YMO- YM7) signals
(YS Po- YS P7)
I
Controls
Y-value of addressed spare read/write head, controlled b)' (SPO-SP2) an0
SPSEL
~~-----------------~-----------------------------------------------------------------.--------~
5-23/5-24
XDS 901565
Paragraphs 6-1 to 6-2
SECTION VI
DRAWINGS
6-1 SCOPE OF SECTION
This section contains engineering drawings necessary to
support the text of other sections and a list of related
engineering data (table 6-1) necessary to maintain the
EP RAD File.
6-2 LOCATION OF RELATED TEXT
Figures 6-1 through 6-3 are discussed in paragraphs 4-5.
Figure 6-4 is discussed in parfJgraph 4-2. Figures 6-5
through 6-9, which are logic diagrams of the EP RAD selection u~lit, are discussed in paragraph 4-103. Figures 6-10
through 6-13, which provide detailed information concerning the reed/write head selection matrix, are discussed in
paragraph 4-103. Figure 6-14 is a schema~ic of a modified
motor control assembly which is installed on some EP RAD
storage units. Figures 6-15 through 6-22 are schemati c
diagrams of the EP RAD contrl)ller, showing differences
introduced by the logical sparing option. Differences introduced by logical sparing circuits are discussed in paragraph 4-111.
Table 6-1. list of Related Engineering Data
Drawing Number
Title/Content
134029
Wire list, motor control assembly
134293
JT18 operating procedure
137532
Wire list, power distribution panel
139812
Wire list, switch power and connector
139866-202
Wiring data, EP RAD seledion unit
139866-502
Wiringdato, EP RAD
139866-902
Wiring data, EP RAD selection unit
146883-002
Logic equa:ions, EP RAD controller
i46883-100
li:;t, s::;:1ol dictionary, EP RAD controller
146884-202
Wiring data, EP RAD controller
146884-502
Wiring data, EP RAD
'146884-902
1~7608
148784
sele~ti"on
unit
con:r::-I!~r
IWi ring data, EP RAD co",,,11 er
Wire list, power, EP RAD controller
I
Wire list,
c~binetl p~wer
6-1
TBI
¢s
TO DISC
MOTORS
N
N
G
TB2
EI
G
INT
-n
cO·
S
C'!i
0I
~
-0
0
~
.,
(b
CJ
......
'"
.,
X
~
0
s.
tn
o·
:J
'¢
JI
-0
120V,5Q160 H r
(b
INPUT
0
+25V
VI
REMOTE-ON-OFF
0
:J
0-
VI
GRD
...
K5
120'1, 50/60 H r
tn
()
:::r-
REMOTE ON-OFF
OUT PUT
(i)
3
....
0
o·
0
o·
co
T81
POWER
a
MONITOR
3
{c;
9
120V,
~O/60
Hi
OUTPUT FANS
120 V, 51')/60 Hr
OIJTPUT rANS
120 V, 50/60 HZ
9UTPUT FflNS
E2.
s NOTES:
~.SR1 SHOW~ _Ii'~
"-.
\
120V, 50/60 HZ
~
EFEREN ... .:
OFF POSITION
xcs DW'''"!'
.'''' • 0
. . ., . 1-~-·5
"I ~ ,)vI
OUTPUT FANS
JII
Ill"'; 50,,1'..0I1Z
OUTPUT FANS
L..r---~
-n
01 02 03 04 OS 06 07 OS 09 II) II 12 13 TIl 15 16 17 18 19 20 21 22 23
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NOTE: REfERENC!: XDS DWG: 14'Y337- 16.'\
I
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III
46
46'46
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VIEWED FRCM URING SIDE
CD
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22 23 2'1 25 26 27 2B zg 30 31
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12 13 II! 15 16 17 18 19 20 21
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01 02 03 0'1 OS 06
CHASSIS
XDS 901565
TBI
GRtlLr..'UA --+-~-+---,
,- -
----------- i
I
I
DISTRIBUTION
TBI
CH.lSSIS
I
TBZ
I
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ACSEi'\SE I
~~c {:J11~1-+---0--+---:--;--------.-------<>-:-tz
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9
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SLOT
.
I
I
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I
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I
~
~
17
_____________ _
J
b;-o-1
C.~DO,)B ~
I
UP Trl SPEED
StITCH
,---1
10
I
~!O~4-~__~~-4~
12
I IT 29
I CALIBRATION 1
AC
2
4B
I
r--
I
I
I
26
AOK
DELAY
(SLOt)
I
I
-----t
DC
SENS:iR
(+
'l
L ___J
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(FAST)
---~
SENSC'R
POS2')VB
POWER MONITOR
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40
42
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22
40
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SLNR
>
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UNIT
10111
ADDRESS
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~
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~'
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C)l
)/SP/
~'
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J
C'9
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3
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)/.011/
SECTOR
ADDRESS
lB
~
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:!'.l
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y;t..3!
n
t---+-- SC III
NJSU
Fig u r e 6 - 7 .
NOlL RTHRHJCr 'XDS nWG: 149337-'-JA
In p lJ t 1 0
6-10
LJ
t PlJ 1
[P RA D Se lee t ion Un it,
C i leu its Log i c D jag ram
I
XDS 901565
+'IY
mo
1R2
NTR2
1I1R3
!fl'R'I
313
lITGOI
2~
OS
I!II
:iJ...-1 0 8
18
I 8 '--__--'--=---'--_--' 36
SURfACE 2
\
NOTE:
REFERENC~_XD~£?WG:
149337-14A
r - - - - - - - - ----
---'--------------------1
Figure 6-10. Head Location Chart
(Slleet 1 of 2)
901565A.604/1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -_ _ _ _ _ _ _-1
6-14
XDS 901565
...
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co
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27
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NOTE: REFERUKE XDS DWG: 149337 - A15
r - - - - - - - - - - - - - - . - - - - ...
-.------------------i
Figure 6-10. Head Location (hart
(,I I(:C t 2 of 2)
....-------~.---------~
6-15/6-l-6
XDS 901565
"
I
lflClC
IDa
DO - 31
Y SELECT
6'1 - 95
YOO
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256 - 287
no - 351
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07
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- 15
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- 15
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- 16
- 16
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16
- 16
, ..6
- 16
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- 17
- 17
- 11
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- 11
YlS
- 19
- 19
19
- 19
TII8
- 19
• 20
- 20
- 20
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- 20
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- 21
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- 22
23
- 23
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- 25
- 26
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- 28
- 29
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NOTE: REFERENCE XDS DWG:~49337-12A
901565A.611
.__1
L---_ _ _ _~_ _ _ _ _ _ _ _ _~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~,. _ _ _
Figure 6-11.
Head Centertap Chert
6-17
XDS 901565
III' U T
flUTPUT
PIN
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238
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098
038
078
28
12
22
23
211
25
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Figure 6-12.
6-18
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XDS 901565
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NOTE: REFERE:"'KE XDS DWG: 149337-13A
Figure 6-13.
90!565A.613
Input/Output and Start/Finish location Cbart (Without Logical Sparing)
6-19/6-20
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1_- ___.____ _
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I«IlU LOCATICIf OiART
TRACK lIO?[SS
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00 - 63
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64 - 127
193
128 - 191
188
192 - 255
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218
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I)iogrom
9G1565A.614
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Figure 6-16.
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Channel, (,cllcmatic Diagram
(;1
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128 - 191
188
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178
256 - 319
158
320 - 383
36't - 'PI7
146
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12B
192 -
1m3
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13
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1K3
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118
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Chan~el (Witl] I o~ical Sporing), Schematic
Diagram
901)651\.617
NOTE: REfERENCE XDS DWG: 14 9339-9B
i
l._ _ __
.
_.--- --------_ ..... _---_... - . - . - - - - - - -
6-24
XDS901565
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C
25
01
NTR2
20
37
E
18
18
Ie
Ie
POlY
sc 1I~
TPSAG
37
TR9B
TR88
TRSB '"'
31
28
38
TR7
TR~
50
TRID
~12A
18
TRIJ8
12A
18
PDty
POL Y
SCIR - - - -
SC I ~
~ NTR5BG
-0
NTR9B
- -------------------1
NlllE. RIILI\~I'(1
NT i-"A:, ~
I\j f-I~.llx4
I)
T
81
0)
IEHR
06
III
STARflflNlSHJ
RElD
III [TE AMP
S[LEC T
In,
I/(PUT
OUTPUT
PIN
IIHAlo.PI
ROXOOPtTS
09
~'RTlKPI
1I0XOO~EG
II
PIN
I
WTP\IT
I~8Br II g8g~ i~
n
)X80~ H 0
TlilCt
ICON~E(
00 - 1) -
--
I
TOA
PIN
PI! -Ol
16-]132 -'\7--
-a?
II
"If
If5
~~ ~}~ - ~8-63-PtI-O'-~~
l~gl?
N'T;:',lJ,)'2
NTe-'/!/3
~~'
TFl,1IX~
1915
IEN~
N-;-"V!X2
Trlk) X:3
06
~
'JTP'~IX~
II1B
IESR
06
1)
ROXO 1Pe'5
09
111
IlDXOINEG
II
g81~-
RDX02rl!'S
09
1'+
ROX02NEG
II
61f-79-- P8-0B:~~
80-95-
r :~l
1~8Ir--96-111-1
n
13
-
:~~
IfX01S-11Z-127-t -If6
~IOI~
P8-0B-Ifl
37
)5
H
23
24
NTRMIX2
TRM x,3
TRMIX4
178
IENR
TR,;:x2
NTRIJX3
~~'
06
~3'
"'TR~JIX4
158
IENIl
13
14
'~TA"'''
I
NII/ToH!? I
13
IRTlfl02
14
~'RH~P2
RDXOJ~S
09
ROXO]~EG
II
RD04 Ptrs
RDX04~G
09
II
06
3S
34
I~6~f - 2 S6 - 2 71 -
37
36
n8~f-272-297-
=~3
~J
JXO'iS
nC'ir-288-303-
-44
-45
H
'IXQ'4$-J04-JI9-
-46
4~04F
P8]-
H: ~ 1
P8-H-47 I
1~6~~ -320-]]5- PS-23:j?
TRM x2
NTPJAIX::
~51
TF\MIX~
IllS
IENR
06
13
ROxn5 P ffS
09
14
RDWSNEG
II
BSSf -336-351-1
=~3
1i~~~ -)52-367-
:~~
~ ~~~~ -358 - 38 )-08 - 2B =~~
TRMIX 2
T Rl,'I'I 3
~TF~'_!~'1
13B
IUiR
06
13
nU~>,2
14
HIRU~P2
ROXa6?~S
-
RDX05~,E
G
09
II
J84-3'l9~e-JA-'~O
)C,-r
3'i
IXDS.S
lXOf)F -
~l
n~~~-480-~15-
H
H
li~~~-416-431-
"RMI x)
TRMI'I4
12B
IENR
06
IJ
U,UI1>'2
RDX07~S
09
PI
f4'RU~P2
ROX07NEG
11
-41
j
=~~
:~~
~i&~r-412-wn-pa_}~~~~
2X~7:-46'4-479j
I~op - 448 -46] -
TRM IX 2
+
PA 3B:~~
2x07F
-42
-43
3XI17S-480-4953X07F
-4't
-45
'4xg7S
-41':
4X
n- 496 _511 _
P8-3B-47
Figure 6-19. Input/Output ar·-J Start"jFinish
Location Chart (With Logical Spnri'i-tg)_
NOTE: REFERENCE XOS OWG: 149J3 7-188
9G! 56SA. 619
6-26
XDS 901565
I N PUT
lfUTPUT
"'COUl[
MOOUlE
PIN
2~8
258
NnlDS
N71<98
HTR88
2~
NTRI08
NTR9B
NTRBS
NTR7B
NTR58
25
'-iTRS8G
"TRSR~
28
12
22
23
TlOB
NTR6B
22
TRIOB
NTR9B
NTR8S
23
24
NTR5B
TR10B
f>TR9B
NTRsa
TR7B
NTR6B
NTRsaCo
~'-iTh.~:31~
PI
12
25
28
27
-22
23
24
Nuns
27
22
23
24
1~
228
lOB
098
aBa
078
NTIl I DB
Ii TR I DB
NTR99
NTRS9
NTR76
TI<69
NTR9S
NTRBS
11178
NTR I 0
NTR9
liTR8
NTR7
NTR6
NTPIO
NTR9
NTRS
TR7
HTR6
NTR 10
NTR9
NTR8
NTR7
NTI< I 0
NTR9
NTRe
TR7
TR6
TRIOS
NTP38
-;....L~,.
i~C;~Cl
H6B
'nr;:,:~
STR59
i~5B
TRIOS
NTR9B
NTR88
TR7B
TR5B
'~~:-.::..~~-
:,~~:::;..
NH7B
':, '"~,~
H16
T P5i\(J
a
TRIO
NTR7
NTRS
"TR8
TR7
:'TR6
IH"6
NTR9
NTRS
NTII7
TR6
TRIO
NTR9
NTR8
TR I
258
2118
2J8
228
lOB
098
088
018
YOD
YOB
Y16
Y24
02
V40
Y4B
Y56
YOI
Y09
Y17
Y25
YJJ
Y41
Y4 <;1
Y57
YIB
Y26
Y]4
VII2
Y5D
Y5B
Y43
YSI
V59
V52
Y60
TR"'.~::'
TRIO
NTR9
HTR8
TR7
1116
T::;c·,.iC,
'''':.)".-.(J
~-------+--------.----------~------~.--------.+-------_1--------~------~
NTRiOB
~TR103
NTRIO
~iRIO
IoITRI08
TR96
TI198
:-ITRS8
NTil73
NTR6B
TR78
25
I~
238
TRIOS
T~9B
NTRSB
N~~88
~TT~5,B~:,
I
,
TRIOS
I ":'RT~o8~S
"
Nl~8B
NTRi8
NTRIOB
TR99
r;T;<3B
TR7S
NT~8
NTR7
~:TR8
TR?
NTRIO
TRS
NTR8
N1R7
:;~~Sc:.:
:,~5;:B,,:.
~1~6t=<
~:,R,:6H.
J~6;.
T~IOB
TRIOS
TRIO
TR98
~TR88
IR'l
~TRe
TRIO
TI(9
NTR8
Til?
NTR6
TRIO
TI(9
NTR8
r<1R7
TRS
TRIO
TR9'
06
NTR8'
~l>+'---o-~
TR7:.,/
TRIOB
TR98
IP8B
NTP7B
TRG8
TRS
NTR7
NTR6
~ . . 1h;t..,.\-.
.,..~c;:.-
TRIOB
TR98
TRBS
TRIO
TR9
TRB
NTP1
NTP6
- - -------TRi8
TR6G
NTR9
TRa
NTR7
TR6
NTR I 0
TR9
TRS
TR7
NTR6
1 ... ,c.
TRS
TR7
TR6
STRIO
TR9
IRS
TR1
TR6
T 'J~:.'
~(J
TR10
TR9
TR8
TII7
"TR6
r ~ -I
NTR10
TR9
lR8
NTR7
TR8
TRIO
TR9
H18.
NTR1
TR6
TP I a
lR9
as
TR7
TR6
~01
l~r>-+---O---f
YJI
r., ~~C
Fi~iure
NOH: IHlflHtJU XDS DWG: 149337-178
-
_.. _-----_._---- -..--.- --_._._-----------------------_._----.
6-20.
Y-';elect Location Chart
(V/itll I oqical Sparing)
.._----------_..
_------------6-2
XDS 901565
, - - - - - - - ....~.~---y---------J
I~
I Ir--~-~----=-~+-~+--~-r-~-=--=+~~-=--:j/
I I ~ -~-=
~---j
r
~--~-+-+-+---+--4
~r
I
J~-
I
I
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I
I
i--+--t--r--+--+-
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I
, I
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rrlttl~fI ~U>--~--_J I
tfrJ: I
n
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-=1
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I
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11~7
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400
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I~ I
3
0---0
2
I
I
o
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1 I I I I 1 I rl If f r I r
12 13
14 15 :7
18 19 20
TYPICAL LT 105 LOGIC
Ar
1~IS
uFUKiE
3
1HIS oc.:.~
4,
H6Ti'lLL
(;
C!.l\G8M~
~O(J,TIGr~S AT
WYICH SPNm.JG
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o
LX) 51:it 3.."', }/\ 35 Y) 37 21 22 23 24 25 26 27 28
L -), r~~ ~X~,2s, t
.'JUI,I!:J tK ::- ,:--".... ::':
43
4
012345670123456701234567
Jo LU
C
50
s
I
[:>
3~5
i I
-
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r
8
>-----'---
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:<:~t·:E ~~S ,L![
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W,f,[::O
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AfJrr.l/,prw,TE
SLOTS
x. Yt Z.
FOR
UNITS WITH LOGICAL SPA R I i'JG
sr.JLUE~~ .J'. ·\J~-'t ~~':~ 1(; ~)r\[!~) (}t~ lO.J!)(.;r~rNT ~JI[)f (SF.L PE~ DIA AB'JVE)
1IJ"~;c.fC)':':::::-- ,'\[H i, ~,(i[·:)l R AJores Selector Module,
LO(jic [)jflqram
----.-~~--
...
901565A.621
-~--~.-~.
6-28
XDS 901565
4 XO
- - - - - - - - - - - . - -..- - - 29
r-----·--·-----··---------~21
13
TR4
XI --+--+---- .. - - - - . - . - .----.--- 30
r---------------------22
f---~--~~--=:.=~---=
~3~
,..--
X2
NTR4
I
8T·12
i4
X3 --+--++--1',-+- r-
TR3
CK-I
NTR3
r--~
NMODI
~
NSPSEL
, - - - - - - . - - - - . -- -----.------ 12
r - - - - - - - - - - - - - - i 15
X4
20A
33
24
--+--++-+-1-+-+-+
TR2
11 - :! i~---=-3;~
::
NTR2
24
Ir==-~~~ ~~
I
r-----O
NSPO
p20
NSPI
L T 105
XO
47
--0
03~.----__-
__----~XO~~B-
~ ~MOD5
NSP2
XI
UIOS
22A
I
X7
.2 2A
02 : :::'4
X2
- - - - - - - - II ' 07 - - - - - - - - - - - - - - - - +
X3 - - - - - - (~6 i ,1-) - - - - - - - - - - - - - - - - - 1
X4
- - - - ~ 5 ! 4'l, - - - - - - - - - - - - - - - - - - -
X5
--------- 40
j
~
w2 -------------;
NSPSEL
I
34
Tc<7
NT R7
YMJ
II I
33 YM! --r.-
43
~"'
I
I
i I' i
2'i 'M2 -
.-
i.
I '
i.
N~:: ~~ ~~: ::o:::-~- -jill
42
NTR5
45
I
I
I
I
;
I
I
46 YM7
I
I
L TI05
23A
I
I
I
I
~fJ
--+-+---+~-+--tl_.t-~
13
TRIO
0-----
NTRIO
0---
TR3
0-
3 YLI
(,
8
YLO
6 T"': 12
CK-i
-
1o H2 - - - - I
I 0-1 ----------~--.
II i:'J - - - - - - - - . - - - - - - 4S I .14
YM2
YM3
45
YM4
40 ~''42
Yf.,~~ B
-------V------------------1
YM~
_____
O-"-3~05
02! 9~
YM6
LTI05
~JSPO
~
"JSP1
-47
--{)
NSD2
I Co:) -----.-------~
26A
_ _ _ _ _ _ ...:!~
-----------------
v' - - - - - - - - . - - - - . ,16 . ~"'" - - - - - - - - - - - - - - - j
--15: ...j 3 -----.------------j
YM7
YL0
YL 1
II I
40~~~
25A
--
______O_~~~~~O~j~------------~
I
--0
______
YL2B
.
YL2 ------.....,V-.----~~O---i
L TIOS
4
X7
Y M O - - - - - - 02
I
L TI05
24A
-------
YMI
I
YM5--~~I~---LI
47 YM6
36
I
I
I
I! III I i
:~
TR5
!
X68
3C;~'
,22A'41 . - - - . - - - - . - - - - - 1
X6
I
:~:
y L5
YL 6
O_"'~-~ >-': :. . :.': . . . . . . -__._~--_.-_~-_-_~-_=~-_~=y:L3=-8~- -j4
I I I :. 7 - ...- - - - - - - - - - - - - - - 1
4(; • q --------------~
~"~.n
YL78
YL 7 ---------t~ty~------------~---
YL3
21A
NTR ':J
TR 8
o'i...
.!.::lDYL4
12
1~-oYL5
7
2?oYL6
0--
NT f~ B
------~---
----
24 YL7
I.
t
~
.1,):-
. ~,r, 1.1 I
.'-:-, L THY> ?>~A, -l TIO,)- 29A?
L T 10:)' ,'CA_
,\:~
l TliY, .' 3 .... , L. T IOS- ?-1A, LT 10S- Z"lA)
~."Mt
A.~
LTIO~-22A.
Figure 6-22.
f,t I t f\INCf. XDS DWG:149J17 j7A
EP
ru\[) Selection Unit, Spares
Se lee t Ci rc lJ ih, Log jeD ia~Fam
----------.-~-
.. --.-
- - -..
(SII(!('j
1 of 2)
'(01 ')6:)tL.622/i
---~~---
6-29
XDS 901565
LTI05
36
5
RTi8
Nt.AOD2
~_ _ _3_9iL3A >4-1-----.
NMOD4
~_ _----'3::..::9-L::>5A>4..:...:1_---I
YSPO
LTt05
YSPI
38 YSP2
26B
NMOD&
35 YSP4
4
37
~_ _ _
39-1c' A >4-1-___1
YSP5
lTI05
YSP6
7
NXSP4
LTI05
6 YSP3
39
NMOD 8
41
>----'
YSP7
LTI05
;:>~A ,,>-4.:...:.1_--,
N MO J 3
0-0_ _ _-"3.-"-9.
NM 0 D 4
o~_ _ _~_O-!12 ,A>_42_---1
LTI05
19
-1~_~-J.lJ~!A iX ('---()
o-----L§l~·24
L-----:----":9~~~2~T RIm 3
L-----~~TRMIX4
0---
I-------{)
---4-,-=2,----,
L T105,
N MOD 5
o----~ 5{33>~
NMOD5
o _____
LT105:
GTR5B
NG T nSA
t-----{l
NGTR5B
SA >-4...=2'------1
LT105:
GT R 5A
-- --(l
NXSP3
LTI05
~.~~3.
------Q
NXSP2
L 1105.
N~~OD 8
0 ___
.45~_.__ _
NOTES:
III
ALL GATEINPUfS OF THIS ELEMENT
ARE OPEN (TRUE)
Figure
2.
REFERENCE XDS DWG: 149337-21 B
... __ ...
_----_._
...
_._._._------_.
6-22.
EP r~AD Selection Unit, Spares
Select Circuits, loqic Diagram
(Slleel
__._-----------6-30
7 of 2)
90],)6',/1.627 '2
Paragra~hs
XDS 901565
7-1 to 7-4
SECTION VII
SPECIFICA nONS AND INSTALLATION DATA
7-1
b. Multiplexing Input/Output Processor Model 8471
(Sigma 7)
SPECIFICATIONS
Specifications for the EP RAD storage unit are listed in
table 7-1. An EP RAD file consists of a maximum of eight
EP RAD storage units, one of which contains an EP RAD
controller.
c.
Four-byte MI:)P Model 8273 (Sigma 5)
d.
Four-byte MIOP Model 8473 (Sigma 7)
e. Selector Input/Output ·Processor Model 8285
(Sigma 5)
7-2
INSTAlLA nON
7-3
INSTALLATION REQUIREMENTS
f.
Selector Input/Outpu~ Processor Model 8485
(Sigma 7).
Refer to figure 7-1 for overall space requirements of an EP
RAD storage unit, including fro!1t and rear access areas for
maintenance. Refer to figures 7-2 and 7-3 for cabling requirements.
Table 7-2 summarizes cable connections between an EP
RAD controller and an lOP for various systems. The lOF
equipment may be one of the fo! lowing:
7-4
Integral lOP (Sigma 2)
h.
Integral lOP (Sigma 5)
INSTALLA nON PROCEDURE
Tile installation sequence indicated in table 7-3 may be
vS"3d for installation of an EP RAO fi Ie as a suLsystem of a
o. Multiplexing Inpui/Output Processoi' Model 8271
(Sigma 5)
Table 7-1.
g.
cvmo/ete computer installation or as an addition to a comp,:ter installation.
EP RAD Storage Unit Specifications
Characteristic
<:;pecificction
~---------------------------------------------------------+-----------------------------------------------------
Physical Characteristics
Height
63-1/2 inches
Width
29-1/2 inches
Depth
35-1/2 inches
Weight
1200lbs
Po"{er Source Requirements
208 Vac ± 10%, three-phase,
60 ± 1/2 Hz
Voltage
Current
Starting (max)
57A
Running (max)
15A
Power Requirements
3000W
EP RAD storage unit
(Continued)
7-1
XDS 901565
Table 7-1.
EP RAD Storage Unit Specifications (Cont.)
Characterist ic
Specification
Power Requirements (Cont.)
EP RAD controller
300W
EP RAD file (maximum size)
24,300#
Operational Characteristics
Disc file speed
1774 rpm
Period of revolution
33.8 ms
Period per sector
2.81 ms
Intersector gap time
100 jJs
Effective data transfer rates
Bits/second
3,070,000
Byf"es/second
354,000
Words/second
88,500
t:
Environmental Chorac~eristics
I
I
I
Ambient room temperature
Relative humidity
100C to 40°C
(500 F to 104°F)
100/0 to 9001c
I
Tabl€ 7-2. "Connections Between EP RAD CC~,;jdkr and lOP
EP RAD CONTROLLER
MODULE AND LOCATION
AT17
26C
vi
ATlO
?8C
V
AT 11
30C
V
AT12
32C
V
lOP MOOJ
,
-
!
SlOP
MIOP
ATll
9E
AT111
1D
AT12
llE
ATl2
14C
AT 11
21E
All 1
32A
All 0
14E
AnO
14B
._,,-,'
,.~~,
..
I
AT12
1e
A.T12
9F
V
AT11
3C
All 1
~
All 1
5C
ATlO
10l
,.-.--_._-
ATU
19E
A Tl1**
'L9A
AT11t
31B
ATllt
17E
AT11**
Used only for four-byte lOP interface (Models 8285/8485)
**Used only for four«byte lOP interface (Mod.3ls 8273/8473)
7-2
AT 11
9E
AT 11 *
28B
* Used only for two- or four-byte lOP interface (Models 8285/8485)
Sigma 5
Integra I 10 P
All 1
7C
vi
19C
Sigma 2
L,tegral lOP
BL
XDS 901565
Table 7-3. Installation Procedure Checkoff list
Item
Operation
Visually inspect crated equipment for obvious 5igns of damage during shipment
2
Check that each item of the Insto IIation Material List (IML) is included in the
shipment
3
Check that maintenance documents specif!ed in the IMl are included in the
shipment
4
Check that revision level of maintenance documents agrees with revision level
or equipment*
5
Check that revision level of diagnostic program documents agrees with revision
level of media
Do not tilt EP RAD storoge unit m0rp than 15 degrees from
vertical during uncrating
Note
Inspect equipment for damage during uncroting
6
7
Uncrafe equipment usi ng following tools:
a.
Claw hammer
b.
12- inch crescent wrer.ch
c.
1-1/8-inch socket wrench with H:~-inch ratchet
d.
Four meta I plates to prevent floor damage by EP RAD
storage un it feet
Locate equipment according to Installation ::Ioor Plan
Note
Do not move EP RAD storcge unit after it has
been insta lied and i5 operati ng
8
[)efore connecting power cables or control cables, check that all circuit breakers
ond switches of primary power source are off
*Revision level of maintenance documents is indicated by change letter. Revision level of modules
is indicated by change letter on mother board. Revision levEl of automated wire lists is indicated
by letter suffix of part number. Revision level of equipment is indicated on attached sticker
(Continued)
7-3
XDS 901565
Table 7-3. Installation Procedure Checkoff list (Cont.)
Operation
Item
9
Check power supplies (PT16, PT17, pn8, PT19, and PT20) for loose connections
10
Check that all power supplies have circuit breakers set to ON and MARGIN
switches set to N (normal)
11
Check power distribution boxes (PT14 and PT15) for loose connecHons
12
Check that items connected to the primary power source are distributed among
all three phases as evenly as possible
13
Check primary power source outlets for proper wiring of each phase and neutral
to ground
14
Check primary power cables for short circuits
15
Check power buses on side of each frame for short circuits and loose connections
16
Connect control cables according to Installation Cable list, noting the following
features:
i
17
a.
Port expander cables are connected t:pside down
b.
All terminated cables have 16 ohms impedance to ~round
t:.
Major assemblies of computer are locot"ed as indicated in Computer
Assemb Iy Chart
d.
Cables for add-on installations labelled end-for-end (A, B, C, •.• )1 so
that corresponding ends can be identified ofter cables ore beneatn
flooring
Check that modules of EP RAD selection units
figure 7-4
art;;
installed as indicated in
Note
Optional modules in EP RAD controller are dependent on use of one-, two-, or four-by~e interface
with lOP
18
Check that modules of EP RAD controller are ins~arled as indicated in figure 7-5
19
Connect primary power cabling according to InstCJllation Power Chart
20
Turn on circuit breakers and switches of primary power source
(Continued)
7-4
XDS 901565
Table 7-3. Installation Procedure Checkoff List (Cont.)
~------------r--------------------'--------------------------------------------------------------------
Item
21
Operation
Check that all fans are operating
Note
EP RAD storage units are checked before shipment; however, the procedure of paragraph 8-4
may be used as required during installation
22
Use turn-on procedure for each item of computp.r installation (computer, memory,
lOP, peripherals)
23
Exercise each item of installation with its diagnostic
24
Exercise systems evaluation and test program (SEVA)
XDS 901565
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2a~v.
50'&01 HZ
38
Fig u r e 7 - 2 .
EP RA D F i Ie, Cob 1i n9 D jag rom
(Sheet 1 of 2)
7-8
XDS 901565
lItOTES.
REfERENC( DRAW I NG S I
A.
INSTAllATION DRAWING, SIGMA SYSTEM POWER
IHTERCONHECTION5.- 133273
I.
INSTALLATION DRAWl":;, RAD MEMORY ~ 126657
t.
INSTALLATION DRAWING, RAD MEMORY - 1328101
II.
INSTALLATION DRAWING, RAD CONTROLLER - 135747
E.
INSTALLATION DRAWING, SINGLE BAY CABINET - 131417
f.
INSTALUTION DRAWING, DISC MEMORY - 135345
,.
PROCEDURE. INSTALLATION RAD
INTERCONNECTIONS ~ 134i 24
H.
INSTALLATION DRAWING, STORAGE UNIT-137534
"I.
J.
/
FOR CONNECTIDNS OF SIG'lAL ANO PRIORITY CABLE
OiA IN fROM THE RAO CONTROLLER TO THE lOP
INTERFACE OR DEVICE CO"TROLLER S[[,
INSTALLlTlON
DRAWING, PERIPHERAL DEVICE AND CONTROL
PMIEl· tNTERCONN[CT ION SYSTEM-137113.
120V. 50/60 HZ
311 FROM
POIER FIL TER
8.
120Y. 50/60 HZ
ROUTE INTERCO~NECT I NG SIGNAL CABLES ALONG
HINGE SIDE or fRAMES.
120Y.
SELECTION
UNIT
HAROI IRED
TO MOTClt
ROUTE STATION TO STATION INTERCONNECTING
SIGNAL OBLES ALONG CABLE TROUGHS PROV IDEO
AT TH£ TOP Of CAB I NOS.
INSTALLATION DRAWING, CONTROLL£R-137506
CONTROL UNIT
INSTALLATION DRAWlliG PT20-13!t()'J
1:.
INSTALLATION DRAWING STORAGE UNIT -149338
t.
INSTALLATION DRAWING CONTROLLER 149333
AN EP RACl FILE MA· BE EXPA'<
8
XYI
o
J.5"r-
6
in Rrior
1
yyyy
X X .xIX
. . . w "~~ 17812 "R ~ ~YJ.
........
-r
76 43 18 18 18 13 15
' '
·1
y yyy
~
8 7
J
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~.~.
,
. I' .
5 4 3
I
2
1
HnlLT I p!
17,9
11 32
1:1 .
I '
351
Ifrl
Ff
3$
l
5"4-1'
1. MODULES IN LOCATIONS A1if B26, AND A19 THROUGH A29 AR::: LOGICAL SPARING CIRCUITS
INSE~TED
2.
LTl 05 MODULES IN LOCA iIONS A22 THROUGH A29 NEED NO)" BE
SPP.RING IS REQUIRED
UNLE)S LOGICAL
3.
LTl05 MODULES MUST BE INSERTED IN LOCATIONS A22 THROUGH A25 BEFORE ANY LT105
MODULES CAN BE INSERTED IN LOCATIONS A26 THROUGH P-:29
901565A. 702
Figure 7-4. EP RAD Selection Unit, Module Location Chart
7-12
XDS 901565
U/..J
CHASSIS A
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 i 1 10 9
J
J
181
18.3
f'
AT FT FT FT FT XT IT FT FT IT LT BT FT BT IT
10 27 41 41 41 10 71 27 27 58 58 11 10 11 13
AT
12
8
7 6
5
4 3
2
1
r
ICT
BT BT IT ST iT FT
10 13 11 11 11 10
I
i
L-PET~'
CHASSIS B
32 31 30 29 28 27 L6 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
AT fT FT AT FT FT IT AT
11 27 27 11 27 27 15 24
kG'
3:2 '3.2. :>2- .:JZ-
AG r1b ;(,
:n.
:JZ- ~z.
FTFT aTIFT BT IT fT IT
FT\nIXT 2625
i5 27 il 16 27 15
2612TO
~l
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CHASSiS C
~i
11
I
I
I
I
I
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I
1FT FT IT s:rl FT IT BT FT IT
27 11 li 27 1311110 11
126
I
2
1
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II
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CD0
32 31 30 29 28 2725 25 24 23 22 2120 19 18 17 16 1514 13 12 11 10 9
LT IT XT
26 25 10
4 3
flTIDTIIFTlf.~
ITI!n
L.J
IT AT
AT L.T AT
LTIAT
12 43 11 41 10 24 1/
5
ST HTIIAT
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16 15 16 24 II 11 14 15 J4 18!12 '10
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8
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11 11 15 15 2
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L----SUBCONTROLL:::R--~
t~OTES:
1. MODULES IN LOCATIONS 11 BAND 25B THROUGH 28B MUST
BE INSERTED WHEN ~6-BlT DATA PATH OPTION IS INSTALI.ED
2. MODULES IN LOCt.TIONS 11 BAND 25B THROUGH 31 B MUST
BE INSERTED WHEN 32-SIT DATA PATH OPTION IS INSTALLED
3. PET CONNECTIQNS USED ONLY DURING OFFLINE TEST OR FOR
MONITORING ONLINE OPERATION
901565A.703
Figure 7-5. EP RAD Controller, Iv\odule location Chart
7-13/7-14
Paragraphs 8-1 to 8-5
XDS 901565
SECTION VIII
MAINTENANCE
8-1
SCOPE OF SECTION
XDS Publication No.
The EP RAD file maintenance procedures in this section are
for use following installation. However, the basic checks
and adjustments. of paragraph 8-4 can be used during installation, if required. For any operation requiring relocation
of an EP RAD storage unit, refer to section VII.
8-2
GENERAL MAINTENANCE
All assembly and maintenance documents should be avaiiable at the installation that includes the EP RAD file.
These documents should accurately reflect the change level
of the EP RAD fife.
External surfaces of the EP RAD file must Le kept clean and
dust free. Doors and panels must close completely and be
in reasonahle alignment. The tops of cabinets must remain
clear to allow free intake:: and exhaust of air.
The interiors of the EP RAD file must be kept free of wire
cuttings, dust, spare parts, tind other foreign matter. No
cl ip leads or push-on jumpers should be in I.Jse during normal
operation, and all cables must be neatly dressed by cia:r.ps
or routIng. All chassis and frames must be properly belted
down, with all hardware in place. Air filters should be
checked periodically for cleanliness and replaced if dirt-yo
8-3
Diognostic Control Program for
Sigmu 5 and Sigma 7 Computer Peripheral Device, Reference Manu(ll
900712
Si~ma 5 and 7 Relocatable DiagncsHc Program Loader, Diagnostic
Program Manual
<;00972
Sigrnn 2 Relocatable Diagnostic
Program loader, Diagnostic Program
Ivk: .. ual
901128
Sis;:na 2 High Capacity, Rapid Access
Dotri (RAD) File Test, Diagnostic
Program Manual
901538
An,! failures that cannot be isolated !Jsing the diagnostic
test programs may be isolated usin~ one or mere of the offli/1~ te~ts.
84
oc
During adjustment procedures, it wi:(
often necessary to remove a module: insert the card extender (XDS part Nc,.
117306)r and adjust components of ~Le
module. Before removing a module,. ~hut
down dc power from the PT20 power S!JPply by setting the circuit breaker to OFF.
After inserting the card extender and the
module, set the circuit breaker to O~..:.
DIAGNOSTIC TEST PROGRAMS
Diagnostic test programs shodd be run at freq~ent" iritervals
as the primary preventive maintenance method for the EP
RAD file. Programs should be run with the MARGIN switch
of the PT20 power supply set .:;t N (normal), L (low), and
H (high).
Note
8-5
Before using a diagn0stic test, check that
documentation and media are for the same
revision level.
The following documents "are required for diagnostic testing:
Title
Sigma 5 and 7 Extended Performance
Rapid Access Data (RAD) File, Program No. 704978B, Diagnostic
Program Manual
XDS Publ ication No.
901540
BASIC CHECKS AND ADJUSTMENTS
R,A [;
PRELIMINARY OPERA lIONS
a. Check that ac power is not connecte-::f to the EP
storage unit.
b. Check that all cables are installed.
7-2 and 7-3. )
(See figures
c. Inspect controller and selection unit" fc-:-Ioose wires,
bent pins, or other obvious mechanical defects.
d. At the power distribution ponel, check that the
REMOTE-OFF-ON switch is in the OFF (center) position.
8-1
Paragraphs 8-6 to 8-8
XDS 901565
e. Check that the phase relation at TB 1 of the power
distribution panel is as follows:
Note
For normal operation, the EMERGENCY
USE ONLY circuit breaker is left ON,
so that power is always applied to the
compressor. For installation or test, the
circuit breaker may be set to OFF.
e. At the motor control assembly, check that the
POWER switch is OFF, and that the circuit breaker (under
the EMERGENCY USE ONLY cover) is OFF.
8-6
POWER TEST
a.
source.
Connect the EP RAD storage unit to the ac pow'er
•
b. At the PT20 power supply, set the MARGIN s\''1itch
N (normal) and the circuit breaker to ON.
c. At the power djst~ibution pane!, set the REMOTEOFF-ON switch to ON.
Pin
A
1B-1
B
TB-2
C
TB-3
f. At the motor control os~embly, set the circuit
breaker (under EMERGENCY USE ONLY cover) to ON.
Check that the compressor starts.
g. Set POWER toggle switch tc. ON. Check that the
disc rotates clockwise.
8-7
.
Phase
ADJUSTMENT OF TIMING SIGNALS
a. While observing the oul'put at test point A of the
CTl 0 Clrc:~ Oscillator module (control !er location 2A),
adjust inductor II for peCJk ;:;1goal ampl itude.
UL
b. Adjust pulse shape potentiometer R16 for positive
pulse width of 140 ± 10 ns at pin 2A-34. (See fi21Jre 8-1. )
Note
If any of the voltages mt::asured Me not
within ±2 percent of nominal value, adjust as necE;sscry, using tI,e fe<,t point of
the selection unit as a reference. (Refer
to XDS publication No. 901157 for adjustment procedure. )
d. Check the dc voltages of the controller and the
selection unit as follows:
US
UL
Voltage
----2A-49
20B-49
+8.0
2A-51
21B-51
-8.0
2A-50
20B-50
+25.0
20B-45
-25.0
20B-41
+45.0
21B-46
1
CAUTiON
__J.
If the phase relations specified are not
correct, the magnetic surface of the
disc file and the flying heads may be
damaged.
8-2
Adjust R28 for waveshapes ns iliustmted in figure
8-2.
e. Synchronize on ~lgnal IP (pin 2B-13) and observe
signals ~p and SP (pin 2B-19). Check that there (":-e i 1 SP
pulses for each IP pulse and that waveforms are as indicated
in figure 2.-3.
Note
+4.0
L-=.:~~
d.
LJ S
Selection Un-it
Controller
i
c. Replace CT10CIock Oscillator module and remove
sector/index amplifier P35 from locat!on 1P, of tht selection unL. Connect sector/index amplifier P35 through the
card ext-s:n...!a.
H there are not 11 SP pulses for each IP
pulse, as indicated, the timing track
must be re-recorded, as described in JTl8
Operating Procedure, XDS Drawing No.
134293.
Gr :B'-t~)
f.
8-8
Replace sector/index amplifier P35.
POWER FAIL-SAFE TEST
a. I\emove WT29 Power Monitor
unit location 4B.
r.;~dule
from s81ection
Note
If adjustment potentiometers of WT29
module have been sea led, sk ip to step
I. If potentiometers hove not been
sealed, proceed with step b.
US
XDS 901565
r-TJ--lI
CLK3MH _______
(2A-34)
1.
1____-
....._ _ _..J
___1
1........
..----T2 ------~
NOTES:
1. ITEMS IN PARENTHESES It'>lDlCATE LOCATION IN THE EP RAD CONTROLLER
(MODULE - PIN NUMBER)
2. T1 IS 140 ± 10 N S
3. T2 IS 324 TO 336 NS
901565.4.813
Figure 8-1. Signal CLK3MH, Timing Diagram
us
SECT
(1 B-30)
.~
11
f...-
--J
12
~
A. SECTOR PULSE
US
SECT
(1 B-30)
-.r-...J
-,I.
T3
I
r~
~
~
k
!
T2
J...e...
-..J
T2
~ \~
f...-
B. IN[>EX PULSE
NOTES:
1. ITEM:; IN PAKcNTHESES H<:'JlCATE LOCATION IN THE EP RAD SELECTION UNIT
(MODULE - PIN NUMBER)
2. T! IS ~OO TO 750 NS
:i .. T? IS 500 TO ~j,lO NS
L~~'3 ~~
9.5
~S
N\.\XlMUM
_ _ _ _ _ _ __
Figuie 8-2.
J
Signal SECT.. Timing Diagram
b. Connact the WT29 Power Monitor module through
cord extender.
c.
Connect a clip leod from pin 4B-44 to pin 4B-45.
d.
At the power distribution panel, remove fuse Fl.
e. On the WT29 modu!~, adjust R15 untilsignalAOK
(pin 4B-26) just reaches O. av. (Normal voltage is +8.0
±1.0V.)
f.
Remove the clip leod installed in step b and replace fuse Fl (removed 1n step c).
g. Remove the WT29 mmule (wiih ca-rd extender from
location 4B) and ploce in location 58.
h.
901565".612
Check that output at pin 26 is normal (+8.0 ± 1. 9V).
i. Adjust R5 counterclockwise until output level falls
to OV; then adjust R5 siov,r1y clockwise until output level
returns to normal range and remaim there.
j.
Adjust Rll as described in step i for P5.
k.
Adjust R19 as described in step i fer R5.
I.
Replace the WT29 module in location 4B.
m.
Check that signal NPDL Y (selection unit location
1JA-l4.) is at +4V.
n. Temporarily connect selection unit pin 10A-31 to
ground. Check that signal NPDL Y falls to OV,
Note
If 10--second delay is not ottained after
removal of ground connection in step 0,
adiust Rl0 on 0T15 10-Second One-Shot
module (selection ur.it location 68). Use
card extender during adjustment.
8-3
Pnragraph 8-9
XDS 901565
~
--J
SP
Jet.
lIL
lJS- I
~S
r--l
II--~
I
l- (2B-19}:J
.)'fi: .26 t) rJI
2.2 TO 3.0
I
~ 2. 78 TO 2.91
,.'I1S--/
1--
G
'f\
~
A. SECTOR PULSE
rc-
---I
2.2 TO 3. 0 ~S
~C('(/'/I,'·r1JB-l~~-L
-/
I
LJL I? f?
~ ,
~-- 33. 4 TO 35.4 MS---I
2{ tJOh
,:5 G
,.-
iL
r
I
1-----1
B. INDEX PULSE
- - - - - - 3 3 . 4 TO 35.4 MS -------------Bi1A=r=---41
IIl'ilf
IPR
(2B-13)
I
I
_L--_
~;:-] 9} _ _--:.I__~____'Il_-_.L..-~
_
-,~
_'__ _ _ _ _ < __
_'_____'__~~_
~
2.78 TO 2.91 MS
C. RELATION OF INDEX PULSE AND SECTOR PULSE
NOTE:
ITEMS IN PARENTHESES INDIC'\T~ LOCATlOi4 IN THE EP RAD SELECTION UNIT (MODUlE-PH--i NUMBER)
Figl.Jre 8-3.
Signals SP r.nd IP, Timing Diagram
o. Remove ground connected in step r.. Check that
NPDLY remains at OV level for at lemt 10 seconds fol !')wing removal of ground connection.
I
ADJUSTMENT OF AT41 WRITE t:LOCK DRIVER
a. At tlte power distribution panel, cher~ that the
REMOTE-OFF-ON switch is OFF (renter).
b.
Insert PET connectvr P181 in controller lecation
32A.
c.
Insert PET connector P183 in controller location
30A.
d. Check that all modules are inserted in controller
'(figure 7...;5) and in selection unit (f:gure 7-4).
e. Place the PET panel oveclay (figure 8-4) over the
_,_ PET control panel.
.<:s
8-4
90]5.','<;A,811
f.
Set the PET panel ADDRESS $v.'itches fo the adof the EP RAD storage unit under test.
g. l·t ~he controller, place online/offline sV>/ltch of
LT25 Spec :ClI rt:rpose Logic module (location 23C) in the 0
position (doym). (See figure 2-2. )
h. J..~ PET, place PET/MONITOR switch to :E!- place
three switch~s marked with arrows to position indicated by
arrowhead, and place all other switches in down po:;ition.
i.
Apply power to PET.
j.
A?ply power to the controller and selection unit.
k. s~~ the following switches in the up pos1Ijoi1:
ORDER 1/ :'IO, REPEAT/ and COUNTER RESET sit/itches
1, 2, 4, 8, ~6, and 32.
I.
m.
button.
Press and release the RESET pushbutton.
Press and release the COUNTER INITIALIZ::: push-
n. Press and release the FS pushbutton. Not~ thai'
the WRITE lamp is lighted, and that the TRACK lamps incre-'
ment from TRACK lamp 10 lighted (000 0000 000l) to TRAe K
lamp 5 lighl'ed (000 0010 0000), and repeat.
Paragraph 8 -10
XDS 901565
u. Adjust R43 to place the fa II ing edge of signa I MC6
within 130 to 140 ns from falling edge of signal NSC2R, as
indicated in figure 8-5.
Remove dc power before removing modules.
UL
v. If any jitter is observed on signal MC6, readjust
L4 a maximum of 1/8 turn in either direction tv remove
jitter.
"---. o. At controller, remove BTll Buffered AND Gate
module from location 7A.
p. Connect a clip lead from ground to signal REND
(pin 7A-l).
w. Recheck the sine wave at pin 18A-2 to check that
the amplitude has not decreased.
q. Connect CI clip lead from signal RWCK-3 (pin 2A10) to signal SC2D (pin 7A-35).
x.
Remove clip leads installed in steps p and q.
y.
Replace AT41 module in location 18A.
z.
Disconnect PET.
r. At selection unit, remove AT 41 Write Clock
Driver module from location 'InA and connect through card
extender.
s.
Synchronize on, andd;splay, signaINSC2R(18A-27}.
t.
Alternately adjust L4 and L6 for maximum sinusoidal amplitude at pin 18A-2.
8-10
DATA PATH TIMING ADJUSTMENT
a. At the power distribution panel, check that the
REMOTE-OFf-ON switch is OFF (center).
Note
For iitter test/trigger the oscilloscope on
tht:> fal Hng edge of s;!:~nal MC6 (pin 18A8). Adjust fall ing erlge of signal MC6 for
thinnesi trcce possible. Use .the expanded
scale tu check the next two falling edges
for jitter. Any jitter ~m these edges wi Ir
seriously reduce the r.;v-.;;;-all timing mar£)in
of the system.
.
~.
Insert PET connector P181 in controller lecation
c.
Insert PET connector P183 in controller location
32A.
30A.
d. Check thClt all modules ar~ inserted if'l contro! ler
(figule 7-5) and in selection unit (figure 7-4).
------------------------------------------_.--SINGi..E INO. ERRO~ ALTEr ..., .--ORDER--,
4
UP !:iTOP ORDE.H~ _.,
2
I
C'
1'10
(----
C)
./\
('!
1024
512
25'-
128
64
J2
IS
H
\0
qo
.~
?
6,
8
r
ADDRESS
a
.,
'"
2
Z'
4
'1
I
0
'I
-,
DATA
0
3
hm-mi IlblY'meter
I
g. At the controller, place the online/offline switch
on the l T25 Special Purpose L08ic module (location 23C) in
the 0 position (down). (See figure 2-2. )
h. At PEt place the PET/MONITOR switch to PET,
place the three switches marked with arrows to the position
indicated by the arrow, and place all other switches in the
down position.
i.
Apply power to the PET.
;.
Apply power to the controller and selection unit.
Tektronix
Model 630A
k.
8-13
f. Set the PET panel AODRESS switches to the address
of the EP RAD storage unit under test.
iektrcn:x
Model lA 1
d. Check that all modlJes are inserted in the controller (figure 7-5) and in the sciectlon unit (figure 7-4).
e. Place the PET panel ("'erlay (figure 8-4) over the
PET control panel.
I
M::>del 543
XDS
_
Triplett
I
Perform testing as requited.
SII'~GlE
PHASE SEQUENCES
kS
a..
0,
Perform the preliminary operations described ira
paragraph 8-12, unless previously done. ChAck that
switches arc in positions noted in steps e throu9h h of paragraph 8-12.
b.
Place the HIO !>witch and the SINGLt: PHASE
switch ii1 the ·up position.
c.
Press and release the RESET pushbuttcr..
the PHFS lamp is lighted.
Note that
d.
Press and re Iease the FS pushbutton. Note that
the PHFS lamp goes off and that the PHFSZ lamp is lighted.
e. Press and release the PHASE STEP pushbutton.
Note that the PHFSZ lamp goes off and that the PHFSL lamp
is lighted.
8-9
XDS 901565
·agraphs 8-14 to 8-15
f.
Press and release the PHASE STEP pushbutton again.
Note that the PHFSL lamp goes off, and that the PHFS lamp
is lighted.
12
PHRSA
13
PHRS
h.
Place the TOV switch in the up position.
14
PHTO
i.
Repeat steps c through f.
15
PHFS, UNE
j.
Place the TOV switch in the down position.
14
F
!;"
k.
Piece the TIO switch in thG up position.
I.
Repeat steps c through f.
m.
Perform additional testing as required.
Perform additional testing as required.
Relation between DATA switch settings
and bytes of seek order is as indicated
in table 8-3 .
~GAL.<:£ERwS~~E:'J~£..
Table 8-3.
Note that
d. Pre$~ and i~leosp. the FS ':''Jshbui'ton. Note that the
PHFS lamp soes off and that the PH~SZ lamp is lighted.
e. Press and release the PHf 'E STE P pushbuttl"n for
ea:h step or the fol hv:!ng sequer,,,;(;:
2!ep
.!..amps Li~!-:j-ed
Remarks
PHFSl
2
(VlL.) ~ '3&2 ....
PHFSZ
4
PHFSL
5
PHRSA
6
PHRS
7
P~TO
8
~C:t'
:J,C'3't
PHFS, DATA, IN
9
PHFSZ, UNE
PHFSL
11
PHRS
0
TOF (track overflow bit)*
T07 .... 'S Ft
1
(not used)* TOO -1qR .3
T03
/lgA
2
(not
T09
A8~
3
102 A'1 t'rz ....
no
AS~
4
T03
A&f ~.-'1 Lt
SOJ~
A8~
5
T04
AetA4Z.
SOlt 1'l8fl
6
T05
..,qA.-1T
sr,,....
\.IL
A6.fi
7
T06 /1~A2..b
503
4~~
used):~
T01 A"A "a 6
tIf SDO and SOl are both true, a sector unavaik:Lie
error occurs
_ _ _-----.J
26A '1.:l{VL)
3
10
BYt~~
Byte 0
.u. A 2,,"'5
*Jf. 1 OF, TOO, or T01 true, a sector unavaiiaLie
er:-or occurs
Dva
PHFS, DeB,
Data In Bytes of Seek Order
DAiA Switch
b. Piece the S10 switch and the SINGLE PHASE
switch in the lip position.
c.
Pr8ss and release the RESE r pushbutton.
the PHFS lamp is lighted.
Order in service cycle.
IN lomp goes off
Note
a.
Perform the preliminary operations described in
paragraph 8-12, unless previously done. Check that switches
are in pozitions noted in steps e through h of paragraph 8-12.
A successful SIO sets DCB.
OrdN out service cycle
8-15 SINg,~;..::.,~,~Z!:,,~ (
b.3) 4JtCa
a.
Perform the preliminary operations described in
paragrnph 8-12 un less previo!.Jsly done. Check thcT switches
are in p0;;itions noted in steps e through h of paru9raph 812.
b. Set the following switches in the up podtiori:
SINGLE PHASE, ORDER~-·ORDER.~r-SIO, PET •
DQ~o in service cycle.
Data lamp off. I1lega I
order sets UNE
(UL)A~C.~f
8-10
}
Place the HIO switch in the down position.
r::c,,-....-e-1-'--
Remarks
Data in service cycle.
Data lamp off. Illegal
order sets UNE
g.
f.
•
~amps lighted
Step
. c.
sition.
5'csa
Set DATA
switc~es 3 throu~ 7
to the center po-
d.
Press and release the RESET pushbutlon.
the PHFS lamp is lighted.
Nole that
XDS 901565
UL
e. Press and release the FS pushbutton. Note that
PHFS lamp goes off and that the PHFSZ lamp is lighted.
",,,';3C 38the
)
f. Press and release the PHASE STEP pushbutton for
each step of the following sequence.
lamps lighted
PHFSl
Remarks
}
Paragraph 8-16
Step
Remarks
lamps lighted
3
PHFSl
4
PHRS
5
PHRSA
6
PHRS
7
PHTO
8
PHFS
DA TA lamp goes off.
Order in service cycle
SIO accepted
S-~·9
2
PH~S, DCB,
$c"!f
3
PHFSZ
3CAr
4
PI-:FSl
.2C3e
5
PHRSA
J.C236
,!
o. Repeat steps d through f.
d;fferent byte is stor~d •
PHRS
7
PHTO
S-C9
8
PHFS, DATA
l,3 c 3>'8'
9
PHFSZ
A7 10
PHFSL
,2.(':38 11
PHRSA
2£23
12
lc 3~ '13
Q.
Byte one of seek order
o. Perform the prelimir;ory oiJarations .:.~escribed in
paragraph 8-12, unless previously done. Check that
s\vitches are in positions note(1 in sleps e through h of paragraph 8-12.
'~
PHRSA
·f
?
~. ~l
Notc
-
h. Set- DATA switches 0 through 4, 6, and 7 to the
center position, ond set DATA switch/5~to the down position.
.2...
i.
Place the IND. UP switch to the down position.
j.
Press anr] release the PHASE STEP pushbutton.
Note that the PHRSA lamp goes off Clnd the PHRS lamp is
lighted.
b. Sd the fo! I,'wing switches in the up i ositions:
SIt-JGLE PHASE, OR~)ER4; SIO, and PET.
/2
"". Press and rel.case the RESET pushbutto:l.
the PHFS lamp is lighted •
I. Place the IND. UP ~\lVitch to the up position. Note
that all TRACK lamps are lighted.
-1"
.:J ""ef" hi "?
~.
Press and release the RESET pushbutton.
b. Set the following switches in the up position:
ORDER 1, ORDER 2, 510, unJ REPEAT.
c.
Note
Press and release 1he RESET pushbutton.
During step d, the controller cycle5 continuousl y through the phases I isted it!
paragraph 8-15. All lamps listed wiil be
lighted briefly and will appear to be dimly
Iit.
Note
During step d, the controller cycles continuously through the ?hases ir..:licated in
paragraph 8-15. A!llomps listed will be
lighkd briefly and will appear to be dimly
lit.
d. Pre:;s and release the ;'$ pushbutton.
the DCB lamp is lighted.
d. Press and release the FS pushbutton.
the DeS 1amp is lighted.
Note that
e. Set the REPEAT switch to the down pcsition.
that the PHFS lamp is lighted.
f.
e. Set the REPEAT switch to the down position.
that the PHFS I amp is lighted.
f.
Set the IND. UP switch to the up position.
g. Select track 12, sector 3, by setting DATA
S'Nitches 0 through 7 to positions 1100 0011 (table 8-3).
h.
Set the ORDER 2 switch to the down position.
Note that
Note
Set the ORDER 2 switch to the down position.
·"'''1
Note
.;:"
g.
Set the REPEAT switch to the up position.
h, Set DATA switches 1, 3, 5, and 7 to the center
position.
i.
j.
button.
Press and release the RESET pushbutton.
Press and release the COUNTER INITIALIZE push-
8-17
co
I
co
TIME IN NS
o
(1 B-5)
(4B-15)
Os. 01'~
300
400
~~~'----.------------~~
CYClE/C
DCl
200
100
~---------
,Wj
J
TC 5000-1 " "
r:0j'7t'----,0'7W/A~
(lB-27)
~
~
."
TCSOOO~2 ~
--------.----~-
~------------------------
(22C-44)
1(5000-3
(lB-28)
~
NTCSOOO
(22C-21) ,
NTCS080
(18-29 )
~~---------------------------
~-------------------------~-NTCS180
(21 A-36)
TC5300
08-31)
~
-----------------------------~
NOTES:
1. 'THE ITEMS IN PARENTHESES INDICATE MODULE 'LOCATION AND PIN NUMBER
2. ALL SIGNALS ORIGrNATE IN THE EP RAD CONTROlltR
3. SIGNAL TCS1 00-3 IS IDENTICAL TO SIGNAL TCS100-2, AND CAN BE TESTED AT (2C-47)
-0
0
u;
0-
(.n
"!>
co
0
co
4. SHADED
~,~EAS REFRr:SE~H
R.\,NGE CF FJSr: 'j liVE OR
l:i~U
TV:\E:
0
100
CYCLER
10/80 t (1 B-4)
SWRITE
dBci(10B-2)
05B 1 NTRSOOO
o (21 A-6)
TRS030
'"T1
.,C
~
~
.-f
~
r-
0
CD
Q
'<
c:
[t'.sS
NTRS030
(22C-50)
TRS060
rS.Bo6 (22C-4)
:;,
C'P
VI
<.0'
::I
0
~
-f
of)C3o NTRS090
. (1 B-33)
&f.. (18-41)
TRS130
~
~r
m------- ;.
0~ r-
..;.0'y
~~'"'ij
~.J'
0
Jfa
3
0~
w~
~~~~~----------------------------------------------
--1,0
r-II
.
~
-------~.~~
r77:1~~"'-
~.-i~®
0-1
0~
t---
~
~~--~---~
------~-~--. ~~--------
TRS180
;:J
co
~
osBot,- (1 B-33)
bS&oS-
TRS270
(22C -7)
--------------------~~
TRS300
. OS.81
r (l B-44) -----------~~.
NOTES:
1. THE ITEMS IN PARENTHESES INDICATE MODULE LOCATION AND PIN NUMBER
2. SHApED AREAS REPRr.SENT THE RA~G: OF R::SE TIME OR f,AlL TIME
3
IJl
0-
~
400
~
CD
co
300
-~~------------------------------
J
~
58.2' (22C-47) ------~~
co
TIME IN NS
200
3. ALL SIGNALS ORGINATE IN THE t:P RAD CONTROLLER
4. NTRS030 FALL TIME RANGE CORRESPONDS TO TRS030 RISE TIME RANGE PLUS DELAY
5. NTRS030 RISE TIME RAijN A;
t::.
Set the ERROR STOP swHch in the up position, unless reset at error detection is desired.
i.
Press and release the RESET pushbutton.
j.
Press and release the COUNTER INITIALIZE push-
I
"1-,
m.
Set the ORDER 2 switch to the up position.
n.
Set the REPEAT switch to the up position.
G. Set the DATA switches to the eight-bit pattern
selected for writing.
Co
the
o.
Repeat steps c through e.
<'~
p.
Set the ORDER
,2 switch
/jI.".
to the down position.
q.
Set the ORDERA s\.vitch to the up position.
r.
Set the REPEAT swirch to the up position.
track into w!. ich data is to be written.
f.
Press and release the RESET pushbutton.
9.
Press and release the COUNTER INITIALIZE push-
buttnn.
Note
s.
Repeat steps i through k. The CHECKWRITE lamp
is I ighted, the TRACK lamps increment, and no error lamps
are lighted.
::J.I'Jj) .
+
Set the COUNTER RESET switches to Thl-) n:..lmber of
r. ;ghest
rJ?
Following step hi a write order Vliil be executed (WRITE lamp I ighted) and the partern
8-21
~09rophS 8-29 to 8-34
XDS 901565
established in step d wi" be written in track
O. After the write order is executed, a
checkwrite order will be executed (CHECKWRITE lamp lighted). If the ERROR STOP
switch is up, detection of eriOrs will cause
reset of the track register and automatic rewriting of data on the disc. If the ERROR
STOP switch is down, the track register will
be reset at the track address established in
step d, and the operation will repeat from
track O.
8-31 SIGMA 5 OR SIGMA 7 MACHINE LANGUAGE TEST
PROGRAM
Table 8-5 defines a simple mach ine language program that
can be used for basic troubleshooting of the EP RAD controller. When run, the program causes a continual start of
on input/output operation (SIO), followed by a halt of the
input/output operation (HIO) after a controlled delay. Signals of the EP RAD controller may be read continual:y as
the progr'J:l1 repeats.
8-32 SIGMA 2 MACHINE LANGUAGE TEST PROGRAM
h.
Press and release the FS pushbutton.
i.
Perform additional tesling as requi red.
8iZat~;~~!~!,5~~~~"~~J'~!9,~~' ,~~_~ GLE<,:~.~~>~~~:~,,~;
~~'
a. Perform the prel ir.linary operal'ions described in
paragraph 8·-12, unless previously done. Check that
switches are in posit ions noted in steps.; through h of paragraph 8-12.
b. Set the COUNTER RESET switches to the trock
number to be tesfed.
c. Set the following switches in the up position:
ORDER 1, SIO, REPEAT, and Ii"-lD. UP.
d.
button.
e.
Press and release the RESET pushbutton.
i.
Set the following switches in the ur position:
ORDER 4, ERROR STOP, ALTERN. ORDERS, and SINGLE
TRACK.
Note
Do not press RESET pushbuaon.
i.
Press the FS pushbutton. Note that the WRITE
lamp and the CHECKWRITE lamp are lighted cnd that the
TRACK lamps do not increment.
Perform additional testing as requi red.
:8-30 CPU MODE TESTS
•
The following machine language programs can be used to
!he EP RAD file.
8-22
~-~:;r-'(. T()(i,o''\'leJer Gu.fPUT Vct,T»-&~ TE~T 1'l~~'a~nrYl (ih~e &-22~
8-34 REPLACEMENT OF THE DRIVE MOTOR STA fOR
Replace the r/rive motor stator as follows:
f: C~UTlON
]
Study the enti re procedure before attempt:cf: replacement. Do not loosen any bolls
or screws on the RAD bulkhead because
th.s "vi" cause severe damage to the disc
file.
Set the DATA switches to any eight-bit pattern.
h. Set all COUNTER RESET switches to the down
position.
k.
8-33 REPAIRS, REPLACEMENTS, AND ADJUSTMff'lTS
Press and release the COUNTER INITIALIZE push-
f.
Pre~s and release the FS pushbutton.
t'Jote that
the operatior, halts with ;he track nur,lber selected in step
b displayed on the TRACK lamps.
g.
Tcble 8-6 defines a simple machine language program that
can be used for basic troubleshooting of the EP RAD f!le.
When run, the program seeks sector 0, track 0, writes 360
bytes, then seeks sector 0, track 0 again and checkwrites
360 byte:;. The starting address is 0100 (hexadeciMal). The
instructions used are described in table 8-7. For more detailed infunnation, refer to XDS publication No. 900964.
The progroF.' of table 8-6 wi II be run once. To calIse continual rec~/cling, change the contents of the last audres~ as
indicated.
a. Af Ihe motor control assembly, set the PUWER
switch 10 OrF.
b. I.fier the disc has come to a complete halt, set
the cirCUit breaker under the EMERGEt'-1CY USE Of'-JL Y
cover 1'0 OFF.
c.
flul! the bulkhead assembl y fOrNard and drop the
front legs clown to support the extended bulkhead aS5embly
(figure 7- i).
d.
Loosen and remove the four Alien screws that secure the brake and tachometer assembly to the end of the
motor housing (see section IX). Remove the broke and tachometer os:c:T,bly from the motor housing, leaving th('
stator wires attached.
e.
Loosen and remove the four Allen screws that secure the stator to the motor housing'ond the motor housing
to the spindle housing. Remove the motor housin~1 and stator from the spindle housing with the brake and spindle
PDQ NO.
70-054
PUBLICATION NO.
901565A-l
PagE; __2_ of ___
2 __
--.
(
INSTRUCTIONS (Cont.)
!
8-32A TACHOMETER OUTPUT VOLTAGE TEST PROCEDURE
The tachometer generates an output of seven volts per 1000 rpm. The normal output at RAD
operating speed is approximately 12 vdc and should not drop belC'w 10 vdc. Voltages lower
than 10 vdc can causE' problems during stcrt·,·up. Noise spikes greater than 10 vdc can cause
data errors.
The tachometer output voltage should be checked on c monthly basis as follows:
a.
Connect t~le oscilloscope ~round probe to the 'Nhit; wir~on the f'achometer and
....
the signal probe to the blue wire on the tach;)meter.
-
b.
-
ftt RAD operating speed any tachometer with an output of less than 10 vdc or ""ith
noise spikes greater than 10 vdc should be replaced. There wi II be some ripple,
which is :le-rmal. If there is no output, inspect the tachometer shaft coupling for
possible fai lure.
Duri ng the replacement of a tachometer, use care when re:noving the three No.2 screws (XC'S part No. 123054-104)
;'hat attach the adapter plate to the tachometer. These screw
heads can be easily dama8ed due to the torque required to
cvercome the Loctite applied to their threads. The applicLltion
of Loctite has now been discontinued, therefore it ~hould not be
lIsed when installing the adapter phte on a new tachometer.
(See figure 9-5 for assembly drawing).
8-??l\
XDS 901565
Table 8-5.
Memory Location*
EP RAD File Program for Continuous Test (Sigma 5 or Sigma 7)
Remarks
Contents*
Load immediate (LI). The value 0000 0100, which
. is the address of the first half of the command doubleword, is stored in general register O. (For doubleword
address i ng, 0200 is addressed as 01 00)
0008
2200 0100
0009
2220 XXXX
Load immediate (LI). The value 0000 XXXX, which
controls the number of count~ in the delay introduced
by the BDR instruction, is stored in general register
2. (A typicol value for XXXX is 0200)
OOOA
4COO Oyyy
Start input/output operation (510).
must address theEP RAD controller
OOOS
6420 OOOB
Branch on decrementing register (BDR). The value in
general register 2 is reduced by one. If the value ;s
then positive, the BDR instruction is repeated (loca ..
tion OOOB). When the value is zero, the instructic;-,
in location DOOe is executed
DO DC
4FOO OYYY
Halt input/output operation (HIG). The operation
started by :he instruction in lecation OOOA is halted
OOOD
6800 0009
Branch on conditions reset (BCR). The logical pror.h; ...;t
of the R-field of this insl·ruction (0) and the condith.. n
code, whkh is alwo)'s zero, causes the instruction :~
memory locaticn 0009 tc be execute.d
I
0200
!
I,
OOXM MMMM
First half of command doubleword. Character X has
no significance. Characters M MMMM repre~ent t:~e
memory b)'~e address at which the SIO instruction wi!!
start processing information. Characters 00 represE:.,t
one of six EP RAD file order codes, as follows:
Code
,
0201
I
1
The value YYY
FFXX BBBB
)
I
_
I
* Memory location and contents are in
Order
X'Ol'
Write
X;02'
Read record
X'12'
Read sector
X'03'
Sense
X'04'
Seek
X'OS'
Checkwrite
Second half of command doubleword. Characters XX
have no significance. Characlers BBBB represent the
byte count (number of bytes to be written, read, or
checked by write order, read order, or checkwrite order).
Characters rF represent flag codes, but may be set to 00
for this test. (Refer to XDS publication No. 900950 and
900959 for flag codes in normal operatio~l)
hexade~in:al notation
j
I
~-------------------------------------------------------------------------------------------------..-
8··23
XDS 901565
Table 8-6.
Contents*
Memory Location*
!
Mnemonic
Remarks
0000
400A
B
Branch to first instruction
0001
0003
WD
Order byte for seek
0002
0001
WD
Order byte for write
0003
0005
WD
Order byte for checkwrite
0004
0169
WD
Byte count for write and checkwrite
0005
0003
WD
Byte count for seek
0006
OOFD
WD
Starting add;-ess for seek
0007
OOFF
WD
Starting address for write and checkwrite
0008
0000
WD
Track to secror
0009
0090
WD
RAD devic~ numb~r (90)
OOOA
8006
LOA
Load seek starting address
OOOB
OOOA
WD
Load starting address in
8005
LDA
Load seek byte count
OOOD
0008
WD
Store byte .::ount in
CODE
8001
LDA
OOOF
EOFLJ
STA
Store order byte in table
0010
8009
LDA
Load RAD device number
Ot)11
1041
RD
Start seek operation (SIO)
0012
1042
RD
Test for comparison (TIO)
0013
6202
BNC
Branch if complete (address +2)
0014
49FE
B
Branch back if not complete (address -2)
0015
8007
LDA
Load write ;;tarting address
0016
OOOA
WD
Load starti.'g address in
0017
8004
LDA
load byte c')unt
0018
OOOB
WD
Store byte C0u~t in
0019
8002
LDA
load write crder byte
001 A
EOFF
STA
Store order byte in
OOOC
•
Sigma 2 Machine Language Test Program for EP RAD File
I
I
Va
Va
register A
register B
Load order byte for seek
Va
I/o
Va
lIa
for starting address
register A
register B
table starting address
f--
• * Memory locations and contents are in hexadecimal nototion
8-24
.J
(Continued)
XDS 901565
Table 8-6.
Memory Location*
Sigma 2 Machine Language Test Program for EP RAD File (Cont.)
Contents*
Mnemonic
001S
8009
LDA
Load RAD device number
ODIC
1041
RD
Start write (510)
0010
1042
RO
Te5~
DOlE
6202
BNC
Branch if complete (address +2)
OOlF
49FE
B
Branch back if nof" complete (address -2)
0020
8007
LOA
load starting address foi' checkwrite
0921
OOOA
WD
Store starting address in
0022
8004
LOA
Loao byte count
0023
0008
WD
Store byte count in
0024
8003
LOA
Load order byte for checkwrite
0025
EOFF
STA
Store order byte in table I/O starting address
0026
8009
LOA
load RA, D device number
0027
1041
RO
Start c.heckwrite (SIO)
0028
1042
RD
Te!>· for comparison (TIO)
6202
BNC
Brar..::h if checkwrite complete (acidress +2)
49FE
B
BrC'-:(;;~
OODO
WO
End
0029
I
002A
002Bt
-.
I
I
Remarks
for comparison (TIO)
~f
Va
Va
register A
register
back if checkwrite not complete (addre::.s -::)
pr:>gram
-
* Memory locations ar,c! contents are in Lexadecimal notation
t To cause the program to recycle continually, change the contents of memory location 002B to 400A.
This commands a bran~h to the first instruction as in memory lc::,tion 0000
Tobie 8-7.
"-
Instructions Used in Sigma 2 Test Program
Mnemonic
Operation
~----------------------------------~------~--------------------------------------------------~
BRANCH. Tht.:: effective address is loeded into the prog~am
B
address regi~f.E:r (general register 1). The next instruction is
accessed from the location pointed to by the effective address of the brunch i:Jstruction
BNC
BRANCH IF !'JO CARRY. The branch condition is true only
if the carry indicator is reset (0)
LDA
LOAD ACCUA~ULATOR. The effective word is loaded into
the accumulator (general register 7)
RD
READ DIRECT. The contents of the effective location are
interpreted by mode (bits a through 3) and function (bits 4
through 15) for read direct operations
(Continued)
8--25
· Paragraph 8-35
XDS 901565
Table 8-7.
Instructions Used in Sigma 2 Test Program (Cont.)
Mnemonic
Operation
STA
STORE ACCUMULATOR. The contents of the accumulator
(general register 7) are stored into the effective location
WD
WRITE DIRECT. The contents of the effective location are
interpreted by mode (bits 0 through 3) and function (bits 4
through 15) for write direct operations
attached. This removal may require some effort as the end
of the motor housing is tightly fitted into a lip in the spindle housing.
f.
Position the stator and motor housing on the spindle housing sO that the four mounting holes in the stator
are aligned v,/ith the four tapped holes in the spindle hous• g. Install and tighten the four A lien screws that were
noved in step e.
•
g. Loosen and remove the three Allen screws that
secure the tachometer to the brak~ and tachometer assembly. Remove the tachometer from the assembl y.
h. Mount the brake and tc;c.hcmeter assembl y on the
end of the motor housing. Insta II and tighten the four
Allen screws that were removed in step d.
Note
Make sure that the fork
is properly inserted.
("'·il
the tachometer
i.
Mount the tachometer on the brake and tachometer
assembly by first ins'3rting the tach )meter shaft into the
shaft cvupier and then aligning the. three holes in the tachometer base with the three tappt_-:I holes in the brake and
hometer assembly. Install and tighten the three Allen
(CWS that were removed in step g.
e
j. Push the bulkhead assernuiy back into the RAD
storage unit and raise the front leg.>.
Note
If the RAD storage unit Clborts folloVJi ng the
turn-on procedure of steps k and I, check
the coupling between ti,(=! tachometer and
the coupltng shaft.
b. Set the circuit breaker (under the EMERGE NCY
USE ONLY cover) to OFF.
c. Disco~mect the EP RAD fife from the 208V threephase source.
Use the feet at the base of the disc fi Ie to
support the file when it is in the extended
position (figure 7-1). Place plates on thE"
floor to protect the floor from the feet I if
pecessary.
d.
Pull the disc file forward, and set the adjustable
feet on the floor.
e. Remove relay K7 to prevent the cpplicatioll of
power il') the disc file motor.
f.
Cormeet a jumper from the +4V connectio'"l on the
select;')!', unit (E2, E4, or E6) to terminal board TB 1-E4.
1.=::1
DO NOT REACH INTO THE MOTOR
CONTROL ASSEMBLY AFTER POWER
HAS BEEN CONNECTED.
g. Connect the EP RAD fi Ie to the 208V three-phase
powers..:;;,:rcc.
A~
h. At the motor control assembly, set the circuit
breaker to ON.
I.
Set the POWER switch to ON.
i.
Set switch S 1 to ON.
brake retracts.
8-35 ADJUSTMENT OF THE DISC FILE BRAKE
a.
~F.
8-26
Wait until the disc has stopped before
proceeding.
k.
the motor control assembly, set the circuit
breaker under th~ EMERGENCY USE OhJ l Y cover to ON.
~
Note
At the motor control assembly, set ~witch Sl to
Note that the disc fi Ie
j. Measure the gap between the armature and friction brake at all four cutouts in the brake collar. The gap
should be 0.010 in. to 0.015 in. Adjust the gap as described in stePf k and I.
XDS 901565
k.
Paragraphs 8-36 to 8-37
e.
loosen each of four slot-head screws two turns.
Measure and adjust the gap as described in steps
k and I of paragraph 8-35.
r:
Note
The gap changes by 0.015 in. for each
1/4 turn of the brake collar.
I. To increase the gap, rotate the brake collar clockwise; to decrease the gap, rotate the brake collar counterclockwise.
m.
Never remove power from the brake unless
the four brake housing screws are secure.
f.
Replace the brake assembly and tighten the four
slot-head screws.
At the motor control assembly, set switch S 1 to
Note
OFF.
n.
Replace the tachometer coupl ing with XDS
part number 149272, cven if the part replaced has a different number.
Set the circuit breaker to OFF.
o. Disconnect the EP RAD file from the 208V threephase source.
p.
Replece relay K7~r.:;moved in step e).
q.
Remcve the jumper connected in step f.
•".
source.
~onraect
g. Engage the slotted tachometer drive and coupling
with the pin on the end of the motor shaft (see section IX).
h. Replace the tachometer and tighten the three Allenhead scr~ws •
the EP RAD file to the 208V three-phase
i.
OFf.
s. At the motor conho! assembly, set the circuit
breaker to ON.
t.
CAUTI?N
At the motor control assembly, set SNitch Sl fo
Note
Set swltch S1 to ON.
Wait until the disc has stopped befor.::
proceeding.
8-36 REPLACt,VIENT OF THf DISC FILE BRAKE LININGS
a. Remo'!e the power ~rom the EP RAD file and prepare for replacement by pe.brming steps a through i of
paragraph 8-35.
j.
Perfonn steps n through t of paragraph 8-35.
8-37 RAD FILTER REPLACEMENT
Do not attempt to r~lTIove the brake
assembly with the power off.
b. Remove three Allen-head screws at the back of
the brake assembly and remo\'::! the tachometer.
c. Remove four slot-head screws and remove the
brake assembly.
Note
Replace the brake linings with XDS part
number 147222-002 even if the part replaced has a different number. If necessary, adjust the brake collar to allow for
increased thickness of the new lining.
d.
Replace brake linings.
Revised June 1970
These instructions are applicable to motor co.ltr')l unit,
number 146485 and to motor control unit, t-'0rt number
152692.
par~
T!.e motor control unit, part nUillber 146485 is equipped
with three separate filters, tv."ocharcoal and one absolute,
that must be replaced periodically. See table 9-7A.
Th~ motor control unit,part number 152692, IS equipped
with two separate fi Iters, one charcoal and .(me absoIUk, which must be replaced once a year. See table
8-7!). "
In some cases the absolute filter, part number 158947, has
an additional part number on the identifying label. It is
assumed to be a vendor part number.
Always order the XDS part number.
8-27
Paragraph 8-38 to 8-39
XDS 901565
Table 8-7A. Replacement Filter Part Numbers for Motor Control Unit, Part Number 146485
Item
Number
Service
Frequency
Number
Required
1
90 Days
2
Charcoal
Fi Iter
132514
2
90 Days
2
Gasket
132744
3
1 Year
1
Absolute
Filter
158947
Part
Part
Number
Comments
One gasket, item 2 should be installed
with each filter every time it is replaced
I
I
I
See Comment, Item 1
This item, which is to be used in place of
assembly port number 129666, is a complete assembly
Table 8-7B. Replacement Filter Part Numbers for Motor Control Unit, Port Number 152692
--,-
Service
Frequency
Number
Required
1
1 Year
1
Charcoal
Filter
145527
I,.
This is a complete item
2
1 Year
1
Absolute
Filter
158947
I
This is a compiete item
Part
Part
Number
I
Item
Number
I
I
II
:,
8-38 RAD INTERFACE CONNECTOR CLEANII'-IG
PROCEDURE
The RAD interface connectors, which /)I'e mounted on top
. of the disc file, are to be cleaned 0S follow's:
----
Comments
The number, 1024514, which may app~or
on the label, is assumed to be a v61!dor
part number
--
e. Brl..sh both parts of the connector perallel to the
long dimens:(")n of the connector.
f. ~::f..reat steps c through e, so that ~he connector is
cleaned w!~n at least tv/o applications of alcohol •
g. Rr :~ate the connechrs as soen as possible ufter
cleaning.
Use only isopropyl alcohol (filtered)
and a typewriter cleaning brush for
this procedure. Any other materials
may contomi nate the connectors.
a. At the motor control assembiy, set the POWER
switch to OFf.
b. Check that the disc is not rotating and th'Jt the
compressor is running.
Note
Do not dip the brush in the alcohol, as
this action will contaminate the alcohol.
c. Pour suffic ient alcohol over the brush to remove
flux and other soluble contaminants from the brush.
d. Pour additional alcohol over the brush and shake
out the excess by striking the brush handle against a sharp
•
ner.
8-28
h. A: the motor control assembly, place the POWER
switch to ON. Check that the disc rotates.
8-39 SELECTION OF A SPARE WRITE CLOCK
When necessary, select a spare write clock as follows:
a. Check the maintenance log to determine if spare
write clock :;ources are available.
b. ,At ~he motor control assembly, set the POWER
switch to OFF.
c. Check that the disc is not rotating and that the
compressor is running.
Note
Write clock signals are available from
four heads, as indicated in figure 8-14•
Revised June 1970
XDS 901565
r----------,
I
DISC FILE
I
I
I
SELECTION - - ,
UNIT
I
P3SIJ3S
(
\
7
7
14
14
5
5
~·---------------------~19
~--~--~1--~1---412
12
~----------------------~19
6
6
--
~,
t
I
I
I
I
I
: i
I
I
7
I
I
I
I
I
I
J
'r'
t------------f
~,
."
-I-
I
!I
I
I
._ __I
I
I
!
I
I
I
7
I
~
I .
s,.>----,-----I
\.,
I
I
L
._ _
-J16S1
--
I
I
9
I
I
8
I
I
I
I
I
I
I
14
5
I
I
I
6
L _____.__ ~
NOTES:
1. J16A-14 IS ACTIVE WRITE CLOCK TRACK
2. J16A.,..5, J16B-14, AND J16B-S ARE SPARE WRITE CLOCK TRACKS
3. WIRE FROM P16A-S TO P3S-19 MAY BE DISCONNECTED
901565A. e15
Figure 8-14.
Write Clock Tracks, Schematic Diagram
8-29
•
Paragraphs 8 -40 to 8-41
XDS 901565
d. If possible, select a spare write clock by disconnecting P16A from J16A and inserting it in J16B
(or by disconnecting P16A from J16B and inserting it
in J16A) ..
b. Activate an unused gate on an Ln05 Spares Selector module by removing the ground jumper frory'! the gate
input. (See figure 6-21.)
Note
e. If necessary, rewi re connector P16A to se lect the
write clock signal from pin 5 instead of pin 14 (or pin 14
instead of pin 5).
Each gate selects a spare read/write head
circuit when activated. Therefore, do not
provide identical inputs to two gates.
f. If rewiring is necessary, insert P16A in J16A or
J16B.
c. Connect jumpers from the octally coded trac~ address signals to the inputs to the activated gate, as summarized in table 8-8. Example: To spare read/write head
circuit 335 {octal}l connect one gate input to signal X3 at
pin 33, one gate input to signal YM3 at pin 24, and one
gate input to signal YL5 at pin 18.
g. At the motor control assembly, place the POWER
switch to ON. Check that the disc rotates.
8-40 LOGICAL SPARING OF READ/ViRITE HEAD
d. Solder the jumpers atboth sides of the circu:t board.
Replace a fail ing read/write head circuit with a spare
.Write head circuit as follows:
e. Record spared address and spare read/wri te head
circuit used on the head wiring connection chart. (See
figure 8-15.)
a. Express the track address of i he fai ling read/write
head circuit in three-digit octal nc-i'ation. Example: Track
address 221 (decimal) is track address 335 (octal).
f. lns~rt the LT1 05 Spares Selec tor module in tb:: selection unit.
8-41 SELECTION OF SPARE READ/WRITE ~EADS
Note
Ifaspare .. ead/write head is needed, select itas indica~ed in
the following example which substitutes a spare for heck 221.
An unused gate on any LT1 05 Spares
Selector module may be llScd with the
restriction that modules mu~t be inserted in 10..::aii0ns 22A, 23~, 24A,
and 25A before modules '~c.il be inser~ed in locations 26A, 27A, 28A, or
29 A. (See f: gure 7..:.4.)
Note
Cecimal notation is used throughout this
puragraph.
Table 8-8. Summary of Logical Spmi"g Signals
~OCTAL
DIGIT
X-VALUE
V-VALUE
Most Significant
Digit
(10° )
8
Least Significant
Digit
(18)
Middle Di8H
(1 OS)
Signals
Pin
Signals
Pin
Signals
0
XO, XOB
29
YMO, YMOB
21
YLD, YLOB
i2
1
Xl, Xl B
30
YM1, YM1B
22
YLl,YLlB
13
31
YN\2, YM2B
23
YL2, YL2B
14
33
YM3, YM3B
24
YL3, YL3B
15
~
"
Pin
----
2
X2, X2B
3
X3, X3B
4
X4, X4B
34
YM4, YM4B
25
YL4, YL4B
17
5
X5, X5B
35
YM5, YM5B
26
YL5, YL5B
18
6
X6, X6B
36
Y~6,
27
YL6, YL6B
19
Yl7, YL7B
20
k-
YM6B
",I-
/
7
X7, X7B
37
YM7, YM7B
28
./,
8-30
SPARE
HEAD - S
FAULTY HEAD - 0
USED
HEAD CENTER TAP WIRING CHART
SPARE - X
I
NO.1
0&4
1 9 S
2 1
3 10
"T'I
co
c
(0
ex>
I
~
UJ
c:c
~
::J
Z
0
I
W
XDS 901565
a. Find track 221 on the input/output and start/finish
location chart (figure 6-13). Since track 221 is in the
range (208-223), it has an X-value of 3 (NTR2 TR3 TR4)
and is connected to the LT76 Read/Write Coupler module
in location 17B through signals 2X03S and 2X03F (pins Pal B-42 and P8 -1 8-43).
d. A spare read/write head is available at J8-1 A-36.
(.A. read/write head is available at J8-1A-27, since this
read/write head is connected to the same read/write
coupler through PS-1 B-42 and P8-1 B-43.)
Note
b. Find the X-values of 3 on the head location chart
(figure 6-10, sheet 1 of 2). The read/write head for track
221 is on surfac~ 2, slot 5, and is controlled by Y -se lect
signal Y29.
Record any changes in wiring on the
site documentation and on the head
wiring connection chart of the EP RAD
file (figure 8-15).
c. Y -select signal Y29 is connected to the read/write
head assembly at J8-1A-·33.
e. Disconnect the centertap wire from J8-1A-33 and
connect it to the spare.
8-32
XDS 901565
Paragraphs 9-1 to 9-2
SECTION IX
ILLUSTRATED PARTS BREAKDOWN
9-1
GROUP ASSEMBLY PARTS LIST
The Group Assembly Parts list is a breakdown of a" systems,
assemblies, and subassemblies which can be disassembled,
reassembled, or replaced and which are contained in the
end arti cle. The Group Assembly Parts list consists of
columnar listings of parts related to illustrations. Parts
are listed in order of di sassembly sequence, except in cases
where sequence of disassembly ccnnot be maintained.
Attaching parts are listed below the related assembly or
subassemblies. Items which are purchased in bulk form
(for example, wire and insulating materials) are not listed.
is restricted to the model identified by the code letter.
{Where no letter symbol appears in this column, the part is
used on all models of this configuration.}
How to use the III ustrated Parts Breakdown.
To obt(1i:\ information about a part, the following steps
shou Id be taken:
a.
Refer to the applicable assembly breakdown
b. Compare the part with the illustration until part is
located.
Each parts list table is arranged in seven columns C1~ follows:
c.
a. The figure number of the part listed and the index
number corresoondir.g to the i "ustration reference
b.
The XDS manufacturer's part number for the part
c.
The vendor's part number for the part (if available)
Note the index number
d. locate the index number in the correspoi,ding Group
Assembly Parts List
e. Find the part number and name of part oPFosite
the Index number listed
d. A brief description of the part
e.
The manufacturer's code for the part
f.
The quantity of the par~ :Jsed per assembl,"
g. Usable on code column indicating that when a
letter is ~sed in the code column, the use of the coded part
9-2
NUMERICAL INDEX
This index is a listing of the items contained in t!1e Group
Assembly Parts list. The numerical order of the index
(table 9-11) is determined by the XDS part number.
9-1
ILLUSTRATED PARTS BREAKDOWN CONTENTS
Sec. - Fig.
9-2
Page
9-1
Extended Performance RAD Storage Unit and RAD Controller • • • . . . . . . . • . . . . . . . . . • . . • • •
9-3
9-2
RAD Storage Unit Cabinet Assembly . . . . • . . . . . . . . . . . . . . • . . . . . . . . . . . • . • . . . . . . .
9-5
9-3
Selection Unit Assembly . . . .
9-14
9-4
Module Location (Selection Unit Assembly) . . . . . . . . • • . . . . . • . . . . . . . . . . . . . . • . . . . .
9-22
9-5
Spindle and Drive Assembly . . • • . ". • • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . .
9-24
9-6
Motor Control Unit Assembly • . . . . . . . . . ". . . . . . . . . . . . . . . . . . . . . . . • . . . • . . . •.
9-29
9-7
Printed Wiring Board (TB1) .
9-40
9-8
Power Distribution P~nel Assembly . . . . . . . . . . . . . . . . . . . : . . . . . . . . . . . • . . • . • • . . . .
9-43
9-9
Extended Performam..:: RAD Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . .
9-48
9-10
Module- Location (RA[) Controller} . . . . . . . . . . . . . . • . . . . ; . . . . . . . . . . . . . . . • • . . . . .
9-54
•.
XDS 901565
J.
i
901 565 A. 901
Figure 9-1.
Extended Performance RAD Storage Unit and RAD Controller
9-3
XDS 901565
Table 9.:..1. Extended Performance RAD Storage Unit
Fig. &
Index No.
XDS
Part Number
9-1-
139576 0
- 1
Vendor
Part Number
7
Mfg.
Code
Units Per Usable on
Assy
Code
Extended Perf RAD"Storage Unit (7232)
. (Fig 9-1)
149763 C
Storage Uni t Cabi net Assy
(Fig 9-2)
1
131419
·
Cabinet Door Assy (Not shown)
2
- 2
131410
·
Cabinet Side Panel Assy
2
- 3
139697 C
Disc File Assy (Spindle and Drive)
(Fig 9-5)
1
- 4
139690 E
·
Selection Unit Assy
(Fig 9-3)
1
- 5
149330 M
Extended Perf RAD Controller (7231)
(Fig 9-9)
l
/
9-4
Description
1 2 3 456
1
XDS 901565
8
7
2
3
30
33
35
52
32
1:________-r_~~
Ii 13::~_7;~-~
1240
'----26
~~L-l--i+--fi~*TH---18
A
I
. l. _ _-
______________~------901 565A. 902
Figure 9-2.
RAD Storage Unit Cabinet Assembly
9-5
XDS
Table
XDS
Fig. &
Index No.
Part Number
9-2-
149763 C
Vendor
Part Number
901565
9-2. RAD Storage Unit Cabinet Assembly
Description
Mfg.
Code
1 2 345 6 7
Units Per Usable on
Assy
Code
· RADStorage Unit Cabinet Assy
· · Cabinet Basic Structure
· · Cap Cabinet Top
· · Clip, Speed U Type
REF
-·1
153320 A
- 2
117424
- 3
139565-002
- 4
139814-001
·
Bracket, Chassis locking ~H
1
- 4
139814-002
·
Bracket, Chassis Locking RH
1
I
1
1
2
(Attaching Parts)
-
101441-105
·
Screw, Cap Hex Hd
-2
-
101441-104
Screw, Cap Hex Hd
6
-
1(1)018-600
·
· ·
-
100023-600
-
100008-600
·
16
Washer, Flat
Washer, Lock Spri ng
8
Nut, Hex
8
/
---*--- 5
139994-001
· ·
Angle, Mtg LF (Retma)
1
- 5
139994-002
A?1g Ie, Mt8 RF {Retma}
1
- 6
132019
· ·
··
Angle, Mtg Rear (Retma)
2
(Attaching Parts)
-
100023-600
-
107311
10144"i-1C4
· ·
·
· ·
Screw, Cap Hex Hd
18
Washer, lock Spring
18
Nut, Unistrut
18
---*--- 7
145412-001
·
Bracket, Latch Ad1usting LH
- 7
145412-002
· ·
Bracket, Latch Adjusting RII
-. -
(Continued)
9-6
1
1
-
-.- - -
- -- -
-
-
-
XDS 90156!J
Table 9-2. RAD Storage Unit Cabinet Assembly (Cont.)
Fig. &
Index No.
XDS
Part Number
Vendor
Description
Part Number 1 2 3 4 5 6 7
9-2-
Mfg.
Code
Units Per Usable on
Assy
Code
(Attaching Ports)
-
101441-104
Screw, Cap Hex Hd
8
100018-600
Washer, Flat
8
-
100023-600
Washer, lock Spring
-
100008-600
Nut, Hex
16
8
---*--- 8
111097
·
Brocket, locking
2
(Attaching Parts)
-
100012-610
-
100018-600
· ·
-
100023-600
·
-
100008-600
·
Screw, Pan Head
4
Washer, Flat
8
Washer, lock Sprir.:;
4
Nut, Hex
..f.
---*--- 9
129459
-10
131354
-11
132088
-12
139815-001
-i2
139815-002
-13
139816-001
-13
139816-002
·
·
·
·
·
·
Slide, 2J hch (j is Ib)
4
Brccket SI ide, Mtg Front
2
Bra~kei·
Si ide,
2
Bra~ket
SI ide, Sel lvitg RH Frt
100039-510
-
·
Rear
!
Bracket SI ide, Set :V\tg lH Frt
Brocket SI ide, Sel Mtg RH Rear
i
Bracket SI.ide, Sel Mtg lH Rear
1
(Attaching
-
/v.t~
POi
ts)
Screw, Flat Head
28
100018-500
Washer, Flat
28
-
100024-500
Washer, lock lnt Tooth
28
-
100008-500
Nut, Hex
28
---*---
(Continued)
9-7
XDS 901565
Table 9-2. RAD Storage Unit Cabinet Assembly (Conf.}
XDS
Fig. &
Index No.
Part Number
9-2-14
139858
Vendor
Description
Part Number 1 2 345 6 7
Mfg.
Code
Units Per Usable on
Assy
Code
Angle, Support Front
1
(Attaching Parts)
-
100012-406
-
100018-400
-
100024-400
· ·
· ·
· ·
Screw, Pan Head
4
Washer, Flat
4
Washer, Lock lnt Tooth
4
-- -*- --
I
-15
·
145698
4
Bumper, Rubber
{Attaching Parts}
-
100018-307
-
100018-300
· ·
·
Screw, Pan Head
8
Washer, Flat
8
-- -*---16
147912-001
·
Bracket, Frame Mtg RH
1
-16
147912-002
· ·
Bracket, Frame Mtg lH
1
(Attachi ng Perts)
,
-
100039-609
-
100012-505
-
100024-500
· ·
· ·
·
6
Screw, Flat Head
Screw, Pan Head
.Washer, Lock
I
6
6
---*---17
139690
-18
132646
-18
133155
·
· ·
· ·
Selection Unit Assy (See Fig. 9-3)
REF
Plate, Counter Balance
1
Plate, Counter Balance
1
(Attaching Parts)
f
I,
I
-
101441-407
·
Screw, Cap Hex Head
6
-
100018-600
Washer, Flat
6
-
100023-600
·
· ·
Washer, Lock Spri ng
6
-- - * -- (Conti nued)
XDS 901565
Table 9-2. RAD Storage Unit Cabinet Assembly (Cont.)
Fig. &
Index No.
XDS
Part Number
9-2-19
145315-001
-19
145315-002
Vendor
Part Number
Description
1 2 3 4 5 6 7
·
· ·
Mfg.
Code
Units Per US0ble on
Assy
Code
Angle, Spacer Slide RH
1
Angle, Spacer Slide LH
1
(Attaching Parts)
-
100039-609
·
---*
I
-20
131356
I
· ·
8
Screw, Flat Head
---
Plate, Drum Mounti ng
1
(Attaching Parts)
-
100012-520
I
I
I
-
iOOO1S-500
-
100023-500
I
· ·
·
·
Screw, Pan Head
10
Washer, Flat
10
Washer, Lock Spri ng
10
- - - * - _. -21
132644
-22
13131.2
II
· ·
I
leg Support Assy
Bracket,
L~g
Support
2
2
(At;-aching Part.,)
I
-
100012-500
-
10001S-500
-
iOO024-500
10000S-500
I
Screw, Pan Head
I
!
Ij
Washer, Flat
·
·
131357
12
Washer, Lock Int loath
6
Nut, Hex Machine
6
- - - * - ... -
II
-23
6
·
Bracket, Shi ppi ng
1
(Attaching Parts)
-
101441-104
-
10001S-600
-
100023-600
10000S-600
I
·
·
·
· ·
Screw, Cap Hex Hf'Jd
2
Washer, Flat
2
Washer, Lock Spri ng
2
Nut, Hex
2
-- - * - - -
(Continued)
9-9
XDS 901565
Table 9-2. RAD Storage Unit Cabinet Assembly (Cont.)
XDS
Fig. &
Index No.
Part Number
9-2-24
147931-006
Mount, Shock
4
-25
129633-628
Screw, Cap Soc Hd
4
Vendor
Part Number 1 2 3 4 5 6
Desc.ription
7
Mfg.
Code
-
Units Per Usable on
Assy
Code
(Attaching Parts)
-
100012-305
Screw, Pan Hd
8
-
10001S-300
Washer, Flat
8
-
100024-300
Washer, Lock lnt Tooth
8
·
---*- - I
-26
139697
Disc Fi Ie Assy (Sec Fig. 9-5)
-27
100008-410
-28
100018-310
-29
101918
-30
149960
-31
111945
-32
117026-005
-33
1320S3-001
Union, Tube Fitting
I
1
-33
132570···001
Terminal, Ins Ring TO'lgue
I
1
·
·
·
Nut, Hex
8
Washer, Flat
8
Bolt
4
Compressor Assy
1
Pump,Positi'!l~
·
-
REF
1
Pressure
4
Mount, SI,zer
(Attaching Parts)
I
I
-
100008-600
Nut, Hex
-
10001S-600
Washer, Flat
4
-
100024-600
Washer, Lock lnt Too~h
4
·
4
---*---34
146649
Bra cket, Compressor Mou'lt i ng
1
(Attaching Parts)
-
10000S-600
Nut, Hex
4
-
10001S-600
Washer, Flat
4
-
100023-600
Washer, Lock Spri ng
4
---*
.'
(Continued)
9-10
-- -
XDS 901565
Table 9-2. RAD Storage Unit Cabinet Assembly (Cont.)
Fig. &
Index No.
XDS
Part Number
9-2-35
116701
Tubing, Pressure
A/R
-35
101625-003
Tubing, Spirop
A/R
-36
100657-003
·
Clomp, Nylon
2
-36
100657-008
·
Clamp, Nylon
2
Vendor
Description
Part Number 1 2 345 6 7
Mfg.
Code
Units Per Usable on
Assy
Code
(Attaching Part:;)
-
100012-506
·
Screw, Pan Hd
2
-
100018-500
·
Washer, Flat
2
-
100024-500
· ·
Washer, Lock lnt Tooth
2
Ir
I
-37
---*---
·
146485
I
-
100012-506
-
100018-500
-
!00024-500
-38
137529
Screw, Pan Hd
8
· ·
Washer, Flat
8
·
Washer, Lock lnt T~oth
8
·
Power Distribution Panel Assy
(See Fig. 9-8)
I
I
I
1
{Attaching Parts}
I
j
Motor Control Unit Assy
(See Fig. 9-6)
---*---1
(Attaching Part!»
-
. 1000 12-506
-
100018-500
-
100024-500
II
II
· ·
·
Screw, Pan Hd
6
Washer, Flat
6
Washer, Lock lnt Tooth
6
- - - * - --39
136674
· ·
Power Supply Assy
-40
146488-001
·
Angle, Chassis Mounting RH
(PT20)
1
1
(Continued)
9-11
XDS 901565
Table 9-2. RAD Storage Unit Cabinet Assembly (Cont.)
Fig. &
Index No.
XDS
Part Number
9-2-40
146488-002
Vendor
Part Number 1 2 345 6
· ·
Description
7
Mfg.
Code
Angle, Chassis Mounting LH
Units Per Usable on
Assy
Code
1
(Attaching Parts)
-
100012-504
· ·
Screw, Pan Hd
10
100012-506
·
Screw, Pan Hd
10
100018-500
Washer, Flat
-
100024-500
· ·
· ·
"-
Washer, Lock Int Tooth
10
10
--- * - - -41
·
139222
I
Power, Fi Iter Assy
1
(Attaching Parts)
-
100012-508
-
100018-500
-
I 100024-500
-42
I
I
-43
·
· ·
Screw, Pan Hd
3
Washer, Flat
3
Washer, Lock Int Tooth
3
---*---
·
· ·
139223
139224-002
Plate, Mounting
1
Cover, Fi Iter
1
(Attaching Parts)
-
I
·
100012··404
Screw, Pan Hd
4
100018-400
·
Washer, Flat
4
100024-400
· ·
Washer, Lock Int Tooth
4
- -- * - - -44
100840-001
·
·
-45
100840-003
·
-46
139175
-47
132570-004
-48
110996-105
·
-49
100274-016
· ·
-50
109432-001
·
·
Grommet, Nylon
A/K
Grommet, Nylon
A/R
Filter, Power (C1 C2 C3 C4)
4
Termi no I, Ri ng Tongue
9
Resistor Fixed Fi 1m 1W
4
Sleeve, Plosf'ic
AIR
Block, Terminul Stack Type
10
(Continued)
9-12
XDS 901565
Table
XDS
9-2. RAD Storage Unit Cabinet Assembly (Cont.)
Fig. &
Index No.
Port Number
9-2-50
109432-005
· · ·
-?O
109432-006
·
-50
109432-008
-51
130191-002
· ·
· · ·
Vendor
Part Number
Description
Mfg.
Code
1 2 3 4 5 6 7
Units Per Usable on
Assy
Code
Clip, Retaining
4
Channel, Mounting
2
Plate, End
2
Clamp, Conduit
2
(Attaching Parts)
-
100039-405
-
100024-400
-
100008-400
·
· · ·
· ·
Screw, Flat Hd
4
Washer, Lock Int Tooth
4
Nut, Hex
4
I
-- - * - - 149330
-52
·
Extended RAD Contro!!el (See Fig.
9-9)
REF
I
I
I
9-13
XDS 901565
.
Unit Assembly
Figure 9- 3 . Selection
9-14
XDS 901565
Table 9-3. Selection Unit Assembly
Fig. &
Index No.
XDS
Part Number
9-3-
139690
- 1
131958
- 2
131959
- 2
131960
Vendor
Description
Part Number 1 2 3 4 5 6 7
·
Selection Unit Assy
·
· ·
Mfg.
Code
Units Per Usable on
Assy
Code
REF
Door, Chassis
2
Hinge, Chassis Door
1
Hinge, Chassis Door
1
(Attaching Parts)
-
· ·
100012-204
100018-200
Scre'N, Pan Hd
8
. Washer, F lot
·
100024-200
8
Washer, Lock Int Tooth
8
-- -* --- 3
· ·
129554
Trigger, Door Latch
I')
L
(Attaching Parts)
-
·
· ·
100012-105
100024-100
2
Washer, Lock
2
---*
I
- 4
Screw, Pan Hd
129540
_
~a
_
Sprinz; Door latch Mounting
1
(Aaaching Parts>
-
100012... 304
-
100018-300
-
100024-300
I
·
I
ScreVv, Pon Hd
2
Washer, F 101-
2
Washer, Lock lnt To')~h
2
- - - * - ... - 5
130639
·
Bracket, Door Lctch !v\ounti ng Support
1
(Attaching Parts)
-
100012-203
Screw, Pan Hd
4
-
100018-200
Washer, Flat
4
-
100024-200
Washer, Lock Tnt Tooth
4
·
---* - --
(Continued)
9-15
XDS 901565
Table 9-3. Selection Unit Assembly (Cont.)
Fig. &
Index No.
XDS
Part Number
9-3-6
116231
· ·
Chassis, 32 Module (See Fig 9-4 for
Mod location)
2
-6
129567-001
· ·
Nut, Strip Speed
4
-7
129694
· ·
Panel, Blank
1
[
Vendor
Description
Part Number 1 2 345 6 7
Mfg.
Code
Units Per Usable on
Assy
Code
(Attaching Parts)
-
100012-304
-
100018-400
-
100024-400
-
·
·
Screw, Pan Hd
19
Washer, Flat
19
19
Washer, Lock Int Tooth
0"
100008-400
·
5
Nut, Hex Mach
---*--l
- 8
116522
·
Channel, Cable Routing
1
- 9
123940-001
·
Channel, Cable Routing
2
(Attaching Parts)
-
100012-203
·
-
100018-200
-
100024-200
· ·
·
Screw, Pan Hd
12
Washer, Flat
12
Washer, Lock Int Tooth
12
- --*---10
117427
· ·
Filter, Air
1
-11
100657-002
·
Clamp, Cable
2
(Attaching Parts)
-
100012-407
Screw, Pan Hd
2
-
100018-400
Washer, Flat
2
-
100024-400
Washer, Lock Int Tooth
2
Nut, Hex Mach
2
·
100008-400
---*---
9-16
-12
139865
-13
100657-003
·
·
Backwiring Board Assy
1
Clamp, Plastic
2
-
(Continued)
XDS 901565
Table 9-3. Selection Unit Assembly (Cont.)
Fig. &
Index No.
XDS
Part Number
9-3-14
152673
Vendor
Part Number
Description
1 2 345 6 7
..
Ground· Strap Assy
Mfg.
Code
Units Per Usable on
Ass}'
Code
2
(Attaching Parts)
-
114538-214
-
100008-300
-
100024-300
· ·
·
· ·
Screw, Sheet Meta I
36
Washer, Flat
36
Washer, Lock lnt Tooth
36
.-
-15
139968
• . Strip Mounting, Wire Clamp
I
-
100012-304
-
100018-300
-
100024-300
139969
·
·
·
I
1100039-310
l
· ·
I
· ·
I
139637
I
-
100012-304
-
100018-300
-
100024-300
II
3
Washer, Flat
3
Washer, lock Int Tooth
3
Brock, Wire Clamoir:g
2
(Aftochi ng Por~s)
I
-17
Screw, Pan Hd
- - - * - --
I
-
1
(Attaching Parts)
I
-16
---*---
Screw, Flat Hd
6
- - - * - -· ·
Top Fan Assy
1
(Attaching Par:-s)
·
· ·
··
Screw, Pan Hd
8
Washer, Flat
8
Washer, lock Jilt TDoth
8
---*---18
100657-011
· ·
Clamp, Cable
2
(Continued)
9-17
XDS 901565
Table 9-3. Selection Unit Assembly (Cont.)
Fig. &
Index No.
XDS
Part Number
9-3-19
100657-009
Vendor
Description
Part Number 1 2 345 6 7
· ·
Clamp, Cable
Mfg.
Code
Units Per Usable on
Assy
Code
2
(Attachi ng Parts)
{
-
100012-407
-
100018-400
100024-400
·
Screw, Pan Hd
4
·
Washer, Flat
4
· ·
Washer, Lock Int Tooth
4
---*---
r,
-20
109432-001
-20
109432-011
-20
109432-008
-20
109432-006
·
·
Block, Terminal Stack Type
14
End, Block
4
·
End, Plate
2
· ·
Channel, Mounting
2
(Attachi r.g Parts)
-
100012-310
·
Screw, Pan Hd
4
-
100018-300
· ·
Washer, Flat
4
100024-300
· ·
Washer, Lock lnt Tooth
4
---*---21
139967
·
Bracket Mounting, Termincl Block
(22-4 AWG)
I
-
2
(Attaching Parts)
100012-405
100018-400
· ·
· ·
100024-400
Screw, Pan Hd
4
Washer, Flat
4
Washer, Lock Int Tooth
-1
---*---22
139634-001
-22
139634-002
-23
139635
· ·
· ·
·
Panel, Side Chassis RH
1
Panel, Si de Chassi s LH
1
Frame, Pivot Chassis Mounting
1
{Attaching Parts}
,
\.
-24
126340-010
·
Fastener, Capti ve
---*--(Continued)
9-18
2
XDS 901565
Table 9-3. Selection Unit Assembly (Cont.)
Fig. &
Index No.
XDS
Part Number
9-3-25
107199-308
-26
Vendor
Part Number 1 2 345 6
·
Description
7
Mfg.
Code
Units Per
A<:.sy
Pin, Roll Corrosion
2
116722-003
Spring, Compressioll
2
-27
145419-001
Rod, Latch
1
-27
145419-002
Rod, Latch
1
-28
145418
Guide, Rod
4
l~sable on
Code
I
(Attaching Parts)
-
100012-401
·
Screw, Pan Hd
8
-
100018-400
·
Washer, Flat
8
-
100024-400
·
Washer, Lock Int Tooth
8
I
-29
I 145420-001
-29
145420-002
--- *
·
I
·
100039-520
-
·
100012-524
__
Block, Latch
1
Block, latch
1
{Attachi ng
-
"-0
I
Par~s}
!
Screw. Flat Hd
4
Screw, Pan Hd
4
Washer, Flat
4
Washer, Lock I nt -:- ooth
4
i
-
-
I 100018-500
I 100024-500
·
-- - * - - -30
107396
·
Switch, Toggle
-31
145704
· ·
Panel, Switch Mounting
16
1
(Attaching Parts)
-
100012-50.5
-
100018-500
-
100024-500
I
I
I
Screw, Pan Hd
8
Washer, Flat
8
Washer, Lock Int Toath
8
- - - * - -. -32
147024
Rod Hanger, Interface Plate
1
-33
139686
Pin, Hinge
2
(Conti nued)
9-19
XDS 901565
Table 9-3. Selection Unit Assembly (Cont.)
Fig. &
Index No.
XDS
Part Number
9-3 -34
139636
· ·
Frame, Pivot Selection Unit Mtg
1
-35
139892-002
··
Angle, Support
1
-35
139892-001
·
Angle, Support
Vendor
Part Number
:
1 2 3 4 5 6
Description
7
Mfg.
Code
Units Per Usable on
Assy
Code
(Attaching Parts)
-
100012-508
·
Screw, Pan Hd
4
-
100018-500
Washer, Flat
4
-
100024-500
·
·
Washer, Lock
4
- - - *- - -36
·
109159-008
Bumper, Rubber
2
(AttC'o:hing Parts)
u
-
100018-400
-
100024-400
-
100008-400
·
·
· ·
Washer, Flaf
2
Washer, Lock Int Tooth
4
Nur, Hex Mach
6
-- - * ---37
113800-212
-38
145515
2
Screw, Shoulder Slotted
·
Cover, Connector- Base
Pla~e
1
(Attaching Parts)
-
100012-205
-
100018-200
-
100024-200
·
·
·
Screw, Pan Hd
4
Washer, Flai
4
Washer, Lock Ii'lt Tooth
4
*- - -39
146673
·
Hanger
2
-40
113800-204
·
Screw, Shoulder Slotted
2
---*---
.,
le
9-20
-41
145514
-41
153709-001
-42
126340-002
·
-
·
·
Cover, Connector
1
Chart, Head Wiring
1
Captive, Fastener
2
(Conti nU 0 d)
XDS 901565
Table 9-3. Selection Unit Assembly (Cont.)
Fig. &
Index No.
9-3 -:-43
XDS
Part Number
139969
Vendor
Description
Part Number 1 2 345 6 7
·
Block, Wire 'Clamping
Mfg.
Code
Units Per Usable on
Assy
Code
2
(Attaching Parts)
-
100039-307
·
Screw, Flat Hd
6
---*---44
127489-002
·
Connector, 50 Pin
8
(.4. ttach i ng Pa rts)
-
100012-205
-
100024-200
·
·
Screw, Pan Hd
16
Washer, Lock Int Tooth
16
127614
-46
152L1·29-001
-47
152429-002
·
·
·
I
I
---*---45
1
Plate Mtg, Connector Plug
1
Screw, Captive
2
Nut, Mtg
2
---*--I
i,
I
I
I
I
9-21
XDS 901565
r
""
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 i3 12 11 10 9 8 7 6 5 4 3 2 1
~'v..
"V
W
I
I
A
J1l\ 111\ III'.
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
B
901565A. 904
Figure 9-4. Module location (Selection Unit Assembly)
9-22
XDS 901565
Table 9-4. Module Locations (Selection tJ.nit Assembly)
Fig. &
Index No.
XDS
Part Number
Vendor
Part Number
Description
Mfg.
Code
1 2 3 456 7
Unit·s Per Usable on
Assy
Code
149853 B
Module Kit Assy (SOelection Unit Assy)
1
-:-1
139418
8
-2
139409
Module Assy, HT42 Read AMP
1
-3
13956«
·
·
·
Module Assy, LT76 Read Write
Module Assy, RT18 Y Select
9
-4
139714
Modu Ie Assy, HT 44 Limi ter
1
-5
147791
·
·
Module Assy, AT51 Clock Discr
1
-6
139716
Module Assy, LT77 Dato Decode
1
-7
139792
·
·
Module Assy, HT43 Write AMP
2
-8
130747
·
Module Assy, L132 Sec Ind Dec
1
-9
139570
Module Assy, AT 41 WriTe Clock
1
-10
133500
I
Module Assy, V-lT29 RAD Pwr Monitor
1·
-11
126982
I
·
·
·
Module Assy, LT26 Switch Comp
1
-12
117028
Module Assy, FT12 GotE:d FF
2
-'3
.116029
·
·
Module Assy, BTl1 BAt'-:D Gate
2
Modu Ie Ass)"
1
·
Module Assy, ATl2 Cable Driver
1
·
Module Assy, AT1 0 Cabic Rec
1
·
Module Assy, OT12 Lomp Dr Rec
1
9-4 -
I
r
P35 Sector AMP
I
I
I
I
I
-14
145221-001
-15
124629
-16
123018
-17
131572
-18
116994
·
Module Assy, ITl1 lnvertci Matrix
1
-19
131572
Module Assy, FT11 Hig~1 !;peed Ctr
1
-20
116257
·
·
Module Assy, X110 Term Module
1
I
-21
130689
·
Module Assy, BTl5 10 Sat: 1st
1
-22
147800
1
I
-23
145085
·
·
Module Assy, LT85 Pul
Module Assy, BT31 BAND Gote
1
-24
145095
·
Modu Ie Assy, IT31 NAND Gate
1
-25
115965
Module Assy, BTl 2 Binary Decoder
·2
-26
164375
·
·
Module A~sy, LTl05 Spare Select-or
8
II
II
I
PtlC
Comp
I
9-23
XDS 901565
3
901565A.905
Figure 9-5.
9-24
Spindle and Drive Assembly
XDS 901565
Table 9-5. Spindle and Drive Assembly
Fig. &
Index No.
XDS
Part Number
Vendor
Part Number
Description
7
1 2 3 4 5 6
9-5 -
139697 C
Disc Fi Ie Assy
9-5 -
148433 D
.
9-5 -
123455 R
-1
127387-001
-2
127388
-3
127389
-3
126716
-3
127054
-3
111468-502
-4
126623
-5
123456
-6
147222-001
··7
133079-406
Spindle & Drive Assy
·
·
I
.
Units Per Usable on
Assy
Code
REF
Bulk Hd Unit-(Disc Fi Ie Assy}
·
Mfg.
Code
1
1
Nut, lock
2
Washer, Hub Positioning
1
Hub Assy
1
.
Disc, Hub
1
Insert, Hub
1
Insert, Thleod
6
.
Bearing, Retainer
'i
·
Bail, Bearing
2
·
Brake, Magnetic
1
(Attaching Parts)
·
Screw, Flat Hd
4
---*---8
132086
-9
107199-413
-10
131965
·
.
I
Spline, Brake Drive
1
Pin, Roll
1
Cap, Motor Housing
1
(Attaching Palts)
-11
Screw, Cap Sc ... Hd
113440-206
- - - *- - -
I
-12
136561-001
-13
132570-002
I
I
4
·
Connector, Male 14 Pin (J37)
1
Terminal, Ins ;:ing Tongue
1
(Attaching Parts)
·
Screen, Pan HJ
1
100018-400
Washer, Flat
1
113221-400
Washer, Lock
1
-14
100012-404
-15
-16
- - - * - - (Continued)
9--25
XDS 901565
Table 9-5. Spindle and Drive Assembly (Cont.)
Fig_ &
Index No.
9-5 -17
Ii
XDS
Part Number
Vendor
P9rt Number
Description
·
149581
Mfg.
Code
1 2 3 4 5 6 7
Clamp, Cartridge
Units Per Usable on
Assy
Code
1
(Attaching Parts)
I
-18
129633,.. 206
-19
100008-200
·
·
Screw, Cap Soc Hd
4
Nut, Hex Mach
2
---*---20
149479-001
-21
149580
-22
I
152008
.......
....-23..."'.",,- 149578-001
~.~"'
t~
.......-""~~.,.,
,-.---~-"
,~; "('j;:; 1)
·
·
Cartridge, Brush Holder
·
Plug, Screw
5"" . t:?~?
1
1
Bracket, Cartridge
-'
· .~:.~!-~~!!!:~._ ~~,~~.t~,~~
1
1
-24
100720-006
·
Grommet, Rubber
2
-25
128155-001
·
Thermostat, Overtemp
1
(Attaching Parts)
-26
100012-104
-26
100018-100
·
-26
100024-1~0
·
-26
100008-100
·
·
Screw, Pan Hd
2
Washer, Flat
2
Washer, Lock
2
Nut, Hex Mach
2
---*---
I
I
-27
130777-001
·
Spacer, Rotor
1
-28
131977-005
·
Motor, Rotor
1
.;..29
131186
·
Cap, load Spring Retaining
1
{Attaching Parts}
-30
129633-508
-30
129633-506
·
·
·
Screw, Cap Soc Hd
4
Screw, Cap Soc Hd
4
---*---
"C
-31
123460-02i
·
110" Ring, Teflon
-32
127346-001
·
Shim, Retaining Beariog
AIR
-32
127346-002
Shim, Retaining Bearing
AIR
(Continued)
9-26
2
XDS 901565
Table 9-5. Spindle and Drive Assembly (Cont.)
Fig. &
Index No.
XDS
Part Number
Vendor
Descdption
Part Number 1 2 3 4 5 6 7
Mfg.
Code
Units Per Usable on
Assy
Code
9-5 -32
127346-003
·
Shim, Retaining Bearing
-33
128163-002
· ·
Washer, Spring
2
-34
123458
Shaft, Spindle
1
-35
126835-003
·
Woodruff, Key
1
-36
107199-108
·
Roll, Pin
1
-37
131964
·
Baffle, Motor Housing
1
.
.
A/R
(Attaching Parts)
-38
129633-204
-39
100018-200
·
-
Screw, Cap Soc Hd
4
Washer, Ftat
4
---*---40
131997-004
· ·
Motor, Elec ThreE' Phase (Stator)
1
(Attaching Parts)
-41
132103-001
·
Screw, Motor HC.lsing Mtg
4
---*---42
131963
-43
129687
·
·
HOllsing, Motor
1
Baffle, Air Spindle & Drive
1
(Attaching Parts)
-44
131530-103
·
Screw, Drive
4
---*---45
127056
-46
107199-614
-47
126624
-48
133080
·
· ·
·
· ·
.
~
Spindle Housing Assy
1
Pin, Roll Cres (3/16 Dia x 7/8 Lg)
3
Liner, Spindle Housing
1
Plate, Adaptor Ta<..hometer
1
I
(Attaching Parts)
-49
113440-206
·
Screw, Cap Soc Hd
3
---* -- I
(Continued)
9-27
XDS 901565
Table 9-5. Spindle and Drive Assembly (Cont.)
Fig. &
Index No.
9-5 -50
XDS
Part Number
Vendor
Description
Port Number 1 2 3 4 5 6 7
·
132593
>t1lX 1;.
-51
123054-104
·
Mfg.
Code
1
Generator, Tachometer ~
.
a
. Units Per Usable on
Assy
Code
it
(Attaching Parts)
Screw, Button Hd
3
---*---52
133559-026
·
Wire, Twisted Pair
AIR
-52
102066-001
·
Cord, loci ng
AIR
-53
149272
Coupling, Shaft
1
-54
132743
·
·
Shaft, Coupling-Tachometer
1
- - - * -- -
.-
~
g:..28
-
XDS 901565
901 565A. 906
Figure 9-6.
Motor Control Unit Assembly
9-29
XDS 901565
Table 9-6. Motor Control Unit Assembly
Fig. 8.
Index No.
9-6 -1
XDS
Part Number
Vendor
Part Number
Description
Mfg.
Code
J 2 3 4 5 6 7
146485 J
·
132175
·
Units Per Usable on
Assy
Code
Motor Control Unit Assy
REF
Chassis Motor Control Unit
1
(Attaching Parts)
-
113526-006
·
Nut, Self Clinching
10
-
113526-012
·
Nut, Self Clinching
5
---*---2
146484
·
Chassis, Filter Mtg Control Unit
1
(Attaching Parts)
-
113526-012
-
100012-508
-
100018-500
-
11322i -500
-
100008-500
·
·
·
Nut, Self Clinching
2
Screw, Pan Hd
5
Washer, Flat
5
·
Washer, Lock Spring
5
·.
Nut, Hex Mach
5
I
-" - - * - - -3
146487
·
Angle, Mtg RH
-3
146486
·
Angle, Mtg lH
I
I
1
1
(Attaching Parts)
-
100012-508
· .
Screw, Pan Hd
6
-
100018-500
·
Washer, Flat
6
-
113221-500
·
Washer, Lock Spring
6
-
100008-500
·
Nut, Hex Mach
6
---*---4
132176
-4
126340-012
·
·
Cover, Chassis (Motor Control Unit)
1
Fastener, Captive
4
---*---5
147044-001
·
Label, Filter
"2
-6
129731
·
Filter, Container Assy
2
(Continued)
9-30
XDS 901565
Table 9-6. Motor Control Uni t Assembly (Cont.)
Fig. &
Index No.
XDS
Part Number
9-6 -6
127990
·
Container, Filter-Charcoal
2
-7
126440-012
Fastener, Captive
4
-8
116702-002
·
· ·
Connector, Elbow
4
-9
134844-001
·
Nut, Lock
8
-10
132514
·
Filter, Air Charcoal
2
-11
132744
Go!.ket, Fi Iter Mtg
2
-12
147044-002
· ·
· ·
Label, Fi Iter
1
-13
158947
·
Absoll}te Filter Unit Assy
1
Vendor
Description
Part Number 1 2 3 4 5 6 7
I
-
Mfg.
Code
Units Per Usable on
Assy
Code
1
(Attaching Parts)
100012-306
4
Screw, Pan Head
I
-"- - * - - -14
132084
-15
116701
-16
117226
-17
~34993
I
I
i
I
I
-18
133033-001
··19
132749-001
- 20
145646
-21
~
-22
132534
16702-001
I
I
I
i
··
·
·
·
··
·
··
· ·
Union, Bulkhead
2
Tubi ng, Pressure
72
FiI~er,
Air
1
Regulator, PreSSUie
1
Plug, Pi pe Hex Hd
1
Nippl~,
2
Pipe Fitting
Fitting, Adaptpr Bulkhead
1
· ·
Connector, Elbow
2
··
Valve, Solenoid (K12, K13, K14)
3
I
I
(Attaching Parts)
-
100012-508
·
-
100018-500
-
113221-500
·
·
·
.
· ·
Screw, Pan Hd
".
Washer, Flat
6
6
Washer, Lock Sp;: ng
-"- - * - - -23
100720-009
·
Grommet, Rubber
"3
I
(Continued)
9-31
XDS 901565
Table 9-6. Motor Control Un it Assembly (Cont.)
Fig. &
Index No.
9-6 -24
XDS
Part Number
132359
Vendor
Description
Port Number 1 2 3 -4 5 6 7
·
Mfg.
Code
Units Per Usable on
Assy
Code
1
Bracket, Solenoid Mtg
(Attaching Parts)
-
100012-306
-
100018-300
-
113221-300
·
·
·
Screw, Pan Hd
2
Washer, Flat
2
Washer, Lock Spring
2
---*---
(,
-25
113707-002
-26
134843
-27
116702-002
-28
·
·
Swi tch, Pressure (52, S3j
2
Cover, Protective
2
·
Connector, Elbow
2
132749-005
·
Nipple-Pipe Fitting
5
-29
132083-002
·
Union, Tube Fitting (Male)
1
-30
116701
·
Tubi ng, Pre!>S'Jre
-31
132532-002
·
Elbow, Street
2
-32
132528
Tee, Tube Fitting
1
-33
132529-001
-34
133033-002
-35
132178
-36
100840-002
·
·
·
·
·
AIR
Tee, Female Pipe Fitting
Plug, Pipe Hex Hd
·
bracket, Component
GiOmmet, Nylon .
I
.(
1
M~D
1
2
(Attaching Parts)
-
100012-407
-
100018-4·00
-
1l3221-400
· . ·
· ·
·
Screw, Pan Hd
3
Washer,_ Flat
3
V/asher, . lock Spring
3
---* ... --
-37
-
9-32
100657-004
-
100012-410
-
100018-400
-
100008-400
113221-400
·
Clomp, Cobte Nylon
·
·
·
·
Screw, Pan Hd
1
Washer, Flat
1
Washer, Lod: Spring
1
Nut, Hex Mach
1
1
(Attaching Parts)
- - - * - - (Conti nued)
XDS 901565
Table 9-6. Motor Control Unit Assembly (Cont.)
Fig. &
Index No.
XDS
Part Number
9-6 -38
149710
Vendor
Description
Part Number 1 2 3 4 5 6 7
· · ·
Mfg.
Code
Cover, Protective
Units Per Usable on
Assy
Code
1
(Attaching Parts)
-
100012-306
-
100018-300
-
113221-300
· ·
·
·
Screw, Pan Hd
2
Washer, Flat
2
Washer, lock Spring
2
---*---39
132495
·
Thyristor, (XDS 236) (SCR1, R2, R3)
-
3
(Attaching Parts)
-
132570-005
·
113220-600
-41
Terminal, Ins Ring Tongue
3
· ·
Washer, Flat
3
I
Switch, Subminiature DPDT Toggle SI
1
I
Circuit, Breaker CBl
1
113694
133034-001
·
·
·
100039-304
0
Screw: Flat Head 100
4
100992-003
-·43
107132-003
-44
107018-314
I
·
·
Capacitor, DV Oil/Paper (C30, 31,32)
3
Spacer, Round
2
Standoff, Hex
2
100012-320
-
100012-307
-
100018-300
-
100024-300
· ·
·
·
I
I
I
I
I
I
I
I
I
(Attaching Parts)
-
I
II
---*--.-42
I
I
(Attaching Parts)
-
I
·
---*---40
I
Screw, Pan Hd
2
Screw, Pan Hd Recessed
2
Washer, Flat
4
Washer, lock
4
I
I
---*---45
109432-001
-46
109432-005
·
Block, Terminal 18-8 AWS
20
Clip, Retaining
1
(Conti nued)
9-33
XDS 901565
Table 9-6. Motor Control Unit Assembly (Cont.)
Fig. &
Index No.
XDS
Part Number
9-6 -47
109432-006
-48
109432-008
-49
109432-012
[
Vendor
Description
Part Number 1 2 3 4 5 6 7
I·
·
· ·
Mfg.
Code
Units Per Usable on
Ass}'
Code
Mounti ng, Channe I
1
Plate, End
1
Jumper
2
(Att!:lching Parts)
-
100012-407
I-
Screw, Pan Hd
4
-
100018-400
Washer, Flat
4
-
113221-400
- - ·
Washer, Lock Spring
4
-
100008-400
·
Nut, Hex Mach
4
·
---*---50
132343
-
PW Assy, (TB1) (See FiQ, 9-7)
l
-51
100657-005
·
Clamp, Cable Nylon
1
--52
107018-308
·
Standoff, Threaded
4
·
(Attaching Parts)
-
100012-306
-
100018-300
-
113221-300
·
·
Screw, Pan Hd
4
Washer, Flat
4
Washer, Lock Spring
4
- - - *---53
130422-001
·
Contactor, 3 Pole (K5. K6)
2
(Attaching Parts)
-
100012-307
·
Screw, Pan Hd
-
100018-300
·
Washer, Flat
6
-
100024-300
-
Washer, Lock
6
-
100008-300
·
Nut, Hex Mach
6
Rece~sed
6
---*---54
106994
·
·
Reloy, DC (K3, K4, K7, K8)
(Continued)
9-34
4
XDS901565
Table 9-6. Motor Control Unit Assembly (Cont.)
fig- &
Index No.
9-6 -55
XDS
Part Number
106843
Vendor
Description
Part Number 1 2 3 456 7
·
Socket, Relay
Mfg.
Code
Units Per Usable on
Assy
Code
4
(Attaching Parts)
-
100012-207
-
100018-200
·
-
113221-200
-
100008-200
·
·
Screw, Pan Hd
4
·
Washer, rlat
4
·
·
Washer, lock Spri ny
4
Nut, Hex Mach
4
~
---*---56
146260
· .
Bracket, Relay Mtg
1
(Attaching Parts)
·
Screw, Pan Hd
2
100010-400
·
Washer, Flat
2
-
113221-400
·
Washer, lock Spiing
2
-
100008-400
·
Nut, Hex Mach
2
-
100012-407
-
130132
·
Relay, DPDT lOA (K1, K2, K9)
3
10a012-306
-
100018-300
-
11 ,)221- 300
·
·
Screw I Pan Hd
9
Washer, Flat
9
Washer, lock Spring
9
·
-58
110996-471
·
Resistor, Fi 1m 1W (R56)
1
-59
132179
·
Bracket, Relay Mtg
1
-
100018-300
-
113221-300
·
·
II
I
I
I
.
II
I
(Attaching Parts)
100012-306
I
I
---*---
-
j
I
(Attaching Parts)
-
I
I
---*---57
I
Screw, Pan Hd
4
Washer, Flat
4
Washer, lock Spring
4
I
--- *--(Continued)
9-35
XDS 901565
Table 9-6. Motor Control Unit Assembly (Cont.)
Fig. &
Index No.
9-6 -60
XDS
Part Number
130765
Vendor
Description
Part Number 1 2 3 456 7
I·
.
Relay, 4 Form C 24VDC (K10)
Mfg.
Code
Units Per Usable on
Assy
Code
1
(Attaching Parts)
[
-
100012-407
-
100018-400
...
113221-400
I·
.
·
·
Screw, Pan Hd
1
Washer, Flat
1
Washer, Lock Spring
1
---*---61
129681
.-62
129682
-63
132570-001
· ·
· ·
· · ·
Relay, Time De lay (K 15)
1
Socket, Time Delay
1
Terminar, Ins Ring Tongu'3
2
(Attaching Parts)
l
-
100012-314
·
Screw, Pan Hd Recessed
2
-
100018-300
· ·
Washer, Flat
2
100024-300
·
Washer, Lock
2
100008-300
·
Nut, Hex Mach
2
----*---64
101155-150
·
·
Resistor, Fixed WN (Ri)
1
(A ttach i ng Po rts)
1.-
100012-210
·
Screw, Pan Hd
2
-
100018-200
Washer, Flat
2
-
113221-200
Washer, Lock Spring
2
-
100008-200
· ·
· ·
· ·
Nut, Hex Mach
2
---*---65
108474
·
Capacitor, IN Electrolytic (C1)
~
•
9-36
(Continued)
1
XD~
Table 9-6.
Fig. &
Index No.
XDS
Port Number
9-6 -66
126945-002
901565
Motor Control Unit Assembly (Cant.)
Vendor
Port Number 1 2 3 456
Description
7
Brocket, Capoc:tor Mtg
Mfg.
Code
Units Per Usable on
Assy
Code
1
(Attaching Ports)
-
100012-306
-
100018-300
-
113221-300
-
100008-300
·
·
I
I
Screw, Pan Hd
3
Washer, r-tat
4
Washer, Lock Spring
2
Nut, Hex Mach
3
---*---67
100992-003
-68
107132-005
-68
107132-006
.
I
Capacitor, DV Oil/Paper (C3, C4)
2
Spacer, Round LH
2
Spacer, Round RH
2
I
(Attaching Ports)
-
100012-320
-
113220-300
-
1i 3221-300
I
t
II
·
II
100992-006
-
100012-306
-
113220-300
-
113221-300
2
Washer, riot
2
Washer, Lock Spring
2
I
- - - * - - -
I
-69
Screw, Pan Hd
I
Capacitor, DV On/Paper (C5)
1
II
Screw, Pan Hd
2
I
Washer, Flat
2
Washer, Lock Spring
2
(Attaching Ports)
I
---*---70
Brocket, Capacit0r Mtg
132177
1
(Attachi n9 Ports)
-
100012-306
-
100018-300
-
113221-300
.
·
Screw, Pan Hd
4
Washer, Flat
4
Washer, Lock Spring
4
---*--(Continued)
9-37
XDS 901565
Table 9-6. Mol-or Control Unit Assembly (Cont.)
Fig. &
Index No.
9-6 -71
XDS
Part Number
100992-003
Vendor
Part Number
, 2 456 Description
I
3
7
·
Capacitor, DV Oil/Paper (C6,7, 8)
Mfg.
Code
Units Per Usable on
Assy
Code
3
(Attaching Parts)
-
100012-306
·
Screw, Pan Hd
6
-
113220-300
·
Washer, Flat
6
-
113221-300
·
Washer, Lock Spring
6
---*---72
132369
Transformer (T 1)
·
1
(Attaching Parts)
-
-
100012-508
·
Screw, Pan Hd
4
-
100018-500
·
Washer, Flat
4
-
113221-500
Washer, lock Spring
4
-
100008-500
Nut, Hex Mach
4
!
·
.. --* ---73
132492
Transformer (T 2)
·
1
100012--306
-
100018-300
-
113221-300
·
·
·
136179
-75
130191-001
-76
132570-001
·
·
·
100012-306
-
113221-300
-
100008-300
100018-300
·
·
·
·
·
Washer, Flat
4
Washer, Lock Spring
4
I
AIR
I
I
Cable, 4 ConductN (Grn Wire)
·
I
I
4
Connector, Cable Grip
2
Terminal, Ins Ring Te;ngue
1
Screw, Pan Hd
1
Washer, Flat
1
Washer, Lock Spring
1
Nut, Hex Mach
1
-- - *- - (Continued)
9-38
I
Screw, Pan Hd
(Attaching Parts)
-
,I
I
---*----74
II
I
(Attaching Parts)
-
II
I
XDS 901565
Table 9-6. Motor Control Unit Assembly (Cont.)
Fig. &
Index No.
XDS
Port Number
9-6 -77
136560-002
~78
101625-003
Vendor
Description
Port Number 1 2 3 .4 5 6 7
Mfg.
Code.
Connector, 14 Contact-Female
..
Tubing, Spiral
Units Per Usable on
Assy
Code
1
AIR
---*---
I
I
I
I
~
I
I
I
I
II
I
I
I
I
I
II
I
I
I
II
I
I
I
I
II
I
I
,
I
I
I
I
I
II
I
9-39
XDS 901565
901565A. 907
Figure 9-7. Printed Wiring Board (TB 1)
9-40
XDS 901565
Table 9-7.
Fig. &
Index No.
XDS
Part Number
Printed Wiring Boord TBI
Vendor
Description
Part Number 1 2 3 456 7
·
·
·
9-7 -
132343
-
132344
-
100698
· ·
-
102055
·
-
103242
-
124298
··
·
-
100323
·
-
100025
· ·
-
111516
·
-
132494
·
-
101154
-
123300-475
-
123300-126
-
11 0996-10~
-
110996-622
-
110996-473
-
110996-273
-
130109-097
-
110996-183
-
123363-164
Mfg.
Code
PW Motor Control Uni t (T Bl)
Units Per Usable on
Assy
Code
1
1
Board, PW
Transistor XDS 231, (Ql,5)
2
Transistor XDS 210, (Q2, 3,6,7,
8,10, 11)
7
Transistor X0$ 214, (Q4)
1
Transistor XDS 216, (Q9)
1
·
Pad, Transistor (01 thru 8, 10,
11)
10
·
Diode XDS 106 (VR1,2,5 thru 9)
7
Diode XDS 101, (VR3,4)
2
Diode X DS 123, (CR14)
1
Diode XDS 135, (CR23, 24, 25)
3
DiodeXDS 113, (CRI thru 13,
16, 17)(CJ{19 thru 22,26,27)
21
·
Capacitof, Tantalum (C9 thru 12)
(C 14 thru 20, C24 thru 27)
15
· ·
·
Capacito!'", Tantalum (C13, 22, 23)
3
Resistor, 1W (R2)
1
110996-152
·
Resistor, lW (R3)
1
110996-20~
· ·
·
Resistor, lW (R25, 45,50)
3
Resistor, lW (RIB, 30, 3B)
3
·
Resistor, lW (R20 thru 24)
5
·
Resistor, ~W (R32)
1
Resistor, ~'N (R33)
1
111530
110996-100
110996-105
·
·
·
---
·
~
I
·
·
· ·
·
· ·
·
·
~
.. . ·
.
~ \!1
(R46 thru 49)
4
Resistor, lW· (R39, 41,43).
3
Resistor, IW {R3n
1
Resistor, 1!8W (R37)
1
Resistor,
(Continued)
9-4·1
XDS 901565
Table 9-7. Printed Wiring Board T81 (Cont.)
Fig. &
Index No.
XDS
Part Number
9-7 -
123362-243
·
Resistor, 1/8W (R4, 5,9, 13,35,
51,10)
7
-
123362-084
·.
Resistor, 1/8W (R6,8)
2
-
123362-281
Resistor, 1/8W (R7)
1
-
123362-147
Resistor, 1/8W (R28, 40, 42, 44,
53,54)
6
-
123362-i97
Reshtor, 1/8W (R12)
1
~
-
123362-219
-
123362-176
-
123362-212
-
121362-339
-
123362-172
-
110996-101
-
123300-124
-
126297-001
Vendor
Description
Part Number 1 2 3 4 5 6 7
·
·
·
·
·
· ·
Units Per Usable on
Assy
Code
- -
· ·
·
· ·
Resistor, 1/8W (R14)
1
Resistor, 1/8W (R17, 34,11, 15,
29,52)
6
1/8w (R26, 36)
2
Resistor, 1/8W (R19, 27)
2
Resistor, 1/8W (RJ6)
1
·
Resistor, lW (P.55)
1
·
·
Capacitor, TanroilJm (C29)
1
Terminal, Sif Ri",et (El thru 45)
45
Resistor,
.
---*---
,
9-12
Mfg.
Code
XDS 901565
Figure 9 -8.
.
Pane I Assembly
Power Distribution
9-43
XDS 901565
Table 9-8. Power Distribution Panel Assembly.......
Fig. &
Index No.
Vendor
Part Number 1 2 3
Description
Mfg.
Code
456 7
Units Per Usable on
Assy·
Code
137529 E:
·
-1
137530
·
Chassis Distribution Panel
1
-2
131326
·
Cover, Distribution Panel
1
9-8 {
XDS
Part Number
Power Distribution Panel Assy
REF
(Attaching Parts)
-
100012-407
-
100018-400
-
100024-400
·
·
·
Screw, Pan Hd
14
Washe·r, Flat
14
14-
Washer, Lock
.'
---*---3
127055
·
Transformer (T1)
(Attachi ng Parts)
I
1
t
-
100012-407
·
Screw, Pan Hd
4
-
100018-400
·
Washer, Flat
4
-
100024-400
Washer, Lock Int Tooth
4
-
100008-400
·
··
Nut, Hex Mach
- - - * .- - -4
130132
-4
110996-331
·
·
· .
·
RelaYt DPDT lOA (K4)
I
4
I
I
Resistor, 330 1W (Rl)
1
1
(Attaching Parts)
-
100012-307
-
100018~·300
100024-300
··
·
·
Screw, Par. Hd
I
1
Washer, Flat
1
Washer, Lock lnt Tooth
1
---*---5
129681
·
·
Relay, Time Delay Thelma! (K5)
,
(Continued)
9-44
1
XDS 901565
Table 9-8.
Fig. &
Index No.
9-8 -5
XDS
Part Number
129682
Power Distribution Panel Assembly (Cont.)
Vendor
Part Number 1 2 3 456
·
Description
7
Mfg.
Code
Socket, Relay
Units Per Usable on
Assy
Code
1
(Attaching Ports)
-
100012-316
-
100018-300
-
100024-300
-
100008-300
·
·
·
·
.
.
Screw, Pan Hd
2
Washer, Flat
2
Washer, Lock Int Tooth
2
Nut, Hex Mach
2
---*---6
130540
-6
101154
Relay, DPDT 5A
·
2~VDC
Coil (K3)
Diode, XDS 113 {CR1)
1
1
(Attaching Pans)
-
100012-406
-
100018-400
-
100024-400
·
·
·
1
Screw, Pan Hd
1
Washer, Flat
1
Washer, Lock Int Tooth
1
130422-001
·
Contactor, 3 Pole AC (K1)
I
1
---*---i
I
I
1
I
(Attaching Parts)
-
100012-414
-
·
Screw, Pan Hd
3
100018-400
Washer, Flat
3
-
100024-400
Washer, Lock Int Tooth
3
-
100008-400
Nut, Hex Mach
3
I
--- *--
-
I
-8
109432-001
· .
Block (TB1, TB2)
22
-8
109432-005
·
Clip, Retaining
4
-8
109432-006
Mounting, Channel
2
-8
109432-008
Plate, End
2
(Continued)
9-45
XDS 901565
Table 9-8. Power Distribution Panel Assembly (Cont.)
Fig. &
Index No.
9-8 -8
XDS
Part Number
109432-012
Vendor
Part Number
r
Description
2 3 4 5 6 7
·
Jumper, Terminal
Mfg.
Code
Units Per Usable on
Assy
Code
4
(Attaching Parts)
!
-
100012-407
·
-
100018-400
-
100024-400
·
·
-
100008-400
-9
.
Screw, Pan Hd
4
Washer, Flat
4
Washer, Lock Int Tooth
4
·
Nut, -Hex Mach
4
100653-006
·
FUse, .250 AMP 3AG (n)
1
-10
100331
Holder, Fuse
1
-11
130462
· .
·
Switch, T.:>ggle DPDT (S 1)
1
-12
101430
·
Receptacle, Female 3 Contact (J2 thru
J8)
7
-13
127675
·
Receptacle, Male 3 Coraicct (Jl)
1
.
(Attaching Parts)
-
100012-307
-
100018-300
-
100024-300
·
-
100008-300
·
·
·
-'
Screw, Pan Hd
16
Washer, flat
16
Washer, LockInt Tooth
16
Nut, Hex Machine
i6
---*--.-14
109350-021
·
Plug, Snap In
1
-15
130191-002
Clamp, Cable
2
-16
100657-001
·
·
·
Clamp, Cable
1
Clamp, Cable
1
...l
-17
100657-005
(Attaching Parts)
-
100012-307
-
100018-300
-
100008-300
100024-300
· .
·
Screw, Pan Hd
2
Washer, Flat
2
·
Washer, Lock Int. Tooi-h
2
·
Nut, Hex Mach
2
- -- *- - (Continued)
9-46
XDS 901565
Table 9-8.
Fig. &
Index No.
XDS
Part Number
9-8 -18
100720-004
·-19
100720-007
-
132570-004
-
132570-001
·
Vendor
Part Number
Power Distribution Panel Assembly (Cont.)
Description
1 2 3 456 7
·
·
Mfg.
Code
Units Per Usable on
Assy
Code
Grommet, Rubber
1
Grommet, Rubber
1
· .
Terminal, Ins Ring Tongue
4
.
Terminal, Ins Ring Tongue
49
---*---
I
f
]
I
I
I
I
I
I
I
I
I
9-47
XDS 901565
90IS~A9~ I
Figure 9-9.
9-48
Extended Performance RAD Controller
XDS 901565
Table 9-9. Extended Performance RAD Controller
Fig. &
Index No.
XDS
Port Number
9-9 -
149330 0
RAD Controller Assy (7231)
-1
131958
-2
131960
-2
131959
·
·
·
Vendor
Part Number 1 2 3 456
Description
7
Mfg.
Code
Units Per Usable on
Assy
Code
REF
Door, Chassis
2
Hinge, Chassis Door LH
1
Hinge, Chassis Door RH
1
(Attaching Parts)
-
100012-204
-
100018-200
-
100024-200
·
·
·
Screw, Pan Hd
8
Washer, Flat
8
Washer, Lock Int Tooth
8
---*~--
-3
·
129940
Bracket, Door Latch fvhg
1
(Attaching Parts)
-
100012-203
-
100018-200
-
100024-200
I
·
Screw, Pan Hd
3
·
Washer, Flat
3
·
Washer, Lock Int Toot!,
3
I
---*---4
·
129554
Trigger, Door Latch
2
(Attaching Parts)
-
100012-105
·
Screw, Pan Hd
2
-
100018-100
·
Washer, Flat
2
---*-P"-5
129540
I
-
100012-304
-
-
·
I,
I
Spring, Door Latch
1
(Attaching Parts)
Screw, Pan Hd
2
100018-300
Washer, Flat
2
100024-300
Washer, lock I nt Tooth
2
---*---6
116231
·
Chassis, 32 Module (See Fig. 9-10 for Module
Locations)
3
(Continued)
9-49
XDS 901565
Table 9-9. Extended Performance RAD Controller (Cont. )
Fig. &
Index No.
XDS
Part Number
9-9 -6
129567-001
Vendor
Description
Part Number 1 2 3 456 7
·
Mfg.
Code
Units Per Usable on
Assy
Code
Nut, Strip Speed
6
(Attaching Parts)
[
-
100012-405
-
100024-400
100018-400
·
·
·
Screw, Pan Hd
24
Washer, Flat
24
Washer, Lock Int Tooth
24
- - :- * - - -7
116522
·
Channel, Cable Routing
2
-8
123940-001
•. Channel, Cable Routing
1
(Attaching Parts)
~
I
-
100012-203
·
Screw, Pan Hd
15
-
100018-200
·
Washer, Flat
15
-
100024-200
·
Washer, Lock lnt Tooth
is
---*---9
117427
-10
139637
·
Fi Iter, Air Panel
Top Fan Assy
I
I
1
1
(Attaching Parts)
-
100012-304
-
100018-300
-
100024-300
·
·
·
Screw, Pan Hd
8
Washer, Flat
8
Washer, Lock Int Tooth
8
---*---11
139876 B
·
Backwi ri ng Board Assy
1
(Attaching Parts)
-
114538-214
-
100018-300
-
100024-300
·
·
·
Screw, Sheet Metal
54
Washer, Flat
54
Washer, Lock lnt Tooth
54
---*---
~
-12
145474-001
·
Panel, Side Chassis Mtg LH
il
(Continued)
9-50
1
XDS 901565
Table 9-9. Extended Performance RAD Controller (Cont.)
Fig. &
Index No.
XDS
Part Number
9-9 -12
145475-002
-13
109432-001
-13
109432-012
-13
109432-006
-13
109432-008
-13
109432-011
Vendor
Port Number 1 2 3 456
·
·
·
·
Description
. Mfg.
Code
7
Units Per Usable on
Assy
Code
Panel, Side Chassis Mtg LH
1
Block, Terminal
7
Jumper, Terminal Block
1
Channel, Mtg (3.65 LG)
1
·
End, Plate
1
·
End, Anchor
2
(Attaching Parts)
-
100012-304
-
100018~300
-
100024-300
·
·
·
Screw, Pan Hd
.-
2
Washer, Flat
2
Washer, lock Int Tooth
2
---*---14
139967
·
Bracket, Mtg Terminal Block
1
(Attaching Parts)
-
100012-410
-
100018-400
-
100024-400
·
·
Screw, Par. Hd
2
Washer, Flat
2
·
Washer, Lot;k J. nt Tooth
2
---*---15
100657-005
-15
100657-007
·
·
Clomp, Cable Nylon
1
Clomp, Cabfe Nylon
2
(Attaching Parts)
-
100012-405
·
Screw, Pan Hd
1
-
100018-400
·
Washer, Fiat
1
-
100024-400
·
Washer, Lock Int Tooth
1
I
I
---*---16
147842
·
Frame, Swing
1
(Continued)
9-51
XDS 901565
Table 9-9. Extended Performance RAD Controller (Cont.)
Fig. &
Index No.
9-9 -17
XDS
Part Number
147843
Vendor
Part Number
Description
7
1 2 3 4 5 6
·
Mfg.
Code
Units Per Usable on
Assy
Code
1
Bracket, Mtg
-
(Attach ing Parts)
-
100012-506
-
100018-500
-
100024-500
·
·
Screw, Pan Hd
4
W\lsher, Flat
4
Washer, Lock Int Tooth
4
-
-18
139592
·
-
I
---*---
Block, Shear Pin Mtg
2
(Attaching Parts)
-
100012-508
·
100018-500
Screw, Pan Hd
2
Washer, Flat
2
139593
-20
149332
·
·
II
I
---*---19
iI
-/
Block, Swing Frame Stop
2
Plate, Block Mtg
2
I
II
II
(Attachi ng Part!»
I
-
100012-507
-
100023-500
·
Screw, Pan Hd
2
·
Washer, Lock Spring
2
---*---
149219
·
2
Hinge Assy
(Attoching Parts)
-
108605-710
100023-7(:0
·
·
Screw, Cap Steel Soc Hd
4
Washer, Lock Spring
.4
---*---21
148498
-22
148499
-23
152051
-24
132268-008
·
· . .
· .
·
Bracket, Hinge
1
Bracket, Hinge Swing Frame
1
Pin, Hinge
1
Washer, Flat
2
(Continued)
9-52
I
I
II
I
i
I
XDS 901565
Table 9-9.
XDS
Fig. &
Index No.
Part Number
9-9 -25
149331
Vendor
Part Nu~ber
Extended Performance RAD Controller (Cont.)
Description
Mfg.
Code
1 2 3 4 5 6 7
·
Angle, Swing Frame Mtg
Units Per Usable on
Assy
Code
1
(Attaching Parts)
-
108605-712
· .
-
100018-700
-
10n023-700
·
·
Screw, Cap Stee I Soc Hd
4
Washer, Flat
4
Washer, Lock Spring
4
,-
I
I
II
II
II
!.
I
I
II
I
II
II
I;
I
I
I
I
9-53
XDS 901565
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
10
33
6
21
21
32 31 30 29 28 27 i6 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7
I
I
B
i
II
I'
IIII
IIII
~!II
\~
]8
25
9
23
7
11
II
II
I!
18
!I
21
'~
~\24
15
15
33
14
c
901 565A. 910
Figure 9-10. Module Location (RAD Controller)
9-54
XDS 901565
Table 9-10. Module Locations (RAD Controller)
Fig. &
Index No.
XDS
Part Number
Vendor
Part Number 1 2 3 456
Description
7
Mfg.
Code
Units Per Usable on
/l.ssy
Code
(Module Locations) RAD Controller Assy
9-10
·
·
Module Assy, AT24, Clock Driver 112
1
Module Assy, ATl 0 Cable Rec
2
123019
·
Module Assy, AT11 Cable Dr/Rec
1
-4
124629
Module Assy, AT12 Cable Driver
2
-5
126714
Module Assy, ATl7 Coble Dr/Rec
1
-6
116056
·
·
·
Module Assy, BT10 Buff AND/OR Gate
1
-7
116029
·
Module Assy, BTll BAND Gate
8
-8
116407
Module Assy, BT 13 Buff Matrix
1
-9
125262
Module Assy, BT16 Gated Buffer
1
-10
123491
-11
126611
-12
127393
·
·
·
·
·
-13
116380
9-10-1
128168
-2
123018
-3
I
I
II
J
-14
117028
-15
127319
-16
126743
-17
126856
-18
126986
-19
133251
I
Module I\'~sy,
en 0 Clock Osci lIator
'I
Module Assy, AT 16 Re iection Gate
1
Module Assy, 8T22 Fast Buffer
1
·
Module Assy, FTlO
·
·
·
Module Assy, FTl2 Gated Flip-Flop
Module Assy, DT14
~o~ic
o~ lay
Flip-Flop
Li ne
2
2
Module Assy, FT25 Fost Access Mem
1
·
·
Module Assy, FT26 Buff Latch No. 3
4
Module Assy, FT27 Buff Latch No. 2
8
·
Me-dute Assy, FT41 RegisterFF
3
I
Module Assy, HT 15 De lay/li ne Sense
1
I
·
·
Module Assy, 1T11 NAND Gate
6
I
I
4
-20
127391
-21
116994
-22
117000
·
Module Assy, 1T13 In.'erter Matrix
2
-23
117375
·
Module Assy, IT J5 Gated Inverter
2
-24
124634
·
Module Assy, FT18 Counter Flip-Flop
1
-25
125264
·
Module Assy, IT 16 Gated Inverter
1
-26
128188
·
Module Assy, IT24 NAND-NOR Gate
1
(Continued)
9-55
XDS 901565
Table 9-10. Module Locations (RAD Controller) (Cont.)
Fig. &
Index No.
XDS
Part Number
·
·
·
·
Mfg.
Code
Units Per Usable on
Assy
Code
Module Assy, LT24 logic Element
1
Modu Ie Assy, lT25 logic Element
1
Modu Ie Assy, LT26 Switch Cornp
1
Module Assy, LT41 Logic Element
1
·
·
Module Assy, LT43 Logic Element
1
Module Assy, LT58 I ncr Decr
2
116257
·
Module Assy, XTl 0 Term Module
-4
-34
117389
Module Assy, BTl5 Gated Buff No. 1
2
-35
127643
Module Assy, LT29 Clock Logic
1
-36
136547
·
·
·
Module Assy, LT71 Exclusive OR
1
9-10-27
126710
-28
126712
-29
126982
-30
133392
-31
133657
-32
134278
-33
t
Vendor
Description
Part Number 1 2 3 456 7
I
i
I
,
J
I
~
9-56
XDS 901S6S
Table 9-11.
Fig. &
Index No.
XDS
Part Number
·2-27
Numericallndex
Fig. &
Index No.
Description
XDS
Part Number
Description
100008-100
Nut, Hex Mach
100012-410
Screw, Pan Hd
100008-200
Nut, Hex Mach
100012-414
Screw, Pan Hd
100008-300
Nut, Hex Mach
100012-S00
Screw, Pan Hd
100008-400
Nut, Hex Mach
1oo012-S04
Screw, Pan Hd
100008-410
Nut, Hex
100012-505
Screw, Pan Hd
100008-S00
Nut, Hex Mach
100012-S06
Screw, Pan Hd
100008-600
Nut, Hex
100012-507
Screw, Pan Hd
100012-104
Screw, Pan Hd
100012-508
Screw, Pan Hd
100012-520
Screw, Pan Hd
\
3-
!
100012-105
Sc;ew, Pan Hd
100012-203
Scrt:#, Pan Hd
100012-610
Screw, Pan Hd
100012-204
Sr.rcw, Pan Hd
100018-100
Washer, Flat
100012-205
Scr.::w, Pan Hd
100018-200
Washer, Flat
100012·207
ISc!ew, Pan Hd
100018-300
Washer, Flat
100012-210
I Screw,
100018-310
Washer, Flat
2-23
Pan Hd
100012-304
SCiew, Pan Hd
100018-400
Washer, Flat
100012-305
Scrt:: w, Pan Hd
100018-500
Washer, Flat
100012-306
Screw: Pan Hd
100018-600
Washer, Flat
100012-307
Screw, Pan Hd
100023-SOO
Washer, Lock Spri,:;,
1100012-310
Screv:, Pan Hd
100023-600
Washer, Lock Spr;il8
100012-314
Screw, Pan Hd
100023-700
Washer, Lock Spr:ng
100012-316
Screw, Pan Hd
100024-100
Washer, Lnck Int loath
100012-320
Screw, Pan Hd
100024-200
Washer, Lock Int Tooth
100012-404
Screw, Pan Hd
100024-300
Washer, Lock I nt Tooth
loo012-40S
Screw, Pan Hd
100024-400
Washer, Lock I nt Tooth
100012-406
Screw, Pan Hd
100024-500
Washer, Lock Int Tooth
100012-407
Screw, Pan Hd
100024-600
Washer, Lock Int Tcoth
100012-408
Screw, Pan Hd
100025
Diode, XDS 101 (VR3,4)
I
I
7-8
(Continued)
9-S7
XDS 901565
TobIe 9-11.
Fig.&
Index No.
XDS
Port Number
Numerical Index (Cont.)
Description
Fig. &
Index No.
Pcmt Number
XDS
Description
100039-307
Screw, Flat Hd
2-45
100040-003
Grommet, Nylon
100039-310
Screw, Flat Hd
6-42,67,69
100992-003
Capacitor, DV Oil/Paper
(C3, 4, 6,7,8, 30,31,32)
100039-405
Screw, Flat Hd
6-75
100992-006
100039-510
Screw, Flat Hd
Capacitor, DV Oil/Paper
(C5)
3-
100039-520
Screw, Flat Hd
7-11
101154
2-
100039-609
Screw, Flat Hd
Diode, XDS113 (CR1 thru
13, 16, 17, 19 thru 22,
26,27)
2-49
100274-016
Sleeve, Plastic'
6-64
101155-150
Resistor, Fixed WW (R 1)
7-7
100323
Diode, XDS106 (VR1, 2,5
thru 9)
8-13
101430
Receptacle, Female 3
Contact (J2, 3,4,5,6.
7,8)
8-11
100331
Fuse, Holder
101441-104
Screw, Cap Hex Hd
8-10
100653-006
Fuse, .250 AMP 3AG (Fl)
101441-105
Screw, Cap Hex Hd
8-17
100657-001
Clamp, Cable
101441-407
Screw, Cap Hex Hd
10T625-003
Tubing, S!Ji rap
3-
2223-11
100657-002
I
I
I
CiampI Cable
6-78
2-36,3-13
100657-003
ClamI', Cable
6-37 / 8-19
100657-004
Clarr.?, Cable Nylon
6-51,8-18
100657-005
CIampI Cable
8-17
100657-007
Clamp! Cable Nylon
2-35
100657-008
Clamp, Nylon
3-19
3-18
100657-009
100657-011
Tranc:!stor XDS21 0 (Q2 / 3,
6,7, 8, 10, 11)
8-18
100720-004
Grommet, Rubber
5-24
100720-006
Gromrrad, Rubber
8-20
100720-007
Grommet, Rubber
6-23
100720-009
Grommet, Rubber
2-44
100840-001
Grommet, Nylon
6-36
100840-002
Grommet, Nylon
7-4
I
Transistor X DS 214 (Q4)
102055
I 102066-001
Cord, lacing
103242
Transistor XDS 216 (09)
1'06843
Socket, Relay
106994
Relay DC (K3, 4,7,8)
1:07013-308
Standoff, Threaded
6-44
107018r314
Standoff, Hex
6-43
107132'--003
Spacer, Round
6-68
107132....005
Spacer, Round lH
6-68
1W132-006
Spacer, Round RH
9-22
r0115 1-303
Screw, 'Set Socket
3-25
1:07199- 308
Roll, Pin
5-9
107199'-4;13
Roll,' Pin
6-55
(Continued)
9-58
Bort
7-5
Clamp, Cable
100698
I 101918
5-52
Clamp, Cable
7-3
2-29
6-54
Ij
6-52
I
I
I
XDS 901565
Table 9-11. Numerical Index (Cont.)
Fig.&
Index No.
XDS
Part Number
Fig. &
Index No.
Description
5-46
107199-614
Roll Pin, Cres (3/16 Die x
7/8lg)
3-30
107396
Switch, Toggle
6-{,5
108474
Capacitor, IN Electrolytic
(Cl)
XDS
Part Number
Description
7-2
111530
Transistor, XDS231 (Ql,5)
2-31
111945
Pump, Posi ti ve Pressure
6-
113220-300
Washer, Flat light Series
6-
113220-600
Washer, Flat Light Series
3-36
109159-008
Bumper, Rubber
6-
113221-200
Washer, lock Spri ng
8-15
109350-021
PlLlg, Snap In
6-
113221-300
Washer, lock Spring
3-20,2-50,
6-45
109432-001
Block, Terminal Stack Type
8-18 AWG
6-
113221-400
Washer, lock Spring
6-
113221-500
Washer, lock Spring
2-50,6-46
109432-005
~~taining
5-11
113440-206
Screw, Cap Soc Hd
6-
113526-006
Nut, Self Clinching
6-
113526-012
Nut, Self Clinching
6-40
113694
Switch, Subminiature OPT
Toggle (51)
Clip
3-20,2-50,
6-47
109432-006
Mounti ng Channe I
3-20,2-50,
6-48
109432-008
End Plate
3-20
109432-011
End Anchor
6-4 9 ,9-13
109432-012
Jumper, Terminal Block
6-25
113707-002
Swi tch, Pressure (52, 3)
7-18
110996-100
Resistor 1W (R18, 30(38)
3-40
113800-204
Screw,
7-36
11 0996-1 01
R.esistor 1W (R55)
3-37
113800-212
Screw, Shoulde; Slotted
7-·15
110996-103
R.)sistor 1W (R2)
3-
114538-214
Screw, Sheet Metal
2-48
1 t 0996-1 05
R"?sistor 1W (R20 thru 24)
7-14
115763-i03
Capacitor Myla;· (C21, 22,
23)
7-16
110996-152
Resistor 1W (R3)
10-7
116029
7-24
1 j 0996-183
Resistor 1W (R31)
Module Assy, BTl i BAND
Gate
7-17
110996-202
Resistor 1W (R25, 45,50)
iO-6
116056
Module Assy, fH10 Buff
AND/OR Gate
7-22
110996-273
Res:stor 1W (R46 thru 49)
116231
8-4
110996-331
Resistor 1W (Rl)
Chassis, 32 Modu!e (See
Fig. 9-10 For Mudule
locations)
6-58
110996-471
Resistor 1W (R56)
~ 0-33
116257
7-21
110996-473
Resistor 1W (R33)
Module A)sy,
Module
2-8
111 097
Bracket, locking
10-13
116380
Module Assy, FTl 0 Basic
Flip-Flop
5-3
111468-502
Inse rt Th read
10-8
116407
7-9
111516
Diode, XDS123 (CR14)
Module Assy I BTl3 Buff
Matrix
3-6,9-6
Should~r
Slotted
xno Term
(Continued)
9-59
XDS 901565
Table 9-11. Numerical Index (Cont.)
Fig. &
Index No.
XDS
Part Number
Description
3-8
116522
Channel, Cable Routing
2-35,6-15,
30
116701
Tubi ng, Pressure
116702-001
Connector, Elbow
6-8,6-21,27 116702-002
Connector, Elbow
6-27
Fig. &
Index No.
XDS
Part Number
7-12
123300-475
Capacitor, Tantalum (C9
thru 12)
7-27
123362-084
Resistor, 1/8W (R6,8)
7-29
123362-147
Resistor, 1/8W (R28,40,
42,44,53,54)
7-25
123362-164
Resistor, 1/BW (R37)
Description
3-26
116722-003
Spri ng, Compression
7-35
123362-172
Resistor, i/8W (R 16)
10-21
116994
Module Assy, IT11 NAND
Gate
7-32
123362-176
Resistor, 1!8W (R17, 34, 11j
15,29,52)
Module Assy, IT13
Inverted Matrix
7-30
I· 123362-197
123362-212
Resistor, 1/8W (R26,36j
123362-219
Resistor, 1/8W (R14)
10-22
117000
Resistor, 1!8W (R12)
2-32
117026-005
Mount, Shear
7-33
10-14
117028
Module Assy, FTl2 Gated
Flip-Flop
7-31
I
7-26
9-21
117136
Pivot, Hinge Swing Frame
I 123362-243
Resistor, 1/eW (R3,5, 9,
10, 13, 35, 51)
9-24
117137
Block, Hinge Swing Frame
7-28
Resistor, 1/8W (R7)
6-16
117226
Filter, Air
7-34
II
10-23
10-34
117375
117389
Module Ass)" Il15 Gated
Invertel
Module Pssy, (H15 Gated
Buffc.r No. 1
5-34
I
5-
3-10
117427
Filter, A:r
10-2
123018
Module Assy, ATlO Cable
Rec
7-6
Module Assy, ATll Cable
Dr/Rec
10-4
3-9,9-8
10-24
123300-126
Capacitor, Tantalum (C13,
28)
II
I
!I
I
cno Clock
123491
Module Assy,
Osci Ilator
123940
Channel, Cable Routing
124298
Pad, Transistor (Ql thru
8, 10, 11 REF)
I
Screw, Button Hd
7-13
Spindle & Drive Assy
"0" Ring Teflon
10-10
CapacitN, Tantalum (C29)
I 123455
1 123460-021
I
Cap, Cr:hinet Top
123300-124
Shaft, Spi ndle
Bal I Bearing
117424
7-37
123450
I
2-2
123054-104
Resistor, 1/8W (R19, 27)
I, 123456
5-31
5-51
I
123362-339
5-5
Cabi net, Basi c Structure
123019
II
I
117419
10-3
I 123362-281
I
I 124629
I
I 124634
I
Modu Ie Assy, AT12 Cuble
Driver
Modu Ie Assy, FT18
Counter FI ip-Flop
I
10-9
(Continued)
9-60
125262
Module Assy, BT16
Gated Buffer
XDS 901565
Table 9-11.
Fig. &
Index No.
XDS
Part Number
Numerical Index (Cont.)
Description
Fig. &
Index No.
XDS
Part Number
5-32
127346-001
Shim, Retaining Bearing
Description
10-25
125264
Module Assy, IT16 Gated
Inverter
5-32
127346-002
Shim, Retaining Bearing
7-38
126297-001
Terminal Bif Rivet (El thru
45)
5-32
127346-003
Shim, Retaining Bearing
126340-002
Fastener, Captive XDS
5-1
127387-001
Nut, lock
3-24
126340-010
Fastener, Captive XDS
5-2
127388
Washer, Hub Positioning
6-7
126440-012
Fastener, Captive XDS
5-3
127389
Hub, Assy
10-11
126611
Module Assy, AT16
Rejection Gate
10-20
127391
Module Assy, HT15 Delay/
line Sense
5-4
126623
Bearing, Retainer
10-· i 2
127393
Module Assy, BT22 Fast
Buffer
5-47
126624
Liner, Spindle Housing
3-44
127489-002
Connector, 50 Pir.
10-27
126710
Module Assy, LT24 Logic
Element
3-45
127614
Plate Mtg, Connedor
Plug
Module Assy, LT25 Logic
Element
10-35
127643
Module Assy, L729 Clock
log:c
Module Assy, ATl7 Cable
Dr/Rec
8-14
127675
Receptacle MCle, 3
Contact (Jl)
3-42,6-4
10-2S
10-5
126712
126714
5-3
126716
Disc, Hub
6-6
127990
Container, Filter-Charcoal
10-16
126743
Module Assy, FT25 Fast
Access Memory
5-2)
128155-001
Thermostat, Overt ~rY'p
5-35
126835-003
Woodruff, Key
5-33
128i63-002
Wusher, Spring
7-17
126856
Module Assy, FT26 Buff
Latch No.3
10-1
128168
Module Assy, AT24 Clock
Driver #2
6-66
126945-002
Bracket, Capacitor Mtg
10- 26
1:iSlB8
Module Assy, IT?4 NAND
NOR Gate
10-29
126982
Module Assy, LT26 Switch
Comp
2-9
129459
Slide, 20 Inch 175 Lb
3-4, 9-5
129540
Spring, Door Latch
3-3,9-4
129554
Trigger, Door lat,:h
3-6, 9-6
129567
Nut, Strip Speed
5-38
129633-204
Screw, Cap Soc Hd
5-1S
129633-206
Screw, Cap Soc Hd
5-30
129633-506
Screw, Cap Soc Hd
10-1S
126986
Module Assy, FT27 Buff
Latch No. 2
5-3
127054
Insert, Hub
8-3
127055
Transformer (T 1)
5-45
127056
Spi nd Ie, Housi ng Assy
10-15
127319
Module Assy, DTl4 Delay
Line
(Con ti nued)
9-61
XDS 901565
Table 9-11.
Fig. &
Index No.
XDS
Part Number
Numerical Index (Cont.)
Fig. &
Index Ne.
Description
XDS
Part Number
I
Description
5-30
129633-508
Screw, Cap Soc Hd
2-22
131362
Bracket, leg Support
2-25
129633-628
Screw, Cap Soc Hd
5-44
131530-103
Screw, Drive
6-70
129645-002
Bracket Capacitor Mtg
9-2
131950
Hinge, Chassis Door lH
6-61,8-5
129681
Relay, Time Delay Thermal
(K5, K15)
131958
Door, Chassi s
131959
Hinge, Chassis Door
6-62,8-6
129682
Socket, Time Delay
3-2,9-2
131960
Hi nge, Chassis Doer RH
129687
Baffle, Air Spi ndle &
Drive
5-42
131963
Hous i ng, Mo tor
3-1,9-1
3-2
5-43
3-7
129694
Panel, Blank
5-37
131964
Baffle, Motor Housing
6-6
129731
Fi I ter, Container Assy
5-10
131965
Cap, Motor Housi og
9-3
129940
Bracket, Door latch M tg
5-40
131977-004
Motor, EIec Th ree Phase
(Stator)
7-23
130109-097
Rcsis~orl
5-28
131977-005
Motor, Rotor
6-57,8-4
130132
Relay, DPDT lOA (K1, 2,9)
2-6
132019
Angle, Mtg Rear (Retma)
6-75,8-16
130191-001
Co nr.E:: c tor, Cable Grip
2-33
132083-001
Union, Tube Fitting
2-51,8-15
130192-002
Clamp. Condui t
6-29
132083-002
6-53, 8-8
130422-001
Cor.tactor, 3 Pole St (K5,
6, 1)
Union, Tube Fittitig (Male
Pipe to Plastic)
6-14
132084
Union, Bulkhead
8-12
130462
Switch, Toggle DPDT (Sl)
5-8
132086
Spline, Brake Drive
8-7
130540
Rela"1 DPDT 5A 24VDC
Co;1 (K3)
2-11
132088
Bracket Slide, M:'g Rear
5-4~
132103-001
Screw, Motor Housing
6-1
132175
Chassis, Motor Control
Unit
6-4
132176
Cover, Chassis Motor
Control Unit
3-5
130639
Brac~~f.,
1W (R39, 41,43)
,
Door latch Mtg
Support
6-60
130765
Re lay, 4 Form C 24VDC
(K10)
5-27
130777-001
Spacer, Rotor
5-29
131186
Cap, load Spring Retaini ng
6-70
132177
Brocket, Capacit(.!' Mtg
8-2
131326
Cover, Distribution Panel
6-35
132178
Bracket, Compone"t Mtg
2-10
131354
Bracket, Slide Mtg Front
6-59
132179
Bracket, Relay Mtg
2-20
131356
Plate, Drum Mtg
7-
132343
Printed Wiring, Motor
Control Unit (TBl)
2-23
131357
Bracket, Sh i ppi ng
7-11
132344
Board, Pri nted Wi ri ng
(Continued)
9-62
XDS 901565
Table 9-11.
Fig.&
Index No.
XDS
Part Number
Numerical Index (Cont.)
Fig. &
Index No.
Description
XDS
Part Number
Description
6-24
132359
Bracket, Solenoid Mtg
5-48
133080
Plate, Adaptor Tachometer
6-72
132369
Transformer (Tl)
2-18
133155
Plate, Counter Balance
6-73
132492
Transformer (T2)
10-19
133251
Module Assy, FT41
Register FF
7-10
132494
Diode, XDS 135 (CR23, 24,
25)
10-30
133390
Module Assy, LT41 Logic
Element
Thyristor, XDS 236 (SCRI f
SCR2, SCR3)
5-52
133559-026
Wire, Twisted Pair
10-31
133657
Module Assy, LT43 Logic
Element
10-32
134279
Module Assy, LT58 Incr
Deer
6-31
134843
Cover, Protective
6-26
134843
Cover, Protective
6-9
134844-001
Nut, Lock
9-23
134897
Pin, Hinge
6-39
132495
6-10
132514
6-32
i32528
IFi Iter, Air Charcoal
I
ITee, Tube Fitting
6-33
132529-001
ITee, Female Pipe Fitting
6-31
132532-002
IElboVl,
6-22
132534
!valve. Solenoid (K12, 13,
II
Street
14)
ITerminal, Ins Ring Tongue
3-45,6-63
132570-001
5-13
132570-002
I
134993
Regulator,
132570-004
ITerminal, Ins Ring Tongue
6-17
2-47
136179
Cable, 4 Condudor
132570-005
I
17erminal, Ins Ring Tongue
6-74
6-
10-36
136547
5-50
132593
1'3enerator, Tachometer
Modu Ie Assy, Li71
Exclusive OR
6-77
136560-002
Connector, 14 Contact
Female
5-1~
136561-001
Connector, MCJie 14 Pin
(J37)
3-41
136588
Chari, Hd Wiring
Pipe Fitting
2~39
136674
Power Supply Assy, PT20
Nipple. Pipe Fitting
2-38,8-
137529
~
.~::;;;---..."..... ·~",.. w_,~
!
I ferminal,
I-"--.-'~'-".,,,-~,.,-.~
_..
Ins Ring Tongue
,,""""~"'_''''
______'__ __
''''~
2-21
132644
, eg Support Assy
2-18
132646
Plate, Counter Ba lance
5-54
132743
Shaft, Coupling-Tachometer
6-11
132744
6-19
132749-001
6-25
132749-002
6-28,6-34
132749-005
Nipple, Pipe Fitting
6-18
133033-001
Plug, Pipe Hex Hd
6-34
133033-002
Plug, Pipe Hex Hd
6-41
133034-001
Circuit Breaker (CB1)
5-7
133079-406
Screw, Flat Hd
(asket. Fi Iter Mtg
~ipple,
I
Pr~ss .... re
I
Power Distribution, Panel
Assy
8-1
137530
Chassis, Distribution Panel
2-46
139175
Fi Iter, Power (C 1,2,3,4)
2-41
139222
Power, Fi Iter Assy
2-42
139223
Plate, Mtg
2-43
139224-002
Cover Fi Iter
(Continued)
9-63
XDS 901565
Table 9-11. Numerical Index (Cont.)
Fig~ &
Index No.
i
XDS
Part Number
Fig. &
Index No.
Description
4-1
139418
Module Assy, LT76 Read
Write
2-3
139565-002
Clip, Speed U Type
1-
139576
Extended Performance, RAD
Assy
9-18
139592
Block, Shear Pin Mtg
9-19
139593
Block, Swing Frame Stop
3-22
139634-001
Panel, Side Chassis RH
3-22
139634-002
Panel, Side Chassis LH
XDS
Part Number
139967
Brocket Mtg Terminal
Block
3-15
139968
Strip Mtg, Wire Clomp
3-16,3-43
139969
Block, Wire Clamping
139994-001
Angle Mtg, RF (Retma)
139994-002
Angle Mtg, RF (Retma)
145315-001
Angle Spacer Slide, RH
145315-002
Angle Spacer Slice, LH
9-14,3-21
2-5
2-5
,
2-19
2-19
2-7
3-23
139635
Frame Pivot, Chassis Mtg
3-34
139636
Frame Pivot, Sel Unit Mtg
3-17,9-10
139637
Top For. Assy
3-33
139686
Pin, Hinge
2-17,3-
139690
Selection Unit Assy
2-26,5-
139697
Disc Fi I~ Assy
4-6
139716
Module Assy, LT77 Data
Decode
2-7
~
139814-001
Bracket, Chassis Locki ng LH
2-12
139815-001
BrackE.·~,
139815-002
I 145412-001
I
115412-002
Brocket, Latch Adjusting
LH
Brocket, Latch Adjusting
RH
3-28
I 145418
Guide, Rod
3-27
I 145419-001
Rod, Latch
3-27
145419-002
Rod, Latch
3-29
145420-001
Block, Latch
3-29
1I 145420-002
9-12
145474-001
Panel, Side Chassis Mtg
LH
9-12
I 145474-002
Panel, Side Chassis Mrg
RH
I Block,
Latch
Slide Sel Mtg RH
Front
2-12
I
I
2-4
Description
Bracke!, Slide Sel Mtg LH
Front
3-41
145514
Cover, Connector
2-13
1139816-001
Bracket, 51 ide Sel Mtg RH
Rear
3-38
145515
Cover, Connector- Bass
Plate
2-13
139816-002
Bracket, Slide Sel Mtg LH
Rear
6-20
145646
Fitting, Adapter Bulkhead
2-15
145698
Bumper, Rubber
2-14
139858
Ang Ie SL'pport, Front
3-12
139865
Backwiring Board Assy
9-11
139876
Backwiring Board Assy
3-35
139892-001
Ang Ie Support
3-35
139892-002
Angle Support
I 145704
6-56
146260
Bracket, Relay Mtg
6-2
146484
Chassis, Fi Iter Mtg Motor
Control Unit
146485
Motor Control Unit Assy
2-37,6(Conti nued)
9-64
3-31
Panel, Switch Mtg
XDS
Table 9-11.
Fig. &
Index No.
XDS
Part Number
901565
Numerical Index (Cont.)
Fig. &
Index No.
Description
'xb's
Part Number
Description
6-3
146486
Angle Mtg LH, Motor .
Control Unit
2-
149763
RAD Storage, Unit
Cabinet Assy
6-3
146487
Angle Mtg RH, Motor
Control Unit
2-30 .
149960
Compressor, Assy
5-22
152008
Plug, Screw
2-40
146488-001
Angle, Chassis Mtg RH
3-·46
152429-001
Screw, Captive
2-40
146488-002
Angle, Chassis Mtg LH
3-47
152429-002
Retainer, Inseri Screw
2-34
146649
Bracke t, Component Mtg
3-14
152673
Ground Strap Assy
3-39
146673
Hanger
6-13
158947
Abso!u'te Filter U~it Assy
3-32
147024
Rod Hanger, Interface
6-5
147044-001
Label, Fi Iter
6-12
147044-002
label, Fi Iter
5-6
147222-001
Broke, Magneti c
4-5
147791
J\A.odule Assy, A115 Clock
Discr
9-16
147842
F~me,
9-17
147843
Bracket, Mtg
2-16
147912-001
Blacket, Frame Mtg RH
2-16
147912-002
Bracket, Frame .Mtg LH
2-24
147931.,.006
~~0unt,
5-
148433
SI.i!khead Unit-Disc Fi Ie
Assy
2-52,9-
149330
li:31 RAD Controller Assy
9-25
149331
Angle Swing Frame Mtg
9-20
149332
Plate, Block Mtg
5-23
149578-001
Brush, Metal Graphite
5-20
149579-001
Cartridge, Brush Holder
5-21
J49580
Bracket, Cartridge
5-17
149581
C lamp, Cartridge
6-38
149710
Cover, Protective
I
II
Swing
I
Shock
I
9-65/9-66
,..., ..
I
PDQ NO.
PUBliCATION
70-Q)~4_ _ _ __
PUBLICATlON NO. ___ XDS 90i56;5A-l
I
I!i
I
DATE
22 July 1970
DATA
I
,.
1
Page _ _ Oi
QUICK
TO: ALL HOLDERS OF XDS
2
----:=-_
II
.
Extended Performance RAD Fi Ie, Mode Is 7231/7232
SUBjECT: TEMPORARY CHANGES TO TECHNICAL MANUAL
The following changes to Technical Manual ~015?_5A-l .
are necessary to i'eflect the latest
technical inform~tion. The changes ore released in ~:1is manner for purposes of expediF..lcy.
The next schedu'ed revision to the manual will incoq~orate these changes formally.
PURPOSE:
To add a monthly check of the tachometer output voltage to the mainteno,',ce
section.
INSTRUCTION S:
1.
Make fhe following changes in the technical manual with pen and ink!
o.
Page 8-22, paragraph 8-33. Betweer, ~ast line of pc,ugraph 8-33 cnd paragraph 8-31, writ~ in:
u8-·33A TACHOt·AETER OUTPUT VOL TAGE TEST
PROGRA"'~
(:ee insert ,),
att(1ched page 8~22A) ".
2.
Insert pages of this PDQ into t:ie technicc! manual as follows:
o.
Pog~ 1 of this PDQ between
b.
Page 2 of this PDQ (marked page 8-22/\) between pcges 8-22 find 8-23.
cover and title page of the technical manual.
Do not remove these pages until the above chariges hove been incorpcrated in a r,:·-
leased revision or re-issue of the technical manual.
~rtt- 4 -_.----
.APPROVED:_4i1f'~~~_,~~~_. ________ ..
___ ... ____,_
M'At'-~A('.;FR_ PUBLICATJe)NS DEVELOPtv'iE~'~T
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